1987_Rockwell_Controller_Products_Databook 1987 Rockwell Controller Products Databook
User Manual: 1987_Rockwell_Controller_Products_Databook
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1987
CONTROLLER PRODUC IS
DATA BOOK
Rockwell International
Semiconductor Products Division
©Rockwell International Corporation 1987
All Rights reserved
Printed in U.S.A.
Order No.3
July 1987
..,:.
.~
Rockwell Semiconductor Products Division is headquartered in Newport Beach, California with Field Sales Offices located
throughout the United States, Canada, Europe and the Far East. Their listings, plus those of domestic and international representatives and distributors, appear in Appendix A.
DEFINITION OF DOCUMENT TYPES
Document Type
Definition
Product Status
Product Preview
Formative or
Development
The document type contains the general features and/or specifications for a product
in definition or development. The features and/or specifications may change in any
manner without notice.
Product Summary
Development or
Production
This document type contains the general features and/or specifications of a product
in development or in production. Additional information is usually available in a separate document, not contained in this book, such as a Designer's Guide.
Data Sheet
(Preliminary)
Sampling or
Pre-Production
This document type contains preliminary or design-to-characteristic data for a product
in pre-production. Additional and/or refined characteristic data will be released in
subsequent revisions to the document.
Data Sheet
Production
This document type contains final specification information resulting from measured
characteristics. This document type is subject to revision if characteristics are further
refined during production.
Product Description
Production
This document type contains final specification information resulting from measured
characteristics along with additional application aid information. This document type
is subject to revision if characteristics are further refined during production.
Application Note
Development or
Production
This document type contains application aids in the use of the subject product. Schematics included in an application note are intended to convey system design concept
only.
NOTICE
Information furnished by Rockwell International Corporation is believed to be accurate and reliable. However, no responsibility is assumed by
Rockwell International for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of Rockwell International other than for circuitry embodied in a Rockwell
product. Rockwell International reserves the right to change circuitry at any time without notice. All document in this book are subject to
change without notice.
TABLE OF CONTENTS
Part No.fData Book Page Index ................................
iv
Controller Products - Providing Solutions for Your
VLSI Requirements ...................................................
v
Product Index ...........................................................
vii
4
CMOS 8-Bit Microprocessors & Peripherals ......
1-1
Product Family Overview .....................................
1-2
R65C02, R65Cl02 and R65Cl12
Microprocessors (CPU) ....................................
1-3
R65C21 Peripheral Interface Adapter (PIA) .......... 1-19
R65C22 Versatile Interface Adapter (VIA) ............. 1-31
R65NC22 Versatile Interface Adapter (VIA) .......... 1-53
R65C24 Peripheral Interface AdapterlTimer
(PlAT) ..............................................................
1-75
R65C51 Asynchronous Communications Interface
Adapter (ACIA) ................................................. 1-95
R65C52 Dual Asynchronous Communications
Interface Adapter (DACIA) ................................ 1-116
2
3
5
NMOS 8-Bit Microprocessors & Peripherals ......
2-1
Product Family Overview .....................................
2-2
R650X and R651X Microprocessors (CPU) ...........
2-3
R6520 Peripheral Interface Adapter (PIA) ............. 2-18
R6522 Versatile Interface Adapter (VIA) ............... 2-30
R6532 RAM-I/O-Timer (RIOT) .............................. 2-52
R6545/R6545E CRT Controller (CRTC) ................ 2-62
R6549 Color Video Display Generator (CVDG) ..... 2-81
R6551 Asynchronous Communications Interface
Adapter (ACIA) ................................................. 2-112
8-Bit Microcomputers ........................................
Product Family Overview .....................................
R65Cl0 One-Chip Microcomputer .......................
R6500/1 One-Chip Microcomputer .......................
R6500/1E Microprocessor Emulator Device .........
R6500/1 EB Backpack Emulator ...........................
R6500/11, /12 and /15 One-Chip Microcomputers
R65/11 EB Backpack Emulators ...........................
6
3-1
3-2
3-3
3-26
3-49
3-57
3-63
3-98
A
iii
R6501 One-Chip Microp~ocessor .........................
R6511 Q One-Chip Microprocessor and R6500/13
One-Chip Microcomputer .................................
R6518 One-Chip Microprocessor .........................
R65Fll and R65F12 FORTH Based
Microcomputers ...............................................
R65FRx FORTH Development and Kernel ROMs ..
3-103
16-Bit Microprocessors and Peripherals ...........
Product Family Overview .....................................
R68000 16-bit Microprocessing Unit (MPU) ..........
R68C552 Dual Asynchronous Communications
Interface Adapter (DACIA) ................................
R68560 Multi-Protocol Communications Controller
(MPCC) ............................................................
4-1
4-2
4-3
Intelligent Display Controllers ...........................
Product Family Overview .....................................
10937 and 10957 Alphanumeric Display
Controller .........................................................
10938 and 10939 Dot Matrix Display Controller ....
10939,10942 and 10943 Dot Matrix Display
Controller .................................. :, .....................
10941 and 10939 Alphanumeric and Bargraph
Display Controller .............................................
10951 Bargraph and Numeric Display Controller ..
10955 Segmented Display Controller/Driver .........
3-138
3-173
3-203
3-235
4-62
4-83
5-1
5-2
5-3
5-11
5-21
5-31
5-41
5-51
Application Notes ..............................................
Low-Cost Crystal Oscillator for Clock Input ...........
R6500/R6532 Timer Interrupt Precautions ...........
A Dot Matrix Controller System Design Using
10938/10939 Display Drivers and R6500/1 EB
Microcomputer .................................................
Intelligent Display Controller Designer's Notes .....
6-1
6-3
6-4
6-6
6-22
SPO Regional Offices and U.S./Canada
Sales Reps ......................................................
SPD Industrial Distributors ...................................
SPD International Distributors/Sales Reps ...........
Notes ..................................................................
A-l
A-3
A-6
A-7
PART NO.lDATA BOOK PAGE INDEX
Part No.lDescrlption
Page
Part No./Descrlption
10937 and 10957 Alphanumeric Display Controller ... .
10938 and 10939 Dot Matrix Display Controller ......... .
10939,10942 and 10943 Dot Matrix Display
Controller .............................................................. ..
10941 and 10939 Alphanumeric and Bargraph
Display Controller .................................................. .
10951 Bargraph and Numeric Display Controller ...... ..
10955 Segmented Display Controller/Driver ............. ..
R65/l1 EB Backpack Emulators ................................. .
R6500/1 One·Chip Microcomputer ............................ .
R6500111, 112 and /15 One·Chip Microcomputer ...... .
R6500/1E Microprocessor Emulator Device ............... .
R6500/1EB Backpack Emulator ............................... ..
R6501 One·Chip Microprocessor ............................... .
R650X Microprocessors (CPU) .................................. .
R6511Q One·Chip Microprocessor and
R6500113 One·Chip Microcomputer ...................... ..
R6518 One·Chip Microprocessor ............................... .
R6520 Peripheral Interface Adapter (PIA) ................. ..
R6522 Versatile Interface Adapter (VIA) .................... ..
R6532 RAM·I/O·Timer (RIOT) ................................... ..
I 5·3
'5·11
R6545 CRT Controller (CRTC) ....................................
R6549 Color Video Display Generator (CVDG) ............
R6551 Asynchronous Communications
Interface Adapter (ACIA) .........................................
R65C02 Microprocessors (CPU) .................................
R65C10 One·Chip Microcomputer ..............................
R65C21 Peripheral Interface Adapter (PIA) .................
R65C22 Versatile Interface Adapter (VIA) ...................
R65C24 Peripheral Interface AdapterlTimer (PlAT) .....
R65C51 Asynchronous Communications Interface
Adapter (ACIA) ........................................................
R65C52 Dual Asynchronous Communications Interface
Adapter (DACIA) .....................................................
R65F11 and R65F12 FORTH Based Microcomputers.
R65FRx FORTH Development and Kernel ROMs .......
R65NC22 Versatile Interface Adapter (VIA) .................
R68000 16·bit Microprocessing Unit (MPU) .................
R68560 Multi·Protocol Communications Controller
(MPCC) ...................................................................
R68C552 Dual Asynchronous Communications
Interface Adapter (DACIA) .......................................
5·21
5·31
5-41
5·51
3·98
3·26
3·63
3·49
3·57
3·103
2·3
3·138
3·173
2·18
2·30
2·52
iv
Page
2·62
2·81
2·112
1·3
3·3
1-19
1·31
1·75
1·95
1·116
3·203
3·235
1·53
4·3
4·83
4·62
CONTROLLER PRODUCTS
Providing Solutions for Your VLSI Requirements
These products are produced in high volume at a modern
state-of-the-art facility located in Newport Beach, California,
and are packaged in a newly constructed, fully automated
manufacturing facility in Mexicali, Mexico. The class 10,000
clean room environment produces devices to the most stringent industry standards. Rockwell has the organization, systems and support to manufacture products to existing and
future quality levels.
In fact, Rockwell is the first and only semiconductor company to offer a 5 year warranty. You can rely on customer
satisfaction and service when choosing a Rockwell semiconductor product.
Rockwell International designs and manufactures a family
of VLSI products to serve your system requirements. As
shown in the diagram below, compatible controller products
are available for a wide range of 16-bit and 8-bit applications.
Peripheral devices operate on either the 68000 or the 6500
microprocessor bus structure. Many of the peripheral devices
are now being used on additional bus structures such as
8085, 80286 and Z80, just to name a few.
The product line utilizing the R6502 processor, recognized
world-wide for its high performance, was recently improved by
redesigning it in a CMOS process. Enhancements include a
200% improvement in speed and a 20 times reduction in
power dissipation.
8BIT
16BIT
SLAVE
PROCESSOR
RAM/ROM
'---___ • COMBO DEVICES
Serving System Requirements
v
PRODUCT INDEX
CMOS 8-Bit Microprocessors & Peripherals
NMOS 8-Bit Microprocessors & Peripherals
8-Bit Microcomputers
16-8il Microprocessors and Peripherals
Intelligent Display Controllers
Application Notes
vii
o
Section 1
CMOS 8-Bit Microprocessors & Peripherals
Page
Product Family Overview ................................................. .
1-2
R65C02, R65C102 and R65C112 Microprocessors (CPU) ....................... .
1-3
R65C21 Peripheral Interface Adapter (PIA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1-19
R65C22 Versatile Interface Adapter (VIA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1-31
R65NC22 Versatile Interface Adapter (VIA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1-53
R65C24 Peripheral Interface Adapter/Timer (PlAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1-75
R65C51 Asynchronous Communications Interface Adapter (ACIA) . . . . . . . . . . . . . . . ..
1-95
R65C52 Dual Asynchronous Communications Interface Adapter (DACIA) ........... 1-116
1-1
CMOS 8-bit Microprocessors & Peripherals
Fastest Executing - Low Power
There is no CMOS microprocessor family easier to imple·
ment than the R65CXX. It is the fastest instruction executing
8·bit family available. It's software compatible with a family of
single·chip microcomputers and has three powerful CPUs and
peripherals for parallel and serial 110.
In the 8·bit range, nothing gives faster instruction execution
(500 I's) with most parts available in 1, 2, 3 and 4 MHz ver·
sions. Thirteen address modes provide the most efficient
ways of addressing memory. R65CXX peripherals are system
oriented, designed to implement systems with minimum
device count.
Because of its inherent characteristics, advanced Rockwell
CMOS provides low power consumption, high noise immunity
and high speed operation. Its 2 MHz CPU dissipates only
40 mW (compared to 800 mW in NMOS) and requires only
10 mA standby current. Instruction memory requirements are
20% less due to added bit manipulation features.
The entire 8·bit R65CXX family is upward compatible with
the l6·bit 68000 bus, software compatible with Rockwell's
8·bit microcomputers, and are the building blocks for a wide
range of system applications. It's one of the world's highest
performing and lowest cost microprocessors.
GENERAL PURPOSE
I/O DEVICES
R65C51
R65C52
CMOS R65CXX Microprocessor Family
1·2
R65C02 • R65C102 • R65C112
'1'
R65C02, R65C102 and R65C112
R65COO Microprocessors (CPU)
Rockwell
DESCRIPTION
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
CMOS silicon gate technology
Low Power (4 mA/MHz)
Software compatible with R6502
Single 5V ± 5% power supply requirements
Eight-bit parallel processing
Decimal and binary arithmetic
True indexing capability
Programmable stack pointer
Interrupt capability
Non-maskable interrupt
Eight-bit bidirectional data bus
Memory address range of up to 64K bytes
"Ready" input
Direct memory access (DMA) capability
Memory lock output
1 MHz, 2 MHz, 3 MHz, and 4 MHz versions
Choice of external or on-chip clocks
On-chip clock options
-E;xternal single clock input
-Direct crystal input ( .;. 4)
• Commercial and industrial temperature versions
• Pipeline architecture
• Slave processor version (R65C112)
The 8-bit R65COO microprocessor family of devices are produced
using CMOS silicon gate technology which provides advanced system architecture for performance speed and system costeffectiveness enhancements over their NMOS counterparts, the
R6500 family of microprocessor devices.
Three CPU devices are available. All are software-compatible and
provide 64K bytes of memory addressing, two interrupt inputs, and
on-chip clock oscillators and/or drivers. All are bus-compatible with
the NMOS R6500 family devices.
The CMOS family includes two microprocessors (R65C02 and
R65C102) with on-board clock oscillators and drivers and one
microprocessor (R65C112) driven by an extemal clock. The on-chip
clock versions are aimed at high performance, low-cost applications
where single phase inputs, crystal or RC inputs provide the time
base. The slave processor version is geared for multiprocessor system applications where maximum timing control is mandatory. All
R65COO microprocessors are available in ceramic and plastic packaging, operating frequencyof 1 MHz, 2 MHz, 3 MHz and 4 MHz, and
commercial and industrial temperature versions. All three devices
are available in 40-pin DIP or 44-pin PLCC packages.
ORDERING INFORMATION
Part Number:
R65C02
R65C102
R65C112
MAJOR FEATURES AND DIFFERENCES
Feature
Pin compatible with NMOS R6502
64K addressable bytes of memory
IRQ interrupt
On-chip clock oscillator
External clock only
TTL level Single phase clock input
RC time base clock input
Crystal time base clock input
Single phase clock input
Two phase output clock
SYNC and ROY signals
Bus Enable (BE) signal
Memory Lock (ML) output signal
Direct Memory Access (DMA) capacity
NMI interrupt signal
Document No_ 29651 N52
R65C02 R65C102 R65C112
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
lLT-p-~,mT"
Blank =
ODC to + 70 DC
E = -40°Cto +85°C
M = -55°Cto 125DC
Frequency Range
1 = 1 MHz
2 = 2MHz
3 = 3MHz
4 = 4MHz
'-----Package
C = 40-Pin Ceramic DIP
P = 40-Pin Plastic DIP
J = 44-Pin Plastic Leaded Chip
Carrier (PLCC)
X
X
X
X
X
X
X
Product Description
1-3
Order No. 2149
Rev. 6, June 1987
D
R65C02, R65C102, R65C112
R65COO Microprocessors (CPU)
INTERFACE SIGNALS
therefore not related to, or controlled by the CPU internal clock
signals. Figure 5 shows timing relationships of BE to Rm and
address output buffers.
Figure 1 shows the pin assignments for the members of th~
R65COO CPU family. All devices are housed in 40-pin ceramic
or plastic dual-in-line (DIP) or 44-pin plastic leaded chip carrier
(PLCC) packages.
INTERRUPT REQUEST (IRQ)
This TTL compatible input requests that an interrupt sequence
begin within the microprocessor. IRO is sampled at the falling
edge of Ql2 prior to the last cycle of the instruction; if the interrupt flag in the processor status register is zero, the current
instruction is completed and the interrupt sequence begins during I'll. The program counter and processor status register are
stored in the stack. The microprocessor will then set the interrupt mask flag high so that no further IROs may occur. At the
end of this cycle, the program counter low byte will be loaded
from address FFFE, and program counter high byte from location FFFF, thus transferring program control to the memory
vector located at these addresses. The RDY signal must be in
the high state for any interrupt to be recognized. A 3K ohm
external resistor should be used for proper wire OR operation.
Refer to the timing diagrams (Figures 3, 4, and 5) for the particular device in the following discussion.
CLOCK SIGNALS (R65C02)
The R65C02 requires an external QlO clock. See Figure 6 for an
example clock circuit. 00 is a TTL level input that is used to
generate the internal clocks of the R65C02. Two full level output clocks are generated by the R65C02. The Ql2 clock is in
phase with 00. The I'll clock output is 180· out of phase with
QlO. When the input clock is stopped, the CPU is in the standby
mode. See Figure 8 for special standby mode considerations.
For non-critical timing configurations, a simple RC or crystal network may be strapped between Qlo (IN) and I'll (OUT).
MEMORY LOCK (ML)
CLOCK SIGNALS (R65C102)
In a multiprocessor system, the ML output indicates the need
to defer the rearbitration of the next bus cycle to ensure the
integrity of read-modify-write instructions. ML goes low during
ASL, DEC, INC, LSR, ROL, ROR, RMB, 5MB, TRB, TSB
memory referencing instructions. This signal is low for the modify
and write cycles.
The R65Cl02 internal clocks may be generated by a TTL level
single phase input, an RC time base input, or a crystal time base
input ( .;. 4) using the XTLO and XTU input pins. See Figure 7
for an example of a crystal time base circuit. Two full level output clocks are generated by the R65Cl02. The Ql2 clock output
provides timing for external Rm operations. Addresses are
valid after the address delay time (tAOS) referenced to the failing edge of 02 (OUn. The Ql4 output is a quadrature output clock
that is delayed from the falling edge of the Ql2 clock by delay
time tAVS' Using the Ql4 clock, addresses are valid at the rising
edge of 04.
NON-MASKABLE INTERRUPT (NMI)
A negative-going edge on this input requests that a nonmaskable interrupt sequence be generated within the
microprocessor. The NMI is sampled during Ql2; the current
instruction is completed and the interrupt sequence begins
during I'll. The program counter is loaded with the interrupt
vector from locations FFFA (low byte) and FFFB (high byte),
thereby transferring program control to the non-maskable interrupt routine.
CLOCK SIGNALS (R65C112)
All internal clock signals for the R65C112 are generated by the
input clock signal 02 (IN). Since this device is intended to be
operated in the slave mode it does not have internal clock generation, but rather requires the external clock Ql2 (IN) from a host
device. Figure 7 shows an example of a clock circuit for the
R65C112 configured for slave mode.
NOTE
Since this interrupt is non-maskable, another NMI can
occur before the first is finished. Care should be taken
when using NMI to avoid this.
ADDRESS BUS (AO-A1S)
READY (ROY)
Address lines AO-A15 form a 16-bit address bus for memory and
1/0 exchanges on the data bus. The output of each address line
is TTL compatible, capable of driving one standard TTL load
and 130 pF.
This input allows the user to single-cycle the microprocessor on
all cycles including write cycles. A negative transition to the low
state, during or coincident with 02, will halt the microprocessor
with the output address lines reflecting the current address. This
condition will remain through a subsequent Ql2 in which the RDY
signal is low. This feature allows microprocessor interfacing with
low-speed memory as well as direct memory access (DMA).
DATA BUS (00-07)
The data lines (DO-D7) constitute an 8-bit bidirectional data bus
used for data exchanges to and from the device and peripherals.
The outputs are tri-state buffers capable of driving one TTL load
and 130 pF.
READ/WRITE (R/W)
BUS ENABLE (BE)
This signal is normally in the high state indicating that the
microprocessor is reading data from memory or 110 bus. In the
low state the data bus has valid data from the microprocessor
to be stored at the addressed memory location.
This signal allows external control of the data and the address
output buffers and Rm. For normal operation, BE is high causing
the address buffers and Rm to be active and the data buffers
to be active during a write cycle. For external control, BE is held
low to disable the buffers. BE is an asynchronous signal and
A negative transition on this line sets the overflow bit (V) in the
processor status register. The signal is sampled prior to the rising
edge of Ql2 by the SO setup time (tsos).
SET OVERFLOW (SO)
1-4
R65C02, R65C102, R65C112
V,,
...
RES
02 (OUT)
ROY
01 (OUT)
IRQ
NC
NMI
AD
01
02
A2
A3
A4
A5
03
04
05
06
07
A15
At4
A13
A12
A6
A7
AS
A9
Al0
"-'-=-__-=-'
0
Z
~IUI
UlwNIOoU
-
"-
Z_otrz>a:ocnoz
0
NMI
SYNC
NC
Vee
AO
At
A2
A3
A4
AS
A6
DO
At
o
::>-
o
00 (IN)
NC
NC
R/W
Vee
i='
::>
0 - >
0c
1 r_CU
so
SYNC
A11
R65COO Microprocessors (CPU)
PIN 1
INDICATOR
10
11
12
13
14
15
16
17
39
NC
38
37
36
35
34
33
32
31
30
29
NC
RIW
DO
01
02
03
04
05
06
D7
V"
40-PIN DIP
44-PIN PLCC
8. R65C02
V"
....r-:-----;;;"""l--, RES
ROY
04 (OUT)
IRQ
XTLI
02 (OUT)
BE
NMI
SYNC
XTLO
00
01
02
03
04
05
06
07
A15
At4
A13
A12
Vee
AD
Al
A2
A3
A4
AS
A6
A7
A8
A9
Al0
Atl
o
NMI
SYNC
RIW
39
38
37
36
35
34
33
32
31
30
29
PIN 1
INDICATOR
'NC
Vee
AD
Al
A2
A3
A4
AS
A6
XTLO
NC
RIW
DO
Dl
02
D3
D4
D5
D6
D7
Vss
40-PIN DIP
44-PIN PLCC
b. R65Cl02
z
>
lUI
;I~uco
gjwulo;w
1 ~_Ztrz>a:zcnGm
RES
NC
V"
RDY
SO
·NC
IRQ
02 (IN)
ML
COu)VMN ... ;~t#:;:!i
o
BE
NMI
SYNC
NMI
SYNC
NC
NC
R/W
00
Dl
D2
D3
D4
D5
Vee
AD
Al
A2
A3
A4
AS
Vee
D6
A6
D7
A15
A14
A13
A12
A7
AS
A9
Al0
A11 ,"""","-_ _~, V"
40-PIN DIP
PIN 1
INDICATOR
AD
Al
A2
A3
A4
AS
16
A6
17
c. R65Cl12
Figure 1. Pin Assignments
1-5
44-PIN PLCC
39
38
37
36
35
34
33
32
31
30
29
NC
NC
RJ\\
DO
Dl
D2
D3
D4
D5
D6
D7
NC "" NO INTERNAL
CONNECTION
R65COO Microprocessors (CPU)
R65C02, R65C102, R65C112
RESET (RES)
program counter (PCH) is placed on the high-order 8 bits. The
counter is incremented each time an instruction or data is fetched
from program memory.
This input resets the microprocessor. Reset must be held low for
at least two clock cycles after Vee reaches operating voltage from
a power down. A positive transition on this pin will then cause an
initialization sequence to begin. Likewise, after the system has been
operating, a low on this line of at least two cycles will cease
microprocessing activity, followed by initialization after the positive
edge on RES.
INSTRUCTION REGISTER AND DECODE
Instructions fetched from memory are gated onto the internal data
bus. These instructions are latched into the instruction register, then
decoded, along with timing and interrupt signals, to generate control signals for the various registers.
When a positive edge is detected, there is an initialization sequence
lasting seven clock cycles. Then the interrupt mask flag is set, the
decimal mode is cleared, and the program counter is loaded with
the restart vector from locations FFFC (Iow,byte) and FFFD (high
byte). This is the start location for program control. This input should
be high in normal operation.
ARITHMETIC AND LOGIC UNIT (AW)
All arithmetic and logic operations take place in the AlU including
incrementing and decrementing internal registers (except the program counter). The AlU has no internal memory and is used only
to perform logical and transient numerical operations.
ACCUMULATOR
The accumulator is a general purpose 8-bit register that stores the
results of most arithmetic and logic operations, and in addition, the
accumulator usually contains one of the two data words used in
these operations.
SYNCHRONIZE (SYNC)
This output line identifies those cycles during which the microprocessor is fetching the instruction operation code (OP CODE).
The SYNC line goes high during 01 of an OP CODE fetch and stays
high for the remainder olthat cycle. If the RDY line is pulled low during the clock cycle in which SYNC went high, the processor will stop
in its current state and will remain in the state until the RDY line goes
high. In this manner, the SYNC signal can be used to control RDY
to cause single instruction execution.
INDEX REGISTERS
There are two 8-bit index registers (X and y), which may be used
to count program steps or to provide an index value to be used in
generating an effective address.
When executing an instruction which specifies indexed addressing, the CPU fetches the op code and the base address, and
modifies the address by adding the index register to it prior to performing the desired operation. Pre- or post-indexing of indirect
addresses is possible (see addressing modes).
FUNCTIONAL DESCRIPTION
Figure 2 shows the block diagram of the R65CDD CPU internal architecture for all three devices. With the exception of the crystal
oscillator, clock signals, Memory Lock (ML), and Bus Enable (BE)
signals, the internal architecture of the three members of the
R65CDD CPU of devices is identical. This block diagram supports
the following text that describes the function of each of the device's
major elements.
STACK POINTER
The stack pointer is an 8-bit register used to control the addressing of the variable-length stack on page one. The stack pointer is
automatically incremented and decremented under control of the
microprocessor to perform stack manipulations under direction of
either the program or interrupts (NMI and IRQ). The stack allows
simple implementation of nested subroutines and multiple level
interrupts. The stack pointer should be initialized before any interrupts or stack operations occur.
CRYSTAL OSCILLATOR (R65C102 Only)
The crystal oscillator, driven by a crystal across XTLO arid XTLI,
divides the crystal frequency by four to provide the basic 02 clock
signal that drives the internal clock generator.
CLOCK GENERATOR
PROCESSOR STATUS REGISTER
The 8-bit processor status register contains seven status flags.
Some of the flags are controlled by the program, others may be controlled both by the program and the CPU. The R65CDD instruction
set contains a number of conditional branch instructions which are
designed to allow testing of these flags.
The clock generator develops all internal clock signals, and (where
applicable) external clock signals, associated with the device. It is
the clock generator that drives the timing control unit and the
external timing for slave mode operations.
TIMING CONTROL
The timing control unit keeps track of the instruction cycle being
monitored. The unit is set to zero each time an instruction fetch is
executed and is advanced at the beginning of each phase one clock
pulse for as many cycles as is required to complete the instruction.
Each data transfer which takes place between the registers
depends upon decoding the contents of both the instruction register
and the timing control unit.
HARDWARE ENHANCEMENTS
The R65CDD family of CPU devices have incorporated hardware
enhancements over their NMOS counterpart, the R65D2. These
hardware enhancements are:
• The NMOS device would ignore the assertion of a Ready (RDY)
during a write operation. The CMOS family will stop the
processor during 02 clock if RDY is asserted during a write
operation.
• On the NMOS device, unused input-only pins (IRQ, NMI, RDY,
RES, and SO) must be connected to a low impedance signal to
avoid noise problems. These unused pins on the CMOS devices
are internally connected by a high impedance to Vce (approximately 25DK ohms).
PROGRAM COUNTER
The 16-bit program counter provides the addresses which step the
microprocessor through sequential instructions in a program.
Each time the microprocessor fetches an instruction from program
memory, the lower byte of the program counter (PCl) is placed on
the low-order bits of the address bus and the higher byte of the
1-6
R65C02, R65C102, R65C112
R65COO Microprocessors (CPU)
CONTROL SECTION - - - .
. . - - REGISTER SECTION
RES IRQ NMI
AO
Al
A2
I-----_~ ML(S)
1+------ RDY
A3
I-----~~
ABL
SYNC
M
1---1'" XTLO(3)
AS
A6
A7
ADDRESS
BUS
AS
A9
Al0
All
ABH
A12
A13
A14
INSTRUCTION
REGISTER
A15
L---------------------~Dl
NOTES:
(1) R65C02 ONLY
(2) R65C02, R65Cl 02 ONLY
(3) R65Cl02 ONLY
(4) R65Cl12 ONLY
(5) R65Cl02, R65Cl12 ONLY
L-----------------------.D2
~-----------------------~D3
L-------------------------~D4
...
L-------------------------~ D5
L---------------------------~D6
L-_
_____________
~~
Figure 2,
R65COO Internal Architecture
1-7
LEGEND:
DATA
BUS
11
t
8 BIT LINE
SINGLE LINE
R65C02, R65C102, R65C112
R65COO Microprocessors (CPU)
ADDRESSING MODES
RELATIVE ADDRESSING IRelative)- Relative addressing is
used only with branch instructions and establishes a destination for the conditional branch.
The R65COO CPU family has 15 address modes (two more than
the NMOS equivalent family). In the following discussion of these
addressing modes, a bracketed expression follows the title of
the mode. This expression is the term used in the Instruction
Set Op Code Matrix table (later in this product description) to
make it easier to identify the actual addressing mode used by
the instruction.
The second byte of the instruction becomes the operand which
is an "Offset" added to the contents of the lower eight bits of
the program counter when the counter is set at the next instruction. The range of the offset is -128 to + 127 bytes from the
next instruction.
ACCUMULATOR ADDRESSING [Accum)- This form of
addressing is represented with a one byte instruction, implying
an operation on the accumulator.
ZERO PAGE RELATIVE ADDRESSING [ZP REL)· - This mode
bit tests the zero page location specified for bit set/reset per the
mask and performs a conditional relative branch based on the
results of the bit test.
IMMEDIATE ADDRESSING IIMM)- In immediate addressing,
the second byte of the instruction contains the operand, with
no further memory addressing required.
INDEXED INDIRECT ADDRESSING ((IND, X)) - In indexed
indirect addressing (referred to as (Indirect, X», the second byte
of the instruction is added to the contents of the X index register,
discarding the carry. The result of this addition points to a
memory location on page zero whose contents are the low order
eight bits of the effective address. The next memory location
in page zero contains the high order eight bits of the effective
address. Both memory locations specifying the high and low
order bytes of the effective address must be in page zero.
ABSOLUTE ADDRESSING [ABS) - In absolute addressing,
the second byte of the instruction specifies the eight low order
bits of the effective address while the third byte specifies the
eight high order bits. Thus the absolute addressing mode allows
access to the entire 64K bytes of addressable memory.
ZERO PAGE ADDRESSING IZP) - The zero page instructions
allow for shorter code and execution times by fetching only the
second byte of the instruction and assuming a zero high address
byte. Careful use of the zero page can result in significant
increase in code efficiency.
INDIRECT INDEXED ADDRESSING ((IND), V) - In indirect
indexed addressing (referred to as (Indirect), y), the second byte
of the instruction points to a memory location in page zero. The
contents of this memory location are added to the contents of
the Y index register, the result being the low order eight bits
of the effective address. The carry from this addition is added
to the contents of the next page zero memory location, the result
being the high order eight bits of the effective address.
ZERO PAGE INDEXED ADDRESSING IZP, X or y] - (X, Y
indexing) - This form of addressing is used with the index
register and is referred to as "Zero Page, X" or "Zero Page, Y".
The effective address is calculated by adding the second byte
to the contents of the index register. Since this is a form of "Zero
Page" addressing, the content of the secpnd byte references
a location in page zero. Additionally, due to the "Zero Page"
addressing nature of this mode, no carry is added to the high
order eight bits of memory and crossing of page boundaries does
not occur.
ABSOLUTE INDIRECT I(ABS)) - The second byte of the
instruction contains the low order eight bits of a memory location. The high order eight bits of that memory location are contained in the third byte of the instruction. The contents of the
fully specified memory location are the low order byte of the
effective address. The next memory location contains the high
order byte of the effective address which is loaded into the sixteen bits of the program counter. (JMP (ABS) only.)
ABSOLUTE INDEXED ADDRESSING [ABS, X or V) - (X, Y
indexing) - This form of addressing is used in conjunction with
X and Y index register and is referred to as "Absolute, X" and
"Absolute, Y". The effective address is formed by adding the
contents of X or Y to the address contained in the second and
third bytes of the instruction. This mode allows the index register
to contain the index or count value and the instruction to contain the base address. This type of indexing allows any location
referencing and the index to modify fields, resulting in reduced
coding and execution time.
INDIRECT ((IND))* - The second byte of the instruction contains a zero page address serving as the indirect pointer.
ENHANCEMENTS OVER R6502
The CMOS family of microprocessor devices has been designed
with many enhancements over the R6502 NMOS device while
maintaining software compatibility. Besides the increased speed
and lower power consumption inherent in CMOS technology,
the R65COO family has the following additional characteristics.
•
•
•
•
•
INDEXED ABSOLUTE INDIRECT [(ABS, Xl)· - The contents
of the second and third instruction bytes are added to the
X-register. The sixteen-bit result is a memory address containing the effective address. (JMP (ABS, X) only).
IMPLIED ADDRESSING [Implied) - In the implied addressing
mode, the address containing the operand is implicitly stated
in the operation code of the instruction.
12 new instructions for a total of 68
59 new op codes, for a total of 210
Two new addressing modes
Seven software/operational enhancements
Two hardware enhancements
·These addressing modes are not available to the NMOS CPU
family (e.g., the R6502).
1-8
R65C02, R65C102, R65C112
R65COO Microprocessors (CPU)
INSTRUCTION SET
NMOS family, but have been assigned new addressing modes
in the CMOS CPU family.
Table 1 lists the instruction set for the CMOS CPU family in
alphabetic order according to mnemonic. Tabe 2 lists the hexadecimal codes for each of the instructions that are new to the
CMOS family and were not available in the NMOS R6502 device
family. Table 3 lists those instructions that were available on the
OPERATIONAL ENHANCEMENTS
Table 4 lists the operational enhancements that have been
added to the CMOS family of CPU devices and compares the
results with their NMOS R6502 counterpart.
Table 1. •Alphabetic Listing of the R65COO Instruction Set
Mnemonic
Function
ADC
AND
ASL
Add Memory to Accumulator with" Carry
"AND" Memory with Accumulator
Shift Left One Bit (Memory or Accumulator)
BBR
BBS
BCC
BCS
BEQ
BIT
BMI
BNE
BPL
BRA
BRK
BVC
BVS
Branch on Bit Reset
Branch on Bit Set
Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits in Memory with Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Branch Always
Force Break
Branch on Overflow Clear
Branch on Overflow Set
CLC
CLD
CLI
CLV
CMP
CPX
CPY
Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable Bit
Clear Overflow Flag
Compare Memory and Accumulator
Compare Memory and Index X
Compare Memory and Index Y
DEC
DEX
DEY
Decrement Memory by One
Decrement Index X by One
Decrement Index Y by One
(2)
EOR
"Exclusive-OR" Memory with Accumulator
(2)
INC
INX
INY
Increment Memory by One
Increment Index X by One
Increment Index Y by One
(2)
JMP
JSR
Jump to New Location
Jump to New Location Saving Return Address
(2)
LDA
LDX
LDY
LSR
Load Accumulator with Memory
Load Index X with Memory
Load Index Y with Memory
Shift One Bit Right (Memory or Accumulator)
(2)
(2)
(1)
(1)
(2)
(1)
(2)
(2)
Function
Mnemonic
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(1)
(1)
(1)
NOP
No Operation
ORA
"OR" Memory with Accumlator
PHA
PHP
PHX
PHY
PLA
PLP
PLX
PLY
Push Accumulator on Stack
Push Processor Status on Stack
Push X Register on Stack
Push Y Register on Stack
Pull Accumulator from Stack
Pull Processor Status from Stack
Pull X Register from Stack
Pull Y Register from Stack
RMB
ROL
ROR
RTI
RTS
Reset Memory Bit
Rotate One Bit Left (Memory or Accumulator)
Rotate One Bit Right (Memory or Accumulator)
Return from Interrupt
Return from Subroutine
sse
SEC
SED
SEI
5MB
STA
STX
STY
STZ
Subtract Memory from Accumulator with Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Set Memory Bit
Store Accumulator in Memory
Store Index X in Memory
Store Index Y in Memory
Store Zero
TAX
TAY
TRB
TSB
TSX
TXA
TXS
TYA
Transfer Accumulator to Index X
Transfer Accumulator to Index Y
Test and Reset Bits
Test and Set Bits
Transfer Stack Pointer to Index X
Transfer Index X to Accumulator
Transfer Index X to Stack Register
Transfer Index Y to Accumulator
Notes:
(1) Instruction not available on the NMOS family.
(2) R6502 instruction with additional addressing mode(s).
1-9
R65COO Microprocessors (CPU)
R65C02, R65C102, R65C112
Table 2. Hexadecimal Codes For New Instructions in the R65COO Microprocessors
Hex
Mnemonic
80
DA
5A
FA
7A
9C
9E
64
74
lC
14
OC
04
0F-7Fll)
8F-FFll)
BRA
PHX
PHY
PLX
PLY
Description
Branch relative always [Relative[
Push X on stack [Implied]
Push Y on stack [Implied]
Pull X from stack [Implied
Pull Y from stack [Implied]
Store zero [Absolute]
Store zero [ABS, X]
Store zero [ZP]
Store zero [ZP, X]
Test and reset memory bits with accumulator [ABS]
Test and reset memory bits with accumulator [ZP]
Test and set memory bits with accumulator [ABS]
Test and set memory bits with accumulator [ZP]
Branch on bit reset [Bit Manipulation, Zp, REL]
Branch on bit set [Bit Manipulation, ZP, REL]
Reset memory bit [Bit Manipulation, ZP]
Set memory bit [Bit Manipulation, ZP]
STZ
STZ
STZ
STZ
TRB
TRB
TSB
TSB
BBR
BBS
RMB
5MB
07.771 1)
87·F71 1)
Note:
1. Most significant digit change only.
Table 3. Hexadecimal Codes For R65COO Instructions With New Addressing Modes
Hex
Mnemonic
Description
72
AOC
AND
BIT
BIT
BIT
CMP
DEC
EOR
INC
JMP
LOA
ORA
SBC
STA
Add memory to accumulator with carry [(INO)]
AND memory with accumulator [(INOll
Test memory bits with accumulator [ABS, X]
Test memory bits with accumulator [ZP, X]
Test Immediate with accumulator [IMM]
Compare memory and accumulator [(INO)]
Decrement accumulator [Accum]
Exclusive Or memory with accumulator [(INOll
Increment accumulator [Accum]
Jump (New addressing mode) [(ABS, X)]
Load accumulator with memory [(INO)]
OR memory with accumulator [(INO)]
Subtract Memory from accumulator with borrow [(INO)]
Store accumulator in memory [(INO)]
32
3C
34
89
02
3A
52
lA
7C
B2
12
F2
92
Table 4. R65COO Operational Enhancements
Function
NMOS R6502 Microprocessor
CMOS R65COO Family Microprocessor
Indexed addressing across page boundary.
Extra read of invalid address.
Extra read of last instruction byte.
Execution of invalid op codes.
Some terminate only by reset. Results are
undefined.
All are NOPs (reserved for future use).
Page address does not increment.
Page address increments and adds one additional cycle.
Read/modify/write instructions at effective
address.
One read and two write cycles.
Two read and one write cycle.
Decimal flag.
Indeterminate after reset.
Initialized to binary mode (0 =0) after reset
and interrupts.
Flags after decimal operation.
Invalid N, V and Z /lags.
Valid flag adds one additional cycle.
Interrupt after fetch of BRK instruction.
Interrupt vector is loaded, BRK vector is
ignored.
BRK is executed, then interrupt is executed.
Jump Indirect, operand
= XXFF.
1-10
R65C02, R65C102, and R65C112
R65COO Microprocessors (CPU)
INSTRUCTION SET OP CODE MATRIX
The following matrix shows the 210 Op Codes associated with
the R65COO family of CPU devices. The matrix identifies the
hexadecimal code, the mnemonic code, the addressing mode,
LSD
'"
en
::;;
c
o
E
F
TSB
ZP
2 5
ORA
ZP
2 3
ASL
ZP
2 5
RMBO
ZP
2 5
PHP
Implied
3
ORA
IMM
2 2
ASL
Accum
2
TSB
ABS
3 6
ORA
ABS
3 4
ASL
ABS
3 6
BBRO
ZP
3 5--
TRB
2 5
ORA
ZP. X
2 4
ASL
ZP, X
2 6
RMB,
ZP
2 5
CLC
Implied
2
ORA
ABS. Y
3 4-
INC
Accum
2
TRB
ABS
3 6
BIT
ZP
2 3
AND
ZP
2 3
ROL
ZP
2 5
RMB2
ZP
2 5
PLP
Implied
4
AND
IMM
2 2
ROL
Accum
2
BIT
ASS
3 4
BIT
ZP. X
2 4
AND
ZP. X
2 4
ROL
ZP, X
2 6
RMB3
ZP
2 5
SEC
Implied
2
AND
ABS. Y
3 4'
DEC
Accum
2
BIT
ABS. X
3 4-
EOR
ZP
2 3
LSR
ZP
2 5
RMB4
ZP
2 5
PHA
Implied
3
EOR
IMM
2 2
LSR
Accum
2
JMP
ABS
3 3
EOR
ZP. X
2 4
LSR
ZP. X
2 6
RMB5
ZP
2 5
CLI
Implied
2
EOR
ABS. Y
3 4-
PHY
Implied
3
STZ
ZP
2 3
ADC
ZP
2 3t
ROR
ZP
2 5
RMB6
ZP
2 5
PLA
Implied
4
ADC
IMM
2 2t
ROR
Accum
2
JMP
(ABS)
3 6
ADC
ABS
3 4t
ROR
ABS
3 6
3
STZ
ZP, X
2 4
ADC
ZP. X
2 4t
ROR
ZP. X
2 6
RMB7
ZP
2 5
SEI
Implied
2
ADC
ABS. Y
3 4-t
PLY
Implied
4
JMP
ABS, X
3 6
ADC
ABS, X
3 4-t
ROR
ABS. X
3 7
3
STY
ZP
2 3
STA
ZP
2 3
STX
ZP
2 3
5MBO
ZP
2 5
DEY
Implied
2
BIT
IMM
2 2
TXA
Implied
2
STY
ABS
3 4
STA
ABS
3 4
STX
ABS
3 4
3
STA
(IND)
2 5
STY
ZP.X
2 4
STA
ZP. X
2 4
STX
ZP. Y
2 4
5MB'
ZP
2 5
TYA
Implied
2
STA
ABS. Y
3 5
TXS
Implied
2
STZ
ABS
3 4
LOX
IMM
2 2
LOY
ZP
2 3
LOA
ZP
2 3
LOX
ZP
2 3
5MB2
ZP
2 5
TAY
Implied
2
LOA
IMM
2 2
TAX
Implied
2
LOY
ABS
3 4
LOA
(IND)
2 5
LOY
ZP, X
2 4
LOA
ZP. X
2 4
LOX
ZP, Y
2 4
5MB3
ZP
2 5
CLV
Implied
2
LOA
ABS, Y
3 4-
TSX
Implied
2
LOY
ABS.X
3 4-
CPY
ZP
2 3
CMP
ZP
2 3
DEC
ZP
2 5
5MB4
ZP
2 5
INY
Implied
2
CMP
IMM
2 2
DEX
Implied
2
CPY
ABS
3 4
CMP
ZP. X
2 4
DEC
ZP. X
2 6
5MB5
ZP
2 5
CLD
Implied
2
CMP
ABS, Y
3 4-
PHX
Implied
3
SBC
ZP
2 3t
INC
ZP
2 5
5MB6
ZP
2 5
INX
Implied
2
SBC
IMM
2 2t
NOP
Implied
2
SBC
ZP, X
2 4t
INC
ZP. X
2 6
5MB7
ZP
2 5
SED
Implied
2
SBC
ABS, Y
3 4-t
PLX
Implied
4
A
4
0
BRK
ORA
Implied (IND. X)
7
2 6
,
SPL
ORA
Relative (IND). Y
2 2-2 5JSR
ASS
3 6
ORA
(IND)
2 5
zp
AND
(IND. X)
2 6
BMI
AND
Relative (IND), Y
2 2"
2 5-
AND
(IND)
2 5
RTI
EOR
Implied (IND. X)
6
2 6
,
BVC
EOR
Relative (IND). Y
2 2-2 5RTS
Imphed
6
,
EOR
(IND)
2 5
ADC
(IND, X)
2 6t
BVS
ADC
Relative (IND). Y
2 2-- 2 s-t
ADC
(IND)
2 5t
BRA
STA
Relative (IND. X)
2 32 6
BCC
STA
Relative (IND), Y
2 2-2 6
A
B
C
o
E
F
LOY
IMM
2 2
LOA
(IND. X)
2 6
BCS
LOA
Relative (IND). Y
2 2-2 5CPY
IMM
2 2
CMP
(IND. X)
2 6
BNE
CMP
Relative (IND). Y
2-2
2 5CPX
IMM
2 2
the number of instruction bytes, and the number of machine
cycles associated with each Op Code. Also, refer to the instruction set summary for additional information on these Op Codes.
CMP
(IND)
2 5
CPX
ZP
2 3
SBC
(IND. X)
2 6t
BEQ
SBC
Relative (IND). Y
2 2-2 5-t
SBC
(IND)
2 5t
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
o
,
,
,
,
,
D-
New Opcode
o
-OP Code
-Addressing Mode
-Ins'ruction Bytes; Machine Cycles
1-11
ORA
ASL
ABS, X ABS. X
3 43 7
AND
ABS
3 4
ROL
ABS
3 6
AND
ROL
ABS, X ABS, X
43
7
3
EOR
ABS
3 4
LSR
ABS
3 6
EOR
LSR
ABS, X ABS. X
3 43 7
,
,
,
,
,
,
,
,
STA
STZ
ABS. X ABS. X
3 5
3 5
LOA
ABS
3 4
LOX
ABS
3 4
LOX
LOA
ABS, X ABS. Y
3 43 4CMP
ABS
3 4
DEC
ABS
3 6
CMP
DEC
ABS. X ABS. X
3 43 7
,
CPX
ABS
3 4
,
sec
ABS
3 4t
INC
ABS
3 6
INC
SSC
ABS. X ABS. X
3
7
3 4-t
,
A
o
B
B
C
o
E
o
BBR'
ZP
3 5-BBR2
ZP
3 5-BBR3
ZP
5"
3
BBR4
ZP
5--
3
BBR5
ZP
5--
5
3
BBR6
ZP
5-BBR7
ZP
5"
BBSO
ZP
5--
BBS'
ZP
5--
3
BBS2
ZP
5--
A
BBS3
ZP
3 5--
S
BBS4
ZP
3 5--
C
BBS5
ZP
3 5"
o
BBS6
ZP
3 5--
E
BBS7
ZP
5--
F
3
3
F
tAdd , to N Hin decimal mode.
"Add 1 to N if page boundary is crossed.
...Add 1 to N if branch occurs to same page;
Add 2 to N if branch occurs to different page.
OPERATION
MNEMONIC
ADC
AND
ASL
BBA ['(0-7)1
Branch on M. '" 1
Branch on C "',
Branch on C::: 1
Branch on Z", 1
A>M (6)
Branch on N", 1
Branch on Z"" III
Branch on N =if
Branch Always
Break
Branch on V = III
Branch on V = 1
0-C
e-D
0-1
0-V
A-M
X-M
V-M
IMPlIED
P n
•
(1110, XI
P n •
61
21
0A 2
;- 5
3
:;; 5
3
6
6
2 71
2 31
5
5
1
2 75 4
2 35 4
16 6
a9 2
2 2C 4
3 24 3
ABS. X
P n •
2 7D 4
2 3D 4
ABS. Y
P n
•
79 4
39 4
3
3
I2l-M t • (4)
AOL
AOA
ATI
ATS
SBC
SEC
SED
SEI
~
Rlrn Int
5MB['~711
1-Mb
STA
STX
STY
STZ
TAX
TAV
TAB
TSB
TSX
TXA
TXS
TVA
A-M
X-M
V-M
0-M
A-X
A-V
AA M-M
Rlrn Sub
A-M C-A (1) (3) (5)
•
P n
•
72 5
32 5
2
2
P n
•
N V
N
N
N
•
D
I
V
Z C
Z
Z
Z
C
C
34 4
2
0e 7
2 3C 4
M.
3
ES2
C0 2
~ F.g
m
....
2
~~
3
3
3
3
C5
E4
C4
C6
Cl 6
3
3
3
5
2 Dl 5
2 D5 4
2 DD 4
09 4
3
2 40 4
3A 2
1
41
45 3
E6 5
EE 6
lA 2
6
2 51
5
D6 6
2 DE 7
2 55 4
f6 6
2 50 4
4C 3
2111 6
2 AD 4
2 AE 4
2 AC 4
4E 6
3
3
3
3
3
3
AS
A6
A4
46
1
59 4
4A 2
2 ,D 4
3 215 3
~~-
5
2
3 26 5
3 66 5
2
2
01
2A 2
6A 2
3
3
3
3
4
4111
4
4
6
2 11
5
2 ED 4
3 E5 3
2
6e 6
3
2 B5 4
2 BD 4
B4 4
56 6
2 Be 4
2 5E 7
82 5
2
2 15 4
36 6
76 6
1
1
3
B9 4
BE 4
B6 4
2
El
6
2 fl
5
2 f5 4
4
4
4
4
87f7
B5
B6
84
64
lC 6
ec 6
14
'4
AV M-M
BD
BE
BC
9C
Bl
6
2 91
6
2 95 4
2 10 43
19 4
3
12 5
2 FD 43
F9 4
3
F2 5
1. AcId 1 to N if page boundary is crossed.
2. Add 1 to N If branch occurs to same page.
Add 2 to N...!f branch occurs to different page.
3. Carry not (C) "" Borrow.
4. Effects 8-bit data fteld of the specified zero page address.
5. Add 1 to N If in Decimal Mode.
6. On the Bit Immediate Instruction, the results of the M7 and Ms bits (N and V flags) are indeterminate and should be considered invalid.
7. If in Decimal Mode. Z flag is invalid. Accumulator must be checked for zero result
a JMP (OP Code 6C) is an Absolute Indirect /l,ddressing Mode (ABS).
Q.
JJ
en
0.....
(II
2 90 53
1
99 5
3
92 5
JJ
en
0
(II
C
2
0
0
3:
2
3
0"
""I
2
N
0
'tJ
""I
0
()
CD
N
2
2
2
2
Notes:
-<
::::I
(Restored)
C
C
AA 2
AS 2
BA
BA
9A
9B
l>
:::D
N
N
2 3E 73
2 7E 7 3
2
2 9E 5
II)
2
96 4
94
74
j')
s::
s::
N
Fa
7B
(4)
....0
,
(Restored)
2
JJ
en
0
(II
.....
3B
l-C
1-0
1-1
0
j')
N
3
I I I I I I I I I I I I I I I I I I I I I I I I I I I
4'
60
E9 2
52 5
1
2
4B
,a
DA
SA
6B
2a
fA
7A
2E 6
6E 6
2 Bl 5
1
3
2 FE 7
7C 6
Al 6
3
3
3
5
EA 2
09 2
C
2
3
EB 2
CB 2
A9 2
A2 2
Ae 2
02 5
C
C
CA 2
aB 2
49 2
3
JJ
en
0
(II
(J)
c:
1
"
2
Da
2
sa 2
Ba 2
4
4
4
6
0
....
(J)
M~
50 2
7~ 2
C9 2
~
:::D
c:
z
30 2
D~ 2
10 2
a0 3
Ms-Y
RMBII(fIf-7)1
n
Z. PAGE, Y 7 6 5 4 3 2 1 0
INO
2 lE 7
(2)
(2)
No Operation
AVM-A
(I)
A-Ms S-1-5
P-Ms $-1-$
X-Ms S-1-S
Y-Ms S-1-S
S+1-S Ms-A
$+1-S Ms-P
S+ 1-S Ms-X
RELA,nVE
0
(2)
(2)
(2)
(2)
Jump to New Loc (8)
Jump Sub
M-A
(I)
M-X
(I)
M-V
111
-C
0- u::=:::ID
Z
CODES
(INOI. V l. PAGE, X ABS. X
P n •
P n •
P n •
ge 2
B0 2
fe 2
M+l-MorA+l-A
X+l-X
Y+ t_Y
S-X
X-A
X-S
V-A
ACCUM.
P n •
(2)
(2)
(2)
M-l-M or A-l-A
X-l-X
Y-l-Y
A¥M-A
(11
S+1-S
ZP REl
P n •
65 3
25 3
06 5
2 60 4
2 20 4
0E 6
Branch on M. "'"
BCC
BCS
BEQ
BIT
BMI
BNE
BPL
BAA
BAK
BVC
BVS
CLC
CLD
CLI
CLV
CMP
CPX
CPV
DEC
DEX
DEV
EOA
INC
INX
INV
JMP
JSA
LDA
LOX
LDV
LSA
NOP
PHA
PHP
PHX
PHV
PLA
PLP
PLX
PLY
69 2
29 2
PROCESSOR STATUS
ADDRESSING MODES
,IMMEDIATf AIISOLIIT£ ZERO PAGE
)P n ,
P n •
P n •
rr:=::ID
BBS [11("-7)]
lORA
N
A+M +C-A(l) (5) (7)
A M-A
(I)
C-~
I
N
LEGEND
X
== Index X
y
= Index Y
A = Accumulator
M = Memory per .effective address
Ms = Memory per stack pOtnter
Mb "" Selecter zero page memory bit
M, = Memory Btt 7
"" Memory Bit 6
= Add
- = SublraC1
1\
= And
V = Or
= Exdusive or
¥
n = Number of cycles
# _ = Number of Bytes
M6
til
til
0""I
til
0
"'0
c:
R65C02, R65C102, and R65C112
R65COO Microprocessors (CPU)
SWITCHING CHARACTERISTICS (Over operating conditions unless otherwise noted)
Parameter
CLOCK TIMING
~2 Cycle Time
tevc
1000
Note 1
500
Note 1
333
Note 1
250
Note 1
ns
02 Low Pulse Width
tCl
430
5000
210
5000
150
5000
100
5000
ns
02 High Pulse Width
tCH
450
-
220
-
160
110
-
ns
tDly
-
50
-
-
00 Low to 02 Low Skew(2)
50
-
40
-
30
ns
02 Low to 01 High Skew(2)
tDLY1
-20
20
-20
20
-20
20
-20
20
ns
XTLI High to 02 Low(')
tOXI
-
100
-
100
100
100
ns
XTLO Low to 02 Lowl')
t DXO
-
75
-
75
75
ns
85
-
65
ns
-
100
-
ns
02 Low to 04 High Delay(4)
tAVS
-
250
-
125
-
04 Low Pulse Width(')
t~L
430
-
210
-
150
~4 High Pulse Width(4)
1¢4H
450
Clock Rise and Fall Times
tR' tF
-
25
-
20
-
15
-
100
-
-
15
5000
220
5000
160
75
5000
110
5000
ns
-
12
ns
85
-
70
ns
-
15
-
ns
-
70
ns
READ/WRITE TIMING
RIW Delay Time
tAWS
-
125
RIW Hold Time
tHAW
15
-
Address Delay Time
tAOS
-
125
-
100
-
85
10
-
0
-
ns
15
-
15
-
ns
215
-
160
15
Address Valid to \14 High(4)
tA~
100
-
25
Address Hold Time
tHA
15
-
15
Read Access Time
tACe
775
-
340
-
Read Data Setup Time
tDS U
100
-
60
-
40
-
30
Read Data Hold Time
tHR
10
-
10
-
10
-
10
-
Write Data Delay Time(2)
tWDS
-
200
110
85
-
55
Write Data Delay Time(4)
toow
-
200
85
65
ns
Write Data Delay Time(S)
t0012
-
170
-
120
ns
Write Data Hold Time
tHw
30
30
-
ns
-
ns
ns
ns
450
-
235
-
-
30
-
30
-
-
85
-
70
ns
60
ns
ns
110
ns
CONTROL LINE TIMING
SYNC Delay
tsvs
-
125
-
100
ROY Setup Time
tAOS
200
-
110
80
40
-
30
-
-
85
-
70
10
-
10
-
ns
10
-
10
-
ns
40
-
40
ns
-
60
-
ns
150
-
ns
SO Setup Time
tsos
75
-
50
-
ML Delay Time(5)
t MLS
-
125
-
100
ML Hold Time(4)
tHML
10
-
10
ML Hold Time(S)
tHML
10
-
10
-
BE Delay Time(5)(a)
teE
-
40
-
40
IRQ, RES Setup Time
tiS
200
-
110
-
ao
NMI Setup Time
tNMJ
300
-
200
-
170
ns
Notes:
1. R65C02 and R65Cl02 minimum operating frequency is limited by 02 low pulse width. All processors can be stopped with 02 held high.
2. R65C02 only.
3. Note 3 deleted.
4. R65Cl02 only.
5. R65Cl02 and R65C112 only.
6. R65C112 only.
7. Measurement pOints shown are o.av (low) and 2.0V (high) for outputs and 1.5V (low and high) for inputs, unless otherwise specified.
a. BE signal is asynchronous.
1-13
R65COO Microprocessors (CPU)
R65C02, R65C102, R65C112
$0 (IN)'
--IOlV
$1 (OUT)'
02 (OUT)'
$2 (IN)'
AO-A1S, Riw
SYNC
-
J
-
-tOlV'
tCl
-
I
tAOS' tRWS' tsvs
Icvc
- tR
•
READ (RJW
).
.WRITE (RIW
tACe
~ I--IF
tCH
=
=
HIGH)
LOW)
tosu_
00-07
(READ)
-
tDD12
00-07
(WRITE)
ML2
-
- tMlS
----+
tHA' tHAW
}(
I--
~IHR
_ t HW
tHMl
I--
-9~-I-
t,s
)
IRO, NMI, RES ACTIVE
I-- tsos
NOTES:
1. R6SC02
2. R6SCl12
Figure 3.
-
r--
K
}
ROY ACTIVE
ROY, IRO
NMI, RES
-twos
-
1
Timing Diagram for the R65C02 and R65C112
1-14
.... INM'
-tRos
R65C02, R65C102, R65C112
R65COO Microprocessors (CPU)
XTLI (IN)
-l
_ I oxi
-
XTLO (OUT)
~
--1
~
I-
~
_ I oxo
ICYC
ICl
-
112 (OUT)
1\
-IF
_ _ IAVS
IR -
114 (OUT)
IAos'
00-07
I--
li4H
/
tRWS'
tsvs
tHRW,tHA~
RiW, SYNC,
AO-A15, ML
I'-
~IMLS----:
----...
-
IA'4
READ (RiW
-
~-u--
1'4l
=
WRITE (RiW
-
•
ICH
HIGH)
=
rr-
LOW)
lAce
I+--IHMlI--IHR
losu_
I!'IEAD)
00-07
-'rrr
(WRITE)
/-
r----
IHW -
loow
,
Isos
I----
I-
I
Ils_
ROY ACTIVE
ROY, IRQ,
NMI, RES
J.
IRQ, NMI AND RES ACTIVE
tNMI-+
IRos -+
Figure 4.
AO-A15
R/W
-,/-
......
--
Timing Diagram for the R65Cl02
TRI-STATE
---
BE - - - - - - ' ,
I{
NOTE: BUS ENABLE APPLIES TO THE R65Cl02 AND R65C112. BE IS ASYNCHRONOUS AND THEREFORE NOT DIRECTLY
RELATED TO THE 02 CLOCK.
Figure 5.
Timing Diagram for Bus Enable (BE)
1-15
I-
R65COO Microprocessors (CPU)
R65C02, R65C102, R65C112
CLOCK/CRYSTAL CONSIDERATIONS
NOTE
A crystal controlled time base generator circuit sholild be used
to drive 00 (IN) (R65C02) or the XTLI and XTLO (R65Cl02)
inputs. Alternatively, a TIL level clock input to XTLI may be used,
with XTLO floating.
As with any clock oscilltor circuit, stray capacitance due
to board layout can affect circuit operation requiring "fine
tuning" (e.g. component repOSitioning or value change)
of the circuits shown in Figures 6 and 7. Shunt capacitance
(C) includes stray capacitance.
Figure 6 shows a time base generation scheme, for a 4 MHz
operation of the R65C02, that has been tested and proven reliable for normal environments.
'
Figure 7 shows a possible external clock scheme for a R65Cl02
and R65C112 master/slave configuration.
Vee
R6SC102
MASTER
The on-chip oscillator is designed for a parallel resonant crystal connected between XTLI and XTLO pins. The equivalent
oscillator circuit is shown in Figure 7.
S~F
SpF
f-......---I>-+-I
XTLO
A parallel resonant crystal is specified by its load capacitance
and series resonant resistance. For proper oscillator operation,
the load capacitance (C L), series resistance (Rs) and the crystal resonant frequency (F) must meet the following two relations:
(C + 5) = 2C L
or
C = 2C L
-
5
\12
R65C112
SLAVE
39
(OUT)
7404
Notes: 1. The oscillator in the R65Cl02 is parallel
resonant.
2. R65Cl02 crystal frequency is divided by 4,
i.e., ~2 (OUT) = F/4.
3. See STOPPING THE CLOCK.
6
Rs :s Rsmax = 2 X 10
(FCLl 2
where: F is in MHz, C and CL is in pF, and R is in ohms.
Figure 7. Example of R65Cl02/R65C112
Master/Slave Clock Circuit
To select a parallel resonant crystal for the oscillator, first select
the load capacitance from a crystal manufacturer's catalog. Next,
calculate Rsm., based on F and C L• The selected crystal must
have a Rs less than the Rsmax.
STOPPING THE CLOCK-STANDBY MODE
For example, if C L = 30 pF for a 4 MHz parallel resonant
crystal, then
Caution must be exercised when configuring the R65C02 or
R65C112 in the standby mode (i.e., 00 IN or 02 IN clock stopped).
The input clock can be held in the high state indefinitely;
however, if the input clock is held in the low state longer than
5 microseconds, internal register and data status can be lost.
Figure 8 shows a circuit that will stop the 00 IN (R65C02) or
021N (R65CI12) clock in the high state during standby mode.
C = (2x30) - 5 = 55 pF
(use standard value of 56 pF)
The series resistance of the crystal must be less than
Rsmax =
I.SK
2 X 106 = 138 ohms
(4 X 30)2
3.0K
R65C02
STOP
L=STANDBY
H=ACTIVE
\12 (OUT)
39
TIME
BASE
(SEE FIG. 6)
+SV
Notes: 1. Crystal CTS Knight MP Series.
2. See STOPPING THE CLOCK.
Note: 1. R65C02 = 00 (IN)
R65C112 = 02 (IN)
Figure 6. Example of R65C02 External Time Base
Generator Circuit
Figure 8. Stopping the Clock (Standby Mode) Circuil
1-16
R65COO Microprocessors (CPU)
R65C02, R65C102, and R65C112
ABSOLUTE MAXIMUM RATINGS·
Symbol
Value
Unit
Supply Voltage
Parameter
Vee
-0.3 to +7.0
Vdc
Input Voltage
VIN
- 0.3 to Vce + 0.3 Vdc
Output Voltage
VOUT
-0.3 to Vee +0.3 Vdc
Storage Temperature
TSTG
-55 to + 150
·NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the other sections of this document
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
°C
OPERATING CONDITIONS
Parameter
Symbol
Value
Vee
5 Vdc ±5%
Supply Voltage
Operating Temperature (Ambient)
Commercial
Industrial
Military
TL to TH
O°C to 70°C
-40°C to +85°C
- 55°C to + 125°C
ELECTRICAL CHARACTERISTICS
(Over operating conditions unless otherwise noted)
Parameter
Min
Symbol
Input High Voltage
-40°C to 85°C
-55°C to 125°C
VIH
Input Low Voltage
-40°C to 85°C
-55°C to 125°C
VIL
Typ4
Max
Unit
2.0
2.4
Vee +0.3
Vee +0.3
-0.3
-0.3
+0.8
+0.4
V
Input High Voltage 00 R65C02)
VIHO
2.4
Vee +0.3
Input Low Voltage 00 (R65C02)
vILa
-0.3
+0.4
V
Input High Voltage 02 (IN) (R65CI12)
VIH2
Vee -0.4
Vec +0.3
V
Input Low Voltage 02 (IN) (R65CI12)
VIL2
-0.3
+0.4
Input Leakage Current
NMI, IRQ, BE,RDY,RES,SO
02 (IN), 00 (IN), XTLI
liN
Three-State (Off State) Input Current
Data Lines
ITSI
Output High Voltage
SYNC, Data, AO-A1S,
VOH
RNJ,
VOL
Supply Current
Standby'
Active (R6SC02)
Active (R6SC102)
Active (R6SC112)
Low Power (R65C02)
Low Power (R65Cl02)
Low Power (R65C112)
Icc
Capacitance
NMI,IRQ,SO,BE, RDY
SYNC, Data, AD-AI5, RiW, 01 (OUT), 02 (OUT), 04 (OUT), ML,
XTLO
00 (IN), XTLI
02 (IN)
V
V
p.A
VIN = OV to 5.25V
Vec = OV
pA
VIN = 0.4V to 2.4V
Vee = S.2SV
-
-
-SO
1.0
-
10
2.4
-
V
Vee = 4.75V
ILOAD = - 100 p.A
+0.4
V
Vee = 4.7SV
lLOAO = 1.6 mA
01 (OUT), 02 (OUT), 04 (OUT), ML
Output Low Voltage
SYNC, Data, AD-AI5, RiW, 01 (OUT), 02 (OUT), 04 (OUT), ML
-
-
-
2
2.6
5
2
1.5
3
0.7
10
4
7
4
2
5
1
Vee = 5.0V
p.A
mNMHz
mNMHz
mNMHz
mNMHz RDY=O
mNMHz RDY=O
mNMHz flDY=O
pF
CIN
COUT
-
-
7
10
Co
C2
-
10
30
Notes:
1. All units are direct current (de).
2. Negative sign indicates outward current flow, positive indicates inward flow.
3. IRQ and NMI require external pull-up resistor.
4. Typical values shown for Vec = 5.0V and TA = 25°C.
1-17
Test Conditions
V
Vee = 5.0V
VIN = OV
Y,N = OV
f = 1 MHz
TA = 2SOC
R65C02, R65C102, R65C112
R65COO Microprocessors (CPU)
PACKAGE DIMENSIONS
40·PIN CERAMIC DIP
[ D ]J]
I·1
w
113;In
IH~~LD
A
t
F
G...j
K_ _ J
M-j
MILLIMETERS
MIN
MAX
MIN
MAX
A
50.29
15.11
51.31
2.020
0.625
15.88
1.980
0.595
C
2.54
4.19
0.100
0,165
D
0.38
0.53
0.015
0.021
F
0.76
1.27
0.030
B
G
c
~~
-JHI-
---jG\+
F ...... D
K
M
esc
2.54
H
0.76
J
0.20
0.050
0.100
esc
1.78
0.33
0.030
0.008
0.070
0.013
K
2.54
4.19
0.100
0.165
L
14.60
15.37
0.575
0.605
M
o·
10'
0'
W
0.51
1.52
0.020
0.060
N
40·PIN PLASTIC DIP
I;::::::::: ~:::::: ::;P r<4
INCHES
DIM
DIM
MILLIMETERS
MIN
MAX
INCHES
MIN
MAX
A
51.82
52.32
2.040
2.060
B
13.46
13.97
0.530
0.550
C
3.56
5.08
0.140
D
0.38
0.53
0.015
0.021
F
1.02
1.52
0.040
0.060
asc
H
1.65
2.16
0.100 BSC
0.065 0.085
J
0.20
0.30
0.008
0.012
K
3.30
4.32
0.130
0.170
L
15.24
G
2.54
0.200
M
7'
N
0.51
esc
I
10'
1.02
o.soo esc
7·
I
10·
0.040
0.020
44·PIN PLASTIC LEADED CHIP CARRIER (PLCC)
,"ou~g@
1~r=D2:j 'I
?
rrr
1M ""'
CORNER
6
D2
L
39-
X
45"
'~
+
~i
~
~8~
ill tnn.fiIi:
~
I-ce
CHAM.
11 PINS
h X 45" PER SIDE
3 PLCS EQUALLY
SPACES
SECTION A-A
TYP FOR BOTH AXIS (EXCEPT FOR BEVELED EDGE)
~~b
EJECTOR PIN MARKS
4 PLCS BOTTOM OF
PACKAGE ONLY
(TYPICAL)
BOTTOM VIEW
1-18
MAX
INCHES
MIN
MAX
A
4.14
4.39
0.163
0.173
1.37
1.47
0.054
0.058
A.
2.31
2.46
0.457 TVP
0.091
0.097
0.D18 TVP
D
17.45
17.60
0.687
D1
16.46
16.56
0.648
0.652
D2
12.62
I 12.78
0.497
I 0.503
D3
~~"'
MIN
A1
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R65C21
'1'
R65C21
Peripheral Interface Adapter (PIA)
Rockwell
DESCRIPTION
FEATURES
The R65C21 Peripheral Interface Adapter (PIA) is designed to
solve a broad range of peripheral control problems in the implementation of microcomputer systems. This device allows a very
effective trade-off between software and hareware by providing
significant capability and flexibility in a low cost chip. When
coupled with the power and speed of the R6500, R6500/' or
R65COO family of microprocessors, the R65C21 allows implementation of very complex systems at a minimum overall cost.
• Low power CMOS N-well silicon gate technology
• Direct replacement for NMOS R6520 or MC6821 PIA
• Two 8-bit bidirectionalI/O ports with individual data direction
control
• Automatic "Handshake" control of data transfers
• Two interrupts (one for each port) with program control
• 1, 2, 3, and 4 MHz versions
• Commercial and industrial temperature range versions
• Wide variety of packages
- 40-pin plastic and ceramic DIP
- 44-pin plastic leaded chip carrier (PLCC)
• Single + 5 Vdc power requirement
• Compatible with the R6500, R6500,. and R65COO family of
microprocessors
Control of peripheral devices is handled primarily through two
8-bit bidirectional ports. Each of these lines can be programmed
to act as either an input or an output. In addition, four peripheral
control/interrupt input lines are provided. These lines can be used
to interrupt the processor or to "handshake" data between the
processor and a peripheral device.
vss
CA.
CA2
IRQA
IRQB
RSO
RS.
RES
DO
D.
02
03
04
05
06
07
.2
CS.
CS2
PAO
PAl
PA2
PA3
PA4
PAS
PA6
PA7
PBO
PB,
PB2
PB3
PB4
PBS
PB6
PB7
CB.
CB2
PA4
PAS
PA6
PA7
PBO
PB.
PB'
PB3
PB4
PB5
PB6
~
.,
~
~
~
M
~
N
10(1"'
N
~
M N
0
..,. ..,.
..,. ..,. ..,.
~
~
0
39
38
37
36
35
34
33
32
3.
30
29
PIN.
INDICATOR
.0
11
.2
.3
'4
'5
.6
'7
m m
~
P
0
N
~
N
N
N
M
N
..,.
N
~
N
~
~
N N
RSO
RS.
RES
DO
D.
02
03
04
05
06
07
m
N
fB~~~'~~IB~g~
RM
40-PIN DIP
44-PIN PLCC
Figure 1.
Document No. 29651N53
N
CCCl:cI;O =c(c(~~u
a.a..a.a..z>uu
__ z
eso
Vee
...
NC = NO INTERNAL
CONNECTION
R65C21 Pin Assignments
Product Description
1-19
Order No. 2150
Rev. 5, June 1987
Peripheral Interface Adapter (PIA)
R65C21
ORDERING INFORMATION
decoder circuits. When the PIA is selected, data will be transferred
between the data lines and PIA registers, and/or peripheral inter·
face lines as determined by the Rm, RSO, and RSl lines
and the contents of Control Registers A and B.
,/
Part Number:
R65C21
RESET SIGNAL (RES)
The Reset (RES) input initializes the R65C21 PIA. A low signal
on the RES input causes all internal registers to be cleared.
CLOCK SIGNAL (02)
Frequency
1 =
2 =
3 =
4 =
The Phase 2 Clock Signal (02) is the system clock that triggers
all data transfers between the CPU and the PIA. 02 is generated
by the CPU and is therefore the synchronizing signal between the
CPU and the PIA.
1 MHz
2 MHz
3 MHz
4MHz
' - - - - Package
C = 40·Pin Ceramic DIP
P = 40·Pin Plastic DIP
J = 44·Pin Plastic Leaded
Chip Carrier (PLCC)
READIWRITE SIGNAL (R/W)
ReadlWrite (RiW) controls the direction of data transfers between
the PIA and the data lines associated with the CPU and the
peripheral devices. Rm high permits the peripheral devices to
transfer data to the CPU from the PIA. R/Vii low allows data to
be transferred from the CPU to the peripheral devices from the
PIA.
INTERFACE SIGNALS
The PIA interfaces to the R6500, R6500" or the R65COO micro·
processor family with a reset line, a02 clock line, a read/write line,
two interrupt request lines, two register select lines, three chip
select lines, and an B·bit bidirectional data bus.
REGISTER SELECT (RSO, RS1)
The two Register Select lines (RSO, RS1), in conjunction with the
Control Registers' (CRA, CRB) Data Direction Register access
bits select the various R65C21 registers to be accessed by the
CPU. RSO and RS1 are normally connected to the microprocessor
(CPU) address output lines. Through control of these lines, the
CPU can write directly into the Control Registers (CRA, CRB), the
Data Direction Registers (DDRA, DDRB) and the Peripheral Out·
put Registers (ORA, ORB). In addition, the processor may directly
read the contents of the Control Registers and the Data Direction
Registers. Accessing the Peripheral Output Register forthe pur·
pose of reading data back into the processor operates differently
on the ORA and the ORB registers and, therefore, are shown
separately in Table 1.
The PIA interfces to the peripheral devices with four interrupti
control lines and two B·bidirectional data ports.
Figure 1 (on the front page) shows the R65C21 PIA pin assign·
ments and Figure 2 groups the signals by functional interface.
CHIP SELECT (CSO, CS1, CS2)
The PIA is selected when CSO and CS1 are high and CS2 is
low. These three chip select lines are normally connected to the
processor address lines either directly or through external
L
00·07
<-
(81
--"
81
> PAO.PA7}
112
R6S00,
R6S001'
OR
R6SCOO
MICROPROCESSOR
FAMILY
CAl
CA2
R/W
RSO
RSl
CSO
CSl
CS2
RES
IROA
IROB
VSS
VCC
PERIPHERAL
DEVICE
A
R65C2l
PIA
...
..
..
(81
Figure 2.
...>
R65C21 ACIA Interface Signals
1·20
CBl
CB2
PBO·PB7
}
PERIPHERAL
DEVICE
B
R65C21
Peripheral Interface Adapter (PIA)
Table 1.
Register
Address
(Hex)
RSI
0
0
1
2
2
3
L
L
L
H
H
H
INTERRUPT INPUT/PERIPHERAL CONTROL LINES
(CA1, CA2, CB1, CB2)
ORA and ORB Register Addressing
Register
Data Direction
Control
Select Lines
RSO
L
L
H
L
L
H
CRA
CRB
(Bit 2) (Bit 2)
1
0
-
-
-
-
1
0
-
Register Operation
-
R,w=L
R/W=H
Read
Read
Read
Read
Read
Read
PIBA
DDRA
CRA
PIBB
DDRB
CRB
The four interrupt input/peripheral control lines provide a number of special peripheral control functions. These lines greatly
enhance the power of the two general purpose interface ports
(PAO-PA7), PBO-PB7). Figure 4 summarizes the operation of
these control lines.
WrileORA
Write DDRA
Write CRA
Write ORB
Write DDRB
Write CRB
CA 1 is an interrupt input only. An active transition of the signal
on this input will set bit 7 of the Control Register A to a logic 1.
The active transition can be programmed by setting a 0 in bit 1
of the CRA if the interrupt flag (bit 7 of CRA) is to be set on a negativetransition of theCAl signal ora 1 if it isto beset on a positive
transition.
INTERRUPT REQUEST LINES (IRQA, IRQB)
The active low Interrupt Request lines (IROA and IROB) act to
interrupt the microprocessor either directly or through external
interrupt priority circuitry. These lines are open drain and are capable of sinking 1.6 mA from an external source. This permits all
interrupt request lines to be tied together in a wired-OR configuration. The A and B in the titles of these lines correspond to the
peripheral port A and the peripheral port B so that each interrupt
request line services one peripheral data port.
CA2 can act as a totally independent interrupt or as a peripheral
control output. As an input (CRA, bit 5 = 0) it acts to set the interrupt flag, bit 6 of CRA, to a logic 1 on the active transition selected
by bit 4 of CRA.
These control register bits and interrupt inputs serve the same
basic function as that described above for CA 1. The input signal
sets the interrupt flag which serves as the link between the
peripheral device and the processor interrupt structure. The interrupt disable bit allows the processor to exercise control over the
system interrupt.
Each Interrupt Request line has two interrupt flag bits which can
cause the Interrupt Request line to go low. These flags are bits 6
and 7 in the two Control Registers (CRA, CRB). These flags act
as the link between the peripheral interrupt signals and the
microprocessor interrupt inputs. Each flag has a corresponding
interrupt disable bit which allows the processor to enable or disable the interrupt from each of the four interrupt inputs (CAl, CA2,
CB1, CB2). The four interrupt flags are set by active transitions
of the signal on the interrupt input (CA I, CA2, CBI, CB2).
In the output mode (CRA, bit 5 = 1), CA2 can operate independently to generate a simple pulse each time the microprocessor
reads the data on the Peripheral A I/O port. This mode is selected
by setting CRA, bit 4 to a 0 and CRA, bit 3 to a 1. This pulse output can be used to control the counters, shift registers, etc., which
make sequential data available on the Peripheral input lines.
CRA bit 7 (IROA1) is always set by an active transition of the CAl
interrupt input signal. However, IROA can be disabled by
setting bit 0 in CRA to a O. Likewise, CRA bit 6 (IROA2) is
set by an active transition of the CA2 interrupt input signal and
IROA can be disabled by setting bit 3 in CRA to a O.
Both bit 6 and bit 7 in CRA are reset by a "Read Peripheral Output
Register A" operation. This is defined as an operation in which
the read/write, proper data direction register and register select
signals are provided to allow the processor to read the Peripheral
A I/O port. A summary of IROA control is shown in
Table 2.
A second output mode allows CA2 to be used in conjunction with
CA I to "handshake" between the processor and the peripheral
device. On the A side, this technique allows positive control of data
transfers from the peripheral device into the microprocessor. The
CA 1 input signals the processor that data is available by interrupting the processor. The processor reads the data and sets CA2
low. This signals the peripheral device that it can make new data
available.
Control of IROB is performed in exactly the same manner as
that described above for IROA (Table 2). Bit 7 in CRB (IROB1)
is set by an active transition on CB1 and IROB from this flag
is controlled by CRB bit O. Likewise, bit 6 (IROB2) in CRB is set
by an active transition on CB2, and IROB from this flag is
controlled byCRB bit 3. Also, both bit 6 and bit 7 of CRB are reset
by a "Read Peripheral B Output Register" operation.
The final output mode can be selected by setting bit 4 of CRA to
a 1. In this mode, CA2 is a simple peripheral control output which
can be set high or low by setting bit 3 of CRA to a 1 or 0,
respectively.
Table 2.
CB1 operates as an interrupt input only in the same manner as
CA 1. Bit 7 of CRB is set by the active transition selected by bit
o of CRB. Likewise, the CB2 input mode operates exactly the
same as the CA2 input modes. The CB2 output modes, CRB
bit 5 = 1, differ somewhat from those of CA2. The pulse output
occurs when the processor writes data into the Peripheral B
Output Register. Also, the "handshaking" operates on data transfers from the processor into the peripheral device.
IRQA and IRQB Control Summary
Control Register Bits
Action
CRA-?= 1 and CRA-O=!
IROA goes low (Active)
CRA-S =! and eRA-3 = I
IROA goes low (Active)
CRB-?=! and CRB-O=!
IROB goes low (Active)
CRB-S =! and CRB-3 = !
IROB goes low (Active)
1-21
Peripheral Interface Adapter (PIA)
R65C21
FUNCTIONAL DESCRIPTION
of the 02 clock. This assures that the data on the peripheral output
lines will make smooth transitions from high to low (or from low
to high) and the voltage will remain stable except when it is going
to the opposite polarity.
The R65C21 PIA is organized into two independent sections
referred to as the A Side and the B Side. Each section consists
of a Control Register (CRA, CRB), Data Direction Register
(DDRA, DDRB), Output Register (ORA, ORB), Interrupt Status
Control (ISCA, ISCB), and the buffers necessary to drive the
Peripheral Interface buses. Data Bus Buffers (DBB) interface
data from the two sections to the data bus, while the Data Input
Register (DIR) interfaces data from the DBB to the PIA registers.
Chip Select and Rm control circuitry interface to the processor
bus control lines. Figure 3 is a block diagram of the R65C21 PIA.
CONTROL REGISTERS (CRA AND CRB)
Table 3 illustrates the bit designation and functions in the two control registers. The control registers allow the microprocessor to
control the operation of the Interrupt Control inputs (CA1, CA2,
CB1, CB2), and Peripheral Control outputs (CA2, CB2). Bit 2 in
each register controls the addressing of the Data Direction
Registers (DDRA, DDRB) and the Output Registers (ORA, ORB).
In addition, two bits (bit 6 and 7) in each control register indicate
the status of the Interrupt Input lines (CA1, CA2, CB1, CB2). These
Interrupt Status bits (IRQA1, IRQA2 or IRQB1, IRQB2)
are normally interrogated by the microprocessor during the
IRQ interrupt service routine to determine the source of the
interrupt.
DATA INPUT REGISTER (DIR)
When the microprocessor writes data into the PIA, the data which
appears on the data bus during the 02 clock pulse is latched into
the Data Input Register (DIR). The data is then transferred into
one of six internal registers of the PIA alier the trailing edge
IRQA
t
01
02
03
04
05
06
07
-
·
CONTROL
I
REGISTERA I
(CRA)
f1
·
DO
~r
OUTPUT BUS
DATA BUS
BUFFER
(DBB)
~
==
~
J
PERIPHERALll
OUTPUT
REGISTER A
(ORA)
U
DATA INPUT
REGISTER
(DIR)
PERIPHERAL
OUTPUT
REGISTER B
(ORB)
CSO
·
·
-'"
RSO
RSl
RiW
'2
CHIP
SELECT
& RiW
CONTROL
INPUT BUS
L
~
RES
CONTROL
REGISTERB
(CRB)
U
b
PERIPHERAL
INTERFACE
BUFFER A
(PIBA)
PERIPHERAL
INTERFACE
BUFFER B
(PIBB)
PBO
PBl
PB2
PB3
....
PB4
PBS
PB6
PB7
fi
~L
R65C21 PIA Block Diagram
1-22
~. PAS
-'"
DATA DIRECTION
REGISTER B
(DDRB)
INTERRUPT STATUS
CONTROL B (ISCB)
Figure 3.
PAO
PAl
PA2
PA3
PA4
....L
b
CA2
PA6
PA7
~
IRQB
-'"
DATA DIRECTION
REGISTER A
(DORA)
CSl
CS2
CAl
INTERRUPT STATUS
CONTROL A (ISCA)
CBl
CB2
R65C21
Peripheral Interface Adapter (PIA)
Table 3
I
CRA
CRB
7
I
IROAl
I
7
I
IROBl
I
1
I
J
6
IROA2
6
IROB2
1
1
I
1
Control Registers Bit Designations
5
3
4
3
4
CB2 Control
DATA DIRECTION REGISTERS (DDRA, DDRB)
2
1
I
1
DORA/ORA
Select
CA2 Control
5
I
2
DDRB/ORB
Select
1
0
CAl Control
1
0
CBl Control
I
J
I
J
The buffers which drive the Peripheral A 110 lines contain "passive" pull-up devices. These pull-up devices are resistive in nature
and therefore allow the output voltage to go to Vee for a logic 1.
The switches can sink a full 3.2 mA, making these buffers capable of driving two standard TTL loads.
The Data Direction Registers (DORA, DDRB) allow the processor
to program each line in the 8-bit Peripheral 110 port to be either
an input or an output. Each bit in DORA controls the corresponding line in the Peripheral A port and each bit in DDRB controls the
corresponding line in the Peripheral B port. Writing a 0 in a bit position in the Data Direction Register causes the corresponding
Peripheral 110 line to act as an input; a 1 causes it to act as an
output.
In the input mode, the pull-up devices are still connected to the
110 pin and still supply current to this pin. For this reason, these
lines also represent two standard TTL loads in the input mode.
The Peripheral B 110 port duplicates many of the functions of the
Peripheral A port. The process of programming these lines to act
as an input or an output is similar to the Peripheral A port, as is
the effect of reading or writing this port. However, there are several
characteristics olthe buffers driving these lines which affecttheir
use in peripheral interfaCing.
Bit2 in each Control Register (CRA and CRB) controls access to
the Data Direction Register or the Peripheral interface. If bit 2 is
ai, a Peripheral Output register (ORA, ORB) is selected, and if
bit 2 is a 0, a Data Direction Register (DORA, DDRB) is selected.
The Data Direction Register Access Control bit, together with the
Register Select lines (RSO, RS1) selects the various internal
registers as shown in Table 1.
The Peripheral B 110 port buffers are push-pull devices, i.e., the
pull-up devices are switched OFF in the a state and ON for a
logic 1. Since these pull-ups are active devices, the logic 1 voltage
will not go higher than + 2.4 Vdc.
PERIPHERAL OUTPUT REGISTER (ORA, ORB)
The Peripheral Output Registers (ORA, ORB) store the output
data from the Data Bus Buffers (DBB) which appears on the
Peripheral 110 port. If a line on the Peripheral A Port is programmed as an output by the DORA, writing a 0 into the corresponding bit in the ORA causes that line to go low (s 0.4 Vdc);
writing a 1 causes the lineto go high. The lines of the Peripheral
B port are controlled by ORB in the same manner.
Another difference between the PAO-PA7 lines and the PBa
through PB7 lines is that they have three-state capability which
allows them to enter a high impedance state when programmed
to be used as input lines. In addition, data on these lines will be
read properly, when programmed as output lines, even if the data
signals fall below 2.0 Vdc for a "high" state or are above 0.8 Vdc
for a "low" state. When programmed as output, each line can
drive at least a two TTL load and may also be used as a source
of upto 3.2 mA at 1.5 Vdcto directly drive the base of a transistor
switch, such as a Darlington pair.
INTERRUPT STATUS CONTROL (ISCA, ISCB)
The four interrupt/peripheral control lines (CAl, CA2, CBl , CB2)
are controlled by the Interrupt Status Control logic (A, B). This logic
interprets the contents of the corresponding Control Register and
detects active transitions on the interrupt inputs.
Because these outputs are designed to drive transistors directly,
the output data is read directly from the Peripheral Output Register
for those lines programmed to act as inputs.
PERIPHERAL 110 PORTS (PAO-PA7, PBO-PB7)
The final characteristic is the high-impedance input state which
is a function of the Peripheral B push-pull buffers. When the
Peripheral B 110 lines are programmed to act as inputs, the output buffer enters the high impedance state.
The Peripheral A and Peripheral B 110 ports allow the microprocessor to interface to the input lines on the peripheral device
by writing data into the Peripheral Output Register. They also allow
the processor to interface with the peripheral device output lines
by reading the data on the Peripheral Port input lines directly onto
the data bus and into the internal registers of the processor.
DATA BUS BUFFERS (DBB)
The Data Bus Buffers are 8-bit bidirectional buffers used for data
exchange, on the 00-07 Data Bus, between the microprocessor
and the PIA. These buffers are tri-state and are capable of driving a two TTL load (when operating in an output mode) and
represent a one TTL load to the microprocessor (when operating
in an input mode).
Each olthe Peripheral 110 lines can be programmed to act as an
input or an output. This is accomplished by selling a 1 in the corresponding bit in the Data Direction Register for those lines which
are to act as outputs. A 0 in a bit of the Data Direction Register
causes the corresponding Peripheral 110 lines to act as an input.
1-23
Peripheral Interface Adapter (PIA)
R65C21
CONTROL REGISTER A (CRA)
CA2 INPUT MODE (BIT 5
=0)
7
6
5
4
3
2
1
0
IRQA1
FLAG
IRQA2
FLAG
CA21NPUT
MODE SELECT
(=0)
IRQA2
TRANSITION
SELECT
IRQA
ENABLE
FOR IRQA2
DDRA/ORA
SELECT
IRQAl
TRANSITION
SELECT
IRQA
ENABLE
FOR IRQAl
IRQA/IRQA2
CONTROL
CA2 OUTPUT MODE (BIT 5
=
IRQAIIRQA1
CONTROL
1)
7
6
5
4
3
2
1
0
IRQA1
FLAG
0
CA20UTPUT
MODE SELECT
CA2
OUTPUT
CONTROL
CA2
RESTORE
CONTROL
DDRA/ORA
SELECT
IRQAl
TRANSITION
SELECT
IRQA
ENABLE
FORIRQAl
(=1)
CA2
CONTROL
CA2 INPUT OR OUTPUT MODE (BIT 5
Bit 7
1
o
Bit 2
1
o
Bit 1
1
o
Bit 0
1
o
o
= 0 OR 1)
IRQA1 FLAG
A transition has occurred on CAl that satisfies the bit 1 IRQA1 transition polarity criteria. This bit is cleared by a read of Output Register A
or by RES.
No transition has occurred on CAl that satisfies the bit 1 IRQA1 transition polarity criteria.
DATA DIRECTION REGISTER AlOUTPUT REGISTER A SELECT
Select Output Register A.
Select Data Direction Register A.
IRQA1 TRANSITION SELECT
Set IRQA1 Flag (bit 7) on a positive (Iow-te-high) transition of CAl.
Set IRQAl Flag (bit 7) on a negative (high-te-Iow) transition 01 CAl.
IRQA ENABLE FOR IRQAl
Enable assertion of IRQA when IRQA1 Flag (bit 7) is set.
Disable assertion of IRQA when IRQA1 Flag (bit 7) is set.
CA2 INPUT MODE (BIT 5
Bit 6
= 0)
CA2 OUTPUT MODE (BIT 5
IRQA2 FLAG
A transition has occurred on CA2 that satisfies the bit 4
IRQA2 transition polarity criteria. This lIag is cleared by
a read of Output Register A or by RES.
No transition has occurred on CA2 that satisfies the
bit 4 IRQA2 transition polarity criteria.
CA2 MODE SELECT
Select CA2 Input Mode.
Bit 4
IRQA2 TRANSITION SELECT
Set IRQA2 Flag (bit 6) on a positive (Iow-to-high) transition
ofCA2.
Set IRQA2 Flag (bit 6) on a negative (high-te-Iow) transition
ofCA2.
NOT USED
Always zero.
Bit 5
CA2 MODE SELECT
Select CA2 Output Mode.
o
1
1
o
1
o
Bit 3
1
o
Bit 3
1
o
IRQA ENABLE FOR IRQA2
Enable assertion ollRQA when IRQA2 Flag (bit 6) is set.
Disable assertion of IRQA when IRQA2 Flag (bit 6) is set.
Figure 4_
CA2 OUTPUT CONTROL
CA2 goes low when a zero is written into CRA bit 3.
CA2 goes high when a one is written into CRA bit 3.
CA2 goes low on the lirst negative (high-to-Iow) 02 clock
transition following a read of Output Register A.
CA2 returns high as specified by bit 3
=
CA2 READ STROBE RESTORE CONTROL (4
0)
CA2 returns high on the next 02 clock negative
transition following a read 01 Output Register A.
CA2 returns high on the next active CAt transition
following a read 01 Output Register A as specified by
bit 1.
Control Line Operations Summary (1 .of 2)
1-24
= 0)
Bit 6
Bit 4
Bit 5
o
IRQA/IRQAI
CONTROL
Peripheral Interface Adapter (PIA)
R65C21
CONTROL REGISTER B (CRB)
CB2 INPUT MODE (BIT 5
= 0)
7
6
5
4
3
2
I
0
IROBI
FLAG
IROB2
FLAG
CB21NPUT
MODE SELECT
(=0)
IROB2
TRANSITION
SELECT
IROB
ENABLE
FOR IROB2
DDRB/ORB
SELECT
IROBI
TRANSITION
SELECT
IROB
ENABLE
FORIROBI
IROB/IROB2
CONTROL
CB2 OUTPUT MODE (BIT 5
IROBIIROBI
CONTROL
= 1)
7
6
5
4
3
2
1
0
IROBI
FLAG
0
CB20UTPUT
MODE SELECT
(=1)
CB2
OUTPUT
CONTROL
CB2
RESTORE
CONTROL
DDRB/ORB
SELECT
IROBI
TRANSITION
SELECT
IROB
ENABLE
FORIROBI
CB2
CONTROL
CB21NPUT OR OUTPUT MODE (BIT 5
Bit 7
1
o
= 0 OR 1)
IRQBI FLAG
A transition has occurred on CBlthat satisfies the bit 1 IROBI transition polarity criteria. This bit is cleared by a read of Output Register B
or by RES.
No transition has occurred on CBl that satisfies the bit I IROBI transition polarity criteria.
Bit 2
1
DATA DIRECTION REGISTER B/OUTPUT REGISTER B SELECT
Select Output Register B.
Select Data Direction Register B.
Bit I
1
IRQBI TRANSITION SELECT
SetlROBI Flag (bit 7) on a positive (Iow-to-high) transition of CBI.
Set IROBI Flag (bit 7) on a negative (high-to-Iow) transition of CBI.
Bit 0
I
o
IRQB ENABLE FOR IRQBI
Enable assertion of IROB when IROBI Flag (bit 7) is set.
Disable assertion of IROB when IROBI Flag (bit 7) is set.
o
o
CB2 INPUT MODE (BIT 5
Bit 6
1
o
Bit 5
o
IROB/IROBI
CONTROL
= 0)
CB2 OUTPUT MODE (BIT 5
IRQB2 FLAG
A transition has occurred on CB2 that satisfies the bit 4
IROB2 transition polarity criteria. This flag is cleared by
a read of Output Register B or by RES.
No transition has occurred on CB2 that satisfies the
bit 4 IROB2 transition polarity criteria.
Bit 6
NOT USED
Always zero.
Bit 5
I
CB2 MODE SELECT
Select CB2 Output Mode.
Bit 4
I
CB2 OUTPUT CONTROL
CB2 goes low when a zero is written into CRB bit 3.
CB2 goes high when a one is written into CRB bit 3.
CB2 goes Iowan the first negative (high-to-low) 02 clock
transition following a read of Output Register B.
CB2 returns high as specified by bit 3
o
CB2 MODE SELECT
Select CB2 Input Mode.
o
Bit 4
1
o
Bit 3
1
o
IRQB2 TRANSITION SELECT
Set IROB2 Flag (bit 6) on a positive (low-to-high) transition
ofCB2.
Set IROB2 Flag (bit 6) on a negative (high-to-low) transition
ofCB2.
Bit 3
I
o
IRQB ENABLE FOR IRQB2
Enable assertion of IROB when IROB2 Flag (bit 6) is set.
Disable assertion of IROB when IROA2 Flag (bit 6) is sel.
Figure 4_
=
CB2 READ STROBE RESTORE CONTROL (4
0)
CB2 returns high on the next 02 clock negative
transition following a read of Output Register B.
CB2 returns high on the next active CBI transition
following a read of Output Register B as specified by
bit 1.
Control Line Operations Summary (2 of 2)
1-25
= 0)
Peripheral Interface Adapter (PIA)
R65C21
READING THE PERIPHERAL A 1/0 PORT
+ 2.4 Vdc when the Peripheral Output register contains a logic 1.
In this case, the processor will read a 0 from the Peripheral A pin,
even though the corresponding bit in the Peripheral Output
register is a 1.
Performing a Read operation with RSl = 0, RSO = 0 and the Data
Direction Register Access Control bit (CRA-2) = 1, directly transfers the data on the Peripheral A I/O lines to the data bus. In this
situation, the data bus will contain both the input and output data.
The processor must be programmed to recognize and interpret
only those bits which are important to the particular peripheral
operation being performed.
READING THE PERIPHERAL B I/O PORT
Reading the Peripheral B I/O port yields a combination of input
and output data in a manner similar to the Peripheral A port.
However, data is read directly from the Peripheral B Output
Register (ORB) for those lines programmed to act as outputs. It
is therefore possible to load down the Peripheral B Output lines
without causing incorrect data to be transferred back to the
processor on a Read operation.
Since the processor always reads the Peripheral A I/O port pins
instead of the actual Peripheral Output Register (ORA), it is
possible for the data read by the processor to differ from the
contents of the Peripheral Output Register for an output line.
This is true when the I/O pin is not allowed to go to a full
'2 ---------11
RSO, RS1,
CSO, CS1, CS2
PAO-PA7
PBO-PB7
00-07
DATA OUT
CA2
(PULSE OUT)
CAl
CA2
(HAND SHAKE)
Figure 5.
Read Timing Waveforms
1-26
R65C21
Peripheral Interface Adapter (PIA)
D
02
RSD, RS1,
CSD, CS1, CS2
RIW
00-07
OATAIN
PAD-PA7
PBD-PB7
~~~~~~~~~L..t------t-----------
"==~::'::'::'::'~~1'---ir-------t------------
CB2
(PULSE OUT)
CBl
CB2
(HAND SHAKE)
Figure 6.
Write Timing Waveform
1-27
Peripheral Interface Adapter (PIA)
R65C21
SWITCHING WAVEFORMS
(Vee = 5.0 Vde
± 5%, Vss
= 0, T A =
h
to T H, unless otherwise noted)
BUS TIMING
1 MHz
Parameter
4 MHz
3 MHz
2 MHz
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
02 Cycle
!cve
1.0
-
0.5
-
0.33
-
0.25
-
~s
02 Pulse Width
te
450
-
220
-
160
-
110
-
ns
02 Rise and Fall Time
trcI t,c
15
-
10
ns
-
25
-
12
-
Unit
Read
Address Set-Up Time
tACA
140
-
70
-
53
-
35
-
ns
Address Hold Time
tCAA
0
0
-
0
-
0
-
ns
Peripheral Data Set-Up Time
tpCA
300
-
150
-
110
-
75
-
ns
Data Bus Delay Time
tcoA
-
335
-
145
-
105
-
85
ns
Data Bus Hold Time
tHA
20
-
20
-
20
-
20
-
ns
-
70
-
53
-
35
-
ns
0
-
0
-
0
-
ns
90
-
67
-
45
-
ns
-
67
-
45
-
ns
Write
Address Set-Up Time
tACW
140
Address Hold Time
0
RIW Set-Up Time
!cAW
twcw
180
RIW Hold Time
tcww
0
-
Data Bus Set-Up Time
tocw
180
-
90
Data Bus Hold Time
tHw
10
-
10
Peripheral Data Delay Time
tcpw
Peripheral Data Delay Time
to CMOS Level
tCMOS
-
1.0
2.0
0
-
0
10
0
10
ns
ns
0.5
-
0.5
-
0.5
~s
1.0
-
0.7
-
0.5
~s
-
110
PERIPHERAL INTERFACE TIMING
Peripheral Data Set-Up
tpCA
02 Low to CA2 Low Delay
!cA2
02 Low to CA2 High Delay
CAl Active to CA2 High Delay
tAS1
t RS2
02 High to CB2 Low Delay
tCB2
Peripheral Data Valid to CB2 Low Delay
toc
02 High to CB2 High Delay
tAS1
CBl Active to CB2 High Delay
t AS2
CAl, CA2, CBl and CB2
Input Rise and Fall Time
t"t f
300
-
-
1.0
1.0
2.0
1.0
0
-
1.5
-
1.0
-
-
150
-
0.5
0.5
-
0.5
1.0
-
1.0
0.5
0.5
0
-
0.5
0.75
0
0.5
-
0.5
2.0
1.0
-
0.67
1.0
-
1.0
-
1.0
1-28
ns
~s
0.5
-
~
1.0
~s
-
0.5
~s
0.5
-
NOTE: Timing measurements are referenced to and from a low voltage of 0.8 Vdc and a high voltage of 2.0 Vdc.
0.5
75
-
0
-
-
0.37
~s
0.5
~s
0.5
~s
1.0
~s
Peripheral Interface Adapter (PIA)
R65C21
ABSOLUTE MAXIMUM RATINGS*
Symbol
Value
Unit
Supply Voltage
Parameter
Vcc
-0.3 to + 7.0
Vdc
Input Voltage
V'N
VOUT
-0.3 to Vcc +0.3
Vdc
-0.3 to Vcc +0.3
Vdc
Output Voltage
Operating Temperature Range
Commercial
Industrial
TA
Storage Temperature
TSTG
"NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in other sections of this document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
°C
oto
+ 70
-40to +B5
-55to +150
°C
OPERATING CONDITIONS
Symbol
Value
Supply Voltage
Parameter
Vcc
5V ±5%
Temperature Range
Commercial
Industrial
TA
TltoTH
O°C to 70°C
- 40°C to + 85°C
ELECTRICAL CHARACTERISTICS
(Vee
= 5.0 Vdc
± 5%, V55
= 0, T A = TL to T H, unless otherwise noted)
Min.
Typ.3
Max.
Unit2
V'H
+2.0
-
Vcc
V
Input Low Voltage
V'l
-0.3
-
+O.B
Inpu!.!-e~e
I'N
Parameter
Input High Voltage
Current
_
RIW, RES, RSO, RSI, CSO, CS2, CAl, CBI, 02
CSI
Symbol
Input Leakage Current lor Three-State Ott
00-07, PBO-PB7, CB2
ITS'
Input High Current
PAO-PA7, CA2
I'H
Input Low Current
PAO-PA7,CA2
I'l
Output High Voltage
Logic
PBO-PB7, CB2 (Darlington Drive)
V OH
Output Low Voltage
PAO-PA7,CA2,PBO-PB7,CB2
00-07, IROA, IROB
Val
Output High Current (Sourcing)
Logic
PBO-PB7, CB2 (Darlington Drive)
10H
Output Low Current (Sinking)
PAO-PA7,PBO-PB7,CB2,CA2
00-07, IROA, IROB
10l
O~Leakage
-200
±I
±2.5
±IO.O
±2
±IO
-300
-
-2
204
1.5
-
-
-
-3.2
V
p.A
V'N = OV to Vcc
Vcc = 5.25V
~A
V'N = OAV to 2AV
Vcc = 5.25V
~A
V'H = 2.0V
mA
V'l = O.BV
V
Vcc = 4.75V
IlOAD = - 200~A
ILOAD = - 3.2mA
V
Vcc = 4.75V
-
-
+0.4
ILOAD = 3.2 mA
ILOAD = 1.6 mA
-200
-3.2
-1500
-6
-
-
-
~A
mA
-
10FF
-
I
±IO
p.A
Power Dissipation
PD
-
7
10
mW/MHz
Input Capacitance
DO-D7,PAO-PA7,PBO-PB7,CA2,CB2
RNV, RES, RSO, RSI, CSO,CSI, CS2
CAI,CBI;02
C'N
-
-
10
7
20
pF
pF
pF
-
10
pF
-
VOH = 2AV
VOH = 1.5V
Val = 0.4V
3.2
1.6
Current (Ott State)
Test Conditions
mA
mA
IROA,IROB
V OH = 2AV
Vcc = 5.25V
-
-
Output CapaCitance
COUT
Notes:
I. Ail units are direct current (dc) except capacitance.
2. Negative sign indicates outward current flow, positive indicates inward flow.
3. Typical values are shown for Vee = 5.0V and TA = 25°C.
1-29
Vee = 5.0V
V'N = OV
1= 2 MHz
TA = 25°C
D
Peripheral Interface Adapter (PIA)
R65C21
PACKAGE DIMENSIONS
40·PIN CERAMIC DIP'
[ D ]lJ
I-
MILLIMETERS
·1
A
w
H~~LD
G
MIN
MAX
MIN
A
50.29
51.31
1.980
2.020
B
15.11
15.88
0.595
0625
W:=5jn
-.j IM-j
K---J
2.54
4.19
0.100
0.165
D
038
0.53
0.015
0.021
F
0.76
1.27
0.030
0.050
H
4li a
a a a a
0
a
0
2.54
esc
0.76
1.78
0.030
0.070
J
0.20
0.33
0.008
0.013
2.54
4.19
0.100
0.165
0.605
L
14.60
15.37
0.575
M
o·
10"
o·
10"
N
0.51
1.52
0.020
0.060
MILLIMETERS
a a a a a a
0 0 0
a
i1]f
.
B
2oi~
I:VVVVVVVVV~VVVVVVOV:I
1
~f~~
+f~~F
-jGI-
-+0
K
M
INCHES
DIM
MIN
MAX
MIN
MAX
A
51.82
52.32
2.040
2.060
B
13.46
13.97
0.530
0.550
C
3.56
5.08
0.140
0.200
0
038
0.53
0.015
0.021
F
1.02
1.52
0.040
0.060
G
cili
O.100BSC
K
40·PIN PLASTIC DIP
o
MAX
C
G
+
F
INCHES
DIM
2.54
esc
O.100BSC
H
1.65
2.16
0.065
0.085
J
0.20
0.30
0.008
0.012
K
3.30
4.32
0.130 1 0.170
L
15.24 SSC
0.600 sse
M
z·
10'
7'
10'
N
0.51
1.02
0.020
0.040
)
44·PIN PLASTIC LEADED CHIP CARRIER (PLCC)
,"~~g~
1~t:,D2-1 'I
39~
.L !I
~
CORNER
TTf·
lJiL
L
0
INDICATOR
17
2.
~
X
45°
~'uur~~~
~()39
·O~
~
1
~. ~
P,
xr--+
A~
lnn.lIUD
i-ce
CHAM.
11 PINS
h X 45° PER SIDE
3 PlCS EQUAllY
SPACES
-I!-uua:a:a:
RSD
RSl
PA3
PA4
PA5
PA6
PA7
PBD
PBl
PB2
PB3
PB4
PBS
PB6
PB7
CDII'I":I'C")N,....::~~;;~
RS2
RS3
RES
DO
Dl
D2
D3
D4
PA5
PA6
PA7
PBD
NC
PBl
PB2
PB3
PB4
PB5
PB6
05
D6
D7
CBl
CB2
02
CSl
CS2
R/W
Vee
IRQ
40-PtN DIP
0
10
11
12
39
38
37
36
35
34
RS3
NC
RES
DO
01
D2
13
14
15
33
32
31
NC
D3
16
30
29
D5
D6
PIN 1
INOICATOR
17
D4
cocnO
_ _ N ....
N C"\IC"J,O:!,U)CO,...CO
N N N N N N N
f 5 5 Jf~I~'~16 ~ g
NC = NO INTERNAL CONNECTION
Figure 1.
Document No. 29651N87
Latched output and input registers on both I/O ports
S
44-PIN PLCC
R65C22 Pin Assignments
Product Description
1-31
Order No. 2184
Rev. 4, June 1987
o
Versatile Interface Adapter (VIA)
R65C22
ORDERING INFORMATION
MICROPROCESSOR
BUS INTERFACE
Part Number:
R65C22
L
00-07
PAO-PA7
1+---"-- CAt
.2
Temperature Range (Tl to TH):
Blank =
OOC to + 70°C
E = -4O o C to + 85°C
R/W
CSt, CS2
-
PERIPHERAL
INTERFACE
RSO-RS3
Frequency
t = 1 MHz
2 = 2 MHz
3 = 3 MHz
4 = 4 MHz
2
i+---+CA2
R65C22
VIA
i+---+CBt
4
14----.CB2
RES
IRQ
Package
C = 40-Pin Ceramic DIP
P = 40-Pin Plastic DIP
J = 44-Pin Plastic Leaded
Chip Carrier (PLCC)
Figure 2.
PBO-PB7
R65C22 VIA Interface Signals
CHIP SELECTS (CS1, CS2)
Normally, the two chip select lines are connected to the microprocessor address lines. This connection may be direct or
through decoding. To access a selected R65C22 register, CSI
must be high (logic 1) and CS2 must be low (logic 0).
INTERFACE SIGNALS
Figure 1 (on the front page) shows the R65C22 VIA pin assignments and Figure 2 groups the signals by functional interface.
REGISTER SELECTS (RSO-RS3)
RESET (RES)
The Register Select inputs allow the microprocessor to select
one of 16 internal registers within the R65C22. Refer to Table 1
for Register Select coding and a functional description.
Reset (RES) clears all internal registers (except T1 and T2
counters and latches, and the Shift Register (SR». In the RES
condition, all peripheral interface lines (PA and PB) are placed
in the input state. Also, the Timers (Tl and T2), SR and interrupt logic are disabled from operation.
INTERRUPT REQUEST (IRQ)
The system Phase 2 (02) Input Clock controls all data transfers
between the R65C22 and the microprocessor.
The Interrupt Request (IRQ) output signal is generated whenever
an internal Interrupt Flag bit is set and the corresponding Interrupt Enable bit is a Logic 1. The Interrupt Request output is an
open-drain configuration, thus allowing the IRQ signal to be
wire-ORed to a common microprocessor IRQ input line.
REAO/wRITE (RIW)
PERIPHERAL PORT A (PAO-PA7)
INPUT CLOCK (PHASE 2)
Peripheral Data Port A is an 8-line, bidirectional bus for the
transfer of data, control and status information between the
R65C22 and a peripheral device. Each Peripheral Data Port bus
line may be individually programmed as either an input or output
under control of a Data Direction Register. Data flow direction
may be selected on a line-by-line basis with intermixed input and
output lines within the same port. When a "0" is wrillen to any
bit position of the Data Direction Register, the corresponding
line will be programmed as an input. When a "1" is written into
any bit pOSition of the register, the corresponding data line will
serve as an output. Polarity of the data output is determined by
the Output Register, while input data may be latched into the
Input Register under control of the CA 1 line. All modes are program controlled by the microprocessor by way of the R65C22's
internal control registers. Each Peripheral Data Port line represents two TTL loads in the input mode and will drive two standard
TTL loads in the output mode. A typical output circuit for
Peripheral Data Port A is shown in Figure 3.
The direction of the data transfers between the R65C22 and the
system processor is controlled by the RiW line in conjunction
with the CSI and CS2 inputs. When RiW is low (write operation) and the R65C22 is selected, data is transferred from the
processor bus into the selected R65C22 register. When RiW is
high (read operation) and the R65C22 is selected, data is transferred from the selected R65C22 register to the processor bus.
DATA BUS (00-07)
The eight bidirectional Data Bus lines transfer data between the
R65C22 and the microprocessor. During a read operation, the
contents of the selected R65C22 internal register are transferred
to the microprocessor via the Data Bus lines. During a write
operation, the Data Bus lines serve as high impedance inputs
over which data is transferred from the microprocessor to a
selected R65C22 register. The Data Bus lines are in the high
impedance state when the R65C22 is unselected.
1-32
R65C22
Versatile Interface Adapter (VIA)
PORT A CONTROL LINES (CA1, CA2)
output mode. Port B lines are also capable of sourcing 3.2 rnA
at 1.5 Vdc in the output mode. This allows the outputs to directly
drive Darlington transistor circuits. A typical output circuit for
Port B is shown in Figure 3.
Control lines CA 1 and CA2 serve as interrupt inputs or handshake outputs for Peripheral Data Port A. Each line controls an
internal Interrupt Flag with a corresponding Interrupt Enable bit.
CA1 also controls the latching of Input Data on Port A. CA1 is
a high impedance input, while CA2 represents two standard TIL
loads in the input mode. In the output mode, CA2 will drive two
standard TIL loads.
PORT B CONTROL LINES (CB1, CB2)
Control lines CB1 and CB2 serve as interrupt inputs or handshake outputs for Peripheral Data Port B. Like Port A, these two
control lines control an internal Interrupt Flag with a corresponding Interrupt Enable bit. These lines also serve as a serial data
port under control of the Shift Register (SR). Each control line
represents two standard TIL loads in the input mode and can
drive two TIL loads in the output mode. Note that CB1 and CB2
can drive Darlington transistor circuits, because they both will
source 3.2 rnA at 1.5 Vdc. Each line represents two standard
TIL loads in the input mode and will drive two standard TIL
loads in the output mode.
PORT B (PBO-PB7)
Peripheral Data Port B is an S-line, bidirectional bus which is
controlled by an Output Register, Input Register and Data Direction Register in a manner much the same as Data Port A. With
respect to Port B, the output signal on line PB7 may be controiled by Timer 1 while Timer 2 may be programmed to count
pulses on the PB6 line. Port B lines represent two standard TIL
loads in the input mode and will drive two TIL loads in the
Table 1.
Register
Number
1153
0
0
0
1
0
0
0
0
0
2
3
4
5
6
7
B
9
10
11
12
13
14
15
0
0
0
1
1
1
1
1
1
1
1
RS Coding
RS2
RSI
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
Register
Oeslg.
ORB/IRB
ORA/IRA
DDRB
DORA
IISO
0
0
1
R65C22 Register Addressing
TtC·L
T1C·H
T1L-L
0
1
0
1
Tt Low·Order Latches
Tl High·Order Latches
T2 Low·Order Latches
I T2 Low-Order Counter
T2 High·Order Counter
Shift Register
TtL·H
T2C·L
T2C·H
SR
ACR
PCR
0
1
0
1
0
1
ReglsterlDescrlptlon
Write (RiW - LI
Read (RJW - HI
L
Output Register B
I Input Register B
Output Register A
I Input Register A
Data Direction Register B
Data Direction Register A
Tt Low·Order Latches
I Tl Low-Order Counter
Tt High-Order Counter
Auxiliary Control Register
Peripheral Control Register
IFR
IER
ORA/IRA
Interrupt Flag Register
Interrupt Enable Register
Input Register A·
Output Register N
I
NOTE: ·Same as Register 1 except no handshake.
1/0
CONTROL
PBO-PB7,
CB1, CB2
I-r---•• PAO-PA7,
CA2
INPUT DATA ....~_ _ _ _ _ _ _ _.J
a. Port A Data and Control Line Output Circuit
Figure 3.
b. Port B Data and Control Line Output Circuit
Port A and B Output Circuits
1-33
o
R65C22
Versatile Interface Adapter (VIA)
FUNCTIONAL DESCRIPTION
Register bits corresponding to pins which are programmed as
inputs. In this case, however, the output signal is unaffected.
The internal organization of the R65C22 VIA is illustrated in
Figure 4.
Reading a peripheral port causes the contents of the Input
Register (IRA, IRB) to be transferred onto the Data Bus. With
input latching disabled, IRA will always reflect the levels on the
PA pins. With input latching enabled, IRA will reflect the levels
on the PA pins at the time the latching occurred (via CAl).
PORT A AND PORT B OPERATION
The R65C22 VIA has two a-bit bidirectional 1/0 ports (Port A and
Port B) and each port has two associated control lines.
The IRB register operates similar to the IRA register. However,
for pins programmed as outputs there is a difference. When reading IRA, the level on the pin determines whether a "0" or a "1"
is sensed. When reading IRB, however, the bit stored in the output register, ORB, is the bit sensed. Thus, for outputs which have
large loading effects and which pull an output "1" down or which
pull an output "0" up, reading IRA may result in reading a "0"
when a "1" was actually programmed, and reading a "1" when
a "0" was programmed. Reading IRB, on the other hand, will
read the" 1" or "0" level actually programmed, no matter what
the loading on the pin.
Each a-bit peripheral port has a Data Direction Register (DORA,
DDRB) for specifying whether the peripheral pins are to act as
inputs or outputs. A "0" in a bit of the Data Direction Register
causes the corresponding peripheral pin to act as an input. A "1"
causes the pin to act as an output.
Each peripheral pin is also controlled by a bit in the Output
Register (ORA, ORB) ~nd the Input Register (IRA, IRB). When
the pin is programmed as an output, the voltage on the pin is
controlled by the corresponding bit of the Output Register. A "1"
in the Output Register causes the output to go high, and a "0"
causes the output to go low. Data may be written into Output
INTERRUPT
CONTROL
FLAGS
(IFR)
Figures 5 through a illustrate the formats of the port registers.
r----------------IRQ
INPUT LATCH
(IRA)
-ouipui--
-ENASLEDATA
BUS
-OATA-OIF(
DATA
BUS
BUFFERS
(DORA)
PORT A
--------
PORT B
RES
R/W
\12
PORTA
(ORA)
(IER)
LATCH
(Tl L-H)
:
:
1-----,
HANDSHAKE
CONTROL
LATCH
(Tl L-L)
COUNTER 1COUNT-ER
(TlC-H)
1-----------CA1
----~--- CA2
rsSHH;IF~TIR~E~Gil.----~~--------CB1
LJ(~SR:!!.)_j__---4------ CB2
: (T1C-L)
CS1
CHIP
CS2
ACCESS
RSO - - CONTROL
RS1
RS2
RS3
OUTPUT
(ORB)
--------DATA DIR
(DDRB)
Figure 4.
R65C22 VIA Block Diagram
1-34
BUFFERS
(PB)
PORT B
R65C22
Versatile Interface Adapter (VIA)
HANDSHAKE CONTROL OF DATA TRANSFERS
port. This signal normally interrupts the processor, which then
reads the data, causing generation of a "Data Taken" signal.
The peripheral device responds by making new data available.
This process continues until the data transfer is complete.
The R65C22 allows positive control of data transfers between
the system processor and peripheral devices through the operation of "handshake" lines. Port A lines (CA1, CA2) handshake
data on both a read and a write operation while the Port 8 lines
(CB1, CB2) handshake on a write operation only.
In the R65C22, automatic "Read" Handshaking is possible on
the Peripheral A port only. The CA 1 interrupt input pin accepts
the "Data Ready" signal and CA2 generates the "Data Taken;'
signal. The "Data Ready" signal will set an internal flag which
may interrupt the processor or which may be polled under program control. The "Data Taken" signal can either be a pulse
or a level which is set low by the system processor and is cleared
by the "Data Ready" signal. These options are shown in Figure 9
which illustrates the normal Read Handshake sequence.
Read Handshake
Positive control of data transfers from peripheral devices into
the system processor can be accomplished very effectively using
Read Handshaking. In this case, the peripheral device must
generate the equivalent of a "Data Ready" signal to the
processor signifying that valid data is present on the peripheral
REG O-ORB/IRB
REG 1-0RA/IRA
1'1'1'1'1'1' •1 1
0
1' 1-1' 1 1'1' I' 1 1
4
~PBO
~
PB'
PB'
PB'
PB'
PD,
OUTPUT REGISTER
"B" (ORB) OR
INPUT REGISTER
"B" (IRB)
PAl
PA'
OUTPUT REGISTER
"A" (ORA) OR
INPUT REGISTER
"A" (IRA)
PA'
' -_ _ _ _ _ _ _ PA1
PB'
~N
PLN
READ
WRITe
DATA DIRECTION
SELECTION
SELECTION
CORB = ·.,.'(OIlTPUT)
:::
PAl
PA;
PB'
OATA DIRECTION
0
MPU WRITES OUTPUT LEVEL
UPU READS OUTPUT REGISTER
(ORB)
BIT lti ORe PIN LEVEL HAS NO
DDflB - "0" (INPl/Tl
MPU WRITES INTO ORB. BUT
MPU READS INPUT LEVEL ON PB
(INPUT LATCHING DI5ABI.EO)
NO EFFECT ON PIN LEVEL.
PIN
READ
"'M
CORA ..
(OUTPUT)
(INPUT LATCHING DISABLED)
AFFECT
CORA ..
MPUWRITESOUTPUT LEVEL
tORAI
~IM(OIJTPUT)
MPUREAQSIRABITWHICHISTHE
(INPUT LATCHING ENABLED)
LEVEL OF THE PA PIN AT THE TIME
OFTl1E LAST CAl ACTIVE
lNTlL DORB CHANGED
~B="O"(INPl1Tl
TRANSITION
MPU READS LRB BIT, WHICH IS THE
lEVELOFlHE P8 PINATTHE TIME
OF THE LAST CB1 ACTIVE
T1W.1
PB
DISABLE
l ' ENABLE LATCHING
o
1 CONTINUOUS
INTERRUPTS
1 0 TIMED INTERRUPT
EACH TIME T1 IS
LOADED
, 1 CONTINUOUS
INTERRUPTS
ONE SHOT
OUTPUT
SHIFT REGISTER CONTROL
4
J 2 OPERATION
0
T2-0
1 otsHIFT IN UNDER CONTROL OF tl2
1 1 SHIFT IN UNDER CONTROL Of EXT eLK
1 0 otSHiFf OUT FREE RUNNING AT T2 RATE
101 SHIFT OUT UNDER CONTROL OF 12
1 1 0 SHIFT OUT UNDER CONTROL OF tJ2
111 SHIFT OUT UNDER CONTROL OF EXT elK
o
o
o
o
SQUARE
WAVE
OUTPUT
12 TIMER CONTROL
S OPERATION
o TIMED INTERRUPT
1~~~ieTs ~~v:.~:ITHJ
Figure 14.
~~·:;~~~NOER-CONTROiOF
Auxiliary Control Register (ACR)
Timer 1 One-Shot Mode
In the one-shot mode, writing into the T1 L-H has no effect on
the operation of Timer 1. However, it will be necessary to
assure that the low order latch contains the proper data before
initiating the count-down with a "write T1C-H" operation. When
the processor writes into the high order counter (T1 C-H), the
T1 interrupt flag will be cleared, the contents of the low order
latch will be transferred into the low order counter, and the timer
will begin to decrement at system clock rate. If the PB7 output
is enabled, this signal will go low on the falling edge of 02 following the write operation. When the counter reaches zero, the T1
interrupt flag will be set, the IRQ pin will go low (interrupt
enabled), and the signal on PB7 will go high. At this time the
counter will continue to decrement at system clock rate. This
allows the system processor to read the contents of the counter
to determine the time since interrupt. However, the T1 interrupt
flag cannot be set again unless it has been cleared as described in this specification.
The Timer 1 one-shot mode generates a single interrupt for each
timer load operation. As with any interval timer, the delay
between the "write T1 C-H" operation and generation of the processor interrupt is a direct function of the data loaded into the
timing counter. In addition to generating a single interrupt,
Timer 1 can be programmed to produce a single negative pulse
on the PB7 peripheral pin. With the output enabled (ACR7 1)
a "write T1C-H" operation will cause PB7 to go low. PB7 will
return high when Timer 1 times out. The result is a single programmable width pulse.
=
Timing for the R65C22 interval timer one-shot modes is shown
in Figure 15.
I I
WRITE T1C-H
IRQ OUTPUT
PB7 OUTPUT
T1 COUNTER
- r i l l
-----,1-----------1.::1-<-----1----------I
I
N
I
N-l
I
N-3
N-2
I . - - - - N + 1.5
Figure 15.
I
//
o
FFFF
CYCLES------~."11
Timer 1 One-Shot Mode Timing
1-38
N
N-l
I N-2 I
R65C22
Versatile Interface Adapter (VIA)
Timer 1 Free-Run Mode
the time-out can be prevented completely if the processor continues to rewrite the timer before it reaches zero. Timer 1 will
operate in this manner if the processor writes into the high order
counter (TIC-H). However, by loading the latches only, the
processor can access the timer during each down-counting
operation without affecting the time-out in process. Instead, the
data loaded into the latches will determine the length of the next
time-out period. This capability is particularly valuable in the freerunning mode with the output enabled. In this mode, the signal
on PB7 is inverted and the interrupt flag is set with each timeout. By responding to the interrupts with new data for the latches,
the processor can determine the period of the next half cycle
during each half cycle of the output signal on PB7. In this manner,
very complex waveforms can be generated.
The most important advantage associated with the latches in Tl
is the ability to produce a continuous series of evenly spaced
interrupts and the ability to produce a square wave on PB7 whose
frequency is not affected by variations in the processor interrupt
response time. This is accomplished in the "free-running" mode.
In the free-running mode, the interrupt flag is set and the signal
on PB7 is inverted each time the counter reaches zero at which
time the timer automatically transfers the contents of the latch
into the counter (16 bits) and continues to decrement from there.
The interrupt flag can be cleared by writing T1C-H or T1L-H, by
reading T1C-L, or by writing directly into the flag as described
later. However, it is not necessary to rewrite the timer to enable
setting the interrupt flag on the next time-out.
A precaution to take in the use of PB7 as the timer output concerns the Data Direction Register contents for PB7. Both DDRB
bit 7 and ACR bit 7 must be 1 for PB7 to function as the timer
output. If one is 1 and other is 0, then PB7 functions as a normal outpin pin, controlled by ORB bit 7.
All interval timers in the R65C22 are "re-triggerable". Rewriting
the counter will always re-initialize the time-out period. In fact,
1l2.JL....fVl-.,~~
~
WRITE T1C-H
OPERATION ----'!-----f~
I
IRQ OUTPUT
PB7 OUTPUT
i!
I
I
~/
I-
N + 1.5 CYCLES
I
;',!-'------'-----
i'l'
1L--_ __
//
-~.If4'---- N + 2 CYCLES -----1.1
Figure 16. Timer 1 Free-Run Mode Timing
Timer 2 Operation
decrementing again through zero. The processor must rewrite
12C-H to enable setting of the interrupt flag. The interrupt flag
is cleared by reading 12C-L or by writing 12C-H. Timing for this
operation is shown in Figure 18.
Timer 2 operates as an interval timer (in the "one-shot" mode
only), or as a counter for counting negative pulses on the PB6
peripheral pin. A single control bit in the Auxiliary Control Register
selects between these two modes. This timer is comprised of
a "write-only" lower-order latch (12L-L), a "read-only" low-order
counter (T2C-L) and a readiwrite high order counter (T2C-H). The
counter registers act as a 16-bit counter which decrements at
02 rate. Figure 17 illustrates the 12 Latch/Counter Registers.
Timer 2 Pulse Counting Mode
In the pulse counting mode, 12 counts a predetermined number
of negative-going pulses on PB6. This is accomplished by first
loading a number into 12. Writing into 12C-H clears the interrupt flag and allows the counter to decrement each time a pulse
is applied to PB6. The interrupt flag is set when T2 counts down
past zero. The counter will then continue to decrement with each
pulse on PB6. However, it is necessary to rewrite T2C-H to allow
the interrupt flag to set on a subsequent time-out. Timing for this
mode is shown in Figure 19. The pulse must be low on the leading
edge of 02.
Timer '2 One-Shot Mode
As an interval timer, 12 operates in the "one-shot" mode similar
to Timer 1. In this mode, 12 provides a single interrupt for each
"write 12C-H" operation. After timing out, the counter will continue to decrement. However, setting of the interrupt flag is disabled after initial time-out so that it will not be set by the counter
1-39
Versatile Interface Adapter (VIA)
R65C22
REG 9-TIMER 2 HIGH-ORDER LATCH/COUNTER
REG 8-TIMER 2 LOW-ORDER LATCH/COUNTER
l'I'I'i'I 3 1'I'l o l
~
COUNT
VALUE
' -_ _ _ _ 16
25'
'12
1024
COUNT
VALUE
2048
'------409'
' -_ _ _ _ _ 32
L . . - - - - - - S192
L.._ _ _ _ _ _ 64
L--------16384
L.._ _ _ _ _ _ _ 128
'---------32768
WRITE -
8 BITS LOADED INTO T2l0W ORDER
LATCH
REAO -
8 BITS FROM T2 LOW ORDER COUNTER
TRANSFERRED TO MPU. T2 INTERRUPT
WRITE -
8 BITS LOADED INTO T'! HIGH ORDER
COUNTER AlSO,lOW ORDER LATCH
TRANSFERRED TO LOW ORDER
COUNTER IN ADDITION, T2INTERRUPT
FLAG IS RESET
READ -
8 BITS FROM T2 HIGH ORDER COUNTER
flAG IS RESET
TRANSFERRED TO MPU
Figure 17.
Timer 2 (T2) Latch/Counter Registers
WRITE T2C-H
/
IRQ OUTPUT
N
T2 COUNTER
N-'
I
N-2
1------- N +
Figure 18.
. WRITE T2C-H
I
N-3
I
o
'.5 CYCLES
FFFF
I
FFFE
I
FFFD
I
FFFC
------~.I
Timer 2 One-Shot Mode Timing
r--1
OPERATION ----J
1~.----------------7ij~i------------------------
PB6 INPUT -------u--ur-----1,',~i
---.Ur-------
IRQ OUTPUT
T2 COUNTER
-----------------t,',r'------""L____
N
N-'
N-2
Figure 19. Timer 2 Pulse Counting Mode
1-40
o
FFFF
I
Versatile Interface Adapter (VIA)
R65C22
SHIFT REGISTER OPERATION
control shifting in external devices. The time between transitions
of this output clock is a function of the system clock period and
the contents of the low order T2 latch (N).
The Shift Register (SR) performs serial data transfers into and
out of the CB2 pin under control of an internal modul0-8 counter. Serial data transfer in and out of the Shift Register (SR) begin
with the most significant bit (MSB) first. Shift pulses can be
applied to the CBl pin from an external source or, with the proper
mode selection, shift pulses generated internally will appear on
the CBl pin for controlling external devices.
The shifting operation Is triggered by the read or write of the SR
if the SR flag is set in the IFR. Otherwise the first shift will occur
at the next time-out of T2 after a read or write of the SR. The
input data should change before the positive-going edge of CBl
clock pulse. This data is shifted into the shift register during the
02 clock cycle following the positive-going edge of the CBl clock
pulse. After 8 CBl clock pulses, the shift register interrupt flag
will set and IRQ will go low.
The control bits which select the various shift register operating
modes are located in the Auxiliary Control Register. Figure 20
illustrates the configuration of the SR data bits and Figure 21
shows the SR control bits of the ACR.
SR Mode 0 -
SR Mode 2 -
Shift Register Interrupt Disabled
Mode 0 disables the Shift Register interrupt. In this mode the
microprocessor can write or read the SR and the SR will shift
on each CBl positive edge shifting in the value on CB2. In this
mode the SR interrupt Flag is disabled (held to a logic 0).
SR Mode 1 -
Shift In Under Control of T2
In mode 1, the shifting rate is controlled by the low order 8 bits
of T2 (Figure 22). Shift pulses are generated on the CBl pin to
REG 10-SHIFT REGISTER
"l~
REG ll-AUXILIARY CONTROL REGISTER
1+1+1+1,1,1
JJ....L
L
SHIFT
REGISTER
BITS
SHIFT REGISTER
MODE CONTROL
,, ,, ,,
,, ,
,, ,
, ,
,,,
4
3
0
0
NOTES
1. WHEN SHIFTING OUT, BIT 7 IS THE FIRST BIT
OUT AND SIMULTANEOUSLY IS ROTATED BACK
0
0
INTO BIT O.
2
OPERATION
DISABLED
SHIFT IN UNDER CONTROL OF T2
0
SHIFT IN UNDER CONTROL OF 02
0
0
2.WHEN SHIFTING IN, BITS INITIALLY ENTER
BIT 0 AND ARE SHIFTED TOWARDS BIT 7
Figure 20.
Shift In Under IP2 Control
In mode 2, the shift rate is a direct function of the system clock
frequency (Figure 23). CBl becomes an output which generates
shift pulses for controlling external devices. Timer 2 operates
as an independent interval timer and has no effect on SR. The
shifting operation is triggered by reading or writing the Shift
Register. Data is shifted, first into bit 0 and is then shifted into
the next higher order bit of the shift register on the trailing edge
of each 02 clock pulse. After 8 clock pulses, the shift register
interrupt flag will be set, and the output clock pulses on CBl
will stop.
Shift Register
SHIFT IN UNDER CONTROL OF EXT eLK
SHIFT OUT FREE RUNNING AT T2 RATE
SHIFT OUT UNDER CONTROL OF 12
SHIFT OUT UNDER CONTROL OF 02
SHIFT OUT UNDER CONTROL OF EXT eLK
Figure 21.
Shift Register Modes
\12
WRITE OR READ
SHIFT REG
CBl OUTPUT
SHIFT CLOCK
CB2 INPUT
DATA
N2r:!cLES ~- 4-.-JN
+
J1IlIlIlMnIl
+
/~
21
CYCLES
2
1
3
8
XX*xO\tf.('NmOltIXIYllllllllt:r)!lllltlll;Cf)!tt?lx;*Xt<~
I
I
L
Figure 22.
SR Mode 1 -
Shift In Under T2 Control
1-41
o
R65C22
Versatile Interface Adapter (VIA)
SR Mode 3 -
Shift In Under CB1 Control
set by T2. However, in mode 4 the SR Counter does not stop
the shifting operation (Figure 25). Since the Shift Register bit 7
(SRl) is recirculated back into bit 0, the 8 bits loaded into the
shift register will be clocked onto CB2 repetitively. In this mode
the shift register counter is disabled.
In mode 3, external pin CB1 becomes an input (Figure 24). This
allows an external device to load the shift register at its own pace.
The shift register counter will interrupt the processor each time
8 bits have been shifted in. The shift register stops after 8 counts
and must be reset to start again. Reading or writing the Shift
Register resets the Interrupt Flag and initializes the SR counter
to count another 8 pulses.
SR Mode 5 -
Note that the data is shifted during the first system clock cycle
following the positive-going edge of the CB1 shift pulse. For this
reason, data must be held stable during the first full cycle following CB1 going high.
SR Mode 4 - Shift Out Under T2 Control (Free-Run)
Mode 4 is very similar to mode 1 in which the shifting rate is
H
READSR
CBl OUTPUT
SHIFT CLOCK
Shift Out Under T2 Control
In mode 5, the shift rate is controlled by T2 (as in mode 1). The
shifting operation is triggered by the read or write of the SR if
the SR flag is set in the IFR (Figure 26). Otherwise the first shift
will occur at the next time-out of T2 after a read or write of the
SA. However, with each read or write of the shift register the SR
Counter is reset and 8 bits are shifted onto CB2. At the same
time, 8 shift pulses are generated on CB1 to control shifting in
external devices. After the 8 shift pulses, the shifting is disabled,
the SR Interrupt Flag is set and CB2 remains at the last data level.
I
~~---------------------
C B 2
2I3N
4
5
P
6
7
8U T .
l
DATA
1 IRQ
LI_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Figure 23.
SR Mode 2 - Shift In Under 1/12 Control
02
CB2INPUT~~~ggK:I:)Q~~CJ2[:~~~:13:)Q2~X:J[J(~/~ ~
DATA
:
~
I
L
Figure 24.
WRITE SR
SR Mode 3 - Shift In Under CB1 Control
I
~I--+---I---+:-:--::l---+-----j.------!---------
I I
N + 2 CYCLES j<'~-+l-~
CBl OUTPUT - - - - - ;
SHIFT CLOCK
Figure 25.
SR Mode 4 - Shift Out Under T2 Control (Free-Run)
1-42
R65C22
Versatile Interface Adapter (VIA)
SR Mode 6 -
ShiH Out Under 02 Control
Interrupt Flag each time it counts 8 pulses but it does not disable
the shifting function. Each time the microprocessor, writes or
reads the shift register, the SR Interrupt Flag is reset and the
SR counter is initialized to begin counting the next 8 shift pulses
on pin CB1. After 8 shift pulses, the Interrupt Flag is set. The
microprocessor can then load the shift register with the next byte
of data.
In mode 6, the shift rate is controlled by the 02 system clock
(Figure 27).
SR Mode 7 -
ShiH Out Under CB1 Control
In mode 7, shifting is controlled by pulses applied to the CB1
pin by an external device (Figure 28). The SR counter sets the SR
~
~
I~
_ ;..-.
Ii
I
-.n'-,,=~~---+I----t.,;-:-:::=.-::-:::--o----+---II~I
_+1'------
WRITE SR
2CYCLES~
N +
"-../~8
I ,
~
.t.N+2CYCLES
I
2
--'L--.,;3;....-....I!
L..-_---'
r--i
g:~~UTPUT XXXXXXXXXXXXXlO~__....:...._--'X'--_...:2~_-IX'--_3=---I/ P.........;8=-.:t--__
CBl OUTPUT
SHIFT CLOCK
Ii-'
Figure 26.
SR Mode 5 -
Shift Out Under 12 Control
'1su1.n.IuUL.
WRITE SR
CB10UTPUT
SHIFT CLOCK
CB2 OUTPUT
DATA
'ti-U-
IIIIIIII
----11_'
----1:
~jDcI::x"'-+1---=8~_
I
Figure 27.
SR Mode 6 -
Shift Out Under 02 Control
f-t.n.Jl.sl.n..
\12
I
WRITESR
CBl INPUT
SHIFT CLOCK
CB2 OUTPUT
DATA
I
~~---------------~Ir----r-----
I
2
L..-_---'
f
--------------------------------------~
Fv
tRS2~
2.0~V~-----
CA1
"DATA READY"
1----
O.BV
LACTIVE
TRANSITION
Figure 31b.
CA2 Timing for Read Handshake, Handshake Mode
WRITE ORA, ORB
OPERATION
CA2, CB2
"DATA READY"
PA,PB
PERIPHERAL
DATA
~
---IDS---~I
2.0V
O.BV
F--------------------------------
Figure 31c.
CA2, CB2 Timing for Write Handshake, Pulse Mode
1·46
Versatile Interface Adapter (VIA)
R65C22
WRITE ORA, ORB
OPERATION
CA2,CB2
"DATA READY"
O.BV
- t----1DS-----lb
PA, PB
PERIPHERAL
DATA
_
2.0V
._O.BV
1==------1--1
/
CAl, CBI
"DATA TAKEN"
Figure 31d.
PA,PB
PERIPHERAL
INPUT DATA
CONTROL
CA2, CB2 Timing for Write Handshake, Handshake Mode
~2.0V
-f
f
O.BV
~tlL
~~--------------
CAI,CBI
INPUT LATCHING
;2'-
--------
iov
.
J.::::::-IA-L:::::~--H ~::TJVE
TRANSITION
Figure 31e.
Peripheral Data Input Latching Timing
CBI
SHIFT CLOCK
(INPUT OR
OUTPUT)
Figure 311.
Timing for Shift Out with Internal or External Shift Clocking
1·47
Versatile Interface Adapter (VIA)
R65C22
SHIFT DATA
CB2
(INPUT)
~~~~~~~~
2.0V
+-_-+_______________
!'-=-O.;.::8.:.V+_ _ _ _
CBt
SHIFT CLOCK
(INPUT OR
OUTPUT)
SET UP TIME MEASURED TO THE FIRST $2
RISING EDGE AFTER CBt RISING EDGE.
NOTE: SET UP TIMES 'SR. AND 'SR3 MUST BE OBSERVED.
Figure 31 g.
Timing for Shift In with Internal or External Shift Clocking
CBt
SHIFT CLOCK
INPUT
Figure 31 h.
PB6
PULSE COUNT
INPUT
'[""
External Shift Clock Timing
rt
2.0V
O.8V. -
"pw-----i
I------.,Ps
I
COUNTER T2
DECREMENTS
HERE
Figure 311.
Pulse Count Input Timing
1·48
R65C22
Versatile Interface Adapter (VIA)
BUS TIMING WAVEFORMS
\12
CLOCK
REGISTER
SELECTS,
CHIP
SELECTS,
R/W
~;~;~~1\",,;;~-+__-+__+"":::';'::':~>~i~~~I~~~~
PERIPHERAL
DATA
2.0Y
DATA BUS
r----'\.I
-----------<.
O.BY
Figure 32a.
~
2.0Y
_ _ _". O.BY
Read Timing Waveforms
tcv
r--tPWH-==!
112
/
CLOCK
2.4V
2.4V
O.4V
-- -
I- tACW -
tCAW
2.0Y
2.0V
CHIP SELECTS,
REGISTER SELECTS
2.4V
O.BY
O.SY.
I- tocw R/W
\
2.0Y
O.BY
-
!--IHW
2.0Y
DATA
BUS
O.SY
r- Icpw2.0Y
PERIPHERAL
DATA
:>0000"I
Figure 32b.
Write Timing Waveforms
1-49
O.BY
Versatile Interface Adapter (VIA)
R65C22
ABSOWTE MAXIMUM RATINGS·
Symbol
Value
Unit
Supply Voltage
Parameter
Vee
-0.3 to + 7.0
Vdc
Input Voltage
V,N
- 0.3 to Vee + 0.3 Vdc
Output Voltage
VOUT
- 0.3 to Vee + 0.3 Vdc
Operating Temperature
Commercial
Industrial
TA
Storage Temperature
TSTG
"NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the other sections of this document is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
°C
o to
+70
-40 to +85
-55 to + 150
°C
OPERATING CONDITIONS
Parameter
Symbol
Value
Supply Voltage
Vec
5V ±5%
Temperature Range
Commercial
Industrial
TA
TL to TH
O°C to 70°C
- 40°C to + 85°C
ELECTRICAL CHARACTERISTICS
Nee = 5.0 Vdc ±5%, Vss = 0, TA = h to TH,
unless otherwise noted)
Parameter
Symbol
Input High Voltage
Logic
O2
V,H
Input Low Voltage
Logic
O2
Input Leakage Current
RNY,RES, RSO, RS1,RS2, RS3,CS1,CS2,CA1,02
V,L
Min.
Typ.'
Max.
Unit'
Test Conditions
V
+2.0
+2.4
-
Vee
Vee
-0.3
-0.4
-
+0.8
+0.4
liN
-
±1
±2.5
pA
Y'N = OV to Vee
Vee = 5.25V
Input Leakage Current lor Three-State Off
00-07
Input High Current
PAO-PA7,CA2, PBO-PB7,CB1, CB2
ITSI
-
±2
±10
pA
Y,N = 0.4V to 2.4V
Vee = 5.25V
pA
V,H = 2.4V
Input Low Current
PAO-PA7,CA2, PBO-PB7,CB1, CB2
I,L
V,L = 0.4V
Output High Voltage
All outputs
PBO-PB7, CBl and CB2 (Darlington Drive)
VOH
Output Low Voltage
PAO-PA7, CA2, PBO-PB7, CB1, CB2,
00-07, IRQ
VOL
Output High Current (Sourcing)
Logic
PBC-PB7, CBl and CB2 (Darlington Drive)
10H
Output Low Current (Sinking)
10L
3.2
-
Output Leakage Current (Off State)
IRQ
10FF
-
1
±10
Power Dissipation
Po
-
7
10
mW/MHz
Input Capacitance
DO-D7,PAO-PA7,CA1,CA2,PBO-PB7,CB1,CB2
RNY, RES, RSO, RS1, RS2, RS3,CS1,CS2,
02
C'N
-
-
10
7
20
pF
pF
pF
-
10
pF
I'H
V
-200
2.4
1.5
-200
-3.2
-
-
COUT
Notes: ,
1. All units are direct current (DC) except lor capacitance.
2. Negative sign indicates outward current Ilow, positive indicates inward flow.
3. Typical values shown for Vee = 5.0V and TA = 25°C.
Output Capacitance
1-50
-400
-
-2
-2.6
mA
-
-
V
V
+0.4
V
-1500
-6
-
pA
mA
VOH = 2.4V
V OH = 1.5V
-
mA
VOL = 0.4V
pA
VOH = 2.4V
Vee = 5.25V
Vee = 4.75V
ILOAD = 200 pA
ILOAD2 = - 3.2 mA
Vee = 4.75V
ILOAD = 3.2 mA
ILOAD = 1.6 mA
Vee = 5.0V
Y'N = OV
1= 2 MHz
TA = 25°C
Versatile Interface Adapter (VIA)
R65C22
PACKAGE DIMENSIONS
40-PIN CERAMIC DIP
[: D
I·
]JJ
DIM
·1
A
~n
H~~LD
50.29
5131
G-ll-
K_ _J
M-j
B
15.11
1588
0.595
0.625
254
4.19
0.100
0165
0
0.38
053
0015
0021
F
0.76
1.27
0.030
esc
--jGi-
F ...... 0
K
178
0.030
0070
J
0.20
0.33
0.008
0.013
K
2.54
4.19
0100
0.165
0605
L
14.60
15.37
0.575
M
0'
0'
100
N
0.51
10'
152
0.020
0060
INCHES
DIM
MIN
MAX
MIN
A
51.28
52.32
2.040
MAX
2.060
B
13.72
14.22
0.540
0.560
C
3.55
5.08
0.140
0.200
0
0.36
0.51
0.014
0.020
F
1.02
1.52
0,040
G
M
0.050
O.100BSC
0.76
MILLIMETERS
~~
1Hj-
254
H
40-PIN PLASTIC DIP
~:::::: ::~: : : : :::~I'I
INCHES
MIN
MAX
1980 2.020
C
G
t
rfF
MILLIMETERS
MAX
MIN
A
2.54
esc
0.100
0.060
esc
1.85
2.16
0.065
0.085
J
0.20
0.30
0.008
0.012
K
3.30
4.32
0.130
L
15.24
H
esc
0.600
0.170
esc
M
7'
10'
7'
10'
N
0.51
1.02
0.020
0.040
44-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
,-~g~
I~t:,
lTr
39-~
JJ& ""' ,I
CORNER
02--1 '\
?
6
~
L
INDICATOR
-17
2.
~
CHAM.J " 45·
~il
J--+
·Oc;
'~
c;
1
A~
~
~6~
1nn. i1.rtnM
CHAM.
11 PINS
h " 45· PER SIDE
3 PLCS EQUALLY
SPACES
~~
:,(~
..jfcb
MILLIMETERS
i
MIN
MAX
MIN
A
4.14
4.39
0.163
A1
1.37
1.47
0.054
A2
2.31
2.46
0.091
0
01
02
DO
.
h
J
~~.
R
SECTION A·A
TYP FOR BOTH AXIS (EXCEPT FOR BEVELED EDGE)
EJECTOR PIN MARKS
4 PLCS BOTTOM OF
PACKAGE ONLY
(TYPICAL)
BOTTOM VIEW
1·51
INCHES
DIM
b
SIDE VIEW
TOP VIEW
-I I-ce
SEATING PLANE
b!
_uuuuuuuuuuu
20"
~
V
02
R
Rl
0.457 TVP
MAX
0.173
0.058
0.097
0.018 TVP
17,45
17.60
0.687
16.46
16.56
0.648
0.652
12.62
12.78
0.497
0.503
0.693
15.75 REF
0.620 REF
1.27 Bse
0.050 Bse
1.15 TYP
0.045 TVP
0.25 TVP
0.010 TVP
45° TVP
45°TYP
0.89 TYP
0.035 TVP
0.25 TVP
0.010 TVP
Versatile Interface Adapter (VIA)
R65C22
R65NC22/R65C22 DIFFERENCES
R65C22
1. Register select lines are decoded during
R65NC22
02.
1. Register select lines are decoded during 02 only if CS2 is active
low.
2. CBl must not change during last 100 ns of 02. CBl must have a
pulse width greater than one period.
2. CBl can change anytime but is sampled only during 02. CBl must
have a pulse greater than one period.
3. PBD-PB7 and CB1, CB2 have active pull·ups.
3. PBO-PB7 and CB1, CB2 have passive pull ups (=3 KIl).
4. PBD-PB7, CBl and CB2 represent two standard TTL loads in the
Input mode and will drive two standard TTL loads in the output mode.
4. PBO-PB7, CBl and CB2 represent one standard TTL load in the input
mode and will drive one standard TTL load in the output mode.
1·52
R65NC22
'1'
R65NC22
Versatile Interface Adapter (VIA)
Rockwell
DESCRIPTION
FEATURES
The R65NC22 Versatile Interface Adapter (VIA) is a very flexible I/O control device. In addition, this device contains a pair
of very powerful 16-bit interval timers, a serial-to-parallel/parallelto serial shift register and input data latching on the peripheral
ports. Expanded handshaking capability allows control of bidirectional data transfers between VIA's in multiple processor systems.
• Low power CMOS N-well silicon gate technology
• Fully compatible with NMOS 6522 devices
• Two 8-bit bidirectional I/O ports
• Two 16-bit programmable timer/counters
• Serial bidirectional peripheral I/O
The R65NC22 includes functions for programmed control of up
to two peripheral devices (Ports A and B). These two program
controlled 8-bit bidirectional peripheral I/O ports allow direct interfacing between the microprocessor and selected peripheral
units. Each port has input data latching capability. Two programmable Data Direction Registers (A and B) allow selection of data
direction (input or output) on an individual line basis.
• TTL compatible peripheral control lines
• Expanded "handshake" capability allows positive control
of data transfers between processor and peripheral
devices.
• Latched output and input registers on both I/O ports
The R65NC22 also has two programmable 16-bit Interval
Timer/Counters with latches. Timer 1 may be operated in a OneShot Interrupt Mode with interrupts on each count-to-zero, or
in a Free-Run Mode with a continuous series of evenly spaced
interrupts. Timer 2 functions as both an interval and pulse
counter. Serial data transfers are provided by a serial-toparallel/parallel-to-serial shift register. Application versatility is
further increased by various control registers, including-the
Interrupt Flag Register, the Interrupt Enable Register, the
Auxiliary Control Register and the Peripheral Control Register.
CAl
CA2
RSO
RSl
RS2
RS3
RES
DO
01
02
03
04
05
06
07
.2
CSl
CS2
RNi
IRQ
Vs.
PAO
PAl
PA2
PA3
PA4
PAS
PA6
PA7
PBO
PBl
PB2
PB3
PB4
PBS
PBS
PB7
CBl
CB2
Vee
40-PIN DIP
• Commercial and industrial temperature range versions
• Single + 5 Vdc power requirement
• Wide variety of packages
- 40-pin plastic and ceramic DIP
- 44-pin plastic leaded chip carrier (PLCC)
;~~c!l =c~~u;:;;
a.a.o..Q,Q,>uua:a:a::
m
PAS
PA6
PA7
PBO
NC
PBl
PB2
PB3
PB4
PBS
PB6
~
•
~ N
~ :
~ ~ ;
~
0
39
38
37
36
35
34
33
32
31
30
29
PIN 1
INDICATOR
10
11
12
13
14
15
16
17
~
~
0
,...
...
N
~
N
~
•
~
~
~
RS3
NC
RES
DO
01
02
NC
03
04
05
06
m
__ NNNNNNNNN
U
U
10 I~ IN ...
N ,...
f~5~Z~a::~~-C
NC = NO INTERNAL CONNECTION
Figure 1.
Document No. 29651 N98
• 1, 2, 3, and 4 MHz operation
44-PIN PLCC
R65NC22 Pin Assignments
Product Description
1-53
Order No. 2198
June 1987
Versatile Interface Adapter (VIA)
R65NC22
ORDERING INFORMATION
r
MICROPROCESSOR
BUS INTERFACE
Part Number:
R65NC22
,_,,'··_0,·'",'
PERIPHERAL
INTERFACE
00-07
Blank =
O·C to + 70·C
E = -40·C to + 85·C
PAO-PA7
...- - - - C A 1
'2
Frequency
1 = 1 MHz
2 = 2 MHz
3 = 3 MHz
4 = 4 MHz
L-_ _ _ Package
RIW
CS1, CS2
RSO-RS3
R65NC22 ...- - -.... CA2
2
VIA
4
. .- - -.... CB1
14----.CB2
RES
C = 40-Pin Ceramic DIP
P = 40-Pin Plastic DIP
J = 44-Pin Plastic Leaded
Chip Carrier (PLCC)
IRQ
INTERFACE SIGNALS
Figure 2.
Figure 1 (on the front page) shows the R65NC22 VIA pin assignments and Figure 2 groups the signals by functional interface.
PBO-PB7
R65NC22 VIA Interface Signals
REGISTER SELECTS (RSO-RS3)
The Register Select inputs allow the microprocessor to select
one of 16 internal registers within the R65NC22. Refer to Table 1
for Register Select coding and a functional description. The RS
lines are decoded only if CS2 is low.
RESET (RES)
Reset (RES) clears all internal registers (except T1 and T2
counters and latches, and the Shift Register (SR) ). In the RES
condition, all peripheral interface lines (PA and PB) are placed
in the input state. Also, the Timers (T1 and T2), SR and interrupt logic are disabled from operation.
INTERRUPT REQUEST (IRQ)
The Interrupt Request (IRQ) output Signal is generated whenever
an internal Interrupt Flag bit is set and the corresponding Interrupt Enable bit is a Logic 1. The Interrupt Request output is an
open-drain configuration, thus allowing the IRQ signal to be
wire-ORed to a common microprocessor IRQ input line.
INPUT CLOCK (PHASE 2)
The system Phase 2 (02) Input Clock controls all data transfers
between the R65NC22 and the microprocessor.
PORT A DATA LINES (PAO-PA7)
Peripheral Data Port A is an 8-line, bidirectional bus for the
transfer of data, control and status information between the
R65NC22 and a peripheral device. Each Peripheral Data Port
bus line may be individually programmed as either an input or
output under control of a Data Direction Register. Data flow direction may be selected on a line-by-Iine basis with intermixed input
and output lines within the same port. When a "0" is written
to any bit position of the Data Direction Register, the corresponding line will be programmed as an input. When a "1" is written
into any bit position of the register, the corresponding data line
will serve as an output. Polarity of the data output is determined
by the Output Register, while input data may be latched into the
Input Register under control of the CA1 line. All modes are program controlled by the microprocessor by way of the R65NC22's
internal control registers. Each Peripheral Data Port line represents two TIL loads in the input mode and will drive two standard
TIL loads in the output mode. A typical output circuit for
Peripheral Data Port A is shown in Figure 3.
REAOIWRITE (RM)
The direction of the data transfers between the R65NC22 and
the system processor is controlled by the Rm line in conjunction
with the CS1 and CS2 inputs. When Rm is low (write operation) and the R65NC22 is selected, data is transferred from the
processor bus into the selected R65NC22 register. When Rm is
high (read operation) and the R65NC22 is selected, data is transferred from the selected R65NC22 register to th~ processor bus.
DATA BUS (00-07)
The eight bidirectional Data Bus lines transfer data between the
R65NC22 and the microprocessor. During a read operation, the
contents of the selected R65NC22 internal register are transferred to the microprocessor via the Data Bus lines. During a
write operation, the Data Bus lines serve as high impedance
inputs over which data is transferred from the microprocessor
to a selected R65NC22 register. The Data Bus lines are in the
high impedance state when the R65NC22 is unselected.
PORT A CONTROL LINES (CAt, CA2)
Control lines CA1 and CA2 serve as interrupt inputs or handshake outputs for Peripheral Data Port A. Each line controls an
internal Interrupt Flag with a corresponding Interrupt Enable bit.
CA1 also controls the latching of Input Data on Port A. CA1 is
a high impedance input, while CA2 represents two standard TIL
loads in the input mode. In the output mode, CA2 will drive two
standard TIL loads.
CHIP SELECTS (CSt, CS2)
Normally, the two chip select lines are connected to the microprocessor address lines. This connection may be direct or
through decoding. To access a selected R65NC22 register, CS1
mu!}t be high (logic 1) and CS2 must be low (logic 0).
1-54
Versatile Interface Adapter (VIA)
R65NC22
PORT B DATA LINES (PBO-PB7)
drive Darlington transistor circuits. A typical output circuit for
Port B is shown in Figure 3.
Peripheral Data Port B is an S-line, bidirectional bus which is
controlled by an Output Register, Input Register and Data Direction Register in a manner much the same as Data Port A. With
respect to Port B, the output signal on line PB7 may be controlled by Timer 1 while TImer 2 may be programmed to count
pulses on the PB6 line. Port B lines represent one standard TTL
load in the input mode and will drive one TTL load in the output
mode. Port B lines are also capable of sourcing 3.2 rnA at
1.5 Vdc in the output mode. This allows the outputs to directly
PORT B CONTROL LINES (CB1, CB2)
Table 1.
Register
Number
0
I
2
3
4
5
6
7
B
9
10
II
12
13
14
IS
NOTE: ·Same
110
1'153
0
0
a
a
a
a
a
0
I
I
I
I
I
I
I
I
RS Coding
R52
RS1
0
0
0
0
a
I
a
I
I
a
I
a
I
I
I
I
a
0
0
0
I
I
I
I
Register/Description
Write (RIW - L)
Read lRIW - H)
~
Input Register B
Output Register B
Input Register A
Output Register A
Data Direction Register B
Data Direction Register A
Tl Low-Order Counter
Tl Low-Order Latches
Tl High-Order Counter
I
I
ORNIRA
DDRB
DORA
T1C-L
T1C-H
T1L-L
T1L-H
T2C-L
T2C-H
a
I
a
I
0
I
0
I
0
I
I
Tl Low-Order Latches
Tl High-Order Latches
T2 Low-Order Counter
T2 Low-Order Latches
T2 High-Order Counter
Shill Register
1
SR
ACR
PCR
IFR
IER
ORNIRA
0
I
0
I
Auxiliary Control Register
Peripheral Control Register
Interrupt Flag Register
Interrupt Enable Register
Output Register A·
Input Register A·
I
as Register I except no handshake.
~p--_ _
•
CONTROL
R65NC22 Register Addressing
Register
Deslg.
ORBIIRB
RSO
0
I
0
0
I
I
0
0
I
I
Control lines CB1 and CB2 serve as interrupt inputs or handshake outputs for Peripheral Data Port B. Like Port A, these two
control lines control an internal Interrupt Flag with a corresponding Interrupt Enable bit. Similar to CA 1, CB1 controls the latching of input data on Port B. These lines also serve as a serial
data port under control of the Shift Register (SR). Each control
line represents one standard TTL load in the input mode and
can drive one TTL load in the output mode.
110
PAO-PA7,
CA2
t-r--...... PBa-PB7
CONTROL
INPUT DATA
a. Port A Data and Control Line Output Circuit
b. Port B Data Line Output Circuit
c. Port B Control Line Output Circuit
Figure 3.
Port A and
1-55
B Output Circuits
o
Versatile Interface Adapter (VIA)
R65NC22
FUNCTIONAL DESCRIPTION
Register bits corresponding to pins which are programmed as
inputs. In this case, however, the output signal is unaffected.
The internal organization of the R65NC22 VIA is illustrated in
Figure 4.
Reading a peripheral port causes the contents of the Input
Register (IRA, IRB) to be transferred onto the Data Bus. With
input latching disabled, IRA will always reflect the levels on the
PA pins. With input latching enabled, IRA will reflect the levels
on the PA pins at the time the latching occurred (via CAl).
PORT A AND PORT B OPERATION
The R65NC22 VIA has two a-bit bidirectional I/O ports (Port A
and Port B) and each port has two associated control lines.
The IRB register operates similar to the IRA register. However,
for pins programmed as outputs there is a difference. When reading IRA, the level on the pin determines whether a "0" or a "1"
is sensed. When reading IRB, however, the bit stored in the output register, ORB, is the bit sensed. Thus, for outputs which have
large loading effects and which pull an output' '1" down or which
pull an output "0" up, reading IRA may result in reading a "0"
when a "1" was actually programmed, and reading a "1" when
a "0" was programmed. Reading IRB, on the other hand, will
read the "1" or "0" level actually programmed, no matter what
the loading on the pin.
Each a-bit peripheral port has a Data Direction Register (DORA,
DDRB) for specifying whether the peripheral pins are to act as
inputs or outputs. A "0" in a bit of the Data Direction Register
causes the corresponding peripheral pin to act as an input. A "1"
causes the pin to act as an output.
Each peripheral pin is also controlled by a bit in the Output
Register (ORA, ORB) and the Input Register (IRA, IRB). When
the pin is programmed as an output, the voltage on the pin is
controlled by the corresponding bit of the Output Register. A "1"
in the Output Register causes the output to go high, and a "0"
causes the output to go low. Data may be written into Output
Figures 5 through a illustrate the formats of the port registers.
r--------------------------------IRQ
INTERRUPT
CONTROL
FLAGS
(IFR)
INPUT LATCH
(IRA)
-OUTPUT--
-ENASLeDATA
BUS
DATA
BUS
BUFFERS
-OATXOlif
(DORA)
PERIPHERAL
(PCR)
r-:P:O:R:T~A~14-----------------CAl
. - - - - - - - - - - - - - CA2
-------- 1----,
AUXILiARY
(ACR)
FUNCTION
CONTROL
RES
RIW
.2
CSl
CHIP
CS2
ACCESS
RSO - - CONTROL
RSl
RS2
PORTA
(ORA)
(IER)
(n L-H)
i
PORT B
LATCH
(n L-L)
CQUNTERic'Q-UtiTER
(n C-H)
HANDSHAKE
CONTROL
rsSiHHii IFT'TiRRiEEiGil _____.j...L_______ CBl
L-~(~S~R)~-t----+---------CB2
: (n Col)
TIMER 1
INPUT LATCH
(IRB)
-------OUTPUT
(ORB)
RS3
-OATA-OIR(DDRB)
Figure 4.
R65NC22 VIA Block Diagram
1-56
BUFFERS
(PB)
PORT B
Versatile Interface Adapter (VIA)
R65NC22
HANDSHAKE CONTROL OF DATA TRANSFERS
port. This signal normally interrupts the processor, which then
reads the data, causing generation of a "Data Taken" signal.
The peripheral device responds by making new data available.
This process continues until the data transfer is complete.
The R65NC22 allows positive control of data transfers between
the system processor and peripheral devices through the operation of "handshake" lines. Port A lines (CA1, CA2) handshake
data on both a read and a write operation while the Port B lines
(CB1, CB2) handshake on a write operation only.
In the R65NC22, automatic "Read" Handshaking is possible
on the Peripheral A port only. The CA1 interrupt input pin accepts
the "Data Ready" signal and CA2 generates the "Data Taken"
signal. The "Data Ready" signal will set an internal flag which
may interrupt the processor or which may be polled under program control. The "Data Taken" signal can either be a pulse
or a level which is set low by the system processor and is cleared
by the "Data Ready" signal. These options are shown in Figure 9
which illustrates the normal Read Handshake sequence.
Read Handshake
Positive control of data transfers from peripheral devices into
the system processor can be accomplished very effectively using
Read Handshaking. In this case, the peripheral device must
generate the equivalent of a "Data Ready" signal to the
processor signifying that valid data is present on the peripheral
REG O-ORB/IRB
REG 1-0RAlIRk
PBO
PAO
PBl
P02
L..._ _ _ P03
' - - - - - PB4
L..._ _ _ _ _ POS
PAl
OUTPUT REGISTER
PA'
"B" (ORB) OR
INPUT REGISTER
"B" (IRB)
'----PA3
L..._ _ _ _ PA'
' -_ _ _ _ _ PAS
' - - - - - - - - PB.
OUTPUT REGISTER
"A" (ORA) OR
INPUT REGISTER
"A" (IRA)
' - - - - - - - PA.
' -_ _ _ _ _ _ _ PA7
' -_ _ _ _ _ _ _ _ P07
~N
CATA DIRECTION
~N
R.",
OORB - "'''(OUTPUT}
MPUWRJTESOUTPUTLEVEl
MPU READS OUTPUT REGISTER
(ORBI
BlTI", OflO PIN LEVEL HAS NO
AFFECT
00R8 • '1r IINPlIJ)
(INPUT LATCHING DISABLED)
MPU WRITES INTO ORB. BUT
NO EfFECT ON PIN LEVEL.
MPU READS INPUT LEVEL ON PB
PIN
R.'"
OATA DlRECTlON
SELECTION
SElECTION
ODAA •
M," tOUTPUTl
MPU WRITES OVTPUT LEVEL.
(INPUT LATCHING DISABlEDI
DORA •
"1~
,ORA)
(OUTPUT)
MPU READS IRA BIT WHICH 15 THE
LEV1:L OF THE PA PIN ATTHE TlME
OF THE LAST CAl ACTlV1:
(INPUT LATCHING ENABLED)
UNTIL DORD CHANGED
00R8 - '''CnINPlIJ)
(INPUT LATCHING ENA8LEDI
MPUReADSIRBBJ'T, WHICHISTHE
LEVEL OF THE PB PIN ATTHE TIME
DORA • "0" (INPUT)
(INPUT
Of' TliE lAST CBI ACTIVE
TRANSITION
LATOtING DISABLED)
MPU WRITES INTO ORA. BUT
NO EFFECT ON PIN L.EV1:L.
UNTIL. DORA CHANGED
DORA • ''0'' (INPUT)
Output Register B (ORB), Input Register B (IRB)
Figure 6.
Output Register A (ORA), Input Register A (IRA)
REG 2-DDRB
REG3-DDRA
'71.~""'f§~~:
l'I.~I'I'lr~~
!
!
P04
DATA DIRECTION
REGISTER "B" (DDRB)
I
I
PB.
' -_ _ _ _ _ _ _ _ PB7
"0"
~
ASSOCIATED PB PIN IS AN INPUT
DATA DIRECTION
REGISTER "A" (DDRA)
ASSOCIATED PB PIN IS AN OUTPUT
WHOSE LEVEL IS DETERMINED BV
ORB REGISTER BIT
Data Direction Register B (DDRB)
PA.
________________ PA7
"0"
ASSOCIATED PA PIN IS AN INPUT
(HIGH IMPEDANCE)
","
ASSOCIATED PA PIN IS AN OUTPUT
WHOSE lEVEL IS DETERMINED BY
ORA REGISTER BIT
(HIGH IMPEDANCE)
Figure 7.
PA4
PAS
PBS
","
TRANsmON
Ml'U READS LEV!L ON PA PIN
MPU READS IRA BIT. WHICH IS THE
LEVEL OF THE PA PIN AT THE TIME
OF THE LAST CAl ACTIVE
TRANSITlON
(INPUT LATCHING ENABLED)
Figure 5.
MPU ReADS LEVEL. ON PA PIN
Figure 8.
1-57
Data Direction Register A (DORA)
Versatile Interface Adapter (VIA)
R65NC22
02 JL.SLJL....rL~JL...J""""1J"L.
~~"''''
IRQ OUTPUT
READ IRA OPERATION
"DATA TAKEN"
HANOSHAKE MODE
(CA2)
"DATA TAKEN'.'
PULSE MODE
(CA2)
fl/1
WR"r'%Z0Y
"
I~
I
I
'I'
~
Il
'""1---
/I
II
1I
i
11
•
II
I
11
1-1- - -
11'--------
~
Figure 9.
Read Handshake Timing (Port A Only)
Write Handshake
The sequence of operations which allows handshaking data from
the system processor to a peripheral device is very similar to
that described for Read Handshaking. However, for Write Hand·
shaking, the R65NC22 generates the "Data Ready" signal and
the peripheral device must respond with the "Data Taken" signal. This can be accomplished on both the PA port and the PB
port on the R65NC22. CA2 or CB2 act as a "Data Ready" output in either the handshake mode or pulse mode and CA1 or
CB1 accept the "Data Taken" signal from the peripheral device,
setting the interrupt flag and clearing the "Data Ready" output.
This sequence is shown in Figure 10.
REG 12-PERIPHERAL CONTROL REGISTER
C82CONTROl~
7 6 S OPERATION
0 0 INPUT NEGATIVE ACTIVE EDGE
0 1 INDEPENDENT INTERRUPT
o
o
LJ
AI LATCH/INTERRUPT CONTROL
O· NEGATIVE ACTIVE EDGE
1
INPUT NEGATIVE EOaE"
~
: ~ ::~~!:~~~~~~NATCET~~t~
INPUT POSITIVE EDGE'
I 0 0 HANDSHAKE OUTPUT
1 0 1 PULSE OUTPUT
Latching
~ ~ ~ ~~:HOO~T:pUUTT
The PA port and the PB port on the R65NC22 can be enabled
in the Auxiliary Control Register (Figure 14) to be latched by their
individual port control lines (CA1, CB1). Latching is selectable
to be on the rising or falling edge of the signal at each individual port control line. Selection of operating modes for CA 1, CA2,
CB1 and CB2 is accomplished by the Peripheral Control Registor (Figure 11).
---
CBI LATCH/INTERRUPT CONTROL -
I~: ~~~~:~~~~~~~~EE~~~E I
POSITIVE ACTIVE EDGE
J 2 1 OPERATION
o
o
0 0 INPUT NEGATIVE ACTIVE EDGE
0 1 INDEPENDENT INTERRUPT
INPUT NeGATIVE EDGE'
D 1 0 INPUT PO::\TIVE ACT\\I(:-EOG"E"
o
1 1 INDEPENDENT INTERRUPT
INPUT POSITIVE EDGE'
1 0 0 HANDSHAKE OUTPUT
1 0 1 PULSE OUTPUT
I I 0 lOW OUTPUT
\ 1 1 HIGH OUTPUT
"SEE NOTE IN FIGURE 29
Figure 11.
Peripheral Control Register (PCR)
.2 JL.JL....rl....1I~1I.IL...r1...S""1
WRITE ORA, ORB
OPERATION
"DATA READY"
HANDSHAKE
MODE
I
I
I
,
II~
II=R=
~'1-'_ _ _ _-'
,
,..---·11-/1----1------11
I
~II
I
( ~~~~,
DATA READY - - - - - ,
PULSE MODE
~
;f!'~iJ~~EN
IRQ OUTPUT
t?/Z///ZZZlf22Z?J
/I
I
---------Ilf----iL_____ II_ _ _ _--JrFigure 10.
Write Handshake Timing
1-58
I
I
CA2CONTROl
Versatile Interface Adapter (VIA)
R65NC22
COUNTER/TIMERS
disables any further interrupts and automatically transfers the
contents of the latches into the counter and continues to decrement. In addition, the timer may be programmed to invert the
output signal on peripheral pin PB7 each time it "times-out".
Each of these modes is discussed separately below.
There are two independent 16-bit counter/timers (called Timer 1
and TImer 2) in the R65NC22. Each timer is controlled by writing
bits into the Auxiliary Control Register (ACR) to select the mode
of operation (Figure 14).
Note that the processor does not write directly into the low-order
counter (TlC-L). Instead, this half of the counter is loaded
automatically from the low order latch (Tl L-L) when the
processor writes into the high order counter (T1C-H). In fact, it
may not be necessary to write to the low order counter in some
applications since the timing operation is triggered by writing
to the high order latch.
Timer 1 Operation
Interval Timer Tl consists of two S-bit latches (Figure 12) and
a 16-bit counter (Figure 13). The latches store data which is to
be loaded into the counter. After loading, the counter decrements
at 02 clock rate. Upon reaching zero, an interrupt flag is set,
and IRQ goes low if the Tl interrupt is enabled. Timer 1 then
REG 7-TIMER 1 HIGH-ORDER LATCH
REG 6-TIMER 1 LOW-ORDER LATCH
1+1-1 1+1,1 1
4
0
~~
COUNT
VALUE
'-------3'
L.._ _ _ _ _ _ _ 64
COUNT
VALUE
'--------16384
'---------"8
'---------32768
WRITE
8 BITS lOADED INTO T1 HIGH.oRDER
LAlt:HES. UNLIKE REG 4 OPERATION
NO LATCH.:JO.COUNTER TRANSFERS
TAKE PLACE. T1 INTERRUPT FLAG IS
RESET.
READ - 8 BITS FROM T1 HIGH-ORDEA LAlCHES
TRANSFERREO 10 MPU.
WRITE - B BITS LOADED INTO T1 LOW·ORDER
LATCHES THIS OPERATION IS NO
DIFFERENT THAN A WRITE INTO
REG 4.
READ - 8 BITS FROM T1 LOW.()RDEA LATCHES
TRANSFERRED TO MPU UNLIKE REG '"
OPERATION, THIS DOES NOT CAUSE
RESET OF 11 INTERRUPT FLAG
Figure 12.
~
Timer 1 (Tl) Latch Registers
REG 4-TIMER 1 LOW-ORDER COUNTER
REG 5-TIMER 1 HIGH-ORDER COUNTER
1 1+1 11'1,1 1
7
4
3
0
l§~
COUNT
VALUE
L..------3'
'--_ _ _ _ _ _ 64
L-------8'9'
'--------'6384
'---------"8
L---------32768
WRITE - 8 BITS LOADED INTO 11 LOW-OADER
LATCHES LATCH CONTENTS ARE
WRITE - 8 BITS LOADED INTO T1 HIGH.()RDER
LATCHES ALSO, AT THIS TIME BOTH
HIGH- AND lOW-ORDEA LATCHES ARE
mANSFERRED INTO T1 COUNTER
T1 INTERRUPT FLAG ALSO IS RESET.
READ - 8 BITS FROM T1 HIGH-ORDER COUNTER
TRANSFERRED TO MPU.
TRANSFERRED INTO LOW-ORDER
COUNTER AT THE TIME THE HIGH.
ORDER COUNTER IS LOADED (REG 5)
READ - 8 BITS FROM T1 LOW-ORDER COUNTER
TRANSFERRED TO MPU. IN ADDITION,
T1 INTERRUPT FLAG IS RESET (BIT 6
IN INTERRUPT FLAG REGISTER)
Figure 13.
Timer 1 (n) Counter Registers
1-59
COUNT
VALUE
D
Versatile Interface Adapter (VIA)
R65NC22
REG ll-AUXILIARY CONTROL REGISTER
TLL::
l'I·Isi-I'I'I'lo
y
T1 TIMER CONTROl
7 6 OPERATION
o 0 TIMED INTERRUPT
EACH TIME T1 IS
LOADED
1 CONTINUOUS
INTERRUPTS
1 0 TIMED INTERRUPT
EACH TIME T1 IS
LOADED
1 1 CONTINUOUS
INTERRUPTS
PB7
DISABLED
LATCH ENA.LE'D"A."
1:':~~t,\.".,~1
o
ONE SHOT
OUTPUT
SHIFT REGISTER CONTROL
OPE RAT' ON
SQUARE
WAVE
OUTPUT
'H1F" eN UNDERDNTRDL
T2 TIMER CONTROL
5 OPERATION
'EJ
'H1FT DU' UNDER
Figure 14.
Auxiliary Con1rol Register (ACR)
Timer 1 One-Shot Mode
assure that the low order latch contains the proper data before
initiating the count-down with a "write T1C-H" operation. When
the processor writes into the high order counter (T1C-H), the T1
interrupt flag will be cleared, the contents of the low order latch
will be transferred into the low order counter, and the timer will
begin to decrement at system clock rate. If the PB7 output is
enabled, this signal will go low on the falling edge of 02 following the write operation. When the counter reaches zero, the
T1 interrupt flag will be set, the IRQ pin will go low (interrupt
enabled), and the signal on PB7 will go high. At this time the
counter will continue to decrement at system clock rate. This
allows the system processor to read the contents of the counter
to determine the time since interrupt. However, the n interrupt
flag cannot be set again unless it has been cleared as described
in this specification.
The Timer 1 one-shot mode generates a single interrupt for each
timer load operation. k; w~h any interval timer, the delay between
the "write T1C-H" operation and generation of the processor interrupt is a direct function of the data loaded into the timing counter,
In addition to generating a single interrupt, Timer 1 can be
programmed to produce a single negative pulse on the PB7
peripheral pin. With the output enabled (ACR7 1) a "write nC-H"
operation will cause PB7 to go low. PB7 will return high when Timer
1 times out. The result is a single programmable width pulse.
=
Timing for the R65NC22 interval timer one-shot modes is shown
in Figure 15,
In the one-shot mode, writing into the T1L-H has no effect on
the operation of Timer 1. However, it will be necessary to
I I
WRITE TtC-H
~~I--------~:~:----~---------
IRQ OUTPUT
PB7 OUTPUT
I
T1 COUNTER
I
N
I
N-l
I
N-2
I
N-3
I
//
o
FFFF
I . - - - N + 1.5 CYCLES------.J.I
Figure 15.
Timer 1 One-Shot Mode Timing
1-60
N
N-l
I N-2 I
Versatile Interface Adapter (VIA)
R65NC22
Timer 1 Free-Run Mode
the time-out can be prevented completely if the processor continues to rewrite the timer before it reaches zero. Timer 1 will
operate in this manner if the processor writes into the high order
counter (T1C-H). However, by loading the latches only, the
processor can access the timer during each down-counting
operation without affecting the time-out in process. Instead, the
data loaded into the latches will determine the length of the next
time-out period. This capability is particularly valuable in the freerunning mode with the output enabled. In this mode, the signal
on PB7 is inverted and the interrupt flag is set with each timeout. By responding to the interrupts with new data for the latches,
the processor can determine the period of the next half cycle
during each half cycle of the output signal on PB7. In this manner,
very complex waveforms can be generated.
The most important advantage associated with the latches in T1
is the ability to produce a continuous series of evenly spaced
interrupts and the ability to produce a square wave on PB7 whose
frequency is not affected by variations in the processor interrupt
response time. This is accomplished in the "free-running" mode.
In the free-running mode, the interrupt flag is set and the signal
on PB7 is inverted each time the counter reaches zero at which
time the timer automatically transfers the contents of the latch
into the counter (16 bits) and continues to decrement from there.
The interrupt flag can be cleared by writing T1C-H or T1L-H, by
reading T1C-L, or by writing directly into the flag as described
later. However, it is not necessary to rewrite the timer to enable
setting the interrupt flag on the next time-out.
A precaution to take in the use of PB7 as the timer output concerns the Data Direction Register contents for PB7. Both DDRB
bit 7 and ACR bit 7 must be 1 for PB7 to function as the timer
output. If one is 1 and other is 0, then PB7 functions as a normal outpin pin, controlled by ORB bit 7.
All interval timers in the R65NC22 are "re-triggerable". Rewriting
the counter will always re-initialize the time-out period. In fact,
.2 Jl.....J!-JL.-.~,.JL.JL...f"LrL
~
I
I
WRITET1C-H
::::
PB7 OUTPUT
1";-
I
~;
l--
;/
//
N + 1.5 CYCLES --I.If..---- N + 2 CYCLES
Figure 16.
L.!- - - -
-----1.1
Timer 1 Free-Run Mode Timing
Timer 2 Operation
decrementing again through zero. The processor must rewrite
T2C-H to enable setting of the interrupt flag. The interrupt flag
is cleared by reading T2C-L or by writing T2C-H. Timing for this
operation is shown in Figure 18.
Timer 2 operates as an interval timer (in the "one-shot" mode
only), or as a counter for counting negative pulses on the PB6
peripheral pin. A single control bit in the Auxiliary Control Register
selects between these two modes. This timer is comprised of
a "write-only" lower-order latch (T2L-L), a "read-only" low-order
counter (T2G-L) and a read/write high order counter (T2C-H). The
counter registers act as a 16-bit counter which decrements at
02 rate. Figure 17 illustrates the T2 Latch/Counter Registers.
Timer 2 Pulse Counting Mode
In the pulse counting mode, T2 counts a predetermined number
of negative-going pulses on PB6. This is accomplished by first
loading a number into T2. Writing into T2C-H clears the interrupt flag and allows the counter to decrement each time a pulse
is applied to PB6. The interrupt flag is set when T2 counts down
past zero. The counter will then continue to decrement with each
pulse on PB6. However, it is necessary to rewrite T2C-H to allow
the interrupt flag to set on a subsequent time-out. Timing for this
mode is shown in Figure 19. The pulse must be Iowan the leading
edge of 02.
Timer 2 One-Shot Mode
As an interval timer, T2 operates in the "one-shot" mode similar
to Timer 1. In this mode, T2 provides a single interrupt for each
"write T2C-H" operation. After timing out, the counter will continue to decrement. However, setting of the interrupt flag is disabled after initial time-out so that it will not be set by the counter
1-61
D
Versatile Interface Adapter (VIA)
R65NC22
REG a-TIMER 2 LOW-ORDER LATCH/COUNTER
REG 9-TIMER 2 HIGH-ORDER LATCH/COUNTER
2"
S12
1024
....
COUNT
VALUE
'-_____ 1.
'--_ _ _ _ _ 32
'-------
COUNT
VALUE
2048
..
8192
1638..
'--------128
32768
WRITE _
8 BITS LOADED INTO 12 LOW ORDER
LATCH
READ -
8 BITS FROM 12 LOW ORDER COUNTER
WRITE -
8 BITS LOADED INTO T1: IIIGH ORDER
COUNTER ALSO, LOWOROER LATCH
TRANSFERRED TO lOW ORDER
COUNTER IN ADDITION, T2 INTERRUPT
READ -
8 BITS FROM T2 HIGH OROER COUNTER
TRANSfERRED TO MPU
TRANSFERRED TO MPU T2 INTERRUPT
flAG IS RESET
Figure 17.
flAG IS REseT
Timer 2 (T2) Latch/Counter Registers
WRITE T2C-H
/
IRQ OUTPUT
T2 COUNTER
N
N-'
I N-2 I N-3 I
o
FFFF
I
FFFE
I
FFFD
I
FFFC
1 - - - - - - - N + 1.5 CYCLES - - - - - -...
Figure 18.
WRITE T2C-H
Timer 2 One-Shot Mode Timing
r:
OPERATION ----J
I~---------------------------ii~r!-------------------------
PB61NPUT -------~r----i/,~!
----,Ur------
IRQ OUTPUT
T2 COUNTER
-------------------------------------~;~r!----------------,
N
N-l
N-2
Figure 19. Timer 2 Pulse Counting Mode
1-62
o
FFFF
I
Versatile Interface Adapter (VIA)
R65NC22
SHIFT REGISTER OPERATION
of this output clock is a function of the system clock period and
the contents of the low order T2 latch (N).
The Shift Register (SR) performs serial data transfers into and
out of the CB2 pin under control of an internal modul0-8 counter.
Serial data transfer in and out of the Shift Register (SR) begin
with the most significant bit (MSB) first. Shift pulses can be
applied to the CBl pin from an external source or, with the proper
mode selection, shift pulses generated internally will appear on
the CBl pin for controlling external devices.
The shifting operation is triggered by the read or write of the SR
if the SR flag is set in the IFR. Otherwise the first shift will occur
at the next time-out of T2 after a read or write of the SR. The
input data should change before the positive-going edge of CBl
clock pulse. This data is shifted into the shift register during the
02 clock cycle following the positive-going edge of the CBl clock
pulse. The minimum CBl positive pulse width must be one clock
period. After 8 CBl clock pulses, the shift register interrupt flag
will set and IRQ will go low.
The control bits which select the various shift register operating
modes are located in the Auxiliary Control Register. Figure 20
illustrates the configuration of the SR data bits and Figure 21
shows the SR control bits of the ACR.
SR Mode 2 -
SR Mode 0 - Shift Register Interrupt Disabled
Mode 0 disables the Shift Register interrupt. In this mode the
microprocessor can write or read the SR and the SR will shift
on each CBl positive edge shifting in the value on CB2. In this
mode the SR interrupt Flag is disabled (held to a logic 0).
SR Mode 1 -
Shift In Under Control of T2
In mode 1, the shifting rate is controlled by the low order 8 bits
of T2 (Figure 22). Shift pulses are generated on the CBl pin to
control shifting in external devices. The time between transitions
REG ll-AUXILIARY CONTROL REGISTER
REG lO-SHIFT REGISTER
"l~
1+1+1+1+1
J...LL
L
SHIFT REGISTER
MODE CONTROL
SHIFT
REGISTER
BITS
NOTES
1. WHEN SHIFTING
OUI, BIT 715 THE FIRST BIT
OUT AND SIMULTANEOUSLY IS ROTATED BACK
INTO BIT O.
2. WHEN SHIFTING IN, SITS INITIALLY ENTER
BIT 0 AND ARE SHIFTED TOWARDS BIT 7.
Figure 20.
Shift Register
CB2 INPUT
DATA
4
0
0
0
0
3
0
0
1
1
0
1
OPERATION
DISABLED
SHIFT IN UNOER CONTROL OF T2
SHIFT IN UNDER CONTROL OF "2
SHIFT IN UNOER CONTROL OF EXT eLK
1
1
1
1
0
0
0
SHIFT OUT fREE RUNNING AT T2 RATE
1
SHIFT OUT UNDER CONTROL OF T2
SHIFT OUT UNDER CONTROL OF 02
SHIFT OUT UNDER CONTROL Of EXT eLK
2
0
1
,.
0
1
1
Figure 21.
Shift Register Modes
,fUlMflIlfl.1l
WRITE OR READ
SHIFT REG
CBl OUTPUT
SHIFT CLOCK
Shift In Under 102 Control
In mode 2, the shift rate is a direct function of the system clock
frequency (Figure 23). CBl becomes an output which generates
shift pulses for controlling external devices. Timer 2 operates
as an independent interval timer and has no effect on SA. The
shifting operation is triggered by reading or writing the Shift
Register. Data is shifted, first into bit 0 and is then shifted into
the next higher order bit of the shift register on the trailing edge
of each 02 clock pulse. After 8 clock pulses, the shift register
interrupt flag will be set, and the output clock pulses on CBl
will stop.
N + 2r:!CLES
I. .1.
.IN + 21
CYCLES
2
1
/~
3
8
YtltnNOflOOOliX:IY{llllllJ)(I:~::rY{l:(/iglli\t$l~
I
Figure 22.
SR Mode 1 -
Shift In Under T2 Control
1-63
I
L
D
Versatile Interface Adapter (VIA)
R65NC22
SR Mode 3 -
Shift In Under CBl Control
the shifting operation (Figure 25). Since the Shift Register bit 7
(SR7) is recirculated back into bit 0, the 8 bits loaded into the
shift register will be clocked onto CB2 repetitively. In this mode
the shift register counter is disabled.
In mode 3, external pin CB1 becomes an input (Figure 24). This
allows an external device to load the shift register at its own pace.
The shift register counter will interrupt the processor each time
8 bits have been shifted in. The shift register stops after 8 counts
and must be reset to start again. Reading or writing the Shift
Register resets the Interrupt Flag and initializes the SR counter
to count another 8 pulses.
SR Mode 5 -
Note that the data is shifted during the first system clock cycle
following the positive-going edge of the CB1 shift pulse. For this
reason, data must be held stable during the first full cycle fol·
lowing CB1 going high. The minimum CB1 positive pulse width
must be one clock period.
SR Mode 4 -
Shift Out Under T2 Control (Free-Run)
Mode 4 is very similar to mode 1 in which the shifting rate is
set by T2. However, in mode 4 the SR Counter does not stop
H
READSR
CB1 OUTPUT
SHIFT CLOCK
Shift Out Under T2 Control
In mode 5, the shift rate is controlled by T2 (as in mode 1). The
shifting operation is triggered by the read or write of the SR if
the SR flag is set in the IFR (Figure 26). Otherwise the first shift
will occur at the nextlime·out of T2 after a read or write of the
SA. However, with each read or write of the shift register the SR
Counter is reset and 8 bits are shifted onto CB2. At the same
time, 8 shift pulses are generated on CB1 to control shifting in
external devices. After the 8 shift pulses, the shifting is disabled,
the SR Interrupt Flag is set and CB2 remains at the last
data level.
I
~-+----------
C B 2 I N P U T .
DATA
I
I~
IRQ
Figure 23.
SR Mode 2 -
________________
Shift In Under 1/)2 Control
CB2INPUT~~ggggK:I:~~~CJ2L:~~~:13:>~~X:J4C:~;~ : ~
~
DATA
I
L
Figure 24.
WRITE SR
SR Mode 3 -
Shift In Under CB1 Control
I I.....+-__
I +---+:-:--~__-+-___--+_____+'__-+-'______
--1l
t-.~*-..J
N + 2 CYCLES
CB1 OUTPUT - - - - - - - - ;
SHIFT CLOCK
H
.
I _ r----,
I
~
_ r--
L!...J
~:~~UTPUT XXXXlOOOOOOOf
----------------~----------------------~
CA1
"DATA READY"
;fDv
IAS2~
2.0~V~-----
1----
O.BV
LACTIVE
TRANSITION
Figure 31b.
CA2 Timing for Read Handshake, Handshake Mode
WRITE ORA, ORB
OPERATION
CA2,CB2
"DATA READY"
PA,PB
PERIPHERAL
DATA
~
---IDS----I
2.0V
O.BV
~-------------------------------------Figure 31c.
CA2, CB2 Timing for Write Handshake, Pulse Mode
1-68
R65NC22
Versatile Interface Adapter (VIA)
02
----..\,-----,t. . "-.~
\'------.J,r--_I
WRITE ORA, ORB
OPERATION
2.0V
CA2,CB2
"DATA READY"
O.BV
los
G,,-
PA,PB
-.i2.OV
PERIPHERAL
DATA
_______________ ~._~O~.B~V______________~~~______________
)
-+_
lRS4
I
CAl, CBl
"DATA TAKEN"
)
Figure 31d.
PA,PB
PERIPHERAL
INPUT DATA
~;~;:~ TCHING
I
CA2, CB2 Timing for Write Handshake, Handshake Mode
f
~2.0V
O.BV
_____________________
~I- :. -:. -:. -I= ~ -IA-L:1:'L:::~f-lol:~~
- - - - - - - - - - - -.....
TRANSITION
Figure 31e.
Peripheral Data Input Latching Timing
CBl
SHIFT CLOCK
(INPUT OR
OUTPUT)
Figure 31f.
Timing for Shift Out with Internal or External Shift Clocking
1-69
D
R65NC22
Versatile Interface Adapter (VIA)
CB1
SHIFT CLOCK
I
MUST BE HIGH DURING THE FULL
.2 HIGH SAMPLE PERIOD.
I
I
I
I
n
I
INTERNAL
SHIFT PULSE _ _ _--I
L -_ _
I
I
CB2
SHIFT DATA
T"1~"'7"':rrrrT7''''''''''''-----~=
IJlJ
/JlJJJJI I>V
MUST BE VALID DURING THE FULL
lflii/I11III//\ VALID
INTERNAL SHIFT PULSE PERIOD.
Figure 31g.
Timing for Shift In with Internal or External Shift Clocking
O._8_v~rt~_2._0V
CB1
SHIFT CLOCK
INPUT
I,ew _ _ _
Figure 31h.
_ _ _ IICS
External Shift Clock Timing
O_.8_V~ j._2._0V
PB6
PULSE COUNT
INPUT
IIPW _ _ _
_ _ _ IIPS
COUNTER T2
DECREMENTS
HERE
Figure 311.
Pulse Count Input Timing
1-70
R65NC22
Versatile Interface Adapter (VIA)
BUS TIMING WAVEFORMS
D
.2
CLOCK
REGISTER
SELECTS,
CHIP SELECTS,
RNV
~I~~~~
~
~~~~I~~~~I~
__-+____~____~__~~~
PERIPHERAL
DATA
2.0V 1----~ 2.0V
DATA BUS
---------------------{I
O.BV l\-_ _---'J'I O.BV
Figure 32a.
Read Timing Waveforms
Icv
~tPWH-=1
I
e2
CLOCK
2.0V
O.8V
- -
I- t ACW -
IcAW
2.0V
2.0V
CHIP SELECTS,
REGISTER SELECTS
"",
2.0V
\.OV
O.BV
O.BV.
I- t DCW RIW
\
2.0V
O.BV
-
~tHW
2.0V
DATA
BUS
O.BV
•
tcpw-
2.0V
PERIPHERAL
DATA
O.BV
,Figure 32b.
Write Timing Waveforms
1-71
Versatile Interface Adapter (VIA)
R65NC22
ABSOWTE MAXIMUM RATINGS*
Parameter
Symbol
Value
Unit
Vee
-0.3 to + 7.0
Vde
Supply Voltage
Input Voltage
V,N
-0.3 to Vee +0.3 Vdc
Output Voltage
VOUT
-0.3 to Vee +0.3 Vdc
Operating Temperature
Commercial
Industrial
TA
Storage Temperature
TSTG
'NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the other sections of this document
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
°C
o to + 70
-40 to +85
-55 to +150
°C
OPERATING CONDITIONS
Parameter
Symbol
Value
Supply Voltage
Vee
5V ±5%
Temperature Range
Commercial
Industrial
TA
TL to TH
OOC to 70°C
- 40°C to + 85°C
ELECTRICAL CHARACTERISTICS
(Vee = 5.0 Vdc ±5%, Vss = 0, TA = TL to TH , unless otherwise noted)
Parameter
Symbol
Input High Voltage
Logic
V,H
Input Low Voltage
Logic
V,L
InpuU.e~e Current
liN
Input Leakage Current lor Three-State 011
DO-D7
Input High Current
PAO-PA7,CA2, PBO-PB7,CBI,CB2
ITSI
Input Low Current
PAO-PA7, CA2
PBO-PB7, CBI, CB2
I,L
Output High Voltage
All outputs
PBO-PB7 (Darlington Drive)
V OH
Output Low Voltage
PAO-PA7,CA2,DO-D7
IRO, PBO-PB7, CBI, CB2
VOL
Output High Current (Sourcing)
All outputs
PBO-PB7 (Darlington Drive)
CBI, CB2
10H
Output Low Current (Sinking)
PAO-PA7, CA2, DO-D7
All others
10L
O~t
_
RAN,RES,RSO, RSI, RS2, RS3,CSI,CS2,CAI,~2
I'H
Min.
Typ.-
Max.
Unit'
Test Conditions
V
+2.0
-
Vee
-0.3
+0.8
-
±I
±2.5
pA
Y'N = OV to Vee
Vee = 5.25V
-
±2
±IO
pA
Y,N = OAV to 2AV
Vee = 5.25V
V,H = 2.4V
-200
-
-
-400
V
-
pA
V,L = OAV
-1.6
-
204
1.5
-
-
-
-2.6
-1.6
+0.4
rnA
rnA
V
V
V
Vee = 4.75V
lLOAD = 200 pA
lLOAD2 = - 3.2 rnA
Vee = 4.75V
lLOAD = 3.2 rnA
ILOAD = 1.6 rnA
-
-
-
pA
rnA
pA
VOH = 2AV
VOH = 1.5V
VOH = 2.4V
3.2
1.6
-
-
rnA
rnA
VOL = OAV
10FF
-
I
±IO
I'A
V OH = 2AV
Vee = 5.25V
Power Dissipation
Po
-
7
10
mW/MHz
Input Capacitance
C'N
-
-
10
7
20
pF
pF
pF
-
10
pF
Leakage Current (Ott State)
-200
-3.2
-750
-1500
-6
-
IRO
DO~D~AO-PA7,CAI,CA2, PBO-PB7,CBI,CB2
RAN, RES, RSO,RSI, RS2,RS3,CSI,CS2
~2
Output Capacitance
-
COUT
Notes:
I. All units are direct current (DC) except lor capacitance.
2. Negative sign indicates outward current flow, positive indicates inward flOW.'
3. Typical values shown lor Vee = 5.0V and TA = 25°C.
4. Maximum loading on CBI and CB2 is 50 pF.
1-72
-
Vee = 5.0V
Y'N = OV
1= 2 MHz
TA = 25°C
R65NC22
Versatile Interface Adapter (VIA)
PACKAGE DIMENSIONS
40-PIN CERAMIC DIP
::III
[: D
I·
MAX
MIN
MAX
50.29
51.31
1.980
2.020
0.615
H~~LD
G
B
14.86
15.62
0.100
C
2.54
4.19
0.585
0.165
D
0.38
0.53
0.Q15
0,021
F
0.76
1.40
0.030
G
•
F
n~n
-IIK ---J
INCHES
MIN
A
·1
A
w
MILLIMETEAS
DIM
M-j
2.54
esc
0.055
0.100 Bse
0,030
0.070
0.76
1.78
J
0.20
0.33
O.OOB
0.Q13
K
2.54
4.19
0.100
0.165
L
14.60
15.37
0.575
0.605
M
0'
W'
0'
10'
N
0.51
1.52
0.020
0.060
H
40-PIN PLASTIC DIP
[::::::: ~: : ::::~PI'I
MILLIMETERS
MIN
MAX
MIN
MAX
A
51.28
52.32
2.040
2.060
0.560
..,Gi-
F
-J... 0
K
B
13.72
14.22
0.540
C
3.55
5.08
0.140
0.200
D
0.36
0.51
0.014
0,020
F
1.02
1.52
0.040
G
~~
1HI-
INCHES
DIM
0.085
0.30
0.008
0.Q12
4.32
0.130
2.16
J
0.20
K
3.30
15.24
0.060
0.100 BSC
0.065
1.65
L
M
2.54 BSC
H
esc
0.170
0.600
M
7'
10'
7'
N
0.51
1.02
0.020
I
sse
10'
0.040
44-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
,-~g:;a
1~t:D2-1 'I
CORNER
1Tf'
rn± ""'
~
L
?
39-
0 39 ·Oc:
~~
@
.~
1
l~
JA
~.~
'iILrtn m
CHAM.
11 PINS
h x 45· PER SIDE
3 PLCS EQUALLY
SPACES
",,""b
MILLIMETERS
MIN
A
MIN
4.14
4.39
0.163
0.173
AI
1.37
1.47
0.054
0.058
A2
2.31
2.46
0.091
0.097
SECTION A-A
TYP FOR BOTH AXIS (EXCEPT FOR BEVELED EDGE)
EJECTOR PIN MARKS
4 PLCS BOTTOM OF
PACKAGE ONLY
(TYPICAL)
BOTTOM VIEW
1-73
0.457 TYP
MAX
0,018 TYP
D
17.45
17.60
0.687
Dl
16.46
16.56
0.648
D.
12.62
12.78
0.497
.
':;--f-L
INCHES
MAX
0.693
I 0.652
I 0.503
15.75 REF
0.620 REF
1.27 BSC
0.050
h
1.15 TYP
0.045 TYP
J
0.25 TYP
0.010 TYP
D3
~~.
c:
+
\
DIM
b
SIDE VIEW
CHAM.J x 45·
"" i-ce
-'A--1
~
2.
TOP VIEW
~
SEATING PLANE
~
INDICATOR
-17
V
0'
esc
45° TYP
45° TYP
A
0.89 TYP
0.035 TYP
AI
0.25 TYP
0.010 TYP
R65NC22
Versatile Interface Adapter (VIA)
R65NC22/R65C22 DIFFERENCES
R65C22
1. Register select lines are decoded during
R65NC22
02.
1. Register select lines are decoded during 02 only if CS2 is active
low.
2. CB1 must not change during last 100 ns of 02. CB1 must have a
pulse width greater than one period.
2. CB1 can change anytime but is sampled only during 02. CB1 must
have a pulse greater than one period.
3. PBO-PB7 and CB1, CB2 have active pull-ups.
3. PBO-PBl and CB1, CB2 have passive pull ups (=3 KIl).
4. PBO-PB7, CB1 and CB2 represent two standard TTL loads in the
input mode and will drive two standard TTL loads in the output mode.
4. PBO-PBl, CB1 and CB2 represent one standard TTL load in the input
mode and will drive one standard TTL load In the output mode.
1-74
R65C24
'1'
Rockwell
R65C24
Peripheral Interface Adapter/Timer (PlAT)
DESCRIPTION
FEATURES
The R65C24 Peripheral Interface AdapterlTimer (PlAT) is
designed to solve a broad range of peripheral control problems in
the implementation of microcomputer systems. This device allows
a very effective trade-off between software and hardware by providing significant capability and flexibility in a low cost chip. When
coupled with the power and speed of the R6500, R65001* or
R65COO family of microprocessors, the R65C24 allows implementation of very complex systems at a minimum overall cost.
• Low power CMOS N-well sillicon gate technology
Control of peripheral devices is handled primarily through two
8-bit bidirectional ports. Each of these lines can be programmed
to act as either an input or an output. In addition, four peripheral
control/interrupt input lines are provided. These lines can be
used to interrupt the processor or to "handshake" data between
the processor and a peripheral device.
• Automatic "Handshake" control of data transfers
The PlAT also contains one 16-bit CounterlTimer comprised of
a 16-bit counter, two 8-bit latches associated with the counter,
and an 6-bit snapshot latch for the upper half of the counter.
A counter mode control register, under software direction, selects
anyone of eight counter modes of operation, and the status
register contains an underflow flag to report counter time-out.
A maskable interrupt request allows immediate CPU notification upon counter time-out.
• Commercial and industrial temperature range versions
• Two 8-bit bidirectional I/O ports with individual data direction
control
• Programmable 16-bit CounterlTimer with eight modes of
operation
• Three a-bit latches associated with the CounterlTimer
• Selectable divide-by-sixteen prescaler for ali modes
• Three interrupts with program control
-PortA
-Port B
- CounterlTimer
• 1, 2, 3, and 4 MHz versions
• Wide variety of packages
- 40-pin plastic and ceramic DIP
- 44-pin plastic leaded chip carrier (PLCC)
• Single
:~i~~J~31~~~
CD"".C')N_:::::~;;:~
PA4
PAS
PAB
PA7
PBO
PBI
PB2
PB3
PB4
PBS
PB6
'2
RS2
CS2
CSO
RtW
Vee
40-PIN DIP
0
PIN I
INDICATOR
44-PIN PCC
Figure 1.
Document No. 29651N54
power requirement
a:
CAl
CA2
IRQ
CNTR
RSO
RSI
RES
DO
01
02
03
04
05
06
07
vss
PAO
PAl
PA2
PA3
PA4
PAS
PA6
PA7
PBO
PBI
PB2
PB3
PB4
PBS
PB6
PB7
CBI
CB2
+ 5 Vdc
• Compatible with the R6500, R65001* and R65COO family of
microprocessors
39
38
37
36
35
34
33
32
31
30
29
RSO
RSI
RES
DO
01
02
03
04
05
DB
07
NC = NO INTERNAL
CONNECTION
R65C24 Pin Assignments
Product Description
1-75
Order No. 2151
Rev. 5, June 1987
Peripheral Interface Adapter/Timer (PlAT)
R65C24
ORDERING INFORMATION
NOTE:
An R65C24 PlAT may be installed in a circuit in place of
an R65C21 PIA subject to chip select considerations. Since
the R65C21 has a CS1 input and the R54C24 does not
have a CS1 input, the PlAT will be selected in the same
addresses as the PIA and maybe more depending upon
external address decoding circuitry.
Part Number:
R65C24
t=
Temperature Range:
O°C to + 70°C
Blank =
E = -40°C to +85°C
RESET SIGNAL (RES)
Frequency Range:
1 = 1 MHz
2 = 2 MHz
3 = 3 MHz
4 = 4 MHz
L---_ _ _ Package:
C = 40-Pin Ceramic DIP
P = 40-Pin Plastic DIP
J = 44-Pin Plastic Leaded
Chip Carrier (PLCC)
The Reset (RES) input initializes the R65C24 PlAT. A low signal
on the (RES) input causes all internal registers to be cleared.
CLOCK SIGNAL (1/12)
The Phase 2 Clock Signal (1))2) is the system clock that triggers
all data transfers between the CPU and the PlAT. 1))2 is generated
by the CPU and is therefore the synchronizing signal between
the CPU and the PlAT.
INTERFACE SIGNALS
READIWRITE SIGNAL (R/IN)
The PlAT interfaces to the R6500, R6500r or the R65COO
microprocessor family with a reset line, a 1))2 clock line, a
readlwrite line, an interrupt request line, three register select lines,
two chip select lines, and an 8-bit bidirectional data bus.
Read/Write (RiW) controls the direction of data transfers between
the PlAT and the data lines associated with the CPU and the
peripheral devices. A high on the RiW line permits the peripheral
devices to transfer data to the CPU from the PlAT. A low on the
Rm line allows data to be transfered from the CPU to the
peripheral devices from the PlAT.
The PlAT interfaces to the peripheral devices with four
interrupt/control lines and two 8-bit bidirectional data ports. A
CounterlTimer input/output line (CNTR) also interfaces to a
peripheral device.
REGISTER SELECT (RSO, RS1, RS2)
Figure 1 (on the front page) shows the pin assignments for these
interface signals and Figure 2 shows the interface relationship of
these signal as they pertain to the CPU and the peripheral devices.
Two of the Register Select lines (RSO, RS1), in conjunction with
the Control Registers (CRA, CRB), select various R65C24
registers to be accessed by the CPU. RSO and RS1 are normally
connected to the microprocessor (CPU) address output lines.
Through control of these lines, the CPU can write directly into
the Control Registers (CRA, CRB), the Data Direction Registers
(DORA, DDRB) and the Peripheral Output Registers (ORA, ORB).
In addition, the processor may directly read the contents of the
Control Registers and the Data Direction Registers. Accessing
the Peripheral Output Register for the purpose of reading data
back into the processor operates differently on the ORA and the
ORB registers and, therefore, are shown separately in Table 1.
CHIP SELECT (CSO, CS2)
The PlAT is selected when CSO is high and CS2 is low. These
two chip select lines are normally connected to the processor
address lines either directly or through external decoder circuits.
When the PlAT is selected, data will be transferred between the
data lines and PlAT registers, and/or peripheral interface lines
as determined by the Rm, RSO, RS1 and RS2 lines and the
contents of Control Registers A and B.
00-07
R6S00,
R6S00/"
OR
R6SCOO
MICROPROCESSOR
FAMILY
<
(SI
"
-'0.
I
SI
"> PA()'PA7
02
RNi
CAl
CA2
}
PERIPHERAL
DEVICE
A
RSO
RSl
RS2
R6SC24
PlAT
CSO
CNTR
CS2
RES
IRQ
VSS
..
PERIPHERAL
DEVICE
"(Sl
VCC
Figure 2.
~
Interface Signals Relationship
1-76
B
R65C24
Peripheral Interface Adapter/Timer (PlAT)
Table 1.
Peripheral Register Addressing
Data
Direction
Register
Control
Register
Select
Lines
Register
Address
CRA CRB
(Hex) RS2 RS1 RSO {Bit 2) {Bit 2)
Table 2.
Counter/Timer Register Addressing
Register
Select Lines
Register
Address
(Hex) RS2 RSl RSO
Register Operation
Rm = H
Rm= L
Read PIBA
Write ORA
4
H
L
L
1
-
4
H
L
L
0
-
Read DORA Write DORA
5
H
L
H
-
Read CRA
Write CRA
6
H
H
L
-
1
Read PIBB
Write ORB
6
H
H
L
-
0
Read OORB Write DDRB
7
H
H
H
-
-
Read CRB
(R/w = L)
0
L
L
L Read Snapshot
Latch (SL)
SL - 00·07
0 - UF
Write Upper Latch
(UL)
00·07_ UL
0_ UF
Load and Enable
Counter
UL- UC,
LL- LC
1
L
L
H Read Upper
Counter (UC)
UC- 00·07
Write Upper Latch
(UL)
00·07- UL
2
L
H
L Read Lower
Counter (LC)
LC - 00·07
UC- SL
Write Lower Latch
(LL)
00·07_ LL
UC- SL
3
L
H
H Read Status
Register (SR)
SR - 00·07
0- UF,
Write Counter Control
Mode Register
(CMCR)
00-07_ CMCR
Write CRB
Register Select line RS2 determines whether the addressed
registers are part of the CounterlTimer or the peripheral Port A
and Port B sections of the PlAT. When RS2 is high, the Port
AlPort B registers shown in Table 1 are selected. When the RS2
is low, the CounterlTimer registers are selected and operated
upon as shown in Table 2.
CounterlTlmer Operation
(R/W = H)
set by an active transition of the CA2 interrupt input signal and
IROA can be disabled by setting bit 3 in CRA to a O.
INTERRUPT REQUEST LINE (IRQ)
Three internal active low Interrupt Request lines (lROA, IROB,
and IROT) act to interrupt the microprocessor through the
externallRO output. IRO is an open drain output and is capable
of sinking 1.6 mA from an external source. This permits all
interrupt request lines to be tied together in a wired·OR config·
uration. The A and B in the titles of these internal lines
correspond to the peripheral port A and the peripheral port B
so that each interrupt request line services one peripheral
data port. The T corresponds to the CounterlTimer generated
interrupt request.
Both bit 6 and bit 7 in CRA are reset by a "Read Peripheral Output
Register A" operation. This is defined as an operation in which the
readlwrite. proper data direction register and register select signals
are provided to allow the processor to read the Peripheral A I/O port.
A summary of IROA control is shown in Table 3.
Control of IROB is performed in exactly the same manner as that
described above for IROA (Table 3). Bit 7 in CRB (IROB1) is set by
an active transition on CBl and IROB from this flag is controlled by
CRB bit O. Likewise, bit 6 (IRQB2) in CRB is set by an active transi·
tion on CB2, and IROB from this flag is controlled by CRB bit 3. Also,
both bit 6 and bit 7 of CRB are reset by a "Read Peripheral B Output
Register" operation.
IRQA and IRQB Lines - These two internal Interrupt Request
lines are associated with the Port A and Port B sections of the
PlAT and are controlled by Control Registers CRA and CRB,
and the Peripheral Control lines CAl, CA2, CB1, and CB2.
IRQT Line - The internal IROT line is associated with the
CounterlTimer and is controlled by the IROT Enable bit in the
Counter Mode Control Register and the Underflow Flag in the
Status Register. A thorough discussion of the functions and
operation of the IROT line is given in the CounterlTimer
Operation section of this product description.
These Interrupt Request lines have three interrupt flag bits which
can cause the Interrupt Request line to go low. These flags are
bits 6 and 7 in the two Control Registers (CRA, CRB). These
flags act as the link between the peripheral interrupt signals and
the microprocessor interrupt inputs. Each flag has a corresponding interrupt disable bit which allows the processor to enable
or disable the interrupt from each of the four interrupt inputs
(CAl, CA2, CB1, CB2). The four interrupt flags are set (enabled)
by active transitions of the Signal on the interrupt input (CAl,
CA2, CB1, CB2).
Table 3. IRQA and IRQB Control Summary
Control Register Bits
CRA bit 7 (IROA1) is always set by an active transition of the
CAl interrupt input signal. However, IROA can be disabled by
setting bit 0 in CRA to a O. Likewise, CRA bit 6 (I ROA2) can be
1·77
Action
CRA·7=1 and CRA·0=1
IROA goes low (Active)
CRA'6=1 and CRA·3=1
IROA goes low (Active)
CRB·7=1 and CRB·0=1
IROB goes low (Active)
CRB·6=1 and CRB·3=1
IROB goes low (Active)
R65C24
Peripheral Interface Adapter/Timer (PlAT)
FUNCIIONAL DESCRIPTION
INTERRUPT INPUT/PERIPHERAL CONTROL LINES
(CA1, CA2, CB1, CB2)
The R65C24 PlAT is organized into three independent sections
referred to as the A Side, the B Side, and a CounterlTimer. The
A Side and B Side each consist of a Control Register (CRA,
CRB), Data Direction Register (DDRA, DDRB), Output Register
(ORA, ORB), Interrupt Status Control (ISCA, ISCB), and the buffers necessary to drive the Peripheral Interface buses. Data Bus
Buffers (DBB) interface data from the two sections to the data
bus, while the Data Input,Register (DIR) interfaces ~ta from
the DBB to the PlAT registers. Chip Select and RIW control
circuitry interface to the processor bus control lines. The
CounterlTimer consists of a 16-bit counter; i.e., an B-bit Upper
Counter (UC) and B-bit Lower Counter (LC), an B-bit Upper Latch
(UL), an B-bit Lower Latch (LL), an B-bit Snapshot Latch (SL),
and a Status Register (SR). A Counter Mode Control Register
(CMCR) selects the CounterlTimer mode of operation. Figure 3
is a block diagram of the R65C24 PlAT.
The four interrupt inpuVperipheral control lines provide a number
of special peripheral control functions. These lines greatly
enhance the power of the two general purpose interface ports
(PAO-PA7, PBO-PB7). Figure 5 summarizes the operation of
these control lines.
CA1 is an interrupt input only. An active transition of the signal
on this input will set bit 7 of the Control Register A to a logic 1 .
The active transition can be programmed by setting a 0 in bit 1
of the CRA if the interrupt flag (bit 7 of CRA) is to be set on a
negative (high to low) transition of the CA 1 signal, or by setting
a 1 if it is to be set on a positive (low to high) transition.
CA2 can act as a totally independent interrupt or as a peripheral
control output. As an input (CRA, bit 5 = 0) it acts to set the
interrupt flag, bit 6 of CRA, to a logic 1 on the active transition
selected by bit 4 of CRA.
DATA INPUT REGISTER (DIR)
When the microprocessor writes data into the PlAT, the data
which 'appears on the data bus during the 02 clock pulse is
latched into the Data Input Register (DIR). The data is then
transferred into one of six internal registers of the PlAT after
the trailing edge of the 02 clock. This assures that the data on
the peripheral output lines will make smooth transitions from high
to low (or from low to high) and the voltage will remain stable
except when it is going to the opposite polarity.
These control register bits and interrupt inputs serve the same
basic function as that described above for CA 1. The input signal
sets the interrupt flag which serves as the link between the
peripheral device and the processor interrupt structure. The
interrupt disable bit allows the processor to exercise control over
the system interrupt.
CONTROL REGISTERS (CRA AND CRB)
In the output mode (CRA, bit 5 = 1), CA2 can operate independently to generate a single pulse each time the microprocessor
reads the data on the Peripheral A 1/0 port. This mode is selected
by setting CRA, bit 4 to a 0 and CRA, bit 3 to a 1. This pulse
output can be used to control the counters, shift registers, etc.
which make sequential data available on the Peripheral input
lines.
Table 4 illustrates the bit designation and functions in the two
control registers. The control registers allow the microprocessor
to control the operation of the Interrupt Control inputs (CA 1, CA2,
CB1, CB2), and Peripheral Control outputs (CA2, CB2). Bit 2
in each register controls the addressing of the Data Direction
Registers (DDRA, DDRB) and the Output Registers (ORA, ORB).
In addition, two bits (bit 6 and 7) in each control register indicate
the status of the Interrupt Input lines (CA1, CA2, CB1, CB2).
These Interrupt Status bits (IRQA1, IRQA2 or IRQB1, IRQB2)
are normally interrogated by the microprocessor during the IRQ
interrupt service routine to determine the source of the interrupt.
A second output mode allows CA2 to be used in conjunction
with CA1 to "handshake" between the processor and the
peripheral device. On the A side, this technique allows positive
control of data transfers from the peripheral device into the
microprocessor. The CA1 input signals the processor that data
is available by interrupting the processor. The processor reads
the data and sets CA2 low. This signals the peripheral device
that it can make new data available.
DATA DIRECTION REGISTERS (DORA, DDRB)
The Data Direction Registers (DDRA, DDRB) allow the processor
to program each line in the B-bit Peripheral 1/0 port to be either
an input or an output. Each bit in DDRA controls the corresponding line in the Peripheral A port and each bit in DDRB controls
the corresponding line in the Peripheral B port. Writing a 0 in
a bit position in the Data Direction Register causes the corresponding Peripheral 1/0 line to act as an input; a 1 causes
it to act as an output.
The final output mode can be selected by setting bit 4 of CRA
to a 1. In this mode, CA2 is a simple peripheral control output
which can be set high or low by setting bit 3 of CRA to a 1 or
a 0, respectively.
CB1 operates as an interrupt input only in the same manner as
CA 1. Bit 7 of CRB is set by the active transition selected by bit
o of CRB. Likewise, the CB2 input mode operates exactly the
same as the CA2 input modes. The CB2 output modes, CRB
bit 5 = 1, differ somewhat from those of CA2. The pulse output
occurs when the processor writes data into the Peripheral B Output Register. Also, the "handshaking" operates on data transfers
from the processor into the peripheral device.
Bit 2 (DDRA, DDRB) in each Control Register (CRA and CRB)
controls the accessing to the Data Direction Register or the
Peripheral interface. If bit 2 is a 1, a Peripheral Output register
(ORA, ORB) is selected, and if bit 2 is a 0, a Data Direction
Register (DDRA, DDRB) is selected. The Data Direction Register
Access Control bit, together with the Register Select lines (RSO,
RS1 and RS2) selects the various internal registers as shown
in Table 1.
1-7B
Peripheral Interface Adapter/Timer (PlAT)
R65C24
CNTR
IRQT
AlB-BIT
COUNTER/TIMER
~
t
Fl
DO
01
02
DATA BUS
BUFFERS
(DBB)
03
04
k,
06
07
U
DATA INPUT
REGISTER
(DIR)
CSO
CS2
RS2
RSO
.-
RSl
RiW
CONTROL
REGISTER A
(CRA)
I
lTlr
~
COUNTER MODE
CONTROL
REGISTER
(CMCR)
;:::>
PERIPHERAL
OUTPUT
REGISTER B
(ORB)
CHIP
SELECT
& RiW
CONTROL
DATA DIRECTION
REGISTER A
(DORA)
I
I
PERIPHERAL
OUTPUT
REGISTER A
(ORA)
~
b
U
PERIPHERAL
INTERFACE
BUFFER A
(PIBA)
---
I-
~
b
pJ2
CONTROL
REGISTER B
(CRB)
-...
Table 4.
CRA
CRB
6
IRQAl
IRQA2
7
6
IRQBl
IRQB2
5
~L
DATA DIRECTION
REGISTER B
(DDRB)
CBl
INTERRUPT STATUS
CONTROL B (ISCB)
CB2
R65C24 PlAT Block Diagram
Control Registers Bit Designations
4
3
4
CB2 Control
1-79
2
1
DORA
Access
CA2 Conlrol
5
PBS
PB6
PB7
---
6
7
PBO
PBl
PB2
PB3
PB4
if
IRQB
Figure 3.
PAO
PAl
PA2
PA3
PA4
PAS
PA6
PA7
- -=-
PERIPHERAL
INTERFACE
BUFFER B
(PIBB)
INPUT BUS
RES
CA2
I
OUTPUT BUS
05
CAl
INTERRUPT STATUS
CONTROL A (ISCA)
IRQA
3
2
DDRB
Access
0
CAl Control
1
0
CBl Control
R65C24
Peripheral Interface Adapter/Timer (PlAT)
In order to write data into DORA, ORA, DDRB, or ORB registers,
bit 2 in the proper Control Register must first be set. The desired
register may then be accessed with the address determined by
the address interconnect technique used.
The Peripheral B 1/0 port buffers are push-pull devices i.e., the
pull-up devices are switched OFF in the 0 state and ON for a
logic 1. Since these pull-ups are active devices, the logic 1
voltage will not go higher than + 2.4 Vdc.
PERIPHERAL OUTPUT REGISTERS (ORA, ORB)
Unlike the PAO-PA7 lines (which have pull-up devices), the PBO
through PB7 lines have three-state capability which allows them
to enter a high impedance state when programmed to be used
as input lines. In addition, data on these lines will be read
properly, when programmed as output lines, even if the data
signals fall below 2.0 Vdc for a "high" state or are above 0.8 Vdc
for a "low" state. When programmed as output, each line can
drive at least a two TTL load and may also be used as a source
of up to 3.2 rnA at 1.5 Vdc to directly drive the base of a transistor switch, such as a Darlington pair.
The Peripheral Output Registers (ORA, ORB) store the output
data from the Data Bus Buffers (DBB) which appears on the
Peripheral 1/0 port. If a line on the Peripheral A Port is programmed as an output by the DORA, writing a 0 into the corresponding bit in the ORA causes that line to go low (s 0.4 Vdc);
writing a 1 causes the line to go high. The lines of the Peripheral
B port are controlled by ORB in the same manner.
INTERRUPT STATUS CONTROL (ISCA, ISCB)
Because these outputs are designed to drive transistors directly,
the output data is read directly from the Peripheral Output
Register for those lines programmed to act as inputs.
The four interrupVperipheral control lines (CA 1, CA2, CBl , CB2)
are controlled by the Interrupt Status Control logic (A, B). This
logic interprets the contents of the corresponding Control
Register and detects active transitions on the interrupt inputs.
The final characteristic is the high-impedance input state which
is a function of the Peripheral B push-pull buffers. When the
Peripheral B 1/0 lines are programmed to act as inputs, the output buffer enters the high impedance state.
PERIPHERAL 1/0 PORTS (PAO·PA7, PBO·PB7)
DATA BUS BUFFERS (DBB)
The Peripheral A and Peripheral B 1/0 ports allow the
microprocessor to interface to the input lines on the peripheral
device by writing data into the Peripheral Output Register. They
also allow the processor to interface with the peripheral device
output lines by reading the data on the Peripheral Port input lines
directly onto the data bus and into the internal registers of the
processor.
The Data Bus Buffers are 8-bit bidirectional buffers used for data
exchange, on the 00-07 Data Bus, between the miroprocessor
and the PlAT. These buffers are tri-state and are capable of driving a two TIL load (when operating in an output mode) and represent a one TTL load to the microprocessor (when operating in
an input mode).
Each of the Peripheral 1/0 lines can be programmed to act as
an input or an output. This is accomplished by setting a 1 in
the corresponding bit in the Data Direction Register for those
lines which are to act as outputs. A 0 in a bit of the Data Direction Register causes the corresponding Peripheral 110 lines to
act as an input.
COUNTERITIMER
The CounterlTimer includes a 16-bit counter and three 8-bit data
latches. It also includes an 8-bit Counter Mode Control Register
(CMCR) to select the CounterlTimer operating mode and options
and an 8-bit Status Register to report time-out conditions as well
as peripheral data port interrupt conditions. Figure 4 illustrates
the Timer/Counter.
The buffers which drive the Peripheral A 1/0 lines contain
"passive" pull-up devices. These pull-up devices are resistive
in nature and therefore allow the output voltage to go to Vcc
for a logic 1. The switches can sink a full 3.2 rnA, making these
buffers capable of driving two standard TTL loads.
CounterlLatches - The Upper Counter (UC) and Lower
Counter (LC) form a 16-bit down-counter that counts either
02 clock pulses from the processor bus or external events from
input line CNTR, depending on the mode selected. The Upper
Latch (UL) and Lower Latch (LL) hold the initial higher- and lowerorder count values to be loaded into the counter. The Snapshot
Latch (SL) is loaded with the value of the UC when the LC is
read or the LL is written into by the PlAT. After a read of the
LC, the Snapshot Latch is read to provide the current 16-bit value
of the counter. The Underflow Flag (UF) in the Status Register
(SR) is set to a 1 whenever the counter (UC, LC) decrements
past $0000. A Prescaler can be program activated to divide-bysixteen rather than divide-by-one for any of the CounterlTimer
modes.
In the input mode, the pull-up devices are still connected to the
1/0 pin and still supply current to this pin. For this reason, these
lines also represent two standard TTL loads in the input mode.
The Peripheral B 1/0 port duplicates many of the functions of
the Peripheral A port. The process of programming these lines
to act as an input or any output is similar to the Peripheral A
port, as is the effect of reading or writing this port. However,
there are several characteristics of the buffers driving these lines
which affect their use in peripheral interfacing.
1-80
Peripheral Interface Adapter/Timer (PlAT)
R65C24
Status Register set to a 1) will cause IROto be asserted. When
bit 7 is set to a 0, the IROT is disabled.
Counter Mode Control Register - The Counter Mode Control Register (CMCR) allows program selection of any of eight
CounteriTimer modes of operation, for the enabling or disabling of the Prescaler, and the enabling or disabling of the IROT
interrupt line_ Bits 2, 1 and 0 of the CMCR select one of the
following CounterlTimer operating modes:
Disable CounterlTimer
One-Shot Interval Timer
Free-Run Interval Timer
Pulse Width Measurement
Event Counter
One-Shot Pulse Width Generation
Free-Run Pulse Generation
Retriggerable Interval Timer
Bit 4 of the CMCR enables or disables the Prescaler. A 1 in bit 4
causes the Prescaler to be enabled so that the CounterlTimer
is operating in a divide-by-sixteen mode. When this bit is a 0
the Prescaler is disabled so that the CounterlTimer is operating
in a normal (divide-by-one) mode.
Status Register - Bit 7 of the Status Register (SR) reports the
Counter Underflow Status. This underflow (UF) bit is set to 1
when the counter decrements past $0000. When this bit is set,
the IRO output will be asserted if the Interrupt Enable bit in the
CMCR is set to a 1. The status of the Port A Interrupt Flag (IROA)
and Port B Interrupt Flag (IROB) are reported in bits 6 and 5,
respectively, in addition to being reported in the ISCA and ISCB
registers.
Bit 7 of the CMCR controls the IROT line. When bit 7 is set to
a I, IROT is enabled and an Underflow Flag (UF bit in the
DO-D7
I-"T""-"""'T--"T"".....
iRQf ENABLED
PRESCALER
ENABLED
1----''------,1...--+- CNTR
PRESCALER
L ___~"-1-02
. .- - - - I
DO-D7
Figure 4.
Counter/Timer
1-81
Peripheral Interface Adapterrrimer (PlAT)
R65C24
CA2 INPUT MODE (BIT 5
=0)
CONTROL REGISTER A (CRA)
7
6
5
4
3
2
1
0
IRQAl
FLAG
IRQA2
FLAG
CA2 INPUT
MODE SELECT
(=0)
IRQA2
POSITIVE
TRANSITION
IRQA
ENABLE
FOR IRQA2
ORA
SELECT
IRQAl
POSITIVE
TRANSITION
IRQA
ENABLE
FOR IRQAl
IRQNIRQAl
CONTROL
IRQNIRQA2
CONTROL
CA2 OUTPUT MODE (BIT 5 = 1)
7
6
5
4
3
2
1
0
IRQAl
FLAG
0
CA20UTPUT
MODE SELECT
(=1)
CA2
OUTPUT
CONTROL
CA2
RESTORE
CONTROL
ORA
SELECT
IRQAl
POSITIVE
TRANSITION
IRQA
ENABLE
FOR IRQAl
CA2
CONTROL
CA21NPUT OR OUTPUT MODE (BIT 5
Bil7
1
o
=0 or 1)
IRQAl FLAG
A transition has occurred on CAl Ihat salisfies the bit 1 IRQA 1 transition polarity criteria. This bit is cleared by a read of Output Register
A or by RES.
No trans ilion has occurred on CAl that satisfies the bit 1 IRQAl transition polarity criteria.
Bit 2
I
OUTPUT REGISTER A SELECT
Select Output Register A.
Select Data Direction Register A.
Bit 1
1
IRQAl POSITIVE TRANSITION
Set IRQAI Flag (bit 7) on a positive (Iow-to-high) transijion of CAl.
Set IRQAl Flag (bit 7) on a negative (high-to-Iow) transition of CAl.
o
o
BH 0
I
o
IRQNlRQAI
CONTROL
IRQA ENABLE FOR IRQAl
Enable assertion of IRQA when IRQAI Flag (bit 7) is set.
Disable assertion of IRQA when IRQAl Flag (bit 7) is set.
CA2 INPUT MODE (BIT 5 = 0)
Bit 6
I
o
IRQA2 FLAG
A transilion has occurred on CA2 that satisfies the bit 4 IRQA2 transilion polarity criteria. This flag is cleared by a read of Output
Register A or by RES.
No transition has occurred on CA2 that salisfies the bit 4 IRQA2 transition polarity criteria.
Bit 5
CA2 MODE SELECT
Select CA2 Input Mode.
Bit 4
I
IRQA2 POSITIVE TRANSITION
Set IRQA2 Flag (bit 6) on a positive (Iow-to-high) transition of CA2.
Set IRQA2 Flag (bit 6) on a negative (high-to-Iow) transition of CA2.
Bit 3
IRQA ENABLE FOR IRQA2
Enable assertion of IRQA when IRQA2 Flag (bit 6) is set.
Disable assertion of IRQA when IRQA2 Flag (bit 6) is set.
o
o
1
o
CA2 OUTPUT MODE (BIT 5
= 1)
Bit 6
NOT USED
Always zero.
Bit 5
CA2 MODE SELECT
Select CA2 Output Mode.
o
1
Bit 4
1
o
Bit 3
CA2 OUTPUT CONTROL
CA2 goes low when a zero is written into CRA bit 3. CA2 goes high when a one is written into CRA bit 3.
CA2 goes low on the first negative (high-to-Iow) 02 clock transition following a read of Output Register A. CA2 returns high as specified
by bit 3.
=
CA2 READ STROBE RESTORE CONTROL (BIT 4 0)
CA2 returns high on the next 02 clock negative transition following a read of Output Register A.
CA2 returns high on the next active CAl transition following a read of Output Register A as specified by bit I.
Figure 5.
Summary of Control Lines Operation (1 of 2)
1-82
Peripheral Interface Adapterrrimer (PlAT)
R65C24
CONTROL REGISTER B (CRB)
CB2 INPUT MODE (BIT 5 = 0)
7
6
5
4
3
2
I
D
IROB1
FLAG
IROB2
FLAG
CB2 INPUT
MODE SELECT
IROB2
POSITIVE
TRANSITION
IROB
ENABLE
FOR IROB2
ORB
SELECT
IROB!
POSITIVE
TRANSITION
IROB
ENABLE
FOR IROBI
(=D)
IROB/IROB2
CONTROL
IROB/IROBI
CONTROL
CB2 OUTPUT MODE (BIT 5 = 1)
7
6
5
4
3
2
I
D
IROB1
FLAG
a
CB2 OUTPUT
MODE SELECT
CB2
OUTPUT
CONTROL
CB2
RESTORE
CONTROL
ORB
SELECT
IROBI
POSITIVE
TRANSITION
IROB
ENABLE
FOR IROBI
(=1)
CB2
CONTROL
CB21NPUT OR OUTPUT MODE (BIT 5
Bit 7
1
a
= 0 or
1)
IRQB! FLAG
A transition has occurred on CB1 that salisfies the bit t IROBI transition polarity criteria. This bit is cleared by a read of Output Register
B or by RES.
No transition has occurred on CB1 that satisfies the bit! IROB! transition polarity criteria.
Bit 2
!
OUTPUT REGISTER B SELECT
Select Output Register B.
Select Data Direction Register B.
Bit I
!
IRQB! POSITIVE TRANSITION
Set IROBI Flag (bit 7) on a positive (Iow-to-high) transttion of CB1.
Set IROBI Flag (bit 7) on a negative (high-to-Iow) transition 01 CBt.
o
o
Bit D
1
o
IROB/IROB!
CONTROL
IRQB ENABLE FOR IRQBI
Enable aSfP-rtion of IROB when IROB! Flag (bit 7) is set.
Disable assertion of IROB when IROB1 Flag (bit 7) is set.
CB2 INPUT MODE (BIT 5 = 0)
Bit 6
I
a
IRQB2 FLAG
A transition has occurred on CB2 that satisfies the bit 4 IROB2 transition polarity criteria. This flag is cleared by a read of Output
Register B or by RES.
No transition has occurred on CB2 that satisfies the bit 4 IROB2 transition polarity criteria.
Bit 5
CB2 MODE SELECT
Select CB2 Input Mode.
Bit 4
I
IRQB2 POSITIVE TRANSITION
Set IROB2 Flag (bit 6) on a positive (low-to-high) transttian of CB2.
Set IROB2 Flag (bit 6) on a negative (high-to-low) transition of CB2.
Bit 3
1
IRQB ENABLE FOR IRQB2
Enable assertion of IROB when IROB2 Flag (bit 6) is set.
Disable assertion of IROB when IROB2 Flag (bit 6) is set.
a
a
o
CB2 OUTPUT MODE (BIT 5
Bit 6
o
= 1)
NOT USED
Always zero.
Bit 5
I
CB2 MODE SELECT
Select CB2 Output Mode.
Bit 4
I
CB2 OUTPUT CONTROL
CB2 goes low when a zero is written into CRB btt 3. CB2 goes high when a one is written into CRB bit 3.
CB2 goes Iowan the first negative (high-ta-Iow) 02 clock transition following a write to Output Register B. CB2 returns high as specified
by bit 3.
o
Bit 3
I
a
CB2 WRITE STROBE RESTORE CONTROL (BIT 4 = D)
CB2 returns high on the next 02 clock negative transition following a write to Output Register B.
CB2 returns high on the next active CBI transition following a write to Output Register B as specified by bit 1.
Figure 5.
Summary of Control Lines Operation (2 of 2)
l-B3
Peripheral Interface Adapter/Timer (PlAT)
R65C24
COUNTER/TIMER REGISTERS
Bit 7
Counter Underflow (UF) Interrupt Flag
Counter underflow has not occurred.
Counter underflow has occurred.
Bit 6
IRQA Interrupt Flag
Port A interrupt has not occurred.
Port A interrupt has occurred.
Bit 5
IRQB Interrupt Flag
Port B interrupt has not occurred.
Port B interrupt has occurred.
o
COUNTER MODE CONTROL REGISTER (CMCR)
The 8-bit Counter Mode Control Register (CMCRl selects the
CounterfTimer mode of operation and enables or disables both
the internal IROT and the Prescaler. The format of the CMCR is:
7
6
5
4
3
IROT
Enabled
0
0
Prescaler
Enabled
0
Bit 7
0
1
1
Bits 6-5
Bit
4-0
Prescaler Enabled
Prescaler Oisabled (.;. 11
Prescaler Enabled (.;. 16)
Bit 3
Not used, don't care value during write.
o
Bits 2-0
210
000
o 0 1
010
o 1 1
0
0
1
1
0
Counter/Timer Mode
Mode O-Oisable CounterfTimer
Mode 1-0ne-Shot Interval Timer
Mode 2-Free-Run Interval Timer
Mode 3-Pulse Width Measurement
Mode 4-Event Counter
Mode 5-0ne-Shot Pulse Width Generation
Mode 6-Free-Run Pulse Generation
Mode 7-Retriggerable Interval Timer
LOWER LATCH (LL)
The Lower Latch (LL) holds the least significant 8-bits of the
16-bit latch value. The LL is written from the data bus (00-07)
when the register address is 2 and RiW is low. When the LL
is loaded, the contents of the UC are copied into the Snapshot
Latch (SL) without affecting the counting operation of the UC.
UPPER LATCH (UL)
The Upper Latch (UL) holds the most significant 8-bits of the
16-bit latch value. The UL is written from the data bus (00-07)
when RiW is low and the register address is either 0 or 1. The
difference in the two regi~ter address functions are:
The CMCR can be written into at any time without disabling or
stopping the Countermmer. This allows the CounterfTimer mode
of operation to be changed while it is still in operation. However,
selecting Mode 0 disables the Countermmer and stops its operation. The Prescaler and the IROT interrupt can also be enabled
or disabled at any time. The CMCR is written to when the register
address is 3 and RiW is low.
Register Address 0
1. The UL is loaded from 00-07.
2. The contents of the latches (U Land LL) are transferred to
the counters (UC and LC, respectively).
3. The UF bit is cleared in the SR.
4. The Counter is enabled, i.e., the count in UC and LC is decremented by one upon detection of a rising edge on either
02 or CNTR (depending upon mode selection) as scaled by
the Prescaler.
STATUS REGISTER (SR)
The 8-bit Status Register (SRl reports the status of three interrupt conditions: Counter underflow (IROT), Port A interrupt
(lROA) and Port B interrupt (IROB). The format of the Status
Register is:
7
6
5
4
3
2
1
0
UF (IROT)
Interrupt
Flag
IRQA
Interrupt
Flag
IROB
Interrupt
Flag
1
1
1
1
1
Not used, always read as shown in register
figure_
The Counter Underflow (UF) Interrupt, bit 7, is updated in the
same clock cycle that an underflow condition occurs on the
CounterfTimer. The IROA and IROB interrupt flags (bits 6 and
5) are updated at the rising edge of the next 02 clock immediately
following the setting of corresponding interrupt bits in the CRA
register. The IROA Interrupt Flag is set whenever the IROA 1 or
IROA2 bit is set. The IROB Interrupt Flag is set whenever the
IROBI or IROB2 bit is set. The Counter Underflow bit is cleared
whenever the Snapshot Latch is read, the Upper Latch (ULl is
written to at register address 0, Mode 0 is selected in the CMCR,
or a RES occurs. The Status Register is read when the register
address is 3 and RiW is high.
Not used, don't care value during write.
Bit 4
o
o
Countermmer Mode
IRQT Enabled
IROT Oisabled
IROT Enabled
o
1
2
o
Register Address 1
1. The UL is loaded from DO-D7.
2. All other elements of the CounteriTimer are unaffected.
1-84
Peripheral Interface Adapter{Timer (PlAT)
R65C24
LOWER COUNTER (LC)
UL and LL values are loaded into the UC and LC, respectively,
_and the counter is enabled. The counter then decrements one
count for every positive edge (low to high) transition detected
on the 02 or CNTR input (depending on the selected mode) as
scaled by the Prescaler. In most modes, each time the counter
underflows below $0000, the underflow bit is set in the SR, the
counter reloads to the latch value and the down-counting continues. If the UF bit is set when the IROT is enabled in the
CMCR, the IRQ output will be asserted to the processor.
The Lower Counter (LC) holds the least significant 8-bits of the
16-bit counter.
When the LC decrements below $00, 1 is borrowed from the
UC to load $FF into the LC.
The LC is read to the data bus (DO-D7) when the register
address is 2 and R/Vii is high. When LC is read, the 8-bit contents of the UC is transferred to the Snapshot Latch without
affecting the operation of the counter (i.e., the count-down continues without interruption).
MODE O-DISABLE COUNTER/TIMER
The Counter/Timer is disabled (all counting stops), the IRQT
interrupt (bit 7 in the CMCR) is disabled, and the counter underflow (bit 7 in the SR) is cleared. Mode 0 may be selected at any
time by selecting Mode 0 in the CMCR or upon RES which
initializes the CMCR to $00. Selecting Mode 0 in the CMCR
does not affect any data in the LL or UL, any count in the LC
or UC, or any data in the SL.
UPPER COUNTER
The Upper Counter (UC) holds the most significant 8-bits of the
16-bit counter. The UC is read to the data bus (DO-D7) when
the register address is 1 and R/W is high. When the UC is read,
there is no other effect on the Counter/Timer operation. Counter
underflow occurs when the LC borrows a 1 from an UC value
of $00.
MODE 1-0NE SHOT INTERVAL TIMER
The counter counts down once from the latch value at the 02
clock rate (as scaled by the Prescaler) and sets the UF bit in
the SR upon underflow. The counter starts when data is written
to the UL at register address 0, which causes the UL and LL
values to be loaded into the UC and LC, respectively. When the
counter decrements below $0000, the UF bit in the SR is set.
The set UF bit causes IRQ to be asserted if the IROT Enable
bit is set in the CMCR. Upon decrementing below $0000, the
UC and LC are automatically reset to a value of $FFFF and the
counter continues down-counting. However, the UF bit in the
SR will not be set again (due to the counter again decrementing
through $0000) until the UL is again written at register address
O. The CNTR line is not used in this mode. Figure 6 shows the
timing relationship for Mode 1 operation.
Note:
When reading the UC directly, the value read can be one
count too high if the LC value is just above $00 at the
start of the read since an underflow in the LC will result
in decrementing the UC by one count. The Snapshot
Latch should be read to obtain the UC value corresponding to the LC value.
SNAPSHOT LATCH (SL)
The Snapshot Latch holds the value of the UC corresponding
to the LC value. The SL is loaded with the value of the UC when
the LL is written to, or when the LC is read. The SL is read to
the data bus (DO-D7) when the register address is 0 and R/W
is high, without affecting the counting operation. When the SL
is read, the UF in the SR is cleared. Since the SL is loaded with
the value of the UC whenever the LC is read, an accurate count
of the total 16-bit counter can be made without the need for
further calculations to account for delays between the reading
of the LC and the UC.
Typical Application: Can be used for an accurate time delay
such as would be required to control the duration of time to have
a thermal printer element activated.
MODE 2-FREE-RUN INTERVAL TIMER
The counter repetitively counts down at the 02 clock rate, as
scaled by the Prescaler, and sets the UF bit in the SR each time
the counter underflows. The counter is initialized to the UL and
LL values and starts down counting at the clock rate when the
UL value is written to register address O. Each time the counter
decrements below $0000, the UF bit in the SR is set, the counter
is reloaded with the UL and LL value, and the count-down cycle
continues. If the IRQT Enable bit is set in the CMCR, IRQ will
be asserted upon each time-out. The CNTR line is not used in
this mode. Figure 7 shows the timing relationship for Mode 2
operation.
COUNTERfTlMER OPERATION
The Counter/Timer has eight modes of operation. The Counter/
Timer is always either disabled (mode 0) or operating in one of
the other seven modes as selected in the Counter Mode Control
Register (CMCR).
To operate the Counter/Timer, first issue Mode 0 to stop any
counting in progress due to a previously selected mode, to clear
the counter underflow bit in the SR and to disable the IROT
interrupt. The order of mode selection and latch loading depends
upon the desired mode. Generally, if a timer mode based on the
02 clock rate is to be selected, first select the mode then write
the timer initialization value to the latch. Write the LL first then
the UL value (to register address 0). When the UL is written, the
Typical Application: Can be used for a timed interrupt structure when a hardware location needs updating at specific intervals, such as would be required to update a multiplexed display.
1-85
R65C24
Peripheral Interface Adapterrrimer (PlAT)
WRITE
UPPE~A~~~C~--""""
~':
IRQ-----~-------'n~~---~
READ
1
1.'-----..J
N + 2
f------CYCLES-----l
STATUS_~_ _ _ _ _ _ _ _ _ _~)~)------~l
~ _ _ _ _ _ _ _ _ _ _ __
"l~
REGISTER
READ
,
r\.
SNAPSHOT-------------~(~V-------l~~~----J
~-------
LATCH
Figure 6. Mode 1-0ne-Shot Interval Timer Timing
""m~~~~);_'--l~"'-----(ADDR 0)
' "
IRQ
_
READ
STATUS
REGISTER
READ
:__.
__
/
t'
()~
-CYCLES---I----N + 1 CYCLES
_ ~
,"
N + 2
tV
t')~
'-t(~'-----_T(V(~-----------~
SNAPSHOT----~a~l----~I~V---~~~
~(~'------------
LATCH
Figure 7. Mode 2-Free-Run Interval Timer Timing
1-86
\
R65C24
Peripheral Interface Adapter/Timer (PlAT)
MODE 3-PULSE WIDTH MEASUREMENT
Typical Application: Can be used to measure the duration of
an event from an external device. Allows an accurate measurement of the duration of a logical low pulse on the CNTR line.
The counter counts down from the latch value at the 02 clock
rate (scaled by the Prescaler) from the time the CNTR input goes
low until CNTR goes high to provide a measurement of the CNTR
low pulse duration. The counter is loaded with the value of the
ULand LL upon writing UL to register address O. The counter
starts decrementing at the scaled 02 clock rate when the CNTR
line goes low and stops decrementing when the CNTR line
returns high. If the counter decrements below $0000 before the
CNTR line goes high, the UF bit in the SR is set, the counter
is reloaded with the UL and LL value, and the cycle continues
down until CNTR goes high. Once the CNTR line has cycled
from high to low and back to high, the Counterrrimer will ignore
any additional high to low transitions on the CNTR line. To
reinitiate Mode 3, it is necessary to reload the UL by writing to
register address O. Figure 8 shows the timing relationships for
a Mode 3 operation.
$2
c"m~
MODE 4-EVENT COUNTER
CNTR is an input and the Counterrrimer counts the number of
positive transitions on CNTR. The counter is initially loaded with
the UL and LL value when the UL is written to register address O.
The counter then decrements one count on the falling edge of
the CNTR input aiter a falling edge (high-to-Iow transition) is
detected on the 02 clock. The maximum rate at which this failing edge can be detected is one-half the 02 clock rate. When
the counter decrements below $0000, the UF bit in the SR is
set, the counter is reloaded with the UL and LL value and the
operation repeats. Figure 9 shows the timing relationship of a
Mode 4 operation.
Typical Application: Can be used with a timed software loop
to count external events (i.e., a frequency counter).
L
I I I I J)j ~=.:,a""",,;'----.L..---JI
TIMER DOES NOT DECREMENT
_:
_, _, _.
Figure 8.
Mode 3-Pulse Width Measurement Timing
.
,
I
CNTR ~,--_ _-,I
COUNTER
DECREMENTED
I
~
\
1
COUNTER
DECREMENTED
PAST $0000, UF BIT SET
AND UC, LC RELOADED FROM UL, LL
.\
1
COUNT'-ER-----'
DECREMENTED
.\.
I
1
\'--_ _ _ _ _....J
READ
,---..
SNAPSHOT----------------------------~{
,'------LATCH
Figure 9.
Mode 4-Event Counter Timing
1-87
o
Peripheral Interface Adapterrrimer (PlAT)
R65C24
owhich also starts the counter. The counter decrements at the
MODE 5-0NE-SHOT PULSE WIDTH GENERATION
02 clock
rate as scaled by the Prescaler. When the counter
decrements below $0000, CNTR toggles from low to high (or
high to low depending upon its initial state), the counter is
reloaded with the UL and LL value and the counter continues
down-counting. The UF bit in the SR is set the first time the
counter decrements past $0000 and is cleared only if a new write
to UL at register address 0 occurs. Figure 11 shows the timing
relationship of a Mode 6 operation.
CNTR is an output which can be pulsed low for a programmed
time interval. When this mode is selected in the CMCR, the
CNTR output goes high if the UF bit is set. It goes low if the
UF bit is cleared. The CNTR line then goes low when data is
written to the UL at register address 0, which also starts the
counter. The counter decrements from the UL and LL value at
the 02 clock rate as scaled by the Prescaler. When the counter
decrements below $0000, the CNTR output goes high, the UF
bit is set in the SR, the counter is reloaded wtth $FFFF and the
count-down continues. Figure 10 shows the timing relationship
of Mode 5 operation.
This mode can be used to generate an asymmetrical waveform
by toggling the UL and LL with the CNTR high and low times.
Immediately after starting the counter with the first CNTR low
time, load the LL and UL (by writing to register address 1, which
does not restart the counter) with the CNTR high time. When
the first counter underflow occurs, the counter loads the new
latch value (i.e., the CNTR high time) into the counter and continues counting. During the I RQ interrupt processing resulting
from the first counter time-out, load the LL and UL (at register
address 1) with the original CNTR low time. Continue to alternate loading of the high and low time latch values during the
interrupt processing for the duration of the mode.
Note that clearing the UF bit after it is set upon the first timeout
causes CNTR to go low, in which case CNTR will again go high
upon the next counter timeout.
Typical Application: Can be used to hold-off (delay) an extemal
hardware event on an asynchronous basis such as disallowing
a motor startup until certain parameters are met.
MODE 6-fREE-RUN PULSE GENERATION
CNTR is an output and the CounterfTimer can be programmed
to generate a symmetrical waveform, an asymmetrical waveform,
or a string of varying width pulses on CNTR. The CNTR line is
forced low when data is written to the UL at register address
Typical Application: Can be used to supply external circuitry
with a software variable clock based upon the system 02 clock
(e.g., a tone generator for audio feedback).
CNTR~_C~;L~~~-=~.r------UNDERFLOW
FLAG
SET
Figure 10_ Mode 5-0ne-Shot Pulse Width Generation Timing
N+2_-+_ _ N+1
CYCLES
CYCLES
Figure 11. Mode 6-Free-Run Pulse Generation Timing
1-88
Peripheral Interface Adapter(Timer (PlAT)
R65C24
MODE 7-RETRIGGERABLE INTERVAL TIMER
LDA
STA
LDA
STA
The CounterlTimer operates as a timer which is retriggered, i.e.,
reinitialized to its starting value, upon detection of a negative
transition on the CNTR input. The counter is initially loaded with
the UL and LL value when the UL is written to register address O.
The counter starts decrementing at the 02 clock rate (as scaled
by the Prescaler) when a falling edge (high to low transition)
is detected on CNTR. The counter is reinitialized to the UL
and LL value whenever a falling edge is subsequently detected
on CNTR. If the counter decrements past $0000 before the failing edge is detected, the UF bit is set in the SR, the counter
is initialized to the UL and LL value and the count-down
continues.
#$Iovalue
LL
#$hivalue
ULEC
;Iower latch value
;write to lower latch
;upper latch value
;write to upper latch
;clear underflow flag, and enable
counter
The following instructions change the mode while the
CounterlTimer is in operation:
LDA
#$mode
STA
CMCR
;select desired mode, except
mode 0
;write to mode register
The change of mode operation will take effect immediately.
Thus, the Free-Run Internal Timer mode (Mode 2) could be systematically stopped by changing to the One-Shot Interval Timer
mode (Mode 1). The Counter/Timer will then halt operation
when the underflow condition occurs. This technique can also
be used to enable or disable IRQ during program execution.
Typical Application: Can be used to monitor signals that should
be periodic and can interrupt Ihe processor if the signal being
monitored does not occur within a specified time frame; such
as a synchronous motor that has fallen out of synchronization.
PRESCALER
READING THE COUNTER/TIMER
The CounterlTimer operates in either the divide by one or divide
by sixteen mode. In the divide by one mode, the counter holds
from 1 to 65,535 counts. The counter capacity is therefore 1 p.s
to 65,535 p.s at 1 MHz 02 clock rate or 0.25 p.s to 16,383 }1.S
at a 4 MHz 02 clock rate. Timer intervals greater than the maximum counter value can be easily measured by counting underflow flags or IRO interrupt requests.
To service an interrupt request, the following sequence can be
used:
BIT
BNE
LDA
LDX
The divide by sixteen prescaler can be enabled to extend the
timing interval by 16. This provides timing from 1048.56 ms
(1 MHz) to 260.21 ms (4 MHz). The prescaler clocks the
CounterlTimer at the 02 clock rate divided by sixteen, except
for Mode 4. In Mode 4, sixteen positive CNTR edges must occur
to decrement the CounterlTimer by one count.
$status
error
$LC
$SL
;get underflow flag
;check if flag is set
;get low counter value for overflow
;get high counter value for overflow
;underflow flag is cleared
By reading the LC and SL, it is possible to determine the amount
of time between the interrupt request and servicing the interrupt.
To read a timer value at any time, the suggested technique is
as follows:
LDA
$LC
LDA
$SL
INITIALIZING THE COUNTERmMER
The following program segment is one suggested technique for
initializing the Counter/Timer:
;get low counter value
;upper counter transferred to
snapshot
;any miscellaneous code to store
value if desired
;get high counter value
;Data Definition
SL
UC
LC
SR
ULEC
UL
LL
CMCR
=
=
=
=
=
=
=
=
$XXXO
$XXX1
$XXX2
$XXX3
$XXXO
$XXX1
$XXX2
$XXX3
;Snapshot Latch
;Upper Counter
;Lower Counter
;Status Register
;Upper Latch and Enable Counter
;Upper Latch
;Lower Latch
;Counter Mode Control Register
READIWRITE TIMING
CHARACTERISTICS OF PlAT
Figure 13 is a timing diagram for the R65C24 PlAT during a Read
operation (input mode). Figure 14 is a timing diagram for the
PlAT during a Write operation (output mode).
; Program
LDA
STA
LDA
#$modeO
CMCR
#$mode
STA
CMCR
;disable CounterlTimer
;write to mode register
;select mode and Prescaler and
IROT enable/disable
;write to mode register
1-89
D
R65C24
Peripheral Interface Adapter/Timer (PlAT)
CNTR---.......
UNDERFLOW MUST
OCCUR BY THIS TIME TO
SET UNDERFLOW FLAG
1 - - - - - - TIME DECREMENTS,
POSSIBLE TO>--+---TIMER STILL DECREMENTS
SET UNDERFLOW FLAG
IF NO UNDERFLOW HAS
OCCURRED
Figure 12. Mode 7-Retriggerable Interval Timer Timing
~~~~~===t===l=======!===========
PBO·PB7 ~
PAO·PA7
00·07
DATA OUT
CA2
(PULSE OUT)
CA1
CA2
(HAND SHAKE)
Figure 13. Read Timing Diagram
1·90
Peripheral Interface Adapterrrimer (PlAT)
R65C24
D
ii\2
RSO, RS1, RS2
CSO,CS2
RIW
DO-D7
DATAIN _ _ _ __
PAO-PA7 ?::7~~I1"'2"l!"l!"l!T~~
PBO-PB7
Ji'---ii-------+------------
~~~~~~~~~~~~------------~------------------------
CB2
(PULSE OUT)
CBl
CB2
(HAND SHAKE)
Figure 14. Write Timing Diagram
READING THE PERIPHERAL A 1/0 PORT
when the Peripheral Output register contains a logic 1. In this
case, the processor will read a 0 from the Peripheral A pin, even
though the corresponding bit in the Peripheral Output register
is a 1.
Performing a Read operation with RS1 = 0, RSO = 0 and the
Data Direction Register Access Control bit (CRA-2) = 1, directly
lines to the data bus.
transfers the data on the Peripheral A
In this situation, the data bus will contain both the input and
output data. The processor must be programmed to recognize
and interpret only those bits which are important to the particular
peripheral operation being performed.
va
READING THE PERIPHERAL B I/O PORT
va
Reading the Peripheral B
port yields a combination of input
and output data in a manner similar to the Peripheral A port.
However, data is read directly from the Peripheral B Output
Register (ORB) for those lines programmed to act as outputs.
It is therefore possible to load down the Peripheral B Output
lines without causing incorrect data to be transferred back to the
processor on a Read operation.
va
Since the processor always reads the Peripheral A
port pins
instead of the actual Peripheral Output Register (ORA), it is possible for the data read by the processor to differ from the contents of the Peripheral Output Register for an output line. This
is true when the I/O pin is not allowed to go to a full + 2.4 Vdc
1-91
Peripheral Interface Adapter/Timer (PlAT)
R65C24
SWITCHING CHARACTERISTICS
(Vee = 5.0 Vdc ± 50fa, Vss = 0, TA = TL to T H, unless otherwise noted)
BUS TIMING
2 MHz
1 MHz
Parameter
3 MHz
4 MHz
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
~2 Cycle
tCYC
1.0
-
0.5
-
0.33
-
0.25
pS
~2 Pulse Width
tc
450
-
220
-
160
110
-
~2 Rise and Fall Time
trcI
25
-
15
-
-
10
ns
-
70
-
53
ttc
-
12
ns
Read
35
-
ns
0
-
ns
110
-
75
-
ns
-
105
-
85
ns
-
20
-
20
-
ns
-
35
-
'ns
45
-
ns
0
-
ns
0.5
pS
0.5
pS
Address Set-Up Time
t ACR
140
Address Hold Time
0
Peripheral Data Set-Up Time
tCAR
tpCR
300
-
150
-
Data Bus Delay Time
tCOR
-
335
-
145
Data Bus Hold Time
tHR
20
-
0
20
0
Write
70
-
53
-
0
-
0
-
90
-
67
0
-
0
-
90
-
67
-
10
-
10
-
1.0
-
2.0
-
-
150
Address Set-Up Time
tACW
140
Address Hold Time
0
RIW Set-Up Time
tCAW
t wcw
180
RIW Hold Time
tcww
0
Data Bus Set-Up Time
180
Data Bus Hold Time
tocw
I HW
10
Peripheral Data Delay Time
!cpw
Peripheral Data Delay Time
10 CMOS Level
tCMOS
-
-
-
0.5
-
0.5
1.0
-
0.7
-
110
-
0.5
0.5
1.0
0
45
10
-
ns
ns
ns
PERIPHERAL INTERFACE TIMING
Peripheral Data Set-Up
tpCR
~2 Low to CA2 Low Delay
~2 Low to CA2 High Delay
tCA2
t RS1
~2 Low to CNTR Low/High Delay
tCNTA
CA 1 Active to CA2 High Delay
300
-
ns
0.5
pS
0.5
pS
0.5
pS
-
1.0
pS
0.5
-
0.5
pS
0
0.5
0
0.37
pS
0.5
-
0.5
-
0.5
pS
-
1.0
0.67
0.5
pS
-
1.0
-
1.0
pS
-
-
1.0
-
1.0
1.0
t RS2
-
2.0
-
1.0
-
02 High to CB2 Low Delay
tCB2
-
1.0
-
0.5
-
Peripheral Data Valid to CB2 Low Delay
0
1.5
0
0.75
~2 High to CB2 High Delay
toc
t RS1
-
1.0
-
CBl Active to CB2 High Delay
t RS2
2.0
CAl, CA2, CB1 and CB2
Input Rise and Fall Time
tr,tf
-
1.0
-
0.5
0.5
0.5
0.5
1.0
NOTE: Timing measurements are referenced to and from a low voltage of 0.8 Vdc and a high voltage of 2.0 Vdc.
1-92
75
-
-
Peripheral Interface Adapter/Timer (PlAT)
R65C24
ABSOLUTE MAXIMUM RATINGS*
Symbol
Value
UnIt
Supply Voltage
Parameter
Vee
-0.3 to + 7.0
Vde
Input Voltage
V'N
VOUT
Output Voltage
Operating Temperature Range
Commercial
Industrial
TA
Storage Temperature
TSTG
"NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in other sections of this document is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
- 0.3 to Vee + 0.3 Vdc
- 0.3 to Vce + 0.3 Vdc
·C
o to + 70
-40 to +85
-55 to + 150
·C
OPERATING CONDITIONS
Symbol
Value
Supply Voltage
Parameter
Vee
5V ±5%
Temperature Range
Commercial
Industrial
TA
TL 10 TH
O·C to 70·C
- 40·C to + 85·C
ELECTRICAL CHARACTERISTICS
= 5.0 Vdc ±5%, Vss = 0, TA = h to TH,
(Vee
Parameter
Volt~e_
AI~x~ RIW, CS2
Input High
unless otherwise noted)
Symbol
V'H
R/W, CS2
Min.
Max.
Unit'
Test Conditions
V
+2.0
+2.4
Input Low Voltage
V'L
Inpu!J.e~e
I'N
-
Input Leakage Current for Three-State Off
00-07, PBO-PB7, CB2
ITS'
-
Input High Current
PAO-PA7, CA2
I'H
Input Low Current
PAO-PA7, CA2
I'L
Output High Voltage
Logic
PBO-PB7, CB2 (Darlington Drive)
VOH
Output Low Voltage
PAO-PA7, CA2, PBO-PB7, CB2
00-07, IRQ, CNTR
VOL
Output High Current (Sourcing)
Logic
PBO-PB7, CB2 (Darlington Drive)
IOH
Output Low Current (Sinking)
PAO-PA7, PBO-PB7, CB2, CA2
00-07, IRQ, CNTR
IOL
Current
RIW, RES, RSO, RS1, CSO, CS2, CAl,
CB1, ¢2
RS2
Typ.3
-0.3
-
Vec
Vee
+0.8
V
pA
-200
±1
±2.5
±1
±10
±2
±10
-400
-
-2
2.4
1.5
-
-
-
-200
-3.2
3.2
1.6
-1500
-6
-
-3.2
+0.4
~A
V,N = O.4V to 2.4V
Vee = 5.25V
pA
V'H
= 2.0V
rnA
V'L
= 0.8V
V
Vee = 4.75V
ILOAO' = - 200~A
ILOAD' = - 3.2mA
V
Vee = 4.75V
ILOAD = 3.2 rnA
ILOAD = 1.6 rnA
-
pA
rnA
-
rnA
rnA
Output Leakage Current (Off State)
IRQ
10FF
-
1
±10
~A
Power Dissipation
PD
-
7
10
mW/MHz
Input Capacitance
00-07, PAO-PA7, PBO-PB7, CA2, CB2
R/Vii, RES, RSO, RS1, RS2, CSO, CS2,
CNTR, CAl, CB1, ¢2
C'N
-
-
-
-
10
7
20
pF
pF
pF
-
10
pF
-
Output Capacitance
COUT
Notes:
1. All units are direct current (dc) except capacitance.
2. Negative sign indicates outward current flow, positive indicates inward flow.
3. Typical values are shown lor Vee = 5.0V and TA = 25·C.
1-93
V'N = OV to Vee
Vee = 5.25V
VOL
= 2.4V
= 1.5V
= O.4V
VOH
Vee
= 2.4V
= 5.25V
VOH
VOH
Vee = 5.0V
V'N = OV
f = 2 MHz
TA = 25·C
D
Peripheral Interface Adapter/Timer (PlAT)
R65C24
PACKAGE DIMENSIONS
40-PIN CERAMIC DIP
MILLIMETERS
[ D ::I]
.\
I~
~F
?Ck.in
t
H~~LD
!
G
-11-
MIN
MAX
MIN
MAX
A
5029
5131
1980
2.020
B
1511
15.B8
0.595
0625
C
2.54
419
0100
0165
D
038
0.53
0015
0021
076
127
0030
0050
F
A
M-j
K ---J
G
...jGi-
F
0
076
1.78
0.030
0.070
0.20
0.33
0.013
0.605
K
2.54
4.19
0008
0100
L
1460
15.37
0.575
M
0°
10°
0°
10°
N
051
1.52
0.020
0060
44-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
'-~~~'I
1~t:D2-j
11f.
lH
!!
CORNER
?
39-
CHAM.J x 45·
~~
~~
1~
·O~
+
]
:<~
~
CHAM.
h x 45·
3 PLCS
11 PINS
PER SIDE
EQUALLY
SPACES
MAX
2040
2060
B
13.46
1397
0530
0.550
C
356
508
0.140
0.200
D
0.38
053
0015
0.021
F
102
152
0.040
sse
2.54
0060
asc
0100
H
1.65
2.16
0.065
I 0085
J
020
0.30
K
3.30
4.32
0.008
0.130
0012
0.170
esc
L
1524
M
7°
100
N
0.51
1.02
a 600 esc
I
70
0.020
10°
0040
MILLIMETERS
MIN
MAX
MIN
MAX
A
4.14
439
0.163
0,173
0058
A1
137
147
0.054
A2
231
246
0091
~
A
~'l
SECTION A-A
TYP FOR BOTH AXIS (EXCEPT FOR BEVELED EDGE)
~i-cb
EJECTOR PIN MARKS
4 PLCS BOTTOM OF
PACKAGE ONLY
(TYPICAL)
BOTTOM VIEW
1-94
0097
0.018 TYP
17.45
17.60
01
1646
1656
0.648
I 0693
I 0.652
12.62
12.78
0497
0503
.
.
0457 TYP
02
03
~~.
INCHES
DIM
0
~.~
In. ll1IlIU
~ Ice
MIN
5232
b
SIDE VIEW
TOP VIEW
~03.
~~
~
_u
MAX
51.B2
-
J
2.
INCHES
MIN
A
SEATING PLANE
r
.~,
INDICATOR
L-17
V
0165
DIM
G
M
K
O.100BSC
J
MILLIMETERS
-+
~~
+1--
esc
2.54
H
40-PIN PLASTIC DIP
~:: :::: ::~:::::: :::PCICI
INCHES
DIM
1575 REF
127
esc
0687
0620 REF
0050
esc
h
1.15 TYP
0.045 TYP
J
0.25 TYP
0010 TYP
.
45° TVP
45° TYP
A
089 TVP
0035 TYP
R1
025 TVP
0.010 TYP
R65C51
'1'
R65C51
Asynchronous Communications
Interface Adapter (ACIA)
Rockwell
DESCRIPTION
FEATURES
The Rockwell CMOS R65C51 Asynchronous Communications
Interface Adapter (ACIA) provides an easily implemented, program controlled interface between 8-bit mi~roprocessor-based
systems and serial communication data sets and modems.
•
•
•
•
•
•
The ACIA has an internal baud rate generator. This feature
eliminates the need for multiple component support circuits, a
crystal being the only other part required. The Transmitter baud
rate can be selected under program control to be anyone of
15 different rates from 50 to 19,200 baud, or '/'6 times an external clock rate. The Receiver baud rate may be selected under
program control to be either the Transmitter rate, or at '/'6 times
an external clock rate. The ACIA has programmable word
lengths of 5, 6, 7, or 8 bits; even, odd, or no parity; 1, 1'/2, or
2 stop bits.
•
•
•
•
•
•
•
•
The ACIA is designed for maximum programmed control from
the microprocessor (MPU), to simplify hardware implementation.
Three separate registers permit the MPU to easily select the
R65C51 's operating modes and data checking parameters and
determine operational status.
•
•
Low power CMOS N-well silicon gate technology
Replacement for NMOS R6551 ACIA
Full duplex operation with buffered receiver and transmitter
Data set/modem control functions
Internal baud rate generator with 15 programmable baud
rates (50 to 19,200)
Program-selectable internally or externally controlled receiver
rate
Programmable word lengths, number of stop bits, and parity
bit generation and detection
Programmable interrupt control
Program reset
Program-selectable serial echo mode
Two chip selects
1 or 2 MHz operation
5.0 Vdc ± 5% supply requirements
Wide range of packages available
- 28-pin ceramic or plastic DIP
- 28-pin plastic leaded chip carrier (PLCC)
Full TTL compatibility
Compatible with R6500, R6500/' and R65COO microprocessors
Ira!Ui
g =I;e NI~
a:uO>lI:s_
R/W
vss
CSO
.2
CS,
IRQ
RES
RxC
XTLI
07
06
05
XTLO
O.
RTS
CTS
03
02
CTS
TxO
0'
OTR
TxO
OTR
RxO
":l")N"'re~~
RSO
RS'
Vee
Document No. 29651N60
10
11
25
2.
23
22
2,
20
'9
07
06
05
D.
03
02
01
~~:!~~t::~
UjC Ill: 0
co ....
~12~~g~Q
28-PIN PLCC
28-PIN DIP
Figure 1.
PIN 1
INOICATOR
RTS
DO
DSR
OCD
0
RxC
XTLI
XTLO
R65C51 ACIA Pin Assignments
Product Description
1-95
Order No. 2157
Rev. 5, June 1987
D
R65C51
Asynchronous Communications Interface Adapter (ACIA)
ORDERING INFORMATION
Data Bus (00-07)
The eight data line (00-07) pins transfer data between the
processor and the ACIA. These lines are bi·directional and are
normally high·impedance except during Read cycles when the
ACIA is selected.
Part Number:
R6SCSl
L
Chip Selects (CSO, CS1)
Frequency
1 = 1 MHz
2 = 2 MHz
The two chip select inputs are normally connected to the proc·
essor address lines either directly or through decoders. The ACIA
is selected when CSO is high and CSl is low. When the
ACIA is selected, the internal registers are addressed in
accordance with the register select lines (RSO, RS1).
Package
C = 28·Pin Ceramic DIP
P = 28·Pin Plastic DIP
J = 28-Pin PIas1ic Leaded
Chip Carrier (PLCC)
Register Selects (RSO, RS1)
The two register seleC1lines are normally connected to the proc·
essor address lines to allow the processor to select the various
ACIA internal registers. Table 1 shows the internal register select
decoding.
INTERFACE SIGNALS
Figure 1 (front page) shows the R65C51 ACIA pin assignments
and Figure 2 groups the signals by functional interface.
Table 1.
ACIA Register Selection
Regis1er Operation
MICROPROCESSOR INTERFACE
RSl
RSO
R/W = Low
L
L
Write Transmit Data
Register
Read Receiver
Data Register
L
H
Programmed Reset
(Data is "Don't
Care")
Read Status
Register
H
L
Write Command
Register
Read Command
Register
H
H
Write Control
Register
Read Control
Register
Reset (RES)
During system initialization, a low on the RES input causes a
hardware Reset to occur. Upon Reset, the Command Register
and the Control Register are cleared (all bits set to 0). The Sta·
tus Register is cleared with the exception of the indications of
Data Set Ready and Data Carrier Detect, which are externally
controlled by the DSR and DCD lines, and the Transmitter Empty
bit, which is set. RES must be held low for one 02 clock cycle
for a reset to occur.
R/W = High
The Command Register controls parity, receiver echo mode,
transmitter interrupt control, the state of the RTS line, receiver
interrupt control, and the state of the DTR line.
Input Clock (1/12)
The input clock is the system 02 clock and clocks all data trans·
fers between the system microprocessor and the ACIA.
The Control Register controls the number of stop bits, word
length, receiver clock source, and baud rate.
Read/Write (RM)
The Status Register indicates the states of the IRQ, DSR, and
DCD lines, Transmitter and Receiver Data Registers, and Overrun, Framing, and Parity Error conditions.
The Rfiiii input, generated by the microprocessor controls the
direC1ion of data transfers. A high on the Rfiiii pin allows the
processor to read the data supplied by the ACIA, a low allOws
a write to the ACIA.
The Transmitter and Receiver Data Registers are used for
temporary data storage by the ACIA Transmit and Receive
circuits.
Only the Command and Control registers can be both read and
written. The programmed Reset operation does not cause any
data transfer, but is used to clear bits 4 through 0 in the Com·
mand register and bit 2 in the Status Register. The control
Register is unchanged by a programmed Reset. It should be
noted that the programmed Reset is slightly different from the
hardware Reset (RES); refer to the register description.
Interrupt Request (IRQ)
The IRQ pin is an interrupt output from the interrupt control logic.
It is an open drain output, permitting several devices to be con·
nected to the common IRQ microprocessor input. Normally a
high level, IRQ goes low when an interrupt occurs.
1-96
R65C51
Asynchronous Communications Interface Adapter (ACIA)
0
CTS
TxD
IRQ
MICROPROCESSOR
INTERFACE
DCD
R/W
CSO
DSR
CS1
RxC
RSO
XTLI
RS1
XTLO
MODEM
INTERFACE
112
DTR
RES
RTS
VCC
RxD
VSS
Figure 2.
ACIA Interface Diagram
ACIA/MODEM INTERFACE
mode results if the internal baud rate generator is selected for
receiver data clocking.
Crystal Pins (XTLI, XTLO)
Request to Send (ATS)
These pins are normally directly connected to a parallel mode
external crystal (1.8432 MHz) to derive the various baud rates.
Note that capacitors are required from XTLI to ground and from
XTLO to ground. Alternatively, an externally generated clock can
drive the XTLI pin, in which case the XTLO pin must float.
The RTS output pin controls the modem from the processor.
The state of the RTS pin is determined by the contents of the
Command Register.
Clear to Send (CTS)
Transmit Data (TxD)
The CTS input pin controls the transmitter operation. The enable
state is with CTS low. The transmitter is automatically disabled
if CTS is high.
The TxD output line transfers serial non-return-to-zero (NRZ) data
to the modem. The least significant bit (LSB) of the Transmit
Data Register is the first data bit transmitted and the rate of data
transmission is determined by the baud rate selected or by an
external transmitter clock. This selection is made by programming the Control Register.
Data Terminal Ready (DTR)
This output pin indicates the status of the ACIA to the modem.
A Iowan DTR indicates the ACIA is enabled, a high indicates
it is disabled. The processor controls this pin via bit 0 of the Command Register.
Receive Data (RxD)
The RxD input line transfers serial NRZ data into the ACIA from
the modem, LSB first. The receiver data rate is determined by
the programmed baud rate or by an externally generated receiver
clock. The selection is made by programming the Control
Register.
Data Set Ready (DSR)
The DSR input pin indicates to the ACIA the status of the modem.
A low indicates the "ready" state and a high, "not-ready."
Data Carrier Detect (DCD)
Receive Clock (RxC)
The DCD input pin indicates to the ACIA the status of the carrierdetect output of the modem. A low indicates that the modem
carrier signal is present and a high, that it is not.
RxC is a bi-directional pin which is either the external receiver
clock input or a clock output of 16x the baud rate. The latter
1-97
R65C51
Asynchronous Communications Interface Adapter (ACIA)
FUNCTIONAL DESCRIPTION
TIMING AND CONTROL
A block diagram of the R65C51 ACIA is presented in Figure 3.
A description of each functional element of the device follows.
The Timing and Control logic controls the timing of data transfers on the internal data bus, the registers, the Data Bus Buffer,
the microprocessor data bus, and the hardware reset.
DATA BUS BUFFERS
Timing is controlled by the system 02 clock input. The chip will
perform data transfers to or from the microcomputer data bus
during the 02 high period when selected.
The Data Bus Buffer interfaces the system data lines to the
internal data bus. The Data Bus Buffer is bi-directional. When
the Rm line is low and the chip is selected, the Data Bus Buffer
writes the data from the system data lines to the ACIA internal
data bus. When the Rm line is high and the chip is selected,
the Data Bus Buffer drives the data from the internal data bus
to the system data bus.
All registers will be initialized by the Timing and Control Logic
when the Reset (RES) line goes low. See the individual register
description for the state of the registers following a hardware
reset.
INTERRUPT LOGIC
The Interrupt Logic will cause the IRQ line to the microprocessor
to go low when conditions are met that require the attention of
the microprocessor. The conditions which can cause an interrupt will set bit 7 and the appropriate bit of bits 3 through 6 in
the Status Register, if enabled. Bits 5 and 6 correspond to the
Data Carrier Detect (DCD) logic and the Data Set Ready (DSR)
logic. Bits 3 and 4 correspond to the Receive Data Register full
and the Transmitter Data Register empty conditions. These conditions can cause an interrupt request if enabled by the Command Register.
TRANSMITTER AND RECEIVER DATA REGISTERS
These registers are used as temporary data storage for the ACIA
Transmit and Receive circuits. Both the Transmitter and
Receiver are selected by a Register Select 0 (RSO) and Register
Select 1 (RS1) low condition. The ReadlWrite (RIW) line determines which actually uses the internal data bus; the Transmitter
Data Register is write only and the Receiver Data Register is
read only.
Bit 0 is the first bit to be transmitted from the Transmitter Data
Register (least significant bit first). The higher order bits follow
in order. Unused bits in this register are "don't care" bits.
I/O CONTROL
The I/O Control Logic controls the selection of internal registers
for a data transfer on the internal data bus and the direction of
the transfer to or from the register.
The Receiver Data Register holds the first received data bit in
bit 0 (least significant bit first). Unused high-order bits are "0".
Parity bits are not contained in the Receiver Data Register. They
are stripped off after being used for parity checking.
The registers are selected by the Register Select (RS1, RSO)
and ReadlWrite (Rm) lines as shown in Table 1.
Figure 3.
R65C51 ACIA Block Diagram
1-98
R65C51
Asynchronous Communications Interface Adapter (ACIA)
STATUS REGISTER
Parity Error (Bit 0), Framing Error (Bit 1),
and Overrun (Bit 2)
The Status Register indicates the state of interrupt conditions
and other non-interrupt status information. The interrupt conditions are Data Set Ready and Data Carrier Detect transitions,
Transmitter Data Register Empty and Receiver Data Register Full
as reported in bits 6 through 3, respectively. If any of these bits
are set, the Interrupt (IRQ) indicator (bit 7) is also set. Overrun,
Framing Error, and Parity Error are also reported (bits 2 through
0, respectively).
7
6
5
4
3
2
None of these bits causes a processor interrupt to occur, but they
are normally checked at the time the Receiver Data Register is
read so that the validity of the data can be verified. These bits
are self clearing (I.e., they are automatically cleared after a read
of the Receiver Data Register.)
Receiver Data Register Full (Bit 3)
o
This bit goes to a 1 when the ACIA transfers data from the
Receiver Shift Register to the Receiver Data Register, and goes
to a 0 (is cleared) when the processor reads the Receiver Data
Register.
PE
Bit 7
0
1
Bit 6
0
1
Bit 5
0
Bit 4
0
1
Bit 3
0
1
Bit 2
0
Bit 1
0
1
Bit 0
0
1
Interrupt (IRQ)
No interrupt
Interrupt has occurred
Transmitter Data Register Empty (Bit 4)
Data Set Ready (DSR)
DSR low (ready)
DSR high (not ready)
This bit goes to a 1 when the ACIA transfers data from the Transmitter Data Register to the Transmitter Shift Register, and goes
to a 0 (is cleared) when the processor writes new data onto the
Transmitter Data Register.
Data Carrier Detect (DCD)
DCD low (detected)
DCD high (not detected)
NOTE: There is a delay of approximately y" of a bit time after
the TDR becomes emptylfull before this flag is updated.
Transmitter Data Register Empty
Not empty
Empty
Data Carrier Detect (Bit 5) and Data Set Ready (Bit 6)
Receiver Data Register Full
Not full
Full
These bits reflect the levels of the DCD and DSR inputs to the
ACIA. A 0 indicates a low level (true condition) and a 1 indicates
a high level (false). Whenever either of these inputs change state,
an immediate processor interrupt (IRQ) occurs, unless bit 1 of
the Command Register (IRD) is set to a 1 to disable IRQ.
When the interrupt occurs, the status bits indicate the levels of
the inputs immediately after the change of state occurred. Subsequent level changes will not affect the status bits until after
the Status Register has been interrogated by the processor. At
that time, another interrupt will immediately occur and the status bits will reflect the new state. These bits are not automatically cleared (or reset) by an internal operation.
Overrun"
No overrun
Overrun has occurred
Framing Error"
No framing error
Framing error detected
Parity Error"
No parity error
Parity error detected
Interrupt (Bit 7)
• No interrupt occurs for these conditions
This bit goes to a 1 whenever an interrupt condition occurs and
goes to a 0 (is cleared) when the Status Register is read.
Reset Initialization
76543210
11-1-1 I I I I I
1 0 0 0 0 Hardware reset
0
. - . - . - . - . - . 0.-.-. Program reset
1-99
D
Asynchronous Communications Interface Adapter (ACIA)
R65C51
CONTROL REGISTER
Selected Baud Rate (Bits 0, 1, 2, 3)
The Control Register selects the desired baud rate, frequency
source, word length, and the number of stop bits.
These bits select the Transmitter baud rate, which can be at y"
an external transmitter clock rate or one of 15 other rates controiled by the internal baud rate generator.
7
5
6
4
3
2
o
If the Receiver clock uses the same baud rate as the transmitter (bit 4 = 1), then RxC becomes an output (at 16x the baud rate)
and can be used to slave other circuits to the ACIA. Figure 4
shows the Transmitter and Receiver layout.
Bit 7
o
1
1
Stop Bit Number (SBN)
1 Stop bit
2 Stop bits
1Y, Stop bits
For WL = 5 and no parity
1 Stop bit
For WL = 8 and parity
( 4 -.......-RxD
Word Length (WL)
No. Bits
8
7
6
5
~====-----I~RxC
XTLI'
Receiver Clock Source (RCS)
External receiver clock
Baud rate
XTLO
Selected Baud Rate (SBR)
Baud
0
0 TxC rate.;. 16'
0
1 50
1
0 75
1
1 109.92
0
0 134.58
0
1 150
1
0 300
1
1 600
0
0 1200
1 1800
0
1
0 2400
1
1 3600
0
0 4800
0
1 7200
1
0 9600
1 19,200
..!.. .Q.
'AND EXTERNAL TRANSMITTER CLOCK INPUT (TxC)
Figure 4.
Transmitter/Receiver Clock Circuits
Receiver Clock Source (Bit 4)
This bit controls the clock source to the Receiver. A 0 causes
the Receiver to operate at a baud rate of y" the external receiver
clock on pin RxC. A 1 causes the Receiver to operate at the
same baud rate as is selected for the transmitter.
Word Length (Bits 5, 6)
These bits determine the word length to be used (5, 6, 7 or 8 bits).
'XTLI is the input for the External Transmitter Clock (TxC)
Stop Bit Number (Bit 7)
Reset Initialization
This bit determines the number of stop bits used. A 0 always
indicates one stop bit. A 1 indicates 1y, stop bits if the word length
is 5 with no parity selected, 1 stop bit if the word length is 8 with
parity selected, and 2 stop bits in all other configurations.
1-100
R65C51
Asynchronous Communications Interface Adapter (ACIA)
COMMAND REGISTER
Data Terminal Ready (Bit 0)
The Command Register controls specific modes and functions.
This bit enables all selected interrupts and controls the state
of the Data Terminal Ready (DTR) line. A 0 indicates the
microcomputer system is not ready by setting the DTR line
high. A 1 indicates the microcomputer system is ready by setting the DTR line low. DTR also enables and disables the transmitter and receiver.
Bits 7-6
E-
1...
O
0
o
1
o
Bit 5
o
Bit 4
o
1
Bits 3-2
3
Receiver Interrupt Control (Bit 1)
Parity Mode Control (PMC)
This bit disables the Receiver DCD and DSR from generating an interrupt when set to a 1. The Receiver DCD and DSR
interrupts are enabled when this bit is set to a 0 and Bit 0 is
set to a 1.
Odd parity transmitted/received
Even parity transmitted/received
Mark parity bit transmitted
Parity check disabled
Space parity bit transmitted
Parity check disabled
Transmitter Interrupt Control (Bits 2, 3)
These bits control the state of the Ready to Send (RTS) line and
the Transmitter interrupt.
Parity Mode Enabled (PME)
Parity mode disabled
No parity bit generated
Parity check disabled
Parity mode enabled
Receiver Echo Mode (Bit 4)
A 1 enables the Receiver Echo Mode and a 0 disables the
Receiver Echo Mode. When bit 4 is a 1 bits 2 and 3 must be
O. In the Receiver Echo Mode, the Transmitter returns each
transmission received by the Receiver delayed by one-half bit
time.
Receiver Echo Mode (REM)
Receiver normal mode
Receiver echo mode
Bits 2 and 3 must also be zero for receiver echo
mode, RTS will be low.
Parity Mode Enable (Bit 5)
This bit enables parity bit generation and checking. A 0 disables
parity bit generation by the Transmitter and parity bit checking
by the Receiver. A 1 bit enables generation and checking of
parity bits.
Transmitter Interrupt Control (TIC)
2
o
0"
1
1
1
0
1
o
Bit 1
o
1
Bit 0
o
RTS
RTS
RTS
RTS
=
=
=
=
High, transmitter disabled*
Low, transmit interrupt enabled
Low, transmit interrupt disabled
Low, transmit interrupt disabled,
transmit break on TxD"
Parity Mode Control (Bits 6, 7)
These bits determine the type of parity generated by the Transmitter, (even, odd, mark or space) and the type of parity check
done by the Receiver (even, odd, or no check).
Receiver Interrupt Request Disabled (IRD)
IRQ enabled (receiver)
IRQ disabled (receiver)
Reset Initialization
76543210
Data Terminal Ready (OTR)
Data terminal not ready (DTR high"
Data terminal ready (DTR low)
101~0 I~ I~ I~ I~I~I :~~~~%er::~t (RES)
NOTE
*The transmitter is disabled immediately. The receiver
is disabled but will first complete receiving a byte in
process of being received .
•• A "BREAK" is transmitted only after the end of a
character stream. If the Transmitter Data Register contains a character, the "BREAK" is not transmitted.
1-101
D
Asynchronous Communications Interface Adapter (ACIA)
R65C51
STATUS REGISTER OPERATION
Reset operates somewhat differently from the hardware Reset
(RES pin) and is described as follows:
Because of the special functions of the various status bits, there
is a suggested sequence for checking them. When an interrupt
occurs, the ACIA should be interrogated, as follows:
1. Internal registers are not completely cleared. Check register
formats for the effect of a program Reset on internal registers.
1. Read Status Register
2. The DTR line goes high immediately.
This operation automatically clears Bit 7 (IRQ). Subsequent
transitions on DSR and DCD will cause another interrupt.
3. Receiver and transmitter interrupts are disabled immediately.
If IRQ is low when the reset occurs,it stays low until serviced,
unless interrupt was caused by DCD or DSR transition.
2. Check IRQ (Bit 7) in the data read from the Status Register
If not set, the interrupt source is not the ACIA.
4. DCD and DSR interrupts are disabled immediately. If IRQ is
low and was caused by DCD or DSR, then it goes high, also
DCD and DSR status bits subsequently will follow the input
lines, although no interrupt will occur.
3. Check DCD and DSR
These must be compared to their previous levels, which must
have been saved by the processor. If they are both 0 (modem
"on-line") and they are unchanged, then the remaining bits
must be checked.
5. Overrun cleared, if set.
TRANSMITTER AND RECEIVER OPERATION
4. Check RDRF (Bit 3)
Continuous Data Transmit
Check for Receiver Data Register Full.
In the normal operating mode, the interrupt request output (IRQ)
signals when the ACIA is ready to accept the next data word
to be transmitted. This interrupt occurs at the beginning of the
Start Bit. When the processor reads the Status Register of the
ACIA, the interrupt is cleared.
5. Check Parity, Overrun, and Framing Error (Bits 0-2) if the
Receiver Data Register is full.
6. Check TDRE (Bit 4)
Check for Transmitter Data Register Empty.
The processor must then identify that the Transmit Data Register
is ready to be loaded and must then load it with the next data
word. This must occur before the end of the Stop Bit, otherwise
a continuous "MARK" will be transmitted. Figure 5 shows the
continuous Data Transmit timing relationship.
PROGRAM RESET OPERATION
A program Reset occurs when the processor performs a write
operation to the ACIA with RSO low and RS1 high. The program
CHAR#n+1
CHAR#n
,/
/
TxD
CHAR#n+3
CHAR#n+2
,/
,/
,
lSt. t5""GJ~ 1~;oE1StopISt. t5Fl~ ~ lSEJStopISt"trs;Er~ lSEJStopISt."5""GJ~~ lSEJStopL
,
Lllr
/LJlj
lJlJ
l
I
I
I
I
I
I
I
I
I
I
/
~
L...J\
PROCESSOR READS STATUS
(TRANSMIT DATA
REGISTER,CAUSES iRci
PROCESSOR MUST
LOAD NEW DATA
IN THIS TIME
REGISTER EMPTY'
TO CLEAR
~O::!~~~~;;~~ARK"
PROCESSOR
INTERRUPT
Figure 5.
INTERVAL; OTHERWISE,
Continuous Data Transmit
1-102
R65C51
Asynchronous Communications Interface Adapter (ACIA)
Continuous Data Receive
Similar to the Continuous Data Transmit case, the normal
operation of this mode is to assert IRQ when the ACIA has
received a full data word. This occurs at about 9/,6 point through
the Stop Bit. The processor must read the Status Register and
CHAR#n
CHAR#n+1
/
RxC
lstart5FJ ~ ~
lSEJSto p
'-/
ls. rt5FJ ~ ~ liEJ lstart5"EJ ~ ~
S1DP
I
~
LlIr
) '-'\
PROCESSOR
INTERRUPT OCCURS
ABOUT 9/16 INTO
LAST STOP 81T.
PARITY. OVERRUN.
AND FRAMING ERROR
ALSO,UPDATED
CHAR#n+3
CHAR#n+2
'J
I
rna
read the data word before the next interrupt, otherwise the
Overrun condition occurs. Figure 6 shows the continuous Data
Receive Timing Relationship.
'-/
lSEJSto p
I
I
I
I
I
I
Lm
L
'u
~
PROCESSOR MUST READ
RECEIVER DATA IN THIS
TIME INTERVAL; OTHERWise,
OVERRUN OCCURS
PROCESSOR READS ~TUS
~~~I~!=. CAUSES IRQ
Figure 6.
""-
lstar.5FJ ~ ~ ~StopL
Continuous Data Receive
Transmit Data Register Not Loaded by Processor
When the processor finally loads new data, a Start Bit immediately occurs, the data word transmission is started, and another
interrupt is initiated, signaling for the next data word. Figure 7
shows the timing relationship for this mode of operation.
If the processor is unable to load the Transmit Data Register in
the allocated time, then the TxD line goes to the "MARK" con·
dition until the data is loaded. IRQ interrupts continue to occur
at the same rate as previously, except no data is transmitted.
CONTINUOUS "MARK"
CHAR#n
I
/
TxD
RStartrn~ ~
I
I
~~-,--'-~------5EJSto
l
I
lJr-p
_CHARACTER_I
TIME
LJlr
PRocLoR
CHAR#n+1
\
~
L....J
" . /
INTERRUPT
FOR DATA
REGISTER
EMPTV
PROCESSOR
READS
STATUS
REGISTER
INTERRUPTS
CONTINUE AT
CHARACTER RATE.
EVEN THOUGH
NO DATA IS
TRANSMITTED
Figure 7.
WHEN PROCESSOR FINALLY LOADS
NEW DATA, TRANSMISSION STARTS
IMMEDIATELY AND INTERRUPT
OCCURS. INDICATING TRANSMIT
DATA REGISTER EMPTY
Transmit Data Register Not Loaded by Processor
1·103
CHAR#n+2
D
Asynchronous Communications Interface Adapter (ACIA)
R65C51
Effect of CTS on Transmitter
bit. Then TxD goes immediately to a "MARK" condition. Bit 4 in
the Status Register indicates that the Transmitter Data Register
is not empty and IRQ is not asserted. CTS is a transmit control line
only, and has no effect on the ACIA Receiver Operation. Figure 8
shows the timing relationship for this mode of operation.
CTS is the Clear-ta-Send signal generated by the modem. It is normally low (true state) but may go high in the event of some modem problems. When this occurs, the TxD line goes to the "MARK"
condition afterthe entire last character (including parity and stop
bit) has been transmitted, unless CTS goes high during the start
CHAR#n
CHAR#n+1
CONTINUOUS "MARK"
TxD
1ftl:'i IS
/
NOT ASSERTED
AGAIN UNTIL ~
NOT CLEAR.TO.SEND
GOES LOW
CLEAR.TO·SEND
CTS Goes HIGH, INDICATING MODEM IS NOT READY TO RECEIVE DATA. TxD GOES
TO "MARK" CONDITION AFTER COMPLETE CHARACTER IS TRANSMITTED.
Figure 8.
Effect of CTS on Transmitter
Effect of Overrun on Receiver
If the processor does not read the Receiver Data Register in the
status bit is set. Thus, the Data Register will contain the last valid
data word received and all following data is lost. Figure 9 shows
the timing relationship for this mode.
allocated time, when the next interrupt occurs, the new data word
is not transferred to the Receiver Data Register, but the Overrun
CHAR#n
~/
RxO
I
CHAR#n+1
,/
I
CHAR#n+2
,/
I
CHAR#n+3
,/
'
~St. t~ ~ ~ EEJStlpIS"rt~ ~ ~ EElStjPlstart[%FI ~ EElstj+a{SO]"Bi] ~~ ~
~
PRoceSSOR
INTERRUPT
FOR RECEIVER
DATA REGISTER
FULL
RECEIVER DATA REGISTER
NOT UPDATED, BeCAUSE
PROCESSOR DID NOT READ
PREVIOUS DATA, OVERRUN
BIT SET IN STATUS
REGISTER
~
Figure 9.
OVERRUN BIT SET IN
STATUS REGISTER
Effect of Overrun on Receiver
1-104
R65C51
Asynchronous Communications Interface Adapter (ACIA)
Echo Mode Timing
o
In Echo Mode, the TxD line re-transmits the data on the RxD
line, delayed by V2 of the bit time, as shown in Figure 10.
Figure 10.
Echo Mode Timing
Effect of CTS on Echo Mode Operation
In Echo Mode, the Receiver operation is unaffected by CTS,
however, the Transmitter is affected when CTS goes high, i.e.,
the TxD line immediately goes to a continuous "MARK" condition. In this case, however, the Status Request indicates that
CHAR#n+1
CHAR#n
CHAR#n+2
I
1/
CTS
TxO
the Receiver Data Register is full in response to an IRQ, so the
processor has no way of knowing that the Transmitter has
ceased to echo. See Figure 11 for the timing relationship of this
mode.
CHAR#n+3
J.
CONTINUOUS "MARK" UNTIL
ffi GOES LOW
=::FE::I:~::~I~~ s,opr "'l"o\",l "2lJ
L
t
TS GOES TO)
I
"FALse" CONDITION
NORMAL
_
RECEIVER DATA
L-------------------------------REGI~ERFULL------------------------~
INTERRUPTS
Figure 11.
Effect of CTS on Echo Mode
1-105
R65C51
Asynchronous Communications Interface Adapter (ACIA)
Overrun in Echo Mode
"MARK" condition until the first Start Bit after the Receiver Data
Register is read by the processor. Figure 12 shows the timing
relationship for this mode.
If Overrun occurs in Echo Mode, the Receiver is affected the
same way as a normal overrun in Receive Mode. For the retransmitted data, when overrun occurs, the TxD line goes to the
CHAR #x
CHAR#n
I
r-.,--rlI-T----r-~..,/
CHAR 1Fx+1
L--L..--'--~In I IpIStopISta"R;;I~ l±JStoplsu"ffi~~ EE
~}I----'LJI]
Ull
I
"
/
BN
!-....L_L.....J==~
hD
I
i
TxO DATA
PROCESSOR FINALLY
ReSUMES
READS RECEIVER
DATA REGISTER.
LAST VALID
CHARACTER (#nl
PRoceSSOR
INTERRUPT
FORCHAR#x
PROCESSOR
INTERRUPT
fOR RECEIVER
DATA REGISTER
FULL
PROCESSOR
READS
STATUS
REGISTER
OVERRUN OCCURS
TxD GOES TO
"MARK"
IN RECEIVER
DATA REGISTER
CONDITION
Figure 12.
Overrun in Echo Mode
Framing Error
checked for the Framing Error. Subsequent data words are
tested for Framing Error separately, so the status bit will always
reflect the last data word received. See Figure 13 for Framing
Error timing relationship.
Framing Error is caused by the absence of Stop Bit(s) on
received data. A Framing Error is indicated by the setting of bit 1
in the Status Register at the same time the Receiver Data
Re~er Full bit is set, also in the Status Register. In response
to IRQ, generated by RDRF, the Status Register can also be
RxD
IEXPECTED) - ' _..........
RxC
IACTUALI - ' _..........
PROCESSOR
NOTES: 1, FRAMING ERROR DOES NOT
INTERRUPT
FRAMING
ERROR
BIT seT
INHIBIT RECEIVER OPERATION.
2. IF NEXT DATA WORD IS OK,
FRAMING ERROR IS CLEARED.
Figure 13.
Framing Error
1-106
R65C51
Asynchronous Communications Interface Adapter (ACIA)
Effect of DeD on Receiver
DCD is a modem output indicating the status 01 the carrier-Irequency-detection circuit 01 the modem. This line goes high for
a loss of carrier. Normally, when this occurs, the modem will
stop transmitting data some time later. The ACIA asserts IRQ
whenever DCD changes state and indicates this condition via
bit 5 in the Status Register.
Once such a change of state occurs, subsequent transitions will
not cause interrupts or changes in the Status Register until the
first interrupt is serviced. When the DCD input is high, the
receiver is disabled (see Figure 14).
CONTINUOUS "MARK"
,
t
NORMAL
PROCESSOR
INTERRUPT
"
AS LONG AS
D'C5 IS HIGH,
NO FURTHER
PROCESSOR
INTERRUPT
FORDCo
GOING HIGH
I
III
L_...J.LI
t
INTERRUPTS
PROCESSOR
INTERRUPT
FOR RECEIVER
WILL OCCUR
FORDeD
GOING LOW
NO INTERRUPT
WILL OCCUR
HERE, SINCE
RECEIVER IS NOT
ENABLED UNTIL
FIRST START BIT
PROCESSOR /
INTERRUPT
FOR
RECEIVER
DATA
DETECTEO
Figure 14.
Effect of DeD on Receiver
Timing with 1V2 Stop Bits
trailing half-Stop Bit. Figure 15 shows the timing relationship for
this mode.
It is possible to select 1Y2 Stop Bits, but this occurs only for
5-bit data words with no parity bit. In this case, the IRQ asserted
for Receiver Data Register Full occurs halfway through the
CHAR#n
CHAR#n+1
(
R.O
LJ]]
I
PROCESSOR INTERRUPT
OCCURS HALFWAV
THROUGHT THE 1/2
STOP BIT
Figure 15. Timing with 1Y2 Stop Bits
1-107
L
Asynchronous Communications Interface Adapter (ACIA)
R65C51
Transmit Continuous "BREAK"
NOTE
This mode is selected via the ACIA Command Register and
causes the Transmitter to send continuous "BREAK" characters, beginning with the next character transmitted. At least one
full "BREAK" character will be transmitted, even if the processor
quickly re-programs the Command Register transmit mode.
Later, when the Command Register is programmed back to
normal transmit mode, an immediate Stop Bit will be generated
and transmission will resume. Figure 16 shows the timing relationship for this mode.
If, while'operating in the Transmit Continuous "BREAK"
mode, the CTS should go to a high, the TxD will be
overridden by the CTS and will go to continuous "MARK"
at the beginning of the next character transmitted after the
CTS goes high.
~
PERIOD DURING
I - - - - - - - - f - ~EH~~~:sROCESSOR
CONTINUOUS
"BREAK" MOOE
NORMAL
INTERRUPT
POINT AT WHICH
PROCESSOR
SELECTS
NORMAL
PROCESSOR
INTERRUPT
TO LOAD
TRANSMIT
TRANSMIT
DATA
/
MODE
Figure 16.
TranslI'!it Continuous "BREAK"
Receive Continuous "BREAK"
shows the timing
characters.
In the event the modem transmits continuous "BREAK" characters, the ACIA will terminate receiving. Reception will resume
only after a Stop Bit is encountered by the ACIA. Figure 17
-------~"
RxC
CONTINUOUS "BREAK"
]~Lffiil••,·. ,', ,_
relationship
for
continuous "BREAK"
"/r----
/
," " '·Ltf-I.L.I_-,-~Fjls. rtr;FI=ffiTISt. tIBO \B,I
urr---------,l
~
j
NMOO'R-E
~
NO INTERRUPT
SINCE RECEIVER
PROCESSOR
~~TRERRUPT
RECEIVER
OATA REGISTER
FULL
PROCESSOR INTERRUPT WITH
INTERRUPTS
~::::;~~:~~L
FRAMING ERROR SET. EVEN
PARITY CHECK WILL ALSO GIVE
A PARITY ERROR BECAUSE ALL
ZEROS (CONTINUOUS BREAK)
REPRESENT EVEN PARITY.
Figure 17.
Receive Continuous "BREAK"
1-108
NORMAL
RECEIVER
INTERRUPT
R65C51
Asynchronous Communications Interface Adapter (ACIA)
CRYSTAL/CLOCK CONSIDERATIONS
To select a parallel resonant crystal for the oscillator, first select
the load capacitance from a crystal manufacturer's catalog. Next,
calculate R,ma, based on F and CL• The selected crystal must
have a Rs less than the Rsma,'
CLOCK OSCILLATOR
The on-chip oscillator is designed for a parallel resonant crystal connected between XTLI and XTLO pins. The equivalent
oscillator circuit is shown in Figure 18.
For example, if CL = 13 pF for a 1.8432 MHz parallel resonant
crystal, then
C
= (2 x 13)
- 2
= 18 pF
The series resistance of the crystal must be less than
C±5%
XTLI
2 pF
1---+-.--1 f---+...--J
J"'' '
2 pF
Rsmax =
2 x 106
== 3.3K ohms
(1.8432 x 13)2
EXTERNAL CLOCK MODES
The XTLI input may be used as an external clock input (Figure 19). For this implementation, a times 16 clock is input on
XTLI and XTLO is left open.
-=-
Figure 18_ Internal Clock
A parallel resonant crystal is specified by its load capacitance
EXTERNAL
TRANSMITTER
CLOCK
and series resonant resistance. For proper oscillator operation,
the load capacitance (C L), series resistance (R,) and the crystal resonant frequency (F) must meet the following two relations:
(C + 2) = 2CL
or
C = 2C L
-
NO CONNECTION
RS5C51
XTLO
2
RCCCQZ
RI'W
RS2
RSI
RSO
39
38
37
36
35
34
33
32
31
30
29
TxC
TxD2
OTR2
RxD2
IRQ2
RTS2
CTS2
OC02
OSR2
NC
ClK OUT
COcnO_NM .. IOUlII"'-IID
... ... N N N N N N N N N
lii a:
1II1~ I~ ~~ Ifn
~ 9
rr
a: ~ ...
cc ~
"t(
44-PIN PLCC
40-PIN DIP
NC = NO CONNECTION. NO SIGNAL SHOULD BE CONNECTED TO THIS PIN.
Figure 1.
R/W
CS
RES
'"
CONTROL LINES
8·BIT DATA LINES
MULTI·BIT
Cg~TROL LINES
Figure 3.
DACIA Block Diagram
1·120
Dual Asynchronous Communications Interface Adapter (DACIA)
R65C52
Table 3.
Register Accessed
Register Select
Lines
HEX
RS2
RSl
RSO
L
L
L
1
L
L
H
L
H
Read
Write
0
2
DACIA Register Selection
Symbol
Name
IERl
Interrupt Enable
Register 1
CRl
Control
Register l'
FRl
Format
Register 1"
CDRl
Compare Data
Register l '
ACRl
Auxiliary Control
Register l '
L
Symbol
Name
ISRl
Interrupt Status
Register 1
CSRl
Control Status
Register 1
Not Used
3
L
H
H
TDRl
Transmit Data
Register 1
RDRl
Receive Data
Register 1
4
H
L
L
IER2
Interrupt Enable
Register 2
ISR2
Interrupt Status
Register 2
CR2
5
H
L
H
Control
Register 2'
CSR2
Format
Register 2"
Control Status
Register 2
FR2
CDR2
Compare Data
Register 2'
ACR2
Auxiliary Control
Register 2'
TDR2
Transmit Data
Register 2
6
7
H
H
H
H
L
H
Notes:
1. D7 must be set low to write to the Control Registers.
2. D7 must be set high to write to the Format Registers.
3. Control Register bit 6 must be set to 0 to access the Compare Register.
4. Control Register bit 6 must be set to 1 to access the Auxiliary Control Register.
1·121
Not Used
RDR2
Receive Data
Register 2
Dual Asynchronous Communications Interface Adapter (DACIA)
R65C52
SERIAL DATA CHANNELS
is high and the Transmit Shift Register is empty, the transmitter
(except for Echo Mode) is inhibited. When CTS is low, the
transmitter is enabled.
Two independent serial data channels are available for the full
duplex (simultaneous transmit and receive) transfer of asynchronous frames. Separate internal registers are provided for each
channel for the selection of frame parameters (number of bits per
character, parity options, etc.), status flags, interrupt control and
handshake. The asynchronous frame format is shown in Figure 4.
-u-I
I
START
Transmit data from the host system is loaded into the Transmit Data
Register. From there, it is transferred to the Transmit Shift Register
where it is shifted, LSB first, onto the TxD line. All transmissions
begin with a start bit and end with the user selected number of
stop bits. A parity bit is transmitted before the stop bit(s) if parity
is enabled.
LSB
I
_____ J.I ___ lI __
I I
MSB
I
JI
Figure 4.
Asynchronous Frame Format
INTERNAL REGISTERS
Register Formats
Bit
Register
R/W
0
4
ISR1
ISR2
R
0
4
IER1
IER2
W
1
5
CSR1
CSR2
R
1
5
CR1
CR2
W
1
5
FR1
FR2
W
2
6
CDR1
CDR2
(CR6 = 0)
2
6
ACR1
ARC2
(CR6 = 1)
3
7
RDR1
RDR2
R
3
7
TDR1
TDR2
W
W
W
7
6
I
The DACIA contains ten control registers and four status registers
in addition to the transmit and receive registers. The Control
Registers provide for control of frame parameters, baud rate, interrupt generation, handshake lines, transmission and reception. The
status registers provide status information on transmit and receive
registers, error conditions and interrupt sources. Table 4 summarizes the bit definitions of these registers. A detailed description
follows.
Five 110 lines are provided for each channel for handshake with
the data communications equipment (DCE). Four of these signals
(RTS, DTR, DSR and DCD) are general purpose inputs or outputs.
The fifth Signal, CTS, enables/disables the transmitter. When CTS
Register
Select
(Hex)
II... __ J._
I
PAllITV STOP
(OPr) I (1 OR 2 BITS)
5T08B1TS~1
f
Receive data is shifted into the Receive Shift Register from the
associated RxD line. Start and stop bits are stripped from the frame
and the data is transferred to the Receive Data Register. Parity bits
may be discarded or stored in the ISA.
Table 4.
--T----il- - - - - , - - , - -,---,---r
I ___ L
I ____jf.
5
4
3
Reset
Value
76543210
o
2
1 - 00000-
- 0000000
1 - - - - 011
o
CDRI
ACR
STOP
BITS
ECHO
0- - - - - --
BITR+ESEL
1-------
COMPA~E DATA
UN~SED
TRNS
PAR
I ------00
L-____~____~______L~______L-____~____~__B_R_K__L_E_R_R/~S_T~
00000000
1-122
Dual Asynchronous Communications Interface Adapter (DACIA)
R65C52
INTERRUPT STATUS REGISTERS (ISR1, ISR2)
INTERRUPT ENABLE REGISTERS (IER1, IER2)
The Interrupt Status Registers are read-only registers indicating
the status of each interrupt source. Bits 6 through 0 are set when
the indicated IRQ condition has occurred. Bit7 is set to a 1 when
any IRQ source bit is set, or if Echo Mode is disabled, when CTS
is high.
The Interrupt Enable Registers are write-only registers that
enable/disable the IRQ sources. IRQ sources are enabled by
writing to an IER with bit 7 set to a 1 and the bit for every IRQ source
to be enabled set to a 1. IRQ sources are disabled by writing to
an IER with bit 7 reset to a 0 and the bit for every source to be disabled set to a 1. Any source bit reset to 0 is unaffected and remains
in its original state. Thus, writing $7F to an IER disables all of that
channel's interrupts and writing an $FF to an IER enables all of
that channel's interrupts.
7
6
5
4
3
2
ANY
BIT
SET
TORE
CTST
DeDT
DSRT
PAR
Address = 0,4
Bit 7
1
o
1
0
FIOIB RDRF
Reset Value = 1 - 00000 -
Any Bit Set
Any bit (S through 0) has been set to a 1 or CTS
is high with echo disabled
No bits have been set to a 1 or echo is enabled
Bit 6
1
Transmit Data Register Empty (TORE)
Transmit Data Register is empty and CTS is low
Transmit Data Register is full or CTS is high
Bit 5
1
Transition On CTS Line (CTST)
A positive or negative transition has occurred on
CTS
No transition has occurred on CTS, or ISR has
been Read
o
o
Bit 4
1
o
Bit 3
1
o
Bit 2
1
o
o
Bit 1
1
o
Bit 0
1
o
6
5
4
3
2
1
0
TORE
IE
CTST
IE
DeDT
IE
DSRT
IE
PAR
IE
FIOIB
RDRF
IE
Address = 0,4
Bit 7
1
IE
Reset Value = - 0000000
Enable/Disable
Enable selected IRQ source
Disable selected IRQ source
o
Bits 0-6
1
Select for enable/disable
No change
o
CONTROL STATUS REGISTERS (CSR1, CSR2)
The Control Status Registers are read-only registers that provide
I/O status and error condition information. A CSR is normally read
after an IRQ has occurred to determine the exact cause of the
interrupt condition.
7
Transition On DCD Line (DCDT)
A positive or negative transition has occurred on
DCD
No transition has occurred on DCD, or ISR has
been Read
FE
Address
Transition On DSR Line (DSRT)
A positive or negative transition has occurred on
DSR
No transition has occurred on DSR, or ISR has
been Read
=
TUR
2
1
0
BRK
DTR
LVL
RTS
LVL
Reset Value
= 1 _. - • 011
Transmitter Underrun (TUR)
Transmit Shift Register is empty and TDRE is set
Transmitter Shift Register is not empty
Bit 5
1
CTS Level (CTS LVL)
CTS line is high
CTS line is low
DCD Level (DCD LVL)
DCD line is high
DCD line is low
o
Bit 3
1
DSR Level (DSR LVL)
DSR line is high
DSR line is low
Bit 2
1
Receive Break (BRK)
A Receive Break has occurred
No Receive Break occurred, or RDR was read
Bit 1
1
DTR Level (DTR LVL)
DTR line is high
DTR line is low
Bit 0
1
RTS Level (ATS LVL)
RTS line is high
RTS line is low
o
o
o
o
1-123
3
DSR
LVL
BitS
1
o
Receive Data Register FuJI (RDRF)
Receive Data Register is full
Receive Data Register is empty
4
DeD
LVL
Framing Error (FE)
A framing error occurred in receive data
No framing error occurred, or the RDR was read
Bit 4
1
Frame Error, Overrun, Break
A framing error, receive overrun, or receive break
has occurred or has been detected
No error, overrun, break has occurred or RDR
has been Read
5
CTS
LVL
= 1,5
o
Parity Status (PAR)
ACRbitO
0
A parity error has occurred in received data
No parity error has occurred, or the Receive Data
Register (RDR) has been Read
ACR bit 0
1
Parity bit = 1
Parity bit = 0
6
Bit 7
1
o
=
1
7
SET
BITS
D
R65C52
Dual Asynchronous Communications Interface Adapter (DACIA)
CONTROL REGISTERS (CR1, CR2)
FORMAT REGISTERS (FR1, FR2)
The Control Registers are write-only registers. They control access
to the Auxiliary Control Register and the Compare Data Register.
They select the number of stop bits, control Echo Mode, and select
the data rate.
The Format Registers are write-only registers. They select the
number of data bits per character and parity generation/checking
options. They also control RTS and DTR.
(Accessed when Bit 7
3
= 0)
2
(Accessed when Bit 7
= 1)
o
BAUD RATE SEL
Address = 1,5
Bit 7
0
Control or Format Register
Access Control Register
Bit6
CDR/ACR
Access the Auxiliary Control Register (ACR)
Access the Compare Data Register (CDR)
1
0
Bit 5
1
0
Bit 4
1
0
3
0
0
0
0
0
0
0
0
1
Bits
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
3-0
1 0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
0
1
Address = 1,5
Resel Value = 0 - - - - - - -
Bit 7
1
Number of Stop Bits Per Character
Two stop bits
One stop bit
Echo Mode Selection
Echo Mode enabled
Echo Mode disabled
Baud Rate Selection
(bits per second with 3.6864 MHz crystal)
50
109.2
134.58
150
300
600
1200
1800
2400
3600
4800
7200
9600
19200
38400
External TxC and RxC X16 Clocks
1-124
Reset Value = 1 - - - - - - -
Control or Format Register
Access Format Register
Bits 6-5
6 5
o 0
0 1
1 0
1 1
Number of Data Bits Per Character
Bits 4-3
4 3
o 0
0 1
1 0
Parity Mode Selection
5
6
7
8
Odd Parity
Even Parity
Mark in Parity bit
Space in Parity bit
Bit 2
1
0
Parity Enable
Parity as specified by bits 4-3
No Parity
Bit 1
1
0
DTR Control
SetDTR high
SetDTR low
Bit 0
1
0
RTS Control
Set RTS high
Set RTS low
R65C52
Dual Asynchronous Communications Interface Adapter (DACIA)
OPERATION
COMPARE DATA REGISTERS (CDR1, CDR2)
The Compare Data Registers are write-only registers which can
be accessed when CR bit 6 = O. By writing a value into the CDR,
the DACIA is put in the compare mode. In this mode, setting of the
RDRF bit is inhibited until a character is received which matches
the value in the CDR. The next character is then received and the
RDRF bit is sel. The receiver will now operate normally until the
CDR is again loaded.
(Control Register bit 6
7
6
5
4
TERMINATION OF UNUSED INPUTS
Noise on floating inputs can affect chip operation. All unused
inputs must be terminated. If the baud rate generator is bypassed,
XTALI must be connected to ground (XTALO is an output and
must be left open). If the external clock mode is not used, RxC
and TxC may be tied either to + 5V or to ground. If the handshake
inputs are not needed, the CTS inputs should be tied low to
enable the transmitters. The DCD and DSR inputs may either be
tied high or low.
= 0)
2
3
o
COMPARE DATA
Address = 2,6
Reset Value = - - - - - - - -
AUXILIARY CONTROL REGISTERS (ACR1, ACR2)
RESET INITIALIZATION
The Auxiliary Control Registers are write-only registers. Bits 7-2
are unused. Bit 1 causes the transmitter to transmit a BREAK. Bit 0
determines whether parity error or the parity bit is displayed in ISR
bit 2.
(Control Register bit 6
7
6
5
4
3
During power on initialization, all readable registers should be read
to assure that the status registers are initialized. Specifically, the
RDRF bit of the Interrupt Status Registers is not initialized by reset.
The Receiver Data Registers must be read to clear this bit.
= 1)
2
NOT USED
Address = 2,6
Bits 7-2
BAUD RATE CLOCK OPTIONS
Reset Value = - - - - - - 00
Not Used
Bit 1
The receiver and transmitter clocks may be supplied either by the
internal Baud Rate Generator or by user supplied external clocks.
Both channels may use the same clock source or one may use
the Baud Rate Generator and the other channel external clocks.
If both channels use the Baud Rate Generator, each channel may
have a different bit rate. The options are shown in Figure 5.
Transmit Break (TRNS BRK)
Transmit continuous Break
Normal transmission
1
o
Bit 0
1
Parity Error/State (PAR ERR/ST)
Send value of parity bit to ISR bit 2 (Address
Recognition mode)
Send Parity Error status to ISR bit 2
o
An internal clock oscillator supplies the time base for the Baud
Rate Generator. The oscillator can be driven by a crystal or an
external clock.
RECEIVE DATA REGISTERS (RDR1, RDR2)
The Receive Data Registers are read-only registers which are
loaded with the received data character of each frame. Start bits,
stop bits and parity bits are stripped off of incoming frames before
the data is transferred from the Receive Shift Register to the
Receive Data Register. For characters of less than eight bits, the
unused bits are the high order bits which are set to O.
MSB
7
If the on-chip oscillator is driven by a crystal, a parallel resonant
crystal is connected between the XTALI and XTALO pins. The
equivalent oscillator circuit is shown in Figure 6.
A parallel resonant crystal is specified by its load capacitance and
series resonant resistance. For proper oscillator operation, the load
capacitance (C l ), series resistance (Rs) and the crystal resonant
frequency (F) must meet the following two relations:
LSB
6
5
4
3
2
o
RECEIVE DATA
Address = 3,7
Reset Value = 00000000
(C
+ 2) = 2C l
or
C = 2C l
-
2
TRANSMIT DATA REGISTERS (TDR1, TDR2)
Rs :5 Rsmax = 2 X 106
The Transmit Data Registers are write-only registers which are
loaded from the CPU with data to be transmitted. For data characters of less than eight bits, the unused bits are the high order bits
which are "don't care".
MSB
7
(FCd"
where: F is in MHz; C and Cl are in pF; R is in ohms.
LSB
6
5
4
3
2
To select a parallel resonant crystal for the oscillator, first select
the load capacitance from a crystal manufacturer's catalog. Next,
calculate Rsmax based on F and C l . The selected crystal must
have a Rs less than the Rsmax.
o
TRANSMIT DATA
Address = 3,7
Reset Val ue = - - - - - - - -
1-125
R65C52
Dual Asynchronous Communications Interface Adapter (DACIA)
CLOCK INPUT
I--_----IXTALI
o
• Baud rate determined by XTALlfrequency and 1 of 15 divisors selected In
CRI and CR2. CRI and CR2 must not be
set to all ones.
Lf1JlfUl
OPEN CIRCUIT
XTALO
I - - - - - - - - l XTALO
• Channell baud rate may be different
from channel 2 baud rate.
• Receiver baud rate must be the same as
transmitter baud rate.
A. Both Channels Use Internal Baud Rate Generator
16 x Tx BAUD RATE
• Transmitter baud rate 1/16 TxC Input
frequency.
~
• Receiver baud rate 1/16 RxC input
frequency.
16 x Rx BAUD RATE
lJ1Jlf1f
INTERNAL CLOCK
OSCILLATOR DISABLED
• Channell baud rate Is the same as
channel 2 baud rate.
• Receiver baud rate may be different from
transmitter baud rate.
XTALO
• Bits 3-0 of CRI and CR2 must be set to
all ones.
B. Both Channels Use External Clocks
CLOCK INPUT
t
XTALI
1IlJlJ"
• Channel 1 baud rate may be different
from channel 2 baud rate.
OPEN CIRCUIT
• Transmitter baud rate may be different
from receiver baud rate on channel
using external clock.
D
XTALO
16 x Tx BAUD RATE
lJUL
16 x Tx BAUD RATE
lJlJlI
lJlJL
TxC
16 x Rx BAUD RATE
1JlJL
16 x Rx BAUD RATE
RxC
C. One Channel Uses Internal Baud Rate Generator;
One Channel Uses External Clocks
Figure 5.
Baud Rate Clock Options
1-126
Dual Asynchronous Communications Interface Adapter (DACIA)
R65C52
The series resistance of the crystal must be less than
2 X 106
R,m., =
C±5%
fro
(3.6864 x 22)2
XTU
2 pF
I
MHz
-=-
C± 50/.
= 304 ohms
XTLO
If the on·chip oscillator is driven by an external clock, the clock
is input at XTALI and XTALO is left open.
R65C52
H
2pF
An internal counter/divider circuit divides the frequency input at
XTALI by the divisor selected in bits 3 through a of the Control
Registers. Table 5 lists the divisors that may be selected and shows
the bit rates generated with a 3.6864 MHz crystal or clock input.
Other bit rates may be generated by changing the ciock or crystal frequency. However, the input frequency must not exceed
4 MHz.
-=-
Figure 6.
For external clock operation, a transmitter times 16 clock must be
supplied at TxC and a receiver times 16 clock must be input at RxC.
Since there are separate receiver and transmitter ciock inputs, the
receiver data rate may be different from the transmitter data rate.
For example, if C L = 22 pF for a 3.6864 MHz parallel resonant
crystal, then
C = (2 x 22) - 2 = 42 pF (use standard value of 43 pF)
Table 5.
Controt
Register
Bits
Baud Rate Generator Divisor Setection
3
2
1
0
Divisor Selected
For The
Internal Counter
Baud Rate Generated
With 3.6864 MHz
Crystal or Clock
Baud Rate Generated"
With a Crystal or Clock
of Frequency (f)
0
0
0
0
73,728
(3.6864 x 10')/73,728
0
0
1
33,538
(3.6864 x 10')/33,538
1/33,538
0
0
1
0
27,408
0
0
1
1
24,576
0
1
0
0
12,288
0
1
0
1
6,144
0
1
1
0
3,072
= 50
= 109.92
(3.6864 x 10')/27,408 = 134.58
(3.6864 x 10')/24,576 = 150
(3.6864 x 10')/12,288 = 300
(3.6864 x 10')/6,144 = 600
(3.6864 x 10')/3,072 = 1,200
(3.6864 x 10')/2,048 = 1,800
(3.6864 x 10')/1,536 = 2,400
(3.6864 x 10')/1,024 = 3,600
(3.6864 x 10')/768 = 4,800
(3.6864 x 10')/512 = 7,200
(3.6864 x 10')/384 = 9,600
(3.6864 x 10')/192 = 19,200
(3.6864 x 10')/96 = 38,400
Transmitter Baud Rate = TxC/16
1/73,728
0
0
1
1
1
2,048
1
0
0
0
1,536
1
0
0
1
1,024
1
0
1
0
768
1
0
1
1
512
1
1
0
0
384
1
1
0
1
192
1
1
1
0
96
1
1
1
1
16
"Baud Rate =
Frequency
Divisor
1-127
1/27,408
1/24,576
1/12,288
1/6,144
1/3,072
1/2,048
111 ,536
1/1,024
1/768
1/512
1/384
1/192
1/96
Receiver Baud Rate
= RxC/16
D
Dual Asynchronous Communications Interface Adapter (DACIA)
R65C52
CONTINUOUS DATA TRANSMIT
CAUTION:
When the Baud Rate Generator is the clock source, writing
to the Format or Control Register of a channel with an active
transmitter can result in loss of data. Do not write to the Control or Format Register when the transmitter is shifting out
data. This precaution does not apply to channels using the
external clock option, i.e., TxC.
In the normal operating mode, the TORE bit in the ISR signals the
MPU thatthe DACIA is ready to accept the next data word. An IRQ
occurs if the corresponding TORE IRQ enable bit is set in the IER.
The TORE bit is set at the beginning of the start bit. When the MPU
writes a word to the TOR the TORE bit is cleared. In order to maintain continuous transmission the TOR must be loaded before the
stop bit(s) are ended. Figure 7 shows the relationship between IRQ
and TxO for the Continuous Data Transmit mode.
CHAR #n + 1
CHAR #n
I
CHAR #n + 2
I
CHAR #n + 3
'-/
TX~ t r:Fl~]~;:[~JtW~;:I~I ~ GEJ t I t rs:JB0~ ~ GEJ
: START
IRilJu
STOP: START
LuJ'
/lJJJ
Lw
STOP
(TUR) is set. This condition persists until the TOR is loaded with
a new word. Figure 8 shows the relation between IRQ and TxO for
the Transmit Underrun Condition.
CHAR #n + 1
UNDERRUN BIT
SET
Figure 8.
CHAR #n + 2
II t rs:EI I~JiJ t II t rn ~ ]~I
ILJlJ
LWrTT""-/
'\./
START
1'---------/-..,.--------/----::1
PROCESSOR
INTERRUPT
FOR DATA
EMPTY
l
Continuous Data Transmit
CONTINUOUS '"MARK'"
r-"""T'"---,r-".,....----
TtlI t @BJ=]~JiJ t I
I
STOP START
IRQ
I
STOP:
INTERVAL OTHERWISE,
CONTINUOUS "MARK"
IS TRANSMITTED
If the MPU is unable to load the TOR before the last stop bit is sent,
the TxO line goes to the MARK condition and the underrun flag
CHAR #n
~ ~ =GEJ t L
STOP: START
TRANSMIT UNDERRUN CONDITION
/
I
t t
STOP: START
READS
ISR, CAUSES
IRQ TO CLEAR
Figure 7.
TxD
'./
_"""" / 1.,,"" ~ ~E~>E~'~"
INTERRUPT
(TRANSMIT DATA
REGISTER EMPTY)
"
I
I
,,/
/
PROCESSOR READS
ISR, CLEARS IRQ
\WHEN PROCESSOR FINALLY LOADS
NEW DATA, TRANSMISSION STARTS
IMMEDIATELY AND INTERRUPT
OCCURS, INDICATING TRANSMIT
DATA REGISTER EMPTY
Transmit Underrun Condition Relationship
1-128
STOP START
I
R65C52
Dual Asynchronous Communications Interface Adapter (DACIA)
one character time to assure that a proper BREAK is transmitted.
If the Transmit Break bit is cleared before one character time of
BREAK has been transmitted, the BREAK will be terminated after
one character time has elapsed. If the Transmit Break bit is cleared
after one character time of BREAK has been transmitted, the
BREAK will be terminated immediately. Figure 9 shows the relationship of TxD, IRQ and ACR bit 1 for various BREAK options.
TRANSMIT BREAK CHARACTER
A BREAK may be transmitted by setting bit 1 of the ACR (Transmit Break bit) to a 1. The BREAK is transmitted after the character in the Transmit Shift Register is sent. If there is a character in
the Transmit Data Register, it will be transmitted after the BREAK
is terminated. The Transmit Break bit must remain set for at least
STOP START
TxO
STOP START
~]§B t
ACR
BIT 1
STOP START
STOP START
ffi]§I£1 ; 1 t CS¥f ]§I£J ; 1 t [B?Jii;[~
1'
f"'T,.T-n T I"'T1
I!
I!
I, I!
I I
I I _________________________________________________________
UlUl~'~'
TORE~'
I
I
IRO
J
Ll]'
I
LlJ'
I
I
J
,'
LJj'
I
J
J
a. Transmit Break bit cleared before BREAK begins-BREAK is ignored
STOP START
STOP
STOP START
STOP START
=rtlJl~I~2[ @d£]tl-I.....I-...l-....LBR_EA...I-K..........~!1l t fBOF1"[ ~ tit @~i1"[~~ =
ACR
, , 1- ,--r-"
;-r-I : :
BIT 1
TxO
,
!
__
I
I
L._L_
.L_.J
I
'
I
,
I
,
TORE~'
IRO
I
J
LIJj
LlJ'
I
I
J
b. Transmit Break bit cleared during first character time of BREAK-BREAK terminates after one character time
STOP START
TxO
STOP
STOP START
rtl t@OPi1J= l§!0
~~~ tI-l_____B_RE_A_I<_ _ _ _ _.....
ACR
rTT-lr--------------------------------------~
BIT 1 _______....:.......: .....
: .....
' -___________________
TORE
IRO
W'
-uJ'
I
I
I
I
J
J
c. Transmit Break bit cleared after first character time of BREAK-BREAK terminates immediately
Figure g.
Transmit BREAK
EFFECTS OF CTS ON TRANSMITTER
Any transition on ers sets bit 5 (erST) of the ISR. A high on ers
forces bit 6 ITQ£IE) of the ISR to a O. Bit 7 of the ISR also goes
to a 1 when ers is high, if Echo Mode is disabled. Thus, when
the ISR is $80, it means that ers is high and no interrupt source
requires service. A processor interrupt will not be generated under
these circumstances, but an ISR polling routine should accommodate this.
The ers control line controls the transmission of data or the handshaking of data to a "busy" device (such as a printer). When the
ers line is low, the transmitter operates normally. A high condition inhibits the TORE bit in the ISR from becoming set. Transmission of the word currently in the shift register is completed but any
word in the TOR is held until ers goes low.
CHAR #n
cHARtn + 1
T.D ---'----~" /~------L---~"
EI]~EJ t 1t [BJBJ - 'I
CONTINUOUS MARK
NEXT CHARACTER IS SENT IMMEDIATELY
UPON CTS GOING LOW IF PROCESSOR
HAS ALREADY LOADED NEW DATA,
OTHERWISE IT WAITS FOR NEW DATA.
-'-'-".:.-..::..:.------,;-~_t-t'J
'I
Bp'l-t""'I'-'-N'-"Ex-"T
N
STOP START
STOP
CHARACTER
IS NOT SENT
TORE IS NOT SET
t
oc;-
START
MPU
CLEARS
IRQ AGAIN
WHEN PROCESSOR
FINALLY LOADS
NEW DATA,
TRANSMISSION STARTS
un CTSJ'---------------------'~
~MEDIATELY
i
'\
IRQ
CLEAR· TO-SEND
~~~ARS
1
IRQ
Figure 10_
Effects of ers on Transmitter
1-129
1
AND
CTS
INTERRUPT OCCURS,
INDICATING TRANSMIT
IRQ
DATA REGISTER EMPTY
o
Dual Asynchronous Communications Interface Adapter (DACIA)
R65C52
ECHO MODE TIMING
underflow flag would be set and continuous Mark transmitted. If
Echo is initiated, the underflow flag will not be set at end of data
and continuous Mark will not be transmitted. Figure 11 shows the
relationship of RxD and TxD for Echo Mode.
In the Echo Mode, the TxD line re-transmits the data received on
the RxD line, delayed by 1/2 of a bit time. An inlernal underrun
mode must occur before Echo Mode will start transmitting. In normal transmit mode if TORE occurs (indicating end of data) an
STOP
RxD
START
STOP
END OF
DATA
STOP
J1l +~~]~JiJ ~ 1t ~"B~r]~iJ + 1,--/__
\1 \ \ \
TxD
START
\ \
W t rs:FJ= =~ t
STOP START
\ \ \ ________ ~O:;~~gHU;~~:
\ \ \
1
t rBOTB~I 1~;JiJ t [= ===
STOP~
STOP START
IF ECHO MODE,
NO UNDERFLOW,
THEREFORE NO
CONTINUOUS MARK
Figure 11.
Echo Mode Timing
CONTINUOUS DATA RECEIVE
CAUTION:
The normal receive mode sets the RDRF bit in the ISR when the
DACIA channel has received a full data word. This occurs at about
the 9116 point through the stop bit. The processor must read the
RDR before the next stop bit, or an overrun error occurs. Figure 12
shows the relationship between IRQ and RxD for the continuous
Data Receive mode.
CHAR #n
,,/
I
/
When the Baud Rate Generator is the clock source, writing
to the Control or Format Registers of a channel with an active
receiver can result in loss of data. Do not write to the Control or Format Registers when the receiver is shifting in data.
This precaution is not necessary on channels using the
external clock option, i.e., RxC.
CHAR #n + 1
CHAR #n + 2
!
CHAR #n + 3
I
'-/
'-/
!
"-
RX~ t [qBJ~]~JiJ/I t ~~=~/I t ~~I~E]/1 t [BOIB1J~]ilil L
START
STOP: START
STOP:
I
IR~rn-----iUJ'
IRQ PROCESSOR
INTERRUPT OCCURS
ABOUT 9116 INTO
LAST STOP BIT
PARITY OVERRUN,
AND FRAMING ERROR
UPDATED ALSO
START
I
ILJI]
) \ ~
PROCESSOR READS
ISR, CAUSES
IRQ TO CLEAR
Figure 12.
START
I
Lill
PROCESSOR MUST READ
RECEIVER DATA IN THIS
TIME INTERVAL, OTHERWISE
OVERRUN OCCURS
Continuous Data Receive
1-130
STOP:
STOP:
L
I
R65C52
Dual Asynchronous Communications Interface Adapter (DACIA)
EFFECTS OF OVERRUN ON RECEIVER
contains the last word not read by the MPU and all following data
is lost. The receiver will return to normal operation when the RDR
is read. Figure 13 shows the relationship of IRQ and RxD when
overrun occurs.
" the processor does not read the RDR before the stop bit of the
next word, an overrun error occurs, the overrun bit is set in the ISR,
and the new data word is not transferred to the RDA. The RDR
CHAR Un + 1
CHAR Un
~/
I
,,/
JIl t ~~]~;:riJ!
RxD
STOPI START
IRO
,,/
CHAR Un + 3
,,/~_ _ _.LI_ __
I
t ~~]~EJ! I t [BOIBJ~~hliJ! I t ro-EI~~
I
STOP I START
LJ]]
CHAR Un + 2
I
STopl
I
ISTOP I
START
Il'-_____- - - t
I
PROCESSOR /
INTERRUPT
FOR RECEIVER
DATA REGISTER
FULL
MPU DOES
NOT READ
RDR. OVERRUN
BIT SET
Figure 13.
START
MPU READS
ISR
CLEARS IRO
'CHAR #n + 2
IRQ.
CHAR#n + 1
IS LOST
Effects of Overrun on Receiver
RECEIVE BREAK CHARACTER
next character is to be received normally. Figure 14 shows the relationship of IRQ and RxD for a Receive Break Character.
In the event that a Break character is received by the receiver, the
Break bit is set. The receiver does not set the RDRF bit and
remains in this state until a stop bit is received. At this time the
------~"
RxD
E[]~~liJ~11 t
------;U
CONTINUOUS "BREAK"
I BOI B'I
STOP START
f
~N~~~~~~~R
FOR
RECEIVER
DATA REGISTER
FULL
STOP /
t [~~I]~diJ~ t I
_I BN I P l;t' I fl-'-\I----1----!m
STOP
START
I
I
i rrI
Lll
I"
t ~
Receive Break Character
1-131
I
STOP
Bol B,I
I START
rr---
L_.-l.I
NO- ' " NO INTERRUPT
I
MORE
SINCE RECEIVER.
PROCESSOR INTERRUPTS
DISABLED UNTIL
INTERRUPT
FIRST START BIT
WITH BREAK AND FRAMING ERROR BIT SET.
EVEN PARITY CHECK WILL ALSO GIVE A PARITY
ERROR BECAUSE ALL ZEROS (CONTINUOUS
BREAK) REPRESENT EVEN PARITY.
Figure 14.
,,/~----
t
NORMAL
RECEIVER
INTERRUPT
D
Dual Asynchronous Communications Interface Adapter (DACIA)
R65C552
FRAMING ERROR
reflects the last data word received. Figure 15 shows the relationship of IRQ and RxD when a framing error occurs.
Framing error is caused by the absence of stop bit(s) on received
data. The framing error bit is set when the RDRF bit is set. Subsequent data words are tested separately, so the status bit always
RxD
(EXPECTED)
RxD
(ACTUAL)
I
NOTES: 1. FRAMING ERROR DOES NOT
INHIBIT RECEIVER OPERATION.
PROCESSOR
INTERRUPT,
FRAMING
ERROR
BIT SET
2. IF NEXT DATA WORD IS OK,
FRAMING ERROR IS CLEARED.
Figure 15.
Framing Error
PARITY ERROR DETECT/ADDRESS
FRAME RECOGNITION
this type of operation, bit 0 of the ACR is set to a 1 and bits 2, 3
and 4 of the FR select a parity checking mode. Then, ISR bit 2 will
be set to a 1 by incoming address frames and it will be a 0 on data
frames.
The Parity Status bit (ISR bit 2) may be programmed to indicate
parity errors (ACR bit 0 = 0) or 10 display the parity bit received
(ACR bit 0 = 1).
COMPARE MODE
In applications where parity checking is used, one of the parity
checking modes is enabled by setting bits 2, 3 and 4 of the Format Register to the desired option and bit 0 of the Auxiliary Control Register is reset to O. Then, when the RDRF bit (bit 0) is set
in the ISR, the PAR bit (bit 2) will be set when a parity error is
detected.
The Compare Mode is automatically enabled, i.e., the channel is
put to sleep, whenever data is written to the Compare Data
Register. NOTE: Bit 6 of the Control Register must be set to 0 to
enable access to the Compare Data Register. When the channel
is in the compare mode, the RDRF bit (bit 0 of the ISR) is forced
to a O. Upon receipt of a matching character, normal receiver operation resumes and the RDRF bit (bit 0 of the ISR) will be set upon
receipt of the next character.
In multi-drop applications, the parity bit is used as an address/data
flag. It is set to 1 for address frames and is 0 on data frames. For
1-132
Dual Asynchronous Communications Interface Adapter (DACIA)
R65C52
SPECIFICATIONS
DACIA READ/WRITE WAVEFORMS
D
00-07
i----------REAO CYCLE
DACIA READ/WRITE CYCLE TIMING
(Vee
= 5 Vdc ± 5%, Vss = 0 Vdc, TA = T L to T H, unless otherwise noted)
2 MHz
1 MHz
Number
Characteristic
Symbol
Min.
Max.
Min.
3 MHz
Max.
Max.
Unit
-
ns
210
-
ns
-
210
ns
10
50
ns
-
20
-
ns
-
30
-
ns
-
0
-
0
45
-
45
640
-
320
-
-
340
-
245
1
R/W, RSO-RS2 Valid to CS Low (Setup)
TRSU
0
2
CS Low to RIW, RSO-RS2 Invalid (Hold)
TRH
45
3
CS Pulse Width
Tcp
6
CS Low to Data Valid (Read)
Teov
8
CS High to Data Invalid (Read)
TeoR
10
50
10
50
9
Data Valid to CS High (Write, Setup)
Tosu
20
20
10
CS High to Data Invalid (Write Hold)
Teow
30
-
30
1·133
Min.
ns
R65C52
Dual Asynchronous Communications Interface Adapter (DACIA)
DACIA TRANSMIT/RECEIVER WAVEFORMS
TXC,RXC
TxD
CS
RTS, DTS
-----f--'t
---~®}-~
------------~f-
TRANSMIT/RECEIVE AND INTERRUPT ACKNOWLEDGE TIMING
(Vce
= 5 Vdc
Number
± 5%, Vss
= 0 Vdc, TA = Tl to TH' unless otherwise noted)
Characteristic
Symbol
Min.
Max.
Unit
TRANSMIT/RECEIVE TIMING
12
Transmit/Receive Clock Rate
tev
250
13
Transmit/Receive Clock High
tCH
100
-
14
Transmit/Receive Clock Low
tel
100
-
ns
15
TxC, RxC 10 TxD Propagalion Delay
100
-
285
ns
16
TxC, RxC to
rna Propagation Delay
tOI
-
250
ns
17
CTS, DCD, DSR Valid to IRQ Low
terl
-
150
ns
18
IRQ Propagation Delay (Clear)
tlRQ
-
150
ns
19
RTS, DTR Propagation Delay
tOlV
-
150
ns
1-134
ns
ns
Dual Asynchronous Communications Interface Adapter (DACIA)
R65C52
ABSOLUTE MAXIMUM RATINGS*
Parameter
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Commercial
Industrial
Symbol
Value
Unit
Vee
-0.3 to + 7.0
Vdc
V,N
-0.3 to Vce +0.3
Vdc
VOUT
-0.3 to Vce +0.3
Vdc
·NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in other sections of this document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
DC
TA
o to +70
-40to +85
Storage Temperature
TSTG
-55to +150
DC
OPERATING CONDITIONS
Symbol
Value
Supply Voltage
Parameter
Vee
5V±5%
Temperature Range
Commercial
Industrial
TA
Oto 70 DC
_40DC to +85 DC
DC CHARACTERISTICS
(Vee
= 5.0 V
± 5%,
Vss
= 0, TA = T L to T H, unless otherwise noted)
Parameter
Symbol
Input High Voltage
Except XTALI and XTALO
XTALI and XTALO
V,H
Input Low Voltage
Except XTALI and XTALO
XTALI and XTALO
V,L
Input Leakage Current
Riw, RES, RSO, RS1, RS2, RxD, ers, DCD, DSR, RxC,
TxC,CS
Min
Typ
Max
Unit
Test Conditions
V
+2.0
+2.4
-
-
Vee + 0.3
Vee + 0.3
-0.3
-0.3
-
+0.8
+0.4
liN
-
10
50
pA
V ,N = OV to 5.0V
Vee = S.2SV
Input Leakage Current for Three-State Off
DO-D7
ITSI
-
±2
10
pA
V,N = 0.4V to 2.4V
Vee = S.2SV
Output High Voltage
00-D7, TxD, CLK OUT, RTS, DTR
VOH
-
-
V
Vee = 4.7SV
ILOAO = -100 pA
Output Low Voltage
00-D7, TxO, CLK OUT, RTS, DTR
VOL
-
-
+0.4
V
Vee = 4.7SV
ILOAO = 1.6 mA
10FF
-
±2
±10
pA
Vee = 5.25V
VOUT = 0 to 2.4V
Power Dissipation
Po
-
-
10
mW/MHz
Input CapaCitance
Except XTALI and XTALO
XTALI and XTALO
C 'N
-
-
5
10
pF
pF
10
pF
Output Leakage Current (Off State)
IRQ
Output Capacitance
V
+2.4
-
-
COUT
Notes:
1. All units are direct current (dc) except for capacitance.
2. Negative sign indicates outward current flow, positive indicates inward flow.
3. Typical values are shown for Vec = 5.0V and TA = 25 DC.
1-135
Vee = 5.0V
V ,N = OV
f = 2 MHz
TA = 25 DC
Dual Asynchronous Communications Interface Adapter (DACIA)
R65C52
PACKAGE DIMENSIONS
40·PIN CERAMIC DIP
[ D ::J]]
I·
DIM
A
a
·1
A
w
~n
H~~LD
G-II-
M-j
K_ _ J
50.29
15.11
INCHES
MIN
MAX
51.31
1.980
2.020
15.88
0.595
0.625
C
2.54
4.19
0.100
0.165
0
0.38
0.53
0.015
0.021
F
0.76
1.27
0.030
0.050
G
t
F
MILLIMETERS
MIN
MAX
2.54 esc
0.100 sse
H
0.76
1.78
0.030
J
0.20
0.33
0.008
0.013
0.070
K
2.54
4.19
0.100
0.165
l
14.60
15.37
0.575
0.605
M
0'
10'
N
0.51
1.52
0'
10'
0.020
0.060
40·PIN PLASTIC DIP
MILLIMETERS
I::::::::::::::::::::p
•
A
•
Cllj
MIN
MAX
MIN
A
51.82
52.32
2.040
2.060
a
13.46
13.97
0.530
0.550
MAX
C
3,56
5.09
0,140
0.200
0
0.38
0.53
0.015
0.021
F
1.02
1.52
0.040
G
~p
INCHES
DIM
2.54 sse
0.100
0.060
ase
H
1.65T 2.16
0.085
0.085
J
0.20
I
0.30
0.008
0.012
K
3.30
4.32
0.130
0.170
l
M
15.24 sse
7°
10"
7'
10'
N
0.51"1" 1.02
0.020
0.040
T
0.600 ase
44·PIN PLASTIC LEADED CHIP CARRIER (PLCC)
1~t:!D2-j 'I
~~g~
Iff·
l!l "~,
CORNER
0
~
INDICATOR
OS
~
.U!
MILLIMETERS
~/d'~
I~
CHAM.J )( 45·
~~il
~03.
I
80~
~
~.~
iAAlmn
..j 1-.
..jf.cb
DIM
MIN
A
,
SIDE VIEW
~~.
,
A2A
R
SECTION A·A
TYP FOR BOTH AXIS (EXCEPT FOR BEVELED EDGE)
CHAM.
EJECTOR PIN MARKS
11 PINS
h )( 45· PER SIDE
4 PlCS BOTTOM OF
3 PlCS EQUAllY
PACKAGE ONLY
(TYPICAL)
SPACES
BOTTOIIII VIEW
1-136
INCHES
MAX
MIN
MAX
414
4.39
0.163
0.173
A1
1.37
1,47
0.054
0.058
A2
2.31
2.46
0.091
0.097
b
~
TOP VIEW
~
l§
SEATING PLANE
:,.(~
H-
L-17
V
0.457 TYP
O.Q18TYP
0
17.45
17.60
0.687
01
16.46 T 16.58
0.648
0.652
02
12.62T 12.78
0.497
0.503
D.
15.75 REF
0.620 REF
e
127 BSC
0.050 BSC
h
1.15TVP
0.045 TYP
J
0.25 TYP
0.010 TYP
.
0.693
45° TYP
45° TYP
R
0.89 TYP
0.035 TYP
R1
0.25 TYP
0.010 TYP
Section 2
NMOS 8-Bit Microprocessors & Peripherals
Page
Product Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-2
R650X and R651X Microprocessors (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3
R6520 Peripheral Interface Adapter (PIA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2-18
R6522 Versatile Interface Adapter (VIA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2-30
R6532 RAM-I/O-Timer (RIOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2-52
R6545/R6545E CRT Controller (CRTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2-62
R6549 Color Video Display Generator (CVDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2-81
R6551 Asynchronous Communications Interface Adapter (ACIA) .................. 2-112
2-1
NMOS 8-bit Microprocessors and Peripherals
Largest Selling 8-Bit Family
The NMOS R6500 microprocessor family has a wide range
of CPUs and peripheral controllers plus versatile memory-IIO
timer combinations. It is software compatible with the CMOS
microprocessor and peripheral family, as well as, with the
family of single-chip microcomputers.
A parallel processing, pipeline architecture provides faster
instruction execution and data throughput. Thirteen address
modes provide the most efficient ways of addressing memory.
R6500 peripherals are system oriented and are designed to implement systems with a minimum device count. Fast instruction
execution (1 P.s and 2 p.s) is available in 2 and 1 MHz versions,
respectively.
The entire 8-bit R6500 family is upward compatible with the
16-bit 68000 bus, software compatible with the Rockwell 8-bit
microcomputers, and are the building blocks for a wide range
of system applications.
INTELLIGENT
PERIPHERAL
CONTROLLER DEVICES
MEMORY I/O TIMER
COMBO DEVICE
NMOS R65XX Microprocessor Family
2-2
R650X • R651X
'1'
R650X and R651X
Microprocessors (CPU)
Rockwell
FEATURES
DESCRIPTION
The S-bit R6500 microprocessor devices are produced with
N-channel, silicon gate technology. Performance speeds are
enhanced by advanced system architecture. This innovative
architecture results in smaller chips-the semiconductor
threshold is cost-effectivity. System cost-effectivity is further
enhanced by providing a family of 10 software-compatible
microprocessor (CPU) devices, described in this document.
Rockwell also provides single chip microcomputers, memory and
peripheral devices-as well as low-cost design aids and
documentation.
• N-channel, silicon gate, depletion load technology
•
•
•
•
•
•
•
•
•
•
•
•
Ten CPU devices are available. All are software-compatible.
They provide options of addressable memory, interrupt input,
on-chip clock oscillators and drivers. All are bus-compatible with
earlier generation microprocessors like the M6S00 devices.
The R650X and R651X family includes six microprocessors with
on-board clock oscillators and drivers and four microprocessors
driven by external clocks. The on-Chip clock versions are aimed
at high performance, low cost applications where single phase
inputs, crystal or RC inputs provide the time base. The external
clock versions are geared for multiprocessor system applications where maximum timing control is mandatory. All R6500
microprocessors are also available in a variety of packaging
(ceramic and plastic), operating frequency (1 MHz, 2 MHz and
3 MHz) and temperature (commercial and industrial) versions.
S-bit parallel processing
56 instructions
Decimal and binary arithmetic
Thirteen addressing modes
True indexing capability
Programmable stack pointer
Variable length stack
Interrupt request
Non-maskable interrupt
Use with any type of speed memory
S-bit bidirectional data bus
Addressable memory range of up to 64K bytes
•
o
•
•
•
•
".Ready" input
Direct Memory Access capability
Bus compatible with M6S00
1 MHz, 2 MHz, and 3 MHz versions
Choice of external or on-chip clocks
On-chip clock options
-External single clock input
-Crystal time base input
• Commercial and industrial temperature versions
• Pipeline architecture
• Single +5V supply
ORDERING INFORMATION
Part Number: R65XX __ _
R6S00 CPU FAMILY MEMBERS
Temperature Range (TL to TH):
No letter = O'C to + 70'C
E = -40'C to +85'C
L
Microprocessors with Internal Two Phase Clock Generator
Package:
C = Ceramic DIP
P = Plastic DIP
-
Frequency Range:
No letter
1 MHz
A = 2 MHz
B
=
Model
No. Pins
Addressable Memory
R6502
R6503
R6504
R6505
R6506
R6507
40
28
28
28
28
28
64K Bytes
4K Bytes
8K Bytes
4K Bytes
4K Bytes
8K Bytes
3 MHz
Microproces:;ors w~h External Two Phase Clock Input
' - - - Model Designator:
XX = 02, 03, 04, ... 15
Document No. 29000039
Model
No. Pins
Addressable Memory
R6512
R6513
R6514
R6515
40
28
28
28
64K Bytes
4K Bytes8K Byies
4K Bytes
Data Sheet
2-3
Order No. 039
Rev. 8, June 1987
II
R6500 Microprocessors (CPU)
R650X, R651X
are stored in the stack. The microprocessor will then set the
interrupt mask flag high so that no further interrupts can occur.
At the end of this cycle, the program counter low will be loaded
from address FFFE, and program counter high from location
FFFF, therefore transferring program control to the memory
vector located at these addresses. The RDY signal must be in
the high state for any interrupt to be recognized. A 3KO external
resistor should be used for proper wire-OR operation.
INTERFACE SIGNAL DESCRIPTIONS
CLOCKS ("'1, ~2)
The R651 X requires a two phase non-overlapping clock that
runs at the Vcc voltage level. The R650X clocks are supplied
with an internal clock generator. The frequency of these clocks
is externally controlled.
NON-MASKA~LE
ADDRESS BUS (AO-A15)
INTERRUPT (NMI)
A negative going edge on the NNfI input requests that a nonmaskable interrupt sequence be generated within the microprocessor.
The address line outputs access data in memory device locations or cells, access data in I/O device registers and/or effect
logical operations in I/O or controller devices depending on
system design. The addressing range is determined by the
number of address lines available on the particular CPU device.
The R6502 and R6512 can address 64K bytes w~h a 16-bit
address bus (AO-A15); the R6504, R6507, and the R6514 can
address 8K bytes with a 13-bit address bus (AO-A 12); and the
R6503, R6505, R6506, R6513, and R6515 can address 4K
bytes with a 12-bit address bus (AO-A 11). These outputs are
TTL-compatible and are capable of driving one standard TTL
load and 130 pF.
NMI is an unconditional interrupt. Following completion of the
current instruction, the sequence of operations defined for IRQ
will be performed, regardless of the state interrupt mask flag.
The vector address loaded into the program counter, low and
high, are locations FFFA and FFFB respectively, thereby transferring program control to the memory vector located at these
addresses. The instructions loaded at these locations cause the
microprocessor to branch to a non-maskable interrupt routine
in memory.
NMI also requires an external 3KO register to Vcc for proper
wire-OR operations.
DATA BUS (Do-D7)
The data lines (DO-D7) form an 8-bit bidirectional data bus
which transfers data between the CPU and memory or peripheral devices. The outputs are tri-state buffers capable of driving
one standard TTL load and 130 pF.
Inputs IRQ and NNfI are hardware interrupts lines that are sampled during l!J2 (phase 2) and will begin the appropriate interrupt
routine on the l!J1 (phase 1) following the completion of the current instruction.
DATA BUS ENABLE (DBE, R6512 ONLy)
SET OVERFLOW FLAG (SO)
The TTL-compatible DBE input allows external control of the tristate data output buffers and will enable the microprocessor bus
driver when in the high state. In normal operation DBE is driven
by the phase two (l!J2) clock, thus allowing data output from
microprocessor only during ~2. During the read cycle, the data
bus drivers are internally disabled, becoming essentially an
open circuit. To disable data bus drivers externally, DBE should
be held low.
A negative going edge on the SO input sets the overflow bit in
the Processor Status Register. This signal is sampled on the
trailing edge of !P1 and must be externally synchronized.
SYNC
The SYNC output line identifies those cycles in which the microprocessor is doing an OP CODE fetch. The SYNC line goes high
during ~1 of an OP CODE fetch and stays high for the remainder
of that cycle. If the RDY line is pulled low during the l!J1 clock
pulse in which SYNC went high, the processor will stop in its
current state and will remain in the state until the RDY line goes
high. In this manner, the SYNC signal can be used to control
RDY to cause single instruction execution.
READY (RDY)
The Ready input signal allows the user to halt or single cycle
the microprocessor on all cycles except write cycles. A negative
transition to the low state during or coinCident with phase one
(l!J1) will halt the microprocessor w~h the output address lines
reflecting the current address being fetched. If Ready is low
during a write cycle, it is ignored until the following read operation. This condition will remain through a subsequent phase two
(l!J2) in which the Ready signal is low. This feature allows microprocessor interfacing with the low speed PROMs as well as
Direct Memory Access (DMA).
RESET (RES)
The active low RES resets, or starts, the microprocessor from
a power down or restart condition. During the time that this line
is held low, writing to or from the microprocessor is inhibited.
When a positive edge is detected on the input, the microprocessor will immediately begin the reset sequence.
INTERRUPT REQUEST (IRQ)
After a system initialization time of six clock cycles, the mask
interrupt flag is set and the microprocessor loads the program
counter from the memory vector locations FFFC and FFFD. This
is the start location for program control.
The TTL level active-low Ti'iEi input requests that an interrupt
sequence begin within the microprocessor. The microprocessor
will complete the current instruction being executed before recognizing the request. At that time, the interrupt mask bit in the
Processor Status Register will be examined. If the interrupt
mask flag is not set, the microprocessor will begin an interrupt
sequence. The Program Counter and Processor Status Register
After Vcc reaches 4.75 volts in a power up routine, reset must
be held low for at least two clock cycles. At this time the RiW
and SYNC signals become valid.
2-4
R650X, R651X
R6500 Microprocessors (CPU)
R6502 FEATURES
m
VSS
• 64K addressable bytes of memory (AO-A15)
• On-chip clock
TTL-level single phase input
RC time base input
crystal time base input
• Two phase output clock for timing of support chips
• IRQ interrupt
AoV
(/)2 lOUT)
4»1 (OUT)
ml
i'Rci
¢lo (IN)
Ne
NMi
N,e
Ne
SYNC
R/'W
vee
DO
AD
01
A1
02
A3
03
04
os
os
A4
AS
• NMI interrupt
AS
AI;
• RDY signal
A8
A9
• SYNC signal
(can be used for single instruction execution)
A13
A12
A10
VSS
• 40-pin DIP
R6503 FEATURES
RES
02 fOUTI
V5S
OOON)
R/W
DO
iFio
NMr
vee
• 4K addressable bytes of memory (AO-A 11)
• On-chip clock
• IRQ Interrupt
AD
02
A'
A3
D4
03
• NMI interrupt
OS
oG
AS
• 28-pin DIP
AS
A11
A8
A9
A10
RES
210UTI
R6505 FEATURES
VSS
4>0 ON)
ADV
R/W
•
•
•
•
•
IFfb
4K addressable bytes of memory (AO-A 11)
On-chip clock
IRQ Interrupt
RDY signal
28-pin DIP
vee
0'
AD
A,
0'
A'
A3
04
A4
OS
OS
AS
AS
A11
A,O
A8
2-5
A9
R650X, R651X
R6500 Microprocessors (CPU)
REs
vss
R6506 FEATURES
<1>, (OUT)
iRa
vcc
• 4K addressable bytes of memory (AO-A11)
AO
A1
A2
A3
A4
A5
A6
A7
AS
• On-chip clock
• Two phase output clock for timing of support chips
• IRQ interrupt
• 28-pin DIP
RES
vss
R6507 FEATURES
•
•
•
•
AO
A1
A2
A3
A4
A5
A6
A7
AS
A9
8K addressable bytes of memory (AO-A12)
On-chip clock
ROY signal
28-pin DIP
vss
ROY
<1>, (IN)
IRQ
<1>2 (OUT)
<1>0 ON)
RiW
00
01
02
03
04
05
06
07
A11
A10
A9
<1>2 (OUT)
<1>0 ON)
RiW
DO
01
02
03
04
05
06
07
A12
A11
A10
RES
<1>2 (OUT)_
So
R6512 FEATURES
vss
NMi
<1>2 (IN).
OBE
N.C.
• 64K addressable bytes of memory (AO-A15)
SYNC
R/W
•
•
•
•
•
•
•
vcc
DO
01
02
03
04
05
06
07
Two phase clock input
IRQ interrupt
NMI interrupt
ROY signal
SYNC signal
Data Bus Enable
40-pin DIP
AO
A1
A2
A3
A4
A5
A6
A7
AS
A9
A10
A11
A15
A14
A13
A12
VSS
"Pins 37 and 39 are connected internally
2-6
R650X, R651 X
R6500 Microprocessors (CPU)
VSS
R6513 FEATURES
<1>, (IN)
fRO
• 4K addressable bytes of memory (AO-A 11)
AD
At
A2
A3
A4
A5
A6
A7
AS
DO
Ot
02
03
04
05
06
07
Att
AtD
A9
vss
RES
NMI
• Two phase clock input
• IRQ interrupt
• NMI interrupt
vcc
• 28-pin DIP
<1>, (IN)
R6514 FEATURES
• 8K addressable bytes of memory (AO-A12)
• Two phase clock input
• IRQ interrupt
• 28-pin DIP
RES
<1>2 (IN)
R/W
<1>2 (IN)
IRa
R/W
vcc
AD
At
A2
A3
A4
A5
A6
A7
AS
A9
DO
Ot
02
03
04
05
06
07
At2
Att
AtD
vss
RES
<1>2 (IN)
R/iiii
R6515 FEATURES
•
•
•
•
IRa
vcc
4K addressable bytes of memory (AO-f 11)
Two phase clock input
IRQ interrupt
RDY signal
AD
At
A2
A3
A4
A5
A6
A7
AS
• 28-pin DIP
2-7
DO
Ot
02
03
04
05
06
07
Att
AtD
A9
R6500 Microprocessors (CPU)
R650X, R651X
FUNCTIONAL DESCRIPTION
ARITHMETIC AND LOGIC UNIT (ALU)
The internal organization of all R6500 CPUs is identical except
for some variations in clock interface, the number of address
output lines, and some unique input/output lines between
versions.
All arithmetic and logic operations take place in the ALU including
incrementing and decrementing internal registers (except the program counter). The ALU has no internal memory and is used only to
perform logical and transient numerical operations.
CLOCK GENERATOR
ACCUMULATOR
The clock generator develops all intemal clock Signals, and (where
applicable) external clock signals, associated with the device. It is
the clock generator that drives the timing control unit and the externaltiming for slave mode operations.
The accumulator is a general purpose 8-bit register that stores
the results of most arithmetic and logic operations, and in addition, the accumulator usually contains one of the two data words
used in these operations.
TIMING CONTROL
INDEX REGISTERS
The timing control unit keeps track of the instruction cycle being
monitored. The unit is set to zero each time an instruction fetch is
executed and is advanced at the beginning of each phase one
clock pulse for as many cycles as is required to complete the
instruction. Each data transfer which takes place between the registers depends upon decoding the contents of both the instruction
register and the timing control unit.
There are two 8-bit index registers (X and V), which may be used
to count program steps or to provide an index value to be used in
generating an effective address.
When executing an instruction which specifies indexed addressing,
the CPU fetches the op code and the base address, and modifies
the address by adding the index register to it prior to performing the
desired operation. Pre- or post-indexing of indirect addresses is
possible (see addressing modes).
PROGRAM COUNTER
The 16-bit program counter provides the addresses which step
STACK POINTER
the microprocessor through sequential instructions in a program.
The stack pointer is an 8-bit register used to control the addressing
of the variable-length stack on page one. The stack pointer is automatically incremented and decremented under control of the microprocessor to perform stack manipulations under direction of either
the program or interrupts (NMI) and IRQ). The stack allows simple
implementation of nested subroutines and mu~iple level interrupts.
The stack pointer should be initialized before any interrupts or stack
operations occur.
Each time the microprocessor fetches an instruction from program memory, the lower byte of the program counter (PCL) is
placed on the low-order bits of the address bus and the higher
byte of the program counter (PCH) is placed on the high-order
8 bits. The counter is incremented each time an instruction or
data is fetched fromprogram memory.
INSTRUCTION REGISTER AND DECODE
PROCESSOR STATUS REGISTER
Instructions fetched from memory are gated onto the internal
data bus. These instructions are latched into the instuction register, then decoded, along with timing and interrupt signals, to generate control signals for the various registers.
The 8-bit processor status register contains seven status flags.
Some of the flags are controlled by the program, others may be
controlled both by the program and the CPU.
\
2-8
R650X, R651 X
R6500 Microprocessors (CPU)
.....-- REGISTER SECTION
CONTROL SECTION
-+
AO
AI
A3
t------~ SVNC2
ABL
A.
A'
AS
A7
ADDRESS
BUS2
A8
A.
Al0
.....1+-- ,,2
(IN),
A11
ASH
AI.
'---'-""lC:~-Ij~==+=+=~ ~ (OUnS
A13
L - - - . t I I 2 (OU1l3
L -_ _- . _
AI'
'-----D8E'
'"
ft
I
1.
2.
3.
4.
5.
6.
03
D.
-8 BIT LINE
DATA
8US
0'
DS
.. 1 BIT LINE
07
NOTE
CLOCK GENERATOR IS NOT INCLUDED ON R6512, R6513, R6514 AND R6515.
ADDRESSING CAPABILITY AND CONTROL OPTIONS VARY WITH EACH OF
THE CPUs.
R6502, R6503, R6504, R6505, R6506 AND R6507.
R6512, R6513, R6514 AND R6515.
R6512 ONLY.
R6502 AND R6506.
R650X and R651X Internal Architecture
2·9
R6500 Microprocessors (CPU)
R650X, R651X
INSTRUCTION SET
The R6500 CPU has 56 instruction types which are enhanced
by up to 13 addressing modes for each instruction. The
Accumulator, index registers, Program Counter, Stack Pointer
and Processor Status Register are illustrated below.
Alphabetic Listing of Instruction Set
Mnemonic
Function
Mnemonic
Function
ADC
AND
ASL
Add Memory to Accumulator with Carry
"AND" Memory with Accumulator
Shift LeI! One Bit (Memory or Accumulator)
JMP
JSR
Jump to New Location
Jump to New Location Saving Return Address
BCC
BCS
BEQ
BIT
BMI
BNE
BPL
BRK
BVC
BVS
Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits in Memory with Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Force Break
Branch on Overflow Clear
Branch on Overflow Set
LOA
LOX
LOY
LSR
Load Accumulator with Memory
Load Index X with Memory
Load Index Y with Memory
Shift One Bit Right (Memory or Accumulator)
NOP
No Operation
ORA
"OR" Memory with Accumulator
CLC
CLD
CLI
CLV
CMP
CPX
CPY
Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable
Clear Overflow Flag
Compare Memory and
Compare Memory and
Compare Memory and
PHA
PHP
PLA
PLP
Push Accumulator on Stack
Push Processor Status on Stack
Pull Accumulator from Stack
Putl Processor Status from Stack
ROL
ROR
RTI
RTS
Rotate
Rotate
Return
Return
DEC
DEX
DEY
Decrement Memory by One
Decrement Index, X by One
Decrement Index Y by One
EOR
"Exclusive-OR" Memory with Accumulator
SBC
SEC
SED
SEI
STA
STX
STY
Subtract Memory from Accumulator with Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Store Accumulator in Memory
Store Index X in Memory
Store Index Y in Memory
INC
INX
INY
Increment Memory by One
Increment Index X by One
Increment Index Y by One
TAX
TAY
TSX
TXA
TXS
TYA
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
I
·PCH
8
I7
A
I7
I7
V
I7
PCL
111
Accumulator
Index X
Index Y
7
0
7
15
Bit
I ACCUMULATOR
A
Y
0
X
I INDEX REGISTER
X
0
S
Accumulator to Index X
Accumulator to Index Y
Stack POinter to Index X
Index X to Accumulator
Index X to Stack Register
Index Y to Accumulator
0
I N I VlllB IDill zici PROCESSOR STATUS REG 'P"
0
I INDEX REGISTER
One Bit Left (Memory or Accumulator)
One Bit Right (Memory or Accumulator)
from Interrupt
from Subroutine
IPROGRAM COUNTER "PC"
0
ISTACK POINTER "S"
LCARRY
~
L
ZERO
1 =TRUE
1 = RESULT ZERO
IRQ DISABLE
' - - - - - DECIMAL MODE
' - - - - - - B R K COMMAND
' - - - - - - - OVERFLOW
'--------NEGATIVE
Programming Model
2-10
1 = DISABLE
1 = TRUE
1 = BRK
1 = TRUE
1 =NEG.
R6500 Microprocessor (CPU)
R650X, R651X
ADDRESSING MODES
The R6500 CPU family has 13 addressing modes. In the
following discussion of these addressing modes, a bracketed
expression follows the title of the mode. This expression is the
term used in the Instruction Set Op Code Matrix table (later in
this product description) to make it ea~er to identify the actual
addressing mode used by the instruction.
address. This type of indexing allows referencing of any location and the index may modify multiple fields, resulting in
reduced coding and execution time.
IMPLIED ADDRESSING [lmpJied]-ln the implied addressing mode, the address containing the operand is impliCitly stated
in the operation code of the instruction.
ACCUMULATOR ADDRESSING [Accum]-This form of
addressing is represented with a one byte instruction, implying
an operation on the accumulator.
RELATIVE ADDRESSING [Relative]-Relative addressing
is used only with branch instructions and establishes a destination for the conditional branch.
IMMEDIATE ADDRESS [IMM]-In immediate addressing,
the second byte of the instruction contains the operand, with
no further memory addressing required.
The second byte of the instruction is an operand. This operand
is an offset which is added to the program counter when the
counter is set at the next instruction. The range of the offset is
-128 to + 127 bytes.
ABSOLUTE ADDRESSING [Absolute]-In absolute
addressing, the second byte of the instruction specifies the eight
low order bits of the effective address while the third byte
specifies the eight high order bits. Thus, the absolute addressing mode allows access to the entire 64K bytes of addressable
memory.
INDEXED INDIRECT ADDRESSING [(IND, X)]-In indexed
indirect addressing (referred to as (Indirect, X)), the second byte
of the instruction is added to the contents of index register X
discarding the carry. The result of this addition points to a
memory location on page zero which contains the low order byte
of the effective address. The next memory location in page zero
contains the high order byte of the effective address. Both
memory locations specifying the effective address must be in
page zero.
ZERO PAGE ADDRESSING [ZP]-The zero page instructions allow for shorter code and execution times by fetching only
the second byte of the instruction and assuming a zero high
address byte. Careful use of the zero page can result in significant increase in code efficiency.
INDIRECT INDEXED ADDRESSING [(IND), Y)]-In
indirect indexed addressing (referred to as (Indirect), Y), the
second byte of the instruction points to a memory location in
page zero. The contents of this memory location are added to
the contents of index register Y. The result is the low order byte
of the effective address. The carry from this addition is added
to the contents of the next page zero memory location, to form
the high order byte of the effective address.
INDEXED ZERO PAGE ADDRESSING [ZP, X or Y]-This
form of addressing is used with the index register and is referred
to as "Zero Page, X" or "Zero Page, Y". The effective address
is calculated by adding the second byte to the contents of the
index register. Since this is a form of "Zero Page" addressing,
the content of the second byte references a location in page zero.
Additionally, due to the "Zero Page" addressing nature of this
mode, no carry is added to the high order eight bits of memory
and crossing of page boundaries does not occur.
ABSOWTE INDIRECT [Indirect]-The second byte of the
INDEXED ABSOLUTE ADDRESSING [ABS, X or Y)-
instruction contains the low order byte of a memory location.
The high order eight bits of that memory location are contained
in the third byte of the instruction. The contents of the fully specified memory location are the low order byte of the effective
address. The next memnory location contains the high order byte
of the effective address which is loaded into the sixteen bits of
the program counter. (JMP (IND) only)
This form of addressing is used in conjunction with X and Y index
register and is referred to as "Absolute, X" and "Absolute, Y."
The effective address is formed by adding the contents of X or
Y to the address contained in the second and third bytes of the
instruction. This mode allows the index register to contain the
index or count value and the instruction to contain the base
2-11
R650X, R651X
R6500 Microprocessors (CPU)
INSTRUCTION SET OP CODE MATRIX
The following matrix shows the Op Codes associated wah the
R6500 family of CPU devices. The matrix identifies the hexadecimal code. the mnemonic code. the addressing mode. the
LSD
A
2
BRK
ORA
Implied (IND. X)
,
7
2 6
BPL
ORA
Relative (IND). V
2 2"
2.3
2 3
2 5
AND
BMI
Relative (IND). V
2 2"
2 5"
AND
ZP.X
ROL
ZP, X
2 4
2 6
RTI
EOR
Implied (IND, X)
EOR
ZP
LSR
ZP
2 3
2 5
EOR
ZP. X
LSR
ZP, X
2 6
6
2 6
2 2"
2 5"
RTS
ADC
Implied (IND. X)
,
2 6
6
ADC
BVS
Relative (IND), V
2 2"
2 6
-
STA
BCC
Relative (IND), V
2 2"
PHP
Implied
,
3
CLC
Implied
,
2
PLP
Implied
,
4
SEC
Implied
,
2
PHA
Implied
,
3
CLI
Implied
,
ORA
IMM
2 2
AND
IMM
AND
ABS, V
AND
ABS, X
ROL
ABS, X
3 4"
3 4"
3
EOR
ABS
LSR
ABS
3 4
3 6
EOR
IMM
2 2
3 4"
DEV
Implied
2 3
2 3
2 3
1 2
STY
Zp, X
STA
ZP. X
STX
ZP, V
TVA
Implied
,
2
JMP
ABS
LSR
Accum
,
2
3 3
ADC
IMM
2 2
RDR
JMP
Accum
1 2
Indirect
3 5
3 4"
3 7
ADC
ABS
RDR
ABS
3 4
3 6
ADC
RDR
ABS, X ABS.X
3
TXA
Implied
,
STA
ABS. V
7
EOR
LSR
ABS. X ABS, X
3 4"
ADC
ABS, V
1 2
,
EOR
ABS, V
SEI
Implied
STX
ZP
ROL
Accum
3 7
ROL
ABS
RDR
ZP. X
2 6
3 4"
3 6
ADC
ZP. X
STA
ZP
3 6
3 4
2 5
2 4
3 4
ORA
ASL
ABS. X ABS, X
3 4
2 2
2 3
4
2
F
AND
ABS
2 6
,
E
ASL
ABS
BIT
ABS
ROR
ZP
2
,
o
ORA
ABS
C
3 4"
ADC
ZP
PLA
Implied
B
ASL
Accum
ORA
ABS. V
2 4
STV
ZP
2 5"
STA
(IND,X)
F
ASL
ZP. X
ROL
ZP
BVC
EOR
Relative (IND), V
E
2 5
2 6
,
o
2 3
ORA
ZP.X
AND
ZP
3 6
C
ASL
ZP
2 4
AND
Absolute (IND. X)
B
ORA
ZP
BIT
ZP
2 5"
JSR
A
number of instruction bytes. and the number of machine cycles
associated with each Op Code. Also. refer to the instruction set
summary for additional information on these Op Codes.
2
3
7
STA
ABS
STX
ABS
3 4
3 4
3 4
TXS
Implied
,
4"
STY
ABS
STA
ABS, X
2 4
2 4
2 4
LDV
IMM
LOA
(IND. X)
LOX
IMM
LDV
ZP
LOA
ZP
LOX
ZP
TAV
Implied
LOA
IMM
2 2
2 6
2 2
2 3
2 3
2 3
1 2
2 2
LDV
ZP.X
LOA
ZP. X
LOX
ZP, V
TSX
Implied
2 4
2 4
CLV
Implied
1 2
LOA
ABS, V
2 4
3 4"
1 2
3 4"
3 4"
3 4"
INV
Implied
1 2
CMP
IMM
DEX
Implied
crv
CMP
ABS
3 0\
DEC
ABS
2 6
BCS
LOA
Relative (IND). V
2
3 5
3 5
2
TAX
Implied
,
2
LDV
ABS
LOA
ABS
LOX
ABS
3 4
3 4
3 4
LDV
LOA
ABS, X ABS. X
LOX
ABS, V
2 2"
2 5"
CPV
IMM
CMP
(IND,X)
CPV
ZP
'CMP
ZP
DEC
ZP
2 2
2 6
2 3
2 3
2 5
CMP
ZP, X
DEC
ZP,X
CMP
ABS, X
DEC
ABS, X
2 6
CLD
Implied
1 2
CMP
ABS, V
2 4
3 4"
3 4"
3 7
CPX
ABS
sec
ABS
INC
ABS
3 4
3 4
3 6
BNE
CMP
Relatlve (IND), V
2 2"
2 5"
2 2
,
ABS
3 4
2
SBC
(IND, X)
CPX
ZP
sec
ZP
INC
ZP
INX
Implied
SBC
IMM
2 2
2 6
2 3
2 3
2 5
1 2
2 2
SBC
ZP, X
INC
ZP, X
SBC
ABS, V
secX
ABS,
2 4
2 6
SED
Implied
1 2
3 4"
3 4"
3 7
o
E
BEQ
SBC
Relative (IND), V
2 2" 2 5"
4
9
6
o
o
A
B
C
B
C
3 6
CPX
IMM
NDP
Implied
1 2
A
I
INC X
ABS,
o
E
I
F
"Add 1 to N if page boundary is crossed.
"Add 1 to N if branch occurs to same page;
add 2 to N if branch occurs to different page.
-op Code
-Addressing Mode
-Instruction Bytes; Machine Cycles
2-12
R650X, R651X
R6500 Microprocessors (CPU)
INSTRUCTION SET SUMMARY
,---,----i---,---,----,---,---,---,---,--,--,--.
.,---,----,
PAOCESSDRSUTUS
IMMEDIATE ABSIlUIH ZERO PAIiE
"tCLlM
IMPliED
liND. XI
(lNDI. Y
l PAIiE. J
IBS. Y
RElATIH
INDIRECT
l PAGE, Y CODES
IttSTRuctlQNS
MNEMONIC
OP n
,
OP n
14,(1) 69
'2
'2
60
111 29
'2
'2
20
4
3
DE
6
J
OPERATION
ADe
AND
c~-o
'CC
BRANCH ON C ,,0 121
'C S
BRANCHONC
BEO
BRANCH ON Z ,,1
=
4
•
J
J
'2
25
J
'2
06
5
'2
65
OP n
• OP n
• 0'
1542704
616'2
21
0.1,
'2
6
'2
31
5
'2
,
•
'2
3D
4
3
166'2
IE
7
3
35 4
QP n
,QP n
39
, T
M ,
BRANCH ON N ,,1
121
'N'
BRANCHQNZ ,,0
m
90
4
J
24
J
ADe
AND
,ee
,es
,,
'2
Z·
'2
JO' ,
DO '2
'2
'2
BRANCH ON N ,,0
121
avc
BRANCH ON II ,,0
121
'" , ,
,,
'v S
BRANCH ON II
=1
121
70'2
aPL
Ie
• Z.
"
FO'2
2C
'65432' 0
'NV.SOllC
• leA 5 L
(21
,
.OPn
4 J
1 (2)
,
.OPn
37943
00
'R K
7
,
BIT
,
M ,
'N'
'PL
B.A K
,VC
'v S
C LC
o-c
CLD
0-0
08
1
C L 0
C L ,
0-'
5821
C L ,
88
C L V
CM'
CP>
C9 '2
x_M
CPV
D'C
DEX
DEY
X-I
'2
CO 4
EO
'2
'2 EC 4
CO
'2
'2 CC 4
3 C!)
3
'2
J E4
3
'2
J C4 3
'2
CE
6
3 C6
5
2
2 40
4
3 45
3
2
'2
'2
C L V
1
CI 6
2 aT
5
'2 05
4
'2 DO 4
3 09 4
06 6
2 DE
7
3
55 4
2
4
3
• I C
• Z C
DEX
2
EE 6 3 E6
41
6
2
51
5
2
5~
'OR
l.
F6 6
52
E821
C8
JUMPTONEWLOC
4C
JUMPSU8
2063
3
2
LOX
z·
3
6C
LOY
A2
2
2 AE
111
AO
2
2 AC 4
3 A4
J
2
4E
3 46
5
2 4A
O-~C
4
6
J
A6
1
A-Ms
5-1-5
48
'H'
P-Ms
5-1-5
0831
PLA
PL ,
S .. 1-5
ROL
3 05
3
5
2 85
4
2 80 4
J
B9
4
4
2 BC
4
3
4
3
J M P
3
J
B6
4
2
2
LOA
Z·
LOX
Z C
01
6
2
11
5
2
15
4
2 10
19
4
J
1
'H A
68
5 .. 1-5
Ms-P
1--{7--,"-©::l
"
2E
63265
6E
6
3
5
2
2 ED
4
J E5 3
2
66
6A 2
IRESTOREO)
J. JE
N •••••
Z C
76627E
N •••••
Z C
~6
1
6
4061
R 7S
A - M - C-A
SEC
'-C
411
E9
2
, -a
S, ,
S T A
80
4
J
85
J
ST ,
8E
4
J
86
32
STV
8C 4
3 84
3
El
382
1
F82
1
782
1
2
6
2
Fl
5
4
2 Fa
4
3 F9
4
3
• Z 131
sec
SEC
SED
2 90
5
3
99
5
STA
3
96.
2
S-X
2 F5
81629162
srx
,
ST ,
9442
A
T S x
R 0 L
R 7 ,
,RESTORED)
RTRN5UB
S B C
SED
L S R
Nap
1
2
J
l'
I'
56625E
EA
2 00 4
81
84
NO OPERATION
2
2
2
NO'
ORA
09
6
5
B'
111
1 N C
I·
1
AI
L S R
0 EC
I.
N •
411 49
'NC
M'
x
C p y
-x.
'OR
J
JSR
C p
Z C
z.
,
,
· z
1
• 1
AS
2
BA
l.
1
l'
T 5 X
SA
2
1
Z'
T X A
982
1
I'
T YA
ADD 110 N IF PAGE 80UNDARY 15CROS5ED
INDEX X
121
AD01TO N IFBRANCHOCCURSTOSAMEPAGE
AOD 2 TO N IF BRANCH OCCURS TOOIFFERENT PAGE
INDEX Y
131
CARRY NOT = BORROW
14,
IF IN DECIMAL MODE Z FLAG IS INVALID
ACCUMULATOR MUST BE CHECKED FORIERO RESUl T
2·13
MEMORY BIT 7
SUBTRACT
M~
MEMORy BIT 6
AND
NO CYCLES
MEMORY PER EFFECTIVE ADDRESS
OR
NO BYTES
MEMORY PER STACK POINTER
EXCLUSIVE OR
ACCUMULATOR
TAY
R6500 Microprocessors (CPU)
R650X, R651X
R650X CLOCK TIMING
1--------TCyC--------i
,po (IN)
"'-------VIL
TFO
~2 (OUT)
REFB
R651X CLOCK TIMING
IE ••
REF A
R65XX READ WRITE TIMING
ADDRESS
LIES
=UNES -+----------1----1:"""_-+:::-:'1""
~WB-+---------t~~~~U----_t~~_
SYNC
RDV
2-14
R650X, R651X
R6500 Microprocessors (CPU)
AC CHARACTERISTICS
R65XX
(1 MHz)
Characteristic
Symbol
Min
I
R65XXA
(2 MHz)
Max
Min
I
R65XXB
(3 MHz)
Max
Min
I
Max
Unit
R650X CLOCK TIMING
Clock Cycle Time
Tcyc
1.0
110 (IN) Low Pulse Width
TL0e
480
110 (IN) High Pulse Width
T HOO
460
-
\10 (IN) Rise and Fall TIme'. 2
TRD. TFO
-
111 (OUT) High Pulse Width
TpWH&1
\12 (OUT) High Pulse Width
TpWH02
10
0.5
10
0.33
10
.,.s
240
-
160
-
ns
240
-
160
-
ns
10
-
10
-
10
ns
460
-
235
-
155
460
-
240
-
160
0
Delay Between \11 (OUT) and \12 (OUT)
To
0
-
\11 (OUT), 112 (OUT) Rise and Fall
TR, TF
-
25
10
-
0
-
-
25
-
15
ns
0.5
10
0.33
10
.,.s
ns
ns
ns
Time'. 2
R651 X CLOCK TIMING
Clock Cycle Time
Tcyc
1.0
\11 (IN) High Pulse Width
T pwH0,
430
\12 (IN) High Pulse Width
T pWH02
470
Delay Between 01 and 02
To
\11 (IN), \12 (IN) Rise and Fall Time'. 3
0
-
TR, TF
-
160
-
0
-
ns
0
-
25
-
20
-
15
ns
ns
215
235
150
ns
ns
R65XX READIWRITE TIMING
RIW Setup Time
TRws
-
225
-
140
-
110
RIW Hold Time
THRW
30
-
30
-
15
-
ns
Address Setup Time
TAOS
-
225
-
140
-
110
ns
Address Hold Time
THA
30
-
30
-
15
-
ns
Read Access TIme
TAce
-
650
-
310
-
170
ns
Read Data Setup Time
TDSU
100
ns
Read Data Hold Time
THR
Write Data Setup Time
50
-
50
-
10
-
10
-
10
-
ns
TMDS
-
175
-
100
-
85
ns
Write Data Hold Time
THw
30
15
-
ns
TSYH
30
-
-
SYNC Hold Time
ROY Setup TIme
TROY
100
-
50
-
SO Setup Time
Tso
100
-
50
-
SYNC Setup Time
TSYN
-
225
-
30
30
Notes:
1. Loads: All output except clocks = 1 TIL + 130 pF. Clock outputs = 1 TIL + 30 pF.
2. Measured between 0.8 and 2.0 points on waveform load.
3. Measured between 10% and 90% points on waveforms.
4. 'ROY must never switch states within RROY to end of 02.
2-15
140
35
-
-
110
15
35
ns
ns
ns
ns
fI
R6500 Microprocessors (CPU)
R650X, R651X
EXAMPLE OF TIME BASE GENERATION FOR R6502
UK
3.0K
R650X
15K
7404
7404
7404
L.----'--IOt-----'
R6502
2 (OUT)
XTAL
(1 MHz - 3 MHz)"
"CRYSTAL: CTS KNIGHTS MP SERIES, OR EQUIVALENT
2-16
R6500 Microprocessor (CPU)
R650X, R651X
ABSOLUTE MAXIMUM RATINGS·
Symbol
Value
Unit
Vee
-0.3 to +7.0
Vde
Input Voltage
V,N
-0.3 to + 7.0
Vde
Operating Temperature Range
Commercial
Industrial
TA
Storage Temperature
TSTG
Parameter
Supply Voltage
°NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in the other sections of this document is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
·C
-40 to +85
·C
-55 to +150
OPERATING CONDITIONS
Symbol
Value
Supply Voltage
Parameter
Vee
SV ±S%
Temperature Range
Commercial
TA
O·C to + 70·C
- 40·C to + 8S·C
Industri~1
DC CHARACTERISTICS
(Vee
= 5.0V
±5%. Vss
=
0; TA
= TL to T H• unless otherwise noted)
Parameter
Symbol
Input High Voltage
Logic
00 (IN)
01 (IN), 112 (IN)
V,H
Input Low Voltage
Logic
\110 (IN), \III (IN), 112 (IN)
V,L
Input Leakage Curre~
Logic (Excl. ROY. SO)
\III (IN). \112 (IN)
\110 (IN)
liN
Input Leakage Current lor Three State Oflf
00-07
ITSI
Output High Voltage
SYNC. 00-07. AO-A1S, Rm.lill (OUT). \112 (OUT)
VOH
Output Low Voltage
SYNC. 00-07, AO-AIS. Rm.lill (OUT).1il2 (OUT)
VOL
Power Dissipation
1 and 2 MHz
3 MHz
Po
Capacitance
Logic
00-07
AO-AIS. Rm. SYNC
110 (IN)
01 (IN)
\112 (IN)
C
C,N
Min.
Typ.S
Max.
Unit1
Test Conditions
V
2.0
2.4
Vee - 0.3
-0.3
-0.3
-
-
Vee
Vee
Vce + 0.25
V
0.8
004
-
-
-
2.5
100
10
-
-
10
+2.4
-
-
-
-
+004
-
-
450
500
700
800
-
-
-
-
10
15
12
15
50
80
"A
Y,N = OV to S.2SV
Ve = OV
"A
Y,N = OAV to 2.4V
Vec =S.2SV
V
ILOAO = -100"A
Vee = 4.7SV
V
ILOAO = I.S rna
Vee = 4.7SV
mW
pF
-
COUT
CIilO(IN)
C\IIl
C02
30
50
Notes:
1. All units are direct current (de) except lor capacitance.
2. Negative sign indicates outward current flow. positive indicates inward Ilow.
3. IRQ and NMI require 3K pull-up resistor.
4.01 (IN) and \112 (IN) apply to RSSI2. 13. 14, and 15; \110 (IN) applies to RSS02. 03, 04. 05. OS and 07.
5. Typical values shown lor Vee = S.OV and TA = 2S·C.
2-17
Vee = S.OV
V,N = OV
1= 1 MHz
TA = 2S·C
R6520
'1'
Rockwell
R6520
Peripheral Interface Adapter (PIA)
DESCRIPTION
FEATURES
The R6520 Peripheral Interface Adapter (PIA) is designed to
solve a broad range of peripheral control problems in the
implementation of microcomputer systems. This device allows
a very effective trade·off between software and hardware by
providing significant capability and flexibility in a low cost chip.
When coupled with the power and speed of the R6500, R6500r
or R65COO family of microprocessors, the R6520 allows
implementation of very complex systems at a minimum overall
cost.
• Two B·bit directional I/O ports with individual data direction
control
• Automatic "Handshake" control of data transfers
• Two interrupts (one for each port) with program control
• Commercial and industrial temperature range versions
• 40'pin plastic and ceramic versions
• 5 volt ± 5% supply requirements
• Compatible with the R6500, R6500/· and R65COO family of
microprocessors
Control of peripheral devices is handled primarily through two
B·bit bidirectional ports. Each of these lines can be programmed
to act as either an input or an output. In addition, four peripheral
control/interrupt input lines are provided. These lines can be
used to interrupt the processor or to "handshake" data between
the processor and a peripheral device.
•
1 and 2 MHz versions
ORDERING INFORMATION
VSS
PAD
CA,
CA2
PA,
PA 2
iRQA
PA3
RSO
PA4
RS,
RES
PAS
PA6
Part Number
R6520 __ _
Temperature Range (TL to T H):
Blank = ODC to + 70DC
E = -40D C to +B5D C
L
Package:
C = 40·Pin Ceramic DIP
P = 40·Pin Plastic DIP
'-- Frequency Range:
No letter = 1 MHz
A = 2 MHz
0,
PB O
°2
PB,
°3
PB 2
°4
PB3
Os
PB 4
°6
PBs
PB6
°7
PB 7
CS,
CS2
CB,
CB 2
Product Description
2·1B
°0
PA7
Figure 1.
Document No. 29651 N30
IRQB
\12
CSo
RtW
R6520 Pin Configuration
Order No. 2127
Rev. 4, June 1987
R6520
Peripheral Interface Adapter (PIA)
FUNCTIONAL DESCRIPTION
The R6520 PIA is organized into two independent sections
referred to as the A Side and the B Side. Each section consists
of a Control Register (CRA, CRB), Data Direction Register
(DDRA, DDRB), Output Register (ORA, OBR), Interrupt Status
Control (ISCA, ISCB), and the buffers necessary to drive the
Peripheral Interface buses. Data Bus Buffers (DBB) interface
data from the two sections to the data bus, while the Data Input
Register (DIR) interfaces data from the DBB to the PIA registers.
Chip Select and R/W control circuitry interface to the processor
bus control lines. Figure 2 is a block diagram of the R6520 PIA.
IRQA
t
DO
01
02
DATA BUS
BUFFER
(DBB)
03
04
05
06
-
CONTROL
REGISTERA
(CRA)
f4
-
OUTPUT BUS
k
~
~
07
I
~
CSO
CSl
-
CS2
RSO
RSl
RiW
.2
RES
~
~
CHIP
SELECT
& RiW
CONTROL
PERIPHERAL
OUTPUT
REGISTER B
(ORB)
CA2
l
I
~r
I
PERIPHERALll
OUTPUT
REGISTER A
(ORA)
U
DATA INPUT
REGISTER
(DIR)
CAl
INTERRUPT STATUS
CONTROL A (ISCA)
DATA DIRECTION
REGISTER A
(DORA)
U
b
~
PERIPHERAL
INTERFACE
BUFFER A
(PIBA)
PAO
PAl
PA2
PA3
PA4
PAS
PA6
PA7
PERIPHERAL
INTERFACE
BUFFER B
(PIBB)
PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7
~
~
~
~
{)
INPUT BUS
S
CONTROL
REGISTER B
(CRB)
~L
•
~
INTERRUPT STATUS
CONTROL B (ISCB)
IRQB
Figure 2.
DATA DIRECTION
REGISTER B
(DDRB)
R6520 PIA Block Diagram
2-19
CBl
CB2
R6520
Peripheral Interface Adapter (PIA)
DATA INPUT REGISTER (DIR)
PERIPHERAL OUTPUT REGISTERS (ORA, ORB)
When the microprocessor writes data into the PIA, the data
which appears on the data bus during the 02 clock pulse is
latched into the Data Input Register (DIR). The data is then
transferred into one of six internal registers of the PIA after the
trailing edge of the 02 clock. This assures that the data on the
peripheral output lines will make smooth transITions from high
to low (or from low to high) and the voltage will remain stable
except when it is going to the opposite polarity.
The Peripheral Output Registers (ORA, ORB) store the output
data from the Data Bus Buffers (DBB) which appears on the
Peripheral VO port. If a line on the Peripheral A Port is programmed as an output by the DDRA, writing a 0 into the corresponding bit in the ORA causes that line to go low «0.4 V);
writing a 1 causes the line to go high. The lines of the Peripheral
B port are controlled by ORB in the same manner.
INTERRUPT STATUS CONTROL (ISCA, ISCB)
CONTROL REGISTERS (CRA and CRB)
The four interrupVperipheral control lines (CA 1, CA2, CB1, CB2)
are controlled by the Interrupt Status Control logic (A, B). This
logic interprets the contents of the corresponding Control Register and detects active transitions on the interrupt inputs.
Table 1 illustrates the bit designation and functions in the two
control registers. The control registers allow the microprocessor
to control the operation of the Interrupt Control inputs (CA 1,
CA2, CB1, CB2), and Peripheral Control outputs (CA2, CB2).
Bit 2 in each register controls the addressing of the Data Direction Registers (DDRA, DDRB) and the Output Registers (ORA,
ORB). In addition, two bits (bit 6 and 7) in each control register
indicate the status of the Interrupt Input lines (CAl, CA2, CB1,
CB2). These Interrupt Status bits (IRQA1, IRQA2 or IRQB1,
IRQB2) are normally interrogated by the microprocessor during
the IRQ interrupt service routine to determine the source of the
interrupt.
PERIPHERAL 1/0 PORTS (PAO-PA7, PBO-PB7)
The Peripheral A and Peripheral B 1/0 ports allow the microprocessor to interface to the input lines on a peripheral device
by writing data into the Peripheral Output Register. They also
allow the processor to interface WITh the peripheral deVice output
lines by reading the data on the Peripheral Port input lines
directly onto the data bus and into the internal registers of the
processor.
Bit 2 (DDRA, DDRB) in each Control Register (eRA and CRB)
controls access to the Data Direction Register or the Peripheral
Interface. If bit 2 is a "1," a Peripheral Output Register (ORA,
ORB) is selected, and if bit 2 is a "0," a Data Direction Register
(DDRA, DDRB) is selected. The Data Direction Register Access
Control bit, together with the Register Select lines (RSO, RS1)
selects the various internal registers as shown in Table 2.
Each of the Peripheral VO lines can be programmed to act as
an input or an output. This is accomplished by setting a 1 in the
corresponding bit in the Data Direction Register for those lines
which are to act as outputs. A 0 in a bit of the Data Direction
Register causes the corresponding Peripheral VO lines to act
as an input.
In order to write data into DDRA, ORA, DDRB, or ORB registers,
bit 2 in the proper Control Register must first be set. The desired
register may then be accessed with the address determined by
the address interconnect technique used.
The buffers which drive the Peripheral A I/O lines contain "passive" pull-up devices. These pull-up devices are resistive in
nature and therefore allow the output voltage to go to VCC for
a logic 1. The switches can sink 1.6 mA, making thesse buffers
capable of driving one standard TTL load.
In the input mode, the pull-up devices are still connected to the
DATA DIRECTION REGISTERS (DORA, DDRB)
1/0 pin and still supply current to this pin. For this reason, these
The Data Direction Registers (DDRA, DDRB) allow the processor to program each line in the 8-bit Peripheral I/O port to
be either an input or an output. Each bit in DDRA controls the
corresponding line in the Peripheral A port and each btt in DDRB
controls the corresponding line in the Peripheral B port. Writing
a "0" in a bit position in the Data Direction Register causes the
corresponding Peripheral I/O line to act as an input; a "1"
causes it to act as an output.
Table 1.
7
CRA
CRB
6
IRQAl
IRQA2
7
6
IRQBl
IRQB2
5
lines also represent one standard TTL load in the input mode.
The Peripheral B I/O port duplicates many of the functions of
the Peripheral A port. The process of programming these lines
to act as an input or an output is similar to the Peripheral A port,
as is the effect of reading or writing this port. However, there
are several characteristics of the buffers driving these lines
which affect their use in peripheral interfacing.
Control Registers Bit Designations
4
3
CA2 Control
5
4
CB2 Control
2-20
2
1
DDRNORA
Select
3
2
DDRB/ORB
Select
0
CAl Control
1
0
CBl Control
Peripheral Interface Adapter (PIA)
R6520
CHIP SELECT (CSO, CS1, CS2)
The Peripheral B I/O port buffers are push-pull devices i.e., the
pull-up devices are switched OFF in the 0 state and ON for a
logic 1. Since these pull-ups are active devices, the logic 1
voltage will not go higher than +2.4V.
The PIA is selected when CSO and CSl are high and CS2 is
low. These three chip select lines are normally connected to the
processor address lines either directly or through external
decoder circuits. When the PIA is selected, data will be transferred between the data lines and PIA registers, and/or peripheral
interface lines as determined by the RiW, RSO, and RSl lines
and the contents of Control Registers A and B.
Another difference between the PAO-PA7 lines and the PBO
through PB71ines is that they have three-state capability which
allows them to enter a high impedance state when programmed
to be used as input lines. In addition, data on these lines will
be read properly, when programmed as output lines, even if the
data signals fall below 2.0 volts for a "high" state or are above
0.8 volts for a "low" state. When programmed as output, each
line can drive at least one TTL load and may also be used as
a source of up to 1 milliampere at 1.5 volts to directly drive the
base of a transistor switch, such as a Darlington pair.
RESET SIGNAL (RES)
The Reset (RES) input initializes the R6520 PIA. A low signal
on the RES input causes all internal registers to be cleared.
CLOCK SIGNAL (1/12)
DATA BUS BUFFER (DBB)
The Phase 2 Clock Signal (02) is the system clock that triggers
all data transfers between the CPU and the PIA. 02 is generated by the CPU and is therefore the synchronizing signal
between the CPU and the PIA.
The Data Bus Buffer is an 8-bit bidirectional buffer used for data
exchange, on the DO-D7 Data Bus, between the microprocessor and the PIA. This buffer is tri-stateable and is capable of
driving a two TTL load (when operating in an output mode) and
represents a one TTL load to the microprocessor (when
operating in an input mode).
READ/WRITE SIGNAL (R/W)
ReadlWrite (RiW) controls the direction of data transfers
between the PIA and the data lines associated with the CPU
and the peripheral devices. A high on Ihe RiW line permits the
peripheral device to transfer data to the CPU from the PIA. A
low on the RiW line allows data to be transferred from the CPU
to the peripheral devices from the PIA.
INTERFACE SIGNALS
The PIA interfaces to the R6500, R6500/" or the R65COO microprocessor family with a reset line, a 0 clock line, a read/write
line, two interrupt request lines, two register select lines, three
chip select lines, and an 8-bit bidirectional data bus.
REGISTER SELECT (RSO, RS1)
The PIA interfaces to the peripheral device with four interrupti
control lines and two 8-bit bidirectional data ports.
The two Register Select lines (RSO, RS1), in conjunction with
the Control Registers (CRA, CRB) Data Direction Register
access bits (bit 2), select the various R6520 registers to be
accessed by the CPU. RSO and RSl are normally connected
to the microprocessor (CPU) address output lines. Through control of these lines, the CPU can write directly into the Control
Figure 1 (on the front page) shows the pin assignments for these
interface signals and Figure 3 shows the interface relationship
of these signals to the CPU and the peripheral devices .
00-07
...
~
(8)
(8)
> PAO-PA7
1\2
R6500,
R65001"
OR
R65COO
MICROPROCESSOR
FAMILY
CAt
CA2
RrW
RSO
RSt
CSO
CSt
CS2
RES
IROA
IROB
VSS
VCC
}
PERIPHERAL
DEVICE
A
R6520
PIA
..
.....
..
-'(8)
Figure 3.
Interface Signals Relationship
2-21
.
CBt
CB2
~ PBO-PB7
}
PERIPHERAL
DEVICE
B
fI
Peripheral Interface Adapter (PIA)
R6520
Registers (CRA, CRB), the Data Direction Registers (DORA,
DDRB), and the Peripheral Output Registers (ORA, ORB). In
addition, the processor may directly read the contents of the
Control Registers and the Data Direction Registers. Table 2
shows the internal register address decoding.
transition on CB2, and IROB from this flag is controlled by CRB
bit 3.
Also, both bit 6 and bit 7 of CRB are reset by a "Read Peripheral
B Output Register" operation. A summary of IROB control is
shown in Table 3.
Table 3.
Table 2.
Internal Register Addressing
Register
Data Direction
Select Lines
Control
Register
Address
(Hex)
RSI
0
0
1
2
2
3
L
L
L
H
H
H
RSO
L
L
H
L
L
H
CRA CRB
(Bit 2) (Bit 2)
1
0
-
-
1
0
-
-
Register Operation
R,w=H
Read
Read
Read
Read
Read
Read
PIBA
DDRA
CRA
PIBB
DDRB
CRB
IRQA and IRQB Control Summary
Control Register Bits
R,w=L
Write
Write
Write
Write
Write
Write
Action
CRA-7=1 and CRA-O=l
IROA goes low (Active)
CRA-6=1 and 'CRA-3=1
IRQA goes low (Active)
CRB-7=1 and CRB-O=l
IROB goes low (Active)
IROB goes low (Active)
CRB-6=1 and CRB-3=1
ORA
DDRA
CRA
ORB
DDRB
CRB
Note:
The flags act as the link between the peripheral interrupt signals
and the processor interrupt inputs. The interrupt disable bits allow
the processor to control the interrupt function.
INTERRUPT INPUT/PERIPHERAL CONTROL LINES
(CA1, CA2, CB1, CB2)
INTERRUPT REQUEST LINES (IRQA, IRQB)
The four interrupt input/peripheral control lines provide a number
of special peripheral control functions. These lines greatly
enhance the power of the two general purpose interface ports
(PAO-PA7, PBO-PB7). Figure 4 summarizes the operation of
these control lines.
The active low Interrupt Request lines (IROA and IROB) act to
interrupt the microprocessor either directly or through external
interrupt priority circuitry. These lines are open drain and are
capable of sinking 1.6 milliamps from an external source. This
permits all interrupt request lines to be tied together in a wiredOR configuration. The A and B in the titles of these lines correspond to the peripheral port A and the peripheral port B so
that each interrupt request line services one peripheral data
port.
CAl is an interrupt input only. An active transition of the signal
on this input will set bit 7 of the Control Register A to a logic 1.
The active transition can be programmed by setting a "0" in bit
1 of the CRA if the interrupt flag (bit 7 of CRA) is to be set on
a negative transition of the CAl signal or a "1" if it is to be set
on a positive transition.
Each Interrupt Request line has two interrupt flag bits which can
cause the Interrupt Request line to go low. These flags are bits
6 and 7 in the two Control Registers (CRA, CRB). These flags
act as the link between the peripheral interrupt signals and the
microprocessor interrupt inputs. Each flag has a corresponding
interrupt disable bit which allows the processor to enable or disable the interrupt from each of the four interrupt inputs (CAl,
CA2, CBI, CB2). The four interrupt flags are set (enabled) by
active transitions of the signal on the interrupt input (CAl, CA2,
CB1, CB2).
Note:
A negative transition is defined as a transition from a high
to a low, and a positive transition is defined as a transition
from a low to a high voltage.
CA2 can act as a totally independent interrupt or as a peripheral
control output. As an input (CRA, bit 5 = 0) it acts to set the
interrupt flag, bit 6 of CRA, to a logic 1 on the active transition
selected by bit 4 of CRA.
CRA bit 7 (IROA1) is always set by an active transition of the
CAl interrupt input signal. However, IROA can be disabled by
setting bit 0 in CRA to a O. Likewise, CRA bit 6 (lROA2) can be
set by an active transitioll of the CA2 interrupt input signal and
IROA can be disabled by setting bit 3 in CRA to a O.
These control register bits and interrupt inputs serve the same
basic function as that described above for CAl. The input signal
sets the interrupt flag which serves as the link between the
peripheral device and the processor interrupt structure. The
interrupt disable bit allows the processor to exercise control over
the system interrupt.
Both bit 6 and bit 7 in CRA are reset by a "Read Peripheral
Output Register A" operation. This is defined as an operation
in which the read/write, proper data direction register and register select signals are provided to allow the processor to read
the Peripheral A I/O port. A summary of IROA control is shown
in Table 3.
In the output mode (CRA, bit 5 = 1), CA2 can operate independently to generate a simple pulse each time the microprocessor reads the data on the Peripheral A I/O port. This mode
is selected by setting CRA, bit 4 to a 0 and CRA, bit 3 to a I.
This pulse output can be used to control the counters, shift registers, etc., which make sequenllal data available on the Peripheral input lines.
Control of IROB is performed in exactly the same manner as
that described above for IROA. Bit 7 in CRB (IROB1) is set by
an active transition on CBl and IROB from this flag is controlled
2-22
R6520
Peripheral Interface Adapter (PIA)
CONTROL REGISTER A (CRA)
CA2 INPUT MODE (BIT 5
= 0)
7
6
5
4
3
2
1
0
IRQAl
FLAG
IRQA2
FLAG
CA21NPUT
MODE SELECT
(=0)
IRQA2
POSITIVE
TRANSITION
IRQA
ENABLE
FOR IRQA2
DDRNORA
SELECT
IRQAl
POSITIVE
TRANSITION
IRQA
ENABLE
FOR IRQAl
IRQNlRQAl
CONTROL
IRQNlRQA2
CONTROL
CA2 OUTPUT MODE (BIT 5 = 1)
7
6
5
4
3
2
1
0
IRQAl
FLAG
a
CA20UTPUT
MODE SELECT
(=1)
CA2
OUTPUT
CONTROL
CA2
RESTORE
CONTROL
DDRNORA
SELECT
IRQAl
POSITIVE
TRANSITION
IRQA
ENABLE
FOR IRQAl
IRQA/IRQAl
CONTROL
CA2
CONTROL
CA21NPUT OR OUTPUT MODE (BIT 5
Bit 7
1
a
=0 or 1)
IRQAl FLAG
A transition has occurred on CAl that satisfies the bit 1 IRQAl transition polarity criteria. This bit is cleared by a read of Output Register
A or by RES.
No transition has occurred on CAl that satisfies the bit 1 IRQAl transition polarity criteria.
Bit 2
1
a
OUTPUT REGISTER A SELECT
Select Output Register A.
Select Data Direction Register A.
Bit 1
1
IRQAl POSITIVE TRANSITION
Set IRQAl Flag (bit 7) on a positive (low-to-high) transition of CAL
Set IRQAl Flag (bit 7) on a negative (high-to-Iow) transition of CAl.
Bit 0
1
IRQA ENABLE FOR IRQAl
Enable assertion of IRQA when IRQAl Flag (bit 7) is set.
Disable assertion of IRQA when IRQAl Flag (bit 7) is set.
a
a
CA2 INPUT MODE (BIT 5
Bit 6
1
a
= 0)
CA2 OUTPUT MODE (BIT 5
IRQA2 FLAG
A transition has occurred on CA2 that satisfies the bit 4
IRQA2 transition polarity criteria. This flag is cleared by
a read of Output Register A or by RES.
No transition has occurred on CA2 that satisfies the bit
4 IRQA2 transition polarity criteria.
Bit 5
CA2 MODE SELECT
Select CA2 Input Mode.
Bit 4
1
IRQA2 POSITIVE TRANSITION
Set IRQA2 Flag (bit 6) on a positive (Iow-to-high)
transition of CA2.
Set IRQA2 Flag (bit 6) on a negative (high-to-Iow)
transition of CA2.
o
o
Bit 3
1
o
NOT USED
Always zero.
Bit 5
1
CA2 MODE SELECT
Select CA2 Output Mode.
Bit 4
1
CA2 OUTPUT CONTROL
CA2 goes low when a zero is written into CRA bit 3.
CA2 goes high when a one is written into CRA bit 3.
CA2 goes low on the first negative (high-to-Iow) 02
clock transition following a read of Output Register A.
CA2 returns high as specified by bit 3.
o
o
Bit 3
1
o
IRQA ENABLE FOR IRQA2
Enable assertion of IRQA when IRQA2 Flag (bit 6) is
set.
Disable assertion of IRQA when IRQA2 Flag (bit 6) is
set.
Figure 4_
CA2 READ STROBE RESTORE CONTROL (4 = 0)
CA2 returns high on the next 02 clock negative
transition following a read of Output Register A.
CA2 returns high on the next active CAl transition
following a read of Output Register A as specified by
bit 1.
Control Line Operations Summary (1 of 2)
2-23
= 1)
Bit 6
R6520
Peripheral Interface Adapter (PIA)
CONTROL REGISTER B (CRB)
CB2 INPUT MODE (BIT 5 = 0)
7
6
5
4
3
2
1
0
IROBl
FLAG
IROB2
FLAG
CB21NPUT
MODE SELECT
IROB2
POSITIVE
TRANSITION
IROB
ENABLE
FOR IROB2
DDRB/ORB
SELECT
IROBI
POSITIVE
TRANSITION
IROB
ENABLE
FOR IROBI
(~O)
IROB/IROB2
CONTROL
IROB/IROBI
CONTROL
CB2 OUTPUT MODE (BIT 5 = 1)
7
6
5
4
3
2
1
0
IROBI
FLAG
a
CB20UTPUT
MODE SELECT
CB2
OUTPUT
CONTROL
CB2
RESTORE
CONTROL
DDRB/ORB
SELECT
IROBI
POSITIVE
TRANSITION
IROB
ENABLE
FOR IROBI
(~I)
IROB/IROBI
CONTROL
CB2
CONTROL
CB21NPUT OR OUTPUT MODE (BIT 5
Bit 7
I
a
= 0 or 1)
IRQBl FLAG
A transition has occurred on CBI that satisfies the bit I IROBl transition polarity criteria. This bit is cleared by a read of Output Register
B or by RES.
No transition has occurred on CBI that satisfies the bit I IROBI transition polarity criteria.
Bit 2
I
OUTPUT REGISTER B SELECT
Select Output Register B.
Select Data Direction Register B.
Bit 1
I
IRQBl POSITIVE TRANSITION
Set IROBI Flag (bit 7) on a pos~ive (Iow-to-high) transition of CBI.
Set IROBI Flag (bit 7) on a negative (high-to-Iow) transition of CBI.
Bit 0
1
IRQB ENABLE FOR IRQBl
Enable assertion of iRQB when IROBI Flag (bit 7) is sel.
Disable assertion of iRQB when IROBI Flag (bit 7) is sel.
a
a
a
CB2 INPUT MODE (BIT 5 = 0)
Bit 6
a
CB2 OUTPUT MODE (BIT 5
IRQB2 FLAG
A trans~ion has occurred on CB2 that satisfies the bit 4
IROB2 transition polar~ criteria. This flag is cleared by
a read of Output Register B or by RES.
No transition has occurred on CB2 that satisfies the bit
4 IROB2 transition polarity criteria.
Bit 5
CB2 MODE SELECT
Select CB2 Input Mode.
Bit 4
IRQB2 POSITIVE TRANSITION
Set IROB2 Flag (bit 6) on a positive (low-to-high)
transition of CB2.
Set IROB2 Flag (bit 6) on a negative (high-to-Iow)
transition of CB2.
a
NOT USED
Always zero.
Bit 5
I
CB2 MODE SELECT
Select CB2 Output Mode.
Bit 4
1
CB2 OUTPUT CONTROL
CB2 goes low when a zero is written into CRB bit 3.
CB2 goes high when a one is written into CRB bit 3.
CB2 goes Iowan the first negative (high-to-Iow) 02
clock transition following a write to Output Register B.
CB2 returns high as specified by bit 3.
a
D
a
Bit 3
a
Bit 3
IRQB ENABLE FOR IRQB2
Enable assertion of IROB when IROB2 Flag (bit 6) is
sel.
Disable assertion of IROB when IROB2 Flag (bit 6) is
sel.
Figure 4.
a
CB2 WRITE STROBE RESTORE CONTROL
(BIT 4 = 0)
CB2 returns high on the next 02 clock negative
transition following a write to Output Register B.
CB2 returns high on the next active CBI transition
following a write to Output Register B as specified by
bit I.
Control Line Operations Summary (2 of 2)
2-24
= 1)
Bit 6
R6520
Peripheral Interface Adapter (PIA)
transfers the data on the Peripheral A 110 lines to the data bus.
In this situation, the data bus will contain both the input and output data. The processor must be programmed to recognize and
interpret only those bits which are important to the particular
peripheral operation being performed.
A second output mode allows CA2 to be used in conjunction
with CA1 to "handshake" between the processor and the
peripheral device. On the A side, this technique allows positive
control of data transfers from the peripheral device into the
microprocessor. The CA 1 input signals the processor that data
is available by interrupting the processor. The processor reads
the data and sets CA2 low. This signals the peripheral device
that it can make new data available.
Since the processor always reads the Peripheral A 1/0 port pins
instead of the actual Peripheral Output Register (ORA), it is
possible for the data read by the processor to differ from the
contents of the Peripheral Output Register for an output line.
This is true when the 110 pin is not allowed to go to a full
+ 2.4V DC when the Peripheral Output register contains a
logic 1. In this case, the processor will read a 0 from the
Peripheral A pin, even though the corresponding bit in the
Peripheral Output register is a 1.
The final output mode can be selected by setting bit 4 of CRA
to a 1. In this mode, CA2 is a simple peripheral control output
which can be set high or low by setting bit 3 or CRA to a 1 or
a 0 respectively.
CB 1 operates as an interrupt input only in the same manner as
CA 1. Bit 7 of CRB is set by the active transition selected by bit
o of CRB. Likewise, the CB2 input mode operates exactly the
same as the CA2 input modes. The CB2 output modes, CRB
bit 5 = 1, differ somewhat from those of CA2. The pulse output
occurs when the processor writes data into the Peripheral B Output Register. Also, the "handshaking" operates on data transfers
from the processor into the peripheral device.
READING THE PERIPHERAL B 110 PORT
Reading the Peripheral B 1/0 port yields a combination of input
and output data in a manner similar to the Peripheral A port.
However, data is read directly from the Peripheral B Output
Register (ORB) for those lines programmed to act as outputs.
It is therefore possible to load down the Peripheral B Output lines
without causing incorrect data to be transferred back to the
processor on a Read operation.
READING THE PERIPHERAL A 110 PORT
Performing a Read operation with RS1 = 0, RSO = 0 and the
Data Direction Register Access Control bit (CRA-2) = 1, directly
1l2------.....J)
RSO, RS1,
CSO,CS1,CS2
00-07
DATA OUT
CA2
(PULSE OUT)
CA1
CA2
(HAND SHAKE)
Figure 5.
Read Timing Waveforms
2-25
II
Peripheral Interface Adapter (PIA)
R6520
RSO, RS1,
CSO, CS1, CS2
RIW
00-07
DATA IN
PAO-PA7
PBO-PB7
~~i~~%~~oo:5<:'X~~~T------t----------",""AA~':::"::'QQo:::':';'~~ 1t-~I--------I------------
CB2
(PULSE OUT)
CB1
CB2
(HAND SHAKE)
Figure 6.
Write Timing Waveforms
2·26
Peripheral Interface Adapter (PIA)
R6520
BUS TIMING CHARACTERISTICS
2 MHz
1 MHz
Parameter
02 Cycle
02 Pulse Width
02 Aise and Fall Time
Symbol
Min.
tCYC
tc
lrc. tfc
1.0
0.47
-
Max.
-
5
25
Min.
Max.
0.5
0.24
-
-
5
15
Unit
"S
"S
ns
READ TIMING
Address Set·Up Time
Address Hold Time
Peripheral Data Set·Up Time
Data Bus Delay Time
Data Bus Hold Time
-
90
0
150
395
-
t ACA
tCAA
tpCA
tCDA
tHA
180
0
300
10
-
tACW
tCAW
t wcw
tcww
t DCW
tHW
180
0
130
50
300
10
-
tpCA
tCDW
tCMOS
300
-
-
-
-
190
10
-
-
-
90
0
65
25
150
10
-
150
ns
ns
ns
ns
ns
WRITE TIMING
Address Set·Up Time
Address Hold Time
Am Set·Up Time
Am Hold Time
Data Bus Set-Up Time
Data Bus Hold Time
-
-
-
-
ns
ns
ns
ns
ns
ns
PERIPHERAL INTERFACE TIMING
Peripheral Data Set-Up
Peripheral Data Delay Time
Peripheral Data Delay TIme to
CMOS Level
02 Low to CA2 low Delay
02 low to CA2 High Delay
CAl Active to CA2 High Delay
02 High to CB2 low Delay
Peripheral Data Valid to CB2 Low Delay
02 High to CB2 High Delay
CBl Active to CB2 High Delay
CAl. CA2. CBl and CB2
Input Rise and Fall Time
tCA2
tAS !
t AS2
tCB2
t DC
tAS !
'AS2
tr.t,
-
-
-
0
-
2-27
1.0
2.0
1.0
1.0
2.0
1.0
1.5
1.0
2.0
1.0
-
ns
-
0.5
1.0
"S
-
0.5
0.5
1.0
0.5
0.75
0.5
1.0
1.0
-
0
-
-
""
"S
"s
"S
"s
""
"s
"s
"s
Peripheral Interface Adapter (PIA)
R6520
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
Value
Unit
Vee
-0.3 to +7.0
Vdc
Input Voltage
Y'N
-0.3 to +Vee
Vdc
Operating Temperature Range
Commercial
Industrial
TA
TL TH
o to + 70
-40 to +85
·C
Storage Temperature
TSTG
-55 to +150
·C
Supply Voltage
·NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in the other sections of this document is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
OPERATING CONDITIONS
Parameter
Symbol
Value
Supply Voltage
Vee
5V ±5%
Temperature Range
Commercial
Industrial
TA
O·C to 70·C
- 40·C to + 85·C
DC CHARACTERISTICS
(Vee
= 5.0V
±5%, VSS
= 0, TA = TL to T H, unless otherwise
noted)
Min.
Typ.-
Max.
Unit'
Input High Voltage
V,H
+2.0
-
Vee
V
Input Low Voltage
V ,L
-0.3
-
+0.8
V
Input Leakage Current
RiW, RES, RSO, RS1, CSO, CS1, CS2,
CA1, CB1, 02
liN
-
±1
±2.5
pA
Y'N = OV to 5.0V
Vee = OV
Input Leakage Current lor Three-State Off
00-07, PBO-PB7, CB2
ITSI
-
±2
±10
pA
Y,N = OAV to 2.4V
Vee = 5.25V
Input High Current
PAO-PA7, CA2
I'H
pA
V,H = 2AV
Input Low Current
PAO-PA7, CA2
I,L
mA
V,L = OAV
Output High Voltage
All outputs
PBO-PB7, CB2 (Darlington Drive)
VOH
Output Low Voltage
VOL
Output High Current (Sourcing)
Logic
PBO-PB7, CB2 (Darlington Drive)
IOH
Output Low Current (Sinking)
10L
1.6
Output Leakage Current (Off State)
IRQA, IRQB
10FF
-
Parameter
Symbol
Power Dissipation
PD
Input Capacitance
00-07, PAO-PA7, PBO-PB7, CA2, CB2
RiW, RES, RSO, RS1,CSO, CS1,CS2
CA1, CB1, 02
C,N
Output Capacitance
COUT
-100
-250
-
-1
204
-
1.5
-
-
-
-100
-1.0
-1000
-2.5
-
-1.6
-
V
V
Test Conditions
Vee = 4.75V
ILOAD = -100pA
ILOAD = -1.0 mA
+004
V
-
pA
mA
VOH = 2AV
VOH = 1.5V
-
-10
Vec = 4.75V
ILOAD = 1.6 mA
mA
VOL = 0.4V
1
±10
pA
VOH = 2AV
Vcc = 5.25V
200
500
mW
-
-
10
7.0
20
-
-
10
pF
Notes:
1. All units are direct current (de) except lor capacitance.
2. Negative sign indicates outward current Ilow, positive indicates inward flow.
3. Typical values are shown lor Vee = 5.0V and TA = 25·C.
2-28
pF
Vec = 5.0V
Y'N = OV
1= 1 MHz
TA = 25·C
Perlpheral
.
Interface Adapter (PIA).
R6520
----===[J~]]l
m-----l~~
Inll
B
C
L.,;...,1r-[
t
F
- - - A ____
"J~~D
...... ,2~n~n..JLJl..Jl....-
I/=t=i=
W 1..-.-1/
H
WRITE ORA, ORB
OPERATION
----I
"DATA READY"
HANDSHAKE MODE
g:~A READY
PULSE MODE
(CA2, CB2)
"DATA TAKEN
(CAl, CB1)
IRQ OUTPUT
(CA2,
I
~
I/~
III--_ _ _~
r--II
~
n
1/
I
I
/I,..,..,"""---+_I
vmflZ/Zl/.Z2?J
11----....,______ /
Figure 10.
L..-..--
Write Handshake Timing
2-35
r-
II
Versatile Interface Adapter (VIA)
R6522
COUNTER/TIMERS
disables any further interrupts and automatically transfers the
contents of the latches into the counter and continues to decrement. In addition, the timer may be programmed to invert the
output signal on peripheral pin PB7 each time it "times-out".
Each of these modes is discussed separately below.
There are two independent 16-bit counte(/timers (called TImer 1
and Timer 2) in the R6522. Each timer is controlled by writing
bits into the Auxiliary Control Register (ACR) to select the mode
of operation (Figure 14).
Note that the processor does not write directly into the low-order
counter (T1 Col). Instead, this half of the counter is loaded
automatically from the low order latch (T1 L-L) when the
processor writes into the high order counter (T1 C-H). In fact, it
may not be necessary to write to the low order counter in some
applications since the timing operation is triggered by writing
to the high order latch.
Timer 1 Operation
Interval Timer T1 consists of two S-bit latches (Figure 12) and
a 16-bit counter (Figure 13). The latches store data which is to
be loaded into the counter. After loading, the counter decrements
at 02 clock rate. Upon reaching zero, an interrupt flag is set,
and IRQ goes low if the T1 interrupt is enabled. Timer 1 then
REG 6-TIMER 1 LOW-ORDER LATCH
REG 7-TIMER 1 HIGH-ORDER LATCH
I+H+12I,IL
1+IsI+H+1
~t~
~~
32
'---------64
COUNT
VALUE
'--------'638.
'---------'2.
'----------32768
WRITE - 8 BITS LOADED INTO T1 LOW-ORDER
WRITE - 8 BITS LOADED INTO 11 HIGH-QRDER
LATCHES UNLIKE REG 4 OPERATION
LATCHES THIS OPERATION IS NO
DIFFERENT THAN A WAITE INTO
NO LATCH·TO-CDUNTER TRANSFERS
REG 4
TAKE PLACE.
READ - 8 BITS FROM T1 LQW.{)ADER LATCHES
READ - 8 BITS FROM T1 HIGH'()RDER LATCHES
TRANSFERRED TO MPU UNLIKE REG 4
OPERATION, THIS DOES NOT CAUSE
RESET OF T1 INTERRUPT FLAG
TRANSFERRED TO MPU.
Figure 12.
Timer 1 (T1) Latch Registers
REG 4-TIMER 1 LOW-ORDER COUNTER
REG 5-TIMER 1 HIGH-ORDER COUNTER
COUNT
VALUE
COUNT
VALUE
'-------32
' - - - - - - - 8'92
'--------64
'--------'638.
'---------'28
'---------32768
WRITE - 8 BITS LOADED INTO T1 LOW.()RDER
LATCHES. LATCH CONTENTS ARE
TRANSFERRED INTO LDW.()RDER
COUNTER AT THE TIME THE HIGH·
ORDER COUNTER IS LOADED (REG 5).
WRITE - 8 BITS LODED INTO T1 HIGH-OROER
LATCHES. ALSO, AT THIS TIME BOTH
READ - 8 BITS FROM T1 LOW·ORDER COUNTER
TRANSFERRED TO MPU. IN ADDITION,
T1 INTERRUPT FLAG IS RESET (BIT 6
IN INTERRUPT FLAG REGISTER).
READ - 8 IBTS FROM T1 HIGH·ORDER COUNTER
TRANSFERRED TO MPU
HIGH· AND lOW-ORDER LATCHES
TRANSFERRED INTO T1 COUNTER.
T1 INTERRUPT FLAG ALSO IS RESET
Figure 13.
Timer 1 (n) Counter Registers
2-36
Versatile Interface Adapter (VIA)
R6522
REG 11-AUXILIARY CONTROL REGISTER
E
l'i'i i i i'i'i o l
5
'
T1 TIMER CONTROL
7 6 OPERATION
0 TIMED INTERRUPT
EACH TIME T1 IS
LOADED
CONTINUOUS
INTERRUPTS
1 0 TIMED INTERRUPT
EACH TIME T1 IS
LOADED
1 CONTINUOUS
INTERRUPTS
I
'
PB'
o
DISABLED
4
3
PB
'"""'.~"""."':;1
IO~DISABLE
1· ENABLE LATCHING
o ,
ONE SHOT
OUTPUT
,
SHIfT REGISTER CONTROL
43 2 OPERATION
SOU ARE
o0 o
00 1
o , o
o , 1
, 0 o
WAVE
OUTPUT
12 TIMER CONTROL
5 OPERATION
o
DISABLED
SHIFT IN UNDER CONTROL OF 12
SHIFT IN- UNDER CONTROL OF 02
SHIFT IN UNDER CONTAOL OF EXT. elK
SHIFT OUT FREE·RUNNING AT T2 RATE
,, ,, o
, 0 1 SHIFT OUT UNDER CONTROL OF T2
TIMED INTERRUPT
'1 ~~~:E~ ~~~~:'TH j
SHIFT OUT UNDER CONTROL OF 02
1 SHIFT OUT UNDER CONTROL OF EXT elK
Figure 14.
Auxiliary Control Register (ACR)
Timer 1 One-Shot Mode
that the low order latch contains the proper data before initiating the count-down with a "write T1C-H" operation. When the
processor writes into the high order counter (T1 C-H), the T1 interrupt flag will be cleared, the contents of the low order latch will
be transferred into the low order counter, and the timer will begin
to decrement at system clock rate. If the PB7 output is enabled,
this signal will go low on the falling edge of 02 following the
write operation. When the counter reaches zero, the T1 interrupt flag will be set, the IRQ pin will go low (interrupt
enabled), and the signal on PB7 will go high. At this time the
counter will continue to decrement at system clock rate. This
allows the system processor to read the contents of the counter to determine the time since interrupt. However, the T1 interrupt flag cannot be set again unless it has been cleared as
described in this specification.
The Timer 1 one-shot mode generates a single interrupt for each
timer load operation. As with any interval timer, the delay
between the "write T1 C-H" operation and generation of the processor interrupt is a direct function of the data loaded into the
timing counter. In addition to generating a single interrupt,
Timer 1 can be programmed to produce a single negative pulse
on the PB7 peripheral pin. With the output enabled (ACR7 1)
a "write T1C-H" operation will cause PB7 to go low. PB7 will
return high when Timer 1 times out. The result is a single programmable width pulse.
=
Timing for the R6522 interval timer one-shot modes is shown
in Figure 15.
In the one-shot mode, writing into the T1l-H has no effect on
the operation of Timer 1. However, it will be necessary to assure
112
I I
~::::I
PB7 OUTPUT
T1 COUNTER
//
If'
I
I
N
I
N-1
I
N-2
I
l - - - - N + 1.5
Figure 15.
N-3
I
//
o
FFFF
CYCLES------~._ll
Timer 1 One-Shot Mode Timing
2-37
N
N-1
I
N-2
I
Versatile Interface Adapter (VIA)
R6522
Timer 1 Free-Run Mode
the time-out can be prevented completely if the processor continues to rewrite the timer before it reaches zero. Timer 1 will
operate in this manner if the processor writes into the high order
counter (T1C-H). However, by loading the latches only, the
processor can access the timer during each down-counting operation without affecting the time-out in process. Instead, the data
loaded into the latches will determine the length of the next timeout period. This capability is particularly valuable in the freerunning mode with the output enabled. In this mode, the signal
on PB7 is inverted and the interrupt flag is set with each timeout. By responding to the interrupts with new data for the latches,
the processor can determine the period of the next half cycle
during each half cycle of the output Signal on PB7. In this manner,
very complex waveforms can be generated.
The most important advantage associated with the latches in Tl
is the ability to produce a continuous series of evenly spaced
interrupts and the ability to produce a square wave on PB7 whose
frequency is not affected by variations in the processor interrupt
response time. This is accomplished in the "free-running" mode.
In the free-running mode, the interrupt flag is set and the signal
on PB7 is inverted each time the counter reaches zero at which
time the timer automatically transfers the contents of the latch
into the counter (16 bits) and continues to decrement from there.
The interrupt flag can be cleared by writing T1C-H or T1L-H, by
reading T1C-L, or by writing directly into the flag as described
later. However, it is not necessary to rewrite the timer to enable
setting the interrupt flag on the next time-out.
A precaution to take in the use of PB7 as the timer output concerns the Data Direction Register contents for PB7. Both DDRB
bit 7 and ACR bit 7 must be 1 for PB7 to function as the timer
output. If one is 1 and other is 0, then PB7 functions as a normal outpin pin, controlled by ORB bit 7.
All interval timers in the R6522 are "re-triggerable". Rewriting
the counter will always re-initialize the time-out period. In fact,
\12 .JL.J!.---ll...~;-ILJI.....fLJL
rl
WRITE T1C-H
OPERATION - - - - '
IRQ OUTPUT
PB70UTPUT
~f-
I (/
I
I
~/
I---
II
IL..-_ __
;'/
N + 1.5 CYCLES
Figure 16.
I
-----1.-------------'-----
.1.
N + 2 CYCLES
.1
Timer 1 Free-Run Mode Timing
Timer 2 Operation
decrementing again through zero. The processor must rewrite
12C-H to enable setting of the interrupt flag. The interrupt flag
is cleared by reading 12C-L or by writing 12C-H. Timing for this
operation is shown in Figure 18.
Timer 2 operates as an interval timer (in the "one-shot" mode
only), or as a counter for counting negative pulses on the PB6
peripheral pin. A single control bit in the Auxiliary Control Register
selects between these two modes. This timer is comprised of
a "write-only" lower-order latch (T2L-L), a "read-only" low-order
counter (T2C-L) and a readlwrite high order counter (T2C-H). The
counter registers act as a 16-bit counter which decrements at
02 rate. Figure 17 illustrates the 12 Latch/Counter Registers.
Timer 2 Pulse Counting Mode
In the pulse counting mode, 12 counts a predetermined number of negative-going pulses on PB6. This is accomplished by
first loading a number into 12. Writing into 12C-H clears the interrupt flag and allows the counter to decrement each time a pulse
is applied to PB6. The interrupt flag is set when 12 counts down
past zero. The counter will then continue to decrement with each
pulse on PB6. However, it is necessary to rewrite 12C-H to allow
the interrupt flag to set on a subsequent time-out. Timing for this
mode is shown in Figure 19. The pulse must be low on the leading edge of 02.
Timer 2 One-Shot Mode
As an interval timer, 12 operates in the "one-shot" mode similar
to Timer 1. In this mode, 12 provides a single interrupt for each
"write 12C-H" operation. After timing out, the counter will continue to decrement. However, setting of the interrupt flag is disabled after initial time-out 50 that it will not be set by the counter
2-38
Versatile Interface Adapter (VIA)
R6522
REG 9-TIMER 2 HIGH-ORDER LATCH/COUNTER
REG a-TIMER 2 LOW-ORDER LATCH/COUNTER
1'1'1+1 31'1 ,11
I,' "5'4'3",,101
0
c;
~-
512
'---4
,
16
1024
COUNT
VALUE
4096
32
WRITE -
READ -
COUNT
VALUE
2048
8192
64
16384
128
32768
8 BITS LOADED INTO T2l0W ORDER
WRITE -
881TS LOADED INTO T1 tllGH ORDER
LATCH
COUNTER ALSO, L.OWORDER LATCH
B BITS FROM 12 LOW OROER COUNTER
TRANSFERRED TO LOW ORDER
COUNTER. IN ADDITION, 12 INTERRUPT
TRANSFERRED TO MPU T2INTERAUPT
FLAG IS RESET.
flAG IS RESET.
READ-
a BITS FROM T2 HIGH·ORDER COUNTER
TRANSFERRED TO MPU.
Figure 17_ Timer 2 (T2) Latch/Counter Registers
WRITE T2C-H
~-----------------------i}j~'-------------+----------------------/
IRQ OUTPUT
N
N-l
I
N-2
I
N-3
I
o
I
N-l
I
N-2
I
N-3
1 - - - - - - - N + 1.5 CYCLES - - - - - - J
Figure 18. Timer 2 One-Shot Mode Timing
WRITE T2C-H
OPERATION
---Jr :
I~
_________________________________________________
;'t--------,W r - - - - 1W . - - -
PB61NPUT
IRQ OUTPUT
N
N-l
N-2
II
Figure 19. Timer 2 Pulse Counting Mode
2-39
o
-1
I
Versatile Interface Adapter (VIA)
R6522
SHIFT REGISTER OPERATION
of this output clock is a function of the system clock period and
the contents of the low order T2 latch (N).
The Shift Register (SR) performs serial data transfers into and
out of the CB2 pin under control of an internal modulo-a counter.
Serial data transfer in and out of the Shift Register (SR) begin
with the most significant bit (MSB) first. Shift pulses can be
applied to the CB1 pin from an external source or, with the proper
mode selection, shift pulses generated internally will appear on
the CB1 pin for controlling external devices.
The shifting operation is triggered by the read or write of the SR
if the SR flag is set in the IFA. Otherwise the first shift will occur
at the next time-out of T2 after a read or write of the SA. The
input data should change before the positive-going edge of CB1
clock pulse. This data is shifted into the shift register during the
02 clock cycle following the positive-going edge of the CB1 clock
pulse. The minimum CB1 positive pulse width must be one clock
period. After ~B1 clock pulses, the shift register interrupt flag
will set and IRQ will go low.
The control bits which select the various shift register operating
modes are located in the Auxiliary Control Register. Figure 20
illustrates the configuration of the SR data bits and Figure 21
shows the SR control bits of the ACA.
SR Mode 0 -
SR Mode 2 -
Shift Register Interrupt Disabled
Shift In Under 02 Control
In mode 2, the shift rate is a direct function of the system clock
frequency (Figure 23). CB1 becomes an output which generates
shift pulses for controlling external devices. Timer 2 operates
as an independent interval timer and has no effect on SR. The
shifting operation is triggered by reading or writing the Shift
Register. Data is shifted, first into bit 0 and is then shifted into
the next higher order bit of the shift register on the trailing edge
of each 02 clock pulse. After a clock pulses, the shift register
interrupt flag will be set, and the output clock pulses on CB1
will stop.
Mode 0 disables the Shift Register interrupt. In this mode the
microprocessor can write or read the SR and the SR will shift
on each CB1 positive edge shifting in the value on CB2. In this
mode the SR interrupt Flag is disabled (held to a logic 0).
SR Mode 1 - Shift In Under Control of 12
In mode 1, the shifting rate is controlled by the low order a bits
of T2 (Figure 22). Shift pulses are generated on the CB1 pin to
control shifting in external devices. The time between transitions
REG 11-AUXILIARY CONTROL REGISTER
REG 10-SHIFT REGISTER
171-~15~14~[t[k
l:==
1 1-101 1+1,101
J..LL
7
L
SHIFT REGISTER
MODE CONTROL
SHIFT
REGISTER
BITS
4
0
0
0
0
3
2
,,
,
,
,
,,
,,,
NOTES
1. WHEN SHIFTING OUT. BIT 7!S THE FIRST BIT
?~TTOAB~~ ~.IMUL TANEOUSl Y IS ROTATED BACK
1
0
0
0
0
0
0
1
0
0
2. WHEN SHIFTING IN, BITS INITIALLY ENTER
BIT 0 AND ARE SHiFTED TOWARDS BIT 7.
Figure 20.
4
Shift Register
OPERATION
DISABLED
SHIFT IN UNDER CONTROL OF 12
SHIFT IN UNDER CONTROL OF 'I'
SHIFT IN UNDER CONTROL OF EXT eLK
SHIFT OUT FREE RUNNING AT 12 RATE
SHIFT OUT UNDER CONTROL OF T2
SHIFT OUT UNDER CONTROL OF '1'2
SHIFT OUT UNDER CONTROL OF EXT elK
Figure 21.
Shift Register Modes
",2
WRITE OR READ
SHIFT REG
IRQ ____
~r-----------------------------------------~
Figure 22.
SR Mode 1 -
Shift In Under T2 Control
2-40
R6522
SR Mode 3 -
Versatile Interface Adapter (VIA)
Shift In Under CB1 Control
the shifting operation (Figure 25). Since the Shift Register bit 7
(SR?) is recirculated back into bit 0, the 8 bits loaded into the
shift register will be clocked onto CB2 repetitively. In this mode
the shift register counter is disabled.
In mode 3, external pin CSI becomes an input (Figure 24). This
allows an external device to load the shift register at its own pace.
The shift register counter will interrupt the processor each time
8 bits have been shifted in. The shift register stops after 8 counts
and must be reset to start again. Reading or writing the Shift
Register resets the Interrupt Flag and initializes the SR counter
to count another 8 pulses.
SR Mode 5 -
Note that the data is shifted during the first system clock cycle
following the positive-going edge of the CSI shift pulse. For this
reason, data must be held stable during the first full cycle following CSI going high. The minimum CSI positive pulse width
must be one clock period.
SR Mode 4 -
Shift Out Under T2 Control
In mode 5, the shift rate is controlled by T2 (as in mode I). The
shifting operation is triggered by the read or write of the SR if
the SR flag is set in the IFR (Figure 26)_ Otherwise the first shift
will occur at the next time-out of T2 after a read or write of the
SA. However, with each read or write of the shift register the SR
Counter is reset and 8 bits are shifted onto CS2. At the same
time, 8 shift pulses are generated on CSt to control shifting in
external devices. After the 8 shift pulses, the shifting is disabled,
the SR Interrupt Flag is set and CS2 remains at the last
data level.
Shift Out Under T2 Control (Free-Run)
Mode 4 is very similar to mode I in which the shifting rate is
set by T2. However, in mode 4 the SR Counter does not stop
~I_________________
IRQ
Figure 23_
SR Mode 2 -
Shift In Under \!l2 Control
CB2INPUT~~~~CJC:~~~J2L:~~~J3L:~~~J[~~/;iI~~ ~
DATA
:
~
I
L
Figure 24.
112
WRITE SR
CBt OUTPUT
SHIFT CLOCK
I
SR Mode 3 - Shift In Under CSI Control
I
I I
I
I
I
~'-+-""""'I---t:-;-:-;;I-""""'--+-+--I--+--+I--'
__
-:-'t=!
~N~+":2~C:Y~C:L:E~S~-.
-
Figure 25.
SR Mode 4 -
I
I
H -8 1--------1' -9 r-'L!..J
L!...J
Shift Out Under T2 Control (Free-Run)
2-41
R6522
Versatile Interface Adapter (VIA)
SR Mode 6 - Shift Out Under $2 Control
Interrupt Flag each time it counts 8 pulses but it does not disable the shifting function. Each time the microprocessor, writes
or reads the shift register, the SR Interrupt Flag is reset and the
SR counter is initialized to begin counting the next 8 shift pulses
on pin CB1. After 8 shift pulses, the Interrupt Flag is set. The
microprocessor can then load the shift register with the next byte
of data.
In mode 6, the shift rate is controlled by the 02 system clock
(Figure 27).
SR Mode 7 -
Shift Out Under CB1 Control
In mode 7, shifting is controlled by pulses applied to the CB1
pin by an external device (Figure 28). The SR counter sets the SR
CiCy;C ULEiSs+}:-;: : =: : r---,
·:tI·;: :=·!NIN+ 2 iC~Y:ciC~tE S --r----tL--=-tl-8-~:.
--
1/)2
WRITE SR
---tl'22
CB10UTPUT
SHIFT CLOCK
I
1
2
CB2 OUTPUT ~,-*",.
DATA
!
1-1---->L.-...;.3........
I ,
L-.!.......J
3 It:=x--.:8~il----
__..:......-_~X\ __-=-2_.....JX
1
Figure 26.
SR Mode 5 -
Shift Out Under T2 Control
1Jl.J1.rLIl.JlJ
1/)2
oa,W::;; --.H I I I I I I I I
SHIFT CLOCK
CB20UTPUT
DATA
WI
~\_~~
8
~~-+--=----
1
Figure 27.
SR Mode 6 -
Shift Out Under 02 Control
h...n..nsuL
1/)2
WRITE SR
CB11NPUT
S:~7o~~~~~
DATA
___
~
L
1
2
,..----,-----.X
Figure 28.
r--'8
2-----t,1
8.-
i
1
SR Mode 7 -
Shift Out Under CB1 Control
2-42
a
Versatile Interface Adapter (VIA)
R6522
function: IRQ = IFRS x IERS + IFR5 x IER5 + IFR4 x IER4
+ IFR3 x IER3 + IFR2 x IER2 + IFRl x IERI + IFRO x
IERO.
INTERRUPT OPERATION
Controlling interrupts within the RS522 involves three principal
operations. These are flagging the interrupts, enabling interrupts
and signaling to the processor that an active interrupts exists
within the chip. Interrupt flags are set in the Interrupt Flag
Register (IFR) by conditions detected within the RS522 or on
inputs to the RS522. These flags normally remain set until the
interrupt has been serviced. To determine the source of an interrupt, the microprocessor must examine these flags in order, from
highest to lowest priority.
Note:
x = logic AND, + = Logic OR.
The IFR bit 7 is not a flag. Therefore, this bit is not directly cleared
by writing a logic 1 into it. It can only be cleared by clearing all
the flags in the register or by disabling all the active interrupts
as discussed in the next section.
Associated with each interrupt flag is an interrupt enable bit in
the Interrupt Enable Register (IER). This can be set or cleared
by the processor to enable interrupting the processor from the
corresponding interrupt flag. If an interrupt flag is set to a logic 1
by an interrupting condition, and the corresponding interrupt enable bit is set to a 1, the Interrupt Request Output (IRQ)
will go low. IRQ is an "open-collector" output which can be
"wire-OR'ed" with other devices in the system to interrupt the
processor.
Interrupt Enable Register (IER)
For each interrupt flag in IFR, there is a corresponding bit in the
Interrupt Enable Register (IER) (Figure 30). Individual bits in the
IER can be set or cleared to facilitate controlling individual interrupts without affecting others. This is accomplished by writing
to the (IER) after bit 7 set or cleared to, in turn, set or clear
selected enable bits. If bit 7 of the data placed on the system
data bus during this write operation is a 0, each 1 in bits Sthrough
o clears the corresponding bit in the Interrupt Enable Register.
For each zero in bits S through 0, the corresponding bit is
unaffected.
Interrupt Flag Register (IFR)
In the RS522, all the interrupt flags are contained in one register,
i.e., the IFR (Figure 29). In addition, bit 7 of this register will be
read as a logic 1 when an interrupt exists within the chip. This
allows very convenient polling of several devices within a system to locate the source of an interrupt.
Selected bits in the IER can be set by writing to the IER with
bit 7 in the data word set to a 1. In this case, each 1 in bits S
through 0 will set the corresponding bit. For each zero, the corresponding bit will be unaffected. This individual control of the
setting and clearing operations allows very convenient control
of the interrupts during system operation.
The Interrupt Flag Register (IFR) may be read directly by the processor. In addition, individual flag bits may be cleared by writing
a "1" into the appropriate bit of the IFR. When the proper chip
select and register signals are applied to the chip, the contents
of this register are placed on the data bus. Bit 7 indicates the
status of the IRQ output. This bit corresponds to the logic
In addition to setting and clearing IER bits, the contents of this
register can be read at any time. Bit7 will be read as a logiC 1,
however.
REG 13-INTERRUPT FLAG REGISTER
/1716151413121,101
t
SET BY
LCA2 CA2 ACTIVE EDGE
CA1- CAl ACTIVE EDGE
SHIFT REG
ca2
ca,
TIMER 2
~TIMER
1
COMPLETE 8 SHIFTS
CB2 ACTIVE EDGE
CBl ACTIVE EDGE
TIME·OUT Of T2
11s1s1-l+1+1
7
CLEARED BY
~~'""
READ OR WRITE
REG 1 (ORA)-
=~~~J~R~~ITE
READ OR WAITE
SHIFT REG
READ OR WRITe ORBREAD OR WRITE ORa
READ T2 LOW OR
WRITE T2 HIGH
TIME·aUT OF T1
ANV ENABLED
INTERRUPT
IRQ
REG 14-INTERRUPT ENABLE REGISTER
TIMER 2
READ 11 LOW OR
INTERRUPT
DISABLED
= INTERRUPT
ENABLED
'--------TlMER'
WRITE 11 HIGH
CLEAR ALL
INTERRUPTS
L----------SET/CLEAR
NOTES .
1. IF BIT 7 IS A "0", THEN EACH "'" IN BITS 0 - 6 DISABLES THE
CORRESPONDING INTERRUPT.
2. IF BIT 7 IS A ",", THEN EACH ", .. IN BITS 0 - 6 ENABLES THE
CORRESPONDING INTERRUPT.
3. IF A READ OF THIS REGISTER IS DONE, BIT 7 WILL BE "1" AND
ALL OTHER BITS WILL REFLECT THEIR ENABLE/DISABLE STATE.
• IF THE CA2/ca2 CONTROL IN THE PCR IS SELECTED AS
"INDEPENDENT" INTERRUPT INPUT, THEN READING OR
WRITING THE OUTPUT REGISTER ORA/ORB WILL NOT
CLEAR THE FLAG BIT. INSTEAD, THE BIT MUST BE
CLEARED BY WRITING INTO THE IFR, AS DESCRIBED
PREVIOUSLV
Figure 29.
o=
Interrupt Flag Register (IFR)
Figure 30.
2-43
Interrupt Enable Register (IER)
Versatile Interface Adapter (VIA)
R6522
PERIPHERAL INTERFACE CHARACTERISTICS
Min.
Max.
Unit
tr,t,
Rise and Fall Time for CAl, CB1, CA2 and CB2 Input Signals
-
1.0
~s
1eA2
Delay Time, Clock Negative Transition to CA2 Negative Transition (read handshake or
pulse mode)
-
1.0
~s
31a,31b
t RS ,
Delay Time, Clock Negative Transition to CA2 Positive Transition (pulse mode)
~s
31a
Delay Time, CAl Active Transition to CA2 Positive Transition (handshake mode)
-
1.0
tRS2
2.0
~s
31b
tWHS
Delay Time, Clock Positive Transition to CA2 or CB2 Negative Transition
(write handshake)
0.05
1.0
~s
31c,31d
0.20
1.5
~s
31c,31d
-
1.0
~s
31c
2.0
~s
31d
Symbol
Characteristic
tos
Delay Time, Peripheral Data Valid to CB2 Negative Transition
tRS3
Delay Time, Clock Positive Transition to CA2 or CB2 Positive Transition (pulse mode)
t RS'
Delay Time, CAlor CBI Active Transition to CA2 or CB2 Positive Transition
(handshake mode)
Figure
-
t2,
Delay Time Required from CA2 Output to CAl Active Transition (handshake mode)
400
31d
Setup Time, Peripheral Data Valid to CAlor CBI Active Transition (input latching)
300
-
ns
t'L
ns
31e
tAL
CAl, CBl Setup Prior to Transition to Arm Latch
300
-
ns
31e
tpDH
Peripheral Data Hold After CAl, CBI Transition
150
-
ns
31e
tSR,
Shift-Out Delay Time -
-
300
ns
311
tSR2
Shift-In Setup Time -
300
-
ns
31g
tSR3
External Shift Clock (CB1) Setup Time Relative to "'2 Trailing Edge
100
Tcv
ns
31g
tlPw
Pulse Width -
PB6 Input Pulse
2 x Tev
-
31i
t lCW
Pulse Width -
CBl Input Clock
2 x TCY
-
31h
'IPS
Pulse Spacing -
PB6 Input Pulse
2 x Tev
tiCS
Pulse Spacing -
CBl Input Pulse
2 x Tey
-
31h
Time from "'2 Falling Edge to CB2 Data Out
Time from CB2 Data In to "'2 Rising Edge
2-44
31i
Versatile Interface Adapter (VIA)
R6522
PERIPHERAL INTERFACE WAVEFORMS
READ IRA
OPERATION
fI
CA2
"DATA TAKEN"
Figure 31a. CA2 Timing for Read Handshake, Pulse Mode
READ IRA
OPERATION
/
{f----f'OV
O.BV
~
CA2
"DATA TAKEN"
;'
~
"DATA READY"
I,:'..!
>f
--------------------------------~i~----
tRS
20~.BVV
'
t_ ACTIVE
TRANSITION
Figure 31b. CA2 Timing for Read Handshake, Handshake Mode
WRITE ORA, ORB
OPERATION
CA2, CB2
"DATA READY"
PA,PB
PERIPHERAL
DATA
Figure 3le. CA2, CB2 Timing for Write Handshake, Pulse Mode
2-45
R6522
Versatile Interface Adapter (VIA)
WRITE ORA, ORB
OPERATION
CA2, CB2
"DATA READY"
PA,PB
PERIPHERAL
DATA
CAl, CBl
"DATA TAKEN"
------------------------------7fFigure 31d. CA2, CB2 Timing for Write Handshake, Handshake Mode
CAl, CBl
INPUT LATCHING
CONTROL
Figure 31e. Peripheral Data Input Latching Timing
CB2
SHIFT DATA
(OUTPUT)
CBl
SHIFT CLOCK
(INPUT OR
OUTPUT)
DELAY TIME MEASURED FROM THE FIRST "'.
FALLING EDGE AFTER CBl FALLING EDGE.
Figure 31f. Timing for Shift Out with Internal or External Shift Clocking
2·46
R6522
Versatile Interface Adapter (VIA)
CB2
SHIFT DATA
(INPUT)
CB1
SHIFT CLOCK
(INPUT OR
OUTPUT)
SET UP TIME MEASURED TO THE FIRST .2
RISING EDGE AFTER CB1 RISING EDGE.
Figure 31 g. Timing for Shift In with Internal or External Shift Clocking
CB1
SHIFT CLOCK
INPUT
O_.B_v_rtl+_2._0_V__ IICS
IICW _ _ _
Figure 31h. External Shift Clock Timing
PBS
PULSE COUNT
INPUT
o.svr
lo.~---tIPw---~~
\O.SV
l-_oIIPS
I
COUNTER T2
DECREMENTS
HERE
Figure 311.
Pulse Count Input Timing
2-47
_'~~,---
.I '
R6522
Versatile Interface Adapter (VIA)
BUS TIMING CHARACTERISTICS
Paranieter
Symbol
READ TIMING
Cycle Time
Address Set-Up Time
Address Hold Time
Peripheral Data Set-Up Time
Data Bus Delay TIme
Data Bus Hold Time
Tev
TACR
TeAR
TPCR
TCOR
1
10
0.5
10
~s
180
-
90
-
0
300
-
-
0
150
365
-
190
ns
ns
ns
ns
10
-
ns
-
-
THR
10
-
TCY
Tc
TAcw
TCAW
1
10
0.50
10
~
470
180
-
-
235
90
ns
ns
0
180
-
0
90
ns
-
-
ns
WRITE TIMING
Cycle Time
02 Pulse Width
Address Sel-Up Time
Address Hold Time
R/W Sel-Up Time
AIW Hold Time
Dala Bus Sel-Up Time
Dala Bus Hold Time
Peripheral Data Delay Time
Peripheral Data Delay Time
10 CMOS Levels
Twcw
Tcww
0
-
0
-
ns
Tocw
THW
Tcpw
200
10
-
90
10
-
ns
ns
-
1.0
-
0.5
~
TCMOS
-
2.0
-
1.0
P.s
Note: IR and tF = 10 10 30 ns.
2-48
-
-
R6522
Versatile Interface Adapter (VIA)
BUS TIMING WAVEFORMS
02
CLOCK
-----+--"
CHIP SELECTS,
RE..§ISTER SELECTS,
R/W
PERIPHERAL
DATA
DATA BUS
-----------<.
Read Timing Waveforms
\12
CLOCK
CHIP SELECTS,
REGISTER SELECTS
DATA
BUS
PERIPHERAL
DATA
2-49
Versatile Interface Adapter (VIA)
R6522
ABSOLUTE MAXIMUM RATINGS·
Symbol
Value
UnIt
Supply Voltage
Parameter
Vee
-0.3 to +7.0
Vdc
Input Voltage
VIN
-0.3 to +7.0
Vdc
Operating Temperature
Commercial
Industrial
TA
Oto+70
-40 to +85
·C
·C
Storage Temperature
TSTG
-55 to +150
·C
°NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
other sections of this document is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
OPERATING CONDITIONS
Parameter
Value
Symbol
Supply Voltage
Vee
Temperature Range
Commercial
TA
5V ±5%
O·C to 70·C
DC CHARACTERISTICS
(Vee
= 5.0 Vde
±5%, Vss
= 0, TA = TL to TH, unless otherwise noted)
Min.
Typ.3
Max.
Unit
VIH
2.4
-
Vee
V
Input Low Voltage
VIL
-0.3
0.4
V
liN
-
-
Inpu!j.eakage Current
RNV,RES,RSO, RS1,RS2.RS3.CS1,CS2,CA1,,2
±1
±2.5
p.A
VIN = OV to 5.25V
Vcc = OV
Input Leakage Current for Three-State Off
00-007
Input High Current
PAo-PA7. CA2, PBo-PB7, CB1, CBS
ITSI
-
±2
±10
p.A
VIN = 0.4V to 2.4V
Vee = 5.25V
IIH
-100
-200
-
p.A
VIN = 2.4V
Vee = 5.25V
Input Low Current
PAO-PA7, CA2, PBo-PB7, CB1, CB2
IlL
-
-0.9
-1.8
mA
VIL = 0.4V
Vee = 5.25V
Output High Voltage
All outputs
PBo-PB7. CB2 (Darlington Drive)
VOH
-
-
Output Low Voltage
VOL
Output High Current (Sourcing)
Logic
PBD-PB7, CB2 (Darlington Drlve)
10H
Parameter
Input High Voitage
Symbol
2.4
1.5
-
-
-100
-1.0
-1000
-2.5
-
Output Low Current (Sinking)
IOL
1.6
Output Leakage Current (Off State)
IRQ
IOFF
-
Power DIsSipation
Po
Input CapaCitance
R~,RES,RSO,RS1,RS2,RS3.CS1,CS2,
00-07, PAO-PA7, CA1, CA2, PBo-PB7
CB1, CB2
\J2lnput
CIN
Output Capacitance
COUT
-
V
V
0.4
V
-
-10
-
Vee = 4.75V
ILOAO = -100 p.A
ILOAO = -1.0 mA
Vec = 4.75V
ILOAO = 1.6 mA
p.A
mA
VOH = 2.4V
VOH = 1.5V
mA
VOL = O.4V
4
±10
~A
VOH = 2.4V
Vee = 5.25V
-
450
700
mW
-
-
7
pF
Vee = 5.0V
VIN = OV
-
-
10
20
pF
pF
1= 1 MHz
TA = '25°C
10
pF
-
Notas:
1. All units are direct current (DC) except lor capacitance.
2. Negative sign indicates outward current Ilow, positive indicates inward flow.
3. Typical values shown lor Vee = 5.0V and TA = 25°C.
2-50
-
Test Conditions
Versatile Interface Ad apter (VIA)
R6522
~ACKAGE
DIMENSIONS
40-PIN CERAMIC DIP
lQ!M lM!,LLIMETERS
INCHES
A
5~1~ MAX MIN
MAX
"~t;:
40
-PIN PLASTIC DIP
G
'?nj
-IIK
n
-1i-J
~~ ~~
B
14 86
1.980
2 020
C
254
419 0.585
0615
o
0.38
0.76
2.54
076
053
1 40 0 030
F
G
H
J
a
K
L
~
I"i"
I!L
~~~
0165
0.021
esc
a 055
O.l00BSC
178 0030 0070
2'~~
0.33 0.008
460
0"
051
4.19 0.100
1537 0.575
10"
00
1520020
"
0.013
0.165
0605
10"
0'l§2.,
~
M--l
DIM M~I~METEAS
A
MAX
2060
1372 1422 0540
3.55 SOB 0140
0560
0200
C
D
(..Q.
I..!:!.
J
K
L
M
N
2-51
MIN
2040
51 28
I.!.
INCHES
MAX
52.32
S
~.~~
2 54
~51 0014 0.020
B~
165
0.040 0060
O.100BSC
2160.065 0085
020
030 0008 0012
305 3560120 0140
15.24 esc
a 600 esc
r
100
0.51
1 02 0.020
r
10°
0040
R6532
'1'
R6532
RAM-I/O-Timer (RIOT)
Rockwell
DESCRIPTION
FEATURES
The R6532 RAM-I/O-Timer (RIOT) integrates random access
memory (RAM), parallel 1/0 data ports and timer functions into
a single peripheral device which operates in conjunction with
any CPU in the R6500 microprocessor family. It is comprised
of a 128 x 8 static RAM, two software-controlled, 8-bit bidirectional data ports allowing direct interfacing between the microcomputer and peripheral devices, a software programmable
interval timer, with interrupt, capable of timing in various intervals
from 1 to 262,144 clock periods, and a programmable edge-detect
circuit.
•
•
•
•
•
•
• 8 bit bidirectional data bus
• 6500/6800 bus compatible
• 1 MHz and 2 MHz parts available
• Single +5V power supply
VSS
AS
A4
A3
A2
Al
AO
PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7
PB7
PB6
PBS
PB4
Vee
ORDERING INFORMATION
L
Part Number: R6532-r __
Temperature Range:
Blank = O°C to + 70"C
E = -40"C to +85°C
Package:
C = Ceramic DIP
P = Plastic DIP
Frequency:
No Letter = 1 MHz
A
Document No. 29000042
=
128 x 8 static RAM
Two 8 bit bidirectional data ports
Programmable interval timer with interrupt capability
TTL & CMOS compatible peripheral lines
One port has direct transistor drive capability
Programmable edge-sensitive interrupt input
A6
RIOT Interface Signals
2-53
) PBO-PB7
R6532
RAM-I/O-Timer (RIOT)
Table 1. Address Decoding
RS
RJW
A4
A3
A2
A1
AD
Write RAM
Read RAM
0
0
0
-
-
-
-
-
-
-
Write Output Reg A
Read Output Reg A
1
1
0
-
1
-
-
0
0
0
0
0
0
Write DDRA
Read DDRA
1
1
0
1
-
-
0
0
0
0
1
1
Write Output Reg B
Read Output Reg B
1
1
0
1
1
1
0
0
1
1
0
1
-
0
0
Write DDRB
Read DDRB
-
0
0
1
1
1
1
Write Timer
+1T
+8T
+64T
+1024T
Read Timer
Read Interrupt Flag
Write Edge Detect Control
1
1
1
1
1
1
1
0
0
0
0
1
1
0
1
1
1
1
1
1
1
0
0
1
0
1
0
1
(c)
Operation
1
-
(a)
(a)
(a)
(a)
(a)
1
1
1
1
-
-
-
0
-
0
1
1
(b)
Notes:
- = Don't Care, ""I" = High level (;;'2.4V) , ""0" = Low level (';;0.4V)
(a) A3 = o to disable timer interrupt
A3= 1 to enable timer interrupt
(c) AO = 0 for negative edge·detect
AO = 1 for positive edge·detect
(b) AI = o to disable PA7 interrupt
AI = 1 to enable PA7 interrupt
Table 2.
Start
Address
$0
$1
$2
$3
$4
$4
$5
$5
$6
+
Register Addressing
Register/Function
Start
Address
DRA ('A' side data register)
DDRA ('A' side data direction register)
DRB ('B' side data register)
DDRB ('B' side data direction register)
Read timer (disable interrupt)
Write edge·detect control (negative edge·detect,
disable interrupt)
Read interrupt flag register (bit 7 = timer, bit 6 =
PA7 edge'detect) Clear PA7 flag
Write edge·detect control (positive edge·detect,
disable interrupt)
Write edge·detect control (negative edge·detect,
enable interrupt)
$7
$C
$14
$15
$16
$17
$IC
$10
$IE
$IF
2-54
+
Register/Function
Write edge-detect control (positive edge·detece,
enable interrupt)
Read timer (enable interrupt)
Write timer (divide by I, disable interrupt)
Write timer (divide by 8, disable interrupt)
Write timer (divide by 64, disable interrupt)
Write timer (divide by 1024, disable interrupt)
Write timer (divide by I, enable interrupt)
Write timer (divide by 8, enable interrupt)
Write timer (divide by 64, enable interrupt)
Write timer (divide by 1024, enable interrupt)
R6532
RAM-I/O-Timer (RIOT)
INTERNAL ORGANIZATION
The R6532 is divided into four basic sections, RAM, I/O, Timer,
and Interrupt Control. The RAM interfaces directly with the
microprocessor through the system data bus and address lines.
The I/O section consists of two 8-bit halves. Each half contains
a Data Direction Register (DDR) and a Data Register (DR).
Data is read directly from the data pins during any read operation. For any output pin, the data transferred into the processor
will be the same as that contained in the Data Register if the
voltage on the pin is allowed to go to 2.4V for a logic one. Note
that for input lines, the processor can write into the corresponding bit of the Data Register. This will not affect the polarity
on the pin until the corresponding bit of DORA is set to a logic
one to allow the VO line to act as an output.
RAM-128 BYTES (1024 BITS)
The 128 x 8 Read/Write Memory acts as a conventional static
RAM and can be accessed from the microprocessor by selecting
the chip (CS1 = high, CS2 = low) and by setting RS low.
Address lines AD through A6 then select the desired byte of
storage.
The operation of the Port B is exactly the same as the normal
I/O operation of the Port A. Each of the eight lines can each be
programmed to act as either an input or as an output by placing
a Dor a 1 into the Port B Data Direction register (DORB). In the
output mode, the voltage on a peripheral pin Is controlled by the
Port B Data Register (ORB).
I{O PORTS AND REGISTERS
The primary difference between Port A and the Port B is in the
operation of the output buffers which drive these pins. The Port
B output buffers a;e push· pull devices which are capable of
sourcing 3 ma at 1.5V. This allows these pins to directly drive
transistor switches. To assure that the microprocessor will read
proper data on a "Read Port B" operation, logic in the R6532
allows the microprocessor to read the Output Register instead
of reading the peripheral pin as on Port A.
The I/O Ports consist of eight lines which can be individually programmed to act as either an input or an output. A logic zero in
a bit of the Port A Data Direction Register (DORA) causes the
corresponding line of Port A to act as an input. A logic one
causes the corresponding Port A line to act as an output. The
voltage on any line programmed to be an output is determined
by the corresponding bit in the Port A Data Register (ORA).
PAD
DATA
DIRECTION
REGISTER
A
DATA
BUS
BUFFER
DO
PB7
DATA
REGISTER
A
DATA
REGISTER
B
ADDRESS
DECODER
07
PA7 PBO
AD
~
~
CHIP
SELECT
R/W
A6
RS
R6532 Block Diagram
2-55
INTERRUPT
CONTROL
DATA
DIRECTION
REGISTER
B
INTERVAL
TIMER
R6532
RAM-I/O-Timer (RIOT)
EDGE DETECTING WITH PA7
In addition to acting as a peripheral I/O line, the PA7 line can
be used as an edge-detecting input. In this mode, an active transition sets the internal interrupt flag (bit 6 of the Interrupt Flag
register). Setting the interrupt flag causes IRQ output to go low
if the PA7 interrupt has been enabled.
.
During system initialization, the interrupt flag may inadvertently
be set by an unexpected transition on the PA7. It is therefore
recommended that the interrupt flag be cleared before enabling
interrupting from PA7. To clear PA7 interrupt flag, simply read
the interrupt Flag Register.
Control of the PA7 edge detecting mode is accomplished by
writing to one of four addresses. In this operation, AD co~trols
the polarity of the active transition and A 1 acts to enable or disable interrupting of the processor. The data which is placed on
the Data Bus during this operation is discarded and has no
effect on the control of PA7.
The Timer section of the R6532 contains three basic parts: preliminary divide down register, programmable S-bit register and
interrupt logic.
INTERVAL TIMER
The Timer can be programmed to count up to 255 time intervals.
Each time interval can be either 1T, ST, 64T or 1D24T increments, where T is the system clock period. When a full count
is reached, an interrupt flag is set to logic "1". After the interrupt
flag is set the internal clock begins counting down at the system
clock rate to a maximum of -255T. Thus, after the interrupt flag
is set, a Read of the timer will tell how long since the flag was
set up to a maximum of 255T.
The PA7 interrupt flag is set on an active transition, even if the
pin is being used as a normal input or as a peripheral control
output. The flag is also set by an active transition if the PA7
interrupt is disabled. The reset signal (RES) disables the PA7
interrupt and enables negative (high-to-Iow) edge detection on
PA7. The PA7 edge detect logic can be set to detect either a
positive or negative transition and to either enable or disable
interrupt (IRQ) generation upon detection.
R/W
A3
AO
A1
DIVIDE
DOWN
INTERRUPT
CONTROL
D4
D2
DO
Basic Elements of Interval Timer
2-56
R6532
RAM-I/O-Timer (RIOT)
INTERVAL TIMER EXAMPLE
The 8-bit microprocessor data bus transfers data to and from
the Timer. If a count of 52 time intervals were to be counted,
the pattern 0 0 1 1 0 1 0 0 would be put on the data bus and
written into the divide by 1 Timer register.
Value read = 1 1 1 0 0 1 0 0
Complement = 0 0 0 1 1 0 1 1
ADD 1
= 0 0 0 1 1 1 0 0 =
= 0 0 0 1
SUB 1
At the same time that data is being written to the Timer, the
counting intervals of I, 8,64, 1024T are decoded from address
lines AO and AI. During a Read or Write Operation address line
A3 controls the interrupt enable, i.e., A3 = 1 enables IRQ,
A3 = 0 disables IRQ. When the time is read prior to the interrupt flag being set, the number of time intervals remaining will
be read, i.e., 51, 50, 49, etc.
Thus, to arrive at the total elapsed time, merely do a two's complement add to the original time written into the timer. Again,
assume time written as 0 0 1 1 0 1 0 0 (=52). With a divide
by 8, total time to interrupt is (52 x 8) + 1 = 417T. Total elapsed
time would be 416T + 27T = 443T, assuming the value read
after interrupt was 1 1 1 0 0 1 0 O.
The interrupt flag will be reset whenever the Timer is accessed
by a read or a write. However, the reading of the timer at the
same time the interrupt occurs will not reset the interrupt flag.
When the interrupt flags are read (07 for the timer, 06 for the
edge detect) data bus lines DO-OS go to O.
When the Timer has counted through 0 0 0 0 0 0 0 0 on the
next count time an interrupt will occur and the counter will read
1 1 1 1 1 1 1 1. After the interrupt flag is set, the timer register decrements at a divide by "1" rate of the system clock. If
the timer is read after the interrupt flag is set and a value of
1 1 1 0 0 1 0 0 is read, the time since interrupt is 27T. The
value read is in two's complement, but remember that interrupt
occurred on count number one. Therefore, we must subtract 1.
COUNTER CONTENTS
o
IN.'
r P'T'---I
N·2
0 1 1 =
28 Equals two's complement of register
27
When reading the timer after an interrupt, A3 should be low so
as to disable the TRO pin. This is done so as to avoid future
interrupts until after another Write timer operation.
I'
0
I 255
I 254 I
253 I
I
64
I
1Q11,lf811911i611lr;j1r:i1mT41l41l41m~
02 PULSE NUMBER -.J L-.J ' ..... ~" L-.J Lt rI·"Lt ~ L-.J 04 r' ~ I-J 0 4
L-.Ji LJ; LJ , ~
0
U
rJ;
0
~
WRITE TIMER
PRE-SCALE OUTPUT
9
7
8
9
0
.IlL_____________________________
P·T,· T,/2
---:fI. . __-1n. . ____. . .n . . __. . .ru
N·P·T, + T,/2
4
7),---------------------'
READTIMER------------------------'rl~----------
INTERRUPT FLAG (BIT
Notes:
Assume 52 Loaded into Timer with a divide by 8.
The Counter Contents and the Clock Pulse Numbers will coincide.
Prescale, P = 8.
Cycle Time, Tc = t fLsec (for 1 MHz)
Count, N = 52
Interval Time Example Waveforms
2-57
RAM-I/O-Timer (RIOT)
R6532
BUS AND PERIPHERAL TIMING WAVEFORMS
READ TIMING
ADDRESS
CS, AS, ETC
PERIPHERAL
DATA
DATA
BUS
=~--='-'-'I
- - - - - - - - - - - - - - - - - - 0.4V
WRITE TIMING
177'.===============777 2.' V
ADDRESS.
es, RS, ETC
r-----------------
2.4 V
RtW
I'-=''''-'----------T''''''"' = : - - -_
-_
-_
, ._-_-_-_-_-_-_-_-_
-_
-_
-_
-_
-_
- 0.4 V
V~·3~
~=------------- 2.4 V
PERIPHERAL
DATA
DATA
BUS
2-58
R6532
RAM-I/O-Timer (RIOT)
AC CHARACTERISTICS
R6532
(1 MHz)
Characteristic
Symbol
R6532A
(2 MHz)
Max
Unit
10
,..,s
240
-
ns
25
-
15
ns
-
90
-
ns
Min
Max
1
10
Clock Cycle Time
Tcvc
Clock Pulse Widlh
Tc
470
Rise & Fall Times
TR• TF
-
Address Set Up Time
TACR
180
Address Hold Time
TCAR
0
RIW Sel Up Time
Data Bus Delay Time
-
Min
0.5
READ TIMING
TWCR
180
-
90
-
TCCR
-
395
-
190
n
-
ns
10
,..,S
Data Bus Hold Time
THR
Peripheral Data Sel Up Time
TPCR
10
300
0
-
10
150
ns
ns
ns
WRITE TIMING
~2 Cycle Time
Tcvc
~2 Pulse Width
Tc
470
Address Set Up Time
TACW
180
1
10
-
0.5
240
-
ns
90
-
ns
Address Hold Time
TCAH
0
-
R/W Set Up Time
Twcw
180
-
90
R/W Hold Time
TcwH
0
-
0
Data Bus Set-Up Time
Tccw
300
-
150
-
Data Bus Hold Time
THw
10
-
10
-
Peripheral Data Delay Time
TcFW
-
1
Peripheral Data Delay Time CMOS
TCMOS
-
2
2-59
0
-
-
ns'
ns
ns
ns
ns
0.5
,..,s'
1
,..,s
R6532
RAM-I/O-Timer (RIOT)
MAXIMUM RATINGS*
Symbol
Value
Unit
Supply Voltage
Vee
-0.3 to +7.0
Vdc
Input Voltage
Y'N
-0.3 to +7.0
Vdc
Operating Temperature
Commercial
Industrial
TA
o to +70
-40 to +85
'C
'C
Storage Temperature
TSTG
-55 to + 150
'C
Parameter
"NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
other sections of this document is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
DC CHARACTERISTICS
(Vee
= 5.0
= TL to
±5%, TA
TH unless otherwise noted)
Parameter
Symbol
Input High Voltage
V,H
Min
Max
Unlt(')
2.4
Vee
V
Test Conditions
Input Low Voltage
V,L
0
0.4
V
Input Leakage C.!!!:rent:
AO-AS, RS, RIW, RES, \!2, CS1,CS2
liN
-
2.5
fJoA
V,N = 5.25V
Vee = OV
Input Leakage Current for Three-State Off
DO-D7
hsr
-
±10
JJ.A
Y'N = O.4V to 2.4V
Input High Current
PAO-PA7, PBO-PB7
I'H
fJoA
V,H = 2.4V
Input Low Current
PAO-PA7, PBO-PB7
I'L
rnA
Y'N = O.4V
Output High Voltage
PAO-PA7, PBO-PB7 (TTL drive), DO-D7
PBO-PB7 (other than TTL drive, e.g., Darlington)
VOH
Output Low Voltage
DO-D7
VOL
Output High Current (Sourcing)
PAO-PA7, PBO-PB7 (TTL drive), DO-D7
PBO-PB7 (other drive, e.g., Darlington)
10H
Output low Current (Sinking)
PAO-PA7, PBO-PB7
10L
-100
-
-
-1.6
2.4
1.5
-
-
0.4
V
Vee = 4.75V
ILOAD = -100 fJoA
ILOAD = 3 rnA
V
Vee = 4.75V
ILOAD = 1.S rnA
-100
-3.0
-
fJoA
rnA
VOH = 2.4V
VOH = 1.5V
1.S
-
rnA
VOL = 0.4V
30
10
pF
pF
Vee = 5.0V
Y'N = OV
f = 1 MHz
TA = 25'C
Input Capacitance
\!2
Other
C'N
-
Output Capacitance
COUT
-
10
pF
Po
-
1000
mW
Power Dissipation
CCLK
Notes:
1. All units are direct current (DC).
2. Negative sign indicates outward current flow, positive indicates inward flow.
2-60
TA = O·C
~PA~C;K~AG~E~~DI:M:EN=S=IO=N~--------=====-~RiAA~M.I/O.Timer
(RIOT)
S
R6532
4()'PIN CERAMIC DIP
[ D ]J]
·1
i:
:: -:ffi
H~~LD
.-l~ ,n
I~
A
N
-1
k:m
MILLIMETERS
M MIN
A
~
~
Q
:
~
M
N
MAX
50.29 51.31
INCHES-
MIN
MAX
1980
2020
O:6~
14.86 1562 0.585
2.54
4.19 0 100
0 165
038 0.53 0.015 0:021
0.16 1.40 0.030 0.055
254 BSe
0100 esc
0.76
1.78
0,20 0.33
2.54 4.19
14.60 15.37
0.030
0008
0.100
0.575
0"
10"
051
1.52 0.020
0"
ooTo
0.013
0.165
0605
10"
0060
4()'PIN PLASTIC DIP
~:::::::::~~:::::::~·1
MILLIMETERS
B
C
CIL~
~"~
,H/_ .IG~~F-J.D
~
K
INCHES
DIM MIN MAX MIN
A 51.28 52.32 2.040
M
J
2-61
o
F
G
H
J
13.72 1422 0.540
3.55 508 0.140
0.36 0.51 0.014
1.02 1.52 0.040
0.100
2.54 esc
, 65 2.16 0065
0.20 030 0008
305 3.56 0.120
15.24
0600
L .,.
K
M
N
051
esc
",.
r
102 0020
MAX
2.060
0.560
0.200
0020
0.060
BSC
0.085
0.D12
0.140
esc
100
0040
R6545/R6545E
'1'
Rockwell
R6545/R6545E
CRT Controller (CRTC)
DESCRIPTION
FEATURES
The R6545/R6545E CRT Controller (CRTC) interfaces an B-bit
microprocessor to CRT raster scan video displays, and adds an
advanced CRT controller to the established and expanding line
of R6500, R6500/* and R65COO microprocessor, microcomputer
and peripheral device products.
•
•
•
•
Compatible with B-bit microprocessors
3.7 MHz character clock operation (R6545E)
2.5 MHz character clock operation (R6545)
Refresh RAM may be configured in row/column or straight
binary addressing
The R6545 and R6545E devices differ only in the character clock
frequency (CClK) specifications. The maximum CClK frequency
is 2.5 MHz for the R6545 and 3.7 MHz for the R6545E. Throughout this document, the nomenclature R6545 applies to both
devices, unless specified otherwise.
•
•
•
•
•
Alphanumeric and limited graphics capability
Up and down scrolling by page, line, or character
Programmable vertical sync width
Fully programmable display (rows, columns, character matrix)
Video display RAM may be configured as part of microprocessor memory field or independently slaved to R6545
(Transparent Addressing)
Interlaced or non-interlaced scan
50/60 Hz refresh rate
Fully programmable cursor
Light pen register
Addresses refresh RAM to 16K characters
No external DMA required
Internal status register
40-pin ceramic or plastic DIP
Pin-compatible with MC6B45R
Single + 5 ± 5% Vdc power supply
The R6545 provides refresh memory addresses and character
generator row addresses which allow up to 16K characters with
32 scan lines per character to be addressed. A major advantage of the R6545 is that the refresh memory may be addressed
in either straight binary or by row/column.
•
•
•
•
•
•
•
•
•
•
Other functions in the R6545 include an internal cursor register
which generates a cursor output when its contents are equal
to the current refresh address. Programmable cursor start and
end registers allow a cursor of up to the full character scan in
height to be placed on any scan lines of the character. Variable
cursor display blink rates are provided. A light pen strobe input
allows capture of the current refresh address in an internal light
pen register. The refresh address lines are configured to provide direct dynamic memory refresh.
ORDERING INFORMATION
All timing for the video refresh memory signals is derived from
the character clock input (CClK). Shift register, latch, and mUltiplex control signals (when needed) are provided by external
high-speed timing. The mode control register allows noninterlaced video display modes at 50 or 60 Hz refresh rate. The
internal status register may be used to monitor the R6545
operation. The RES input allows the CRTC-generated field rate
to be dynamically-synchronized with line frequency jitter.
t
Part Number:
R6545 ___ _
operating Temperature (TL to T H)
No Letters = O·C to 70·C
E = - 40·C to 85·C
Package
P = 4D-Pin Plastic DIP
C = 40·Pin Ceramic DIP
J = 44-Pin Plastic Leaded Chip Carrier (PLCC)
-
-
Document No. 29001035
Data Sheet
2-62
Operating Frequency (Bus)
1 MHz
No Letter
A = 2 MHz
=
Character Clock Frequency (CCLK)
No Letter = 2.5 MHz
E = 3.7 MHz
Order No. 0135
Rev. 2, June 1987
CRT Controller (CRTC)
R6545/R6545E
~
I'"
VSYNC
HSYNC
Vss
RES
LPEN
CCO/MAO
CC1/MAl
CC2/MA2
CC3/MA3
CC4/MA4
CCS/MAS
CC6/MA6
Cr:T/MA7
CRO/MAS
CR1/MA9
CR2/MA10
CR3/MAll
CR4/MA12
CRS/MA13
DISPLAY ENABLE
CURSOR
Vee
C)
«
c..>c..>
:O:Oz
zz
(.)(,)a.w
_
;::
0 W
?: ?: 9__
:: ~
c..>c..>.Ja:>z>:ca:a:a:
~ou'v,
RAO
RAI
RA2
RA3
RA4/STB
DO
01
02
03
04
05
06
D7
CS
RS
CC2/MA2
CC3/MA3
CC4/MA4
o
PINI
INDICATOR
RA3
RA4/STB
DO
CCS/MAS
01
CC6/MA6
02
CC7/MA7
03
CRO/MA8
04
CR1/MA9
05
06
07
NC
CR2/MA10
CR3/MAll
N/C
02
R/W
CCLK
40·PIN DIP
44·PIN PLCC
R6545/R6545E Pin Configuration
2·63
CRT Controller (CRTC)
R6545/R6545E
INTERFACE SIGNAL DESCRIPTION
VIDEO INTERFACE
Figure 1 illustrates the interface between the CPU, the R6545,
and the video circuitry. Figure 2 shows typical timing waveforms
at the video interface.
vee
HSYNC (Horizontal Sync)
The HSYNC active-high output signal determines the start of
the horizontal raster line. It may drive a CRT monitor directly
or may be used for composite video generation. HSYNC time
position and width are fully programmable.
GND
VIDEO I/F
00-07 __..Jo.~r..L.---....a._ _• HSYNC
VSYNC
DISPLAY ENABLE
$2
CURSOR
LPEN
CCLK
CS
RES
RS
VSYNC (Vertical Sync)
Rm
The VSYNC active-high output signal determines the start of
the vertical frame. Like HSYNC, VSYNC may drive a CRT
monitor or composite video generation circuits. VSYNC time
position and width are both programmable.
MAG-MA13 RAG-RA4
REFRESH RAM AND CHARACTER ROM
Figure 1.
DISPLAY ENABLE (Display Enable)
The DISPLAY ENABLE active-high output signal indicates when
the R6545 is generating active display information. The number
of horizontal display characters per row and the number of
vertical display rows are both fully programmable and together
generate the DISPLAY ENABLE signal. DISPLAY ENABLE may
be delayed one character time by setting bit 4 of R8 to a 1.
R6545 Interface Diagram
CPU INTERFACE
$2 (Phase 2 Clock)
The Phase 2 (02) input clock triggers all data transfers between
the system processor (CPU) and the R6545. Since there is no
maximum limit to the allowable 02 clock time, it is not necessary for it to be a continuous clock. This capability permits the
R6545 to be easily interfaced to non-6500 compatible
microprocessors.
CURSOR (Cursor Coincidence)
The CURSOR active-high output signal indicates when the scan
coincides with the programmed cursor position. The cursor
position is programmable to any character in the address field.
Furthermore, within the character, the cursor may be programmed to be any block of scan lines, since the cursor start
scan line and end scan line are both programmable. The cursor output may be delayed by one character time by setting Bit 5
ofR8toa1.
RtW (ReadlWrite)
The Rm input signal generated by the processor controls the
direction of data transfers. A high on the Rm pin allows the
processor to read Ihe data supplied by the R6545, a low on the
Rm pin allows data on data lines DO-D7 to be written into
the R6545.
LPEN (Light Pen Strobe)
CS (Chip Select)
The LPEN edge-sensitive input signal loads the internal Light
Pen Register. A low-to-high transition activates LPEN.
The Chip Select input is normally connected to the processor
address bus either directly or through a decoder. The R6545
is selected when CS is low. Then, data may be written to, or
read from, the R6545 depending on the state of RS and Rm.
CCLK (Clock)
The CCLK character timing clock input signal is the time base
for all internal count/control functions.
RS (Register Select)
The Register Select input allows access to internal registers. A
low on this pin permits writing (Rm = low) into the Address
Register and reading (Rm = high) from the Status Register. The
Address Register selects the register accessed when RS is high.
The RES active-low input signal initializes all internal scan
counter circuits. When RES is low, all internal counters stop and
clear and all scan and video outputs go low; control registers
are unaffected. RES must stay low for at least one CCLK period.
All scan timing initiates when RES goes high. In this way, RES
can synchronize display frame timing with line frequency. RES
may also synchronize multiple CATC's in horizontal and/or
vertical split screen operation.
00-07 (Data Bus)
The eight data lines (DO-D7) transfer data between the processor and the R6545. These lines are bidirectional and are normally high-impedance except during read cycles when the chip
is selected (CS = lOw).
2-64
CRT Controller (CRTC)
R6545/R6545E
REFRESH RAM AND CHARACTER ROM
INTERFACE
become row address CRO-CR5. In this case, the software
manipulates characters in terms of row and column locations,
but additional address compression circuits are needed to convert the CCO-CC7 and CRO-CR5 addresses into a memoryefficient binary address scheme.
MAO-MA13 (Refresh RAM Address Lines)
These 14 active-high output signals address the refresh RAM
for charaC1er storage and display operations. The starting scan
address is fully programmable and the ending scan address is
determined by the total number of characters displayed, which
is also programmable, in terms of charaC1ersiline and lineslframe.
RAO-RA4 (Raster Address Lines)
These five active-high output signals select each raster scan
within an individual character row. The number of raster scan
lines is programmable and determines the character height, including spaces between character rows.
There are two selectable address modes for MAO-MA13:
In the straight binary mode (RS, Mode Control, bit 2 = 0),
characters are stored in successive memory locations. Thus, the
software design must translate row and column character coordinates into sequentially-numbered addresses for Refresh
memory operations.
The high-order line, RA4, is unique in that it can also function
as a strobe output pin when the R6545 is programmed to operate in the "Transparent Address Mode:' In this case the strobe
is an active-high output and is true at the time the Refresh RAM
updates address gates on to the address lines, MAO-MAl3. In
this way, updates and readouts of the Refresh RAM can be made
under control of the R6545 with only a small amount of external
circuitry.
In the row/column mode (RS, Mode Control, bit 2 = 1), MAOMA7 become column addresses CCO-CC7 and MAS-MA13
~__________________~1~C~O~M~P~L=E~TE~F=IE=L~D~(VE~R_T~IC~A_L_T_O~T_A~L~)---------------------l
VERTICAL DISPLAYED
I
DISPLAY
ENABLE
HSYNC
VSYNC
~---------------+--+---------------------~
CCLK
RAO-RA4
----~------------------------------------------------1~-Figure 2.
Vertical and Horizontal Timing
2-65
CRT Controller (CRTC)
R6545/R6545E
INTERNAL REGISTER DESCRIPTION
SR
7
Table 1 summarizes the internal registers and indicates their
address selection and read/write capabilities.
ADDRESS REGISTER
I~ I
6
I~ I
zI ~ I r I ~
o
SR
6
o
o
This 5-bit write-only register is used as a "pointer" to direct
CRTC/CPU data transfers within the CRTC. It contains the
number of the desired register (0-31). When RS is low, this
register may be loaded; when RS is high, the selected register
is the one whose identity is stored in this address register.
o
o
2
Notes:
0
!IT!
VAT -Vertical Re-Trace
Scan is not currently in the vertical re-trace time.
Scan is currently in its vertical re-trace time.
NOTE: This bit goes to a 1 when vertical re-trace
starts. It goes to a 0 five character clock times before
vertical re-trace ends to ensure that critical timings
for refresh RAM operations are met.
SR
4-0
This 3-bit register contains the status of the CRTC.
Table 1.
LRF -LPEN Register Full
Register R16 or R17 has been read by the CPU.
LPEN strobe has been received.
SR
~
STATUS REGISTER (SR)
3
UR
-Update Ready
Register R31 has been either read or written by the
CPU.
An update strobe has occurred.
-Not used.
Internal Register Summary
DeSignates used bit in register
Designates unused bit in register. Reading this bit is always 0, except for R31, which does not drive the data bus.
2-66
CRT Controller (CRTC)
R6545/R6545E
RO-HORIZONTAL TOTAL CHARACTERS
7
6
5
4
3
2
to the line frequency to ensure flicker-free appearance. If the
frame time is adjusted to be longer than the period of the line
frequency, then RES may provide absolute synchronism.
o
NUMBER OF CHARACTERS -1
RS-VERTICAL TOTAL LINE ADJUST
This B-bit write-only register contains the total of displayed and
non-displayed characters, minus one, per horizontal line. This
register determines the frequency of HSYNC.
4
6
5
4
3
2
The 5-bit write-only Vertical Total Line Adjust Register (R5) contains the number of additional scan lines needed to complete
an entire frame scan and is intended as a fine adjustment for
the video frame time.
o
NUMBER OF CHARACTERS
This B-bit write-only register contains the number of displayed
characters per horizontal line.
R6-VERTICAL DISPLAYED ROWS
6
5
R2-HORIZONTAL SYNC POSITION
7
6
5
4
3
2
o
6
3
o
2
RS-MODE CONTROL (MC)
o
2
RAD
IMC
This 8-bit write-only register selects the operating modes of the
R6545, as follows:
MC
HVSW
3-0 HSYNC Pulse Width
The width of the horizontal sync pulse (HSYNC)
expressed as the number of character clock times
(CClK). When bits 0-3 are all zero, HSYNC is 16 bit
times wide.
l
Control of these parameters allows the R6545 to interface with
a variety of CRT monitors, since the HSYNC and VSYNC timIng signals may be accommodated without the use of external
one shot timing.
...!...
o
UM(T)-Update/Read Mode (Transparent Mode)
Update occurs during horizontal and vertical blanking times with update strobe.
Update interleaves during 02 portion of cycle.
Me
o
1
MC
5
R4-VERTICAL TOTAL ROWS
2
4
This 7-bit write-only register selects the character row time at
which the vertical SYNC pulse occurs and, thus, positions the
displayed text in the vertical direction.
HVSW
7-4 VSYNC Pulse Width
The widlh of the vertical sync pulse (VSYNC)
expressed as the number of scan lines. When bits
4-7 are all 0, VSYNC is 16 scan lines wide.
3
5
VERTICAL POSITION
This 8-bit write-only register contains the widths of both HSYNC
and VSYNC as follows:
4
o
2
R7-VERTICAL SYNC POSITION
R3-HORIZONTAL AND VERTICAL SYNC WIDTHS
5
3
This 7-bit write-only register contains the number of displayed
character rows in each frame. This determines the vertical size
of the displayed text.
This B-bit write-only register contains the position of HSYNC on
the horizontal line, in terms of the character location number
on the line. The position of the HSYNC determines the left to
right location of the displayed text on the video screen. In this
way, the side margins are adjusted.
6
4
DISPLAYED CHAR. ROWS
HORIZONTAL SYNC POSITION
I~ I
o
2
SCAN LINES
R1-HORIZONTAL DISPLAYED CHARACTERS
7
3
o
o
1
US(T) -Update Strobe (Transparent Mode)
Pin 34 functions as memory address (RA4).
Pin 34 functions as update strobe (ST8).
CSK -Cursor Skew
No delay.
Delays Cursor one character time.
NO. OF CHAR. ROWS -1
MC
4
The 7-bit Vertical Total Register contains the total number of
character rows in a frame, minus one. This register, along with
R5, determines the overall frame rate, which should be close
o
1
2-67
DES -Display Enable Skew
No delay.
Display Enable delays one character time.
o
CRT Controller (CRTC)
R6545
MC
3
---01
MC
2
---01
These registers together form a 14-bit register whose contents
are the memory address of the first character to be displayed
(the character on the top left of the video display, as in Figure 4).
Subsequent memory addresses are generated by the R6545 as
a result of CCLK input pulses. Scrolling of the display is accomplished by changing R12 and R13 to the memory address of
the first character of the first line of text to be displayed. Entire
pages of text may be scrolled or changed as well via R12 and
R13.
RRA -Refresh RAM Access
Shared memory access
Transparent memory access
RAD -Refresh RAM Addressing Mode
Straight binary addressing
Row/column addressing
MC1-MCa IMC
-Interlace Mode Control
R14-CURSOR POSITION HIGH
MC
1
X
o
MC
a
o
1
1
1
5
Operation
Non-interlace
Interlace SYNC raster scan
Interlace SYNC and video raster scan
4
3
o
2
CURSOR POSITION HIGH
R15-CURSOR POSITION LOW
R9-ROW SCAN LINES
3
4
2
7
o
6
5
4
3
o
2
CURSOR POSITION LOW
SCAN LINES -1
These registers together form a 14-bit register whose contents
are the memory address of the current cursor position. When
the video display scan counter (MA lines) matches the contents
of this register, and when the scan line counter (RA lines) falls
within the bounds set by Rl0 and Rll, then the CURSOR output becomes active. Bn 5 of the Mode Control Register (R8) may
be used to delay the CURSOR output by a full CCLK time to
accommodate slow access memories.
This 5-bit write-only register contains the number of scan lines,
minus one, per character row, including spacing.
R10-CURSOR START LINE
3
4
2
o
START SCAN LINE
The cursor is positioned on the screen by loading the Cursor
Position Address High (R14) and Cursor Position Address Low
(R15) registers with the desired refresh RAM address. The cursor
can be positioned in any of the 16K character positions. Hardware paging and data scrolling is thus allowed without loss of
cursor position. Figure 3 is an example of several cursor options.
R11-CURSOR END LINE
4
3
2
o
END SCAN LINE
These 5-bit write-only registers select the starting and ending
scan lines for the cursor. In addition, bits 5 and 6 of Rl0 are
used to select the cursor blink mode, as follows:
8,
0
0
Bo
0
1
1
0
Cursor Operating Mode
Display Cursor Continuously
Blank Cursor
Blink cursor at 1116 Field Rate
Blink Cursor at 1/32 Field Rate
1
1
UNDERLINE
CURSOR
R12-DISPLAY START ADDRESS HIGH
4
3
2
CURSOR
,II ,!I .II
A one character wide cursor can be controlled by storing values
into the Cursor Start Line (Rl0) and Cursor End Line (Rll)
registers and into the Cursor Position Address High (R14) and
Cursor Position Low (R15) registers.
5
BOX
OVERLINE
CURSOR
o
DISPLAY START ADDRESS HIGH
11
11
11
CURSOR START
LINE = 9
CURSOR START
LINE = 1
CURSOR START
LINE
1
CURSOR END
LINE
9
CURSOR END
LINE = 1
CURSOR END
LINE = 9
=
=
R13-DISPLAY START ADDRESS LOW
7
6
5
4
3
2
o
DISPLAY START ADDRESS LOW
Figure 3.
2-68
Cursor Display Scan Line Control Examples
CRT Controller (CRTC)
R6545/R6545E
R16-LlGHT PEN HIGH
5
3
4
These registers together comprise a 14-bit register whose contents are the memory address at which the next read or update
will occur (for transparent address mode only). Whenever a
read/update occurs, the update location automatically increments to allow for fast updates or readouts of consecutive
character locations. The section on REFRESH RAM ADDRESSING describes this more fully.
o
2
LPEN HIGH
R17-LlGHT PEN LOW
7
s
5
3
4
o
2
R31-DUMMY LOCATION
LPEN LOW
3
These registers together form a 14-bit register whose contents
are the light pen strobe position, in terms of the video display
address at which the strobe occurred. When the LPEN input
changes from low to high, then, on the next negative-going edge
of CCLK, the contents of the internal scan counter is stored in
registers R16 and R17.
2
o
This register does not store any data, but is required to detect
transparent addressing updates. This is necessary to increment
the Update Address Register and to set the Update Ready bit
in the status register.
R18-UPDATE ADDRESS HIGH
5
4
3
REGISTER FORMATS
o
2
Register pairs R12/R13, R141R15, R16/R17, and R18JR19 are
formatted in one of two ways:
UPDATE ADDRESS HIGH
R19-UPDATE ADDRESS LOW
7
s
5
4
3
(1) Straight binary, if register RB, bit 2 = 0
(2) Row/Column, if register RB, bit 2 = 1. In this case the low
byte is the Character Column and the high byte is the
Character Row.
o
2
UPDATE ADDRESS LOW
,
NUMBER OF HORIZONTAL TOTAL CHARACTERS (RO+l)
A
,
NUMBER OF HORIZONTAL DISPLAYED CHARACTERS (Rt)
,
"
' / DISPLAY START ADDRESS HIGH (Rt2)
DISPLAY START ADDRESS LOW (Rt3)
...
~
I NUMBER OF
SCAN LINES (RS)
~
CURSOR START LINE (RtO)
rCURSOR END LINE (Rtt)
"-
NUMBER OF
VERTICAL
TOTAL
ROWS
(R4+t)
NUMBER OF
VERTICAL
DISPLAY
ROWS
(RS)
CURSOR POSITION ADDRESS HIGH (Rt4)
CURSOR POSITION ADDRESS LOW (Rt5)
DISPLAY PERIOD
VERTICAL RETRACE PERIOD
(NON-DISPLAY)
VERTICAL
{
TOTAL
ADJUST (RS)
Figure 4.
Video Display Format
2-69
HORIZONTAL
RETRACE
PERIOD
(NON-DISPLAY)
D
R6545
CRT Controller (CRTC)
= 0)
DESCRIPTION OF OPERATION
Shared Memory Mode (RS, BIT 3
VIDEO DISPLAY
In this mode, the Refresh RAM address lines (MAO-MA 13)
directly reflect the contents of the internal refresh scan character counter. Multiplex control, to permit addressing and selection of the RAM by both the CPU and the CRTC, must be
provided externally to the CRTC. In the Row/Column address
mode, lines MAO-MA7 become character column addresses
(CCO-CCl) and MA8-MA13 become character row addresses
(CRO-CR5). Figure 5 illustrates the system configuration.
Figure 4 indicates the relationship of the various program registers in the R6545 and the resulant video display.
Non-displayed areas of the Video Display are for horizontal and
vertical retrace functions of the CRT monitor. The horizontal and
vertical sync signals, HSYNC and VSYNC, are programmed to
occur during these intervals and trigger the retrace in the CRT
monitor. The pulse widths are constrained by the monitor requirements. The time position of the pulses may be adjusted to vary
the display margins (left, right, top, and bottom).
Transparent Memory Addressing (RS, BIT 3
REFRESH RAM ADDRESSING
There are two modes of addressing for the video display memory:
SYSTEM
BUS
VSYNC
HSYNC
R6545
DISPLAY ENABLE
CRT CONTROLLER
TO
VIDEO
CIRCUITS
CURSOR
RAO-RA4
CPU
SCAN UNE
COUNT
SHIFT
REGISTER
1==::e=~>1~~:::i~=
CHARACTER
DATA
Figur~
5.
ROM
SCAN UNE
DOT PATTERN
Shared Memory System Configuration
SYSTEM
BUS
R&S45
CRT CONTROLLER
RA4
CPU
MAO-MA13
UPDATE
STROBE
RAO-RA3
DISPLAY/UPDATE
ADDRESS
SCAN UHE
COUNT
CHARACTER
GENERATO
ROM
CHARACTER
DATA
Figure 6.
= 1)
For this mode, the display RAM is not directly accessible by the
CPU, but is controlled entirely by the R6545. All CPU accesses
are made via the R6545 and a small amount of external circuitry. Figure 6 shows the system configuration for this approach.
CHARACTER
DATA
Transparent Memory Addressing System Configuration
(Data Hold Latch Needed for HorizontallVertical Blanking Updates, Only).
2-70
R6545/R6545E
CRT Controller (CRTC)
ADDRESSING MODES
viable technique, since the Display Enable signal controls the
actual video display blanking. Figure 7 illustrates Refresh RAM
addressing for both row/column and binary addressing for
SO columns and 24 rows with 10 non-displayed columns and 10
non·displayed rows.
Figure 7 illustrates the address sequence for both modes of the
Refresh RAM address.
Row/Column
Note that the straight-binary mode has the advantage that all
display memory addresses are stored in a continuous memory
block, starting with address 0 and ending at 1919. The disadvantage with this method is that, if it is desired to change a
displayed character location, the row and column identity of the
location must be converted to its binary address before the
memory may be written. The row/column mode, on the other
hand, does not need to undergo this conversion. However,
memory is not used as efficiently, since the memory addresses
are not continuous, gaps exist. This requires that the system
be equipped with more memory than actually used and this extra
memory is wasted. Alternatively, address compression logic may
be employed to translate the row/column format into a continuous address block.
In this mode, the CRTC address lines (MAO-MA13) generate
B column (MAO-MA7) and 6 row (MAB-MA13) addresses. Extra
hardware is needed to compress this addressing into a straight
binary sequence in order to conserve memory in the refresh RAM
(register RS, bit 2 is a 1).
Binary
In this mode, the CRTC address lines are straight binary and
no compression circuits are needed. However, software complexity increases since the CRT characters cannot be stored in
terms of their row and column locations, but must be sequential (register RS, bit 2 is a 0).
USE OF DYNAMIC RAM FOR REFRESH MEMORY
The user selects whichever mode is best for the given application. The trade-offs between the modes are software versus hardware. Straight-binary mode minimizes hardware requirements
and row/column minimizes software requirements.
The R6545 permits use of dynamic RAMS as storage devices
for the Refresh RAM by continuing to increment memory
addresses in the non-display intervals of the scan. This is a
rl------
I
_~I,
1
I
~
DISPLAY
,86000
,8 ',
6
'2
82
rl- - - - - - TOTAL
TOTAL
77
78
79
80
157158159160
162 - - - - - - 137
238
239
240
81 _ ••
161 ___
I
I~
I c:; 1
89
169
~:;:
241 - - - 249
I/:p
i
1-[L
C
1161 1762 - - - --- 1837 18381839 1840 1841 -
I
COLUMN ADDRESS (MAO-MA7J - - - ,
~ ~ ~
g 17~O
= 90 - - - - - - . . . ,
Ir---- DISPLAY =80 - - - - - - - ,
------...,
= 80 ~
_0--------
= 90
2
:
10
a
,
256
251
-
- - - -
n
n
~180 ~
77
78
7'
258 - - - - - - 333 334
8D
8'
001
- --
8.
335 336 JJ7 . - - 345
51" 513 514 -~- --- 589 590 591
59~
593···601
I
: 1-':+---1-+-,-l-+---1f-'-+-4-+-+--'-l
j ~l i :; 56~2
1849
2
5633 5634 - - - - -- 5709 5710 5711 5712 5713 - - - 5721
1840 18411842 ______ 19111918191919201921- __ 1929
... ~" -.E
1920 1921 1922 - - - - - - 1997 1998 1999 2000 ::'001 - - - 2009
~
24 61446145 6146 - - - - - - 6:?21 622" 6223 6224 6225 • - - 6233
a:
2S 6400 6401 6402 - - - - - - 6477 6478 6479 6480 6481 . - - 6489
0-
LI
:1000 2001 1002 - - - - - - 2017 2078 2079 :m80 2081 - - - 2089
.,
"
"
26402641 2642 - - - - - - 2711 271a 2719 27202721 -
OM
~
2729
STRAtGHT BINARY ADDRESSING SEQUENCE
Figure 7.
5888 5889 5890 _ •. - _. 5965 5966 5967 5968 5969 •. - 5977
:
::
8448 8449 8450 - - - - - - 8525 8526 8527 8528 8529 - - - 8537
ROW/COLUMN ADDRESSING SEQUENCE
Display Address Sequences (with Start Address=O) for 80 x 24 Example
2-71
II
R6545/R6545E
CRT Controller (CRTC)
MEMORY CONTENTION SCHEMES FOR
SHARED MEMORY ADDRESSING
TRANSPARENT MEMORY ADDRESSING
In this mode of operation, the video display memory address
lines are not switched by contention circuits, but are generated
by the R6545. In effect, the contention is handled by the R6545.
As a result, the schemes for accomplishing CPU memory access
are different:
From the diagram of Figure 5, it is clear that both the R6545
and the system CPU must address the video display memory.
The R6545 repetitively fetches character information to generate
the video signals in order to keep the screen display active. The
CPU occasionally accesses the memory to change the displayed
information or to read out current data characters. Three ways
of resolving this dual-contention requirement are apparent:
•
• .1 and .2 Interleaving
This mode is similar to the Interleave mode used with shared
memory. In this case, however, the 02 address is generated
from the Update Address Register (R18 and R19) in the
R6545. The CPU loads the address to be accessed into
R18/R19. This address is then gated onto the MA lines during
02. Figure 9 shows the timing.
CPU Priority
In this technique, the address lines to the video display memory are normally driven by the R6545 unless the CPU needs
access, in which case the CPU addresses immediately override those from the R6545 giving the CPU immediate access.
· .1 .2
and
Memory Interleaving
This method permits both the R6545 and the CPU to access
the video display memory by time-sharing. During the 01 portion of each cycle (the time when 02 is low), the R6545
address outputs are gated to the video display memory. During 02 time, the CPU address lines are switched in. This way,
both the R6545 and the CPU have unimpeded access to the
memory. Figure 8 illustrates these timings.
e.
CLOCK
MAO ...MA13
Figure 9.
02
.1 and
.2
Transparent Interleaving
CLOCK
• HorizontalNertical Blanking
VIDEO
DISPLAV
MEMORV
ADDRESSES
Figure 8.
In this mode, the CPU loads the Update Address into R18
and R19. This address is gated onto the MA lines during
horizontal or vertical blank times, so memory accesses do
not interfere with the display appearance. Pin 34 can be programmed, by R8 bit 6, to function as an update strobe which
signals the presence of an update address on the MA lines.
Data hold latches are necessary to temporarily retain the
character to be stored until the retrace time occurs. In this
way, the system CPU is not halted waiting for the blanking
time to arrive. Figure 11 illustrates the address and strobe
timing for this mode.
.1 and 02 Interleaving
• Vertical Blanking
With this approach, the address circuitry is identical to the
case for CPU Priority updates. The only difference is that the
Vertical Retrace status bit (bit 5 of the Status Register) is used
by the CPU so that access to the video display memory is
only made during vertical blanking time (when bit 5 is a 1).
In this way, no visible screen perturbations result. See
Figure 10 for details.
CURSOR AND DISPLAY ENABLE SKEW CONTROL
Bits 4 and 5 of the Mode Control register (R8) are used to delay
the Display Enable and Cursor outputs, respectively. Figure 12
illustrates the effect of the delays.
2-72
R6545/R6545E
.
CRT Controller (CRTC)
FRAME
.
VERTICAL DISPLAYED
FRAME
VERTICAL
BLANKING
DISPLAY
ENABLE
VERTICAL
BLANKING
STATUS
BIT
--,
(STATUS
"0"
DISPLAY
ACTIVE
REGISTER
L-_ _
_=
_
___
____
I
~
\
BIT 5)
SWITCHES STATE AT
END OF LAST DISPLAYED
SCAN LINE.
Figure 10.
, - - I_
_- - - - '
"I" = VERTICAL
BLANKING
ACTIVE
Operation of Vertical Blanking Status Bit
2-73
CRT Controller (CRTC)
R6545/R6545E
CCLK
-+---r--- I HORIZONTAUVERTICAL BLANKING - - -
f*'
DISPLAY'
DISPlAY
ENABLE
CRT DISPLAY
~~
:
'I
I
I
I
I
:
:
:
'I'
\'
I
::~; ~ ~~~R~;~
I
I
UPSTB
I
I
:
I
n
,
NON·DISPLAY
IJ
'tX,I=x
I
I
---------------------+:---J1
I~--_r---------------------------------------
Figure 11.
Retrace Update Timing
CCLK
,"~,{
(NO DELAY)
{
,,~, {
(WITH DELAY)
,,~,
(NO DELAY)
ENABLE
POSITIVE
EDGE
(WITH DELAY)
(NO DELAY)
ENABLE
NEGATIVE
EDGE
(WITH DELAY)
Figure 12.
~~~~
Cursor and Display Enable Skew
2·74
CRT Controller (CRTC)
R6545/R6545E
BUS WRITE TIMING CHARACTERISTICS (Vee =
5.DV
± 5%, TA = TL to T H , unless otherwise noted)
2 MHz
1 MHz
Symbol
Characteristic
Min.
Max.
Min.
Max.
-
0.5
200
Unit
tCl
02 Pulse Width Low
420
-
190
t ACW
Address Set-Up Time
80
-
40
-
tCAH
Address Hold Time
0
-
0
-
ns
t wcw
RIW Set-Up Time
80
40
-
ns
tCWH
RIW Hold Time
0
0
ns
t DCW
Data Bus Set-Up Time
165
-
-
60
ns
tHW
Data Bus Hold Time
10
-
10
-
tCYC
Cycle Time
1.0
tCH
02 Pulse Width High
440
-
~s
ns
ns
ns
ns
(tA and tF = 10 to 30 ns)
BUS READ TIMING CHARACTERISTICS
(Vee = 5.DV
± 5%, TA = TL to T H, unless otherwise noted)
1 MHz
Symbol
Characteristic
2 MHz
Mln_
Max.
Min_
Max.
-
0.5
-
200
ns
40
-
tCYC
Cycle Time
1.0
tCH
02 Pulse Width
440
Unit
~s
tCl
02 Pulse Width Low
420
t ACA
Address Set-Up Time
80
tCAA
Address Hold Time
0
t WCA
RIW Set-Up Time
80
-
tCDA
Read Access Time (Valid Data)
-
290
-
150
ns
tHR
Read Hold Time
10
10
Data Bus Active Time (Invalid Data)
40
-
ns
tCDA
-
190
40
0
40
(tA and tF = 10 to 30 ns)
BUS WRITE TIMING WAVEFORMS
BUS READ TIMING WAVEFORMS
2
2
CS,RS
CS,RS
RNi
RNi
DATA BUS
DATA BUS
2-75
ns
ns
ns
ns
ns
fI
R6545/R6545E
CRT Controller (CRTC)
MEMORY AND VIDEO INTERFACE CHARACTERISTICS
(Vee
= 5.0V
±
5%, T A
= T L to T H,
unless otherwise noted)
R6545E
R6545
Symbol
Parameter
Min.
leCH
Minimum Clock Pulse Width. High
200
tCCY
Clock Frequency
Typ.
Max.
Min.
Typ.
Max.
Units
3.7
MHz
t30
ns
2.5
tR' tF
Rise and Fall Time for Clock Input
20
ns
tMAO
Memory Address Delay Time
t80
300
20
100
160
ns
tRAo
Raster Address Delay Time
180
300
100
160
ns
toTO
Display Timing Delay Time
240
450
160
300
ns
tHso
Horizontal Sync Delay Time
240
450
160
300
ns
tvso
Vertical Sync Delay Time
240
450
160
300
ns
leoo
Cursor Display Timing Delay Time
240
450
160
300
ns
MEMORY AND VIDEO INTERFACE WAVEFORMS
~----------tcCY----------~
MAO-MAI3
RAO-RA4
DISPLAY ENABLE
HSYNC, VSYNC
CURSOR
2-76
R6545/R6545E
CRT Controller (CRTC)
LIGHT PEN STROBE TIMING CHARACTERISTICS (For Reference Only)
R6545
R6545A
Max.
Unit
t lPH
LPEN Hold Time
150
-
100
-
ns
tLP1
LPEN Setup Time
120
-
120
ns
t lP2
CCLK to LPEN Delay
-
0
-
0
ns
Symbol
Note: t R• tF
Characteristic
Min.
Max.
Min.
= 20 ns (max)
LIGHT PEN STROBE TIMING WAVEFORMS
CCLK
LPEN
MA~MA13 ______n____-J)(~_____n+_l____J)(~
____
n_+_2_____~
NOTE: "Safe" time position for LPEN positive edge to cause
address n+2 to load Into Ligi)t Pen Register.
It.P2 and t lP1 are time positions causing uncertain results.
TEST LOAD
Vee
2.4KO
I ....
R6545 PIN
.......
'r
R
':'
'7
'7
~7
':'
R = llKO FOR D~D7
24KO FOR ALL OTHER OUTPUTS
C = 130 pF TOTAL FOR D~D7
= 30 pF ALL OTHER OUTPUTS
=
2-77
R6545/R6545E
CRT Controller (CRTC)
CRTC Register Comparison
GENERAL FUNCTIONS
REGISTER
Ra HORIZONTAL TOT
MC6845R
HD6845R
HD6845S
TOT·l
R6545·1
TOT·l
TOT·l
R6545/R6545E
TOT·1
R1 HORIZONAL DISP
ATUAL
ACTUAL
ACTUAL
ACTUAL
R2 HORIZONTAL
SYNC
ACTUAL
ACTUAL
ACTUAL
ACTUAL
R3 HORIZ AND VERT
SYNC WIDTH
HORIZONTAL
HORIZONTAL
AND VERTICAL
HORIZONTAL
AND VERTICAL
HORIZONTAL
AND VERTICAL
R4 VERTICAL TOT
TOT·1
TOT·1
TOT·1
TOT·1
ANY VALUE
R5 VERTICAL
TOT ADJ
ANY VALUE
ANY VALUE
ANY VALUE
EXCEPT
R5 = R9H. X
R6 VERTICAL DISP
ANY VALUE
VIDEO/COLOR OUTPUTS
R, G, B-Red, Green and Blue Color Outputs. Three separate
color analog output voltages. Each output provides a 1.0 Vpp
video signal at high impedance with a I.B Vdc offset. Each color
level is controlled by a 4-bit color code accessed from the LUT
for each pixel position. A digital-to-analog converter (DAC)
converts the 4-bit code to one of 16 output voltage levels (black
level = I.B75 Vdc; white level = 2.BOO Vdc). The three outputs
allow 4096 color level combinations. A composite blanking signal
(1.800 Vdc) Is included in each output.
The output signals include high frequency clock components
which may require low pass filtering in some applications. The
outputs can be connected to the R IN, G IN, and B IN inputs
to a MCI377 color encoder through 15 I'F (typical) AC coupling
capacitors.
CSUBC-Color Subcarrler Clock Output. A TTL compatible
3.579545 MHz ± 10% color subcarrier clock. The clock rate complies with the North American Color Burst Clock Output
Standard. The rate is the SYSCLK divided by eight and is phase
keyed to the horizontal sync (HSYNC) output on C/HSYNC (as
either a component of CSYNC or pure HSYNC). Vertical blanking
interval (VBI) color gating by VSYNC must be done externally
(since some modems require an uninterrupted 3.579 MHz clock).
The color outputs, through external buffers, can also drive
75 ohm loads, e.g., the inputs to an RGB color monitorlTV.
XPAR-Transparent Output. A TTL compatible, active HIGH,
output controlled by one bit in a 4-bit code (three bits are don't
care) in the LUT. A LUT value of lXXX in DRAM asserts XPAR
(HIGH); LUT value of OXXX in DRAM negates XPAR (LOW). This
output can be used to indicate which video source to select.
When XPAR output is HIGH, external video signals should be
selected to display background video; when XPAR output is
LOW, CVDG outputs should be selected to display graphics. The
XPAR output is always HIGH during composite blanking to pass
external vertical blanking interval (VBI) signals, external sync,
color burst, etc.
When the color outputs are connected to an MCI377 color
encoder, the CSUBC output can be connected to the MCI377
CLK input, typically through a 500 pF capacitorl150 I'H inductor
filter network.
C/HSYNC-Composite/Horlzontal Sync Output. Either a
composite sync (CSYNC) or a horizontal sync (HSYNC) output
at TTL levels, asserted "tips down", is selected by the External
Sync (EXT) bit in the Switch Register.
In internal sync (EXT = D), an RS-HO composite sync with lull
serration and equalization is output in either 2: 1 or 1: 1 interlace
as selected by the 2:1 Interlace Select (S21) bit in the Switch
Register (S21 = 1 for 2:1; S21 .. 0 for 1:1).
POWER/GROUND
VeC-Primary Power. 5.0 Vdc.
VSS-Ground. Power and signal ground.
In external sync (EXT = I), a pure HSYNC is output in either
normal or early timing as selected by the Normal Horizontal Sync
(NHS) bit in the Switch Register. In normal timing (NHS = I),
a 15.7 kHz signal is output; in advance timing (NHS = D), a
15.9 kHz stop clock signal is output.
The R6549 CVDG operation is controlled by three free-running
synchronous state machines with the following cycle rates:
When the color outputs are connected to an MCI377 color
encoder, the C/HSYNC output can be connected directly to the
MCI377 SYNC input pin.
Address/Data (AID) Bus Cycle
Horizontal Raster Line Cycle
Vertical Raster Frame Cycle
VSYNC-Vertlcal Sync Input/Output. A TTL compa!ible
vertical sync (VSYNC) input or output signal depending on the
state of the External Sync (EXT) bit in the Switch Register (see
Mode 3). VSYNC ,is an externally generated input at power up
or when EXT = '1. VSYNC is an internally generated output
when EXT = O.
The CVDG also includes timing shift registers and sample flipflops to generate internal and external timing signals; programmed logic arrays (PLAs) to perform I/O decoding, generate
DRAM control signals and determine state machine outputs;
registers to hold command/status and data; an internal 16-bit
row/column bus in display X-V coordinates; internal input and
output B-bit data busses; and input/output buffers to isolate
internal circuits from external interfaces and to drive outputs.
Figure 2 illustrates the main CVDG components.
FUNCTIONAL DESCRIPTION
The VSYNC output can be used to disable the color subcarrier
at the chroma modulator during VBI. Videotex decoders can also
use VSYNC to interrupt the MPU at a 60 Hz rate for blink, task
and timekeeping operations,
698 ns/cycle (1.43 MHz)
63.5 I's/cycle (15.74 kHz)"
33.3 mslcycle (30 Hz)
• A 15.9 kHz stop-clock early sync is selectable.
2-B4
~
TTX
REGISTER/
COUNTER
8
TTX
DMA
CONTROL
& BUFFERS
TTXREO
TTXOE
!!
co
c
t;
!'>
A1
A13
LOGIC
... ADO-AD7
"ar0" <
C
iD
co
a;
g
CAS2
]i)
I--
1'5
~
A/DBUS
CONTROL
PLA
8
i
17
10
8
-y
A/DBUS
INPUT
OUTPUT
BUFFERS
-f
DRAM PAGE
REGISTER
~
~~
INTERNAL
II-BIT
OUTPUT
BUS
I
_
INTERNAL
,......
8-BIT
INPUT
BUS
AID BUS
OUTPUT
CONTROL
LOGIC
I-a
~
~
SWITCH
REGISTER
5
LUTDATA
REGISTER
f--"':'
~
I-
4
~
<'
DRAM
CONTROL
PLA
& BUFFERS
f
~
INTERNA~~
CLOCKING
TIMING
SHIFT
REGISTER &
FLIP-FLOPS
~
~~
3
r<>
4
M
t
I-<
6
'--
VIDEO
DATA
REGISTER
8
l
4
I .-
I
I
1
VERTICAL
STATE
MACHINE
(VSM)
COLOR
LOOKUP
TABLE
(lUT)
5
~
VI
RTIME
CTIME
11
H
SYSTEM
CLOCK
PIXEL
CLOCK
2
,6
4
!-f?
COMPOSITE
SYNC
GENERATOR
(CSG)
l
R
I---
COLOR
SUBCARRIER
CLOCK
1
SYSCLK
I
1
I
PIXCK
I----
~
lUT
OUTPUT
lATCHES
fA.
(')
o
o
<
a:
~
l
I
CSUBC
C/HSYNC
VSYNC
(1/
o
C
XPAR
~ j...1FI""\
~ j... ~
~AC<
~ f-~
..}16
1"'6
VIDEO
SHIFT
REGISTER
,
OE2
OTIME
4
LUTADDRES~ HlL
REGISTER
STATE
MACHINE
(HSM)
OE1
f1¥--
'-- HORIZONTAL
~6
'I
8
k}'
CASP
DRAM
CONTROL
OUTPUT
BUFFERS
f--
.......".
j-!..~
I---
REGISTER
~g ~
RASH
8
K= ~ .OOWT.ru.~
4
ORCS
'"0
,..n
YSCROLL
REGISTER &
COUNTER
8
IOCS
...
<
C
~
& COLUMN (RC)
en
U1
.Ilo
CD
CAS1
&
U1
01
YCDP
REGISTER
8
AID BUS
CONTROL
LINE
BUFFERS
:g:
~16-BIT
I--
2
en
'"cD
8
0
AO
:D
XCDP
REGISTER/
COUNTER
E
RtW
:rJ
RASL
INTERNAL
I--
1
--
1t~...L2 I -
R
G
0'a
i
C')
(1/
~
B
(1/
a
o
~
lUT
ADDRESS
GENERATOR
~C
-
PIXEL CLOCK
c;)
II
R6549
Color Video Display Generator (CVDG)
SYSTEM TIMING
Vertical Raster Frame Cycle
System Clock
An internal vertical state machine (VSM) controls the 33.3 ms
vertical raster frame cycle. The VSM is incremented twice each
horizontal raster line cycle. The VSM count (VSO - VS523 or
VSO - VS524), or state, supports two frames per 30 ms vertical
raster cycle. The upper count depends on the interlace mode
(S21) switch position selected in the Switch Register. When 2:1
interlace mode is selected (S21 = 1), the upper VSM count supports a 262'12 line frame. When 1:1 interlace is selected (S21 = 0),
the upper VSM count supports a 262 line frame.
Internal and output timing signals are derived from the
28.636363 MHz crystal frequency on the SYSClK input pin. A
two-phase non-overlapping 14.318181 MHz (SYSClKl2) clock
is generated to sequence high speed data transfer within the
CVDG.
Timing Shift Register
The Timing Shift Register generates internal timing pulses as
internal timing references at frequencies from 14.318 MHz down
to 13.98 kHz. Flip-flops sample the various timing pulses to
generate derivative" timing reference signals for use by other
CVDG circuits.
A VSM clear sign is normally generated when the VSM upper
count is reached to restart the VSM at 0; however, when external sync is selected (EXT = 1) the VSM clear signal is generated
from the external sync signal input on the VSYNC pin. Internal
vertical state timing signals are generated for internal logic and/or
external output. These signals include vertical sync (VSYNC),
vertical border and blanking, vertical blanking, and equalization
enable pulses and the load Y scroll pointer time.
A two-phase non-overlapping 1.431818 MHz (SYSClKl20) clock
is generated for low speed sequencing within the CVDG and
is also the external microprocessor bus and NO bus timing
reference. One phase of the 1.43 MHz clock drives the E clock
output pin. A quadrature 1.431818 MHz clock leading the E clock
is output on the Q output pin.
An internal vertical sync pulse, a vertical blan~ing pulse, and
an equalization pulse are generated for combining with the
HSYNC serration and equalization pulses when internal sync
is selected (EXT = 0) to output composite sync on the CIHSYNC
pin.
Pixel Clock
A 5.72 MHz pixel clock is output on the PIXCK output pin. Four
pixel output clocks occur each 698 ns (one clock pulse coincident with each of the red, green and blue color level outputs
and the transparent bit output for each pixel location).
The vertical blanking pulse is also buffered and output on the
VSYNC pin wherf internal sync is selected in the Switch Register
(EXT = 0).
VIDEO .RASTER CONTROL
Horizontal Raster Line Cycle
The internal vertical border and blanking pulse is generated and
reported in bit 7 (VB) of the Status Register. The pulse width
is 3.302 ms for 2: 1 interlace (S21 = 1) or 3.333 ms for 1: 1 interlace
(S21 = 0). This duration identifies the time the border color determined from the lUT Data Register is output, except during actual
vertical blanking.
An internal horizontal state machine (HSM) controls the horizontal raster line cycle. The HSM is incremented at the E clock
rate, nominally every 698 ns. When normal horizontal sync
timing is selected in the Switch Register (NHS= 1), 91 horizontal
counts (HSO - HS90), or states, comprise the 63.56 !'s line raster.
When early horizontal sync timing is selected (NHS = 0), typically
to support external synchronization, 90 horizontal counts
(HSO - HS89) provide a 62.86!,s line raster. The first 64 counts
clock the 256 displayed pixels (at four pixels per count). Figure 3
illustrates the horizontal and vertical raster count reference.
An internal load Y offset pointer signal is generated and routed
to the Y Scroll Counter to cause the Y offset to load during the
non-visible portion of the display raster.
Composite Sync and Color Subcarrier
Clock Generation
The HSM generates the horizontal raster timing pulses for
internal logic andlor external output. These signals are the
horizontal sync (HSYNC), horizontal border and blanking, horizontal blanking, serration and equalization timing pulses.
HSYNC is output in one of two forms on the CIHSYNC pin
depending upon the EXT bit state in the Switch Register. If
internal sync is selected (EXT = 0), HSYNC is combined with
horizontal blanking serration, equalization and vertical sync
(VSYNC) pulses to output as composite sync (CSYNC). If
external sync is selected (EXT = 1), the HSYNC signal is output
on CIHSYNC.
The horizontal border and blanking pulse identifies the time that
a border color is output (see lUT Data Register description) outside of the 256 pixel locations except during actual horizontal
blanking. This Signal is reported in bit 6 (HB) of the Status
Register.
A 3.58 MHz color subcarrier clOCk (SYSClKl8 and phase keyed
to horizontal sync) is generated from composite sync and
horizontal sync signals then is output on the CSUBC pin.
An increment vertical count signal is also generated to increment the vertical state machine.
2-86
Color Video Display Generator (CVDG)
R6549
t------t.~ HORIZONTAL STATE MACHINE (HSM) COUNT
= VIDEO REFRESH COLUMN ADDRESSES
89 (EARLY HSYNC)
90 (NORMAL HSYNC)
STATE
MACHINE
(VSM)
COUNT
Y ADDRESS CNTR
(YO-Y7)
= VtDEO REFRESH
ROW ADDRESSES
ACTIVE
PIXEL
o
PIXEL X LOCATION
NOTES:
1. Vertical Slate Transition (HS28)
2. Vertical State Transition and HSYNC (HS73)
3. Symbot definitions:
HBLANK = Horizontal Blanking
tHBLANK = Horizontal Border and Blanking
VBLANK = Verticat Blanking
IVBLANK = Vertical Border and Blanking
CBLANK = HBLANK + VBLANK = Composite Blanking
ICBLANK
IHBLANK + IVBLANK = Composite Borders and Blanking
4. Shading Legend:
==
~ Active Pixel Display Region
~ Right and Left Borders
lSI
Top and Bottom Borders
o
Blanking Region
m Composite SYNC (CSYNC)
Figure 3.
CVDG Video Raster Count Reference
2·87
Color Video Display Generator (CVDG)
R6549
ADDRESSIDATA BUS CONTROL
The E and Q output cloc~ are suppressed during a teletext DMA
transfer. When nXREQ input goes LOW, the Q and E clock
outputs are held LOW to disable the clocks for one MPU bus
cycle. In addition, the increment nx address count goes HIGH
to increment the modulo 32 nx Counter. When nXREQ goes
HIGH at the completion of the DMA data transfer, the E and
Q output clocks are enabled, the nXOE output is negated
(reset HIGH), and the increment nx address count signal is
reset.
The Address/Data Bus state machine controls the operation of
the 698 ns A/D bus cycle. The AID bus cycle contains a 2-byte
video data access cycle and a l-byte I/O data access cycle
(Figure 4). The addresses and data transferred on the AID bus
depend on the phase of the AID bus cycle (Le., the E clock level)
and the type of operation in the 110 data access cycle. Table 2
identifies the source of the addresses for each type of DRAM
access.
Internal reset and initialization signals are generated when both
10CS and DRCS inputs are LOW for test purposes.
Video Data Access Cycle
The video data access cycle (also referred to as the video portion
of the AID bus cycle) occurs during the first half of the AID bus
cycle (when the E clock is LOW). Two bytes of video data
(containing four LUT addresses correspondil'lg to four pixellocations on the display) are read each cycle' from DRAM at the
DRAM address generated by the CVDG. The DRAM address
is generated corresponding to the first of four pixel column locations in the horizontal raster and the pixel row location in the
vertical raster. The video column (X) address of 0 to 64 is controlled by the horizontal state machine. The video row M address
of 209 to 0 is controlled by the Y Address Counter, which is in
turn controlled by the vertical state machine and the Y Scroll
Register. The two data bytes are loaded into the CVDG Video
Data Register for subsequent serialization and LUT access (see
the Pixel Color Generation description).
AID Bus Control PLA
The AID Bus Control PLA decodes CVDG and AID Bus operation commands from buffered AID bus control input signals and
encoded mode bits in the Mode Register. Outputs from the PLA
are buffered and routed to other circuits in the CVDG as internal enable signals.
AID Bus InputlOutput Buffers
The AID Bus InpuVOutput Buffers isolate the internal CVDG data
bus lines from the external AID bus lines (ADO - AD7). Input buffers continuously copy ADO - AD7 onto the internal input data
bus. Output buffers drive the states of the internal output data
bus lines onto ADO - AD7 when enabled by a CVDG output function and clocked by the 14.3 MHz internal clock. Two of these
output buffers drive ADS and AD6 during MPU DRAM access
(DRCS = L) with the DRAM page Signals, Le., VO and
Vl, respectively, or A13 and AO inputs, respectively, depending
on the state of the A 13 input and the P bit in the DRAM Page
Register.
Up to 48k-bytes of Dynamic RAM (DRAM) can be connected to
the AID bus to store video data (LUT addresses) for video refresh,
program instructions/data and received teletext data. The DRAM
is segmented into six 8k-byte blocks with page selection of one
block at a time during access (Figure 5). Four pages are required
for video refresh (VOO - Vll); three pages (VOO, VOl and Vl0)
hold video data exclusively, and one page (Vll) holds video and
program/teletext data. Two other pages hold program data. During the video data access cycle, and some modes of the I/O data
access cycle, paging is handled automatically by the CVDG. The
A13 and AO input lines and the P, Vl and VO bits in the CVDG
DRAM Page Register select the page for MPU DRAM access
during the 110 data access cycle (see MPU DRAM Access
description).
AID Bus Output Control Logic
The AID Bus Output Control Logic drives data onto the internal
output bus from the internal row and column bus lines, from the
LUT, and from other internal CVDG circuits when enabled by
outputs from the AID Bus Control PLA.
DRAM Control PLA and Buffers
The DRAM Control PLA and Buffers generate and drive control
and timing output signals to th'e DRAM; the row, column and
data time output control signals for use by external line buffers
and data line transceivers; and internal signals to control
input/output data direction and to enable the internal row and
column bus,
1/0 Data Access Cycle
The I/O data access cycle (also referred to as the processor
portion of the AID bus cycle) occurs during the second half of
the AID bus cycle (when E clock is HIGH). AID bus address
source and data source/destination depends upon CVDG chip
select (IOCS and DRCS) and Teletext Request (nXREQ)
input levels, the selected CVDG mode, and the register select
(AO and A 1) input levels. Refer to the description of each I/O
access cycle function for details.
Timing pulses from the Timing Shift Registers; control signals
from the Mode and Page registers, AID Bus Control Buffers and
Logic, and AID Bus Control PLA; and control signals generated
and derived from other sections of the CVDG are input to the
PLA.
AID Bus Control Line Buffers and Logic
Output control states from the PLA are buffered and routed to
external DRAM control si9!!al pins (RASL, RASH, CAS1, CAS2,
CASP, OE1, OE2, and W) and to external AID bus control
signal pins (CTIME, RTIME and DTIME). Other output
signals are inverted and routed to internal logic.
The AID Bus Control Line Buffers and Logic condition input and
output AID Bus control Signals. Six input signals (RNi, AO, Al,
A 13, 10CS and DRCS) are buffered and routed to the DRAM
Control PLA.
2-88
Color Video Display Generator (CVDG)
R6549
~1~~-----------------698ns------------------~~1
a
_ _ _ _-.If
I.."--
"'I~t------- VIDEO TIME---__...
E
,~-----PROCESSOR
TIME~
\ ' __ _ _ _ _---Jf
r
RASL AND RASH
, _ __
RASL AND/OR RASH
~~~--_--'/~--~\'-------------CASl AND CAS2
CASP, CAS1 OR CAS2
--~;---\'-(--------~~'-~------WRITE
\ -READ-I
WRITE
\ - "READ - , - READ
,-wRiTE
VIDEO DATA ACCESS
.
I/O DATA ACCESS
I
ADO-AD7
\J ,
Figure 4.
DRAM Address/Data (A/D) Bus Cycle
2-89
-r
R6549
Color Video Display Generator (CVDG)
Table 2.
DRAM Row/Column
-
CVDG Display Row/Column Bus
AlD Bus
Video Cycle'
Address/Data Bus Address Sources
-
CAS
CA4
CA3
CA2
CAl
CAO
RA7
RA6
RAS
RA4
RA3
RA2
RAI
C7
C6
CS
C4
C3
C2
Cl
CO
R7
R6
RS
R4
R3
R2
Rl
RO
AD7
AD6
ADS
AD4
AD3
AD2
ADI
ADO
AD7
AD6
ADS
AD4
AD3
AD2
ADI
ADO
0
V7
V6
V5
V4
V3
V2
0
VI
VO
H6
H5
H4
H3
H2
HI
XI"
Y7
V6
V5
V4
V3
V2
XO'
VI
VO
X7
X6
XS
X4
X3
X2
A06
VI'
V02
A12
All
AID
A9
0
A8
A7
A6
A5
A4
A3
A2
AI
0
AO·
AI39
A12
All
AID
A9
0
AB
A7
A6
AS
A4
A3
A2
AI
TO
I"
I"
TI2
TIl
110
T9
0
TB
T7
T6
T5
T4
T3
T2
TI
RAO
Processor Cycle
COP Graphics'
(IOCS = L. Mode 0)
MPU Video DRAM Access 5
(ORCS
= L. P =
0)
MPU Program DRAM Access8
(ORCS
= L. P =
I)
Teletext DMA Access'o
(TTXREQ = L)
Notes:
1. Video Cycle:
HI - H6
HSM Output = 0 to 64 (= 0 to 255 pixel LUT addresses @ 4 addresses per access);
VO - V7 = V Scroll Counter Output
209 to 0
=
=
2. COP Graphics:
XO - X7 a X COP Register/Counter contents
0 to 255;
VO - V7 = V COP Register contents
0 to 255 (0 to 209 for displayable data)
=
=
3. XI controls the CASI and CAS2 outputs:
Assert CASI
1 - Assert CAS2
o=
-
4. XO controls the RA5[ and RASH outputs:
Assert RASL
1
Assert RASH
o-
=
5. MPU Video DRAM Access: AD - A 12
= MPU Address = 0 to 4096.
6. AO input controls the CASI and CAS2 outputs:
L - Assert CASt
H - Assert CAS2
7. VO and VI bits In the DRAM Page Register control assertion of ADS and ADS outputs. respectively:
Negate output
1 - Assert output
o_
8. MPU Program DRAM Access: AO-AI3 - MPU Address - 0 to 8192
9. AD and A13 Inputs control the AD6 and ADS outputs. respectively:
L - Negate output
H _ Assert output
10. Teletext Access:
T1 - T 4 - Modulo 32 counter incremented by each DMA byte transfer
T5 - T12 • Teletext Pointer Register contents Incremented by Tl - T4 overflow
11. ADS and ADS asserted to select program DRAM.
2-90
Color Video Display Generator (CVDG)
R6549
DRAM Page
Register
A13
1
P
1
VI
X
VO
X
Addr
(Hex)
Addr
(Dec)
lFFF
8191
{
0
0
1
0
X
1
X
1
0
8191
{
{
0
1
0
lFFF
0
8191
0900
08FF
2304
2303
0
0
8191
}
Video 3 (VII)
0
0
0
0
0
lFFF
0
8191
Note 2
VIDEO'
DATA
1
0
PROGRAMI
TELETEXT
Video 2 (VI 0)
Video 1 (VOl)
0
lFFF
0
0,209 J 1,209
--------
0
~
0
PROGRAM
Program 0
(A13 = 0)
lFFF
0
Memory Function
Program 1
(A13 = 1)
lFFF
0
Memory Page
0
8191
{
Video 0 (VOO)
0
---ol---254,0
255,0
0
Note 2
Not•• :
1. 28,880 bytes of video memory are required to support video refresh, i.e., to supply 53,760 4-bit LUT addresses in support of the
210 )( 256 pixel display area. With 32,768 bytes supplied in four 4416 DRAM devices, 5888 bytes are available for general
programfTTX message use in the upper part of video memory page 3 (VII).
2. Nibbles shown correspond to beginning and ending data for 210 x 256 pixel display area in X(column), Y(row) coordinates.
Figure 5.
DRAM Memory Map
2-91
R6549
Color Video Display Generator (CVDG)
PIXEL COLOR GENERATION
parent state (see Table 3). Each entry holds three 4-bit encoded
color levels (0000 = lowest voltage level, 1111 = highest voltage
level) and a l-bit transparent state (0 = off, 1 = on). For each pixel
location the three color level codes (R, G and 8) are sampled
from the LUT, latched and routed through three separate digitalto-analog converters. The transparent bit corresponding to each
pixel location is also accessed from the LUT, latched, buffered
and output on the XPAR pin.
LUT Address Generation
The 16-bit Video Data Register latches the four LUT addresses
contained in the two data bytes acquired during the video data
access cycle. Two 4-bit color lookup table (LUT) addresses are
packed into each byte. The Video Shift Register serializes the
four LUT addresses and transfers them one byte at a time to
the LUT Address Generator. The LUT Address Generator latches
the 4-bit coded LUT addresses from the Video Shift Register,
converts the coded address to 16 binary signals and latches the
binary address (0 - 15) for routing to the LUT.
Digital-To-Analog Conversion (DACs)
The 4-bit color code for each color (R, G and 8) at a pixel position is converted to a corresponding analog voltage through a
16-level digital-to-analog converter (DAe). Four lines from the
four color code lines and their four complements are decoded
to one of 16 levels, sampled and latched. The latched outputs
are in turn connected to the color output pin (R, G and 8) through
a voltage divider ladder network.
LUT Operation
The color look-up table (LUT) is a 16 x 13 bit memory holding
16 entries of R, G and 8 color codes and corresponding trans-
Table 3.
LUT Structure
LUT FORMAT
LUT
ADDR
(HEX)
F
E
0
C
0
B
A
9
GREEN'
XPAR'
3
/" / /
/ /' /
/'/ /
/ ' 1/ /
/ V /
V V V
/'
1
NO
8
/'
7
/ / 1/
/ / 1/
6
5
4
3
2
1
0
RED'
2
1
0
3
2
1
0
3
2
1
0
0
0
0
0
0
1
0
0
0
1
1
1
Example 13
1
0
0
0
1
1
0
0
1
1
1
1
Example 24
./
/ ' ACTUAL . /
DATA
BLUE'
3
./
L L L
~L L
,/ / /
1/ / V
L / V
L L L
Noles:
1. XPAR is a single bit in the LUT; the format shown corresponds
to the LUT Data Register format:
OXXX = XPAR output LOW
1XXX = XPAR output HIGH
2. Color Data Level:
0000 = lowest output voltage = 1.875 Vdc
1111 = highest output voltage = 2.800 Vdc
3. Example 1-LUT Address C Data:
XPAR output = LOW
G output = 1.875 + 0 (0.0617) = 1.875 Vdc
B output = 1.875 + 4 (0.0617) = 2.122 Vdc
R output = 1.875 + 7 (0.0617) = 2.307 Vdc
4. Example 2-LUT Address 9 Data:
XPAR output = HIGH
G output = 1.875 + 8 (0.0617) = 2.369 Vdc
B output = 1.875 + 12 (0.0617) = 2.615 Vdc
R output = 1.875 + 15 (0.0617) = 2.800 Vdc
2-92
Color Video Display Generator (CVDG)
R6549
When iDcs is LOW, the register address inputs (AD and AI)
and the mode selected in the CVDG Mode Register define the
specific CVDG I/O operation, i.e., Mode/Status Register Access,
CVDG Graphics Access (Mode 0). or one of the six CVDG
Parameter Access modes (Modes 1-6). Table 4 shows the
CVDG registers accessible during the I/O access cycle and the
bit assignments. When AI and AD are both HIGH, the register
bits are defined with reference to a pseudo Data Register (DR).
The aOlual internal CVDG register accessed nepends on the
selected mode (see Table 4). The bits are defined in the following
text.
I/O DATA ACCESS CY,CLE FUNCTIONS
The I/O access cycle operates in one of five ways:
1. CVDG Mode/Status Register Access (enabled by 10CS LOW)
2. CVDG Graphics Access (enabled by 10CS LOW)
3. CVDG Parameter I/O Access (enabled by 10CS LOW)
4. MPU DRAM I/O Access (enabled by ORCS LOW)
5. Teletext Byte DMA (enabled by TIXREO LOW)
CVDG Mode/Status Register Access
The basic type of I/O access cycle is determined by the chip
select (IOCS or ORCS) and Teletext Request (TIXREO) inputs.
When neither of the chip select inputs are LOW, nor has a TIX
DMA transfer been initiated by TIXREO LOW, the I/O access
cycle is idle with no data transfer occurring during the processor
portion of the AID bus cycle.
Table 4.
When 10CS is LOW and the register address is zero (AD and
AI inputs are both LOW), the Mode Register (MR) or the Status
Register (SR) is accessed depending upon the Rm input level.
When Rm is LOW, the Mode Register is written; when Rm is
HIGH, the Status Register is read.
CVDG Register Summary
Register
Select
Lines
Register Bit No.
Mode
AI
AD
2
1
D
Mode Register
-
0
0
W
-
-
-
-
S
M2
Ml
MO
OF
Status Register
-
0
0
R
VB
HB
M2
Ml
MO
P
VI
VO
-00
Internal CVOG Register
RIW4
5
6
7
4
3
Resel'
X COP Register
0
0
1
RIW
X7
X6
X5
X4
X3
X2
XI
XO
Y COP Register
0
1
0
RIW
Y7
Y6
Y5
Y4
Y3
Y2
Yl
YO
00
DRAM'
0
1
1
RIW
P3
P2
PI
PO
03
02
01
00
--
LUT Address Register
1
1
1
W
XPE
RE
GE
BE
A3
A2
AI
AD
00
LUT2
2
1
1
R
-
-
-
03
02
01
DO
--
LUT Data Register
2
1
1
W
-
-
-
-
03
02
01
DO
--
Switch Register
3
1
1
W
NHS
S21
EXT
LS
TST
-
-
-
FB
Y Scroll Register
4
1
1
W
Y7
Y6
Y5
Y4
Y3
Y2
Yl
YO
00
TTX Pointer Register
5
1
0
RIW
A12
All
AID
A9
AS
A7
A6
A5
00
DRAM Page Register
6
1
1
W
-
-
-
-
-
P
VI
VO
07
NOles:
1. The DRAM is directly accessed and not the CVDG.
2. Data is transferred from the LUT onto the A/D bus without going through the LUT Data Register.
3. Reset state upon power up.
4. RIW = Read/write (R = read only: W = write only: RIW = read or wrile).
2-93
Color Video Display Generator (CVOG)
R6549
Mode Register
The write-only Mode Register selects the CVDG mode for next
read from, or write to, the CVDG. In addition, the Mode Register
contains a submode flag applicable only to Mode O. The Mode
Register may be written at any time regardless of the current
CVDG mode. The mode and submode bits are initialized to ones
upon power up.
SR7 Vertical Blanking (VB)
o
Vertical blanking is asserted.
Vertical blanking is not asserted.
SR6 Horizontal Blanking (HB)
Bit Position
Register
Mode
A1 AO
0
0
RIW
W
o
716\51 4 13 12 1110
- 1 -1- 1- I S IM21 M1 IMO
SRS-SR3 Mode Selected (M2-MO)
MR7-MR4 Not used (no effect)
Reports the current CVDG mode as selected in bits 2-0
of the Mode Register.
MR3 COP Submode Flag (S) - (Mode 0 only-see Mode 0
description)
o Enable COP Nibble Sub mode. Allows read/write of a
single 4-bit pixel nibble in a by1e.
Enable COP By1e Submode. Allows read/write of two 4-bit
pixel nibbles in a by1e with automatic increment of the
X COP for faster storage of LUT addresses in DRAM.
MR2-MRO
SRS SR4
(M2) (Ml)
0
0
0
0
1
1
1
1
CVDG Mode (M2-MO)
(M2)
(Ml)
(MO)
0
0
0
0
0
0
1
1
0
0
0
1
0
1
0
1
0
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Not used -
Port COP Graphics
LUT Address
LUT Data
Switch Register
V Scroll Offset Register
Teletext DMA Pointer
Set DRAM Page
no effect
SR2 SRl
(P) (Vl)
o
o
o
o
The read-only Status Register reports the selected CVDG mode,
the selected DRAM page and the status of the horizontal and
vertical raster blanking signals. The Status Register may be read
at any1ime regardless of the CVDG mode.
The horizontal blanking (HB) and vertical blanking (VB) signals
report the state of the video raster at the time of access. The
states of these two signals can be used for 15 kHz poll-driven
timing, vertical blanking interval (VBI) identification, LUT loading,
etc. These blanking times reflect the non-pixel display time
including the time actual horizontal and vertical blanking Signals
are generated (for inclusion in composite sync output).
Status
0
0
R
Mode 0 Mode.1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Not used -
Port COP Graphics
LUT Address
LUT Data
Switch Register
V Scroll Offset Register
Teletext DMA Pointer
DRAM Page
no effect
SRO
(VO) Selected DRAM Page
o
o
o
o
o
1
o
Video Page 0: 8k-by1e video RAM
Video Page 1: 8k-by1e video. RAM
Video Page 2: 8k-byte video RAM
Video Page 3: 2.3k-by1e video RAM;
5.9k-byte program RAM
Program Page: 16k-by1e optional program
RAM accessed via ORCS (additionally paged
by A13 and AO inputs)
Mode 0 - Port COP Graphics
When IOCS is LOW and Mode 0 is selected in the Mode
Register, the Port Current Drawing Pointer (COP) Mode is active.
In this mode display column and row addresses can be written
to the CVDG Current Drawing Pointer (COP) X and V registers,
respectively, and pixel data accessed in DRAM. This mode is
primarily used to update LUT addresses (i.e .• the COPs) in the
video pages of DRAM. These LUT addresses are the video data
read from the DRAM by the CVDG during the video portion of
the ND bus cycle.
Bit Position
R/W
1
0
0
0
1
0
1
0
1
0
Reports the current DRAM Page selected in bits 2-0 of
the Page Register (see Mode 6 - Write DRAM Page).
P is the program RAM page indicator. VO and V1 are the
video page indicators.
Status Register
A1 AO
0
0
SR3
(MO)
SR2-SRO DRAM Page Selected (P. Vl. VOl
Note that the mode must be written into the Mode Register before
the desired mode can be executed.
Register
Horizontal blanking is asserted.
Horizontal blanking is not asserted.
\6\51413121110
VB1 Hal M21 Ml IMO I P I Vl IVO
7
2-94
R6549
Color Video Display Generator (CVDG)
into the DRAM (row address strobed by RASL); if XO = 1, the
P nibble (data bits 7-4) is written into the DRAM (row address
strobed by RASH).
This mode can be used to write or read data in any of the four
Bk-byte video pages of DRAM defined by the VO and VI bits
in the CVDG DRAM Page Register. The first three pages (VOO,
VOl and Vl0) are used exclusively for video data. 2304 bytes
(addresses O-BFF) of the fourth page (V11) are used for video
data while the rest of the DRAM can be used for program or
teletext message storage.
When reading the data, only one nibble is read depending on
the state of XO in the X CDP. If XO = 0, the
nibble is read
(row address strobed by RASL); if XO = 1, the P nibble is read
(row address strobed by RASH).
a
In mode 0, the MPU writes the address of the data in display
coordinates into the CVDG X CDP and Y CDP registers. The
X CDP contains the pixel position in the horizontal axis (i.e., the
display column number) and varies from 0 to 255 (hex FF). Each
pixel data nibble corresponds to a location (0 to 15) in the color
look-up table (LUT) from which the corresponding R, G and B
color levels and transparent bit data are retrieved for color
generation. The Y CDP contains the pixel position in the vertical
axis (i.e., the display row number) and varies from 0 to
255 (hex FF). Only values of 0 to 209 are used by the CVDG
during the video portion of the AID bus cycle to access video
data. Y addresses 210-255 identify DRAM address on video
DRAM page VII that can contain non-displayable data, i.e.,
program or teletext data.
Reading or writing the data in this submode has no effect on
the X CDP or Y COP register values.
COP Byte Access Submode
=
The CDP Byte Submode (S
1) reads or writes two 4-bit LUT
addresses at a time (in one byte) with an automatic increment
of the X CDP value in the X CDP Register during write. Each
write of the DRAM data writes the eight data bits on ADO-AD7
into DRAM and increments the X CDP by two upon the completion of the write cycle. (The new X CDP count can be read from
the X CDP Register at any time.) As writing of the data continues,
the X CDP value eventually wraps around to zero and continues
incrementing. The Y COP Register value must be incremented
by writing a new Y COP value. The automatic increment of
X CDP value allows fast horizontal drawing for filling of polygon
and rectangle type shapes (i.e., no intervening X CDP update
Is required). Note that the filled boundaries must be addressed
by the horizontal line software since the XO value has no effect
in this sub mode.
The registers accessible (besides in Mode and Status registers)
in this mode are:
Bit Position
Register
A1 AD RIW
7
&
1
D
XCDP
0
1 RIW X7
X6 X5
X4 X3 X2 XI
XO
V CDP
1
o
V6 V5 V4 V3 V2 VI
VO
DRAM'
1
1 RIW P3
RIW V7
P2
5
PI
4
3
2
This feature is useful for fast non-modulo 210 Y scrolling with
quick reads/writes interleaved by old/new Y address updates.
Note that when S = 1 in the Mode Register, the XO value has
1 and the nibble
no effect (the P nibble corresponds to XO
corresponds to XO
0).
PO 03 02 01 00
'Not CVDG Access
=
=
=
CVOG PARAMETER 1/0 ACCESS
Six CVDG Parameter Access modes allow the MPU to load control parameters into CVDG internal registers. Two of the modes
also allow the MPU to read the parameter values from registers.
The exact mode and access is controlled by the selected mode
in the Mode Register and the regisler select input lines (A 1
and AO).
There are two submodes in Mode 0 that allow accessing of
DRAM data at either the nibble (4-bit) or byte (B-bit) level. The
submode is selected by the S bit (bit 3) in the Mode Register:
COP Nibble Submode
CDP Byte Submode
S=O
=1
Mode 1 -
LUT Address
In Mode 1, data written to register address 3 (A 1 = 1 and
AO = 1) is loaded into the LUT Address Register. Four bits
control LUT write and read and the other four bits contain the
actual LUT address. Bits 7-4 (XPE, RE, GE and BE) enable
writing into, or reading from, corresponding sections of the LUT
(i.e., XPAR, R, G and B) during Mode 2 access. Bits 3-0 in the
register contain the LUT address (0-15) accessed during
Mode 2.
COP Nibble Sub mode
The CDP Nibble Submode (S = 0) reads or writes DRAM data
one nibble at a time. Eight bits of data corresponding to two 4-bit
LUT addresses (P3-PO and 03-00) are on the AID data bus,
but only one nibble is read or written during each access.
a
When writing the data, the
nibble should contain the same
pixel data as the P nibble. Only one of the nibble values is
strobed Into DRAM according to the XO value in the X CDP
Register which enables the RASL or RASH signal to DRAM
during the write. If XO 0, the nibble (data bits 3-0) is written
=
a
Reading of the DRAM data in this submode does not effect the
X CDP count.
=
=
S
=
=
The X CDP Register is accessed at register address 1 (AI = 0
and AO = 1) and the Y CDP Register is accessed at register
1 and AO 0). When register address 3 (AI 1
address 2 (A1
1) is detected,the CVDG generates DRAM row and
and AO
column addresses corresponding to the display coordinates
loaded in the X CDP and Y CDP registers. Data is then written
from the AID bus to the DRAM (RiW = low) or read from the
high).
DRAM to the AID bus (RiW
Bit Position
Register
a
LUT Address
2-95
AI AD RIW
1
1
W
7]&151413121110
XPE] REjGEj':E 1A31A21 A1 1AO
R6549
Color Video Display Generator (CVDG)
OR7
Transparent Enable (XPE)
0
Disable XPAR write or read
Enable XPAR write or read
OR6
0
DRS
0
1
During a read, data is transferred from the LUT directly to the
AID bus without going through the LUT Data Register. XPAR is
not availabe for read back.
BII Posilion
Red Enable (RE)
Register
Disable R write or read
Enable R write or read
LUT Data"
Al AD RIW
1
AIW
1
I & 15 J 41 3 121' 1 0
- I - I - I - I 03 I02 J01 I DO
7
"During a read. data is transferred directly from LUT to NO bus
without going through LUT Data Register.
Green Enable (GE)
OR7-0R4 Not used (no effect)
Disable G write or read
Enable G write or read
OR3-0RO Color Level Code or Transparent Bit State
OR4
0
Blue Enable (BE)
Disable B write or read
Enable B write or read
R, G or B Color Output Level
03
02
01
00
0
0
0
0
0
0
0
Color output level 0
Color output level 1
03
02
01
00
XPAR Output Level
0
X
X
X
X
X
X
XPAR output LOW
XPAR output HIGH
(X = no effect)
OR3-0RO LUT Address (A3-AO)
Color output level 15
OR3 OR2 ORI
(A3) (A2) (AI)
o
o
o
o
o
o
ORO
(AO)
o
1
LUT address 0
LUT address 1
LUT address 15
Mode 3 -
Switch Register
In Mode 3, switch position data (represented by bit states) written
to register address 3 (A 1 = 1, AO = 1) is loaded into the CVDG
Switch Register. Three bits control video raster operation, one
bit controls the LUT address access source, and one bit enables
the CVDG test mode. All five bits are set to a 1 by power up.
The LUT address in the LUT Address Register, rather than the
LUT addresses read from DRAM, is also used to lookup the color
level code in the LUT during the active display time (border andlor
pixel) in two circumstances:
1. Outside the 256 x 210 graphics area, i.e., to generate the
border color. Note that programs loading the LUT during the
vertical blanking interval {VB I) must restore the address of the
border color in the LUT into the LUT Address Register prior
to unblanking.
Bit Position
Register
Switch
2. Within the 256 x 210 graphics area when the LS bit = 0 in
the Switch Register.
OR7
o
1
Mode 2 - LUT Data
In Mode 2, LUT data (i.e., color levels and transparent state)
written to, or read from, register address 3 (AI = " AO = 1)
is loaded into, or read from the LUT at the LUT address contained in the LUT Address Register. Only the section (R, G, B
andlor XPAR codes) of the LUT entry enabled by bits 7-4 in the
LUT Address Register are accessed. Normally only one enable
bit at a time is set to a 1. During a write, data will be written
into each LUT section enabled. During a read, ambiguous data
will be accessed if more than one enable bit is set.
OR6
The transparent state (XPAR) is only one bit (03). The other three
data bits (02-00) are don't care.
OR4
o
1
ORS
o
o
During a write, the data on the AID bus is written into the CVDG
LUT Data Register. The LUT Address Generator latches the 4-bit
LUT address from the LUT Data Register rather than from the
Video Shift Register. The LUT Address Generator then
generates the 16-bit binary address for routing to the LUT. The
LUT is loaded in a Similar manner as described for pixel color
generation.
OR3
o
2-96
Al AD RIW
1
1
w
71&151413121'10
NHSIS211EXTI LS ITSTI-I -
1-
Normal Horizontal Sync (NHS) Select
Early 15.9 kHz (HSYNC) Output
Normal 15.7 kHz HSYNC Output
2:1 Interlace Select (S21)
1: 1 interlace
2: 1 interlace
External Sync Select (EXT)
Internal sync output on VSYNC (C/HSYNC output
enabled.
External sync input on VSYNC (C/HSYNC output
disabled)
LUT Address Select (LS)
Select the LUT Address Register as the LUT address
source
Select Video Shift Register data as LUT address source
Test Mode Select (TST)
Normal mode; Vertical state machine (VSM) and Y
address counter (YAC) run at normal rate
Test mode; VSM and YAC run at 1.413 MHz (used for
factory test only)
R6549
Mode 4 -
Color Video Display Generator (CVDG)
Y Scroll Register
DR7-DR3 Not Used (no effect)
In Mode 4, a Y scroll offset value written to register address 3
(A 1 = 1, AO = 1) is loaded into the Y Scroll Register. The Yscroll
offset may vary from 0 to 209 (decimal). The value written defines
the first horizontal row to be displayed at the top of the
2S6 x 210 graphics image area.
Y Scroll
A1 AO RIW
I
1
W
Selected DRAM Page
DR2 DR1
(P) (VI)
ORO
(VO)
0
0
0
0
Bit Position
Reglsler
DR2-DRO
716151413121110
0
0
DR7-DRO
Y Scroll Offset
0000000
0000001
Offset = 0
Offset =
11010001
Offset = 209 (maximum allowed)
Mode 5 -
Teletext DMA Pointer
MPU DRAM I/O ACCESS
nx
nx
A13 input high causes program DRAM to be accessed during
the processor portion 01 the AID bus independent of the P bit
value in the DRAM Page Register. CASP is asserted in response
to the A13 HIGH to strobe the column address lines into pro·
gram DRAM.
Bit Position
o
Telelext Pointer 1
716151413121110
RIW A121Al11AlO1 A91 ASI A71 A61 AS
When A13 input is LOW, the section of DRAM accessed depends
on the P bit value in the DRAM Page Register and the AO input.
If P = 0, video DRAM is accessed; CAS1 is generated when
AO is LOW and CAS2 is generated when AO is HIGH. If P = 1,
program DRAM is accessed since CASP is generated instead
of CAS1 or CAS2 to strobe the DRAM column address.
The status of the P, VI and va in the Mode/Status Register are
unchanged during a Teletext DMA data transfer.
Mode 6 -
Set DRAM Page
The ADS and AD6 outputs are driven by the CVDG during DRAM
column address generation in the processor portion 01 the AID
bus cycle as controlled by the P bit in the DRAM Page Register.
If video DRAM is selected (P = 0), the VO and V1 bits in the
DRAM Page Register are output on ADS and AD6, respectively.
If program DRAM is selected (P = 1), the AO and A13 inputs
are output on ADS and AD6, respectively.
In Mode 6, data written to register address 3 (A1 = 1, AO = 1)
is loaded into the DRAM Page Register. The data contains a
3-bit DRAM page select code and five unused bits (don't care).
These DRAM page select bits specify the Bk-byte DRAM page
accessed during a MPU DRAM access (DRCS = low) when A13
input is LOW. The DRAM page bits can be read Irom the Status
Register at any time.
Note that the DRAM requires assertion 01 all three control signals
lor a valid access (i.e., RAS, CAS and OE for a read and RAS,
CAS and W for a write). The CVDG sometimes outputs one or
two of these signals but not all three control signals in "no
access" situations.
BII Position
Register
DRAM Page
0
Video Page 0: Bk-byte video RAM
Video Page 1: Bk·byte video RAM
Video Page 2: Bk·byte video RAM
Video Page 3: 2.3k-byte video RAM;
S.9k·byte program RAM
Program Page 0: 16k-byte optional program
RAM accessed via ORCS (additionally paged
by A 13 and AO inputs)
When ORCS is LOW, the MPU directly accesses the DRAM in
an address map manner. The MPU generates the DRAM row
and column addresses (except lor two column address lines
which are driven by the CVDG). The CVDG drives the ADS and
AD6 lines during DRAM column address time and also outputs
control signals (RTIME, CTIME and DTIME) to enable external
AID bus buffers. MPU address line A1-AB are enabled onto AID
bus lines ADO-AD?, respectively, by RTIME to drive the DRAM
row address. MPU address line A9-A12 are enabled onto AID
bus lines AD1-AD4, respectively, by CTIME to drive the DRAM
column address. The CVDG drives ADS and AD6 with one 01
two sets of Signals during CTIME. External bidirectional data line
buffers are enabled by DTiME in the direction controlled by the
MPU Rm output to transfer data between the MPU data bus
lines 00-07' and AID bus lines ADO-AD7.
In Mode S, an B-bit Teletext pointer written to register address 2
(A1 = 1, AO = 0) is loaded into the
Pointer Register and
Counter. The pointer, consisting of address bits A12-AS
specifies the starting address on a 32-byte boundary for the DMA
transfer of teletext data into video page 3 of DRAM. During a
teletext DMA data transfer, the Modulo 32 Teletext Counter is
incremented by one upon each DMA byte transfer. The
Pointer Register is incremented by one every 32 bytes. The value
of the Teletext Pointer can be read at any time in Mode S.
A1 AO R/W
1
0
Y7 1 Y6 1 YSI Y4 1 Y3 1Y21 Yl 1 YO
0
Register
0
A1 AO R/W
1
1
W
716151413121110
- I - I - I - I - I P I V1 I VO
2-97
II
R6549
Color Video Display Generator (CVDG)
TELETEXT DMA 110 ACCESS
the upper count is incremented by one to increment the total
address. The address is reset to zero during horizontal blanking. The upper couni may be read from the TTX Pointer Register
at any time in Mode 5.
Teletext data can be DMA transferred from a teletext prefix
processor connected to the AID bus to DRAM locations
addressed by the CVDG. A 13-b" TTX Latch/Counter determines
the DRAM address. The upper a-bits of the TTX Counter Is a
latch. The value of the latch is defined by the TTX Pointer
Register which can be loaded in Mode 5 by writing to register
address 2 (A1 = 1 and AO = 0). The TTX Pointer Register vahle
therefore defines the TTX DMA starting address on a 32-by1e
boundary. The lower 5-bits of the TTX Latch/Counter is a
modulo 32 counter. This counter increments by one after each
TTX by1e transfer. When the counter overflows (i.e., from 31 to 0)
TTX DMA transfer is initiated by asserting TTXREO to the
CVDG. The CVDG asserts TTX Output Enable (TTXOE) to
acknowledge TTXREO receipt, suspends outputting the E and
clocks for one cycle, outputs the 13-bit DRAM address and
asserts DRAM Write Enable fiI) to enable writing into DRAM.
a
Note that DMA must be used only when the horizontal sync is
genlocked to the external teletext raster.
2-98
Color Video Display Generator (CVDG)
R6549
~-----------------------MPUADDRESSBUSINPUT------------------~.
_ _ MPU DATA BUS 1 1 0 _
RTIME
CliME
Vi:::,.
DTIME
74LS245
AD7
AD6
ADS
AD4
AD3
AD2
ADl
ADO
R6549
CVDG
4416
_(V1.L) __
CASl
(VIDEO)
CAS2
(VIDEO)
~----------.
CASP I---.....H:I
(PGM)
OEl r-----------~~~~~
~
___0_E2J1----------------t~it~~
NOTES: 1. CASP allows memory managemenl 01 many program RAM pages in 16K-byte blocks
(TMS4416-120 RAM devices may be required lor extended AID bus).
2. Page bits may come Irom address decoder or static outputs of a parallel port.
Figure 6.
CVDG Connection to AID Bus and DRAM
2-99
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R6549
Color Video Display Generator (CVDG)
AC CHARACTERISTICS
(Vee = 5.0V
± 5%,
Vss = 0)
MPU CLOCK AND CONTROL LINE TIMING
Ref. Fig. 8
No.
I
2
3
4
5
6
7
8
9
10
tl
12
13
14
Symbol
tEcvC
t"t,
tELEH
tEHEl
tElOH
tOHEH
t EHOl
tOlEl
tSlEH
tSHEH
tEHO V
tELOZ
tovEl
tElOZ
Parameter
E Cycle Time
E and Q Rise and Fall
E Low to E High
E High to E Low
E Low to Q Rising
Q High to E Rising
E High to Q Falling
Q Low to E Falling
Chip Select Low to E Rising (Setup)
Chip Select High to E Rising (Hold)
E High to Data Valid (Read)
E Low to Output High Z (Read)
Data Valid to E Falling (Write)
E Falling to Data Invalid (Write)
Note:
1. Based on 28.636363 MHz SYSCLK input.
2-102
Min.
Typ.
700
698
25
350
350
175
175
175
175
70
0
Max.
240
10
100
30
Unit
Notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
I
R6549
Color Video Display Generator (CVDG)
E
II
Q
ADO-AD7 _
(READ) (IOCS '" L,RIW '" H) -
-
-
-
-
-
-
-
-
-
-
-
DRAM VIDEO CYCLE
ADO-AD7 _
(WRITE) (IOCS", L,RIW '" L) -
-
-
-
-
-
-
-
-
-
-
-
~
-
-
-
-
-
-
~--{113}---+I
CVDGDATA
VALID-WRITE
Figure 8.
CVDG-MPU AID Bus Timing Waveforms
2·103
R6549
DRAM TIMING ReI. Fig. 9
No.
1
2
3
4
5
6
7
B
9
10
11
12
13
14
15
16
17
lB
19
20
21
22
23
24
25
26
27
2B
29
DRAM TIMING ReI. Fig. 9
No.
30
31
33
36
37
3B
39
40
41
42
43
44
Color Video Display Generator (CVDG)
VIDEO ACCESS CYCLE
Symbol
tALATL
tRTLRTH
tALCTL
tCTLCTH
tALOTL
tOTLOTH
t AC
tAP
tAAS
tACO
tCAS
tCSH
tASH
tCPN
t CAP
I,
tACS
t ASA
tAAH
tASC
leAH
tAA
tAAC
tCAC
tRLG1L
tGLGHr
tOEA
tOEZ
tALG2L
Min.
Parameter
RAS Low to RTIME Low (Delay)
RTIME Low to RTIME High
RAS Low to CTIME Low (Delay)
CTIME Low to CTIME High
RAS Low to DTIME Low (Delay)
DTiME Low to DTIME High
RAM ReadlWrite Cycle
RAS High Width
RAS Low Width
RAS Low to CAS Low (Delay)
CAS Low Width
RAS Low to CAS Rising (Delay)
CAS Low to RAS Rising (Delay)
CAS High Width
CAS High to RAS Falling (Delay)
RAS and CAS Transition Times
Read Command Setup
Row Address Setup
Row Address Hold
Column Address Setup
Column Address Hold
RAS Low to Column Hold
RAS Low 10 Data Valid (Setup)
CAS Low to Data Valid (Setup)
RAS Low 10 OEI Low (Delay)
OE Low to OE High
OE Low 10 Data Valid (Setup)
OE High to Output High Z (Hold)
RAS Low to OE2 Low (Detay)
Typ.
Max.
315
70
35
B7
122
157
350
105
245
70
245
315
175
105
35
5
105
35
35
35
70
140
150
80
140
70
0
0
40
35
210
Unit
Notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MPU DRAM.ACCESS CYCLE
Symbol
tAAH
IACH
tGLGH
tos
twp
tOH
IOHC
IOHA
IWCA
IWCH
IAWl
tCWL
Min.
Parameter
Read Command Hold After RAS High
Read Command Hold After CAS High
OEI. OE2 Low to OEI. OE2 High
Dala Setup
W Low to W High
Data Hold After W Low
Dala Hold After CAS Low
Dala Hold After RAS Low
Wrile Command Hold After RAS Low
Write Command Hold After CASP Low
Write Command Selup before RAS Rising
Write Command Selup before CAS Rising
2-104
Typ.
2BO
210
140
12
140
70
175
245
315
245
70
140
Max.
Unll
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes,
Color Video Display Generator (CVDG)
R6549
E ~~________________~I
\
FJ
W
(MPU READ)
ADO-AD7
(MPU READ)
W
(MPUWRITE)
ADO-AD7
(MPUWRITE)
Figure 9.
CVDG·DRAM AID Bus Timing Waveforms
2·105
Color Video Display Generator (CVDG)
R6549
TELETEXT DMA CYCLE TIMING
Ref. Fig. 10
No.
1
2
3
4
Symbol
Parameter
Min.
tELAH
tELGL
tOlGH
NORMAL CYCLE
Figure 10.
Max.
Unit
Notes
ns
ns
ns
ns
10
595
140
TTX DMA CYCLE
Teletext Prefix Processor -
Typ.
80
TTXREO Low to E Low (Setup)
E Low to TTXREO High (Hold)
E Low to TTXOE Low
TTXOE Low to TTXOE High
tRlEl
NORMAL CYCLE
CVOG Timing Waveforms
HORIZONTAL VIDEO TIMING
Rei. Fig. 11
No.
I
2
3
4
5
6
7
8
9
'10
11
Symbol
Parameter
Min.
Typ.
Max.
Unit
H Sync to Setup
H Front Porch
H Sync to XPAR
XPAR Front Porch
H Sync to Border 1
H Sync to Graphics
H Sync to Border 2
Border Front Porch
H Sync Tip
H Period (Normal)
H Period (Early)
9.3
1.4
9.4
1.5
10.16
2.79
8.38
12.57
57.27
2.79
4.81
63.556
62.857
9.5
1.6
ps
ps
ps
ps
ps
pS
-
-
-
-
Notes: 1. RS-170A Specification (shown for reference only).
2. ± O.lps; based on 28.636363 MHz SVSCLK input.
2-106
-
-
-
-
-
pS
pS
pS
pS
pS
Notes
I
1
2
2
2
2
2
2
2
2
2
R6549
Color Video Display Generator (CVDG)
~
EXTERNAL ACTIVE VIDEO
REF
®
EXTERNAL
VIDEO
REFERENCE
II
0
XPAR
OUTPUT
0
RGBVIDEO
OUTPUT
- VYH
_ VYL
- VYB
C/HSYNC OUTPUTS,
BORDER COLOR TIME
CSYNC
OUTPUT
HSYNC
NORMAL
OUTPUT
- VOH
- VOL
HSYNC
EARLY
OUTPUT
- VOH
- VOL
@
Figure 11.
Horizontal Video Output Timing Waveforms
2-107
R6549
Color Video Display Generator (CVDG)
Vertical Cycle Timing
Ref. Fig. 12
No.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
1
2
Vsu
VH
VSYNC Low Input to First Serration Setup
VSYNC Low Input Pulse Duration
VSYNC Low Output Pulse Duration (Burst Blank)
V Blank Duration
V Unblank to Graphics Duration (Top Border)
Graphics to V Blank Duration (Bottom Border)
20
63.5
19
52
21
31
-
-
ns
~s
-
H
H
H
H
3
3
1
1
1
1.2
-
-
Notes: 1. H = HSYNC pulse width (63.5 ~s)
2. 2:1 interlace mode.
3. Shown lor reference only-not an R6549 requirement.
EXTERNAL
SYNC
REFERENCE
(FROM
EXTERNAL
CIRCUIT)
VSYNCINPUT
~~
--------,1 II"T"T"IIT'T'TI I".•----I-.- - - i--r-T
a.
Vertical Synchronization
BLACK NEGATIVE
DIRECTION TIME-
+
CSYNC
OUTPUT
3H--~----3H---4-H~
I
I-H+-3H
EQUALIZING PULSE VERT SYNC
PULSE
INTERVAL
I INTERVAL
O.SH
1,~T1 + V
I-
,
I--
1nnn.nJ
EQUALlZ!NG
9 TO 12 H PULSES
PULSE
INTERVAL
1
\-H-j
:
---I
I
:
I
n~~r'~I~r--ir-,rl~
i
b.
RS·17OA Composite Sync VBI Timing Specifications
Figure 12.
Vertical Cycle Waveforms-2:1 Interlace
2·108
R6549
Color Video Display Generator (CVDG)
TELETEXT DMA CYCLE TIMING
ReI. Fig. 13
No.
1
2
3
4
Symbol
Parameter
tElPL
E Low to PIXCK High
PIXCK High to PIXCK Low
PIXCK Low to PIXCK High
PIXCK Cycle
tpHPL
tplPH
IpCYC
Figure 13.
Min.
Video Output Waveforms
2-109
Typ.
0
70
105
175
Max.
Unit
ns
ns
ns
ns
Notes
Color Video Display Generator (CVDG)
R6549
DC CHARACTERISTICS
= 5.0V ± 5%, Vss = OV, TA
(Vee
= O°C to 70°C,
Parameter
unless otherwise noted)
Symbol
Input High Voltage
SYSCLK
IOCS, ORCS, TTXREO, AO,AI, A13, RNY,
VSYNC, ADO-AD7
Min.
Typ.
Max.
Unit
Test Conditions
V
V'He
Vee - 0.75
V'H
Vss + 2.0
V'Le
V'L
Vss - 0.3
Vss - 0.3
-
Vee
-
Vss + 0.4
Vss + 0.8
Vee
Input Low Voltage
V
SYSCLK
IOCS, ORCS, TTXREO, AO,AI,AI3, RNY
VSYNC, ADO-AD7
Input Leakage Current
I'L
Output High Voltage
E
-
-
flO
-
VOH
~A
V
V'N = OV to 5.25V
Vee = 0
Vee = 4.75V
10H = -0.14 mA
Note I
Vee - 0.75
-
-
0, RTIME, CTIME, DTIME,
RASL, RASH, iii
CASI, CAS2, CASP, OEI, OE2, TTXOE,
C/HSYNC, VSYNC, CSUBC, PIXCK, XPAR
Vss + 2.4
-
-
10H = -80
Note 2
ADO-AD7
Vss + 2.4
-
-
10H = -170
Note 3
-
-
Vss + 0.4
O,RTIME,CTIME, DTIME,
RASL, RASH, iii,
CASI, CAS2, CASP, OEI, OE2, TTXOE,
C/HSYNC, VSYNC, CSUBC, PIXCK, XPAR
-
-
Vss + 0.4
10L = 1.6 rnA
Note 2
ADO-AD7
-
-
Vss + 0.4
10L = 3.0 rnA
Note 3
10FF
-
-
f20
VVH
-
+2.800
Output Low Voltage
R,G, B
VVL
-
Output Blanking Voltage
VVB
-
Output Low Voltage
E
.
Output Leakage Current
(Off·State)
V
VOL
~A
~A
Vee = 4.75V
10L = 1.7 rnA
Note I
~A
V'N = 0 to 5.25V
-
V
CL =30pF
RL = 10K Ohms
t,lt, = 50 ns
+ 1.875
-
V
+ 1.800
-
V
ADO-AD7
Output High Voltage
R,G, B
R,G, B
Input Capacitance'
SYSCLK
IOCS, ORCS, TTXREO, AO, AI, A13, RNY,
VSYNC, ADO-AD7
Notes:
I. Output Load: I
2. Output Load: I
3. Output Load: 6
4. This parameter
C'N
pF
-
TTL gate; C L = 140 pF
TTL gate; C L = 100 pF
DRAM, 2 LS244 buffers and I LS245 transceiver; C L = 180 pF
is periodically sampled and is not 100% tested.
2·110
-
to
-
5
Vee = 5.0V, chip
deselected, pin
Under test at OV,
TA = 25°C,
f = 0.986 MHz
(SYSCLK
= 28.6363 MHz)
R6549'
Color Video Display Generator (CVDG)
ABSOLUTE MAXIMUM RATINGS*
Parameter
Supply Vollage
Symbol
Value
Unit
Vcc
-0.3 to + 7.0
V
Input Voltages
V,N
-0.3 to +7.0
V
Operating Temperature
TA
Oto+70
·C
Storage Temperature
TsTO
-55 to + 150
·C
'NOTE: Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the other
sections of this document is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
PACKAGE DIMENSIONS
40·PIN PLASTIC DIP
[: ~~ ~ ~~ ~~ ~ ~ ~~: ~::: :IJ
I
I
A
rL~
J~±rr-:l
H
..! L G
-- F
..... ·0
K __ M
2-\\\
OtM
A
B
C
0
F
G
H
J
K
L
M
N
MILLtMETERS
MIN
MAX
51.28 52.32
13.72 14.22
3.55
5.08
0.36
0.51
1.02
1.52
2.54 BSC
1.65
2.16
0.20
0.30
3.05
3.56
15.24 BSC
10·
7"
0.51
1.02
tNCHES
MtN
MAX
2.040 2.060
0.540 0.560
0.140 0.200
0.014 0.020
0.040 0.060
0.100 BSC
0.065 0.085
0.008 0.012
0.120 0.140
0.6OOBSC
10°
7°
0.020 0.040
EI
R6551
'1'
Rockwell
R6551
Asynchronous Communications
Interface Adapter (ACIA)
DESCRIPTION
FEATURES
The Rockwell R6551 Asynchronous Communications Interface
Adapter (ACIA) provides an easily implemented, program controlled interface between 8-bit microprocessor-based systems
and serial communication data sets and modems.
• Compatible with 8-bit microprocessors
• Full duplex operation with buffered receiver and transmitter
• Data set/modem control functions
• Internal baud rate generator with 15 programmable baud
rates (50 to 19,200)
• Program-selectabl~ internally or externally controlled receiver
rate
• Programmable word lengths, number of stop bits, and parity
bit generation and detection
• Programmable interrupt control
The ACIA has an internal baud Jate generator. This feature eliminates the need for muHiple component support circuits, a crystal
being the only other part required. The Transmitter baud rate
can be selected under program control to be enhe~ 1 of 15 different rates from 50 to 19,200 baud, or at '/'6 times an external
clock rate. The Receiver baud rate may be selected under program control to be either the Transmitter rate, or at '/'6 times
an external clock rate. The ACIA has programmable word
lengths of 5, 6, 7, or 8 bits; even, odd, or no parity; 1, 1'12, or
2 stop bits.
• Program reset
• Program-selectable serial echo mode
•
•
•
•
•
•
The ACIA is designed for maximum programmed control from
the microprocessor (MPU), to simplify hardware implementation. Three separate registers permit the MPU to easily select
the R6551's operating modes and data checking parameters
and determine operational status.
Two chip selects
2 or 1 MHz operation
5.0 Vdc ± 5% supply requirements
28-pin plastic or ceramic DIP
Full TTL compatibility
Compatible with R6500, R6500/* and R65COO microprocessors
The Command Register controls parity, receiver echo mode,
transmitter interrupt control, the state of the RTS line, receiver
interrupt control, and the state of the DTR line.
The Control Register controls the number of stop bits, word
length, receiver clock source, and baud rate.
VSS
eso
eSI
RES
Rxe
XTLI
XTLO
RTS
eTS
TxD
DTR
RxD
RSO
RSI
The Status Register indicates the states of the IRQ, DSR, and
DCD lines, Transmitter and Receiver Data Registers, and
Overrun, Framing, and Parity Error conditions.
The Transmitter and Receiver Data Registers are used for temporary data storage by the ACIA Transmit and Receiver circuits.
ORDERING INFORMATION
Part No.: R655L __
[
Temperature Range (T L to T H):
Blank = O"C to + 70°C
E = -40"C to +85°C
Package:
C = Ceramic
P = Plastic
Frequency Range:
No Letter = 1 MHz
A = 2 MHz
Document No. 29651N90
Figure 1.
Product Description
2-112
1
28
RiW
2
27
P2
3
4
26
25
07
IRQ
5
24
06
6
7
8
23
22
21
05
04
9
10
20
19
01
11
12
18
00
17
16
OSR
DCD
vee
13
14
15
03
02
R6551 ACtA Pin Configuration
Order No. 284
Rev. 4, June 1987
Asynchronous Communications Interface Adapter (ACIA)
R6551
as
T,a
00.D7
iFiQ
fiCO
MV
R,C
DsR
CSO
lCTu
CS1
lCTLO
RSO
iifII
RS1
RfS
;,
R,a
RES
Figure 2.
ACIA Internal Organization
FUNCTIONAL DESCRIPTION
TIMING AND CONTROL
A block diagram of the ACIA is presented in Figure 2. A descrip·
tion of each functional element of the device follows.
The Timing and Control logic controls the timing of data transfers
on the internal data bus, the registers, the Data Bus Buffer, the
microprocessor data bus, and the hardware reset.
DATA BUS BUFFERS
Timing is controlled by the system 02 clock input. The chip will
perform data transfers to or from the microcomputer data bus during the 02 high period when selected.
The Data Bus Buffer interfaces the system data lines to the inter·
nal data bus. The Data Bus Buffer is bi-directional. When the
RNi line is low and the chip is selected, the Data Bus Buffer
writes the data from the system data lines to the ACIA internal
data bus. When the RNi line is high and the chip is selected,
the Data Bus Buffer drives the data from the internal data bus
to the system data bus.
All registers will be initialized by the Timing and Control Logic
when the Reset (RES) line goes low. See the individual register
description for the state of the registers following a hardware
reset.
INTERRUPT LOGIC
The Interrupt Logic will cause the IRQ line to the microprocessor
to go low when conditions are met that require the attention of
the microprocessor. The conditions which can cause an interrupt will set bit 7 and the appropriate bit of bits 3 through 6 in
the Status Register, if enabled. Bits 5 and 6 correspond to the
Data Carrier Detect (DCD) logic and the Data Set Ready (DSR)
logic. Bits 3 and 4 correspond to the Receiver Data Register full
and the Transmitter Data Register empty conditions. These conditions can cause an interrupt request if enabled by the Command Register.
TRANSMITTER AND RECEIVER DATA REGISTERS
These registers are used as temporary data storage for the
ACIA Transmit and Receive Circuits. Both the Transmitter and
Receiver are selected by a Register Select 0 (RSO) and Register
Select 1 (RS1) low condition. The Reacl/Write (RiW) line determines which actually uses the internal data bus; the Transmitter
Data Register is write only and the Receiver Data Register is
read only.
Bit 0 is the first bit to be transmitted from the Transmitter Data
Register (least significant bit first). The higher order bits follow
in order. Unused bits in this register are "don't care".
1/0 CONTROL
The 1/0 Control Logic controls the selection of internal registers
for a data transfer on the internal data bus and the direction of the
transfer to or from the register.
The Receiver Data Register holds the first received data bit in
bit 0 (least significant bit first). Unused high-order bits are "0".
Parity bits are not contained in the Receiver Data Register. They
are stripped off after being used for parity checking.
The registers are selected by the Register Select (RS1, RSO) and
ReadlWrite (RiW) lines as described later in Table 1.
2-113
fI
R6551
Asynchronous Communications Interface Adapter (ACIA)
Parity Error (Bit 0). Framing Error (Bit 1). and
Overrun (Bit 2)
STATUS REGISTER
The Status Register indicates the state of interrupt conditions and
other non-interrupt status information. The interrupt conditions are
Data Set Ready and Data Carrier Detect transitions, Transmitter
Data Register Empty and Receiver Data Register Full as reported
in bits 6 through 3, respectively. If any of these bits are set, the
Interrupt (IRQ) indicator (bit 7) is also
Overrun, Framing Error,
and Parity Error are also reported (bits 2 through 0 respectively).
set.
7
6
Bit 7
0
1
BitS
0
1
Bit 5
0
1
Bit 4
0
1
Bit 3
0
1
Bit 2
0
1
Bit 1
0
1
Bit 0
0
1
5
4
3
2
Interrupt (IRQ)
No interrupt
Interrupt has occurred
None of these b,its causes a processor interruptto occur, but they
are normally checked at the time the Receiver Data Register is
read so thatthe validity olthe data can be verified. These bits are
self clearing (i.e., they are automatically cleared after a read olthe
Receiver Data Register).
o
Receiver Data Register Full (Bit 3)
PE
This bit goes to a 1 when the ACIA transfers data from the Receiver
Shift Register to the Receiver Data Register, and goes to a 0 (is
cleared) when the processor reads the Receiver Data Register.
Transmitter Data Register Empty (Bit 4)
Data Set Ready (DSR)
DSR low (ready)
DSR high (not ready)
This bit goes to a 1 when the ACIA transfers data from the Transmitter Data Register to the Transmitter Shift Register, and goes
to a 0 (is cleared) when the processor writes new data onto the
Transmitter Data Register.
Data Carrier Detect (DCD)
DCD low (detected)
DCEi high (not detected)
NOTE: There is a delay of approximately y" of a bit time after
TOR becomes empty/full before this flag is updated.
Transmitter Data Register Empty
Not empty
Empty
Data Carrier Detect (Bit 5) and Data Set Ready
(Bit 6)
Receiver Data Register Full
Notfuil
Full
Overrun"
No overrun
Overrun has occurred
Framing Error"
No framing error
Framing error detected
Parity Error"
No parity error
Parity error detected
These bits reflect the levels of the DCD and DSR inputs to the
ACIA. A 0 indicates a low level (true condition) and a 1 indicates
a high level (false). Whenever either of these inputs change state,
an immediate processor interrupt (IRQ) occurs. When the interrupt occurs, the status bits indicate the levels of the inputs immediately after the change of state occurred. Subsequent level changes
will not affect the status bits until after the Status Register has been
interrogated by the processor. At that time, another interrupt will
immediately occur and the status bits will reflect the new input
levels. These bits are not automatically cleared (or reset) by an
internal operation.
Interrupt (Bit 7)
This bit goes to a 1 whenever an interrupt condition occurs and
goes to a 0 (is cleared) when the Status Register is read._
• No interrupt occurs for these conditions
Reset Initialization
2-114
R6551
Asynchronous Communications Interface Adapter (ACIA)
CONTROL REGISTER
Selected Baud Rate (Bits 0, 1, 2, 3)
The Control Register selects the desired baud rate, frequency
source, word length, and the number of stop bits.
These bits select the Transmitter baud rate, which can be at
'/'6 an external clock rate or one of 15 other rates controlled by
the internal baud rate generator.
If the Receiver clock uses the same baud rate as the transmitter,
then RxC becomes an output and can be used to slave other
circuits to the ACIA. Figure 3 shows the Transmitter and Receiver
layout.
Bit 7
0
1
1
Stop Bit Number (SBN)
1 Stop bit
2 Stop bits
1Y2 Stop bits
For WL = 5 and no parity
1 Stop bit
For WL = 8 and parity
Bits 6-5
~ .§..
0
0
0
1
0
Word Length (WL)
No. Bits
8
7
6
5
Bit 4
0
1
Receiver Clock Source (RCS)
External receiver clock
Baud rate
Bits 3-0
Selected Baud Rate (SBR)
J.. .Q.. Baud
0
16x External Clock
0
1
50
0
1
0
75
1
1
109.92
0
134.58
0
0
1
150
1
0
300
1
1
600
0
0
1200
0
1
1800
1
0
2400
1
1
3600
0
0
4800
0
1
7200
0
9600
1
19,200
~
0
0
0
0
0
0
0
0
1
1
1
1
1
1
10
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
...- ....-RxO
....- - - - - - - - _ R x C
1----_TxO
Figure 3.
Receiver Clock Source (Bit 4)
This bit controls the clock source to the Receiver. A 0 causes
the Receiver to operate at a baud rate of '/'6 an external clock.
A 1 causes the Receiver to operate at the same baud rate as
is selected for the transmitter.
Word Length (Bits 5, 6)
Reset Initialization
7654321
Transmitter/Receiver Clock Circuits
These bits determine the word length to be used (5, 6, 7 or 8
bits).
0
I~I~I~I~I~I~I~I~I
Hardware reset (RES)
Stop Bit Number (Bit 7)
Program reset
This bit determines the number of stop bits used. A 0 always
indicates one stop bit. A 1 indicates 1Y2 stop bits if the word
length is 5 with no parity selected, 1 stop bit if the word length
is 8 with parity selected, or 2 stop bits in all other configurations.
2-115
R6551
Asynchronous Communications Interface Adapter (ACIA)
COMMAND REGISTER
Data Terminal Ready (Bit 0)
The Command Register controls specific modes and functions.
This bit enables all selected interrupts and controls the state of
the Oata Terminal Ready (OTR) line. A 0 indicates the microcomputer system is not ready by setting the OTR line high. A
1 indicates the microcomputer system is ready by setting the
OTR line low. OTR also enables and disables the transmitter
and receiver.
Bits 7-6
7
6
o
1
0
o "0
1
Bit 5
o
Bit 4
o
1
Bits 3-2
3
Receiver Interrupt Control (Bit 1)
Parity Mode Control (PMC)
This bit disables the Receiver from generating an interrupt when
set to a 1. The Receiver interrupt is enabled when this bit is set
to a 0 and Bit 0 is set to a 1.
Odd parny transmitted/received
Even parity transmitted/received
Mark parity bit transmitted
Parity check disabled
Space parity bit transmitted
Parity check disabled
Transmitter Interrupt Control (Bits 2, 3)
These bits control the state of the Ready to Send (RTS) line and
the Transmitter interrupt.
Parity Mode Enabled (PME)
Parity mode disabled
No parity bit generated
Parity check disabled
Parny mode enabled
Receiver Echo Mode (Bit 4)
A 1 enables the Receiver Echo Mode and a 0 disables the
Receiver Echo Mode. When bit 4 is a 1 bits 2 and 3 must be
O. In the Receiver Echo Mode, the Transmitter returns each
transmission received by the Receiver delayed by one-half bit
time.
Receiver Echo Mode (REM)
Receiver normal mode
Receiver echo mode
Bits 2 and 3 must also be zero for receiver
echo mode, RTS will be low.
Parity Mode Enable (Bit 5)
This bit enables parity bit generation and checking. A 0 disables
parity bit generation by the Transmitter and parity bit checking
by the Receiver. A 1 bit enables generation and checking of
parity bits.
Transmitter Interrupt Control (TIC)
2
o
0
1
1
0
1
o
1
Bit 1
o
1
Bit 0
o
RTS
RTS
RTS
RTS
= High, transmitter disabled= Low, transmit interrupt enabled
= Low, tansmit interrupt disabled
= Low, transmit interrupt disabled,
transmit break on TxO'-
Parity Mode Control (Bits 6, 7)
These bits determine the type of parity generated by the Transmitter, (even, odd, mark or space) and the type of parity check
done by the Receiver (even, odd, or no check).
Receiver Interrupt Request Disabled (IRD)
IRQ enabled (receiver)
IRQ disabled (receiver)
Reset Initialization
765 432 1 0
Data Terminal Ready (DTR)
Oata terminal not ready (OTR high)Oata terminal ready (OTR low)
1010101010101010
Hardware reset (RES)
-.-.-. 0.0 0.0.0 I .Program
reset
NOTES
-The transmitter is disabled immediately. The receiver is
disabled but will first complete receiving a byte in process of
being received.
_. A break is transmitted only after the end of a character stream.
If the Transmit Data Register contains a character, the break is
not transmitted.
2-116
R6551
Asynchronous Communications Interface Adapter (ACIA)
INTERFACE SIGNALS
Read/Write (R/W)
Figure 4 shows the ACIA interface signals associated with the
microprocessor and the modem.
The RiW input, generated by the microprocessor controls the
direction of data transfers. A high on the RiW pin allows the
processor to read the data supplied by the ACIA, a low allows a
write to the ACIA.
Interrupt Request (IRQ)
CTS
The IRQ pin is an interrupt output from the interrupt control logic.
It is an open drain output, permitting several devices to be connected to the commmon IRQ microprocessor input. Normally a
high level, IRQ goes low when an interrupt occurs.
TxO
iiffi
iiCD
RiW
cso
CSt
Data Bus (00-07)
OSR
RxC
RSO
The eight data line (00-07) pins transfer data between the processor and the ACIA. These lines are bi-directional and are normally high-impedance except during Read cycles when the ACIA
is selected.
XTLI
XTLO
RSI
,2
OTR
RES
Chip Selects (CSO, CS1)
RTS
vcc
The two chip select inputs are normally connected to the processor address lines either directly or through decoders. The ACIA
is selected when CSO is high and CSl is low. When the ACIA
is selected, the internal registers are addressed in accordance with
the register select lines (RSO, RS1).
RxO
VSS
Register Selects (RSO, RS1)
Figure 4. ACIA Interface Diagram
The two register select lines are normally connected to the processor address lines to allow the processor to select the various
ACIA internal registers. Table 1 shows the internal register select
decoding.
MICROPROCESSOR INTERFACE
Table 1. ACIA Register Selection
Reset (RES)
Register Operation
During system initialization a Iowan the RES input causes a
hardware reset to occur. Upon reset, the Command Register and
the Control Register are cleared (all bits set to 0). The Status
Register is cleared with the exception of the indications of Data
Set Ready and Data Carrier Detect, which are externally controlled
by the DSR and DCD lines, and the transmitter Empty bit,
which is set. RES must be held low for one 02 cloCk cycle for a
reset to occur.
Input Clock ($2)
RSl
RSO
R/W = Low
L
L
Write Transmit Data
Register
Read Receiver
Data Register
L
H
Programmed Reset
(Data is "Don't
Care")
Read Status
Register
H
L
Write Command
Register
Read Command
Register
H
H
Write Control
Register
Read Control
Register
RIW = High
Only the Command and Control registers can be both read and
written. The programmed Reset operation does not cause any data
transfer, but is used to clear bits 4 through 0 in the Command
register and bit 2 in the Status Register. The Control Register is
unchanged by a programmed Reset. It should be noted that the
p.lQ9fammed Reset is slightly different from the hardware Reset
(RES); refer to the register description.
The input clock is the system 02 clock and clocks all data transfers between the system microprocessor and the ACIA.
NOTE: The specified maximum cycle time for the signal on this
input is 40 I's. This specification must be observed to prevent loss
of data.
2-117
fJ
Asynchronous Communications Interface Adapter (ACIA)
R6551
Clear to Send (CTS)
ACIA/MODEM INTERFACE
The CTS input pin controls the transmitter operation. The enable
state is w~h CTS low. The transmitter is automatically disabled
if CTS is high.
Crystal Pins (XTLI, XTLO)
These pins are normally directly connected to a series mode
external crystal (1.8432 MHz) to derive the various baud rates.
Alternatively, an externally generated clock can drive the XTU pin,
in which case the XTLO pin must float. XTU is the input pin for
the transmit clock.
Data Terminal Ready (DTR)
This output pin indicates the status of the ACIA to the modem.
A low on DTR indicates the ACIA is enabled, a high indicates
it is disabled. The processor controls this pin via bit 0 of the
Command Register.
Transmit Data (TxD)
Data Set Ready (DSR)
The TxD output line transfers serial nonreturn-to-zero (NRZ) data
to the modem. The least significant bit (LSB) of the Transmit Data
Register is the first data bit transmitted and the rate of data transmission is determined by the baud rate selected or by an external
clock. This selection is made by programming the Control Register.
The DSR input pin indicates to the ACIA the status of the
modem. A low indicates the "ready" state and a high, "notready."
Data Carrier Detect (DCD)
The DCD input pin indicates to the ACIA the status of the carrierdetect output of the modem. A low indicates that the modem
carrier signal is present and a high, that it is not.
Receive Data (RxD)
The RxD input line transfers serial NRZ data into the ACIA from
the modem, LSB first. The receiver data rate is determined by the
programmed baud rate or by an externally generated receiver
clock. The selection is made by programming the Control Register.
I
TRANSMITTER AND RECEIVER
OPERATION
Receive Clock (RxC)
Continuous Data Transmit
RxC is a bi-directional pin which is either the receiver 16x clock
input or the receiver 16x clock output. The latter mode results if
the internal baud rate generator is selected for receiver data
clocking.
In the normal operating mode, the interrupt request output (IRQ)
Signals when the ACIA is ready to accept the next data word to
be transmitted. This interrupt occurs at the beginning of the Start
Bit. When the processor reads the Status Register of the ACIA,
the interrupt is cleared.
Request to Send (RTS)
The processor must then identify that the Transmit Data Register is ready to be loaded and must then load it with the next
data word. This must occur before the end of the Stop Bit, otherwise a continuous "MARK" will be transmitted. Figure 5 shows
the continuous Data Transmit timing relationship.
The RTS output.E!!!.. controls the modem from the processor.
The state of the RTS pin is determined by the contents of the
Command Register.
CHAR#n
/
TxD
CHAR#n+1
I
'/
CHAR#n+2
I
'/
I
lSto~5El~~ffislopls",.5YJ~J~E}loplsl"'5El~~
:
:
/
PROCESSOR
INTERRUPT
(TRANSMIT DATA
REGISTER EMPTV,
/LllJ
~
PROCESSOR READS STATUS
REGISTER, CAUSES iifci
TO CLEAR
Figure 5.
PROCESSOR MUST
LOAD NEW DATA
IN THIS TIME
INTERVAL. OTHERWISE,
CONTINUOUS "MARK"
IS TRANSMITTED
Continuous Data Transmit
2-118
'
,
ffislopls. rt5El~~ ffis.o{
:
LlIJ'
'-'\
CHAR#n+3
,/
:
I
UTI
L
R6551
Asynchronous Communications Interface Adapter (ACIA)
Continuous Data Receive
read the data word before the next interrupt, otherwise the
Overrun condition occurs. Figure 6 shows the continuous Data
Receive Timing Relationship.
Similar to the Continuous Data Transmit case, the normal
operation of this mode is to assert IRQ when the ACIA has
received a full data word. This occurs at about 911. point through
the Stop Bit. The processor must read the Status Register and
CHAR#n
CHAR#II+1
RxD
iRa
CHAR#n+3
CHAR#n+2
""lstart5EJ ~ ~!SEJ s,opls,.n5EJ ~ ~ !SEJs,oplstart5EJ ~ ~ !SEJs,oplstart[qBJ ~ ~ ~StopL
'-/
/
I
I
I
I
I
I
I
I
I
I
I
L
'LJlJ
~rn-----;LJIr
~
) '-'\
PROCESSOR
INTERRUPT OCCURS
ABOUT 9/16 INTO
LAST STOP BIT.
PARITV, OVERRUN,
AND FRAMING eRROR
ALSO,UPDATED
'-/
'-/
m
TUS
PROCESSOR READS
~~~I~~!=. CAUSES IRQ
Figure 6.
I
LJI]
PROCESSOR MUST READ
RECEIVER DATA IN THIS
TIME INTERVAL; OTHERWISE.
OVERRUN OCCURS
Continuous Data Receive
Transmit Data Register Not Loaded by Processor
If the processor is unable to load the Transmit Data Register in
the allocated time, then the TxD line goes to the "MARK" condition until the data is loaded. IRQ interrupts continue to occur
at the same rate as previously, except no data is transmitted.
CONTINUOUS "MARK"
CHAR#n
I
TxO
When the processor finally loads new data, a Start Bit imme'
diately occurs, the data word transmission is started, and another
interrupt is initiated, signaling for the next data word. Figure 7
shows the timing relationship for this mode of operation.
/
r-~-'-'-7-------
I
I
CHAR#n+1
RStart5EJ~ ~!SEJStopl
-UIJ'
_CHARACTER_I
TIME
'LlII--
\
~
PRocLoR '-'
""
INTERRUPT
FOR DATA
REGISTER
EMPTY
PROCESSOR
READS
STATUS
REGISTER
/"
INTERRUPTS
CONTINUE AT
CHARACTER RATE,
EVEN THOUGH
NO DATA IS
TRANSMITTED
Figure 7.
WHEN PROCESSOR FINALLY LOADS
NEW DATA, TRANSMISSION STARTS
IMMEDIATELY AND INTERRUPT
OCCURS, INDICATING TRANSMIT
DATA REGISTER EMPTY
Transmit Data RegIster Not Loaded by Processor
2·119
CHAR#n+2
Asynchronous Communications Interface Adapter (ACIA)
R6551
Effect of CTS on Transmitter
CTS is the Clear-to-Send Signal generated by the modem. It is
normally low (true state) but may go high in the event of some
modem problems. When this occurs, the TxD line immediately
goes to the "MARK" condition. Interrupts continue atth!! same
rate, but the Status Register does not indicate that the Transmit
Data Register is empty. Since there is no status bit for CTS, the
processor must deduce that CTS has gone to the FALSE (high)
state. CTS is a transmit control line only, and has no effect on
the R6551 Receiver Operation. Figure 8 shows the timing relationship for this operation.
CONTINUOUS "MARK"
CHAR#n
I
TxD
I
'/
I
r-~-'-r/_----------------------
EI~ IiEJStoPIStart5El~~-..L._.L--t._+_..L._L--t.-!B2
I
LWrn---I---iuu
LJI]
iiiii
l.-- CHARACTER ----...I
I
TIME
I
LlIJ
CLEAR-TO-SEND
NEXT
CTS GOES HIGH,
INDICATING MODEM
IS NOT READY TO
RECEIVE DATA. TxD
PROCESSOR
INTERRUPT
AT NORMAL
START BIT
TIME
PROCESSOFI READS
STATUS REGISTER.
SINCE DATA REGISTER
IS NOT EMPTY, PROCESSOR
MUST DEDUCE THAT
CTS IS SOUnCE OF
INTERRUPT (THIS IS
COVERED ELSEWHERE
IN THIS NOTE).
IMMEDIATELY GOES
TO "MARK" CONDITION
Figure 8.
Effect of CTS on Transmitter'
Effect of Overrun on Receiver
Overrun status bit is sel. Thus, the Data Register will contain the
last valid data word received and all following data is losl. Figure 9
shows the timing relationship for this mode.
If the processor does not read the Receiver data Register in the
allocated time, then, when the next interrupt occurs, the new data
word is not transferred to the Receiver Data Register, but the
CHAR#n.1
CHAR#n
PROCESSOR
INTERRUPT
FOR RECEIVER
DATA REGISTER
FULL
CHAR#n+2
~
PROCESSOR
READS
STATUS
REGISTER
RECEIVER DATA REGISTER
NOT UPDATED, BECAUSE
PROCESSOR DID NOT READ
PREVIOUS DATA, OVERRUN
BIT SET IN STATUS
REGISTER
''-----.----------'/ ~
OVERRUN BIT SET IN
STATUS REGISTER
Figure 9.
Effect of Overrun on Receiver
2·120
CHAR#n+3
Asynchronous Communications Interface Adapter (ACIA)
R6551
Echo Mode Timing
In Echo Mode, the TxD line re-transmits the data on the RxD
line, delayed by '/2 of the bit time, as shown in Figure to.
Figure 10.
Echo Mode Timing
Effect of CTS on Echo Mode Operation
In Echo Mode, the Receiver operation is unaffected by CTS,
however, the Transmitter is affected when CTS goes high, i.e.,
the TxD line immediately goes to a continuous "MARK" condition. In this case, however, the Status Request indicates that
CHAR#n
the Receiver Data Register is full in response to an IRQ, so the
processor has no way of knowing that the Transmitter has
ceased to echo. See Figure 11 for the timing relationship of this
mode.
CHAR#n+1
CHAR#n+2
1r-__-+___
CHAR#n+3
co_N_T_'N_U_oU_S_._.M_A_RKJ.._U_N_TI_L_cr_S_G_J+E_S_L_OW
______________,
TxD
~~~~s'opls''''IBOIB,IB211
I
ILALSE"CONDITION
CTSGOESTO)
~~~~e~RDATA ' - - - - - - - - - - - - - - - - - - - - - - - REGISTER FULL - - - - - - - - - - - - - - '
INTERRUPTS
Figure 11.
Effect of CTS on Echo Mode
2-121
Asynchronous Communications Interface Adapter (ACIA)
R6551
Overrun in Echo Mode
If Overrun occurs in Echo Mode, the Receiver is affected the
same way as a normal overrun in Receive Mode. For the retransmitted data, when overrun occurs, the TxD line goes to the
··MARK" condition until the first Start Bit after the Receiver Data
Register is read by the processor. Figure 12 shows the timing
relationship for this mode.
CHAR11x+1
CHAR#x
!--'-_L--'
I
PROCESSOR
INTERRUPT
FOR RECEIVER
DATA REGISTER
FULL
PROCESSOR FINAlL V
READS RECEIVER
DATA REGISTER,
LAST VALID
CHARACTER (#nJ
PROCESSOR
READS
STATUS
REGISTER
1
~ =~
TxD DATA
RESUMES
PROCESSOR
INTERRUPT
FOR CHAR#x
OVERRUN OCCURS
TxDGOESTO
IN RECEIVER
"MARK"
DATA REGISTER
CONDITION
Figure 12.
Overrun In Echo Mode
Framing Error
Framing Error is caused by the absence of Stop Bit(s) on received
data. A Framing Error is indicated by the setting of bit 1 in the
Status Register at the same time the Receiver Data Register Full
bit is set, also in the Status Register. In response to IRQ,
generated by RDRF, the Status Register can also be checked for
the Framing Error. Subsequent data words are tested for Framing
Error separately, 50 the status bit will always reflect the last data
word received. See Figure 13 for Framing Error timing relationship.
RxD
(EXPECTED) ......" -......--1
RxD
(ACTUAL) - ' _..........
PROCESSOR
NOTES: 1. FRAMING ERROR DOES NOT
INHIBIT RECEIVER OPERATION.
INTERRUPT
FRAMING
ERROR
2. IF NEXT DATA WORD IS OK.
SIT SET
FRAMING ERROR IS CLEARED.
Figure 13.
Framing Error
2-122
R6551
Effect of
Asynchronous Communications Interface Adapter (ACIA)
oeD on Receiver
DCD is a modem output indicating the status of the carrier-frequency-detection circuit of the modem. This line goes high for
a loss of carrier. Normally, when this occurs, the modem will
stop transmitting data some time later. The ACIA asserts IRQ
whenever DCD changes state and indicates this condition via
bit 5 in the Status Register.
Once such a change of state occurs, subsequent transitions will
not cause interrupts or changes in the Status Register until the
first interrupt is serviced. When the Status Register is read by
the processor, the ACIA automatically Checks the level of the
DCD line, and if it has changed, another IRQ occurs (see Figure
14).
CONTINUOUS "MARK"
,
I
III
L._....I ....
NORMAL
INTERRUPT
t
NO INTERRUPT
AS LONG AS
OCD1SHIGH,
PROCESSOR
PROCESSOR
INTERRUPT
FOR
6Co
GOING HIGH
Figure 14.
NO FURTHER
PROCESSOR
INTERRUPTS
FOR RECEIVER
WILL OCCUR
FOR oeD
GOING LOW
INTERRUPT
WILL OCCUR
HERE. SINCE
RECEIVER IS NOT
ENABLED UNTIL
FIRST START BIT
DETECTED
PROCESSOR /
INTERRUPT
FOR
RECEIVER
DATA
Effect of OeD on Receiver
Timing with 1Y2 Stop Bits
It is possible to select 1V2 Stop Bits, but this occurs only for
5-bit data words with no parity bit. In this case, the IRQ asserted
for Receiver Data Register Full occurs halfway through the
trailing half-Stop Bit. Figure 15 shows the timing relationship for
this mode.
CHAR#n
CHAR#n+1
I
I
RxD
U
i
PROCESSOR INTERRUPT
OCCURS HALFWAY
THROUGHT THE 1/2
STOP BIT
Figure 15.
Timing with 1112 Stop Bits
2-123
R6551
Asynchronous Communications Interface Adapter (ACIA)
Transmit Continuous "BREAK"
This mode is selected via the ACIA Command Register and
causes the Transmitter to send continuous "BREAK" characters, beginning with the next character transmitted. At least one
full "BREAK" character will be transmitted, even if the processor
quickly re-programs the Command Register transmit mode.
Later, when the Command Register is programmed back to
normal transmit mode, an immediate Stop Bit will be generated
and transmission will resume. Figure 16 shows the timing relationship for this mode.
Note
If, while operating in the Transmit Continuous "BREAK"
mode, the CTS should go to a high, the TxD will be
overridden by the CTS and will go to continuous "MARK"
at the beginning of the next character transmitted after the
CTS goes high.
~,
PERIOD DURING
WHICH PROCESSOR
1 - - - - - - - - 1 - SELECTS
CONTINUOUS
"BREAK" MODE
NORMAL
INTERRUPT
POINT AT WHICH
PROCESSOR
PROCESSOR
INTERRUPT
SELECTS
NORMAL
TRANSMIT
TO LOAD
TRANSMIT
OATA
/
MODE
Figure 16. Transmit Continuous "BREAK"
Receive Continuous "BREAK"
In the event the modem transmits continuous "BREAK" characters, the ACIA will terminate receiving. Reception will resume
only after a Stop Bit is encountered by the ACIA. Figure 17
-------~"
RxD
shows the timing
characters.
CONTINUOUS ".REAK··
relationship
for continuous "BREAK"
"/r----
/
]~~[J9o:JTlst.,.,.t'.-.-O-'-·-'----I-·-N--P_'_Ltt-I.,-.
. . . .--'rrSt.rtroEJ--ffiTISt. tl.o I·, I
jU
rna
PROCESSOR
~TRERRUPT
1
l-MNOOOR~E ~NOINTERRUPT L I
PROCESSOR INTERRUPT WITH INTERRUPTS
~~:~~~R~:E~~ !~~L ALSO
RECEIVE R
DATA REGISTER
GIVE A PARITY eRROR BECAUSE
ALL ZEROS (CONTINUOUS BREAK)
FULL
REPRESENT EVEN PARITY,
SINCE REceiVER
~::~~~~~~I~I
Figure 17. Receive Continuous "BREAK"
2-124
~~~I~~~R
INTERRUPT
R6551
Asynchronous Communications Interface Adapter (ACIA)
STATUS REGISTER OPERATION
3. Receiver and transmitter interrupts are disabled immediately.
If IRQ is low when the reset occurs, it stays low until serviced,
unless interrupt was caused by DCD or DSR transition.
Because of the special functions of the various status bits, there
is a suggested sequence for checking them. When an interrupt
occurs, the ACIA should be interrogated, as follows:
4. DCD and DSR interrupts are disabled immediately. If IRQ
is low and was caused by DCD or DSR, then it goes high,
also DCD and DSR status bits subsequently will follow the
input lines, although no interrupt will occur.
1. Read Status Register
This operation automatically clears Bit 7 (IRQ). Subsequent
transitions on DSR and DCD will cause another interrupt.
5. Overrun cleared, if set.
2. Check IRQ (Bit 7) in the data read from the Status Register
MISCELLANEOUS
If not set, the interrupt source is not the ACIA.
3. Check DCD and DSR
1. If Echo Mode is selected, RTS goes low.
These must be compared to their previous levels, which must
have been saved by the processor. If they are both 0 (modem
"on-line") and they are unchanged then the remaining bits must
be checked.
2. If Bit 0 of Command Register (DTR) is 0 (disabled), then:
a) All interrupts are disabled, including those caused by
DCD and DSR transitions.
b) Transmitter is disabled immediately.
c) Receiver is disabled, but a character currently being
received will be completed first.
4. Check RDRF (Bit 3)
Check for Receiver Data Register Full.
3. Odd parity occurs when the sum of all the 1 bits in the data word
(including the parity bit) is odd.
5. Check Parity, Overrun, and Framing Error (Bits 0-2) if the
Receiver Data Register is full.
4. In the receive mode, the received parity bit does not go into the
Receiver Data Register, but generates parity error or no parity
error for the Status Register.
6. Check TDRE (Bit 4)
Check for Transmitter Data Register Empty.
5. Transmitter and Receiver may be in full operation simultaneously. This is "full-duplex" mode.
7. If none of the above conditions exist, then CTS must have
gone to the false (high) state.
·6. lithe RxD line inadvertently goes low and then high right after
a Stop Bit, the ACIA does not interpret this as a Start Bit, but
samples the line again halfway into the bit time to determine
if it is a true Start Bit or a false one. For false Start Bit detection, the ACIA does not begin to receive data, instead, only a
true Start Bit initiates receiver operation.
PROGRAM RESET OPERATION
A program reset occurs when the processor performs a write operation to the ACIA with RSIl-Iow and RS1 high. The program reset
operates somewhat different from the hardware reset (RES pin)
and is described as follows:
7. DCD andd DSR transitions, although causing immediate
processor interrupts, have no affect on transmitter operation.
Data will continue to be sent, unless the processor forces transmitter to turn off. Since these are high-impedance inputs, they
must not be permitted to float (un-connected). If unused, they
must be terminated to GND.
1. Internal registers are not completely cleared. Check register
formats for the effect of a program reset on internal registers.
2. The DTR line goes high immediately.
2-125
Asynchronous Communications Interface Adapter (ACIA)
R6551
CRYSTAL/CLOCK CONSIDERATIONS
CLOCK OSCILLATOR
EXTERNAL CLOCK
The on-chip oscillator is designed for a series resonant crystal connected between XTLI and XTLO pins (Figure 18).
The XTLI input may be used as an external clock input (Figure 19).
For this implementation, a times 16 clock is input on XTLI and
XTLO is left open.
A series resonant crystal is specified by the series resistance (R,)
at its series resonant frequenby. For proper oscillator operation,
the selected series resonant crystal should have a series
resistance less than 400 ohms.
EXTERNAL
TRANSMITTER
CLOCK
R6551
R6551
NO CONNECTION
Figure 18. Internal Clock Connection
Figure 19. External Clock Connection
GENERATING NON-STANDARD BAUD RATES
BAUD RATE GENERATION
By using a different crystal, non-standard baud rates may be
generated. These can be determined by:
DIVISORS
Baud Rate =
The internal counter/divider circuit generates appropriate
divisors to produce standard baud rates when a 1.8432 MHz crystal
is connected between XTLI and XTLO. Control Register bits 0-3
select the divisor for a particular bit rate as shown in Table 2.
Crystal Frequency
Divisor
.
Furthermore, it is possible to drive the ACIA with an off-chip
oscillator to achieve other baud rates. In this case, XTALI (pin 6)
must be the clock input and XTALO (pin 7) must be a no-connect.
Table 2. Divisor Selection
Control
Register
Bits
3
,
Divisor Selected
For The
Internal Counter
Baud Rate Generated
With 1.8432 MHz
Crystal
Baud Rate Generated
With a Crystal
of Frequency (F)
16 x External Clock at Pin RxC
16 x External Clock at Pin RxC
2 1 0
0 0 0 0
No Divisor Selected
0 0 0 1
36,864
1.8432 x 10' I 36,864
F 136,864
0 0 1 0
24,576
1.8432 x
F 124,576
0 0 1 1
16,769
1.8432 x
0 1 0 0
13,704
1.8432 x
0 1 0 1
12,288
1.8432 x
0 1 1 0
6,144
1.8432 x
0 1 1 1
3,072
1.8432 x
1 0 0 0
1,536
1.8432 x 10' 11,536 = 1,200
F 11,536
1 0 0 1
1,024
1.8432 x 10'/1,024 = 1,800
F 11,024
1 0 1 0
768
1.8432 x 10'1 768
= 2,400
F 1768
1 0 1 1
512
1.8432 x 10'/512 = 3,600
F 1512
1 1 0 0
384
1.8432 x 10'/384 = 4,800
F 1384
1 1 0 1
256
1.8432 x 10'/256
F 1256
1 1 1 0
192
1.8432 x
F 1192
1 1 1 1
96
1.8432 x
= 7,200
10' 1192 = 9,600
10'/96 = 19,200
2-t26
= 50
10' I 24,576 = 75
10'/16,769 = 109.92
10'/13,704 = 134.51
10'112,288 = 150
10'/6,144 = 300
10'/3,072 = 600
F 116,769
F 113,704
F 112,288
F 16,144
F 13,072
F 196
R6551
Asynchronous Communications Interface Adapter (ACIA)
DIAGNOSTIC LOOP·BACK
OPERATING MODES
3. Connects transmitter outputs to respective receiver inputs (i.e.
TxD to AxD, DTA to DCD, ATS to CTS).
A simplified block diagram for a system incorporating an ACIA is
shown in Figure 20.
LLB may be tied to a peripheral control pin (from an A6520 or
A6522, for example) to provide processor control of local loop-back
operation. In this way, the processor can easily perform local loopback diagnostic testing.
It may be desirable to include in the system a facility for local loopback testing.
In loop-back testing from the point of view of the processor, the
Modem and Data Link must be effectively disconnected and the
ACIA transmitter connected back to its own receiver, so that the
processor can perform diagnostic checks on the system, excluding
the actual data channel.
The ACIA does not contain automatic loop-back operating modes,
but they may be implemented with the addition of a small amount
of external circuitry. Figure 21 indicates the necessary logic to be
used with the ACIA. The LLB line is the positive-true signal to
enable local loop-back operation. Essentially, LLB = high does
the following:
TO DATA LINK
1. Disables outputs TxD, DTA, and ATS (to Modem).
2. Disables outputs AxD, DCD, CTS, DSA (from Modem).
I
Figure 20.
R6551
ill
OTR TxO
RxD
LLB
-::r.
-
4Y
74151
'A
2A
3B
3A
48
4A
F
+5
DTR
RTS
r-
74151
,B
t:=-
CTS
DSR
MODEM
3Y
4Y
RxO
OCD
TxD
1Y
2Y
STB
I
3Y
STB
'B
2B
.,r-
DCD ffi i5"S'Fi
;~~
SEL
SEL
Simplified System Diagram
2B
'A
2A
3B
3A
4B
4A
NOTES:
" HIGH ON LLD SELECTS LOCAL LOOP·BACK MODE.
2. HIGH ON 74157 SELECT INPUT GATES "0" INPUTS
TO "V" OUTPUTS; LOW GATES "A" TO "Y",
r-
'----
Figure 21.
Loop-Sack Circuit Schematic
2-127
Asynchronous Communications Interface Adapter (ACIA)
R6551
READ TIMING DIAGRAM
Timing diagrams for transmit with external clock, receive with
external clock, and IRQ generation are shown in Figures 22, 23
and 24, respectively. The corresponding timing characteristics are
listed in the Table 3.
Table 3.
XTLI
(TRANSMIT
CLOCK INPUT)
Transmit/Receive Characteristics
1 MHz
Characteristic
2 MHz
TxO
Symbol
Min
Max
Min
Max
Unit
TransmiUReceive
Clock Rale
Iccy
400*
-
400*
-
ns
TransmiUReceive
Clock High TIme
tCH
175
-
175
-
ns
tel
175
-
175
-
ns
500
-
500
ns
500
-
SOD
ns
500
-
500
ns
130
30
-
130
30
pF
pF
TransmiURecelve
Clock Low Time
)(TUto TxD
Propagation Delay
too
RTS Propagation
Delay
IDLY
IRQ Propagation
Delay (Clear)
tlAQ
Load Capacitance
DTR,RTS
TxD
Cl
-
NOTE: TxO rate is 1/16 TxC rate
Figure 22.
Transmit Timing with External Clock
RxC
/lNPUTI
NOTE: RxO rat. is 1/16 RxC rate
Figure 23.
-
-
\
Notes:
(tA' tF = 10 to 30 ns)
*The baud rale with external clocking is: Baud Rale =
Receive External Clock Timing
__
1_
16 x teCY
r--
iffii. iffi _ _ _ _ _ _ _ _+----I) -
IRQ
(CLEAR)
Figure 24.
2-128
~.'"Q!-Interrupt and Output Timing
Asynchronous Communications Interface Adapter (ACIA)
R6551
AC CHARACTERISTICS
(Vee = 5.0V ± 5%, Vss = 0, TA = T, to TH, unless otherwise noted)
1 MHz
Parameter
Symbol
Min
Cycle Time
tCYC
02 Pulse Width
tc
400
Address Set-Up Time
tACW ' tACR
Address Hold Time
tCAH ' tCAR
R/W Set-Up Time
twcw , tWCR
R/W Hold Time
tCWH
0
Data Bus Set-Up Time
locw
150
Data Bus Hold Time
IHw
Read Access Time (Valid Data)
2 MHz
Max
Min
40
1.0
Max
40
0.5
Unit
ILs
200
-
ns
120
-
70
-
ns
0
-
0
-
ns
70
-
ns
0
-
ns
60
-
ns
20
-
20
-
ns
ICOR
-
200
-
150
ns
Read Hold Time
tHR
20
-
20
-
ns
Bus Active Time (Invalid Data)
tCOA
40
-
40
-
ns
120
Notes: 1. IR and tF = 10 to 30 ns.
2. 00-07 load capacitance = 130 pF.
3. Timing measurements are referenced tolfrom a low of O.B volts and a high of 2.0 volts.
tR te
I
~
....,
<1>2
J
tc c
I-tF
1
I-tCAH-
-tACWeso, CS1, RSO, RS1
c-twew-
I--tewH-1
\
RiW
!
VfH
VIL
~~~~~~~~~~~~~ r--~
__t_D_C_W_________tH_W____~VIH
DATABUS_
_ _
F----------~
VIL
Write Timing Diagram
VIH
\
I
<1>2
VIL
-tACR-
I-tCAR·
VfH
CSO, CS1, RSO, RS1
/
VIL
-tWCR-tCDR-
-teDA-~
DATA BUS
~
Read Timing Diagram
2-129
I-tHR-
D
I
R6551
Asynchronous Communications Interface Adapter (ACIA)
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Supply Voltage
Vee
-0.3 to +7.0
Vdc
Value
,Unit
Inpul Voltage
V ,N
-0.3 to Vee
Vdc
Output Voltage
VOUT
-0.3 to Vee
Vde
Operating Temperature
TA
Storage Temperature
T STG
o to +70
"NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in other sections of this document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
·C
·C
-55 to +150
OPERATING CONDITIONS
Parameter
Symbol
Value
Supply Voltage
Vee
5V ±5%
Temperature Range
Commercial
Industrial
TA
O· to 70·C
- 40·C to + 85·C
DC CHARACTERISTICS
(Vec
= 5.0V +-
5%, Vss
= 0,
TA
= TL to TH,
unless otherwise noted)
Parameter
Symbol
Input High Voltage
Except XTU and XTLO
XTLI and XTLO
V,H
Input Low Voltage
Except XTU and XTLO
XTLI and XTLO
V,L
Min
Typ
2.0
2.4
-
liN
-
Input Leakage Current for High Impedance (Three State 011)
00-07
iTS'
-
-
Output High Voltage _ _ _
00-07, TxO, AxC, RTS, OTR
VOH
2.4
-
Output Low Voltage _ _ _ _
00-07, TxO, AxC, RTS, OTR, IRQ
VOL
-
-
Output High Current (Sourcing)
00-07, TxO, AxC, RTS, OTR
10H
-100
-
Output Low Current (Sinkil!ID- _
00-07, TxO, AxC, RTS, OTR, IRQ
10L
1.6
Output Leakage Current (off state)
IRQ
10FF
Clock Capacitance
(1ot2)
CeLK
Input Capacitance
except 02, XTLI, XTLO
C'N
Output Capacitance
COUT
-
-
Power Dissipation
Po
-
170
Vss
Vss
i5C5,
OSR
2-130
Test Conditions
Unit
V
-
Input Le~age Current
1ot2, R/W, RES, CSO, CS1, RSO, RS1, CTS, RxO,
Max
Vee
Vee
V
0.8
0.4
2.5
pA
V,N = OVto 5V
Vee = OV
±10.0
pA
V'N = O.4V to 2.4V
Vee = 5.25V
V
ILOAD = -100 pA
Vee = 4.75V
V
Vee = 4.75V
ILOAD = 1.6 mA
-
/LA
VOH
= 2.4V
-
-
mA
VOL
= O.4V
-
-
10.0
pA
VOUT
-
-
20
pF
-
10
pF
10
pF
TA
mW
TA
0.4
Vcc
300
= 5V
= 51/
V ,N = OV
1=1 MHz
= 25·C
= O·C
R6551
Asynchronous Communications Interface Adapter (ACIA)
PACKAGE DIMENSIONS
28-PIN CERAMIC DIP
28-PIN PLASTIC DIP
I
~~~~nT~~Tn~~
(.5501
(.115)
:::::---~I
~R' ,m,
~ !1!."!
J..-- (.&201
1.0081
I
1.5901----1
1.0901
11.470)
1-~--I""OI-'~r:~1-""
-1 ~ ~j~t~~::::: :JE:.j~ ~I-~~::::---l
u
(.0851
(.0851
1.1551 (.0651
i:ii51
1.1601
1.0151
2-131
1.0081
~I .032 REF. (,1101
(.0151
(.0901
(.1501 (.0601
(.1251 (.0201
EI
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Section 3
8-Bit Microcomputers
Page
Product Family Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2
R65C10 One-Chip Microcomputer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3
R6500/1 One-Chip Microcomputer..........................................
3-26
R6500/1 E Microprocessor Emulator Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3-49
R6500/1 EB Backpack Emulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3-57
R6500/11 , 112 and 115 One-Chip Microcomputers . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3-63
R65/11 EB Backpack Emulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3-98
R6501 One-Chip Microprocessor ............................................ 3-103
R6511Q One-Chip Microprocessor and R6500/13 One-Chip Microcomputer ......... 3-138
R6518 One-Chip Microprocessor ............................................ 3-173
R65F11 and R65F12 FORTH Based Microcomputers ........................... 3-203
R65FRx FORTH Development and Kernel ROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-235
3-1
CMOS and NMOS 8-Bit Microcomputers
Highest Industry Performers
channels, bit manipulation instructions, expansion bus,
multiple bus interfaces, directly executable RAM with low
power standby, and multiple interrupts - all from a single
5V power supply. They are also available in ROM-less
versions, for large memory system applications and for
developing and simulating products in prototype, with
external memory.
And, the R65Fli and R65F12 even have all system
software on the chip, including an operating system and
high-level FORTH language. It is an extremely versatile
microcomputer, and is available in three configurations to
accommodate application programs to 48K.
The R6500 single-chip CMOS and NMOS microcomputers
provide high-speed and low CMOS power while being
completely software compatible with the 8-bit multi-chip
family. They let you move easily from a multi-chip to a
single-chip solution when the application warrants. They
also function as intelligent peripheral controllers. The R65Cl0,
a CMOS version of the R6500/1, combines the low power of
CMOS with advanced pipelining architecture to provide an
efficient high-speed single-chip system solution.
Features of the microcomputer family include 1.5K to
4K bytes of ROM, 64 to 192 bytes of RAM, 23 to 56 I/O
ports, multiple use counter/timers, serial communication
FEATURE/MODELS
R6500/1
R6500/11
R6500112
R6500113
R6500/15
R65Cl0
•
•
•
•
•
•
•
•
1000n9
2K
64
32
1000n6
3K
192
32
USART
TWO
16K
1000n6
3K
192
56
USART
TWO
16K
1000ns
256
192
32
USART
TWO
65K
1000n6
4K
192
32
UART
TWO
16K
500ns
2K
64
32
6
4
800
1240 DIP
44 PLCC
6
4
800
1264 QUIP
68 PLCC
6
4
800
1264 QUIP
68PLCC
6
4
800
1240 DIP
44 PLCC
5
1
40
12
40 DIP
44PLCC
INSTRUCTION SPEED
ROM (x8)
RAM (x8)
I/O LINES
SERIAL COMM.
16-BIT COUNTERS
EXPANSION BUS
INTERRUPTS
- EXTERNAL
-INTERNAL
• OPERATING POWER (mW)
• STANDBY (mW)
• PACKAGE
ONE
5
1
750
3540 DIP
44 PLCC
- Standby RAM
Rockwell Microcomputers
3-2
ONE
R65C10
'1'
R65C10
One-Chip Microcomputer
Rockwell
SECTION I
INTRODUCTION
SUMMARY
FEATURES
The Rockwell R65C10 microcomputer is a complete 8-bit computer fabricated on a single chip using an N-well silicon gate
CMOS process. The R65C10 complements an industry standard
line of R6500 and R65COO microprocessors, R6500/" and
R65COO/" microcomputers and compatible peripheral devices.
The R65Cl0 has a wide range of microcomputer applications
where high 8-bit performance, minimal chip count and low power
consumption is required.
• Single-chip microcomputer
• R6502 CPU instruction compatible
• 8-bit parallel processing
• Decimal or binary arithmetic
• Variable length stack
• True indexing capability
The R65C10 consists of a 6502 Central Processing Unit (CPU),
2048 bytes of mask programmable Read Only Memory (ROM),
64 bytes of Random Access Memory (RAM) and interface circuitry for peripheral devices. The parallel interface consists of
four 8-bit ports including two edge detect lines. A 16-bit
counter/timer with four selectable modes is also included.
• 13 addressing modes
• Internal 1 MHz to 4 MHz clock with crystal or clock input
- Internal divide-by-2 network
- 2 MHz to 8 MHz crystal input
- 20 kHz to 8 MHz clock input
The innovative architecture and the demonstrated high performance of the R65C02 CPU, as well as instruction simplicity,
result in system cost-effectiveness and a wide range of computational power. These features make the R65Cl0 a leading
candidate for low-power single-chip microcomputer applications.
• Software-controllable prescaler
- Selectable system clock and timer clock prescaler or timer
clock only prescaler
- Divide by 8, 32, 64, or 128 options
Hardware enhancements of the R65C10 include a softwarecontrolled system and/or counter/timer clock prescaler, and an
ultra-low-power Stop mode.
• 15 mW to 60 mW operating power (1 MHz to 4 MHz)
This description assumes that the reader is familiar with the
R6502 CPU programming capabilities as described in the R6500
Programming Manual (Order No. 202).
• 64 x 8 RAM on-chip
• Low-power oscillator Stop mode (cleared by RES)
• 2K x 8 ROM on-Chip
• 32 bidirectional TTL compatible I/O lines
- 1 positive edge-sensitive I/O line
- 1 negative edge-sensitive 110 line
ORDERING INFORMATION
t
R65C1D
-
• 1 bidirectional TTL compatible counter I/O line
Temperature Range
No letter =
DOC to + 7DoC
E = -4DoC to +B5°C
Operating Frequency (Internal
1 = 1 MHz
2 = 2 MHz
3 = 3 MHz
4 = 4 MHz
• 16-bit buffered timer/counter with four modes
- Interval timer
- Pulse generator
- Event counter
- Pulse width measurement
02 clock)
• Three maskable interrupt requests (IRQ)
- 1 counter overflow
- 2 I/O edge detect
Package
C = 40-pin CERDIP
P = 40-pin Plastic DIP
J = 44-pin Plastic Leaded
Chip Carrier (PLCC)
•
• Available in 40-pin DIP and 44-pin PLCC packages
•
Document No. 29651N93
NMI and RES inputs
+51/ ± 10% power
Product Description
3-3
Order No. 2193
Rev. 1, June 1987
One-Chip Microcomputer
R65C10
SECTION 2
INTERFACE DESCRIPTION
identified in Figure 2-2. The function of each pin of the R65C10
is explained in Table 2-1.
This section describes the interface requirements for the R65C1 0
single-chip microcomputer. An interface diagram for the R65C10
is shown in Figure 2-1. The R65C10 pin assignments are
Figure 2-1.
R65C10 Interface Diagram
0_
Vee
NMI
PD7
PD6
RES
PAD
PDS
PAl
PD4
PA2
PD3
PD2
PA3
PA4
POI
POD
PAS
XTLI
PA7
NC
XTLO
Vee
CNTR
PAS
u u u
=u~~8cS8
a.a.a.>Z)()(a.a.a.a.
~
~
~
~
IN _
:
~
~
;
~
0
PC4
pea
PIN 1
INDICATOR
PC2
PCl
PCD
39
PD4
36
37
3&
PDS
PD6
PD7
35
Vee
34
NMI
RES
V..
PBD
PB7
33
32
PC7
PBl
PBS
31
PAD
Pes
PB2
PAl
PCS
PB3
PBS
PB4
30
29
PA2
PC4
pea
PB4
PBS
PC2
PB6
PCl
PB7
PCD
CNTR
m
_
~
CO)
IN ,.. CI (J
_
_
IN M ~ ~ ~ ~ m
IN IN
N IN N N N IN IN
0
u,...
CD in "II'
40-PIN DIP
44-Pin PLCC
NC • NO INTERNAL CONNECTION
Figure 2-2.
c")
ffffZ~~::f::f
R65C10 Pin Assignments
3-4
NC
R65C10
One-Chip Microcomputer
Table 2-1.
Signal Name
R65C10 Pin Description
I/O
Description
POWER. + 5 Vdc; must be connected to both pins.
Vee
GROUND. Signal return and power ground (OV).
Vss
XTLI
I
CRYSTAL INPUT. The crystal or external clock input to the internal clock oscillator. The oscillator generates the internal
master clock at the frequency of the input crystal/clock divided either by 1 or by 2 depending upon mask option. The
system and counter/timer clocks are derived from the master clock under control of the Prescaler Control Register.
XTLO
0
CRYSTAL OUTPUT. The crystal output from the internal clock oscillator. XTLO should be left open when a clock is input
at XTLI.
RES
I
RESET. The active low RES input initializes the R65C10. This signal must not transition from low to high for at least
eight cycles after Vee reaches operating range and the internal oscillator has stabilized.
NMI
I
NON·MASKABLE INTERRUPT. A negative-going edge on the NMI input interrupts the CPU.
PAO-PA7
I/O
PORT A. General purpose I/O Port A.
PBD-PB7
I/O
PORT B. General purpose I/O Port B.
PCO-PC7
I/O
PORT C. General purpose I/O Port C.
PDO-PD7
I/O
PORT D. General purpose I/O Port D.
Four a-bit ports used for either input or output. Each line consists of an active transistor to Vss and an optional active
pull-up to Vee (see Section 4.3). The two lower bits of the Port A (PAD and PA1) also serve as edge-detect inputs with
maskable interrupts. PAD detects a positive-going edge and PA 1 detects a negative-going edge.
CNTR
I/O
COUNTER. This line is either an input to. or an output from, the counter. CNTR is an input in the event counter and
pulse width measurement modes, and is an output in the pulse generator modes. It consists of an active transistor to
Vss and an optional active pull-up to Vee.
3-5
One-Chip Microcomputer
R65C10
SECTION 3
SYSTEM ARCHITECTURE
memory, the lower (least significant) byte of the Program Counter
(PCl) is placed on the eight low-order lines of the internal
address bus and the higher (most significant) byte of the Program Counter (PCH) is placed on the four high-order lines of
the internal address bus. The Program Counter is incremented
each time an instruction or data is fetched from program
memory.
This section provides a functional description of the R65C10.
A block diagram of the R65C10 is presented in Figure 3-1.
3.1 INDEX REGISTERS
There are two S-bit index registers: X and Y. Either index register
can be used as a base to modify the program counter contents
and thus obtain a new address-the sum of the program counter
contents and the index register contents.
3.6 INSTRUCTION REGISTER AND
INSTRUCTION DECODE
When executing an instruction which specifies indexed
addressing, the CPU fetches the op code and the address, and
modifies the address from memory by adding the index register
to it prior to loading or storing the value of memory.
Instructions are fetched from ROM or RAM and gated onto the
internal data bus. These instructions are latched into the
Instruction Register, then decoded along with timing and
interrupt signals to generate control signals for the various
registers.
3.2 STACK POINTER
The Stack Pointer is an S-bit register. It is automatically incremented and decremented under control of the CPU to perform
stack manipulation in response to program instructions, the NMI
interrupt input or the internally generated IRQ interrupt. The
Stack Pointer must be initialized by the user program. The JSR,
BRK, RTI, and RTS instructions use the stack and the Stack
Pointer. The stack is located in RAM from address 0 to address
$3F (0 to 63 decimal).
3.7 PROCESSOR STATUS REGISTER (PSR)
The 8-bit Processor Status Register, shown in Figure 3-2, contains seven status flags. Some of these flags are controlled by
the user program; others may be controlled both by the user
program and the CPU. The R65C10 instruction set contains a
number of conditional branch instructions which allow testing
of these flags. Each of the seven processor status flags is
described in the following paragraphs.
3.3 ARITHMETIC AND LOGIC UNIT (AW)
All arithmetic and logic operations take place in the AlU,
including incrementing and decrementing internal registers
(except the Program Counter). The AlU cannot store data for
more than one cycle. If data is placed on the inputs to the AlU
at the beginning of a cycle, the result is always gated into one
of the storage registers or to memory during the next cycle.
CARRY (C) BIT
The Carry (C) bit can be considered as the ninth bit of an
arithmetic operation. It is set to logic 1 if a carry from the eighth
bit has occurred, or cleared to logic 0 of no carry occurred, as
the result of arithmetic operations.
Each bit of the AlU has two inputs. These inputs can be tied
to various internal buses or to a logic 0; the AlU then generates
the function (AND, OR, SUM, and so on) using the data on the
two inputs.
The Carry bit may be set or cleared under program control by
use of the Set Carry (SEC) or Clear Carry (ClC) instruction,
respectively. Other operations which affect the Carry bit are ADC,
ASL, CMP, CPX, CPY, LSR, PlP, ROL, ROR, RTI, and SBC.
3.4 ACCUMULATOR
ZERO (Z) BIT
The Accumulator is a general purpose 8-bit register that stores
the results of most arithmetic and logic operations. In addition,
the Accumulator usually contains one of the two data words used
in these operations.
The Zero (Z) bit is set to logic 1 by the CPU during any data
movement or by any calculation which sets all eight bits of the
result to zero. This bit is cleared to logic 0 when the resultant
eight bits of a data movement or calculation operation are not
all zero. The R65C10 instruction set contains no instruction to
specifically set or clear the Zero bit. The Zero bit is, however,
affected by the following instructions: ADC, AND, ASL, BIT,
CMP, CPX, CPY, DEC, DEX, DEY, EOR, INC, INX, INY, LOA,
LDX, LDY, LSR, ORA, PLA, PLP, ROL, ROR, RTI, SBC, TAX,
TAY, TXA, TSX, and TVA.
3.5 PROGRAM COUNTER
The 12-bit Program Counter provides the addresses that step
the processor through sequential instructions in a program. Each
time the processor fetches an instruction from the program
3-6
::Jl
Q)
U1
o
.....
o
"TI
cO'
c
~
~
:D
en
't'
'-I
U1
~
0
m
...gc
iii'
ea
iil
3
o::;,
CD
(,
::T
-So
s:
0"
a
n
o
3
"C
c:
S'
~
'I
One-Chip Microcomputer
R65C10
7
654
N
3
D
Bit 7
1
0
Bit 6
1
0
NOT USED
BREAK (B)
Break command
No Break command
Bit 3
1
0
Bit 2
1
0
.!2i1..1
1
0
Bit 0
1
0
C
OVERFLOW (V)'
Overflow set
Overflow cleared
Bit 4
1
z
NEGATIVE (N)'
Negative value
Positive value
Bit 5
0
a decimal adder. When this bit is cleared to logic 0, the adder
operates as a straight binary adder. The adder mode is controlled
only by two instructions. The Set Decimal Mode (SED) instruction sets the 0 bit; the Clear Decimal Mode (CLD) instruction
clears it. The PLP and RTI instructions also affect the Decimal
Mode Bit. The Decimal Mode Bit is cleared upon power application and by RES thus establishing binary mode.
o
2
BREAK (B) BIT
The Break (B) bit indicates the condition which caused the IRQ
service routine to be entered. If the IRQ service routine was
entered because the CPU executed a BRK command, the B bit
will be set to logic 1. If the IRQ routine was entered as the result
of an IRQ occurring, the B bit will be cleared to logic 0. There
are no instructions which can set or clear this bit.
DECIMAL MODE (D)3
Decimal mode selected
Binary mode selected
INTERRUPT DISABLE (1)2
IRQ interrupt disabled
IRQ interrupt enabled
OVERFLOW (V) BIT
ZERO (Z)'
Zero results
Non-zero results
The Overflow (V) bit indicates that the result of a signed, binary
addition or subtraction operation is a value that cannot be
contained in seven bits (-128 :;; n :;; + 127). The indicator only
has meaning when signed arithmetic (sign and seven magnitude
bits) is performed. When the ADC or SBC instruction is
performed, the V bit is set to logic 1 if the polarity of the sign
bit (bit 7) is changed because the result exceeds + 127 or-128;
otherwise the V bit is cleared to logic O. The V bit may also be
cleared under program control by the Clear Overflow (CLV)
instruction.
CARRY(C),
Carry set
Carry cleared
Notes: 1. Not initialized by RES.
2. Set to a 1 by RES.
3. Set to a 0 by power-on.
Figure 3·2.
The Overflow bit may also be used with the BIT instruction. The
BIT instruction, which may be used to sample interface devices,
allows the Overflow bit to reflect the condition of Bit 6 in the
sampled field. During a BIT instruction, the Overflow bit is set
equal to the content of Bit 6 of the data tested with the BIT
instruction. When used in this mode, the Overflow bit has nothing
to do with signed arithmetic, but is just another sense bit for the
CPU. Instructions which affect the V flag are ADC, BIT, CLV,
PLP, RTI, and SBC.
Processor Status Register
INTERRUPT DISABLE (I) BIT
The Interrupt Disable (I) bit controls the servicing of the internal
interrupt request (IRQ). If the I bit is reset to logic 0, the IRQ
will be serviced. If the bit is set to logic 1, the IRQ will be ignored.
The CPU will set the Interrupt Disable bit to logic 1 if NMI, an
enabled IRQ interrupt or the RES signal is detected.
NEGATIVE (N) BIT
The I bit is restored by the Pull Processor Status from Stack
(PLP) instruction, or as the result of executing a Return from
Interrupt (RTI) instruction (provided the Interrupt Disable bit was
cleared prior to the interrupt). The Interrupt Disable bit may be
set or cleared under program control using a Set Interrupt
Disable (SEI) or a Clear Interrupt Disable (CLI) instruction,
respectively.
The Negative (N) bit copies the arithmetic sign bit value resulting
from a data movement or an arithmetic operation. If the sign
bit is set, the resulting value of the data movement or arithmetic
operation is negative and the N bit is a logic 1; if the sign bit
is cleared, the result of the data movement or arithmetic
operation is positive and the N bit is a logic O. There are no
instructions that set or clear the N bit since the N bit represents
only the status of a result. The instructions that affect the
slate of the bit are: ADC, AND, ASL, BIT, CMP, CPX, CPY, DEC,
DEX, DEY, EOR, INC, INX, INY, LDA, LDX, LDY, LSR, ORA,
PLA, PLP, ROL, ROR, RTI, SBC, TAX, TAY, TSX, TXA,
and TYA.
DECIMAL MODE (D) BIT
The Decimal Mode (D) bit controls the arithmetic mode of the
CPU. When this bit is set to a logic 1, the adder operates as
3-8
R65C10
One-Chip Microcomputer
3.S 1/0 ADDRESS DECODE
3.9 2KxS ROM
The internal memory, control registers, I/O ports, and Counter/
Latch are memory mapped into the 4096-byte address space.
The I/O Address Decode logic decodes the address from the
internal address bus and routes enable signals to the appropriate functions. The memory map of the R65Cl0 is shown in
Figure 3-3.
The internal 2,048 x B-bit Read Only Memory (ROM) usually contains the user's program instructions and other fixed constants.
These program instructions and constants are maskprogrammed during fabrication.
The ROM is mapped from $800 to $FFF.
3.10 64 X S RAM
Parameter
IRQ Vector HiQh
IRQ Vector Low
RES Vector High
RES Vector Low
NMI Vector High
NMI Vector Low
Address
Hex
Dec
FFF
FFE
FFD
FFC
FFB
FFA
FF9
4095
4094
4093
4092
4091
4090
4089
800
7FF
2048
2047
The internal 64 x 8-bit Random Access Memory (RAM) contains
the user program stack and is used for scratch pad memory during system operation. This RAM is completely static in operation and requires no clock or dynamic refresh. The data
contained in RAM is read out nondestructively with the same
polarity as the input data. In the event that execution stops, RAM
data is retained until execution resumes.
The R65Cl0 RAM is assigned page zero memory address 0 to
$03F.
R65ClO User Program
Unassigned
Port
Port
Port
Port
0
C
B
A
Direction Register (Write Only)'
Direction RElgister (Write Only)3
Direction Register (Write Only)'
Direction ReQister (Write Only)'
Control Register (CR)
Prescaler Control Register (PCR)
Stop Mode (Write Only)3
Unassigned
Clear PAl Neg Edge Detected (Write Only)'
Clear PAO Pos Edge Detected (Write Only)'
Upper Latch and Transfer Latch to Counter,
Clear Counter Overflow (Write Only)2
Lower Count, Clear Counter Overflow
(Read Only)2
Upper Count (Read Only)
Lower Latch (Write Only)
Upper Latch (Write Only)
Port 0 (PO)
Port C (PC)
Port B (PB)
Port A (PA)
094
093
092
091
090
08F
08E
080
08C
08B
08A
089
148
147
146
145
144
143
142
141
140
139
138
137
088
136
087
135
086
085
084
083
082
081
080
07F
134
133
132
131
130
129
128
127
3.11 CLOCK OSCILLATOR
The Clock Oscillator provides the basic timing signals used by
the R65Cl0. The reference frequency is provided by an external
source and can be from a crystal or clock input. The external
frequency may vary from 2 MHz to 8 MHz for a parallel resonant crystal input or from 20 kHz to 8 MHz for a clock input.
The external clock rate is divided by 2 or 1 to generate an internal master clock (MCLK) as shown in Figure 3-4. Selection of
the input crystal/clock divide-by-2 or divide-by-l is a mask option.
The divide-by-2 option can be used with either a crystal or clock
input. The divide-by-l option can be used only with a clock input.
The divide-by-2 option causes the A65Cl0 to operate at the
same internal frequency as the A6500/1 or R6500/1 E when connected to the same input clock frequency. MCLK may be prescaled by four different values under program control (discussed
below).
The on-chip oscillator is designed for a parallel resonant crystal connected between XTLI and XTLO pins. The equivalent
oscillator circuit is shown in Figure 3-5A.
A parallel resonant crystal is specified by its load capacitance
and series resonant resistance. For proper oscillator operation,
the load capacitance (Cc), series resistance (As) and the crystal resonant frequency (F) must meet the following two relations:
(C + 22) = 2C L
Unassigned
040
03F
64
63
000
0
Rs
-
22
6
Asmax = 2 X 10
where: F is in MHz; C and C L are in pF; A is in ohms.
1. 1/0 command only; i.e., no stored data.
To select a parallel resonant crystal for the oscillator, first select
the load capacitance from a crystal manufacturer's catalog. Next,
calculate Asmax based on F and CL• The selected crystal must
have a Rs less than the Asmax.
2. Clears Counter Overflow - Bit 7 in Control Register.
3. Mask option.
Figure 3-3.
C = 2C L
(FCd 2
User RAM
Notes:
:s
or
R65el0 Memory Map
3-9
One-Chip Microcomputer
R65C10
INTERNAL
SYSTEM
CLOCK
MASK
OPTION
,------. +2
XTLI
1/'\1,--.,
r
1/)1
MCLK
I
PRESCALER
t----t
L.: _...J
OSCILLATOR
XTLO
+1
1AJ---------t----I
A. Internal Clock Circuit Block Diagram
XTLI
MCLK,1/)2
( + 2 OPTION')
MCLK, .2
( + 1 OPTION')
B. Clock Timing Waveforms
NOTE: 1. PRESCALER IN MODE 0
Figure 3-4.
Internal System Clock Timing
3.12 PRESCALER CONTROL
For example, if C L = 30 pF for a 4 MHz parallel resonant crystal, then
'
Clock prescaler mode and value selection is controlled by the
Prescaler Control Register (PCR) at the address $08E (see
Figure 3-6). The prescaler mode (PM) is determined by the value
written to bits 0 and 1. The prescaler value (PV) is determined
by the value written to bits 2 and 3. The system clock (02) and
timer clock (TCLK) rates are determined by the combination of
selected prescaler mode and value. When prescaler mode 0 is
selected, 02 and TCLK both run at the internal master clock
(MCLK) rate regardless of the selected prescaler value. 02 runs
at MCLK in prescaler modes 0 and 1 and at MCLK + PV in
prescaler mode 3. TCLK runs at MCLK in prescaler mode 0 and
at MCLK + PV in prescaler modes 1 and 3. Prescaler mode 2
is illegal and will cause indeterminate operation if selected.
C = (2 x 30) - 22 = 38 pF (Use standard value of 39 pF.)
(Note: C = Total shunt capacitance including that due to board
layout.)
The series resistance of the crystal must be less than
R.max =
2 X 106 = 139 ohms
(4x 30)2
The R65C10 internal oscillator and clock can be stopped under
program control (Stop mode) and restarted by a RES input. The
Stop mode is described in Section 4.
The selected prescaler value is invoked in the cycle following
the write or interrupt occurrence. Waveforms for five of these
operations are'illustrated in Figure 3-7.
3-10
One-Chip Microcomputer
R65C10
7
XTLI
I---X-T-L'O
ADDR
22pF
$08E
I- -' - -i~~J~'
I
o
o
4
5
NOT USED
3
2
VI
VO
o
MI
MO
L-__L-__~__~__~
L ._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Bits 3-2
.Y1.
6
Prescaler Value (PV) Select'
VO
0
1
Prescale Value
Divide by 8
Divide by 32
Divide by 64
Divide by 128
o
A. Crystal Input
Bits 1-0 Prescaler Mode (PM) Select'
Ml
0
0
MO
0
1
0
1
Mode
0
1
2
3
System Clock
(021 Rate
MCLK
MCLK
N/A
MCLK .;. PV
Timer Clock
(ICLKI RaJe
MCLK
MCLK.;. PV
N/A (Illegal Mode)
MCLK.;. PV
Note: 1. All bits are reset to 0 by RES.
Figure 3-6.
Prescaler Control Register
B. Clock Input
Notes:
1. Clock input divide·by·2 option must be selected.
2. Clock input divide·by·2 selected.
3. Clock input divide·by·l selected.
Figure 3-5.
Clock Oscillator Input Options
3.13 CONTROL REGISTER (CR)
The Counter is reset to the Interval Timer mode (Mode 0) byas·
sertion of RES (which causes Os to be loaded into all bits of
the Control Register).
The Control Register (CR), shown in Figure 3-8, is located at
address $8F. The CR contains five control bits and three status
bits. The control bits must be written to the Control Register.
The status bits can be read, along with the previously written
control bits, by reading the register. All control and status bits
in the Control Register are cleared to 0 by the assertion of RES.
The signals controlled by and reported in the CR are described
in the following paragraphs.
PAl INTERRUPT ENABLE BIT (AilE)
If the PAl Interrupt Enable bit (bit 2) is set to a I, IRQ will occur
when the PAl Negative Edge Detected bit (bit 5) is set to a 1.
PAO INTERRUPT ENABLE BIT (AOIE)
Bits 0 to 4 in the Control Register are control bits (Figure 3-8).
The control signals are set by writing a 1 into the respective bit
position, and cleared either by writing a 0 into the respective
bit position or by assertion of RES.
If the PAO Interrupt Enable bit (bit 3) is set to a I, IRQ will occur
when the PAO Positive Edge Detected bit (bit 6) is set to a 1.
Bits 5 to 7 in the Control Register are status bits (Figure 3-8).
The status bits are read-only information. Each status bit is set
to a 1 by monitoring circuitry, and is cleared to a 0 either by writ·
ing to specific address or by assertion of RES.
If the Counter Interrupt Enable Bit (bit 4) is set to a I, IRQ will
occur when Counter Overflow (bit 7) is set to a 1.
COUNTER INTERRUPT ENABLE BIT (CIE)
PAl NEGATIVE EDGE DETECTED BIT (A1ED)
The PAl Negative Edge Detected bit (bit 5) is set to a 1 whenever
a negative (falling) edge is detected on PAl. This bit is cleared
to a 0 by writing to address $08A or by assertion of RES.
COUNTER MODE CONTROL 0 AND 1
Counter Mode Control signals CMCO and CMCI (bits 0 and 1)
control the Counter operating modes. The modes of operation
and the corresponding configuration of CMCO and CMCI are
shown in Figure 3-8. These modes are selected by writing the
appropriate bit values into the Counter Mode Control bits.
The edge detecting circuitry is active regardless of whether PA 1
is an input or is an output. When PAl is used as an output, A1ED
will be set when the negative edge is detected during a high·to·
low transition. When PAl is used as an input and the negative
3·11
D
One-Chip Microcomputer
R65C10
A. CHANGE FROM MODE 0 TO MODE 3 (DIVIDE BY 8) BY WRITING TO PCR
COUNT
='--___
(4-_1_2_)..JX,\.. _ _ _ _ _ _ _ _ _(8~)X'--__
B. CHANGE FROM MODE 3 (DIVIDE BY 8) TO MODE 0 BY WRITING TO PCR
SYSTEM
CLOCK
(M_hJ)X~_ _ _ _ _ _ _ _(~M_h)JX\..______~~_·l~n)~
COUNT _ _ _ _ _ _
C. CHANGE FROM MODE 0 TO MODEl (DIVIDE BY 8) BY WRITING TO PCR
1/12
(8th) X
D. CHANGE FROM MODE 1 (DIVIDE BY 8) TO MODE 1 (DIVIDE BY 32) BY WRITING TO PCR
~~
32nd
1/12
COUNT
~
E. CHANGE FROM MODE 3 (DIVIDE BY 8) TO MODE 1 (DIVIDE BY 8) BY WRITING TO PCR, OR IRQ, OR NMI.
SYSTEM
CLOCK
(8_th~)X~_ _ _ _ _ _ _ _(_M_~JX~______(4-_l_n~)X~_ _ _ _ _ _ _ _ _ _ _ _~
COUNT _______
F. CHANGE FROM MODE 1 (DIVIDE BY 8) TO MODE 3 (DIVIDE BY 8) BY WRITING TO PCR OR BY A RETURN FROM INTERRUPT.
SYSTEM
CLOCK
COUNT
_________~_th~)X~_________________________
(1_1._1/_2)J~~__________________(8_th~)X====
Figure 3·7.
Prescaler Waveform Examples
3·12
One-Chip Microcomputer
R65C10
The CTRO bit should be cleared by the user program upon initialization and upon completion of Counter Overflow IRQ interrupt processing.
I 7 I 6 I 5 I 4 I 3 121 1 I 0
ADDR I INTERRUPT STATUS I INTERRUPT ENABLE I TIMER MODE
$08F ITIMERL PAO I PAl ITIMERI PAO I PAl I CONTROL
Bit 7
1
COUNTER OVERFLOW (CTRO)1
Counter overflow occurred
No counter overflow
Bit 6
1
PAO POSITIVE EDGE DETECT (AOED),
PAO positive edge detected
PAO positive edge not detected
Bit 5
I
PAl NEGATIVE EDGE DETECT (AI ED)'
PAl negative edge detected
PAl negative edge not detected
o
o
o
Bit 4
I
o
PAO INTERRUPT ENABLE (ADlE)'
Enable PAO interrupt
Disable PAO interrupt
Bit 2
PAl INTERRUPT ENABLE (AIlE)'
Enable PAl interrupt
Disable PAl interrupt
I
o
Bit 10
o0
oI
1 0
1 1
3.14 PARALLEL INPUT/OUTPUT PORTS
The R65Cl0 provides four memory-mapped 8-bit Input/Output
(110) ports: PA, PB, PC and PD. All 32 110 lines of the four ports
COUNTER INTERRUPT ENABLE (CIE)2
Enable counter interrupt
Disable counter interrupt
Bit 3
1
o
When a Counter Overflow occurs, the Upper Count (UC) in
address $086, and the lower Count (lC) in address $087, are
loaded with to the values contained in the Upper latch (Ul) in
address $084, and in the lower latch (ll) in address $085,
respectively.
are completely bidirectional. All lines may be used either for input
or output in any combination, i.e., there are no line grouping
or port association restrictions. A mask option is available to
select 110 port operation with or without direction registers.
Table 3-1 lists the I/O port and edge detected bit reset addresses.
Table 3-1.
COUNTER MODE CONTROL (CMCI & CMC2)'
Interval Timer
Pulse Generator
Event Counter
Pulse Width Measurement
Notes: 1. Read only.
2. Read/write.
Figure 3-8.
Control Register
edge detecting circuitry is used, AI ED should be cleared by the
user program upon initialization and upon completion of the PAl
Negative Edge Detected IRQ processing.
I/O Port Addresses
Port/Function
Address
Port A Direction Register (Write Only)
Port B Direction Register (Write Only)
Port C Direction Register (Write Only)
Port D Direction Register (Write Only)
Port A Data Register (Readtwrite)
Port B Data Register (Readtwrite)
Port C Data Register (Readtwrite)
Port D Data Register (Readtwrite)
Clear PAO Positive Edge Detected Bit (Write Only)
Clear PAl Negative Edge Detected Bit (Write Only)
$090
$091
$092
$093
$080
$081
$082
$083
$089
$08A
I/O PORT OPERATION WITHOUT DIRECTION
REGISTERS
If direction registers are not selected, the direction of the 321/0
lines is controlled by writing to the four 8-bit port data registers
located in page zero at addresses $80-$83 (see Figure 3-3). This
arrangement provides quick programming access using simple
2-byte zero page address instructions. I/O handling is simplified since programming of direction registers is not required.
PAD POSITIVE EDGE DETECTED BIT (ADED)
The PAO Positive Edge Detected bit (bit 6) is set to a 1 whenever
a positive (rising) edge is detected on PAO. This bit is cleared
to a 0 by writing to address $089 or by assertion of RES.
The edge detecting circuitry is active regardless of whether PAO
is an input or is an output. When PAO is used as an output, AOED
will be set when the positive edge is detected during a low-tohigh transition. When PAO is used as an input and the positive
edge detecting circuitry is used, AOED should be cleared by the
user program upon initialization and upon completion of PAO
Positive Edge Detected IRQ processing.
Inputs
Inputs are enabled by writing a 1 into all 110 port register bit
positions that correspond to input lines. A low (s 0.8 Vdc) input
level causes a 0 to be read when a read instruction is issued
to the port register. A high (~2.0 Vdc) input level causes a 1
to be read. Assertion of RES forces all bits in the 110 port
registers to 1s, thus initially treating all I/O lines as inputs.
COUNTER OVERFLOW BIT (CTRO)
The Counter Overflow bit (bit 7) is set to a 1 whenever the Counter overflow occurs in any of the four counter operating modes.
Overflow occurs when the Counter is decremented one count
from O. This bit is cleared to a 0 by reading from address $087,
writing to address $088, or by assertion of RES.
The status of the input lines can be interrogated at any time by
reading the I/O port addresses. Note that this will return the
actual status of the input lines, not the data written into the 110
port register.
3-13
One-Chip Microcomputer
R65C10
Outputs
PA1 Negative Edge Detection
Outputs are controlled by writing the desired 110 line output
states into the corresponding 110 port register bit positions.
In addition to its normal I/O function, an asynchronous negative
(falling) edge signal can be detected on PAl. This occurrence
wit be reported in the PAl Negative Edge Detected bit in the
Control Register (CR5). CR5 is cleared by writing to address
$08A or by assertion of RES.
A 1 will force a high (;;,; 2.4 Vdc) output while a 0 will force a low
(:$ 0.4 Vdc) output.
1/0 PORT OPERATION WITH DIRECTION REGISTERS
3.15 COUNTER/LATCH
If direction registers are selected, the direction of all 32 110 lines
is controlled by individual bits in four write-only 110 port direction registers. The direction registers for ports A, B, C and D
are located at addresses $90, $91, $92 and $93, respectively.
Setting a bit in a direction register to a 1 causes the corresponding I/O line to operate as an output; resetting the bit to a 0 causes
the I/O line to be an input. Assertion of RES clears all
direction register bits to Os causing all 110 lines to initially be
inputs.
GENERAL
The CounterlLatch consists of a 16-bit Counter, and a 16-bit
Latch. The Counter resides in two 8-bit registers: address $086
contains the Upper Count value (bits 8-15 of the Counter) and
address $087 contains the Lower Count value (bits 0-7 of the
Counter). The Counter contains the count of either unscaled or
prescaled 02 clock periods, or external events, depending on
Counter mode selected in the Control Register and, for clock
driven Counter modes, the Prescaler mode and value selected
in the Prescaler Control Register. Table 3-2 lists the addresses
associated with CounterlLatch operation.
Inputs
If an 110 line is an input, the state of the corresponding bit in
the I/O port data register shows the input logic level: 1 = high;
O=low.
Table 3-2.
Outputs
If an 1/0 line is an output, the state of the corresponding bit written to the port data register determines the output logic level:
l=high; 0= low.
EDGE DETECTION CAPABILITY
The Port A PAO and PAl circuitry has edge detection capability. Edges detected on these lines are reported in the Control
Register and will cause an IRQ if enabled in the Control Register
(see Section 3.14). The edge detect timing waveforms are illustrated in Figure 3-9.
Counter/Latch Addresses
Function
Address
Write Upper Latch (Write Only)
Write Lower Latch (Write Only)
Read Upper Count (Read Only)
Read Lower Count, Clear Timer Overflow (Read Only)
Write Upper Latch and Transfer Latch to Counter,
Clear Counter Overflow (Write Only)
$084
$085
$086
$087
$088
The Latch contains the Counter initialization value. The Latch
resides in two 8-bit registers: address $084 contains the Upper
Latch value (bits 8-15 of the Latch) and address $085 contains
the Lower Latch value (bits 0-7 of the Latch). The 16-bit Latch
can hold values from 0 to 65,535.
PAO Positive Edge Detection
In addition to its normal I/O function, an asynchronous positive
(rising) edge signal can be detected on PAO. This occurrence
will be reported in the PAO Positive Edge Detected bit in the Control Register (CR6). CR6 is cleared by writing to address $089
or by assertion of RES.
The latch registers can be loaded at any time by writing to the
Upper Latch address ($084) and the Lower Latch address ($085).
In each case, the contents of the Accumulator are copied into
the applicable Latch register. The Upper Latch and Lower Latch
L..--_----II
~~~~g~TECT ~_:_::_:
:_:_:~
________________
--'
~I-_";--_ _ _ T PW
________________________________________
1-1 \
- - - - - 1...
'SEE NOTE
'NOTE: IRQ WILL STAY LOW UNTIL IT IS SERVICED
Figure 3-9.
PAO and PAl Edge Detection Timing Waveforms
3-14
One-Chip Microcomputer
R65C10
Pulse Generator Mode (Mode 1)
can be loaded independently; it is not required to load both
registers at the same time, or sequentially. The Upper Latch can
also be loaded by writing to address $088.
In the Pulse Generator mode, the CNTR line operates as a
Counter-Out. When a write is performed to address $088 the
CNTR output is initialized high. The Counter is decremented at
the TCLK rate. The CNTR line toggles from low to high or from
high to low whenever a Counter overflow occurs.
The Counter will also be initialized to the Latch value whenever
the Counter overflows. When the Counter decrements from 0,
the next Counter value will be the Latch value, not $FFFF.
Whenever the Counter overflows, the Counter Overflow status
bit in the Control Register (CR7) is set to a 1. This bit is cleared
whenever the lower eight bits of the Counter are read from
address $087 or by writing to address $088.
Either a symmetric or an asymmetric output waveform can be
output on the CNTR line in this mode. The CNTR output is
initialized to the high impedance siate (output disabled) by
assertion of RES since the Interval Timer mode is established
by RES.
COUNTER/TIMER MODES
Event Counter Mode (Mode 2)
The Counter operates in any of four modes. These modes are
selected by the Counter Mode Control bits in the Control Register
(see Table 3-3).
In this mode, the CNTR line is used as an Event-In input, and
the Counter will decrement with each rising edge detected on
this line. The maximum rate at which this edge can be detected
is one-half the system (02) clock rate.
The Interval Timer, Pulse Generator, and Pulse Width Measurement modes are internally clocked modes. The Event Counter
Mode counts the occurrences of an external event on the CNTR
line.
The Counter can count up to 65,535 occurrences before
overflowing. As in the other modes, the Counter Overflow bit
(CR7) is set to a 1 if the overflow occurs.
Figure 3-11 is a timing diagram of the Event Counter mode.
Interval Timer (Mode 0)
Pulse Width Measurement Mode (Mode 3)
In the Interval Timer mode, the Counter is initialized to the Latch
value by either of two conditions:
This mode allows the accurate measurement of a low pulse duration on the CNTR line. In this mode, CNTR is used in the Event-In
capacity. The Counter decrements at the TCLK rate as long as
the CNTR line is held in the low state. The Counter is stopped
when CNTR is in the high state.
1. When the Counter is decremented from 0, the next Counter
value is the Latch value, not $FFFF.
2. When a write operation is performed to the Upper Latch and
the Transfer Latch to Counter address ($088), the Counter
is loaded with the Latch value. Note that the contents of the
Accumulator are loaded into the Upper Latch before the Latch
value is transferred to the Counter.
If the CNTR pin is left disconnected, this mode may be selected
to stop the Counter since the internal pull-up device (if present)
will cause the CNTR input to be in the high (2:2.0 volt) state.
A timing diagram for the Pulse Width Measurement mode is
shown in Figure 3-12.
The Counter value is decremented at the timer clock (TCLK) rate.
The 16-bit Counter can hold from 1 to 65,535 counts. For a
4 MHz internal 02 clock and no prescaler selected, the timer
range is 0.25 P.s to 16.384 ms. For a 4 MHz internal 02 clock
and divide-by-128 prescaler selected, the timer range is 32 P.s
to 2.097 seconds.
3.16 INTERRUPT LOGIC
Interrupt logic controls the sequencing of RES and the two
interrupts: NMI, and IRQ.
When the Counter decrements from 0, the Counter Overflow bit
in the Control Register (CR7) is set to a 1 at the next counter
clock pulse. If the Counter Interrupt Enable bit (CR4) is also set,
IRQ will occur. The Counter Overflow bit in the Control Register
can be examined in the IRQ interrupt routine to determine that
the IRQ was caused by the Counter overflow.
RES Sequencing
RES going from low-to-high causes the R65C/l to set the Interrupt Disable bit in the Processor Status Register (bit 2) and to
initiate RES vector fetch at address $FFC and $FFD to begin
user program execution. All of the I/O ports (PA, PB, PC, and
PO) and CNTR are forced to the high (logic 1) state. All bits of
the Control Register are cleared to logic 0, causing the Interval
Timer Counter Mode (Mode 0) to be selected and causing all
interrupt enable bits to be reset. All Prescaler Control Register
bits are also reset to 0 causing Prescaler Mode 0 to be selected.
While the timer is operating in the Interval Timer mode, the
Counter-Out/Event-In (CNTR) line is held in the high impedance
state (output disabled).
A timing diagram of the Interval Timer mode is shown in
Figure 3-10.
3-15
One-Chip Microcomputer
R65C10
Cl>2
I
COUNTER OVERFLOW
COUNT
~
===><___-JX'-__2_..JX'--__-JX
I
'
3
f""-(U-L'-L-L)~X
(UL. LL)-l
COUNTER INTERRUPT ENABLED
SET ANY TIME BEFORE
COUNTER OVERFLOW
\
COUNTER OVERFLOW
IRQ
CNTR _ \ _ _ _ _
_
_
_
_
_
_
_
__ _
_
_
_
_
_
_
_
_
____ _
HELD HIGH IN MODE 00
Figure 3-10. Interval Timer (Mode 0) Timing Waveforms
\~----~nr----------
CNTR
*_______
COUNT _ _ _ _N
____
Figure 3-11.
N_.1_ _ _ _
~*
N-2
Event Counter (Mode 2) Timing Waveforms
3·16
:
:1-___
One-Chip Microcomputer
R65C10
OE
6
3
06
5
;> OA
21
;>
6
;>
31
:.
2
35
4
;>
1
V ,,1
Z PAGE.l
OP n
1/
toon
N V
~ ~ ~ ~
;
g
MNEMONIC
30
4
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39
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f-~~~_~____-r~+-TE~Er6~3~E6~'r'~~+-~~~-+-+_r-r~"~~6r'~FE~'~'t-~-+-+-r-r~+-+-t-~~------~~~~
E821
z·
I ~y
J M P
JUMP TO NEW LOC
2.0V)
state.
The Counter can count up to 65,535 occurrences before
overflowing. As in the other modes, the Counter Overflow
bit (CR7) is set to logic 1 if the overflow occurs.
A timing diagram for the Pulse Width Measurement Mode is
shown in Figure 3-7.
Figure 3-6 is a timing diagram of the Event Counter Mode.
3.15INPUT/OUTPUT PORTS
Pulse Width Measurement Mode (Mode 3)
The R6500/1 provides four B-bit Input/Output (1/0) ports
(PA, PB, PC, PO). These 32 1/0 lines are completely
bidirectional. All lines may be used either for input or output
in any combination; that is, there are no line grouping or
pori association restrictions.
This mode allows the accurate measurement of a low pulse
duration on the CNTR line. In this mode, CNTR is used in
the Event In capacity. The Counter decrements by one
\~--«tf--------
N-2
N·l
COUNT
READ
N·l
N·2
Figure 3-6. Event Counter Mode (Mode 2)
~
CNTR
COUNT
~2.0V
j
T,,,"
~
_
I I I I I I I
N
READ
r-
N·l
1,I ,.,
N·2
N,
T pDSU
2.0V
I N~ I IN~ I
N.31
"I
..
Figure 3·7. Pulse Width Measurement (Mode 3)
3-36
\)
N~
One-Chip Microcomputer
R6500/1
The direction of the 32 I/O lines are controlled by four 8-bit port
registers located in page zero. This arrangement provides quick
programming access using simple two-byte zero page address
instructions. There are no direction registers associated with the
I/O ports, which simplifies I/O handling. The I/O addresses are
shown in Table 3-4.
The status of the input lines can be interrogated at any
time by reading the liD port addresses. Note that this will
retum the actual status of the input lines, not the data written into the liD port registers.
Table 3-4. I/O Port Addresses
3.15.2 OUTPUTS
Port
Address
A
080
Outputs are controlled by writing the desired liD line output
states into the corresponding liD port register bit positions.
A logic 1 will force a high (>2.4V) output while a logic 0
will force a low «O.4V) output.
B
081
3.15.3 EDGE DETECTION CAPABILITY
C
082
D
083
Ports PAO and PA 1 have an edge detection capability. Figure 3-9 shows the edge detection timing.
Figure 3-8 shows the liD Port Timings.
PAO Positive Edge Detecting Capability
In addition to its normal liD function, PAO will detect an
asynchronous positive (rising) edge Signal and set the PAO
Positive Edge Detected signal (CR6) to logic 1. The maximum rate at which this positive edge can be detected is
one-half the !t2 clock rate.
3.15.1 INPUTS
Inputs are enabled by loading logic 1 into all I/O port register bit
positions that are to correspond to I/O input lines. A low «0.8V)
input signal will cause a logic 0 to be read when a read instruction
is issued to the port register. A high (>2.0V) input will cause a
logic 1 to be read. An RES signal forces all I/O port registers to
logic 1 thus initially treating all I/O lines as inputs.
If the PAO Interrupt Enable Bit (CR3) is set, an IRQ interrupt request will also be generated. The PAO Positive Edge
Detected signal can be cleared by writing to address 089.
I/O PORT OUTPUT TIMING
,~'"~",.
I~
~------fl_·~----T
;'M~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-'-_ _ _ _ _P_O_w__
PA. PB,
pc, PO
OUTPUT
-1
~ ~::vvcc
-
O.4V
t/O PORT INPUT TIMING
f
INTERNAL RtW
PA, PB,
pc, PO
INPUT
----------------------------
Figure 3·8. 1/0 Port Timing
3-37
TPOSU---l
2.0V
O.BV
-------------------
One-Chip Microcomputer
R6500/1
---JI
I I'-__---'
(/)2
~;~~'''' ~ ~:~:-:-V-:-~DS~U~ ~ ~TP-W- - - - - -:=:~:;~;t<:~~
L -_ _
____________________________________
'SEE NOTE
'NDTE: IRQ WILL STAY LOW UNTIL IT IS SERVICED
Figure 3-9. PAD and PAl Edge Detection Timing
PA1 Negative Edge Detecting Capability
3.16 MASK OPTIONS
In addition to its normal 1/0 function, PAl will detect an
asynchronous negative (falling) edge signal and set the PAl
Negative Edge Detected signal (CRS) to logic 1. The maximum rate at which this negative edge can be detected is
one-half the ~2 clock rate.
An option is provided to delete the internal pull-up resistance from
PA, PB, PC and/or PD ports at mask time. This option is available
for 8-bit port groups only, not for individual port lines. This option
may by used to aid interface with CMOS drivers, or in order to
interface with external pull-up devices.
If the PAl Interrupt Enable signal (CR2) is set, an fRQ
interrupt request will also be generated. The PA1 Negative
Edge Detected signal may be cleared by writing to address
D8A.
An option is also provided to delete the internal pull-up
resistance on the CNTR line.
3-38
R6500/1
One-Chip Microcomputer
SECTION 4
IRQ INTERRUPT REQUEST GENERATION
An IRQ interrupt request can be initiated by any or all of
three possible sources. These sources are all capable of
being enabled or disabled by the use of the appropriate
interrupt enabled bits in the Control Register.
Multiple simultaneous interrupts will cause the IRQ interrupt
request to remain active until all interrupting conditions have
been serviced and cleared.
The first source of IRQ is Counter Overflow. The IRQ interrupt
request will be driven low whenever both the Counter Interrupt
Enable (CR4) and the Counter Overflow (CR7) are logic 1.
If the same data, i.e., the same RAM, counter/latch or I/O
addresses, are operated on asynchronously by a normal
processing routine and by an interrupt service routine, care
must be taken to prevent loss of data due to the interrupt
routine altering the data during update of the data by the
normal processing routine. This situation can be prevented
by disabling the IRQ interrupt with the SEI instruction before starting the data update in the normal processing and
then enabling the interrupt with the CLI instruction upon
completion of data update.
The second source of IRQ is detection of a positive edge
on PAO. The IRQ inerrupt request will be driven low whenever both the PAO Interrupt Enable (CR3) and the PAO
Positive Edge Detected (CR6) are logic 1.
The third source of IRQ is detection of a negative edge on
PA1. The IRQ interrupt request will be driven low whenever
both the PA1 Interrupt Enable (CR2) and the PA1 Negative
Edge Detected (CR5) are logic 1.
3-39
R6500/1
One-Chip Microcomputer
SECTION 5
POWER ON/OFF CONSIDERATIONS
low at least eight ~2 clock pulses before vee falls out of
operating range. RES must then be held low while vee is
out of operating range and until at least eight (112 clock
cycles after vee is again within operating range and the
internal (112 oscillator is stabilzed. VRR must remain within
vee operation range during normal R6500/1 operation.
When vee is out of operating range, VRR must remain
within the VRR retention range in order to retain data. Figure 5-2 shows typical waveforms.
5.1 POWER·ON RESET
The occurrence of RES going from low to high will cause
the R6500/1 to set the Interrupt Mask Bit - bit 2 of the
Processor Status Register - and initiate a reset vector fetch
at address FFE and FFF to begin user program execution.
All of the I/O ports (PA, PB, PC, and PD) and eNTR will
be forced to the high (logic 1) state. All bits of the Control
Register will be cleared to logic 0 causing the Interval
Timer counter mode (mode 00) to be selected and causing
all interrupt enabled bits to be reset.
5.4 RAM DATA RETENTION OPERATION
The requirement for R6500/1 RAM dala retention and restart operation is application dependent. If R6500/1 RAM
dala retention is not required during loss of vee, then VRR
can be connected 10 the same power source as VCC.
With this configuration a complete initialization of R6500/1
program variables in RAM is required upon vee and VRR
power application.
5.2 POWER ON/OFF TIMING
After application of vee power to the R6500/1, RES must
be held low for at least eight 02 clock cycles after vee
reaches operating range and the internal clock oscillator has
stabilized. This stabilization time is dependent upon the
input vee voltage and performance of the crystal, clock, or
Re network input circuit. The clock oscillator output can be
monitored on XTLO (pin 11).
If the R6500/1 RAM is to retain data during loss of vee,
the following is required:
1. Connection of vee and VRR 10 separate power supplies
or to the same primary power supply with isolation
diodes and battery or other backup power for VRR.
Figure 5-1 illustrates the power turn-on waveforms.
5.3 RAM DATA RETENTION REQUIREMENTS
VRR
2. vee power monitor hardware with power loss and
cold/warm start indications to the R6500/1.
3 Power loss detection as well as cold and warm start
initialization in the R6500/1 program.
For the RAM to retain data upon loss of vee, VRR must
be supplied within operating range and RES must be driven
VCC +5
-- -C
- - --. - : - ' - - - - - - - - - - - - - - - I f J
o
XTLO
ifJ2
POWER ON
I
..L- CLOCK
---
STABI LIZATION TIME
--j
~8
IJ
Figure 6-1. Power Turn-On Timing Detail
3-40
R6500/1
One-Chip Microcomputer
RAM OPERATING MODE
. .-. - - - - n - - -
~----n-----
VRR
VCC
RAM RETENTION MODE
-;;.#
®
o
®
o
--
1--0
~I-------lH~---=--___!1
~ I--®
8
;>8
CP2 CLOCK PULSES AFTER:/12 OSCILLATOR STABILIZATION.
CP2 CLOCK PULSES.
Figure 5-2. RAM Retention Mode Timing
The power monitor hardware must sense the loss of VCC
power in sufficient time to allow the RS500/! to save required CPU register data in RAM. The power loss indication
line can be connected to the NMI interrupt input in order to
cause an immediate RS500/! interrupt upon power loss
detection.
depending upon coldlwarm start condition.
Upon power loss detection, the RS500/1 should save all required
CPU register data in either the stack or dedicated RAM. The stack
may be preferred if dedicated RAM is not available. If the program
is to restart at the interrupted address, then all CPU registers
must be saved, i.e., S, P, PC, A, X, and Y. The stack pointer must
be saved in a dedicated RAM address. Note that processor status
P and the program counter, PC, are already saved on the stack by
the NMI interrupt RS500/1 hardware processing. If the warm start
can be performed at a specific address, then the saving of the
register data at power loss detection may not be required. Figure
5-3 shows top level flowcharts of typical power down and
power-up processing.
The power monitor hardware should also provide an indication of cold start (initial VCC and VRR power application) or
warm start (VCC power re-application while VRR is retained
on backup power) provided as input on a data 1/0 pin.
A level indication is sufficient. The RS500/! program can
then initialize all, or partial, program variables upon initialization then jump to any other starting address as required
3-41
D
R6500/1
One-Chip Microcomputer
NO
'HANG UP IN SHORT
LOOP UNTIL EXECUTION
TERMINATES
a.
Program Recovery at
Address of Interruption
NO
'HANG UP IN SHORT
LOOP UNTIL EXECUTION
TERMINATES
b.
Program Recovery at
Specific Restart Address
Figure 5·3. Typical R6500/1 Power Loss Recovery Flowcharts
3·42
R6500/1
One-Chip Microcomputer
APPENDIX A -
SYSTEM MEMORY MAP
HEX
FFF
FFE
FFD
FFC
IRQ Vector High
IRQ Vector Low
RES Vector High
RES Vector Low
ROM
FFB
FFA
FF9
NMI Vector High
NMI Vector Low
User Program
800
7FF
R6500/f E User Program
400
3FF
.
Unassigned
<
Control Register
900
08F
08E
.. >
>08B
Unassigned
Clear PAf Neg Edge Detected (Write Only)
(f)
08A
Clear PAO Pas Edge Detected (Write Only)
(f)
089
Upper Latch and Transfer Latch to Counter (Write Only)
(2)
088
Lower Count (Read Only)
(2)
087
Upper Count (Read Only)
086
Lower Latch (Write Only)
085
Upper Latch (Write Only)
084
PORTD
083
PORTC
082
PORTB
08f
PORTA
~
InpuVOutput
080
Unassigned
-<>
03F
User RAM
}
000
Notes:
(f) I/O command only; i.e., no stored data.
(2) Clears Counter Overflow - Bit 7 in Control Register.
3-43
RAM
One-Chip Microcomputer
R6500/1
APPENDIX B -
R6500 INSTRUCTION SET
This appendix contains a summary of the R6500 instruction set. For detailed information, consult the R6500 Microcomputer System Programming Manual, Document Order No. 202.
B.1 INSTRUCTION SET IN ALPHABETIC SEQUENCE
Mnemonic
Description
Mnemonic
ADC
AND
ASL
Add Memory to Accumulator with Carry
''AND'' Memory with Accumulator
Shift Left One Bit (Memory or Accumulator)
LDA
LDX
LDY
LSR
Description
Load Accumulator with Memory
Load Index X with Memory
Load Index Y with Memory
Shift One Bit Right (Memory or Accumulator)
BCC
BCS
BEQ
BIT
BMI
BNE
BPL
BRK
BVC
BVS
Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits in Memory with Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Force Break
Branch on Overflow Clear
Branch on Overflow Set
NOP
No Operation
CLC
CLD
CLI
CLV
CMP
CPX
CPV
Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable Bit
Clear Overflow Flag
Compare Memory and Accumulator
Compare Memory and Index X
Compare Memory and Index Y
DEC
DEX
DEY
Decrement Memory by One
Decrement Index X by One
Decrement Index Y by One
EOR
"Exclusive-Or" Memory with Accumulator
iNC
INX
INY
Increment Memory by One
Increment Index X by One
Increment Index Y by One
JMP
JSR
Jump to New Location
Jump to New Location Saving Return Address
ORA
"OR" Memory with Accumulator
\
PHA
PHP
PLA
PLP
3-44
I
Push Accumulator on Stack
Push Processor Status on Stack
Pull Accumulator from Stack
Pull Processor Status from Stack
ROL
ROR
RTI
RTS
Rotate One Bit Left (Memory or Accumulator)
Rotate One Bit Right (Memory or Accumulator)
Return from Interrupt
Return from Subroutine
SBC
SEC
SED
SEI
STA
STX
STY
Subtract Memory from Accumulator with Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Store Accumulator in Memory
Store Index X in Memory
Store Index Y in Memory
TAX
TAY
TSX
TXA
TXS
TYA'
Transfer Accumulator to Index X
Transfer Accumulator to Index Y
Transfer Stack Pointer to Index X
Transfer Index X to Accumulator
Transfer Index X to Stack Register
Transfer Index Y to Accumulator
R6500/1
One-Chip Microcomputer
82. INSTRUCTION SET SUMMARY TABLE
.---,-----r--r---,----y---r---r---y---r---r---y---r---,p~OCESSORSTATUS
IMMEDIATe
INSTRUCTIONS
ABSOllJTE
,
• OP
OPERATION
MNEMONIC
111 29
c --rr:::=::::::i-o
=Q
ZEROI'AGE
OP ,.,
(IND. Xl
_ OP n
/I
OP n
/I
32532
06
OE
')
2
IIND).Y
OP n
"OP
61
2
I;
2162
OA
;;>
n
Z'",GE.X
/I
AaSx
OP n
"BS,Y
~
OP n
,"
JI
5
2
35
n,OIRECT
• OP n
IIOP,.,
I PAGe. Y COOfS
.OPn
7 6
:,
4
IE
1
2
1 0
MNEMONIC
Z C
33943
4
1
3
'NVo8DIZC
3
o
Z
o
Z C
AND
0
ASC
BCC
BRANCH ON C
12\
90
22
B C S
BRANCH ON Cool
121
a, 0
80
2
2
BCS
BRANCH ON Z ,,1
121
,
2
B'O
BIT
lC
a
M I
B R K
4
J
24
3
BCC
z
2
BRANCH ON N
oo,
121
JO
2
2
BRANCH ON Z
=0
(2)
DO
2
2
BRANCH ON N '" 0
(2)
0
BN,
an
aA,
avc
BREAK
BRANCH ON V '" 0
(2)
50
8 V S
BRANCH ON V
(2)
702
CLe
o-c
=,
22
2
o
0
CLC
CLO
C L I
C L I
C9 ,
2
EO
cn
,
CO
,
CD
2 EC
.
4
0' C
3"
3 C6
C LV
00
,
3,
,
J C5 3
Cl
6
2 01
:,
2 D5
4
2 DO
4
.1 09
4
3
• z c,
CMP
Z C
CP>
Z C
cn
o
5
06
6
2 DE
7
3
z
'0 A
2
11149
2
4D
5
II
JUMP TO NEW LOC
3
3
20
6
3
AD
4
3 A5
3
A9
2
A2
2
2 AE
4
3 A6
3
2
(1)
AQ
2
2
AC
4
3
3
2
4E
6
Q-L-=-=-lJ-·c
E82
1
P L A
S+I-5
2
51
:,
2
55
4
2 50
C8
T
2
4
3 59
,
3
4
z
3
'OA
0
INC
z
Z
A4
2
Al
6
2
61
:,
2
2 BO
,
:,
J MP
J
4
3 69
4
3
BE
4
3
85
4
2
8C
Z
LOA
1
L0 ,
Z
LBA
50525E
01
s-
6
J S A
(1)
L 0 ,
2
41
2
5C
4C
0
DEY
31,
4
INC
0' C
0"
1 °
1 ·5
08
MS-A
3
6
2
"
5
2
15
4
J
4
2 10
36 6
2 JE
N
2 IE
N°
19
4
ORA
Z
J
,
58
Z
P L P
IRESTOREDI
3
6E 6
26
5
3 66
5
2 2A
2
I
e
Z e
HOL
1
AOA
(RESTORED)
A T S
AT S
A - M -
C • All)
E9
2
2
EO
4
3 E5
3
2
£1
6
2
Fl
:,
2 F5
4
;;>
FO
4' 3 F9
4
3
Z (31
sac
SEC
Fa
S ,
2
1
I
S , I
80 ,
S T A
2 90
5
3
99
5
S TA
3
S T ,
5T ,
STY
8C
,
944
STY
2
TA ,
1
Z
9A
2
1
98
~
,
"S
ADO 1 to N IF PAGE BOUNDARY IS CROSSED
ADO 1 TO N IF BflANCH OCCURS TO SAME PAGE
ADD2 TO N IF BRANCH OCCURS TODIFFERENT PAGE
~
131
CARRY NOT
141
IF IN DECIMAL MODF Z FLAG IS INVALID
ACCUMULA TOR MUST BE C~,ECKED FOR ZERO R~SUL T
BORROW
INDEX Y
SUBTRACT
ACCUMULATOR
AND
MEMORY PER EFFECTIVE ADDRfSS
MEMOR~
3·45
PER STACK POINTER
M,
M,
MEMORY BIT 7
MEMOR~·
81T 5
NO. CYCLES
NO BYTES
EXCLUSIVE OR
II
One-Chip Microcomputer
R650011
APPENDIX C
SYSTEM SPECIFICATIONS
MAXIMUM RATINGS·
Parameter
Symbol
Value
Unit
Vee, VRR
-0.3 to +7.0
Vde
Input Voltage
V ,N
-0.3 to +7.0
Vde
Operating Temperature
Commercial
Industrial
TA
T L to TH
o to +70
-40 to +85
°C
TSTG
-55 to +150
°C
Supply Voltage
Storage Temperature
-NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in other sections of this document is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
DC CHARACTERISTICS
(Vee
= 5.0V
± 10% for R6500!1, Vee
= 5.0V
Parameter
±5% for R650011A, VRR
Symbol
RAM Standby Voltage (Retention Mode)
VRR
RAM Standby Current (Retention Mode)
Commercial
Industrial
IRR
Input High Voltage
All Except XTLI
XTLI
V'H
Input Low Voltage
VIL
Input Leakage Current
RES, NMI
liN
= Vee; Vss = OV; TA = 0° to 70°C, unless otherwise specified)
Min
Typl
-
3.5
Max
Vee
Unit
Test Conditions
V
mA
-
10
12
V
+2.0
+4.0
-
-
Vee
Vee
-0.3
-
+0.8
V
-
±1.0
±2.5
~A
V ,N
= 0 to
-
-1.0
-1.6
mA
VIL
= OAV
-
-
V
ILOAO = -100
Vee = 4.75V
5.0V
Input Low Current
III
Output High Voltage
VOH
Output High Voltage (CMOS)
VeMos
-
V
Vee
Output Low Voltage
VOL
-
-
+0.4
V
Vee = 4.75V
ILOAD = 1.6 mA
1/0 Port Pull-Up Resistance
PAO-PA7, PSO-PS7, PCO-PC7,
PDO-PD7, CNTR
RL
3.0
6.0
11.5
Kohm
+204
Vee - 30%
-
= 4.75V
Output High Current (Sourcing)
IOH
-100
-
-
~A
Vour
Output Low Current (Sinking)
10L
1.6
-
-
mA
Vour
Input Capacitance
XTLI, XTLO
PA, PS, PC, PD,CNTR
C 'N
pF
-
-
TA = 25°C
V ,N = OV
f = 1.0 MHz
Output Capacitance (Three-State Off)
Cour
-
50
10
-
10
pF
TA = 25°C
V,N = OV
f = 1.0 MHz
Power Dissipation (Outputs High)
Po
-
mW
Vee
Notes:
1. Typical values measured at TA = 25°C and Vee = 5.0V.
2. Negative sign indicates outward current flow, positive indicates inward flow.
3-46
600
990
~A
= 2AV
= 0.4V
=
+5.5V
One-Chip Microcomputer
R6500/1
AC CHARACTERISTICS
(Vee
= 5V
+
- 10% for R6500/1, Vee
= 5V
± 5% for R6500/1A)
1 MHz
Parameter
Symbol
2 MHz
Min
Max
Min
Max
Unit
0.500
5.0
0.250
5.0
,,"sec
XTLI Inpul Clock Cycle Time
Toyc
Internal Write to Peripheral Data Valid (TTL)
Tpow
1.0
0.5
floSec
Internal Write to Peripheral Data Valid (CMOS)
TeMos
2.0
1.0
,,"sec
Peripheral Dala Selup Time
TpDSU
400
200
nsec
Count and Edge Deteel Pulse Width
Tpw
1.0
0.5
,,"sec
3-47
One-Chip Microcomputer
R6500/1
PACKAGE DIMENSIONS
40-PIN PLASTIC DIP
MILLIMETERS
I;::::::::: ~::::::: :~i~",
~Gf+
F -+0
K
MIN
MAX
MIN
MAX
A
5162
5232
2040
2.060
B
1346
13.97
0530
0.550
C
356
5.08
0140
0200
D
038
0.53
0015
0.021
F
1.02
1.52
0.040
G
~~
+1-
M
INCHES
DIM
sse
254
0.100
0.060
esc
H
165
2.16
0.065
J
K
020
3.30
0.30
4.32
0008
0012
0.130
0.170
L
15.24
M
7"
N
051
esc
10"
1.02
0600
0085
ssc
7"
10"
0.020
0.040
44-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
SEATING PLANE
INDEX!I~g~
CORNE~kr;D~1
TEr
oil
ill±
6
0
1
.. -
PIN 1
MIN
MAX
4.39
0163
0.173
A1
1.37
147
0.054
0.058
A.
2.31
2.46
0.091
0,097
SIDE VIEW
CHAM.J x 45°
~~LA1
~~
A
SECTION A-A
TYP FOR BOTH AXIS (EXCEPT FOR BEVELED EDGE)
EJECTOR PIN MARKS
4 PLCS BOTTOM OF
PACKAGE ONLY
(TYPICAL)
BOTTOM VIEW
3-48
0.457 TVP
0018 TVP
D
11.45
17.60
0.687
0.693
D1
16.46
16.56
0.648
0.652
D.
12.62
I 12.78
0.497
e
TOP VIEW
CHAM.
11 PINS
h x 45° PER SIDE
3 PLCS EQUALLY
SPACES
MAX
4.14
D3
••
INCHES
MIN
A
b
I~2 ! INDICATOR
~-17
1
MILLIMETERS
DIM
15.75 REF
1.27
esc
0.503
0.620 REF
0.050
esc
h
1.15 TVP
0.045 TYP
J
0.25 TV?
0.010 TVP
.
45 0 TVP
45 0 TVP
R
0.89 TV?
0.035 TVP
R1
0.25 TVP
0.010 TVP
R6500l1E
'1'
R6500/1E
Microprocessor Emulator Device
Rockwell
INTRODUCTION
document. The R6500/1 Product Description (Order No. 212) contains a description of R6500/1 functions and interface signals.
The R6500/1 E device provides all the features of the R6500/1
Microcomputer in a ROMless form suitable for use as an
advanced microprocessor complete with 16-bit counter and 32
110 lines, and an address and data bus for 4K of external memory.
The R6500/1 E device is available in both 64-pin ceramic DIP
(R6500/1 EC) and 64-pin plastic QUIP (R6500/1 EQ).
ORDERING INFORMATION
To aid in designing R6500/1 microcomputer systems, it may also
be used as an emulator device. Device architecture is basically
the same as the R6500/1 except that the address, data, and
associated control lines are routed off the chip for connection to
an external memory.
The functions and operation of the R6500/1 E device are identical to the R6500/1 except for minor differences noted in this
XTLO
XTLI
112
VSS
ROY
RES
NMI
SYNC
PB7
PB6
PBS
PB4
PB3
PB2
PBl
PBO
PA7
PA6
PAS
PA4
PA3
PA2
PAl
PAD
VRR
CNTR
AD
Al
A2
A3
A4
AS
A6
A7
Part
Number
Package
Type
Frequency
Option
Temperature
Range
R6500/1EC
R6500/1EAC
R6500/1EO
R6500/1EAO
Ceramic
Ceramic
Plastic
Plastic
1 MHz
2 MHz
1 MHz
2MHz
O·Cta 70·C
O·Cto 70·C
O·Cta 70·C
O·Cta 70·C
XTLO
XTLI
112
VSS
ROY
RES
NMI
SYNC
PB7
PB6
PBS
PB4
PB3
PB2
PBl
PBO
PA7
PA6
PAS
PA4
PA3
PA2
PAl
PAD
VRR
CNTR
AD
Al
A2
A3
A4
AS
A6
A7
Rfii
PCO
PCl
PC2
PC3
PC4
PCS
PC6
PC7
DO
01
02
03
04
05
06
07
P07
P06
POS
P04
P03
P02
POl
POO
All
Al0
A9
AS
VCC
R6S00/l E (64-PIN DIP)
Rfii
PCO
PCl
PC2
PC3
PC4
PCS
PC6
PC7
DO
01
02
03
04
05
06
07
P07
P06
POS
P04
P03
P02
POl
POD
All
Al0
A9
AS
VCC
R6S00/1Ea (64-PIN aUIP)
R6500/1 E Pin Assi9nments
Document No. 29000D51S
Data Sheet
3-49
Order No_ D51S
Rev. 3, June 1987
Microprocessor Emulator Device
R6500/1E
INTERFACE SIGNALS
debugging with the R650011E but cannot be used when the object
code is transferred to masked ROM in an R650011 (which is restricted to $800-$FF9).
All R650011 interface signals are available in the R6500l1E
microcomputer plus the additional address (12), data (8), and control (4) lines required to extend the address bus and the data bus
external to the device. The R6500/1E emulator unique interface
signals are shown in Figure 1 and are described in Table 1. While
the pin assignments are different in order to accommodate
64-pin DIP and QUIP packages, the interface characteristics of
signals common to the R650011 are identical.
A memory map of the R6500l1E is shown in Figure 2.
INTERNAL 1/0 PORT PULL-UPS
The R6500/1E has the internal I/O and CNTR port pull-up resistors only. The option to delete the pull-up resistors is not available for the R6500/1 E.
I
SYSTEM ARCHITECTURE
EARLIER I/O PORT INITIALIZATION
The architecture of the R6500l1E is identical to the R6500/1 with
the following differences:
Ports A, B, C, D and the CNTR line in the R6500/1 E are initialized
to the logic high state two 02 clock cycles earlier than in the
ResOO/l.lt is still required, however, thatthe RES line be held low
for at least eight 02 clock cycles after VCC reaches operating range
(Figure 3).
EXTERNAL ADDRESSING
ROM addressing is routed externally in the R650011E. The address
range for internal ROM in the R6500/1 ($800-$FF9) is available
externally for connection to ROM or RAM devices(s).
WRITE-ONLY MONITORING
The R6500l1E allows the user to monitor write operations to the
internal RAM and I/O by routing those operations externally as well
as internally. Read operations are not routed externally.
An additional 1024 bytes ($400-$7FF) are decoded for external
memory access. Note that this address range can be used for
r
8-BIT
PORTA
PAD-PA7
V RR
POWER
8-BIT
PORTB
PBO-PB7
Vss
CRYSTAL
r
8-BIT
PORTC
PCO-PC7
XTLO
12 ADDRESS
LINES
R6500/1E
SINGLE CHIP
MICROCOMPUTER
EMULATOR
8-BIT
PORTO
PDO-PD7
CNTR
8 DATA
LINES
EMULATOR
CONTROL
NMI
\12
ROY
RES
SYNC
R/W
Figure 1.
R6500/1E Emulator Interface Diagram
3-50
TO
INTERFACE
DEVICES
Microprocessor Emulator Device
R6500/1E
Table 1.
R6500/1E Emulator Unique Signals Description
Signal
Name
Pin
No.
RIW
62
ReadlWrite. ReadlWrite allows the CPU to control the direction of data transfer between the R6500/IE Emulator CPU and
external memory. This line is high when reading data from memory and is low when writing data to memory.
ROY
3
Ready. The Ready input delays execution of any cycle during which the ROY line is low. This allows the user to halt or
single step the CPU on all cycles except write cycles. A negative transition to the low state during the 02 clock low pulse
will halt the CPU with the address lines containing the current address being fetched. If ROY is low during a write cycle.
it is ignored until the following read operation. This condition will remain through a subsequent 02 clock pulse in which
the ROY line is low. This feature allows the CPU to interface with memories having slow access times, such as EPROMS
used with the R6500ltE during prototype system development.
SYNC
6
Sync. The Sync signal is provided to identify cycles in which the CPU is performing OP COOE fetch. SYNC goes high
during the 02 clock low pulse of an OP CODE fetch and stays high for the remainder of that cycle. If the ROY line is pulled
low during the 02 clock low pulse in which SYNC went high, the CPU will halt in its current state and will remain in that
state until the ROY line goes high. Using this technique, the SYNC signal can be used to control ROY to cause single instruc-
02
I
Phase 2 (02) clock: Oata transfer takes place only during 02 clock pulse high.
Description
tion execution.
AO-A11
25-37
Address Bus Lines_ The address bus buffers on the R6500ltE are push/pull type drivers capable of driging at least 130 pF
and one standard TIL load. The address bus always contains known data. The addressing tgechnique involves putting
an address on the address bus which is known to be either in program sequence, on the same page in program memory,
or at a known point in memory. The I/O address commands are also placed on these lines.
00-07
53-46
Data Bus Lines. All transfers of instructions and data between the CPU and memory. 110. and other interfacing circuitry
take place on the bidirectional data bus lines. The butters driving the data bus lines have full three-state capability. Each
data bus pin is connected to an input and output buffer, with the output butter remaining in the floating condition.
HEX
~l
IRQ VECTOR HIGH
IRQ VECTOR LOW
RES VECTOR HIGH
RES VECTOR LOW
NMI VECTOR HIGH
NMI VECTOR LOW
FFE
FFD
FFC
FFB
FFA
FF9
BOO
7FF
400
R6S00/t USER PROGRAM
R6S00/1E EXTENDED PROGRAM AREA (1)
'< CONTROL REGISTER
>
UNASSIGNED
~
UNASSIGNED
CLEAR PAt NEG EDGE DETECTED
CLEAR PAO POS EDGE DETECTED
UPPER LATCH AND TRANSFER LATCH TO COUNTER
LOWER COUNT
UPPER COUNT
LOWER LATCH
UPPER LATCH
PORTD
PORTC
PORTB
PORTA
UNASSIGNED
2
2
(3
(3)
OBF
OBE
OBB
DBA
OB9
OBB
OB7
OB6
OB5
OB4
083
OB2
OB1
OBO
ROM
NOTES:
( 1) Additional 1024 bytes are decoded for external
memory addressing_ This area can be used during
debug, but cannot be used in a masked ROM
R6500/1_
(2)
110
command only; i_eo, no stored data.
(3) Clears Counter Overflow -
INPUT/OUTPUT
~~~ }RAM(4)
USER RAM
Figure 2.
R6500/1E Memory Map
3-51
Bit 7 In Control Register
(4) CAUTION: The device allows RAM mapping into
040-07F, 100-13F, 140-17F, 200-23F, 240-27F,
300-33F, and 340-37F; as well as 000-03F_ The
production R6500/1, however allows RAM mapping
only at 000-03F.
R6500/1E
Microprocessor Emulator Device
~ RES TRANSITION
~ WINDOW
110
PORTS
RES
~II.QIL_ _ _ _ _.....:8...;:tP:::2...:C:::L:::0.::C:..::K..:C:..:.Y.::CL=E:.:S;.;M::::I::.:N::::IM::.:U;;;M::...._ _ _ _~
R6500/1E
':'O~~"""~--------------------I!\r--
RaSOO/1
t'O~~"""~=,,="""~--------------""'1V--
~
DON'T CARE STATE
{
Figure 3.
R6500/1E 1/0 Port Initialization
TYPICAL PROGRAM MEMORY
INTERCONNECTIONS
Two typical connections between the R6500/1E and program
memory (in this case, type 2716 and 2732 PROMS) are illustrated.
Figure 4 shows a connection to a 2K 2716 PROM. Since the
R6500n has a 2K ROM capacity, the contents of the PROM could
be masked directly into the production R6500/1 ROM.
Figure 5 shows a connection to a 4K 2732 PROM. Only 3K bytes
($400-$FFF) are enabled. The upper 2K bytes correspond the pro·
duction ROM space ($800·$FFF) in the R6500/1. The extra
1K ($400-$7FF) allows expanded or additional programs to be
used during R6500/1 firmware development. The production pro·
gram, however, must be reduced to 2K maximum ($800·$FFF)
before masking into R6500n ROM.
3·52
R6500/1E
Microprocessor Emulator Device
CONNECTION
MEMORY MAP
FFF
00-07
K
8
00-07
2716
PROM
....
AO-Al0
R6500l1E
All
>
11
H> r-
800
7FF
AO-Al0
2716
PROM
OE
NOT USED
CE
090
08F
II
RAM &110'
000
'SEE DETAILED
MEMORY MAP
Figure 4.
R6500/1E Connected to One 2716 PROM (2K Bytes)
CONNECTION
00-07
V'
r--.
MEMORY MAP
8
~I
00-07
2732
PROM
AO-All
12
-" ~
800
AO-A11
v
R6500/1E
Al0
All
V
74LS02
r
7FF} EXTENDED
MEMORY
PROGRAM
400
3FF
2732
PROM
OE
-
NOT USED
CE
RAM & I/O
090
• OaF
000
'SEE DETAILED
MEMORY MAP
Figure 5.
PROGRAM
MEMORY
R6500/1E Connected to One 2732 PROM (3K Bytes)
3-53
Microprocessor Emulator Device
R6500/1E
DEVICE TIMING
1 MHz
Signal
RJW setup time from
Symbol
CPU
Min.
2 MHz
Max.
Min.
Max.
Unit
ns
TRWS
300
200
Address setup time from CPU
TAOS
300
200
ns
Memory read access time
TACC
525
225
ns
Data stabilization time
TDSU
150
75
ns
Data hold time -
Read
THR
10
10
ns
Data hold time -
Write
THW
30
Data delay time from CPU
TMDS
ROY setup time
TROY
I
30
200
ns
150
50
100
SYNC delay time from CPU
TSYNC
Address hold time
THA
30
30
RiW hold time
THRW
30
30
Cycle Time
TCYC
1.0
ns
175
350
0.5
10.0
ns
ns
ns
ns
10.0
I's
TIMING DIAGRAMS
PHASE 2 (<1>2) TIMING REFERENCE
~
<1>2
rf..----TCYC
0.4~
0.4V (
TIMING FOR READING FROM MEMORY
RiW
----"
TIMING FOR WRITING TO MEMORY
R/W
"
.
ADDRESS --t--,.......
FROM'CPU _ _ _,
--r---.
ADDRESS
FROM CPU'_-Io_'"
DATAFROM~~~~~~__4--=~~--~~
DATAFROM_~~::~_ _4-~~~---r1s:
MEMORY
CPU
RDY
SYNC
3-54
Microprocessor Emulator Device
R6500/1E
MAXIMUM RATINGS*
Parameter
Symbol
Value
Unit
Supply Voltage
Vee
-0.3 to + 7.0
Vdc
Input Voltage
V,N
-0.3to+7.0
Vdc
Operating Temperature
TA
Storage Temperature
TSTG
oto
+ 70
-55 to + 150
"NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device atr these or any other conditions above
those indicated in other sections of this document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
°C
°C
ELECTRICAL CHARACTERISTICS
(Vee
= 5.0 ± 5%, Vss = 0, TA = O°C to 7O°C unless otherwise specified)
Characteristic
Symbol
Min
Typ
Max
Unit
RAM Standby Voltage (Retention Mode)
VRR
3.5
-
Vee
V
10
-
Vdc
RAM Standby Current (Retention Mode)
IRR
Input High Voltage
V,H
+2.4
-
-
-
+0.8
Vdc
±10
pA
V,N = 0.4 to 2.4V
Vee = 5.25V
-
-
Vdc
ILOAO = -100 pA
Vee = 4.75V
+0.6
Vdc
ILOAO = 1.6 pA
Vee = 4.75V
1200
pW
Vee
V,L
ITSI
Output High Voltage
00-07, SYNC, AO-A11, RiW, 02
VOH
Output Low Voltage
00-07, SYNC, AO-A11, RiW, 02
VOL
-
-
Po
-
750
Power Oissipation (Vee
= 5.5V)
Input Capacitance
ROY, PA, PB, PC, PO, CNTR
00-07
XTLI, XTLO
Output Capacitance
AO-A11, RiW, SYNC
02
1/0 Port Pull-up Resistance
C 'N
rnA
-
Input Low Voltage
Three-State (Off State) Input Current
00·07
+2.4
Test Conditions
= S.5V
pF
-
-
10
15
SO
-
-
TA = 2SoC
V,N = 0
f = 1 MHz
COUT
C02
-
-
12
80
pF
-
RL
3.0
6.0
11.5
kohm
Notes:
1. Typical values measured at TA = 2S o C and Vee = S.OV.
2. Negative sign indicates outward current flow, positive indicates inward flow.
3-55
Microprocessor Emulator Device
R6500/1E
PACKAGE DIMENSIONS
R6500/1EC 64·PIN DIP CERAMIC
10· MAX
~Me",oo·'~D[j~
-Ji~_rw
J I "r :
" ' -32 1
1'--"3235
.050 NOM
~.
.120 MIN
.028 (.71 M M ) j t
.032 (.81 MM)
.015 (.38 MM)
.019 (.48 MM)
.070 (1.78 MM)
.080 (2.03 MM)
(3.05 MM)
LEADS .100
(2.54 MM)
cr. TO cr.
NOTE: PIN NO.1 IS IN LOWER LEFT CORNER WHEN
SYMBOLIZATION IS IN NORMAL ORIENTATION
R6500/1 EQ 64-PIN QUIP PLASTIC
1t
l
10
.020 TYP.
(.508 MM)
.925
I
o
o
1.628
(41.35 MM)
1
:g
-.nr-
rf'!:!
.200
dz ~c:
oZ
~~
,...
() UI
32
33
.680
I
1-(17.27
MM)--I
t Iii
-cr.-I
-cr.-+0.50 REF
(1.27 MM)
TYP
i: i
~_J_
.020 RE;r
TYP
3·56
MM)91"I
(19.05 MM)
1··1
-=-
'----_"--.1-_
(5.08~
:I>
c: "
;;::1>'
"1_(23·~;;0
~ci.
64 PIN QUIP
R6500l1EB • R6500l1EAB
'1'
R6500/1EB and R6500/1EAB
Backpack Emulator
Rockwell
INTRODUCTION
FEATURES
The Rockwell R6S00/1 EB and R6S00/1 EAB Backpack Emulator
is the PROM prototyping version of the 8-bit, masked-ROM
R6S00/1 one-chip microcomputer. Like the R6S00/1, the backpack device is totally upward/downward compatible with all
members of the R6S00/1 family. It is designed to accept standard S-volt, 24-pin EPROMs or ROMs directly, in a socket on
top of the Emulator. This packaging concept allows a standard
EPROM to be easily removed, reprogrammed, then reinserted
as often as desired.
• PROM version of the R650011
• Completely pin compatible
microcomputers
The backpack devices have the same pinouts as the maskedROM R6500/1 microcomputer. These 40 pins are functionally and
operationally identical to the pins on the R6S00/1, with some
minor differences (described herein). The R6S00/1 Microcomputer Product Description (Order No. 212) includes a description of the interface signals and their functions. Whereas the
masked-ROM R6S00/1 provides 2K bytes of read-only memory,
the R6S00/1EB will address 3K bytes of external program
memory. This extra memory accommodates program patches,
test programs or optional programs during breadboard and prototype development states.
•
•
•
•
•
•
with
R6S00/1
single-chip
• Profile approaches 4O-pin DIP of R6S00/1
• Accepts S-volt, 24-pin industry-standard EPROMs
-4K memories-2732, 2732A (3K bytes addressable)
• Use as prototyping tool or for low volume production
• 3K bytes of memory capacity (4K memories)
64 x 8 static RAM
Separate power pin for RAM
Software compatibility with the R6500 family
32 bi-directional TTL compatible
lines (4 ports)
1 bi-directional TTL compatible counter
line
l6-bit programmable counterllatch with four modes (interval
timer, pulse generator, event counter, pulse width
measurement)
• 5 interrupts (reset, non-maskable, two external edge sensitive, counter)
va
va
• Crystal or extemal time base
• Single +SV power supply
ORDERING INFORMATION
BACKPACK EMULATOR
Part
Number
Memory
Capacity
Compatible
Memories
Temperature
Range and Speed
R6500/1EB3
3KxB
2732
OOC to 70°C
1 MHz
R6500/1 EAB3
3KxB
2732A
(250 ns)
O°C to 70°C
2 MHz
SUPPORT PRODUCTS
Part
Number
Description
RDC-3101
RDC-3030
RDC-369
Low Cost Emulator (LCE)
PROM Programmer Module
1- or 2-MHz R6500/1 Personality Module
R6500/1EB-R6500/1EAB Backpack Emulator
Document No. 29000060
Data Sheet
3-S7
Order No. 060
Rev. 4, June 1987
II
Backpack Emulator
R650011 EB and R6500/1 EAB
CONFIGURATION
1/0 PORT PULWPS
The emulator devices have internal I/O port pullup resistors.
The external memory must always occupy the upper 2K of
available memory (addresses 800 through FFF) for implementation of interrupt vectors. See Memory Map. The Backpack
Emulator provides a read block to the external memory where
internal RAM or 110 are located in the same addresses as that
occupied by external memory.
PRODUCT SUPPORT
The Backpack Emulator is just one of the products that Rockwell
offers to facilitate system and program development for the
R6500/1.
The Low Cost Emulator (LCE) with R6500/1 Personality Module
supports both hardware and software development. Complete
in-circuit user emulation with the R6500/1 Personality Module
allows total system test and evaluation. With the optional PROM
Programmer, the LCE can also be used to program EPROMs
for the development activity. When PROM programs have been
finalized, the PROM device can be sent to Rockwell for masking into the 2K ROM of the R6500/1.
EXTERNAL FREQUENCY REFERENCE
The external frequency reference may be a crystal or a clock.
The R6500/1 EB and R6500/1 EAB divide the input clock by two
regardless of the source.
XTLI
XTLO
RES
NMI
VCC, VRR, VSS
PAD-PA7
¢a:»
PCG-PC7
<=<>
VCC,VSS
POG-P07
¢s:>
PROM/
ROM
CNTR
OE
CE
40 R6500/1
COMPATIBLE PINS
24 PROM/ROM
PINS
R6500/1 EB Interface Diagram
3-58
Backpack Emulator
R6500/1 EB and R650011 EAB
DETAILED MEMORY MAP
PROM
BACKPACK MEMORY SIGNAL
DESCRIPTION
IRQ VECTOR HIGH
IRQ VECTOR LOW
RES VECTOR HIGH
RES VECTOR LOW
NMI VECTOR HIGH
NMI VECTOR LOW
R650011 USER PROGRAM
PROM
R6S00/1EB EXTENDED PROGRAM AREA (1)
NOT
USED
UNASSIGNED
Signal
Name
Pin No.
Description
00·07
95·115,
13S·175
Data Bus Lines. All instruction and data
transfers take place on the data bus lines. The
buffers driving the data bus lines have full threestate capability. Each data bus pin is connected
to an input and an output buffer, with the out·
put buffer remaining in the floating condition.
AO·A9
15·8S,
Address Bus Lines. The address bus lines are
23S,24S buffered by push/pull type drivers that can drive
one standard TTL load.
A10
19S
Address Bus Line 10. This address line has the
same characteristics and functions as Lines
AO·A9.
CE
18S
CE is active when the address is 400-FFF.
This line can drive one TTL load.
OE
20S
Memory Enable Line. This signal provides the
output enable for the memory to place informa·
tion on the data bus lines. This signal is driven
by the Rm signal from the CPU and then
inverted by a standard TTL inverter, to form OE.
Vcc
24S
Main Power 5upply$5V. This pin is tied directly
to pin 30 (Vcd.
A11
21S
Address Bus Line II. This pin is tied toA11. Our·
ing backup power, power is supplied only to the
RAM memory, and not to the PROMs.
Vss
12S
Signal and Power Ground (zero volts). This pin
is tied directly to pin 12 (Vss).
400
CONTROL REGISTER
2
2
08F
08E
08B
08A
089
(3)
088
3
087
086
08S
084
083
082
081
080
UNASSIGNED
I/O
HEX
FFF
FFE
FFD
FFC
FFB
FFA
FF9
400
3FF
CLEAR PAl NEG EDGE DETECTED
CLEAR PAO POS EDGE DETECTED
UPPER LATCH AND TRANSFER
LATCH TO COUNTER
LOWER COUNT
UPPER COUNT
LOWER LATCH
UPPER LATCH
PORT 0
PORTC
PORT B
PORTA
NOT
USED
UNASSIGNED
RAM
USER RAM
03F
000
NOTES
(1) Additional 1024 bytes are decoded for external memory
addressing by the Backpack Emulator Device. This area can
be used during debug, but cannot be used In a masked
ROM R6S0011.
(2) I/O command only; I.e., no stored data.
(3) Clears Counter Overflow-Bit 7 in Control Register
(4) CAUTION: The device allows RAM mapping into 040·07F,
10o-13F, 140-17F, 200.23F, 240·27F, 300-33F, and 340-37F;
as well as 000·03F. The production R6S00/1, however
allows RAM mapping only at 000·03F.
VAA
PD7
PD6
PD5
PD4
PD3
PD2
POI
PDO
XTLI
XTLO
Vss
PC7
PC6
PCS
PC4
-PC3
PC2
PCl
PCO
RAM MAPPING
The Backpack Emulator allows RAM mapping into 040-07F,
100-13F, 140-17F, 200-23F, 240·27F, 300·33F and 340-37F, as
well as 000·03F. The production R650011, however, allows RAM
mapping only at 000·03F. This means that a write to location
40, for example, will write to location 0 in the Backpack Emulator,
and to invalid RAM in the R6500/1 production part.
1/0 PORT INITIALIZATION
Ports A, B, C, and 0 and the CNTR line in the Backpack
Emulator are initialized to the logic hil!!!..!tate two 02 clock
cycles earlier than in the R6500/1. The RES line to the device
must, however, still be held low for at least eight 02 clock
cycles after Vee reaches operating range. See timing diagram.
NMI
RES
PAO
PAl
PA2
PA3
PA4
PAS
PA6
PA7
Vee
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7
CNTR
Pin Configuration
3·59
II
Backpack Emulator
R6500/1EB and R6500/1EAB
. READ TIMING CHARACTERISTICS
1 MHz
Signal
Symbol
OE setup time from CPU
Address setup time from CPU
Memory read access time
Data stabilization time
Data hold time-Read
Address hold time
OEholdtime
Cycle Time
TOEs
TAos
TAce
Max.
Min.
Max.
Unit
-
300
300
525
-
150
150
250
100
10
30
30
0.5
10.0
ns
ns
ns
ns
ns
ns
ns
p.s
150
10
30
30
1.0
Tosu
THO
THA
THOE
Tcyc
2 MHz
Min.
-
10.0
-
READ TIMING WAVEFORMS
ADDRESS FROM
CPU
DATAFROM--~----4-----+---~
MEMORY
-n-
:;-::-"t__ _
Tasu
*q,2 IS SHOWN FOR REFERENCE ONLY AND IS NOT AVAILABLI!' EXTERNAL TO THE DEVICE.
1/0 PORT INITIALIZATION TIMING
REi -m~~
________
______________________________ -v-l
8_"':...2_C_LO_C_K_CY_C_LE_S_M_I_N_IM_U_M_ _ _ _ _ _ _
~~~~
R6500NEB
1/0
PORTS
[
~~
~
"<"""",~""",~"",,,,,,,,,,,,,,,.....----------------Irv--
R6500N ~
3·60
~
RES TRANSITION WINDOW
~
DON'T CARE STATE
R6500/1EB and R6500/1EAB
Backpack Emulator
MAXIMUM RATINGS·
Symbol
Value
Unit
Supply Voltage
Parameter
Vee
-0.3 to + 7.0
Vdc
Input Voltage
V,N
-0.3 to +7.0
Vdc
Operating Temperature
Commercial
TA
TL to TH
o to +70
·C
TSTG
-55 to + 150
·C
Storage Temperature
·NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in other sections of this document is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
DC CHARACTERISTICS
(Vee = 5.0V ±5%, Vss = OV; TA = O· to 70·, unless otherwise specified)
Symbol
Min
Typ1
Max
Input High Voltage
00-07
V,H
+2.4
-
-
V
Input Low Voltage
00-07
V,L
-
-
+O.B
V
Input Leakage Current (Three-State Off)
00-07
liN
-
-
±10.0
"A
V,N = 0.4 to 2.4V
Vcc = 5.25V
Output High Voltage (Except XTLO)
00-07, AO-A11 , OE
VOH
+2.4
-
-
V
ILOAD = -100 "A
Vss= 4.75V
Output Low Voltage
00-07, AO-A11 , OE
VOL
-
-
+0.6
V
ILOAD = 1.6 mA
Vss = 4.75V
1/0 Port Pull-Up Resistance
RL
3.0
6.0
11.5
Kohm
Input Capacitance
00-07
C'N
-
-
15
pF
TA = 25·C
V,N = OV
f = 1.0 MHz
Output Capacitance (Three-State Off)
AO-A11
COUT
-
-
12
pF
TA = 25·C
V,N = OV
f = 1.0 MHz
Power Dissipation (Less EPROM)
PD
-
BOO
1300
mW
TA = O·C
Parameter
Notes:
1. Typical values measured at TA = 25·C and Vec = 5.0V.
2. Negative sign indicates outward current flow, positive indicates inward flow.
3-61
Unit
Test Conditions
Backpack Emulator
R6500/1EB and R6500/1EAB
PACKAGE DIMENSIONS
4D-PIN BACKPACK
1.,
40
m~DDDDDDDDDDD
~~)
DD
j _I_If
000000000000
PI~1
LJ
-
20
IDENTIFICATION
2.0.0 MAX
-------1
-- J.-r----1
t 0.050 ± .020.••OMAX - - - - I .I
J1r==d~J'1
0.5~~Q~'-4
.:.-':.
±.D'O
0.050 ± 015 BOTH eNDS -
f««m~NY¥YYMYYYYY¥~
I
--III
J
r--0.100 %.010 TYP
0.018
1.900±-ivO:3
REF
3-62
0.040
--
~.~~~ TVP
01.
I
I
MIN
R6500/11-/12-/15
'1'
R6500/11 , R6500/12 and R6500/15
One-Chip Microcomputers
Rockwell
SECTION 1
INTRODUCTION
1.1 FEATURES
-
• Enhanced 6502 CPU
-Four new bit manipulation instructions:
Set Memory Bit (SMB)
Reset Memory Bit (RMB)
Branch on Bit Set (BBS)
Branch on Bit Reset (BBR)
-Decimal and binary arithmetic modes
-13 addressing modes
-True indexing
•
•
•
•
•
-
• 1 pS minimum instruction execution time @ 2 MHz
• NMOS-3 silicon gate, depletion load technology
• Single + 5V power supply
• 12 mW stand-by power for 32 bytes of the 192-byte RAM
• 40-pin DIP (R6500/11 and R6500/15)
• 44-pin PLCC (R6500/11 and R6500/15)
3K-byte mask-programmable ROM (R6500/11, R6500/12)
4K-byte mask-programmable ROM (R6500/15)
192-byte static RAM
32 TIL-compatible 110 lines (R6500/11, R6500/15)
56 TIL-compatible 110 lines (R6500/12)
• 64-pin QUIP (R6500/12)
1.2 SUMMARY
These Rockwell microcomputers are complete, highperformance 8-bit NMOS-3 microcomputers on a single chip,
and are compatible with all members of the R6500 family.
• One 8-bit port may be tri-stated under software control
• One 8-bit port with programmable latched input
• Two 16-bit programmable counter/timers, with latches
-Pulse width measurement
-Asymmetrical pulse generation
-Pulse generation
-Interval timer
-Event counter
-Retriggerable interval timer
The R6500/11 consists of an enhanced 6502 CPU, an internal
clock oscillator, 3072 bytes of Read-Only Memory, 192 bytess
of Random Access Memory (RAM) and versatile interface circuitry (Figure 1-1). The interface circuitry includes two 16-bit
programmable timer/counters, 32 bidirectional input/output lines
(including four edge-sensitive lines and input latching on one
8-bit port), a full-duplex serial 110 channel, ten interrupts and
bus expandability.
• Serial port
-Full-duplex asynchronous operation mode
-Selectable 5- to 8-bit characters
-Wake-up feature
-Synchronous shift register mode
-Standard programmable bit rates, programmable up to
62.5K bits/sec @ 1 MHz
• Ten interrupts
-Four edge-sensitive lines; two positive, two negative
-Reset
-Non-maskable
-Two counter underflows
-Serial data received
-Serial data transmitted
The R6500/15 is identical to the R6500111 except it has 4K of
ROM.
The innovative architecture and the demonstrated high performance of the R6502 CPU, as well as instruction simplicity,
results in system cost-effectiveness and a wide range of computational power. These features make either device a leading
candidate for microcomputer applications.
The R6500/12 consists of all the features of the R6500/11 plus
three additional 110 ports. It is packaged in a 64 pin QUIP.
To allow prototype circuit development, Rockwell offers a PROMcompatible 64-pin extended microprocessor device. This device,
the R6511Q, provides all R6500/11 or R6500/15 interface lines,
plus the address bus, data bus and control lines to interface with
external memory. With the addition of external circuits it can also
be used to emulate the R6500/12 (contact Rockwell sales offices
listed on the back page for details).
• Bus expandable to 16K bytes of extemal memory
• Flexible clock circuitry
-2-MHz or I-MHz internal operation
Document No. 29651N23
Internal clock with external 2 MHz to 4 MHz series
resonant XTAL at two or four times internal frequency
External clock input divided by one, two or four
Product Description
3-63
Order No. 2119
Rev. 7, June 1987
One-Chip Microcomputers
R6500/11-/12-/15
1.3 CUSTOMER OPTIONS
A backpack emulator, the R65/11 EB, is available for developing R6500111 applications. No backpack part is available for the
R6500/12.
The R6500/11 microcomputer is available with the following
customer specified mask options:
The R6511Q may also be used as a CPU-RAM-I/O counter
device in multichip systems.
Rockwell supports development of R6500/" single chip microcomputer applications with the Rockwell Design Center Low Cost
Emulator (LCE) and R65001" Personality Set. Program assembly
can be performed on any user-provided computer using an
assembler generating R6500/" machine code. The machine
code can then be downloaded via an RS-232-C serial channel
to the LCE for program debugging and in-circuit emulation. Complete in-circuit emulation with the R65ocl" Personality Set allows
total system test and evaluation. Refer to the ROC-31 01/2 LCE
and ROC-3XX R6500/" Personality Set data sheets, Order
Nos. ROC17 and ROC06, respectively, for additional information.
Crystal oscillator
• Option 2
Clock divide-by-2 or divide-by-4
• Option 3 Clock MASTER Mode or SLAVE Mode
• Option 4
Port A with or without internal pull-up resistors
• Option 5
Port B with or without internal pull-up resistors
• Option 6
Port C with or without internal pull-up resistors
All options should be specified on an R650C/ll , 112 or 115 order
form.
The R6500/12 is available with all of the above options plus:
This product description is for the reader familiar with the R6502
CPU hardware and programming capabilities. A detailed description of the R6502 CPU hardware is included in the R6500
Microcomputer System Hardware Manual (Order Number 201).
A description of the instruction capabilities of the R6502 CPU
is contained in the R6500 Microcomputer System Programming
Manual (Order Number 202).
XTLO
• Option 1
• Option 7
Port F with or without internal pull-up resistors
• Option 8
Port G with or without internal pull-up resistors
Refer to the R65001" ROM Code Order Forms (Order Number 2134) for detail option ordering information.
r-----~
••=~=~~' O·r·=·=~=~~1.______,
XTLI
v'"
PAO-PA7 (PAD, PA1,
POSITIVE: PA2, PAl
NEGATIVE EDGE DETECTS)
Vee
PBD-PB7 (LATCHED INPUTS)
v..
'2
DS(PAO} (INPUT DATA STROBE)·
PCO-PC7/(Ao..A3, A12.
RIW • .1.13, Elm)
PDO-PD7/DATA BUS (DCI-D7)
ADDR BUS 1.1.4-.1.1')
so ("')'
SI(PAl)'
PEO-PE7
R&5OD/12
1. A8500/11 OR ReSOO/12
2. H6500/15
-MULTIPLEXED FUNCTION PINS
Figure 1-1,
R6500/11, R6500112 and R6500115 Interface Signals
3-64
One-Chip Microcomputers
R6500/11-112-/15
SECTION 2
INTERFACE REQUIREMENTS
This section describes the interface requirements for the single
chip microcomputer devices. Figures 2-1 and 2-2 show the
pin assignments and Table 2-1 describes the function of each
pin. Figures 2-3 and 2-4 show the package dimensions.
-
XTLO
XTLI
02
PCO/AO
PCI/Al
PC2/A2
PC3/A3
PC4/AI2
pcs/RiW
PC6/A13
PC7/EMS
P07/Al1/07
P06/Al0/06
POS/A9/0S
P04/A8/04
P03/A7/03
P02/A6/02
POI/AS/Ol
POO/A4/00
RES
0
:!:!
v"
_0
~~~~~~;~J~f
VRR
PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7
PAO
PAl
PA2
PA3
PA4
PAS
PA8
PA7
~
~
~
~
~
~
~
'lit
PC2/A2
PC3/A3
PC4/AI2
PCS/RIW
PC6/AI3
PC7/EMS
P07/Al1/07
P06/Al0/06
POS/A9/05
P04/A8/04
P03/A7ID3
~
N
_
........
PIN 1
INDICATOR
10
11
12
13
14
15
16
17
=~~N~~~~~~~
~~~!~~~~I~::f
NMI
......
~~:!
N_O
Vee
ccc
40-PIN DIP
44-PIN PLCC
Figure 2-1.
0
..,
0
R6500111 and R6500/15 Pin Assignments
PB7
PB6
PB5
PB4
PB3
PB2
PBl
PBO
XTLO
XTLI
V••
VRR
64
63
62
61
60
S9
58
57
56
S5
54
53
52
51
50
49
4B
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
02
PGS
PG6
PG7
PF7
PF6
PF5
PF4
PF3
PF2
PFI
PFO
PCO/AO
PCI/Al
PC2/A2
PC3/A3
PC4/AI2
pC5/RiW
PC6/AI3
PC7/EMS
PAO
PAl
PA2
PA3
PA4
PAS
PA6
PA7
PG4
PG3
PG2
PGl
PGO
NMI
Vee
PEO
PEl
PE2
PE3
PE4
PES
PE6
PE7
RES
POO/A4/0D
POI/AS/Ol
P02/A6/02
PD3/A7/D3
P04/AB/04
P05/A9/0S
P06lAl01D6
P07/Al1/07
64-PIN QUIP
Figure 2-2.
R6500/12 Pin Assignments
3-65
39
38
37
36
3S
34
33
32
31
30
29
PB2
PB3
PB4
PBS
PB6
PB7
PAO
PAl
PA2
PA3
PA4
One-Chip Microcomputers
R6500/11-/12-/15
Table 2-1.
Pin Descriptions
1/0
Pin Number
Signal Name
Description
Vee
Main power supply + SV.
VRR
Separate power pin for RAM. In the event that Vee power is lost, this power retains RAM data.
Signal and power ground (OV).
Vss
XTLI
I
Crystal or clock input for internal clock oscillator. Also allows input of Xt clock signal if XTLO is connected
to Vss or X2 or X4 clock if XTLO is floated.
XTLO
0
Crystal output from internal clock oscillator.
RES
I
The Reset input is used to initialize the device. This signal must not transition from low to high for at
least eight cycles after Vee reaches operating range and the internal oscillator is stabilized.
02
I
Clock signal output at internal frequency.
NMI
I
A negative going edge on the Non·Maskable interrupt signal requests that a non·maskable interrupt be
generated within the CPU.
1/0
Four B-bit ports used for either input/output. Each line of Ports A, Band C consists of an active transistor
to Vss and an optional passive pull-up to Vce. In the abbreviated or multiplexed modes of operation Port C
has an active pull-up transistor. Port D functions as either an B-bit input or B-bit output port. It has active
pull-up and pull-down transistors.
PAO-PA7
PBO-PB7
PCO-PC7
PDO-PD7
110
110
110
PEO-PE7
PFO-PF7
PGO-PG7
0
110
110
For the R5S00/t2, the 54-pin QUIP version, three additional ports (24 lines) are provided. Each line consists
of an active transistor to Vss. PFO-PF7 and PGO-PG7 are bidirectional, and an optional passive pull-up
to Vee is provided. PEO-PE7 is outputs only with an active pull-up. All ports will source tOO ~amps at
2.4V except port E (PEO-PE7) which will source 1 mA at I.SV.
64 PIN PLASTIC QUIP
DIM
-t
_t
'mnmmmmmr,,",,",",,""",,1'11"I11T'I111
Figure 2-3.
64-PIN QUIP Dimensions
3-66
INCHES
MIN
MAX
F
G
H
J
K
L
1.620
0.670
0.120
0.024
0.050
0.100
0.040
0.110
0.745
0.045
7·
0.170
0.755
M
23.37
0.920
0.930
D
B
MILLIMETERS
MIN
MAX
41.15 41.66
17.02 17.53
4.56
3.05
0.38
0.51
1.27 esc
2.54 BSC
1.02
1.14
7·
2.75
4.32
18.92
19.81
A
B
C
23.62
1.640
0.690
0.180
0.020
esc
esc
One-Chip Microcomputers
R6500/11-/12-/15
PACKAGE DIMENSIONS
40-PIN PLASTIC DIP
40-PIN PLASTIC DIP
MILLIMETERS
I:~:::: ::::: :::: :::::p
•
A
•
MIN
MAX
A
51.B2
52.32
2.040
2060
B
13.46
1397
0.530
0550
Cili
--JGf-
F
0
K
M
MAX
MIN
C
3.56
50B
0.140
0.200
D
0.38
0.53
0015
0021
F
102
152
0040
asc
254
G
-+
~~
1HI+
INCHES
DIM
I
I
H
165
J
K
020
,"0
L
1524
216
0.065
0.30
4.32
0.008
esc
I
M
70
N
051~ 1.02
10 0
0.060
0.100
esc
0085
0.012
0.170
0.130
0600
esc
70
100
0020
0.040
44-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
".,,~g@
I~t:,
rrr
lH ""'
CORNER
02-1
?
6
~
L
'I
2.
X
3•
~r~~~
e0
·05
~
.~
e
+
5
J
~.~
CHAM.
h X 45·
3 PlCS
11 PINS
PER SIDE
EQUAllY
SPACES
MIN
MAX
A
4.14
4.39
0.163
0.173
Al
1.37
1.47
0.054
0.058
A2
2.31
2.46
0.091
0097
0.457 TVP
0.Q18 TVP
D
17.45
17.60
0.6B7
16.46
1656
0.648
I 0.693
L0.652
~
D2
12.62
12.78
0.497
0503
D3
.
~~.
'~
R
SECTION A·A
TYP FOR BOTH AXIS (EXCEPT FOR BEVELED EDGE)
oI~b
EJECTOR PIN MARKS
4 PlCS BOTTOM OF
PACKAGE ONLY
(TYPICAL)
VU1J
oI!-ce
MAX
Dl
~A
UUi.n..
INCHES
MIN
~
~
45·
MILLIMETERS
DIM
b
SIDE VIEW
TOP VIEW
l~
~F\
i
INDICATOR
CHAM.J
SEATING PLANE
:,(1
3'-
-17
~
BOTTOM VIEW
3-67
15.75 REF
0.620 REF
esc
1.27 BSC
0.050
h
1.15 TYP
0.045 TYP
0.010 TYP
J
0.25 TVP
a
45 0 TVP
45 0 TVP
R
0.89 TVP
0.035 TYP
Rl
025 TVP
0010 TYP
R6500/11-/12-/15
One-Chip Microcomputers
SECTION 3
SYSTEM ARCHITECTURE
location is stored (or "pushed") anto the stack. Each time
data are to be pushed onto the stack, the Stack Pointer is
placed on the Address Bus, data are written into the memory
location addressed by the Stack Pointer, and the Stack
Pointer is decremented by 1. Each time data are read (or
"pulled") from the stack, the Stack Pointer is incremented by
1. The Stack Pointer is then placed on the Address Bus, and
data are read from the memory location addressed by the
Pointer.
This section provides a functional description of the devices.
Functionally they consist of a CPU, both ROM and RAM memories, four B-bit parallel I/O ports (seven in the 64-pin versions),
a serial I/O port, dual counter/latch circuits, a mode control
register, and an interrupt flag/enable dual register circuit. A
block diagram of the system is shown in Figure 3-1.
NOTE
Throughout this document, unless specified otherwise,
all memory or register address locations are specified
in hexadecimal notation.
The stack is located on zero page, i.e., memory locations
00FF-0040. After reset, which leaves the Stack Pointer
indeterminate, normal usage calls for its initialization at OOFF.
3.1 CPU LOGIC
3.1.4 Arithmetic And Logic Unit (ALU)
The internal CPU is a standard 6502 configuration with an
8-bit Accumulator register, two 8-bit Index Registers (X and
V); an 8-bit Stack Pointer register, an AlU, a 16-bit Program
Counter, and standard instruction register/decode and internal
timing control logic.
All arithmetic and logic operations take place in the AlU,
including incrementing and decrementing internal registers
(except the Program Counter). The AlU cannot store data
for more than one cycle. If data are placed on the inputs to
the AlU at the beginning of a cycle, the result is always gated
into one of the storage registers or to external memory during
the next cycle.
3.1.1 Accumulator
The accumulator is a general purpose 8-bit register that
stores the results of most arithmetic and logic operations. In
addition, the accumulator usually contains one of the two
data words used in these operations.
Each bit of the AlU has two inputs. These inputs can be tied
to various internal buses or to a logic zero; the AlU then
generates the function (AND, OR, SUM, and so on) using
the data on the two inputs.
3.1.2 Index Registers
3.1.5 Program Counter
There are two 8·bit index registers, X and Y. Each index register can be used as a base to modify the address data program counter and thus obtain a new address-the sum of
the program counter contents and the index register contents.
The 16-bit Program Counter provides the addresses that are
used to step the processor through sequential instructions
in a program. Each time the processor fetches an instruction!
from program memory, the lower (least significant) byte of
the Program Counter (PCl) is placed on the low-order bits
of the Address Bus and the higher (most significant) byte of
the Program Counter (PCH) is placed on the high-order 8
bits of the Address Bus. The Counter is incremented each
time an instruction or data is fetched from program memory.
When executing an instruction which specifies indirect
addressing, the CPU fetches the op code and the address,
and modifies the address from memory by adding the index
register to it prior to loading or storing the value of memory.
Indexing greatly simplifies many types of programs, especially those using data tables.
3.1.6 Instruction Register and Instruction Decode
3.1.3 Stack Pointer
Instructions are fetched from ROM or RAM and gated onto
the Internal Data Bus. These instructions are latched into the
Instruction Register then decoded along with timing and
interrupt signals to generate control signals for the various
registers.
The Stack Pointer is an 8-bit register. It is automatically
incremented and decremented under control of the microprocessor to perform stack manipulation in response to either
user instructions, an internal IRQ interrupt, or the external
interrupt line NMI. The Stack Pointer must be initialized by
the user program.
3.1.7 Timing Control
The Timing Control logic keeps track of the specific instruction cycle being executed. This logic is set to TO each time
an instruction fetch is executed and is advanced at the
beginning of each Phase One clock pulse for as many cycles
'as are required to complete the instruction. Each data transfer
which takes place between the registers is caused by
decoding the contents of both the instruction register and
timing control unit.
The stack allows simple implementation of multiple level
interrupts, subroutine nesting and simplHication of many types
of data manipulation. The JSR, BRK, RTI and RTS instructions use the stack and Stack Pointer.
The stack can be envisioned as a deck of cards which may
only be accessed from the top. The address of a memory
3-68
~~
L=-.J
~
:a
en
U1
o
g...
::.:•
N
::.:•
U1
4>
en
CD
o
~
(I)
I
o
:::T
"C
s:
PGO-PGl'
PFO.PF1'
PEe.PD'
0'
,R
a
(')
o
NMi
"A6f1OO1120n1y
"R6SOO'1SOnly
3
"C
C
Figure 3-1.
;-
System Block Diagram
a
Ul
One-Chip Microcomputers
R6500/11-/12 -/15
3.1.8 Interrupt Logic
3.3 READ·ONlY·MEMORY (ROM)
Interrupt logic controls the sequencing of three interrupts;
RES, NMI and IRQ. IRQ is generated by anyone of eight
conditions: 2 Counter Overflows, 2 Positive Edge Detects,
2 Negative Edge Detects, and 2 Serial Port Conditions.
In the R6500/11 or R6500/12 the ROM consists of 3072 by1es
(3K) of mask programmable memory with an address space
from F400 to FFFF. ROM locations FFFA through FFFF are
assigned for interrupt and reset vectors.
3.2 NEW INSTRUCTIONS
In the R6500/15 the ROM consists of 4096 by1es (4K) of mask
programmable memory with an address space from FOOO to
FFFF. ROM locations FFFA through FFFF are assigned for
interrupt and reset vectors.
In addition to the standard 6502 instruction set, four instruc·
tions have been added to the devices to simplify operations
that previously required a read/modify/write operation. In
order for these instructions to be equally applicable to any
VO ports, wnh or wnhout mixed input and output functions,
the VO ports have been designed to read the contents of the
specified port data register during the Read cycle of the read/
modify/write operation, rather than VO pins as in normal read
cycles. The added instructions and their format are explained
in the following subparagraphs. Refer to Appendix A for the
Op Code mnemonic addressing matrix for these added
instructions.
3.4 RANDOM ACCESS MEMORY (RAM)
The RAM consists of 192 bytes of read/write memory with
an assigned page zero address of 0040 through OOFF. The
R6500/11 provides a separate power pin (VRR ) which may be
used for standby power for 32 bytes located at 0040-005F.
In the event of the loss of Vee power, the lowest 32 bytes of
RAM data will be retained if standby power is supplied to the
VRR pin. If the RAM data retention is not required then VRR
must be connected to Vee. During operation VRR must be at
the Vee level.
3.2.1 Set Memory Bit (SMB m, Addr.)
For the RAM to retain data upon loss of Vee, VRR must be
supplied within operating range and RES must be driven low
at least eight 02 clock pulses before Vee falls out of operating
range. RES must then be held low while Vee is out of operating range and until at least eight 02 clock cycles after Vee
is again within operating range and the internal ~2 oscillator
is stabilized. VRR must remain within Vee operating range
during normal operation. When Vee is out of operating range,
V RR must remain within the VRR retention range in order to
retain data. Figure 3.2 shows typical waveforms.
This instruction sets to "1" one of the 8-bit data field specified
by the zero page address (memory or I/O port). The first byte
of the instruction specifies the 5MB operation and 1 of 8 bits
to be set. The second byte of the instruction designates
address (OO-FF) of the byte or I/O port to be operated upon.
3.2.2 Reset Memory Bit (RMB m, Addr.)
This instruction is the same operation and format as 5MB
instruction except a reset to "0" of the bit results.
3.2.3 Branch On Bit Set Relative (BBS m, Addr,
DEST)
RAM OPERATING MODE
RAM RETENTION MODE
:::~
~ -- ~-l'=-=~f~ I r--
~~
__ l
This instruction tests one of 8 bits designated by a three bit
immediate field within the first by1e of the instruction. The
second by1e is used to designate the address of the by1e to
be tested within the zero page address range (memory or
I/O ports). The third by1e of the instruction is used to specify
the 8 bit relative address to which the instruction branches
if the bit tested is a "1". If the bit tested is not set, the next
sequential instruction is executed.
VRRO
,
1
2
3
4
5
3.2.4 Branch On Bit Reset Relative (BBR m,
Addr,DEST)
This instruction is the same operation and format as the BBS
instruction except that a branch takes place if the bit tested
is a "0".
~®____.~~
8112 CLOCK PULSES AFTER OSCILLATOR STABILIZATION.
>8112 CLOCK PULSES.
Data Retention Timing
One-Chip Microcomputers
R6500/11-/12-/15
3.5 CLOCK OSCILLATOR
For example, if CL = 22 pF for a 4 MHz parallel resonant crystal,
then
Customer selectable mask options are available for controlling the
device timing. It can be ordered with a crystal oscillator, a divideby-2 ordivide-by-4 countdown network and for clock master mode
or clock slave mode operation.
C = (2 x 22) - 27 = 17 pF
(use standard value of 18 pF)
Note:
The series resistance of the crystal must be less than
For 2 MHz internal operations the divide-by-two option must
be specified.
Rsmax
The on-chip oscillator is designed for a parallel resonant crystal
connected between XTLI and XTLO pins. The equivalent oscillator circuit is shown in Figure 3-3a.
= 2C L
or
C
= 2CL -
(FCd 2
where: F is in MHz; C and CL are in pF; R is in ohms.z
To select a parallel resonant crystal for the oscillator, first select
the load capacitance from a crystal manufacturer's catalog. Next,
calculate Rsmax based on F and CL• The selected crystal must
have a Rs less than the Rsmax.
C 6'-'""'
T
-:"
XTAL
C±5%
XTLO{
One device is operated in the CLOCK MASTER MODE and a
second in the CLOCK SLAVE MODE. Mask options in the SLAVE
unit convert the 02 signal into a clock input pin which is tightly coupled to the internal timing generator. As a result the internal timing of the MASTER and SLAVE units are synchronized with minimum skew. If the 02 signal to the SLAVE unit is inverted, the
MASTER and SLAVE UNITS WILL OPERATE OUT OF PHASE.
This approach allows the two devices to share external memory
using cycle stealing techniques.
27pF
XTLI
1 d"~"
27pF
= 258 ohms
The operation described above assumed a CLOCK MASTER
MODE mask option. In this mode a frequence souce (crystal or
external source) must be applied to the XTLI and XTLO pins. 02
is a buffered output signal which closely approximates the internal timing. When a common external source is used to drive mUltiple devices the internal timing between devices as well as their
02 outputs will be skewed in time. If skewing represents a system
problem it can be avoided by the Master/Slave connection and
options shown in Figure 3-4.
27 pF
Rs s Rsmax = 2 X 10·
C±5%
2 X 10·
(4 X 22)2
Internal timing can also be controlled by driving the XTLI pin with
an external frequency source. Figure 3-3b shows typical connections. If XTLO is left floating, the external source is divided by the
internal countdown network. However, if XTLO is tied to Vss, the
internal countdown network is bypassed causing the chip to operate at the frequency of the external source.
A parallel resonant crystal is specified by its load capacitance and
series resonant resistance. For proper oscillator operation, the load
capacitance (CLl, series resistance (Rs) and the crystal resonant
frequency (F) must meet the following two relations:
(C + 27)
=
-=
A. CRVSTAL INPUT
R65DDI11 OR 112
H.",~
R65DD/11
NC
XTLO
XTLI
liNT
:52 MHz
.,2
c:::J*
DIVIDE-BY-2 OR
DIVIDE-BV-4
(OUTPUT CLOCK)
MASTER
XTLO
INVERTER USED
f-- --1 WHEN SLAVE IS
"'."'~'
R6500/11
R65DDI11 OR 112
liNT
:52 MHz
:
L__
i TO OPERATE
__.J
OUT OF PHASE
WITH MASTER
XTLI
DIVIDE·BV·1
SLAVE
XTLO
(INPUT CLOCK)
Vss ~
B.CLOCKINPUTS
Figure 3·3.
Clock Oscillator Input Options
Figure 3·4.
3-71
Master/Slave Connections
One-Chip Microcomputers
R6500/11 e /12 e /15
3.7 INTERRUPT FLAG REGISTER (IFR)
AND INTERRUPT ENABLE
REGISTER (IER)
3.6 MODE CONTROL REGISTER (MCR)
The Mode Control Register contains control bits for the multifunction I/O ports and mode select bits for Counter A and
Counter B. Its setting, along with the setting of the Serial
Communications Control Register (SCCR), determines the
basic configuration of the device in any application. Initializing this register is one of the first actions of any software
program. The Mode Control Register bit assignment is shown
in Figure 3-5.
MCR
An IRQ interrupt request can be initiated by any or all of eight
possible sources. These sources are all capable of being
enabled or disabled by the use of the appropriate interrupt
enabled bits in the Interrupt Enable Register (IER). Multiple
simultaneous interrupts will cause the IRQ interrupt request
to remain active until all interrupting conditions have been
serviced and cleared.
The Interrupt Flag Register contains the information that
indicates which I/O or counter needs attention. The contents
of the Interrupt Flag Register may be examined at any time
by reading at address: 0011. Edge detect IFR bits may be
cleared by executing a RMB instruction at address location
0010. The RMB X, (0010) instruction reads FF, modifies bit
X to a "0", and writes the modified value at address location
0011. In this way IFR bits set to a "1" after the read cycle of
a Read-Modify-Write instruction (such as RMB) are protected
from being cleared. A logic "1" is ignored when writing to
edge detect IFR bits.
Addr 0014
Counter B
I I
Mode select
Bus Mode select
0 - 0 Interval Timer
01 Pulse Generation
1 - 0 Event Counter
1_
1 Pulse Width Meas.
0 - 0 Interval Timer
o1 Asymmetric Pulse Generation
1_
0 Event Counter
1_
1 Retriggerable Interval Timer
Port B Latch
(1 = Enabled)
Port D Trl-State
(0= Tti State High Impedance Mode)'
Each IFR bit has a corresponding bit in the Interrupt Enable
Register which can be set to a "1" by wrHing a "1" in the
respective bit pOSition at location 0012. Individual IER bits
may be cleared by writing a "0" in the respective bit position,
or by RES. If set to a "1", an IRQ will be generated when the
corresponding IFR bit becomes true. The Interrupt Flag Register and Interrupt Enable Register bit assignments are shown
in Figure 3-6 and the functions of each bit are explained in
Table 3-1.
O-XNonnal
11_
0 Abbr. Bus
1 Mux'd Bus
Figure 3-5.
Mode Control Register
The use of Counter A Mode Select is shown in Section 6.1.
The use of Counter B Mode Select is shown in Section 6.2.
The use of Port B Latch Enable is shown in Section 4.4.
The use of Port D in Tri-State Enable is shown in Section
4.6.
The use of Bus Mode Select is shown in Section 4.5 and 4.6.
3-72
R6500/11-/12-/15
One-Chip Microcomputers
Addr 0012
IER
Addr 0011
IFR
PAD Positive
Edge Detect
PA1 Positive
Edge Detect
PA2 Negative
Edge Detect
PA3 Negative
Edge Deleet
Counter A
Und_rflow Flag
Counter B
Underflow Flag
Receiver
Flag
XMTR
Flag
Figure 3·6.
Interrupt Enable and Flag Registers
Table 3·1. Interrupt Flag Register Bit Codes
BIT
CODE
FUNcnON
IFR 0:
PAO Positive Edge Detect Flag-Set to a "1" when a positive going edge is detected on PAO.
Cleared by RMB 0 (0010) instruction or by RES.
IFR 1:
PAl Positive Edge Detect Flag-Set to a ~en a positive going edge is detected on PAl.
Cleared by RMB 1 (0010) instruction or by RES.
IFR2:
PA2 Negative Edge Detect Flag-Set to a 1 when a negative going edge is detected on PA2.
Cleared by RMB 2 (0010) instruction or by RES.
IFR3:
PA3 Negative Edge Detect Flag-Set to 1 when a negative going edge is detected on PA3.
Cleared by RMB 3 (0010) instruction or by RES.
IFR 4:
Counter A Underflow Flag-Set to a 1 when Counter A underflow occurs. Cleared by reading
the Lower Counter A at location 0018. by writing to address location 001A. or by RES.
IFR5:
Counter B Underflow Flag-Set to a 1 when Counter B underflow occurs. Cleared~reading
the Lower Counter B at location 001C, by writing to address location 001E, or by RES.
IFR 6:
Receiver Interrupt Flag-Set to a 1 when any of the Serial Communication Status Register bits
o through 3 is set to a 1. Cleared when the Receiver Status bits (SCSR 0-3) are cleared or by
RES.
IFR 7:
TransmiHer Interrupt Flag-Set to a 1 when SCSR 6 is set to a 1 while SCSR 5 is a 0 or SCSR
7 is set to a 1. Cleared when the Transmitter Status bits (SCSR 6 & 7) are cleared or by RES.
3-73
One-Chip Microcomputers
R6500/11·/12·/15
zero. This bit fs cleared to logic D when the resultant a bits
of a data movement or calculation operation are not all zero.
The R65DD instruction set contains no instruction to specifically set or clear the Zero Bit. The Zero Bit is, however,
affected by the following instructions; ADC, AND, ASL, BIT,
CMP, CPX, CPY, DEC, DEX, DEY, EOR, INC, INX, INY,
LDA,'LDX, LOY, LSR, ORA, PLA, PLP, ROL, ROR, RTI,
SBC, TAX, TAY, TXA, TSX, and TVA.
3.8 PROCESSOR STATUS REGISTER
The a-bit Processor Status Register, shown in Figure 3-7,
contains seven status flags. Some of these flags are controlled by the user program; others may be controlled both
by the user's program and the CPU. The R6502 instruction
set contains a number of conditional branch instructions
which are designed to allow testing of these flags. Each of
the eight processor status flags is described in the following
sections.
3.8.3 Interrupt Disable Bit (I)
The carry Bit (C) can be considered as the ninth bit of an
arithmetic operation. It is set to logic 1 if a carry from the
eighth bit has occurred or cleared to logic D if no carry
occurred as the result of arithmetic operations.
The Interrupt Disable Bit (I) is used to control the servicing
of an interrupt request (IRQ). If the I Bit is reset to logic D,
the IRQ signal will be serviced. If the bit is set to logic 1, the
IRQ signal will be ignored. The CPU will set the Interrupt
Disable Bit to logic 1 if a RESET (RES), IRQ, or Non-Maskable Interrupt (NMI) signal is detected.
The Carry Bit may be set or cleared under program control
by use of the Set Carry (SEC) or Clear Carry (CLC) instruction, respectively. Other operations which affect the Carry Bit
are ADC, ASL, CMP, CPX, CPY, LSR, PLP, ROL, ROR, RTI,
and SBC.
The I bit is cleared by the Clear Interrupt Mask Instruction
(CLI) and is set by the Set Interrupt Mask Instruction (SEI).
This bit is set by the BRK Instruction. The Return from Interrupt (RTI) and Pull Processor Status (PLP) instructions will
also affect the I bit.
3.8.1 Carry Bit (C)
3.8.2 Zero Bit (Z)
The Zero Bit (Z) is set to logic 1 by the CPU during any data
movement or calculation which sets all a bits of the result to
INlv\
lelDII\zlcJ
l=;
= carry Set
= Carry Clear
ZERO(Z)Q)
1
= Zero Result
o =Non-Zero Result
INTERRUPT DISABLE (Il:!>
1 = IRQ Interrupt Disabled
o :: IRQ Interrupt Enabled
DECIMAL MODE (D)
CD
1 :: Decimal Mode
o :: Binary Mode
eREAK COMMAND (e) Q)
1 _ Break Command
o .; Non Break Command
OVERFLOW (O)Q)
1:: Overtlow Set
0:: Overflow Clear
NEGATIVE (N)Q)
. NOTES
Not Initialized by RES
2.4V) output while a logic 0 will force a low
«0.4V) output.
va
4.2 OUTPUTS
va
Table 4-1.
1/0 Port Addresses
Port
Address
A
0000
0001
0002
0003
0004
0005
0006
B
C
0
E
F
G
Port 0 all outputs is selected by setting MCRS to a "1".
Port E is always all outputs.
4.3 PORT A (PA)
Port A can be programmed via the Mode Control Register
(MCR) and the Serial Communications Control Register
(SCCR) as a standard parallel S-bit, bit independent, VO port
or as serial channel
lines, counter VO lines, or an input
data strobe for the Port B input latch option. Table 4-2 tabulates the control and usage of Port A.
va
4.1 INPUTS
In addition to their normal VO functions, PAO and PA1 can
detect positive going edges, and PA2 and PA3 can detect
negative going edges. A proper transition on these pins will
set a corresponding status bit in the IFR and generate an
interrupt request if the respective Interrupt Enable Bit is set.
The maximum rate at which an edge can be detected is onehalf the 02 clock rate. Edge detection timing is shown in Section E.S.
Inputs for Ports A, B, and C and also Ports F and G of the
R6500/12 are enabled by loading logic 1 into all 110 port
register bit positions that are to correspond to 1/0 input lines.
A low «O.SV) input signal will cause a logic 0 to be read when
a read instruction is issued to the port register. A high (>2.0V)
input will cause a logic 1 to be read. An RES signal forces
all 110 port registers to logic 1 thus initially treating all 1/0 lines
as inputs.
3-76
R6500/11-/12-/15
One-Chip Microcomputers
Table 4-2.
Port A Control & Usage
PAO I/O
PORT B LATCH MODE
MCR4 = 0
MCR4 = I
SIGNAL
PAO(2)
SIGNAL
NAME
TYPE
NAME
TYPE
PAO
I/O
PORTB
LATCH STROBE
INPUT (I)
PAI-PA31/0
PA1 (2)
SIGNAL
PA2(3)
NAME
TYPE
PA3(3)
PAl
PA2
PA3
I/O
I/O
I/O
COUNTER A I/O
PA41/0
PA4
MCRO = 0
MCRI = 0
SCCR? = 0
RCVR SIR MODE = 0
(4) (5)
SCCR? = 0
SCCRS = 0
MCRI = I
MCRO = I
MCRI = 0
SCCR? = 0
RCVR SIR MODE = 0
(4)
SIGNAL
SIGNAL
SIGNAL
NAME
TYPE
NAME
TYPE
NAME
PA4
I/O
CNTA
OUTPUT
CNTA
I
I
TYPE
INPUT (I)
SERIAL I/O SHIFT REGISTER CLOCK
RCVR SIR MODE = I
(4)
SCCR? = I
SCCR5 = I
SIGNAL
SIGNAL
NAME
XMTR CLOCK
J
I
TYPE
NAME
OUTPUT
RCVRCLOCK
MCR3 = I
MCR2 = X
MCR3 = 0
MCR2 = I
SIGNAL
SIGNAL
SIGNAL
NAME
TYPE
NAME
TYPE
NAME
PAS
I/O
CNTB
OUTPUT
CNTB
PA6
PA61/0
SERIAL I/O
XMTR OUTPUT
SCCR? = 0
SCCR? = I
SIGNAL
SIGNAL
NAME
TYPE
NAME
TYPE
PA6
I/O
XMTR
OUTPUT
PA7
TYPE
INPUT (I)
COUNTER B 1/0
PAS I/O
MCR3 = 0
MCR2 = 0
PAS
I
I
PA?IIO
SERIAL I/O
RCVRINPUT
SCCR6 = 0
SCCRS = I
SIGNAL
SIGNAL
NAME
TYPE
NAME
TYPE
PAl
I/O
RCVR
INPUT (I)
3·77
I
I
TYPE
INPUT (I)
Noles:
(I) Hardware Buffer Floal
(2) Pos~ive Edge Detect
(3) Negative Edge Detect
(4) RCVR SIR Mode = I when
SCCRS • SCCRS • SCCR4 = I
(5) For the following mode combina·
tlons PA4 is available as an input
only pin:
SCCR?·SCCR60SCCR5.MCRI
+SCCR7·SCCR60SCCR4.MCRI
+ SCCR?'SCCR&SCCR5
+ SCCR?·SCCRSoSCCR40
One-Chip Microcomputers
R6500/11-/12-115
output drivers can be selected as tri-state drivers by setting
bit 5 of the MCR to 0 (zero). Table 4-5 shows the necessary
settings for the MCR to achieve the various modes for Port
D. When Port D is selected to operate in the Abbreviated
Mode PDO-PD7 serves as data register bits DO-D7. When
Port D is selected to operate in the MuHiplexed Mode data
bits DO through D7 are time multiplexed with address bits A4
through All, respectively. Refer to the Memory Maps
(Appendix C) for Abbreviated and MuHiplexed memory
assignments. See Appendix E.3 through E.5 for Port D timing.
4.4 PORT B (PB)
Port B can be programmed as an 8 bit, bit independent VO
port. It has a latched input capability which may be enabled
or disabled via the Mode Control Register (MCR). Table
4-3 tabulates the control and usage of Port B. An Input Data
Strobe signal must be provided thru PAO when Port B is programmed to be used with latched input option. Input data
latch timing for Port B is shown in Section E.5.
Table 4-3. Port B Control & Usage
Latch
Mode
110 Mode
4.7 PORT E, PORT F AND PORT G (PE,
PF & PG R6500/12 ONLY
MCR4 = 1
Pin
Name
MCR4 = 0
Signal
Type (1)
Name
(2)
Port E only operates in'the Output mode. It provides a Darlington output that can source current at the high (1) level.
Port F and Port G operate identically and can be programmed as bidirectional VO ports. They have standard
output capability. See Appendix E.5 for Port E, F & Port G
timing.
Signal
Name
PBO
PBO
1/0
PBO
PBl
PBl
PBl
1/0
PB2
PB2
PB2
1/0
PB3
PB3
1/0
PB3
PB4
1/0
PB4
PB4
PBS
1/0
PBS
PBS
PB6
1/0
PBS
PB6
PB7
1/0
PB7
PB7
(1) Resistive pull-up, active buffer pull down
(2) Input data Is stored In port B latch by PAO pulse
Type
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
4.8 BUS MODES
4.5 PORT C (PC)
In the Abbreviated Bus Mode, Port C and Port D are automatically transformed into an abbreviated address bus and control
signals (Port C) and a bidirectional data bus (Port D).
64 Peripheral addresses can be selected. In general usage,
these 64 addresses would be distributed to several external
1/0 devices such as R6522 and R6520, etc., each of which may
contain more than one unique address.
Port C can be programmed as an I/O port and in conjunction
with Port D, as an abbreviated bus, or as a multiplexed bus.
When used in the abbreviated or muHiplexed bus modes,
PCO-PC7 function as AO-A3, A12, R/W, A13, and EMS,
respectively, as shown in Table 4-4. EMS (External Memory
Select) is asserted (low) whenever the internal processor
accesses memory area between 0100 and 3FFF. (See
Memory Map, Appendix B). The leading edge of EMS may
be used to strobe the eight address lines multiplexed on Port
D in the Multiplexed Bus Mode. See Appendix E.3 through
E.5 for Port C timing.
In the Multiplexed Bus Mode, the operation is similar to the
Abbreviated Mode except that a full 16K of external addresses
are provided. Port C provides the lower addresses and control
signals. Port D multiplexes functions. During the first half of the
cycle it contains the remaining necessary 8 address bits for
16K; during the second half of the cycle it contains a bidirectional data bus. The address bits appearing on Port D must be
latched into an external holding register. The leading edge of
EMS, which indicates that the bus function is active, may be
used for this purpose.
4.6 PORT 0 (PO)
MCR5 must be a logic 1 in the Abbreviated and Multiplexed
Bus Modes.
Port D can be programmed as an I/O Port, an 8-bit tri-state
data bus, or as a multiplexed bus. Mode selection for Port
D is made by the Mode Control Register (MCR). The Port D
Figures 4-1 a through 4-1c show the possible configurations of
the four bus modes.
3-78
One-Chip Microcomputers
R6500111-/12-115
,,,-----+1
,.. -----+1
"'-----+1
RES-----1
I'~
..... .-:...__,,)
PORTS
I'~
..... _ _ _/)
PORTO
,,------1
INTERNAL 110
ORNEMORY
.....,,,
.,,,
ACTIVE FROM
F::'uL,LL)
a
a
The Interval Timer, Pulse Generation, and Pulse Width Measurement Modes are ~2 clock counter modes. The Event
Counter Mode counts the occurrences of an external event
on the CNTR line.
Counter A consists of a 16-bit counter and a 16-bit latch
organized as follows: Lower Counter A (LCA), Upper Counter
A (UCA), Lower Latch A (LLA), and Upper Latch A (ULA).
The counter contains the count of either ¢2 ciock pulses or
external events, depending on the counter mode selected.
The contents of Counter A may be read any time by executing a read at location 0019 for the Upper Counter A and
at location 001A or location 0018 for the Lower Counter A.
A read at location 001B also clears the Counter A Underflow
Flag (IFR4).
COUNTER
MCRO
(bit 0)
1
1
6.1 COUNTER A
'2
MCR1
(bit 1)
Interval Timer Timing Diagram
3-B3
One-Chip Microcomputers
R6500111-/12-115
While the timer is operating in the Interval Timer Mode, PA4
operates as a PA I/O bit.
The Counter A underflow flag will be set only when the count
in the timer reaches zero. Upon reaching zero the timer will
be loaded with the latch value and continue counting down
as long as the CA pin is held low. After the counter is stopped
by a high level on CA, the count will hold as long as CA
remains high. Any further low levels on CA will again cause
the counter to count down from its present value. The state
of the CA line can be determined by testing the state of PA4.
A timing diagram of the Interval Timer Mode is shown in
Figure 6-1.
6.1.2 Pulse Generation Mode
In the Pulse Generation mode, the CA line operates as a
Counter Output. The line toggles from low ,to high or from
high to low whenever a Counter A Underflow occurs, or a
write is performed to address 001A.
A timing diagram for the Pulse Width Measurement Mode is
snown in Figure 6.3.
The normal output waveform is a symmetrical square-wave.
The CA output is initialized high when entering the mode and
transitions low when writing to 001A.
I,
-1
CNTR
Asymmetric waveforms can be generated if the value of the
latch is changed after each counter underflow.
COUNT
A one-shot waveform can be generated by changing from
Pulse Generation to Interval Timer mode after only one
occurrence of the output toggle condition.
r-Tposu
2.0V
I
N-,
Figure 6-3.
N-'
N-'
Pulse Width Measurement
6.1.3 Event Counter Mode
In this mode the CA is used as an Event Input line, and the
Counter will decrement with each rising edge detected on
this line. The maximum rate at which this edge can be
detected is one-half the 162 clock rate.
6.1.5 Serial 1(0 Data Rate Generation
Counter A also provides clock timing for the Serial 1(0 which
establishes the data rate for the Serial 1/0 port. When the
Serial 1/0 is enabled, Counter A is forced to operate at the
internal clock rate. Counter A is not required for the RCVR
SIR mode. The Counter 1/0 (PA4) may also be required to
support the Serial If0 (see Table 4-2).
The Counter can count up to 65,535 occurrences before
underflowing. As in the other modes, the Counter A Underflow bit (IER4) is set t,\logic 1 if the underflow occurs.
Figure 6.2 is a timing diagram of the Event Counter Mode.
Table 6-1 identifies the values to be loaded in Counter A for
selecting standard data rates with a p2 clock rate of 1 MHz
and 2 MHz. Although Table 6-1 identifies only the more
common data rates, any data rate from 1 to 62.5K Ilps can
be selected by using the formula:
N
~
16 x bps
-1
)
where
N
Figure 6-2.
Event Counter Mode
~2
bps
6.1.4 Pulse Width Measurement Mode
decimal value to be loaded into Counter A using
its hexadecimal equivalent.
the clock frequency (1 MHz or 2 MHz)
the desired data rate.
NOTE
This mode allows the accurate measurement of a low pulse
duration on the CA line. The Counter decrements by one
count at the 162 clock rate as long as the CA line is held in
the low state. The Counter is stopped when CA is in the high
state.
In Table 6-1 you will notice that the standard data rate
and the actual data rate may be slightly different.
'Transmitter and receiver errors of 1 .5% or less are
acceptable. A revised clock rate is included in Table
6-1 for those baud rates which fall outside this limit.
3-84
One-Chip Microcomputers
R6500/11-/12-/15
Table 6-1.
Standard
Baud
Rate
50
75
110
150
300
600
1200
2400
3600
4800
7200
9600
6.2.1 Retriggerable Interval Timer Mode
Counter A Values for Baud Rate Selection
Hexadecimal
Value
Actual
Baud
Rate
At
Clock Rate
Needed
To Get
Standard
Baud Rate
1 MHz 2 MHz
1 MHz
2 MHz 1 MHz 2 MHz
04El
0340
0237
01AO
OOCF
0067
0033
0019
0010
OOOC
0008
0006
50.00
75.03
110.04
149.88
300.48
600.96
1201.92
2403.85
3676.47
4807.69
6944.44
8928.57
50.00
74.99
110.04
150.06
299.76
600.96
1201.92
2403.85
3676.47
4807.69
7352.94
9615.38
09C3
0682
046F
0340
01AO
OOCF
0067
0033
0021
0019
0010
OOOC
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
0.9792
1.0000
1.0368
1.0752
When operating in the Retriggerable Interval Timer mode,
Counter B is initialized to the latch value by writing to address
001 E, by a Counter B underflow, or whenever a positive edge
occurs on the CB pin (PA5). The Counter B interrupt flag will
be set if the counter underflows before a positive edge occurs
on the CB line. Figure 6-4 illustrates the operation.
2.0000
2.0000
2.0000
2.0000
2.0000
2.0000
2.0000
2.0000
1.9584
2.0000
1.9584
2.0000
LATCH VALUE
0000----------------7---------~---------1
RESET BY
COUNTER B
FLAG
6.2 COUNTER B
Figure 6-4.
Counter B consists of a 16-bit counter and two 16-bit latches
organized as follows: Lower Counter B (LCB), Upper Counter
B (UCB), Lower Latch B (LLB), Upper Latch B (ULB), Lower
Latch C (LLC), and Upper Latch C (ULC). Latch C is used
only in the asymmetrical pulse generation mode. The counter
contains the count of either
clock pulses or external
events depending on the counter mode selected. The contents of Counter B may be read any time by executing a read
at location 001 D for the Upper Counter B and at location
001 E or 001 C for the Lower Counter B. A read at location
001C also clears the Counter B Underflow Flag.
_ _ _ _ _--1r--l.¥1/" SOFTWARE
!
!
Counter B Retriggerable Interval Timer Mode
6.2.2 Asymmetrical Pulse Generation Mode
Counter B has a special Asymmetrical Pulse Generation
Mode whereby a pulse train with programmable pulse width
and period can be generated without the processor intervention once the latch values are initialized.
112
In this mode, the 16-bit Latch B is initialized with a value
which corresponds to the duration between pulses (referred
to as D in the following descriptions). The 16-bit Latch C is
initialized with a value which corresponds to the desired
pulse width (referred to as P in the following descriptions).
The initialization sequence for Latch Band C and the starting
of a counting sequence are as follows:
Latch B contains the counter initialization value, and can be
loaded at any time by executing a write to the Upper Latch
B at location 0010 and the Lower Latch B at location 001C.
In each case, the contents of the accumulator are copied into
the applicable latch register.
1. The lower 8 bits of P are loaded into LLB by writing to
address 001 C, and the upper 8 bits of P are loaded
into ULB and the full 16 bits are transferred to Latch
C by writing to address location 0010. At this point
both Latch B and Latch C contain the value of P.
Counter B can be initialized at any time by writing to address:
001 E. The contents of the accumulator is copied into the
Upper Latch B before the value in the 16-bit Latch B is transferred to Counter B. Counter B will also be set to the latch
value and the Counter B Underflow Flag bit (IFR5) will be set
to a "1" whenever Counter B underflows by decrementing
from 0000.
2. The lower 8 bits of D are loaded into LLB by writing to
address 00lC, and the upper 8 bits of D are loaded
into ULB by writing to address location 001E. Writing
to address location 001 E also causes the contents of
the 16-bit Latch B to be downloaded into the Counter
B and causes the CB output to go low as shown in
Figure 6-5.
IFR 5 may be cleared by reading the Lower Counter B at
location 001C, by writing to address location 001E, or by
RES.
3. When the Counter B underflow occurs the contents of
the Latch C is loaded into the Counter B, and the CB
output toggles to a high level and stays high until
another underflow occurs. Latch B is then down-loaded
and the CB output toggles to a low level repeating the
whole process.
Counter B operates in the same manner as Counter A in the
Interval Timer and Event Counter modes. The Pulse Width
Measurement Mode is replaced by the Retriggerable Interval
Timer mode and the Pulse Generation mode is replaced by
the Asymmetrical Pulse Generation Mode.
3-85
II
R6500111·/12·115
One-Chip Microcomputers
SECTION 7
POWER ON/INITIALIZATION CONSIDERATIONS
7.1 POWER-ON TIMING
7.3 RESET (RES) CONDITIONING
After applications of Vcc and VRR power to the device, RES
must be held low for at least eight 02 clock cycles after Vcc
reaches operating range and the interal oscillator has stabil·
ized. This stabilization time is dependent upon the input Vcc
voltage and performance of the internal oscillator. The clock
can be monitored at 02 (pin 3). Figure 7-1 illustrates the
power turn-on waveforms. Clock stabilization time is typically
20 ms.
When RES is driven from low to high the device is put in a
reset state causing the registers and I/O ports to be configured as shown in Table 7-1. All RAM and other CPU
registers will initialize in a random, non-repeatable data
pattern.
Table 7.1
RES Initialization of I/O Ports and Registers
Add.
(Hex.)
11
+5______
Vee 0----<::":
n/nn
Registers
Processor Status
In!. Flag (IFR)
In!. Enable (IER)
Mode Control (MCR)
Ser. Com. Control (SCCR)
Ser. Com. Status (SCSR)
'.~~~E.~ ~hN.
C~OCK STABILIZATION TIME
XTLO~ uu u ,[U1Il.fUlJUUlJU
'2~{1.Jl...flJlS1.
hiCLOCK;j
CYCLES MINr--
RES
Figure 7·1.
Ports
PA Latch
PB Latch
PC Latch
PD Latch
Power Turn-on Timing Detail
7.2 POWER-ON RESET
The occurrence of RES going from low to high will cause the
device to set the Interrupt Mask Bit - bit 2 of the Processor
Status Register - and initiate a reset vector fetch at address
FFFC and FFFD to begin user program execution. All of the
1/0 ports (PA, PB, PC, PD) will be forced to the high (logic 1)
state. All bits of the Control Register will be cleared to logic
o causing the Interval Timers counter mode (mode 00) to be
selected and causing all interrupt enabled bits to be reset.
Bit No.
7 6 5 4 3 2 1 0
--
-
-----
11
12
14
15
16
a a a a a a a a
a 1 a a a a a a
a
1
2
3
1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 a a a
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7.4 INITIALIZATION
Any initialization process for the device should include a
RES, as indicated in the preceding paragraphs. After stabilization of the internal clock (if a power on situation) an initialization subroutine should be executed to perform (as a minimum)
the following functions:
The Stack Pointer should be set
Clear or Set Decimal Mode
Set or Clear Carry Flag
Set up Mode Controls as required
5. Clear Interrupts
1.
2.
3.
4.
CB
A typical initialization subroutine could be as follows:
OUTPUT
LDX
TXS
CLD
1&3. Counter B -+- Latch B (D)
2&4.
SEC
Counter B -+- Latch C (P)
Figure 6·5.
Counter B Pulse Generation
CLI
3-86
Load stack pointer starting address into X
Register
Transfer X Register value to Stack Pointer
Clear Decimal Mode
Set Carry Flag
Set-up Mode Control and
special function
registers as required
Clear Interrupts
R6500/11·112·/15
One-Chip Microcomputers
APPENDIX A
ENHANCED R6502 INSTRUCTION SET
This appendix summarizes the R6500/11. R6500/12 and
R6500/15 instruction set. For detailed information, consult
the R6500 Microcomputer System Programming Manual
(Order No. 202). Four new bit access instructions are added
to enhance the standard 6502 instruction set.
Table A.l
R6500/11, R6500/12 and R6500/15 Instruction Set in Alphabetic Sequence
Mnemonic
Instruction
Mnemonic
ADC
AND
ASL
Add Memory to Accumulator with Carry
"AND" Memory with Accumulator
Shift Left One Bit (Memory or Accumulator)
LDA
LDX
LDY
LSR
Load Accumulator with Memory
Load Index X with Memory
Load Index Y with Memory
Shift One Bit Right (Memory or
Accumulator)
NOP
No Operation
ORA
"OR" Memory with Accumulator
PHA
PHP
PLA
PLP
Push Accumulator on Stack
Push Processor Status on Stack
Pull Accumulator from Stack
Pull Processor Status from Stack
"RMB
ROL
Reset Memory Bit
Rotate One Bit Left (Memory or
Accumulator)
Rotate One Bit Right (Memory or
Accumulator)
Return from Interrupt
Return from Subroutine
"BBR
"BBS
BCC
BCS
BEQ
BIT
BMI
BNE
BPL
BRK
BVC
BVS
Branch on Bit Reset Relative
Branch on Bit Set Relative
Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits in Memory with Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Force Break
Branch on Overflow Clear
Branch on Overflow Set
CLC
CLD
CLI
CLV
CMP
CPX
CPY
Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable Bit
Clear Overflow Flag
Compare Memory and Accumulator
Compare Memory and Index X
Compare Memory and Index Y
DEC
DEX
DEY
Decrement Memory by One
Decrement Index X by One
Decrement Index Y by One
EOR
"Exclusive-Or" Memory with
Accumulator
INC
INX
INY
Increment Memory by One
Increment Index X by One
Increment Index X by One
JMP
JSR
Jump to New Location
Jump to New Location Saving Return
Address
ROR
RTI
RTS
SBC
SEC
SED
SEI
·SMB
STA
STX
STY
TAX
TAY
TSX
TXA
TXS
TVA
Notes:
• Instructions added to this standard 6502 instruction set.
3-87
Instruction
Subtract Memory from Accumulator with
Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Set Memory Bit
Store Accumulator in Memory
Store Index X in Memory
Store Index Y in Memory
Transfer Accumulator to Index X
Transfer Accumulator to Index Y
Transfer Stack Pointer to Index X
Transfer Index X to Accumulator
Transfer Index X to Stack Register
Transfer Index Y to Accumulator
Table A.2
::D
R6500/11, R6500/12 and R6500/15 Instruction Set Summary
en
U1
o
PROCESSOR STATUS
CODES
ADDRESSING MODES
INSTRUCTIONS
BIT ADDRESSING (OP BY BIT #)
MNEMONIC
Ace
AND
ASl
BBR[#(O-711 BranchonM,,~O
(5)(2)
885[#(0-7)]
BranchonM.~l
(5)(2)
Bee
Branch on C=O
Branch on C ~ 1
Branch on Z~l
(2)
BEQ
BIT
8M'
AAM
BranchonN=l
{21
BNE
BranchonZ=O
(2)
BPl
Branch on N." 0
BRK
Break
BeS
2
A M (t)
X M
C9
EO
CO
CD
EC
CE
CC
491212140
EE
A9A2
AO I 2
IE
N V
Z C
B 0
I
°rrrTrrll····· .
·· ......
......
C51312
E4 3
C4
3
C6 5 12
3
~
RIm Inl
RTS
SSC
AIm Sub
A M C-A {II
l-C
1-0
l-T
1-Mo (5)
A-M
X-M
Y-M
A-X
A-Y
S-X
X-A
X-S
V-A
EB
C8
U1
z
•
0
z
C
2
2
61215115121
~~I
: I~ I~~!
Z
Z
4131591413
1
1
. z
6C 15 13
43
B4428C
All61 T'lll B51l1
BD 1 1 1~~ I: I~
56625E
4AI2111
;
~I~~I~I~
E9 2 2 ED 4 3 E5
3
2
EA 121' 101
48
0868
28
6
2
11
5
2
15
4
2
10 14
I3
N •
B61 4 I 2
z
z
o .
1,9 1 4 13
N
•
N
•
•
C
Z
z •
(Restored)
07117127137147157167177
;:I:I~I;~
40
N
N
z
•
•
C
Z C
(Restored)
SO
N V
Ell 61 21 Fll 5 I 2 I Fsi 4 I 2 I FO I 4 I 3 I F9 I 4 I 3
Z (3)
2
(,
1
a:
87 I 97 I A7 I B7 IC7 I 07 r E7 IF7
811 61 21 911 61 2 I 951 41 2 I 90 I 5 I 3 I ( , I 5 I 3
961412
"C
941 41 2
84
o:::J
CD
38121'
F8 2 1
78
I
·0
88 2 1
CA
121' 1411
2E 6 326
6E 6 3 66
NOTES
1 Add 1 to N If page boundary IS crossed
2 Add 1 to N If branch occurs to same page
Add 2 to N II branch occurs to different page
3 Carry not -= Borrow
4 If In deCImal mode Z flag IS mvalld
accumulator must be checked on zero result
5 Effects a·blt data field of the specIfied zero page address
•
::l:
Z C
Z C
2
80 4 3 8586 33 22
8E
32
8C
I\)
·0
• 0
061612]OE1713
E6
AS
•
::l:
,
Cll 6 I 2 I 01 I 5 I 2 I 051 4 I 2 100 I 4 I 3 1 09 I 4 I 3
451312
4C
20
AD
A51312
AE
21 AC 4131 A4 3 2
4E 6 3 46 5 2
•••
.
;g I~ I~
081812 11
58
B812 11
~
.....
· ......
M.M.·
30
DO
09 ] 2 1 2 ] 00] 4 I 3] 05 I 3 I 2
=~~
STA
STX
STY
TAX
TAY
TSX
TXA
TXS
. TYA
2
7
101212
Y M
M l-M
X 1_X
Y l-Y
AVM-A (1)
M l-M
X-l-X
Y·l-Y
Jump 10 New Loc
Jump Sub
M-A (1)
M-X (1)
M_Y (1)
O-r:::z==::[]-C
No Operal!on
AVM-A (1)
A-Ms 5 1-5
P-Ms 5 1-5
5 1-5 Ms---A
5·1-5 Ms-P
RMB[#(O-7)] O-Mn (5)
SEC
SED
SEI
5MB{#{O-7)1
6
90
BO
FO
o-v
eMP
16
3
N V •••• Z C
N ••••• Z •
N ••••• Z C
79
39
8F9FAFBFCFOFEFFF·······
CPY
DEC
OEX
DEY
EOR
INC
INX
INY
JMP
JSR
LOA
LOX
lOY
LSR
NOP
ORA
PHA
PHP
PLA
PLP
ATI
OA 12 I 1
O~D
CPX
21711512175141217014
2 31 5 2 35 4 2 3D
6'
2'
1 0
00 I 7 11
(2)
(2)
O~C
65
25
0615
(21
Branch on V"'O
0-1
6014
20
DE
2C 14131 241 3 12
BranchonV=l
ell
29
(2)
BVS
CLC
CLD
69
(2)
BVe
elV
'"coci>
OPERATION
A·M·C-A (4)(1)
A M-A
(1)
C- cr::.==![] -.0
7 6 5 4 3 2
AA 1211
N
A8
BA
8A
9A
98
•
3:
0'
a
LEGEND
X
Index X
Y
Index Y
A
Accumulator
M
Memory per effechve address
M.
Memory per stack pomter
MD
Selecter zero page memory bit
M,
Memory BII 7
M,
A
Memory Bit 6
Add
Subtract
And
V
0,
#
ExcluSIve Or
Number of cycles
Number of Bytes
-=
n
o
3
"C
C
sUI
One-Chip Microcomputers
R6500/11-/12-/15
Table A,3
""0
LSD
5
6
7
8
9
A
ORA
ZP
2 3
ASL
ZP
2 5
RMBO
ZP
2 5
PHP
ASL
Implied
1 3
ORA
IMM
2 2
ORA
Zp, x
2 4
A5L
ZP, X
2 6
RMSI
ZP
2 5
CLC
Implied
1 2
ORA
ASS, Y
3 4'
AND
ZP
2 3
ROL
ZP
2 5
RMS2
ZP
2 5
PLP
Implied
1 4
AND
IMM
2 2
Relative (INo, Y)
2 2"
2 5'
AND
Zp.X
2 4
ROL
ZP, X
2 6
RM83
ZP
SEC
Implied
2 5
1 2
AND
ASS, Y
3 4'
RTI
EOR
Implied (INo, X)
1 6
2 6
EOR
ZP
2 3
LSR
ZP
2 5
RMS4
ZP
2 5
PHA
Implied
1 3
EOR
IMM
2 2
Relative (INo), Y
2 2"
2 5'
EOR
ZP, X
2 4
LSR
ZP,X
2 6
RMS5
ZP
2 5
Cli
Implied
EOR
ASS. Y
3 4'
RTS
AoC
Implied (IND. X)
1 6
2 6
AoC
ZP
2 3
ROR
ZP
2 5
RMS6
ZP
2 5
PLA
Implied
1 4
AoC
ZP,X
2 4
ROR
Zp, X
2 6
RMS7
ZP
2 5
5EI
Implied
0
2
4
6
SVS
7
Cl
en
3
4
ORA
JSR
AND
Absolule (INo, X)
3 6
2 6
SVC
5
2
Relative (INo), Y
2 2"
2 5'
SMI
3
1
BRK
ORA
Implied (INo, X)
2 6
1 7
BPL
1
R6500/11, R6500112 and R6500/15 Instruction Operation Code Matrix
SIT
ZP
2.3
AND
EOR
AoC
Relative (IND. Y)
2 2"
2 5'
::;:
1 2
1 2
8
STA
(INo,X)
2 6
STY
ZP
2 3
STA
ZP
2 3
STX
ZP
2 3
SMSO
ZP
2 5
DEY
Implied
1 2
9
SCC
STA
Relative (INo, Y)
2 2"
2 6
STY
Zp, X
2 4
STA
ZP, X
2 4
STX
ZP, Y
2 4
SMSI
ZP
2 5
TYA
Implied
LOY
ZP
2 3
LOA
ZP
2 3
LOX
ZP
2 3
5MB2
ZP
2 5
TAY
Implied
LOY
ZP,X
2 4
LOA
ZP, X
2 4
LOX
ZP, Y
2 4
SM83
ZP
2 5
CLV
Implied
CPY
ZP
2 3
CMP
ZP
2 3
DEC
ZP
2 5
SM84
ZP
2 5
CMP
ZP, X
2 4
DEC
ZP, X
2 6
SSC
ZP
2 3
A
LOY
IMM
2 2
SCS
S
2"
CPY
IMM
2 2
SNE
0
2"
CPX
IMM
2 2
SEQ
F
5'
CMP
(IND. X)
2 6
CMP
2
5'
SSC
(INo, X)
2 6
CPX
ZP
2 3
SSC
Relative (INo), Y
2
V
LOA
2
Relative (INo), Y
2
E
LOX
IMM
2 2
Relative (INo), Y
2
C
LOA
(INo,X)
2 6
2"
0
5'
2
1
2
3
4
B
Accum
1 2
LSR
AoC
IMM
ROR
Accum
2 2
1 2
TXA
Implied
1 2
TAX
Implied
LOA
ASS, Y
3 4'
TSX
Implied
1 2
Implied
1 2
CMP
IMM
2 2
oEX
Implied
1 2
SMS5
ZP
2 5
CLo
Implied
1 2
CMP
ASS, Y
3 4'
INC
ZP
2 5
SMS6
ZP
2 5
INX
Implied
1 2
SSC
IMM
2 2
SSC
Zp, X
2 4
INC
ZP,X
2 6
SMS7
ZP
2 5
SED
Implied
1 2
SSC
ASS, Y
3 4'
5
6
7
8
9
INY
LSD
MSD = Most Significant Digit
LSD = Least Significant Digit
JMP
Indirect
3 5
AoC
ASS, Y
3 4'
LOA
IMM
2 2
1 2
JMP
ASS
3 3
Accum
1 2
TXS
Implied
1 2
BIT
ASS
3 4
ROL
Accum
1 2
STA
ASS, Y
3 5
1 2
C
STY
ASS
3 4
LOY
ASS
3 4
1 2
F
BBRO
ZP
3 5"
ORA
ASS, X
3 4'
ASL
ASS, X
3 7
3
AND
ASS
3 4
ROL
ABS
3 6
3
AND
ASS, X
3 4'
ROL
ASS,X
3 7
3
EOR
ASS
3 4
LSR
ASS
3 6
SSR4
ZP
3 5"
4
EOR
ASS, X
3 4'
LSR
ASS, X
3 7
SSR5
ZP
3 5"
5
AoC
ASS
3 4
ROR
ASS
3 6
SSR6
ZP
3 5"
6
AoC
ASS, X
3 4'
ROR
ABS, X
3 7
SSR7
ZP
3 5"
7
STA
ASS
3 4
STX
ASS
3 4
SSSO
ZP
3 5"
8
SBSI
ZP
5"
9
SS52
ZP
5"
A
SS53
ZP
5"
S
SS54
ZP
5"
C
1
2
5"
SSR3
ZP
3
5"
Cl
en
::;:
3
LOX
ASS
3 4
3
CMP
ASS
3 4
DEC
ASS
3 6
3
CMr
ASS. X
3 4'
DEC
ASS, X
3 7
3
SSC
ASS
3 4
INC
ASS
3 6
3
sse
ASS, X
3 4'
INC
ASS, X
3 7
3
0
E
C
0
5"
SBR2
ZP
3
CPX
ASS
3 4
S
LOA
ASS
3 4
ElBRI
ZP
LOY
LOA
LOX
ASS. X ASS, X ASS, Y
3 4'
3 4'
3 4'
CPY
ASS
3 4
NOP
Implied
1 2
A
E
ASL
ABS
3 6
STA
ASS, X
3 5
1 2
/
0
ORA
ABS
3 4
SS55
ZP
0
5"
SS56
ZP
E
5"
SSS7
ZP
5"
F
F
""
'Add 1 to N if page boundary is crossed,
"Add 1 to N if branch occurs to same page;
add 2 to N if branch occurs to different page.
o
o
3-89
BRK
Implied
1 7
-OP Code
-Addressing Mode
-Instruction Bytes; Machine Cycles
One-Chip Microcomputers
R6500/11·/12·115
APPENDIX B
KEY REGISTER SUMMARY
7
I
7
I
7
I7
I7
I
I.
PC"
ACCUMULATOR
1"1
INDEX REGISTER Y
1.1
I
v
0
1
PCl
PROGRAM COUNTER
SP
PC
STACK POINTER
7
vi 10 lOl'
INI
IZ IC
PROCESSOR STATUS REG
I
I Zl CI
~
INDEX REGISTER X
P
CARRY Ie)
CD
l=CarrySet
o = Carry Clear
ZERO IZI
1
o
(D
= Zero Resull
= Non-Zero Resull
I NTERAUPT DISABLE (I)
CPU Registers
®
1 -ifiQlnlerrupl Disabled
o . ~ 'iFiOlnterrupt Enabled
~ECIMAL MODe (OJ
pO
PORTD
II"Brr
II
peO
po
CPU
RAM
I
23
PCI).PC7/(A13, A14
(Full address mode)"
PDo-PD7/
(DATA/ADDR BUS (M·A11»
I I=g:f~:;::
I I+--
45
PAO-PA7
PBO-PB7
PCO-PC7
PDO-PD7
39-32
31-24
54-61
62-64,
1-5
AO-AI2, A15
20-7
DBO-DB7
53-46
~ ~O (PA6)'
SI (PA7)
R6500/13
• MULTIPLEXED FUNCTIONS PINS (Software Selectable)
Figure 2-2. Interface Diagram
SYNC
22
40
3-140
Main power supply +5V
Separate power pin for RAM.
In the event that Vce power
is off. this power retains RAM
data.
Signal and power ground (OV)
Crystal or clock input for internal clock oscillator. Also
allows input of XI clock sig·
nal if XTLO is connected to
V ss. or X2 or X4 clock if XTLO
is floated.
Crystal output from internal
clock oscillator.
The Reset input is used to
initialize the device. This signal must not transition from
low to high for at least eight
cycles after Vee reaches operating range and the internal oscillator has stabilized.
Clock signal output at internal frequency.
A negative going edge on the
Non-Maskable Interrupt signal requests that a nonmaskable interrupt be generated with the CP U.
Four 8-bit ports used for
either input/output. Each line
of Ports A. Band C consists
of an active transistor to Vss
and an optional passive pullup to Vee. In the abbreviated
or multiplexed modes of operation Port C has an active
pull-up transistor. Port D
functions as either an B-bit
input or B-bit output port. It
has active pull-up and pulldown transistors.
Fourteen address lines used
to address a complete
65K external address space.
Note: A13 & A14 are sourced
through PC6 & PC7 when in
the Full Address Mode.
Eight bidirectional data bus
lines used to transmit data to
and from external memory.
SYNC is a positive going signal for the full clock cycle
whenever the CPU is performing an OP CODE fetch.
Controls the direction of data
transfer between the CPU
and the external 65K address space. The signal is
high when reading and low
when writing.
R6511 Q Microprocessor and R6500/13 Microcomputer
SECTION 3
SYSTEM ARCHITECTURE
location is stored (or "pushed") onto the stack. Each time
data are to be pushed onto the stack, the Stack Pointer is
placed on the Address Bus, data are written into the memory
location addressed by the Stack Pointer, and the Stack
Pointer is decremented by 1. Each time data are read (or
"pulled") from the stack, the Stack Pointer is incremented by
1. The Stack Pointer is then placed on the Address Bus and
data are read from the memory location addressed by the
Pointer.
This section provides a functional description of the R6500/
13. Functionally the R6500/13 consists of a CPU, both RAM
and optional ROM memories, four 8-bit parallel I/O ports, a
serial I/O port, dual counter/latch circuits, a mode control register, and an interrupt flag/enable dual register circuit. A block
diagram of the system is shown in Figure 3-1.
NOTE
Throughout this document, unless specified otherwise,
all memory or register address locations are specified
in hexadecimal notation.
The stack is located on zero page, i.e., memory locations
00FF-0040. After reset, which leaves the Stack Pointer
indeterminate, normal usage calls for its initialization at OOFF.
3_1 CPU LOGIC
3.1.4 Arithmetic And Logic Unit (ALU)
The R6500/13 internal CPU is a standard 6502 configuration
with an 8-bit Accumulator register, two 8-bit Index Registers
(X and V); an 8-bit Stack Pointer register, an AlU, a 16-bit
Program Counter, and standard instruction register/decode
and internal timing control logic.
All arithmetic and logic operations take place in the AlU,
including incrementing and decrementing internal registers
(except the Program Counter). The AlU cannot store data
for more than one cycle. If data are placed on the inputs to
the AlU at the beginning of a cycle, the result is always gated
into one of the storage registers or to external memory during
the next cycle.
3.1.1 Accumulator
The accumulator is a general purpose 8-bit register that
stores the results of most arithmetic and logic operations. In
addition, the accumulator usually contains one of the two
data words used in these operations.
Each bit of the AlU has two inputs. These inputs can be tied
to various internal buses or to a logic zero; the AlU then
generates the function (AND, OR, SUM, and so on) using
the data on the two inputs.
3.1.2 Index Registers
3.1.5 Program Counter
There are two 8-bit index registers, X and Y. Each index register can be used as a base to modify the address data program counter and thus obtain a new address-the sum of
the program counter contents and the index register contents.
The 16-bit Program Counter provides the addresses that are
used to step the' processor through sequential instructions
in a program. Each time the processor fetches an instruction
from program memory, the lower (least significant) byte of
the Program Counter (PCl) is placed on the low-order bits
of the Address Bus and the higher (most significant) byte of
the Program Counter (PCH) is placed on the high-order 8
bits of the Address Bus. The Counter is incremented each
time an instruction or data is fetched from program memory.
When executing an instruction which specifies indirect
addressing, the CPU fetches the op code and the address
and modifies the address from memory by adding the index
register to it prior to loading or storing the value of memory.
Indexing greatly simplifies many types of programs, especially those using data tables.
3.1.6 Instruction Register and Instruction Decode
Instructions are fetched from ROM or RAM and gated onto
the Internal Data Bus. These instructions are latched into the
Instruction Register, then decoded along with timing and
interrupt signals to generate control Signals for the various
registers.
3.1.3 Stack Pointer
The Stack Pointer is an 8-bit register. It is automatically
incremented and decremented under control of the microprocessor to perform stack manipulation in response to either
user instructions, an internal IRQ interrupt, or the external
interrupt line NMI. The Stack Pointer must be initialized by
the user program.
3.1.7 Timing Control
The Timing Control logic keeps track of the specific instruction cycle being executed. This logic is set to TO each time
an instruction fetch is executed and is advanced at the
beginning of each Phase One clock pulse for as many cycles
as are required to complete the instruction. Each data transfer
which takes place between the registers is caused by
decoding the contents of both the instruction register and
timing control unit.
The stack allows simple implementation of multiple level
interrupts, subroutine nesting and simplification of many types
of data manipulation. The JSR, BRK, RTI and RTS instructions use the stack and Stack Pointer.
The stack can be envisioned as a deck of cards which may
be accessed only from the top. The address of a memory
3-141
R6511Q Microprocessor and R6500113 Microcomputer
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3-142
R6511Q Microprocessor and R6500113 Microcomputer
3.1.8 Interrupt Logic
3.3 READ-ONLY-MEMORY (ROM)
Interrupt logic controls the sequencing of three interrupts;
RES. NMI and IRQ. IRQ is generated by anyone of eight
conditions: 2 Counter Overflows. 2 Positive Edge Detects,
2 Negative Edge Detects. and 2 Serial Port Conditions.
The optional ROM consists of 256 bytes mask programmable
memory with an address space from 7FOO to 7FFF. ROM
locations FFFA to FFFF are assigned for interrupt vectors.
The reset vector can be optionally at 7FFE or FFFC.
The R6511 Q has no ROM and its Reset vector is at FFFC.
3.2 NEW INSTRUCTIONS
3.4 RANDOM ACCESS MEMORY (RAM)
In addition to the standard R6502 instruction set, four new
bit manipulation instructions have been added to the R6500/
13. The added instructions and their format are explained in
the following paragraphs. Refer to Appendix A for the Op
Code mnemonic addressing matrix for these added instruc·
tions. The four added instructions do not impact the CPU
processor status register.
The RAM consists of 192 bytes of read/write memory with
an assigned page zero address of 0040 through OOFF. The
R6500/13 provides a separate power pin (V RR) which may be
used for standby power for 32 bytes located at 0040·005F.
In the event of the loss of Vee power, the lowest 32 bytes of
RAM data will be retained if standby power is supplied to the
VRR pin. If the RAM data retention is not required then VRR
must be connected to Vee. During operation VRR must be at
the Vee level.
3.2.1 Set Memory Bit (SMB m, Addr.)
This instruction sets to "1" one of the a·bit data field specified
by the zero page address (memory or 1/0 port). The first byte
of the instruction specifies the 5MB operation and one of eight
bits to be set. The second byte of the instruction designates
address (0-255) of the byte to be operated upon.
For the RAM to retain data upon loss of Vee, VRR must be
supplied within operating range and RES must be driven low
at least eight ~2 clock pulses before Vee falls out of operating
range. RES must then be held low while Vee is out of oper·
ating range and until at least eight ~2 clock cycles after Vee
is again within operating range and the internal ¢2 oscillator
is stabilized. VRR must remain within Vee operating range
during normal operation. When Vee is out of operating range,
VRR must remain within the VRR retention range in order to
retain data. Figure 3.2 shows typical waveforms.
3.2.2 Reset Memory Bit (RMB m, Addr.)
This instruction is the same operation and format as 5MB
instruction except a reset to "0" of the bit results.
3.2.3 Branch On Bit Set Relative (BBS m, Addr,
DEST)
RAM OPERATING MODE RAM RETENTION MODE
This instruction tests one of eight bits designated by a 3·bit
immediate field within the first byte of the instruction. The
second byte is used to designate the address of the byte to
be tested within the zero page address range (memory or
I/O ports). The third byte of the instruction is used to specify
the a·bit relative address to which the instruction branches
if the bit tested is a "1". If the bit tested is not set, the next
sequential instruction is executed.
I
I
I
::lj@, : t::~:~
I-@
-J I- ®
-J l-
TRL
1 INITIAL APPLICATION OF vee AND VRR •
@
2 LOSS OF Vee, RAM ON STANDBY POWER.
3 REAPPLICATION OF Vee.
4 >8112 CLOCK PULSES AFTER OSCILLATOR STABILIZATION.
5.>8112 CLOCK PULSES.
3.2.4 Branch On Bit Reset Relative (BBR m,
Addr,DEST)
This instruction is the same operation and format as the BBS
instruction except that a branch takes place if the bit tested
is a "0".
Figure 3·2.
3·143
Data Retention Timing
R6511Q Microprocessor and R6500/13 Microcomputer
3.5 CLOCK OSCILLATOR
For example, if CL
crystal, then
22 pF for a 4 MHz parallel resonant
The R6511Q has been configured for a crystal oscillator, a divide
by 2 countdown network, and for Master Mode Operation.
C = (2x22) - 27 = 17 pF
(use standard value of 18 pF)
Three customer selectable mask options are available for controlling the R6500/13 timing. The R6500/13 can be ordered with
a crystal oscillator, a divide by 2 or divide by 4 countdown network and for clock master mode or clock slave mode operation.
The series resistance of the crystal must be less than
For 2M Hz interval operation the divide-by-2 options must be
specified.
Rsmax =
The on-chip oscillator is designed for a parallel resonant crystal connected between XTLI and XTLO pins. The equivalent
oscillator circuit is shown in Figure 3-3.
Internal timing can also be controlled by driving the XTLI pin
with an external frequency source. Figure 3-3b shows typical
connections. If XTLO is left floating, the external source is divided
by the internal countdown network. However, if XTLO is tied to
V .., the internal countdown network is bypassed causing the
chip to operate at the frequency of the external source.
A parallel resonant crystal is specified by its load capacitance
and series resonant resistance. For proper oscillator operation,
the load capacitance (Cc), series resistance (Rs) and the crystal resonant frequency (F) must meet the following two relations:
(C + 27) = 2CL
or
2 X 106 = 258 ohms
(4x22j"
The operation described above assumed a CLOCK MASTER
MODE mask option. In this mode a frequence source (crystal
or external source) must be applied to the XTLI and XTLO pins.
C,;, 2CL - 27 pF
s Rsmax = 2x 106
Rs
(FCd 2
02 is a buffered output signal which closely approximates the
interal timing. When a common external source is used to drive
multiple devices the internal timing between devices as well as
their 02 outputs will be skewed in time. If skewing represents
a system problem it can be avoided by the MasterlSlave connection and options shown in Figure 3-4.
where: F is in MHz; C and CL are in pF; R is in ohms.
To select a parallel resonant crystal for the oscillator, first select
the load capacitance from a Crystal Manufacturer's catalog.
Next, calculate Rsmax based on F and CL. The selected crystal
must have a Rs less than the Rsmax.
C±5%
C
-=-
XTLI
a'T--MH'
XTAL
C±5%
XTLO
One R6500/13 is operated in the CLOCK MASTER MODE and
a second in the CLOCK SLAVE MODE. Mask options in the
SLAVE unit convert to 02 signal into a clock input pin which is
tightly coupled to the internal timing generator. As a result the
internal timing of the MASTER and SLAVE units are synchronized with minimum skew. If the 02 signal to the SLAVE
unit is inverted, the MASTER and SLAVE UNITS WILL OPERATE OUT OF PHASE. This approach allows the two devices to
share external memory using cycle stealing techniques.
27 pF
Y:1-"
27 pF
-=
A.CRYSTALINPUT
~-~
R6500/13
NC
XTLO
R6500/13
I'NT :52 MHz
MASTER
DIVIDE-BY-2 OR
DIVIDE-BY-4
'2 (OUTPUT CLOCK)
r-- __ .., INVERTER USED
I
I
IL __
H."'~U
')
R6500/13
R6500/13
I'NT :52 MHz
XTLI
I WHEN SLAVE IS
: TO OPERATE
---' OUT OF PHASE
WITH MASTER
DIVIDE-BY-l
SLAVE
XTLO
(INPUT CLOCK)
Vss .".
XTLO
B.CLOCKINPUTS
Figure 3-3. Clock Oscillator Input Options
Figure 3-4. MasterlSlave Connections
3-144
R6511 Q Microprocessor and R6500/13 Microcomputer
3.6 MODE CONTROL REGISTER (MCR)
3.7 INTERRUPT FLAG REGISTER (IFR)
AND INTERRUPT ENABLE
REGISTER (IER)
The Mode Control Register contains control bits for the multifunction I/O ports and mode select bits for Counter A and
Counter B. Its setting. along with the setting of the Serial
Communications Control Register (SCCR). determines the
basic configuration of the R6500/13 in any application. Initializing this register is one of the first actions of any software
program. The Mode Control Register bit assignment is shown
in Figure 3-5.
MCR
An IRQ interrupt request can be initiated by any or all of eight
possible sources. These sources are all capable of being
enabled or disabled by the use of the appropriate interrupt
enabled bits in the Interrupt Enable Register (IER). Multiple
simultaneous interrupts cause the IRQ interrupt request to
remain active until all interrupting conditions have been
serviced and cleared.
The Interrupt Flag Register contains the information that
indicates which I/O or counter needs attention. The contents
of the Interrupt Flag Register may be examined at any time
by reading at address: 0011. Edge detect IFR bits may be
cleared by executing a RMB instruction at address location
0010. The RMB X. (0010) instruction reads FF. modifies bit
X to a "0". and writes the modified value at address location
0011. In this way IFR bits set to a "1" after the read cycle of
a Read-Modify-Write instruction (such as RMB) are protected
from being cleared. A logic "1" is ignored when writing to
edge detect IFR bits.
Addr 0014
Counter B
Mode Select
I I
Bus Mode Select
0-
0 Interval Timer
0 - 1 Pulse Generation
11_
0 Event Counter
1 Pulse Width Meas.
0 - 0 Interval Timer
o-
1 Asymmetric Pulse Generation
0 Event Counter
1 Relrlggerable Interval Timer
Port B Latch
(1 = Enabled)
Port 0 Trj-State
(0= Tn State High Impedance Mode)
11_
Each IFR bit has a corresponding bit in the Interrupt Enable
Register which can be set to a "1" by writing a "I" in the
respective bit position at location 0012. Individual IER bits
may be cleared by writing a "0" in the respective bit position.
or by RES. If set to a "1". an IRQ will be generated when the
corresponding IFR bit becomes true. The Interrupt Flag Register and Interrupt Enable Register bit assignments are shown
in Figure 3-6 and the functions of each bit are explained in
Table 3-1.
0 - 0 Full Address
0 - 1 Normal
1 - - 0 Abbr. Bus
1 - - 1 Mu,,'d Bus
Figure 3-5.
Mode Control Register
The use of Counter A Mode Select is shown in Section 6.1.
The use of Counter B Mode Select is shown in Section 6.2.
The use of Port B Latch Enable is shown in Section 4.4.
The use of Port D in Tri-State Enable is shown in Section
4.6.
The use of Bus Mode Select is shown in Section 4.5 and 4.6.
3-145
R6511Q Microprocessor and R6500/13 Microcomputer
IER
IFR
PA2 Negative
Edge Detect
PA3 Negative
Edge Detect
Counter A
Underflow Flag
Counter B
Underflow Flag
Receiver
Flag
XMTR
Flag
Figure 3-6.
Interrupt Enable and Flag Registers
Table 3·1.
BII
Code
Interrupt Flag Register Bit Codes
Funcllon
IFR 0:
PAO Positive Edge Detect Flag-Set to a "1" when a positive going edge is detected on PAO.
Cleared by RMB 0 (0010) instruction or by RES.
IFR 1:
PAl Positive Edge Detect Flag-Set to a 1 when a positive going edge is detected on PAL
Cleared by RMB 1 (0010) instruction or by RES.
IFR 2:
PA2 Negative Edge Detect Flag-Set to a 1 when a negative going edge is detected on PA2.
Cleared by RMB 2 (0010) instruction or by RES.
IFR3:
PA3 Negative Edge Detect Flag-Set to 1 when a negative going edge is detected on PA3.
Cleared by RMB 3 (0010) instruction or by RES.
IFR 4:
Counter A Underflow Flag-Set to a 1 when Counter A underflow occurs. Cleared by reading
the Lower Counter A at location 0018. by writing to address location 001A. or by RES.
IFRS:
Counter B Underflow Flag-Set to a 1 when Counter B underflow occurs. Cleared by,' reading
the Lower Counter B at location 001C. by writing to address location 001E. or by RES.
IFR 6:
Receiver Interrupt Flag-Set to a 1 when any of the Serial Communication Status Register bits
othrough 3 is set to a 1. Cleared when the Receiver Status bits (SCSR 0-3) are cleared or by
RES.
IFR 7:
Transmitter Interrupt Flag-Set to a 1 when SCSR 6 is set to a 1 while SCSR 5 is a 0 or SCSR
7 is set to a 1. Cleared when the Transmitter Status bits (SCSR 6 & 7) are cleared or by RES.
3·146
R6511 Q Microprocessor and R6500/13 Microcomputer
zero. This bit is cleared to logic 0 when the resultant 8 bits
of a data movement or calculation operation are not all zero.
The R6500 instruction set contains no instruction to specifically set or clear the Zero Bit. The Zero Bit is, however,
affected by the following instructions; ADC, AND, ASL, BIT,
CMP, CPX, CPY, DEC, DEX, DEY, EaR, INC, INX, INY,
LDA, LDX, LDY, LSR, ORA, PLA, PLP, ROL, ROR, RTI,
SBC, TAX, TAY, TXA, TSX, and TYA.
3.8 PROCESSOR STATUS REGISTER
The 8-bit Processor Status Register, shown in Figure 3-7,
contains seven status flags. Some of these flags are
controlled by the user program; others may be controlled both
by the user's program and the CPU. The R6502 instruction set
contains a number of conditional branch instructions which are
designed to allow testing of these flags. Each of the eight processor status flags is described in the following sections.
3.8.3 Interrupt Disable Bit (I)
The Carry Bit (C) can be considered as the ninth bit of an
arithmetic operation. It is set to logic 1 if a carry from the
eighth bit has occurred or cleared to logic 0 if no carry
occurred as the result of arithmetic operations.
The Interrupt Disable Bit (I) is used to control the servicing
of an interrupt request (IRQ). If the I Bit is reset to logic 0,
the IRQ signal will be serviced. If the bit is set to logic 1, the
IRQ signal will be ignored. The CPU will set the Interrupt
Disable Bit to logic 1 if a RESET (RES), IRQ, or Non-Maskable Interrupt (NMI) signal is detected.
The Carry Bit may be set or cleared under program control
by use of the Set Carry (SEC) or Clear Carry (CLC) instruction, respectively. Other operations which affect the Carry Bit
are ADC, ASL, CMP, CPX, CPY, LSR, PLP, ROL, ROR, RTI,
and SBC.
The I bit is cleared by the Clear Interrupt Mask Instruction
(CLI) and is set by the Set Interrupt Mask Instruction (SEI).
This bit is set by the BRK Instruction. The Return from Interrupt (RTI) and Pull Processor Status (PLP) instructions will
also affect the I bit.
3.8.1 Carry Bit (C)
3.8.2 Zero Bit (Z)
The Zero Bit (Z) is set to logic 1 by the CPU during any data
movement or calculation which sets all 8 bits of the result to
CARRV(C)Q)
1
=Carry Set
o =Carry Clear
' - -_ _ ZERO (Z)Q)
1
= Zero Result
o = Non-Zero Result
1--_ _ _ _ _ INTERRUPT DISABLE (I)®
1
= IRQ Interrupt Disabled
o =IRQ Interrupt Enabled
' - - - - - - - - DECIMAL MODE (D)Q)
1
=Decimal Mode
o = Binary Mode
L._ _ _ _ _ _ _ _ _ BREAK COMMAND (B)Q)
1
~
Break Command
o =Non Break Command
' - - - - - - - - - - - - - - - OVERFLOW (O)Q)
=
1 Overflow Set
o Overflow Clear
1... _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ NEGATIVE (N)Q)
=
NOTES
CD Not initialized by RES
Figure 3·7.
=
Negative Value
0= Postive Value
1
® Set to LogiC 1 by RES
Processor Status Register
3-147
R6511 Q Microprocessor and R6500/13 Microcomputer
This indicator only has meaning when signed arithmetic (sign
and seven magnitude bits) is performed. When the ADC or
SBC instruction is performed, the Overflow Bit is set to logic
1 if the polarity of the sign bit (bit 7) is changed because the
result exceeds + 127 or -128; otherwise the bit is cleared
to logic O. The V bit may also be cleared by the programmer
using a Clear Overflow (CLV) instruction.
3.8.4 Decimal Mode Bit (D)
The Decimal Mode Bit (D) is used to control the arithmetic
mode of the CPU. When this bit is set to logic 1, the adder
operates as a decimal adder. When this bit is cleared to logic
0, the adder operates as a straight binary adder. The adder
mode is controlled only by the programmer. The Set Decimal
Mode (SED) instruction will set the 0 bit; the Clear Decimal
Mode (CLD) instruction clears it. The PLP and RTI instructions also affect the Decimal Mode Bit.
The Overflow Bit may also be used with the BIT instruction.
The BIT instruction-which may be used to sample interface
devices-allows the overflow flag to reflect the condition of
bit 6 in the sampled field. During a BIT instruction the Overflow Bit is set equal to the content of the bit 6 on the data
tested with BIT instruction. When used in this mode, the
overflow has nothing to dQ with signed arithmetic, but is just
another sense bit for the microprocessor. Instructions affecting
the V flag are ADC, BIT, CLV, PLP, RTI and SBC.
CAUTION
The Decimal Mode Bit will either set or clear in an
unpredictable manner upon power application. This bit
must be initialized to the desired state by the user program or erroneous results may occur.
3.8.7 Negative Bit (N)
3.8.5 Break Bit (B)
The Negative Bit (N) is used to indicate that the sign bit (bit
7) in the resulting value of a data movement or data arithmetic operation is set to logic 1. If the' sign bit is set to logic
1, the resulting value of the data movement or arithmetic
operation is negative; if the sign bit is cleared, the result of
the data movement or arithmetic operation is positive. There
are no instructions that set or clear the Negative Bit since the
Negative Bit represents only the status of a result. The
instructions that effect the state of the Negative Bit are: ADC,
AND, ASL, BIT, CMP, CPX, CPY, DEC, DEX, DEY, EOR,
INC, INX, INY, LOA, LOX, LOY, LSR, ORA, PLA, PLP, ROL,
ROR, RTI, SBC, TAX, TAY, TSX, TXA, and TVA.
The Break Bit (B) is used to determine the condition which
caused the IRQ service routine to be entered. If the IRQ ser·
vice routine was entered because the CPU executed a BRK
command, the Break Bit will be set to logic 1. If the IRQ routine was entered as the result of an IRQ signal being generated, the B bit will be cleared to logic O. There are no
instructions which can set or clear this bit.
3.8.6 Overflow Bit (V)
The Overflow Bit (V) is used to indicate that the result of a
signed, binary addition, or subtraction, operation is a value
that cannot be contained in seven bits (-128 ". n ". 127).
3-148
R6511 Q Microprocessor and R6500/13 Microcomputer
SECTION 4
PARALLEL INPUT/OUTPUT PORTS
& BUS MODES
Port D may only be all inputs or all outputs. All inputs is
selected by setting bit 5 of the Mode Control Register (MCR5)
to a "0".
The devices have 32 I/O lines grouped into four a-bit ports
(PA, PB, PC, and PD). Ports A through C may be used either
for input or output individually or in groups of any combination.
Port D may be used as all inputs or all outputs.
The status of the input lines can be interrogated at any time
by reading the I/O port addresses. Note that this will return
the actual status of the input lines, not the data written into
the 1/0 port registers.
Multifunction 1I0's such as Pori A and Port C are protected
from normal port I/O instructions when they are programmed
to perform a multiplexed function.
Internal pull-up resistors (FET's with an impedance range. of
3K :S Rl :S 12K ohm) are optional on all port pins except
Port D (R6500/13 only).
Read/Modify/Write instructions can be used to mOdify the
operation of PA, PB, PC, & PD. During the Read cycle of a
Read/Modify/Write instruction the Port 1/0 register is read.
For all other read instructions the port input lines are read.
Read/Modify/Write instructions are: ASL, DEC, INC, LSR,
RMB, ROL, ROR, and 5MB.
The direction of the 32 1/0 lines are controlled by four a-bit
port registers located in page zero. This arrangement provides quick programming access using simple two-byte zero
page address instructions. There are no direction registers
associated with the I/O ports, thus simplifying 1/0 handling.
The 1/0 addresses are shown in Table 4-1. Appendix E.6
shows the 1/0 Port Timing.
4.2 OUTPUTS
Outputs for Ports A thru D are controlled by writing the
desired I/O line output states into the corresponding 1/0 port
register bit positions. A logic 1 will force a high (>2.4V)
output while a logic 0 will force a low «0.4V) output.
Port D all outputs is selected by setting MCR5 to a "1".
Table 4-1.
I/O Port Addresses
Port
Address
A
B
0000
0001
0002
0003
C
0
4.3 Port A (PA)
Port A can be programmed via the Mode Control Register
(MCR) and the Serial Communications Control Register
(SCCR) as a standard parallel a-bit, bit independent, 1/0 port
or as serial channel 1/0 lines, counter 1/0 lines, or an input
data strobe for the Port B input latch option. Table 4-2 tabulates the control and usage of Port A.
4.1 INPUTS
In addition to their normal I/O functions, PAO and PA1 can
detect positive going edges and PA2 and PA3 can detect
negative going edges. A proper transition on these pins will
set a corresponding status bit in the IFR and generate an
interrupt request if the respective Interrupt Enable Bit is set.
The maximum rate at which an edge can be detected is onehalf the 162 clock rate. Edge detection timing is shown in Appendix E.5.
Inputs for Ports A, B, and C are enabled by loading logic 1
into all 1/0 port register bit positions that are to correspond
to I/O input lines. A low «o.aV) input signal will cause a logic
o to be read when a read instruction is issued to the port
register. A high (>2.0V) input will cause a logic 1 to be read.
An RES signal forces all 1/0 port registers to logic 1 thus
initially treating all I/O lines as inputs.
3-149
R6511 Q Microprocessor and R6500/13 Microcomputer
Table 4-2.
Port A Control & Usage
PAO I/O
PORT B LATCH MODE
=0
MCR4
MCR4
SIGNAL
PAD (2)
PIN 39
=1
SIGNAL
NAME
TYPE
NAME
TYPE
PAO
I/O
PORT B
LATCH STROBE
INPUT (1)
PA1-PA31/0
PAl (2)
PIN 38
PA2(3)
PIN 37
PA3(3)
PIN 3S
SIGNAL
NAME
TYPE
PAl
PA2
PA3
I/O
I/O
1/0
COUNTER A I/O
PA4I!O
PA4
PIN 35
MCRO = 0
MCRl = 0
SCCR7 = 0
RCVR SIR MODE
SCCR7 = 0
SCCRS = 0
MCRl = 1
MCRO = 1
MCRl = 0
SCCR7 = 0
RCVR SIR MODE = 0
(4)
=0
(4) (5)
SIGNAL
SIGNAL
SIGNAL
NAME
TYPE
NAME
TYPE
NAME
PA4
I/O
CNTA
OUTPUT
CNTA
I
TYPE
I
INPUT (1)
SERIAL I/O SHIFT REGISTER CLOCK
seCR7
SCCR5
RCVR SIR MODE = 1
(4)
=1
=1
SIGNAL
SIGNAL
NAME
XMTR CLOCK
I
TYPE
NAME
I
OUTPUT
RCVR CLOCK
PAS I/O
MCR3
MCR2
PA5
PIN 34
I
I
COUNTER B I/O
=0
=0
MCR3
MCR2
SIGNAL
=0
=1
MCR3
MCR2
TYPE
NAME
TYPE
NAME
PAS
110
CNTB
OUTPUT
CNTB
SERIAL I/O
XMTROUTPUT
PAS I/O
SCCR7
=0
SCCR7
SIGNAL
=1
SIGNAL
NAME
TYPE
NAME
TYPE
PAS
I/O
XMTR
OUTPUT
SERIAL I/O
RCVR INPUT
PA71/0
SCCRS
PA7
PIN 32
=0
SCCRS
SIGNAL
=1
SIGNAL
NAME
TYPE
NAME
TYPE
PA7
I/O
RCVR
INPUT (1)
3-150
=1
=X
SIGNAL
SIGNAL
NAME
PAS
PIN 33
TYPE
INPUT (1)
I
I
TYPE
INPUT (1)
(1) Hardware Buffer Float
(2) Positive Edge Detect
(3) Negative Edge Detect
(4) RCVR SIR Mode = 1 when SCCRS
• SCCR5 • SCCR4 = 1
(5) For the following mode combinations PA4 is available as an input
only pin:
SCCR7 oSCCRSoSCCR5oMCRl
+ seCR7oSCCRSo7SCCR4oMCRl
+ SCCR7 oSCCRSoSCCR5
+ SCCR7 oSCCR5CoSCCR4.
R6511Q Microprocessor and R6500/13 Microcomputer
4.4 PORT B (PB)
selected to operate in the Abbreviated Mode PDO-PD7 serves
as data register bits DO-D7. When Port D is selected to operate in the Multiplexed Mode data bits DO through D7 are time
multiplexed with address bits A4 through A 11, respectively. Refer
to the Memory Maps (Appendix C) for Abbreviated and Multiplexed memory assignments. See Appendices E.3 through E.5
for Port D timing.
Pori B can be programmed as an a-bit, bit-independent I/O
port. It has a latched input capability which may be enabled
or disabled via the Mode Control Register (MCR). Table
4-3 tabulates the control and usage of Port B. An Input Data
Strobe signal must be provided thru PAO when Port B is programmed to be used with latched input option. Input data
latch timing for Port B is shown in Appendix E.5.
4.7 BUS MOOES
Table 4-3.
Port B Control & Usage
MCR4
=0
MCR4
(2)
Signal
Pin
#
Pin
Name
Name
31
30
29
28
27
26
25
24
PBa
PBl
PB2
PB3
PB4
PB5
PB6
PB7
PBa
PBl
PB2
PB3
PB4
PB5
PB6
PB7
A special attribute of Port C and Port D is their capability to be
configured via the Mode Control Register (see Section 3.6) into
four different modes.
Latch
Mode
110 Mode
=1
In the Full Address Mode, the separate address and data bus
are used in conjunction with PC6 and PC7, which automatically
provide A 13 and A 14. The remaining ports perform the normal
1/0 function.
Signal
Type.
(1)
1/0
1/0
1/0
110
110
1/0
1/0
1/0
Name
Type
PBa
PBl
PB2
PB3
PB4
PB5
PB6
PB7
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
In the 1/0 Bus Mode all ports serve as 1/0. The address and data
bus are still functional but without A 13 and A 14. Since the internal RAM and registers are in the OOXX location, A 15 can be used
for chip select and AO-A12 used for selecting 8K of external
memory. Thus, the device can be used to emulate the R6500/11
in the Normal Bus Mode.
(1) Resistive Pull-Up, Active Buffer Pull-Down
(2) Input data is stored in Port B latch by PAa Pulse
In the Abbreviated Bus Mode, the address and data lines can
be used as in the 1/0 Bus Mode to emulate the R6500/11. Port C
and Port D are automatically transformed into an abbreviated
address bus and control signals (Port C) and a bidirectional data
bus (Port D). 64 Peripheral addresses can be selected. In general
usage, these 64 addresses would be distributed to several externalliO devices such as R6522 arid R6520, etc., each of which
may contain more than one unique address.
4.5 PORT C (PC)
Port C can be programmed as an I/O port, as part of the full
address bus, and, in conjunction with Port D, as an abbreviated bus, or as a multiplexed bus. When operating in the
Full Address Mode PC6 and PC7 serve as A 13 and A 14 with
PCO-PC5 operating as normal I/O pins. When used in the
abbreviated or multiplexed bus modes, PCO-PC7 function as
AO-A3, A12, R/W, A13, and EMS, respectively, as shown in
Table 4-4. EMS (External Memory Select) is asserted (low)
whenever the internal processor accesses memory area
between 0100 and 3FFF. (See Memory Map, Appendix B).
The leading edge of EMS may be used to strobe the eight
address lines multiplexed on Port D in the Multiplexed Bus
Mode. See Appendices E.3 through E.5 for Port C timing.
In the Multiplexed Bus Mode, the operation is similar to the
Abbreviated Mode except that a full 16K of external addresses
are provided. Port C provides the lower addresses and control
signals. Port D multiplexes functions. During the first half of the
cycle it contains the remaining necessary a address bits for 16K;
during the second half of the cycle it contains a bidirectional
data bus. The address bits appearing on Port D must be latched
into an external holding register. The leading edge of EMS, which
indicates that the bus function is active, may be used for this
purpose.
4.6 PORT 0 (PO)
MCR5 must be a logic 1 in the Abbreviated and Multiplexed Bus
Modes.
Port D can be programmed as an 1/0 Port, an S-bit tri-state data
bus, or as a multiplexed bus. Mode selection for Port D is made
by the Mode Control Register (MCR). The Port D output drivers
can be selected as tri-state drivers by setting bit 5 of the MCR
to 1 (one). Table 4-5 shows the necessary settings for the MCR
to achieve the various modes for Port D. When Port D is
Figures 4-1 a through 4-1d show the possible configurations of
the four bus modes. Figure 4-2 shows a memory map of the part
as a function of the Bus Mode and further shows which
adddresses are active or inactive on each of the three possible
buses.
3-151
R6511 Q Microprocessor and R6500/13 Microcomputer
Table 4-4.
Port C Control & Usage
Full Address
Mode
MCR7
MCR6
=a
=a
MCR7
MCR6
Signal
Pin
#
Pin
Name
54
55
56
57
58
59
60
61
PCl
PC2
PC3
PC4
PCS
PC6
PC7
=a
=1
MCR7
MCR6
=1
=a
MCR7
MCR6
Signal
Signal
Name
Type
Name
Type
(1)
PCO
PCl
PC2
PC3
PC4
PC5
A13
A14
1/0(1)
1/0(1)
1/0(1)
1/0(1)
1/0(1)
1/0(1)
OUTPUT (2)
OUTPUT (2)
PCO
PCl
PC2
PC3
PC4
PC5
PC6
PC7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
pca
Multiplexed
Mode
Abbreviated
·Mode
Normal Mode
Signal
Type
(2)
Name
AO
Al
A2
A3
A12
RW
A13
EMS
=1
=1
Type
(2)
Name
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
AO
Al
A2
A3
A12
RW
A13
EMS
(1) Resistive Pull·Up, Active Buffer Pull·Down
(2) Active Buffer Pull·Up and Pull·Down
Table 4-5.
Port 0 Control & Usage
Abbreviated
Mode
Normal Modes
MCR7
MCR6
MCR5
=a
=X
=a
MCR7
MCR6
MCR5
Signal
Pin
#
62
63
64
1
2
3
4
S
Pin
Name
Name
PD~
PD~
POl
PD2
PD3
PD4
PD5
PD6
PD7
POl
PD2
PD3
PD4
PD5
PD6
PD7
1
Type
(1)
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
=a
MCR7
MCR6
MCR5
=X
=1
Signal'
Name
PD~
POl
PD2
PD3
PD4
PDS
PD6
PD7
Multiplexed Mode
=1
MCR7
MCR6
MCR5
=a
=1
Signal
Signal
.2 Low
.2 High
Signal
Type
(2)
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
Name
DATAO
DATAl
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
Type
(3)
1/0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
(1) Tri·State Buffer is in High Impedance Mode
(2) Tri·State Buffer is in Active Mode
(3) Tri·State Buffer is in Active Mode only during the phase 2 portion of a Write Cycle
3-152
=1
=1
=1
Name
A4
A5
A6
A7
A8
A9
Al0
All
Type (2)
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
Name
DATAO
DATAl
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
Type (3)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
R6511 Q Microprocessor and R6500/13 Microcomputer
&-BITS
)
PORTA
~
,..
'.
""
.....
&-BITS
~
.....
""
.....
,,,-----+1
,------+1
,------1
... -----1
"'-----1
PORT 8
~PORTC
&-lilTS
)
PORTS
'<'"""-""""'"
"'...."
J..BJTS
.....>
POlITe
RlUIIOORA65OOJ13
&-BITS
-"
)
PORTO
~
AI3(PC6)
A14(PC7)
"
UP TO 64K
.w
UP TO 11K-244
OF EXTERNAL
OF EXTERNAL
OATABUS
......,. "]
[AC"","'
O&;-DB7
( VECTORS AT )
IIOORMEY(lRY
SYNC
aOlllQoFFFF
DB-.oB7
FfFA-FFFF
ADDIIESSDUS
[ =~]
DIDO-I'"
&EOOO-FfFF
_AT
FFFA-FFFF)
Af.\12, ... '5
A. FULL ADDRESS MODE
---r--I""
'"----~
B. NORMAL BUS MODE
-----+I---l """'" ..
.....
1.
'<"
,------+\
H I T S ) POIUD
'-----~
"'-----.j
"'''''''
UPT084 BYTES OF
EXTEIINAL
DATA BUS (PDO-PD7J
~
PORTA
&-BlTS)
PORTS
RIW(PC5)
'<'"""-""""'"
... -----+1
BITS
:r:::::::x
I/O 011 IIEIIOIIY
'------+\
,..-----1
Af-Aa.AII,AI3(PCf-'I.6j
UP TO 16K·258
OP'!XTERHAL
110 OR MEMORY
... -----+1
[ ~=:::]
2000-ZOOF,
"""3. 11.12,11.13 (PC"". 8)
......"
•
EMS(PC7)
lr~----'
""
UP TO 32K
UPT032K
EXTERNAL 110 OR
OF EXTERNAL
I/O OR MEMORY
DB;'DB7
MEMORY
ACTlVEFROM
[EJ
"';'AI2,AI5
[==~]
~12,AI5
'...,-....!!'----I
..J
'--_ _ _----'-(PCISl--"''-----t_ _ _ _ _
C. ABBREVIATED BUS MODE
Figure 4-1.
D. MULTIPLEXED BUS MODE
Bus Mode Configurations
3-153
R6511 Q Microprocessor and R6500/13 Microcomputer
ABBREVIATED
MODE
FULL ADDRESS
MODE
NORMAL
MODE
MULTIPLEXED
MODE
- . - - - - - - - - - , FFFF
8000
7FFF
INTERNAL BOOT
STRAP ROM
(R6500113 ONLY
7FOO
7EFF
4000
3FFF
EMS VALID
(WHEN ABBR OR
MUX MODE
SELECTED)
1FFF
0100
OOFF
RAM AND
INTERNAL
REGISTERS
0010
OOOF
0003
1/0 PORTS
0000
UI
::::I
ID
II!
ID
ID
UI
::::I
ID
UI
::::I
ID
... ...
0(
Z
II!
~ t<
w
~
UI
::::I
ID
II!
ID
ID
~::::I
::E
UI
UI
...
......
0(
::::I
ID
0(
Z
::::I
ID
Z
II!
II!
tA
X-S
V_A
aA
9A
N
9B
N
NOTES
1. Add 1 to N If page boundary IS crossed
2. Add 1 to N If branch occurs to same page
Add 2 to N If branch occurs to different page
3. Carry not = Borrow
4. If In decimal mode Z flag IS invalid
accumulator must be checked on zero result.
5. Effects a-bit data field of the speCIfied zero page address.
...
o
•
·0
3
3
3
(3
til
til
1
50
70
E022EC
CTITD
o
s:
(;'
"8...
· z
18
C6
M-A (1)
M-X (1)
M----Y (1)
lSR
O-~-C
NOP
No Operation
OAA
AVM __ A(1)
PHA
A__ Ms 5 1-5
PHP
P--Ms 5 1-5
PLA
S· l-S Ms-A
PLP
5·1--5 Ms-P
AM8{#(U-7)] O-Mo (5)
C
Z •
M,M••
8a
Y
Jump to New Lac
1 0
!;I !~I ~~ I~~I g~1 ~~ I~~
Da
sa
tNY
2
z
·1'
(2)
(2)
X·l-X
3
N V
00 I 7 11
Y 1_Y
AVM-A (11
M·l-M
4
.,n.·8DIZC
..
4
3
0 4133179
39
7D1
IE 7 3
2C]4]3]24]3]2
M (1)
M
M
l_M
5MB{#(U-7)] l-Mo
STA
A__ M
STX
X__ M
I ....
71
(2)
(2)
(2)
DEY
EOR
INC
~g~
4
3 25
20
6D1 4 1 3 1"
OE 6 3 06] 5
I ".-
61
(5)(2)
(5)(2)
(2)
(2)
(2)
INX
JMP
JSR
LOA
LOX
LOY
69
29
....CI1....
AA
Aa
LEGEND
X
Y
A
M
M.
M~
M7
Index X
IndexY
"" Accumulator
Memory per effective address
Memory per stack pointer
Selecter zero page memory bit
Memory Bit 7
M6
=
=
•
•
=
II
V
#
•
Z
Memory Bit 6
Add
= Subtract
= And
= Or
ExclUSive Or
Number of cycles
"" Number of Bytes
=
(3
C')
o
3
"cCD
...
R6511 Q Microprocessor and R6500/13 Microcomputer
A.3 INSTRUCTION CODE MATRIX
A
4
BRK
ORA
Implied (IND, X)
7
2 6
ORA
Zp
2 3
ASL
ZP
2 5
RMBO
ZP
2 5
PHP
Implied
3
ORA
IMM
2 2
ORA
BPL
Relative (IND), V
2 2"
2 5'
ORA
ZP, X
2 4
ASL
ZP, X
2 6
RMB,
ZP
2 5
CLC
Implied
2
ORA
ABS, V
3 4'
AND
ZP
2 3
ROL
ZP
2 5
RMB2
ZP
2 5
PLP
Implied
4
AND
IMM
2 2
BMI
AND
Relative (IND, V)
2 2"
2 5'
AND
ZP, X
2 4
ROL
Zp, X
2 6
RMB3
ZP
2 5
SEC
Implied
2
AND
ABS, V
3 4'
RTI
EOR
Implied (IND, X)
6
2 6
EOR
ZP
2 3
LSR
ZP
2 5
RMB4
ZP
2 5
PHA
Implied
3
EOR
IMM
2 2
EOR
Zp, X
2 4
LSR
ZP, X
2 6
RMB5
ZP
2 5
CLI
Implied
2
EOR
ABS, V
3 4'
RTS
ADC
Implied (IND,X)
6
2 6
ADC
ZP
2 3
ROR
ZP
2 5
RMB6
ZP
2 5
PLA
Implied
4
ADC
IMM
2 2
BYS
ADC
Relative (IND, V)
2 2"
2 5'
ADC
ZP,X
2 4
ROR
ZP, X
2 6
RMB7
ZP
2 5
SEI
Implied
2
ADC
ABS, V
3 4'
,
JSR
AND
BIT
ZP
2 3
Absolute (IND, X)
3
6
2
6
,
BYC
EOR
Relative (IND), V
2
2"
2
5'
,
BCC
B
C
CPV
IMM
o
E
,
,
Aceum
2
7YA
Implied
1 2
STA
ABS, V
3 5
TXS
Implied
1 2
LDV
ZP
2 3
LOA
ZP
2 3
LOX
ZP
2 3
5MB2
ZP
2 5
TAV
Implied
2
LOA
IMM
2 2
TAX
Implied
2
LDV
Zp, X
2 4
LOA
Zp, X
2 4
LOX
ZP, V
2 4
5MB3
ZP
2 5
CLY
Implied
1 2
LOA
ABS, V
3 4'
TSX
Implied
2
CPV
ZP
2 3
'CMP
ZP
2 3
DEC
ZP
2 5
5MB4
ZP
2 5
INV
Implied
2
CMP
IMM
2 2
DEX
Implied
2
CMP
ZP, X
2 4
DEC
ZP,X
2 6
5MB5
ZP
2 5
CLD
Implied
CMP
ABS, V
3 4'
SBC
ZP
2 3
INC
ZP
2 5
5MB6
ZP
2 5
INX
Implied
SBC
ZP, X
2 4
INC
ZP, X
2 6
5MB7
ZP
2 5
SED
Implied
1 2
CPX
ZP
2 3
SBC
5'
,
,
7
2
2
SBC
IMM
2 2
STY
ABS
3 4
EOR
ABS
3 4
LSR
ABS
3 6
ADC
ABS
3 4
ROR
ABS
3 6
STA
ABS
3 4
STX
ABS
3 4
LDV
ABS
3 4
LOA
ABS
3 4
CPV
ABS
3 4
,
CMP
ABS
3 4
LOX
ABS
3 4
DEC
ABS
3 6
CMP
DEC
ABS, X ABS, X
3 4'
3 7
CPX
ABS
3 4
NOP
Implied
2
,
SBC
ABS, V
3 4'
B
C
BBR,
ZP
3 5"
BBR2
ZP
3 5"
BBR3
ZP
3 5"
BBR4
ZP
3 5"
4
BBR5
ZP
3 5"
BBRB
ZP
3 5"
BBR7
ZP
3 5"
BBSO
ZP
3 5"
3
LOA
LOX
LDV
ABS, X ABS, X ABS, V
3 4'
3 4'
3 4'
,
BBRO
ZP
5"
3
BBS,
ZP
5"
STA
ABS, X
3 5
,
A
o
ROL
ABS
3 6
ADC
ROR
ABS, X ABS, X
3 4'
3 7
5MB1
ZP
2 5
,
JMP
Indirect
3 5
ROR
STX
ZP, V
2 4
,
AND
ABS
3 4
EOR
LSR
ABS, X ABS, X
3 4'
3 7
STA
Zp, X
2 4
2
o
2
STY
Zp,X
2 4
LOX
IMM
2 2
JMP
ABS
3 3
LSR
,
Accum
TXA
Implied
1 2
,
E
ASL
ABS
3 6
AND
ROL
ABS, X ABS, X
3 7
3 4'
STA
SBC
(IND, X)
2 6
2"
,
2
DEV
Implied
2
Relative (IND), V
2
,
BIT
ABS
3 4
ROL
,
Accum
5MBO
ZP
2 5
BNE
CMP
Relative (IND), V
2 2"
2 5'
BEQ
F
,
o
ORA
ABS
3 4
ORA
ASL
ABS, X ABS, X
3 4'
3 7
STX
ZP
2 3
CMP
(IND, X)
2 6
CPX
IMM
2 2
,
2
STA
ZP
2 3
BCS
LOA
Relative (IND), V
2 2"
2 5'
2 2
,
,
STY
ZP
2 3
LOA
(IND, X)
2 6
LDV
IMM
2 2
,
C
Accum
STA
(IND, X)
2 6
Relative (IND, y)
2 2"
2 6
A
,
B
ASL
BBS2
ZP
5"
A
3
BBS3
ZP
B
3 5"
BBS4
ZP
5"
C
BBSS
ZP
5"
o
BBS6
ZP
5"
E
BBS7
ZP
5"
F
3
3
SBC
ABS
3 4
INC
ABS
3 6
3
SBC
ABS,X
3 4'
INC
ABS, X
3 7
3
o
E
F
'Add 1 to N if page boundary is crossed,
"Add 1 to N If branch occurs to same page;
add 2 to N if branch occurs to different page,
-op Code
-Addressing Mode
-Instruction Bytes; Machine Cycles
3,163
R6511 Q Microprocessor and R6500/13 Microcomputer
APPENDIX B
KEY REGISTER SUMMARY
7
D
I
I ACCUMULATOR
7
D
7
D
I
I
15
v
I
1"1 DI
I
I zl cl
~
I INDEX REGISTER X
7
D
I
PCH
1"1
I INDEX REGISTER V
I PROGRAM COUNTER
pel
7
PC
D
I
I STACK POINTER
Sp
7
D
INlvl Ie 10 II Iz Ie I PROCESSQRSTATUSREO
P
CARRV Ie)
CD
1= Carry Sel
D-=CarryClear
ZERO (ZleD
1 :::;ZeroResul!
o :::; Non-Zero Result
INTERRUPT DISABLE (II Q)
CPU Registers
1 -'i'RQ'nterrupt Disabled
o ": iRQ Interrupt Enabled
DECIMAL MODE (0)
CD
t.,-: DeCimal Mode
0-= Binary Mode
BREAK COMMAND (B)
.
6
Gl
Y3
A13
50pf maximum
50pf maximum
130pf maximum
130pf maximum
A12
All
2
13
Y2
C
12
14
B
Yl
A
YO
15
380IJ..3FFF
300IJ..37FF
280IJ..2FFF
200IJ..27FF
180IJ..1FFF
100IJ..17FF
080IJ..OFFF
010IJ..07FF
Note that both EMS and Phase 2 (,j must be used to correctly
enable the chip selects in the multiplexed or abbreviated bus modes.
E.2 CLOCK TIMING
PARAMETER
3
10
11
74LS138 Y4
5. All capacitive loading is 130pf maximum, except as noted
below:
SYMBOL
9
Y6
G2A
3. All timing reference levels are O.8V and 2.0V, unless
otherwise specified.
PA,PB
PC (110 Modes Only)
PC (ABB and Mux Mode)
PC6, PC7 (Full Address Mode)
7
Y7
1 MHz
2 MHz
MIN
MAX
MIN
MAX
10/Ls
500
10/Ls
Tcyc
Cycle Time
1000
T pWX1
XTLI Input Clock
Pulse Width
XTLO = VSS
500
± 25
TpW02
Output Clock Pulse
Width at Minimum
TpWX1
-
250
± 10
T pWX1
± 25
TPWXl
-
TpWX1
± 20
Tcvc
T R, TF
Output Clock Rise,
Fall Time
-
25
-
15
TIA ,
Input Clock Rise,
Fall Time
-
10
-
10
TIF
)
IXTLI
•
Tcyc
-l
T1R
1.5V
TpWX1
{XTLO = Vssl
_
....._TR
3-168
T pW02
•
R6511 Q Microprocessor and R6500/13 Microcomputer
E.3 ABBREVIATED MODE TIMING-PC AND PD
(MCR 5
~
1, MCR 6
~
0, MCR 7
SYMBOL
~
1)
PARAMETER
MIN
MAX
MIN
MAX
225
-
140
T pCRS
(PC5) R/w Setup Time
T pCAS
(PCO-PC4, PC6) Address Setup Time
-
T pBSU
(PO) Data Setup Time
50
T pBHR
(PO) Data Read Hold Time
10
T pBHW
(PO) Data Wrile Hold Time
TpBDD
225
f-----
35
--- -10
--
30
-
(PO) Data Output Delay
-
175
T pCHA
(PCO-PC4, PC6) Address Hold Time
30
TpCHR
(PC5) R/W Hold Time
30
-
-
2 MHz
1 MHz
-
---
T pCHV
(PC7) EMS Hold Time
10
-
Tpcvp
(PC7) EMS Stabilization Time
30
-
TESU
EMS Setup TIme
-
-
350
-
140
-
-
f------ 30
-
150
f------ r---
30
f------1 - - 30
-
-
10
II
-- -30
-
210
E.3.1 Abbreviated Mode Timing Diagram
WRITE
READ
\12
.-TPCHR
RIW
14-~--~1 TPCRS
_TPCHV
_TESU_
TPCHA
TPBDD
TPBSU
PDO-PD7
TPBHR
3-169
TPBHW
R6511 Q Microprocessor and R6500/13 Microcomputer
E.4 MULTIPLEXED MODE TIMING-PC AND PD
(MCR 5
~
1, MCR 6
~
1, MCR 7
~
1)
.-~-
SYMBOL
2 MHz
1 MHz
PARAMETER
--
----
--- - - -
MIN
MAX
MIN
MAX
T pCRS
(PC5) R/W Setup Time
-
225
-
140
T pCAS
(PCO-PC4, PC6) Address Setup Time
-
225
140
T pBAS
(PO) Address Setup Time
-
225
-
TpBSU
(PO) Data Setup Time
50
-
35
-
TpBHR
(PO) Data Read Hold Time
10
-
10
-
(PO) Data Write Hold Time
30
-
30
-
1?5
-
-,
---
TpBHW
--TpBoD
(PO) Data Output Delay
"-~
(PCO-PC4, PC6) Address Hold Time
T pCHA
---
T pBHA
--
r-(PO) Address Hold Time
30
----
--~--
10
100
-
T pCHR
(PC5) RM Hold Time
30
T pCHV
(PC?) EMS Hold Time
10
(PC7) Address to EMS Delay Time
30
(PC?) EMS Stabilization Time
30
EMS Setup Time
-
140
-- - -
150
i -- 30
-
---10
80
, -- -
-
30
"~--
-
10
-~--
TpCVD
'"
T pcvp
--------'
TESU
I
30
-
30
350
-
-
,
210
NOTE 1 Values assume PCO-PC4, PC6 and PC? have the same capacitive load.
E.4.1 Multiplex Mode Timing Diagram
READ
WRITE
r-------------~I
RIW
(PCS)
.
TPCRS
_TPCHV
EMS
(PC7) ,
----- T ESU
',-
TPCVP
TPCHA
PCD-PC4,
PC6
TPCAS
--+-
_TPBHA
TPBSU
PDDPD7
TPBAS
-TPCVD
TPBHR
3-170
TPBDD
R6511Q Microprocessor and R6500/13 Microcomputer
E.S I/O, EDGE DETECT, COUNTERS, AND SERIAL I/O TIMING
1 MHz
PARAMETER
SYMBOL
2 MHz
i-MIN
MAX
MIN
MAX
-
500
1000
175
-
500
1000
150
Internal Write to Peripheral Data Valid
TpDWl1l
TCMOS(1l
TpDDW
PA, PB, PC TTL
PA, PB, PC CMOS
PO
+--
Penpheral Data Setup Time
Tposu
TpDSU
200
50
-
75
10
Tcvc
-
Tcyc
Tcyc
-
Tcyc
PA, PB, PC
PO
TEPW
PA, PB, PC
PO
PAO-PA3 Edge Delecl Pulse Widlh
-
200
-50-I--
Peripheral Data Hold Time
TpHR
TpHR
-
75
10
-
--
Counters A and B
T,,..
Tee(1)
PA4, PA5 Inpul Pulse Widlh
PA4, PA5 Output Delay
-
-
500
-
500
Port B Latch Mode
TpBLW
TpLSU
TpBLH
-
Tcyc
PAO Strobe Pulse Width
PB Data Setup Time
PB Data Hold Time
175
30
Tcyc
150
30
SarialliO
TpDWI1)
TCMOSm
Tcpw
TpDW lll
TCMOS(1)
PAS
PAS
PA4
PA4
PA4
-
XMTRTTL
XMTR CMOS
RCVR SIR Clock Width
4 Tcyc
XMTR Clock-SIR Mode (TTL)
XMTR Clock-SIR Mode (CMOS)
-
-
500
1000
-
500
1000
4 Tcyc
500
1000
-
500
1000
NOTE 1: Maximum Load Capacitance: 50pF
Passive Pull-Up Required
E.S.1 I/O, Edge Detect, Counter, and Serial I/O Timing
.2
Teye
.I ..
\
...
PAO·PA7
PBO·P B7
PCO·P C7
PDO-P 07
EDGE DETECTS
(PAO-PA3)
TPDSU
)t
1.SV
•
J
1<
TP'Hit'1
){
I
CNTR
PA4,PAS
~.I
1.SV\
/
,
TEPW
1.S~
1;1.SV
..
TCD
CNTR
(PA4, P AS)
1,SV:r
..
TCPW
~
TCPW
2.4V!
O.4V,
T pDDW
X-
PDO-P 07
TCMOS
TPDW
PAO·PA7
PCO·PC7
PBO·P B7
PB
(LATCH MODE)
PAO STROBE
2.4V
,
VDD-30%1
O.4V
V--
f\--
>1.SV
.-TpLSU _!"
1.SV
TpBLW
3-171
~l
- TpBLH
R6511 Q Microprocessor and R6500/13 Microcomputer
E.6 MICROPROCESSOR TIMING (00-07,
AO-A 12, A15, SYNC, R/W)
SYMBOL
PARAMETER
2 MHz
1 MHz
MIN
MAX
MIN
-
MAX
T Rws
RlW Setup Time
-
225
TAos
AO-AI2, A15 Setup
Time
-
150
T osu
00-07 Oata Setup Time
50
00-07 Read Hold Time
10
THw
00-07 Write Hold Time
30
-
35
THR
30
-
T MOS
00-07 Write Output
Oelay
-
175
-
130
10
140
75
-
TsnJ
SYNC Setup
-
225
-
175
THA
AO-AI2, A15 Hold Time
30
-
30
-
T HRw
RIW Hold Time
30
-
30
T Acc
External Memory Access
-
TAcc
Time TAcc = Tcyc-T F-
-
TAcc
TAOS-T DSU
T SYH
SYNC Hold Time
30
-
30
-
E.6.1 Microprocessor Timing Diagram
WRITE
READ
02
RIW
AO·A12,
A15
TDSU_
TMOS
DATAO·
DATA 7
-THR
----,
SYNC
3-172
1-.-----.,
R6518
'1'
Rockwell
R6518
One-Chip Microprocessor
INTRODUCTION
FEATURES
SUMMARY
• Enhanced 6502 CPU
- Four new bit manipulation instructions:
Set Memory Bit (SMB)
Reset Memory Bit (RMB)
Branch on Bit Set (BBS)
Branch on Bit Reset (BBR)
- Decimal and binary arithmetic modes
- 13 addressing modes
- True indexing
The Rockwell R651B one-chip microprocessor is a complete B-bit
microcomputer on a single VLSI chip with the exception of
external user-provided application ROM. The R651B interfaces
with up to 16K bytes of ex1ernal memory via a multiplexed
address/data bus.
The R651B consists of an enhanced R6502 CPU, an internal
clock oscillator, 192 bytes of Random Access Memory (RAM)
and versatile interface circuitry. The interface cirCUitry includes
two 16-bit programmable timer/counters, 16 bidirectional
input/output lines (including four edge-sensitive lines and input
latching on one 8-bit port), a full-duplex serial I/O channel, ten
interrupts and 16K of external address space.
• 192-byte static RAM
•
16 TTL-compatible I/O lines
• One B-bit port with programmable latched input
• Two 16-bit programmable counter/timers, with latches
- Pulse width measurement
- Asymmetrical pulse generation
- Pulse generation
- Interval timer
- Event counter
- Retriggerable interval timer
The innovative architecture and the demonstrated high performance of the R6502 CPU, as well as instruction simplicity, results
in system cost-effectiveness and a wide range of computational power. These features make this device a leading candidate
for microprocessor applications.
• Serial port
- Full-duplex asynchronous operation mode
- Selectable 5- to B-bit characters
- Wake-up feature
- Synchronous shift register mode
- Standard programmable bit rates, programmable up to
62.5K bits/sec @ 1 MHz
Rockwell supports development of R6S00/' single-chip microcomputer applications with the Rockwell Design Center Low Cost
Emulator (LCE) and R6500!" Personality Set. Program assembly can be performed on any user-provided computer using an
assembler generating R6500/' machine code. The machine
code can then be downloaded via an RS-232-C serial channel
to the LCE for program debugging and in-circuit emulation. Refer
to the RDC-31 01/2 LCE and RDC-3XX R6500!" Personality Set
data sheets, Order No.s RDC17 and RDC06, respectively, for
detailed information.
• Ten interrupts
- Four edge-sensitive lines; two positive, two negative
- Reset
- Non-maskable
- Two counter underflows
- Serial data received
- Serial data transmitted
•
16K bytes of external memory addressing
•
Flexible clock circuitry
- 2 MHz or 1 MHz internal operation
- Internal clock with external 2 MHz to 4 MHz series resonant
XTAL at two times internal frequency
- External clock input divided by one or two
•
1 p,s minimum instruction execution time @ 2 MHz
•
NMOS-3 silicon gate, depletion load technology
This product description is for the reader familiar with the R6502
CPU hardware and programming capabilities. A detailed description of the R6502 CPU hardware is included in the R6500
Microcomputer System Hardware Manual (Order No. 201). A
description of the instruction capabilities of the R6502 CPU is
contained in the R6500 Microcomputer System Programming
Manual (Order No. 202).
• Single + 5V power supply
•
12 mW stand-by power for 32 bytes of the 192-byte RAM
CUSTOMER OPTIONS
•
40-pin DIP
•
44-pin PLCC
The R651B is available in 1 MHz (no suffix letter) or 2 MHz
(A suffix) versions.
Document No. 29651 N92
Product Description
3-173
Order No. 2189
Rev. 2, June 1987
II
One.Chip Microprocessor
R6518
INTERFACE
ORDERING INFORMATION
This section presents the interface requirements for the R6S18
single·chip microprocessor. Figure 1 is the Interface Diagram,
Figure 2 shows the pin configurations and Table 1 describes the
function of each pin. A detailed block diagram of the device and
its internal function is illustrated in Figure 3. Package dimensions
are illustrated in the last section.
Part Number:
R6S18
L
Temperature Range (T L to T H):
Blank =
OOC to + 70°C
E = -40°C to +85°C
-
Package
C = 40·Pin Ceramic DIP
P = 40·Pin Plastic DIP
J = 44·Pin Plastic Leaded
Chip Carrier (PLCC)
Frequency
1 = 1 MHz
A = 2 MHz
R651a
XTLO
CLOCK
OSCILLATOR
XTLI
I
EDGE DETECT
I
PM-PA7 (EDGE DETECTS:
INTERRUPT
LOGIC
112
Vee
Vss
.
..
I
I
CPU
6502
192 x a
RAM
PORTA
I
PORTB
II
I
16-BIT
COUNTER/LATCH A
16-BIT
COUNTER/LATCH B
SERIAL RECEIVE,
TRANSMIT
REGISTERS
PAD, PAl POSITIVE
PA2, PA3 NEGATIVE)
DS(PAO) (INPUT DATA STROBE)·
~ao
PBO-PB7 (LATCHED INPUTS)
I
I
EXTERNAL
ADDRESS/DATA
BUS
CONTROL
REGISTERS
OaO
::JaO
AO-A3, A12, RM, A13, EMS
0 80
DATA (DO-D7)/ADDR BUS (A4-All)
...
OIl
...
CA(PA4)·
CB(PAS)·
SO (PA6)·
SI (PA7)·
·MULTIPLEXED FUNCTION PINS
Figure 1.
Interface Diagram
3-174
R6518
One-Chip Microprocessor
XTLO
XTLI
v••
v ••
U
RiW
PBO
PBl
PB2
PB3
PB4
PB5
PBG
An
EMS
All/D7
Al0/D6
PB7
PAO
PAl
PA2
A9/D5
AB/D4
PA3
PA4
A7/D3
A6/D2
A5/Dl
A4/DO
PA5
PA6
PA7
NMI
RES
vee
AO
Al
A2
A3
A12
_
0
c~~~~~::~Jff
CD.., ..
R/W
A13
EMS
All/D7
Al0/D6
A9/D5
AB/D4
A7/D3
"'C"\I
..........
....
0
A2
A3
A12
MN
... O
PIN 1
INDICATOR
10
11
12
13
14
15
16
17
39
3B
37
36
35
PB2
PB3
PB4
PB5
PBB
34
33
32
31
30
29
PB7
PAO
PAl
PA2
PA3
PA4
CDGlIO_N"" .... ..,CD .... CO
.. .. N
N
N N
N
N
N
N N
uli . .
~~~~zz~z::~::
......
N_oICOUU
4D-PIN DIP
CDIII
44-PIN PLCC
Figure 2.
R6518 Pin Assignments
Table 1.
Pin Description
Pin Number
DIP
PLCC
Vee
Signal Name
21
24
Main power supply
VRR
39
42
Separate power pin for RAM. In the event that Vee power is lost. this power retains 32 bytes of RAM Data.
Vss
40
44
XTLI
2
3
Crystal or clock input for internal clock oscillator. Also allows input of X1 clock signal if XTLO is connected
to Vss. or X2 clock if XTLO is floated.
1
2
Crystal output from internal clock oscillator.
20
21
XTLO
RES
A4-A 11100·07
NC
The Reset input is used to initialize the device. This signal must not transition from low to high for at least
eight cycles after Vec reaches operating range and the internal oscillator is stabilized.
Clock signal output at internal frequency. )
3
4
25
30-23
38·31
33-26
41-34
4-11
5-12
19-12
20-13
These multiplexed address/data pins have active pull-up and pull-down transistors.
-
1.22
23,43
No connection. These pins should be left open.
NMI
AD-A3. A 12. Rm
A13. & EMS
Signal and power ground (OV)
22
02
PAD-PA7
PSD-PS7
Description
+ 5V
A negative going edge on the Non-Maskable Interrupt signal requests that a non·maskable interrupt be
generated within the CPU.
Two 8-bit ports used for either inlluUoutpul. Each line of Ports A and S consists of an active transistor to
Vss and a passive pull-up to Vee.
The address and timing pins have an active transistor to Vss and a passive pull·up to Vee.
3-175
One-Chip Microprocessor
R6518
SYSTEM ARCHITECTURE
I
This section provides a functional description of the R6518.
Functionally it consists of a CPU, RAM memory, two 8-bit parallel
I/O ports, a serial I/O port, dual counter/latch circuits, a mode
control register, and an interrupt flag/enable dual register circuit.
A block diagram of the system is shown in Figure 3.
The stack can be envisioned as a deck of cards which may only
be accessed from the top. The address of a memory location
is stored (or "pushed") onto the stack. Each time data are to
be pushed onto the stack, the Stack Pointer is placed on the
Address Bus, data are written into the memory location
addressed by the Stack Pointer, and the Stack Pointer is
decremented by 1. Each time data are read (or "pulled") from
the stack, the Stack Pointer is incremented by 1. The Stack
Pointer is then placed on the Address Bus, and data are read
from the memory location addressed by the Pointer.
NOTE
Throughout this document, unless specified otherwise, all
memory or register address locations are specified in
hexadecimal notation.
The stack is located on zero page, i.e., memory locations
00FF-0040. After reset, which leaves the Stack Pointer indeterminate, normal usage calls for its initialization at OOFF.
CPU LOGIC
ARITHMETIC AND LOGIC UNIT (AW)
The internal CPU is a standard 6502 configuration with an 8-bit
Accumulator register, two 8-bit index registers (X and V); an 8-bit
Stack Pointer register, an AlU, a 16-bit Program Counter, and
standard instruction register/decode and internal timing control
logic.
All arithmetic and logic operations take place in the AlU,
including incrementing and decrementing internal registers
(except the Program Counter). The AlU cannot store data for
more than one cycle. If data are placed on the inputs to the AlU
at the beginning of a cycle, the result is always gated into one
of the storage registers or to external memory during the next
cycle.
ACCUMULATOR
The Accumulator is a general purpose 8-bit register that stores
the results of most arithmetic and logic operations. In addition,
the Accumulator usually contains one of the two data words used
in these operations.
Each bit of the AlU has two inputs. These inputs can be tied
to various internal buses or to a logiC zero; the AlU then
generates the function (AND, OR, SUM, and so on) using the
data on the two inputs.
INDEX REGISTERS
PROGRAM COUNTER
There are two 8-bit index registers, X and Y. Each index register
can be used as a base to modify the address data program
counter and thus obtain a new address-the sum of the program counter contents and the index register contents.
The 16-bit Program Counter provides the addresses that are
used to step the processor through sequential instructions in
a program. Each time the processor fetches an instruction from
program memory, the lower (least significant) byte of the Program Counter (PCl) is placed on the low-order bits of the
Address Bus and the higher (most significant) byte of the
Program Counter (PCH) is placed on the high-order 8 bits of the
Address Bus. The Counter is incremented each time an instruction or data is fetched from program memory.
When executing an instruction which specifies indirect addressing, the CPU fetches the op code and the address, and modifies
the address from memory by adding the index register to it prior
to loading or storing the value of memory.
Indexing greatly simplifies many types of programs, especially
those using data tables.
INSTRUCTION REGISTER AND INSTRUCTION DECODE
Instructions are fetched from ROM or RAM and gated onto the
Internal Data Bus. These instructions are latched into the Instruction Register then decoded along with timing and interrupt
signals to generate control signals for the various registers.
STACK POINTER
The Stack POinter is an 8-bit register. It is automatically
incremented and decremented under control of the microprocessor to perform stack manipulation in response to either
user instructions, an internal IRQ interrupt, or the external
interrupt line NMI. The Stack Pointer must be initialized by
the user program.
TIMING CONTROL
The Timing Control Logic keeps track of the specific instruction
cycle being executed. This logic is set to TO each time an
instruction fetch is executed and is advanced at the beginning
of each Phase One clock pulse for as many cycles as are
required to complete the instruction. Each data transfer which
takes place between the registers is caused by decoding the
contents of both the instruction register and timing control unit.
The stack allows simple implementation of multiple level interrupts, subroutine nesting and simplification of many types of data
manipulation. The JSR, BRK, RTI and RTS instructions use the
stack and Stack Pointer.
3-176
One-Chip Microprocessor
R6518
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One-Chip Microprocessor
R6518
INTERRUPT LOGIC
R6518 provides a separate power pin (VRAl which may be used
for standby power for 32 bytes located at 0040-005F. In the event
of the loss of Vee power, the lowest 32 bytes of RAM data will
be retained if standby power is supplied to the VRR pin. If the
RAM data retention is not required then VRR must be connected to Vee. During operation VRR must be at the Vee level.
Interrupt logic controls the sequencing of three interrupts; RES,
NMI and IRQ. IRQ is generated by anyone of eight conditions:
2 Counter Overflows, 2 Positive Edge Detects, 2 Negative Edge
Detects, and 2 Serial Port Conditions.
The R6518 requires that 3-byte JMP instructions for NMI, RES
and IRQ be programmed in user-provided external ROM at hex
locations 3FF7, 3FFA and 3FFD, respectively. These instructions must jump to the first instruction of the respective reset
or interrupt handler routine. Terminate the interrupt handler routines as normal with an RTI. See Power-On Reset for details
of RES internal initialization.
For the RAM to retain data upon loss of Vee, VRR must be sup·
plied within operating range and RES must be driven low at
least eight 02 clock pulses before Vee falls out of operating
range. RES must then be held low while Vee is out of operating
range and until at least eight 02 clock cycles after Vee is again
within operating range and the internal 02 oscillator is stabilized. VRR must remain within Vee operating range during
normal operation. When Vee is out of operating range, VRR
must remain within the VRR retention range in order to retain
data. Figure 4 shows typical waveforms.
NEW INSTRUCTIONS
In addition to the standard 6502 instruction set, four instructions
have been added to the device to simplify operations that previously required a read/modify/write operation. In order for these
instructions to be equally applicable to either 110 port, with or
without mixed input and output functions, the 110 ports have been
designed to read the contents of the specified port data register
during the Read cycle of the read/modify/write operation, rather
than 110 pins as in normal read cycles. The added instructions
and their format are explained in the following subparagraphs.
Refer to Appendix A for the Op Code mnemonic addressing
matrix for these added instructions.
SET MEMORY BIT (SMB
RAM OPERATING MODE
m, ADDR,)
This instruction sets to "1" one of the 8 bits specified by the
zero page address (memory or 110 port). The first byte of the
instruction specifies the 5MB operation and 1 of 8 bits to be set.
The second byte of the instruction designates address (OO-FF)
of the byte or 110 port to be operated upon.
RESET MEMORY BIT (RMB
1
2
3
4
5
INITIAL APPLICATION OF Vcc AND VRR •
LOSS OF Vee, RAM ON STANDBY POWER.
REAPPLICATION OF Vee.
>8.2 CLOCK PULSES AFTER OSCILLATOR STABILIZATION.
>8.2 CLOCK PULSES.
m, ADDR.)
Figure 4.
This instruction is the same in operation and format as the 5MB
instruction except that a reset to "0" of the bit results.
Data Retention Timing
CLOCK OSCILLATOR
BRANCH ON BIT SET RELATIVE (BBS m, ADDR, DEST)
,
RAM RETENTION MODE
A reference frequency can be generated with the on-chip oscillator using an external crystal. The oscillator reference frequency
passes through an internal countdown network (divide by 2) to
obtain the internal operating frequency (see Figure 5a). The
on-chip oscillator is designed for a parallel resonant crystal connected between XTU and XTLO pins. The equivalent oscillator
circuit is shown in Figure 5.
This instruction tests one of 8 bits designated by a three bit
immediate field within the first byte of the instruction. The second
byte is used to designate the address of the byte to be tested
within the zero page address range (memory or 110 ports). The
third byte of the instruction is used to specify the 8 bit relative
address to which the instruction branches if the bit tested is a
"1". If the bit tested is not set, the next sequential instruction
is executed.
A parallel resonant crystal is specified by its load capacitance
and series resonant resistance. For proper oscillator operation,
the load capacitance (Cu, series resistance (Rs) and the crystal resonant frequency (F) must meet the following two relations:
BRANCH ON BIT RESET RELATIVE
(BBR m, ADDR, DEST)
This instruction is the same in operation and format as the BBS
instruction except that a branch takes place if the bit tested is
(C + 27)
a "0".
= 2CL
or
C
= 2CL
-
27 pF
2x 10·
Rs :s; Rsmax = (FCd 2
READ ONLY MEMORY (ROM)
This device has no internal application ROM. Up to 16K of
external memory can be attached via the 16 address/data and
timing pins.
where: F is in MHz; CL is in pF; and R is in ohms.
To select a parallel resonant crystal for the oscillator, first select
the load capacitance from a crystal manufacturer's catalog. Next,
calculate Rsmax based on F and C L• The selected crystal must
have a Rs less than the Rsmax.
RANDOM ACCESS MEMORY (RAM)
The RAM consists of 192 bytes of read/write memory with an
assigned page zero address of 0040 through OOFF. The
3-178
R6518
One-Chip Microprocessor
For example, if CL = 22 pF for a 4 MHz parallel resonant crystal, then
ADOR 0014
MCR
C = (2 x 22) - 27 = 17 pF
(use standard value of 18 pF)
COUNTER B
MTST
The series resistance of the crystal must be less than
BUS MODE SELECT
R,ma< =
2 x 106 = 258 ohms
(4 x 22)2
o-
1 - 1 RETRIGGERABLEINTERVAL TIMER
PORT B LATCH
(1
ENABLED)
=
PORT 0 TRI-STATE
1 = NORMAL
1-
1 MUX'DBUS
Figure 6.
1:
::- C±5%
XTLI
The use of Counter S Mode Select is shown in Section
"Counter S".
:1"""
27 pF
The use of Port S Latch Enable is shown in Section
"Port S (PS)".
-=-
A. CRYSTAL INPUT
2-4 MHz
INTERRUPT FLAG REGISTER (IFR) AND
INTERRUPT ENABLE REGISTER (IER)
~LI
An IRQ interrupt request can be initialized by any or all of eight
possible sources. These sources are all capable of being enabled or disabled by the use of the appropriate interrupt enabled
bits in the Interrupt Enable Register (IER). Multiple simultaneous interrupts will cause the IRQ interrupt request to remain
active until all interrupting conditions have been serviced and
cleared.
NC~LO
1-2MHZ~LI
v __
~LO
The Interrupt Flag Register contains the information that
indicates which I/O or counter needs attention. The contents of
the Interrupt Flag Register may be examined at any time by reading at address: 0011. Edge detect IFR bits may be cleared by
executing a RMS instruction at address location 0010. The RMS
X, (0010) instruction reads FF, modifies bit X to a "0", and writes
the modified value at address location 0011. In this way IFR bits
set to a "1" after the read cycle of a Read-Modify-Write instruction (such as RMS) are protected from being cleared. A logic
"1" is ignored when writing to edge detect IFR bits.
Vss ~
B. CLOCK INPUTS
Figure 5.
Mode Control Register
The use of Counter A Mode Select is shown in Section
"Counter A".
27 pF
XTLO
0 INTERVAL TIMER
0 - 1 ASVMMETRIC PULSE GENERATION
10 EVENT COUNTER
Internal timing can also be controlled by driving the XTU pin
with an external frequency source. Figure 5b shows typical connections. If XTLO is left floating, the external source is divided
by the internal countdown network. However, if XTLO is tied to
Vss , the internal countdown network is bypassed causing the
chip to operate at the frequency of the external source.
C±5%
CT
Clock Oscillator Input Options
MODE CONTROL REGISTER (MCR)
The Mode Control Register contains a control bit for Port S
and mode select bits for Counter A and Counter S. Its setting,
along with the setting of the Serial Communications Control
Register (SCCR), determines the basic configuration of the
device in any application. Initializing this register is one of the
first actions of any software program. MCR bits 7, 6, 5 must
remain 1s in order for external memory referencing to be
enabled. The Mode Control Register bit assignment is shown
in Figure 6.
Each IFR bit has a corresponding bit in the Interrupt Enable
Register which can be set to a "1" by writing a "1" in the respective bit position at location 0012. Individual IER bits may be
cleared by writing a "0" in the respective bit position, or by RES.
If set to a "1", an IRQ will be generated when the corresponding IFR bit becomes true. The Interrupt Flag Register and Interrupt Enable Register bit assignments are shown in Figure 7 and
the functions of each bit are explained in Table 2.
3-179
One-Chip Microprocessor
R6518
PROCESSOR STATUS REGISTER
IFR
ADDR 0011
IER
AOOR 0012
The 8-bit Processor Status Register, shown in Figure 8 contains
seven status flags. Some of these flags are controlled by the
user program; others may be controlled both by the user's program and the CPU. The R6502 instruction set contains a number of conditional branch instructions which are designed to allow
testing of these flags. Each of the eight processor status flags
is described in the following sections.
PAO POSITIVE
EDGE DETECT
CARRY BIT (e)
PA2 NEGATIVE
EDGE DETECT
PA3 NEGATIVE
The Carry Bit (C) can be considered as the ninth bit of an arithmetic operation. It is set to logic 1 if a carry from the eighth bit
has occurred or cleared to logic 0 if no carry occurred as the
result of arithmetic operations.
EDGE DETECT
COUNTER A
UNDERFLOW FLAG
COUNTER S
UNDERFLOW
FLAG
RECEIVER
FLAG
The Carry Bit may be set or cleared under program control by
use of the Set Carry (SEC) or Clear Carry (CLC) instruction,
respectively. Other operations which affect the Carry Bit are
ADC, ASL, CMP, CPX, CPY, LSR, PLP, ROL, RPR, RTI, and
SBC.
XMTR
FLAG
Figure 7.
Interrupt Enable and Flag Registers
Table 2.
Interrupt, Flag Register Bit Codes
Bit
Code
Function
IFR 0:
PAD Positive Edge Detect Flag-Set to a "1" when a positive going edge is detected on PAD.
Cleared by RMB 0 (0010) instruction or by RES.
IFR 1:
PA1 Positive Edge Detect Flag-Set to a 1 when a positive going edge is detected on PA1.
Cleared by RMB 1 (0010) instruction or by RES.
IFR 2:
PA2 Negative Edge Detect Flag-Set to a 1 when a negative going edge is detected on PA2.
Cleared by RMB 2 (0010) instruction or by RES.
IFR 3:
PA3 Negative Edge Detect Flag-Set to 1 when a negative going edge is detected on PA3.
Cleared by RMB 3 (0010) instruction or by RES.
IFR 4:
Counter A Underflow Flag-Set to a 1 when Counter A underflow occurs. Cleared by reading the
Lower Counter A at location 0018, by writing to address location 001A, or by RES.
IFR 5:
Counter B Underflow Flag-Set to a 1 when Counter B underflow occurs. Cleared by reading the
Lower Counter B at location 001 C, by writing to address location 001 E, or by RES.
IFR 6:
IRF 7:
Receiver Interrupt Flag-Set to a 1 when any of the Serial Communication Status Register bits
othrough 3 is set to a 1. Cleared when the Receiver Status bits (SCSRO-3) are cleared or by RES.
Transmitter Interrupt Flag-Set to a 1 when SCSR6 is set to a 1 while SCSR5 is a 0 or SCSR7
is set to a 1. Cleared when the Transmitter Status bits (SCSR6 & 7) are cleared or by RES.
3-180
One-Chip Microprocessor
R6518
as a decimal adder. When this bit is cleared to logic 0, the adder
operates as a straight binary adder. The adder mode is controlled
only by the programmer. The Set Decimal Mode (SED) instruction will set the D bit; the Clear Decimal Mode (CLD) instruction
will clear it. The PLP and RTI instructions also effect the Decimal
Mode Bit.
CARRY (C) (i)
1 CARRY SET
0= CARRY CLEAR
=
ZERO (Z) (i)
1 ZERO RESULT
0= NON-ZERO RESULT
CAUTION
=
The Decimal Mode Bit will either set or clear in an
unpredictable manner upon power application. This bit
must be initialized to the desired state by the user program or erroneous results may occur.
0
INTERRUPT DISABLE (I)
1 = IRQ INTERRUPT DISABLED
0= IRQ INTERRUPT ENABLED
DECIMAL MODE (D)
1 = DECIMAL MODE
0= BINARY MODE
(i)
BREAK BIT (B)
BREAK COMMAND (B) (i)
1 = BREAK COMMAND
0= NON-BREAK COMMAND
The Break Bit (B) is used to determine the condition which
caused the IRQ service routine to be entered. If the IRQ service
routine was entered because the CPU executed a BRK command, the Break Bit will be set to logic 1. If the IRQ routine was
entered as the result of an IRQ signal being generated, the B bit
will be cleared to logic o. There are no instructions which can
set or clear this bit.
OVERFLOW (0) (i)
1 = OVERFLOW SET
0= OVERFLOW CLEAR
NEGATIVE (N) (i)
1 = NEGATIVE VALUE
o= POSITIVE VALUE
NOTES:
OVERFLOW BIT (V)
(i)
The Overflow Bit M is used to indicate that the result of a signed,
binary addition, or subtraction, operation is a value that cannot
be contained in seven bits (-128 :5 n :5 127).
o
NOT INITIALIZED BY RES
SET TO LOGIC 1 BY RES
Figure 8.
Processor Status Register
This indicator only has meaning when Signed arithmetic (sign
and seven magnitude bits) is performed. When the ADC or SBC
instruction is performed, the Overflow Bit is set to logic 1 if the
polarity of the sign bit (bit 7) is changed because the result
exceeds + 127 or -128; otherwise the bit is cleared to logic O.
The V bit may also be cleared by the programmer using a Clear
Overflow (CLV) instruction.
ZERO BIT (Z)
The Zero Bit (Z) is set to logic 1 by the CPU during any data
movement or calculation which sets all 8 bits of the result to zero.
This bit is cleared to logic 0 when the resultant 8 bits of a data
movement or calculation operation are not all zero. The R6500
instruction set contains no instruction to specifically set or clear
the Zero Bit. The Zero Bit is, however, affected by the following
instructions; ADC, AND, ASL, BIT, CMP, CPX, CPY, DEC, DEX,
DEY, EOR, INC, INX, INY, LDA, LDX, LDY, LSR, ORA, PLA,
PLP, ROL, ROR, RTI, SBC, TAX, TAY, TXA, TSX, and TVA.
The Overflow Bit may also be used with the BIT instruction. The
BIT instruction which may be used to sample interface devices,
allows the overflow flag to reflect the condition of bit 6 in the
sampled field. During a BIT instruction the Overflow Bit is set
equal to the content of the bit 6 on the data tested with BIT
instruction. When used in this mode, the overflow has nothing
to do with signed arithmetic, but is just another sense bit for the
microprocessor. Instructions which affect the V flag are ADC,
BIT, CLV, PLP, RTI and SBC.
INTERRUPT DISABLE BIT (I)
The Interrupt Disable Bit (I) is used to control the servicing of
an interrupt request (IRQ). If the I Bit is reset to logic 0, the IRQ
signal will be serviced. If the bit is set to logic 1i the IRQ signal
will be ignored. The CPU will set the Interrupt Disable Bit to logic
1 if a RESET (RES), IRQ, or Non-Maskable Interrupt (NMI) signal
is detected.
NEGATIVE BIT (N)
The Negative Bit (N) is used to indicate that the sign bit (bit 7),
in the resulting value of a data movement or data arithmetic operation, is set to logic 1. If the sign bit is set to logic I, the resulting value of the data movement or arithmetic operation is
negative; if the sign bit is cleared, the result of the data movement or arithmetic operation is positive. There are no instructions that set or clear the Negative Bit since the Negative Bit
represents only the status of a result. The instructions that effect
the state of the Negative Bit are: ADC, AND, ASL, BIT, CMP,
CPX, CPY, DEC, DEX, DEY, EOR, INC, INX, INY, LDA, LDX,
LDY, LSR, ORA, PLA, PLP, ROL, ROR, RTI, SBC, TAX, TAY,
TSX, TXA, AND TVA.
The I bit is cleared by the Clear Interrupt Mask Instruction (CLI)
and is set by the Set Interrupt Mask Instruction (SEI). This bit
is set by the BRK Instruction. The Return from Interrupt (RTI)
and Pull Processor Status (PLP) instructions will also affect the
I bit.
DECIMAL MODE BIT (D)
The DeCimal Mode Bit (D), is used to control the arithmetic mode
of the CPU. When this bit is set to logic I, the adder operates
3-181
One-Chip Microprocessor
R6518
PARALLEL INPUT/OUTPUT PORTS
The R6518 has 16 I/O lines grouped into two 8-bit ports (PA,
PB). Ports A and B may be used either for input or output
individually or in groups of any combination.
bit positions. A logic 1 will force a high (>2.4V) output while a
logic D will force a low «D.4V) output.
Multifunction I/O's in Port A are protected from normal port I/O
instructions when they are programmed to perform a multiplexed
function.
PORT A (PA)
Port A can be programmed via the Mode Control Register (MCR)
and the Serial Communications Control Register (SCCR) as a
standard parallel 8-bit, bit independent, I/O port or as serial channel I/O lines, counter I/O lines, or an input data strobe for the
Port B input latch option. Table 4 tabulates the control and usage
of Port A.
Internal pull-up resistors (FET's with an impedance range of
3K :5 Rpu :5 12K ohm) are provided on all port pins.
The direction of the I/O lines are controlled by 8-bit port registers
located in page zero. This arrangement provides quick programming access using simple two-byte zero page address instructions. There are no direction registers associated with the I/O
ports, which simplifies I/O handling. The I/O addresses are
shown in Table 3. I/O Port Timing is shown on page 29.
Table 3.
In addition to their normal I/O functions, PAD and PAl can detect
positive going edges, and PA2 and PA3 can detect negative
going edges. A proper transition on these pins will set a
corresponding status bit in the IFR and generate an interrupt
request if the respective Interrupt Enable Bit is set. The maximum rate at which an edge can be detected is one-half the
phase 2 (02) clock rate. Edge detection timing is shown on
page 29.
I/O Port Addresses
Port
Address
A
B
0000
0001
PORT B (PB)
INPUTS
Port B can be programmed as an 8 bit, bit independent I/O port.
It has a latched input capability which may be enabled or disabled via the Mode Control Register (MCR). Table 5 tabulates
the control and usage of Port B. An Input Data Strobe signal
must be provided through PAD when Port B is programmed to
be used with latched input option. Input data latch timing for
Port B is shown on page 29.
Inputs for Ports A and B are enabled by loading logic 1 into all
I/O port register bit positions that are to correspond to I/O input
lines. A low « D.8V) input signal will cause a logic D to be read
when a read instruction is issued to the port register. A high
(>2.DV) input will cause a logic 1 to be read. An RES signal
forces both I/O port registers to logic 1 thus initially treating all
110 lines as inputs.
Table 5.
The status of the input lines can be interrogated at any time by
reading the I/O port addresses. Note that this will return the
actual status of the input lines, not the data written into the 110
port registers.
Port B Control & Usage
Latch
Mode
110 Mode
MCR4
Ready/ModifylWrite instructions can be used to modify the
operation of PA and PB. During the Read cycle of a
Read/Modify/Write instruction the Port I/O register is read. For
all other read instructions the port input lines are read.
Read/ModifylWrite instructions are: ASl, DEC, INC, lSR, RMB,
ROl, ROR, and 5MB.
OUTPUTS
=
0
MCR4 = 1
(2)
Signal
Signal
Pin
Name
Name
Type (1)
Name
Type
PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7
PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
(1) Resistive pull-up, active buffer pull down
(2) Input data is stored in port B latch by PAO pulse
Outputs for Ports A and B are controlled by writing the desired
I/O line output states into the corresponding I/O port register
3-182
One-Chip Microprocessor
R6518
Table 4.
Port A Control & Usage
PAO 1/0
PORT B LATCH MODE
=0
MCR4
MCR4
SIGNAL
PAD (2)
=1
SIGNAL
NAME
TYPE
NAME
TYPE
PAO
I/O
PORT B
LATCH STROBE
INPUT (1)
PA1-PA31/0
PA1(2)
SIGNAL
PA2(3)
NAME
TYPE
PA3 (3)
PAl
PA2
PA3
1/0
1/0
1/0
COUNTER A 1/0
PA41/0
PA4
MCRO = 0
MCRI = 0
SCCR? = 0
RCVR SIR MODE ~ 0
(4) (5)
MCRO = 1
MCRI = 0
SCCR? = 0
RCVR SIR MODE = 0
(4)
SIGNAL
SCCR? = 0
SCCR6 = 0
MCRI = 1
SIGNAL
SIGNAL
NAME
TYPE
NAME
TYPE
NAME
PA4
I/O
CNTA
OUTPUT
CNTA
I
I
TYPE
INPUT (1)
SERIAL I/O SHIFT REGISTER CLOCK •
SCCR?
SCCR5
=1
=1
RCVR SIR MODE = 1
(4)
SIGNAL
I
I
NAME
XMTR CLOCK
SIGNAL
TYPE
NAME
OUTPUT
RCVR CLOCK
PA51/0
MCR3
MCR2
PAS
I
I
TYPE
INPUT (1)
COUNTER B I/O
=0
=0
MCR3
MCR2
SIGNAL
~
0
MCR3
MCR2
=1
=1
=X
SIGNAL
SIGNAL
NAME
TYPE
NAME
TYPE
NAME
I
TYPE
PA5
I/O
CNTB
OUTPUT
CNTB
I
INPUT (1)
PA6
SCCR?
PA6
SERIAL 1/0
XMTROUTPUT
VO
=0
SCCR?
SIGNAL
=1
SIGNAL
NAME
TYPE
NAME
TYPE
PAS
I/O
XMTR
OUTPUT
SERIAL 1/0
RCVRINPUT
PA?IIO
SCCR6
PAl
=0
SCCR6
=1
SIGNAL
SIGNAL
NAME
TYPE
NAME
TYPE
PAl
I/O
RCVR
INPUT (1)
3-183
Notes:
(1) Hardware Buffer Float
(2) Pasttive Edge Detect
(3) Negative Edge Detect
(4) RCVR SIR Mode = 1 when
SCCR6 • SCCR5 • SCCR4 = 1
(5) For the following mode cambina·
tians PA4 is available as an input
only pin:
SCCR?·SCCR60SCCR5.MCRI
+ SCCR?·SCCR60SCCR4·MCR1
+ SCCR?·SCCR&SCCR5
+ SCCR?·SCCR50SCCR4-
One-Chip Microprocessor
R6518
SERIAL INPUT/OUTPUT CHANNEL
The device provides a full duplex Serial 1/0 channel with
programmable bit rates and operating modes. The serial 1/0
functions are controlled by the Serial Communication Control
Register (SCCR). The SCCR bit assignment is shown in Figure 9.
The serial bit rate is determined by Counter A for all modes
except the Receiver Shift Register (RCVR SIR) mode for which
an external shift clock must be provided. The maximum data
rate using the internal clock is 62.5K bits per second (@ 02 =
1 MHz). The transmitter (XMTR) and receiver (RCVR) can be
independently programmed to operate in different modes and
can" be independently enabled or disabled.
ASYNCHRONOUS MODE WITHOUT PARITY
\ST!RTI
~~ul
I
8_BITDAT'"
2 STOP
________________________
L -_ _ _ _~
2·STDP
I
ASYNCHRONOUS MODE WITH PARITY
\PA~'TYI
SCCR
IPA~'TVI
IPA~ITV I
&-BITDATA
2 STOP
2 STOP
2 STOP
o PARITY DISABLE
o
o
1
1
0 XMTR
o 1 XMTR
1
X XMTR
o RCVR DISABLE
1 RCVR ENABLE
o XMTR DISABLE
1 XMTR ENABLE
o
Figure 9.
SHIFT REGISTER MODE 8-BIT DATA
1 PARITY ENABLE
0-8 BITS/CHAR
1-7 BITS/CHAR
0-6 BITS/CHAR
1-5 BITSCHAR
AND RCVR ASYN MODE
ASYN RCVR SIR
SIR RCVR ASYN
WORDM
I
WOROM+1
SHIFT REGISTER CLOCK (PA4)
Figure 10.
Transmitter Data Modes
In the SIR mode, eight data bits are always shifted out. Bitsl
character and parity control bits are ignored. The serial data is
shifted out via the SO output (PA6) and the shift clock is available
at the CA (PA4) pin. When the transmitter under-runs in the
SIR mode the SO output and shift clock are held in a high state.
Serial Communication Control Register
Except for the Receiver Shift Register Mode (RCVR SIR), all
XMTR and RCVR bit rates will occur at one sixteenth of the
Counter A interval timer rate. Counter A is forced into an interval timer mode whenever the serial 1/0 is enabled in a mode
requiring an internal clock.
The XMTR Interrupt Flag bit (IFR7) is controlled by Serial
Communication Status Register bits SCSR5, SCSR6 and
SCSR7.
IFR7 = SCSR6 (SCSR5 + SCSR7)
RECEIVER OPERATION (RCVR)
Whenever Counter A is required as a timing source it must be
loaded with the hexadecimal code that selects the data rate for
the serial I/O Port. Refer to Section "Counter A," Table 6 for
hexadecimal values to represent the desired data rate.
The receiver and its selected control and status functions are
enabled when SCCR6 is set to a "1". In the ASYN mode, data
format must have a start bit, appropriate number of data bits,
a parity bit (if enabled) and one stop bit. Refer to Figure 10 for
a diagram of bit allocations. The receiver bit period is divided
into 8 sub-intervals for internal synchronization. The receiver bit
stream is synchronized by the start bit and a strobe signal is
generated at the appropriate center of each incoming bit. Refer
to Figure 11 for ASYN Receive Data Timing. The character
assembly process does not start if the start bit signal is less than
one-half bit time after a low level is detected on the Receive Data
Input. Framing error, over-run, and parity error conditions or a
RCVR Data Register Full will set the appropriate status bits, and
any of the above conditions will cause an Interrupt Request if
the Receiver Interrupt Enable bit is set to logic 1.
TRANSMITTER OPERATION (XTMR)
The XTMR operation and the transmitter related controllstatus
functions are enabled by bit 7 of the Serial Communications Control Register (SCCR). The transmitter, when in the Asynchronous
(ASYN) mode, automatically adds a start bit, one or two stop
bits, and when enabled, a parity bit to the transmitted data. A
word of transmitted data (in asynchronous parity mode) can have
5-,6-,7-, or 8-bits of data. The nine data modes are in Figure 10.
When parity is disabled, the 5-, 6-, 7- or 8-bits of data are terminated with two stop bits.
3-184
One-Chip Microprocessor
R6518
SERIAL
INPUT -'l,,=:J:~~:::::::
START LSB
BIT
INTERNAL
1
a parity error. This bit is cleared by reading the Receiver Data
Register or by RES.
=:::::r=::rl=:-rl=:rl
STOP STOP
BIT
seSR3: Framing Error-Set to a logic 1 when the received data
contains a zero bit after the last data or parity bit in the stop
bit slot. Cleared by reading the Receiver Data Register or by
RES. (ASYN Mode only).
BIT
~~g=JK L.Fl.......fL..~
SCSR4: Wake-Up-Set to a logic 1 by writing a "1" in bit 4 of
address: 001S. The Wake-Up bit is cleared by RES or when
the receiver detects a string of ten consecutive 1s. When the
Wake-Up bit is set SCSRO through SCSR3 are inhibited.
'SERIAL INPUT DATA SHIFTED IN
Figure 11.
ASYN Receive Data Timing
seSR5: End of Transmission-Set to a logic 1 by writing a "1 "
in bit position 5 of address: 001S. The End of Transmission bit
is cleared by RES or upon writing a new data word into
the Transmitter Data Register. When the End-of-Transmission
bit is true the Transmitter Data Register Empty bit is disabled
until a Transmitter Under-Run occurs.
In the SIR mode, an external shift clock must be provided at
CA (PA4) pin along with 8 bits of serial data (LSB first) at the
SI input (PA7). The maximum data rate using an external shift
clock is one-eighth the internal clock rate. Refer to Figure 12
for SIR Mode Timing.
seSR6: Transmitter Data Register Empty-Set to a logic 1
when the contents of the Transmitter Data Register are transferred to the Transmitter Shift Register. Cleared upon writing
new data into the Transmit Data Register. This bit is initialized
to a logic 1 by RES.
SCSR7: Transmitter Under-Run-Set to a logic 1 when the last
data bit is transmitted if the transmitter is in a SIR Mode or when
the last stop bit is transmitted if the XMTR is in the ASYN Mode
while the Transmitter Data Register Empty Bit is set. Cleared
by a transfer of new data into the Transmitter Shift Register, or
by RES.
'SERIAL INPUT DATA SHIFTED IN
"SERIAL OUTPUT DATA MAKES TRANSITION
Figure 12.
SIR Mode Timing
SCSR
A RCVR interrupt (IFRS) is generated whenever any of SCSRO-3
are true.
SERIAL COMMUNICATION STATUS
REGISTER (SCSR)
PARITY ERROR
FRAME ERROR
WAKE-UP
END OF TRANSMISSION
XMTR DATA REG EMPTY
XMTR UNDER-RUN
The Serial Communication Status Register (SCSR) holds information on various communication error conditions, status of
the transmitter and receiver data registers, a transmitter
end-of-transmission condition, and a receiver id'ie line condition
(Wake-Up Feature). The SCSR bit assignment is shown in
Figure 13, SCSR bit assignments and functions are:
Figure 13.
seSRO: Receiver Data Register FUll-Set to a logic 1 when a
character is transferred from the Receiver Shift Register to the
Receiver Data Register, This bit is cleared by reading the
Receiver Data Register, or by RES and is disabled if
SCCRS = 0, The SCSRO bit will not be set to a logic 1 if the
received data contains an error condition, instead, a corresponding error bit will be set to a logic 1.
SeSR Bit Allocation
WAKE-UP FEATURE
In multi-distributed microprocessor or microcomputer applications, a destination address is usually included at the beginning
of the message, The Wake-Up Feature allows non-selected
CPU's to ignore the remainder of the message until the beginning of the next message by setting the Wake-Up bit. As long
as the Wake-Up flag is true, the Receiver Data Register Full Flag
remains false. The Wake-Up bit is automatically cleared when
the receiver detects a string of ten consecutive ls which indicates an idle transmit line. When the next byte is received, the
Receiver Data Register Full Flag signals the CPU to wake-up
and read the received data,
SeSR1: Over-Run Error-Set to a logic 1 when a new character
is transferred from the Receiver Shift Register, with the last
character still in the Receiver Data Register. This bit is cleared
by reading the Receiver Data Register, or by RES.
SeSR2: Parity Error-Set to a logic 1 when the RCVR is in the
ASYN Mode, Parity Enable bit is set, and the received data has
3-185
II
One-Chip Microprocessor
R6518
COUNTER/TIMERS
The device ,contains two 16-bit counters (Counter A and
Counter B) and three 16-bit latches associated with the counters.
Counter A has one 16-bit latch and Counter B has two 16-bit
latches. Each counter can be independently programmed to
operate in one of four modes:
Counter A
Counter B
• Pulse width
measurement
• Pulse Generation
• Interval Timer
• Event Counter
• Retriggerable Interval Counter
• Asymmetrical Pulse
Generation
• Interval Timer
• Event Counter
Counter A operates in any of four modes. These modes are
selected by the Counter A Mode Select bits in the Mode Control Register.
MCRI
(bit 1)
MCRO
(bit 0)
Mode
0
0
1
1
0
1
0
1
Interval Timer
Pulse Generation
Event Counter
Pulse Width Measurement
The Interval Timer, Pulse Generation, and Pulse Width Measurement Modes are 02 clock counter modes. The Event Counter
Mode counts the occurrences of an external event on the CNTR
line.
Operating modes of Counter A and Counter B are controlled by
the Mode Control Register. All counting begins at the initialization value and decrements. When modes are selected requiring a counter input/output line, PA4 is automatically selected
for Counter A and PA5 is automatically selected for Counter B
(see Table 4).
The Counter is set to the Interval Timer Mode (00) when a RES
signal is generated.
INTERVAL TIMER
COUNTER A
In the Interval Timer mode the Counter is initialized to the Latch
value by either of two conditions:
Counter A consists of a 16-bit counter and a 16-bit latch
organized as follows: Lower Counter A (LCA), Upper Counter A
(UCA), Lower Latch A (LLA), and Upper Latch A (ULA). The
counter contains the count of either 02 clock pulses or external
events, depending on the counter mode selected. The contents
of Counter A may be read any time by executing a read at
location 0019 for the Upper Counter A and at location OOIA or
location 0018 for the Lower Counter A. A read at location 0018
also clears the Counter A Underflow Flag (IFR4).
I. When the Counter is decremented from 0000, the next
Counter value is the Latch value (not FFFF).
2. When a write operation is performed to the Load Upper
Latch and Transfer Latch to Counter address 001 A, the
Counter is loaded with the Latch value. Note that the contents of the Accumulator are loaded into the Upper Latch
before the Latch value is transferred to the Counter.
The 16-bit latch contains the counter initialization value, and can
be loaded at any time by executing a write to the Upper Latch A
at location 0019 and the Lower Latch A at location 0018. In either
case, the contents of the accumulator are copied into the
applicable latch register.
The Counter value is decremented by one count at the 02 clock
rate. The 16-bit Counter can hold from I to 65535 counts. The
Counter Timer capacity is therefore I p'S to 65.535 ms at the
I MHz 02 clock rate or 0.5 P.s to 32.7675 ms at the 2 MHz 02
clock rate. Time intervals greater than the maximum Counter
value can be easily measured by counting IRQ interrupt requests
in the counter IRQ interrupt routine.
Counter A can be started at any time by writing to address: OOIA.
The contents of the accumulator will be copied into the Upper
Latch A before the contents of the 16-bit latch are transferred
to Counter A. Counter A is set to the latch value whenever
Counter A underflows. When Counter A decrements from 0000
the next counter value will be the latch value, not FFFF, and
the Counter A Underflow Flag (IFR 4) will be set to "1". This
bit may be cleared by reading the Lower Counter A at location
0018, by writing to address location OOIA, or by RES.
When Counter A decrements from 0000, the Counter A
Underflow (IFR4) is set to logic I. If the Counter A Interrupt
Enable Bit (IER4) is also set, an IRQ interrupt request will be
generated. The Counter A Underflow bit in the Interrupt Flag
Register can be examined in the IRQ interrupt routine to
determine that the IRQ was generated by the Counter A
Underflow.
3-186
R6518
One-Chip Microprocessor
PULSE WIDTH MEASUREMENT MODE
While the timer is operating in the Interval Timer Mode, PA4
operates as a PA 1/0 bit.
This mode allows the accurate measurement of a low pulse duration on the CA line. The Counter decrements by one count at
the 02 clock rate as long as the CA line is held in the low state.
The Counter is stopped when CA is in the high state.
A timing diagram of the Interval Timer mode is shown in
Figure 14.
The Counter A underflow flag will be set only when the count
in the timer reaches zero. Upon reaching zero the timer will be
loaded with the latch value and continue counting down as long
as the CA pin is held low. After the counter is stopped by a high
level on CA, the count will hold as long as CA remains high.
Any further low levels on CA will again cause the counter to count
down from its present value. The state of the CA line can be
determined by testing the state of PA4 (Figure 16).
I
COUNTER UNDERFLOW
COUNTER
j
I
=~-'-_":"""-'-_'---L--'~...JI..l(""UL~ I(UL,LL)-'I
COUNTER
INTERRUPT
ENABLED
I SET ANY TIME
'BEFORE COUNTER
COUNTER
UNDERFLOW
UNDER"-F~LO~W~_ _ _ _ _ _ _---,I
FLAG -
I
I
.--+-____
_
I
IRq
\12
Figure 14.
Interval Timer Timing Diagram
--1 f- Tposu
2.0V
CNTR
PULSE GENERATION MODE
COUNT
In the Pulse Generation mode, the CA line operates as a Counter
Output. The line toggles from low to high or from high to low
whenever a Counter A Underflow occurs, or a write is performed
to address 00lA.
N
I N-l
Figure 16.
The normal output wave form is a symmetrical square-wave. The
CA output is initialized high when entering the mode and transitions low when writing to 00lA.
N-2
N-3
Pulse Width Measurement Timing
SERIAL 1/0 DATA RATE GENERATION
Counter A also provdes clock timing for the Serial 1/0 which
establishes the data rate for the Serial 1/0 port. When the Serial
1/0 is enabled, Counter A is forced to operate at the internal clock
rate. Counter A is not required for the RCVR SIR mode. The
Counter 1/0 (PA4) may also be required to support the Serial
1/0 (see Table 4).
Asymmetric waveforms can be generated if the value of the latch
is changed after each counter underflow.
A one-shot waveform can be generated by changing from Pulse
Generation to Interval Timer mode after only one occurrence
of the output toggle condition.
Table 6 identifies the values to be loaded in Counter A for selecting standard data rates with a 02 clock rate of 1 MHz and 2 MHz.
Although Table 6 identifies only the more common data rates,
any data rate from 1 to 62.5K bps can be selected by using the
formula:
EVENT COUNTER MODE
In this mode the CA is used as an Event Input line, and the
Counter will decrement with each rising edge detected on this
line. The maximum rate at which this edge can be detected is
one-half the 02 clock rate (Figure 15).
N
The Counter can count up to 65,535 occurrences before
underflowing. As in the other modes, the Counter A Underflow
bit (IER4) is set to logic 1 if the underflow occurs.
16
02
-1
x bps
where
N
= decimal value to be loaded into Counter A using
its hexadecimal equivalent
02 = the clock frequency (1 MHz or 2 MHz)
bps = the desired data rate.
NOTE
Figure 15.
In Table 6 you will notice that the standard data rate and
the actual data rate may be slightly different. Transmitter
and receiver errors of 1.5% or less are acceptable. A
revised clock rate is included in Table 6 for those baud
rates which fall outside this limit.
Event Counter Mode Timing
3-187
R6518
Table 6.
One-Chip Microprocessor
Counter A Values for Baud Rate Selection
LATCH VALUE
Standard
Baud
Rate
50
75
110
150
300
600
1200
2400
3600
4800
7200
9600
Hexadecimal
Value
1 MHz 2 MHz
04E1
0340
0237
01AO
OOCF
0067
0033
0019
0010
OOOC
0008
0006
09C3
0682
046F
0340
01AO
OOCF
0067
0033
0021
0019
0010
OOOC
Actual
Baud
Rate
At
1 MHz
2 MHz
50.00
75.03
110.04
149.88
300.48
600.96
1201.92
2403.85
3676.47
4807.69
6944.44
8928.57
50.00
74.99
110.04
150.06
299.76
600.96
1201.92
2403.85
3676.47
4807.69
7352.94
9615.38
Clock Rate
Needed to Get
Standard
Baud Rate
OOOO--------------~----------~-------1
1 MHz 2 MHz
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
0.9792
1.0000
1.0368
1.0752
2.0000
2.0000
2.0000
2.0000
2.0000
2.0000
2.0000
2.0000
1.9584
2.0000
1.9584
2.0000
RESET BY
COUNTER B
FLAG
Figure 17.
_ _ _ _ _.....Ir-l4/ SOFTWARE
!
!
Counter B Retriggerable Interval Timer Mode
ASYMMETRICAL PULSE GENERATION MODE
Counter B has a special Asymmetrical Pulse Generation Mode
whereby a pulse train with programmable pulse width and period
can be generated wilhout the processor intervention once the
latch values are initialized.
COUNTER B
Counter B consists of a 16-bit counter and two 16-bit latches
organized as follows: Lower Counter B (LCB), Upper Counter
B (UCB), Lower Latch B (LLB), Upper Latch B (ULB), Lower
Latch C (LLC), and Upper Latch C (ULC). Latch C is used only
in the asymmetrical pulse generation mode. The counter contains the count of either 02 clock pulses or external events
depending on the counter mode selected. The contents of
Counter B may be read any time by executing a read at location 001 D for the Upper Counter B and at location 001 Ear 001 C
for the Lower Counter B. A read at location 001C also clears
the Counter B Underflow Flag.
In this mode, the 16-bit Latch B is initialized with a value which
corresponds to the duration between pulses (referred to as D
in the following descriptions). The 16-bit Latch C is initialized
with a value which corresponds to the desired pulse width
(referred to as P in the following descriptions). The initialization
sequence for Latch Band C and the starting of a counting
sequence are as follows:
1. The lower 8 bits of P are loaded into LLB by writing to
address 001 C, and the upper 8 bits of P are loaded into
ULB and the full 16 bits are transferred to Latch C by writing
to address location 001 D. At this point both Latch Band
Latch C contain the value of P.
Latch B contains the counter initialization value, and can be
loaded at any time by executing a write to the Upper Latch B
at location 001 D and the Lower Latch B at location 001 C. In each
case, the contents of the accumulator are copied into the
applicable latch register.
2. The lower 8 bits of D are loaded into LLB by writing to
address 001C, and the upper 8 bits of D are loaded into
ULB by writing to address location 001 E. Writing to address
location 001 E also causes the contents of the 16-bit Latch
B to be downloaded into the Counter B and causes the CB
output to go low as shown in Figure 18.
Counter B can be initialized at any time by writing to address:
001 E. The contents of the accumulator is copied into the Upper
Latch B before the value in the 16-bit Latch B is transferred to
Counter B. Counter B will also be set to the latch value and the
Counter B Underflow Flag bit (IFR5) will be set to a "1" whenever
Counter B underflows by decrementing from 0000.
3. When the Counter B underflow occurs the contents of the
Latch C is loaded into the Counter B, and the CB output
toggles to a high level and stays high until another underflow
occurs. Latch B is then down-loaded and the CB output
toggles to a low level repeating the whole process.
IFR 5 may be cleared by reading the Lower Counter B at location 001C, by writing to address location 001E, or by RES.
Counter B operates in the same manner as Counter A in the
Interval Timer and Event Counter modes. The Pulse Width
Measurement Mode is replaced by the Retriggerable Interval
Timer Mode and the Pulse Generation mode is replaced by the
Asymmetrical Pulse Generation Mode.
CB
OUTP\JT
2 3
4
RETRIGGERABLE INTERVAL TIMER MODE
When operating in the Retriggerable Interval Timer mode,
Counter B is initialized to the latch value by writing to address
001 E, by a Counter B underflow, or whenever a positive edge
occurs on the CB pin (PA5). The Counter B interrupt flag will
be set if the counter underflows before a positive edge occurs
on the CB line. Figure 17 illustrates the operation of this timer
mode.
1 AND 3. COUNTER B
2 AND 4. COUNTER B
Figure 18.
3-188
+-- LATCH B(D)
+-- LATCH C (P)
Counter B Pulse Generation
R6518
One-Chip Microprocessor
POWER-ON/INITIALIZATION CONSIDERATIONS
POWER-ON TIMING
Table 7.
After applications of Vee and VRR power to the device, RES
must be held low for at least eight 02 clock cycles after Vee
reaches operating range and the internal oscillator has stabilized. This stabilization time is dependent upon the input Vee
voltage and performance of the internal oscillator. The clock can
be monitored at 02 (pin 3). Figure 19 illustrates the power turn-on
waveforms. Clock stabilization time is typically 20 ms.
RES Initialization of 1/0 Ports and Registers
7
Registers
Processor Status
Mode Control (MCR)
In!. Enable (IER)
In!. Flag (IFR)
Ser. Com. Control (SCCR)
Sar. Com. Status (SCSR)
6
5
4
- - - -
3
2
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
-
1
0
0
0
1
0
0
0
0
0
0
-
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Ports
PA Latch
PB Latch
All RAM and other CPU registers will initialize in a random, nonrepeatable data pattern.
XTlO
1-
-l
I
INITIALIZATION
8 112 CLOCKS
CYCLES MINr--
Figure 19.
Any initialization process for the device should include a RES,
as indicated in the preceding paragraphs. After stabilization of
the internal clock (if a power-on situation) an initialization
subroutine should be executed to perform (as a minimum) the
following functions:
Power Turn-on Timing Detail
POWER-ON RESET
1. The Stack Pointer should be set
The occurrence of RES going from low to high will cause the
device to set the Interrupt Mask Bit - bit 2 of the Processor
Status Register. Both I/O ports (PA, PB) will be forced to the
high (logic 1) state. An internal initialization sequence lasting
16 clock cycles is then performed which sets bits 5-7 of the Mode
Control Register to logic 1, thus enabling external user memory
(Multiplexed Bus Mode). The remaining bits of the Control
Register will be cleared to logic 0 causing the Interval Timers
counter mode (mode 00) to be selected and causing all interrupt
enabled bits to be reset.
2.
3.
4.
5.
Clear or Set Decimal Mode
Set or Clear Carry Flag
Set up Mode Controls as required
Clear Interrupts
A typical initialization subroutine could be as follows:
LOX
TXS
CLD
SEC
RESET (RES) CONDITIONING
When RES is driven from low to high the device is put in a reset
state causing the registers and I/O ports to be configured as
shown in Table 7.
CLI
3-189
Load stack pointer starting address into X Register
Transfer X Register value to Stack Painter
Clear Decimal Mode
Set Carry Flag
Set-up Mode Control and
special function
registers as required
Clear Interrupts
R6518
One-Chip Microprocessor
ENHANCED R6502 INSTRUCTION SET
The following table contains a summary of the R6502 instruction set. For detailed information, consult the R6502 Microcomputer System Programming Manual, Order No. 202. The four
instructions notated with a ' are added instructions to enhance
the standard 6502 instruction set.
Instruction Set In Alphabetic Sequence
Mnemonic
ADC
AND
ASL
'BBR
'BBS
BCC
BCS
BEQ
BIT
BMI
BNE
BPL
BRK
BVC
BVS
Mnemonic
Description
Add Memory to Accumulator with Carry
"AND" Memory with Accumulator
Shift Left One Bit (Memory or Accumulator)
Branch on Bit Reset Relative
Branch on Bit Set Relative
Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits in Memory with Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Force Break
Branch on Overflow Clear
Branch on Overflow Set
CLC
CLD
CLI
CLV
CMP
CPX
CPY
Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable Bit
Clear Overflow Flag
Compare Memory and Accumulator
Compare Memory and Index X
Compare Memory and Index Y
DEC
DEX
DEY
Decrement Memory by One
Decrement Index X by One
Decrement Index Y by One
EOR
"Exclusive-Or" Memory with Accumulator
INC
INX
INY
Increment Memory by One
Increment Index X by One
Increment Index Y by One
JMP
JSR
Jump to New Location
Jump to New Location Saving Return Address
Load Accumulator with Memory
Load Index X with Memory
Load Index Y with Memory
Shift One Bit Right (Memory or (Accumulator)
NOP
No Operation
ORA
PHA
PHP
PLA
PLP
"OR" Memory with Accumulator
Push Accumulator on Stack
Push Processor Status on Stack
Pull Accumulator from Stack
Pull Processor Status from Stack
'RMB
ROL
ROR
RTI
RTS
Reset Memory Bit
Rotate One Bit Left (Memory or Accumulator)
Rotate One Bit Right (Memory or Accumulator)
Return from Interrupt
Return from Subroutine
SBC
SEC
SED
SEI
'SMB
STA
STX
STY
Subtract Memory from Accumulator with Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Set Memory Bit
Store Accumulator in Memory
Store Index X in Memory
Store Index Y in Memory
TAX
TAY
TSX
TXA
TXS
TVA
3-190
Description
LOA
LOX
LOY
LSR
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Accumulator to Index X
Accumulator to Index Y
Stack Pointer to Index X
Index X to Accumulator
Index X to Stack Register
Index Y to Accumulator
:::tI
en
...
U1
(X)
PROCESSOR STATUS
COOES
INSTRUCTIONS
BIT ADDRESSING fOP BY BIT #)
OPERATION
MNEMONIC
ADC
AND
A·M·G-A
A M~A
ASL
C~
B8R[#(O-711
885[#(0-7))
Bee
BGS
BeQ
BIT
8MI
SNE
BPL
BRK
Brancf'lonM.~O
BVe
~
BranchonM.~1
Branch on C""O
BranchonC-l
Branch on Z= 1
AAM
BranchonN-l
BranchonZ=O
BranchonN=Q
Break
(2)
(2)
o-v
A M (I)
X M
Y M
DEC
DEX
DEY
EOR
INC
INX
M l-M
X I-X
V I-Y
AVM-A (1)
M·l-M
X-l-X
INY
JMP
JSR
LOA
lOX
Y·1-Y
Jump to New Loc
Jump Sub
M-A (1)
M_X (1)
LOY
M_Y
lSA
O-~-C
NOP
'ORA
PHA
A ..... Ms
PHP
PlA
PlP
P-Ms S 1-5
S· 1-5 Ms--A
5·1-5 Ms--P
(tl
FO
2
1 0
I
Z C
AIm Sub
A-M-C-A
l-C
1-0
SEI
1_1
(1)
Z C
212
MM..'
•••
2
2
2
2
•
2
40
• 0
cll 6
09
2
2
Z
I
2
I 2 I ED I
• 0
N •••••
Z C
Z C
~; I~
4
Ii
411 61
EB
I3
Z
21
Z
!
I 2 1~~ I : I ~ 1~~ ~
51
I
5
21 81
I
512
591413
6C 15 13
All
61
I 851
4 12
I BO 14 1 3 I B9
Z
BE
B61 412
B41 6TIBC
43
I
17
Z
56
4
I DE
ca
~~ I: I ~I
E9
..
0
Z C
EE 6
4C
20
00
I 2 1 01 I 5 I 2 I 051 4 I 2 I DO I 4 1 3 I 09 I 4 I 3
061 612
AllTO
4E
~
ATS
Z C
Z •
~~I ~~I !~ I ~~ 1~~I g~1 ~~ 1~~
11
A2 2 2 AE
A022AC
Rim Inl -
SEC
seD
4
N V
00 22
10 212
BB
EA 1211 \011 6121111512115
4a
.B
68
2a
(5)
sec
5
N
N •
354230433943
16 6 2 1E
50
70
4912
No OperallOn
AVM-A (1)
5 1-5
X-M
Y_M
A-X
A..... Y
S-X
X..... A
X..... S
V..... A
6
30
EOCT2 co
EC
CO
2 2 CC
CE
CPY
A_M
3
N V • B 0
sa
eMP
5MB[#(0-71] l-M.
7
7
751412170 141'17914 I'
71
31
BO90
0_1
eLV
TYA
5210A]211
~: I ~
CPX
ns
06
0017 11
Branch on V""Q
STX
STY
TAX
TAY
TSX
TXA
3
2C 14131 24] 3 12
Branch on V""l
STA
6
(2)
(2)
(2)
O-.C
0-0
~~~
ATI
OE
(5)(2)
(5)(2)
(2)
(2)
(2)
BVS
AM8(#(O-7)) O_M.
""
691212160141'1651'12
29 2 2 20 4 3 25 3 2
-.(l
CLC
CLD
elf
~
(4)(1)
(II
cr==:::QJ
6
6
2
38
Fa
7a
5E
2
10 14131191413
N
•••••
Z
N
•
Z
11.1 JJ.I ,I:~I ~ 1~ I:~I :1
22 11
2
31 F,I
071 171 27 I 37 1471 57
I 67 177
Z C
Z C
(Restored)
41 ,
N V ••••
Z (3)
I
87 I 97
1"I 61 21 9116121 :: I:I:I,D I 51 ,I" I 5I 3
aOl41'1
8E 4 3 as
86
I A7 I B7
le7
I D7 I E7
o
:r
IF7
961412
-0"
8c43841312
NOTES
1. Add 1 10 N If page boundary IS crossed
2. Add 1 to N II branch occurs to same page
Add 2 to N II branch occurs to different page
3 Carry not == Borrow
4 If In deCimal mode Z nag IS Invalid
accumulator must be checked on zero result.
5. Effects 8-M data field of the specdled zero page address.
o::l
(J)
1
(5)
AA
AB
BA
aA
'98A
•
[Restored)
!: I; I~ I!~I ~ I~ 40
60 6
I
31 E51 3
4
Z
Z
Z C
2
o ...•.
N
N •••••
J 2 11
LEGEND
X
== Index X
V
== Index Y
A
M
M.
MD
M,
=
Accumulator
Memory per eHecbve address
Memory per slack pointer
Selecter zero page memory bJI
Memory 811 7
m
M,
And
== Or
ExcluSIve Or
== Number 01 cycles
== Number of Bytes
=
#
Z
== Memory BI16
== Add
== Sublracl
=
V
:s:
•
n"
a
a
"C
(')
(J)
In
In
...
o
One-Chip Microprocessor
R6518
INSTRUCTION
coce MATRIX
o
o
8
9
A
ORA
ZP
2 3
ASL
ZP
2 5
RMBO
ZP
2 5
PHP
Implied
1 3
ORA
IMM
2 2
ASL
Accum
1 2
ORA
ZP,X
2 4
ASL
ZP, X
2 6
RMBI
ZP
2 5
CLC
Implied
1 2
ORA
ABS, Y
3 4'
AND
ZP
2 3
ROL
ZP
2 5
RMB2
ZP
2 5
PLP
Implied
1 4
AND
IMM
2 2
BMI
AND
Relallve (INO, y)
2 2"
2 5'
AND
ZP,X
2 4
ROL
Zp,X
2 6
RMB3
ZP
2 5
SEC
Implied
1 2
AND
ABS, Y
3 4'
RTI
EOR
Implied (INO,X)
1 6
2 6
EOR
ZP
2 3
LSR
ZP
2 5
RMB4
ZP
2 5
PHA
Implied
1 3
EOR
IMM
2 2
EOR
ZP, X
2 4
LSR
zp,X
2 6
RMB5
ZP
2 5
CLI
Implied
1 2
EOR
ABS, Y
3 4'
AOC
ZP
2 3
ROR
ZP
2 5
RMB6
ZP
2 5
PLA
Implied
1 4
AOC
IMM
2 2
AOC
ZP, X
2 4
ROR
ZP,X
2 6
RMB7
ZP
2 5
SEI
Implied
1 2
AOC
ABS, Y
3 4'
STY
ZP
2 3
STA
ZP
2 3
STX
ZP
2 3
5MBO
ZP
2 5
DEY
Implied
1 2
STY
ZP,X
2 4
STA
ZP, X
2 4
STX
ZP, Y
2 4
5MBI
ZP
2 5
TYA
Implied
1 2
STA
ABS, Y
3 5
TXS
Implied
1 2
LOY
ZP
2 3
LOA
zp
2 3
LOX
ZP
2 3
5MB2
ZP
2 5
TAY
Implied
1 2
LOA
IMM
2 2
TAX
Implied
1 2
LOY
zp,X
2 4
LOA
Zp, X
2 4
LOX
ZP, Y
2 4
5MB3
ZP
2 5
CLV
Implied
1 2
LOA
ABS, Y
3 4'
TSX
Implied
1 2
CPY
ZP
2 3
·CMP
ZP
2 3
DEC
ZP
2 5
5MB4
ZP
2 5
INY
Implied
1 2
CMP
IMM
2 2
OEX
Implied
1 2
CMP
ZP, X
2 4
DEC
ZP,X
2 6
5MB5
ZP
2 5
CLO
Implied
1 2
CMP
ABS, Y
3 4'
SBC
ZP
2 3
INC
ZP
2 5
5MB6
ZP
2 5
INX
Implied
1 2
SBC
IMM
2 2
SBC
ZP, X
2 4
INC
ZP,X
2 6
5MB7
ZP
2 5
SED
Implied
2
SBC
ABS, Y
3 4'
6
9
3
BRK
ORA
Implied (INO,X)
1 7
2 6
BPL
ORA
Relative (INO), Y
2 2"
2 5'
JSR
AND
Absolute (INO,X)
3 6
2 6
3
4
BVC
5
EOR
Relative (INO), Y
2 2"
6
BIT
ZP
2 3
2
5'
RTS
AOC
Implied (INO,X)
1 6
2 6
BVS
AOC
Relative (INO, y)
2 2"
2 5'
STA
(INO,X)
2 6
BCC
9
2
A
B
o
E
F
2"
2
6
LOY
IMM
2 2
LOA
(INO,X)
2 6
BCS
LDA
Relative (INO), Y
2
C
STA
Relative (INO, y)
2"
CPY
IMM
2 2
2
5'
CMP
(INO, Xl
2 6
LOX
IMM
2 2
BNE
CMP
Relalive (INO), Y
2 2"
2 5'
CPX
IMM
2 2
SBC
(INO,X)
2 6
BEQ
sec
CPX
ZP
2 3
Relative (INO), Y
2 2"
2 5'
o
,
4
BRK
Implied
1 7
B
-op Code
-Addressing Mode
-Instruction Bytes; Machine Cycles
C
o
E
F
ORA
ABS
3 4
ASL
ABS
3 6
BBRO
ZP
3 5"
ORA
ASL
ABS, X ABS, X
3 4'
3 7
ROL
BIT
ABS
3 4
Accum
1 2
AND
ABS
3 4
ROL
ABS
3 6
AND
ROL
ABS, X ABS,X
3 7
3 4'
JMP
ABS
3 3
LSR
Accum
1 2
EOR
ABS
3 4
LSR
ABS
3 6
EOR
LSR
ABS, X ABS, X
3 4'
3 7
ROR
JMP
Accum
1 2
Indirect
3 5
AOC
ABS
3 4
ROR
ABS
3 6
AOC
ROR
ABS, X ABS, X
3 4'
3 7
STY
ABS
3 4
TXA
Implied
1 2
STA
ABS
3 4
STX
ABS
3 4
LOA
ABS
3 4
LOY
LOA
ABS, X ABS,X
3 4'
3 4'
CPY
ABS
3 4
CMP
ABS
3 4
BSRI
ZP
3
BBR3
ZP
5"
CPX
ABS
3 4
sec
ABS
3 4
BBR4
ZP
5"
3
BBR5
ZP
5"
3
BBR6
ZP
3
B
C
o
5"
BBR7
ZP
3 5"
BBSO
ZP
3 5"
LOX
ABS
3 4
BBS2
ZP
3 5"
A
LOX
ABS, Y
3 4'
BBS3
ZP
3 5"
B
DEC
ABS
3 6
BBS4
ZP
3
E
C
5"
BBSS
ZP
3
INC
ABS
3 6
SBC
INC
ABS, X ABS, X
3 4'
3 7
A
3
3
CMr
DEC
ABS, X ABS, X
3 4'
3 7
NOP
Implied
1 2
5"
BBR2
ZP
3 5"
BBSI
ZP
3 5"
STA
ABS, X
3 5
LOY
ABS
3 4
o
o
5"
BBSS
ZP
5"
E
BBS7
ZP
5"
F
3
I
3
F
'Add 1 to N if page boundary is crossed.
"Add 1 to N if branch occurs to same page;
add 2 to N if branch occurs to different page.
3-192
One-Chip Microprocessor
R6518
KEY REGISTER SUMMARY
•
7
1::1___..::A'---_ _-,-:'I
7
~17::::::::==~===~.~1
'=71----"-----.='1
15
ACCUMULATOR
MCR
ADDA 0014
•
INDEX REGISTER Y
' -_ _:..:PC:::H=--_ _ _-J,I;-_ _..::P!OcL=--_ _~1 PROGRAM COUNTER
7
•
'=-__
-,:'I
--=:SP_ _ _
I I
INDEX REGISTER X
BUS MODE SELECT
PC
o-
COUNTER A
MODE SELECT
0 INTERVAL TIMER
o-
0 - 1 PULSE GENERATION
1 0 EVENT COUNTER
1 1 PULSE WIDTH MEAS.
0 INTERVAL TIMER
0 - 1 ASVMMETRICPULSEGENERATION
STACK POINTER
7
IN Iv I I BID I I I z I C I PROCESSOR STATUS REG
1 -
0 EVENT COUNTER
1 -
1 RETRIGGERABLE INTERVAL TIMER
PORT B LATCH
(1 = ENABLED)
P
PORT 0 TRJ-S1 ATE
1 = MUX'O BUS
CPU Registers
1 - lMUX'OBUS
Mode Control Register
INlvl
IBIDI
I
Izici
IFR
ADDR 0011
IER
ADDR 0012
LCARRY(C) CD
1 = CARRY SET
0= CARRY CLEAR
~ZERO(Z)CD
1 =ZERO RESULT
0= NON-ZERO RESULT
L
L
L-
PAO POSITIVE
EDGE DETECT
®
INTERRUPT DISABLE (I)
1 =!!!!;l INTERRUPT DISABLED
0= IRQ INTERRUPT ENABLED
DECIMAL MODE (D)
1 = DECIMAL MODE
0= BINARY MODE
0
PA2 NEGATIVE
EDGE DETECT
PA3 NEGATIVE
EDGE DETECT
COUNTER A
UNDERFLOW FLAG
COUNTER B
UNDERFLOW
FLAG
RECEIVER
FLAG
BREAK COMMAND (B) CD
1 = BREAK COMMAND
0= NON-BREAK COMMAND
' - OVERFLOW (0) CD
1 = OVERFLOW SET
0= OVERFLOW CLEAR
'-- NEGATIVE (N) CD
1 = NEGATIVE VALUE
0= POSITIVE VALUE
XMTR
FLAG
NOTES:
CD
o
o
Interrupt Enable and Flag Registers
NOT INITIALIZED BY RES
SET TO LOGIC 1 BY RES
SET TO LOGIC 0 BY RES
Processor Status Register
SCCR
o PARITY DISABLE
1 PARITY ENABLE
0--8 BITS/CHAR
1-7 BITS/CHAR
0--6 BITS/CHAR
1
1-5 BITSCHAR
o
0 XMTR AND RCVR ASYN MODE
o
1 XMTR ASYN RCVR SIR
1
X XMTR SIR RCVR ASYN
o RCVR DISABLE
1 RCVR ENABLE
o XMTR DISABLE
1 XMTR ENABLE
SCSR
o
o
1
RCVR OVER-RUN
PARITV ERROR
FRAME ERROR
WAKE-UP
END OF TRANSMISSION
XMTR DATA REG EMPTY
XMTR UNDER-RUN
Serial Communications Status Register
Serial Communications Control Register
3-193
One-Chip Microprocessor
R6518
ADDRESS ASSIGNMENTS
AND MEMORY MAPS
110 AND INTERNAL REGISTER ADDRESS
ADDRESS
(HEX)
001F
1E
WRITE
READ
--
-
1C
Lower Counter B
Upper Counter B
Lower Counter B, CLR Flag
1B
1A
19
18
Lower Counter A
Upper Counter A
Lower Counter A, CLR Flag
Upper Latch A, Cntr A +--Latch A, CLR Flag
Upper Latch A
Lower Latch A
17
16
15
14
Serial
Serial
Serial
Mode
Serial
Serial
Serial
Mode
10
13
12
11
0010
OF
OE
00
OC
OB
OA
09
08
07
06
05
04
03
02
01
0000
Upper Latch B, Cntr B +--Latch B) CLR Flag
Upper Latch B, Latch C +--Latch B
Lower Latch B.
--
--
Receiver Data Register
Comm. Status Register
Comm. Control Register
Control Register
--
Transmitter Data Register
Comm. Status Reg. Bits 4 & 5 only
Comm. Control Register
Control Register
--
Interrupt Enable Register
Interrupt Flag Register
Read FF
Interrupt Enable Register
--
Clear Int Flag (Bits 0-3 only, Write O's only)
--
----
--
-----
----
-----
---------
--
Port B
Port A
Port B
Port A
3-194
R6518
One-Chip Microprocessor
MULTIPLEXED MODE MEMORY MAP
3FFF
FE
FD
FC
FB
FA
F9
Fa
3FF7
HIGH BYTE
LOW BYTE
}} IRQ INSTRUCTION
HIGH BYTE
LOW BYTE
RES INSTRUCTION
JMP
JMP
}
HIGH BYTE
LOW BYTE
JMP
NMI INSTRUCTION
EMS
VALID
001F
I
EXTERNAL
MEMORY
/
INTERNAL
REGISTERS
/
/
/
/
0100
OOFF
0040
003F
0020
001F
/
/
INTERNAL RAM
192 BYTES
RESERVED
0010
OOOF
/
/
RESERVED
II
I/O & REGISTERS
-
0000
3-195
I/O PORTS A, B
0002
0001
0000
One-Chip Microprocessor
R6518
ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS*
Parameter
Symbol
Value
Unit
Vee & VRR
-0.3 to + 7.0
Vdc
Input Voltage
V IN
-0.3 to + 7.0
Vdc
Operating Temperature
Commercial
TA
Supply Voltage
Storage Temperature
o to
TSTG
+70
-55 to +150
• NOTE: Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in other sections of this document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
°C
°C
DC CHARACTERISTICS
(Vee = 5V ±5%, VRR = Vee, Vss
0, TA = 0 to lOoe except as noted)
Parameter
Symbol
Min
Typ.
Max.
Unit
Power Dissipation (Outputs High)
Commercial @ O°C
Po
-
1000
mW
RAM Standby Voltage (Retention Mode)
VRR
3.0
-
Vee
Vdc
RAM Standby Current (Retention Mode)
Commercial @ 25°C
IRA
-
4
-
-
Vee
mAde
Input High Voltage
VIH
+2.0
Input High Voltage (XTLI)
VIH
+4.0
Input Low Voltage
V IL
-0.3
Input Leakage Current (RES, NMI)
Vin = 0 to 5.0 Vdc
liN
Input Low Current PA, PB, and Address/Data
(VIL = 0.4 Vdc)
IlL
-
Output High Voltage (Except XTLO)
(I LOAD = 100 pAdc)
VOH
Output Low Voltage
(I LOAD = 1.6 mAde)
VOL
Input Capacitance
(Vin = OV, TA = 25°C, , = 1.0 MHz)
PA, PB
XTLI, XTLO
Cin
Vde
Vee
Vde
+0.8
Vde
±10.0
pAdc
-1.0
-1.6
mAde
+2.4
-
Vee
Vdc
-
-
+0.4
Vdc
pF
-
-
10
50
I/O Port Pull-Up Resistance AO-A3, 00-07; EMS, R!W
PAO-PA7, PBO-PB7
RL
3.0
6.0
11.5
K!I
Output Capacitance
VIN = OV, TA = 25°C, , = 1.0 MHz
CQUT
-
-
10
pF
Note: Negative sign indicates outward current flow, positive indicates inward flow.
3-196
R6518
One-Chip Microprocessor
TYPICAL MEMORY HOOKUP
~c~;;:lt:C~2~~~
~
:"r
i~
8iiSSiSiS3o
rl"1
§!l§iH!H~~
·~::::!:!::n:;;
~1~
2:
I Ii
18
3·197
IS
One-Chip Microprocessor
R6518
TIMING REQUIREMENTS AND CHARACTERISTICS
CLOCK TIMING
GENERAL NOTES
1 MHz
1. Vee = 5V ±5%, DOC :5 TA :5 7DoC
Symbol
2. A valid Vec - RES sequence is required before proper
operation is achieved.
XTLI
Max
Min
Max
Unit
1
10
0.5
10
pS
250
±10
-
ns
Cycle Time
TpwX1
XTLI Input Clock
Pulse Width
(XTLO = VSS)
Tpwa2
Output Clock Pulse T pWX1 TpWX1 TpWX1 T pWX1
Width at Minimum
+0
+0
-25
-20
Tcyc
ns
4. All time units are nanoseconds, unless otherwise specified.
I-
-
500
±25
TA, TF
Output Clock Rise
Fall Time
-
25
-
15
ns
T'A, T'F
Input Clock Rise,
Fall Time
-
10
-
10
ns
•
-I
Tcve
T,•
1.SV
TPWX1
eXTLO = V.S>
of
_ _ T,
3-198
2 MHz
Min
TCyc
3. All liming reference levels are D.8V and 2.DV, unless otherwise specified.
5. All capacitive loading is 130 pF maximum, except for Ports A
and B which are 50 pF maximum.
Parameter
T pW02
•
One-Chip Microprocessor
R6518
ADDRESSIDATA TIMING
1 MHz
Symbol
Parameter
2 MHz
Min
Max
Min
Max
Units
225
140
ns
140
ns
225
-
140
ns
ns
T pCRS
RIW Setup Time
TpcAS
Address Setup Time
T pBAS
Address Setup Time
-
T pBsu
Data Setup Time
50
-
35
TpBHR
Data Read Hold Time
10
-
10
TpBHW
Data Write Hold Time
30
-
30
-
TpBDD
Data Output Delay
-
175
-
150
ns
TpCHA
Address Hold Time
30
-
30
-
ns
TpBHA
Address Hold Time
10
100
10
80
ns
TpCHR
R/W Hold Time
30
30
EMS Hold Time
10
T pCVD(l)
Address to EMS Delay Time
30
-
30
-
ns
TpCHV
-
Tpcvp
EMS Stabilization Time
30
-
30
-
ns
T Esu
EMS Setup Time
-
350
-
210
ns
225
10
Note 1: Values assume Address and EMS have the same capacitive load.
READ
r-------------__ I
3-199
WRITE
r--------------.
ns
ns
ns
ns
One-Chip Microprocessor
R6518
1/0, EDGE DETECT, COUNTERS, AND SERIAL 1/0 TIMING
2 MHz
I MHz
Symbol
Parameter
Min
Max
Min
Max
-
-
500
1000
-
-
500
1000
200
-
200
-
75
-
75
-
TCYC
-
-
TCYC
Internal Write to Peripheral Data Valid
TpDVP)
TCMOS(l)
PA, PB, TTL
PA, PB, CMOS
Peripheral Data Setup Time
T pDSU
PA, PB
Peripheral Data Hold Time
TpHR
T EPW
PA, PB
PAO-PA3 Edge Detect Pulse Width
TCYC
Counters A and B
Tcpw
T CD(l)
PA4, PA5 Input Pulse Width
PA4, PA5 Output Delay
TCYC
-
500
-
500
Port B Latch Mode
T pBLW
T pLSU
TpBLH
PAO Strobe Pulse Width
PB Data Setup Time
PB Data Hold Time
TCYC
175
30
-
TCYC
ISO
30
-
-
Serial 1/0
TpDW(l)
TCMOS(l)
Tcpw
T pDW(l)
TCMOS(l)
PAS
PAS
PA4
PA4
PA4
XMTR
XMTR
RCVR
XMTR
XMTR
-
TTL
CMOS
SIR Clock Width
Clock-SIR Mode (TTL)
Clock-SIR Mode (CMOS)
4 TCYC
-
Notes: 1. Maximum load capacitance: 50 pF; passive pull-up required.
2. All times are in nanoseconds.
3-200
500
1000
500
1000
-
4 TCYC
-
500
1000
-
500
1000
One-Chip Microprocessor
R6518
110, EDGE DETECT, COUNTER, AND SERIAL 1/0 TIMING
1.SV
/
TPDSU
OIl
PAO-PA7
PBO-PB7
.
Tcvc
_I'"
..
~
I
I
X
)!
T~
EDGE DETE CTS
(PAO-PA3)
~K
).
TEPW
CNTRINPU T
(PA4, PAS)
1s-
1.SVi
1•SV
1.SV}
'"
TCPW
TCD
CNTR OUTP UT
(PA4, PAS)
..
TCPW
2.4V
O.4V
PAO-PA7
PBO-PB7
PB
(LATCH MOD_E_)_ _
PAO
STROBE
1.SV
1.SV
~I
, . . - - - - - - TpBLW - - - - - - -..
3-201
_
TpBLH
One-Chip Microprocessor
R6518
PACKAGE DIMENSIONS
MILLIMETERS
40·PIN PLASTIC DIP
INCHES
DIM
MIN
MAX
MIN
A
51.28
52.32
2.040
2.060
B
1372
14.22
0.540
0.560
C
3.55
5.08
0140
0200
D
0.36
0.51
0.014
0020
F
1.02
1.52
0.040
G
2.54
H
1.65
J
0.20
K
3.30
esc
I
L
15.24
M
7"
N
0.51
MAX
0.060
0.100
esc
2.16
0.065
0.085
030
0.008
0012
4.32
0.130 ~ 0.170
ase
10"
102
0.600 BSC
10"
7"
I 0.040
0.020
44-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
SEATING PLANE
INDE~R~g~
CORNE~kr;D~1
1Eir
illd
61
I ~2
6
?
39-
CHAM.J x 45°
SECTION A·A
TYP FOR BOTH AXIS (EXCEPT .FOR BEVELED EDGE)
11 PINS
PER SIDE
EOUALLY
SPACES
MAX
4.39
0.163
0173
A1
137
1.47
0054
0058
A2
2.31
246
0091
0097
EJECTOR PIN MARKS
4 PLCS BOTTOM OF
PACKAGE ONLY
(TYPICAL)
BOTTOM VIEW
3·202
0457 TVP
0018 TVP
0
1745
1760
0687
01
1646
16.56
0.648
0652
02
1262
1278
0497
I 0503
15.75 REF
esc
0693
0.620 REF
esc
e
1 27
h
115 TVP
0045 TVP
J
0.25 TVP
0010 TVP
.
SIDE VIEW
TOP VIEW
CHAM.
h x 45°
3 PLCS
MIN
414
03
2.
17
MIN
INCHES
MAX
A
b
PIN 1
INDICATOR
~
MILLIMETERS
DIM
0050
45° TYP
45° TVP
R
089 TVP
0.035 TYP
R1
025 TVP
0010 TVP
R65F11 • R65F12
·'1'
Rockwell
R65F11 and R65F12
FORTH Based Microcomputers
SECTION 1
INTRODUCTION
1.1 FEATURES
• Aexible clock circuitry
-2-MHz or l-MHz internal operation
-Internal clock with external XTAL at two times intemal
frequency
-External clock input divided by one or two
• FORTH kemel in ROM
• Enhanced 6502 CPU
-Four new bn manipulation instructions:
Set Memory Bit (SMB)
Reset Memory Bit (RMB)
Branch on Bit Set (BBS)
Branch on Bit Reset (BBR)
-Decimal and binary arithmetic modes
( -13 addressing modes
.-True indexing
• 1 ,..s minimum instruction execution time @ 2 MHz
o NMOS silicon gate, depletion load technology
•
•
•
•
• 192-byte static RAM
• 16 bidirectional, TTL-compatible I/O lines (two ports, R65Fll )
or 40 bidirectional, TTL-compatible I/O lines (five ports,
R65F12)
Single +5V power supply
12 mW standby power for 32 bytes of the 192-byte RAM
4O-pin DIP (R65Fll)
64-pin QUIP (R65F12) has three additional a-bit I/O ports to
provide a total of 40 I/O lines.
1.2 SUMMARY
The Rockwell R65Fll and R65F12 are complete, high-performance. a-bit NMOS single Chip microcomputers, and are compatible with all members of the R6500 family.
• One a-bit port with programmable latched input
• Two 16-bit programmable counter/timers, wnh latches
-Pulse width measurement
-Asymmetrical pulse generation
-Pulse generation
-Interval timer
-Event counter
-Retriggerable interval timer
The kernel of the high level Rockwell Single Chip RSC-FORTH
language is contained in the preprogrammed ROM of the R65Fll
and R65F12. RSC-FORTH is based on the popular fig-FORTH
model wnh extensions. All of the run time functions of RSCFORTH are contained in the ROM, including 16- and 32-bit
mathematical, logical and stack manipulation, plus memory and
input/output operators. The RSC-FORTH Operating System
allows an external user program written in RSC-FORTH or
Assembly Language to be executed from external EPROM, or
development of such a program under the control of the R65FRl
RSC-FORTH Development ROM. Other development ROM's
can also be accommodated.
• Serial port
-Full-duplex asynchronous operation mode
-Selectable 5- to a-bit characters
-Wake-up feature
-Synchronous shift register mode
-Standard programmable bit rates, programmable up to
62.5K bitS/sec
• Ten interrupts
-Four edge-sensitive lines; two positive, two negative
-Reset
-Non-maskable
-Two counter
-Serial data received
-Serial data transmitted
• Expandable to 16K bytes of external memory
The R65Fll and R65F12 consist of an enhanced 6502 CPU,
an internal clock oscillator, 192 bytes of Random Access Memory
(RAM) and versatile interface circuitry. The interface circuitry
includes two 16-bit programmable timer/counters, 16 bidirectional inpul/outputlines (including four edge-sensnive lines and
input latching on one a-bit port), a full-duplex serial I/O channel,
ten interrupts and bus expandabilily.
The innovative architecture and the demonstrated high performance of the R6502 CPU, as well as instruction simplicity,
resuils in system cost-effectiveness and a wide range of
Document No. 29651 N49
Product Description
3-203
Order No. 2146
Rev. 4, June 1987
FORTH Based Microcomputers
R65F11 • R65F12
computational power. These features in combination with the
FORTH high level operating system make the R65F11 and
R65F12 ideal for microcomputer applications.
(Order Number 201). A description of the instruction capabilites
of the R6502 CPU is contained in the R6500 Microcomputer
System Programming Manual (Order Number 202).
For systems requiring additional 1/0 ports, the 64-pin QUIP
version, the R65F12, provides three additional 8-bit ports.
1_3 ORDERING INFORMATION
A complete RSC-FORTH development system can be created wfth three MOS parts: the R65F11, one RAM chip and
the R65FR1 Development ROM.
This product description is for the reader familiar with the
R6502 CPU hardware and programming capabilities. A
detailed description of the R6502 CPU hardware is included
in the R6500 Microcomputer System Hardware Manual
Part No.
Description
R65F11P
R65F11AP
R65F12Q
R65F12AQ
R65FR1P
R65FR2P
R65FK2P
4()..Pin FORTH Based Microcomputer at 1 MHz
40·Pin FORTH Based Microcomputer at 2 MHz
64-Pin FORTH Based Microcomputer at 1 MHz
64-Pin FORTH Based Microcomputer at 2 MHz
FORTH Development ROM for R65F11 or R65F12
FORTH Development ROM for expanded capacity
FORTH Kernel ROM for expanded capacity
development
FORTH Development ROM for R6501Q
FORTH Kernel ROM for R6501Q
R65FR3P
R65FK3P
Description
Order No.
2148
FORTH Based Microcomputer User's Manual-
Note:
-Included with R65FR1.
3-204
R65F11 • R65F12
FORTH Based Microcomputers
SECTION 2
INTERFACE REQUIREMENTS
This section describes the interface requirements for the
R65Fll and R65F12 single chip microcomputers. Figure
2-1 is the Interface Diagram for the R65Fll and R65F12.
Figure 2-2 shows the pin out configuration and Table 2-1
describes the function of each pin of the R65Fll and R65F12.
Figure 3-1 is a detailed block diagram.
'-
"'"""'
'.
Table 2-1.
Signal
Name
R65F11 and R65F12 Pin Descriptions
Pin No.
R65Fll
Pin No.
R65F12
Vee
21
50
Main power supply +5V
V RR
39
12
Separate power pin for RAM.
In the event that Vee power
is lost, this power retains
RAM data.
Vss
40
11
Signal and power ground COY)
XTLI
2
10
Crystal or clock input for internal clock oscillator. Also
allows input of XI clock signal if XTLO is connected to
Vss. or X2 or X4 clock if
XTLO is floated.
XTLO
1
9
Crystal output from internal
clock oscillator.
20
41
The Reset input is used to
in~ialize the R65Fll. This
signal must not trans~ion from
low to high for at least eight
cycles after V cc reaches operating range and the internal oscillator has stabilized.
3
13
Clock signal output at internal frequency.
22
51
A negative going edge on the
Non-Maskable Interrupt signal requests that a nonmaskable interrupt be generated w~hin the CPU.
PAO-PA7
PBO-PB7
30-23
38-31
64-57
B-1
Two B-bit ports used for eHher
input/output. Each line of
Ports A and B Consist of an
active transistor to V ss and
a passive pull-up to V cc.
PCO-Pe7
AO-A3
A12,RiW
AI3.EMS
4-11
25-32
PDO-PD7
A4-All
DO-D7
19-12
40-33
Port C has an active pull-up
transistor. Port D has active
pull-up and pull-down Itanslstors. Ports C and D lines
form the external muHiplexed
address and data bus to allow external memory addressing.
PM-PA1fPAO,PAI
POSITIVE PA2 PA3
NEGATlVEEOGECETECTS}
PBO-PB7(lJITCtED'NPUTSj
DS(PAOI(INPUT DATA STROBEl'
RES
M-A3,A,2,
RIW. A13 lD! IPea·pcr}
,...,...n
"'''"''U AODI'\'OC·07 OATA BUS
_2
SO/PAll)"
SlU· ...'I·
NMI
Figure 2-1. R65F11 and R65F12 Interface Diagram
PEO-PE7
PFO-PF7
PGO-PG4
PG5-PG7
3-205
Description
49-42
24-17
52-56.
14-16
On the R65FI2, Port E may
be used for output only. Ports
F and G are similar to Ports
A and B In construction and
may be used for inputs or
outputs.
R65F11 • R65F12
FORTH Based Microcomputers
~OT
OR NOTCH
TO lOCATE
PIHNO 1
015S.AX
(3t13~._._J_ _-.j
(025"101)
InterflceDilgram
I
T
L
,'861 "II,
,u
20SOMAX
(51.30MM)
00 MMj
tt EOUAL SPACES
0100 ... TOl MOHeu..
(254MM)
•,
'"
R65F11 Pin Out Designation
,,15M") 0055
".DIMM} DeMO
40 PIN DIP
R65F11 Dimensional Outline
pat
PBS
::;
PAO
PAl
PBS
PA2
PB2
PSI
paD
PAS
PA'
Plot
=~
:~~
~
ViS
VRR
PG2
PO.
POI
PGt
PF7
PF6
Vee
PEO
PEl
PE2
~
~~
PF3
:~~
'..:r,
~
~
~~
PES
:~
if
.
".
==
~ ="1.!!-_ _ _---!!!F= ¥.rr::;-
R65F12 Pin Out Designation
R65F12 Dimensional Outline
Figure 2-2.
Pin Out Configuration
3-206
r
1045 ....'
001'
R65F11 • R65F12
FORTH Based Microcomputers
SECTION 3
SYSTEM ARCHITECTURE
This section provides a functional description of the R65F11
and R65F12. Functionally the R65F11 consists of a CPU,
RAM memory, two 8-bit parallel VO ports (five in the 64-pin
R65F12), a serial VO port, dual counter/latch circuits, a mode
control register, an interrupt flag/enable dual register circuit,
and an internal Operating System. The kernel of FORTH in
ROM complements the system hardware. A block diagram
of the system is shown in Figure 3-1.
The stack can be envisioned as a deck of cards which may
only be accessed from the top. The address of a memory
location is stored (or "pushed") onto the stack. Each time
data are to be pushed onto the stack, the Stack Pointer is
placed on the Address Bus, data are written into the memory
location addressed by the Stack Poi nter, and the Stack
Pointer is decremented by 1. Each time data are read (or
"pulled") from the stack, the Stack Pointer is incremented by
1 . The Stack Pointer is then placed on the Address Bus, and
data are read from the memory location addressed by the
Pointer.
NOTE
Throughout this document, unless specified
otherwise, all memory or register address locations are specified in hexadecimal notation.
The stack is located on zero page, i.e., memory locations
00FF-0040. After reset, which leaves the Stack Pointer
indeterminate, normal usage calls for its initialization at OOFF.
3.1 CPU LOGIC
3.1.4 Processor Status Register
The R65F11 internal CPU is a standard 6502 configuration
w~h an 8-bit Accumulator register, two 8-b~ Index Registers
(X and Y); an 8-bit Stack Pointer register, and ALU, a 16-bit
Program Counter, and standard instruction register/decode
and internal timing control logic.
The 8-bit Processor Status Register contains seven status
flags. Some of these flags are controlled by the user program; others may be controlled both by the user's program
and the CPU. The R6500 instruction set contains a number
of conditional branch instructions which are designed to allow
testing of these flags. See Appendix B for details.
3.1.1 Accumulator
3,1,5 Program Counter
The accumulator is a general purpose 8-bit register that
stores the results of most arithmetic and logic operations. In
addition, the accumulator usually contains one of the two
data words used in these operations.
The 16-bit Program Counter provides the addresses that are
used to step the processor through sequential instructions
in a program. Each time the processor fetches an instruction
from program memory, the lower (least significant) byte of
the Program Counter (PCL) is placed on the low-order bits
of the Address Bus and the higher (most significant) byte of
the Program Counter (PCH) is placed on the high-order 8
bits of the Address Bus. The Counter is incremented each
time an instruction or data is fetched from program memory.
3.1.2 Index Registers
There are two 8-bit index registers, X and Y. Each index register can be used as a base to modify the address data program counter and thus obtain a new address-the sum of
the program counter contents and the index register contents.
When executing an instruction which specifies indirect
addressing, the CPU fetches the op code and the address,
and modifies the address from memory by adding the index
register to it prior to loading or storing the value of memory.
3.1.6 Arithmetic And Logic Unit (ALU)
Each bit of the ALU has two inputs. These inputs can be tied
to various intemal buses or to a logic zero; the ALU then
generates the function (AND, OR, SUM, and so on) using
the data on the two inputs.
Indexing greatly simplifies many types of programs, especially those using data tables.
3.1.7 Instruction Register and Instruction Decode
3.1.3 Stack Pointer
Instructions are fetched from ROM or RAM and gated onto
the Internal Data Bus. These instructions are latched into the
Instruction Register then decoded along with timing and
interrupt signals to generate control signals for the various
registers.
The Stack Pointer is an 8-bit register. It is automatically
incremented and decremented under control of the microprocessor to perform stack manipulation in response to either
user instructions, an internal IRQ interrupt, or the exterrial
interrupt line NMI. The Stack POinter must be initialized by
the user program.
The stack allows simple implementation of multiple level
interrupts, subroutine nesting and Simplification of many types
of data manipulation. The JSR, BRK, RTI and RTS Instructions use the stack and Stack POinter.
3-207
:::D
m
."
.....
....
•
~
."
....
N
~
al
~
~
~
::::t
tD
II)
t
CAIP".)
50 (PAS)
1
51 (P"'1)
I
3:
c;"
Figure 3-1. Detailed Block Diagram
(3
o
n
3
c::
;..,.
"t:I
til
FORTH Based Microcomputers
R65F11 • R65F12
3.1.8 Timing Control
For the RAM to retain data upon loss of V cc , V RR must be
supplied within operating range and RES must be driven low
at least~t ~2 clock pulses before Vee falls out of operating
range. RES must then be held low while Vee is out of operating range and until at least eight ~2 clock cycles after Vee
is again w~hin operating range and the internal ~2 oscillator
is stabilized. V RR must remain within Vcc operating range
during normal operation. When Vcc is out of operating range,
V RR must remain within the V RR retention range in order to
retain data. Figure 3-2 shows typical waveforms.
The Timing Control Logic keeps track of the specific instruction cycle being executed. This logic is set to TO each time
an instruction fetch is executed and is advanced at the
beginning of each Phase One clock pulse for as many cycles
as are required to complete the instruction. Each data transfer
which takes place between the registers is caused by
decoding the contents of both the instruction register and
timing control unit.
3.1.9 Interrupt Logic
RAM OPERATING MODE
Interrupt logic controls the sequencing of three interrupts;
RES. NMI and IRQ. IRQ is generated by anyone of eight
cond~ions: 2 Counter Overflows, 2 Positive Edge Detects,
2 Negative Edge Detects. and 2 Serial Port Conditions.
~
3.2 CPU INSTRUCTION SET
The machine code instruction set of the R65F11 and R65F12
microcomputers are based on the popular R6500 microprocessor set. They contain all the instructions in the standard
R6502 set. with the addition of the four new bit instructions
added to the R6511 processor family. Refer to Appendix A
for the Op Code mnemonics addressing matrix for details on
these instructions.
I
RAM RETENTtON MODE
I
i} :
I
r::~:~
-l1-0
1-0
TRL0-1
I-
1 INITIAL APPLICATION OF Vee AND VRR •
2 LOSS OF Vcc , RAM ON STANDBY POWER.
3 REAPPLICATION OF Vee'
4 >8112 CLOCK PULSES AFTER OSCILLATOR STABILIZATION.
5 >8 112 CLOCK PULSES.
Figure 3-2. Data Retention Timing
3.3 READ-ONLY-MEMORY (ROM)
The ROM consists of pre programmed memory with an
address space from F400 to FFFF. It contains the run time
kernel of the high level language Rockwell Single Chip
FORTH. There are 133 included functions stored in the
ROM. Codes are in the format of a two byte code field, which
identifies the interpreter assigned to execute that word, followed by a variable length Parameter Field. which contains
the instructions and data used by that interpreter according
to the programmed intention of that definition. See Appendix
D for a complete list of the names of all included words. All
words needed for support of the run time operation of dedicated applications programs are included. The RSC-FORTH
Operating System is also part of the ROM code and is
entered upon Reset. This Operating System allow the R65F11
and R65F12 to auto start a user program written in either
RSC-FORTH or Assembly Language or enter a Development ROM if one is present. If no auto start program is found,
an attempt will be made to boot an operating program from
floppy disk.
3.5 CLOCK OSCillATOR
A reference frequency can be generated with the on-chip
oscillator using an external crystal. The oscillator reference
frequency passes through an internal countdown network
(divide by 2) to obtain the internal operating frequency.
The on-chip oscillator is designed for a parallel resonant
crystal connected between XTLI and XTLO pins. The equivalent oscillator circuit is shown in Figure 3-3a.
A parallel resonant crystal is specified by its load capacitance
and series resonant resistance. For proper oscillator operation, the load capacitance (Cw, series resistance (R,) and
the crystal resonant frequency (F) must meet the following
two relations:
(C + 27)
= 2CL
or
R, :;; R,max = 2 X 106
C
= 2CL
-
27 pF
F in MHz; C L in pF
(FCd2
To select a parallel resonant crystal for the oscillator, first
select the load capacitance from a Crystal Manufacturer's
catalog. Next, calculate R,max based on F and CL• The
selected crystal must have a Rs less than the R,max,
3.4 RANDOM ACCESS MEMORY (RAM)
The RAM consists of 192 bytes of read/write memory with
an assigned page zero address of 0040 through OOFF. The
R65F11 and R65F12 provide a separate power pin (V RR)
which may be used for standby power for 32 bytes located
at 0040-005F. In the event of the loss of Vcc power, the
lowest 32 bytes of RAM data will be retained if standby power
is supplied to the V RR pin. If the RAM data retention is not
required then V RR must be connected to Vee. During operation V RR must be at the Vee level.
For example, if C L = 22 pF for a 4 MHz parallel resonant
crystal, then
C = (2 x 22) -27 = 17 pF
(use standard value, 18 pF)
The series resistance of the crystal must be less than
R,max =
3-209
2x106 = 258 ohms
(4 X 22)2
FORTH Based Microcomputers
R65F11 • R65F12
Internal timing can also be controlled by driving the XTU pin
with an external frequency source. Figure 3-3b shows typical connections. If XTLO is left floating, the external source
is divided by the internal countdown network. However, if
XTLO is tied to Vss, the internal coundown network is
bypassed casuing the chip to operate at the freqency of the
external source.
R65F11 OR R65F12
XTLI
112
MASTER
INVERTER USED
r-- --, WHEN SLAVE IS
I
TO OPERATE
I
IL__
lOUT
--' OF PHASE WITH
MASTER
~
The R6SF11 and R6SF12 operate in the CLOCK MASTER
mode. In this mode a frequence source (crystal or external
source) must be applied to the XTU and XTLO pins.
I
R6500/11, ETC.
XTLI
SLAVE
02 is a buffered output signal which closely approximates the
internal timing. When a common external source is used to
drive multiple devices the internal timing between devices
as well as their 02 outputs will be skewed in time. If skewing
represents a system problem it can be avoided by the
Master/Slave connection and options shown in Figure 3-4.
C 6'~·~
(tNPUT CLOCK)
Figure 3-4. Master/Slave Connections
C±5%
3.6 MODE CONTROL REGISTER (MCR)
The Mode Control Register contains bits for the multifunction I/O ports and mode select bits for Counter A and
Counter B. Its setting, along with the setting of the Serial Communications Control Register (SCCR), determines the basic
configuration of the R6SF11 and R6SF12 in any application.
The Model Control Register bit assignment is shown in Figure 3-S. MCR Bits 7, 6, S must remain 1's in order for external memory referencing to be enabled.
27 pF
XTLI
1 d~""
::r XTAL
-=-
112
XTLO
The R6SF11 and R6SF12 is operated in the CLOCK MASTER
MODE. A second processor could be operated in the CLOCK
SLAVE MODE. Mask options in the SLAVE unit convert the
02 signal into a clock input pin which is tightly coupled to the
internal timing generator. As a result, the internal timing of
the MASTER and SLAVE units are synchronized with minimum skew. If the 02 signal to the SLAVE unit is inverted, the
MASTER and SLAVE UNITS WILL OPERATE OUT OF
PHASE. This approach allows the two devices to share external memory using cycle stealing techniques.
C±5%
XTLO L
27 pF
Addr 0014
ounter A
Counter B
-=
"."'~' 'M-'."""
=
0-
0 Interval Timer
0 - 1 Puis. Generation
•_
0 Event Counter
ao_
0 Inlerval Tlm.r
1 Asymmetnc Puis. Generation
1_
1_
0 Event Counte,
1 Retrtga-rabla Interval Time,
Port B Latch
1'~E_'od)
,ParlDT,.....
1 _ Mux'd Bus
R65F11
XTLO
Mode Select
. _ 1 Pulse Width Meas.
Bus Mode Select
A.CRYSTALINPUT
fEXT
I
Mode Select
1\
NC
(OUTPUT CLOCK)
2X f'NT
• _
1 Mux'd Bus
Figure 3-5. Mode Control Register
..
M",~'
"" _ , ."'.'"
R65F11
XTLO f EXT
= f'NT
The use of Counter A Mode Select is shown in Section 6.1.
Vss -:
The use of Counter B Mode Select is shown in Section 6.2.
B.CLOCKINPUTS
Figure 3-3. Clock Oscillator Input Options
The use of Port B Latch Enable is shown in Section 4.4.
3-210
FORTH Based Microcomputers
R65F11 • R65F12
3.7 INTERRUPT FLAG REGISTER (IFR)
AND INTERRUPT ENABLE
REGISTER (IER)
IER
An IRQ interrupt request can be initiated by any or all of eight
possible sources. These sources are all capable of being
enabled or disabled by the use of the appropriate interrupt
enabled bits in the Interrupt Enable Register (IER). Multiple
simultaneous interrupts will cause the IRQ interrupt request
to remain active until all interrupting conditions have been
serviced and cleared.
Addr 0012
IFR
Add, 0011
PAD Po.lliv.
Edge Oetect
PA 1 Poeiliv.
Edge Detect
PAZ Negotl.e
Edge Detect
PA3 Negetl.e
EdgeDetact
The Interrupt Flag Register contains the information that
or counter needs attention. The contents
indicates which
of the Interrupt Flag Register may be examined at any time
by reading at address: 0011. Edge detect IFR bits may be
cleared in low level code by executing a RMB instruction at
address location 0010. The RMB X, (0010) instruction reads
FF, modifies bit X to a "0", and writes the modified value at
address location 0011. In this way IFR bits set to a "1" alter
the read cycle of a Read-Modily-Write instruction (such as
RMB) are protected from being cleared. A logic "1" is ignored
when writing to edge detect IFR bits.
va
eou_A
UndelftowFIeg
eou_B
Underflow Fl.
Receiver
Flag
XMTR
Rag
Figure 3-6. Interrupt Enable and Flag Registers
Each IFR bit has a corresponding bit in the Interrupt Enable
Register which can be set to a "1" by writing a "1" in the
respective bit posnion at location 0012. Individual IER bits
may be cleared by writing a "0" in the respective bit posnion,
or by RES. If set to a "1", an IRQ will be generated when the
corresponding IFR bit becomes true. The Interrupt Flag Register and Interrupt Enable Register bit assignments are shown
in Figure 3-6 and the functions of each bit are explained in
Table 3-1.
Table 3-1. Interrupt Flag Register Bit Codes
BII
Code
Function
IFRO:
PAD Positive Edge Detect Flag-Set to a "1" when a positive going edge is detected on PAD.
Cleared by RMB 0 (0010) instruction or by RES.
IFR 1:
PAl Positive Edge Detect Flag-Set to a 1 when a positive going edge is detected on PAl.
Cleared by RMB 1 (0010) instruction or by RES.
IFR2:
PA2 Negative Edge Detect Flag-Set to a 1 when a negative going edge is detected on PA2.
Cleared by RMB 2 (0010) instruction or by RES.
IFR 3:
PA3 Negative Edge Detect Flag-Set to 1 when a negative going edge is detected on PA3.
Cleared by RMB 3 (0010) instruction or by RES.
IFR 4:
Counter A Underflow Flag-Set to a 1 when Counter A underflow occurs. Cleared by reading
the Lower Counter A at location 001B, by writing to address location 001A, or by RES.
IFR 5:
Counter B Underflow Flag-Set to a 1 when Counter B underflow occurs. Cleared by reading
the Lower Counter B at location ODIC, by writing to address location ODIE, or by RES.
IFR 6:
Receiver Interrupt Flag-Set to a 1 when any of the Serial Communication Status Register bits
o through 3 is set to a 1. Cleared when the Receiver Status bils (SCSR 0-3) are cleared or by
RES.
IFR 7:
Transmitter Interrupt Flag-Set to a 1 when SCSR 6 is set to a 1 while SCSR 5 is a 0 or SCSR
7 is sello a 1. Cleared when the Transmitter Status bits (SCSR 6 & 7) are cleared or by RES.
3-211
R65F11. R65F12
FORTH Based Microcomputers
3.8 OPERATING SYSTEM
Whether a warm or cold reset, the memory map is then
searched at every 1K byte boundary starting at location 0400
Hex. The first two bytes at each boundary are checked
against an ASSA Hex bit pattern. This pattern indicates that
an auto start program is installed. The next two bytes are
assumed to point to the Parameter Field of the high level
RSC-FORTH word to be executed upon reset. This may be
the main function of a user defined program or the start up
routine of a Development ROM. Figure 3-7 details proper
alignment.
The system startup function, COLD, is executed upon Reset.
COLD, a high level FORTH word, forms the basis of the RSC
Operating System. Upon reset this function innializes the
R6SF11 or R6SF12 registers to establish the external 16K
byte memory map and disable all interrupt sources. It also
sets up the serial channel for 1200 baud (assuming a 1 MHz
internal clock) asynchronous transmission (seven bits, parity
disabled). The intemal FORTH structure 'W' is prepared for
use and the low level input/output vectors are forced to point
to the system serial channel routines. The FORTH User Area
Pointer, UP, is assigned the value 0300 Hex.
If no auto start ROM is found, the Operating System turns
control over to a program that issues a "NO ROM" message
to the systems terminal via the serial channel and attempts
to boot a program from disk. A floppy disk controller compatible with the WD1793 type, is assumed to be pre~ent at
address 01 00 Hex. The first half of Track 0 Sector 1 is loaded
from a double density boot diskette into RAM starting at
address OOSF. When successfully loaded execution will be
turned over to this boot program.
A test is made of the variable CLD/WRM in memory location
030E. If this contains a value other than ASSA Hex a cold
reset is assumed. In this case, the low level IRQ vector,
IRQVEC; the low level NMI Vector, NMIVEC, and the high
level interrupt vector, INTVEC, are all forced to point to the
system reset routine. This prevents an unintentionally generated interrupt from crashing the system. System variables
TIB, RO, SO, UC/L, UPAD, UR/W and BASE are also initialized to their default values.
XX03
XX02
XX01
XXOO
XX07
XX06
XX05
XX04
XX03
XX02
XX01
XXOO
H{ ~-WA",oomroc=m
::
{AUTO START ROM PATrERN
~{
'BB
AABB
= ENTRY POINT ROUTINE
I-CC{
'Do CCDD = XX06
tHH{
t--t:f HHLL =XX04
fAS{
'SA AUTO START PATTERN
'-1 K BOUNDARY
AUTO START MACHINE CODE PROGRAM
1KBOUNDARY
AUTO START FORTH PROGRAM
Figure 3-7. Auto Start ROM
3-212
R65F11 • R65F12
FORTH Based Microcomputers
SECTION 4
PARALLEL INPUT/OUTPUT PORTS
4.2 OUTPUTS
The R65Fll has 16 VO lines grouped into two B-bit ports
(PA, PB) and 16 lines programmed as an Address/Data bus
(PC & PO). Ports A and B may be used either for input or
output individually or in groups of any combination. The
R65F12 has 24 additional port lines grouped into three B-bit
ports (PE, PF, PG).
Outputs for Ports A and B are controlled by writing the
desired VO line output states into the corresponding I/O port
register bit positions. A logic 1 will force a high (>2.4V)
output while a logic 0 will force a low «O.4V) output.
Multifunction VO's such as Port A are protected from normal
port I/O instructions when they are programmed to perform
a multiplexed function.
4.3 PORT A (PA)
Port A can be programmed via the Mode Control Register
(MCR) and the Serial Communications Control Register
(SCCR) as a standard parallel B-bit, bit independent, I/O port
or as serial channel VO lines, counter VO lines, or an input
data strobe for the Port B input latch option. Table 4-3 tabulates the control and usage of Port A.
Internal pull-up resistors (FET's with an impedance range of
3K ,.; Rpu ,.; 12K ohm) are provided on all port pins.
The direction of the VO lines are controlled by B-bit port registers located in page zero. This arrangement provides quick
programming access using simple two-byte zero page
address instructions. There are no direction registers associated with the VO ports, which simplifies I/O handling. The
VO addresses are shown in Table 4-1.
Table 4-1.
In addition to their normal VO functions, PAO and PAl can
detect positive' going edges, and PA2 and PA3 can detect
negative going edges. A proper transition on these pins will
set a corresponding status bit in the IFR and generate ah
interrupt request if the respective Interrupt Enable Bit is set.
The maximum rate at which an edge can be detectb i is onehalf the ~2 clock rate. Edge detection timing is shown in
Appendix F.4.
I/O Port Addresses
Port
Address
A
B
E
F
0000
0001
0004
0005
0006
G
4.4 PORT B (PB)
Port B can be programmed as an 8 bit, bit independent I/O
port. It has a latched input capability which may be enabled
or disabled via the Mode Control Register (MCR). Table
4-2 tabulates the control and usage of Port B. An Input Data
Strobe signal must be provided thru PAO when Port B is programmed to be used with latched input option. Input data
latch timing for Port B is shown in Appendix F.4.
Appendix F.4 shows the I/O Port Timing.
4.1 INPUTS
Table 4-2.
Inputs for Ports A and B are enabled by loading logic 1 into
all I/O port register bit posnions that are to correspond to
VO input lines. A low «O.8V) input signal will cause a logic
o to be read when a read instruction is issued to the port
register. A high (>2.0V) input will cause a logic 1 to be read.
An RES signal forces all VO port registers to logic 1 thus
initially treating all VO lines as inputs.
Port B Control & Usage
Latch
Mode
1/0 Mode
MCR4
The status of the input lines can be interrogated at any time
by reading the VO port addresses. Note that this will return
the actual status of the input lines, not the data written into
the VO port registers.
Read/Modify/Write instructions can be used to modify the
operation of PA and PB. During the Read cycle of a Read/
Modify/Wrne instruction the Port VO register is read. For all
other read instructions the port input lines are read. Read/
Modify/Wrne instructions are: ASL, DEC, INC, LSR, RMB,
ROL. ROR, and 5MB.
=0
MCR4
(2)
Pin
No.
R65F12
Name
Type (1)
Name
Type
38
37
36
35
34
33
32
31
8
7
6
5
4
3
2
1
PBO
PBI
PB2
PB3
PB4
PBS
PBS
PB7
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
PBO
PBI
PB2
PB3
PB4
PBS
PBS
PB7
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Signal
Signal
(1) Resistive pull-up, active buffer pull down
(2) Input data is stored in port B latch by PAO pulse
3-213
=1
Pin
No.
R65Fli
D
R65F11 • R65F12
FORTH Based Microcomputers
Table 4-3.
Port A Control and Usage
PAO I/O
R65Fll/R65FI2
PORTIS)
PORT B LATCH MODE
=0
MCR4
PAOI')
=1
MCR4
SIGNAL
SIGNAL
NAME
TYPE
NAME
TYPE
PAO
I/O
PORTB
LATCH STROBE
INPUTI1I
PA1-PA3I/0
PAl i2l
PA213)
PA3 13 )
SIGNAL
NAME
TYPE
PAl
PA2
PA3
I/O
I/O
I/O
PA41/0
PA4
MCRO = 0
MCRI = 0
SCCR? = 0
RCVR SIR MODE
COUNTER A I/O
MCRO = 1
MSRI = 0
SCCR? = 0
RCVR SIR MODE
= 0 14 )
SCCR? = 0
seCR6 = 0
MCRI = 1
= 0 14 )
(6)
SIGNAL
SIGNAL
SIGNAL
NAME
TYPE
NAME
TYPE
NAME
PA4
I/O
CNTA
OUTPUT
CNTA
I
TYPE
I
INPUT (1)
SERIAL I/O SHIFT REGISTER CLOCK
seCR?
SCCR5
=1
=1
RCVR SIR MODE
SIGNAL
J
NAME
I
XMTR CLOCK
SIGNAL
TYPE
NAME
OUTPUT
RCVR CLOCK
PA51/0
MCR3
MCR2
PAS
= 1 14 )
I
I
COUNTER B I/O
=0
=0
MCR3
MCR2
SIGNAL
=0
=1
MCR3
MCR2
SIGNAL
TYPE
NAME
TYPE
NAME
PA5
I/O
CNTB
OUTPUT
CNTB
SERIAL I/O
XMTR OUTPUT
PA61/0
seCR?
=0
SCCR?
=1
SIGNAL
SIGNAL
NAME
TYPE
NAME
TYPE
PAS
I/O
XMTR
OUTPUT
SERIAL I/O
RCVRINPUT
PA?I/O
seCR6
PAl
=0
SCCR6
SIGNAL
=1
SIGNAL
NAME
TYPE
NAME
TYPE
PAl
I/O
RCVR
INPUT (1)
3-214
=1
=X
SIGNAL
NAME
PAS
TYPE
INPUT (1)
(1)
(2)
(3)
(4)
I
I
TYPE
INPUT (1)
HARDWARE BUFFER FLOAT
POSITIVE EDGE DETECT
NEGATIVE EDGE DETECT
RCVR SIR MODE = 1 WHEN
SCCR6 • SCCRS • SCCR4 = 1
(5) APPLIES TO EITHER R65Fll
OR R65F12 PORT (SEE PIN
DIAGRAM)
(6) FOR THE FOLLOWING MODE
COMBINATIONS PA4 IS
AVAILABLE AS AN INPUT
ONLY PIN:
SCCR?·SCCR6·SCCR5·
MCRI + SCCR? • SCCR6 •
ScCFi4 • MCRI + SCCR? •
SCCR6 • SCCFi5 + SCCR?·
SCCRS • SCCR4·
R65F11 • R65F12
FORTH Based Microcomputers
4.5 PORT C (PC)
4.6 PORT D (PD)
Port C is preprogrammed as part of the Address/Data bus.
PCO-PC7 function as AO-A3, A12, R/W, A13, and EMS,
respectively, as shown in Table 4-4. EMS (External Memory
Select) is asserted (low) whenever the internal processor
accesses memory area between 0100 and 3FFF. (See
Memory Map, Appendix C). The leading edge of EMS may
be used to strobe the eight address lines multiplexed on Port
D. See Appendix F.3"for Port C timing.
Port [j is also preprogrammed as part of the Address/Data
bus. Data bits DO through 07 are time multiplexed with
address bits A4 through All, respectively. Refer to the
Memory Maps (Appendix C) for Multiplexed memory assignments. See Appendix F.3 for Port 0 timing.
4.7 PORT E (PE~ PORT F (PF).
PORT G (PG)
Ports E, F and G are available on the R65F12 only. Port E
can only be used as outputs. Port F and Port G can be used
for inputs or outputs and are similar to Port A and Port B in
operation.
Table 4-4.
Port C Control and Usage
Multiplexed
Mode
MCR7
MCR6
=1
=1
R65Fll1
R65F12
Port
Name
Type (1)
PCO
PCl
PC2
PC3
PC4
PC5
PCS
PC7
AO
A1
A2
A3
A12
RIW
A13
EMS
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
Signal
Table 4-5.
Port 0 Control and Usage
Muttlptexed
Mode
MCR7 = 1
MCR6' = 1
MCR5 = 1
R65F111
R65F12
Port
PD~
PD1
PD2
PD3
PD4
PD5
PD6
PD7
Signal
Signat
Phase 1
Phase 2
Name
Type (2)
Name
Type (3)
M
A5
A6
A7
AS
A9
A10
A11
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
DATAO
DATA1
DATA2
DATA3
DATM
DATA5
DATA6
DATA7
1/0
1/0
(1). Active Buffer Pull-up and Pull-Down
(2) Tri-State Buller is in Active Mode
(3) Tri-State Buffer is in Active Mode only during the Phase 2 Portion 01 a Write Cycle
3-215
110
1/0
1/0
1/0
1/0
1/0
FORTH Based Microcomputers
R65F11. R65F12
SECTION 5
SERIAL INPUT/OUTPUT CHANNEL
ASYNCHRONOUS MOOE WITHOUT PARITY
The R65Fll and R65F12 Microcomputers provide a full
duplex Serial 110 channel with programmable bit rates and
operating modes. The serial VO functions are controlled by
the Serial Communication Control Register (SCCR). The
seCR bit assignment is shown in Figure 5-1. The serial bit
rate is determined by Counter A for all modes except the
Receiver Shift Register (RCVR SIR) mode for which an
external shift clock must be provided. The maximum data
rate using the internal clock is 62.5K bits per second (@ ~2
= 1 MHZ). The transmitter (XMTR) and receiver (RCVR) can
be independently programmed to operate in different modes
and can be independently enabled or disabled.
SCCR
2 STOP
I
I Sl~RlI
IPA~ITYI
Addr 0015
2 STOP
I PA~rTV 1
O-Odd Parity
1....... Even Parity
I
o
1
o XMTR
1 XMTR
o Parity Disable
1 Parity Enable
a 0 - 8 Bits/Char
o
1 _7 Bits/Char
1
0-6 Bits/Char
1- 5 Bits/Char
1
a a XMTR • RCVR ASYN Mode
o
1 XMTR ASYN, RCVR SIR
1
X XMTR SIR, RCVR ASYN
RCVR Disable
RCVR Enable
Disable
Enable
StlIFTREGtSTEAClOCKtPA4)
Figure 5·2. Bit Allocations
In the SIR mode, eight data bits are always shifted out. Bitsl
character and parity control bits are ignored. The senal data
is shifted out via the SO output (PA6) and the shift clock is
available at the CA (PA4) pin. When the transmitter underruns in the SIR mode the SO output and shift clock are held
in a high state.
Figure 5-1. Serial Communication Control Register
Except for the Receiver Shift Register Mode (RCVR SIR), all
XMTR and RCVR bit rates will occur at one sixteenth of the
Counter A interval timer rate. Counter A is forced into an
interval timer mode whenever the serial 1/0 is enabled in a
mode requiring an internal clock.
The XMTR Interrupt Flag bit (IFR7) is controlled by Serial
Communication Status Register bits SCCR5, SCCR6 and
SCCR7.
IFR7
Whenever Counter A is required as a timing source it must
be loaded with the hexadecimal code that sEllects the data
rate for the serial 110 Port. Refer to Counter A (paragraph
6.1) for a table of hexadecimal values to represent the desired
data rate.
= SCSR6 (SCCR5 + SCCR7)
5.2 RECEIVER OPERATION (RCVR)
The receiver and its selected control and status functions are
enabled when SCCR-6 is set to a "1." In the ASYN mode,
data format must have a start bit, appropriate number of data
bits, a parity bit (if enabled) and one stop bit. Refer to Figure
5-2 for a diagram of b~ allocations. The receiver bit period
is divided into 8 sub-intervals for internal synchronization.
The receiver bit stream is synchronized by the start bit and
a strobe signal is generated at the approximate center of
each incoming bit. Refer to Figure 5-3 for ASYN Receive
Data Timing. The character assembly process does not start
if the start bit signal is less than one-half the bit time after a
low level is detected on the Receive Data Input. Framing
error, over-run, and parity error cond~ions or a RCVR Data
Register Full will set the appropriate status bits, and any of
the above conditions will cause an Interrupt Request if the
Receiver Interrupt Enable bit is set to logic 1.
5.1 TRANSMITTER OPERATION (XTMR)
The XTMR operation and the transmitter related controll
status functions are enabled by bit 7 of the Serial Communications Control Register (SCCR). The transmitter, when in
the Asynchronous (ASYN) mode, automatically adds a start
bit, one or two stop bits, and, when enabled, a parity bit to
the transmitted data. A word of transmitted data (in asynchronous parity mode) can have 5, 6, 7, or 8 bits of data.
The nine data modes are shown below. When parity is disabled, the 5, 6, 7 or 8 bits of data are terminated with two
stop bits.
3-216
R65F11. R65F12
Serial
FORTH Based Microcomputers
I
received data has a parity error. This bit is cleared
by reading the Receiver Data Register or by RES.
SCSR 3: Framing Error-Set to a logic 1 when the received
data contains a zero bit after the last data or parity
bit in the stop bit slot. Cleared by reading the
Receiver Data Register or by RES. (ASYN Mode
only).
SCSR 4: Wake·Up-Set to a logic 1 by writing a "1" in bit
4 of address: 0016. The Wake· Up bit is cleared by
RES or when the receiver detects a string of ten
consecutive l's. When the Wake·Up bit is set
SCSRO through SCSR3 are inhibited.
SCSR 5: End of Transmission-Set to a logic 1 by writing
a "1" in bit position 5 of address: 0016. The End
of Transmission bit is cleared by RES or upon
writing a new data word into the Transmitter Data
Register. When the End·of·Transmission bit is true
the Transmitter Register Empty bit is disabled until
a Transmitter Under·Run occurs.
SCSR 6: Transmitter Data Register Empty-Set to a logic
1 when the contents of the Transmitter Data Reg·
ister is transferred to the Transmitter Shift Reg·
ister. Cleared upon writing new data into the
Transmit Data Register. This bit is initialized to a
logic 1 by RES.
SCSR 7: Transmitter Under·Run-Set to a logic 1 when the
last data bit is transmitted if the transmitter is in a
SIR Mode or when the last stop bit is transmitted
if the XMTR is in the ASYN Mode while the Trans·
mltter Data Register Empty Bit is set. Cleared by
a transfer of new data into the Transmitter Shift
Register, or by RES.
I
Inpul - ,
::
'::s::t.=rt"':a:::II""--:L:";S:";;a:--'-'" ...--....L..---"Stop all Stop alt
Internal
~~=k L..FL...fL.....~
-S.rlallnput Oeta Shtfted In
Figure 5-3. ASYN Receive Data Timing
In the SIR mode, an external shift clock must be provided at
CA (PA4) pin along with 8 bits of serial data (LSB first) at the
SI input (PA7). The maximum data rate using an external
shift clock is one·eighth the internal clock rate. Refer to
Figure 5·4 for SIR Mode Timing.
. Senal Input Data Shifted In
.. Serial Output Data Makes Transition
Figure 5-4. SIR Mode Timing
A RCVR interrupt (IFR6) is generated whenever any of
SCSRO·3 are true.
SCSRI
7
I
6
I
5
I
4
I J I I I
II l-~
3
2
5.3 SERIAL COMMUNICATION STATUS
REGISTER (SCSR)
1
0
Add. 0016
Reg Full
RCVR Over-Run
The Serial Communication Status Register (SCSR) holds
information on various communication error conditions, status
of the transmitter and receiver data registers, a transmitter
end·ol·transmission condition, and a receiver idle line can·
dition (Wake· Up Feature). The SCSR bit assignment is shown
in Figure 5·5. Bit assignments and functions of the SCSR are
as follows:
Parity Error
Frame Error
Wake-Up
End of Transml'slon
XMTR Data Reg Empty
SCSR 0: Receiver Data Register Full-Set to a logic 1 when
a character is transferred Irom the Receiver Shift
Register to the Receiver Data Register. This bit is
cleared by reading the Receiver Data Register, or
by RES and is disabled if SCCR 6 = O. The SCSR
o bit Will not be set to a logic 1 If the received data
contains an error condition, however, a carre·
sponding error bit will be set to a logic 1 instead.
XMTR Under·Run
Figure 5-5.
SCSR Bit Allocations
5.4 WAKE-UP FEATURE
In a multi-distributed microprocessor or microcomputer applications, a destination address is usually included at the
beginning of the message. The Wake-Up Feature allows
non-selected CPU's to ignore the remainder of the message
until the beginning of the next message by setting the WakeUp bit. As long as the Wake-Up flag is true, the Receiver
Data Register Full Flag remains false. The Wake-Up bit is
automatically cleared when the receiver detects a string of
ten consecutive 1"s which indicates an idle transmit line.
When the next byte is received, the Receiver Data Register
Full Flag signals the CPU to wake·up and read the received
data.
SCSR 1: Over·Run Error-Set to a logic 1 when a new char·
acter is transferred from the Receiver Shift Reg·
ister, with the last character still in the Receiver
Data Register. This bit IS cleared by reading the
Receiver Data Register, or by RES.
SCSR 2: Parity Error-Set to logic 1 when the RCVR is in
the ASYN Mode, Parity Enable bit is set, and the
3-217
R65F11 • R65F12
FORTH Based M'icrocomputers
SECTION 6
COUNTER/TIMERS
The R65F11 and R65F12 Microcomputers contain two 16-bit
counters (Counter A and Counter B) and three 16-bit latches
associated with the counters, Counter A has one 16-bit latch
and Counter B has two 16-bit latches, Each counter can be
independently programmed to operate in one of four modes:
Upper Latch A before the contents of the 16-bit latch are
transferred to Counter A Counter A is set to the latch value
whenever Counter A underflows. When Counter A decrements from 0000 the next counter value wil! be the latch
value, not FFFF, and the Counter A Underflow Flag (IFR 4)
will be set to "1", This bit may be cleared by reading the
Lower Counter A at location 0018, by writing to address
location 001 A, or by RES,
Counter B
Counter A
• Retriggerable Interval Counter
• Asymmetrical Pulse
Generation
• Interval Timer
• Event Counter
• Pulse width
measurement
• Pulse Generation
• Interval Timer
• Event Counter
Counter A operates in any of four modes. These modes are
selected by the Counter A Mode Control bits in the Control
Register, See Table 6-1,
Table 6-1. Counter A Control Bits
Operating modes of Counter A and Counter B are controlled
by the Mode Control Register, All counting begins at the
initialization value and decrements, When modes are selected
requiring a counter inpuVoutput line, PA4 is automatically
selected for Counter A and PA5 is automatically selected for
Counter B (see Table 4,2),
Counter A consists of a 16-bit counter and a 16-bit latch
organized as follows: Lower Counter A (LCA), Upper Counter
A (UCA), Lower Latch A (LLA), and Upper Latch A (ULA) ,
The counter contains the count of either ¢2 clock pulses or
external events, depending on the counter mode selected,
The contents of Counter A may be read any time by executing a read at location 0019 for the Upper Counter A and
at location 001A or location 0018 for the Lower Counter A,
A read at location 0018 also clears the Counter A Underflow
Flag (IFR4),
1. When the Counter is decremented from 0000, the next
Counter value is the Latch value (not FFFF),
2, When a write operation is performed to the Load Upper
Latch and Transfer Latch to Counter address 001 A,
the Counter is loaded with the Latch value. Note that
the contents of the Accumulator are loaded into the
Upper Latch before the Latch value is transferred to
the Counter,
The Counter value is decremented by one count at the ~2
clock rate, The 16-bit Counter can hold from 1 to 65535
counts, The Counter Timer capacity is therefore 1/Ls to 65535
ms at the 1 MHz ~2 clock rate or 0.5 /LS to 32,767 ms at the
2 MHz ~2 clock rate. Time intervals greater than the maximum Counter value can be easily measured by counting
IRQ interrupt requests in the counter IRQ interrupt routine,
I
COUNTER UNDERFLOW
I
cOuHTER'-"---'-_'------'----'_--L----''-...l.,--''(u'i'L,'''LLol,.-,-'",(U",L,,,,LL::!,)-=-"L'_
SET ANY TIME BEFORE
COUNTER UNDERFLOW
Mode
Interval Timer
Pulse Generation
Event Counter
Pulse Width Measurement
In the Interval Timer mode the Counter is initialized to the
Latch value by either of two conditions:·
to
COUNTER UNDERFLOW FLAG
0
1
0
1
6.1.1 Interval Timer
Counter A can be started at any time by writing to address:
001 A, The contents of the accumulator will be copied into the
~
0
0
1
1
The Counter IS set to the Interval Timer Mode (00) when a
RES signal is generated,
The 16-bit latch contains the counter initialization value, and
can be loaded at any time by executing a write to the Upper
Latch A at location 0019 and the Lower Latch A at location
0018, In either case, the contents of the accumulator are
copied into the applicable latch register,
COUNTER INTERRUPT ENABLED
MCRO
(bit 0)
The Interval Timer, Pulse Generation, and Pulse Width Measurement Modes are ~2 clock counter modes, The Event
Counter Mode counts the occurrences of an external event
on the CNTR line,
6.1 COUNTER A
I
MCRI
(bit 1)
II
10----:- - - - - -
When Counter A decrements from 0000, the Counter A
Underflow (IFR4) is set to logic 1, If the Counter A Interrupt
Enable Bit (IER4) is also set, an IRQ interrupt request will be
generated, The Counter A Underflow bit in the Interrupt Flag
Register can be examined in the IRQ interrupt routine to
determine that the IRQ was generated by the Counter A
Underflow.
1
Figure 6-1. Interval Timer Timing Diagram
3-218
R65F11 • R65F12
FORTH Based Microcomputers
While the timer is operating in the Interval Timer Mode, PM
operates as a PA 1/0 bit.
The Counter A underflow flag will be set only when the count
in the timer reaches zero. Upon reaching zero the timer will
be loaded with the latch value and continue counting down
as long as the CA pin is held low. After the counter is stopped
by a high level on CA, the count will hold as long as CA
remains high. Any further low levels on CA will again cause
the counter to count down from its present value. The state
of the CA line can be determined by testing thE' state of PM.
A timing diagram of the Interval Timer Mode is shown in
Figure 6-f.
6.1.2 Pulse Generation Mode
In tile Pulse Generation mode, the CA line operates as a
Counter Output. The line tOggles from low to high or from
high to low whenever a Counter A Underflow occurs, or a
write is performed to address 00IA.
A timing diagram for the Pulse Width Measurement Mode is
shown in Figure 6-3.
The normal output waveform is a symmetrical square-wave.
The CA output is initialized high when entering the mode and
transitions low when writing to 001 A.
112
CNTR
Asymmetric waveforms can be generated if the value of the
latch is changed after each counter underflow.
COUNT
A one-shot waveform can be generated by changing from
Pulse Generation to Interval Timer mode after only one
occurrence of the output toggle condition.
--I f--T
PDSU
2.0V
NI
N-l
N·3
N·2
Figure 6·3. Pulse Width Measurement
6.1.3 Event Counter Mode
In this mode the CA is used as an Event Input line, and the
Counter will decrement with each rising edge detected on
this line. The maximum rate at which this edge can be
detected is one-half the ~2 clock rate.
6.1.5 Serial 1/0 Data Rate Generation
Counter A also provides clock timing for the Serial 1/0 which
establishes the data rate for the Serial 1/0 port. When the
Serial I/O is enabled, Counter A is forced to operate at the
internal clock rate. Counter A is not required for the RCVR
SIR mode. The Counter 1/0 (PM) may also be required to
support the Serial 1/0 (see Table 4-2).
The Counter can count up to 65,535 occurrences before
underflowmg. As in the other modes, the Counter A Underflow bit (IER4) is set to logic 1 if the underflow occurs.
Figure 6.2 is a timing diagram of the Event Counter Mode.
Table 6-2 identifies the values to be loaded in Counter A for
selecting standard data rates with a ~2 clock rate of 1 MHz
and 2 MHz. Although Table 6-2 identifies only the more
common data rates, any data rate from 1 to 62.5K bps can
be selected by using the formula:
N
=
16
~2
x bps
-1
where
N
Figure 6·2. Event Counter Mode
~2
bps
6.1.4 Pulse Width Measurement Mode
decimal value to be loaded into Counter A using
its hexadecimal equivalent.
the clock frequency (1 MHz or 2 MHz)
the desired data rate.
NOTE
This mode allows the accurate measurement of a low pulse
duration on the CA line. The Counter decrements by one
count at the ~2 clock rate as long as the CA line is held in
the low state. The Counter is stopped when CA is in the high
state.
In Table 6-2 you will notice that the standard data rate
and the actual data rate may be slightly different.
Transmitter and receiver errors of 1.5% or less are
acceptable. A revised clock rate is included in Table
6-2 for those baud rates which fall outside this limit.
3-219
II
FORTH Based Microcomputers
R65F11 • R65F12
occurs on the CB pin (PAS). The Counter B interrupt flag will
be set if the counter underflows before a positive edge occurs
on the CB line. Figure 6-4 illustrates the operation.
Table 6-2. Counter A Values for Baud Rate Selection
I
Standard
Baud
Rate
50
75
110
150
300
600
1200
2400
3600
4800
7200
9600
Hexadecimal
Value
Actual
Baud
Rate At
1 MHz 2 MHz
1 MHz
O4El
0340
0237
01AO
OOCF
0067
0033
0019
0010
OOOC
0006
0006
50.00
75.03
110.04
149.88
300.48
600.96
1201.92
2403.85
3676.47
4807.69
6944.44
8928.57
09C3
0682
046F
0340
01AO
OOCF
0067
0033
0021
0019
0010
oooc
Clock Rate
Needed .
To Get
Standard
Baud Rate
2 MHz 1 MHz 2 MHz
50.00
74.99
110.04
150.06
299.76
600.96
1201.92
2403.85
3676.47
4807.69
7352.94
9615.38
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1 .0000
0.9792
1 .0000
1.0368
1.0752
2.0000
2.0000
2.0000
2.0000
2.0000
2.0000
2.0000
2.0000
1.9584
2.0000
1.9584
2.0000
CB LINE
RESET BY
4/S0FTWARE
COUNTERB-----.....JIlL
FLAG
----
Figure 6-4. Counter B. Retriggerable Interval Timer Mode
6.2.2 Asymmetrical Pulse Generation Mode
6.2 COUNTER B
Counter B has a special Asymmetrical Pulse Generation
Mode whereby a pulse train with programmable pulse width
and period can be generated without the processor intervention once the latch values are initialized.
Counter B con!jists of a IS-bit counter and two IS-bit latches
organized as follows: Lower Counter B (LCB). Upper Counter
B (UCB), Lower Latch B (LLB). Upper Latch B (ULB), Lower
Latch C (LLC), and Upper Latch C (ULC). Latch C is used
only in the asymmetrical pulse generation mode. The counter
contains the count of either ~2 clock pulses or external
events depending on the counter mode selected. The contents of Counter B may be read any time by executing a read
at location 0010 for the Upper Counter B and at location
ODIE or ODIC for the Lower Counter B. A read at location
ODIC also clears the Counter B Underflow Flag.
In this mode. the 16-bit Latch B is initialized with a value
which corresponds to the duration between pulses (referred
to as 0 in the following descriptions). The 16-bit Latch C is
initialized with a value which corresponds to the desired
pulse width (referred to as P in the following descriptions).
The initialization sequence for Latch Band C and the starting
of a counting sequence are as follows:
I. The lower 8 bits of P are loaded into LLB by writing to
address 001 C. and the upper 8 bits of P are loaded
into ULB and the full 16 bits are transferred to Latch
C by writing to address location DOlO. At this point
both Latch B and Latch C contain the value of P.
Latch B contains the counter initialization value, and can be
loaded at any time by executing a write to the Upper Latch
B at location 0010 and the Lower Latch B at location ODIC.
In each case, the contents of the accumulator are copied into
the applicable latch register.
2. The lower 8 bits of 0 are loaded into LLB by writing to
address ODIC, and the upper 8 bits of 0 are loaded
into ULB by writing to address location DOlE. Writing
to address location 00 I E also causes the contents of
the 16-bit Latch B to be downloaded into the Counter
B and causes the CB output to go low as shown in
Figure 6-5.
Counter B can be initialized at any time by writing to address:
ODIE. The contents of the accumulator is copied into the
Upper Latch B before the value in the IS-bit Latch B is transferred to Counter B. Counter B will also be set to the latch
value and the Counter B Underflow Flag bit (IFR5) will be set
to a "I" whenever Counter B underflows by decrementing
from 0000.
3. When the Counter B underflow occurs the contents of
the Latch C is loaded into the Counter B, and the CB
output toggles to a high level and stays high until
another underflow occurs. Latch B is then down-loaded
and the CB output toggles to a low level repeating the
whole process.
IFR 5 may be cleared by reading the Lower Counter B at
location DOIC. by writing to address location ODIE. or by
RES.
Counter B operates in the same manner as Counter A in the
Interval Timer and Event Counter modes. The Pulse Width
Measurement Mode is replaced by the Retriggerable Interval
Timer mode and the Pulse Generation mode is replaced by
the Asymmetrical Pulse Generation Mode.
CB
OUTPUT
6.2.1 Retriggerable Interval Timer Mode
2 3
1 AND 3. COUNTER B 2 AND 4. COUNTER B _
When operating in the Retriggerable Interval Timer mode,
Counter B is initialized to the latch value by writing to address
001 E. by a Counter B underflow. or whenever a positive edge
Figure 6·5.
3-220
4
LATCH B (D)
LATCH C (P)
Counter B Pulse Generation
FORTH Based Microcomputers
R65F11 • R65F12
SECTION 7
POWER ON/INITIALIZATION CONSIDERATIONS
7.1 POWER·ON·RESET
-5------
_------~.~----
Vcco~
. '-..POWERON
The occurrence of RES going from low to high will cause the
R65Fli or R65F12 to reset and enter the RSC-FORTH
Operating System. As was described in Section 3.8, upon
reset certain system variables will be inttialized. See Appendix
C.4 for a list of these variables names, locations and contents. The external memory map will be searched for an auto
start ROM.
XTLO
1_ CLOCK
STABILIZATION
TIME
1l2~JlJ1JUl.J1nIlJL
I~L~C~
RES
A bit pattern of A55A at a 1K byte page boundary indicates
that an auto start program follows. The next two bytes are
assumed to be a pointer to the high level RSC-FORTH word
that is the entry point to that program. Auto start programs
is written in assembly language, rather than RSC-FORTH,
a series of indirect pointers as shown in 3-7 can be used to
inttiate program execution.
CYCLES M I N r -
Figure 7-1.
Power Turn-On Timing Detail
7.3 RESET (RES) CONDITIONING
When RES is driven from low to high the R65Fli or R65F12
is put in a reset state. The registers and VO ports are configured as shown in Table 7-1 when the external ROM is
autostarted.
Table 7-1. RES Initialization of I/O Ports and Registers
7.2 POWER ON TIMING
After application of Vcc and V RR power to the R65Fli or
clock
R65F12, RES must be held low for at least eight
cycles after Vcc reaches operating range and the internal
oscillator has stabilized. This stabilization time is dependent
upon the input V cc voltage and performance of the internal
oscillator. The clock can be monitored at
(pin 3). Figure
7-1 illustrates the power turn-on waveforms. Clock stabilization time is typically 20 ms.
P2
Jt2
3-221
7
6
5
4
3
2
1
0
REGISTERS
Mode Control (MCR)
Int. Enable (IER)
Int. Flag (IFR)
Ser. Com. Control (SCCR)
Sar. Com. Status (SCSR)
1
0
0
1
0
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
PORTS
PA Latch
PB Latch
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R65F11 • R65F12
FORTH Based Microcomputers
APPENDIX A
R65F11 AND R65F12 INSTRUCTION SET
This appendix contains a summary of the R6500 instruction
set. For detailed information, consult the R6500 Microcomputer System Programming Manual, Document 29650 N30.
The four instructions notated with a • are added instructions
for the R65F11 and R65F12 which are not part of the standard 6502 instruction set.
A.1 INSTRUCTION SET IN ALPHABETIC SEQUENCE
Mnemonic
Instruction
Mnemonic
ADC
AND
ASL
Add Memory to Accumulator with Carry
"AND" Memory with Accumulator
Shift Left One Bit (Memory or Accumulator)
LDA
LDX
LDY
LSR
Load Accumulator with Memory
Load Index X with Memory
Load Index Y with Memory
Shift One Bit Right (Memory or
Accumulator)
NOP
No Operation
ORA
"OR" Memory with Accumulator
PHA
PHP
PLA
PLP
Push Accumulator on Stack
Push Processor Status on Stack
Pull Accumulator from Stack
Pull Processor Status from Stack
'RMB
ROL
Reset Memory Bit
Rotate One Bit Left (Memory or
Accumulator)
Rotate One Bit Right (Memory or
Accumulator)
Return from Interrupt
Return from Subroutine
'BBR
'BBS
BCC
BCS
BEQ
BIT
BMI
BNE
BPL
BRK
BVC
BVS
)
Branch on Bit Reset Relative
Branch on Bit Set Relative
Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits in Memory with Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Force Break
Branch on Overflow Clear
Branch on Overflow Set
CLC
CLD
CLI
CLV
CMP
CPX
CPY
Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable Bit
Clear Overflow Flag
Compare Memory and Accumulator
Compare Memory and Index X
Compare Memory and Index Y
DEC
DEX
DEY
Decrement Memory by One
Decrement Index X by One
Decrement Index Y by One
EOR
"Exclusive-Or" Memory with
Accumulator
INC
INX
INY
Increment Memory by One
Increment Index X by One
Increment Index Y by One
JMP
JSR
Jump to New Location
Jump to New Location Saving Return
Address
ROR
RTI
RTS
SBC
SEC
SED
SEI
'SMB
STA
STX
STY
TAX
TAY
TSX
TXA
TXS
TYA
3-222
Instruction
Subtract !VIemory from Accumulator with
Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Set Memory Bit
Store Accumulator in Memory
Store Index X in Memory
Store Index Y in Memory
Transfer Accumulator to Index X
Transfer Accumulator to Index Y
Transfer Stack POinter to Index X
Transfer Index X to Accumulator
Transfer Index X to Stack Register
Transfer Index Y to Accumulator
~;
~
A.2 R65F11 AND R65F12 INSTRUCTION SET SUMMARY TABLE
UI
PROCESSOR STATUS
CODES
R65Fll AND R65F12 ADDRESS MODES
INSTRUCTIONS
7 6
BIT ADDRESSING lOP BV BIT of)
MNEMONIC
'"
'"
~
OPERATION
ADC
ANO
A·M·c--.A
A M~A
(4)(1)
(1)
ASL
C~ ~.-O
BBAI#ID-7))
B85(1I(0-711
BCe
BeS
BEQ
M. ~ 1
BranchonC,O
Brsn:::honC-,'
Branch on Z - 1
BranchonM.~O
(5)[2)
(5)(2)
(2)
(2)
(2)
BrarICh on
BIT
AJ\M
8MI
SNE
BPL
BRK
BVe
BranchonN'"
SranchonZ=O
BranchonN",O
Break
Blanch on V-O
(2)
(2)
(2)
BVS
Bran:;:hOll V"t
(2)
CLC
O~C
ClD
0--0
ell
elV
eMP
0-1
A M (1)
X M
V M
M l ____ M
DEX
DEY
X I_X
V I-V
EOR
A"iM-A
JMP
JSR
LOA
LOX
Jump 10 New Loc
Jump Sub
M-A (1)
M_X (1)
LOV
M-Y
(1)
lSR
O--~-C
NOP
ORA
PHA
PHP
PlA
No Operation
AVM-A (I)
PLP
5 -1-5 Ms-P
sec
30
DO
10
;~
08
56
86
c,
•
Z C
Z
I'
,
20
A222AE
A022AC
ATITO
'E
09
2
2
00
·
,
3
•
3
~
46
2
2
2 14AI 211
05
3
2
A M C-A (1) (4)
•
(5)
~
UI
"T1
MM. -
-
••
z
I'
,
I; I~
EllTO
80
8E ••
8C
5
E5
3
2
2
I
5
I 2 I 55
~~1~1;1591413
I 2 I Bll
5
I 2 I 851
4
I 2 I BO I 4 I 3 I :~
I:
.c
1'131
~:I:I~I~~I~I;
B,I.I,I
I
I
1
1
1
1
1
I~
I
6A
2
3 1
311
Z
Z
Z
Z C
N •••••
•
1
:~ I: I!
071 17 I 21 I 37 141 I 51 I 67 1171 •
;:1 :1~ I;~
Z C
Z C
{ReSloredl
Ell 61 21 Fll 51 2 J F51 41 2 I FO I 41 3 J F91 4 I 3
1
1
8197
85
TAX
TAY
TSX
TXA
A..... X
A-Y
S-X
X_A
TXS
X-S
9A
TYA
Y..... A
9BI 2 ! 1
Z (31
N V
381'11
F6 2
762
Z
IResloredl
A-M
X-M
Y-M
NOTES
1 Add 1 to N If page boundary IS crossed
2. Add 1 to N II branch occurs to same page
Add 2 to N II branch occurs to dIfferent page
3. Carry not = Borrow
4 If In deCImal mode Z flag IS Invalid
accumulator must be checked on zero result
5 Effects 8-bIt data fIeld 01 the spectlled zero page address
Z C
Z C
Z C
Z
Z
Z
Z
Z
Z
Z
0616121nEI713
"128 •
STA
STX
STY
4
O·
• 0
011 61 21 11 I 5 I 2 I 151 4 I 2 110 I 4 I 3 I 19 I 4 13
'ITTII
2'
3
o ..
Fa
EA 12 11
06
66
,
All 6
68
6E2E
2
411 61 21 51
3
3
5
A4
1
1
E8
C8
"IT
A6
2
2
;: I~ I~
E6
Ms--A
(5)
l-C
1-0
-"
•
-"
N
;:1 !~I ~~ I~~I ~~I·~~ I~~
cll 6 I 2 I 01 I 5 I 2 I 051 4 I 2 I DO I 4 I 3 I 09 I 4 I 3
C.E'
C6
451 3 12
5 1-5
5 1-5
Rlm)nl
Alrn Sub
SEI
l-T
SM8[1I(0-7)J l_M.
~:I
90
(1)
X·l-X
y·, ... y
RIS
V
N
BO
Fa 12 12
EO 2 2 EC
C'I'ITO
CO 2 2 CC
CE
M·l-M
A-Ms
P-Ms
1 D
00 I 7 11
INC
5-1-5
2
Z C
(2)
INX
INY
SEC
SEC
N
"1211
CPX
CPY
=g~
ATI
"
2C 14131 241 3 12
DEC
3
71NV-BDIZC
.9
o-v
RMB[N(O-71] O-M.
5 ..
"T1
-"
A1
87
C1
07
E71F7
I:
96
4
~
2
I I~
941 41 2
84
MI2
A8
BA
8A
N
LEGEND
x
Y
A
M
M.
MD
M,
M.
'"
Index X
Index Y
Accumulator
Memory per effective address
Memory per slack pointer
Selecter zero page memory bll
.,. Memory BIt 7
=
=
=
=
::I:
OJ
I»
611 61 21 911 61 2 I 951 41 2 I 90 I 5 I 3 I ' ,I 5 I 3
86
C3
~
Co
s:
c:;.
• Z
•
= Memory Btt 6
= Add
= Subtract
A
And
V
0,
ExcluSive Or
Number 01 cycleS
Number 01 Bytes
...
o
(')
o
3
"tJ
C
...
CD
tn
II
FORTH Based Microcomputers
R65F11 • R65F12
A,3 INSTRUCTION CODE MATRIX
9
A
ORA
zp
2 3
ASl
ZP
2 5
RMBO
ZP
2 5
PHP
Implied
I 3
ORA
IMM
2 2
ASl
Accum
I 2
BPL
ORA
Relative (IND), Y
2 2"
2 5-
ORA
zp, X
2 4
ASl
ZP,X
2 6
RMBI
ZP
2 5
CLC
Implied
I 2
ORA
ABS, Y
3 4-
AND
ZP
2 3
ROL
ZP
2 5
RMB2
ZP
2 5
PLP
Implied
I 4
AND
IMM
2 2
BMI
AND
Relative (IND,Y)
2'2
2 5-
AND
Zp, X
2 4
ROL
zp,X
2 6
RM83
ZP
2 5
SEC
Implied
I 2
AND
ABS, Y
3 4-
RTI
EOR
Implied (IND,X)
I 6
2 6
EOR
ZP
2 3
LSR
ZP
2 5
RMB4
ZP
2 5
PHA
Implied
I 3
EOR
IMM
2 2
(I~~)~Y
EOR
ZP,X
2 4
LSR
zp,X
2 6
RMB5
ZP
2 5
CLI
EOR
Implied ABS, Y
3 4I 2
RTS
ADC
Implied (IND, X)
I 6
2 6
ADC
ZP
2 3
ROR
ZP
2 5
RMB6
ZP
2 5
PLA
Implied
I 4
ADC
IMM
2 2
BVS
ADC
Relative (IND, Y)
2 52 2"
ADC
zp,X
2 4
ROR
Zp, X
2 6
RMB7
ZP
2 5
SEI
Implied
I 2
ADC
ABS,Y
3 4-
STA
ZP
2 3
STX
ZP
2 3
5MBO
ZP
2 5
DEY
Implied
I 2
2
JSR
AND
Absolute (IND,X)
3 6
2 6
BVC
Relative
2 2"
A
B
C
o
E
F
B
B
BRK
ORA
Implied (IND, X)
2 6
I 7
3
BIT
zp
2 3
2 5-
STY
LSR
Accum
I 2
5MBI
ZP
2 5
TYA
Implied
I 2
STA
ABS, Y
3 5
TXS
Implied
I 2
LOY
ZP
2 3
LOA
2 3
LOX
ZP
2 3
5MB2
ZP
2 5
TAY
Implied
I 2
LOA
IMM
2 2
TAX
Implied
I 2
LOY.
ZP,X
2 4
LOA
Zp,X
2 4
LOX
ZP, Y
2 4
SM83
ZP
2 5
CLV
Implied
I 2
LOA
ABS, Y
3 4-
TSX
Implied
I 2
CPY
ZP
2 3
CMP
ZP
2 3
DEC
ZP
2 5
5MB4
ZP
2 5
INY
Implied
I 2
CMP
IMM
2 2
DEX
Implied
I 2
CMP
Zp, X
2 4
DEC
ZP,X
2 6
5MB5
ZP
2 5
CLO
Implied
I 2
CMP
ABS, Y
3 4-
sse
INC
ZP
2 5
5MB6
ZP
2 5
INX
Implied
I 2
sse
IMM
2 2
INC
Zp,X
2 6
5MB7
ZP
2 5
SED
Implied
I 2
ASS, Y
3 4-
CPY
IMM
2 2
BNE
CMP
(IND, X)
2 6
CMP
Aelative (INO), Y
2 2"
2 5-
CPX
IMM
2 2
(IND,X)
2 6
sse
;,lBC
BEQ
Relative (IN D), Y
2 2"
2 5-
CPX
ZP
2 3
ZP
2 3
sse
Zp, X
2 4
JMP
Indirect
3 5
TXA
Implied
I 2
STY
ABS
3 4
ROL
ABS
3 6
EOR
ABS
3 4
LSR
ABS
3 6
ADC
ABS
3 4
ROR
ABS
3 6
STA
ABS
3 4
STX
ABS
3 4
STA
ABS, X
3 5
LOY
ABS
3 4
LOA
ABS
3 4
CPY
ABS
3 4
CMP
ABS
3 4
LOX
ABS
3 4
DEC
ABS
3 6
CMP
DEC
ABS, X ABS, X
3 43 7
CPX
ABS
3 4
NOP
Implied
I 2
sse
ABS
3 4
INC
ABS
3 6
sse
INC
ABS, X ABS, X
3 43 7
A
B
C
o
BBRI
ZP
5"
3
BBR2
ZP
3 5"
2
BBR3
ZP
3 5"
BBR4
ZP
3 5"
BBR5
ZP
3
5"
BBR6
ZP
3 5"
BBR7
ZP
5"
3
BBSO
ZP
3 5"
BBSI
ZP
3 5"
LOY
LOA
LOX
ABS, X ABS, X ABS. Y
3 43 43 4-
sse
9
AND
ABS
3 4
ADC
ROR
ABS,X ABS, X
3 43 7
STX
Zp, Y
2 4
BCS
LOA
Relative (IND), Y
2 2"
2 5-
JMP
ASS
3 3
ROR
Accum
I 2
STA
Zp,X
2 4
ZP
F
BBRO
ZP
3 5--
EOR
LSR
ABS, X ABS, X
3 43 7
ZP,X
2 4
LOX
IMM
2 2
E
ASl
ABS
3 6
AND
ROL
ABS, X ABS, X
43 7
3
Bec
STA
Relative (IND, Y)
2 2"
2 6
LOA
(IND, X)
2 B
BIT
ABS
3 4
ROL
Accum
I 2
ZP
2 3
LOY
IMM
2 2
o
ORA
ABS
3 4
ORA
ASL
ABS, X ABS, X
3 7
3 4-
STA
(IND, X)
2 6
STY
C
E
BBS2
ZP
5"
A
BBS3
ZP
3 5"
B
BBS4
ZP
3 5"
C
BBSS
ZP
3 5"
o
BBS6
ZP
3 5"
E
BBS7
ZP
3 5"
F
3
F
o
o
-OPCode
-Add 1 to N if page boundary is crossed.
.. Add 1 to N if branch occurs to same page;
add 2 to N if branch occurs to different page.
-Addressing Mode
-Instruction Bytes; Machine Cycles
3-224
R65F11 • R65F12
FORTH Based Microcomputers
APPENDIX B
KEY REGISTER SUMMARY
0
I ACCUMULATOR
I7
0
I7
I7
15
0
INDEX REGISTER
MCR
Addr 0014
v
O-OlmervalTlmer
0 - 1 Pulse Generallon
I INDEX REGISTER X
0
I
PC"
I
I PROGRAM COUNTER
PCl
7
1_!)EwenICounlet
PC
l
I STACK POINTER
SP
7
0
IN\V\
\0
10 1112 Ie I PROCESSOR STATUS REG
1_,PulseWldlhMeas
Bus Mode Select
0
P
0 - 1 Asymmetnc Pulse Generation
1_0EvenlCountel
1 _ ' RelnQgerable'ntelValT,mer
Pon BLaich
(I-Enable)
Port 0 Tn-Sta,e
(\ .. MUll'dBus)
CPU Registers
1 _ I MU.dBus
Mode Control Register
1"IVIIOlol'I'ICI
l L~:::,:~ls~
IFR
O-=Carry Clear
ZERO (ll(!)
1 -=Zero Result
O~Non-ZeloResult
INTERRUPT DISABLE (I)
IER
CD
1 -ffialnlerruPI Disabled
o ·'iRQlrllerrup, Enabled
DECIMAL MODE (0)
CD
PA2 Negative
,-=
Edge Delec;1
DeCimal Mode
0-= Binary Mode
BREAK COMMA.ND IB)
PA3 Negallve
Edge DetltCt
Counter A
Underflow Flag
CD
1 = Break Command
o =Non Break Command
OVERFLOW (01
Count.r B
Underflow Flag
ID
RCVR
Flag
1 .= Overflow Sel
0::: Overflow Clear
NEGATIVE INI
XMTR
Flag
CD
NOTES
G> Nol Initialized by iiE'S
1 :;NegallveValue
0= POSllve Value
Q)
Interrupt Enable and Flag Registers
Sello Logie 1 by liE!>
Processor Status Register
Addr 0015
SCCR
O-odd·Parily
1_Even Parity
o Parity Dlaabla
1 Parity Enabl.
Parity Error
0- 8 Blta/Char
1 _ 7 Bite/Char
0-6 Blta/Char
1
1_ 5 BltafChar
0 - 0 XMTR • RCVR ASYN M_
o- 1 XMTR ASYN, RCVR SIR
1_
End 01 Transml. .ion
X XMTR SIR, RCVR ASYN
XMTR Dlita Reg Empty
o ReVR Dlaabla
1 ReVR Enable
XMTA U.....Aun
oXMTR Dlaable
Serial Communlcellons Stetus Register
1 XMTR Enabla
Serial Communications Control Register
3-225
R65F11. R65F12
FORTH Based Microcomputers
APPENDIX C
ADDRESS ASSIGNMENTS/MEMORY
MAPS/PIN FUNCTIONS
C.1 1/0 AND INTERNAL REGISTER ADDRESSES
ADDRESS
(HEX)
00IF
IE
WRITE
--
lC
Lower Counter B
Upper Counter B
Lower Counter B, CLR Flag
lB
lA
19
18
Lower Counter A
Upper Counter A
Lower Counter A, CLR Flag
Upper Latch A, Cntr
Upper Latch A
Lower Latch A
17
16
15
14
Serial Receiver Data Register
Serial Comm. Status Register
Serial Comm. Control Register
Mode Control Register
Serial
Serial
Serial
Mode
13
12
11
10
Interrupt Enable Register
Interrupt Flag Register
Read FF
10
1---
READ
--
OF
DE
DO
DC
DB
OA
09
08
07
06
05
04
03
02
01
0000
--
--
Upper Latch B, Cntr B<-Latch B, CLR Flag
Upper Latch B, Latch C~Latch B
Lower Latch B.
--
PortG*
Port F*
Port E*
Transmitter Data Register
Comm. Status Reg. Bits 4 & 5 only
Comm. Control Register
Control Register
--Clear Int Flag (Bits 0-3 only, Write D's only)
--
---
--
----
---
PortG*
Port F*
Port E'
--
--Port B
PortA
A, CLR Flag
Interrupt Enable Register
--
---------
A~Latch
--
PortB
PortA
NOTE: 'R65F12 Only
3-226
R65F11. R65F12
FORTH Based Microcomputers
C.3 MULTIPLEXED MODE
MEMORY MAP
C.2 MULTIPLE FUNCTION
PIN ASSIGNMENTSPORT C AND PORT D
PIN
NUMBER
R65Fll
R65F12
I/O PORT
FUNCTION
REPLACED
MULTIPLEXED PORT
FUNCTION
AO
Al
A2
A3
4
5
6
7
25
26
27
28
PCO
PCl
PC2
PC3
8
9
10
11
29
30
31
32
PC4
PC5
PC6
PC7
FFFE
IRQ Vector
RES Vector
NMI Vector
FFFC
FFFA
FORTH Kernal
F400
Reserved
A12
R/W
A13
EMS
19
18
17
16
40
39
38
37
POO
POI
P02
P03
M/OO
A5!Dl
A6/02
A7/03
15
14
13
12
36
35
34
33
P04
P05
P06
P07
A8/04
A9/05
Al 0/06
A11I07
I
-,-3FFF
IUJ9
//
Exlernal Memory
116384 - 256)
Mux'd Addr Mode
I~~
-t-ooFF
Internal RAM (192)
0040
Reserved
oolF
0000
1/0 & Registers
/
/
I
/
/
/
I
/
oolF
I
Internal
Reglaters
/
0010
Resorved
I/O Ports E, F. G
(R65OOJ12Q Only)
1/0 Ports A. B. C, D
WARM START
VALUE
ADDRESS
NAME
0040
0042
0044
0046
0048
004A
004B
004C
004E
0050
0051
0059
005B
0050
IRQVEC
NMIVEC
UKEY
UEMIT
UP
INTFLG
(W-l)
W
IP
(N-l)
N
XSAVE
INTVEC
TOS
(COLO)
(COLD)
(INK)
(OUT)
0300
00
6C
0300
0302
0304
0306
0308
030A
030C
030E
0310
0312
0314
0316
0318
031C
TIB
RO
SO
UCIL
UPAD
UR/W
BASE
CLO/WRM
IN
OPL
HLD
OISKNO
CURCYL
B/SIDE
0380
0380
OOFF
OOFF
OOC2
(COLD)
-
OOC2
0050
037E
(DISK)
0010
-
-
3-227
0006
0004
0003
0000
C.4 SYSTEM VARIABLES IN RAM
COLD START
VALUE
oooF
0007
-
(INK)
(OUT)
0300
00
6C
-
-
-
R65F11 • R65F12
FORTH Based Microcomputers
J•
.l.I... ".. .•.
1
,,~
02
~J.I." ...
~c:l~::I:l
;: ~
:1!:i:1
0
=~
i~!i
§!i§HHi!~
· ' : " ' 0 ••
l!il~
20
I~
I~
•18 •
,,~~8~
t~
.~
F-
•• ·L • -0.
L---4-------~~----------~
I.L ...!rl
W
3-228
FORTH Based Microcomputers
R65F11 • R65F12
APPENDIX E
ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS*
Symbol
Value
Unit
Vee & VRR
-0.3 to +7.0
Vdc
Input Voltage
VIN
-0.3 to + 7.0
Vdc
Operating Temperature Range,
Commercial
TA
T L to TH
o to +70
°C
TSTG
-55 to +150
°C
Parameter
Supply Voltage
Storage Temperature
• NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in the other sections of this document is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
DC CHARACTERISTICS
(Vee
= 5.0V
±5%, VRR
= Vee; Vss = OV; TA = 0° to 70°,
Parameter
RAM Standby Voltage (Retention Mode)
unless otherwise specified)
Symbol
Min
VRR
3.0
-
RAM Standby Current (Retention Mode)
IRR
Input High Voltage
All Except XTLI
XTLI
VIH
Max
Vce
-
4
Unit
Test Conditions
V
mA
TA
= 25°C
V
+2.0
+4.0
-0.3
Vec
Vee
V
±10.0
p.A
VIN
= 0 to 5.0V
-1.6
mA
VIL
= O.4V
-
Vee
V
ILOAD
-
+0.4
V
ILOAD
= -100 p.A
= 1.6 mA
6.0
11.5
Kohm
-
-
±10
p.A
-1.0
-
-
= 1.5V
VIL
liN
-
Input Low Current
PA, PB,PC,PD,PF3, PG3
IlL
-
Output High Voltage (Except XTLO)
VOH
Output Low Voltage
VOL
-
I/O Port Pull-Up Resistance
PAO-PA7, PBO-PB7, PCO-PC7, PFO-Pf73,
PGO-PG73
RL
3.0
Output Leakage Current (Three-State Ofi)
lOUT
10H
+2.4
Input Capacitance
XTLI, XTLO
All Others
CIN
Output Capacitance (Three-State Off)
COUT
-
Power Dissipation (Outputs High)
Po
-
Notes:
1. Typical values measured at TA = 25°C and Vee = 5.0V.
2. Negative sign indicates outward current flow, positive indicates inward flow.
3. R65F12 only.
3-229
-
+0.8
Input Low Voltage
Input Leakage Current
RES, NMI
Darlington Current Drive
PE3
Typl
-1.0
rnA
VOUT
pF
TA = 25°e
VIN = OV
f = 1.0 MHz
-
-
50
10
-
10
pF
TA = 25°C
VIN = OV
f = 1.0 MHz
1000
mW
TA
= 25°C
FORTH Based Microcomputers
R65F11 • R65F12
APPENDIX F
TIMING REQUIREMENTS AND CHARACTERISTICS
F.2 CLOCK TIMING
F.1 GENERAL NOTES
1. Vcc
= 5V
± 5%, O°C .. TA" 70°C
SYMBOL
2. A valid V cc - RES sequence is required before proper
operation is achieved.
3. All timing reference levels are O.BV and 2.0V, unless
otherwise specified.
-
MIN
MAX
500
10/Ls
250
-
Cycle Time
1000
10/Ls
T PWX1
XTU Input Clock
Pulse Width
XTLO = VSS
500
-
± 25
OU1put Clock Pulse T PWX1
Width at Minimum
T A, TF
50pf maximum
T ,A, T'F
(XTLO
T PNX1
T PWX1
± 25
T PWX1
± 20
-
25
-
15
InpU1 Clock Rise,
-
10
-
10
•
Tcyc
-I
T"
XTLI
± 10
OU1pU1 Clock Rise,
Fall Time
Fall Time
I~
2 MHz
MAX
Tcvc
5. All capacitive loading is 130pf maximum, except as noted
below:
PA, PB, PE, PF, PG
1 MHz
MIN
Tcvc
T P'lN02
4. All time un~s are nanoseconds, unless otherwise specified.
PARAMETER
1.SV
= V.S>
T pWX1
TpWQ2
~
02
__ T
A
3-230
.
R65F11 • R65F12
FORTH Based Microcomputers
F.3 MULTIPLEXED MODE TIMING-PC AND PD
(MeR 5 = 1, MeR 6 = 1, MeR 7 = 1)
2 MHz
1 MHz
SYMBOL
PARAMETER
MIN
MIN
MAX
MAX
225
-
-
225
-
140
(PO) Data Setup Time
50
35
-
T P8HR
(PO) Data Read Hold Time
10
10
-
T pBHW
(PO) Data Write Hold Time
30
-
30
-
T pBOO
(PO) Data Output Delay
-
175
-
150
TPCHA
(PCO·PC4, PCS) Address Hmo Time
30
-
30
T pBHA
(PO) Address Hold Time
10
100
10
TpcHR
(PC5) R/W Hold Time
30
-
30
-
T pcHv
(PC7) EMS Hold Time
10
-
(PC7) Address to EMS Delay Time
30
T pcvp
(PC7) EMS Stabilization Time
30
-
10
T pcva (0
T ESU
EMS Set Up Time
-
350
T pcRs
(PC5) R/W Setup Time
T pcAS
(PCO·PC4, PCS) Address Setup Time
-
T pBAS
(PO) Address Setup Time
T pBSU
225
140
140
80
30
-
30
-
-
210
NOTE 1: Values assume PCQ-PC4, peG and PC7 have the same capacitive load.
F.3.1 Multiplex Mode Timing Diagram
READr-______________ 1
WRITE
1,...------_____
RIW
(PCS)
1 - - - -••1 TPCRS
-TPCHV
EMS
(PC-7)
TESU
TPCVP
TPCHAPCo-PC4,
PCS
-
_TPBHA
PDDPD7
TPBAS
--TPCVP
TPBHR
3-231
TPBHW
R65F11 • R65F12
FORTH Based Microcomputers
F.4 I/O, EDGE DETECT, COUNTERS, AND SERIAL I/O TIMING
SYMBOL
PARAMETER
Internal Write to Peripheral Data Valid
T pow (1)
T CMOS(l)
PA, PB TTL
PA, PBCMOS
T posu
Peripheral Data Setup Time
PA,PB
T PHR
Peripheral Data Hold Time
PA,PB
TEPW
PAO-PA3 Edge Detect Pulse Width
Tcpw
Tco(1)
Counters A and B
PA4, PA5 Input Pulse Width
PA4, PA5 Output Delay
1
MIN
MHz
MAX
t -
500
1000
2
MIN
MHz
MAX
-
500
1000
200
-
200
75
-
75
-
Tcyc
Tcyc
-
Tcyc
-
Tcyc
-
-
500
-
-
500
Port B Latch Mode
TpBLW
T plsu
T pBlH
PAO Strobe Pulse Width
PB Data Setup Time
PB Data Hold Time
Serial
T pow (1)
TCMosl1J
Tcpw
T pow (1)
TCMOS(ll
PA6
PA6
PA4
PA4
PA4
VO
Tcyc
175
30
-
Tcyc
150
30
-
XMTRTTL
500
XMTR CMOS
1000
RCVR SIR Clock Width
4 Tcyc
4 Tcyc XMTR Clock-SIR Mode (TTL)
500
XMTR Clock-SIR Mode (CMOS)
1000
-
NOTE 1: Maximum Load CapacHance: 50pF Passive Pull-Up Required.
3-232
-
500
1000
500
1000
R65F11. R65F12
FORTH Based Microcomputers
F.4.1 1/0 Edge Detect, Counter, and Serial 110 Timing
/
PA()'PA7
PBO·PB7
PCO·PC7
PDO·PD7
..
TCYC
.I"
1.5V
1.5V\
..
TPDSU
>t
L-
..
I
t
I.".---.l
TPHR
EDGE DETECTS
(PAD·PA3)
)
K
o
TEPW
CNTR
PA4,PA5
~1.5V
1.SV-l
..
TCPW
TCD
CNTR
(PA4, PA5)
1.5V]
~
TCPW
2.4V
O.4V
TCMOS
PAO·PA7
TPDW
2.4V
VDD-30%1
I
PBO·PB7
O.4V
PB
(LATCH MODE)
PAO STROBE
1.5V
1.5V
1------ T p B L W - - - - - - + i
........
3·233
',.
,
FORTH Based Microcomputers
R65F11 • R65F12
APPENDIX G
INCLUDED FORTH FUNCTIONS IN ROM
BANKEXECUTE
EEC!
?
D.R
#>
IN IT
DISK
Mob
MI
DABS
S->D
BLANKS
EXPECT
COUNT
SPACE
<
2PAD
IN
UPAD
TIB
2
I
+!
SWAP
DNEGATE
0<
>R
RP!
OR
CMOVE
EMIT
(DO)
BRANCH
BANKEEC!
#S
<#
DWRITE
MlMOD
I
M*
ABS
COLD
ERASE
(.")
DECIMAL
PICK
U<
1C/L
CLD/WRM
UC/L
BL
1
C@
BOUNDS
2DROP
NEGATE
0=
LEAVE
SP!
AND
CR
ENCLOSE
(+LOOP)
EXECUTE
BANKC@
.R
#
SPACES
DREAD
*1
IMOD
BANKe!
D.
SIGN
SEEK
SELECT
*/MOD
MAX
D+(NUMBER)
FILL
-TRAILING
HEX
ROT
*
MIN
+HOLD
QUERY
TYPE
-DUP
>
2+
HLD
BASE
RO
1+
DPL
UR/W
SO
4
3
0
@
2DUP
DROP
D+
R
;S
SP@
C!
TOGGLE
DUP
OVER
+
R>
RP@
XOR
U·
KEY
DIGIT
OBRANCH
LIT
UI
?TERMINAL
(FIND)
(LOOP)
CLiT
3-234
R85FRx • R65FKx
'1'
R65FRx and R65FKx
RSe FORTH
Development and Kernel ROMS
Rockwell
INTRODUCTION
FEATURES
The Rockwell Single Chip (RSC) FORTH System can be configured using the R65F11, R65F12 microcomputers or the
R6501Q ROM-less microcomputer. One of these microcomputers, when used in conjunction with a development ROM and
a FORTH kernel ROM, provide the designer with maximum flexibility when developing FORTH applications.
•
R65FR1 FORTH Development ROM
-8K ROM
-Addressable from $2000 through $3FFF in FORTH development configuration memory map
-R65F11 and R65F12 compatible
-Operates in the R65F111F12 FORTH development
configuration
•
R65FR2 FORTH Development ROM
-8K ROM
-Addressable from $4000 through $5FFF in the FORTH
development configuration memory map
-R6501 Q compatible for use in emulation of the R65F111F12
FORTH development configuration
•
R65FR3 FORTH Development ROM
-8K ROM
-Addressable from $COOO through $DFFF in the FORTH
development configuration memory map
-Operates in the' R6501Q FORTH development
configuration
RSC-FORTH is based on the popular fig-FORTH model with
extensions. The R65F11 and R65F12 both have the kernel of
the high level Rockwell Single Chip RSC-FORTH language contained in the preprogrammed ROM. The R65FK2 and R65FK3
Kernel ROMs are preprogrammed ROMs for use with the
R6501Q when developing larger applications requiring more
memory and 1/0 line support. All of the run time functions of the
RSC-FORTH are contained in these ROMs, including 16- and
32-bit mathematical, logical and stack manipulation, plus
memory and inpuVoutput operators. The RSC-FORTH Operating
System allows an external user program written in RSC-FORTH
or Assembly Language to be executed from external EPROM,
or development of such a program under the control of the
R65FR1, R65FR2 or R65FR3 RSC-FORTH Development ROMs.
• R65FK2 FORTH Kernel ROM
-4K ROM
-Addressable from $F400 through $FFFF in the FORTH
development configuration memory map
-R6501 Q compatible for use in the emulation of the
R65F11/F12 FORTH development configuration
-Replaces the FORTH kernel contained in the R65F11 and
R65F12 microcomputers during development
This document describes five different RSC-FORTH system configurations using the development and kernel ROMs.
ORDERING INFORMATION
Part No.
R65FRIP
R65FR2P
R65FR3P
R65FK2P
R65FK3P
R65FllP
R65Fl1AP
R65F12Q
R65F12AQ
R650W
R6501AQ
Description
FORTH Development ROM for R65Fll or R65F12
FORTH Development ROM for R6501Q
FORTH Development ROM for R6501Q
FORTH Kernel ROM for R6501Q
FORTH Kernel ROM for R650W
40-Pin FORTH Based Microcomputer at 1 MHz
40-Pin FORTH Based Microcomputer at 2 MHz
64-Pin FORTH Based Microcomputer at 1 MHz
64-Pin FORTH Based Microcomputer at 2 MHz
64-Pin One-Chip Microprocessor at 1 MHz
64-Pin One-Chip Microprocessor at 2 MHz
Order No.
2145
2146
2148
2162
• R65FK3 FORTH Kernel ROM
-4K ROM
-Addressable from $F400 through $FFFF in the FORTH
development and production configuration memory maps
-R6501Q compatible
-Operates in the R6501 Q FORTH development and production configurations
RSC-FORTH SYSTEM CONFIGURATIONS
The three configurations of the RSC-FORTH System are identified by the CPU-Development ROM combinations listed below:
Description
RS501 Q One-Chip Microprocessor Product
Description
R65Fl1 and R65F12 FORTH Based Microcomputer
Product Description
RSC-FORTH User's Manual
Application Note: A Low-Cost Development Module
for the R65Fll FORTH Microcomputer
Document No. 29651N80
RSC-FORTH System Configurations
CPU
Kernel
ROM
Development
ROM
RSC
Configuration
R65Fll
R65F12
R6501Q
R6501Q
none
none
R65FK2
R65FK3
R65FRI
R65FRI
R65FR2
R65FR3
1
1
2
3
Product Description
3-235
Order No. 21n
Rev. 1, June 1987
R65FR1
RSC FORTH ROMs
RSC·FORTH CONFIGURATION 1 (R65FR1)
R65F11/R65F12 DEVELOPMENT AND PRODUCTION
Although programs may reside in the upper BK bytes of memory
area, normally filled by the R65FR1 Development ROM, it is difficult to develop code for that area using this configuration of
the RSC-FORTH System.
The RSC-FORTH Configuration 1 provides the designer with a
FORTH development and application environment at a minimal
cost. The application program is developed using an R65F11
or R65F12 microcomputer, an R65FR1 Development ROM and
external RAM. Up to BK bytes of RAM space is available using
this configuration. However, Configuration 1 is limited to 5K or
less bytes of RAM during development. This is the result of
allocating 2K bytes of RAM for disk buffers and at least 1 K bytes
of RAM for the "Program heads". The program heads are contained in a dictionary containing the Name (NFA), Link Field
Address (LFA) and the Parameter Field Address Pointer (PFA).
This dictionary is a list of FORTH word words and user-defined
FORTH words used in the development of a FORTH program
and is not present during the execution of the FORTH program.
The difference in using the R65F11 or the R65F12 is in the
number of 1/0 lines available to the user. The R65F11 supports
16 1/0 lines, the R65F12 supports 40 1/0 lines.
Figure 1 shows the development and production configurations
for the R65F11/F12. Configurations 1A and 1B list the features,
memory maps, and the relationship of the R65F11 and R65F12
to the R65FR1 Development ROM in the development and production environment.
APPLICATION
DEVELOPMENT
RAM
",OK BYTES
APPLICATION
EPROM
",OK BYTES
R65F11!
R65F12
MICROCOMPUTER
R65F11!
R65F12
MICROCOMPUTER
R65FR1
DEVELOPMENT
ROM
OK BYTES
APPLICATION
RAM
(OPTIONAL)
DEVELOPMENT
Figure 1.
PRODUCTION
R65FR1 Configuration 1 Block Diagram
3-236
R65FR1
RSC FORTH ROMs
CONFIGURATION 1A CONSIDERATIONS
CONFIGURATION 1B CONSIDERATIONS
Features
• 8K Bytes of User Memory
• 16 I/O Lines
Features
• 8K Bytes of User Memory
• 40 1/0 Lines
Device Configuration
Device Configuration
DEVELOPMENT PRODUCTION
DEVELOPMENT PRODUCTION
R65F11 Microcomputer
R65F12 Microcomputer
R65FR1 Development ROM
R65FR1 Development ROM
User Memory-I/O Resource Matrix
User Memory-I/O Resource Matrix
User memory may be a mix of ROM, EEROM, UVPROM or
RAM.
User memory may be a mix of ROM, EEROM, UVPROM or
RAM.
48K
1
1
II
1
48KI
MEMORY
MEMORY
16K
16K
8K
8K
0
0
0
16
110 LINES
32
1/0 LINES
~'F9
Memory Map
40
0
40
-F9
Memory Map
KERNEL
FOOD
FOOD
t"'
4000
{
4000
R65FR1
MUX BUS
2000
USER MEMORY
0000
3-237
{
R65FR1
2000
USER MEMORY
0000
RSC FORTH ROMs
R65FR2 • R65FK2
RSC·FORTH CONFIGURATION 2
(R65FR2, R65FK2)
Using this configuration, the application program can be developed using the R650l Q and then later installed in an R65Fll
or R65F12 microcomputer without modification.
R65D1Q DEVELOPMENT AND R65F111F12
PRODUCTION
Figure 2 shows the development and production configuration
for the R6501Q. Configurations 2A and 2B list the features,
memory maps, and the relationship of the R6501Q to the
R65FR2 Development ROM and R65FK2 Kernel ROM in the development and production environment. Figure 3 is a schematic of the R6501Q, R65FR2, R65FK2 development setup
designed to plug into a 40 pin socket in place of the R65Fll.
The RSC-FORTH Configuration 2 provides the designer with the
capability of using the full 16K bytes of external address space
of the R65Fll and R65F12.
The R6501Q ROM-less microprocessor, when used with the
R65FK2 Kernel ROM and the R65FR2 Development ROM, emulates the operation of the R65Fll/F12. Because of the greater
address space of the R650l Q, the R65FR2 Development ROM
can be relocated to address $4000 and the disk buffers and
HEADS program to $6000. This expands the available user
memory space to 16K bytes, $0000 through $3FFF.
--=>
:)
R6501Q
MICROPROCESSOR
K=
DISK AND
HEADS RAM
sSK BYTES
R65FR2
DEVELOPMENT
ROM
BK BYTES
r:)
R65FK2
KERNEL
ROM
3K BYTES
:>
~
Note: Ports E, F and G of the R65F12 are not present on the
R6501Q and must be emulated by external TIL logic. Contact
Rockwell for further information.
R65Fl11
R65F12
MICROPROCESSOR
APPLICATION
DEVELOPMENT
RAM
s16K BYTES
Figure 2.
/-
'\,--
~
L-.yI
DEVELOPMENT
PRODUCTION
R65FR2 and R65FK2 Configuration 2 Block Diagrams
3-238
APPLICATION
EPROM
s16K
APPLICATION
RAM
16K BYTES
RSC FORTH ROMs
R65FR2 • R65FK2
CONFIGURATION 2A CONSIDERATIONS
CONFIGURATION 28 CONSIDERATIONS
Features
• 16K Bytes of User "Headerless" Memory
• 16110 Lines
Features
• 16K Bytes of User "Headerless" Memory
• 40 1/0 Lines
Device Configuration
Device Configuration
DEVELOPMENT PRODUCTION
DEVELOPMENT PRODUCTION
t/
R65F11 Microcomputer
t/
R65F12 Microcomputer
R6501 Q Microprocessor
t/
R6501Q Microprocessor
t/
R65FR2 Development ROM
t/
R65FR2 Development ROM
t/
R65FK2 Kernel ROM
t/
R65FK2 Kernel ROM
t/
Memory-I/O Matrix
Memory-I/O Matrix
If floppy disk is used in the application, space for the disk buffers must be allocated in memory from $0500 through $3FFF
or $6000 through $7FFF. User memory can be a mix of ROM,
EEROM, UVROM or RAM.
If floppy disk is used in the application, space for the disk buffers must be allocated in memory $0000 through $3FFF. User
memory can be a mix of ROM, EEROM, UVROM or RAM.
48K.----------------,
1
MEMORY
MEMORY
16K
16K
8K
8K
32
16
16
40
110 LINES
Memory Maps
R65FK2
FFF
Fn
F400
6000
1
FFFF~
1
F400
KERNEL
DEVELOPMENT
FFFF.r9.
8000
8K USER RAM
(HEADS)
6000
R65FR2
4000
0000
40
Memory Maps
PRODUCTION
DEVELOPMENT
8000
32
1/0 LINES
USER
MEMORY
(CODES ONLy)
PRODUCTION
FFFF~
8K USER RAM
(HEADS)
R65FR2
40001------1
USER
MEMORY
0000 (CODES ONLY)
4000
2000
3-239
USER
MEMORY
(CODES ONLY)
4000 1-----------1
USER
MEMORY
0000 (CODES ONLY)
iC1I
+5V
121
c:
en
m
.1>0
C
"
Z
c
:;:;
c..
c:
==
"m
pce
4
PCl 5
PC2 6
PC3 7
PC4 8
PC5 9
PC6 10
PC7 11
PD71-1.2
PD6 13
PD5 14
PD4 15
o
CI>
UI
...
"TI
en
oo
E
8KRAM
::D
Q)
C1I
"11
~
60
61
5
-4
3
2
...c:
~
8!------J
UI
63
62
o
51 Vcc~
"
NMI 22
23
en PA7 23 32
i
"z
f¥.----¥.34
!!l""PA4~
PA3 27
36
PA2 28
37
pee
v..v..
ADDRESS BUS
DATA BUS
oc:
j
_
29
30
31
32
33
34
35
36
37
38
39
40
D7
D6
D5
D4
D3
D2
Dl
De
~
PA6
PAS L!5
PAl
PAG
PB7
PB6
PBS
PB4
PB3
PB2
PBl
•
24
55
56
57
58
59
oo
:D
:a
I\)
+5V
54
Z
-I
2KRAM
41
42
45
a
"Ii)
E
o
...
1
2
3
PD3
~ PD2 17
64
"
PDl 18
_ PDe 1 19
ZRES 2 0 6
:D
'"~
c..
XTLO
XTLI
02
"11
....... WE
A15 r.i;;,-----'-1
A13m----,
38
39
24
25
26
27
28
29
30
31
43
EMS
~~====~~=----L~
441
L.._~_~
44
US
U6
U7
74LS04
74LS10
74LSOO
+5V
GND
14
14
14
7
7
7
NOTES
Pin 22 on R6501Q-Sync Signal not connected.
When emulating a R65F12 system Ports E, F or G
must be constructed externally using TTL circuits
, (contsct Rockwell).
:II
fJ)
o
"11
o
:a
-I
:::J:
:a
Figure 3.
R6501Q, R6SFR2 and R6SK2 Application Configuration Schematic
o
s:
tn
RSC FORTH ROMs
R65FR3 • R65FK3
RSC-FORTH CONFIGURATION 3
(R65FR3, R65FK3)
CONFIGURATION 3 CONSIDERATIONS
Features
• R6501 Q w/FORTH
• 48K Bytes of User Memory
• 30 I/O Lines
R6501 Q BASED SYSTEM DEVELOPMENT
AND PRODUCTION
The RSC-FORTH Configuration 3 is designed for those applications which require a larger amount of ROM or RAM space than
the R65F11 or R65F12 can provide.
Device Configuration
DEVELOPMENT PRODUCTION
In the development configuration, the user is provided with up
to 48K bytes of memory. The user memory is located from $0000
through $BFFF. The program heads will use some of this area
but the user will still have considerably more memory space
available then in the previous configurations.
The production configuration provides up to 56K bytes of user
memory. This is due to the fact that the R65FR3 Development
ROM, used in the development configuration, is not required
in the production configuration and releases the 8K bytes of
memory space. This memory is located at $COOO through
$DFFF.
R65010
MICRO·
PROCESSOR
V'-Iv
~
--=:>
r/
R65FK3 Development ROM
r/
R65FR3 Kernel ROM
r/
r/
r/
User Memory-I/O Resource Matrix
All ports act as I/O ports. Memory is on the bus. PC6 & PC7
(I/O lines) are assigned to memory. User memory can be a mix
of ROM, EEROM, UVPROM or RAM.
Figure 4 shows the development and production configurations
for the R6501 a. Configuration 3 lists the features, memory maps,
and the relationship of the R6501 Q to the R65FR3 Development
ROM and the R65FK3 Kernel ROM in the development and production environment.
,.--"\
-,.I
R6501 Q Microcomputer
R65FR3
DEVELOPMENT
ROM
8K BYTES
MEMORY
R65FK3
KERNEL
ROM
4K BYTES
110 LINES
APPLICATION
DEVELOPMENT
RAM
s48K BYTES
Memory Maps
PRODUCTION
DEVELOPMENT
DEVELOPMENT
FFFF
FOOO
R65FK3
KERNEL
ROM
FFFF
R65FK3
R65FK3
FOOO
AVAILABLE
AVAILABLE
E107
E107
FLOPPY CONTROL
EOOO
EOOO
R6501Q
MICROPROCESSOR
FLOPPY CONTROL
R65FR3
COOO
APPLICATION
RAM
USER
MEMORY
USER
MEMORY
s56K BYTES
PRODUCTION
oool
Figure 4. R65FR3 and R65FK3
Configuration 3 Black Diagrams
J
00001
J
Note: Chip select for the Floppy Disk Controller should be at $EOOQ-$EOO6
and at $E100-$E106 for this configuration.
3-241
fiSC FORTH ROMs
R65FRx • R65FKx
NC
A12
A7
A6
AS
A4
A3
A2
A1
AO
00
01
02
GNO
2
3
4
5
6 R65FR1
OR
7
R65FR2
8
OR
9 R65FR3
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
NC
NC
A7
A6
AS
A8
A9
A11
OE
A10
A4
A3
A2
A1
AO
00
01
02
CS
07
06
05
04
03
GNO
2
3
4
5
6
7
8
9
10
11
12
RSC·FORTH ROM Pin Assignments
3-242
24
23
22
21
20
R65FK2 19
OR
18 ,
R65FK3 17
16
15
13
14
VCC
A8
A9
A11
OE
A10
CS
07
06
05
04
03
RSC FORTH ROMs
R65FR2 • R65FK2
ABSOLUTE MAXIMUM RATINGS·
R65FR1,R65FR2,R65FR3,R65FK2,R65FK3
Parameter
Value
Unit
Vee
-0.5 to +7.0
V
-0.5 to + 7.0
Symbol
Supply Vollage
V
Input Voltage
VIN
Operating Temperature Range
TA
Storage Temperature
TST
-65 to + 150
DC
Power Dissipation
Po
1.0
W
Oto + 70
'NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device atr these or any other conditions above
those indicated in the other sections of this document is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
DC
OPERATING CONDITIONS
Parameter
Range
Vee Power Supply
5.0V ± 50Al
Operating Temperature
O°C to 70 0
D.C. CHARACTERISTICS
Vee = 5.DV ± 5%, TA = DOG to + lOoG (unless otherwise specified)
Symbol
Min
Typ
Max
Units
VOH
Output High Voltage
R65FRx
R65FKx
Parameter
2.4
-
Vee
V
Vee = 4.75V
10H = -400 pA
10H = -240pA
Test Conditions
VOL
Output Low Voltage
R65FRx
R65FKx
-
-
0.4
V
Vee = 4.75V
10L = 3.3 mA
10L = 2.1 rnA
VIH
Input High Voltage
2.0
-
Vee
V
VIL
Input Low Voltage
-0.5
-
0.8
V
III
Input Load Current
pA
Vee = 5.25V, OV SVIN 5.25V
Output Leakage Current
-
10
ILO
-
±10
pA
Chip Deselected,
Vee = 5.25V, VOUT = +0.4V to Vee
Icc
Power Supply Current
R65FRx
R65FKx
25
80
55
135
rnA
rnA
-
7
pF
Vee = 5.0V, Chip Deselected,
pin under test at OV
-
10
pF
Vee = 5.0V, Chip Deselected,
pin under test at OV
Vee = 5.25V @ O°C
CI
Input Capacitance
-
Co
Output Capacitance
-
3-243
Section 4
16-Bit Microprocessors and Peripherals
Page
Product Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-2
R68000 16-bit Microprocessing Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3
R68C552 Dual Asynchronous Communications Interface Adapter (DACIA) . . . . . . . . ..
4-62
R68560 Multi-Protocol Communications Controller (MPCC) . . . . . . . . . . . . . . . . . . . . . ..
4-83
II
4-1
16-Bit Microprocessor and Peripherals
Meeting System Communications Needs
It is available to work with either a 16·bit or 8·bit bus and can
be adapted to function with essentially any of today's more
common busses.
The R68C552 Dual Asynchronous Interface Adapter
(DACIA) provides an easily implemented, programmed con·
trolled interface between 16·bit microprocessor·based sys·
tems and serial communication data sets and modems. This
device is the first CMOS ACIA in the industry.
Rockwell lets you build efficient and economical16·bit sys·
tems through families of 16·bit and 8·bit peripherals, all com·
patible. No other company offers you more.
Rockwell peripherals give a designer the communication .
control elements for the 68000 processor. They allow you to
design functional systems utilizing all the speed and data
handling potential of the 16·bit 68000 family.
These peripherals consist of the Rockwell designed
Multi·Protocol Communications Controller and the Dual
Asynchronous Interface Adapter - each a significant "first"
that eliminates "glue parts" between a CPU and peripherals.
The R68561 Multi·Protocol Communications Controller
(MPCC) is one of the highest throughput communications
devices ever commercially made. It operates up to
4 Mbits/sec and supports all major communication protocols.
R6S000/R6S00 Peripheral Migration
4-2
'1'
R68000
16-Bit Microprocessing Unit (MPU)
Rockwell
DESCRIPTION
The R68000 offers seventeen 32-bit registers in addition to the
32-bit program counter and a 16-bit status register. The first eight
registers (DO-D7) are used as data registers for byte (8-bit), word
(16-bit), and long word (32-bit) data operations. Th~ second set
of seven registers (AO-A6) and the system stack pOinter may be
used as software stack pointers and base address registers. In
addition, these registers may be used for word and long .word
address operations. All 17 registers may be used as Index
registers.
The R68000 microprocessor is designed for high performance
where operational computation and versatility is required. The
R68000 provides powerful mass-memory handling capability and
architectural features designed to fit the broad range of 16-bit
needs. The Rockwell family of 16-bit products also includes a
wide range of peripherals that will allow complete system design
and manufacture.
FEATURES
16 15
87
•
•
•
•
•
•
O.
00
01
02
03 EIGHT
04 OATA
REGISTERS
05
06
07
31
• 16-Bit Data Bus
• 23-Line Address Bus
• 32-Bit Data and Address Registers Including:
- Eight General Purpose Data Registers
- Seven Address Registers
- Two Stack Pointers (User, Supervisory)
•
•
•
•
•
•
0
~~
SEVEN
AOORESS
REGISTERS
A7 TWO STACK
POINTERS
o
31
15
87
o
•
PROGRAM
COUNTER
•
STATUS
REGISTER
SYSTEM BYTE USER BYTE
•
•
R6S000 Registers
Document No. 68650N01
16M byte (8M word) Linear Addessing Range
14 Operand Addressing Modes
56 Powerful Instruction Types
Instruction Set Supports Structured High-Level Languages
Pipelining Instruction Execution
32-Bit Program Counter
All 17 Registers Can Be Index Registers
Memory Mapped Peripheral Devices
Vector Generated Exception Processing
Seven Unique Autovectors for Interrupt Service Routines
Trace Mode for Software Debugging
Operations Occur on Five Main Data Types
-Bit
-BCD
- Byte
-Word
- Long Word
Asynchronous and Synchronous Peripheral Interface
Capability
Many Peripheral Chips Available
- R68560/R68561 Multi-Protocol Communications Controller (MPCC)
Local Network Controller (LNET)
- R68S02
- R68C552
Dual Asynchronous Communications
Interface Adapter (DACIA)
Up to 12.5 MHz Input Clock
+ 5 VDC Power Supply
Product Description
4-3
Order No. 700
Rev. 6, May 1985
16-Bit MPU
R68000
04
03
02
01
00
AS
UOS
[OS
RiW
OTACK
BG
BGACK
BR
VCC
ClK
GNO
HALT
RESET
VMA
E
VPA
BERR
IPL2
IPl1
IPlO
FC2
FC1
FCO
A1
A2
A3
A4
05
06
07
OB
09
010
011
012
013
014
015
GNO
A23
A22
A21
~
1.
~
M
03
2
63
3
62
02
01
4
61
00
5
60
AS
6
59
UOS
7
58
lOS·
8
57
RiW
9
56
OTACK
10
55
BG
11
54
BGACK
12
53
BR
13
52
VCC
14
51
ClK
15
50
GNO
16
49
HALT
17
48
18
47
RESET
VMA
19
46
20
45
E
VPA
21
44
22
43
BERR
IPL2
23
42
IPL 1
24
41
IPlO
25
40
FC2
26
39
FC1
27
38
FCO
28
37
A1
29
36
A2
30
35
A3
31
34
A4 --0....:;3:.2_ _ _ _ _ _ _---=33=-..--
VCC
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
06
07
08
09
010
011
012
013
014
015
GNO
A23
A22
A21
VCC
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
AB
A7
A6
AS
R68000Q Pin Assignments-64-Pin QUIp·
R68000C/P Pin Asslgnments-64-Pin DIp·
ORDERING INFORMATION
OTACK
~
BGACK
BR
VCC
ClK
GNO
GNO
Part Number:
R68000
[
Temperature Range (TL to TH) and
Screening/Burn-in
Blank = DoC to 70°C
M = -55°C to 125°C
R = -55°C to 125°C and burned-in 168 hours
B = - 55°C to 125°C and screened to
MIL-STD 883B
Frequency
6
6 MHz
8 = 8 MHz
10 = 10 MHz
12 = 12.5 MHz
o
PIN 1
INOICATOR
(PCC ONLY)
~
(HALT
REJIEI
VMA
---E
....lleA
B.!ffi8
=
IfU
IPl1
Package
C = 64-Pin Ceramic DIP
P = 64-Pin Plastic DIP
Q = 64-Pin Plastic QUIP
J = 64-Pin Plastic Leaded Chip Carrier (PCC)
L = 64-Pin Leadless Ceramic
Chip Carrier (LCCC)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
013
014
015
GNO
GNO
A23
A22
A21
vce
A20
A19
A18
A17
A16
A15
A14
A13
R68000J/l Pin Assignments-68-Pln pce and lee·
·Pin Assignment package outlines are not actual size (refer to PACKAGE DIMENSIONS on pages 56-59).
4-4
R68000
16-Bit MPU
SIGNAL DESCRIPTION
Address Strobe (AS). The AS output indicates that there is a
valid address on the address bus.
The following paragraphs briefly describe the input and output
signals and also reference (if applicable) other paragraphs that
contain more detail about the function being performed. Bus
operation during the various machine cycles and operations is
also discussed. The input and output signals can be functionally
organized into the groups shown in Figure 1.
Read/Write (RiW). The RiW output defines the data bus transfer
as a read or write cycle. The Rm signal also works in conjunction
with the upper and lower data strobes as explained in the following paragraph.
Upper and Lower Data Strobes (UDS, LOS). The UDS and LOS
outputs control the data on the data bus, as shown in Table 1.
When the Rm line is high, the processor reads from the data
bus as indicated. When the Rm line is low, the processor writes
to the data bus as shown.
Note
The terms assertion and negation are used to avoid confusion when dealing with a mixture of "active-low" and
"active-high" signals. The terms assert, or assertion, indicates that a signal is active, or true, independent of
whether that voltage is low or high. The term negate, or
negation, indicates that a signal is inactive or false.
Data Transfer Acknowledge (DTACK). The DTACK input indicates that the data transfer is completed. When the processor
recognizes DTACK during a read cycle, data is latched and the
bus cycle terminated. When DTACK is recognized during a write
cycle, the bus cycle terminates. Refer to ASYNCHRONOUS
VERSUS SYNCHRONOUS OPERATION.
ADDRESS BUS (A1 THROUGH A23). This 23-bit, unidirectional,
three-state bus can address eight megawords of data. It provides the address for bus operation during all cycles except interrupt cycles. During interrupt cycles, address lines A 1, A2, and
A3 encode the interrupt level to be serviced while address lines
A4 through A23 are all set high.
BUS ARBITRATION CONTROL. These three signals form a bus
arbitration circuit to determine which device will be the bus
master device.
Bus Request (BR). The BR input indicates to the processor that
some other device desires to become the bus master. This input
can be externally ORed with all other devices that could be bus
masters.
DATA BUS (DO THROUGH 015). This 16-bit, bidirectional,
three-state bus is the general purpose data path. It transfers and
accepts data in either word or byte length. During an interrupt
acknowledge cycle, an external device supplies the vector
number on data lines 00-07.
Bus Grant (BG). The BG output indicates to all other potential
bus master devices that the processor will release bus control
at the end of the current bus cycle.
ASYNCHRONOUS BUS CONTROL. Asynchronous data
transfers are handled using the following control signals: address
strobe, readlwrite, upper and lower data strobes, and data
transfer acknowlege. These signals are explained in the following paragraphs.
VCC(2)
-
GNO(2)
ADDRESS
Table 1.
J.:
BUS) A1-A23
.APAT~
CLK
Bus Grant Acknowledge (BGACK). The BGACK input indicates
that some other device has become the bus master. This signal
cannot be asserted until the following four conditions are met:
1. a bus grant (8G) has been received,
2. address strobe (AS) is inactive which indicates that the
processor is not using the bus
~
AS
00-015
R/W
FCD
PRO{
CESSOR
STATUS
R6500
{
PERIPHERAL
CONTROL
SYSTEM {
CONTROL
FC1
FC2
UOS
R68000
MPU
E
LOS
ASYNCHRO} NOUS BUS
CONTROL
BUS
} ARBITRABG
TION
BGACK CONTROL
VPA
BERR
IPLO
RESET
'IPL1
HALT
IPL2
INTERRUPT
} CONTROL
'----
Figure 1.
-
UOS
LOS
RlW
08-015
00-07
High
High
-
No valid data
No valid data
Valid data bits
0-7
Low
Low
High
Valid data bits
8-15
High
Low
High
No valid data
Valid data bits
0-7
Low
High
High
Valid data bits
8-15
No valid data
Low
Low
Low
Valid data bits
8-15
Valid data bits
0-7
High
Low
Low
Valid data bits
0-7'
Valid data bits
0-7
Low
High
Low
Valid data bits
8-15
Valid data bits
8-15'
OTACK
BR
VMA
Data Strobe Control of Data Bus
'These conditions are a result of current implementation and may not
appear on future devices.
Input and Output Signals
4-5
10
16-Bit MPU
R68000
3. data transfer acknowledge (DTACK) is inactive which
indicates that neither memory nor peripherals are using the
bus, and
4. bus grant acknowledge (BGACK) is inactive which
indicates that no other device is still claiming bus mastersl:Jip.
R6500 PERIPHERAL CONTROL. These control signals are
used to allow the interfacing of synchronous RSSOO peripheral
devices with the asynchronous RSBOOO. These signals are
explained in the following paragraphs.
Enable (E). The E output signal is the standard enable signal
(02 clock) common to all R6S00 type peripheral devices. The
period for this output is ten R6BOOO clock periods (six clocks
low; four clocks high). Enable is generated by an internal ring
counter which may come up in any state (i.e., at power on, it
is impossible to guarantee phase relationship of E to ClK). E
is a free-running clock and runs regardless of the state of the
bus on the MPU.
INTERRUPT CONTROL (IPLO, IPL 1, IPL2). These input pins
indicate the encoded priority level of the device requesting an
interrupt. level seven is the highest priority while level zero indicates that no interrupts are requested. Level seven cannot be
masked. IPLO is the least significant bit while IPl2 is the most
significant bit. To insure an interrupt is recognized, the interrupt control lines (IPlX) must remain stable until the processor
signals interrupt acknowledge (FCO, FC1, and FC2 all high).
Valid Peripheral Address (VPA). The VPA input indicates that
the device or region addressed is a RSSOO family device and
that data transfer should be synchronized with the enable (E)
signal. This input also indicates that the processor should use
automatic vectoring for an interrupt. Refer to INTERFACE WITH
R6S00 PERIPHERALS.
SYSTEM CONTROL. The system control inputs either reset or
halt the processor or indicate to the processor that bus errors
have occurred. The three system control inputs are explained
in the following paragraphs.
Bus Error (BERR). The BERR input informs the processor that
a problem exists with the cycle currently being executed.
Problems may be a result of:
1. nonresponding devices,
2. interrupt vector number acquisition failure,
3. illegal access request as determined by a memory management unit, or
4. other application dependent errors.
Valid Memory Address (VMA). The VMA output indicates to
R6S00 peripheral devices that there is a valid address on the
address bus and that the processor is synchronized to enable.
This signal only responds to a valid peripheral address (VPA)
input which indicates that the peripheral is a R6S00 family device.
PROCESSOR STATUS (FCO, FC1 , FC2). These function code
outputs indicate the state (user or supervisor) and the cycle type
currently being executed, as shown in Table 2. The information
indicated by the function code outputs is valid whenever address
strobe (AS) is active.
The Bus Error (BERR) Signal interacts with the HALT signal to
determine if exception processing should be performed or the
current bus cycle should be retried.
CLOCK (CLK). The clock input is a TTL-compatible signal that
is internally buffered for development of the internal clocks
needed by the processor. The clock input should not be gated
off at any time and the clock signal must conform to minimum
and maximum pulse width times.
Refer to BUS ERROR AND HALT OPERATION paragraph for
additional information about the interaction of the bus error and
halt signals.
Reset (RESET). This bidirectional signal line acts to reset (initiate
a system initialization sequence) the processor and system in
response to an external reset signal. An internally generated
reset (result of a RESET instruction) resets all external devices
while not affecting the internal state of the processor. A total
system reset (processor and external devices) is the result of
external HALT and RESET signals applied simultaneously. Refer
to RESET OPERATION paragraph for additional information.
SIGNAL SUMMARY. Table 3 summarizes all the signals discussed in the previous paragraphs.
Table 2.
Halt (HALT). The bidirectional HALT line, when driven by an
external device, will cause the processor to stop at the completion of the current bus cycle. Halting the processor using HALT
causes all control signals to go inactive and all three-state lines
to go to their high-impedance state. Refer to BUS ERROR AND
HALT OPERATION paragraph for additional information about
the interaction between the HALT and BERR signals.
When the processor has stopped executing instructions, such
as in a double bus fault condition, the HALT line is driven by
the processor to indicate to external devices that the processor
has stopped. Refer to paragaph on Double Bus Faults.
4-6
Function Code Outputs
FC2
FC1
FCD
Cycle Type
Low
Low
Low
(Undefined, Reserved)
Low
Low
High
User Data
Low
High
Low
User Program
Low
High
High
(Undefined, Reserved)
High
Low
Low
(Undefined, Reserved)
High
Low
High
Supervisor Data
High
High
Low
Supervisor Program
High
High
High
Interrupt Acknowledge
16-Bit MPU
R68000
Table 3.
Signal Summary
HI-Z
Signal Name
Input/Output
Mnemonic
Active State
On HALT
On BGACK
Address Bus
AI-A23
Output
High
Yes
Yes
Data Bus
DO-DI5
Input/Output
High
Yes
Yes
Address Strobe
AS
Output
Low
No
Yes
ReadlWrite
RIW
Output
Read-High
Write-Low
No
Yes
Upper and Lower Data Strobes
UDS. LDS
Output
Low
No
Yes
Data Transfer Acknowledge
DTACK
Input
Low
No
No
Bus Request
BR
Input
Low
No
No
Bus Grant
BG
Output
Low
No
No
Bus Grant Acknowledge
BGACK
Input
Low
No
No
Interrupt Priority Level
IPLO. IPLI. IPL2
Input
Low
No
No
Bus Error
BERR
Input
Low
No
No
Reset
RESET
Input/Output
Low
No·
No·
Halt
HALT
Input/Output
Low
No·
No·
Enable
E
Output
High
No
No
Valid Memory Address
VMA
Output
Low
No
Yes
Valid Peripheral Address
VPA
Input
Low
No
No
Function Code Output
FCO. FCI. FC2
Output
High
No
Yes
Clock
CLK
Input
High
No
No
Power Input
VCC
Input
Ground
GND
Input
-
-
·Open drain.
REGISTER DESCRIPTION AND DATA
ORGANIZATION
OPERAND SIZE
STATUS REGISTER. The status register contains the eight level
interrupt mask as well as the condition codes; extend (X),
negative (N), zero (Z), overflow (V), and carry (e). Additional
status bits indicate that the processor is in a trace (T) mode
and/or in a supervisor (S) state.
Operand sizes are defined as follows: a byte equals 8 bits, a
word equals 16 bits, and a long word equals 32 bits. The operand
size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction operation. Implicit
instructions support some subset of all three sizes.
.
SYSTEM BYTE
15
13
10
DATA ORGANIZATION IN REGISTERS
USER , BYTE·
8 If
The eight data registers support data operands of " 8, 16, or
32 bits. The seven address registers together with the active
stack pointer support address operands of 32 bits.
01
4
I ~S ~12111110~X I I Ivic I
T
TRACE
~ODE I
SUPERVISOR
STATE
N Z
IN~T
MASK
I
DATA REGISTERS. Each data register is 32 bits wide. Byte
operands occupy the low order 8 bits, word operands the low
order 16 bits, and long word operands the entire 32 bits. The
least significant bit is addressed as bit zero; the most significant bit is addressed as bit 31. When a data register is used
as either a source or destination operand, only the appropriate
low-order portion is changed; the remaining high order portion
is neither used nor changed.
EXTE1NDI
NEGATIVE
ZERO
OVERFLOW
CARRY
·CONDITION CODE REGISTER
Status Register
4-7
D
R68000
16·Bit MPU
15
14
13
12
11
10
9
7
8
6
5
4
3
2
0
WORD ,00000
BYTE 000000
BYTE 000001
WORDtOOO02
BYTE 000002
BYTE 000003
WORD FFFFFE
I
BYTE FFFFFE
Figure 2.
BYTE FFFFFF
Word Organization In Memory
ADDRESS REGISTERS. Each address register and the stack
pointer is 32 bits wide and holds a full 32·bit address. Address
registers do not support byte sized operands. Therefore, when
an address register is used as a source operand, either the low
order word or the entire long word operand is used depending
upon the operation size. When an address register is used as
the destination operand, the entire register is affected regardless
of the operation size. If the operation size is word, any other
operands are sign extended to 32 bits before the operation is
performed.
The address and data buses are separate parallel buses which
transfer data using an asynchronous bus structure. In all cycles,
the bus master assumes responsibility for deskewing all signals
it issues at both the start and end of a cycle. In addition, the
bus master is responsible for deskewing the acknowledge and
data signals from the slave device.
The following paragraphs explain the read, write, and readmOdify-write cycles. The indivisible read-modify-write cycle is the
method used by the R68000 for interlocked multiprocessor
communications.
DATA ORGANIZATION IN MEMORY
Read·Cycle. During a read cycle, the processor receives data
from memory or a peripheral device. The processor reads bytes
of data in all cases, and for a word (or double word) operation,
the processor reads both upper and lower bytes simultaneously
by asserting both upper and lower data strobes. When the
instruction specifies byte operation, the processor uses an
internal AO bit to determine which byte to read and then issues
the data strobe required for that byte. When the AO bit equals
zero, the upper data strobe is issued, and when the AO bit equals
one, the lower data strobe Is issued. The processor correctiy
positions the received data internally.
Bytes are individually addressable with the high order byte
having an even address the same as the word, as shown in
Figure 2. The low order byte has an odd address that is one
higher than the word address. Instructions and multi-byte data
are accessed only on word (even byte) boundaries. If a long word
datum is located at address n (n even), then the second word
of that datum is located at address n + 2.
The data types supported by the R68000 are: bit data, integer
data of 8, 16, or 32 bits, 32-bit addresses and binary coded
decimal data. Each of these data types is put in memory, as
shown in Figure 3. The numbers indicate the order in which data
is accessed from the processor.
A word read cycle flow chart is given in Figure 4. A byte read
cycle flow chart is given in Figure 5. Read cycle timing is given
in Figure 6. Figure 7 details word and byte read cycle operations.
BUS OPERATION
Write Cycle. During a write cycle, the processor sends bytes
of data to memory or a peripheral device. If the instruction
specifies a word operation, the processor writes both bytes.
When the instruction specifies a byte operation, the processor
uses an internal AO bit to determine which byte to write and then
issues the data strobe required for that byte. When the AO bit
equals zero, the upper data strobe is issued and when the AO
bit equals one, the lower data strobe is issued. A word write cycle
flow chart is given in Figure 8. A byte write cycle flow chart is
given in Figure 9. Write cycle timing is given in Figure 6.
Figure 10 details word and byte write cycle operation.
The following paragraphs explain control signal and bus operation during data transfer operations, bus arbitration, bus error
and halt conditions, and reset operation.
DATA TRANSFER OPERATIONS. Transfer of data between
devices involves the following signals:
• Address Bus A 1 through A23
• Data Bus DO through 015
• Control Signals
4-8
16-Bit MPU
R68000
BIT DATA
1 BYTE = 8 BITS
7
5
6
o
2
3
4
INTEGER DATA
1 BYTE = 8 BITS
14
15
13
12
11
10
I MSB
7
8
9
BYTE 0
LSB
BYTE 2
6
5
4
I
3
2
0
2
0
BYTE 1
BYTE 3
1 WORD = 16 BITS
15
14
I·~
13
12
11
10
7
8
9
6
4
5
3
"'I
WORD 0
WORD 1
WORD 2
1 LONG WORD = 32 BITS
14
15
MSB
13
11
12
LONG WORD 0 -
10
-
-
--
LONG WORD 1 - -
-
LONG WORD 2 - -
-
-
-
-
-
-
-
4
5
3
0
2
-----LSB
- -
-----
-
-
6
HIGH ORDER
- - - LOW ORDER
-
-
7
8
9
-
-
-
---- -
-
-
-
-
-
-
-
ADDRESSES
1 ADDRESS
32 BITS
=
15
MSB
-
14
-
-
-
-
-
MSB
LSB
13
11
12
ADDRESS 0- -
-
ADDRESS 1- -
- ADDRESS 2 -
10
-
-
-
-
8
9
-
-
-
-
-
-
6
-
-
-
-
-
-
-
-
LSB
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
= MOST SIGNIFICANT BIT
= LEAST SIGNIFICANT BIT
DECIMAL DATA
2 BINARY CODED DECIMAL DIGITS
15
MSD
o
2
3
4
5
HIGH ORDER
LOW ORDER
-
-
7
14
13
12
11
10
9
BCD 0
BCD 1
BCD 4
BCD 5
8
7
LSD
6
= 1 BYTE
5
4
BCD 6
BCD 7
=
Data Organization In Memory
4-9
2
BCD 3
MSD
MOST SIGNIFICANT DIGIT
LSD = LEAST SIGNIFICANT DIGIT
Figure 3.
3
BCD 2
o
II
16-Bit MPU
R68000
BUS MASTER
SLAVE
BUS MASTER
ADDRESS DEVICE
1)
2)
3)
4)
5)
SLAVE
ADDRESS DEVICE
SET RlW TO READ
PLACE FUNCTION CODE ON FCO-FC2
PLACE ADDRESS ON A1-A23_
ASSERT ADDRESS STROBE (AS)_
ASSERT UPPER DATA STROBE (UDS) AND
LOWER DATA STROBE (LOS)
1)
2)
3)
4)
5)
,
SET RlW TO READ
PLACE FUNCTION CODE ON FCO-FC2
PLACE ADDRESS ON A1-A23_
ASSERT ADDRESS STROBE (AS)_
ASSERT UPPER DATA STROBE (UDS) OR
LOWER DATA STROBE (LOS) (BASED ON AO)
,
INPUT DATA
INPUT DATA
1) DECODE ADDRESS
2) PLACE DATA ON 00-015
3) ASSERT DATA TRANSFER ACKNOWLEDGE
(DTACK)
1) DECODE ADDRESS
2) PLACE DATA ON 00-07 or 08-015 (BASED ON
UOS OR LOS)
3) ASSERT DATA TRANSFER ACKNOWLEDGE
(OTACK)
I
1) LATCH DATA
2) NEGATE UDS AND LOS
3) NEGATE AS
ACQUIRE DATA
1) LATCH DATA
2) NEGATE UOS ORILDS
3) NEGATE AS
,
t
TERMINATE CYCLE
. 1) REMOVE DATA FROM 00-015
2) NEGATE,DTACK
TERMINATE CYCLE
1) REMOVE DATA FROM 00-015 OR 08-015
2) NEGATE OTACK
1
START NEtT CYCLE
Figure 4.
I
•
+
ACQUIRE DATA
I
START NEtT CYCLE
Figure 5.
Word Read Cycle Flow Chart
Read-Modify-Write Cycle. The read-modify-write cycle performs
a read, modifies the data in the arithmetic-logic unit, and writes
the data back to the same address. In the R68000 this cycle
is indivisible in that the address strobe is asserted throughout
the entire cycle. The test and set (TAS) instruction uses this cycle
to provide meaningful communication between processors in a
multiple processor environment. TAS is the only instruction that
uses the read-modify-write cycles. Since the test and set instruction only operates on by1es, all read-modify-write cycles are by1e
operations. A read-modify-write cycle flow chart is given in
Figure 11 and a timing diagram is given in Figure 12.
Byte Read Cycle Flow Chart
Figure 13 is a flow chart showing the detail involved in a request
from a Single device. Figure 14 is a timing diagram for the same
operation. This technique allows processing of bus requests during data transfer cycles.
The timing diagram shows that the bus request is negated at
the time that an acknowledge is asserted. This is true for a
system consisting of the processor and one device capable of
bus mastership. However, in systems having a number of
devices capable of bus mastership, the bus request line from
each device is ORed to the processor. In this system, it is easy
to see that there could be more than one bus request being
made. The timing diagram shows that the bus grant signals
negate a few clock cycles after the transition of the acknowledge
(BGACK) signal.
BUS ARBITRATION. Bus arbitration is a technique used by
master-type devices to request, be granted, and acknowledge
bus mastership. In its simplest form, it consists of:
However, if the bus requests are still pending, the processor will
assert another bus grant within a few clock cycles after negation. This additional assertion of bus grant allows external arbitration circuitry to select the next bus master before the current
bus master has completed its requirements. The following paragraphs provide additional information about the three steps in
the arbitration process.
1. asserting a bus mastership request,
2. receiving a grant that the bus is available at the end of the
current cycle, and
3. acknowledging that mastership has been assumed.
4-10
16-Bit MPU
R68000
ClK
~~~------~=~~--------~~~----------------~~
\~______~r----\
___-=~~--~r----\
;-UDS------\~______~r
~
I
lDS
\
Ir----~
I
AS
RiVi
I
\
DTACK~~~~~\~~~~~~/~~~~~\~~~~~/'~-~-~-~-~-~-~-~-~-~-~-~~~\~~~~~r>-
D8-D15
( )
)
DO-D7)
FCO-FC2
}-
J _______--'X'-_______...JX"--__________~>-
I. . .
_---READ,---.~_tl.....----WRITE--....,~
..
""I. .
Figure 6.
I------SLOW READ---..
~~I
Read and Write Cycle Timing Diagram
ClK
AO·
AS
UDS
lDS
RNi
DTACK
D8-D15
~~
FCO-FC2
\'---_ _~I
\
r--\
\
I
~~~~~~~~~~~;~~~~~~~/~~~\~~~~r--===
=:x
______
\
--J)---
(...._ _ _
)
~X'-
)
______~X'--------->__
·INTERNAl SIGNAL ONLY
~WORD READ-_"'~I""'''_-ODD BYTE READ ~
Figure 7.
I..
EVEN BYTE READ-+!
Word and Byte Read Cycle Timing Diagram
Receiving the Bus Grant. Normally the processor asserts bus
grant (BG) as soon as possible after internal synchronization. The
only exception occurs when the processor has made an internal decision to execute the next bus cycle but has not progressed
far enough into the cycle to have asserted the address strobe
(AS) signal. In this case, bus grant will not be asserted until one
clock after address strobe is asserted to indicate to external
devices that a bus cycle is being executed.
Requesting the Bus. External devices capable of becoming bus
masters request the bus by asserting the bus request (BR) signal.
This ORed signal (although it need not be constructed from open
collector devices) indicates to the processor that some external
device requires control of the external bus. The processor, at
a lower bus priority level than the external device, will relinquish
the bus after it has completed the last bus cycle it has started.
If no acknowledge is received before the bus request signal goes
inactive, the processor will continue processing when it detects
that the bus request is inactive. This allows ordinary processing
to continue if the arbitration circuitry inadvertently responded
to noise.
The bus grant signal may be routed through a daisy-chained
network or through a specific priority-encoded network. The processor is not affected by the external method of arbitration as
long as the protocol is obeyed.
4-11
16-Bit MPU
R68000
BUS MASTER
SLAVE
ADDRESS DEVICE
1) PLACE FUNCTION CODE ON FCO-FC2
2) PLACE ADDRESS ON A1-A23_
3) ASSEI!! ADDRESS STROBE (AS)
4) Sel R/W TO WRITE
5) PLACE DATA ON DO-D15
6) ASSERT UPPER DATA STROBE (UDS) AND
LOWER DATA STROBE (LDS)
1)
2)
3)
4)
5)
PLACE FUNCTION CODE ON FCO-FC2
PLACE ADDRESS ON A1-A23_
ASSEI!! ADDRESS STROBE (AS)
Sel RIW TO WRITE
PLACE DATA ON DO-D7 or D8-D15 (ACCORDING
TO AO)
6) ASSERT UPPER DATA STROBE (UDS) OR
LOWER DATA STROBE (LDS) (BASED ON AO)'
,
•
INPUT DATA
INPUT DATA
1) DECODE ADDRESS
2) STORE DATA ON DO-D15
3) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACK)
1) DECODE ADDRESS
2) STORE DATA ON DO-D7 If LDS IS ASSERTED
STORE DATA ON D8-D15 IF UDS IS ASSERTED
3) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACK)
,
I
•
TERMINATE OUTPUT TRANSFER
1) NEGATE UDS AND LDS
2) NEGATE AS
3) REMOV.E DATA FROM DO-D15
4) SET RIW TO READ
I
TERMINATE OUTPUT TRANSFER
1)
2)
3)
4)
•
NEGATE UDS OR LDS
NEGATE AS
REMOV.E DATA FROM DO-D7 OR D8-D15
SET RIW TO READ
TERMINATE CYCLE
1) NEGATE DTACK
I
t
•
TERMINATE CYCLE
1) NEGATE DTACK
+
START NEXT CYCLE
Figure 8.
SLAVE
BUS MASTER
ADDRESS DEVICE
START NEXT CYCLE
Word Write Cycle Flow Chart
Figure 9.
Byte Write Cycle Flow Chart
CLK
AO·
AS
====\---~=-----,.
UDS--~~'----1--~r--~======~---===~-~
~
LDS
------'----I
RiWf\,
DTACK
I
\
\
1\
I
r
~
(
)
====>-<~~~~~==~~~~~~==~~~~~
.J<'--______
)
DO-D7
D8-D15
FCO-FC2
'L--.I
1\
====>-<~
(
)
)
)
X
X
...J
·INTERNAL SIGNAL ONLY
f.--
WORD WRITE
Figure 10.
~
I..
ODD BYTE WRITE
~
I..
>
EVEN BYTE WRITE-.J
Word and Byte Write Cycle Timing Diagram
4-12
I
16-Bit MPU
R68000
,
BUS MASTER
SLAVE
-
ADDRESS DEVICE
1)
2)
3)
4)
5)
SET RIW TO READ
PLACE FUNCTION CODE ON FCO-FC2
PLACE ADDRESS ON A1-A23_
ASSERT ADDRESS STROBE (AS)_
ASSERT UPPER DATA STROBE (UDS) OR
LOWER DATA STROBE (LOS)
INPUT DATA
1) DECODE ADDRESS
2) PLACE DATA ON 00-07 OR 08-015
3) ASSERT DATA TRANSFER ACKNOWLEDGE
(DTACK)
I
•
•
ACQUIRE DATA
1) LATCH DATA
2) NEGATE UDS OR LOS
3) START DATA MODIFICATION
TERMINATE CYCLE
1) REMOVE DATA FROM 00-07 OR 08-015
21 NEGATE DTACK
I
t
•
START OUTPUT TRANSFER
INPUT DATA
1) STORE DATA ON 00-07 OR 08-015
2) ASSERT DATA TRANSFER ACKNOWLEDGE
(DTACK)
1) SET Rm TO WRITE
2) PLACE DATA ON 00-07 or 08-01_5_
3) ASSERT UPPER DATA STROBE (UDS) OR
LOWER DATA STROBE (LOS)
~
TERMINATE OUTPUT TRANSFER
1)
2)
3)
41
II
1
+
NEGATE UDS OR LOS
NEGATE AS
REMOVE DATA FROM 00-07 OR 08-015
SET RIW TO READ
TERMINATE CYCLE
1) NEGATE
DTACi<
I
,
START NEXT CYCLE
Figure 11.
AS
\
UDS OR LOS
\
Read-Modify-Write Cycle Flow Chan
/
\
I
\
RlW
\
(
DTACK
08-015
FCO-FC2
=X
I·
I
)
\
<
INDIVISIBLE CYCLE
Figure 12. Read-Modify-Wrlte Cycle Timing Diagram
4-13
r-r-
r-
>--x:::
-I
16-Bit MPU
R68000
The bus request from the granted device should be dropped after
bus grant acknowledge is asserted. If a bus request is still
pending, another bus grant will be asserted within a few clocks
of the negation of bus grant. Refer to Bus Arbitration Control
section. The processor does not perform any external bus cycles
before it reasserts bus grant.
REQUESTING DEVICE
PROCESSOR
REQUEST THE BUS
1) ASSERT BUS REQUEST
(SR)
t
I,
GRANT BUS ARBITRATION
") ASSERT BUS GRANT (BG)
1
I
BUS ARBITRATION CONTROL. The bus arbitration control unit
in the R68000 is implemented with a finite state machine. A state
diagram of this machine is shown In Figure 15. All asynchronous
signals to the R68000 are synchronized before being used internally. This synchronization is accomplished in a maximum of
one cycle of the system clock, assuming that the asynchronous
input setup time (#47) has been met (see Figure 16). The input
signal is sampled on the falling edge of the clock and is valid
internally after the next falling edge. If BR and BGACK meet
the asynchronous set-up time tASI (#47), then tBGKBR (#37A)
can be ignored. If BR and BGACK are asserted asynchronously
with respect to the clock, BGACK has to be asserted before BR
is negated.
t
ACKNOWLEDGE BUS MASTERSHIP
1) EXTERNAL ARBITRATION DETERMINES
NEXT BUS MASTER
2) NEXT BUS MASTER WAITS FOR CURRENT CYCLE TO COMPLETE
3) NEXT BUS MASTER ASSERTS BUS
GRANT ACKNOWLEDGE (BGACK) TO
TO BECOME NEW MASTER
4) BUS MASTER NEGATES BR
I
+
J
TERMINATE ARBITRATION
1) NEGATE BG (AND WAIT FOR
BGACK TO BE NEGATED)
•
As shown in Figure 15, input Signals labeled R and A are internally synchronized on the bus request and bus grant
acknowledge pins respectively. The bus grant output is labeled
G and the internal three-state control signal T. If T is true, the
address, data, and control buses are placed in a high-impedance
state when AS is negated. All signals are shown in positive logic
(active high) regardless of their true active voltage level.
I
OPERATE AS BUS MASTER
1) PERFORM DATA TRANSFER (READ AND
WRITE CYCLES) ACCORDING TO THE
SAME RULES THE PROCESSOR USES.
t
State changes (valid outputs) occur on the next riSing clock edge
after the internal signal is valid.
RELEASE BUS MASTERSHIP
1) NEGATE BGACK
I
•
RE-ARBITRATE OR RESUME
PROCESSOR OPERATION
Figure 13.
A timing diagram of the bus arbitration sequence during a
processor bus cycle is shown in Figure 17. The bus arbitration
sequence while the bus is inactive (i.e., executing internal operations such as a multiply instruction) is shown in Figure 18.
I
If a bus request (BR) is made at a time when the MPU has
already begun a bus cycle but AS has not been asserted (bus
state SO), BG will not be asserted on the next rising edge. Instead
BG will be delayed until the second rising edge following its internal assertion. This sequence is shown in Figure 19.
Bus Arbitration Cycle Flow Chart
Acknowledgment of Mastership. Upon receiving a bus grant
(BG), the requesting device waits until address strobe (AS), data
transfer acknowledge (DTACK), and bus grant acknowledge
(BGACK) are negated before issuing its own BGACK. The negation of the address strobe indicates that the previous master has
completed its cycle, while the negation of bus grant acknowledge
indicates that the previous master has released the bus. (If
address strobe is asserted no device is allowed to "break into"
a cycle.) The negation of data transfer acknowledge indicates
the previous slave has terminated its connection to the previous
master. In some applications data transfer acknowledge may
not be required. In this case the devices would use the address
strobe. When bus grant acknowledge is issued the device is bus
master. Only after the bus cycle(s) is (are) completed should bus
grant acknowledge be negated to terminate bus mastership.
BUS ERROR AND HALT OPERATION. In a bus architecture
that requires a handshake from an external device, the possibility
exists that the handshake might not occur. Since different
systems will require a different maximum response time, a bus
error input is provided.
External circuitry must be used to determine the duration
between address strobe and data transfer acknowledge before
issuing a bus error signal. When a bus error signal is received,
the processor has two options: initiate a bus error exception
sequence or try running the bus cycle again.
4-14
R68000
16-Bit MPU
CLK
LOS IUDS
_~~_-,I
~\~---,I
BG _ _ _
BGACK
,\~-------,I
\
_ _ _ _ _ _ _~\~----11
\~______________
!-- DMA DEVICE _I"
PROCESSOR-----1~~I..
-
PROCESSOR ___
Figure 14.
DMA DEVICE_
Bus Arbitration Cycle Timing Diagram
RA
INTERNAL SIGNAL VALIDl
EXTERNAL SIGNAL~
SAMPLED
, ,
CLK
I
BGACK------------~
"THIS DELAY TIME IS EQUAL TO PARAMETER #33, tCHGL
Figure 16. Timing Relationship of External
Asynchronous Inputs to Internal Signals
= BUS REQUEST INTERNAL
BUS GRANT ACKNOWLEDGE INTERNAL
= BUS GRANT
= THREE-STATE CONTROL TO BUS CONTROL LOGIC'
= DON'T CARE
1. STATE MACHINE WILL NOT CHANGE STATE IF BUS IS
IN SO OR S1. REFER TO BUS ARBITRATION CONTROL
FOR ADDITIONAL INFORMATION.
2. THE ADDRESS BUS WILL BE PLACED IN THE HIGH
IMPEDANCE STATE IF T IS ASSERTED AND AS
NEGATED.
R
A
G
T
X
Bus Error Operation. When BERR is asserted, the current bus
cycle is terminated. If BERR is asserted before the falling edge
of 82, A8 will be negated in 87 in either a read or write cycle.
As long as BERR remains asserted, the data and address buses
will be in the high-impedance state. When BERR is negated,
the processor will begin stacking for exception processing.
Figure 20 is a timing diagram for the exception sequence. The
sequence is composed of the following elements:
1. stacking the program counter and status register,
2. stacking the error information,
3. reading the bus error vector table entry, and
4. executing the bus error handler routine.
=
Figure 15.
State Diagram of R68000 Bus
Arbitration Unit
4-15
IJ
16-Bit MPU
R68000
BUS THREE STATED------,
BG ASSERTED
BR VALID INTERNAL
BR SAMPLED
BR ASSE~TED.
BUS RELEASED FROM THREE
STATE AND PROCESSOR
STARTS NEXT BUS CYCLE
BGACK NEGATED INTERNAL
BGACK SAMPLED
BGACK NEGATED
CLK
SO S1 S2 S3 S4 S5 S6 S7
BR
BG
/
\
BGACK
A1·A23
)
AS
\
UDS
LDS
FCO·FC2
R/W
===x
/
\
\
\
~
~
~
r--\,
~
c
(
\
'----l
..
>-C
(
~
!'
!'
!'
DTACK
DO·D15
SO S1 S2 S3 S4 S5 S6 S7 SO S1
/
\
~
(
PROCESSOR
.. I-
ALTERNATE BUS MASTER
.. I-
PROCESSOR
•
Figure 17. Bus Arbitration During Processor Bus Cycle
1
BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE----...,
BGACKNEGATED _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- .
BG ASSERTED AND BUS THREE STATED
BR VALID INTERNAL _ _ _ _ _ _ _---,
BR SAMPLED - - - - - - - - - ,
BR ASSERTED-------..
CLK
SO S1 S2 S3 S4
SO S1 S2 S3 S4 S5 S6 S7
~
\
/
BG------------------~======~\-J
OO~
\
UDS~
/r----~
LDS~
/
FCO·FC2
/
'-----'
--_----------------------C===
R/W - - - - - - - - - - - - - - - - - - - - - - - - - - - , ' - -__________________~-------
DTACK-------~'____!r---------------------,'___
DO·D15
-~===~(C===~)
=:-::-==---~==:::=-:::==_--__:===:_
PROCESSOR
• I.. BUS
INACTIVE .. 1..
ALTERNATE BUS MASTER
.. 1':ROCESSO~
Figure 18. Bus Arbitration with Bus Inactive
4·16
16-Bit MPU
R68000
BUS RELEASED FROM THREE
STATE AND PROCESSOR
STARTS NEXT BUS CYCLE - - - - ,
BGACK NEGATED INTERNAL
BGACK SAMPLED
BGACK NEGATED
BR ASSERTED
BR SAMPLED
BUS THREE sTATED'-----,
BG ASSERTED
BR VALID INTERNAL
SO Sl S2 S3 S4 S5 S6 S7 SO Sl
SO Sl S2 S3 S4 S5 S6 S7
/
BR\
BG
,
/
BGACK _ _ _ _ _ _ _===~\------J
/
;;====;r-c
_ ____Jr__
'------'
-==>---<2:j:;~===~)~=====----;::i;(
A1-A23
AS - . /
,'-_ _ _..JI''----------~'__
_ _ _....Jr__
~'-_ _ _-'r__
I'
,'-___.JI'
~\...
UDS - . / , - - - - - - . ,
LOS
FCO-FC2
-.-I
===x
C
Riw - - ' r - - - - - - - - ' -________J - - - - - - - - -
DTACK~::::~_~~~~'----!c======}-~~~~~~=_---';~~c===r--=====
I.
I.
00-015
..
PROCESSOR
Figure 19_
AS
..
ALTERNATE BUS MASTER
..
PROCESSOR
Bus Arbitration During Processor Bus Cycle Special Case
---'1
\'-_ _ _ _ _ _ _ _ _ _ _
\
jr-----"
LOS UDS - - - - - - , \
RIW
\
DTACK-----------------------00-015
FCO-2
BERR
\
=::::==i(~~~~~~~~~~~~~~~;t:=j
J=~===========\-------~ ~--========
\
HALT-------------~========~
I
, ",INITIATIi
READ ~ '"
I
I '"
INITIATE BUS
RESPONSE FAILURE --'''~''I-----BUS ERROR DETECTION --l'~~E=RR=O:"R::-S:=T':'A::.;C":'K'--ING
Figure 20_
Bus Error Timing Diagram
4-17
16-Bit MPU
R6S000
The single-step mode, derived from correctly timed transitions
on the HALT signal input, forces the processor to execute a
single bus-cycle by entering the "run" mode until the processor
starts a bus cycle then changing to the "halt" mode. Thus, the
single-step mode allows the user to proceed through (and
therefore debug) processor operations one bus cycle at a time.
The stacking of the program counter and the status register is
identical to the interrupt sequence. Several additional items are
stacked when a bus error occurs. These items are used to determine the nature of the error and correct it, if possible. The bus
error vector is vector number two located at address $000008.
The processor loads the new program counter from this location. A software bus error handler routine is then executed by
the processor. Refer to EXCEPTION PROCESSING for additional information.
Figure 22 details the timing required for correct single-step
operations. Some care must be exercised to avoid harmful interactions between BERR and HALT when using the single cycle
mode as a debugging tool. This is also true of interactions
between the HALT and RESET lines since these can reset the
machine.
Re·Running the Bus Cycle. When, during a bus cycle, the
processor receives a BERR, and HALT is being driven by an
external device, the processor enters the re-run sequence.
Figure 21 is a timing diagram for re-running the bus cycle.
When the processor completes a bus cycle after recognizing
that HALT is active, most three-state signals are put in the highimpedance state. These include:
The processor terminates the bus cycle, then puts the address
and data output lines in the high-impedance state. The processor
remains "halted" and will not run another bus cycle until external logic negates HALT. Then the processor will re-run the
previous bus cycle using the same address, the same function
codes, the same data (for a write operation), and the same controls. BERR should be negated at least one clock cycle before
HALT is negated.
1. address lines, and
2. data lines.
This is required for correct performance of the re-run bus cycle
operation.
Honoring the halt request has no effect on bus arbitration. Only
the bus arbitration function removes the control signals from the
bus.
Note
The processor will not re-run a read-modify-write cycle.
This restriction is made to guarantee that the entire cycle
runs correctly and that the write operation of a Test-andSet operation is performed without ever releasing AS. If
BERR and HALT are asserted during a read-modify-write
bus cycle, a bus error operation results.
Total debugging flexibility is derived from the software debugging
package, the halt function, and the hardware trace capability.
These processor capabilities allow the hardware debugger to
trace single bus cycles or single instructions at a time.
Double Bus Faults. When a bus error exception occurs, the
processor will attempt to stack several words containing informa·
tion about the state of the machine. If a bus error exception
occurs during the stacking operation, there have been two bus
errors in a row, or a double bus fault. A double bus fault causes
the processor to halt. Once a bus error exception has occurred,
any bus error exception occurring before the execution of the
next instruction constitutes a double bus fault.
Halt Operation with No Bus Error. The HALT input signal to
the R68000 performs a HalVRun/Single-Step function in a similar
fashion to the R6500 halt functions. When the HALT signal is
constantly active the processor "halts" (does nothing) and when
the HALT signal is constantly inactive the processor "runs"
(does something).
1
r----
\ ....._ _ _..J
,-------------------~\
\
r-
~~~~~)==============~~~~
====~----~X~========================~==
'-----~t:;,:1
lc- - - - - -_ _ _ _ _ _ _ _ __
CLOCK PERIODi
Jo I.
Figure 21.
H A L T - - - - -...Jo+I.---RE.RUN--....;.~1
Re·Run Bus Cycle Timing Diagram
4-18
R68000
16-Bit MPU
ClK
\'--______
AS
\'-_ _~....JI
Ir - - - - - - - - - - ' \
/~---
\
lOS UDS
R!W
\
DTACK
00-015
FCO-FC2
=x
HALT
IOf
\~----------------~I
READ ------~·~I~Of~-------HAlT--------~·+I·c------READ----~.~I
Figure 22_
Halt Signal Timing Waveforms
THE RELATIONSHIP OF DTACK, BERR, AND
HALT
Note that a bus cycle which is re-run does not constitute a bus
error exception, and does not contribute to a double bus fault.
This means that as long as the external hardware requests it,
the processor will continue to re-run the same bus cycle.
In order to properly control termination of a bus cycle for are-run
or a bus error condition, DTACK, BERR, and HALT should be
asserted and negated on the rising edge of R68000 clock. This
will assure that when two signals are asserted simultaneously,
the required setup time (#47) for both of them will be met during
the same bus state.
The bus error (BERR) pin also has an effect on processor operation after the processor receives an external reset input. The
processor reads the vector table after a reset to determine the
address to start program execution. If a bus error occurs while
reading the vector table (or at any time before the first instruction is executed), the processor reacts as if a double bus fault
has occurred and it halts. Only an external reset will start a halted
processor.
This, or some equivalent precaution, should be designed external to the R68000. Parameter #48 is intended to ensure this
operation in a totally asynchronous system, and may be ignored
if the above conditions are met.
RESET OPERATION. The reset signal is a bidirectional signal
that allows either the processor or an external signal to reset
the system. Figure 23 is a timing diagram for reset operations.
Both HALT and RESET must be applied to ensure total reset
of the processor.
The preferred bus cycle terminations may be summarized as
follows (case numbers refer to Table 4):
Normal Termination: DTACK occurs first (case 1).
Hall Terminalion: HALT is asserted at same time, or precedes
OTACK (no BERR) cases 2 and 3.
When the RESET and HALT are driven by an external device
the entire system, including the processor, is reset. The
processor responds by reading the reset vector table entry (vector number zero, address $000000) and loading into the supervisor stack pointer (SSP). Vector table entry number one at
address $000004 is read next and loaded into the program
counter. The processor initializes the status register to an interrupt level of seven, with no other register being affected.
Bus Error Termination: BERR is asserted in lieu of, at same
time, or preceding OTACK (case 4); BERR negated at same
time, or after OTACK.
Re-Run Termination: HALT and BERR asserted in lieu of, at
the same time, or before OTACK (cases 6 and 7); HALT must
be negated at least one cycle after BERR. (Case 5 indicates
BERR may precede HALT which allows fully asynchronous
assertion).
Execution of the RESET instruction drives the reset pin low for
124 clock periods. In this case, the processor is trying to reset
the rest of the system. The internal state of the processor, including the processor's internal registers and the status register, is
unaffected by the execution of a RESET instruction. All external
devices connected to the reset line will be reset at the completion of the RESET instruction.
Table 4 details the resulting bus cycle termination under various
combinations of control signal sequences. The negation of these
same control signals under several conditions is shown in
Table 5. (OTACK is assumed to be negated normally in all
cases; for best results, both OTACK and BERR should be
negated when address strobe is negated).
Asserting RESET and HALT for 10 clock cycles will cause a
processor reset, except when Vcc is initially applied to the
processor. In this case, an external reset must be applied for
100 milliseconds.
Example A: A system uses a watch-dog timer to terminate
accesses to unpopulated address space. The timer asserts
OTACK and BERR simultaneously after timeout (case 4).
4-19
II
16-Bit MPU
R68000
CLK
PLUS 5 VOLTS
t - >100 MILLISECONDS
•
VCC
•I
RESET
HALT
l~
______________________~
f-----lt
<4 CLOCKS
BUS CYCLES XX~~~~~~~--------------~~
__)l__J(__->~~~__
2
NOTES:
1) INTERNAL START-UP TIME
2) SSP HIGH READ IN HERE
3) SSP LOW READ IN HERE
4) PC HIGH READ IN HERE
5) PC LOW READ IN HERE
6) FIRST INSTRUCTION FETCHED HERE.
Figure 23.
345
')\j::J)¢(
>----<
6
BUS STATE UNKNOWN (ALL
CONTROL SIGNALS INACTIVE)
DATA BUS IN READ MODE
Reset Operation Timing Diagram
Example B: A system uses error detection on RAM contents.
Designer may (a) delay DTACK until data verified, and return
BERR and HALT simultaneously to re-run error cycle (case 6),
or if valid, return DTACK (case 1); (b) delay DTACK until data
verified and return BERR at same time as DTACK if data in
error (case 4).
The BERR signal is allowed to be asserted after the DTACK
signal is asserted. BERR must be asserted within the time given
as parameter #48 after DTACK is asserted in any asynchronous
system to insure proper operation. If this maximum delay time
is violated, the processor may exhibit erratic behavior.
Synchronous Operation
To allow for those systems which use the system clock as a
signal to generate DTACK and other asynchronous inputs, the
asynchronous inputs setup time is given as parameter #47. If
this setup is met on an input, such as DTACK, the processor is
guaranteed to recognize that signal on the next falling edge of
the system clock. However, the converse is not true-if the input
signal does not meet the setup time it is not guaranteed not to
be recognized. In addition, if DTACK is recognized on a falling
edge, valid data will be latched into the processor (on a read
cycle) on the next falling edge provided that the data meets the
setup time given as parameter #27. Given this, parameter #31
may be ignored. Note that if DTACK is asserted, with the required
setup time, before the falling edge of S4, no wait states will be
incurred and the bus cycle will run at its maximum speed of four
clock periods.
ASYNCHRONOUS VERSUS SYNCHRONOUS
OPERATION
Asynchronous Operation
To achieve clock frequency independence at a system level, the
R68000 can be used in an asynchronous manner. This entails
using only the bus handshake lines (AS, UDS, LDS, DTACK,
BERR, HALT, and VPA) to control the data transfer. Using this
method, AS signals the start of a bus cycle and the data strobes
are used as a condition for valid data on a write cycle. The slave
device (memory or peripheral) then responds by placing the
requested data on the data bus for a read cycle or latching data
on a write cycle and asserting the data transfer acknowledge
signal (DTACK) to terminate the bus cycle. If no slave reponds
or the access is invalid, external control logic asserts the BERR,
or BERR and HALT, signal to abort or rerun the bus cycle.
In order to assure proper operation in a synchronous system
when BERR is asserted after DTACK, the following conditions
must be met. Within one clock cycle after DTACK was recognized, BERR must meet the setup time parameter #27A prior
to the falling edge of the next clock. The setup time is critical
to proper operation, and the R68000 may exhibit erratic behavior
if it is violated.
The DTACK signal is allowed to be asserted before the data from
a slave device is valid on a read cycle. The length of time that
DTACK may precede data is given as parameter #31 (See
Figure 45) and it must be met in any asynchronous system to
insure that valid data is latched into the processor. Notice that
there is no maximum time specified from the assertion of AS
\ to the assertion of DTACK. This is because the MPU
will insert wait cycles of one clock period each until DTACK is
recognized.
Note
During an active bus cycle, VPA and BERR are sampled
on every falling edge of the clock starting with SO. DTACK
is sampled on every falling edge of the clock starting with
S4 and data is latched on the falling edge of S6 during
a read. The bus cycle will then be terminated in S7 except
when BERR is asserted in the absence of DTACK, in
which case it will terminate one clock cycle later in S9.
4-20
16-Bit MPU
R68000
Table 4.
DTACK, BERR, HALT Assertion Results
Asserted on Rising
Edge 01 State
Case
No.
Control
Signal
N
1
DTACK
BERR
HALT
A
NA
NA
5
X
X
Normal cycle terminate and continue.
2
DTACK
BERR
HALT
A
NA
A
5
X
5
Normal cycle terminate and halt. Continue when HALT removed.
3
DTACK
BERR
HALT
NA
NA
A
A
NA
5
Normal cycle terminate and halt. Continue when HALT removed.
4
DTACK
BERR
HALT
X
A
NA
X
S
NA
Terminate and take bus error trap.
5
DTACK
BERR
HALT
NA
A
NA
X
5
A
Terminate and re-run.
6
DTACK
BERR
HALT
X
A
A
X
5
5
Terminate and re·run when HALT removed.
7
DTACK
BERR
HALT
NA
NA
A
X
A
5
Terminate and re·run when HALT removed.
Legend:
N A NA X 5 -
N
+ 2
Result
the number of the current even bus state (e.g., 54, 56. etc.)
signal is asserted in this bus state
signal is not asserted in this state
don't care
signal was asserted in previous state and remains asserted in this state
Table 5.
Conditions 01
Termination in
Table 4-4
..
BERR AND HALT Negation Results
Negated on Rising
Edge 01 State
Control
Signal
N
•
•
Bus Error
BERR
HALT
Re-run
BERR
HALT
Re-run
BERR
HALT
•
Normal
BERR
HALT
Normal
BERR
HALT
•
•
•
•
•
N
or
or
or
or
or
+2
•
•
•
•
•
•
none
• = 5ignal is negated in this bus state.
4-21
Results -
Next Cycle
Takes bus error trap.
Illegal sequence; usually traps to vector number O.
Re-runs the bus cycle.
May lengthen next cycle.
If next cycle is started it will be terminated as a bus error.
16-Bit MPU
R68000
All exception processing is done in the supervisor state,
regardless of the setting of the S-bi!. The bus cycles generated
during exception processing are classified as supervisor
references. All stacking operations during exception processing
use the supervisor stack pointer.
PROCESSING STATES
The following paragraphs describe the actions of the R6S000
which are outside the normal processing associated with the
execution of instructions. The functions of the bits in the supervisor portion of the status register are covered: the supervisor/user bit, the trace enable bit, and the processor interrupt
. priority mask. The sequence of memory references and actions
taken by the processor on exception conditions are detailed.
USER STATE. The user state is the lower state of privilege. For
instruction execution, the user state is determined by negating
(low) the S-bit of the status register.
The R6S000 is always in one of three processing states: normal, exception, or halted. The normal processing state
associated with instruction execution; the memory references
are to fetch instructions and operands, and to store results. A
special case of the normal state is the stopped state which the
processor enters when a STOP instruction is executed. In this
state, no further references are made.
Most instructions execute the same in user state as in the supervisor state. However, some instructions which have important
system effects are made privileged. User programs are not permitted to execute the STOP instruction, or the RESET instruction. To ensure that a user program cannot enter the supervisor
state except in a controlled manner, the instructions which
modify the whole state register are priviled. To aid in debugging
programs which are to be used as operating systems, the move
10 user stack pointer (MOVE to USP) and move from user stack
pointer (MOVE from USP) instructions are also privileged.
The exception processing state is associated with interrupts, trap
instructions, tracing and other exceptional conditions. The
exception may be internally generated by an instruction or by
an unusual condition arising during the execution of an instruction. Externally, exception processing can be forced by an interrupt, by a bus error, or by a reset. Exception processing is
designed to provide an efficient context switch so that the
processor may handle unusual conditions.
The bus cycles generated by an instruction executed in user
state are classified as user state references. This allows an external memory management device to translate the address and
to control access to protected portions of the address space.
While the processor is in user privilege state, those instructions
which use either the system stack pointer implicitly or address
register seven explicitly, access the user stack pointer.
The halted processing state is an indication of a catastrophic
hardware failure. For example, if during the exception processing
of a bus error another bus error occurs, the processor assumes
that the system is unusable and halts. Only an external reset
can restart a halted processor. Note that a processor in the
stopped state is not in the halted state, n~r vice versa.
PRIVILEGE STATE CHANGES. Once the processor is in the
user state and executing instructions, only exception processing
can change the privilege state. During exception processing,
the current setting of the S-bil of the status register is saved and
the S-bit is asserted, putting the processing in the supervisor
state. Therefore, when instruction execution resumes to process
the exception, the processor is in the supervisor privilege state.
PRIVILEGE STATES
The processor operates in one of two states of privilege: the
"user" state or the "supervisor" state. The privilege state determines legal operations. It is used to choose between the supervisor stack pointer and the user stack pointer in instruction
references, and by the external memory management device
to control and translate accesses.
REFERENCE CLASSIFICATION. When the processor makes
a reference, it classifies the kind of reference being made by
using the encoding on the three function code output lines. This
allows external translation of addresses, control of access, and
differentiation of special processor states, such as interrupt
acknowledge. Table 6 lists the classification of references.
The privilege state is a mechanism for providing security in a
computer system by allowing most programs to execute in user
state. In this state, the accesses are controlled, and the effects
on other parts of the system are limited. Programs should access
only their own code and data areas, and ought to be restricted
from accessing information.
Table 6.
Reference Classification
Function Code Output
The operating system which executes in the supervisor state,
has access to all resources and performs the overhead tasks
for the user state programs.
SUPERVISOR STATE. The supervisor state is the higher state
of privilege. For instruction execution, the supervisor state is
determined by asserting (high) the S-bit of the status register.
All instructions can be executed in the supervisor state. The bus
cycles generated by instructions executed in the supervisor state
are classified as supervisor references. While the processor is
in the supervisor privilege state, those instructions which use
either the system stack pointer implicitly or address register
seven explicitly access the supervisor stack pointer.
4-22
FC2
FC!
FCO
a
a
a
a
a
1
User Dala
0
1
0
User Program
Reference Class
(Unassigned)
a
1
1
(Unassigned)
1
a
(Unassigned)
1
a
a
1
Supervisor Data
1
1
a
Supervisor Program
1
1
1
Interrupt Acknowledge
16-Bit MPU
R68000
WORD 0
NEW PROGRAM COUNTER (HIGH)
AO=O, A1 =0
WORD 1
NEW PROGRAM COUNTER (LOW)
AO=0,A1=1
Figure 24.
Exception Vector Format
DB D7
D15
DO
IGNORED
WHERE:
v7 IS THE MSB OF THE VECTOR NUMBER
vO IS THE LSB OF THE VECTOR NUMBER
Figure 25.
Peripheral Vector Number Format
A23
A10 A9 AB A7
AS A5 A4
A3 A2
A1
AO
ALL ZEROES
Figure 26.
Address Translated From 8-Bit Vector Number
EXCEPTION PROCESSING
address 1023. This provides 255 unique vectors; some of these
are reserved for TRAPS and other system functions. Of the 255,
there are 192 reserved for user interrupt vectors. However, there
is no protection on the first 64 entries, so user interrupt vectors
may overlap at the discretion of the systems designer.
Before discussing the details of interrupts, traps, and tracing,
a general description of exception processing is in order. The
processing of an exception occurs in four steps, with variations
for different exception causes. During the first step, a temporary
copy of the status register is made, and the status register is
set for exception processing. In the second step the exception
vector is determined, and the third step is the saving of the current processor contents. In the fourth step a new context is
obtained, and the processor switches to instruction processing.
KINDS OF EXCEPTIONS. Exceptions can be generated either
internally or externally. Externally generated exceptions include
interrupts (IRQ), bus error (BERR), and reset (RESET) requests.
Interrupts are requests from peripheral devices for processor
action while BERR and RESET inputs are used for access control and processor restart. Internally generated exceptions come
from instructions, from address errors, or from tracing. The trap
(TRAP), trap on overflow (TRAPV), check register against bounds
(CHI<) and divide (DIV) instructions can all generate exceptions
as part of their instruction execution. In addition, illegal instructions, word fetches from odd addresses and privilege violations
cause exceptions. Tracing behaves like a very high priority, internally generated interrupt after each instruction execution.
EXCEPTION VECTORS. Exception vectors are memory locations from which the processor fetches the address of a routine
which will handle that exception. All exception vectors are two
words in length (Figure 24), except for the reset vector, which
is four words. All exception vectors lie in the supervisor data
space, except for the reset vector which is in the supervisor program space. A vector number is an eight-bit number which, when
multipled by four, gives the address of an exception vector. Vector numbers are generated internally or externally, depending
on the cause of the exception. In the case of interrupts, during
the interrupt acknowledge bus cycle, a peripheral provides an
S-bit vector number (Figure 25) to the processor on data bus lines
DO through 07. The processor translates the vector number into
a full 24-bit address, as shown in Figure 26. The memory layout
for exception vectors is given in Table 7.
EXCEPTION PROCESSING SEQUENCE. Exception processing
occurs in four identifiable steps. In the first step, an internal copy
is made of the status register. After the copy is made, the S-bit
is asserted, putting the processor into the supervisor privilege
state. Also, the T-bit is negated which will allow the exception
handler to execute unhindered by tracing. For the reset and interrupt exceptions, the interrupt priority mask is also updated.
As shown in Table 7, the memory layout is 512 words long
(1024 bytes). It starts at address 0 and proceeds through
4-23
16-Bit MPU
R68000
Table 7.
Exception Vector Assignment
Address
Vector
Number(s)
Assignment
Dec
Hex
Space
0
0
000
SP
Reset: Initial SSP
-
4
004
SP
Reset: Initial PC
2
8
008
SO
Bus Error
3
12
OOC
SO
Address Error
4
16
010
SO
5
20
014
SO
Illegal Instruction
I
Zero Oivide
6
24
018
SO
CHK Instruction
7
28
01C
SO
TRAPV Instruction
8
32
020
SO
Privilege Violation
9
36
024
SO
Trace
10
40
028
SO
Line 1010 Emulator
11
44
02C
SO
Line 1111 Emulator
12-
48
030
SO
(Unassigned, reserved)
13-
52
034
SO
(Unassigned, reserved)
14-
56
038
SO
(Unassigned, reserved)
15
60
03C
SO
Un initialized Interrupt Vector
64
04C
SO
(Unassigned, reserved)
95
05F
24
96
060
SO
Spurious Interrupt
16·23-
-
-
25
100
064
SO
Levell Interrupt Autovector
26
104
068
SO
Level 2 Interrupt Autovector
27
108
06C
SO
Level 3 Interrupt Autovector
28
112
070
SO
Level 4 Interrupt Autovector
29
116
074
SO
Level 5 Interrupt Autovector
30
120
078
SO
Level 6 Interrupt Autovector
31
124
07C
SO
Level 7 Interrupt Autovector
32·47
128
080
SO
TRAP Instruction Vectors
191
OBF
48·63-
192
OCO
SO
(Unassigned, reserved)
255
OFF
256
100
SO
User Interrupt Vectors
1023
3FF
64·255
...
-
-
-Vector numbers 12,13,14,16 through 23, and 48 through 63 are reserved for future enhancements. No user peripheral devices should be assigned
these numbers.
\
4·24
16-Bit MPU
R68000
SSP_
STATUS REGISTER
HIGH
I-PROGRAM COUNTER- - - - - -
Table 8.
1
Group
0
HIGHER
ADDRESSES
LOW
Figure 27.
1
Exception Stack Order (Groups 1 and 2)
2
In the second step, the vector number of the exception is determined. For interrupts, the vector number is obtained by a
processor fetch, classified as an interrupt acknowledge. For all
other exceptions, internal logic provides the veclor number. This
vector number is then used to generate the address of the exception vector.
Exception Grouping and Priority
Exception
Processing
Reset
Address Error
Bus Error
Exception processing begins
within two clock cycles.
Trace
Interrupt
Illegal Instruction
Privilege Violation
Exception processing begins
before the next instruction.
TRAP, TRAPV, CHK,
Zero Divide
Exception processing is started
by normal instruction execution
The priority relation between two exceptions determines which
is taken first if the conditions for both arise simultaneously.
Therefore, if a bus error occurs during a TRAP instruction, the
bus error takes precedence, and the TRAP instruction processing is aborted. In another example, if an interrupt request
occurs during the execution of an instruction while the T-bit is
asserted, the trace exception has priority, and is processed first.
Before instruction processing resumes, however, the interrupt
exception is also processed, and instruction processing commences finally in the interrupt handler routine. Table 8 gives a
summary of exception grouping and priority.
The third step is to save the currenl processor status except for
the reset exception. The current program counter value and the
saved copy of the status register are stacked using the supervisor stack pointer as shown in Figure 27. The program counter
value stacked usually points to the nexl unexecuted instruction;
however, for bus error and address error, the value stacked for
the program counter is unpredictable, and may be incremented
from the address of the instruction which caused the error. Additional information defining the current context is stacked for the
bus error and address error exceptions.
The last step is the same for all exceptions. The new program
counter value is fetched from the exception vector. The
processor then resumes instruction execution. The instruction
at the address given in the exception vector is fetched, and
normal instruction decoding and execution is started.
EXCEPTION PROCESSING DETAILED DISCUSSION
Exceptions have a number of sources, and each exception has
a unique processing sequence. The following paragraphs detail
the sources of exceptions, how each arises, and how each is
processed.
MULTIPLE EXCEPTIONS. These paragraphs describe the processing which occurs when multiple exceptions arise
simultaneously. Exceptions can be grouped according to their
occurrence and priority. The Group 0 exceptions are reset, bus
error, and address error. These exceptions cause the instruction currently being executed to be aborted, and the exception
processing to commence within two clock cycles. The Group 1
exceptions are trace and interrupt, as well as the privilege violations and illegal instructions. These exceptions allow the current instruction to execute to completion, but preempt the execution of the next instruction by forcing exception processing to
occur (privilege violations and illegal instructions are detected
when they are the next instruction to be executed). The Group 2
exceptions occur as part of the normal processing of instructions. The TRAP, TRAPV, CHK, and zero divide exceptions are
in this group. For these exceptions, the normal execution of an
instruction may lead to exception processing.
RESET. The reset input provides the highest exception level.
The processing of the reset signal is designed for system initiation, and recovery from catastrophic failure. Any processing in
progress at the time of the reset is aborted and cannot be
recovered. The processor is forced into the supervisor state and
the trace state is forced off. The processor interrupt priority mask
is set at level seven. The vector number is internally generated
to reference the reset exception vector at location 0 in the supervisor program space. Because no assumptions can be made
about the validity of register contents, in particular the supervisor stack pointer, neither the program counter nor the status
register is saved. The address contained in the first two words
of the reset exception vector is fetched as the initial supervisor
stack pointer, and the address in the last two words of the reset
exception vector is fetched as the initial program counter. Finally,
instruction execution is started at the address in the program
counter. The powerup/restart code should be pointed to by the
initial program counter.
Group 0 exceptions have highest priority, while Group 2 exceptions have lowest priority. Within Group 0, reset has highest
priority, followed by address error and then bus error. Within
Group 1, trace has priority over exlernal interrupts, which in turn
takes priority over illegal instruction and privilege violation. Since
only one instruction can be executed at a time, there is no priority
relation within Group 2.
The RESET instruction does not cause loading of the reset vector, but does assert the reset line to reset external devices. This
allows the software to reset the system to a known state and
then continue processing with the next instruction.
4-25
R68000
16·Bit MPU
INTERRUPTS. Seven levels of interrupt priorities are provided.
Devices may be chained externally within interrupt priority levels,
allowing an unlimited number of peripheral devices to interrupt
the processor. Interrupt priority levels are numbered from one
to seven, level seven being the highest priority. The status
register contains a three-bit mask which indicates the current
processor priority. Interrupts are inhibited for all priority levels
less than or equal to the current processor priority.
INTERRUPTING DEVICE
PROCESSOR
REQUEST INTERRUPT
t
1)
An interrupt request is made to the processor by encoding the
interrupt request level on the interrupt request lines; a zero indicates no interrupt request. Interrupt requests arriving at the
processor do not face immediate exception processing, but are
made pending. Pending interrupts are detected between instruction executions. If the priority of the pending interrupt is lower
than or equal to the current processor priority, execution continues with the next instruction and the interrupt exception
processing is postponed. (The recognition of level seven is
slightly different, as explained in a following paragraph.)
2)
3)
4)
5)
GRANT INTERRUPT
COMPARE INTERRUPT LEVEL IN STATUS
REGISTER AND WAIT FOR CURRENT
INSTRUCTION TO COMPLETE
PLACE INTERRUPT LEVEL ON A1, A2, A3
SET FUNCTION CODE TO INTERRUPT
ACKNOWLEDGE
ASSERT ADDRESS STROB~S)
ASSERT DATA STROBES (LOS AND UDS*)
t
PROVIDE VECTOR NUMBER
1) PLACE VECTOR NUMBER OF 00-07
2) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACK)
If the priority of the pending interrupt is greater than the current
processor priority, the exception processing sequence is started.
First a copy of the status register is saved, and the privilege state
is set to supervisor, then tracing is suppressed, and the
processor priority level is set to the level of the interrupt being
acknowledged. The processor fetches the vector number from
the interrupting device, classifying the reference as an interrupt
acknowledge and displaying the level number of the interrupt
being acknowledged on the address bus. If external logic
requests an automatic vectoring, the processor internally
generates a vector number which is determined by the interrupt
level number. If external logic indicates a bus error, the interrupt is taken to be spurious, and the generated vector number
references the spurious interrupt vector. The processor then proceeds with the usual exception processing, saving the program
counter and status register on the supervisor stack. The saved
value of the program counter is the address of the instruction
which would have been executed had the interrupt not been
present. The content of the interrupt vector whose vector number
was previously obtained is fetched and loaded into the program
counter, and normal instruction execution commences in the
interrupt handling routine. A flow chart for the interrupt
acknowledge sequence is given in Figure 28, a timing diagram
is given in Figure 29, and the interrupt exception timing
sequence is shown in Figure 30.
•
ACQUIRE VECTOR NUMBER
1) LATCH VECTOR NUMBER
2) NEGATE LOS AND UDS
3) NEGATE AS
t
RELEASE
1) NEGATE DTACK
t
START INTERRUPT PROCESSING
• ALTHOUGH A VECTOR NUMBER IS ONE BYTE, BOTH
DATA STROBES ARE ASSERTED DUE TO THE
MICROCODE USED FOR EXCEPTION PROCESSING. THE
PROCESSOR DOES NOT RECOGNIZE ANYTHING ON
DATA LINES 08 THROUGH 015 AT THE TIME.
Figure 28.
Priority level seven is a special case. Level seven interrupts cannot be inhibited by the interrupt priority mask, thus providing
a "non-maskable interrupt" capability. An interrupt is generated
each time the interrupt request level changes from some lower
level to level seven. Note that a level seven interrupt may still
be caused by the level comparison if the request level is a seven
and the processor priority is set to a lower level by an instruction.
Interrupt Acknowledge Sequence Flow Chart
SPURIOUS INTERRUPT. If during the interrupt acknowledge
cycle no device responds by asserting DTACK or VPA, the bus
error line should be asserted to terminate the vector acquisition.
The processor separates the processing of this error from bus
error by fetching the spurious interrupt vector instead of the bus
error vector. The processor then proceeds with the usual exception processing.
UN INITIALIZED INTERRUPT. An interrupting device asserts
VPA or provides an interrupt vector during an interrupt
acknowledge cycle to the R68000. If the vector register has not
been initialized, the responding R68000 Family peripheral will
provide vector 15, the uninitialized interrupt vector. This provides
a uniform way to recover from a programming error.
INSTRUCTION TRAPS. Traps are exceptions caused by instructions. They arise either from processor recognition of abnormal
conditions during instruction execution, or from use of instructions whose normal behavior is trapping.
4-26
16-Bit MPU
R68000
ClK
--~====~/--~----==========~~\~------~~--~~
\~____~r---\~___
~~~~~~~
::::: ..." .... "'''-,
OF INSTRUCTION
r=-(R~~~gR ~14
~
S~~~K
(SSP)
~
(
<
x'-_(____
lACK CYCLE
STACK AND
~14 (VECTOR NUMBER ACQUISITION)+VECTOR FETCH--j
"ALTHOUGH A VECTOR NUMBER IS ONE BYTE, BOTH DATA STROBES ARE ASSERTED DUE TO THE MICROCODE USED
FOR EXCEPTION PROCESSING. THE PROCESSOR DOES NOT RECOGNIZE ANYTHING ON DATA liNES D8 THROUGH D15
AT THIS TIME.
Figure 29.
lAST BUS CYCLE
OF INSTRUCTION
(DURING WHICH
INTERRUPT WAS
RECOGNIZED)
r---.
~
STACK
PCl
(AT SSP-2)
READ
VECTOR
HIGH
(A16-A23)
Interrupt Acknowledge Sequence Timing Diagram
lACK
CYCLE
r- (VECTOR
NUMBER
ACQUISITION)
r-
Figure 30.
READ
VECTOR
lOW
(AO-A15)
-
STACK
STATUS
(AT SSP-6)
FETCH FIRST
WORD OF
INSTRUCTION
OF INTERRUPT
ROUTINE
Interrupt Exception Timing Sequence
4-27
r-
STACK
PCH
(AT SSP-4)
--
NOTE:
SSP REFERS TO THE
VALUE OR THE SUPERVISOR STACK POINTER
BEFORE THE INTERRUPT
OCCURS
lEI
16-Bit MPU
R68000
is pending on completion, the trace exception is processed
before the interrupt exception. If, during the execution of the
instruction, an exception is forced by that instruction, the forced
exception is processed before the trace exception.
Some instructions are used specifically to generate traps. The
TRAP instruction always forces an exception, and is useful for
implementing system calls for user programs. The TRAPV and
CHK instructions force an exception if the user program detects
a runtime error, which may be an arithmetic overflow or a
subscript out of bounds.
As an extreme illustration of the above rules, consider the arrival
of an interrupt during the execution of a TRAP instruction while
tracing is enabled. First the trap exception is processed, then
the trace exception, and finally the interrupt exception. Instruction execution resumes in the interrupt handler routine.
The signed divide (DIVS) and unsigned divide (DIVU) instructions will force an exception if a division operation is attempted
with a divisor of zero.
BUS ERROR. Bus error exceptions occur when the external logic
requests that a bus error be processed by an exception. The
current bus cycle which the processor is making is then aborted.
Whether the processor was doing instruction or exception
processing, that processing is terminated, and the processor
immediately begins exception processing.
ILLEGAL' AND UNIMPLEMENTED INSTRUCTIONS. Illegal
instruction refers to any of the word bit patterns which are not
the bit pattern of the first word of a legal instruction. During
instruction execution, if such an instruction is fetched, an illegal
instruction exception occurs. Rockwell reserves the right to
define instructions whose opcodes may be any of the illegal
instructions. Three bit patterns will always force an illegal instruction trap on all R68000 Family compatible microprocessors. They
are: $4AFA, $4AFB, and $4AFC. Two of the patterns, $4AFA
and $4AFB, are reserved for Rockwell system products. The third
pattern, $4AFC, is reserved for customer use.
Exception processing for bus error follows the usual sequence
of steps. The status register is copied, the supervisor state is
entered, and the trace state is turned off. The vector number
is generated to refer to the bus error vector. Since the processor
was not between instructions when the bus error exception
request was made, the context of the processor is more detailed.
To save more of this context, additional information is saved on
the supervisor stack. The program counter and the copy of the
status register are of·course saved. The value saved for the program counter is advanced by some amount, two to ten bytes
beyond the address of the first word of the instruction which
made the reference causing the bus error. If the bus error
occurred during the fetch of the next instruction, the saved program counter has a value in the vicinity of the current instruction, even if the current instruction is a branch, a jump, or a return
instruction. Besides the usual information, the processor saves
its internal copy of the first word of the instruction being
processed, and the address which was being accessed by the
aborted bus cycle. Specific information about the access is also
saved: whether it was a read or a write, whether the processor
was processing an instruction or not, and the classification
displayed on the function code outputs when the bus error
occurred. The processor is processing an instruction if in the
normal state or processing a Group 2 exception; the processor
is not processing an instruction when processing a Group 0 or
a Group 1 exception. Figure 31 iIIustates how the information
is organized on the supervisor stack. Although this information
is not sufficient to effect full recovery from the bus error, it does
allow software diagnosis. Finally, the processor commences
instruction processing at the address contained in the vector.
It is the responsibility of the error handler routine to clean up
the stack and determine where to continue execution.
Word patterns with bits 15 through 12 equaling 1010 or 1111
are distinguished as unimplemented instructions and separate
exception vectors are given to these patterns to permit efficient
emulation. This facility allows the operating system to detect program errors, or to emulate unimplemented instructions in
software.
PRIVILEGE VIOLATIONS. In order to provide system security,
various instructions are privileged. An attempt to execute one
of the privileged instructions while in the user state will cause
an exception. The privileged instructions are:
STOP
AND Immediate to SR
RESET
RTE
MOVE USP
EOR Immediate to SR
OR Immediate to SR
MOVE to SR
TRACING. To aid in program development, the R68000 includes
a facility to allow instruction by instruction tracing. In the trace
state, after each instruction is executed an exeception is forced,
allowing a debugging program to monitor the execution of the
program under test.
The trace facility uses the T-bit in the supervisor portion of the
status register. If the T-bit is negated (off), tracing is disabled,
and instruction execution proceeds from instruction to instruction as normal. If the T-bit is asserted (on) at the beginning of
the execution of an instruction, a trace exception will be
generated after the execution of that instruction is completed.
If the instruction is not executed, either because "an interrupt
is taken, or the instruction is illegal or privileged, the trace exception does not occur. The trace exception also does not occur
if the instruction is aborted by a reset, bus error, or address error
exception. If the instruction is indeed executed and an interrupt
If a bus error occurs during the exception processing for a bus
error, address error, or reset, the processor is halted, and all
processing ceases. This simplifies the detection of catastrophic
system failure, since the processor removes itself from the
system rather than destroy all memory contents. Only the RESET
pin can restart a halted processor.
4-28
16-Bit MPU
R68000
15
14
13
12
11
10
9
7
8
6
5
4
3
SSP
IR!Wll/N
I
o
2
FUNCTION
CODE
HIGH
-- - - - - - - - - - - - - - - - - - - - -
-ACCESS ADDRESS
lOW
1
HIGHER
ADDRESS
INSTRUCTION REGISTER
STATUS REGISTER
HIGH
f- - PROGRAM COUNTER
-
- - - - - - - - - ----------lOW
RlW (READ/WRITE): WRITE = 0, READ = 1. I/N (INSTRUCTION/NOT): INSTRUCTION = 0, NOT = 1 •
Figure 31.
Supervisor Stack Order (Group 0)
ClK
-:::===j~;======~=~~;=====~
A1-A23
AS UDS
lOS
\
\
\'-----~----~====~--~
------.\1....
___-'I
\
RIWj
-
I
DTACK - - - - - - - - . \ ' -_ _....J
\
\
~
I
======:J>-<'
-___ -I"
I
00-015 - - - - - - { (
II-....
~
~
ADDRESS ERROR
- - - - R E A D - - -.....~....t--.....::=:!!·
WRITE
Figure 32.
....J~:__------«::::==::::
Address Error Timing
ADDRESS ERROR. Address error exceptions occur when the
processor attempts to access a word or a long word operand
or an instruction at an odd address. The effect is much like an
internally generated bus error, so that the bus cycle is aborted,
and the processor ceases whatever processing it is currently
doing and begins exception processing. After exception
processing commences, the sequence is the same as that for
bus error including the information that is stacked, except that
the vector number refers to the address error vector instead.
Likewise, if an address error occurs during the exception
processing for a bus error, address error, or reset, the processor
is halted. As shown in Figure 32, an address error will execute
a short bus cycle followed by an exception processing.
4-29
I-
APPROX. 8 CLOCKS
IDLE
-
WRITE STACK
--l
II
16-Bit MPU
R68000
INTERFACE WITH R6500 PERIPHERALS
DATA TRANSFER OPERATION
Rockwell's line of R6500 peripherals are directly compatible with
the R68000. Some of these devices that are particularly useful
are:
R6520 Peripheral Interface Adapter (PIA)
R6522 Versatile Interface Adapter (VIA)
R6545 CRT Controller (CRTC)
R6551 Asynchronous Communication Interface Adapter
(ACIA)
Three signals on the processor provide the R6500 interface.
They are: enable (El. valid memory address (VMA), and valid
Peripheral address (VPA). Enable corresponds to the E or 112
signal in existing R6500 systems. The bus frequency is one tenth
of the incoming R68000 clock frequency. The timing of E allows
1 MHz peripherals to be used with an 8 MHz R6BOOO. Enable
has a 60/40 duty cycle; that is, it is low for six input clocks and
high for four input clocks. This duty cycle allows the processor
to do successive VPA accesses on successive E pulses.
To interface the synchronous R6500 peripherals with the asynchronous R68000, the processor modifies its bus cycle to meet
the R6500 cycle requirements whenever ·an R6500 device
address is detected. This is possible since both processors use
memory mapped I/O. Figure 33 is a flow chart of the interface
operation between the processor and R6500 devices. 6800
peripherals are also compatible with the R68000 processor.
PROCESSOR
II
Figures 34 and 35 give a general R6500 to R6BOOO interface
timing, while Figures 36 and 37 detail the specific timing
parameters involved in the interface. At state zero (SO) in the
cycle, the address bus is in the high-impedance state. A function code is asserted on the function code output lines. Onehal! clock later, in state 1, the address bus is released from the
high-impedance state.
During state 2, the address strobe (AS) is asserted to indicate
that there is a valid address on the address bus. I! the bus cycle
is a read cycle, the upper and/or lower data strobes are also
ass~rted in state 2. I! the bus cycle is a write cycle, the read/write
(R/w) signal is switched to a low (write) during state 2. Qne-hal!
clock later, in state 3, the write data is placed on the data bus,
and in state 4 the data strobes are issued to indicate valid data
on the data bus. The processor now inserts wait states until it
'
recognizes the assertion of VPA.
SLAVE
INITIATE CYCLE
1) THE PROCESSOR STARTS A
NORMAL READ OR WRITE CYCLE
L
+
DEFINE R6SDD CYCLE
1) EXTERNAL HARDWARE ASSERTS
VALID PERIPHERAL ADDRESS (VPA)
The VPA input signals the processor that the address on the
bus is the address of an R6500 device (or an area reserved for
R6500 devices) and that the bus should conform to the 112
transfer characteristics of the R6500 bus. Valid peripheral
address (VPA) is derived by ~ecoding the address bus,
conditioned by address strobe (AS). Chip select for the R6500
peripherals should be derived by decoding the address bus conditioned by VMA.
t
SYNCHRONIZE WITH ENABLE
1) THE PROCESSOR MONITORS ENABLE
(E) UNTIL IT IS LOW (PHASE 1)
2) THE PROCESSOR ASSERTS VALID
MEMORY ADDRESS (VMA)
I
,
After the recognition of VPA, the processor assures that the
Enable ~s low, by waiting if necessary, and subsequently
asserts VMA. Valid memory address is then used as part of the
chip select equation of the peripheral. This ensures thilt the
R6500 peripherals are selected and deselected at the correct
time. The peripheral now runs its cycle during the high portion
of the E signal. Figures 34 and 35 depict the best and worst case
R6500 cycle timing. This cycle length is dependent strictly upon
when VPA is asserted in relationship the E clock,
TRANSFER DATA
1) THE PERIPHERAL WAITS UNTIL E
IS ACTIVE AND THEN TRANSFERS
THE DATA
•
TERMINATE CYCLE
1) THE PROCESSOR WAITS UNTIL E
GOES LOW. (ON A READ CYCLE THE
DATA IS LATCHED AS E GOES LOW
INTERNALLY)
2) THE PROCESSOR NEGATES VMA
3) THE PROCESSOR NEGATES AS, UDS,
and LOS
If we assume that external circuitry asserts VPA as soon as
possible after the assertion of AS, then VPA will be recognized
as being asserted on the falling edge of S4. In this case, no
"extra" wait cycles will be inserted prior to the recognition of
VPA assertion and only the wait cycles inserted to synchronize
with the E clock will determine the total length of the cycle. In
any case, the synchronization delay will be some integral number
of clock cycles within the following two extremes:
START N!XT CYCLE
Figure 33.
1. Best Case-VPA is recognized as being asserted on the
falling edge three clock cycles before E rises (or three clock
cycles after E falls).
R650D Interfacing Flow Chart
4-30
16·Bit MPU
R68000
50
52
54
w
w
w
w
w
w
56
SO
S2
CLK
A1-A23
=>-<
>---C
~
A5F\
DTACK
DATA IN
FCO-FC2
>->--
<
DATA OUT
<
==x
E\
\
/
~
\
VPA
C
r-
\
VMA
Figure 34.
R68000 to R6500 Peripheral Timing-Best Case
~~~wwwwwwwwwwwwwww~~
CLK
ill
A1-A23
~
>-C
I
AS~
DTACK
DATA OUT
DATA IN
FCO-FC2
--<
=x
>-
c::=>-
)C
/
E
VPA
\
\
\
VMA
Figure 35.
/
'---I
r
R68000 to R6500 Peripheral Timing-Worst Case
4-31
II
:0
0)
CO
o
o
o
so
elK
r--"\
--..1
S1
S2
S3
r--"\I
S4
,..---..1
w
~W
w
r--"\
w
w
~I w ,...--..
w
w
w
r--"\
w
,...--..
S5
S6
~I
S7~
A1·A23
AS
E
----.I "---~
®
11-
@
...W
_~I
"""
®
"
VPA
I\)
VMA
DATA OUT - - - - - DATAIN _ _ _ _ _ _ _
- - - - -' - ,- - @
--------------------------
NOTES:
THIS FIGURE REPRESENTS THE BEST CASE R6500 TIMING WHERE VPA FAllS BEFORE THE THIRD SYSTEM CLOCK CYCLE
AFTER THE FALLING EDGE OF E.
THIS TIMING DIAGRAM IS INCLUDED FOR THOSE WHO WISH TO DESIGN THEIR OWN CIRCUIT TO GENERATE VMA IT SHOWS
THE BEST CASE POSSIBLY ATTAINABLE.
....
0)
I
III
;::::;:
:s:
Figure 36.
R6500 Timing-Best Case
"'C
c:
16-Bit MPU
R68000
Included in the register indirect addressing modes is the capability to do postincrementing, predecrementing, offsetting and
indexing. Program counter relative mode can also be modified
via indexing and offsetting.
2. Worst Case-VPA is recognized as being asserted on the
falling edge two clock cycles before E rises (or four clock
cycles after E falls).
Near the end of a read cycle, the processor latches the
peripheral's data in state 6. For all cycles, the processor negates
the address and data strobes one half clock cycle later in state 7,
and the Enable signal goes low at this time. Another half clock
later, the address bus is put in the high-impedance state. Upon
write cycle completion, the data bus is put in the high-impedance
state and the read/write signal is switched high. The peripheral
logic must remove VPA within one clock after address strobe
is negated.
Table 9,
Addressing Modes
Generation
Mode
DTACK should not be asserted while VPA is asserted. Note
that the R6S000 VMA is active low. This allows the processor
to put its buses in the high-impedance state on DMA requests
without inadvertently selecting peripherals.
INTERRUPT OPERATION
During an interrupt acknowledge cycle while the processor is
fetching the vector, if VPA is asserted, the R68000 will assert
VMA and complete ~ normal R6500 read cycle as shown in
Figure 38. The processor will then use an internally generated
vector, called an autovector, that is a function of the interrupt
being served. The seven autovectors are vector numbers 25
through 31 (decimal).
Autovectors operate in the same fashion as (but are not restricted
to) the R6500 interrupt sequence. The basic difference is that
there are six normal interrupt vectors and one NMI type vector.
As with both the R6500 and the R68000's normal vectored interrupt, the interrupt service routine can be located anywhere in
the address space. This is due to the fact that while the vector
numbers are fixed, the contents of the vector table entries are
assigned by the user.
Register Direct Addressing
Data Register Direct
Address Register Direct
EA = On
EA = An
Absotute Data Addressing
Absolute Short
Absolute Long
EA = (Next Word)
EA = (Next Two Words)
Program Counter Relative
Addressing
Relative with Offset
Relative with Index and Offset
EA = (PC) + dl6
EA = (PC) + (Xn) + de
Register Indirect Addressing
Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with Offset
EA =
EA =
An_
EA =
EA =
Immediate Data Addressing
Immediate
Quick Immediate
DATA = Next Word(s)
Inherent Data
Implied Addressing
Implied Register
EA = SR,USP,SP, PC
NOTES:
EA = Effective Address
An = Address Register
On = Data Register
Xn = Address or Data Register
used as Index Register
SR = Status Register
PC =::: Program Counter
( ) = Contents of
de = Eight-bit Offset
(displacement)
dl6 = Sixteen-bit Offset
(displacement)
Since VMA is asserted during autovectoring, the R6500
peripheral address decoding should prevent unintended
accesses.
DATA TYPES AND ADDRESSING MODES
Five basic data types are supported. These data types are:
Bits
BCD Digits (4-bits)
Bytes (8-bits)
Word (16-bits)
Long Words (32-bits)
(An)
(An),
An (An)
(An)
An-+ An + N
N, EA = (An)
+ d16
+ (Xn~ + de
N = 1 for Byte, 2 for
Words and 4 for
Long Word. " An
is the stack pointer
and the operand
size is byte, N = 2
to keep the stack
pOinter on a word
boundry.
-+ = Replaces
INSTRUCTION SET OVERVIEW
The R68000 instruction set is shown in Table 10. Some additional instructions are variations, or subsets, of these and they
appear in Table 11. Special emphasis has been given to the
instruction set's support of structured high-level languages to
facilitate ease of programming. Each instruction, with few exceptions, operates on bytes, words, and long words and most
instructions can use any of the 14 addressing modes. Combining
instruction types, data types, and addressing modes, over 1000
useful instructions are provided. These instructions include
signed and unsigned multiply and divide, "quick" arithmetic
operations. BCD arithmetic and expanded operations (through
traps).
In addition, operations on other data types such as memory
addresses, status word data, etc., are provided for in the instruction set.
The 14 addressing modes, shown in Table 9, include six basic
types:
Program Counter Relative
Register Direct
Register Indirect
Implied
Absolute
Immediate
4-33
16-Bit MPU
R68000
SO Sl S2 S3 S4
w w w w w w w w w w w w w w w w w w w w w w w w w w w w S5 S6 S7 SO
CLK
E
A1-A23
DATA OUT---DATAIN ________________________________________________________________~~*=====~
NOTE: THIS TIMING DIAGRAM IS INCLUDED FOR THOSE WHO WISH TO DESIGN THEIR OWN CIRCUIT TO GENERATE VMA.
IT SHOWS THE WORST CASE POSSIBLY ATTAINABLE.
Figure 37.
RC68000 to R6500 Peripheral Timing Diagram - Worst Case
CLK
A1-A3
A4-A23
AS
UDS'
LOS
RJW
DTACK
08-015
00-07
FCO-FC2
IPLO-IPL2
~
---c:)
---c:)
X
y
'C
~
E
VPA
VMA
L-
------======~------~
, ' - - - - _.......1
\
-10(
~ NORMAL...~---AUTOVECTOR OPERATION------""""'I-~I
CYCLE
'ALTHOUGH A VECTOR NUMBER IS ONE BYTE, BOTH DATA STROBES ARE ASSERTED DUE TO THE MICROCODE USED
FOR EXCEPTION PROCESSING. THE PROCESSOR DOES NOT RECOGNIZE ANYTHING ON DATA LINES 08 THROUGH
015 AT THIS TIME.
Figure 38.
Autovector Operation Timing Diagram
4-34
16-Bit MPU
R6S000
Table 10.
Description
Mnemonic
Mnemonic
ADBC
ADD
AND
ASL
ASR
Add Decimal with Extend
Add
Logical And
Arithmetic Shift Left
Arithmetic Shift Right
BCC
BCHG
BCLR
BRA
BSET
BSR
BTST
Branch Conditionally
Bit Test and Change
Bit Test and Clear
Branch Always
Bit Test and Set
Branch to Subroutine
Bit Test
CHK
Check Register Against
Bounds
Clear Operand
Compare
CLR
CMP
DBCC
DIVS
DIVU
Test Condition, Decrement and
Branch
Signed Divide
Unsigned Divide
ADD
AND
Variation
JMP
JSR
Jump
Jump to Subroutine
LEA
LINK
LSL
LSR
Load Effective Address
Link Stack
Logical Shift Left
Logical Shift Right
MOVE
MULS
MULU
Move
Signed Multiply
Unsigned Multiply
NBCD
NEG
NOP
NOT
Negate Decimal with Extend
Negate
No Operation
One's Complement
OR
Logical Or
Description
AND
ANDI
ANDI to CCR
Logical And
And Immediate
And Immediate to
Condition Codes
And Immediate to
Status Register
CMP
CMPA
CMPM
CMPI
Compare
Compare Address
Compare Memory
Compare Immediate
EOR
EOR
EORI
EORI to CCR
Exclusive Or
Exclusive Or Imrnediate
Exclusive Or Immediate
to Condition Codes
Exclusive Or Immediate
to Status Register
EORI to SR
Instruction
Type
Push Effective Address
RESET
ROL
ROR
ROXL
ROXR
RTE
RTR
RTS
Reset External Devices
Rotate Left without Extend
Rotate Right without Extend
Rotate Left with Extend
Rotate Right with Extend
Return from Exception
Return and Restore
Return from Subroutine
SBCD
SCC
STOP
SUB
SWAP
Subtract Decimal with Extend
Set Conditional
Stop
Subtract
Swap Data Register Halves
TAS
TRAP
TRAPV
TST
Test and Set Operand
Trap
Trap on Overflow
Test
UNLK
Unlink
II
4-35
Variation
Description
MOVE
MOVEA
MOVEM
MOVEP
MOVEQ
MOVE from SR
MOVE to SR
MOVE to CCR
MOVE USP
Move
Move
Move
Move
Move
Move
Move
Move
Move
NEG
NEG
NEGX
Negate
Negate with Extend
OR
OR
ORI
ORI to CCR
ORI to SR
Logical Or
Or Immediate
Or Immediate to Condition Codes
Or Immediate to
Status Register
SUB
SUB
SUBA
SUBI
SUBQ
SUBX
Subtract
Subtract
Subtract
Subtract
Subtract
Address
Quick
Immediate
with Extend
CMP
PEA
Variations of Instruction Types
MOVE
Add
Add
Add
Add
Add
Description
Mnemonic
Exclusive Or
Exchange Registers
Sign Extend
ADD
ADDA
ADDQ
ADD I
ADDX
ANDI to SR
Description
EOR
EXG
EXT
Table 11.
Instruction
Type
Instruction Set Summary
Address
Multiple Registers
Peripheral Data
Quick
from Status Register
to Status Register
to Condition Codes
User Stack Pointer
Address
Immediate
Quick
with Extend
16-Bit MPU
R68000
The following paragraphs contain an overview of the form and
structure of the R68000 instruction set. The instructions form
a set of tools that include all the machine functions to perform
the following operations:
Data Movement
Integer Arithmetic
Logical
Shift and Rotate
Bit Manipulation
Binary Coded Decimal
Program Control
System Control
Data Movement Operations
Table 12.
Instruction
Operand Size
EXG
32
LEA
32
8,16,32
s _d
MOVEM
16,32
(EA) _An, On
An, On _EA
MOVEP
16,32
(EA) _On
On _(EA)
MOVE
The complete range of instruction capabilities combined with
the flexible addressing modes described previously provide a
very flexible base for program development.
ADDRESSING
Instructions for the R68ODO contain two kinds of information: the
type of function to be performed, and the location of the
operand(s) on which to perform that function. The methods used
to locate (address) the operand(s) are explained in the following paragraphs.
MOVEO
8
#xxx .... On
PEA
32
EA _ -(SP)
SWAP
32
UNLK
NOTES:
s = source
d = destination
[ 1 = bit number
Instructions specify an operand location in one of three ways:
Register Specification - the number of the register is given
in the register field of the
instruction.
Effective Address
- use of the different effective
address modes.
ImpliCit Reference
- the definition of certain instructions
implies the use of specific
registers.
EA __ An
An _-(SP)
SP _An
SP + displacement -SP
-
LINK
Operation
Rx_Ry
On[31:161-0n[15:01
An -Sp
(SP) + _An
-
-( ) = indirect with predecrement
(
) + = indirect with postdecrement
# = immediate data
operand sizes. Address operations are limited to legal address
size operands (16 or 32 bits). Data, address, and memory compare operations are also available. The clear and negate instructions may be used on all sizes of data operands.
The multiply and divide operations are available for signed and
unsigned operands using word multiply to produce a long word
product, and a long word dividend with word divisor to produce
a word quotient with a word remainder.
DATA MOVEMENT OPERATIONS
The move (MOVE) instruction provides a means for data acquisition (transfer and storage). The move instruction and the effective addressing modes allow both address and data manipulation. Data move instructions allow byte, word, and long word
operands to be transferred from memory to memory, memory
to register, register to memory, and register to register. Address
move instructions allow word and long word operand transfers
and ensure that only legal address manipulations are executed.
In addition to the general move instruction there are several
special data movement instructions: move multiple registers
(MOVEM), move peripheral data (MOVEP), exchange registers
(EXG), load effective address (LEA), push effective address
(PEA), link stack (LINK), unlink stack (UNLK), and move quick
(MOVEQ). Table 12 summarizes the data movement operations.
Multiprecision and mixed size arithmetic can be accomplished
using a set of extended instructions. These instructions are: add
~I(tended (ADDl<), subtract extended (SUBX), sign extend (EXT),
and negate binary with extend (NEGX).
A text operand (TSn instruction that sets the condition codes
as a result of a compare of the operand with zero is available.
Test and set (TAS) is a synchronization instruction useful in
multiprocessor systems. Table 13 summrizes the integer
arithmetic operations.
INSTRUCTION FORMAT
Instructions, as shown in Figure 39, vary from one to five words
in length. The first word of the instruction, called the operation
word, specifies the length of the instruction and the operation
to be performed. The remaining words further specify the
operands. These words are either immediate operands or extensions to the effective address mode specified in the operation
word.
INTEGER ARITHMETIC OPERATIONS
The arithmetic operators include the four basic operations of add
(ADD), subtract (SUB), multiply (MUL), and divide (DIV) as well
as arithmetic compare (CMP), clear (CLR), and negate (NEG).
The add and subtract instructions are available for both address
and data operations, and with data operations accepting all
4-36
16-Bit MPU
R68000
Table 13.
Instruction
PROGRAMIDATA REFERENCES
Integer Arithmetic Operations
Operand Size
8.16.32
Operation
16.32
On + (EA) .... Dn
(EA) + On .... (EA)
(EA) + #xxx .... (EA)
An + (EA) .... An
ADDX
8.16.32
16.32
Ox + Dy + X .... Dx
-(Ax) + -(Ay) + X .... (Ax)
CLR
8.16.32
o -EA
8.16.32
ADD
The R6SDDD separates memory references into two classes: program references, and data references. Program references
reference that section of memory that contains the program
being executed. Data references refer to that section of memory
that contains data. Operand reads are from the data space,
except in the case of the program counter relative addressing
mode. All operand writes are to the data space.
REGISTER SPECIFICATION
The register field within an instruction specifies the register to
be used. Other fields within the instruction specify whether the
register selected is an address or data register and how the
register is to be used.
16.32
On - (EA)
(EA) - #xxx
(Ax)+ - (Ay)An - (EA)
DIVS
32.,. 16
On.,. (EA) _On
EFFECTIVE ADDRESS
DIVU
32.,. 16
On .,. (EA) _On
EXT
8_16
16 _32
(Dn)8 -Dn16
(Dnh6 .... Dn32
MULS
16 x 16 -32
On x (EA) _On
MULU
16 x 16 -32
On x (EA) _On
NEG
8,16,32
NEGX
8,16,32
oo-
Most instructions specify the location of an operand by using
the effective address field in the operation word. For example,
Figure 40 shows the general format of the single effective
address instruction operation word. The effective address is composed of two 3-bit fields: the mode field, and the register field.
The value in the mode field selects the different address modes.
The register field contains the number of a register.
CMP
(EA) -(EA)
The effective address field may require additional information
to fully specify the operand. This additional information, called
the effective address extension, is contained in the following
word or words and is considered part of the instruction, as shown
in Figure 39. The effective address modes are grouped into three
categories: register direct, memory addressing, and special.
(EA) - X -(EA)
On - (EA) _On
(EA) - On .... (EA)
(EA) - #xxx -(EA)
An - (EA) -An
8,16,32
SUB
16, 32
SUBX
8,16,32
Ox - Dy - X -Ox
-(Ax) - -(Ay) - X _(Ax)
TAS
8
[EA] - 0, 1 _EA[7]
TST
8,16,32
(EA) - 0
REGISTER DIRECT MODES. These effective addressing modes
specify that the operand is in one of the 16 multifunction
registers.
Data Register Direct. The operand is in the data register
specified by the effective address register field.
NOTES:
[ ] = bit number
-( ) = indirect with predecrement
( ) + = indirect with postdecrement
# = immediate data
Address Register Direct. The operand is in the address register
specified by the effective address register field.
MEMORY ADDRESS MODES. These effective addressing
modes specify that the operand is in memory and provide the
specific address of that operand.
15
14
13
12
11
10
9
8
7
6
5
4
OPERATION WORD
(FIRST WORD SPECIFIES OPERATION AND MODES)
IMMEDIATE OPERAND
(IF ANY, ONE OR TWO WORDS)
SOURCE EFFECTIVE ADDRESS EXTENSION
(IF ANY, ONE OR TWO WORDS)
DESTINATION EFFECTIVE ADDRESS EXTENSION
(IF ANY, ONE OR TWO WORDS)
Figure 39.
Instruction Format
4-37
3
2
o
II
16-Bit MPU
R68000
Figure 40.
Single-Effective-Address Instruction Operation Word General Format
address is the second extension word. The reference classifies
as a data reference with the exception of the jump and jump
to subroutine instructions.
Address Register Indirect. The address of the operand is in
the address register specified by the register field. The reference
is classified as a data reference with the exception of the jump
and jump to subroutine instructions.
Program Counter With Displacement. This address mode
requires one word of extension. The address of the operand
sums the addresses in the program counter and the signextended 16-bit displacement integer in the extension word. The
value in the program counter is the address of the extension
word. The reference classifies as a program reference.
Address Register Indirect With Postincrement. The address
of the operand is in the address register specified by the register
field. After the operand address is used, it is incremented by
one, two or four depending upon whether the size of the operand
is byte, word, or long word. If the address register is the stack
pointer and the operand size is byte, the address is incremented
by two rather than one to keep the stack pointer on a word
boundary. The reference classifies as a data reference.
Program Counter With Index. This address mode requires one
word of extension. This address sums the addresses in the program counter, the sign-extended displacement integer in the
lower eight bits of the extension word, and the contents of the
index register. The value in the program counter is the address
of the extension word. This reference classifies as a program
reference.
Address Register Indirect With Predecrement. The address
of the operand is in the address register specified by the register
field. Before the operand address is used, it is decremented by
one, two, or four depending upon whether the operand size is
byte, word, or long word. If the address register is the stack
pointer and the operand size is byte, the address is decremented
by two rather than one to keep the stack pointer on a word
boundary. The reference is classified as a data reference.
Immediate Data. This address mode requires either one or two
words of extension depending on the size of the operation.
Byte Operation
- operand is low order byte of extension word
Word Operation
- operand is extension word
Long Word Operation - operand is in the two extension
words, high-order 16 bits are in the
first extension word, low-order 16
bits are in the second extension
word.
Address Register Indirect with Displacement. This address
mode requires one word of extension. The address of the
operand is the sum of the address in the address register and
the sign-extended 16-bit displacement integer in the extension
word. The reference classifies as a data reference with the
exception of the jump to subroutine instructions.
Address Register Indirect With Index. This address mode
requires one word of extension. The address of the operand
sums the addresses in the address register, the sign-extended
displacement integer in the low order eight bits of the extension
word, and the contents of the index register. The reference is
classified as a data reference with the exception of the jump
and jump to subroutine instructions.
IMPLICIT REFERENCE
Some instructions make implicit reference to the program
counter (PC), the system stack pointer (SP), the supervisor stack
pointer (SSP), the user stack pointer (USP), or the status register
(SR).
A selected set of instructions may reference the status register
by means of the effective address field. These are:
ANDI to CCR
ANDlto SR
EORlto CCR
EORlto SR
MOVE to CCR
MOVE to SR
MOVE from SR
ORI to CCR
ORlto SR
SPECIAL ADDRESS MODE. The special address modes use
the effective address register field to specify the special addressing mode instead of a register number.
Absolute Short Address. This address mode requires one word
of extension. The address of the operand is the extension word.
The 16-bit address is sign extended before it is used. The
reference classifies as a data reference with the exception of
the jump and jump to subroutine instructions.
Absolute Long Address. This address mode requires two words
of extension. The address of the operand is developed by the
concatenation of the extension words. The high-order part of
the address is the first extension word; the low-order part of the
EFFECTIVE ADDRESS ENCODING SUMMARY
Table 14 summarizes the effective addressing modes discussed
in the previous paragraphs.
4-38
R6BOOO
Table 14.
16-Bit MPU
Effective Address Encoding Summary
Addressing Mode
Mode
Register
Data Register Direct
000
register number
Address Register Direct
001
register number
Address Register Indirect
010
register number
Address Register Indirect with
Postincrement
011
register number
Address Register Indirect with
Predecrement
100
register number
Address Register Indirect with
Displacement
101
register number
Address Register Indirect with
Index
110
register number
Absolute Short
111
000
Absolute Long
111
001
Program Counter with
Displacement
111
010
Program Counter with Index
111
011
Immediate
111
100
Table 15.
Logical Operations
Instruction
Operand Size
AND
8,16,32
DnA(EA) _Dn
(EA)ADn _(EA)
(EA)A#xxx _(EA)
OR
8,16,32
Dn P (EA) _Dn
(EA) P Dn _(EA)
(EA) P #xxx -(EA)
EOR
8.16.32
(EA) .. Dy _(EA)
(EA) .. #xxx -(EA)
NOT
8,16,32
- (EA) _(EA)
NOTES:
- = invert
# = immediate data
A = logical AND
Operation
P = logical OR
.. = logical exclusive OR
Memory shifts and rotates are for word operands only and allow
only single-bit shifts or rotates.
Table 16 summarizes the shift and rotate operations.
BIT MANIPULATION OPERATIONS
The following instructions provide bit manipulation operations:
bit test (BTST), bit test and set (BSET), bit test and clear (BCLR),
and bit test and change (BCHG). Table t 7 is a summary of the
bit manipulation operations. (Bit 2 of the status register is Z.)
SYSTEM STACK. The system stack is used implicitly by many
instructions; user stacks and queues may be created and maintained through the addressing modes. Address register seven
(A7) is the system stack pointer (SP). The system stack pointer
is either the supervisor stack pointer (SSP) or the user stack
pointer (USP), depending on the state of the S·bit in the status
register. If the S-bit indicates supervisor state (High), SSP is the
active system stack pointer, and the USP cannot be referenced
as an address register. If the S-bit indicates user state (Low),
the USP is the active system stack pointer, and the SSP cannot be referenced. Each system stack fills from high memory
to low memory.
Table 16.
Instruction
Operand
Size
SHIFT AND ROTATE OPERATIONS
Shift operations in both directions are provided by arithmetic
instructions ASR and ASL and logical shift instructions LSR and
LSL. The rotate instructions (with and without extend) available
are ROXR, ROXL, ROR, and ROL. All shift and rotate operations can be performed in either registers or memory. Register
shifts and rotates support all operand sizes and allow a shift
count specified in a data register.
4-39
Operation
ASL
8,16,32
~-I"
ASR
8,16,32
d;
LSL
8,16,32
~
LSR
8,16,32
0-1
ROL
8,16,32
m.q ..
ROR
8,16,32
q
ROXL
8,16,32
~
ROXR
8,16,32
~
LOGICAL OPERATIONS
Logical operation instructions AND, OR, EOR, and NOT are
available for all sizes of integer data operands. A similar set of
immediate instructions (ANDI, ORI, and EORI) provide these
logical operations with all sizes of immediate data. Table 15 summarizes the logical operations.
Shift and Rotate Operations
..
f-o
~
I-@
1-- 0
.. f.--@
P
.. P-rrJ
.
f4=ttjJ
.. fJ.m
16-Bit MPU
R68000
Table 17.
Bit Manipulation Operations
Instruction
Operand Size
BTST
8,32
- bit of (EA) _Z
BSET
8,32
- bit of (EA) _Z
1 _bit of EA
BCLR
8,32
- bit of (EA) _Z
o _bit of EA
BCHG
8,32
- bit of (EA) _Z
- bit of (EA) _bit of EA
Table 19.
Operation
Program Control Operations
Instruction
Conditional
BCC
Branch conditionally (14 conditions)
8- and 16-bit displacement
OBCC
Test condition, decrement, branch
16-bit displacement
SCC
Set byte conditionally (16 conditions)
Unconditional
BRA
NOTE: - = invert
Branch always
8- and 16-bit displacement
BSR
Branch to subroutine
8- and 16-bit displacement
JMP
Jump
JSR
Jump to subroutine
BINARY CODED DECIMAL OPERATIONS
The following instructions accomplish multi precision arithmetic
operations on binary coded decimal numbers: add decimal with
extend (ABCD), subtract decimal with extend (SBCD), and
negale decimal with extend (NBCD). Table 18 summarizes the
binary coded decimal operations.
Operation
Returns
RTR
RTS
,
Return and restore condition codes
Return from subroutine
PROGRAM CONTROL OPERATIONS
Program control operations implementation requires a series of
conditional and unconditional branch instructions and return
instructions. These instructions are summarized in Table 19.
SYSTEM CONTROL OPERATIONS
System control operations are accomplished by using privileged
instructions, trap generating instructions, and instructions that
use or modify the status register. These instructions are summarized in Table 20.
The conditional instructions provide setting and branching for
the following conditions:
CC - carry clear
CS - carry set
EO-equal
F - never true
GE - greater or equal
GT - greater than
HI - high
LE - less or equal
LS - low or same
LT -less than
MI -minus
NE - not equal
PL - plus
T - always true
VC - no overflow
VS -overflow
Table 18.
ADDRESSING CATEGORIES
Effective address modes may be categorized by the ways in
which they may be used. The following classifications will be
used in the instructions definitions.
Data
If an effective address mode may be used to refer
to data operands, it is considered a data addressing
effective address mode.
Memory If an effective address mode may be used to refer
to memory operands, it is considered a memory
addressing effective address mode.
Alterable If an effective address mode may be used to refer
to alterable (writeable) operands, it is considered an
alterable addressing effective address mode.
Control
If an effective address mode may be used to refer
to memory operands without an associated size, it
is considered control addressing effective address
mode.
Binary Coded Decimal Operations
Instruction
Operand Size
Operation
ABCO
8
OxlO + OYIO + X -Ox
-(Axllo + -(AYlIO + x _(Ax)
SBCO
8
OX10 - OY10 - X -Ox
-(Axho - -(AYhO - X _(Ax)
NBCO
8
o - (EA)10 - X _(EA)
NOTE: -(
INSTRUCTION SET
The following paragraphs provide information about the addressing categories and instruction set of the R68000.
Table 21 shows the various categories to which each of the effective address modes belong. Table 22 is the instruction set
summary.
) = indirect with predecrement
4-40
R68000
Table 20.
16-Bit MPU
System Control Operations
Instruction
INSTRUCTION PREFETCH
The R6SDDD uses a two-word tightly-coupled instruction prefetch
mechanism to enhance performance. This mechanism is
described in terms of the microcode operations involved. If the
execution of an instruction is defined to begin when the
microroutine for that instruction is entered, some features of the
prefetch mechanism can be described.
Operation
Privileged
ANDI to SR
EORI to SR
MOVE EA to SR
MOVE USP
ORI to SR
RESET
RTE
STOP
Logical AND to Status Register
Logical EOR to Status Register
Load New Status Register
Move User Stack Pointer
Logical OR to Status Register
Reset External Devices
Return from Exception
Stop Program Execution
Trap Generating
CHK
TRAP
TRAPV
Check Data Register Against Upper Bounds
Trap
Trap on Overflow
Status Register
ANDI to CCR
EORI to CCR
MOVE EA to CCR
MOVE SR to EA
ORI to CCR
Logical AND to Condition Codes
Logical EOR to Condition Codes
Load New Condition Codes
Store Status Register
Logical OR to Condition Codes
1) When execution of an instruction begins, the operation word
and the word following have already been fetched. The operation word is in the instruction decoder.
2) In the case of multi-word instructions, as each additional word
of the instruction is used internally, a fetch is made to the
instruction stream to replace it.
3) The last fetch from the instruction stream is made when the
operation word is discarded and decoding is started on the
next instruction.
4) If the instruction is a single-word instruction causing a branch,
the second word is not used. But because this word is fetched
by the preceding instruction, it is impossible to avoid this
superfluous fetch.
5) In the case of an interrupt or trace exception, both words are
not used.
6) The program counter usually points to the last word fetched
from the instruction stream.
INSTRUCTION EXECUTION TIMES
The status register addressing mode is not permitted unless it
is explicitly mentioned as a legal addressing mode.
The following paragraphs contain listings of the instruction
execution times in terms of external clock (elK) periods. In this
timing data, it is assumed that both memory read and write cycle
times are four clock periods. Any wait states caused by a longer
memory cycle must be added to the total instruction time. The
number of bus read and write cycles for each instruction is
enclosed in parenthesis following the execution periods and is
shown as (r/w) where r is the number of read cycles and w is
the number of write cycles.
These categories may be combined, so that additional, more
restrictive, classifications may be defined. For example, the
instruction descriptions use such classifications as alterable
memory or data alterable. The former refers to those addressing modes which are both alterable and memory addresses, and
the latter refers to addressing modes which are both data and
alterable.
Table 21.
Effective
Address
Modes
Effective Addressing Mode Categories
Addressing Categories
Mode
Register
Data
Memory
Control
Alterable
Dn
An
(An)
000
001
010
Register Number
Register Number
Register Number
-
X
-
-
-
X
X
X
X
X
(An) +
-(An)
d(An)
all
100
101
Register Number
Register Number
Register Number
X
X
X
X
X
X
X
X
X
X
d(An, ix)
xxx.W
xxx.L
110
111
111
Register Number
000
001
X
X
X
X
X
X
X
X
X
X
X
X
d(PC)
d(PC, ix)
#xxx
111
111
111
010
011
X
X
X
X
X
X
X
X
X
-
-
X
4-41
-
II
R68000
16-Bit MPU
Table 22.
Instruction Set
Condition Codes
Description
Mnemonic
Operation
ABCD
Add Decimal with Extend
(Destinationl1 0 + (Source)10 + X _ Destination
ADD
Add Binary
(Destination) + (Source) _ Destination
ADDA
Add Address
(Destination) + (Source) _Destination
ADDI
Add Immediate
(Destination) + Immediate Data _Destination
ADDQ
Add Quick
(Destination) + Immediate Data _Destination
ADDX
Add Extended
(Destination) + (Source) + X _ Destination
AND
AND logical
(Destination) A (Source) _ Destination
ANDI
AND Immediate
(Destination) A Immediate Data _Destination
ANDI to CCR
AND Immediate to Condition Codes
(Source) A CCR _CCR
(Source) A SR _SR
X
N
Z
· ·
···
U
V
C
U
- - - - -
· · ·
· · · ·
· ·· ·
- ·
0
0
·
·
··
··
·
··
·
· ·
-
0
0
-
-
ANDI to SR
AND Immediate to Status Register
ASl, ASR
Arithmetic Shift
(Destination) Shifted by < count> _Destination
BCC
Branch Conditionally
If CC then PC + d -PC
- - -
BCHG
Test a Bit and Change
- «bit number» OF Destination -Z
- «bit number» OF Destination < bit number> OF Destination
- -
·
BClR
Test a Bit and Clear
o _
- «bit number» OF Destination -Z
_OF Destination
- -
·-
BRA
Branch Always
PC + d _PC
- - - - -
BSET
Test a Bit and Set
- «bit number» OF Destination _Z
1 _ OF Destination
BSR
Branch to Subroutine
PC _(SP); PC + d _PC
- - - - - - -
BTST
Test a Bit
- «bit number» OF Destination _Z
CHK
Check Register Against Bounds
If Dn <0 or Dn> «ea» then TRAP
ClR
Clear and Operand
o _Destination
CMP
Compare
(Destination) - (Source)
CMPA
Compare Address
(Destination) - (Source)
CMPI
Compare Immediate
(Destination) - Immediate Data
CMPM
Compare Memory
(Destination) - (Source)
DBCC
Test Condition, Decrement and Branch If - CC then Dn - 1 _Dn; il Dn '" - 1 then PC + d ....PC
DIVS
Signed Divide
(Destination)/(Source) _Destination
DIVU
Unsigned Divide
(Destination)/(Source) _Destination
EOR
Exclusive OR logical
(Destination) e (Source) _Destination
EORI
Exclusive OR Immediate
(Destination) e Immediate Data _Destination
EORI to CCR
Exclusive OR Immediate
to Condition Codes
(Source) e CCR _ CCR
NOTES:
A = logical
p
= logical
e = logical
- = logical
AND
OR
exclusive OR
complement
.
= affected
- = unaffected
0 = cleared
1 = set
U = undefined
4-42
- -
·
·-
- U U U
- 0 1 0 0
- - - - 0
0
0 0
0 0
(
·
·
·
·
·
·
·
·
·
·
··
·
·
· · ·
· · ·
·
·
·· ·
R68000
16-Bit MPU
Table 22.
Instruction Set (Continued)
Condition Codes
Description
Mnemonic
Operation
X
(Source) .. SR _SR
EXG
Exchange Register
Rx_Ry
EXT
Sign Extend
(Destination) Sign·Extended _ Destination
JMP
Jump
Destination _ PC
JSR
Jump to Subroutine
PC _ - (SP); Destination _ PC
LEA
Load Effective Address
... An
LINK
Link and Allocate
An _(SP); SP _An; SP + Displacement _SP
LSL, LSR
Logical Shift
(Destination) Shifted by < count> ..... Destination
MOVE
Move Data from Source to Destination
(Source) _ Destination
MOVE to CCR
Move to Condition Code
(Source) _CCR
MOVE to SR
Move to the Status Register
(Source) _SR
MOVE from SR
Move from the Status Register
SR - Destination
MOVE USP
Move User Stack Pointer
USP _An; An _USP
MOVEA
Move Address
(Source) _ Destination
MOVEM
Move Multiple Registers
Register _ Destination
(Source) ... Registers
MOVEP
Move Peripheral Data
(Source) ... Destination
MOVEQ
Move Quick
Immediate Data _Destination
MULS
Signed Multiply
(Destination)X(Source) _ Destination
MULU
Unsigned Multiply
(Destination)X(Source) ... Destination
NBCD
Negate Decimal with Extend
NEG
Negate
aa-
X _ Destination
(Destination) ... Destination
Negate with Extend
0 - (Destination) - X ... Destination
No Operation
-
NOT
Logical Complement
- (Destination) ... Destination
OR
Inclusive OR Logical
(Destination) v (Source) _ Destination
ORI
Inclusive OR Immediate
(Destination) v Immediate Data - Destination
ORI to CCR
Inclusive OR Immediate
to Condition Codes
(Source) v CCR ... CCR
ORI to SR
Inclusive OR Immediate
to Status Register
(Source) v SR _SR
PEA
Push Effective Address
_ - (SP)
RESET
Reset External Device
-
ROL, ROR
Rotate (Without Extend)
(Destination) Rotated by < count> ... Oestination
-
.
= affected
- = unaffected
a = cleared
1 = set
U = undefined
4-43
C
·
·
·
·
·
·
·
- - - - - - - - - - - - -
- - - - -
NOP
AND
OR
exclusive OR
complement
---------
--------
NEGX
NOTES:
A = logical
v = logical
.. = logical
= logical
V
- - - a a
- - - - - - - - - - - - - a
a a
-
·
..
I
-
·
-
Z
· ·
EORI to SR
Exclusive OR Immediate
to Status Register
(Destinationl1 a
N
- - - a
a
a
-
-
· aa
· a
·
· ·.·
· ·
· ·- ·
U
U
- - -
·
·
a a
a a
a a
· · ·
· · ·
- - - - - - - - a
-
·
16-Bit MPU
R68000
Table 22.
Instruction Set (Continued)
Condition Codes
Mnemonic
Description
X
Operation
ROXL, ROXR
Rotate with Extend
(Destination) Rotated by +-Destination
RTE
Return from Exception
(SP)
+ +-SR; (SP) + +-PC
RTR
Return and Restore Condition Codes
(SP)
+ _CC; (SP) + _PC
RTS
Return from Subroutine
(SP)
+ _PC
SBCD
Subtract Decimal with Extend
(Destination), a - (Source), a - X - Destination
SCC
Set According to Condition
If CC then 1's _ Destination else a's -
STOP
Load Status Register and Stop
Immediate Data _ SR; STOP
SUB
Subtract Binary
(Destination) - (Source) ... Destination
SUBA
Subtract Address
(Destination) - (Source) ... Destination
SUBI
Subtract Immediate
(Destination) - Immediate Data _Destination
SUBQ
Subtract Quick
(Destination) - Immediate Data _Destination
.
.
Destination
N
Z
V
C
· .·
· ·
··
- - - ·
a
U
U
- - - - -
··
·
· ·
- - - - -
··
··
·· ·
SUBX
Subtract with Extend
(Destination) - (Source) - X _Destination
SWAP
Swap Register Halves
Register [31:16]_Register [15:0]
-
TAS
Test and Set an Operand
(Destination) Tested _CC; 1 -[7] OF Destination
-
TRAP
Trap
PC _ - (SSP); SR _ - (SSP); (Vector) _PC
- - - - -
TRAPV
Trap on Overflow
If • then TRAP
TST
Test and Operand
(Destination) Tested _ CC
- - - - a a
-
UNLK
Unlink
An _SP; (SP)
NOTES:
[ ] = bit number
A
= logical AND
= logical OR
= logical exclusive OR
= logical complement
•..
-
+ _An
· ·
· ·
a
a
a
a
- - - - -
= affected
- = unaffected
a = cleared
1 = set
U = undefined
STANDARD INSTRUCTION CLOCK PERIODS
Note
The number of clock periods shown in Table 26 delineate the
time required to perform the operations, store the results, and
read the next instruction. The number of bus read and write
cycles is shown in parenthesis as (r/w). The number of clock
periods and the number of read and write cycles must be added
respectively to those of the effective address calculation where
indicated.
The number of periods includes instruction fetch and all
applicable operand fetches and stores.
EFFECTIVE ADDRESS OPERAND
CALCULATION TIMING
Table 23 lists the number of clock periods required to compute
an instruction's effective address. It includes fetching of any
extension words, the address computation, and fetching of the
memory operand. The number of bus read and write cycles is
shown in parenthesis as (r/w). Note there are no write cycles
involved in processing the effective.. address.
In Table 26, the headings have the following meanings:
An =address register operand, On =data register operand,
ea = an operand specified by an effective address, and
M = memory effective address operand.
MOVE INSTRUCTION CLOCK PERIODS
IMMEDIATE INSTRUCTION CLOCK PERIODS
Tables 24 and 25 indicate the number of clock periods for the
move instruction. This data includes instruction fetch, operand
reads, and operand writes. The number of bus read and write
cycles is shown in parenthesis as (r/w).
The number of clock periods shown in Table 27 includes the
time to fetch immediate operands, perform the operations, store
the results, and read the next operation. The number of bus read
and write cycles is shown in parenthesis as (r/w). The number
4·44
16-Bit MPU
R68000
Table 23.
Effective Address Calculation Timing
Addressing Mode
Long
Byte, Word
Register
O(O/~)
On
An
Data Register Direct
Address Register Direct
0(0/0)
0(0/0)
0(0/0)
(An)
(An) +
Memory
Address Register Indirect
Address Register Indirect with Postincrement
4(1/0)
4(110)
8(2/0)
8(2/0)
-(An)
d(An)
Address Register Indirect with Predecrement
Address Register Indirect with Displacement
6(1/0)
8(2/0)
to(2/0)
12(3/0)
d(An. ix)'
xxx.w
Address Register Indirect with Index
Absolute Short
10(2/0)
8(2/0)
14(3/0)
12(3/0)
xxx.L
d(PC)
Absolute Long
Program Counter with Displacement
12(3/0)
8(2/0)
16(4/0)
12(3/0)
d(PC. ix)'
Program Counter with Index
Immediate
10(2/0)
4(1/0)
14(3/0)
8(2/0)
#xxx
'The size of the index register (ix) does not affect execution time.
Table 24.
D
Move Byte and Word Instruction Clock Periods
Destination
(An)
(An) +
-(An)
d(An)
d(An, ix)'
xxx.W
xxx.L
4(110)
4(110)
8(2/0)
4(110)
4(1/0)
8(2/0)
8(1/1)
8(1/1)
12(2/1)
8(111)
8(1/1)
12(2/1)
8(1/1)
_8(1/1)
12(2/1)
12(2/1)
12(2/1)
16(3/1)
14(2/1)
14(2/1)
18(3/1)
12(2/1)
12(2/1)
16(3/1)
16(3/1)
16(3/1)
20(4/1)
(An) +
-(An)
d(An)
8(2/0)
10(2/0)
12(3/0)
8(2/0)
10(2/0)
12(3/0)
12(2/1)
14(2/1)
16(3/1)
12(2/1)
14(2/1)
16(3/1)
12(2/1)
14(2/1)
16(3/1)
16(3/1)
18(3/1)
20(4/1)
18(3/1)
20(3/1)
22(4/1)
16(3/1)
18(3/1)
20(4/1)
20(4/1)
22(4/1)
24(5/1)
d(An. ix)'
xxx.L
14(3/0)
12(3/0)
16(4/0)
14(3/0)
12(3/0)
16(4/0)
18(3/1)
16(3/1)
20(4/1)
18(3/1)
16(3/1)
20(4/1)
18(3/1)
16(3/1)
20(4/1)
22(4/1)
20(4/1)
24(5/1)
24(4/1)
22(4/1)
26(5/1)
22(4/1)
20(4/1)
24(5/1)
26(5/1)
24(5/1)
28(6/1)
d(PC)
d(PC, ix)'
#xxx
12(3/0)
14(3/0)
8(2/0)
12(3/0)
14(3/0)
8(2/0)
16(3/1)
18(3/1)
12(2/1)
16(3/1)
18(3/1)
12(2/1)
16(3/1)
18(3/1)
12(2/1)
20(4/1)
22(4/1)
16(3/1)
22(4/1)
24(4/1)
18(3/1)
20(4/1)
22(4/1)
16(3/1)
24(5/1)
26(5/1)
20(4/1)
Source
Dn
An
(An)
xxx.w
On
An
'The size of the index register (ix) does not affect execution time.
of clock periods and the number of read and write cycles must
be added respectively to those of the effective adress calculation where indicated.
SINGLE OPERAND INSTRUCTION CLOCK PERIODS
Table 28 indicates the number of clock periods for the single
operand instructions. The number of bus read and write cycles
is shown in parenthesis as (r/w). The number of clock periods
and the number of read and write cycles must be added respectively to those of the effective address calculation where
indicated.
In Table 27, the headings have the following meanings:
operand, Dn ~ data register operand,
An ~ address register operand, M ~ memory operand, and
SR ~ status register.
# ~ immediate
4-45
16-Bit MPU
R68000
Table 25.
Move Long Instruction Clock Periods
Destination
On
An
(An)
(An) +
-(An)
dIAn)
dIAn, ix)'
xxx.W
xxx.L
On
An
(An)
4(110)
4(110)
12(3/0)
4(1/0)
4(1/0)
12(3/0)
12(1/2)
12(112)
20(3/2)
12(112)
12(1/2)
20(3/2)
12(112)
12(112)
20(3/2)
16(2/2)
16(2/2)
24(4/2)
18(212)
18(2/2)
26(4/2)
16(2/2)
16(2/2)
24(4/2)
20(3/2)
20(3/2)
28(5/2)
(An) +
-(An)
dIAn)
12(3/0)
14(3/0)
16(4/0)
12(3/0)
14(3/0)
16(4/0)
20(3/2)
22(3/2)
24(4/2)
20(3/2)
22(3/2)
24(4/2)
20(3/2)
22(3/2)
24(4/2)
24(4/2)
26(4/2)
28(5/2)
26(4/2)
28(4/2)
30(5/2)
24(4/2)
26(4/2)
28(5/2)
28(5/2)
30(5/2)
32(6/2)
dIAn, ix)"
xxx.W
xxx.L
18(4/0)
16(4/0)
20(5/0)
18(4/0)
16(4/0)
20(5/0)
26(4/2)
24(4/2)
28(5/2)
26(412)
24(4/2)
28(5/2)
26(4/2)
24(4/2)
28(5/2)
30(5/2)
28(5/2)
32(6/2)
32(5/2)
30(5/2)
34(6/2)
30(5/2)
28(5/2)
32(6/2)
34(6/2)
32(6/2)
36(7/2)
d(PC)
d(PC. ix)"
#xxx
16(4/0)
18(4/0)
12(3/0)
16(4/0)
18(4/0)
12(3/0)
24(4/2)
26(4/2)
20(3/2)
24(4/2)
26(4/2)
20(3/2)
24(4/2)
26(4/2)
20(3/2)
28(5/2)
30(5/2)
24(4/2)
30(5/2)
32(5/2)
26(4/2)
28(5/2)
30(5/2)
24(4/2)
32(5/2)
34(6/2)
28(5/2)
Source
"The size of the Index register (Ix) does not affect execution time.
Table 26.
Instruction
Standard Instruction Clock Periods
\
Size
op, Ant
ADD
Byte, Word
Long
8(1/0)+
6(110)+ ""
AND
Byte. Word
Long
CMP
Byte, Word
Long
op, On
6(110)+
6(110)+
8(111)+
12(112) +
4(1/0)+
6(1/0)+"
8(1/1)+
12(1/2)+
4(1/0)+
6(110)+
-
-
DIVS
-
-
158(110)+ •
DIVU
-
-
140(110) +'
EOR
Byte, Word
Long
MULS
MULU
-
OR
Byte, Word
Long
SUB
Byte, Word
Long
-
-------
4(110)'"
8(110)'"
8(111)+
12(112)+
70(1/0)+"
-
70(110)+ "
-
~1I0)+
8(1/0)+
6(1/0)+""
op On,
4(110) +
6(1/0)+"
6(1/0)+ ••
8(111)+
12(112)+
4(110) +
6(110)+ ••
8(111)+
12(1/2)+
NOTES:
+ add effective address calculation time
t word or long only
• indicates maximum value
"" The base time of six clock periods is increased to eight if the effective address mode is register direct or immediate (effective address time
should also be added).
" "" Only available effective address mode is data register direct
DIVS, DIVU The divide algorithm used by the R6BOOO provides less than 10% difference between the best and worst case timings.
MULS, MULU The multiply algorithm requires 3B + 2n clocks where n is defined as:
MULU: n = the number of ones in each
MULU: n = concatanatethe with a zero as the LSB; n is the resultant number of 10 or 01 patterns in the 17·bit source; i.e., worst
case happens when the source is $5555.
4-46
R68000
16-Bit MPU
Table 27.
Immediate Instruction Clock Periods
Size
op #, On
op #, An
op #, M
ADDI
Byte, Word
Long
8(2/0)
16(3/0)
-
12(2/1)+
20(3/2)+
ADDO
Byte, Word
Long
4(110)
8(1/0)
ANDI
Byte, Word
Long
8(2/0)
16(3/0)
CMPI
Byte, Word
Long
8(210)
14(3/0)
EaRl
Byte, Word
Long
8(2/0)
16(3/0)
MOVEO
Long
ORI
Byte, Word
Long
8(2/0)
16(3/0)
SUBI
Byte, Word
Long
8(2/0)
16(3/0)
SUBO
Byte, Word
Long
4(110)
8(1/0)
Instruction
8(1/0)"
8(1/0)
4(110)
8(1/1)+
12(112) +
-
12(2/1)+
20(3/1)+
-
12(2/1)+
20(3/2)+
8(1/0)"
8(1/0)
8(2/0)+
12(30)+
12(2/1)+
20(3/2)+
12(2/1)+
20(3/2)+
8(1/1)+
12(1/2)+
+ add effective address calculation time
word only
Table 28.
Single Operand Instruction Clock Periods
Size
Register
Memory
CLR
Byte, Word
Long
4(110)
6(1/0)
8(111)+
12(112) +
NBCD
Byte
6(110)
8(1/1)+
NEG
Byte, Word
Long
4(1/0)
6(110)
8(1/1)+
12(1/2)+
NEGX
Byte, Word
Long
4(110)
6(1/0)
8(111)+
12(1/2)+
NOT
Byte, Word
Long
4(110)
6(1/0)
8(111)+
12(1/2)+
SCC
Byte, False
Byte, True
4(1/0)
6(110)
8(1/1)+
8(1/1)+
TAS
Byte
4(1/0)
10(1/1)+
TST
Byte, Word
Long
4(1/0)
4(1/0)
4(1/0)+
4(1/0)+
Instruction
+ add effective address calculation time
4·47
16-Bit MPU
R68000
SHIFT/ROTATE INSTRUCTION CLOCK PERIODS
CONDITIONAL INSTRUCTION CLOCK PERIODS
Table 29 delineates the number of clock periods for the shift
and rotate instructions. The number of bus read and write cycles
is shown in parenthesis as: (r/w). The number of clock periods
and the number of read and write cycles must be added respectively to those of the effective address calculation where
indicated.
Table 31 delineates the number of clock periods required for
the conditional instructions. The number of bus read and write
cycles is indicated in parenthesis as: (r/w). The number of clock
periods and the number of read and write cycles must be added
respectively to those of the effective address calculation where
indicated.
BIT MANIPULATION INSTRUCTION CLOCK PERIODS
JMP, JSR, LEA, PWA, MOVEM INSTRUCTION CLOCK
PERIODS
Table 30 indicates the number of clock periods required for the
bit manipulation instructions. The number of bus read and write
cycles is shown in parenthesis as: (r/w). The number of clock
periods and the number of read and write cycles must be added
respectively to those of the effective address calculation where
indicated.
Table 29.
Instruction
Table 32 indicates the number of clock periods required for the
jump, jump to subroutine, load effective address, push effective address, and move multiple registers instructions. The
number of bus read and write cycles is shown in parenthesis
as: (r/w).
Shift/Rotate Instruction Clock Periods
Size
Register
Memory
ASR,ASL
Byte, Word
Long
6 + 2n(1I0)
8 + 2n(1I0)
8(111)+
LSR, LSL
Byte, Word
Long
6 + 2n(1I0)
8 + 2n(1I0)
8(1/1)+
ROR,ROL
Byte, Word
Long
6 + 2n(I/0)
8 + 2n(I/0)
8(1/1)+
ROXR,ROXL
Byte, Word
Long
6 + 2n(1I0)
8 + 2n(I/0)
8(111)+
+ add effective address calculation time
n is shift or rotate count
Table 30.
\
Bit Manipulation Instruction Clock Periods
Dynamic
Static
Register
Memory
Register
Memory
-
8(1/1)+
-
12(2/1)+
-
8(111)+
-
8(1/1)+
Instruction
Size
BCHG
Byte
Long
BCLR
Byte
Long
10(110)"
BSET
Byte
Long
8(1/0)'
BTST
Byte
Long
6(1/0)
8(1/0)'
12(2/0)'
-
12(2/1)+
14(2/0)"
-
12(211)+
12(2/0)'
-
4(1/0)+
10(2/0)
+ add effective address calculation time
* indicates maximum value
4-48
8(210)+
16-Bit MPU
R68000
Table 31.
Instruction
Displacement
Branch Taken
Branch Not Taken
Bee
Byte
Word
10(2/0)
10(2/0)
8(1101
12(2/0)
BRA
Byte
Word
10(2/0)
10(2/0)
BSR
Byte
Word
18(2/2)
18(2/2)
DBCC
CC true
CC false
10(2/0)
Table 32.
Instr
Size
(An)
16(2/2)
LEA
-
PEA
-
12(112)
JMP
JSR
MOVEM
M-R
MOVEM
R-M
Conditional Instruction Clock Periods
8(2/0)
4(110)
-
-
-
12(2/0)
14(3/0)
JMP, JSR, LEA, PEA, MOVEM INSTRUCTION CLOCK PERIODS
(An) +
-
-(An)
-
-
dIAn)
xxx.W
dIAn, ix)" +
xxx.L
d(PC)
d(PC, Ix)"
10(210)
14(3/0)
10(2/0)
12(3/0)
10(210)
14(3/0)
18(2/2)
22(212)
18(212)
20(3/2)
18(2/2)
22(2/2)
8(210)
12(2/0)
8(210)
12(3/0)
8(210)
12(210)
16(212)
20(2/2)
16(212)
20(3/2)
16(2/2)
20(2/2)
20 + 4n
16 + 4n
(4 + n/O)
18 + 4n
(4 + n/O)
16 + 8n
(4 + 2n/0)
18 + 8n
(4 + 2n/0)
Word
12 + 4n
(3 + n/O)
12 + 4n
(3 + n/O)
-
16 + 4n
(4 + n/O)
18 +4n
(4 + n/O)
16 + 4n
(4 + n/O)
(5 + n/O)
Long
12 + 8n
(3 + 2n/0)
12 + 8n
(3 + 2n/0)
-
16 + 8n
(4 + 2n/0)
18 + 8n
(4 + 2n/0)
16 + 8n
(4 + 2n/0)
(5 + 2n/0)
Word
8 + 4n
(2/n)
-
8 + 4n
(21n)
12 + 4n
(3/n)
14 + 4n
(3/n)
12 + 4n
(3/n)
16 + 4n
(4/n)
Long
8 + 8n
(2/2n)
-
-
8 + 8n
(2/2n)
12 + 8n
(3/2n)
14 + 8n
(3/2n)
12 + 8n
(3/2n)
16 + 8n
(4/2n)
20 + 8n
-
-
-
-
-
n is the number of registers to move
• The size of the index register (ix) does not affect the instruction's execution time
Table 33.
MULTI-PRECISION INSTRUCTION CLOCK PERIODS
Table 33 delineates the number of clock periods for the mUltiprecision instructions. The number of clock periods includes the
time to fetch both operands, perform the operations, store the
results, and read the next instructions. The number of read and
write cycles is shown in parenthesis as: (r/w).
In Table 33, the headings have the following meanings: Dn = data
register operand and M = memory operand.
4-49
Multi-Precision Instruction Clock Periods
Instruction
Size
op On, On
op M, M
ADDX
Byte, Word
Long
4(110)
8(110)
18(3/1)
30(5/2)
CMPM
Byte, Word
Long
-
12(3/0)
20(5/0)
SUBX
Byte, Word
Long
4(110)
8(110)
18(311)
30(5/2)
ABeD
Byte
6(110)
18(311)
SBeD
Byte
6(110)
18(311)
II
R68000
16-Bit MPU
MISCELLANEOUS INSTRUCTION CLOCK PERIODS
EXCEPTION PROCESSING CLOCK PERIODS
Table 34 and 35 indicate the number of clock periods for the
following miscellaneous instructions. The number of bus read
and write cycles is shown in parenthesis as: (r/w). The number
of clock periods plus the number of read and write cycles must
be added to those of the effective address calculation where
indicated.
Table 36 delineates the number of clock periods for exception
processing. The number of clock periods includes the time for
all stacking, the vector fetch, and the fetch of the first instruction of the handler routine. The number of bus read and write
cycles is shown in parenthesis as (r/w).
Table 34.
Instruction
Miscellaneous Instruction Clock Periods
Size
Register
ANDI to CCR
Byte
20(3/0)
-
LINK
-
16(2/2)
ANDI to SR
Word
20(3/0)
-
MOVE from USP
-
4(110)
4(1/0)
Memory
Instruction
Size
Register
10(1/0)+
-
MOVE to USP
-
EORI to CCR
Byte
20(3/0)
NOP
-
4(1/0)
EORI to SR
Word
20(3/0)
-
RESET
-
132(1/0)
ORI to CCR
Byte
20(310)
RTE
Word
20(3/0)
RTR
-
20(5/0)
ORI to SR
-
CHK
MOVE from SR
MOVE to CCR
MOVE to SR
EXG
- ,
Word
Long
EXT
-
Memory
-
-
20(5/0)
6(1/0)
8(1/1)+
RTS
-
16(4/0)
12(2/0)
12(2/0)+
STOP
-
4(0/0)
-
12(2/0)
12(2/0)+
SWAP
4(110)
-
6(1/0)
-
TRAPV
4(1/0)
-
UNLK
-
4(1/0)
4(1/0)
-
12(3/0)
-
+ add effective address calculation time
Table 35.
Move Peripheral Instruction Execution Times
Instruction
Size
Register_Memory
Memory-+-Register
MOVEP
Word
Long
16(2/2)
24(2/4)
16(4/0)
24(6/0)
Table 36.
Exception Processing Clock Periods
Exception
Periods
Address Error
50(4n)
Bus Error
50(4/7)
CHK Instruction
44(5/4)+
Divide by Zero
42(5/4)
Illegal Instruction
34(4/3)
Interrupt
44(5/3)'
Privilege Violation
34(4/3)
RESET"
40(6/0)
Trace
34(4/3)
TRAP Instruction
38(4/4)
TRAPV Instruction
34(4/3)
+ add effective address calculation time
, The interrupt acknowledge cycle is assumed to take four clock
periods.
" Indicates the time from when RESET and HALT are first sampled
as negated to when instruction execution starts.
4-50
R6S000
16·Bit MPU
MAXIMUM RATINGS
Where:
Rating
Symbol
Value
Unit
Supply Voltage
VCC
-0.3 to +7.0
V
Input Voltage
VIN
-0.3 to +7.0
V
Operating Temperature Range
TA
TL to TH'
°c
TSTG
-65 to +150
°c
Storage Temperature
T A '" Ambient Temperature, ·C
OJA '" Package Thermal Resistance, Junction-toAmbient, °CIW
Po '" PINT
, See ordering information
Characteristic
Symbol
PlIO
PlIO '" Power Oissipation on Input and Output PinsUser Oetermined
THERMAL CHARACTERISTICS
Thermal Resistance
64-Pin Ceramic
64-Pin Plastic Oip
+
PINT'" ICC' VCC, Watts-Chip Internal Power
Value
Unit
30
55 ±5
°CIW
°CIW
DJA
For most applications PlIO CCQCZ
cs
R/iii
RS2
CD
RS'
RSO
IACK2
DSR2
DCD2
CTS2
RTS2
IRQ2
AxD2
DTR2
Tx02
TxC
07
06
OS
04
IACK1
RxC
Tx01
DTR,
DSR'
AxD1
_
<
Jo..
DO-D7
.".
IRQ2
IACK2
-y
DATA
BUS
BUFFERS
ACIA2
INTERRUPT
LOGIC
0
N
_
N
N
N
RxD2
IRQ2
RTS2
CTS2
DCD2
DSR2
IACK2
CLKOUT
M ., 1ft CD ,.. m
N N N N N N
g"I"'I"':::;
44-PIN PLCC
R6BC552 Pin Assignments
DTRl
DSRl
RTSl
CTSl
TxDl
DCDl
RxDl
ACIAl
REGISTERS
AND
CONTROL
LOGIC
}
ACIA
CHANNELl
ACIAl BAUD
RATE SELECT
I
I
DTACK
LOGIC
DATA
1/0
MUX
I
•
CLOCK
LOGIC
•
R68C552 DACIA Interface Signals
4-63
XTALI
XTALO
CLKOUT
RxC
TxC
ACIA2 BAUD
RATE SELECT
ACIA2
REGISTERS
AND
CONTROL
LOGIC
IACK2
LOGIC
Figure 2.
m
_
TxC
Tx02
DTR2
Ui
II!I~I'"
0"
a:a:
U>Z~~~;;Z
b>[I££] tit [BOIB1J]~ ; I t rqq]~~
ACR
BITI
I"'T"TT-n T I"'Tl
II
II
I, I,
.. II
U!~!~'L'
_________________________________________________________
LlJj
TORE-U
! '!
IRQ
~
LlJ'
,
LlJ'
!
I
~
I
~
a. Transmit Break bit cleared before BREAK begins-BREAK is ignored
STOP START
TxO
ACR
BIT 1
STOP
~= E9£]
i-r-I : :
,
,
t
STOP START
STOP START
..I..-.L.....Jrtl t 1~@;-[&0 tit fBO"TBJ=~~=
K
I-1-'--1-....o.BR_E....o.A_
, , 1- ,--r-'
I
__ L_.J
I
I.._.L._
I
'
TORE~'
IRQ
!
J
I
I
!
!
LIJj
UJ'
!
!
J
b. Transmit Break bit cleared during first character time of BREAK-BREAK terminates after one character time
STOP START
TxO
ACR
BIT 1
TORE
IRQ
STOP
~~E9£I
;
STOP START
-Irtl t rsorq= ~
B_R_E_AK
_____
1 - 1_ _ _ _ _
_________
rTT-rl--------------------------------------~
:~:_L:~
~
___________________
, ,
~'
LIT
!
~
!
J
c. Transmit Break bit cleared after first character time of BREAK-BREAK terminates immediately
Figure 9.
Transmit BREAK
EFFECTS OF CTS ON TRANSMITTER
Any transition on CTS sets bit 5 (CTST) of the ISR. A high on CTS
forces bit 6 C!:QBE) of the ISR to a O. Bit 7 of the ISR also goes
to a 1 when CTS is high, if Echo Mode is disabled. Thus, when
the ISR is $80, it means that CTS is high and no interrupt source
requires service. A processor interrupt will not be generated under
these circumstances, but an ISR polling routine should accommodate this.
The CTS control line controls the transmission of data or the handshaking of data to a "busy" device (such as a printer). When the
CTS line is low, the transmitter operates normally. A high condition inhibits the TDRE bit in the ISR from becoming set. Transmission of the word currently in the shift register is completed but any
word in the TDR is held until CTS goes low.
TxD
NEXT CHARACTER IS SENT IMMEDIATELY
UPON CTS GOING LOW IF PROCESSOR
HAS ALREADY LOADED NEW DATA.
CHAR #n + 1
CHAR #n
EI]~EJ t'l~ GF['I-B-N'I-p--rl-t"-T.:I,,.:c:":::"::X:..:TT.:.:IN:..:U:..:O:..:U:..:s-,M:::A.:.:R::.K=--_O_T_H_E-;Rtr-W_--I'i_:---'~I ~A~.
STOP START
STOP
CHARACTER
IS NOT SENT
TDRE IS NOT SET
START
MPU
CLEARS
IRQ AGAIN
WHEN PROCESSOR
FINALLY LOADS
NEW DATA,
TRANSMISSION STARTS
LJI] CTSJ'---------------------J~ ~MEDIATELY
IRQ
CTS ________
\
-=CL=E=A::.R::..T:..:O::.-=SE=N~D=--_____~I
Figure 10_
MPU
CLEARS
IRQ
Effects of CTS on Transmitter
4-75
'\
CTS
I
iRQ
AND
INTERRUPT OCCURS,
INDICATING TRANSMIT
DATA REGISTER EMPTY
II
Dual Asynchronous Communications Interface Adapter (DACIA)
R68C552
ECHO MODE TIMING
underflow flag would be set and continuous Mark transmitted. If
Echo is initiated, the underflow flag will not be set at end of data
and continuous Mark will not be transmitted. Figure 11 shows the
relationship of RxD and TxD for Echo Mode.
In the Echo Mode, the TxD line re-transmits the data received on
the RxD line, delayed by 1/2 of a bit time. An internal underrun
mode must occur before Echo Mode will start transmitting. In normal transmit mode if TDRE occurs (indicating end of data) an
STOP
RxD
START
STOP
STOP
END OF
DATA
J1Ul~EI=~ +I ~ ~==~ t ILo-/
__
\ \ \ \ \ \ _______ ~O~6~N~gHU~ ::~~:
~ITW~~]~~[ ]is!J t I t [B~IB~I ]~]i] t [= ===
\1 \ \ \
TxD
START
\ \
STOP START
STOP~
STOP START
IF ECHO MODE,
NO UNDERFLOW,
THEREFORE NO
CONTINUOUS MARK
Figure 11.
Echo Mode Timing
CONTINUOUS DATA RECEIVE
CAUTION:
The normal receive mode sets the RDRF bit in the ISR when the
DACIA channel has received a full data word. This occurs at about
the 9/16 point through the stop bit. The processor must read the
RDR before the next stop bit, or an overrun error occurs. Figure 12
shows the relationship between IRQ and RxD for the continuous
Data Receive mode.
CHAR Un + 1
CHAR Un
/
When the Baud Rate Generator is the clock source, writing
to the Control or Format Registers of a channel with an active '
receiver can result in loss of data. Do not write to the Control or Format Registers when the receiver is shifting in data.
This precaution is not necessary on channels using the
external clock option, i.e., RxC.
I
....... /
I
CHAR Un + 2
'-/
CHAR Un + 3
I
'-/
I
"-
RX~ t ~~]~JiJ/I t [iO"F]==~/1 t ~=]~~EJ/I t [BO"FI=~I L
START
STOP: START
STOP:
I
'LIll
IR~r-rr------;LllJ'
IRQ PROCESSOR
INTERRUPT OCCURS
ABOUT 9116 INTO
LAST STOP BIT
PARITY OVERRUN,
AND FRAMING ERROR
UPDATED ALSO
)
START
I
\ ~
PROCESSOR READS
ISR, CAUSES
IRQ TO CLEAR
Figure 12.
START
I
LJlJ
PROCESSOR MUST READ
RECEIVER DATA IN THIS
TIME INTERVAL, OTHERWISE
OVERRUN OCCURS
Continuous Data Receive
4-76
STOP:
STOP:
I
L
Dual Asynchronous Communications Interface Adapter (DACIA)
R68C552
EFFECTS OF OVERRUN ON RECEIVER
contains the last word not read by the MPU and all following data
is lost. The receiver will return to normal operation when the RDR
is read. Figure 13 shows the relationship of IRQ and RxD when
overrun occurs.
If the processor does not read the RDR before the stop bit of the
next word, an overrun error occurs, the overrun bit is set in the ISR,
and the new data word is not transferred to the RDR. The RDR
CHAR #n + 1
CHAR #n
CHAR#n + 3
I
CHAR #n + 2
I
!
~/
I
'-./
'-./
"-./
JIll
[BJB;J ~]~;]iJ/l t r:FJ~ ]~;:G! I t ~~~ ~I I t ro-FI]~
I s1
I
I
IST~P I
RxD
STOP
IRQ
ART
STOP
L.JlJ
START
STOP
START
START
Il
It"
I
L -..."..._ _ __
PROCESSOR . / "
INTERRUPT
FOR RECEIVER
DATA REGISTER
MPU DOES
NOT READ
RDR. OVERRUN
~~
~S~
Figure 13.
MPU READS
ISR
CLEARS IRQ
CHAR #n + 2
IRQ.
CHAR #n + 1
IS LOST
Effects of Overrun on Receiver
RECEIVE BREAK CHARACTER
next character is to be received normally. Figure 14 shows the relationship of IRQ and RxD for a Receive Break Character.
In the event that a Break character is received by the receiver, the
Break bit is set. The receiver does not set the RDRF bit and
remains in this state until a stop bit is received. At this time the
------~'-.
RxD
EI~~;:
CONTINUOUS "BREAK"
I t IBolB'lnlBNI P,,! I
STopi START
STOP
I (\
i rr--l
L.lJ
U
------i
i
~N~~;~~~~R
FOR
RECEIVER
DATA REGISTER
FULL
I
m
t [BOJB0~]~I:J;11 t
I
I
START
IBoIB,j
START
,..----
L._...I.!
1 ~
Receive Break Character
4-77
STOP
I"
NO-+ " " NO INTERRUPT
MORE
SINCE RECEIVER.
PROCESSOR INTERRUPTS
DISABLED UNTIL
INTERRUPT
FIRST START BIT
WITH BREAK AND FRAMING ERROR BIT SET.
EVEN PARITY CHECK WILL ALSO GIVE A PARITY
ERROR BECAUSE ALL ZEROS (CONTINUOUS
BREAK) REPRESENT EVEN PARITY.
Figure 14.
"-./~----
STOP /
1
NORMAL
RECEIVER
INTERRUPT
Ii.II
__
Dual Asynchronous Communications Interface Adapter (DACIA)
R68C552
FRAMING ERROR
reflects the last data word received. Figure 15 shows the relationship of IRQ and RxD when a framing error occurs.
Framing error is caused by the absence of stop bit(s) on received
data. The framing error bit is set when the RDRF bit is set. Subsequent data words are tested separately, so the status bit always
RxD
(EXPECTED)
RxD
(ACTUAL)
IPROCESSOR
NOTES: 1. FRAMING ERROR DOES NOT
INHIBIT RECEIVER OPERATION.
INTERRUPT,
FRAMING
ERROR
BIT SET
2. IF NEXT DATA WORD IS OK,
FRAMING ERROR IS CLEARED.
Figure 15.
Framing Error
PARITY ERROR DETECT/ADDRESS
FRAME RECOGNITION
this type of operation, bit 0 of the ACR is set to a 1 and bits 2, 3
and 4 olthe FR select a parity checking mode. Then, ISR bit 2 will
be set to a 1 by incoming address frames and it will be a 0 on data
frames.
The Parity Status bit (ISR bit 2) may be programmed to indicate
parity errors (ACR bit 0 = 0) or to display the parity bit received
(ACR bit 0 = 1).
COMPARE MODE
In applications where parity checking is used, one of the parity
checking modes is enabled by setting bits 2, 3 and 4 of the Format Register to the desired option and bit 0 of the Auxiliary Control Register is reset to O. Then, when the RDRF bit (bit 0) is set
in the ISR, the PAR bit (bit 2) will be set when a parity error is
detected.
The Compare Mode is automatically enabled, i.e., the channel is
put to sleep, whenever data is written to the Compare Data
Register. NOTE: Bit 6 of the Control Register must be set to 0 to
enable access to the Compare Data Register. When the channel
is in the compare mode, the RDRF bit (bit 0 of the ISR) is forced
to a O. Upon receipt of a matching character, normal receiver operation resumes and the RDRF bit (bit 0 of the ISR) will be set upon
receipt of the next character.
In multi-drop applications, the parity bit is used as an address/data
flag. It is set to 1 for address frames and is 0 on data frame,S. For
4-78
Dual Asynchronous Communications Interface Adapter (DACIA)
R68C552
SPECIFICATIONS
DACIA READ/WRITE WAVEFORMS
-(1)-+~--0---1
RSO-RS2 ------i=====+===============~------~~====~============~~----~------'---,·II @DS -----~_,J @i\~~----------~
R/W
II,
----------1-,1~----0----~1r_------------,1-------0
CS
.
L~
I
..Ii
1---0- @
DO-D7------------t-~~_{========~==~~------_i~t=====~=======t~~k
~0-
_ _ _--r~_(0:r_,1 ~0
1-0j
~0~~--_++~10,~11
~e-----------_+-J~,
DTACK
~
I
I
I]
I
·------------READ CyCLE------------l\-.----------WRITE CyCLE--------+i'
'""I
DACIA READ/WRITE CYCLE TIMING
(Vee
= 5 Vdc
Number
±5%, VSS
= 0 Vdc, TA = TL to TH, unless otherwise noted)
Characteristic
Symbol
Min.
Typ.
Unil
-
ns
-
ns
320
ns
RIW, RSO·RS2 Valid to CS Low (Setup)
T RSU
2
CS Low to R/W, RSO·RS2 Invalid (Hold)
TRH
45
3
CS Pulse Width
Tcp
210
4
CS Low to DTACK Low
TCTl
160
5
CS High to DTACK High
TCTH
200
6
CS Low to Data Valid (Read)
Tcov
7
DTACK Low to Data Valid (Read)
TTDV
8
CS High to Data Invalid (Read)
TCOR
10
50
ns
9
Data Valid to CS High (Write, Setup)
Tosu
20
ns
10
CS High to Data Invalid (Write Hold)
Tcow
30
-
11
OS Low to CS Low (Delay for CS
derived from Data Strobe)
Tosc
4·79
0
Max.
1
-
ns
210
90
20
ns
ns
ns
ns
ns
Dual Asynchronous Communications Interface Adapter (DACIA)
R68C552
DACIA TRANSMIT/RECEIVER WAVEFORMS
TXC,RXC
TxD
------~~.~~--
@RTS, DTS _ _ _ _ _ _ _ _ _ _ _ __
DACIA INTERRUPT ACKNOWLEDGE WAVEFORMS
TRANSMIT/RECEIVE AND INTERRUPT ACKNOWLEDGE TIMING
(Vee = 5 Vdc
Number
± 5%, Vss
= 0 Vdc, TA = Tl to TH, unless otherwise noted)
Characteristic
Symbol
Min.
Max.
Unit
-
ns
TRANSMIT/RECEIVE TIMING
12
TransmiUReceive Clock Rate
tev
250
13
Transmit/Receive Clock High
IeH
100
14
TransmiUReceive Clock Low
tCl
100
15
TxC, RxC to TxD Propagation Delay
too
285
ns
16
TxC, RxC to IRQ Propagation Delay
tOI
-
250
ns
17
CTS, DCD, DSR Valid to IRQ Low
len
-
150
ns
18
IRQ Propagation Delay (Clear)
tlRQ
-
150
ns
19
RTS, DTR Propagation Delay
t DLy
-
150
ns
-
210
ns
-
ns
30
ns
ns
ns
INTERRUPT ACKNOWLEDGE TIMING
20
lACK Low to Data Valid
tloy
21
lACK Low to DTACK Low
tlTL
0
22
lACK High to DTACK High
tlTH
0
23
lACK High to Data Invalid
tlDZ
10
4·80
ns
R68C552
Dual Asynchronous Communications Interface·Adapter (DACIA)
ABSOLUTE MAXIMUM RATINGS·
Parameter
Supply Vollage
Input Voltage
Output Voltage
Operating Temperature
Commercial
Industrial
Symbol
Value
Unit
Vee
-0.3 to +7.0
Vde
V,N
-0.3 to Vee +0.3
Vde
Vour
-0.3 to Vee + 0.3
Vdc
·NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in other sections of this document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
°C
TA
o to +70
-40to +85
Storage Temperature
-55to +150
Tsm
°C
OPERATING CONDITIONS
Parameter
Supply Voltage
Temperature Range
Commercial
Industrial
Symbol
Value
Vee
5V±5%
TA
o to 70°C
- 40°C to + 85°C
DC CHARACTERISTICS
(Vee
=
5.0 V ±5%, Vss
=
0, TA
=
TL to T H, unless otherwise noted)
Parameter
Min
Symbol
Typ
Max
Unit
Test Conditions
Input High Voltage
Except XTALI and XTALO
XTALI and XTALO
V,H
Input Low Voltage
Except XTALI and XTALO
XTALI and XTALO
V,L
Input Leakage Current
RiW, RES, RSO, RS1, RS2, RxD, CTS, DCD, DSR, RxC,
TxC, CS, lACK
liN
-
10
50
~A
V,N = OV to 5.0V
Vce = 5.25V
Input Leakage Current for Three-State Off
DO-07
IrSi
-
±2
10
rA
V ,N = OAV to 2AV
Vee = 5.25V
Output High Voltage
DO-07, TxD, CLK OUT, RTS, DTR
VOH
-
-
V
Vcc = 4.75V
ILOAO = -100
Output Low Voltage
DO-07, TxD, CLK OUT, RTS, OTR
VOL
-
-
+004
V
Vee = 4.75V
ILOAO = 1.6 mA
Output Leakage Current (Off State)
IRQ, DTACK
10FF
-
±2
±10
pA
Vcc = 5.25V
Vour = 0 to 2AV
Power Dissipation
Po
-
-
10
mW/MHz
Input Capacitance
Except XTALI and XTALO
XTALI and XTALO
C'N
-
-
5
10
pF
pF
10
pF
Output Capacitance
V
+204
-
Vee + 0.3
Vce + 0.3
-0.3
-0.3
-
+0.8
+2.0
V
+204
-
-
Cour
Notes:
1. All units are direct current (dc) except for capacitance.
2. Negative sign indicates outward current flow, positive indicates inward flow.
3. Typical values are shown for Vee = 5.0V and TA = 25°C.
4-81
+004
Vee = 5.0V
V,N = OV
f = 2 MHz
TA = 25°C
rA
D
Dual Asynchronous Communications Interface Adapter (DACIA)
R68C552
PACKAGE DIMENSIONS
40-PIN CERAMIC DIP
[ D ]J]
I·1
w
~n
H~~LD
MILLIMETERS
A
G-ll-
K_ _J
MIN
MAX
A
50.29
51.31
1.980
2.020
B
15.11
15.88
0595
0.625
M-j
MIN
MAX
C
2.54
0.165
038
"9
0.53
0.100
D
0015
0.021
F
076
1.27
0.030
0.050
G
+
F
INCHES
DIM
H
2.54 BSC
0.100 esc
0.76
1.76
0030
0.070
J
020
0.33
K
254
4.19
0.008
0100
0165
L
14.60
15.37
0575
0.605
M
0°
100
0°
10°
N
051
1.52
0.020
0060
0.013
40-PIN PLASTIC DIP
MILLIMETERS
[~:::::::: ~::::::: ::Pr'~
~~
~ ~F
-1Hi-
--JGf+
..... 0
M
\
MIN
MAX
MIN
MAX
A
5182
52.32
2.040
2.060
B
1346
13.97
0530
0.550
C
3.56
508
0.140
0.200
D
0.38
0.53
0.015
0.021
F
102
1.52
0.040
0060
G
H
1.65
J
0.20
K
3.30
L
J-
INCHES
DIM
2.54 BSC
I
15.24
M
7°
N
0.51
0.065
0.OB5
0.008
0.012
4.32
0.130
0.170
esc
10°
I
0100 esc
2.16
0.30
1.02
0.600 sse
7°
0.020
10°
0.040
44-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
,-~g@
1~t:D2-j 'I
CORNER
TTf·
lIt± ""' ,
39O l0e
~
Ii
INDICATOR
L-17
28
~
j--+
A~
~'l
~8~
inrulnIlAA
I
-l k.
CHAM.
11 PINS
h)( 45· PER SIDE
3 PLCS EQUALLY
SPACES
~~
:<~
605
'~
5
»I fob
MILLIMETERS
I~
MIN
MAX
MIN
MAX
A
439
0.163
0.173
Al
41'
1.37
1.47
0.054
0.058
A2
2.31
2.46
0.091
.
~
"
SECTION A-A
TYP FOR BOTH AXIS (EXCEPT FOR BEVELED EDGE)
EJECTOR PIN MARKS
4 PLCS BOTTOM OF
PACKAGE ONLY
(TYPICAL)
BOTTOM VIEW
4-82
0.457 TYP
0.097
0.018 TVP
D
17.45
17.60
0.687
J 0.693
Dl
16.46
16,56
0.648
0,652
D2
12.62
12,78
0.497
0,503
D3
~~"'
INCHES
DIM
b
SIDE VIEW
CHAM,J )( 45·
~
SEATING PLANE
O;;l
""'
""
TOP VIEW
~039
V
15.75 REF
0,620 REF
e
1.27
esc
0.050 esc
h
J
1.15TVP
0.045 TVP
0,25 TYP
0.010TYP
a
45° TYP
45° TYP
0,89 TYP
0.035 TVP
0,25 TVP
0.010TVP
.,•
R68560 • R68561
~
'1'
Rockwell
R68560, R68561
Multi-Protocol Communications
Controller (M PCe)
DESCRIPTION
FEATURES
The R68560, R68561 Multi-Protocol Communications Controller
(MPCC) interfaces a single serial communications channel to
a 68008/68000 microcomputer-based system using either asynchronous or synchronous protocol. High speed bit rate, automatic formatting, low overhead programming, eight character
buffering, two channel DMA interface and three separate interrupt vector numbers optimize MPCC performance to take full
advantage of the 68008/68000 processing capabilities and
asynchronous bus structure.
• Full duplex synchronous/asynchronous receiver and transmitter
• Implements IBM Binary Synchronous Communications (BSC)
in two coding formats: ASCII and EBCDIC
• Supports other synchronous character-oriented protocols
(COP), such as six-bit BSC, X3.28k, ISO IS1745, ECMA-16, etc.
• Supports synchronous bit oriented protocols (BOP), such as
SDLC, HDLC, X.25, etc.
• Asynchronous and isochronous modes
• Modem handshake interface
• High speed serial data rate (DC to 4 MHz)
• Internal oscillator and baud rate generator with programmable data rate
• Crystal or TTL level clock input and buffered clock output
(8 MHz)
• Direct interface to 68008/68000 asynchronous bus
• Eight-character receiver and transmitter buffer registers
• 22 directly addressable registers for flexible option selection,
complete status reporting, and data transfer
• Three separate programmable interrupt vector numbers for
receiver, transmitter and serial interface
• Maskable interrupt conditions for receiver, transmitter and
serial interface
• Programmable microprocessor bus data transfer; polled, interrupt and two.channel DMA transfer compatible with
MC68440/MC68450
• Clock control register for receiver clock divisor and receiver
and transmitter clock routing
• Selectable full/half duplex, autoecho and local loop-back
modes
In synchronous operation, the MPCC supports bit-oriented
protocols (BOP), such as SDLC/HDLC, and character-oriented
protocols (COP), such as IBM Bisync (BSC) in either ASCII or
EBCDIC coding. Formatting, synchronizing, validation and error
detection is performed automatically in accordance with protocol
requirements and selected options. Asynchronous (ASYNC) and
isochronous (ISOC) modes are also supported. In addition,
modem interface handshake signals are available for general
use.
Control, status and data are transferred between the MPCC and
the microcomputer bus via 22 directly addressable registers and
a DMA interface. Two first-in first-out (FIFO) registers, addressable through separate receiver and transmitter data registers,
each buffer up to eight characters at a time to allow more MPU
processing time to service data received or to be transmitted
and to maximize bus throughput, especially during DMA operation. The two-channel Direct Memory Access (DMA) interface
operates with the MC68440/MC68450 DMA Controllers. Three
prioritized interrupt vector numbers separately support receiver,
transmitter and modem interface operation.
An on-chip oscillator drives the internal baud rate generator
(BRG) and an external clock output with an 8 MHz input crystal
or clock frequency. The BRG, in conjunction with two selectable prescalers and 16-bit programmable divisor, provides a data
bit rate of DC to 4 MHz.
• Selectable parity (enable, odd, even) and CRC (control field
enable, CRC-16, CCITT V.41, VRC/LRC)
ORDERING INFORMATION
Part Number
The 48-pin R68561 supports word-length (16-bit) operation when
connected to the 68000 15-bit asynchronous bus, as well as bytelength (8-bit) operation when connected to the 68008 8-bit bus.
The 40-pin R68560 supports byte-length operation on the 68008
bus.
R68S6
T
LI
Frequency
Temperature Range
4 MHz
O·C to 7O·C
Package: C = Ceramic
P = Plastic
Number of pins: 0 = 40
1 = 48
Document No. 68650N06
Product Description
4-83
Order No. 705
Rev. 6, June 1987
II
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
Vcc-"
1-..-------
GND--..
T,D
TO Rx LOGIC
(TEST MODE)
BUS
MICROPROCESSOR
iiCR
iRQ
flO.D7'
DD-D15 2
INTERFACE,
'\r---.."...--....,..,/\
os
CONTROL
REGISTERS
~
STATUS
•~~m
CTs
DcO
~
~~~~~~R:E:GI:ST:E:RS~
BAUD RATE GENERATOR
t - - - - - - - - - - - - - I - - - - - - TxC
RxFlFO READ
.----_BCLK
TxFIFO WRITE
EXTAL
XTAL
~===:::j
r----i
t-----+------
DMA
INTERFACE
R,C
RxFIFO READ
ToTx LOGIC
(ECHO MODE)
T,D
(TEST MODE)
t------<~-- R,D
NOTES:
1. R68560 ONLY.
2. R68561 ONLY.
3. UOS ON R68561 AD ON R68560
4. LOS ON R68561 OS ON R68560
Figure 1.
MPCC Block Diagram
PIN DESCRIPTION
A1-A4-Address Lines. A1-M are active high inputs used in
conjunction with the CS input to access the internal registers.
The address map for these registers is shown in Table 1.
Throughout the document. signals are presented using the terms
active and inactive or asserted and negated independently of
whether the signal is active in the high·voltage state or low·
voltage state. (The active state of each logic pin is described
below.) Active low signals are denoted by a superscript bar. For
example. RiW indicates write is active low and read is active
high.
DO-D15-Data Lines. The bidirectional data lines transfer data
between the MPCC and the MPU, memory or other peripheral
device. DO-D15 are used when connected to the 16·bit 68000
bus and operating in the MPCC word mode. DO-D7 are used
when connected to the 16·bit 68000 bus or the 8·bit 68008 bus
and operating in the MPCC byte mode. The data bus is three·
stated when CS is inactive. (See exceptions in DMA mode.)
Note: The R68561 interface is described for word mode opera·
tion only and the R68560 interface is described for byte
mode operation only.
4·84
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
CS-Chip Select. CS low selects the MPCC for programmed
transfers with the host. The MPCC is deselected when the CS
input is inactive in non-DMA mode. CS must be decoded from
the address bus and gated with address strobe (AS).
UDS-Upper Data Strobe (R68561). When interfacing to a
16-bit data bus system such as the 68000, a low on control bus
signal UDS enables access to the upper data byte on D8-D15.
A high on UDS disables access to D8-Dt5. Data is latched and
enabled in conjunction with LDS.
RtW-ReadlWrite. Rm controls the direction of data flow
through the bidirectional data bus by indicating that the current
bus cycle is a read (high) or write (low) cycle.
IRQ-Interrupt Request. The active low IRQ output requests
interrupt service by the MPU. IRQ is driven high after assertion
prior to being tri-stated.
DTACK-Oata Transfer Acknowledge. DTACK is an active
low output that signals the completion of the bus cycle. During
read or interrupt acknowledge cycles, DTACK is asserted by
the MPCC after data has been provided on the data bus; during
write cycles it is asserted after data has been accepted at the
data bus. DTACK is driven high after assertion prior to being
tri-stated. A holding resistor is required to maintain OTACK high
between bus cycles.
lACK-Interrupt Acknowledge. The active low lACK input
indicates that the current bus cycle is an interrupt acknowledge
cycle. When lACK is asserted the MPCC places an interrupt
vector on the lower byte (DO-D7) of the data bus.
TDSR-Transmitter Data Service Request. When Transmitter DMA mode is active, the low TDSR output requests DMA
service.
OS-Data Strobe (R6856D). During a write (R/Iii low), the
DS positive transition latches data on data bus lines DO-D7
into the MPCC. During a read (Rm high), DS low enables data
from the MPCC to data bus lines DO-D7.
ROSR-Receiver Data Service Request. When receiver DMA
mode is active, the low RDSR output requests DMA service.
OACK-OMA Acknowledge. The DACK low input indicates
that the data bus has been acquired by the DMAC and that the
requested bus cycle is beginning.
LOS-Lower Data Strobe (R68561). During a write (Rm low),
the positive transition latches data on the data bus lines DO-D7
(and on D8-D15 if UDS is low) into the MPCC. During a read
(Rm high), LDS low enables data from the MPCC to DO-D7
(and to D8-D15 if UDS is lOW).
OTC-Data Transfer Complete. On a 68000 bus, the DTC low
input indicates that a DMA data transfer was completed with no
bus conflicts. DTC in response to a RDSR indicates that the data
has been successfully stored in memory. DTC in response to
a TDSR indicates that the data is present on the data bus for
strobing into the MPCC. If not used, this input should be connected to ground.
AD-Address Line AD (R68560). When interfaCing to an 8-bit
data bus system such as the 68008, address line AD is used
to access an internal register. AD = 0 defines an even register
and AD = 1 defines an odd register. See Table 1b.
DATA
BUS
ADDRESS
BUS
<
A1-A4
RTS
CTS
DTR
DSR
DCD
.
UDS/AO
LDS/DS
CS
ASYNCHRONOUS
BUS
CONTROL
R/W
DMA
CONTROL
INTERRUPT
CONTROL
DO-D15
{
DTACK
RESET
TDSR
RDSR
DACK
DONE
DTC
IRQ
lACK
Figure 2.
R68560/
R68561
MPCC
}
TxD
TxC
} TRANSMITTER
INTERFACE
RxD
RxC
}
RECEIVER
INTERFACE
EXTAL
XTAL
BCLK
}
CLOCK
INTERFACE
Vee
GND
MPCC Input and Output Signals
4-85
MODEM
INTERFACE
II
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
DONE-Done. DONE is a bidirectional active low signal. The
DONE signal is asserted by the DMAC when the DMA transfer
count is exhausted and there is no more data to be transferred,
or asserted by the MPCC when the status byte following the last
character of a frame (block) is being transferred in response to
a RDSA. The DONE signal asserted by the DMAC in response
to a TDSR will be stored to track with the data byte (lower
byte for word transfer) through the TxFIFO.
DCD-Data Carrier Detect. The DCD active low input positive
transition and level are reported in the DCDT and DCDLVL bits
in the the SISR, respectively.
TxD-Transmitted Data. The MPCC transmits serial data on the
TxD output. The TxD output changes on the negative going edge
of TxC.
RxD-Received Data. The MPCC receives serial data on the RxD
input. The RxD input is shifted into the receiver with the negative going edge of RxC.
RESET-Reset. RESET is an active low, high impedance
input that initializes all MPCC functions. RESET must be
asserted for at least 500 ns to initialize the MPCC.
TxC-Transmitter Clock. TxC can be programmed to be an input
or an output. When TxC is selected to be an input, the transmitter
clock must be provided externally. When TxC is programmed to
be an output, a clock is generated by the MPCC's internal baud
rate generator.
DTR-Data Terminal Ready. The DTR active low output is
general purpose in nature, and is controlled by the DTRLVL bit
in the Serial Interface Control Register (SICR).
RxC-Reeeiver Clock. RxC provides the MPCC receiver with
received data timing information.
EXTAL-CrystallExternal Clock Input.
XTAL Crystal Return. EXTAL and XTAL connect a 20 kHz to
8.064 MHz parallel resonant external crystal to the MPCC internal oscillator (see CLOCK OSCILLATOR). The pin EXTAL may
also be used as a TTL level input to supply DC to 8 MHz reference timing from an external clock source. XTAL must be tied
to ground when applying an external clock to the EXTAL input.
RTS-Request to Send. The RTS active low output is general
purpose in nature, and is controlled by the RTSLVL bit in the
SICR.
CTS-Clear to Send. The CTS active low input positive transition and level are reported in the CTST and CTSLVL bits in the
Serial Interface Status Register (SISR), respectively.
BCLK-Buffered Clock. BCLK is the internal oscillator buffered
output available to other MPCC devices eliminating the need for
additional crystals.
DSR-Data Set Ready. The DSR active low input negative
transition and level are reported in the DSRT and DSRLVL bits
in the SISR, respectively. DSR is also an output for RSYN.
UOS
OTACK
RxO
010
OTR
OSR
OCO
011
ROSR
AI
GNO
A4
A2
A3
RxC
012
TxC
BCLK
EXTAL
XTAL
013
RJW
IRQ
RTS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
17
18
19
20
21
22
23
24
Vee-Power.5V ±5%.
GND-Ground. Ground (Vss).
lACK
LOS
OTC
09
CS
OACK
GNO
DO
08
01
02
03
04
05
06
015
07
RESET
CTS
AO
OTACK
RxO
OTR
OSR
OCO
ROSR
AI
GNO
A4
A2
A3
RxC
TxC
BCLK
EXTAL
XTAL
Vee
014
DONE
TxO
TOSR
RJW
IRQ
RTS
R68561
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R68560
Pin Configuration
4-86
lACK
OS
OTC
CS
OACK
GNO
DO
01
02
03
04
05
06
07
RESET
CTS
Vee
DONE
TxO
TOSR
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
MPCC REGISTERS
Table 2 summarizes the MPCC register bit assignments and their
access. A read from an unassigned location results in a read
from a "null register." A null register returns all ones for data
and results in a normal bus cycle. Unused bits of a defined
register are read as zeros unless otherwise noted.
Twenty-two registers control and monitor the MPCC operation.
The registers and their addresses are identified in Table 1a
(A6B561 operation in word mode) and in Table lb (A6B560 operation in byte mode). When the A68561 is operated in the word
mode, two registers are read or written at a time starting at an
even boundary. When the A68560 is operated in the byte mode,
each register is explicitly addressed based on AO.
Table 1a_
A68561 Accessible Registers (Word Mode)
Register(s)
15
(Odd Registers)
7
8
Receiver Control Register (RCR)
(Even Registers)
R/W
Addr
(Hex.)
Address Lines
A4 A3 A2 Al
RIW
00
0
0
0
R
02
0
0
0
1
04
0
0
1
0
0
0
Receiver Status Register (RSR)
Receiver Data Register (RDR)-16 bits'
0
Receiver Interrupt Enable Register (RIER)
Receiver Interrupt Vector Number Register (RIVNR)
RIW
Transmitter Control Register (TCR)
Transmitter Status Register (TSR)
RIW
08
0
1
0
W
OA
0
1
0
1
Transmitter Data Register (TDR)-16 bits2
Transmitter Interrupt Enable Register (TIER)
Transmitter Interrupt Vector Number Register (TIVNR)
RIW
OC
0
1
1
0
Serial Interface Control Register (SICR)
Serial Interface Status Register (SISR)
RIW
10
1
0
0
0
RIW
12
1
0
0
1
Serial Interrupt Vector Number Register (SIVNR)
RIW
14
1
0
1
0
Protocol Select Register 2 (PSR2)
Protocol Select Register (PSR1)
RIW
18
1
1
0
0
Address Register 2 (AR2)
Address Register 1 (AR1)
RIW
lA
1
1
0
1
Baud Rate Divider Register 2 (BRDR2)
Baud Rate Divider Register 1 (BRDR1)
RIW
lC
1
1
1
0
Error Control Register (ECR)
Clock Control Register (CCR)
RIW
lE
1
1
1
1
Reserved 3
Reserved 3
Serial Interrupt Enable Register (SIER)
Notes:
1. Accessible register of the four word R,FIFO. The data is not initialized, however, RES resets the R,FIFO pointer to the start of the first word.
2. Accessible register of the four word T,FIFO. The data is not initialized, however, RES resets the T,FIFO pOinter to the start of the first word.
3. Reserved registers may contain random bit values.
CLOCK OSCILLATOR
C, = 2C L
-
12 pF
An on-chip oscillator is designed for a parallel resonant crystal
connected between XTLI and XTLO pins. The equivalent oscillator circuit is shown in the figure below.
C2 =2C L
-
33 pF
As/R
_2xl0·
smax - (FCd2
where: F is in MHz; C and C L are in pF; A is in ohms.
C, ± 5%
G~
-=-
EXTAL
0
C2 ±5%
J. ,"
12 pF
!-----+---l
XTAL
To select a parallel resonant crystal for the oscillator, first select
the load capacitance from a crystal manufacturer's catalog. Nexl,
calculate Asmax based on F and CL• The selected crystal must
have a As less than the Asmax.
33 pF
For example, if C L = 20 pF for an 8.064 MHz parallel resonant
crystal, then
-=-
C, = 40 - 12 = 28 pF (Use standard value of 27 pF.)
C2 =
40 - 33 = 7 pF (Use standard value of 6.8 pF.)
Note: Cx = Total Shunt Capacitance including that due to
board layout.
A parallel resonant crystal is specified by its load capacitance
and series resonant resistance. For proper oscillator operation,
the load capacitance (C,), series resistance (As) and the crystal resonant frequency (F) must meet the following two relations:
The series resistance of the crystal must be less than
Asmax =
4-87
2 X 10·
= 77 ohms
(8.064 x 20)2
II
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
Table 1b.
R68560 Accessible Registers (Byte Mode)
Address Lines
Reglster(s)
A4
A3
A2
Al
AD
0
o
7
Receiver Status Register (RSR)
RIW
00
0
0
0
0
Receiver Control Register (RCR)
RIW
01
0
0
0
0
1
R
02
0
0
0
1
0
Receiver Data Register (RDR)-8 bits'
03
0
0
0
1
1
Receiver Interrupt Vector Number Register (RIVNR)
RIW
04
0
0
1
0
0
Receiver Interrupt Enable Register (RIER)
RIW
05
0
0
1
0
1
Transmitter Status Register (TSR)
RIW
08
0
1
0
0
0
Transmitter Control Register (TCR)
RIW
09
0
1
0
0
1
W
OA
0
1
0
1
0
Reserved3
Transmitter Data Register (TDR)2-8 bits
Reserved3
OB
0
1
0
1
1
Transmitter Interrupt Vector Number Register (TIVNR)
RIW
OC
0
1
1
0
0
Transmitter Interrupt Enable Register (TIER)
RIW
00
0
1
1
0
1
Serial Interface Status Register (SISR)
RIW
10
1
0
0
0
0
Serial Interface Control Register (SICR)
RIW
11
1
0
0
0
1
12
1
0
0
1
0
Reserved 3
13
1
0
0
1
1
Serial Interrupt Vector Number Register (SIVNR)
Reserved 3
RIW
14
1
0
1
0
0
Serial Interrupt Enable Register (SIER)
RIW
15
1
0
1
0
1
Protocol Select Register 1 (PSR1)
RIW
18
1
1
0
0
0
Protocol Select Register 2 (PSR2)
RIW
19
1
1
0
0
1
Address Register 1 (AR1)
RIW
lA
1
1
0
1
0
Address Register 2 (AR2)
RIW
lB
1
1
0
1
1
Baud Rate Divider Register 1 (BRDR1)
RIW
1C
1
1
1
0
0
Baud Rate Divider Register 2 (BRDR2)
RIW
10
1
1
1
0
1
Clock Control Register (CCR)
RIW
lE
1
1
1
1
0
Error Control Register (ECR)
RIW
1F
1
1
1
1
1
Notes:
1. Accessible register of the eight byte RxFIFO. The data is not initialized, however, RES resets the RxFIFO painter to the start of the first byte.
2. Accessible register of the eight byte TxFIFO. The data is not initialized, however, RES resets the TxFIFO pointer to the start of the first byte.
3. Reserved registers may contain random bit values.
4·88
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
Table 2.
MPCC Register Bit Assignments
Bit Number
RIW
Access
7
6
5
4
3
2
1
0
Resetl'l
Value
RIW
RDA
EOF
0
C/PERR
FRERR
ROVRN
RNB
RIDLE
00
Receiver Status
Register (RSR)
RIW
0
RDSREN
DONEEN
RSYNEN
STRSYN
0
RABTEN
RRES
Ot
Receiver Control
Register (RCR)
Receiver Data
Register (RDR)
R
RECEIVER DATA (RxFIFO)2
--
RIW
RECEIVER INTERRUPT VECTOR NUMBER (RIVN)
OF
Receiver Interrupt Vector
Number Register (RIVNR)
RIW
RDA
IE
EOF
IE
0
C/PERR
IE
FRERR
IE
ROVRN
IE
RNB
IE
0
00
Receiver Interrupt Enable
Register (RIER)
RIW
TORA
TFC
0
0
0
TUNRN
TFERR
0
80
Transmitter Status
Register (TSR)
RIW
TEN
TOSREN
TICS
THW
TLAST
TSYN
TABT
TRES
01
Transmitter Control
Register (TCR)
Transmitter Data
Register (TOR)
W
TRANSMITTER DATA (TxFIFO)2
--
RIW
TRANSMITTER INTERRUPT VECTOR NUMBER (TIVN)
OF
Transmitter Interrupt Vector
Number Register (TIVNR)
RIW
lORA
IE
TFC
IE
0
0
0
TUNRN
IE
TFERR
IE
0
00
Transmitter Interrupt Enable
Register (TIER)
RIW
CTST
DSRT
DCDT
CTSLVL
DSRLVL
DCDLVL
0
0
00
Serial Interface Status
Register (SISR)
RIW
RTSLVL
DTRLVL
0
0
0
ECHO
TEST
0
00
Serial Interface Control
Register (SICR)
RIW
RANDOM BIT VALUES
(reserved)
RANDOM BIT VALUES
(reserved)
CTS
IE
DSR
IE
DCD
IE
0
0
0
0
RIW
0
0
0
0
0
0
CTLEX
RIW
WD/BYT
RIW
OF
Serial Interrupt Vector
Number Register (SIVNR)
0
00
Serial Interrupt Enable
Register (SIER)
ADDEX
00
Protocol Select
Register 1 (PSF,ll)
00
Protocol Select
Register 2 (PSR2)
SERIAL INTERRUPT VECTOR NUMBER (SIVN)
STOP BIT SEL
SB2
I
SBI
CHAR LEN SEL
CL2
I
I
PROTOCOL SEL
CLI
PS3
PS2
I
PSl
RIW
BOP ADDRESs/BSC & COP PAD
00
Address Register 1 (AR1)
RIW
BOP ADDRESS/BSC & COP SYN
00
Address Register 2 (AR2)
RIW
BAUD RATE DIVIDER (LSH)
01
Baud Rate Divider
Register 1 (BRDR1)
RIW
BAUD RATE DIVIDER (MSH)
00
Baud Rate Divider
Register 2 (BRDR2)
00
Clock Control
Register (CCR)
04
Error Control
Register (ECR)
RIW
0
0
0
PSCDIV
TeLKO
RCLKIN
RIW
PAREN
ODDPAR
0
0
CFCRC
CRCPRE
Notes:
1. RESET = Register contents upon power up or RESET.
2. 16·bits for R68561 (word mode); a·bits for R68560 (byte mode).
4·89
CLK DIV
CK2
I
CKl
CRC SEL
CR2
I
CRt
II
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
REGISTER DEFINITIONS
RSR
~
o
RECEIVER REGISTERS
1
Receiver Status Register (RSR)
Address = 00
Reset Value = $00
The Receiver Status Register (RSR) contains the status of the
receiver including error conditions. Status bits are cleared by
writing a 1 into respective positions, by writing a 1 into the RCR
RRES bit or by RESET. If an EOF, C/PERR, or FRERR is set
in the RSR, the data reflecting the error (the next byte or word
in the RxFIFO) must be read prior to resetting the corresponding status bit in the RSR. The IRQ output is asserted if any
of the conditions reported by the status bits occur and the corresponding interrupt enable bit in the RIER is set.
C/PERR -CRC/Parity Error.
No CRC or parity error detected.
CRC error detected (BOP, BSC) or parity error
detected (ASYNC, ISOC and COP). The C/PERR bit
is loaded into the RxFIFO with the negative-going RxC
edge, along with the byte or word with which it is
associated. For ASYNC, ISOCH or COP protocols, this
is with the byte/word containing a parity error. For BOP
or BSC, it is loaded to RxFIFO (after the CRC check)
with the FSB. C/PERR is loaded into the RSR and the
interrupt issued (when the read pointer is positioned
at the FSB) with the trailing edge of LOS.
C/PERR Reset - The byte/word containing the FSB must be
read from the RxFIFO before resetting the C/PERR bit. Then
it may be reset by writing a 1 to RSR4.
RSR
3 FRERR
-Frame Error.
-0No frame error detected.
1
FRERR is set for receiver overrun, flag detected off
boundary (BOP), or frame error (ASYNC, ISOCH). For
receiver overrun, the FRERR bit is set in the RxFIFO
with the last byte when the overrun is detected.
The RSR format is the same as the frame status format (see
below) except as noted.
RSR
~
o
For BOP, a minimum message size is an opening flag,
one address byte and one control byte. If the closing
flag is detected before the control byte is sent, a short
frame is indicated and a frame error results. For
address extension, multi-address bytes may be
received before the control byte is expected. The
FRERR bit is latched in RxFIFO with the negative-going
edge of RxC with the last address byte received upon
detection of the flag off boundary. FRERR is loaded
into the RSR and the interrupt issued when the read
pointer is positioned at the FSB with the trailing edge
of LOS.
RDA
-Receiver Data Available. (RSR only).
The FxFIFO is empty (i.e., no received data is
available).
ROA is set and an interrupt issued (if enabled) when
the RxFIFO has 1 to 8 bytes, or 1 to 4 words, of data
in it.
ROA Reset - ROA cannot be cleared or reset in software. It
is initialized to 0 upon hardware reset and remains 0 if no data
has been received. It is set to a 1 and an interrupt issued when
a data byte/word is loaded to the RxFIFO with the negative edge
of RxC coincident with the first bit of the next byte transmitted. It is automatically reset to 0 when the last byte/word is
read from the RxFIFO by the host through ROA.
In ASYNC or ISOCH, a FRERR bit set indicates that
the stop bit was detected off boundary (too early or too
late for the number of bits expected by the setting of
PSR2-3 and PSR2-4) or it was not the correct width
(as expected by the setting of PSR2-6 and PSR2-5).
RSR
...§..... EOF
-End of Frame. (BOP and BSC)
No end of frame has been detected.
1
The closing flag (BOP) or pad (BSC) has been
detected. EOF is loaded in the RxFIFO along with the
FSB with which it is associated. The EOF is loaded into
the RSR and the interrupt issued, if enabled, (when
the RxFIFO read pointer is positioned at the FSB) with
the trailing edge of LOS.
o
FRERR Reset - The byte/word containing the FSB must be
read from the RxFIFO before resetting the C/PERR bit. The
C/PERR bit may then be reset by writing a 1 to RSR3.
RSR
2 ROVRN
-Receiver Overrun.
-0No receiver overrun detected.
1
Receiver overrun detected. Data is loaded into the
RxFIFO on byte boundaries with the negative-going
edge of RxC coincident with the first bit of the subsequent data being received. When the eighth byte, or
fourth word, of data has been written into RxFIFO
without any data being read out, the RxFIFO is full and
the incremented write pointer "catches up" with the
read pointer. The next attempt to write data to RxFIFO
causes ROVRN bit to be loaded to the RSR and the
interrupt issued (if enabled). The data in the RxFIFO
is not affected, but new received data is lost.
EOF Reset - The byte/word containing the FSB must be read
from the RxFIFO before resetting the EOF bit. Then EOF may
be reset by writing a 1 to RSR6.
RSR
_5_ RHW
o
-Receive Half Word. (Frame Status only)*
The last word of the frame contains data on the upper
half (08-015) and frame status on the lower half
(00-07) of the data bus.
The lower half of the data bus (00-07) contains the
frame status but the upper half (D8-015) is blank or
invalid.
ROVRN Reset - The ROVRN bit is not self-clearing when data
is read from the RxFIFO, but may be reset by writing a 1 to RSR2.
'See Frame Status (RSR) on next page.
4-90
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
tents, the frame status byte has a RHW status in bit 5 which
indicates either an even or odd boundary (applicable to word
mode only).
RSR
_1_ RAtB
-Receiver Abort/Break.
o
Normal Operation.
(BOP) When an ABORT (seven Is) is detected after
the opening flag, the RAJB bit is set in the RSR and
an interrupt issued (if enabled). This bit is latched with
the negative edge of RxC after the seventh 1 bit is
detected. (NOTE: Because the previous byte can end
in zero to five 1 bits, the abort could be recognized in
the next byte as early as two to seven 1 bits.)
If the MPCC is in word mode and the last data byte was on an
even byte boundary (i.e., there was an even number of bytes
in the message), a blank byte will be loaded into the RxFIFO
prior to loading the frame status byte in order to force the "frame
status" byte and the next frame to be on an even boundary.
When RHW = 0, the last word of the frame contains data on
the upper half and status on the lower half of the data bus. If
RHW = I, the lower half of the bus contains status but the upper
half is a blank or invalid byte.
(BSC) When ENQ is detected in a block of text data,
the RAJB bit is set in the RSR and the interrupt issued
(if enabled) with the next negative edge of the RxC
clock.
RAJB Reset -
In the byte mode, the status byte will always immediately follow
the last data byte of the block/frame (see Figure 3). The EOF
status in the RSR is then set when the byte/word containing the
frame status is the next byte/word to be read from the RxFIFO.
The RAJB bit is reset by writing a 1 to RSRI.
In the receiver DMA mode, when the EOF status in the RSR
is set, DONE is asserted to the DMAC. Thus the last byte
accessed by the DMAC is always a status byte, which the
processor may read to check the validity of entire frame.
RSR
_0_ RIDLE
o
1
-Receiver Idle. (BOP only).
Receiver is not idle.
15 or more Is have been detected. The RIDLE bit is
set in RSR with the negative edge of the next RxC after
15 consecutive 1s have been detected.
Receiver Control Register (RCR)
RIDLE Reset - The RIDLE is reset by writing a 1 to RSRO.
(NOTE: The RIDLE bit will set again in 15 clock cycles if RxD
is still in the idle condition.)
Address = 01
* Frame Status (RSR)
The Receiver Control Register (RCR) selects receiver control
options.
Reset value
= $01
RCR
2For the BSC and BOP protocols which have defined message
blocks or frames, a "frame status" byte will be loaded into the
RxFIFO following the last data byte of each block. The frame
status contains all the status contained within the RSR with the
exception of RDA and RIDLE. But, in addition to the RSR con·
-Not used.
RCR
-.!L.
o
1
RDSREN -Receiver Data Service Request Enable.
Disable receiver DMA mode.
Enable receiver DMA mode.
ODD NUMBER OF BYTES
015
WORD
WORD
MODE
N
N + 1
08
EVEN NUMBER OF BYTES
DO
07
015
WORD
0807
STATUS
N
NEXT
FRAME
N + 1
BLANK
STATUS
N+2
NEXT
FRAME
(RHW = 0)
DATA
DATA
(RHW = 1)
M
BYTE
MODE
DO
07
BYTE
BYTE
DATA
07
M
DO
DATA
M + 1
STATUS
M + 1
STATUS
M+2
NEXT FRAME
M+2
NEXT FRAME
Figure 3.
DO
DATA
BSC/BOP Block/Frame Status Location
4·91
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
RCR
-.L
o
1
Receiver Interrupt Vector Number Register (RIVNR)
DONEEN -DONE Output Enable.
Disable DONE output.
Enable DONE output. (When the receiver is in the DMA
mode, Le., RDSREN = 1).
If a receiver interrupt condition occurs (as reported by status
bits in the RSR that correspond to interrupt enable bits in the
RIER) and the corresponding bit is set in the RIER, IRQ output
is asserted to request MPU receiver interrupt service. When the
lACK input is asserted from the bus, the Receiver Interrupt Vector Number (RIVN) from the Receiver Interrupt Vector Number
Register (RIVNR) is placed on the data bus.
RCR
-L
o
1
Reset value = $OF
Address = 04
RSYNEN
-RSVNEN Output Enable. Selects the
DSR signal input or the RSYN SYNC
signal output on the DSR pin.
Input DSR on DSA.
Output RSYN on DSA.
RCR
~
o
1
Receiver Interrupt Enable Register (RIER)
STRSYN -Strip SYN Character (COP only).
Do not strip SYN character.
Strip SYN character.
RCR
_2_ MUST BE ZERO
Address = 05
o
Reset value = $00
The Receiver Interrupt Enable Register (RIER) contains interrupt enable bits for the Receiver Status Register (RSR). When
enabled, the IRQ output is asserted when the corresponding
condition is detected and reported in the RSA.
RCR
_1_ RABTEN -Receiver Abort Enable (BOP only).
o
Do not abort frame upon error detection.
1
Abort frame upon RxFIFO overrun (ROVRN bit = 1 in
the RSR) or CFCRC error detection (C/PERR bit = 1
in the RSR). If either error occurs, the MPCC ignores
the remainder of the current frame and searches for
the beginning of the next frame. (EOF is set upon
abort).
RIER
_7_ RDA IE
o
1
-Receiver Data Available Interrupt
Enable.
Disable RDA Interrupt.
Enable RDA Interrupt.
RIER
_6_ EOF IE
-End of Frame Interrupt Enable.
o
Disable EOF Interrupt.
Enable EOF Interrupt.
RCR
_0_ RRES
-Receiver Reset Command.
o
Enable normal receiver operation.
1
Reset receiver. Resets the receiver section including
the RxFIFO and the RSR (but not the RCR). RRES is
set by RESET or by writing a 1 into this bit and must
be cleared by writing a 0 into this bit. RRES requires
clearing after RESET.
RIER
_5_
-Not used.
RIER
_4_ C/PERR IE -CRC/Parity Error Interrupt Enable.
o
Disable C/PERR Interrupt.
Enable C/PERR Interrupt.
Receiver Data Register (RDR)
RIER
_3_ FRERR IE -Frame Error Interrupt Enable.
o
Disable FRERR Interrupt.
1
Enable FRERR Interrupt.
R68560 (Byte Mode)
4
MSB
3
Byte 0
RIER
_2_ ROVRN IE -Receiver Overrun Interrupt Enable.
o
Disable ROVRN Interrupt.
1
Enable ROVRN Interrupt.
o
2
LSB
Address = 02
RIER
_1_ RA/B IE
-Receiver Abort/Break Interrupt Enable.
o
Disable RNB Interrupt.
1
Enable RNB Interrupt.
The receiver has an B-byte (or 4-word) First In First Out (FIFO)
register file (RxFIFO) where received data are stored before
being transferred to the bus. The received data is transferred
out of the RxFIFO via the RDR in B-bit bytes or 16-bit words depending on the WD/BYT bit selting in PSR2. When the RxFIFO
has a data byte/word ready to be transferred, the RDA status
bit in the RSR is set to 1.
RIER
_0_
4-92
-Not used.
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
TRANSMITTER REGISTERS
The TUNRN bit is set in TSR2 and the interrupt issued
with the positive edge of the TxC coincident with the
eighth bit of data prior to the ABORT in BOP or to SYN
in BSC or COP.
Transmitter Status Register (TSR)
2
TUNRN
Address = 08
TUNRN Reset - One full cycle of the serial clock (TxC) must
elapse before the TUNRN bit can be reset by writing a 1 to TSR2.
TFERR
Reset value = $80
The Transmitter Status Register (TSR) contains the transmitter
status including error conditions. The transmitter status bits are
cleared by writing a 1 into their respective positions, by writing
a 1 into the TCR TRES bit, or by RESET. The IRQ output is
asserted if any of the conditions reported by the status bits occur
and the corresponding interrupt enable bit in the TIER is set.
TSR
_1_ TFERR
-Transmit Frame Error (BOP only).
o
No frame error has occurred.
1
A short frame condition exists in that no control field
is transmitted. (TLAST was issued early with an
address byte.) TFERR bit is set and the interrupt issued
with the positive edge of TxC coincident with the end
of the last bit of the byte causing the error.
TSR
_7_ TDRA
-Transmitter Data Register Available.
o
The TxFIFO is full.
1
The TxFIFO is available to be loaded via the TOR
(1 to 8 bytes, or 1 to 4 words).
TFERR Reset - One full cycle of the serial clock (TxC)
must elapse before TFERR bit can be reset by writing
a 1 to TSR1.
TDRA Reset - TDRA cannot be reset by the host in normal
operation. It initializes to a 1 upon hardware or software reset
of the MPCC. TDRA is not dependent on the serial clock.
Transmitter Control Register (TCR)
TSR
Address = 09
~
o
-Transmitted Frame Complete. (BOP, BSC
and COP only).
(All) Frame not complete.
(BOP) Closing flag or ABORT has been transmitted.
The TFC bit is set and the interrupt issued (if enabled)
with 1,he negative edge of TxC coincident with the end
of the last bit of the flag. When TABT is set in TCR1,
an ABORT is transmitted immediately but TFC is not
issued until after the closing flag or 8 bits of the MARK
idle condition after the TxFIFO is flushed of all current
data bytes.
The Transmitter Control Register (TCR) selects transmitter control function.
TCR
~
o
o
1
(COP) Last byte has been transmitted (TLAST set in
TCR3). TFC bit set andlor interrupt issued with negative edge of the TxC coincident with the end of the last
bit of the last byte.
TCR
o
TSR
-Not used.
TSR
_2_ TUNRN
1
-Transmitter Data Service Request
Enable.
Disable transmitter DMA mode.
Enable transmitter DMA mode.
_5_ TICS
TFC Reset - One full cycle of the serial clock (TxC) must elapse
before the TFC bit can be reset by writing a 1 to TSR6.
..H..
TEN
-Transmitter Enable.
Disable transmitter. TxD output is idled. The TxFIFO
may be loaded while the transmitter is disabled.
Enable transmitter.
TCR
_6_ TDSREN
(BSC) Trailing pad has been transmitted. TFC bit set
andlor interrupt issued with negative edge of TxC coincident with the end 'of the last bit of the trailing pad.
o
Reset value = $01
TFC
-Transmitter Idle Character Select. Selects
the idle character 10 be transmitted when
the transmitter is in an active idle mode
(transmitter enabled or disabled).
Mark Idle (TxD output is held high).
Content of AR2 (BSC and COP), BREAK condition
(ASYNC and ISOC), or FLAG character (BOP).
TCR
_4_ THW
-Transmitter Underrun (BOP, BSC and
COP only).
No TxFIFO underrun has occurred.
An empty TxFIFO was accessed for data.
(BOP) Underrun is treated as an ABORT in that eight
consecutive 1s are transmitted followed by the idle
condition of MARK or FLAG.
o
(BSC, COP) Underrun causes SYN characters to be
transmitted until new data is available in the TxFIFO.
4-93
-Transmit Half Word. (R68561, word mode
only). This bit is used when the frame or
block ends on an odd boundary in conjun.ction with the TLAST bit and indicates that
the last word in the TxFIFO contains valid
data in the upper byte only. This bit must
always be 0 in byte mode (R6a560).
Transmit full word (16 bits) from the TxFIFO.
Transmit upper byte (a bits) from the TxFIFO.
lEI
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
TCR
_3_ TLAST
o
Transmitter Interrupt Vector Number Register (TIVNR)
-Transmit Last Character (BOP, BSC and
COP only).
The next character is not the last character in a frame
or block.
The next character to be written into the TOR is the
last character of the message. The TLAST bit automatically returns to a 0 when the associated word/byte
is written to the TxFIFO. If the transmitter DMA mode
is enabled, TLAST is set to a 1 by DONE from the
DMAC. In this case the character written into the TOR
in the current cycle is the last character.
6543210
Address
Transmitter Interrupt Enable Register (TIER)
Address = 00
TIER
_7_ TDRA IE
o
o
5-3
-Not used.
TIER
_2_ TUNRN IE -Transmitter Underrun (TUNRN) Interrupt
Enable.
o
Disable TUNRN Interrupt.
1
Enable TUNRN Interrupt.
TIER
_1_ TFERR IE -Transmit Frame Error (TFERR) Interrupt
Enable.
o
Disable TFERR Interrupt.
Enable TFERR Interrupt.
1
Address = OA
R68560 (Byte Mode)
Address
-Transmit Frame Complete (TFC) Interrupt
Enable.
Disable TFC Interrupt.
Enable TFC Interrupt.
TIER
Transmit Data Register (TOR)
o
2
I
-Transmitter Data Register (TOR) Available Interrupt Enable.
Disable TDRA Interrupt.
Enable TDRA Interrupt.
TIER
_6_ TFCIE
TCR
_0_ TRES
-Transmitter Reset Command.
o
Enable normal transmitter operation.
Reset transmitter. Clears the transmitter section
including the TxFIFO and the TSR (but not the TCR).
The TxD output is held in "Mark" condition. TRES is
set by RESET or by writing a 1 into this bit and is
cleared by writing a 0 into this bit. TRES requires clearing after RESET.
3
Reset value = $00
The Transmitter Interrupt Enable Register (TIER) contains
interrupt enable bits for the Transmitter Status Register. When
enabled, the IRQ output is asserted when the corresponding
condition is detected and reported in the TSR.
TCR
_1_ TABT
-Transmit ABORT (BOP only).
o
Enable normal transmitter operation.
1
Causes an abort by sending eight consecutive 1'so A
data word/byte must be loaded into the TxFIFO after
setting this bit in order to complete the command. The
TABT bit clears automatically when the subsequent
data word/byte is loaded into the TxFIFO.
Byte 0
Reset value = $OF
If a transmitter interrupt condition occurs (as reported by status
bits in the TSR that correspond to interrupt enable bits in the
TIER) and the corresponding bit in the TIER is set, the IRQ
output is asserted to request MPU transmitter interrupt service.
When the lACK input is asserted from the bus, the Transmitter
Interrupt Vector Number (TIVN) from the Transmitter Interrupt
Vector Number Register (TIVNR) is placed on the data bus.
TCR
_2_ TSYN
-Transmit SYN (BSC and COP only).
o
Do not transmit SYN characters.
Transmit SYN characters. Causes a pair of SYN
characters to be transmitted immediately following the
current character. If BSC transparent mode is active,
a OLE SYN sequence is transmitted. The TSYN bit
automatically returns to a 0 when the SYN character
is loaded into the Transmitter Shift Register.
4
= OC
TIER
_0_
LSB
= OA
-Not used.
SERIAL INTERFACE REGISTERS
The transmitter has an S-byte (or 4-word) FIFO register file
(TxFIFO). Data to be transmitted is transferred from the bus into
the TxFIFO via the TOR in S-bit bytes or 16-bit words depending on the WD/BYT bit setting in PSR2. The TDRA status bit
in the TSR is set to 1 when the TxFIFO is ready to accept another
data word/byte.
Serial Interface Status Register (SISR)
Address = 10
4-94
Reset value = $00
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
The Serial Interface Status Register (SISR) contains the serial
interface status information. The transition status bits (CTST,
DSRT and DCDT) are cleared by writing a 1 into their respective positions, or by RESET. The level status bits (CTSLVL,
DSRLVL and DCDLVL) rellect the state 01 their respective inputs
and cannot be cleared internally. The IRQ output is asserted
if any 01 the conditions reported by the transition status bits occur
and the corresponding interrupt enable bit in the SIER is set.
SISR
_2_ DCDLVL -Data Carrier Detect Level.
o
The input on DCD is negated (high, inactive).
The input on DCD is asserted (low, active).
DCDLVL Reset - The DCDLVL bit in SISR2 follows the state
of the input to DCD and cannot be reset internally.
SISR
1-0
SISR
_7_ CTST
-Clear to Send Transition Status.
o
The input on CTS has not transitioned positive.
The input on CTS has transitioned positive from active
to inactive. To detect this transition, RTS must be
active (low) and the transmitter must be enabled
(TRES in TCRO = 0). The CTST bit is set in SISR7 and
an interrupt issued (if enabled) with the negative edge
01 TxC.
-Not used.
Serial Interface Control Register (SICR)
TEST
Address = 11
Reset value
= $00
The Serial Interface Control Register (SICR) controls various
serial interface signals and test functions.
SICR
_7_ RTSLVL -Request to Send Level.
o
Negate RTS output (high).
1
Assert RTS output (low).
CTST Reset - A negative transition of the serial clock (TxC)
must occur after the CTS input goes high before the CTST bit
can be reset by writing a 1 to SISR7.
SISR
_6_ DSRT
-Data Set Ready Transition Status.
o
The input on DSR has not transitioned negative.
The input on DSR has transitioned negative from
inactive to active. The DSRT bit is set in SISR7 and
an interrupt issued (if enabled) with the negative edge
of RxC. The receiver must be enabled (RRES in
RCRO=O).
NOTE
In BOP, BSC, or COP, when the RTSLVL bit is cleared
in the middle of data transmission, the RTS outputremains asserted until the end 01 the current frame
or block has been transmitted. In ASYNC or ISOC, the
RTS output is negated when the TxFIFO is empty. If
the transmitter is idling when the RTSLVL bit is reset,
the RTS output is negated within two bit times.
DSRT Reset - A negative transition of the serial clock (RxC)
must occur after the DSR input goes high before the DSRT
bit can be reset by writing a 1 to SISR6.
SICR
_6_ DTRLVL -Data Terminal Ready Level.
o
Negate DTR output (high).
1
Assert DTR output (low).
SISR
-Data Carrier Detect Transition Status.
_5_ DCDT
o
The input on DCD has not transitioned positive.
1
The input on DCD has transitioned positive from active
to inactive. The DCDT bit is set in SISRS and an interrupt issued (il enabled) with the negative edge of RxC.
The receiver must be enabled (RRES in RCRO=O).
SICR
5-3
-Not used. These bits are initialized to 0 by
RESET and must not be set to 1.
SICR
_2_ ECHO
-Echo Mode Enable.
o
Disable Echo mode (enable normal operation).
Enable Echo mode. Received data (RxD) is routed
1
back through the transmitter to TxD. The contents of
the TxFIFO is undisturbed. This mode may be used
for remote test purposes.
DCDT Reset - A negative transition of the serial clock (RxC)
must occur after the DCD input goes high before the DCDT bit
can be reset by writing a 1 to SISRS.
SISR
_4_ CTSLVL -Clear to Send Level.
o
The input on CTS is negated (high, inactive).
1
The input on CTS is asserted (low, active).
SICR
_1_ TEST
-Self-test Enable.
o
Disable self-test (enable normal operation).
Enable self-test. The transmitted data (TxD) and clock
1
(TxC) are routed back through to the receiver through
RxD and RxC, respectively (DCD and CTS are
ignored). This "Ioopback" self-test may be used lor
all protocols. RxC is external and CCR bits 2 and 3
must be a 1.
CRSLVL Reset - The CTSLVL bit in SISR4 follows the state
of the input to CTS and cannot be reset internally.
SISR
_3_ DSRLVL -Data Set Ready Level.
o
The input on DSR is negated (high, inactive).
The input on DSR is asserted (low, active).
SICR
_0_ MUST BE ZERO
DSRLVL Reset - The DSRLVL bit in SISR3 follows the state
of the input to DSR and cannot be reset internally.
o
4-95
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
Protocol Select Register 1 (PSR1)
Serial Interrupt Vector Number Register (SIVNR)
Address
= 14
3
2
o
o
o
CTlEX
Address = 18
Reset value = $OF
ADDEX
Reset value = $00
Protocol Select Register 1 (PSR1) selects BOP protocol related
options.
If a serial interface interrupt condition occurs (as r~orted by
status bits in the SISR that correspond to interrupt enable bits
in the SIER) and the corresponding bit in the SIER is set, the
IRQ output is asserted to request MPU serial interface interrupt
service. When the lACK input is asserted from the bus, the Serial
Interrupt Vector Number (SIVN) from the Serial Interrupt Vector
Number Register (SIVNR) is placed on the data bus.
PSR1
...l:L
-Not used.
PSR1
_1_ CTLEX
-Control Field Extend (BOP only).
o
Select B·bit control field.
Select 16·bit control field.
1
Serial Interrupt Enable Register (SIER)
PSR1
_0_ ADDEX
-Address Extend (BOP only).
Disable address extension. All eight bits of the
address byte are utilized for addreSSing.
Enable address extension. When bit 0 in the address
byte is a 0 the address field is extended by one byte.
An exception to the address field extension occurs
when the first address byte is all O's (null address).
o
Address
= 15
Reset value = $00
The Serial Interrupt Enable Register (SIER) contains interrupt
enable bits for the Serial Interface Status Register. When an
interrupt enable bit is set, the IRQ output is asserted when the
corresponding condition occurs as reported in the SISR.
Protocol Select Register 2 (PSR2)
7
6
WD/BYT
SB2
SIER
_7_ CTS IE
o
1
-Clear to Send (CTS) Interrupt Enable.
Disable CTS Interrupt.
Enable CTS Interrupt.
Address
=
3
I SBl
Cl2
I
2
I Cll
1
I;
0
PROTOCOL SEl
PS3
J PS21
PSl
Reset value = $00
19
-Data Bus Word/Byte Mode.
Select byte mode. Selects the number of data bits to
be transferred from the RxFIFO and the registers to
the data bus and to be transferred from the data bus
to the TxFIFO and the registers. The MPCC is initial·
ized by RESET to the byte mode.
Select word mode. For operation with the 16·bit bus,
select the word mode by sending $BO on 07-00 to
address $19 prior to transferring subsequent data
between the MPCC and the data bus.
o
SIER
1
I
_7_ WD/BYT
-Data Set Ready (DSR) Interrupt Enable.
Disable DSR Interrupt.
Enable DSR Interrupt.
_5_ DCD IE
o
4
PSR2
SIER
1
5
Protocol Select Register 2 (PSR2) selects protocols, character
size, the number of stop bits, and word/byte mode.
_6_ DSR IE
o
I
STOP BIT SEl CHAR lEN SEl
-Data Carrier Detect (DCD) Interrupt
Enable.
Disable DCD Interrupt.
Enable DCD Interrupt.
PSR2
SIER
4-0
~
STOP BIT SEL
-Not used.
-Number of Stop Bits Select.
Selects the number of stop bits
transmitted at the end of the data
bits in ASYNC and ISOC modes.
No. of Stop Bits
GLOBAL REGISTERS
6
SB2
The global registers contain command information applying to
different modes of operation and protocols. After changing global
register data, TRES in the TCR and RRES in the RCR should
be set then cleared prior to performing normal mode processing.
4·96
0
0
5
SB1
0
1
1
0
ASYNC
1
1·1/2
2
ISOC
1
2
2
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
Baud Rate Divider Register 1 (BRDR1)
PSR2
..±L
CHAR lEN SEl -Character length Select. Selects
the character length except in BOP
and BSC where the character length
is always eight bits. Parity is not
included in the character length.
3
Cll
0
1
0
1
4
Cl2
0
0
1
1
7
0
PSl
0
1
0
1
0
1
0
1
0
2
Reset value = $01
Baud Rate Divider Register 2 (BRDR2)
Character length
5 bits
6 bits
7 bits
8 bits
1
PS2
0
0
1
1
0
0
3
Address = 1C
7
5
6
4
3
o
2
BAUD RATE DIVIDER (MSH)
Address = lD
Reset value = $00
The two 8-bit Baud Rate Divider Registers (BRDRl and BRDR2)
hold the divisor of the Baud Rate Divider circuit. BRDRl contains the least significant half (lSH) and BRDR2 contains the
most significant half (MSH), With an 8.064 MHz EXTAL input,
standard bit rates can be selected using the combination of
Prescaler Divider (in the CCR) and Baud Rate Divider values
shown in Table 3. For isochronous or synchronous protocols,
the Baud Rate Divider value must be multiplied by two for the
same Prescaler Divider value.
PROTOCOL SEl-Protocol Select. Selects protocol
and defines the protocol dependent
control bits.
2
PS3
0
0
0
0
1
1
4
BAUD RATE DIVIDER (lSH)
PSR2
~
5
6
Protocol
BOP (Primary)
BOP (Secondary)
Reserved
COP
BSC EBCDIC
BSC ASCII
ASYNC
ISOC
The Baud Rate Divider (BRD) value can be computed for other
crystal frequency, prescaler divider and desired baud rate values
as follows:
BRD =
Crystal Frequency
(Prescaler Divider) (Baud Rate) (I<)
Address Register 1 (AR1) Address
7
6
5
4
3
o
2
K = 1 for isochronous or synchronous
2 for asynchronous
where:
BOP ADDRESS/BSC & COP PAD
Address = 1A
Reset value
= $00
Clock Control Register (CCR)
Address Register 2 (AR2)
7
6
5
4
3
o
2
6
5
4
3
2
0
0
PSCDIV
TClKO
RCLKIN
= 1B
Reset value
Address = 1E
= $00
I
0
ClK DIV
CK2
BSC & COP SYN
Address
1
7
0
I CKI
Reset value = $00
The CCR selects various clock options.
The protocol selected in PSR2 (BOP, BSC and COP only) determines the function of the two 8-bit Address Registers (ARl and
AR2). As a secondary station in BOP, the contents of ARl is
used for address matching. In BSC and COP, ARl and AR2 contain programmable leading PAD and programmable SYN
characters, respectively.
CCR
.1::§..
CCR
_4_ PSCDIV
Address Register (AR) Contents
Protocol Selected
AR1
BOP (Primary)
BOP (Secondary)
BSC EBCDIC
BSC ASCII
COP
X
Address
leading PAD
leading PAD
leading PAD
-Not used.
AR2
o
X
X
SYN
SYN
SYN
-Prescaler Divider. The Prescaler Divider
network reduces the external/oscillator frequency to a value for use by the internal
Baud Rate Generator.
Divide by 2.
Divide by 3.
CCR
_3_ TClKO
-Transmitter Clock Output Select.
Select TxC to be an input.
1
Select TxC to be an output. (lX clock)
o
'X = Not used
4-97
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
Table 3.
Standard Baud Selection (8.064 MHz Crystal)
Baud Rate Divider
Prescaler Divider
Decimal
Value
PSCDIV
(0 to 1)
Decimal
Value
BRDR2
(MSH)
BRDR1
(LSH)
Decimal
Value
BRDR2
(MSH)
BRDR1
(LSH)
50
75
110
135
150
300
1200
1800
2400
3600
4800
7200
9600
19200
38400
3
2
3
2
3
2
3
2
2
2
3
2
3
3
3
1
0
1
0
1
0
1
0
0
0
1
0
1
1
1
26,880
26,880
12,218
14,933
8,960
6,720
1,120
1,120
840
560
280
280
140
70
35
69
69
2F
3A
23
1A
04
04
03
02
01
01
00
00
00
00
00
SA
55
00
40
60
60
48
30
18
18
8C
46
23
53,760
53,760
24,436
29,866
17,920
13,440
2,240
2,240
1,680
1,120
560
560
280
140
70
D2
02
5F
74
46
34
08
08
06
04
02
02
01
00
00
00
00
74
AA
00
80
CO
CO
90
60
30
30
18
8C
46
CCR
ECR
~
RClKIN
-Receiver Clock Internal Select (ASYNC
only).
Select External RxC.
Select Internal RxC.
o
o
..1:l!..
ODD PAR -Odd/Even Parity Select (Effective only
when PAREN=1).
Generate/check even parity.
Generate/check odd parity.
ECR
..§:!.
CCR
ClK DIV
-External Receiver Clock Divider. Selects
the divider of the external RxC to determine
the receiver data rate.
CK2
CK1
o
o
o
1
1~}(ISOC)
1
32
64
(ASYNC)
only
ECR
_2_ CRCPRE
o
Error Control Register (ECR)
7
6
PAREN
OOOPAR
5
4
- -
3
2
CFCRC
CRCPRE
1
0
CRCSEL
CR2
Address = 1F
I
-Not used .
ECR
_3_ CFCRC
-Control Field CRC Enable. (BOP Only)
o
Disable control field CRC.
1
Enables an intermediate CRC remainder to be
appended after the address/control field in transmitted
BOP frames and checked in received frames. The CRC
generator is reset after control field CRC calculation.
Divider
o
1
1
-CRC Generator Preset Select.
(BOP, BSC Only)
Preset CRC Generator to O. (For BSC)
Preset CRC Generator to 1 and transmit the 1's complement of the resulting remainder. (For BOP)
ECR
I CR1
..1:l!..
CRCSEl
Reset value = $04
The Error Control Register (ECR) selects the error detection
method used by the MPCC.
1
CR2
0
CR1
o
o
0
-CRC Polynomial Select, Selects one of the
RC polynominals.
Polynominal
X16+X12+X5+ 1 (CCln V.41) (BOP)
X16+X15+X2+1 (CRC-16) (BSC)
1
o xB + 1
(VRC/lRC)* (BSC,
ASCII, non-transparent)
Not used.
*VRC: Odd-parity check is performed on each
character including the lRC character.
ECR
_7_ PAREN
1
Hexadecimal Value
Hexadecimal Value
Desired
Baud Rate
(Bit Rate)
~
o
Isochronous and Synchronous
Asynchronous
-Parity Enable. (ASYNC, ISOC and COP
only).
Disable parity generation/checking.
Enable parity generation/checking.
4-98
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
INPUT/OUTPUT FUNCTIONS
and the DMAC is accomplished by a two-signal requesV
acknowledge handshake. Since the MPCC has only one
acknowledge input (DACK) for its two DMA request lines, an
external OR function must be provided to combine the two DMA
acknowledge signals. The MPCC uses the RiW input to
distinguish between the Transmitter Data Service Request (TDSR
acknowledge and the Receiver Data Service Request (RDSR)
acknowledge.
MPU INTERFACE
Transfer of data between the MPCC and the system bus involves
the following signals:
R68561
R68560
Address Lines
A1-A4
AO-A4
Data Lines
DO-D7
DO-D15
Read/Write
RiW
RiW
Data Transfer Acknowledge
DTACK
DTACK
Chip Select
CS
CS
UDS and LDS
Data Strobes
DS
Receiver DMA Mode
The receiver DMA mode is enabled when the RDSREN bit in the
RCR is set to 1. When data is available in the RxFIFO, Receiver
Data Service Request (RDSR) is asserted for one receiver clock
period (BOP and BSG) to initiate the MPCC to memory DMA transfer. For asynchronous operation, RDSR is asserted for 2-3
periods of the system clock depending on prescale factor. The
next RDSR cycle may be initiated as soon as the current RDSR
cycle is completed (i.e., a full sequence of DACK, DS, and DTC).
Figures 10 and 11 show typical interface connections.
ReadIWrite Operation
The RiW input controls the direction of data flow on the data bus.
CS (Chip Select) enables the MPCC for access to the internal
registers and other operations. When CS is asserted, the data
I/O buffer acts as an output driver during a read operation and
as an input buffer during a write operation. CS must be decoded
from the address bus and gated with address strobe (AS).
In response to RDSR assertion, the DMAC sets the RiW line to
write, asserts the memory address, address strobe, and DMA
acknowledge. The MPCC outputs data from the RxFIFO to the
data bus and the DMAC asserts the data strobes. The memory
latches the data and asserts DTACK to complete the data transfer.
The DMAC asserts DTC to indicate to the MPCC that data transfer
is complete. Figure 14 shows the timing relationships for the
receiver DMA mode.
When the R68561 is connected to the 16-bit bus for operation
in the word mode (WD/BYT = 1 in the PSR2), address lines
A 1-A4 select the internal register(s) (the 8-bit control/status
registers are accesed two at a time and the 16-bit data registers
are accessed on even address boundaries). When the MPCC is
selected (CS low) during a read (RiW high), 16 bits of register
data are placed on the data bus when the data strobes (LDS and
UDS) are asserted. LDS strobes the eight data bits from the even
numbered registers to the lower data bus lines (DO-D7) and UDS
strobes the eight data bits from the odd numbered registers to
the upper data bus lines (D8-D15). The MPCC asserts Data
Transfer Acknowledge (DTACK) prior to placing:data on the data
bus. Conversely, when the MPCC is selected (CS low) during
a write (RiW low) LDS and UDS strobe data from the DO-D7
and D8-D15 data bus lines into the addressed even and odd numbered registers, respectively, and the MPCC asserts DTACK.
DTACK is negated when CS is negated. Figures 12 and 13
show the read and write timing relationships.
RDSR is inhibited when either RDSREN is reset to 0 or RRES
is set to 1 (both in the RCR), or when RESET is asserted.
Transmitter DMA Mode
The transmitter DMA mode is enabled when the TDSREN bit in
the TCR is set to 1. When the TxFIFO is available, Transmitter
Data Service Request (TDSR) is asserted for one transmitter clock
period to initiate the memory to MPCC DMA transfer. For asynchronous operation, TDSR is asserted for a period of one-half
the transmitter baud rate. The next TDSR cycle may be initiated
as soon as the current TDSR cycle is completed.
In the transmitter DMA mode, the TxFIFO Is implicitly addressed.
That is, when the transfer is from memory to the TxFIFO, only
the memory is addressed. In response to TDSR assertion, the
DMAC sets the RiW line to read, asserts the memory address,
the address strobe, the data strobes and DMA acknowledge. The
memory places data on the data bus and asserts DTACK. Data
is valid at this time and will remain valid until the data strobes
are negated. The DMAC asserts DTC to indicate to the MPCC
that data is available. The MPCC loads the data into the TxFIFO
on the negation (rising edge) of DS and the transfer is complete.
When a TxFIFO underrun occurs, the TUNRN bit is set in TSR2,
the interrupt is issued, and the ABORT sequence is entered (eight
consecutive 1s are transmitted). The next word/byte in TxFIFO
clears the ABORT bit and the idle mode is entered. When a transmission is aborted, it is expected that the interrupt will allow the
host system to decide the next course of action; probably to reset
the DMAC and retransmit the message. A timing diagram for the
transmitter DMA Mode is shown in Figure 15.
When the R68560 is connected to the 8-bit bus for operation in
the byte mode (WD/BYT = 0 in the PSR2), address lines AO-A4
select one internal 6-bit register. When the MPCC is selected (CS
low) during a read (RiW high), eight bits of register data are placed
on data bus lines DO-D7 when the data strobe (DS) is asserted.
When the MPCC is selected (CS low) for a write (RiW low), DS
strobes data from the DO-D7 data lines into the selected register.
DMA INTERFACE
The MPCC is capable of providing DMA data transfers at up to
2 Mbytes per second when used with the MC68440 or MC68450
DMAC in the single address mode. Based on 4 Mb/s serial data
rate and 5 bits/character, the maximum DMA required transfer
rate is 800 Kbytes per second.
The MPCC has separate DMA enable bits for the transmitter and
receiver, each of which requires a DMA channel. Both the transmitter and receiver data are implicitly addressed (TDR or RDR)
therefore addressing of the data register is not required before
data may be transferred. Communication between the MPCC
TDSR is inhibited when either TDSREN is reset to 0 or TRES
is set to 1 (both in the TCR), or when RESET is asserted.
4-99
II
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
DONE Signal
Vector
When the DMA transfer count is exhausted in transmitter DMA
mode, the DMAC asserts DONE which sets the TLAST bit in the
TCR to indicate that the last word/byte has been transferred.
In the receiver DMA mode of operation, DONE is issued by tlie
MPCC on an MPCC-to-memory transfer when the last byte/word
is being transferred from the RxFIFO to the data bus (if DONEEN
bit is set in RCR5). In the byte mode, this is the Frame Status
Byte (FSB). In the word mode, this is the last data byte and FSB
(for an odd number of data byte transfers) or FSB and blank (for
an even number of data byte transfers).
Vector Value
(Hex)
Vector Value
(Binary)
44
01000100
4C
01001100
5C
01011100
Receiver Interrupt
Vector Number
(RIVN)
Transmitter Interrupt
Vector Number
(TIVN)
Serial Interrupt
Vector Number
(SIVN)
l l
t !!
A timing diagram for the interrupt acknowledge sequence is
shown in Figure 16.
DONE is asserted as a result of the FSB being transferred and
not as a result of the error conditions. The EOF, C/PERR and
FRERR are addendum bits in the RxFIFO which are written to
FIFO when they occur and follow the data through the FIFO.
The frame is aborted upon overrun or error detection if RCRI = 1.
SERIAL INTERFACE
The MPCC is a high speed, high performance device supporting
the more popular bit and character oriented data protocols. The
lower speed asynchronous (ASYNC) and isochronous (I SOC H)
modes are also supported. An on-chip clock oscillator and baud
rate generator provide an output data clock at a frequency of DC
to a 4 MHz .. The clock can also be used in the ASYNC mode to
provide a receive clock for the incoming data. The serial interface consists of the following signals:
CAUTION
DONE is reasserted with each occurrence of DACK
until EOF is cleared in the RSA.
INTERRUPTS
RTS (Request to Send) Output
If an interrupt generating status occurs and the interrupt is
enabled, the MPCC asserts the IRQ output. Upon receiving lACK
for the pending interrupt request, the MPCC places an interrupt
vector on DO-D7 data bus and asserts DTACK.
The RTS output to the DCE is controlled by the RTSLVL bit in
the SICR inn conjunction with the state of the transmitter section.
When the RTSLVL bit is set to I, the RTS output is asserted.
When the RTSLVL bit is reset to 0 (no sooner than one full cycle
of TxC after transmission has started), the RTS output remains
asserted until the TxFIFO becomes empty, or the end of the
message (or frame), complete with CRC code (if any), closing
flag, and one full cycle of idle has been transmitted. RTS also is
negated when the RTSLVL bit is reset during transmitter idle,
or when the RESET input is asserted.
The MPCC has three vector registers: Receiver Interrupt Vector
Number Register (RIVNR), Transmitter Interrupt Vector Number
Register (TIVN), and Serial Interrupt Vector Number Register
(SIVNR). The receiver interrupt has priority over the transmitter
interrupt, and the transmitter interrupt has priority over the
serial interface interrupt. For example, if a pending interrupt
request has been generated simultaneously by the receiver and
the transmitter, the Receiver Interrupt Vector Number (RIVN)
is placed on DO-D7 when acknowledged by the MPU. Upon completion of the first interrupt request cycle (which clears the
receiver interrupt), IRQ will remain low to start the transmitter
interrupt cycle. IRQ is negated by clearing all bits set in a
status register that could have caused the interrupt.
CTS (Clear to Send) Input
The CTS input signal is normally generated by the DCE to indicate whether or not the data set is ready to receive data. The
CTST bit in the SISR reflects the transition status of the CTS
input while the CTSLVL bit in the SISR reflects the current level.
A positive transition on the CTS pin asserts IRQ if the CTS IE bit
in the SIER is set. The CTS input in an inactive state disables
the start of transmission of each frame.
CAUTION
DCD (Data Carrier Detect) Input
A higher priority interrupt occuring while lACK is low during
transfer of a lower priority interrupt vector to the MPU will
cause the lower priority interrupt vector on the data bus
to be invalid if there are any l's in the higher priority interrupt vector in the same bit poositions as any O's in the
lower priority interrupt vector. To prevent this problem from
occuring, ensure that the higher priority interrupt vectors
contain l's only in bit positions where there are l's in the
lower priority interrupt vectors, e.g.:
The DCD input signal is normally gnerated by the DCE and indicates that the DCE is receiving a data carrier signal suitable for
demodulation. The DCDT bit in the SISR reports the transition
status of the DCD input while the DCDLVL bit in the SISR contains the current level. A positive transition on the DCD pin
asserts the IRQ output if the DCD IE bit in the SIER is set. A
negated DCD input disables the start of the receiver but does
not stop the operation of an incoming message already in
progress.
4-100
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
DSR (Data Set Ready) Input/RSYN Output
For low speed operation between the MPCC and a modem or
RS-232C Data Communications Equipment (DC E), an inverter
can be used in the TxC output lines as shown in Figure 17.
RS-232 and RS-423 (covering serial data interface up to
100K baud) require that data be centered ± 25% about the
negative-going edge of the RxC. This criteria is met for frequencies up to 1.25 MHz using the inverter. Use of the inverter
also allows MPCC to MPCC operation up to 2.17 MHz.
The DSRT input from the DCE indicates the status of the local
set. The DSRT bit in the SISR contains the transition status of
the DSR input while the DSRLVL bit in the SISR reports the
current level. A negative transition on the DSR pin asserts the
IRQ output if the DSR IE bit in the SIER is set.
The DSR pin is used as an output for RSYN when enabled by
a 1 in RSR4 (RSYNEN = 1). OSR output low indicates detection
of a SYN (non-transparent) in BSC or COP protocols or OLESYN pair (transparent) in BSC protocol. It is asserted as a
negative-going pulse one-bit time after the end of the SYN byte
and lasts for one full serial clock cycle before being reset.
SERIAL COMMUNICATION MODES
AND PROTOCOLS
In BOP protocol, RSYN is asserted as a result of address match
at the beginning of a frame. It is asserted one bit time after the
end of the address byte(s) if an address match is made, and
lasts for one full serial clock cycle.
ASYNCHRONOUS AND ISOCHRONOUS MODES
Asynchronous and isochronous data are transferred in frames.
Each frame consists of a start bit, 5 to 8 data bits plus optional
even or odd parity, and 1, 1 '12, or 2 stop bits. The data character is transmitted with the least significant bit (LSB) first. The data
line is normally held high (MARK) between frames, however, a
BREAK (minimum of one frame length for which the line is held
low) is used for control purposes. Figure 4 illustrates the frame
format supported by the MPCC.
DTR (Data Terminal Ready) Output
The OTR output is general purpose in nature and can be used
to control switching of the OCE. The OTR output is controlled by
the OTRLVL bit in the SICR.
TxC (Transmitter Clock) Input/Output
Asynchronous Receive
The transmitter clock (TxC) may be programmed to be input or
an output. When the TCLKO control bit in the CCR is set to a
1 , the TxC pin becomes an output and provides the OCE with
a clock whose frequency is determined by the internal baud rate
generator. When the TCKLO control bit is reset, TxC is an input
and the transmitter shift timing must be provided exernally. The
TxO output changes state on the negative-going edge of the
transmitter clock. In the asynchronous mode when TCLKO = 0
in the CCR, the TxC input frequency must be two times the
desired baud rate.
In the asynchronous (ASYNC) mode, data reception on RxO
occurs in three phases: (1) detection of the start bit and bit
synchronization, (2) character assembly and optional parity check,
and (3) stop bit detection. The receiver bit stream may be synchronized by the internal baud rate generator clock or by an external
clock on RxC. When RCLKIN in the CCR is set to 0, an external
clock with a frequency of 16, 32, or 64 times the data rate establishes the data bit midpoint and maintains bit synchronization.
The character assembly process does not start if the start bit is
less than one-half bit time. Framing and parity errors are
detected and buffered along with the character on which errors
occurred. They are passed on to the RxFIFO and set appropriate
status bits in the RSR when the character with an error reaches
the last RxFIFO register where it is ready to be transferred onto
the data bus via the ROA.
TxD (Transmitted Data) Output
The serial data transmitted from the MPCC is coded in NRZ data
format. The first byte of a message transmitted out of the R68561
MPCC is the even byte of the 68000 bus (08-015). It is transmitted least significant bit (LSB) first.
Isochronous Receive
RxC (Receiver Clock) Input
In the isochronous (ISOC) mode, a times 1 clock on RxC is
required with the data on RxO and the serial data bit is latched
on the falling edge of each clock pulse. The requirement for the
detection of a valid start bit, or the beginning of a break, is satisfied by the detection of a high-to-Iow transition on the serial data
input line. Error detection and status indication are the same as
the asynchronous mode.
The receiver latches data on the negative transition of the RxC.
RxD (Received Data) Input
The serial data received by the MPCC is in NRZ data format.
The first byte received in the MPCC RXFIFO is output to the
68000 bus on (08-D15).
Serial Interface Timing
Asynchronous and Isochronous Transmit
The timing for the serial interface clock and data lines is shown
in Figure 18. The MPCC supports high speed synchronous operation. As shown, the TxO output changes with the negative-going
edge of TxC and the received data on RxD is latched on the
negative edge of RxC. This assures high speed two-way operation between two MPCCs connected as shown in Figure 17.
In asynchronous and isochronous transmit modes, output data
transmission on TxO begins with the start bit. This is followed
by the data character which is transmitted LSB first. If parity generation is enabled, the parity bit is transmitted after the MSB of the
character. Each frame is terminated with 1,1 1/2 or 2 stop bits as
selected by PSR2 bils 5 and 6.
4-101
I]
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
ASYNCHRONOUS FRAME FORMAT
---,
r--T----(~----,--"'T--.,---,
I
DATA
I
I
START
I
1
I
I
I
I
1
L ___ -(~-_---.L---L--..J
L..._--L.I
I
lBS
I~
MSB
1 r::~~Y 1 ~~~~,
I
1
L...l_L_
OR 2 BITS)
1
.1
5 TO 8 BITS
ISOCHRONOUS FRAME FORMAT
ClK
DATA
I
I
---,'r----...L--...L--.J
I
I I r::;~Y 1
i--I---~~----l--l--
I
_--L.I __
!-.
START
I
~
lBS
.1
address field can be extended by setting the ADDEX bit to a 1
in PSR1. In this case, the address field will be extended until the
occurrence of an address byte with a 1 in bit O. The first byte
of the address field is automatically checked when the MPCC is
programmed to be a secondary station in BOP. An automatic
check for global (11111111) or null (00000000) address is also
made. The control field of one or two bytes is transparent to the
MPCC and sent directly to the host without interpretation.
In synchronous modes, a times one clock is provided along with
the data. Serial output data is shifted out and input data is latched
on the falling edge of the clock.
BIT ORIENTED PROTOCOLS (BOP)
In bit oriented protocols (BOP), messages (data) are transmitted
and received in frames. Each frame contains an opening lIag,
address field, control field, frame check sequence, and a closing
flag. A frame may also contain an information field. (See Figure 5).
The optional information field consists of 8-bit characters. Cyclic
redundancy checking is used for error detection and the CRC
remainder resulting from the calculation is transmitted as the
frame check sequence field. For BOP, the polynomial X16 + X12
+ X5 + 1 (CRC-CCITT) should be used, i.e., selected in the
CRC SEL bits in the ECA. The registers representing the
CRC-CCITT polynomial are generally preset to all 1s, and the 1s
complement of the resulting remainder is transmitted. (See
X.25 Recommendation.)
The opening flag is a special character whose bit pattern is
01111110. It marks the frame boundaries and is the interframe
fill character. The address field of a frame contains the address
of the /lecondary station which is receiving or responding to a
command. The address field may be one or more bytes long. The
01111110
I
Asynchronous and Isochronous Frame Format
SYNCHRONOUS MODES
FLAG
L_..J._
STOP
(lOR 2 BITS)
MSB
5T08BITS
Figure 4.
I -II
I
ADDRESS
lOR N
BYTES
INFORMATION
N BYTES
(OPTIONAL)
CONTROL
lOR
2 BYTES
Figure 5.
Bit Oriented Protocol (BOP) Frame Format
4-102
FCS
2 BYTES
FLAG
01111110
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
Zero insertion/deletion is employed to prevent valid frame data
from being confused with the special characters. A 0 is inserted
by the transmitter after every fifth consecutive 1 in the data
stream. These inserted zeros are removed by the receiver to
restore the data to its original form. The inserted zeros are not
included in the CRC calculation.
For the control field, one or two byles are assembled and passed
on to the RxFIFO depending on the state of the extended control field bit.
If the CFCRC bit in the ECR is set to 1, an intermediate CRC
check will be made after the address and control field. The Frame
Check Sequence is still calculated over the remainder of the
frame.
The end of the frame is determined by the detection of the closing
Flag special character which is the same is the opening Flag.
With the control options offered by the MPCC, commonly used
bit oriented protocols such as SDLC, HDLC and X.25 standards
can be supported. Figure 6 compares the requirements of these
options.
BOP Transmitter Operation
In BOP, the TxFIFO can be preloaded through the TDR while
the transmitter is disabled (TEN = 0 in the TCR). When the transmitter is enabled (TEN = 1 in the TCR), the leading Flag is automatically sent prior to transmitting data from the TxFIFO. The
TDRA bit is set to 1 in the TSR as long as TxFIFO is not full.
If an underrun occurs, the TUNRN bit in the TSR is set to a 1
and an Abort (11111111) is transmitted followed by continuous
Flags or marks until a new sequence is initiated.
BOP Receiver Operation
In BOP, the receiver starts assembling characters and accumulating CRC immediately after the detection of a Flag. The receiver
also continues to search for additional Flag, or Abort, characters on a bit-by-bit basis. Zero deletion is implemented in the
Receiver Shift Register after the Flag detection logic and before
the CRC circuitry. The receiver recognizes the shared flag (the
closing flag for one frame serves as the opening flag for the next
frame) and the shared zero (the ending 0 of a closing flag serves
as the beginning 0 of an opening flag forming the pattern
"011111101111110."
The TLAST bit in the TCR must be set prior to loading the last
character of the message to signal the transmitter to append
the two-byte Frame Check Sequence (FCS) following the last
character. If the transmitter DMA mode is selected (the TDSREN
bit set to 1 in the TCR) the TLAST bit is set by the DONE signal
from the DMAC.
Character assembly and CRC accumulation are stopped when
a closing Flag or Abort is detected. The CRC accumulation
includes all the characters between the opening Flag and the
closing Flag. The contents of the CRC register are checked at
the close of a frame and the C/PERR bit in the RSR is updated.
The FCS and the Flag are not passed on to the RxFIFO.
A message may be terminated at any time by setting the TABT
bit in the TCR to 1. This causes the transmitter to send an Abort
character followed by the remainder of the current frame data
in the TxFIFO.
If the Flag is a closing flag, checks for short frame (no control
field) and CRC error conditions are made and the appropriate
status is updated. When an Abort (seven 1s) is detected, the
remaining frame is discarded and the RNB bit is set in the RSR.
When a link idle (15 or more consecutive 1s) is detected, the
RIDLE status bit is set in the RSR. The zeros that have been
inserted to distinguish data from special characters are detected
and deleted from the data stream before characters are assembled. The MPCC programmed as a secondary station provides
automatic address matching of the first byte. If there is no
address match, or if null address is received, the receiver ignores
the remainder of the frame by searching for the Flag. If there
is a match, the address bytes are transferred to the RxFIFO as
they are assembled.
The serial data from the Transmitter Shift Register is continuously monitored for five consecutive 1s, and a 0 is inserted in
the data stream each time this condition occurs (excluding Flag
and Abort characters).
CRC accumulation begins with the first non-Flag character and
includes all subsequent characters. The CRC remainder is transmitted as the FCS following the last data character. If the
CTLCRC bit in the ECR is set to 1, an intermediate CRC
remainder is appended after the Address and Control field. The
final Frame Check Sequence is calculated over the balance of
the frame.
IBM SDLC FRAME FORMAT
FLAG
01111110
ADDRESS
1 BYTE
CONTROL
1 BYTE
INFORMATION
N BYTES
FCS
2 BYTES
FLAG
01111110
ADDRESS
N BYTES
CONTROL
lOR
2 BYTES
INFORMATION
N BYTES
FCS
2 BYTES
FLAG
01111110
HDLC FRAME FORMAT
FLAG
01111110
Figure 6_
Bit Oriented Protocols
4-103
II
R68560, R68561
LEADING PAD
1 BYTE
(AR1)
Multi-Protocol Communications Controller (MPCC)
SYN
1 BYTE
(AR2)
SYN
1 BYTE
(AR2)
BODY
BCC
TRAILING
PAD
11111111
Figure 7. BSC Block Format
BISYNC (BSC)
ETB followed by the BCC. Only the first SOH or STX in a transmission block following a line turnaround causes the BCC to
reset. All succeeding STX or SOH characters are included in
the BCC. This permits the entire transmission (excluding the first
SOH or STX) to be block-checked.
The slructure of messages utiiizing the IBM Binary Synchronous
Communications (BSC) protocol, commonly called Bisync, is
shown in Figure 7. The MPCC can process both transparent and
nontransparent messages using either the EBCDIC or the ASCII
codes. The CRC-16 polynomial should be selected by setting
the appropriate CRCSEL bits in the ECR for both transparent
and non-transparent EBCDIC and for transparent ASCII coded
messages. VRC/LRC should be selected for non-transparent
ASCII coded messages. BSC messages are formatted using
defined data-link control characters. Data-link control characters
generated and recognized by the MPCC are listed in Table 4.
Table 4.
Command
SYN
SOH
STX
ET6
ETX
ENQ
OLE
IT6
EOT
ACKW
NAK
WACK
RVI
The text data is transmitted in complete units called messages,
which are initiated by STX and concluded with ETX. A message
can be subdivided into smaller blocks for ease in processing
and more efficient error control. Each block starts with STX and
ends with ETB (except for the last block of a message, which
ends with ETX). A single transmission can contain any number
of blocks (ending with ETB) or messages (ending with ETX). An
EOT following the last ETX block indicates a normal end of transmission. Message blocking without line turnaround can be
accomplished by using ITB (see the Additional Data Link Capabilities section, IBM GA 27-3004-2).
BSC Control Sequences-Inclusion
in CRe Accumulation
ASCII
Byte 1
16"
01
02
17
03
05
10
IF
04
10
15
10
10
Byte 2
-
-
-
-
-
30-37
36
3C
Command
SYN
SOH
STX
E06 (ET6)
ETX
ENQ
OLE
ITB
EOT
ACKO
ACK 1
NAK
WACK
RVI
EBCDIC
Byte 1
32"
01
02
26
03
20
10
IF
37
10
10
30
10
10
Byte 2
Two modes of data transfers are used in BSC. In non-transparent
mode, data link control characters may not appear as text data.
In transparent mode, each control character is preceded by a
data link escape (OLE) character to differentiate it from the text
data. Table 5 indicates which control characters are excluded
in the CRC generation. All characters not shown in the table are
included in the CRC generation. Figure 8 shows various formats
for Control/Response Blocks and Heading and Text Blocks.
-
-
70
61
-
Table 5.
66
7C
Transparent Mode BSC Control Sequences Inclusion in CRC Accumulation
Included in CRC Accumulation
Note: "Programmable
A heading is a block of data starting with an SOH and containing one or more characters that are used for message control
(e.g., message identification, routing, and priority). The SOH initiates the block-check-character (BCC) accumulation, but is not
included in the accumulation. The heading is terminated by STX
when it is part of a block containing both heading and text. A
block containing only a heading is terminated with an ITB or an
Character of Sequence
Yes
No
TSYN
TSOH
TSTX"
TETS
TETX
TOLE
-
DLESYN
OLESOH
OLESTX
OLE
OLE
OLE(OLE)
-
ETB
ETX
(OLE)OLE
"If not preceded within the same block by transparent heading
information.
4-104
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
CONTROL/RESPONSE BLOCKS:
ADDRESS
NEGATIVE ACKNOWLEDGEMENT
HEADING AND TEXT BLOCKS:
-I
RESET BCC-!••- - - - - -INCLUDED IN BCC
IHE~:ING
I
ETB
BCC
IFOLLOW-I
ING PAD
I
HEADING ONLY
D
BCC
!--:INCLUDED IN BI:C---j
SYN
I
::
IDLE-
TRANSPARENT TEXT
Figure 8.
sse Message Format Examples
4-105
I
ETX
I
BCC
I~~~L~~-I
"OLE EXCLUDED FROM BCC CALCULATION
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
esc
Receiver Operation
CHARACTER ORIENTED PROTOCOLS
Character length defaults to eight bits in BSC mode. When ASCII
is selected, the eighth bit is used for parity provided that
VRC/LRC polynomial is selected. Character assembly starts after
the receipt of two consecutive SYN characters. Serial data bits
are shifted through the Receiver Shift Register into the Serialto-Parallel Register and transferred to the RxFIFO. The RDA status bit in the RSR is set to 1 each time data is transferred to
the RxFIFO. The SYN character pairs in non-transparent mode
and DLE-SYN pairs in transparent mode are discarded.
The character oriented protocol (COP) option uses the format
shown in Figure 9. It may be used for various character oriented
protocols with 5-8 bit character sizes and optional parity checking. The input data is checked on a bit-by-bit basis for a pair
of consecutive SYN characters to establish character
synchronization. These SYN characters are discarded after
detection. The PAD and SYN characters may be 5-8 bits long
and are user programmable as stored in ARl and AR2,
respectively.
The receiver starts each block in the non-transparent mode. It
switches to transparent mode if a block begins with a DLE-SOH
or DLE-STX pair. The receiver remains in transparent mode until
a DLE-ITB, DLE-ETB, DLE-ETX or DLE-ENQ pair is received.
BCC accumulation begins after an opening SOH, STX, or DLESTX. SYN characters in non-transparent mode or DLE-SYN pairs
in transparent mode are excluded from the BCC accumulation.
The first DLE of a DLE-DLE sequence is not included in the BCC
accumulation and is discarded. The BCC is checked after receipt
of an ITB, ETB, or ETX in non-transparent mode or DLE-ITB,
DLE-ETB, DLE-ETX in transparent mode. If a CRC error is
detected, the C/PERR and EOF bits in the RSR are set to 1.
If no error is detected only the EOF bit is set. If the clOSing
character was an ITB, BCC accumulation and character assembly starts again on the first character following the BCC.
If parity checking is enabled the characters assembled after
character sync are checked for parity errors. If STRSYN is set
in the RCR, all SYN characters detected within the message
will be discarded and will not be passed on to the RxFIFO. If
STRSYN is reset, SYNs detected within the message will be
treated as data.
DMA CONSIDERATIONS
When the R68561, in the word mode, is used with a DMAC, high
throughput of bit-oriented protocols is achieved. However, problems can arise when trying to DMA byte-oriented data in the word
mode.
esc Transmitter Operation
BOP and BSC have well-defined message boundaries and the
MPCC can detect the end of message, determine if there is an
odd (single) byte at the end of a message, and so inform the
host MPU by setting the Received Half Word (RHW) bit in the
Frame Status byte.
BSC transmission begins with the sending of an opening pad
(PAD) and two sync (SYN) characters. These characters are
programmable and stored in AR1(PAD) and AR2(SYN). The first
SOH or STX initiates the block-check-character (BCC) accumulation. An initial SOH or STX is not included in the BCC accumulation. Should an underrun condition occur, the content of AR2
(normally SYN character) is transmitted until new characters
become available. The message is terminated by the transmission of the BCC followed by a closing pad when an ETB, ITB,
or ETX is fetched from the TxFIFO. The closing PAD is generated by the MPCC.
In byte-oriented protocols (such as ASYNC and COP) there is
no defined message length. In the word mode, received bytes
are grouped in pairs. In the byte mode, each byte is available
through the RxFIFO as it is received. Thus, the MPCC in the
word mode has no way of knowing when an odd (Single) byte
has been received at an end of a transmission to be passed onto
the host MPU. In the word mode received bytes are grouped
in pairs. In the byte mode each byte is available through the FIFO
as it is received.
In transparent mode, the BCC accumulation is initiated by DLESTX and is terminated by the sequences DLE-ETX, DLE-ETB,
or DLE-ITB. See Table 5 for character sequence and inclusion
in CRC accumulation. If an underrun occurs, DLE-SYN characters will be transmitted until new characters are available in the
TxFIFO. ETB, ETX, ITB, or ENQ with a TLAST tag is treated
as a control character and the MPCC automatically inserts a DLE
immediately preceding these characters. DLE-ETB, DLE-ETX,
DLE-ITB, or DLE-ENQ terminates a block of transparent text,
and returns the data link to normal mode. BCC generation is
not used for messages beginning with characters other than
SOH, STX, DLE-SOH, or DLE-STX. On all message types, if the
TSYN bit is set to 1 in the TCR, a SYN-SYN (DLE-SYN sequence
on transparent messages) sequence is transmitted before the
next character is fetched from the TxFIFO.
LEADING PAD
5-8 BITS
(AR1)
SVN
5-8 BITS
(AR2)
SVN
5-8 BITS
(AR2)
Figure 9.
For transmission of data by the MPCC in the word mode, the
MPCC provides a Transmit Half Word (THW) bit in the Transmit Control Register. When set, this bit informs the MPCC that
the last word in the TxFIFO (marked by setting the TLAST bit
with DONE) contains only the upper byte as valid data. However,
the currently available DMACs have no method to inform the
MPCC that the last word of the message contains a single byte
and MPU intervention is necessary.
To handle byte-oriented protocols with DMAC, an R68561 in the
byte mode or the R68560 (byte mode only) should be used.
1+-------
MESSAGE
5-8 BIT CHARACTERS
Character Oriented Protocol Format
4-106
--------+/
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Q)
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Q)
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Q)
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00-015
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DONE
f-.:!!!...
~
Y5
3:
c
0
REOl
MEMORY
A2
It,....
~I §I rl"
~ ~I ~
~l
REao
<0
':'
....--
~
> "
=\
Pu
.?
~-
.
'" 5"/A3
tJ· ~
J
~I illl ~I '1\/,;1 albl
0
,,~
~6
a
=\
o~u 1
BR
8G
BGACK
14 IPLO
14
~
,---
I-I-->h{::
I-- ~
DTACK
....--
'----
I--
AS
R6BOOO
MPU
...
U1
~
1~lt~
~
i"
~
~I
ROSA
R68S6l
MPCC
lACKS
lACK
IACK6
f-li-
"'§I
SYSTEM CLOCK
n
~
oo
~
foo
iRa
~
~
i5A'C'K
2-
3
3
c
:::I
0'
a0'
:::I
(I)
l
CLOCK
OSC
oo
J
:::I
2...
(i'
-
NOTE: UDS MAY BE TIED LOW (GROUND).
3:
"tI
o
Figure 10. Typical Interface to 6BOOO-Based System
II
.n
2J
en
Q)
en
en
5'
2J
en
Q)
en
en
.....
AO-A19
I"
00-07
RM
'--
.Q§.
.--
AS
MC68008
MPU
DTACK
I~
iiR
!9.
BGAeK
I---
r--'iPLo'
IPL.1
74L.Sl-48
~11~'
IPL2
FCO
r----m
gll~,I~
~
~II~'I ~II~II~I
~I
~!I~II~
bll
s::
C
I I¥-"tI
a
I~I
-
r"fc2
r-
El
REQ1~RDSR
!
a
a1;1
Q)
A3
A2
:1
~.
Al
MC68440
DMAC
MEMORY
74LSl38
vo
t~
V3
G2.
V5
IACK5
V6
IAeK6
~~IT~ll~
0
()
OACK
2-
OTC
DONE
VI
V2
V4
qG2A
ACKO
ACK1
R68560
MPCC
0
0
~I
~i
XTAl
IRQ
=
lACK
EXTAl
+5v~J2L
SYSTEM CLOCK
;1
3
3
C
j
n'
S»
o·
j
(/)
I
0
-..2-
CLOCK
DOC
0
j
(i'
-s::
"tI
Figure 11.
Typical Interface to 68008·Based System
0
0
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
SOURCE
MPU
A1-A4
AD'
MPU
BUS
CS
MPU
LOS/OS
UDS2
MPU
RJ'ii
MPCC
DTACK
MPCC
00-015
NOTES:
1. BYTE MODE WHEN CONNECTED TO AD ON 68008 BUS.
2. WORD MODE WHEN CONNECTED TO UDS ON 68000 BUS.
3. TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE
OF 2.0 VOLTS, UNLESS OTHERWISE NOTED.
4. SEE ADDITIONAL NOTES ON PAGE 32.
Figure 12.
MPCC Read Cycle Timing
SOURCE
MPU
A1-A4
AD'
MPU
BUS
CS
MPU
LOS/OS
UDS2
MPU
RiW
MPCC
DTACK
MPU
00-015
i+----{11)----.-jf+--{·
DATA IN
NOTES:
1. BYTE MODE WHEN CONNECTED TO AD ON 68008 BUS.
2. WORD MODE WHEN CONNECTED TO UDS ON 68000 BUS.
3. TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE
OF 2.0 VOLTS, UNLESS OTHERWISE NOTED.
4. SEE ADDITIONAL NOTES ON PAGE 32.
Figure 13.
MPCC Write Cycle Timing
4-109
II
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
SOURCE
INTERNAL
RECEIVER
CLOCK
(BAUD RATE)
MPCC
ROSA
DMAC
DACK
DMAC
LDS/Os
UDS/A02
MPCC
Do-D15
DMAC
R/W
MPCC
DONE
DMAC
DTC
\
I
\
~
@
~
NOTES:
1. TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE
OF 2.0 VOLTS UNLESS OTHERWISE NOTED.
2. WORD MODE ONLY.
3. SEE ADDITIONAL NOTES ON PAGE 32.
Figure 14.
MPCC to Memory DMA Transfer Cycle Timing (Receiver DMA Mode)
4·110
I
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
SOURCE
INTERNAL
TRANSMITTER
CLOCK
(BAUD RATE)
MPCC
/
\
~
@
~
DMAC
LOS/OS
UDS/A02
MEMORY
00-015
I
/
\
DMAC
DMAC
\
R/Iii
DMAC
DMAC
NOTES:
1. TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE
OF 2.0 VOLTS UNLESS OTHERWISE NOTED.
2. WORD MODE ONLY.
3. SEE ADDITIONAL NOTES ON PAGE 32.
Figure 15.
Memory to MPCC DMA Transfer Cycle Timing (Transmitter DMA Mode)
4·111
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
SOURCE
MPCC
IRQ
~~------------------------------~!
lACK
MPU
MPCC
DTACK
MPU
LOS/OS
26
00-07
MPCC
INTERRUPT VECTOR
NOTES:
1. TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH
VOLTAGE OF 2.0 VOLTS, UNLESS OTHERWISE NOTED.
2. IRQ IS NEGATED WHEN ALL BITS IN STATUS REGISTERS THAT COULD HAVE CAUSED THE INTERRUPT
ARE CLEARED.
3. SEE ADDITIONIONAl NOTES ON PAGE 32.
Figure 16. Interrupt Request Cycle Timing
I
MDCC1
MPCC2
MPCC 1
MODEM/DCE
TxC
RxC
TxC
Rx TIMING (DD)
TxD
RxD
TxD
Rx DATA (BB)
RxC
TxC
RxC
Tx TIMING (DA)
RxD
TxD
RxD
Tx DATA (BA)
HIGH SPEED INTERFACE
LOW SPEED (RS-232) INTERFACE
Figure 17. Serial Interlace
4-112
'-
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
HIGH SPEED APPLICATION
~--------~:30r---------~
TxC/RxC
TxD/RxD
LOW SPEED APPLICATION (RS-232 COMPATIBLE)
TxC
TxD
DATA A
II
RxC (TxC)
Figure 18.
Serial Interface Timing
RxD
TxD
NOTE:
TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE
OF 2.0 VOLTS, UNLESS OTHERWISE NOTED.
Figure 19.
Serial Interface Echo Mode Timing
4-113
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
AC CHARACTERISTICS
(Vee = 5.0 Vdc ± 5%, Vss = 0
Vdc, TA = OOC to 70°C)
Number
Parameter
Symbol
Min
Max
Unit
ns
30
-
tCLOAL
0
60
ns
CS, DS Low to Data Valid
t SLOV
0
140
ns
5
DS High to Data Invalid
tSHOXA
10
150
ns
6
DS High to DTACK High
ISHOAT
0
40
ns
1
RIW High to CS, DS Low
t AHSL
0
2
Address Valid to CS, DS Low
t AVSL
3'
CS Low to DTACK Low
4'
ns
7
DS High 10 Address Invalid
ISHA'
20
-
ns
8
CS, DS High 10 RIW Low
ISHRL
20
-
ns
9
RIW Low to CS, DS Low
IRLSL
0
-
ns
10
CS High, DS High 10 RIW High
ISHRH
20
ns
11
Dala Valid 10 CS, DS High
IOVSH
60
-
12
es, DS High to Data Invalid
tSHOXW
0
-
ns
17
DTC Low to DS High
tCLSH
60
-
ns
18
DACK Low 10 Data Valid, DONE Low
t ALOV
0
140
ns
\
ns
19
DS High to Data Invalid
ISHOXOR
10
150
ns
21
Data Valid to DS High
t OVSH
60
22
DS High to Data Invalid
tSHOXOW
0
-
ns
25
lACK Low to DTACK Low
t'ALAL
0
40
ns
26
lACK, DS Low 10 Data Valid
tlALDV
0
140
ns
27
DS High to Data Invalid
10
150
ns
0
40
ns
t'SHO'
28
lACK High to DTACK High
t'AHOAT
30
RxC and TxC Period
tcp
31
TxC Low to TxD Delay
tTCLTO
32
AxC Low to RxD Transition (Hold)
33
RxD Transition to RxC Low (Setup)
34
ns
-
ns
0
200
ns
IRCLRO
0
-
ns
tROACL
30
ns
RxD to TxD Delay (Echo Mode)
tROTO
-
200
ns
35
RIW Low to DACK Low (Setup)
tRLAL
0
-
ns
36
DACK High to DONE High
tAHDH
0
-
ns
372• 3
RDSR Pulse Width
tRPW
1
clock period
382 • 4
TDSR Pulse Width
t TPW
1
-
248
clock period
Notes:
1. For read cycle timing, the MPCC asserts DTACK within the MPU S4 clock low setup time requirement and establishes
valid data (Data In) within the MPU S6 clock low setup time requirement.
2. For synchronous protocols, this is one full serial clock period of RxC for RDSR and TxC for TDSR.
3. For asynchronous protocols, RDSR is asserted for two system clock periods for a prescale factor of 2 and for three system clock
periods for a prescale factor of 3.
4. For asynchronous protocols, TDSR is asserted for a period of one-half the baud rate.
"NOTES TO FIGURES 12-16.
(IsHOXR, item 5) will remain valid for 0-150 ns after the negation of
CS or LOS, whichever is negated first.
Address, LOS, UOS and 'RiW are signals generated by the
68000 MPU and its bus timing prevails. CS is derived with
external logic from the address bus and generally an Address
Strobe (AS) signal from the MPU. It will naturally be delayed
somewhat from the AS signal. The active read or write cycle
timing in the MPCC is during the summation of the active sig·
nal time. i.e., the last.active signal starts the timing sequence.
For an MPCC read cycle, for example, the data out parameter
(IsLOV. item 4) will be available 0 to 140 ns from the falling edge
of CS or LOS whichever is active last. The data out parameter
The minimum pulse widths for CS, LOS, UOS, OACK, lACK and
are not specified since they are system dependent and relate
to system clock timing. For example, it is apparent that the mini·
mum active time for "AND" condition of CS and LOS is 140 ns
(tSLOV • item 4) plus the setup time of the Data In to the receiving
device if LOS high is used to strobe the data in. These same factors hold true for UOS, OACK and lACK. If OTC is used it must be
true a minimum of 60 ns before the rising edge of LOS and thus
this is the minimum pulse width. It may be connected to ground.
orc
4·114
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
Value
Unit
Supply Vollage
Vee
-0.3 to +7.0
V
Input Voltage
VIN
-0.3 to + 7.0
V
Operating Temperalure Range
TA
o to + 70
°C
Siorage Temperature
Tsm
-55 to +150
°C
·NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in other
sections of this document is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
Parameter
Symbol
Thermal Resistance
Ceramic
Plastic
°JA
Value
Rating
°C/W
50
68
DC CHARACTERISTICS
(Vee = 5.0 Vdc ±5%, Vss = 0 Vdc, TA = ooe to 70'e unless otherwise noted)
Symbol
Min
Max
Unit
Input High Voltage
All Inputs
Parameter
VIH
2.0
Vee
V
Input low Voltage
All Inputs
VIL
-0.3
+0.8
V
Input leakage Current
RiW, RESET, CS, Al-A4
liN
-
10.0
p.A
VIN = 0 to 5.25V
Vee = 5.25V
Three-State (Off State) Input Current
IRQ, DTACK, DO-DIS
TTSI
-
10.0
p.A
VIN = 0.4 to 2.4V
Vee = 5.25V
Output High Voltage _ _
RDSR, TDSR, IRQ, DTACK, DO-DIS, DSR, DTR, RTS,
TxD, TxC
VOH
Vss + 2.4
-
V
VOH
Vss + 2.4
-
V
VOL
-
0.5
V
VOL
-
0.5
V
Vee = 4.75V
ILOAD = B.B mA
-
1
W
TA = 25°C
13
pF
VIN = OV
TA = 25°C
f = 1 MHz
BClK
Output low Voltage
RDSR, TOSR, IRQ, DTACK DO-DI5, DSR, DTR, RTS,
TxD, TxC, BClK,
DONE
Internal Power Dissipation
PINT
Input Capacitance
CIN
4-115
Test Conditions
Vee = 4.75V
ILOAD = - 400 p.A
C LOAD = 130 pF
Vee = 4.75V
ILOAD = 0
CLOAD = 30 pF
Vcc = 4.75V
ILOAD = 3.2 mA
II
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
PACKAGE DIMENSIONS -
40-PIN DIP
40-PIN CERAMIC DIP
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 50.29 51.31 1.980 2.020
B
C
o
~FI
~
--I,
--l::'.- , -=I~.
JL ,
I.-
F
G
J
K
L
M
N
14.73 15.24 0.580 0.600
3.30
4.32 0.130 0.170
0.38
0.53 0.015 0.021
1.02
1.52 0.040 0.060
2.54 esc
0.100 esc
0.20
0.30 0.008 0.012
2.54 4.06 0.100 0.160
14.99 15.49 0.590 0.610
0°
10 0
0°
10 0
1.02
1.52 0.040 0.060
•
40-PIN PLASTIC DIP
MILLIMETERS
DIM
A
B
C
o
F
G
H
J
K
L
4-116
MIN
MAX
INCHES
MIN
MAX
51.82 52.32 2.040 2.060
13.72 14.22 0.540 0.560
4.06
5.08 0.160 0.200
0.38
0.53 0.015 0.021
1,14
1.40 0.045 0.055
2.54 esc
0.100 esc
1.40
1.91 0.055 0.075
0.20
0.30 0.008 0.012
3.30
4.32 0.130 0.170
14.48 16.00 0.570 0.630
M
00
10 0
N
0.51
1.02 0.020 0.040
00
10 0
R68560, R68561
PACKAGE DIMENSIONS -
Multi-Protocol Communications Controller (MPCC)
48·PIN DIP
48-PIN CERAMIC DIP
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A SO.35 61.57 2.376 2.424
B
N
14.73 15.24 0.580 0.600
3.30 4.32 0.130 0.170
0.38 0.53 0.015 0.021
1.52 0.040 0.060
1.02
2.54 BSC
0.100 esc
0.20
0.30 0.008 0.012
2.54 4.06 0.100 0.160
14.99 15,49 0.590 0.610
o· 10· o· 10"
1.02
1.52 0.040 0.060
DIM
MILLIMETERS INCHES
MIN MAX MIN MAX
C
D
F
G
J
K
L
M
48-PIN PLASTIC DIP
A
B
C
o
F
G
H
J
K
L
M
N
GO.83 61.85 2.395 2.435
13.72 14.22 0.540 0.560
4.06 5.08 0.160 0.200
0.38 0.53 0.016 0.021
1.14
1.40 0.045 0.055
2.54
esc
0.100
1.40
1.91 0.055
0.20 0.30 0.008
3.30 4.32 0.130
14.48 16.00 0.570
0°
10°
0°
0.51
1.02 0.020
esc
0.075
0.012
0.170
0.630
10°
0.040
'----------------------'
4-117
lEI
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
4-118
Section 5
Intelligent Display Controllers
Page
Product Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-2
10937 and 10957 Alphanumeric Display Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-3
10938 and 10939 Dot Matrix Display Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5-11
10939, 10942 and 10943 Dot Matrix Display Controller . . . . . . . . . . . . . . . . . . . . . . . . ..
5-21
10941 and 10939 Alphanumeric and Bargraph Display Controller. . . . . . . . . . . . . . . . ..
5-31
10951 Bargraph and Numeric Display Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5-41
10955 Segmented Display Controller/Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5-51
5-1
5·2
10937 • 10957
'1'
Rockwell
10937 and 10957
Alphanumeric Display Controller
DESCRIPTION
FEATURES
The 10937 and 10957 Alphanumeric Display Controllers, two
of the Rockwell Intelligent Display Controller products, are
MaS/LSI general purpose display controllers designed to interface to segmented displays (vacuum fluorescent, or LED).
•
•
•
•
•
16 character display driver with decimal point and comma tail
14 or 16 segment drivers
Up to 66 kHz data rate
Direct digit drive of 20 ma at 50 volts
Supports vacuum fluorescent, or LED displays
• 64 x 16-bit PLA provides segment decoding for ASCII
character set (all caps only)
• Serial data input for a-bit display and control data words.
• 40-Pin DIP
The 10937 or 10957 will drive displays with up to 16 characters
with 14 or 16 segments plus a decimal point and comma tail.
Segment decoding within each device provides for the ASCII
character set (upper case only). No external drive circuitry is
required for displays that operate on 20 ma of drive current up
to 50 volts. A 16 x 64-bit segment decoder provides internal
ASCII character set decoding for the display.
ORDERING INFORMATION
Package
Part
Number
Type
109X7P-40
Plastic
109X7P-50
Plastic
109X7PE-40
Plastic
Plastic
109X7PE·50
Note: X - 3 or 5
The 10937 and 10957 are identical with the exception that the
10957 has two additional decodings for the decimal pOint and
comma tail.
Drive
Voltage
40V
50V
40V
50V
6 x 16
DISPLAY
DATA
BUFFER
2 x 16
POR
VSS
VDD
A
DECIMAL PT.
COMMA TAIL
BUFFER
SEGMENT
DRIVERS
(ANODE)
DIGIT DRIVERS
(GRID)
Temperature
Range (OC)
o to +70
o to +70
-40 to +85
-40 to +85
SGA
SGB
SGC
SGD
SGE
SGF
SGG
SGH
SGI
SGJ
SGK
SGL
SGM
SGN
SGO
SGP
PNT
TAIL
10937 and 10957 Block Diagram
Document No. 29000085
Data Sheet
5-3
Order No. 085
Rev. 6, June 1987
Alphanumeric Display Controller
10937 • 10957
INTERFACE DESCRIPTION
VSS
ADI6-ADI
VDD
A
POR
DATA
SCLK
SGA-SGP
TAIL
PNT
Pin No.
Function
1
2-17
18
19
20
21
22
23-38
39
40
Power and signal reference
Digits 16 through 1 driver outputs
DC power connection
A clock output used for testing
Power-on reset input
Serial data input
Serial data clock input
Segments A through P driver outputs
Comma tail driver output
Decimal point driver output
SPECIFICATIONS
MAXIMUM RATINGS'
All voltages are specified relative to Vss.
Parameter
Symbol
Min
Supply Voltage
Input Voltage
Output Voltage
Operating Current
Output Current Digits
Output Current Segments
Operating Temperature
Commercial
Industrial
Storage Temperature
Input Capacitance
Output Capacitance
Voo
VIN
VOUT
+0.3
+0.3
+0.3
Max
V
V
+70
+85
+125
5
10
·C
·C
·C
pF
pF
100
Iso
Iss
0
-40
-55
Tc
TI
TSTG
CIN
COUT
Unit
-20
-20
-50
7
20
10
PNT
TAIL
SGP
SGO
SGN
SGM
SGL
SGK
SGJ
SGI
SGH
SGG
SGF
SGE
SGD
SGC
SGB
SGA
SCLK
DATA
VSS
AD16
ADIS
AD14
AD13
AD12
ADll
AD10
AD9
AD8
AD7
AD6
ADS
AD4
AD3
AD2
AD1
VDD
A
POR
Pin Functions
Signal Name
Pin Configuration
V
mA
mA
mA
"NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this document is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect device reliability.
DC CHARACTERISTICS
Limits (Vss = 0)
Parameter
Supply Voltage (Voo)
Power dissipation
Input DATA, SCLK,
Logic "1"
Logic "0"
Input POR
Logic "1"
Logic "0"
Output Digit and
Segment Strobes
Driver On
Commercial
Industrial
Limits (Vss = +5V)
Max.
Typ.
Min.
Typ.
Max.
Min.
-16.5
-15.0
40
-13.5
100
-11.5
-1.0
Voo
+0.3
-4.2
+4.0
Voo
+5.3
+0.8
-3.0
Voo
+0.3
-10.0
+2.0
Voo
+5.3
-5.0
-10.0
40
-1.5
-1.7
Driver Off 109X7·40
Driver Off 109X7-50
Output Leakage
Input Leakage
Unit
Conditions
-8.5
100
V
mW
V
V
+3.5
+3.3
At 10 mA
V
V
-40
-50
-35
-45
Actual value
determined by
external circuit
V
V
10
10
10
10
Per driver when
driver is off
pA
pA
Notes: All outputs require pulldown resistors. X = 3 or 5 depending on device.
AC CHARACTERISTICS
Parameter
SCLK Clock
On Time
Off Time
Data Input Sample Time
Before SCLK Clock Off
After SCLK Clock Off
Symbol
Min
Ton
TOft
1.0
1.0
Tboff
200
100
Taoff
5-4
Typ
Max
20.0
Unit
p's
p's
ns
ns
Alphanumeric Display Controller
10937 • 10957
SCLK
DATA INPUT
Vss
OV
+5V
CD
-1.0V
+4.0V
-4.2V
+O.8V
CD
SCLK and Serial Data Timing
MSB
LSB
SCLK
DATA
~ ~ ~
~ 1 I~ ~ 1 ~
1 '
I
0
I
I
DATA
DATA
~1
L
~
I
I
I
~
~
1 I
I
I
0
__ ,
0
= 11
(1 CONTROL BIT, 2 COMMAND BITS)
~ DUTY CYCLE
~
~
~
~
01
I
I
0
~ ~ ~ ~ ~
~1~
I
o I
0
CONTROL:
BIT
I
I
COMMAND
BITS
t?dl
DATA
BITS
I
I
= 11
(1 CONTROL BIT, 3 COMMAND BITS)
~ BUFFER POINTER
1 I
I
I
= 15
(1 CONTROL BIT, 3 COMMAND BITS)
~ DIGIT COUNT
1 I
I
I
I
NOTE: CROSSHATCH
SCLK and Serial Data (Control Word) Examples
END OF
DATA WORD
NEXT
DATA WORD
LSB
MSB
~
[\
I\.----H--J
MIN 40 "SEC
MIN 120 "SEC
Data Word LSB/MSB Timing
VDD
~
100,,5
(MIN.)
POR
VDD STABLE
I
I
100 !'5
(MIN.)
I
r---
/
DATA/COMMAND
Ic------t
r--DATA VALID
Power-On Reset Timing
5-5
r---
= DON'T CARE
Alphanumeric Display Controller
10937 • 10957
FUNCTIONAL DESCRIPTION
Table 2. Buffer Pointer Control Codes
The 10937 or 10957 is a general purpose display controller for
multiplexed, segmented displays with up to 16 character positions and 14 or 16 segments, plus decimal paint and comma
tail. No external drive circuitry is needed for displays requiring
up to 20 ma of drive current up to 50 volts. All timing signals
required to control the display are generated in the 10937 or
10957 device without any refresh input from the host processor.
Hex Code
Pointer Value
Character Controlled By
AO
A1
A2
A3
0
1
2
3
4
5
6
7
S
9
10
11
12
13
14
15
AD2
AD3
AD4
ADS
AD6
AD7
ADS
AD9
AD10
AD11
AD12
AD13
AD14
AD1S
AD16
AD1
A4
AS
A6
A7
AS
A9
AA
AB
Input data is loaded into the Display Data Buffer via the Serial
Data Input (Data) channel. Internal timing and control blocks
synchronize the segment and digit output signals to provide the
proper timing for the multiplexing operation. A 16 x 64-bit PLA
is provided for segment decoding for the full ASCII character
set (upper case only).
AC
AD
AE
AF
Digit Counter Control
Input data is loaded into the 10937 or 10957 ADC as a series
of 8-bit words with the most significant bit (MSB), bit 7, first. If
bit 7 of any word loaded is a logic 1 (this bit is referred to as
the control bit C), the loaded word is a control data word. If the
C bit of any word is a logic 0, the loaded word is a display data
word. The following paragraphs describe the format and functions of these control and display data words.
The Digit Counter Control code is normally used only during initialization routines to define the number of character positions to
be controlled. This code maximizes the duty cycie for any display. If 16 characters are to be controlled, enter a value of 0 (zero).
Otherwise, enter the value desired.
Duty Cycle Control
The Duty Cycle Control code is used to turn the display on and off,
and to adjust display brightness. As shown in the block diagram,
the time slot for each character is 32 clock cycles. The segment
and digit drivers for each character are on for a maximum of
31 cycles with a 1 cycle inter-digit off-time. The Duty Cycle Control code contains a 5-bit numeric field which modifies the on-time
for the driver outputs from 0 to 31 cycles. A duty cycle of 0 puts
both the segment and digit drivers Into the off state.
INPUT CONTROL DATA WORDS
When the C-Bit (bit 7) of the 8-bit input word is a logic 1, bits
5 and 6 are decoded into one of four control commands while
data associated with the command are extracted from bits 0 - 4
(see Table 1). The four control codes perform the following
display functions:
• Load the Display Data Buffer pointer,
Test Mode Enable
• Load the Digit Counter,
The Test Mode Enable code is a device test function only. If executed, it will lock the device in the Test Mode. Once locked in,
the device can only be removed from Test Mode by performing
a power-on reset.
• Load the Duty Cycle register,
• Enable the Test Mode.
Table 1 lists the control codes and their functions.
If this mode is activated, the digit time is reduced from 32 to
4 ciock cycles to speed up the output driver sequencing time
for ease in testing.
Buffer Pointer Control
The Buffer Pointer Control code allows the Display Data Buffer
pointer to be set to any digit position so that individual characters may be modified. The Buffer Pointer is loaded with a decimal
equivalent value 2 less than the desired value (i.e., to point to
the digit controlled by AD6 of the display, a value of 4 is entered).
See Table 2 for a complete list of the Buffer Pointer values.
INPUT DISPLAY DATA WORDS
Display data words are loaded as S-bit ASCII format codes. The
64 codes available (with the C-bi! set to 0 to indicate a display
data word) are shown in Table 3 with their corresponding ASCII
characters.
Table 1. Control Data Words
8-Blt Control Word
C-Blt (Bit 7)
7-Bit Code (Bits 6-0)
Function
1
1
1
1
010NNNN(1)
100NNNN(1)
11NNNNN(2)
00NNNNN(3)
BUFFER POINTER CONTROL (Position of character to be changed)
DIGIT COUNTER CONTROL (Number of characters to be output)
DUTY CYCLE CONTROL (On/off and brightness control)
TEST MODE ENABLE (Not a user function)
Notes: 1. NNNN is a 4-bit binary value representing the
digit number to be loaded.
2. NNNNN is a S-bit binary value representing the
number of clock cycles each digit is on.
3. This code is a device test function only. If executed it will lock the device In the test mode.
Once locked in, the device can only be removed
from Test Mode by performing a power-on reset.
5-6
Alphanumeric Display Controller
10937 • 10957
position to be loaded out of the normal sequence, use the Buffer
Pointer Control command before entering the display data word.
It is not necessary to use the Buffer Pointer Control command
to cycle back to position 1 when less than 16 character positions are being used.
Sixteen display data words must be entered to completely load
the Display Data Buffer. The Buffer Pointer is automatically incremented before each data word is stored in the Display Buffer
except for decimal point and comma words. These do not cause
the Buffer Pointer to increment and thus are always associated
with the previous character entered. To select the next character
1 - - : - - . - - - - - - - - 1 DISPLAY CYCLE _ _ _ _ _ _ _ _ _ _ _w-t1
512 BIT TIMES
ADI
~
AD2
~~
AD3
AD4
ADS
AD6
~~
____________________________________________
~r_oL
~~
~~
AD10
ADll
AD12
AD13
~rlL
ADIS
AD16
SGX
_______
~roL
~roL
____________
~rlL
_____________
_____
~~
_________________________________________________
~roL
_________________________________________________
~~------------------~rlL------------------------------------------__ ___________
_______________________
~r-rL
~-~-------------~r-l~---------------------
~~----------------------------~r-IL----------------------------------______________________________
______________________________
~~
~r_IL
-7~--------------------------------~r!~-------------------------____________________________________
_______________________
~~
AD14
___________
~r_oL
______
______________________________________________
____
__________________________________________
~
AD9
~rlL
________________________________________________
~~
AD7
ADS
__
__
~rlL
~
~~
______________________
~r_!~
________________________________________
-l I-
31 BIT TIMES
__________
~L-
I
II
I - . 1-1 BIT TIME
II
~rlL
_ _ _ _ _ _ _ _ _ _ __
~rlL
__________________________
_________________
~~
___________
NOTE:
TIMING SHOWN IS FOR 16 CHARACTERS WITH A DUTY CYCLE OF 31
Figure 1. Display Scan Timing Diagram (Duty Cycle)
Table 3. Character Assignments for Display Data Words
DATA WORD
BINARY
HEX
OXOOOOOO
OXOOOOOI
OXOOO010
OXOOOOll
OXOOO100
OXOO010l
OXOOOll0
OXOO0111
OXOO1000
OX00100l
OX0010l0
OXOO10ll
OXOOll00
OXOOll0l
OXOOlll0
OXOOllll
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
CHARACTER
@
A
B
C
0
E
F
G
H
I
J
K
L
M
N
0
DATA WORD
BINARY
HEX
OX010000
OX01000l
OX0100l0
OX0100ll
OX010l00
OX010l0l
OX010ll0
OX010l11
OXOll000
OXOll00l
OXOll010
OX011011
OXOll 100
OX011 101
OXOll110
OXOlll11
10
11
12
13
14
15
16
17
18
19
lA
lB
IC
10
IE
IF
DATA WORD
CHARACTER
P
Q
R
S
T
U
V
W
X
Y
Z
[
I
I
1\
BINARY
HEX
OX100000
OX10000l
OX1000l0
OX1000ll
OX100l00
OX100l0l
OX100l10
OX100111
OX101000
OX10l001
OX10l0l0
OX101011
OX101100
OX101101
OX10ll10
OXIOll11
20
21
22
23
24
25
26
27
28
29
2A
29
2C
20
2E
2F
CHARACTER
I
"
#
$
%
&
,
(
)
.
+
-
.
\
DATA WORD
BINARY
HEX
OXll0000
OXll0001
OXll00l0
OXll00ll
OXll0l00
OXll0l0l
OX110110
OXll0ll1
OX111000
OX111001
OXlll0l0
OXlll0ll
OXllll00
OX111101
OX111110
OXll1111
30
31
32
33
34
35
36
37
38
39
3A
39
3C
3D
3E
3F
CHARACTER
a
1
2
3
4
5
6
7
8
9
:
;
<
=
>
?
Note: X means this bit (bit 7) is a "don't care" bit except for PNT and TAIL on 10957 only. The hex codes shown assume bit 7 is a zero.
5-7
Alphanumeric Display Controller
10937 • 10957
POWER-ON RESET (POR)
SEGMENT DRIVERS (SGA-SGP)
The Power-On Reset (PaR) initializes the internal circuits of the
10937 or 10957 ADC when power (Voo) is applied. The following conditions are established after a Power-On Reset:
Sixteen (16) Segment Drivers are provided (SGA - SGP), plus
the decimal point (PNT) and comma tail (TAIL). The segment
outputs are internally decoded from the 8-bit characters in the
Display Data Buffer by means of a 64 x 16-bit PLA. The
Segment Driver Allocations are shown in Figure 2. Data codes
and their corresponding segment patterns are shown in Figure 3.
Timing characteristics for the segment outputs are shown in
Figure 1. See paR for the Power-On Reset state of these
drivers.
a. The Digit Drivers (ADl - AD16) are in the off state (floating).
b. The Segment Drivers (SGA-SGP) are in the off state
(floating). This includes PNT and Tail.
c. The Duty Cycle is set to O.
d. The Digit Counter is set to 16 (a bit code value of 0).
e. The Buffer Pointer points to the character controlled by AD1.
DIGIT DRIVERS (AD1-AD16)
The sixteen Digit Drivers (ADl - AD16) are used to select each
of the display digits sequentially during a refresh scan. Display
segments will be illuminated when both the Digit Drivers and
Segment Drivers for a particular character are energized simUltaneously. The timing characteristics of both the digits and
segments are shown in Figure 1. See paR for the Power-On
Reset state of these drivers.
NOTE
For 14-segment displays, SGA is used for the top segment
and SGF is used for the bottom segment. SGB and SGE
can be floated.
Table 4. Comparison of 10957 with 10937
Input
Data
10937
Character
10957
Character
2C
,
,
TYPICAL SYSTEM HOOK-UP
Figure 4 shows the 10937 or 10957 as it would be connected
to a V-F display when driven by a host system. EK is determined by the V-F display specifications and Rc is selected to
provide proper biasing current for zeners. Pull down resistors
RA and RG are determined by the interconnection capacitance
between the device and the display.
2E
BC
,
BE
o
j)
o
PNT } SEE
TAIL TABLE 4
j)
16-SEGMENT
14-SEGMENT
Figure 2. Segment Driver Allocations
5-8
PNT } SEE
TAIL TABLE 4
Alphanumeric Display Controller
10937 • 10957
00
01
I I
I 08 1--1
1=1- I
I
I 09
1--1
I I OA
02
-'J
03
04
05
I
I--
OB
I
I-
00
OE
wi
I_=1
OF
I
11
I
I
I 12 I
1-\
-- I
I I
I
1-\
I
I
lB
14
I
I
lC
I
IE
II
\1
\1
\
I
31
2A
\11
-11\
32
22
I I
30
29
I I
I
I-
24
\
I I
I
2C
----
34
--
35
----
36
= 0 6C'
I 25 III
I
10
26
1\
I I 17 I I IF
I- - I 1/\1
20
\1
2E
[~I
6E' Blank
I
27
2F
/
I
I II 38 I I
II I 1--1
I
I
39
I I
--I
I 3A
-
c=
23 -1-1 2B -1- 33
\
I I 10
I-- I
I 16 I I
1\
21
I
\
28
--
=J
I
20
I 19 \1
I
I lA I
13
1\/1 15
\1
1\
\1
I
I I OC I
I- -I- I
I
I-
06
I
-I-
10 1_-' 18
I
--I 3B I
I I 3C I
--I
I
-I
--I 3D --
--
I
3E
\
\
--
[J
I 3F
I
37
-
I
I
16-Segment Display
I 08 I I
I_I I 1--1
00 -
01
I
04
05
06
I
11
I
I
I 19
\1
1\
20
\ ( 21
\1
I
I-
OB
I 12 I I lA I
1-\
- I
-I
I I 13 I
lB I
1-\
I=1
I I OC I
I I II
I=I
I-
wi
I--=1
00
OE
OF
I
I
14
1\/1 15
I
I-
I
I
1\
I 16 I I
I
I
I-
\1
II
lC
22
\1
29
I I
24 -1-1
\
I 25 I II
I
In
110
1"-
I 17 I I IF
I 1/\1
-
\
I
30
\11
11\
I
I~I
I
I
c.-=:
I
38
39
-
=1
2C
----
34
--
35
6C'
20
I
I
37
I
I I 3C I
--I
I
I
3D - -
-
=1
2F
I I
C_-=I
I I
--I
I 3A
I 3B
-1- 33
2E
\1
---- 36
26
1-\1 6E' Blank
27
I II
31
2A - - 32
23 -1-1
I
IE
I I
I I 2B
\
I
\
28
-
I I OA
I-I I
02
03
I
I
I
1--1 09
10 1_-' 18
I
C_J
3E
I 3F
I
\
-
\
-I
I
14-Segment Display
Notes: Bit 7 01 the data byte is a "don't care" bit except for PNT and TAIL on 10957_ Data byte hex codes shown assume bit 7 is a zero_
• = 10957 only.
Figure 3_
Display Segment Driver Character Patterns
5-9
Alphanumeric Display Controller
10937 • 10957
+5
15V
10~r---------VV~SS;-------~D~A~TiAl.r-----------------~
-------------------1
SCLK ...
10937 OR 10957
VDD ADX
SGX
POR
16
16
TYPICAL
r-:=~:--+-..J\y'V\,_.. ANODE
Rc
TYPICAL
GRID
(DIGIT)
DRIVER
CIRCUIT
RA
(SEGMENT)
DRIVER
CIRCUIT
RG
VDD
VACUUM FLUORESCENT
DISPLAY
-VD1SP
Figure 4.
Partial System Schematic
5·10
HOST
SYSTEM
10938 • 10939
'1'
10938 and 10939
Dot Matrix Display Controller
Rockwell
DESCRIPTION
FEATURES
The Rockwell 10938 and 10939 Dot Matrix Display Controller
is a two-chip MOS/LSI general purpose display controller system
designed to interface to dot matrix displays (vacuum-fluorescent
or LED).
• Standard 5 x 7 character font.
• 20-character display driver cascadable to 80
• Separate cursor driver output
• Direct drive capability for vacuum-fluorescent displays
The two-chip set will drive displays with up to 35 anodes (dots)
and up to 20 grids (characters) plus a cursor. The chips can be
cascaded to drive larger displays of as many as 80 characters.
An internal PLA-type decoder provides character decoding and
dot pattern generation for the full 96-character ASCII set and
an additional 32 special characters.
• 128 x 35 PLA provides segment decoding for full
96-character ASCII set, plus 32 special characters
• Serial or parallel data input for 8-bit display and control
characters
• Brightness, refresh rate, and display mode controls
• 40-pin DIP
ORDERING INFORMATION
Part
Number
Package
Type
10938P
10938PE
10939P
10939PE
Plastic
Plastic
Plastic
Plastic
Temperature
Range (OC)
o to
-40 to
o to
-40 to
I
+70
+85
+ 70
+85
20-CHARACTER 5 x 7 DOT MATRIX DISPLAY
SG01-SG35
STROO-STR19
CURSOR
10939
10938
IANODE DRIVERS AND LATCHES
I INVE:SION
LOGIC
t--
GRID DRIVERS
t
I t
t
1128 x 35 PLA 1
LEVEL
DETECT
LOGIC
8-BIT SHIFt a E r REGISTER
~6~~8T
r--
DATA-LOAD
CONTROL
LOGIC
x 8
I - 20RAM
~
SCLK-DIS
t
1
HOST
Block Dla9ram of 10938 and 10939
Document No. 29000096
Data Sheet
5-11
Order No. 096
Rev. 4, June 1987
Dot Matrix Display Controller
10938 • 10939
INTERFACE DESCRIPTION
10938 Pin Functions
Signal Name
Pin No.
Vss
SG01·SG35
SCLK·DIS
DATA·LOAD
Voo
VGG
2
3·25,27·38
39
40
1
26
10939 Pin Functions
Function
Power and signal reference
Anode driver outputs
Serial data shift clock
Serial data output/latch control
DC Power
Display voltage
DATA-LOAD
SCLK-DIS
SGOI
SG02
SG03
SG04
SG05
SG06
SG07
SG08
SG09
SG10
SGII
_SGI2
VGG
SG13
SG14
SG15
SG16
SG17
Voo
V"
SG35
SG34
SG33
SG32
SG31
SG30
SG29
SG28
SG27
SG26
SG25
SG24
SG23
SG22
SG21
SG20
SG19
SG18
Signal Name
Pin No.
Vss
Voo
CLOCK
CURSOR
MASTER
SIP
SOP
00·07
LD
POR
SCLK-DIS
DATA-LOAD
STROO-STRI9
VGG
36
37
38
14
39
3
2
6-13
5
4
1
40
15-34
35
SCLK-DIS
SOP
SIP
POR
LD
DO
01
02
03
D4
05
06
07
CURSOR
STR19
STR18
STR17
STR16
STR15
STR14
10938 Pin Configuration
Function
Power and signal reference
DC Power
Synchronization Clock
Cursor drive output
Master/Slave Mode control
Sync Input
Sync Output
Serial or parailel data input
Input data strobe
Power-on reset
Serial data shift clock
Serial data output/latch control
Grid Driver Outputs
Display voltage
DATA-LOAD
MASTER
CLOCK
Voo
V"
V••
STROO
STROI
STR02
STR03
STR04
STRD5
STRD6
STR07
STROS
STR09
STR10
STRII
STR12
STR13
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS·
10939 Pin Configuration
Voltages are referenced to Vss
Parameter
Symbol
Value
Unit
Tc
Ti
o to +70
-40 to +85
-55 to +125
·C
·C
·C
Operating Voltage
Voo
-22 to -18
Vdc
Operating Display Voltage
VGG
-50
Vdc
Operating Temperature
Commercial
Industrial
Storage Temperature
"NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in other
sections of this document is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
5-12
Dot Matrix Display Controller
10938 • 10939
DC CHARACTERISTICS
All voltages referenced to Vss
Parameter
Notes
Input 00·07, LD, SIP
Logic "1"
Logic "0"
2
Input POR
Logic "1"
Logic "0"
2
Output SOP
Logic "1"
Logic "0"
2
Output Grids, Cursor, and Anodes
Logic "1" (iload = 10 rnA 10939, 2 rnA 10938)
Logic "0" (iload = 0 rnA)
1
Symbol
Min
Max
VIH
VIL
-1.2
Voo
+0.3
-4.2
V
V
V IHPO
VILPO
-3.0
Voo
+0.3
-10.0
V
V
VOHSY
VOLSY
-1.2
Voo
VOH
VOL
-1.5
VGG
Typ
V
V
Vss
-4.2
Vss
0.95
X
Unit
VGG
V
V
Notes: 1. Designates characteristics for both 10938 and 10939.
2. Designates characteristics for 10939.
OPERATING CURRENTS
Typical
Maximum
Parameter
Unit
Industrial
TA = -40·C
Vee = -22 Vdc
VGG = -50 Vdc
Commercial
TA = O·C
Vee = -22 Vdc
VGG = -50 Vdc
TA = 25·C
Vee = -20 Vdc
VGG = -50 Vdc
4.5
11.2
3.6
9.0
3.2
8.0
rnA
rnA
13.6
1.0
10.9
0.8
6.0
0.5
rnA
rnA
9.1
1.0
7.3
0.8
4.0
0.5
rnA
rnA
10938'
100
IGG
10939 (master)2
100
IGG
10939 (slave)2
100
IGG
Notes:
1. The 10938 has 35 internal drivers which are brought out. IGG is proportional to the number of drivers on. The values given are for
all 35 drivers on. Divide IGG shown by 35 to determine IGG for one driver.
2. The 10939 will never have more than two drivers on at anyone time; one grid driver and the cursor. The values shown are for two
drivers on with 100% duty cycle.
5·13
Dot Matrix Display Controller
10938 • 10939
AC CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Unit
GENERAL INTERFACE TIMING
Data Load (LO)
On Time
Ofllime
Commercial
Industrial
Cycle Time
Commerical
Industrial
T1don
1.0
~s
40.0
44.5
~s
60.0
66.7
~s
T'doff
~s
T ldcyc
~s
SERIAL INTERFACE TIMING
Serial Clock (01)
On Time
OflTime
Cycle Time
1.0
1.0
2.0
Tscon
Tscoff
Tsccyc
20.0
~s
~s
~s
Serial Clock (~O)
Set-up Time
Hold Time
Tssetup
TShOld
Serial Clock to LO Time
T' I
1.0
~s
LO to Serial Clock
Tis
1.0
p's
0
ns
ns
400
400
ns
ns
PARALLEL INTERFACE TIMING
Parallel Data (00-07)
Set-up Time
Hold Time
Tpsetup
200
T phold
TIMING WAVEFORMS
01
(SERIAL CLOCK)
-I
___ S-
LO
-,
00
(OATA)
Serial Interface Timing Waveforms
"'I,I-----TldcyC------I,1
LO
00-07
Parallel Interface Timing Waveforms
5-14
Dot Matrix Display Controller
10938 • 10939
FUNCTIONAL DESCRIPTION
Table 1. Control Word Assignments
Once the display buffer has been loaded from the host processor, the 10938/10939 system generates !III timing signals
required to control the display.
Input data is loaded into the Display Data Buffer as a series of
8-bit words via the Serial or Parallel Data Input channel on the
10939. Internal timing and control logic synchronize the digit output signals with the Serial Data and Load signals to the 10938
to provide the proper timing for the multiplexing operation. A
128 x 35 bit PLA is provided for decoding the full 96 character
ASCII set, plus 32 special characters.
Hex Value
Function
00
01
02
03
04
05
06
07
OB
Not used
Load 01 into Data Buffer
Not used
Not used
Not used
Set digit time to 16 cycles per grid
Set digit time to 32 cycles per grid
Set digit time to 64 cycles per grid
Enable Normal Display Mode (MSB in data words
is used for cursor control only)
Enable Blank Mode (data words with MSB = 1 will
be blanked and cursor will be on)
Enable Inverse Mode (data words with MSB = 1
will be "inversed" and cursor will be on)
Not used
Not used
Not used
Start Display Refresh Cycle (use only once after
reset)
Not used
Not used
Load Duty Cycle Register with lower 6 bits (0-63)
Load Digit Counter (80 = 32, 81 = 1, 82 = 2, etc.)
Not used
Load Buffer Pointer Register with lower 5 bits
Not used
09
OA
The parallel data input mode is implemented by toggling any
of data lines 02-07 after POR has gone low. Once the parallel
data load mode has been implemented, a power-on reset procedure must be performed to return to serial data load mode.
Parallel data transfer is accomplished by putting the command
or display data on the data lines, then pulsing the LD line. The
load cycle time must be at least 60 ".s with the LD line set high
for at least one ".s and held low for at least 40 ".s.
OB
OC
00
OE
OF
10-3F
40-7F
BO-9F
AO-BF
CO-D3
EO-FF
The serial data input mode is implemented during the poweron reset procedure. In those systems using serial mode, ports
02-07 should be tied low to prevent the inadvertent implementation of the parallel load mode. Serial data bytes are shifted
into a data buffer MSB first on line DO using line 01 as the serial
clock. The last eight bits clocked in are latched into the display
controller by a pulse on the LD line. The cycle time for each data
bit is 2 ".s and the load time for each byte is 60 ".s.
Table 2. Buffer Pointer Control Codes
Input data may be Control or Display data. The following
paragraphs describe the format and functions of these control
and display data words.
CONTROL DATA WORDS
Control data words are used to select the operating parameters
of the display controller. They must be preceded by a Control
Prefix word (0000 0001, hexadecimal 01) to be distinguished
from Display Data words.
Buffer Pointer Control
The Buffer Pointer Control code sets the Display Data Buffer
pointer. The lower 5 bits of the code are loaded into the buffer
pointer (see Table 2).
Code
Value
Pointer
Value
Character
Position
CO
Cl
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
DO
01
02
03
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Note:
DO NOT USE CHARACTER POSITIONS 20-31
(CODES D4-DF)
5-15
10938 • 10939
Dot Matrix Display Controller
Digit Counter Control
Table 4. Duty Cycle Control Codes
Digit Time = 16
The Digit Counter Control code defines the number of character
pos"ions (grids) to be controlled. This code is normally used only
during initialization routines, but it may also be used in conjunction with the Duty Cycle Control code to extend the range of
brightness control (see Table 3).
Duty Cycle Control
The Duty Cycle Control code turns the display on and off, adjusts
display brightness, and modifies display timing. The time slot
for each character is 16, 32, or 64 cycles as selected by the Digit
Time Control codes (see Table 1). The anode and grid drivers
for each character are on for a maximum of 13, 29, or 61 cycles
with a 3 cycle inter-digit off-time. The lower 6 bits of the Duty
Cycle Control code are loaded into the Duty Cycle Register.
Resultant duty cycles are shown in Table 4.
Table 3. Digit Counter Control Codes
Code
DIgIt
Counter Value
No. of Grids
Controlled
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
90
9E
9F
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
'18
19
1A
1B
1e
10
1E
1F
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Code
On
Off
40
41
42
43
44
45
46
47
48
49
4A
48
4C
40
4E
4F
50
51
52
53
-
1
2
3
4
5
6
7
8
9
10
11
12
13
13
13
13
13
16
16
16
15
14
13
12
11
10
9
8
7
6
5
4
3
3
3
3
3
58
5C
50
5E
5F
60
61
62
13
13
13
13
13
13
13
13
7C
70
7E
7F
13
13
13
13
DigIt TIme = 32
Digit Time=64
On
Off
On
Off
-
-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
32
32
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
64
64
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
3
3
3
3
3
3
3
3
25
26
27
28
29
29
29
29
7
6
5
4
3
3
3
3
25
26
27
28
29
30
31
32
39
38
37
36
35
34
33
32
3
3
3
3
29
29
29
29
3
3
3
3
58
59
60
61
6
5
4
3
-
-
-
Display Mode Select
Digit Time Select
Each ASCII character is represented by the lower seven bits of
the B-bit value loaded into the 10939. The eighth (most significant) bit controls the cursor (see Cursor Control). This bit is
known as the data byte control bit. If either Blank or Inverse mode
is selected, a "0" in this bit causes a normal character display,
while "1" selects either Blank or Inverse mode, depending on
which mode is enabled. Three control codes are provided (see
Table 1) to enable Blank Mode, Inverse Mode, or Normal Display Mode.
The Digit Time Select code sets the total time for each character
during the refresh cycle. Three values can be set using the three
codes shown in Table 1. The default value set at power-on is
64 cycles per grid. For displays with 40 or more characters, or
under conditions where the display can be subjected to quick
movements during viewing (e.g. portable or vehicle-mounted
applications), it may be necessary to increase the refresh rate
by selecting 16 or 32 cycles per grid with the appropriate control code.
In the Blank mode, any character with the MSB = "1" will be
blanked. In the Inverse mode, it will be displayed with all segment driver outputs inverted. On video displays, this is referred
to as "Inverse Video" format. These controls allow individual
characters or groups of characters to be blinked or blanked by
simply changing the mode without changing the data in the
Display Buffer.
5-16
Dot Matrix Display Controller
10938 • 10939
Cursor Control
b. The Anode Drivers (SG01-SG35) on the 10938 are in the off
state.
c. The Duty Cycle is set to O.
d. The Digit Counter is set to 32.
e. The Buffer Pointer is set to O.
f. The Digit time is set to 64.
g. The Normal display mode is set.
h. DATA-LOAD is set to high impedance state.
L SCLK-DIS is set to VOL to disable the anode drivers in the
10938.
j. SOP is set to VOL to disable the sync pulse.
The data byte control bit (MSB 8), besides selecting Blank,
Inverse, or Normal mode, also controls the cursor output which
is enabled on all characters with the MSB equal to one.
Therefore, when the Normal mode is enabled and the MSB of
the data byte is set to a one, the normal character is displayed
with the cursor on. When the Blank mode is enabled and the
MSB is set to a one, the character is blanked but the cursor is
on. If Inverse mode is enabled and the MSB is set to a one, the
inverse character is displayed and the cursor is on but not
inversed.
Start Refresh
NOTE:
1. When the paR signal is removed, SCLK-DIS is set to the high
impedance state.
2. During the initial rise time of Voo at power turn-on, the
magnitude of VGG should not exceed the magnitude of Voo.
At power on, the 10939 is held in an internal halt mode. The
normal display refresh sequence starts upon receipt of a Start
Refresh control code. This is particularly useful for synchronizing systems using more than one 10939. Only the Master 10939
in a multi-chip system will recognize the Start Refresh code. The
Master starts the Slave(s) at the appropriate time, using the SOP
signal.
GRID (DIGIT) DRIVERS (STROD-STR19) PLUS CURSOR
The 20 Digit Drivers select each of the display character positions sequentially during a refresh scan. Display dots will be illuminated when both the Digit Drivers and Dot Drivers for a
particular character are energized simultaneously. The cursor
segment is generated by the 10939, but its timing characteristics
are identical to the anode timing generated by the 10938.
INPUT DISPLAY DATA WORDS
Display data words are loaded as 8-bit codes. The eighth (most
significant) bit specifies normal (0) or blank/inverse (1) display
mode, depending on the blank/inverse mode selection (see Control data words 09 and OA in Table 1). This bit also controls the
cursor.
ANODE (DOT) DRIVERS (SG01-SG35)
Twenty display data words must be entered to completely load
the Display Data Buffer. The Buffer Pointer automatically increments after each data word is stored in the buffer. To select a
character pOSition to be loaded out of sequence, use the Buffer
Pointer control code. The Buffer Pointer will automatically reset
to character position 0 when its value is equal to the programmed
Digit Count.
35 Dot Drivers are provided in the 10938. The output states for
each character pattern are internally decoded from the 8-bit
characters received from the 10939 by means of a 128 x 35-bit
PLA. Data codes and the corresponding patterns are shown in
Figure 1. Figure 2 shows the Dot Driver (SG01-SG35) assignments as they relate to the 5 x 7 dot matrix patterns.
POWER-ON RESET
TYPICAL SYSTEM HOOKUPS
The Power-on Reset (PaR) initializes the internal circuits of the
10939. This is normally accomplished when power (Voo) is
applied. The following conditions are established by application
of paR:
Figure 3 shows a 10938 and 10939 in a parallel interface with
the host system driving a 20 character display. Figure 4 shows
a 10938 and a 10939 in a serial interface with the host system
driving a 20 character display. Figure 5 shows a 10938 and two
10939's in a parallel interface with the host system driving a
40 character display.
a. The Grid Drivers (STROO-STR19) on the 10939 are in the
off state.
5-17
Dot Matrix Display Controller
10938 • 10939
00
0'
...
...
08
'0
'8
...
...
09
...
.... " ....
.. I: ...
: .. :
20
02
03
OA
OB
...
....
'2
'3
'9
'A
,B
2'
22
23
2A
2B
.. ..
.. ..
...
29
28
30
38
40
48
...
...
: ... :
: ... :
...
: ...
..
:
50
58
:
:
:
:
3'
39
4'
49
5'
68
69
78
7'
79
32
.....
3A
33
3B
:
...
06
... ...
. . . .
07
OC
...
..
...
:
OF
'5
'6
'7
'C
10
,E
1F
24
25
26
27
2C
.....
:
:
: :
OE
'4
:
00
20
34
35
3C
3D
.....
....
...
......
....
2E
36
2F
...
... :
37
3E
3F
46
47
4E
4F
...
42
43
44
....
45
4A
4B
4C
.....
40
52
53
54
55
...
56
57
5C
50
....
5E
5F
.....
...:
.......
...
:
:
...
....
...
:
:
05
....
... ... ...
...
.... .... .... .... ....
..: .....
..
:
: ..
..:
....
... .. .. :.. :
...
...
:
. . .... : ...
... .. ....
...
:
: ...
..
....:
:
6'
:
...
...
59
80
70
......
:
...:
04
.. :
OA
.....
5B
....
62
.... :
63
....
eA
..
..
6B
.....
78
72
:
7A
73
....
...
..
...
....
.....
....
65
6C
...
60
74
..
75
64
7C
:
...
....
....
70
..
..
67
6E
6F
...
76
77
:
7E
7F
.....
Figure 1. 5 x 7 Dot Matrix PLA Patterns
888S8
888se
seese
88888
8e888
88888
seese
Figure 2.
Anode (Dot) Driver Assignments
5-18
:
66
....
...
Dot Matrix Display Controller
10938 • 10939
FILAMENT 1
20-CHARACTER VACUUM TUBE
FLUORESCENT DISPLAY
FILAMENT 2
20
CURSOR STROO-STR19
VOD
10938
SOP
VDD
SIP
Vss
VSS
VGG .-,--=,,-,-r-----,VGG
10939
MASTER
DATA-LOAD
CLOCK
SCLK-DIS
LD
-15V (VDD)
N.C.
POR
·PULWPS ARE REQUIRED
ON ALL INPUTS FROM
TTL SOURCES.
Vss""
Figure 3.
Typical Display System with Parallel Interface to Host System
FILAMENT 1
20-CHARACTER VACUUM TUBE
FLUORESCENT DISPLAY
FILAMENT 2
20
CURSOR STROO-STR19
VDD
VOO
10938
Vss
Vss
VGG . -___c- "''-"--'-----, VGG
SOP
SIP
10939
MASTER
DATA-LOAD
SCLK-DIS
·PULWPS ARE REQUIRED
ON ALL INPUTS FROM
TTL SOURCES.
Figure 4.
CLOCK
LD
01
DO POR 02-07
Vss·
Typical Display System with Serial Interface to Host System
5-19
-15V (VOD)
N.C.
-1SV (VDO)
Dot Matrix Display Controller
10938 • 10939
f---FIL AMENT 1
40 CHARACTER VACUUM TUBE
FLUORESCENT DISPLAY
,....-
35
20)'
SG01-SG35
10938
Voo
,Vss
VGG
~r
II
i"5V
-45V
DATA-LOAD
r
Voo
Vss
VGG
SCLK-DIS
"P ULWPS ARE REQUIRED
oN ALL INPUTS FROM
TTL SOlJRCES.
Vi
~
I
20
CURSOR
CURSOR STROO-STR19
VGG
SIP
SOP
SOP
SIP
MASTER
MASTER r--15V (Voo)
10939
10939
CLOCK (SLAVE)
(MASTER) CLOCK
STROO-STR19
LD
VSS"L
I---FILAMENT 2
,II
OO-D7 POR
V8
If
LD
DO-D7 POR
1 1
-
---
DATA RES
I/O
CONTROL
HOST SYSTEM
Figure 5. Typical Display System with Parallel Interface to Host and Two 10939 Devices
5-20
i"5V (VSS)
Voo
Vss
VGG
10939 • 10942 • 10943
'1'
10939, 10942, and 10943
Dot Matrix Display Controller
Rockwell
DESCRIPTION
FEATURES
The Rockwell 10939,10942, and 10943 Dot Matrix Display Controller is a three-<:hip MaS/LSI general purpose display controller
system designed to interface to dot matrix displays (vacuumfluorescent or LED).
•
•
•
•
20-character display driver cascadable to BO characters
Standard 5 x 12 character font
Separate cursor driver output
Two 12B x 23 PLAs provide decoding for full 96-character
ASCII set plus 32 special characters
• Serial or parallel data input for B-bit display and control
characters
• Brightness, refresh rate, and display mode controls
The three-chip set will drive displays with up to 46 anodes (dots)
and up to 20 grids (characters) plus a cursor. The chips can be
cascaded to drive larger displays of up to BO characters. An
internal PLA-type decoder provides character decoding and dot
pattern generation for the full 96-character ASCII set and an
additional 32 special characters.
•
•
10939 provided in 40-pin DIP
10942 and 10943 provided in 2B-pin DIP
ORDERING INFORMATION
Pan
Number
Package
Type
10939P
10939PE
10942P
10942PE
10943P
10943PE
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
Temperature
Range (DC)
o to
-40 to
o to
-40 to
o to
-40 to
+70
+85
+70
+85
+70
+85
C-
20-CHARACTER 5 x 12 DOT MATRIX DISPLAY
23 .} SG01-SG23
1 ANODE DRIVERS AND LATCHES
-I
t
t
I-
t
t
t
10943
\
LEVEL
DETECT
DATA-LOAD
LEVEL
DETECT
1128 x 23 PLA 1
--I
J- SG01-SG23
r+l ANODE DRIVERS AND LATCHES I
~
10942
INVERSION \
LOGIC
23
r-'~
DET
8-BIT SHIFT REGISTER
illB-r"'"
SCLK-DIS
DET
1
20 x 8
RAM
CONTROL
LOGIC
GRID
DRIVERS
t
10939
I
INVERSION
LOGIC
\_
t
1128 x 23 PLA 1
t
8-BIT SHIFT REGISTER
I-
CURSOR
I
STROO-STRI9
20
HOST
I
Block Diagram of 10939, 10942, 10943
Document No_ 29000099
Data Sheet
5-21
Order No_ 099
Rev. 3, June 1987
Dot Matrix Display Controller
10939 • 10942 • 10943
INTERFACE DESCRIPTION
10939 Pin Functions
Signal Name
10942 and 1 0943 Pin Functions
Signal Name
Pin No.
Function
Voo
Vss
SG01-SG23
VGG
SCLK·DIS
DATA·LOAD
1
2
3-17. 19-26
18
27
28
DC Power
Power and signal reference
Anode (Dot) driver outputs
Display voltage
Serial data shift clock
Serial data outputllatch control
VDD
Vss
SG23
SG22
SG21
SG20
SG19
SG18
SG17
SG16
SG15
SG14
SG13
SG12
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vss
Voo
CLOCK
CURSOR
MASTER
SIP
SOP
00-07
LD
POR
SCLK·DIS
DATA·LOAD
STROO-STR19
DATA-LOAD
SCLK-DIS
SGOl
SG02
SG03
SG04
SG05
SG06
SG07
SG08
VGG
SCLK-DIS
SOP
SIP
POR
LD
DO
01
02
03
04
05
06
07
CURSOR
STR19
STR18
STR17
STR16
STR15
STR14
Vaa
SG09
SG10
SG11
10942 and 10943
Pin Configurations
Pin No.
36
37
38
14
39
3
2
6-13
5
4
1
40
15-34
35
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Function
Power and signal reference
DC Power
Synchronization Clock
Cursor driver output
Master/Slave Mode control
Sync Input
Sync Output
Serial or parallel data input
Input data strobe
Power·on reset
Serial data shift clock
Serial data outputllatch control
Digit (grid) driver outputs
Display voltage
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
DATA-LOAD
MASTER
CLOCK
VDD
Vss
VGG
STROO
STROl
STR02
STR03
STR04
STR05
STR06
STR07
STR08
STR09
STR10
STR11
STR12
STR13
10939 Pin Configurations
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS·
Voltages are referenced to Vss. where Vss = +5 Vdc
Parameter
Operating Temperature
Commercial
Industrial
Storage Temperature
Symbol
Value
Unit
o to + 70
-40 to +85
-55 to + 125
·C
·C
·C
·NOTE: Stresses above those listed under ABSOLUTE MAX·
IMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
other sections of this document is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
TA
Ts
Operating Voltage
Voo
-2210-18
-20 typical
Vdc
Operating Display Voltage
VGG
-50
Vdc
5·22
Dot Matrix Display Controller
10939 • 10942 • 10943
DC CHARACTERISTICS
(Vee = -18.0 to -22 Vdc, Vss
Parameter
10942 and 10943
Output Anodes (Dots)
Logic "1" (I LOAO = 2 mAl
Logic "0" (I LOAD = 0 mAl
10939
Input 00-07, LO, SIP
Logic "1"
Logic "0"
Input POR
Logic "1"
Logic "0"
Output SOP
Logic "1"
Logic "0"
Output Digits, Cursor
Logic "1" (I LOAO = 10 mAl
Logic "0" (I LOAo = 0 mAl
Note: TA
= O°C
0 Vdc, unless otherwise noted. All voltages referenced to Vss .)
Symbol
Min.
Max.
Unit
Vss
0.95 X VGG
V
V
Typical
VOH
VOL
-1.5
VGG
V'H
V'L
-1.2
Voo
+0.3
-4.2
V
V
V'HPO
V'LPO
-3.0
Voo
+0.3
-10.0
V
V
VOHSY
VOLSY
-1.2
Voo
Vss
-4.2
V
V
VOH
VOL
-1.5
VGG
Vss
0.95 x VGG
V
V
to + 70°C (commercial) or - 40°C to + 85°C (industrial), unless otherwise noted.
OPERATING CURRENTS
Maximum
Parameter
Typical
Industrial
TA
-40°C
Voo
-22 Vdc
VGG
-50 Vdc
Commercial
TA
O°C
Voo
-22 Vdc
VGG
-50 Vdc
4.5
7.4
3.6
5.9
3.2
5.3
mA
mA
13.6
1.0
10.9
0.8
6.0
0.5
mA
mA
9.1
1.0
7.3
0.8
4.0
0.5
mA
mA
=
=
=
=
=
=
= 25°C
= -20Vdc
= -50 Vdc
TA
Voo
VGG
Unit
10942 or 10943
100
IGG'
10939 (master)
100
IGG2
10939 (slave)
100
IGG 2
Notes:
1. The 10942 and 10943 each have 23 driver outputs. IGG is proportional to the number of drivers on. The values given are for all 23 drivers
on. Divide IGG shown by 23 to determine IGG for one driver. Multiply IGG by 2 to find total current requirements for all drivers on for both
devices.
2. The 10939 will never have more than two drivers on at anyone time; one grid driver and the cursor. The values shown are for two drivers
on with 100010 duty cycle.
5-23
Dot Matrix Display Controller
10939 • 10942. 10943
AC CHARACfERISTICS
Parameter
Symbol
Data Load (LO)
On Time
OlfTime
Commercial
Industrial
Cycle Time
Commercial
Industrial
Min.
Tldon
Tldott
Typical
Max.
Unit
1.0
~s
40.0
44.5
~s
60.0
66.7
~s
~s
T,dcyc
SERIAL INTERFACE TIMING
Seriat Clock (01)
On Time
OlfTime
Cycle Time
Serial Data (~O)
Set-up time
Hold Time
Serial Clock to LO Time
LO to Serial Clock
1.0
1.0
2.0
Tscon
Tscoff
Tsccyc
20.0
~
~s
~
400
400
1.0
1.0
Tssetup
TShOld
TSI
TIS
PARALLEL INTERFACE TIMING
Parallel Data (00-07)
Set-up Time
Hold Time
~
ns
ns
~s
~
0
200
Tpsetup
Tphold
ns
ns
TIMING WAVEFORMS
01
(SERIAL CLOCK)
·1
___ --.I
LO
-I
00
~-----
(DATA)
Serial Interface Timing Waveforms
I.
T,dcyc
j. T ,do"
LO
____~I
p.nupL
_I.
J
-----1.1
Tldolt
---f
I~______~r---
Tphold
Do-07
Parallel Interface Timing Waveforms
5-24
Dot Matrix Display Controller
10939 • 10942 • 10943
FUNCTIONAL DESCRIPTION
time slot for each character is 16, 32, or 64 cycles as selected
by the Digit Time Control codes (see Table 1). The segment and
digit drivers for each character are on for a maximum of 13, 29,
or 61 cycles with a 3 cycle inter-digit oil-time. The lower 6 bits
of the Duty Cycle Control code are loaded into the Duty Cycle
Register. Resultant duty cycles are shown in Table 4.
Once the display buller has been loaded from the host
processor, the 10939, 10942, and 10943 system generates all
timing signals required to control the display.
Input data is loaded into the Display Data Buffer as a series of
8-bit words via the Serial or Parallel Data Input channel on the
10939. Internal timing and control logic synchronize the digit output signals with the Serial Data and Load signals to the
10942/10943 to provide the proper timing for the multiplexing
operation. Two 128 x 23 bit PLAs, one in the 10942 and the
other in the 10943, decode the full 96-character ASCII set plus
32 special characters.
Table 1.
The parallel data input mode is implemented by toggling any
of data lines 02-07 after POR has gone low. Once the parallel
data load mode has been implemented, a power-on reset procedure must be performed to return to serial data load mode.
Parallel data transfer is accomplished by putting the command
or display data on the data lines, then pulsing the LD line. The
load cycle time must be at least 60 /Ls with the LD line set high
for at least one /LS and held low for at least 40 /Ls.
Function
00
01
02
03
04
05
06
07
08
Not Used
Load 01 into Data Buffer
Not used
Not used
Not used
Set Digit Time to 16 cycles per grid
Set Digit Time to 32 cycles per grid
Set Digit Time to 64 cycles per grid
Enable Normal Display Mode (MSB in data words
is ignored
Enable Blank Mode (data words with MSB = 1 will
be blanked)
Enable Inverse Mode (data words with MSB = 1 will
be "inversed")
Not used
Not used
Not used
Start Display Refresh Cycle (use only once after
reset)
Not used
Not used
Load Duty Cycle Register
Load Digit Counter (80 = 32,81 = 1,82 = 2, etc.)
Not used
Load Buffer Pointer Register with lower 5 bits
Not used
09
OA
The serial data input mode is implemented during the poweron reset procedure. In those systems using serial mode, ports
02-07 should be tied low to prevent the inadvertent implementation of the parallel load mode. Serial data bytes are shifted into
a data buffer MSB first on line DO using line 01 as the serial
clock. The last eight bits clocked in are latched into the display
controller by a pulse on the LD line. The cycle time for each data
bit is 2 /LS and the load time for each byte is 60 /Ls.
OB
OC
00
OE
OF
10-3F
40-7F
80-9F
AD-BF
CO-OF
EO-FF
Input data may be Control or Display data. The following
paragraphs describe the format and functions of these control
and display data words.
Table 2.
CONTROL DATA WORDS
Control data words are used to select the operating parameters
of the display controller. They must be preceded by a control
prefix word (0000 0001 , hexadecimal 01) to be distinguished from
display data words.
Buffer Pointer Control
The Buffer Pointer Control code sets the Display Data Buffer
pointer. The lower 5 bits of the code are loaded into the buffer
pointer (see Table 2).
Digit Counter Control
The Digit Counter Control code defines the number of character
pOSitions (grids) to be controlled. This code is normally used only
during initialization routines, but it may also be used in conjunction with the Duty Cycle Control code to extend the range of
brightness control (see Table 3).
Duty Cycle Control
The Duty Cycle Control code is used to turn the display on and
oil, to adjust display brightness, or to modify display timing. The
Control Word Assignments
Hex Value
Buffer Pointer Control Codes
Code
Value
Pointer
Value
Character
Position
CO
Cl
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
DO
01
02
03
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Note: Do not use character positions 20-31 (Codes D4-DF).
5-25
Dot Matrix Display Controller
10939 • 10942 • 10943
Table 3
Digit Counter Control Codes
Code
Digit
Counter Value
No. of Grids
Controlled
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
80
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
90
9E
9F
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
1F
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Table 4
Duty Cycle Control Codes
Digit Time = 16
Digit Time Select
The Digit Time Select code sets the total time for each charac·
ter during the refresh cycle. Three values can be set using the
three codes shown in Table 1. The default value set at poweron is 64 cycles per grid. For displays with 40 or more characters,or under conditions where the display can be subjected to
quick movements during viewing (e.g. portable or vehiclemounted applications), it may be necessary to increase the
refresh rate by selecting 16 or 32 cycles per grid with the appropriate control code.
Digit Time = 32
Digit Time _ 64
Code
On
Off
On
Off
On
Off
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
4F
50
51
52
53
-
-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
32
32
32
31
30
29
28
27
26
26
24
23
22
21
20
19
18
17
16
15
-
1
2
3
4
5
6
7
8
9
10
11
12
13
13
13
13
13
16
16
16
15
14
13
12
11
10
9
8
7
6
5
4
3
3
3
3
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
64
64
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
5B
5C
50
5E
5F
60
61
62
13
13
13
13
13
13
13
13
3
3
3
3
3
3
3
3
25
26
27
28
29
29
29
29
7
6
5
4
3
3
3
3
25
26
27
28
29
30
31
32
39
38
37
36
35
34
33
32
7C
70
7E
7F
13
13
13
13
3
3
3
3
29
29
29
29
3
3
3
3
58
59
60
61
6
5
4
3
-
-
-
characters or groups of characters to be blinked or blanked by
Simply changing the mode without changing the data in the Display Buffer.
Cursor Control
The data byte control (MSB 8), besides selecting Blank, Inverse,
or Normal mode, also controls the cursor output which is enabled on all characters with the MSB equal to one. Therefore,
when the Normal mode is enabled and the MSB of the data byte
is set to a one, the normal character is displayed with the cursor on. When the Blank mode is enabled and the MSB is set
to a one, the character is blanked but the cursor is on. If Inverse
mode is enabled and the MSB is set to a one, the inverse character is displayed, and the cursor is on but not inversed.
Display Mode Select
Each ASCII character is represented by the lower seven bits of
the 8-bit value loaded into the 10939. The eighth (most significant) bit is used to turn the cursor (see Cursor Control) on in
Normal display mode. If either Blank or Inverse mode is selected, a "0" in this bit causes a normal character display mode,
while a "1" selects either Blank or Inverse mode, depending
on which mode is enabled. Three control codes are provided
(see Table 1) to enable Blank Mode, Inverse Mode, or Normal
Display Mode.
Start Refresh
At power on, the 10939 is held in an internal halt mode. The
normal display refresh sequence starts upon receipt of a Start
Refresh control code. This is particularly useful for synchronizing
systems using more than one 10939. Only the Master 10939 in
a multi-chip system will recognize the Start Refresh code. The
Master starts the Slave(s) at the appropriate time, using the SOP
signal.
In the Blank mode, any character with the MSB = "1" will be
blanked. In the Inverse mode, it will be displayed with all segment driver outputs inverted. On video displays, this is referred
to as "Inverse Video" format. These controls allow individual
5-26
Dot Matrix Display Controller
10939 • 10942 • 10943
INPUT DISPLAY DATA WORDS
POWER-ON RESET
Display data words are loaded as 8-bit codes. The eighth (most
significant) bit is a dual purpose bit. This bit specifies normal
(0) or blank/inverse (1) display mode, depending on the
blank/inverse mode selection (see control data words 09 and
OA in Table 1). It also controls the cursor output from the 10939;
on (1) or off (0). Note, that this bit always controls the cursor
no matter what display mode is selected.
The Power-On Reset (POR) initializes the internal circuits of the
10939. This is normally accomplished when power (Voo) is
applied. The following conditions are established by the application of POR:
a. The Grid Drivers (STROO-STR19) on the 10939 are in the off
state.
b. The Anode Drivers, SG01-SG23 on the 10942 and
SG01-SG23 on the 10943, are in the off state.
Twenty display data words must be entered to completely load
the Display Data Buffer. The Buffer Pointer automatically increments after each data word is stored in the buffer. To select a
character position to be loaded out of sequence, use the Buffer
Pointer Control code command. The Buffer Pointer will automatically reset to character position 0 when its value is equal
to the programmed Digit Count.
c. The Duty Cycle is set to O.
d. The Digit Counter is set to 32.
e. The Buffer Pointer is set to O.
f. The Digit time is set to 64.
g. The Normal display mode is set.
h. DATA-LOAD is set to high impedance state.
, DIGIT GRID DRIVERS (STROO-STR19) PLUS CURSOR
SCLK-DIS is set to VOL to disable the anode drivers in the
10942 and 10943.
The 20 Digit Drivers select each of the display character positions sequentially during a refresh scan. Display dots are
illuminated when both the Digit Drivers and Anode (Dot) Drivers
for a particular character are energized simultaneously. The
Cursor output is generated by the 10939, but its timing
characteristics are identical to the 46 segment outputs generated
by the 10942 and the 10943.
j. SOP is set to VOL to disable the sync pulse.
NOTE:
1. When th POR signal is removed, SCLK-DIS is set to the high
impedance state.
2. During the initial rise time of Voo at power turn-on, the
magnitude of VGG should not exceed the magnitude of Voo.
ANODE (DOT) DRIVERS (SG01-SG23)
TYPICAL SYSTEM HOOKUPS
A total of 46 Dot Drivers are provided by the 10942 and the
10943. The output states for each ASCII charcter pattern are
internally decoded from the 8-bit characters received from the
10939 by means of two 128 x 23-bit PLAs, one in the 10942
and the other in the 10943. Figure 1 shows the dot matrix drivers
(SG01-SG23) as they relate to the 10942 and 10943. Data codes
and the corresponding character patterns are also shown in
Figure 1.
Figure 2 shows a 10939,10942, and a 10943 in a parallel interface with the host system driving a 20-character display. Figure 3
shows a 10939, 10942, and a 10943 in a serial interface with
the host system driving a 20-character display. Figure 4 shows
two 10939s, a 10942, and a 10943 in a parallel interface with
the host system driving a 40-character display.
5-27
Dot Matrix Display Controller
10939 • 10942 • 10943
~
~
~
.
o
.
o
I!
.<:
.<:
01
02
08
09
OA.
10
11
12
::J
Q.
.<:
03
00
~
.
o
I!
I!
• OB ...
13
E
.
I!
.<:
o
04
05
06
07
OC
OD
OE
OF
15
16
14
....
Segments Driven By 10942
18
•
•
19
...
1A
1B
1C
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
32
33
34
35
36
37
3A
3B
3C
3D
3E
42
43
44
45
46
47
4A
4B
4C
4D
4E
4F
52
53
54
55
56
57
5A
5B
5C
5D
5E
5F
30 •
•
31
...
38
39
40
41.
48.
•
•
50
51
58
59
•
•
.'
'.
88888
88888
88888
888 8
88888
88888
88888
80088
80088
88888
00000
00000
SG19
3F
Segments Driven By 10943
10942 and 10943 Driver Assignments
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73....
74
75
76
n
..
78
79
7A .....
7B
7C
7D
7E
7F
.....
Figure 1.
5 x 12 Dot Matrix PLA Patterns and Driver Assignments
5-28
Dot Matrix Display Controller
10939 • 10942 • 10943
r
23
20-CHARACTER 5 x 12 DOT MATRIX VACUUM FLUORESCENT DISPLAY
1==
FILAMENT 1
FILAMENT 2
~3
SG01-SG23
VSS
-45V
DATA-LOAD
VGG
T
VGG
10943
SCLK-DIS
I
VGG
SG01-SG23
Voo
+5V
V••
10942
I
-15V
Voo
T
Vss
Voo
SOP
SIP
:J
MASTER --15V (Voo)
10939
~
Vss •
.(
STROO-STR19
S
').
·PULLUPS REQUIRED
ON ALL INPUTS FROM
TTL SOURCES.
CLOCK -N.C.
CURSOR
LD
00-07
t
t
1/0
CONTROL
I
20
POR
t
RES
DATA
HOST SYSTEM
Figure 2. Typical Display System with Parallel Interface to Host System
r
I
23
FILAMENT 1
20-CHARACTER 5 x 12 VACUUM FLUORESCENT DISPLAY
23
I
SG01-SG23
VSS
-45V
VGG
SG01-SG23
Voo
+5V
Vss
10942
I
-15V
Voo
10943
VGG
DATA-LOAD
SCLK-DIS
T
I T
VGG
Vss
Voo
SOP
SIP
:J
MASTER --15V (Voo)
10939
-15V(Voo)- 02-07
Vss
.~
·PULLUPS REQUIRED
ON ALL INPUTS FROM
TTL SOURCES.
Figure 4.
CLOCK I-- N.C.
CURSOR
STROO-STR19
LD
01
DO
!
t
t
LATCH SERIAL DATA
CLOCK
HOST SYSTEM
POR
I
2~
t
RES
Typical Display System with Serial Interface to Host System
5-29
FILAMENT 2
Dot Matrix Display Controller
10939 • 10942 • 10943
rt
FILAMENT 1
40-CHARACTER 5 x 12 DOT MATRIX VACUUM FLUORESCENT DISPLAY
FILAMENT 2
t
1'23
SG01-SG23
-15V
Voo
10942
Voo
+5V
-45V
Vss
VGG
23
SG01-SG23
Vss
VGG
20
10943
20
DATA-LOAD
SCLK-DIS
SCLK-DIS DATA-LOAD SOP
SIP
SIP
10939 (MASTER)
VL
POR
'PULLUPS REQUIRED
ON ALL INPUTS FROM
TTL SOURCES.
DO-07
+5V (Vss)- MASTER 10939 (SLAVE)
f-*
r---
CURSOR
STROO-STR19
LD
1"
VGG
SOP
MASTER t-- 15V (Voo)
CURSOR
STROO-STR19
1
I
I
DATA-LOAD SCLKDIS
CONTROL
0
(LOAD)
DO-D7
DATA
RES
lI0
CONTROL
(LOAD)
HOST SYSTEM
'-*-
POR
l
i
Figure 4. Typical Display System with Parallel Interface to Host and Two 10939 Devices
5-30
10941 • 10939
•
.'
~;'.; ~-
'
<
'...'
10941 and 10939
Alphanumeric and Bargraph
Display Controller
Bockwell
.. ,
~
,,- ' .
,
~.
".-
,~
""'.
,,"
DESCRIPTION
FEATURES
The Rockwell 10939 and 10941 Alphanumeric and Bargraph
Display Controller is a two-chip MOS/LSI general purpose display
controller system designed to interface with bargraph and
segmented displays (vacuum-fluorescent or LED).
• 20-character display driver cascadable to 80 characters
The two-chip set will drive displays with up to 16 segments (plus
decimal point and comma tail) and up to 20 grids (characters)
plus a cursor. The chips can be cascaded to drive larger displays
of 80 characters. Segment decoding for ASCII characters and
bargraph patterns is accomplished through an internal PLA.
• Serial or parallel data input for 8-bit display and control
characters
• Direct drive capability for vacuum-fluorescent displays
• 128 x 18 PLA provides segment decoding for ASCII
characters (all caps only) and bargraph patterns
• Brightness, refresh rate, and display mode controls
• Separate cursor driver output
• 10939-40-pin DIP package
• 10941-24-pin DIP package
ORDERING INFORMATION
Part
Number
Package
Type
Temperature
Range (OC)
10941P
10941PE
10939P
10939PE
Plastic
Plastic
Plastic
Plastic
o to +70
-40 to +85
Oto+70
-40 to +85
I
TAIL
20-CHARACTER 16-SEGMENT ALPHANUMERIC OR BARGRAPH DISPLAY
SG01-SGI6
PNT
CURSOR
STROO-STR19
10941
10939
MSEGMENT DRIVERS AND LATCHES
INVE~SION
f
tt
i
8-BIT SHIFT
REGISTER
GRID DRIVERS
t
I ,l-
LOGIC
128 x 18 PLA
I..
LEVEL
DETECT
I
SCLK-DIS
CONTROL
LOGIC
LOGIC
'-r-LEVEL
DETECT
LOGIC
It:--
DATA-LOAD
-
20 x 8
RAM
-
t
I
HOST
Block Diagram of 10941 and 10939
Document No. 29000097
Data Sheet
5-31
Order No. 097
Rev. 3, June 1987
Alphanumeric and Bargraph Display Controller
10941 • 10939
INTERFACE DESCRIPTION
10941 Pin Functions
Signal Name
Pin No.
Vss
SG01·SGI6
SCLK·DIS
DATA· LOAD
PNT
TAIL
Voo
VGG
2
6·15,17·22
23
24
4
5
1
16
Voo
V"
PNT
TAIL
NOT USED
SG16
SG15
SG14
SG13
SG12
SGII
SGIO
10939 Pin Functions
Function
Power and signal relerence
Segment driver outputs
Serial data shift clock
Serial data output/latch control
Decimal Point driver output
Comma Tail driver output
DC Power
Display voltage
'-1...:.::-_ _ _..1-'
DATA·LOAD
SCLK·DIS
SGOI
SG02
SG03
SG04
SG05
SG06
VGG
SG07
SG08
SG09
Signal Name
Pin No.
Vss
Voo
CLOCK
CURSOR
MASTER
SIP
SOP
DO·D7
LD
POR
SCLK·DIS
DATA·LOAD
STROO·STRI9
VGG
36
37
38
14
39
3
2
6·13
5
4
1
40
15·34
35
SCLK·DIS
SOP
SIP
POR
LD
DO
01
02
D3
D4
D5
06
07
CURSOR
STRI9
STRIS
STR17
STRI6
STRI5
STRI4
10941 Pin Configuration
Function
Power and signal reference
DC Power
Synchronization Clock
Cursor driver output
Master/Slave Mode control
Sync Input
Sync Output
Serial or parallel data input
Input data strobe
Power·on reset
Serial data shill clock
Serial data output/latch control
Grid Driver Outputs
Display voltage
DATA·LOAD
MASTER
CLOCK
Voo
Vss
VGG
STROO
STROI
STR02
STR03
STR04
STR05
STR06
STR07
STROS
STR09
STRIO
STRII
STRI2
STRI3
SPECIFICATIONS
10939 Pin Configuration
ABSOLUTE MAXIMUM RATINGS'
Voltages are referenced to Vss
Symbol
Value
Unit
Operating Temperature
Commercial
Industrial
Storage Temperature
Tc
Ti
o to + 70
-40 to +85
-55 to +125
°C
°C
°C
Operating Voltage
Voo
-22to-18
- 20 (typical)
Vdc
Operating Display Voltage
VGG
-50
Vdc
Parameter
'NOTE: Stresses above those listed under ABSOLUTE MAXI·
MUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in other
sections of this document is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
5·32
Alphanumeric and Bargraph Display Controller
10941 • 10939
DC CHARACTERISTICS
All voltages referenced to V5S
Symbol
Min
10941
Output Segments
Logic "1" (iload = 2 mAl
Logic "1" (ILOAO = 0 mAl
Parameter
Max
Unit
VOH
VOL
-1.5
VGG
Vss
0.95 x VGG
V
V
10939
Input 00-07, LD, SIP
Logic "1"
Logic "0"
VIH
V,L
-1.2
Voo
+0.3
-4.2
V
V
Input POR
Logic "1"
Logic "0"
VIHPO
VILPO
-3.0
Voo
+0.3
-10.0
V
V
Output SOP
Logic "1"
Logic "0"
VOHSY
VOLSY
-1.2
Voo
Vss
-4.2
V
V
Output Digits, Cursor
Logic "1" (110ad = 10 mAl
Logic "0" (iload = 0 mAl
VOH
VOL
-1.5
VGG
Vss
0.95 X VGG
V
V
Typ
.~
OPERATING CURRENTS
Maximum
Parameter
Typical
Industrial
TA = -40·C
Voo = -22 Vdc
Vaa= -SOVdc
Commercial
TA = D·C
Voo = -22 Vdc
VGG = -SO Vdc
TA = 2S·C
Voo = -20 Vdc
VGG = -SDVdc
Unit
1
4.5
5.7
3.6
4.6
3.2
4.1
mA
mA
2
13.6
1.0
10.9
0.8
6.0
0.5
mA
mA
2
9.1
1.0
7.3
0.8
4.0
0.5
mA
mA
Notes
10941
100
IGG
10939 (master)
100
IGG
10939 (slave)
100
IGG
Notes:
1. The 10941 has 18 internal drivers which are brought out. IGG is proportional to the number of drivers on. The values given are for
,
all 18 drivers on. Divide IGG shown by 18 to determine IGG for one driver.
2. The 10939 will never have more than two drivers on at anyone time; one grid driver and the cursor. The values shown are for two
drivers on with 100% duty cycle.
5-33
Alphanumeric and 8argraph Display Controller
10941 • 10939
AC CHARACTERISTICS
Parameter
Symbol
GENERAL INTERFACE TIMING
Data Load (LD)
On Time
Off time
Commercial
Industrial
Cycle Time
Commerical
Industrial
Min
Max
Typ
1.0
Tldon
Tldoff
Unit
pS
40.0
pS
44.5
~s
60.0
66.7
pS
Tldcyo
SERIAL INTERFACE TIMING
Serial Clock (01)
On Time
Off Time
Cycle Time
Serial Data (DO)
Set-up Time
Hold Time
Serial Clock to LD Time
LD to Serial Clock
1.0
1.0
2.0
Tscon
TSCOff
Tsccyc
Tsl
Tis
400
400
1.0
1.0
Tpsetup
TphOld
200
Tssetup
TshOld
PARALLEL INTERFACE TIMING
Parallel Data (00-07)
Set-up Time
Hold Time
pS
20.0
~s
"s
pS
ns
ns
pS
~s
ns
ns
0
,
"
TIMING WAVEFORMS
c=-+~
~;ERIAL CLOCK)~
1
-----.t---------II
1-1
!-T,.--I
T'dolf-------1.~1
"--____ --.1
-----II
LD
- - - - - T'dcyc
T S8etup
DO
(DATA)
Serial Interface Timing Waveforms
..I·_-----Tldcyc-----_·~I
14.--- 'doff---...·tl ___
\4--T'don_.+
LD
T
I
00-07
Parallel Interface Timing Waveforms
5-34
1
10941 • 10939
Alphanumeric and Bargraph Display Controller
FUNCTIONAL DESCRIPTION
Table 1. Control Word Assignments
Once the display buffer has been loaded from the host processor, the 10941/10939 system generates all timing signals
required to control the display.
Input data is loaded into the Display Data Buffer as a series of
8-bit words via the Serial or Parallel Data Input channel on the
10939. Internal timing and control logic synchronize the digit output signals with the Serial Data and Load signals to the 10941
to provide the proper timing for the multiplexing operation. A
128 x 18 bit PLA is provided for decoding the character set and
bargraph codes.
Hex Value
Function
00
01
02
03
04
05
06
07
08
Not used
Load 01 into Data Buffer
Not used
Not used
Not used
Set digit time to 16 cycles per grid
Set digit time to 32 cycles per grid
Set digit time to 64 cycles per grid
Enable Normal Display Mode (MSB in data words
is cursor control-only)
Enable Blank Mode (data words with MSB = 1 will
be blanked and cursor will be on)
Enable Inverse Mode (data words with MSB = 1
will be "inversed" and cursor will be on)
Not used
Not used
Not used
Start Display Refresh Cycle (use only once after
reset)
Not used
Not used
Load Duty Cycle Register with lower 6 bits (0-63)
Load Digit Counter (80 = 32, 81 = 1, 82 = 2, etc.)
Not used
Load Buffer Pointer Register with lower 5 bits
Not used
09
OA
The parallel data input mode is implemented by toggling any
of data lines D2-D7 after POR has gone low. Once the parallel
data load mode has been implemented, a power-on reset procedure must be performed to return to serial data load mode.
Parallel data transfer is accomplished by putting the command
or display data on the data lines, then pulsing the LD line. The
load cycle time must be at least 60 "s with the LD line set high
for at least one "s and held low for at least 40 "s.
OB
OC
00
OE
OF
10-3F
40-7F
80-9F
AO-BF
CO-OF
EO-FF
The serial data input mode is implemented during the poweron reset procedure. In those systems using serial mode, ports
D2-D7 should be tied low to prevent the inadvertent implementation of the parallel load mode. Serial data bytes are shifted
into a data buffer MSB first on line DO using line Dl as the serial
clock. The last eight bits clocked in are latched into the display
controller by a pulse on the LD line. The cycle time for each data
bit is 2 "s and the load time for each byte is 60 "s.
Table 2. Buffer Pointer Control Codes
Input data may be Control or Display data. The following
paragraphs describe the format and functions of these control
and display data words.
CONTROL DATA WORDS
Control data words are used to select the operating parameters
of the display controller. They must be preceded by a Control
Prefix word (0000 0001, hexadecimal 01) to be distinguished
from Display Data words. Table 1 shows the Control Word code
assignments and functions.
Buffer Pointer Control
The Buffer Pointer Control code sets the Display Data Buffer
pointer. The lower 5 bits of the code are loaded into the buffer
pointer (see Table 2).
Code
Value
Pointer
Value
Character
Position
CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
DO
01
02
03
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Note:
DO NOT USE CHARACTER POSITIONS 20-31 (Codes D4-DF}.
5-35
Alphanumeric and Bargraph Display Controller
10941 • 10939
Digit Counter Control
Table 4_ Duty Cycle Control Codes
The Digit Counter Control code defines the number of character positions (grids) to be controlled. This code is normally used
only during initialization routines, but it may also be used in conjunction with the Load Duty Cycle control code to extend the
range of brightness control (see Table 3).
Digit Tlme=16
Digit Time Select
The Digit Time Select code sets the total time for each character
during the refresh cycle. Three values can be set using the three
codes shown in Table 1. The default value set at power-on is
64 cycles per grid. For displays with 40 or more characters, or
under conditions where the display can be subjected to quick
movements during viewing (e.g. portable or vehicle-mounted
applications), it may be necessary to increase the refresh rate by
selecting 16 or 32 cycles per grid with the appropriate control code.
Table 3_ Digit Counter Control Codes
Code
Digit
Counter Value
No. of Grids
Controlled
00
01
02
03
04
05
06
07
08
09
OA
08
OC
00
OE
OF
10
11
12
13
14
15
16
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
17
23
24
25
26
27
28
29
30
31
80
81
82
83
84
85
86
87
88
89
8A
88
8C
80
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
98
9C
90
9E
9F
Off
On
Off
On
Off
40
-
-
-
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
32
32
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
17
64
64
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
45
46
47
48
49
4A
48
4C
40
4E
4F
50
51
52
53
1
2
3
4
5
6
7
8
9
10
11
12
13
13
13
13
13
16
16
16
15
14
13
12
11
10
9
8
7
6
5
4
3
3
3
3
3
58
5C
50
5E
5F
60
61
62
13
13
13
13
13
13
13
13
3
3
3
3
3
3
3
3
25
26
27
28
29
29
29
29
7
6
5
4
3
'3
3
3
25
26
27
28
29
30
31
32
39
38
37
36
35
34
33
32
7C
70
7E
7F
13
13
13
13
'3
3
3
3
29
29
29
29
3
3
3
3
58
59
60
61
6
5
4
3
43
44
Duty Cycle Control
18
19
1A
18
1C
10
1E
1F
Digit Time = 64
On
41
42
The Duty Cycle Control code turns the display on and off, adjusts
display brightness, or modifies display timing. The time slot for
each character is 16, 32, or 64 cycles as selected by the Digit
Time Control codes (see Table 1). The segment and digit drivers
for each character are on for a maximum of 13, 29, or 61 cycles
with a 3 cycle inter-digit off-time. The lower 6 bits of the Duty
Cycle Control code are loaded into the Duty Cycle Register.
Resultant duty cycles are shown in Table 4.
Digit Time = 32
Code
-1
-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
significant) bit controls the cursor (see Cursor Control). This bit
is known as the data byte control bit. If either Blank or Inverse
mode is selected, a "0" in this bit causes a normal character
display, while a "1" selects either Blank or Inverse mode,
depending on which mode is enabled. Three control codes are
provided (see Table 1) to enable Blank Mode, Inverse Mode,
or Normal Display mode.
In the Blank mode, any character with the MSB = "1" will be
blanked. In the Inverse mode, it will be displayed with all segment driver outputs inverted. On video displays, this is referred
to as "Inverse Video" format. These controls allow individual
characters or groups of characters to be blinked or blanked by
simply changing the mode without changing the data in the
Display Buffer.
22
Cursor Control
The data byte control bit (MSB 8), besides selecting Blank,
Inverse, or Normal mode, also controls the cursor output which
is enabled on all characters with the MSB equal to one.
Therefore, when the Normal mode is enabled and the MSB of
the data byte is set to a one, the normal character is displayed
with the cursor on. When the Blank mode is enabled and the
MSB is set to a one, the character is blanked but the cursor is
on. If Inverse mode is enabled and the MSB is set to a one, the
inverse character is displayed and the cursor is on but not
inversed.
Display Mode Select
Each ASCII character is represented by the lower seven bits
of the 8-bit value loaded into the 10939. The eighth (most
5-36
10941 • 10939
. Alphanumeric and 8argraph Display Controller
Start Refresh
SEGMENT (ANODE) ORIVERS (SG01-SG16, PNT, TAIL)
At power on, the 10939 is held in an internal halt mode. The
normal display refresh sequence starts upon receipt of a Start
Refresh control code. This is particularly useful for synchronizing systems using more than one 10939. Only the Master 10939
in a multi-chip system will recognize the Start Refresh code. The
Master starts the Slave(s) at the appropriate time, using the SOP
signal.
Eighteen Segment (Anode) Drivers are provided in the 10941The output states for each character pattern and each bargraph
pattern are internally decoded from the B-bit characters received from the 10939 by means of a 12B x 1B-bit PLA. Data codes
and the corresponding segment patterns are shown in Figure 1.
Data codes and the corresponding bargraph patterns are shown
in Figure 2.
~ ~ ~
INPUT DISPLAY DATA WORDS
~
~
~
~
~
II I,
08 :- -~ 0'
10 1_-'
Twenty display data words must be entered to completely load
the Display Data Buffer. The Buffer Pointer automatically increments aiter each data word is stored in the buffer. To select a
character position to be loaded out of sequence, use the Buffer
Pointer control code. The Buffer Pointer will automatically reset
to character position 0 when its value is equal to the programmed
Digit Count.
11
I·
18
121 __
I
21
I
,
2ll
30 I II 31
II I
,I
22
I
I
I
3.
,I
/ \
I
I
U
I I
70
I
69
20
3C
43
I
I
\1
I
I
SA (._
--
I
62
5C
63
64
II
/
SA
72
71
- 6.
\
6C
I
I
I
I
,,3F
3E
I
I
I
55 1I II 56 III
I
I
SF
-.,1
65
"
60
6E -
-
I
SF
I
I" I
175
I
eSGll)
4
(SGOS)
7D
I ILl
In I
I I
I III
1/1\1 7E 171\1
1F
•
PNT
TAIL
SEGMENT DRIVER ASSIGNMENTS
Figure 1.
\
/
(SG02)
3
(SG06)
I
" 1/\1
I 5E
1\
-I
rn~rn ~rn .J
7
I
I
50
\
-I
I
4,1 -
46 1-
--
\
I '4
I
I"
(SG1S)
5-37
I
I
401\1 I 4E I \ I 4F I
I
I I I \1
rn~rn~rn
The 20 Digit (Grid) Drivers select each of the display character
positions sequentially during a refresh scan. Display segments
are illuminated when both the Digit Drivers and Segment Drivers
for a particular character are energized simultaneously. The Cursor segment is generated by the 10939, but its timing characteristics are identical to the 16 segments generated by the 10941.
;
I
2F
2E
I 145 1_
I I I
44
5. I
(SG01)
DIGIT (GRID) DRIVERS (STROO-STR19) PLUS CURSOR
I
I
17
I 1E I I 1F 1_-'
__ t
I' c~
3D - -
//
"I I 1,.1 III 'A I ILl,. I III 70 I It.!
'\1 U,"I
I I I I I I
I- CHARACTER
Note:
1. When the paR signal is removed, SCLK-DIS is set to the high
impedance state.
2. During the initial rise time of Voo at power turn-on, the
magnitude of VGG should not exceed the magnitude of Voo.
--l
-
I 4. I / 4C I
I 1-,
I
4A1
"
60
68
59
,
DE 1- -.! OF
/
50 1_-' "I I 52 1_-'
I
I_'0.1
I \ 53 1= =1 54
"
I,
I
32 1--' 33 ==: 34 1_-'I 35 1= =1
" := =1 37
I
I
I
I
,I
II
23 -'-' 24 U_ 25 I;1=1
26 1=::,1 Z7
I I
I I
I
-' 42
40 I-I I 41 1I I
a. The Grid Drivers (STROO-STR19) on the 10939 are in the
off state·.
b. The Segment Drivers (SG01-SG16) on the 10941 are in the
off state.
c. The Duty Cycle is set to O.
d. The Digit Counter is set to 32.
e. The Buffer Pointer is set to O.
f. The Digit time is set to 64.
g. The Normal display mode is set.
h. DATA-LOAD is set to high impedance state.
SCLK-DIS is set to VOL to disable the anode drivers in the
10941j. SOP is set to VOL to disable the sync pulse.
06 1__ 1 ",1 __ ,
--:
1_- 10
1- -';
\11
2A 71'\ 2. -:- 2C I
I
48 1_ -' 4'
1C
~
-'-'
\
I
38 1_-' 39 1- -' 3A
I
~
~
i ~ 1j
I 14 I I 15 1_-' 16 III III;
I. 1--1.
L
13
I.
-';
28
The Power-On Reset (PaR) initializes the internal circuits of the
10939. This is normally accomplished when power (Voo) is
applied. The following conditions are established by application
of paR:
I
I II
lOA I I 0. 1_-'
00
I DC II 1.
I, 1--\
I__ ~
~
~
~ 1 j
, 04 1- -, 05
- ' 19 - - ' 1A I--l
; 1. 1==1
1-__
20
POWER-ON RESET
I
I
02 1 II 03
01
00
~
c
~
J!
! ~ I ~ 1§1
Display data words are loaded as B-bit codes. The eighth (most
significant) bit specifies normal (0) or blank/inverse (1) display
mode, depending on the blank/inverse mode selection (see Control data words 09 and OA in Table 1). This bit also controls the
cursor.
l6-Segment PLA Character Codes
I
I
I::,I{.I
1/1\1
Alphanumeric and Bargraph Display Controller
10941 • 10939
Figure 2.
16-Segment BarGraph Codes
5-38
Alphanumeric and Bargraph Display Controller
10941 • 10939
TYPICAL SYSTEM HOOKUPS
driving a 20 character display. Figure 5 shows a 10941 and two
10939's in a parallel interface with the host system driving a
40 character display.
Figure 3 shows a 10941 and 10939 in a parallel interface with
the host system driving a 20 character display. Figure 4 shows
a 10941 and a 10939 in a serial interface with the host system
r
FILAMENT 1
20·CHARACTER VACUUM TUBE FLUORESCENT DISPLAY
FILAMENT 2
bo
f16'
PNT TAIL
Voo
Vss
Vaa
10941
SG01-SGI6
~
_
+5V
-45V
_
CURSOR STROO-STRI9
Voo
Vss
VGG
10939
DATA-LOAD
SCLK·DIS
'PULLUPS REQUIRED ON
ALL INPUTS FROM
TTL SOURCES. PULLUP
SHOWN IS TYPICAL.
Figure 3.
SIP
P
MASTER I-- -15V (VOD)
CLOCK I-- N.C.
~
<;>
Vss
SOP
••
LD
DO-D7
!
l
1/0 CONTROL DATA
HOST SYSTEM
POR
l
RESI
Typical Display System with Parallel Interface to Host System
r---~r-----------------------------------------------------~-FILAMENT1
20·CHARACTER VACUUM TUBE FLUORESCENT DISPLAY
FILAMENT 2
20
16
SG01-SGI6
10941
PNT TAIL
CURSOR
Voo
Voo
Vss
Vss
VGG r-""L=~---' VaG
STROO-STR19
SOP
SIP
10939
DATA-LOAD
MASTER
CLOCK
D2-07
'PULLUPS REQUIRED ON
ALL INPUTS FROM
TTL SOURCES. PULLUP
SHOWN IS TYPICAL.
Vss·
Figure 4.
Typical Display System with Serial Interface to Host System
5·39
-15V (voo)
N.C.
-15V (voo)
Alphanumeric and Bargraph Display Controller
10941 • 10939
--
40 CHARACTER VACUUM TUBE FLUORESCENT DISPLAY
FILAMENT 1
FI LAMENT 2
16
20 ~
SG01-SG16 PNT TAIL
VDD
Vss
VGG
10941
~
+5V
-45V
DATA-LOAD
J~
II
LD
vss"L
"PU LLUPS REQUIRED ON
AL L INPUTS FROM
TT L SOURCES. PULLUP
SH OWN IS TYPICAL.
Figure 5.
~
CURSOR
STROO-STR19
VGG
SOP
VDD
SIP
Vss
MASTER r--15V (VDD)
VGG
10939
CLOCK
(MASTER)
SCLK-DIS[
00-07 POR
I
1/0
DATA
CONTROL
HOST
SYSTEM
20 ,-
IA
If
J
CURSOR STROO-STR19
SIP
SOP
MASTER f-- +5V (Vss)
10939
CLOCK
VDD
(SLAVE)
Vss
VGG
LD 00-07 POR
I+-
~
1 r
RES
Typical Display System with Parallel Interface to Host and Two 10939 Devices
5-40
10951
'1'
10951
Bargraph and Numeric
Display Controller
Rockwell
DESCRIPTION
FEATURES
The Rockwell 10951 Bargraph and Numeric Display Controller
is an LSI general purpose display controller designed to interface
to bargraph and numeric displays (vacuum fluorescent or LED).
• 16 segment drivers plus decimal point and comma tail drivers
• 16 digit drivers
• Up to 66 kHz data rate
The 10951 will drive 16-segment bargraph or seven-segment
plus comma and decimal numeric displays with up to 16 display
posijions. The controller accepts command and data input words
on a clocked serial input line. Commands control the onloff duty
cycle, starting character position and number of characters to
display. Encoded data words display bargraph position (single
segment or increasing bar length), numbers, comma, decimal
and selected upper and lower case letters. No external drive
circuitry is required for displays that operate on 20 mA of drive
current up to 50 volts. A 64 x 16-bit segment decoder provides
character set decoding for the display.
• Direct digit drive of 20 rnA for up to 50 volt displays
• Supports vacuum fluorescent or LED displays
• Serial data input for 8-bit display and control data words
• 64 x 16-bit PLA provides data decoding driving
- Any 1 of 16 bargraph segments
-
ORDERING INFORMATION
Package
Type
Drive
Voltage
10951P-40
10951P-50
10951PE-40
10951PE-50
Plastic
Plastic
Plastic
Plastic
40V
50V
40V
50V
+ 70
+70
-40 to +85
-40 to +85
6 x 16
SCLK--H--f
TIMING
AND
CONTROL
-
o to
o to
DISPLAY
DATA
BUFFER
Eight upper and lower case seven-segment characters
Duty cycle adjust
- Character position select
-
Number of characters
• 40-Pin DIP package
64 x 16
PLA
DECIMAL PT.
COMMA TAIL
VSS
VDD
A
SEGMENT
DECODER
SEGMENT
DRIVERS
(ANODE)
2 x 16
POR
segments
• Command functions
Temperature
Range (OC)
DATA--H~
bargrap~
- Comma and decimal
-
Part
Number
1 to 16
- Ten seven-segment numeric characters (0-9)
DIGIT DRIVERS
(GRID)
SGA
SGB
SGC
SGD
SGE
SGF
SGG
SGH
SGI
SGJ
SGK
SGL
SGM
SGN
SGO
SGP
PNT
TAIL
10951 Block Diagram
Document No. 29000094
Data Sheet
Order No. 094
Rev. 3, June 1987
5-41
Bargraph and Numeric Display Controller
10951
INTERFACE DESCRIPTION
10951 Pin Functions
Signal Name
Pin No.
Vss
ADI6-ADI
Voo
A
POR
DATA
SCLK
SGA-SGP
TAIL
PNT
1
2-17
18
19
20
21
22
23-38
39
40
VSS
AD16
AD15
AD14
AD13
AD12
ADl1
AD10
AD9
ADS
AD7
AD6
AD5
AD4
AD3
AD2
ADI
VDD
A
POR
Function
Power and signal reference
Digits 16 through 1 driver outputs
DC power connection
A clock output used for testing
Power·on reset input
Serial data input
Serial data clock input
Segments A through P driver outputs
Comma tail driver output
Decimal pOint driver output
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS·
All voltages are specified relative to Vss.
Parameter
Symbol
Value
Unit
Supply Voltage
Operating Current
Input Voltage
Output Voltage
Output Current Digits
Output Current Segments
Operating Temperature
Commercial
Industrial
Storage Temperature
Input Capacitance
Output Capacitance
Voo
Is
+0.3 to -20
7
+0.3 to -20
+0.3 to -50
20
10
~
mA
V
V
mA
mA
Tc
TI
TSTG
CIN
COUT
to +70
-40 to +85
-55 to +125
5
10
100
VIN
VOUT
10
o
PNT
TAIL
SGP
SGO
SGN
SGM
SGL
SGK
SGJ
SGI
SGH
SGG
SGF
SGE
SGD
SGC
SGB
SGA
SCLK
DATA
10951 Pin Configuration
"NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation 01 the device
at these or any other conditions above those indicated in the
other sections of this document is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
.oC
°C
°C
pF
pF
DC CHARACTERISTICS
Limits (Vss
Parameter
Supply Voltage (V001
Power Dissipation
Input DATA,SCLK,
Logic "I"
Logic "0"
Input POR
Logic "I"
Logic "0:'
Output Digit and
Segment Strobes
Driver On
Commercial
Industrial
Driver Off 10951·40
Driver Off 10951·50
= 01
Limits (Vss = +5V)
Min
Typ
Max
Min
Typ
Max
-16.5
-15.0
40
-13.5
100
-11.5
-10.0
40
-8.5
100
V
mW
-1.0
Voo
+0.3
-4.2
+4.0
Voo
+5.3
+0.8
V
-3.0
Voo
+0.3
-10.0
+2.0
Voo
+5.3
-5.0
-1.5
-1.7
-40
-50
-35
-45
Output Leakage
Input Leakage
Conditions
At 10 mA
V
V
-30 }
-40
Actual value
determined by
external circuit
V
V
10
10
Per driver at
driver off
+3.5 }
+3.3
-35
-45
10
10
Unit
}
p.A
~A
Note: All outputs require Pulldown Resistors.
AC CHARACTERISTICS
Parameter
SCLK Clock
On Time
On Time
Data Input Sample Time
Before SCLK Clock Off
After SCLK Clock Off
Symbol
Min
1.0
1.0
Ton
Toff
Tbolf
Taoff
200
100
5·42
Typ
Max
Unit
20.0
~s
~s
ns
ns
10951
Bargraph and Numeric Display Controller
SCLK
DATA INPUT
Vss
OV
+5V
CD
-1.0V
+4.0V
-4.2V
+0.8V
®
'DATA MUST BE STABLE DURING THIS TIME.
SCLK and Serial Data Timing
SCLK
= 11
(1 CONTROL BIT, 2 COMMAND BITS)
~ DUTY CYCLE
DATA
1
0
DATA
I
~
1
®
I
I§j ~
0
I
DATA
® t®
oI
0
~ ~
1
®
oI
COMMAND
BITS
CONTROL:
BIT
~
DATA
BITS
= 11
(1 CONTROL BIT, 3 COMMAND BITS)
~ BUFFER POINTER
I
~ ~ ~ ~ @I ~
1 I
0
I
I
I
I
= 15
(1 CONTROL BIT, 3 COMMAND BITS)
~ DIGIT COUNT
1
I
I
I
NOTE: CROSSHATCH
SCLK and Serial Data (Control Word) Examples
NEXT
DATA WORD
END OF
DATA WORD------l
SCLK
MIN 40 ,.sEC
MIN 120 ,.sEC
Data Word LSB/MSB Timing
VDD
\
VDD STABILIZED
_100 ,.s-t-100 ,.s(MIN)
(MIN)
POR
I
DATA/COMMAND
/
Power-On Reset
5-43
~~
DATA VALID
= DON'T CARE
8argraph and Numeric Display Controller
10951
FUNCTIONAL DESCRIPTION
Buffer Pointer Control
The 10951 receives commands and data on a serial input line
clocked externally by a separate clock input line. The controller
decodes the commands from control data words, decodes the
data words in accordance with an internal 64 x 16-bit programmable logic array (PLA) and turns on and off segment and digit
output drivers. The segment output patterns are controlled by
the decoded data words while the digit output and segment output timing are controlled by the decoded control words. All timing
signals required to control the display are generated in the 10951
device without any refresh input from the host processor.
The Buffer Pointer Control code allows the Display Data Buffer
pointer to be set to any digit position so that individual characters
may be modified. The Buffer Pointer is loaded with a decimal
equivalent value 2 less than the desired value (i.e., to point to
the digit controlled by AD6 of the display, a value of 4 is entered).
See Table 2 for a complete list of the Buffer Pointer values.
Digit Counter Control
The Digit Counter Control code is normally used only during initialization routines to define the number of character positions
to be controlled. This code maximizes the duty cycle for any
display. If 16 characters are to be controlled, enter a value of 0
(zero). Otherwise, enter the value desired.
Input data is loaded into the Display Data Buffer via the Serial
Data Input (Data) channel. Internal timing and control blocks synchronize the segment and digit output signals to provide the
proper timing for the multiplexing operation. The 16 x 64 PLA
decodes B-bit data words to drive the 16 segment, comma and
decimal point drivers. The decoded data words will drive 16 segments to display bargaph patterns (single segment and mUltiple segment for increasing length displays) or seven-segment
patterns to display numbers, selected upper and lower case
letters, comma and decimal point.
Duty Cycle Control
The Duty Cycle Control code is used to turn the display on and
off, and to adjust display brightness. As shown in the block diagram, the time slot for each character is 32 clock cycles. The
segment and digit drivers for each character are on for a maximum of 31 cycles with a 1 cycle inter-digit off-time. The Duty
Cycle Control code contains a 5-bit numeric field which modifies
the on-time for the driver outputs from 0 to 31 cycles. A duty
cycle of 0 puts both the segment and digit drivers into the off
state. Figure 1 shows the timing characteristics for the segment
outputs.
Input data is loaded into the 10951 as a series of B-bit words with
the most significant bit (MSB), bit 7, first. If the MSB is a logic 1
(this bit is referred to as the control bit C), the loaded word is a
control data word. If the C bit of any word is a logic 0, the loaded
word is a display data word. The following paragraphs describe
the format and functions of these control and display data words.
INPUT CONTROL DATA WORDS
When the C-Bit (bit 7) of the B-bit input word is a logic 1, bits 5
and 6 are decoded into one of four control commands while data
associated with the command are extracted from bits 0-4. There
are four control codes which perform the following display
functions:
• Load the Display Data Buffer painter,
• Load the Digit Counter,
• Load the Duty Cycle register,
• Enable the Test Mode.
Table 1 lists the control codes and their functions.
Table 1.
Test Mode Enable
The Test Mode Enable code is a device test function only. If
executed, it will lock the device in the Test Mode. This mode
can be disabled only by performing a power-on reset.
If this mode is activated, the digit time is reduced from 32 to
4 clock cycles to speed up the output driver sequencing time
for ease in testing.
Control Data Words
8-81t Control Word
C-Blt
7-Bit Code
1
1
1
1
010NNNN'
100NNNN'
11NNNNN2
OONNNNN3
Function
Buffer Pointer Control (Position of character to be changed)
Digit Counter Control (Number of characters to be output)
Duly Cycle Control (On/off and brightness control)
Test Mode Enable (Not a user function)
Note:
1. NNNN is a 4-bit binary value representing the digit number to be loaded.
2. NNNNN is a 5-bit binary value representing the number of clock cycles each digit is on.
3. This code is a device lest function only. " executed it will lock the device in the Test Mode. Test Mode can be
disabled only by performing a power-on reset.
5-44
8argraph and Numeric Display Controller
10951
Table 2.
Buffer Pointer Control Codes
Hex Code
Pointer Value
Character Controlled By
AO
A1
A2
A3
0
1
2
3
4
5
6
7
S
9
10
11
12
13
14
15
AD2
AD3
AD4
AD5
ADS
AD7
ADS
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD1
A4
A5
AS
A7
AS
A9
M
AB
AC
AD
AE
AF
Sixteen display data words must be entered to completely load
the Display Data Buffer. The Buffer Pointer is automatically
incremented before each data word is stored in the Display
Buffer except for decimal point and comma words. The decimal
point and comma words do not cause the Buffer Pointer to
increment and thus are always associated with the previous
character entered. To enter a character position out of the normal
sequence, use the Buffer Pointer control command before entering the display data word. It is not necessary to use the Buffer
Pointer control command to cycle back to position 1 when less
than 16 character positions are being used (Digit Counter", 0).
DIGIT DRIVERS (AD1-AD16)
The sixteen Digit Drivers (AD1 - AD16) are used to select each
of the display digits sequentially during a refresh scan. Display
segments will be illuminated when both the Digit Drivers and
Segment Drivers for a particular character are energized
simultaneously. The timing characteristics of both the digits and
segments are shown in Figure 1. See paR for the Power-On
Reset state of these drivers.
INPUT DISPLAY DATA WORDS
Display data words are loaded as B·bit format codes. There are
64 codes available (with the C-bit set to 0 to indicate a display
data word).
~
AD1
AD2
AD3
AD4
1~4~i------------------15D1IS2PBLAITYTCIMYECSLE----------------------~~~I
: ... 31 BIT TIMES
~_1_B_IT_T_I_M_E____________________________________________~r_l~___________
-+-7--~r-I~--------------------------------------------------~r-I~-------~-r----~rtL----------------------------------------------~
________
______________________________________________
~~
AD5
AD6
AD7
ADS
AD9
r-J, ______________
~
~rtL
-+-+__________
~~
~r_lL_
_______________________________________________
-7~----------------~r-l~------------------------------------------------+~---------------------"rI~----------------------------------------------+~----------------------~~~-------------------------------------------+-+
________________________
___________________________________
~r_t~
AD10
AD11
AD12
AD13
AD14
AD15
-+~r_------------------------------~r-t~--------------------------------------+-+
______________________________
______________________________
~r_tL
~1~------------------------------~r-tL--------------------------+1~------------------------------~r-tL---------------------+1~------------------------------------~r-tL-------------------
AD16
-r1~---------------------------------------------------~r-tL---------------------
SGX
-r-x-'~--------~r-tL------------------------~r-ur!---------------
~I
I
I
I'"
~I
31 BIT TIMES
I'" 1 BIT TIME
II
NOTE:
TIMING SHOWN IS FOR 16 CHARACTERS WITH A DUTY CYCLE OF 31.
Figure 1. Display Scan Timing Diagram (Duty Cycle)
5-45
10951
Bargraph and Numeric Display Controller
POWER·ON RESET (POR)
decimal point are shown in Figure 2. The input codes associated
with seven-segment alphanumeric. comma and decimal point
display are also shown in Figure 2. The complete set of B-bit
codes for the bargraph and alphanumeric display is shown in
Table 3. Note that only segment drivers SGA-SGG are used to
drive the seven-segment characters. Segment drivers SGH-SGP
may be used for other purposes as decoded in accordance with
Table 3. Figure 3 shows the total allocation of the 16-segment
drivers as they would appear on a 7-segment display or a
16-segment bargraph display. Timing characteristics for the
segment outputs are shown in Figure 1. See POR for the
Power-On Reset state of these drivers.
The Power-On Reset (POR) initializes the internal circuits of the
10951 when power (Voo) is applied. The following conditions
are established after a Power-On Reset:
a. The Digit Drivers (AD1-AD16) are in the off state (floating).
b. The Segment Drivers (SGA-SGP) are in the off state (floating).
This includes PNT and TAIL.
c. The Duty Cycle is set to O.
d. The Digit Counter is set to 16 (a bit code value of 0).
e. The Buffer Pointer points to the character controlled by AD1.
SEGMENT DRIVERS (SGA-SGP)
TYPICAL SYSTEM HOOK·UP
Sixteen (16) Segment Drivers are provided (SGA-SGP). plus the
decimal point (PNT) and comma tail (TAIL). The segment. PNT
and TAIL outputs are internally decoded from the B-bit characters
in the Display Data Buffer by means of a 64 x 16-bit PLA. The
driver allocations for the 16-segment bargraph display and
the seven-segment alphanumeric character plus comma and
Figure 4 shows the 10951 as it would be connected to a V-F
display when driven by a host system. EK is determined by the
V-F display specifications and Rc is selected to provide proper
biasing current for zeners. Pull down resistors RA and RG are
determined by the interconnection capacitance between the
10951 and the display.
5-46
10951
Bargraph and Numeric Display Controller
Table 3.
Segment Driver Output Patterns (1
Input Code
Function
7 6 5
4 3
a
a
a
a
a
a
a
a
a
a
a x a
a X a
a x a
a
a
a
a
a
a
a
a
a
a
a
a
a
0 X
X
X
X
X
X
X
X
0 X
a X
2 1
0
a a a a
a 0 a 1
a a 1 0
a a 1 1
a 1 a a
a 1 a 1
a 1 1 a
a 1 1 1
1 0 a a
1 a a 1
1 0 1 a
1 a 1 1
1 1 0 0
0 X 0 0 1 1 0 1
0 X 0 0 1 1 1 0
a X a 0 1 1 1 1
Segment
Segment
Segment
Segment
Segment
Segment
Segment
Segment
Segment
Segment
Segment
Segment
Segment
Segment
Segment
Segment
0 X a 1 a a
a X a 1 a a
a X 0 1 a a
a X a 1 a a
a X 0 1 0 1
a x a 1 a 1
a X 0 1 a 1
0 X a 1 a 1
a X 0 1 1 a
a X a 1 1 a
a X a 1 1 a
a X a 1 1 a
0 X a 1 1 1
a X a 1 1 1
0 X a 1 1 1
a X 0 1 1 1
Segment A On
Segments A&B On
Segment A-C On
Segment A-D On
Segment A-E On
Segment A-F On
Segment A-G On
Segment A-H On
Segment A-IOn
Segment A-J On
Segment A-K On
Segment A-L On
Segment A-M On
Segment A-N On
Segment A-O On
Segment A-P On
a
a
a
a
a
a
a
a
a
a
a
a
a
X 1
X 1
X 1
X 1
X 1
X
0 X
a X
a X
0 X
a X
a X
a
a
a
1
1
1
1
1
1
1
X 1
X 1
X 1
0 X 1
a
a
X
X
0 X
0 X
a X
0 X
0 X
a X
a
a
a
a
a
a
X
X
X
X
X
X
0 X
0 X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
a a
a 1
1
1
0
1
a a
a 1
1 a
1
a
a
1
0
1
1 0
1 1
0 0
a 1
1 0
1 1
a a 0 0 0
0 a a a 1
a a a 1 a
a a a 1 1
0 0 1 0 a
a a 1 a 1
0 a 1 1 a
a a 1 1 1
a 1 0 a a
a 1 0 0 1
a 1 a 1 a
0 1 a 1 1
a 1 1 a a
0 1 1 a 1
a 1 1 1 a
a 1 1 1 1
1 a a a a
1 0 0 a 1
1 a a 1 a
1 a a 1 1
1 a 1 a a
1 0 1 a 1
1 a 1 1 a
1 a 1 1 1
1
1
1
1
1
1
1
1
1
1
1
0 0 0
a a 1
a 1 a
1 0
1 1
1 1
1 1
1 1
10951 Data Codes
1
1
a a
a 1
1 a
1
1
A On
BOn
C On
D On
E On
F On
G On
H On
t On
JOn
K On
L On
M On
N On
0 On
P On
Number 0
Number 1
Number 2
Number 3
Number 4
Number 5
Number 6
Number 7
Number 8
Number 9
Letter P
Letter L
Semicolon
Blank
Decimal
Blank
Number 0
Number 1
Number 2
Number 3
Number 4
Number 5
Number 6
Number 7
Number 8
Number 9
Letter A
Letter b
Letter C
Letter d
Letter E
Letter F
'-r-
= On)
SGA SGB SGC SGD SGE SGF SGG SGH SGI SGJ SGK SGL SGM SGN SGO SGP PNT TAIL
1
1
1
1
1
1
1
Any 1 of
1
16 Segments
1
1
1
1
1
1
1
1
Bargraph
Codes
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 to 16
1
1
1
1
1
1
Segments
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
** Sets decimal output for last character entered.
5-47
AI phanumerlc
and
Special
Codes
1
1
1
Notes:
Sets comma and decimal outputs for last character entered.
,. ,.
,..
1
1
1
1
1
1
...ci-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I--L
Bargraph and Numeric Display Controller
10951
00
I
01
02
I
03
10
09
11
I
19
OA
12
I
1A
OB
13
04
05
I
I
06
-
07
18
08
II
OC
14
OD
15
OE
16
OF
17
II
IIIII-
I
I
I
I
I
I
I
I
I
I
1B
1C
10
1E
1F
SGPSGOSGNSGMSGLSGKSGJ SGI
SGHSGGSGFSGESGDSGCSGBSGA-
-
16-SEGMENT
BARGRAPH
I_I
I- I
20
I_I
I- I
I- I
I- I
I I
I- I
21
22
I- I
I- I
I- I
I- I
I- I
I- I
I- I
I- I
23
24
25
26
I- I
I- I
27
-
I
I
I
II
I
I- I
I
-
I-
- I
II- I
I
I
28
29
2A
2B
I- I
I- I
I- I
- I
I- I
I
I
I-
,
•
2C
30
I I
I- I
31
32
33
34
2D
35
2E
• 36
2F
37
-
I
I
I
II
I
I- I
I
I- I
II- I
-
I
I
38
39
3A
3B
3C
3D
3E
3F
SGA
SGB
SGF
SGG
SGE
SGC
SGD
• PNT
'TAIL
7-SEGMENT
ALPHANUMERIC
Figure 2. Segment Allocation and 7-Segment Alphanumeric Codes
5-48
I- I
I- I
I- I
- I
I- I
I I
II- I
I
I- I
I- I
IIII
Bargraph and Numeric Display Controller
10951
00
01
02
03
04
05
06
07
08
09
OA
DB
DC
00
DE
OF
I
SEE FIGURE 2
7-SEGMENT
CHARACTERS
SGP_
SGO_
SGN_
SGM_
SGL_
SGK_
SGJ_
SGI_
SGH_
SGG_
SGF_
SGE_
SGD_
SGC_
SGB_
SGA_
BARGRAPH
CODES
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
1F
SEE FIGURE 2
1
7-SEGMENT
CHARACTERS
SGP_
SGO_
SGN_
SGM_
SGL_
SGK_
SGJ_
SGI_
SGH_
SGG_
SGF_
SGE_
SGD_
SGC_
SGB_
SGA_
BARGRAPH
CODES
20
21
10
22
23
24
25
26
2
3
4
5
6
27
7
28
29
8
9
2A
P
2B
2C
20
2E
2F
L
1
SGP_
SGO_
SGN_
SGM_
SGL_
SGK_
SGJ_
SGI_
SGH_
SGG_
SGF_
SGE_
SGD_
SGC_
SGB_
SGA_
7-SEGMENT
CHARACTERS
• = PNT and TAIL both set
•• = PNT only set
SPECIAL
BARGRAPH
CODES
30
10
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
2
3
4
5
6
7
8
9
A
b
C
d
E
FI
7-SEGMENT
CHARACTERS
SGP_
SGO_
SGN_
SGM_
SGL_
SGK_
SGJ_
SGI_
SGH_
SGG_
SGF_
SGE_
SGD_
SGC_
SGB_
SGA_
SPECIAL
BARGRAPH
CODES
Figure 3. Total Character Allocation for Bargraph or 7-Segment Displays
549
10951
Bargraph and Numeric Display Controller
+5
Vss
15V
DATA
10,.f
SCLK
10951
+5
VDD
ADX
SGX
POR
16
TYPICAL
GRID
(DIGIT)
TYPICAL
ANODE
(SEGMENT)
DRIVER
DRIVER
CIRCUI",T~......_C_IR_C_UI_T+
VACUUM
FLUORESCENT
DISPLAY
~
___
Sf __ _
RG
..--r--------il----50000
ULATCH
CR
DLAY2
WATEO
WATE
WATEI
TO GET 50 MS DELAY
LDA
STA
NOP
DEC
BPL
RTS
WAIT 27US
STORE LOOP COUNTER
#$00
WAITER
WAITER
WATEI
DLAYI
TIMING WAVEFORMS
I""'·----TLOCYC----Ooil
LD
40
1
Do-D7
"sec· ..
"sec ..
T LOOFF
T LOON
o .. TpSETUP
1,.sec .. TPHOLO
60 ,..sec. .. T LOCYC
·FOR INDUSTRIAL RATED PARTS SUBSTITUTE 44.5 FOR 40
66.7 FOR 60
Parallel Interface Timing Waveforms
2 "sec '" TSCCYC
1 ,.sec .. TSCON .. 20 ,..sec
1 ,.sec .. TSCOFF
LD
1,.sec '" TSSETUP
1 ,.sec '" TSHOLO
DO
(DATA)
1,.sec '" TLOON
,.sec· '" TLDOFF
40
,.sec· '"
60
TLOCYC
1,.sec '" TLS
1,.sec '"
TSL
·FOR INDUSTRIAL RATED PARTS SUBSTITUTE 44.5 FOR 40
66.7 FOR 60
Serial Interface Timing Waveforms
6-11
Application Note
10938/10939 Display Controller System
Output A Character-Serial
This version of OPUT performs a serial data transfer from the
host system to the selected 10939(s). Load line timing is the
same for serial data transfer as it is for parallel data transfer.
Serial data is shifted into each 10939 most significant bit first.
It is not necessary to reload character data between load line
pulses so a string of identical characters (when blanking the
display for example) may be loaded by successively pulsing the
load line.
OUTS1
OUTPUT A CHARACTER
OUTPUT NEXT
DATA BIT
(BEGIN WITH
MSB)
SERIAL OUTPUT MSB FIRST
HOLD = LOAD LlNE(S)
ACC OR DATA = DATA
OPUT
STA DATA
OUTPUT lDX #$08
lDA DATA
STA SDATA
WHEN DATA IN ACC
INIT COUNTER
FETCH DATA
OUTSI
DATA BIT TO C
INITACC
ROL SDATA
LDA #$01
BIT 1 = SERIAL CLOCK LINE
BIT 0 = DATA BIT
ROL
STA
AND
STA
DEX
BNE
OUTPT
Flowchart: Serial Data Transfer to Display Controllers
6-12
A
PBIO
#01
PBIO
DATA & SER CLK IN ACC
OUTPUT DATA, TURN ON SER ClK
OUTSI
OUTPUT NEXT BIT
TURN OFF SER ClK
ROL SDATA
RESTORE CARRY
LDA
STA
JSR
lDA
STA
LDA
JSR
RTS
SET LOAD LlNE(S) HI
HOLD
PCIO
WATEO
#00
PCIO
#02
WATE
WAIT 20 US
SET LOAD LlNE(S) LO
WAIT 40 US
Application Note
10938/10939 Display Controller System
Output A Character-Parallel
This version of subroutine OPUT performs a parallel data transfer
from the host system to one or both of the 10939'5. Note that
this subroutine contains two time delays. These are used to
adjust the load line off and load cycle times. Also, it contains
two entry points. OPUT is used when the output data is in the
accumulator and OUTPUT is used, when the output data has
been stored in RAM location DATA.
OUTPUT A CHARACTER
PARALLEL OUTPUT
HOLD = LOAD LlNE(S)
ACC OR DATA = DATA
OPUT
OUTPUT
STA
LDA
STA
DATA
DATA
PBIO
WHEN DATA IN ACC
FETCH DATA
OUTPUT DATA
OUTPT
LOA
STA
JSR
LOA
STA
LDA
JSR
RTS
HOLD
PCIO
WATEO
#00
PCIO
#02
WATE
SET LOAD LlNE(S) HI
WAIT 20 US
SET LOAD LINE(S) LO
WAIT 40 US
Flowchart: Parallel Data Transfer to
Display Controllers
Send A Control Word
CMND sends a control word from the host system to the selected
10939(s). The accumulator is loaded wtth the control word prior
to the transfer to this subroutine.
SEND A COMMAND
ACC = COMMAND
CMND
Flowchart: Send a Control Word to
Display Controllers
6-13
PHA
LDA #$01
JSR OPUT
PLA
JSR OPUT
RTS
PREPARE DISPLAY DRIVER
FOR CONTROL WORD
SEND CNTL WORD
Applicaticm Note
10938/10939 Display Controller System
Initialize Display Drivers .
r"\
TRNON
TRNON is an.ex1mple of an initialization routine.
SET UP DISPLAY CONTROLLER
TRNON LOA
STA
STA
STA
TRN1
#$00
POlO
PCIO
PBIO
DISABLE 10939'S
SET LOAD LINES LOW
SET DATA LINES LOW
LOY
JSR
#$01
DLAYO
WAIT 50 MS
LOA
STA
#$01
POlO
RELEASE POR
LOY
JSR
#$01
DLAYO
WAIT 50 MS
LOA
STA
LOA
STA
#$FF
PBIO
#$00
PBIO
* PARALLEL DATA LOAD ONLY
* PULSE DATA LINES
** PARALLEL DATA LOAD ONLY
LOA
STA
LOA
JSR
LOA
JSR
LOA
JSR
#ALL
HOLD
#CC
CMND
SET DISPLAY CONTROLLER PARAMS
ADDRESS BOTH 10939'S
DIGIT COUNT = 20
#DT
DIGIT TIME = 32 CYC/CHAR
CMND
#DUT
CMND
DUTY CYCLE = 24/32
LOA
STA
LOA
JMP
#MRS
HOLD
#$OE
CMND
LOAD MASTER ONLY
START REFRESH CYCLE
(RETURN VIA CMND)
·THESE STEPS ACTIVATE
THE PARALLEL LOAD
MODE. OMIT THEM
ON SYSTEMS USING
SERIAL DATA LOAD
Flowchart: Display Controller Initialization
6-14
Application Note
10938/10939 Display Controller System
BLANK The Display
BLNK is a routine which fills the display buffers with blanks. By
preloading HOLD, DATA and KNTR, thel") entering the routine
at location OUTC, it can be used to display a string of constants.
BLANK DISPLAY
BLNK
BLN1
BLN11
BLN2
LDA
STA
LDA
JSR
LDA
STA
LDA
STA
BNE
#ALL
HOLD
#$CO
CMND
#$20
DATA
#$14
KNTR
OUTC1
ADDRESS BOTH 10939·S
SET BUFFER POINTER TO ZERO
ASCII BLANK
OUTPUT 20 DIGITS
OUTPUT A CONSTANT
ACC = DATA
KNTR = # DIGITS (MAX=20)
OUTC STA
OUTC1 JSR
DEC
BNE
RTS
DATA
OUTPUT
KNTR
OUTC1
SAVE DATA
SEND IT
Flowchart: Blank the Display
6-15
Application Note
10938/10939 Display Controller System
Load A Message
TOUTO loads the display with data from a table stored in RAM
or ROM. Locations PNTR and PNTR+1 contain the address of
the first byte of data to be fetched from the table. KNTR is preloaded with the number of characters to load. $FF is defined as
an end of table flag so the execution of the routine can be terminated either by the count down of KNTR or the detection of
the end of a table.
OUTPUT FROM TABLE
BUFFER POINTER MUST BE PRELOADED
WHEN USING ENTRY POINTS BEFORE
TOUT5
TOUTO
JSR
POINT
SET UP POINTER
TOUT
TOUT1
TOUT2
TOUT3
TOUT4
LDA
STA
LDA
STA
JSR
#MRS
HOLD
#$14
KNTR
oun
SELECT MASTER
TOUT5
LDA
EOR
STA
LDA
JSR
LDA
STA
JMP
#$03
HOLD
HOLD
#$CO
CMND
#$14
KNTR
OUn1
LDY
LDA
CMP
BEQ
JSR
INY
DEC
BNE
RTS
#$00
(PNTR),Y
#$FF
OUn2
OPUT
TOUT?
TOUTS
OUTT
OUTT1
OUTT2
KNTR
OUn1
20 CHARS MAX
SEND IT
SELECT THE OTHER 10939
BUFF PNTR = 0
20 CHARS MAX
SEND IT
INITIALIZE COUNTER
FETCH DATA
END OF TABLE?
YES
NO: SEND IT
POINT TO NEXT TBL LOCN
COUNT DONE?
NO
YES: EXIT
LOAD TABLE POINTER
X = OFFSET FOR POINTER TABLE
POINT
LDA
MESS, X
STA
PNTR
LDA
STA
RTS
MESS+1,X
PNTR+1
FETCH ADDRESS FROM
POINTER TABLE
TRANSFER TO POINTER
REGISTER
Flowchart: Display with Table Data
6-16
Application Note
10938110939 Display Controller System
Message Scroll
The next three subroutines are used for scrolling messages
across the display. SHFI clears the display then shifts in a message. SHFTO shifts a message across the display and ROTR
is a loop which repeatedly rotates a message through the display. These routines may be used separately or combined to
create various effects.
Scroll In A Message
SHFI blanks the display then shifts in a table message. The
embedded transfers to delay loops are used to control the
shifting speed.
CLEAR DISPLAY
SHIFT IN TABLE MESSAGE RIGHT TO LEFT
EXIT WHEN MSD MASTER HOLDS FIRST
CHARACTER OF TABLE
SHFI
POINT
BLNK
DELAY
SET UP TABLE POINTER
BLANK DISPLAY
WAIT
LDA
BNE
SHF1 LDA
SHF2 STA
#SLV
SHF2
#MRS
HOLD
START WITH SLAVE ONLY
LDA
STA
SHF3 STA
#01
KNT2
KNTR
START WITH ONE DIGIT
SAVE # OF DIGITS
JSR
JSR
JSR
SEC
LDA
SBC
ORA
JSR
SET BUFFER PNTR = 20 - #
DIGITS
#$14
KNT2
#$CO
CMND
LDA HOLD
CMP #MRS
BNE SHF4
JSR
JSR
LDA
STA
JMP
SHF4 JSR
JSR
SHF5 JSR
INC
LDA
CMP
BNE
LDA
CMP
BEQ
RTS
LOAD MASTER & SLAVE
HOLD DOUBLES AS A FLAG
TOUT4
SHFT2
#MRS
HOLD
SHF5
OUTPT TO MSTR & SLV
ADD A SPACE IF END OF TABLE
SET UP FOR NEXT PASS
oun
OUTPT TO SLAVE ONLY
ADD A SPACE IF END OF TABLE
WAIT
SHFT2
DELAY
KNT2
KNT2
#$15
SHF3
#SLV
HOLD
SHF1
ADD ANOTHER DIGIT
BUFFER LOADED: WHICH ONE?
SLAVE LDED, ADD MSTR
MSTR & SLV LOADED: EXIT
Flowchart: Display Clear and Message Shift In
6-17
Application Note
10938/10939 Display ControHer System
Scroll A Message Across the Display
SHFTO blanks the display, shifts in a table message then shifts
the message out of the display while simultaneously shifting in
blanks.
SHIFT TABLE MESSAGE ACROSS DISPLAY
'SHFTO JSR
SHFT02 JSR
JSR
BCC
RTS
SHFI
SHFTY
DELAY
SHFTOl
BLANK DISPLAY, SHIFT IN MESSAGE
SHIFT LEFT 1 DIGIT
WAIT
SHFT01
PNTR
SHFT02
PNTR+1
SHFT02
ADJ PNTR 4 NEXT SHIFT
INC
BNE
INC
BCC
DONE ON C=l
SHIFT TABLE MESSAGE LEFT ONE
DIGIT. OUTPUT A BLANK IF END
OF TABLE IS DETECTED.
SHFTY
SHFTY1
SHFTl
SHFT11
SHFT2
SHFTB
SHFT3
LDY
LDA
JSR
LDA
BEQ
CMP
CLC
BNE
SEC
BEQ
#00
#MRS
TOUT7
KNTR
SHFTl
#$14
INITIALIZE POINTER OFFSET
SELECT MASTER
OUTPUT MESSAGE
END OF TABLE?
NO
YES
SHFTB
SET C=l IF END OF TABLE
DETECTED AT MSD OF MASTER.
OUTPUT A BLANK
SHFTB
LDA #SLV
JSR TOUT7
CLC
LDA KNTR
BEQ SHFT3
STA
LDA
STA
LDA
JSR
RTS
TEMP
#01
KNTR
#$20
OUTC
SELECT SLAVE
OUTPUT MESSAGE
END OF TABLE?
NO: EXIT
YES: SVE XIT CNTR VALUE
FOR ROTR THEN
OUTPUT A BLANK
Flowchart: Shift Message Across Display
6-18
Application Note
10938/10939 Display Controller System
Flowchart: Shift Message Left One Position
6-19
Application Note
10938/10939 Display Controller System
Rotate A Message-Continuous Loop
ROTR rotates a message on the display.
ROTATE A TABLE MESSAGE-CONTINUOUS LOOP
MESSAGE MUST BE '" 20 CHARACTERS
ROTR
JSR
LDA
STA
LDA
STA
ROTR1
SHFI
PNTR
BPNT
PNTR+1
BPNT+1
LDA #00
SHIFT IN MESSAGE
SAVE TBL ADDRSS FOR WRAP
AROUND
TEMP IS CNTR VALUE 4 WRAP
AROUND
TEMP"IO=TBL END DETECTED
SHIFT LEFT ONE DIGIT
TBL END IN MSD DISP ?
NO: TABLE END DETECTED?
STA
JSR
BCS
LDA
CMP
BEQ
TEMP
SHF1Y
ROTR5
#pO
TEMP
ROTR25
LDA
PHA
LDA
PHA
LDA
STA
LDA
STA
DEC
BNE
LDA
CMP
BNE
JSR
JMP
PNTR
BPNT
PNTR
BPNT+1
PNTR+1
TEMP
ROTR10
#MRS
HOLD
ROTR20
SHFT1
ROTR20
FETCH 1ST BYTE PNTR
LDA
STA
LDA
STA
JMP
BPNT
PNTR
BPNT+1
PNTR+1
ROTR26
TBL END IN MSD DISP
RESET PNTR
ROTR10 LDA
STA
LDA
CMP
BNE
JSR
JMP
TEMP
KNTR
#MRS
HOLD
ROTR15
TOUT4
ROTR20
COUNT NOT DONE
RESET COUNTER
WHICH HALF?
ROTR15 JSR
oun
LOWER: FINISH LOWER
ROTR5
NO
YES
TABLE END: WRAP AROUND
SAVE TAIL POINTER ON STACK
PNTR+1
SHFTY ADDED BLNK: ADJ CNTR
COUNT DONE-WHICH HALF?
LOWER: SET UP 4 NEXT SHIFT
UPPER: DO LOWER
SET UP 4 NEXT SHIFT
RESTART:
REINITIALIZE
TABLE POINTER
DO NEXT SHIFT
UP: FINISH UP, DO LOW
ROTR20 PLA
STA PNTR+1
PLA
STA PNTR
RECLAIM TAIL POINTER
ROTR25 INC PNTR
BNE ROTR26
INC PNTR+1
INCREMENT TABLE
POINTER FOR
NEXT SHIFT
ROTR26 JSR DELAY
WAIT
[ADD EXIT SEQUENCE HERE]
JMP ROTR1
DO NEXT SHIFT
Flowchart: Rotate Message
6-20
Application Note
10938/10939 Display Controller System
For further product information, refer to the following documents:
Order Number
Document Title
096
10938 and 10930 Dot Matrix Display
Controller Data Sheet
060
R650011 EB Backpack Emulator Data Sheet
051
R650011 One-Chip Microcomputer Data Sheet
D51S
R650011 E Emulator Device Data Sheet
Supplement
212
R650011 One-Chip Microcomputer Product
Description
2175
Intelligent Display Controller
Designer's Notes
6-21
Application Note
'1'
Intelligent Display Controller
Designer's Notes
Rockwell
by Terry Christensen and Tal Klaus,
Semiconductor Products Division, Newport Beach, California
DESCRIPTION
control. Also available is the 10957 which is a 10937 modified to
provide greater decimal and tail control.
The Rockwell Intelligent Display Controller family of products is
designed to interface host processors to various types of vacuum
fluorescent displays. In addition to providing the display drive
signals, these products perform character decoding, grid timing
and display refresh functions. Included in the family are a series
of single chip display controllers, a series of anode decoder/drivers
and a grid controller/driver.
The block diagram of Figure 2 shows a typical host and display
interface for a single chip display controller.
Grid controller/drivers are combined with anode decoder/drivers
to create multi-chip display controllers. As shown in the block
diagram of Figure 3, the grid controller/driver (10939) accepts commands and data from the host system, sends data and timing information to the anode decoder/driver, and controls a cursor output
in addition to controlling the display grids. Commands for
brightness control, buffer control, and blank and inverse display
modes are available. These commands and the character data
may be input to the 10939 through either a serial or a parallel data
port. Each 10939 can drive up to 20 grids and store the related
character data for automatic refresh. With the synchronization
logic provided, as many as four 10939's can be daisy chained
together to drive 80 character displays as shown in Figure 4.
Figure 1 is a block diagram of the single chip display controller.
The products of this series contain 18 anode drivers and 16 grid
drivers. Commands and data are input through a serial data port.
A 64 x 16-bit mask programmable PLA provides character
decoding. A 16 x 8-bit data buffer holds character data. Commands for brightness control, data buffer control and test mode
enable are available.
Two PLA patterns are provided as standard products. One, the
10937 provides ASCII to 16 segment decoding. The other, the
10951 provides 7 segment numeric and 16 segment bargraph
decoding. Both of these products feature decimal paint and tail
The anode decoder/driver can drive up to 35 anodes. Data input
from the grid controllerldriver are decoded in a 128 character mask
DISPLAY
DATA
BUFFER
DECIMAL PT.
COMMA TAIL
SEGMENT
DRIVERS
POR
VSS
VDD
A
DIGIT DRIVERS
SGA
SGB
SGC
SGD
SGE
SGF
SGG
SGH
SGI
SGJ
SGK
SGL
SGM
SGN
SGO
SGP
PNT
TAIL
Figure 1. Single Chip Display Controller Block Diagram
Document No. 29651N78
Application Note
6-22
Order No. 2175
Rev. 2, June 1987
):10
"C
~
5·
@--~
ADl
AD2
AD3
AD4
ao·
VDD
~
,.
z
~
AD5t--------------.4-~+_------~~
AD6
AD7
,.
AD10
,.
AD12
AD13
......
,.
AD8t-------~~HHHH~-----4~
~
~~
ADllt-------~rt+++4~~+-------~~
AD14t---1rttti~~~~~~------~
~
AD15
AD16
~
HOST
SYSTEM
~. '~,.
, k'
I:
SINGLE CHIP
DISPLAY
CONTROLLER
I---
RESET
CIRCUIT
I---
POR
II 1
'-r>
;ss· .
I
)"
1,.
I
SGA
r-----------------I.i DATA
~--------------~~SCLK
>:,;~~,
-..
,.
"v
'/\
I',
><
1:>1
.
I
I
I'
~:
1
-
VOISP
I
SGB
~
SGD
......
SGG
-..
SGCt---~Hrrt~+++4~~~----~~
•
t----------+++++++++------.;J
SGJt:::::::::::~t+~~tti=::::~
SGL~--------~~HH~----~
t
+5 V
VSS
-10V -
VDD
~
SGH
SGI
SGMtl--------------~~+++_----~
I--.
VSS I' ~
~______~ ~
-l::
ce·
SGEt-----~rt+++414~~++----~~
SGF
~
SGKt
vcc
16 CHARACTER
16 SEGMENT
DISPLAY
SGN
r--------------.....I+++----~;J
SG0r-----------~~+_--~
SGP
-TAIL t-----------------.....:...~-----.....:;.J
L-_____P~N~Tt---------------~----~
CI)
ANODES
~
c
Cii·
"C
.f
oo
3-
a
CD
Figure 2: 16 Character 16 Segment Display Driven by Single-Chip Display Controller
ED
til
Intelligent Display Controllers
Application Note
ANODE DECODER DRIVER
t
INVERSION
LOGIC
128 x 35 PLA
P
~
P
8 BIT SHIFT
REGISTER
ANODE
DRIVERS
AND
LATCHES
f.35
SGXX
I--
VSS __
LEVEL
DETECT
+
VDD-VGG .....
f--
LEVEL
DETECT
DATA-LOAD
SCLK·DIS
GRID CONTROLLER DRIVER
DX
>
8
LDPOR-
CONTROL
LOGIC
::
~
GRID
DRIVERS
20 x 8
RAM
f20
STRXX
'-
VSS_
VDDVGG ......
-
&1- ,
I ,
MASTER
~
I
IL
§ iii
t
IL
5l
Figure 3. Multl·Chlp Display Controller Block Diagram
6·24
~CURSOR
Application Note
Intelligent Display Controllers
80 CHARACTER 5 x 12 DOT MATRIX DISPLAY
ANODES
~V
23
./
CURSOR
SLAVE
10939
V
20 1-- 20
./ ./
DATA-LOAD
SCLK-DIS
GRIDS
20 ~20
./
./
V
STRXX
CURSOR --"
~
LD
CLOCK
OX
r - - - SOP
SIP
r--
POR
I-
MASTERiJ.
VSS
SGXX
SLAVE
10939
' - SOP
10943
STRXX
SCLK-DIS
DATA-LOAD CURSOR
LD
SCLKDIS
DATALOAD
CLOCK
~
OX
~ SIP
POR
MASTER
11
HOST
VSS
SCLKDIS
DATA
LOAD
'--- SOP
SLAVE
10939
\
STRXX
SCLK-DIS
DATA-LOAD CURSOR
LD
OX
SGXX I-CLOCK
10942
2~R8
rI"
POR
SIP
MASTER
0
I--
VSS
'--- SOP
MASTER
10939
~ SIP
STRXX
CURSOR .J-LD
OX
CLOCK
~
SCLK-DIS
POR
DATA-LOAD
~
MASTER I4-VDD
;>
~
VGG
Figure 4. Block Diagram of 80 Character 5 x 12 Dot Matrix
Display Driven by Multi-Chip Display Controller
6-25
Application Note
Intelligent Display Controllers
Rockwell's intelligent display controller approach are: reduction
of operating time required of the host computer, less display
overhead electronics, simplified system design, less board real
estate for the display control function, reduced power and cooling, lower overall installed cost and lower maintenance costs.
programmable PLA to determine which anodes to activate.
Several anode drivers may be driven as shown in Figure 4 to produce characters from more than 35 anodes.
Four PLA patterns are produced as standard products. The 10938
provides ASCII to 5 x 7 dot matrix decoding. The 10941 generates
16 segment ASCII and bargraph patterns. The 10942 and 10943
are used together to generate 5 x 12 dot matrix ASCII characters.
This can be seen from the following comparison. Several techniques can be used to drive a 20 character, 5 x 7 dot matrix,
vacuum fluorescent display. One way is to use two IO-bit shift
register latched drivers to drive the grids and five 8-bit latched
drivers to drive the anodes as shown in Figure 5. This configuration uses 19 outputs from the host system for display control. The
host system must perform the grid timing and character to dot conversion. Because of this, the host system must service the display
every character cycle.
Tables 1 and 2 compare the features of the display controller
products.
Typical applications for the intelligent display controller family
include: automotive instrument clusters, interactive terminals,
typewriters, telecommunications products, industrial automation,
appliances, hand-held computers and instrumentation systems.
An efficient alternate method is to use the 10938/10939 chip set
as shown in Figure 6. With this configuration, 4 or 10 outputs from
the host system and a Simple reset circuit are needed to drive the
display controller. At initialization, the host loads operating
parameters into the display controller. Then the display buffer is
loaded with the ASCII code of the characters to be displayed. After
that the host accesses the display controller only when display
characters or operating parameters need to be changed. The
display controller performs the grid timing and ASCII to dot conversion functions.
Although intended for vacuum fluorescent displays, users are finding these intelligent controllers are cost effective for use with gas
discharge, LED and incandescent displays even though buffering is required.
By providing a simple interface both with the host computer and
the associated display, the Intelligent controller family provides
significant advantages over other approaches. The benefits of
Table 1. Comparison of Single Chip Display Controller Features
Features
10937
10957
10951
PLASlze
64
64
64
Font
16 Segment Alphanumeric
Decimal Point
Comma
7 Segment Numeric
Decimal Point
Comma
16 Segment Bargraph
16 Segment Alphanumeric
Decimal Point
Comma
Open-Drain
Open-Drain
Open-Drain
18
10
18
10
18
10
Open-Drain
Open-Drain
Open-Drain
16
20
16
20
16
20
Host Interface
Serial
Serial
Serial
Control Options
Duty Cycle
Character Count
Buffer Pointer
Test Mode
Duty Cycle
Character Count
Buffer Pointer
Test Mode
Duty Cycle
Character Count
Buffer Pointer
Test Mode
Anode Drivers
Type
Number
Current Limit (mA)
Grid Drivers
Type
Number
Current Limit (mA)
Power Supply Limits
VDD(V)
VGG(V)
-15±1.5
-15±1.5
-15±1.5
to -50
to -50
to -50
Package
40 Pin Dip
40 Pin Dip
40 Pin Dip
Other
2 Decimal and Tail Commands
2 Decimal and Tail Commands
4 Decimal and Tail Commands
6-26
Application Note
Intelligent Display Controllers
Table 2.
Features
Comparison of Multi·Chip Display Controller Features
Grid Drivers
Anode Drivers
10939
10941
10938
10942
10943
PLA Size
128
128
128
128
Font
5 x 7 Dot Matrix
Alphanumeric
16 Segment
Alphanumeric and
Bargraph
Top Half
5 X 12 Dot Matrix
Alphanumeric
Bottom Half
5 x 12 Dot Matrix
Alphanumeric
Push·Pull
35
2
Push·Pull
18
2
Push·Pull
23
2
Push·Pull
23
2
Via 10939
Via 10939
Via 10939
Via 10939
Grid Drivers
Type
Number
Current Limit (rnA)
Push·Pull
20
10
Anode Drivers
Type
Number
Current Limit (rnA)
Host Interface
Serial or Parallel
Control Options
Digit Time
Duty Cycle
Character Count
Buffer Pointer
Blank Mode
Inverse Mode
Start Refresh
Power Supply Limits
VDD(V)
VGG(V)
-20±2.0
to -50
-20±2.0
to -50
-20±2.0
to -50
-20±2.0
to -50
-20±2.0
to -50
Package
40 Pin Dip
40 Pin Dip
24 Pin Dip
28 Pin Dip
28 Pin Dip
Other
Cursor Driver
Cascadable
Decimal Point Driver
Comma Driver
6·27
,
10 BIT
SHIFT REGISTER
LATCH DRIVER
I
BLANK
10"
1~
,
LATCH STROBE
SERIAL CLOCK
--
GRIDS
GRIDS
SERIAL DATA
l+
8 BIT
LATCHED DRIVER
SERIAL DATA
~ SERIAL CLOCK
20 CHARACTER
5 x 7 DOT MATRIX
VACUUM
FLUORESCENT
DISPLAY
f--
~
"C
"C
~
0"
~
Z
~
ENABLE
LATCH STROBE
BLANK
HOST
SYSTEM
8 BIT
LATCHED DRIVER
10 BIT
SHIFT REGISTER
LATCH DRIVER
~
-~
STROBE
r-
DATA
ENABLE
~
ANODES
7L
,
ANODES
STROBE
~ DATA
8L
8 BIT
LATCHED DRIVER
DATA
ENABLE
~ DATA
STROBE
8 BIT
LATCHED DRIVER
8 BIT
LATCHED DRIVER
ENABLE
Figure 5.
ANODES
~
10"
CD
ANODES
~
c
STROBE
ENABLE
W+
7
L..., DATA
~
STROBE
20 Character 5 x 7 Dot Matrix Display Driven by Latched Drivers
~
r-
ANODES
CURSOR
iir
"C
of
oo
a
2CD
Ul
Application Note
Intelligent Display Controllers
10938
SGXX
~ 35
\
--
ANODES
DATA-LOAD SCLK-DIS
20 CHARACTER
5 x 7 DOT MATRIX
VACUUM
FLUORESCENT
DISPLAY
HOST
SYSTI'M
DATA-LOAD SCLK-DIS
J
RESET
I
I CIRCUIT I
POR
~20R8
\
LD
STRXX
OX
CURSOR
~20
\
.....
~
GRIDS
CURSOR
10939
Figure 6.
20 Character 5
x 7 Dot Matrix Display Driven by Multi-Chip Display Controller
HOST-DISPLAY CONTROLLER INTERFACE
The single chip display controller recognizes four types of commands which are summarized in Table 3. The Buffer Pointer
Control command sets the display data buffer pointer to the
desired digit position. This enables easy modification of any
individual character. When the command is executed, the buffer
pointer is loaded with two less than the value of the controlling
strobe line. Thus, to set the buffer pointer to the anode data for
the character controlled by ADS, the command A6'6 is sent to
the display controller.
These devices contain circuitry to protect the inputs against
damage due to high static voltages. However, it is advised that
normal precautions be taken to avoid application of any voltage
beyond the maximum rated limits. All inputs are TTL compatible
although pullup (to VSS) resistors may be required in certain
applications.
CONTROL OF SINGLE CHIP DISPLAY CONTROLLERS
Commands and display data are clocked into the single chip
display controller from the host serially with the DATA and SCLK
inputs. Input data is shifted in as serial bytes, MSB first. Each bit
is latched in on the falling edge of the SCLK pulse. The SCLK .
signal must remain high from one to 20 itS and low at least one /Ls
for each bit. There must be a 40 itS gap, with SCLK held low,
between each byte. It is recommended that the display controller
be reset periodically to assure bit synchronization. Figure 7 contains a summary of the data transfer timing requirements and a
flow chart of the data transfer procedure.
The Digit Counter Control command sets the number of strobe
lines to be activated on the display controller. It is normally used
during initialization to define the number of characters to be controlled. In some cases it may also be used to adjust display
brightness. This is discussed in the section describing display
control techniques. The four least significant bits of the command
byte determine the number of strobes to be activated. A command
code of CO'6 enables all 16 strobes. Otherwise, the number in
the lower half of the command is the number of active digits.
The MSB of the input byte is called the control bit. The state of
this bit determines the function of the input data. If the control
bit is a one, the input data is a command or control word. If the
control bit is a zero, the input byte is display data.
Display brightness and display onloff are controlled by the Duty
Cycle Control command. The internal clock of the display
controller runs at 100 KHz ± 50%. 32 clock cycles are allotted
each active strobe. One of these 32 cycles is an inter-digit off time.
6-29
Intelligent Display Controllers
Application Note
DATA
DATA
SERIAL CLOCK
SCLK
OUTPUT NEXT DATA
BIT' (TRANSFER
DATA MSB FIRST)
RESET
~
2N2907
POR
~ 33K
VDD
HOST
1.0 ~S
1.0pS
200 ns
100 ns
40 pS
120 ~S
:S TON:S
10937
10957
OR
10951
20.0
:S TOFF
:S
TbOFF
:S T.oFF
:S
:S
T GAP
T BYTE
SCLK
DATA
"DATA MUST BE STABLE DURING THIS TIME
Figure 7.
Data Transfer to Single-Chip Display Controller
The Duty Cycle Control command is used to select the number
of the remaining 31 clock cycles a strobe is on. The number of
"on" cycles is the five least significant bits of the command byte.
command or display data on the data lines, then pulsing the LD
line. The load cycle time must be at least 60 !'5 with the LD line
set high for at least one p,s and held low for at least 40 p,s.
The fourth command type is a Test Mode Enable. When this mode
is activated, the digit time is reduced from 32 to 4 clock cycles.
After the test mode has been entered, a power-on reset sequence
must be performed to resume normal operation.
The serial data input mode is implemented during the power-on
reset procedure. In those systems using serial mode, ports D2-07
should be tied low to prevent the inadvertent implementation of
the parallelload·mode. Serial data bytes are shifted into a data
buffer MSB first on line DO using line D1 as the serial clock. The
last eight bits clocked in are latched into the display controller
by a pulse on the LD line. As shown in Figure 9, the cycle time
for each data bit is 2 p,s and the load time for each byte is 60 p,s.
CONTROL OF MULTI-CHIP DISPLAY CONTROLLERS
In systems using the multi-chip display controller, commands and
display data are sent from the host to the 10939(s) through the .
data (DO-D7) and LD lines. Either a parallel or a serial data input
mode may be used.
The 10939's may be cascaded together to drive displays having
more than 20 characters. As many as four 10939's can be daisy
chained as shown in Figures 4 and 14 to control up to 80
characters.
The parallel data inpul mode is implemented by toggling any of
data lines D2-D7 after paR has gone low. Once the parallel data
load mode has been implemented, a power-on reset procedure
must be performed to return to serial data load mode. Parallel data
transfer is accomplished, as shown in Figure 8, by pUlling the
Each 10939 has its own on-chip oscillator and a clock generator
operating at approximately 100 kHz. When more than one 10939
is used in a system, the same clock must be used for all the
6-30
Intelligent Display Controllers
Application Note
Table 3.
Single Chip Command Summary
Control Word Assignment
Hex Code
Digit Counter Control Codes
Function
80·9F
AO-AF
CO·CF
EO·FF
Enter Test Mode
Load Buffer Pointer
Load Digit Counter
Load Duty Cycle
Duty Cycle Control Codes
Hex Code
On Cycles
Oil Cycles
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Hex Code
Hex Digit
Counter Value
Number of
Digits Controlled
CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
16
1
2
3
4
S
6
7
8
9
10
11
12
13
14
15
Buller Pointer Control Codes
Hex Code
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
devices. To do this, one 10939 is designated the master by connecting its MASTER pin to VDD. This activates the oscillator on
that device and causes a three-level four-state signal to be output on the CLOCK pin. The MASTER pin on the remaining, I.e.,
slave, devices is connected to VSS. This deactivates the oscillators
on these devices so that the master's CLOCK output can be input
on the slaves' CLOCK pins.
Pointer Value
0
1
2
3
4
S
6
7
a
9
10
11
12
13
14
15
Character Controlled By
AD2
AD3
AD4
ADS
AD6
AD7
ADa
AD9
AD10
AD11
AD12
AD13
AD14
AD1S
AD16
AD1
10939 receives this pulse on its SIP input and starts its display
cycle. This sequence continues through all of the 10939's in a
chain. The SOP of the last 10939 is connected back to the SIP
of the first 10939 to start another cycle. The limit to the number
of 10939's in the chain is determined by: 1) the load on the clock
output of the master 10939, and 2) the display refresh requirements. The synchronization signal propagates during the last
character time of its own 10939 and thus does not require any extra
time before the first character of the next 10939. The duty cycles
of all the 10939's in the chain must be the same.
A two line synchronization port (SOP and SIP) ensures that only
one 10939 device at a time drives the display. When one 10939
outputs its last character, it emits a pulse on its SOP. The next
6-31
Intelligent Display Controllers
Application Note
LOAD
LD
B I
DATA
RESET
Do-D7
~:
2N2907
POR
133K
~
VDD
10939
HOST
PARALLEL INTERFACE TIMING WAVEFORMS
1---TLDC'tC
----t.1
40,.sEC·
1 ,.sEC
T LDOFF
T LDON
o .s TLDSETUP
1 ,.sEC s T LDHOLD
60,.sEC· S TLDCYC
S
s
·FOR INDUSTRIAL RATED PARTS SUBSTITUTE 44.5 FOR 40
66.7 FOR 60
Figure 8.
Parallel Data Transfer to 10939
6-32
Intelligent Display Controllers
Application Note
LOAD
t--------I
LD
SERIAL CLOCK 1 - - - - - - - - 1 01
DATA I------_~ DO
OUTPUT NEXT
DATA BIT
(BEGIN WITH
MSB)
02-07
HOST
VSS
VDD
10939
RESET
t----.lPOR
33K
VDD
~TSSCyC__,
r-
~ERIAL CLOCK) ~
TS C O N + T SCOF~
11----,
i
I'" T
I
i-TLS+j
SL+ TLOON1+"- T LOOFF---.J
________________~i__~ ___ ~
LD
i
DO
(DATA)
I---- T
________X,..---T-~
2!,SEC
l!,SEC
l!,SEC
l!,SEC
l!,SEC
l!,SEC
40!,SEC"
60!,SEC"
l!,SEC
l!,SEC
LOeve
====
•
I
::::;T SCCYC
S TSCON S 20 !,SEC
:::;T SCOFF
::::;T SSETUP
:sT SHOlD
:5:T LDON
:$TLDOFF
:5TLDCYC
:5T Ls
:5TSL
"FOR INDUSTRIAL RATED PARTS SUBSTITUTE
44.5 FOR 40
66.7 FOR 60
Figure 9.
Serial Data Transfer to 10939
6-33
Application Note
Intelligent Display Controllers
The data pattern 01 16 is a control prefix byte. When this byte is
transmitted to a 10939, it indicates that the next byte is a command. Several command types, listed in Table 4 are recognized
by the 10939.
The SCLK-DIS signal is composed of the shift clock which shifts
new data into the anode decoder/driver and a disable signal which
sets all of the anode drivers to the display off state. The DATALOAD signal is composed of serial 8-bit data and a load signal
to transfer the new data from the 10938 input buffer through the
PLA to the display driver outputs. The data is output with the most
significant bit first.
One of these, the Digit Time Select, determines the amount of time
allotted to each character during the refresh cycle. Three options
are available. These are 16, 32 or 64 half clock cycles per
character. A clock cycle is one cycle of the internal clock of the
master 10939 of the system.
The anode decoder/driver devices can drive a maximum of 35
anodes. For displays having more than 35 anodes per character,
such as the 5x12 dot matrix example of Figure 4, two or more
anode decoder/drivers may be connected in parallel.
The Duty Cycle Select is another command type. This determines
the number of clock cycles a digit driver is on during its character
time. Three half clock cycles of each character time are used as
an inter-digit off time so the selectable duty cycle range is zero
to digit time minus three.
POWER·ON RESET AND INITIALIZATION
The power-on reset (PaR) input controls the initialization of the
internal circuits of the display controllers. Chip reset is achieved
by setting the paR input high (VSS), waiting a minimum of 100 pS
then setting the paR input low. After another delay of at least
1001's, commands and data may be sent to the display controllers.
On a cold start, paR should be held high for at least 100 I's after
VDD stabilizes. Figure 11 contains examples of circuits that can
be used to control this input while Figure 12 contains cold start
timing diagrams.
A third command type is the Digit Count Select. This determines
the number of character positions to be controlled. Note that a
digit count greater than the actual number of characters can be
selected. This is a feature that can be use.d to extend the display
cycle time and thus expand the range of brightness control since
adding phantom characters causes a proportionate reduction of
display brightness.
The 10939 contains a 20 character data buffer which holds the
anode data for each digit. A buffer pointer, which can be set on
command, allows direct access to the data for each character.
A power-on reset establishes the following default conditions on
the single chip display controllers:
a. The grid drivers (ADXX) are off (floating).
b. The anode drivers (SGX, PNT, TAIL) are off (floating).
c. Duty cycle is set to zero.
d. Digit Count is set to 16.
e. The buffer pointer selects the character controlled by AD1.
f. The display data buffer is filled with zeros.
The multi-chip display controllers may be operated in three command selectable display modes. These are the normal, inverse
and blank modes. When the inverse mode is enabled, selected
characters will be inverted. The anodes that would be enabled in
normal mode are disabled and the anodes that would be disabled
in normal mode are enabled. When the blank mode is enabled,
selected characters will be blanked.
When performing chip initialization it is recommended that a
sequence such as that of Figure 13 be followed. In this sequence,
the digit count is adjusted and the display data buffer is loaded
before the duty cycle is set. This prevents the flashing of random
data on the display.
The MSB of the data byte is a control bit which determines which
characters are selected for a particular display mode. Characters
for which this bit is a zero will be displayed in the normal mode.
A power-on reset establishes the following default conditions on
the multi-chip display controller.
a. The Grid Drivers (STRXX) are off.
b. Duty Cycle is set to zero.
c. Digit Count is set to 32.
d. The Buffer Pointer is set to zero.
e. Digit Time is set to 64 cycles per character.
f. Normal display mode is selected.
g. The DATA-LOAD output is set to the high impedance state.
h. SCLK-DIS is set to Vol to disable the anode drivers.
When the paR signal is removed, SCLK-DIS is set to the high
impedance state.
i. SOP is set to Vol to disable the synchronization pulse.
j. The 10939(s) is (are) placed in an internal halt mode. This
allows the host system to load the control registers and the data
buffer without flashing "garbage" on the display. The normal
display refresh sequence is started upon receipt of a START
REFRESH control code. Only the master 10939 in a multi-chip
system will recognize the START REFRESH code. The slave(s)
will be started by the master at the appropriate time, using the
SOP signal.
The data byte control bit also controls the cursor output. The cursor output will be enabled on all characters with the MSB equal
to one. So when normal mode is enabled and the MSB of the data
byte is set, the normal character will be displayed with the cursor
on. When blank mode is enabled and the MSB equals one, the
character will be blanked and the cursor will be on.
Two commands remain. One is the Start Refresh Command. At
power on, 10939s are placed in an internal halt mode. The normal display refresh sequence starts when a master 10939 receives
this start refresh command.
The final command is the command to load 01 16 into the data buffer. This byte signifies that a command follows. When the command is also 01 16, it means that 01 16 is data.
Display data and timing (Figure 10) are output to the anode
decoder/driver via a two line serial port consisting of the SCLK-DIS
and DATA-LOAD PINS. In order to minimize the number of package
pins, these outputs are multiplexed, three-level, four-state drivers.
6-34
Application Note
Intelligent Display Controllers
Table 4.
Multi-Chip Command Summary
Control Word Assignments
Digit Counter Control Codes
Hex Code
Function
Hex Code
Digit Counter value
No. of Grids Controlled
01
05
06
07
08
Load 01 into Data Buffer
Set digit time to 16 cycles per grid
Set digit time to 32 cycles per grid
Set digit time to 64 cycles per grid
Enable Normal Display Mode (MSB in data words
is ignored)
Enable Blank Mode (data words with MSB = 1 will
be blanked)
Enable Inverse Mode (data words with MSB = 1
will be "inversed")
Start Display Refresh Cycle (use only once after
reset)
Load Duty Cycle Register with lower 6 bits (0-63)
Load Digit Counter (80 = 32. 81 = 1. 82 = 2. etc.)
Load Buffer Pointer Register with lower 5 bits
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
80
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
90
9E
9F
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
lA
lB
lC
10
lE
lF
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
09
OA
OE
40-7F
80-9F
CO-OF
Duty Cycle Control Codes
Hex
Code
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
4F
50
51
50
5E
SF
60
61
7C
70
7E
7F
Digit Time
On
=
16 Digit Time
5
4
3
3
"
"
"
27
28
29
30
31
37
36
35
"
27
28
29
29
."
"
"
"
"
"
"
"
"
"
"
58
59
60
61
6
5
4
3
··
"
"
"
"
"
"
··"
·
= 64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
10
11
12
13
13
·
Digit Time
On
On
-
= 32
Off
32
32
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Off
16
16
16
15
14
13
12
11
10
9
8
7
6
5
4
3
3
.
-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Off
64
64
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Buffer Pointer Control Codes
34
33
6-35
Hex Code
Pointer value
Character Controlled By
CO
Cl
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
DO
01
02
03
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
STROO
STROl
STR02
STR03
STR04
STR05
STR06
STR07
STR08
STR09
STR10
STR11
STR12
STR13
STR14
STR15
STR16
STR17
STR18
STR19
»
"C
'2.
(;'
a0'
~
_ _~ 1
2
y
SCLK·DIS
3
U
4
lIj
U
5
z
r-u
6
7
U
8r-_ _ _ _ _ _-.
U
LJ
Vih I
sa.
ICD
Vim
VII
,
I
I
,
DATA-LOAD
-Y..
DATA= O:NORMAL
DATA= 1:INVERSE
~
CJ)
=j
STRXX
X
X
- ,
U
;C
I
),(
I
X
X
I
I
x:J
9
!
Vih
Vim
LSBDATA
MSBDATA
VII
--------~~
V
I
Voh
Vol
CURSOR
~
SHIFT PULSES ARE MARKED 1 THROUGH 8. DATA IS LATCHED ON THE POSITIVE TRANSITION OF SCLK·DIS.
IF THE DATA INPUT DURING CLOCK PULSE 1 IS A LOGIC 1, THE SEGMENT OUTPUTS ARE COMPLEMENTED
TO PROVIDE AN INVERSE CHARACTER. THE MOST SIGNIFICANT BIT OF THE CHARACTER CODE IS INPUT
DURING CLOCK PULSE.:! AND THE LEAST SIGNIFICANT BIT DURING CLOCK PULSE 8.
THE DRIVERS ARE DISABLED AFTER THE NEGATIVE TRANSITION (Vlh to VII) OF THE DISABLE PULSE (CLOCK
PULSE 5 IN THE EXAMPLE). THE DRIVERS CHANGE TO THEIR NEW VALUES AFTER THE POSITVE TRANSITION
OF THE LOAD P.ULSE (MARKED 9).
CD
cS'
CD
~
c
0'
"C
i
rl
a
a
CD
Figure 10. Data Transfer from Grid Driver to Anode Driver
Ul
Intelligent Display Controllers
Application Note
VSS
rl
VSS
ELECTRONIC OR MANUAL
I
INITIALIZATION SWITCH - - - ,
10 KO
0.47 pF
'--.......-.---1..
TTL LEVEL
INPUT
POR
e--_MII'----r
2N2907
POR
180 KO
CHIP IS RESET WHEN
TTL INPUT IS LOW
CHIP IS RESET WHEN
SWITCH IS CLOSED
VDD
33 KO
VDD
Figure 11. Power On/Reset Control Circuits
SINGLE CHIP
DISPLAY CONTROLLER
MULTI CHIP
DISPLAY CONTROLLER
_____
I~
1VSS
t
POR
VDD~
1\__
~31
1-/
~---
T
VDD
...L
~--1---1-1
VSST
POR
VDD~
~--
1 - POR STAYS HIGH A MINIMUM OF 100 ,.s AFTER VDD
BECOMES STABLE
2 - WAIT A MINIMUM OF 100 ,.s AFTER POR IS STABLE
BEFORE SENDING DATA TO THE DISPLAY
CONTROLLER
3 - KEEP VGG MORE POSITIVE THAN VDD UNTIL
VDD
VSS - 10V
=
Figure 12. Power On/Reset Timing
6·37
Intelligent Display Controllers
Application Note
(SYSTEMS USING
PARALLEL DATA
LOAD ONLY)
PULSE THE
DATA LINES
Figure 13.
Single Chip Display Controller Initialization
START REFRESH
CYCLE ON
MASTER 10939
Figure 14 is an example of an initialization sequence for the multi·
chip display controller. In systems using parallel data loading, one
or more' of data lines D2 through D7 should be toggled before
sending data to the 10939. Digit time should be set before the duty
cycle is selected. To prevent the flashing of random data on the
display,1he display data buffer should be loaded before the start
refresh cycle command is given.
Figure 14.
6-38
MUlti-Chip Display Controller Initialization
Intelligent Display Controllers
Application Note
Each segment driver can source up to 10 rnA and each digit driver
can source up to 20 rnA. Operating the chips beyond these limits
can reduce chip life time. Both 40 and 50 volt versions of the single
chip display controller are available as standard products.
CONTROLLER DISPLAY INTERFACE
DISPLAY INTERFACE OF SINGLE CHIP
DISPLAY CONTROLLER
The single chip display controllers can drive up to 16 digits and
18 segments. These are open drain drivers so external pull down
resistors must be supplied. The total capacitance on an output
and the display duty cycle determine the resistor values to use.
To prevent ghosting, the RC time constant of an output must be
less than the interdigit off time. However, the resistor value should
be as large as possible to maximize the portion of the driver current going to the display. Thus R :sToff/C.ff, where Toff is the interdigit off time and C.ff is the total capacitance on the driver. For
VF displays, this value is usually between 30 kll and 50.kll.
Table 5.
..
s
c
:;
a.
.5
00
01
02
03
04
05
06
fJl
~
.
I!
J:
0
..
s
c
:;
a.
.5
~
.
I!
~
c
:;
ti
I!
.5
~
a.
J:
0
I 08 I- - I 10
I-I- I I I
I I
I
1--1 09 I 11
--
.
Su
I!
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20
21
16 Segment PLA Patterns
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29
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--
.
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c
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Bit 7 of the data byte is a don't care
Table input data is for bit 7 equal to zero
6-39
32
33
34
35
36
I
I
39
- - I 3A
I- - I
I
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I
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3B
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I- -
10937 Driver Assignments
I
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Two PLA patterns are offered as standard products. One of them,
part number 10937, displays 16 segment upper case ASCII
characters plus decimal and tail. It can also be used for
14 segment ASCII and 7 segment numeric displays. The 14 and
16 segment driver assignments and character patterns are listed
in Tables 5 and 6. Part number 10951 generates 7 segment
numeric and 16 segment bargraph codes. Tables 7 and 8 contain
the segment assignments and patterns generated by this device.
I 3F
I
--
\
\
-
I
I
Intelligent Display Controllers
Application Note
Table 6.
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Bil 7 of the data byte is a don't care
Table input data is for bit 7 equal to zero
6·40
(SGK)
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(
/
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-
10937 Driver Assignments
35
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TAIL
Application Note
Intelligent Display Controllers
Table 7.
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c
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30
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25
26
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c
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33
1=1
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Bit 7 of the data byte is a don't care
Table input data is for bit 7 equal to zero
,2
34
;
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I
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-
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.
,
3C
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,
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00
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3F
,,
10951 Driver Assignments
1
2
1
-
,
,-
2
'Segment drivers SGH. SGI, SGJ, SGK, SGL are enabled when these codes are used.
2Segment drivers SGM, SGN, SGO, SGP are enabled when these codes are used.
6·41
Application Note
Intelligent Display Controllers
Table 8. 16 Segment Bargraph Patterns
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17
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Bit 7 of the data by1e is a don't care
Table input data is for bit 7 equal to zero
6-42
10951 Driver Assignments
Intelligent Display Controllers
Application Note
In addition to the grid drivers, each 10939 contains a cursor output to drive the cursor segment present on some displays. This
output is activated when the MSB of the data byte for a particular
digit is a one.
A modified version of the 10937, part number 10957, offers
expanded decimal and comma control. To provide this, two of the
10937 data codes have been redefined. Table 9 lists the unique
10957 codes and compares the 10957 with the 10937.
The single chip display controllers were not designed for paralleled or cascaded operation. The mUlti-chip display controller
should be used for displays having more than 16 digits or more
than 18 segments per character.
Table 9.
USE OF EXTERNAL DRIVERS WITH INTELLIGENT
DISPLAY CONTROLLERS
If external drivers are added, the devices of the Intelligent Display
Controller product line can be used to control displays which
operate beyond the range of the display controllers' internal
drivers. This applies to LED, Gas Discharge and certain VF
displays.
Comparison of 10957 with 10937
Input
Data
10937
Character
10957
Character
2C
,
,
,
,
An example of this is shown in Figure 16. Here the 10941/10939
chip set is used to control a 16 segment LED display. The display
consists of two Hewlett Packard HDSP-6508s. These are
16 segment GaAsP red LEOs. They are common cathode configured and mounted in an 8-character package. The 10939 strobe
outputs are connected to 600 rnA inverting drivers which control
the cathodes. The 10941 segment outputs are connected to
500 rnA sourcing drivers which control the anodes. A 470 current
limiting resistor is also supplied to each anode.
2E
6C
6E
DISPLAY INTERFACE OF MULTI-CHIP
DISPLAY CONTROLLERS
DISPLAY CONTROL TECHNIQUES
Multi-chip display controllers are constructed from various combinations of anode decoder/drivers and grid controller/drivers.
DIGIT STROBING
The display controller strobe lines are activated sequentially starting with STROO (AD1 on single chip controllers) and ending with
the highest strobe enabled by the character count select commands. After the last strobe in the chain has completed its cycle,
the process repeats. The strobe drivers may be connected to
strobe a display from right to left, or from left to right, depending
on the system requirements. In most cases this will be determined
by board layout or software constraints.
The anode decoder/drivers can each drive a maximum of 35 dots
or segments. Each driver can carry a 2 rnA load and no external
pull downs are required. The devices may be driven in parallel to
generate patterns of more than 35 dots. An example of this is the
5 x12 dot matrix block diagram of Figure 4.
Display data codes and timing information are sent from a 10939
or other source to the anode decoder/drivers serially on the DATALOAD and SCLK-DIS lines. An on-board 128 character PLA
decodes the data bytes to determine which drivers to enable.
Standard PLA patterns are available for three character fonts. The
10938, listed in Table 10, generates 5 x 7 dot matrix patterns. The
10941, listed in Tables 11 and 12, generates 16 segment and bargraph patterns. It also features separate decimal and comma
drivers. This PLA may also be used for 14 segment and 7 segment
displays. The 10942 and 10943 are combined to produce the
5 x 12 dot matrix patterns shown in Table 13.
BRIGHTNESS CONTROL
In certain applications, particularly in situations where the environmentallight level varies, the display brightness must be varied
from time to time. This can be done by varying the duty cycle and
by adding and deleting fictitious digits.
For example, suppose a 10937 is used to control a 7-digit alphanumeric display. Assume that the maximum progammable duty
cycle, i.e. each strobe ON 31 clock cycles, is used when ambient
light levels are high. Then the display brightness can be
decreased by decreasing the duty cycle. Display dimming from
maximum to minimum brightness will be achieved in 31 steps with
a 3.22 percent decrease from full brightness at each step.
Each grid controller/driver, i.e. 10939, can drive 20 digits and a cursor. These are push-pull drivers which can source 10 rnA each.
The 10939s may be cascaded, as shown in Figure 4, to drive
displays of more than 20 characters. They may be connected in
parallel, as shown in Figure 15, to drive mUlti-line displays having shared grids. In this configuration, the grid drivers may be
wired ORed if additional grid current is required. However, when
this is done, diodes and pull down resistors must be used as they
are used with the cursor outputs. Alternatively, external drivers
may be added. The total number of 10939s that may be connected
together is limited by the duty cycle requirements of the display
and the load on the master 10939 clock output. Typically, this limit
is four 10939s but more may be added if the clock output load is
kept below 50 pF.
At lower light levels it may be desirable to decrease the display
brightness in smaller steps. This can be done by using fictitious
digits. In this example, after the display has been dimmed to
approximately 20 percent of full brightness, i.e. duty cycle value
as been decreased from 31 to 7, the character count is increased
from 7 to 16. At the same time, the duty cycle number is changed
from 7 to 14. Display dimming then proceeds by successively
reducing the duty cycle. However, now the brightness is reduced
about 1.4 percent with each step.
6-43
Intelligent Display Controllers
Application Note
Table 10. 5 x 7 Dot Matrix PLA Patterns
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20
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38 •••••
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5B
60
68
70
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50
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51
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62 ;:::. 63
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71
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30:
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10938 Driver Assignments
Application Note
Intelligent Display Controllers
Table 11. 16 Segment PLA Patterns
CD
10
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--
10941 Driver Assignments
Application Note
Intelligent Display Controllers
Table 12.
.
1;
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CJ
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60
61
62
63
64
65
66
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68
69
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6B
6e
60
6E
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( 8G09 )
( 8G08 )
( 8G07 )
71
70
73
72
78
7A
79
-
-
74
-
-
7C
7B
-
75
-
76
-
70
-
77
7E
-
-
( 8G05 )
( 8G04 )
7F
-
( 8G06 )
-
( 8G03 )
( 8G02 )
~
10941 Driver Assignments
6-46
Application Note
Intelligent Display Controllers
Table 13.
~
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D.
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00
08
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10
01
02
09
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12
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03
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5 x 12 Dot Matrix PLA Patterns
05.
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15
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13
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16
07
OF
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17
Segments Driven 8y 10942
19
lA
18
lC
lD
IE
21
22
23
24
25
26
••••
27
29
2A
28
2C.
2D
2E
••
2F
•
31
32
33
34
35
36
•••
37
....
39
3A
38
3C
3D
3E .'
3F
40
41
42
43
44
45
46
47
48
49
4A
48
4C •••••
4D
4E
50
51
52
53
54
55
56
58
59
5A
58
5C
• 5D
5E
60
61
62
63
64'
• 65
66
67
68
69
SA
68
6C
6D
6E
6F
70
71
72
73
74
75
76"
77
• 79
7A
78
7C
7D
7E
7F •••••
18
••
20
28
30
38
•
•
••••
'.
••••
•
IF
.'
SG19
4F
•
57.
•
88888
88888
88888
888 8
88888
8888e
88888
80088
80088
88888
00000
00000
."
5F
Segments Driven 8y 10943
10942 and 10943 Driver Assignments
78.
••
6-47
:I>
, - DATA-LOAD
r-- SCLK·DIS
"'2.(;'
ao·
10938
SGXX
35
-
./
I
I
2 x 40
10938
SGXX
DATA-LOAD SCLK·DIS
35
./
-
I
f\
..
1
vJG
~
5 x 7 DOT MATRIX DISPLAY
I
!
~
~
~
z
.
N
N
2
CURSOR STRXX
I I
VDD- MASTER
10939
I I
SCLK·DIS (MASTER) I I
1
I
DATA-LOAD
CURSOR
I
SOP
SIP
SIP
SOP
10939
(SLAVE)
CLOCK
CLOCK
STRXX
I 'MASTER ~~ S
I I
SCLK·DIS I--
I
hlTA-LOADn
I
I
' I
~
cS'
CD
t
CURSOR
SCLK·DIS
JG
DATA-LOAD
1
!
I,
I I
CURSOR
STRXX
SIP
10939
(SLAVE)
I-
'"-"
CLOCK
SIP
CLOCK
DATA·LOAD
MASTER !-VSS VSS- MASTER
---
--
-
Figure 15. Driving a Two Line Display
- -
~Ith
a 10938 and a 10939
-
c
C;;'
STRXX
SCLK·DIS
10939
(SLAVE)
a
I' II
I I
----
I--
n
"of
oo
a
2CD
UJ
»
+5V~
~C
HOST
SYSTEM
10941
I
UDN
2981
:::l
Z
~
TI
I
I
~C
470
TYP
+5V
1 - - - - _... 1
1----_-12
....
10939
LD
~DX
4
§1CA>HODB
HDSP.6508
:::l
!:
cE'
CD
:::l
I
VCC
STR08
STR09
STR10
STR11
STR12
STR13
STR14
STR15
ANODES
1-----t3
ULN
2815
+5V
SOP
POR
G~~
_ _ _ _ _ _ _ _ _~
UDN
2981
SCLK- DATA STROO
DIS
LOAD
STR01
+5V ~VSS
STR02
VGG
STR03
STR04
STR05
STR06
STR07
-15V-dVDD
MSTR
~SIP
C'V
+5V,
SG09
SG10
SG11
SG12
SG13
SG14
SG15
SCLK- DATA- SG16
DIS
LOAD
~
a0'
VDD
-15V
~
..J
between the multiplexed digit pulses to assure that the response
time lag and extraneous noise does not cause undesirable
character illumination. Note that brightness will be constant when
duty factor is constant regardless of pulse width except that
brightness will deteriorate when the pulse width nears 8 pS or less.
Figure 22 shows the relationship of adjacent multiplexed grid
pulses with t~e blanking separation.
50
W
a:
25
0~--_~270--~0~~2~0--~40~~6~0~~a~0----
Because the fluorescent material has semiconductor properties
the luminance is also affected by ambient temperature as shown
in Figure 23. Most display tube manufacturers recommend operation between -10·C to + 55·C.
AMBIENT TEMPERATURE (OC)
Figure 23.
Ambient Temperature Effect
Tr
-GRID 1
I I I
)I'
..!... r-
t
:
FILAMENT LEVEL
u
u
II
;
I
r-
GRID 2
""W
Du
M
tp
tb
:
:
:
:
Tr :
ec :
eb :
Ek :
ecc :
ebb :
DUTY CYCLE
MULTIPLEXING RATE
PULSE DURATION
INTERDIGIT BLANKING
REFRESH PERIOD
GRID VOLTAGE
ANODE VOLTAGE
CATHODE BIAS
GRID SWING VOLTAGE
ANODE SWING VOLTAGE
t---
-
T
C±
ANODES
'--'
.c
.c
II
Du = tp/Tr
T, = Mxt
t
= tp + tb
ecc=ec+Ek
ebb =eb + Ek
""w
Figure 22.
Relationship of Adjacent Multiplexed Grid Pulses with Blanking Separation
6-53
[I
>
'"tI
'2.
0"
VSS
~
I
I
~
GRID
~
DRIVERS
f
~
VDD
~
ANODE
.....
VGG
B.
DRIVERS
C
---~
UI
~
r;J
z
2CD
r<
LOGIC
..J
LOGIC
VGG
~
1
1
VDD
a0"
VSS
VSS
1
VGG
VDD
~
DEVICE TYPE:
DRIVER TYPE:
PART NUMBER:
GRID/ANODE CONTROLLER
OPEN-DRAIN
10937, 10951, 10957
GRID CONTROLLER
PUSH-PULL
10939
ANODE CONTROLLER
PUSH-PULL
1093B, 10941, 10942, 10943
VDD
MAX Idd AT 25°C
L\lddlVdc
-15 ± 1.5 Vdc
2.12 rnA
0.057 mA/Vdc
-20 ±2 Vdc
4.0 rnA Slave, 6.0 rnA Master
0.025 mANdc
-20 ±2 Vdc
3.2 rnA
0.015 mA/Vdc
-50 Vdc
0.5 rnA
NEGLIGIBLE
-50 Vdc
BmA
0.15mANdc
VGG
MAX Igg AT 25°C
L\lgglVdc
~
cD"
CD
a
c
0"
'"tI
i
o
o
a
a
CD
Figure 24.
Disp.lay Controller Architecture
CiJ
Application Note
Intelligent Display Controllers
2 mA each. Each tube type is differenfand actual current requirements must be taken from the manufacturers display tube
specifications. This power is dissipated in the display tube rather
than in the controller device and is also dependent on the numb~r
of grids or anodes that are driven ON.
Device Power Requirements
Figure 24 shows the three basic types of Rockwell display controller devices. They have open-drain or push-pull drivers which
are shown schematically in Figure 25.
Vdd power is used in all three device types for the logic section.
Worst case dissipation is at Vdd max (-16.5 Vdc for the open-drain
device and -22 Vdc for the push-pull devices) and at the lowest
temperature (O°C for the commercial range and -40°C for the
industrial range). Idd varies as a function of applied voltage and
temperature.
Character Load Variations
The total device power required is dependent on the number of
grids or anodes being driven ON at any particular moment. The
grids are driven ON sequentially in a multiplexed fashion so that
only one grid is ever enabled at any time. The anodes are driven
individually to form different characters in both the segmented and
dot matrix displays. The anode driver devices are designed with
up to 35 output drivers available as shown in Table 14. However,
not every driver is used to form characters in each application.
Vgg power is dissipated in the push-pull driver devices when an
output grid or anode driver is ON (pulled to Vss). Most of the dissipation is in the logic pre-drivers but a small amount is also used
in the driver itself. At worst case, with Vgg at -50 Vdc and a temperature of -40°C, the maximum drain for each ON grid driver
is 25 mW or 0.5 mNdriver. As an example, since only one grid
driver and the cursor driver can be ON at the same time, the maximum Igg load of the 10939 device is 1.0 mAo The maximum drain
for each ON anode driver is 16 mW or .32 mA per driver, so the
maximum Igg load of the anode controller with all 35 anode drivers
ON would be 11.2 mA.lgg varies not only as a function of the number of drivers ON, but also as a function of applied voltage and
temperature.
Table 14 shows the dot patterns of the 128 character font for the
10938 anode driver device. Except for the inverse mode in which
all the dot patterns are reversed, and character 7F which has all
anodes ON; the worst case dot pattern is letter "8" which has
20 anodes ON. If, for example, a particular application requires
only alpha-numeric characters displayed, the peak drive current
required for the load would be only 57 percent of the worst case
load. With a display tube requiring a maximum load of 2 mA
for each dot anod3, the total Igg current required would
be (35 x 2 mA x 0.57) 39.9 mA for the display tube and
(35 x 0.32 mA x 0.57) 6.4 mA for the 10938 drivers. The average
current would be (35 x 2 mA x 0.384) 27 mA for the display tube
and (35 x 0.32 x 0.384) 4.3 mA for the 10938 drivers. Note,
however, that the actual predominance or frequency of use of each
character has to be considered to obtain a realistic average current over a given time period. Table 15 lists the average ratios of
anodes ON per total anodes for the various anode driver devices.
Effects of Voltage Variations
The effects of supply voltage variations on current drains are
shown in Figure 26. As Vdd supply voltage increases the current
also increases at rates from approximately 0.015 mNVdc to almost
0.06 mNVdc depending on device type. Igg also increases as Vgg
increases for the push-pull driver devices as shown for the 1094X
anode driver devices.
Effects of Temperature Variation
As previously stated, the worst case supply current is at the lowest
temperature extremes. The power dissipation in the controller
device for both Vdd and Vgg generally follow the curve shown in
Figure 27. The curve is defined by the equation below and is normalized to +25°C:
DISPLAY SYSTEM POWER CONSIDERATIONS
The controller device power is not the only power that has to be
considered in deriving display system power requirements. Also
to be considered are the power for the host microprocessor and
the display tube load.
K' (T)m
To
Ko' =
Where K'
Ko'
T
To
m
= K factor at new temperature, T
= K factor at To (25°C)
Typical Power Flow
= New temperature, in Kelvin
= Initial temperature (25°C = 298°1<)
The microprocessor is normally a bipolar or MaS device requiring +5 vdc for its power source. In such a display system the Vss
return for the control devices is returned to the +5 vdc Vcc as
shown in Figure 28. Vdd is a negative supply, referenced to Vss,
to supply the logic sections of the controller device. Vgg is a
negative voltage to supply anode and grid current through the controller output switches to the display' tube. Ek is a positive level
voltage referenced to Vgg for cathode bias (to the center tap of
the filament transformer). The filament voltage is an ac 60 cycle
voltage supplied through a step down transformer or a dc-dc converter output which supplies a chopped high frequency square
wave.
= Exponent, dependent on device materials
Display Load Variations
Current is drawn from the Vgg supply due to the display grid or
anode load itself. This load is a function of the display tube and
may be any load up to the maximum allowed by the device driver.
Iload (max) for the grid, cursor, point and tail drivers is 20 mA for
the single chip controllers and 10 mA for the grid controller drivers.
The maximum load on the segment drivers of the single chip controllers is 10 mA and the maximum load of the anode drivers is
6-55
Application Note
Intelligent Display Controllers
OPEN-DRAIN DRIVERS
(10937, 10951, 10957)
>>-----t~
PUSH PULL-DRIVERS
(10938, 10939, 1094X)
Vss
- I
R .. 860 FROM I
=0 TO 25 MA
Vgg
Figure 25.
Controller Drive Circuits
0.225
0.200
0.175
0.150
4.ldd
(mA)
0.125
0.100
0.075
0.050
0.025
0.000
2
0
3
4.Vdd (VDC)
41dd/4.Vdd 10937, 51, 57
10939
10938, 4X
4.lgg/4.Vgg 10938,4X
Figure 26.
..
..
..
..
0.057 mAlVdc
0.025 mAlVdc
0.015 mA/Vdc
0.15 mA/Vdc
Effects of Voltage Variation, .6ldd/.6Vdd (at 25°C)
6-56
4
Application Note
Intelligent Display Controllers
1.4
1.2
K'
Ko'
RATIO
1.0
0.8
0.6
-40
0
70
25
85
AMBIENT TEMPERATURE, ·C
Temp (·C)
K'/Ko'RATIO
Figure 27.
I
-40
1.38
I I
0
1.1
+25
1.0
I
+70
0.83
Effects of Temperature Variations
6-57
+85
0.78
Application Note
Intelligent Display Controllers
Table 14.
z
z
o
o
I
I
~
~
o
17
14:
:
17
13
17
.c
U
.....
18
7
14
18
9
11
17
11
17
o
5
6
9
... ....·
·.... ·
... ...
·.... .
· . ··......
·· .
.
r"i ...·
·..... · .
· ·.
..
·
·. ·
.. .....
.....
·
....
.
· . ··........
·.
·... ..·
11
10
••
9
16'
17
•
...
18 : : ;
z
o
:=
j..
... .. · ..
· ..
· ..
10
16
18
14
.....
....
·
18
.....
·
2
....
9
.....
16
....
7
."
·
4
....
::::.
......
·
·.....
. .·
·
·.... ....
14
U
12
....
,':
7
o
:=
'8c:
~
~
16
15
16
5
17
16
9
7
15
.. . ··....
· .. ·....
16
3
•••••
2
5
13
5
3
9
15
15
.c
8
z
z
o
:=
'8
j.
I
....
18
...
...
.....
10938 Dot Patterns
.....
...
15
#
%
Anodes Anodes
17
16.
7
10
.. .
•
.
.·....
Character!s)
11
2
3
9
·....
. . ...
· ...
.....
·.....
13 : ..
17
•••
17
11
15
•
13
13
5
13
11
14
15
11
..
....
·.....
·
.
·.
·· ~':"
..... · .
·...
....
....
· . · .·
·...... ........
....
·
·
·..... ·.... · ....
....
· ·....
i
.... :::i .....
·
...· · .. · . ·....
..·
. · ·
··... ... ......
·.
·
..
.....
......·
.·
.·....
20 : ••••
13 : ••••
18'
11
•
•
17
•
16 :
11
9
15 : ••••
17 : . :
18
13
10
15
14
14 ;:::.
11
8
8
11
;:.
9
16 • • •
12'
14
8
12
::::.
10
12.
•
9
12
10
13
13
14
.'::
5
35
17
3
14
9
•
:....
·.....
14
:':'
15
15
••••
:
6-58
':
16'
18
.:.
•
:.:.:
11
17 : •••
•
12
•••••
4
5
Letter "8"
Avg of all Numeric
Avg of all Alpha
Caps
Avg of all Alpha
Lowercase
Avg of items
2&3
6 Avg of items 2
thru 4
7 Avg of all
characters
ON
ON
20.0
14.1
57.1
40.0
14.9
42.6
11.7
33.4
14.7
41.9
13.4
38.4
12.4
35.4
Application Note
Intelligent Display Controllers
Table 15.
Character Anodes ON Summary
% Anodes On
Character(s)
Display Type
10937, 10957
10938
10941""
16
35
16
10942/43
46
$.%,0
10
63.0
B
20
57.1
$,%,0,8
10
62.5
B
20
43.5
• Numeric (Avg, 010)
46.0
40.0
46.3
31.1
• Alpha all caps (Avg, %)
39.0
42.6
38.9
32.4
• Total Anodes
• Worst Case Digit(s)"
Anodes ON
% Anodes ON
-
33.4
-
26.9
• Alpha Caps - Numeric (Avg, %)
41.0
41.9
41.0
32.1
• Alpha - Numeric (Avg. Ofo)
41.0
38.4
41.0
29.9
24
35.4
:r7.0
27.2
• Alpha lower case (Avg, %)
• All Characters (Avg, %)
"Excluding inverse and all dots ON pattern.
"" Excluding bargraph
(
(ISSG(M0
r-""Vs:-Js-"
GRID
DRIVER (M)
+
Veld
-=-
20 VDC
Veld Vgg
Igg
+
Idd
Vgg
50VDC--
Idd~
~==::====::=::;::=.;::::>I
Ie -
Vss
GRID
DRIVER(S)
Veld Vgg
Idd~
Vss
ANODE
DRIVER
Vdd Vgg
Ib-
Idd A
..J
Ek
Igg~
Vee
Veld
Vgg
Icc
Idd
Igg
Igg~
= Icc (HOST)
= Idd G(M) + Idd G(S) + Idd A
= Igg G(M) + Igg G(S) + Igg A + Ibe
Figure 28.
Typical Display System Power Flow
6-59
I~
Application Note
Intelligent Display Controllers
Example 1: 20·Character Display
As discussed before, Vgg is determined by the sum of eblec and
Ek. Ek bias above Vgg is normally provided by a zener diode
reference. The ac filament voltage, Ek and eblec are specified by
the display tube manufacturer.
Figure 29 shows a 5 x 7 doi matrix 20·character display tube
being driven by a 10938 anode driver and a 10939 grid driver and
controlled by an R6500/1 microprocessor. Five voltage levels are
required including the ac filament voltage of 6 Vac @ 23 mA
typically.
The Vcc current requirement is typically 100 mA at +25°C. The
Vdd current requirements from Figure 24 are 6 mA for the 10939
grid driver and 3.2 mA for the 10938 anode driver. Vgg current from
Figure 24 is .25 mA for the 10939 and 8 mA for the 10938,
however, this is at a Vgg of -50 Vdc. At -33 Vdc the 10938 cur·
rent reduces at a rate of 0.15 mANdc for a total of [8-(0.15)(17)]
5.5 mAo Other Igg components from the display tube
characteristics include the anode drive of 2.7 mNall dots ON, and
the grid drive of 2.9 mA. This total Igg current of 11.3 mA is
representative of all 35 dots on continuously.
The other voltages are:
Vcc of +5 Vdc referenced to Gnd for the microprocessor
Vdd of -20 Vdc referenced to Vss for the driver devices
Vgg of -33 Vdc referenced to Vss for the driver devices
Ek of +6 Vdc referenced to Vgg for the display tube cathode
10
FUTABA
1
2 n1Z
Vss
Vee
HOST
".P
10
I~
I
.
VddVgg
~
Vee
Vdd
, Vee
10938
R650011
<;.
..
Vss
~
10939
MASTER
Vdd Vgg
GND
Ib5 x 7 DOT MATRIX
20 CHARACTER DISPLAY
eb/ee
= 27VDC
Ib/ALL DOTS = 2.7 mA,
IcJDIG
= 2.9 mA
le-.
~
~
-$-
--
Vg!l
~ Ef = 6.0 VDC at 23 mA
10
'2
r-'.
~ Ek
= 6.0V
0
Vee = +5 VDC
Vdd = -20VDC
Vgg = (Vebe + Ek) = -33 VDC
AT 25·C, TYPICAL
• Idd (AT -20 VDC)
• Igg (AT -33 VDC)
ALL DOTS "ON"
ALPHA NUMERIC ONLY
PEAK, LETTER "B"
AT -40·C W.e.
• Idd (AT -22 VDC)
• Igg (AT -36 VOC)
ALL DOTS "ON"
'PULLUPS REQUIRED ON
ALL INPUTS FROM
TTL SOURCES
(1) 10939
GRID DRIVE
(1) 10938
ANODE DRIVE
6.0
DISPLAY TUBE
TOTAL
(mAl
Ib
Ie
3.2
-
-
0.2
0.2
0.2
5.5
2.1
3.1
2.7
1.1
1.5
2.9
2.9
2.9
11.3
6.3
7.7
13.6
4.5
-
-
18.1
8.2
3.7
4.0
16.4
0.5
Figure 29. 20 Character Display Example
6-60
9.2
Application Note
Intelligent Display Controllers
For display operation of alphanumerics only, with an average of
38.4 percent of the dots ON as shown in Table 15, anode drive
currents reduce to a totallgg of 6.3 mAo Peak Igg for the letter
"8" increases anode drive current to 57 percent of all dots for
a total of 7.7 mA.
Example 3: Two-line by 40-Character Display
Figure 31 is an example of a more advanced display system. The
major difference between this example and Example 2 is that two
grids are enabled at the same time (one in each line) and therefore the grid drive current and Ic are doubled.
Worst case power dissipation is also shown in Figure 29. This is
at maximum voltage excursions and a temperature of -40·C.
(Keep in mind, however, that most VF display tubes are recommended for operation down to only about - 1O·C to - 20·C.) Idd
at - 22 Vdc increases by 0.03 mA for the 10938 (as shown in
Figure 24) to 3.23 mAo Figure 27 shows that a factor of 1.38 is
used to determine Idd or Igg at - 40·C so that the total Idd
becomes (3.23 • 1.38) 4.5 mA. Igg for the 10938 becomes
[(5.5 mA + 0.15 mANdc • 3 Vdc) 1.38) 8.2 mAo The same
procedure is used to determine the grid driver current requirements. Igg is assumed to increase by 50 percent worst case. The
tube currents ib and ic are assumed to increase by 20 percent
as temperature decreases from + 25·C to - 20·C and voltage
increases to maximum which is worst case for VF display tubes.
Power Source
The power source for the display systems can be derived from
standard power supplies, custom designs, or DC-DC converters.
Four separate standard supplies could be used to furnish the four
dc voltages required for Example 1 as shown in Figure 32. This
is expensive, however, and the proper voltage levels are not really
"standard" in most cases, and therefore not readily available.
Tracking of the power supplies upon power turn-on and turn-off
could also be a problem. The structure of the PMOS display driver
devices is such that Vgg should not be more negative than Vdd
unless Vdd is at -10 Vdc or greater; otherwise, damage to the output drivers is possible. If the 40 Vdc Vgg supply has much faster
response than the 20 Vdc Vdd supply in Figure 32, this problem
could exist.
Note in these examples that the cursor drive requirements for the
10939 and display tube have not been included and would have
to be added to the totals when used.
Figure 33 shows how the voltages could be derived using only two
standard supplies and zener diodes for the other levels. Using a
zener diode to generate Vdd from the Vgg supply level assures
that the Vdd and Vgg levels "track" all the way to Vdd. This is also
shown in Figure 33. Another zener is used to generate the Ek bias
voltage above Vgg for the filament transformer center tap.
Example 2: 40-Character Display
Figure 30 shows how the 10939 controller devices are cascaded
to control the 40-character display tube. The 10942143 devices
are used in parallel to provide an expanded font capability for a
5 x 12 dot matrix.
DC-DC converters are also available that have been designed
specifically to provide the power requirements for particular
display tube types available in the marketplace. As shown in
Figure 34, these converters normally oscillate the low voltage dc
input through a step-up transformer and then rectify and filter the
high frequency square wave to provide the desired output voltage.
A dc feedback Is applied to the input oscillator transistor to adjust
the oscillation duty cycle and thus provide a constant voltage output. provide multiple dc output levels (such as for Vdd and Vgg)
muill-turn secondary transformer taps and rectifier filter sections
are included In the design. See Reference 3 for addresses of DCDC converter vendors.
The current requirements for this system are determined in the
same way as in Example 1. Note that when two 10939s are used,
the logic current (Idd) is the sum of a master and one slave but
the grid drive current (Igg) remains the same. This is because in
a master-slave configuration only one grid is enabled at any given
moment giving a constant Igg and ic load of a single grid.
:0
For this example Vgg is - 50 Vdc (eb/ec of 41 Vdc and Ek of
9 Vdc) for an Igg of .25 rnA for the grid drivers. However, only 23
of the 35 drivers are used in the anode driver bringing the total
to 5.25 rnA/device. For totally alphanumeric applications the
anode currents reduce to 30 percent of all dots ON and the peak
currents for letter "8" reduce to 43.5 percent of full ON.
FOOTPRINTS
Figure 35 contains the pin configurations of all the products of the
Intelligent Display Controller family.
The worst case power dissipation at voltage and temperature
extremes are calculated in the same way as in Example 1.
6-61
Application Note
Intelligent Display Controllers
10942
r+-
Vdd
10943
~
-"
""23..,.....
Vgg
Ib
-t
'b"V
Vgg
eb/ee
ib/ALL DOTS
ib/46 ANODES
ie/DIGIT
40 CHARACTER
5 x 12 DOT MATRIX
NORITAKE
DC4010A2
~
I
Vdd
-
W
F= -
0
'"
+
0
Ie
'"
Ef = 9.7V AT 104 MA
'2.~
10939
(S)
10939
(M)
Vdd
41 VDC
15T030mA
9.9 TO 19.7 mA
12T024mA
,...........,
.
Ie
=
=
=
=
Vgg
Vdd
Vgg
/\
'\
Vee
Vee = +5 VDC
Vdd = -20VDC
Vgg = (41 + 9) = -50 VDC
HOST
R6500/1
Vee_ Vee
Vee ;>
Vdd~
Vgg
·PULWPS REQUIRED ON ALL
INPUTS FROM TTL SOURCES
(2) 10939
GRID DRIVE
AT 25"C, TYPICAL
• Idd (AT -20 VDC)
• Igg (AT -50 VDC)
ALL DOTS "ON"
ALPHA NUMERIC ONLY
PEAl<, LETTER "B"
AT -40·C W.e.
• Idd (AT -22 VDC)
• Igg (AT -55 VDC)
ALL DOTS "ON"
M
6.0
13.6
"
(1) 10942
(1) 10943
ANODE DRIVE
DISPLAY TUBE
Ib
Ie
TOTAL
(mA)
S
4.0
6.4
-
-
16.4
0.3
0.3
0.3
10.5
3.2
4.6
15.0
4.5
9.4
12.0
12.0
12.0
37.8
20.0
25.3
9.1
8.9
-
-
31.6
0.5
14.5
18.0
14.4
47.4
Figure 30.
40 Character Display Example
6·62
Intelligent Display Controllers
Application Note
10938
eb/ee
= 42 VDC
Ek
=8VDC
ib/ALL DOTS = 7.5 to 15 mA
ie/DIGIT
= 15 to 25 mA
Ef = 9 VAC AT 15 mA
2 LINE
2 )( 40 CHARACTER
5 )( 7 DOT MATRIX
NORITAKE
DC40026B2
10938
HOST
(SEE FIGURE 15 FOR TYPICAL INTERCONNECTIONS.)
(4) 10939
GRID DRIVE
AT 25°C, TYPICAL
• Idd (AT -20 VDC)
• Igg (AT -50 VDC)
ALL DOTS "ON"
ALPHA NUMERIC ONLY
PEAK, LEITER "B"
AT -40°C W.C.
• Idd (AT -22 VDC)
• Igg (AT -55 VDC)
ALL DOTS "ON"
M
6.0
(2) 10938
ANODE DRIVE
(3) S
12.0
6.4
0.5
0.5
0.5
16.0
6.2
9.2
13.6 27.3
9.0
1.0
22.4
DISPLAY TUBE
ib
ie
TOTAL
(mA)
15.0
5.8
8.6
30.0
30.0
30.0
61.5
42.5
48.3
22.4
49.9
18.0
'PULLUPS REQUIRED ON
ALL INPUTS FROM
ITLSOURCES
Figure 31.
Advanced Display System Example
6-63
36.0
77.4
Intelligent Display Controllers
Application Note
Vel."
5VDC
+
+
1
+
+
Vdd
40VDC
20VDC
Vgg
I-
-
+
I
I -1 I 1
6.8 VDC
T
Figure 32.
Standard Power Supply Source
6-64
Application Note
Intelligent Display Controllers
r-----------------r--------------------------oGND
5VDC
+
Vss, Vee
r
+
20VDC
40VDC
1
40VDC
Vdd
v,
Ek
--
c;J
Vgg
Vee
+5VDC-OVDC--
Vdd
-20VDC--
Vgg
-40VDC - 200MS
__
_
TURN-ON
1~--~-----800MS----------~.~1
__
--.
Figure 33_
TURN-OFF
Modified Power Supply Source
6-65
_
Application Note
•
0
DC
INPUT
0
OSCILLATOR
.IL
•
TRANSISTOR
Intelligent Display Controllers
][
STEP-UP
RECTIFIER·
FILTER
f----
~
f----
TRANSFORMER
T
•
•
CIRCUIT
II
ACOUTPUT
VOLTAGE
REGULATOR
Figure 34.
DC
OUTPUTIS)
I~
DC·DC Converter Power Source
6·66
Application Note
Intelligent Display Controllers
Voo
Vss
SG35
DATA·LOAD
SG34
DATA·LOAD
SCLK·DIS
SG01
Voo
Vss
PNT
SG02
TAIL
SG33
SG03
SG32
DATA·LOAD
Voo
SCLK·DIS
SG01
Vss
SG23
SG02
SG22
SG02
NOT USED
SG03
SG21
SG03
SG04
SG16
SG04
SG20
SG04
SG31
SG05
SG15
SG05
SG19
SG05
SG30
SG29
SG06
SG07
SG14
SG06
SG18
SG06
SG13
SG17
SG07
SG28
SG08
SG12
VGG
SG07
SG16
SG08
SG27
SG09
SG11
SG08
SG15
SG26
SG10
SG10
SG09
SG14
VGG
SG09
SG25
SG11
SG13
SG10
SG24
SG23
SG12
SG12
SG11
SCLK·DIS
SG22
VGG
SG13
SG21
SG14
SG20
SG15
SG19
SG16
10941
Anode Driver
Multl·Chlp Display Controller
SG01
10942 and 10943
Anode Driver
Multl·Chlp Display Controller
SG17
SG18
10938
Anode Driver
Multl·Chlp Display Controller
SCLK·DIS
SOP
VSS
PNT
MASTER
AD16
TAIL
DATA·LOAD
CLOCK
AD15
SGP
POR
Voo
AD14
SGO
LD
Vss
AD13
SGN
DO
AD12
SGM
01
VGG
STROO
AD11
SGL
02
STR01
AD10
SGK
03
STR02
AD9
SGJ
04
STR03
AD8
SGI
05
STR04
AD7
SGH
06
STR05
AD6
SGG
07
ADS
AD4
SGF
CURSOR
STR06
STR07
STR19
STR08
AD3
SGD
STR18
STR09
AD2
STR17
STR10
AD1
SGC
SGB
STR16
STR11
VDD
SGA
STR15
STR14
STR12
STR13
A
POR
SCLK
SIP
10939
Grid Driver
Multl·Chlp Display Controller
Figure 35.
SGE
DATA
10937,10951 and 10957
Single Chip Display Controller
Pin Configurations of Intelligent Display Controllers
6·67
II
Application Note
Intelligent Display Controllers
REFERENCES
3. DC-DC Converters
• FUJI Electrochemical Co., Ltd.
16921 South Western Avenue
Gardena, CA 90247
(213) 323-1134
1. Application Notes
• A Dot Matrix Controller System Design using the
10938/10939 Display Drivers and R6500/1EB Microcomputer," Rockwell International, APP Note Order
No. 2163, P.O. Box C, Newport Beach, CA 92660.
• TDK Corp. of America
3102 Kashiwa Street
Torrance, CA 90505
(213) 539-6631
• "Vacuum Fluorescent Display," Application Notes AP-01
through AP-05. Noritake Electronics (See Reference 2.)
4711 West Golf Road, Suite 300
Skokie, IL 60076
(312) 679-8200
2. Vacuum Fluorescent Display Tubes
• Futaba Corporation
555 West Victoria Street
Compton, CA 90220
(213) 537-9610
142 Crossen
Elk Grove Village, IL 60007
(312) 364-7204
• Noritake Electronics, Inc.
22410 Hawthorne Boulevard, Suite #6
Torrance, CA 90505
(213) 373-6704
1822 Brummel Drive
Elk Grove Village, IL 60007
(312) 439-9020
6-68
ROCKWELL SEMICONDUCTOR PRODUCTS SALES OFFICES
REGIONAL SALES OFFICES/ROCKWELL SEMICONDUCTOR PRODUCTS
HEADQUARTERS
0104
Semiconductor Products Division
Rockwell International
4311 Jamboree Road
P.O. Box C, M S 501-300
Newport Beach, California 92660-3095
(714) 833-4700
1WX: 910591-1698
UNITED STATES/CANADA
0105
Semiconductor Products' Division
Rockwel11ntemational
4311 Jamboree Road
Newport Beach, California 92660-3095
(714) 833-4655
1WX: 910 591-1698
0106
Semiconductor Products Division
Rockwell International
3375 Scott Blvd., Suite 41 0
Santa Clara, California 95054
(408) 980-1900
1WX: 650 260-6750
FAX: (408) 980-0744
0109
Semiconductor Products Division
Rockwellinternationai
3081 Holcomb Bridge Rd., Suite A
Norcross, Georgia 30071
(404) 446-7414
FAX: (404) 446-7598
0101
Semiconductor Products Division
Rockwell International
2001 N. Collins Blvd., Suite 103
Richardson, Texas 75080
(214) 996-6500
TLX: 650227-9516
FAX: (214) 996-7812
0102
Semiconductor Products Division
Rockwell International
FAR EAST
0210
0240
Semiconductor Products Div. GmbH
Semiconductor Products Division
Rockwell International
10700 West Higgins Rd.
Suite 102
Rosemont, Illinois 60018
Overseas Corp.
Dai-ichi Hirakawa-cho Bldg.
7-S, 2-chome, Hirakawa-cho
Chiyoda-ku, Tokyo 102, Japan
(312)297-8862
FAX: (312) 297-3230
0103
Semiconductor Products Division
Rockwellinternationai
5001 B Greentree
Executive Campus, Rt. 73
Marlton, New Jersey 08053
0263
Rockwell International Ltd.
20123 Milano, Italy
FAX: (39-2) 498-1450
TLX: 316562 RCIMIL 1
(852-5) 246-033
TLX: HX74071
0107
EUROPE
Semiconductor Products Division
Rockweillnternational
2 Burlington Woods Drive
Burlington, Massachusetts 01 803
0201
Semiconductor Products Division
Rockwell International GmbH
Fraunhoferstrasse 11
0-8033 Munchen-Martinsried
West Germany
Semiconductor Products Division
55 Town Center Court
Suite 700
Scarborough, Ontario
Canada M 1 P 4X4
Semiconductor Products
Rockwell-Collins Italiana S.P.A.
Via Boccaccio, 23
0278
Semiconductor Products Division
Rockwell International
Immeuble Bureaux Evry 2
523, Place des Terrasses
91 034 Evry Cedex, France
(33-16) 497-2828
TLX: 690-328
FAX: (33-16) 078-2888
SOUTH AMERICA
0110
Semiconductor Products Division
(49-89) 857-6016
TLX: 521-2650 rimd d
FAX: (089) 8.57.57.93
Rockwell International
3375 Scot1 Blvd" Suite 410
0202
(408) 980-1900
1WX: 650 260-6750
Semiconductor Products Division
Rockwell International Limited
Central House
3, Lampton Road
Hounslow, Middlesex,
(416) 296-1644/1645
TLX: 06525235
FAX: (416) 296-1259
16340 Spanga
(46-8) 751-5000
TLX: 122442
0246
(609) 596-0090
MCI: 6502229511
FAX: (609) 596-5681
0111
Isafjordsgatan 11
Sweden
(81-3) 265-8808
TLX:J22198
FAX: (81-3) 263-0639
904 World Wide House
19 Des Voeux Road Central
Hong Kong
(61 7) 272-5645
MCI: 6502512464
FAX: (617) 273-2399
Rockwell International
1W3 1 HY England
(44-1) 577-2800 -or(44-1) 577-1034
TLX: 265871 MONREF G REF. DUCOOl
Santa Clara, CA 95054
CENTRAL AM ERICA/M EXICO
0110
Semiconductor Products Division
Rockwell International
4311 Jamboree Rd.
P.O. Box C, M S 501-301
Newport Beach, CA 92658-8902
(714) 833-4655
1WX: 910 591-1698
For applications assistance, price quotations or technicalliteralure on Rockwell modem, controller and high speed telecommunication producls,
call your local Rockwell Semiconductor and Products Division sales office.
SALES REPRESENTATIVES - UNITED STATES/CANADA
ALABAMA
2000
Robert O. Whitesell & Associates
Braham Springs Professional Village
2227 Drake Ave., S.W., Ste. 10-F
P.O. Box 1797
GEORGIA
2060
Criterion Sales Inc_
2002
3350 Scott Blvd., Bldg. #44
Santa Clara, CA 95054-3126
(408) 988-6300
FAX: (408) 986-9039
Currie, Peak and Frazier, Inc_
5664 Peachtree Parkway, Ste. J
Norcross, GA 30092
(404) 449-7662
Huntsville, AL 35807
(205) 883-5110
FAX: 205882-9626
ARKANSAS
2026
Norcom Inc.
2227 S. Garnet1 Rd., St •• 109A
(Tulsa, Oklahoma 74129)
(918) 832-7747
1WX: 910845-2298
CALIFORNIA
2033
Centaur Corporation
18006 Skypark Circle, Ste. lOS
Irvine, CA 92714
(714) 261-2123
1WX: 910595-2887
FAX: (714) 261-2905
2037
Centaur Corporation
23901 Calabasas Rd., Ste. 1063
Calabasas, CA 91302
(818) 704-1655
2045
Centaur Corporation
9420 Farnham, Suite 201 A
San Diego, CA 92123
(619) 278-4950
FAX: (619) 278-0649
COLORADO
IDAHO
2072
Quorum 3
8000 E. Girard Ave., Suite 302
Denver, CO 80231
Westerberg Associates
(See Bellevue, Washington)
(303) 696-8480
1WX: 910 997-8013
FAX: (303) 696-8579
ILLINOIS
2009
Robert
O.
Whitesell & AssOCiates
1825 S. Plale, Suite A
Kokomo, IN 46901
(317) 457-9127
1WX: 810 269-1917
IOWA
2070
Dy-Tronlx Inc.
23 Twixt Town Rd. N.E" Sle. 201
Cedar Rapids, IA 52402-3297
(319) 377-8275
FAX: (319) 377-9163
2006
LTD Technologies Inc.
810 Arlington Heights Rd.
Itasca, IL S0143
CONNECTICUT
2004
Kitchen & Kutchin
23 Peck Street
North Haven, CT 06473
(312) 773-2900
1WX:332415
FAX: (312) 773-0358
(203) 239-0212
1WX: 910 474-0011
INDIANA
DELAWARE
2007
2003
Robert O. Whitesell & Associates
Beacon North
103-F Carpenter Dr.
3426 Taylor SI.
iSterling, VA 22170)
(703) 478-2480
(219) 432-5591
1WX: 810332-1416
Fort Wayne, IN 46804
2008
Robert O. Whitesell & Associates
6691 E. Washington SI.
P.O. Box 19904
FLORIDA
2005
Currie, Peak & Frazier, Inc_
7335 Lake Ellenar Or.
Orlando Central Park, FL 32809
Indianapolis, IN 46219-0904
(317) 359-9283
1WX: 810 341-3320
FAX: (317) 359-2091
(305) 855-0843
1WX: 810 850-0106
FAX: (305) 855-5619
A-1
KANSAS
2081
Dy-Tronlx Inc.
1999 Amidon, Suite 322
Wichita, KS 67203-2124
(316) 838-0884
KENTUCKY
2082
Robert O. Whitesell & Associates
313 Lagrange Rd., Suite 201
P.O.80x797
Pewee Valley, KY 40056-9998
(502) 241-8977
LOUISIANA
Robert O. Whitesell & Associates
(See Huntsville, Alabama)
MAINE
Kitchen & Kutchln, Inc.
(See Burlington, Massachusetts)
SALES REPRESENTATIVES - UNITED STATES/CANADA (cont'd)
MARYLAND
Beacon North
(See Sterling, Virginia)
MASSACHUSETTS
2012
Kitchen & Kutchln, Inc.
87 Cambridge 8t.
Burlington, MA 01803
(617) 229-2660
FAX: (617)273-5895
MICHIGAN
2011
R.O. Whitesell & Associates
8332 Office Park Dr., Ste. A
Grand Blanc, MI 48439-2035
(313) 695-0770
TWX: 810 224-4939
2013
Robert O. Whitesell & Associates
688 Cascade West Parkway S.E.
Grand Rapids, MI 49506
(616) 942-5420
2014
Robert O. Whitesell & Associates
18444 W_l0 Mile Rd,
Southfield, MI48075
(313) 559-5454
TWX: 510 601-2458
2015
R.O. Whitesell & Associates
1822 Hilltop Rd,
S!. Joseph, MI 49085
(616)983-7337
MINNESOTA
2077
Electronic Innovators, Inc.
9727 Valley View Rd.
Eden Prairie, MN 55344
(612)941-0830
TWX: 499-7805
FAX: (612)941-6193
MISSISSIPPI
Robert O. Whitesell & Associates
(See Huntsville, Alabama)
MISSOURI
2068
Dy-Tronlx Inc.
3407 BridgeJand Drive
Bridgeton, MO 63044
(314)291-4777
FAX: (314) 291-3861
2069
Dy~Tronix
Inc.
8801 E, 63rd St., Ste, 108
Raytown, MO 64133-4865
(816) 356-6340
MONTANA
2067
Rockwell International
10700 W. Higgins. Ste. 102
(Rosemont, IL 60018)
(312) 297-8862
TWX: 910 233-0179
NEBRASKA
DY'Tronix Inc.
(See Cedar Rapids, Iowa)
(See Bridgeton, Missouri)
NEVADA
Criterion Sales Inc.
(See Santa Clara, California)
NEW HAMPSHIRE
2025
Robert O. Whitesell & Associates
4133 South Dixie Ave.
Dayton, OH 45439
(513) 298-9546
TWX: 510 601-2416
Kitchen & Kutchin, Inc.
(See Burlington, Massachusetts)
NEW JERSEY
2043
PAF Associates
VIRGINIA
2034
Beacon North, Inc.
103-F Carpenter Dr.
Sterling, VA 22170
(703)478-2480
TLX: 510600-8363
FAX: (703)435-7115
OREGON
508 MainSt.
2079
Westerberg Assoc., Inc.
7165 S.W. Fir Loop
Portland, OR 97223
(503) 620-1931
Boonton, NJ 07005
(201) 335-0680
2017
Naudaln Associates
The Pavilions at Greentree
Route 73, Ste. 307
Marlton, NJ 08053
(609) 983-5300
FAX: (609) 596-5367
PENNSYLVANIA
Naudain Associates
(See Marlton, New Jersey)
2028
Robert O. Whitesell & Associates
1360 Old Freeport Rd., Ste. l·B
Pittsburgh, PA 15238
(412)963-6161
NEW MEXICO
2018
Rep NewTec
9219 Lagrima De Oro Rd., N.E.
Albuquerque, NM 87111
(505) 293-2582
WASHINGTON
2078
Westerberg Assoc., Inc.
12505 N.E. Bel-Red Rd., Ste. 112
Bellevue, WA 98005
(206)453-8881
TWX: 910240-1599
FAX: (206) 453-8758
WASHINGTON, D.C.
2076
Beacon North
103·F Carpenter Dr.
(Sterling, VA 22170)
(703)478-2480
WEST VIRGINIA
RHODE ISLAND
Kitchen & Kutchln, Inc.
(See Burlington, Massachusetts)
NEW YORK
2048
Ossmann Component Sales Corp.
6666 Old Collamer Rd.
East Syracuse, NY 13057
(315)437-7052
FAX: (315)437-2332
2049
Ossmann Component Sales Corp.
280 Metro Park
Rochester, NY 14623
(716) 424-4460
TWX: 310 493-7053
FAX: (716) 427-2861
2020
PAF Associates
120 W. Main St.
Smithtown, LI, NY 11787
(51 6) 360-0940
Mel: 6502811354
SOUTH DAKOTA
Rockwell International
(See Rosemont, Illinois)
TENNESSEE
2029
Robert O. Whitesell & Associates
408 Cedar Bluff Rd., Ste. 145
Knoxville, TN 37923
(615) 694-9476
TEXAS
2031
Norcom, Inc.
8330 Burnet Rd., Suite 106
Austin, TX 78758
(512) 451-2757
TWX: 910 874-1383
NORTH CAROLINA
2030
Norcom, Inc.
4450 Sigma Ad.
Suite 135
Dalias, TX 75234
(21 4) 386-4888
FAX: (214)386-4907
2021
Currie, Peak and Frazier, Inc.
1212GroveSI.
P,O, Box 5588
Greensboro, NC 27403
(91 9) 373-0380
2032
Norcom, Inc.
8502 Tybor, Suite 115
Houston, TX 77074
(713)778-0392
TWX: 910 881-1056
NORTH DAKOTA
Rockwell International
(See Rosemont, Illinois)
OHIO
2022
Robert O. Whitesell & Associates
1172 West Galbraith
Cincinnati, OH 45231
(513) 521-2290
2023
Robert O. Whitesell & Associates
6000 West Creek Rd., Suite 21
Cleveland, OH 44131
(21 6) 447-9020
TWX: 810427-2211
2024
Robert O. Whitesell & Associates
6161 Busch Blvd., Ste.l08
Columbus, OH 43229
(614) 888-9396
TWX: 801 337-2076
A-2
2080
Norcom, Inc.
7110 Mountain Grove
San Antonio, TX 78250
(512) 680-4513
UTAH
2073
Quorum 3
7427 Parkcrest Ct.
Salt Lake City, UT 84121
(801) 943-9227
VERMONT
Kitchen & Kutchin, Inc.
(See Burlington, Massachusetts)
Robert O. Whitesell & Associates
(See Cincinnati, Ohio)
WISCONSIN
2058
Larsen Associates Inc.
10855 W, Patter Rd.
Wauwatosa, WI 53226
(414) 258-0529
FAX: (414)258-9655
WYOMING
Quorum 3
(See Denver, Colorado)
CANADA
2036
Renmark Electronics Limited
110 West Beaver Creek Road, Ste. 7
Richmond Hill, Ontario
Canada L4B 1 J9
(416) 881-8844
FAX: (416) 881-8848
2047
Renmark Electronics limited
1445 Woodruffe Ave.
Ottawa, Ontario
Canada K2G 1W1
(613)727-0320
FAX: (613)727-5527
AUSTRALIA
2046
VSI Electronics Pty. Limited
16 Dickson Ave.
Artarmon, NSW
2064 Australia
(02) 439-4655
TLX: AA22846
FAX: (02)439-6435
BRAZIL
2070
Round Valley Services
478 West 650 South
Orem, UT 84058
(801)224-5773
FAX: (801)375-6880
NEW ZEALAND
2050
VSI Electronics, (N.Z.) Ltd.
Private Bag, Newmarket
Auckland, New Zealand
~a9~~6~340
FAX: (9) 593694
INDUSTRIAL DISTRIBUTORS - UNITED STATES/CANADA
The lollowing Distributors stock Rockwell modem, controller and high speed telecommunication products, If there is no distributor location close to
you, call the nearest Rockwell Semiconductor Products Division sales representative,
ALABAMA
1000
Hamilton/Avnet Electronics
4940 Research Dr. N.W.
Huntsville, AL 35805
(205) 837-7210
TWX: 810726-2162
1001
Quality Components
4900 University Sq., Sle. 20
Huntsville, AL 3581 6
(205) 830-1881
1188
Marshall Industries
3313 Memorial Parkway South
Huntsville, AL 35801
(205) 881-9235
1194
Marshall Industries
336 Los Caches St.
Milpitas, CA 95035
(408) 942-4600
1196
Hamllton/Avnet Electronics
3002 East G. Street
Ontario, CA 91764
(714) 989-4602
1172
Marshall Industries
3039 Kilgore Avenue, #140
Rancho Cordova, CA 95670
(916) 635-9700
1182
Marshall Industries
20 Sterling Dr.
Barnes Ind. Park, N.
Post Office Box 200
Wallingford, CT 06492
(203) 265-3822
1008
Alma Electronics
31 Village Street
Wallingford, CT 06492
(203) 269-6801
FLORIDA
1092
Hamllton/Avnet Electronics
4103 Northgate Blvd.
Sacramento, CA 95834
(916)925-2216
1013
Hamilton/Avnet Electronics
6801 N.W. 15th Way
Fort Lauderdale, FL 33309
(305) 971-2900
TWX: 510 956-3097
1007
Hamilton/Avnet Electronics
4545 View ridge Ave.
San Diego, CA 92123
(619) 571-7510
TWX:910335-1216
1186
Marshall Industries
2700 W. Cypress Creek
Suite Cl06
Ft. Lauderdale, FL 33309
(305) 977-4880
1173
Marshall Industries
10105 Carroll Canyon Rd.
San Diego, CA 92131
(619) 578-9600
Reptron
3320 N.W. 53rd Street
Ft. Lauderdale, FL 33309
(305) 735-1112
FAX: (305) 735-1121
1174
Zeus
1580 Old Oakland Rd., Sle. 205
SanJose,CA95131
(408) 998-5121
1165
Marshall Industries
4205 34th Street, S.w.
Orlando, FL 32811
(305) 841-1878
1158
Marshall Industries
9710 De Soto Avenue
Chatsworth, CA 91311
(818)407-4100
1178
Western Microtechnology Inc.
12900 Saratoga Avenue
Saratoga, CA 95070
(408) 725-1660
FAX: (408) 255-6491
TWX: 910338-0013
1066
Zeus
1750 West Broadway
Suite 114
Ovievo, FL 32765
(305) 365-3000
1149
Hamllton/Avnet
9650 De Soto Ave.
Chatsworth, CA 91311
(818) 700-6500
1008
Hamilton/Avnet Electronics
1175 Bordeaux Dr.
Sunnyvale, CA 94086
(408) 743-3355
TWX: 910339-9332
1004
Avnet Electronics
350 McCormick
Costa Mesa, CA 92626
(714) 754-6111
TWX: 910595-2638
1152
Image Electronics
1342 Bell Ave.
Tustin, CA 92680
(714) 259-0900
ARIZONA
1002
Hamilton/Avnet Electronics
505 So. Madison Dr.
Tempe, AZ 85281
(602) 231-5100
TWX: 910 950-0077
1167
Marshall Industries
9830 So. 51 st Street
SUite B121
Phoemx, AZ 85044
(602) 496-0290
CALIFORNIA
1157
Zeus West Anaheim
1130 Hawk Circle
Anaheim, CA 92807
(714) 632-6880
1005
Hamilton Electro Sales
3170 Pullman 51.
Costa Mesa, CA 92626
(714) 641-4100
1003
Hamilton Electro Sales
10950 Washington Blvd.
Culver City, CA 90230
(213) 558-2000
(213) 558-2441 (I nt'l Group)
1159
Marshall Industries
9674 Telstar Avenue
EI Monte, CA 91731
(818) 459-5500
COLORADO
1185
Marshall Industries
12351 N. Grant
Thornton, CO 80241
(303) 451-8444
FAX: (303) 457-2899
1009
Hamllton/Avnet Electronics
8765 E. Orchard Rd., Ste. 708
Englewood, CO 80111
(303) 740-1000
TWX: 910 935-0787
CONNECTICUT
1155
Hamilton Electro Sales
1361-8 West 190th St.
Gardena, CA 90248
(213) 217-6748
1011
Hamilton/Avnet Electronics
Commerce Industrial Park
Commerce Dr.
Danbury, CT 0681 0
(203) 797-2800
TWX: 71 0 456-9974
1190
Marshall Industries
1 Morgan Avenue
Irvine, CA 92710
(714) 859-5050
1012
J.V. Electronics
690 Main SI.
East Haven, CT 0651 2
(203) 469-2321
1014
Hamilton/Avnet Electronics
3197 Tech Dr. North
51. Petersburg, FL 33702
(813) 229-7010
TWX: 810863-0374
1018
Marshall Industries
2840 Scherer Dr.
Suite410
St. Petersburg, FL 33702
(813) 576-1399
1019
Reptron
14501 McCormick Dr.
Tampa, FL 33625
(813) 855-4656
1146
Hamilton/Avnet Electronics
6947 University Blvd.
Winter Park, FL 32792
(305) 628-3888
Quality Components
(800) 241-0037
GEORGIA
1015
Hamilton/Avnet Electronics
58250 Peachtree Corner E.
Norcross, GA 30092
(404) 447-7500
TWX: 810 776-0432
1176
Marshall Industries
4350-J International Blvd.
Norcross, GA 30093
(404) 923-5750
FAX: (404) 923-2743
A-3
1174
Quality Components
6145 Northbelt Pkwy., Ste. B
Norcross, GA 30071
(404) 449-9508
FAX: (404) 449-0275
ILLINOIS
1016
Advent Electronics
7110-16 N. Lyndon St.
Rosemont. IL 60018
(312) 298-4210
1017
Hamllton/Avnet Electronics
1130 Thorndale Ave.
Bensenville, IL 60106
(312) 860-8522
TWX: 910 227-0060
1180
Marshall Industries
1261 Wiley Road, #F
Schaumburg, IL 60195
(312) 490-01 55
INDIANA
1036
Hamilton/Avnet Electronics
485 Gradle Dr.
Carmel, IN 46032
(317) 844-9333
TWX: 810 260-3966
1035
Advent Electronics
8446 MoJler Rd.
indianapolis, IN 46268
(317) 872-491 0
1189
Marshall Industries
6990 Corporate Dr.
Indianapolis, IN 46278
(317) 297-0483
IOWA
1086
Advent Electronics
682 58th Ave. Ct. S.W.
Cedar Rapids, IA 52404
(319) 363-0221
1085
Hamilton/Avnet
915 33rd Ave., S.W.
Cedar Rapids, IA 52404
(319) 362-4757
KANSAS
1191
Marshall Industries
8321 Melrose Dr.
Lenexa, KS 66214
(913)492-3121
1037
Hamllton/Avnet EI~ctronlcs
9219 Quivira Rd.
Overland, KS 66215
(913) 888-8900
TWX: 910 743-0005
MARYLAND
1039
Hamllton/Avnet Electronics
6822 Oak Hall Ln.
Columbia, MD 21045
(301) 995-3550
TWX: 710 862-1861
1040
Zeus
8930A Rt. 108
Columbia, MD 20145
(301)997-1118
1161
Marshall Industries
6445 Helgerman Ct.
Gaithersburg, MO 20677
(301) 640-9450
1075
Alma Electronics Corp.
8502 Dakota Dr.
Gaithersburg, MD 20877
(301) 670-0090
MASSACHUSETTS
1109
Alma Electronics
60 Shawmut Rd.
Canton, MA02021~1410
(617)621-1420
Zeus
420 Marrett Road
Lexington, MA 02173
(617) 663-6600
1115
MISSOURI
1046
Hamllton/Avnet Electronics
13743 Shoreline Ct.
(315) 451-2371
444 E. Industrial Park Dr.
Manchester, NH 03103
1021
Zeus
(603) 624-9400
1116
Marshall Industries
Fairfield, NJ 07006
(201) 575-3390
TWX: 710734-4366
MICHIGAN
1043
1166
Marshall Industries
1077
Hamllton/Avnet Electronics
2215 29th St., S.E. A-5
Grand Rapids, MI49508
(609) 766-6767
1162
Marshall Industries
31067 Schoolcraft
Livonia, MI 48150
1027
Hamilton/Avnet Electronics
3510 Spring Forest Rd.
Raleigh, NC 27604
(919) 676-0610
TWX: 510 926-1636
1170
Marshall Industries
5221 North Blvd.
Raleigh, NC 27604
(919) 676-9662
1173
Quality Components
2940-15 Trawick Rd.
Raleigh, NC 27604
(919) 676-7767
1021
(313) 525-2700
MINNESOTA
1127
Voyager Electronics Corp.
7163 Commerce Circle West
Fridley, MN 55432
(612)571-7766
1047
Hamllton/Avnet Electronics
10300 Bren Rd. E.
1026
Hamllton/Avnet Electronics
4588 Emery Industrial Parkway
Cleveland, OH 44126
(216) 631-3500
TWX: 61 0 427-9452
NEW MEXICO
1022
Hamilton/Avnet Electronics
1029
2524 Baylor Dr. S.E.
Hamllton/Avnet Electronics
954 Senate Dr.
Albuquerque, NM 87106
P.O. Box610
Day10n, OH 45459
(513) 439-6700
TWX: 610 450-2531
(505) 765-1500
TWX: 910969-0614
Minnetonka, MN 55343
NEW YORK
Marshall Industries
6212 Executive Blvd.
(516) 293-2710
FAX: (516) 293-2707
(51 6) 231-9600
TWX: 510 224-6166
129 Brown St.
Johnson City, NY 13790
1037
Hamilton/Avnet
2600 Liberty Ave., Bldg. E
Pittsburgh, PA 15222
(412) 261-4150
1166
Marshall Industries
701 Alpha Drive
Suite 240
Pittsburgh, PA 15236
(412) 963-0441
TEXAS
Quality Components, Inc.
4257 Kellway Circle
Addison, TX 75001
(214) 733-4300
TWX: 910 660-5459
1050
Hamllton/Avnet Electronics
1807-AW. Braker Lane
Austin, TX 76756
(512) 637-6911
TWX: 910 674-1319
1177
Marshall Industries
8504 Cross Park Dr.
Austin, TX 76754
(512) 637-1991
1112
Austin, TX 76756
(512) 635-0220
TLX: 324930
1133
(614) 662-7004
275 Oser Ave.
Hauppauge, LI, NY 11788
1193
Marshall Industries
Philadelphia, PA 19114
(215) 696-4000
1161
Hamllton/Avnet Electronics
777 Brooksedge Blvd.
Westerville, OH 43081
1192
Marshall Industries
1163
Marshall Industries
Almo Electronics
9815 Roosevelt Blvd.
Quality Components, Inc.
2120-M Baker Ln.
30700 Bainbridge Rd.
Unit A
Solon, OH 44139
(216) 246-1766
1025
3800 Annapolis In.
PENNSYLVANIA
Dayton, OH 45424
(51 3) 236-6066
Marshall Industries
Hamilton/Avnet Electronics
933 Motor Parkway
Hauppauge, LI, NY 11787
(516) 273-2424
Plymouth, MN 55441
(612) 559-2211
1164
1114
Semlspeclallsts of America
105 Baylis Road
Melville, NY 11747
(612) 932-0600
TWX: 910 576-2720
(503) 635-6157
TWX: 910455-6179
1110
OHIO
(313) 525-5650
Reptron
34403 Glendale Rd.
Post Office Box 2768
Livonia, MI48150
6024 S.w. Jean Rd.
Bldg. C, Suite 10
1034
NORTH CAROLINA
1126
1044
(313) 522-4700
TWX: 610 242-6775
(315)437-2641
(609) 234-9100
(616) 243-6605
TWX: 610 273-6921
1032
Hamilton/Avnet Electronics
Lake Oswego, OR 97034
1023
Hamllton/Avnet Electronics
103 Twin Oaks Dr.
Syracuse, NY 13206
158 Gaither Dr.
Mt. Laurel, NJ 08054
General Components Inc.
245-0 Clifton Ave.
West Berlin, NJ 08091
Hamllton/Avnet Electronics
32487 Schoolcraft Rd.
Livonia, MI 48150
(716) 235-7620
101 Fairfield Rd.
Advent Electronics
24713 Crestview Ct.
Farmington Hills, MI48018
(313)477-1650
1169
Marshall Industries
8333 S.W. Cirrus Drive
Beaverton, OR 97005
1280 Scottsville Rd.
Rochester, NY 14624
1164
Marshall Industries
Fairfield, NJ 07006
(201) 662-0320
(503) 629-2062
(503) 644-5050
Hamilton/Avnet Electronics
1 Keystone Ave., Bldg. 36
(617) 366-2400
1150
Western Micro Technology Inc.
13770 S.w. 24th
100 Midland Avenue
Port Chester, NY 10573
1171
Marshall Industries
(201) 639-0077
Hamllton/Avnet Electronics
10 Industrial Rd.
OREGON
(914) 937-7400
FAX: (914) 937-2553
1156
Pan American Electronics Inc.
59 Main Street
Bloomingdale, NH 07403
1076
Tulsa, OK 74146
(916) 664-6612
Beaverton. OR 97005
NEW JERSEY
Cherry Hili, NJ 06003
(609) 424-0110
TWX: 710 940-0262
(617) 656-0610
7453 Morgan
Liverpool, NY 13088
1049
Hamllton/Avnet Electronics
(617) 531-7430
33 Upton Dr.
Wilmington, MA 01887
1022
Future Electronics
NEW HAMPSHIRE
1020
Future Electronics
133 Flanders Rd.
Westboro, MA 01581
1113
Quality Components, Inc.
3158 So. 10Bth East Avenue
Suite 274
(716) 475-9140
TWX: 510 253-5470
Earth City, MO 63045
(314)344-1200
TWX: 910762-0664
Hamllton/Avnet
10-0 Centennial Dr.
Peabody, MA 01 960
1064
1024
Hamllton/Avnet Electronics
333 Metro Park
Rochester, NY 14623
1163
Marshall Industries
2045 Chenault
Carrollton, TX 75006
(214) 233-5200
1167
Marshall Industries
7250 Langtry
Houston, TX 77040
OKLAHOMA
1117
Hamllton/Avnet Electronics
12121 E. 51st Street
Suite.l02A
Tulsa, OK 74146
(916) 252-7297
(607) 796-1611
A-4
(713) 695-9200
1052
Hamllton/Avnet Electronics
2111 W. Walnut Hill Ln.
Irving (Dalias), TX 75062
(214)550-7755
TWX: 910 660-5929
1051
Zeus
1800 N. Glenville Dr.
Suite 120
Richardson, TX 75081
(214) 783·7010
1053
Hamilton/Avnet Electronic
4850 Wnght Rd.
Stafford, TX 77477
(713) 240·7898
1111
Quality Components, Inc.
1005 I ndustrial Blvd.
Sugarland, TX 77478
(713) 240·2255
UTAH
1059
Hamilton/Avnet Electronics
1585 West 2100 South
Salt Lake City. UT 84119
(801) 972·2800
TWX:910925·4017
1058
Marshall Industries
466 Lawndale Dr., Ste. C
Salt Lake City, UT 84115
(801)485,1551
WASHINGTON
1060
Hamilton/Avnet Electronics
14212N.E.21st5t
Bellevue, WA 98007
(206) 643·3950
TWX: 910443·2469
1175
Marshall Industries
14102 N.E. 21st Street
Bellevue, WA 98007
(206) 747·9100
1149
Western Micro Technology Inc.
14636 N.E. 95th Street
Redmond, WA 98052
(206) 881·6737
WISCONSIN
1061
Hamllton/Avnet Electronics
2975 Marrland Rd.
New Berlin, WI 53151
(414) 784·4510
TWX: 91 0 262·1182
1062
Marshall Industries
235 N. Executive Dr., #305
Brookfield, WI 53005
(414) 797·8400
(800) 472·2420
CANADA
1091
Hamilton/Avnet Electronics
281621stSI.N.E.
Calgary, Alberta
Canada T2E 622
(403) 250·3586
TWX: 03·827642
1092
ITT Multlcomponents
11680 170SI.
Edmonton, Alberta
Canada T5S 1J7
(403) 451·4001
1093
ITT Multlcomponents
3455 Gardner Court
Burnaby. British Columbia
Vancouver, Canada V5G 4J7
(604) 291·8866
TLW: 04·356533
1072
Future Electronics, Inc.
1695 Boundary Rd.
Vancouver, British Columbia
Canada V5K 4X7
(604) 294·1166
TLX: 04·354744
FAX: (604) 294·1206
1073
ITT Multlcomponents
760 Century St.
Winnipeg, Manitoba
Canada R3H OMl
(204) 786·8401
1074
ITT Multlcomponents
15 Mount Royal Blvd.
P.O. Box 621
Moncton, New Brunswick
Canada El C aN6
(506) 857·8001
1075
ITT Multicomponents
#103-11 Morris Dr.
Burnside Industrial Park
Dartmouth, Nova Scotia
Canada B3B 1 M2
(902) 465·2350
1076
ITT Multlcomponents
300 N. Rivermede Rd.
Concord, Ontario
Canada L4K 224
(416)736'1144
TLX: 06·964814
FAX: (416) 736·4831
1081
Future Electronics Inc.
82 Saint Regis Crescent North
Downsview, Ontario
Canada M3J 123
(416) 638·4771
TWX: 610 491·1470
FAX: (416) 638·2936
1063
Hamilton/Avnet Electronics
6845 Rexwood Rd., Units 3-5
Mississauga, Ontario
Canada L4V 1 R2
(416) 677·7432
1064
Harnilton/Avnet Electronics
190 Colonnade Rd.
Nepean, Ontario
Canada K2E 7J5
(613) 226·1700
TWX: 053·4971
A-5
1070
Future Electronics Inc.
Baxter Center
1050 Baxter Rd.
Ottawa, Ontario
Canada K2C 3P2
(613) 820·8313
TWX: 610 563·1697
FAX: (613) 820·3271
1080
Future Electronics Inc.
237 Hymus Blvd.
Pointe Claire, Quebec
Canada H9R 5e?
(514) 694·7710
FAX: (514) 695·3707
TLX: 05·823554
1065
Hamilton/Avnet Electronics
2795 Halpern
St. Laurent
Montreal, Quebec
Canada H4S 1 P8
(514) 335·1000
1067
ITT Multlcomponents
2295 Halpern 51.
Ville St. Laurent, Quebec
Canada H4S 153
(514) 335·7697
TLX: 05·824138
FAX: (514) 335·9330
1068
ITT Multlcomponents
3521 8th Street E., #209
Saskatoon, Saskatchewan
Canada S7H ON5
(306) 933·2888
ROCKWELL SEMICONDUCTOR PRODUCTS SALES OFFICES -I NTERNATIONAL
You can obtain expert applications assistance, price quotations and delivery data from the Distributors and Sales Representatives listed below for Rockwell
semiconductor and telecommunication products. If there is no Rockwell distributor convenient to your country, please consider Hamilton/Avnet
International listed below.
INDIA
AFRICA
South Continental Device!>
(Ply) Ltd.
P.O. Box 56420
Pinegowkig 2123, South Africa
AUSTRIA
0226
W. MoorGESMBH
Storchengasse 1/1/1
A·1150 Wien
Austria
43 (222) 858·646
TLX: 047-135701 moor a
FAX: (43·2221615 537 151
BELGIUM
0272
Microtron
Generaal Dewittelaan 7,
2800 Mechelen
Belgium
TLX: 846-22606 mitron b
BRAZIL
Round Valley Services
R. Vitorino Carmllo, 672
CEP 01153-Barrafunda SP
(011) 825·3111
TLX: (011) 53612
Phone U.S.A.: (801) 224·5773
WEST GERMANY
4066
Semiconductor Complex Limited
Phase VIII. S.A.S. NAGAR·160059
:~~ka~,~~~i~9,
87065
TLX: 395270 LSI
0245
Unltronic GmBH
Munsterstr.338
P.O. Box 330 429
4000 Dusseldorf 30
W.Germany
(49·2111626364·67
TLX: 8586434 unid d
ISRAEL
0255
Bynet Data Communications
8-Hanechoshet St.
Ramat-Hachayal
Tel-Aviv 6971 0, Israel
TLX: 342132
FAX: (972) 3·475933
0237
Astronlc GmBH
Winzererstr.47d.
8000 Munchen 40
Munich, West Germany
(49·891309031
TLX: 5216187 a strd
ITALY
0260
Murata Elettronlca
Via Melchiorre Gioia, 66
T-20125 Milano, Italy
(39·2) 607·3786
(39·2) 688·4833
1WX: 330385
AUSTRALIA/NEW ZEALAND
4054
VSI Electronics
(Australia) Ply. Lid.
16 Dickson Avenue
Artarmon, NSW 2064 Australia
FAX: (021439·6435
TLX: AA·22846
NORWAY
0271
Satt Electronics
O.H. Bangs Vei 17
Postboks 70
1322 Hovik, Norway
(47·02) 123 600
TLX: 72559 SAn N
VSI ElectroniCs Pty. Ltd.
P.O. Box 578
Crows Nest, NSW 2065
Artarmon, Australia
(02) 439·4655
FAX: (021439·4655
TLX: AA·22846
DENMARK
0244
Micronor APS
Torvet 1
8600 Silkeborg
Denmark
(45·61816522
TLX: 63245 MICRONOR OK
FINLAND
0252
Satt Electronics
oy Hitsaajakatu 8,
P.O. BoxeS
00811, Helsinki
Finland
(358) 0·7555133
TLX: 124870 ELOYN SF
FRANCE
0222
System Contact
88, Avenue du General de Gaulle
67200 Eckbolsheim
France
Phone: (33·88) 782089
(33) 88782089
TLX: 890266 SYSCO
0259
ERN
237 rue de Fourny
78530 BUe France
(33·11 3956·0011
TLX: 698627 ERN BUC
HOLLAND
2087
Alcom Electronics BV
Esse Baan 1
Post bus 358, 2908 AJ
Capelle AID !jssel
Holland
(31-10) 4519·533
TLX: 26 160
0250
Bltronic GmBH
Dingolfingerstr. 6
0-8000 M uenchen 80, Germany
(49·89) 41 8007·0
TLX: 5212931 bit d
SPAIN
0239
ComeltaSA.
Emilio Munoz 41
ESC 1, Planta 1, Nave 1-1-2
Madrid 17, Spain
(34·1) 754·3001
TLX: 42007 CETA E
FAX: (3411754·2151
HONG KONG
2086
Tekcomp Electronics Ltd.
1702 Bank Centre
636 Nathan Rd.
Kowloon, Hong Kong
(852·31 880629
TLX: 38513 TEKHL
FAX: (852) 123·40746
SWEDEN
Betoma Component AB
Box 3005
Dalvaegen 12
17128 Solna, Sweden
(46·81 734·8300
TLX: 8126331 BETOMA S
JAPAN
0268
KS Semiconductor, Inc.
3-6-31-1 F Osaki Shinasgawaku
T141 Tokyo, Japan
(81·3) 490·0762
TLX: 2466528 AIS·J
FAX: (81·3) 495·5565
SWITZERLAND
0227
Aumann & Co. AG
Foerrllbuckstr. 150
CH-8037 Zurich
Switzerland
(4 H) 443·300
TLX: 822 966
0269
Kanematsu Semiconductor Corp.
6-' Shintomi 1 chome
Chuo-Ku, Tokyo 104, Japan
(81·3) 551·7791
TLX: 252 3798 KSC J
UNITED KINGDOM
0203
Kyokuto Boekl Kalsha, Ltd.
7th Floor, New Otemachi Bldg.
1-1, 2-chome, Otemachl, Chlyoda-ku
Tokyo, Japan
(81·3) 244·3803
TLX: J22440
FAX: (81·31246·1846
0258
R.C.S. Microsystems Ltd.
The Kings Arms
141 Uxbridge Rd.
Hampton Hill, Middlesex
RW12 1 BL. England
(011979·2204
TLX: 8951470 RCS MIC
0204
Kyokuto Boeki Kaisha, Ltd.
Rm.606
Mainichi Osaka Kalkan Kitakan
6-16 Dojima 1-chome. Kita-ku
Osaka, Japan
(06) 344·1121
TLX: clo KBK's Tokyo Office
0280
Abacus Electronics PLC
Abacus House
Bone Lane, Newbury
Berkshire, RG14 5SF, England
(0635) 30680
TLX: 849343
A-6
0266
Marubenl-Hytech Co. Ltd.
1-1, Higashi Ikebukuro
3 Chome, Toshimaku
Tokyo, Japan
(81·31989·7813
TLX: NTT 2722648 HYTEC J
0206
Matsushita Electric Trading Co.
P.O. Box 18
Trade Center, 32nd Floor
World Trade Center Bldg.
4-' Hamamatsu-cho 2-chome
Minato-ku
Tokyo 105, Japan
(81·3) 435·4552
TLX: 522·8771 METOSK J
0207
Matsushita Electric Trading Co.
Twin 21 National Tower, 32nd. Fir.
1-61, Shiromi 2-chome
Higashi-ku
Osaka 541, Japan
(06) 946·4841
TLX: 522·8771 METOSKJ
KOREA
0242
Unistandard Corp.
757-' Bang Bae-Dong
Kang-Nam Ku
Seoul, Korea
TLX: K22116 ··UNISr'
(82·2) 532·6815
SINGAPORE
0262
Dynamar International Ltd.
12, Lorong Bakar Batu
Kolam Ayer, Suite 05-11
Singapore RE 1334
7476188
TLX: 26283
TAIWAN
0213
Sertek International Inc.
3·9, 1"'2 Fir.
135-137 Sec. 2 Chien Kuo N. Road
Taipei, 10479 Taiwan, ROC
(86·21 501·0055
TLX: 13579
FAX: 025012521
THAILAND
0263
Loxley (Bangkok) Ltd.
GPO Box 214 #304
Suapah Road
Bangkok, 10501
Thailand
221·6121·30
221·9156·60
223·9066·8
TLX: LOXLEY TH81188
OTHER COUNTRIES
1006
Hamilton/Avnet Electronics
International Group
, 0950 Washington Blvd.
Culver City, CA 90230
(213) 558·2441
NOTES
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A-8
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A·9
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A-10
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A-12
Source Exif Data:
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