1987_Rockwell_Modem_Products_Data_Book 1987 Rockwell Modem Products Data Book
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MODEM PRODUCTS
DATA BOOK
Rockwell International
Semiconductor Products Division
©Rockwell International Corporation 1987
All Rights Reserved
Printed in U.S.A.
Order No.1
February, 1987
Rockwell Semiconductor Products Division is headquartered in Newport Beach, California with Field
Sales Offices located throughout the United States, Canada, Europe and the Far East. Their listings,
plus those of domestic and international representatives and distributors, appear in Appendix A.
DEFINITION OF DOCUMENT TYPES
Document Type
Product Status
Definition
Product Preview
Formative or
Development
The document type contains the general features and/or
specifications for a product in definition or development. The
features and/or specifications may change in any manner
without notice.
Product Summary
Development or
Production
This document type contains the general features and/or
specifications of a product in development or in production.
Additional information is usually available in a separate
document, not contained in this book, such as a Designer's
Guide.
Data Sheet
(Preliminary)
Sampling or
Pre-Production
This document type contains preliminary or design-to
characteristic data for a product in pre-production. Additional
and/or refined characteristic data will be released in
subsequent revisions to the document.
Data Sheet
Production
This document type contains final specification information
resulting from measured characteristics. This document type
is subject to revision if characteristics are further refined
during production.
Product Description
Production
This document type contains final specification information
resulting from measured characteristics along with additional
application aid information. This document type is subject
to revision if characteristics are further refined during
production.
Application Note
Development or
Production
This document type contains application aids in the use of
the subject product. Schematics included in an application
note are intended to convey system design concepts only.
NOTICE
Information furnished by Rockwell International Corporation is believed to be accurate and reliable. However,
no responsibility is assumed by Rockwell International for its use, nor any infringement of patents or other
rights of third parties which may result from its use. No license is granted by implication or otherwise under
any patent or patent rights of Rockwell International other than for circuitry embodied in a Rockwell product.
Rockwell International reserves the right to change circuitry at any time without notice. All documents in
this book are subject to change without notice.
TABLE OF CONTENTS
Part No./Data Book Page Index .................. .
iv
Modem ProductsSetting Standards in Connectivity .............. .
v
Product Index ........................... .
1200,2400 bps Data Modems ................ .
Product Family Overview ..................... .
R212DP Device Set Bell 212A Compatible ..... .
R212AT Device Set "AT" Command Set Bell
212A Compatible ........................... .
R1212 1200 bps Full-Duplex Modem ........... .
R2424 2400 bps Full-Duplex Modem ........... .
R201/26DP 2400/1200 bps Data Pump Modem ..
RC1212 V.22 1200 bps Modem ............... .
RC2424 V.22 bis 2400 bps Modem ............ .
RDAA Rockwell Data Access Arrangement
Module .................................... .
2
3
4800,9600, 14400 bps Data Modems ........ .
Product Family Overview ..................... .
R208/201 4800 bps Modem ................... .
R48DP/208 4800 bps Data Pump Modem ...... .
R48DP 4800 bps Data Pump Modem .......... .
R96DP 9600 bps Data Pump Modem .......... .
R96FT 9600 bps Fast Train Modem ........... .
R96FT/SC 9600 bps Fast Train Modem with
Forward Secondary Channel ....... .
R144DP V.33 Ultra High Speed Modem ........ .
R9696DP V.32 Ultra High Speed Modem ....... .
R1496MM V.33, V.32 Ultra High
Speed Modem ............................ ..
Imaging Modems ............................ .
Product Family Overview ..................... .
R24MFX 2400 bps MONOFAXTM Modem ...... .
R24BKJ 2400 bps V.26 bis Modem ............ .
R48MFX 4800 bps MONOFAX Modem. . . . . .. ..
3-51
R48PCJ 4800 bps PC Communication Modem ..
3-67
R24/48MEB Modem Evaluation Board ..
R96PCJ 9600 bps PC Communication Modem .. . 3-80
R96F 9600 bps Facsimile Modem ............. . 3-93
3-112
R96MD 9600 bps Facsimile Modem ......... .
R144HD 14400 bps Half-Duplex Modem ....... . 3-130
3-144
R96MFX 9600 bps MONOFAX Modem ..
vii
1-1
1-2
1-3
1-5
1-7
1-36
1-65
1-82
1-84
4
Custom and Private Label Modems .......... .
Product Line Overview ........................ .
RG224EC 2400 bps Private Label Modem ...... .
RG208 4800 bps Private Label Modem ........ .
RGV29FT 9600 bps Private Label Modem ..
4-1
4-2
4-3
4-5
4-7
5
Application Notes ........................... .
An R6500/11-R2424 Intelligent Modem Design .. .
Interfacing Rockwell Signal Processor-Based
Modems to an Apple lie Computer ........... .
240011200/300 bps International Modem Design.
Quality of Received Data for Signal
Processor-Based Modems .................. .
R2424 and R1212 Modems Auto Dial and Tone
Detection ................................. ..
8088 Microprocessor to R1212/R2424 Modem
Interface .................................. .
High Speed Modems Filter Characteristics
R96F Modem Tone Detector Filter Tuning.
R96F Modem Recommended Receive
Sequence for Group 2 Facsimile ...... .
DTMF Dialing for R24MFX, R48MFX, R24BKJ,
or R48BKJ .......................... .
5-1
5-3
1-86
2-1
2-2
2-3
2-25
2-47
2-68
2-90
2-105
2-120
2-122
2-124
3-1
3-2
3-3
3-19
3-35
A
iii
SPD Regional Offices and U.S./Canada
Sales Reps....
. ............... .
SPD Industrial Distributers ............. .
SPD International Distributers/Sales Reps ...... .
Notes .......................... .
5-46
5-50
5-83
5-104
5-114
5-119
5-121
5-127
5-130
A-1
A-3
A-5
A-6
PART NO.lDATA BOOK PAGE INDEX
Part No.lDescription
Page
1-7
R1212 1200 bps Full-Duplex Modem.,..............
R144DP V.33 Ultra High Speed Modem ............. 2-120
R144HD 14400 bps Half-Duplex Modem.... ..
3-130
R1496MM V.33, V.32 Ultra High Speed Modem ..... 2-124
R201/26DP 2400/1200 bps Data Pump Modem.. .... 1-65
R208/201 4800 bps Modem. . . . . . . . . . . . . . . . . . . . . . . .
2-3
R212AT Device Set "AT" Command Set Bell
212A Compatible. . . . . . . . . . . . . .. . . . . . . . . .. . . . . .
1-5
R212DP Device Set Bell 212A Compatible...... ...
1-3
R24/48MEB Modem Evaluation Board .............. 3-67
1-36
R2424 2400 bps Full-Duplex Modem. . . . . . . . . . . .
R24BKJ 2400 bps V.26 bis Modem..... .. ...... .... 3-19
3-3
R24MFX 2400 bps MONOFAX Modem. . . . . . . . . . . . . .
R48DP 4800 bps Data Pump Modem........... .... 2-47
R48DP/208 4800 bps Data Pump Modem. . . .
2-25
R48MFX 4800 bps MONOFAX Modem. . . . . . . . . . . . . . 3-35
IV
Part No.lDescription
Page
R48PCJ 4800 bps PC Communication Modem.
R9696DP V.32 Ultra High Speed Modem ..
R96DP 9600 bps Data Pump Modem .............. .
R96F 9600 bps Facsimile Modem ................. .
R96FT 9600 bps Fast Train Modem ............. .
R96FT/SC 9600 bps Fast Train Modem with
Forward Secondary Channel ................. .
R96MD 9600 bps Facsimile Modem ..
R96MFX 9600 bps MONOFAX Modem. . . . .. . ..... .
R96PCJ 9600 bps PC Communication Modem ... .
RC1212 V.22 1200 bps Modem ................... .
RC2424 V.22 bis 2400 bps Modem ................ .
RDAA Rockwell Data Access Arrangement Module ..
RG208 4800 bps Private Label Modem ......... .
RG224EC 2400 bps Private Label Modem .. .
RGV29FT 9600 bps Private Label Modem ...... .
3-51
2-122
2-68
3-93
2-90
2-105
3-112
3-144
3-80
1-82
1-84
1-86
4-5
4-3
4-7
Modem Products
Setting Standards in Connectivity
Rockwell International's OEM modem products offer
a highly reliable, cost effective solution for your modem
needs. Rockwell has been a driving force behind data
communications technology for over 30 years. In the early
1950's we introduced our first modem product. We later
pioneered the development of many digital signal processing
techniques such as automatic adaptive equalization, digital
filtering carrier recovery, phase lock loop and quadrature
amplitude modulation. In addition to advanced signal
processing technology, Rockwell engineers have developed
sophisticated analog filtering techniques.
Today, Rockwell is a generation ahead of our competition
with the first fully integrated VLSI modems. Whether
communicating at 1200, 2400, 4800, 9600 or 14400 bps,
we provide products for any dial-up or leased line modem
requirement. High speed network control and multiplexers,
personal computer and terminals, standalone and custom
modems, facsimile and desktop publishing equipment are
samples of end user equipment using Rockwell modems.
With the confidence borne of many years experience in the
business, Rockwell offers a full five year warranty on all its
standard modem modules and components. This guarantee to
our customers reinforces Rockwell's commitment to quality and
reliability.
Rockwell is the world's largest supplier of original equipment
manufacturer (OEM) modems. We are uniquely positioned to
provide the highest quality and performance at competitive
prices. With extensive pre-and post-sale support from
experienced application engineers, dOing business with
Rockwell combines the advantages of a large, stable supplier
with the responsiveness and innovation of a small
entrepreneurial firm.
v
MONOFAX is a trademark of Rockwell International.
Microsoft is a registered trademark of Microsoft CorporatIon.
H P and LaserJet are trademarks of Hewlett Packard.
Smartcom II IS a trademark of Hayes MIcrocomputer Products, Inc.
Microcom Network Protocol and MNP are trademarks of Microcom, Inc
CROSSTALK is a registered trademark of DIgItal Communications AssocIates, Inc
VI
PRODUCT INDEX
1200,2400 bps Data Modems
4800,9600,14400 bps Data Modems
fJ
Imaging Modems
II
Custom and Private Label Modems
11
Applications Notes
vii
o
SECTION 1
1200,2400 bps DATA MODEMS
Product Family Overview ...................................................... .
R212DP Device Set Bell 212A Compatible ...................................... .
R212AT Device Set "AT" Command Set Bell 212A Compatible ................... .
R1212 1200 bps Full-Duplex Modem ............................................ .
R2424 2400 bps Full-Duplex Modem ............................................ .
R201/26DP 2400/1200 bps Data Pump Modem .................................. .
RC1212 V.22 1200 bps Modem ................................................ .
RC2424 V.22 bis 2400 bps Modem ............................................. .
RDM Rockwell Data Access Arrangement Module ............................... .
1-1
Page
1-2
1-3
1-5
1-7
1-36
1-65
1-82
1-84
1-86
1200,2400 bps DATA MODEMS
Experience Makes a Difference
peripheral device thus speeding design time. Also, the scratch
pad RAM allows the modem to be easily controlled and
configured for a wide variety of applications in markets
worldwide.
Rockwell also maximizes the design option to develop a
single host board and, by plugging in different Rockwell device
sets or modules, have a variety of full- or half-duplex, 1200 or
2400 bps modems. Rockwell pioneered this concept with Eurosized modules incorporating DIN connectors. Now, the next
generation form factor is available - a module only seven
inches square with dual-in-line pins. This DIP module can be
handled as any DIP-type integrated circuit during board
assembly and wave soldering. Its small size is ideal for
extremely dense designs, such as "112 card" modems for
personal computers. What's more, all medium speed DIP
module products are pin compatible and have the same
external dimensions. System designers thereby have a
smooth, economical upgrade path from the current R1212 and
R2424 products to the new RC1212 and RC2424 families.
Rockwell's line of 1200 and 2400 bit-per-second (bps)
modem products can easily be incorporated into products
requiring high performance, quality and reliability while
maintaining a competitive cost advantage. Whether the
modem application is internal to a personal computer, or for
installation in remote monitoring equipment, Rockwell has a
product with the features, form factor and price to meet your
requirement.
With the medium speed modem market moving 50 quickly,
time to market is critical. For designers not wishing to develop
a custom product, Rockwell offers a Bell 212A and 103
compatible, two-chip set modem with an RS-232-C interface. It
also includes the standard ':A.T" command set in firmware. With
minimal external components, such as the FCC-required
phone line protection circuitry, a complete modem can be
developed within a few weeks. For product designs requiring
more flexibility and control, Rockwell offers a standard
microprocessor bus (8088 compatible) interface along with
user accessible, dual port scratch pad RAM. Together, they
allow you to treat the Rockwell modem as a microprocessor
Model
Data Speed
(bps)
PSTNI
Leased
Line
R212AT
1200,0-300
P
2WFD
Async
Bell 212A, 103
':A.T" Command Set
R212DP
1200,0-300
P
2WFD
Async
Bell 212A, 103
R1212
1200,600,
0-300
P/L
2WFD
Sync, Async
CCITT V.22 AlB;
Bell 212A, 103
R2424
2400,1200,
600,0-300
P/L
2WFD
Sync, Async
CCITT V.22 bis, V.22 AlB;
Bell 212A, 103
R201/26DP
2400, 1200
P/L
2WHD,4WFD
Sync
CCITT V.26, V.26 bis;
Bell 201B/C
RC1212
1200,600,
0-300
P/L
2WFD
Sync, Async
CCITT V.22 AlB, V.21; V.23;
Bell 212A, 103
RC2424
2400,1200,
600,0-300
P/L
2WFD
Sync, Async
CCITT V.22 bis, V.22 AlB,
V.21, V.23;
Bell 212A, 103
2/4-Wire
Half/Full-Duplex
1-2
Sync/Async
Compliance
R212DP/DS and R212DP/EB
'1'
Rockwell
R212DP
Modem Device Set
Bell 212A Compatible
INTRODUCTION
FEATURES
The R212DP/DS Data Pump device set is a high performance
1200/300 bps modem. Using state-of-the-art VLSI technology,
the R212DP provides the entire modulation/demodulation
process, high and low band filtering, and complete auto dialing
function in only two devices.
• 2 Device Implementation
- R8200 Modulator/Demodulator
- 10468 Integrated Analog
D
• Bell 212A and 103 Compatible (2-Wire Full-Duplex)
- Asynchronous
1200 bps DPSK ( + 1%, - 2.5%)
0-300 bps FSK
Auto Fallback, Answer Mode
The R212DP is ideal for data transmission over the 2-wire dial-up
network. Bell 212A and 103 compatible, the R212DP can handle
virtually all applications for full-duplex 1200 bps and 0 to 300 bps
asynchronous data transmission over the public switched
telephone network (PSTN).
• DTE Interface
- Functionally: RS-232-C Compatible
- Electrically: TTL
The RS-232-C compatible interface integrates easily into a personal computer, box modem, terminal or any other communications product. The added feature of an integral asynchronous
serial auto dialer capable of dialing with DTMF tones or pulses
from its 40-byte character buffer offers the user added flexibility
in creating a 1200 bps modem customized for specific packaging
and functional requirements.
• Auto/Manual Answer
• Auto/Manual Dial
- DTMF or Pulses
- 0-9 # *, T P CR (ASCII)
- 40-Byte Character Buffer
An R212DP/EB Evaluation Board is also available to aid modem
system design and evaluation. Included on the printed circuit
board are the R212DP/DS modem device set, RS-232-C connector, power connector, an RJ-ll phone jack, six LED indicators, and four configuration switches. The evaluation board
comes with an in-depth R212DP Device Set Designer's Guide
(Order No. 678) and a wall-mount power supply. All that is
required to use the R212DP/EB is an RS-232-C cable connected
to a terminal or computer, and a phone cord.
•
10-Bit Character Length
•
Break Generation/Detection
• Send/Receive Space Disconnect
• Automatic Adaptive Equalizer
• Analog Loopback
- 0 to 300 bps, 1200 bps
•
Packaging Options
- 40-pin Plastic DIP
- 44-pin PLCC
40-PIN DIP
44-PIN PLCC
R212DP/DS Modem Device Set
Document No. 29220N77
Product Summary
1-3
Order No. 677
Rev. 2, February 1987
Data Pump Modem Device Set
R212DP
+5V
+5V
DTR
DCD
-5V
'
::=:J
1XD~
--<
iii __ ...i
RxD _
CH--_
Ci -
--;
10468-XX
R8200·XX
OH--_
ORGIANS-+AL-_
}
TO
LINE
INTERFACE
o
INTEGRATED
ANALOG
DEVICE
MODULATORI
DEMODULATOR
DEVICE
R212DPIDS Modem Device Set Interface Diagram
SPECIFICATIONS
Environmental
Power Consumption
Temperature: Operating
to 70°C
Storage - 55°C to + 150°C
Relative Humidity: Up to 90% noncondensing, or a wet bulb
temperature up to 35 o e, whichever is less.
ooe
+5 Vdc ±5% <300 mA
-5 Vdc ±5% <40 mA
600 mW (typical)
1-4
R212AT/DS and R212AT/EB
'1'
R212AT Modem Device Set
"AT" Command Set
Bell 212A Compatible
Rockwell
INTRODUCTION
FEATURES
The R212ATIDS ("AT" Command Set Compatible) device set
is a high performance 1200/300 bps modem. Using state-of-theart VLSI technology, the R212AT provides the entire modulation/
demodulation process, high and low band filtering, and an
enhanced "AT" Command Set in only two devices.
• 2 Device Implementation
- R8203 Modulator/Demodulator
- 10468 Integrated Analog
• Bell 212A and 103 Compatible (2-Wire Full-Duplex)
- 1200 bps DPSK (+ 1%, - 2.5%) asynchronous
- 0-300 bps FSK asynchronous
- Auto Fallback, Answer Mode
The R212AT is ideal for data transmission over the 2-wire dial-up
network. Bell 212A and 103 compatible, the R212ATcan handle
virtually all applications for full-duplex 1200 bps and 0 to 300 bps
asynchronous data transmission over the public switched
telephone network (PSTN).
• Auto/Manual Answer
The RS-232-C compatible interface integrates easily into a personal computer, box modem, terminal or any other communications product. The added features of the enhanced "AT"
Command Set offer the user added flexibility in creating a
1200 bps modem customized for specific packaging and functional requirements. The R212AT can be readily used with
industry standard communication software packages.
• Auto/Manual Dial
• "AT" Command Set (see reverse side)
An R212AT/EB Evaluation Board is also available to aid modem
system design and evaluation. Included on the printed circuit
board are the R212AT/DS modem device set, RS-232-C connector, power connector, two RJ-ll phone jacks, 11 LED indicators, four configuration switches, and a speaker with volume
control. The evaluation board comes with a detailed R212AT
Device Set Designer's Guide (Order No. 686), and a wall-mount
power supply. All that is required to use the R212ATlEB is an
RS-232-C cable connected to a terminal or computer, and a
phone cord.
•
DTE Interface
- Functionally: RS-232-C Compatible
- Electrically: TTL
•
Data Format
- 7 Data Bits; 1 or 2 Stop Bits; Even, Odd, or Fixed Parity
- 8 Data Bits; 1 or 2 Stop Bits; No Parity
• Automatic Adaptive Equalizer
•
Packaging Options
- 40-pin Plastic DIP
- 44-pin PLCC
40-PIN DIP
44-PIN PLCC
R212AT/DS Modem Device Set
Document No. 29220N83
Product Summary
1-5
-----
--
-
-----
Order No. 683
Rev. 2, February 1987
D
"AT" Compatible Modem Device Set
R212AT
R212AT "AT" Command Set
Command
AT
A/
A
D
R
T
P
Sr?
Function
Command
Attention Code
Repeat Last Command
Answer
Dial
Reverse Dial
Tone Dial
Pulse Dial
Read Register
Sr=n
V
;
E
Function
Command
Set Register
Verbal/Numeric
Result Code
Pause
Return to Command
State After Dialing
Echo On/Off
H
I
M
0
0
Z
+++
+5V
+5V
-5V
DSR
DTR
DCD
TxD
RxD
Ai
RB203-XX
1046B-XX
Ci
MR.....AA
SPEAKER ON . . . . . -
Function
On/Off Hook
Returns Product Code
Speaker On/Off
On Line
Ouiet On/Off
Reset
Escape Code
}
TO
LINE
INTERFACE
o
MODULATOR/
DEMODULATOR
DEVICE
INTEGRATED
ANALOG
DEVICE
R212AT/DS Modem Device Set Interface Diagram
SPECIFICATIONS
Environmental
Power Consumption
Temperature: Operating ooe to 70°C
Storage - 55°C to + 150°C
Relative Humidity: Up to 90% noncondensing, or a wet bulb
temperature up to 35°C, whichever is less.
+5 Vdc ±5% <300 rnA
-5 Vdc ±5% <40 rnA
600 mW (typical)
1-6
R1212
Integral Modems
'1'
Rockwell
R1212
1200 bps Full-Duplex Modem
INTRODUCTION
FEATURES
The Rockwell R1212 is a high performance full-duplex 1200 bps
modem. Using state-of-the-art VLSI and signal processing technology, the R1212 provides enhanced performance and reliability. The modem is assembled as a small module with a DIN connector (R1212M amd R1212DC) or a new, smaller module (seven
square inches) with a dual-in-line pin (DIP) interface.
•
•
•
•
•
Being CCITI V.22 A, B compatible, as well as Be1l212A and 103
compatible, the R1212 fits most applications for full-duplex
1200 bps (synchronous and asynchronous) and 0 to 300 bps
asynchronous data transmission over the general switched telephone network, and over point-to-point leased lines.
•
•
•
The dlrect-connect, auto dial/answer features are specifically
designed for remote and central site computer applications. The
bus interface allows easy integration into a personal computer,
box modem, microcomputer, terminal or any other communications product that demands the utmost in reliability and
performance.
•
•
•
•
•
The R12121DM, with its small form factor and DIP connection,
can be automatically installed and soldered onto a host module.
Its small size is ideal for internal "1/2-card" PC modem applications. Moreover, the R12121DM is pin and firmware compatible
with the R2424/DM and pin compatible with Rockwell's next generation of medium speed modems, the RC2424 and RC1212.
CCITT V.22 A, B Compatible
Bell 212A and 103 Compatible
Synchronous: 1200 bps, 600bps ±0.01%
Asynchronous: 1200 bps, 600 bps + 1%, - 2.50/0,
0-300 bps
- Character Length 8, 9, 10, or 11 bits
DTE Interface
- Functional: CCITI V.24 (RS-232-C) (Data/Control) and
Microprocessor Bus (Data/Configuration/Control)
- Electrical: TIL Compatible
2-wire Full-Duplex Operation
Adaptive and Fixed Compromise Equalization
Test Configurations:
- Local Analog Loopback
- Remote Digital Loopback
- Self Test
Auto/Manual Answer
Auto/Manual Dial-DTMF Tone or Pulse Dial
Power Consumption: 2.3 Watts Typical
Power Requirements: + 5 Vdc, ± 12 Vdc
Three Functional Configurations:
- R1212DC (Direct Connect): DIN connector module with
FCC approved DAA Part 68 Interface
- R1212M: DIN connector module without DAA
- R12121DM: DIP connection module without DAA
R1212/DM Modem
R1212M Modem
Document No. 29200N10
Data Sheet
1-7
Order No. MD10
Rev. 4, February 1987
o
R1212
1200 bps Full-Duplex Modem
3. DTMF Tones: The R1212 generates dual tone multifrequency tones. When the transmission of DTMF tones are
required, the CRO and DTMF bits (see Interface Memory
Definitions)must be set to a 1. When in this mode, the specific
DTMF tones generated are decided by loading the dial digit
register with the appropriate digit as shown in Table 2.
TECHNICAL SPECIFICATIONS
TRANSMITTER CARRIER AND SIGNALING
FREQUENCIES
The transmitter and signaling frequencies supported in the
R1212 are listed in Table 1.
Table 1.
Table 2.
Transmitter Carrier and Signaling
Frequencies Specifications
Hex
Frequency
(Hz ±O.OI%)
Mode
V.22 low channel, Originate Mode
V.22 high channel, Answer Mode
Bell 212A high channel Answer Mode
Bell 212A low channel Originate Mode
Bell 1031113 Originating Mark
Bell 103/113 Originating Space
Bell 103/113 Answer Mark
Bell 1031113 Answer Space
00
01
02
03
04
05
06
07
08
09
OA
DB
DC
OD
DE
OF
1200
2400
2400
1200
1270
1070
2225
2025
TONE GENERATION
The specifications for tone generation are as follows:
1. Answer Tones: The R1212 generates echo disabling tones
for both the CCITT and Bell configurations, as follows:
a. CCITT: 2100 Hz ± 15 Hz.
b. Bell: 2225 Hz ± 10 Hz.
2. Guard Tones: If GTS (see Interface Memory Definitions) is
low, an 1800 Hz guard tone frequency is selected; if GTS is
high, a 553.846 Hz tone is employed. In accordance with the
CCITT V.22 Recommendation, the level of transmitted power
for the 1800 Hz guard tone is 6 ± 1 dB below the level of the
data power in the main channel. The total power transmitted
to the line is the same whether or not a guard tone is enabled.
If a 553.846 Hz guard is used, its transmitted power is
3 ± 1 dB below the level of the main channel power, and again
the overall power transmitted to the line will remain constant
whether or not a guard tone is enabled. The device accomplishes this by reducing the main channel transmit path gain
by .97 dB and 1.76 dB for the cases of the 1800 Hz and
553.846 Hz guard tones respectively.
Table 3.
Operating Mode
V.22
(Alternative A)
Mode i
Mode IIi
(Alternative B)
Mode i
Mode '"
Mode Ii
Tone Pairs
0
1
2
3
4
5
6
7
8
9
941
697
697
697
770
770
770
852
852
852
941
697
770
852
941
941
*
Spare (B)
Spare (C)
Spare (D)
#
Spare (F)
10
1336
1209
1336
1477
1209
1336
1477
1209
1336
1477
1209
1633
1633
1633
1477
1633
1300 Hz Calling Tone
TONE DETECTION
The R1212 detects tones in the 340 ± 5 Hzto 640
Detection Level. -10 dBm to -43 dBm
Response Time: 17 ± 2 ms
± 5 Hz band.
SIGNALING AND DATA RATES
The signaling and data rates for the R1212 are defined in
Table 3.
Signaling and Data Rates
Signaling Rate (Baud)
Data Rate
600
1200 bps ± 0.01 % Synchronous
600
600 bps ± 0.01 % Synchronous
600
600
1200 bps ± 0.01 % Synchronous
600 bps ± 0 01 % Synchronous
1200 bps Asynchronous, 8, 9, 10 or 11 Bits Per Character
Mode iv
Bell 212A;
Dial Digits/Tone Pairs
Dial
Digits
600 bps Asynchronous, 8, 9, 10 or 11 Bits Per Character
600
1200 bps ±0.01%, Synchronous/Asynchronous
o to 300
o to 300 bps Asynchronous
1-8
R1212
1200 bps Full-Duplex Modem
DATA ENCODING
PERMISSIVE/PROGRAMMABLE CONFIGURATIONS
The specifications for data encoding are as follows:
The R1212M transmit level is + 6 dBm to allow a Data Access
Arrangement (DAA) to be used. The DAA then determines the
permissive or programmable configuration.
1. 1200 bps (\1.22 and Bell 212A). The transmitted data is
divided into groups of two consecutive bits (dibits) forming a
four-point signal structure.
The R1212DC transmit level is strapped in the permissive mode
so that the maximum output level is -10 dBm ± 1.0 dBm.
2. 600 bps (\1.22). Each bit is encoded as a phase change relative to the phase preceding signal elements.
AUTOMATIC RECONFIGURATION
EQUALIZERS
The R1212 is capable of automatically configuring itself to the
compatibility of a remote modem. The R1212 can be in either the
answer or originate mode for this to occur. The R1212 adaptation
compatibilities are limited to V.22 AlB (1200 bps), Bell 212, and
Bell 103. If the R1212 is to originate in a specific configuration,
the MODE bits (see Interface Memory Definitions) must be set.
The R1212 provides equalization functions that improve performance when operating over low quality lines.
Automatic Adaptive Equalizer-An automatic adaptive equalizer is provided in the receiver Circuit for V.22 and Bell 212A configurations.
Fixed Compromise Equalizer-A fixed compromise equalizer
is provided in the transmitter.
MODEM OPERATION
TRANSMITTED DATA SPECTRUM
Because the modem is implemented in firmware executed by a
specialized computer (the Signal processor), operation can best
be understood by dividing this section into hardware circuits and
software circuits. Hardware circuits include all pins on the
modem connector. Software circuits include configuration, control (soft strapping), status, and RAM access routines.
After making allowance for the nominal specified compromise
equalizer characteristic, the transmitted line signal has a frequency spectrum shaped by the square root of a 75 percent
raised cosine filter. Similarly, the group delay of the transmitter
output is within ± 150 microseconds over the frequency range
900 to 1500 Hz (low channel) and 2100 to 2700 Hz (high channel).
HARDWARE CIRCUITS
The functional interconnect diagram (Figure 1) shows the
modem connected into a system. In this diaoram, any pOint that
is active when exhibiting the relatively more negative voltage of a
two voltage system (e.g., 0 Vdc for TTL or -12 Vdc for
RS-232-G) is called low active and is represented by association
with a small Circle at tl:1e signal pOint. The particular voltage levels used to represent the binary states do not change the logic
symbol. Two types of 1/0 points that may cause confusion are
edge-triggered inputs and open-collector (open-source or opendrain) outputs. These signal points include the additional notation of a small triangle or a small half-circle (see signal IRQ),
respectively. Active low signals are named with an overscore
(e.g., POR). In deciding whether a clock output is high active or
low active, the convention followed is to assume that the clocking
(activating) edge appropriate to the host hardware is a transition
from the clocks active to its inactive state (i.e., a trailing edge
trigger). A clock intended to activate logic on its rising edge is
called low active while a clock intended to activate logic on its
falling edge is called high active. When a clock input is associated with a small circle, the input activates on a falling edge. If
no circle is shown, the input activates on a rising edge.
SCRAMBLERJDESCRAMBLER
The R1212 incorporates a self-synchronizing scramblerIdescrambler. In accordance with the CCITT V.22 and the Bell
212A recommendations.
RECEIVED SIGNAL FREQUENCY TOLERANCE
The receiver circu it olthe R1212 can adapllo received frequency
errors of up to ± 7 Hz with less than a 0.2 dBm degradation in
BER performance.
RECEIVE LEVEL
The receiver circuit of the R1212 satisfies all specified performance requirements for the received line signals from - 10 dBm to
- 48 dBm. The received line signal is measured at the receiver
analog input RXA.
The interconnect signals on Figure 1 are organized into six
groups of modem operation: overhead signals, V.24 interface
Signals, microprocessor interface signals, DAA signals, analog
signals, and ancillary Signals. Table 4 lists these groups along
with their corresponding connector pin numbers. The column
titled "Type" refers to designations found in the Hardware Circuits Interface Characteristics (Tables 5 and 6). The six groups
of hardware circuits are described in the following paragraphs.
TRANSMIT LEVEL
The R1212M output control circuitry contains a variable gain
buffer which reduces the modem output level. The R1212M can
be strapped via the host interface memory to accomplish this.
1-9
D
R1212
1200 bps Full-Duplex Modem
plete. The R1212 POR sequence leaves the modem configured
as follows:
POWER-ON RESET
Basic modem operation can be understood most easily by beginning with the modem configured to default conditions. When the
modem IS initially energized a signal called Power-On-Reset
(POR) causes the modem to assume a valid operational state.
The modem drives pin 13C to ground during the beginning of the
POR sequence. Approximately 10 ms after the low to high transition of pin 13C, the modem is ready for normal use. The POR
sequence is reinitiated anytime the + 5V supply drops below
+ 3.5V for more than 30 ms, or an external device drives pin 13C
low for at least 3 pS. When an external low input is applied to
pin 13C, the modem is ready for normal use approximately
10 ms after the low input is removed. Pin 13C is not driven low by
the modem when the POR sequence is initiated externally. In all
cases, the POR sequence requires 50 ms to 350 ms to com-
This configuration is suitable for performing high speed data
transfer over the public switched telephone network using the
serial data port. Individual features are discussed in subsequent
paragraphs.
r- - - - - - - - - - - ---,
RTS
CTS
TXD
TDCLK
XTCLK
V 24
INTERFACE
I
I
I
RDCLK
DTR
DSR
I
RING
rI
I
REAO
R1212
MODEM
WRITE
DATA BUS (8)
4
l
~
OECODER
J
CS(2)
iAQ
(
J
+5
POR
LINE MONITOR
TIP
L_
RI
HOST
PROCESSOR
(DTE)
INTERFACE
I
I
I
I
I
I
I
L_
}
I
I
TELEPHONE
LINE
I
I
~~_J
------------ - -- - - - ---,
I
RCCT
CCT
OH
RD
RXA
TXA
DAA
~VE
LEPHONE
LINE
ANALOG
INTERFACE
R1212M ONLY
I
I
I
I
I
I
I
---------- __...J
TBCLK'
RBCLK1
1'1
TLK'
ORG1
+5V
+12V
POWER
SUPPLY
ANALOG
INTERFACE
R1212
I
I
i)
I
I
I
A~?~~~Y
OH
I
RLSD
RXD
~
1200 bps
Asynchronous
10-bit Character Length
Constant Carrier
Serial Mode
Answer Mode
Auto Answer Disabled
RAM Access Code = 00
•
•
•
•
•
•
•
•
Ill'
ANCILLARY
CIRCUIT
INTERFACE
TID RELAY'
-12V
AGND
DOND
NOTES:
1
DIN MODU LE ONLY.
2
DIP MODULE ONLY.
=
=
Figure 1.
R1212 Modem Functional Interconnect Diagram
1-10
R1212
1200 bps Full-Duplex Modem
Table 4.
Name
DIN
Pin No.
Type
DIP
Pin No.
Hardware Circuits
Description
Name
A. OVERHEAD SIGNALS
AGND
31C,32C
Ground (D)
DGND
+5 volts
PWR
+ 12 volts
PWR
PWR
1I0B
3C,8C,
5A, 10A
19C,23C,
26C,3OC
15A
12A
13C
21,26,
39
20,40,
51,60
1,19,
61
Analog Ground
Return
Digital Ground
RelUrn
+ 5 volt supply
22
25
+ 12 volt supply
- 12 voH supply
Power·on·Reset
13
B. MICROPROCESSOR INTERFACE SIGNALS
07
05
04
03
02
01
DO
RS3
RS2
RS1
RSO
CSO
1I0A
1I0A
1I0A
1I0A
1I0A
1I0A
1I0A
1I0A
IA
IA
IA
IA
IA
4A
5C
58
6C
6A
7C
7A
10C
45
44
CS1
IA
9C
41
DB
READ
WRITE
IRQ
IA
IA
OB
DIP
Pin No.
Descriptton
C. V.24 INTERFACE SIGNALS
Ground (A)
-12 volts
POR
DIN
Pin No.
Type
1C
1A
2C
2A
I
52
53
54
55
3A
56
57
4C
43
42
48
12C
11A
11C
47
49
50
IB
22A
3
TDCLK
RDCLK
RTS
CTS
TXD
RXD
RLSD
OC
OC
IB
OC
IB
OC
OC
23A
21A
24C
22C
24A
7
8
4
5
6
9
10
DTR
DSR
IB
OC
OC
21C
20A
18A
12
11
2
32A
31A
23
24
RJ11 Jacks
-
Ai
25A
25C
External Transmit
Clock
Transmit Data Clock
Receive Data Clock
Request-to-Send
Clear-to-Send
Transmrt Data
Receive Data
Received Line Signal
Detector
Data Terminal Ready
Data Set Ready
Ring Indicator
D. ANALOG SIGNALS
Data Bus (Mines)
RXA(M)
TXA(M)
t
59
XTCLK
IB
OC
TIP/RING (DC) AE
LINE
MONITOR (DC) AD
Register Select
(4-Lines)
30A
Receive Analog Input
Transmit Analog
Output
Phone Line Interface
Analog Line Monitor
E. OM INTERFACE SIGNALS
Chip Select
Receiver (Baud
Rate Device)
Chip Select
Transmitter
(Sample Rate
Device)
Read Enable
Write Enable
Interrupt Request
RD(M)
RCCT (M)
IB
OC
27A
28A
CCT(MI
OH
T/D Relay
IB
OC
OC
IC
29C
29A
Mi
Ring Detect
Request Coupler Cut
Through
Coupler Cut Through
Off-Hook Relay Status
TalklData Relay
Manual Input
-
36
-
37
38
F. ANCILLARY INTERFACE SIGNALS
TBCLK
RBCLK
TLK
ORG
-
27C
26A
28C
16C
OC
OC
IC
IB
(M) R1212M Only,
Table 5.
35
Transmit Baud Clock
Receive Baud Clock
Talk (TLK = Data)
Originate (ORG =
Answer)
-
(DC) R1212DC Only,
-
= not applicable
Digital Interface Characteristics
InputiOuput Type
Symbol
V,H
V,L
VOH
VOL
I'N
10H
10L
IL
Ipu
CL
Co
Parameter
Input Voltage, High
Input Voltage, Low
Output Voltage, High
Output Voltage, Low
Input Current, Leakage
Output Current, H'gh
Output Current, Low
Output Current, Leakage
Pull-up Current
(Short Circuit)
Capacitive Load
Capacitive Drive
CirCUit Type
Notes: 1. I load = -1OO~
Units
IA
IB
V
2.0 min.
2.0 min.
IC
2.0 min.
V
V
V
0.8 max.
0.8 max.
0.8 max.
~A
±2.5 max.
-0.1 max.
16 max.
~
5
TTL
2.lIoad = 16 rnA
-240 max
-10 min.
5
-240 max
-10 min.
20
TTL
w/Pull-up
TTL
w/Pull-up
3.lIoad = -40~
1-11
OB
OC
110 A
1I0B
5.25 max.
2.0 min.
0.8 max. 0.8 max.
2.4 min." 2.4 min. 3
0.4 max" 0.4 max,5
±2.5 max.2.0 min.
2.4 min.'
0.4 max"
rnA
rnA
~
pF
pF
OA
0.4 max"
0.4 max"
1.6 max.
±10 max.
1.6 max.
-240 max.
-10 min.
100
TTL
-260 max.
-100 min.
10
40
100
100
100
100
Open-Drain
Open-Drain Open-Drain
3 State
w/Pull-up Transceiver w/Pull-up
4. V'N = 0.4 to 2.4 Vdc, Vee = 5.25 Vde
5 I load = 0.36 rnA
1200 bps Full-Duplex Modem
R1212
Table 6.
Name
TXA
RXA
disregard all signals appearing on the interchange circuitsexcept Ai. DSR will switch to the OFF state when in test state.
The ON condition of DSR indicates the following:
Analog Interface Characteristics
Type
AA
AB
Characteristics
The transmitter output Impedance is 6040
±1% with an output level of +6 dBm.
To obtain a 0 dBm output, a 6000 load to
ground is needed.
1. The modem is not in the talk state, I.e., an associated telephone handset is not in control of the line.
2. The modem is not in the pnocess of automatically establishing
a call via pulse or DTMF dialing.
The receiver input impedance is 23.7 KO
± 1%. The receive level at RXA must be
no greater than -9 dBm (or -6 dBm
with the 3DB bit enabled).
LINE
MONITOR
AD
The line monitor output impedance is
15 KO ±5%.
TIP/RING
AE
The impedance of TIP with respect to
RING is 600 0.
3. The modem has generated an answer tone or detected
answer tone.
4. After ring indicate (Ai) goes ON, DSR waits at least two seconds before turning ON to allow the telephone company
equipment to be engaged.
DSR will go OFF 50 ms after DTR goes OFF, or 50 ms plus a
maximum of 4 seconds when the SSD bit is enabled.
V.24 INTERFACE
Request To Send CATS)
Eleven hardware circuits provide timing, data, and control signals for implementing a serial interface compatible with CCITT
Recommendation V.24. These signals interface directly with circuits using TTL logic levels (OV, + 5V). These TTL levels are
suitable for driving the short wire lengths or prin!ed circuitry normally found within stand-alone modem enclosures or equipment
cabinets. For driving longer cables, the voltage levels and connector arrangement recommended by EIA standard RS-232-C
are preferred.
RTS ON allows the modem to transmit data on TXD when CTS
becomes active. In constant carrier mode, RTS can be wired to
DTR. In controlled carrier operation, independent operation of
RTS turns the carrier ON and OFF. The responses to RTS are
shown in Table 7 (assume the modem is in data mode).
Table 7.
RTS Responses
RTSON
Carrier ON
210 to 275 ms Scrambled
1 s Transmitted
CTSON
CTSON
CTS OFF
Carrier ON
Carrier ON
Scrambled 1 s Data Transmitted
Transmitted
RTS OFF
Leased or Dial Line1
Controlled Carrier
CTS OFF
Carrier OFF
The sequence of events leading to successful data transfer fnom
transmitter to receiver is:
1. The transmitter is activated and a training sequence is sent.
Constant Carner
2. The receiver detects channel energy above the prescribed
threshold level and synchronizes its operation to the
transmitter.
Note:
1. After handshake is complete.
3. Data transfer pnoceeds to the end of the message.
4. The transmitter turns off after in!!uring that all dat,a has had
time to be recovered at the receiver output.
Clear To Send (CTS)
CTS ON indicates to the terminal equipment that the modem will
transmit any data which are present on TXD. CTS response times
from an ON or OFF condition of RTS are shown in Table 8.
Data Terminal Ready (DTR)
DTR prepares the modem to be connected to the communications channel, and maintains the connection established by the
DTE (manual answering) or internal (automatic answering)
mean~. DTR OFF places the modem in the disconnect state.
Table 8. CTS Response Times
CTS Transition
Constant Carrier
OFF to ON
<2 ms
ON to OFF
<20 ms'
Note: 'Programmable
Data Set Ready (DSR)
Data Set Ready (DSR) ON indicates that the modem is in the
data transfer state. DSR OFF is an indication that the DTE is to
1-12
Controlled Carrier
210 to 275 ms
<20 ms'
R1212
1200 bps Full-Duplex Modem
Transmit Data Clock (TDCLK)
RLSD will not respond to guard tones or answer tones.
The modem provides a Transmit Data Clock (TDCLK) output with
the following characteristics:
When RLSD is active, it indicates to the terminal equipment that
valid data is available on RXD.
1. Frequency. Selected data rate of 1200 Hz or 600 Hz
(±0.01%).
Transmitted Data (TXD)
2. Duty Cycle. 50
The modem obtains serial data from the local DTE on this input.
± 1%.
Received Data (RXD)
TDCLK is provided to the user In both asynchronous and synchronous commUnications. TDCLK is not necessary in asynchronous communication but it can be used to supply a clock for
UART/USART timing (TDCLK is not valid in FSK). TDCLK is necessary for synchronous communication. In this case Transmit
Data (TXD) must be stable during the one /LS periods immediately preceding and following the rising edge of TDCLK.
The modem presents received data to the local DTE on this
output.
Ring Indicator (RI)
The modem provides a Ring Indicator (Ri) output; its low state
indicates the presence of a ring signal on the line. The low condition appears approximately coincident with the ON segment of
the ring cycle (during rings) on the communication channel. (The
ring signal cycle is typically two seconds ON, four seconds OFF.)
The high condition of the Ri output is maintained during the OFF
segment of the ring cycle (between rings) and at all other times
when ringing is not being received. The operation of Ri is not
disabled by an OFF condition on DTR.
External Transmit Clock (XTCLK)
In synchronous communication where the user needs to supply
the transmit data clock, the input XTCLK can be used. The clock
supplied at XTCLK must exhibit the same charactenstics of
TDCLK. The XTCLK input is then reflected at TDCLK.
Receive Data Clock (RDCLK)
RI will respcmd to ring signals in the frequency range of 15.3 Hz
to 68 Hz with voltage amplitude levels of 40 to 150 Vrms (applied
across TIP and RING), with the response times given in Table 13.
The modem provides a Receive Data Clock (RDCLK) output in
the form of a 50 ± 1% duty cycle squarewave. The low-to-high
transitions of this output coincide with the center of received data
bits. The timing recovery circuit is capable of tracking a ± .035%
(relative) frequency error in the associated transmit timing
source.
This OFF-to-ON (ON-to-OFF) response time is defined as the
time interval between the sudden connection (removal) of the
ring signal across TIP and RING and the subsequent ON (OFF)
transition of Ai.
RDCLK is provided to the user in both asynchronous and synchronous communications. RDCLK is not necessary in asynchronous communication but it can be used to supply a clock for
UART/USARTtiming (RDCLK is not valid in FSK). RDCLK is necessary for synchronous communication.
Table 9.
Received Line Signal Detector (RLSD)
The RLSD thresholds for both high and low channels are:
RI Response Time
RI Transilion
Response Time
OFF·lo-OW
ON·lo·OFF
110 ±SO ms (SO% duly cycle)
450 ±SO ms
Nole: ·The OFF-Io-ON lime is duty cycle dependent:
890 ms (IS%) ;,: lime;,: 50 ms (100%)
RLSD ON 2: - 43 dBm
RLSD OFF :5 - 48 dBm
1-13
R1212
1200 bps Full-Duplex Modem
MICROPROCESSOR INTERFACE
rupt. Any of these sources can drive the host interrupt input low,
and the interrupt servicing process continues until all interrupts
have been cleared and all IRQ sources have returned to their
~ impedance state. Because of the open-drain structure of
IRQ, an external pull-up resistor to + 5 volts is required at some
point on the IRQ line. The resistor value should be small enough
to pull the IRQ line high when all IRQ drivers are off (i.e., it must
overcome the leakage currents). The resistor value should be
large enough to limit the driver sink current to a level acceptable
to each driver. For the case where only the modem IRQ driver is
used, a resistor value of 5.6K ohms ± 20%, 0.25 watt, is
sufficient.
Seventeen hardware circuits provide address, data, control, and
interrupt signals for implementing a parallel interface compatible
with an 8080 microprocessor. With the addition of a few external
logic gates, the interface can be made compatible with a wide
variety of microprocessors such as 6500, 6800, or 68000.
The microprocessor interface allows a host microprocessor to
change modem configuration, read or write channel data as well
as diagnostic data, and supervise modem operation by means of
soft strappable control bits and modem status bits. The significance of the control and status bits and methods of data interchange are discussed in a later section devoted to software circuits. This section describes the operation olthe interface from a
hardware standpoint.
DAA INTERFACE
The R1212M provides a Data Access Arrangement (DAA) interface that is directly hardware and software compatible with the
RDAA. Manual/automatic originate and answer are then controlled via the appropriate R 1212M hardware ancillary circuits or
software control bits. The modem provides the only interface with
the microprocessor (MPU) bus, i.e., no RDAA interface signals
must be directly controlled from the MPU bus.
Chip Select (CSO and CS1) and
Register Selects (RSO-RS1)
The signal processor to be accessed is selected by grounding
one of two unique chip select lines, CSI or CSO. The selected
chip decodes the four address lines, RS3 through RSO, to select
one of sixteen internal registers. The most significant address bit
(23) is RS3 while the least significant address bit (2°) is RSO.
Once the address bits have been decoded, the selected register
can be read from or written into via an 8-bit parallel data bus, 07
through DO. The most significant data bit (27) is 07 while the
least significant data bit (20) is DO.
Ring Detect (RD)
RD indicates to the modem by an ON (low) condition that a ringing signal is present. The signal (a 4N35 optoisolator compatible
output) into the RD input should not respond to momentary
bursts of ringing less than 125 ms in duration, or to less than
40 Vrms, 15 to 68 Hz, appearing across TIP and RING with
respect to ground. The ring is then reflected on Ri.
Read Enable (READ) and
Write Enable (WRITE)
Request Coupler Cut Through (RCCT)
Reading or writing is activated by pulsing either the READ line
high or the WRITE line low. During a read cycle, data from the
selected register is gated onto the data bus by means of threestate drivers. These drivers force the data lines high for a one bit
or low for a zero bit. When not being read, the three-state drivers
assume their off, high-impedance, state. During a write cycle,
data from the data bus is copied into the selected register, with
high and low bus levelS representing one bits and zero bits,
respectively. The timing required for correct read/write cycles is
illustrated in Figure 2. Logic necessary to convert the single Rm
output from a 65XX series microprocessor to the separate READ
and WRITE signals required by the modem is shown in Figure 3.
RCCT is used to request that a data transmission path through
the DAA be connected to the telephone line. When RCCT goes
OFF (low), the cut-through buffers are disabled and CCT should
go OFF (high). RCCT should be OFF during dialing but ON for
tone address signaling.
Coupler Cut Through (CCT)
An ON (low) signal to the CCT lead indicates to the modem that
the data transmission path through the DAA is connected. This
input can always be grounded if the two second billing delay
squelch is desired. If CCT is user controlled, the billing delay
squelch can only be 2 seconds or greater.
Interrupt Request (IRQ)
Off-Hook Relay Status (OH)
The final ~nal on the microprocessor interface is Interrupt
Request (IRQ). This signal may be connected to the host microprocessor interrupt request input in order to interrupt host program execution for modem service. The use of IRQ is optional
and the method of software implementation is described in a
subsequent section, Software Circuits. The IRQ output structure
is an open-drain field-effect-transistor (FET). This form of output
allows IRQ to be connected in parallel to other sources of inter-
The modem provides an OH output which indicates the stale of
the OH relay. A high condition on OH implies the OH relay is
closed and the modem is connected to the telephone line (offhOOk). A low condition on OH implies the OH relay is open (i.e.,
the modem is on-hOOk). The delay between the low-to-high or
high-to-Iow transition of OH and the subsequent close-to-open or
open-to-close transition of the OH relay is 8 ms maximum.
1-14
1200 bps Full-Duplex Modem
R1212
READ
WRITE
CSi
(i
= 0,1)
RSi
(i
= 0-3)
READ
Di
(i
= 0-7)
Characteristic
CSi. RSi setup time prior
to Read or Write
Data access time after Read
Data hold ti me after Read
CSi. RSi hold time after
Read or Write
Write data setup time
Write data hold time
Write strobe pulse width
Figure 2.
_2
Symbol
Min
TCS
TDA
TDH
30
TCH
TWDS
TWDH
TWR
10
75
10
75
10
Max
Units
140
50
ns
ns
ns
ns
ns
ns
ns
Microprocessor Interface Timing Diagram
J~
READ
R1212
MODEM
WRITE
R/Vi
Figure 3.
R/W to READ WRITE Conversion Logic
1-15
1200 bps Full-Duplex Modem
R1212
ANALOG SIGNALS (R1212M)
TO
(
NETWORK
Two connections are devoted to analog audio signals: TXA and
RXA.
----_e_-+---r--
Transmit Analog (TXA)
:2134
1
MINIATURE
1
I I
6 POSITION JACK
The TXA output is suitable for driving a data access arrangement
for connection to either leased lines or the public switched telephone network. The transmitter output impedance is 604 ohms
±1% with an output level of +6dBm ±1 dBm. To obtain a
o dBm output, a 600 ohm load to ground is needed.
) TO OTHER
EQUIPMENT
--,
516: R2424
I
I
I
L ________
..J
IA
A'
MODEM JACK
r------.,
MINIATURE
:
6 POSITION PLUG I
RING (RED
Receive Analog (RXA)
RXA is an input to the receiver from a data access arrangement.
The input impedance is 23. 7K ohms ± 1%. The received level at
RXA must be no greater than - 9 dBm (or - 6 dBm with the 3DB
bit enabled).
t
j3j4j j
I
+I :I
TELEPHONE
CORD
W~~ J t ~':(GREEN
Figure 4.
WIRE)
RJ11 Telephone Jack
ANCILLARY CIRCUITS
Transmit Baud Clock (TBCLK) and
Received Baud Clock (RBCLK)
ANALOG SIGNALS (R1212DC)
Three analog signals are output by the R1212DC: LINE MONITOR, TIP and RING.
TBClK and RBClK are provided to the user at the baud rate
(600 Hz).
Talk (TLK) (DIN Module Only)
Analog Line Monitor (LINE MONITOR)
TlK is an input which manually places the modem on-hook (relay
open, TlK = O} or off-hook (relay closed, TlK = 1). Theon-hook
condition is referred to as TALK mode and the off-hook condition
is referred to as DATA mode. TlK is used with ORG to manually
originate or answer a call. TlK should be 0 at power-on or reset to
prevent the modem from inadvertently entering the data mode.
The LINE MONITOR output is suitable for a speaker interface. It
provides an output for all dialing signals, call progress signals,
and the carrier signals. The output impedance is 15K ohms
± 1%. The signals which appear on LINE MONITOR are approximately the same level as the signals would appear on the network (assuming a 1 dB loss attributed to the audio transformer).
Originate (ORG)
ORG is an input which manually places the modem in the originate mode (ORG = O) or the answer mode (ORG = 1). To manually originate a call, ORG = 0 and TlK = O. Dial the number
using the telephone. When the other modem answers and sends
answer tone switch the TlK input from 0 to 1 placing the modem
off-hook.
Phone Line Interface (TIP and RING)
TIP and RING are the DAA analog outputs to the public switched
telephone network. These outputs use two RJ 11 jacks in parallel
as the interface to the network (see Table 10 and Figure 4). The
R1212DC, which contains the DAA TIP and RING interface, has
been FCC Part 68 approved. The user need not apply for further
Part 68 approval. The impedance of TIP with respect to RING is
600 ohms.
To manually answer a call ORG = 1 and TlK = O. When the
phone rings switch the TlK input from 0 to 1 placing the modem
off-hook.
Off-Hook Relay Status (OH)
Table 10.
The modem provides an OH output which indicates the state of
the OH relay. A high condition on OH implies the OH relay is
closed and the modem is connected to the telephone line (offhook). A low condition on OH implies the OH relay is open (i.e.,
the modem is on-hook). The delay between the low-to-high or
high-to-Iow transition of OH and the subsequent close-to-open or
open-to-close transition of the OH relay is 8 ms maximum.
R1212DC Network Interface
Connector
Type
Pin
Number
Name
Function
RJ11 Jack
3
4
RING
TIP
One Side of TELCO Line
One Side of TELCO Line
1-16
R1212
1200 bps Full-Duplex Modem
TID Relay. (DIP Module Only)
interface memory. A set of sixteen a-bit registers, labeled register 0 through register F, can be read from or written into by either
the host processor or signal processor. The host communicates
via the microprocessor interface lines shared between the two
signal processors. The signal processor communicates via its
internal I/O bus. Information transfer from SP RAM to interface
memory is accomplished by the signal processor logic unit moving data between the SP main bus and the SP I/O bus. Two olthe
16 addressable interface memory registers (i.e., register 0 and
register E) have unique hardware connections to the interrupt
logic. It is possible to enable a bit in register E to cause an interrupt each time it sets. This interrupt can then be cleared by a read
or write cycle from the host processor to register o. This operation is discussed in detail later in this section.
The TID Relay signal may be used as a second relay control
when the parallel control mode of operation is selected (BUS bits
oand 1 = 1). If the serial control mode is selected (BUS bits 0 and
1 =: O).the TID relay follo~ the status of the OH output signal
which IS controlled by the MI signal. In the parallel control mode
the OH output signal is controlled by the status of the DATA bit
while independent control of the TID relay is provided by the
signal. During pulse dialing the OH signal reflects the pulse signals being dialed. It is therefore possible to use the TID Relay
signal to control the off-hook relay and use the OH signal to perform pulse dialing on a separate, independent relay.
Mi
Manual Input (MI) (DIP Module Only)
MI is an input which manually places the modem on-hook (relay
open, MI = 0) or off-hook (relay closed, MI = 1). The on-hook
condition is referred to as TALK mode and the off-hook condition
is .~ferred to as DATA mode. MI is used with ORG to manually
onglnate or answer a call. MI should be 0 at power-on or reset to
prevent the modem from inadvertently entering the data mode.
Memory maps of the 32 addressable registers in the modem
receiver (eSO) and transmitter (CS1) interface memory are
shown in Figures 5 and 6, respectively. These registers may be
read or written on any host read or write cycle, but all eight bits of
that register are affected. In order to read a single bit or a group of
bits in a register, the host processor must mask out unwanted
data. When writing a single bit or group of bits in a register the
host processor must perform a read-modify-write operation. That
is, the entire register is read, the necessary bits are set or reset in
the accumulator of the host, then the original unmodified bits and
the modified bits are written back into the register of the interface
memory.
SOFTWARE CIRCUITS
Operation of the microprocessor interface circuits was described
in the hardware section from the standpoint of timing and loadIdrive characteristics. In this section, operation of the microprocessor interface is described from a software standpoint.
Figures 7 and a show the registers according to the overall functi?n they perform in the receiver and transmitter, respectively.
Figures 9 and 10 show the power-on configuration for the R1212
modem receiver and transmitter devices, respectively.
The modem is implemented in firmware running on two special
purpose signal processors. These signal processors share the
computing load by performing tasks that are divided into two
areas. These areas are partitioned into receiver and transmitter
devices.
Table 11 defines the individual bits in the interface memory. In the
Table 11 descriptions, bits in the interface memory are referred to
using the format Y:Z:Q. The chip number is specified by Y (0 or
1), the register number by Z (0 through F), and the bit number by
Q (0 through 7, with 0 = LSB).
INTERFACE MEMORY
Each signal processor can communicate with the host processor
by means of a specialized, dual-port, scratch-pad memory called
1-17
R1212
1200 bps Full-Duplex Modem
~
7
Register
6
4
5
F
2
3
1
~
0
-
IRQ
ENSI NEWS
0
BUS
CRQ
B
-
-
-
-
A
ERDL
RDL
DL
ST
-
-
C
9
-
7
6
NEWC
-
-
-
LCD
RSD
-
-
CHAR
-
-
-
AL
-
-
-
-
-
-
2
-
ENSI NEWS
0
BUS
CRQ DATA AAE
C
DSRA
TXCLK
ERDL
-
DTR
CHAR
TX LEVEL
A
GTE
RDL
DL
ST
-
9
NAT'
-
ORG
LL
RTS
CC
EF
NTS
RLSD
8
DLO
CTS
DSR
RI
-
-
-
7
-
-
-
-
-
-
-
-
-
-
6
-
RAM Data YTL (YRAMTL)
RAM Data XTM (XRAMTM)
RAM Data XRL (XRAMRL)
0
-
-
-
RAM Data XTL (XRAMTL)
2
-
-
-
-
-
-
-
1
~
Reglste
7
Dial Digit Register
Notes
1. Not valid before R5312-16
(-) Indicates reserved for modem use only.
Receiver (CSO) Interface Memory Map
I
6
I
5
I
4
1i l l
2
3
- -
-
-
-
0
Note
(-) Indicates reserved for modem use only.
Figure 5.
1
Figure 6.
~
0
Reglste
Transmitter (CS1) Interface Memory Map
7
I
6
5
I
I
4
I
3
I
2
DIAGNOSTIC CONTROL
HANDSHAKE
E
HANDSHAKE
0
CONFIGURATION
0
CONFIGURATION
C
CONFIGURATION
C
CONFIGURATION
B
CONFIGURATION
B
CONFIGURATION
A
CONFIGURATION
A
CONFIGURATION
9
STATUS
9
CONFIGURATION
8
STATUS
8
STATUS
7
RESERVED
7
RESERVED
F
6
RESERVED
6
RESERVED
5
DIAGNOSTIC
5
DIAGNOSTIC
4
DIAGNOSTIC
4
DIAGNOSTIC
3
DIAGNOSTIC
3
DIAGNOSTIC
2
DIAGNOSTIC
2
DIAGNOSTIC
1
RESERVED
1
0
RESERVED
0
Bit
Figure 7.
7
I
6
I
5
I
4
I
3
I
2
11
I
Bit
Receiver (CSO) Interface Memory Functions
Figure 8.
1-18
1
I
0
I
0
RESERVED
DIAL
~
0
I
DIAGNOSTIC CONTROL
F
E
~
-
RAM Data YTM (YRAMTM)
5
4
-
AL
-
3
-
SSD
DLSF'
MODE
RAM Data YRL (YRAMRL)
-
DDRE
3DB DTMF
GTS
RAM Data XRM (XRAMRM)
-
-
NEWC DDEI
4
1
0
RAM Access T
IRQ
3
2
1
TM
RAM Data YRM (YRAMRM)
5
3
4
E
B
MODE
SPEED
-
TONE ATD
8
5
F
RAM Access R
E
6
7
Reglsta
7
I
6
I
5
DIGIT REGISTER
I
4
I
3
I
2
I
1
Transmitter (CS1) Interface Memory Functions
1200 bps Full-Duplex Modem
R1212
~
7
Regl
6
5
4
3
2
1
~
0
Regl
RAM Access R
F
7
5
6
0
0
0
0
0
0
0
0
F
0
0
0
E
IRQ
ENSI
0
0
NEWS
-
NEWC
-
-
-
E
IRQ
ENSI
0
NEWS
0
D
BUS
CRQ
0
LCD
1
RSD
0
D
BUS
C
-
-
-
-
-
C
OSRA
AL
B
0
0
0
ERDL
0
A
ERDL
RDL
DL
9
NAT
-
ORG
0
8
DLO
CTS
OSR
-
B
A
- - 1
RDL
DL
ST
0
0
0
0
0
-
-
9
-
-
TONE
ATD
0
0
-
-
6
0
-
8
7
0
5
CHAR
- SPEED
-
0
-
-
0
-
MODE
0
-
0
0
1
1
- TM- -
- - - 0
-
-
-
-
RLSD
0
-
0
0
7
-
6
RAM Data YRM (Random)
3
RAM Access T
2
0
0
0
0
0
NEWC
DDEI
0
0
DDRE
CRQ
DATA
AAE
0
0
DTR
0
-
-
3DB
DTMF
AL
TXCLK
0
0
0
0
0
-
-
0
0
0
-
0
CHAR
1
0
GTS
GTE
0
0
ST
0
0
LL
RTS
0
0
RI
0
-
-
0
0
0
-
-
-
-
-
-
-
-
CC
- -
RAM Data YTM (Random)
5
4
RAM Data YTL (Random)
3
RAM Data XTM (Random)
2
RAM Data XRL (Random)
0
-
-
-
7
6
5
~
Bit
-
-
-
-
-
-
4
3
2
1
0
Figure 9.
RAM Data XTL (Random)
-
1
-
- - -
-
Dial Digit Reglater (Write·Only Reglater)
0
~
Bit
(-) Indlcatea rellrved for modem UII only.
0
1
NTS
0
RAM Data YRL (Random)
-
0
DLSF
1
EF
0
0
RAM Data XRM (Random)
-
0
SSD
0
MODE
4
1
0
-
3
2
1
0
TX LEVEL
0
4
7
6
5
4
3
2
1
0
(-) Indicates re..rved lor modem uee only.
R1212 Receiver (CSO) Interface Memory
Power On Configuration
Figure 10. R1212 Transmitter (CS1) Interface Memory
Power On Configuration
1-19
I
R1212
1200 bps Full-Duplex Modem
Table 11.
Mnemonic
AAE
Name
Auto Answer Enable
Interface Memory Definitions
Memory
Location
1:D:4
Description
When configuration bit AAE is a 1, the modem will automatically answer
when a ringing signal is present on the line. When AAE IS set to a 1, the
modem will answer after one ring and go into data mode.
The modem goes off-hook 1 second after the on-to-off transition of the ring.
The ORG pin or ORG bit need not to be set to the answer polarity. If it IS
deSired to answer after more than one ring, then the user must use the alternative answer method described under the DATA bit. The DTR pin or
the DTR bit must also be set before the modem Will auto answer. Writing a 0
into the AAE bit Will cause the modem to go on-hook. This will occur only
when the modem auto answers using the AAE bit
AL
Analog Loopback
(O,l):B:O
When configuration bits AL are a 1, the modem is in local analog loopback
(V.54 Loop 3). In this loop, the transmitter's analog output is coupled to the
receiver's analog input at a pOint near the modem's telephone line interface.
An attenuator is Introduced into the loop such that the signal level coupled
into the receive path is attenuated 14 ± 1 dBm. The modem may be placed
into analog loopback In either the idle mode or the data mode. However, In
the data mode, setting the AL bits to a 1 will terminate the connecllon.
Analog loopback will only function in the high speed modes (1200, or 600
bps).
The DTE may be tested when the modem is in analog loopback. Also, all
parts of the modem except the line interface are checked. If no DTE is connected, the modem integrity may be verified by use of the self test function.
When entering analog loopback, set AL in the receiver to a 1 before selting
AL In the transmitter to a 1.
When exiting analog loopback, reset AL in the transmitter to a 0 before resetting AL in the receiver to a O.
ATD
Answer Tone Detected
BUS
Bus Select
0:8:6
When status bit ATD is a 1, It signifies that the modem receiver detected the
answer tone. The bit is 1 set 75 ms after the answer tone is first detected,
and is cleared to a 0 when the modem goes on-hook. The user may clear
ATD manually after CTS is active.
(0,1):D:7
When configuration bits BUS are a 1, the modem is In the parallel control
mode; and when 0, the modem is in the serial control mode. BUS can be In
either state to configure the modem.
Serial Control Mode
The serial mode uses standard V.24 (RS-232-C compatible) Signals to
transfer channel data. The control Signals used in serial control mode are
DTR, RTS, TLK, and ORG. Outputs such as RLSD and DSR are reflected
both in the interface memory and the V.24 interface. Once the bus bits have
been set to a 0, the state of the DTR, RTS, DATA, and ORG bits are
ignored.
Parallel Control Mode
The modem has the capability of modem control via the microprocessor bus.
Data transfer is maintained over the serial V.24 channel. The control bits
used in parallel control are DTR, RTS, ORG, and DATA
The modem automatically defaults to the serial mode at power-on.
If the parallel control mode Is~be used, it is recommended that the TLK pin
be tied to ground. A floating TLK pin will assume a logic 1 which will
Immediately put the modem into the data mode before the BUS bits are set.
In either mode, the modem IS configured by the host processor via the
microprocessor bus
1-20
R1212
1200 bps Full-Duplex Modem
Table 11.
Mnemonic
CC
Name
Controlled Carner
Interface Memory Definitions (Continued)
Memory
Location
1:9'2
Description
When configuration bit CC is a 1, the modem operates in controlled carrier;
when 0, the modem operates In constant carrier.
Controlled carrier allows the modem transmitter to be controlled by the RTS
pin or the RTS bit. Its effect may be seen In the RTS and CTS descriptions.
CHAR
Character Length Select
(O,l):C:(3,4)
These character length bits select either 8, 9, 10, or 11 bit characters
(includes data, stop, and start bits) as shown below:
Configuration Word
!
!
o
o
0
1
1
Configuration
8 bits
9 bits
10 bits
11 bits
1
0
1
It IS possible to change character length during the data mode. Errors in the
data Will be expected between the changeover and the resynchronization
(which occurs on the next start bit after the change is Implemented).
CRa
Call Request
(0,1):0:6
When configuration bit CRa in chip 1 (the transmitter) is a 1, it places the
transmitter in auto dial mode. The data then placed in the Dial Digit Register
is treated as digits to be dialed. The format for the data should be a hex
representation of the number to be dialed (if a 9 is to be dialed then an 09 16
should be loaded in DDR). CRa in chip 1 should be a 1 for the duration of
the data mode. If CRa in chip 1 is changed to a 0, the modem will go
on·hook. Also, see DDRE bit.
When configuration bit CRa in chip 0 (the receiver) is a 1, the receiver goes
into tone detect mode. Any energy above threshold and in the 345 to 635 Hz
bandwidth is reflected by the TONE bit. CRa in chip 0 must be reset to a 0
(after the last digit was dialed and tone detection completed) before the
answer tone is sent by the answering modem (after ringback is detected).
CRa in chip 0 need not be used during auto dialing, but may be used to pro·
vide call progress information as part of an intelligent auto dialing routine An
example flowchart is given in Figure 11.
FF (hex) should be loaded into the Dial Digit Register after the last digit IS
dialed and tone detection is completed. This action also puts the modem in
data mode and starts a 30 second abort timer. If the handshake has not
been completed in 30 seconds the modem will go on·hook.
CTS
Clear·to·Send
1:8:6
When status bit CTS is a 1, it indicates to the terminal equipment that the
modem will transmit any data which are present at TXD.
CTS response tim~s from an ON or OFF condition of RTS are shown below:
CTS Transition
OFF to ON
ON to OFF
• Programmable
Constant Carrier
,;;2 ms
s20 ms"
Controlled Carrier
210 to 275 ms
,;;20 ms'
DATA
Talk/Data
1:0:5
When control bit DATA is a 1, the modem is in the data state (off-hook); and
when 0, the modem is in the talk state (on-hOOk). This bit allows the modem
to go off·hook after a programmable number of rings by counting the required
number of RI bit transitions and then setting the DATA bit (assuming ORG = 0).
DDEI
Dial Digit Empty Interrupt
1:E:2
When handshake bit DDEI is a 1, an interrupt will occur when the Dial Digit
Register (1:0) is empty (DDRE=l). This is independent of the state of the
ENSI bit. The interrupt will set the IRa bit and also assert the IRa signal.
Loading the Dial Digit Register with a new digit will clear the Interrupt
condition.
1-21
R1212
1200 bps Full-Duplex Modem
Table
Mnemonic
Name
DDR
Dial Digit Register
DDRE
Dial Digit Register Empty
11. Interface Memory Definitions (Continued)
Memory
Location
10:(0-7)
l'E:O
Description
DDR IS used to load the digits to be dialed. Example: If a 4 IS to be dialed,
an 04 (hex) should be loaded. This action also causes the interrupt to be
cleared. Tl]e modem automallCally accounts for the interdlgit delay. Note.
DDR is a wrlte·only register.
When handshake bit DDRE IS a 1, it indicates that the dial digit register IS
empty and can be loaded with a new digit to be dialed. If the DDEI bit is set,
the IRQ bit will be set when the DDRE bit is set. Also, the IRQ signal will be
generated.
After the DDR is loaded, DDRE goes to a 0 and the interrupts are
automatically cleared.
DL
Digital Loopback (Manual)
(0,1):A'5
When configuration bits DL are set to a 1, the modem IS manually placed in
digital loopback. DL should only be set during the data mode. The DSR and
CTS bits will be reset to a O. The local modem can then be tested from the
remote modem end by looping a remotely generated test pattern. At the
remote modem, all interface circuits behave normally as In the data mode.
At the conClusion of the test, DL must be reset to a O. The local modem will
then return to the normal data mode with control reverting to the DTEs, DTR.
DL does not functIOn In 300 bps.
DLO
Dial Line OCCUPied
1:8:7
When status bit DLO is a 1, it Indicates that the modem is in the auto dial
state, i.e., CRQ in the transmitter IS a 1 and the modem is off·hook and
ready to dial.
DLSF
Disable Low Speed Fallback
l:C:O
When configuration bit DLSF is a 1, the modem will not automatically
fallback to the 300 bps operating mode if it is configured for another data
rate. This bit, is valid in originate mode only.
DSR
Data Set Ready
1:8:5
The ON condillon of the status bit DSR indicates that the modem is In the
data transfer state. The OFF condition of DSR is an indication that the DTE
IS to disregard all signals appearing on the Interchange circuits - except RI.
DSR will sWitch to the OFF state when in test state. The ON condition of
DSR indicates the following:
rhe modem is not In the talk state, i.e., an associated telephone handset is
not in control of the line.
The modem IS not in the process of automatically establishing a call via
pulse or DTMF dialing.
The modem has generated an answer tone or detected answer tone.
After ring Indicate goes ON, DSR waits at least two seconds before turning
ON to allow the telephone company equipment to be engaged.
DSR will go OFF 50 msec after DTR goes OFF, or 50 msec plus a maximum
of 4 sec when the SSD bit is enabled.
DSRA
Data Set Ready In Analog
Loopback
1:C:7 '
When configuration bit DSRA is a 1, It causes DSR to be ON during analog
loopback.
1-22
R1212
1200 bps Full-Duplex Modem
Table 11.
Mnemonic
DTMF
Name
Touch Tones/Pulse Dialing
Interface Memory Definitions (Continued)
Memory
Location
I:B'1
Description
When configuration bit DTMF is ai, It tells the modem to auto dial using
tones; and when 0, the modem will dial uSing pulses.
The timing for the pulses and tones are as follows (power-on timing):
Pulses -
Relay open 64 ms
Relay closed 36 ms
Interdigit delay 750 ms
Tones - Tone duration 95 ms
Interdigit delay 70 ms
The DTMF bit can be changed during the dialing process to allow either tone
or pulse dialing of consecutive digits. The output power level of the DTMF
tones is as follows:
±15dBm ±1 measuredatTXAfortheR1212M
-1 dBm ± 1 measured at TIP/RING for the R1212DC
DTR
Data Terminal Ready
1:0:3
Control bit DTR must be a 1 for the modem to enter the data state. either
manually or automatically. DTR must also be a 1 in order for the modem to
automatically answer an incoming call.
During the data mode, DTR must remain at a I, otherwise the connectIon will
be terminated if DTR resets to a 0 for greater than 50 ms.
EF
Enable Filters
1:9:1
ENSI
Enable New Status Interrupt
(O,I):E:6
When handshake bit ENSI is a I, it causes an interrupt to occur when the
status bits in registers (0:[8,9]) and (1 :8) are changed by the modem.
(NEWS = 1). The IRQ bit will be set to a 1 and the IRQ signal will be
generated. The interrupt is cleared by writing a 0 into the NEWS bit.
ERDL
Enable Response to
Remote Digital Loopback
(O,I):A:7
When configuration bits ERDL are a I, it enables the modem to respond to
another modem's remote digital loopback request, thus going into loopback.
When this occurs, the modem clamps RXD to a mark; resets the CTS, DSR
and RLSD bits to a 0 and turns the CTS, DSR and RLSD signals to a logiC 1.
The TM bit is set to inform the user of the test status. When thE! ERDL bits are
a 0, no response will be generated.
GTE
Guard Tone Enable
I:B:4
When configuration bit GTE is a I, it causes the specified guard tone to be
transmitted (CCITI configurations only), according the state of the GTS bit. Note:
The guard tone will only be transmitted by the answering modem.
Setting CRQ in the transmitter to a 1 disables the high and low band filters
used in data mode so that call progress tone detection can be done. Setting
CRQ In the receiver to a 1 inserts a passband filter In the receive path which
passes energy in the 345 Hz to 635 Hz bandwidth. The high and low band
filters must be enabled and the passband fmer disabled for the answer tone
and carrier to be detected. This occurs automatically during the auto dial process when EF is set to a O. In this case, the high and low band filters are
disabled when CRQ in the transmitter is set to a 1. If tone detection is reqUired, CRQ in the receiver should be set to a 1. After dialing and call progress tone detection, CRQ in the receiver is set to a 0 and FF is loaded into
the dial digit register. (Loading FF enables the high and low band filters). At
this time, the answer tone can be detected. To re-enable the high and low
band fi~ers disabled by setting CRQ in the transmitter, set EF to a 1. After
CRQ In the transmitter and receiver is set to a 1 and tone detection is completed, it may be necessary to detect the answer tone before loading FF into
the dial digit register (see the section on sending 1300 Hz calling tone). At
that point, EF can be set to a 1 and CRQ in the receiver set to a 0 so the
answer tone can be detected (using the ATD bit) and the 1300 Hz calling
tone can still be sent. Once the answer tone is detected, FF should be loaded Into the dial digit register and the EF bit set to a O.
1-23
R1212
1200 bps Full-Duplex Modem
Table 11.
Mnemonic
Name
GTS
Guard Tone Select
IRQ
Interrupt
LCD
Loss of Carrier Disconnect
Interface Memory Definitions (Continued)
Memory
Location
Description
I:B:3
When configuration bit GTS is a 0, it selects the 1800 Hz tone; when GTE is
a 1 it selects the 550 Hz tone. The selected guard tone will be transmitted
only when GTE is enabled.
(O,I):E:7
When status bit IRQ is a I, it indicates that an interrupt has been generated.
The IRQ hardware signal is generated following the setting of the IRQ bit.
IRQ is cleared when either the NEWS bit is reset to a 0 or lhe DDR is
loaded with a number.
0:0:2
When configuration bit LCD is a I, the modem terminates a call when a loss
of received carrier energy is detected after 400 ms. After the first 40 ms of
loss of carrier, RLSD goes off. 360 ms later, if no carrier is detected, CTS
goes off, and the modem goes on·hook. If energy above threshold is
detected during the 360 ms period, RLSD will be set to a 1 again. If further
loss of energy occurs, the 400 ms time frame is restarted.
If LCD is set to a 0, RLSD will be set to a 1 when energy is above threshold,
but will not force the modem on·hook when energy falls below threshold. In
this case, it is necessary to re-enable LCD in order to put the modem on-hook.
LCD is not automatically disabled in leased line operation. The user must
write a 0 into LCD bits for this to occur.
LL
Leased Line
1:9:4
MODE
Mode Select
(0,1 ):A:(O,3)
When configuration bit LL is a I, the modem IS in leased line operation;
when 0, the modem is in switched line operation. When LL is set to a I, the
modem immediately goes off-hook and into data mode.
These bits select the compatibility at which the modem is to operate, as
shown below:
Configuration Word
~
g
!
~
0
0
0
1
1
1
1
0
0
1
0
0
0
0
1
1
0
0
0
1
1
0
1
0
0
1
0
1
Configuration
Bell 212A
Bell 212A
Bell 212A
V.22A
V.22B
V.22A
V.22B
1200 Sync.
1200 Async.
o to 300 Async.
1200 Sync.
1200 Async.
600 Sync.
600 Async.
NOTE: The Mode bits in both chips should be set exclusively of all other
bits, followed immediately by the setting of the NEWC bits. This will ensure
proper modem configuration.
Automatic Reconfiguration
The modem is capable of automatically falling back during the handshake to
the compatibility of a remote modem. The modem can be in either the
answer or originate mode for this to occur. The compatibilities that the
modem are limited to adapt to are V.22 AlB (1200 bps), Bell 212 and
Bell 103. If the R1212 is to originate in a specific configuration, the MODE
bits must be set.
When the answer modem is configured for Bell 300 asynchronous and is
called by a 1200 bps modem, the handshake will be completed at 1200 bps.
NAT
No Answer Tone
1:9:7
When configuration bit NAT is a I, the modem will not transmit the 2100 Hz
CCID answer tone. This bit is only valid for CCID configurations. With this
bit enabled in answer mode, when the modem goes off-hook it will remain
silent for 75 ms and then transmit unscrambled ones.
1-24
R1212
1200 bps Full-Duplex Modem
Table 11,
Mnemonic
Name
Interface Memory Definitions (Continued)
Memory
Location
Description
NEWC
New Configuration
(0,t):E:3
When the NEWC bit is at, It tells the modem that a new configurallon has
been written into the configuration registers. The modem will then read the
configuration registers and then reset NEWC to a O. NEWC must be set to a
t after a new configuration has been written Into the following registers:
(O:[A-D]) and (1 :[9-0]). The remaining registers do not require the use of
NEWC to tell the modem that new data was wntten into them.
NEWS
New Status
(0,1):E:5
When handshake bit NEWS is aI, it tells the user that there has been a
change of status In the status registers. The user must write a 0 Into NEWS
to reset It. This action also causes the interrupt to be cleared.
NTS
No Transmitter Scrambler
1:9:0
When configuration bit NTS is aI, when the modem is off-hook It will
transmit all data in an unscrambled form. This bit should be disabled if the
normal modem handshake is desired.
ORG
Originate/Answer
1:9:5
When configuration bit ORG is aI, the modem IS in onginate mode; and
when a 0 the modem is in answer mode. (This is only valid in manual
originate/answer and analog loopback). If ORG is a 1 in analog loopback, the
modem will transmit in the high band and receive In the low band. If ORG is
a 0 in analog loopback, the modem will transmit in the low band and receive
in the high band.
(None)
RAM Access R
0:F:0-7
Contains the RAM access code used in reading RAM locations in chip 0
(receiver device).
(None)
RAM Access T
I:F:0-7
Contains the RAM access code used in reading RAM locations in chip 1
(transmitter device).
XRAMRL
RAM Data XRL
0:2:0-7
Least significant byte of 16-bit word X used In reading RAM locations in chip
o.
XRAMRM
RAM Data XRM
0:3:0-7
Most significant byte of 16-bit word X used in reading RAM locations in chip
o.
XRAMTL
RAM Data XTL
1:2:0-7
Least significant byte of 16-bit word X used in reading RAM locations in chip 1.
XRAMTM
RAM Data XTM
1:3:0-7
Most significant byte of 16-bit word X used in reading RAM locations In chip 1.
YRAMRL
RAM Data YRL
0:4:0-7
Least significant byte of 16-bit word Y used in reading RAM locations in chip
YRAMRM
RAM Data YRM
0:5:0-7
Most significant byte of 16-blt word Y used in reading RAM locations in chip O.
YRAMTL
RAM Data YTL
1:4:0-7
Least significant byte of 16-bit word Y used in reading RAM locations in chip 1.
YRAMTM
RAM Data YTM
1:5:0-7
Most significant byte of 16-bit word Y used in reading RAM locations in chip 1.
RDL
Remote Digital Loopback
(0,1):A:6
When configuration bits RDL are aI, it causes the modem to initiate a
request for the remote modem to go into digitalloopback. RXD is clamped to
a mark and the CTS bit and CTS signal will be reset until the loop is
established. The TM bit is not set in this case, since the local modem initiated the request. RDL does not function in 300 bps.
RI
Ring Indicator
1:8:4
When status bit RI is aI, it Indicates that a ringing signal is being detected.
The RI bit follows the ringing signal with a 1 during the on time and a zero
during the off time coincident with the Ai signal. The following are the RI bit
response ti mes:
RI Bit Transition
OFF-to-ON"
ON-to-OFF
"The OFF-te-ON time
IS
o.
Response
110 ±50 ms (50% duty cycle)
450 ±50 ms
duty cycle dependent. 890 ms (15%) " time" 50 ms (100 010)
This OFF-la-ON (or ON-to-OFF) response time IS defined as the time interval
between the sudden connection (removal) of the ring signal across TIP and
RING and the subsequent transition of the RI bit.
1-25
R1212
1200 bps Full-Duplex Modem
Table 11.
Mnemonic
RLSO
Name
Received Line Signal
Detector
Interface Memory Definitions (Continued)
Memory
Location
0:8:0
Description
When status bit RLSO is a 1, it indicates that the carrier has successfully
been received. RLSO will not respond to the guard tones or answer tones.
RLSO response times are given below:
RLSO' .
OFF·to-QN
ON·to·OFF
Constant
Carrier
Controlled
Carrier
105 to 205 ms
10 to 24 ms
105 to 205 ms
10 to 24 ms
Note:
1. After handshake has occurred.
RSO
Receive Space Disconnect
0:0:1
When configuration bit RSD is a 1, the modem goes on-hook after receiving
approximately 1.6 seconds of continuous spaces.
RTS
Request-ta-Send
1:9:3
When control bit RTS is a 1, the modem transmits any data on TXD when
CTS becomes active. In constant carrier mode, RTS should be set the same
time as DTR and then left ON. In controlled carrier operation, independent
operation of RTS turns the carrier ON and OFF. The responses to RTS are
shown (assume the modem is in data mode).
Leased or Dial Line'
RTS Off
RTS On
Controlled Carrier
CTS OFF
Carrier OFF
Carrier ON
210 to 275 ms Scrambled l's
Transmitted
CTSON
Constant Carrier
CTS OFF
Carrier ON
Scrambled l's
Transmitted
CTSON
Carrier ON
Data Transmitted
Note:
1. After handshake is complete.
For ease of use in constant carrier mode, RTS should be turned ON the
same time as DTR.
SPEED
Speed Indication
0:9:(4,5)
The SPEED status bits reflect the speed at which the modem is operating.
The SPEED bit representations are shown.
~
!
Speed
o
o
0
1
0-300
600
1
0
1200
Note:
The SPEED bits are not active in analog loopback and leased line mode.
1-26
R1212
1200 bps Full-Duplex Modem
Table 11.
Interface Memory Definitions (Continued)
Memory
Mnemonic
Name
SSD
Send Space Disconnect
ST
Self Test
Description
Location
1:0:0
(0,1):A:4
When configuration bit SSD is a 1, it causes the modem to transmit
approximately 4 seconds of spaces before disconnecting, when DTR goes
from active to inactive state,
When configuration bit ST is a 1, self test is activated. ST must be a 0 to end
the test. It is possible to perform self test in analog loopback with or without a
DTE connected. During any self test, TXD and RTS are Ignored. Self test does
not test asynchronous·to·synchronous converter circuits m either the transmit·
ter or receiver.
Error detection is accomplished by monitoring the self test error counter in
the RAM. If the counter increments during the self test, an error was made.
The counter contents are available in the diagnostic register when the RAM
access code 00 is loaded in the diagnostic control register (O:F).
Self Test End·to·End (Data Mode)
Upon activation of self test an internally generated data pattern of alternate
binary ones and zeros (reversals) at the selected bit rate are applied to the
scrambler. An error detector, capable of identifying errors in a stream of
reversals are connected to the output of the descrambler.
Self Test with Loop 3
Loop 3 is applied to the modem as defined in Recommendation V.54. Self
test is activated and DCE operation is as in the end·to·end test, In this test
DTR is ignored.
Self Test with Loop 2 (Data Mode)
The modem IS conditioned to mstigate a loop 2 at the remote modem as
specified in recommendation V.54. Self test is activated and DCE operation
is as in the end·to·end test.
ST does not function in 300 bps.
3DB
3 dB Loss to Receive
Signal
1:B:2
When configuration bit 3DB is a 1, it attenuates the received signal 3 dB.
This is only used if the modem will see 0 dBm or greater line signal at the
receiver input. Insertion of the 3 dB loss will then prevent saturation.
TM
Test Mode
0:8:1
When status bit TM is a 1, it indicates that the modem has completed the
handshake and is in one of the following test modes: AL or RDL.
TONE
Tone Detect
0:8:7
TONE follows the energy detected in the 340 to 640 Hz frequency band. The
user must determine which tone is present on the line by determining the
duty cycle of the TONE bit. TONE is active only when CRO in chip 0 is a 1.
Detection Range: - 10 to - 43 dBm
Response Time:
17 ± 2 ms
TXCLK
Transmit Clock Select
1:C:(5,6)
TXCLK allows the user to designate the origin of the transmitter data clock,
as shown below:
Configuration Word
Transmit Clock
~
~
Internal
External
Slave
o
o
1
1
1
o
If external clock IS chosen the user clock must be mput at XTCLK. The clock
characteristics must be the same as TDCLK. The external clock Will be
reflected by TDCLK.
If slave clock is chosen the transmitter is slaved to the receive clock. This is
also reflected by TDCLK.
1·27
R1212
1200 bps Full-Duplex Modem
Table 11.
Mnemonic
TX LEVEL
Interface Memory Definitions (Continued)
Memory
Location
Name
1:B:(5-7)
Transmit Level
Description
TX LEVEL allows the user to change the transmit level at TIP and RING
(assuming the OAA has 10 dBm attenuation in the transmit path).
Configuration
Word
!.
!
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
~
0
1
0
1
0
1
0
1
Transmit Level <:I: 1.0 dBm)
<
!!
m
~
~
I
MODEM
TEST SET
PHOENIX
5000
MODEM
TRANSMITTER
MODEM
RECEIVER
2- TO 4-WIRE
HYBRID
2- TO 4-WIRE
HYBRID
MODEM
RECEIVER
MODEM
TRANSMITTER
MODEM
TEST SET
PHOENIX
5000
'11
It
s-
3
II
::s
n
It
~
!Sf/)
LEVEL METER
HP 3552A
ATTENUATOR
HP 350D
-
IMPAIRMENT
SOURCE
BRADLEY
2A AND 2B
~
LINE
SIMULATOR ...
(3002)
SEG FA-1445
.....
~
o
o
--
!!.
0"
Ie
'0
'i
9:
't:J
(I)
NOTE: SIGNAL AND NOISE ARE MEASURED WITH 3 KHZ FLAT WEIGHTING,
c;
."
!?
0'
::s
C
C
'i"'
.!.
c
CD
't:J
>C
s::
o
a.
CD
3
.JIlL
~
1200 bps Full-Duplex Modem
R1212
Table 17. Modem Power Requirements
Voltage
Tolerance
Current (Typical) @ 25°C
Current (Max) @ DOC
+5 Vdc
+ 12 Vdc
-12 Vdc
±5%
±5%
±5%
390 rnA
25 rnA
4 rnA
<455 rnA
< 30 rnA
< 5 rnA
Note: All voltages must have ripple :s0.1 volts peak-to-peak.
Table 18. Modem Environmental Restrictions
Parameter
Specification
Temperature
Operating
Storage
Relative Humidity:
Altitude
O°C to +60°C (32°F to 140°F)
- 40°C to + BO°C (- 40°F to 176°F) (Stored in heat sealed antistatic bag and shipping container)
Up to 90% noncondensing, or a wet bulb temperature up to 35°C, whichever is less.
-200 feet to + 10,000 feet
Table 19. Modem Mechanical Considerations
Parameter
DIN Connector Version
Board Structure:
Mating Connector:
PCB Dimensions:
DC Version
Width
Length
Height
M Version
Width
Length
Height
Weight (max):
Lead Extrusion (max.):
DIP Connector Version
Board Structure
Dimensions
Width
Length
Height
Weight (max.)
Pin Length (max.)
Specification'
Single PC board with a 3-row 64-pin right angle male DIN connector with rows A and C populated.
The modem can also be ordered with the following DIN connector: 64-pin DIN right angle female,
64-pin DIN vertical male or 64-pin DIN vertical female.
Female 3-row 64-pin DIN receptacle with rows A and C populated. Typical mating receptacle:
Winchester 968-6043-0531-1, Burndy RI96B32ROOAOOZ1, or equivalent.
3.937 in. (100 mm)
4.725 in. (120 mm)
0.75 in. (19 mm)
3.937 in.
3.328 in.
0.40 in.
0.45 Ibs.
0.100 in.
(100 mm)
(82 mm)
(10.2 mm)
(0.20 kg.)
(2.54 mm)
Single PC board with a row of 30 pins and a row of 31 pins in a dual in-line pin configuration.
2.0 in. (50.B mm)
3.5 in. (88.9 mm)
0.2 in. (5.0B mm) above, 0.13 in. (3.30 mm) below
2.6 oz. (73g)
0.53 in. (13.5 mm) above
1-32
I
R1212
1200 bps Full-Duplex Modem
MALE 64-PIN
DIN CONN ECTOR
/
0.496
(12.6)
MALE 64-PIN
DIN CONNECTOR
(3_96)
Tr-'-
! ! !
1
COMPONENT
SIDE
o156 ± 003 DIA (4 PL)
3.937
(100)
1I
I
COMPONENT
SIDE
-fo-
.- 0.496
(12.6)
(94)
0.119
(3)
II
I.
}
2.625
(66.7) 3.228 _ _
0.483
O(~~91
T----
(12.3)
O.483
3.275 (66.7)
(1 2.3)
(104) 4.725
0.200 MAX
COMPONENT ARE A
/
I" (5.1)
rtL-E====~---~--
=-~-~:npJ
-=====- - -=====-
0.062
(11.1)
(1.6)
:
0.100 MAX
~
_2.625
4.100 (83.2)
(82)
120)
(
n~
r~~~
t~~~-~---.'-~
(1.6)
COMPONENT AREA
(2.54)
DIN CONNECTOR VERSION
0.098 DIA (4 PL)
(2.5)
J
0.100
(2.54)
0.075
(1.9)
UNITS: INCHES
mm
DIP CONNECTOR VERSION
Figure 13.
i
Modem Printed Circuit Board Dimensions
1·33
MAX
R1212
1200 bps Full-Duplex Modem
FCC RULES PART 68 REQUIREMENTS
R1212 MODEM INSTALLATION AND
MAINtENANCE
The FCC Rules Part 68 requires that the telephone interface
leads shall:
This section contains installation instructions and maintenance
procedures for the Rockwell R1212DC Modem. It also contains a
special notice from the Canadian Department of Communications (DOC) for Canadian operation and from the Federal Communications Commission (FCC) for United States operation.
1. Be reasonably physically separated and restrained from; not
routed in the same cable as; nor use the same connector as
leads or metallic paths connecting to power connections.
Note
Power connections are defined as the connections
between com mercial power and any transformer, power
supply rectifier, converter or other circuitry associated
with the modem. The connections of the interface pins
(including the + 12 Vdc, - 12 Vdc and + 5 Vdc) are not
considered power connections.
GENERAL DESCRIPTION
The Rockwell R1212DC modem is designed to be used with the
United States or Canadian Telephone Switched Networks in 2wire full-duplex dial-up operation. The modem requires protective circuitry registered with the Federal Communications Commission (FCC) Part 68 which allows direct connection to the U.S.
switched telephone network. This circuitry also complies with
the Canadian Department of Communications (DOC) Terminal
Attachment Program (TAP) which similarly defines their
switched telephone network requirements.
2. Be reasonably physically separated and restrained from; not
routed in the same cable as; nor use adjacent pins on the
same connector as metallic paths that lead to unregistered
equipment, when specification details provided to the FCC do
not show that the interface voltages are less than nonhazardous voltage source limits in Part 68.
The R1212DC features automatic dial and answer capabilities
along with surge suppression and hazardous voltage and longitudinal balance protection. Its maximum output signal level at the
telephone interface is set at - 10 dBm ± 1 dBm (permissive
mode of operation).
Note
All the DIN connector interface voltages to the modem
have been established as non-hazardous.
Two standard telephone jack connectors (RJlls) are mounted
side by side on one edge of the board and are wired in parallel.
One is for connection to the telephone line network and the other
for the telephone headset connection.
ROUTING OF TELEPHONE INTERFACE LINES
In routing the telephone interface leads from the modem telephone connector jacks to the telephone line network connection,
the following precautions should be strongly considered for
safety.
INSTALLATION AND SIGNAL ROUTING
INSTRUCTIONS
1. The telephone interface routing path should be as direct and
as short as possible.
PHYSICAL MOUNTING
2. Any cable used in establishing this path should contain no
signal leads other than the modem telephone interface leads.
The modem module may be physically incorporated into the customer's end product by utilizing the four corner 0.156" diameter
mounting holes (for the self-hooking plastic type standoffs or for
bolting it down to some rigid structure) or by installing the module
into card guides.
3. Any connector used in establishing this path shall contain not
commercial power source signal leads, and adjacent pins to
the TIP and RING (T and R) pins in any such connector shall
not be utilized by any signals other than those shown in this
document.
ELECTRICAL INTERFACING INSTRUCTIONS
The electrical interfacing is accomplished via the DIN (Euro) connector (for external power inputs and digital logic signals) and
the telco connectors (for the telephone network connection).
Note that the telephone interface connectors are physically separated from the modem interface control connector and extreme
care must be taken in routing the telephone interface leads from
the modem to the telephone network (line connector jack in the
wall).
MAINTENANCE PROCEDURE
Under the FCC Rules, no customer is authorized to repair
modems. In the event of a Rockwell modem malfunctioning,
return it for repair to an authorized ROCKWELL INTERNATIONAL distributor (if in Canada) or send it directly to the Semiconductor Products Division, Rockwell International Corporation, EI Paso, Texas 79906.
1-34
1200 bps Full-Duplex Modem
R1212
Sample label below:
SPECIAL INSTRUCTION TO USERS
Unit contains Registered Protective Circuitry which complies with Part 68 of FCC Rules.
If the Rockwell modem has been registered with the Federal
Communications Commission (FCC), you must observe the following to comply with the FCC regulations:
FCC Registration Number: AMQ9SQ-14211-DM-E
A. All direct connections to the telephone lines shall be made
through standard plugs and telephone company provided
jacks.
Ringer Equivalence: 0.9B
Note
B. It is prohibited to connect the modem to pay telephones or
party lines.
The Rockwell modem module has the FCC registration
number and ringer equivalence number permanently
affixed to the solder side of the PCB and any unit contaimng this modem shall use this information for the
label requirements.
C. You are required to notify the local telephone company of the
connection or disconnection of the modem, the FCC registration number, the ringer equivalence number, the particular line
to which the connection is made and the telephone number to
.
be associated with the jack.
Note
SPECIAL NOTICE FROM THE CANADIAN
DEPARTMENT OF COMMUNICATIONS
If the proper jacks are not available, you must order the
proper type of jacks to be Installed by the telephone
company (VSOC RJ11 for permissive mode of operation).
The Canadian Department of Communications label Identifies
certified equipment. This certification means that the equipment
meets certain telecommunications network protective, operational and safety reqUirements. The Department does not guarantee the equipment will operate to the user's satisfaction.
D. You should disconnect the modem from the telephone line if it
appears to be malfunctioning. Reconnect it only if it can be
determined that the telephone line and not the modem is the
source oltrouble. lithe Rockwell modem needs repair, return
it to the ROCKWELL INTERNATIONAL CORPORATION. This
applies to the modem whether it is in or out of warranty. Do not
attempt to repair the unit as this is a violation of the FCC rules
and may cause danger to persons or to the telephone network.
Before installing this equipment, users should insure that it is
permissible to be connected to the facilities of the local telecommunications company. The equipment must also be installed
using an approved method of connection. In some cases, the
company's inside wiring associated with a Single line individual
service may be extended by means of a certified jack-plug-cord
ensemble (telephone extension cord). The customer should be
aware that the compliance with the above conditions may not
prevent degradation of service in some situations. Existing telecommunications company requirements do not permit their
equipment to be connected to customer-provided jacks except
where specified by individual telecommunications company tariffs.
TELEPHONE COMPANY RIGHTS
AND RESPONSIBILITIES
A. The Rockwell modem contains protective circuitry to prevent
harmful voltages to be transmitted to the telephone network. If
such harmful voltages do occur, then the telephone company
may temporarily discontinue service to you. In this case, the
telephone company should:
The Department of Communications requires the Certificate
Holders to identify the method of network connection in the user
literature provided with the certified terminal equipment.
1. Promptly notify you of the discontinuance.
2. Afford you the opportunity to correct the situation which
caused the discontinuance.
Repairs to certified equipment should be made by an authorized
Canadian maintenance facility deSignated by the supplier. Any
repairs or alterations made by the user to this eqUipment, or
equipment malfunctions may give the telecommunications company cause to request the user to disconnect the equipment.
3. Inform you of your right to bring a complaint to the FCC
concerning the discontinuance.
B. The telephone company may make changes in its facilities
and services which may affect the operation of your eqUipment. It is, however, the telephone company's responsibility to
give you adequate notice in writing to allow you to maintain
uninterrupted service.
Users should ensure for their own protection that the electrical
ground connections olthe power utility, telephone lines and internal metallic water pipe system, if present, are connected
together. This precaution may be particularly important in rural
areas.
LABELING REQUIREMENTS
CAUTION
A. The FCC requires that the following label be prominently displayed on the outside surface of the customer's end product
and that the size of the label should be such that all the
required information IS legible without magnification.
Users should not attempt to make such connections themselves, but should contact the appropriate electric inspection authority, or electrician, as appropriate.
1-35
-----~~------
~--~
-----=---~-= - - - ,- - - - - - - - - -
.-,----.-~
--------
R2424
Integral Modems
'1'
Rockwell
R2424
2400 bps Full-Duplex Modem
INTRODUCTION
FEATURES
The Rockwell R2424 is a high performance full-duplex 2400 bps
modem. Using state-of-the-art VLSI and signal processing technology, the R2424 provides enhanced performance and reliability. The modem is assembled as a small module with a DIN connector (R2424M and R2424DC) or a new, smaller module (seven
square inches) with a dual-in-line pin (DIP) interface.
•
•
•
•
•
Being CCITTV.22 bis, V.22 A, B compatible, as well as Bell 212A
and 103 compatible, the R2424 fits most applications for fullduplex 2400 and 1200 bps fallback (synchronous and asynchronous) and 0 to 300 bps asynchronous data transmission over the
general switched telephone network, and over pOint-to-point
leased lines.
•
•
•
The direct-connect, auto dial/answer features are specifically
designed for remote and central site computer applications. The
bus interface allows easy integration into a personal computer,
box modem, microcomputer, terminal or any other communications product.
•
•
•
•
•
The R2424/DM, with its small form factor and DIP connection,
can be automatically installed and soldered onto a host module.
Its small size is ideal for internal "1/2-card" PC modem applications. Moreover, the R2424/DM is pin and firmware compatible
with the R1212/DM and pin compatible with Rockwell's next generation of medium speed modems, the RC2424 and RC1212.
•
CCITT V.22 bis, V.22 A, B Compatible
Be1l212A and 103 Compatible
Synchronous: 2400 bps, 1200 bps, 600 bps ±0.01%
Asynchronous: 2400 bps, 1200 bps, 600 bps + 1%, -2.5%,
0-300 bps
- Character Length 8, 9, 10, or 11 bits
DTE Interface
- Functional: CCITT V.24 (RS-232-C) (Data/Control) and
Microprocessor Bus (Data/Configuration/Control)
- Electrical: TTL Compatible
2-wire Full-Duplex Operation
Adaptive and Fixed Compromize Equalization
Test Configurations:
- Local Analog Loopback
- Remote Digital Loopback
- Self Test
Auto/Manual Answer
Auto/Manual Dial-DTMF Tone or Pulse Dial
Power Consumption: 2.3 Watts Typical
Power Requirements: + 5 Vdc, ± 12 Vdc
Three Module Configurations:
- R2424DC (Direct Connect): DIN connector module with
FCC approved DAA Part 68 Interface
- R2424M: DIN connector module without DAA
- R2424/DM: DIP connection module without DAA
Two Functional Versions
- R2424/US All data rates specified except 600 bps
- R2424/1NT All data rates specified except 0-300 bps
R2424/DM Modem
R2424M Modem
Document No. 29200N11
Data Sheet
1-36
Order No. MD11
Rev. 4, February 1987
R2424
2400 bps Full-Duplex Modem
3. DTMF Tones: The R2424 generates dual tone multifrequency tones. When the transmission of DTMF tones are
required, the CRa and DTMF bits (see Interface Memory
Definltions)must be set to a 1. When in this mode, the specific
DTMF tones generated are decided by loading the dial digit
register with the appropriate digit as shown in Table 2.
TECHNICAL SPECIFICATIONS
TRANSMITTER CARRIER AND SIGNALING
FREQUENCIES
The transmitter and signaling frequencies supported in the
R2424 are listed in Table 1.
Table 1.
Table 2.
Transmitter Carrier and Signaling
Frequencies Specifications
Frequenc)'
(Hz ±O.OI%)
Mode
V 22 bls low channel, Originate Mode
V 22 low channel, Originate Mode
V.22 bis high channel, Answer Mode
V 22 high channel, Answer Mode
Bell 212A high channel Answer Mode
Bell 212A low channel Originate Mode
Bell 103/113 Onglnatlng Mark
Bell 103/113 Originating Space
Bell 103/113 Answer Mark
Bell 103/113 Answer Space
Hex
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
aD
OE
OF
1200
1200
2400
2400
2400
1200
1270
1070
2225
2025
TONE GENERATION
The specifications for tone generation are as follows:
1. Answer Tones: The R2424 generates echo disabling tones
for both the CCITT and Bell configurations, as follows:
a. CCITT: 2100 Hz ± 15 Hz.
b. Bell: 2225 Hz ± 10 Hz.
2. Guard Tones: If GTS (see Interface Memory Definitions) is
low, an 1800 Hz guard tone frequency is selected; if (nS is
high, a 553.846 Hz tone is employed. In accordance wiith the
CCITT V.22 Recommendation, the level of transmitted power
for the 1800 Hz guard tone is 6 ± 1 dB below the level of the
data power in the main channel. The total power transmitted
to the line is the same whether or not a guard tone is enabled.
If a 553.846 Hz guard is used, its transmitted power is
3 ± 1 dB below the level of the main channel power, and again
the overall power transmitted to the line will remain constant
whether or not a guard tone is enabled. The device accomplishes this by reducing the main channel transmit path gain
by .97 dB and 1.76 dB for the cases of the 1800 Hz and
553.846 Hz guard tones respectively.
Table 3.
Operating Mode
Dial Digits/Tone Pairs
Dial
Digits
*
10
TONE DETECTION
The R2424 detects tones in the 340 ± 5 Hz to 640 ± 5 Hz band.
Detection Level: -10 dBm to -43 dBm
Response Time: 17 ± 2 ms
SIGNALING AND DATA RATES
The signaling and data rates for the R2424 are defined in
Table 3.
Signaling and Data Rates
Signaling Rate (Baud)
Data Rate
-
V.22 bis'
600
V.22:
(Alternative A)
Mode I
600
1200 bps ± 0.01 Ofo Synchronous
600
600 bps ± 0.01 Ofo Synchronous
600
600
1200 bps ± 0.01 Ofo Synchronous
600 bps ± 0 010f0 Synchronous
Synchronous/Asynchronous, 2400 bps ± 0.01 Ofo
Synchronous/Asynchronous, 1200 bps ±0.010f0
Mode Ii
1200 bps Asynchronous, 8, 9, 10 or 11 Bits Per Character
Mode iv
Bell 212A:
1336
1209
1336
1477
1209
1336
1477
1209
1336
1477
1209
1633
1633
1633
1477
1633
1300 Hz Calling Tone
600
(Alternative B)
Mode i
Mode IIi
941
697
697
697
770
770
770
852
852
852
941
697
770
852
941
941
Spare (B)
Spare (C)
Spare (D)
#
Spare (F)
V.22 b,s'
Mode III
Tone Pairs
0
1
2
3
4
5
6
7
8
9
600
o to 300
600 bps Asynchronous, 8, 9, 10 or 11 Bits Per Character
-.
1200 bps ±0.010f0, Synchronous/Asynchronous
o to 300 bps Asynchronous
1-37
0
I
2400 bps Full-Duplex Modem
R2424
DATA ENCODING
The R2424DC transmit level is strapped in the permissive mode
so that the maximum output level is -10 dBm ± 1.0 dBm.
The specifications for data encoding are as follows:
1. 2400 bps (\1.22 bis). The transmitted data is divided into
groups of four consecutive bits (quad bits) forming a 16-point
signal structure.
AUTOMATIC RECONFIGURATION
The R2424 is capable of automatically configuring itself to the
compatibility of a remote modem. The R2424 can be in either the
answer or originate mode for this to occur. The R2424 adaptation
compatibilities are limited to V.22 bis, V.22 AlB (1200 bps), Bell
212, and Bell 103. If the R2424 is to originate in a specifiC configuration, the MODE bits (see Interface Memory Definitions)must
beset.
2. 1200 bps (\1.22 and Bell 212A). The transmitted data is
divided into groups of two consecutive bits (dibits) forming a
four-point signal structure.
3. 600 bps (\1.22). Each bit is encoded as a phase change rela-
tive to the phase preceding signal elements.
EQUALIZERS
The R2424 provides equalization functions that improve performance when operating over low quality lines.
Automatic Adaptive Equalizer-An automatic adaptive equalizer is provided in the receiver circuit for V.22 bis, V.22 and Bell
212A configurations.
MODEM OPERATION
Because the modem is implemented in firmware executed by a
spec.ialized computer (the signal processor), operation can best
be understood by dividing this section into hardware circuits and
software circuits. Hardware circuits include all pins on the
modem connector. Software circuits include configuration, control (soft strapping), status, and RAM access routines.
Fixed Compromise Equalizer-A fixed compromise equalizer
is provided in the transmitter.
TRANSMITTED DATA SPECTRUM
After making allowance for the nominal specified compromise
equalizer characteristic, the transmitted line signal has a frequency spectrum shaped by the square root of a 75 percent
raised cosine filter. Similarly, the group delay of the transmitter
output is within ± 150 microseconds over the frequency range
900 to 1500 Hz (low channel) and 2100 to 2700 Hz (high channel).
HARDWARE CIRCUITS
The functional interconnect diagram (Figure 1) shows the
modem connected into a system. In this diagram, any point that
is active when exhibiting the relatively more negative voltage of a
two .voltage system (e.g., 0 Vdc for TIL or -12 Vdc for
RS-232-C) is called low active and is represented by association
with a small circle at the signal point. The particular voltage levels used to represent the binary states do not change the logic
symbol. Two types of 1/0 points that may cause confusion are
edge~triggered inputs and open-collector (open-source or opendrain) outputs. These signal points include the additional notation of a small triangle or a small half-<:ircle (see signal IRQ),
respectively. Active low signals are named with an overscore
(e.g., POR). In deciding whether a clock output is high active or
low !IClive, the convention followed is to assume that the clocking
(activating) edge appropriate to the host hardware is a transition
from the clocks active to its inactive state (i.e., a trailing edge
trigger). A clock intended to activate logiC on its rising edge is
called low active while a clock intended to activate logic on its
falling edge is called high active. When a clock input is associated with a small circle, the input activates on a falling edge. If
no circle is shown, the input activates on a rising edge.
SCRAMBLERIDESCRAMBLER
The R2424 incorporates a self-synchronizing scramblerIdescrambler. In accordance with the CCITI V.22 bis, V.22 and
the Bell 212A recommendations.
RECEIVED SIGNAL FREQUENCY TOLERANCE
The receiver circuit of the R2424 can adapt to received frequency
errors of up to ± 7 Hz with less than a 0.2 dBm degradation in
BER performance.
RECEIVE LEVEL
The receiver circuit of the R2424 satisfies all specified performance requirements for the received line signals from -10 dBm to
- 48 dBm. The received line Signal is measured at the receiver
analog input RXA.
TRANSMIT LEVEL
The R2424M output control circuitry contains a variable gain
buffer which reduces the modem output level. The R2424M can
be strapped via the host interface memory to accomplish this.
The interconnect signals on Figure 1 are organized into six
groups of modem operation: overhead signals, V.24 interface
signals, microprocessor interface signals, DAA Signals, analog
signals, and ancillary signals. Table 4 lists these groups along
with their corresponding connector pin numbers. The column
titled "Type" refers to deSignations found in the Hardware Circuits Interface Characteristics (Tables 5 and 6). The six groups
of hardware circuits are described in the following paragraphs.
PERMISSIVE/PROGRAMMABLE CONFIGURATIONS
The R2424M transmit level is + 6 dBm to allow a Data Access
Arrangement (DAA) to be used. The DAA then determines the
permissive or programmable configuration.
1-38
2400 bps Full-Duplex Modem
R2424
plete. The R2424 paR sequence leaves the modem configured
as follows:
POWER-ON RESET
Basic modem operation can be understood most easily by beginning with the modem configured to default conditions. When the
modem is initially energized a signal called Power-On-Reset
(paR) causes the modem to assume a valid operational state.
The modem drives pin 13C to ground during the beginning of the
paR sequence. Approximately 10 ms after the low to high transition of pin 13C, the modem is ready for normal use. The paR
sequence is reinitiated anytime the + 5V supply drops below
+ 3.5V for more than 30 ms, or an external device drives pin 13C
low for at least 3 (ts. When an external low input is applied to
pin 13C, the modem is ready for normal use approximately
10 ms after the low input is removed. Pin 13C is not driven low by
the modem when the paR sequence is initiated externally. In all
cases, the paR sequence requires 50 ms to 350 ms to com-
•
•
•
•
•
•
•
•
This configuration is suitable for performing high speed data
transfer over the public switched telephone network using the
serial data port. Individual features are discussed in subsequent
paragraphs.
r- ---------- ---,
RTS
CTS
TXD
I
I
I
I
TDCLK
XTCLK
V.24
RLSD
RXD
INTERFACE
2400 bps
Asynchronous
1O-bit Character Length
Constant Carrier
Serial Mode
Answer Mode
Auto Answer Disabled
RAM Access Code = 00
I
RDCLK
TR
DSR
I
-"
I
L_
RI
rI
READ
WRITE
R2424
DATA BUS (8)
MODEM
A
HOST
PROCESSOR
(DTE)
I
U
~
DECODER
r
(4)
cs (2)
I
J
L_
-12V
AGND
TIP
RING
ANALOG
INTERFACE
}
I
I
TELEPHONE
LINE
I
I
::'N~_J
------------------- ---,
R2424D
RCCT
..---
CCT
OH
DAA
RD
I
~}'
'-----RXA
TXA
ANALOG
INTERFACE
ELEPHONE
I
LINE
I
I
I
I
I
----------M~::J
R2424
RBCLK'
+5V
+12V
POWER
I
LINE MONITOR
TBCLK'
POR
SUPPLY
I
I
I
I
INTERFACE
I
IRQ
+5
I
I
I
I
ANCILLARY
CIRCUIT
OH
TLK'
ORG'
ANCILLARY
MI'
INTERFACE
CIRCUIT
TID RELAY'
OGND
NOTES:
DIN MODU LE ONLY.
1
2
DIP MODULE ONLY.
=
=
Figure 1. R2424 Modem Functional Interconnect Diagram
1-39
o
R2424
2400 bps Full-Duplex Modem
Table 4.
Name
DIP
Pin No.
DIN
Pin No.
Type
Hardware 9ircuits
Name
Description
Ground (A)
AGND
31C,32C
Ground (D)
DGND
+5 volts
PWR
+ 12 volts
-12 volts
POR
PWR
PWR
1I0B
3C,8C,
5A, lOA
19C,23C,
26C,3OC
15A
12A
13C
21,26,
39
20,40,
51,60
1,19,
61
Analog Ground
Return
Digttal Ground
Return
+ 5 volt supply
22
+ 12 volt supply
- 12 volt supply
Power·on·Reset
25
13
B. MICROPROCESSOR INTERFACE SIGNALS
07
06
05
04
03
02
01
DO
RS3
RS2
RS!
RSO
CSO
IIOA
IIOA
IIOA
IIOA
IIOA
1I0A
IIOA
IIOA
IA
IA
IA
IA
IA
2C
2A
3A
4C
4A
5C
6C
6A
7C
7A
lOC
52
53
54
55
56
57
58
59
45
44
43
42
48
CSl
IA
9C
41
lC
lA
IA
IA
OB
DIP
Pin No.
Description
C. V.24 INTERFACE SIGNALS
A. OVERHEAD SIGNALS
READ
WRITE
IRQ
DIN
Pin No.
Type
47
49
50
12C
llA
llC
XTCLK
IB
22A
3
TDCLK
RDCLK
RTS
CTS
TXD
RXD
RLSD
OC
OC
IB
OC
IB
OC
OC
23A
21A
25A
25C
24C
22C
24A
7
8
4
5
6
9
10
DTR
DSR
IB
OC
OC
21C
20A
18A
12
11
2
32A
31A
23
24
RJ11 Jacks
-
Receive Analog Input
Transmit Analog
Output
Phone Line Interface
30A
-
Analog Line Monitor
35
Ring Detect
Request Coupler Cut
Through
Coupler Cut Through
Off·Hook Relay Status
Talk/Data Relay
Manual Input
Ri
1
D. ANALOG SIGNALS
Data Bus (B-Lines)
RXA(M)
TXA (M)
j
IB
OC
TIPIRING (DC) AE
LINE
MONITOR (DC) AD
Register Select
(4-LineS).
E. DAA INTERFACE SIGNALS
Chip Select
Receiver (Baud
Rate Device)
Chip Select
Transmitter
(Sample Rate
Device)
Read Enable
Write Enable
Interrupt Request
RD(M)
RCCT (M)
IB
OC
27A
28A
CCT(M)
OH
TID Relay
IB
OC
29C
29A
Mi
IC
36
-
OC
37
-
38
F. ANCILLARY INTERFACE SIGNALS
TBCLK
RBCLK
TLK
ORG
-
27C
26A
28C
16C
OC
OC
IC
IB
(M) R2424M Only,
Table 5.
External Transmit
Clock
Transmit Data Clock
Receive Data Clock
Request·to-Send
Clear·to-Send
Transmit Data
Receive Data
Received Line Signal
Detector
Data Terminal Ready
Data Set Ready
Ring Indicator
-
(DC) R2424DC Only,
Transmit Baud Clock
Receive Baud Clock
Talk (TLK = Data)
Originate (ORG =
Answer)
- =
not applicable
Digital Interface Characteristics
Input/Ouput Type
Sy_mbol
Parameter
Units
IA
18
IC
OA
V ,H
Input Voltage, High
V
2.0 min.
2.0 min.
2.0 min.
V,L
V OH
VOL
I'N
10H
10L
IL
Ipu
Input Voltage, Low
Output Voltage, High
Output Voltage, Low
Input Current, Leakage
Output Current, High
Output Current, Low
Output Current, Leakage
Pull·up Current
(Short Circuit)
Capacitive Load
Capacitive Drive
Circuit Type
V
V
V
0.8 max.
0.8 max.
O.B max.
~A
±2.5 max.
CL
Co
Notes: 1. I load
=
-100~
-0.1 max.
1.6 max.
~
~
pF
pF
2. I load
5
TIL
= 1.6 rnA
-240 max.
-10 min.
5
-240 max.
-10 min.
20
TIL
w/Pull·up
TIL
w/Pull·up
3. I load
=
-40~
1-40
110 A
2.0 min.
2.4 min.'
0.4 max'
rnA
rnA
DC
DB
4. V'N
0.4 max. 2
0.4 max'
1.6 max.
± 10 max.
1.6 max.
0.8
2.4
0.4
±2.5
I/OB
5.25
2.0
max. O.S
min 2 2.4
max' 0.4
max 4
max.
min.
max.
min. 3
max. s
-240 max.
-10 min.
100
TTL
-260 max.
-100 min.
10
40
100
100
100
100
Open·Drain Open·Drain
3 State
Open·Drain
w/Pull-up Transceiver w/Pull-up
= 0.4 to 2.4 Vdc,
Vec
= 525 Vdc
5. I load
= 0.36 rnA
R2424
2400 bps Full-Duplex Modem
Table 6.
Name
TXA
RXA
Analog Interface Characteristics
Type
Characteristics
AA
The transmitter output impedance IS 604n
± 1% with an output level of + 6 dBm.
To obtain a 0 dBm output, a 600n load to
ground IS needed.
AB
disregard all signals appearing on the interchange circuitsexcept Ai. DSR will switch to the OFF state when in test state.
The ON condition of DSR indicates the following:
1. The modem is not in the talk state, i.e., an associated telephone handset is not in control of the line.
2. The modem is not in the process of automatically establishing
a call via pulse or DTMF dialing.
The receiver mput impedance IS 23.7 Kn
± 1%. The receive level at RXA must be
no greater than - 9 dBm (or - 6 dBm
with the 30B bit enabled).
LINE
MONITOR
AD
The line mOnitor output impedance is
15 Kn ±5%.
TIP/RING
AE
The impedance of TIP with respect to
RING is 600 n.
3. The modem has generated an answer tone or detected
answer tone.
4. After ring indicate (Ai) goes ON, DSR waits at least two seconds before turning ON to allow the telephone company
equipment to be engaged.
DSR will go OFF 50 ms after DTR goes OFF, or 50 ms plus a
maximum of 4 seconds when the SSD bit is enabled.
V.24 INTERFACE
Request To Send (RTS)
Eleven hardware circuits provide timing, data, and control signals for implementing a serial interface compatible with CCITT
Recommendation V.24. These signals interface directly with circuits using TTL logic levels (OV, + 5V). These TTL levels are
suitable for driving the short wire lengths or printed circuitry normally found within stand-alone modem enclosures or equipment
cabinets. For driving longer cables, the voltage levels and connector arrangement recommended by EIA standard RS-232-C
are preferred.
RTS ON allows the modem to transmit data on TXD when CTS
becomes active. In constant carrier mode, RTS can be wired to
DTR. In controlled carrier operation, independent operation of
RTS turns the carrier ON and OFF. The responses to RTS are
shown in Table 7 (assume the modem is in data, mode).
Table 7. RTS Responses
RTS OFF
Leased or Dial Line 1
The sequence of events leading to successful data transfer from
transmitter to receiver is:
CTS OFF
Carrier OFF
Carrier ON
210 to 275 ms Scrambled
1s Transmitted
CTS ON
Constant Carrier
CTS OFF
Carrier ON
Scrambled IS
Transmitted
CTSON
Carrier ON
Data Transmitted
1. The transmitter is activated and a training sequence is sent.
2. The receiver detects channel energy above the prescribed
threshold level and synchronizes its operation to the
transmitter.
RTSON
Controlled Carrier
Note:
1. After handshake is complete.
3. Data transfer proceeds to the end of the message.
4. The transmitter turns off after insuring that all data has had
time to be recovered at the receiver output.
Clear To Send (CTS)
Data Terminal Ready (OTR)
CTS ON indicates to the terminal equipment that the modem will
transmit any data which are present on TXD. CTS response times
from an ON or OFF condition of RTS are shown in Table 8.
DTR prepares the modem to be connected to the communications channel, and maintains the connection established by the
DTE (manual answering) or internal (automatic answering)
means. DTR OFF places the modem in the disconnect state.
Table 8. CTS Response Times
CTS Transition
Constant Carrier
OFF to ON
ON to OFF
Data Set Ready (OSR)
Data Set Ready (DSR) ON indicates that the modem is in the
data transfer state. DSR OFF is an indication that the DTE is to
Note: 'Programmable
1-41
<2 ms
<20 ms'
Controlled Carrier
210 to 275 ms
<20 ms'
D
R2424
2400 bps Full-Duplex Modem
Transmit Data Clock (TDCLK)
RLSD will not respond to guard tones or answer tones.
The modem provides a Transmit Data Clock (TDCLK) output with
the following characteristics:
When RLSD is active, it indicates to the terminal equipment that
valid data is available on RXD.
1. Frequency. Selected data·rate of 2400 Hz, 1200 Hz or 600 Hz
(±0.01%).
2. Duty Cycle. 50
Transmitted Data (TXD)
The modem obtains serial data from the local DTE on this input.
± 1%.
TDCLK is provided to the user in both asynchronous and synchronous communications. TDCLK is not necessary in asynchronous communication but it can be used to supply a clock for
UART/USART timing (TDCLK is not valid in FSK). TDCLK is necessary for synchronous communication. In this case Transmit
Data (TXD) must be stable during the one p's periods immediately preceding and following the rising edge of TDCLK.
Received Data (RXD)
The modem presents received data to the local DTE on this
output.
Ring Indicator (RI)
The modem provides a Ring Indicator (RI) output; its low state
indicates the presence of a ring signal on the line. The low condition appears approximately coincident with the ON segment of
the ring cycle (during rings) on the communication channel. (The
ring signal cycle is typically two seconds ON, four seconds OFF.)
The high condition of the Ai output is maintained during the OFF
segment of the ring cycle (between rings) and at all other times
when ringing is not being received. The operation of Ai is not
disabled by an OFF condition on DTR.
External Transmit Clock (XTCLK)
In synchronous communication where the user needs to supply
the transmit data clock, the input XTCLK can be used. The clock
supplied at XTCLK must exhibit the same characteristics of
TDCLK. The XTCLK input is then reflected at TDCLK.
Receive Data Clock (RDCLK)
Ai will respond to ring signals in the frequency range of 15.3 Hz
The modem provides a Receive Data Clock (RDCLK) output in
the form of a 50 ± 1% duty cycle squarewave. The low-to-high
transitions of this output COincide with the center of received data
bits. The timing recovery circuit is capable oftracking a ± .035%
(relative) frequency error in the associated transmit timing
source.
to 68 Hz with voltage amplitude levels of 40 to 150 Vrms (applied
across TIP and RING), with the response times given in Table 13.
This OFF-to-ON (ON-to-OFF) response time is defined as the
time interval between the sudden connection (removal) of the
ring signal across TIP and RING and the subsequent ON (OFF)
transition of Ai.
RDCLK is provided to the user in both asynchronous and synchronous communications. RDCLK is not necessary in asynchronous communication but it can be used to supply a clock for
UART/USARTtiming (RDCLK is not valid in FSK). RDCLK is necessary for synchronous communication.
Table 9_
Received Line Signal Detector (RLSD)
The RLSD thresholds for both high and low channels are:
RI Response Time
RI Transition
Response Time
OFF-Io-OW
ON-Io-OFF
110 ± 50 ms (50% duly cycle)
450 ±50 ms
Note: 'The OFF-Io-ON lime is duly cycle dependent:
890 ms (15%) 2: lime;,: 50 ms (100%)
RLSD ON 2: - 43 dBm
RLSD OFF :5 - 48 dBm
1-42
2400 bps Full-Duplex Modem
R2424
rupt. Any of these sources can drive the host interrupt input low,
and the interrupt servicing process continues until all interrupts
have been cleared and all IRQ sources have returned to their
high impedance state. Because of the open-drain structure of
IRQ, an external pull-up resistor to + 5 volts is required at some
point on the IRQ line. The resistor value should be small enough
to pull the IRQ line high when all IRQ drivers are off (i.e., it must
overcome the leakage currents). The resistor value should be
large enough to limit the driver sink current to a level acceptable
to each driver. For the case where only the modem IRQ driver is
used, a resistor value of 5.6K ohms ± 20%, 0.25 watt, is
sufficient.
MICROPROCESSOR INTERFACE
Seventeen hardware circuits provide address, data, control, and
interrupt signals for implementing a parallel interface compatible
with an 8080 microprocessor. With the addition of a few external
logic gates, the interface can be made compatible with a wide
variety of microprocessors such as 6500, 6800, or 68000.
The microprocessor interface allows a host microprocessor to
change modem configuration, read or write channel data as well
as diagnostic data, and supervise modem operation by means of
soft strappable control bits and modem status bits. The significance of the control and status bits and methods of data interchange are discussed in a later section devoted to software circuits. This section describes the operation of the interface from a
hardware standpoint.
DAAINTERFACE
The R2424M provides a Data Access Arrangement (DAA) interface that is directly hardware and software compatible with the
RDAA. Manual/automatic originate and answer are then controlled via the appropriate R2424M hardware ancillary circuits or
software control bits. The modem provides the only interface with
the microprocessor (MPU) bus, i.e., no RDAA interface signals
must be directly controlled from the MPU bus.
Chip Select (CSO and CS1) and
Register Selects (RSO-RS1)
The signal processor to be accessed is selected by grounding
one of two unique chip select lines, CSI or CSO. The selected
chip decodes the four address lines, RS3 through RSO, to select
one of sixteen internal registers. The most significant address bit
(23) is RS3 while the least significant address bit (2°) is RSO.
Once the address bits have been decoded, the selected register
can be read from or written into via an 8-bit parallel data bus, D7
through DO. The most significant data bit (27) is D7 while the
least significant data bit (2°) is DO.
Ring Detect (RD)
RD indicates to the modem by an ON (low) condition that a ringing signal is present. The signal (a 4N35 optoisolator compatible
output) into the RD input should not respond to momentary
bursts of ringing less than 125 ms in duration, or to less than
40 Vrms, 15 to 68 Hz, appearing across TIP and RING with
respect to ground. The ring is then reflected on AI.
Read Enable (READ) and
Write Enable (WRITE)
Request Coupler Cut Through (RCCT)
Reading or writing is activated by pulsing either the READ line
high or the WRITE line low. During a read cycle, data from the
selected register IS gated onto the data bus by means of threestate drivers. These drivers force the data lines high for a one bit
or low for a zero bit. When not being read, the three-state drivers
assume their off, high-impedance, state. During a write cycle,
data from the data bus is copied into the selected register, with
high and low bus levels representing one bits and zero bits,
respectively. The timing required for correct read/write cycles is
illustrated in Figure 2. Logic necessary to convert the single Rm
output from a 65XX series microprocessor to the separate READ
and WRITE signals required by the modem is shown in Figure 3.
RCCT is used to request that a data transmission path through
the DAA be connected to the telephone line. When RCCT goes
OFF (low), the cut-through buffers are disabled and CCT should
go OFF (high). RCCT should be OFF during dialing but ON for
tone address signaling.
Coupler Cut Through (CCT)
An ON (low) signal to the CCT lead indicates to the modem that
the data transmission path through the DAA is connected. ThiS
input can always be grounded if the two second billing delay
squelch is desired. If CCT is user controlled, the billing delay
squelch can only be 2 seconds or greater.
Interrupt Request (IRQ)
Off-Hook Relay Status (OH)
The final signal on the microprocessor interface is Interrupt
Request (IRQ). This signal may be connected to the host microprocessor interrupt request input in order to interrupt host program execution for modem service. The use of IRQ is optional
and the method of software implementation is described in a
subsequent section, Software Circuits. The IRQ output structure
is an open-drain field-effect-transistor (FET). This form of output
allows IRQ to be connected in parallel to other sources of inter-
The modem provides an OH output which indicates the state of
the OH relay. A high condition on OH implies the OH relay is
closed and the modem is connected to the telephone line (offhook). A low condition on OH implies the OH relay is open (i.e.,
the modem is on-hOOk). The delay between the low-to-high or
high-to-Iow transition of OH and the subsequent close-to-open or
open-to-close transition of the OH relay is 8 ms maximum.
1-43
D
2400 bps Full-Duplex Modem
R2424
WRITE
READ
CSi
(i
= 0,1)
RSi
= 0-3)
(i
READ
Di
= 0-7)
(i
Characteristic
CSi, RS. setup time prior
to Read or Write
Data access time after Read
Data hold t.me after Read
CSi, RSi hold time after
Read or Write
Write data setup time
Wnte data hold time
Write strobe pulse width
Figure 2.
_2
Symbol
Min
TCS
TDA
TDH
30
TCH
TWOS
TWDH
TWR
10
75
10
75
10
Max
Units
140
50
ns
ns
ns
ns
ns
ns
ns
Microprocessor Interface Timing Diagram
~
I
READ
R2424
MODEM
WRITE
R/W
Figure 3.
R/Iii to READ WRITE Conversion Logic
1-44
R2424
2400 bps Full-Duplex Modem
ANALOG SIGNALS (R2424M)
TO
(
NETWORK
Two connections are devoted to analog audio signals: TXA and
RXA.
-----e-+---r--
) TO OTHER
EQUIPMENT
--,
11:2134516: R2424
MODEM JACK
MINIATURE
I
I
I I
6 POSITION JACK IL. ________
..J
IA
AI
Transmit Analog (TXA)
The TXA output is suitable for driving a data access arrangement
for connection to either leased lines or the public switched telephone network. The transmitter output impedance is 604 ohms
± 1% with an output level of + 6 dBm ± 1 dBm. To obtain a
dBm output, a 600 ohm load to ground is needed.
r------,
i tI j3j4j +! II
i
MINIATURE
I
6 POSITION PLUG
o
RING (RED
W~: J
TELEPHONE
CORD
t ~I;(GREEN
WIRE)
Receive Analog (RXA)
Figure 4.
RXA is an input to the receiver from a data access arrangement.
The input impedance is 23. 7K ohms ± 1 %. The received level at
RXA must be no greater than - 9 dBm (or - 6 dBm with the 3DB
bit enabled).
RJll Telephone Jack
ANCILLARY CIRCUITS
Transmit Baud Clock (TBCLK) and
Received Baud Clock (RBCLK)
ANALOG SIGNALS (R2424DC)
TBClK and RBClK are provided to the user at the baud rate
(600 Hz).
Three analog signals are output by the R2424DC: LINE MONITOR, TIP and RING.
Talk (TLK) (DIN Module Only)
TlK is an input which manually places the modem on-hook (relay
open, TlK = 0) or off-hook (relay closed, TlK = 1). Theon-hook
condition is referred to as TALK mode and the off-hook condition
is referred to as DATA mode. TlK is used with ORG to manually
originate or answer a call. TlK should be 0 at power-on or reset to
prevent the modem from inadvertently entering the data mode.
Analog Line Monitor (LINE MONITOR)
The LINE MONITOR output is suitable for a speaker interface. It
provides an output for all dialing signals, call progress signals,
and the carrier signals. The output impedance is 15K ohms
± 1%. The signals which appear on LINE MONITOR are approximately the same level as the signals would appear on the network (assuming a 1 dB loss attributed to the audio transformer).
Originate (ORG)
ORG is an input which manually places the modem in the originate mode (ORG = OL£l:..!!1e answer mode (ORG = 1). To manually originate a call, ORG = 0 and TlK = O. Dial the number
using the telephone. When the other modem answers and sends
answer tone switch the TlK input from 0 to 1 placing the modem
off-hook.
Phone Line Interface (TIP and RING)
TIP and RING are the DAA analog outputs to the public switched
telephone network. These outputs use two RJ 11 jacks in parallel
as the interface to the network (see Table 10 and Figure 4). The
R2424DC, which contains the DM TIP and RING interface, has
been FCC Part 68 approved. The user need not apply for further
Part 68 approval. The impedance of TIP with respect to RING is
600 ohms.
To manually answer a call ORG = 1 and TlK = O. When the
phone rings switch the TlK input from 0 to 1 placing the modem
off-hook.
Off-Hook Relay Status (OH)
Table 10.
Connector
Type
RJ11 Jack
R2424DC Network Interface
Pin
Number
3
4
The modem provides an OH output which indicates the state of
the OH relay. A high condition on OH implies the OH relay is
closed and the modem is connected to the telephone line (offhook). A low condition on OH implies the OH relay is open (Le.,
the modem is on-hook). The delay between the low-to-high or
high-to-Iow transition of OH and the subsequent close-to-open or
open-to-close transition of the OH relay is 8 ms maximum.
Name
Function
RING
TIP
One Side of TELCO Li ne
One Side of TELCO Line
1-45
o
R2424
2400 bps Full-Duplex Modem
interface memory. A set of sixteen a-bit registers, labeled register 0 through register F, can be read from or written into by either
the host processor or signal processor. The host communicates
via the microprocessor interface lines shared between the two
signal processors. The signal processor communicates via its
internal 1/0 bus. Information transfer from SP RAM to interface
memory is accomplished by the signal processor logic unit moving data between the SP main bus and the SP 1/0 bus. Two of the
16 addressable interface memory registers (Le., register 0 and
register E) have unique hardware connections to the interrupt
logiC. It IS possible to enable a bit m register E to cause an mterrupt each time it sets. This interrupt can then be cleared by a read
or write cycle from the host processor to register O. This operation is discussed in detail later m this section.
TID Relay. (DIP Module Only)
The TID Relay signal may be used as a second relay control
when the parallel control mode of operation is selected (BUS bits
oand 1 = 1). If the serial control mode is selected (BUS bits 0 and
1 = 0) the TID relay follows the status of the OH output signal
which is controlled by the MI signal. In the parallel control mode
the OH output signal is controlled by the status of the DATA bit,
while independent control of the TID relay is provided by the MI
signal. During pulse dialing the OH signal reflects the pulse signals being dialed. It is therefore possible to use the TID Relay
signal to control the off-hook relay and use the OH signal to perform pulse dialing on a separate, independent relay.
Manual Input (MI) (DIP Module Only)
Memory maps of the 32 addressable registers in the modem
receiver (CSO) and transmitter (CS1) interface memory are
shown in Figures 5 and 6, respectively. These registers may be
read or written on any host read or write cycle, but all eight bits of
that register are affected. In order to read a single bit or a group of
bits in a register, the host processor must mask out unwanted
data. When writing a single bit or group of bits in a register the
host processor must perform a read-modify-write operation. That
is, the entire register is read, the necessary bits are set or reset in
the accumulator of the host, then the original unmodified bits and
the modified bits are written back into the register of the interface
memory.
MI is an input which manually places the modem on-hook (relay
open, MI = 0) or off-hook (relay closed, MI = 1). The on-hook
condition is referred to as TALK mode and the off-hook condition
is referred to as DATA mode. MI is used with ORG to manually
originate or answer a call. MI should be 0 at power-on or reset to
prevent the modem from inadvertently entering the data mode.
SOFTWARE CIRCUITS
Operation of the microprocessor interface circuits was described
in the hardware section from the standpoint of timing and loadIdrive characteristics. In this section, operation of the microprocessor interface is described from a software standpoint.
Figures 7 and a show the registers according to the overall function they perform in the receiver and transmitter, respectively.
Figures 9 through 12 show the power on configurations of the
interface memory bits for the R2424/US and the R2424/1NT versions.
The modem is implemented in firmware running on two special
purpose signal processors. These signal processors share the
computing load by performing tasks that are divided into two
areas. These areas are partitioned into receiver and transmitter
devices.
Table 11 defines the individual bits in the interface memory. In the
Table 11 descriptions, bits in the interface memory are referred to
using the format Y:Z:Q. The chip number is specified by Y (0 or
1), the register number by Z (0 through F), and the bit number by
Q (0 through 7, with 0
LSB).
INTERFACE MEMORY
Each signal processor can communicate with the host processor
by means of a specialized, dual-port, scratch-pad memory called
=
1-46
2400 bps Full-Duplex Modem
R2424
~
7
Register
2
1
0
~
NEWC
-
-
-
E
IRQ
ENSI NEWS
-
LCD
RSD
0
BUS
CRQ DATA AAE
-
-
-
C
DSRA
-
AL
3
4
5
6
RAM Access R
F
-
E
IRQ
ENSI NEWS
0
BUS
CRQ
-
C
-
-
B
-
-
-
-
A
ERDL
RDL
DL
ST
9
-
-
8
TONE
ATD
-
-
7
6
-
4
-
1
ERDL
-
-
-
-
9
NAT'
-
-
-
TM
RLSD
8
DLO
-
-
-
-
-
-
7
-
-
-
6
GTE
RTRN ORG
LL
CTS
DSR
RI
-
-
-
-
-
-
GTS
3DB
ST
DL
RDL
CC
EF
NTS
-
-
-
-
-
-
-
-
RAM Data YTM (YRAMTM)
5
RAM Data YRL (YRAMRL)
4
RAM Data YTL (YRAMTL)
3
RAM Data XTM (XRAMTM)
0
-
-
RAM Data XTL (XRAMTL)
2
RAM Data XRL (XRAMRL)
-
-
-
-
-
-
1
-
-
-
-
-
0
AL
SSD
RTS
RAM Data XRM (XRAMRM)
-
DTMF
DDRE
MODE
4
1
DLSF'
-
DTR
3
2
0
-
NEWC DDEI
CHAR
TXCLK
TX LEVEL
A
-
RAM Data YRM (YRAMRM)
2
3
RAM Access T
B
MODE
-
5
6
F
CHAR
SPEED
-
5
7
Register
-
-
-
-
-
-
Dial Digit Register
Notes
Note
(-) Indicates reserved for modem use only.
Figure 5.
~
Register
7
1. Not valid before R5310-22
(-) Indicates reserved for modem use only.
Receiver (CSO) Interface Memory Map
I
F
6
I
5
I
4
I
DIAGNOSTIC
3
I
2
I
1
I
Figure 6.
I~
0
Register
CONTROL
E
HANDSHAKE
Transmitter (CS1) Interface Memory Map
7
I
6
I
5
I
4
I
DIAGNOSTIC
F
3
I
2
HANDSHAKE
CONFIGURATION
0
CONFIGURATION
0
C
CONFIGURATION
C
CONFIGURATION
B
CONFIGURATION
B
CONFIGURATION
A
CONFIGURATION
A
CONFIGURATION
CONFIGURATION
9
STATUS
9
8
STATUS
8
STATUS
7
RESERVED
7
RESERVED
6
RESERVED
6
RESERVED
5
DIAGNOSTIC
5
DIAGNOSTIC
DIAGNOSTIC
4
DIAGNOSTIC
4
3
DIAGNOSTIC
3
DIAGNOSTIC
2
DIAGNOSTIC
2
DIAGNOSTIC
1
RESERVED
1
RESERVED
0
RESERVED
0
~
Bit
Figure 7.
7
I
6
I
5
I
4
I
3
I
2
I
1
I
~
0
BII
Figure 8.
Receiver (CSO) Interface Memory Functions
1-47
7
I
6
I
5
DIGIT
I
4
I
1
I
0
CONTROL
E
DIAL
I
REGISTER
3
I
2
I
1
I
0
Transmitter (CS1) Interface Memory Functions
2400 bps Full-Duplex Modem
R2424
~~
7
Registe
6
5
4
2
3
1
~
0
F
0
0
0
0
0
0
0
0
E
IRQ
ENSI
NEWS
0
0
-
NEWC
0
-
-
0
BUS
CRQ
-
-
RSD
0
-
LCD
0
1
0
-
-
-
1
0
-
-
-
-
A
ERDL
RDL
DL
ST
9
-
-
8
TONE
ATD
0
0
7
-
6
-
C
B
0
0
0
CHAR
0
0
-
0
0
-
AL
MODE
0
0
1
7
Register
RAM Access R
6
5
4
F
0
0
0
E
IRQ
ENSI
NEWS
0
0
0
-
0
BUS
CRQ
DATA
0
0
0
C
DSRA
0
0
0
0
0
-
DDRE
0
AAE
DTR
0
-
-.
SSD
0
0
-
-
DLSF
1
GTE
GTS
3DB
DTMF
AL
0
0
0
0
0
NEWC DDEI
CHAR
0
TX LEVEL
0
B
0
0
0
ERDL
RDL
ST
0
0
DL
0
0
1
1
0
1
CC
EF
NTS
MODE
-
-
-
-
9
NAT
RTRN
ORG
LL
0
0
0
RTS
0
0
0
0
0
0
-
RLSD
CTS
0
8
DLO
0
-
-
7
-
-
-
-
-
6
-
-
-
-
-
-
-
-
TM
-
-
-
-
-
SPEED
DSR
RI
0
0
0
0
-
-
-
-
-
-
-
-
5
4
RAM Data VRL (Random)
4
RAM Data VTL (Random)
3
RAM Data XRM (Random)
3
RAM Data XTM (Random)
RAM Data XRL (Random)
2
~
Bit
-
-
7
6
RAM Data VTM (Random)
RAM Data XTL (Random)
2
-
-
-
-
1
-
-
-
-
-
-
0
5
4
3
2
1
0
~
-
7
Bit
Figure 10.
10:;;;::::
,~~i
7
Reglste
F
I
6
I
5
I
I
4
3
I
2
RAM Access R
-
6
5
4
I
1
I
I~~
0
Reglste
i
7
6
I
5
i
0
0
0
0
F
0
0
0
E
IRQ
ENSI
NEWS
0
-
-
-
E
IRQ
0
-
NEWC
0
ENSI
NEWS
0
0
0
-
0
BUS
CRQ
-
-
RSD
DATA
0
0
BUS
1
-
CRQ
0
-
LCD
0
0
0
0
-
-
-
0
-
-
C
-
-
-
-
-
DSRA
1
A
ERDL
RDL
0
0
DL
1
1
0
1
9
-
-
-
-
-
8
TONE
ATD
-
7
6
B
-
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
0
5
0
I
NEWC DDEI
0
AAE
DTR
0
0
-
0
0
3DB
DTMF
AL
0
0
0
0
0
0
DL
ST
0
DLSF
0
ERDL
0
0
0
0
1
1
0
1
-
9
NAT
RTRN
ORG
LL
0
0
0
CC
EF
0
RTS
NTS
TM
RLSD
CTS
DSR
RI
0
8
DLO
0
0
0
0
0
-
-
-
7
-
-
-
-
-
-
6
-
-
-
-
-
0
RDL
MODE
0
0
-
-
-
-
-
-
-
-
-
-
-
-
0
4
RAM Data VTL (Random)
RAM Data XTM (Random)
RAM Data XRL (Random)
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
7
6
5
4
3
2
1
0
0
RAM Data VTM (Random)
5
3
Figure 11.
SSD
GTS
CHAR
RAM Data YRL (Random)
BII
DDRE
1
RAM Data XRM (Random)
~
0
-
GTE
0
TX LEVEL
4
0
0
-
3
1
1
I
0
A
RAM Data VRM (Random)
2
I
1
0
0
TXCLK
0
0
2
0
0
MODE
0
0
B
ST
SPEED
0
3
RAM Access T
0
AL
I
4
0
CHAR
1
I
0
C
2
3
R2424/US Transmitter (CS1) Interface Memory
Power On Configuration
0
0
-
-
(-) Indicates reserved for modem use only.
R2424/US Receiver (CSO) Interface Memory
Power On Configuration
1<:::::
-
-
Dial Digit Register (Write-Only Register)
(-) Indicates reserved for modem use only.
Figure 9.
0
0
A
flAM Data VRM (Random)
0
0
0
5
1
0
1
0
TXCLK
0
2
3
RAM Access T
RAM Data XTL (Random)
-
1
-
-
-
-
-
Dial Digit Register (Write-Only Register)
0
~
Bit
(-) Indicates reserved for modem use only.
7
6
5
4
3
2
1
0
(-) Indicates reserved for modem use only.
R2424/INT Receiver (CSO) Interface Memory
Power On Configuration
Figure 12.
1-48
R2424/INT Transmitter (CS1) Interface Memory
Power On Configuration
R2424
2400 bps Full-Duplex Modem
Table 11. Interface Memory Definitions
Mnemonic
AAE
Name
Auto Answer Enable
Memory
location
1:D:4
When configuration bit AAE IS a 1, the modem will automatically answer
when a ringing signal IS present on the line. When AAE is set to a 1, the
modem will answer after one ring and go Into data mode
The modem goes off·hook 1 second after the on·to·off transition of the ring
The ORG pin or ORG bit need not to be set to the answer polarity. I! it IS
desired to answer after more than one ring, then the user must use the
alternative answer method described under the DATA bit. The DTR pin or
the DTR bit must also be set before the modem will auto answer. Writing a
into the AAE bit will cause the modem to go on·hook. ThiS will occur only
when the modem auto answers using the AAE bit.
Al
Analog loopback
(0,1):B:O
D
Description
°
When configuration bits AL are a 1, the modem is in local analog loopback
(V.54 Loop 3). In this loop, the transmitter's analog output is coupled to the
receiver's analog input at a paint near the modem's telephone line interface
An attenuator IS Introduced Into the loop such that the signal level coupled
into the receive path IS attenuated 14 ± 1 dBm. The modem may be placed
into analog loopback in either the Idle mode or the data mode However, In
the data mode, setting the AL bits to a 1 will terminate the connection
Analog loopback will only function in the high speed modes (2400, 1200, or
600 bps).
The DTE may be tested when the modem is In analog loopback. Also, all
parts of the modem except the line interface are checked If no DTE is
connected, the modem integrity may be verified by use of the self test
function. When entering analog loopback, set AL in the receiver to a 1 before
setting AL in the transmitter to a 1
When exiting analog loopback, reset AL in the transmitter to a
resetting AL in the receiver to a 0.
ATD
Answer Tone Detected
0:8:6
°before
When status bit ATD is a 1, It Signifies that the modem receiver detected the
answer tone. The bit is 1 set 75 ms after the answer tone is first detected,
and is cleared to a when the modem goes on-hook The user may clear
ATD manually after CTS is active.
°
BUS
Bus Select
(0,1):0:7
When configurallon bits BUS are a 1, the modem IS In the parallel control
mode; and when 0, the modem IS In the serial control mode BUS can be In
either state to configure the modem.
Serial Control Mode
The senal mode uses standard V.24 (RS-232-C compatible) Signals to
transfer channel data. The control Signals used in serial control mode are
DTR, RTS, TLK, and ORG. Outputs such as RLSD and DSR are reflected
both in the interface memory and the V.24 interface. Once the bus bits have
been set to a 0, the state of the DTR, RTS, DATA, and ORG bits are
ignored.
Parallel Control Mode
The modem has the capability of modem control via the microprocessor bus
Data transfer is maintained over the senal V.24 channel The control bits
used in parallel control are DTR, RTS, ORG, and DATA.
The modem automatically defaults to the senal mode at power-on.
I! the parallel control mode is to be used, It IS recommended that the 'ilK pm
be tied to ground A floating TLK pin Will assume a logiC 1 which will
Immediately put the modem into the data mode before the BUS bits are set
In either mode, the modem IS configured by the host processor via the
microprocessor bus
1-49
R2424
2400 bps Full-Duplex Modem
Table 11. Interface Memory Definitions (Continued)
Mnemonic
CC
Name
Controlled Carner
Memory
Location
1:9:2
Description
When configurallOn bit CC is a " the modem operates In controlled carner;
when 0, the modem operates in constant carrier.
Controlled carner allows the modem transmitter to be controlled by the RTS
pin or the RTS bit. Its effect may be seen In the RTS and CTS descriptions.
CHAR
Character Length Select
(O,1):C:(3,4)
These character length bits select either 8, 9, 10, or 11 bit characters
(Includes data, stop, and start bits) as shown below:
Configuration Word
!
~
o
o
o
1
1
Configuration
1
8 bits
9 bits
1
10 bits
11 bits
o
It IS possible to change character length dUring the data mode. Errors In the
data will be expected between the changeover and the resynchronization
(which occurs on the next start bit after the change is implemented).
CRO
Call Request
(0,1):0:6
When configuration bit CRO in chip 1 (the transmitter) IS a I, it places the
transmitter in auto dial mode. The data then placed in the Dial Digit Register
IS treated as digits to be dialed. The format for the data should be a hex
representation of the number to be dialed (if a 9 is to be dialed then an 09 16
should be loaded in DDR) CRO in chip 1 should be a 1 for the duration of
the data mode. If CRO in chip 1 is changed to a 0, the modem will go
on-hook. Also, see DDRE bit.
into tone detect mode. Any energy above threshold and in the 345 to 635 Hz
bandwidth IS reflected by the TONE bit. CRO in chip 0 must be reset to a 0
(after the last digit was dialed and tone detection completed) before the
answer tone IS sent by the answering modem (after ringback is detected).
CRO in chip 0 need not be used during auto dialing, but may be used to provide call progress information as part of an intelligent auto dialing routine. An
example flowchart is given In Figure 13.
FF (hex) should be loaded into the Dial Digit Register after the last digit is
dialed and tone detection is completed. This action also puts the modem In
data mode and starts a 30 second abort timer. If the handshake has not
been completed in 30 seconds the modem will go on-hook.
CTS
Clear-to-Send
1:8:6
When status bit CTS is a I, it indicates to the terminal equipment that the
modem will transmit any data which are present at TXD.
CTS response times from an ON or OFF condition of RTS are shown below:
CTS Transition
OFF to ON
ON to OFF
• Programmable
Constant Carrier
s2 ms
s20 ms'
Controlled Carrier
210 to 275 ms
s20 ms'
DATA
Talk/Data
1'0:5
When control bit DATA is a I, the modem IS in the data state (off-hook); and
when 0, the modem is in the talk state (on-hook). This bit allows the modem
to go off-hook after a programmable number of rings by counting the required
number of RI bit tranSItions and then setting the DATA bit (assuming ORG = 0).
DDEi
Dial Digit Empty Interrupt
1:E:2
When handshake bit DOE I IS a I, an interrupt will occur when the Dial Digit
Register (1 :0) is empty (DDRE = 1). This is independent of the state of the
ENSI bit. The interrupt will set the IRO bit and also assert the IRO signal.
Loading the Dial Digit Register with a new digit will clear the interrupt
condition.
1-50
R2424
2400 bps Full-Duplex Modem
Table 11. Interface Memory Definitions (Continued)
Mnemonic
Name
DDR
Dial Digit Register
DDRE
Dial Digit Register Empty
Memory
Location
1:0:(0-7)
I:E:O
Description
DDR is used to load the digits to be dialed. Example: If a 4 IS to be dialed,
an 04 (hex) should be loaded. This actIon also causes the Interrupt to be
cleared. The modem automatIcally accounts for the interdlgit delay. Note:
DDR is a write-only register
When handshake bit DDRE IS a I, it indicates that the dIal dIgIt regIster IS
empty and can be loaded with a new digit to be dialed. If the DDEI bIt IS set,
the IRQ bit will be set when the DDRE bit IS set. Also, the IRO signal will be
generated.
After the DDR is loaded, DDRE goes to a 0 and the Interrupts are
automatically cleared.
DL
Digital Loopback (Manual)
(O,I):A:5
When configuration bits DL are set to a I, the modem is manually placed In
digital loopback. DL should only be set during the data mode. The DSR and
CTS bits will be reset to a O. The local modem can then be tested from the
remote mode,m end by looping a remotely generated test pattern. At the
remote modem, all interface circuits behave normally as in the data mode.
At the conclusion of the test, DL must be reset to a O. The local modem WIll
then return to the normal data mode wIth control reverting to the DTEs, DTR.
DL does not function in 300 bps.
DLO
Dial Line Occupied
1:8:7
When status bit DLO is a I, it indicates that the modem IS in the auto dial
state, i.e., CRO in the transmitter is a 1 and the modem is off-hook and
ready to dial.
DLSF
Disable Low Speed Fallback
I:C:O
When configuration bit DLSF is a I, the modem WIll not automatIcally
fallback to the 300 bps operating mode if it is configured for another data
rate. This bit is valid in origInate mode only.
DSR
Data Set Ready
1:8:5
The ON condition of the status bit DSR indicates that the modem is In the
data transfer state. The OFF conditIon of DSR is an indIcation that the DTE
IS to disregard all signals appearing on the interchange cIrcuIts - except RI
DSR will switch to the OFF state when in test state. The ON condition of
DSR indIcates the following:
The modem is not in the talk state, I.e., an associated telephone handset IS
not in control of the lone.
The modem is not in the process of automatically establishIng a call via
pulse or DTMF dIaling.
The modem has generated an answer tone or detected answer tone.
After ring indicate goes ON, DSR walts at least two seconds before turning
ON to allow the telephone company equipment to be engaged
DSR will go OFF 50 msec after DTR goes OFF, or 50 msec plus a maxImum
of 4 sec when the SSD bit is enabled.
DSRA
Data Set Ready in Analog
Loopback
I:C:7
When configuratIon bIt DSRA IS a I, It causes DSR to be ON during analog
loopback.
1-51
2400 bps Full-Duplex Modem
R2424
Table 11. Interface Memory Definitions (Continued)
Mnemonic
DTMF
Name
Touch Tones/Pulse Dialing
Memory
Location
I:B:l
Deecrlptlon
When configuration bit DTMF is a I, it tells the modem to auto dial using
tones; and when 0, the modem will dial using pulses.
The timing for the pulses and tones are as follows (power-on timing):
Pulses -
Relay open 64 ms
Relay closed 36 ms
Interdigit delay 750 ms
Tones -
Tone duration 95 ms
Interdiglt delay 70 ms
The DTMF bit can be changed during the dialing process to allow either tone
or pulse dialing of consecutive digits. The output power level of the DTMF
tones is as follows:
'-
--
--
± 15 dBm ± 1 measured ai TXA for the R2424M
-1 dBm ± 1 measured at TIP/RING for the R2424DC
DTR
Data Terminal Ready
1:0:3
Control bit DTR must be a 1 for the modem to enter the data state, either
manually or automatically. DTR must also be a 1 in order for the modem to
automatically answer an incoming call.
During the data mode, DTR must remain at a I, otherwise the connection will
be terminated if DTR resets to a 0 for greater than 50 ms.
1:9:1
Enable Filters
ENSI
Enable New Status Interrupt
(O,I):E:6
When handshake bit ENSI is a I, It causes an interrupt to occur when the
status bits in registers (0:[8,9]) and (1 :8) are changed by the modem.
(NEWS-I). The IRQ bit will be set to a 1 and the IRQ signal will be
generated. The interrupt is cleared by writing a 0 into the NEWS bit.
ERDL
Enable Response to
Remote Digital Loopback
(O,I):A:7
When configuration bits ERDL are a I, It enables the modem to respond to
another modem's remote digital loopback request, thus going into loopback.
When this occurs, the modem clamps RXD to a mark; resets the CTS, DSR
and RLSD bits to a 0 and turns the CTS, DSR and RLSD signals to a logiC 1.
The TM bit is set to inform the user of the test status. When the ERDL bits are
a 0, no response will be generated.
GTE
_Guard Tone Eneble
I:B:4
When configuration bit GTE is a I, it causes the specified guard tone to be
transmitted (CCITT configurations only), according the state of the GTS bit. Note:
The guard tone will only be transmitted by the answering modem.
:
c
Setting CRQ in the transmitter to a 1 disables the high and low band filters
used in data mode so that call progress tone detection can be done. Setting
CRQ in the receiver to a 1 inserts a passband filter in the receive peth which
passes energy In the 345 Hz to 835 Hz bandwidth ThA high "nrtl.,... "~_n(!
filters must be enabled and the passband filter disabled for the answer tone
and carrier to be detected. This occurs automatically during the auto dial
process when EF Is set to a O. In this case, the high and low band filters are
disabled when CRQ in the transmitter Is set to a 1. If tone detection is
required, CRQ in the receiver should be set to a 1. After dialing and call
progress tone detection, CRQ in the receiver is set to a 0 and FF is loaded
Into the dial digit register. (Loading FF enables the high and low band filters).
At this time, the answer tone can be detected. To re-enable the high and low
band filters disabled by setting CRQ In the transmitter, set EF to a 1. After
CRQ in the transmitter and receiver is set to a 1 and tone detection Is
completed, it may be necessary to detect the answer tone before loading FF
Into the dial digit register (see the section on sending 1300 Hz calling tone).
At that point, EF can be set to a 1 and CRQ In the receiver set to a 0 so the
answer tone can be detected (using the ATD bit) and the 1300 Hz calling
tone can still be sent. Once the answer tone Is detected, FF should be
loaded into the dial digit register and the EF bit set to a O.
EF
1-52
R2424
2400 bps Full-Duplex Modem
Table 11. Interface Memory Definitions (Continued)
Mnemonic
Name
GTS
Guard Tone Select
IRO
Interrupt
LCD
Loss of Carrier Disconnect
Memory
Location
Description
I:B:3
When configuration bit GTS is a 0, It selects the 1800 Hz tone; when GTE is
a 1 it selects the 550 Hz tone. The selected guard tone will be transmitted
only when GTE is enabled.
(0,1):E:7
When status bit IRO is a 1. it indicates that an interrupt has been generated.
The IRO hardware signal is generated following the setting of the IRO bit.
IRO is cleared when either the NEWS bit is reset to a 0 or the DDR is
loaded with a number.
0:D:2
When configuration bit LCD is a 1. the modem terminates a call when a loss
of received carrier energy is detected after 400 ms. After the first 40 ms of
loss of carrier. RLSD goes off. 360 ms later. if no carrier is detected, CTS
goes off. and the modem goes on-hook. If energy above threshold is
detected during the 360 ms period. RLSD will be set to a 1 again. If further
loss of energy occurs, the 400 ms time frame is restarted.
If LCD is set to a O. RLSD will be set to a 1 when energy is above threshold,
but will not force the modem on-hook when energy falls below threshold. In
this case, it is necessary to re-enable LCD in order to put the modem on-hook.
LCD is not automatically disabled in leased line operation. The user must
write a 0 into LCD bits for this to occur.
LL
Leased Line
1:9:4
MODE
Mode Select
(0,1 ):A:(0,3)
When configuration bit LL is aI, the modem is in leased line operation;
when 0, the modem is in switched line operation. When LL is set to aI, the
modem immediately goes off-hook and into data mode.
These bits select the compatibility at which the modem is to operate, as
shown below:
Configuration Word
~
~
!
~
0
0
0
0
0
0
0
1
0
0
1
0
1
1
0
0
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
1
1
0
1
1
0
0
1
1
1
0
1
1
1
0
1
1
1
1
Configuration
Bell 2400
Bell 2400
Bell 212A
Bell 212A
Be1l212A
V.22A
V.22B
V.22A
V.22B
V.22 bis
V.22 bis
V.22 bis
V.22 bis
2400 Sync.
2400 Async.
1200 Sync.
1200 Async.
o to 300 Async.
1200 Sync.
1200 Async.
600 Sync.
600 Async.
2400 Sync.
2400 Async.
1200 Sync.
1200 Async.
NOTE: The Mode bits in both chips should be set exclusively of all other
bits, followed immediately by the setting of the NEWC bits. This will ensure
proper modem configuration.
Automatic Reconfiguration
The modem is capable of automatically falling back during the handshake to
the compatibility of a remote modem. The modem can be in either the
answer or originate mode for this to occur. The compatibilities that the
modem are limited to adapt to are V.22 bis, V.22 AlB (1200 bps), Bell 212
and Bell 103. If the R2424 is to originate in a specific configuration, the
MODE bits must be set.
When the answer modem is configured for Bell 300 asynchronous and is
called by a 1200 bps modem, the handshake will be completed at 1200 bps.
NAT
No Answer Tone
1:9:7
When configuration bit NAT is aI, the modem will not transmit the 2100 Hz
CCITT answer tone. This bit is only valid for CCITT configurations. With this
bit enabled in answer mode, when the modem goes off-hook it will remain
silent for 75 ms and then transmit unscrambled ones.
1-53
D
R2424 ,
2400 bps Full-Duplex Modem
Table 11.
Mnemonic
Name
Interface Memory Definitions (Continued)
Memory
Location
Description
NEWC
New Configuration
(0,1)'E:3
When the NEWC bit is a 1, it tells the modem that a new configuration has
been written into the configuration registers. The modem will then read the
configuration registers and then reset NEWC to a O. NEWC must be set to a
1 after.a new configuration has been written into the following registers:
(O:[A-D]) and (1 :[9-D]), The remaining registers do not require the use of
NEWC t6 tell the modem that new data was written into them,
NEWS
New Status
(0,1):E:5
When handshake bit NEWS is a 1, it tells the user that there has been a
ohange of status in the status registers. The user must write a 0 into NEWS
to reset it. This action also causes the interrupt to be cleared.
NTS
No Transmitter Scrambler
1:9:0
When configuration bit NTS is a 1, when the modem is off-hook it will
transmit all data in an unscrambled form. This bit should be disabled if the
normal modem handshake is desired.
ORG
Originate/Answer
1:9:5
When confIguration bit ORG is a 1, the modem is in originate mode; and
when a 0 the modem is in answer mode. (This is only valid in manual
originate/answer and analog loopback). If ORG is a 1 in analog loopback, the
modem will transmit in the high band and receive in the low band. If ORG is
a 0 In analog loopback, the modem will transmit in the low band and receive
m the high band.
(None)
RAM Access R
0:F:0-7
Contains the RAM access code used in reading RAM locations in chip 0
(receiver device).
(None)
RAM Access T
1:F:0-7
Contains the RAM access code used in reading RAM locations in chip 1
(transmitter device).
XRAMRL
RAM Data XRL
0:2:0-7
Least significant byte of 16-bit word X used in reading RAM locations in chip O.
XRP..~.~RM
R.A.~.~
XRAMTL
RAM Data XTL
1:2:0-7
Least significant by1e of 16-blt word X used in reading RAM locations in chip 1.
XRAMTM
RAM Data XTM
1:3:0-7
Most significant byte of 16-bit word X used in reading RAM locations in chip 1.
YRAMRL
RAM Data YRL
0:4:0-7-
Least significant by1e of 16-bit word Y used in reading RAM locations in chip O.
YRAMRM
RAM Data YRM
0:5:0-7
Most significant byte of 16-bit word Y used in reading RAM locations in chip O.
YRAMTL
RAM Data YTL
1:4:0-7
Least sIgnificant byte of 16-bit word Y used in reading RAM locations in chip 1.
YRAMTM
RAM Data YTM
1:5:0-7
Most significant byte of 16-bit word Y used in reading RAM locations in chip 1.
RDL
Remote DIgItal Loopback
(0,1):A:6
When configuration bits RDL are a 1, it causes the modem to initiate a
request for the remote modem to go into digital loopback. RXD is clamped to
a mark and the CTS bit and CTS signal will be reset until the loop is
established. The TM bit is not set in this case, since the local modem
initiated the requesl. RDL does not function in 300 bps.
RI
Ring Indicator
1:8:4
When status bit RI is a 1, It indicates that a rlngmg Signal is being detected.
The RI bit follows the ringing signal with a 1 dUring the on time and a zero
during the off time coincident with the Ai signal. The following are the RI bit
response times:
[):;:.!::. XRM
n.~.n
~
,~Y~v<;t ~;gii;fjCCiii\ by~~
01 ~ G-t;;t wvrd X
. RI Bit Transition
OFF-to-ON'
ON-to-OFF
u~t:ru iii
.-cQui(IY RAM iUl.idiium:l in cnip ii.
Response
110 ± 50 ms (50% duty cycle)
450 ±50 ms
'The OFF-te-ON time is duty cycle dependent· 890 ms (15%) " time" 50 ms (tOO%)
This OFF-to-ON (or ON-to-OFF) response time is defined as the time interval
between the sudden connection (removal) of the ring signal across TIP and
RING and the subsequent transItion of the RI bit.
1·54
R2424
2400 bps Full-Duplex Modem
Table 11.
Mnemonic
RLSD
Name
Received Line SIgnal
Detector
Interface Memory Definitions (Continued)
Memory
Location
0:8:0
Description
When status bit RLSD IS a I, it indIcates that the carrier has successfully
been receIved. RLSD wIll not respond to the guard tones or answer tones
RLSD response tImes are given below:
RLSD'
OFF-to-ON
ON-to-OFF
Constant
Carrier
Controlled
Carrier
40 to 65 ms
40 to 65 ms
40 to 65 ms
40 to 65 ms
Note:
1. After handshake has occurred.
RSD
Receive Space Disconnect
0:0:1
When configuration bit RSD is a I, the modem goes on-hook after receIving
approximately 1.6 seconds of continuous spaces.
RTRN
Retrain (2400 bps only)
1:9:6
When configuratIon bit RTRN is a I, the modem sends the training sequence. It resets when the training sequence from the remote modem has
successfully been received. If the sequence has not been successfully receIved from the remote modem, CTS will remain OFF. In order to put the modem
back in the data mode, it is necessary to write a 0 into the RTRN bit, then
repeat the retrain sequence.
RTS
Request-to-Send
1:93
When control bit RTS is a I, the modem transmits any data on TXD when
CTS becomes active. In constant carner mode, RTS should be set the same
tIme as DTR and then left ON. In controlled carrier operatIon, independent
operation of RTS turns the carner ON and OFF. The responses to RTS are
shown (assume the modem is in data mode).
RTS Off
Leased or Dial Line'
RTS On
Controlled Carrier
CTS OFF
Carner OFF
Carrier ON
210 to 275 ms Scrambled l's
Transmitted
CTS ON
Constant Carrier
CTS OFF
Carrier ON
Scrambled l's
Transmitted
CTSON
Carner ON
Data TransmItted
Note:
1. After handshake IS complete.
For ease of use in constant carrier mode, RTS should be turned ON the
same time as DTR.
SPEED
Speed IndIcation
0:9:(4,5)
The SPEED status bits reflect the speed at whIch the modem IS operating.
The SPEED bit representations are shown
~
0
0
1
1
~
0
1
0
1
Note:
The SPEED bits are not active
1-55
Speed
0-300
600
1200
2400
In
analog loopback and leased line mode.
R2424
2400 bps Full-Duplex Modem
Table 11.
Mnemonic
Name
SSD
Send Space Disconnect
ST
Self Test
Interface Memory Definitions (Continued)
Memory
Location
1"0:0
(O,I)'A:4
Description
When configuration bit SSD is a I, it causes the modem to transmit
approximately 4 seconds of spaces before disconnecting, when DTR goes
from active to Inactive state.
When configuration bit ST is a I, self test is activated. ST must be a 0 to end
the test. It IS possible to perform self test in analog loopback with or without a
DTE connected During any self test, TXD and RTS are ignored, Self test does
not test asynchronous-to-synchronous converter circuits in either the
transmitter or receiver.
Error detection is accomplished by monitoring the self test error counter in
the RAM. If the counter increments during the self test, an error was made.
The counter contents are available in the diagnostic register when the RAM
access code 00 is loaded in the diagnostic control register (O:F).
"
Self Test End-to-End (Data Mode)
Upon activation of self test an internally generated data pattern of ,alternate
binary ones and zeros (reversals) at the selected bit rate are applied to the
scrambler. An error detector, capable of identifying errors in a·stream of.
reversals are connected to the output of the descrambler.
Self Test with Loop 3
I
I'
i
Loop 3 IS applied to the modem as defined in Recommendation V.54. Self
test IS activated and DCE operation is as in the end-te-end test, In this test
DTR is ignored.
[.i
Self Test with Loop 2 (Data Mode)
The modem is conditioned to instigate a loop 2 at the remote modem as
specified in recommendation V,54. Self test is activated andDCE operation
is as in the end-ta-end tAst
ST does not function in 300 bps.
3DB
k
3 dB Loss to Receive
Signal
I:B.2
When configuration bit 3DB is a I, it attenuates the received signal 3 dB.
ThiS is only used If the modem will see 0 dBm or greater line signal at the
receiver input. Insertion of the 3 dB loss will then prevent saturation.
TM
Test Mode
0:8:1
When status bit TM is a I, it indicates that the modem has completed the
handshake and is in one of the following test modes: AL or RDL
TONE
Tone Detect
0:8:7
TONE follows the energy detected in the 340 to 640 Hz frequency band. The
user must determine which tone is present on the line by determining the ,
duty cycle of the TONE bit. TONE is active only when CRQ in chip O.ill a 1.
Detection Range: -10 to -43 dBm
Response Time: 17 ±2 ms
TXCLK
Transmit Clock Select
I:C:(5.6)
TXCLK allows the user to designate the origin of the transmitter data clock,
as shown below
Configuration Word
Transmit Clock
~
?
Internal
External
Slave
0
1
1
0
0
1
If external clock is chosen the user clock must be input at XTCLK. The clock
characteristics must be the same as TDCLK. The external clock will be
reflected by TDCLK.
If slave clock is chosen the transmitter is slaved to the receive clock, This is
also reflected by TDCLK.
1-56
R2424
2400 bps Full-Duplex Modem
Table 11.
Name
Mnemonic
TX LEVEL
Interface Memory Definitions (Continued)
Memory
Location
Transmit Level
1'B:(5-7)
Description
TX LEVEL allows the user to change the transmit level at TIP and RING
(assuming the DAA has 10 dBm attenuation in the transmit path).
Configuration
Word
7.
0
0
0
0
1
1
1
1
~
0
0
1
1
0
0
1
1
~
0
1
0
1
0
1
0
1
Transmit Level (± 1.0 dBm)
(at TIP and RING)
-10
-12
-14
-16
-18
-20
-22
-24
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
Internal Modem Timing
AUTO DIAL SEQUENCE
In a microprocessor environment it is necessary to know how
long various functions last or what the response times of certain
functions are. Since the modem is a part of the microprocessor
environment its timing and response times are necessary.
Table 12 provides the timing relationships between interface
memory bits and modem functions.
The following flow chart defines the auto dial sequence via the
microprocessor interface memory.
Table 12.
Internal Modem Timing
Parameter
Time Interval
NEWC bit checked
Transmitter
Receiver
Once per sample 1
Once per baud 2
NEWC bit set by host until
modem action
Transmitter
Receiver
,;; One baud time
One baud time
Control, Configuration bits read
Transmitter
Receiver
Status bits updated
Transmitter
Receiver
Status change reflected by
NEWS, IRQ
TransmItter
Receiver
Memory status reflected to
modem pin
Transmitter
Receiver
1. Sample TIme
= 7200 Hz
Only after NEWC is set
ST, RSD-every sample,
all others after NEWC set
Once per sample
Once per baud
Figure 13.
MIN < one sample time
MAX one sample time
MIN one sample tIme
MAX one baud time
33.33
33.33
Note: The modem timing for the auto dialer accounts for interdigit delay for pulses and tones.
~s
~s
2. Baud Time
Auto Dial Sequence Flow Diagram
= 600 Hz
1-57
D
2400 bps Full-Duplex Modem
R2424
SP RAM location as specified by the RAM access code (82-86) in
register 1:F (Table 13). Once the data is written into the RAM
access register 1:F, the XRAM registers 1:2 and 1:3 or the YRAM
registers 1:4 and 1:5, set the NEWC bit 1:E:3 to a 1. ThiS action
causes the information to be transferred from interface memory
into SP RAM. Bit 7 of register 1:F is cleared to a 0 by the modem
after the RAM is read. New data can be written into the SP RAM
after the NEWC bit is reset to a 0 by the SP
SIGNAL PROCESSOR RAM ACCESS
RAM AND DATA ORGANIZATION
Each signal processor contains 128 words of random access
memory (RAM). Each word is 32-bits wide. Because the signal
processor is optimized for performing complex arithmetic, the
RAM words are frequently used for storing complex numbers.
Therefore, each word is organized into a real part (16-bits) and an
imaginary part (16-bits) that can be accessed independently.
The portion of the word that normally holds the real value is
referred to as XRAM. The portion that normally holds the imaginary value is referred to as YRAM. The entire contents of XRAM
and YRAM may be read by the host processor via the microprocessor interface.
Note:
Any transmitter RAM Write operation must always be preceded by a RAM read from the desired location. This is to
guarantee that the correct information is written into the 16
unchanged bits, since all transmitter RAM operations are
32 bit transfers with typically only 16 of the bits used.
Interface Memory Locations
Both the transmitter and receiver (chips 1 and 0, respectively)
allow data to be transferred from SP RAM into the interface memory. A 0 in transmitter bit 1 :F:7 enables the SP to transfer 32 bits
of data from SP RAM to the XRAM and YRAM registers (16 bits
each) in the interface memory as specified by the RAM access
code in register 1:F. A 0 in receiver bit 0:F:7 enables the SP to
transfer 32 bits of data from SP RAM to the XRAM and YRAM
registers (16 bits each) in the interface memory as specified by
the access code in register O:F. To read the SP RAM in chip 1
(transmitter), load into 1:F the RAM access code which identifies
the 32 bits of data to transfer to the XRAM and YRAM registers.
Next, set the NEWC bit 1 :E:3 to a 1. After transferring the data
from RAM to the XRAM or YRAM registers, the NEWC bit is reset
to a 0 by the SP Chip 0 (receiver), on the other hand, will provide
The interface memory acts as an intermediary during these host
to signal processor RAM data exchanges. Information transfer
between RAM and interface memory is accomplished by the signal processor logic unit moving data between the SP main bus
and the SP 1/0 bus. The SP logic unit normally transfers a word
from RAM to interface memory once each clock cycle of the SP
device. In the transmitter, a word is transferred from SP RAM to
the interface memory every sample time. In the receiver, a word is
transferred from RAM to the interface memory every sample time
as well. Each RAM word transferred to the interface memory is
32-bits long. These bits are written by the SP logic unit into interface memory registers 5, 4, 3, and 2. Registers 3 and 2 contain
the most Significant byte and least significant byte, respectively,
of the XRAM data. Registers 5 and 4 contain the most and least
significant bytes of YRAM data, respectively.
+&...'"
.... _..J
V~AI\."
\11..,- "~I 1'""'111'1 g i l ....
I 11r\IVI
V~"'.JI
............ _______ I ....... : _ _
uau;" Vllv
~_II_ ••. : __
.. 1-_ 1 __ -1
o;JQllltJlQ Lillie:;; IVIIV"VIII~ UI'Cl' luau·
ing of the RAM access code into register O:F, and will continue to
provide the same data at one sample time intervals until a new
RAM access code is loaded.
RAM Access Codes
The SP logic unit determines the SP RAM address to read from,
or write to, by the code stored in the RAM Access bits of interface
memory register F (RAM Access R in the receiver O:F and RAM
Access T in the transmitter 1:F).
When reading from or writing into RAM, no bits are provided for
handshaking or interrupt functions. The NEWC bit can be used
as a mechanism to provide sample and baud intervals. Since the
NEWC bit is checked, once per baud in chip 0 and once per
sample in chip 1, the user can set the NEWC bit and wait for it to
be cleared. Depending on which chip the NEWC bit was set, the
time interval from the setting to the clearing of the NEWC bit will
be either one sample or one baud time. This, however, will not
guarantee that the action of reading and writing the XRAM and
YRAM will occur in the middle of an actual sample or baud time.
Only the transmitter (chip 1) allows data to be transferred from
interface memory to SP RAM. When set to a 1, bit 1 :F:7 signals
the SP logic unit to disable transfer of SP RAM data to the interface memory, and instead, to transfer data from interface memory to SP RAM. When writing into SP RAM, 32 bits of data in the
XRAM and YRAM registers will be written into the appropriate
1-58
R2424
2400 bps Full-Duplex Modem
Table 13.
RAM Access Codes
RAM Access Code
Function
RAM Read
RAM Write
Chip
Reg. No.
Demodulator Output
Low Pass Filter Output
Input Signal to Equalizer Taps
AGC Gain Word
Equalizer Tap Coefficients
Equalizer Output
Rotated Equalizer Output
(Received Point Eye Pattern)
Decision Points
(Ideal Eye Pattern)
Rotated Error
Rotation Angle
Phase Error
Self Test Error Counter
56
40
41-40
14
01-00
53
11
-
0
0
0
0
0
0
0
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
2, 3
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
Node
1
2
3
4
5
6
7
8
9
10
11
12
DTMF Tone Duration
DTMF Interdigit Delay
Pulse Interdlgit Delay
Pulse Relay Make Time
Pulse Relay Break Time
Handshake Abort Counter
Handshake Abort Timer
CTS Off-Time
NOTE: 1.
2.
3.
4.
-
51
-
0
2, 3, 4, 5
52
12
10
00
-
0
0
0
0
2, 3,
4,
2,
2,
02
03
03
04
04
05
06
07
82
83
83
84
84
85
86
87
1
1
1
1
1
1
1
1
4,
2,
4,
2,
4,
4,
2,
2,
4, 5
5
3
3
5
3
5
3
5
5
3
3
All the chip 1 access codes are not valid before R5310-18.
Access codes are hexadecimal.
Only chip 1 RAM can be written
CTS Off-Time IS not valid before R5310-22.
Table 15.
BER Summary
Data Rate
Bit Error Rate
Originate Mode
Answer Mode
2400 bps
1 x 10- 5
19.0 dB
17.3 dB
1200 bps
1 x 10- 5
8.3 dB
8.1 dB
ERROR RATES
R2424
Bit error rate (BER) is a measure of the throughput of data on the
communication channel. It is the ratio of the number of received
bits in error to the number of transmitted bits. This number
increases with decreasing signal-to-noise ratio (SNR). The type
of line disturbance and the modem configuration affect the BER.
Table 14.
600 bps
1
X
10- 5
5.0 dB
5.0 dB
300 bps
1
X
10- 5
10.4 dB
7.2 dB
Test Condition: Signal Level = - 43 dBm,
Sync for 2400 bps, 1200 bps, 600 bps,
Async for 300 bps,
With 3002 Unconditioned Line.
Tables 14 through 16 summarize the BERs for various conditions. Figure 14 shows the BER measurement setup.
BER Summary
Signal to Noise Ratio
R2424
Signal to Noise Ratio
Table 16.
BER Summary
Signal to Noise Ratio
R2424
Data Rate
Bit Error Rate
Originate Mode
Answer Mode
Data Rate
Bit Error Rate
Originate Mode
Answer Mode
2400 bps
1 x 10- 5
16.6 dB
16.2 dB
2400 bps
1 x 10- 5
17.0 dB
16.6 dB
1200 bps
1 x 10- 5
8.2 dB
7.9 dB
1200 bps
1 x 10- 5
7.7 dB
7.9 dB
600 bps
1
X
10- 5
5.0 dB
5.0 dB
600 bps
1
X
10- 5
4.6 dB
4.5 dB
300 bps
1
X
10- 5
9.2 dB
7.0 dB
300 bps
1
X
10- 5
9.3 dB
6.2 dB
=
Test Condition: Signal Level = -40 dBm,
Sync for 2400 bps, 1200 bps, 600 bps,
Async for 300 bps,
Back-To-Back.
Test Condition: Signal Level
-30 dBm,
Sync for 2400 bps, 1200 bps, 600 bps,
Async for 300 bps,
With 3002 Unconditioned Line.
1-59
:::D
N
oIloo
N
oIloo
."
cO'
c
iil
....
f>
~
iil
LINE
INIPAIRMENT
SOURCE
~ SIMULATOR
~
~ BIIADLEY
(3002)
2J. AND 2B
SEG FA-1445
6c
.....
ATTENUATOR
HP 350D
LEVEL METER
HP 3552A
"g
<
~
~
~
m
a
:u
~
"tI
CD
MODEM
TEST SET
PHOENIX
5000
MODEM
TRANSMITTER
MODEM
RECEIVER
2- TO 4-WIRE
HYBRID
2- TO 4-WIRE
HYBRID
MODEM
RECEIVER
MODEM
TRANSMITTER
MODEM
TEST SET
PHOENIX
5000
~
3
III
=
n
CD
~
!!l-
m
!a
c
LEVEL METER
HP 3552A
ATTENUATOR
HP 350D
.-
IMI>AIRMENT
SOURCE
BRADLEY
2A AND 2B
f-
LINE
SIMULATOR
(3002)
SEG FA-14~
N
r-
"g
"ijj
tT
'0
til
"T1
C
a:
~0'
=
~
01::00
Q
Q
NOTE: SIGNAL AND NOISE ARE
MEASU~ED
WITH 3 KHZ FLAT WEIGHTING.
'i'"
oC
'0
ii"
><
s::
o
D-
O)
3
R2424
2400 bps Full-Duplex Modem
Table 17.
Modem Power Requirements
Voltage
Tolerance
Current (Typical) @ 25°C
Current (Max) @ DOC
+5 Vdc
+12 Vdc
-12 Vdc
±5%
±5%
±5%
390 mA
25 mA
4mA
<455 mA
< 30 mA
< 5 mA
Note: All voltages must have ripple
s 0.1 volts peak-to-peak.
Table 18.
Modem Environmental Restrictions
Parameter
Specification
Temperature
Operating
Storage
Relative Humidity:
Altitude
OOC to + 60°C (32°F to 140°F)
- 40°C to + 80°C (- 40°F to 176°F) (Stored in heat sealed antistatic bag and shipping container)
Up to 90% noncondensing, or a wet bulb temperature up to 35°C, whichever is less.
-200 feet to + 10,000 feet
Table 19. Modem Mechanical Considerations
Parameter
DIN Connector Version
Board Structure.
Mating Connector:
PCB Dimensions:
DC Version
Width
Length
Height
M Version
Width
Length
Height
Weight (max):
Lead Extrusion (max.):
DIP Connector Version
Board Structure
Dimensions
Width
Length
Height
Weight (max.)
Pin Length (max.)
Specification
Single PC board with a 3·row 54·pin right angle male DIN connector with rows A and C populated.
The modem can also be ordered with the following DIN connector: 64-pin DIN right angle female,
64-pin DIN vertical male or 64-pin DIN vertical female.
Female 3-row 54·pin DIN receptacle with rows A and C populated. Typical mating receptacle:
Winchester 968-6043·0531·1, Burndy R196B32ROOAOOZ1, or equivalent.
3.937 in. (100 mm)
4.725 in. (120 mm)
0.75 in. (19 mm)
3.937 in. (100 mm)
3.328 in. (82 mm)
0.40 in. (10.2 mm)
0.45 Ibs. (0.20 kg.)
0.100 in. (2.54 mm)
Single PC board with a row of 30 pins and a row of 31 pinS
2.0 in. (50.8 mm)
3.5 In. (88.9 mm)
0.2 In. (5.08 mm) above, 0.13 in. (3.30 mm) below
2.6 oz. (73g)
0.53 in. (13.5 mm) above
1-61
In
a dual in-line pin configuration.
R2424
2400 bps Full-Duplex Modem
MALE 64·PIN
DIN CONNECTOR
MALE 64·PIN
DIN CONNECTOR
IT
3.937
COMPONENT
SIDE
0.498
(12.6)
(100)
COMPONENT
I~~~~==~~~S=ID=E====~~
OA98
(12.8)
8",,:,:~ j r~
4.100 (83.2)
0.200 MAX
(104) 4.725
(120)
/ ' COMPONENT AREA
It~..;.~::::--::-:'-...,] r·5O)
f ~l"~:-n I:SD~
0.062
(16)
•
(11.1)
0.082 (5.1)
--(1.8)
0.100 MAX
(11.1)
COMPONENT AREA
(2.54)
DIN CONNECTOR VERSION
0.100 TYP
(2.54)
rr=~8~~:~
3.300
(83.8)
t
-,
2.000
1.850
(50.8)
(47)
1.800
(45.7)
'
,
II
0.098 DIA (4 PL)
(2.5)
,
---.L'
J
0.100
(2.54)
0.100
(2.54)
0.100
(2.54)
0.075
(1.9)
0.535
(13.8)
0.200 MAX
Q~'~~)--_h __ h_I-_h_i
1
L
0.082
(1.6)
--
---"
0.100 MAX
J
UNITS: INCHES
mm
0.130 MAX]
~.3)
DIP CONNECTOR VERSION
Figure 15. R2424 Modem Dimensions and Pin Locations
1-62
R2424
2400 bps Full-Duplex Modem
FCC RULES PART 68 REQUIREMENTS
R2424 MODEM INSTALLATION AND
MAINTENANCE
The FCC Rules Part 68 requires that the telephone interface
leads shall:
This section contains Installation Instructions and maintenance
procedures for the Rockwell R2424DC Modem. It also contains a
special notice from the Canadian Department of Communications (DOC) for Canadian operation and from the Federal Communications Commission (FCC) for United States operation.
1. Be reasonably physically separated and restrained from; not
routed in the same cable as; nor use the same connector as
leads or metallic paths connecting to power connections.
Note
Power connections are defined as the connections
between commercial power and any transformer, power
supply rectitter, converter or other circuitry associated
with the modem. The connections of the interface pins
(including the + 12 Vdc, - 12 Vdc and + 5 Vdc) are not
considered power connections.
GENERAL DESCRIPTION
The Rockwell R2424DC modem is designed to be used with the
United States or Canadian Telephone Switched Networks in
2-wire full-duplex dial-up operation. The modem requires protective circuitry registered with the Federal Communications Commission (FCC) Part 68 which allows direct connection to the U.S.
switched telephone network. This circuitry also complies with
the Canadian Department of Communications (DOC) Terminal
Attachment Program (TAP) which similarly defines their
switched telephone network requirements.
2. Be reasonably physically separated and restrained from; not
routed in the same cable as; nor use adjacent pins on the
same connector as metallic paths that lead to unregistered
equipment, when specification details provided to the FCC do
not show that the interface voltages are less than nonhazardous voltage source limits in Part 68.
The R2424DC features automatic dial and answer capabilities
along with surge suppression and hazardous voltage and longitudinal balance protection. Its maximum output signal level at the
telephone interface is set at - 10 dBm ± 1 dBm (permissive
mode of operation).
Note
All the DIN connector interface voltages to the modem
have been established as non-hazardous.
ROUTING OF TELEPHONE INTERFACE LINES
Two standard telephone jack connectors (RJ 11 s) are mounted
side by side on one edge of the board and are wired in parallel.
One is for connection to the telephone line network and the other
for the telephone headset connection.
In routing the telephone interface leads from the modem telephone connector jacks to the telephone line network connection,
the following precautions should be strongly considered for
safety.
1. The telephone interface routing path should be as direct and
as short as possible.
INSTALLATION AND SIGNAL ROUTING
INSTRUCTIONS
PHYSICAL MOUNTING
2. Any cable used in establishing this path should contain no
signal leads other than the modem telephone interface leads.
The modem module may be physically incorporated into the customer's end product by utilizing the four corner 0.156" diameter
mounting holes (for the self-hooking plastic type standoffs or for
bolting it down to some rigid structure) or by installing the module
into card guides.
3. Any connector used in establishing this path shall contain not
commercial power source signal leads, and adjacent pins to
the TIP and RING (T and R) pins in any such connector shall
not be utilized by any signals other than those shown in this
document.
ELECTRICAL INTERFACING INSTRUCTIONS
The electrical interfacing is accomplished via the DIN (Euro) connector (for external power inputs and digital logic signals) and
the telco connectors (for the telephone network connection).
Note that the telephone interface connectors are physically separated from the modem interface control connector and extreme
care must be taken in routing the telephone interface leads from
the modem to the telephone network (line connector jack in the
wall).
MAINTENANCE PROCEDURE
Under the FCC Rules, no customer is authorized to repair
modems. In the event of a Rockwell modem malfunctioning,
return it for repair to an authorized ROCKWELL INTERNATIONAL distributor (if in Canada) or send it directly to the Semiconductor Products Division, Rockwell International Corporation, EI Paso, Texas 79906.
1-63
D
R2424
2400 bps Full-Duplex Modem
SPECIAL INSTRUCTION TO USERS
Sample label below:
If the Rockwell modem has been registered with the Federal
Communications Commission (FCC), you must observe the following to comply with the FCC regulations:
Unit contains Registered Protective Circuitry which complies with Part 68 of FCC Rules.
FCC Registration Number: AMQ9SQ-14211-DM-E
A. All direct connections to the telephone lines shall be made
through standard plugs and telephone company provided
jacks.
Ringer Equivalence: 0.9B
Note
The Rockwell modem module has the FCC registration
number and ringer equivalence number permanently
affixed to the solder side of the PCB and any unit containing this modem shall use this information for the
label requirements.
B. It is prohibited to connect the modem to pay telephones or
party lines.
C. You are required to notify the local telephone company of the
connection or disconnection of the modem, the FCC registration number, the ringer equivalence number, the particular line
to which the connection is made and the telephone number to
be associated with the jack.
SPECIAL NOTICE FROM THE CANADIAN
DEPARTMENT OF COMMUNICATIONS
Note
If the proper jacks are not available, you must order the
proper type of jacks to be installed by the telephone
company (VSOC RJ11 for permissive mode of operation).
The Canadian Department of Communications label identifies
certified equipment. This certification means that the equipment
meets certain telecommunications network protective, operational and safety requirements. The Department does not guarantee the equipment will operate to the user's satisfaction.
D. You should disconnect the modem from the telephone line if it
appears to be malfunctioning. Reconnect it only if it can be
determined that the telephone line and not the modem is the
source of trouble. If the Rockwell modem needs repair, return
it to the ROCKWELL INTERNATIONAL CORPORATION. This
applies to the modem whether it is in or out of warranty. Do not
attempt to repair the unit as this is a violation of the FCC rules
and may cause danger to persons or to the telephone net-
Before installing this equipment, users should insure that it is
permissible to be connected to the facilities of the local telecommunications company. The eqUipment must also be installed
using an approved method of connection. In some cases, the
company's inside wiring aSSOCiated with a single line individual
service may be extended by means of a certified jack-plug-cord
ensemble (telephone extension cord). The customer should be
aware that the compliance with the above conditions may not
prevent degradation of service in some situations. Existing telecommunications company requirements do not permit their
equipment to be connected to customer-provided jacks except
where specified by individual telecommunications company tariffs.
TELEPHONE COMPANY RIGHTS
AND RESPONSIBILITIES
. A. The Rockwell modem contains protective circuitry to prevent
harmful voltages to be transmitted to the telephone network. If
such harmful voltages do occur, then the telephone company
may temporarily discontinue service to you. In this case, the
telephone company should:
The Department of Communications requires the Certificate
Holders to identify the method of network connection in the user
literature provided with the certified terminal equipment.
1. Promptly notify you of the discontinuance.
2. Afford you the opportunity to correct the situation which
caused the discontinuance.
Repairs to certified equipment should be made by an authorized
Canadian maintenance facility designated by the supplier. Any
repairs or alterations made by the user to this equipment, or
equipment malfunctions may give the telecommunications company cause to request the user to disconnect the equipment.
3. Inform you of your right to bring a complaint to the FCC
concerning the discontinuance.
B. The telephone company may make changes in its facilities
and services which may affect the operation of your equipment. It is, however, the telephone company's responsibility to
give you adequate notice in writing to allow you to maintain
uninterrupted service.
Users should ensure for their own protection that the electrical
ground connections of the power utility, telephone lines and internal metallic water pipe system, if present, are connected
together. This precaution may be particularly important in rural
areas.
LABELING REQUIREMENTS
CAUTION
A. The FCC requires that the following label be prominently displayed on the outside surface of the customer's end product
and that the size of the label should be such that all the
required information is legible without magnification.
Users should not attempt to make such connections themselves, but should contact the appropriate electric inspection authority, or electrician, as appropriate.
1-64
R201/26DP
Integral Modems
'1'
Rockwell
R201/26DP
2400/1200 bps Data Pump Modem
INTRODUCTION
FEATURES
The Rockwell R201/26DP is a synchronous, 240011200 bits per
second (bps) modem. It is designed for half duplex operation
over the public switched telephone network or (PSTN) full duplex
operation over unconditioned leased lines.
• Configurations:
- CCITI V.26, V.26 bis
-Be1l201B/C
• Full-duplex (4-wire) over Leased Lines
• Half-duplex (2-wire) over PSTN
• Ideal for point-to-point applications
• Synchronous Operation:
- 2400 bps (with fall-back) ± .01 %
-1200 bps ±.01%
• Dual Tone Multi-Frequency (DTMF) Generation
• Programmable Tone Generation
• Call Progress Tone Detection
• Programmable Output Level: -1 dBm to -15 dBm
• Equalization
- Automatic Adaptive
- Compromise Cable and Link (Selectable)
• DTE Interface:
- Microprocessor Bus
- CCITI V.24 (RS-232-C Compatible)
• Local and Remote Test Configurations
• Selectable Scrambler/Dascrambler (V.27 bis)
• Dynamic Range: 0 dBm to - 43 dBm
• Diagnostic Capability
- Provides Telephone Line Quality Monitoring Statistics
• Small Size: 100 mmx120 mm (3.94 in. x 4.73 in.)
• Low Power Consumption: 3W (Typical)
• TIL and CMOS Compatible
The modem satisfies the telecommunications requirements
specified in CCITI Recommendation V.26 bis Alternate A or B,
and Bell Specification 201 B/C.
The R201l26DP is optimized for pOint-to-point applications and
is suitable for network applications where the optimum in data
transfer is needed. Its small size and low power consumption
offer the user flexibility in creating a 2400/1200 bps modem customized for specific packaging and functional requirements.
Data can be transferred between the host computer either
serially over the CCITI V.24 (RS-232-C) interface or in parallel
over an B-bit microprocessor bus.
The R201/26DP is a member of Rockwell's family of plug
compatible integral modems.
R201/26DP Modem
Document No. 29200N23
Data Sheet
1-65
Order No. MD23
Rev. 1, January 1987
2400/1200 bps Data Pump Modem
R201/26DP
TECHNICAL SPECIFICATIONS
DATA ENCODING
TRANSMITTER CARRIER AND SIGNALING
FREQUENCIES
At either 2400 bps or 1200 bps the R201/26DP operates at
1200 baud.
The transmitter carrier and signaling frequencies of the
R201l26DP are listed in Table 1.
At 2400 bps the data stream is encoded into dibits. Two different
methods of coding are used in accordance with CCITI Recommendation V.26 AlB. The V.26B method is compatible with
Bell 201 B/C modems.
Table 1.
Transmitter Carrier and Signaling
Frequency Specifications
At 1200 bps the data stream is encoded into single bits in
accordance with CCITI Recommendation V.26 bis.
Frequency
(Hz ±O.O1%)
Function
Carrier frequency
CCITT Echo Suppression
and Answering Tone Frequencies
BELL Echo Suppression
and Answering Tone Frequencies
1800
2100
EQUALIZERS
2025
The modem provides equalization functiuons that improve performance when operating over low quality lines.
Cable Equalizers - Selectable compromise cable equalizers in
the receiver and transmitter are provided to optimize performance
over different lengths of non-loaded cable of 0.4 mm diameter.
DTMF GENERATION
The R201/26DP is capable of generating Dual Tone Multifrequency (DTMF) signals. The duration ofthe DTMF signal is 95 ms
and the interdigit delay is 70 ms. The amplitude of the lower
frequency is - 5.S dBM and ofthe higher frequency is - 3.S dBM.
Link Equalizers - Selectable compromise link equalizers in the
receiver optimize performance over channels exhibiting severe
amplitude and delay distortion. Two standards are provided: U.S.
survey long and Japanese 3-link.
Table 2 lists the Dial Digit Register (DDR) codes necessary for
DTMF dialing and the corresponding tone pairs.
Table 2.
Automatic Adaptive Equalizer - An automatic adaptive
equalizer is provided in the receiver circuit. The equalizer can be
configured as either a T or a Tl2 equalizer.
Dial Digits/Tone Pairs
Dial Digit Register (OOR)
Hexadecimal Code
Dial Digit
00
01
02
03
04
05
06
07
08
09
OA
OB
0
1
2
3
4
5
6
7
8
9
*
#
Tone Pair
(Hz)
941
697
697
697
770
770
770
852
852
852
941
941
TRANSMITTED DATA SPECTRUM
'1336
1209
1336
1477
1209
The transmitted spectrum occupies the bandwidth between
SOO Hz and 2S00 Hz and is shaped by a square root of 90% raised
cosine filter.
1!l!lfl
SCRAMBLERIDESCRAMBLER
1477
1209
1336
1477
1209
1477
The R201/26DP incorporates a self-synchronizing scramblerl
descrambler. This facility is in accordance with CCITI Recommendation V.27 bis and V.27 ter. The scrambler/descrambler is
optionally enabled by interface memory bits.
TONE GENERATION
RECEIVED SIGNAL FREQUENCY TOLERANCE
Under control of the host processor, the R201/26DP can generate voice band tones up to 4800 Hz with a resolution of 0.15 Hz
and an accuracy of 0.01 0lb. Tones over 3000 Hz are attenuated.
The receiver circuit of the R201l26DP can adapt to received
frequency errors of up to ± 10 Hz with less than 0.5 dB degradation in BER performance.
TONE DETECTION
RECEIVE LEVEL
The R201/26DP features a Tone Detector receiver configuration.
The tone detector responds to energy in the 345 ± 10Hz to 650
± 10 Hz frequency range. The presence of atone is indicated by
the zero state of a status bit. The tone detector response time is
10 ±5 ms.
The. receiver circuit of the modem satisfies all specified performance requirements for received line signal levels from 0 dBm to
-43 dBm. The received line Signal level is measured at the
receiver analog input (RXA).
RECEIVE TIMING
SIGNALING AND DATA RATES
The R4SDP/20S provides a data derived Receive Data Clock
(RDClK) output in the form of a squarewave. The low to high
transitions of this output coincide with the centers of received data
bits. The timing recovery circuit is capable of tracking a ± 0.01 %
frequency error in the associated transmittiming source. RDCLK
duty cycle is 50% ± l olb.
The data signaling and modulation rates for normal and fallback
operation are listed in Table 3.
Table 3.
Slgnallng/Data Rates
Parameter
Specification
(±O.O1%)
Signaling Rate: Normal Operation
Data Rate;
1200" Baud
2400 bps
TRANSMIT LEVEL
Signaling Rate; Fallback Operation
Data Rate:
1200 Baud
1200 bps
The transmitter output level is accurate to ± 1.0 dB and is
programmable from -1.0 dBm to -15.0 dBm in 2 dB steps.
1-66
2400/1200 bps Data Pump Modem
R201/26DP
TRANSMIT TIMING
RECEIVED LINE SIGNAL DETECTOR (RLSD)
The R201/26DP provides a Transmit Data Clock (TDCLK) output with the following characteristics:
1. Frequency. Selected data rate of 2400 or 1200 Hz (±0.01%).
2. Duty Cycle. 50% ± 1%
The off-to-on (on-ta-off) response time of the RLSD signal and the
CDET bit is defined as the time period between the sudden connection (removal) of the received line signal to (from) the
modem's receiver, and the subsequent on (off) transition of carrier detect. Table 5 shows the carrier detect response times.
Input data presented on TXD is sampled by the R201/26DP at
the low to high transition of TDCLK. Data on TXD must be stable
for at least one microsecond prior to the rising edge of TDCLK
and remain stable for at least one microsecond after the rising
edge of TDCLK.
Table 5. Carrier Detect Response Times
Carrier Detect Transition
Off-to-on
On-to-off
EXTERNAL TRANSMIT CLOCK
The R201/26DP is capable of tracking an external transmit clock
signal on input XTCLK. This input signal must equal the desired
data rate ±0.01% with a duty cycle of 50% ±20%.
Response Time (ms)
14±1
8±3
The RLSD on-ta-off response time ensures that all valid data
bits have appeared on RXD.
TRAIN ON DATA
Four threshold options are provided for carrier detect and are
selected by writing to the Receiver Threshold (RTH) bits in the
interface memory. Table 6 shows the relationship betweeen the
setting of the RTH bits and the carrier detect thresholds.
When train on data is enabled, the receiver trains on data in
less than 3.5 seconds.
TURN-ON SEQUENCE
A total of 13 selectable turn-on sequences can be generated
by the R201/26DP. These are listed in Table 4. The Turn-on
Sequence data are written to the Turn On Sequence select field
in chip O.
Table 6
Table 4. Turn-On Sequences
Turn On
Sequence
Number
Compatibility
CTS Response
Time (ms)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
V.26 bls
V.26 bis
V.26 bis
V.26 bls
V.26 bis
V.26, V.26 bls
V.26, V.26 bis
Bell 201C
Bell201C
V.26 bls
V.26 bls
V.26 bis
V.26 bis
0
6.67
8.33
30.0
30.0
90.0
90.0
148.3
148.3
220.0
220.0
800.0
800.0
Carrier Detect Levels
RTH
RLSD On
00
01
10
11
>-43 dBm
>-33 dBm
>-26 dBm
>-16dBm
RLSD Off
<-48
<-30
<-31
<-21
dbm
dbm
dbm
dbm
Comments
NOTE
Performance may be at a reduced level when the received
signal is less than - 43 dBm.
Scrambler inserted
A minimum hysteresis action of 2 dB exists between the actual
off-to-on and on-to-off transition levels. The threshOld levels and
hysteresis action are measured with an unmodulated 2100 Hz
tone applied to the receiver's audio input (RXA).
Scrambler inserted
Scrambler inserted
Scrambler Inserted
MODES OF OPERATION
Scrambler inserted
The R201/26DP is capable of being operated in either a serial
or a parallel mode of operation.
·NOTE: The scrambler bits, DDIS and SOlS must also be set to Insert
or disable the scrambler.
TURN-OFF SEQUENCE
SERIAL MODE
The R201l26DP turn-off sequence consists of a maximum of
6 ms of remaining data and scrambled ones at 1200 baud.
The serial mode uses standard V.24 (R5-232-C compatible)
signals to transfer channel data. An optional USRT device shown
in the Functional Interconnect Diagram (Figure 1) illustrates this
capability.
CLAMPING
The Received Data (RXD) signal is clamped to a constant mark
(one) whenever the Received Line Signal Detector (RLSD) is off.
PARALLEL MODE
RESPONSE TIMES OF CLEAR-TO-SEND (C'fS)
The R201/26DP has the capability of transferring channel data
up to eight bits at a time via the microprocessor bus.
The time between the off-to-on transition of Request-To-Send
(RTS) and the off-ta-on transition of CTS is determined by the
modem configuration and its associated turn-on sequence.
MODE SELECTION
These times are listed in Table 4. If training is not enabled
RTS/CTS delay is less than 2 baud times.
Selection of either the serial or parallel mode of operation is by
means of a control bit. To enable the parallel mode, the control
bit must be set to a 1. The modem automatically defaults to the
serial mode at power-on. In either mode the R201/26DP is configured by the host processor via the microprocessor b\ls.
The time between the on-ta-off transition of RTS and the on-tooff transition of CTS in the data state is a maximum of 2 baud
times for all configurations.
1-67
R201/26DP
240011200 bps Data Pump Modem
r-----'
I
I
I
I
USRT
I (OPTIONAL)
I
I
I
I
.J
L---
r
HOST
PROCESSOR
(DTE)
l
RTS
CTS
TXD
TDCLK
XTCLK
RLSD
RXD
RDCLK
TBCLK
RBCLK
qCOPE
EVEX
EVEV
EVSVNC
EVECLK
EVE
PATTERN
GENERATOR
+12V
+5V
GND
-12V
R201/26DP
MODEM
READ
WRITE
DATA BUS (8)
Di
ADDRESS BUS (4i:
RSi
CS(3)
CSi
DECODER
POR
RXA
t
IRQ
.AVAA
POWER
SUPPLY
TXA
LINE
INTERFACE
:}
TELEPHONE
LINE
AUXIN
I
+5V
I
xt tv
-
J
Figure 1. R201/26DP Functional Interconnect Diagram
Table 7.
FULL/HALF DUPLEX MODES
...-...-
The ~2C1 t23DP j"iiceivef c.an Utt (,;uniigurec.i iar eiiher iuii dupiex
operation over four-wire leased lines or for half duplex operation
over the switched telephone network. Full duplex or half duplex
operation is selected by writing the appropriate configuration
code into the receiver configuration register. When configured
for half duplex operation, the receiver is squelched and
unsquelched by setting and resetting of a control bit. When the
receiver is squelched, RLSD is turned off and RXD is clamped
to the marking state. When the receiver is unsquelched, it
searches for a 20 ms period of silence before entering the
training state. This prevents line echoes from interfering with
the proper reception of training sequence.
R201/26DP Hardware Circuits
IT.,;::: i
.... ,._.
I
i
.,;=:".~.;vii
A. OVERHEAD:
Analog Ground Return
31C,32C
Ground (A) AGND
Digital Ground Return
3C,8C,5A,10A
Ground (D) DGND
PWR 19C,23C,26C,30C + 5 volt supply
+5 vo~s
+ 12 volt supply
15A
PWR
+12 volts
- 12 volt supply
12A
PWR
-12 volts
Power-on-reset
13C
IIOB
POR
B. MICROPROCESSOR INTERFACE:
IIOA
IIOA
IIOA
IIOA
IIOA
IIOA
IIOA
IIOA
lC
lA
2C
2A
3A
RS3
RS2
RSl
RSO
IA
IA
IA
IA
6C
6A
7C
7A
CSO
IA
10C
CSl
IA
9C
CS2
IA
9A
READ
WRITE
IRQ
IA
IA
OB
12C
llA
llC
D7
D6
05
04
D3
D2
01
DO
INTERFACE CRITERIA
The modem interface comprises both hardware and software
circuits. Hardware circuits are assigned to specific pins in a
64-pin DIN connector. Software circuits are assigned to specific
bits in a 48-byte interface memory.
HARDWARE CIRCUITS
Signal names and descriptions of the hardware circuits, including
the microprocessor interface, are listed in Table 7. In the table,
the column titled 'Type' refers to designations found in the Hardware Circuit Characteristics. Figure 2 shows the Microprocessor
Interface Timing Diagram. The microprocessor interface is
designed to be directly compatible with an 8080 microprocessor.
With the addition of a few external logic gates, it can be made
compatible with 6500, 6800, or 68000 microprocessors. Table 8
lists the timing parameters of the microprocessor interface.
1-68
4C
4A
5C
}
Data Bus (8 BIts)
}
Register Select
(4 Bits)
Chip Select
Transmitter Device
Chip Select ReceIver
Sample Rate Device
Chip Select Receiver
Baud Rate Device
Read Enable
Write Enable
Interrupt Request
240011200 bps Data Pump Modem
R201/26DP
Table 7.
Name
MICROPROCESSOR TIMING
R201/26DP Hardware Circuits (Cont.)
Type
Pin No.
Description
C. V.24 INTERFACE:
RDCLK
TDCLK
XTCLK
RTS
CTS
TXD
RXD
RLSD
OC
OC
IB
IB
OC
IB
OC
OC
READ
21A
23A
22A
25A
25C
24C
22C
24A
Receive Data Clock
Transmit Data Clock
External Transmit Clock
Request-to-Send
Clear-to-Send
Transmitter Data
Receiver Data
Received Line Signal Detector
CSI
OC
OC
26A
27C
Receiver Baud Clock
Transmitter Baud Clock
31A
32A
30A
Transmitter Analog Output
Receiver Analog Input
Auxiliary Analog Input
15C
14A
14C
13A
Eye
Eye
Eye
Eye
Ii
= 0-2)
Ii
= 0-3)
RSi
D. ANCILLARY CIRCUITS:
RBCLK
TBCLK
WRITE
E. ANALOG SIGNALS:
TXA
RXA
AUXIN
AA
AB
AC
TWR
F. DIAGNOSTIC:
EYEX
EYEY
EYECLK
EYESYNC
OC
OC
OA
OA
READ
Pattern
Pattern
Pattern
Pattern
Data-X AXIs
Data-Y Axis
Clock
Synchronizing Signal
TWOS
(i
=
Di
0-7) --~"
Figure 2.
Microprocessor Interface Timing Diagram
Table 8.
EVE PATTERN GENERATION
Critical Timing Requirements
Characteristic
The four hardware diagnostic circuits, identified in Table 7, allow
the user to generate and display an eye pat1ern. Circuits EYEX
and EYEY serially present eye pattern data for the horizontal
and vertical display inputs respectively. The 8-bit data words are
shifted out most significant bit first, clocked by the rising edge
of the EYECLK output. The EYESYNC output is provided for
word synchronization. The falling edge of EYESYNC may be
used to transfer the 8-bit word from the shift register to a holding
register. Digital to analog conversion can then be performed for
driving the X and Y inputs of an oscilloscope.
Min
Max
Units
-
nsec
140
nsec
TCS
30
Data access time after Read
TDA
-
Data hold time after Read
TDH
10
50
nsec
nsec
nsec
CSi, RSi hold time after
Read or Write
TCH
10
Write data setup time
TWDS
75
Write data hold time
TWDH
TWR
10
-
75
,-
Write strobe pulse width
1-69
Symbol
CSi, RSi setup time prior
to Read or Write
nsec
nsec
2400/1200 bps Data Pump Modem
R201/26DP
HARDWARE CIRCUiT CHARACTERISTICS
Digital Interface Characteristics
Table 9 lists the parameters associated with the digital interface
provided by the R201/26DP.
Table 9.
Digital Interface Characteristics
Input/Output Type
Symbol
Parameter
Units
IA
IB
IC
OA
V,H
Input Voltage, High
V
2.0 Min.
2.0 Min.
2.0 Min.
V'L
VOH
Input Voltage, Low
V
0.8 Max.
0.8 Max.
0.8 Max.
Output Voltage, High
V
VOL
Output Voltage, Low
liN
Input Current, Leakage
0.4 Max. 2
Output Current, High
mA
-0.1 Max.
Output Current, Low
mA
1.6 Max.
IL
Output Current, Leakage
~
Ipu
Pull-up Current
(Short Circuit)
~
CL
Capacitive Load
pF
CD
Capacitive Dnve
pF
-240 Max.
-10 Min.
-240 Max.
-10 Min.
5
20
5
-100~
1.6 mA
TTL
w/Pull-up
TTL
w/Pull-up
Notes
3. I Load = -40~
4. V,N = 04 to 2 4 Vdc, Vcc
Anaiog interiace Characteristics
0.8 Max.
2.4 Mln.3
0.4 Max. 2
0.4 Max.5
1.6 Max.
1.6 Max.
AA
The transmitter output IS 604 ohms ± 1%.
RXA
AB
The receiver input Impedance is 60K ohms
±23%.
AUXIN
AC
The auxiliary analog Input allows access to the
transmitter for the purpose of interfacing with
user provided equipment. Because this is a
sampled data input, any signal above 4800 Hz
will cause aliaSing errors. The input impedance
IS 1K ohms, and the gain to transmitter output is
the TLVL setting + 0.6 dB - 1.4 dB. If unused,
this input must be grounded near the modem
connector. If used, it must be driven from a low
Impedance source.
100
40
100
Open-Drain Open-Drain
3-State
Open-Drain
w/Pull-up Transceiver w/Pull-up
5. I Load
=
10
100
=
0 36 mA
5.25 Vdc
Status Control Bits
Characteristics
TXA
TTL
100
-260 Max.
-100 Min.
When information in these registers is being discussed, the
format Y:Z:O is used. The chip is specified by Y(O - 2), the
register by Z(O - F), and the bit by 0(0 - 7, 0 = LSB).
Table 10. Analog Interface Characteristics
Type
0.8 Max.
2.4 Min.'
-240 Max.
-10 Min.
100
Table 10 lists the parameters associated with the analog interface provided by the R201/26 DP.
Name
I/O B
5.25 Max
20 Min.
±10 Max.
TTL
=
=
0.4 Max. 2
I/O A
2.0 Min.
±2.5 Max.-
IOH
1. I Load
2. I Load
0.4 Max. 2
±2.5 Max.
IOL
Circuit Type
OC
2.4 Min.'
V
~
OB
The operation of the R201/26DP is affected by a number of software control inputs. These inputs are written into registers within
the interface memory via the host microprocessor bus. Modem
operation is monitored by various software flags that are read
from interface memory via the host microprocessor bus. All status
and control bits are defined in the Interface Memory tables
(tables 12-14). Bits designated by a dash (-) are reserved for
modem use only and must not be changed by the host. Table
15 describes the function of each bit in the interface memory.
RAM Data Access
SOFTWARE CIRCUITS
The R201/26DP provides the user with access to much of the
data stored in the modem's memories. This data is useful for
performing certain diagnostic functions.
The R201/26DP comprises three signal processor chips. Each
of these chips contains 16 registers to which an external (host)
microprocessor has access. Although these registers are within
the modem, they may be addressed as part of the host
processor's memory space. The host may read data out of or
write data into these registers. The registers are referred to as
interface memory. Registers in chip 1 update at half the modem
sample rate (2400 bps). Registers in chip 0 and 2 update at the
baud rate (1200 bps).
Two RAM access registers in chip 1 allow user access to RAM
locations via the X word registers (1:3 and 1:2) and the Y word
registers (1:1 and 1:0). Comparable registers in chip 2 provide
access to chip 2 RAM locations. The access code stored in RAM
ACCESS XS (1 :5) selects the source of data for RAM DATA XSM
and RAM DATA XSL (1:3 and 1:2). Similarly, the access code
stored in RAM ACCESS YS (1 :4) selects the source of data for
RAM DATA YSM and RAM DATA YSL (1: 1 and 1 :0). Chip 2
registers are associated in the same way.
1-70
2400/1200 bps Data Pump Modem
R201/26DP
Reading of RAM data is performed by storing the necessary
access codes in 1:5 and 1:4 (or 2:5 and 2:4), reading 1:0 (or 2:0)
to reset the associated data available bit (1:E:0 or 2:E:0), then
waiting for the data available bit to return to a one. Data is now
valid and may be read from 1:3 through 1:0 (or 2:3 through 2:0).
The contents of registers 2:3 and 2:1 are also available serially
on outputs EYEX and EYEY, respectively, unless the IFIX bit
(1:6:7) is set to a one. When IFIX is a one, EYEX and EYEY
remain fixed on the rotated equalizer output.
AUTO DIAL SEQUENCE
The flowchart shown in Figure 3 defines the auto dial sequence
via the microprocessor interface memory.
o -RTS (0:7:7)
WRITE DTMF CONFIGURATION
CODE: $04 - 0:6
1 - TSB (O:E:3)
FIRST DIGIT - DDR (0:0)
1 -RTS (0:7:7)
TBA (O:E:O) = 1
y
NEXT DIGIT - DDR (0:0)
N
LAST DIGIT
y
$FF - DDR (0:0)
TBA (O:E:O)
=1
y
o-
RTS (0:7:7)
,
END
Figure 3.
)
Auto Dialing Sequence Flowchart
1-71
o
R201/26DP
240011200 bps Data Pump Modem
RAM Access Codes
Table 13.
The RAM access codes defined in Table 11 allow the host processor to read diagnostic information within the modem.
I~
Receiver Interface Memory Chip 1 (CS1)
7
6
4
5
2
3
1
0
Register"
Table 11.
4tNo ·
./
1
2
3
4
5
RAM Access Codes
Function
Chip X Access Y Acoess Register
Received Signal Samples
Demodulator Output
low Pass Filter Output
Average Energy
AGC Gain Word
6 Equalizer Input
7 Equalizer Tap Coefficients
8 Unrotated Equalizer
Output
9 Rotated Equalizer Output
(Received POints)
10 Decision Points
(Ideal Data POints)
11 Error
12 Rotation Angle
13 Frequency Correction
14 EOM
15 Dual Point
1
1
1
1
1
CO
C2
04
DC
81
2
2
CO
81-90
2
2
2
6
5
-
-
-
-
-
-
El
A2
61
22
0,1,2,3
0,1,2,3
7
E2
62
0,1,2,3
5
RAM ACCESS XS
4
RAM ACCESS YS
3
RAM DATA XSM
B
-
A
TODF
-
9
-
FED
E3
63
0.1.2.3
Not Used
00
0.1
AA
Not Used
2.3
A7
Not Used
2,3
AE
2E
0.1.2,3
3
2
1
-
RTH
IFIX
-
-
DDIS
TOD
RV26
-
-
TONE
-
-
RPDM WSRD WBRD
-
RAM DATA XSL
1
RAM DATA YSM
0
RAM DATA YSURECEIVER DATA
7
6
5
4
-
0
-
-
C
-
-
B
-
A
9
-
8
-
Table 14.
~
0
-
-
-
-
-
TSB
-
-
-
TIE
-
-
T2
2
3
1
CDEr
-
RTDIS
RBPS
0
7
Receiver Interface Memory Chip 2 (CS2)
6
5
4
-
F
-
-
-
TBA
E
RBIA
-
-
-
-
-
-
-
-
-
-
-
0
-
-
-
C
-
9
-
S
-
-
-
-
-
-
7
RTS TIDIS SOlS MHlD DWTR TPDM XCEN DTMF
6
TONE
-
2
1
-
-
-
-
-
RBIE
-
RBDA
-
-
-
3
-
CEO
LAEN lDEN
A3l
D3l
-
LCEN
-
-
7
TV26 TBPS TURN·ON SEQUENCE SELECT
-
B
A
6
-
-
-
-
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
2
1
0
5
RAM ACCESS XB
4
RAM ACCESS YB
3
RAM DATA XBM
2
FREOl
2
RAM DATA XBl
1
RAM DATAXTM
1
RAM DATA YBM
0
RAM DATA XTlffRANSMITTER DATA/DDR
0
RAM DATA YBl
7
6
5
TlVl
4
3
2
1
.~
0
Sit
Bit
1-72
7
6
5
-
-
FREOM
L3ACT l4ACT l4HG
-
-
3
I~
-
Bit
RAM ACCESS XT
TIA
4
RSDA
TDET HD2W RLRT
2
~
-
-
Register
F
5
-
0,1,2,3
0,1,2,3
Register
E
-
-
6
4
-
-
0
40
01-10
Transmitter Interface Memory Chip 0 (CSO)
7
RSIE
-
C
NOTE
."::::;
-
RSB
RSIA
Not Used
2,3
0,1,2,3
42
0,1,2,3
54
Not Used
2,3
Not Used
2,3
In the interface memory tables that follow. those columns
marked by a dash (-) indicate reserved and are for
modem use only.
Table 12.
-
-
RTSD SOH SOHT
8
2
2
2
2
2
-
-
F
E
4
3
-
R201/26DP
240011200 bps Data Pump Modem
Table 15. R201/26DP Interface Memory Definitions
Mnemonic
Name
Memory
location
Description
A3L
Amplitude 3-Link
Select
0:5:1
A3L is used in conjunction with LAEN. When A3L is a one the Japanese 3 link equalizer
is selected and when A3L IS a zero the U.S. Survey Long link equalizer IS selected
COET
Carner Detector
1:B:0
When zero, status bit CDET Indicates that passband energy is being detected, and
that a training sequence is not in process. CDET goes to a zero at the start of the
data state, and returns to a one at the end of the received signal. CDET activates up to
1 baud time betore RLSD and deactivates Within 2 baud times aiter RLSD.
CEO
Cable Equalizer
Field
0:5:4,5
The CEO Control field simultaneously controls amplitude compromise equalizers in both
the transmit and receive paths. The follOWing tables list the possible cable equalizer
selection codes and responses.
CEQ
Cable Length (0.4 mm diameter)
0
1
2
3
0.0
1.8 km
3.6 km
7.2 km
Cable Equalizer Nominal Gain
."
CEQ CODE 1
--"'"
Frequency
(Hz)
.""
c:""
"'
I,'
.
700
1500
2000
3000
Gain Relative to 1700 Hz (dB)
Tranamltter
Receiver
-0.99
-0.20
+0.15
+1.43
-0.94
-0.24
+0.31
+1.49
CEQ CODE 2
Gain Relative to 1700 Hz (dB)
Frequency
(Hz)
Tranamltter
Receiver
700
1500
2000
3000
-2.39
-0.65
+0.87
+3.06
-2.67
-0.74
+1.02
+3.17
CEQ CODE 3
"
.
Gain Relative 10 1700 Hz (dB)
Frequency
(Hz)
Transmitter
Receiver
700
1500
2000
3000
-3.93
-1.22
+1.90
+4.58
-3.98
-1.20
+1.81
+4.38
Unless a problem with training or high bit error rate is encountered, most applications
operate successfully with no cable equalizer selected.
DDIS
Oescrambler Disable
1:7:5
When control bit DDIS is a one, and at device reset the receiver descrambler circuit is
removed from the data path.
DTMF
Dual Tone Multifrequency Select
0:7:0
When this bit is set to a one, the DTMF mode is selected. To initiate DTMF tone
generation, the TSB bit must be set to a one for each tone pair desired. Although the
R201/260P will perform a 95 ms timeout on the tone pair, it does not notify the host
that the tone is completed. Thus the host must perform its own 95 ms timeout to know
when to start the next tone pair. DTMF is reset to zero by device reset.
1-73
D
2400/1200 bps Data Pump Modem
R201/26DP
Table 15. R201/26DP Interface Memory Definitions (Continued)
Mnemonic
DWTR
Name
DiagnostIcs Write
to RAM
Memory
location
0: 7: 3
Deacriptlon
To write data into the internal memory of the Transmitter Interface Memory Chip 0, the
DWTR bit is used. Note that setting DWTR to a one takes the modem out of data mode
(important because RAM DATA XTL and TRANSMITTER DATA share the same
address). DWTR is reset to zero by device reset.
The proper operational sequence for DWTR is given below:
1. Set'OWTR bit to one.
2. Load RAM ACCESS CODE (see Table 11) into RAM ACCESS XT Register.
3. Load new data into RAM DATA XTM and RAM DATA XTL Registers.
4. Set TBA bit to zero to actually write data.
5. Wait for TBA bit to return to a one to insure that the new data is loaded correctly.
6. Repeat steps 2, 3, 4, and 5 until finished loading data.
7. Set DWTR bit to a zero.
D3L
(None)
Delay 3-Llnk Select
0:5:0
D3L is used in conjunction with LDEN. When D3L is a one the Japanese 3 link
equalizer is selected and when D3L is a zero the U.S. Survey Long link equalizer is
selected.
Fast Energy
Detector
1:9:6
When status bit FED is a zero, it indicates that energy above the receiver threshold is
present in the passband.
FREQUFREQM
0:2:0-7,
0:3:0-7
The host processor conveys tone generation data to the transmitter by writing a 111-bit
data word to the FREQL and FREQM registers in the interface memory space, as
shown below:
FREQM Register (0:3)
I
B~I
IData Word: I
7
I
6
I
5
I
4
I
3
I
2
I
215
I
214
I
213
I
212
I
211
I
210
I
1
211
I
I
0
211
FREQL Register (0: 2)
6
5
3
4
The frequency number (N) determines the frequency (F)
F - (0.146466) (N) Hz ±0.01%
o
2
as follows:
Hexadecimal frequency numbers (FREQL, FREQM) for commonly generated tones are
given below:
Frequency (Hz)
FREQM
FREQl
462
1100
1650
1850
2100
OC
52
65
00
55
00
10
2C
31
38
HD2W
Half Duplex
(Two Wire)
1:6:2
When control bit HD2W is a zero and at device reset, full duplex (4-wire) operation is
enabled. When it is a one, half duplex (2-wire) operation is enabled.
IFIX
Eye Fix
1:6:7
When control bit IFIX is a one, the serial data on EVEX and EVEV reflect the rotated
equalizer output and do not follow the data selected by RAM ACCESS XB and RAM
ACCESS VB. IFIX is reset to 0 by device reset.
1·74
I
I
R201/26DP
2400/1200 bps Data Pump Modem
Table 15.
Mnemonic
LAEN
Name
Link Amplitude
Equalizer Enable
R201/26DP Interface Memory Definitions (Continued)
Memory
Location
0:5:3
Description
The link amplitude equalizer enable and select bits control an amplitude compromise
equalizer In the receive path according to the following table:
LAEN
A3L
Curve Matched
o
X
1
1
1
No Equalizer
U.S. Survey Long
Japanese 3-Link
o
The link amplitude equalizer responses are given in the following table.
Link Amplitude Equalizer
Gain Relative to 1700 Hz (dB)
Frequency
(Hz)
U.S. Survey Long
Japanese 3-Link
1000
1400
2000
2400
2800
3000
-0.27
-0.16
-0.33
-1.54
-5.98
-8.65
-0.13
-0.08
+0.16
+0.73
-2.61
+3.43
LCEN
Loop Clock Enable
0:4:0
When control bit LCEN is a one, the transmitter clock tracks the receiver clock. LCEN is
reset to 0 by device reset.
LDEN
Link Delay
Equalizer Enable
0:5:2
The link delay equalizer enable and select bits control a delay compromise equalizer in
the receive path according to the following table:
LDEN
o
D3L
X
1
1
1
Curve Matched
No Equalizer
U.S. Survey Long
Japanese 3-Link
o
The link delay equalizer responses are given in the following table.
Link Delay Equalizer
Delay Relative to
1700 Hz (Microseconds)
Frequency
(Hz)
U.S. Survey Long
Japanese 3-Link
800
1200
1600
1700
2000
2400
2800
-498.1
-188.3
-15.1
+0.0
-39.8
-423.1
-672.4
-653.1
-398.5
-30.0
+0.0
+ 11.7
-117.1
-546.3
L3ACT
Local Analog
Loopback Activate
0:4:7
When control bit L3ACT is a one, the transmitter analog output is coupled to the
receiver analog input through an attenuator in accordance with CCITI recommendation
V.54 loop 3. L3ACT is reset to 0 by device reset.
L4ACT
Remote Analog
Loopback Activate
0:4:6
When control bit L4ACT is a one, the receiver analog input is connected to the transmitter analog output through a variable gain amplifier in a manner similar to recommendation V.54 loop 4. L4ACT IS reset to 0 by device reset.
L4HG
Loop 4 High Gain
0:4:5
When control bit L4HG is a one, the loop 4 variable gain amplifier is set for + 16 dB,
and when at zero the gain is zero dB. L4HG is reset to 0 by device reset.
1-75
R201/26DP
2400/1200 bps Data Pump Modem
Table 15.
R201/26DP Interface Memory Definitions (Continued)
Memory
Mnemonic
Name
Description
Location
MHlD
Mark Hold
0:7:4
When control bit MHLD is a one, the transmitter input data stream is forced to all marks
(ones). MHLD is reset to 0 by device reset.
(None)
RAM Access XB
2:5:0-7
Contains the RAM access code used in reading chip 2 RAM locations via word X (2: 3
and 2:2).
(None)
RAM Access XS
1 :5:0-7
Contains the RAM access code used in reading chip 1 RAM locations via word X (1 : 3
and 1 :2).
(None)
RAM Access XT
0:F:0-7
Contains the RAM access code used in reading chip 0 RAM locations via word (0: 1 and
0:0).
(None)
RAM Access YB
2:4:0-7
Contains the RAM access code used in reading chip 2 RAM locations via word Y (2: 1
and 2:0) .
(None)
RAM Access YS
1 :4:0-7
. Contains the RAM access code used in reading chip 1 RAM locations via word Y (1 : 1
and 1 :0).
(None)
RAM Data XBl
2:2:0-7
least significant byte of HI·bit word X used in reading RAM locations in chip 2.
(None)
RAM Data XBM
2:3:0-7
Most significant byte of 16·bit word X used in reading RAM locations in chip 2.
(None)
RAM Data XSL
1 :2:0-7
least significant byte of 16-bit word X used in reading RAM locations in chip 1.
(None)
RAM Data XSM
1 :3:0-7
Most significant byte of 16·bit word X used in reading RAM locations in chip 1.
(None)
RAM Data XTL
0:0:0-7
Least significant byte of 16·bit word X used in reading RAM locations in chip O.
(None)
RAM Data XTM
0: 1 :0-7
Most significant byte of 16-bit word X used in reading RAM locations in chip O.
(None)
RAM Data YBl
2:0:0-7
Least significant byte of 16·bit word Y used in reading RAM locations in chip 2.
(None)
RAM Data YBM
2: 1 :0-7
Most significant byte of 16-bit word Y used in reading RAM locations in chip 2.
(None)
RAM Data YSl
1 :0:0-7
least significant byte of 16-bit word Y used in reading RAM locations in chip 1. Shared
by parallel data mode for presenting channel data to the host microprocessor bus. See
'Receiver Data.'
(None)
RAM Data YSM
1:1:0-7
Most significant byte of 16-bit word Y used in reading RAM locations in chip 1.
RBDA
Receiver Baud
Data Available
2:E:0
Status bit RBDA goes to a one when the receiver writes data into register 2:0. The bit
goes to a zero when the host processor reads data from register 2:0.
RBIA
Receiver Baud
Interrupt Active
2:E:7
This status bit is a one whenever the receiver baud rate device is driving IRQ low.
RBIE
Receiver Baud
Interrupt Enable
2:E:2
When the host processor writes a one in the RBIE control bit, the IRQ line of the
hardware interface is driven to zero when status bit RBDA is a one.
RBPS
Receiver Data Rate
(bps)
1 :6:0
When control bit RBPS is a one and at device reset, the receiver data rate is set to
2400 bps. When control bit RBPS is a zero, the receiver data rate is set to 1200 bps.
(None)
Receiver
Configuration
1 :6:0-5
The host processor configures the receiver by writing a control code into the receiver
configuration field in the interface memory space (see RSB).
The bits included in this field and their initial values are RBPS (1: 2400 bps), RLRT
(0: RLSD Response Time = 6 ms), RV26 (0: V.26 Alternate B), HD2W (0: Full Duplex,
4·Wire), and TDET (0: Tone Detector Off).
(None)
Receiver Data
1 :0:0-7
The host processor obtains channel data from the receiver in the parallel data mode
by reading a data byte from the receiver data register. The data is divided on baud
boundaries as is the transmitter data. When using receiver parallel data mode, the
registers 1:3 through 1:0 can not be used for reading the chip 1 RAM.
RlRT
RLSD Response
Time
1 :6: 1
When control bit RLRT is a zero and at device reset, the RLSD Response Time is set
to 6 ms. When control bit RlRT is a one, the RLSD Response Time is set to 14 ms.
1-76
R201/26DP
2400/1200 bps Data Pump Modem
Table 15.
Mnemonic
Name
Ii
R201/26DP Interface Memory Definitions (Continued)
Memory
Location
Description
RPDM
Receiver Parallel
Data Mode
1 :7:4
When control bit RPDM is a one, the receiver supplies channel data to the receiver
data register (1 : 0) as well as to the hardware serial data output. (See Receiver Data).
RPDM is reset to 0 by device reset.
RSB
Receiver Setup Bit
1 :E:3
When the host processor changes the receiver configuration field or writes a one in the
SOH or SOHT control bits, the host processor must write a one in the RSB control bit.
RSB goes to zero when the changes become effective. Worst case setup time is 2 baud
times.
RSDA
Receiver Sample
Data Available
1 :E:O
Status bit RSDA goes to a one when the receiver writes data to register 1:0. RSDA
goes to a zero when the host processor reads data from register 1:0.
RSIA
Receive Sample
Interrupt Active
1 :E:7
This status bit is a one whenever the receiver sample rate device
RSIE
Receiver Sample
Interrupt Enable
1 :E:2
When the host processor writes a one in the RSIE control bit, the IRO line of the
hardware interface is driven to zero when status bit RSDA is a one.
RTDIS
Receiver Training
Disable
1 :7:0
When control bit RTDIS is a one, the receiver is prevented from recognizing a training
sequence and entering the training state. RTDIS is reset to 0 by device reset.
RTH
Receiver Threshold
Field
1 :7:6,7
The receiver energy detector threshold is set by the RTH field according to the following
codes (see RSB):
RTH
RLSD On
00
01
10
11
> -43 dBm
> -33 dBm
> -26 dBm
> -16 dBm
IS
driving IRO to zero.
RLSD Off
<-48
<-38
< -31
< -21
dBm
dBm
dBm
dBm
The RTH bits are reset to 00 by device reset.
RTS
Request-ta-Send
0:7:7
When control bit RTS is set to a one, the modem begins a transmit sequence. It
continues to transmit until RTS is reset to zero, and the turn·off sequence has been
completed. This input bit parallels the operation of the hardware RTS control input.
These inputs are ORed by the modem. RTS is reset to 0 by device reset.
RTSD
Request-to·Sendl
Disable Receiver
1 :F:7
When control bit RTSD is a zero and at device reset, the receiving Circuits are enabled.
When control bit RTSD is a one, the receiving functions are put in an idle mode. This
function is intended to be used for half duplex (2-wire) modem operation and gives the
user the ability to turn off the receiver when transmitting.
RV26
Receiver V.26 Alt.
AlAn. B Select
1 :6:5
When control bit RV26 is a zero and at device reset, V.26 Alternate B is selected. When
control bit RV26 is a one, V.26 Alternate A is selected.
SDIS
Scrambler Disable
0:7:5
When control bit SDIS is a one, and at device reset, the transmitter scrambler circuit is
removed from the data path. This bit must match the selection in the turn-on sequence
selection field (see table 4) i.e. the scrambler must be either enabled or disabled in
both.
SOH
Receiver Squelch
1 :F:6
When control bit SOH is set to a one, the receiver is squelched, RLSD is turned off
and RXD is clamped to all marks. SOH only affects the receiver operation when a half
duplex receiver configuration has been selected. (see RSB.)
SOHT
Receiver Squelch
Time
1 :F:5
This bit controls the duration of the squelch clamping (see SOH). If SOHT is a zero, the
squelch lasts for 100 ms, but if it is a one, the squelching lasts for 148 ms. SOHT is
reset to zero by device reset.
TBA
Transmitter Buffer
Available
O:E:O
This status bit resets to zero when the host processor writes data to transmitter data
register 0: O. When the transmitter empties register 0: 0, this bit sets to a one.
TBPS
Transmitter Dala
Rate (bps)
0:6:4
When control bit TBPS is a one and at device reset, the transmitter data rate is set to
2400 bps. When control bit TBPS is a zero, the transmitter data rate is set to 1200 bps.
TIA
Transmitter
Interrupt Active
0:E:7
This status bit is a one whenever the transmitter is driving IRO to a zero.
1-77
--
!
R201/26DP
240011200 bps Data Pump Modem
Table 15.
Mnemonic
Name
R201/26DP Interface Memory Definitions (Continued)
Memory
Location
Description
TIE
Transmitter
Interrupt Enable
0:E:2
When the host processor writes a one in control bit TIE, the IRQ line of> the hardware
interface is driven to zero when status bit TBA is at a one.
TDET
Tone Detector
Enable
1 :6:3
When control bit TDET is a one, the tone detector is disabled. TDET is reset to zero by
device reset.
TLVL
Transmitter Level
Field
0:4:2-4
The transmitter analog output level is determined by eight TLVL codes, as follows:
TLVL
Transmitter Analog Output"
000
001
010
011
100
101
110
111
-1
-3
-5
-7
-9
-11
-13
-15
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
±1 dB
±1 dB
±1 dB
±1 dB
±1 dB
± 1 dB
± 1 dB
± 1 dB
"Each step above is a 2 ± 0.2 dB change
The TLVL bits are reset to 000 by device reset.
TOD
Train-on Data
1 :6:6
When control bit TOD is a one, it enables the train-an-data algorithm to converge the
equalizer if the signal quality degrades suffiCiently. When TOD is a one, the modem still
recognizes a training sequence and enters the force train state. A BER of approximately
10- 3 for 0.5 seconds initiates train-on data. TOD is reset to 0 by device reset.
TODF
Train-On Data Flag
1 :A:7
Indicates Train On Data in process.
TONE
Tone Detect
1 :9:2
TONE indicates with a zero the presence of energy in the 345-650 ± 10 Hz frequency
range. For call progress purposes, the user may determine which tone is present by
detsimining the duty cycle of the TONE bit.
TPDM
Transmitter Parallel
Data Mode
0:7:2
When control bit TPDM is a one, the transmitter accepts data for transmission from the
transmitter data register (0: 0) rather than the serial hardware data input. TPDM is reset
to 0 by device reset.
(None)
Transmitter
Configuration
0:6:0-7
The host processor configures the transmitter by writing a control byte into the
transmitter configuration register in its interface memory space. (See TSB)
The bits included in this field and their initial values are DTMF (0: DTMF Generation = Off),
TTONE (0: Transmit Tone = Off), TV26 (0: V.26 Alternate B), TBPS (1: Transmitter Data
Rate = 2400 bps, and Turn-on Sequence Selector (2: see Table 4).
(None)
RAM DATA XTLI
Transmitter
DataJDDR
0:0:0-7
The host processor conveys output data to the transmitter in the> parallel mode by writing
a data byte to the transmitter data register.
TSB
Transmitter
Setup Bit
0:E:3
When the host processor changes the transmitter configuration field (DTMF, TTONE,
TV26, TBPS, or the Turn-on sequence selector field), the host must write a one in this
control bit. TSB resets to zero when the change becomes effective. Worst case setup
time is 2 baud + turnoff sequence + training (if applicable).
TTDIS
Transmitter Train
Disable
0:7:6
When control bit TTDIS is a one, the transmitter does not generate a training sequence
at the start of transmission. With training disabled, RTS/CTS delay is less than two baud
times. TTDIS is reset to 0 by device reset.
When the transmitter is configured for DTMF dialing, this register becomes the Dial Digit
Register (DDR). Refer to figure 3 for the proper Auto Dialing Procedure.
1-78
I
2400/1200 bps Data Pump Modem
R201/26DP
Table 15. R201/26DP Interface Memory Definitions (Continued)
Mnemonic
Name
TTONE
Transmit (Single)
Tone Output Select
Memory
Location
0:6:7
Description
When this bit is set to a one, the single tone output mode IS selected. To initiate a tone,
the TSB bit must be set to a one for each tone desired. The R201/260P does not
perform a timeout on the tone; thus the host must perform its own timeout to know
when to start the next tone. TTONE is reset to zero by deVice reset.
The proper operational sequence to generate a tone is given below·
1. Set the TTONE bit.
2. Load the desired value mto FREOM/FREOL (see FREOUFREOM)
3. Set the TSB bit.
4. Wait for deSired timeout.
5. Repeat steps 2, 3, and 4 until all desired tones have been generated.
6. Reset the TTONE bit.
(None)
Turn-on Sequence
Selector Field
0:6:3-0
Selects the turn·on sequence timing and whether or not the scrambler is in the circUit.
See 'SOlS' and Table 4. This field IS set to 0010 (Turn-on sequence number 2) by
deVice reset.
TV26
Transmitter V.26
Alt. AlAIt. B Select
1 :6:5
When control bit TV26 is a zero and at device reset, V.26 Alternate B is selected. When
control bit TV26 IS a one, V.26 Alternate A is selected.
T2
T/2 Equalizer
Select
1 :7:1
When control bit T2 is a one, an adaptive equalizer with two taps per baud IS used.
When T2 is a zero, the equalizer has one tap per baud. The total number of taps
remains the same for both cases. T2 is reset to 0 by device reset.
WBRO
Write to Baud Rate
Device (Receiver #2)
1:7:2
When control bit WBRO IS a one, data Is written into receiver device 2. WBRO is reset
to zero by device reset.
WSRD
Write to Sample Rate
Device (Receiver #1)
1:7:3
When control bit WSRD is a one, data is written into receiver device 1. WSRD is reset
to zero by device reset.
XCEN
External Clock
Enable
0:7:1
When control brt XCEN is a one, the transmitter timing is established by the external
clock supplied at the hardware input XTCLK, pin 22A. XCEN is reset to 0 by device
reset.
POWER-ON INITIALIZATION
PERFORMANCE
When power is applied to the R201/260P, a period of 50 to
350 ms is required for power supply settling. The power-on-reset
signal (POR) remains low during this period. Approximately
10 ms after the low to ~transition of POR, the modem is ready
to be configured, and RTS may be activated. If the 5 Vdc power
supply drops below 3.5 Vdc for more than 30 msec, the POR
cycle is generated.
Functioning as either a Bell 201 or a V.26/V.26 bis type modem,
the R201l260P provides the user with excellent, reliable
performance.
TYPICAL BIT ERROR RATES
The Bit Error Rate (BER) performance of the modem is specified
for a test configuration conforming to that specified in CCITT
recommendation V.56. Bit error rates are measured at a received
line signal level of - 20 dBm as illustrated in Figures 4 & 5.
Figure 6 shows the BER test equipment set up.
At POR time the modem defaults to the following configuration:
V.26B/Beli 201 B/C, short train, full-duplex, T, no echo protector tone, serial data mode, internal clock. transmitter output level
set to -1 dBm ± 1 dB, receiver threshold set to - 43 dBm, eye
pattern selectable, train-on data disabled, the tone generator
is off, RLSO response time set to 6 ms, the tone detector is off,
no extended squelch, and squelch clamping set to 100 ms.
TYPICAL PHASE JITTER
At 2400 bps (V.26 Alternate A or B), the modem exhibits a bit
error rate of 10- 6 or less with a signal-ta-noise ratio 0112.5 dB
in the presence of 15° peak-to-peak phase jitter at 150 Hz or
with a signal-ta-noise ratio of 15 dB in the presence of 30° peakto-peak phase jitter at 120 Hz (scrambler not inserted, equalizer
not inserted).
POR can be connected to a user supplied power-on-reset signal
in a wire-or co~ratlon. A low active pulse of 3 !'Sec or more
applied to the POR pin causes the modem to reset. The modem
is ready to be configured 10 msec after POR is removed.
1-79
2400/1200 bps Data Pump Modem
R201/26DP
10-'
10-'
\
\
\
\
~
\
10-'
~
1\ 0
0
\
10-'
w
w
l-
\
I-
e
II:
II:
~
\
~
II:
0
\
II:
W
iii
10-'
'\
II:
II:
W
!\
\
I-
\
I-
iii
10- 5
,
~
\
\
10- 8
4
5
6
\
\
\
14
15
4
Conditions:
1. 1200 bps, Back-to-Back, scrambler, no equalizer,
RX level = - 20 dBm.
2.2400 bps, V.26 AlB Back-to-Back, scramblsr, no
equalizer, RX level = - 20 dBm.
Figure 4.
\
10- 8
7
10 11 12 13
9
8
SIGNAL TO NOISE RATIO (dB)
5
8
7
8
9
10 11 12 13
SIGNAL TO NOISE RATIO (dB)
Conditions: 2400 bps, V.28 AlB, 3002 line,
no scrambler, equalizer, RX level
Typical BER Performance Back-ta-Back.
Figure 5.
14
= - 20 dBm
Typical BER Performance 3002
Unconditioned Line.
300-3400 HZ
MODEM
TRANSMITTER
-
NOISE
SOURCE
GR1381
5 KHZ BW
r---
LINE
SIMULATOR
(3002)
r---
-
FILTER
ATTENUATOR
COMSTRON ~
HP350D
FA2874
IMPAIRMENT
SOURCE
BRADLEY 2A
AND 28
1
r--
ATTENUATORr----HP 3500
I
E
1--
LEVEL
METER
HP3555B
MODEM
RECEIVER
I
I
MODEM
TEST SET
PHOENIX 5000
Figure 6.
BER Performance Test Set-up
1-80
15
R201/26DP
2400/1200 bps Data Pump Modem
GENERAL SPECIFICATIONS
Table 10.
Modem Power Requirements
Voltage
Tolerance
Current (Typical) @ 25°C
Current (Max) @ OOC
+5 Vdc
+12 Vdc
-12 Vdc
±5%
±5%
±5%
550 rnA
5 rnA
25 rnA
<700 rnA
< lOrnA
< 50 rnA
Note: All voltages must have ripple sO. 1 volts peak-to-peak.
Modem Environmental Restrictions
Parameter
Specification
Temperature
Operating
Storage
Relative Humidity:
Altitude
OOC to +60 o C (32°F to 140°F)
- 40°C to + 60°C ( - 40°F to 176°F) (Stored in heat sealed antistatic bag and shipping container)
Up to 90% noncondensing, or a wet bulb temperature up to 35°C, whichever is less.
-200 feet to + 10,000 feet
Modem Mechanical Considerations
Parameter
DIN Connector Version
Board Structure:
Mating Connector:
Dimensions:
Width
Length
Height
Weight (max):
Lead Extrusion (max.):
Specification
Single PC board with a 3-row 64-pin right angle male DIN connector with rows A and C populated.
The modem can also be ordered with the following DIN connector: 64-pin DIN right angle female,
64-pin DIN vertical male or 64-pin DIN vertical female.
Female 3-row 64-pin DIN receptacle with rows A and C populated. Typical mating receptacle:
Winchester 96S-6043-0531-1, Burndy RI96B32ROOAOOZ1, or equivalent.
3.937 in. (100 mm)
4.725 In. (120 mm)
0.40 in. (10.2 mm)
3.6 oz. (100 g)
0.100 In. (2.54 mm)
0.156 :I: 0.003 DIA (6 PL)
(3.96)
MALE 64-PIN
DIN CONNECTOR
OA96
(12.6)
0.119
(3)1
0.463
(12.3)
OA37
UNITS: INCHES
mm
COMPONENT AREA
R201/26DP Board Dimensions and Pin Locations
1-81
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"
'
"~,I
"
PIn
,:' PIn~nct'i=ttmWIN
CompatIble With
'.
,',
CompatIble
" 1!rith,.' ,
,
"
,
".
,.'
,
,
""
';
-
"
,
',"
,
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,
'
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.
.~
.
'
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, )"
/'
;,'
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"RC12,12
, ":-,i;,~~.'
,',
"
'
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:'
,
,
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,
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RC1212
1200 bps Full Duplex Modem
ATS
CTS
TXO
TDClK
XTCLK
V.24
INTERFACE
ALSO
AXO
RDCLK
r
D'fii
OSA
AI
ACCT
CCT
OH
READ
OAA
RO
..
"
r--}
1+-.
WRITE
DATA BUS (8)
ADDRESS BUS (5)
HOST
PROCESSOR
(OTE)
~
I
RC1212
MODEM
AXA
TXA
DECODER
r
CS(2)
IAQ
(
+5
..A
POA
J
ANALOG
INTERFACE
1'1
TBCLK
1'1
RBCLK
TlK
OAG
+5V
+12V
POWER
SUPPLY
J
L
-12V
AGND
DGNO
RC1212 Modem Functional Interconnect Diagram
1·83
ANCILLARY
CIRCUIT
INTERFACE
TELEPHONE
LINE
"
'''',
',~
,/' '
'
,·RC2424
Integral
MOrJems
• COmpatibilitieS
"':'A/l Models: (lCITT V.22 bis, V.22A1B and V.21 and Bell
212A8nd 103
'. '-R024241DME: AboVe Modes Plus COITT V.23 and Bell
c
"'202'
.
,'. Syncnl'OnoUs: 2400 bps, 1200 bps, 600 bps
rntets
ThebasicRC2424l1'1Oderii
the rSquii'ert\ent$si*lfled in,
.• AsYnchronous: 2400 bps. 1200 bps. 600 bps ( +1%,
'ooITTV.221>I,II, V22A1S;endV.21,.wellas~t2.12Aand/9tllI' '. '
:"2.5%)1 ().$OO bps
103. The,RC242I11OM£!ncf~dejlaV;~,~·device..to'pI'C!- " . 'ChAract!l"l.sI'I!lth:8,9, 10, or 11 bits
·vlde asynchronous, fiI~opei8tioMt 1~,bpl1 Wiffi,~
,. , Dyrillmlc ReceiVe Range: 0 dBm to - 48 dBm
wards chlll1nei up to 150 bpl1";",
. ,', "
,','
+2,3%,
"."l"aollitaiesAutil Speed Recognition
i,
TheRC2424JOMar.d:~~~~.
'•. ,::~m:b:1
,8ddlti()nalcll'CUifi1'tO~the ~tQ ,~,DIh~
. 1 o ;.o1E interface .
Progress Tone
Detection
~(I:!AA): ;,TheDlP~~ :~'$qWre.· '.. ,,:':'" FlinCtional: MicrOprocessor Bus (DatalConflgurationl
, inches)~be,handI$l:Ibyautornatecf:manu~eqoipm!ll'lt', '. " "; . ContrOl) andCCITT V.24 (RS-232.(l) (DatalControJ)
, . for i~(1Qn and SOldering onto a ha$t boan:l..·
- EleCtlical: TTL IlI1d CMOS cornpa1ibie
• ,Equallzation:"
,
...:.,:Au«fAdSptive (Receive)
...:. Fixed Compromise (lI'ansmit)
'. AufulManual Answer
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.:..
lriparafleloverthemicroJ)l'OCleisorbujllntei'filCe;Thejleoptioml>
. combined with a ilsereCcessible, dual. port $CratCb Pad RAM '(lila "
.
the microprocessor bull),providethedasignerri\axlmumifleXll;>Il- , .
ity inCu$ton'tizing theAC2424 fora~:¥at1ety,Of:fUnetionar,
, , '
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requi~.
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:
• Programmable Pulse and DTMF Tone Generation
• 'SljlllCtai3le:Guard Tone Generation (1800 Hz or 550 Hz)
• 1l!&t Modes .
'.' - Local Analog I..oopback
, . ':"":' Remote Digital Loopback
. ...:. Digital LoopbaCk
•'
.... S811.Test
.
.
. • I-OwPQWer ConsumptiOn
. " - RC2.4241OS and AC24241OM: 400 mW (lYplcal)
,..::.:. R024241DME: 500 mW (1YpIcal)
.: .PaCkaging
" - AC2424/DS 2·DeVice Set:
Digital Signal Processor (OSP); 64-pin QUIp, 68-pin PLeC
. Analog Filter: 40.pin DIP, 44-pin PLCC
. .PIit imd i=lrri'WIth
tWare".. .
.COropa_
:fIC1212tDs\ . .
•...,..,RC2.424IOM and AC2424IOME Modules
.50;8 mm
)C
88.9 mm (2.0in. x 3.5 in.)
~~~;AC:i2~~i;';
.,., ..,.':.ar--wr-----------------------------------------------------,
pc>------------------------------------------------,
TXA
T>-+-r---~--_t-J ~+-t---ro
~+_------------+_~RXA
~----------------------~------+_------------+_~OH
L!!~j---~--------~w.---r:::------------·y.·.I11
...--,
...
Figure 3. RDAA Functional Block Diagram
Table 2·1. RDAA Intarface Circuits
Signal Direction To:
LeIId Designation
User
Both
RDAA
R,T
MI, MIC
PR,PC
+5V, +12V, -12V
SG
RDI
RCCT
OH
SH
CCTI
TXA
RXA
Function
X
X
X
Transmission leads for data signals.
Leads to telephone set switch hook.
Leads to programming resistor.
X
Signal ground required.
Ringing signal present indication.
To request data transmiSSion path cut through.
To control Off-Hook relay.
Status of telephone set switch hook.
Transmission path cut through indication.
Lead to modem output.
Lead to modem Input.
X
DC power required.
X
X
X
X
X
X
X
1-88
RDAA
Rockwell Data Access Arrangement Module
SG
NOTE
WARNING. If OH IS asserted to a logiC high before the
Incoming call ring signal is completed, the OH reed relay
switch contacts may suffer degradation.
The SG (Signal Ground) IS the common reference for all modem
Interface signals.
RDI
RDt (Ring Detect) indicates to the user by an ON (Low) condition that a ringing signal IS present. The RDt signal will not
respond to momentary bursts of ringing less than 125 ms In duration, or to less than 40V rms, 15 to 68 Hz appearing across Tip
and Ring with respect to ground. RDt is also used to disable
the transmission path. The electrical characteristics of the RDt
signal are shown in Table 2-2.
SH
An ON (High) signal on the SH lead indicates to the user that
the aSSOCiated telephone (if used) IS in the talk mode I.e., a contact closure exists between MI and MIC. The characteristics of
the SH Signal are shown In Table 2-2.
CCTI
Table 2-2. Output Signals RDt
SH and CCTt Characteristics
Output
Logic State
CCTt is the Coupler Cut Through. An ON (Low) signal to the
CCTtlead indicates to the user that the data transmiSSion path
through the RDAA is connected. The ON (Low) state does not
indicate the status of the telephone line or connection. The
characteristics of the CCTt signal are shown in Table 2-2.
Output Levels
0.0 to O.4V while sinking < 1.6 rna
2 4 to 5.0V while sourcing < 40 ",A
LOW
HIGH
TXA
TXA (Transmit Analog) is the lead from modem transmitter output. This lead should be tied to GND when the modem is in the
receive only mode.
RCCT
RCCT (Request Coupler Cut-Through) is used to request that
a data transmission path through the RDAA be connected to
the telephone line. When RCCT goes OFF (Low), the cut-through
buffers are disabled and CCT will go OFF (High) within 1 millisecond. RCCT must be OFF (Low) during dial pulsing but ON (High)
for tone address signaling. The electrical characteristics of the
RCCT signal are shown in Table 2-3.
RXA
RXA (Receive Analog) is the lead to modem receiver input. This
lead may be left open when the modem IS in the transmit-only
mode.
POWER REQUIREMENTS
The following power must be provided at the RDAA interface.
Table 2-3. Input Signals RCCT and OH Characteristics
Input
logic State
OFF or LOW
ON or HIGH
A. + 12 VDC ± 5% @ 15 ma with a maximum ripple of 50 mv
peak-to-peak
Input Levels
RCCT
OH
~
~
0.0 to O.BV, load current"" 0.36 rna
2.0 to 5.0V, load current"" 20 ",a
2.0V, load current"" 100 ",a
5.0V, load current"" 250 ",a
B.
+5 VDC ±5% @ 20 ma with a maximum ripple of 100 mv
peak-to-peak
C. -12 VDC ± 5% @ 15 ma With a maximum ripple of 50 mv
peak-to-peak.
OH
OH controls the OFF-HOOK relay. Applying an ON (High) signal
to OH closes the OH relay and establishes a DC path between
T and R. Maximum delay between the ON signal to OH and the
close of the OH relay IS 10 ms. When originating a call, an ON
(High) Signal is used to request dial tone. After detecting dial
tone, OH can be pulsed to generate the dial pulses corresponding to the number of the called station (see Section 4.2).
On incoming calls, an ON (High) signal to the OH lead initiates
the answering sequence (see Section 4.1). The characteristics
of the OH signal is shown in Table 2-3.
HAZARDOUS VOLTAGE PROTECTION
l.Jghtning induced surge voltages and other hazardous voltages
are limited to 10.0 volts peak between the secondary leads of
the coupling transformer T1. The isolation between the relay
contacts and coils prOVides the protection of the telephone line
from hazardous voltages appearing on any control lead.
1-89
Rockwell Data Access Arrangement Module
RDAA
RING DETECTOR AND TIMER
The output control circuitry contains a variable gain buffer which
reduces the RDAA output to the maximum allowed level across
T and R. When the RDAA IS jumpered to operate in the Programmable mode, the resistor in the telephone company wall
jack sets the output level to one of thirteen poSSible values. If
the RDAA is jumpered to operate in the Permissive mode, then
an internal resistor Will set the output to a fixed value. The relationship between the RDAA input amplitude (in dBm) across
TXA and GND and the nominal RDAA output level across T and
R is given below:
When the Ring Detector detects the presence of a ringing signal
ranging from 15.3 to 68 Hz with voltage levels of 40 to 150 VRMS
across Tip and Ring (T and FrI) leads, after a delay of 125 ms
to 500 ms, it will send an RDI (Ring Detect) signal to the user's
data terminal equipment (DTE). If the DTE is conditioned for
answering, the DTE will return an ON signal on OH and RCCT.
The OH signal closes the OH relay and starts a timer. The timer
is used to provide a quiet interval of more than two seconds
between the closing of OH relay and the connection of data
transmission path. This allows the telephone company to properly engage their billing equipment. After this delay the CCT!
interface lead goes ON (Low) and data transmission may begin.
A. For Programmable mode: output level across T and R
(input amplitude at TXA - 7 dB + (Programmed level set by
wall jack resistor).
RDI will go OFF (High) in less than 400 MSEC after the ringing
signal is stopped. The ring detector is disabled when OH is ON
(High) or SH is ON (High).
B. For Permissive mode: output level across T and R = (input
amplitude at TXA) -16 dB.
SIGNAL LEVEL LIMITER AND GAIN
CONTROL CIRCUITRY
IMPEDANCE SPECIFICATIONS
On-Hook DC:
The DC resistance between T and R,
and between either T or R and signal
ground are greater than 10 megohms
for DC voltages up to 100 volts.
On-HookAC:
The on-hook AC impedance
measured between T and R is less
than 40K ohms (15.3 Hz minimum).
NOTE
Off-Hook DC:
Less than 100 ohms.
The off-hook relay is not affected by the limiting function,
therefore, so triggering the limiting function need 1101 resutt
in call termination.
Off-Hook AC:
600 ohms nominal when measured
between T and R.
TXA and GND:
2 megohms typical (operational
amplifier voltage follower input
impedance).
RXA and GND:
75 ohms typical (operational amplifier
voltage follower output impedance).
The limiter monitors the signal level applied to the RDAA input
lead TXA and is unaffected by the level of receive signal. When
the applied signal amplitude becomes greater than + 7 dBm for
a period of 1.3 to 3 seconds, the transmission path is disconnected via the transmit and receive buffers, and the output signal
CCT! will go OFF (High).
Reducing the input signal amplitude to less than + 7 dBm will
reset the limiter in less than 4 milliseconds, restore the data
transmission path, and cause the signal CCT to go ON (Low).
In order not to activate the limiter during normal operation, care
must be taken to ensure that the maximum Signal amplitude Into
the RDAA input TXA never exceeds +6 dBm. If the modem
output has a tolerance of ± 1 dB, then it is recommended to set
the modem output to +5 dBm (± 1 dB), so that the maximum
signal amplitude into TXA is 6 dBm.
INSERTION LOSS
There is no insertion loss for the RDAA. The RDAA contains a
receive buffer which compensates for transformer Insertion loss.
For this reason, additional receive buffering is not necessary.
1-90
RDAA
Rockwell Data Access Arrangement Module
SECTION 3 -
INSTALLATION/CHECKOUT
TELEPHONE SET AND JACK
ORDERING INFORMATION
RDAA CONNECTION TO TELEPHONE LINE
Connection of the telephone line interface pins of the RDAA to
the network shall be made via standard Jacks and plugs as
shown in Figure 4. Cable color codes are also shown in Figure
4. A number of telephone Ime cord manufacturers produce the
standard plugs and cables (Meyer Wire Co., Hamden, CT; Vir·
glnla PlastICs, Roanoke, VA, etc.)
-
~
•,
,
USOC
RJ45S
·
7
•
If it is desirable to have manual call origination or alternate voice
capability, an exclusion key telephone set may be ordered from
a local telephone company. The telephone line may be trans·
ferred to the telephone set by lifting both the handset and the
exclusion key, if the telephone is configured as Data Set Con·
trois Une. This operation is for manual origination or alternate
voice transfer (refer to paragraph 4.4 for manual origination pro·
cedure). A call may be terminated by replacing the handset in
ItS cradle and taking OH low if OH IS not already low.
MI
BLACK
,-.
RED
SILVER
~
.IIM
~
PR
......,
STANDARD
CABLE
BLACK
JACK
PC
REO
•
GREEN
5
VELLOW
3
5
4
-1'
6
L ______ J
I JACK
RJ16X
r-------,
:t~~~o~E LT~T~T--l.:T-=TJ
ADA" PAOGFIAMMABLE
000£
,-..
MI
R
T
MIC
TO RDAA
R
ROM
T
~
~
~
--2
MI
3
STANDARO
PLUG
R1
T1
r l:=~i:jNEI ~
MIC
JACK
-
MIC
T
YELL.OW
BROWN
STANDARD
PLUG
MI
R
GREEN
TO JACK
SUCH AS
{
RJ36X
SHOWN ON
FIGURE 3-2
MIC
TO MINIATURE 6 POSITION JACK
~
1'1
STANDARD
CABLE
I
l'
I
I
ADAPTER
RJA2X
I
AJ41S IS A UNIVERSAL JACK WHICH
CAN BE UTILIZED WITH EITHER
1
THE PROGRAMMABLE MODE OR
FixeD LOSS LOOP !FLLJ MODE
2
3
.1J~
r----:l
l.TJJJJ.:TJ
RJ41S
JACK
6 POSITION
MINIATURE PLUG
Figure 4.
Standard Jacks, Plugs and Cable Color Codes
1·91
I
I
I I
1
2
3
,~,.
rl'- - - -1"
L: :JJ_11~: J
6 POSITION
MINIATURE PLUG
RDAA
Rockwell Data Access Arrangement Module
The ringer of the telephone set may be disconnected by the
telephone company to prevent the bell from ringing.
When ordering this telephone, specify the USOC number RTC
and the following options:
The telephone company provides an exclusion key telephone
under the Universal Service Order Code (USOC) RTC. This telephone set has the following customer options:
A. A2 - Data set controls line
B. B3 - Aural monitoring not provided
or
B4 - Aural monitoring provided
A. A 1 - Telephone set controls line
C. B3 - Aural monitoring not provided
C. C5 - Touch tone dial telephone (503C)
or
C6 - Rotary dial telephone (2503C)
O. B4 - Aural monitoring provided (See Note 1)
D. 08 - Voice mode Indication only
B. A2 - Data set controls line
E. C5 - Touch tone dial
Another telephone set provided by the telephone company is
the Model 502 with exclusion key. To order this telephone set,
specify the following:
F. C6 - Rotary dial
G. 07 - Switch hook indication
H. 08 - Voice mode indication only (See Note 2)
A. Modem 502 with exclusion key
B. Data set controls line
NOTES
A summary of the informallon for ordering telephone and jacks
is given in Table 3-1. Examples of typical installation are given
in Figure 3-2.
1. The aural monitoring feature allows the telephone
handset to be used for listening to line signals without
interfering with data transmission.
2. In this option the make contact of the exclusion key and
a make contact on the switchhook are connected in
series and to the mode indication leads MI and MIC of
the data jack. Therefore, the SH signal of the ROM
goes ON only when the exclusion key is lifted.
Table 3-1. Telephones and Jacks Ordering Information
Output
Configuration
Optional
Telephone Set
Programmable
With
Telephone Set
Without
Telephone Set
PermiSSive
With
Telephone Set
Without
Telephone Set
Talephone Jack
USOC No.
FCC
Reg. No.
Ringer
Equivalent
AMQ9SQ
67943
DP-E
AMQ9SQ
67943
DP-E
AMQ9SQ
67943
DP-E
AMQ9SQ
67943
DP-E
.86
'RJ36X and
2.3RJ45S
.86
23RJ45S
.86
'RJ36X and RJ 16X
or
4RJA2X and RJllC
RJllC
.86
Telephone Set
USOC No.
RTC or 502
with exclusion key
N.A.
RTC or 502
with exclusion key
N.A.
Notes:
1. RJ36X is an 8 position miniature jack Into which the telephone plugs. Rather than using an RJ36X jack, the telephone company may use a
connecting block to connect the telephone set and data jack to the telephone line.
2. RJ41 S IS a universal data jack. It may be used for either Programmable or Fixed-Loss Loop mode The RJ45S jack IS preferred, because It
costs less
3. For muHipie connections, the RJ45M jack should be ordered. The letter M indicates multiple single line jack for up to 8 lines. Specify the number
of lines required when ordering.
4. RJA2X is the adapter shown In Figure 3-1. The use of the RJ36X and RJ16X jacks IS recommended.
1-92
RDAA
Rockwell Data Access Arrangement Module
TODTE
OH Reel ADI SH ceTI
TXA
A
TOOTE
MODEM
ROAA
MIC 1
MI
TX
OUTPUT
T
T
AXA
MIC
AX
INPUT
STANDARD
MINIATURE
PLUG
RJ36X 4
JACK
,....
CORD
,. 1
3
).
I
I
) 5
, 6
)
EX
I
2
}
NETWORK
I
J
JII~
7
8
EX
+
1
P
"' ....
"
: }TO NETWOA
l~H
K
EX
1.
2.
3.
4.
BRIDGiNG
TRANSFORMER
ATe
OPTIONED FOR DATA seT
CONTROL OF THE LINE
MI AND MIC ARE REQUIRED ONLY IF HANDSET IS USED.
PR AND PC ARE REQUIRED FOR PROGRAMMABLE MODE ONLY.
STANDARD TELEPHONE CO. PROVIDED JACK RJ16X, RJ45S OR RJ41S.
RJ36X OR CONNECTING BLOCK IS REQUIRED ONLY IFTELEPHONE HANDSET IS USED. WHEN THE RDAA
IS IN THE PERMISSIVE MODE, THE RJA2X ADAPTER AND RJ11C OF FIGURE 4 MAY BE USED WITH THE
ASSOCIATED TELEPHONE SET.
Figure 5.
Transmit and Receive (Half Duplex) and (Full Duplex)
MODEM INTERFACE
There are 4 possible two-wire modes of operation configurations: receive-only, transmit-only, and receive and transmit (half
duplex) and full-duplex (using two different frequencies simultaneously) as described below:
C. For the transmit-only configuration, the RDAA lead RXA is
left open rather than connected to the modem receiver as
shown in Figure 5.
A For the half-duplex and full-duplex configurations, the interface connection circuitry could be as shown in Figure 5.
For a 4-wire full-duplex configuration, 2 RDAA modules and 2
telephone lines are required. The connection circUitry consists
of one 2-wire receive-only connection, and one 2-wlre transmitonly connection.
B. For the receive-only configuration, the connection circuitry is
the same as that shown In Figure 5, except that the RDAA
input lead TXA is grounded rather than connected to the
modem transmitter output.
1-93
RDAA
Rockwell Data Access Arrangement Module
MODULE MOUNTING' AND SECURING
Care must be taken in routing the telephone interface pins to
the telephone jack. The FCC (Rules, Part 68) reqUIres that the
telephone Interface leads shall be separated from the leads or
metallic paths connecting to power connections.
The RDAA may be physICally incorporated into the OEM's end
product by using the four corner (0.156 inch diameter) mounting
holes and self-locking plastic standoffs, or by bolting the RDAA
module to a rigid structure. The RDAA module may also be
mounted using card guides without card edge connector.
NOTE
Power connections are those connections between commercial power and any transformer, power supply rectifier,
converter, or other circuitry associated with the RDAA.
The connection of the interface pins (Including the ±12V
and +5V) shown in Flgure.2 are not power connections.
A number of manufacturers such as Richlock Corporation, Chicago, IL., produce plastic standoffs (Part Number CBS-3N).
ELECTRICAL INTERFACE
Electrical connection to the RDAA module is made through
ribbon type connectors. The connector(s) interface pins (Figure
2) are contained on the component side of the board. There are
two test points brought out to the interface connector of the
board. Therefore care must be taken to prevent shorting test
points with any of the other interface signals.
The telephone Interface leads shall not be routed In the same
cable (or use the same connector) as leads or metallic paths
connecting to commercial power.
FCC (Rules, Part 68) also requires that the telephone leads T
and R be separated from metallic paths to leads connecting to
non-registered eqUipment, when speCification details provided
to FCC do not show that the interface vottages are less than
non-hazardous voltage source limits in Part 68. T and R shall
not be routed in the same cable (or use adjacent pins on the
same connector) as metallic paths to leads which are not considered non-hazardous. All DTE interface connector signals
shown in Table 3-2 have been established as non-hazardous.
The RDAA telephone line interface connector pins are physically
separated from the RDAA DTE interface connector pins, as
shown in Figure 2 and described in Table 3-2.
Therefore, in routing the telephone interface leads from the
RDAA P1 connector to the telephone jack, the following precautions must be strictly adhered to. The telephone jack interface routing path should be as direct as possible. Any cable
used in establishing this path should contain no signal leads
other than possibly the (prevIously established as non-hazardous) DTE interface Signals shown in Table 3-2. Any connector used in establishing this path should contain no
commercial power source signal leads, and adjacent pins to the
T and R (Tip and Ring) pins in any such connector should not
be utilized by any signals other than possibly those shown in
Table 3-2. Also the DTE interface routing path should be made
as short as possible.
Table 3-2. RDAA Telephone and
Modem Interface
Type
Interface
Circuit
DTE
Interface
Connections
RDAA
Connectors!
Pin No.
Interface
Circuit/Signal
P2-1
P2-2
P2-3
P2-4
P2-S
P2-6
P2-7
P2-B
P2-9
P2-10
CCT!
RXA
TXA
OH
RCCT
RD!
-12V
SH
GND
TP2 EXCESSIVE
POWER DETECT
+12V
+SV
N/U
TP1 BILLING
DELAY TIME
P2-11
P2-12
P2-13
P2-14
Telephone
Line
Interface
Connections
Pl-4
Pl-3
PH
Pl-2
P1-(S-B) & (11-12)
Pl-9.10
PH3, 14
INSTALLATION PROCEDURE
A. Check the telephone line interface cable(s) plug(s) and jack(s)
(Figure 4). If the USOC RJ41 S jack is used for the Programmable mode, ensure that the jumper W2 is installed and W1
jumper is removed for the programmable mode of operation.
B. Make sure the telephone company installer has measured
the loop loss correctly and has selected the proper programming resistor in the RJ45S or RJ41S jack.
PC
PR
MIC
MI
(Not Used)
R
T
NOTE
You have the right to know the method used by the
installer for measuring loop loss and selecting the programming resistor.
1-94
RDAA
Rockwell Data Access Arrangement Module
A. All direct connections to the telephone lines shall be made
C. Check the power supplies to see if they meet the proper
requirements specified in paragraph 2.2.
through standard plugs and jacks as speCified in Figure 4
and Table 3-1.
D Insert the telephone cable plug into the jack, and make the
DTE Interface connection. Then sWitch on the power supplit s.
B. It is prohibited to connect the RDAA to pay telephones or
party lines.
OPERATIONAL CHECKOUT PROCEDURE
C. You are required to notify the local telephone company of
the connection or disconnection of the RDAA, the make, the
modem number, the FCC registration number, the nnger
eqUivalence number (refer to Table 3-1) and the particular
line to which the connection is made. If the proper Jacks are
not available, you must order the type of jacks to be used
from the telephone company. (Refer to Table 3-1 for the
proper jacks and telephones.)
The following procedures check out the RDAA in association
with a modem, a data terminal, a telephone set and an automatic dialer. The telephone set IS reqUired only in the mam,al
onglnatton mode (refer to paragraph 4.4) or if alternate vOI~e
communication IS desired. The automatic dialer IS reqUired 01 dy
In the automatic dial mode (refer to paragraph 4.3).
D. You should disconnect the RDAA from the telephone line If
it appears to be malfunctioning. If the RDAA needs repair,
return it to Rockwell International. This applies to equipment
both in and out of warranty. Do not attempt to repair the Unit
as this Will violate the FCC rules.
AUTOMATIC ANSWER MODE
A. Set the, modem transmitted output level to +5 dBm.
B. Call the local modem from a remote station.
C. Follow the Instructions given In Figure 6.
E. The RDAA contains protective CIrcuitry to prevent harmful
voltages being transmitted to the telephone network. If however, such harmful voltages do occur, then the telephone
company has the right to temporarily discontinue your service. In this case, the telephone company shall:
D. Transmit data from the local terminal to the remote terminal
and monitor the CCT / signal. It should stay low.
E. Terminate the call sequence and verify the received data.
AUTOMATIC ORIGINATE MODE
1. Promptly notify you of the discontinuance.
A. Set the modem transmitted output level to +5 dBm.
2. Afford you the opportunity to correct the situation that
caused the discontinuance.
B. Follow the procedure of Figure 8 for touch tone origination
or Figure 7 for pulse dial origination.
3 Inform you of your nght to bring a complaint to the FCC
concerning the discontinuance.
C. Transmit data from the local terminal and monitor the CCT!
signal. It should stay low.
F. The telephone company also has the right to make changes
In their faCilities and services which may affect the operation
of your equipment. However, you shall be given notice in
writing by the telephone company adequate to allow you to
maintain uninterrupted service.
D. Terminate the call sequence and verify the received data.
MANUAL OPERATION MODE
A. Set the modem transmitted output level to +5 dBm.
G. Labeling ReqUirements:
B. Follow the instructions given in paragraph 4.4.
C. Transmit data from the local terminal. CCT should stay low.
1. The FCC requires that the following label be prominently
displayed on an outside surface of the OEM's end product:
D. Terminate the call sequence and venfy the received data.
Unit contains Registered Protective Circuitry
which complies with Part 68 FCC Rules
SPECIAL INSTRUCTIONS TO USER
FCC Registration Number:
Your Rockwell Data Access Arrangement has been registered
with the Federal Communications Commission (FCC). To comply
with the FCC regulations you are requested to observe the
following:
Ringer Equivalence: .8B
2. The size of the label should be such that all the reqUired
information is legible without magnification.
1-95
RDAA
Rockwell Data Access Arrangement Module
SECTION 4
OPERATING INSTRUCTIONS
IDLE
•
AUTOMATIC ANSWER
r---
The connection of the data transmission path for automatic
answer is as described in paragraph 2.4. To disconnect the data
transmission path, just turn off OH and/or DA, as shown in
Figure 6.
I
CCT/- ON
I
I
RceT - OFF2
DETECT DIAL TONE 1
IDLE
+
r--
,.--
ROlON
I
I
ceT/- OFF3
·OH & RceT· ON
I
2-SECOND MINIMUM DELAY
I
R
CCT/- ON
A
A
OH PULSES FOR NO.
0
I
RceT - ON
I
I
I
DATA TRANSMISSION
I
OH & RCCT - OFF
·OH & RceT - OFF
I
CCT/- OFF
•
IDLE
E
DETECT ANSWER TONE 4
DATA TRANSMISSION
-
T
I
E
I
0
CC'r/- DN3
A
T
ANSWER TONE
I
R
A
0
I
0
~
OH & RCCT - ON
I
ceT/- OFF
-
'---
~
IDLE
*DA MAY BE ON PERMANENTLY FOR AUTOMATIC ANSWER.
NOTES.
1. DIAL TONE DETECTION IS NOT PROVIDED WITHIN THE RDAA.
ALTERNATIVELY, DTE MAY START FROM.,IDLE, TURN ON OH,
THEN TIME FOR 3 SECONDS TO ENSURE DIAL TONE PRESENT
AND PULSE OH FOR NUMBER,
2. DA MUST BE OFF DURING DIAL PULSING, DA MAY BE ON AT
ALL OTHER TIMES.
3. THE DA TO CCT RESPONSE TIME IS LESS THAN 1 MS.
4. ANSWER TONE DETECTION CIRCUITRY IS NOT PROVIDED
WITHIN THE RDAA.
Figure 6_ Automatic Answering Sequence
AUTOMATIC DIAL
Figure 7_
DIAL PULSE ORIGINATION
The DTE must provide the logic to turn ON the OH and DA
leads, detect dial tone (or time for 3 seconds to ensure dial tone
present), then turn OFF the DA lead and generate the dial
pulses corresponding to the called number (Figure 7). The
2-second delay period between OH and DA going ON and the
response of CCT going ON will not be invoked in the origination
mode. The DTE should monitor for call progress indication (dial
tone, busy tone, answer tone, and call intercept).
Dial Pulse Origination Sequence
face with Voiceband Ancillary and Data Equipment"
(PUB 47001).
The following is an example for pulse dialing the digit #2 through
the OH lead.
Requirements for proper call establishment exist on the pulse
repetition rate (8 to 11 pulses per second), off duty cycle
(60 percent nominal), interdigital delay timing (600 ms to
2 seconds) and chatter and spurious makes and breaks. The
RDAA off-hook relay is a Reed relay designed to long life. Be.ll
System requirements for pulse and touch-tone dialing are
described in their Communications reference "Electrical
Characteristics of Bell System Network Facilities at the Inter-
+SV/MAI
I
•
•
•
•
•
•
•
CTS
..
O
.'
::
SCOPE
I'
1....
TDCLK
EYEX
I
XTCLK
EYEY
TXD
I
RXD
h
RDCLK
TBCLK""
--
L---~f\ :r
EYE
PATTERN
EYESYNC . .IGENERATOR
~~~~~
RLSD
R208/201
MODEM
RBCLK
EYECLK
+12V
+5V
POWER
SUPPLY
GND
READ
-12V
WRITE
.....--4-+=D;:;,:A"'TA::..=BU::,;S:...;lO:
(18L-)_~ Di
TXA
I-_+A:::;D::.:D::.:R.:.:E:::S::::S~B:::U:.:S~;(c'4~) RSi
HOST
PROCESSOR
(DTE)
RXA
DECODER ' "
(P
CS
(2),
LINE
INTERFACE
CSi
POR
AUXIN
IRQ
(
+5
- ' 1vJV,,---,l
Figure 1.
R208/201 Functional Interconnect Diagram
2-5
TELEPHONE
LINE
Bell208A/B and Bell201C Modem
R208/201
R208/201 Hardware Circuits
Table 4.
Name
Type'
DIN
Pin No.
DIP'
Pin No.
Description
Name
A. OVERHEAD:
Ground (A)
Ground (D)
DIN
DIP'
Type' Pin No. Pin No.
AGND
DGND
+5 volts
PWR
+ 12 volts
-12 volts
POR
PWR
PWR
1I0B
31C,32C
30,31
Analog Ground Return
3C,8C, 29,37,53 Digital Ground Return
5A,10A
19C,23C, 1,45,61 + 5 volt supply
26C,30C
15A
32
+ 12 volt supply
12A
36
- 12 volt supply
13C
2
Power·on-reset
RDCLK
TDCLK
XTCLK
RTS
CTS
TXD
RXD
RLSD
OC
OC
IB
IB
OC
IB
OC
OC
21A
23A
22A
25A
25C
24C
22C
24A
23
46
51
50
49
48
26
27
Receive Data Clock
Transmit Data Clock
External Transmit Clock
Request-to-Send
Clear-to-Send
Transmitter Data
Receiver Data
Received Line Signal
Detector
22
47
Receiver Baud Clock
Transmitter Baud Clock
31A
32A
30A
34
33
Transmitter Analog Output
Receiver Analog Input
Auxiliary Analog Input
15C
14A
14C
13A
56
55
57
58
B. MICROPROCESSOR INTERFACE:
07
06
05
04
03
02
01
DO
I/OA
I/OA
I/OA
I/OA
1C
IA
2C
2A
3A
4C
4A
5C
3
4
5
6
7
8
9
10
RS3
RS2
RS1
RSO
IA
IA
IA
IA
6C
6A
7C
7A
16
17
18
19
CSO
IA
10C
20
CS1
IA
9C
21
CS2
IA
9A
13
12C
11A
11C
14
12
11
READ
WRITE
IRQ
Description
C. V.24 INTERFACE:
I/OA
1I0A
I/OA
1I0A
fA
IA
OB
D. ANCILLARY CIRCUITS:
}-'~{"'.,
RBCLK
TBCLK
OC
OC
26A
27C
E. ANALOG SIGNALS:
TXA
RXA
AUXIN
AA
AB
AC
-
F. DIAGNOSTIC:
}
Register Select
(4 Bits)
EYEX
EYEY
EYECLK
EYESYNC
Chip Select
Transmitter Device
Chip Select Receiver
Sample Rate Device
Chip Select Receiver
Baud Rate Device
Read Enable
Write Enable
Interrupt Request
Table 5.
OC
OC
OA
OA
Eye Pattern
Eye Pattern
Eye Pattern
Eye Pattern
Signal
Data-X Axis
Data-Y Axis
Clock
Synchronizing
Notes:
1. Refer to Table 5 for digital circuit Interface characteristics and
Table 7 for analog circuit interface characteristics.
2. Pins not used on the DIP Version: 15, 24, 25, 28, 35, 38, 39,
40, 41, 42,4~, 44, 52, 54, 59, 60
-
Digital Interface Characteristics
Input/Output Type
Symbol
Units
Parameter
IA
IB
IC
VIH
Input Voltage, High
V
2.0 Min.
2.0 Min.
2.0 Min.
V'l
VOH
Input Voltage, Low
V
0.8 Max
0.8 Max.
0.8 Max.
Output Voltage, High
V
VOL
Output Voltage, Low
lIN
Input Current, Leakage
p.A
OA
OB
2.4 MIn.1
V
0.4 Max. 2
Output Current, High
rnA
-0.1 Max.
Output Current, Low
rnA
1.6 Max.
IL
Output Current, Leakage
p.A
Ipu
Pull-up Current
(Short Circuit)
~A
Cl
Capacitive Load
pF
Co
Capacitive Drive
pF
1/0 B
2.0 Min.
5.25 Max.
2.0 Min.
0.8 Max.
0.8 Max.
2.4 Min.'
2.4 Min.3
0.4 Max. 2
0.4 Max.5
1.6 Max.
1.6 Max.
± 10 Max.
5
-240 Max.
-10 Min.
-240 Max.
-10 Min.
5
20
-240 Max.
-10 Min.
100
TTL
= -100 p.A
= 1.6 rnA
0.4 Max. 2
I/O A
±2.5 Max.'
IOH
1 I Load
2. I Load
0.4 Max. 2
±2.5 Max.
IOL
Circuit Type
OC
TTL
w/Pull-up
TTL
w/Pull-up
Notes
3. I Load = -40 ~A
4. VIN = 0.4 to 2.4 Vdc, Vee
2-6
TTL
100
100
10
40
100
100
Open-Drain Open-Drain
3-State
Open-Drain
w/Pull-up Transceiver w/Pull-up
5. I Load
= 5.25
-260 Max.
-100 Min.
Vdc
= 0.36 rnA
Bell208A/B and Bell201C Modem
R208/201
This configuration is suitable for performing high speed data
transfer using the serial data port. Individual features are discussed in subsequent paragraphs.
Received Line Signal Detector (RLSD)
For Be1l208A1B and CCITT V.27, RLSO turns on at the end of the
training sequence. If training is not detected at the receiver, the
RLSO off-to-on response time is 15 ± 10 ms. For Be1l201C, RLSO
turns on in 10 ± 5 ms after the detection of energy above threshold. The RLSO on-to-off response time for Bell 208A/B, CCITT
V.27 and Bell 201C is 10 ± 5 ms. Response times are measured
with a signal at least 3 dB above the actual RLSO on the threshold or at least 5 dB below the actual RLSO off threshold.
V.24 INTERFACE
Eight hardware circuits provide timing, data, and control signals for
implementing a serial interface compatible with CCITT Recommendation V.24. These signals interface directly with circuits using TTL
logic levels (OV, + 5V). These TTL levels are suitable for driVing the
short wire lengths or printed circuitry normally found within standalone modem enclosures or equipment cabinets. For driving longer
cables, the voltage levels and connector arrangement recommended by EIA standard RS-232-C are preferred.
The RLSO on-to-off response time ensures that all valid data bits
have appeared on RXO.
Four threshold options are provided:
The sequence of events leading to successful data transfer from
transmitter to receiver is:
1. Greater than - 43 dBm (RLSO on)
Less than - 49 dBm (RLSO off)
1. The transmitter is activated and a training sequence is sent.
2. The receiver detects channel energy above the prescribed
threshold level and synchronizes its operation to the
transmitter.
3. Oata transfer proceeds to the end of the message.
4. The transmitter turns off after insuring that all data has had
time to be recovered at the receiver output.
2. Greater than - 33 dBm (RLSO on)
Less than - 38 dBm (RLSO off)
3. Greater than - 26 dBm (RLSO on)
Less than - 31 dBm (RLSO off)
4. Greater than - 16 dBm (RLSO on)
Less than - 21 dBm (RLSO off)
NOTE
Transmitted Data (TXD)
Performance may be at a reduced level when the
received signal is less than - 43 dBm.
The modem obtains serial data from the local OTE on this input.
Received Data (RXD)
A minimum hysteresis action of 2 dB exists between the actual
off-to-on and on-to-off transition levels. The threshold level and
hysteresis action are measured with an unmodulated 2100 Hz
tone applied to the receiver's audio input (RXA).
The modem presents received data to the local OTE on this output.
Request To Send (RTS)
RTS ON allows the modem to transmit data on TXO when CTS
becomes active. The responses to RTS are shown in Table 6.
Transmit Data Clock (TDCLK)
Clear To Send (CTS)
The modem provides a Transmit Data Clock (TOCLK) output with
the following characteristics:
CTS ON indicates to the terminal equipment that the modem will
transmit any data which are present on TXO. CTS response times
from an ON condition of RTS are shown in Table 6.
1. Frequency. Selected data rate of 4800 or 2400 Hz (± 0.01 %).
2. Duty Cycle. 50 ± 1%.
The time between the on-to-off transition of RTS and the on-to-off
transition of CTS in data state is a maximum of 2 band times for
all configurations.
Table 6.
TOCLK is provided to the user in synchronous communications
for USRT timing. In this case Transmit Oata (TXO) must be stable
during the one P.s periods immediately preceding and following
the rising edge of TOCLK.
RTS-CTS Response Times
RT5-CTS Turn-On Time
Specification
Bell 20BA/B Long
Bell 208A1B Short
Bell 201C 26.4 ms Sync Seq
Bell 201C 148.3 ms Sync Seq
Bell 201C 220 ms Sync. Seq.
V.27 4800 Long
V.27 4800 Short
V.27 2400 Long
V.27 2400 Short
V.26A 2400 90 ms Sync. Seq.
V.26 1200 90 ms Sync. Seq
External Transmit Clock (XTCLK)
Echo Protector Echo Protector
Tone Disabled Tone Enabled'
150
50
26.4
148.3
220
708
50
943
67
90
90
In synchronous communication where the user needs to supply
the transmit data clock, the input XTCLK can be used. The clock
supplied at XTCLK must exhibit the same characteristics of
TOCLK. The XTCLK input is then reflected at TOCLK.
355
255
231.4
353.3
425
913
255
1148
272
295
295
Receive Data Clock (RDCLK)
The modem provides a Receive Oata Clock (ROCLI<) output in
the form of a 50 ± 1% duty cycle squarewave. The low-to-high
transitions ofthis output coincide with the center of received data
bits. ROCLK is provided to the user in synchronous communications for USRTtiming. The timing recovery circuit is capable of
tracking a ± .01 % frequency error in the associated transmit timing source.
• For short echo protector tone, subtract 155 ms from RTS·CTS
turn·on time.
2-7
R208/201
Bell 208A/B and Bell 201C Modem
MICROPROCESSOR INTERFACE
overcome the leakage currents). The resistor value should be
large enough to limit the driver sink current to a level acceptable
to each driver. For the case where only the modem IRQ driver is
used, a resistor value of 5.6K ohms ± 20%, 0.25 watt, is
sufficient.
Eight hardware circuits provide address, data, control, and interrupt signals for Implementing a parallel interface compatible with
an 8080 microprocessor. With the addition of a few external logic
gates, the interface can be made compatible with a wide variety
of microprocessors such as 6500, 6800, or 68000.
The microprocessor interface allows a host microprocessor to
change modem configuration, read or write channel data as well
as diagnostic data, and supervise modem operation by means of
soft strappable control bits and modem status bits. The significance of the control and status bits and methods of data interchange are discussed in a later section devoted to software circuits. This section describes the operation of the interface from a
hardware standpoint.
ANALOG SIGNALS
The analog signal characteristics are described in Table 7.
Table 7. Analog Interface Characteristics
Chip Select (CSO-CS2) and
Register Selects (RSO-RS3)
The signal processor to be accessed is selected by grounding
one of three unique chip select lines, CS2, CS1 or CSO. T~e
selected chip decodes the four address lines, RS3 through RSO,
to select one of sixteen internal registers. The most significant
address bit (~) is RS3 while the least significant address bit (20)
is RSO. Once the address bits have been decoded, the selected
register can be read from or written into via an 8-bit parallel data
bus, D7 through DO. The most significant data bit (27) is D7while
the least significant data bit (20) is DO.
Name
Type
TXA
AA
The transmitter output IS S04 ohms ± 1%.
Characteristics
RXA
AB
The receiver input impedance IS 60K ohms
±23%.
AUXIN
AC
The auxiliary analog input allows access to the
transmitter for the purpose of interfacing With
user provided equipment. Because this is a
sampled data Input, any signal above 4800 Hz
will cause aliasing errors. The Input impedance
Is 1K ohms, and the gain to transmitter output is
the TLVL setting + O.S dB - 1.4 dB.
Transmitter Analog (TXA)
The TXA line is an output suitable for driving an audio transformer or data access arrangement for connection to either
leased lines or the public switched telephone network. The output structure of TXA is a low impedance amplifier in series with
an internal 604 ohm ± 1% resistor to match a standard telephone load of 600 ohms.
Read Enable (READ) and
Write Enable (WRITE)
Reading or writing is activated by pulsing either the READ line
high or the WRITE line low. During a read cycle, data from the
selected register is gated onto the data bus by means of threestate drivers. These drivers force the data lines high for a one bit
or low for a zero bit. When not being read, the three-state drivers
assume their off, high-impedance, state. During a write cycle,
data from the data bus is copied into the selected register, with
high and low bus levels representing one bits and zero bits,
respectively. The timing required for correct read/write cycles ~
illustrated in Figure 2. Logic necessary to convert the single R/W
output from a 65)0( series microprocessor to the separate READ.
and WRITE signals required by the modem is shown in Figure 3.
Receiver Analog (RXA)
RXA is an input to the receiver from an audio transformer or
data access arrangement. The input impedance is nominally
60K ohms but a factory select resistor allows a variance of 23%.
The RXA input must be shunted by an external resistor in order to
match a 600 ohm source. A 604 ohm ± 1% resistor is
satisfactory.
Some form of transient protection for TXA and RXA is recommended when operating directly into a transformer. This protection may take the form of back-to-back zener diodes across the
transformer or a 'varistor across the transformer.
Interrupt Request (IRQ)
The final signal on the microprocessor interface is Interrupt
Request (IRQ). This signal may be connected to the host microprocessor interrupt request input in order to interrupt host program execution for modem service. The use of IRQ is optional
and the method of software implementation is described in a
subsequent section, Software Circuits. The IRQ output structure
IS an open-drain field-effect-transistor (FET). This form of output
allows IRQ to be connected in parallel to other sources of interrupt. Any of these sources can drive the host interrupt input low,
and the interrupt servicing process continues until all interrupts
have been cleared and all IRQ sources have returned to their
high impedance state. Because of the open-drain structure of
IRQ, an external pull-up resistor to +5 volts is required at some
pOint on the IRQ.line. The resistor value should be small enough
to pull the IRQ line high when all IRQ drivers are off (i.e., it must
Auxiliary Input (AUXIN)
AUXIN provides a means of inserting audio signals into the
modem output stage. Because this input IS summed With the
transmitter output prior to the transmitter low pass filter and compromise equalizers, the AUXIN signal is sampled by a compensated sample-and-hold circuit at a rate of 9600 samples-persecond. Any signal above 4800 Hz on the AUXIN line Will be
aliased back into the passband as nOise. The input Impedance of
AUXIN is 1K ohm. The gain from AUXIN to TXA IS the same as
the selected transmit level + 0.6 dB - 1.4 dB. AUXIN must be
g rounded if not used.
2-8
R208/201
Bell208A/B and Bell201C Modem
WRITE
READ
CSi
(i
= 0,1)
RSi
(i
= 0-3)
READ
Di
(i
= 0-7)
Characteristic
Symbol
Min
TCS
30
TDA
-
TDH
10
TCH
TWDS
TWDH
TWR
10
75
10
75
CSI, RSI setup time prior
to Read or Write
Data access time after Read
Data hold time after Read
CSI, RSi hold time after
Read or Write
Write data setup time
Write data hold time
Write strobe pulse width
Figure 2.
Max
Units
-
ns
ns
ns
140
50
-
-
ns
ns
ns
ns
Microprocessor Interface Timing Diagram
$2
12C
READ
R208/201
MODEM
llA
RiW
Figure 3.
WRITE
R/W to READ WRITE Conversion Logic
2-9
Bell208A/B and Bell201C Modem
R208/201
or RS-232 recommendations since they mark the baud interval
for the transmitter and receiver rather than the data rate. The
baud clocks can be useful in identifying the order of data bits in a
baud (e.g., for multiplexing data, etc.). Both signals are high
active, meaning the baud boundaries occur on falling edges. The
first bit in each baud begins with the falling edge of the corresponding baud clock.
DIAGNOSTIC SIGNALS
EYEX, EYEY, EYECLK, and EYESYNC
Four card edge connections provide the timing and data necessary to create an oscilloscope quadrature eye pattern. The eye
pattern is simply a display of the received baseband constellation. By mOnitoring this constellation, an observer can often identify common line disturbances as well as defects in the modulation!
demodulation process.
SOFTWARE CIRCUITS
The outputs EYEX and EYEY provide two serial bit streams containing data for display on the oscilloscope X axis and Y axis,
respectively. Since this data is in serial digital form it must first be
converted to parallel digital form by two serial-to-parallel converters and then to analog form by two D!A converters. A clock
for use by the serial-to-parallel converters is furnished by signal
EYECLK. A strobe for loading the D!A converters is furnished by
signal EYESYNC. Timing of these signals is illustrated in Figure 4. The EYEX and EYEY outputs furnish 9-bit serial words.
Since most serial to parallel conversion logic is designed for a-bit
words, an extra storage flip-flop is required for 9-bit resolution.
However, the ninth bit is not generally needed for eyepattern generation, and eight-bit hardware can be used if data is copied on
the rising edge of EYECLK rather than the falling edge.
Operation of the microprocessor interface circuits was described
in the hardware section from the standpoint of timing and load!
drive characteristics. In this section, operation of the microprocessor interface is described from a software standpoint.
The modem is implemented in firmware running on three special
purpose signal processors. These signal processors share the
computing load by performing tasks that are divided into areas.
These areas are partitioned into transmitter, baud rate, and sample rate devices.
INTERFACE MEMORY
Each signal processor can communicate with the host processor
by means of a specialized, dual-port, scratch-pad memory called
interface memory. A set of sixteen a-bit registers, labeled register 0 through register F, can be read from or written into by either
the host processor or signal processor. The host communicates
via the microprocessor interface lines shared between the two
signal processors. The signal processor communicates via its
internal I/O bus. Information transfer from SP RAM to interface
memory is accomplished by the signal processor logic unit moving data between the SP main bus and the SP I/O bus. Two olthe
16 addressable interface memory registers (i.e., register 0 and
register E) have unique hardware connections to the interrupt
logic. It is possible to enable a bit in register E to cause an interrupt each time it sets. This interrupt can then be cleared by a read
or write cycle from the host processor to register O. This operation is discussed in detail later in this section.
ANCILLARY SIGNALS
Transmitter Baud Clock (TBCLK) and
Receiver Baud Clock (RBCLK)
Two clock signals called TBCLK and RBCLK are provided at the
modem connector. These signals have no counterpart in the V.24
EYESYNC
Memory maps of the 48 addressable registers in the modem are
shown in Figure 5. These registers may be read or written on any
host read or write cycle, but all eight bits of that register are
affected. In order to read asingle bit or a group of bits in a register,
the host processor must mask out unwanted data. When writing
a single bit or group of bits in a register the host processor must
perform a read-modify-write operation. That is, the entire register
is read, the necessary bits are set or reset in the accumulator of
the host, then the original unmodified bits and the modified bits
are written back into the register of the interface memory.
EYEX,
EYEY
lSB
MSB
Figure 4.
Table 8 defines the individual bits in the interface memory. In the
Table 8 descriptions, bits in the interface memory are referred to
using the format Y:Z:Q. The chip number is specified by Y (0 or
1), the register number by Z (0 through F), and the bit number by
Q (0 through 7, with 0 = LSB).
Eye Pattern Timing
2-10
Bell208A/B and Bell201C Modem
R208/201
Transmitter Interface Memory Chip 0 (CSO)
~
7
6
5
E
TIA
-
-
-
0
-
-
-
-
-
C
-
-
-
-
-
-
-
9
-
B
-
1
0
TIE
-
TBA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
2
3
Register
F
B
A
7
RAM ACCESS T
RTS
TSB
-
-
-
-
-
-
-
-
-
-
-
-
EPT
TPDM
XCEN
SEPT
A3L
D3L
TTDIS
SOlS
MHLD
-
TRANSMITTER CONFIGURATION
6
-
-
5
4
CEO
LJACT L4ACT
LAEN
L4HG
LDEN
TLVL
3
L2ACT LCEN
FREOM
2
FREOL
1
RAM DATA YTM
0
RAM DATA YTL, TRANSMITTER DATA, DDR
/::
7
5
6
4
2
3
0
1
Bit
(-) Indicates reserved for modem use only.
Receiver Interface Memory Chip 1 (CS1)
~
7
5
6
4
3
2
Receiver Interface Memory Chip 2 (CS2)
I~
0
1
7
6
5
4
3
2
1
0
Register
Register
F
SOH
-
-
-
E
RSIA
-
-
-
-
-
-
F
-
-
-
-
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
-
C
-
-
-
-
-
-
-
-
C
-
-
-
-
-
-
-
-
B
-
PNDET
-
-
-
-
-
A
-
-
9
-
B
-
7
-
-
-
-
FED
-
-
-
-
-
RTH
IFIX
6
DO IS
TOO
RSB
RSIE
-
RSDA
USMD TONE
-
P2DET
RPDM SWRT BWRT
E
RBIA
B
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
9
-
-
-
-
-
-
-
-
-
-
B
-
-
-
-
-
-
-
7
-
-
-
-
-
-
6
-
-
-
-
-
-
-
2
1
0
T2
RTDIS
RECEIVER CONFIGURATION
RAM ACCESS XS
5
RAM ACCESS XB
RAM ACCESS YS
4
RAM ACCESS YB
3
RAM DATA XSM
3
RAM DATA XBM
2
RAM DATA XSL
2
RAM DATA XBL
1
RAM DATA YSM
1
RAM DATA YBM
0
RAM DATA YSL, RECEIVER DATA
0
RAM DATA YBL
7
6
5
4
3
2
RBDA
A
4
1
~
0
7
6
5
4
3
Bit
Bit
(
-
-
CDET
5
/::
RBIE
) Indicates reserved for modem use only.
Figure 5,
( ) Indicates reserved for modem use only.
Interface Memory Map
2-11
-
-
Bell 208A/B and Bell 201 C Modem
R208/201
Table S.
Mnemonic
Name
R20S/201 Interface Memorv Definitions
Memory
Location
I
Description
Amplitude 3·Link
Select
0:5:1
BWRT
Baud Write
1 :7:2
When control bit BWRT is a one, the RAM write operation is enabled for Chip 2.
CEO
Cable Equalizer
Field
0:5:(4.5)
The CEO Control field simultaneously controls amplitude compromise equalizers In both
the transmit and receive paths. The following tables list the possible cable equalizer
selection codes and responses.
A3L
A3L is used in conjunction with LAEN. When A3L is a one the Japanese 3 link
equalizer is selected and when A3L is a zero the U.S. Survey Long link equalizer
selected.
CEQ
Cable Length (0.4 mm diameter)
0
1
0.0
1.8 km
3.6 km
7.2 km
2
3
IS
Cable Equalizer Nominal Gain
CEQ CODE 1
Gain Relative to 1700 Hz (dB)
Frequency
(Hz)
Transmitter
Receiver
700
1500
2000
3000
-0.99
-0.20
+0.15
+ 1.43
-0.94
-0.24
+0.31
+ 1.49
CEQ CODE 2
I
Gain Relative to 1700 Hz (dBI
Frequency
(Hz)
Transmitter
Receiver
700
1500
2000
3000
-2.39
-0.65
+0.87
+3.06
-2.67
-0.74
+ 1.02
+3.17
CEQ CODE 3
I
Gain Relative to 1700 Hz (dB)
Frequency
(Hz)
Transmitter
Receiver
700
1500
2000
3000
-3.93
-1.22
+1.90
+4.58
-3.98
-1.20
+1.81
+4.38
~
Unless a problem with training or high bit error rate is encountered, most applications
operate successfully with no cable equalizer selected.
CDET
Carner Detector
l:B:O
When zero, status bit CDET indicates that passband energy is being detected, and
that a training sequence is not in process. CDET goes to a zero at the start of the
data state, and returns to a one at the end of the received signal. CDET activates
up to 1 baud time before RLSD and deactivates within 2 baud times after RLSD. If the
FED bit goes to a zero and no P2 sequence is detected, the CDET bit goes to zero
within 5 to 25 ms indicating that the receiver has entered the data state Without a
training sequence.
DO IS
Descramble Disable
1 :7:5
When control bit DDIS is a one, the receiver descrambler Circuit is removed from the
data path.
DDR
Dial Digit Register
0:0:0-7
DDR is used to tell the modem which DTMF digit to transmit (see Transmitter Data).
D3L
Delay 3-Link Select
0:5:0
D3L is used in conjunction with LDEN. When D3L is a one the Japanese 3 link
equalizer is selected and when D3L is a zero the U.S. Survey Long link equalizer is selected.
-2-12
I
Bell208A/B and Bell201C Modem
R208/201
Table S.
Mnemonic
Name
R20S/201 Interface Memory Definitions (Continued)
Memory
Location
Description
EPT
Echo Protector
Tone
0'7 3
When control bit EPT is a one, an unmodulated carner IS transmitted for 185 ms
(optionally 30 ms) followed by 20 ms of no transmitted energy at the start of transmission.
FED
Fast Energy
Detector
1 9 6
When status bit FED IS a zero, It indicates that energy above the receiver threshold is
present In the passband, and the receiver is searching for the training sequence.
(None)
FREOUFREOM
0'2:0-7,
0'3 0-7
The host processor conveys tone generation data to the transmitter by writing a 16-blt
data word to the FREOL and FREOM registers In the interface memory space, as
shown below:
FREQM Register (0:3)
Bit:
Data Word:
I
I
7
2 '5
I
I
6
2'4
I
I
I
I
5
2 '3
4
2'2
I
I
3
2"
I
I
2
2'°
I
I
1
29
I
I
0
28
FREQL Register (0: 2)
Bit:
Data Word:
I
I
7
27
I
I
6
26
I
I
I
I
5
25
4
24
I
I
3
23
I
I
2
22
I
I
1
2'
I
I
0
2°
The frequency number (N) determines the frequency (F) as follows:
F = (0.146486) (N) Hz ±0.01%
Hexadecimal frequency numbers (FREOL, FREOM) for commonly generated tones are
given below:
FREQM
FREQL
Frequency (Hz)
OC
10
2C
31
38
52
55
00
55
00
462
1100
1650
1850
2100
IFIX
Eye Fix
1 :6:7
When control bit IFIX is a one, the senal data on EYEX and EYEY reflect the rotated
equalizer output and do not follow the data selected by RAM ACCESS XB and RAM
ACCESS VB.
LAEN
Link Amplitude
Equalizer Enable
0:5:3
The link amplitude equalizer enable and select bits control an amplitude compromise
equalizer In the receive path according to the follOWing table:
LAEN
A3L
Curve Matched
0
1
1
X
0
1
No Equalizer
U.S. Survey Long
Japanese 3-Llnk
The link amplitude equalizer responses are given In the following table.
Link Amplitude Equalizer
Frequency
(Hz)
1000
1400
2000
2400
2800
3000
Gain Relative to 1700 Hz (dB)
U.S. Survey Long
-0.27
-0.16
+0.33
+1.54
+5.98
+8.65
2-13
Japanese 3-Link
-0.13
-008
+016
+0.73
+2.61
+3.43
~I
Bell208A/B and Bell201C Modem
R208/201
Table S.
Mnemonic
Name
R20S/201 Interface Memory Definitions (Continued)
Memory
Location
Description
LCEN
Loop Clock Enable
0:4:0
When control bit LCEN is a one, the transmItter clock tracks the receIver clock
LDEN
Link Delay
Equalizer Enable
0:5:2
The link delay equalizer enable and select bits control a delay compromise equalizer
the receive path according to the follOWing table:
LDEN
D3L
Curve Matched
o
X
1
1
1
No Equalizer
U.S. Survey Long
Japanese 3-Link
o
In
The link delay equalizer responses are given in the following table.
Link Delay Equalizer
Delay Relative to
1700 Hz (Microseconds)
Frequency
(Hz)
U.S. Survey Long
Japanese 3-Link
800
1200
1600
1700
2000
2400
2800
-498.1
-188.3
-15.1
+0.0
-39.8
-423.1
-672.4
-653.1
-398.5
-30.0
+0.0
+11.7
-117.1
-546.3
L2ACT
Remote Digital
Loopback ActIvate
0:4:1
When control bit L2ACT IS a one, the receiver digital output is connected to the
transmitter digital input in accordance with CCITT recommendation V.54 loop 2.
L3ACT
Local Analog
Loopback Activate
0:4:7
When control bit L3ACT is a one, the transmitter analog output IS coupled to the
receiver analog input through an attenuator in accordance with CCITT recommendation
V.54 loop 3.
L4ACT
Remote Analog
Loopback Activate
0:4:6
When control bit L4ACT is a one, the receiver analog Input IS connected to the transmitter
analog output through a vanable gain amplifier in a manner similar to recommendation
V.54 loop 4.
L4HG
Loop 4 High Gain
0:4:5
When control bit L4HG is a one, the loop 4 variable gain amplifier is set for + 16 dB,
and when at zero the gain is zero dB.
MHLD
Mark Hold
0:7:4
When control bit MHLD is a one, the transmItter input data stream is forced to all marks
(ones).
PNDET
Period N Detector
1 :B:6
When status bit PNDET is a zero, it indicates a PN sequence has been detected. This
bit sets to a one at the end of the PN sequence.
P2DET
Period Two
Detector
1 :8:2
When status bIt P2DET is a zero, it indicates that a P2 sequence has been detected.
ThIs bit sets to a one at the start of the PN sequence.
(None)
RAM Access T
O:F:0-7
Contains the RAM access code used in reading or writing chIp 0 RAM locatIons via
word Y (0:1 and 0:0).
(None)
RAM Access XB
2:5:0-7
Contains the RAM access code used in reading or writing chIp 2 RAM locatIons via
word X (2:3 and 2:2).
(None)
RAM Access XS
1 :5:0-7
Contains the RAM access code used In reading or writing chIp 1 RAM 10caIIOns vIa
word X (1:3 and 1 :2).
(None)
RAM Access YB
2:4:0-7
Contains the RAM access code used in reading or wntlng chIp 2 RAM locatIons vIa
word Y (2: 1 and 2:0).
2-14
Bell208A/B and Bell201C Modem
R208/201
Table S.
Mnemonic
Name
R20S/201 Interface Memory Definitions (Continued)
Memory
Location
Description
(None)
RAM Access YS
1 40-7
Conlams the RAM access code used
word Y (1 1 and 1'0)
(None)
RAM Data XBL
2 2'0-7
Least significant byte of 16·blt word X used
10
reading or writing RAM locations In chip 2
(None)
RAM Data XBM
2 3 0-7
Most significant byte of 16·bIt word X used
10
reading or wrltmg RAM locations
In
chip 2
(None)
RAM Data XSL
1'2 0-7
Least significant byte of 16·bit word X used
10
readmg or writing RAM locations
10
chip 1
(None)
RAM Data XSM
1 :3.0-7
Most significant byte of 16·bIt word X used in reading or writing RAM locations
10
chip 1
(None)
RAM Data YBL
20 0-7
Least significant byte of 16·blt word Y used In readmg or writing RAM locations
10
chip 2
(None)
RAM Data YBM
2:1.0-7
Most significant byte of 16·blt word Y used
(None)
RAM Data YSL
1.0.0-7
Least significant byte of 16·blt word Y used in readmg or writing RAM locations In
chip 1. Shared by parallel data mode for presenting channel data to the host
microprocessor bus. See 'Receiver Data'
(None)
RAM Data YSM
1'1.0-7
Most significant byte of 16·bit word Y used
(None)
RAM Data YTL
0:0:0-7
Least significant byte of 16·bit word Y used in reading or wrltmg RAM locations 10
chip O. It is shared by parallel data mode and DTMF dialing (see Transmitter Data)
(None)
RAM Data YTM
0:1 :0-7
Most Significant byte of 16·byte word Y used
RBDA
Receiver Baud
Data Available
2'E:0
Status bit RBDA goes to a one when the receiver writes data Into register 2: O. The bit goes
to a zero when the host processor reads data from register 2' O.
RBIA
Receiver Baud
Interrupt Active
2'E:7
This status bit IS a one whenever the receiver baud rate device IS driving IRQ low In
Idle mode the mterrupts from chip 2 occur at half the baud rate. During diagnostic access
in data mode, the mterrupts occur at the baud rate.
RBIE
Receiver Baud
Interrupt Enable
2:E.2
When the host processor writes a one in the RBIE control bit, the IRQ line of the
hardware interface IS driven to zero when status bit RBDA IS a one.
(None)
Receiver
Configuration
1'6.0-5
The host processor configures the receiver by writing a control code IOta the receiver
configuration field in the interlace memory space (see RSB).
10
readmg or wrltmg chip 1 RAM locations via
10
10
readmg or writing RAM locations In chip 2.
readmg or writing RAM locations
10
readmg or writing locations
In
10
chip 1.
chip 0
ReceIver ConfIguratIon Control Codes
Control codes for the modem receiver configuration are:
Configuration Code (Hex)
Receiver Configuration
18
16
12
34
30
35
31
14
10
26
22
25
21
06
02
05
01
15
11
08
Bell 208/201 Auto. Configuration'
Beli 208NB HDX
Beli 208NB FDX
Beli 201 C HDX 26.4 ms Sync. Seq.
Bell 201 C FDX 26.4 ms Sync. Seq
Beli 201C HDX 148.3 ms Sync. Seq.
Beli 201C FDX 1483 ms Sync Seq
Beli 201 C HDX 220 ms Sync Seq.
Beli 201 C FDX 220 ms Sync. Seq
V 27 4800 HDX Long
V.27 4800 FDX Long
V.27 2400 HDX Long
V.27 2400 FDX Long
V.27 4800 HDX Short
V.27 4800 FDX Short
V.27 2400 HDX Short
V.27 2400 FDX Short
V.26A 2400 FOX 90 ms Sync. Seq.
V 26 1200 FDX 90 ms Sync Seq
Tone Detector
'When this configuration IS selected, the receiver will detect a Beli 208 or 201 C handshake
and configure itself accordingly.
2·15
Bell 208A/B and Bell 201C Modem
R208/201
Table S.
Mnemonic
Name
R20S/201 Interface Memory Definitions (Continued)
Memory
location
Description
(None)
Receiver Data
1 :0:0-7
The host processor obtains channel data from the receiver In the parallel data mode
by reading a data byte from the receiver data register. The data is divided on baud
boundaries as is the transmitter data. When using receiver parallel data mode, the
registers 1:3 through 1'0 can not be used for reading the chip 1 RAM.
RPDM
Receiver Parallel
Data Mode
1'7:4
When control bit RPDM is a one, the receiver supplies channel data to the receiver data
register (1 : 0) as well as to the hardware serial data output. (See Receiver Data)
RSB
Receiver Setup Bit
1 :E:3
When the host processor changes the receiver configuration or the RTH field, the host
processor must write a one in the RSB control bit. RSB goes to zero when the changes
become effective. Worst case setup time IS 2 baud times.
RSDA
Receiver Sample
Data Available
1 :E:O
Status bit RSDA goes to a one when the receiver writes data to register 1 : O. RSDA
goes to a zero when the host processor reads data from register 1 : O.
RSIA
Receiver Sample
Interrupt Active
1 :E:7
This status bit is a one whenever the receiver sample rate device IS driving IRO to zero.
RSIE
Receiver Sample
Interrupt Enable
1 :E:2
When the host processor writes a one in the RSIE control bit, the IRO line of the
hardware interface is driven to zero when status bit RSDA is a one.
RTDIS
Receiver Training
Disable
1 :7:0
When control bit RTDIS is a one, the receiver is prevented from recognizing a training
sequence and entering the training state.
RTH
Receiver Threshold
Field
1 :7:6,7
The receiver energy detector threshold is set by the RTH field according to the following
codes (see RSB):
RlSD On
RTH
> -43
> -33
> -26
> -16
0
1
2
3
dBm
dBm
dBm
dBm
RlSD Off
< -48 dBm
< -38 dBm
< -31 dBm
< -21 dBm
RTS
Request-to-Send
0:7:7
When control bit RTS goes to a one, the modem begins a transmit sequence. It
continues to transmit until RTS is reset to zero, and the turn-off sequence has been
completed. ThiS input bit parallels the operation of the hardware RTS control input.
These inputs are ORed by the modem.
SOlS
Scrambler Disable
0:7:5
When control bit SOlS is a one, the transmitter scrambler circuit is removed from the
data path.
SEPT
0:7:0
When control bit SEPT is a one, the echo protector tone is 30 ms long rather than 185 ms
SOH
Short Echo
Protector Tone
Receiver Squelch
1 :F:7
When control bit SOH is set to a one, the receiver is squelched, RlSD is turned off and
RXD is clamped to all marks. SOH only affects the receiver operation when a half
duplex receiver configuration has been selected.
SWRT
Sample Write
1 :7:3
When control bit SWRT is a one, the RAM write operation is enabled for chip 1.
TBA
Transmitter Buffer
Available
O:E:O
ThiS status bit resets to zero when the host processor writes data to transmitter data
register 0: O. When the transmitter empties register 0: 0, thiS bit sets to a one. DUring a
RAM access in chip 0, when TBA IS a one the host can perform either a RAM read or
write depending on the state of bit 0:6:3 (see Transmitter ConfigurallOn).
TIA
Transmitter
Interrupt Active
O:E'7
This status bit IS a one whenever the transmitter IS driving IRQ to a zero
TIE
Transmitter
Interrupt Enable
0:E'2
When the host processor writes a one In control bit TIE, the IRQ line of the hardware
Interface is driven to zero when status bit TBA IS at a one.
2-16
Bell208A/B and Bell201C Modem
R208/201
Table S.
Mnemonic
TLVL
Name
Transmitter Level
Field
R20S/201 Interface Memory Definitions (Continued)
Memory
Location
o4
2-4
Description
The transmitter analog output level IS determmed by eight TLVL codes, as follows
TLVL
o
1
2
3
Transmitter Analog Output'
-1
-3
-5
-7
dBm
dBm
dBm
dBm
±1
±1
±1
±1
dB
dB
dB
dB
TLVL
Transmitter Analog Output'
4
5
6
- 9
-11
-13
-15
7
dBm
dBm
dBm
dBm
±1
±1
±1
±1
dB
dB
dB
dB
'Each step above IS a 2 dB change ± 0.2 dB
TOO
Tram-an-Data
1'6:6
When control bit TOO is a one, It enables the train-an-data algonthm to converge the
equalizer If the signal quality degrades sufficiently. When TOO IS a one, the modem stili
recognizes a tramlng sequence and enters the force tram state A BER of approximately
10- 3 for 05 seconds mitlates tram-an-date.
TONE
Tone Detect
1'9'2
TONE mdlcates with a zero the presence of energy In the 345-650 ± 10 Hz frequency
range. For call progress purposes, the user may determine which tone IS present by
determmlng the duty cycle of the TONE bit.
TPDM
Transmiller Parallel
Data Mode
0'7'2
When control bit TPDM IS a one, the transmitter accepts data for transmission from the
transmitter data register (0: 0). When TPDM IS a zero channel data from the senal hardware
Input TXD IS accepted and the chip 0 RAM access IS enabled.
(None)
Transmitter
Configuration'
0'6:0-7
The host processor configures the transmitter by writing a control byte Into the transmitter
configuration register In ItS Interface memory space. (See TSB )
Transmitter Configuration Control Codes
Control codes for the modem transmitter configurations are:
Configuration Code (Hex)'
Configuration
32
12
30
31
10
22
02
21
01
15
11
80
08
Bell 208A1B Long
Bell 208A1B Short
Bell 201C 26.4 ms Sync Seq.
Bell 201C 148.3 ms Sync Seq.
Bell 201C 220 ms Sync. Seq
V.27 4800 Long
V.27 4800 Short
V.27 2400 Long
V.27 2400 Short
V.26 2400 90 ms Sync Seq
V.26 120090 ms Sync. Seq.
Tone Transmit
DTMF Tone Transmit
'Note:
B" 3 of the transmitter configuralion register IS used in the RAM access operation for
chip 0 When 0: 6.3 IS a one, a RAM wnte operation will occur when TPDM IS a zero,
and when 0: 6.3 IS a zero, a RAM read operalion will occur when TPDM IS a zero
Configuration Definitions
Defmitlons of the eight Transmitter Configurations are:
1. Bell 208. When any of the Bell 208 conflguralions are selected, the modem operates
as specified in the Bell 208A1B Standard.
2. Bell 201C. When any of Bell 201 C configuralions are selected, the modem operates
as specified in the Bell 201C Standard.
3. V.27. When any of the V.27 configurations are selected, the modem operates as
specified 10 CCITT Recommendation V.27 ter.
4 V.26. When any of the V.26 configurations are selected, the modem operates as
specified 10 CCITT Recommendation V.26.
5 Tone Transmit. In this conflguralion, activating signal RTS causes the modem to
transmit a tone at a smgle frequency specified by two registers 10 the host interface
memory space containing the frequency code. The most significant bits are specified
in the FREOM register (0' 3). The least significant bits are specified in the FREOL
register (0:2). The least significant bit represents 0 146486 Hz ±O 01%. The frequency
generated IS: f =0.146486 (256 FREOM + FREOL) Hz ±O 01%.
6. DTMF Tone Transmit. In this conflguralion, activating signal RTS causes the modem
to transmit a Dual Tone Multi-Frequency (DTMF) tone specified by the code loaded
10 the Dial Digit Register (DDR, 0'0). The twelve codes, their associated dial digits
and tone pairs are as follows:
~~_ _ ~~~~~~___ ~~~~-L___~___~~~~~~~~~~~~~~~~~~~~_ _~~
2-17
I
fI
R208/201
Bell 208A/B and Bell 201 C Modem
Table S.
Name
Mnemonic
R20S/201 Interface Memory Definitions (Continued)
Memory
Location
Description
Dial Digit Register (DDR)
Hexadecimal Code
Tone Pair
(Hz)
Dial Digit
00
01
02
03
04
05
06
07
08
09
OA
OB
941
697
697
697
770
770
770
852
852
852
941
941
0
1
2
3
4
5
6
7
8
9
*#
1336
1209
1336
1477
1209
1336
1477
1209
1336
1477
1209
1477
Figure 6 shows the utilization of the DTMF Tone Transmit conflgurallon in an auto
dialing application.
(None)
Transmiller; DDR;
RAM Data YTL
0:0:0-7
1. The host processor transmits data In the parallel mode by writing a data byte to the
transmiller data register. The data IS divided on baud boundaries, as follows:
NOTE
Data is transmitted bit zero firSt.
Bits
I
Configuration
7
Bell 208A1B
V.274800
Not Used
BeIl201C,V26,
V.272400
6
Baud 3
Baud 0
Baud 1
Baud 2
I
Baud 1
I
Baud 0
2. Register 0: 0 is used to transmit DTMF digits when the transmiller is configured In
the DTMF tone transmit mode.
3. Register 0: 0 is a RAM data register used for reading or writing the least significant
byte of the 16-bit Y word in Chip 0 when TPDM is a zero and no tone or DTMF tone
transmission IS occurring.
TSB
Transmitter Setup
Bit
0:E:3
When the host processor changes the transmitter configuration, the host must write a
one in thiS control bit. TSB goes to a zero when the change becomes effective Worst
case setup time is 2 baud + turnoff sequence + training (If applicable).
TTDIS
Transmiller Train
Disable
0:7:6
When control bit TTDIS is a one, the transmitter does not generate a training sequence
at the start of transmission. With training disabled, RTS/CTS delay IS less than two
baud times.
T2
T/2 Equalizer
1 :7: 1
When control bit T2 is a one, an adaptive equalizer with two taps per baud IS used
When T2 is a zero, the equalizer has one tap per baud. The total number of taps
remains the same for both cases.
Select
USMD
Unscrambled Mark
Detection
1 :9:3
When status bit USMD IS a one, unscrambled mark as defined by Bell 201C has been
detected. The response time is 5 ms.
XCEN
External Clock
Enable
0:7: 1
When control bit XCEN IS a zero, the transmitter timing is established by the external
clock supplied at the hardware Input XTCLK, pin 22A. The clock appearing at the
XTCLK Input Will appear at the TDCLK output.
2-18
Bell208A/B and Bell201C Modem
R208/201
to zero when the host processor writes into register 2:0 and sets
to a one when the SP logic unit reads data from register 2:0.
SIGNAL PROCESSOR RAM ACCESS
RAM and Data Organization
When reading from RAM, or writing into RAM, the bits in registers O:E, 1:E, 2:E can be used for handshakmg or interrupt functions as in parallel data mode. When not in parallel data mode,
the bits in register I:E perform the handshake and interrupt functions for RAM access. In both serial and parallel data modes, the
bits in register 2:E perform handshake and interrupt functions for
RAM access. When set to one, bit RBIE (2:E:2) enables RBDA to
drive the IRQ connector signal to zero volts when RBDA is a one.
Bit RBIA (2:E:7) identifies chip 2, the baud rate device, as a
source of IRQ interrupt. Bit RBIA is a one when both RBIE and
RBDA are set to one. In the event that other system elements may
cause IRQ to be driven low, the host must determine if modem
chip 2 IS causing an interrupt by reading RBIA.
Each signa! processor contains 128 words of random access
memory (RAM). Each word is 32 bits wide. Because the signal
processor is optimized for performmg complex arithmetic, the
RAM words are frequently used for storing complex numbers.
Therefore, each word IS organized into a real part (16 bits) and an
imaginary part (16 bits) that can be accessed mdependently.
The portion of the word that normally holds the real value is
referred to as XRAM. The portion that normally holds the imaginary value is referred to as YRAM. In the sample rate and baud
rate devices the entire contents of XRAM and YRAM may be read
from or written into by the host processor via the microprocessor
interface. Access to the YRAM is possible only in the transmitter
device.
Table 9 provides the available RAM access functions, codes, and
registers.
Interface Memory
Auto Dial Sequence
The interface memory acts as an intermediary during these host
to signal processor RAM data exchanges. Information transfer
between RAM and interface memory is accomplished by the signal processor logic unit moving data between the SP main bus
and the SP 110 bus. The SP logic unit determines the RAM
address to read from or write into by the code stored in the RAM
ACCESS bits of interface memory registers. The SP logic unit
normally transfers a word from RAM to interface memory once
each cycle of the device code. Each RAM word transferred to the
interface memory is 32 bits long (16 bits in the transmitter). These
bits are written by the SP logic unit into interface memory registers 3, 2, 1, and 0 in that order. Registers 3 and 2 contain the
most and least significant bytes of XRAM data, respectively,
while registers 1 and 0 contain the most and least significant
bytes of YRAM data, respectively. As previously described for
parallel data mode, the data available bits set to a one when
register 0 of the respective signal processor is written into by the
.. device and resets to a zero when register 0 is read from by the
host. Since the parallel data mode transmitter and receiver data
register shares register 0 with the YRAM data, chip 0 and 1 RAM
access are disabled in parallel data mode. However, chip 2 RAM
access remains active in receiver parallel data mode.
The Figure 6 flowchart defines the auto dial sequence via the
microprocessor interface memory. The modem timing for the
auto dialer accounts for DTMF tone duration and interdigit delay.
The default tone duration is 95 ms and the default interdigit delay
is 71 ms. The default amplitudes for the high and low frequencies
are - 4 dBm and - 6 dBm, respectively. The above four parameters can be changed by performing a RAM write.
Table 9.
No.
RAM Access Codes
Function
1 DTMF Low Frequency
Amplitude'
2 DTMF High Frequency
Amplitude'
3 Interdigit Delay'
4 DTMFTone Duration'
5
6
7
8
9
The transmitter, sample rate device and the baud rate device
allow data to be transferred from interface memory to RAM.
When set to a one, bit SWRT (1 :7:3) signals the chip 1 SP logic
unit to suspend transfer of RAM data to the interface memory,
and instead, to transfer data from interface memory to RAM. Bit
BWRT (1 :7:2) performs the same function for chip 2 RAM. When
writing into the RAM, 32 bits are transferred. The 16 bits written
into XRAM come from registers 3 and 2, with register 3 being the
more significant byte. The 16 bits written into YRAM come from
registers 1 and 0, with register 1 being the more significant byte.
When only 16 bits of data are to be written, FF (a dummy RAM
location) must be stored in RAM ACCESS XS or RAM ACCESS
YS to prevent writing the mSlgnificant 16 bits of registers 1:3
through 1:0 into a valid RAM location. When the host processor
writes into register 1:0 the RSDA bit (1 :E:O) is reset to zero. When
the SP logic unit reads data from register 1 :0, the RSDA bit
(1 :E:O) is set to aone.ln a similar manner, bit RBDA (2:E:0) resets
Received Signal Samples
Demodulator Output
Low Pass Filter Output
Average Energy
AGC Gain Word
10 Equalizer Input
11 Equalizer Tap CoeffiCients
12 Unrotated Equalizer
Output
13 Rotated Equalizer Output
(Received Points)
14 Decision Points
Ideal Points
15 Error
16 Rotation Angle
17 Frequency Correction
18 EQM
19 Dual Point
2-19
X Access YAccess
Code
Code
(Hex) Register
Chip (Hex)
-
88
0,1
0
-
08
0,1
°°
1
-
89
09
0,1
0,1
1
1
1
1
CO
C2
D4
DC
81
Not Used
42
54
Not Used
Not Used
2,3
0,1,2,3
0,1,2,3
2,3
2,3
2
2
CO
81-AO
40
01-20
0,1,2,3
0,1,2,3
2
2
El
A2
61
22
0,1,2,3
0,1,2,3
2
62
0,1,2,3
2
2
2
2
2
E3
Not Used
63
00
Not Used
Not Used
2E
°
AA
A7
AE
0,1,2,3
0,1
2,3
2,3
0,1,2,3
Bell208A/B and Bell201C Modem
R20a/201
Figure 6.
R208/201 Auto Dial Sequence
2-20
Bell208A/B and Bell201C Modem
R208/201
PERFORMANCE
TYPICAL PHASE JITTER
TYPICAL BIT ERROR RATES
At 2400 bps, the modem exhibits a bit error rate of 10-6 or less
with a slgnal-to-noise ratio of 12.5 dB in the presence of 15°
peak-to-peak phase jitter at 150 Hz or with a slgnal-to-noise ratio
of 15 dB in the presence of 30° peak-to-peak phase jitter at
120 Hz (scrambler inserted).
The Bit Error Rate (BER) performance of the modem IS specified
for a test configuration conforming to that specified in CCITT
Recommendation V.56, except with regard to the placement of
the filter used to bandlimit the white noise source. Bit error rates
are measured at a received line signal level of - 20 dBm as
Illustrated.
At 4800 bps, the modem exhibits a bit error rate of 10-6 or less
with a signal-to-noise ratio of 19 dB in the presence of 15° peakto-peak phase jitter at 60 Hz.
TYPical BER performance IS shown In Figure 7. Figure 8 shows a
typical test setup to measure BER.
BELL 201C
2400 BPS
BELL 201C
2400 BPS
I
\
I
BELL 208A/B
4800 BPS
V.27
I
\,
\,
8
10
12
14
\
~
\ \
\
,
\
\.27
1\
\
10- 5
BELL 208A1B
4800 BPS
18
18
\
I
20
22
6
10
8
12
14
\
16
I
18
20
22
SIGNAL-TO-NOISE RATIO dB
SIGNAL-TO-NOISE RATIO dB
a) TYPICAL BIT ERROR RATE
(BACK TO BACK, Tl2 EQUALIZER, - 20 dBm)
b) TYPICAL BIT ERROR RATE
(UNCONDITIONED 3002 LINE, T/2 EQUALIZER, -20 dBm)
Figure 7.
R208/201 BER versus SNR
2-21
24
R208/201
Bell 208A/B and Bell 201C Modem
r-
MODEM
TRANSMITTER
-
3002
LINE
SIMULATOR
SEG FA-1445
-
IMPAIRMENT
SOURCE
BRADLEY 2A
AND 2B
-
ATTENUATOR
HP 3500
I
MODEM
RECEIVER
J
j
MODEM
TEST SET
PHOENIX
5000
LEVEL
METER
HP 3552A
NOTE
SIGNAL AND NOISE ARE MEASURED WITH 3 KHZ FLAT WEIGHTING.
Figure 8. BER Performance Test Set-up
2-22
I
I
"
\
Bell 208A/B and Bell 201C Modem
R208/201
GENERAL SPECIFICATIONS
Table 10.
Modem Power Requirements
Voltage
Tolerance
Current (Typical) @ 25°C
Current (Max) @ DOC
+5 Vdc
+12 Vdc
-12 Vdc
±5%
±5%
±5%
550 rnA
5 rnA
25 rnA
<700 rnA
< 10mA
< 50 rnA
Note: All voltages must have ripple ,,0.1 volts peak-to-peak.
Table 11. Modem Environmental Restrictions
Parameter
Temperature
Operating
Storage
Relative Humidity:
Altitude
Specification
O·C to +60 o C (32°F to 140°F)
- 40°C to + 80°C ( - 40°F to 176°F) (Stored In heat sealed antistatic bag and shipping container)
Up to 90% noncondensing, or a wet bulb temperature up to 35°C, whichever is less.
- 200 feet to + 10.000 feet
Table 12. Modem Mechanical Considerations
Parameter
DIN Connector Version
Board Structure:
Mating Connector:
Dimensions:
Width
Length
Connector Height
Component Height
Top (max.)
Bottom (max.)
Weight (max):
Lead Extrusion (max.):
DIP Connector Version
Board Structure:
Dimensions:
Width
Length
Component Height
Top (max.)
Bottom (max.)
Weight (max.):
Pin Length (max.)
Specification
Single PC board with a 3-row 64-pin right angle male DIN connector with rows A and C populated.
The modem can also be ordered with the following DIN connector: 64-pin DIN right angle female,
64-pin DIN vertical male or 64-pin DIN vertical female.
Female 3-row 64-pin DIN receptacle with rows A and C populated. Typical receptacle:
Winchester 968-6043-0531-1, Burndy R196B32ROOAooZ1, or equivalent.
3.94 in. (100 mm)
4.725 in. (120 mm)
0.437 in. (11.1 mm)
0.200 in. (5.1 mm)
0.130 in. (3.3 mm)
3.6 oz. (100 g)
0.100 in. (2.54 mm)
Single PC board with a row of 30 pins and a row of 31 pins in a dual In-line pin configuratiOn.
3.228 in. (82 mm)
3.937 In. (100 mm)
0.200 in. (5.1 mm)
0.130 in. (3.3 mm)
3.6 oz. (100 g)
0.53 in. (13.5 mm)
2-23
R208/201
Bell 208A/B and Bell 201C Modem
II
!
1
0.156 :I: 0.003 DIA (6 PL)
(3.96)
-
~~
T
3.937
)
0.496
-
II
.700
(94)
1
1 ~-
0.119
(3)1
-
~
1-(12.6)
,
~.~.
I--
4.100 (83)
-4.725 (104)
f~')
MALE 64-PIN
DIN CONNECTOR
O. 483
(1 2.3)
120
0.200 MAX
0.437
fl
cn_nnn_n_nn,
ro.~::~~~--------
----- m---h--~~~:~MAxJ
(1.6)
COMPONENT AREA
DIN CONNECTOR VERSION
-I
I
0.250
(6.4)
-I
~
I
3.228
'j~~
0.098 DIA (3 PL)
(2.5)
!.
I.,
~~~~o~~~o~o~o~~~
0'100~'100 (TYP.)
(2.54)
0.100
(2.54)
(2.54)
3 725
-'3.937 _(_94_.6_)_-+1
0.53 MAX
(100)
0.025
so. PIN
0.200 MAX
~--::::~~: f"t"'"
(1.6)
(3.3)
COMPONENT AREA
DIP CONNECTOR VERSION (PRELIMINARY)
Figure 9.
R208/201 Modem Dimensions and Pin Locations
2-24
UNITS: INCHES
mm
R48DP/208
Integral Modems
'1'
Rockwell
R48DP/208
4800 bps Data Pump Modem
INTRODUCTION
FEATURES
•
•
•
•
•
•
•
The Rockwell R48DP/208 is a synchronous 4800 bits per second
(bps) modem. It is designed for operation over the public switched
telephone network (PSTN) as well as leased lines through the
appropriate line termination.
The modem satisfies the telecommunications requirements
specified in CCITT Recommendation V.27 bis/ter and Bell
208AJB. The R48DP/208 can operate at speeds of 4800 and
2400 bps. Employing advanced signal processing techniques,
the R48DP/208 can transmit and receive data even under
extremely poor line conditions.
•
The R48DP/208 is designed for use in point-to-point environments. User programmable features allow the modem operation
to be tailored to support a wide variety of functional requirements. The modem's small size, low power consumption, and
serial/parallel host interface simplify system design and allow
installation in a compact enclosure. The modem module is available with a DIN connector for connection to a mating connector
or with dual-in-line pins (DIP) for direct plug-in installation onto a
host module.
•
•
•
•
•
CCITT V.27 bis/ter and Bell 208AJB Compatible
Point-ta-Point Applications
2-Wire Half-Duplex, 4-Wire Full-Duplex
Programmable Tone Generation
Programmable DTMF Tone Dialer
Dynamic Range: - 43 dBm to 0 dBm
Equalization
- Automatic Adaptive
- Compromise Cable and Link (Selectable)
DTE Interface
- Functional: CCITT V.24 (RS-232-C)(DataiControl) and
Microprocessor Bus (Data/Configuration/Control)
- Electrical: TTL and CMOS Compatible
Diagnostic Capability
Programmable Transmit Output Level
Loopbacks
- Local and Remote Analog
- Remote Digital
Small Size
- DIN Connector Version:
100 mm x 120 mm (3.94 in. x 4.73 in.)
- DIP Connector Version:
82 mm x 100 mm (3.23 in. x 3.94 in.)
Power Consumption: 3 W (Typical)
R48DP/208 DIN Connector Version
Document No. 29200N14
R48DP/208 DIP Connector Version
Data Sheet
2-25
Order No. MD14
Rev. 4, February 1987
4800 bps Data Pump Modem
R48DP/208
TECHNICAL SPECIFICATIONS
TRANSMITTED DATA SPECTRUM
TRANSMITTER CARRIER FREQUENCIES
If the cable equalizer is not enabled. the transmitter spectrum is
shaped by the following raised cosine filter functions:
The supported transmitter carrier frequencies are listed in
Table 1.
1. 1200 Baud.
Square root of 90 percent
2. 1600 Baud.
Square root of 50 percent
Table 1.
The out-of-band transmitter power limitations meet those specified by Part 68 of the FCC's rules. and typically exceed the
requirements of foreign telephone regulatory bodies.
Transmitter Carrier Frequencies
Function
Frequency
(Hz ±O.Ol%)
V.27 biS/ter and Bell 208 Carrier
1800
SCRAMBLERIDESCRAMBLER
The R960P incorporates a self-synchronizing scrambler!
descrambler. This facility is in accordance with either V.27 bis!
ter or Bell 208A1B depending on the selected configuration.
TONE GENERATION
RECEIVED SIGNAL FREQUENCY TOLERANCE
Under control of the host processor, the modem can generate
voice band tones up to 4800 Hz with a resolution of 0.15 Hz and
an accuracy of 0.01 %. Tones over 3000 Hz are attenuated.
OTMF tone transmission capability is provided to allow the
modem to operate as a programmable DTMF tone dialer.
The receiver circuit can adapt to received frequency error of up to
± 10 Hz with less than 0.2 dB degradation in BER performance.
RECEIVE LEVEL
The receiver circuit of the modem satisfies all specified performance requirements for received line signal levels from 0 dBm to
-43 dBm. The received line signal level is measured at the
receiver analog input (RXA).
SIGNALING AND DATA RATES
The supported signaling and data rates are listed in Table 2.
Table 2.
TRANSMIT LEVEL
The transmitter output level is accurate to ± 1.0 dB and is programmable from - 1.0 dBm to - 15.0 dBm in 2 dB steps.
Signaling/Data Rates
Baud Rate
Bits Per
Data Rate
Symbol
Specification (Symbols/sec.) Baud (bps)(±O.OlO/o) Points
V.27
Bell 208
V.27
1600
1600
1200
3
3
2
4800
4800
2400
TRAIN ON DATA
When train on data is enabled. the receiver typically trains on
data in less than 3.5 seconds.
8
4
4
TURN-ON SEQUENCE
Selectable turn-on sequences can be generated as defined in
Table 3.
DATA ENCODING
Table 3.
Turn-On Sequences
RTS-CTS Turn-On Time
The data encoding conforms to CCITT Recommendation V.27
bis!ter and Bell 20BA/B.
Specification
Bell 208 4800 bps long
Bell 208 4800 bps short
V.27 4800 bps long
V.27 4800 bps short
V.27 2400 bps long
V.27 2400 bps short
EQUALIZERS
The modem provides equalization functions that improve performance when operating over low quality lines.
Echo Protector
Tone Disabled
150
50
708
50
943
67
ms
ms
ms
ms
ms
ms
Echo Protector
Tone Enabled'
355
255
913
255
1148
272
ms
ms
ms
ms
ms
ms
• For short echo protector tone. subtract 155 ms from RTS-CTS
turn-on time.
cable Equalizers - Selectable compromise cable equalizers in
the receiver and transmitter are provided to optimize performance
over different lengths of non-loaded cable of 0.4 mm diameter.
TURN-OFF SEQUENCE
Link Equalizers - Selectable compromise link equalizers in the
receiver optimize performance over channels exhibiting severe
amplitude and delay distortion. Two standards are provided: U.S.
survey long and Japanese 3-link.
For V.27 ter and Bell 208. the turn-off sequence consists of
approximately 10 ms of remaining data and scrambled ones at
1200 baud or approximately 7 ms of data and scrambled ones at
1600 baud followed by a 20 ms period of no transmitted energy.
Automatic Adaptive Equalizer - An automatic adaptive equalizer is provided in the receiver circuit. The equalizer can be configured as either a T or a T!2 equalizer.
CLAMPING
Received Data (RXO) is clamped to a constant mark (one) whenever the Received Line Signal Detector (RLSO) is off.
2-26
R48DP/208
4800 bps Data Pump Modem
MODEM OPERATION
The interconnect signals on Figure 1 are organized into six groups
of modem operation: overhead signals, V.24 interface signals,
microprocessor interface signals, diagnostic signals, analog signals, and ancillary signals. Table 4 lists these groups along with
their corresponding connector pin numbers. The six groups of hardware circuits are described in the following paragraphs. Table 5 lists
the digital interface characteristics.
Because the modem is implemented in firmware executed by a
specialized computer (the signal processor), operation can best
be understood by dividing this section into hardware circuits and
software circuits. Hardware circuits include all pins on the
modem connector. Software circuits include configuration, control (soft strapping), status, and RAM access routines.
POWER-ON RESET
Basic modem operation can be understood most easily by beginning with the modem configured to default conditions. When the
modem is initially energized a signal called Power-On-Reset
(POR) causes the modem to assume a valid operational state.
The modem drives pin 13C to ground during the beginning of the
POR sequence. Approximately 10 ms after the low to high transition of pin 13C, the modem is ready for normal use. The POR
sequence is reinitiated anytime the + 5V supply drops below
+ 3.5Vfor more than 30 ms, or an external device drives pin 13C
low for at least 3 "s. When an external low input is applied to
pin 13C, the modem is ready for normal use approximately
10 ms after the low input is removed. Pin 13C is not dnven low by
the modem when the POR sequence is initiated externally. In all
cases, the POR sequence requires 50 ms to 350 ms to complete. The modem POR sequence leaves the modem configured
as follows:
HARDWARE CIRCUITS
The functional interconnect diagram (Figure 1) shows the
modem connected into a system. In this diagram, any point that
is active when exhibiting the relatively more negative voltage of a
two voltage system (e.g., 0 Vdc for TTL or -12 Vdc for
RS-232-C) is called low active and is represented by association
with a small circle at the signal point. The particular voltage levels used to represent the binary states do not change the logic
symbol. Two types of I/O points that may cause confusion are
edge-triggered inputs and open-collector (open-source or opendrain) outputs. These signal pOints include the additional notation of a small triangle or a small half-circle (see signal IRQ),
respectively. Active low signals are named with an overscore
(e.g., POR). In deciding whether a clock output is high active or
low active, the convention followed is to assume that the clocking
(activating) edge appropriate to the host hardware is a transition
from the clocks active to its inactive state (i.e., a trailing edge
trigger). A clock intended to activate logic on its rising edge is
called low active while a clock intended to activate logic on its
falling edge is called high active. When a clock input is associated with a small circle, the input activates on a falling edge. If
no circle is shown, the input activates on a riSing edge.
r-------.,
RTS
I
CTS
..
TXD
•
•
•
•
•
•
•
Bell 208 4800 bps Short Train
Serial channel data
T/2 equalizer
Standard echo protector tone
- 43 dBm threshold
Cable and link equalizers disabled
Train-On-Data disabled
O
.
.::.
t>---'-:..:..::.-•••. (~~
USRT
(OPTIONAL)
.l.-
SCOPE
TDCLK
EVEX
XTCLK
EVEV
EVE
PATTERN
t-_E~V~E:::S:..:;V..::N:.=C__~GENERATOR
RLSD
I
RXD
....
RDCLK
,::,1
xt tv
k
~
R48DP/208
TBCLK~
MODEM
RBCLK
EVECLK
+12V
+5V
POWER
SUPPLY
GND
READ
-12V
WRITE,..,
~~~D~A~T~A~BU~S~~(18~)-4~-Di
TXA
t-_+A:..:;D~D::..:R..::E:::S:.=S...:B::..:U:::S,-,(c:.'4)~ RSi
HOST
PROCESSOR
(DTE)
DECODER h
{
I'"'
CS (2).
RXA
CSi
POR;~
AUXIN
.....____....( ~.-______~I~RQ~-CI)
J -I'
+5
LINE
INTERFACE
-'\N'-
Figure 1.
R48DP/208 Functional Interconnect Diagram
2-27
TELEPHONE
LINE
R48DP/208
4800 bps Data Pump Modem
Table 4.
Name
Type'
DIN
Pin No.
DIP'
Pin No.
R48DP/208 Hardware Circuits
Description
Name
A. OVERHEAD:
Ground (A)
Ground (D)
DIN
DIP'
Type' Pin No. Pin No.
Description
C. V.24 INTERFACE:
AGND
DGND
+5 volts
PWR
+ 12 volts
-12 volts
POR
PWR
PWR
IIOB
31C,32C
30,31
Analog Ground Return
3C,8C, 29,37,53 Digital Ground Return
5A,10A
19C,23C, 1,45,61 + 5 volt supply
26C,30C
15A
32
+ 12 volt supply
12A
36
- 12 volt supply
13C
2
Power·on·reset
RDCLK
TDCLK
XTCLK
RTS
CTS
TXD
RXD
RLSD
21A
23A
22A
25A
25C
24C
22C
24A
OC
OC
IB
IB
OC
IB
OC
OC
23
46
51
50
49
48
26
27
Receive Data Clock
Transmit Data Clock
External Transmit Clock
Request·to·Send
Clear·to·Send
Transmitter Data
Receiver Data
Received Line Signal
Detector
22
47
Receiver Baud Clock
Transmitter Baud Clock
31A
32A
30A
34
33
Transmitter Analog Output
Receiver Analog Input
Auxiliary Analog Input
15C
14A
14C
13A
56
55
57
58
Eye Pattern
Eye Pattern
Eye Pattern
Eye Pattern
Signal
B. MICROPROCESSOR INTERFACE:
IIOA
IIOA
IIOA
IIOA
IIOA
IIOA
IIOA
IIOA
1C
1A
2C
2A
3A
4C
4A
5C
3
4
5
6
7
8
9
10
RS3
RS2
RS1
RSO
IA
IA
IA
IA
6C
6A
7C
7A
16
17
18
19
CSO
IA
10C
20
CS1
IA
9C
21
D7
D6
D5
D4
D3
D2
D1
DO
CS2
IA
9A
13
READ
WRITE
IRQ
IA
IA
OB
12C
11A
11C
14
12
11
},...~ ..,
D. ANCILLARY CIRCUITS:
RBCLK
TBCLK
('
26A
27C
OC
OC
E. ANALOG SIGNALS:
TXA
RXA
AUXIN
AA
AB
AC
-
F. DIAGNOSTIC:
}
Register Select
(4 Bits)
EYEX
EYEY
EYECLK
EYESYNC
Chip Select
Transmitter Device
Chip Select Receiver
Sample Rate Device
Chip Select Receiver
Baud Rate Device
Read Enable
Write Enable
Interrupt Request
Table 5.
OC
OC
OA
OA
Data-X AXIs
Data-Y AXIs
Clock
Synchronizing
Notes:
1. Refer to Table 5 for digital circuit Interface characteristics and
Table 7 for analog circuit Interface characteristics.
2. Pins not used on the DIP Version: 15, 24, 25, 28, 35, 38, 39,
40,41,42,43,44,52,54,59,60
Digital Interface Characteristics
Input/Output Type
Symbol
Parameter
Units
IA
IB
IC
V,H
Input Voltage, High
V
2.0 Min.
2.0 Min.
2.0 Min.
V'L
VOH
Input Voltage, Low
V
0.8 Max.
0.8 Max.
0.8 Max.
Output Voltage, High
V
VOL
Output Voltage, Low
liN
Input Current, Leakage
0.4 Max. 2
Output Current, High
mA
-0.1 Max.
Output Current, Low
mA
1.6 Max.
IL
Output Current, Leakage
p.A
Ipu
Pull-up Current
(Short Circuit)
p.A
CL
Capacitive Load
pF
Co
Capacitive Drive
pF
=
-100 p.A
1.6 mA
0.4 Max. 2
I/OB
2.0 Min.
5.25 Max.
2.0 Min.
O.B Max
O.B Max.
2.4 Min.'
2.4 Min 3
0.4 Max. 2
1.6 Max.
0.4 Max.5
4
1.6 Max.
± 10 Max.
5
-240 Max.
-10 Min.
-240 Max.
-10 Min.
5
20
-240 Max.
-10 Min.
100
TTL
=
0.4 Max. 2
I/O A
±2.5 Max
10H
1. I Load
2. I Load
OC
±25 Max.
10L
CircUit Type
OB
2.4 Min.'
V
p.A
OA
TTL
w/Pull-up
TTL
w/Pull-up
Notes
3. I Load = -40 p.A
4. V,N = 0.4 to 2.4 Vdc, Vee
2-28
TTL
100
100
10
40
100
100
Open-Drain Open-Drain
3-State
Open-Drain
w/Pull-up Transceiver w/Pull-up
5. I Load
=
-260 Max
-100 Min.
525 Vdc
=
036 mA
R48DP/208
4800 bps Data Pump Modem
This configuration IS suitable for performing high speed data
transfer uSing the serial data port. Individual features are discussed In subsequent paragraphs.
Received Line Signal Detector (RLSD)
For V.27 bis/ter or Bell 208, RLSD turns on at the end of the
training sequence. If training is not detected at the receiver, the
RLSD off-to-on response time is 15 ± 10 ms. The RLSD on-to-off
response time for V.27 IS 10 ± 5 ms. Response times are measured with a signal at least 3 dB above the actuai RLSD on the
threshold or at least 5 dB below the actual RLSD off threshOld.
V.24 INTERFACE
Eight hardware circuits provide timing, data, and control signals for
implementing a serial interface compatible with CCITT Recommendation V.24. These signals interface directly with circuits using TTL
logic levels (OV, + 5V). These TTL levels are suitable for driving the
short wire lengths or printed circuitry normally found within standalone modem enclosures or equipment cabinets. For driving longer
cables, the voltage levels and connector arrangement recommended by EIA standard RS-232-C are preferred.
The RLSD on-to-off response time ensures that all valid data bits
have appeared on RXD.
Four threshold options are provided:
1. Greater than - 43 dBm (RLSD on)
Less than - 49 dBm (RLSD off)
The sequence of events leading to successful data transfer from
transmitter to receiver is:
2. Greater than - 33 dBm (RLSD on)
Less than - 38 dBm (RLSD off)
1. The transmitter is activated and a training sequence is sent.
3. Greater than - 26 dBm (RLSD on)
Less than - 31 dBm (RLSD off)
2. The receiver detects channel energy above the prescribed
threshold level and synchronizes its operation to the
transmitter.
4. Greater than - 16 dBm (RLSD on)
Less than - 21 dBm (RLSD off)
3. Data transfer proceeds to the end of the message.
NOTE
4. The transmitter turns off after insuring that all data has had
time to be recovered at the receiver output.
Performance may be at a reduced level when the
received signal is less than - 43 dBm.
Transmitted Data (TXD)
A minimum hysteresis action of 2 dB exists between the actual
off-to-on and on-to-off transition levels. The threshold level and
hysteresis action are measured with an unmodulated 2400 Hz
tone applied to the receiver's audio input (RXA).
The modem obtains serial data from the local DTE on this input.
Received Data (RXD)
The modem presents received data to the local DTE on this
output.
Transmit Data Clock (TDCLK)
The modem provides a Transmit Data Clock (TDCLK) output with
the following characteristics:
Request To Send (RTS)
RTS ON allows the modem to transmit data on TXD when CTS
becomes active. The responses to RTS are shown in Table 6.
1. Frequency. Selected data rate of 4800 or 2400 Hz (± 0.01 %).
2. Duty Cycle. 50 ± 1%.
Clear To Send (CTS)
TDCLK is provided to the user in synchronous communications
for USRTtimlng. In thiS case Transmit Data (TXD) must be stable
during the one P.s periods immediately preceding and following
the rising edge of TDCLK.
CTS ON indicates to the terminai equipment that the modem will
transmit any data which are present on TXD. CTS response times
from an ON condition of RTS are shown in Table 6.
The time between the on-to-off transition of RTS and the on-to-off
transition of CTS in data state is a maximum of 2 band times for
all configurations.
Table 6.
External Transmit Clock (XTCLK)
In synchronous communication where the user needs to supply
the transmit data clock, the input XTCLK can be used. The clock
supplied at XTCLK must exhibit the same characteristics of
TDCLK. The XTCLK input is then reflected at TDCLK.
RTS-CTS Response Times
RTS-CTS Turn-On Time
Specification
Bell 208 4800 bps long
Bell 208 4800 bps short
V 27 4800 bps long
V.27 4800 bps shorl
V 27 2400 bps long
V.27 2400 bps short
Echo Protector
Tone Disabled
150
50
708
50
943
67
ms
ms
ms
ms
ms
ms
Echo Protector
Tone Enabled'
355
255
913
255
1148
272
Receive Data Clock (RDCLK)
ms
ms
ms
ms
ms
ms
The modem provides a Receive Data Clock (RDCLI<) output in
the form of a 50 ± 1% duty cycle squarewave. The low-to-high
transitions of this output coinCide with the center of received data
bits. RDCLK is provided to the user In synchronous communications for USRTtiming. The timing recovery circuit is capable of
tracking a ± .01 % frequency error in the associated transmit timing source.
• For short echo protector tone, subtract 155 ms from RTS-CTS
turn-on time.
2-29
4800 bps Data Pump Modem
R48DP/208
MICROPROCESSOR INTERFACE
to pull the IRQ line high when all IRQ drivers are off (i.e., it must
overcome the leakage currents). The resistor value should be
large enough to limit the driver sink current to a level acceptable
to each driver. For the case where only the modem IRQ driver is
used, a resistor value of 5.6K ohms ± 20%, 0.25 watt, is
sufficient.
Eight hardware circuits provide address, data, control, and interrupt signals for implementing a parallel interface compatible with
an 8080 microprocessor. With the addition of a few external logic
gates, the interface can be made compatible with a wide variety
of microprocessors such as 6500, 6800, or 68000.
ANALOG SIGNALS
The microprocessor interface allows a host microprocessor to
change modem configuration, read or write channel data as well
as diagnostic data, and supervise modem operation by means of
soft strappable control bits and modem status bits. The significance of the control and status bits and methods of data interchange are discussed in a later section devoted to software circuits. This section describes the operation of the interface from a
hardware standpoint.
The analog signal characteristics are described in Table 7.
Table 7. Analog Interface Characteristics
Chip Select (CSO-CS2) and
Register Selects (RSO-RS3)
The signal processor to be accessed is selected by grounding
one of three unique chip select lines, CS2, CS1 or CSO. The
selected chip decodes the four address lines, RS3 through RSO,
to select one of sixteen internal registers. The most significant
address bit (23) is RS3 while the least significant address bit (20)
is RSO. Once the address bits have been decoded, the selected
register can be read from or written into via an 8-bit parallel data
bus, D7 through DO. The most significant data bit (27) is D7 while
the least significant data bit (20) is DO.
Name
Type
TXA
AA
The transmitter output is S04 ohms ± 1%.
Characteristics
RXA
AB
The receiver input impedance is SOK ohms
±23%.
AUXIN
AC
The auxiliary analog input allows access to the
transmitter for the purpose of interfacing with
user provided equipment. Because this IS a
sampled data input, any signal above 4800 Hz
will cause aliasing errors. The input impedance
is 1K ohms, and the gain to transmitter output is
the TLVL setting + O.S dB - 1.4 dB.
Transmitter Analog (TXA)
The TXA line is an output suitable for driving an audio transformer or data access arrangement for connection to either
leased lines or the public switched telephone network. The output structure of TXA is a low impedance amplifier in series with
an internal 604 ohm ± 1% resistor to match a standard telephone load of 600 ohms.
Read Enable (READ) and
Write Enable (WRITE)
Reading or writing is activated by pulsing either the READ line
high or the WRITE line low. During a read cycle, data from the
selected register is gated onto the data bus by means of threestate drivers. These drivers force the data lines high for a one bit
or low for a zero bit. When not being read, the three-state drivers
assume their off, high-impedance, state. During a write cycle,
data from the data bus is copied into the selected register, with
high and low bus levels representing one bits and zero bits,
respectively. The timing required for correct read/write cycles is
illustrated in Figure 2. Logic necessary to convert the single Rm
output from a 65XX series microprocessor to the separate READ
and WRITE signals required by the modem is sho~n in Figure 3.
Receiver Analog (RXA)
RXA is an input to the receiver from an audio transformer or
data access arrangement. The input impedance is nominally
60K ohms but a factory select resistor allows a variance of 23%.
The RXA input must be shunted by an external resistor in order to
match a 600 ohm source. A 604 ohm ± 1% resistor is
satisfactory.
Some form of transient protection for TXA and RXA is recommended when operating directly into a transformer. This protection may take the form of back-to-back zener diodes across the
transformer or a varistor across the transformer.
Interrupt Request (IRQ)
The final signal on the microprocessor interface is Interrupt
Request (IRQ). This signal may be connected to the host microprocessor interrupt request input in order to interrupt host program execution for modem service. The use of IRQ is optional
and the method of software implementation is described in a
subsequent section, Software Circuits. The IRQ output structure
is an open-drain field-effect-transistor (FET). This form of output
allows IRQ to be connected in parallel to other sources of interrupt. Any of these sources can drive the host interrupt input low,
and the interrupt servicing process continues until all interrupts
have been cleared and all IRQ sources have returned to their
high impedance state. Because of the open-drain structure of
IRQ, an external pull-up resistor to + 5 volts is required at some
point on the IRQ line. The resistor value should be small enough
Auxiliary Input (AUXIN)
AUXIN provides a means of inserting audio signals into the
modem output stage. Because this input is summed with the
transmitter output prior to the transmitter low pass filter and compromise equalizers, the AUXIN signal is sampled by a compensated sample-and-hold circuit at a rate of 9600 samples-persecond. Any signal above 4800 Hz on the AUXIN line will be
aliased back into the passband as noise. One application for
AUXIN is to inject dual-tone multifrequency (DTMF) touch-tone
signals for dialing, however, the source of these tones must be
well filtered to eliminate components above 4800 Hz. The input
impedance of AUXIN is 1K ohm. The gain from AUXIN to TXA is
the same as the selected transmit level + 0.6 dB - 1.4 dB.
2-30
I
4800 bps Data Pump Modem
R48DP/208
WRITE
READ
CSi
(i
= 0,1)
RSi
(i
= 0-3)
READ
Di
(i
= 0-7)
Characteristic
CSi, RSI setup time prior
to Read or Write
Data access time after Read
Data hold time after Read
CSI, RSi hold time after
Read orWnte
Wnte data setup time
Write data hold time
Write strobe pulse width
Figure 2.
Figure 3.
Symbol
Min
TCS
TDA
TDH
30
TCH
TWDS
TWDH
TWR
10
75
10
75
10
Max
Units
140
50
ns
ns
ns
ns
ns
ns
ns
Microprocessor Interface Timing Diagram
RiW to
READ WRITE Conversion Logic
2-31
4800 bps Data Pump Modem
R48DP/208
or RS-232 recommendations since they mark the baud interval
for the transmitter and receiver rather than the data rate. The
baud clocks can be useful in identifying the order of data bits In a
baud (e.g., for multiplexing data, etc.). Both signals are high
active, meaning the baud boundaries occur on falling edges. The
first bit in each baud begins with the falling edge of the corresponding baud clock.
DIAGNOSTIC SIGNALS
EYEX, EYEY, EYECLK, and EYESYNC
Four card edge connections provide the timing and data necessary to create an oscilloscope quadrature eye pattern. The eye
pattern is simply a display of the received baseband constellation. By monitoring this constellation, an observer can often identify common line disturbances as well as defects in the modulation!
demodulation process.
SOFTWARE CIRCUITS
The outputs EYEX and EYEY provide two serial bit streams containing data for display on the oscilloscope X axis and Y axis,
respectively. Since this data is in serial digital form it must first be
converted to parallel digital form by two serial-to-parallel converters and then to analog form by two D!A converters. A clock
for use by the serial-to-parallel converters is furnished by signal
EYECLK. A strobe for loading the D!A converters is furnished by
signal EYESYNC. Timing of these signals is illustrated in Figure 4. The EYEX and EYEY outputs furnish 9-bit serial words.
Since most serial to parallel conversion logic is designed for 8-bit
words, an extra storage flip-flop is required for 9-bit resolution.
However, the ninth bit is not generally needed for eyepattern generation, and eight-bit hardware can be used if data is copied on
the rising edge of EYECLK rather than the failing edge.
Operation olthe microprocessor interface circuits was described
in the hardware section from the standpoint of timing and load!
drive characteristics. In this section, operation of the microprocessor interface is described from a software standpoint.
The modem is implemented In firmware running on three special
purpose Signal processors. These signal processors share the
computing load by performing tasks that are divided into areas.
These areas are partitioned into transmitter, baud rate, and sample rate devices.
INTERFACE MEMORY
Each signal processor can communicate with the host processor
by means of a specialized, dual-port, scratch-pad memory called
interface memory. A set of sixteen 8-bit registers, labeled register 0 through register F, can be read from or written into by either
the host processor or signal processor. The host communicates
via the microprocessor interface lines shared between the two
signal processors. The signal processor communicates via its
internal I/O bus. Information transfer from SP RAM to interface
memory is accomplished by the Signal processor logic unit moving data between the SP main bus and the SP I/O bus. Two of the
16 addressable interface memory registers (I.e., register 0 and
register E) have unique hardware connections to the Interrupt
logic. It is possible to enable a bit in register E to cause an interrupt each time it sets. This interrupt can then be cleared by a read
or write cycle from the host processor to register O. This operation is discussed in detail later in this section.
ANCILLARY SIGNALS
Transmitter Baud Clock (TBCLK) and
Receiver Baud Clock (RBCLK)
Two clock signals called TBCLK and RBCLK are provided at the
modem connector. These signals have no counterpart in the V. 24
LSB
MSB
Figure 4.
Memory maps of the 48 addressable registers in the modem are
shown in Figure 5. These registers may be read or written on any
host read or write cycle, but all eight bits of that register are
affected. In order to read aSingle bit or agroupof bits in a register,
the host processor must mask out unwanted data. When writing
a Single bit or group of bits in a register the host processor must
perform a read-modify-write operation. That is, the entire register
is read, the necessary bits are set or reset in the accumulator of
the host, then the original unmodified bits and the modified bits
are written back into the register of the interface memory.
Table 8 defines the individual bits in the interface memory. In the
Table 8 descriptions, bits in the interface memory are referred to
using the format Y:Z:Q. The chip number is specified by Y (0 or
1), the register number by Z (0 through F), and the bit number by
Q (0 through 7, with 0 = LSB).
Eye Pattern Timing
2-32
4800 bps Data Pump Modem
R48DP/208
Transmitter Interface Memory Chip 0 (CSO)
I~
7
6
5
E
TIA
0
-
c
-
-
B
8
-
-
7
RTS
4
2
3
0
1
Register
RAM ACCESS T
F
A
9
-
TPDM
XCEN
SEPT
A3L
D3L
TSB
TIE
-
-
-
SOlS
MHLD
EPT
-
TID IS
TBA
-
-
-
-
-
TRANSMITIER CONFIGURATION
6
-
5
-
CEO
L3ACf L4ACf
4
LDEN
LAEN
L4HG
TLVL
L2ACf LCEN
FREOM
3
2
FREOL
1
RAM DATA VTM
0
RAM DATA VTL; TRANSMITIER DATA, DDR
~
7
5
6
4
2
3
0
1
Bit
(-) Indicates reserved for modem use only.
Receiver Interface Memory Chip 2 (CS2)
Receiver Interface Memory Chip 1 (CS1)
I~
7
5
6
4
3
1
2
~
0
F
SOH
E
RSIA
0
-
c
B
A
9
8
7
-
-
-
PNDET
FED
-
IFIX
DDIS
ATH
6
7
6
5
4
3
2
1
-
-
-
-
RBIE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TOO
-
-
-
RSB
RSIE
-
-
-
-
-
-
-
-
TONE
-
P2DET
RPDM SWAT BWAT
-
F
E
RSDA
-
A
-
-
9
-
-
-
-
-
D
-
CDET
B
-
T2
ATDIS
C
8
7
8
RECEIVER CONFIGURATION
RBIA
5
RAM ACCESS XS
5
RAM ACCESS XB
4
RAM ACCESS VS
4
RAM ACCESS VB
3
RAM DATA XSM
3
RAM DATA XBM
2
RAM DATA XSL
2
RAM DATA XBL
1
RAM DATA YSM
1
RAM DATA VBM
0
RAM DATA VSL, RECEIVER DATA
0
RAM DATA VBL
7-
0
Registe
Register
7
6
5
4
3
1
2
~
0
7
6
5
4
3
( ) Indicates reserved for modem use only.
Figure 5.
2-33
-
-
-
-
-
-
-
-
-
-
-
-
2
1
0
(-) Indicates reserved lor modem use only.
Interface Memory Map
-
-
Bit
Bit
RBDA
-
4800 bps Data Pump Modem
R48DP/208
Table 8.
Mnemonic
Name
R48DP/208 Interface Memory Definitions
Memory
Location
Description
A3L
Amplitude 3-Link
Select
0:5: 1
A3L is used in conjunction with LAEN. When A3L is a one the Japanese 3 link
equalizer IS selected and when A3L is a zero the U.S. Survey Long link equalizer is
selected.
BWRT
Baud Write
1 :7:2
When control bit BWRT is a one, the RAM write operation is enabled for Chip 2
CEO
Cable Equalizer
Field
0:5:4,5
The CEO Control field simultaneously controls amplitude compromise equalizers In both
the transmit and receive paths. The following tables list the possible cable equalizer
selection codes and responses.
CEQ
Cable Length (0.4 mm diameter)
0
1
2
3
0.0
1.8 km
3.6 km
7.2 km
Cable Equalizer Nominal Gain
CEQ CODE 1
Gain Relative to 1700 Hz (dB)
Frequency
(Hz)
Transmitter
Receiver
700
1500
2000
3000
-0.99
-0.20
+0.15
+ 1.43
-0.94
-0.24
+0.31
+ 1.49
CEQ CODE 2
Frequency
(Hz)
700
1500
2000
3000
Gain Relative to 1700 Hz (dB)
Transmitter
Receiver
-2.39
-0.65
+0.87
+3.06
-2.67
-0.74
+1.02
+3.17
CEQ CODE 3
Gain Relative to 1700 Hz (dB)
Frequency
(Hz)
Transmitter
Receiver
700
1500
2000
3000
-3.93
-1.22
+ 1.90
+4.58
-3.98
-1.20
+ 1.81
+4.38
Unless a problem with training or high bit error rate is encountered, most applications
operate successfully with no cable equalizer selected.
CDET
Carner Detector
I:B:O
When zero, status bit CDET indicates that passband energy is being detected, and
that a training sequence is not in process. CDET goes to a zero at the start of the
data state, and returns to a one at the end of the received signal. CDET activates
up to 1 baud time before RLSD and deactivates within 2 baud times after RLSD If the
FED bit goes to a zero and no P2 sequence is detected, the CDET bit goes to zero
within 5 to 25 ms Indicating that the receiver has entered the data state without a
training sequence.
DDIS
Descramble Disable
1 :7:5
When control bit DDIS is a one, the receiver descrambler CirCUit IS removed from the
data path.
DDR
Dial Digit Register
0:0:0-7
DDR is used to tell the modem which DTMF digit to transmit (see Transmitter Data).
D3L
Delay 3-Link Select
0:5:0
D3L IS used in conjunction with LDEN. When D3L is a one the Japanese 3 link
equalizer is selected and when D3L is a zero the U.S Survey Long link equalizer is selected.
2-34
R48DP/208
4800 bps Data Pump Modem
Table S.
Mnemonic
Name
R4SDP/20S Interface Memory Definitions (Continued)
Memory
Location
Description
EPT
Echo Protector
Tone
0:7.3
When control bit EPT IS a one, an unmodulated carner IS transmitted for 185 ms
(optionally 30 ms) followed by 20 ms of no transmitted energy at the start of transmission.
FED
Fast Energy
Detector
1.9.6
When status bit FED IS a zero, It indicates that energy above the receiver threshold IS
present In the passband, and the receiver IS searching for the training sequence.
(None)
FREQUFREQM
o 2:0-7,
0.3 0-7
The host processor conveys tone generation data to the transmitter by writing a 16-bIt
data word to the FREQL and FREQM registers In the interface memory space, as
shown below'
FREQM Register (0:3)
Bit: ,
7
Data WOrd:,
2'5
,
,
6
2'4
FREQL Register (0:2)
Bit: ,
7
Data Word:'
27
,
,
6
26
,
,
2'3
,
,
25
,
,
5
,
,
5
2'2
,
,
4
,
4
,
2'
3
2"
3
23
,
,
2 '0
,
,
22
,
,
2
1
29
,
,
2
1
2'
,
0
,
28
,
,
2D
0
The frequency number (N) determines the frequency (F) as follows:
F = (0146486) (N) Hz ±0.01%
Hexadecimal frequency numbers (FREQL, FREQM) for commonly generated tones are
given below'
FREQM
FREQL
Frequency (Hz)
OC
10
2C
31
38
52
55
00
55
00
462
1100
1650
1850
2100
IFIX
Eye F,x
1 6:7
When control bit IFIX IS a one, the serial data on EYEX and EYEY reflect the rotated
equalizer output and do not follow the data selected by RAM ACCESS XB and RAM
ACCESS VB.
LAEN
Link Amplitude
Equalizer Enable
0:5'3
The link amplitude equalizer enable and select bits control an amplitude compromise
equalizer in the receive path according to the following table:
LAEN
A3L
Curve Matched
0
1
1
X
0
1
No Equalizer
U.S. Survey Long
Japanese 3-Link
The link amplitude equalizer responses are given
In
the follOWing table.
Link Amplitude Equalizer
Frequency
(Hz)
1000
1400
2000
2400
2800
3000
Gain Relative to 1700 Hz (dB)
U.S. Survey Long
-0.27
-0.16
+0.33
+154
+5.98
+8.65
2-35
Japanese 3-Link
-0.13
-0.08
+0.16
+0.73
+2.61
+343
4800 bps Data Pump Modem
R48DP/208
Table S.
Mnemonic
Name
R4SDP/20S Interface Memory Definitions (Continued)
Memory
Location
Description
LCEN
Loop Clock Enable
0:4:0
When control bit LCEN is a one, the transmitter clock tracks the receiver clock.
LDEN
Link Delay
Equalizer Enable
0:5:2
The link delay equalizer enable and select bits control a delay compromise equalizer in
the receive path according to the following table:
LDEN
D3L
Curve Matched
o
X
1
1
1
No Equalizer
U.S. Survey Long
Japanese 3-Link
o
The link delay equalizer responses are given in the following table.
Link Delay Equalizer
Frequency
(Hz)
Delay Relative to
1700 Hz (Microseconds)
u.s.
Survey Long
-498.1
-188.3
-15.1
+0.0
-39.8
-423.1
-672.4
800
1200
1600
1700
2000
2400
2800
Japanese 3·Link
-653.1
-398.5
-30.0
+0.0
+11.7
-117.1
-546.3
L2ACT
Remote Digital
Loopback Activate
0:4:1
When control bit L2ACT is a one, the receiver digital output is connected to the
transmitter digital input in accordance with CCITT recommendation V.54 loop 2.
L3ACT
Local Analog
Loopback Activate
0:4:7
When control bit L3ACT is a one, the transmitter analog output is coupled to the
receiver analog Input through an attenuator in accordance with CCITT recommendation
V.54 loop 3.
L4ACT
Remote Analog
Loopback Activate
0:4:6
When control bit L4ACT is a one, the receiver analog Input is connected to the transmitter
analog output through a variable gain amplifier in a manner similar to recommendation
V.54 loop 4.
L4HG
Loop 4 High Gain
0:4:5
When control bit L4HG is a one, the loop 4 variable gain amplifier is set for + 16 dB,
and when at zero the gain is zero dB.
MHLD
Mark Hold
0:7:4
When control bit MHLD is a one, the transmitter input data stream is forced to all marks
(ones).
PNDET
Period N Detector
I:B:6
When status bit PNDET is a zero, It indicates a PN sequence has been detected. ThiS
bit sets to a one at the end of the PN sequence.
P2DET
Period Two
Detector
1 :8:2
When status bit P2DET is a zero, it indicates that a P2 sequence has been detected.
This bit sets to a one at the start of the PN sequence.
(None)
RAM Access T
0:F:0-7
Contains the RAM access code used in reading or writing chip 0 RAM locations via
word Y (0:1 and 0:0).
(None)
RAM Access XB
2:5:0-7
Contains the RAM access code used in reading or writing chip 2 RAM locations via
word X (2:3 and 2:2).
(None)
RAM Access XS
1· 5:0-7
Contains the RAM access code used in reading or writing chip 1 RAM locations via
word X (1:3 and 1 :2).
(None)
RAM Access YB
2:4:0-7
Contains the RAM access code used in reading or writing chip 2 RAM locations via
word Y (2: 1 and 2:0).
2·36
4800 bps Data Pump Modem
R48DP/208
Table S.
Mnemonic
Name
R4SDP/20S Interface Memory Definitions (Continued)
Memory
Location
Description
(None)
RAM Access YS
1'4'0-7
Contains the RAM access code used
word Y (1 . 1 and 1 0).
(None)
RAM Data XBL
2 2'0-7
Least significant byte of 16·bit word X used In reading or writing RAM locations In
chip 2.
(None)
RAM Data XBM
2'3:0-7
Most significant byte of 16-bit word X used In reading or writing RAM locations
chip 2
(None)
RAM Data XSL
1'2'0-7
Least Significant byte of 16·bIt word X used
chip 1.
(None)
RAM Data XSM
1 :3:0-7
Most Significant byte of l6-bIt word X used In reading or writing RAM locations in
chip 1
(None)
RAM Data YBL
2:0 0-7
Least Significant byte of 16·blt word Y used In reading or writing RAM locations in
chip 2.
(None)
RAM Data YBM
2:1.0-7
Most Significant byte of 16·bit word Y used
chip 2.
(None)
RAM Data YSL
1 :0'0-7
Least significant byte of 16-blt word Y used In reading or writing RAM locations in
chip 1. Shared by parallel data mode for presenting channel data to the host
microprocessor bus. See 'Receiver Data.'
(None)
RAM Data YSM
1 :1'0-7
Most significant byte of 16·bit word Y used In reading or writing RAM locations in
chip 1.
(None)
RAM Data YTL
0:0:0-7
Least Significant byte of 16·blt word Y used In reading or writing RAM locallons In
chip 0 It is shared by parallel data mode and DTMF dialing (see Transmitter Data).
(None)
RAM Data YTM
0:1 0-7
Most significant byte of 16-byte word Y used in reading or writing locations In chip O.
RBDA
Receiver Baud
Data Available
2:E:0
Status bit RBDA goes to a one when the receiver writes data into register 2: O. The bit
goes to a zero when the host processor reeds data from register 2: O.
RBIA'
Receiver Baud
Interrupt Active
2:E:7
ThiS status bit is a one whenever the receiver baud rate deVice IS driving IRQ low. In
idle mode the interrupts from chip 2 occur at half the baud rate DUring diagnostic
access In data mode, the Interrupts occur at the baud rate.
RBIE
Receiver Baud
Interrupt Enable
2:E:2
When the host processor writes a one in the RBIE co~trol bit, the IRQ line of the
hardware Interface IS driven to zero when status bit RBDA is a one.
(None)
Receiver
Conflgurallon
1 :6'0-5
The host processor configures the receiver by writing a control code into the receiver
configuration field In the interface memory space (see RSB).
In
reading or writing chip 1 RAM locations via
In
In
reading or writing RAM locations
reading or writing RAM locations
ReceIver ConfIguration Control Codes
Control codes for the modem receiver configuration are:
Configuration Code (Hex)
Receiver Configuration
16
12
26
22
25
21
06
05
02
01
08
Bell 208A1B HDX
Bell 208A1B FOX
V 27 4800 HDX Long
V.274800 FOX Long
V.27 2400 HDX Long
V.27 2400 FOX Long
V 27 4800 HDX Short
V.27 2400 HOX Short
V 27 4800 FOX Short
V.27 2400 FOX Short
Tone Detector
2·37
In
In
In
R48DP/208
4800 bps Data Pump Modem
Table S.
Mnemonic
Name
R4SDP/20S Interface Memory Definitions (Continued)
Memory
Location
Description
(None)
Receiver Data
1 :0:0-7
The host processor obtains channel data from the receiver in the parallel data mode
by reading a data byte from the receiver data register. The data is divided on baud
boundaries as is the transmitter data When using receiver parallel data mode, the
registers 1:3 through 1:0 can not be used for reading the chip 1 RAM.
RPDM
Receiver Parallel
Data Mode
1:7:4
When control bit RPDM is a one, the receiver supplies channel data to the receiver data
register (1 : 0) as well as to the hardware serial data output (See Receiver Data)
RSB
Receiver Setup Brt
1 :E:3
When the host processor changes the receiver configuration or the RTH field, the host
processor must write a one In the RSB control bit. RSB goes to zero when the changes
become effective. Worst case setup time is 2 baud times
RSDA
Receiver Sample
Data Available
1:E:0
Status bit RSDA goes to a one when the receiver writes data to register 1 : O. RSDA
goes to a zero when the host processor reads data from register 1 : o.
RSIA
Receiver Sample
Interrupt Active
1:E:7
This status bit is a one whenever the receiver semple rate deVice IS driving IRQ to zero.
RSIE
Receiver Sample
Interrupt Enable
1:E:2
When the host processor writes a one in the RSIE control bit, the IRQ line of the
hardware Interface is driven to zero when status bit RSDA IS a one.
RTDIS
Receiver Training
Disable
1:7:0
When control bit RTDIS is a one, the receiver is prevented from recognizing a trainmg
sequence and entering the training state.
RTH
Receiver Threshold
Field
1:7:6,7
The receiver energy detector threshold is set by the RTH field according to the following
codes (see RSB):
RTH
RLSD On
0
1
2
3
> -43
>-33
> -26
>-16
dBm
dBm
dBm
dBm
RLSD Off
<-48
<-38
<-31
<-21
dBm
dBm
dBm
dBm
RTS
Request-to-Send
0:7:7
When control bit RTS goes to a one, the modem begms a transmit sequence. It
continues to transmit until RTS IS reset to zero, and the turn-off sequence has been
completed. This input bit parallels the operation of the hardware RTS control input.
These inputs are ORed by the modem.
SOlS
Scrambler Disable
0:7:5
When control bit SOlS is a one, the transmitter scrambler circuit is removed from the
data path.
SEPT
Short Echo
Protector Tone
0:7:0
When control bit SEPT is a one, the echo protector tone is 30 ms long rather than
185ms.
SQH
Receiver Squelch
1:F:7
When control bit SQH is set to a one, the receiver is squelched, RLSD is turned off and
RXD IS clamped to all marks. SQH only affects the receiver operation when a half
duplex receiver configuration has been selected.
SWRT
Sample Write
1:7:3
When control bit SWRT is a one, the RAM write operation is enabled for chip 1.
TBA
Transmitter Buffer
Available
O:E:O
ThiS status bit resets to zero when the host processor writes data to transmitter data
register 0: O. When the transmitter empties register 0: 0, this bit sets to a one. DUring a
RAM access in chip 0, when TBA IS a one the host can perform either a RAM read or
write depending on the state of bit 0: 6·3 (see Transmitter Configuration).
TIA
Transmitter
Interrupt Active
0.E:7
This status bit is a one whenever the transmitter is driVing IRQ to a zero
TIE
Transmitter
Interrupt Enable
0:E·2
When the host processor writes a one in control bit TIE, the IRQ line of the hardware
Interface is driven to zero when status bit TBA IS at a one.
2-38
R48DP/208
4800 bps Data Pump Modem
Table 8.
Mnemonic
TlVl
Name
Transmitter level
Field
R48DP/208 Interface Memory Definitions (Continued)
Memory
Location
0'4:2-4
Description
The transmitter analog output level is determined by eight TLVl codes, as follows'
Transmitter Analog Output"
TLVl
-1
-3
-5
-7
-9
-11
-13
-15
0
1
2
3
4
5
6
7
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
±1
±1
±1
±1
±1
±1
±1
±1
dB
dB
dB
dB
dB
dB
dB
dB
"Each step above IS a 2 dB change ± 0.2 dB.
TOO
Train-an-Data
1 :6:6
When control bit TOO IS a one, it enables the traln·on-data algonthm to converge the
equalizer if the signal quality degrades sufficiently. When TOO is a one, the modem stili
recognizes a training sequence and enters the force train state. A BER of approximately
10- 3 for 0.5 seconds lnillates train-an-date.
TONE
Tone Detect
1 :9:2
TONE Indicates with a zero the presence of energy In the 345-650 ± 10Hz frequency
range. For call progress purposes, the user may determine which tone IS present by
determining the duty cycle of the TONE bit.
TPDM
Transmitter Parallel
Data Mode
0:72
When control bit TPDM is a one, the transmitter accepts data for transmiSSion from the
transmitter data register (0: 0). When TPDM is a zero channel data from the serial hardware
input TXD is accepted and the chip 0 RAM access is enabled.
(None)
Transmitter
Conflgurallon"
0:6:0-7
The host processor configures the transmitter by wnting a control byte Into the transmitter
configuration register in ItS Interface memory space (See TSB.)
Transmitter Configuration Control Codes
Control codes for the modem transmitter configurations are:
Configuration Code (Hex)"
Transmitter Configuration
32
12
22
21
02
01
80
04
Bell 208A1B long
Bell 208A1B Short
V.27 4800 long
V.27 2400 long
V.27 4800 Short
V.27 2400 Short
Tone Transmit
DTMF Tone Transmit
*Note:
Bit 3 of the transmitter configuration register is used in the RAM access operation for
chip O. When 0.6' 3 IS a one, a RAM write operation Will occur when TPDM is a zero,
and when 0: 6: 3 is a zero, a RAM read operation Will occur when TPDM is a zero
Configuration Definitions
Definitions of the eight Transmitter Configurations are'
1 Bell 208. When a Bell 208 configuration has been selected, the modem operates as
specified In Bell 208A1B.
2. V.27. When a V.27 configuration has been selected, the modem operates as
specified In CCID Recommendation V.27 ter.
3. Tone Transmit. In this configuration, activating signal RTS causes the modem to
transmit a tone at a single frequency specified by two registers In the host interface
memory space containing the frequency code. The most significant bits are specified
In the FREQM register (0' 3). The least significant bits are specified In the FREQl
register (0.2). The least significant bit represents 0.146486 Hz ± 0.01 oro. The frequency
generated IS' f =0.146486 (256 FREQM + FREQl) Hz ±0.010J0.
4. DTMF Tone Transmit. In thiS configuration when the hex value of a DTMF digit IS
stored in register 0 0, a DTMF tone will be transmitted If RTS is enabled.
2-39
R4SDP/20S·
4S00 bps Data Pump Modem
Table S.
Mnemonic
(None)
Name
Transmitter; DDR;
RAM Data YTL
R4SDP/20S Interface Memory Definitions (Continued)
Memory
Location
0:0:0-7
Description
1. The host processor transmits data in the parallel mode by writing a data by1e to the
transmitter data register. The data is divided on baud boundaries, as follows:
NOTE
Data is transmitted bit zero first.
Bits
I
Configuration
7
Bell 208 4800 bps
Not Used
V.27 4800 bps
Not Used
V.27 2400 bps
Baud 3
6
5
I
4
I
3
2
Baud 1
1
I
0
Baud 0
Baud 1
Baud 2
I
Baud 0
I
Baud 1
I
Baud 0
2. Register 0: 0 is used to transmit DTMF digits when the transmitter is configured in
the DTMF tone transmit mode.
3. Register 0: 0 is a RAM data register used for reading or writing the least significant
by1e of the 16·bit Y word in Chip 0 when TPDM is a zero and no tone or DTMF tone
transmission is occurring.
TSB
Transmitter Setup
Bit
0:E:3
When the host processor changes the transmitter configuration, the host must write a
one in this control bit. TSB goes to a zero when the change becomes effective. Worst
case setup time is 2 baud + turnoff sequence + training (if applicable).
TIDIS
Transmitter Train
Disable
0:7:6
When control bit TIDIS is a one, the transmitter does not generate a training sequence
at the start of transmission. With training disabled, RTS/CTS delay is less than two
baud times.
T2
T/2 Equalizer
Select
1 :7:1
When control bit T2 is a one, an adaptive equalizer with two taps per baud is used.
When T2 is a zero, the equalizer has one tap per baud. The total number of taps
remains the same for both cases.
XCEN
External Clock
Enable
0:7:1
When control bit XCEN is a zero, the transmitter timing is established by the external
clock supplied at the hardware input XTCLK, pin 22A. The clock appearing at the
XTCLK input will appear at the TDCLK output.
2·40
R48DP/208
4800 bps Data Pump Modem
When reading from RAM, or writing into RAM, the bits in registers O:E, 1 :E, 2:E can be used for handshaking or interrupt functions as in parallel data mode. When not in parallel data mode,
the bits in register I:E perform the handshake and interrupt functions for RAM access. In both serial and parallel data modes, the
bits in register 2:E perform handshake and interrupt functions for
RAM access. When set to one, bit RBIE (2:E:2) enables RBDA to
drive the IRQ connector signal to zero volts when RBDA is a one.
Bit RBIA (2:E:7) identifies chip 2, the baud rate device, as a
source of IRQ interrupt. Bit RBIA is a one when both RBIE and
RBDA are set to one. In the event that other system elements may
cause IRQ to be driven low, the host must determine if modem
chip 2 is causing an interrupt by reading RBIA.
SIGNAL PROCESSOR RAM ACCESS
RAM and Data Organization
Each signal processor contains 128 words of random access
memory (RAM). Each word is 32 bits wide. Because the signal
processor is optimized for performing complex arithmetic, the
RAM words are frequently used for storing complex numbers.
Therefore, each word is organized into a real part (16 bits) and an
imaginary part (16 bits) that can be accessed independently.
The portion of the word that normally holds the real value is
referred to as XRAM. The portion that normally holds the imaginary value is referred to as YRAM. In the sample rate and baud
rate devices the entire contents of XRAM and YRAM may be read
from or written into by the host processor via the microprocessor
interface. Access to the YRAM is possible only in the transmitter
device.
Table 9 provides the available RAM access functions, codes, and
registers.
Interface Memory
Auto Dial Sequence
Th.e interface memory acts as an intermediary during these host
to signal processor RAM data exchanges. Information transfer
between RAM and interface memory is accomplished by the signal processor logic unit moving data between the SP main bus
and the SP 1/0 bus. The SP logic unit determines the RAM
address to read from or write into by the code stored in the RAM
ACCESS bits of interface memory registers. The SP logic unit
normally transfers a word from RAM to interface memory once
each cycle of the device code. Each RAM word transferred to the
interface memory is 32 bits long (16 bits in the transmitter). These
bits are written by the SP logic unit into interface memory registers 3, 2, 1, and 0 in that order. Registers 3 and 2 contain the
most and least significant bytes of XRAM data, respectively,
while registers 1 and 0 contain the most and least significant
bytes of YRAM data, respectively. As previously described for
parallel data mode, the data available bits set to a one when
register 0 of the respective signal processor is written into by the
device and resets to a zero when register 0 is read from by the
host. Since the parallel data mode transmitter and receiver data
register shares register 0 with the YRAM data, chip 0 and 1 RAM
access are disabled in parallel data mode. However, chip 2 RAM
access remains active in receiver parallel data mode.
The Figure 6 flowchart defines the auto dial sequence via the
microprocessor interface memory. The modem timing for the
auto dialer accounts for DTMF tone duration and interdigit delay.
The default tone duration is 95 ms and the default interdigit delay
is 71 ms. The default amplitudes for the high and low frequencies
are - 4 dBm and - 6 dBm, respectively. The above four parameters can be changed by performing a RAM write.
Table 9.
No.
RAM Access Codes
Function
1 DTMF Low Frequency
Amplitude
2 DTMF High Frequency
Amplitude
3 Interdigit Delay
4 DTMF Tone Duration
The transmitter, sample rate device and the baud rate device
allow data to be transferred from interface memory to RAM.
When set to a one, bit SWRT (1 :7:3) signals the chip 1 SP logic
unit to suspend transfer of RAM data to the interface memory,
and instead, to transfer data from interface memory to RAM. Bit
BWRT (1 :7:2) performs the same function for chip 2 RAM. When
writing into the RAM, 32 bits are transferred. The 16 bits written
into XRAM come from registers 3 and 2, with register 3 being the
more significant byte. The 16 bits written into YRAM come from
registers 1 and 0, with register 1 being the more significant byte.
When only 16 bits of data are to be written, FF (a dummy RAM
location) must be stored in RAM ACCESS XS or RAM ACCESS
YS to prevent writing the insignificant 16 bits of registers 1:3
through 1:0 into a valid RAM location. When the host processor
writes into register 1:0 the RSDA bit (1 :E:O) is reset to zero. When
the SP logic unit reads data from register 1 :0, the RSDA bit
(1 :E:O) is setto a one. In a similar manner, bit RBDA (2:E:0) resets
to zero when the host processor writes into register 2:0 and sets
to a one when the SP logic unit reads data from register 2:0.
5 Received Signal Samples
6 Demodulator Output
7 Low Pass Filter Output
8 Average Energy
9 AGC Gain Word
10 Equalizer Input
11 Equalizer Tap Coefficients
12 Unrotated Equalizer
Output
13 Rotated Equalizer Output
(Received POints)
14 Decision Points
Ideal Points
15 Error
16 Rotation Angle
17 Frequency Correction
18 EQM
19 Dual POint
2-41
X Access Y Access
Code
Code
Register
Chip
(Hex)
(Hex)
0
-
88
0,1
0
-
08
0,1
0
0
-
89
09
0,1
0,1
1
1
1
1
1
CO
C2
D4
DC
81
Not Used
42
54
Not Used
Not Used
2,3
0,1,2,3
0,1,2,3
2,3
2,3
2
2
CO
81-AO
40
01-20
0,1,2,3
0,1,2,3
2
2
El
A2
61
22
0,1,2,3
0,1,2,3
2
62
0,1,2,3
2
2
2
2
2
E3
Not Used
00
AA
A7
AE
63
Not Used
Not Used
2E
0,1,2,3
0,1
2,3
2,3
0,1,2,3
I
I
•
R48DP/208
4800 bps Data Pump Modem
TBA (O:E:O) = 17
Figure 6.
R48DP/208 Auto Dial Sequence
2·42
N
R48DP/208
4800 bps Data Pump Modem
PERFORMANCE
TYPICAL PHASE JITTER
TYPICAL BIT ERROR RATES
At 2400 bps, the modem exhibits a bit error rate of 10-6 or less
with a signal-to-noise ratio of 12.5 dB in the presence of 15°
peak-to-peak phase jitter at 150 Hz or with a signal-to-noise ratio
of 15 dB in the presence of 30° peak-to-peak phase jitter at
120 Hz (scrambler inserted).
The Bit Error Rate (BER) performance of the modem is specified
for a test configuration conforming to that specified in CCITT
Recommendation V.56, except with regard to the placement of
the filter used to band limit the white noise source. Bit error rates
are measured at a received line signal level of - 20 dBm as
illustrated.
At 4800 bps the modem exhibits a bit error rate of 10-6 or less with
a signal-to-noise ratio of 19 dB in the presence of 15° peak-topeak phase jitter at 60 Hz.
Typical BER performance is shown in Figure 7. Figure 8 shows a
typical test seJup to measure BEA.
2400 BPS
V.27
,
\
4800 BPS
V.27
BELL 208
10- 3
'\
W
l-
2400 BPS
V.27
cc
II:
II:
0
10-'
~
II:
II:
w
I-
iii
10- 5
10- 3
CC
0
w
I-
iii
\
6
8
10
12
14
\
\
10- 5
\
10- 6
10-'
II:
II:
\
,
1\
\\
W
l-
II:
II:
4800 BPS
V.27
BELL 208
16
10- 6
18
20
22
6
10
8
12
14
16
~
18
20
22
SIGNAL-TO-NOISE RATIO dB
SIGNAL-TO-NOISE RATIO dB
a) TYPICAL BIT ERROR RATE
(BACK TO BACK, T/2 EQUALIZER, -20 dBm)
b) TYPICAL BIT ERROR RATE
(UNCONDITIONED 3002 LINE, T/2 EQUALIZER, -20 dBm)
Figure 7.
R48DP/208 BER versus SNR
2-43
24
4800 bps Data Pump Modem
R48DP/208
-
MODEM
TRANSMITTER
-
3002
LINE
SIMULATOR
SEG FA-1445
-
IMPAIRMENT
SOURCE
BRADLEY 2A
AND 2B
f--
ATTENUATOR
HP 3500
I
I
MODEM
TEST SET
PHOENIX
5000
LEVEL
METER
HP 3552A
MODEM
RECEIVER
I
NOTE
SIGNAL AND NOISE ARE MEASURED WITH 3 KHZ FLAT WEIGHTING.
Figure 8. BER Performance Test Set-up
2-44
4800 bps Data Pump Modem
R48DP/208
GENERAL SPECIFICATIONS
Table 10. Modem Power Requirements
Voltage
Tolerance
Current (Typical) @ 25°C
Current (Max) @ DOC
+5 Vdc
+ 12 Vdc
-12 Vdc
± 50Al
±50Al
±5%
550 rnA
5 rnA
25 rnA
<700 rnA
< lOrnA
< 50 rnA
Note: All voltages must have ripple
oS 0.1
volts peak-to-peak.
Table 11. Modem Environmental Restrictions
Specification
Parameter
Temperature
Operating
Storage
Relative Humidity:
Altitude
OOC to + BOoC (32°F to 140°F)
- 40°C to + 80·C (- 40°F to 176°F) (Stored in heat sealed antistatic bag and shippmg container)
Up to 90% noncondensing, or a wet bulb temperature up to 35°C, whichever is less.
- 200 feet to + 10,000 feet
Table 12. Modem Mechanical Considerations
Parameter
DIN Connector Version
Board Structure'
Mating Connector
DimenSions:
Width
Length
Connector Height
Component Height
Top (max.)
Bottom (max)
Weight (max):
Lead Extrusion (max.)'
DIP Connector Version
Board Structure:
Dimensions:
Width
Length
Component Height
Top (max.)
Bottom (max)
Weight (max.):
Pin Length (max.)
Specification
Smgle PC board with a 3-row 64-pln right angle male DIN connector with rows A and C populated.
The modem can also be ordered with the following DIN connector: 64·pin DIN right angle female,
64-pm DIN vertical male or 64-pin DIN vertical female.
Female 3-row 64-pm DIN receptacle with rows A and C populated. Typical receptacle:
Wmchester 96S-6043-0531-1, Burndy R196B32ROOAOOZ1, or equivalent.
3.937 in. (100 mm)
4.725 m. (120 mm)
0.437 in. (11.1 mm)
o 200 In. (5.1
mm)
0.13010 (3.3 mm)
36 oz. (100 g)
o 100 in. (2.54 mm)
Single PC board with a row of 30 pins and a row of 31 pms 10 a dual m-line pin configuration.
3228 In. (82 mm)
3.937 in. (100 mm)
o 200 in.
(5.1 mm)
0130 In. (3.3 mm)
36 oz. (100 g)
0.53 in (13.5 mm)
245
R48DP/208
4800 bps Data Pump Modem
0.156 to.003 DIA (6 PL)
(3.96)
MALE 64-PIN
DIN CONNECIOR
IT
3.937
T~
0.496
(12.6)
0.119
(3)1
~~==..::-==~+-.j
~
~3_i8_2:_~__~
0.483
(12.3)
4.725 (104)
(120)
-----+j
0.200 MAX
~ ,---------------------Tt
---
r~;~~~~-------
0.437
[<11;)
i
----------~~~:~MAXJ
(1.6)
COMPONENT AREA
DIN CONNECTOR VERSION
i
j~~
0.098 DIA (3 PL)
(2.5)
I.,
!,
~#=---~~j=
0'100~'100 (TYP.)
(2.54)
0.100
(2.54)
(2.54)
3 725
-'3.937 (94.6)
(100) - - - - - + /
0.53 MAX
0.025 so. PIN
0.200 MAX
~~:::::":~::: f('t.....
UNITS: INCHES
(1.6)
(3.3)
COMPONENT AREA
DIP CONNECIOR VERSION (PRELIMINARY)
Figure 9.
R48DP/208 Modem Dimensions and Pin Locations
2-46
mm
R48DP
Integral Modems
'1'
Rockwell
R48DP
4800 bps Data Pump Modem
INTRODUCTION
FEATURES
• CCITT V.27 bislter Compatible
• Point-to-Point Applications
• 2-Wire Half-Duplex, 4-Wire Full-Duplex
• Programmable Tone Generation
• Dynamic Range: - 43 dBm to 0 dBm
• Equalization
- Automatic Adaptive
- Compromise Cable and Link (Selectable)
• DTE Interface
- Functional: CCITT V.24 (RS-232-C)(Data/Control) and
Microprocessor Bus (Data/Configuration/Control)
- Electrical: TTL and CMOS Compatible
• Diagnostic Capability
• Programmable Transmit Output Level
• Loopbacks
- Local and Remote Analog
- Remote Digital
• Small Size
- DIN Connector Version:
100 mm x 120 mm (3.94 in. x 4.73 in.)
- DIP Connector Version:
82 mm x 100 mm (3.23 in. x 3.94 in.)
• Power Consumption: 3 W (Typical)
The Rockwell R48DP is a synchronous 4800 bits per second
(bps) modem. It is designed for operation over the public switched
telephone network (PSTN) as well as leased lines through the
appropriate line termination.
The modem satisfies the telecommunications requirements
specified in CCITT Recommendation V.27 bis/ter. The R48DP
can operate at speeds of 4800 and 2400 bps. Employing
advanced signal processing techniques, the R48DP can transmit and receive data even under extremely poor line conditions.
The R48DP is designed for use in point-to-point environments.
User programmable features allow the modem operation to be
tailored to support a wide variety of functional requirements. The
modem's small size, low power consumption, and serial/parallel
host interface simplify system design and allow installation in a
compact enclosure. The modem module is available with a DIN
connector for connection to a mating connector or with dual-inline pins (DIP) for direct plug-in installation onto a host module.
R48DP DIP Connector Version
R48DP DIN Connector Version
Document No. 29200N08
Data Sheet
Order No. MD08
Rev. 4, February 1987
2-47
------~-----~--~-----~~-----
~---
R48DP
4800 bps Data Pump Modem
TECHNICAL SPECIFICATIONS
The out-of-band transmitter power limitations meet those specified by Part 68 of the FCC's rules, and typically exceed the
requirements of foreign telephone regulatory bodies.
TRANSMITTER CARRIER FREQUENCIES
The supported transmitter carrier frequencies are listed in
Table 1.
Table 1.
SCRAMBLERIDESCRAMBLER
The modem incorporates a self-synchronizing scrambler/
descrambler. This facility is in accordance with V.27 bislter.
Transmitter Carrier Frequencies
Function
Frequency
(Hz ±0.01%)
V.27 bosJter Carrier
1800
RECEIVED SIGNAL FREQUENCY TOLERANCE
The receiver circuit can adapt to received frequency error of up to
± 10Hz with less than 0.2 dB degradation in BER performance.
TONE GENERATION
RECEIVE LEVEL
Under control of the host processor, the modem can generate
voice band tones up to 4800 Hz with a resolution of 0.15 Hz and
an accuracy of 0.01 %. Tones over 3000 Hz are attenuated.
The receiver circuit of the modem satisfies all specified performance requirements for received line signal levels from 0 dBm to
-43 dBm. The received line signal level is measured at the
receiver analog input (RXA).
SIGNALING AND DATA RATES
TRANSMIT LEVEL
The supported signaling and data rates are listed in Table 2.
Table 2.
The transmitter output level is accurate to ± 1.0 dB and is programmable from -1.0 dBm to - 15.0 dBm in 2 dB steps.
Signaling/Data Rates
Baud Rate
Symbol
Bits Per
Data Rate
Specification (SymbolS/sec.) Baud (bpa)(± 0.01 %) Points
V.27
V.27
1600
1200
3
2
4800
2400
TRAIN ON DATA
8
4
When train on data is enabled, the receiver typically trains on
data in less than 3.5 seconds.
DATA ENCODING
TURN-ON SEQUENCE
The data encoding conforms to CCITT Recommendation V.27
bislter.
Selectable turn-on sequences can be generated as defined in
Table 3.
EQUALIZERS
Table 3.
RTS-CTS Turn-on Time
The modem provides equalization functions that improve performance when operating over low quality lines.
Specification
Cable equalizers - Selectable compromise cable equalizers in
the receiver and transmitter are provided to optimize performance
over different lengths of non-loaded cable of 0.4 mm diameter.
V.27
V.27
V.27
V.27
Link Equalizers - Selectable compromise link equalizers in the
receiver optimize performance over channels exhibiting severe
amplitude and delay distortion. Two standards are provided: U.S.
survey long and Japanese 3-link.
Square root of 50 percent
long
short
long
short
708
50
943
67
ms
ms
ms
ms
913
255
1148
272
ms
ms
ms
ms
For V.27 tar, the turn-off sequence consists of approximately
10 ms of remaining data and scrambled ones at 1200 baud or
approximately 7 ms of data and scrambled ones at 1600 baud
followed by a 20 ms period of no transmitted energy.
If the cable equalizer is not enabled, the transmitter spectrum is
shaped by the following raised cosine filter functions:
2. 1600 Baud.
bps
bps
bps
bps
Echo Protector·
Tone Enabled
TURN-OFF SEQUENCE
TRANSMITTED DATA SPECTRUM
Square root of 90 percent
4800
4800
2400
2400
Echo Protector
Tone Disabled
• For short echo protector tona, subtract 155 ms from RTS·CTS
turn-on time.
Automatic Adaptive Equalizer - An automatic adaptive equalizer is provided in the receiver circuit. The equalizer can be configured as either a T or a T12 equalizer.
1. 1200 Baud.
Turn-On Sequences
CLAMPING
Received Data (RXD) is clamped to a constant mark (one) when·
ever the Received Line Signal Detector (RLSD) is off.
2-48
4800 bps Data Pump Modem
R48DP
MODEM OPERATION
The interconnect signals on Figure 1 are organized Into six groups
of modem operation: overhead signals, V.24 interface signals,
microprocessor interface signals, diagnostic signals, analog signals, and ancillary signals. Table 4 lists these groups along with
their corresponding connector pin numbers. The six groups of hardware circuits are described in the following paragraphs. Table 5 lists
the digital interface characteristics.
Because the modem IS Implemented in firmware executed by a
specialized computer (the signal processor), operation can best
be understood by dividing this section Into hardware circuits and
software circuits. Hardware circuits include all pins on the
modem connector. Software circuits include configuration, control (soft strapping), status, and RAM access routines.
POWER-ON RESET
Basic modem operation can be understood most easily by beginning with the modem configured to default conditions. When the
modem is initially energized a signal called Power-On-Reset
(POR) causes the modem to assume a valid operational state.
The modem drives pin 13C to ground during the beginning of the
POR sequence. Approximately 10 ms after the low to high transition of pin 13C, the modem is ready for normal use. The POR
sequence is reinitiated anytime the + 5V supply drops below
+ 3.5V for more than 30 ms, or an external device drives pin 13C
low for at least 31's. When an external low input is applied to
pin 13C, the modem is ready for normal use approximately
10 ms after the low input is removed. Pin 13C is not driven low by
the modem when the POR sequence IS initiated externally. In all
cases, the POR sequence requires 50 ms to 350 ms to complete. The modem POR sequence leaves the modem configured
as follows:
HARDWARE CIRCUITS
The functional interconnect diagram (Figure 1) shows the
modem connected into a system. In this diagram, any pOint that
is active when exhibiting the relatively more negative voltage of a
two voltage system (e.g., 0 Vdc for TTL or -12 Vdc for
RS-232-C) is called low active and is represented by association
with a small circle at the signal point. The particular voltage levels used to represent the binary states do not change the logic
symbol. Two types of 110 points that may cause confusion are
edge-triggered inputs and open-collector (open-source or opendrain) outputs. These signal points include the additional notation of a small triangle or a small half-circle (see signal IRQ),
respectively. Active low signals are named with an overscore
(e.g., POR). In deciding whether a clock output is high active or
low active, the convention followed is to assume that the clocking
(activating) edge appropriate to the host hardware is a transition
from the clocks active to its inactive state (Le., a trailing edge
trigger). A clock intended to activate logic on its rising edge is
called low active while a clock intended to activate logic on its
falling edge is called high active. When a clock input is associated with a small circle, the input activates on a falling edge. If
no circle is shown, the input activates on a rising edge.
r--------,b
USRT
(OPTIONAL)
RTS
CTS
I
TXD
..A...
TDCLK
EVEX
XTCLK
EVEV
RLSD
EVESVNC
.
v
RDCLK
TBCLK'-'
,)
EVE
PATTERN
GENERATOR
EVECLK
RXD
,..,
JIll
xf tv
v
~
1
..
0SCOPE. .
•
!-..
:....
L---
• V.27, 4800 bps Short Train
• Serial channel data
• Tl2 equalizer
• Standard echo protector tone
• - 43 dBm threshold
• Cable and link equalizers disabled
• Train-On-Data disabled
R48DP
MODEM
RBCLK
+12V
+5V
POWER
SUPPLY
GND
READ
-12V
WRITE
DATA BUS /8\
HOST
PROCESSOR
(DTE)
TXA
Di
ADDRESS BUS (4)
RSi
RXA
DECODER ...... CS (2).
.........
LINE
INTERFACE
CSi
POR
~
IRQ
(I--.
+5
-A ,,...
J
Figure 1.
AUXIN
D
R48DP Functional Interconnect Diagram
2-49
TELEPHONE
LINE
R48DP
4800 bps Data Pump Modem
Table 4.
Name
Type'
DIN
Pin No.
Dlp2
Pin No.
R48DP Hardware Circuits
Description
Name
A. OVERHEAD:
Ground (A)
Ground (D)
DIP2
Pin No.
Description
C. V.24 INTERFACE:
AGND
DGND
+5 volts
PWR
+ 12 volts
-12 volts
POR
PWR
PWR
1I0B
31C,32C
Analog Ground Return
30,31
3C,aC, 29,37,53 Digital Ground Return
5A,10A
19C,23C, 1,45,61 + 5 volt supply
26C,30C
15A
32
+ 12 volt supply
12A
- 12 volt supply
36
13C
2
Power-an-reset
B. MICROPROCESSOR INTERFACE:
07
06
05
04
03
02
01
DO
DIN
Type' Pin No.
1I0A
1I0A
I/OA
I/OA
I/OA
IIOA
I/OA
I/OA
1C
1A
2C
2A
3A
4C
4A
5C
3
4
5
6
7
8
9
10
RS3
RS2
RS1
RSO
IA
IA
IA
IA
6C
6A
7C
7A
16
17
18
19
CSO
IA
10C
20
CS1
IA
9C
21
CS2
IA
9A
13
READ
WRITE
IRQ
IA
IA
OB
12C
11A
11C
14
12
11
},~,",
RDCLK
TDCLK
XTCLK
RTS
CTS
TXD
RXD
RLSD
...
OC
OC
IB
IB
OC
IB
OC
OC
21A
23A
22A
25A
25C
24C
22C
24A
23
46
51
50
49
48
26
27
Receive Data Clock
Transmit Data Clock
External Transmit Clock
Request-to·Send
Clear-to-Send
Transmitter Data
Receiver Data
Received Line Signal
Detector
22
47
Receiver Baud Clock
Transmitter Baud Clock
31A
32A
30A
34
33
Transmitter Analog Output
Receiver Analog Input
AUXIliary Analog Input
15C
14A
14C
13A
56
55
57
58
D. ANCILLARY CIRCUITS:
RBCLK
TBCLK
)
OC
OC
26A
27C
E. ANALOG SIGNALS:
TXA
RXA
AUXIN
AA
AB
AC
-
F. DIAGNOSTIC:
}
Register Select
(4 Bits)
EYEX
EYEY
EYECLK
EYESYNC
Chip Select
Transmitter Device
Chip Select Receiver
Sample Rate DeVice
Chip Select Receiver
Baud Rate Device
Read Enable
Write Enable
Interrupt Request
Table 5.
OC
OC
OA
OA
Eye Pattern
Eye Pattern
Eye Pattern
Eye Pattern
Signal
Data-X Axis
Data-Y Axis
Clock
SynchrOnizing
Notes:
1. Refer to Table 5 for digital.circuit interface characteristics and
Table 7 for analog circuit interface characteristics.
2. Pins not used on the DIP Version: 15, 24, 25, 28, 35, 38, 39,
40,41,42,43,44,52,54,59,60
Digital Interface Characteristics
Input/Output Type
Symbol
Parameter
Units
IA
IB
IC
V,H
Input Voltage, High
V
2.0 Min.
2.0 Min.
2.0 Min.
V'L
VOH
Input Voltage, Low
V
0.8 Max.
0.8 Max.
0.8 Max.
Output Voltage, High
V
VOL
Output Voltage, Low
liN
Input Current, Leakage
Output Current, High
mA
-0.1 Max.
Output Current, Low
mA
1.6 Max.
IL
Output Current, Leakage
I"A
Ipu
Pull-up Current
(Sharf Circuit)
pA
Capacitive Load
pF
Capacitive Drive
pF
Circuit Type
1. I Load
2. I Load
04 Max. 2
1/0 B
2.0 Min.
5.25 Max.
2.0 Min.
0.8 Max.
0.8 Max.
2.4 Min.'
2.4 Min.3
0.4 Max 2
0.4 Max.s
1.6 Max.
1.6 Max.
±10 Max.
5
-240 Max.
-10 Min.
-240 Max.
-10 Min.
5
20
-240 Max.
-10 Min.
100
TTL
= -100 pA
= 1.6 mA
0.4 Max,2
1/0 A
±2.5 Max.-
IOH
CL
OC
±2.5 Max.
IOL
Co
OB
2.4 Min.'
0.4 Max. 2
V
pA
OA
TTL
w/Pull-up
TTL
w/Pull-up
Notes
3. I Load = -40l"A
4. Y'N = 0.4 to 24 Vdc, Vee
2-50
TTL
100
100
-260 Max.
-100 Min.
10
40
100
100
Open-Drain Open-Drain
3-State
Open-Drain
w/Pull-up Transceiver w/Pull-up
5. I Load
= 5.25 Vdc
= 0.36 mA
4800 bps Data Pump Modem
R48DP
Received Line Signal Detector (RLSD)
This configuration is sUitable for performing high speed data
transfer using the serial data port. Individual features are discussed in subsequent paragraphs.
For V.27 bls/ter RLSD turns on at the end of the training
sequence. If training is not detected at the receiver, the RLSD offto-on response time is 15 ± 10 ms. The RLSD on-to-off response
time for V.27 is 10 ± 5 ms. Response times are measured with a
signal at least 3 dB above the actual RLSD on the threshold or at
least 5 dB below the actual RLSD off threshold.
V.24 INTERFACE
Eight hardware circuits provide timing, data, and control signals for
implementing a serial interface compatible with CCITI Recommendation V.24. These signals interface directly with circuits using TTL
logic levels (OV, + 5V). These TIL levels are suitable for driving the
short wire lengths or printed circuitry normally found within standalone modem enclosures or equipment cabinets. For driving longer
cables, the voltage levels and connector arrangement recommended by EIA standard RS-232-C are preferred.
The RLSD on-to-off response time ensures that all valid data bits
have appeared on RXD.
The sequence of events leading to successful data transfer from
transmitter to receiver is:
2. Greater than - 33 dBm (RLSD on)
Less than - 38 dBm (RLSD off)
1. The transmitter IS activated and a training sequence is sent.
3. Greater than - 26 dBm (RLSD on)
Less than - 31 dBm (RLSD off)
Four threshold options are provided:
1. Greater than - 43 dBm (RLSD on)
Less than - 49 dBm (RLSD off)
2. The receiver detects channel energy above the prescribed
threshold level and synchronizes its operation to the
transmitter.
4. Greater than - 16 dBm (RLSD on)
Less than - 21 dBm (RLSD off)
3. Data transfer proceeds to the end of the message.
NOTE
4. The transmitter turns off after insuring that all data has had
time to be recovered at the receiver output.
Performance may be at a reduced level when the
received signal is less than -43 dBm.
Transmitted Data (TXD)
A minimum hysteresis action of 2 dB exists between the actual
off-to-on and on-to-off transition levels. The threshold level and
hysteresis action are measured with an unmodulated 2400 Hz
tone applied to the receiver's audiO Input (RXA).
The modem obtains serial data from the local DTE on this input.
Received Data (RXD)
Transmit Data Clock (TDCLK)
The modem presents received data to the local DTE on thiS
output.
The modem provides a Transmit Data Clock (TDCLK) output with
the following characteristics:
Request To Send (RTS)
RTS ON allows the modem to transmit data on TXD when CTS
becomes active. The responses to RTS are shown in Table 6.
1. Frequency. Selected data rate of 4800 or 2400 Hz (± 0.01 %).
2. Duty Cycle. 50 ±1%.
Clear To Send (CTS)
TDCLK is provided to the user in synchronous communications
for USRTtiming. In this case Transmit Data (TXD) must be stable
during the one P.s periods immediately preceding and following
the rising edge of TDCLK.
CTS ON indicates to the terminal equipment that the modem will
transmit any data which are present on TXD. CTS response times
from an ON condition of RTS are shown in Table 6.
The time between the on-to-off transition of RTS and the on-to-off
transition of CTS in data state is a maximum of 2 band times for
all configurations.
Table 6.
External Transmit Clock (XTCLK)
In synchronous communication where the user needs to supply
the transmit data clock, the input XTCLK can be used. The clock
supplied at XTCLK must exhibit the same characteristics of
TDCLK. The XTCLK input is then reflected at TDCLK.
RTS-CTS Response Times
RTS-CTS Turn-On Time
Specification
V.27
V.27
V 27
V.27
4800
4800
2400
2400
bps
bps
bps
bps
long
short
long
short
Echo Protector
Tone Disabled
708
50
943
67
ms
ms
ms
ms
Receive Data Clock (RDCLK)
Echo Protector"
Tone Enabled
913
255
1148
272
The modem provides a Receive Data Clock (RDCLK) output in
the form of a 50 ± 1% duty cycle squarewave. The low-to-high
transitions ofthis output coincide with the center of received data
bits. RDCLK is provided to the user in synChronous communications for USRT timing. The timing recovery circuit is capable of
tracking a ± .01 % frequency error in the associated transmit timing source.
ms
ms
ms
ms
" For short echo protector tone, subtract 155 ms from RTS-CTS
turn~on tIme
2-51
•
,.
I
R48DP
4800 bps Data Pump Modem
MICROPROCESSOR INTERFACE
to pull the IRQ line high when all IRQ drivers are off (i.e., it must
overcome the leakage currents). The resistor value should be
large enough to limit the driver sink current to a level acceptable
to each driver. For the case where only the modem IRQ driver IS
used, a resistor value of 5.6K ohms ±20%, 0.25 watt, is
sufficient.
Eight hardware circuits provide address, data, control, and interrupt signals for implementing a parallel interface compatible with
an 8080 microprocessor. With th~ addition of a few external logic
gates, the interface can be made compatible with a wide variety
of microprocessors such as 6500,6800, or 68000.
ANALOG SIGNALS
The microprocessor interface allows a host microprocessor to
change modem configuration, read or write channel data as well
as diagnostic data, and supervise modem operation by means of
soft strappable control bits and modem status bits. The significance of the control and status Qits and methods of data interchange are discussed in a later section devoted to software circuits. This section describes the operation of the interface from a
hardware standpoint.
The analog signal characteristics are described in Table 7.
Table 7. Analog Interface Characteristics
Chip Select (CSO-CS2) and
Register Selects (RSO-RS3)
The signal processor to be accessed is selected by grounding
one of three unique chip select lines, CS2, CS1 or CSO. The
selected chip decodes the four address lines, RS3 through RSO,
to select one of sixteen internal registers. The most significant
address bit (23) is RS3 while the least significant address bit (20)
is RSO. Once the address bits have been decoded, the selected
register can be read from or written into via an 8-bit parallel data
bus, 07 through DO. The most significant data bit (27) is 07 while
the least significant data bit (2°) is DO.
Characteristics
Name
Type
TXA
AA
The transmitter output is 604 ohms ± 1%.
RXA
AS
The receiver input impedance is 60K ohms
±23%.
AUXIN
AC
The auxiliary analog input allows access to the
transmitter for the purpose of interfacing with
user provided equipment. Because this is a
sampled data input, any signal above 4800 Hz
will cause aliasing errors. The input impedance
is 1K ohms, and the gain to transmitter output is
the TLVL setting +0.6 dB -1.4 dB.
Transmitter Analog (TXA)
The TXA line is an output suitable for driving an audio transformer or data access arrangement for connection to either
leased lines or the public switched telephone network. The output structure of TXA is a low impedance amplifier in series with
an internal 604 ohm ± 1% resistor to match a standard telephone load of 600 ohms.
Read Enable (READ) and
Write Enable (WRITE)
Reading or writing is activated by pulsing either the READ line
high or the WRITE line low. During a read cycle, data from the
selected register is gated onto the data bus by means of threestate drivers. These drivers force the data lines high for a one bit
or low for a zero bit. When not being read, the three-state drivers
assume their off, high-impedance, state. During a write cycle,
data from the data bus is copied into the selected register, with
high and low bus levels representing one bits and zero bits,
respectively. The timing required for correct read/write cycles is
illustrated in Figure 2. Logic necessary to convert the single Rm
output from a 65XX series microprocessor to the separate READ
and WRITE signals required by the modem is shown in Figure 3.
Receiver Analog (RXA)
RXA is an input to the receiver from an audio transformer or
data access arrangement. The input impedance is nominally
60K ohms but a factory select resistor allows a variance of 23%.
The RXA input must be shunted by an external resistor in order to
match a 600 ohm source. A 604 ohm ± 1% resistor is
satisfactory.
Some form of transient protection for TXA and RXA is recommended when operating directly into a transformer. This protection may take the form of back-to-back zener diodes across the
transformer or a varistor across the transformer.
Interrupt Request (IRQ)
The final signal on the microprocessor interface is Interrupt
Request (IRQ). This signal may be connected to the host microprocessor interrupt request input in order to interrupt host program execution for modem service. The use of IRQ is optional
and the method of software implementation is described in a
subsequent section, Software Circuits. The IRQ output structure
is an open-drain field-effect-transistor (FET). This form of output
allows IRQ to be connected in parallel to other sources of interrupt. Any of these sources can drive the host interrupt input low,
and the interrupt servicing process continues until all interrupts
have been cleared and all IRQ sources have returned to their
high impedance state. Because of the open-drain structure of
IRQ, an external pull-up resistor to + 5 volts is required at some
point on the IRQ line. The resistor value should be small enough
Auxiliary Input (AUXIN)
AUXIN provides a means of inserting audio Signals into the
modem output stage. Because this input is summed with the
transmitter output prior to the transmitter low pass filter and compromise equalizers, the AUXIN signal is sampled by a compensated sample-and-hold circuit at a rate of 9600 samples-persecond. Any Signal above 4800 Hz on the AUXIN line will be
aliased back into the passband as noise. One application for
AUXIN is to inject dual-tone multifrequency (DTMF) touch-tone
signals for dialing, however, the source of these tones must be
well filtered to eliminate components above 4800 Hz. The input
impedance of AUXIN is 1K ohm. The gain from AUXIN to TXA is
the same as the selected transmit level + 0.6 dB - 1.4 dB.
2-52
R48DP
4800 bps Data Pump Modem
WRITE
READ
CSi
(i = 0,1)
RSi
(i
= 0-3)
..
READ
Di
(i = 0-7)
Characteristic
CSi, RSi setup time prior
to Read or Write
Data access time after Read
Data hold time after Read
CSI, RSi hold time after
Read or Write
Write data setup time
Write data hold time
Write strobe pulse width
Figure 2.
Symbol
Min
Max
Units
TCS
TDA
TDH
30
-
10
140
50
ns
ns
ns
10
75
10
75
TCH
TWOS
TWDH
TWR
-
ns
ns
ns
ns
-
Microprocessor Interface Timing Diagram
02
t2C
READ
R48DP
MODEM
ItA
R/W
Figure 3.
R/W to READ WRITE Conversion Logic
2-53
WRITE
R48DP
4800 bps Data Pump Modem
or RS-232 recommendations since they mark the baud interval
for the transmitter and receiver rather than the data rate. The
baud clocks can be useful in Identifying the order of data bits in a
baud (e.g., for multiplexing data, etc.). Both signals are high
active, meaning the baud boundaries occur on falling edges. The
first bit In each baud begins with the falling edge of the corresponding baud clock.
DIAGNOSTIC SIGNALS
EYEX, EYEY, EYECLK, and EYESYNC
Four card edge connections provide the timing and data necessary to create an oscilloscope quadrature eye pattern. The eye
pattern is simply a display of the received baseband constellation. By monitoring this constellation, an observer can often identify common line disturbances as well as defects in the modulationl
demodulation process.
SOFTWARE CIRCUITS
The outputs EYEX and EYEY provide two serial bit streams containing data for display on the oscilloscope X axis and Y aXIS,
respectively. Since this data is in serial digital form it must first be
converted to parallel digital form by two serial-to-parallel converters and then to analog form by two D/A converters. A clock
for use by the serial-to-parallel converters is furnished by Signal
EYECLK. A strobe for loading the D/A converters is furnished by
signal EYESYNC. Timing of these signals is illustrated in Figure 4. The EYEX and EYEY outputs furnish 9-bit serial words.
Since most serial to parallel conversion logic is designed for 8-bit
words, an extra storage flip-flop is required for 9-bit resolution.
However, the ninth bit is not generally needed for eyepattern generation, and eight-bit hardware can be used if data is copied on
the rising edge of EYECLK rather than the falling edge.
Operation olthe microprocessor interface circuits was described
in the hardware section from the standpoint of timing and loadl
drive characteristics. In this section, operation of the microprocessor Interface IS described from a software standpoint.
The modem is implemented in firmware running on three speCial
purpose signal processors. These signal processors share the
computing load by performing tasks that are divided into areas.
These areas are partitioned into transmitter, baud rate, and sample rate devices.
INTERFACE MEMORY
Each signal processor can communicate with the host processor
by means of a specialized, dual-port, scratch-pad memory called
interface memory. A set of sixteen 8-bit registers, labeled register 0 through register F, can be read from or written into by either
the host processor or signal processor. The host communicates
via the microprocessor interface lines shared between the two
signal processors. The signal processor communicates via its
internal 1/0 bus. Information transfer from SP RAM to interface
memory is accomplished by the signal processor logic unit moving data between the SP main bus and the SP 1/0 bus. Two of the
16 addressable interface memory registers (i.e., register 0 and
register E) have unique hardware connections to the interrupt
logic. It is possible to enable a bit in register E to cause an interrupt each time it sets. This interrupt can then be cleared by a read
or write cycle from the host processor to register O. This operation is discussed in detail later in this section.
ANCILLARY SIGNALS
Transmitter Baud Clock (TBCLK) and
Receiver Baud Clock (RBCLK)
Two clock signals called TBCLK and RBCLK are provided at the
modem connector. These signals have no counterpart in the V.24
EYESYNC
Memory maps of the 48 addressable registers in the modem are
shown in Figure 5. These registers may be read or written on any
host read or write cycle, but all eight bits of that register are
affected. In orderto read asingle bit or a group of bits in a register,
the host processor must mask out unwanted data. When writing
a single bit or group of bits in a register the host processor must
perform a read-modify-write operation. That is, the entire register
is read, the necessary bits are set or reset in the accumulator of
the host, then the original unmodified bits and the modified bits
are written back Into the register of the Interface memory.
EYEX,
EYEY
MSB
Figure 4_
Table 8 defines the individual bits in the interface memory. In the
Table 8 descriptions, bits In the interface memory are referred to
using the format Y:Z:Q. The chip number is specified by Y (0 or
1), the register number by Z (0 through F), and the bit number by
Q (0 through 7, with 0 = LSB).
Eye Pattern Timing
2-54
4800 bps Data Pump Modem
R48DP
Transmitter Interface Memory Chip 0 (CSO)
I~
7
6
5
4
3
2
1
0
Register
F
-
-
-
-
-
-
-
E
TIA
-
-
-
TSB
TIE
-
0
--
-
-
-
-
-
-
-
-
-
-
-
B
-
-
-
-
C
-
-
-
-
A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SDIS
MHLD
TPDM
XCEN
SEPT
9
8
7
RTS
TIDIS
6
EPT
-
TBA
-
-
TRANSMITTER CONFIGURATION
X
5
4
X
CEQ
L3ACT L4ACT
LAEN
LDEN
TLVL
L4HG
A3L
D3L
L2ACT
LCEN
FREQM
3
FREQL
2
-
1
-
-
0
-
-
-
-
-
1
0
TRANSMITIER DATA, DDR
~
7
6
5
4
3
2
Bit
(-) Indicates reserved for modem use only.
Receiver Interface Memory Chip 1 (CS1)
~
7
6
5
4
2
3
Receiver Interface Memory Chip 2 (CS2)
~
0
1
F
E
-
-
RSIA
0
-
-
C
-
-
B
-
PNDET
9
-
FED
8
-
-
A
7
-
RTH
IFIX
6
7
6
5
4
3
2
1
-
-
-
-
-
RBIE
-
-
-
DDIS
TOD
-
-
-
-
-
RSIE
RSB
RSDA
F
-
-
E
RBIA
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CDET
-
-
-
A
-
C
B
-
-
-
-
-
9
P2DET
8
BWRT
T2
RTDIS
7
-
-
6
-
-
RPDM SWRT
RECEIVER CONFIGURATION
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
1
5
RAM ACCESS XB
4
RAM ACCESS VS
4
RAM ACCESS VB
3
RAM DATA XSM
3
RAM DATA XBM
2
RAM DATA XSL
2
RAM DATA XBL
1
RAM DATA VSM
1
RAM DATA VBM
0
RAM DATA VSL, RECEIVER DATA
0
RAM DATA VBL
7
6
5
4
3
1
2
~
0
7
6
5
4
3
Bit
(-) Indicates reserved for modem use only.
Figure 5,
(-) Indicates reserved for modem use only.
Interface Memory Map
2·55
-
-
RAM ACCESS XS
Bit
RBDA
-
5
~
0
Registe
Register
-
-
-
-
I
0
4800 bps Data Pump Modem
R48DP
Table 8.
Mnemonic
Name
R48DP Interface Memory Definitions
Memory
Location
Description
A3L
Amplitude 3·Link
Select
0:5:1
A3L is used in conjunction with LAEN. When A3L is a one the Japanese 3 link
equalizer is selected and when A3L is a zero the U.S. Survey Long link equalizer is
selected.
BWRT
Baud Write
1 :7:2
When control bit BWRT is a one, the RAM write operation IS enabled for Chip 2.
CEO
Cable Equalizer
Field
0:5:4,5
The CEO Control field simultaneously controls amplitude compromise equalizers in both
the transmit and receive paths. The following tables list the possible cable equalizer
selection codes and responses.
CEQ
Cable Length (0.4 mm diameter)
0
1
2
3
0.0
1.8 km
3.6 km
7.2 km
Cable Equalizer Nominal Gain
CEQ CODE 1
Gain Relative to 1700 Hz (dB)
Frequency
(Hz)
Transmitter
Receiver
700
1500
2000
3000
-0.99
-0.20
+0.15
+ 1.43
-0.94
-0.24
+0.31
+ 1.49
CEQ CODE 2
Gain Relative to 1700 Hz (dB)
Frequency
(Hz)
Transmitter
Receiver
700
1500
2000
3000
-2.39
-0.65
+0.87
+3.06
-2.67
-0.74
+ 1.02
+3.17
CEQ CODE 3
Gain Relative to 1700 Hz (dB)
Frequency
(Hz)
Transmitter
Receiver
700
1500
2000
3000
-3.93
-1.22
+ 1.90
+4.58
-3.98
-1.20
+1.81
+4.38
Unless a problem with training or high bit error rate IS encountered, most applications
operate successfully with no cable equalizer selected.
CDET
Carrier Detector
1:B:0
When zero, status bit CDET indicates that passband energy is being detected, and
that a training sequence is not In process. CDET goes to a zero at the start of the
data state, and returns to a one at the end of the received signal. CDET activates
up to 1 baud time before RLSD and deactivates within 2 baud times after RLSD. If the
FED bit goes to a zero and no P2 sequence is detected, the CDET bit goes to zero
within 5 to 25 ms indicating that the receiver has entered the data state without a
training sequence.
DDIS
Descramble Disable
1 :7:5
When control bit DDIS is a one, the receiver descrambler Circuit is removed from the
data path.
DDR
Dial Digit Register
0:0:0-7
DDR is used to tell the modem which DTMF digit to transmit (see Transmitter Data).
D3L
Delay 3-Link Select
0:5:0
D3L is used In conjunction with LDEN. When D3L is a one the Japanese 3 link
equalizer is selected and when D3L is a zero the U.S Survey Long link equalizer IS selected
2-56
4800 bps Data Pump Modem
R48DP
Table 8.
Mnemonic
Name
R48DP Interface Memory Definitions (Continued)
Memory
location
Description
EPT
Echo Protector
Tone
0:7:3
When control bit EPT IS a one, an un modulated carrier is transmitted for 185 ms
(optionally 30 ms) followed by 20 ms of no transmitted energy at the start of transmission
FED
Fast Energy
Detector
1'9:6
When status bit FED IS a zero, It indicates that energy above the receiver threshold is
present in the passband, and the receiver IS searchmg for the training sequence.
(None)
FREOLIFREOM
0:2:0-7,
0:3:0-7
The host processor conveys tone generation data to the transmitter by writing a 16-blt
data word to the FREOL and FREOM registers in the interface memory space, as
shown below:
FREOM Register (0:3)
Bit:
Data Word:
I
I
7
2'5
I
I
6
214
I
I
I
5
2'3
I
5
I
I
4
I
2'2
I
4
I
I
3
I
2"
J
3
I
2
I
2'0
I
2
I
1
29
I
I
0
28
FREOL Register (0:2)
Bit:
Data Word:
I
I
7
27
I
I
6
26
I
I
25
2'
23
I
22
1
I
2'
I
I
0
20
The frequency number (N) determines the frequency (F) as follows:
F = (0.146486) (N) Hz ±0.01%
Hexadecimal frequency numbers (FREOL, FREOM) for commonly generated tones are
given below:
FREQM
FREQl
Frequency (Hz)
OC
10
2C
31
38
52
55
00
55
00
462
1100
1650
1850
2100
IFIX
Eye Fix
1 :6:7
When control bit IFIX is a one, the serial data on EYEX and EYEY reflect the rotated
equalizer output and do not follow the data selected by RAM ACCESS XB and RAM
ACCESS VB.
LAEN
Link Amplitude
Equalizer Enable
0:5:3
The link amplitude equalizer enable and select bits control an amplitude compromise
equalizer in the receive path according to the following table:
lAEN
A3l
Curve Matched
0
1
1
X
0
1
No Equalizer
U.S. Survey Long
Japanese 3-Lmk
The link amplitude equalizer responses are given in the following table.
link Amplitude Equalizer
Frequency
(Hz)
Gain Relative to 1700 Hz (dB)
U.S. Survey long
-0.27
-0.16
+0.33
+1.54
+5.98
+8.65
1000
1400
2000
2400
2800
3000
2-57
Japanese 3-Link
-0.13
-0.08
+0.16
+0.73
+2.61
+3.43
R48DP
4800 bps Data Pump Modem
Table 8.
Mnemonic
Name
R48DP Interface Memory Definitions (Continued)
Memory
Location
Description
LCEN
Loop Clock Enable
0:4:0
When control bit LCEN is a one, the transmitter clock tracks the receiver clock.
LDEN
Link Delay
Equalizer Enable
0:5'2
The link delay equalizer enable and select bits control a delay compromise equalizer in
the receive path according to the following table:
LDEN
D3L
Curve Matched
o
X
1
1
1
No Equalizer
U.S. Survey Long
Japanese 3-Link
o
The link delay equalizer responses are given in the following table.
Link Delay Equalizer
Delay Relative to
1700 Hz (Microseconds)
Frequency
(Hz)
U.S. Survey Long
Japanese 3-Link
800
1200
1600
1700
2000
2400
2800
-498.1
- 188.3
-15.1
+0.0
-39.S
-423.1
-672.4
-653.1
- 398.5
-30.0
+0.0
+11.7
-117.1
-546.3
L2ACT
Remote Digital
Loopback Activate
0:4:1
When control bit L2ACT is a one, the receiver digital output is connected to the
transmitter digital input in accordance with CCITT recommendation V.54 loop 2.
L3ACT
Local Analog
Loopback Activate
0:4:7
When control bit L3ACT is a one, the transmitter analog output is coupled to the
receiver analog input through an attenuator in accordance with CCITT recommendation
V.54 loop 3.
L4ACT
Remote Analog
Loopback Activate
0:4:6
When control bit L4ACT is a one, the receiver analog input is connected to the transmitter
analog output through a variable gain amplifier in a manner simiiar to recommendation
V.54 loop 4.
L4HG
Loop 4 High Gain
0:4:5
When control bit L4HG is a one, the loop 4 variable gain amplifier is set for + 16 dB,
and when at zero the gain is zero dB.
MHLD
Mark Hold
0:7:4
When control bit MHLD is a one, the transmitter input data stream is forced to all marks
(ones).
PNDET
Penod N Detector
1 :B:6
When status bit PNDET is a zero, it indicates a PN sequence has been detected. This
bit sets to a one at the end of the PN sequence.
Period Two
Detector
1 :8:2
When status bit P2DET is a zero, it indicates that a P2 sequence has been detected.
This bit sets to a one at the start of the PN sequence.
(None)
RAM Access XB
2:5:0-7
Contains the RAM access code used in reading or writing chip 2 RAM locations via
word X (2:3 and 2:2).
(None)
RAM Access XS
1 :5:0-7
Contains the RAM access code used in reading or writing chip 1 RAM locations via
word X (1:3 and 1 :2).
(None)
RAM Access YB
2:4:0-7
Contains the RAM access code used in reading or writing chip 2 RAM locations via
word Y (2:1 and 2:0).
2-58
4800 bps Data Pump Modem
R48DP
Table 8.
Mnemonic
Name
R48DP Interface Memory Definitions (Continued)
Memory
Location
Description
(None)
RAM Access YS
1 40-7
Contains the RAM access code used In reading or writing chip 1 RAM iocatlons via
word Y (1 1 and 1'0)
(None)
RAM Data XBl
2 2 0-7
least Significant byte of 16·bIt word X used In reading or writing RAM iocatlons In
chip 2
(None)
RAM Data XBM
2:3'0-7
Most significant byte of 16-blt word X used In reading or writing RAM iocatlons in
chip 2.
(None)
RAM Data XSl
1 :2:0-7
least Significant byte of 16-bIt word X used In reading or writing RAM iocatlons In
chip 1.
(None)
RAM Data XSM
1 3:0-7
Most Significant byte of 16-blt word X used In reading or writing RAM iocatlons
chip 1
(None)
RAM Data YBl
2:0 0-7
least Significant byte of 16-bit word Y used in reading or writing RAM iocatlons In
chip 2.
(None)
RAM Data YBM
2:1 0-7
Most significant byte of 16-bIt word Y used In reading or writing RAM locations In
Chip 2.
(None)
RAM Data YSL
1'0:0-7
least Significant byte of 16-bIt word Y used in reading or writing RAM locations
chip 1. Shared by parallel data mode for presenting channel data to the host
microprocessor bus See 'Receiver Data'
(None)
RAM Data YSM
1 1 :0-7
Most Significant byte of 16-bIt word Y used
chip 1
RBDA
Receiver Baud
Data Available
2 E:O
Status bit RBDA goes to a one when the receiver writes data into register 2' O. The bit
goes to a zero when the host processor reads data from register 2: O.
RBIA
Receiver Baud
Interrupt Active
2'E:7
This status bit IS a one whenever the receiver baud rate device IS driving IRQ low. In
Idle mode the Interrupts from chip 2 occur at half the baud rate DUring diagnostic
access In data mode, the Interrupts occur at the baud rate.
RBIE
Receiver Baud
Interrupt Enable
2:E:2
When the host processor writes a one in the RBIE control bit, the iRQ hne of the
hardware interface IS driven to zero when status bit RBDA IS a one.
(None)
Receiver
Configuration
1'6:0-5
The host processor configures the receiver by writing a control code into the receiver
configuration field In the interface memory space (see RSB)
In
Controi codes for the modem receiver configuration are'
22
21
02
01
2-59
In
reading or writing RAM iocations in
Receiver Configuration Control Codes
Configuration Code (Hex)
In
Receiver Configuration
V.27
V 27
V.27
V.27
4800
2400
4800
2400
long
long
Short
Short
R48DP
4800 bps Data Pump Modem
Table 8.
Mnemonic
Name
R48DP Interface Memory Definitions (Continued)
Memory
Location
Description
(None)
Receiver Data
1:0:0-7
The host processor obtains channel data from the receiver in the parallel data mode
by reading a data byte from the receIver data register. The data is divided on baud
boundaries as is the transmitter data When using receiver parallel data mode, the
regIsters 1 : 3 through 1 : 0 can not be used for readIng the chIp 1 RAM.
RPDM
ReceIver Parallel
Data Mode
1'7:4
When control bit RPDM is a one, the receiver supplies channel data to the receiver data
register (1 : 0) as well as to the hardware serial data output. (See Receiver Data)
RSB
Receiver Setup Bit
I:E:3
When the host processor changes the receIver configuration or the RTH fIeld, the host
processor must wnte a one in the RSB control bit. RSB goes to zero when the changes
become effective. Worst case setup time is 2 baud times.
RSDA
Receiver Sample
Data Available
I:E:O
Status bit RSDA goes to a one when the receiver writes data to register 1 : 0 RSDA
goes to a zero when the host processor reads data from register 1 : O.
RSIA
Receiver Sample
Interrupt Active
I:E:7
ThIS status bit is a one whenever the receiver sample rate device IS driving IRQ to zero.
RSIE
ReceIver Sample
Interrupt Enable
I:E:2
When the host processor writes a one in the RSIE control bit, the IRQ line of the
hardware interface is driven to zero when status bit RSDA is a one.
RTDIS
Receiver Training
Disable
1:7:0
When control bit RTDIS Is a one, the receiver is prevented from recognizIng a training
sequence and entering the training state.
RTH
Receiver Threshold
Field
1:7'6,7
The receiver energy detector threshold IS set by the RTH field according to the follOWIng
codes (see RSB):
RTH
RLSD On
RLSD Off
0
1
2
3
>-43dBm
>-33 dBm
>-26 dBm
> -16 dBm
< -48 dBm
< -38 dBm
< -31 dBm
< -21 dBm
RTS
Request·te-Send
0:7:7
When control bIt RTS goes to a one, the modem begins a transmit sequence. It
continues to transmIt until RTS is reset to zero, and the turn-off sequence has been
completed. ThIS input bit parallels the operation of the hardware RTS control input.
These inputs are ORed by the modem.
SDIS
Scrambler DIsable
0:7:5
When control bit SDIS is a one, the transmitter scrambler circuit IS removed from the
data path.
SEPT
Short Echo
Protector Tone
0:7:0
When control bit SEPT is a one, the echo protector tone is 30 ms long rather than
185ms.
SWRT
Sample Write
1'7:3
When control bit SWRT IS a one, the RAM write operation is enabled for chip 1.
TBA
Transmitter Buffer
Available
O:E:O
This status bit resets to zero when the host processor writes data to transmitter data
register 0: O. When the transmitter empties register 0: 0, this bit sets to a one. During a
RAM access in chip 0, when TBA is a one the host can perform eIther a RAM read or
write depending on the state of bit 0: 6: 3 (see Transmitter Configuration).
TIA
Transmitter
Interrupt Active
0:E:7
This status bit is a one whenever the transmitter is driVIng IRQ to a zero.
TIE
Transmitter
Interrupt Enable
0:E:2
When the host processor wntes a one in control bit TIE, the IRQ line of the hardware
Interface is driven to zero when status bit TBA IS at a one.
2·60
R48DP
4800 bps Data Pump Modem
Table 8.
Mnemonic
TLVL
Name
Transmitter Level
Field
R48DP Interface Memory Definitions (Continued)
Memory
Location
0'4:2-4
Description
The transmitter analog output level IS determined by eight TLVL codes. as follows:
TLVL
Transmitter Analog Output"
-1
-3
-5
-7
-9
-11
-13
-15
0
1
2
3
4
5
6
7
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
±1
±1
±1
±1
±1
±1
±1
±1
dB
dB
dB
dB
dB
dB
dB
dB
"Each step above is a 2 dB change ±0.2 dB.
TOD
Train-an-Data
1 :6:6
When control bit TOD IS a one, It enables the train-an-data algorithm to converge the
equalizer if the signal quality degrades sufficiently. When TOD is a one, the modem stili
recognizes a training sequence and enters the force train state. A BER of approximately
10- 3 for 0.5 seconds initiates train-an-date.
TPDM
Transmitter Parallel
Data Mode
0:7:2
When control bit TPDM is a one, the transmitter accepts data for transmission from the
transmitter data register (0' 0) When TPDM is a zero channel data from the serial hardware
Input TXD is accepted.
(None)
Transmtter
Configuration"
0:6'0-7
The host processor configures the transmitter by writing a control byte into the transmitter
configuration register in its interface memory space. (See TSB.)
Transmitter Configuration Control Codes
Control codes for the modem transmitter configurations are:
Configuration Code (Hex)
Transmitter Configuration
22
21
02
01
80
V.27 4800 Long
V.27 2400 Long
V.27 4800 Short
V.27 2400 Short
Tone Transmit
Configuration Definitions
Definitions of the eight Transmitter Configurations are:
1. V.27. When a V.27 configuration has been selected, the modem operates as
specified in CCITT Recommendation V.27 ter.
2. Tone Transmit. In this configuration, activating signal RTS causes the modem to
transmit a tone at a single frequency specified by two registers In the host interface
memory space containing the frequency code The most significant bits are specified
In the FREQM register (0: 3). The least Significant bits are specified in the FREOL
register (0:2). The least significant bit represents 0.146486 Hz ±0.010f0. The frequency
generated IS: f =0.146486 (256 FREOM + FREOL) Hz ±0.010f0.
2-61
R48DP
4800 bps Data Pump Modem
Table 8.
Mnemonic
(None)
Name
Transmitter, DDR
R48DP Interface Memory Definitions (Continued)
Memory
Location
0:0:0-7
Description
The host processor transmits data in the parallel mode by writing a data byte to the
transmitter data register. The data is divided on baud boundaries, as follows:
NOTE
Data IS transmitted bit zero first.
Bits
I
Configuration
7
V.27 4800 bps
Not Used
V.27 2400 bps
Baud 3
6
5
I
4
I
Baud 1
Baud 2
I
3
I
I
2
Baud 1
I
1
I
0
Baud 0
I
Baud 0
TSB
Transmitter Setup
Bit
0:E:3
When the host processor changes the transmitter configuration, the host must write a
one In thiS control bit. TSB goes to a zero when the change becomes effective. Worst
case setup time is 2 baud + turnoff sequence + training (if applicable).
TTDIS
Transmitter Train
Disable
0:7:6
When control bit TTDIS is a one, the transmitter does not generate a training sequence
at the start of transmission. With training disabled, RTS/CTS delay is less than two
baud times.
T2
T/2 Equalizer
1 :7:1
When control bit T2 is a one, an adaptive equalizer with two taps per baud IS used.
When T2 IS a zero, the equalizer has one tap per baud. The total number of taps
remains the same for both cases.
0:7:1
When control bit XCEN is a zero, the transmitter timing is established by the external
clock supplied at the hardware input XTCLK, pin 22A. The clock appearing at the
XTCLK input will appear at the TDCLK output.
Select
XCEN
External Clock
Enable
2-62
R48DP
4800 bps Data Pump Modem
valid RAM location, When the host processor writes into register
1:0 the RSDA bit (1 :E:O) is reset to zero, When the SP logic unit
reads data from register 1:0, the RSDA bit (1 :E:O) is set to a one,
In a similar manner, bit RBDA (2:E:0) resets to zero when the host
processor writes into register 2:0 and sets to a one when the SP
logic unit reads data from register 2:0,
SIGNAL PROCESSOR RAM ACCESS
RAM and Data Organization
Each signal processor contains 128 words of random access
memory (RAM), Each word is 32 bits wide, Because the signal
processor is optimized for performing complex arithmetic, the
RAM words are frequently used for storing complex numbers,
Therefore, each word is organized into a real part (16 bits) and an
imaginary part (16 bits) that can be accessed independently,
The portion of the word that normally holds the real value is
referred to as XRAM, The portion that normally holds the imaginary value is referred to as YRAM, In the sample rate and baud
rate devices the entire contents of XRAM and YRAM may be read
from or written into by the host processor via the microprocessor
interface, No access to the RAM is possible in the transmitter
device,
When reading from RAM, or writing into RAM, the bits in registers 1:E and 2:E can be used for handshaking or interrupt functions as in parallel data mode, When not in parallel data mode,
the bits in register 1:E perform the handshake and interrupt functions for RAM access, In both serial and parallel data modes, the
bits in register 2:E perform handshake and interrupt functions for
RAM access, When set to one, bit RBIE (2:E:2) enables RBDA to
drive the IRQ connector signal to zero volts when RBDA is a one,
Bit RBIA (2:E:7) identifies chip 2, the baud rate device, as a
source of IRQ interrupt. Bit RBIA is a one when both RBIE and
RBDA are set to one, In the event that other system elements may
cause IRQ to be driven low, the host must determine if modem
chip 2 is causing an interrupt by reading RBIA.
Interface Memory
The interface memory acts as an intermediary during these host
to signal processor RAM data exchanges, Information transfer
between RAM and interface memory is accomplished by the signal processor logic unit moving data between the SP main bus
and the SP I/O bus, The SP logiC unit determines the RAM
address to read from or write into by the code stored in the RAM
ACCESS bits of interface memory registers, The SP logic unit
normally transfers a word from RAM to interface memory once
each cycle of the device code, Each RAM word transferred to the
interface memory is 32 bits long, These bits are written by the SP
logic unit into interface memory registers 3, 2, 1, and 0 in that
order, Registers 3 and 2 contain the most and least significant
bytes of XRAM data, respectively, while registers 1 and 0 contain
the most and least significant bytes of YRAM data, respectively,
As previously described for parallel data mode, the data available bits set to a one when register 0 of the respective signal
processor is written into by the device and resets to a zero when
register 0 is read from by the host Since the parallel data mode
receiver data register shares register 0 with the YRAM data, chip
1 RAM access are disabled in parallel data mode, However, chip
2 RAM access remains active In receiver parallel data mode,
Table 9 provides the available RAM access functions, codes, and
registers,
Table 9,
No,
1
2
3
4
5
RAM Access Codes
Function
Received Signal Samples
Demodulator Output
Low Pass Filter Output
Average Energy
AGC Gain Word
6 Equalizer Input
7 EquahzerTap Coefficients
8 Unrotated Eq ualizer
Output
9 Rotated Equalizer Output
(Received Points)
10 Decision Points
I Ideal Points
11 Error
The sample rate device and the baud rate device allow data to be
transferred from interface memory to RAM, When set to a one, bit
SWRT (1 :7:3) signals the chip 1 SP logic unit to suspend transfer
of RAM data to the interface memory, and instead, to transfer
data from interface memory to RAM, Bit BWRT (1 :7:2) performs
the same function for chip 2 RAM, When writing into the RAM, 32
bits are transferred, The 16 bits written into XRAM come from
registers 3 and 2, with register 3 being the more significant byte,
The 16 bits written into YRAM come from registers 1 and 0, with
register 1 being the more significant byte, When only 16 bits of
data are to be written, FF (a dummy RAM location) must be
stored in RAM ACCESS XS or RAM ACCESS YS to prevent writing the insignificant 16 bits of registers 1:3 through 1:0 into a
12 Rotation Angle
~I
1 Frequency Correction
14 EQM
15 Dual Point
2-63
X Access YAccess
Code
Code
(Hex)
(Hex)
Register
Chip
1
1
1
1
1
CO
C2
04
DC
81
Not Used
42
54
Not Used
Not Used
2,3
0,1,2,3
0,1,2,3
2,3
2,3
2
2
CO
81-AO
40
01-20
0,1,2,3
0,1,2,3
2
2
El
A2
61
22
0,1,2,3
0,1,2,3
2
62
0,1,2,3
2
2
2
2
2
E3
Not Used
AA
A7
AE
63
00
Not Used
Not Used
2E
0,1,2,3
0,1
2,3
2,3
0,1,2,3
R48DP
4800 bps Data Pump Modem
PERFORMANCE
TYPICAL PHASE JITTER
TYPICAL BIT ERROR RATES
At 2400 bps, the modem exhibits a bit error rate of 10-6 or less
with a signal-to-noise ratio of 12.5 dB in the presence of 15°
peak-to-peak phase jitter at 150 Hz or with a signal-to-noise ratio
of 15 dB in the presence of 30° peak-to-peak phase jitter at
120 Hz (scrambler inserted).
The Bit Error Rate (BER) performance of the modem is specified
for a test configuration conforming to that specified in CCITT
Recommendation V.56, except with regard to the placement of
the filter used to bandlimit the white noise source. Bit error rates
are measured at a received line signal level of - 20 dBm as
illustrated.
At 4800 bps, the modem exhibits a bit error rate of 10-6 or less
with a signal-to-noise ratio of 19 dB in the presence of 15° peakto-peak phase jitter at 60 Hz.
Typical BER performance is shown in Figure 6. Figure 7 shows a
typical test setup to measure BEA.
4800 BPS
V 27
\400 BPS
V.27
\
4sLps
V.27
1\
2400 BPS
V.27
I
10- 5
~\
\
12
14
16
1\
\
\
,
10
\
\
\
\
\
18
20
22
10
SIGNAL·TO-NOISE RATIO dB
12
14
16
\
16
20
SIGNAL·TO·NOISE RATIO dB
0) TYPICAL BIT ERROR RATE
(BACK TO BACK. T/2 EQUALIZER, - 20 dBm)
Figure 6.
b) TYPICAL BIT ERROR RATE
(UNCONDITIONED 3002 LINE. T/2 EQUALIZER. -20 dBm)
R48DP SER versus SNR
2-64
22
24
R48DP
4800 bps Data Pump Modem
co-
MODEM
TRANSMITTER
~
3002
LINE
SIMULATOR
SEG FA-1445
~
IMPAIRMENT
SOURCE
BRADLEY 2A
AND 2B
f---
ATTENUATOR
HP 3500
I
!
MODEM
TEST SET
PHOENIX
5000
LEVEL
METER
HP 3552A
MODEM
RECEIVER
I
NOTE
SIGNAL AND NOISE ARE MEASURED WITH 3 KHZ FLAT WEIGHTING.
Figure 7. BER Performance Test Set-up
2-65
R48DP
4800 bps Data Pump Modem
GENERAL SPECIFICATIONS
Table 10.
Modem Power Requirements
Voltage
Tolerance
Current (Typical) @ 25°C
Current (Max) @ DOC
+5 Vdc
+ 12 Vdc
-12 Vdc
±5%
±5%
±5%
550 mA
5 mA
25 mA
<700 mA
< 10 mA
< 50 mA
Note: All voltages must have ripple 50.1 volts peak-to-peak.
Table 11.
Modem Environmental Restrictions
Parameter
Tem peratu re
Operating
Storage
Relative Humidity:
Altitude
Specification
O°C to +60°C (32°F to 140°F)
-40°C to +80°C (-40°F to 176°F) (Stored in heat sealed antistatic bag and shipping container)
Up to 90% noncondensing, or a wet bulb temperature up to 35°C, whichever is less.
- 200 feet to + 10,000 feet
Table 12.
Modem Mechanical Considerations
Parameter
DIN Connector Version
Board Structure:
Mating Connector:
Dimensions:
Width
Length
Connector Height
Component Height
Top (max.)
Bottom (max.)
Weight (max):
Lead Extrusion (max.):
DIP Connector Version
Board Structure:
Dimensions:
Width
Length
Component Height
Top (max.)
Bottom (max.)
Weight (max.):
Pin Length (max.)
Specification
Single PC board with a 3-row 64-pin right angle male DIN connector with rows A and C populated.
The modem can also be ordered with the following DIN connector: 64-pm DIN right angle female,
64-pin DIN vertical male or 64-pm DIN vertical female.
Female 3-row 64-pin DIN receptacle with rows A and C populated. Typical receptacle'
Winchester 96S-6043-0531-1, Burndy R196B32ROOAOOZ1, or equivalent.
3.937 in. (100 mm)
4.725 in. (120 mm)
0.437 in. (11.1 mm)
0.200 in. (5.1 mm)
0.130 in. (3.3 mm)
3.6 oz. (100 g)
0.100 In (2.54 mm)
Single PC board with a row of 30 pins and a row of 31 pins in a dual in-line pm configuration.
3.228 in. (82 mm)
3.937 m. (100 mm)
0.200 in. (5.1 mm)
0.130 In. (3.3 mm)
3.6 oz. (100 g)
0.53 in. (13.5 mm)
2-66
R48DP
4800 bps Data Pump Modem
0.156 :I: 0.003 DIA (6 PL)
(3.96)
1/
! !
1
MALE 64-PIN
DIN CONNECTOR
-
1-'
3.937
(100}
-
3 .700
(94)
1
,
0.119
11
-
(3)1
-
~
+-(
.m~_
I+- O. 483
(1 2.3)
4.100 (83)
4.725 (104)
120
0.200 MAX
1::,______________________ ,
t to.~~~~~~-
m
____
m
__
U
____ h
(1.6)
__
0.437
±~
~;.!~
MAX ]
COMPONENT AREA
DIN CONNECTOR VERSION
-I
I
-,--
0.250
(6.4)
0000000 00000000000000 0
000
3.228
(82)
I 3.025
0.098 DIA (3 PL)
(2.5)
iIi
0
0.100~.100 (TYP.)
(2.54)
0.100
(2.54)
(2.54)
3.937
3_
725 _
_.
(94.6)
(100)---~
0.53 MAX
0.025 SQ. PIN
0.200 MAX
rl"'':'==~)(';'
---T;.~;;---------
mm
------"~.130
(1.6)
(3.3)
COMPONENT AREA
DIP CONNECTOR VERSION (PRELIMINARY)
Figure 8.
R48DP Modem Dimensions and Pin Locations
2·67
UNITS: INCHES
R96DP
Integral Modems
'1'
Rockwell
R96DP
9600 bps Data Pump Modem
INTRODUCTION
FEATURES
•
•
•
•
•
•
•
The Rockwell R96DP is a synchronous 9600 bits per second
(bps) modem. It is designed for operation over the public
switched telephone network (PSTN) as well as leased lines
through the appropriate line termination.
The modem satisfies the telecommunications requirements
specified in CCITT recommendations V.29 and V.27 bis/ter. The
R96DP can operate at speeds of 9600, 7200, 4800, and
2400 bps. Employing advanced signal processing techniques,
the R96DP can transmit and receive data even under extremely
poor line conditions.
•
The R96DP is designed for use in point-to-point environments.
User programmable features allow the modem operation to be
tailored to support a wide variety of functional requirements. The
modem's small size,low power consumption, and serial/parallel
host interface simplify system design and allow installation in a
compact enclosure. The modem module is available with a DIN
connector for connection to a mating connector or with dual-inline pins (DIP) for direct plug-in installation onto a host module.
•
•
•
•
•
CCITT V.29, V.27 bis/ter Compatible
Point-to-Point Applications
2-Wire Half-Duplex, 4-Wire Full-Duplex
Programmable Tone Generation
Programmable DTMF Tone Dialer
Dynamic Range: - 43 dBm to 0 dBm
Equalization
- Automatic Adaptive
- Compromise Cable and Link (Selectable)
DTE Interface
- Functional: CCITT V.24 (RS-232-C)(Data/Control) and
Microprocessor Bus (Data/Configuration/Control)
- Electrical: TTL and CMOS Compatible
" Diagnostic Capability
Programmable Transmit Output Level
Loopbacks
- Local and Remote Analog
- Remote Digital
Small Size
- DIN Connector Version:
100 mm x 120 mm (3.94 in. x 4.73 in.)
- DIP Connector Version:
82 mm x 100 mm (3.23 in. x 3.94 in.)
Power Consumption: 3 W (Typical)
R96DP DIN Connector Version
Document No. 29200N07
R96DP DIP Connector Version
Data Sheet
2-68
Order No. MD07
Rev. 3, February 1987
R96DP
9600 bps Data Pump Modem
TECHNICAL SPECIFICATIONS
TRANSMITTER CARRIER FREQUENCIES
.1
SCRAMBLER/DESCRAMBLER
Frequency
(Hz ±0.01%)
Function
Square root of 20 percent
,j
Transmitter Carrier Frequencies
V 27 bls/ter Carner
V 29 Carrier
Square root of 50 percent
The out-of-band transmitter power limitations meet those specIfied by Part 68 of the FCC's rules, and typically exceed the
requirements of foreign telephone regulatory bodies.
The transmitter carner frequencies supported by the R96DP are
listed in Table 1.
Table 1.
2. 1600 Baud.
3. 2400 Baud.
The R96DP incorporates a self-synchronizing scrambler!
descrambler. This facility is in accordance with either V.27 bis!
ter or V.29 depending on the selected configuration.
1800
1700
RECEIVED SIGNAL FREQUENCY TOLERANCE
TONE GENERATION
The receiver circuit of the R96DP can adapt to received frequency error of up to ± 10Hz with less than 0.2 dB degradation in
BER performance.
Under control of the host processor, the R96DP can generate
voice band tones up to 4800 Hz with a resolution of 0.15 Hz and
an accuracy of 0.01 %. Tones over 3000 Hz are attenuated.
DTMF tone transmission capability is provided to allow the
modem to operate as a programmable DTMF tone dialer.
RECEIVE LEVEL
The receiver circuit of the modem satisfies all specified performance requirements for received line signal levels from 0 dBm to
- 43 dBm. The received line signal level is measured at the
receiver analog input (RXA).
SIGNALING AND DATA RATES
The signaling and data rates supported by the R96DP are listed
in Table 2.
Table 2.
TRANSMIT LEVEL
The transmitter output level is accurate to ± 1.0 dB and is programmable from - 1.0 dBm to - 15.0 dBm in 2 dB steps.
Signaling/Data Rates
Bits Per
Data Rate
Symbol
Baud Rate
Specification (Symbols/sec.) Baud (bps)(± 0.01 %) Points
V.29
V.29
V.29
V.27
V.27
2400
2400
2400
1600
1200
4
3
2
3
2
9600
7200
4800
4800
2400
TRAIN ON DATA
16
8
4
8
4
When train on data is enabled, the receiver typically trains on
data in less than 15 seconds for V.29 and 3.5 seconds for V.27.
TURN-ON SEQUENCE
Selectable turn-on sequences can be generated as defined in
Table 3.
DATA ENCODING
The R96DP data encoding conforms to CCITT recommendations V.29 and V.27 bis/ter.
Table 3.
RTS-CTS Turn-On Time
EQUALIZERS
Specification
The R96DP provides equalization functions that improve performance when operating over low quality lines.
V.29 (All data rates)
V.27 4800 bps long
V.27 4800 bps short
V.27 2400 bps long
V.27 2400 bps short
Cable Equalizers - Selectable compromise cable equalizers in
the receiver and transmitter are provided to optimize performance
over different lengths of non-loaded cable of 0.4 mm diameter.
Echo Protector
Tone Disabled
253
708
50
943
67
ms
ms
ms
ms
ms
Echo Protector'
Tone Enabled
438
913
255
1148
272
ms
ms
ms
ms
ms
* For short echo protector tone, subtract 155 ms from RTS-CTS
turn-on time.
Link Equalizers - Selectable compromise link equalizers in the
receiver optimize performance over channels exhibiting severe
amplitude and delay distortion. Two standards are provided: U.S.
survey long and Japanese 3-link.
TURN-OFF SEQUENCE
;-or V.27 ter, the turn-off sequence consists of approximately
10 ms of remaining data and scrambled ones at 1200 baud or
approximately 7 ms of data and scrambled ones at 1600 baud
followed by a 20 ms period of no transmitted energy. For V.29, the
turn-off sequence consists of approximately 5 ms of remaining
data and scrambled ones.
Automatic Adaptive Equalizer - An automatic adaptive equalizer is provided in the receiver circuit. The equalizer can be configured as either a T or a T/2 equalizer.
TRANSMITTED DATA SPECTRUM
If the cable equalizer IS not enabled, the transmitter spectrum is
shaped by the following raised cosine filter functions:
1. 1200 Baud.
Turn-On Sequences
CLAMPING
Received Data (RXD) is clamped to a constant mark (one) whenever the Received Line Signal Detector (RLSD) is off.
Square root of 90 percent
2-69
•
I'
!
R96DP
9600 bps Data Pump Modem
MODEM OPERATION
The interconnect signals on Figure 1 are organized into six groups
of modem operation: overhead signals, V.24 interface signals,
microprocessor interface signals, diagnostic signals, analog signals, and ancillary signals. Table 4 lists these groups along with
their corresponding connector pin numbers. The six groups of hardware circuits are described in the following paragraphs. Table 5 lists
the digital interface characteristics.
Because the modem is implemented in firmware executed by a
specialized computer (the signal processor), operation can best
be understood by dividing this section into hardware circuits and
software circuits. Hardware circuits include all pins on the
modem connector. Software circuits include configuration, control (soft strapping), status, and RAM access routines.
POWER-ON RESET
Basic modem operation can be understood most easily by beginning with the modem configured to default conditions. When the
modem is initially energized a signal called Power-On-Reset
(POR) causes the modem to assume a valid operational state.
The modem drives pin 13C to ground during the beginning ofthe
POR sequence. Approximately 10 ms after the low to high transition of pin 13C, the modem is ready for normal use. The POR
sequence is reinitiated anytime the + 5V supply drops below
+ 3.5V for more than 30 ms, or an external device drives pin 13C
low for at least 3 /ls. When an external low input is applied to
pin 13C, the modem is ready for normal use approximately
10 ms after the low input is removed. Pin 13C is not driven low by
the modem when the POR sequence is initiated externally. In all
cases, the POR sequence requires 50 ms to 350 ms to complete. The R96DP POR sequence leaves the modem configured
as follows:
HARDWARE CIRCUITS
The functional interconnect diagram (Figure 1) shows the
modem connected into a system. In this diagram, any point that
is active when exhibiting the relatively more negative voltage of a
two voltage system (e.g., 0 Vdc for TTL or -12 Vdc for
RS-232-C) is called low active and is represented by association
with a small circle at the signal paint. The particular voltage levels used to represent the binary states do not change the logic
symbol. Two types of I/O points that may cause confusion are
edge-triggered inputs and open-collector (open-source or opendrain) outputs. These Signal paints include the additional notation of a small triangle or a small half-cirde (see signal IRQ),
respectively. Active low signals are named with an overscore
(e.g., PORi. In deciding whether a clock output is high active or
low active, the convention followed is to assume that the clocking
(activating) edge appropriate to the host hardware is a transition
from the clocks active to its inactive state (i.e., a trailing edge
trigger). A clock intended to activate logic on its rising edge is
called low active while a clock intended to activate logic on its
falling edge is called high active. When a clock input is associated with a small circle, the input activates on a falling edge. If
no circle is shown, the input activates on a rising edge.
1"'-------,
RTS
t)
I
USRT
(OPTIONAL)
1
..
~OP~:
I
TXD
.A..,
TDCLK
T
XTCLK
EYEY
RLSD
EYESYNC
h
L---
CTS
• 9600 bps
• Serial channel data
• Tl2 equalizer
• Standard echo protector tone
• - 43 dBm threshold
• Cable and link equalizers disabled
• Train-On-Data disabled
I
RXD
.....
RDCLK
h
R96DP
MODEM
TBCLK~
,,)
xt
EYEX
RBCLK
EYE
PATTERN
GENERATOR
EYECLK
+12V
+5V
POWER
SUPPLY
GND
READ
ty
-12V
WRITE
DATA BUS (8)
HOST
PROCESSOR
(DTE)
ADDRESS BUS (4)
DECODER
~
CS (2)
(
POR
(
IRQ
+5~
TXA
Di
RSi
RXA
LINE
INTERFACE
TELEPHONE
LINE
_ CSi
AUXIN
f.I
-------------------------------------Figure 1.
R96DP Functional Interconnect Diagram
2-70
j
9600 bps Data Pump Modem
R96DP
or RS-232 recommendations since they mark the baud interval
for the transmitter and receiver rather than the data rate. The
baud clocks can be useful in identifying the order of data bits in a
baud (e.g., for multiplexing data, etc.). Both signals are high
active, meaning the baud boundaries occur on falling edges. The
first bit in each baud begins with the failing edge of the corresponding baud clock.
DIAGNOSTIC SIGNALS
EYEX, EYEY, EYECLK, and EYESYNC
Four card edge connections provide the timing and data necessary to create an oscilloscope quadrature eye pattern. The eye
pattern is simply a display of the received baseband constellation. By mOnitoring this constellation, an observer can often identify common line disturbances as well as defects in the modulationl
demodulation process.
SOFTWARE CIRCUITS
The outputs EYEX and EYEY provide two serial bit streams containing data for display on the oscilloscope X axis and Y axis,
respectively. Since this data is in serial digital form it must first be
converted to parallel digital form by two serial-ta-parallel converters and then to analog form by two D/A converters. A clock
for use by the serial-to-parallel converters is furnished by signal
EYECLK. A strobe for loading the D/A converters is furnished by
signal EYESYNC. Timing of these signals is illustrated in Figure 4. The EYEX and EYEY outputs furnish 9-bit serial words.
Since most serial to parallel conversion logic is designed for a-bit
words, an extra storage flip-flop IS required for 9-bit resolution.
However, the ninth bit is not generally needed for eyepattern generation, and eight-bit hardware can be used if data is copied on
the rising edge of EYECLK rather than the falling edge.
Operation of the microprocessor interface circuits was described
in the hardware section from the standpoint of timing and loadl
drive characteristics. In this section, operation of the microprocessor Interface is described from a software standpoint.
The modem is implemented in firmware running on three special
purpose signal processors. These signal processors share the
computing load by performing tasks that are divided into areas.
These areas are partitioned into transm itter, baud rate, and sample rate devices.
INTERFACE MEMORY
Each signal processor can communicate with the host processor
by means of a specialized, dual-port, scratch-pad memory called
interface memory. A set of sixteen a-bit registers, labeled register 0 through register F, can be read from or written into by either
the host processor or signal processor. The host communicates
via the microprocessor interface lines shared between the two
signal processors. The signal processor communicates via its
internal 110 bus. Information transfer from SP RAM to interface
memory is accomplished by the signal processor logic unit moving data between the SP main bus and the SP 110 bus. Two of the
16 addressable interface memory registers (i.e., register 0 and
register E) have unique hardware connections to the interrupt
logic. It is possible to enable a bit in register E to cause an interrupt each time it sets. This interrupt can then be cleared by a read
or write cycle from the host processor to register O. This operation is discussed in detail later in this section.
ANCILLARY SIGNALS
Transmitter Baud Clock (TBCLK) and
Receiver Baud Clock (RBCLK)
Two clock signals called TBCLK and RBCLK are provided at the
modem connector. These signals have no counterpart in the V.24
EYESYNC
Memory maps of the 48 addressable registers in the modem are
shown in Figure 5. These registers may be read or written on any
host read or write cycle, but all eight bits of that register are
affected. In order to read a single bit or a group of bits in a register,
the host processor must mask out unwanted data. When writing
a single bit or group of bits in a register the host processor must
perform a read-modify-write operation. That is, the entire register
is read, the necessary bits are set or reset in the accumulator of
the host, then the original unmodified bits and the modified bits
are written back into the register of the interface memory.
EYEX,
EYEY
LSB
MSB
Figure 4.
Table a defines the individual bits in the interface memory. In the
Table 8 descriptions, bits in the interface memory are referred to
using the format Y:Z:Q. The chip number is specified by Y (0 or
1), the register number by Z (0 through F), and the bit number by
Q (0 through 7, with 0 = LSB).
Eye Pattern Timing
2-71
R96DP
9600 bps Data Pump Modem
Table 4.
Type l
Name
DIN
Pin No.
Dlp2
Pin No.
R96DP Hardware Circuits
Description
Name
A. OVERHEAD:
Ground (A)
Ground (D)
Dlp2
DIN
Type l Pin No. Pin No.
Description
C. V.24 INTERFACE:
AGND
DGND
+5 volts
PWR
+ 12 volts
-12 volts
POR
PWR
PWR
IIOB
31C,32C
30,31
Analog Ground Return
3C,8C, 29,37,53 Digital Ground Return
5A,10A
19C,23C, 1,45,61 + 5 volt supply
26C,30C
15A
32
+ 12 volt supply
12A
36
- 12 volt supply
13C
2
Power·on·reset
RDCLK
TDCLK
XTCLK
RTS
CTS
TXD
RXD
RLSD
DC
DC
IB
IB
DC
IB
DC
DC
21A
23A
22A
25A
25C
24C
22C
24A
23
46
51
50
49
48
26
27
Receive Data Clock
Transmit Data Clock
External Transmit Clock
Request·to·Send
Clear·to·Send
Transmitter Data
Receiver Data
Received Line Signal
Detector
22
47
Receiver Baud Clock
Transmitter Baud Clock
31A
32A
30A
34
33
Transmitter Analog Output
Receiver Analog Input
Auxiliary Analog Input
15C
14A
14C
13A
56
55
57
58
B. MICROPROCESSOR INTERFACE:
07
06
05
04
03
02
01
DO
IIOA
IIOA
IIOA
IIOA
IIOA
IIOA
IIOA
1I0A
lC
lA
2C
2A
3A
4C
4A
5C
3
4
5
6
7
8
9
10
RS3
RS2
RSI
RSO
IA
IA
IA
IA
6C
6A
7C
7A
16
17
18
19
CSO
IA
10C
20
CSI
IA
9C
21
CS2
IA
9A
13
READ
WRITE
IRQ
IA
IA
DB
12C
ItA
llC
14
12
11
)
D. ANCILLARY CIRCUITS:
O~
RBCLK
TBCLK
'"'
I' , ..,
DC
DC
26A
27C
E. ANALOG SIGNALS:
TXA
RXA
AUXIN
AA
AB
AC
-
F. DIAGNOSTIC:
}
Register Select
(4 Bits)
EYEX
EYEY
EYECLK
EYESYNC
Chip Select
Transmitter DeVice
Chip Select Receiver
Sample Rate Device
Chip Select Receiver
Baud Rate Device
Read Enable
Write Enable
Interrupt Request
Table 5.
DC
DC
OA
OA
Eye Pattern
Eye Pattern
Eye Pattern
Eye Pattern
Signal
Data-X Axis
Data-Y Axis
Clock
Synchronizing
Notes:
1. Refer to Table 5 for digital circuit interface characteristics and
Table 7 for analog circuit interface characteristics.
2. Pins not used on the DIP Version: 15, 24, 25, 28, 35, 38, 39,
40,41,42,43,44,52,54,59,60
Digital Interface Characteristics
Input/Output Type
Symbol
Parameter
Units
IA
18
IC
V,H
Input Voltage, High
V
2.0 Min.
2.0 Min.
2.0 Mm.
V,L
VOH
Input Voltage, Low
V
0.8 Max.
0.8 Max.
0.8 Max.
Output Voltage, High
V
VOL
Output Voltage, Low
liN
Input Current, Leakage
p.A
OA
Output Current, High
mA
-0.1 Max.
Output Current, Low
mA
1.6 Max.
IL
Output Current, Leakage
p.A
Ipu
Pull-up Current
(Short Circuit)
p.A
pF
Capacitive Drive
pF
Circuit Type
1 I Load
2 I Load
1108
2.0 Min.
5.25 Max.
2.0 Min.
0.8 Max.
0.8 Max.
2.4 Min.'
2.4 Min.'
0.4 Max. 2
0.4 Max.s
1.6 Max.
1.6 Max.
± 10 Max.
5
-240 Max
-10 Min.
-240 Max.
-10 Min.
5
20
TTL
w/Pull-up
TTL
w/Pull-up
Notes
3. I Load = -40 p.A
4. V,N = 0.4 to 2.4 Vdc, Vee
2-72
-260 Max.
-100 Mm.
-240 Max.
-10 Min.
100
TTL
= -100 p.A
= 1.6 mA
0.4 Max!
110 A
±2.5 Max.'
10H
Capacitive Load
0.4 Max. 2
0.4 Max. 2
±2.5 Max.
10L
Co
OC
2.4 Min.'
V
CL
08
TTL
100
100
10
40
100
100
3-State
Open-Drain
Open-Drain Open-Dram
w/Pull-up Transceiver w/Pull-up
5. I Load
= 5.25 Vdc
= 0.36 mA
R96DP
9600 bps Data Pump Modem
This configuration is suitable for performing high speed data
transfer using the serial data port. Individual features are discussed in subsequent paragraphs.
Received Line Signal Detector (RLSD)
For V.27 bis/ter or V.29, RLSD turns on at the end of the training
sequence. If training is not detected at the receiver, the RLSD offto-on response time is 15 ± 10 ms. The RLSD on-to-off response
time for V.27 is 10 ± 5 ms and for V.29 is 30 ± 9 ms. Response
times are measured with a signal at least 3 dB above the actual
RLSD on the threshold or at least 5 dB below the actual RLSD off
threshold.
V.24 INTERFACE
Eight hardware circuits provide timing, data, and control signals for
implementing a serial interface compatible with CCITI Recommendation V.24. These signals interface directly with circuits using TIL
logic levels (OV, + 5V). These TIL levels are suitable for driving the
short wire lengths or printed circuitry normally found within standalone modem enclosures or equipment cabinets. For driving longer
cables, the voltage levels and connector arrangement recommended by EIA standard RS-232-C are preferred.
The RLSD on-to-off response time ensures that all valid data bits
have appeared on RXD.
Four threshold options are provided:
1. Greater than - 43 dBm (RLSD on)
Less than - 49 dBm (RLSD off)
The sequence of events leading to successful data transfer from
transmitter to receiver is:
2. Greater than - 33 dBm (RLSD on)
Less than - 38 dBm (RLSD off)
1. The transmitter is activated and a training sequence is sent.
3. Greater than - 26 dBm (RLSD on)
Less than - 31 dBm (RLSD off)
2. The receiver detects channel energy above the prescribed
threshold level and synchronizes its operation to the
transmitter.
4. Greater than - 16 dBm (RLSD on)
Less than - 21 dBm (RLSD off)
3. Data transfer proceeds to the end of the message.
NOTE
4. The transmitter turns off after insuring that all data has had
time to be recovered at the receiver output.
Performance may be at a reduced level when the
received signal is less than - 43 dBm.
Transmitted Data (TXD)
A minimum hysteresis action of 2 dB exists between the actual
off-to-on and on-to-off transition levels. The threshold level and
hysteresis action are measured with an unmodulated 2400 Hz
tone applied to the receiver's audio input (RXA).
The modem obtains serial data from the local DTE on this input.
Received Data (RXD)
Transmit Data Clock (TDCLK)
The modem presents received data to the local DTE on this
output.
The modem provides a Transmit Data Clock (TDCLK) output with
the following characteristics:
Request To Send (RTS)
1. Frequency. Selected data rate of 9600, 7200, 4800, or
2400 Hz (±0.01%).
RTS ON allows the modem to transmit data on TXD when CTS
becomes active. The responses to RTS are shown in Table 6.
2. Duty Cycle. 50
Clear To Send (CTS)
TDCLK is provided to the user in synchronous communications
for USRT timing. In this case Transmit Data (TXD) must be stable
during the one fls periods immediately preceding and following
the rising edge of TDCLK.
CTS ON indicates to the terminal equipment that the modem will
transmit any data which are present on TXD. CTS response times
from an ON condition of RTS are shown in Table 6.
External Transmit Clock (XTCLK)
The time between the on-to-off transition of RTS and the on-to-off
transition of CTS in data state is a maximum of 2 band times for
all configurations.
Table 6.
± 1%.
In synchronous communication where the user needs to supply
the transmit data clock, the input XTCLK can be used. The clock
supplied at XTCLK must exhibit the same characteristics of
TDCLK. The XTCLK input is then reflected at TDCLK.
RTS-CTS Response Times
RTS-CTS Turn-On Time
Specification
V.29 (All data rates)
V.27 4800 bps long
V.27 4800 bps short
V.27 2400 bps long
V.27 2400 bps short
Echo Protector
Tone Disabled
253
708
50
943
67
ms
ms
ms'
ms
ms
Receive Data Clock (RDCLK)
Echo Protector"
Tone Enabled
438
913
255
1148
272
The modem provides a Receive Data Clock (RDCLK) output in
the form of a 50 ± 1% duty cycle squarewave. The low-to-high
transitions of this output coincide with the center of received data
bits. RDCLK is provided to the user in synchronous communications for USRTtiming. The timing recovery circuit is capable of
tracking a ± .01 % frequency error in the associated transmit timing source.
ms
ms
ms
ms
ms
• For short echo protector tone, subtract 155 ms from RTS-CTS
turn-on time.
2-73
R96DP
9600 bps Data Pump Modem
to pull the IRQ line high when all IRQ drivers are off (i.e .• it must
overcome the leakage currents). The resistor value should be
large enough to limit the driver sink current to a level acceptable
to each driver. For the case where only the modem IRQ driver is
used. a resistor value of 5.6K ohms ± 20%. 0.25 watt. is
sufficient.
MICROPROCESSOR INTERFACE
Eight hardware circuits provide address. data. control. and interrupt signals for implementing a parallel interface compatible with
an 8080 microprocessor. With the addition of a few external logic
gates. the interface can be made compatible with a wide variety
of microprocessors such as 6500. 6800. or 68000.
ANALOG SIGNALS
The microprocessor interface allows a host microprocessor to
change modem configuration. read or write channel data as well
as diagnostic data. and supervise modem operation by means of
soft strappable control bits and modem status bits. The significance of the control and status bits and methods of data interchange are discussed in a later section devoted to software circuits. This section describes the operation olthe interface from a
hardware standpoint.
The analog Signal characteristics are described in Table 7.
Table 7.
Analog Interface Characteristics
Name
Type
TXA
AA
The transmitter output is S04 ohms ± 1%.
Characteristics
RXA
AB
The receiver input impedance is SOK ohms
AUXIN
AC
The auxiliary analog input allows access to the
transmitter for the purpose of interfacing with
user provided equipment. Because this is a
sampled data input. any Signal above 4800 Hz
will cause aliasing errors. The input impedance
is 1K ohms, and the gain to transmitter output is
the TLVL setting +O.S dB -1.4dB.
±23%.
Chip Select (CSO-CS2) and
Register Selects (RSO-RS3)
The signal processor to be accessed is selected by grounding
one of three unique chip select lines. CS2. CS1 or CSO. The
selected chip decodes the four address lines. RS3 through RSO.
to select one of sixteen internal registers. The most significant
address bit (~) is RS3 while the least significant address bit (20)
is RSO. Once the address bits have been decoded. the selected
register can be read from or written into via an 8-bit parallel data
bus. 07 through DO. The most significant data bit (27) is 07 while
the least significant data bit (20) is DO.
Transmitter Analog (TXA)
The TXA line is an output suitable for driving an audio transformer or data access arrangement for connection to either
leased lines or the public switched telephone network. The output structure of TXA is a low impedance amplifier in series with
an internal 604 ohm ± 1% resistor to match a standard telephone load of 600 ohms.
Read Enable (READ) and
Write Enable (WRITE)
Reading or writing is activated by pulsing either the READ line
high or the WRITE line low. During a read cycle. data from the
selected register is gated onto the data bus by means of threestate drivers. These drivers force the data lines high for a one bit
or low for a zero bit. When not being read. the three-state drivers
assume their off. high-impedance. state. During a write cycle.
data from the data bus is copied into the selected register. with
high and low bus levels representing one bits and zero bits.
respectively. The timing required for correct read/write cycles is
illustrated in Figure 2. Logic necessary to convert the single Rm
output from a 65XX series microprocessor to the separate READ
and WRITE signals required by the modem is shown in Figure 3.
Receiver Analog (RXA)
RXA is an input to the receiver from an audio transformer or
data access arrangement. The input impedance is nominally
60K ohms but a factory select resistor allows a variance of 23%.
The RXA input must be shunted by an external resistor in order to
match a 600 ohm source. A 604 ohm ± 1% resistor is
satisfactory.
Some form of transient protection for TXA and RXA is recommended when operating directly into a transformer. This protection may take the form of back-to-back zener diodes across the
transformer or a varistor across the transformer.
Interrupt Request (IRQ)
The final signal on the microprocessor interface is Interrupt
Request (IRQ). This signal may be connected to the host microprocessor interrupt request input in order to interrupt host program execution for modem service. The use of IRQ is optional
and the method of software implementation is described in a
subsequent section. Software Circuits. The IRQ output structure
is an open-drain field-effect-transistor (FET). This form of output
allows IRQ to be connected in parallel to other sources of interrupt. Any of these sources can drive the host interrupt input low.
and the interrupt servicing process continues until all interrupts
have been cleared and all IRQ sources have returned to their
high impedance state. Because of the open-drain structure of
IRQ. an external pull-up resistor to + 5 volts is required at some
point on the IRQ line. The resistor value should be small enough
Auxiliary Input (AUXIN)
AUXIN provides a means of inserting audio signals into the
modem output stage. Because this input is summed with the
transmitter output prior to the transmitter low pass filter and compromise equalizers. the AUXIN signal is sampled by a compensated sample-and-hold circuit at a rate of 9600 samples-persecond. Any signal above 4800 Hz on the AUXIN line will be
aliased back into the passband as noise. One application for
AUXIN is to inject dual-tone multifrequency (DTMF) touch-tone
signals for dialing. however. the source of these tones must be
well filtered to eliminate components above 4800 Hz. The input
impedance of AUXIN is 1K ohm. The gain from AUXIN to TXA is
the same as the selected transmit level + 0.6 dB - 1.4 dB.
2-74
R96DP
9600 bps Data Pump Modem
WRITE
READ
CSi
(i
= 0,1)
RSi
(i = 0-3)
READ
(i
=
Di
0-7)
Characteristic
CSi, RSi setup time prior
to Read or Write
Data access time after Read
Data hold time after Read
CSi, RSi hold time after
Read or Write
Write data setup time
Write data hold time
Write strobe pulse width
Figure 2.
Symbol
Min
TCS
TDA
TDH
30
TCH
TWDS
TWDH
TWR
10
75
10
75
10
Max
Units
140
50
ns
ns
ns
ns
ns
ns
ns
Microprocessor Interface Timing Diagram
r-______l~2~C~
READ
R96DPMODEM
o-______l_l_AOI
WRITE
R/W
Figure 3.
RlW to
READ WRITE Conversion Logic
2-75
R96DP
9600 bps Data Pump Modem
Transmitter Interface Memory Chip 0 (CSO)
~
7
6
5
E
TIA
-
0
-
B
-
-
A
-
-
9
-
TTOIS
4
2
3
1
0
TBA
Register
F
C
8
7
RAM ACCESS T
-
ATS
TSB
TIE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SOlS
MHlO
EPT
TPDM
XCEN
SEPT
-
-
6
-
-
-
-
TRANSMITTER CONFIGURATION
-
-
5
4
CEO
l3ACT l4ACT
LAEN
l4HG
lDEN
TlVl
3
A3l
D3l
L2ACT
lCEN
FREOM
2
FREOl
1
RAM DATA YTM
0
RAM DATA YTl, TRANSMITTER DATA, DDR
I~
7
5
6
4
3
2
1
0
Bit
(
) Indicates reserved for modem use only.
Receiver Interface Memory Chip 1 (CS1)
~
7
6
5
4
3
2
1
Receiver Interface Memory Chip 2 (CS2)
~
0
Register
7
6
5
-
-
F
-
-
-
-
-
-
-
-
F
-
E
RSIA
-
-
-
RSB
RSIE
E
RBIA
-
-
-
0
-
-
-
0
C
B
A
9
8
7
PNDET
FED
ATH
6
4
3
-
-
-
-
-
-
-
IFIX
DDIS
TOO
-
-
RSDA
-
-
-
-
-
C
B
-
A
-
-
9
-
P2DET
-
CDET
-
-
-
-
8
T2
ATDIS
7
-
-
RPDM SWRT BWRT
-
6
RECEIVER CONFIGURATION
-
-
-
-
-
-
-
-
-
-
-
5
RAM ACCESS XS
5
RAM ACCESS XB
4
RAM ACCESS YS
4
RAM ACCESS YB
3
RAM DATA XSM
3
RAM DATA XBM
2
RAM DATA XSl
2
RAM DATA XBl
1
RAM DATA YSM
1
RAM DATA YBM
0
RAM DATA YSl; RECEIVER DATA
0
RAM DATA YBl
~
2
1
0
Reglste
7
6
5
4
3
2
1
7-
0
Bit
7
6
5
4
3
-
-
RBDA
-
-
-
-
-
-
-
-
-
-
-
-
-
RBIE
-
2
Bit
(
) Indicates reserved for modem use only.
Figure 5.
(-) Indicates reserved for modem use. only.
Interface Memory Map
2-76
1
-
-
-
0
R96DP
9600 bps Data Pump Modem
Table 8.
Mnemonic
Name
Amplitude 3-Unk
SeJect
0:5·1
BWRT
Baud Write
1 :7:2
CEO
Cable Equalizer
Field
A3L
R96DP Interface Memory Definitions
Memory
Location
0:5·4,5
Description
A3L IS used In conjunction with LAEN When A3L IS a one the Japanese 3 link
equalizer IS selected and when A3L is a zero the U.S. Survey Long link equalizer
selected.
When control bit BWRT
IS
a one, the RAM write operation
IS
IS
enabled for Chip 2
The CEO Control field simultaneously controls amplitude compromise equalizers In both
the transmit and receive paths. The following tables list the possible cable equalizer
selection codes and responses
CEQ
Cable Length (0.4 mm diameter)
0
1
2
3
0.0
1.8 km
3.6 km
7.2 km
Cable Equalizer Nominal Gain
CEQ CODE 1
Gain Relative to 1700 Hz (dB)
Frequency
(Hz)
Transmitter
Receiver
700
1500
2000
3000
-0.99
-0.20
+0.15
+1.43
-0.94
-0.24
+0.31
+1.49
CEQ CODE 2
Gain Relative to 1700 Hz (dB)
Frequency
(Hz)
Transmitter
Receiver
700
1500
2000
3000
-2.39
-0.65
+0.87
+3.06
-2.67
-0.74
+1.02
+3.17
CEQ CODE 3
Gain Relative to 1700 Hz (dB)
Frequency
(Hz)
Transmitter
Receiver
700
1500
2000
3000
-3.93
-1.22
+1.90
+4.58
-3.98
-1.20
+1.81
+4.38
Unless a problem with training or high bit error rate is encountered, most applications
operate successfully with no cable equalizer selected.
CDET
Carrier Detector
I:B·O
When zero, status bit CDET indicates that passband energy is being detected, and
that a training sequence is not In process. CDET goes to a zero at the start of the
data state, and returns to a one at the end of the received Signal CDET activates
up to 1 baud time before RLSD and deactivates Within 2 baud times after RLSD. If the
FED bit goes to a zero and no P2 sequence IS detected, the CDET bit goes to zero
within 5 to 25 ms indicating that the receiver has entered the data state Without a
training sequence.
DDIS
Descramble Disable
1 :7:5
When control bit DDIS
data path.
DDR
Dial Digit Register
0·0 0-7
DDR
D3L
Delay 3-Link Select
0:5:0
D3L is used in conjunction with LDEN When D3L IS a one the Japanese 3 link
equalizer IS selected and when D3L IS a zero the U.S. Survey Long link equalizer IS selected.
IS
IS
a one, the receiver descrambler circuit
IS
removed from the
used to tell the modem which DTMF digit to transmit (see Transmitter Data)
2-77
R960P
9600 bps Data Pump Modem
Table 8.
Mnemonic
Nama
R96DP Interface Memory Definitions (Continued)
Memory
Location
Description
EPT
Echo Protector
Tone
0:7:3
When control bit EPT is a one, an unmodulated carrier is transmitted for 185 ms
(optionally 30 ms) followed by 20 ms of no transmitted energy at the start of transmission.
This option is available in the V.27 and V.29 Configurations, although it is not specified
in the CCIIT V.29 recommendation.
FED
Fast Energy
Detector
1 :9:6
When status bit FED is a zero, it indicates that energy above the receiver threshold is
present in the passband, and the receiver is searching for the training sequence
(None)
FREOUFREOM
0:2:0-7,
0:3:0-7
The host processor conveys tone generation data to the transmitter by writing a 16-bit
data word to the FREOl and FREOM registers in the interface memory space, as
shown below:
FREQM Register (0:3)
Bit:
Data Word:
I
I
7
215
I
I
6
214
I
J
I
5
213
j
4
212
I
I
3
211
I
I
I
I
2
2 10
1
29
I
I
0
29
FREQL Register (0: 2)
loata
wo~:; I
6
7
27
I
29
5
I
I
24
2
3
4
25
I
23
I
0
1
I
22
21
I
20
The frequency number (N) determines the frequency (F) as follows:
F = (0.146486) (N) Hz ±0.01%
Hexadecimal frequency numbers (FREOl, FREOM) for commonly generated tones are
given below:
IFIX
Eye Fix
1 :6:7
,
lAEN
Link Amplitude
Equalizer Enable
0:5:3
FREQM
FREQl
Frequency (Hz)
OC
10
2C
31
38
52
55
00
55
00
462
1100
1650
1850
2100
When control bH IFIX is a one, the serial data on EYEX and EYEY reflect the rotated
equalizer output and do not follow the data selected by RAM ACCESS XB and RAM
ACCESS VB.
The link amplitude equalizer enable and select bits control an amplitude compromise
equalizer in the receive path according to the following table:
lAEN
A3L
Curve Matched
0
1
1
X
0
1
No Equalizer
U.S. Survey long
Japanese 3-Link
The link amplitude equalizer responses are given in the following table.
Link Amplitude Equalizer
Frequency
Gain Relative to 1700 Hz (dB)
U.S. Survey long
(Hz)
1000
1400
2000
2400
2800
3000
-0.27
-0.16
+0.33
+1.54
+5.98
+8.65
2·78
Japanesa 3-Llnk
-0.13
-0.08
+0.16
+0.73
+2.61
+3.43
I
R96DP
9600 bps Data Pump Modem
Table 8.
Mnemonic
Name
LCEN
Loop Clock Enable
LDEN
Link Delay
Equalizer Enable
R96DP Interface Memory Definitions (Continued)
Memory
Location
0:40
Description
When control bit LCEN IS a one, the transmItter clock tracks the receIver clock.
The link delay equalizer enable and select bits control a delay compromIse equalizer In
the receive path according to the following table:
LDEN
D3L
Curve Matched
o
X
1
1
1
No Equalizer
U.S Survey Long
Japanese 3-Llnk
o
The link delay equalizer responses are given in the following table.
Link Delay Equalizer
Delay Relative to
1700 Hz (Microseconds)
Frequency
(Hz)
U.S. Survey Long
Japanese 3·Link
800
1200
1600
1700
2000
2400
2800
-498.1
-188.3
-15.1
+0.0
-39.8
-423.1
-672.4
-653.1
-398.5
-30.0
+0.0
+11.7
-117.1
-546.3
L2ACT
Remote DIgital
Loopback ActIvate
0'4:1
When control bit L2ACT IS a one, the receiver digital output IS connected to the
transmitter digItal input in accordance with CCITT recommendation V.54 loop 2
L3ACT
Local Analog
Loopback ActIvate
0'4:7
When control bit L3ACT IS a one, the transmItter analog output IS coupled to the
receIver analog input through an attenuator In accordance with CCITT recommendation
V.54 loop 3.
L4ACT
Remote Analog
Loopback Activate
0:4:6
When control bIt L4ACT IS a one, the receiver analog Input IS connected to the transmItter
analog output through a variable gain amplifier In a manner simIlar to recommendatIon
V.54 loop 4.
L4HG
Loop 4 High Gain
0:4'5
When control bit L4HG is a one, the loop 4 variable gain amplifIer IS set for + 16 dB,
and when at zero the gain is zero dB.
MHLD
Mark Hold
0:7'4
When control bIt MHLD IS a one, the transmItter Input data stream is forced to all marks
(ones).
PNDET
Period N Detector
I'B:6
When status bit PNDET IS a zero, It indIcates a PN sequence has been detected. ThIS
bIt sets to a one at the end of the PN sequence.
P2DET
Period Two
Detector
1 :8:2
When status bit P2DET IS a zero, it indIcates that a P2 sequence has been detected.
ThIS bit sets to a one at the start of the PN sequence.
(None)
RAM Access T
0.F·0-7
Contains the RAM access code used in readmg or writing chIp 0 RAM 10callOns vIa
word V (0'1 and 00)
(None)
RAM Access XB
2:5'0-7
Contains the RAM access code used in reading or writing chIp 2 RAM 10callOns vIa
word X (2:3 and 2.2).
(None)
RAM Access XS
1 :5'0-7
Contains the RAM access code used In reading or writing chip 1 RAM locations vIa
word X (1'3 and 1 :2)
(None)
RAM Access VB
2 4.0-7
Contains the RAM access code used In reading or writIng chip 2 RAM locations via
word V (2:1 and 2:0)
2·79
R96DP
9600 bps Data Pump Modem
Table 8.
Mnemonic
Name
R96DP Interface Memory Definitions (Continued)
Memory
Location
Descrtptlon
(None)
RAM Access YS
1 :4:0-7
Contains the RAM access code used in reading or writing chIp 1 RAM locatIons via
word Y (1: 1 and 1 :0).
(None)
RAM Data XBL
2:2'0-7
Least significant byte of 16·bit word X used on reading or wroting RAM locations In
chip 2.
(None)
RAM Data XBM
2:3:0-7
Most sigmficant byte of 16·bit word X used in reading or wroting RAM locatIons In
chip 2.
(None)
RAM Data XSL
1 :2:0-7
Least significant byte of 16·bIt word X used In readong or writing RAM locatIons on
chip 1.
(None)
RAM DataXSM
1'3:0-7
Most sigmficant byte of 16·bit word X used in reading or wrItIng RAM locations on
chip 1.
(None)
RAM Data YBL
2:0:0-7
Least signifIcant byte of 16·bit word Y used in reading or wroting RAM locations on
chip 2.
(None)
RAM Data YBM
2:1 :0-7
Most significant byte of 16·bit word Y used in reading or writing RAM locatIons on
chIp 2.
(None)
RAM Data YSL
1 :0:0-7
Least significant byte of 16·bit word Y used in reading or writing RAM locations in
chip 1. Shared by parallel data mode for presenting channel data to the host
mIcroprocessor bus. See 'Receiver Data.'
(None)
RAM Data YSM
1 :1:0-7
Most SIgnificant byte of 16-bit word Y used in reading or writing RAM locatIons In
chip 1.
(None)
RAM Data YTL
0.0.0-7
Least significant byte of 16·bIt word Y used on reading or writing RAM locatIons on
chip O. It is shared by parallel data mode and DTMF dialing (see Transmitter Data)
(None)
RAM Data YTM
0: 1 :0-7
Most significant byte of 16-byte word Y used in reading or writing locatIons on chip O.
RBDA
Receiver Baud
Data Available
2:E:0
Status bIt RBDA goes to a one when the receiver writes data into regIster 2: O. The bIt
goes to a zero when the host processor reads data from register 2: O.
RBIA
Receiver Baud
Interrupt Act,ve
2:E:7
This status bit is a one whenever the receiver baud rate device is driVing IRQ low. In
idle mode the interrupts from chip 2 occur at half the baud rate. Durong dIagnostic
access in data mode, the interrupts occur at the baud rate.
RBIE
Receiver Baud
Interrupt Enable
2:E:2
When the host processor writes a one In the RBIE control bit, the IRQ line of the
hardware interface is driven to zero when status bit RBDA is a one
(None)
Receiver
ConfiguratIon
1 :6:0-5
The host processor configures the receiver by writing a control code into the receiver
configuration field in the interface memory space (see RSB).
Receiver Configuration Control Codes
Control codes for the modem receiver configuratIon are:
Configuration Code (Hex)
14
12
11
22
21
02
01
2·80
Receiver Configuration
V.299600
V.297200
V.294800
V.27 4800
V.27 2400
V.27 4800
V.27 2400
Long
Long
Short
Short
R96DP
9600 bps Data Pump Modem
Table 8.
Mnemonic
Name
R96DP Interface Memory Definitions (Continued)
Memory
Location
Description
(None)
ReceIver Data
1'0:0-7
The host processor obtaIns channel data from the receIver In the parallel data mode
by reading a data byte from the receIver data regIster. The dala IS diVIded on baud
boundaries as IS the transmItter data When uSing receIver parallel data mode, the
regIsters 1 3 through 1 : 0 can not be used for reading the chIp 1 RAM
RPDM
ReceIver Parallel
Data Mode
1 74
When control bit RPDM IS a one, the receIver supplies channel data to the receIver data
regIster (1 . 0) as well as to the hardware senal data output (See ReceIver Data)
RSB
Receiver Setup BIt
1 E:3
When the host processor changes the receiver confIguratIon or the RTH fIeld, the host
processor must wnte a one In the RSB control bIt. RSB goes to zero when the changes
become effective. Worst case setup tIme IS 2 baud times
RSDA
Receiver Sample
Data Available
1'E:0
Status bIt RSDA goes to a one when the receIver wntes data to regIster 1 : 0 RSDA
goes to a zero when the host processor reads data from regIster 1 O.
RSIA
Receiver Sample
Interrupt ActIve
1:E 7
This status bit is a one whenever the receIver sample rate deVIce IS dnving IRQ to zero.
RSIE
Receiver Sample
Interrupt Enable
1 :E:2
When the host processor writes a one in the RSIE control bit, the IRQ line of the
hardware Interface is driven to zero when status bit RSDA IS a one
RTDIS
Receiver Training
Disable
1'7:0
When control bit RTDIS IS a one, the receiver is prevented from recognizing a training
sequence and entering the training state.
RTH
ReceIver Threshold
Field
1'7:6,7
The receIver energy detector threshold IS set by the RTH field according to the follOWing
codes (see RSB):
RTH
RLSD On
0
1
2
3
> -43 dBm
> -33 dBm
> -26 dBm
>-16dBm
RLSD Off
<-48
< -38
<-31
<-21
dBm
dBm
dBm
dBm
RTS
Request-te-Send
0'7.7
When control bit RTS goes to a one, the modem begins a transmit sequence. It
continues to transmit untIl RTS IS reset to zero, and the turn-off sequence has been
completed. ThIS Input bit parallels the operatIon of the hardware RTS control Input
These inputs are ORed by the modem.
SDIS
Scrambler Disable
0:7'5
When control bit SDIS IS a one, the transmItter scrambler cIrcuIt IS removed from the
data path.
SEPT
Short Echo
Protector Tone
0:7'0
When control bit SEPT IS a one, the echo protector tone IS 30 ms long rather than
185ms.
SWRT
Sample Write
1'7:3
When control bit SWRT is a one, the RAM write operation IS enabled for chIp 1.
TBA
TransmItter Buffer
AvaIlable
O:E 0
ThIS status bit resets to zero when the host processor writes data to transmItter data
regIster 0: O. When the transmItter emptIes regIster 0.0, thIS bit sets to a one During a
RAM access In chIp 0, when TBA IS a one the host can perform either a RAM read or
write depending on the state of bit 0:6'3 (see Transmitter ConfIguration).
TIA
Transmitter
Interrupt ActIve
0:E'7
This status bit IS a one whenever the transmItter IS dnvlng IRQ to a zero
TIE
Transmitter
Interrupt Enable
0:E'2
When the host processor writes a one in control bit TIE, the IRQ line of the hardware
interface is driven to zero when status bit TBA IS at a one
2-81
R96DP
9600 bps Data Pump Modem
Table 8. R96DP Interface Memory Definitions (Continued)
Mnemonic
TLVL
Name
Transmitter Level
Field
Memory
Location
0:4:2-4
Description
The transmitter analog output level is determined by eight TLVL codes, as follows:
Transmitter Analog Output"
TLVL
-I dBm
-3 dBm
-5 dBm
-7 dBm
-9 dBm
-II dBm
-13dBm
-15dBm
0
I
2
3
4
5
6
7
±I
±I
±I
±I
±I
±I
±I
±1
dB
dB
dB
dB
dB
dB
dB
dB
"Each step above is a 2 dB change ± 0.2 dB.
TOO
Traln-on-Data
1.6:6
When control bit TOO Is a one, it enables the tram-on-data algorithm to converge the
equalizer if the signal quality degrades sufficiently. When TOO is a one, the modem still
recognizes a training sequence and enters the force train state. A BER of approximately
10- 3 for 0.5 seconds initiates train-on-date.
TPDM
Transmitter Parallel
Data Mode
0:7:2
When control bit TPDM Is a one, the transmitter accepts data for transmission from the
transmitter data register (0: 0). When TPDM is a zero channel data from the serial hardware
input TXD is accepted and the chip 0 RAM access is enabled.
(None)
Transmitter
Configuration"
0:6:0-7
The host processor configures the transmitter by writing a control byte into the transmitter
configuration register in its interface memory space. (See TSB.)
Transmitter Configuration Control Codes
Control codes for the modem transmitter configurations are:
Configuration Code (Hex)"
Transmitter Configuration
14
12
II
22
21
02
01
V.29 9600
V.2972OO
V.29 4800
V.27 4800 Long
V.27 2400 Long
V.2748OO Short
V.27 2400 Short
Tone Transm~
DTMF Tone Transmit
80
04
"Note:
Beginning with the R5304-22 device, bit 3 of the transmitter configuration register is
used in the RAM access operation for chip 0 When 0:6:3 is a one, a RAM write
operation will occur when TPDM is a zero, and when 0:6:3 is a zero, a RAM read
operation will occur when TPDM is a zero.
Configuration Definitions
Defin~ions of the eight Transmitter Configurations are:
I. V.29. When a V.29 configuration has been selected, the modem operates as
specified In the CCITT Recommendation V.29.
2. V.27. When a V.27 configuration has been selected, the modem operates as
specified in CCITT Recommendation V.27 ter.
3. Tone Transmit. In this configuration, activating signal RTS causes the modem to
transmit a tone at a single frequency speCified by two registers in the host interface
memory space containing the frequency code. The most significant bits are specified
In the FREQM register (0: 3). The least significant bits are specified in the FREQL
register (0: 2). The least significant bit represents 0.146486 Hz ± 0.01 %. The frequency
generated is: f =0.148486 (256 FREQM + FREQL) Hz ±0.01%.
4. DTMF Tone Transmit. In this configuration when the hex value of a DTMF digit IS
stored in register 0:0, a DTMF tone will be transmitted if RTS is enabled.
2-82
R96DP
9600 bps Data Pump Modem
Table 8.
Mnemonic
(None)
Name
TransmItter; DDR,
RAM Data YTL
R96DP Interface Memory Definitions (Continued)
Memory
Location
00 0-7
Description
1 The host processor transmIts data m the parallel mode by wrltmg a data byte to the
transmItter data regIster The data IS dIvIded on baud boundaries, as follows
NOTE
Data IS transmItted bIt zero first
Bits
Configuration
7
I
6
V.29 9600 bps
5
I
4
Baud 1
V 29 7200 bps
Not Used
V 294600 bps
Baud 3
V.27 4800 bps
Not Used
V.27 2400 bps
Baud 3
I
I
Baud 1
Baud 2
I
3
I
2
I
Baud 1
Baud 1
Baud 2
I
1
I
0
Baud 0
Baud 0
I
Baud 0
Baud 0
I
Baud 1
I
Baud 0
2. RegIster 0 0 IS used to transmit DTMF dIgIts when the transmItter IS confIgured m
the DTMF tone transmit mode.
3. RegIster 0.0 is a RAM data regIster used for reading or wrltmg the least sigmficant
byte of the 16·btt Y word m ChIp 0 when TPDM is a zero and no tone or DTMF tone
transmIssion IS occurring.
TSB
Transmitter Setup
BIt
o E:3
When the host processor changes the transmItter confIguratIon, the host must write a
one m thIS control bIt TSB goes to a zero when the change becomes effectIve. Worst
case setup tIme IS 2 baud + turnoff sequence + tralmng (If applicable).
TIDIS
TransmItter Tram
Disable
0:76
When control bIt TIDIS is a one, the transmItter does not generate a traimng sequence
at the start of transmIssIon. WIth tralmng dIsabled, RTS/CTS delay IS less than two
baud times.
T2
T/2 Equalizer
1 :7:1
When control bIt T2 IS a one, an adaptive equalIzer with two taps per baud is used
When T2 IS a zero, the equalizer has one tap per baud. The total number of taps
remams the same for both cases.
0'7:1
When control bIt XCEN IS a zero, the transmItter tImIng IS established by the external
clock supplied at the hardware Input XTCLK, pin 22A. The clock appearing at the
XTCLK input wIll appear at the TDCLK output
Select
XCEN
External Clock
Enable
2·83
R96DP
9600 bps Data Pump Modem
When reading from RAM, or writing into RAM, the bits in registers O:E, 1:E, 2:E can be used for handshaking or interrupt functions as in parallel data mode. When not in parallel data mode,
the bits in register 1:E perform the handshake and interrupt functions for RAM access. In both serial and parallel data modes, the
bits in register 2:E perform handshake and interrupt functions for
RAM access. When set to one, bit RBIE (2:E:2) enables RBDA to
drive the IRQ connector signal to zero volts when RBDA is a one.
Bit RBIA (2:E:7) identifies chip 2, the baud rate device, as a
source of IRQ interrupt. Bit RBIA is a one when both RBIE and
RBDA are set to one. In the event that other system elements may
cause IRQ to be driven low, the host must determine if modem
chip 2 is causing an interrupt by reading RBIA.
SIGNAL PROCESSOR RAM ACCESS
RAM and Data Organization
Each signal processor contains 128 words of random access
memory (RAM). Each word is 32 bits wide. Because the signal
processor is optimized for performing complex arithmetic, the
RAM words are frequently used for storing complex numbers.
Therefore, each word is organized into a real part (16 bits) and an
imaginary part (16 bits) that can be accessed independently.
The portion of the word that normally holds the real value is
referred to as XRAM. The portion that normally holds the imaginary value is referred to as YRAM. In the sample rate and baud
rate devices the entire contents of XRAM and YRAM may be read
from or written into by the host processor via the microprocessor
interface. Access to the YRAM is possible only in the transmitter
device.
Table 9 provides the available RAM access functions, codes, and
registers.
Interface Memory
Auto Dial Sequence
The interface memory acts as an intermediary during these host
to signal processor RAM data exchanges. Information transfer
between RAM and interface memory is accomplished by the signal processor logic unit moving data between the SP main bus
and the SP 110 bus. The SP logic unit determines the RAM
address to read from or write into by the code stored in the RAM
ACCESS bits of interface memory registers. The SP logic unit
normally transfers a word from RAM to interface memory once
each cycle of the device code. Each RAM word transferred to the
interface memory is 32 bits long (16 bits in the transmitter). These
bits are written by the SP logic unit into interface memory registers 3, 2, 1, and 0 in that order. Registers 3 and 2 contain the
most and least significant bytes of XRAM data, respectively,
while registers 1 and' 0 contain the most and least significant
bytes of YRAM data, respectively. As previously described for
parallel data mode, the data available bits set to a one when
register 0 of the respective signal processor is written into by the
device and resets to a zero when register 0 is read from by the
host. Since the parallel data mode transmitter and receiver data
register shares register 0 with the YRAM data, chip 0 and 1 RAM
access are disabled in parallel data mode. However, chip 2 RAM
access remains active in receiver parallel data mode.
The Figure 6 flowchart defines the auto dial sequence via the
microprocessor interface memory. The modem timing for the
auto dialer accounts for DTMF tone duration and interdigit delay.
The default tone duration is 95 ms and the default interdigit delay
is 71 ms. The default amplitudes for the high and low frequencies
are - 4 dBm and - 6 dBm, respectively. The above four parameters can be changed by performing a RAM write.
liIIble 9.
RAM Access Codes
No.
Function
1 DTMF Low Frequency
XAcceas YAccess
Code
Code
Chip (Hex)
(Hex) Register
0
Ampl~ude'
2 DTMF High Frequency
0
Ampl~ude'
3
4
5
6
7
8
9
10
11
12
The transmitter, sample rate device and the baud rate device
allow data to be transferred from interface memory to RAM.
When set to a one, bit SWRT (1 :7:3) signals the chip 1 SP logic
unit to suspend transfer of RAM data to the interface memory,
and instead, to transfer data from interface memory to RAM. Bit
BWRT (1 :7:2) performs the same function for chip 2 RAM. When
writing into the RAM, 32 bits are transferred. The 16 bits written
into XRAM come from registers 3 and 2, with register 3 being the
more significant byte. The 16 bits written into YRAM come from
registers 1 and 0, with register 1 being the more significant byte.
When only 16 bits of data are to be written, FF (a dummy RAM
location) must be stored in RAM ACCESS XS or RAM ACCESS
YS to prevent writing the insignificant 16 bits of registers 1:3
through 1:0 into a valid RAM location. When the host processor
writes into register 1:0 the RSDA bit (1 :E:O) is reset to zero. When
the SP logic unit reads data from register 1:0, the RSDA bit
(1 :E:O) is setto aone.ln a similar manner, bit RBDA (2:E:0) resets
to zero when the host processor writes into register 2:0 and sets
to a one when the SP logic unit reads data from register 2:0.
13
14
15
16
Interdigit Delay'
DTMFTone Duration'
ReceIVed SIgnal Samples
Demodulator Output
Low Pass Filter Output
Average Energy
AGC Gain Word
Equalizer Input
Equalizer Tap Coefficients
Unrotated Equalizer
Output
Rotated Equalizer Output
(Received POints)
Decision Points
Ideal Points
Error
Rotation Angle
Frequency Correction
EQM
Dual POInt
-
0
0
1
1
1
1
1
DC
81
2
2
CO
al-AO
2
2
2
CO
C2
D4
88
0,1
08
0,1
89
0,1
0,1
09
Not Used
42
2,3
0,1,2,3
0,1,2,3
54
Not Used
2,3
Not Used
2,3
01-20
0,1,2,3
0,1,2,3
A2
61
22
0,1,2,3
0,1,2,3
62
0,1,2,3
El
40
2
E3
0,1,2,3
63
2 Not Used
0,1
00
17
2
AA
Not Used
2,3
18
2
A7
Not Used
2,3
19
2
AE
2E
0,1,2,3
Note: 1. Added in transmitter device R5304-22.
2-84
9600 bps Data Pump Modem
R96DP
TBA (O:E:O) = 1?
Y
Figure 6.
R96DP Auto Dial Sequence
2-85
R96DP
9600 bps Data Pump Modem
PERFORMANCE
TYPICAL PHASE JITTER
TYPICAL BIT ERROR RATES
At 2400 bps, the modem exhibits a bit error rale of 10-6 or less
wilh a signal-la-noise ratio of 12.5 dB in Ihe presence of 15°
peak-la-peak phase jitter al 150 Hz or wilh a signal-la-noise ratio
of 15 dB in Ihe presence of 30° peak-la-peak phase jitter al
120 Hz (scrambler inserled).
The Bit Error Rate (BER) performance of the modem is specified
for a test configuration conforming to that specified in CCITT
Recommendation V.56, except with regard to the placement of
the filter used to bandlimit the white noise source. Bit error rates
are measured at a received line signal level of - 20 dBm as
illustrated.
AI 4800 bps (V.27 bis/ter), the modem exhibits a bil error rale of
10-6 or less wilh a signal-la-noise ratio of 19 dB in Ihe presence of
15° peak-la-peak phase jitter at 60 Hz.
AI 9600 bps, the modem exhlbils a bil error rale of 10-6 or less
with a signal-la-noise ralio of 23 dB in Ihe presence of 10° peakla-peak phase jitter at 60 Hz. The modem exhibits a bil error rale
of 10-5 or less with a signal-la-noise ratio of 23 dB in Ihe presence
of 20° peak-la-peak phase jitter al 30 Hz.
Typical BER performance is shown in Figure 7. Figure 8 shows a
typical test setup to measure BEA.
9600 BPS
V.29
10-'~--~--~---i----t---~--~----tt--~r--
10
SIGNAL-TO-NOISE RATIO dB
24
SIGNAL-TO-NOISE RATIO dB
a) TYPICAL BIT ERROR RATE
(BACK TO BACK, T/2 EQUALIZER, - 20 dBm)
Figure 7,
b) TYPICAL BIT ERROR RATE
(UNCONDITIONED 3002 LINE, TI2 EQUALIZER, - 20 dBm)
R96DP BER versus SNR
2-86
9600 bps Data Pump Modem
R96DP
r-
MODEM
TRAN5MITTER
-
3002
IMPAIRMENT
ATTENUATOR
LINE
SOURCE
'
~
HP 350D
SIMULATOR
BRADLEY 2A
SEG FA·1445
AND 2B
I
J
MODEM
TEST SET
PHOENIX
5000
LEVEL
METER
HP 3552A
MODEM
RECEIVER
I
NOTE
SIGNAL AND NOISE ARE MEASURED WITH 3 KHZ FLAT WEIGHTING.
Figure 8. BER Performance Test Set-up
2·87
9600 bps Data Pump Modem
R96DP
GENERAL SPECIFICATIONS
Table 10.
Voltage
Tolerance
+5 Vdc
+ 12 Vdc
-12 Vdc
±5%
±5%
±5%
Modem Power Requirements
Current (Typical)
@
25°C
550 mA
5 mA
25 mA
Current (Max)
@
aoc
<700 mA
< 10 mA
< 50 mA
Note: All voltages must have ripple s 0.1 volts peak·to·peak.
Table 11.
Modem Environmental Restrictions
Specification
Parameter
Temperature
Operating
Storage
Relative Humidity:
Altitude
DoC to +60°C (32°F to 140°F)
- 40°C to + 80°C (- 40°F to 176°F) (Stored in heat sealed antistatic bag and shipping container)
Up to 90% noncondensing, or a wet bulb temperature up to 35°C, whichever is less.
- 200 feet to + 10,000 feet
Table 12.
Modem Mechanical Considerations
Specification
Parameter
DIN Connector Version
Board Structure:
Mating Connector:
Dimensions:
Width
Length
Connector Height
Component Height
Top (max.)
Bottom (max.)
Weight (max):
Lead Extrusion (max.):
DIP Connector Version
Board Structure:
Dimensions:
Width
Length
Component Height
Top (max.)
Boltom (max.)
Weight (max.):
Pin Length (max.)
Single PC board with a 3·row 64-pin right angle male DIN connector with rows A and C populated.
The modem can also be ordered with the following DIN connector: 64-pin DIN right angle female,
64'pin DIN vertical male or 64-pln DIN vertical female.
Female 3-row 64'pin DIN receptacle with rows A and C populated. Typical receptacle:
Winchester 96S-6043-0531-1, Burndy RI96B32ROOAOOZ1, or equivalent.
3.937 in. (100 mm)
4.725 in. (120 mm)
0.437 In. (11.1 mm)
0.200 in. (5.1 mm)
0.130 in. (3.3 mm)
3.6 oz. (100 g)
0.100 in. (2.54 mm)
Single PC board with a row of 30 pins and a row of 31 pins in a dual in-line pin configuration.
3.228 in. (82 mm)
3.937 In. (100 mm)
0200 In. (5.1 mm)
0130 in. (3.3 mm)
3.6 oz. (100 g)
0.53 in. (13.5 mm)
2-88
R96DP
9600 bps Data Pump Modem
II
!
1
0.156 ± 0.003 DIA (6 PL)
(3.96)
MALE 64-PIN
DIN CONNECTOR
-
T
T~
~r
3.937
(100)
0.496
-
3.700
(94)
'0'
1--(
III
12.6)
I
11
1
,
0.119
(3)1
-
~
M
""~-'
4.100 (83)
~
I--
:§:
~
M
O. 483
(1 2.3)
•
4.725 (104)
120
0.200 MAX
0.437
~:n_n_nm ___ u __ nn: -f~
t to.~~~~~~---m----m---~;.!~MAXJ
---
(1.6)
COMPONENT AREA
DIN CONNECTOR VERSION
-I
3.228
'j~~~
0
0
00
0
0.098 DIA (3 PL)
(2.5)
.J
0.1~0£!.100 (TYP.)
(2.54)
0.100
(2.54)
(2.54)
I
3725
_.
___
3.937
0.53 MAX
(13.6)
_
(94.6)
(100)
0.025 SQ. PIN
~ (61
-
PL)
r
0.200 MAX
(5.1)
rlT:~~~~~~~~~~~~ -~----~-~--- ~~~;~
T
0.062
(1.6)
L~.130
(3.3)
COMPONENT AREA
DIP CONNECTOR VERSION (PRELIMINARY)
Figure 9.
R96DP Modem Dimensions and Pin Locations
2-89
UNITS: INCHES
mm
R96FT
Integral Modems
'1'
Rockwell
R96FT
9600 bps Fast Train Modem
INTRODUCTION
FEATURES
The Rockwell R96FT is a synchronous serial 9600 bps modem
designed for multipoint and networking applications. The R96FT
allows full-duplex operation over 4-wire dedicated unconditioned
lines, or hall-duplex operation over the public switched telephone
network (PSTN).
•
•
•
•
•
•
•
•
•
Proprietary fast train configurations provide training times of
23 ms for V.29FTI960017200/4800, 22 ms for V.27FT/4800, and
30 ms for V.27FT/2400. A 240014800 bps Gearshift configuration provides a training time of 10 ms. For applications requiring
operation with international standards, fallback configurations
compatible with CCITI recommendations V.29 and V.27 bislter
are provided. A 300 bps FSK configuration, compatible with
CCITI V.21 Channel 2, is also provided.
•
The small size and low power consumption of the R96FT offer
the user flexibility in formulating a 9600 bps mo~em design customized for specific packaging and functional requirements.
•
This data sheet corresponds to assembly number
TR96-D400-061 and subsequent revisions.
•
•
•
•
R96FT DIN Connector Version
Document No. 29200N09
Proprietary Fast Train
2400/4800 bps Gearshift
CCITI V.29, V.27 bislter and V.21 Channel 2 Compatible
Train on Data
2-Wire Half Duplex, 4-Wire Full Duplex
Programmable Tone Generation
Dynamic Range - 43 dBm to - 5 dBm
Diagnostic Capability
Equalization:
- Automatic Adaptive
- Compromise Cable and Link (Selectable)
DTE Interface:
- Microprocessor Bus
- CCITI V.24 (RS-232-C Compatible)
Loopbacks
- Local Analog
- Remote Analog and Digital
Small Size
- DIP Connector Version:
120 mmx100 mm (4.73 in. x 3.94 in.)
- DIN Connector Version:
82 mmx100 mm (3.23 in. x 3.94)
Low Power Consumption: 3W (typical)
Programmable Transmit Output Level
TIL and CMOS Compatible
R96FT DIP Connector Version
Data Sheet
2-90
Order No. MD09
Rev. 4, February 1987
R96FT
9600 bps Fast Train Modem
TECHNICAL SPECIFICATIONS
Cable Equalizers - Selectable compromise cable equalizers in
the receiver and transmitter are provided to optimize performance
over different lengths of non-loaded cable of 0.4 mm diameter.
TRANSMITTER CARRIER FREQUENCIES
Function
V.27 bislter Carner
V.27FT Carner
2400/4800 bps Gearshift
V.29 Carrier
V.29FT Carner
V.21 Channel 2:
Mark
Space
Frequency
(Hz ±O.O1%)
link Equalizers - Selectable compromise link equalizers in the
receiver optimize performance over channels exhibiting severe
amplitude and delay distortion. Two standards are provided: U.S.
survey long and Japanese 3-link.
1800
1800
1800
1700
1700/1800'
Automatic Adaptive Equalizer - An automatic adaptive T
equalizer is prOVided In the receiver circuit.
1650
1850
TRANSMITTED DATA SPECTRUM
'Selectable carner frequency
If the cable equalizer is not enabled, the transmitter spectrum
is shaped by the following raised cosine filter functions:
1. 1200 Baud. Square root of 90 percent.
2. 1600 Baud. Square root of 50 percent.
3. 2400 Baud. Square root of 20 percent.
TONE GENERATION
Under control of the host processor, the R96FT can generate
voice band tones up to 4800 Hz with a resolution of 0.15 Hz and
an accuracy of 0.01%. Tones over 3000 Hz are attenuated.
The out-of-band transmitter power limitations meet those
specified by Part 68 of the FCC's rules, and typically exceed
the requirements of foreign telephone regulatory bodies.
SIGNALING AND DATA RATES
Parameter
Specification
Signahng Rate:
Data Rate:
2400
9600
7200
4800
Signaling Rate:
Data Rate:
1800 baud
4800 bps
Signaling Rate·
Data Rate:
Gearshift Data Rate:
Signaling Rate:
Data Rate:
baud
bps
bps
bps
SCRAMBLERIDESCRAMBLER
The R96FT incorporates a self-synchronizing scrambler/
descrambler. This facility is in accordance with either V.27 bislter
or V.29 depending on the selected configuration.
The scrambler/descrambler facilities for Gearshift can be
selected to be in accordance with either V.27 bis/ter or V.29.
The scrambler/descrambler selection is made by writing the
appropriate configuration codes into the transmitter and receiver.
1200 baud
2400 bps
2400/4800 bps
300 baud
300 bps
RECEIVED SIGNAL FREQUENCY TOLERANCE
The receiver circuit of the R96FT can adapt to reCeived
frequency error of up to ± 10 Hz with less than 0.2 dB degradation in BER performance.
DATA ENCODING
At 2400 baud, the data stream is encoded per CCITT V.29. At
9600 bps, the data stream is divided in groups of four-bits (quadbits) forming a 16-point structure. At 7200 bps, the data stream
is divided into three bits (tribits) forming an 8-point structure.
At 4800 bps, the data stream is divided into two bits (dibits)
forming a 4-pOint structure.
During fast train polling, frequency offset must be less than
±2 Hz for successful training.
RECEIVE LEVEL
At 1600 baud, the 4800 bps data stream is encoded Into tribits
per CCITT V.27 bis/ter.
The receiver circuit of the modem satisfies all specified performance requirements for received line signal levels from -5 dBm
to -43 dBm. The received line signal level is measured at the
receiver analog input (RXA).
At 1200 baud, the 2400 bps data stream is encoded into dibits
per CCITT V.27 bislter.
For the Gearshift configuration, the signaling rate is 1200 baud.
The 2400 bps data stream is encoded into dibits forming a 4-point
structure, and the 4800 bps data stream is encoded into quadbits forming a 16-point structure. The first 32 bauds of data are
transmitted at 2400 bps and the remaining message is transmitted at 4800 bps.
RECEIVE TIMING
The R96FT provides a data derived Receive Data Clock (RDCll<)
output in the form of a squarewave. The low-te-high transitions
of this output coincide with the centers of received data bits.
For the Gearshift configuration, the first 32 bauds of data are
at 2400 bps followed by 4800 bps data for the remaining
message. The timing recovery circuit is capable of tracking a
± 0.01 % frequency error in the associated transmit timing
source. RDCLK duty cycle is 50% ± 1%.
At 300 baud, the 300 bps data stream is encoded per CCITT V.21
Channel 2 into a mark frequency of 1650 Hz and a space frequencyof 1850 Hz.
EQUALIZERS
TRANSMIT LEVEL
The R96FT provides equalization functions that improve performance when operating over low quality lines.
The transmitter output level is accurate to ± 1.0 dB and is programmable from - 1.0 dBm to - 15.0 dBm in 2 dB steps.
2-91
R96FT
9600 bps Fast Train Modem
TRANSMIT TIMING
20 ms period of no transmitted energy (V.27 bis/ter only). For
V.29 and V.29FT, the turn-off sequence consists of approximately 8 ms of remaining data and scrambled ones.
The R9EiFT provides a Transmit Data Clock (TDCLK) output with
the following characteristics:
1. Frequency. Selected data rate of 9600, 7200, 4800, 2400 or
300 Hz (± 0.01 %). For the Gearshift Configuration, TDCLK
is a 2400 Hz clock for the first 32 bauds of data, and a
4800 Hz clock for the remaining message.
2. Duty Cycle. 50% ± 1%
CLAMPING
Received Data (RXD) is clamped to a constant mark (one) when
the Received Line Signal Detector (RLSD) is off.
RESPONSE TIMES OF CLEAR TO SEND (CTS)
Input data presented on TXD is sampled by the R96FT at the
low-ta-high transition of TDCLK. Data on TXD must be stable
for at least one microsecond prior to the riSing edge of TDCLK
and remain stable for at least one microsecond after the rising
edge of TDCLK.
The time between the off-to-on transition of Request To Send
(RTS) and the off-ta-on transition of Clear to Send (CTS) is
dictated by the length of the training sequence and the echo
protector tone, if used. These times are given in the Turn-On
Sequences table. If training is not enabled, RTS/CTS delay
is less than 2 baud times.
EXTERNAL TRANSMIT CLOCK
The transmitter data clock (TDCLK) can be phase locked to a
signal on input XTCLK. This input signal must equal the desired
data rate ±0.01% with" a duty cycle of 50% ±20oAl.
The time between the on-to-off transition of RTS and the on-tooff transition of CTS in the data state is a maximum of 2 baud
times for all configurations.
TRAIN ON DATA
RECEIVE LINE SIGNAL DETECTOR (RLSD)
When train on data is enabled (by setting a bit in the interface
memory), the modem monitors the EQM signal. If EQM indicates
a loss of equalization (Le., BER approximately 10- 3 for
0.5 seconds) the modem attempts to retrain on the data stream.
The time for retrain is typically 3 to 15 seconds.
Response
For Fast Train and Gearshift configurations, the receiver enters
the training state upon detecting a significant increase in the
received signal power. If the received line signal power is greater
than the selected threshold level at the end of the training state,
the receiver enters the data state and RLSD is activated. If the
received line signal power is less than the selected threshold
level at the end of the training state, the receiver returns to the
idle state and RLSD is not activated.
TURN·ON SEQUENCE
A total of 20 selectable turn-on sequences can be generated
as defined in the following table:
blslter
(bps)
RT8-CTS
Gearshift Response Time
(bps)
(milliseconds) Comments
FT/4800
FT/2400
23
24
23'
22
30
V.27
V.29
No.
(bps)
1 FT/9600
2 FT17200
3 FT/4900
4
5
6
7
8
9
10
11
12
13
9600
7200
4800
14
15
16
17
18
19
20
9600
7200
4800
4800
2400
4900
2400
Also, in Fast Train and Gearshift configurations, the receiver
initiates the turn-off delay upon detecting a significant decrease
in the received signal power. If the received signal power is less
than the selected threshold at the end of the turn-off delay, the
receiver enters the idle state and RLSD is deactivated. If the
received signal power is greater than the selected threshold at
the end of the turn-off delay, the receiver returns to the data state
and RLSD is left active.
Proprietary
Fast Train
253
253
253
708
long
long
short
short
For CCIIT configurations, the receiver enters the training
detection state when the received line signal power crosses the
selected threshold level. RLSD is activated at the end of the
training sequence. For V.21 Channel 2, a separate received line
Signal detector (FRLSD) is provided. FRLSD is activated when
energy above - 43 dBm is present at the receiver's audio input
(RXA). The FRLSD off-to-on response time is 15 ±5 ms and
the on-to-off response time is 25 ± 5 ms.
943
2400/4800
4800 long
2400 long
4900 short
2400 short
50
67
10
438
438
438
913
1148
255
272
Preceded'
by Echo
Protector
Tone for
lines using
echo
suppressors.
The RLSD on-to-off response times are:
1. For short echo protector tone, subtract 155 ms from values of
RTS-CTS response time.
2. V.21 (300 bps FSK) RTS-CTS response time is <35 ms.
TURN·OFF SEQUENCE
For V.27 bis/ter, V.27FT and 2400/4800 bps Gearshift
configurations, the turn-off sequence consists of approximately
10 ms of remaining data and scrambled ones followed by a
Configuration
RLSO On-To-Off
Response Time (ms)
V.29 Fast Train
V.27 Fast Train
Gearshift
V.29
V.27 bis/ter
6.5 ±1
8 ±1
6 ±1
30 ±9
10 ±5
RLSD response times are measured with a signal at least 3 dB
above the actual RLSD on threshold or at least 5 dB below the
actual RLSD off threshold.
2-92
9600 bps Fast Train Modem
R96FT
...,
r
I
I
I
I
I
I
RTS
C
0SCOPE
CTS
xt ty
TXO
A--.
USRT
(OPTIONAL)
I
I
I
L __ -
HOST
PROCESSOR
(DTE)
r
.
TDCLK
XTCLK
RLSD
RXD
RDCLK
TBCLK
"':
~
A
i
EYEX
EYEY
EYECLK
RBCLK
.J
EYE
PATTERN
GENERATOR
EYSYNC
MODEM
+12V
+5V
POWER
SUPPLY
GND
-12V
READ
WRITE
DATA BUS (8)
ADDRESS BUS (4\..
IDECODER
CS (3)
TXA
Di
RXA
RSi
LINE
- -}
INTERFACE __
TELEPHONE
LINE
AUXIN
CSi
POR
IRQ
+5~
R96FT Functional Interconnect Diagram
Threshold Options
MODE SELECTION
Four threshold options are provided:
For the transmitter, a control bit determines whether the source
of transmitted data is the V.24 interface (serial mode) or the
parallel transmitter data register (parallel mode). The transmitter
automatically defaults to the serial mode at power-on.
1. Greater than - 43 dBm (RLSD on)
Less than - 48 dBm (RLSD off)
2. Greater than - 33 dBm (RLSD on)
Less than - 38 dBm (RLSD off)
The receiver simultaneously outputs received data via the V.24
interface and the parallel receiver data register.
3. Greater than - 26 dBm (RLSD on)
Less than - 31 dBm (RLSD off)
In either parallel or serial mode, the R96FT is configured by the
host processor via the microprocessor bus.
4. Greater than -16 dBm (RLSD on)
Less than - 21 dBm (RLSD off)
NOTE
Performance may be at a reduced level when the received
signal is less than -43 dBm.
INTERFACE CRITERIA
The modem interface comprises both hardware and software
circuits. Hardware circuits are assigned to specific pins in a
64-pin DIN connector. Software circuits are assigned to specific
bits in a 4B-byte interface memory.
For CCID configurations, a minimum hysteresis action of 2 dB
exists between the actual off-to-on and on-to-off transition levels.
The threshold levels and hysteresis action are measured with
unmodulated 2100 Hz tone applied to the receiver's audio input
(RXA).
HARDWARE CIRCUITS
Signal names and descriptions of the hardware circuits, including
the microprocessor interface, are listed in the R96FT Hardware
Circuits table. In the table, the column titled 'Type' refers to
designations found in the Hardware Circuit Characteristics. The
microprocessor interface is designed to be directly compatible
with an 8080 microprocessor. With the addition of a few external
logic gates, it can be made compatible with 6500, 6800, or
68000 microprocessors.
MODES OF OPERATION
The R96FT is capable of being operated in either a serial or a
parallel mode of operation.
SERIAL MODE
The serial mode uses standard V.24 (RS-232-C compatible) signals to transfer channel data. An optional USRT device (shown
in the Functional Interconnect Diagram) illustrates this capability.
Eye Pattern Generation
The four hardware diagnostic circuits, identified in the following table, allow the user to generate and display an eye pattern.
Circuits EYEX and EYEY serially present eye pattern data for
the horizontal and vertical display inputs respectively. The B-bit
data words are shifted out most significant bit first, clocked by the
PARALLEL MODE
The R96FT has the capability of transferring channel data (up
to eight bits at a time) via the microprocessor bus.
2-93
R96FT
9600 bps Fast Train Modem
Microprocessor Timing
rising edge of the EYECLK output. The EYESYNC output is provided for word synchronization. The falling edge of EYESYNC
may be used to transfer the 8-bit word from the shift register
to a holding register. Digital to analog conversion can then be
performed for driving the X and Y inputs of an oscilloscope.
READ
WRITE
CSi
(i = 0-2)
R96FT Hardware Circuits
Name
Type
DIN
Pin No.
DIP
Pin No.
Description
RSi
A. OVERHEAD:
(i
Ground (A) AGND
31C,32C
30,31 Analog Ground Return
Ground (D) DGND 3C,8C,5A, 1OA 29,37,53 Digital Ground Return
PWR
+5 volts
19C,23C,
1,45,61 + 5 Vdc Supply
26C,30C
+ 12 volts PWR
15A
32
+ 12 Vdc Supply
-12 volts PWR
12A
36
- 12 Vdc Supply
13C
2
Power-on-reset
POR
IIOB
= 0-3)
B. MICROPROCESSOR INTERFACE:
D7
D6
D5
D4
D3
D2
D1
DO
IIOA
I/OA
IIOA
IIOA
IIOA
I/OA
I/OA
IIOA
1C
1A
2C
2A
3A
4C
4A
5C
RS3
RS2
RSI
RSO
IA
IA
IA
IA
6C
6A
7C
7A
CSO
IA
10C
20
CS1
IA
9C
21
CS2
IA
9A
13
IA
IA
DB
12C
11A
11C
14
12
11
21A
23A
22A
25A
25C
24C
22C
24A
23
46
51
50
49
48
26
27
Receive Data Clock
Transmit Data Clock
External Transmit Clock
Request to Send
Clear to Send
Transmitter Data
Receiver Data
Received Line Signal
Detector
22
Receiver Baud Clock
Transmitter Baud Clock
FSK Receiver Data
(inverted data)
FSK Received Line
Signal Detector
READ
WRITE
IRQ
II
READ
Data Bus (8 Bits)
Di
(i
17
16}
Register Select (4 Bits)
18
Microprocessor Interface Timing Diagram
19
Chip SelectTransmitter Device
Chip Select-Receiver
Sample Rate Device
Chip Select-Receiver
Baud Rate Device
Read Enable
Write Enable
Interrupt Request
Critical Timing Requirements
Characteristic
C. V.24 INTERFACE:
RDCLK
TDCLK
XTCLK
RTS
CTS
TXD
RXD
RLSD
DC
DC
IB
IB
DC
IB
DC
DC
DC
DC
00
26A
27C
16A
47
60
FRLSD
OD
17C
44
AA
31A
34
RXA
AUXIN
AB
AC
32A
30A
33
15C
14A
14C
13A
56
55
57
58
-
Transmitter Analog
Output
Receiver Analog Input
Auxiliary Analog Input
F. DIAGNOSTIC:
EYEX
EYEY
EYECLK
EYESYNC
DC
DC
OA
OA
Min
TCS
30
Data access time after Read
TDA
-
Data hold time after Read
TDH
10
50
nsec
-
nsec
TCH
10
Write data setup time
TWOS
75
Write data hold time
TWDH
10
TWR
75
Write strobe pulse width
E. ANALOG SIGNALS:
TXA
Symbol
CSi, RSi setup time prior
to Read or Write
CSi, RSi hold time after
Read or Write
D. ANCILLARY CIRCUITS:
RBCLK
TBCLK
FRXD
= 0-7) ---~"
Eye Pattern Data-X Axis
Eye Pattern Data-Y Axis
Eye Pattern Clock
Eye Pattern
Synchronizing Signal
NOTE: PinS not used on the DIP Version: 15, 24, 25, 28. 35,
38-43, 52. 54 and 59.
2-94
Max
Units
-
nsec
140
nsec
-
nsec
nsec
nsec
R96FT
9600 bps Fast Train Modem
Digital Interface Characteristics
Digital Interface Characteristics
Input/Output Type
Symbol
VIH
Parameter
IA
IB
IC
V
2.0 Min.
2.0 Mm
2.0 Min.
08 Max.
0.8 Max
0.8 Max.
Units
Input Voltage, High
VIL
Input Voltage, Low
V
VOH
VOL
liN
Output Voltage, High
Output Voltage, Low
V
V
Input Current,
Leakage
~A
OA
Output Current, High
rnA
-0.1 Max.
rnA
1.6 Max.
Ipu
Pull-up Current
(Short Circuit)
~A
CL
Capacitive Load
pF
Co
Capacitive Dnve
pF
= -100 ~A
= 1.6 rnA
1/0 A
IIOB
20 Min.
5.25 Max
2.0 Min.
0.8 Max.
2.4 Mm.3
04 Max 2 0.4 Max. 2
6
0.6 Max.7
24 Mm'
0.4 Max. 2
0.4 Max. 5
±25 Max.'
Output Current, Low
Notes 1. I Load
2. I Load
2.2 Min
±25 Max.
10H
Circuit Type
00
OC
0.8 Max.
2.4 Mm.'
0.4 Max 2
10L
IL
Output Current,
Leakage
OB
~A
1.6 Max.
1.6 Max.
±10 Max.
-240 Max. -240 Max.
-10 Mm. -10 Min.
5
5
-240 Max.
-10 Min.
20
10
100
TTL
TTL
w/Pull-up
-260 Max.
-100 Min.
TTL
w/Pull-up
3. I Load = -40~
4. VIN = 0.4 to 2.4 Vdc, Vee
TTL
= 5.25 Vdc
Analog Interface Characteristics
Name
Type
AA
The transmitter output Impedance is 604 ohms ± 1%.
RXA
AB
The receiver input Impedance is 60K ohms
±23%.
AUXIN
AC
The auxiliary analog input allows access to the
transmitter for the purpose of interfacing with
user provided equipment. Because this IS a
sampled data input, any signal above 4800 Hz
will cause aliasing errors. The mput impedance is
1K ohms, and the gain to transmitter output IS
TLVL setting + 0.6 dB -1.4 dB. If unused, this
mput must be grounded near the modem
connector. If used, It must be dnven from a low
impedance source.
100
Open-Drain Open-Drain
w/Pull-up
5. I Load
6. I Load
= 0.36 rnA
= -400 ~A
100
TTL
40
100
3-State Open-Drain
ranscelver w/Pull-up
7. I Load
= 2.0 rnA
Status Control Bits
Analog Interface Characteristics
TXA
100
The operation of the R96FT is affected by a number of software
control inputs_ These inputs are written into registers within the
interface memory via the host microprocessor bus. Modem
operation is monitored by various software flags that are read
from interface memory via the host microprocessor bus. All status
and control bits are defined in the Interface Memory table. Bits
designated by a dash (-) are reserved for modem use only and
must not be changed by the host.
Characteristics
RAM Data Access
The R96FT provides the user with access to much of the data
stored in the modem's memories. This data is useful for performing certain diagnostic functions.
Two RAM access registers in chip 2 allow user access to RAM
locations via the X word registers (2:3 and 2:2) and the Y word
register (2:1 and 2:0). The access code stored in RAM ACCESS
X (2:5) selects the source of data for RAM DATA XM and RAM
DATA XL (2:3 and 2:2). Similarly, the access code stored in RAM
ACCESS Y (2:4) selects the source of data for RAM DATA YM
and RAM DATA YL (2:1 and 2:0).
SOFTWARE CIRCUITS
The R96FT comprises three signal processor chips. Each of
these chips contains 16 registers to which an external (host)
microprocessor has access. Although these registers are within
the modem, they may be addressed as part of the host
processor's memory space. The host may read data out of or
write data into these registers. The registers are referred to as
interface memory. Registers in chip 1 update at half the modem
sample rate (4800 bps). Registers in chip 0 and 2 update at the
selected baud rate.
Reading of diagnostic RAM data is performed by storing the
necessary access codes in 2:5 and 2:4, reading 2:0 to reset the
associated data available bit (2:E:0), then waiting for the data
available bit to return to a one. Data is now valid and may be
read from 2:3 through 2:0.
An additional diagnostic is supplied by the sample rate processor (chip 1). Registers 1:2 and 1:3 supply a 16 bit AGC Gain
Word. These two diagnostic data registers are updated at the
sample rate during the data state and may be read by the host
processor asynchronously.
When information in these registers is being discussed, the
format Y:Z:O is used. The chip is specified by Y(0-2), the register
by Z(O-F), and the bit by 0(0-7, 0 = LSB).
2-95
9600 bps Fast Train Modem
R96FT
RAM Access Codes
Transmitter Interface Memory Chip 0 (CSO)
:~
The RAM access codes defined in the following table allow the
host processor to read diagnostic information within the modem.
Baud Rate Processor (Chip 2) RAM Access Codes
No.
Function
1
2
3
4
5
Equalizer Input
Equalizer Tap Coefficients
Un rotated Equalizer Output
Rotated Equalizer Output
Decision Points
(Ideal Data Points)
Error Vector
Rotation Angle
Frequency Correction
Eye Quality Monitor (EQM)
6
7
8
9
7
6
5
4
3
-
-
-
2
1
0
-
-
TSB
TIE
-
TBA
Register
X Access Y Access Register
CO
81-AO
E1
E2
E8
40
01-20
61
62
68
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
E5
A7
A5
AC
65
Not Used
Not Used
Not Used
0,1,2,3
2,3
2,3
2,3
F
-
-
E
TIA
0
-
-
C
B
A
-
FSKT ASCR
9
8
-
7
RTS
-
-
-
-
-
TCF
DDEE
-
-
-
-
-
TTDIS SDIS MHLD
-
-
-
~
-
EPT TPDM XCEN SEPT
TRANSMITTER CONFIGURATION
6
-
5
-
LAEN LDEN
CEQ
L3ACT L4ACT L4HG
4
TLVL
A3L
D3L
L2ACT LCEN
FREQM
3
FREQL
2
-
1
-
-
-
-
-
-
-
1
0
TRANSMITTER DATA
0
~
7
6
5
4
3
2
Bit
NOTE
(-) indicates reserved for modem use only.
Receiver Interface Memory Chip 2 (CS2)
Receiver Interface Memory Chip 1 (CS1)
I~
7
6
5
4
2
3
1
~
0
Registe
F
-
E
RIA
0
-
-
-
-
B
-
A
-
-
9
-
FED
-
-
8
-
-
C
7
6
5
4
3
-
-
2
1
0
-
-
-
RBIE
RBDA
-
-
-
Register
7
RTH
6
TOD
5
-
DO IS
-
-
-
-
F
-
-
RSB
RIE
-
RDA
E
RBIA
-
-
-
0
-
-
-
-
-
-
-
-
CDET
-
P2DET
-
-
-
-
RCF
RDIS
-
8
-
7
-
6
-
-
5
RAM ACCESS X
B
A
9
RECEIVER CONFIGURATION
-
-
-
-
-
-
-
-
C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
1
0
-
-
4
RAM ACCESS Y
AGC GAIN WORD (MSB)
3
RAM DATAXM
2
AGC GAIN WORD (LSB)
2
RAM DATA XL
1
RAM DATA YM
0
RAM DATA YL
-
1
-
-
-
-
-
-
-
RECEIVER DATA
0
~
7
6
5
4
3
2
1
~
0
Bit
7
6
5
4
3
Bit
NOTE
(-) indicates reserved for modem use only.
NOTE
(-) indicates reserved for modem use only.
2-96
-
-
3
4
-
-
-
-
!I
i;
9600 bps Fast Train Modem
R96FT
R96FT Interface Memory Definitions
Mnemonic
Name
Memory
location
Description
ASCR
Append Scrambled
Ones
0:9:6
When control bit ASCR IS a one, one baud of scrambled marks IS included in the
V.29FT and V.27FT training sequences. The RTS·CTS delay IS thus extended by one
baud penod when ASCR is a one.
A3l
Amplitude 3-Link
Select
0:5:1
See LAEN.
Carrier Detector
1 :9:2
When zero, status bit CDET indicates that passband energy is being detected, and
that a training sequence is not in process. CDET goes to a zero at the start of the
data state, and returns to a one at the end of the received signal. CDET activates up to
1 baud time before RlSD and deacllvates within 2 baud times after RlSD.
Cable Equalizer
Field
0:5:(4,5)
The CEQ Control field simultaneously controls amplitude compromise equalizers In both
the transmit and receive paths. The following table lists the possible cable equalizer
selection codes:
CEQ
CEQ
Cable length (0.4 mm diameter)
o
0.0
1.8km
3.6 km
7.2 km
1
2
3
DDEE
Digital Delay
Equalizer Enable
0:9:2
When control bit DDEE is a one, a fourth order digital delay equalizer IS inserted
transmit path.
DDIS
Descramble Disable
1 :7:5
When control bit DDIS is a one, the receiver descrambler cirCUit is removed from the
data path.
D3l
Delay 3·Link Select
0:5:0
See LDEN.
EPT
Echo Protector
Tone
0:7:3
When control bit EPT is a one, an unmodulated carrier is transmitted for 185 ms
(optionally 30 ms) followed by 20 ms of no transmitted energy at the start of
transmission. This option is available in the V.27 and V.29 configurations, although It is
not specified in the CCITT V.29 Recommendation.
Fast Energy
Detector
1 :9:6
When status bit FED IS a zero, It indicates that energy above the receiver threshold IS
present in the passband.
FREQLlFREQM
0:2:0-7,
0:3:0-7
The host processor conveys tone generation data to the transmitter by writing a 16·blt
data word to the FREQl and FREQM registers in the interface memory space, as
shown below:
(None)
In
the
FREQM Register (0:3)
1
B~I
IData Word:
I
7
2'5
1
.1
6
1
5
1
4
1
3
2'4
I
213
1
2'2
1
2"
1
2
1
12 1
1
1
o
1
1
o
1
'0
FREQL Register (0:2)
Bit: 1
7
1
6
1
5
1
4
1
IData Word: 1
27
1
26
1
25
1
24
1
1
3
1
2
1
22
1
2'
1
The frequency number (N) determines the frequency (F) as follows:
F = (0.146486) (N) Hz ±0.01%
Hexadecimal frequency numbers (FREQl, FREQM) for commonly generated tones are
given below:
FSKT
FSK Transmitter
I Configuration
0:9:7
Frequency (Hz)
FREQM
FREQl
462
1100
1650
1850
2100
OC
52
55
00
55
00
10
2C
31
38
The V.21 Channel 2 (300 bps synchronous FSK) transmitter configuration is selected by
setting the FSKT control bit to a one (see TS8). While set to a one, thiS control bit over·
rides the configurallon selected by the control code In register 0:6. The FSK data may
be transmitted in parallel mode or in serial mode (see TPDM).
2·97
I~
!
9600 bps Fast Train Modem
R96FT
R96FT Interface Memory Definitions (Continued)
Mnemonic
LAEN
Name
Link Amplitude
Equalizer Enable
Memory
Location
0:5:3
Description
The link amplitude equalizer enable and select bits control an amplitude compromise
equalizer in the receive path according to the following table:
lAEN
0
1
1
A3l
X
0
1
Curve Matched
No Equalizer
U.S. Survey Long
Japanese 3-Lmk
LCEN
Loop Clock Enable
0:4:0
When control bit LCEN is a one, the transmitter clock tracks the receiver clock.
LDEN
Link Delay
Equalizer Enable
0:5·2
The link delay equalizer enable and select bits control a delay compromise equalizer In
the receive path according to the following table:
LDEN
0
1
1
D3l
X
0
1
Curve Matched
No Equalizer
U.S. Survey Long
Japanese 3-Link
L2ACT
Remote Digital
Loopback Activate
0:4:1
When control bit L2ACT is a one, the receiver digital output is connected to the
transmitter digital Input In accordance with CCITT Recommendation V.54 loop 2.
L3ACT
Local Analog Loopback Activate
0:4:7
When control bit L3ACT is a one, the transmitter analog output is coupled to the
receiver analog input through an attenuator in accordance with CCITT Recommendation
V.54 loop 3.
L4ACT
Remote Analog
Loopback Activate
0:4:6
When control bit L4ACT is a one, the receiver analog input is connected to the transmltter analog output through a variable gain amplifier in a manner similar to CCITT
Recommendation V.54 loop 4.
L4HG
Loop 4 High Gain
0:4:5
When control bit L4HG is a one, the loop 4 van able gain amplifier is set for + 16 dB,
and when at zero the gain IS zero dB.
MHLD
Mark Hold
0:7:4
When control bit MHLD IS a one, the transmitter input data stream is forced to all
marks (ones).
P2DET
Period 2 Detector
1 :8·3
When status bit P2DET is a zero, it indicates that a period 2 sequence has been
detected. This bit sets to a one at the start of the period N sequence. This bit is only
significant for CCITT V.29 and V.27 bislter configurations.
(None)
RAM Access X
2:5.0-7
Contains the RAM access code used in reading chip 2 RAM locations via word X (2: 3
and 2:2).
(None)
RAM Access Y
2:4:0-7
Contains the RAM access code used in reading chip 2 RAM locations via word Y (2: 1
and 2:0).
(None)
RAM Data XL
2:2:0-7
Least significant byte of IS-bit word X used in reading RAM locallons in chip 2.
(None)
RAM Data XM
2:3:0-7
Most significant byte of IS-bit word X used in reading RAM locations in chip 2.
(None)
RAM Data YL
2:0.0-7
Least significant byte of IS-bit word Y used in reading RAM locations In chip 2.
(None)
RAM Data YM
2:1 :0-7
Most significant byte of IS-bit word Y used in reading RAM locations in chip 2.
RBDA
Receiver Baud
Data Available
2:E:0
Status bit RBDA goes to a one when the receiver writes data into register 2: O. The bit
goes to a zero when the host processor reads data from register 2: o.
RBIA
Receiver Baud
Interrupt Active
2:E:7
This status bit IS a one whenever the receiver baud rate device is dnving IRQ low.
RBIE
Receiver Baud
Interrupt Enable
2:E:2
When the host processor writes a one in the RBIE control bit, the IRQ hne of the hardware Interface is driven to zero when status bit RBDA is a one.
RCF
Receiver Carrier
Frequency
1·7:2
Control bit RCF selects the demodulator carner frequency for V.29FT conflgurallons as
follows:
RCF
0
1
Demodulator Carrier Frequency
1700 Hz
1800 Hz
2-98
9600 bps Fast Train Modem
R96FT
R96FT Interface Memory Definitions (Continued)
Mnemonic
(None)
Name
Receiver
Configurallon
Memory
Location
1 :6:0-6
Description
The host processor configures the receiver by writing a control code Into the receiver
configuration field In the Interface memory space (see RSB).
Note: The receiver must be disabled prior to changing configurations See RDIS.
Receiver Configuration Control Codes
Control codes for the modem receiver conflgurallon are:
Configuration
V27 bislter
V29
Configuration Code (Hex)
FT/4800
FT/2400
1C
1A
19
OA
09
4800
2400
4800
2400
14
12
11
22
21
02
01
FT/9600
FT/7200
FT/4800
9600
7200
4800
long
long
short
short
2400/4800 bps GearshlftlV.29 descrambler
2400/4800 bps GearshlftlV.27 bislter descrambler
V.21 Channel 2
61'
41'
See Note 2
1. The Receiver Configuration code automatically changes from a hex 61 (or hex 41)
to a hex 64 (or hex 44) when the receiver transitions from the 2400 bps data state
to the 4800 bps data state.
2. The FSK receiver IS active at all times. Two ancillary hardware circuits, FRLSD
and FRXD, are supplied for FSK message reception. FRLSD is described under
the Received Line Signal Detector section. FRXD provides inverted FSK received
data. Timing extraction must be performed on the FRXD signal externally as no
FSK receiver data clock is provided by the R96FT.
(None)
Receiver Data
1 :0:0-7
The host processor obtains channel data from the receiver in the parallel data mode by
reading a data byte from the receiver data register. The data is divided on baud
boundaries as is the transmitter data.
Status bit RDA goes to a one when the receiver writes data to register 1 : O. RDA goes
to a zero when the host processor reads data from register 1 : O.
RDA
Receiver Data
Available
1 :E:O
RDIS
Receiver Disable
1 :7: 1
When control bit RDIS IS a one, the receiver IS disabled, RLSD is turned off and RXD
IS clamped to all marks. This bit can be used to squelch the receiver during half duplex
transmissions over two wires. This bit must be set to a one prior to changing the
RIA
Receiver Interrupt
Active
1 :E:7
This status bit IS a one whenever the receiver sample rate device is driving IRQ to zero.
RIE
Receiver Interrupt
Enable
1 :E:2
When the host processor writes a one in the RIE control bit, the IRQ line of the
hardware interface is driven to zero when status bit RDA IS a one.
RSB
Receiver Setup Bit
1 :E:3
When the host processor changes the receiver configuratIOn or the RTH field, the host
processor must write a one in the RSB control bit. RSB goes to zero when the changes
become effective.
RTH
Receiver Threshold
Field
1 :7:6,7
The receiver energy detector threshold IS set by the RTH field according to the
following codes (see RSB):
receiver configuration.
RTH
RLSD On
RLSD Off
> -43 dBm
< -48 dBm
1
< -38 dBm
> -33 dBm
2
< -31 dBm
> -26 dBm
3
>-16dBm
< -21 dBm
When control bit RTS goes to a one, the modem begins a transmit sequence. It
continues to transmit until RTS is reset to zero, and the turn-off sequence has been
completed. This Input bit parallels the operation of the hardware RTS control Input
These inputs are OR'ed by the modem.
o
RTS
Request-to-Send
0:7:7
2-99
~
"
R96FT
9600 bps Fast Train Modem
R96FT Interface Memory Definitions (Continued)
Mnemonic
Name
Memory
Location
Description
SDIS
Scrambler Disable
0:7:5
When control bit SDIS
data path.
SEPT
Short Echo
Protector Tone
0:7:0
When control bit SEPT IS a one, the echo protector disable tone is 30 ms long rather
than 185 ms. (See TSB.)
TBA
Transmitter Buffer
Available
O:E:O
This status bit resets to zero when the host processor writes data to transmitter data
register 0: O. When the transmitter empties register 0: 0, this bit sets to a one.
TCF
Transmitter Carrier
Frequency
0:9:3
Control bit TCF selects the modulator carrier frequency for V.29FT configurations as follows:
TIA
Transmitter
Interrupt Active
0:E:7
This status bit is a one whenever the transmitter is driving IRQ to a zero.
TIE
Transmitter
Interrupt Enable
0:E:2
When the host processor writes a one in control bit TIE, the IRQ line of Ihe hardware
interface is driven to zero when status bit TBA is at a one.
TLVL
Transmitter Level
Field
0:4:2-4
The transmitter analog output level is determined by eight TLVL codes, as follows:
IS
a one, the transmitter scrambler circuit is removed from the
TCF
o
1
Modulator Carrier Frequency
1700 Hz
1800 Hz
TLVL
Transmitter Analog Output"
-1 dBm ±1 dB
1
-3dBm±ldB
2
-5 dBm ±1 dB
3
-7 dBm ±1 dB
-9 dBm ± 1 dB
4
5
-11 dBm ±1 dB
6
- 13 dBm ± 1 dB
7
- 15 dBm ± 1 dB
• Each step above is a 2 dB change ± 0.2 dB.
o
TaD
Train-an-Data
1 :6:7
When conlrol bit TaD is a one, it enables the train-an-data algorithm to converge the
equalizer if the signal quality degrades sufficiently. When TaD is a one, the modem still
recognizes a training sequence and enters the force train state. A BER of approximately
10 - 3 for 0.5 seconds initiates train-an-data.
TPDM
Transmitter Parallel
Data Mode
0:7:2
When control bit TPDM is a one, the transmitter accepts data for transmission from the
transmitter data register (0: 0) rather than the serial hardware data input.
(None)
Transmitter
Configuration
0:6:0-7
The host processor configures the transmitter by writing a control byte into the
transmitter configuration register in its interface memory space. (See TSB.)
Transmitter Configuration Control Codes
Control codes for the modem transmitter configurations are:
Configuration
V29
V27 blslter
Configuration Code (Hex)
FT/2400
lC
lA
19
OA
09
4800
2400
4800
2400
14
12
11
22
21
02
01
FT/9600
FT17200
FT/4800
FT/4800
9600
7200
4800
long
long
short
short
2400/4800 bps GearshlftN.29 Scrambler
2400/4800 bps GearshiftlV.27 bis/ter Scrambler
61
41
V.21 Channel 2
See FSKT
Tone transmit
80
2-100
9600 bps Fast Train Modem
R96FT
R96FT Interface Memory Definitions (Continued)
Mnemonic
(None)
Name
Transmitter Data
Memory
Location
0:0:0-7
Description
The host processor conveys output data to the transmitter in the parallel mode by
writing a data byte to the transmitter data register. The data is divided on baud
boundaries, as follows:
Note: Data
IS
transmitted bit zero first
Bits
Configuration
7
V.29 9600 bps
I
6
5
I4
3
I
2
Baud 1
Baud 1
I
V.29 7200 bps
Not Used
V.29 4800 bps
Baud 3
V.27 4800 bps
Not Used
V.27 2400 bps
Baud 3
Baud 2
Baud 1
2400 bps Gearshift
Baud 3
Baud 2
Baud 1
4800 bps Gearshift
I
1
I
0
Baud 0
Baud 2
Baud 1
Baud 1
Baud 1
I
Baud 0
I
Baud 0
Baud 0
I
I
Baud 0
Baud 0
Baud 0
TSB
Transmitter Setup
Bit
O:E:3
When the host processor changes the transmitter configuration, the SEPT bit or the
FSKT bit, the host must write a one in this control bit. TSB goes to a zero when the
change becomes effective. Worst case setup time is 2 baud + turnoff sequence
+ training (if applicable).
TTDIS
Transmitter Train
Disable
0:7:6
When control bit TTDIS is a one, the transmitter does not generate a training sequence
at the start of transmission. With training disabled, RTS/CTS delay is less than two baud
times.
XCEN
External Clock
Enable
0:7:1
When control bit XCEN is a one, the transmitter timing is established by the external
clock supplied at the hardware Input XTCLK, pin 22A.
POWER-ON INITIALIZATION
POLLING SUCCESS
When power is applied to the R96FT, a period of 50 to 350 ms
is required for power supply settling. The power-on-reset signal
(POR) remains low during this period. Approximately 10 ms after
the low to high transition of POR, the modem is ready to be
configured, and RTS may be activated. If the 5 Vdc power supply
drops below 3.5 Vdc for more than 30 msec, the POR cycle is
generated.
In the 9600 bps fast train configuration the modem approaches
a 98% success rate over unconditioned 3002 lines for a signalto-noise ratio of 26 dB, with a received signal level of - 20 dBm.
BIT ERROR RATES
The Bit Error Rate (BER) performance of the modem is specified
for a test configuration conforming to that specified in CCITT
Recommendation V.56. Bit error rates are measured at a
received line signal level of - 20 dBm as illustrated.
At POR time the modem defaults to the following configuration:
fast train, V.29, 9600 bps, no echo protector tone, 1700 Hz carrier frequency, scrambled ones segment disabled, serial data
mode, internal clock, cable equalizers disabled, transmitter
digital delay equalizer disabled, link amplitude equalizer disabled, link delay equalizer disabled, transmitter output level set
to - 1 dBm ± 1 dB, interrupts disabled, receiver threshold set
to - 43 dBm, and train-on-data enabled.
PHASE JITTER
At 2400 bps, the modem exhibits a bit error rate of 10- 6 or less
with a signal-to-noise ratio of 12.5 dB in the presence of 15°
peak-to-peak phase jitter at 150 Hz, or with a signal-to-noise ratio
of 15 dB in the presence of 30° peak-to-peak phase jitter at
120 Hz (scrambler inserted).
POR can be connected to a user supplied power-on-reset signal
in a wire-or configuration. A low active pulse of 3 !,sec or more
applied to the POR pin causes the modem to reset. The modem
is ready to be configured 10 msec after POR is removed.
At 4800 bps (V.27 bis/ter), the modem exhibits a bit error rate
of 10- 6 or less with a slgnal-Io-noise ratio of 19 dB in the
presence of 15° peak-to-peak phase jitter at 60 Hz.
At 9600 bps, the modem exhibits a bit error rate of 10 - 6 or less
with a signal-to-noise ratio of 23 dB in the presence of 10° peakto-peak phase jitter at 60 Hz. The modem exhibits a bit error
rate of 10- 5 or less with a signal-to-noise ratio of 23 dB in the
presence of 20° peak-to-peak phase jitter at 30 Hz.
PERFORMANCE
Whether functioning in V.27, V.29 or the proprietary fast train
configurations, the R96FT provides the user with high
performance.
2-101
9600 bps Fast Train Modem
R96FT
An example of the SER performance capabilities is given in the
following diagrams:
4800 BPS
V.27
2400/4800 BPS
AND
7200 BPS GEARSHIFT
V.29
9600 BPS
300 BPS 2400 BPS 4800 BPS
V.29
V.21
V.27
V.29
4800 BPS
V.29
!
,
10- 3
I
2400/480 o BPS
GEARS HIFT
AND
7200 BPS
10- 3
/
300 BPS
V.21
"!\
/
10-'
w
Ioct
?9 9600 BPS
V.29
2400 BPS ""'4800 BPS
V.27
V.27
I
I
10-'
w
oct
I-
II:
II:
II:
II:
II:
II:
II:
II:
I-
I-
0
0
w
W
iii
iii
10- s
10-s
10- 6
\
10- 6
0
2
4
6
8 10 12 14 16 18
SIGNAL TO NOISE RATIO (dB)
20
22
24
2
Typical BER Performance
Back-to-Back, - 20 dBm Receive Signal Level
4
6
\
8 '0 12 14 16 18 20
SIGNAL TO NOISE RATIO (dB)
22
24
Typical BER Performance
3002 Unconditioned Line, - 20 dBm Receive Signal Level
The SER performance test set-up is shown in the following diagram:
300-3400 HZ
NOISE
SOURCE
GR1381
5 KHZ BW
MODEM
TRANSMITTER
~
r--
FILTER
COMSTRON
FA2874
IMPAIRMENT
LINE
SOURCE
SIMULATOR f--BRADLEY 2A
(3002)
AND 2B
26
-
ATTENUATOR
HP350D
-
ATTENUATOR
I--HP 3500
I
1:
-
LEVEL
METER
HP3555B
-'--
MODEM
RECEIVER
I
1
MODEM
TEST SET
PHOENIX 5000
BER Performance Test Set-up
2-102
R96FT
9600 bps Fast Train Modem
GENERAL SPECIFICATIONS
Modem Power Requirements
Voltage
Tolerance
Current (Typical) @ 25°C
Current (Max) @ DOC
+5 Vdc
+ 12 Vdc
-12 Vdc
±5%
±5%
±5%
550 mA
20 mA
50 mA
<700 mA
< 30 mA
< 80 mA
Note: All voltages must have ripple ,,;01 volts peak·ta-peak.
Modem Environmental Restrictions
Parameter
Temperature
Operating
Storage
Relative Humidity.
Altitude
Specification
O°C to + 60°C (32°F to 140°F)
- 40°C to + 80°C (- 40°F to 176°F) (Stored in heat sealed antistatic bag and shiPPing container)
Up to 90% noncondensing, or a wet bulb temperature up to 35°C, whichever IS less
-200 feet to + 10,000 feet
Modem Mechanical Considerations
Parameter
DIN Connector Version
Board Structure:
Mating Connector:
Dimensions:
Width
Length
Height
Weight (max):
Lead Extrusion (max):
DIP Connector Version
Board Structure'
Dimensions:
Width
Length
Height
Weight (max.):
Pm Length (max.)
Specification
Single PC board with a 3-row 64-pin right angle male DIN connector with rows A and C populated.
The modem can also be ordered with the following DIN connector' 64·pin DIN right angle female,
64-pin DIN vertical male, or 6 64·pin DIN vertical female.
Female 3·row 64-pin DIN receptacle with rows A and C populated. TYPical mating connector'
Winchester 965-6043·0531·1, Burndy RI96B32ROOAOOZ1, or equivalent.
3.937 In (100 mm)
4.725 In. (120 mm)
0.40 In. (10.2 mm)
3.60z (100 g)
0.100 in. (254 mm)
Single PC board With a row of 30 pins and a row of 31 pinS m a dual In·line pm configuration.
3.937 In (100 mm)
3.228 in (82 mm)
02 In. (5.08 mm) above, 0.13 in. (3.30 mm) below
360z (100 g)
0.53 In (135 mm)
2·103
R96FT
9600 bps Fast Train Modem
0.156 :t 0.003 DIA (6 PL)
(3.96)
MALE 64-PIN
DIN CONNEClOR
-1
\:!
3.937
1"~~~~~==~~====~~~
_3i8_2:_~
0.496
(12.6)
0.119
(3)1
~
:!
III
000
~... III ~...
0.483
(12.3)
_ _.,
4.100
I~!
4.725 (104)
(120) - - - - - - + 1
0.200 MAX
[]=fi
0.437
[(5.1), ______________________ ;
Tf~~ nn--'Z\=~ ~MAXJ
~COMPONENT
(1.6)
AREA
DIN CONNECTOR VERSION
000 0
'[
l~
0.098 DIA (3 PL)
(2.5)
,
l,
I"
~~--=-==--~~~
0.100~.100 (TYP.)
(2.54)
0.100
(2.54)
(2.54)
3 725
_.3.937 (94.6)
(100) ------+I
0.53 MAX
0.025
so. PIN
0.200 MAX
1::::::::~~~:::: f"t.'"
(1.6)
(3.3)
COMPONENT AREA
DIP CONNEClOR VERSION (PRELIMINARY)
R96FT Modem Dimensions and Pin Locations
2·104
UNITS: INCHES
mm
R96FT/SC
Integral Modems
'1'
Rockwell
R96FT/SC
9600 bps Fast Train Modem
with Forward Secondary Channel
INTRODUCTION
FEATURES
The Rockwell R96FT/SC is a synchronous serial 9600 bps modem containing a 75 bps asynchronous FSK forward channel. This
modem is designed for multipoint and networking applications.
The R96FT/SC allows full-duplex operation over 4-wire dedicated
unconditioned lines, or half-duplex operation over the general
switched telephone network.
•
•
•
•
•
•
•
•
•
•
•
Proprietary fast train configurations provide training times of
23 ms for V.29FT/9600/7200/4800, 22 ms for V.27FT/4800, and
30 ms for V.27FT/2400. A 240014800 bps Gearshift configuration provides a training time of 10 ms. For applications requiring
operation with international standards, fallback configurations
compatible with CCITI Recommendations V.29 and V.27 bis/ter
are provided. A 300 bps FSK configuration, compatible with
CCITI V.21 Channel 2, is also provided.
•
The small size and low power consumption of the R96FT/SC
offer the user flexibility in formulating a 9600 bps modem design customized for specific packaging and functional requirements.
•
This data sheet corresponds to assembly number
TR96-D500-021 .
•
•
•
•
Proprietary Fast Train
75 bps Forward Channel
2400/4800 bps Gearshift
User Compatibility:
- CCITI V.29, V.27 bis/ter and V.21 Channel 2
Train on Data
Full-Duplex (4-Wire)
Half-Duplex (2-Wire)
Programmable Tone Generation
Dynamic Range -43 dBm to -5 dBm
Diagnostic Capability
Equalization:
- Automatic Adaptive
- Compromise Cable (Selectable)
- Compromise Link (Selectable)
DTE Interface:
- Microprocessor Bus
- CCITI V.24 (RS-232-C Compatible)
Loopbacks
- Local Analog (V.54 Loop 3)
- Remote Analog (Locally Activated)
- Remote Digital (Locally Activated V.54 Loop 2)
Small Size
- 100 mm x 160 mm (3.94 in. x 6.3 in.)
Low Power Consumption
- 4 watts, typical
Programmable Transmit Output Levels for Primary Channel
and Forward Channel
TIL and CMOS Compatible
R96FT/SC Modem
Document No. 29200N13
Data Sheet
2-105
Order No. MD13
Rev. 2, February 1987
R96FT/SC
9600 bps Fast Train Modem
TECHNICAL SPECIFICATIONS
Link Equalizers - Selectable compromise link equalizers in the
receiver optim ize performance over cHannels exhibiting severe
amplitude and delay distortion. Two standards are provided: U.S.
survey long and Japanese 3-link.
TRANSMITTER CARRIER FREQUENCIES
Frequency
Function
(Hz ±O.Ol%)
V.27 bislter Carrier
V 27 FT Carner
2400/4800 bps Gearshift
V.29 Carrier
V.29 FT Carrier
V 21 Channel 2:
Mark
Space
1800
1800
1800
1700
1700'
Automatic Adaptive Equalizer - An automatic adaptive T
equalizer is provided in the receiver circuit.
TRANSMITTED DATA SPECTRUM
If the cable equalizer is not enabled, the transmitter spectrum
is shaped by the following raised cosine filter functions:
1. 1200 Baud. Square root of 90 percent.
2. 1600 Baud. Square root of 50 percent.
3. 2400 Baud. Square root of 20 percent.
NOTE
When used with the 75 bps Forward Channel the
2400 Baud filter is narrower.
1650
1850
'1800 when used In conjunction with 75 bps Forward Channel.
TONE GENERATION
Under control of the host processor, the R96FT/SC can generate
voice band tones up to 4800 Hz with a resolution of 0.15 Hz and
an accuracy of 0.01%. Tones over 3000 Hz are attenuated.
The out-of-band transmitter power limitations meet those
specified by Part 68 of the FCC's rules, and typically exceed
the requirements of foreign telephone regulatory bodies.
SIGNALING AND DATA RATES
SCRAMBLERIDESCRAMBLER
Specification
Parameter
Signaling Rate:
Data Rate:
Signaling Rate'
Data Rate:
Signaling Rate:
Data Rate:
Gearshift Data Rate:
Signaling Rate:
Data Rate:
Signaling Rate:
Data Rate:
The R96FT/SC incorporates a self-synchronizing scramblerl
descrambler. This facility is in accordance with either V.27 bislter
or V.29 depending on the selected configuration.
(±O.Ol%)
2400
9600
7200
4800
1600
4800
baud
bps,
bps,
bps
baud
bps
The scrambler/descrambler facilities for Gearshift can be
selected to be in accordance with either V.27 bislter or V.29.
The scrambler/descrambler selection is made by writing the
appropriate configuration codes into the transmitter and receiver.
1200 baud
2400 bps
2400/4800 bps
300 baud
300 bps
75 baud
75 bps
RECEIVED SIGNAL
FREQUENCY TOLERANCE
The receiver circuit of the R96FT/SC can adapt to received
frequency error of up to ± 10Hz with less than 0.2 dB degradation in BER performance.
During fast train polling, frequency offset must be less than
± 2 Hz for successful training.
DATA ENCODING
RECEIVE LEVEL
At 2400 baud, the data stream is encoded per ccrn- V.29. At
9600 bps, the data stream is divided in groups of four-bits (quadbits) forming a 16-point structure. At 7200 bps, the data stream
is divided into three' bits (tribits) forming an 8-point structure.
At 4800 bps, the data stream is divided into two bits (dibits)
forming a 4-point structure.
The receiver circuit of the modem satisfies all specified performance requirements for received line signal levels from -5 dBm
to -43 dBm. The received line signal level is measured at the
receiver analog input (RXA).
RECEIVE TIMING (Synchronous Configurations)
At 1600 baud, the 4800 bps data stream is encoded into tribits
per CCITT V.27 bislter.
At 1200 baud, the 2400 bps data stream
per CCITT V.27 bis/ter.
IS
The R96FTlSC provides a data derived Receive Data Clock
(RDClK) output in the form of a squarewave. The low-to-high
transitions of this output coincide with the centers of received
data bits. For the Gearshift Configuration, the first 32 bauds of
data are at 2400 bps followed by 4800 bps data for the remaining message. The timing recovery circuit is capable of tracking
a ± o.OI k frequency error in the associated transmit timing
source. DClK duty cycle is 500/0 ± 1%.
encoded into dibits
For the Gearshift Configuration, the Signaling rate is 1200 baud.
The 2400 bps data stream is encoded into dibits forming a 4-point
structure, and the 4800 bps data stream is encoded into quadbits forming a 16-point structure. The first 32 bauds of data are
transmitted at 2400 bps and the remaining message is transmitted at 4800 bps.
R
TRANSMIT LEVEL
The main channel output level is accurate to ± 1.0 dB and is
programmable from - 1.0 dBm to - 15.0 dBm in 2 dB steps.
At 300 baud, the 300 bps data stream is encoded per CCITT
V.21 channel 2 into a mark frequency of 1650 Hz and a'space
frequency 01 1850 Hz.
The forward channel transmit level is set relative to the main
channel as -6 dB, -10 dB, -14 dB, or -18 dB.
At 75 baud, the 75 bps data stream is encoded to a mark frequency of 356 Hz and a space frequency of 300 Hz.
TRANSMIT TIMING (Synchronous Configurations)
The R96FT/SC provides a Transmit Data Clock (TDClK) output with the following characteristics:
1. Frequency. Selected data rate of 9600, 7200, 4800, 2400 or
300 Hz (± 0.01 %). For the Gearshift Configuration, TDClK
is a 2400 Hz clock for the first 32 bauds of data, and a
4800 Hz clock for the remaining message.
2. Duty Cycle. 50 0k ± 1%
EQUALIZERS
The R96FT/SC provides equalization functions that improve performance when operating over low quality lines.
Cable Equalizers - Selectable compromise cable equalizers in
the receiver and transmitter are provided to optimize performance
over different lengths of non-loaded cable of 0.4 mm diameter.
2-106
9600 bps Fast Train Modem
R96FT/SC
RESPONSE TIMES OF CLEAR TO SEND (CTS)
Input data presented on TXD is sampled by the R96FT/SC at
the low-to-high transition of TDCLK. Data on TXD must be stable
for at least one microsecond prior to the rising edge of TDCLK
and remain stable for at least one microsecond after the riSing
edge of TDCLK.
The time between the off-to-on transition of Request To Send
(RTS) and the off-to-on transition of Clear to Send (CTS) is
dictated by the length of the traming sequence and the echo
protector tone, if used. These times are given in the Turn-On
Sequences table. If training is not enabled, RTS/CTS delay is
less than 2 baud times.
EXTERNAL TRANSMIT CLOCK
The transmitter data clock (TDCLK) can be phase locked to a
signal on input XTCLK. This input signal must equal the desired
data rate ± 0.01 % With a duty cycle of 50% ± 20%.
The time between the on-to-off transition of RTS and the on-tooff transition of CTS in the data state is a maximum of 2 baud
times for all configurations.
TRAIN ON DATA
RESPONSE TIMES OF FORWARD CHANNEL
CLEAR TO SEND (SCCTS)
When train on data is enabled (by setting a bit in the interface
memory), the modem monitors the EQM signal. If EQM indicates
a loss of equalization (Le., BER approximately 10- 3 for
0.5 seconds) the modem attempts to retrain on the data stream.
The time for retrain is typically 3 to 15 seconds.
SCRTS/SCCTS response times vary according to the transmit
level set by the SCTLVL field.
SCTLVL
(0:9:0-1)
TURN-ON SEQUENCE
0
1
2
3
A total of 20 selectable turn-on sequences can be generated
as defined in the following table:
No.
V.29
(bps)
1 FT/9600
2 FT/7200
3 FT/4800
4
5
6
7
8
9
10
11
12
13
9600
7200
4800
14
15
16
17
18
19
20
9600
7200
4800
V.27
bis/ter
(bps)
RTS-CTS
Gearshift Response Time
(bps)
(milliseconds) Comments
FT/4800
FT/2400
23
24
23
22
30
4800
2400
4800
2400
long
long
short
short
240014800
4800 long
2400 long
4800 short
2400 short
-6
-10
-14
-18
SCCTS Response Time
(ms)
dB
dB
dB
dB
378
238
150
95
RECEIVE LINE SIGNAL DETECTOR (RLSD)
Response
For Fast Train and Gearshift configurations, the receiver enters
the training state upon detecting a significant increase in the
received signal power. If the received line signal power is greater
than the selected threshold level at the end of the training state,
the receiver enters the data state and RLSD is activated. If the
received line signal power is less than the selected threshold
level at the end of the training state, the receiver returns to the
idle state and RLSD is not activated.
Proprietary
Fast Train
253
253
253
708
943
50
67
10
438
438
438
913
1148
255
272
TX Level
Relative to Primary
Also, in Fast Train and Gearshift configurations, the receiver
initiates the turn-off delay upon detecting a significant decrease
in the received Signal power. If the received signal power is less
than the selected threshold at the end of the turn-off delay, the
receiver enters the idle state and RLSD is deactivated. If the
received signal power is greater than the selected threshold at
the end of the turn-off delay, the receiver returns to the data state
and RLSD is left active.
Preceded'
by Echo
Protector
Tone for
lines usmg
echo
suppressors.
For CCITT configurations, the receiver enters the training
detection state when the received line signal power crosses the
selected threshold level. RLSD is activated at the end of the
training sequence. For V.21 Channel 2, a separate received line
signal detector (FRLSD) is provided. FRLSD is activated when
energy above -43 dBm is present at the receiver's audio input
(RXA). The FRLSD off-to-on response time is 15 ± 5 ms and
the on-to-off response time is 25 ± 5 ms.
1 For short echo protector tone, subtract 155 ms from values of
RTS-CTS response time.
2. V.21 (300 bps FSK) RTS-CTS response time IS <35 ms
3. 75 bps forward channel SCRTS-SCCTS response time is
<500 ms.
The RLSD on-to-off response times are:
TURN-OFF SEQUENCE
For V .27bis/ter, V.27FT and 2400/4800 bps Gearshift configurations, the turn-off sequence consists of approximately 10 ms
of remaining data and scrambled ones followed by a 20 ms
period of no transmitted energy (V.27 bis/ter only). For V.29 and
V.29FT, the turn-off sequence consists of approximately 8 ms
of remaining data and scrambled ones.
Configuration
V 29 Fast Tram
V.27 Fast Tram
Gearshift
V.29
V.27 bis/ter
CLAMPING
Response Time (ms)
6.5
8
6
30
10
±1
±1
±1
±9
±5
RLSD response times are measured with a Signal at least 3 dB
above the actual RLSD on threshold or at least 5 dB below the
actual RLSD off threshold.
Received Data (RXD) is clamped to a constant mark (one) when
the Received Line Signal Detector (RLSD) is off.
2-107
9600 bps Fast Train Modem
R96FT/SC
Threshold Options
Threshold
Four threshold options are provided:
1. Greater than - 43 dBm (RLSO on)
Less than .- 48 dBm (RLSO off)
2. Greater than - 33 dBm (RLSO on)
Less than - 38 dBm (RLSO off)
3. Greater than - 26 dBm (RLSO on)
Less than - 31 dBm (RLSO off)
4. Greater than -16 dBm (RLSO on)
Less than - 21 dBm (RLSO off)
The SCRLSO Turn-On threshold is - 54 dBm. The SCRLSO
Turn-Off threshold is - 58 dBm.
MODES OF OPERATION
The R96FT/SC is capable of being operated in either a serial
or a parallel mode of operation.
SERIAL MODE
The serial mode uses standard V.24 (RS-232-C compatible) signals to transfer channel data. An optional USRT device (shown
in the Functional Interconnect Oiagram) illustrates this capability.
NOTE
Performance may be at a reduced level when the received
signal is less than -43 dBm.
PARALLEL MODE
The R96FTlSC has the capability of transferring channel data
(up to eight bits at a time) via the microprocessor bus.
For CCITT configurations, a minimum hysteresis action of 2 dB
exists between the actual off-to-on and on-to-off transition levels.
The threshold levels and hysteresis action are measured with
unmodulated 2100 Hz tone applied to the receiver's audio input
(RXA).
MODE SELECTION
For the transmitter, a control bit determines whether the source
of transmitted data is the V.24 interface (serial mode) or the
parallel transmitter data register (parallel mode). The transmitter
automatically defaults to the serial mode at power-on.
FORWARD CHANNEL SIGNAL DETECTOR (SCRLSD)
Response
Signal Level
SCRLSD Turn-On (ms)
SCRLSD Turn-Off (ms)
-7dBm
140 ± 10
800± 10
-48 dBm
34O± 10
550±10
r------,
I
I
I
I
I
I
I
.A-
...i
r
L-_-
0SCOPE
~
CTS
TXD
TDCLK
XTCLK
RLSD
RXD
RDCLK
TBCLK
RBCLK
USRT
(OPTIONAL)
I
In either parallel or serial mode the R96FT/SC is configured by
the host processor via the microprocessor bus.
RTS
k
I
The receiver simultaneously outputs received data via the V.24
interface and the parallel receiver data register.
i
.J
MODEM
xf fy
EYEY
EYSYNC
EYECLK
EYE
PATTERN
GENERATOR
+12V
+5V
GND
-12V
READ
WRITE
DATA BUS (8)
HOST
PROCESSOR
(DTE)
EYEX
TXA
Di
ADDRESS BUS 14[
RSi
CS (3)
CSi
IDECODER
POR
t
RXA
AUXIN
iRa
+s---wv--l
r
- -,
I
I
UART
I (OPTIONAL)
I
'--
SCRTS
SCCTS
I
SCTXD
r
- -
POWER
SUPPLY
SCRLSD
SCRXD
-'
R96FT/SC Functional Interconnect Diagram
2-108
LINE
INTERFACE
~}
TELEPHONE
LINE
9600 bps Fast Train Modem
R96FT/SC
INTERFACE CRITERIA
R96FT/SC Hardware Circuits (Continued)
The modem interface comprises both hardware and software
circuits. Hardware circuits are assigned to specific pins In a
64-pin DIN connector. Software circuits are assigned to specific
bits in a 48-byte interface memory.
I Type
F. DIAGNOSTIC:
EYEX
OC
EYEY
OC
OA
EYECLK
OA
EYESYNC
Name
HARDWARE CIRCUITS
Signal names and descriptions of the hardware circuits, including
the microprocessor interface, are listed in the R96FT/SC Hardware Circuits table. In the table, the column titled 'Type' refers
to designations found in the Hardware Circuit Characteristics.
The microprocessor interface is designed to be directly compatible with an 8080 microprocessor. With the addition of a few
external logic gates, it can be made compatible with 6500, 6800,
er 68000 microprocessors.
CS1
CS2
IA
9A
READ
WRITE
IRQ
IA
IA
OB
12C
11A
11C
9C
Data-X Axis
Data-Y Axis
Clock
SynchroniZing
READ
WRITE
CSi
(i = 0-2)
4C
4A
5C
IA
Eye Pattern
Eye Pattern
Eye Pattern
Eye Pattern
Signal
Microprocessor Timing
'C}
6C
6A }
7C
7A
10C
Description
Eye Pattern Generation
R96FT/SC Hardware Circuits
1I0A
1I0A
1I0A
IA
IA
IA
IA
IA
15C
14A
14C
13A
I
The four hardware diagnostic circuits, identified in the preceding
table, allow the user to generate and display an eye pattern.
Circuits EYEX and EYEY serially present eye pattern data for
the horizontal and vertical display inputs respectively. The 8-bit
data words are shifted out most significant bit first, clocked by
the rising edge of the EYECLK output. The EYESYNC output
is provided for word synchronization. The falling edge of
EYESYNC may be used to transfer the 8-bit word from the shift
register to a holding register. Digital to analog conversion can
then be performed for driving the X and Y inputs of an
oscilloscope.
Description
Pin No.
Name I Type
I
A. OVERHEAD:
Ground (A) AGND
31C,32C
Analog Ground Return
Ground (D) DGND 3C,8C,5A,10A
Digital Ground Return
PWR 19C,23C,26C,30C + 5 Vdc supply
+5 volts
15A
+ 12 volts PWR
+ 12 Vdc supply
-12 volts PWR
12A
- 12 Vdc supply
Power-on-reset
POR
1I0B
13C
B. MICROPROCESSOR INTERFACE:
D7
1I0A
1A
D6
1I0A
D5
1I0A
2C
D4
I/OA
2A
Data Bus (8 Bits)
D3
1I0A
3A
D2
D1
DO
RS3
RS2
RS1
RSO
CSO
Pin No.
RSi
Register Select (4 Bits)
(i
Chip SelectTransmitter Device
Chip Select-Receiver
Sample Rate Device
Chip Select-Receiver
Baud Rate Device
Read Enable
WYlte Enable
Interrupt Request
= 0-3)
READ
C. V.24 INTERFACE:
21A
RDCLK
OC
TDCLK
23A
OC
XTCLK
IB
22A
RTS
IB
25A
CTS
OC
25C
TXD
IB
24C
22C
OC
RXD
RLSD
24A
OC
SCRTS
IB
21C
SCCTS
20A
OC
SCTXD
IB
19A
SCRLSD
OD
20C
18A
SCRXD
OD
D. ANCILLARY CIRCUITS:
RBCLK
OC
26A
TBCLK
27C
OC
FRXD
OD
16A
FRLSD
OD
17C
E. ANALOG SIGNALS:
TXA
AA
31A
RXA
AB
32A
AUXIN
AC
30A
Receive Data Clock
Transmit Data Clock
External Transmit Clock
Req uest to Send
Clear to Send
Transmitter Data
Receiver Data
Received Line Signal Detector
Forward Channel RTS
Forward Channel CTS
Forward Channel TXD
Forward Channel RLSD
Forward Channel RXD
Di
(i
= 0-7)
Microprocessor Interface Timing Diagram
Critical Timing Requirements
Characteristic
CSi. RSI setu~e prior
to Read or Write
Data access time after Read
Data hold time after Read
CSI, RSi hold time after
Read or Write
Write data setup time
Write data hold time
Write strobe pulse Width
Receiver Baud Clock
Transmitter Baud Clock
FSK Receiver Data
(inverted data)
FSK Received Line Signal
Detector
Transmitter Analog Output
Receiver Analog Input
Auxiliary Analog Input
2-109
Symbol
Min
TCS
TDA
TDH
30
-
-
140
50
TCH
TWDS
TWDH
TWR
10
75
10
75
10
Max
-
-
Units
nsec
nsec
nsec
nsec
nsec
nsec
nsec
•
I
9600 bps Fast Train Modem
R96FT/SC
Digital Interface Characteristics
Input/Output Type
~ymbol
Parameter
Units
IA
18
Ie
08
OA
VIH
Input Voltage, High
V
2.0 Min.
2.0 Min.
2.0 Min.
V IL
VOH
Input Voltage, Low
V
0.8 Max
0.8 Max.
0.8 Max.
Output Voltage, High
V
2.4 Min'
VOL
Output Voltage, Low
V
0.4 Max. 2
liN
Input Current,
Leakage
10H
Output Current, High mA
Output Current, Low
Ipu
Pull-Up Current
(Short Circuit)
p.A
CL
Capacitive Load
pF
Co
Capacitive Drive
pF
22 Min. 6
0.4 Max 2
0.4 Max. 2
0.6 Max'?
1/0 A
1/08
2.0 Min.
525 Max.
2.0 Min.
0.8 Max.
2.4 Min.'
0.8 Max.
24 MIn.3
0.4 Max. 2
0.4 Max.5
±2.5 Max.'
-0.1 Max.
mA
1.6 Max.
~A
1.6 Max.
1.6 Max.
±10 Max.
-240 Max. -240 Max.
-10 Min. -10 Min
5
5
-240 Max.
-10 Min.
TIL
I Load = -100 p.A
I Load = 1.6 mA
I Load = -40 ~A
V IN = 0.4 to 2.4 Vdc, Vcc
TIL
w/Puil-up
-260 Max.
-100 Min.
20
100
Circuit Type
Notes 1.
2.
3.
4.
00
p.A ±2.5 Max.
10L
IL
Output Current,
Leakage
OC
TTL
w/Puil-up
TTL
100
Open-Drain Open-Drain
w/Puil-up
5. I Load
6. I Load
7 I Load
= 5.25 Vdc
Analog Interface Characteristics
Name
Type
TXA
AA
The transmitter output impedance is 604 ohms
±1%
RXA
AB
The receiver input impedance is 60K ohms
±23%.
AUXIN
AC
The auxiliary analog Input allows access to the
transmitter for the purpose of interfacing with
user provided equipment. Because this is a
sampled data input, any signal above 4800 Hz
will cause aliasing errors. The input impedance
is 1K ohms, and the gain to transmitter output is
TLVL setting +0.6dB -1.4dB." unused, thiS
Input must be grounded near the modem
connector. " used, It must be driven from a low
impedance source.
100
TIL
10
40
100
100
3-State Open-Drain
Transceiver w/Puil-up
= 0.36 mA
= -400 ~A
= 2.0 mA
When information in these registers is being discussed, the
format Y:Z:Q is used. The chip is specified by Y(0-2), the register
by Z(O-F), and the bit by Q(0-7, 0 = LSB).
Characteristics
Status Control Bits
The operation of the R96FT/SC is affected by a number of software control inputs. These inputs are written into registers within
the interface memory via the host microprocessor bus. Modem
operation is monitored by various software flags that are read
from interface memory via the host microprocessor bus. All status
and control bits are defined in the Interface Memory table. Bits
deSignated by a dash (-) are reserved for modem use only and
must not be changed by the host.
RAM Data Access
The R96FT/SC provides the user with access to much of the
data stored in the modem's memories. This data is useful for
performing certain diagnostic functions.
SOFTWARE CIRCUITS
The R96FT/SC comprises three signal processor chips. Each
of these chips contains 16 registers to which an external (host)
microprocessor has access. Although these registers are within
the modem, they may be addressed as part of the host
processor's memory space. The host may read data out of or
write data into these registers. The registers are referred to as
interface memory. Registers in chip 1 update at half the modem
sample rate (4800 bps). Registers in chip 0 and 2 update at the
selected baud rate.
Two RAM access registers in chip 2 allow user access to RAM
locations via the X word registers (2:3 and 2:2) and the Y word
register (2:1 and 2:0). The access code stored in RAM ACCESS
X (2:5) selects the source of data for RAM DATA XM and RAM
DATA XL (2:3 and 2:2). Similarly, the access code stored in RAM
ACCESS Y (2:4) selects the source of data for RAM DATA YM
and RAM DATA YL (2:1 and 2:0).
2-110
Ii
I~
"
R96FT/SC
9600 bps Fast Train Modem
Reading of diagnostic RAM data is performed by storing the
necessary access codes in 2:5 and 2:4, reading 2:0 to reset the
associated data available bit (2:E:0), then waiting for the data
available bit to return to a one. Data is now valid and may be
read from 2:3 through 2:0.
Transmitter Interface Memory Chip 0 (CSO)
~
7
6
5
4
F
-
E
TIA
-
0
-
-
-
-
-
-
-
-
-
An additional diagnostic is supplied by the sample rate proc·
essor (chip 1). Registers 1:2 and 1:3 supply a 16 bit AGe Gain
Word. These two diagnostic data registers are updated at the
sample rate during the data state and may be read by the host
processor asynchronously.
C
B
A
FSKT ASCR
9
RAM Access Codes
The RAM access codes defined in the following table allow the
host processor to read diagnostic information within the modem.
8
-
7
RTS
-
Function
1
2
3
4
5
Equalizer Input
Equalizer Tap Coefficients
Unrotated Equalizer Output
Rotated Equalizer Output
DecIsion POints
(Ideal Data Paints)
Error Vector
Rotation Angle
Frequency Correction
Eye Quality Monitor (EQM)
6
7
8
9
X Access Y Access Register
40
01·20
61
62
68
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
E5
A7
A5
AC
65
Not Used
Not Used
Not Used
0,1,2,3
2,3
2,3
2.3
7
6
5
4
3
2
1
F
RIA
D
-
A
9
8
FED
RTH
7
6
TOD
5
-
4
-
-
-
-
TIE
TBA
-
-
-
CF
DDEE
-
-
-
-
SCTLVL
-
-
EPT TPDM XCEN SEPT
CEO
LAEN LDEN
TLVL
A3L
D3L
L2ACT LCEN
FREOM
FREOL
-
1
-
-
-
-
-
-
-
1
0
TRANSMITTER DATA
0
~
7
6
5
4
3
2
Bit
NOTE
(-) indicates reserved for modem use only.
Receiver Interface Memory Chip 2 (CS2)
:~
0
7
6
5
4
3
-
DDIS
-
-
-
-
-
RSB
RIE
-
-
-
CDET
-
P2DET
-
-
-
SCEN RDIS
RDA
-
-
-
-
-
RBIE
-
-
-
-
-
-
-
-
-
E
RBIA
-
0
-
C
-
B
A
9
8
7
RECEIVER CONFIGURATION
-
F
6
-
-
5
RAM ACCESS X
4
RAM ACCESS Y
AGC GAIN WORD (MSB)
3
RAM DATA XM
2
AGC GAIN WORD (LSB)
2
RAM DATA XL
1
RAM DATA YM
0
RAM DATA YL
-
-
-
-
-
-
-
-
RECEIVER DATA
0
Register
h
0
TSB
3
1
1
2
1
0
Register
E
B
-
2
Register
C
-
3
Receiver Interface Memory Chip 1 (CS1)
~
-
L3ACT L4ACT L4HG
4
CO
81-AO
El
E2
E8
2
TRANSMITTER CONFIGURATION
-
5
Baud Rate Processor (Chip 2) RAM Access Codes
PCF SCRTS
TTDIS SDIS MHLD
6
No.
3
Register
7
6
5
4
3
2
1
~
0
7
6
5
4
3
Bit
NOTE
(-) indicates reserved for modem use only
NOTE
(-) Indicates reserved for modem use only.
2·111
-
-
-
-
-
-
-
-
-
-
-
2
1
0
RBDA
-
R96FT/SC
9600 bps Fast Train Modem
R96FT/SC Interface Memory Definitions
Mnemonic
Name
Memory
Location
Description
ASCR
Append Scrambled
Ones
0:9:6
When control bit ASCR is a one, one baud of scrambled marks is included in the V.29FT
and V.27FT traming sequences. The RTS-CTS delay is thus extended by one
baud period when ASCR IS a one.
A3L
Amplitude 3-lInk
Select
0:5: 1
See LAEN.
CDET
Carrier Detector
1 :9:2
When zero, status bit CDET indicates that passband energy IS bemg detected, and
that a training sequence is not in process. CDET goes to a zero at the start of the
data state, and returns to a one at the end of the received signal. CDET activates up to
1 baud time before RLSD and deactivates within 2 baud times after RLSD.
CEO
Cable Equalizer
Field
0:5:(4,5)
The CEO Control field simultaneously controls amplitude compromise equalizers in both
the transmit and receive paths. The following table lists the possible cable equalizer
selection codes:
CEQ
Cable Len9th (0.4 mm diameter)
o
0.0
1.8 km
3.6 km
7.2 km
1
2
3
CF
Carrier Frequency
0:9:3
When control bit CF is a one, the transmitter carrier frequency for V.29FT changes from
1700 Hz to 1800 Hz.
DDEE
Digital Delay
Equalizer Enable
0:9:2
When control bit DDEE is a one, a fourth order digital delay equalizer is inserted in the
transmit path.
DO IS
Descramble Disable
1 :7:5
When control bit DDIS is a one, the receiver descrambler circuit is removed from the
data path.
D3L
Delay 3-Link Select
0:5:0
See LDEN.
EPT
Echo Protector
Tone
0:7:3
When control bit EPT is a one, an unmodulated carrier is transmitted for 185 ms
(optionally 30 ms) followed by 20 ms of no transmitted energy at the start of
transmission. This option is available in the V.27 and V.29 Configurations, although it is
not specified in the CCITT V.29 recommendation.
FED
Fast Energy
Detector
1 :9:6
When status bit FED is a zero, it indicates that energy above the receiver threshold is
present in the passband.
(None)
FREOUFREOM
0:2:0-7,
0:3:0-7
The host processor conveys tone generation data to the transmitter by writing a 16-bit
data word to the FREOL and FREQM registers in the interface memory space, as
shown below:
FREQM Register (0:3)
Bit: I
I
IData Word: I
7
I
6
I
5
I
4
I
3
J
2
J
1
I
0
I
2 '5
I
2"
I
2'3
I
2'2
I
2"
I
2'0
I
29
I
28
I
6
I
5
I
4
I
3
I
2
I
1
I
0
I
L
24
23
I
22
I
2'
I
20
I
FREQL Register (0: 2)
Bit: I
I
IData Word: I
7
I
27
2'l
25
I
I
I
The frequency number (N) determines the frequency (F) as follows:
F = (0.146486) (N) Hz ±0.01%
HexadeCimal frequency numbers (FREQL, FREQM) for commonly generated tones are
given below:
Frequency (Hz)
462
1100
1650
1850
2100
2-112
FREQM
DC
10
2C
31
38
FREQL
52
55
00
55
00
"1
iJ
R96FT/SC
9600 bps Fast Train Modem
R96FT/SC Interface Memory Definitions (Continued)
Mnemonic
Name
Memory
Location
Description
FSKT
FSK Transmitter
Configuration
09'7
The V.21 Channel 2 (300 bps synchronous FSK) transmitter configuration is selected by
setting the FSKT control bit to a one (see TSB). While set to a one, this control bit
overrides the configuration selected by the control code In register 0:6. The FSK data
may be transmitted in parallel mode or ,n serial mode (see TPDM).
LAEN
Link Amplitude
Equalizer Enable
0'5:3
The link amplitude equalizer enable and select bits control an amplitude compromise
equalizer in the receive path according to the following table:
lAEN
o
A3l
X
1
1
1
o
Curve Matched
No Equalizer
U.S. Survey Long
Japanese 3-Link
LCEN
Loop Clock Enable
0:4:0
When control bit LCEN IS a one, the transmitter clock tracks the receiver clock.
LDEN
Link Delay
Equalizer Enable
0:5'2
The link delay equalizer enable and select bits control a delay compromise equalizer In
the receive path according to the following table:
lDEN
o
D3l
X
1
1
1
o
Curve Matched
No Equalizer
U.S. Survey Long
Japanese 3-Llnk
L2ACT
Remote Digital
Loopback Activate
0.4: 1
When control bit L2ACT is a one, the receiver digital output IS connected to the
transmitter digital Input In accordance with CCITT Recommendation V.54 loop 2.
L3ACT
Local Analog Loopback Activate
0:4:7
When control bit L3ACT is a one, the transmitter analog output IS coupled to the
receiver analog Input through an attenuator in accordance with CCITT Recommendation
V.54 loop 3.
L4ACT
Remote Analog
Loopback Activate
0.4:6
When control bit L4ACT IS a one, the receiver analog input IS connected to the transmitter analog output through a variable gain amplifier In a manner Similar to CCID
Recommendation V.54 loop 4.
L4HG
Loop 4 High Gain
0:4'5
When control bit L4HG IS a one, the loop 4 variable gain amplifier IS set for + 16 dB,
and when at zero the gain is zero dB.
MHLD
Mark Hold
0:7'4
When control bit MHLD IS a one, the transmitter input data stream is forced to all
marks (ones).
PCF
Primary Channel
Filter
0'9:5
When control bit PCF is a one, the 2400 baud primary channel transmitter filter is set to
a narrower bandwidth than normal.
P2DET
Period 2 Detector
1 :8:3
When status bit P2DET is a zero, it indicates that a period 2 sequence has been
detected. ThiS bit sets to a one at the start of the period N sequence. ThiS bit is only
Significant for CCID V.29 and V.27 bis/ter configurations.
(None)
RAM Access X
2:5:0-7
Contains the RAM access code used
and 2:2).
(None)
RAM Access Y
2.4:0-7
Contains the RAM access code used in reading chip 2 RAM locations via word Y (2: 1
and 2:0).
(None)
RAM Data XL
2:2:0-7
Least significant byte of 16-bit word X used in reading RAM locations
(None)
RAM Data XM
2:3:0-7
Most significant byte of 16-bit word X used in reading RAM locations In chip 2.
(None)
RAM Data YL
2:0:0-7
Least Significant byte of 16-bit word Y used in reading RAM locations in chip 2.
In
reading chip 2 RAM locations via word X (2: 3
In
chip 2.
(None)
RAM Data YM
2: 1 :0-7
Most Significant byte of 16-blt word Y used in reading RAM locations In chip 2
RBDA
Receiver Baud
Data Available
2:E'0
Status bit RBDA goes to a one when the receiver writes data Into register 2: 0 The bit
goes to a zero when the host processor reads data from register 2: O.
RBIA
Receiver Baud
Interrupt Active
2:E'7
This status bit IS a one whenever the receiver baud rate device is driVing IRQ low.
RBIE
Receiver Baud
Interrupt Enable
2:E:2
When the host processor writes a one In the RBIE control bit, the IRQ line of the hardware interface IS driven to zero when status bit RBDA IS a one.
2-113
R96FT/SC
9600 bps Fast Train Modem
R96FT/SC Interface Memory Definitions (Continued)
Mnemonic
(None)
Name
Receiver
Configuration
Memory
Location
1 60-6
Description
The host processor configures the receiver by Writing a control code into the receiver
configuration field in the Interface memory space (see RSB)
Note: The receiver must be disabled pnor to changing configurations See RDIS.
Receiver Configuration Control Codes
Control codes for the modem receiver configuration are:
Configuration
V27 bislter
V29
Configuration Code (Hex)
lC
lA
19
FT/9600
FT/7200
FT/4800
OA
FT/4800
FT/2400
09
4800
2400
4800
2400
14
12
11
22
21
02
01
9600
7200
4800
long
long
short
short
2400/4800 bps GearshiftlV.29 descrambler
2400/4800 bps GearshlftlV:27 bislter descrambler
V 21 Channel 2
61'
41'
See Note 2
1. The Receiver Configuration code automatically changes from a hex 61 (or hex 41)
to a hex 64 (or hex 44) when the receiver transitions from the 2400 bps data state
__
to the 4800 bps data state.
2. The FSK receiver is active at all times. Two ancillary hardware Circuits, FRLSD
and FRXD, are supplied for FSK message reception. FRLSD is described under
the Received Line Signal Detector section. FRXD provides Inverted FSK received
data. Timing extraction must be performed on the FRXD signal externally as no
FSK receiver data clock is provided by the R96FT/SC.
(None)
Receiver Data
1 :0:0-7
The host processor obtainS channel data from the receiver in the parallel data mode by
reading a data byte from the receiver data register. The data IS diVided on baud boundaries as is the transmitter data.
RDA
Receiver Data
Available
I:E 0
Status bit RDA goes to a one when the receiver writes data to register 1 : O. RDA goes
to a zero when the host processor reads data from register 1 : O.
RDIS
Receiver Disable
1'7:1
When control bit RDIS IS a one, the receiver IS disabled, RLSD is turned off and RXD
IS clamped to all marks. This bit can be used to squelch the receiver dUring half duplex
transmissions over two wires. ThiS bit must be set to a one prior to changing the
receiver conflgurallon.
RIA
Receiver Interrupt
Active
1 :E:7
ThiS status bit is a one whenever the receiver sample rate device IS driVing IRQ to zero.
RIE
Receiver Interrupt
Enable
1 :E:2
When the host processor writes a one in the RIE control bit, the IRQ line of the
hardware interface IS driven to zero when status bit RDA is a one.
RSB
Receiver Setup Bit
1 :E:3
When the host processor changes the receiver configuration, the FSKR bit or the RTH
field, the host processor must wnte a one In the RSB control bit. RSB goes to zero
when the changes become effective.
RTH
Receiver Threshold
Field
1 :7:6,7
The receiver energy detector threshold IS set by the RTH field according to the following codes (see RSB):
RTH
RLSO On
> -43
> -33
> -26
> -16
0
1
2
3
2-114
dBm
dBm
dBm
dBm
RLSO Off
< -48
< -38
< -31
< -21
dBm
dBm
dBm
dBm
R96FT/SC
9600 bps Fast Train Modem
R96FTfSC Interface Memory Definitions (Continued)
Mnemonic
Name
Memory
Location
Description
RTS
Request-to-Send
o7
SCEN
Forward Channel
Enable
1'7:2
When control bit SCEN IS a one, the forward channel demodulator IS enabled and the
primary channel receiver carrier frequency is changed from 1700 to 1600 Hz m V.29 FT
configurations.
SCRTS
Forward Channel
Request-to-Send
0:9'4
When control bit SCRTS IS a one, the modem begins a forward channel transmit sequence. Transmission continues until SCRTS is a zero. SCRTS in the mterface memory
is ORed with signal SCRTS on the card connector.
SCTLVL
Forward Channel
Transmit Level
0:9:0-1
The forward channel transmit level is set relative to the main channel transmit level by
the following SCTLVL codes:
7
When control bit RTS goes to a one, the modem begms a transmit sequence It continues to transmit until RTS is reset to zero, and the turn-off sequence has been completed. This input bit parallels the operation of the hardware RTS control mput.
These mputs are ORed by the modem.
SCTLVL
Code
o
1
2
3
Forward Channel Transmit
Level Relative to Primary Channel
-6
-10
-14
-16
dB
dB
dB
dB
SOlS
Scrambler Disable
0:7'5
When control bit SOlS is a one, the transmitter scrambler cirCUit
data path.
IS
removed from the
SEPT
Short Echo
Protector Tone
o 7:0
When control bit SEPT IS a one, the echo protector disable tone
than 185 ms. (See TSB.)
IS
30 ms long rather
TBA
Transmitter Buffer
Available
o E'O
This status bit resets to zero when the host processor writes data to transmitter data
register 0: O. When the transmitter empties register 0: 0, this bit sets to a one.
TIA
Transmitter Interrupt Active
0:E:7
This status bit is a one whenever the transmitter is driving IRQ to a zero.
TIE
Transmitter Interrupt Enable
0:E:2
When the host processor writes a one in control bit TIE, the IRQ line of the hardware
interface is driven to zero when status bit TBA is at a one.
TLVL
Transmitter Level
Field
0:4:2-4
The transmitter analog output level is determmed by eight TLVL codes, as follows:
TLVL
o
Transmitter Analog Output"
-1 dBm
-3 dBm
-5 dBm
-7 dBm
3
-9 dBm
4
-11 dBm
5
-13 dBm
6
7
-15 dBm
"Each step above is a 2 dB change ± 0.2 dB.
1
2
± 1 dB
± 1 dB
± 1 dB
± 1 dB
± 1 dB
± 1 dB
± 1 dB
± 1 dB
TOO
Train-an-Data
1 :6:7
When control bit TOO is a one, it enables the train-an-data algorithm to converge the
equalizer if the signal quality degrades suffiCiently. When TOO IS a one, the modem stili
recognizes a training sequence and enters the force train state. A BER of approximately
10 - 3 for 0.5 seconds initiates train-an-data
TPDM
Transmitter Parallel
Data Mode
0:7:2
When control bit TPDM IS a one, the transmitter accepts data for transmission from the
transmitter data register (0: O) rather than the serial hardware data input
2-115
9600 bps Fast Train Modem
R96FT/SC
R96FT/SC Interface Memory Definitions (Continued)
Mnemonic
(None)
Name
Transmitter
Configuration
Memory
Location
0:6:0-7
Description
The host processor configures the transmitter by writing a control byte Into the transmltter configuration register In Its Interface memory space. (See TSB.)
Transmitter Configuration Control Codes
Control codes for the modem transmitter configurations are:
Configuration
V27 bis/ter
V29
Configuration Code (Hex)
FT/2400
lC
lA
19
OA
09
4800
2400
4800
2400
14
12
11
22
21
02
01
FT/9600
FT/7200
FT/4800
FT/4800
9600
7200
4800
(None)
Transmitter Data
0:0:0-7
long
long
short
short
2400/4800 bps GearshiftIV.29 Scrambler
2400/4800 bps GearshiftIV.27 bis/ter Scrambler
61
41
V.21 Channel 2
See FSKT
Tone transmit
80
The host processor conveys output data to the transmitter in the parallel mode by
writing a data byte to the transmitter data register. The data is divided on baud boundaries, as follows:
Note: Data is transmitted bit zero first.
Bits
Configuration
V.29 9600 bps
7
I
6
5
I4
3
I
2
Baud 1
Not Used
Baud 3
V.27 4800 bps
Not Used
V.27 2400 bps
Baud 3
Baud 2
Baud 1
2400 bps Gearshift
Baud 3
Baud 2
Baud 1
Baud 1
Baud 1
I
V.29 7200 bps
V.29 4800 bps
4800 bps Gearshift
I
1
I
0
Baud 0
Baud 2
Baud 1
Baud 1
I
Baud 0
I
Baud 0
Baud 0
I
I
Baud 0
Baud 0
Baud 0
TSB
Transmitter Setup
Bit
0:E:3
When the host processor changes the transmitter configuration, the SEPT bit or the
FSKT bit, the host must write a one In this control bit. TSB goes to a zero when the
change becomes effective. Worst case setup time is 2 baud + turnoff sequence +
training (If applicable).
TTDIS
Transmitter Train
Disable
0:7'6
When control bit TTDIS is a one, the transmitter does not generate a training sequence
at the start of transmission. With training disabled, RTS/CTS delay IS less than two
baud times.
XCEN
External Clock
Enable
0:7:1
When control bit XCEN IS a one, the transmitter timing IS established by the external
clock supplied at the hardware input XTCLK, pin 22A.
2-116
9600 bps Fast Train Modem
R96FT/SC
paR can be connected to a user supplied power-on-reset signal
In a wire-or configuration. A low active pulse of 3 "sec or more
applied to the paR pin causes the modem to reset. The modem
IS ready to be configured 10 msec after paR IS removed.
The following is a list of the configurations that may be used
with the forward channel and the states of the various control
bits.
Transmitter Control
Configuration
FTIV. 29/9600
FTIV. 29/7200
FTIV.29/4BOO
FTIV.27/4BOO
FTIV.27/2400
'V.27/4BOO
'V.27/2400
V.21 FSK
PCF
CF
0:9:5
0:9:3
1
1
1
0
0
0
0
X
'Both V.27 long and short train may be
Receiver
Control
PERFORMANCE
SCEN
1 :7:2
1
1
1
X
X
X
X
X
used. X = Don't
Whether functioning in V.27, V.29 or the proprtetary fast train
configurations, the R96FT/SC provides the user with high
performance.
1
1
1
1
1
1
1
1
care.
POLLING SUCCESS
In the 9600 bps fast train configuration the modem approaches
a 98% success rate over unconditioned 3002 lines for a signalto-noise ratio of 26 dB, with a received signal level of - 20 dBm.
When used in conjunction with the 75 bps forward channel,
9600 bps main channel polling performance degrades by
approximately 2 dB.
Note that CCITT V.29 and Gearshift configurations cannot be
used with the forward channel.
BIT ERROR RATES
The Bit Error Rate (BER) performance of the modem is specified
for a test configuration conforming to that specified in CCITT
Recommendation V.56. Bit error rates are measured at a
received line signal level of - 20 dBm as illustrated.
POWER-ON INITIALIZATION
When power is applied to the R96FT/SC, a period of 50 to
350 ms is required for power supply settling. The power-on-reset
signal (paR) remains low during this period. Approximately
10 ms after the low to high transition of paR, the modem is ready
to be configured, and RTS may be activated. If the 5 Vdc power
supply drops below 3.5 Vdc for more than 30 msec, the paR
cycle is generated.
PHASE JITTER
At 2400 bps, the modem exhibits a bit error rate of 10 - 6 or less
with a signal-to-noise ratio of 12.5 dB in the presence of 15°
peak-to-peak phase jitter at 150 Hz, or with a signal-to-noise ratio
of 15 dB in the presence of 30° peak-to-peak phase jitter at
120 Hz (scrambler Inserted).
At 4800 bps (V.27 bislter), the modem exhibits a bit error rate
of 10- 6 or less with a signal-to-noise ratio of 19 dB in the
presence of 15° peak-to-peak phase jitter at 60 Hz.
At paR time the modem defaults to the following configuration:
fast train, V.29, 9600 bps, no echo protector tone, 1700 Hz carrier frequency, scrambled ones segment disabled, serial data
mode, internal clock, cable equalizers disabled, transmitter
digital delay equalizer disabled, link amplitude equalizer disabled, link delay equalizer disabled, transmitter output level set
to - 1 dBm ± 1 dB, interrupts disabled, receiver threshold set
to - 43 dBm, and train-on-data enabled.
At 9600 bps, the modem exhibits a bit error rate of 10- 6 or less
with a signal-to-noise ratio of 23 dB in the presence of 10° peakto-peak phase jitter at 60 Hz. The modem exhibits a bit error
rate of 10- 5 or less with a signal-to-noise ratio of 23 dB in the
presence of 20° peak-to-peak phase jitter at 30 Hz.
2-117
R96FT/SC
9600 bps Fast Train Modem
An example of the SER performance capabilities is given in the
following diagrams:
I
4800 BPS
V.27
240014800 BPS
AND
7200 BPS GEARSHIFT
V.29
9600 BPS
300 BPS 2400 BPS 4800 BPS
V.29
V.21
V.27
V.29
4000 BPS
V.29
1
10- 3
I
10- 3
V
\ I
2400/480 o BPS
GEARS HIFT
AND
1200 BPS
300 BPS
V.21
yg
2400 BPS ""000 BPS
V.21
V.21
1'1
9600 BPS
V.29
I
I
IY
\
10-'
w
10-'
\
I-
0(
a:
a:
0
a:
a:
w
w
I0(
a:
a:
0
a:
a:
w
.,
l-
I-
iii
iii
10- 5
10- 5
,
10- 6
0
2
4
20
22
24
2
Typical BER Performance
Back-to-Back, - 20 dBm Receive Signal Level
The SER performance test set-up is shown
In
MODEM
TRANSMITTER
I---
LINE
SIMULATOR
(3002)
4
6
10 12 14 16 18 20
8
SIGNAL TO NOISE RATIO (dB)
22
24
26
Typical BER Performance
3002 Unconditioned Line, - 20 dBm Receive Signal Level
the following diagram:
300-3~OO
NOISE
SOURCE
GR1381
5 KHZ BW
\
\
10- 6
8 10 12 14 16 18
6
SIGNAL TO NOISE RATIO (dB)
HZ
~
FILTER
COMSTRON
FA2874
I---
ATTENUATOR
HP350D
I---
IMPAIRMENT
SOURCE
BRADLEY 2A
AND 2B
r--
ATTENUATOR
HP 3500
I
!----
E
;--
LEVEL
METER
HP3555B
r-'---
MODEM
RECEIVER
I
I
I
MODEM
TEST SET
PHOENIX 5000
~-----------------~
BER Performance Test Set-up
2-118
R96FT/SC
9600 bps Fast Train Modem
GENERAL SPECIFICATIONS
Modem Power Requirements
Voltage
Tolerance
Current (TypiCal) @ 25°C
Current (Max) @ OOC
+5 Vdc
+ 12 Vdc
-12 Vdc
±5%
±5%
±5%
650 mA
50 mA
60 mA
<820 mA
< 80 mA
< 90 mA
Note: All voltages must have ripple '" 0.1 volts peak-to-peak.
Modem Environmental Restrictions
Specification
Parameter
Temperature
Operating
Storage
O°C to + 60°C (32°F to 140°F)
- 40°C to + ao°c ( - 40°F to 176°F) (Stored in heat sealed antistatic bag and shipping
container)
Up to 90% noncondensmg, or a wet bulb temperature up to 35°C, whichever is less
- 200 feet to + 10,000 feet
Relative Humidity:
Altitude
Modem Mechanical Considerations
Specification
Parameter
Single PC board with a 3-row 64-pln right angle male DIN connector with rows A and C populated.
The modem can also be ordered with the following DIN connector: 64-pm DIN right angle female,
64-pin DIN vertical male or 64-pin DIN vertical female.
Board Structure'
Mating Connector:
Female 3-row 64-pm DIN receptacle with rows A and C populated. TYPical mating receptacle:
Winchester 96S-6043-0531-1, Burndy R196B32ROOAOOZ1, or equivalent.
PCB Dimensions:
Width
Length
Height
Weight (max):
Lead Extrusion (max.)
3.937 In. (100 mm)
6.300 In. (160 mm)
0040 m. (10.2 mm)
5.5 oz (156 g)
0.100 in. (2.54 mm)
/
0.156 ±0.003 DIA (4 PL)
(3.96)
1
r
I
3.937
l;::
__ 0.496
-
I
0(~~91
(12.6)
i
~~~-====~===-~=-~~I
J.
_t_~.1 1-- 0.483
5.675
6.300 _ _
(1_44_)_ _ _ _ _
I.~
f + - - - - - - - (160)
I,
(12.3)
UNITS: INCHES
mm
R96FTlSC Modem Dimensions and Pin Locations
2-119
1NTROOUCrt6N~
·.TheAockIV$IlR1440Plsa~yMnrOl\OUSCCfTTv.33~m.IUs'·
. designed to operate,~ ~Joned or oondltionec! 1Inee.
throughth&a~e Ilnetetminatkin.ltls~ Inasll1all
module with .• DIN connectOr, .01' aslI1aII~ mOd!Jle With dl~hl"" .
line pin (OlP}CiIltiEi$
.
- CC1Tl! V.32. V.22bis, V.22, end V.21
-. BeU: Be11212A
.
• SynchronousJAsynthronouS .
• 2-Wire Fwl.oup/ex
.•.. . .
• Trellis Coded MOdulation (TOM).
• Neat and Far End Echocancellatlon
• . Automatic HMdsbake Recognition
• AuiO-.D!aI and AutO-Answer .
• on:
l/1!erfac.l!
. ' ..
....: Functional: CCITT V.24 (RS-232-CY .(Data/Control). and
Microprocessor Bus (OaialConfiguratlonlControl)'
m
~Eleotrlcel:
aII(I CMOS Compatible
• D~mlc Rai1ge: .. 43'dBm to 0 d8m
... kitOniatlcAdaptive Equalizer
'. Diagnostic Capability
• 1.I:Jopback'
- Local arld Remote. AnatoS
· -:;'REfniOle.DlQitaI
.. Small Size .
- ~mm)( 100mm(3.23in.x3.94ln.)wltbDIPConAi9ctlCn
• PQWer Consumption: 2 W (Typical}
.
•
R96t6DP Modem
Document ~'. 2931JQN07
Qrder No. 801.
February 1987
V.32 Ultra High Speed Modem
R9696DP
RTS
CTS
TXD
TDCLK
XTCLK
RLSD
RXD
RDCLK
TBCLK ,.,
RBCLK
r----~
r
I
I
I
I
USRT
(OPTIONAL)
L_-
.....-T
r-.
I.
"
READ
WRITE
DATA BUS (8)
ADDRESS BUS (5)
HOST
PROCESSOR
(DTE)
~
I
DECODER
r
CS(3)
POR
IRQ
(
+5
'AA.
0·0·
SCOPE
R9696DP
MODEM
-"
EYEX
EYEY
EYESYNC
EYECLK
+12V
+5V
GND
-12V
TXA
RXA
.r.
h
X.
EYE
PATTERN
GENERATOR
POWER
SUPPLY
LINE
J INTERFACE
} TELEPHONE
LINE
"
J
R9696DP Functional Interconnect Diagram
SPECIFICATIONS
Power Requiraments
Environmental
+5 Vdc ±5 0k ,: ;' ":t .
,>,
.\,
":'.1, '
',"<
,
:"
::"",
' ..
','
:>'~".':, >- :"" ;"" R1496u.. ,': .... :.. :' ":; --,' ,
,,: 'Y~:a:t: ;,". 3~·~· Hitt$I).td~·~em·
,
,
..
, ' ; , . " '
.....
",,'
t
','
•
,
"
,~/ .... ~
,.
,
",
"
l
•
tfkt:,.\" :,:~.,.: :::'~>.,.: ~ " <".... :'~.-.-:
"
'J,'"
"..
• "
'"
•
,.,~u...~'.,":
,'
:;~t!~7,":jt>,::.'Ibe~I~~,~~:!;~~;~rOnouIl. ~t,
" .;:: 'il,", » ,;: ;' syJiC~
'.
. V_ .ai\d}I.32· ir\odem,
It ;1$' _tgned 10 .
t.::~~)::.',·~':'··:· :'~~;;==,~~=~!~::
~_' .. ~ln .,~~I ~ W\th~n!! (DIP) OOtmectk»L ,.
.,
'. for dI~,~,Ohto·~ ~ 1tIO
.
',',
."
),
,~""
,
"',
'
. \:
.
,
'~'
'.
"<,
'
,~
I,·
,,',";
,
.
"
"
.. "
".
"
-'-:"
.: " ,
.'
';
'~
"",.'
.... : ,~.,
7:--~,
.' , , -
,,:~;,
~
•
<
:'
"
:.~.'
'....
~""
.'
' . "Y
,,:,,'
.' .
,:"
,.. ..... :
,,'
'.>
'.,
'
~.
";", ,
'
, '. ' •. "'.,\ <,
',':
,'"
,~
.
,.'
"
,
~
..
"r.
",
.
::~~;:f;~If;·iYil.~~:·:~~~~>,:<~:i;~~':· f?>.·, .:,.~~.,,~ ';
f,
'
...:,:
~:.: /. ;;' .;cL .:,~~'~/J;/\:~
. FtbNary 'nW1 .
.,
:'., ,
,
..
~
'
{
'.
,
(
R1496MM
V.33, V.32 Ultra High Speed Modem
RTS
CTS
TXD
TDCLK
XTCLK
r----~
r
I
I
I
USRT
(OPTIONAL)
r
I
L_-
.......
T
h
0
'0'
SCOPE
RLSD
RXD
RDCLK
TBCLK
RBCLK
,~
['"
READ
WRITE
DATA BUS (8)
I
DECODER
+5
""'V'
+12V
+5V
GND
TXA
RXA
POR
IRQ
~
EYECLK
J
POWER
SUPPLY
-12V
CS(3)
r
h
EYE
PATTERN
GENERATOR
EYESYNC
R1496MM
MODEM
ADDRESS BUS (5)
HOST
PROCESSOR
(DTE)
X~
EYEX
EYEY
I
LINE
INTERFACE
}
TELEPHONE
LINE
I)
b
R1496MM Functional Interconnect Diagram
SPECIFICATIONS
Power Requirements
Environmental
+5 Vdc ±5% <650 mA
+12 Vdc ±5% < 10 mA
-12 Vdc ±5% < 70 mA
Temperature: Operating O°C to 60°C
Storage - 40°C to 80°C
Relative Humidity: Up to 90% noncondensing, or a wet bulb temperature up to 35°C, whichever is less,
2-125
2-126
SECTION 3
IMAGING MODEMS
i"j
I!
Page
Imaging Modems .............................................................. .
3-1
Product Family Overview ...................................................... .
3-2
R24MFX 2400 bps MONOFAX Modem .......................................... .
3-3
R24BKJ 2400 bps V.26 bis Modem ............................................. . 3-19
R48MFX 4800 bps MONOFAX Modem .......................................... . 3-35
R48PCJ 4800 bps PC Communication Modem ................................... . 3-51
R24/48MEB Modem Evaluation Board ........................................... . 3-67
R96PCJ 9600 bps PC Communication Modem ................................... . 3-80
R96F 9600 bps Facsimile Modem .............................................. . 3-93
R96MD 9600 bps Facsimile Modem ............................................ . 3-112
R144HD 14400 bps Half-Duplex Modem ........................................ . 3-130
R96MFX 9600 bps MONOFAX Modem .......................................... . 3-144
3-1
!!
Ii
•
I
IMAGING MODEMS
Leading the World in Facsimile Modems
4800 bps, are the world's first single-package modems
designed for the emerging personal facsimile market.
In addition, Rockwell offers single device modems for other
imaging applications. The R48PCJ, a V.27 ter modem with
both long and short training options, is designed for
applications in personal computer communication, teletex and
intelligent workstations. The R24BKJ, a V.26 bis modem, is
designed for applications in banking terminals and intelligent
workstations.
Continuing our digital communications leadership role,
Rockwell has introduced a 14.4 Kbps half-duplex modem for
general switched telephone line operation. This high
performance, ultra high speed product introduction further
establishes Rockwell as a leader in setting standards for the
facsimile modem industry.
Rockwell is the world leader in the production and sale of
highly integrated 9600 bps Group 3 facsimile modems. We are
a major supplier to Japanese facsimile manufacturers and have
been a key factor in "driving" signal processor (SP) and
integrated analog (IA) technology.
Rockwell's R96F - a half-duplex, dial-up, 9600 bps,
synchronous modem - is the industry standard for facsimile
image transmission. Its compact size, unexcelled performance
and proven reliability record have made it the choice of every
major facsimile manufacturer since its introduction in 1984.
The R96F is designed for use in Group 3 facsimile machines
and is also compatible with Group 2 machines.
In response to market demands for smaller facsimile
machines, Rockwell has introduced a line of single-package,
64-pin QUIP, facsimile modems. The R24 MONOFAX,
operating at 2400 bps, and the R48 MONOFAX, operating at
Model
Data Speed
(bps)
PSTNI
Leased
Line
2/4-Wire
Half/Full-Duplex
Sync/Async
Compliance
R24MFX
2400,300
P/L
2WHD
Sync
CCITT V.27 ter Fallback,
V.21 Channel 2,
R24BKJ
2400
P/L
2WHD
Sync
CCITT V.26 bis,
Bell201C
R48MFX
4800,2400,
300
P/L
2WHD
Sync
CCITT V.27 ter,
V.21 Channel 2,
T.4, T.30
R48PCJ
4800,2400,
300
P/L
2WHD
Sync
CCITT V.27 ter Short Train,
V.21 Channel 2,
T.4, T.30
R96PCJ
9600,7200,
4800,2400
300
P/L
2WHD
Sync
CCITT V.29, V.27 ter Short Train,
V.21 Channel 2,
T.4, T.30
R96F
9600,7200,
4800,2400
300
P/L
2WHD
Sync
CCITT V.29, V.27 ter,
V.21 Channel 2,
T.3, T.4, T.30
R96MD
9600,7200,
4800,2400
300
P/L
2WHD
Sync
CCITT V.29, V.27 ter,
V.21 Channel 2,
T.3, T.4, T.30
R144HD
14400,12000,
9600,7200,
4800,2400,
300
P/L
2WHD
Sync
CCITT V.33, V.29, V.27 ter,
V.21 Channel 2,
T.3, T.4, T.30
R96MFX
9600,7200,
4800,2400
300
P/L
2WHD
Sync
CCITT V.29, V.27 ter,
V.21 Channel 2,
T.4, T.30
3-2
R24MFX
MONOFAX'" Modems
'1'
R24MFX
2400 bps MONOFAXTM Modem
Rockwell
1.1
INTRODUCTION
FEATURES
The R24MFX MONOFAX 24 is a synchronous, serial/parallel,
2400 bps modem in a single 64-pin quad in-line package (QUIP).
The modem is designed for operation over the public switched
telephone network with appropriate line terminations, such as
a data access arrangement, provided externally.
•
•
•
•
•
•
•
•
The R24MFX satisfies the telecommunications requirements
specified in CCITT Recommendation V.27 ter fallback
(2400 bps), T.4 and the binary signaling capabilities of Recommendation T.30.
'" MONOFAX is a trademark of Rockwell International
RSO
RS1
RS'
RS3
WRITE
cs
READ
IRQ
DO
01
D.
03
04
05
OS
D7
OGN02
RCVO
RTS
NC
SCLKO
PORO
RCI
SYNCINI
DAIN
XTLI
XTLO
+5VD
RXO
TXO
OAOUT
AOIN
RCVl2
CTS
RLSO
OCLK
SYNCOUT
NC
DGNOt
AGCIN
AGNO
-SVA
AUXI
ADOUT
FOUT
TXOUT
SCLKIN.
RXIN
AOUT
FIN
DGND4
SCLKINI
+5VA
RCYI1
CABLEI
NC
Single 64-Pin QUIP
CCITT V.27 ter Fallback, T.30, V.21 Channel 2, T.4
Group 3 Facsimile Transmission/Reception
Half-Duplex (2-Wire)
Programmable Dual Tone Generation
Programmable Tone Detection
Dynamic Range: - 43 dBm to 0 dBm
Diagnostic Capability
- Provides Telephone Line Quality Monitoring Statistics
• Equalization
- Automatic Adaptive
- Compromise Cable (Selectable)
• DTE Interface: Two Alternate Ports
- Microprocessor Bus
- CCITT V.24 (RS-232-C Compatible)
• Low Power Consumption: 1W (Typical)
• Programmable Transmit Output Level
• TTL and CMOS Compatible
The R24MFX is optimized for use in compact Group 3 facsimile
machines. Its small size and low power consumption offer the
user flexibility in creating a 2400 bps modem customized for
specific packaging and functional requirements.
SYNCIN3
NC
PORI
OGNOS
SYNCIN.
NC
NC
OGN03
II
CABLE'
= NO CONNECTION
R24MFX Pin Assignments
Document No. 29200N17
R24MFX 2400 bps MONOFAX Modem
Data Sheet
3-3
Order No. MD17
June 1986
R24MFX
2400 bps MONOFAX Modem
TECHNICAL CHARACTERISTICS
RECEIVE LEVEL
The receiver circuit of the R24MFX satisfies all specified performance requirements for received line signal levels from 0 dBm
to - 43 dBm. An external input buffer and filler must be supplied between the receiver analog input (RXA) and the R24MFX
RXIN pin. The receivee:! line signal level is measured at RXA.
TONE GENERATION
Under control of the host processor, the R24MFX can generate single or dual frequency voice band tones up to 3600 Hz
with a resolution of 0.11 Hz and an accuracy of 0.01 %. The
transmit level and frequency of each tone is independently
programmable.
RECEIVE TIMING
Single frequency tones are detected by a programmable filter.
The presence of energy at the selected frequency is indicated
by a bit in the interface memory.
In the receive state, the R24MFX provides a Data Clock (DClK)
output in the form of a square wave. The low to high transitions
of this output coincide with the centers of received data bits.
The timing recovery circuit is capable of tracking a ± 0.01 % frequency error in the associated transmit timing source. DClK
duty cycle is 50% ± 1%.
SIGNALING AND DATA RATES
TRANSMIT LEVEL
TONE DETECTION
Signaling/Date Rates
Configuration
Parameter
Specification
(± 0.01%)
V.27
Signaling Rate
Data Rate
1200 Baud
2400 bps
V.21
Signaling Rate
Data Rate
300 Baud
300 bps
The transmitter output level is programmable. An external output buffer and filter must be supplied between the R24MFX
TXOUT pin and the transmitter analog output (TXA). The default
level at TXA is + 5 dBm ± 1 dB. When driving a 600 ohm load
the TXA output requires a 600 ohm series resistor to provide
- 1 dBm ± 1 dB to the load.
TRANSMIT TIMING
In the transmit state, the R24MFX provides a Data Clock (DClK)
output with the following characterisiics:
DATA ENCODING
At 1200 baud, the 2400 bps data stream is encoded into dibits
per CCITT V.27 ter.
1. Frequency: Selected data rate of 2400 or 300 Hz (± om %).
2. Duty Cycle: 50% ± 1%.
At 300 baud, the data stream is 300 bps FSK per CCITT V.21
channel 2.
Transmit Data (TXD) must be stable during the 1 microsecond
periods immediately preceding and following the rising edge of
DClK.
COMPROMISE CABLE EQUALIZERS
TURN-ON SEQUENCE
In addition to the adaptive equalizer, the R24MFX provides selectable compromise cable equalizers to optimize performance over
three different lengths of non-loaded cable of 0.4 mm diameter
(1.8 km, 3.6 km, and 7.2 km).
Three turn-on sequences are generated by the R24MFX, as
defined in the following table:
Turn-On Sequences
Cable Equalizer Nominal Gain
Frequency
(Hz)
700
1500
2000
3000
Gain (dB) Relative to 1700 Hz
1.8 km
3.6 km
7.2 km
-0.99
-0.20
+0.15
+ 1.43
-2.39
-0.65
+0.87
+3.06
-3.93
-1.22
+1.90
+4.58
Comments
Bit Rate.
1
300 bps
<14
No Training
Sequence
2
2400 bps2
943
No Echo
Protector Tone
3
2400 bps2
1148
Preceded'
By Echo
Protector Tone
TRANSMITTED DATA SPECTRUM
When operating at 1200 baud, the transmitter spectrum is
shaped by a square root of 90% raised cosine filer.
RTS-CTS
Time (ms)
No.
Notes:
1. Turn-on sequence 3 is used on lines with protection
against talker echo.
2. V.27 ter long trainmg sequence only.
The out-of-band transmitter power limitations meet those specified by Part 68 of the FCC's Rules, and typically meet the
requirements of foreign telephone regulatory agencies.
TURN-OFF SEQUENCE
For V.27 ter, the turn-off sequence consists of approximately
10 ms of remaining data and scrambled ones at 1200 baud,
followed by a 20 ms period of no transmitted energy. In V.21
the transmitter turns off within 7 ms after RTS goes false.
SCRAMBLER/DESCRAMBLER
The R24MFX incorporates a self-synchronizing scrambler/
descrambler. This facility is in accordance with CCITT V.27 ter.
3-4
R24MFX
2400 bps MONOFAX Modem
CLAMPING
Receiver threshold is programmable over the range 0 dBm to
- 50 dBm, however, performance may be at a reduced level
when the received signal IS less than - 43 dBm.
The following clamps are provided with the R24MFX:
1. Received Data (RXD). RXD is clamped to a constant mark
(1) whenever RLSD is off.
2. Received Line Signal Detector (RLSD). RLSD is clamped off
(squelched) whenever RTS IS on.
A minimum hysteresis action of 2 dB exists between the actual
off-to-on and on-to-off transition levels. The threshold levels and
hysteresIs acllOn are measured with an unmodulated 2100 Hz
tone applied to RXA.
RESPONSE TIMES OF CLEAR-TO-SEND (CTS)
POWER
The time between the off-to-on transition of RTS and the off-toon tranSItion of CTS is dictated by the length of the training
sequence. Response time is 943 ms for V.27 ter at 2400 bps.
In V.21 CTS turns on in 14 ms or less.
Voltage Tolerance Current (Max) @ 25°C Current (Max) @ 60°C
+5 Vdc
-5 Vdc
±5%
±5%
250 rnA @ 5.0 Vdc
25 rnA @ -50 Vdc
225 rnA @ 50 Vdc
25 rnA @ -5.0 Vdc
Note: All voltages must have ripple :s0.1 volts peak-to-peak. If
a sWitching supply is chosen, user may select any frequency
between 20 kHz and 150 kHz so long as no component of the
sWitching frequency IS present outside of the power supply with
an amplitude greater than 500 microvolts peak
The time between the on-to-off transition of RTS and the on-tooff transition of CTS in the data state IS a maximum of 2 baud
times for all configurations.
RECEIVED LINE SIGNAL DETECTOR (RLSD)
ENVIRONMENTAL
RLSD turns on at the end of the training sequence. If training
is not detected at the receiver, the RLSD off-to-on response time
is 674 ± 10 ms. The RLSD on-to-off response time is 10 ±5 ms.
Response times are measured with a signal at least 3 dB above
the actual RLSD on threshold or at least 5 dB below the actual
RLSD off threshold.
Parameter
Temperature
Operatmg
Storage
r
---
RTS
CABLE2
r
CABLE 1
I""
USRT
(OPTIONAL)
L
TXD
I
DCLK
AUXI
XTLO
I
RLSD
~
I
L
CTS
r-
I
I
I
o
RXD
XLTI
TXOUT
R24MFX
MONOFAX
MODEM
WRITE
RXIN
r
DATA BUS (8)
ADDRESS BUS (4)
~h
CLOCK
- . - CRYSTAL
J
U
READ
HOST
PROCESSOR
(DTE)
DoC to + 60°C (32°F to 140°F)
-40°C to +80 oC (-40°F to 176°F) (Stored
in suitable antistatic contamer)
Relative Humidity Up to 90% non condensing, or a wet bulb
temperature up to 35°C, whichever is less.
The RLSD on-to-off response time ensures that all valid data
bits have appeared on RXD.
I
Specification
.r- CS
DECODERf""_
POR
IRQ
+5
,...
+5V
~
,...~
-5V
GND
v\l\rJ
R24MFX Functional Interconnect Diagram
3-5
-
- } TELEPHONE
LINE
LINE
INTERFACE
2400 bps MONOFAX Modem
R24MFX
INTERFACE CHARACTERISTICS
gates, the interface can be made compatible with a wide variety
of microprocessors such as 6500, 6800, or 68000.
The modem interface comprises both hardware and software
circuits. Hardware circuits are assigned to specific pins on the
64-pin QUIP. Software circuits are assigned to specific bits in
a 16-byte interface memory.
The microprocessor interface allows a host microprocessor to
change modem configuration, read or write channel data as well
as diagnostic data, and supervise modem operation by means
of software strappable control bits and modem status bits. The
significance of the control and status bits and methods of data
interchange are discussed in the Software Circuits section.
HARDWARE CIRCUITS
Signal names and descriptions of the hardware circuits, including
the microprocessor interface, are listed in the R24MFX Hardware Circuits table; the table column titled 'Type' refers to
designations found in the Digital and Analog Interface Characteristics tables.
V.24 Interface
Seven hardware Circuits provide timing, data and control signals
for implementing a serial interface compatible with CCITT
Recommendation V.24. These signals interface directly with circuits using TTL logic levels (0, + 5 volt). These TTL levels are
suitable for driving the short wire lengths or printed circuitry
normally found within stand-alone modem enclosures or equipment cabinets.
Microprocessor Interface
Sixteen hardware circuits provide address (RSO-RS3), data
(00-07), control (CS, READ and WRITE) and interrupt (IRQ)
signals for implementing a parallel interface compatible with an
8080 microprocessor. (Refer to the Microprocessor Interface
Timing Waveforms figure and Microprocessor Interface Timing
Requirements table.) With the addition of a few external logic
In applications where the modem is operated in parallel data
mode only (I.e., where the V.24 signals are unused), all V.24
pins may remain unterminated.
R24MFX Hardware Circuits
Name
Type
Pin No.
Description
Name
AGND
DGND1
DGND2
DGND3
DGND4
DGND5
+5 VA
+5 VD
-5 VA
GND
GND
GND
GND
GND
GND
PWR
PWR
PWR
24
22
Connect
Connect
Connect
Connect
Connect
Connect
Connect
Connect
Connect
48
8
29
4
31
11
25
to
to
to
to
to
to
to
to
to
Analog Ground
AGND Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Analog + 5V Power
Digital + 5V Power
Analog - 5V Power
I/OA
I/OA
I/OA
I/OA
I/OA
I/OA
I/OA
I/OA
49
50
51
52
53
54
55
56
RS3
RS2
RS1
RSO
IA
IA
IA
IA
61
62
63
64
CS
READ
WRITE
IRQ
IA
IA
IA
OB
59
58
60
57
Chip Select
Read Strobe
Write Strobe
Interrupt Request
19
46
17
13
12
18
Data Clock
Request-to-Send
Clear-to-Send
Transmitter Data Signal
Receiver Data Signal
Received Line Signal Detector
32
33
Cable Select 1
Cable Select 2
}
}
OC
IB
OC
IB
OC
OC
Data Bus (8 Bits)
Register Select (4 Bits)
Select Reg. 0 - F
IC
IC
Connect to Output Op Amp
Connect to Input Op Amp
Auxiliary Analog Input
IIOB
IIOB
R*
43
3
10
9
47
34
16
44
30
38
36
23
14
40
39
15
27
35
20
41
Power-On-Reset Output
Power-On-Reset Input
Connect to Crystal Circuit
Connect to Crystal Circuit
Receive Mode Output
Connect to RCVO
Connect to RCVO
Switched Capacitor Clock Output
Connect to SClKO
Connect to SClKO
Smoothing Filter Output
AGC Input
DAC/AGC Data Out
Connect to DAOUT
ADC Output
Connect to ADOUT
Smoothing Filter Output
Connect to FOUT
Sample Clock Output
Connect to SYNCOUT
Connect to SYNCOUT
Connect to SYNCOUT
RC Junction for POR Time
Constant
W
W
W
W
W
W
R*
R*
W
R*
R*
R*
R*
W
R*
R*
W
R*
R*
R*
5
1
42
G. RESERVED
R*
W
W
W
W
D. CABLE EQUALIZER:
CABlE1
CABlE2
28
37
26
F.OVERHEAD
PORO
PORI
XTlO
XTU
RCVO
RCVl1
RCVI2
SClKO
SClKIN1
SClKIN2
AOUT
AGCIN
DAOUT
DAIN
ADOUT
ADIN
FOUT
FIN
SYNCOUT
SYNCIN1
SYNCIN2
SYNCIN3
RCI
C. V.24 INTERFACE:
DClK
RTS
CTS
TXD
RXD
RLSD"
Description
Pin No.
AA
AB
AC
TXOUT
RXIN
AUXI
B. MICROPROCESSOR INTERFACE:
D7
D6
D5
D4
D3
D2
D1
DO
Type
E. ANALOG SIGNALS:
A. POWER:
2
6
7
21
45
Do
Do
Do
Do
Do
Not
Not
Not
Not
Not
Connect
Connect
Connect
Connect
Connect
OR = Required overhead connectIon; no connection to host equipment.
3-6
R24MFX
2400 bps MONOFAX Modem
Digital Interface Characteristics
Type
Input
Symbol
Parameter
VIH
Input Voltage, High
VIL
VOH
VOL
liN
10H
10L
IL
Ipu
Input Voltage, Low
Output Voltage, High
Output Voltage, Low
Input Current, Leakage
Output Current, High
Output Current, Low
Output Current, Leakage
Pull-up Current
(Short Circuit)
Capacitive Load
Capacitive Drive
Circuit Type
CL
CD
Output
Units
IA
IB
IC
OA
V
2.0 min.
2.0 min.
2.0 mm
V
V
V
p.A
rnA
rnA
pA
pA
0.8 max.
0.8 max.
0.8 max.
2.4 min.'
0.4 max. 2
OB
Input/Output
OC
0.4 max. 2
0.4 max. 2
1.6 max.
±10 max.
1.6 max.
±2.5 max.
-0.1 max.
1.6 max.
pF
pF
5
-240 max.
-10min.
5
-240 max.
-10min.
20
TTL
w/Pull-up
TTL
w/Pull-up
TTL
Notes
1. I load = -100pA
2. I load = 1.6 rnA
3. I load = -40 pA
4. VIN s 0.4 to 2.4 Vdc, Vcc
5. I load = 0.36 rnA
IIOB
2.0 min.
5.25 max.
2.0 min.
0.8 max.
2.4 min.3
0.4 max. S
0.8 max.
2.4 min.'
0.4 max. 2
±12.5 max.
-240 max.
-10 min.
100
TTL
s
IIOA
-260 max.
-100 min.
10
40
100
100
100
100
Open-Drain Open Drain
3 State
Open-Drain
w/Pull-up Transceiver w/Pull-up
5.25 Vdc
Analog Interface Characteristics
Analog Interface Characteristics
Name
Type
Characteristics
TXOUT
AA
The transmitter output can supply a
maximum of ± 3.03 volts into a load
resistance of 10k II minimum. In order to
match to 600 II, an external smoothing
filter with a transfer function of
15726.43/(S + 11542.44) and 604 II senes
resistor are required.
RXIN
AUXI
AB
AC
READ
The receiver input impedance is greater
than 1M II. An external antialiasing filter
with a transfer function of
19533.88/(S+ 11542.44) is required.
WRITE
RSi
(I
The auxiliary analog input allows access
to the transmitter for the purpose of
interfacing with user provided equipment.
Because this IS a sampled data input,
any signal above 3600 Hz will cause
aliasing errors. The mput impedance is
1M II, and the gain to transmitter output
(TXA) is + 5.6 dB ± 1 dB.
= 0-3)
READ
Note: Absolute maximum voltage ratings for analog inputs are:
(-5 VA - 0.3) s VIN S (+5 VA + 0.3)
Microprocessor Interface Timing Requirements
Characteristic
CS, RSi setup lime prior
to READ or WRITE
Data Access time after READ
Data hold time after READ
CS, RSi hold time after
READ or WRITE
Write data setup time
Write data hold time
WRITE strobe pulse width
Symbol
Min
TCS
TDA
TDH
10
TCH
TWOS
TWDH
TWR
10
75
10
01
Max
Units
30
-
-
140
50
ns
ns
ns
-
ns
ns
ns
ns
75
(I
= 0-7)
Microprocessor Interface Timing Waveforms
3-7
R24MFX
2400 bps MONOFAX Modem
Cable Equalizers
SOFTWARE CIRCUITS
Modems may be connected by direct wiring, such as leased
telephone cable or through the public switched telephone network, by means of a data access arrangement. In either case,
the modem analog signal is carried by copper wire cabling for
at least some part of its route. The cable characteristics shape
the passband response so that the lower frequencies of the passband (300 Hz to 1700 Hz) are attenuated less than the higher
frequencies (1700 Hz to 3300 Hz). The longer the cable the more
pronounced the effect.
The R24MFX contains 16 memory mapped registers to which
an external (host) microprocessor has access. The host may read
data out of or write data Into these registers. Refer to the R24MFX
Host Processor Interface figure.
When information in these registers is being discussed, the format Z:Q is used. The register is specified by Z{O-F), and the bit
by Q{0-7, 0 = LSB). A bit is considered to be "on" when set to
a one (1) and "off" when reset to a zero CO).
To minimize the impact of this undesired passband shaping, a
compromise equalizer with more attenuation at lower frequencies than at higher frequencies can be placed in series with the
analog signal. The modem includes three such equalizers
designed to compensate for cable distortion.
Status/Control Bits
The operation of the R24MFX is affected by a number of software control inputs. These Inputs are written into registers within
the interface memory via the host microprocessor bus. Modem
operation is monitored by various software flags that are read
from Interface memory via the host microprocessor bus.
Cable Equalizer Selection
CABLE1
CABLE2
0
0
0
0.0
1
1
1
0
1.8 km
3.6 km
7.2 km
1
Length of O.4mm Diameter Cable
All status and control bits are defined in the R24MFX Interface
Memory Map table. Bits deSignated by , - ' are reserved for
modem use only and must not be changed by the host.
Anyone of the registers may be read or written on any host read
or write cycle, but all eight bits of that register are affected. In
order to read a single bit or a group of bits in a register, the host
processor must mask out unwanted data. When writing a single
bit or group of bits in a register the host processor must perform
a read-modify-write operation. That is, the entire register is read,
the necessary bits are set or reset in the accumulator of the host,
then the original unmodified bits and the modified bits are written
back into the register of the interface memory.
Analog Signals
Three analog signals provide the interface pOint for telephone
company audio circuits and host audio inputs. Signals TXOUT
and RXIN require buffering and filtering to be suitable for driving
and receiving the communication channel. Signal AUXI provides
access to the transmitter for summing host audio signals with
the modem analog output.
The filters required for anti-aliasing on the receiver input and
smoothing on the transmitter output have a single pole located
at 11,542 radians. Although this pole is located within the modem
passband, internal filters compensate for its presence and,
therefore, the pole location must not be changed. Some variation from recommended resistor and capaCitor values is permitted as long as the pole is not moved, overall gain is preserved,
and the device is not required to drive a load of less than 10k O.
Configuration Control
Notice that when reference is made to signals TXA, RXA, and
AUXIN, these signals are not electrically identical to TXOUT,
RXIN, and AUXI. The schematic of the recommended modem
interface circuit illustrates the differences.
When the modem is initialized by power-on-reset, the configuration defaults to V.27. When the host wants to change configuration, the new code is written to the configuration field and the
SETUP bit (E:3) is set to a one. Once the new configuration takes
effect, the SETUP bit is reset to zero by the modem.
Three configurations are available in the R24MFX modem: V.27,
V.21, and Tone. These three configurations are selected by
writing an 8-bit binary code into the configuration field (CONF)
of the interface memory. The configuratio,"! field consists of bits
7 through 0 of register D. The code for these bits is: 0 = V.21,
4 = V.27, and 8 = Tone. All other codes represent invalid states.
Overhead
Except for the power-on-reset signal PORO, the overhead
signals are intended for internal use only. The various required
connections are illustrated in the recommended modem interface circuit schematic. No host connections should be made to
overhead signals other than PORO.
The information in the interface memory Is serviced by the
modem at either 1200 times per second or 7200 times per
second depending on configuration. In V.21, the rate is 7200
times per second. In both V.27 and Tone configuration, the rate
is 1200 times per second.
3-8
R24MFX
2400 bps MONOFAX Modem
READ
WRITE
r-
READ
WRITE
LOGIC
8
~8
....
"
"
00-07
~r
I
~LOGIC~
UNIT
·· ···
REGISTER 1
REGISTER 0
INTERRUPT
LOGIC
IRQ
I
SP
REGISTER F _ I/O
REGISTERE_ BUS
···
REGISTER
SELECT
LOGIC
RSO_RS3 4 /
r--
Jo-
--
SP
MAIN
BUS
~
RAM
I
7
5
6
4
3
2
1
0
F
E
ODIE
-
OOREQ
COlE COREQ
-
0
-
RAMW
CONF
C
RTSP
B
RX
A
lOET
9
8
-
7
-
6
-
TPDM lOIS EQSV EQFZ
EPT
FED
GHIT
-
-
CDET
-
-
/
5
'""'-
Channel Data
6 "\,
-
-
When performing parallel data transfer of channel data, the host
and modem can synchronize their operations by handshaking bits
in register E. Bit E:5 (CDREQ) is the channel data request bit.
This bit is set to a one by the modem when receiver data is
available in RXCD or when transmitter data is required in TXCD.
Once the host has finished reading RXCD or writing TXCD, the
host processor must reset CDREQ by writing a zero to that bit
location.
DDYM
,
7
-
-
-
DDXL
!
1
-
-
Parallel Mode-Parallel data is transferred via two registers in
the interface memory. Register 5 (RXCD) is used for receiver
channel data, and Register 4 (TXCD) is used for transmitter channel data. Register 5 is continuously written every eight bit times
when in the receive state. Register 4 is used as the source of
channel transmitter data only when bit C:5 (TPDM) is set to a one
by the host. Otherwise the transmitter reads data from the V.24
interface. Both RTS and RTSP remain enabled, however, regardless of the state of TPDM.
-
DDXM
I
0
PN
-
TXCO
/
2
-
RXCD
/
4
3
i/.:
SETUP
DDYL
5
4
3
2
1
0
When set to a on~ the host, Bit E:6 (CDIE) enables the CDREQ
bit to cause an IRQ interrupt when set. While the IRQ line is
driven to a TTL low level by the modem, bit E:7 (IA) is a one.
Transfe~,
Data sent to or received from ~i1e~ta channel may be transferred
between the modem and host processor-in_either serial or parallel
form. The receiver operates in both serial and parallel mode
simultaneously and requires no mode control bit selection. The
transmitter operates in either serial or parallel mode as selected
by mode control bit C:5 (TPDM).
If the host does not respond to the channel data request within
eight bit times, the RXCD register is over written or the TXCD
register is sent again.
Refer to Channel Data Parallel Mode Control flow chart for recommended software sequence.
3-9
"II
"
"
h....,..
Serial Mode-The serial mode uses a standard V.24 (RS-232-C)
hardware interface (optional USRT) to transfer channel data.
Transmitter data can be sent serially only when TPDM is set to
a zero.
RAMA
IA
I','J
Ii
!I
To enable the transmitter parallel mode, TPDM must be set to
a 1. The modem automatically defaults to the serial mode
(TPDM =0) at power-on. In either transmitter serial or parallel
mode, the R24MFX is configured by the host processor via the
microprocessor bus.
Register
Ij
I',
R24MFX Host Processor Interface
I~
'I
Ii
INTERFACE MEMORY
R24MFX Interface Memory Map
iJ
R24MFX
2400 bps MONOFAX Modem
R24MFX Interface Memory Definitions
Mnemonic
Name
Memory
Location
Description
CDET
Carrier Detector
8:5
The one state of CDET indicates passband energy is being detected, and a training sequence is
not present. CDET goes to one at the start of the data state, and returns to zero at the end of the
received signal. CDET activates one baud time before RlSD and deactivates one baud time after
RlSD.
CDIE
Channel Data
Interrupt Enable
E:S
When set to a one, CDIE enables an IRO interrupt to be generated when the channel data
request bit (CDREO) is a one.
CDREO
Channel Data
Request
E:5
Parallel data mode handshaking bit. Set to a one when the modem receiver writes data to RXCD,
or the modem transmitter reads data from TXCD. CDREO must be reset to zero by the host
processor when data service IS complete.
CONF
Configuration
D:0-7
The 8-bit field CONF controls the configuration of the modem according to the following table:
Hex Code
Configuration
\1.21
\1.27
Tone
Invalid
0
4
8
All else
Configuration Definitions
1I.21-The modem operates as a CCITT T.30 compatible 300 bps FSK modem having
characteristics of the CCITT V.21 Channel 2 modulation system.
Tone-The modem sends single or dual frequency tones in response to the RTS or RTSP signals.
Tone frequencies and amplitudes are controlled by RAM locations written by the host. When not
transmitting tones the Tone configuration allows detection of single frequency tones by the TDET
bit. The tone detector frequency can be changed by the host by altering the contents of several
RAM locations.
1I.27-The modem operates as specified in CCIIT Recommendation V.27 for a 2400 bps data rate.
DDIE
Diagnostic Data
Interrupt Enable
E:2
When set to a one, DDIE enables an IRO interrupt to be generated when the diagnostic data
request bit (DDREO) is a one.
DDREO
Diagnostic Data
Request
E:O
DDREO goes to a one when the modem reads from or writes to DDYL. DDREO goes to a zero
when the host processor reads from or writes to DDYL. Used for diagnostic data handshaking bit.
DDXl
Diagnostic Data
X least
2:0-7
least significant byte of IS-bit word used in reading XRAM locallons.
DDXM
Diagnostic Data
X Most
3:0-7
least significant byte of IS-bit word used in reading XRAM locations.
DDYl
Diagnostic Data
Y least
0:0-7
least significant byte of IS-bit word used
locations.
DDYM
Diagnostic Data
Y Most
1:0-7
Most significant byte of IS-bit word used in reading YRAM locallons or writing XRAM and YRAM
locations.
EPT
Echo Protector
Tone
C:S
When EPT is a one, an unmodulated carrier is transmitted for 185 ms followed by 20 ms of no
transmitted energy at the beginning of the training sequence.
EOFZ
Equalizer Freeze
C:2
When EOFZ
EOSV
Equalizer Save
C:3
When EOSV IS a one, the adaptive equalizer taps are not zeroed when reconfiguring the modem
or when entering the training state.
FED
Fast Energy
Detector
8:5,S
FED consists of a 2-bit field that indicates the level of received signal according to the following
code.
Energy Level
Code
IS
In
reading YRAM locations or writing XRAM and YRAM
a one, the adaptive equalizer taps stop updating and remain frozen.
0
I
2
3
None
Invalid
Above Turn-off Threshold
Above Turn-on Threshold
While receiving a signal, FED normally alternates between Codes 2 and 3.
3-10
2400 bps MONOFAX Modem
R24MFX
R24MFX Interace Memory Definitions (continued)
Mnemonic
Name
Memory
Location
Description
GHIT
Gain Hit
B:4
The gain hit bit goes to one when the receiver detects a sudden Increase in passband energy
faster than the AGC circuit can correct. GHIT returns to zero when the AGC output returns to
normal.
IA
Interrupt Active
E:7
IA is a one when the modem
PN
Period N
8:3
PN sets to a one at the start of the received PN sequence PN resets to zero at the start of the
receiver data state. PN does not operate when EQFZ (C:2), EOSV (C:3) or TDIS (C:4) IS set to one
RAMA
RAM Access
F:0-7
The RAMA register is written by the host when reading or writing diagnostic data. The RAMA
code determines the RAM location with which the diagnostic read or wnte IS performed.
RAMW
RAM Write
C:O
RAMW is set to a one by the host processor when performing diagnostic wntes to the modem
RAM. RAMW is set to a zero by the host when reading RAM diagnostic data.
RTSP
Request to Send
Parallel
C:7
The one state of RTSP begins a transmit sequence. The modem continues to transmit until RTSP
IS turned off and the turn-off sequence has been completed. RTSP parallels the operallon of the
hardware RTS control input. These inputs are ORed by the modem.
RXCD
Receiver
Channel Data
5:0-7
RXCD is written to by the modem every eight bit times. This byte of channel data can be read by
the host when the receiver sets the channel data request bit (CDREO).
IS
driVing the Interrupt request hne (IRO) to a low TTL level.
RX
Receive State
B:7
RX
SETUP
Setup
E:3
The host processor must set the SETUP bit to a one when reconflguring the modem, Le., when
changing CONF (D:O-7).
TDET
Tone Detected
A:7
The one state of TDET Indicates reception of a tone. The filter can be retuned by means 01 the
diagnostic write routine.
TDIS
Trai mng Disable
C:4
If TDIS is a one in the receive state, the modem is prevented from entering the training phase. If
TDIS is a one when RTS or RTSP go active, the generation of a training sequence is prevented at
the start of transmission.
TPDM
Transmitter
Parallel Data
Mode
C:5
When control bit TPDM is a one, the transmitter accepts data for transmission from the TXCD
register rather than the serial hardware data input.
TXCD
Transmitter
Channel Data
4:0-7
The host processor conveys output data to the transmitter in parallel data mode by writing a data
byte to the TXCD register when the channel data request bit (CDREQ) goes to a one Data is
transmitted as single bits In V.21 or as dibits In V.27 starting with bit 0 or dibit 0,1.
IS
a one when the modem is in the receive state (Le., not transmitting)
Diagnostic Data Transfer
These bits are written into interface memory registers 3, 2, 1
and 0 in that order. Registers 3 and 2 contain the most and least
significant bytes of XRAM data, respectively, while registers 1
and 0 contain the most and least significant bytes of YRAM data
respectively.
The modem contains 128 words of random access memory
(RAM). Each word is 32-bits wide. Because the modem is
optimized for performing complex arithmetic, the RAM words
are frequently used for storing complex numbers. Therefore,
each word is organized into a real part (16 bits) and an imaginary
part (16-bits) that can be accessed independently. The portion
of the word that normally holds the real value is referred to as
XRAM. The portion that normally holds the imaginary value is
referred to as YRAM. The entire contents of XRAM and YRAM
may be read by the host processor via the microprocessor
interface.
When set to a one, bit C:O (RAMW) causes the modem to
suspend transfer of RAM data to the interface memory, and
instead, to transfer data from interface memory to RAM. When
writing into the RAM, only 16 bits are transferred, not 32 bits
as for a read operation. The 16 bits written in XRAM or YRAM
come from registers 1 and 0, with register 1 being the more
significant byte. Selection of XRAM or YRAM for the destination
is by means of the code stored in the RAMA bits of register F.
When bit F:7 is set to one, the XRAM is selected. When F:7
equals zero, YRAM is selected.
The interface memory acts as an intermediary during these host
to signal processor RAM data exchanges. The RAM address
to be read from or written to is determined by the contents of
register F (RAMA). The R24MFX RAM Access Codes table lists
27 access codes for storage in register F and the corresponding
diagnostic functions. The R24MFX Diagnostic Data Scaling table
provides scaling information for these diagnostic functions. Each
RAM word transferred to the interface memory is 32 bits long.
When the host processor reads or writes register 0, the
diagnostic data request bit E:O (DDREQ) is reset to zero. When
the modem reads or writes register 0, DDREQ is set to a one.
When set to a one by the host, bit E:2 (ODIE) enables the DDREQ
bit to cause an IRQ interrupt when set. While the IRQ line is
driven to a TIL low level by the modem, bit E:7 (IA) goes to a one.
3-11
i
~
III,
I
I'
•
R24MFX
2400 bps MONOFAX Modem
l-TPDM
N
l-RTSP
OR
O-RTS
y
N
O-CDREQ
N
DATA -
TXCO
O-COREQ
READ RXCD
N
N
N
0 - RTSP
AND
1 - RTS
Channel Data Parallel Mode Control
3-12
R24MFX
2400 bps MONOFAX Modem
R24MFX RAM Access Codes
Node
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
R24MFX Diagnostic Data Scaling
Function
RAMA
Reg. No.
Node
AGC Gain Word
Average Power
Receiver Sensitivity
Receiver Hysteresis
Equalizer Input
Equalizer Tap Coefficients
Unrotated Equalizer Output
Rotated Equalizer Output
Decision Points
Error Vector
Rotation Angle
Frequency Correction
EQM
Alpha (a)
Beta One (13,)
Beta Two (/32)
Alpha Prime (a')
Beta One Prime (130
Beta Two Prime (I>;)
Alpha Double Prime (a")
Beta Double Prime (13")
Output Level
Tone 1 Frequency
Tone 1 Level
Tone 2 Frequency
Tone 2 Level
Checksum
B1
F2
F1
84
5B
1B·2A
6B
OA
6C
6D
87
8B
BO
36
37
38
39
3A
3B
B6
B7
43
8E
44
8F
45
02
2,3
2,3
2,3
2,3
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
2,3
2,3
2,3
0,1
0,1
0,1
0,1
0,1
0,1
2,3
2,3
0,1
2,3
0,1
2,3
0,1
0,1
5,7-9
6
ParameterlScaling
All base-band signal pOint nodes (i.e., Equalizer Input,
Unrotated Equalizer Output, Rotated Equalizer Output,
and Decision POints) are 32·bit, complex, twos
y
complement numbers.
Point
X
Y
1
2
1600
EAOO
1600
1600
3
EAOO
4
1600
EAOO
EAOO
e2
e1
X
e3
e4
Equalizer Tap Coefficients (32-bit, complex, twos
complement)
Complex numbers with X =real part, Y = Imaginary part
X and Y range: 0000 to (FFFF)'6 representing ± full scale
in hexadecimal twos complement.
10
Error Vector (32-bit, complex, twos complement)
Complex number with X = real part,
Y = imaginary part.
X and Y range: (8000)'6 to (7FFF)'6
11
Rotation Angle (16-bit, signed, twos complement)
12
Frequency Correction (16-bit signed twos complement)
Rotation Angle in deg.
= (Rot.
Angle Word/65,536) x 360
Frequency correction in Hz
= (Freq. Correction Word/65,536) x Baud Rate
Range: (FCOO)'6 to (400),6 representing ± 18.75 Hz
13
EQM (16-bit, unsigned)
Filtered squared magnitude of error vector.
Proportionality to BER determined by particular application
14-21
Filter Tuning Parameters (16-bit unsigned) Alpha, Beta One,
Beta Two, Alpha Prime, Beta One Prime, Beta Two Prime,
Alpha Double Prime, and Beta Double Prime are set according
to instructions in application note 668. Use a sample rate of
7200 samples per second for all calculations.
22
Output Level (16-bit unsigned)
Output Number = 27573.6 [1O(PoI20)]
R24MFX Diagnostic Data Scaling
ParameterlScaling
Node
1
AGC Gain Word (16-bit unsigned).
AGC Gain in dB
= 50
- [(AGC Gain Word/64) x 0.098]
Range: (16CO)'6 to (7FFF)'6' For - 43 dBm Threshold
2.
Average Power (16-bit unsigned)
Post·AGC Average Power in dBm
= 10 Log (Average Power Word/2185)
Po
Typical Value = (0889),6, corresponding to 0 dBm
Pre-AGC Power in dBm
= (Post-AGC Average Power-AGC Gain)
3
Into 600 ohm load.
Convert Output Number to hexadecimal and store at
access code 43
Receiver Sensitivity (16-bit twos complement)
On·Number
where: PON
=655.36 (52.38 + PON)
=Turn-on threshold in dB
24
and
26
Tone 1 and Tone 2 Levels
Calculate the power of each tone independently by uSing
the equation for Output Number given at node 22.
Convert these numbers to hexadecimal then store at
access codes 44 and 45. Total power transmitted in tone
mode IS the result of both tone 1 power and tone 2
power.
23
and
25
Tone 1 and 2 Frequency (16-bit unsigned)
N = 9.1022 (Frequency in Hz)
Convert N to hexadecimal then store at access code 8E
or 8F.
27
Checksum (16-bit unsigned)
ROM checksum number determined by revision level.
Convert On-Number to hexadecimal and store at access
code F1
4
Receiver Hysteresis (16-bit twos complement)
Off·Number
= output power in dBm with series 600 ohm resistor
= [65.4 (10 A )]'/2
A = (POFF - PON - 0.5)/20
PON = Turn-on threshold In dB
POFF = Turn-off threshold In dB
Convert Off-Number to hexadecimal and store at access
code 84.
where:
3-13
2400 bps MONOFAX Modem
R24MFX
POWER·ON INITIALIZATION
PERFORMANCE
When power is applied to the R24MFX, a period of 50 to 350 ms
is required for power supply settling. The power-an-reset signal
(POR) remains low during this period. Approximately 10 ms after
the low to high transition of POR, the modem is ready to be
configured, and RTS may be activated. If the 5 Vdc power supply
drops below approximately 3 Vdc for more than 30 msec, the
POR cycle is repeated.
Whether functioning as a V.27 ter or V.21 type modem, the
R24MFX provides the user with unexcelled high performance.
TYPICAL BIT ERROR RATES
The Bit Error Rate (BER) performance of the modem is specified
for a test configuration conforming to that illustrated in CCITT
Recommendation V.56. Bit error rates are measured at a
received line signal level of -20 dBm.
At POR time the modem defaults to the following configuration:
RECEIVED SIGNAL FREQUENCY TOLERANCE
V.27/2400 bps, serial mode, training enabled, echo protector
The receiver circuit of the R24MFX can adapt to received
frequency error of ± 10Hz with less than 0.2 dB degradation
in BER performance.
tone enabled, interrupts disabled, RAM access code OA,
transmitter output level set for + 5 dBm at TXA, receiver turnon threshold set for -43.5 dBm, receiver turn-off threshold set
for -47.0 dBm, tone 1 and tone 2 set for 0 Hz and 0 volts output,
and tone detector parameters zeroed.
TYPICAL PHASE JITTER
At 2400 bps, the modem exhibits a BER of 10-6 or less with a
signal-to-noise ratio of 12.5 dB in the presence of 15° peak-topeak phase jitter at 150 Hz or with a signal-to-noise ratio of 15
dB in the presence of 30° peak-to-peak phase jitter at 120 Hz
(scrambler inserted).
POR can be connected to a user supplied power-an-reset signal
in a wire-or configuration. A low active pulse of 3 !,sec or longer
applied to the POR pin causes the modem to reset. The modem
is ready to be configured 10 msec after the low active pulse is
'removed from POR.
An example of the BER performance capabilities is given in the
following diagrams:
/V27,2400
/SK
10- 3
10- 3
10-'
w
10-'
w
l-
I
FSK
/V27,2400
\
l-
e(
e(
II:
II:
II:
II:
II:
II:
II:
0
0
a:
w
W
I-
I-
10- 5
10- 5
iii
iii
\
10- 6
0
\
5
10
15
20
SIGNAL TO NOISE RATIO IN DB
\
10- 6
0
25
Typical Bit Error Rate
(Back-to-Back, Level -20 dBm)
\
10
15
20
5
SIGNAL TO NOISE RATIO IN DB
Typical Bit Error Rate
(Unconditioned 3002 Line, Level - 20 dBm)
3-14
25
R24MFX
2400 bps MONOFAX Modem
The BER performance test set-up is show in the following
diagram:
r--
MODEM
TRANSMITTER
r---
3002
LINE
SIMULATOR
SEG FA-1445
r---
IMPAIRMENT
SOURCE
BRADLEY 2A
AND 2B
r---
ATTENUATOR
HP 3500
I
I
MODEM
TEST SET
PHOENIX
5000
LEVEL
METER
HP 3552A
MODEM
RECEIVER
I
NOTE
SIGNAL AND NOISE ARE MEASURED WITH 3 KHZ FLAT WEIGHTING.
BER Performance Test Set-up
3-15
2400 bps MONOFAX Modem
R24MFX
5. Pin 22 should be tied directly to pin 24 at the R24MFX
package. Pin 24 should tie directly, by a unique path, to the
common ground point for analog and digital ground.
APPLICATION
Recommended Modem Interface Circuit
6. An analog ground plane should be supplied beneath all
analog components. The analog ground plane should
connect to pin 24 and all analog ground points shown in the
recommended circuit diagram.
The R24MFX is supplied as a 64-pin QUIP device to be designed
into original equipment manufacturer (OEM) circuit boards. The
recommended modem interface circuit and parts list illustrate
the connections and components required to connect the modem
to the OEM electronics.
7. Pins 4, 8, 29, and 48 should tie together at the R24MFX
package. Pin 48 should tie directly, by a unique path, to the
common ground point for analog and digital ground.
If the auxiliary analog input (pin 26) is not used, resistors R2
and R3 can be eliminated and pin 26 must be connected to
analog ground (pin 24). When the cable equalizer controls
CABLEl and CABLE2 are connected to long leads that are
subject to picking up noise spikes, a 3k 0 series reSistor should
be used on each input (Pins 32 and 33) for isolation.
8. A digital ground plane should be supplied to cover the
remaining allocated area. The digital ground plane should
connect to pin 48 and all digital ground points shown in the
recommended circuit diagram plus the crystal-can ground.
9. The R24MFX package should be oriented relative to the two
ground planes so that the end containing pin 1 is toward the
digital ground plane and the end containing pin 32 is toward
the analog ground plane.
Resistors R4 and R9 can be used to trim the transmit level and
receive threshold to the accuracy required by the OEM
equipment. For a tolerance of ± 1 dB the 1% resistor values
shown are correct for more than 99.8% of the units.
10. As a general rule, digital signals should be routed on the
component side of the PCB while analog signals are routed
on the solder side. The sides may be reversed to match a
particular OEM requirement.
Typical Modem Interface Parts List
Component
Manufacturer's
Part Number
C3,C5,C7,C9
C2
592CX7R104M050B
N511BY10OJW
C1
C11
Y1
Z1
R5,R6
C114C330J2G5CA
SA405C274MAA
333R14-002
LM1458N
CML 1/10
T86.6K ohm ± 10f0
5MA434.0K ± 1%
5043CX3ROOOJ
5043CX2M700J
5043CX47KOOJ
5043CX3KOOJ
5043CX1 KOOJ
ECEBEF100
SMC50Tl ROM5X12
C124C102J5G5CA
IN751D
CRB '/4XF47K5
ER025QKF2370
Determined by IRQ
characteristics
R4
R11
RIO
R1
R7
R2,R3
C10
C8
C4,C6
CR1
R9
R8
R14
Manufacturer
11. Routing of R24MFX signals should provide maximum
isolation between noise sources and sensitive inputs. When
layout requirements necessitate routing these signals
together, they should be separated by neutral signals. Refer
to the table of noise characteristics for a list of pins in each
category.
Sprague
San Fernandol
Wescap
Kemet
AVX
Uniden
National
Pin Noise Characteristics
Dale Electronics
Corning Electronics
Mepco Electra
Mepco Electra
Mepco Electra
Mepco Electra
Mepco Electra
Panasonic
United Chern-Con
Kemet
I.T.T.
R-Ohm
Matsushita ElectriC
Noise Source
PC Board Layout Considerations
1. The R24MFX and all supporting analog circuitry, including
the data access arrangement if required, should be located
on the same area of printed circuit board (PCB).
2. All power traces should be at least 0.1 inch width.
3. If power source is located more than approximately 5 inches
from the R24MFX, a decoupling capacitor of 10 microfarad
or greater should be placed in parallel with Cll near pins 11
and 48.
4. All circuitry connected to pins 9 and 10 should be kept short
to prevent stray capacitance from affecting the oscillator.
3-16
Noise Sensitive
High
Low
Neutral
Low
High
1
2
5
14
15
20
21
30
38
39
40
41
44
6
7
9
10
12
13
17
18
19
45
3
4
8
11
16
22
24
25
29
31
34
42
43
47
48
26
28
32
33
23
27
35
36
37
46
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
::D
N
.j::Io
:s:
."
><
g"
C1
3
PORI
PORO 32
CABLE1
5%,50V
C2
CABLE2
CABLE1
33
10 PF
"='
POR
•
CABlE2
C3
5%, SOY
AOUT
""""A'D'Xi'N
R1
c.
AGCIN
:tJ
AUXI
...0CD
3
3
CD
"
.2'
SERIAL
INTERFACE
"
0
OAIN
n
~
FOUT
FIN
R6
-5.
866K 1%
R9
SYNCINl
SYNCIN2
SYNCIN3
~
9-
1000 PF
5%, SOV
SYNCOUT
;;
CD
RXIN
+5 VOLTS
:;
n
C6
AOIN
47 neva
34 RCVI,
16 RCVI2
3
.
TXA
ADOUT
;s:
Co
CD
+12VOLTS
DAOUT
Co
CD
Co
~
•
TXOUT
1458
Z1
v
+5VO 31
P.t
MICROPROCESSOR
,
+~Vc': 42
PARALLEL
INTERFACE
l
-
RXA
47-SK 1%
~
II' -12VOLTS
C'
1.0,F
N
.;.
4 ......
5=~:D
60 WRITE
R24MFX
""
~--------~--~---!~~~--+-----3 O~M
ell
•
+5 VOLTS
ClO
+ 10 /IF
NOTES UNLESS OTHERWISE SPECIFIED
1 RESISTOR VALUES ARE IN OHMS ±5% 114W
2 CAPACITOR VALUES ARE IN MICROFARADS ±20% SOV
10%
25.
I
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<:)
tT
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en
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oz
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R24MFX
2400 bps MONOFAX Modem
PACKAGE DIMENSIONS
I
1:
.020 TYP.
"r'- m
I
I
-,rr-
1.628
(41.35 MM)
:&
::>
(5.0!;~M)
'"
" w
ozz "..c
I
g ~
~~ r
I
680
_____ (17."27 MM)
33
~
-£
-£-OSOREF
(1.27 MM)
TYP
J
I!I I I1~.020REF
~t
_I
1 _ 1.50
(3.81 MM)
64-Pin QUIP
3-18
I
£ £
I
:l
.. a
o-J
'----==3_2_ . . . . J
"
I I-(19.05MM)~1
TYP
.925
(23.495 MM)
..
.750
----,
1··1
-11
I
I
£ £
I"
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R24BKJ
'1'
Rockwell
R24BKJ
2400 bps V.26 bis, Bell 201B/C Modem
INTRODUCTION
FEATURES
The R24BKJ is a synchronous, serial/parallel, 2400 bps modem
in a single 64-pin quad in-line package (QUIP). The modem is
designed for operation over the public switched telephone network with appropriate line terminations, such as a data access
arrangement, provided externally.
• Single 64-Pin QUIP
• CCITT V.26 bis Alternate A or B
The R24BKJ satisfies the telecommunications requirements
specified in CCITT Recommendation V.26 bis Alternate A or B
and Bell 201B/C.
•
•
•
•
Bell 201B/C
Half-Duplex (2-Wire)
Programmable RTS/CTS Delay
Programmable Dual Tone Generation
•
•
Programmable Tone Detection
Dynamic Range: - 43 dBm to 0 dBm
• Diagnostic Capability
- Provides Telephone Line Quality Monitoring Statistics
The R24BKJ is optimized for use in compact original equipment
manufacturer (OEM) systems. Its small size and low power consumption offer the user flexibility in creating a 2400 bps modem
customized for specific packaging and functional requirements.
•
Equalization
- Automatic Adaptive
- Compromise Cable (Selectable)
•
DTE Interface: Two Alternate Ports
- Microprocessor Bus
- CCITT V.24 (RS-232-C Compatible)
•
•
Low Power Consumption: 1W (Typical)
Programmable Transmit Output Level
• TTL and CMOS Compatible
SYNCIN3
RSO
RS1
RS2
RS3
NC
PORI
DGNOS
SVNCIN2
NC
NC
DGN03
WRITE
cs
READ
IRQ
DO
01
02
03
D.
05
06
XTU
XTLO
+SVD
RXD
TXO
OAOUT
AOIN
D7
RCYI2
CTS
DGND2
RLSO
DCLK
SVNCOUT
RCVO
RTS
NC
selKO
PORO
RCI
NC
DGNOl
AGCIN
AGND
-5VA
SVNCIN1
AUXI
FOUl
TXOUl
ADOUT
SCLKIN2
RXIN
AQUT
OAIN
OGND4
SCLKIN1
FIN
+SVA
CABlEl
RCYll
CABlE2
Ne = NO CONNECTION
R24BKJ 2400 bps V.26 bis/Bell 201B/C Modem
R24BKJ Pin ASSignments
Document No_ 29200N20
Data Sheet
3-19
Order No_ MD20
Rev _ 1, February 1987
R24BKJ
2400 bps V.26 bis, Bell 201B/C Modem
TECHNICAL CHARACTERISTICS
RECEIVE LEVEL
The receiver circuit of the R24BKJ satisfies all specified performance requirements for received line signal levels from 0 dBm
to -43 dBm. An external input buffer and filter must be supplied between the receiver analog input (RXA) and the R24BKJ
RXIN pin. The received line signal level is measured at RXA.
TONE GENERATION
Under control of the host processor, the R24BKJ can generate single or dual frequency voice band tones up to 3600 Hz
with a resolution of 0.11 Hz and an accuracy of 0.01 %. The
transmit level and frequency of each tone is independently
programmable.
RECEIVE TIMING
In the receive state, the R24BKJ provides a Data Clock (DClK)
output in the form of a square wave. The low to high transitions
of this output coincide with the centers of received data bits.
The timing recovery circuit is capable of tracking a ± 0.01 % frequency error in the associated transmit timing source. DClK
duty cycle is 50% ± 1%.
TONE DETECTION
Single frequency tones are detected by a programmable filter.
The presence of energy at the selected frequency is indicated
by a bit in the interface memory.
SIGNALING AND DATA RATES
TRANSMIT LEVEL
Signaling/Data Rates
Parameter
Specification
(±0.01%)
Signaling Rate
Data Rate
1200 Baud
2400 bps
The transmitter output level is programmable. An external output buffer and filter must be supplied between the R24BKJ
TXOUT pin and the transmitter analog output (TXA). The default
level at TXA, when sending pseudorandom data, is + 5 dBm
± 1 dB. When driving a 600 ohm load the TXA output requires
a 600 ohm series resistor to provide -1 dBm ± 1 dB to the load.
DATA ENCODING
TRANSMIT TIMING
The 2400 bps data stream is encoded into dibits per CCITT V.26
bis Alternate A or B and Bell 201 B/C.
In the transmit state, the R24BKJ provides a Data Clock (DCll<)
output with the following characteristics:
1. Frequency: Data rate of 2400 Hz (± 0.01 %).
COMPROMISE CABLE EQUALIZERS
2. Duty Cycle: 50% ± 1%.
In addition to the adaptive equalizer, the R24BKJ provides
selectable compromise cable equalizers to optimize performance
over three different lengths of non-loaded cable of 0.4 mm
diameter (1.8 km, 3.6 km, and 7.2 km).
Transmit Data (TXD) must be stable during the 1 microsecond
periods immediately preceding and following the rising edge of
DClK.
Cable Equalizer Nominal Gain
Frequency
(Hz)
700
1500
2000
3000
SYNCHRONIZING SEQUENCE
Gain (dB) Relative to 1700 Hz
7.2 km
1.8 km
3.6 km
-0.99
-0.20
+0.15·
+ 1.43
-2.39
-0.65
+0.87
+3.06
The synchronizing sequence of the R24BKJ consists of two
segments: a fixed segment of unscrambled ones, and an open
segment which may be either unscrambled or scrambled ones,
depending on the configuration selected. Both segments are programmable by allowing the synchronizing sequence to be varied
for specific applications.
-3.93
-1.22
+1.90
+4.58
TRANSMITTED DATA SPECTRUM
TURN-OFF SEQUENCE
The transmitter spectrum is shaped by a square root of 90%
raised cosine filter.
The turn-off sequence consists of approximately 10 ms of
remaining data and scrambled or unscrambled ones at
1200 baud.
The out-of-band transmitter power limitations meet those specified by Part 68 of the FCC's Rules, and typically meet the
requirements of foreign telephone regulatory agencies.
CLAMPING
The following clamps are provided with the R24BKJ:
SCRAMBLER/DESCRAMBLER
1. Received Data (RXD). RXD is clamped to a constant mark
(1) whenever RlSD is off.
The R24BKJ incorporates a self-synchronizing scrambler/
descrambler. This facility is in accordance with CCITT V.27 ter.
The scrambler can be disabled by setting a bit in interface
memory.
2. Received Line Signal Detector (RLSD). RlSD is clamped off
(squelched) whenever RTS is on.
3-20
2400 bps V.26 bis, Bell 201B/C Modem
R24BKJ
RESPONSE TIMES OF CLEAR-TO-SEND (CTS)
A minimum hysteresis action of 2 dB exists between the actual
off-to-on and on-to-off transition levels. The threshold levels and
hysteresis action are measured with an unmodulated 2100 Hz
tone applied to RXA.
The time between the off-to-on transition of RTS and the off-toon transition of CTS is dictated by the length of the synchronizing
signal. The response time is programmable. The choice of
response times depends upon the system application: a) limited
protection against line echoes; b) protection given against line
echoes.
i
I'
POWER
Current
(Max) @ 25°C
Voltage Tolerance
The time between the on-to-off transition of RTS and the on-tooff transition of CTS in the data state is a maximum of 2 baud
times for all configurations.
+S Vdc
-S Vdc
RLSD turns on whenever energy is detected on the line. The
RLSD off-to-on response time is 10 ±5 ms.
The RLSD on-to-off response time ensures that all valid data
bits have appeared on RXD. The on-to-off response time is
10 ± 5 ms. Response times are measured with a signal at least
3 dB above the actual RLSD on threshold or at least 5 dB below
the actual RLSD off threshold.
ENVIRONMENTAL
Parameter
Temperature
Operating
Storage
Receiver threshold is programmable over the range 0 dBm to
-50 dBm, however, performance may be at a reduced level
when the received signal is less than - 43 dBm.
---
CABLE1
AUXI
USRT
(OPTIONAL)
--0
DCLK
h
RLSD
I""
I
RXD
XTLO
,.
XTLI
CLOCK
- . - CRYSTAL
TXOUT
R24BKJ
MODEM
RXIN
WRITE
DATA BUS (8)
ADDRESS BUS (4)
.h
DECODER 1
~P
o
J
READ
HOST
PROCESSOR
(DTE)
Up to 90% noncondensing, or a wet bulb
temperature up to 35°C, whichever is less.
TXD
I
I
,..,
~
I'-'
I
O°C to + 60°C (32°F to 140°F)
-40°C to +80°C (-40°F to 176°F) (Stored
In suitable antistatic container).
CABLE2
~
CTS
h
I
L
Relative Humidity
Specification
RTS
I
I
I
250 mA@ S.O Vdc 225 mA @ S.O Vdc
25 mA @ -S.O Vdc 25 mA @ -5.0 Vdc
Note: All voltages must have ripple ,;0.1 volts peak-to-peak. If
a switching supply is chosen, user may select any frequency
between 20 kHz and 150 kHz so long as no component of the
sWitching frequency IS present outside of the power supply with
an amplitude greater than SOO microvolts peak.
RECEIVED LINE SIGNAL DETECTOR (RLSD)
r-
±5%
±S%
Current
(Max) @ 60°C
CS
_
+5V
POR
-5V
IRQ
+5~
5
GND
R24BKJ Functional Interconnect Diagram
3-21
-
- } TELEPHONE
LINE
LINE
INTERFACE
if
I'
I
~
i
I
R24BKJ
2400 bps V.26 bis, Bell 201B/C Modem
INTERFACE CHARACTERISTICS
gates, the interface can be made compatible with a wide variety
of microprocessors such as 6500, 6800, or 68000.
The modem interface comprises both hardware and software
circuits. Hardware circuits are assigned to specific pins on the
64-pin QUIP. Software circuits are assigned to specific bits in
a 16-byte interface memory.
The microprocessor interface allows a host microprocessor to
change modem configuration, read or write channel data as well
as diagnostic data, and supervise modem operation by means
of software strappable control bits and modem status bits. The
significance of the control and status bits and methods of data
interchange are discussed in the Software Circuits section.
HARDWARE CIRCUITS
Signal names and descriptions of the hardware circuits, including
the microprocessor interface, are listed in the R24BKJ Hardware
Circuits table; the table column titled 'Type' refers to designations found in the Digital and Analog Interface Characteristics
tables.
V.24 Interface
Seven hardware circuits provide timing, data and control signals
for implementing a serial interface compatible with CCITT
Recommendation V.24. These signals interface directly with circuits using TTL logic levels (0, + 5 vOlt). These TTL levels are
suitable for driving the short wire lengths or printed circuitry
normally found within stand-alone modem enclosures or equipment cabinets.
Microprocessor Interface
Sixteen hardware circuits provide address (RSO-RS3), data
(00-07), control (CS, READ and WRITE) and interrupt (IRQ)
signals for implementing a parallel interface compatible with an
8080 microprocessor. (Refer to the Microprocessor Interface
Timing Waveforms figure and Microprocessor Interface Timing
Requirements table.) With the addition of a few external logic
In applications where the modem is operated in parallel data
mode only (i.e., where the V.24 signals are unused), all V.24
pins may remain unterminated.
R24BKJ Hardware Circuits
Name
Type
Pin No.
Description
Name
A. POWER:
AGND
DGNDI
DGND2
DGND3
DGND4
DGND5
+5 VA
+5 VD
-5 VA
GND
GND
GND
GND
GND
GND
PWR
PWR
PWR
24
22
48
8
29
4
31
11
25
Connect
Connect
Connect
Connect
Connect
Connect
Connect
Connect
Connect
to
to
to
to
to
to
to
to
to
Analog Ground
AGND Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Analog + 5V Power
Digital + 5V Power
Analog - 5V Power
TXOUT
RXIN
AUXI
1I0A
1I0A
1I0A
1I0A
1I0A
1I0A
1I0A
1I0A
"}
50
51
52
53
54
55
56
Data Bus (8 Bits)
RS3
RS2
RSI
RSO
IA
IA
IA
IA
61 }
62
63
64
Register Select (4 Bits)
Select Reg. 0 - F
CS
READ
WRITE
IRQ
IA
IA
IA
OB
59
58
60
57
Chip Select
Read Strobe
Write Strobe
Interrupt Request
19
46
17
13
12
18
Data Clock
Request-to-Send
Clear-to-Send
Transmitter Data Signal
Receiver Data Signal
Received Line Signal Detector
32
33
Cable Select 1
Cable Select 2
C. V.24 INTERFACE:
DClK
RTS
CTS
TXD
RXD
RLSD
OC
IB
OC
IB
OC
OC
Description
IC
IC
--
AB
AC
28
37
26
Connect to Output Op Amp
Connect to Input Op Amp
Auxiliary Analog Input
1I0B
1I0B
R'
R'
R"
R'
R"
R'
R"
R"
R'
R"
R"
R'
R"
R'
R'
R'
R'
R"
R"
R'
R'
43
3
10
9
47
34
16
44
30
38
36
23
14
40
39
15
27
35
20
41
5
1
42
Power-On-Reset Output
Power·On-Reset Input
Connect to Crystal Circuit
Connect to Crystal Circuit
Receive Mode Output
Connect to RCVO
Connect to RCVO
Switched Capacitor Clock Output
Connect to SClKO
Connect to SClKO
Smoothing Filter Output
AGC Input
DAC/AGC Data Out
Connect to DAOUT
ADC Output
Connect to ADOUT
Smoothing Filter Output
Connect to FOUT
Sample Clock Output
Connect to SYNCOUT
Connect to SYNCOUT
Connect to SYNCOUT
RC Junction for POR Time
Constant
2
6
7
21
45
Do
Do
Do
Do
Do
AA
G. RESERVED
R'
R'
R'
R"
R"
D. CABLE EQUALIZER:
CABLE 1
CABLE2
Pin No.
F.OVERHEAD
PORO
PORI
XTlO
XTLI
RCVO
RCVll
RCVI2
SClKO
SClKINl
SClKIN2
AOUT
AGCIN
DAOUT
DAIN
ADOUT
ADIN
FOUT
FIN
SYNCOUT
SYNCINI
SYNCIN2
SYNCIN3
RCI
B. MICROPROCESSOR INTERFACE:
D7
D6
D5
D4
D3
D2
Dl
DO
Type
E. ANALOG SIGNALS:
Not
Not
Not
Not
Not
Connect
Connect
Connect
Connect
Connect
• R = Required overhead connection; no connection to host equipment.
3-22
R24BKJ
2400 bps V.26 bis, Bell 201B/C Modem
Digital Interface Characteristics
Type
Input
Parameter
Symbol
Input/Output
Output
Units
IA
IB
IC
OA
OB
OC
1/0A
I/OB
5.25 max.
2.0 min.
0.8 max.
2.4 min.3
0.4 max. S
V,H
Input Voltage, High
V
2.0 min.
2.0 min.
2.0 min
2.0 min.
V,L
VOH
VOL
liN
IOH
IOL
IL
Ipu
Input Voltage, Low
Output Voltage, High
Output Voltage, Low
Input Current, Leakage
Output Current, High
Output Current, Low
Output Current, Leakage
Pull-up Current
(Short Circuit)
Capacitive Load
Capacitive Dnve
Circuit Type
V
V
V
0.8 max.
0.8 max
0.8 max.
~A
±2.5 max.
0.8 max.
2.4 min.
0.4 max. 2
± 12.5 max.
CL
Co
Notes
1. I load
2. I load
2.4 min.'
0.4 max. 2
mA
rnA
-0.1 max.
1.6 max.
~A
~A
pF
pF
5
-240 max.
-10 min.
5
-240 max.
-10 min.
20
TTL
wlPull-up
TTL
wlPull-up
TTL
3. I load = -40 ~
4. V,N = 0.4 to 2.4 Vdc, Vee
5. I load = 0.36 mA
= -100~
= 1.6 rnA
,
0.4 max. 2
0.4 max 2
1.6 max.
± 10 max.
1.6 max.
-240 max.
-10 min.
-260 max.
-100 min.
10
40
100
100
100
100
Drain
3
State
Open-Drain
Open
Open-Drain
wlPull-up Transceiver wlPull-up
100
TTL
= 5.25 Vdc
Analog Interface Characteristics
Analog Interface Characteristics
Name
Type
Characteristics
TXOUT
AA
The transmitter output can supply a
maximum of ± 3.03 volts into a load
resistance of 10k 0 minimum. In order to
match to 600 0, an external smoothing
filter with a transfer function of
15726.43/(S + 11542.44) and 604 0 series
resistor are required.
RXIN
AUXI
AB
AC
READ
The receiver input impedance is greater
than 1M O. An external anti aliasing filler
with a transfer fu nction of
19533.88/(S + 11542.44) is required.
(I
The auxiliary analog input allows access
to the transmitter for the purpose of
Interfacing with user provided equipment.
Because this is a sampled data input,
any signal above 3600 Hz will cause
aliasing errors. The input impedance is
1M 0, and the gain to transmitter output
(TXA) is + 5.6 dB ± 1 dB.
READ
Microprocessor Interface Timing Requirements
CS, RSI setup time prior
to READ or WRITE
Data Access time after READ
Data hold time after READ
CS, RSi hold time after
READ or WRITE
Write data setup time
Write data hold time
WRITE strobe pulse width
Symbol
Min
TCS
TDA
TDH
30
TCH
TWDS
TWDH
TWR
Di
Max
Units
-
10
140
50
ns
ns
ns
10
75
10
75
-
ns
ns
ns
ns
-
RSi
0-3)
WRITE
Note: Absolute maximum voltage ratings for analog inputs are:
(-5VA - 0.3) s V,N S (+5VA + 0.3)
Characteristic
WRITE
(I
= 0-7)
--~',
Microprocessor Interface Timing Waveforms
3-23
,
"
I
R24BKJ
2400 bps V.26 bis, Bell 201B/C Modem
Cable Equalizers
When information in these registers is being discussed, the format Z:O IS used. The register is specified by Z(O-F), and the bit
by 0(0-7, 0= LSB). A bit is considered to be "on" when set to
a one (1) and "off" when reset to a zero (0).
Modems may be connected by direct wiring, such as leased
telephone cable or through the public switched telephone network, by means of a data access arrangement. In either case,
the modem analog signal is carried by copper wire cabling for
at least some part of its route. The cable characteristics shape
the passband response so that the lower frequencies of the passband (300 Hz to 1700 Hz) are attenuated less than the higher
frequencies (1700 Hz to 3300 Hz). The longer the cable the more
pronounced the effect.
Status/Control Bits
The operation of the R24BKJ is affected by a number of software control inputs. These inputs are written into registers within
the interface memory via the host microprocessor bus. Modem
operation is monitored by various software flags that are read
from interface memory via the host microprocessor bus.
To minimize the impact of this undesired passband shaping, a
compromise equalizer with more attenuation at lower frequencies than at higher frequencies can be placed in senes with the
analog signal. The modem includes three such equalizers
designed to compensate for cable distortion.
All status and control bits are defined in the R24BKJ Interface
Memory Map table. Bits designated by , - ' are reserved for
modem use only and must not be changed by the host.
Cable Equalizer Selection
CABLE2
CABLEl
Length of O.4mm Diameter Cable
0
0
1
1
0
1
0
1
0.0
1.8 km
3.6 km
7.2 km
Anyone of the registers may be read or written on any host read
or write cycle, but all eight bits of that register are affected. In
order to read a single bit or a group of bits in a register, the host
processor must mask out unwanted data. When writing a single
bit or group of bits in a register the host processor must perform
a read-modify-write operation. That is, the entire register is read,
the necessary bits are set or reset in the accumulator of the host,
then the original unmodified bits and the modified bits are written
back into the register of the interface memory.
Analog Signals
Three analog signals provide the interface pOint for telephone
company audio circuits and host audio inputs. Signals TXOUT
and RXIN require buffering and filtering to be suitable for driving
and receiving the communication channel. Signal AUXI provides
access to the transmitter for summing host audio signals with
the modem analog output.
Configuration Control
Five configurations are available in the R24BKJ modem. The
configuration is selected by writing an 8-bit binary code into the
configuration field (CONF) of the interface memory. The configuration field consists of bits 7 through of register D. The
code for these bits is shown in the following table. All other codes
represent invalid states.
a
The filters required for anti-aliasing on the receiver input and
smoothing on the transmitter output have a single pole located
at 11,542 radians. Although this pole is located within the modem
passband, internal filters compensate for its presence and,
therefore, the pole location must not be changed. Some variation from recommended resistor and capacitor values is permitted as long as the pole is not moved, overall gain is preserved,
and the device is not required to drive a load of less than 10k fl.
Configuration CodeS
Notice that when reference is made to signals TXA, RXA, and
AUXIN, these signals are not electrically identical to TXOUT,
RXIN, and AUXI. The schematic of the recommended modem
interface circuit illustrates the differences.
Overhead
CONF
Code
Configuration
Scramblerl
Descrambler
04'
V.26B
disabled
44
V.26A
disabled
84
V.26B
enabled
C4
V 26A
enabled
DC
Tone
Not applicable
'Default value at POR With 220 ms synchronizing sequence
Except for the power-an-reset signal PORO, the overhead
signals are intended for internal use only. The various required
connections are illustrated in the recommended modem interface circuit schematic. No host connections should be made to
overhead signals other than PORO.
When the modem is initialized by power-an-reset, the configuration defaults to V.26B with scrambler disabled and 220 ms
synchronizing signal. When the host wants to change configuration, the new code is written to the configuration field and the
SETUP bit (E:3) is set to a one. Once the new configuration takes
effect, the SETUP bit is reset to zero by the modem.
SOFTWARE CIRCUITS
The R24BKJ contains 16 memory mapped registers to which an
external (host) microprocessor has access. The host may read
data out of or write data into these registers. Refer to the R24BKJ
Host Processor Interface figure.
The information in the interface memory is serviced by the
modem at 1200 times per second.
3-24
2400 bps V.26 bis, Bell 201B/C Modem
R24BKJ
READ
READ
WRITE
LOGIC
8
8
00-07
RSO-RS3 _4f-t_~
I---::---~~~~~
REGISTER
SELECT
LOGIC
INTERFACE MEMORY
R24BKJ Host Processor Interface
To enable the transmitter parallel mode, TPDM must be set to
a 1. The modem automatically defaults to the serial mode
(TPDM = 0) at power-on. In either transmitter serial or parallel
mode, the R24BKJ is configured by the host processor via the
microprocessor bus.
R24BKJ Interface Memory Map
~
7
6
5
4
3
2
1
0
ODIE
-
OOREO
EQFZ
-
RAMW
Register
F
E
COlE COREO
-
SETUP
0
eONF
c
RTSP
B
RX
A
TDET
9
8
7
6
-
-
TPDM
FED
-
-
eDET
-
1
-
GHIT
-
-
-
-
5
4
RxeD
3
DDXM
2
DDXL
1
DDYM
0
DDYL
~
Serial Mode-The serial mode uses a standard V.24 (RS-232-C)
hardware interface (optional USRT) to transfer channel data.
Transmitter data can be sent serially only when TPDM is set to
a zero.
RAMA
IA
-
-
-
Parallel Mode-Parallel data is transferred via two registers in
the interface memory. Register 5 (AXCD) is used for receiver
channel data, and Register 4 (TXCO) is used for transmitter channel data. Register 5 is continuously written every eight bit times
when in the receive state. Register 4 is used as the source of
channel transmitter data only when bit C:5 (TPDM) is set to a one
by the host. Otherwise the transmitter reads data from the V.24
interface. Both RTS and RTSP remain enabled, however, regardless of the state of TPDM.
-
-
TxeD
7
6
5
4
3
2
1
When performing parallel data transfer of channel data, the host
and modem can synchronize their operations by handshaking bits
in register E. Bit E:5 (CDREQ) is the channel data request bit.
This bit is set to a one by the modem when receiver data is
available in RXCD or when transmitter data is required in TXCD.
Once the host has finished reading RXCD or writing TXCD, the
host processor must reset CDREQ by writing a zero to that bit
location.
0
When set to a one by the host, Bit E:6 (CDIE) enables the CDREQ
bit to cause an IRQ interrupt when set. While the IRQ line is
driven to a TTL low level by the modem, bit E:7 (IA) is a one.
Channel Data Transfer
Data sent to or received from the data channel may be transferred
between the modem and host processor in either serial or parallel
form. The receiver operates in both serial and parallel mode
simultaneously and requires no mode control bit selection. The
transmitter operates in either serial or parallel mode as selected
by mode control bit C:5 (TPDM).
If the host does not respond to the channel data request within
eight bit times, the RXCD register is over written or the TXCD
register is sent again.
Refer to Channel Data Parallel Mode Control flow chart for recommended software sequence.
3-25
2400 bps V.26 bis, Bell 201B/C Modem
R24BKJ
R24BKJ Interface Memory Definitions
Mnemonic
Name
Memory
Location
Description
CDET
Carrier Detector
8:5
The one state of CDET indicates passband energy is being detected, and a training sequence is not
present. CDET goes to one at the start of the data state, and returns to zero at the end of the
received signal. CDET activates one baud time before RLSD and deactivates one baud time after RLSD.
CDIE
Channel Data
Interrupt Enable
E:6
When set to a one, CDIE enables an IRQ interrupt to be generated when the channel data
request bit (CDREQ) is a one.
CDREQ
Channel Data
Request
E:5
Parallel data mode handshaking bit. Set to a one when the modem receiver writes data to RXCD,
or the modem transmitter reads data from TXCD. CDREQ must be reset to zero by the host
processor when data service is complete.
CONF
Configuration
D:0-7
The 8-bit field CONF controls the configuration of the modem according to the following table:
Hex Code
0444
84
C4
OC
Configuration
v.26B,
V.26A,
V.26B,
V.26A,
Tone
Bell 201 B/C, Scrambler/descrambler disabled
Scrambler/descrambler disabled
Bell 201B/C, Scrambler/descrambler enabled
Scrambler/descrambler enabled
-Default value at POR with 220 ms turn-on sequence.
Configuration Definitions
V.26JBell 201-The modem operates as specified in CCITT Recommendation v.26 bis Alternate A
or B, and Bell 201 B/C, at a 2400 bps data rate.
Tone-The modem sends single or dual frequency tones in response to the RTS or RTSP signals.
Tone frequencies and amplitudes are controlled by RAM locations written by the host. When not
transmitting tones the Tone configuration allows detection of single frequency tones by the TDET
bit. The tone detector frequency can be changed by the host by altering the contents of several
RAM locations.
DDIE
Diagnostic Data
Interrupt Enable
E:2
When set to a one, DDIE enables an IRQ interrupt to be generated when the diagnostic data
request bit (DDREQ) is a one.
DDREQ
Diagnostic Data
Request
E:O
DDREQ goes to a one when the modem reads from or writes to DDYL. DDREQ goes to a zero
when the host processor reads from or writes to DDYL. Used for diagnostic data handshaking bit.
DDXL
Diagnostic Data
X Least
2:0-7
Least significant byte of 16-bit word used in reading XRAM locations.
DDXM
Diagnostic Data
X Most
3:0-7
Least significant byte of 16-bit word used in reading XRAM locations.
DDYL
Diagnostic Data
Y Least
0:0-7
Least significant byte of 16-bit word used in reading YRAM locations or writing XRAM and YRAM
locations.
DDYM
Diagnostic Data
Y Most
1:0-7
Most significant byte of 16-bit word used in reading YRAM locations or writing XRAM and YRAM
locations.
EQFZ
Equalizer Freeze
C:2
When EQFZ is a one, the adaptive equalizer taps stop updating and remain. frozen.
FED
Fast Energy
Detector
B:5,6
FED consists of a 2-bit field that indicates the level of received signal according to the following
code.
Code
o
1
2
3
Energy Level
None
Invalid
Above Turn-off Threshold
Above Turn-on Threshold
While receiving a signal, FED normally alternates between Codes 2 and 3.
3-26
2400 bps V.26 bis, Bell 201B/C Modem
R24BKJ
R24BKJ Interace Memory Definitions (continued)
Mnemonic
Name
Memory
Location
Description
GHIT
Gain Hit
B:4
The gain hit bit goes to one when the receiver detects a sudden increase in passband energy
faster than the AGC circuit can correct. GHIT returns to zero when the AGC output returns to
normal.
IA
Interrupt Active
E:7
IA is a one when the modem is driving the interrupt request line (IRQ) to a low TTL level.
RAMA
RAM Access
F:O-7
The RAMA register is written by the host when reading or writing diagnostic data. The RAMA
code determines the RAM location with which the diagnostic read or write is performed
RAMW
RAM Wrote
C:O
RAMW is set to a one by the host processor when performing diagnostic writes to the modem
RAM. RAMW IS set to a zero by the host when reading RAM diagnostic data.
RTSP
Request to Send
Parallel
C:7
The one state of RTSP begins a transmit sequence. The modem continues to transmit until RTSP
is turned off and the turn-off sequence has been completed. RTSP parallels the operation of the
hardware RTS control input. These inputs are ORed by the modem.
RXCD
Receiver
Channel Data
5:()"7
RXCD is written to by the modem every eight bit times. This byte of channel data can be read by
the host when the receiver sets the channel data request bit (CDREQ).
RX
Receive State
B:7
RX is a one when the modem is
SETUP
Setup
E:3
The host processor must set the SETUP bit to a one when reconfiguring the modem, i.e., when
changing CONF (D:O-7).
TDET
Tone Detected
A:7
The one state of TDET indicates reception of a tone. The filter can be retuned by means of the
diagnostic write routine.
TPDM
Transmitter
Parallel Data
Mode
C:5
When control bit TPDM is a one, the transmitter accepts data for transmission from the TXCD
register rather than the serial hardware data input.
TXCD
Transmitter
Channel Data
4:0-7
The host processor conveys output data to the transmitter in parallel data mode by writing a data
byte to the TXCD register when the channel data request bit (CDREQ) goes to a one. Data is
transmitted as single bits in V.21 or as dibils in V.27 starting with bit 0 or dibit 0,1.
Diagnostic Data Transfer
In
the receive state (i.e., not transmitting).
These bits are written into interface memory registers 3, 2, 1
and in that order. Registers 3 and 2 contain the most and least
significant bytes of XRAM data, respectively, while registers 1
and contain the most and least significant bytes of YRAM data
respectively.
°
The modem contains 128 words of random access memory
(RAM). Each word is 32-bits wide. Because the modem is
optimized for performing complex arithmetic, the RAM words
are frequently used for storing complex numbers. Therefore,
each word is organized into a real part (16 bits) and an imaginary
part (16-bits) that can be accessed independently. The portion
of the word that normally holds the real value is referred to as
XRAM. The portion that normally holds the imaginary value is
referred to as YRAM. The entire contents of XRAM and YRAM
may be read by the host processor via the microprocessor
interface.
°
When set to a one, bit C:O (RAMW) causes the modem to
suspend transfer of RAM data to the interface memory, and
instead, to transfer data from interface memory to RAM. When
writing into the RAM, only 16 bits are transferred, not 32 bits
as for a read operation. The 16 bits written in XRAM or YRAM
come from registers 1 and 0, with register 1 being the more
significant byte. Selection of XRAM or YRAM for the destination
is by means of the code stored in the RAMA bits of register F.
When bit F:7 is set to one, the XRAM is selected. When F:7
equals zero, YRAM is selected.
The interface memory acts as an intermediary during these host
to signal processor RAM data exchanges. The RAM address
to be read from or written to is determined by the contents of
register F (RAMA). The R24BKJ RAM Access Codes table lists
27 access codes for storage in register F and the corresponding
diagnostic functions. The R24BKJ Diagnostic Data Scaling table
provides scaling information for these diagnostic functions. Each
RAM word transferred to the interface memory is 32 bits long.
When the host processor reads or writes register 0, the
diagnostic data request bit E:O (DDREQ) is reset to zero. When
the modem reads or writes register 0, DDREQ is set to a one.
When set to a one by the host, bit E:2 (ODIE) enables the DDREQ
bit to cause an IRQ interrupt when set. While the IRQ line is
driven to a TTL low level by the modem, bit E:7 (IA) goes to a one.
3-27
II
II
I:
~
I
2400 bps V.26 bis, Bell 201B/C Modem
R24BKJ
l
l-TPOM
RX=O?
l-RTSP
OR
O-RTS
y
N
O-COREa
N
DATA -
COREa=l ?
TXCO
O-COREa
READ RXCD
N
CDREa=l ?
DONE?
N
0 - RTSP
AND
1 - RTS
EXIT
Channel Data Parallel Mode Control
3-28
N
R24BKJ
2400 bps V.26 bis, Bell 201B/C Modem
R24BKJ Diagnostic Data Scaling
R24BKJ RAM Access Codes
Node
Function
1
2
3
4
5
6
7
6
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
AGC Gain Word
Average Power
Receiver Sensitivity
Receiver HysteresIs
Equalizer Input
Equalizer Tap Coefficients
Unrotated Equalizer Output
Rotated Equalizer Output
Decision Points
Error Vector
Rotation Angle
Frequency Correction
EQM
Alpha (,,)
8eta One (13,)
Beta Two (132)
Alpha Prime (,,')
Beta One Prime (13,')
Beta Two Prime (1321
Alpha Double Prime (,,")
Beta Double Prime (13")
Output Level
Tone 1 Frequency
Tone 1 Level
Tone 2 Frequency
Tone 2 Level
Checksum
Fixed Synchronizing
Segment
Open SynchrOnizing
Segment
29
RAMA
Reg. No.
Node
81
F2
F1
84
58
1B-2A
68
OA
6C
6D
B7
88
80
36
37
38
39
3A
3B
B6
B7
43
8E
44
8F
45
02
11
2,3
2,3
2,3
2.3
0,1,2,3
0.1.2,3
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
2,3
2,3
2,3
0,1
0,1
0,1
0,1
0,1
0,1
2,3
2,3
0,1
2,3
0,1
2,3
0,1
0,1
2,3
5,7-9
11
Point
1
2
3
4
5
6
7
8
6
1
4
8
e5
X
6
Equalizer Tap Coefficients (32-bit, complex, twos
complement)
Complex numbers with X = real part, Y = Imaginary part
X and Y range: 0000 to (FFFF)'6 representing ± full scale
in hexadecimal twos complement.
Frequency Correction (16-blt signed twos complement)
Frequency correction In Hz
= (Freq. Correction Word/65,536) x Baud Rate
Range: (FCOO)'6 to (400),6 representing ± 18.75 Hz
13
EQM (16-bit, unsigned)
Filtered squared magnitude of error vector.
Proportionality to BER determined by particular application.
14-21
Filter Tuning Parameters (16-bit unsigned) Alpha, Beta One,
Beta Two, Alpha Prime, Beta One Prime, Beta Two Pnme,
Alpha DQuble Prime, and Beta Double Prime are set according
to instructions in application note 668. Use a sample rate of
7200 samples per second for all calculations.
22
Output Level (16-bit unsigned)
Output Number = 27573.6 [10(Po/20)]
Po = output power in dBm with senes 600 ohm resistor
into 600 ohm load.
Convert Output Number to hexadecimal and store at
access code 43
Average Power (16-blt unsigned)
Post-AGC Average Power in dBm
= 10 Log (Average Power Word/2185)
24
and
26
Receiver Sensitivity (16-bit twos complement)
On-Number = 655.36 (52.38 + PON)
In
23
and
25
dB
Convert On-Number to hexadecimal and store at access
code Fl
Receiver HystereSiS (16-bit twos complement)
Off-Number = [65.4 (10A)]'/2
A = (P OFF - PON - 0.5)/20
PON = Turn-on threshold in dB
POFF = Turn-off threshold in dB
Convert Off-Number to hexadecimal and store at access
code 84
3-29
,
'j
e7
12
Parameter/Scaling
where'
i
I
el
Rotation Angle (16-bit, signed, twos complement)
0,1
TYPical Value = (0689),6' corresponding to 0 dBm
Pre-AGC Power in dBm
= (Post-AGC Average Power-AGC Gain)
4
e3
Rotation Angle in deg. = (Rot. Angle Word/65,536) x 360
AGC Gain Word (16-bit unsigned).
where: PON = Turn-on threshold
1600
1F1C
1600
0000
EAOO
EOE4
EAOO
0000
l
If
2
11
Range: (16CO)'6 to (7FFF)'6, For - 43 dBm Threshold
3
1600
0000
EAOO
EOE4
EAOO
0000
1600
lF1C
i
V
Error Vector (32-bit, complex, twos complement)
Complex number With X = real part,
Y = Imaginary part.
X and Y range: (8000),6 to (7FFFh6
AGC Gain in dB = 50 - [(AGC Gain Word/64) x 0.098]
2.
Value (hex)
V
X
10
R24BKJ Diagnostic Data Scaling
Node
Parameter/Scaling
All base-band Signal point nodes (I.e., Equalizer Input,
Unrotated Equalizer Output, Rotated Equalizer Output,
and Decision Points) are 32-bit, complex, twos
complement numbers.
Tone 1 and Tone 2 Levels
Calculate the power of each tone independently by using
the equation for Output Number given at node 22.
Convert these numbers to hexadecimal then store at
access codes 44 and 45. Total power transmitted In tone
mode is the result of both tone 1 power and tone 2 power.
Tone 1 and 2 Frequency (16-bit unsigned)
N = 9.1022 (Frequency in Hz)
Convert N to hexadecimal then store at access code 8E
or8E
27
Checksum (16-bit unsigned)
ROM checksum number determined by reviSion level.
28,29
Fixed and Open Synchronizing Segments (16-bIt unsigned)
SynchrOnizing Sequence = [Fixed + (Open + 1)] baud times
(± 1 baud time)
7FFF'6 '" Fixed, Open baud times", 0
(baud time = 111200 = 0.833 ms)
Fixed = unscrambled ones
Open = unscrambled or scrambled ones
il
•
2400 bps V.26 bis, Bell 201B/C Modem
R24BKJ
POWER-ON INITIALIZATION
PERFORMANCE
When power is applied to the R24BKJ, a period of 50 to 350 ms
is required for power supply settling. The power-an-reset signal
(POR) remains low during this period. Approximately 10 ms after
the low to high transition of POR, the modem is ready to be
configured, and RTS may be activated. If the 5 Vdc power supply
drops below approximately 3 Vdc for more than 30 msec, the
POR cycle is repeated.
The R24SKJ proVides the user with unexcelled high performance.
TYPICAL BIT ERROR RATES
The Bit Error Rate (SER) performance of the modem is specified
for a test configuration conforming to that illustrated in eelD
Recommendation V.56. Bit error rates are measured at a received
line signal level of -20 dBm.
RECEIVED SIGNAL FREQUENCY TOLERANCE
At POR time the modem defaults to the following configuration:
V.26B, scrambler disabled, serial mode, 90 ms synchronizing
signal, interrupt disabled, RAM access code OA, transmitter
output level set for + 5 dBm at TXA, receiver turn-on threshold
set for -43.5 dBm, receiver turn-off threshold set for -47.0 dBm,
tone 1 and tone 2 set for 0 Hz and 0 volts output, and tone
detector parameters zeroed.
The receiver circuit of the R24BKJ can adapt to received
frequency error of ± 10 Hz with less than 0.2 dB degradation in
BER performance.
TYPICAL PHASE JITTER
The modem exhibits a BER of 10--il or less with a signal-to-noise
ratio of 12.5 dB in the presence of 15° peak-to-peak phase jitter
at 150 Hz or with a signal-to-noise ratio of 15 dB in the presence
of 30° peak-ta-peak phase jitter at 120 Hz (scrambler inserted).
POR can be connected to a user supplied power-an-reset signal
in a wire-or configuration. A low active pulse of 3 pSec or longer
applied to the POR pin causes the modem to reset. The modem
is ready to be c~ured 10 msec after the low active pulse is
removed from POR.
An example of the BER performance capabilities is given in the
following diagrams:
V26,2400
V26,2400
I
10- 3
I
10 - 3
\
10-"
10-"
w
w
I-
I-
<
a:
oc(
a:
a:
0
a:
a:
0
w
ffi
a:
a:
I-
I-
iii
iii
10- 5
10- 5
\
10- 6
0
5
10
15
20
SIGNAL TO NOISE RATIO IN DB
\
10- 6
25
0
15
20
10
SIGNAL TO NOISE RATIO IN DB
5
Typical Bit Error Rate
(Unconditioned 3002 Line, Level - 20 dBm)
Typical Bit Error Rate
(Back-to-Back, Level - 20 dBm)
3-30
25
2400 bps V.26 bis, Bell 201 BIC Modem
R24BKJ
The BER performance test set-up is show in the following
diagram:
-
MODEM
TRANSMITTER
r--
3002
LINE
SIMULATOR
SEG FA-1445
r--
IMPAIRMENT
SOURCE
BRADLEY 2A
AND 2B
ATTENUATOR
HP 350D
-
I
I
MODEM
TEST SET
PHOENIX
5000
LEVEL
METER
HP 3552A
MODEM
RECEIVER
I
NOTE
SIGNAL AND NOISE ARE MEASURED WITH 3 KHZ FLAT WEIGHTING.
BER Performance Test Set-up
3-31
R24BKJ
2400 bps V.26 bis, Bell 201B/C Modem
APPLICATION
5. Pin 22 should be tied directly to pin 24 at the R24BKJ
package. Pin 24 should tie directly, by a unique path, to the
common ground pOint for analog and digital ground.
Recommended Modem Interface Circuit
6. An analog ground plane should be supplied beneath all
analog components. The analog ground plane should
connect to pin 24 and all analog ground points shown in the
recommended circuit diagram.
The R24BKJ is supplied as a 64-pin QUIP device to be designed
into original equipment manufacturer (OEM) circuit boards. The
recommended modem interface circuit and parts list illustrate
the connections and components required to connect the modem
to the OEM electronics.
7. Pins 4, 8, 29, and 48 should tie together at the R24BKJ
package. Pin 48 should tie directly, by a unique path, to the
common ground point for analog and digital ground.
If the auxiliary analog input (pin 26) is not used, resistors R2
and R3 can be eliminated and pin 26 must be connected to
analog ground (pin 24). When the cable equalizer controls
CABLEl and CABLE2 are connected to long leads that are
subject to picking up noise spikes, a 3k n series resistor should
be used on each input (Pins 32 and 33) for isolation.
8. A digital ground plane should be supplied to cover the
remaining allocated area. The digital ground plane should
connect to pin 48 and all digital ground points shown in the
recommended circuit diagram plus the crystal-can ground.
9. The R24BKJ package should be oriented relative to the two
ground planes so that the end containing pin 1 is toward the
digital ground plane and the end containing pin 32 is toward
the analog ground plane.
Resistors R4 and R9 can be used to trim the transmit level and
receive threshold to the accuracy required by the OEM
equipment. For a tolerance of ± 1 dB the 1% resistor values
shown are correct for more than 99.8% of the units.
10. As a general rule, digital signals should be routed on the
component side of the PCB while analog signals are routed
on the solder side. The sides may be reversed to match a
particular OEM requirement.
Typical Modem Interface Parts List
Component
Manufacturer's
Part Number
C3,C5,C7,C9
C2
592CX7Rl04M050B
N511BY100JW
Cl
Cll
Yl
Zl
R5,R6
Cl14C330J2G5CA
SA405C274MM
333R14-002
LM1458N
CML 1/10
T86.6K ohm ± 1%
5MA434.0K ± 1%
5043CX3ROOOJ
5043CX2M700J
5043CX47KOOJ
5043CX3KOOJ
5043CXl KOOJ
ECEBEF100
SMC50Tl ROM5X12
C124Cl02J5G5CA
IN751D
CRB '/4XF47K5
ER0250KF2370
Determined by IRO
characteristics
R4
Rll
Rl0
Rl
R7
R2,R3
Cl0
C8
C4,C6
CRl
R9
R8
R14
Manufacturer
11. Routing of R24BKJ signals should provide maximum
isolation between noise sources and sensitive inputs. When
layout requirements necessitate routing these signals
together, they should be separated by neutral signals. Refer
to the table of noise characteristics for a list of pins in each
category.
Sprague
San Fernandol
Wescap
Kemet
AVX
Uniden
National
Pin Noise Characteristics
Dale Electronics
Corning Electronics
Mepco Electra
Mepco Electra
Mepco Electra
Mepco Electra
Mepco Electra
Panasonic
United Chern-Con
Kemet
I.T.T.
R-Ohm
Matsushita Electric
Noise Source
Low
Neutral
Low
High
1
2
5
14
15
20
21
6
7
9
10
12
13
17
18
19
45
46
49
50
51
52
53
54
55
56
57
58
59
3
4
8
11
16
22
24
25
29
31
34
42
43
47
48
26
28
32
33
23
27
35
36
37
30
38
39
40
41
44
PC Board Layout Considerations
1. The R24BKJ and all supporting analog circuitry, including
the data access arrangement if required, should be located
on the same area of printed circuit board (PCB).
2. All power traces should be at least 0.1 inch width.
3. If power source is located more than approximately 5 inches
from the R24BKJ, a decoupling capacitor of 10 microfarad
or greater should be placed in parallel with Cl1 near pins 11
and 48.
60
61
62
63
64
4. All circuitry connected to pins 9 and 10 should be kept short
to prevent stray capacitance from affecting the oscillator.
3-32
Noise Sensitive
High
JJ
I\)
~
OJ
~
C1
p."
=~
5%, SOY
C2
":'"
POR
CABLEl
CABlEl 32
CASLE2
CABLE2 33
10 PF
5%, SOY
-""AuXiN'
C3
R1
AOUT
AGelN
AUXI
.,:II
0
3
3
,.
OAOUY
SERIAL
INTERFACE
OAIN
ADOut
8.
lXA
1%
V 2.
mA
mA
- 0.1 max.
16 max.
OB
InputlOutput
OC
IIOA
IIOB
2.0 min
5.25 max.
2.0 min.
0.8 max.
2.4 mln. 3
0.4 max. S
,
0.4 max,>
0.4 max. 2
1.6 max.
1.6 max.
0.8 max.
2.4 min.
0.4 max,>
± 12.5 max'
± 10 max.
~A
~
pF
pF
-240 max.
-10 min.
5
5
TTL
TTL
w/Pull-up
-240 max.
-10 min.
20
100
TTL
TTL
w/Pull-up
3. I load = -40 ~A
4. V,N = 0.4 to 2.4 Vdc, Vee
5. I load = 0.36 mA
-100 ~A
1.6 mA
-240 max.
-10 min.
=
-260 max.
-100 min.
10
40
100
100
100
100
Open-Drain
3 State
Open-Drain Open Drain
w/Pull-up Transceiver w/Pull-up
5.25 Vdc
--
Analog Interface Characteristics
Analog Interface Characteristics
Name
Type
TXOUT
AA
Characteristics
The transmitter output can supply a
maximum of ± 3.03 volts Into a load
resistance of 10k 0 minimum. In order to
match to 600 0, an external smoothing
filter with a transfer function of
15726.43/(S + 11542.44) and 604 0 series
resistor are required.
RXIN
AB
The receiver input impedance is greater
than 1M O. An external antialiasing filter
with a transfer function of
19533.88/(S + 11542.44) is required.
AUXI
AC
The auxiliary analog input allows access
to the transmitter for the purpose of
interfacing with user prOVided equipment.
Because this is a sampled data input, any
signal above 4800 Hz will cause aliasing
errors. The Input impedance is 1M 0, and
the gain to transmitter output (TXA) IS
+5.6 dB ± 1 dB.
READ
(i
WRITE
RSi
0-3)
WRITE
Note: Absolute maximum voltage ratings for analog inputs are: ( - 5
VA - 0.3) s V,N S (+5 VA + 0.3)
READ
Microprocessor Interface Timing Requirements
Characteristic
CS, RSi setup time prior
to READ or WRITE
Data Access time after READ
Data hold time after READ
CS, RSI hold time after
READ or WRITE
Write data setup time
Wnte data hold time
WRITE strobe pulse Width
Symbol
Min
Max
Units
TCS
lOA
lOH
30
-
ns
-
140
50
ns
n5
TCH
TWOS
TWDH
TWR
10
75
10
-
ns
n5
ns
ns
10
75
Di
(i
= 0-1)
Microprocessor Interface Timing Waveforms
3-39
il
o
I
4800 bps MONOFAX Modem
R48MFX
Cable Equalizers
data out of or write data into these registers. Refer to the R48MFX
Host Processor Interface figure.
Modems may be connected by direct wiring, such as leased
telephone cable or through the public switched telephone network, by means of a data access arrangement. In either case,
the modem analog signal is carried by copper wire cabling for
at least some part of its route. The cable characteristics shape
the passband response so that the lower frequencies of the passband (300 Hz to 1700 Hz) are attenuated less than the higher
frequencies (1700 Hz to 3300 Hz). The longer the cable the more
pronounced the effect.
When information in these registers is being discussed, the format Z:O is used. The register is specified by Z(O-F), and the bit
by 0(0-7, 0 = LSB). A bit is considered to be "on" when set to
a one (1) and "off" when reset to a zero (0).
Status/Control Bits
The operation of the R48MFX IS affected by a number of software control inputs. These inputs are written into registers within
the interface memory via the host microprocessor bus. Modem
operation is monitored by various software flags that are read
from interface memory via the host microprocessor bus.
To minimize the impact of this undesired passband shaping, a
compromise equalizer with more attenuation at lower frequencies than at higher frequencies can be placed in series with the
analog signal. The modem includes three such equalizers
designed to compensate for cable distortion.
All status and control bits are defined in the R48MFX Interface
Memory Map table. Bits designated by , - ' are reserved for
modem use only and must not be changed by the host.
Cable Equalizer Selection
CABLE2
CABLEI
Length of O.4mm Diameter Cable
0
0
1
1
0
1
0
1
0.0
1.8 km
3.6 km
7.2 km
Anyone of the registers may be read or written on any host read
or write cycle, but all eight bits of that register are affected. In
order to read a single bit or a group of bits in a register, the host
processor must mask out unwanted data. When writing a single
bit or group of bits in a register the host processor must perform
a read-modify-write operation. That is, the entire register is read,
the necessary bits are set or reset in the accumulator of the host,
then the original unmodified bits and the modified bits are written
back into the register of the interface memory.
Analog Signals
Three analog signals provide the interface point for telephone
company audio circuits and host audio inputs. Signals TXOUT
and RXIN require buffering and filtering to be suitable for driving
and receiving the communication channel. Signal AUXI provides
access to the transmitter for summing host audio signals with
the modem analog output.
Configuration Control
Four configurations are available in the R48MFX modem: V.27
4800/2400 bps long train, V.21, and Tone. The configuration is
The filters required for anti-aliasing on the receiver input and
smoothing on the transmitter output have a single pole located
at 11,542 radians. Although this pole is located within the modem
passband, internal filters compensate for its presence and,
therefore, the pole location must not be changed. Some variation from recommended resistor and capacitor values is permitted as long as the pole is not moved, overall gain is preserved,
and the device is not required to drive a load of less than 10k n.
selected by writing an 8-bit binary code into the configuration
field (CONF) of the interface memory. The configuration field
consists of bits 7 through 0 of register D. The code for these
bits is shown in the following table. All other codes represent
invalid states.
Configuration Codes
CONF Code
Notice that when reference is made to signals TXA, RXA, and
AUXIN, these signals are not electrically identical to TXOUT,
RXIN, and AUXI. The schematic of the recommended modem
interface circuit illustrates the differences.
00
04
06*
08
Configuration
V.21
V.27, 2400 Long Train
V.27, 4800 Long Train
Tone Mode
* Default value at POR.
Overhead
Except for the power-on-reset signal PORO, the overhead
signals are intended for internal use only. The various required
connections are illustrated in the recommended modem interface circuit schematic. No host connections should be made to
overhead signals other than ·PORO.
When the modem is initialized by power-on-reset, the configuration defaults to V.27 4800 bps. When the host wants to change
configuration, the new code is written to the configuration field
and the SETUP bit (E:3) is set to a one. Once the new configuration takes effect, the SETUP bit is reset to zero by the modem.
SOFTWARE CIRCUITS
The information in the interface memory is serviced by the
modem at the baud rate (V.27 and V.21), 9600 times per second
(tone generator), or 1600 times per second (tone detector).
The R48MFX contains 16 memory mapped registers to which
an external (host) microprocessor has access. The host may read
3-40
"
,i
!
I
4800 bps MONOFAX Modem
R48MFX
READ
READ
WRITE
LOGIC
8
8
00-07
REGISTER
SELECT
LOGIC
RSO-RS3 _4+-+--~
r---:---~~~~~
INTERFACE MEMORY
R48MFX Host Processor Interface
To enable the transmitter parallel mode, TPDM must be set to
a 1. The modem automatically defaults to the serial mode
(TPDM = 0) at power-on. In either transmitter serial or parallel
mode, the R48MFX is configured by the host processor via the
microprocessor bus.
R48MFX Interface Memory Map
~
7
5
6
3
4
2
1
0
Register
F
Serial Mode-The senal mode uses a standard V.24 (RS-232-C)
hardware interface (optional USRT) to transfer channel data.
Transmitter data can be sent serially only when TPDM is set to
a zero.
RAMA
E
IA
COlE COREQ
-
0
SETUP
ODIE
-
OOREQ
CONF
C
RTSP
B
RX
A
TDET
-
9
8
7
6
EPT
TPOM TDIS
FED
-
GHIT
-
-
CDET
-
-
-
5
EOSV EQFZ
-
SDIS RAMW
PN
-
-
-
-
-
-
-
Parallel Mode-Parallel data is transferred via two registers in
the interface memory. Register 5 (RXCD) is used for receiver
channel data, and Register 4 (TXCD) is used for transmitter channel data. Register 5 is continuously written every eight bit times
when in the receive state. Register 4 is used as the source of
channel transmitter data only when bit C:5 (TPDM) is set to a one
by the host. Otherwise the transmitter reads data from the V.24
interface. Both RTS and RTSP remain enabled, however, regardless of the state of TPDM.
-
-
RXCD
4
TXCD
3
DDXM
2
DDXL
1
DOYM
0
DDYL
I~
7
6
5
4
3
2
1
When performing parallel data transfer of channel data, the host
and modem can synchronize their operations by handshaking bits
in register E. Bit E:5 (CDREQ) is the channel data request bit.
This bit is set to a one by the modem when receiver data is
available in RXCD or when transmitter data is required in TXCD.
Once the host has finished reading RXCD or writing TXCD, the
host processor must reset CDREQ by writing a zero to that bit
location.
0
Bit
When set to a one by the host, Bit E:6 (CDIE) enables the CDREQ
bit to cause an IRQ interrupt when set. While the IRQ line is
d.-iven to a TTL low level by the modem, bit E:7 (IA) is a one.
Channel Data Transfer
Data sent to or received from the data channel may be transferred
between the modem and host processor in either serial or parallel
form. The receiver operates in both serial and parallel mode
simultaneously and requires no mode control bit selection. The
transmitter operates in either serial or parallel mode as selected
by mode control bit C:5 (TPDM).
If the host does not respond to the channel data request within
eight bit times, the RXCD register is over written or the TXCD
register is sent again.
Refer to Channel Data Parallel Mode Control flow chart for recommended software sequence.
3-41
R48MFX
4800 bps MONOFAX Modem
R48MFX Interface Memory Definitions
Mnemonic
Name
Memory
Location
Description
CDET
Carrier Detector
8:5
The one state of CDET indicates passband energy is being detected, and a training sequence is
not present. CDET goes to one at the start of the data state, and returns to zero at the end of the
received signal. CDET activates one baud time before RLSD and deactivates one baud time after
RLSD.
COlE
Channel Data
Interrupt Enable
E:6
When set to a one, COlE enables an IRQ interrupt to be generated when the channel data
request bit (CDREQ) is a one.
CDREQ
Channel Data
Request
E:5
Parallel data mode handshaking bit. Set to a one when the modem receiver writes data to RXCD,
or the modem transmitter reads data from TXCD. CDREQ must be reset to zero by the host
processor when data service is complete.
CONF
Configuration
0:0-7
The B-bit field CONF controls the configuration of the modem according to the following table:
Configuration
V.21
V.27, 2400 Long Train
V.27, 4600 Long Train (Default)
Tone
Invalid
Hex Code
00
04
06
08
All else
Configuration Definitions
V.21-The modem operates as a CCITI T.30 compatible 300 bps FSK modem having
characteristics of the CCITI V.21 Channel 2 modulation system.
Tone-The modem sends Single or dual frequency tones in response to the RTS or RTSP signals.
Tone frequencies and amplitudes are controlled by RAM locations written by the host. When not
transmitting tones the Tone configuration allows detection of single frequency tones by the TDET
bit. The tone detector frequency can be changed by the host by altering the contents of several
RAM locations.
V.27-The modem is compatible with CCITI Recommendation V.27 ter.
ODIE
Diagnostic Data
Interrupt Enable
E:2
When set to a one, ODIE enables an IRQ interrupt to be generated when the diagnostic data
request bit (DDREQ) is a one.
DDREQ
Diagnostic Data
Request
E:O
DDREQ goes to a one when the modem reads from or writes to DDYL. DDREQ goes to a zero
when the host processor reads from or writes to DDYL. Used for diagnostic data handshaking bit.
DDXL
Diagnostic Data
X Least
2:0-7
Least Significant byte of 1B-bit word used in reading XRAM locations.
DDXM
Diagnostic Data
X Most
3:0-7
Least significant byte of 1B-bit word used in reading XRAM locations.
DDYL
Diagnostic Data
Y Least
0:0-7
Least significant byte of 16-bit word used in reading YRAM locations or writing XRAM and YRAM
locations.
DDYM
Diagnostic Data
Y Most
1:0-7
Most significant byte of 16-bit word used in reading YRAM locations or writing XRAM and YRAM
locations.
EPT
Echo Protector
Tone
C:6
When EPT is a one, an unmodulated carrier is transmitted for 185 ms followed by 20 ms of no
transmitted energy at the beginning of the training sequence. EPT is not active if TDIS is on.
EQFZ
Equalizer Freeze
C:2
When EQFZ is a one, the adaptive equalizer taps stop updating and remain frozen.
EQSV
Equalizer Save
C:3
When EQSV is a one, the adaptive equalizer taps are not zeroed when reconfiguring the modem
or when entering the training state. Adaptive equalizer taps are also not updated during training.
FED
Fast Energy
Detector
8:5,6
FED consists of a 2-bit field that indicates the level of received signal according to the following
code.
Code
Energy Level
o
None
1
Invalid
Above Turn-off Threshold
2
Above Turn-on Threshold
3
While receiving a signal, FED normally alternates between Codes 2 and 3.
3-42
R48MFX
4800 bps MONOFAX Modem
R48MFX Interace Memory Definitions (continued)
Name
Mnemonic
GHIT
Gain Hit
IA
PN
Memory
Location
Description
B'4
The gain hit bit goes to one when the receiver detects a sudden Increase In passband energy
faster than the AGC CirCUit can correct. GHIT returns to zero when the AGC output returns to
normal.
Interrupt Active
E.7
IA IS a one when the modem is driving the interrupt request line (IRQ) to a low TTL level.
Period N
8:3
PN sets to a one at the start of the received PN sequence. PN resets to zero at the start of the
received scrambled ones. PN does not operate when TDIS is set to a one.
RAMA
RAM Access
FO-7
The RAMA register is written by the host when reading or writing diagnostic data. The RAMA
code determines the RAM location with which the diagnostic read or write is performed.
RAMW
RAM Write
C:O
RAMW is set to a one by the host processor when performing diagnostic writes to the modem
RAM. RAMW is set to a zero by the host when reading RAM diagnostic data.
RTSP
Request to Send
Parallel
C'7
The one state of RTSP begins a transmit sequence. The modem continues to transmit until RTSP
IS turned off and the turn-off sequence has been completed. RTSP parallels the operation of the
hardware RTS control input. These inputs are ORed by the modem.
RXCD
Receiver Channel
Data
5.0-7
RXCD is written to by the modem every eight bit times. This byte of channel data can be read by
the host when the receiver sets the channel data request bit (CDREQ).
RX
Receive State
B:7
RX
SDIS
Scrambler Disable
C:1
When SDIS IS a one, the scrambler/descrambler
scrambler/descrambler is enabled (default)
SETUP
Setup
E:3
The host processor must set the SETUP bit to a one when reconfiguring the modem, I.e., when
changing CONF (D:O-7).
TDET
Tone Detected
A:7
The one state of TDET indicates reception of a tone. The filter can be retuned by means of the
diagnostic write routine.
TDIS
Training Disable
C:4
If TDIS is a one in the receive state, the modem is prevented from entering the training phase. If
TDIS is a one when RTS or RTSP go active, the generation of a training sequence is prevented at
the start of transmission.
TPDM
Transmitter Parallel
Data Mode
C:5
When control bit TPDM is a one, the transmitter accepts data for transmission from the TXCD
register rather than the serial hardware data input.
TXCD
Transmitter
Channel Data
4:0-7
The host processor conveys output data to the transmitter in parallel data mode by writing a data
byte to the TXCD register when the channel data request bit (CDREQ) goes to a one. Data IS
transmitted as Single bits In V.21 or as dibits In V.27 starting with bit 0 or dibit 0,1.
15
a one when the modem is in the receive state (i.e., not transmitting).
Diagnostic Data Transfer
15
disabled. When SDIS is a zero, the
These bits are written into interface memory registers 3, 2, 1
and 0 in that order. Registers 3 and 2 contain the most and least
significant bytes of XRAM data, respectively, while registers 1
and 0 contain the most and least significant bytes of YRAM data
respectively.
The modem contains 128 words of random access memory
(RAM). Each word is 32-bits wide. Because the modem is
optimized for performing complex arithmetic, the RAM words
are frequently used for storing complex numbers. Therefore,
each word is organized into a real part (16 bits) and an imaginary
part (16-bits) that can be accessed independently. The portion
of the word that normally holds the real value is referred to as
XRAM. The portion that normally holds the imaginary value is
referred to as YRAM. The entire contents of XRAM and YRAM
may be read by the host processor via the microprocessor
interface.
When set to a one, bit C:O (RAMW) causes the modem to suspend transfer of RAM data to the interface memory, and instead,
to transfer data from interface memory to RAM. When writing
into the RAM, only 16 bits are transferred, not 32 bits as for a
read operation. The 16 bits written in XRAM or YRAM come from
registers 1 and 0, with register 1 being the more significant byte.
Selection of XRAM or YRAM for the destination is by means of
the code stored in the RAMA bits of register F. When bit F:7
is set to one, the XRAM is selected. When F:7 equals zero,
YRAM is selected.
The interface memory acts as an intermediary during these host
to signal processor RAM data exchanges. The RAM address to
be read from or written to is determined by the contents of
register F (RAMA). The R48MFX RAM Access Codes table lists
27 access codes for storage in register F and the corresponding
diagnostic functions. The R48MFX Diagnostic Data Scaling table
provides scaling information for these diagnostic functions. Each
RAM word transferred to the interface memory is 32 bits long.
When the host processor reads or writes register 0, the
diagnostic data request bit E:O (DDREQ) is reset to zero. When
the modem reads or writes register 0, DDREQ is set to a one.
When set to a one by the host, bit E:2 (ODIE) enables the DDREQ
bit to cause an IRQ interrupt when set. While the IRQ line is
driven to a TTL low level by the modem, bit E:7 (IA) goes to a one.
3-43
4800 bps MONOFAX Modem
R48MFX
l-TPDM
N
l-RTSP
OR
O-RTS
v
N
O-CDREO
N
DATA -
TXCD
O-CDREO
READ RXCD
N
N
N
0 - RTSP
AND
1 - RTS
Channel Data Parallel Mode Control
3·44
i
I
R48MFX
4800 bps MONOFAX Modem
R48MFX Diagnostic Data Scaling (Cont'd)
R48MFX RAM Access Codes
Node
Function
RAMA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
AGC Gain Word
Average Power
ReceIver Sensitivity
Receiver Hysteresis
Equalizer Input
Equalizer Tap Coefficients
Unrotated Equalizer Output
Rotated Equalizer Output
Decision Points
Error Vector
Rotation Angle
Frequency Correction
EQM
Alpha (a)
Beta One (Il,)
Beta Two (1l2)
Alpha Prime (a')
Beta One Prime (Il,')
Beta Two Prime (Il,,)
Alpha Double Prime (a")
Beta Double Prime (Il")
Output Level
Tone 1 Frequency
Tone 1 Level
Tone 2 Frequency
Tone 2 Level
Checksum
fS7
91
47
84
63
23-32
73
OA
74
75
B3
8B
89
38
39
3A
3B
3C
3D
B8
B9
43
8E
44
8F
45
02
.-
Reg. No.
2,3
2,3
Node
Parameter/Scaling
5,7-9
All base-band Signal point nodes (i.e., Equalizer Input,
Unrolated Equalizer Output, Rotated Equalizer Output, and
DecisIon Points) are 32-bit, complex, twos complement
numbers.
0,1
2,3
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
2,3
2,3
2,3
0,1
0,1
0,1
0,1
0,1
0,1
2,3
2,3
0,1
2,3
0,1
2,3
0,1
0,1
Value (Hex)
y
Point
X
y
1
2
3
4
5
6
7
8
1000
OCOO
F400
E300
E300
F400
OCOO
1000
OCOO
1000
1000
OCOO
F400
E300
E300
F400
e3
e2
e4
el
e5
e8
X
e6
e7
if..
6
Equalizer Tap Coefficients (32-bit, complex, twos
complement)
Complex numbers with X
= real
part, Y
=
imaginary part
X and Y range: 0000 to (FFFF)'6 representing ± full scale
in hexadecimal twos complement.
10
11
Error Vector (32-bit, complex, twos complement)
Complex number with X = real part,
Y = imaginary part.
X and Y range: (8000)'6 to (7FFF)'6
Rotation Angle (IS-bIt, signed, twos complement)
Rotation Angle in deg.
12
=
(Rot. Angle Word/65,536) x 360
Frequency Correction (16-bit signed twos complement)
Frequency correction in Hz
= (Freq. Correction Word/65,536) x Baud Rate
Range: (FCOO)'6 to (400),6 representing ± 18.75 Hz
R48MFX Diagnostic Data Scaling
Node
1
Parameter/Scaling
13
EQM (16-bit, unsigned)
Filtered squared magnitude of error vector.
Proportionality to BER determined by particular applicatIon.
14-21
Filter Tuning Parameters (16-bit unsigned) Alpha, Beta One,
Beta Two, Alpha Prime, Beta One Prime, Beta Two Prime,
Alpha Double Prime, and Beta Double Prime are set accordIng
to instructions In application note 668.
22
Output Level (16-bit unsigned)
Output Number = 27573.6 [10IPo/20)]
AGC Gain Word (16-bit unsigned).
AGC Gain in dB
=
50 - [(AGC Gain Word/64) x 0.098]
Range: (16CO)'6 to (7FFF)'6' For - 43 dBm Threshold
2.
Average Power (16-bit unsigned)
Post-AGC Average Power in dBm
= 10 Log (Average Power Word/2185)
Typical Value = (0889),6, corresponding to 0 dBm
Pre-AGC Power in dBm
= (Post-AGC Average Power-AGC Gain)
3
Po
where: PaN
= 655.36 (52.38 + PaN)
= Turn-on threshold in dB
Convert On-Number to hexadecimal and store at access
code 47
4
24
and
26
Tone 1 and Tone 2 Levels
Calculate the power of each tone independently by using
the equation for Output Number given at node 22. Convert
these numbers to hexadecimal then store at access codes
44 and 45. Total power transmitted in tone mode IS the
result of both tone 1 power and tone 2 power.
23
and
25
Tone 1 and 2 Frequency (16-bit unsigned)
N = 6.8267 (Frequency in Hz)
Convert N to hexadecimal then store at access code 8E
or8F.
27
Checksum (16-bit unsigned)
ROM checksum number determined by revision level.
Receiver Hysteresis (l6-bit twos complement)
Off-Number
where:
A
PaN
POFF
output power in dBm with series 600 ohm resistor
into 600 ohm load.
Convert Output Number to hexadecimal and store at
access code 43
Receiver Sensitivity (16-bit twos complement)
On-Number
=
= [65.4 (10A)]'/2
= (POFF - PaN - 0.5)/20
= Turn-on threshold in dB
= Turn-off threshold in dB
Convert Off-Number to hexadecimal and store at access
code 84.
3-45
'I
II
I,
D
I
4800 bps MONOFAX Modem
R48MFX
POWER-ON INITIALIZATION
TYPICAL BIT ERROR RATES
When power is applied to the R48MFX, a period of 50 to 350 ms
is required for power supply settling. The power-on-reset signal
(POR) remains low during this period. Approximately 10 ms after
the low to high transition of POR, the modem is ready to be
configured, and RTS may be activated. If the 5 Vdc power supply
drops below approximately 3 Vdc for more than 30 msec, the
POR cycle is repeated.
The Bit Error Rate (BER) performance of the modem is specified
for a test configuration conforming to that illustrated in CCITT
Recommendation V.56. Bit error rates are measured at a
received line signal level of -20 dBm.
RECEIVED SIGNAL FREQUENCY TOLERANCE
The receiver circuit of the R48MFX can adapt to received
frequency error of ± 10Hz with less than 0.2 dB degradation
in BER performance.
At POR time the modem defaults to the following configuration:
V.27/4800 bps, serial mode, training enabled, echo protector
tone enabled, interrupts disabled, RAM access code OA,
transmitter output level set for + 5 dBm at TXA, receiver turnon threshold set for -43.5 dBm, receiver turn-off th reshold set
for -47.0 dBm, tone 1 and tone 2 set for 0 Hz and 0 volts output,
and tone detector parameters zeroed.
TYPICAL PHASE JITTER
At 4800 bps, the modem exhibits a BER of 10-6 or less with a
signal-to-noise ratio of 19 dB in the presence of 15° peak-topeak phase jitter at 60 Hz.
POR can be connected to a user supplied power-on-reset signal
in a wire-or configuration. A low active pulse of 3!,sec or longer
applied to the POR pin causes the modem to reset. The modem
is ready to be configured 10 msec after the low active pulse is
removed from POR.
PERFORMANCE
At 2400 bps, the modem exhibits a BER of 10-6 or less with a
signal-to-noise ratio of 12.5 dB in the presence of 15° peak-topeak phase jitter at 150 Hz or with a signal-to-noise ratio of 15 dB
in the presence of 30° peak-to-peak phase jitter at 120 Hz
(scrambler inserted).
Whether functioning as a V.27 ter or V.21 type modem, the
R48MFX provides the user with unexcelled high performance.
An example of the BER performance capabilities is given in the
following diagrams:
10- 3
FSK
V.27, 2400 V.27, 4800
FSK
I
10- 3
\
\
10-'
V.27,2400
V.27,4800
I
I
\
I
\
10-'
w
IIJ
t-
t-
a:
a:
0
a:
a:
a:
a:
0
a:
a:
w
~
~
IIJ
t-
t-
iii
iii
10- 5
10- 5
\
10- 6
0
\
5
10
15
20
SIGNAL TO NOISE RATIO IN DB
\
10- 6
0
25
5
\
I
10
15
20
SIGNAL TO NOISE RATIO IN DB
Typical Bit Error Rale
(Back-Io-Back, Level - 20 dBm)
Typical Bil Error Rate
(Unconditioned 3002 Line, Level - 20 dBm)
3-46
25
R48MFX
4800 bps MONOFAX Modem
The BER performance test set-up is show in the following
diagram:
.--
MODEM
TRANSMITTER
-
IMPAIRMENT
3002
SOURCE
ATTENUATOR
LINE
f---- BRADLEY 2A f---HP 350D
SIMULATOR
AND 2B
SEG FA-1445
I
I
MODEM
TEST SET
PHOENIX
5000
LEVEL
METER
HP 3552A
MODEM
RECEIVER
I
NOTE
SIGNAL AND NOISE ARE MEASURED WITH 3 KHZ FLAT WEIGHTING.
BER Performance Test Set-up
3-47
4800 bps MONOFAX Modem
R48MFX
APPLICATION
5, Pin 22 should be tied directly to pin 24 at the R48MFX
package, Pin 24 should tie directly, by a unique path, to the
common ground pOint for analog and digital ground,
Recommended Modem Interface Circuit
6, An analog ground plane should be supplied beneath all
analog components, The analog ground plane should
connect to Pin 24 and all analog ground points shown in the
recommended circuit diagram,
The R48MFX is supplied as a 64-pin QUIP device to be designed
into original equipment manufacturer (OEM) circuit boards, The
recommended modem interface circuit and parts list illustrate
the connections and components required to connect the modem
to the OEM electronics,
7, Pins 4, 8, 29, and 48 should tie together at the R48MFX
package, Pin 48 should tie directly, by a unique path, to the
common ground point for analog and digital ground,
If the auxiliary analog input (pin 26) is not used, resistors R2
and R3 can be eliminated and pin 26 must be connected to
analog ground (pin 24), When the cable equalizer controls
CABLEI and CABLE2 are connected to long leads that are
subject to picking up noise spikes, a 3k n series resistor should
be used on each input (Pins 32 and 33) for isolation,
8, A digital ground plane should be supplied to cover the
remaining allocated area, The digital ground plane should
connect to pin 48 and all digital ground POints shown in the
recommended circuit diagram plus the crystal-can ground,
9, The R48MFX package should be oriented relative to the two
ground planes so that the end containing pin I is toward the
digital ground plane and the end containing pin 32 is toward
the analog ground plane,
Resistors R4 and R9 can be used to trim the transmit level and
receive threshold to the accuracy required by the OEM
equipment. For a tolerance of ± 1 dB the 1% resistor values
shown are correct for more than 99,8% of the units,
10, As a general rule, digital signals should be routed on the
component side of the PCB while analog signals are routed
on the solder side, The sides may be reversed to match a
particular OEM requirement.
Typical Modem Interface Parts List
Component
C3,C5,C7,C9
Cll
Yl
ZI
R5,R6
R4
Rl1
RIO
Rl
R7
R2,R3
CIO
C8
C4,C6
CRI
R9
R8
R14
Manufacturer's
Part Number
592CX7R 104M050B
SA405C274MAA
333R14-002
LM1458N
CML 1/10
T86,6K ohm ± 1%
5MA434,OK ± 1%
5043CX3ROOOJ
5043CX2M700J
5043CX47KOOJ
5043CX3KOOJ
5043CXIKOOJ
ECEBEFIOO
SMC50Tl ROM5X12
C124Cl02J5G5CA
IN751D
CRB '/4XF47K5
ER025QKF2370
Determined by IRQ
characteristics
Manufacturer
11, Routing of R48MFX signals should prOVide maximum
isolation between noise sources and sensitive inputs, When
layout requirements necessitate routing these signals
together, they should be separated by neutral signals, Refer
to the table of noise characteristics for a list of pins in each
category,
Sprague
AVX
Uniden
National
Dale Electronics
Corning Electronics
Mepco Electra
Mepco Electra
Mepco Electra
Mepco Electra
Mepco Electra
Panasonic
United Chern-Con
Kemet
ITT,
R-Ohm
Matsushita Electric
Pin Noise Characteristics
Noise Source
PC Board Layout Considerations
2, All power traces should be at least 0,1 inch width,
3,
Low
Neutral
Low
High
I
2
5
14
15
20
21
30
38
39
40
41
6
7
9
10
12
13
3
4
8
11
16
22
24
25
29
31
34
42
43
47
48
26
28
32
33
23
27
35
36
37
44
1, The R48MFX and all supporting analog circuitry, including
the data access arrangement if required, should be located
on the same area of printed circuit board (PCB),
If power source IS located more than approximately 5 inches
from the R48MFX, a decoupling capacitor of 10 microfarad
or greater should be placed in parallel with Cll near pins 11
and 48,
4, All circuitry connected to pins 9 and 10 should be kept short
to prevent stray capacitance from affecting the oscillator,
3-48
Noise Sensitive
High
17
18
19
45
46
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
~
.1:10
CO
s:
'"T1
><
r
J.
10· XTLO
=~
VI
,..
POR
CABlE1
CABLEl 32
c::I11.98135
MHZ
CASLE2
CASLE2 33
C3
AuXiN
Rl
AOUT
AGCIN
:D
AUXI
CD
n
.,
TXOUT
3
3
CD
"
SERIAL
INTERFACE
OAIN
ADOUT
0
a.
CD
3
5"
57
49
o
07
5%, SOV
R8
R6
-5V
SYNCOUT
SYNCIN1
SYNCIN2
SYNCIN3
1N7510
CRl
S1V 1%
237 OHM
1%
86 6K 1%
R9
1458
53 04
MICROPROCESSOR
0
PARALLEL
INTERFACE
RXA
47-SK 1%
Z1
52 05
III
n
~r
fRO
CS
51 06
::l.
1000 PF
FOUT
FIN
+S VOLTS
CD
CD
C6
AOIN
RXIN
3:
<0
01 "F
DAOUT
a.
CD
a.
.;,
'"
C5
1%
V 2.
+12VOLTS
TXA
0
.,.
,
.. -12 VOLTS
54 03
5
C8
02
~
.. 01
~~3
1.0,F
61
62 RS2
63 AS1
64 RSO
§:
.1:10
CO
:0 :~~~E
Rl1
R48MFX
L - - - - - - - - - - - -.....----''"'-.h
Cl0
... 10 p.F
NOTES:
1.
2.
3.
UNLESS OTHERWISE SPECIFIED
RESISTOR VALUES ARE IN OHMS ±5% 1/4W
•
30HU
10%
25V
CAPACITOR VALUES ARE IN MICROFARADS ±20% SOV
C1 AND C2 NOT USED
!
Cl1
0.27 "F
+5 VOLTS
o
o
C"
'a
til
s:
oz
o
~
><
s:
o
Co
CD
-
3
c~~~~~~.~~. . . . . . . . . . . . . . . .~"'~~-
4800 bps MONOFAX Modem
R48MFX
PACKAGE DIMENSIONS
It
b
.020 TYP.
(.508 MM)
I
1.628
(41.35 MM)
~i
f3
~
i
w~
I
g ....
....
I
~
I
!-
-~-+
i
J
IJ
-~-~-.....:..:r-;.0;;;;50 REF
1_
(1.27MM)
TYP
t
.020 REF
TYP
1.50
(3.81 MM)
54-Pin QUIP
3-50
R48PCJ
Integral Modems
'1'
Rockwell
R48PCJ
4800 bps PC Communication Modem
INTRODUCTION
FEATURES
The Rockwell R48PCJ is a synchronous 4800 bits per second
(bps) modem in a single 64-pin quad in-line package (QUIP).
It is designed for operation over the public switched telephone
network through line terminations provided by a data access
arrangement (DAA).
•
•
•
•
•
•
•
•
The modem satisfies the telecommunications requirements
specified In CCITT recommendations V.'O ter, T.4 and the binary
signaling capabilities of T.30. The R48PCJ can operate at speeds
of 4800, 2400 and 300 bps, and includes the V.'O ter short training sequence option. Employing advanced signal processing
techniques, the R48PCJ can transmit and receive data even
under extremely poor line conditions.
•
User programmable features allow the modem operation to be
tailored to support a wide range of functional requirements. The
R48PCJ is optimized for incorporation into an original equipment
manufacturer (OEM) developed system. The modem's single
device peckage, low power consumption, and seriaUparailel host
interface simplify system design and allow direct installation on
the host module.
•
•
•
•
Single 64-Pin QUIP
CCITI V.27 ter, T.30, V.21 Channel 2, T.4
Group 3 Facsimile Transmission/Reception
Half-Duplex (2-Wire)
Programmable Dual Tone Generation
Programmable Tone Detection
Dynamic Range: - 43 dBm to 0 dBm
Diagnostic Capability
- Provides Telephone Line Quality Monitoring Statistics
Equalization
- Automatic Adaptive
- Compromise Cable (Selectable)
DTE Interface: Two Alternate Ports
- Microprocessor Bus
- CCITI V.24 (RS-232-C Compatible)
Low Power Consumption: 1W (Typical)
Programmable Transmit Output Level
TIL and CMOS Compatible
RIO
SYNClN3
NC
Rl1
Rl2
Rl3
PORI
DGND&
SYNClN2
Ne
Ne
DGN03
XTLI
XTLO
+SVD
WRITE
Ci
READ
IRQ
DO
D1
D2
RXD
D3
TXD
DAOUT
ADiN
D4
D5
D6
RCYI2
CTS
D7
DGND2
RlSD
RCYO
RTS
OClK
SYNCOUT
NC
Ne
SCLKD
POFiO
DGND1
AGCIN
Rei
AGND
SYNClN!
-SVA
PAIN
AUXI
ADOUT
FOUl"
SCLKIN2
RXIN
AOUT
FIN
RCYI1
CABlE2
TXOUT
DGND4
selKlN1
+5VA
CABlE1
Ne = NO CONNECTION
R48PCJ 4800 bps Modem
R48PCJ Pin Assignments
Document No. 29200N19
Data Sheet
3-51
Order No. MD21
Rev. 1, February 1987
R48PCJ
4800 bps PC Communication Modem
TECHNICAL CHARACTERISTICS
RECEIVE LEVEL
TONE GENERATION
The receiver circuit of the R48PCJ satisfies all specified performance requirements for received line signal levels from 0 dBm
to - 43 dBm. An external input buffer and filter must be supplied between the receiver analog input (RXA) and the R48PCJ
RXIN pin. The received line signal level is measured at RXA.
Under control of the host processor, the R48PCJ can generate single or dual frequency voice band tones up to 4800 Hz
with a resolution of 0.15 Hz and an accuracy of 0.01 %. The
transmit level and frequency of each tone is independently
programmable.
RECEIVE TIMING
TONE DETECTION
In the receive state, the R48PCJ provides a Data Clock (DCLK)
output in the form of a square wave. The low to high transitions
of this output coincide with the centers of received data bits.
The timing recovery circuit is capable of tracking a ± 0.01 % frequency error in the associated transmit timing source. DCLK
duty cycle is 50% ± 1%.
Single frequency tones are detected by a programmable filter.
The presence of energy at the selected frequency is indicated
by a bit in the interface memory.
SIGNALING AND DATA RATES
Signaling/Data Rates
Configuration
Parameter
V.27
Signaling Rate
Data Rate
Signaling Rate
Data Rate
V.21
Signaling Rate
Data Rate
TRANSMIT LEVEL
Specification
(±0.01%)
1600
4800
1200
2400
The transmitter output level is programmable. An external output buffer and filter must be supplied between the R48PCJ
TXOUT pin and the transmitter analog output (TXA). The default
level at TXA is + 5 dBm ± 1 dB. When driving a 600 ohm load
the TXA output requires a 600 ohm series resistor to provide
- 1 dBm ± 1 dB to the load.
Baud
bps
Baud
bps
300 Baud
300 bps
TRANSMIT TIMING
DATA ENCODING
In the transmit state, the R48PCJ provides a Data Clock (DCLK)
output with the following characteristics:
1. Frequency: Selected data rate of 4800, 2400 or 300 Hz
At 1600 baud, the 4800 bps data stream is encoded into tribits
per CCITT V.27.
(±O.OI%).
2. Duty Cycle: 50% ± 1%.
Transmit Data (TXD) must be stable during the 1 microsecond
periods immediately preceding and following the rising edge of
DCLK.
At 1200 baud, the 2400 bps data stream is encoded into dibits
per CCITT V.27 ter.
At 300 baud, the data stream is 300 bps FSK per CCITT V.21
channel 2.
COMPROMISE CABLE EQUALIZERS
TURN-ON SEQUENCE
In addition to the adaptive equalizer, the R48PCJ provides selectable compromise cable equalizers to optimize performance over
three different lengths of non-loaded cable of 0.4 mm diameter
(1.8 km, 3.6 km, and 7.2 km).
Eleven turn-on sequences are generated by the R48PCJ, as
defined in the following table:
Turn-On Sequences
No.
Bit
Rate
(bps)
RTSOnCTSOn
Tlme 1
(ms)
Comments
1
300
<14
No Training Sequence, No Echo Tone
Cable Equalizer Nominal Gain
Frequency
(Hz)
700
1500
2000
3000
Gain (dB) Relative to 1700 Hz
1.8 km
-0.99
-0.20
+0.15
+ 1.43
3.6 km
-2.39
-0.65
+0.87
+3.06
7.2 km
-3.93
-1.22
+1.90
+4.58
2
2400
66
3
2400
271
Short Train, with Echo Tone2
TRANSMITTED DATA SPECTRUM
4
2400
943
Long Train, No Echo Tone
When operating at 1600 baud, the transmitter spectrum is
shaped by a square root of 50% raised cosine filter.
5
2400
1148
Long Train, with Echo Tone 2
6
2400
<10
Training Disabled
When operating at 1200 baud, the transmitter spectrum is
shaped by a square root of 90% raised cosine filter.
7
4800
50
8
4800
255
Short Train, with Echo Tone2
9
4800
708
Long Train, No Echo Tone
10
4800
913
Long Train, with Echo Tone 2
11
4800
<10
Training Disabled
The out-of-band transmitter power limitations meet those specified by Part 68 of the FCC's Rules, and typically meet the
requirements of foreign telephone regulatory agencies.
SCRAMBLER/DESCRAMBLER
Short Train, No Echo Tone
Short Train, No Echo Tone
Notes:
1. Assumes the receiver is in idle; if not, add receiver turn-off time.
2. For use on lines with protection against talker echo.
The R48PCJ incorporates a self-synchronizing scrambler/
descrambler. This facility is in accordance with CCITT V.27 ter. The
scrambler can be disabled by setting a bit in interface memory.
3-52
R48PCJ
4800 bps PC Communication Modem
TURN-OFF SEQUENCE
< 10 ms (300 bps). The RLSO on-to-oft response time is
10 ± 5 ms. Response times are measured with a signal at least
3 dB above the actual RLSO on threshold or at least 5 dB below
the actual RLSO off threshold.
Five turn-off sequences are generated by the R48PCJ:
Turn-Off Sequences
No.
Bit Rate (bps)
1
2
3
4
5
300
2400
2400
4800
4800
RTS Off-Energy Off
Time (ms)
Silence
Time (ms)
The RLSO on-to-oft response time ensures that all valid data
bits have appeared on RXO.
<7
7.5
75-10
54
5.4-6.7
0
20
20
20
20
Receiver threshold IS programmable over the range 0 dBm to
- 50 dBm, however, performance may be at a reduced level
when the received signal is less than -43 dBm.
serial
parallel
senal
parallel
A minimum hysteresis action of 2 dB exists between the actual
off-to-on and on-to-oft transition levels. The threshold levels and
hysteresis action are measured with an unmodulated 2100 Hz
tone applied to RXA.
CLAMPING
The following clamps are provided with the R48PCJ:
1. Received Data (RXD). RXO is clamped to a constant mark
(1) whenever RLSO is oft.
2. Received Line Signal Detector (RLSD). RLSO is clamped off
(squelched) whenever RTS is on.
POWER
VoltagelTolerancelCurrent (Max) @ 25°CICurrent (Max) @ 60°C
+5 Vdcl
-5 Vdc
RESPONSE TIMES OF CLEAR-TO-SEND (CTS)
The time between the on-to-ofl transition of RTS and the on-tooft transition of CTS in the data state is a maximum of 2 baud
times for all configurations.
Parameter
Temperature
Operating
Storage
RLSO turns on at the end of the training sequence. If training
is not detected at the receiver, the RLSO oft-to-on response time
is 801 bauds (V.27 long train), 481 bauds (V.27 short train), or
-
CTS
I
h
I
I
I
I
I
TXD
L
DCLK
L
Relative Humidity
USRT
(OPTIONAL)
O°C to +60°C (32°F to 140°F)
- 55°C to + 150°C (- 67°F to + 302°F)
(Stored In sUitable antistatic container).
Up to 90% noncondenslng, or a wet bulb
temperature up to 35°C, whichever IS less
AUXI
I
RLSD
k
r-'
XTLO
,..,
RXD
XTLI
o
CLOCK
- , - CRYSTAL
J
TXOUT
RXIN
READ
WRITE
DATA BUS (8)
ADDRESS BUS (4)
(n
(
S~ecification
CABLE1
R48PCJ
MODEM
HOST
PROCESSOR
(DTE)
5.0 Vdc
25 mA @ -5.0 Vdc
CABLE2
,....
"V
I'"'
-U
I 245 mA @
RTS
I
I
5.0 Vdc
25 mA @ -5.0 Vdc
ENVIRONMENTAL
RECEIVED LINE SIGNAL DETECTOR (RLSD)
---
I 270 mA @
Note: All voltages must have ripple ",0.1 volts peak-to-peak. If
a sWitching supply IS chosen, user may select any frequency
between 20 kHz and 150 kHz so long as no component of the
switching frequency is present outside of the power supply With
an amplitude greater than 500 microvolts peak.
The time between the off-to-on transition of RTS and the off-toon transition of CTS is dictated by the bit rate, the length of the
training sequence, and the presence of the echo tone. The TurnOn Sequences table on page 2 lists the CTS response times.
r
±5%
±5%
h
DECODER 1
CS
+5V
_
POR
IRQ
+s-vvv-l
~
-5V
GND
R48PCJ Functional Interconnect Diagram
3-53
-
- } TELEPHONE
LINE
LINE
INTERFACE
R48PCJ
4800 bps PC Communication Modem
INTERFACE CHARACTERISTICS
gates, the interface can be made compatible with a wide variety
of microprocessors such as 6500, 6800, or 68000.
The modem interface comprises both hardware and software
circuits. Hardware circuits are assigned to specific pins on the
64-pin QUIP. Software circuits are assigned to specific bits in
a 16-byte interface memory.
•
The microprocessor interface allows a host microprocessor to
change modem configuration, read or write channel data as well
as diagnostic data, and supervise modem operation by means
of software strappable control bits and modem status bits. The
significance of the control and status bits and methods of data
interchange are discussed in the Software Circuits section.
HARDWARE CIRCUITS
Signal names and descriptions of the hardware circuits, including
the microprocessor interface, are listed in the R48PCJ Hardware
Circuits table; the table column titled 'Type' refers to designations found in the Digital and Analog Interface Characteristics
tables.
V.24 Interface
Seven hardware circuits provide timing, data and control signals
for implementing a serial interface compatible with CCITT
Recommendation V.24. These signals interface directly with circuits using TTL logic levels (0, +5 volt). These TTL levels are
suitable for driving the short wire lengths or printed circuitry
normally found within stand-alone modem enclosures or equipment cabinets.
Microprocessor Interface
Sixteen hardware circuits provide address (RSO-RS3), data
(00-07), control (CS, READ and WRITE) and interrupt (IRQ)
signals for implementing a parallel interface compatible with an
8080 microprocessor. (Refer to the Microprocessor Interface
Timing Waveforms figure and Microprocessor Interface Timing
Requirements table.) With the addition of a few external logic
In applications where the modem is operated in parallel data
mode only (Le., where the V.24 signals are unused), all V.24
pins may remain unterminated.
R48PCJ Hardware Circuits
Name
Type
Pin No.
Description
Name
AGND
DGND1
DGND2
DGND3
DGND4
DGND5
+5 VA
+5 VD
-5 VA
GND
GND
GND
GND
GND
GND
PWR
PWR
PWR
24
22
48
8
29
4
31
11
25
Connect
Connect
Connect
Connect
Connect
Connect
Connect
Connect
Connect
to
to
to
to
to
to
to
to
to
Analog Ground
AGND Ground
Digital Ground
Digital Ground
Digital Ground
DigItal Ground
Analog ~ 5V Power
Digital + 5V Power
Analog - 5V Power
B. MICROPROCESSOR INTERFACE:
D7
D6
D5
D4
D3
D2
01
DO
IIOA
IIOA
IIOA
IIOA
IIOA
IIOA
IIOA
IIOA
RS3
RS2
RSI
RSO
IA
IA
IA
IA
CS
READ
WRITE
IRQ
IA
IA
IA
OB
~}
50
51
52
53
54
55
56
Data Bus (8 Bits)
61 }
62
63
64
RegIster Select (4 BIts)
Select Reg. 0 - F
59
58
57
ChIp Select
Read Strobe
Write Strobe
Interrupt Request
19
46
17
13
12
18
Data Clock
Request-to-Send
Clear-te-Send
Transmitter Data Signal
ReceIver Data SIgnal
ReceIved Line Signal Detector
32
33
Cable Select 1
Cable Select 2
60
C. V.24 INTERFACE:
DClK
RfS
CTS
TXD
RXD
RlSD
OC
IB
OC
IB
OC
OC
IC
IC
AA
TXOUT
RXIN
AUXI
Pin No.
Description
AB
AC
28
37
26
Connect to Output Op Amp
Connect to Input Op Amp
Auxiliary Analog Input
43
3
10
Power-On-Reset Output
Power-On-Reset Input
Connect to Crystal Circuit
Connect to Crystal Circuit
Receive Mode Output
Connect to RCVO
Connect to RCVO
Switched CapacItor Clock Output
Connect to SClKO
Connect to SClKO
Smoothing Filter Output
AGC Input
DAC/AGC Data Out
Connect to DAOUT
ADC Output
Connect to ADOUT
Smoothing Filter Output
Connect to FOUT
Sample Clock Output
Connect to SYNCOUT
Connect to SYNCOUT
Connect to SYNCOUT
RC JunctIon for POR TIme
Constant
F.OVERHEAD
PORO
PORI
XTlO
XTU
RCVO
RCVI1
RCVI2
SClKO
SClKIN1
SCLKIN2
AOUT
AGCIN
DAOUT
DAIN
ADOUT
ADIN
FOUT
FIN
SYNCOUT
SYNCIN1
SYNCIN2
SYNCIN3
RCI
IIOB
IIOB
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
9
47
34
16
44
30
38
36
23
14
40
39
15
27
35
20
41
5
1
42
G.RESERVED
R*
R*
R*
R*
R*
D. CABLE EQUALIZER:
CABlE1
CABlE2
Type
E_ ANALOG SIGNALS:
A. POWER:
2
6
7
21
45
Do
Do
Do
Do
Do
Not
Not
Not
Not
Not
Connect
Connect
Connect
Connect
Connect
*R = ReqUired overhead connectIon; no connection to host equIpment
3-54
R48PCJ
4800 bps PC Communication Modem
Digital Interface Characteristics
Type
Input
Symbol
Parameter
Output
Units
IA
18
IC
VIH
Input Voltage, High
V
2.0 min.
2.0 min.
2.0 min
VIL
VOH
VOL
liN
10H
10L
IL
Ipu
Input Voltage, Low
Output Voltage, High
Output Voltage, Low
Input Current, Leakage
Output Current, High
Output Current, Low
Output Current, Leakage
Pull-up Current
(Short Circuit)
Capacitive Load
Capacitive Drive
Circuit Type
V
V
V
0.8 max
0.8 max.
0.8 max.
~A
:1:2.5 max.
CL
Co
2.4 min.1
0.4 max. 2
-0.1 max.
1.6 max.
mA
rnA
~
~
pF
pF
5
-240 max.
-10 min.
5
-240 max.
-10 min.
20
TTL
wlPull-up
TTL
w/Pull-up
TTL
Input/Output
08
OA
0.4
max.2
1.6 max.
:1:10 max.
OC
0.4
max. 2
IIOA
1/08
2.0 min.
5.25 max.
2.0 min.
0.8 max.
2.4 mln.3
04 max. 5
0.8 max.
2.4 min. 1
0.4 max. 2
:1:12.5 max.
1.6 max.
-260 max.
-100 min.
10
40
100
100
100
100
Open-Drain
Open-Drain Open Drain
3 State
w/Pull-up Transceiver w/Pull-up
-240 max.
-10 min.
100
TTL
3. I load = -40 ~
4. VIN = 0.4 to 2.4 Vdc, Vee = 5.25 Vdc
5. I load = 0.36 mA
Notes
1. I load = -100~A
2. I load = 1.6 rnA
Analog Interface Characteristics
Analog Interface Characteristics
Name
Type
Characteristics
TXOUT
AA
The transmitter output can supply a
maximum of :I: 3.03 vo~s Into a load
resistance of 10k 0 minimum. In order to
match to 600 0, an external smoothing
filter with a transfer function of
15726.431(S + 11542.44) and 604 0 series
resistor are required.
RXIN
AB
The receiver input impedance is greater
than 1M 0. An external antialiasing filter
with a transfer function of
19533.88/(S+11542.44) is required.
AUXI
AC
The auxiliary analog input allows access
to the transmitter for the purpose of
interlacing with user provided equipment.
Because this is a sampled data input,
any Signal above 4800 Hz will cause
aliasing errors. The input Impedance is
1M D, and the gain to transmitter output
(TXA) is + 5.6 dB :I: 1 dB.
WRITE
READ
Note: Absolute maximum voltage ratings for analog inputs are:
(-5VA - 0.3):s VIN:s (+5VA + 0.3)
Microprocessor Interface Timing Requirements
Characteristic
CS, RSI setup time prior
to READ or WRITE
Data Access time after READ
Data hold time after READ
CS, RSi hold time after
READ or WRITE
Write data setup time
Write data hold time
WRITE strobe pulse Width
Symbol
Min
Max
TCS
30
-
TDA
TDH
10
140
50
TCH
TWOS
TWDH
TWR
10
75
10
75
-
-
-
01
(I = 0-7)
Units
ns
ns
ns
ns
ns
ns
ns
Microprocessor Interface Timing Waveforms
3-55
R48PCJ
4800 bps PC Communication Modem
Cable Equalizers
When information in these registers is being discussed, the format Z:O is used. The register is specified by Z(O-F), and the bit
by 0(0-7, 0 LSB). A bit is considered to be "on" when set to
a one (1) and "off" when reset to a zero (0).
Modems may be connected by direct wiring, such as leased
telephone cabl~ or through the public switched telephone network, by means of a data access arrangement. In either case,
the modem analog signal is carried by copper wire cabling for
at least some part of its route. The cable characteristics shape
the passband response so that the lower frequencies of the passband (300 Hz to 1700 Hz) are attenuated less than the higher
frequencies (1700 .Hz to 3300 Hz). The longer the cable the more
pronounced the effect.
=
Status/Control Bits
The operation of the R48PCJ is affected by a number of software control inputs. These inputs are written into registers within
the interface memory via the host microprocessor bus. Modem
operation is monitored by various software flags that are read
from interface memory via the host microprocessor bus.
To minimize the impact of this undesired passband shaping, a
compromise equalizer with more attenuation at lower frequencies than at higher frequencies can be placed in series with the
analog signal. The modem includes three such equalizers
designed to compensate for cable distortion.
All status and control bits are defined in the R48PCJ Interface
Memory Map table. Bits designated by , - ' are reserved for
modem use only and must not be changed by the host.
Cable Equalizer Selection
CABLE2
CABLE1
Length of O.4mm Diameter cable
0
0
1
1
0
1
0
1
0.0
1.S km
3.S km
7.2 km
Anyone of the registers may be read or written on any host read
or write cycle, but all eight bits of that register are affected. In
order to read a single bit or a group of bits in a register, the host
processor must mask out unwanted data. When writing a single
bit or group of bits in a register the host processor must perform
a read-modify-write operation. That is, the entire register is read,
the necessary bits are set or reset in the accumulator of the host,
then the original unmodified bits and the modified bits are written
back into the register of the interface memory.
Analog Signals
Three analog signals provide the interface point for telephone
company audio circuits and host audio inputs. Signals TXOUT
and RXIN require buffering and filtering to be suitable for driving
and receiving the communication channel. Signal AUXI provides
access to the transmitter for summing host audio signals with
the modem analog output.
Configuration Control
Six configurations are available in the R48PCJ modem: V.27
4800/2400 bps long/short train (foUr variations), V.21, and Tone.
The configuration is selected by writing an 8-bit binary code into
the configuration field (CONF) ofthe interface memory. The configuration field consists of bits 7 through 0 of register D. The
code for these bits is shown in the follOwing table. All other codes
represent invalid states.
The filters required for anti-aliasing on the receiver input and
smoothing on the transmitter output have a single pole located
at 11,542 radians. Although this pole is located within the modem
passband, internal filters compensate for its presence and,
therefore, the pole location must not be changed. Some variation from recommended resistor and capacitor values is permitted as long as the pole is not moved, overall gain is preserved,
and the device is not required to drive a load of less than 10k o.
Configuration Codes
CONF Code
00
Notice that when reference is made to signals TXA, RXA, and
AUXIN, these signals are not electrically identical to TXOUT,
RXIN, and AUXI. The schematic of the recommended modem
interface circuit illustrates the differences.
04
05
OS'
07
OS
Overhead
Configuration
V.21
V.27,
V.27,
V.27,
V.27,
Tone
2400 Long Train
2400 Short Train
4800 Long Train
4800 Short Train
Mode
, Default value at POR.
Except for the power-on-reset signal PORO, the overhead
Signals are intended for internal use only. The various required
connections are illustrated in the recommended modem interface circuit schematic. No host connections should be made to
overhead signals other than PORO.
When the modem is initialized by power-on-reset, the configuration defaults to V.27 4800 bps long train. When the host wants
to change configuration, the new code is written to the configuration field and the SETUP bit (E:3) is set to a one. Once the new
configuration takes effect, the SETUP bit is reset to zero by the
modem.
SOFTWARE CIRCUITS
The R48PCJ contains 16 memory mapped registers to which an
external (host) microprocessor has access. The host may read
data out of or write data into these registers. Refer to the R48PCJ
Host Processor Interface figure.
The information in the interface memory is serviced by the
modem at the baud rate (V.27 and V.21), 9600 times per second
(tone generator), or 1600 times per second (tone detector).
3-56
4800 bps PC Communication Modem
R48PCJ
READ
WRITE
..
:--
READ
WRITE
LOGIC
.A
8
~·r
A
~8
00-07
RSO_RS3
··
REGISTER
SELECT
LOGIC
4L
I
SP
REGISTER F _ 1/0
REGISTER E _ BUS
·· ··
REGISTER 1
REGISTER 0
~
I~
--
INTERRUPT
LOGIC
k==J
SP
MAIN
BUS
~
RAM
I
!
I
h......
IRQ
LOGIC
UNIT
L---....
INTERFACE MEMORY
R48PCJ Host Processor Interface
R48PCJ Interface Memory Map
~
7
5
6
4
3
2
SETUP
ODIE
1
To enable the transmitter parallel mode, TPDM must be set to
a 1. The modem automatically defaults to the serial mode
(TPDM = 0) at power-on. In either transmitter serial or parallel
mode, the R48PCJ is configured by the host processor via the
microprocessor bus.
0
Register
F
Serial Mode-The serial mode uses a standard V.24 (RS-232-C)
hardware interface (optional USRT) to transfer channel data.
Transmitter data can be sent serially only when TPDM IS set to
a zero.
RAMA
IA
E
COlE COREQ
-
0
-
OOREQ
CONF
C
RTSP
B
AX
A
TOET
9
-
8
7
6
EPT
TPDM
FED
-
TOIS
GHIT
CDET
-
-
EOSV EOFZ
PN
-
5
4
RXCD
3
DDXM
2
DDXL
1
DDYM
0
DDYL
-
SDIS RAMW
-
Parallel Mode-Parallel data is transferred via two registers in
the interface memory. Register 5 (RXCD) is used for receiver
channel data, and Register 4 (TXCD) is used for transmitter channel data. Register 5 is continuously written every eight bit times
when in the receive state. Register 4 is used as the source of
channel transmitter data only when bit C:5 (TPDM) is set to a one
by the host. Otherwise the transmitter reads data from the V.24
interface. Both RTS and RTSP remain enabled, however, regardless of the state of TPDM.
-
TXCD
I~
7
6
5
4
3
2
1
When performing parallel data transfer of channel data, the host
and modem can synchronize their operations by handshaking bits
in register E. Bit E:5 (CDREQ) is the channel data request bit.
This bit is set to a one by the modem when receiver data is
available in RXCD or when transmitter data is required in TXCD.
Once the host has finished reading RXCD or writing TXCD, the
host processor must reset CDREQ by writing a zero to that bit
location.
0
Bit
When set to a one by the host, Bit E:6 (CDIE) enables the CDREQ
bit to cause an IRQ interrupt when set. While the IRQ line is
driven to a TIL low level by the modem, bit E:7 (IA) IS a one.
Channel Data Transfer
Data sent to or received from the data channel may be transferred
between the modem and host processor in either serial or parallel
form. The receiver operates in both serial and parallel mode
simultaneously and requires no mode control bit selection. The
transmitter operates in either serial or parallel mode as selected
by mode control bit C:5 (TPDM).
If the host does not respond to the channel data request within
eight bit times, the RXCD register is over written or the TXCD
register is sent again.
Refer to Channel Data Parallel Mode Control flow chart for recommended software sequence.
3-57
a
4800 bps PC Communication Modem
R48PCJ
R48PCJ Interface Memory Definitions
Mnemonic
Name
Memory
location
Description
CDET
Carrier Detector
8:5
The one state of CDET indicates passband energy is being detected, and a training sequence is
not present. CDET goes to one at the start of the data state, and returns to zero at the end of the
received signal. CDET activates one baud time before RLSD and deactivates one baud time after
RLSD.
COlE
Channel Data
Interrupt Enable
E:S
When set to a one, COlE enables an IRQ interrupt to be generated when the channel data
request bit (CDREQ) is a one.
CDREQ
Channel Data
Request
E:5
Parallel data mode handshaking bit. Set to a one when the modem receiver writes data to RXCD,
or the modem transmitter reads data from TXCD. CDREQ must be reset to zero by the host
processor when data service is complete.
CONF
Configuration
0:0-7
The 8-bit field CONF controls the configuration of the modem according to the following table:
Hex Code
00
04
05
OS
07
08
All else
Configuration
V.21
V.27, 2400 Long Train
V.27, 2400 Short Train
V.27, 4800 Long Train (Default)
V.27, 4800 Short Train
Tone
Invalid
Configuration Definitions
1I.21-The modem operates as a CCITT T.30 compatible 300 bps FSK modem having
characteristics of the CCITI V.21 Channel 2 modulation system.
Tone-The modem sends single or dual frequency tones in response to the RTS or RTSP signals.
Tone frequencies and amplitudes are controlled by RAM locations written by the host. When not
transmitting tones the Tone configuration allows detection of single frequency tones by the TDET
bit. The tone detector frequency can be changed by the host by altering the contents of several
RAM locations.
V.27- The modem is compatible with CCITI Recommendation V.27 ter.
ODIE
Diagnostic Data
Interrupt Enable
E:2
When set to a one, ODIE enables an IRQ interrupt to be generated when the diagnostic data
request bit (DDREQ) is a one.
DDREQ
Diagnostic Data
Request
E:O
DDREQ goes to a one when the modem reads from or writes to DDYL. DDREQ goes to a zero
when the host processor reads from or writes to DDYL. Used for diagnostic data handshaking bit.
DDXL
Diagnostic Data
X Least
2:0-7
Least significant byte of IS-bit word used in reading XRAM locations.
DDXM
Diagnostic Data
X Most
3:0-7
Least significant byte of IS-bit word used in reading XRAM locations.
DDYL
Diagnostic Data
Y Least
0:0-7
Least significant byte of 16-bIt word used in reading YRAM locations or writing XRAM and YRAM
locations.
DDYM
Diagnostic Data
Y Most
1:0-7
Most significant byte of IS-bit word used in reading YRAM locations or writing XRAM and YRAM
locations.
EPT
Echo Protector
Tone
C:S
When EPT is a one, an unmodulated carrier is transmitted for 185 ms followed by 20 ms of no
transmitted energy at the beginning of the training sequence. EPT is not active if TDIS is on.
EQFZ
Equalizer Freeze
C:2
When EQFZ is a one, the adaptive equalizer taps stop updating and remain frozen.
EQSV
Equalizer Save
C:3
When EQSV is a one, the adaptive equalizer taps are not zeroed when reconfiguring the modem
or when entering the training state. Adaptive equalizer taps are also not updated during training.
FED
Fast Energy
Detector
8:5,S
FED consists of a 2-bit field that indicates the level of received signal according to the following
code.
Code
o
1
2
3
Energy Level
None
Invalid
Above Turn-off Threshold
Above Turn-on Threshold
While receiving a signal, FED normally alternates between Codes 2 and 3.
3-58
R48PCJ
4800 bps PC Communication Modem
R48PCJ Interace Memory Definitions (continued)
Name
Mnemonic
Memory
Location
Description
GHIT
Gain Hit
B'4
The gain hit bit goes to one when the receiver detects a sudden increase In passband energy
faster than the AGC CircUit can correct GHIT returns to zero when the AGC output returns to
normal
IA
Interrupt Active
E7
IA IS a one when the modem IS dnvlng the Interrupt request line (IRQ) to a low TTL level.
PN
Penod N
8:3
PN sets to a one at the start of the received PN sequence PN resets to zero at the start of the
received scrambled ones PN does not operate when TOiS IS set to a one.
RAMA
RAM Access
F'0-7
The RAMA register IS written by the host when reading or writing diagnostic data The RAMA
code determines the RAM location with which the diagnostic read or write IS performed.
RAMW
RAM Write
CoO
RAMW is set to a one by the host processor when performing diagnostic writes to the modem
RAM. RAMW is set to a zero by the host when reading RAM diagnostic data.
RTSP
Request to Send
Parallel
C:7
The one state of RTSP begins a transmit sequence. The modem continues to transmit until RTSP
IS turned off and the turn-off sequence has been completed. RTSP parallels the operation of the
hardware RTS control input. These inputs are ORed by the modem.
RXCD
Receiver Channel
Oata
5:0-7
RXCD IS written to by the modem every eight bit times. This byte of c~annel data can be read by
the host when the receiver sets the channel data request bit (COREQ)
RX
Receive State
B:7
RX IS a one when the modem IS in the receive state (I.e., not transmitting).
SOlS
Scrambler Disable
C:l
When SOlS IS a one, the scrambler/descrambler is disabled When SOlS IS a zero, the
scrambler/descrambler is enabled (default).
SETUP
Setup
E:3
The host processor must set the SETUP bit to a one when reconfiguring the modem, I.e., when
changing CONF (0:0-7).
TOET
Tone Detected
A:7
The one state of TDET indicates reception of a tone. The filter can be retuned by means of the
diagnostic write routine.
TOIS
Training Disable
C:4
If TDIS is a one in the receive state, the modem is prevented from entering the training phase If
TOIS is a one when RTS or RTSP go active, the generation of a training sequence is prevented at
the start of transmission.
TPDM
Transmitter Parallel
Oata Mode
C:S
When control bit TPOM IS a one, the transmitter accepts data for transmission from the TXCD
register rather than the senal hardware data input.
TXCO
Transmitter
Channel Data
4:0-7
The host processor conveys output data to the transmitter In parallel data mode by Writing a data
byte to the TXCD register when the channel data request bit (COREQ) goes to a one. Oata is
transmitted as Single bits In V.21 or as dibits In V.27 starting wrth bit 0 or diblt 0,1
Diagnostic Data Transfer
These bits are written into interface memory registers 3, 2, 1
and 0 in that order. Registers 3 and 2 contain the most and least
significant bytes of XRAM data, respectively, while registers 1
and 0 contain the most and least significant bytes of YRAM data
respectively.
The modem contains 128 words of random access memory
(RAM). Each word is 32-bits wide. Because the modem is
optimized for performing complex arithmetic, the RAM words
are frequently used for storing complex numbers. Therefore,
each word is organized into a real part (16 bits) and an imaginary
part (l6-bits) that can be accessed independently. The portion
of the word that normally holds the real value is referred to as
XRAM. The portion that normally holds the imaginary value is
referred to as YRAM. The entire contents of XRAM and YRAM
may be read by the host processor via the microprocessor
interface.
When set to a one, bit CoO (RAMW) causes the modem to suspend transfer of RAM data to the interface memory, and insteaa,
to transfer data from interface memory to RAM. When writing
into the RAM, only 16 bits are transferred, not 32 bits as for a
read operation. The 16 bits written in XRAM or YRAM come from
registers 1 and 0, with register 1 being the more significant byte.
Selection of XRAM or YRAM for the destination IS by means of
the code stored in the RAMA bits of register F. When bit F:7
is set to one, the XRAM is selected. When F:7 equals zero,
YRP-flil is selected.
The interface memory acts as an intermediary during these host
to signal processor RAM data exchanges. The RAM address to
be read from or written to is determined by the contents of
register F (RAMA). The R48PCJ RAM Access Codes table lists
27 access codes for storage in register F and the corresponding
diagnostic functions. The R48PCJ Diagnostic Data Scaling table
provides scaling information for these diagnostic functions. Each
RAM word transferred to the interface memory is 32 bits long.
When the host processor reads or writes register 0, the
diagnostic data request bit E:O (DDREQ) IS reset to zero. When
the modem reads or writes register 0, DDREQ is set to a one.
When set to a one by the host, bit E:2 (ODIE) enables the DDREQ
bit to cause an IRQ interrupt when set. While the IRQ line is
driven to a TTL low level by the modem, bit E:7 (IA) goes to a one.
3-59
R48PCJ
4800 bps PC Communication Modem
l-TPDM
l-RTSP
OR
O-RTS
O-CDREQ
N
N
DATA -
TXCD
O-CDREQ
READ RXCD
N
N
N
0 - RTSP
AND
1 -
RTS
Channel Data Parallel Mode Control
3-60
R48PCJ
4800 bps PC Communication Modem
R48PCJ Diagnostic Data Scaling (Cont'd)
R48PCJ RAM Access Codes
Node
Function
RAMA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
AGC Gain Word
Average Power
Receiver Sensitivity
Receiver Hysteresis
Equalizer Input
Equalizer Tap Coefficients
Unrotated Equalizer Output
Rotated Equalizer Oulput
Decision Points
Error Vector
Rotallon Angle
Frequency Correction
EQM
Alpha (a)
Beta One (13,)
Beta Two (/3,,)
Alpha Prime (a')
Bela One Prime (13{)
Beta Two Prime (13:[)
Alpha Double Prime (a")
Beta Double Prime (13")
Output Level
Tone 1 Frequency
Tone 1 Level
Tone 2 Frequency
Tone 2 Level
Checksum
f!7
91
47
84
63
23-32
73
OA
74
75
B3
8B
89
38
39
3A
3B
3C
3D
B8
B9
43
8E
44
8F
45
02
Reg. No.
2,3
2,3
Node
Parameter/Scaling
5,7-9
All base-band signal point nodes (I.e., Equalizer Input,
Unrotated Equalizer Output, Rotated Equalizer Output, and
Decision Points) are 32-bit, complex, twos complement
numbers.
0,1
2,3
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
2,3
2,3
2,3
0,1
0,1
0,1
0,1
0,1
0,1
2,3
2,3
0,1
2,3
0,1
2,3
0,1
0,1
Value (Hex)
X
Y
1
2
3
4
1D00
OCOO
F400
E300
E300
F400
OCOO
1D00
OCOO
1D00
1D00
OCOO
F400
E300
E300
F400
5
6
7
8
6
y
Point
e3
e2
e4
e1
e5
e8
X
e6
e7
Equalizer Tap Coefficients (32-blt, complex, twos
complement)
= real part, Y = imaginary part
X and Y range: 0000 to (FFFF),6 representing ± full scale
Complex numbers with X
in hexadecimal twos complement.
10
Error Vector (32-bit, complex, twos complement)
Complex number with X = real part,
Y = imaginary part.
X and Y range: (8000),6 to (7FFF),6
11
Rotation Angle (16-bit, signed, twos complement)
12
Frequency Correction (16-bil signed twos complement)
Rotation Angle in deg.
= (Rot.
Angle Word/65,536) x 360
Frequency correction in Hz
= (Freq. Correction Word/65,536) x Baud Rate
Range: (FCOO)'6 to (400),6 representing ± 1&75 Hz
R48PCJ Diagnostic Data Scaling
Parameter/Scaling
Node
1
13
EQM (16-bit, unsigned)
Filtered squared magnitude of error vector.
Proportionality to BER determined by particular applicallon.
14-21
Filter Tuning Parameters (16-bit unsigned) Alpha, Beta One,
Beta Two, Alpha Prime, Beta One Prime, Beta Two Pnme,
Alpha Double Prime, and Beta Double Prime are set according
to instructions in application note 668.
22
Output Level (16-bIt unsigned)
Output Number = 27573.6 [10(Po/20) 1
AGC Gain Word (16-bit unsigned),
AGC Gain in dB
= 50
- [(AGC Gain Word/64) x 0.098]
Range: (16CO),s to (7FFF)'6' For -43 dBm Threshold
2.
3
Average Power (16-bit unsigned)
Post-AGC Average Power in dBm
= 10 Log (Average Power Word/2185)
Typical Value = (0889),6, corresponding to 0 dBm
Pre-AGC Power in dBm
= (Post-AGC Average Power-AGC Gain)
Po
power in dBm with series 600 ohm resistor
IOta 600 ohm load.
Convert Output Number to hexadecimal and store at
access code 43
Receiver Sensitivity (16-bit twos complement)
On-Number
where: PaN
= 655.36 (52.38 + PaN)
=Turn-on threshold in dB
Convert On-Number to hexadecimal and store at access
code 47
4
24
and
26
Tone 1 and Tone 2 Levels
Calculate the power of each tone independently by using
the equation for Output Number given at node 22. Convert
these numbers to hexadecimal then store at access codes
44 and 45. Total power transmitted in tone mode is the
result of both tone 1 power and tone 2 power.
23
and
25
Tone 1 and 2 Frequency (16-bit unsigned)
N = 6.8267 (Frequency in Hz)
Convert N to hexadecimal then store at access code BE
or 8F.
27
Checksum (16-bit unsigned)
ROM checksum number determined by revision level.
Receiver Hysteresis (16-bit twos complement)
Off-Number
where:
A
PON
POFF
= output
= [65.4 (10A)]2/2
= (POFF - PON - 0.5)/20
= Turn-on threshold in dB
= Turn-off threshold in dB
Convert Off-Number to hexadecimal and store at access
code 84.
3-61
R48PCJ
4800 bps PC Communication Modem
POWER·ON INITIALIZATION
TYPICAL BIT ERROR RATES
When power is applied to the R48PCJ, a period of 50 to 350 ms
is required for power supply settling. The power-on-reset signal
(POR) remains low during this period. Approximately 10 ms after
the low to high transition of POR, the modem is ready to be
configured, and RTS may be activated. If the 5 Vdc power supply
drops below approximately 3 Vdc for more than 30 msec, the
POR cycle is repeated.
The Bit Error Rate (BER) performance of the modem is specified
for a test configuration conforming to that illustrated in CCITT
Recommendation V.56. Bit error rates are measured at a
received line Signal level of -20 dBm.
RECEIVED SIGNAL FREQUENCY TOLERANCE
The receiver circuit of the R48PCJ can adapt to received
frequency error of ± 10 Hz with less than 0.2 dB degradation
in BER performance.
At POR time the modem defaults to the following configuration:
V.27/4800 bps, serial mode, training enabled, echo protector
tone enabled, interrupts disabled, RAM access code OA,
transmitter output level set for + 5 dBm at TXA, receiver turnon threshold set for -43.5 dBm, receiver turn-off threshold set
for -47.0 dBm, tone 1 and tone 2 set for 0 Hz and 0 volts output,
and tone detector parameters zeroed.
TYPICAL PHASE JITTER
At 4800 bps, the modem exhibits a BER of 10-6 or less with a
signal-to-noise ratio of 19 dB in the presence of 15° peak-topeak phase jitter at 60 Hz.
POR can be connected to a user supplied power-on-reset signal
in a wire-or configuration. A low active pulse of 3 !,sec or longer
applied to the POR pin causes the modem to reset. The modem
is ready to be configured 10 msec after the low active pulse is
removed from POR.
PERFORMANCE
At 2400 bps, the modem exhibits a BER of 10-6 or less with a
signal-to-noise ratio of 12.5 dB in the presence of 15° peak-topeak phase jitter at 150 Hz or with a signal-to-noise ratio of 15 dB
in the presence of 30° peak-to-peak phase jitter at 120 Hz
(scrambler inserted).
Whether functioning as a V.27 ter or V.21 type modem, the
R48PCJ provides the user with unexcelled high performance.
An example of the BER performance capabilities is given in the
following diagrams:
I
10 - 3
I
I
\
\
V.27,2400
FSK
V.27,2400 V.27,4800
FSK
I
\
10- 3
10- 4
10- 4
W
.....
W
.....
a:
a:
0
a:
a:
0
I
V.27,4800
I
\
U1
V 2'
SERIAL
INTERFACE
TXA
C5
0' ~F
DAOUT
DAIN
ADOUT
C6
ADIN
RXIN
!:
1000 PF
5%, SOY
FOUT
FIN
0
a.
CD
3
. . . 12 VOLTS
+5 VOLTS
A6
-5'
SYNCOUT
SYNCIN1
SYNCIN2
SVNCIN3
~
~
I»
A9
.,
()
CD
0
~
RXA
MICROPROCESSOR
PARALLEL
INTERFACE
f
II
-12VOlTS
C8
~
~
0)
475K 1%
o
o
C"
"C
10,F
(I)
C
;::;
"'tIl
A11
R48PCJ
L....-----------~---~v..
3 OHM
Cl.
NOTES: UNLESS OTHERWISE SPECIFIED
1. RESISTOR VALUES ARE IN OHMS ±5% 1/4W
2. CAPACITOR VALUES ARE IN MICROFARADS UO% 50V
3. Cl AND C2 NOT USED
+ 10 "F
10%
25'
II
~
C11
027 p.F
+5 VOLTS
o
&>
3
3
c
~
t)'
a0'
~
3:
o
a.
CD
3
II
R48PCJ
4800 bps PC Communication Modem
PACKAGE DIMENSIONS
£-
1:
:020TYP
(.508 MM)
"
I 1~(19':~M)
.925
I
(23.495 MM)
1.628
(41.35 MM)
~i
~
~
<.>'
:3
...~
"'~
_£ij
- £J- -
i:
'i.
i
I ! I 1-.1
~+
"-------.;;;;050 REF
(1.27MM)
TYP
I
,
_,
1__
1.50
(3.81 MM)
64-Pln QUIP
3-66
020REF
TVP
R24/48MEB
Evaluation Board
'1'
Rockwell
R24/48MEB
Modem Evaluation Board
INTRODUCTION
FEATURES
The Rockwell R24/48MEB Modem Evaluation Board (MEB) aids
the original equipment manufacturer (OEM) during the evaluation and design in phases of product development. Modems supported by the R24/48MEB include the R24MFX. R24BKJ.
R48MFX. and R48PCJ. The Modem Evaluation Board contains
a socket (U1) for mounting the 64-pin quad in-line package (QUIP)
of the selected modem. plus support circuitry to configure a complete data pump. For operation over the public switched
telephone network (PSTN). an appropriate line termination. such
as a data access arrangement (DAA). must be provided
externally.
• Convenient evaluation method for
The R24/48MEB physical and electrical interface is compatible
with the Rockwell R96FAX modem. For users of the R96FAX.
this feature provides a rapid means of preparing to evaluate a
64-pin QUIP modem. Equipment previously developed for use
with the R96FAX can be converted for use with the R24/48MEB
by changing only the software.
• Standard 40-pin flat ribbon connector
R24MFX
R24BKJ
R48MFX
R48PCJ
• Exercises all modem functions
• Easily integrated into a prototype system
• Cost effective for low volume production applications
• Backward compatible with R96FAX hardware
• Low power consumption: 1.5W (typical)
• Small size: 100 mm x 65 mm (3.94 in. x 2.56 in.).
R24/48MEB Modem Evaluation Board
Document No. 29200N22
Data Sheet
3-67
Order No. MD22
Rev. 1, January 1987
Modem Evaluation Board
R24/R48MEB
TECHNICAL SPECIFICATION
Table 1.
For a description of the R24/48MEB characteristics with a 64-pin
QUIP modem installed in socket U1, refer to the corresponding
modem data sheet.
Modem
Number
Data Sheet
Order Number
R24MFX
R24BKJ
R48MFX
R48PCJ
MD17
MD20
MD19
MD21
Name
R24/48MEB Connector Interface Signals
Type
Pin No.
GND
PWR
PWR
PWR
1I0B
14,39
3, 4
26
37
36
Description
A. POWER;
Ground
+5 volts
+ 12 volts
-12 volts
POR
Power Supply Return
+ 5. volt supply
+ 12 volt supply
- 12 volt supply
Power-an-reset
B. MICROPROCESSOR INTERFACE:
D7
D6
D5
D4
D3
D2
D1
DO
CIRCUIT DESCRIPTION
INTERFACE CIRCUITS
The circuitry and design rules used to create the R24/48MEB
follow the recommended modem interface and PC board layout
considerations published in the associated 64-pin QUIP modem
data sheet. The circuit card can be used as a guide in host PC
board design.
Refer to the R24/48MEB schematic diagram (Figure 2) dUring
the following description. The modem being evaluated is inserted
in the 64-pin QUIP socket (U1). Various overhead connections
between QUIP pins are completed by circuits on the evaluation
board. Some of these overhead signals are connected to test
points (E3, E4, ES) or connector pins (P1-11, P1-12, P1-22, P1-24)
for use in Rockwell production test. These signals are not
intended for use by the host equipment.
IIOA
1I0A
IIOA
IIOA
IIOA
IIOA
IIOA
IIOA
J}
15
28
23
29
Data Bus (8 Bits)
RS3
RS2
RS1
RSO
IA
IA
IA
IA
27
10
3~ }
Register Select (4 Bits)
CS
READ
WRITE
IRQ
IA
IA
IA
OB
6
1
2
32
Chip Select
Read Enable
Write Enable
Interrupt Request
13
19
17
20
21
16
Data Clock
Request-to-Send
Clear-to-Send
Transmitter Data
Receiver Data
Received Line Signal Detector
C. V.24 INTERFACE:
DCLK
RTS
CTS
TXD
RXD
RLSD
Modem signals that form the user interface on connector P1
(Table 1) are divided into five categories: Power, Microprocessor
Interface, V.24 Interface, Cable Equalizer, and Analog Signals.
The column titled "Type" refers to designations found in the
digital and analog interface characteristics tables (Tables 2
and 3). The five categories are defined in the following
paragraphs.
OC
IB
OC
IB
OC
OC
D. CABLE EQUALIZER:
CABS!
CABS2
IC
IC
33
34
Cable Select 1
Cable Select 2
E. ANALOG SIGNALS:
TXA
RXA
AUXIN
Power
Power signals include ± 12 volts, +S volts, ground and POR. The
± 12 volt supplies provide power for analog circuits and should
be free from switching transients normally associated with digital
circuits. The + S volt source provides power for digital circuits
and can be driven by the host logic supply.
AA
AB
AC
38
40
35
Transmitter Analog Output
Receiver Analog Input
Auxiliary Analog Input
signal ground (pins 14 and 39) by a parallel set of capacitors.
A large value capacitor of 10 microfarads or greater should
be para"eled by a low inductance sma" value capacitor of
0.1 microfarads.
Because the modem uses switched capacitor filters, the noise
floor can be degraded as the result of high frequency noise
aliased into the passband by beating with the switched capacitor
clock. For this reason, use of linear power supplies, rather than
switching power supplies, is recommended where low level
reception (i.e., around - 40 dBm) is anticipated. If switching
power supplies are used, extra care must be taken to keep
switching noise out of the modem. The following techniques have
proven helpful in designing systems using switching supplies.
The common reference point for all signals, both digital and
analog, is modem ground (pins 14 and 39). These pins provide
the power supply return points for all vOltages and should be
used as reference for transmitter and receiver signals. To
minimize noise problems, circuits that interface to the modem
should maintain their ground references as close as possible
to the same potential as modem pins 14 and 39. Digital signals
and analog signals should be referenced to modem ground via
separate connections to prevent digital noise from appearing on
analog signals due to a common ground impedance.
1. In addition to the decoupling capacitors on a" modem power
inputs, the power supply output leads should be wrapped
around a toroidal core to increase series inductance. This
technique blocks the conducted high frequency noise from
the switching supply.
In order to reduce the effect of noise coupled through direct current (DC) power lines, decoupling capacitors are recommended
on all power inputs. Each supply input should be decoupled to
3-68
R24/R48MEB
Modem Evaluation Board
Table 2.
Digital Interface Characteristics
Type
Input
Symbol
Parameter
Output
Units
IA
IB
IC
OA
V,H
Input Voltage, High
V
20 mm.
2.0 mm
20 mm
V'l
VOH
VOL
liN
10H
IOl
Il
Ipu
Input Voltage, Low
Output Voltage, High
Output Voltage, Low
Input Current, Leakage
Output Current, High
Output Current, Low
Output Current, Leakage
Pull·up Current
(Short Circuit)
Capacitive Load
Capacitive Drive
CircUit Type
V
V
V
0.8 max.
0.8 max.
0.8 max.
pA
±2.5 max
Cl
CD
Notes
1. I load = -100 pA
2. I load = I.S rnA
Table 3.
Name
TXA
-0.1 max.
I.S max.
pA
~A
pF
pF
5
TTL
-240 max.
-10 min.
5
-240 max.
-10 min.
20
TTL
w/Pull-up
TTL
w/Pull-up
OC
IIOA
I/OB
2.0 mm.
5.25 max.
20 min.
0.8 max.
2.4 mm. 3
0.4 max 5
,
2.4 min.'
0.4 max. 2
rnA
rnA
InputlOutput
OB
0.4 max. 2
0.4 max. 2
1.6 max.
± 10 max.
I.S max.
0.8 max.
2.4 min.
0.4 max. 2
± 12.5 max'
-240 max.
-10 min.
100
TTL
-2S0 max
-100 min.
10
40
100
100
100
100
Open-Dram Open Drain
3 State
Open·Dram
w/Pull-up Transceiver w/Pull-up
3. I load = -40 pA
4. V,N = 0.4 to 2.4 Vdc, Vcc = 5.25 Vdc
5. I load = 0.3S rnA
Analog Interface Characteristics
Type
Characteristics
AA
The transmitter output is a low impedance
operational amplifier output. In order to
match to SOD ohms, an external S04 ohm
series resistor IS required.
RXA
AB
The receiver mput impedance is
47.5K ohms ± 1%.
AUXIN
AC
The auxiliary analog input allows access
to the transmitter for the purpose of
interfacing with user provided equipment.
Because this IS a sampled data input, any
signal above half the sample rate will
cause aliasing errors. The input
Impedance is lK ohms, and the gain to
transmitter output is - 0.4 dB ± 1 dB.
30 milliseconds, or an external device drives pin 36 low for at
least 3 microseconds.
Microprocessor Interface
Sixteen hardware circuits provide address (RSO-RS3), data
(DO-D7), control (CS, READ and WRITE) and interrupt (IRQ)
signals for implementing a parallel interface compatible with an
8080 microprocessor. The microprocessor interface timing
waveforms are shown in Figure 1 and the microprocessor
interface timing requirements are listed in Table 4. With the
addition of a few external logic gates, the interface can be made
compatible with a wide variety of microprocessors such as 6500,
6800, or 68000.
The microprocessor interface allows a host microprocessor to
change modem configuration, read or write channel data as well
as diagnostic data, and supervise modem operation by means
of software strappable control bits and modem status bits. The
significance of the control and status bits and methods of data
interchange are discussed in the referenced data sheet of each
64-pin QUIP modem.
2. A ground plane should be inserted between the modem and
the power supply. This technique reduces radiated EMI pickup
by modem circuits.
3. Shield analog signals in coaxial wire. Signals TXA (pin 38),
RXA (pin 40), and AUXIN (pin 35) should be shielded. Signal
AUXIN should be tied to ground (pin 39) if not used.
V.24 Interface
Six hardware circuits provide timing, data and control signals
for implementing a serial interface compatible with CCITT
Recommendation V.24. These signals interface directly with
circuits using TTL logic levels. These TTL levels are suitable
for driving the short wire lengths or printed circuitry normally
found within stand-alone modem enclosures or equipment
cabinets.
By following these procedures, satisfactory performance over
the full dynamic range should be realized even when switching
power supplies must be used.
When the modem is initially energized a signal called Power-On
Reset (POR) causes the modem to assume a valid operational state. The modem drives pin 36 to ground during the
beginning of the POR sequence. Approximately 10 milliseconds
after the low to high transition of pin 36, the modem is ready
for normal use. The POR sequence is reinitialized anytime
the + 5 volt supply drops below + 3.0 volts for more than
In applications where the modem is operated in parallel data
mode only (i.e., where the V.24 signals are unused), all V.24 pins
may remain unterminated.
3-69
Ii
B
Modem Evaluation Board
R24/R48MEB
Table 4.
READ
WRITE
Microprocessor Interface Timing Requirements
Symbol
Min
CS, RSi setup time prior
to Read or WRITE
TCS
Data Access time after Read
TDA
Data hold time after Read
TDH
Characteristic
CS, RSi hold time after
READ or WRITE
Max
Units
30
-
NS
-
140
NS
10
50
NS
NS
NS
TCH
10
Write data setup time
TWOS
75
Write data hold time
TWDH
10
-
TWR
75
-
WRITE strobe pulse width
Table 5.
NS
NS
Cable Equalizer Selection
CABLE1
CABLE2
Length of O.4mm Diameter Cable
0
0
1
1
0
1
0
1
0.0
1.8 km
3.6 km
7.2 km
impedance is 47.5K ohms ± 1%. The RXA input must be
shunted by an external resistor in order to match a 600 ohms
source. The 604 ohms ± 1% resistor recommended for the
transmitter is also suitable for the receiver.
Figure 1.
The last analog connection is the input AUXIN. This line provides a means of inserting audio signals into the modem output
stage. Because this input is summed with the transmitter output prior to the transmitter low pass filter and compromise
equalizers, the AUXIN signal is sampled by a compensated
sample-and-hold circuit. Any signal above half the sample rate
on the AUXIN line will be aliased back into the passband as
noise.
Microprocessor Interface Timing Waveforms
Cable Equalizers
Modems may be connected by direct wiring, such as leased
telephone cable or through the public switched telephone network, by means of a data access arrangement. In either case,
the modem analog signal is carried by copper wire cabling for
at least some part of its route. The cable characteristics shape
the passband response so that the lower frequencies of the passband (300 Hz to 1700 Hz) are attenuated less than the higher
frequencies (1700 Hz to 3300 Hz). The longer the cable the more
pronounced the effect.
MEB SUPPORT CIRCUITS
The modem evaluation board with a 64-pin QUIP modem
installed forms a complete data pump ready for interfacing to
a host microprocessor (Figure 3). The host electronics must provide data and timing on the microprocessor interface pins to
allow normal modem configuration and option selection plus
status monitoring. Additional circuitry is recommended to allow
generation of an eye pattern for diagnostic purposes (Figure 6).
A commercially available modem test set (e.g., Phoenix 5000)
can be connected directly to the V.24 serial interface (using TTL
levels) or can be buffered with OS1488 and OS1489 type drivers
and receivers for operation with standard RS-232 levels.
To minimize the impact of this undesired passband shaping, a
compromise equalizer with more attenuation at lower frequencies than at higher frequencies can be placed in series with
the analog signal. The modem includes three such equalizers
designed to compensate for cable distortion. The low (0) and
high (1) states of signals CABSl and CABS2 that are necessary
to select each of the cable equalizer options are defined in
Table 5.
Analog Signals
Schematic diagrams are provided for the RS-232 buffer circuit
(Figure 4) and the microprocessor bus interface with eye pattern output (Figure 5). Note that the data clock signal must drive
both the transmitter clock and the receiver clock and is therefore
buffered to reduce the load on the R24/48MEB pin 13. Also note
that an SN74121 is used to shorten the write pulse in order to
meet data hold time requirements for the NE5018 devices. The
100 ohm resistors in series with modem signals are required
only when driving several feet of cable where excessive ringing
may require damping. The address decode logiC places the
modem registers between locations 9000 and 900F hexadecimal.
The eye pattern OAC's are at locations 9071 and 9072.
Three connector pins are devoted to analog audio signals: TXA,
RXA, and AUXIN. The TXA (transmitter analog) line is an output suitable for driving an audio translormer or data access
arrangement for connection to either leased lines or the public
switched telephone network. The output structure 01 TXA is a
low impedance amplifier. In order to match this output to a
standard telephone load of 600 ohms, a series resistor is
required. A value of 604 ohms ± 1% is recommended.
The RXA (receiver analog) line is an input to the receiver from
an audio transformer or data access arrangement. The input
3-70
:D
N
~
:D
~
(II)
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m
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ca"
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co
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3
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C:;"
C
S"
u::I
iil
3
15
28
23
29
30
8
27
10
1
03
02
01
DO
RS3
RS2
RS1
RSO
READ
~"
04
53 03
54 02
5 01
56 DO
61 RS3
62 RS2
1.0 FF
63 RS1
64 RSO
58 READ
s:::
o
Q.
CD
3
NOTEs! UNLESS OTHERWISE SPECIFIED
1. RESISTOR VALUES ARE IN OHMS ±S% 1J4W
m
2. CAPACITOR VALUES ARE ±20% SOY
Q1
3. C1 AND C2 NOT USED WITH R48MFX
AND R48PCJ.
c
a
o·
::J
OJ
o$I)
a.
----~
.-
::tI
I\)
+5V
~
+5V
::tI
.j::o.
Q)
r~ r~
--
--,
~ DS1489
~REQUIRED
L.. _ _
::u
'"""~
MODEM
TEST
SET
~
~
I\)
TXD
~
CTS
~
RXD
RLSD
~ REQUIRED I
"TI
~
L
~
~IF
s:
m
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C
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,
- -
0"
::I
!!!.
,...
TXA
,..
14- +12V
14- +5V
14- -12V
R24/48MEB
MODEM
EVAWATION
BOARD
'-
,..
'""
--
NE
,RDAA
IF
I REQUIRI
RXA
~
OR
I- _ _
I+- GND
DCLK
~
DO I
!l
,-- -
CABLE2
J
BB 'DS1488
co
CABLE1
m
'-'
- ---I
Cil
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RTS
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-
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III
EYE
PATTERN
GENERATOR
1
:;
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CD
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f.!-.,
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0
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"
SCOPE
CJ {)
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CD
!l
DATA BUS (8)
iii"
READ
c
ce
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3:
o
WRITE
3
Q.
CD
ADDRESS BUS (4)
3
HOST
PROCESSOR
(:::
(L-..
Y
DECODER
~
P
m
CS
~
c
XDAC
YDAC
POR
IRQ
+5V
ao·
::J
III
o
m
a
i,;
R24/R48MEB
Modem Evaluation Board
+12V
.1~F~
14
21
13
J1*
11
Vee
RECEIVER DATA
3
BB
5
CB
8
CF
17
DO
12
10
17
CLEAR TO SEND
8
9
16
RECEIVED LINE
SIGNAL DETECTOR
DS1488
4
6
5
4
DATA CLOCK
2
3
GND
SN74LS04
+12V
+5V
+5V
-12V
+12V
I
I
-12VI
+5V
+12VI
SN74LS04
26
3
I
4
I . 1 ~F
37
-12V
13
11
-=
-=
,
I
15
DB
2
BA
4
CA
12
10
R24/48MEB
MODEM
EVALUATION
BOARD
GND
GND
.1 ~F
8
9
DS1488
4
14
5
39
-=
2
+12V
POWER
SUPPLY
+5V
-12V
20
Vee
11
TRANSMITTER DATA
13
12
8
10
9
19
6
REQUEST TO SEND
DS1489
4
5
3
----I
=*=100pF
2
-1...
-=-
GND
-=
Figure 4.
7
RS-232 Buffer Circuit
3-73
---
--
-
---
--- ---- - -
-
--~----
-
----_.--
*J1 = DB-25S
TYPE CONNECTOR
D
Modem Evaluation Board
R24/R48MEB
~!i!l158S.;;8
1,··,··,,1
~
Figure 5.
.
R24/48MEB Microprocessor Bus Interface with Eye Pattern Output
3-74
Modem Evaluation Board
R24/R48MEB
MODEM EVAWATION
BIT ERROR RATE
EYE PATTERN
Bit Error Rate (BER) is a measure of the steady-state transfer
of data on the communication channel. It is the ratio of the
number of received bits in error to the number of transmitted
bits. This number increases with decreasing signal-to-noise ratio
(SNR). The type of line disturbance and the modem configuration also affect the BER.
The eye pattern is an oscilloscope display of the received baseband constellation. By monitoring this constellation, an observer
can often identify common line disturbances as well as defects
in the modulation/demodulation process.
In quadrature amplitude modulation (QAM), two multilevel amplitude modulated (AM) carriers are transmitted simultaneously.
Interference between these two modulated carriers is minimized
by using carriers of identical frequency with a constant 90°
relative phase angle. After demodulation, the multilevel baseband signals can be displayed on an oscilloscope with the set
of levels received on one carrier displayed on the X axis and
the set of levels received on the other carrier displayed on the
Y axis. Since these signals consist of discrete levels sent at high
data rates, the resulting oscilloscope pattern appears to be a
fixed set of points.
The BER Performance Test Set-up (Figure 8) illustrates a method
of measuring BER in accordance with CCITT Recommendation
V.5S. The band-limited noise level should be adjusted by the
noise attenuator to give the desired signal to noise ratio for the
selected received signal level. The modem transmitter is then
caused to send a 511-bit pseudo random test pattern. The signal
attenuator is set for a received signal level of - 20 dBm to
simulate leased line operation or - 30 dBm to simulate switched
network operation. In leased line testing the line simulator should
be 3002-C1 or 3002-C2 conditioned.
Once the receiver has trained (as indicated by a stable eye pattern) the BER test can begin. A large enough number of bits
should be sent to cause at least 10 bit errors to be recorded.
BER is calculated by dividing the number of bits in error by the
number of bits sent.
Figures Sa through Sd illustrate four examples of an eye pattern. Figure Sa shows the location of four ideal pOints corresponding to a signal structure using 0 and ± 1 for the three
amplitude levels. One such signal structure is CCITT Recommendation V.27 at 2400 bits per second. The dashed lines
superimposed on the eye pattern represent decision boundaries
used by the receiver in deciding which ideal point corresponds
to the actual received point. Although the transmitter sends ideal
points, line impairments cause the received points to be misaligned. Figure Sb shows the effect of random noise. The
received points cluster around the ideal location, but are
randomly offset from the ideal point by the noise causing
undesired signal modulation. The random offsets are a result
of the random nature of the noise. If the line impairment is not
random but periodic or is a function of the received signal itself
(e.g., harmonic distortion) then the distribution of points around
the ideal location is not random. Figure Sc illustrates the tangential smearing resulting from phase jitter and Figure Sd shows
the effect of amplitude distortion (either gain jitter or harmonic
distortion). The magnitude of the spreading is directly proportional to the severity of the impairment, and represents the quality
of the signal or the likelihood of errors in the received data.
The impairment source can be adjusted to provide phase-jitter
or frequency offset, etc. The BER tests can be repeated in the
presence of these line impairments to determine the amount by
which performance has degraded. All BER tests should be conducted under steady-state conditions; i.e., after the adaptive
equalizer has stabilized.
Transient response can be measured by using very short polling
messages and comparing the number of attempts to send a
message with the number of error free messages received for
a specific signal to noise ratio and line condition. This type of
testing is called block-error-rate (BLER) and can be performed
using the same test set-up as bit-arror-rate.
Data throughput for a specific application is determined by a
combination of bit-error-rate and block-error-rate. Depending on
system architecture, line conditions, error control method used,
etc., an optimum message length can be chosen to maximize
throughput. As messages become shorter, block-error-rate
becomes the limiting factor. As messages become longer, biterror-rate becomes the limiting factor.
Consult the Eye Pattern Generation Flowchart (Figure 7) for an
example of eye pattern generation using the address structure
indicated in the eye pattern output schematic.
3-75
Modem Evaluation Board
R24/R48MEB
a) IDEAL EYE PATTERN
b) WHITE NOISE
y
y
,,
x
4 +1
,,
-
,,
/
-
/
,,
,/
/
-1
/
/
/
/
/
/
,,
/
/
• -1
.•..":.:.'..
+1
,,
,
.. I·
.e.":":•
• SMEARING AROUND EACH
IDEAL LOCATION
• DASHED LINES REPRESENT
DECISION BOUNDARIES
c) PHASE JITTER
d) HARMONIC DISTORTION
y
y
:',:
:
•.£; ;
'
.f
/.
x
::
.,
"~
'.
..
......
••:-t.=:."::: •
..if
':."/::.::.'
• CONTINUOUSLY PERIODIC
PHASE SMEARING
• LITTLE OR NO AMPLITUDE
SMEARING
• NON·PERIODIC AMPLITUDE
SMEARING
• LITTLE PHASE EFFECT
• GAIN-JITTER (AM) EFFECT IS
SIMILAR AND IS PERIODIC
"DEGREE OF THE SPREADING OF THE EYE PATTERN IS PROPORTIONAL TO THE SEVERITY OF THE LINE DISTURBANCE
Figure 6.
Four Point Eye Patterns
3-76
R24/R48MEB
Modem Evaluation Board
WRITE ACCESS CODE
FOR ROTATED
EQUALIZER OUTPUT
INTO 900F (RAMAl
o
READ 9000
(DDYLI TO
CLEAR DDREQ
Figure 7. Eye Pattern Generation Flowchart
3-77
Modem Evaluation Board
R24/R48MEB
300-3~00 HZ
NOISE
SOURCE
GR13B1
5 KHZ BW
MODEM
TRANSMITTER
r--
LINE
SIMULATOR
(3002)
r--
-
FILTER
ATTENUATOR
COMSTRON f - - HP350D
FA2B74
IMPAIRMENT
SOURCE
BRADLEY 2A
AND 2B
-
ATTENUATOR
HP 3500
f---
I
E
r--
LEVEL
METER
HP3555B
I-L-
MODEM
RECEIVER
T
I
MODEM
TEST SET
PHOENIX 5000
Figure 8.
BER Performance Test Set-up
3-78
Modem Evaluation Board
R24/R48MEB
GENERAL SPECIFICATIONS
Voltage
Tolerance
Current (Typical) @ 25°C
Current (Max) @ OOC
+5 Vdc
+ 12 Vdc
-12 Vdc
±5%
±50ib
±50ib
200 mA
5 mA
30 mA
<300 mA
<10 mA
<50 mA
Note: All voltages must have ripple ";0.1 volts peak-te-peak
Environmental
Perameter
Specification
Temperature
Operallng
Storage
Relative Humidity
O°C to + 60°C (32°F to 140°F)
-40°C to +BO°C (-40°F to 176·F) (Stored in heat sealed antistatic bag and shipping container)
Up to 90% noncondensing, or a wet bulb temperature up to 35°C, whichever is less.
Mechanical
Specification
Parameter
Single PC board with Single right angle header with 40 pins. Burndy FRS 40BSBP or eqUivalent
mallng connector.
Board Structure
Dimensions
Width
Length
Height
Weight (max.)
Lead Extrusion (max )
3.937 in. (100 mm)
2.559 In. (65 mm)
0.40 in. (10.2 mm)
2.6 oz. (73 g)
0.100 In. (2 54 mm)
0.156 ±0.003 DIA (4 PL)
(3.96)
r
I
-~ ~
i
3.437
I
l~
~~
,
(25.4)
If=:.:..==::t:::==~
I
2.300
I~ (58.4)
2.559
~(65)
0.400
~
=t
I
,
0.277
(7.04)
0.125
(3.18)
COMPONENT AREA
~~~--/----D
t : :'~6;
(1.6)
i
- -- -- - - -- -
~
0.100
J
(2.54)
t
UNITS:
[0.400 MAX
(10.16)
RIBBON CONNECTOR VERSION
R24/48MEB Dimensions and Pin Locations
3-79
IN~~ES
R96PCJ
Integral Modems
'1'
Rockwell
R96PCJ
9600 bps PC Communication Modem
INTRODUCTION
FEATURES
The Rockwell R96PCJ is a synchronous 9600 bits per second
(bps) modem designed for operation over the public switched
telephone network through line terminations provided by a data
access arrangement (DAA).
• Ultimate User Compatibility:
- CCITT V.29, V.27 ter, T.30, V.21 Channel 2, T.4
The modem satisfies the telecommunications requirements
specified in CCITT recommendations V.29, V.27 ter, V.21, T.4
and the binary signaling capabilities of T.30. The R96PCJ can
operate at speeds of 9600, 7200, 4800, 2400 and 300 bps, and
includes the V.27 ter short training sequence option. Employ·
ing advanced signal processing techniques, the R96PCJ can
transmit and receive data even under extremely poor line
conditions.
User programmable features allow the modem operation to be
tailored to support a wide range of functional requirements. The
modem's small size, low power consumption, and serial/parallel
host interface simplify system design and allow installation in
a small enclosure.
•
•
•
•
•
Half·Duplex (2·Wire)
Programmable Tone Generation and Detection
Dynamic Range: -47 dBm to 0 dBm
Diagnostic Capability
Equalization:
- Automatic Adaptive
- Compromise Cable (Selectable)
- Compromise Link Amplitude (Selectable)
•
DTE Interface:
- Microprocessor Bus
- CCITT V.24 (RS·232·C Compatible)
Small Size: 100 mm x 65 mm (3.94 in. x 2.56 in.)
Low Power Consumption: 2W (typical)
Transmit Output Level: + 5 dBm ± 1 dB
TTL and CMOS Compatible
•
•
•
•
R96PCJ Modem
Document No. 29200N16
Data Sheet
3·80
Order No. MD16
Rev. 2, February 1987
9600 bps PC Communication Modem
R96PCJ
TECHNICAL SPECIFICATIONS
EQUALIZERS
TRANSMITTER TONAL SIGNALING AND CARRIER
FREQUENCIES
The R96PCJ provides the following equalization functions which
can be used to improve performance when operating over poor
lines:
T.30 Tonal Signaling Frequencies
Function
Calling Tone (CNG)
Answer Tone (CEO)
Cable Equalizers - Selectable compromise cable equalizers
are provided to optimize performance over different lengths of
non-loaded cable of 0.4 mm diameter.
Frequency
(Hz ±0.01 Hz)
1100
2100
Link Amplitude Equalizer - The selectable compromise amplitude equalizer may be inserted into the transmit and/or receive
paths under control of the transmit amplitude equalizer enable
and the receive amplitude equalizer enable bits in the interface
memory. The amplitude select bit controls which of two amplitude equalizers is selected.
Carrier Frequencies
Function
V 27 ter Carrier
V.29 Carner
Frequency
(Hz ± 0.01 Hz)
1800
1700
Automatic Adaptive Equalizer - An automatic adaptive equalizer is provided in the receiver circuit for V.27 and V.29 configurations. The equalizer can be configured as either a T or a T/2
equalizer.
TONE GENERATION
Under control of the host processor. the R96PCJ can generate
voice band tones up to 4800 Hz with a resolution of 0.15 Hz and
an accuracy of 0.01 %. Tones over 3000 Hz are attenuated.
TRANSMITTED DATA SPECTRUM
If neither the link amplitude nor cable equalizer is enabled, the
transmitter spectrum is shaped by the following raised cosine
filter functions:
TONE DETECTION
In the 300 bps FSK receive configuration, the presence of tones
at preset frequencies is indicated by bits in the interface memory
of the R96PCJ.
1. 1200 Baud. Square root of 90 percent.
2. 1600 Baud. Square root of 50 percent.
3. 2400 Baud. Square root of 20 percent.
The out-of-band transmitter power limitations meet those specified by Part 68 of the FCC's Rules, and typically exceed the
requirements of foreign telephone regulatory bodies.
SIGNALING AND DATA RATES
Signaling/Data Rates
Parameter
Specification
(±0.01%)
Signaling Rate:
Data Rate:
2400
9600
7200
4800
Signaling Rate:
Date Rate'
1600 baud
4800 bps
Signaling Rate:
Data Rate
1200 baud
2400 bps
SCRAMBLER/DESCRAMBLER
The R96PCJ incorporates a self-synchronizing scrambler!
descrambler. This facility is in accordance with either V.27 ter
or V.29 depending on the selected configuration.
baud
bps,
bps,
bps
RECEIVED SIGNAL FREQUENCY TOLERANCE
The receiver circuit of the R96PCJ can adapt to received frequency error of up to ± 10Hz with less than a 0.2 dB degradation in BER performance.
DATA ENCODING
RECEIVE LEVEL
At 2400 baud, the data stream is encoded per CCITT V.29. At
9600 bps, the data stream is divided in groups of four-bits (quadbits) forming a 16-point structure. At 7200 bps, the data stream
is divided into three bits (tribits) forming an 8-point structure.
At 4800 bps, the data stream is divided into two bits (dibits) forming a 4-point structure.
The receiver circuit of the R96PCJ satisfies all specified performance requirements for received line signal levels from 0 dBm
to - 43 dBm. The received line signal level is measured at the
receiver analog input (RXA).
RECEIVE TIMING
In the receive state, the R96PCJ provides a Data Clock (DCLK)
output in the form of a square wave. The low to high transitions
of this output coincide with the center of received data bits. The
timing recovery circuit is capable of tracking a ± 0.01 % frequency error in the associated transmit timing source. DCLK
duty cycle is 50% ± 1%.
At 1600 baud, the 4800 bps data stream is encoded into tribits
per CCITT V.27 ter.
At 1200 baud, the 2400 bps data stream is encoded into dibits
per CCITT V.27 ter.
3-81
R96PCJ
9600 bps PC Communication Modem
1"'-------,
I
I
I
I
I
I
I
I
I
I
I
I
USRT
(OPTIONAL)
L-_-
J
J
..
..
0scoPE'
CABS2
I
I
CABS1
RTS
'.'
i:::
CTS
i
TXD
EYEX
I
DCLK
EYEY
~
RLSD
EYESYNC
I
RXD
k
i
fy
xf
EYE
PATTERN
GENERATOR
EYECLK
+12V
R96PCJ
MODEM
+5V
POWER
SUPPLY
GND
READ
-12V
WRITE
~
DATA BUS (8)
HOST
PROCESSOR
(DTE)
TXA
ADDRESS BUS (4)
LINE
INTERFACE
RXA
!ECODER ..... CS (21-
TELEPHONE
LINE
~
POR
AUXIN
IRQ
+5
~
J
1.1
R96PCJ Functional Interconnect Diagram
INTERFACE CRITERIA
R96PCJ Hardware Circuits (Cont.)
Name
The modem interface comprises both hardware and software
circuits. Hardware circuits are assigned to specific pins in a
40-pin ribbon connector. Software circuits are assigned to
specific bits in a 32-byte interface memory.
Type
Pin No.
Description
B. MICROPROCESSOR INTERFACE:
D7
D6
D5
D4
D3
D2
D1
DO
HARDWARE CIRCUITS
Signal names and descriptions of the hardware circuits, including
the microprocessor interface, are listed in the R96PCJ Hardware
Circuits table; the table column titled 'Type' refers to designations found in the Hardware Circuit Characteristics. The microprocessor interface is designed to be directly compatible with
an 8080 microprocessor. With the addition of a few external logic
gates, it can be made compatible with 6500, 6800, or 68000
microprocessors.
IIOA
1I0A
1I0A
1I0A
1I0A
1I0A
1I0A
1I0A
.!}
15
28
23
29
Data Bus (8 Bits)
RS3
RS2
RS1
RSO
IA
IA
IA
IA
27
10
3~}
Register Select (4 Bits)
Select Reg. 0- F
CSO
CS1
READ
WRITE
IRQ
IA
IA
IA
IA
OB
6
18
1
2
32
Chip Select Sample Rate Device
Chip Select Baud Rate Device
Read Enable
Wnte Enable
Interrupt Request
13
19
17
20
21
16
Data Clock
Request-to-Send
Clear-ta-Send
Transmitter Data
Receiver Data
Received Line Signal Detector
C. V.24 INTERFACE:
DCLK
RTS
CTS
TXD
RXD
RLSD
R96PCJ Hardware Circuits
Name
Type
Pin No.
Description
A. OVERHEAD:
Ground
+5 volts
+ 12 volts
-12 volts
POR
GND
PWR
PWR
PWR
1I0A
14,39
3, 4
26
37
36
Power Supply Return
+ 5 Vdc Supply
+ 12 Vdc Supply
-12 Vdc Supply
Power-an-reset
OC
IB
OC
IB
OC
OC
D. CABLE EQUALIZER:
CABS1
CABS2
3-82
IC
IC
33
34
Cable Select 1
Cable Select 2
R96PCJ
9600 bps PC Communication Modem
TRANSMIT LEVEL
RESPONSE TIMES OF CLEAR·TO·SEND (CTS)
The transmitter output level is fixed at + 5 dBm ± 1 dB. When
dnving a 600 ohm load the TXA output requires a 600 ohm series
resistor to provide - 1 dBm ± 1 dB to the load.
The time between the off-to-on transition of RTS and the off-toon transition of CTS is dictated by the length of the training
sequence. Response time is 253 ms for V.29, 708 ms for V.27 ter
at 4800 bps, and 943 ms for V.27 ter at 2400 bps. In V.21 CTS
turns on in 14 ms or less.
TRANSMIT TIMING
In the transmit state, the R96PCJ provides a Data Clock (OCLK)
output with the following characteristics:
1. Frequency. Selected data rate of 9600, 7200, 4800, 2400,
or 300 Hz (±0.01%).
2. Duty Cycle. 50 ± 1 %.
The time between the on-to-offtransition of RTS and the on-tooff transition of CTS in the data state is a maximum of 2 baud
times for all configurations.
Transmit Data (TXO) must be stable during the 1 microsecond
periods immediately preceding and following the rising edge of
OCLK.
For either V.27 ter or V.29, RLSO turns on at the end of the training sequence. If training is not detected at the receiver, the RLSO
off-Io-on response time is 15 ± 10 ms. The RLSO on-to-off
response time for V.27 is 10 ±5 ms and for V.29 is 30 ±9 ms.
Response times are measured with a signal at least 3 dB above
the actual RLSO on threshold or at least 5 dB below the actual
RLSO off threshold.
RECEIVED LINE SIGNAL DETECTOR (RLSD)
TURN·ON SEQUENCE
A total of 14 selectable turn-on sequences can be generated
as defined in the following table:
The RLSO on-to-off response time ensures that all valid data
bits have appeared on RXO.
Turn-On Sequences
No.
V.29
V.27 ter
CTS2
Response Time
(milliseconds)
1 9600 bps
2 7200 bps
3 4800 bps
4800 bps long
4
2400 bps long
5
6
4800 bps short
2400 bps short
7
253
253
253
70B
943
50
67
8 9600 bps
9 7200 bps
10 4800 bps
11
4800 bps long
2400 bps long
12
4800 bps short
13
14
2400 bps short
438
438
438
913
1148
255
272
Two threshold options are provided:
1. Greater than - 43 dBm (RLSO on)
Less than - 48 dBm (RLSO off)
2. Greater than -47 dBm (RLSO on)
Less than - 52 dBm (RLSO off)
Comments
NOTE
Performance may be at a reduced level when the received
signal is less than - 43 dBm.
Preceded by 1
Echo Protector
Tone for Imes
usmg echo
suppressors
A minimum hysteresis action of 2 dB exists between the actual
off-to-on and on-to-off transition levels. The threshold levels and
hysteresis action are measured with an unmodulated 2100 Hz
tone applied to the receiver'S audio input (RXA).
1 Turn-on sequences 8 through 14 are used on lines with pro-
MODES OF OPERATION
tection against talker echo.
2 V.21 (300 bps FSK) RTS-CTS delay IS 14 rns or less.
The R96PCJ is capable of being operated in either a serial or
a parallel mode of operation.
TURN·OFF SEQUENCE
SERIAL MODE
For V.27 ter, the turn-off sequence consists of approximately
10 ms of remaining data and scrambled ones at 1200 baud or
approximately 7 ms of data and scrambled ones at 1600 baud
followed by a 20 ms period of no transmitted energy. For V.29,
the turn-off sequence consists of approximately 5 ms of remaining data and scrambled ones followed by a 20 ms period of no
transmitted energy. In V.21 the transmitter turns off within 7 ms
after RTS goes false.
The serial mode uses standard V.24 (RS-232-C compatible) signals to transfer channel data. An optional USRT device (shown
in the R96PCJ Functional Interconnect Diagram) illustrates this
capability.
PARALLEL MODE
The R96PCJ has the capability of transferring channel data eight
bits at a time via the microprocessor bus.
CLAMPING
The following clamps are provided with the R96PCJ:
1. Received Data (RXD). RXO is clamped to a constant mark
(1) whenever RLSO is off.
2. Received Une Signal Detector (R[SD). RLSO is clamped off
(squelched) during the time when RTS is on.
3. Extended Squelch. Optionally, RLSO remains clamped off for
130 ms after the turn-off sequence.
MODE SELECTION
Selection of either the serial or parallel mode of operation is by
means of a control bit. To enable the parallel mode, the control
bit must be set to a 1. The modem automatically defaults to the
serial mode at power-on. In either mode the R96PCJ is configured by the host processor via the microprocessor bus.
3·83
---
-
--
-- -----
o
9600 bps PC Communication Modem
R96PCJ
Critical Timing Requirements
R96PCJ Hardware Circuits (Cont.)
Name
Type
Pin No.
Characteristic
E. ANALOG SIGNALS:
AA
AB
AC
TXA
RXA
AUXIN
38
40
35
Transmitter Analog Output
Receiver Analog Input
Auxiliary Analog Input
F. DIAGNOSTIC:
EYEX
EYEY
EYECLK
EYESYNC
OC
OC
OA
OA
24
25
11
12
Symbol
Min
CSi, RSI setup time prior
to Read or Write
TCS
Data Access time after Read
TDA
Data hold time after Read
TDH
Description
Eye Pattern
Eye Pattern
Eye Pattern
Eye Pattern
Signal
CSi, RSi hold time after
Read or Write
Data - X AXIs
Data - Y AXIs
Clock
Synchronizing
Max
Units
30
-
ns
-
140
ns
10
50
ns
-
ns
TCH
10
Write data setup time
TWOS
75
Write data hold time
TWDH
10
TWR
75
Write strobe pulse Width
ns
ns
ns
Cable Equalizer Selection
Eye Pattern Generation
Cable Equalizer Selection
The four hardware diagnostic circuits, identified in the preceding
table, allow the user to generate and display an eye pattern. Cir·
cuits EYEX and EYEY serially present eye pattern data for the
horizontal and vertical display inputs respectively. The 8-bit data
words obtained from registers 1:3 and 1:1 (see RAM Data
Access) are shifted out most significant bit first clocked by the
rising edge of the EYECLK output. The EYESYNC output is pro·
vided for word synchronization. The falling edge of EYESYNC
may be used to transfer the 8-bit word from the shift register
to a holding register. Digital to analog conversion can then be
performed for driving the X and Y inputs of an oscilloscope.
CABS 2
CABS 1
Length of O.4mm Diameter Cable
0
0
1
1
0
1
0
1
0.0
1.8 km
3.6 km
7.2 km
Digital Interface Characteristics
The digital interface characteristics are listed in the table on the
following page.
Analog Interface Characteristics
Microprocessor Timing
Analog Interface Characteristics
Type
Characteristics
TXA
AA
The transmitter output is a low impedance
operational amplifier output. In order to
match to 600 ohms, an external 604 ohm
series resistor is required.
RXA
AB
The receiver input impedance is
60K ohms ±23%.
AUXIN
AC
The auxiliary analog input allows access
to the transmitter for the purpose of
interfacing with user provided equipment.
Because this is a sampled data Input, any
signal above 4800 Hz will cause aliasing
errors. The input impedance is 1K ohms,
and the gain to transmitter output is
-0.4 dB ± 1 dB.
Name
SOFTWARE CIRCUITS
(i
The R96PCJ comprises two signal processor chips. Each chip
contains 16 registers to which an external (host) microprocessor
has access. Although these registers are within the modem, they
may be addressed as part of the host processor's memory space.
The host may read data from or write data to these registers.
The registers are referred to as interface memory. Registers in
chip 0 update at the modem sample rate (9600 bps). Registers
in chip 1 update at the selected baud rate.
= 0-1'1----<1
Microprocessor Interface Timing Diagram
3-84
9600 bps PC Communication Modem
R96PCJ
Digital Interface Characteristics
Input/Output Type
Symbol
Parameter
VIH
Input Voltage, High
VIL
VOH
VOL
liN
10H
10L
IL
Ipu
Input Voltage, Low
Output Voltage, High
Output Voltage, Low
Input Current, Leakage
Output Current, High
Output Current, Low
Output Current, Leakage
Pull-up Current
(Short Circuit)
Capacitive Load
Capacitive Drive
CirCUit Type
CL
Co
Notes
1 I ioad = -100 ~A
2. I load = 1.6 mA
3. !load = -40 pA
4. VIN = 0.4 to 2.4 Vdc, Vcc
Units
IA
IB
IC
V
2.0 min.
20 min
20 min
OA
V
V
V
pA
mA
mA
0.8 max.
0.8 max
08 max.
2.4 min.'
0.4 max. 2
-0.1 max.
16 max
~A
5
TTL
5. I load
= 5.25
OC
-240 max
-10 min.
5
-240 max.
-10 min.
20
TTL
w/Pull-up
TTL
w/Pull-up
i/O A
I/O B
20 min.
5.25 max.
2.0 min.
0.8 max
24 min 3
0.4 max. S
,
04 max. 2
0.4 max. 2
±2.5 max
~A
pF
pF
OB
1.6 max.
± 10 max.
08 max.
2.4 min
0.4 max. 2
± 125 max.'
I 1.6 max.
-240 max.
-10 min.
100
TTL
-260 max.
-100 min.
10
40
100
100
100
100
Open-Drain Open Drain
3 State
Open-Drain
wlPull-up Transceiver wlPull-up
= 0.36 mA
Vdc
Data in registers 1:3 and 1:1 are presented serially on EYEX
and EYEY, respectively.
When information in these registers is being discussed, the format Y:Z:O is used. The chip is specified by Y(O or 1), the register
by Z(O-F), and the bit by 0(0-7, 0 = LSB). A bit is considered to
be "on" when set to a 1.
RAM Access Codes
Status/Control Bits
The RAM access codes defined in the following table allow the
host processor to read diagnostic information within the modem.
The operation of the R96PCJ is affected by a number of software control inputs. These inputs are written into registers within
the interface memory via the host microprocessor bus. Bits
designated by an 'X' are "Don't Care" inputs that can be set
to either 1 or O. Modem operation is monitored by various software flags that are read from interface memory via the host
microprocessor bus. All status and control bits are defined in
the Interface Memory table. Bits designated by an '-' are
reserved for modem use only and must not be changed by the
host.
R96PCJ RAM Access Codes
Node
RAM Data Access
Received Signal Samples
Demodulator Output
Low Pass Filter Output
Average Energy
AGC Gain Word
6
Equalizer Input
Equalizer Tap Coefficients
Unrotated Equalizer Output
Rotated Equalizer Output
(Received POint-Eye Pattern)
DeciSion POints (Ideal)
Error Vector
Rotation Angle
Frequency Correction
EQM
7
8
9
The R96PCJ provides the user with access to much of the data
stored in the modem's memories. This data is a useful tool in
performing certain diagnostic functions.
10
11
12
13
14
Two RAM access registers are provided in the interface memory
to allow user access to various RAM locations within the modem.
The access code stored in O:F selects the source of data for the
RAM data registers in chip 0 (0:0 through 0:3). Similarly, the
access code stored in 1:F selects the source of data for registers
1:0 through 1 :3. Reading is performed by storing the desired
access code in register O:F (or 1:F), performing a read of 0:0
(or 1:0) to reset O:E:O (or 1:E:O), then waiting for O:E:O (or 1:E:O)
to return to a one. The data may now be read from 0:3 through
0:0 (or 1:3-1 :0).
3-85
Function
1
2
3
4
5
Access
Chip
Reg. No.
40
42
54
5C
01
0
0
0
0
0
2,3
0,1,2,3
0,1,2,3
2,3
2,3
40
01·20
61
22
1
1
1
1
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
62
63
00
AS
AS
1
1
1
1
1
0,1,2,3
0,1,2,3
0,1
2,3
,2,3
R96PCJ
9600 bps PC Communication Modem
R96PCJ Interface Memory Chip 0 (CSO)
I~
F
PDM
E
lAO
0
C
-
B
-
-
-
A
-
-
-
7
-
6
-
-
-
5
4
RTS
TOIS
X
7
6
5
4
2
3
R96PCJ Interface Memory Chip 1 (CS1)
1
0
Register
9
8
~
7
6
5
4
3
RAM ACCESS S
-
-
-
-
1
0
F
RAM ACCESS B
SETUP
lEO
-
MDAO
E
IA1
-
-
-
-
MDA1
-
-
-
0
X
TLE
RLE
J3L
X
IE1
X,
-
-
X
-
-
C
X
X
X
X
X
X
X
X
-
B
FR3
FR2
FR1
-
A
-
-
-
-
-
-
-
-
9
-
-
CDET
-
-
-
1
0
-
-
-
-
X
EPT
SOEXT
T2
8
7
-
6
LRTH
5
PNDET
FED
-
-
-
-
-
-
CONFIGURATION
4
3
RAM DATA XSM; FREOM
3
RAM DATA XBM
2
RAM DATA XSL; FREOL
2
RAM DATA XBL
1
RAM DATA YSM
1
RAM DATA YBM
0
RAM DATA YSL; TRANSCEIVER DATA
0
RAM DATA YBL
17-
2
Register
7
6
5
4
3
2
1
~
0
7
6
5
4
3
Bit
Bit
X = User available (not used by modem)
- = Reserved (modem use only)
X = User available (not used by modem).
-- = Reserved (modem use only).
3-86
P2DET
2
-
-
-
R96PCJ
9600 bps PC Communication Modem
R96PCJ Interface Memory Definitions
Mnemonic
Name
Memory
Location
Description
CDET
Carner Detector
1'70
The zero state of CDET Indicates passband energy IS being detected, and a training sequence IS
not present. CDET goes to zero at the start of the data state, and returns to one at the end of the
received signal CDET activates up to 1 baud time before RLSD and deactivates within 2 baud
times after RLSD.
(None)
Configuration
0"4:0-7
The host processor configures the R96PCJ by writing a control code Into the configuration
register in the interface memory space. (See SETUP.)
Configuration Control Codes
Control codes for the four available R96PCJ configurations are:
Configuration
Configuration Code (HEX)
V.299600
V.297200
V.294800
V.27 4800 Long
V.27 2400 Long
V.27 4800 Short
V.27 2400 Short
Tone Transmit
FSK
14
12
11
OA
09
4A
49
80
20
Configuration Definitions
Definitions for the four available R96PCJ configurations are:
1. V.29. When any of the V.2.9 configurations has been selected, the modem operates as specified
in CCITT Recommendation V.29.
2. V.27. When any of the V.27 configurations has been selected, the modem operates as specified
In
CCIlT Recommendation V.27 ter.
3. FSK. The modem operates as a CCITI T.30 compatible 300 bps FSK modem having
characteristics of the CCITI V 21 channel 2 modulation system.
4. Tone Transmit. In this configuration, activating signal RTS causes the modem to transmit a tone
at a single frequency specified by the user. Two registers in the host interface memory space
contain the frequency code. The most significant bits are specified in the FREOM register (0:3).
The least significant bits are specified in the FREOL register (0:2). The least significant bit
represents 0.146486 Hz ± 001%. The frequency generated is: f = 0.146486 (256 FREOM + FREOL)
Hz ±0.01%.
EPT
Echo Protector
Tone
0.5:3
If EPT is a one, an unmodulated carner IS transmitted for 185 ms followed by 20 ms of no
transmitted energy at the beginning of the training sequence. This option is available in both the
V.27 and V.29 configurations, although It is not specified In the CCITI V.29 Recommendation.
FED
Fast Energy
Detector
1:5.6
The zero state of FED Indicates energy is present above the receiver threshold in the passband.
(None)
FREOLIFREOM
0:2:0-7,
0:3:0-7
The host processor conveys tone generation data to the transmitter by writing a 16-bit data word to
the FREOL and FREOM registers in the interface memory space, as shown below.
FREQM Register (0:3)
IBit:
I
IData Word: I
7
2'5
I
I
6
2'4
I
I
5
2'3
I
I
I
I
6
26
I
I
5
25
I
I
4
2'2
I
I
2"
I
I
23
3
I
I
2
2'0
I
I
2
22
I
1
I
0
I
I
29
I
28
I
I
I
.1
I
I
0
20
I
I
FREQL Register (0:2)
LBi!:
1
IData Word: I
7
27
3-87
4
24
3
2'
9600 bps PC Communication Modem
R96PCJ
R96PCJ Interface Memory Definitions (continued)
Mnemonic
Name
Memory
Location
Description
The frequency number (N) determines the frequency (F) as follows:
F = (0.146486) (N) Hz ±0.01%.
Hexadecimal frequency numbers (FREQM, FREQl) for commonly generated tones are given
below:
Frequency (Hz)
FREQM
FREQl
462
1100
1650
1850
2100
FR1-FR3
Frequency 1,2,3
I:B:5,6,7
DC
52
55
00
55
00
10
2C
31
38
The one state of FR1, FR2 or FR3 indicates reception of the respective tonal frequency when the
modem is configured for FSK. The default frequencies for FR1, FR2 and FR3 are:
Bit
Frequency (Hz)
FR1
FR2
FR3
2100
1100
462
IAI
Interrupt Act,ve
(One)
I:E:7
IAI is a one when Chip 1 is driving IRQ to zero volts.
lAO
Interrupt Active
(Zero)
0:E:7
lAO is a one when Chip 0 is driving IRQ to zero volts.
lEO
Interrupt Enable
(Zero)
0:E:2
The one state of lEO causes the IRQ output to be low when the DAO bit is a one.
lEI
Interrupt Enable
(One)
I:E:2
The one state of lEI causes the IRQ output to be low when the DAI bit is a one.
J3l
Japanese 3 Link
1:0:4
The one state of J3L selects this standard for link amplitude equalizer. The zero state of J3l
selects U.S. survey long.
lRTH
Lower Receive
Threshold
0:5:0
The one state of LRTH lowers the receiver lurn-on threshold from -43 dBm to -47 dBm. (See
SETUP.)
MDAO
Modem Dala
Available (Zero)
O:E:O
MDAO goes to one when the modem reads or writes register 0:0. MDAO goes to zero when the
host processor reads or writes register 0:0. MDAO is used for parallel mode as well as for
diagnostic data retrieval.
MDAI
Modem Data
Available (One)
I:E:O
MDAI goes to one when the modem writes register 1:0. MDAI goes to zero when the host
processor reads regIster 1:0.
PDM
Parallel Data
Mode
0:F:7
The one state of PDM places the modem in the parallel mode and inhibits the readIng of Chip 0
diagnostic data.
PNDET
Period 'N'
Detector
1:7:6
The zero state of PNDET indicates a PN sequence has been detected. PNDET sets to a one at the
end of the PN sequence.
P2DET
Period '2'
Detector
1:4:2
The zero state of P2DET indicates a P2 sequence has been detected. P2DET sets to a one at the
start of the PN sequence.
(None)
RAM Access B
I:F:0-7
Contains the RAM access code used in reading or writing RAM locations In Chip 1 (baud rate
device).
(None)
RAM Access S
0:F:0-6
Contains the RAM access code used in reading RAM locatIons
(None)
RAM Data XBL
1:2:0-7
Least significant byte of 16-bit word x used in reading RAM locations in Chip 1 (baud rate device)
(None)
RAM Data XBM
1:3:0-7
Most Significant byte of 16-bit word x used in reading RAM locations
3-88
In
Chip 0 (sample rate device).
In
Chip 1 (baud rate device).
R96PCJ
9600 bps PC Communication Modem
V27 2400
V27,4800
'
/
V29,7200
V29,9600
\ V29,4800
10- 3 r--;~-,---t--~----r-f-~r--'------,
10- 3
10- 4 r----;-i----~~~--~t-t---rt------~
10- 4
UJ
UJ
II:
II:
II:
II:
II:
II:
II:
,
K
V27,4800
V29,7200
I
V29,9600
\
~
~
ct
o
0
UJ
UJ
~
~
iii
iii
10- 5
r
V27,2400
V29,4800
r------t------~--~--~~~_++_----~
10- 5
____~~____~~___LL___~~__~__~
10- 6
10-6~
o
5
10
15
20
\
0
25
5
10
1\
\
15
20
25
Signal to Noise Ratio in dB
Signal to Noise Ratio in dB
Typical Bit Error Rate
(Back to Back, T Equalizer, Level - 20 dBm)
Typical Bit Error Rate
(Unconditioned 3002 Line, T Equalizer, Level - 20 dBm)
The BER performance test set-up is shown in the following
diagram:
-
MODEM
TRANSMITTER
3002
IMPAIRMENT
LINE
SOURCE
f----- SIMULATOR f----- BRADLEY 2A
SEG FA-1445
AND 2B
r-----
ATTENUATOR
HP 350D
I
MODEM
RECEIVER
J
I
MODEM
TEST SET
PHOENIX
5000
LEVEL
METER
HP 3552A
NOTE
SIGNAL AND NOISE ARE MEASURED WITH 3 KHZ FLAT WEIGHTING.
BER Performance Test Set-up
3-89
R96PCJ
9600 bps PC Communication Modem
R96PCJ Interface Memory Definitions (continued)
Mnemonic
Name
--
Memory
Location
Description
(None)
RAM Data XSL
0:2:0-7
Least significant byte of 16-bit word x used in reading RAM locations in Chip 0 (sample rate
device).
(None)
RAM Data XSM
0:3:0-7
Most significant byte of 16-bit word x used in reading RAM locations In Chip 0 (sample rate
device).
(None)
RAM Data YBL
1:0:0-7
Least significant byte of 16-bit word y used in reading or writing RAM locations in Chip 1 (baud
rate device). (See DA1.)
(None)
RAM Data YBM
1:1:0-7
Most significant byte of 16-bit word y used
rate deVice).
(None)
RAM Data YSL
0:0:0-7
Least significant byte of 16-bit word y used in reading RAM locations in Chip 0 (sample rale
deVice). Shared by parallel data mode for presenting channel data to the host microprocessor
bus. (See Transceiver Data and DAO.)
(None)
RAM Data YSM
0:1:0-7
Most significant byte of 16-bit word y used in reading RAM locations in Chip 0 (sample rate
device).
RLE
Receiver Link
Equalizer
1:0:5
The one state of RLE enables the link amplitude equalizer in the receiver.
RTS
Request-to-Send
0:5:7
The one state of RTS begins a transmit sequence. The modem will continue to transmit until RTS
IS turned off, and the turn-off sequence has been completed. RTS parallels the operation of the
hardware RTS control input. These Inputs are "ORed" by the modem.
SETUP
Setup
0:E:3
The one state of SETUP causes the modem to reconfigure to the control word in the configuration
register, and to assume the options specified for equalizer (0:5:1) and threshold (0:5:0). SETUP
returns to zero when acted on by the modem. The time required for the SETUP bit to cause a
change depends on the current state of the modem. The following table lists worst case delays.
Current
State
V.21
High Speed
Receiver
In
reading or Writing RAM locations in Chip I (baud
High Speed Transmitter
DELAY 14 ms
2 BAUD
2 BAUD + TURNOFF Sequence + Training (if
______~____~________~a~p~p_lic_a_b_'e~)_+__S_Q_U_E_L_C_H_(~if_a~p~p'_ic_a_b_'e~)________~
SQEXT
Squelch Extend
0:5:2
The one state of SQEXT inhibits reception of signals for 130 ms after the turn-off sequence.
TOIS
Training Disable
0:5:6
If TOIS is a one in the receive state, the modem IS prevented from entering the training phase. If
TOIS IS a one prior to RTS going on, the generation of a training sequence is prevented at the
start of transmission.
TLE
Transmitter Link
Equalizer
1:0:6
The one state of TLE enables the link amplitude equalizer in the transmitter.
(None)
Transceiver Data
0:0'0-7
In receive parallel data mode, the modem presents eight bits of channel data in register 0:0 for
reading by the host microprocessor. After the eight bits have been accumulated in register O:C
they are transferred to 0:0 and bit O:E:O goes to a one. When the host reads 0:0, bit O:E:O resets
to a zero. The first bit of received data is not necessarily located in bit 0:0:0. The host must frame
the received data by searching for message sync characters. Bit O:E:O sets at one eighth the bit
rate in parallel data mode rather than at the sample rate (9600 Hz) as it does when reading RAM
locations.
In transmit parallel data mode, the host stores data at location 0:0. This action causes bit O:E:O to
reset to a O. When the modem transfers the data from 0:0 to 0:2 bit O:E:O sets to a 1. The data is
serially transmitted from register 0:2 least significant bit first. Received data is shifted into register
O:C from MSB toward LSB.
T2
T/2 Equalizer
Select
I
~-
0:5:1
If T2 is a one, an adaptive equalizer with two taps per baud IS used. If T2 is a zero, an adaptive
equalizer with one tap per baud is used. The number of taps remains the same for both cases.
(See SETUP.)
I
3-90
R96PCJ
9600 bps PC Communication Modem
POWER-ON INITIALIZATION
Recommendation V.56. Bit error rates are measured at a
received line signal level of -20 dBm as illustrated.
When power is applied to the R96PCJ, a period of 50 to 350 ms
is required for power supply settling. The power-on-reset signal
(POR) remains low during this period. Approximately 10 ms after
the low-to-high transition of POR, the modem is ready to be configured, and RTS may be activated. If the 5 Vdc power supply
drops below 3.5 Vdc for more than 30 ms, the POR cycle is
repeated.
TYPICAL PHASE JITTER
At 2400 bps, the modem exhibits a bit error rate of 10-6 or less
with a signal-to-noise ratio of 12.5 dB in the presence of 15°
peak-to-peak phase jitter at 150 Hz or with a signal-to-noise ratio
of 15 dB in the presence of 30° peak-to-peak phase jitter at
120 Hz (scrambler inserted).
At POR time the modem defaults to the following configuration:
V.29/9600 bps, T/2 equalizer, serial mode, training enabled, echo
protector tone on, no extended squelch, higher receive
threshold, interrupts disabled, no link equalizer, and RAM access
codes 00.
At 4800 bps (V.27 ter), the modem exhibits a bit error rate of
10-6 or less with a signal-to-noise ratio of 19 dB in the presence
of 15° peak-to-peak phase jitter at 60 Hz.
POR can be connected to a user supplied power-on-reset signal
in a wire-or configuration. A low active pulse of 3 I"s or longer
applied to the POR pin causes the modem to reset. The modem
is ready to be configured 10 ms after the low active pulse is
removed from POR.
At 7200 bps (V.29), the modem exhibits a bit error rate of 10- 6
or less with a signal-to-noise ratio of 25 dB in the presence of
12° peak-to-peak phase jitter at 300 Hz.
PERFORMANCE
At 9600 bps, the modem exhibits a bit error rate of 10-6 or less
with a signal-to-noise ratio of 23 dB in the presence of 10° peakto-peak phase jitter at 60 Hz. The modem exhibits a bit error
rate of 10-5 or less with a signal-to-noise ratio of 23 dB in the
presence of 20° peak-to-peak phase jitter at 30 Hz.
Whether functioning as a V.27 ter or V.29 type modem, the
R96PCJ provides the user with unexcelled high performance.
TYPICAL BIT ERROR RATES
An example of the BER performance capabilities is given in the
following diagrams:
The Bit Error Rate (BER) performance of the modem is specified
for a test configuration conforming to that specified in CCITT
3-91
o
R96PCJ
9600 bps PC Communication Modem
GENERAL SPECIFICATIONS
Power
Voltage
Tolerance
Current (Typical) @ 25°C
Current (Max) @ O°C
+5 Vdc
+ 12 Vdc
-12 Vdc
±5%
±5%
±5%
400 mA
5 mA
30 mA
<500 mA
<10 mA
<50 mA
Note: All voltages must have ropple :$0.1 volts peak-Ie-peak
Environmental
Parameter
Temperature
Operating
Storage
Relative HumIdity
Specification
O°C to + ao°c (32°F to 140°F)
-40°C to + aooc (_40°F to 176°F) (Stored in heat sealed antIstatIc bag and shipping container)
Up to 90% noncondenstng, or a wet bulb temperature up to 35°C, whIchever is less
Mechanical
Parameter
Board Structure
DimenSIons
Width
Length
Height
Weight (max)
Lead Extrusion (max)
Specification
SIngle PC board WIth stngle right angle header with 40 pins. Burndy FRS 40BSap or equivalent mating
connector.
3.937 in. (100 mm)
2.559 in. (65 mm)
0.40 in. (10.2 mm)
2.6 oz. (73 g)
0.100 in. (2.54 mm)
r
J!
3.437
(100)
.675
(93.3)
I
~
'---"":===:':'t.:::::!p, ~!~
!'I'I
I~
-----.j
2.300
(58.4) 2.559
0.125
(3.18)
~(65)
0.400
COMPONENT AREA
~~~--/----n
t t~--(1.6)
-----~
0.100
J
(2.54)
+
UNITS: INCHES
[0.400 MAX
(10.16)
RIBBON CONNECTOR VERSION
R96PCJ Dimensions and Pin Locations
3-92
mm
R96F
Integral Modems
'1'
Rockwell
R96F
9600 bps Facsimile Modem
INTRODUCTION
FEATURES
The Rockwell R96F is a synchronous 9600 bits per second (bps)
modem. It is designed for operation over the public switched
telephone network (PSTN) through line terminations provided
by a data access arrangement (DM).
• Compatibility:
- CCITT V.29, V.27 ter, T.30, V.21 Channel 2, T.4, T.3
• Group 3 and Group 2 Facsimile
• Half-Duplex (2-Wire)
• Tone Detection
• Programmable Tone Generation and Detection
• Dynamic Range: -47 dBm to 0 dBm
• Diagnostic Capability
• Equalization:
- Automatic Adaptive
- Compromise Cable (Selectable)
- Compromise Link Amplitude (Selectable)
• DTE Interface:
- Microprocessor Bus
- CCITT V.24 (RS-232-C Compatible)
• Small Size:
- Ribbon cable connector version
100 mmx65 mm (3.94 in.x2.56 in.)
- Dual in-line pin (DIP) connector version
88.9 mm x 50.8 mm (3.5 in. x 2.0 in.)
• Low Power Consumption: 2 W (Typical)
• Transmit Output Level: + 5 dBm ± 1 dB
• TTL and CMOS Compatible
The modem satisfies the telecommunications requirements
specified in CCITT recommendations V.29, V.27 ter, T.30, T.4
and T.3. The R96F can operate at speeds of 9600,7200,4800,
2400 and 300 bps. Employing advanced signal processing
techniques, the R96F can transmit and receive data even under
extremely poor line conditions.
The R96F is designed for use in Group 3 facsimile machines
and is also compatible with Group 2 machines. User programmable features allow the modem operation to be tailored to
support a wide range of functional requirements. The modem's
small size, low power consumption, serial/parallel host interface,
simplify system design. Two module versions are available: one
with a ribbon connector for cable connection to a host, and one
with dual in-line pins for direct connection onto a host module.
R96F Ribbon Connector Version
Document No. 29200N06
R96F DIP Connector Version
Data Sheet
3-93
Order No. MD06
Rev. 5, February 1987
9600 bps Facsimile Modem
R96F
TECHNICAL SPECIFICATIONS
At 1200 baud, the 2400 bps data stream is encoded into dibits
per CCITT V.27 ter.
TRANSMITTER TONAL SIGNALING AND CARRIER
FREQUENCIES
EQUALIZERS
T.30 Tonal Signaling Frequencies
Frequency
(Hz ±O.O1%)
Function
Calling Tone (CNG)
Answer Tone (CEO)
Group 2 Identification (CI2)
Group 2 Command (GC2)
Group 2 Confirmation (CFR2, MCF2)
Line Conditioning Signal (LCS)
End of Message (EOM)
Procedure Interrupt (PIS)
The modem provides the following equalization functions which
can be used to improve performance when operating over poor
lines:
1100
2100
1850
2100
1650
1100
1100
462
Cable Equalizers - Selectable compromise cable equalizers
are provided to optimize performance over different lengths of
non·loaded cable of 0.4 mm diameter.
Link Amplitude Equalizer - The selectable compromise ampli·
tude equalizer may be inserted into the transmit andlor receive
paths under control of the transmit amplitude equalizer enable
and the receive amplitude equalizer enable bits in the interface
memory. The amplitude select bit controls which of two ampli·
tude equalizers is selected.
Carrier Frequencies
Function
T.3 Carrier (Group 2)
V.27 ter Carrier
V.29 Carrier
Frequency
(Hz ±O.OI%)
Automatic Adaptive Equalizer - An automatic adaptive equal·
izer is provided in the receiver Circuit for V.27 and V.29 config·
urations. The equalizer can be configured as either a T or a Tl2
equalizer.
2100
1800
1700
TRANSMITTED DATA SPECTRUM
TONE GENERATION
If neither the link amplitude nor cable equalizer is enabled, the
transmitter spectrum is shaped by the following raised cosine
filter functions:
Under control of the host processor, the modem can generate
voice band tones up to 4800 Hz with a resolution of 0.15 Hz and
an accuracy of 0.01%. Tones over 3000 Hz are attenuated.
TONE DETECTION
1. 1200 Baud.
2. 1600 Baud.
3. 2400 BaUd.
In the 300 bps FSK receive configuration, the presence of tones
at preset frequencies is indicated by bits in the interface memory
of the modem.
The out·of·band transmitter power limitations meet those spe·
cified by Part 68 of the FCC's Rules, and typically exceed the
requirements of foreign telephone regulatory bodies.
SCRAMBLER/DESCRAMBLER
SIGNALING AND DATA RATES
The modem incorporates a self·synchronizing scramblerl
descrambler. This facility is in accordance with either V.27 ter
or V.29 depending on the selected configuration.
Signaling/Data Rates
Parameter
Square root of gO percent.
Square root of 50 percent.
Square root of 20 percent.
Specification
(±O.O1%)
Signaling Rate:
Data Rate:
2400
9600
7200
4800
Signaling Rate:
Dale Rate:
1600 baud
4800 bps
Signaling Rate:
Data Rate:
1200 baud
2400 bps
RECEIVED SIGNAL FREQUENCY TOLERANCE
baud
bps,
bps,
bps
The modem receiver circuit can adapt to received frequency
error of up to ± 10 Hz with less than a 0.2 dB degradation in
BER performance. Group 2 carrier recovery capture range is
2100 ±30 Hz. The Group 2 receiver operates properly when
the carrier is varied by ± 16 Hz at a 0.1 Hz per second rate.
RECEIVE LEVEL
The modem receiver circuit satisfies all specified performance
requirements for received line signal levels from 0 dBm to
- 43 dBm. The received line Signal level is measured at the
receiver analog input (RXA).
DATA ENCODING
At 2400 baud, the data stream is encoded per CCITT V.29. At
9600 bps, the data stream is divided in groups of four·bits (quad·
bits) forming a 16·point structure. At 7200 bps, the data stream
is divided into three bits (tribits) forming an 8·point structure.
At 4800 bps, the data stream is divided into two bits (dibits) form·
ing a 4·point structure.
RECEIVE TIMING
In the receive state, the modem provides a Data Clock (DCLK)
output in the form of a square wave. The low to high transitions
of this output coincide with the center of received data bits. The
timing recovery circuit is capable of tracking a ± 0.01 % fre·
quency error in the associated transmit timing source. DCLK
duty cycle is 50% ± 1%.
At 1600 baud, the 4800 bps data stream is encoded into tribits
per CCITT V.27 ter.
3·94
R96F
9600 bps Facsimile Modem
TRANSMIT LEVEL
sequence. Response time is 253 ms for V.29, 708 ms for V.27
ter at 4800 bps, and 943 ms for V.27 ter at 2400 bps. In V.21 CTS
turns on in 14 ms or less. In Group 2 CTS turns on in 400 /Ls
or less.
The transmitter output level is fixed at + 5 dBm ± 1 dB. When
driving a 600 ohm load the TXA output requires a 600 ohm series
resistor to provide -1 dBm ± 1 dB to the load.
The time between the on-to-off transition of RTS and the on-tooff transition of CTS in the data state is a maximum of 2 baud
times for all configurations.
TRANSMIT TIMING
In the transmit state, the modem provides a Data Clock (DCLK)
output with the following characteristics:
1. Frequency. Selected data rate of 9600, 7200, 4800, 2400,
or 300 Hz (± 0.01 oAl). In Group 2, DCLK tracks an external
10368 Hz clock. If the external clock input (XCLK) is
grounded, the Group 2 DCLK is 10372.7 Hz ±O.Ol oAl.
2. Duty Cycle. 50 ± 1%
RECEIVED LINE SIGNAL DETECTOR (RLSD)
For either V.27 ter or V.29, RLSD turns on at the end of the training sequence. If training is not detected at the receiver, the RLSD
off-ta-on response time is 15 ± 10 ms. The RLSD on-to-off
response time for V.27 is 10 ± 5 ms and for V.29 is 30 ± 9 ms.
Response times are measured with a Signal at least 3 dB above
the actual RLSD on threshold or at least 5 dB below the actual
RLSD off threshold.
Transmit Data (TXD) must be stable during the 1 microsecond
period immediately preceding and the 1 microsecond period
immediately following the rising edge of DCLK.
The RLSD on-to-off response time ensures that all valid data
bits have appeared on RXD.
TURN·ON SEQUENCE
A total of ten selectable turn-on sequences can be generated
by the modem, as defined in the following table:
Two threshold options are provided:
1. Greater than - 43 dBm (RLSD on)
Less than - 48 dBm (RLSD off)
2. Greater than - 47 dBm (RLSD on)
Less than - 52 dBm (RLSD off)
Turn·On Sequences
RTS-CTS Turn-On Time
Specification
Echo Protector
Tone Disabled
Echo Protector
Tone Enabled
V.29
V.27 4800 bps
V.27 2400 bps
253 rns
708 rns
943 rns
438 rns
913 rns
1148 rns
V.21 300 bps
Group 2
",14 rns
",400 ¢I
",14 rns
", 4OO I'S
NOTE
Performance may be at a reduced level when the received
signal is less than - 43 dBm.
A minimum hysteresis action of 2 dB exists between the actual
off-to-on and on-ta-off transition levels. The threshold levels and
hysteresis action are measured with an unmodulated 2100 Hz
tone applied to the receiver'S audio input (RXA).
TURN·OFF SEQUENCE
For V.27 ter, the turn-off sequence consists of approximately
10 ms of remaining data and scrambled ones at 1200 baud or
approximately 7 ms of data and scrambled ones at 1600 baud
followed by a 20 ms period of no transmitted energy. For V.29,
the turn-off sequence consists of approximately 5 ms of remaining data and scrambled ones followed by a 20 ms period of no
transmitted energy. In V.21 the transmitter turns off within 7 ms
after RTS goes false. In Group 2 the transmitter turns off within
200 p.S after RTS goes false.
MODES OF OPERATION
The modem operates in either a serial or a parallel mode.
SERIAL MODE
The serial mode uses standard V .24 (RS-232-C compatible) signals to transfer channel data. An optional USRT device (shown
in the Modem Functional Interconnect Diagram) illustrates this
capability.
CLAMPING
The following clamps are provided with the modem:
1. Received Data (RXD). RXD is clamped to a constant mark
(1) whenever RLSD is off.
2. Received Une Signal Detector (RLSf>2:.£ILSD is clamped off
(squelched) during the time when RTS is on.
3. Extended Squelch. Optionally, RLSD remains clamped off for
130 ms after the turn-off sequence.
PARALLEL MODE
The modem can transfer channel data eight bits at a time via
the microprocessor bus.
MODE SELECTION
Selection of either the serial or parallel mode of operation is by
means of a control bit. To enable the parallel mode, the control
bit must be set to a 1. The modem automatically defaults to the
serial mode at power-on. In either mode the modem is configured
by the host processor via the microprocessor bus.
RESPONSE TIMES OF CLEAR·TO·SEND (CTS)
The time between the off-ta-on transition of RTS and the off-taon transition of CTS is dictated by the length of the training
3-95
9600 bps Facsimile Modem
R96F
,..-------.,
RTS
t::
CTS
:-
USRT
(OPTIONAL)
xt
EYEX
I
DCLK
EYEY
:...
RLSD
EYESYNC
RXD
ty
EYE
PATTERN
GENERATOR
EYECLK
i
l
':SCOP~ :
CABS1
TXD
I
L---
Q ..
CABS2
I
I
R96F
MODEM
oJ
+12V
+5V
POWER
SUPPLY
GND
READ
-12V
WRITE
DATA BUS (8)
HOST
PROCESSOR
(DTE)
ADDRESS BUS (4)
TXA
Di
RSi
RXA
DECODER h
I'
CS (2).
POR
-"y
TELEPHONE
LINE
CSi
AUXIN
IRQ
+5
LINE
INTERFACE
J
Modem Functional Interconnect Diagram
INTERFACE CHARACTERISTICS
V.24 Interface
The modem interface comprises both hardware and software
circuits. Hardware circuits are assigned to specific pins in a
4Q..pin ribbon connector or in a 41-pin dual in-line pin connector.
Software circuits are assigned to specific bits in a 32-byte interface memory.
Seven hardware circuits provide timing, data and control signals
for implementing a serial interface compatible with CCITT
Recommendation V.24. These signals interface directly with circuits using TTL logiC levels (0, + 5 volt). These TTL levels are
suitable for driving the short wire lengths or printed Circuitry
normally found within stand-alone modem enclosures or equipment cabinets.
HARDWARE CIRCUITS
Signal names and descriptions of the hardware circuits, including
the microprocessor interface, are listed in the Modem Hardware
Circuits table; the table column titled 'Type' refers to designations found in the Digital or Analog Interface Characteristics.
In applications where the modem is operated in parallel data
mode only (i.e., where the V.24 signals are unused), all V.24
pins may remain unterminated.
Microprocessor Interface
Cable Equalizers
Sixteen hardware circuits provide address (RSO-RS3), data
(00-07), control (CS, READ and WRITE) and interrupt (IRQ)
signals for implementing a parallel interface compatible with an
8080 microprocessor. (Refer to the Microprocessor Interface
Timing Waveforms figure and Microprocessor Interface Timing
Requirements table.) With the addition of a few external logic
gates, the interface can be made compatible with a wide variety
of microprocessors such as 6qOO, 6800, or 68000.
Modems may be connected by direct wiring, such as leased
telephone cable or through the public switched telephone network, by means of a data access arrangement. In either case,
the modem analog signal is carried by copper wire cabling for
at least some part of its route. The cable characteristics shape
the passband response so that the lower frequencies of the passband (300 Hz to 1700 Hz) are attenuated less than the higher
frequencies (1700 Hz to 3300 Hz). The longer the cable the more
pronounced the effect.
The microprocessor interface allows a host microprocessor to
change modem configuration, read or write channel data as we"
as diagnostic data, and supervise modem operation by means
of software strappable control bits and modem status bits. The
significance of the control and status bits and methods of data
interchange are discussed in the Software Circuits section.
To minimize the impact of this undesired passband shaping, a
compromise equalizer with more attenuation at lower frequencies than at higher frequencies can be placed in series with the
analog signal. The modem includes three such equalizers
designed to compensate for cable distortion.
3-96
9600 bps Facsimile Modem
R96F
Critical Timing Requirements
Modem Hardware Circuits (Cont.)
RC
DIP
Type Pin No. Pin No.
Name
Characteristic
Description
E. ANALOG SIGNALS:
AA
AB
AC
TXA
RXA
AUXIN
38
40
35
23
22
20
TransmItter Analog Output
ReceIver Analog Input
AuxIliary Analog Input
F. DIAGNOSTIC:
EYEX
EYEY
EYECLK
EYESYNC
OC
DC
OA
OA
Min
TCS
30
ns
lOA
-
-
Data Access tIme after Read
140
ns
Data hold time after Read
TDH
10
50
ns
CSI, RSi hold tIme after
Read or Wrije
24
25
11
12
35
40
38
37
Eye Pattern
Eye Pattern
Eye Pattern
Eye Pattern
Signal
Data - X Axis
Data - Y Axis
Clock
Synchronizing
Max
Units
Symbol
CSi, RSi setup tIme prior
to Read or Write
TCH
10
-
ns
Write data setup time
TWOS
75
-
ns
Write data hold time
TWOH
10
-
ns
TWR
75
-
ns
Write strobe pulse width
RC = Ribbon connector
DIP = Dual in-hne pinS
Analog Interface Characteristics
Name
Diagnostic
The four hardware diagnostic circuits, identified in the preceding
table, allow the user to generate and display an eye pattern.
Circuits EYE)( and EYEY serially present eye pattern data for
the horizontal and vertical display inputs respectively. The B-bit
data words are shifted out most significant bit first, clocked by
the rising edge of the EYECLK output. The EYESYNC output
is provided for word synchronization. The falling edge of
EYESYNC may be used to transfer the B-bit word from the shift
register to a holding register. Digital to analog conversion can
then be performed for driving the X and Y inputs of an
oscilloscope.
Type
Characteristics
TXA
AA
The transmitter output is a low Impedance
operational amplifier output. In order to
match to 600 ohms, an external 604 ohm
series resistor IS required.
RXA
AB
The receiver input impedance is
SOK ohms ± 23%.
AUXIN
AC
The auxihary analog input allows access
to the transmitter for the purpose of
interfacing with user provided equipment.
Because this is a sampled data input, any
signal above 4800 Hz will cause aliaSing
errors. The Input impedance is lK ohms,
and the gain to transmItter output is
-0.4 dB ±1 dB.
SOFTWARE CIRCUITS
The modem includes two signal processor chips. Each of these
chips contains 16 registers to which an external (host)
microprocessor has access. Although these registers are within
the modem, they may be addressed as part of the host processor's memory space. The host may read data out of or write
data into these registers. The registers are referred to as interface
memory. Registers in chip 0 update at the modem sample rate
(9600 bps). Registers in chip 1 update at the selected baud rate.
When information in these registers is being discussed, the fOrmat Y:Z:Q is used. The chip is specified by Y(O or 1), the register
by Z(O-F), and the bit by Q(0-7, 0 LSB). A bit is considered to
be "on" when set to a 1.
=
Status/Control Bits
Modem operation is affected by a number of software control
inputs. These inputs are written into registers within the interface memory via the host microprocessor bus. Modem operation is monitored by various software flags that are read from
interface memory via the host microprocessor bus. All status andcontrol bits are defined in the Interface Memory table. Bits
deSignated by a •- ' are reserved fOr modem use only and must
not be changed by the host.
Microprocessor Interface Timing Diagram
3-97
9600 bps Facsimile Modem
R96F
POR pin is not driven low by the modem when the POR
sequence is initiated externally. In all cases, the POR sequence
requires 50 ms to 350 ms to complete. The POR sequence
leaves the modem configures as follows:
• V.29/9600 bps
• Tl2 equalizer
• Serial mode
• Training enabled
• Echo protector tone enabled
• No extended squelch
• Higher receive threshold
• Interrupts disabled
• No link equalizer
• RAM access codes 00
This configuration is suitable for performing high speed data
transfer on the PSTN with the serial data port selected as the
input and output point for data terminal equipment (OTE).
Cable Equalizer Selection
CABS2
CABS1
Length of O.4mm Diameter Cable
0
0
1
1
0
1
0
1
0.0
1.8 km
3.6 km
7.2 km
Analog Signals
Three analog signals provide the interface point for telephone
company audio circuits and host audio inputs: TXA, RXA, and
AUXIN.
The TXA line is an output suitable for driving an audio transformer or data access arrangement for connection to either
leased lines or the PSTN. The output structure of TXA is a low
impedance amplifier in series with an internal 604 ohm ± 1%
resistor to match a standard telephone load of 600 ohms.
Modem Hardware Circuits
RXA is an input to the receiver from an audio transformer or
data access arrangement. The input impedance is nominally
60K ohms but a factory select resistor allows a variance of 23%.
The RXA input must be shunted by an external resistor in order
to match a 600 ohm source. A 604 ohm ± 1% .resistor is
satisfactory.
Name
DIP
RC
Type Pin No. Pin No.
Description
A. OVERHEAD:
Some form of transient protection for TXA and RXA is recommended when operating directly into a transformer. This protection may be back-te-back zener diodes across the transformer
or a varistor across the transformer.
Ground
GND
14, 39
+5 volts
+ 12 volts
-12 volts
POR
PWR
PWR
PWR
1I0B
3, 4
26
37
36
17,18,
41"
33,34
21
19
39
Power Supply Return
+ 5 volt supply
+ 12 volt supply
- 12 volt supply
Power-an-reset
B. MICROPROCESSOR INTERFACE:
D7
D6
D5
D4
D3
D2
Dl
DO
AUXIN provides a means of inserting audio signals into the
modem output stage. Because this input is summed with the
transmitter output prior to the transmitter low pass filter and compromise equalizers, the AUXIN signal is sampled by a compensated sample-and-hold Circuit at a rate of 9600 samples-persecond. Any signal above 4800 Hz on the AUXIN line will be
aliased back into the passband as noise. One application for
AUXIN is to inject dual-tone mullifrequency (OTMF) touch-tone
signals for dialing, however, the source of these tones must be
well filtered to eliminate components above 4800 Hz. The input
impedance of AUXIN is 1K ohm. The gain from AUXIN to TXA
is - 0.4 dB ± 1 dB.
Overhead
1I0A
1I0A
1I0A
1I0A
1I0A
1I0A
IIOA
IIOA
7
5
9
31
15
28
23
29
9
8
2
3
4
5
6
7
RS3
RS2
RSI
RSO
IA
IA
IA
IA
30
8
27
10
13
14
15
16
CSO
IA
6
11
CSI
READ
WRITE
IRQ
IA
IA
IA
OB
18
1
38
10
12
1
Chip Select Sample Rate
Device
Chip Select Baud Rate Device
Read Enable
Write Enable
Interrupt Request
30
31
32
28
27
26
29
Data Clock
External Clock for Group 2
Request-to-Send
Clear-to-Send
Transmitter Data
Receiver Data
Received Line Signal Detector
24
25
Cable Select 1
Cable Select 2
2
32
}-
'"'
}
('
".,
Register Select (4 Bits)
Select Reg. 0 - F
C. V.24 INTERFACE:
Except for the power-on-reset signal POR, the overhead signals
are dc power or ground points. When the modem is initially
energized a signal called Power-On-Reset (POR) causes the
modem to assume a valid operational state. The modem drives
the POR pin to ground during the beginning of the POR
sequence. Approximately 10 ms after the low to high transilion
of the j5()R pin, the modem is ready for normal use. The POR
sequence is reiniliated anytime the + 5V supply drops below
+ 3.5V for more than 30 ms, or an external device drives the
POR pin low for at least 3 I-'s. When an external low input is
applied to the POR pin, the modem is ready for normal use
approximately 10 ms after the low input is removed. The
DCLK
XCLK
RTS
CTS
TXD
RXD
RLSD
OC
IB
IB
OC
IB
OC
OC
13
22
19
17
20
21
16
D. CABLE EQUALIZER:
CABSI
CABS2
IC
IC
33
34
"Pin 41 added for connector keYing, not for use as a ground.
3-98
R96F
9600 bps Facsimile Modem
Digital Interface Characteristics
Input/Output Type
Symbol
Parameter
V,H
Input Voltage, High
V,L
VOH
VOL
liN
10H
10L
IL
Ipu
Input Voltage, Low
Output Voltage, High
Output Voltage, Low
Input Current, Leakage
Output Current, High
Output Current, Low
Output Current, Leakage
Pull-up Current
(Short CircUit)
Capacitive Load
Capacitive Drive
Circu~ Type
CL
CD
Notes
1. I load
2. I load
3. I load
4. V,N =
Units
IA
IB
IC
V
2.0 min
2.0 min
2.0 min
V
V
V
p.A
mA
mA
p.A
p.A
0.8 max.
0.8 max.
08 max
pF
pF
= -100 p.A
= 1.6 mA
= -40 p.A
OA
OB
2.4 min 1
0.4 max 2
0.4 max
2
0.4 max
2
±2.5 max.
-0.1 max
1.6 max.
5
TTL
-240 max.
-10 min.
5
-240 max.
-10 min.
20
TIL
w/Pull-up
TIL
w/Pull-up
1/0 A
1/0 B
20 min
5.25 max
20 min
08 max.
24 mln. 3
04 max. 5
OC
1.6 max.
±10 max
0.8 max
24 min. 1
04 max. 2
±125 max.
1.6 max.
-240 max
-10 min.
100
TIL
-260 max.
-100 min
10
40
100
100
100
100
Open-Drain Open Drain
Open-Drain
3 State
w/Pull-up Transceiver w/Pull-up
5 I load = 0.36 mA
0.4 to 2.4 Vdc, Vcc = 5.25 Vdc
1:1 and 1:0. The eight bits in 1:1 are most significant. Writing
to 1:0 resets bit 1 :E:O to a 0 and starts the write cycle, which
ends by 1 :E:O returning to a 1. Bit RAMW (1 :0:0) must remain
set until the end of the cycle.
Anyone of the registers may be read or written on any host read
or write cycle, but all eight bits of that register are affected. In
order to read a single bit or a group of bits in a register, the host
processor must mask out unwanted data. When writing a single
bit or group of bits in a register the host processor must perform a read-modify-write operation. That is, the entire register
is read, the necessary bits are set or reset in the accumulator
of the host, then the original unmodified bits and the modified
bits are written back into the register of the interface memory.
RAM Access Codes
The RAM access codes defined in the following table allow the
host processor to read diagnostic information within the modem.
The access code stored in chip 1 (1:F) also selects the source
of data for the serial outputs EYEX and EYEY. Diagnostic data
is scaled as shown in the Diagnostic Data Scaling table.
RAM Data Access
RAM Access Codes
The user can access much of the data stored in the modem's
memories. This data is a useful tool in performing certain
diagnostic functions.
//
Node
--~
access registers are provided in the interface memory
to allow user access to various RAM locations within the modem.
The access code stored in O:F selects the source of data for the
RAM data registers in chip 0 (0:0 through 0:3). Similarly, the
access code stored in 1:F selects the source of data for registers
1:0 through 1:3. Reading is performed by storing the desired
access code in register O:F (or 1:F), performing a read of 0:0
(or 1 :0) to reset O:E:O (or 1:E:O), then waiting for O:E:O (or 1 :E:O)
to return to a one. The data may now be read from 0:3 through
0:0 (or 1:3-1:0).
1
2
3
4
5
Received Signal Samples
Demodulator Output
Low Pass Filter Output
Average Power
AGC Gain
6
7
8
9
Equalizer Input
Equalizer Tap Coefficients
Unrotated Equalizer Output
Rotated Equalizer Output
(Received POint-Eye Pattern)
Decision Points (Ideal)
Error Vector
Rotation Angle
Frequency Correction
Eye Quality Monitor (EQM)
G2 Baseband Signal
G2 AGC Gain
G2 AGC Slew Rate
G2 PLL Frequency Correction
G2 PLL Slew Rate
G2 BlacklWhlte Threshold
G2 Phase Limit"
10
11
12
13
14
15
16
17
18
19
20
21
Chip one also provides the capability to write data into RAM.
When bit RAMW is set to a one, reading is suspended and a
write cycle takes place once each time bit DA 1 (1' E:O) is reset
to zero.
Writing is performed by storing the desired access code in
register 1:F, waiting for bit DA 1 (1 :E:O) to be a 1, setting bit
RAMW (1 :0:0) to a 1, then storing sixteen bits of data in registers
"Added
3-99
Function
In
R5301-20
Access Chip Reg. No.
40
42
54
5C
01
0
0
0
0
0
2,3
0,1,2,3
0,1,2,3
2,3
2,3
40
01-20
61
22
1
1
1
1
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
62
63
00
A8
AB
C8
AD
AA
C2
FO
2A
F2
1
1
1
1
1
1
1
1
1
1
1
1
0,1,2,3
0,1,2,3
0,1
2,3
,2,3
2,3
2,3
2,3
2,3
,2,3
0,1
2,3
9600 bps Facsimile Modem
R96F
Diagnostic Data Scaling
Node
1
Parameter/Scallng
Received Signal Samples .. AID Sample Word (signed 16 blta, twos complement)
VEXT
.~ IA DEVICE
CHANNEL
ViNT
V1NT = (AID Sample Word)16 x ~ Volts
256
40 16
SIGNAL
PROCESSOR
VEXT .. V1NT + LOG 101 [ AGC Gain (dB) ]
I
2,3,
6,8,
9,10
20
AGC WORD
All B_band Signal Nodes (32 bHs, complex, twos complement)
Configuration
Point
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V.29/96DO
x,Y
V.29n200
x,Y
V.29/48DO & V.27/2400
x,Y
V.27/4800
x,Y
0000,2800
2800,0000
0000, 0800
0800,0000
0000,1800
1800,1800
1800,0000
1800, E800
0000, E800
E8OO. E800
E800, 0000
E8OO,1800
0000.2400
2400,0000
OOOO,DCOO
DCOO, 0000
OCOO, OCOO
OCOO, F400
F4OO, F400
F400, OCOO
0000, 1COO
lCOO, 0000
0000, E400
E400,OOOO
0000, 1COO
1400,1400
1COO, 0000
1400, ECOO
0000, E400
ECOO,ECOO
E400, 0000
ECOO.1400
0800,0800
0800, F800
F8OO, F800
F8OO, 0800
t
¢
@
~
.)
'"' @ @.(,)..
~~@
e
4
0
(.
@~
0
.
0
0
0
0
';'
-0-
-::-
';'
0
r,.
-0-
~
0
(.
noncondensing, or a wet bulb temperature up to 35°C, whichever is less.
Mechanical
Parameter
DIP Connector Version
Board Structure
Dimensions
Width
Length
Component Height
Weight (max.)
Pins
Length (max.)
Thickness
Ribbon Connector Version
Board Structure
Dimensions
Width
Length
Height
Weight (max.)
Lead Extrusion (max.)
SpeCification
Single PC board with a row of 20 pins and a row of 21 pins in a dual in-line pin configuration. Match
with Berg 65780 or equivalent.
2.0
3.5
0.2
2.6
in. (50.8 mm)
in. (88.9 mm)
in. (5.08 mm) above, 0.13 in. (3.30 mm) below.
oz. (73 g)
0.535 in. (13.6 mm) above.
0.025 in. (0.64 mm) square
Single PC board with single right angle header with 40 pins. Burndy FRS 40BS8P or equivalent
mating connector.
3.94 in. (100 mm)
2.56 in. (65 mm)
0.40 in. (10.2 mm)
2.6 oz. (73 g)
0.100 in. (2.54 mm)
3-110
9600 bps Facsimile Modem
R96F
0.156 ± 0.003 DIA (4 PL)
(3.96)
r r
3.437
(100)
~~
I
I
I 3.675
I (93.3)
m ••
ll
·j;
'"
,
N
Q
..
~
, 0.277
Ii
i~
------I
+(7,04)
0.125
~ 2.559
(3.18)
I
(65)
2.300
0.400
COMPONENT AREA
LE~~--/----D
..
~:0~2
- ---- --"
(1.6)
'
0.100]
[0.400 MAX
(2.54)
(10.16)
RIBBON CONNECTOR VERSION
0.043 DIA (2 PL)
(1.09)
0.125 DIA (2 PL)
(3.175)
0.200 MAX
0.535
~~. un ··1 m:'' ' 1
r
0.130 MAX ]
(3.3)
L
0.062
(1.6)
DIP CONNECTOR VERSION
R96F Dimensions and Pin Locations
3-111
R96MD
Integral Modems
'1'
Rockwell
R96MD
9600 bps Facsimile Modem
INTRODUCTION
FEATURES
The Rockwell R96MD IS a synchronous 9600 bits per second
(bps) modem. It is designed for operation over the public
switched telephone network (PSTN) through line terminations
provided by a data access arrangement (DAA).
• Compatible with:
- CCITT V.29, V.27 ter, T.30, V.21 Channel 2, TA, T.3
• Group 3 and Group 2 Facsimile
• Half-Duplex (2-Wire)
• Programmable Tone Detection
• Programmable Dual/Single Tone Generation
• Dynamic Range: - 47 dBm to 0 dBm
• Programmable Transmit Levels
• Diagnostic Capability
• Equalization:
- Automatic Adaptive
- Compromise Cable (Selectable)
• DTE Interface:
- Microprocessor Bus
- CCITT V.24 (RS-232-C Compatible)
• Small Size: 50.8 mm x 65.4 mm (2.0 in. x 2.575 in.)
• Low Power Consumption: 2 W (Typical)
• Transmit Output Level: + 5 dBm ± 1 dB
• TTL and CMOS Compatible
The modem satisfies the telecommunications requirements
specified in CCITT recommendations V.29, V.27 ter, T.30, T.4
and T.3. The R96MD can operate at speeds of 9600, 7200, 4800,
2400 and 300 bps. Employing advanced signal processing techniques, the R96MD can transmit and receive data even under
extremely poor line conditions.
The R96MD is designed for use in Group 3 facsimile machines
and is also compatible with Group 2 machines. User programmable features allow the modem operation to be tailored to support a wide range of functional requirements. The modem's small
size, low power consumption, serial/parallel host interface, and
dual in-line pin (DIP) interface simplify system design and allow
direct installation on the host module.
R96MD Modem
Document No. 29200N34
Data Sheet
(Preliminary)
3-112
Order No. MD34
February 1987
R96MD
9600 bps Facsimile Modem
TECHNICAL SPECIFICATIONS
EQUALIZERS
TRANSMITTER TONAL SIGNALING AND CARRIER
FREQUENCIES
The modem provides the following equalization functions which
can be used to improve performance when operating over poor
lines:
T.30 Tonal Signaling Frequencies
Cable Equalizers - Selectable compromise cable equalizers
are provided to optimize performance over different lengths of
non-loaded cable of 0.4 mm diameter.
Frequency
(Hz ±O.O10/0)
Function
Calling Tone (CNG)
Answer Tone (CED)
Group 2 Identification (C12)
Group 2 Command (GC2)
Group 2 Confirmation (CFR2, MCF2)
Line Conditioning Signal (LCS)
End of Message (EOM)
Procedure Interrupt (PIS)
1100
2100
1850
2100
1650
1100
1100
462
Automatic Adaptive Equalizer - An automatic adaptive equalizer is provided in the receiver cirCUit for V.27 and V.29 configurations. The equalizer can be configured as either a T or a T/2
equalizer.
TRANSMITTED DATA SPECTRUM
The transmitter spectrum is shaped by the following raised
cosine filter functions:
Carrier Frequencies
1. 1200 Baud.
2. 1600 Baud.
3. 2400 Baud.
Frequency
(Hz ±O.O10/0)
Function
T.3 Carrier (Group 2)
V.27 ter Carner
V.29 Carner
2100
1800
1700
Square root of 90 percent.
Square root of 50 percent.
Square root of 20 percent.
The out-of-band transmitter power limitations meet those specified by Part 68 of the FCC's Rules, and typically exceed the
requirements of foreign telephone regulatory bodies.
TONE GENERATION
SCRAMBLER/DESCRAMBLER
Under control of the host processor, the modem can generate
voice band tones up to 4800 Hz with a resolution of 0.15 Hz and
an accuracy of 0.01%. Tones over 3000 Hz are attenuated.
The modem incorporates a self-synchronizing scrambler/
descrambler. This facility is in accordance with either V.27 ter
or V.29 depending on the selected configuration.
RECEIVED SIGNAL FREQUENCY TOLERANCE
TONE DETECTION
The receiver circuit of the modem can adapt to received frequency error of up to ± 10 Hz with less than a 0.2 dB degradation in SER performance. Group 2 carrier recovery capture range
is 2100 ± 30 Hz. The Group 2 receiver operates properly when
the carrier is varied by ± 16 Hz at a 0.1 Hz per second rate.
In the 300 bps FSK receive configuration, the presence of tones
at preset frequencies is indicated by bits in the interface memory.
SIGNALING AND DATA RATES
Signaling/Data Rates
Specification
Baud Rate
(Symbols/Sec.)
Bits Per
Baud
V29
V 29
V.27
V.27
2400
2400
1600
1200
3
3
4
2
RECEIVE LEVEL
Data Rate
(BPS)
(±O.O10/0)
Symbol
Points
9600
7200
4800
2400
16
8
8
4
The modem receiver circuit satisfies all specified performance
requirements for received line signal levels from a dBm to
- 43 dBm. The received line signal level is measured at the
receiver analog input (RXA).
RECEIVE TIMING
In the receive state, the modem provides a Data Clock (DCLK)
output in the form of a square wave. The low to high transitions
of this output coincide with the center of received data bits. The
timing recovery circuit is capable of tracking a ± 0.01 % frequency error in the associated transmit timing source. DCLK
duty cycle is 50% ± 1%.
DATA ENCODING
The modem data encoding conforms to CCITT recommendations V.29 and V.27 ter.
3-113
I
I,
'I
!
'~
I
o
R96MD
9600 bps Facsimile Modem
TRANSMIT LEVEL
RESPONSE TIMES OF CLEAR-TO-SEND (CTS)
The transmitter output level defaults to + 5 dBm ± 1 dB at power
on. When using the default transmit level and driving a 600 ohm
load, the TXA output requires a 600 ohm series resistor to
provide - 1 dBm ± 1 dB to the load. The output level can be
programmed over a 10 dB range by performing a RAM write
operation.
The time between the off-to-on transition of RTS and the off-loon transition of CTS is dictated by the length of the training
sequence. Response time is 253 ms for V.29, 708 ms for V.27 ter
at 4800 bps, and 943 ms for V.27 ter at 2400 bps. In V.21 CTS
turns on in 14 ms or less. In Group 2 CTS turns on in 400 P.s
or less.
TRANSMIT TIMING
The time between the on-to-off transition of RTS and the on-tooff transition of CTS in the data state is a maximum of 2 baud
times for all configurations.
In the transmit state, the modem provides a Data Clock (OCLK)
output with the following characteristics:
1. Frequency. Selected data rate of 9600, 7200, 4800, 2400,
or 300 Hz (± 0.01 %). In Group 2, OCLK tracks an external
10368 Hz clock. If the external clock input (XCLK) is grounded
the Group 2 OCLK is 10372.7 Hz ±0.01%.
2. Duty Cycle. 50 ± 1%
RECEIVED LINE SIGNAL DETECTOR (RLSD)
Transmit Data (TXO) must be stable during the 1 microsecond
period immediately preceding and the 1 microsecond period
immediately following the rising edge of OCLK.
For either V.27 ter or V.29, RLSO turns on at the end of the training sequence. If training is not detected at the receiver, the RLSO
off-to-on response time is 15 ± 10 ms. The RLSO on-to-off
response time for V.27 is 10 ± 5 ms and for V.29 is 30 ± 9 ms.
Response times are measured with a signal at least 3 dB above
the actual RLSO on threshold or at least 5 dB below the actual
RLSO off threshold.
TURN-ON SEQUENCE
The RLSO on-to-off response time ensures that all valid dala
bits have appeared on RXO.
Two threshold options are provided:
1. Greater than - 43 dBm (RLSO on)
Less than - 48 dBm (RLSO off)
2. Greater than - 47 dBm (RLSO on)
Less than - 52 dBm (RLSO off)
A total of ten selectable turn-on sequences can be generated
by the modem, as defined in the following table:
Turn-On Sequences
RTS-CTS Turn-On Time
Specification
Echo Protector
Tone Disabled
Echo Protector
Tone Enabled
V.29
V.27 4800 bps
V.27 2400 bps
253 ms
708 ms
943 ms
438 ms
913 ms
1148 ms
V.21 300 bps
Group 2
0514 ms
05400 ~s
0514 ms
05400 ~s
NOTE
Performance may be at a reduced level when the received
signal is less than -43 dBm.
A minimum hysteresis action of 2 dB exists between the actual
off-to-on and on-to-off transition levels. The threshold levels and
hysteresis action are measured with an unmodulated 2100 Hz
tone applied to the receiver's audio input (RXA).
MODES OF OPERATION
TURN-OFF SEQUENCE
The modem operates in either a serial or a parallel mode.
For V.27 ter, the turn-off sequence consists of approximately
10 ms of remaining data and scrambled ones at 1200 baud or
approximately 7 ms of data and scrambled ones at 1600 baud
followed by a 20 ms period of no transmitted energy. For V.29,
the turn-off sequence consists of approximately 5 ms of remaining data and scrambled ones followed by a 20 ms period of no
transmitted energy. In V.21 the transmitter turns off within 7 ms
after RTS goes false. In Group 2 the transmitter turns off within
200 !'5 after RTS goes false.
SERIAL MODE
The serial mode uses standard V.24 (RS-232-C compatible) signals to transfer channel data. An optional USRT device (shown
in the Modem Functional Interconnect Diagram) illustrates this
capability.
PARALLEL MODE
The modem can transfer channel data eight bits at a time via
the microprocessor bus.
CLAMPING
The following clamps are provided with the modem:
1. Received Data (RXD). RXO is clamped to a constant mark
(1) whenever RLSO is off.
2. Received Line Signal Detector (RLSD). RLSO is clamped off
(squelched) during the time when RTS is on.
3. Extended Squelch. Optionally, RLSO remains clamped off for
130 ms after the turn-off sequence.
MODE SELECTION
Selection of either the serial or parallel mode of operation is by
means of a control bit. To enable the parallel mode, the control
bit must be set 10 a 1. The modem automatically defaults to the
serial mode at power-on. In either mode the modem is configured
by the host processor via the microprocessor bus.
3-114
R96MD
9600 bps Facsimile Modem
1"'-------.,
CABS2
I
I
RTS
~
CTS
~
USRT
(OPTIONAL)
TXD
I
DCLK
.....
RLSD
I
L---
1
CABS1
,..,
RXD
I
R96MD
MODEM
J
-
POWER
SUPPLY
GND
READ
i
-12V
I'
,..,
WRITE
he
+12V
+5V
I
~
DATA BUS (8)
HOST
PROCESSOR
(DTE)
DECODER
.... CS (2L
TXA
Di
ADDRESS BUS (4)
RSi
RXA
~
LINE
INTERFACE
TELEPHONE
LINE
CSi
POR
IRQ
~
+5
v
J
~
Modem Functional Interconnect Diagram
INTERFACE CHARACTERISTICS
V.24 Interface
The modem interface comprises both hardware and software
circuits. Hardware circuits are assigned to specific pins in a
40-pin dual in·line pin (DIP) connector. Software circuits are
assigned to specific bits in a 32-byte interface memory.
Seven hardware circuits provide timing, data and control signals
for implementing a serial interface compatible with CCITT
Recommendation V.24. These signals interface directly with cir·
cuits using TTL logic levels (0, + 5 volt). These TTL levels are
suitable for driving the short wire lengths or printed circuitry
normally found within stand·alone modem enclosures or equip·
ment cabinets.
HARDWARE CIRCUITS
Signal names and descriptions of the hardware circuits, including
the microprocessor interface, are listed in the Modem Hardware
Circuits table; the table column titled 'Type' refers to designations found in the Digital or Analog Interface Characteristics.
In applications where the modem is operated in parallel data
mode only (i.e., where the V.24 signals are unused), all V.24
pins may remain unterminated.
Microprocessor Interface
Cable Equalizers
Sixteen hardware circuits provide address (RSO-RS3), data
(00-07), control (CS, READ and WRITE) and interrupt (IRQ)
signals for implementing a parallel interface compatible with an
8080 microprocessor. (Refer to the Microprocessor Interface
Timing Waveforms figure and Microprocessor Interface Timing
Requirements table.) With the addition of a few external logic
gates, the interface can be made compatible with a wide variety
of microprocessors such as 6500, 6800, or 68000.
Modems may be connected by direct wiring, such as leased
telephone cable or through the public switched telephone network, by means of a data access arrangement. In either case,
the modem analog signal is carried by copper wire cabling for
at least some part of its route. The cable characteristics shape
the passband response so that the lower frequencies of the passband (300 Hz to 1700 Hz) are attenuated less than the higher
frequencies (1700 Hz to 3300 Hz). The longer the cable the more
pronounced the effect.
The microprocessor interface allows a host microprocessor to
change modem configuration, read or write channel data as well
as diagnostic data, and supervise modem operation by means
of software strappable control bits and modem status bits. The
significance of the control and status bits and methods of data
interchange are discussed in the Software Circuits section.
To minimize the impact of this undesired passband shaping, a
compromise equalizer with more attenuation at lower frequencies than at higher frequencies can be placed in series with the
analog signal. The modem includes three such equalizers
designed to compensate for cable distortion.
3-115
o
R96MD
9600 bps Facsimile Modem
Cable Equalizer Selection
CABS2
CABS1
Length of O.4mm Diameter Cable
0
0
1
1
0
1
0
1
0.0
1.8 km
3.6 km
7.2 km
•
•
•
•
•
No extended squelch
Higher receive threshold
Interrupts disabled
RAM Access S = 00
RAM Access B = 22
This configuration is suitable for performing high speed data
transfer on the PSTN with the serial data port selected as the
input and output point for data terminal equipment (DTE).
Analog Signals
Modem Hardware Circuits
Two analog signals, TXA and RXA, provide the interface point
for telephone company audio circuits.
Name
Type
Pin No.
Description
A. OVERHEAD:
The TXA line is an output suitable for driving an audio
transformer or data access arrangement for connection to either
leased lines or the PSTN. The output structure of TXA is a low
impedance amplifier in series with an internal 604 ohm ± 1%
resistor to match a standard telephone load of 600 ohms.
Ground
+5 volts
+ 12 volts
-12 volts
POR
GNO
PWR
PWR
PWR
1I0B
17,18
33,34
21
19
39
Power Supply Return
+ 5 volt supply
+ 12 volt supply
- 12 volt supply
Power-on-reset
B. MICROPROCESSOR INTERFACE:
RXA is an input to the receiver from an audio transformer or data
access arrangement. The input impedance is nominally
60K ohms but a factory select resistor allows a variance of 23 0Al.
The RXA input must be shunted by an external resistor in order
to match a 600 ohm source. A 604 ohm ± 1% resistor is
salisfactory.
07
06
05
04
03
02
01
DO
Some form of transient protection for TXA and RXA is recommended when operating directly into a transformer. This protection may be back-to-back zener diodes across the transformer
or a varistor across the transformer.
Overhead
Except for the power-on-reset signal POR, the overhead signals
are dc power or ground points. When the modem is initially
energized a Signal called Power-On-Reset (POR) causes the
modem to assume a valid operational state. The modem drives
pin 39 to ground during the beginning of the POR sequence.
Approximately 10 ms after the low to high transition of pin 39,
the modem is ready for normal use. The POR sequence is
reinitiated anytime the + SV supply drops below + 3.SV for more
than 30 ms, or an external device drives pin 39 low for at least
3 ""s. When an external low input IS applied to pin 39, the modem
is ready for normal use approximately 10 ms after the low input
is removed. Pin 39 IS not driven low by the modem when the
POR sequence is initiated externally. In all cases, the POR
sequence requires SO ms to 3S0 ms to complete. The POR
sequence leaves the modem configures as follows:
• V.29/9600 bps
• T/2 equalizer
• Serial mode
• Training enabled
• Echo protector lone enabled
1I0A
IIOA
IIOA
IIOA
IIOA
1I0A
IIOA
IIOA
9
8
3
4
5
6
7
RS3
RS2
RSl
RSO
IA
IA
IA
IA
13
14
15
16
CSO
CSl
READ
WRITE
IRQ
IA
IA
IA
IA
OB
11
38
2
} 0..
}
'"'.'~I
Register Select (4 Bits)
Select Reg. 0 - F
12
1
Chip Select Sample Rate Device
Chip Select Baud Rate Device
Read Enable
Write Enable
Interrupt Request
30
31
32
28
27
26
29
Data Clock
External Clock for Group 2
Request-to-Send
Clear-to-Send
Transmitter Data
Receiver Data
Received Line Signal Detector
10
C. V.24 INTERFACE:
DCLK
XCLK
RTS
CTS
TXO
RXO
RLSO
OC
IB
IB
OC
IB
OC
OC
D. CABLE EQUALIZER:
CABS1
CABS2
IB
IB
24
25
Cable Select 1
Cable Select 2
23
22
Transmitter Analog Output
Receiver Analog Input
E. ANALOG SIGNALS
TXA
RXA
AA
AB
Pm 35 IS removed for keying connector.
3-116
--
R96MD
9600 bps Facsimile Modem
Microprocessor Interface Timing Requirements
WRITE
READ
Min
TCS
Data Access time after Read
TDA
Data hold time after Read
CSI, RSI hold time after
Read or Write
Max
Units
30
-
ns
-
140
ns
i;
TDH
10
50
ns
II
TCH
10
ns
!,
Write data setup time
TWOS
75
ns
Write data hold time
TWDH
10
II
i
TWR
75
-
Characteristic
CSi
(i = 0,1)
RSi
(i
Symbol
CSI, RSi setup time prior
to Read or Write
= 0-3)
Write strobe pulse width
ns
ns
II
i
I
II
Analog Interface Characteristics
Type
Characteristics
TXA
AA
The transmitter output is a low impedance
operational amplifier output. In order to
match to 600 ohms, an external 604 ohm
series resistor IS required,
RXA
AB
The receiver mput impedance is
46.4K ohms ± 230/0,
Name
READ
Di
(i = 0-7)
Microprocessor Interface Timing Diagram
Digital Interface Characteristics
I nput/Output Type
Symbol
Parameter
V,H
Input Voltage, High
V,L
V OH
VOL
liN
IOH
IOL
IL
Ipu
Input Voltage, Low
Output Voltage, High
Output Voltage, Low
Input Current, Leakage
Output Current, High
Output Current, Low
Output Current, Leakage
Pull-up Current
(Short CirCUit)
Capacitive Load
CapaCitive Drive
CirCUit Type
CL
CD
Notes
1. I load = -100 ~A
2. I load = 16 rnA
3. I load = -40 pA
4. V,N = 04 to 2,4 Vdc, Vee
Units
IA
18
V
2,0 min
20 min,
V
V
V
pA
rnA
rnA
0,8 max,
0,8 max,
2.4 mm,'
0.4 max,2
-0,1 max.
1.6 max.
~A
~A
pF
pF
08
OC
5
TTL
0,4 max,>
16 max
± 10 max.
1.6 max
-240 max.
-10 mm.
5
TTL
w/Pull-up
= 0.36
rnA
Vde
3-117
I/O A
I/O 8
20 mm,
5,25 max,
2,0 min,
0,8 max,
2.4 min,3
0,4 max'"
0,8 max,
2.4 min,
0.4 max,>
±12.5 max,'
,
0.4 max,>
±25 max,
5. I load
= 5.25
OA
-240 max.
-10 mm,
100
100
100
10
100
-260 max
-100 min.
40
100
TTL
Open-Dram
Open Dram
w/Pull-up
3 State
Transceiver
Open-Dram
w/Pull-up
D
R96MD
9600 bps Facsimile Modem
These bits are written into interface memory registers 0:3, 0:2,
0:1 and 0:0, or 1:3,1:2,1:1 and 1:0, in that order. Registers 3 and
2 contain the most and least significant bytes of XRAM data,
respectively, while registers 1 and 0 contain the most and least
significant bytes of YRAM data respectively.
SOFTWARE CIRCUITS
The modem includes two signal processor chips. Each of these
chips contains 16 registers to which an external (host) microprocessor has access. Although these registers are within the
modem, they may be addressed as part of the host processor's
memory space. The host may read data out of or write data into
these registers. The registers are referred to as interface memory.
Registers in chip 0 update at the modem sample rate (9600 bps).
Registers in chip 1 update at the selected baud rate except in
Group 2 and FSK configurations when they update at the sample
rate.
When set to a one, bit 0:5:5 (RAMWS) or bit 1:D:0 (RAMWB)
causes the modem to suspend transfer of RAM data to the interface memory, and instead, to transfer data from interface memory
to RAM in chip 0 or in chip 1, respectively. When writing into
the RAM, only 16 bits are transferred, not 32 bits as for a read
operation. The 16 bits written in XRAM or YRAM come from
registers 1 and 0, with register 1 being the most significant byte.
Selection of XRAM or YRAM for the destination is by means of
the code stored in the RAM Access B bits of register 1:F for
chip 1, or by means of 0:5:4 (RAE) and O:F (RAM Access S) for
chip O. When bit 1:F:7 or 0:5:4 is set to one, the XRAM is selected.
When 1:F:7 or 0:5:4 equals zero, YRAM is selected.
When information in these registers is being discussed, the format Y:Z:O is used. The chip is specified by Y(O or 1), the register
by Z(O-F), and the bit by 0(0-7, 0 = LSB). A bit is considered to
be "on" when set to a 1.
Status/Control Bits
When the host processor reads or writes register 0, the modem
data available bit O:E:O or 1:E:0 (MDAi) is reset to zero. When
the modem reads or writes register 0, MDAi is set to a one. When
set to a one by the host, bit 0:E:2 or 1:E:1 (lEi) enables the MDAi
bit to cause an IRO interrupt when set. While the IRO line is
driven to a TTL low level by the modem, bit 0:E:7 or 1:E:7 (lAi)
goes to a one.
Modem operation is affected by a number of software control
inputs. These inputs are written into registers within the interface memory via the host microprocessor bus. Modem operation is monitored by various software flags that are read from
interface memory via the host microprocessor bus. All status and
control bits are defined in the Interface Memory table. Bits
designated by a ' - ' are reserved for modem use only and must
not be changed by the host.
RAM Access Codes
The RAM access codes defined in the following table allow the
host processor to read diagnostic information within the modem.
This information is scaled as shown in the Diagnostic Data
Scaling table.
Anyone of the registers may be read or written on any host read
or write cycle, but all eight bits of that register are affected. In
order to read a single bit or a group of bits in a register, the host
processor must mask out unwanted data. When writing a single
bit or group of bits in a register the host processor must perform
a read-modify-write operation. That is, the entire register is read,
the necessary bits are set or reset in the accumulator of the host,
then the original unmodified bits and the modified bits are written back into the register of the interface memory.
RAM Access Codes
Node
RAM Data Access
The user can access much of the data stored in the modem's
memories. This data is a useful tool in performing certain
diagnostic functions.
The modem contains 128 words of random access memory
(RAM). Each word is 32-bits wide. Because the modem is
optimized for performing complex arithmetic, the RAM words are
frequently used for storing complex numbers. Therefore, each
word is organized into a real part (16 bits) and an imaginary part
(16-bits) that can be accessed independently. The portion of the
word that normally holds the real value is referred to as XRAM.
The portion that normally holds the imaginary value is referred
to as YRAM. The entire contents of XRAM and YRAM may be
read by the host processor via the microprocessor interface.
1
2
3
4
5
6
7
8
9
10
Received Signal Samples
Demodulator Output
Low Pass Filter Output
Average Power
AGC Gain
Tone 1 Frequency
Tone 1 Level
Tone 2 Frequency
Tone 2 Level
Output Level
11
12
13
14
Equalizer Input
Equalizer Tap CoeffiCients
Unrotated Equalizer Output
Rotated Equalizer Output
(Received Point-Eye Pattern)
Decision Points (Ideal)
Error Vector
Rotation Angle
Frequency Correction
Eye Quality Monitor (EQM)
G2 Baseband Signal
G2 AGC Gain
G2 AGC Slew Rate
G2 PLL Frequency Correction
G2 PLL Slew Rate
G2 BlacklWhlte Threshold
G2 Phase Limit
Checksum
15
16
17
18
19
20
21
22
23
24
25
26
27
The interface memory acts as an intermediary during these host
to signal processor RAM data exchanges. The RAM address to
be read from or written to is determined by the contents of register
O:F (RAM ACCESS S) or 1:F (RAM ACCESS B). The RAM Access
Codes table lists access codes for storage in registers O:F or 1:F
and the corresponding diagnostic functions. Each RAM word
transferred to the interface memory is 32 bits long.
Function
Read
Access RAE Chip Reg. No.
40
42
54
5C
3C
71
72
71
72
4C
X
X
X
X
X
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
2,3
0,1,2,3
0,1,2,3
2,3
2,3
2,3
2,3
0,1
0,1
0,1
40
01-20
61
22
N.A.
N.A.
N.A.
N.A.
1
1
1
1
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
62
63
00
A8
AB
C8
AD
AA
C2
FO
2A
F2
2D
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
1
1
1
1
1
1
1
1
1
1
1
1
1
0,1,2,3
0,1,2,3
0,1
2,3
2,3
2,3
2,3
2,3
2,3
2,3
0,1
2,3
2,3
RAE = X is don't care since this location should only be read
from, and not written to, by the host. N.A. is not
applicable since RAE is not used in chip one.
3-118
9600 bps Facsimile Modem
R96MD
Diagnostic Data Scaling
Parameter/Scaling
Node
1
Received Signal Samples
= AID Sample Word (signed 16 bits, twos complement)
V,NT
VEXT
-.
IA DEVICE
CHANNEL
i
2,3,
11, 13
14, 15
INT
(AID Sample Word)'6 x ~ Volts
(40),6
256
VEXT -- VINT ":". LOG 10-, [ AGC Gain (dB) ]
20
AGCWORD
All Baseband Signal Nodes (32 bits, complex, twos complement)
Configuration
Point
1
2
3
4
5
6
7
B
9
10
11
12
13
14
15
16
V.29/9600
x,V
V.2917200
x,V
V.29/4800 & V.27/2400
x,V
V.27/4800
x,V
0000,2BOO
2BOO, 0000
OOOO,DBOO
DBOO, 0000
0000, 1800
1BOO, 1BOO
1BOO, 0000
1BOO, EBOO
0000, EBOO
EBOO, EBOO
EBOO,OOOO
EBOO,1BOO
OBOO,OBOO
OBOO, FBOO
FBOO, FBOO
FBOO,OBOO
0000,2400
2400,0000
0000, DCOO
DCOO, 0000
OCOO,OCOO
OCOO, F400
F400, F400
F400,OCOO
0000,1FOO
1FOO, 0000
0000, E100
E100, 0000
0000, 1FOO
1600,1600
1FOO, 0000
1600, EAOO
0000, E100
EAOO, EAOO
E100, 0000
EAOO, 1600
.
(.)
e
.. e e
e e
(.)
.
e
,
0
0
.
.
,
0
0
0)
0
,
-0-
0
V.29/9600 BPS
4
=
V
SIGNAL
PROCESSOR
~
,
V.2917200 BPS
V,29/4800 BPS and
V.27/2400 BPS
Average Power (16 bits, unsigned)
Typical value: OB89'6 (corresponding to 0 dBm)
Post·AGC Average Power in dBm
=
10 Log (Average Power Word)'6
889,6
Pre·AGC Average Power in dBm = Post-AGC Avg. Power in dBm - AGC gain in dB
3-119
0
B-
---00
.
0
V.27/4800 BPS
R96MD
9600 bps Facsimile Modem
Diagnostic Data Scaling (continued)
Node
5
Parameter/Scaling
AGC Gain (16 bits, unsigned)
Range:
OFCO'6 to 7FFF'6 for LRTH
0640'6 to 7FFF'6 for LRTH
= 0 (- 43 dBm Threshold)
= I (- 47 dBm Threshold)
= 50 _ (AGC Gain Word)'6
AGC Gain In dB
x 0,098
40'6
6,8
Tone 1 and 2 Frequency (16 bits, unsigned)
N = 6.8267 (Frequency in Hz)
Convert N to hexadecimal then store in RAM,
7,9
Tone 1 and Tone 2 Level
Calculate the power of each tone independently by using the equation for Output Number given at node 10, Convert these
numbers to hexadecimal then store in RAM, Total power transmitted in tone configuration is the result of both tone I power and
tone 2 power,
10
Output level (16 bits, unsigned)
= 27573,6 [10(PoJ20)]
= output power in dBm With series 600 ohm
Output Number
Po
resistor Into 600 ohm load,
Convert Output Number to hexadecimal and store in RAM,
12
Equalizer l'Itps (32 bits, complex, twos complement)
Node 12 is not a Single pOint but is actually a set of RAM locations containing adaptive equalizer tap coefficients, In Y.29 configuration, access codes 01 through 20 hexadecimal represent 32 complex taps, In Y.27 configuration, access codes 01 through
10 hexadecimal represent 16 complex taps, since the equalizer for V,27 is only half as long as the equalizer for Y.29,
The equalizer tap access codes can be useful for restoring modem operation after loss of equalization without requesting a training sequence from the transmitter, Since the equalizer tap coefficients are complex numbers they require two write operations per
tap, one for the real part and one for the imaginary part, When writing the real part, the access codes 01 through 20 must be
changed to 81 through AO, When writing the imaginary part, or when reading the complex number, the access codes 01 through
20 are correct,
Registers 1:1 and 1:0 hold the most and least significant bytes, respectively, of the 16 bits during a write operallon,
16
Error Vector (32 bits, complex, twos complement)
Represents the difference between the received point (P2) and the nearest Ideal point (PI),
Configuration
Bit Rate
(BPS)
Registers 3 and 2
Real Error
Registers I and 0
Imag, Error
Magnitude
."jRe 2 + 1m2
Y.29
V,29
V,29
V,27
V,27
9600
7200
4800
4800
2400
"
1\
\
::I
..
~
c
\
3000
1\
..
2000
ii
1000
;:
I
,\
::I
>
.."
:I:
I
.01
\
.1
r---.r-o
to10
100
Seconds to Stabilize AGC for -55 OBM to 0 OBM Step
3-121
D
R96MD
9600 bps Facsimile Modem
Diagnostic Data Scaling (continued)
Node
23
Parameter/Scaling
"Group 2 PLL Frequancy Correction (16 bits, twos complement)
Range:
FC6A'6 to 0346,6 representing
Frequency correction in Hz
24
± 140 Hz
= Frequency correction
number (0.167)
"Group 2 PLL Slew Rate
Represents gain of first order term in phase locked loop.
Range:
0010,6 to 7000,6 for stable operation
Directly proportional to PLL slew rate
25
"Group 2 Black/White Threshold (16 bits, unsigned)
Default value: (7800),6
...
III
a: 6
:I
I
I
CD
a: 5
J 1
W
:.:D.
UC 4
CW
"'13
CD w 3
I
I I
I
7
8
0
0
7
6
0
0
Lt. ...
Ow 2
a: C
Will
CD ... 1
:;;w
I
I
I
I
7
0
0
0
6
F
0
0
C
0
0
NOTE:
1.100 WHITE PIXELS SENT FOLLOWED BY 4 BLACK
PIXELS SENT.
2. RESULTS OBTAINED AT 0 DBM, NO COMPROMISE
EQUALIZERS IN BACK TO BACK CONNECTION.
:I~
ZD.
7
2
0
0
6
6
A
0
0
6
8
0
0
THRESHOLD VALUE (HEXADECIMAL)
26
"Group 2 Phase Limit (16 bits, twos complement)
When phase error exceeds this limit, PLL updating is suspended.
Default: 5000,6 representing
Phase limit
= 180· -
[
±67.5 degrees
(Phase Limit)'6
x 180· ]
(7FFF)'6
Once phasing is acquired, the limits may be narrowed to improve Immunity to phase hits.
27
Checksum (16-bit unsigned)
ROM checksum number determined by reviSIon level.
"See Rockwell Application Note, R96F Modem Recommended Receive Sequence for Group 2 Facsimile (Order No. 655, Rev. 3).
3-122
R96MD
9600 bps Facsimile Modem
Interface Memory Chip 0 (CSO)
t::;:
7
6
5
4
2
3
Interface Memory Chip 1 (CS1)
1
0
Register
F
PDM
lAO
0
-
-
B
A
-
9
8
7
6
6
5
IAl
-
-
4
2
3
RAM ACCESS S
-
-
-
-
-
-
-
-
IRAMWS
RAE
EPT
-
F
-
SETUP
lEO
-
MDAO
E
-
-
-
-
-
0
-
-
SOExr
-
-
-
-
-
12
lRTH
-
-
C
-
B
FR3
FR2
FR1
-
-
-
A
9
-
-
-
-
IE1
-
-
-
-
0
-
MDA1
RAM DATA XSl; FREOl
1
RAM DATA YSM
1
RAM DATA YBM
0
RAM DATA YSl; TRANSCEIVER DATA
0
RAM DATA YBl
-
RTS TDIS
-
-
CONFIGURATION
RAM DATA XSM; FREOM
7
6
5
4
3
2
1
-
-
FED
-
-
-
3-123
- - - - - ---
-
---
-
-
-
-
P2DET
-
-
G2FGC
CDET
-
RAM DATA XBl
7
6
5
4
Bit
= Reserved (modem use only).
-
-
RAM DATAXBM
17-
0
Bit
PNDET
FRT RAMWB
-
-
-
3
2
-
:/'::
1
RAM ACCESS B
8
7
6
5
4
3
2
5
4
-
7
Register
E
C
~
= Reserved (modem use only).
3
2
1
0
R96MD
9600 bps Facsimile Modem
Interface Memory Definitions
Mnemonic
Name
Memory
location
Description
CDET
Carrier Detector
1:7:0
The zero sta~DET indicates passband energy is being detected, and a training sequence IS
not present. CDET goes to zero at the start of the data state, and returns to one at the end of the
received signal. CDET activates up to 1 baud time before RLSD and deactivates within 2 baud
times after RlSD.
(None)
Configuration
0:4:0-7
The host processor configures the modem by writing a control code into the configuration register
in the interface memory space. (See SETUP)
Configuration Control Codes
Control codes for the eight available modem configurations are:
Configuration
V.29 9600'
V.29 7200
V.274800
V.272400
FSK
Group 2
Tone Transmit
DTMF Transmit
Configuration Code (HEX)
14
12
OA
09
20
40
80
81
• Default at POR.
Configuration Definitions
1. V.29. When a V.29 configuration has been selected, the modem operates as specified in
CCITI Recommendation V.29.
2. V.27. When a V.27 configuratIOn has been selected, the modem operates as specified in CCITI
Recommendation V.27 ter.
3. FSK. The modem operates as a CCITI T.3O compatible 300 bps FSK modem having
characteristics of the CCITI V.21 channel 2 modulation system.
4. Group 2. The modem operates as a CCITI T.3 compatible AM modem. This configuration
permits transmission to and reception from Group 2 facsimile apparatus. A carrier frequency ot
2100 Hz is used. A black signal is transmitted as no carrier. The phase of the carrier
representing white is reversed alter each transition through black.
When in the receive state, the modem recovers the carrier of the remote transmitting modem to
perform a coherent demodulation of the incoming signal. This technique allows a baseband of
3400 Hz to be recovered. The recovered baseband signal is available on the microprocessor
bus.
The baseband signal is converted to black or white by comparing the received signal level with
a presat threshold number. This number may be changed by the user.
Receiver data is presented to the RXD output at a rate of 10368 samples per second. The user
should strobe the data on the rising edge of the data clock (DCll<). A logical 1 level (high
voltage) represents white. A logical 0 level (low voltage) represents black.
S. Tone Transmit. In this configuration, activating signal RTS causes the modem to transmit a
tone at a singla frequency specified by the user. Two registers In the host interface memory
space contain the frequency code. The most significant bits are specified in the FREQM
register (0:3). The least significant bits are specified in the FREQl register (0:2). The least
significant bit represents 0.146486 Hz ±0.01%. The frequency generated is:
f = 0.146486 (256 FREQM + FREQl) Hz ±O.oI%.
6. DTMF Transmit. In thiS configuration, activating RTS causes the modem to transmit two tones at
frequencies and output levels specified by the user. By uSing the RAM Data Access routines,
the user can program the tones and levels.
3-124
R96MD
9600 bps Facsimile Modem
Interface Memory Definitions (Continued)
Mnemonic
Name
Memory
Location
Description
EPT
Echo Protector
Tone
0:5:3
If EPT is a one, an unmodulated carrier is transmitted for 185 ms followed by 20 ms of no
transmitted energy at the beginning of the training sequence. This oplion is available in both the
V.27 and V.29 configurations, although it is not specified In the CCITT V.29 recommendation.
FED
Fast Energy
Detector
1:5:6
The zero state of FED indicates energy is present above the receiver threshold in the passband.
FED is not used for Group 2 Facsimile.
(None)
FREOUFREOM
0:2:0-7,
0:3:0-7
The host processor conveys tone generation data to the transmitter by writing a 16-bit data word to
the FREOl and FREOM registers in the Interface memory space, as shown below.
FREQM Register (0:3)
IBit:
I
IData Word: I
7
2'5
I
I
I
6
2"
I
5
2'3
I
I
I
4
2'2
3
I
2"
I
I
2
2'0
I
1
I
29
I
2'
I
0
28
I
20
I
I
I
FREQL Register (0:2)
I. Data
Bit:
I
Word: .
7
27
5
6
I
I
26
25
4
I
3
23
I
24
I
2
22
1
0
I
The frequency number (N) determines the frequency (F) as follows:
F = (0.146486) (N) Hz ± 0.01%.
Hexadecimal frequency numbers (FREOM, FREQl) for commonly generated tones are given below:
FRT
Freeze Taps
FR1 - FR3
Frequency 1,2,3
Frequency (Hz)
FREQM
FREQL
462
1100
1650
1850
2100
OC
10
2C
31
52
55
00
55
00
38
When FRT is a one, adaptive equalization taps are prevented from changing.
1:B:5,6,7
The one state of FR1, FR2 or FR3 indicates reception of the respective tonal frequency when the
modem is configured for FSK. The default frequencies for FR1, FR2 and FR3 are:
Bit
Frequency (Hz)
FR1
FR2
FR3
2100
1100
462
G2FGC
Group 2 Fast
Gain Control
1:C:0
The one state of G2FGC selects a fast AGC rate (8.6 times standard) in Group 2 FaCSimile.
IA1
Interrupt Active
(One)
1:E:7
IA1 is a one when Chip 1 is driving IRO to zero volts.
lAO
Interrupt Active
(Zero)
0:E:7
lAO is a one when Chip 0 is driving IRO to zero volts.
lEO
Interrupt Enable
(Zero)
0:E:2
The one state of lEO causes the IRQ output to be low when the DAD bit is a one.
IE1
Interrupt Enable
(One)
1:E:2
The one state of IE1 causes the IRO output to be low when the DA1 bit is a one.
lATH
Lower Receive
Threshold
0:5:0
The one state of lATH lowers the receiver turn-on threshold from - 43 dBm to - 47 dBm. (See
SETUP)
MDAO
Modem Data
Available (Zero)
O:E:O
MDAO goes to one when the modem reads or writes register 0:0. MDAO goes to zero when the
host processor reads or writes register 0:0. MDAO is used for parallel mode as well as for
diagnostic data retrieval.
3-125
R96MD
9600 bps Facsimile Modem
Interface Memory Definitions (Continued)
Mnemonic
Memory
Location
Name
Description
MDAI
Modem Data
Available (One)
I:E:O
MDAI goes to one when the modem writes register 1:0. MOAt goes to zero when the host
processor reads register 1:0.
PDM
Parallel Data
Mode
0:F:7
The one state of PDM places the modem in the parallel mode and inhIbits the reading of Chip
diagnostic data.
PNDET
Period 'N'
Detector
1:7:6
The zero state of PNDET Indicates a PN sequence has been detected. PNDET sets to a one at the
end of the PN sequence.
P2DET
Period '2'
Detector
1:4:2
The zero state of P2DET indicates a P2 sequence has been detected. P2DET sets to a one at the
start of the PN sequence.
(None)
RAM Access B
I:F:O-7
Contains the RAM access code used in reading or writing RAM locations in Chip 1 (baud rate
device).
(None)
RAM Access S
0:F:0-6
Contains the RAM access code used in reading or writing RAM locations in Chip
device).
a
a (sample rate
(None)
RAM Data XBL
1:2:0-7
Least SignifIcant byte of 16-bit word x used in reading RAM locations in Chip I (baud rate device).
(None)
RAM Data XBM
1:3:0-7
Most sIgnificant byte of 16-bit word x used in reading RAM locations in Chip 1 (baud rate device).
(None)
RAM Data XSL
0:2:0-7
Least significant byte of 16-bit word x used in reading RAM locations in ChIp
device).
a (sample rate
(None)
RAM Data XSM
0:3:0-7
Most significant byte of 16-bit word x used in reading RAM locations in ChIp
device).
a (sample rate
(None)
RAM Data YBL
1:0:0-7
Least significant byte of 16-bit word y used In reading or writing RAM locations in Chip 1 (baud
rate device). See DAI.
(None)
RAM Data YBM
1:1:0-7
Most significant byte of 16-bit word y used in reading or writing RAM locations in Chip t (baud
rate device).
(None)
RAM Data YSL
0:0:0-7
Least significant byte of 16-bit word y used in reading or writing RAM locations in Chip a (sample
rate devIce). Shared by parallel data mode for presenting channel data to the host microprocessor
bus. See Transceiver Data and DAO.
(None)
RAM Data YSM
0:1:0-7
Most significant byte of 16-bit word y used in reading or wrlllng RAM locations in Chip
rate device).
RAE
RAM Address
Extension
0:5:4
This bit is an extension of RAM Access S when RAMWS is a one. During a RAM write to Chip 0,
when RAE is a 1 the XRAM is selected and when RAE is a a the YRAM is selected.
RAMWB
RAM Write Chip I
(baud rate
device)
1:0·0
RAMWB is set to a one by the host processor when performing diagnostic writes to the baud rate
device (Chip 1). RAMWB is set to a zero by the host when reading RAM diagnostic data from
Chipl.
RAMWS
RAM Write Chip
(sample rate
devIce)
0:5:5
RAMWS is set to a one by the host processor when performing diagnostic writes to the sample
rate device (Chip 0). RAMWS IS set to a zero by the host when reading RAM diagnostIc data from
Chip O.
RTS
Request-to-Send
0:5:7
The one state of RTS begins a transmIt sequence. The modem will continue to transmit until RTS
is turned off, and the turn-off sequence has been completed. RTS parallels the operation of the
hardware RTS control input. These inputs are "ORed" by the rnodem.
SETUP
Setup
0:E:3
The one state of SETUP causes the modem to reconfigure to the control word in the configuration
register, and to assume the optIons specified for equalizer (0:5:1) and threshold (0:5:0). SETUP
returns to zero when acted on by the modem. The time required for the SETUP bit to cause a
change depends on the current state of the modem. The following table lists worst case delays.
a
Current
State
V.21
DELAY
14 ms
G2
400
~s
3-126
High Speed
Receiver
2 BAUD
a (sample
High Speed Transmitter
2 BAUD + TURNOFF Sequence + Training (if
applicable) + SQUELCH (if applicable)
R96MD
9600 bps Facsimile Modem
Interface Memory Definitions (Continued)
Memory
Mnemonic
Name
Description
Location
SOEXT
Squelch Extend
0'5:2
The one state of SOEXT Inhibits reception of signals for 130 ms after the turn-off sequence.
TDIS
Training Disable
0:5:6
If TOIS IS a one In the receive state, the modem IS prevented from entering the training phase. If
TOIS IS a one prior to RTS going on, the generation of a training sequence is prevented at the
start of transmission.
(None)
Transceiver Data
0:00-7
In receive parallel data mode, the modem presents eight bits of channel data In register 0:0 for
reading by the host microprocessor. After the eight bits have been accumulated In register O:C
they are transferred to 0:0 and bit O:E:O goes to a one. When the hosl reads 0:0, bit O:E:O resets
to a zero. The first bit of received data IS not necessarily located in bit 0:0:0. The host must frame
the received data by searching for message sync characters. Bit O:E:O sets at one eighth the bit
rate in parallel data mode rather than at the sample rate (9600 Hz) as it does when reading RAM
locations.
In transmit parallel data mode the host stores data at location 0:0. This action causes bit O:E:O to
reset to a O. When the modem transfers the data from 0:0 to 0:2 bit O.E:O sets to a 1. The data is
serially transmitted from register 0:2 least significant bit first. Received data is shifted into register
O:C from MSB toward LSB.
T2
T/2 Equalizer
Select
0:5:1
If T2 is a one, an adaptive equalizer with two taps per baud is used. If T2 is a zero, an adaptive
equalizer with one tap per baud is used. The number of taps remains the same for both cases.
(See SETUP)
PERFORMANCE
At 4800 bps (V.27 ter), the modem exhibits a bit error rate of
10- 6 or less with a signal-to-noise ratio of 19 dB in the
presence of 15° peak-to-peak phase jitter at 60 Hz.
Whether functioning in V.27 ter or V.29 configuration, the modem
provides the user with unexcelled high performance.
TYPICAL BIT ERROR RATES
At 7200 bps (V.29), the modem exhibits a bit error rate of 10- 6
or less with a signal-to-noise ratio of 25 dB in the presence of
12° peak-to-peak phase jitter at 300 Hz.
The Bit Error Rate (BER) performance of the modem is specified
for a test configuration conforming to that specified in eelD
Recommendation V.56. Bit error rates are measured at a
received line signal level of - 20 dBm as illustrated.
At 9600 bps, the modem exhibits a bit error rate of 10- 6 or less
with a signal-to-noise ratio of 23 dB in the presence of 10° peakto-peak phase jitter at 60 Hz. The modem exhibits a bit error
rate of 10- 5 or less with a signal-to-noise ratio of 23 dB in the
presence of 20° peak-to-peak phase jitter at 30 Hz.
TYPICAL PHASE JITTER
At 2400 bps, the modem exhibits a bit error rate of 10 - 6 or less
with a signal-to-noise ratio of 12.5 dB in the presence of 15°
peak-to-peak ph'ase jitter at 150 Hz or with a signal-to-noise ratio
of 15 dB in the presence of 30° peak-to-peak phase jitter at
120 Hz (scrambler inserted).
An example of the BER performance capabilities is given in the
following diagrams:
3-127
9600 bps Facsimile Modem
R96MD
V27.2400
\
F~K
10- 3
\
V27,4800
V29,7200
/
10- 3
le(
II:
II:
0
II:
II:
W
I-
iii
0
w
e(
II:
II:
0
II:
II:
W
I-
iii
10- 5
\
\
10- 6
5
10
15
\
10- 6
25
20
0
Signal to Noise Ratio in dB
5
15
r----
-
Typical Bit Error Rate
(Unconditioned 3002 Line, T Equalizer Level - 20 dBm)
IMPAIRMENT
SOURCE
BRADLEY 2A
AND 2B
-
ATTENUATOR
HP 3500
I
I
MODEM
TEST SET
PHOENIX
5000
25
20
r-
3002
LINE
SIMULATOR
SEG FA-1445
\
I
10
Signal to Noise Ratio in dB
Typical Bit ErrQr Rate
(Back-to-Back, T Equalizer, Level - 20 dBm)
MODEM
TRANSMITTER
I
I
l-
1\
\
10- 5
V29,9600
10-'
\
\
w
I
K
I
\
10-'
r
/V29,9600
V27,4800
V29,7200
V27,2400
LEVEL
METER
HP 3552A
MODEM
RECEIVER
I
NOTE
SIGNAL AND NOISE ARE MEASURED WITH 3 KHZ FLAT WEIGHTING.
BER Performance Test Set-up
3-128
R96MD
9600 bps Facsimile Modem
GENERAL SPECIFICATIONS
Power
Voltage
Tolerance
Current (Typical) @ 25°C
Current (Max) @ O°C
+5 Vdc
+ 12 Vdc
-12 Vdc
±5%
±5%
±5%
350 mA
5 mA
30 mA
<500 mA
< 10 mA
< 50 mA
Note: All voltages must have npple :50.1 volts peak-to-peak.
Environmental
Parameter
Specification
Temperature
Operating
Storage
Relative Humidity
O°C to +60°C (32°F to 140°F)
-40°C to + BO°C (-40°F to 176°F) (Stored in heat sealed antistatic bag and shipping container)
Up to 90% noncondensing, or a wet bulb temperature up to 35°C, whichever is less
Mechanical
Parameter
Specification
Board Structure
Single PC board with a row of 20 pins and a row of 20 pins in a dual-in-line pin configuration.
Mates with Berg 657BO or equivalent.
Dimensions
Width
Length
Component Height
Weight (max.)
Pins
Length (max.)
Thickness
2.0 in. (50.B mm)
2.575 in. (65.4 mm)
0.30 In. (7.6 mm) above, 0.13 in. (330 mm) below
2.6 oz. (73 g)
0.650 in. (16.5 mm) above (tin), 0.535 in. (13.6 mm) above (gold)
0.025 in (0.64 mm) square
0.025
(0.64)
0.098 DIA (2 PL) ___..:::Jtt=±t::==~"-',
(2.5)
.1
/
BETWEEN
PINS
1.850
(47)
~
"
Qae
sa PINS (41 PL)
2.~00
(50.8)
1.800 I
(45.7) ~ BETWEEN
",
+
MOUNTING
00000000000000 -+
HOLES
01:~ ~~O
(1.9)
r
2.575
(65.4)
(2.54)
0.535
(i3.6)
0.300 MAX
-.-----L
1T '
r - -, -
1
-1- __ y~6~ ,~.\
~~62RE0~,
(1.6)
'=*=r
t
0.1;!Q MAX
(3.3)
COMPONENT AREA
R96MD Dimensions and Pin Locations
3-129
R144HD
Integral Modems
'1'
Rockwell
R144HD
14400 bps Half-Duplex Modem
INTRODUCTION
FEATURES
The Rockwell R144HD is a synchronous 14400 bits per second
(bps) half-duplex modem. It is designed for operation over the
public switched telephone network (PSTN) through line terminations provided by a data access arrangement (DAA).
• Compatibility:
- CCITT V.33, V.29, V.27 ter, T.30, V.21 Channel 2, T.4, T.3
- Trellis Coded Modulation (TCM) at 14400, 12000, 9600
and 7200 bps
• Group 3 and Group 2 Facsimile
• Half-Duplex (2-Wire)
• Programmable Tone Detection
• Programmable Dual/Single Tone Generation.
• DTMF Tone Generation
• Dynamic Range: -43 dBm to -6 dBm
• Diagnostic Capability
• Eq ualization:
- Automatic Adaptive
- Compromise Cable and Link (Selectable)
• DTE Interface:
- Microprocessor Bus
- CCITT V.24 (RS-232-C Compatible)
• Transmit Output Level: + 5 dBm ± 1 dBm
• Small Size: 100 mm x 82 mm (3.94 in. x 3.23 in.)
• Low Power Consumption: 2.5W (Typical)
• TTL and CMOS Compatible
The modem satisfies the telecommunications requirements
specified in CCITT recommendations V.33, V.29, V.27 ter, T.30,
T.4 and T.3. The R144HD can operate at speeds of 14400,
12000, 9600, 7200, 4800, 2400 and 300 bps.
The Rl44HD is designed for use in Group 3 facsimile machines
and is also compatible with Group 2 machines. User programmable features allow the modem operation to be tailored to support a wide range of functional requirements. The modem's small
size, low power consumption, serial/parallel host interface, and
standard connector simplify system design and allow installation
in a compact enclosure.
R144HD Modem
Document No. 29200N33
Data Sheet
(Preliminary)
3-130
Order No. MD33
Rev.1, February 1987
R144HD
14400 bps Half-Duplex Modem
TECHNICAL SPECIFICATIONS
EQUALIZERS
TRANSMITTER TONAL SIGNALING AND CARRIER
FREQUENCIES
The R144HD provides the following equalization functions which
can be used to improve performance when operating over poor
lines:
T.30 Tonal Signaling Frequencies
Function
Frequency
(Hz ±O.O1%)
Cable Equalizers - Selectable compromise cable equalizers
are provided to optimize performance over different lengths of
non-loaded cable of 0.4 mm diameter.
1100
2100
1850
2100
1650
1100
1100
462
1080
462
Link Amplitude Equalizer - The selectable compromise amplitude equalizer may be inserted into the transmit and/or receive
paths under control of the transmit amplitude equalizer enable
and the receive amplitude equalizer enable bits in the interface
memory. The amplitude select bit controls which of two amplitude equalizers is selected.
Calling Tone (CNG)
Answer Tone (CED)
Group 2 IdentificatIOn (C12)
Group 2 Command (GC2)
Group 2 ConftrmatlOn (CFR2, MCF2)
Line Conditioning Signal (LCS)
End of Message (EOM)
Procedure Interrupt (PIS)
MF1 Confirmation (CFR)
MF1 Procedure Interrupt (PIS)
Automatic Adaptive Equalizer - An automatic adaptive equalizer is provided in the receiver circuit for high speed data
configurations.
Carrier Frequencies
TRANSMITTED DATA SPECTRUM
Frequency
(Hz ±O.O1%)
Function
T.3 (Group 2)
V.27 ter. V.33, TCM96, TCM72
V.29, (V 33, TCM96, TCM72)1
If neither the link amplitude nor cable equalizer is enabled, the
transmitter spectrum is shaped by the following raised cosine
filter functions:
2100
1800
1700
1. 1200 Baud. Square root of 90 percent.
2. 1600 Baud. Square root of 50 percent.
3. 2400 Baud. Square root of 20 percent.
The out-of-band transmitter power limitations meet those specified by Part 68 of the FCC's Rules, and typically exceed the
requirements of foreign telephone regulatory bodies.
I
1. Selectable option
TONE GENERATION
Under control of the host processor, the R144HD can generate
voice band tones up to 4800 Hz with a resolution of O. 15 Hz and
an accuracy of 0.01 %. Tones over 3000 Hz are attenuated.
SCRAMBLER/DESCRAMBLER
The R144HD incorporates a self-synchronizing scrambler!
descrambler. This facility is in accordance with either V.27 ter,
V.29, or V.33 depending on the selected configuration.
TONE DETECTION
In the 300 bps FSK receive configuration, the presence of tones
at preset frequencies is indicated by bits in the interface memory.
RECEIVED SIGNAL FREQUENCY TOLERANCE
The receiver circuit of the R144HD can adapt to received frequency error of up to ± 10Hz with less than a 0.2 dB degradation in BER performance. Group 2 carrier recovery capture range
is 2100 ± 30 Hz. The Group 2 receiver operates properly when
the carrier is varied by ± 16 Hz at a 0.1 Hz per second rate.
SIGNALING AND DATA RATES
Signaling/Data Rates
Specification
Baud Rate
(Symbols/Sec.)
Bits Per
Baud
V.33
V.33
TCM96
TCM72
V.29
V.29
V.29
V.27
V 27
2400
2400
2400
2400
2400
2400
2400
1600
1200
6
5
4
3
4
3
2
3
I
2
Data Rate
(BPS)
(±O.O1%)
Symbol
Points
14400
12000
9600
7200
9600
7200
4800
4800
2400
128
64
32
16
16
8
4
8
4
RECEIVE LEVEL
The receiver circuit of the R144HD satisfies all specified performance requirements for received line signal levels from -6 dBm
to - 43 dBm. The received line signal level is measured at the
receiver analog input (RXA).
RECEIVE TIMING
In the receive state, the R144HD provides a Data Clock (DCLK)
output in the form of a square wave. The low to high transitions
of this output coincide with the center of received data bits. The
timing recovery circuit is capable of tracking a ± 0.01 % frequency error in the associated transmit timing source. DCLK
duty cycle is 50% ±1%.
DATA ENCODING
The R144HD data encoding conforms to CCITT recommendations V.33, V.32 (TCM96, TCM72), V.29, and V.27 ter.
3-131
14400 bps Half-Duplex Modem
R144HD
TRANSMIT LEVEL
RESPONSE TIMES OF CLEAR·TO·SEND (CTS)
The transmitter output level defaults to + 5 dBm ± 1 dB at power
on. When using the default transmit level and driving a 600 ohm
load, the TXA output requires a 600 ohm series resistor to
provide -1 dBm ± 1 dB to the load. The output level can be
programmed by perlorming a RAM write operation.
The time between the off-te-on transition of RTS and the off-toon transition of CTS is dictated by the length of the training
sequence. Response time is 1393 ms for V.33 and TCM96,
253 ms for V.29, 708 ms for V.27 ter at 4800 bps, and 943 ms
for V.27 ter at 2400 bps. In V.21 CTS turns on in 14 ms or less.
In Group 2 CTS turns on in 400 P.s or less.
TRANSMIT TIMING
The time between the on-to-off transition of RTS and the on-tooff transition of CTS in the data state is a maximum of 2 baud
times for all configurations.
In the transmit state, the R144HD provides a Data Clock (DCLK)
output with the following characteristics:
1. Frequency. Selected data rate of 14400, 12000, 9600, 7200,
4800, 2400, or 300 Hz (± 0.01 %). In Group 2, DCLK tracks
an external 10368 Hz clock. If the external clock input (XCLK)
is grounded the Group 2 DCLK is 10372.7 Hz ±O.ot%.
2. Duty Cycle. 50 ± 1%
RECEIVED LINE SIGNAL DETECTOR (RLSD)
For V.33, TCM96, V.29 or V.27 ter, RLSO turns on at the end of
the training sequence. If training is not detected at the receiver,
the RLSO off-te-on response time is 15 ± 10 ms. The RLSD
on-to-off response time for V.27 is 10 ± 5 ms, V.29 is 30 ± 9 ms,
and V.33 and TCM96 is 40 ± 10 ms. Response times are
measured with a signal at least 3 dB above the actual RLSD
on threshold or at least 5 dB below the actual RLSD off threshold.
Transmit Data (TXD) must be stable during the 1 microsecond
periods immediately preceding and following the rising edge of
DCLK.
TURN·ON SEQUENCE
The RLSO on-te-off response time ensures that all valid data
bits have appeared on RXD. The threshold levels are:
The selectable turn-on sequences of the RI44HD are defined
in the following table:
Greater than -43 dBm (RLSD on)
Less than -48 dBm (RLSD off)
Turn·On Sequences
RTS-CTS Turn-On Time
Specification
V.33
TCM96
TCM72
V.29
V.27 4800
V.27 2400
V.27 4800
V.27 2400
bps
bps
Short
Short
Echo Protector
Tone Disabled
1393
1393
1393
253
708
943
50
67
V.21 300 bps
Group 2
ms
ms
ms
ms
ms
ms
,,;;14 ms
,,;;400 I'S
NOTE
Echo Protector
Tone Enabled
1598
1598
1598
438
913
1148
255
272
Perlormance may be at a reduced level when the received
signal is less than - 43 dBm.
ms
ms
ms
ms
ms
ms
A minimum hysteresis action of 2 dB exists between the actual
off-to-on and on-te-off transition levels. The threshold levels and
hysteresis action are measured with an unmodulated 2100 Hz
tone applied to the receiver's audio input (RXA).
MODES OF OPERATION
,,;;14 ms
,,;;4001's
The R144HD is capable of being operated in either a serial or
a parallel mode of operation.
TURN·OFF SEQUENCE
SERIAL MODE
For V.27 ter, the turn-off sequence consists of approximately
10 ms of remaining data and scrambled ones at 1200 baud or
approximately 7 ms of data and scrambled ones at 1600 baud
followed by a 20 ms period of no transmitted energy. For V.33,
TCM96, and V.29, the turn-off sequence consists of approximately 5 ms of remaining data and scrambled l's followed by
a 20 ms period of no transmitted energy. In V.21 the transmitter
turns off within 7 ms after RTS goes false. In Group 2 the
transmitter turns off within 200 J'Seconds after RTS goes false.
The serial mode uses standard V.24 (RS-232-C compatible) signals to transfer channel data. An optional USRT device (shown
in the R144HO Functional Interconnect Diagram) illustrates this
capability.
PARALLEL MODE
The R144HD has the capability of transferring channel data
eight bits at a time via the microprocessor bus.
CLAMPING
The following clamps are provided with the RI44HD:
1. Received Data (RXD). RXD is clamped to a constant mark
(1) whenever RLSD is off.
2. Received Line Signal Detector (RLSD). RLSD is clamped off
(squelched) during the time when RTS is on.
3. Extended Squelch. Optionally, RLSD remains clamped off for
130 ms after the turn-off sequence.
MODE SELECTION
Selection of either the serial or parallel mode of operation is by
means of a control bit. To enable the parallel mode, the control
bit must be set to a 1. The modem automatically defaults to the
serial mode at power-on. In either mode the R144HD is configured by the host processor via the microprocessor bus.
3-132
14400 bps Half-Duplex Modem
R144HD
1"'--------,I
USRT
(OPTIONAL)
I ..
!,..
RTS
(
CTS
J
xf ty
~
TXD
EYEX
DCLK
:...
EYEY
RLSD
EYESYNC
.
RXD
h
I
I'
Qcop~ :
CABSl
I
I
L---
CABS2
EYECLK
+12V
R144HD
MODEM
J
EYE
PATTERN
GENERATOR
+5V
POWER
SUPPLY
GND
READ
-12V
,..,
WRITE
i
I
~
DATA BUS (8)
HOST
PROCESSOR
(DTE)
ADDRESS BUS (4)
TXA
Di
LINE
INTERFACE
RSi
RXA
DECODER ..... CS (2).
TELEPHONE
LINE
CSi
POR
IRQ
(
+5
.A
J
R144HD Functional Interconnect Diagram
INTERFACE CRITERIA
R144HD Hardware Circuits (Continued)
Name
The modem interface comprises both hardware and software
circuits. Hardware circuits are assigned to specific pins in two
rows. One row contains 20 pins (1-20) and the other row con·
tains 21 pins (21-41). Software circuits are assigned to specific
bits in a 32·byte interface memory.
Type
Pin No.
Description
B. MICROPROCESSOR INTERFACE;
IIOA
IIOA
IIOA
IIOA
IIOA
IIOA
IIOA
IIOA
15
28
23
29
RS3
RS2
RSI
RSO
IA
IA
IA
IA
27
10
CSO
CSI
READ
WRITE
IRQ
IA
IA
IA
IA
OB
6
18
1
2
32
Chip Select Sample Rate DeVice
Chip Select Baud Rate Device
Read Enable
Write Enable
Interrupt Request
13
22
19
17
20
21
16
Data Clock
External Clock for Group II
Request·to·Send
Clear·to·Send
Transmitter Data
Receiver Data
Received line Signal Detector
D7
D6
D5
D4
D3
D2
Dl
DO
HARDWARE CIRCUITS
Signal names and descriptions of the hardware circuits, including
the microprocessor interface, are listed in the R144HD Hard·
ware Circuits table; the table column titled 'Type' refers to
designations found in the Hardware Circuit Characteristics. The
microprocessor interface is designed to be directly compatible
with an 8080 microprocessor. With the addition of a few external
logic gates, it can be made compatible with 6500, 6800, or 68000
microprocessors.
j}
3~ }
Data Bus (8 Bits)
Register Select (4 Bits)
Select Reg. 0 - F
C. V.24 INTERFACE;
DCLK
XCLK
RTS
CTS
TXD
RXD
RLSD
R144HD Hardware Supervisory Circuits
Name
IType I Pin No. I
Description
A. OVERHEAD;
Ground
+5 volts
+ 12 volts
-12 volts
POR
GND
PWR
PWR
PWR
I/OB
14,39
3, 4
26
37
36
Power Supply Return
+ 5 volt supply
+ 12 volt supply
- 12 volt supply
Power·on·reset
OC
IB
IB
OC
IB
OC
OC
D. CABLE EQUALIZER:
CABSI
CABS2
3·133
IB
IB
33
34
Cable Select 1
Cable Select 2
II
R144HD
14400 bps Half-Duplex Modem
R144HD Hardware Circuits (Continued)
Name
Type
Pin No.
Critical Timing Requirements
Characteristic
E. ANALOG SIGNALS:
AA
TXA
RXA
AS
38
40
Transmitter Analog Output
Receiver Analog Input
F. DIAGNOSTIC:
EYEX
EYEY
EYECLK
EYESYNC
OC
OC
OA
OA
24
25
11
12
Symbol
Min
CSI, RSi setup time prior
to Read or Write
TCS
Data Access time after Read
TDA
Data hold time after Read
TDH
Description
Eye Pattern
Eye Pattern
Eye Pattern
Eye Pattern
Signal
Data - X Axis
Data - Y Axis
Clock
SynchroniZing
CSI, RSi hold time after
Read or Write
Units
30
-
NS
-
140
NS
10
50
NS
NS
NS
TCH
10
Write data setup time
TWOS
75
Write data hold time
TWDH
10
-
TWR
75
-
Write strobe pulse width
Eye Pattern Generation
Max
NS
NS
Cable Equalizer Selection
The four hardware diagnostic circuits, identified in the preceding
table, allow the user to generate and display an eye pattern.
Circuits EYEX and EYEY serially present eye pattern data for
the horizontal and vertical display inputs respectively. The 8-bit
data words are shifted out most significant bit first, clocked by
the rising edge of the EYECLK output. The EYESYNC output
is provided for word synchronization. The falling edge of
EYESYNC may be used to transfer the 8-bit word from the shift
register to a holding register. Digital to analog conversion can
then be performed for driving the X and Y inputs of an
oscilloscope.
Cable Equalizer Selection
CABS 2
CABS 1
0
0
0.0
1
1.8 km
3.6 km
7.2 km
a
1
1
Length of O.4mm Diameter Cable
0
1
Digital Interface Characteristics
The digital interface characteristics are listed in the table on the
following page.
Microprocessor Timing
Analog Interface Characteristics
Analog Interface Characteristics
Name
Type
Characteristics
TXA
AA
The transmitter output is a low impedance
operational amplifier output. In order to
match to 600 ohms, an external 604 ohm
series resistor is required.
RXA
AS
The receiver input impedance is
6DK ohms ± 23%.
SOFTWARE CIRCUITS
The R144HD comprises three signal processor chips. Two of
these chips contain 16 registers to which an external (host) microprocessor has access. Although these registers are within the
modem, they may be addressed as part of the host processor's
memory space. The host may read data out of or write data into
these registers. The registers are referred to as interface memory.
Register in chip 0 update at the modem sample rate (9600 bps).
Registers in chip 1 update at the selected baud rate.
When information in these registers is being discussed, the format Y:Z:O is used. The chip is specified by yeO or 1), the register
by Z(O-F), and the bit by 0(0-7, 0 = LSB). A bit is considered to
be "on" when set to a 1.
Microprocessor Interface Timing Diagram
3-134
Ii
14400 bps Half-Duplex Modem
R144HD
Digital Interface Characteristics
Input/Output Type
Symbol
Parameter
V,H
Input Voltage, High
V'L
VOH
VOL
liN
10H
10L
IL
Ipu
Input Voltage, Low
Output Voltage, High
Output Voltage, Low
Input Current, Leakage
Output Current, High
Output Current, Low
Output Current, Leakage
Pull-up Current
(Short Circuit)
Capacitive Load
Capacitive Drive
Circuit Type
CL
Co
Notes
1. I load = -100 pA
2. I load = 1.6 rnA
3. !Ioad = -40 pA
4. V,N = 0.4 to 2.4 Vdc, Vee
Units
IA
IB
V
2.0 min.
2.0 min.
V
V
V
pA
mA
mA
pA
O.S max.
O.S max.
2.4 min.'
0.4 max. 2
OB
OC
-0.1 max
1.6 max.
5
TTL
0.4 max 2
1.6 max.
±10 max.
1.6 max.
5. I load
-240 max.
-10 min.
5
TTL
w/Pull-up
I/O A
I/O B
2.0 min.
5.25 max.
2.0 min.
O.S max.
2.4 min."
0.4 max. S
,
0.4 max. 2
±2.5 max
~A
pF
pF
OA
O.S max.
2.4 min.
0.4 max. 2
± 12.5 max.-
-240 max.
-10 min.
100
100
100
10
100
-260 max.
-100 min.
40
100
TTL
Open-Drain
Open Drain
w/Pull-up
3 State
Transceiver
Open-Drain
w/Pull-up
= 0.36 rnA
= 5.25 Vdc
I'
II
D
I
Status/Control Bits
These bits are written into interface memory registers 0:3, 0:2,
0:1 and 0:0, or 1:3,1:2, 1:1 and 1:0, in that order. Registers 3 and
2 contain the most and least significant bytes of XRAM data,
respectively, while registers 1 and 0 contain the most and least
significant bytes of YRAM data respectively.
The operation of the R144HD is affected by a number of software control inputs. These inputs are written into registers within
the interface memory via the host microprocessor bus. Modem
operation is monitored by various software flags that are read
from interface memory via the host microprocessor bus. All status
and control bits are defined in the Interface Memory table. Bits
designated by a ' - ' are reserved for modem use only and must
not be changed by the host.
When set to a one, bit 0:5:5 (RAMWS) or bit I:D:O (RAMWB)
causes the modem to suspend transfer of RAM data to the interface memory, and instead, to transfer data from interface memory
to RAM in chip 0 or in chip I, respectively. When writing into
the RAM, only 16 bits are transferred, not 32.bits as for a read
operation. The 16 bits written in XRAM or YRAM come from
registers 1 and 0, with register 1 being the most significant byte.
Selection of XRAM or YRAM for the destination is by means of
the code stored in the RAM Access B bits of register I:F for
chip I, or by means of 0:5:4 (RAE) for chip O. When bit I:F:7 or
0:5:4 is set to one, the XRAM is selected. When I:F:7 or 0:5:4
equals zero, YRAM is selected.
RAM Data Access
The R144HD provides the user with access to much of the data
stored in the modem's memories. This data is a useful tool in
performing certain diagnostic functions.
The modem contains 128 words of random access memory
(RAM). Each word is 32-bits wide. Because the modem is
optimized for performing complex arithmetic, the RAM words are
frequently used for storing complex numbers. Therefore, each
word is organized into a real part (16 bits) and an imaginary part
(16-bits) that can be accessed independently. The portion of the
word that normally holds the real value is referred to as XRAM.
The portion that normally holds the imaginary value is referred
to as YRAM. The entire contents of XRAM and YRAM may be
read by the host processor via the microprocessor interface.
When the host processor reads or writes register 0, the modem
data available bit O:E:O or I:E:O (MDAi) is reset to zero. When
the modem reads or writes register 0, MDAi is set to a one. When
set to a one by the host, bit 0:E:2 or I:E:l (lEi) enables the MDAi
bit to cause an IRQ interrupt when set. While the IRQ line is
driven to a TTL low level by the modem, bit 0:E:7 or I:E:7 (IAi)
goes to a one.
The default access codes are 22 for I:F and 00 for O:F.
The interface memory acts as an intermediary during these host
to signal processor RAM data exchanges. The RAM address to
be read from or written to is determined by the contents of register
O:F (RAM ACCESS S) or I:F (RAM ACCESS B). The R144HD
RAM Access Codes table lists access codes for storage in
registers O:F or I:F and the corresponding diagnostic functions.
The R144HD Diagnostic Data Scaling table provides scaling information for these diagnostic functions. Each RAM word
transferred to the interface memory is 32 bits long.
Data in registers 1:3 and 1:1 are presented serially on EYEX and
EYEY, respectively.
RAM Access Codes
The RAM access codes defined in the following table allow the
host processor to read diagnostic information within the modem.
3-135
R144HD
14400 bps Half-Duplex Modem
RAM Access Codes
Node
Function
Received Signal Samples
Demodulator Output
Low Pass Filter Output
Average Energy
AGC Gain Word
Tone 1 Frequency
Tone 1 Level
Tone 2 Frequency
Tone 2 Level
Output Level
Receiver Sensitivity
Receiver Hysteresis
Checksum
TX Level Attenuation
Equalizer Input
Equalizer Tap Coefficients
Unrotated Equalizer Output
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Ram Access Codes (Continued)
Read
Access RAE Chip Reg. No.
40
52
54
5C
3C
7D
7E
7D
7E
4C
X
X
X
X
X
1
0
0
0
0
1
0
0
2,3
0,1,2,3
0,1,2,3
2,3
2,3
2,3
2,3
0,1
0,1
0,1
0
0
0
0
0
0
0
Function
18
Rotated Equalizer Output
(Received Point-Eye Pattern)
Decision Points (Ideal)
Error Vector
Rotation Angle
Frequency Correction
EQM
Group II Base Band Signal
G2 AGC Gain Word
G2 AGC Slew Rate
G2 PLL Frequency Correction
G2 PLL Slew Rate
G2 BlacklWhite Threshold
G2 Phase Limit
19
20
21
22
23
24
25
26
27
28
29
30
I
0
0
0,1
3F
3E
40
01·20
61
0,1
0
1
2,3
0,1,2,3
0,1,2,3
0,1,2,3
1
1
1
Read
Access RAE Chip Reg. No.
Node
22
1
0,1,2,3
62
63
00
A8
AB
C8
AD
1
1
1
1
1
1
1
1
1
1
1
1
0,1,2,3
0,1,2,3
0,1
2,3
2,3
2,3
2,3
AA
C2
FO
2A
F2
2,3
2,3
I "
J
0,1
2,3
RAE = X is don't care since this location should only be read
from, and not written to, by the host.
--.J
R144HD Interface Memory Chip 1 (CS1)
R144HD Interface Memory Chip 0 (CSO)
b::
F
PDM
E
lAO
0
-
7
6
5
4
2
3
1
':;;
0
C
-
B
-
9
-
8
-
7
-
A
-
6
-
-
-
-
-
SETUP
-
-
-
-
-
-
-
-
-
-
-
-
EPT
SOExr
-
-
lEO
-
-
4
CONFIGURATION
3
RAM DATA XSM; FREOM
4
2
3
1
0
-
MDAI
E
IAt
-
-
-
-
D
TLE
RLE
J3L
-
-
-
C
-
-
-
B
FR3
FR2
FRI
-
A
-
-
9
-
-
-
2
RAM DATA XSL; FREOL
RAM DATA YSM
0
RAM DATA YSL; TRANSCEIVER DATA
7
6
5
4
3
2
RAM ACCESS B
MDAO
1
-
-8
-
-
7
6
-
Pf
-
lEI
-
-
-
-.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PNDET
FED
-
/:
0
Bit
= Reserved (modem use only).
-
3-136
_.
-
-
P2DET
FAT RAMWB
G2FGC
CDET
-
RAM DATA XBM
RAM DATA XBL
RAM DATA YBM
0
Bit
-
5
-
1
7-
6
F
RAM ACCESS S
-
RTS mls RAMWS RAE
5
7
Register
Register
RAM DATA YBL
7
6
I5
4
= Reserved (modern use only).
3
2
1
0
R144HD
14400 bps Half-Duplex Modem
R144HD Interface Memory Definitions
Mnemonic
Name
Memory
Location
Description
CDET
Carner Detector
1"70
The zero state of CDET Indicates passband energy IS being detected, and a training sequence IS
not present CDET goes to zero at the start of the data state, and returns to one at the end of the
received signal. CDET activates up to 1 baud time before RLSD and deactivates within 2 baud
times after RLSD
(None)
Configuralion
0"4:0-7
The host processor configures the R144HD by wriling a control code Into the configuration
register In the Interface memory space. (See SETUP)
Configuration Control Codes
Control codes for the R144HD configuralions are:
Configuration
Configuration Code (HEX)
V.33 14400'
V.33 12000
TCM969600
TCM727200
V.33 14400 (1700 Hz)'
V.33 12000 (1700 Hz)'
TCM96 9600 (1700 Hz)'
TCM72 7200 (1700 Hz)'
V.29 9600
V 29 7200
V.29 4800 Long
V.27 4800 Long
V.27 2400
V.27 4800 Short
V.27 2400 Short
FSK
Group 2 and MF1
Single Tone Transmit
Dual Tone Transmit
DTMF Transmit
31
32
34
38
71
72
74
78
14
12
11
OA
09
8A
89
20
40
80
81
82
, Default at POR.
The 1700 Hz carrier frequency is non-standard
2
Configuration Definitions
1. V.33. When a V.33 configuration has been selected, the modem operates as specified in
CCITT Recommendation V.33.
2 TCM96 and TCM72. When configuralion TCM96 or TCM72 IS selected, the training sequence
IS defined by V 33 and the modulation trellis coded is defined by V.32 (32 or 16 point
constellatIOn)
3. V.29. When a V.29 configuration has been selected, the modem operates as specified In CCITT
Recommendation V.29.
4. V.27. When a V.27 configuration has been selected, the modem operates as specified in CCITT
Recommendation V.27 ter.
5. FSK. The modem operates as a CCITT T.30 compatible 300 bps FSK modem having
characteristics of the CCITT V.21 channel 2 modulation system.
6. Group 2. The modem operates as a CCITT T.3 compatible AM modem. This permits trans-
mission to and reception from Group 2 facsimile apparatus. A carner frequency of 2100 Hz is
used. A black signal IS transmitted as no carrier. The phase of the carner representing white IS
reversed after each transition through black.
When In the receive state, the R144HD recovers the carrier of the remote transmitting modem
to perform a coherent demodulatIOn of the Incoming signal. This allows a baseband of 3400 Hz
to be recovered. The recovered baseband signal IS available on the microprocessor bus.
The baseband signal IS converted to black or white by comparing the received signal level with
a preset threshold number. ThiS number may be changed by the user.
3-137
!
I
D
R144HD
14400 bps Half-Duplex Modem
R144HD Interface Memory Definitions (Continued)
Memory
Mnemonic
Name
location
Description
Receiver data is presented to the RXD output at a rate of 10368 samples per second. The user
should strobe the data on the rising edge of the data clock (DCLK). A logical 1 level (high voltage) represents white. A logical 0 level (low voltage) represents black.
7. Single Tone Transmit. In this configuration, activating signal RTS causes the modem to transmit
a tone at a single frequency specified by the user. Two registers in the host interface memory
space contain the frequency code. The most significant bits are specified in the FREOM
register (0:3). The least significant bits are specified in the FREOL register (0:2). The least significant bit represents 0.146486 Hz to.Q1%. The frequency generated is: f = 0.146486
(256 FREOM + FREOL) Hz t 0.01%.
8. Dual Tone Transmit. In this configuration, activating RTS causes the modem to transmit two
tones at frequencies and outpU1 levels specified by the user. By using the RAM Data Access
routines, the user can program the tones and levels.
9. DTMF Transmit. In this configuration, when the hex value of a DTMF digit is stored in register
0:0, a DTMF tone will be transmitted if RTS is enabled.
EPT
Echo Protector
Tone
0:5:3
If EPT is a one, an unmodulated carrier is transmitted for 185 ms followed by 20 ms of no transmitted energy at the beginning of the training sequence. This option is available in both the V.27
and V.29 configurations, although it is not specified in the CCITT V.29 recommendation.
FED
Fast Energy
Detector
1:5:6
The zero state of FED indicates energy is present above the receiver threshold," the passband.
FED is not used for Group 2 Facsimile.
(None)
FREOUFREOM
0:2:0-7,
0:3:0-7
The host processor conveys tone generation data to the transmitter by writing a 16-bit data word to
the FREOL and FREOM registers in the interface memory space, as shown below.
FREQM Register (0:3)
IBit:
LData Word:
I
l
7
2'5
I
I
6
214
I
I
5
213
I
I
I
4
2'2
3
I
I
2"
I
I
3
23
I
2
2'0
I
I
1
29
I
0
I
I
25
I
I
0
20
I
FREQL Register (0:2)
IBit:
I
IData Word: I
7
27
I
I
6
I
I
26
5
25
I
I
4
I
2'
I
2
22
I
I
1
2'
I
I
The frequency number (N) determines the frequency (F) as follows:
F = (0.146486) (N) Hz to.Q1.A>.
Hexadecimal frequency numbers (FREOM, FREOL) for commonly generated tones are given below:
FRT
Freeze Taps
FRl - FR3
Frequency 1,2,3
Frequency (Hz)
FREQM
462
1100
1650
1850
2100
OC
52
10
55
2C
31
38
00
55
00
FREQL
When FRT is a one, adaptive equalization taps are prevented from changing.
1:B:5,6,7
The one state of FR1, FR2 or FR3 indicates reception of the respective tonal frequency when the
modem is configured for FSK. The default frequencies for FR1, FR2 and FR3 are:
Bit
Frequency (Hz)
FRl
FR2
FR3
2100
1100
462
G2FGC
Group 2 Fast
Gain Control
l:C:O
The one state of G2FGC selects a fast AGC rate (8.6 times standard) in Group 2 Facsimile.
IAl
Interrupt Active
(One)
1:E:7
IAl is a one when Chip 1 is driving IRO to zero volts.
lAO
Interrupt Active
(Zero)
0:E:7
lAO is a one when Chip 0 is driving IRO to zero volts.
3-138
14400 bpsHalf-Duplex Modem
R144HD
R144HD Interface Memory Definitions (Continued)
Mnemonic
Name
Memory
Location
Description
lEO
Interrupt Enable
(Zero)
0:E:2
The one state of lEO causes the IRQ output to be low when the DAO bit IS a one
IE1
Interrupt Enable
(One)
1.E:2
The one state of IE1 causes the IRQ output to be low when the DA1 bit is a one.
J3L
Japanese 3 Link
1.D:4
The one state of J3L selects this standard for link amplitude equalizer. The zero state of J3L
selects U.S. survey long.
MDAO
Modem Data
Available (Zero)
O.E:O
MDAO goes to one when the modem reads or writes register 0:0. MDAO goes to zero when the
host processor reads or writes register 0:0. MDAO IS used for parallel mode as well as for diagnostic data retrieval.
Modem Data
Available (One)
1:E:0
PDM
Parallel Data
Mode
0:F:7
The one state of PDM places the modem in the parallel mode and inhibits the reading of Chip 0
diagnostic data.
PNDET
Period 'N'
Detector
1:7:S
The zero state of PNDET indicates a PN sequence has been detected. PNDET sets to a one at the
end of the PN sequence.
P2DET
Period '2'
Detector
1:4'2
The zero state of P2DET indicates a P2 sequence has been detected. P2DET sets to a one at the
start of the PN sequence.
(None)
RAM Access B
1:F:0-7
Contains the RAM access code used in reading or writing RAM locations in Chip 1 (baud rate
deVice).
(None)
RAM Access S
O:F:O-S
Contains the RAM access code used In reading RAM locations in Chip 0 (sample rate device).
(None)
RAM Data XBL
1:2:0-7
Least significant byte of 1S-bit word x used in reading RAM locations in Chip 1 (baud rate device)
(None)
RAM Data XBM
1:3:0 -7
Most significant byte of 1S-bit word x used in reading RAM locations in Chip 1 (baud rate device).
(None)
RAM Data XSL
0:2:0-7
Least significant byte of 1S-bit word x used in reading RAM locations in Chip 0 (sample rate
deVice).
(None)
RAM Data XSM
0:3:0-7
Most significant byte of lS-bit word x used in reading RAM locations in Chip 0 (sample rate
device).
(None)
RAM Data YBL
1:0:0-7
Least significant byte of 1S-bit word y used in reading or writing RAM locations in Chip 1 (baud
rate device). See DA1.
(None)
RAM Data YBM
1.1:0-7
Most Significant byte of 1S-blt word y used
rate deVice).
(None)
RAM Data YSL
0:0:0-7
Least Significant byte of 1S-bit word y used In reading RAM locations In Chip 0 (sample rate
device). Shared by parallel data mode for presenting channel data to the host microprocessor
bus. See Transceiver Data and DAO.
(None)
RAM Data YSM
0:1:0-7
Most significant byte of 1S-blt word y used
deVice).
RAE
RAM Address
Extension
0:5:4
This bit is an extension of RAM Access S when RAMWS is a one. When RAE is a one, the
XRAM in Chip 0 is selected for a RAM write operate, and when a zero the YRAM is selected.
RAMWB
RAM Write Chip 1
(baud rate
device)
1:D:0
RAMWB is set to a one by the host processor when performing diagnostic writes to the baud rate
deVice (Chip 1). RAMWB is set to a zero by the host when reading RAM diagnostic data from
Chip 1.
RAMWS
RAM Write Chip 0
(sample rate
device)
0:5.5
RAMWS IS set to a one by the host processor when performing diagnostic writes to the sample
rate device (Chip 0). RAMWS IS set to a zero by the host when reading RAM diagnostic data from
Chip O.
RLE
Receiver Link
Equalizer
1:D'5
The one state of RLE enables the link amplitude equalizer in the receiver.
RTS
Request-to-Send
0:5'7
The one state of RTS beginS a transmit sequence. The modem will continue to transmit until RTS
is turned off, and the turn-off sequence has been completed. RTS parallels the operation of the
hardware RTS control Input. These Inputs are "ORed" by the modem.
MDA1
MDA1 goes to one when the modem writes register 1:0. MDA1 goes to zero when the host
processor reads register 1'0.
I
II
)1
I
I:
I
o
Ii
3-139
In
In
reading or writing RAM locations
reading RAM locations
In
In
Chip 1 (baud
Chip 0 (sample rate
R144HD
14400 bps Half-Duplex Modem
R144HD Interface Memory Definitions (Continued)
Mnemonic
SETUP
Name
Memory
Location
O;E;3
Setup
Description
The one state of SETUP causes the modem to reconfigure to the control word in the configuration
register, and to assume the options specified for the equalizer (0;5;1). SETUP returns to zero
when acted on by the modem. The time required for the SETUP bit to cause a change depends
on the current state of the modem. The following table lists worst case delays.
Current
State
V.21
DELAY
14 ms
G11
400
~s
High Speed
Receiver
2 BAUD
High Speed li"ansmitter
2 BAUD + TURNOFF Sequence + Training (if
applicable) + SQUELCH (if applicable)
SQEXT
Squelch Extend
0;5;2
The one state of SQEXT inhibits reception of signals for 130 ms after the turn-off sequence.
TDIS
Training Disable
0;5;6
If TDIS is a one in the receive state, the modem is prevented from entering the training phase. If
TO IS is a one prior to RTS going on, the generation of a training sequence is prevented at the
start of transmission.
TLE
Transmitter Link
Equalizer
1;0;6
The one state of TLE enables the link amplitude equalizer
(None)
Transceiver Data
0;0;0-7
In receive parallel data mode, the modem presents eight bits of channel data in register 0;0 for
reading by the host microprocessor. After the eight bits have been accumulated in register O;C
they are transferred to 0;0 and bit O;E;O goes to a one. When the host reads 0;0, bit O;E;O resets
to a zero. The first bit of received data is not necessarily located in bit 0;0;0. The host must frame
the received data by searching for message sync characters. Bit O;E;O sets at one eighth the bit
rate In parallel data mode rather than at the sample rate (9600 Hz) as it does when reading RAM
locations.
In
the transmitter.
In transmit parallel data mode the host stores data at location 0;0. This action causes bit O;E:O to
reset to a O. When the modem transfers the data from 0:0 to 0:2 bit O:E:O sets to a 1. The data is
serially transmitted from register 0:2 least significant bit first. Received data is shifted into register
O:C from MSB toward LSB.
AUTO DIAL SEQUENCE
POWER-ON INITIALIZATION
The modem features a Dual Tone Multifrequency transmitter
configuration. The duration of the DTMF signal is 95 ms and
the interdigit delay is 70 ms.
When power is applied to the modem, a period of 50 to 350 ms
is required for power supply settling. The power-on-reset signal
(POR) remains low during this period. Approximately 10 ms after
the low to high transition of POR, the modem is ready to be
configured, and RTS may be activated. If the 5 Vdc power supply
drops below 3.5 Vdc for more than 30 msec, the POR cycle is
repeated.
The table below lists the Dial Digit Register (DDR) codes
necessary for DTMF dialing and the corresponding tone pairs.
Dial Digits/Tone Pairs
Dial Digit Register (DDR)
Hexadecimal Code
Dial Digit
00
01
02
03
04
05
06
07
08
09
OA
OB
0
1
2
3
4
5
6
7
8
.
9
#
At POR time the modem defaults to the following configuration: V.33/14400 bps, serial mode, training enabled, no echo protector tone on, no extended squelch, interrupts disabled, no link
equalizer, RAM Access B code 22.
Tone Pair
(Hz)
941
697
697
697
770
770
770
852
852
852
941
941
1336
1209
1336
1477
1209
1336
1477
1209
1336
1477
1209
1477
POR can be connected to a user supplied power-on-reset signal
in a wire-or co~ration. A low active pulse of 3/Lsec or longer
applied to the POR pin causes the modem to reset. The modem
is ready to be configured 10 msec after the low active pulse is
removed from POR.
The following flowchart defines the auto dial sequence via the
microprocessor interface memory.
3-140
',I
I'
R144HD
I
I
14400 bpsHalf-Duplex Modem
I
o -RTS
(0:5:7)
WRITE DTMF CONFIGURATION
CODE: $82 - 0:4
II
1 - SETUP (0:E:3)
11
FIRST DIGIT - DDR (0:0)
1 -RTS (0:5:7)
MDAO (O:E:O)
=
1
Y
NEXT DIGIT - DDR (0:0)
N
LAST DIGIT
$FF - DDR (0:0)
y
MDAO (O:E:O)
=
1
Y
o-
RTS (0:5:7)
Auto Dialing Sequence Flowchart
PERFORMANCE
TYPICAL BIT ERROR RATES
Whether functioning as a V.27 ter, V.29, TCM96, TCM72, or V.33
type modem, the Rl44HD provides the user with unexcelled high
performance.
The Bit Error Rate (BER) performance of the modem is specified
for a test configuration conforming to that specified in CCITT
Recommendation V.56. Bit error rates are measured at a
received line signal level of - 20 dBm as illustrated.
3-141
•
I
I
I
R144HD
14400 bps Half-Duplex Modem
An example of the BER performance capabilities is given in the following diagram.
V272400
W9,4800
TCM72
\
V27,4800 JCM98
V29,7200 / V.33, 12000
V29,9600 V.33,14400
10- 3 r--t---r--~~~~~-f~~~r-~~-r------'
10-4~
__-+-+____.-~~~~~~~~__~-+____~
i
iIii
10-5~-----'-----ir-~r-~4r~r-~+---~------i
15
5
10
Signal to Noise Ratio in dB
20
25
30
"lYpical Bit Error Rate
(Back-ta-Back, Level - 20 dBm)
The BER performance test set-up is shown in the following diagram:
;--
MODEM
TRANSMITTER
j
3002
UNE
I - - SIMULATOR
SE~
FA-1445
-
IMPAIRMENT
SOURCE
BRADLEY 2A
AND2B
-
ATTENUATOR
HP 350D
l
MODEM
TEST SET
PHOENIX
5000
LEVEL
METER
HP 3552A
MODEM
RECEIVER
I
NOTE
SIGNAL AND NOISE ARE MEASURED WITH 3 KHZ FLAT WEIGHTING.
BER Performance Test Set-up
3-142
14400 bps Half-Duplex Modem
R144HD
GENERAL SPECIFICATIONS
Power
Voltage
Tolerance
Current (Typical) @ 25°C
+5 Vdc
+ 12 Vdc
-12 Vdc
±5%
±5%
±5%
500 mA
5mA
5 mA
Current (Max) @ OOC
<600 mA
< 10 mA
< 10 mA
Note: All voltages must have ripple sO.l volts peak-ta-peak.
Environmental
Specification
Parameter
Temperature
Operating
Storage
DoC to + 60°C (32°F to 140°F)
-40°C to +60oC (-40°F to 176°F) (Stored in heat sealed antistatic bag and shipping
container)
Up to 90% noncondensing, or a wet bulb temperature up to 35°C, whichever is less.
Relative Humidity
Mechanical
Parameter
Specification
Board Structure
Single PC board with single right angle header with 40 pins. Burndy FRS 4OBS8P or
equivalent mating connector.
Dimensions
Width
Length
Component Height (max)
Connector Height
Weight (max)
3.937 In. (100 mm)
3.228 in. (82 mm)
0.300 in. (7.62 mm) above, 0.130 in. (3.3 mm) below
0.400 in. (10.16 mm)
3.6 oz. (100 g)
0_675
(17.15)
f3~:
:1:0.003 (5 PL)
,--_ _ _ 0.637
(18.18)
r
J!
3.937
(100)
0.512
(13)
.875
(93.3)
(25A)
~
2.300
(58.4) 3.228
:-\
t -'~~~
0.125
(3.18)
UNITS: INCHES
mm
(82)
0.300 MAX
COMPONENT
=ff~---~~b't
1
J
0.082
(1.6)
0.130
(3.3)
0.400 MAX
(10.18)
R144HD Dimensions and Pin Locations
3-143
"
»<
A<
RleMt=X
".~', ',~~,
MONOFAX'"
c
' "
Modems '
"'
'R96MFX
,'96OQbps fJlONOFAXTM, Modam
u~tRODuerION
TruJ' Rockwell,R96, MONOFAX", is a $yIlChn,~ous 9a1)tl bits PfJr "',
. FEATORES,
.
.
. '. ~ond(bps) half-duplex modem in a single 64-Pin ~ne
, package (QUIP). It is desigMd for operation over tile publiC
. switched 1elephone network through line terminatibns provlded '
by a data access arra~t {OM,).
'
,
'
,
'
c
The modem satisfies the telecommunications requirements .
'Specified in COITT reoomrnendatibns V.29, V.21 tar, V.21 and .
T.4, and the binary signallrtg t&qUlrements ot T.30.. The R96MFX
, can ()Jlerate at speeds of 9600, 7200,~, 2400 and 300 bps..
The R96FAX is deSIgned fOr ~ in Group 3 fac:simile maChines. .
. •The modem's small sinrlindlow poWer Consumption allow the
deslgn Qf compllOtsystem enclosuret for use i",both office and
'horne e!wirQnments.
.
.
• .Slrtg~e 64-1211'1 QUIP
.
'.
• cem V.29, V.27 tar. T.30. V.21·Channel 2, T.4
, •. Group 3 FacslmHe TransmlssiontReception, .
• HSIf..ouPIex(2·Wire)
~ Programmable' Dual Tone Generatlolfand' Detection
• Programmable Tone Detection
• Programmable Turn-on and Turn-off ThresilOld .
• DiagnostiC capability,. .....
. ,', .
"
.... Provides Telephone Line Quality Monitoring Statistics
- Equalizatloit
.... . . '
.
- AutomatiC Adaptive
.
- COn1prQmise Cable (Selectable)
. -OTE lmefraoe: Two Alternate Porta
.'
.. .
. - SeleCtable MWroproceseor Bus' (6500 8Oilt! Compatlbl&)
or
- cCITT·V.24(RS-mC CompatJ'bIe)
• . L.ovi;Power ConsurnptlOO: 1W (Typica~
;.... +5Vdc :1:5% dSll rnA'
.
.
- -5 Vdc ;1;5% <,25 mA' .
.. Programmable Transmit OutpUt Level
. •. TTL and CMOSCompatjble
'c
RgeMFX96Oo bps MoNbFAxPllodeln
,
<',
,
:
'
, ,
,.
~'>
,
'
c'"
'
;,,!
, . Producl:.pnwieW
.~144
Oret_rHo. 802
Febrl4ary1987
R96MFX
9600 bps MONOFAX Modem
~i~IAL
INTERFACE
+ 12VTXA
RTS
CTS
TXD
{
XCLK
DCLK
RXA
RLSD
RXD
MICROPROCESSOR
BUS
INTERFACE
DO
01
02
03
04
05
06
07
RSO
RS1
RS2
RS3
RS4
CABLE1
CABLE2
AUXIN
es
READ
WRITE
IRQ
EYE
DIAGNOSTIC
INTERFACE
r
EYEY
EYECLK
NOTES
EYESYNC
1.
STRAP
+ 5V
GND
6
B7
BUS
COMPATIBILITY
65XXJ68XX
8085
2. NC indicates do not connect.
24.00014 MHz
+~
R96MFX Schematic Diagram
3-145
3·146
l
!
SECTION 4
CUSTOM AND PRIVATE LABEL MODEMS
Page
Product Line Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RG224EC 2400 bps Private Label Modem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RG208 4800 bps Private Label Modem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RGV29FT 9600 bps Private Label Modem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1
4-2
4-3
4-5
4-7
CUSTOM AND PRIVATE LABEL MODEMS
Customizing Products for OEM Requirements
software compatibility requirements, including popular error
correction protocols. Stand-alone, custom board, rack mount
and PC card configurations are available to meet your form
factor requirements.
For rapid market entry with minimum investment, Rockwell
offers OEMs and resellers a growing line of private label
modems. Full turn-key solutions, these stand-alone modems
require only the addition of your company logo. Rockwell can
also supply custom front panels and a selection of enclosure
colors. PC card private label modems are also available. The
chart below presents the current models of the private label
modem product line.
Combining communications expertise with custom design
capabilities and vertically integrated manufacturing
capabilities, Rockwell offers fully customized or private label
products to meet your communications requirements. Rockwell
has an experience base of over ten years as a supplier of
custom modems for major computer and data communications
companies worldwide.
Continued advancements in VLSI modem and digital
communications technology enable us to design and produce
custom modems in a full range of speeds and compatibilities.
In addition to Bell and CCITT compliance, custom modems can
be designed specifically for your proprietary hardware or
Data Speed
Model
(bps)
PSTNI
Leased
Line
2/4-Wire
Half/Full-Duplex
Sync/Async
Compliance
Error
Correction
RG224
2400, 1200
300
P
2WFD
Sync, Async
CCITT V.22 bis, V.22A1B;
Bell 212, 103
RG224EC
2400, 1200
300
P
2WFD
Sync, Async
CCITT V.22 bis, V.22A1B;
Bell 212, 103
MNP Class 3
RGV22BEC
2400, 1200
300
P
2WFD
Sync, Async
CCITT V.22 bis, V.22A/B;
Bell 212, 103
MNP Class 3
RG208
4800,2400
P/L
2WHD,4WFD
Sync
BeIl208A1B;
CCITT V.27 bis/ter
RGV29FT
9600,7200,
4800,2400
P/L
2WHD,4WFD
Sync
CCITTV.29,
V.27 bis/ter
4-2
RG224EC and RGV22BEC
Private Label Modems
'1'
Rockwell
RG224EC and RGV22BEC
2400 bps Modems
DESCRIPTION
The RG224EC corrects errors by employing Microcom's
class 3 MNP protocol, which resides in firmware in the
modem itself and is transparent to the user except for a
few simple commands. The RGV22BEC further tailors this
error correcting software to the country of operation. This
protocol is bit-synchronous, which is 20% more efficient
than asynchronous transmission. It has error detection
based upon a 16-bit Cyclic Redundancy Check (CRC),
error correction, and automatic retransmission. These
error correction techniques create a reliable link of virtually error-free data transfer at both 2400 and 1200 bps
when communicating with another MNP type modem.
The RG224EC and RGV22BEC are advanced error correcting
2400/1200/300 bps modems for private labeling by OEMs and
resellers. With Rockwell VLSI and digital signal processing
technology, these modems offer high quality, low cost and a
versatile array of features.
These Bell-compatible modems operate at 2400 bps, 1200 bps
or 300 bps full-duplex, over the dial-up telephone network. Over
shorter hauls, the RG224 works in half-duplex and fallback
(synchronous and asynchronous) modes.
The RG224EC and RGV22BEC are packed with user convenience features. In answer mode, the modem automati·
cally adapts to match the speed of the incoming signal.
For outgoing calls, pulse or tone dialing can be selected,
and communication software is no problem with "AT"
command set compatibility. Rockwell's unique automatic
adaptive equalization technique compensates for noise
on the telephone line or weak incoming signals, delivering
accurate and reliable data. A non-volatile memory stores
up to ten frequently called numbers and command
strings. The RG224 also features auto answer, a call prog·
ress speaker with volume control, and the ability to moni·
tor another data transmission.
INTERNATIONAL COMPATIBILITY
For global markets, the RG224EC and RGV22BEC are
compatible with CCITT V.22A/B and V.22 bis standards.
The RGV22BEC offers all the features of the RG224EC
plus a telco interface and dialing protocol developed for
specific country operation. Contact the Rockwell factory
for information on available international versions.
CUSTOMIZING THE PRODUCT
The RG224EC and RGV22BEC are available with customized logos and enclosure colors. The standard enclosure
color is bone, with other colors available on special order.
Rockwell will silkscreen your own custom artwork or logo
on the available on the front panel. For a true scale front
drawing, request RG224EC brochure (Document No. 0-4).
VIRTUALLY ERROR-FREE TRANSMISSION
Error detection is crucial at 2400 bps because so much
data can be garbled by a single distortion in the line. Simple protocols are not equipped to handle the errors and
delays inherent in the long-distance dial-up network.
RG224EC Modem
Data Sheet
4-3
RG224EC and RGV22BEC
2400 bps Private Label Modems
CUSTOMIZED DQCUMENTATION AND PACKAGING
FOR ADDITIONAL INFORMATION
The corrugated cardboard shipping box is blank, ready to
slip on your sleeve. The text will be supplied to you on an
industry compatible 5-1/4" diskette in Microsoft Word format. It can be directly output to an HP LaserJet printer, or
easily converted for output to a different printer. Photostats of all artwork used in the manual complete the documentation kit. With this kit, you can easily paste up a
manual for printing, or you can have it edited to your specific needs.
For a color brochure on the RG224EC, request Document
No. D-4. Additional 2400 bps private label modems are
available, including a version without error correction, the
RG224, and an internal PC halfcard. Contact the Rockwell
factory for details.
TECHNICAL SPECIFICATIONS
Compliance: Bell 212A and 103
CCITT V.22A/B and V.22 bis
Answer Modes: Manual or automatic, with automatic conversion to speed of incoming data.
Data Format: Synchronous or asynchronous binary serial.
Synchronous: 2400 or 1200 bps.
Asynchronous: 2400, 1200 or 300 bps.
Character lengths: 8, 9, 10 or 11 bits.
Telephone Interface: Connection to two-wire DDD network
via USOC RJ11, RJ12 and RJ13 jack.
Operation: Full or half duplex over 2-wire dial-up or leased
lines.
Error Correction: Microcom Network Protocol (MNP) level 3
DTE Interface: EIA RS-232-C, CCITT V.24IV.28
Command Compatibility: Hayes "AT" command set compatible
Modulation: QAM for V.22 bls; DPSK for V.22 and Bell 212A
FSK for 0-300 bps.
Software Compatibility: Crosstalk XVI and Smartcom II.
Carrier Frequency:
Specification
V.22
V.22
V.22
V.22
Bell
Bell
Bell
Bell
Bell
Bell
bis low channel, Originate Mode
low channel, Originate Mode
bis high channel, Answer Mode
high channel, Answer Mode
212A high channel Answer Mode
212A low channel Originate Mode
103/113 Originating Mark
103/113 Originating Space
103/113 Answer Mark
103/113 Answer Space
Test Modes: Local analog loop back, remote digital loopback.
Frequency
1200
1200
2400
2400
2400
1200
1270
1070
2225
2025
Certification: FCC Parts 68 and 15 Class B. ULlCSA
approved.
Electrical: 120 VAC (104 VAC-128 VAG), 60 Hz, 0.2A external
wall mount transformer
Environmental: Operating: -10°C to 50°C
Storage: - 20°C to 80°C
Relative Humidity: 10% to 90%, noncondensing, or a
wet bulb temperature of 35°C, whichever is less
Equalization: Automatic adaptive and fixed compromise.
Dimensions: Width 6.25 in. (15.88 cm)
Height 1.375 in. (3.49 cm)
Depth 10.50 in. (26.67 cm)
Transit Level: -10 dBm ± 1 dB
Dial modes: Pulse or tone auto dialing. Non-volatile directory stores 10 numbers with 40 digits each.
Weight: 3.75 Ibs. (8.25 kg)
Sensitive: 0 to - 43 dBm
SpeCIficatIon
0287MD37
IS
Warranty: Two-year, limited
subject to change without notIce and shall not be regarded as a warranty
4-4
RG208
Private Label Modem
'1'
Rockwell
RG208
4800 bps Private Label Modem
DESCRIPTION
FEATURES
The RG208 4800 bps synchronous modem is designed for
private labeling by OEMs and resellers. It incorporates
advanced features such as auto-dial, four-wire dial backup
and truly uncomplicated set-up. In addition, the RG208 is
compatible with existing 208A/B modems as well as the
CCITT V.27 bislter standard. The front panel liquid crystal
display and touch sensitive keys make configuration easy,
with menus, call progress and system status displays.
Optimum data transfer over poor or changing lines is
assured with Rockwell's Auto Adaptive Equalization.
•
•
•
•
•
•
JUST ADD YOUR LOGO
Add your logo to the area within the embossed border on
the left side of the front panel. Or, simply send us the
camera-ready art and we wi II do the rest.
•
You may customize the front panel with your choice of
color and graphic designs. Rockwell will be happy to
quote the additional cost for a custom front panel.
•
PERSONALIZED DOCUMENTATION
•
•
•
The RG208 user manual is stored on an industry compatible 5·1/4 in. diskette in Microsoft Word format. Edit the file
to add your company name, model number and any
application·specific instructions. Print the file directly on
an HP LaserJet printer. Photostats of all artwork and photographs used in the manuals complete the documenta·
tion kit.
Self·contained modem with your customized logo
4800 or 2400 bps operation
Bell 208A/B and CCITT V.27 bis/ter compatible
Compatible with industry standard 208A/B modems
Full·duplex, synchronous operation over four-wire
leased lines
Full duplex over four-wire dial backup (dual, two-wire
dual lines)
Half-duplex operation over two·wire, dial·up or leased
lines
Auto/manual dial and answer
LCD front panel displays user commands and system
status for ease of use
Easily configured via front panel touch-sensitive keys:
no internal switches and registers to set
Pulse or tone auto-dialing with automatic redial capa·
bility
Call progress monitored on LCD display or internal
speaker
Non·volatile directory of 20 telephone numbers (35 digits each)
Two year limited warranty; extended warranty plans are
available
RG208 Modem
Data Sheet
4-5
4800 bps Private label Modem
RG208
RG208 PACKAGING
FOR MORE INFORMATION
The RG208 is shipped to you in a blank corrugated cardboard box ready to slip into your branded sleeve_ The
modem, three cables (an RJ11 C, RF45S and a standard telephone cable) and the power supply are packed in foam
protectors and covered with a top tray that holds your customized documentation_
Request the RG208 brochure (Literature Order No. 0-6).
TECHNICAL SPECIFICATIONS
Compliance: Bell 208 A/B and Y.27 bis/ter
Liquid Crystal Display: Two-line, 40-character LCD and
four key system for menu driven operation and configuration from front panel. Configuration stored in
nonvolatile memory. Displays call progress, error
messages, line quality, signal strength, CD, RTS,
CTS, DSR and test results
Data Rates: 4800 and 2400 bps
Data Format: Synchronous binary serial
Operation: Four-wire leased line, full duplex
Two-wire leased line, half-duplex
Two-wire dial-up line, half-duplex or pseudo fullduplex
Four-wire dial backup, full-duplex (two 2-wire dial-up
lines, half-duplex)
Auto-dial: Automatic tone or pulse dialing; telephone
directory stores 20 numbers with 35 digits each
Answer Modes: Manual or automatic
Terminal Mode: May be controlled by terminal commands
in SDLC eight-bit ASCII data format
Modulation: Eight-phase DPSK
Carrier Frequency: 1800 ± 1 Hz
Test Modes: Local and remote analog loopback, digital
loop back, and self-test
Line Requirement: Unconditioned
Certification: FCC parts 68 and 15 Class A. UUCSA certified
Equalization: Automatic adaptive; selectable cable length
equalization
Electrical: 120 VAC (104 VAC-128 VAC), 60 Hz, 0.25 A external wallmount transformer
Transmit Clock: Internal or External
Transmit Level: 0 to -14 dBm (Selectable in -2 dBm
steps)
Environmental: Operating lemperature: 5°C to 40°C
Storage Temperature: - 20°C to 70°C
Relative Humidity: 10% to 90%, noncondensing, or a
wet bulb temperature of 35°C, whichever is less
Receiver Threshold: - 43 dBm, - 33 dBm, - 26 dBm, -16
dBm (Selectable)
Dimensions: Width: 8.5 in. (21.6 cm)
Height: 2.6 in. (6.7 cm)
Depth: 9.3 in. (23.6 cm)
RTS/CTS Delay: Bell 208: 50 ms or 150 ms (Selectable)
Y.27: 50 ms, 67 ms, 708 ms, or 943 ms (Selectabl)
Telephone Interface: Leased Line: RJ14C
Dial-up Lines: RJ11 C and RF45S
Weight: 4.6 Ibs. (10.1 kg)
Warranty: Thlo-year, limited
DTE Interface: EIA RS-232-C, CCITT V.241V.28
Spec/treat/on
0287MD38
IS
subject to change without noNce and shalJ not be regarded as a warranty.
4-6
RGV29FT
Prjvate f"fbel NlodetrJ$
'1'
Rockwell
RGV29FT
9600 bps Private Label Modem
.INTRODUCTION
CUSTOMIZE YOUR DOCUMENTATION
The RGV29FT is a 9600 bps synchroOQus modem with fas·t
training capability for leased line network applications.
OesigriecJ for private labeling by OEMs and reseliers, the
RGV29FT also includes. a four-wire dial line mode Which
may be used to back-up a four-wire leased circuit. The
auto-dlallauto-answer features and convenient configuration from the front panel ensura easy operation for even
the .first-time user. The front panel liquid crystal display
.displays oonflguration rnenus, modem status, tine quality,
signal strength and the talephone numbers stored In the
programmable telephone number directory.
The user manual is supplied on an IBM PC-compatibhll
5 1/4 in. diskette in Microsoft Word format, ready for addition of your company name, model number. It is formatted
for printout on an HP LaserJet ptlnter. Photostats of art·
work used In the manual complete your documentation
kit.
FOR MORE INFORMATION
Request RGV29FT brochure (literature Order
The RGV29FT js compatiblewUh GelTT '1.22 and V.27 blst.
terstandards. The security option provides a cho.ice of
. passWord and diaJbaCk security modes.
READY FOR PRIVATE LABEUNO
The tront panel includes an embossed area ready to
accapt yoUr company logo Or may be customized to your
design. Gost of custom front panel colors and graphic
designs are available by quotation. The RG\f29FT is
shipped in a blank corrugated cardboard box ready for
insertIOn In your branded outer sleeve.
RGV29FT Modem
Data Sheet
H
No. Q.9).
9600 bps Private Label Modem
RGV29FT
TECHNICAL SPECIFICATIONS
Compliance: CCITT V.29 and V.27 bis/ter
DTE Interface: EIA RS·232-C, CCITT V.24IV.28
Data Rates: V.29: 9600, 7200, and 4800 bps
V.27: bis/ter: 4800 and 2400 bps
Liquid Crystal Display: Two-line, 40-character LCD and
four key system for menu driven operation and con·
figuration from front panel. Configuration stored in
non-volatile memory. Displays call progress, error
messages, line quality, signal strength, CD, RTS,
CTS, DSR and test results
Data Format: Synchronous binary serial
Operation: Four·wire leased line, full duplex
Two·wire leased line, half·duplex
Two·wire dijil·up line, half-duplex or pseudo full·
duplex
Four·wire dial backup, full-duplex (two 2-wire half·
duplex dial-up lines)
Auto·dlal: Automatic tone or pulse dialing; telephone
directory stores 20 numbers with 35 digits each
Answer Modes: Manual or automatic
Security Mode Option: Password or dial back
Modulation: V.29: Quadrature Amplitude Modulation
(QAM)
Line Requirement: Unconditioned
Test Modes: Local and remote analog loopback, digital
loopback, and self-test Certification: FCC parts 68
and 15 Class A. Designed for UL and CSA certification
Equalization: Automatic adaptive; selectable cable length
equalization
Electrical: 120 VAC (104 VAC-128 VAC), 60 Hz, 0.25 A external wall mount transformer
Transmit Clock: Internal or External
Environmental: Operating Temperatures: 5°C to 40°C
Storage Temperature: - 20°C to 70°C
Relative Humidity: 10% to 90%, noncondensing, or
a wet bulb temperature of 35°C, whichever is less
Carrier Frequency: 1700 ± 1 Hz or 1800 ± 1 Hz
Transmit Level: 0 to -14 dBm (Selectable in - 2 dBm
steps)
Receiver Threshold: -43dBm, -33dBm, -26dBm, -16
dBm (Selectable)
Dimensions: Width: 8.5 in. (21.B cm)
Height: 2.B in. (B.7 cm)
Depth: 9.3 in. (23.B cm)
RTS/CTS Delay: Fast Train:
23 ms (V.29 9600, 7200, 4800 bps)
22 ms (V.27 4800 bps)
30 ms (V.27 2400 bps)
CCITT Y.29: 253 ms
Weight: 4.B Ibs. (10.1 kg)
Warranty: Two-year, limited
Telephone Interface: Leased Line: RJ14C
Dial-up lines: RJ11C and RJ45S
Specification
0287MD39
IS
subJect to change without notice and shall not be regarded as a warranty.
4-8
SECTION 5
APPLICATION NOTES
An R6500/11-R2424 Intelligent Modem Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interfacing Rockwell Signal Processor-Based Modems to an Apple lie Computer. . . ..
240011200/300 bps International Modem Design ..................................
Quality of Received Data for Signal Processor-Based Modems . . . . . . . . . . . . . . . . . . . . .
R2424 and R1212 Modems Auto Dial and Tone Detection .........................
8088 Microprocessor to R1212/R2424 Modem Interface ...........................
High Speed Modems Filter Characteristics .......................................
R96F Modem Tone Detector Filter Tuning ........................................
R96F Modem Recommended Receive Sequence for Group 2 Facsimile .............
DTMF Dialing for R24MFX, R48MFX, R24BKJ, or R48BKJ .........................
5-1
Page
5-3
5-46
5-50
5-83
5-104
5-114
5-119
5-121
5-127
5-130
5-2
j
1
I
i
Application Note
'1'
Rockwell
An R6500/11 - R2424 Intelligent
Modem Design
!1
by Ron Collins and Joseph W. Hance
Product Applications Engineers
Semiconductor Products Division, Newport Beach, California
INTRODUCTION
The PAL' generates the proper bus control signals needed to
interface the R2424DC to the R6500/11 's bus. It also allows the
R6500/11 to switch the serial data between the host and the line
to accommodate the command and on-line modes. The 1488's
(Z4, Z5) and the 1489 (Z6) provide a standard RS-232-C interface for the host computer. These devices would not be
necessary in the design of a plug-in personal computer modem.
Figure 2 shows the logic equivalent olthe 16L8 PAL and Figure 3
shows the PALASM equations used to program the PAL.
The combination of single chip microcomputers and standard
modems makes possible the implementation of sophisticated and
flexible telecommunications systems. The intelligent modem has
become the standard for personal microcomputers and provides
access to many outside resources over standard telephone lines.
This application note describes the hardware and software design
of a 300/1200/2400 bit-per-second (bps) modem based on the
Rockwell R2424 Single board modem and the R6500/11 singlechip microcomputer. The system design minimizes the number
of devices used and provides the user adequate room for special
features. The software implements the industry standard ''AT''
command set so that compatibility with commercial software
packages is provided. This particular design is that of a standalone "Box Modem" but only minimal changes are needed in
the configuration for a personal computer bus compatible
modem.
SOFTWARE DESIGN
The Functional State diagram for the software is shown in
Figure 4. An assembly listing of the program is included at the
end of this application note. Notes are liberally included in the
listing to assist the understanding of program operation. (Figure 7).
Note: In the discussion of the software and operation of this
deSign, it is assumed the reader knows and understands the
common "AT" commands. If not, refer to any of a number of
source materials devoted to this subject.
HARDWARE DESIGN
The hardware used in this design (see the schematic in Figure 1)
consists of an R6500/11 microcomputer (Zl), an R2424DC
modem module (Z3), and a 16L8 type PAL (Z2). A complete parts
list is tabulated in Table 1.
There are five main sections to this program. In order of occurrance in the listing, they are:
Part
Part
Part
Part
Part
The R6500/11 controls the system and implements the high level
command protocol. It has an internal UART which provides communications between the host computer and the modem. The
R2424DC module is addressed as a peripheral on the abbreviated bus of the R6500/11. All modem configuration, dial, status,
and commands are transmitted over the data bus. The serial
interface to the R2424DC carries only the data transmitted or
received over the telephone line.
Table 1.
Part
Qty
Description
1
2
3
4
5
6
7
P1
R1
R2
R3
Y1
Zl
Z2
Z3
Z4
Z5
Z6
1
1
1
1
1
1
1
1
1
1
1
RS-232C Connector, Female, OB-25
4.7K ResIstor, 5%
3K ReSistor, 5%
3K ReSistor, 5%
1.8432 MHz Crystal
R6500/11 Single-chip Microcomputer
PAL 16L8
R24240C Modem Board
MC1488
MC1488
MC1489
8
9
10
11
1:
2:
3:
4:
5:
Baud rate and protocol determination ($F800-$F998)
Reading in the command string
($F999-$F9E8)
Processing the command string
($F9E9-$FA 1B)
Command definitions
($FB1E-$FEBA)
Interrupt Service Routine
($FF57-$FF79)
Most of the software operates in the Command Mode, responding to inputs from the host system. The Command Mode section
includes Parts 1-5, with the exception of the (Carriage
Return) command in Part 4. The remaining sections of Figure 4
lie within the definition of the < CR > command. Figure 5 shows
the flow chart of the Command Mode section.
R6500/11-R2424 Intelligent Modem Parts List
Item
:l
After initialization, the software loops in Part 1, waiting for an
attention code ("AT" or "Ai") or for the phone to ring. Any
system designed to run the "AT" command set must be able
to operate at either 300 or 1200 (or, in this case, 2400) baud,
using 7 or 8 bits per word, with even, odd or no parity, switching
from one mode to another automatically. The method used to
do this is outlined on page 0004 of the software listing, Figure 7. Figure 6 diagrams the bit patterns of the characters" A" ,
"T" and "I" and shows how the relationship of bits 8 and 9 of
each character determine the characteristics of the serial
protocol.
'PAL and PALASM are registered trademarks of Monolithic Memories, Inc.
Document No. 29220N69
Application Note
5-3
Order No. 669
December 1984
il
'II
'I
Application Note
R6500/11 • R2424 Intelligent Modem Design
In Part 2 the serial communications protocol as been established.
ASCII command characters are read in one at a time and stored
in a buffer (lNBUFF), excepting and non-
control characters, until a character is entered. Should
more than 40 characters be received, a flag (BUFFLG) is set,
indicating an error condition.
General notes on the software:
Liberal use was made of the available RAM for 1-bit flags and
variables, primarily because no premium IS placed on RAM
space in this design. These could be compressed into byte-sized
entities should more space be required.
When the program recognizes a character it stops
accepting commands and goes directly to command execution
(Part 3). It processes each command in sequence until an "A",
"0", "Z" or command. "A" and "0" forces an attempt
to go on-line (examine RSLDI for carrier signal and go on-line
if present, otherwise it will go back to Command Mode.) "Z"
performs a soft reset and returns to Command Mode. < CR >
is the usual end to each command string. This is where error
conditions are reported, on-line data are handled, and a return
to Command Mode from Data Mode is made upon recognition
of a valid escape code sequence.
No attempt was made to provide status information via the S 13,
S14, S15 or S17 pseudo-registers. These could be added if
necessary.
The S10 (Loss of Carrier) and S11 (Touch-Tone) delay times are
limited to 400 ms and 70 ms, respectively, due to the design
of the R2424 Modem.
The "H2" command does nothing additional to the "H1" command since the R2424 Modem does not have an auxiliary relay.
This intelligent modem will recognize that it is being called only
while it is waiting for an attention code (at label L1). If the PAO
flag goes high at this point, indicating the phone is "ringing",
the program branches to RING then jumps to RINGNG, where
a determination is made whether to answer the phone or not.
If not ringing, it goes back to waiting for "AT" or "AI". If it is
ringing, it then bypasses Part 2 and Part 3 and attempts to go
to the Data Mode (depending on presence of a carrier signal)
by executing the "A" (Answer) command.
This program implements the concepts of modularity and structured programming as much as was practical for assembly-level
code. This allows easy customization and tailoring for a particular
application. There are deviations from this guideline, however,
so modifications should be made with this in mind.
Expansion might include detection of Dial tone, Ringing and
Busy signals using the TONE bit of RCV8. For example, if a Busy
Signal is detected, the program could automatically re-dial after
a suitable delay time.
When this modem is called, an assumption is made as to the
proper baud rate and serial protocol, that the values determined
by the most recent attention code are still valid. Should a .call
be received before the first attention code was entered, it defaults
to 1200 baud, 8 bits, no parity. The call is not answered in this
case, Since SO was not set to a non-zero value, however, the
"RING" message is sent out to the host system at this rate.
Unlike some commercial intelligent modems, no default switches
or status LEDs were implemented in this design, nor was an
actual speaker circuit included (though a control line for one,
SPKR-ON/, is provided) in the interests of simplicity.
Finally, this design has not been thoroughly tested to meet the
"AT" specifications. This application note is presented only as
a guide on how to control a R2424 Modem with a R6500/11
single-chip microcomputer.
Part 4 comprises the coding of each "AT" command. All but
AAA, 000, ZZZ and CR end in an RTS instruction, returning
control back to the command string processor at NXTCMD. AAA
and 000 transfer control directly to CR in an attempt to go online. CR always returns to Part 1 of the program, and ZZZ always
jumps to the Power-an-Reset address at RESET.
SERIAL INTERFACE
The modem system supports the following data rates and
asynchronous serial protocols:
Baud: 300, 1200 or 2400
No. of data bits: 7 or 8
No. of stop bits: 1 or 2
Parity: Odd, even or none
Part 5 is divided into two parts: signal processing and delay
timing (execution of one or the other is determined by the value
of the INTFLG flag). The signal processing takes place while
waiting for an attention code, echoing (if enabled) the incoming
bits back to the host system, and is described on page 0004
of Figure 7. Delay timing is selected just before Part 2 (or if a
call is answered). The delay routine is designed to allow a
variable number of precise time delays, where the actual time
interval is determined by the routine needing the delay. For
example, the "," (comma) command tells the modem to do
nothing for S8 number of seconds, so one time interval would
be 1 second. The Carrier Detect Response time interval is 1/10
second and the Escape Code Guard time interval is 20 ms, each
requiring different values for CNTR-B and DELAYT.
The baud rate is determined by the width of the start bit.
The number of data bits, the number of stop bits and parity type
are determined by examining bit 8 and, sometimes, bit 9 in two
consecutive data words comprising an "AT" or "AI" command.
Figure 6 shows the serial stream waveforms for the "AT" or "AI"
commands along with the message bits positions. Table 2 lists
the six selectable protocol configurations.
5-4
R6500/11 • R2424 Intelligent Modem Design
Application Note
+ 5 19C, 23C,26C,30C
+12
15A
12A
-12
~.10A.:!C:,-8C
T 31 32
1.8432 MHZ
Rl
+5
4.7K
DO~
1
2
~21
5
~
22 XTLO XTLlVCC 19
NMI
POO
POl 18
P02 17
P03 16
32
15
P04
PB6
P05 14
13
P06
12
P07 4
PCO
5
PCl
PC2 6
PC3 7
-PKR-ON
S--
DO
01
02
3
04
05
06
07
AO
Al
A2
A3
$2
EMS
RIW
A12
A13
TXO
3
$2 11
PC7 9
PC5
PC4 8
PC6 10
24
PA6
PBO
~~
PBl
PAO
PB2
PB3
PB4
PA3
RES
26
PA4
1
2
3
4
5
6
7
---s-
38
+5+5
23
TXOH
PA7
HI-SPEED 25
PAS
DO
01
02
03
04
05
06
07
RSO
RSl
RS2
RS3
+5
R6500/11
Zl
5C
4A
4C
3A
2A
2C
lA
lC
7A
7C
6A
6
VCC~'
Z3
~NC
~NCWRITE
PAL16L8
Z2
i/GNO
RXOM
llA
WRITE
10C
12C CSO
READ
24C
TXO
RXO
~
9C
CSl
~
16
15
14
READ
TxOM
~
12
.ll.
CTL
TXOH ~
>~~
R24240C
-
CSI
NC
~
37
30
36
35
34
27
20
25C
18A
21C
20A
24A
llC
l:!C
Ri
I
POR
CTS
Ai
OTR
OSR
RSLO
IRQ
POR
4~
28C
1
It)
It)
+
~~
eeu ~I
N'" ~~
~..,;
0
j
+
-'
w
/l:Ul:
c...!.
It)
N
II)
N'"
:;:-=
ti)
"'co "'::
I
W
Q.
N'"
MC1488 Z4
+
Pl
C
N
It)b
MC1488
",co
-
ManNeD
"'N
N
~
-r-
Z5
cll:
xe:
I-C
"'co
...
~..=.
r-~
MC1489 Z6
-...
NO
N
FEMALE OB-25
Figure 1.
TLK
R6500/11-R2424 Intelligent Modem Schematic
5-5
r-Li>
I
R6500/11 • R2424 Intelligent Modem Design
Application Note
1.8432 MHZ
r01
AO
AO
• DO-D7
• RSO
A1
A1
RS1
A2
A2
RS2
A3
A3
RS3
01
PDO-PD7
..
DO-D7
DATA BUS
O2
,..
""
EMS
,....
~
-
RJW
WRITE
,..
READ
""
R6500111
R2424DC
A12
-
A13
RES
TXDH ~
.....
RXD
\..
~
f
"V
,..,
"'"
\..
CS1
I""
POR
TXD
TXDM
CTL
RXDH
CSO
.--
-
~
Figure 2.
,..
I'-'
Logic for 16L8 PAL (Z2)
5-6
RXDM
Application Note
R6500/11 • R2424 Intelligent Modem Design
PAL16L8
MODEM
MODEM CONTROL CIRCUIT
JW HANCE
P2 EMS RW A12 A13 TXD RXDM CTL TXDH GND NC
ICS1 RXDH TXDM READ ICSO IWRITE NC NC VCC
IF (VCC) WRITE = P2 * IEMS * IRW
IF (VCC) IREAD = IP2 + EMS + IRW
IF (VCC) CSO = IEMS * A12 * IA13
IF (VCC) CS1 = IEMS * IA12 * A13
IF (VCC) IRXDH = ITXD * CTL + ITXD * IRXDM + ICTL * IRXDM
IF (VCC) ITXDM = ICTL * ITXDH
*END*
Figure 3.
PAL 16L8 (Z2) PALASM Equations
COMMAND
MODE
-PH ONE RINGS SO TIMES
-"0' , (ON·LlNE) COMMAND
-"A" (ANSWER) COMMAND
-"0" (DIAL) COMMAND
HANG
UP
WAIT
FOR
CARRIER
-
NO CARRIER
DETECTED
-TERMINAL
KEY PRESSED
-CA RRIER DETECTED
- CARRIER LOST
DATA
MODE
-
ESCAPE
CODE
ENTERED
Figure 4.
Modem Software Functional State Diagram
5·7
Application Note
R6500111 • R2424 Intelligent Modem Design
ANSWER PHONE
Figure 5.
Command Mode Flowchart
5-8
Application Note
R6500/11 • R2424 Intelligent Modem Design
WAIT 2 BIT TIMES
Figure 5.
Command Mode Flowchart (Continued)
5·9
Application Note
R6500111 • R2424 Intelligent Modem Design
COMMAND PROCESSOR
Figure 5.
Command Mode Flowchart (Continued)
5-10
Application Note
R6500111 • R2424 Intelligent Modem Design
D
JUMP TO
"CR"
Figure 5.
Command Mode Flowchart (Continued)
5-11
Application Note
R6500/11 • R2424 Intelligent Modem Design
NXTCMD
FETCH (NEXT) CHAR FROM
BUFFER AND COMPARE IT
TO THE VALID COMMAND
BYTES IN CMDTBL
N
PUT ADDRESS OF
CORRESPONDING
SUBROUTINE IN
JUMP VECTOR
JUMP TO
"CR"
Figure 5. Command Mode Flowchart (Continued)
5-12
I
~
I~
11
I,
i
1
Application Note
R6500111 • R2424 Intelligent Modem Design
BIT NO.
CHAR.
A=
2
4
5
7
6
T =
9
L..1.~
0
0
0
0
~..l.
0
-rT------
L.L.L _ _ _ _ _ _
54 (hex)
0
=
8
,-.,,--_ ___
CODE
41 (hex)
DATA
I
3
0
0
0
rTT-----______
2F (hex)
I_.L~
0
0
NO PARITY-ALWAYS 2 STOP BITS
1
8
Is:~1
I
1
START
liT
I
9
STOP
BIT
8 DATA BITS
8
STOP
BIT
7 DATA BITS
STOP
BIT
9
STOP
BIT
WITH PARITY
8 DATA BITS
7 DATA BITS
Figure 6.
Table 2.
Command
Word No.
1
2
1
2
1
2
1
2
1
2
1
2
Command
ASCII Char.
(Bits 1-7)
A
T or I
A
T or I
A
T or I
A
T or I
A
T or I
A
Tori
Serial Protocol Formats Data Length
Selectable Serial Protocol Configurations
Command Word
Bit 8
Command Word
Bit 9
1
0
0
1
1
1
0
0
0
0
0
0
-
1
0
0
1
1
1
5-13
Message Protocol
Odd parity, 7 data bits, 2 stop bits
Even parity, 7 data bits, 2 stop bits
No parity, 7 data bits, 2 stop bits
Odd parity, 8 data bits, 1 stop bit
Even parity, 8 data bits, 1 stop bit
No parity, 8 data bits, 2 stop bits
Application Note
R6500/11 • R2424 Intelligent Modem Design
PASE 0001
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0040
0041
0042
0043
0044
0045
0046
0047
0048
0049
0050
0051
0052
0053
0054
; THIS IS A PROGRAK FOR AN R6500/11 ACTING AS AN INTERFACE
; BETWEEN A HOST COKPUTER WITH A SERIAL PORT AND AN R2424
; "ODE". IT IS DESIGNED TO RUN THE 'AT' COM"AND SET.
; ===::=================================================::==
.OPT
.OPT
0000
0000
0001
*=$0000
PA
PB
1=1+1
.=1+1
f=$11
0002
f=t+l
f=1+2
f=ftl
*=*+1
f=ftl
f=l+l
0011
0012
0014
0015
0016
0017
0017
0018
0019
OOIA
IFR
lEft
"eR
SCCR
SCSR
STDR
SRDR
CNTACl
CNTAH
eNTAL
OOIB
OOIC
0010
OOIE
*=1+1
CNTBCl •• 1+1
CNTBHC f=1+1
CNTBHL t=ft I
STDR
f=ft 1
I=ttl
1=1+1
001F
0040
0041
0042
0043
0044
0045
0046
0047
0048
0049
004A
004B
004C
0074
0075
0076
0077
0078
0079
llEN=132
IVB
= $40
DEFPRO
BAUD
BDRATL
BIlRATH
DElAYC
DELAYT
DELAYS
TESTB
ABIT8
ABIT9
TBIT8
Tsm
INBUFF
REPFLS
BUFFlS
DILFLS
REYFLG
IR9FLS
ECHOFS
1=1+1
t=f+l
t=Hl
1=1+1
I=ft 1
f=ff I
t=1+ I
t=ttl
t=l+!
f=f+!
*=1+1
1=1+1
.=1+40
f=f+ 1
t=f+ I
t=1+1
*=1+1
.=f+l
f=ft 1
; RAK VARIABLES
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
DEFAULT SERIAL PROTOCOL FOR AUTO-ANSIIER COK"UNICATIONS
INDICATOR OF PRESENT TER"INAL BAUD RATE ( 3/12124 )
LOll PART OF BAUD RATE, AS DETER"INED BY CNTR-A
HIGH PART OF BAUD RATE
IRQ COUNTER: COUNTS NU"SER OF TIKES IRQ ROUTINE 15 CALLED
SET TO THE I OF mES THE IRQ ROUTINE IS TO BE CALLED
SET TO THE NU"BER OF SECONDS TO WAIT FOR
CONTAINS THE 7 SAKPLE BITS FRO" THE SERIAL-IN LINE
WHEN THE 7 BITS CLDCKED INTO 'TESTS' "ATCH THE 'A' CHAR,
THE NEXT 2 BITS ARE CLOCkED IN AND STORED HERE.
IIHEN THE 7 SAKPLE BITS IN 'TESTB' "ATCH THE 'T' CHAR, THE
NEXT 2 BITS ARE STORED IN 'TBITS' AND 'TBlT9'.
CONTAINS THE CD"KAND STRINS AS ENTERED FRO" THE HOST SYS.
IIHEN 'AI' 15 ENTERED AS Co""AND, THIS FLAG IS SET.
THIS FLAG IS SET WHEN TOO "ANY COKKAND CHARS ARE ENTERED
IS SET TO INDICATE ANY FOLLOWING NU"BERS ARE DIAL DIGITS
NOR"AL ($00) DR REVERSE ($80) DIAL
$00 ==) IRQ 15 SERIAL-IN mER: $80 ==) IRQ IS DELAY TIKER
$00 ==) DO NOT ECHO CO"KAND CHARS: $80 ==) ECHO CHARS
Figure 7. Software Assembly Listing
5-14
R6500/11 • R2424 Intelligent Modem Design
Application Note
0055
0056
0057
0058
0059
0060
0061
007A
007B
007e
007D
007E
007F
0080
DUPLEX
RSLTFG
SPKRFS
STCODE
VCODE
XCODE
WAITFS
1=1+ I
*=1+1
*=1+ I
t=1+1
t=1+1
t=1+1
t=1+1
;
;
;
;
;
;
;
ECHO CHARS WHILE IN DATA "ODE (ON-LINE) : O=NO, 580=YES
$00 == > SEND OUT RESULT PRO"PT: S80 == >DON' T SEND IT OUT.
USED TO CONTROL THE EXTERNAL SPEAKER
RESULT (STATUS) CODE ( 0-4,5 )
SEND RESULT PRO"PT IN NU"ERIC ( SOO ) OR VERBAL ( S80 ) FOR"
ALLOW EXTENDED RESULT CODES? (SOO = NO I 580 = YES )
'WAlT-FOR-CARRIER ?' FLAG (0 = NO I 580 • YES I
PAGE 0002
0062 0081
0063 0082
0064 0083
0065 0084
0066
0067
0068
0069 0086
0070 0087
0071 0088
0072 0089
0073 008A
0074 008B
0075 008C
0076 008D
0077 008E
0078 008F
0079 0090
OOBO 0091
0081 0092
0082 0093
0083 0094
00B4 0095
0085 0096
0086 0097
0087
0088 0098
0089 009B
0090 009D
WAITC
ESCCNT
SSETFG
SREGP
t=1+1
1=1+ I
t=t+ I
1=1+2
;
;
;
;
INDICATES 'IIAIT-FDR-CARRIER' mE INTERVAL HAS ELAPSED
ESCAPE CODE COUNTER
INDICATES S-REG POINTER HAS BEEN SET TO SO"E VALUE
CONTAINS THE INDIRECT POINTER TO ONE OF THE S-RESISTERS
; THE FOLLOlliNG 17 BYTES CONTAIN THE VALUES FOR THE S-REGISTERS
SO
SI
S2
S3
S4
55
S6
57
58
59
SIO
SII
SI2
513
514
SIS
SI6
517
t=t+1
t=t+1
t=t+\
t=t+1
t=1+1
t=t+1
1=1+1
t=t+\
t=t+1
t=I+1
t=t+1
t=t+\
1=1+1
t:1+1
1=1+1
t=I+1
*=1+1
I=ftl
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
1=1+3
NU"
C"DVEC 1=1+2
mp l=t+1
RI N6 TO ANSWER ON
COUNTS THE NUKBER OF RINSS
ESCAPE CODE CHARACTER
CARR I ASE RETURN CHAR
LI NE FEED CHAR
BACKSPACE CHAR
MAlt-mE FOR DIAL TONE
WAlT-mE FOR CARRIER (AFTER DIALING OR ANSIIERING )
PAUSE-lIKE ( USED BY 'COK"A' CO""AND )
CARRIER-DETECT RESPONSE mE
DELAY-lIKE BETWEEN LDSS OF CARRIER AND 'HANG UP'
DURATION AND SPACING OF TOUCH TONES
ESCAPE CODE GUARD-TlftE
UART STATUS REGISTER
OPTION REGISTER
FLAB RESISTER
I=ENTER SELF-TEST I O=STOP SELF-TEST
BENERAL SYSTE" STATUS
; IIORK AREA FOR ASCll-TO-HEX AND HEX-TO-ASCII CONVERSION
; INDIRECT POINTER TO THE NEXT CD"KAND TO BE EXECUTED
; TEKPORARY STORAGE BYTE
PAGE 0003
0092
0093
0094
0095
009&
0097
0098
0099
0100
0101
0102
1000
RCY
=
$1000
009E
1002
1008
1009
100A
1008
100C
100D
100E
RCV2
RCV8
RCV9
RCVA
RCVB
RCVC
RCYD
RCYE
t=
RCV+2
*=1+6
1=1+1
t=l+\
I=nl
t=1+1
*=1+1
1=1+1
*=1+1
; BASE ADDRESS FOR RECEIVER REGISTERS
5-15
Application Note
0103 100F
0104
0105 2000
0100
0107 1010
0108 2000
0109 2002
0110 200B
0111 2009
0112 200A
01\3 200B
0114 200C
0115 200D
0116 200E
0117 200F
0118
0119 0010
0120 E09C
0121 6760
0122 0001
OI23479C
0124
0125 OOBF
0126 002F
0127 0017
0128
0129 0021
R6500111 • R2424 Intelligent Modem Design
RCVF
l=t+1
XMT
=$2000
; BASE ADDRESS FOR THE TRANSMITTER REGISTERS
xm
t.
IMT
l=t+2
t=t+6
t:HI
.=t+1
'=*+1
t=1+1
.=HI
.=*+1
.=*+1
.=*+1
DlYHIB
DlYTlM
TENTHD
ESCDlY
Escm
=
=
=
=
=
$10
$E09C
$0760
I
; DELAy-mE FACTOR
; ( Dlvm I DlYHIB
; ( TENTHD f DLYHIB
$479C
; I COUNT FOR 'ESCAPE' CODE SUARD TIME ( 20ftS )
BAUD3 =
8AUDI2 =
BAUD24 =
$OOBF
$002F
$0017
; CNTR-A VALUE FDR SERIAL-lID BAUD RATE OF 300 BAUD I i 920KHz
; VALUE FOR 1200 BAUD
; VALUE FOR 2400 BAUD
NUKC"D =
33
j
X"TO
XMT2
IMTB
xm
X"TA
xm
X"TC
XMTD
XMTE
@ 920KHZ
@ 920KHZ
= I SEC. )
= 1110 SEC. I
NUMBER OF CO"MANDS IN' cmBl •
PA6E 0004
0131
0132
0133
0134
0135
0136
0137
0138
0139
0140
0141
0142
0143
0144
0145
0146
t=$F800
2010
RESET lOX
TXS
ClD
SEI
lDA
STA
UFF
j
INITIALIZE THE R6500/1l
mo
j
SET UP "ODE RE61STER FOR ABBREVIATED BUS
F800
FB02
FB03
FB04
F805
F807
A2FF
9A
D8
78
A9 AO
85 14
F809
20 BE FA
JSR
INITSW
; INITIALIZE VARIABLES, ETC.
F80C
FBOE
F810
FBI2
FBI4
87
17
27
07
E7
S"B
R"B
R"B
S"B
5MB
O,PB
I,PB
2,PS
S,PS
I
;
;
;
;
01
01
01
01
01
"eR
O,PS
CTl = 0 I TRANSftlT TO "ODE" I
CTSI = 0
DTRI = 0 ( ACTIVE I
HISPEED = I I HI6H SPEED I
DI SABLE SPEAKER
0147
5·16
Application Note
0148
0149
R6500111 • R2424 Intelligent Modem Design
; **ftftffftfff**f**Hf**ff**f*****tftftffttfff*f********tfffllfftf**ff
FIRST CHARS ACROSS SHOULD BE 'AT' OR "A/'. ASSU"E AN 'A'
IS THE FIRST CHAR: BY mlNG THE DURATION OF THE FIRST LOll
PULSE (START BITl, THE BAUD RATE IS DETER1HNED. USIKS THIS AS
THE IIIDTH OF ONE BIT, 7 SA"PLES ARE IIADE OF THE SERIAL INPUT LINE
AT ONE-BIT INTERVALS, IIITH EACH 'BIT' SHIFTED INTO A TEST BUFFER
t 'TESTB' l. AFTER 7 SAI1PLES, THE TEST BUFFER IS RIGHT-JUSTIFIED
(SHIFTED RIGHT ONE "ORE mEl AND COIIPARED TO THE ASCII 'A' CHAR.
IF A IIATCH IS NOT IIADE, WE WAIT 2 "ORE 'BITS', TItlE THE NEXT LOll PULSE
AND CLOCK IN 7 1I0RE BITS.
IF A "ATCH IS FOUND, AN 'A' CHAR IS ASSU"ED TO HAVE BEEN READ IN
AND THE NEXT TWO BITS ARE SAVED FOR FUTURE DETERI1INATION OF
TRAHsmSION PROTOCOL (PARITV, BITS/CHARl. THE NEXT CHAR IS
CLOCKED IN AND COIIPARED TO 'T' AND "'. IF A "ATCH IS FOUND THEN
THE PROTOCOL IS DETERIIINED AND THE COII"AND BYTES FOR THE 1I0DEI1
( IF ANY ) ARE READ IN AND PROCESSED.
IF A IIATCH IS NOT FOUND FOR 'AT' OR 'AI' THEN liE START OVER ASAIN
LOOKINS FOR AN 'A' CHAR.
I1EANWHILE, IF CHARACTER ECHO INS HAS BEEN ENABLED ( AND BY DEFAULT
IT IS l, mER B IS SENERATING INTERRUPTS AT A FREQUENCY SLISHTLY
GREATER THAN TWICE THE 2400 BAUD ( "AXlI1U" ALLOWABLE BAUD RATE ) FREQUEIiCY.
THE INTERRUPT ROUTINE SAIIPLES THE LEVEL OF THE SERIAL INPUT LINE AND SETS
THE SERIAL OUTPUT LINE TO IIATCH. THIS HAS THE EFFECT OF BLINDLY ECHOIN6
INCOIIIN6 CHARACTERS BACK TO THE HOST COIIPUTER. THIS IIILL BE DONE UNTIL
'AT' OR 'AI' HAS BEEN RECOSNIZEO, AT WHICH POINT THE IRQ IS DISABLED
AND CHARACTERS ARE ECHOED BACK AS CHARACTERS, NOT AS BITS.
0150
0151
0152
0153
0154
0155
015&
0157
0158
0159
01&0
01&1
01&2
0163
01b4
OlbS
01&&
0167
0lb8
01&9
0170
0171
0172
0173
0174
0175
0170
0177
0178
0179
0180
0181
0182
F81t.
F818
F81A
F81C
F81E
F820
FB22
0183 F824
A9
85
85
85
85
85
85
85
0184 F82b
85
0185
0186
0187
0188
0189
85
85
85
AD
09
8D
20
F828
F82A
F82C
F82E
F831
0190 F833
0191 F83b
00
15
74
48
49
4A
49
47
7&
80
75
7D
OD 10
04
OD 10
D7 FD
RESTRT LDA
STA
STA
STA
STA
STA
STA
STA
STA
STA
STA
STA
LOA
ORA
STA
JSR
100
SCCR
REPFLG
ABIT8
ABm
TBlTS
TBlT9
TESTB
DIlFLG
IIAITFG
Bums
sreODE
RCVD
; DISABLE RECEIVER AND TRANSIIITTER
; CLEAR OUT WORKING VAR I ABLES
; PREVENT NUMBERS FROII DIALINS UNTIL 'DIAL' COIIIIAND
; ASSUflE 'OK' -- sreODE MILL BE RESET IF A PROBLEfl ARISES
; SET 'LCD' BIT
1$04
ReVD
NEIICR
; UPDATE RECE I VER RES I STER
PAGE 0005
0192 F839
om F839
0194
0195
019&
0197
FB3D
FB3F
F84!
F844
0198 F84b
07 10
A903
05 14
85 14
7F 79 OC
A9 BO
85 IC
RIIB
LDA
ORA
STA
BBR
LDA
STA
O,IFR-\
103
lIeR
I'ICR
7,ECHOFG,NOIRQ
UBO
CNTBCL
; CLEAR 'RINS' FLAG BIT FROII FLAS RESISTER
; CNTR A = PULSE IIIDTH TIllER
; NO ECHO I F FLAG TURNED OFF
; START mER B TO PERIODICALLY SAIIPLE
; THE SER I AL I "PUT LINE AND ECHO BACK
5-17
Application Note
0199
0200
0201
0202
0203
0204
0205
0206
0207
0208
0209
0210
0211
0212
0213
0214
0215
0216
0217
0218
0219
0220
0221
0222
0223
0224
0225
0226
0227
0228
0229
0230
0231
0232
0233
0234
0235
0236
0237
0238
0239
0240
0241
0242
0243
om
0245
0246
0241
0248
0249
0250
0251
0252
F848
F84A
F84C
F84E
F850
F852
FS53
F855
F857
F85A
FS5D
F85F
A900
85 IE
D7 12
77 78
A9 FF
AS
85 IS
84 IA
8F 11 50
FF 00 FA
67 00
7F 00 FD
F862
F863
F865
FS67
F869
F86A
FS6C
F86E
F86F
FS71
FS73
FS75
F877
F879
F87A
F878
FS7D
F8S0
F882
F8S4
FS8S
FSB7
FSB9
FS8C
F8SE
F890
FS91
F893
F894
F896
F898
F899
F89B
F89D
FS9E
FS9F
F8AI
FBA4
FBA7
58
A5 19
49FF
S543
AS
A5 18
49FF
AA
A9FC
25 14
85 14
8642
86 18
98
4A
85 IA
4F 11
84 IA
AS 00
OA
6047
A206
4F 11
A5 18
AS 00
OA
6647
CA
DO F3
A547
4A
C941
FO 10
98
OA
85 IA
4F 11
7F 00
4C 16
FBAA
4C lC FA
R6500111 • R2424 Intelligent Modem Design
LDA
STA
5MB
RMB
NOIRO LDA
TAY
STA
STY
BBS
L1
88S
RMB
8BR
L2
CLl
LDA
EOR
STA
TAY
LDA
EOR
TAl
LDA
AND
STA
STX
STX
.00
CNTBHL
S,IER
7,IRflFL6
UFF
; THE SAME LOGIC LEVEL ON THE OUTPUT
; LINE,
CNTACL
CNTAL
O,IFR,RINS
7,PA,L!
6,PA
7,PA,L2
; READY CNTR A FOR PULSE-NIDTH MEASUREMENT
CNTAH
ISFF
BDRATH
FD
FD
FD
FS
ISFC
MCR
MCR
8DRATL
CNTACL
lSR
STA
L3
BBR
STY
LDA
ASL
ROR
LDX
BBR
L4
LDA
LDA
ASL
ROR
DEI
BME
LDA
LSR
C"P
BEll
TVA
ASL
STA
B8R
L4A
BBR
L5
B02RES J"P
A
CNTAl
4,IFR,L3
CNTAL
PA
A
TESTB
106
4,IFR,l4
CNTACL
PA
A
TESTB
RIN6
RIHBNS
J"P
IF PHONE IS RINms, so SEE IF IT'S TIME TO ANSNER IT
WAIT FOR RECEIVE LINE TO GO LON
SET SERIAL -OUT LINE LOW TO MATCH
NON WAlT FOR IT TO 60 BACK HISH ( THIS SHOULD
BE THE START BIT OF 'A" )
ALLOW TIftER-B IRQ
6ET PULSE WIDTH COUNT
INVERT IT
AND SAVE IT
CNTACL
ISFF
TVA
FD
;
;
;
;
;
;
;
;
;
L4
TEST8
A
I'A'
FOUMDA
A
CNTAL
4,IFR,L4A
7,PA ,LS
RESTRT
; SET CNTR A = TIME INTERVAL COUNTER
;
;
;
;
SAVE LOll BYT OF COUNT
SET LOW BYTE OF BAUD mER
SET UP COUNTER FOR 1/2 BIT WIDTH, TO
POSlTION SERIAL LINE SAMPLES APPROX.
IN "IDDLE OF BIT,
IIAIT FOR mER
NOli START mER A WITH FULL DELAY (ALSO CLEARS FLA6 )
SET VALUE OF SERIAL BIT (SHOULD BE HIBH)
ROTATE RECEIVE BIT VALUE INTO CARRY BIT
AND RDTATE IT INTO TEST BYTE
CLOCK IN 6 MORE SERIAL BITS
WAlT FOR ONE BIT mE
CLEAR FLAB
BET SERIAL BIT
AND ROTATE IT INTO TESTB
;
;
j
;
;
j
;
;
;
;
;
; CLOCKED IN 6 SITS YET ?
; NO == > BET NEXT BIT
; YES==> IS CHAR AN 'A' ?
; ( RI6HT-JUSTIFY TEST CHAR)
; YES::> CHECK NEXT CHAR FOR 'T' DR '/'
; ND == >IIAIT 2 BIT TlftES
, THEN JU"P TO 'RESTART'
; TO READ I N ANOTHER TEST CHAR
; IIA IT FDR TIMER
; THEN MAKE SURE INPUT LINE IS HI6H
; .,' AND READ I N ANOTHER 7 BITS
.
; CHECK RING COUNT.
5-18
IF PHONE HAS RUNS ENOUGH TIMES
Application Note
R6500111 • R2424 Intelligent Modem Design
PA6E 0001>
0253
0254
0255
0250
0257
0258
om
021>0
0201
0202
0263
021>4
021>5
021>0
om
021>8
0209
0270
027\
0272
0273
0274
0275
0216
0271
0278
om
0280
0281
0282
0283
0284
02B5
0281>
0287
02B8
0289
0290
om
( AS DETER"INED BY S-RE6 0 ) THEN ANSWER IT.
OTHERWISE, 60 BACK TO 'RESTART'
j
4F II FD
AS 18
AS 00
OA
00 48
4F II FD
AS IS
AS 00
OA
1>1> 49
7F 00 FD
FF OOFD
81> 47
98
4A
BS IA
4F II FD
B4 IA
A207
4F 11 FD
AS 18
AS 00
F8AD
F8BO
F882
F8B4
FBB5
FBB7
F8BA
FSBC
F8BE
F8BF
F8CI
F8C4
FBC7
F8C9
F8CA
FBCB
F8CD
FBDO
FBD2
F804
F8D7
F8D9
FBDB
F8DC
FBDE
FBDF
FBEI
F8E3
F8E4
F8Eb
FBE8
F8EA
FeEC
ob47
CA
DO F3
AS 47
4A
C92F
FO 07
C9 54
FO 05
4C lb Fe
FBEF
F774
F8F1
F8F4
F8Fb
FBFB
FBF9
F8FB
F8FE
F900
F902
F903
4F 11 FD
AS 18
A500
OA
bb 4A
4F 11 FD
A5 IB
AS 00
OA
I>b 4B
OA
FOUND AN 'A' CHAR. NOW SAVE NEXT TWO BITS FOR PROTOCOL CHECK,
THEN CHECK FOR 'T' OR '/' CHARS.
FOUNDA BBR
LDA
LDA
ASL
ROR
LI>
BBR
LOA
LDA
ASL
ROR
L7
BBR
BBS
L8
sn
4,IFR,FOUNDA
CNTACL
PA
A
ABITB
4,IFR,Lo
CNTACL
PA
A
ABm
7,PA,L7
7,PA,L8
TESTB
TVA
L9
LlO
LSR
STA
BBR
STY
LOX
BBR
LOA
LDA
ASL
ROR
DEI
BNE
LDA
LSR
C"P
BEQ
CKP
BEQ
JKP
A
CNTAL
4,IFR,L9
CNTAL
107
4,IFR,LlO
CNTACL
PA
A
TESTB
LIO
TESTS
A
"/'
FOUNDS
; WAIT ONE BIT mE
j CLEAR FLA6
; 6ET BIT
; SAVE IT AS BIT 8 OF 'A' ( FOR FOR"AT CHECK 1MS LATER )
j GET BIT 9 ( WAlT ONE "ORE BIT mE )
j CLEAR FLAG
AND SAVE "A' BIT q
WAlT FOR RECEIVE LINE TO 60 HIGH
j NOli IIAlT FOR IT TO SO LOll ( START BIT )
j RESET 'TESTS' FOR 'T' AND' I' CHECK
j DELAY APPROX. 1/2 BIT mE
j ( DIVIDE \'IS8 OF DELAY mE BY 2 )
j START mER
; IIAlT FOR TIMER
j RESTART TlKER ( AND CLEAR FLAG )
; CLOCK IN 7 BITS ONLY ( OF CHAR FOLLOIlING 'A' )
; IIAlT FOR TIKER
j CLEAR FLAG
j GET BIT
j
j
i
;
i
;
i
AND SHIFT IT IN 'TESTB'
7 BITS YET?
NO ==) BET NEXT BIT
YES==) SEE IF THIS CHAR \'lATCHES 'T' DR "/'
( RISHT-JUSTIFY CHAR)
; I,' ?
'AI' CHARS RECEIVED --) FISURE OUT PROTOCOL
'T' ?
'AT' CHARS RECEIVED --) FISURE OUT PROTOCOL
START OVER •••••
FOUNOT
RESTRT
j YES==)
; NO ==)
j YES==)
j NO ==)
FOUNDS 511B
7,REPFLB
; INDICATE REPEAT OF LAST COMMAND STRINS
FOUNDT B8R
LDA
LDII
IISL
RDR
BBR
L12
LOA
LDA
ASL
ROR
4,IFR,FOUNDT
CNTACL
PA
A
TBITS
4,IFR,Ll2
CNTACL
PA
A
T8lT9
; WAIT ONE BIT mE
i CLEIIR FLA6
i SAVE BIT S
IT
0292
0293
0294
0295
om
om
0298
0299
0300
0301
0302
0303
0304
0305
i WAlT ONE LAST BIT mE
; CLEAR BIT-IiIDTH FLAB
i SAVE BIT q
5-19
R6500/11 • R2424 Intelligent Modem Design
Application Note
0306
0307
030B
0309
0310
0311
0312
0313
i BAUD RATE DETmINED. NON FIGURE OUT TRANS"ISSION PROTOCOL
( NU"BER BITS/CHAR, ODD/EVEN/NO PARITY )
F905
F907
F909
F90B
F90D
24 49
10 14
24 4B
10 16
A54B
BIT
BPL
BIT
BPL
LOA
ABIT9
EVEN8
TBm
ODDB
ABIT8
;
;
;
;
;
IS BIT
YES::>
NO ::)
YES:=)
NO :=)
9 OF 'A' : 0 ?
PROTOCOL IS 8 BITS/CHAR, EVEN PARITY
IS BIT 9 OF 'T' : 0 ?
PROTOCOL IS B BITS/CHAR, ODD PARITY
ARE EI6HTH BITS OF 'A' AND 'T'
PAGE 0007
0314 F90F
0315 F911
0316 F913
om F915
0318 F917
om F919
0320 F91B
0321 F91D
0322 F91F
0323 F921
0324 F923
0325 F925
0326 F927
0327 F929
ommB
0329 F920
0330 F92F
0331 F931
0332 F933
0333 F935
0334 F937
0335 F939
0336 F938
0337
0338 F93D
0339 F93F
0340 F941
0341 F943
0342 F945
0343 F947
0344 F948
0345 F94A
0346 F94C
0347 F94E
0348 F950
0349 F952
0350 F954
0351 F956
0352 F9S8
0353 F95A
0354 mc
0355 mE
0356 F960
45 4A
FO lC
244B
10 12
A9 C6
AO 10
DO 20
A9C3
AO IB
DO IA
A9C2
AO 18
DO 14
A9C7
AO 10
DO OE
244B
30 06
AHO
AO 10
DO 04
A9C4
AO 08
EOR
BEg
BIT
BPL
0007 LOA
LDY
BNE
EVEN8 LOA
LDY
BNE
0008 LDA
LDY
BNE
EVEN7 LDA
LDY
SHE
NOPAR BIT
B"1
NOPAR8 LOA
LOY
SHE
HOPAR7 LDA
LDY
85 15
85 40
A2 04
46 43
66 42
CA
DOF9
A5 42
85 18
AS 43
85 IA
57 12
AS 42
C985
9008
A203
57 01
A9 04
DO 12
LABEll STA
STA
LDX
ROTATE LSR
ROR
DEI
BHE
LOA
STA
LDA
STA
RIIB
LDA
CliP
BCC
B03
LDX
RIIB
LDA
BNE
TBlT8
NOPAR
ABITB
EYEN7
1$&6
1$10
LABELl
1$C3
'$18
LABEll
I$C2
'$18
LABEll
I$C7
1$10
LABEll
ABITB
HOPAR7
mo
ISIO
LABELl
UC4
1$08
SCCR
DEFPRO
.04
BDRATH
8DRATL
ROTATE
BDRATL
CNTACL
BDRATH
CNTAL
5,IER
BDRATL
IBAUD3-10
moo
.03
S,PB
1$04
B02
j
j
j
;
;
;
;
THE SA"E ?
YES==) NO PAR ITY USED
NO ==) BIT 8 OF "A" = 0 ?
YES==> 7 BITS, EVEN PARITY, 2 STOP BITS
NO ==) 7 BITS, ODD PAR ITY , 2 STOP BITS
SET VALUE FOR 'RCVC' ( 10 BITS/NORD )
I BRANCH ALIIAYS )
; SET VALUE FOR • RCVC'
; I BRA)
I II BITS/NORD )
SET VALUE FOR 'RCVC'
I BRA)
I II BITS/NORD )
j
j
; SET VALUE FOR 'RCVC' I 10 BITS/NORD )
j I BRA)
I IS BIT 8 OF 'A' = 1 ?
I YES=:) 7 BITS, NO PAR ITY
I NO ==> B BITS, NO PARITY
I SET VALUE FOR 'RCVC' I 10 BITS/NORD )
; I BRA)
; SET VALUE FOR 'Rcve'
I 9 BITS/IIORD )
; SET UP SERIAL CO""AND REGISTER FOR
I BAUD RATE AND PROTOCOL [SAVE PRESENT PROTOCOL J
; DIVIDE BIT -NIDTH mE BY 16
; TO BET BAUD RATE VALUE
; SET UP BAUD RATE TIllER
;
;
;
;
;
;
;
j
DISABLE IRGS
DETER"INE WHAT BAUD RATE WE'RE RUNNINB AT
IS IT GREATER THAN 300 ?
YES== > BRANCH
NO ==> BAUD = 300
SET 'HISPEED' TO 0 ( LOW SPEED )
SET R2424 'I\ODE' CODE (BELL 212A ASYNC )
( BRANCH ALNAYS )
5-20
i
;1
I
I
I
Application Note
0357 F9102
0358 F9104
0359 mb
0360 m8
0301 F9bA
0302mc
0363 mE
0364 mo
0365 Fm
0306 F974
03&7 F97b
03108 F979
0309 F97B
0370 mD
0371 F980
0372 F983
0373 F98S
0374 F987
C925
9008
A20C
D7 01
A9 03
DO 06
A2 18
D7 01
A9 00
859D
AD OA
2HO
05 90
80 OA
AD OA
29F0
0590
80 OA
R6500/11 • R2424 Intelligent Modem Design
moo
B12
B24
BD2
10
10
20
20
CliP
BCC
LOX
SIIB
LOA
BNE
LOX
SIIB
LOA
STA
LOA
AND
ORA
STA
LOA
AND
ORA
STA
IBAUD12-IO
824
t12
S,PB
1$03
BD2
124
S,PB
UOD
Tm
RCVA
UFO
mp
RCVA
xm
UFO
TEIIP
IIlTA
;
;
;
;
;
;
;
IS BAUD GREATER THAN 1200 ?
YES==} !lUST BE 2400
NO ==) IIUST BE 1200
SET 'HISPEED' TO 1 (HIGH SPEED)
SET R2424 "1I0DE' CODE ( BELL 212A ASYNC )
( BRA)
2400 BAUD
; SET R2424 'I\ODE' CODE ( V.22 BIS ASYNC )
; SAVE '1I0DE' CODE IN TEIIPORARY LOCATION
; CHANGE '1I0DE' IN R2424 1I0DEII REGISTERS
; - CLEAR OUT PREVIOUS 1I0DE
; - SET NEil 1I00E
; - AND PROSRAII RECEIVER
; CHANSE TRANSIIlTTER BAUD RATE •••
- CLEAR OUl PREV!DUS 1I0DE
; - SET NEil 1I0DE
; - AND PROSRAII TRANSlIlTTER
PAGE 0008
0375 F9811
0370 F98D
omF990
0378 F993
0379
0380 F995
0381 F997
8C
8C
20
810
OC 10
OC 20
CBFD
41
F7 78
D7 110
STY
SlY
JSR
AND SET 1I0DEII
STX
RCVC
IIITC
NEIICXR
BAUD
; UPDATE R2424 RESISlERS IIITH NEil VALUES
; SAVE BAUD CODE
SIIB
SIIB
7,IRQFLS
5,SCSR
; SET ISR TO PROCESS DELAY TIllE FOR IIAIT-FOR-CARRIER
; SET 'DATA RES EIIPTY' FLAB FOR 'LAST BIT OUT'
PAGE 0009
0383
0384
0385
03810
03B7
0388
0389
0390
0391
0392
0393
0394
; BAUD RATE DElERIIINED. NOli IN COIIIIAND 1I0DE. READ COIIIIAND
; CHARACTERS INTO BUFFER ( INBUFF ). TERIIINATE ON (CR).
F999
mc
F99E
F9AO
F9A2
F9A4
F9AIo
F9A9
0395 mc
0390 mE
0397
0398
0399
0400
0401
0402
0403
mo
F9B2
F9B4
F9810
F9B8
F9BA
F9BC
FF
A2
A5
29
FO
; BRANCH IF 'AI' RECEIVED
; 'AT' RECEIVED --} SET BUFFER INDEX TO 0
; CHECK RECEIVER STATUS
74 4B
00
110
OF
FA
BBS
SETPTR LDX
IIAITIN LDA
AND
BEQ
7,REPFLS,REPEAT
tOO
SCSR
I$OF
IIAITIN
; NO BITS SET ==} NO RECEIVED CHAR, TRY AGAIN
AS 17
7F 79 03
20 51 FF
C5 89
FO ID
C920
FO EA
90 E8
C9 7F
DO 05
A5 8B
20 51 FF
GETCHR LDA
BBR
JSR
mCOD CliP
BEQ
CliP
BEQ
BCC
CliP
BNE
LDA
JSR
SRDR
7, ECHOF6, mCOD
CHROUT
S3
GOTCHR
1$20
IIAITIN
IIAITIN
I$7F
BS
S5
CHROUT
; SEl CHAR FROII RECE I VER BUFFER
; BRANCH IF ECHO DISABLED
; ECHO CHAR BACK TO HOST COIIPUTER
; IS CHAR A (CR) ?
; YES==} SAVE IT AND PROCEED TO 'ALLIN'
; IS INCHAR A (SP) ?
; YES:=) ISNORE IT
; CHAR IS LESS THAN $20 ( CONTROL CODE) --) ISNORE IT
; IS IT A 'DELETE' CHAR? (-- RE"OVE THESE FOUR LINES IF THE
; NO ==) CHECK FOR (BS)
(-- (DELETE) KEY ON THE PARTICULAR
; YES=:) CHANGE IT TO (BS)
(-- TER"INAL USED mH THIS DESISN
j SEND OUT (BACKSPACE>
(-- BACKSPACES THE CURSOR.
5-21
Application Note
0404
0405
0406
0407
0408
0409
0410
0411
F9BF
F9Cl
F9C3
F9C4
F9C6
F9CB
F9CB
C588
DO OA
CA
10 D8
A9 20
20 51 FF
30 CF
CKP
BNE
DELETE DEI
BPL
LDA
JSR
BHI
F9CF
F9DI
F9D3
F9D4
F9D6
F9D8
F9DA
F9DB
95 4C
C589
FO OA
EB
EO 29
DO C6
F7 75
CA
DO CI
GOTCHR STA
CHP
BEQ
INX
CPX
BNE
SHB
DEX
BHE
F9DD
F9EO
F9E2
F9E4
7F
A9
B5
4C
F9E7
A200
0412 F9CD
0413
0414
0415
0416
0411
0418
0419
0420
0421
0422
0423
0424
0425
0426
0427
R6500111 • R2424 Intelligent Modem D.esign
75 07
04
7D
EO FD
BS
S5
GOTCHR
WAITlN
1$20
CHROUT
SETPTR
:
;
;
;
;
IS IT A (BACK-SPACE) ?
NO ==) ACCEPT CHAR
YES==> OVERWRITE PREVIOUS CHAR IN BUFFER
BRANCH IF BUFF POINTER NOT LESS THAN 0
OUTPUT A (SP>
; lim LOWEST VALUE OF POINTER TO 0 ( BRA)
WAITIN
j SAVE CHAR IN BUFFER
; IS IT A (CR> ?
; YES-=> ALL CHARS RECEIVED
; NO ==> INC POINTER AND SET NEXT CHAR
; 1S BUFFER FULL ?
j NO == > SET NEXT CHAR
; YES-=) SET FLAG TO INDICATE ERROR
j KEEP READING UNTIL (CR)
; ( BRA)
ALLIN BBR
LDA
STA
JHP
7,BUFFLG, REPEAT
104
STeODE
CR
j BRANCH IF 40 OR LESS CHARS READ IN
; TOO HANY CHARS ENTERED -- > ERROR
j SET STATUS CODE TO INDICATE ERROR
; AND TERHINATE COHKAND STRING
REPEAT LDX
.00
j
INBUFF, X
S3
ALLIN
141
WAITIN
7,BUFFLG
SET COH"AND STRING POINTER TO ZERO
PAGE 0010
0429
0430
0431
0432
0433
0434
0435
0436
0438
0439
0440
0441
0442
0443
0444
0445
0446
0447
0448
0449
0450
0451
0452
0453
0454
j
j
F9E9
20 F5 F9
F9EC
F9EF
F9F2
20 F2 F9
4C E9 F9
6C 9B 00
ALL COMMANDS AND PARAKETERS HAVE BEEN RECEIVED. NOW EXECUTE
EACH COKMAND, IN ORDER, UNTIL (CR) OR UNRECOGNIZED conKAND (ERROR)
NXTCnD JSR
DocnD
NXTCHD
(CHDVEC)
;
;
;
;
j
FIND CORRESPONDING SUBROUTINE ADDRESS AND
SET UP Junp VECTOR
EXECUTE conHAND.
FETCH NEXT COMnAND
JHP TO conKAND ROliTINE.
EACH conMAND ROUTINE ASSUMES THE X-REG POINTS
TO THE CHAR IN • INBUFF' FOLLOWING THE COMHAND
CHAR, AND LEAVES X-REG POINTING TO THE NEXT
conHAND CHAR. THE Y-REG IS FREE FOR USE AS
A GENERAL SCRATCH-PAD RESISTER.
F9F5
F9F7
F9F9
F9FB
F9FD
FAOO
FA02
FA03
FA05
FA07
FA09
AO
85
C5
FO
D9
FO
C8
CO
DO
A9
85
00
4C
89
OE
47 FA
08
21
F6
04
7D
FNDcnD LDY
LOA
CHP
BEQ
LOOP2 cnp
BEQ
INY
CPY
BNE
LDA
STA
400
INBUFF ,X
S3
GOCR
cnDTBL, Y
FOUND
INunCHD
LOOP2
104
STCODE
j SET UP TABLE INDEX
; FETCH COHHAND BYTE
; IS IT A (CR> ?
; YES:=> TERnINATE conMAND STRING
j NO ==> A HATCH FOUND ?
; YES::) 6ET VECTOR
; NO :=) TRY NEXT TABLE ENTRY
; END OF TABLE ?
; NO ==> GO AGAIN
j YES:' > ERRDR ...
5-22
R6500/11 • R2424 Intelligent Modem Design
Application Note
0455
0456
0457
0458
0459
0460
0461
om
0463
0464
0465
FAOB
AO 21
SOCR
FAOD
FAOE
FAOF
FAIO
FAI3
FAI5
FAI8
FAIA
FAIB
98
OA
A8
B9
85
89
85
EB
60
FOUND TYA
ASL
TAY
LOA
STA
lDA
STA
INt
RTS
69 FA
9B
6A FA
9C
LDY
'NU~C~D
; SET POINTER TO (CR)
CO~MAND
; COIIIIAND FOUND. SET ASSOCIATED VECTOR
; ~ULT INDEX BY 2
VECTBL, Y
CIIDVEC
VECTBL+I, Y
mVEC+I
j GET VECTOR
; AND SET UP COIIIIAND JUIIP
; INC INBUFF INDEX TO POINT TO FIRST
; BYTE FDLLOWING CO""AND BYTE
PAGE 0011
0467
0468
0469
0470
0471
0472
0473
0474
0475
0476
0477
0478
0479
0480
0481
0482
0483
0484
0485
0486
0487
0488
0489
0490
0491
0492
0493
PHONE IS RINSING.
FAIC
FAIE
FA20
FA22
FA24
FA26
FA28
FA2A
FA2C
FA2E
FA30
FA32
FA34
FA37
FA39
FA38
FA3D
FA3F
57 12
07 10
A9 AO
85 14
AS 40
85 IS
AS 42
85 18
AS 43
B5 IA
A9 02
8S 7D
20 E8 FE
E6 87
AU7
C4B6
FO 03
4C 16 F8
RINGN6 RIIB
RIIB
LDA
STA
lOA
STA
LOA
STA
LDA
STA
LDA
STA
JSR
INC
LDY
CPY
BEQ
JIIP
51
SI
SO
ANSWER
RESTRT
FA42
FA44
F7 78
20 OD Fe
ANSIIER SIIB
JSR
7,IRQFLS
AAA
5,IER
O,IFR-I
UAO
IICR
DEFPRO
SCCR
BDRATL
CNTACL
BDRATH
CNTAl
1$02
STCODE
RESPNS
ANSIIER IT ?
; DISABLE IRQ
; RESET PAO ( 'PHONE IS RINGING' I FLAG
; SET IICR fOR SERIAL 110
; SET SERI AL PROTOCOL TO 1I0ST RECENT VALUE
; SET SERIAL CLOCK TO 1I0ST RECENT VALUE
; SET 'STeODE' TO 'RINS' RESPONSE
;
;
;
;
;
;
AND OUTPUT APPROPRIATE IIESSAGE
ADD I TO RIMG COUNTER
NOli CHECK FOR RING COUNT
IS THE RING COUNT UP TO THE SET LIMIT VET ?
YES== > SO ANSIIER THE PHONE !
NO==> START OVER READING IN CHARS FROII HOST SVSTEII
; CHANGE ISR TO PROCESS DELAY mE FOR WAIT-FOR-CARRIER
; NOW SO ANSWER PHONE ( 'JSR' WILL PUT 2 RETURN
ADDRESS 8YTES ON THE STACK. THESE WILL BE
DISCARDED AT THE END OF THE (CR) COMMAND
-- AT LABLE 'MOWAIT' -- FOLLOWED BY
A •J"P RESTRT' )
PAGE 0012
0496
om
0498
0499
0500
OSOI
0502
0503
;
FA47
FA48
FAS4
FA57
FASD
FA63
FA6S
2C
30
3B
41
49
53
00
CIIDTBL .8YT
.BYT
.BYT
.m
.8YT
.BYT
.BYT
,
----- THE ORDER OF THESE TIIO TABLES MUST MATCH ----
'0123456789."
$3B,'=?'
' ACDEFH'
'IMOPQR'
'STVXZ'
$00
; IIARKER FOR {CR) COMMAND
5-23
--~
~---
-
--------
~-----.
-------
Application Note
0504
0505
0506
0507
050B
0509
0510
0511
0512
0513
0514
0515
0516
0517
0518
051'1
0520
0521
FA69
FA6B
FA77
FAB3
FA89
FA95
FAAI
FAAB
IE FB
3C FB
3C FB
5B FB
00 FC
B8FC
3AFD
EO FD
R6500111 • R2424 Intelligent Modem Design
YECTBL .lIoR
.lIoR
.IIOR
.1I0R
.IIOR
.lIoR
.IIOR
.IIOR
CONNA
DIGIT ,DI61T ,Dl6IT ,DI61T ,DI61T ,DI6lT
DI61T ,Dl6IT ,DIGIT ,DISIT ,DIGIT ,DIGIT
mIC,EQUAL, QUESTN
AAA ,CCC ,ODD ,EEE ,FFF ,HHH
111 ,""",oDo,PPP ,9QQ,RRR
SSS, TTT ,YVY,m,zzz
CR
; ---------> MUST BE LAST ENTRY IN TABLE
INITIAL VALUES FOR S-REGISTERS, IN ORDER FRO" 0 TO 16
FAAD
FAB2
FAB6
FABA
FABD
STBL
00
08
06
FF
00
.BYT
.BYT
.BYT
.BYT
.BYT
0,0,43,13,10
8,2,30,02
6,7,70,50
$FF ,$FF ,$FF
0
PASE 0013
0523
0524
0525
0526
0527
0528
0529
0530
0531
0532
0533
0534
0535
0536
0537
0538
0539
0540
0541
0542
0543
0544
0545
0546
0547
0548
0549
0550
0551
0552
0553
0554
0555
0556
THIS ROUTINE INITlALlZES PROGRA" YARIABLES AND
CPU REGISTERS.
FABE
FACO
FAC2
FAC4
FAC7
FACA
FACC
FACF
FADI
FAD4
FAD7
FAD9
FADC
FADF
FAE2
AHO
85 11
85 12
80 00
80 OB
A904
8D OD
A903
80 OA
BD OA
A908
80 OC
BD DC
80 DE
BO OE
FAE5
FAE7
FAE9
FAEB
FAEO
FAEF
FAFI
FAF3
FAF5
FAF7
FAF9
FAFB
FAFD
FAFF
FBOI
A9 00
8583
8587
857F
8576
857B
A980
B579
B5 7A
857E
85 7C
A92F
85 42
A9 00
85 43
20
20
10
10
20
10
20
10
20
INITSII LOA
STA
STA
STA
STA
LOA
STA
LOA
5TA
STA
LOA
STA
STA
STA
STA
LOA
STA
STA
STA
STA
STA
LOA
STA
STA
STA
STA
LDA
STA
LDA
5TA
1$00
IFR
lEft
XNTD
INTB
1$04
ReVD
'$03
RCYA
; DISABLE ALL IRQS
; SET UP R2424 TO DEFAULT VALUES
xm
1$08
RCYC
xm
RCYE
XMTE
.00
5SETFS
51
XCoDE
0lLFL6
RSLTF6
mo
ECHOF6
DUPLEX
YCODE
SPKRFS
I(BAUOI2
BDRATL
.)BAUDI2
BORATH
;
;
;
;
;
;
SET FLAG TO INDICATE SoRES HAS NOT 8EEN SET
SET RIMS COUNT TO 0
STANDARD 'CARRIER' RESPONSE
DISA8LE DIALIN6
ENABLE RESULT RESPONSE
ENABLE ECHO
;
;
;
;
FULL DUPLEX
SET UP FOR YERBAL RESPONSE
SET SPEAKER FOR 'NI' CONNAND OPERATION
SET DEFAUL T BAUD RATE TO 1200 BAUD
5-24
Application Note
0557
0558
0559
0560
0561
0562
0563
0564
0565
0566
0567
0568
0569
0510
0571
FB03
FB05
FB01
F809
FBOB
FBOD
FBOF
FBII
FBU
FBI6
FBI1
FBI9
FBIB
FBID
AHO
85 40
A986
8584
A9 00
B5 85
AOII
B9 AD FA
91 84
88
10 F8
A589
85 4C
60
R6500111 • R2424 Intelligent Modem Design
LOA
STA
LDA
STA
LDA
STA
LOY
SLOOP LOA
STA
DEY
BPL
LOA
STA
RTS
.FILE
mo
DEFPRD
I50
SREGP+!
111
STBL, Y
(SREGP), Y
SLOOP
S3
IN8UFF
; SET DEFAULT SERIAL PROTOCOL TO B BITS, NO PARITY
; BASE POINTER FOR S-REGISTERS
; SET UP IIISH-BYTE OF SoRES POINTER
; INITIALIZE S-REGS
; INITIALIZE COftftAND STRINS TO [NULL)
ftDftlOB
PAGE 0014
0573
0574
0575
0576
0577
0578
0579
0580
0581
0582
0583
0584
0585
0586
0587
0588
0589
0590
0591
0592
FBIE
FB20
FB22
FB24
FB26
FB2B
FB21\
mc
FB2E
FB31
FB33
FB34
FB36
F831
om FB39
0594 FB3B
0595
0596
0597
0598
0599
0600
0601 mc
0602 FB3F
0603 FB41
0604 FB44
0605 FB46
0606
0607
0608
0609
; THE FOLLDIiINS ARE ALL THE CO""AND ROUTINES TO EXECUTE TilE
'AT' COMANDS ....
',' CO""AND
CO""A STX
LDX
BEll
LDA
STA
LDA
STA
DNESEC LDY
IIAlTB BBR
LOA
8690
1\68E
FO 15
Anc
85 IC
1\9£0
B5 IE
AO 10
SF 11 FD
AS IC
88
DO F8
CA
DO F3
AD 90
60
--- NAil FOR ONE PAUSE mE
mp
58
MDDLAY
I{DLYTl"
CNTBCL
I>DLYTI"
CNTBIIL
IDlYHIB
5,IFR,IIAITB
CMTBCl
DEY
SHE
DEI
BHE
MDDlAY LDX
RTS
IIAITB
ONESEC
TE"P
; SAVE I NBUFF PO INTER
; 6ET VALUE OF SoRES 8 ( DELAY TI"E )
i IF ZERO THEN NO DELAY
; START mER-B
;
;
;
;
;
;
I
I S liftER B DONE YET ?
YES == > CLEAR mER FLAG
DONE COUNTING YET ?
NO ==) KEEP 60lNS
ANY ftORE I-SEC DELAYS ?
YES=:) ONE "ORE mE ••••
RESTORE INBUFF POINTER
;.11111111......11............11......111111........11....1111111111.........11
; DIAL A NUftBER
7F 76 15
A9 01
2C OE 20
FO FB
B548
DI6IT BBR
LDA
MAITRE BIT
BEQ
LDA
7,DILFLG,DI6ERR
1$01
I"TE
IIA1TRE
IN8UFF-1,X
i IF NU"BER IS NOT TO BE DIALED --) ERROR
i IIAlT UNTIl DIAL BUFFER E"PTY
; GET ASCI I NU"BER FRO" BUFfER. IN THIS CASE, THE
CO""AND BYTE IS TilE PARA"ETER. SINCE THE X-RES
HAS ALREADY BEEN UPDATED TO POINT TO THE BYTE
FOLLOIlING TillS DIGIT ICO""AND, THE BASE OF THE
CO""AND BUFFER HAS TO BE SHIFTED DOliN ONE BYTE
5-25
--
-
--
--
-
-
---------
Application Note
0610
0611
0012
0613
0614
0615
R6500/11 • R2424 Intelligent Modem Design
FB48
FB4A
FB4C
FB4E
FBSO
FB53
C9 23
DO 02
A90E
29 OF
SO 00 20
60
CliP
BHE
LDA
0162 AND
STA
gDISn RTS
0618 FB54
0619 FB56
0620 FB58
0621
0622
0623
A9 04
85 70
4C EO FD
DISERR LDA
STA
J"P
om
....
;
;
;
;
;
0162
UOE
UOF
XMTO
TO COMPENSATE.
IS THE DIAL DIGIT A 't' ?
NO ==} BRANCH
YES==> EXCHANGE CHAR FOR R2424'S '.' NUMBER
MAKE IT ABSOLUTE
AND DIAL •••
0017
'ERROR'
104
STeDDE
CR
; TERMINATE COMMAND STRING PROCESSING
; ***********tffU***tH*****tfttntffu**n*****fHffff********ttffU***UfU**
0624
; SEMICOLON COIIMAND
0625
---
DONE DIALING - RETURN TO CO""AND 1I0DE
0626
0027
0628
0629
0630
0631
0632
0633
FB5B
FB5E
FB60
FB62
FB6S
FB67
FB69
7F
06
A9
2C
FO
A9
SD
76 11
76
01
OE 20
FB
FF
00 20
SEMIC BBR
ASL
LOA
SEm BIT
BEQ
LDA
STA
7,DILFLG,SEIIERR
DILFLS
10\
xm
SE"12
tsFF
XIITO
; BRANCH IF • i' ENTERED WHILE NOT DIALING (ERROR)
; TURN OFF DIAL FLAG ( S80 --I SOO )
; WAIT UNTIL DIAL REGISTER IS EMPTY
; E"PTY YET ?
; NO ==) KEEP WAITING
; YES=-> FINISH DIALING
PABE 0015
0034
0635
0636
0637
063B
0639
0640
0641
0642
0643
0644
0645
0646
0647
0648
0649
0650
065!
0652
0653
0654
0655
0656
0657
0658
0659
0660
FB6C
F86E
77 80
60
FB6F
FB7!
FB73
A9 04
85 7D
4C EO FD
7,MAITFS
; PREVENT (CR> COllllAND FRO" BOINB ON-LINE (mAIN IN
CO""AND MODE)
1$04
STeODE
eR
; SET sreODE FOR ERROR
RMB
RTS
SEIIERR LDA
STA
JIIP
.,
••• AND TERMINATE COIIIIAND STRING EXECUTION
; ftttftfftftttttftftfntffttfftt**Htf****ttffftttffttfffffHtttfltffftfffftfff
;
FB76
FB79
FB7B
FB70
FB7F
FBB!
FBB4
FBB6
FB88
FBBB
FBBD
FB8F
FB91
F893
FB96
FB98
7F SBB
A900
8598
85 99
859A
20 BE FD
80 36
859S
20 8E FD
BO 15
AHB
84 99
85 98
20 BEFD
80 OA
A4 99
I:'
---
CDIIIIAND
EQUAL BBR
LOA
STA
STA
STA
JSR
BCS
STA
JSR
BCS
LDY
STY
STA
JSR
BCS
LOY
SET S-RESISTER TO A VALUE
7,SSETFG,OISERR
100
NUll
NUll+!
NUII+2
GETNUII
EQ4
NUll
GETNUII
m
NUll
HUII+!
NUll
SETNUII
E92
NUlltl
; IF FLAG IS CLEAR -- > 'ERROR"
; CLEAR OUT TEMP BUFFER
;
;
;
;
;
;
GET FIRST CHAR FRDII BUFFER
IF IT IS NOT A NUIIBER I THEN ASSUIIE ZERO
SAVE NUIIBER IN TEIIP BUFF
IS THERE ANOTHER NUIIBER ?
NO ==> ONES DIGIT ONLY --I BRANCH
YES:=) !lOVE ONES DIBlT OVER
AND I NSERT TENS D16 IT
; IS THERE A THIRD NUIIBER ( HUNDREDS DIGIT I ?
; NO == > ALL NUltBERS FETCHED -- > BRANCH
; YES==> "OVE ONES AND TENS DISITS
5-26
1
Application Note
Obbl FB9A
om FB9C
0663 FB9E
0664 FBAO
0665 FBA2
066& FBA4
0&&7 FBA&
0&68 FBA9
0669 FBAB
0670 FBAD
om FBAF
0672 FBBI
om FBB4
0674 FBB7
0&75 FBB8
0676 F8BA
0677 FBBC
FBBE
om FBCO
06BO FBC2
O&BI FBC4
0&82 FBC6
0&83 FBC8
0&84 FBCB
0685 FBCE
068& FBDO
0&87 FBD3
0&88 FBD6
0&89
0&90 FBD8
0691 FBDA
0&92 FBDD
0&93 FBEO
0094 FBE2
om
849A
A498
8499
85 98
AS 99
FO 07
20 EC
65 98
85 98
A59A
FO OB
20 EC
20 EC
18
65 98
8598
A598
AO 00
91 B4
A59&
DO 12
AUF
20 OA
80 OA
AUF
20 OA
80 OA
DO 10
A9
00
80
A9
00
R6500/11 • R2424 Intelligent Modem Design
STY
LOY
STY
NUK+2
NUK
Nun+l
NUK
NUK+!
EQ3
KULT10
NUH
NUH
Nun+2
EQ4
nULTlO
KULT10
STA
EQ2
FB
FB
FB
10
10
20
20
10
OA 10
OA 10
10
OA 20
OVER AND INSERT HUNDREDS
DIGIT IN FRONT
LOA
BEQ
JSR
ADC
STA
EQ3
LOA
BEQ
JSR
JSR
CLC
ADC
STA
E04
LOA
LDY
STA
LOA
BNE
NOSLFT LOA
AND
STA
LOA
AND
STA
BNE
; GET TENS DI6IT
; IGNORE IT IF IT' S ZERO
; IF >0 , KULTIPLY BY 10
j ADD IN ONES DIBIT
; AND SAVE TENS+ONES
j GET HUNDREDS DIGIT; IS IT : 0 ?
; YES::> FINISHED CONVERTING TO HEX
; NO == > nULTIPL Y HUNDREDS 0I 6lT BY 10
AND BY 10 AGAIN ( t 100 )
NUK
NUn
NUH
100
(SRESP), Y
SI&
SLFTST
UEF
RCVA
RCVA
UEF
IHTA
InTA
OED
; ( BRANCH ALWAYS )
SLFTST LOA
ORA
STA
LOA
ORA
Uto
j
RCVA
RCVA
IflO
I"TII
j
; ADD IN TENS+ONES DISIT
; SAVE TOTAL HEX VALUE
; SO TO SELF -TEST ?
j NO => STOP SELF TEST
j NO SELF TEST -- RETURN TO NORMAL OPERATING HODE
j DISABLE SELF-TEST BITS IN R2424
START SELF -TEST
SET SELF-TEST BITS IN R2424
PASE 0016
0695 FBE5
om FBE8
0&97 FBEB
0698
om FBEC
0700 FBEE
0701 FBEF
0702 FBFO
0703 FBF2
0704 FBF3
0705
0706
8D OA 20
20 CB FD
60
859D
OA
OA
65 9D
OA
60
QEO
1m
STA
JSR
RTS
KUL TI 0 STA
ASL
NENCXR
j
TE"P
A
j SAVE VALUE IN mp STORASE
; "ULTlPL Y BY 2 ( t 2 )
j AND BY 2 ASAIN ( t 4 )
j THEN ADD IN ORIGINAL VALUE (CARRY FLAG ALWAYS CLEAR )
j "ULTIPLY BY 2 AGAIN ( f 10 )
ASL
A
ADC
ASL
RTS
A
mp
UPDATE R2424 SCRATCH-PAD REGISTERS
j fHffHfffflfHfffffffffffffffffffffffffffftfffffffttfttftfttffttlflflftflftff
0707
0708
0709
0710 FBF4
071l FBF7
; '1' CO""AND
20 40 FF
AO 00
QUEm JSR
LDY
---
CRLF
100
SEND BACK CONTENTS OF S-RE6ISTER
j
PREFACE OUTPUT IIITH (CR/LF>
5-27
I
II
I'
I
Application Note
0712 FBF9
0713 FBFB
0714 FBFE
0715 FCOO
0716 FC03
0717 FC06
FC07
0719 FC09
0720 FCOt
0721
0722
om
81 84
20 9F
AO 02
Bns
20 51
SS
10 F7
20 40
60
FD
00
FF
FF
R6500111 • R2424 Intelligent Modem Design
LDA
JSR
LDY
QUES3 LDA
JSR
DEY
BPL
JSR
RTS
(SREGP), Y
HX2ASC
102
NUII,Y
CHRDUT
;
;
;
;
GET VALUE OF S-RES
AND CONVERT IT TO ASCll
SEND OUT 3 CHARS
SET CHAR FRoII 'NUI'I' BUFFER
; LAST CHAR?
; NO == > SEND OUT NEXT ONE
; YES-=) SEND OUT TURN ON 'CC' BIT
; IN IIODE" REGISTER
j
j
QCCC
acce
mB
IIIT9
BRANCH ALWAYS )
PARAIIETER =0 --) TURN OFF 'CC' BIT
j (
j
1m
NEWCX
; UPDATE 1I0DEII RESISTERS
PABE 0017
0756
0757
0758
0759
0760 FC44
0761 FC46
0762 FC49
; tfffttfUfftfffftUtftfffffffftftfffffffffffttfffHfffftttffffttffHfffffff**f
119 20
OD 09 20
BD 09 20
ODD
LDA
ORA
STA
1$20
xm
; PUT IIODEII IN ORIGINATE HODE
; AND SET TO DIAL
xm
5-28
Application Note
om
0704
om
0166
om
0168
FC4C
FC4F
FeSI
FCS3
FCS6
FC59
07D9mc
0770 FC5E
0171 mo
0172 FC61
0173 FC63
0774 FC6S
0175 FC68
071bFCb9
0771 FC6B
0118 FC6D
om FC6F
0780 FC71
0781
AD 00 20
29EF
0948
80 00 20
20 CEFD
2C 08 20
10 FB
AS 8E
48
AS BC
85 BE
20 IE FB
68
8S 8E
F7 76
F1 80
7777
60
0782
0783
0784
0785
0786
0787
0788
0789
0790
om
0792
0793
om
0795
om
0791
om
0799
0800
0801
0802
0803
OB04
OB05
0806
OB07
080B
0809
0810
0811
0812
0813
R6500/11 • R2424 Intelligent Modem Design
LOA
AND
ORA
STA
JSR
WAlTDL BIT
BPL
LDA
PHA
LOA
STA
JSR
PLA
STA
SI'IB
SI'IB
RI'IB
RTS
XI'ITD
UEF
1$48
XI'ITD
NEWCI
Il'lT8
WAlTDL
58
; SET CR9-! AND DTR:l
; UPDATE TRANSI'IITTER RESISTERS
; WAIT UNTIL DLO: 1
; DELA~ '56' NUI'IBER OF SECONDS. USE 'COM"A'
COMI'IAND FOR DELA~ ROUTINE. TO DO THIS, liE HAVE TO
SAVE THE ORIBINAL VALUE OF '58' ( IN THIS CASE ON
THE STACK ) AND THEN SUBSTITUTE THE VALUE FOR '56'
INTO '58'. THIS WILL DELA~ '56' SECONDS. AFTER
THE DELAY IS FINISHED, liE POP THE ORIGINAL '58'
; VALUE OFF THE STACK AND RETURN IT TO 'SS'.
; SET 'DIAL FLAS' TO DIAL SUBSEQUENT NUIIBERS
; ENA8LE WAlT-FOR-CARRIER DELAY
; SET FOR NORIIAL DIALlN6
56
58
COI'IMA
58
7,DILFLB
1,WAITF6
7,REVFL6
; tfttfnffnntn.. ftttUtttntn*n*tt************nff.. nn****ffftn*n*nu
; 'E' COIII'IAND
FC72
Fe7S
FC77
FC79
FC7B
FC7D
FC7F
20 BE FD
BO 06
FO 04
F779
DO 02
77 79
60
EEE
JSR
BCS
BEQ
EOIIE SIIB
BNE
EZERO RMB
QECHO RTS
---
T06BLE ECHOING CHARS BACK TO HOST SYSm
; 6ET PARAMETER, 1F ANY
; BRANCH IF NO PARA"ETER ( ASSUME ZERO )
j BRANCH IF PARAIIETER : 0
; SET ECHO FLA6
j ( BRA)
j CLEAR ECHO FLA6 ( NO ECHO )
BETNUM
EZERO
EZERO
7,ECHOF6
GECHO
7,ECHOF6
j *ftn**tfftftUfU**fUfffffftfftffUfftfftttUftftfftfffttttf**fffUffnftfff
; •F' COMI'IAND
FCBO
FCB3
FCB5
FCB7
FC89
FC8B
FC8D
208EFD
80 06
FO 04
F7 7A
DO 02
77 7A
60
FFF
JSR
BCS
BEQ
FONE SKB
BNE
FIERO R"B
QFFF RTS
---
SET HALF/FULL DUPLEX
;
;
;
;
;
;
SETNUM
FIERO
FIERO
7,DUPLEX
QFFF
7,DUPLEX
GET PARAMETER, IF ANY
IF NONE, ASSUIIE ZERO
BRANCH IF : 0
SET FOR FULL DUPLEX
( BRANCH ALWAYS )
SET FOR HALF DUPLEX
; ftfftftfftftftffftfftftffffffffU*ftfffffffftflffftffffffffffftft**fHffffffff
j
FCBE
FC91
FC93
FC9S
20
BO
FO
AD
8E FD
14
12
OD 20
'H' COMMAND
HHH
JSR
BCS
BEQ
HIAND2 LOA
--6ETNU"
HHZERo
HHZERO
IMTD
0814
0815 m8
0816 FC9A
09 40
8D OD 20
ORA
STA
1$40
I11TD
ON/OFF HOOK
;
;
;
;
;
GET PARAMETER, IF ANY
IF NO PARAMETER, ASSU"E ZERO
BRANCH IF PARAMETER : 0
PARAI'IETER IIUST BE 1 OR 2 ION THE R2424, THEY
FUNCTION THE SAKE)
j
SET xm CRG : 1
5-29
Application Note
R6500/11 • R2424 Intelligent Modem Design
PAGE 0018
0817
0818
0819
0820
0821
0822
OS23
0824
0825
0820
0827
OS28
0829
0830
0831
0832
0833
0834
0835
0836
0837
0838
0839
0840
0841
0842
0843
0844
0845
0846
0847
0848
0849
0850
0851
0852
0853
0854
0855
0856
0857
0858
0859
0860
0861
0862
0863
0864
0865
0866
0867
0868
0869
0870
FC9D
FCAO
FCA2
FCA5
FCA7
FCAA
FCAC
FCAF
FCB2
FCB4
FCB7
FCBA
AD
09
SO
DO
AD
29
80
AD
29
SD
20
60
00
40
00
10
00
AF
00
00
BF
00
CB
10
10
20
20
10
10
FD
RCVD
LOA
ORA
STA
BHE
HHZERO LOA
AND
STA
LDA
AND
STA
HHSET JSR
DHHH RTS
1$40
; SET RCV CRQ = 1
; ( BRANCH ALWAYS )
; SO OFF -LI NE (HANG UP I
RCVD
HHSET
xm
UAF
; SET XKIT CR9 = 0
XIITD
ReVD
I$8F
RCYD
NEIICXR
; SET RCV CR£! = 0
; UPDATE liDDEll'S INTERNAL REGISTERS
; ffffftt***ttn****f**nnf***ftftfffffftffffffUUff******H****************n
j
FeBB
FeeE
FCCI
FCC3
FCC5
FCC7
FCC9
FCCS
FCCE
20
20
90
FO
AO
DO
AO
20
60
40 FF
8E FD
06
04
2D
02
31
33 FF
'I" CoIIIIAND
III
JSR
JSR
BCS
BEQ
1I0NE LOY
BNE
IIZERO LDY
QII
JSR
RTS
---
RESPOND WITH CHECKSUK OR PRODUCT CODe
CRLF
SETNUII
IIZERO
!IlERO
tCHKSUII-IIS6
IIOYE DOWN TO NEXT LI HE
6ET PARAIIETER I IF ANY
j BRANCH IF NO PARAKETER ( ASSUIIE ZERO I
; BRANCH IF PARAHTER = 0
j SEND OUT CHECKSUII
j
j
Gil
tPCODE-IIS6
!lSSDUT
; SEND OUT PRODUCT CODE
; ftftfftffffffftttttftfffttfftffftt ....tttttftftltltffftffttftltffffffffffftftf
; 'II' eOllllAND
FCCF
FCDI
FCD4
FCD6
FCDB
FCDA
FCDC
FCDE
FCEO
FCE3
FCES
77
20
BO
FO
C9
DO
F7
67
4C
E7
60
7C
8E FD
OD
OB
0I
02
7C
01
E5 FC
01
111111
RIIB
JSR
Bes
BED
CliP
8NE
1I110NE SIIB
III1TWO RIIB
JIIP
III1ZERO SIIB
QllfllI RTS
---
ENABLE/DISABLE SPEAKER
7,SPKRF6
6ETNU"
""ZERO
IImRO
tOI
fI"TIiD
7,SPKRFG
6,PB
QIIIIII
6, PB
; DI SABLE SPEAKER FLAG
j GET PARAIIETER, IF ANY
j IF NONE I ASSUIIE ZERO
j BRANCH IF = 0
; IS IT ONE?
j NO ==> LEAVE SPEAKER FLAG DISABLED
j YES==) ENABLE FLAG TO TURN SPEAKER DFF AT CARRIER TONE
j TURN ON SPEAKER
j
DISABLE SPEAKER
; fffftftffffffffttttttffffffffftltffffffffftffffttffltfffffffffftttfUtfftttftt
; '0' COIIIIAND
FCE6
FCE9
FCEB
20 95 FC
F7 80
4C F6 FD
000
JSR
SIIB
JIIP
---
SO ON-LINE
HIAND2
7, IIA 1TF6
CARm
; PICK UP PHONE (60 OFF-HOOK)
j ENABLE CARRIER TEST
; AND 60 DIRECTLY TO CARRIER-DETECT ...
5·30
II
I
I
Application Note
0871
0872
0873
0874
0875
R6500/11 • R2424 Intelligent Modem Design
j fttffttftftf.*Utf.tt**Uftt..nff*.n .....f**fftftf.n**fUUf**fttfUfHUH
'P' COKftAND
j
om FCEE
0877 FCFl
AD DB 20
29 FD
PPP
---
PULSE DIAL
xm
LOA
AND
; SET PULSE/TONE BIT TO 0
UFD
PASE 0019
0878
0879
oe80
0881
0882
0883
OSB4
0885
088&
0887
0888
0889
0890
0891
0892
0893
0894
0895
0896
0897
0898
0899
0900
0901
0902
0903
0904
0905
0906
0907
0908
0909
0910
0911
0912
0913
0914
FCF3
FCF&
FCF9
80 OB 20
20 CE FD
60
STA
JSR
RTS
I"TB
NEWCX
j
UPDATE TRANSftITTER RESISTERS
j .nuf**...fUUU.uffttfttn.ff..ffftUf ....****UftHH.ttfU .... fUU.ftU
j
FCFA
FCFD
FCFF
FOG 1
F003
FD05
FD07
20 8E FD
BO 06
FO 04
F7 7B
DO 02
17 7B
60
'0' CO"KAND
ggg
JSR
BeS
BEQ
QGONE 5"8
BHE
Q9ZERO RKB
99
RTS
---
TOGSLE SENDING RESULT COOE/ftESSAGE
GETNU"
9GZERO
GGZERO
7,RSLTFG
GO
7,RSLTFG
;
;
;
;
SET PARAKETER, IF ANY
BRANCH IF NO PARA"ETER ( AS5UftE ZERO )
BRANCH IF PARA"ETER : 0
SET FLAG (ENABLE PRDftPTS )
j ( BRA>
; CLEAR FLAB (DISABLE PROKPTS l
; .ntt.u.tt.tttt.ft.f.UUftftUUfU....ttftffttfU.....tfftftf.tfftfffUU ••
I 'R' COKKAND
FD08
FDOB
FIlOD
FOOF
7F
A5
C9
FO
7b 28
41
18
21
FD 11
FDI3
FIH 5
FDI7
0916 F02F
0917 FD32
77
F7
A9
00
80
A9
20
8D
A9
2D
09
BO
20
60
7b
77
20
09
09
BF
00
OD
BF
OD
20
00
CB
0918
0919 FD33
0920 FD35
0921 FD37
A9 04
85 7D
4C EO FD
FillA
FDIO
FOIF
FD22
F025
FD27
F02A
om mc
RRR
20
20
10
10
20
20
FO
QRRR
--- SET DIAL FOR REVERSE KDDE
( TO DIAL AN ORI6INATE-DNLY "ODE" )
BBR
LOA
CKP
BEg
7,DILFLG,RERROR
BAUD
124
QRRR
RKB
S"B
LDA
ORA
STA
LDA
AND
STA
LDA
AND
ORA
STA
JSR
RTS
7,DILFLG
7,REVFLG
RERROR LOA
STA
J"P
1$20
; BRANCH IF 'R' ENTERED WHILE NOT DIALING (ERROR)
; ARE WE RUNNING AT 2400 BAUD?
; YES-:) 'REVERSE' KDDE NOT EASILY DONE AT 2400 SINCE
j
'ANSWER' TONE SOES AWAY AFTER 3 SECONDS,
; NO ::) 30011200 --) DISABLE FURTHER DIALING
j SET FLAG TO INDICATE REVERSE DIALING
; SET 'DRS' BIT TO I
X"T9
m9
UBF
; SET RECEIVER'S 'CRG' BIT TO 0
RCVD
RCVD
UBF
X"TD
1$20
mD
NEWCXR
1$04
STeODE
eR
; SET TRANS"ITTER '5 "CR9' BIT TO 0
AND 'DATA' BIT TO 1
; UPDATE REGISTERS
; AND RETURN .....
; SET sreODE FOR ERROR
AND TmlNATE COMMAND STRING EXECUTION
5-31
!
•
Application Note
0922
0923
0924
0925
0926
0927
0928
0929
0930
0931
0932
0933
0934
0935
om
0937
0938
R6500/11 • R2424 Intelligent Modem Design
;tfttfuttttUUtttffftlffltfffHHtlfftUUUftUUttttffUtttfttttfffffffffff
; '5' CD""AND
FD3A
mc
FD3E
FD41
FD43
FD45
FD47
FD4A
FD4C
FD4E
FDSO
FD52
A9 B6
8584
20 BE FD
BO 14
FO 12
8598
20 8E FD
BO 04
690A
85 9B
AS 98
IB
SSS
SS2
LOA
STA
JSR
BCS
BEQ
STA
JSR
BCS
ADC
STA
LDA
CLC
---
IDENTIFV S-RESISTER FOR FUTURE ACCESS
I(SO
SRESP
; START IIITH BASE ADDRESS
emu"
;
;
;
;
;
;
;
9SSS
9SSS
NU"
SETNU"
SS2
110
NU"
NU"
SET NUftBER DF S-RE6ISTER
BRANCH IF ND PARA"ETER FOUND
BRANCH IF PARA"ETER = 0 ( ALREADV SET UP J
SAVE VALUE
6ET DNES DI61T. IF ANV
BRANCH IF DNLV DNE DI&IT
TENS DI6lT CDULD ONLY BE A 'I'
PA6E 0020
0939
0940
0941
0942
0943
om
0945
0946
0947
0948
0949
0950
0951
0952
0953
0954
0955
0956
0957
0958
0959
0960
0961
0962
0963
0964
FD53
FDS5
FD57
FDS9
6584
8584
F7 B3
60
9SSS
ADC
STA
S"B
RTS
SRE6P
SRE6P
7,SSETF6
I ADD IN BASE ADDRESS
; AND STORE IN POINTER
I SET FLA6 TO INDICATE AN S-RES HAS BEEN SET
j fttffffffttflfttftffftfftttfftftfUUttftflfftftttflfttttfttlflffllttflllflfft
; 'T' CO"MND
FD5A
FD5D
FD5F
FDb2
FDb5
AD 08 20
0902
80 OB 20
20 CE FD
60
TTT
LDA
ORA
STA
JSR
RTS
--IftTB
TDUCH-ToNE DIAL
; SET PULSE/TDNE BIT TD 1
1$02
I"T8
NENtX
I UPDATE TRANS" ITTER RE6 I STERS
I fftftftfffftlffffftffftlflltlflflffflttflllflflfllltftfflttflftftftflttfftfttf
j
FD66
FD69
FD6B
FD6D
FD6F
FD71
FD73
208EFD
BO 06
FO 04
F77E
DO 02
77 7£
60
'V' CO""AND
VVV
JSR
BCS
BEQ
VoNE S"B
BNE
VZERO R"8
gyyV RTS
--6ETNU"
VIERD
VlERD
7,YCDDE
IIVVV
7,VCDDE
SET VERBAL/NU"ERIC RESPONSE
; 6ET PARA"ETER, IF ANV
j IF NDNE, ASSU"E ZERO
; BRANCH IF = 0
; SET FOR VERBAL RESPONSE
I ( BRANCH AUAVS )
I SET FDR NUMRIC RESPONSE
0~65
0966
0967
0968
0969
0970 FD74
0971 FD77
0972 FD79
; fffffffffffffftftffffffffffffffffffffffffffffffflfflltlfffffffflfltltltffltlit
j
20 BE FD
80 06
FO 04
'X' CD""AND
xxx
JSR
Bes
8EII
--BETNU"
XZERD
XZERO
ENABLE/D I SABLE EXTENDED RESPONSE conES
; BET PARA"ETER, IF ANY
I ASSUM ZERO, IF NONE
I BRANCH IF = 0
5-32
Application Note
om
0974
om
om
FD7B
FD7D
FD7F
FD81
F7 7F
DO 02
77 7F
60
lONE
5MB
BNE
HERD RHB
QUI RTS
0977
0978
om
09BO
0981
0982
0983
0984
0985
R6500111 • R2424 Intelligent Modem Design
7,ICoOE
j
7,ICoDE
; SET FOR NORHAl CODES
am
SET FOR EXTENOEO CODES
j nntf**ntftftfHHtfHf*ffnfffftf**ff**ffff*nf***Uftftffffffttftftfff***f
j
FD82
FDB5
FDSB
FD8B
20
20
7F
4C
EB
40
16
00
FE
FF
FD
F8
• Z'
COKMAND
ZZZ
JSR
JSR
ZZIiAlT BBR
JMP
---
SOFTWARE RESET
RESPNS
CRLF
7, SCSR, ZZWAIT
RESET
; SEND OUT RESPONSE, I F ENABLED
j WAlT UNTIL ALL CHARS HAYE BEEN SENT OUT
; THEN RESTART
PAGE 0021
0987
0988
0989
0990
0991
09«12 FD8E
0993 FD90
0994 FD92
0995 FD94
om FD96
om F098
0998 F099
om F09B
1000 FD9D
1001 FD9E
1002
1003
1004
1005
1006 FD9F
1007 FOAl
1008 FOA3
1009 FOA5
1010 FOA7
1011 FDAS
1012 FDAA
1013 FDAO
1014 FDAF
lOIS FDBI
1016 FOB3
1017 FOBS
lOIS FDB7
1019 FOB8
1020 FOBA
1021 FDBD
1022 FOBF
1023 FIlCI
1024 FDC3
1025
; CHECK THE NEXT CHAR IN • INBUFF'. IF IT IS AN ASCII NUMBER (0-9),
FETCH IT, MASK OFF MSM, INCREMENT COMMAND STRINS POINTER (RES-X),
j
CLEAR CARRY AND RETURN.
; IF CHAR IS NOT II NUMBER, SET CARRY AND RETURN.
B5
C9
90
C9
BO
E8
29
90
38
60
4C
30
09
3A
06
OF
01
SETNUM LOA
CMP
Bce
CMP
BCS
INX
AND
BCC
NOTNUM SEC
96ETN RTS
INBUFF, I
1'0'
NOTNUM
1'9'+1
G6ETN
nOF
9SETN
; SET CHAR FROH BUFFER
; IS IT LESS THAN '0' ?
j YES==) QUIT
; NO ==} IS IT SREATER THAN '9' ?
; YES==) QUIT
j NO ==) INCREMENT INBUFF POINTER
; MASK OFF TOP-MOST 4 BITS
; AND RETURN
; I NDlCATE CHAR I S NOT AN ASCII NUHBER
; AND RETURN
j fffftftftf*****tffttfftftftU****tf**f***ftf*UUfff****tf***tfffffft*****Htf
; ROUTINE TO CONVERT FROM HEX BYTE TO 3-D161T ASCl! DEmAL
( PASE 154 '6502 SOFTWARE DESISN' ) •
AO 00
C964
9005
E964
CS
DO F7
20 CHO
849A
AO 00
C9 OA
9005
E9 Oil
CB
00 F7
20 CHO
B4 99
0930
B59B
60
HX2ASC LOY
HX2
CMP
BCC
SBC
INY
BNE
60THUN JSR
STY
lOY
HX3
CHf
BCC
SBC
INY
BNE
SOTTEN JSR
STY
ORA
STA
RTS
100
1100
SoTHUN
1100
Hl2
HCONY
NUH+2
100
110
GOTTEN
110
Hl3
HCONY
NUH+!
1$30
NUH
; FIND NUMBER OF HUNDREDS
; CONVERT TO ASCII
; AND SAVE IT
; FIND NUMBER OF TENS
; CONVERT TO Asm
; SAVE TENS DI6lT
; SAVE ONES DI6IT
5-33
Application Note
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
FDC4
FDCS
FDC6
FDCS
FDC9
FDCA
48
98
0930
AS
68
60
R6500/11 • R2424 Intelligent Modem Design
HCONV PHA
TVA
ORA
TAY
PLA
RTS
1$30
; CONVERT ABSOLUTE NU"BER TO ASCII
; tffftftnUftftftftfftUfftffft***lft*tftUUfffffffIUffffffUftfffffftUffff
FDCB
20 D7 FD
NENCXR JSR
NENCR
; UPDATE BOTH RECEIVER AND TRANsmTER REGS
FDCE
FDOO
FD03
FDD6
A9 OB
OD OE 20
8D OE 20
60
NEWCX LDA
ORA
STA
RTS
1$08
XIITE
; UPDATE "ODE"'S TRANSKITTER RESISTERS
FD07
FDD9
FDDt
FDDF
A9 OB
00 OE 10
BD OE 10
60
NENCR LDA
ORA
STA
RTS
1$08
RCVE
RCVE
; UPDATE liDDEll'S RECEIVER RESISTERS
xm
PAGE 0022
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
10S8
1059
lObO
lObi
1062
1063
1064
1065
1066
1067
10b8
1069
1070
1071
1072
1073
1074
; fftttftt.Uftftt.Uftftf.. tftfffff...tt.tff...Uttlftftftfff.Uf...... tt.. tn.
; '(CR)' COIlKAND
FDEO
FDE2
FDE4
FDE7
FDE9
FDEC
FDEE
AS 7D
DO 31
7F 80 2E
A901
2C OE 20
FO FB
FF 77 05
CR
LDA
BHE
BBR
LOA
IIAITDS BIT
BEG
CR2
BBS
FDFI
FDF3
A9FF
80 00 20
LOA
STA
CARRIA6E RETURN: SENO OUT RESPONSE KESSAGE
OR 60 INTO DATA 1I0DE IF REQUESTED AND
IF CARRIER SIGNAL ACTIVE.
STeODE
HOP
7,IIAITF6,HOP
1$01
xm
IIAITDB
7,REVFLG,CARm
I$FF
X"TO
; CHECK STATUS OF PREVIOUS COIlKANDS
; BRANCH IF NOT 'OK'
; BRANCH IF WE ARE NOT TO IIAIT FOR A CARRIER SIGNAL
; IIAlT UNTIL DIAL REG I srER IS Emv
; 'EIIPTY YET ?
; NO ==) CHECK AGAIN •••
; YES==) CHECK FOR 'REVERSE' DIAL --) BRANCH IF
WE ARE REVERSE DIAL! NG ( DON'T CLOSE OUT DlALI N6 JUST YEn
KUST BE 2400 OR NORnAL 30011200 BAUD DIAL.
--) CLOSE DIAL KODE AND 60 TO DATA KDDE.
IF WE WERE AT 300 BAUD AND DIALING 'REVERSE'
nODE THEN WE WOULD HAVE TO WAIT FOR A CARRIER
SIGNAL BEFDRE REVERSING THE KODE" TO 'ANSWER'
KODE. THEN WE WRITE AN $FF TO 'xnTO' TO CLOSE
OUT THE 0I AL SEQUENCE.
FDF6
FDF9
FDFB
FDFD
FEOO
FE03
FE06
20 DHE
AS BD
8546
4F 01 18
8F 16 03
7F 81 F7
57 12
CARTIK JSR
LDA
STA
WCARIR BBR
BBS
BBR
NoeARR RKB
STRTB3
57
DELAYS
4,PB,SOTCAR
0, SCSR, NOCARR
7,WAITC,WCARIR
S,IER
; START CNTR-B FOR SECONDS-LONB TIllE INTERVAL
; SET UP SECONDS COUNTER ( SET BY 'connA' COn"AND )
;
;
;
;
BRANCH IF CARRIER DETECTED
BRANCH (EXm IF A KEY HAS BEEN TYPED
BRANCH IF WAIT me HAS NOT EXPIRED
DISABLE mER B IRQ
5-34
:1I
Application Note
1075 FE08
1070 FEOA
1077 FEOC
1078 FEOE
1079 FEIO
lOBO FEI2
1081 FEI5
10B2
1083 FE18
1084 FElA
1085 FElC
1086 FEIF
1087 FE21
1088 FE23
1089 FE21.
10'10 FE2B
1091 FE2B
1092 FE2D
1093 FE2F
10'14 FE31
1095 FE34
10'16 FE37
1097 FE3A
1098 FE3C
1099 FE3E
1100 FE41
1101 FE44
1102 FE46
1103 FE48
1104 FE4A
1105 FE4C
1106 FE4E
A5
77
87
A9
85
20
4C
IC
80
01
03
7D
A7 Fe
AFFE
57 12
A9FF
80 0020
A9 01
85 7D
7F 7C 02
E7 01
20 EB FE
07 01
A9 00
85 B2
20 BHE
4F 01 11
20 CHE
A5 90
85 46
FF 81 C5
CF 01 FA
AS 16
57 12
A5 16
29 OF
FO E6
4A
R6500111 • R2424 Intelligent Modem Design
lOA
R"B
SHB
LDA
STA
JSR
J"P
HOP
GOTCAR R"B
LDA
STA
LDA
STA
BBR
S"B
BOTCRI JSR
R"B
60TeR2 LDA
STA
GOTCR3 JSR
INCHAR BBR
JSR
LDA
STA
CARCK2 BBS
B8S
LDA
RKB
INCHR2 LOA
AND
BEQ
CHKCHR LSR
CNTBel
7,MAlTFS
O,PB
1$03
STeODE
HHZERO
NDMAIT
5,IER
I$FF
X"TO
1$01
STeODE
7,SPKRF6,60TCRI
6,PB
RESPNS
O,PB
tOO
ESCCNT
STRTBI
4,PB,INCHR2
STRTB2
SIO
DELAYS
7, IIA1TC, NOCARR
4,PB,CARCK2
SCSR
5,IER
SCSR
I$OF
INCHAR
A
;
;
;
;
AND CLEAR CNTB FLAG
TURN OFF WA IT FLAG
DIRECT ALL OUTPUT TD HOST sysm
INDICATE 'NO CARRIER'
FE4F
FESI
FE53
FE55
BO
A9
B5
DO
06
04
7D
58
FE57
FE59
FESC
FE5F
FE61
FE64
FEb7
A5
20
FF
87
20
6F
07
17
51
7A
01
51
16
01
Bes
lDA
STA
BNE
FF
OA
FF
FD
CHKOK LDA
JSR
BSS
SII8
JSR
IIA1lDP BBR
R"B
j
FE69
FE6B
FE6D
FEbF
C5 88
DO C4
A582
FO 06
CHKOK
104
STeODE
NOWAIT
SRDR
CHROUT
7,DUPlEX,ESCCHK
O,PS
CHRDUT
6, SCSR, IIA !TOP
O,PB
il
; 6DT A CARRIER --) DISABLE mER B IRQ
; FINISH UP DIALING (IN CASE OF REVERSE DIALl
S2
GOTCR3
ESCCNT
ESCHK2
;
;
;
;
i
LEAVE SPEAKER ALONE IF FLAG IS NDT SET
CARRIER DETECTED --) TURN SPEAKER OFF
AND OUTPUT ' CONNECT' "ESSAGE, IF ENABLED
THEN DIRECT ALL OUTPUT TO "ODE"
RESET ESCAPE CODE COUNTER
;
;
;
i
;
;
;
;
;
;
;
;
;
START mER-B FOR GUARD-TlftE COUNTER
BRANCH IF CARRIER STILL DETECTED
CARRIER LOST --) WAIT FDR S10 TENTHS-OF-SECDNDS
FOR CARRIER TO RETURN -- OTHERWISE INDICATE
LOSS OF CARRIER AND RETURN TO CO""AND "ODE
BRANCH I F THE mE -OUT FLAB GOES TRUE
BRANCH IF CARRIER STILL LOST
CARRIER DETECTED AGAIN BEFORE mE-OUT -- )CLEAR SERIAL FLAGS
DISABLE IRQ
MAlT FOR RECEIVED CHAR FRO" HOST CO"PUTER
CHAR RECEIVED ?
NO ==) CHECK AGAIN
YES==) CHECK FOR PROPER RECEPTION
; BRANCH I F CHAR OK
; CHAR NOT OK --) ERROR ....
; INDICATE ERROR AND START OVER ( BRA)
; CHAR OK --) FETCH IT
; AND SEND IT TO IIODEII
; BRANCH I F CHAR I S NOT TO BE ECHOED BACK
; ECHO --) DIRECT OUTPUT TO HOST COIIPUTER
; ECHO CHAR BACK
j WAIT UNTIL CHAR IS SENT OUT
j AND REDIRECT OUTPUT BACK TO IIODEII
; liAS CHAR AN 'ESCAPE' CHAR ?
; NO ==> GET NEXT CHAR
j YES:=> IS IT THE FIRST 'ESCAPE' CHAR?
; YES:=> CHECK FOR ELAPSED TIllE SINCE PREY CHAR
5-35
-
---
,--,~-----~
-
------
11
:!
; INDICATE CARRIER DETECTED
NOli CHECK FOR POSS I BlE ESCAPE CODE SEQUENCE ••••
ESCCHK CliP
BNE
LDA
BEQ
I
I
; HANG UP THE PHONE ••••
; AND RETURN TD 'RESTRT'
PAGE 0023
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
I
---
I
Application Note
1126 FE71
1127 FEn
1128 FE75
1129 FE17
1130 FE7A
1131 FE7C
1132 FE7E
1133 FE80
1134 FE82
1135 FE8S
1136
1137 FE88
1138 FE8B
1139 FE8D
1140 FE8F
1141 FE92
1142 FE95
1143 FE97
1144 FE99
1145
1146 FE9B
1147 FE9D
1148 FE9F
1149 FEAI
1150
1151
1152
1153
1154 FEA4
1155 FEA6
I1S6 FEA9
1157
1158
1159 FEA8
1160 FEAD
1161 FEAF
1162 FEBO
1163 FEBt
1164 FEB4
1165 FE86
1166 FEB8
1167
R6500111 • R2424 Intelligent Modem Design
BIT
24 81
3088
10 03
7F 81 B7
E682
AS 82
C903
DO AF
2088FE
4F 01 13
8NI
8PL
ESCHK2 BBR
ESCHK3 INC
LOA
CNP
8NE
JSR
LSTCHK BBR
WAITe
SOTCR2
ESCHK3
7,IIAITe,GDTCR3
ESCCNT
ESCCNT
103
SDTCR3
STRTBI
4, PB, LSTCK2
20 CHE
AS 90
8546
FF 81 AC
CF 01 FA
A5 16
57 12
DO 92
JSR
LOA
STA
CARCK3 BBS
BBS
LDA
RNB
BNE
STRT82
510
DELAYS
7,IIAITC,CARCK2
4,PB,CARCK3
SCSR
5,IER
BDTCR2
AS
29
DO
7F
16
OF
8C
81 EI
LSTCK2 LOA
AND
8NE
88R
SCSR
UOF
BDTCR2
7, IIA lTC, LSTCHK
57 12
6F 16 FD
87 01
ESCAPE RN8
ESC2 88R
SNB
S,IER
6,SCSR,ESC2
0,P8
; STDP mER 8 IRQ
; WAIT UNTIL ALL CHARS ARE TRANSNITTED OUT
; THEN DIRECT OUTPUT TO HDST CDNPUTER
A900
8570
68
68
20 E8 FE
A900
8587
4C 16 F8
LDA
STA
HDIIAIT PLA
PLA
JSR
LDA
STA
JNP
100
STCDDE
j
RESPNS
100
SI
RESTRT
;
;
;
;
;
;
HAS SUARD mE ELAPSED ?
YES:=> IIAITED TOO LONG; ESCAPE NO LONBER VALID
NO == > ADD I TO ESCAPE CDUNT ( 8RANCH ALWAYS )
BRANCH IF BUARD mE HAS NDT ELAPSED
I NCRENENT ESCAPE CDDE CDUNTER
IS THIS THE THIRD SEQUENTIAL 'ESCAPE' CDDE ?
;
;
;
;
;
;
;
;
;
;
ND == > BET NEXT CHAR
YES==) RESTART GUARD-TINER
NDII WAlT FOR I BUARD-TINE INTERVAL FDR A CHARACTER
( 8RANCH IF CARRIER IS OK )
CARRIER LOST --) IIAIT FOR SIO TENTHS-OF-SECDNDS
FOR CARRIER TO RETURN -- OTHERWISE INDICATE
LOSS OF CARRIER AND. RETURN TO CON"AND HoDE
BRANCH IF THE TINE-OUT FLAS SOES TRUE
8RANCH IF CARRIER STILL LDST
CARRIER DETECTED ABAIN 8EFORE TINE-oUT--)CLEAR SERIAL FLAGS
DISABLE IRQ
LOSS DF CARRIER ABDRTS ESCAPE SEQUENCE --) BRANCH ALWAYS
;
;
;
;
;
;
IF A CHARACTER HAS BEEN ENTERED 8EFORE
THE GUARD-mE INTERYAL HAS ELAPSED, THEN THE ESCAPE
SEQUENCE IS A80RTED AND CHAR IS HANDLED IN THE
USUAL FASHION ( AT 'CHKCHR' I. IF TINER HAS
ELAPSED THEN ESCAPE SEQUENCE IS CDNPLETED WITH A
RETURN TD CDNNAND NDDE.
;
;
RESET RESULT CDDE TD 'OK'
; GET RID OF RETURN ADDRESS FRON 'JSR DOC"D'
; ( OR 'JSR AAA' AT LABLE 'ANSWER' I
; SEND OUT RESPONSE, IF ENABLED
; RESET RINS COUNTER TO ZERO
; AND START ALL OYER A6AIN
PAGE 0024
1168
1169
1170
1171
1172 FEB8
1173 FEBD
1174 FEBF
1175 FECI
1176 FEe3
; UUfuH......n ...n ..unn....uf...n.nntnu..tnHn.ntttfftfn ••n
A5
85
57
A9
A2
92
46
t2
01
9C
STRTBI LDA
STA
RNB
LDA
LDX
SI2
DELAYS
5,IER
IESCDLY
I 'NO CARRIER"
RSPERR
; 4 ==) 'ERROR'
=)
IF NUIIERIC RESPONSE SELECTED
( S4 CONTAINS CURRENT (IF> )
OUTPUT {LF>
WAIT UNTIl {LF> IS FINISHED
THEN RETURN
; WAIT TIlL TRANsmTER BUFFER IS Emv
; THEN SEND OUT CHAR
PASE 0026
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
; INTERRUPT SERYICE ROUTINE
FF57
FFS8
FFSA
FF5D
FF5F
FF60
FF62
FFo4
FFo6
FFoB
4S
AS IC
FF 78 OD
AS 00
OA
9004
E7 00
BO 12
67 00
90 OE
FFbA
me
FF6E
Cb44
DO OA
AS 45
ISR
SET!
5ETO
PHA
LDA
BBS
LOA
ASL
Bce
S"B
BCS
R"8
Bee
CARIER DEC
BHE
LDA
CHTBeL
7,IRQFLS,CARIER
PA
A
SEro
6,PA
9I5R
6,PA
91SR
; CLEAR mER B FLA6
; BRANCH IF IRQ IS FOR WAIT -FOR-CARRIER DELAY
; ECHO SERIAL IN TO SERIAL OUT
DELAYC
IlISR
DELAYT
; IS mER COUNTER : 0 ?
; NO :: > RETURN
; YES:: > RESET IT
(BRANCH ALIIAYS)
(BRANCH ALWAYS)
5-38
R6500/11 • R2424 Intelligent Modem Design
Application Note
1278
127'1
1280
1281
1282
1283
FF70
FF72
FF74
FF76
FF78
FF7'1
1285
1286
1287
1288
128'1
12'10
1291
12'12
12'13
1294
12'15
12'16
12'17
12'1B
12'1'1
1300
1301
1302
1303
FF7A
8544
C646
DO 02
F7 81
68
40
STA
DEC
BNE
S"B
QISR PLA
N"IRTN RTI
"56
=
t
.SBY
.SBY
.S8Y
.SBY
.SBY
.SIY
'OK'
'CONNECT'
'RINS'
'NO CARRIER'
'ERROR'
'CONNECT 1200/2400'
FHA
FF7C
FF83
FF87
FF9I
FF'16
4F
43
52
4E
45
43
OK"56
CAR"S6
RII6MB
HDeAR"
ERRM6
Com"
FFA7
FFA8
2A
36
CHKSU" .S8Y
PCODE .S8Y
; IS SECONDS COUNTER • 0 ?
I NO -=) RETURN
; YES=-) SET TIftE-OUT FLAG
'tttt'
'10500'
t·$FFFA
FFAF
FFFA
FFFC
FFFE
DElAYC
DELAYS
DISR
7,IIAlTC
7'1FF
00 F8
51FF
.IIOR
.IIOR
""IRTN
RESET
ISR
•END
"D"10A
.IIDR
ERRORS • 0000 (0000)
PASE 0027
SY"BOL TABLE
AAA
ABIT8
ABIT'1
ALLIN
A"SIIER
BAUD
BAUD12
BAUD24
BAUD3
BDRATH
BDHATL
BD2
8S
BUFFL6
B03
B12
B24
CARCK2
CARCK3
CARIER
CAR"S6
FCOD
0048
004'1
F9DD
FA42
0041
002F
0017
OOBF
0043
0042
F974
F9BF
0075
F95A
F966
F96E
FE3E
FE8F
FF6A
FF7e
048'1 050'1
10044 0l7'1
10045 0180
0414 10422
0485 10488
10037 0378
10126 0357
10127
10125 0351
10039 0215
10038 0223
0356 0362
0401 10404
10050 0186
10353
10359
0358 10363
1109'1 1100
11140 1141
1266 11275
1238 11288
10726
0263 0313 0316 0330
0268 030'1
0'100 1208
0553 0555
0341 0347 0477 • 0556
0342 0345 0350 0475 0554
10366
0418 0422
1140
5-39
Application Note
CARTI"
CCC
CCONE
CCZERD
CHkCHR
CHKOk
CHkSUK
CHROUT
FDF6
FC28
FC2F
m8
FE4E
FE57
FFA7
FF51
C"DTBl FA47
C"DVEC 0098
CNTACl 0018
CNTAH
CNTAl
CNTBCl
CNTBHC
CNTBHl
CO""A
COHm
Cft
CRLF
CR2
eTlCDD
DOD
DEFPRO
DElAYC
DELAYS
DElAVT
DELETE
DIGERR
DISIT
DI62
DIlFlS
DLYHI8
Dl YTlK
Dom
DUPLEX
ECHOFS
0019
OOIA
OOIC
0010
OOIE
FBIE
FF96
FDEO
FF40
FDEE
F9AC
FC44
0040
0044
0046
0045
F9C3
F854
mc
F84E
0076
0010
E09C
F9F2
007A
0079
0870
0509
10746
0744
11106
1107
0839
R6500/11 • R2424 Intelligent Modem Design
1057 11068
10743
0745 10750
11112
.1294
0394 0403 0409 0716 1113 1116 1215 1246 1250 1253
11257
0448
10089
10025
0346
10026
1257
10497
0436 0461 0463
0205 0217 0224 0235 0260 0265 0279 0296 0301
0476
0213
10027 0206 0227 0229 0247 0274 0276 0348 0478
10030 0198 0583 0588 1075 1194 1265
10031
10032 0200 0585 1195
0505 10579 0774
1230 .1292
0425 0512 0620 0639 0921 11051
0710 om 0835 0983 1202 1216 11249
0735 11057
0393 .0395
0509 10760
10036 0339 0473 0558
10040 1196 1275 1278
10042 1070 1098 1139 1173 1279
10041 1197 1277
.0406
0601 tom 0645
0506 0507 10601
0612 10614
t0051 0184 0546 0601 0627 0628 0777 0899 0904
10m 0586 l!B3 1191
10120 0582 0584 1192 1193
0434 10436
10055 0550 0801 0803 1114
10054 0196 0393 0549 0789 0791
PA6E 0028
SYMBOL TABLE
EEE
EONE
EQUAL
EQ2
EG3
E94
ERRIIS6
ESCAPE
ESCCHK
ESCCNT
ESCDLY
FC72
FC79
F876
FBA2
FBAD
FBBC
FF91
FEA4
FE69
0082
0001
0509
10789
0508
0654
0666
0651
*0786
10645
0659 10m
10670
0671 10677
1232 11291
11154
111411122
10063 1093 1124 1130 1131
10122 1m
5-40
Ii
R6500/11 • R2424 Intelligent Modem Design
Application Note
ESCHK2
ESCHK3
Escm
ESC2
EVEN7
EVEN8
£ZERO
FFF
FNDC"D
FONE
FOUND
FOUNDA
FOUNDS
FOUNDT
FIERO
SETCHR
6ETN~
FEn
FE7A
mc
FEA6
F929
F91D
FC7D
FC80
F9F5
Fe87
FAOD
F8AD
F8EF
F8FI
FC8B
F9A4
FD8E
SOCR
SOTCAR
SOTCHR
SOTCRI
BOTCR2
SOTCR3
BOTHUN
BOTTEN
602RES
moo
HCONV
HHH
HHSET
HHZERO
HOP
HX2
HX2ASC
HX3
HIAND2
IER
FA08
FEI8
F9CD
FE28
FE2D
FE31
FDAA
FDBA
FBA7
F962
FDC4
FC8E
FCB7
FCA7
FEIS
FDAI
FD9F
FDBI
FC9S
0012
IFR
0011
III
IIONE
IlZERO
INBUFF
INCHAR
INCHR2
INITSN
IRQFLG
FC8B
FCCS
FCC9
004C
FE34
FE48
FABE
0078
1125 11129
1128 11130
10123 1176 1177
11155 1155
0317 10327
0310 10321
0787 0788 10791
0509 10798
0432 10444
10801
0449 10457
0244 10259 0259
0288· 10m
0290 10295 0295
0799 0800 10803
10392
0650 0653 0658
0929 0933 0958
0447 1045S
1071 11083
om 0405 10412
1088 11090
11092 1127 1144
11094 1123 1129
1008 11012
1016 11020
10250
0352 10357
1012 1020 1102&
0509 10810
0820 10827
0811 0812 10821
1052 1053 11081
11007 lOll
0713 tI006
11015 1019
0726 10813 0868
10019 0201 0349
1174 1182 1190
10018 0192 0207
0295 0300 0470
0510 10835
10839
0837 0838 10841
10048 0412 0445
11095 1105
1095 11103
0140 1052&
10053 0202 0380
I
0743 078& 0798 0810 0836 0851 0886
0970 10992
1148
1133
1:1
1080
om
0528 1074 1083 1102 1143 1154
1199
0228 0234 0248 0259 0264 0275 0278
0527 0587
0569 0605 09'/2
0488 1266
5-41
Application Note
R6500111 • R2424 Intelligent Modem Design
PA6E 0029
SVNBDl TABLE
JSR
LABELl
LoOP2
LSTCHK
LSTCK2
LI
LIO
Ll2
L2
L3
L4
L4A
L5
L6
L7
L8
L9
NCR
""N
""ONE
""Tilo
""ZERO
FF:57
F93D
F9FD
FE85
FE98
F857
F8D4
F8FB
F85F
F87D
F889
F8AI
F8A4
F887
F8CI
F8C4
F8CD
0014
FCCF
FCoC
FCDE
FCE3
FF7A
"58
"S60UT FF33
"ULTIO F8EC
NEIICR FDD7
NENCI FDCE
NEIICXR FDC8
N"IRTN FF19
HOCAR" FF81
NOCARR FE06
NDDLAY F839
NOIRII F8:50
HOPAR F92F
NDPAR1 F939
NOPARB F933
HOSLFT F8C6
NoTNUN FD9D
NollAIT FEAF
NUN
0098
NUNCND
NUNERC
MlTCND
0007
ODDS
DKNS6
ONESEC
ODD
PA
0021
FF04
F9E9
F917
F923
FF7A
FB2C
FCE6
0000
PB
0001
11264 1301
0320 0323 0326 0329 0334 10338
10448 04:52
11135 1149
1135 11146
10207 0208
10278 0278 0284
10300 0300
10210 0210
10228 0228
10234 0234 0240
10248 0248
10249 0249
10264 0264
10269 0269
10270 0270
10215 0275
10020 0138 0194 0195 0221 0222 0472
0510 10850
10856
0855 10851
0852 0853 10859
0839 0841 1230 1232 1234 1236 1238
0842 1231 1233 1235 1237 1239 11242
0667 0672 0673 10699
0191 1034 11041
0733 0753 0767 0819 0951 11036
0377 0696 0827 0916 11034
11283 1299
1234 11290
1072 11014 1099
0:581 10593
0196 10203
om 10330
0331 10335
10332
10682
0994 11000
1081 1110 11161
100BB 0641 0648 0649 0652 0655 0656
0662 0663 0664 0665 066B 0669 0610
0115 0932 0936 0937 1013 1021 1023
10129 0451 0455
11214
10432 0435
10318
0312 10324
1240 11287
10586 0592
0510 10868
10013 0208 0209 0210 0230 0230 0249
0270 0280 0297 0302 1267 1270 1272
10014 0142 0143 0144 0145 0146 0354
0859 1071 1077 1089 1091 1095 1100
1240 1242 11285
1248
06:57 0660 0661
0615 0616 0611
0261 0266 0269
0360 0364 0857
1115 IIIB 1135
5-42
R6500/11 • R2424 Intelligent Modem Design
Application Note
PCODE
PPP
QCCC
GDISlT
QECHO
FFAB
FCEE
FC3D
FB53
FC7F
1141
OB41
0510
0748
10616
0790
1156
11295
10m
0749 10152
10792
PASE 0030
SYMBOL TABLE
QEQ
QFFF
Q6ETN
QHHH
GIl
QISR
Q~""
QQ
QQONE
ggG
QQIERO
9RRR
9RSP
QSSS
QUESTN
QUES3
QVVV
GXXX
RCV
RCVA
RCVB
RCVC
Rev»
RCVE
RCVF
RCV2
RCVS
RCV9
REPEAT
REPFLG
RERROR
RESET
RESPNS
RESTRT
REVFLG
RINS
RIMaNS
RNB"SG
ROTATE
RRR
RSLTF6
RSPCAR
RSPCI2
RSPERR
FBEB
FC8D
FD9E
FCBA
FCCS
FF7B
FCES
FD07
FDOI
FCFA
FD05
FD32
FFOC
FD57
FSF4
FCOO
FD73
FDBI
1000
100A
100B
looe
100D
100E
IOOF
1002
1008
1009
F9E7
om
FD33
FBOO
FEE8
FBI6
0077
F8AA
FAle
FFB3
F943
FDOS
007B
FF2D
FF1D
FF21
068B
OB02
om
IOB28
OB40
1271
0858
OB90
10889
0510
08B7
0902
1203
0930
0508
10715
0962
0974
10092
10098
10099
10100
10101
10102
10103
10095
10096
10097
0386
10049
0899
10m
0481
10176
10052
0207
0252
1236
10341
0510
10056
1222
11230
1228
10m
10804
0999 11001
10842
1273 1276 1280 I12B2
IOB60
10892
IOBBb
08B8 10891
10917
11217
0931 10941
10710
0718
10964
10976
0094
0367 0370 0534 0683 0684
om
0692
0375 0537
0188 0190 0532 0817 0819 OB24 0826 0910 0911
0539 1042 1043
0422
0178
10m
0985
0982
0250
om
10252
10469
11289
0344
10899
0547
11238
10427
0293 0386
1300
1090 1163 11202
0291 0486 1166
0905 1057
0889 0891
1203
11232
5-43
Application Note
RSPNC
RSPOK
RSPRN6
RSP2
SCCR
SCSR
FF25
FF31
FF29
FFOI
0015
0016
SE"ERR
smc
5EII12
SETPTR
SETO
SET!
SlFTST
SLOOP
SPKRFS
FB6F
FB58
F862
mc
FF66
FF62
FBDB
FBlI
007C
1226
1220
1224
1206
10021
10022
1155
0627
0508
10630
10387
1269
11270
0681
10564
10057
11234
11240
11236
1207
0177
0381
1254
10637
10627
0631
0410
11272
R6500111 • R2424 Intelligent Modem Design
1210 11213
0338 0474
0388 om 1072 1101 1103 1117 1142 1146
1257
10690
0567
0552 OS50 0856 IOS8
PAGE 0031
5YII80l TA8lE
5RUR
SRESP
55ETF6
SSS
5S2
ST8l
STCODE
0017
00S4
0083
FU3A
FU50
FAAU
0070
STUR
STRTBI
STRTB2
STRTB3
STRTl"
SO
SI
S10
511
512
513
514
515
516
S17
52
53
54
55
56
57
58
59
T8lT8
TBlT9
TEIIP
0017
FEBB
FEC9
FED3
FEUB
0086
0087
0090
0091
0092
0093
0094
0095
0096
0097
00e8
0089
ooeA
00B8
OOBC
ooeD
ooeE
008F
004A
0048
0090
10024
10065
10064
0511
0934
10517
10058
1087
10023
1094
1096
1068
1178
10069
10070
10079
10080
t0081
10082
10083
t0084
10085
10086
10071
10072
10073
10074
10075
10076
10077
10078
10046
10047
10090
0392
0560
0543
10927
10937
0564
0lS7
1109
0024
1134
1137
11190
IIB6
0484
0482
1097
1112
0562 0565 0679 0712 0928 om 0940
0645 0941
0424 0454 0480 0619 0638 0920 1051 1079
1160 1204 1212 1219
1258
11172
tI182
11194
0559 0561 0927
0483 0544 1165
1138
1172
0680
1122
0395 0413 0446 0568 1249
1252
0402 0404
0772
1069
0580 0770 om 0716
0181 0299 0314
0182 0304 0311
0366 0369 0373 0579 0593 0699 0702
5-44
R6500/11 • R2424 Intelligent Modem Design
Application Note
TENTHD
TESTB
TTl
VCODE
VECTBL
VERIAL
VONE
VVV
VIERO
IIAITB
IIIIITC
IIIIITDB
IIIIITDl
IIIIITDP
IIIIITFB
IIIIm"
IIIIITlF
III\lTRE
IICARIR
leODE
I"T
I"TII
X"TB
me
I"TD
6760
0047
FD5A
007E
FA69
FFOD
FD6D
FD66
FD71
FB2E
0081
F0E9
FC59
FEU
0080
F99E
FF4D
FI41
FDFD
007F
2000
20011
200B
200e
200D
10121
10043
0511
10059
0460
1213
10961
0511
0959
10587
10062
11055
10768
11117
10061
10388
1251
10603
11071
10060
10105
10112
10113
10114
10115
0913
1184
0183
10948
0551
0462
11219
10958
0960
0587
1073
1056
0769
1117
0185
0390
11254
0604
1073
0545
0107
0371
0530
0376
0529
0915
1185
0232 0238 0241 0271 0282 0285
0961 0963 1213 1251
10505
10963
0590
1099 1126 1129 1140 1149 1198 1281
0634 0734 0778 0869 1053 1016
0398 0399 0407 0417 0420
1254
0973 0975 1207
0374 0535 0686 0687 01194 0695
0876 0878 0948 0950
0538
0728 0729 0763 0766 0813 0816 0821 0823
PII&E 0032
SYMOL TA8LE
1m
200E
200F
2000
2002
2008
1m 2009
lONE FD78
xxx FD74
IZERO FD7F
ZZIII\lT FD88
zzz FD82
.HARB tttt
I"TF
I"TO
I"T2
X"TB
END OF
10116
10117
10108
10109
10110
10111
10973
0511
0971
10984
0511
0540 0603 0630 1037 1038 1055
0615 0633 1060 1085
0768
0731 0732 0747 0751 0752 0761 0762 0907 0908
10970
0972 10975
0984
10982
IISS~BL Y
5-45
Application Note
'1'
Interfacing Rockwell Signal
Processor-Based Modems
To An Apple lie Computer
Rockwell
by Garlos A. Laiz, Product Applications Engineer
Semiconductor Products Division, Newport Beach, California
INTRODUCTION
USART. 110 SELECT is active during 00 clock when the micraprocessor references page $Cn, where n is a peripheral
slot number (1-7) in the Apple.
This application note describes the electrical design of a module
that interfaces an Apple lIe* computer to a Rockwell Signal
Processor (SP)-based modem. The design incorporates an
USART (8251A) for asynchronous/synchronous serial data
transfer and control, and two digital-ta-analog converters (DACs)
for quadrature eye pattern generation. Memory mapped
inpuVoutput (110) allows easy access to the modem interface
memory for parallel control and data transfer. The interface
module connects directly to the following modems with minor
software differences required to switch between them:
• R1212M or R1212DC
• R2424M or R2424DC
• R48DP
The data lines are buffered by U2 and routed to multiple destinations (U1, U8, U9 and the interfacing modem). U2 is enabled
by I/O SELECT and the data direction is controlled by READ.
Address lines A4-A6 are decoded (U3) into eight chip select
signals ($CnOR-$Cn3R and $Cn4X-$Cn7X). Addresses
$CnOR-$Cn3R correspond to the modem chip select inputs
(CSO-CS3). Writing to address $Cn4X triggers U4 to generate
a low level pulse (4 ,.s min.) causing the modem to initiate a
Power On Reset (POR) cycle. Addresses $Cn5X and $Cn6X
are used to write eye pattern data into the X-DAC and Y-DAC,
respectively.
• R96DP
• R96FT
Two assembly listings of sample software subroutines for
R12121R2424 automatic dialing and R48DP/R96DP eye pattern
generation are also included.
The USART's input line Control/Data (C/O) is controlled by the
address line A7. Address $Cn7X (A7 = 0) is used to write to the
transmitter register or to read the receiver register in the USART.
Address $CnFX (A7 1) is used to write to the USART Control
register or to read its status register. The USART is supplied
with 01 clock directly from the Apple bus.
=
HARDWARE DESIGN
The interface module schematic (Figure 1) shows the routing
of signals between an Apple lie peripheral slot, the USART, and
the modem. The modem can physically be located outside the
Apple lie and connected by a short 64-conductor ribbon cable
to a 64-pin DIN connector (with the same pin assignments)
installed on the interface module.
The I/O addresses and their functions are summarized in
Table 1.
Table 1. Interface Module Memory Map
The major devices on the interface module are the 8251A
Universal Synchronous/Asynchronous ReceiverlTransmitter
(USART) and two NE5018 DACs. The USART (U1) allows the
microprocessor to transfer data and control to the modem via
the serial interface. This USART supports both asynchronous
and synchronous data transfer modes. The two DACs, U8 and
U9, generate the analog voltages to drive the eye pattern X-OUT
and V-OUT signals, respectively.
Address lines AO-A3 are directly connected to the modem
register select inputs RSO-RS3. The Apple's partially decoded
I/O SELECT (pin 1 in the Apple peripheral connector) is used
to gate RiW to produce two separate READ and WRITE signals
with the proper timing as required by the modem and the
Address
Device Addreessd/Function Performed
$CnOR
$Cn1R
$Cn2R
$Cn3R
$Cn4X
$Cn5X
$Cn6X
$Cn7X
$CnFX
Chip Select 0 (CSO)
Chip Select 1 (CS1)
Chip Select 2 (CS2)
Chip Select 3 (CS3)
POR (Power-On-Reset)
X-CAC Latch Enable (XLE)
Y-CAC Latch Enable (YLE)
USART Chip Select (C/O=A7=0)
USART Chip Select (C/O=A7-1)
Notes:
n = Apple lie peripheral slot number (1-7)
R = Modem register number (O-F)
X = Irrelevant
•Apple and Apple /Ie are regIstered trademarks of Apple Computer, Inc
Document No. 29220N73
Application Note
5-46
Order No. 673
February 1985
+5V
+5V
7A
7C R50
8A AS1
6C R52
R53
8Bit:I
c:ac>'
ac>
"I
~::'~= :
~
~
~
B2
B3
"'m
~
~
~
B6
B7
88
E.W
~I
A6 7
A7 I
A8 9
(00-07)
11<
II<
9C
5V
W
0.1 +
-..,
I
READ
jijS)o6
i
~
I.
19 G
1 DlR
GND VCC
!.-
I~
5C
4A
4C
3A
2A
2C
1A
1C
12C
11A
10C
A2
A3 4
'''''''LJ
2
IIIII [
II
b
1Df
~I
LS32
LS04
~.
l
~ (U") bf
gN
10 •
GND
1,...
U7
6
1
Z
~
R1212
R2424
R41DP
R96DP
R96FT
03
04
OS
DB
07
READ
WRITE
CSO
"i!n
111~7
j:l1~1~1 ..1:!!1 ..
Y
'--l!!rI WR
13:i FiD
1~lel~l= =~
LOO
.Y(D7)
7 06
6 00
r-:"I....".,::r!r::t~9,
B251A
USART
(U1)
N~'5 TxE
TxRDY
GND
q-
Ne 1
He
14 RxRDY
NC 16 SYNC/BRK
21 RESET
.,.
-.2V
11
~9
ts
lflC/D
1I4W .,..
~
Kn.5"
ALL CAPACITOR VALUES IN ,F
UNLESS OTHERWISE SPECIFIED.
• X.oUT
1I4W
~
.,..
Kn.5%
....y-OUT
TO SCOPE
iOl CLK
rr
4
GND
2 03
50.
6 0s
en
Vcc 21
2 ~
'02
74L$138 3
(U3)
A
2 B
3. C
i
b,e.#
.)!, ....
G1 "cc
fi1'\.36
5"
::J
MODEM
BOARD
02
I
213141516171119,
5 ::
~8.L
:"2a0"
DO
01
IIS4
~'
+5V
-12V
WRITE
I
§
12A1
9A
5'
r
-12V
+12V
15AI
+12V
1eel
"
+5V
0.1
l'
m
I»
:
Do
3:
o
Do
CD
3
o
:a-
-a
-a
CD
CD
;::J
in
Figure 1. Apple lie to Rockwell SP Modem Interface Schematic
rat
CD
Application Note
Rockwell SP-Based Modem to Apple lie Interface
SOFTWARE CONSIDERATIONS
R1212 and R2424 data sheets. The subroutine, as shown, starts
at address $6000 but can be easily relocated. As written, it
assumes that the interface module is installed in Apple lie
peripheral slot 4. The number to be dialed should be stored at
$6100 and terminated with an $FF character.
Application software can easily control the modem, the USART
and the two DACs via the addresses decoded on the interface
module (Table 1). The location of bits and registers as well as
diagnostic accass codes vary between modems. Refer to the
appropriate data sheet for specific bit and register locations and
access codes.
The Eye Pattern Generator subroutine for the R48DP/R96DP
(Figure 3) generates a continuous eye pattern in loop 3 (local
analog loopback) by reading a signal point once per baud. The
subroutine starts at $0300 and can also be easily relocated.
Execution is halted and control returned to the calling routine
when a key is pressed. The comments In the listing describe
the detail operation.
Two example software subroutines are included in this application note for interfacing to an SP-based modem. These routines
are written In 6502 esssmbly language.
The Automatic Dialer subroutine for the R12121R2424 (Figure 2)
implements the same function described and flowcharted in the
If.{ ["1
1,1.)
r\(IU~'J'
HI) He t.;t1
1>"08, I'll) II, C'l
6l'l>i!
VI II:!
1>')'.!1' Of) 1t) L:4
(.)(~lUAli n. 1.'1
t,(,1 I .., ~
l"1 oB
~)\ l j ~"
~·Cl) 11.: [ 'j
{tIll H- (\(> 10 C4
o'.IJle·· ./'../ B'I
t,Ol (l
l-- () I-'J
NJJf' t),' (II)
t'1( 1'.:.11
(\IJ U:' 1.4
( .'~/IIIJ
/)I,I{)",
I nil .fL 1:8
S IIi 'j;Cq) IJ
I llrl .l·C/I j b'
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M
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( ,~'l:"'l~
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bt.>."f. - HJ
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1160
11.6[3
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11.11'1 OLU
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;bU PH;! I i-f(UI'I HUf'H.I( AI
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R2424 Automatic Dialer Routine
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Application Note
Rockwell SP-Based Modem to Apple lie Interface
1000
1008
1016
1024
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Application Note
2400/1200/300 bps International Modem Design
Table 2. International Modem I/O Addresses
Address (Hex)
200
201
202
203
204
205
206
207
208
209
20A
208
20C
20D
20E
20F
Register Description
R2424 Receiver Reserved
R2424 Receiver Reserved
R2424 Receiver DiagnostIc 1
R2424 ReceIver DIagnostic 2
R2424 Receiver Diagnostic 3
R2424 ReceIver Diagnostic 4
R2424 ReceIver Reserved
R2424 Receiver Reserved
R2424 Receiver Status 1
R2424 Receiver Status 2
R2424 Receiver Conflgu ration 1
R2424 Receiver Configuration 2
R2424 Receiver Configuration 3
R2424 Receiver Configuration 4
R2424 Receiver Handshake
R2424 Receiver DiagnostIc Control
210
211
212
213
214
215
216
217
218
219
21A
218
21C
21D
21E
21F
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
220
221
222
223
22422F
230
231
232
233
23423F
Z8530 Channel 8 Command
Z8530 Channel 8 Data
Z8530 Channel A Command
Z8530 Channel A Data
Not Used
Not Used
82C55 Port A
82C55 Port 8
82C55 Port C
82C55 Control RegIster
Not Used
Not Used
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
SCC has two I/O channels (A and B). Channel A is used for all
full duplex modes; channel B is used in a V.23 half duplex mode
where a secondary channel is used.
Outgoing data (TXO) written from the host computer is serialized and formatted by the Z8530 SCC (U6). It is then output on
the TXOA or TXOB pin in serial form.
Incoming data (RXO) from the modem is input to the SCC on
the RXOA or RXOB pin and is read via the data bus from the
SCC data register. The data is then routed to the PC display
(application note software), or it may be routed to a different
destination (user-provided software).
The SCC AlB input selects channel A or B. The SCC C/O input
determines if control or data information is being accessed. The
WR and RO inputs determine if data is being written to or read
from the SCC, respectively. The CE input is low at address
220-223 to enable the SCC.
Dial Digit Register
Reserved
Diagnostic 1
Diagnostic 2
Diagnostic 3
Diagnostic 4
Reserved
Reserved
Status 1
Configuration 1
Configuration 2
Configuration 3
Configuration 4
Configuration 5
Handshake
Diagnostic Control
R2424 Modem
The R2424 is mapped into the PC I/O addresses 200H-21 FH.
The R2424 receiver is enabled by CSO (200H-20FH) and the
transmitter is enabled by CS1 (21 OH-21 FH). This enables access
to the 32 locations required by the receiver and transmitter
interface memories. Host computer address lines AO-A3 are
routed to R2424 register select inputs RO-R3, respectively, to
access the required interface memory location.
For more information on the R2424 refer to the R2424 Oata
Sheet (Order No. M011) and Section 4 (R1212/R2424 Modem
Functional Characteristics) in the Modem Interface Guide (Order
No. 685), both available from Rockwell International.
Am7910 Modem
Operation of the Am7g1 0 modem is controlled by five configuration inputs (MCO-MC4). Table 3 lists the available modes and
identifies the modes used in this application note. The Am7910
configuration signals are controlled by PPI (U7) ports PAO-PA4
since there is no direct host computer bus interface.
The V.24 control signals are routed from the Z8530 SCC (U6).
The primary channel (used for all full duplex modes) is routed
to the SCC channel A and the Am791 0 secondary channel (used
for the 1200 half duplex mode) is routed to the SCC channel B.
All data between the host computer and the modem is transferred over the bidirectional data bus (00-07). The data bus
carries data to be transmitted to the modem (TXO) and to be
received from the modem (RXO) via the Z8530 SCC, as well as
control/status signals to/from the R2424 modem, the Z8530 SCC
and the 82C55 PPI. U13b, U13c and U13d enable data bus buffer U3 when an I/O read or I/O write occurs in a valid address
range. The direction of the data bus buffer is controlled by the
host computer I/O read line (lOR) gated with the valid I/O
address signal appearing at U13d/11.
Z8530
The clock for the Am791 0 is provided by the SCC output TRxCA.
V_24 Interface
TIL V.24 signals are routed to/from the R2424/Am7910 modems
as selected by U9 and U10. The RLSO, CTS and RXD outputs
from either the R2424 or the Am791 0 are switched through U9
to Z8530 SCC (U6) channel A inputs OCOA, CTSA and RXOA,
respectively. PPI PA5 output high selects Am791 0 signals; PPI
PA5 output low selects R2424 signals.
The TXO input to both the R2424 and the Am7910 is routed
directly from the SCC TXOA output. The RTS input to the R2424
and/or the Am7910 is routed from the SCC RTSA output through
U10. The RTS input to the R2424 is enabled through U10 by
PPI PA6 output low. The RTS input to the Am7910 is enabled
through U10 by PPI PA7 output low.
see
The Z8530 SCC (U6) transfers the data from the modems to the
data bus and converts the data from parallel to serial and serial
to parallel between the host computer and the modem devices
and provides asynchronous formatting and unformatting. The
5-53
Application Note
2400/1200/300 bps International Modem Design
'BM PC
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International Modem Schematic
5-54
-
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RESET
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PA8 38
PA7 37
PSO 18
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Application Note
2400/1200/300 bps International Modem Design
.""" ""
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Figure 3. International Modem Schematic(Continued)
5-55
ANALOG
SIGNALS
Application Note
240011200/300 bps International Modem Design
Table 3. Am7910 Mode Selection
MC4
MC3
MC2
MCI
MCO
Mode
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
Bell 103 Originate 300 bps Full Duplex
Bell 103 Answer 300 bps Full Duplex
Bell 202 1200 bps Half Duplex
Bell 202 with Equalizer 1200 bps Full Duplex
V.21 Originate 300 bps Full Duplex'
V.21 Answer 300 bps Full Duplex'
V.23 Mode 2 1200 bps Half Duplex'
V.23 Mode 2 with Equalizer 1200 bps Half Duplex
V.23 Mode 1 600 bps Half Duplex
Bell 103 Originate Loopback
Bell 103 Answer Loopback
Bell 202 Main Loopback
Bell 202 with Equalizer Loopback
V.21 Originate Loopback
V.21 Answer Loopback
V.23 Mode 2 Main Loopback
V.23 Mode 2 with Equalizer Loopback
V.23 Mode 1 Main Loopback
V.23 Back Loopback
0
a
0
0
a
0
0
0
I
1
1
1
0
0
0
0
0
1
1
1
a
a
a
a
I
1
a
1
1
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
a
a
1
0
0
1
0
1
a
1
a
1
1
1
0
1
• Modes implemented in application note software.
82C55 PPI
a set of control signals (OH and CCT) is generated to keep the
DAA connected to the phone line. Meanwhile, the R2424 is
disconnected and the Am7910 is configured for the desired
mode. When the remote modem answers the Am7910 has control of the line and is set up to be in originate mode. The connection places the modem in data mode in either V.21 or V.23.
The 82C55 PPI handles control signals between the host computer and the Am7g10 modem and various TTL switches, data
selectors/multiplexers and buffers. The functions of the bits in
the PPI registers are listed in Table 4.
Port A signals control the Am7910 configuration and the U10
switch. Port B output Signals control U11 to select the routing
of TXA and RXA between the RDAA and either the R2424 or
the Am791 O. Port B output signals also control the resetting of
the modems and the PPI. Port C inputs monitor RTS and CTS
from the R2424 and OH and CCT signals from the R2424. The
Port C outputs issue OH and CCT to the RDAA via U10.
Answer Mode
In the answer mode, the modem must be capable of answering
an incoming call from a modem of unknown configuration. The
R2424 always answers the call, regardless of the final configuration. Because the default setup condition exists, the R2424 sends
out the CCITI answertone and waits for the response from the
remote modem. The software determines the configuration of
the remote modem within one second of Data Set Ready becoming active in the R2424. It does this by first examining the SPEED
bits.
RDAA Interface
Routing selection of TXA to the RDAA and RXA from the RDAA
is controlled by U 11. TXA is routed from the R2424 (TXA) or the
Am7910 (TC) and RXA is routed to the R2424 (RXA) or the
Am7910 (RC). OH and RCCT originate from the R2424 (OH and
RCCT) or from the 82C55 PPI (OH.79 on PC6 and RCCT.79 on
PC7) as selected by U10. RD is routed from the RDAA to the
R2424 (RD) and Am7910 (RING) in parallel. CCT is routed to
the R2424 (CCT) and to the PPI (CCT on PC2).
If the SPEED bits are set to 11 (binary), then the modem is connected in V.22 bis mode at 2400 bps. If the SPEED bits are set
to 10, then the modem is connected in V.22 mode at 1200 bps.
If the SPEED bits are set to 00 then the calling modem is a V.21
or V.23 type. The RLSD bit of the R2424 is then examined. If
it is set to 1, then the calling modem is a V.23 modem, otherwise it is a V.21 modem. At this time the Am7910 is already in
data mode, although not connected to the line. (The ringing
signal supplied by the DAA is shared by the R2424 and the
Am7910, so both go off hook in answer mode.) When the software determines that a V.21 or V.23 connection is in progress,
it holds the line by generating a set of control signals for the
DAA. The R2424 is switched oul and the Am7910 is switched
in to the line, already in data mode. The remote modem received
2100 Hz answertone from the R2424. Now the Am7910
completes the handshake and the modems enter the data
mode.
MODEM OPERATION
Originate Mode
Modem operation is divided into two parts: originate and answer.
In the originate mode, the R2424 always does the dialing,
regardless of the final configuration. If a V.22 or V.22 bis connection is desired, the default hardware setup (initialized by
application software) permits the R2424 to stay on line after dialing and connect with the remote modem. If a V.21 or V.23 connection is desired, then the R2424 dials the call. After dialing,
5-56
Application Note
240011200/300 bps International Modem Design
OPERATING PROCEDURE
Type 70 LOAD and press RETURN.
The procedure to operate the modem using the application note
software is described in this section. It is assumed that the user
has entered, edited and stored the FORTH screens listed in
Figure 15. It also assumes that the FORTH command level has
been inVOked.
When loading is complete, the software initializes and configures
all devices for the default settings. A menu screen is then
displayed on the terminal. This menu is function key driven and
prompts the user for a choice of five keys to press for different
options. Four originate modes are presented and one universal
auto anSwer mode. The four originate modes allow the modem
to connect at 300 bps in V.21 mode, 1200 bps in V.22, 2400 bps
in V.22 bis and 1200 bps in V.23. The universal auto answer mode
connects at the speed and configuration of the calling modem
(initially unknown).
Table 4. 82C55 Port Functions
Port Bit
Function
7910 R2424
Port A-8 Outputs (0-7)
PAO
PAl
PA2
PA3
PA4
PAS
0
1
2
3
4
5
PA6
6
PA7
7
7910 Configuration Pin MCO
7910 Configuration Pin MCl
7910 Configuration Pin MC2
7910 Configuration Pin MC3
7910 Configuration Pin MC4
RXD, C'i'S, l)Cl) Modem Select
1 = 7910
0-2424
D'i'R, m'$, RCCT, OH Disable to R2424
1 = Disable
0= Enable
MR, RTS, RCCJ:,OH Dlsab)e to 7910
1 = Disable c
0- Enable
The displayed menu is:
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INTERNATIONAL MODEM
F1
F2
F3
F4
F5
When the menu screen is displayed, the modem is in idle mode
and the program is waiting for a function to be requested. To
initiate a mode, press the corresponding function key.
Originate Mode
Port B-8 Outputs (0-7)
PBO
0
PBl
1
PB2
2
PB3
3
PB4
4
PB5
5
PB6
PB7
6
7
R2424 TXA to DAA
1
Enable
o = Disable
R2424 RXA to DAA
1 = Enable
0= Disable
7910 TC to DAA
1 - Enable
0= Disable
7910 RC to DAA
1 - Enable
Disable
o
Reset Z8530 (Pulse)
1 = Normal
0- Reset
Reset Modems (Pulse)
1 = Normal
o - Reset
Not Used
Not Used
=
I! an originate key is pressed, the user is prompted to enter the
phone number to call. Upon number entry, the call is placed
(always by the R2424). If a V.22 or V.22 bis configuration was
selected then the R2424 stays connected to the line after plac·
ing the call. Otherwise, the Am7910 is switched in to complete
the handshake with the remote modem. Once the modem is in
data mode the program enters the dumb terminal routine.
After an originate mode is selected, the system will display one
of the following messages depending on the selected mode:
=
X
V.21
V.22
V.22
V.23
X
0
1
2
3
4
5
PC6
6
PC7
7
Read R2424 DSR
Read R2424 Ai
Read Status of ~ from DAA
Read Status of OH from DAA
Not Used
Set RCCT on DAA for 7910
1 = Set
0= Off
Set OH on DAA for 7910
1 = Off·Hook
0= On·Hook
Not Used
300 BPS MODE
1200 BPS MODE
2400 BPS MODE
1200 BPS MODE*
followed by
X
X
ENTER PHONE NUMBER
Enter the telephone number to call and press ENTER.
Port C-4 Inputs (0-3), 4 Outputs (4-7)
PCO
PCl
PC2
PC3
PC4
PC5
V.21 ORIGINATE
V.22 ORIGINATE 1200
V.22 ORIGINATE 2400
V.23 ORIGINATE
UNIVERSAL AUTO ANSWER
X
X
X
Upon carrier detection and line connection the system will
display:
CARRIER DETECTED ... ON LINE
TERMINAL ON LINE
X
To terminate the mode anytime during the operation, press CTRL
BREAK. After connection is established, pressing' (single quote)
will also terminate the mode. After terminating the mode, press
RETURN to return to FORTH command entry level. Now type
MENU and press RETURN to disconnect the modem from the
line and to display the mode menu.
X
*V23 call origination results in a hal! duplex data mode connec·
tion. This application note software configures the originate
modem for transmitting by asserting RTS. In order to receive
data, RTS must be made inactive.
5·57
Application Note
2400/1200/300 bps International Modem Design
Auto Answer Mode
Dumb Terminal
In the universal auto answer mode, the program waits for the
phone to ring. It then answers the call with the R2424 which
sends out a 2100 Hz answertone. The R2424 decides the speed
and configuration of the calling modem from the response from
the calling modem. Depending on the response, the line is left
connected to the R2424 or switched to the Am791 O. When the
handshake is complete, the program enters the dumb terminal
routine.
The dumb terminal routine is used once the modem has completed a connection. Data entered on the PC keyboard is sent
to the modem to be transmitted to the remote modem. Incoming data is displayed on the terminal. In order to capture all
received data at 2400 bps, it is necessary to interrupt the PC
so that the data can be stored in a buffer. (This is because the
scrolling actions of the screen take too much time and data would
be lost if a polling method were used.) The dumb terminal routine
interacts with the USART function in the Z8530 SCC device (US)
on the modem board. There are two main actions running continuously. Keyboard data, if available, is written to the data port
of channel A of the Z8530. Then it is sent to the modem via the
TXD line. The received data buffer in memory is checked to see
if there are any characters waiting in the queue to be displayed.
If there are, it displays them.
When the universal auto answer mode is selected, the system
will display:
UNIVERSAL AUTO ANSWER MODE
WAITING TO BE CALLED
Place the call from the remote modem. Upon ring detection and
Data Set Ready assertion, the system will display:
When the modem receives a character, it is passed to the RXD
line of the Z8530. This causes an interrupt to be generated.
RING DETECTED
DATA SET READY ON
The interrupt handling routine services the interrupt by transferring the received data byte from the data port to the next location in the buffer in memory. Housekeeping is done on the buffer
pointers and the loop then repeats itself.
followed by one of the following messages when the corresponding connection is made:
CONNECTED
CONNECTED
CONNECTED
CONNECTED
TO
TO
TO
TO
V.21
V.22
V.22
V.23
MODEM
MODEM
MODEM
MODEM
AT
AT
AT
AT
300 BPS
1200 BPS
2400 BPS
1200 BPS'
SOFTWARE
Structure
The overall operation of the software is flowcharted in Figure 4.
Figures 5 through 8 show subsections of the main routines, such
as basic default settings for the devices. The command flow to
control the modem in each of its configurations is shown in
Figures 9 through 13.
then
TERMINAL ON LINE ...
To terminate the mode anytime during the operation, press CTRL
BREAK. After connection is established, pressing' (single quote)
will also terminate the mode. After terminating the mode, press
RETURN to return to FORTH command entry level. Now type
MENU and press RETURN to disconnect the modem from the
line (if not terminated by the remote modem) and to display the
mode menu.
If an originate connection is selected from the menu, then the
flowcharts of Figure 11 and Figure 12 show the actions which
are performed to set up the modem, make the call and enter
the data state. The algorithm for the universal auto answer mode
is given in Figure 13. This allows the modem to connect with
an unknown calling modem which may be one of four different
standards; V.21, V.22, V.22 bis or V.23. The modem automatically reconfigures itself and connects to the remote modem.
Programming
The application note software is programmed in FORTH. The
FORTH screens are listed in Figure 15. Any FORTH system
implementing the FORTH '83 standard for execution on the IBM
PC should be compatible. The compiled screens presented here
add the extra customized FORTH primitives to the Kernel dictionary. Operation of the modem is governed by routines using
these words to control the hardware circuits from software. The
software can be user-customized for a particular application.
Alternatively, the listing is complete as supplied. There is an
interrupt driven dumb terminal program included, which is
capable of handling 2400 bps full duplex communications.
• Answering a call from a V.23 modem results in a half duplex
data mode connection. This application note software configures the modem for receiving by keeping R'fS inactive. In
order to transmit data after the remote modem has finished
transmitting, RTS must be made active.
5-58
Application Note
2400/1200/300 bps International Modem Design
BASIC DEVICES SETUP
IDLE MODE:
DISPLAY MENU
N
N: ORIGINATE
ANSWER MODE
ORIGINATE MODE
MAKE CALL WITH
R2424
N
CONNECT 7910
CONNECT R2424
CONNECT 7910
CONNECT R2424
DATA MODE
Figure 4.
Flowchart - International Modem Software Overview
5-59
240011200/300 bps International Modem Design
Application Note
Set receiver character size
and clock rate multiple
InWR4
Set RX number of stop bits in WR3
Reset Modems:
Set PPI PBS = 0
Set tra.nsmltter character
size In WRS
Walt 20 ms
Select all internal/external
clocking options in WRll
Clear reset:
Set PPI PBS = 1
Load tha baud rate generator
time constant (low byte)
for 2400 BPS data in WR12
Reset SCC:
Set PPI PB4 = 0
Load the baud rate generator
time constant (high byte)
for 2400 BPS data in WR13
Wait 20 ms
Clear reset:
Set PPI PB4 = 1
Enable bit rate generator in WR14
Enable receiver:
Modify WR3
Enable transmitter:
ModifyWR5
Figure 5.
Flowchart -
Reset Devices
Figure 6.
5-60
Flow~rt
- EI.aslc Del/Ices Setup: 8530
2400/1200/300 bps International Modem Design
Application Note
START
Write configuration
word to control
register
Display Menu Screen
Figure 7.
Flowchart - Basic Devices Setup: 82C55
Prompt for choice of action
by function key
N
Set bus bit in TX Register
0=1
Establish data communications
according to configuration and
mode selected (see Figures 11,
12 and 13)
Set bus bit in RX Register
0=1
Set OTR bit in TX Register
0=1
Switch to dumb terminal or
data handling routine
Set RTS bit in TX Register
9=1
Set AAE bit In TX Register
0=1
Set TX level bits in TX Register B
to desired value
Figure 8.
Figure 9.
Flowchart - Basic Devices Setup: R2424
5-61
Flowchart - Main Operation
Application Note
240011200/300 bps International Modem Design
Prompt for entry of phone number
Read phone number
digits into memory
Set DTMF bit = 1
Set eRa bit in TX=1
N
Get dial digit from memory
y
Write digit to dial digit register
DDRE bit=1?
Perform delay
N
y
Write FFH to dial digit register
Figure 10.
Flowchart -
5-62
Auto Dial
Application Note
2400/1200/300 bps International Modem Design
Reset all devices to known state
(Figure 5)
Set up all devices to basic state
(Figures 6, 7 and 8)
Select R2424 to control
RCCT & OH in DAA:
Set PPI PA6
0 and PA7
=
=1
Select 8530 V.24 signals to come
from/go to R2424:
Set PPI PA5 = 0
Select all analog signals
to DAA to come from R2424:
Set PPI PBO and PBl = 1
and PB2 and PB3 = 0
V: Default Condition
Set MODE bits in R2424 = 1001 B
Set 8530 baud rate for 1200
Perform Auto Dial
(Figure 10)
N
Give connect message
Switch to terminal routine
Figure 11.
Flowchart -
V.22 or V.22 bis Call Origination
5-63
2400/1200/300 bps International Modem Design
Application Note
(
START
)
t
Reset all devices to known state
(Figure 5)
t
Set up all devices to basic state
(Figures 6, 7 and 8)
t
Select R2424 to supply all
DAA control signals, all V.24
and all analog signals
(Figure 11)
V.23?
J
Y
I
Select 7910 configuration
for V.23. Set PPI PAO·PA4
I
N: V.21
Select 7910 configuration
for V.21. Set PPI PAO·PA4
t
DCD in
8530 = 1?
N
Auto dial
t
y
(7910)
Drive dummy RCCT and OH
signals on PPI:
Set PPI PC5 & PC6 = 1
t
I
Output connect message
I
Set 8530 RTS signal active
t
Enable 7910 signals generated
by PPI to control DAA:
Set PPI PA7 = 0 and
PA6 = 1
1
I
N
V.23?
t
Enable 7910 V.24 signals
to 8530: Set PPI PAS = 1
Y
t
I
Enable all analog signals
to come from 7910 to DAA
Set PPI PBO & PB1 = 0
and PB2 & PB3 = 1
t
Set 8530 baud rate
to 1200 bps
I
I
Set 8530 baud rate to 300 bps
r
Switch to terminal routine
t
Set R2424 CRQ bit in
TX = 0
I
+
DONE
Figure 12.
Flowchart -
V.21 or V.23 Call Origination
5·64
I
~
1
Application Note
240011200/300 bps International Modem Design
Reset all devices to known state
(Figure 5)
CALLED' message to terminal
N
Issue 'RING DETECTED'
message to terminal
N
message to terminal
1 Second delay
Figure 13.
Flowchart -
Universal Auto Answer Mode
5-65
2400/1200/300 bps International Modem Design
Application Note
y
Issue 'CONNECTED TO V.22
BIS MODEM AT 2400 BPS'
message to terminal
y
Issue 'CONNECTED TO V.22 MODEM
AT 1200 BPS' message to terminal
N
Set 8530 baud rate to 1200 bps
y
Issue 'CONNECTED TO V.23 MODEM
AT 1200 BPS' message to terminal
Issue 'CONNECTED TO V.21 MODEM
AT 300 BPS' message to terminal
Select 7910 V.23 configuration
Set PPI PAO·PA4
Select 7910 V.21 answer mode
configuration
Set PPI PAO·PA4
Select DAA control, V.24 and
analog signals from 7910
(Figure 12)
Select DAA control, V.24 and
analog signals to come from 7910
(Figure 12)
Set 8530 baud rate to 1200 bps
Set 8530 baud rate to 300 bps
Set 8530 RTS signal active
Switch to terminal routine
Figure 13. Flowchart - Universal Auto Answer Mode (Continued)
5·66
Application Note
2400/1200/300 bps International Modem Design
Screen # 69
o
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Screen # 70
o ( V21/V23 MODEM INTERRUPT HANDLER
1 FORTH DEFINITIONS HEX
27/1/86 MBW )
2
3 -1 CONSTANT COM1?
4
0 CONSTANT COM2?
5
6 COM1? .IF
0223 CONSTANT ASC PORT
7
0010 CONSTANT INT-MASK
8
OOOC CONSTANT INT-#
9
10 . THEN COM2? .IF
0223 CONSTANT ASC BASE
11
0008 CONSTANT INT-MASK
12
OOOB CONSTANT INT=:#
13
14 • THEN
15 -->
Screen # 71
o ( V21/V23 MODEM
1 DECIMAL
( IRQ4 )
( IRQ3 )
27/1/86 MBW )
INTERRUPT HANDLER
2
3 2VARIABLE LINKS
4 VARIABLE X VARIABLE V
5
6
7
8
9
10
11
FIX-VOC-LINKS
@V
VOC-LINK DUP X!
BEGIN
V @
WHILE
V @ HERE U<
IF
V @X @
ELSE V @ @ V
REPEAT
V @X
THEN
X @ @V
12
13
14
15 -->
Figure 14.
International Modem FORTH Screens
5-67
Application Note
2400/1200/300 bps International Modem Design
Screen # 7,2
o (
1
2
3
4
5
6
7
8
9
10
V21/V23 MODEM INTERRUPT HANDLER
BEGIN-MOD
1 ?DEPTH HERE LINKS
LATEST NAME> LINKS 4+ !
LIMIT 500 - SWAP - DP ! ;
LINKS @ DP
END-MOD
I
•
27/1/86 MBW )
•
I
FORGET-MOD
LINKS 4+ @
SHR4
LINKS @ 32 0 SKIP DROP
N>LINK W! FIX-VOC-LINKS
11
12
13
14
15 -->
Screen # 73
o ( V21/V23 MODEM
INTERRUPT HANDLER
27/1/86 MBW )
1
2 DECIMAL
17000 BEGIN-MOD
ASM86
END-MOD
3
4 HEX
5
6 2000 CONSTANT ASC_BUF_SIZE
7
8 CREATE ASC BUF ASC BUF SIZE ALLOT
9
ASC=BUF ASC=BUF=SIZE ERASE
10
11 VARIABLE ASC IN
12 VARIABLE ASC-OUT
13
14
15 -->
Screen # 74
o (
V21/V23 MODEM
1
2 0 INT_# 4
*
INTERRUPT HANDLER
2CONSTANT INT-VEC
3
4 2VARIABLE PREV ASC VEC
5
6
7
8
9
10
11
12
13
14
15 -->
Figure 14.
International Modem FORTH Screens (Continued)
5-68
27/1/86 MBW )
Application Note
2400/1200/300 bps International Modem Design
Screen # 75
o ( V21/V23 MODEM
INTERRUPT
HAtr~H:'::R
27/1/86 MBW )
1
2
3
4
5
6
7
8
9
10
INCR PTR
ROT
2 PICK @ +
2DUP <=
IF
SWAPELSE SWAP DROP
THEN SWAP ! ;
+ASC IN
+ASC-OUT
ASC IN ASC BUF SIZE INCR PTR
ASC=OUT ASC=BUF=SIZE INCR-PTR
11
12
13
14
15 -->
Screen # 76
o ( V21/V23 MODEM
1
2
3
4
?ASC
ASC_IN @ ASC_OUT @ <>
@ASC
BEGIN ?ASC
UNTIL ASC_OUT @ ASC BUF + C@
5
6
7
8
9
INTERRUPT HANDLER
#ASC
ASC OUT @ ASC IN @ 2DUP U>
IF ASC BUF-SIZE +
THEN
27/1/86 MBW )
1 +ASC OUT
- NEGATE
10
11
12
13
14
15 -->
Screen # 77
o ( V21/V23 MODEM INTERRUPT HANDLER
1 HEX
2 CREATE ASC_INT ASSEMBLER
3
STI
4
AX PUSH BX PUSH
5
DX PUSH DS PUSH
AX, CS MOV DS, AX MOV
6
7
DX, # ASC PORT MOV
AL, DX IN8
9
CLI
10
BX, ASC IN 2+ MOV
ASC_BUF [BX], AL MOV
11
12
13
14
15 -->
Figure 14.
International Modem FORTH Screens (Continued)
5-69
27/1/86 MBW )
Application Note
2400/1200/300 bps International Modem Design
Screen # 78
o ( V21/V23 MODEM
1
2
3
4
HAND~ER
27/1/86 MBW )
BX INC
BX , # ASC BUF SIZE CMP
1$ JNZ
BX , BX XOR
ASC IN 2+ I BX MOV
STIAL, # 20 MOV
# 20 I AL OUT
DS POP DX POP
BX POP AX POP
IRET
5
6
INTERRUPT
1$:
7
8
9
10
11
12
13 FORTH
14
15 -->
Screen # 79
o ( V21/V23 MODEM INTERRUPT HANDLER
1 HEX
2 : ASC-TRAP
PREV ASC VEC 2@ OR 0=
IF -INT=VEC @L
3
4
INT-VEC 2+ @L
5
PREV ASC VEC 2!
THEN
6
7
?CS: INT-VEC 2+ !L
8
ASC INT INT-VEC !L
27/1/86 MBW )
9
10
11
12
13
14
15 -->
Screen # 80
o ( V21/V23 MODEM
INTERRUPT HANDLER
1
2 : ASC-RELEASE
3
4
5
6
PREV ASC VEC 2@
INT-VEC 2+ !L
INT-VEC ! L " :
7
8
9
10
11
12
13
14
15 -->
Figure 14.
International Modem FORTH Screens (Continued)
5-70
27/1/86 MBW )
2400/1200/300 bps International Modem Design
Application Note
Screen # 81
o ( V21/V23 MODEM
INTERRUPT HANDLER
27/1/86 MBW )
1 HEX
2 : ASC-ENB
21 PC@
INT MASK NOT
21 PC!
3
4
5
6
AND
ASC IN OFF ASC OUT OFF
ASC=BUF ASC_BUF_SIZE ERASE
7
8
9
10
11
12
13
14
15 -->
Screen # 82
o ( V21/V23 MODEM
INTERRUPT HANDLER
27/1/86 MBW )
1 HEX
2
21 PC@
INT MASK OR
21 PC! ;
3 : ASC-DSB
4
5
6
7
8
9
10
11
12
13
14
15 -->
Screen # 83
o ( V21/V23 MODEM
INTERRUPT HANDLER
1
2
ASC-ON
ABC-TRAP
ASC-ENB
ASC-OFF
ASC-DSB
ASC-RELEASE
3
4
5
6
7
8
9
10
11
12
13
14
15 -->
Figure 14.
International Modem FORTH Screens (Continued)
5-71
27/1/86 MBW )
Application Note
2400/1200/300 bps International Modem Design
Screen # 84
o ( V21/V23 MODEM
1 HEX
INTERRUPT HANDLER
27/1/86 MBW )
2
3
4
ASC_TX_WAIT
BEGIN ASC PORT 1 UNTIL;
-
!ASC
ASC_TX_WAIT
PC@
40 AND
5
6
ASC_PORT PC! ;
7
8
9
10
11
12
13
14
15 -->
Screen # 85
o ( V21/V23 MODEM
1
2
3
INTERRUPT HANDLER
27/1/86 MBW )
HEX HERE OFFFO U>
4 .IF
5
6
7
CR
CR
CR
CR
8
9
10
11 .THEN
12 -->
13
14
15
FORGET COMl?
DECIMAL
." ERROR ..•• MUST BE LOADED BELOW FFFO ..
FORGET-MOD
Screen # 86
o ( V21/V23 MODEM DUMB TERMINAL
1 FORTH DEFINITIONS DECIMAL
2 HEX
27/1/86 MBW )
3 ( --- )
4 : TALK
CR
5
BEGIN
6
7
8
9
10
11
12
13
14
AGAIN
15 DECIMAL -->
." TERMINAL ON LINE ••
?ASC
IF
@ASC 7F AND EMIT
THEN
?TERMINAL
IF
KEY DUP 27 =
IF
DROP CLS QUIT
ELSE !ASC
THEN
THEN
Figure 14.
.. CR CR ASC-ON
International Modem FORTH Screens (Continued)
5-72
2400/1200/300 bps International Modem Design
Application Note
Screen # 87
o ( V21/V23 MODEM
TIMERS
1 DECIMAL
ALL ~
2
3
MS
4
0 DO 22 0 DO LOOP LOOP
5
SEC
6
1000 * MS
27/1/86 MBW )
7
8
9
10
11
12
13
14 DECIMAL
15 -->
Screen # 88
o ( V21/V23 MODEM
INITIALISATION
27/1/86 MBW
1 HEX
2
INIT.8255
81 233 PC! ~ ( 2 1/2 OUTPUT PORTS 1/2 INPUT
3 : RESET.MODEMS
231 PC@ DUP DF AND
SET PB5 TO 0 )
4
231 PC!
5
20 MS
6
20 OR 231 PC!
SET PB5 TO 1
7
50 MS ~
8
RESET.8530
231 PC@ DUP EF AND
SET PB4 TO 0
9
231 PC!
10
20 MS
11
10 OR 231 PC!
12
20 MS ~
13 : INIT
INIT.8255 RESET.MODEMS RESET.8530
( EVERYTHING )
14 DECIMAL
15 -->
Screen # 89
0 ( V21/V23 MODEM
ENABLES/DISABLES
27/1/86 MBW
1 HEX
2
EN.RCCT/OH.M
230 PC@ BF AND
( MAKE PA6=0 )
3
80 OR 230 PC!
( MAKE PA7=1 )
4
EN.RCCT/OH.79 230 PC@ 7F AND
( MAKE PA7=0 )
5
40 OR 230 PC!
( MAKE PA6=1 )
6
EN.V24.79
230 PC@ 20 OR 230 PC!
( MAKE PA5=1 )
7
EN.V24.M
230 PC@ DF AND 230 PC!
( MAKE PA5=0 )
8
EN. ANALOG. M
231 PC@ 03 OR
( PBO/ PB1=1 )
9
F3 AND 231 PC!
( PB2/ PB3=0 )
10
EN.ANALOG.79
231 PC@ OC OR
( PBO/ PB1=0 )
11
FC AND 231 PC!
( PB2/ PB3=1 )
12
ENABLE.INT.8530
1 222 PC! 10 222 PC!
( SET INT ON RX
13
9 222 PC! OA 222 PC!
( MIE
14 DECIMAL
15 -->
Figure 14.
International Modem FORTH Screens (Continued)
5-73
Application Note
240011200/300 bps International Modem Design
Screen # 90
o ( V21jV23 MODEM
ENABLES/DISABLES
27/1/86 MBW )
1 HEX
2
3
4
5
6
7
8
9
10
EN.M
EN.RCCT/OH.M EN.V24.M EN.ANALOG.M
( ENABLE ALL R2424 SIGNALS ) ;
EN.79
EN.RCCT/OH.79 EN.V24.79 EN.ANALOG.79
( ENABLE ALL 7910 SIGNALS ) ;
NEWC.R
11
12
NEWC.T
13
14 DECIMAL
20E PC@ 08 OR
BEGIN 20E PC@
21E PC@ 08 OR
BEGIN 21E PC@
20E PC!
8 = NOT UNTIL
21E PC!
8 = NOT UNTIL
15 -->
Screen # 91
o ( V21/V23 MODEM
R2424 BIT SETTING
1 OF 2
27/1/86 MBW )
1 HEX
2
3
4
5
6
7
8
9
10
NOW
(FLAG REGISTER MASK -SWAP DUP 2SWAP SWAP ROT ROT
ROT 0 = IF
FF SWAP - SWAP DUP PC@
ROT AND SWAP PC!
ELSE
SWAP DUP PC@ ROT
OR SWAP PC!
THEN
11
12
13
14
15 -->
Screen # 92
o ( V21/V23 MODEM R2424 BIT SETTING 2 OF 2
27/1/86 MBW )
1
DUP 20A >= IF
2
DUP 200 <= IF
3
NEWC. R ELSE
4
DUP 219 >= IF
5
DUP 210 <= IF
6
NEWC.T
7
THEN
8
THEN
9
THEN
10
THEN DROP
11
12
13
14
15 -->
Figure 14.
International Modem FORTH Screens (Continued)
5-74
2400/1200/300 bps International Modem Design
Application Note
Screen # 93
o ( V21/V23 MODEM
R2424 D1Tr::rLEI:;~!~""
1 HEX
2
IS
(REGISTER MASK -- BIT VALUE
27/1/86 MBW )
3
4
SWAP PC@ AND IF 1 ELSE 0 THEN :
5
6
7
8
9
10
11
12
13
14 DECIMAL
15 -->
Screen # 94
o ( V21/V23 MODEM R2424 RECEIVER BIT MASKS
1 HEX
2
BUS.R
20D 80
3
CRQ.R
20D 40
4
LCD
20D 04
5
AL.R
20B 01
6
ERDL.R
20A 80
7
RDL.R
20A 40
8
DL.R
20A 20
9
ST.R
20A 20
10
TONE
208 80
11
ATD
208 40
12
TM
208 02
13
RLSD
208 01
14 DECIMAL
15 -->
Screen # 95
o ( V21/V23 MODEM R2424 TRANSMITTER BIT MASKS
1 HEX
2
DDRE
21E 01
3
BUS.T
21D 80
4
CRQ.T
21D 40
5
DATA
21D 20
6
AAE
21D 10
7
DTR
21D 08
8
DSRA
21C 80
9
GTE
21B 10
10
GTS
21B 08
11
3DB
21B 04
12
DTMF
21B 02
13
AL.T
21B 01
14 DECIMAL
15 -->
Figure 14.
International Modem FORTH Screens (Continued)
5·75
27/1/86 MBW )
27/1/86 MBW )
Application Note
240011200/300 bps International Modem Design
Screen # 96
R2424 TRANSMITTER BIT MASKS
o ( V21/V23 MODEM
1 HEX
21A 80
2
ERDL.T
21A 40
3
RDL.T
21A 20
4
DL.T
5
ST.T
21A 10
219 40
6
RTRN
7
ORG
219 20
8
LL
219 10
9
RTS
219 08
10
CC
219 04
219 02
11
EF
12
DLO
218 80
13
CTS
218 40
14 DECIMAL
15 -->
27/1/86 MBW )
Screen # 97
o ( V21/V23 MODEM R2424 TRANSMITTER BIT MASKS
1 HEX
2
DSR
218 20,
3 : RI
218 10;
27/1/86 MBW )
4
5
6
7
8
9
10
11
12
13 DECIMAL
14 -->
15
Screen # 98
o ( V21/V23 MODEM R2424 MULTIPLE BITS
1 HEX
2 : V.22/1200
20A PC@ F9 AND 09 OR 20A
3
NEWC.R
4
21A PC@ F9 AND 09 OR 21A
5
NEWC.T ;
V.22/2400
20A PC@ FD AND OD OR 20A
6
7
NEWC.R
8
21A PC@ FD AND OD OR 21A
9
NEWC.T ;
10
SPEED?
209 PC@ 10 / DUP 4 / 4 *
11
27/1/86 MBW )
PC!
SET RX MODE BITS
PC!
SET TX MODE BITS
PC!
PC!
-
( --
VALUE OF BITS )
12
13
14 DECIMAL
15 -->
Figure 14. 'International Modem FORTH Screens (Continued)
5-76
Application Note
240011200/300 bps International Modem Design
Screen # 99
o ( V21/V23 MODEM
1 HEX
2
ODB
21B PC@
3
-2DB
21B PC@
21B PC@
4
-4DB
21B PC@
5
-6DB
6
-8DB
21B PC@
-lODB 21B PC@
7
8
-12DB 21B PC@
9
-14DB 21B PC@
10
R2424 TRANSMIT LEVEL
OF
3F
5F
7F
9F
BF
DF
FF
AND
AND
AND
AND
AND
AND
AND
AND
00
20
40
60
80
AO
CO
EO
OR
OR
OR
OR
OR
OR
OR
OR
21B
21B
21B
21B
21B
21B
21B
21B
PC!
PC!
PC!
PC!
PC!
PC!
PC!
PC!
27/1/86 MBW )
NEWC.T
NEWC.T
NEWC.T
NEWC.T
NEWC.T
NEWC.T
NEWC.T
NEWC.T
11
12
13
14 DECIMAL
15 -->
Screen # 100
o ( V21/V23 MODEM 8530 SETUP
27/1/86 MBW )
1 ( THIS DEFAULT SETTING CONFIGURES THE 8530 FOR 8 BIT DATA,
)
2 ( 1 STOPBIT, ENABLES THE TRANSMITTER & RECEIVER, SETS DTR, RTS)
3 ( SETS THE CLOCKS, XTAL I/P,AND THE BIT RATE GENERATOR FOR 2400)
4 HEX
5
DEFAULT. 8530
ENABLE. INT. 8530
6
4 222 PC! 44 222 PC! ( SET RX 8 BITS X16 CLOCK
7
3 222 PC! CO 222 PC! ( 1 STOPBIT
8
5 222 PC! 60 222 PC! ( SET TX 8 BITS
9
B 222 PC! D4 222 PC! ( CLOCK OPTIONS
10
C 222 PC! lE 222 PC! ( BAUD RATE GEN LOW FOR 2400
11
D 222 PC! 00 222 PC! ( BAUD RATE GEN HI FOR ALL
12
E 222 PC! 01 222 PC! ( ENABLE BIT RATE GEN
)
13
3 222 PC! Cl 222 PC! ( ENABLE RX
)
14
5 222 PC! 68 222 PC! ( ENABLE TX
)
15 DECIMAL -->
Screen # 101
o ( V21/V23 MODEM CHANGE 8530 PARAMETERS
27/1/86 MBW )
1 HEX
2
RX.ENABLE
3 222 PC! C1 222 PC!
3
RX.DISABLE
3 222 PC! CO 222 PC!
4
RTS.8530.0N
5 222 PC! EA 222 PC!
5
RTS.8530.0FF
5 222 PC! E8 222 PC!
6
300BPS.8530
C 222 PC! FE 222 PC!
7
1200BPS.8530
C 222 PC! 3E 222 PC!
8
2400BPS.8530
C 222 PC! lE 222 PC!
9
DTR/RTS.8530.0FF 5 222 PC! 68 222 PC!
10
DTR.8530.0N
5 222 PC! E8 222 PC!
11
12
13
14 DECIMAL
15 -->
Figure 14. International Modem FORTH Screens (Continued)
5-77
Application Note
2400/1200/300 bps International Modem Design
Screen # 102
o ( V21/V23 MODEM DAA CONTROL MASKS
1 HEX
FLAG
232 04
2
CCT
FLAG
3
OH
232 08
FLAG
4
RCCT.79 232 20
232 40
FLAG
OH.79
5
27/1/86 MBW )
6
7
8
9
10
11
12
13
14 DECIMAL
15 -->
Screen # 103
o ( V21/V23 MODEM R2424 BASIC MODEM SETUP
1 HEX
2
DEFAULT. 2424
3
INIT
4
EN.M
5
V.22/2400
6
1 BUS.R NOW 1 BUS.T NOW
7
1 DTR NOW
8
1 RTS NOW
9
1 AAE NOW
10
ODB
( NO ATTENUATION BEFORE DAA )
11
DEFAULT. 8530
12
13
14 DECIMAL
15 -->
Screen # 104
o ( V21/V23 MODEM 8530
1 HEX
2
RXREADY?
BEGIN 222
3 : TXREADY?
BEGIN 222
4 : DCD.8530? BEGIN 222
5
STATUS
27/1/86 MBW )
PC@ 1 AND 1 = UNTIL ;
PC@ 4 AND 4 = UNTIL ;
PC@ 08 AND 08 - UNTIL
6
7
8
9
10
11
12
13
14 DECIMAL
15 -->
Figure 14.
27/1/86 MBW )
International Modem FORTH Screens (Continued)
5·78
Application Note
2400/1200/300 bps International Modem Design
Screen # 105
o ( V21/V23 MODEM
PHONE NUMBER ENTERING
1 HEX
2 0 VARIABLE PHONE.NUMBER 20 ALLOT
3
PHONE.NUMBER.PROMPT
4
." ENTER PHONE NUMBER"
27/1/86 MBW )
5
6
7
READY. TO. DIAL?
BEGIN DDRE IS UNTIL
8
9
10
11
12
13
14 DECIMAL
15 -->
Screen # 106
o ( V21/V23 MODEM DIALER
27/1/86 MBW )
1 HEX
2
DIAL PHONE.NUMBER.PROMPT
3
PHONE.NUMBER 20 EXPECT CR
4
1 DTMF NOW 1 CRQ. T NOW ." DIALING # " 1 SEC PHONE.NUMBER
5
BEGIN DUP 1+ SWAP C@ DUP DUP 0=
6
IF
7
DROP DROP 1
8
ELSE DUP 44 = IF
2 SEC DROP DROP 0
9
ELSE READY. TO. DIAL?
10
OF AND 210 PC! EMIT 0
11
12
THEN
13 THEN
14 UNTIL DROP READY.TO.DIAL? FF 210 PC! -14DB CLS
15 DECIMAL -->
Screen # 107
o ( V21/V23 MODEM
1 HEX
2
V21.ANS.7910
3
V21.0RG.7910
4
V23.7910
5
V23.EQU.7910
27/1/86 MBW )
7910 CONFIGURATION
230
230
230
230
PC@
PC@
PC@
PC@
EO
EO
EO
EO
AND
AND
AND
AND
05
04
06
07
OR
OR
OR
OR
230
230
230
230
PC!
PC!
PC!
PC!
6
7
8
9
10
11
12
13
14 DECIMAL
15 -->
Figure 14.
International Modem FORTH Screens (Continued)
5-79
Application Note
2400/1200/300 bps International Modem Design
Screen f 108
o ( V21jV23 MODEM 7910 CONNECT V.21
1 HEX
2
CONNECT.V21.0RG
3
CLS." V.21 300BPS MODE" CR
4
DEFAULT. 2424
V21.0RG.7910
5
6
DIAL
7
1 RCCT.79 NOW 1 OH.79 NOW EN.79
0 CRQ.T NOW
8
9
DTR.8530.0N
DCD.8530?" CARRIER DETECTED • • • ON LINE"
10
11
RTS.8530.0N
12
300BPS.8530 TALK
13
14 DECIMAL
15 -->
Screen f 109
o ( V21/V23 MODEM 7910 CONNECT V.23
1 HEX
2
CONNECT.V23.0RG
3
CLS." V.23 1200BPS MODE" CR
4
DEFAULT. 2424
V23.7910
5
6
DIAL
7
1 RCCT.79 NOW 1 OH.79 NOW EN.79
8
0 CRQ.T NOW
9
DTR.8530.0N
10
DCD.8530?" CARRIER DETECTED • • • ON LINE"
11
RTS.8530.0N
1200BPS.8530
12
TALK
13
14 DECIMAL
15 -->
Screen f 110
o ( V21/V23 MODEM 2424 CONNECT V.22
1 HEX
2
CONNECT.V22.0RG
3
CLS." V.22 1200BPS MODE" CR
4
DEFAULT. 2424 V.22/1200 1200BPS.8530
5
DIAL
6
BEGIN CTS IS 1 .. UNTIL
.. CARRIER DETECTED
7
CR CR TALK
~
8
CONNECT.V22.2400
9
CLS." V.22 2400BPS MODE" CR
10
DEFAULT. 2424
DIAL
11
12
BEGIN CTS IS 1 = UNTIL
"CARRIER DETECTED
13
CR CR TALK
14 DECIMAL
15 -->
CR CR
27/1/86 MBW )
CR CR
27/1/86 MBW )
• • • ON LINE ..
• • • ON LINE "
Figure 14. International Modem FORTH Screens (Continued)
5-80
27/1/86 MBW )
Application Note
2400/1200/300 bps International Modem Design
Screen # 111
o ( V21/V23 MODEM V.22 ANSWER MODE CONNECTIONS
27/1/86 MBW )
1 HEX
2
V22BIS.CONNECTION
3
." CONNECTED TO V.22 BIS MODEM AT 2400 BPS" CR CR
4
TALK
5
6
7
8
9
V22.CONNECTION
." CONNECTED TO V. 22 MODEM AT 1200 BPS "
1200BPS.8530
TALK
CR CR
10
11
12
13
14 DECIMAL
15 -->
Screen # 112
o ( V21/V23 MODEM V.21/V.23 ANSWER MODE CONNECTIONS 27/1/86 MBW )
1 HEX
2
V21.CONNECTION
." CONNECTED TO V.21 MODEM AT 300BPS " CR CR
3
4
V21.ANS.7910
5
1 RCCT.79 NOW 1 OH.79 NOW EN.79
6
DTR.8530.0N RTS.8530.0N
7
300BPS.8530
8
TALK
7
9
V23.CONNECTION
10
." CONNECTED TO V. 23 MODEM AT 1200BPS" CR CR
11
V23.7910
12
1 RCCT.79 NOW 1 OH.79 NOW EN.79
13
DTR.8530.0N
14
1200BPS.8530
15
TALK
DECIMAL -->
Screen # 113
o ( V21/V23 MODEM AUTO ANSWER MODE 1 OF 2
1 HEX
2
AUTO. ANSWER
3
DEFAULT. 2424
4
CLS." UNIVERSAL ANSWER MODE " CR
5
." WAITING TO BE CALLED" CR
6
BEGIN RI IS UNTIL
7
." RING DETECTED •
" CR
8
BEGIN DSR IS UNTIL
" DATA SET READY ON
"CR
9
10
1 SEC
11
12
13
14 DECIMAL
15 -->
Figure 14. International Modem FORTH Screens (Continued)
5-81
27/1/86 MBW )
Application Note
2400/1200/300 bps International Modem Design
Screen # 114
o ( V21/V23 MODEM AUTO ANSWER MODE 2 OF 2
27/1/86 MBW )
1 HEX
2
SPEED? DUP 3 = IF V22BIS.CONNECTION ELSE
3
DUP 2 = IF V22.CONNECTION
ELSE
4
THEN THEN DROP
5
RLSD IS IF V23.CONNECTION ELSE V21.CONNECTION THEN
6
7
8
9
10
11
12
13
14 DECIMAL
15 -->
Screen # 115
o ( V21/V23 MODEM
MENU SCREEN
27/1/86 MBW )
1 HEX
2
MENU INIT BEGIN
3
CLS A 3 GOTOXY
II CR
II ROCKWELL INTERNATIONAL'S
4
CR
A SPACES
II CR
II INTERNATIONAL MODEM ...•
5
CR CR A SPACES
II F1
V.21 ORIGINATE
II CR
6
A SPACES
II F2
V.22 ORIGINATE 1200
II CR
7
A SPACES
II F3
V.22 ORIGINATE 2400
II CR
8
A SPACES
II F4
V.23 ORIGINATE
II CR
9
A SPACES
II F5
AUTO ANSWER/CONFIGURE II CR
10 PCKEY DROP DUP 3B
IF CONNECT.V21.0RG ELSE
11
DUP 3C
IF CONNECT.V22.0RG ELSE
12
DUP 3D
IF CONNECT.V22.2400 ELSE
13
DUP 3E
IF CONNECT.V23.0RG ELSE
14
DUP 3F
IF AUTO.ANSWER
15 THEN THEN THEN THEN THEN SWAP DROP UNTIL 1 MENU DECIMAL -->
Screen # 116
o
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Figure 14.
International Modem FORTH Screens (Continued)
5-82
Application Note
'1'
Quality of Received Data
for Signal Processor-Based Modems
Rockwell
by Carlos A. Laiz, Product Applications Engineer
Semiconductor Products Division, Newport Beach, California
INTRODUCTION
block diagrams that relate the RAM access codes to specific
functions are shown in Figures 1 through 4. Refer to the applicable modem data sheet for specific details regarding an
individual modem.
This application note provides the modem design engineer
with detailed information on the generation and interpretation of diagnostic data featured in Rockwell's signal processor
(SP)-based modems.
Rockwell's plug-compatible SP-based modems can generate a
variety of diagnostic data. This data is extremely useful in the
evaluation of modem performance and line conditions. A microprocessor interface can readily access diagnostic data and other
useful signals via the SP interface memory.
EVE PATTERN
A quadrature eye pattern is an extremely useful diagnostic tool.
The visual display of an eye pattern can be monitored to identify common line disturbances, as well as defects in the
modulationldemodulation processes.
The diagnostic capabilities of specific Rockwell modems are
summarized in Table 1.
The ideal eye patterns or signal constellations for the various
encoding methods are illustrated in Figures 5 through 10. By
performing digital-to-analog (D/A) conversion of the received
signal point data (refer Table 2, Node 9), an eye pattern can be
displayed on an oscilloscope. Two methods of eye pattern
generation are available:
ACCESSING DIAGNOSTIC DATA
Diagnostic data can be readily accessed via the microprocessor
interface. The host processor must store the access code corresponding to the desired data in the RAM access register (See
Table 2). The signal processor then stores the desired data in
diagnostic data registers. The data available flag (R48DP,
R96DP, R96FT and R96FAX only) in the respective interface
memory sets when the signal processor writes data into
diagnostic register zero and resets when the host reads data
from register zero and is used to handshake with the diagnostic
data registers. Diagnostic data is generated in 16-bit double
preciSion form, although for most applications only the most
significant byte of data is necessary. The RAM access codes
for the SP-based modems are shown in Table 2. Functional
Table 1.
1. The microprocessor can read the received signal points and
then write this data into two memory mapped D/A converters.
Figure 11 shows a typical microprocessor interface eye pattern generator. A typical parallel eye pattern algorithm is
shown in Figure 12.
2. High speed modems (4800 bps and above) can generate
diagnostic data serially through hardware pins in the modem
connector.
Summary of Diagnostic Capabilities for SP-Based Modems
Eye Pattern
Parallel MPU Bus
EQM
Value
Error
Vector
Phase
Error
Access to
SP RAM
Space 2
R1212M
R1212DC
X
X
1
1
X
X
X
X
X
X
R2424M
R2424DC
X
X
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Modem
R48DP
R96DP
R96FT
R96FAX
Serial
X
X
X
X
X
X
X
X
Notes:
1. EOM may be computed by the host processor from the error vector data.
2. See RAM access codes (Table 2) and block diagrams (Figures 1-4).
Document No_ 29220N71
Application Note
5-83
Order No. 671
February 1985
g
Application Note
Signal Processor-Based Modems
Table 2.
R1212M/DC
R2424M/DC
Node
No.
Function
Access Chip
Codes No.
RAM Access Codes
R48DP/R96DP
Reg.
No.
RAM Access Chip
X
Y
No.
R96FT
Reg.
No.
R96FAX
RAM Access Chip
X
Y
No.
Reg.
RAM
Chip
No. Access No.
Reg.
No.
1
Received Signal
Samples (and Output)
2
Demodulator Output
56
0
2,3,4,5
C2
42
1
0,1,2,3
CO
40
1
0,1,2,3
3
Low Pass Filter Output
40
0
2,3,4,5
D4
54
1
0,1,2,3
DD
5D
1
0,1,2,3
4
Average Energy
-
04
1
0,1
-
32
1
0,1
DC
0
2,3
5
AGC Gain Word
81
-
1
2,3
2E
1
2,3
81
0
2,3
6
Equalizer Input
40
7
Equalizer Taps
8
Unrotated Equalizer
Output
9
Rotated Equalizer
Output (Received
Point Eye Pattern)
11
0
10
Decision Points (Ideal
Eye Pattern Points)
51
11
Error Vector
(Rotated Error)
12
Rotation Angle
13
Frequency Correction
14
EOM
.
15
Dual Point
16
Group II Baseband
Signal
17
CO
1
2,3
DC
61
2
0,1,2,3
2,3,4,5
A2
22
2
0
2,3,4,5
E2
62
52
0
2,3,4,5
E3
12
0
4,5
AA
2
2,3
A7
-
2
2,3
AE
2E
2
0,1,2,3
42
0
54
0
0,1,2,3
1
0,1,2,3
1
0,1,2,3
El
61
2
0,1,2,3
61
1
0,1,2,3
0,1,2,3
E2
62
2
0,1,2,3
22
1
0,1,2,3
2
0,1,2,3
E8
68
2
0,1,2,3
62
1
0,1,2,3
63
2
0,1,2,3
E5
65
2
0,1,2,3
63
1
0,1,2,3
00
2
0,1
A7
-
2
2,3
00
1
0,1
A8
1
2,3
AB
1
2,3
C8
1
2,3
Group II AGC
Gain Word
AD
1
2,3
18
Group II AGC
Slew Rate
AA
1
2,3
19
Group II PLL
Frequency Correction
C2
1
2,3
20
Group II
PLL Slew Rate
FO
1
2,3
21
Group II
BlacklWhite Level
2A
1
0,1
22
Self Test
Error Counter
00
0
2,3,4,5
10
0
2,3
41·4D
0
2,3,4,5
53
0
2,3,4,5
Equalizer Output
El
2,3
0,1,2,3
0,1,2,3 01·20
01·0D
0
2,3,4,5 81·AO
CO
0
0,1,2,3
25
0,1,2,3 81·AO
CO
2
Phase Error
0,1,2,3
2
2,3
2
Input Signal to
Equalizer Taps
2
1
40
23
40
01·20
-
01·20
24
CO
-
AC
Note: • EOM value may be computed by the host processor from error vector data, node 11.
5-84
-
2
2,3
-
Application Note
Signal Processor-Based Modems
Receiver/Equalizer Section
.
TONE
FSK
DETECTOR
r-------IA
I
I
1
Ir - - ' - - - ,
I
CARRIER
DETECTOR
I
I
I
I
RX SP
TRAINING
DETECTOR
....._....1...-----.
TIMING
RECOVERY
I
I
DATA
OUTPUT
I
L.. -
-
-
-
1 '---,------'
I
DESCRAMBLER
SYNC
TO
ASYNC
CONVERTER
JITTER
TRACKER
Transmitter Section
TX SP
ASYNC
TO
SYNC
CONVERTER
~
LOW PASS
FILTER
~
1
f
INPUT
~iTA
~ SCRAMBLER
f+
.
DATA
ENCODER
t
~
~
COW'ASS,
FILTER
FSK
GENERATOR
I
I
I
I
t
SELF TEST
PATTERN
GENERATOR
COMPROMISE
EQUALIZER
t
SIGNAL
POINT
ROM
~
iTA
LK
10-
1 - - - - ---1
COS (wt)
SIGNAL
STRUCTURE
CONTROL
SIN (wt)
CLOCK
r-- DATA
r.. TIMING
-
t
DIGITAL TO
ANALOG
CONVERTER
I
t
I
I
BAND
SPLIT
FILTER
I
t
I
LOW PASS
I
FILTER
I
I
IL _____
-.J
DTMF
GENERATOR
,[
EXTERNAL
CLOCK
TRACKER
f----
REFERENCE
Figure 1.
R1212/R2424 Processing Flow Diagram
5·85
LINE
r---f- INTERFACE
(DAA)
PASSBAN D
LINE
SIGNAL
»
'0
"2-
0"
S»
C)"
:::s
Z
o
CD
TRANSMITTER
DATA INPUT
BAUD RATE DEVICE-TRANSMITTER
IA DEVICE-TRANSMITTER
01
a,
0>
RECEIVER
DATA
OUTPUT
en
ii"
:::s
!!.
"'tJ
a
(")
CD
til
til
o
?
m
S»
til
CD
Q.
s:
o
Q.
CD
3
Figure 2.
R48DP/R96DP/R96FT/R96FAX (Group 3) Processing Flow Diagram
til
»
'tJ
"20"
D)
0"
:l
Z
2(1)
IA DEVICE-TRANSMITTER
IA DEVICE-RECEIVER
&
-..j
en
cS"
:l
!.
RECEIVER
DATA
."
an
(1)
~
o
~
m
D)
til
(1)
Q.
s::
o
Q.
(1)
3
Figure 3.
R96FAX (Group 2) Processing Flow Diagram
mI
til
l>
'a
'E.
C:;"
a
0::J
Z
~
TRANSMmER
DATA
1850 Hz
IA DEVICE-TRANSMITIER
~
IA DEVICE-RECEIVER
en
fS"
::J
!.
RECEIVER
DATA
"'U
a
m
o
i'
III
Ia.
3!:
oa.
CD
3
Figure 4.
R96FAX FSK Processing Flow Diagram
(I)
Application Note
Signal Processor-Based Modems
•
3
• 3j2
03
0
0
1
0°
0
0
0
45°
0
1
0
90°
0
1
1
135°
1
1
1
180°
1
1
0
225°
1
0
0
270°
1
0
1
315°
j2
•
•1
1
180°
•
3
5
0°
•
•
PHASE
CHANGE
02
•
04
ABSOLUTE
PHASE
01
RELATIVE
AMPLITUDE
0
3
1
5
0
j2
1
3j2
0°,90°,
180°,270°
45°,135°,
225°,315°
Figure 5. Ideal Eye Pattern-V.29/9600 bps
90°
3
BOUNDARIES
•
180°
•
1
•1
TRIBIT ENCODING:
j2
3
•
0°
IN V.2917200 BPS FALLBACK MODE, DATA IS ENCODED IN
GROUPS OF 3 BITS OR TRIBITS. THE ENCODING IS AS FOR
V.29/9600 BPS ABOVE EXCEPT THAT: THE FIRST DATA BIT IN
TIME DETERMINES 02 OF THE MODULATOR OUADBIT. THE
SECOND AND THIRD BITS IN TIME DETERMINE 03 AND 04,
RESPECTIVELY. 01
0 FOR ALL EIGHT SIGNAL ELEMENTS.
=
270°
Figure 6.
Ideal Eye Pattern-V.29/7200 bps
5-89
Application Note
Signal Processor-Based Modems
90·
DIBIT ENCODING:
DATA BITS
180·
PHASE
CHANGE
00
O·
01
90·
11
180·
10
270·
RELATIVE
AMPLITUDE
CONSTANT
270·
Figure 7.
Ideal Eye Pattern-V.29/4800 bps and V.27/BISITERl2400 bps
90·
TRIBIT ENCODING:
TRIBIT
VALUE
180·
0 0 1
O·
0 0 0
45·
0 1 0
90·
0 1 1
135·
1 1 1
180·
1 1 0
225·
1 0 0
270·
1 0 1
315·
270·
Figure 8.
V.27 BISITER/4800 bps
5-90
PHASE
CHANGE
RELATIVE
AMPLITUDE
CONSTANT
Application Note
Signal Processor-Based Modems
90 0
•
180 0
DIBIT
VALUES (1200)
BIT VALUES
(600 BPS)
PHASE
CHANGE
00
o
+90 0
01
11
+270 0
10
+180 0
270 0
Figure 9.
V.22 A/B 1200 bps/600 bps
90°
PHASE QUAD. 2
11
•
BOUNDARI~S 10
180 0
01
•
10
•
11
•
00
01
•
00
•
00
01
•
00
•
00
•
10
11
10
01
11
•
FIRST TWO BITS IN
QUADBIT [2400 BIT(S)]
OR DIBIT VALUES
[1200 BIT(S)]
PHASE QUADRANT 1
•
•
•
•
PHASE
QUADRANT CHANGE
1 2 3 -
2
3
4
4- 1
90 0
1- 1
2- 2
3- 3
4- 4
00
00
•
01
1 -
•
11
PHASE QUAD. 3
3- 2
4- 3
1 -
270 0
100
DATA IS ENCODED IN QUADBITS. THE FIRST TWO BITS OR
DIBIT SELECT ONE OF FOUR QUADRANTS. THE SECOND DIBIT
SELECTS ONE OF FOUR POINTS IN THAT QUADRANT, AS
SHOWN BELOW.
Figure 10. V.22 B15/4800 bps
5·91
4
2- 1
270 0
3
2- 4
3- 1
4 2
180 0
Signal Processor-Based Modems
Application Note
+12V
-12V
FULLY
DECODED
MEMORY
LOCATION
B~
.. 161
17
LE
2
DO
X-OU T
(SCO PEl
LSB
3
D1
Vout
4
D2
BUFFERED
,.PROCESSOR
DATA BUS
O.~:,.F
5
D3
NE5018
X-DAC
6
D4
OFFSET
8
De
9
D7
MSB
pI
.$f-. -e
~~
IN914
~
ACOMP
1~
0.1,. +12V
-::0.1,. 19 17
FULLY
DECODED
MEMORY
LOCATION
l,
100pF
74LS04
~8
~2KII
SUM
7
D5
V
*
..
O.O~,.F
116
LE
Y-O UT
(SCOPE)
LSB
VOU!
NE5018
Y-DAC
SUM
OFFSET
T
=rL
,..
.0.
l
1000pF
MSB
ACOMP
1~
=
Figure 11. Typical Microprocessor Bus Eye Pattern Generator
5-92
12KII
IN914B
-=::
*
Application Note
Signal Processor-Based Modems
WRITE ACCESS
CODE FOR
RECEIVED POINT
EYE PATTERN:
ACCESS CODE--+
(RAM ACCESS REG.]
N
READ BYTE 3
DIAGNOSTIC DATA
REG. (MSB ONLY)
WRITE DATA
INTO X-DAC
READ BYTE 1
DIAGNOSTIC DATA
REG. (MSB ONLY)
WRITE DATA
INTO Y-DAC
READ BYTE 0
DIAGNOSTIC DATA
REG. TO CLEAR
DATA AVAILABLE
FLAG
Figure 12. Typical Microprocessor Eye Pattern Generation Loop (R96DP/R48DP)
5-93
Application Note
Signal Processor.. Based Modems
The hardware necessary to generate a serial eye pattern along
with the relevant timing signals are shown in Figures 13 and 14.
The eye pattern consists of dots or received signal pOints. Each
pOint represents the location of a received signal element in the
+5
0.1"F
14
9
A
EYEX
2
EYEClK
6
8
+5V
ClR
741164
B
7
ClK
EYESYNC
~
3
4
5
6
10
11 12
':"
EYEY
2345678
10 lSB
X-OUT
f-----1I--+-~ lE
14 REF OUT
13
REF IN
r----I-N9-1-4-B~P---O (SCOPE)
NE5018
0.01"
-12V
+5V
0.1"F
~
...------------''---1g':"
+5V
741164
7
ClK
4
5
2 3 4
10 lSB
lE
14 REF OUT
13 REF IN
Nc
5
6
7
8
V-OUT
F----IN-9-1-4B-.......---O (SCOPE)
NE501B
12 ADJ
1000pF
-12V
Figure 13. Serial Eye Pattern Generator
5-94
Application Note
Signal Processor-Based Modems
r
tL-__. . .
EyESyNC"lL._ _ _ _ _""
MSB
NOTE: BITS 9 AND 10 ARE IGNORED
Figure 14. Serial Eye Pattern Signal Timing
baseband signal plane. In polar coordinates each point
represents a magnitude and differential phase shift. Eye pattern
data is updated at the baud rate so the oscilloscope display
appears to be a continuous Signal constellation.
ERROR VECTOR AND EQM VAWES
Transient phenomena are difficult to observe in a quadrature
eye pattern. Also, the proper interpretation of the eye pattern
is a function of the observer's training and requires constant
attention. Rockwell's signal processor modems generate error
vector and Eye Quality Monitor (EQM) data that are more suitable
for microprocessor manipulation and interpretation.
For a DPSK (Differential Phase Shift Keyed) modem, the phase
shift from one signal element to the next is decoded to recover
data. For a QAM (Quadrature Amplitude Modulation) modem,
both amplitude and differential phase shift are decoded to
recover data.
The error vector is defined as the angle and magnitude difference
between an actual received signal point and its ideal location
in the baseband signal plane (refer to Figure 16). Error vectors
are represented as complex numbers whose real and imaginary
components may be read out of the modem's diagnostic
registers once per baud. An EQM value may be obtained by processing the error vector data to obtain a positive hexadecimal
value whose magnitude is an indicator of the quality of the
received signal or probability of error of received signal pOints.
In the case of high speed modems (R48DP, R96DP, R98FT, and
R96FAX), the error vector is processed by the SP devices and
the EQM value is available through the diagnostic data registers.
For medium speed modems (R1212 and R2424), the EQM value
may be computed by the host processor using the error vector
data. An algorithm for computing EQM values is given below.
Assume a V.2211200 bps configuration (R1212 modem), and that
initially a dot is displayed at point 1 of Figure 9. If the first dibit
received is 10, the pOint displayed will be point 2, correspond·
ing to a 1800 shift in phase. If the second dibit is a 00 (90 0 ),
point 3 will be displayed. In this fashion a continuous stream
of random data produces the display of Figure 9.
TYPICAL LINE DISTURBANCES
Actual received signal points are distorted by one or more types
of line disturbances such as noise, phase or amplitude hits,
phase or amplitude jitter, harmonic distortion and drop-outs.
White noise produces a smearing of each signal constellation
pOint around its ideal location (see Figure 15A).
It is desirable to have a quantity whose magnitude is proportional to the time average of the error vector magnitude. The
error vector magnitude may be approximated by its squared
magnitude eliminating the computation of a square root:
Phase jitter produces periodic phase smearing with little or no
amplitude effect (see Figure 158).
Harmonic distortion produces a non-periodic amplitude smearing with little phase effect (see Figure 15C).
Amplitude jitter produces an effect similar to harmonic distortion, but in this case the disturbance is periodic.
Re (ERROR)2 + 1m (ERRORj2
An amplitude (or phase) hit is associated with an instantaneous
high error in the amplitude (or phase) signal component.
The squared magnitude may then be averaged by a digital filter
of transfer function (see Figure 17):
The degree of smearing in the eye pattern is proportional to the
severity of the particular disturbance. These dlsturbances may
occur in combination producing more complex smearing of the
eye pattern.
H(Z)..
1 _ "j3Z-1
(Eq.1)
(Eq.2)
The coefficients " and j3 may be computed by a Z-domain
approximation to an RC network of transfer function
(see Figure 18):
A point falling within the signal space delimited by boundaries
is decoded by the modem as if it were located at the ideal point
within that space. When a line disturbance causes the signal
point to cross a decision boundary, the received signal point is
incorrectly decoded.
H(s) =
5-95
+ST ,T=RC
(Eq.3)
Signal Processor-Based Modems
Application Note
..
:.~
.
..
:~
."
......
..
::~':..
~
;'
~
;:"-
'0:
.....:',
'.: ".::
-0::.: •• :::.
A. WHITE NOISE
B. PHASE JITTER
.... : .....
.;
'0.:"
C. HARMONIC DISTORTION
(NON-PERIODIC) AMPLITUDE
JITTER (PERIODIC)
Figure 15.
Typical Line Disturbances
5-96
Signal Processor-Based Modems
Application Note
Re(ERROR)2 + Im(ERROR)2
RESULTANT
ERROR VECTOR
ERROR
MAGNI-
EQM
INPUT
t - - - -......-OOUTPUT
IDEAL
POINT
Figure 17.
IMAGINARY
ERROR COMPONENT
1800
AVERAGE
ERROR
MAGNITUDE
00
R
0
:f@.(.t,~'
.
.'••.•
Vln
IDEAL
POINT
Figure 16.
270 0
0
Figure 18.
Error Vector Phase Error/EQM
+rfT
rfT
1 +rfT
(3 =
+ 7200r
1
1
+ 7200r
(Eq.4)
(Eq.5)
t
I
0
Vout
0
Equivalent Analog RC-Network
Bit Error Rate (BER) curves as a function of the signal-to-noise
ratio (SNR) are used to establish a criteria for determining the
acceptance of EQM values. Figure 20 is a typical BER curve
showing the meaning of a given EQM value in terms of BER
and SNA. From an EQM value, the host processor can determine an approximate BER value. If the BER is found to be
unacceptable, the host may cause the modem to fall-back to
a lower speed to improve BEA.
Re-writing the transfer function H(Z) (Equation 1) as a difference
equation:
Yin) = au(n) + (3y(n -1)
VV'v
The EQM value is the filtered squared magnitude of the error
vector. These values represent the probability of error and can
be used to implement a discrete Data Signal Quality Detector
circuit (circuit 110 of CCITT recommendation V.24 or circuit CG
of RS-232-C recommendation) by comparing the EQM value
against an experimentally obtained criteria (refer to Figures 19
and 20).
Substituting variables (first backward difference approximation) S = 1 - Z-lfT yields a and {3 (r = RC, T = sampling
period 1fT = 7200 Hz for R1212/R2424):
a=
Digital Energy Averaging Filter
(Eq.6)
It should be noted that the meaning of EQM varies with the type
of line disturbance present on the line and with the various configurations. A given magnitude of EQM in V.29/9600 does not
represent the same BER as in V.29/4800. The former configuration has 16 signal points that are more closely spaced than the
four signal pOints in the latter, resulting in a greater probability
of error for a given level of noise or jitter. Also, the type of disturbance has a significant bearing on the EQM value. For example,
white noise produces an evenly distributed smearing of the eye
pattern with about equal magnitude and phase error while phase
jitter produces phase error with little error in magnitude.
letting the input sequence u(n) = Re (ERROR (n»)2 + 1m
(ERROR (n»)2 and the output Yin) = EQM(n) we obtain:
EQM(n) = a [Re(ERROR(n»)2 + Im(ERROR(n»)2] + i3EQM(n-1)
(Eq.7)
where: EQM(n)
EQM(n-1)
= Current EQM value.
= EQM value delayed by one sample
period.
Re (ERROR (n)l = Real component of the error vector.
Re (ERROR (n) = Imaginary component of the error
vector.
Recalling that EQM is an average of the squared magnitude of
the error vector, it can be seen that the correspondence of EQM
to SNR (and hence BER) is dependent upon the signal structure of the modulation being used and the type of line disturbance present.
If we choose r = 0.1 seconds and 1fT = 7200 Hz then, a =
0.001386962 and i3 = 0.998613037. Note that a + i3 = 1 and
a «i3 < 1.
5-97
Signal Processor-Based Modems
Application Note
37
EQM VS. SNR
UNCONDITIONED 3002 LINE
T EQUALIZER
- 20 DBM SIGNAL LEVEL
3 KHZ FLAT WEIGHTING
32
20
28
23
><
~
1E
~
aUJ
19
14
OF
0/.
05
0
0
5
10
50
15
55
60
65
SNR (dB)
Figure 19.
Typical Eye-Quality Versus Signal-To-Noise Ratio for V.29/9600 (R96FAX)
5-98
70
Application Note
Signal Processor-Based Modems
4800 BPS V.27 TER
2400 BPS V.27 TER
'"
9600 B,\ V.29
10-3~------------~----~r-----~---?------~~;-----------~~----------~
10-'~------------+---------~~~------~----~~--~------~----~~----~
w
i
I
l-
ii
10-6~------------+-------------~--------~~~--~~~~--~----------f--i
10-6~0-------------A5------------~10~~~------~1~5------~--~~~~~~--~~25
SIGNAL TO NOISE RATIO (dB)
• EQM VALUE
UNCONDITIONED 3002 LINE, T-EQUALIZER, -20 dBm SIGNAL LEVEL, 3 kHz FLAT WEIGHTING
Figure 20.
Typical Bit Error Rate Versus SNR and EQM
SCALING OF SP SIGNALS (R48DP, R96DP,
R96FT, AND R96FAX)
AGe Gain in dB = 50 - AGe Gain Word x 0 097 dB
(100)8
.
The following list of formulas can be used to obtain diagnostic
data in engineering units. Typical values or ranges for the data
are also given.
2. Average Power Word (16 blts)-Node 4
Typical value: 42118 = 0889'6 (corresponding to 0 dBm)
CONVERSION FORMULAS, RANGES AND
TYPICAL VAWES FOR R48DP, R96DP AND
R96FAX MODEMS
1. AGe Gain Word (16 bits unsigned)-Node 5
Range:
OFOO'6 - 7FFF'6 for LRTH
0 (- 43 dBm Threshold)
0640'6 - 7FFF'6 for LRTH = 1 (- 47 dBm Threshold)
Post-AGe Average
Power in dBm
= 10 Log (Average Power Word) dBm
Pre-AGe Average
Power in dBm
(Post AGe Avg. Power in dBm
= - AGe gain in dB) dBm
(889),6
3. AID Sample Word (16 bits two's complement)-Node 1
=
(Refer to Figure 21 for the location of V1NT and VE'Y:f signals)
5-99
Signal Processor-Based Modems
Application Note
4. Rotation Angle Word (16 bits two's complement)Node 12
VEXT
Range: -180 0
VINT SIGNAL
IA DEVICE I---~ PROCESSOR
CHANNEL
+ 180 0
-
Rotation Angle in degrees = Rot. Angle Word x 180 0
216
5. Frequency Correction Word (16 bits two's complement)Node 13 (Deviation from carrier in Hz)
AGC WORD
Range: FC01 1•
Figure 21.
040016 (±37.5Hz)
-
Freq. Correction in Hz = (Freg. Correction word)
External and Internal Voltages
216
x (Baud Rate in Hz) Hz
v
6. Error Vector Real (16 bits two's complement) and
Imaginary (16 bits two's complement) Words
_ Signed, two's complement HI-bit AID Word
(100).
INT -
x ...LVolts
(Refer to Table 3.)
256
VEXT = VINT
.;.
LOG~Ol
[AGC
,;;;n
7. Scaled Signal Points (16 bits two's complement)
(dB)]
(V.29 to V.27)
(Refer to Figure 22 and Table 4.)
Table 3.
Error Vector Maximum Values
Magnitude
Configuration
Bit Rate
CBPS)
Real Error
Imag. Error
VRe2 + 1m2
V.29
V.29
V.29
V.27
V.27
9600
7200
4800
4600
2400
~74LS30~
74LS04 r--
.01,F
C11·C16
2
1
~
_ ... _-- _._-
470
R4
1
GND+SV+12V-12V_
4
1 74LSOO
5 U6)J
6
11
12
,...
+SV
C2
C3
GND
GND BOl C1
GND ~ .047 .047 ~ ~
GND ~ C4 C5
+12V
+12V 89
-12V
-12V B7
2
3
4~30
~ 4 AEN
F
2
U10
11A
6C
0
3
3
2 U9pL
!:
n
R1212
7404
6
U10
~
!II
DTR
TXD
RXD
RLSO
DSR
CTS
.~.
o
XTAL1 16
r-;fi
16
18
CD
~D7
~'0
4
2
o
-#. D3
CS1
CS2
MR
28
AO
27
A1
26 A2
DOSTR
DISTR
rL -
z
D1
~D4
INS8250
U4
ADDRESS:
3F8·3FF
----#
3S
AO
A1
A2
~
~DO
~D2
1
..,........
a
o·
30 INTRPT
10C
Q)
i:
"
c:
S'
::D
....a.
N
....a.
N
::D
TLKlDATA
ORG/ANSW
9C
Q)
oQ)
CS1
N
01::0
N
01::0
i:
o
Q.
CSO
CD
3
-a~
CD
n
CD
_----
mI
L_
Application Note
8088 MPU to R1212/R2424 Modem Interface
8088 AUTO DIALER ASSEMBLY LISTING
TITLE
8088 AUTO DIALER
CD I AL 1. ASM)
COMMENT*
Rockwell Appllcati ons Lab 5/15/84
ThIS 1$ wrItten as an example of an auto-dIaler 1n B088
Assembly Language.
I t was wrItten uSIng the M1cosoft
Mac:ro Assembler whl.ch runs under the IBM DIsk Operatlng
System.
The hardware used places the Interface memory Bank a
and Bank 1 at locations 30Q-30F and 310-31F respectlvely.
ThIS is the space allocated for- the Pr-ototype Card 1n the
IBM I/O Address Map.
;
,Macro pseudo-op for use 1n sett1ng req bits 1n the 1nterface memory
; The address and b1 t to be set/reset i 5 sent to the Macro.
; The Macro then gets the appropr1ate byte from the R1224.
; Th1 s byte 1 S ORed W1 th the bi t to be set to change onl y that
;b1t.
The byte 15 then sent back to the R1224.
;
SET
MACRO
MOV
IN
OR
OUT
ENDM
0000
0000
STACK
0100 [
ADDR,SIT
DX,ADDR
AL,DX
AL,BIT
DX,AL
SEGMENT STACK
DB
256
DU?
0100
STACK
ENDS
0000
0000
DATA
BUF
SEGMENT
DB
20,21 DUP(Q)
MBG
DB
14 15 t
(?)
;Set up a buffer for the phone number
00
0016
20
20
20
52
002e
20 20 44 49 41 4C
49 4E 47 20 24 20
45
50
4E
3A
4E
48
55
24
54 45 52
4F 4E 45
4D 42 45
20
MESl
DB
0038
DATA
ENDS
0000
CODE
START
• ENTER PHONE NUMBER =$:
DIALING :$
•
•
;
0000
SEGMENT
PROC
FAR
;
; Standard Program Prologue
•
0000
0001
0004
0005
0008
aOOA
0000
aOCE
IE
B8 0000
50
BB ---- R
8E DB
E8 aODE R
ASSUME
PUSH
MOV
PUSH
MOV
MOV
CB
START
CALL
RET
ENDP
cs: CODE,DS: DATA,SS: STACK
DS
AX,O
AX
BX, DATA ; Get data segment base address
DS,BX
MAIN
5-116
Application Note
8088 MPU to R1212/R2424 Modem Interface
8088 AUTO DIALER ASSEMBLY LISTING (Continued)
,
,
DOOE
MAIN
PRQC NEAR
;D1al set-up
SET
MOV
IN
OR
OUT
SET
MOV
IN
OR
OUT
31DH,OOH
OX ,31DH
AL,DX
BA 0300
EC
OC 80
EE
SET
MOV
IN
OR
OUT
30DH,80H
DX,30DH
BA 0310
EC
OC BO
EE
SET
MOV
IN
OR
OUT
31DH,aOH
DX,31DH
SET
MOV
IN
OR
OUT
31BH,02H
DX,31BH
SET
MOV
IN
OR
OUT
30DH,40H
DX,30DH
AL,DX
AL,40H
DX,AL
;Set eRG bit, r.ce:Lver
SET
MOV
IN
OR
OUT
31DH .. 40H
DX,31DH
;Set eRG bit, tr.n.mi t.ter
0011
0012
0014
BA 0310
EC
OC 00
EE
0015
0018
0019
0018
SA 031E
EC
OC 08
EE
OOIC
OOIF
0020
0022
0023
aOOE
0026
0027
0029
002A
0020
002E
0030
SA 0318
EC
OC 02
EE
0035
0037
BA 0300
EC
OC 40
EE
0038
0038
003C
003E
SA 0310
EC
OC 40
EE
003F
0043
83 FF
FE CB
80 FB 00
0046
0031
0034
+
+
+
+
+
+
+
+
,
; Assure that DTR is a 0
AL,OOH
DX,AL
31EH,OBH
DX,31EH
AL,DX
;Set. NEWC
AL,OBH
DX,AL
;Set the BUS bIt, receIver
AL,DX
AL,aOH
DX,AL
;Set the BUS bIt, transml ttltr
AL,DX
AL,80H
DX,AL
;Set. DTMF fOr ton. dialinljl
AL,DX
AL,02H
DX,AL
AL,DX
AL,40H
DX,AL
;Walt at least :50 m.ac between reset. and set. of DTR
BL,OFFH
BL
BL,OOH
75 F9
MOV
DEC
CMP
JNZ
0048
0048
004C
004E
SA 031D
EC
OC 08
EE
31DH,OBH
DX,31DH
AL,DX
+
+
SET
MOV
IN
OR
OUT
BA 030E
EC
OC 08
EE
+
+
SET
MOV
IN
OR
OUT
SET
MOV
IN
OR
OUT
30EH,OBH
004F
0052
0053
0041
0055
0056
0059
OOSA
cose
SA 031E
EC
OC OB
EE
TIMEt;
,
TIMEt
;Set DTR
AL,OBH
DX,AL
;Set NEWe, Receiver
DX,30EH
AL,DX
AL,08H
DX,AL
31EH,08H
DX,31EH
,Set NEWC b1t, Tran.mi tter
AL,DX
AL,OBH
DX,AL
,
; Check that we are off-hock a.nd ready to dIal
005D
0060
0061
0063
OOb5
BA
EC
24
3C
7S
0318
80
80
Fb
WAIT:
MOV
IN
AND
CMP
JNZ
DX,318H
AL,DX
AL,80H
AL,aOH
WAIT
5-117
;Check to s • • i f OLD is sat
; I f not, .....I t for i t
Application Note
8088 MPU to R1212/R2424 Modem Interface
8088 AUTO DIALER ASSEMBLY LISTING (Continued)
;Wait for dlal-t.one on the line
MOV
DX,30BH
006B
SA 0308
EC
24 80
IN
AND
0060
006F
3C 80
75 EC
CMP
JNZ
AL,DX
AL,80H
AL,BOH
WAIT
0067
OObA
MOV
AH,9
MOV
INT
DX,OFFSET MSG
21H
0073
8409
SA 0016 R
0076
CD 21
0078
840A
BA 0000 R
CD 21
MOV
MOV
AH,OAH
OX , OFFSET BUF
INT
21H
820A
B402
CD 21
MOV
MOV
DL,OAH
AH,02
INT
21H
8409
SA 002e R
CD 21
MOV
MOV
OOSA
AH,9
OX ,OFFSET MESl
21H
ooat
BE 0000
0071
;Print prompt for phone" input
Raad the number and dl spl ay it.
007A
007D
007F
0081
0083
0085
0087
INT
; Buffered Keyboard Input
iLine feed
;Oisplay function
;005 call
;Print DIALING message
; Loop and redlsplay telephone number as it
QOBF
89 0000
0092
0096
SA OE 0001 R
SA 94 0002 R
00914
52
0098
SA 031E
EC
MOV
MOV
81,0
MOV
DX,31EH
AL,DX
AL,01H
AL,01H
15
dlaled
CX,O
MOV
CL,BUF+1
;Get number of diglts read
PAD:
MOV
DL,BUF[SI+2]
;DL now contalns the dIal dlgit
PUSH
OX
; Preserve the dIal digl t on the st.ack
;
;Check to sae that the dIal dIgIt reglst.er lS empty
,
009E
009F
aOAI
FULL1:
IN
24 01
AND
CMP
JNZ
3C 01
OOA3
75 F6
OOAS
5A
FULL1
;
;Get th&! dial dlgit. off the stack
,
,
POP
DX
,
;Chlitck t.o see if 1t.·S a carrlage ret.urn
OOA6
OOA9
CMP
80 FA OD
J1
74 10
DL,ODH
DONE
; If It is, and the dialing sequence
;
;Feedback for dialIng
OOA8
OOAD
8402
CD 21
MOV
INT
AH,2
21H
;Prlnt. the dlgit.s as t.hey are dIaled
;
;Send the dial digIt. to the R1224
OOAF
0082
OOB4
OOB7
00B8
0089
80
SA
SA
EE
4&
E2
E2 OF
C2
0310
AND
MOV
MOV
DL,OFH
AL,DL
OUT
DX,AL
91
INC
LOOP
DB
DX,310H
;Dlal Dlgit must be in AL to be sent.
; to the 110 port
;Send i t
;Polnt to t.he ne)(t digit
PAD
;Go here to end tha dlal sequence by putting FF
; int.o t.he dl al dl 91 t regi star
;
; ASSiure DDRE empty agaln
;
008B
OOBE
OOBF
EC
IN
24 01
OOCI
3C 01
AL,OlH
OOC3
75 Fb
AND
CMP
JNZ
oocs
oocs
SA 0310
BO FF
EE
MOV
DX,310H
MOV
OUT
AL,OFFH
OOCA
ooca
oote
ooce
SA 03tE
DONE:
C3
MAIN
CODE
END
MOV
DX,31EH
AL,DX
AL,01H
DONE
OX ,AL
RET
ENDP
ENDS
START
5-118
Application Note
'1'
High Speed Modems
Filter Characteristics
Rockwell
INTRODUCTION
The R96F, R96DP, R48DP, and R96FT modems include
integrated analog devices using switched capacitor filters to perform the functions of receiver input bandpass filtering, transmitter
output lowpass filtering, and compromise equalization. Differences in performance result from half-duplex (HDX) or fullduplex (FDX) versions of the integrated analog device.
The following tables illustrate the change in filter response
caused by enabling each of the compromise equalizers
independently.
A. Receiver
1. Link Amplitude Equalizer HDX and FDX.
R96 FILTERS
The following tables illustrate the response of the receiver input
bandpass and transmitter output low pass filters without
compromise equalization.
US Long
Japanese 3 Link
1000
1400
2000
2400
2800
3000
-0.27
-0.16
+0.33
+1.54
+5.98
+8.65
-0.13
-0.08
+0.16
+0.73
+2.61
+3.43
A. Receiver Input Bandpass Filter
Parameter
Value
Test signal range
Passband
Passband ripple
Loss below 60 Hz
Loss above 6000 Hz
Passband 9ain
Delay distortion 400 Hz1800 Hz
Delay distortion 1800 Hz3000 Hz
o d8m to
-45 d8m
400 Hz - 3000 Hz
0.5 dB max.
40 dB min.
40 dB min.
0.0 dB ± 1.0 dB
2. Link Delay Equalizer FOX Only.
Frequency
Hz
Less than 150 usee
B. Transmitter Output Lowpass Filter
Parameter
Value
o dBm to
Document No. 29220N58
Delay Microseconds Relative to 1700 Hz
800
1200
1600
1700
2000
2400
2800
Less than 1000 usec
Test Signal
Passband
Passband Gain
Passband ripple
Loss at 3600 Hz
Loss at 7800 Hz
Loss at 11400 Hz
Loss at 12000 Hz
Loss above 17400 Hz
Delay distortion 400 - 3000 Hz
Gain dB Relative to 1700 Hz
Frequency
Hz
US Long
Japanese 3 Link
-498.1
-188.3
- 15.1
+ 0.0
- 39.8
-423.1
-672.4
-653.1
-398.5
- 30.0
+ 0.0
+ 11.7
-117.1
-546.3
3. Cable amplitude HDX and FDX.
-16 dBm
400 - 3000 Hz
-1 dB ±1 dB
0.5 dB max.
5.5 dB min.
32 dB min.
33.5 dB min.
41 dB min.
45 dB min.
Less than 300 usee
a. CODE 1
"
Frequency
Hz
700
1500
2000
3000
Application Note
5-119
Gain dB Relative to 1700 Hz
HOX
FOX
-0.99
-0.20
+0.15
+1.43
-0.94
-0.24
+0.31
+1.49
Order No. 658
July 1984
Application Note
High Speed Modems
2. Cable Amplitude HDX and FOX.
b. CODE 2
Frequency
Hz
a. CODE 1
Gain dB Relative to 1700 Hz
700
1500
2000
3000
HOX
FOX
-2.39
-0.65
+0.87
+3.06
-2.67
-0.74
+ 1.02
+3.17
Frequency
Hz
Gain dB Relative
to 1700 Hz
700
1500
2000
3000
-0.99
-0.20
+0.15
+1.43
Frequency
Hz
Gain dB Relative
to 1700 Hz
700
1500
2000
3000
-2.39
-0.65
+0.87
+3.06
Frequency
Hz
Gain dB Relative
to 1700 Hz
700
1500
2000
3000
-3.93
-1.22
+1.90
+4.58
c. CODE 3
Frequency
Hz
Gain dB Relative to 1700 Hz
700
1500
2000
3000
HOX
FOX
-3.93
-1.22
+1.90
+4.58
-3.98
-1.20
+1.81
+4.38
b. CODE 2
B. Transmitter
1. Link Amplitude Equalizer HDX Only.
Gain dB Relative to 1700 Hz
Frequency
Hz
US Long
Japanese 3 Link
1000
1400
2000
2400
2800
3000
-0.27
-0.16
+0.33
+1.54
+5.98
+8.65
-0.13
-0.08
+0.16
+0.73
+2.61
+3.43
c. CODE 3
5-120
Application Note
'1'
R96F Modem
Tone Detector Filter Tuning
Rockwell
INTRODUCTION
The output of the energy averager IS fed to a threshold comparator which sets, or resets, the appropriate bit (Fl, F2 and
F3) in the signal processor (SP) scratch pad memory if the energy
output is eq ual to or greater than 1/8, or less than 1/8,
respectively.
The Rockwell R96F modem includes three independent tone
detectors (Fl, F2 and F3). These tone detectors are operational
when the modem is configured for V.21 FSK, and are centered,
upon power-up, to 2100 Hz (Fl), 1100 Hz (F2), and 462 Hz (F3).
This application note presents a method of tuning these
detectors to any desired frequency in the 300 Hz - 3 kHz band.
Filters 1 and 2 have a typical frequency response as shown in
Figure 2. When cascaded, they form a bandpass filter with a
narrow bandwidth as shown in Figure 3.
COMPUTATION OF TONE
DETECTOR COEFFICIENTS
Each tone detector consists of two second-order filters in
cascade, an energy averaging filter, and a threshold comparator.
A diagram of the tone detector is shown in Figure 1.
Given the transfer functions H,(Z) and H2(Z), an analy1ical
method is required to compute their coefficients for any desired
frequency in the 300 Hz - 3 kHz band. First, consider H,(Z).
This transfer function can be rewritten as:
Filter 1 has a transfer function:
H,(Z)
=
2a
1 _ 2/3,Z-' - 2/32Z -2'
(Eq. 1)
(Eq. 4)
Filter 2 has a transfer function:
H2(Z)
=
which has a conjugate pair of poles:
2a'
1 - 2/3;Z-' - 2/32Z-2
(Eq.2)
P,
The energy averaging filter has a transfer function:
a"
H3(Z) = 1 _ /3" Z-'
a(1)
2
=
/3, + j
V/3~ + 2/32
and
(Eq.3)
a'(4)
a"(7)
2
}-----~~OUTPUT
TO THRESHOLD
COMPARATOR
Fn = 1 IF OUTPUT." 118
Fn = 0 IF OUTPUT
1ST BI-QUAD FILTER
2ND
BI-QUAD FILTER
< 1/8
ENERGY AVERAGING
NOTE: NUMBERS IN ( ) REFER TO NODE NUMBERS IN TABLE 2.
Figure 1.
Document No. 29220N68
R96F Tone Detector Diagram
Application Note
5-121
Order No. 668
Rev_ 1, January 1987
Application Note
R96F Modem Tone Detector Filter Tuning
These poles lie on a circle of radius 0.994030884 on the Z-plane.
The radius of the tone detector circle was chosen so that each
filter has a high Q without being unstable (i.e., poles must lie
inside the unit circle for stability). Figure 4 shows a Z-plane
pole-zero diagram for an arbitrary conjugate pole pair on the tone
detector circle. The angle 8 = 360 0 x lolls, where 10 is the
desired center frequency and Is is the sampling rate
(fs = 9600 Hz). The following equations are derived from the
angle and magnitude of the position vector pointing to a pole
pair located at the desired angle:
cos-'
(f!l)
r
= 8 = 360
0
xlQ
Is
V'-It""~-+-'(~--1t""~---2""1t"""'2) = r = 0.994030884
solving for
It,
and
(104/319)/0 - 78.62
0/=01.'=
= r cos (360 0
~~)
:5
10
:5
1100 Hz
(Eq. 12a)
(441275)/0 + 104
1100
32767
:5
10
:5
1650 Hz
(Eq. 12b)
(4/45)/0 + 221
1650
32767
(Eq.5)
:5
10
:5
3000 Hz
(Eq.12c)
Energy Averaging Filter
(Eq.6)
The coefficients of the energy averaging filter are determined
by a Z-domain approximation to an RC circuit of transfer function:
H(S) = 111 + S7.
1t2:
It,
300
32767
ex"
(Eq.7)
+ 96007
(Eq.8)
1
(Eq.13)
(Eq.14)
+ 96007
In deriving these equations, only H,(Z) was considered.
However, the tone detector consists of two identical filters in
cascade. Referring to Figure 5, shifting filter 1 and filter 2 above
and below the desired center frequency, a response with the
desired bandwidth is achieved. Furthermore, since ex controls
the amplitude response, one may set ex
ex' to uniformly raise
or lower the overall cascade response.
Upon power-up, ex" and 13" are set for 7 = 0.1 seconds. Unless
different tone detector response times are required, these
coefficients need not be changed.
=
Table 1 contains the computed values of the filter coefficients,
including those of default frequencies 462 Hz, 1100 Hz, and
2100 Hz. The value 32767 (Hex 7FFF) is full scale in the SP's
machine units (i.e., 32767 = unity). Coefficients may range from
- 1 to + 1 (or FFFF to 7FFF in machine units).
From Equation 8, we see that 1t2 = 1t'2 = - r2/2 =
- 0.494048699. Rewriting Equation 7 in terms of the offsets IA
and fA we obtain:
It,
r cos [360 0 Vo -
IAlllsI
(Eq.9)
It;
r cos [360 0 Vo +
IA)llsI
(Eq.10)
WRITING NEW COEFFICIENTS INTO THE
SIGNAL PROCESSOR (SP) RAM
The RAM ACCESS B register (1 :F) allows the host processor
to specify an access code for RAM data registers. The access
code specifies the RAM location being written. Table 2 contains
the RAM access codes for all filter coefficients.
The frequency offset is approximately 72% of B/2 (half the
bandwidth):
IA
== 0.72
(~)
The proper procedure for writing new coefficients into the SP
RAM is as follows:
(Eq. 11)
1. Store the desired access code into register 1:F.
The value of IA should be equal to IA' However, IA may be
chosen 1% smaller than fA to compensate for the fact that the
overall cascade response is not perfectly symmetrical (see
Figure 5).
2. Wait for bit OA 1 (1 :E:O) to be a 1.
3. Set bit RAMW (1 :0:0) to a 1.
4. Write the two halves of the 16-bit coefficient into registers 1: 1
and 1:0. (Register 1:1 is the MSB.)
The values for the coefficients ex and ex' that set IH(fo)1 = 0 dB
in equations 1 and 2 were measured and plotted versus center
frequency 10 as shown in Figure 6. Three equations corresponding to three linear approximations result:
Writing to Register 1:0 resets OA 1 (1 :E:O) to a 0 and starts the
write cycle, which ends by OA1 returning to a 1. Bit RAMW
(1 :0:0) must remain set until the end of the cycle.
5-122
:j
Application Note
R96F Modem Tone Detector Filter Tuning
2000
FREQUENCY (Hz)
Figure 2.
500
Typical Single Filter Response
2000
FREQUENCY (Hz)
Figure 3.
Typical Cascade Filter Response
5-123
3000
3500
R96F Modem Tone Detector Filter Tuning
Application Note
ImZ
UNIT CIRCLE r
180 0
=1
90 0
360 0
-1
4800 Hz
9600 Hz
-/1
270 0 7200 Hz
Figure 4.
Z-Plane Pole-Zero Diagram
5-124
Re Z
Application Note
R96F Modem Tone Detector Filter Tuning
I
1
,
II '"
V'
I
/1
I
/
/
/
., " '"
fo - fA
fo +
fo
fA
FREOUENCY (Hz)
Figure 5. Graphical Representation of Bandwidth (B) and Offset Frequencies (fA and fA)
EQ.12a,,/
500
/
450
/
/
400
/
_/-......:
350
...Ie
...
.
Ie
<
:z:
~
<
300
-
.....-
","'"
-- ---L.
",
"'" "'"
"'"
"'"
"'"
EQ. 12b""\. ""':EQ
)II'
"'"
"'
"
"'"
....-: I
I
I
I
I
I
I
I
I
Figure 6.
III
versus Center Frequency for IH(fo)1 = OdB
5-125
"'"
.12c
R96F Modem Tone Detector Filter Tuning
Application Note
Table 1. Calculated Coefficient Values
CoeffIcient Velue
CoeffIcient
Name
Frequency
Detected
2100 Hz ±25 Hz
Hex
Decimal
0198
1A4A
175A
COC5
408132767
6730132767
5976132767
-16187132767
0180
2E37
2869
COC4
384132767
11831132767
11113/32767
- 16188/32767
0170
3048
3M6
COC4
366132767
15686132767
15014/32767
-16186132767
0116
6OB2
5E9C
COC4
280132767
24754/32767
24220132767
-16186132767
a == a'
0048
~1
79F3
7974
C083
72/32767
31219132767
31092/32767
- 16253132767
a'
at: -
~1
~;
/"... 16 Hz
~2 - ~2
1850 Hz ±24 Hz
cl
at: -
~1
~;
fA" 18 Hz
~2 - ~2
at: = a'
1850 Hz ±23 Hz
~1
~;
fA !l! 18 Hz
~2 = ~2
1100 Hz ±3O Hz
a == a'
~1
~;
fA!l! 19 Hz
~2 - ~2
482 Hz ±14 Hz
~;
fA!l! 10 Hz
~2 - ~2
Table 2. Filter Coefficients Access Codes
Acce88 Code (Hex)
Node
No. (n)
Name
F1
F2
F3
1
IX
2E
34
SA
2
~1
2F
35
38
3
~2
30
36
3C
4
IX'
28
31
37
5
~;
2C
32
36
6
~2
20
33
39
7
IX"
87
B9
BB
8
~"
B8
BA
BC
5·126
R96F
Application Note
'1'
R96F Modem
Recommended Receive Sequence for
Group 2 Facsimile
Rockwell
INTRODUCTION
The R96F includes a transmit and receive configuration that
is compatible with the transmission scheme of Group 2 facsimile
equipment. In order to achieve the best results with Group 2
reception, the following procedure is recommended. The step
numbers are keyed to points in Figure 1. Refer to Data Sheet
MD06 and Application Note Order No. 654 for details on how
to configure the modem and write modem data to chip one.
LCS
1100 Hz
IPHASING ITXCFR
IMESSAGE II
TONE
t
Figure 1.
t
t
t t t
2
3
4
5 6
Group 2 Facsimile Sequence
METHOD
1. Enter Group 2 configuration and wait 5 milliseconds to complete initialization. Then:
a. Write hex 0038 using access code C2. This action sets
the Group 2 phase-locked-loop for a frequency correction
of 9 Hz, causing the phase term to drift rapidly to overcome any tendency to slow phase recovery.
b. Write hex 4000 using access code F1 and hex 7FFF using
access code 71. This action allows the Group 2 phaselocked-loop to accept the greatest number of samples for
carrier recovery during phasing.
c. Write hex 2000 using access code AA. This action sets
the AGC slew rate for very fast acquisition.
d. Select fast AGC state by setting control bit G2FGC (1 :C:O)
to a one.
2. After phasing is detected, wait approximately 2 seconds for
the AGC circuit to settle. Then:
a. Write hex 0000 using access code AA. This action stops
AGC tracking in order to preserve the present AGC setting.
b. Select slow AGC state by resetting control bit G2FGC
(1 :C:O) to a zero. This action changes the Group 2 phaselocked-loop characteristics to match reduced AGC
response.
c. Read and save the 16-bit value from registers 1:3 and 1:2
using access code C2. This value represents the
frequency error term from the Group 2 phase-locked-loop.
d. Verify that phasing signal is still being received. This action
guarantees that AGC value was frozen during phasing
signal.
Document No. 29220N55
e. If step d above determines that phasing signal is present,
allow transmission of CFR. If phasing signal is not present,
suppress CFR.
3. Exit Group 2 configuration.
4. At completion of CFR transmission, re-enter Group 2 configuration and wait 5 milliseconds to complete initialization.
Then:
a. Repeat step 1.b.
b. Repeat step 2.a.
c. Add hex 0038 to the value saved in step 2.c above and
write the sum using access code C2. This action forces
a 9 Hz error as in step 1.a.
5. Wait for start of Group 2 message transmission. Then:
a. Write hex 0400 using access code AA. This action restores
the AGC slew rate to the default value.
b. After 2 lines, write the value saved in step 2.c using access
code C2. This action removes the 9 Hz forced frequency
error without waiting for the phase-locked-loop to complete
the correction. This step is optional as the correction will
eventually be completed, but, depending on the percentage of white in the document being sent, the correction may take from 4 to 16 lines (100 ms of white required).
6. After approximately 6 to 10 seconds of message reception,
perform either step a or step b below:
a. Write hex 6100 using access code F1 and hex 0600 using
access code 71. This action places narrow limits on the
received signal used for carrier recovery during message
reception and reduces the chance of errors being caused
by repeated patterns in the message.
b. Synchronize the modem's Group 2 phase-locked-loop to
the facsimile machine's blanking signal as follows:
1. Freeze the phase-locked-loop during data by:
a. Writing hex 7FFF using access code F1
b. Writing hex 0000 using access code 71
2. Enable the phase-locked-loop during the white margins
by:
a. Writing hex 4000 using access code F1
b. Writing hex 7FFF using access code 71
c. The sequence of writing in step 6.b is important and must
be performed as described. Option 6.b requires more
action by the host procesor, but it eliminates the possibility
of data patterns affecting carrier recovery.
Application Note
5-127
Order No. 655
Rev. 3, January 1987
Application Note
R96F Modem
o
o
~
4
Il.
UJ
I1/1
~
I
II
..
~
~
....,
~
~
~
~
g
..,o
V"
g
'"
'fI'fI 3000 SS300'fl DNlsn N3l.LII:IM 3nl'flJl X3H
5·128
f
III
Q
0
0
~
.S!
::i
III
Q
an
an
I
J
./
l/"
I
::i
J
a:
!
IX
~
GI
0
iii
()
0
II.
Cl
«
UJ
N
:::;
iii
«
I-
1/1
0
I1/1
Q
Z
0
()
UJ
1/1
CI
c(
N
~
::I
g)
u::
Application Note
R96F Modem
PARAMETER SCALING
the limit set by F2, PLL updating is suspended. The default
value of 5000 corresponds to a limit of ± 67.5 degrees. A zero
in F2 causes the PLL to update for any phase error. By setting F2 to zero, it may be unnecessary to force a frequency
offset in the receive sequence. For systems using step 6.a
in the receive sequence, reception of messages containing
a large amount of black may be improved by setting F2 to
zero. F2 scaling is:
1. Access code C2 represents frequency error; i.e., the deviation of received carrier from 2100 Hz. LSB = 0.167 Hz.;
Range = ± 140 Hz.
2. Access code FO represents the Group 2 phase-locked-loop
slew rate for the first order term. The number is directly proportional to slew rate. The range of stable operating values
is 0010 to 7000 in hexidecimal.
Phase limit = 180 0
3. Access code M represents the AGC slew rate.
Range = 0000 to 7FFF in hexidecimal.
Scaling: see Figure 2.
-
[(F~;~~e) x
180 0 ]
Once phasing is acquired, the limits may be narrowed to
improve immunity to phase hits, etc.
BLACK/WHITE THRESHOLD
4. Access codes F1 and 71 represent limits on acceptable zero
crossings for use by the carrier recovery loop. The carrier
recovery loop uses several nonlinear controls in attempting
to lock the zero crossings of the local carrier to those of the
transmitter. Since Group 2 facsimile uses VSB transmission,
it is necessary to either reconstruct the upper sideband or
exclude those zero crossings that represent frequencies other
than 2100 Hz. The R96F excludes unwanted zero crossings by testing the effective slope of the waveform as it
crosses zero. In Figure 3, points A and B represent samples
taken about a zero crossing over sample period T, where
T = 1/10,368 seconds.
The magnitude of IAI + IBI is directly proportional to the
slope of line segment AB and is therefore an indicator of frequency. If H represents the value stored at F1 and L
represents the value at 71, then 1 - [IAI + IBII + H must
be less than positive full scale or the frequency is excluded
for being too low. Also 1 - [lAI + IBII + H + L must be
greater than positive full scale or the frequency is excluded
for being too high.
The average value for 1 - [IA I + I B II with an all white
transmission and back-to-back connection is hex 19A1
±0543.
The R96F receives a Group 2 baseband signal that contains
density (gray scale) information in the amplitude modulation. In
order for this information to be used on a Group 3 facsimile
machine the R96F converts the gray scale to black/white baseband form. The threshold at which the black/white decision is
made determines the density of the received page.
Access code 2A represents the Group 2 blacklwhite threshold.
This location defaults to hex 7800 at POR time. The number may
be increased or decreased by the host to achieve a page
weighted more toward white or toward black, respectively.
A
o----~----~~-------B
T
5. An access code added to baud rate chip 5301-20 allows host
control of the limits placed on phase error correction. This
access code is F2 in chip 1. When the phase error exceeds
Figure 3.
5-129
Samples of Zero Crossing
Application Note
'1'
DTMF Dialing Using the R24MFX, R24BKJ,
R48M FX, or R48PCJ Modem
Rockwell
INTRODUCTION
The R24MFX, R24BKJ, R4SMFX, and R4SPCJ modems
include tunable oscillators that can be used to perform
dual-tone multi-frequency (DTMF) dialing. The frequency
and amplitude of each oscillator output is under host control. A programmable tone detector can also be used in
call establishment to recognize an answer tone.
This application note describes the method of oscillator
and filter tuning by the host processor and provides an
example of an auto-dialer routine that may be programmed into the host.
power and -1 dBm of steady state low frequency power in
order to meet all of the listed conditions.
The required duration of the DTMF pulse is 50 ms minimum. By experience, a pulse duration of approximately
95 ms is more reliable. The required interval between
DTMF pulses is 45 ms minimum and 3 seconds maximum.
Again by experience, an interdigit delay of approximately
70 ms is preferred.
The remaining requirements of RS·496, relative to DTMF
dialing, are not influenced by the host processor. These
requirements are all met by the modem's oscillators.
DTMF REQUIREMENTS
SETTING OSCILLATOR PARAMETERS
EIA Standard RS-496, paragraph 4.3.2, specifies require·
ments that ensure proper DTMF signaling through the
public switched telephone network (PSTN). These tones
consist of two sinusoidal signals, one from a high group
of three frequencies and one from a low group of four frequencies, that represent each of the standard pushbutton
telephone characters shown in Table 1.
The oscillator frequency and output power are set by the
host computer using the microprocessor bus and diagnostic data routine. For a description of the microprocessor
bus and other Interface considerations, refer to the
R24/4SMEB modem evaluation board data sheet and the
relevant modem data sheet listed in Table 2.
Table 1.
Table 2. Data Sheet Order Numbers
Title
Order Number
DTM F Signals
~
1209 Hz
697 Hz
1
2
3
770 Hz
4
5
6
652 Hz
.
8
9
0
#
requency
Low
Frequency
941 Hz
7
1336 Hz
R24/48MEB Data Sheet
R24MFX Data Sheet
R24BKJ Data Sheet
R48MFX Data Sheet
R48PCJ Data Sheet
1417 Hz
MD22
MD17
MD20
MD19
MD21
When setting the frequency of tone 1, the host must write
a 16-bit hexadecimal number into RAM using RAMA code
SE. When setting the frequency of tone 2, a 16-bit hexadecimal number must be written into RAM using RAMA
code SF. The power levels of tone 1 and tone 2 are set by
writing 16·bit hexadecimal numbers into RAM using
RAMA codes 44 and 45, respectively. The hexadecimal
numbers written into these RAM locations are scaled as
follows:
Signal power is defined for the combined tones as well as
for the individual tones. Both maximum and minimum
power requirements are functions of loop current. By com·
bining the various requirements of RS·496, compromise
power levels can be determined that meet the power specification for all U.S. lines (when driving the PSTN from a
600 ohm resistive source). The high frequency tone should
be at a higher power level than the low frequency tone by
approximately 2 dB. The maximum combined power, averaged over the pulse duration, should not exceed + 1 dBm.
The minimum steady state power of the high frequency
tone should not be less than - S dBm. When connecting
the modem circuit to the PSTN by means of a data access
arrangement (DAA) set for permissive mode, the DAA gain
is -9 dB. The modem circuit must, therefore, drive the
DAA input with + 1 dBm of steady state high frequency
R24MFX AND R24BKJ
Frequency number = 9.1022 (desired frequency in Hz).
R48MFX AND R48PCJ
Frequency number = 6.S267 (desired frequency in Hz).
R24MFX, R24BKJ, R48MFX, AND R48PCJ
Power number = 27573.6 [10(Po/20)]
Document No. 29300N03
5-130
Order No. 813
January 1987
Application Note
DTMF Dialing Using the R24XXX or R48XXX Modem
DETECTING ANSWER TONE
Where Po = output power in dBm with a series 600 ohm
resistor into a 600 ohm load.
The modem tone detect bit, TDET (A:7), can be used to
detect the presence of answer tone when connection to
the remote modem is successful. Bit TDET goes active
(one) when energy is detected by the associated tone
detect filter. This filter is illustrated in Figure 2.
These decimal numbers must be converted to hexadecimal form then stored in RAM by following the RAM data
write routine illustrated by Figure 1.
Hexadecimal numbers for DTMF generation on the
R24MFX and R48MFX are listed in Table 3. These numbers
are also suitable for use with the R24BKJ and R48PCJ.
Numbers used for setting the frequency of tone 1 and tone
2 are larger in the 2400 bps products than in the 2400/4800
bps products. This variation is due to the sample rate difference between these modems. Power levels are selected
to give the desired output power for each tone while compensating for modem filter characteristics.
Table 3.
A set of eight coefficients determines the filter response.
Table 2 lists the RAM access codes and filter coefficient
values to be written using the RAM Data Write routine of
Figure 1. These values tune the filter to detect 2100 Hz
± 25 Hz.
Once TDET turns on, the calling modem knows the call
has been answered. At the end of the answer tone, TDET
returns to zero and data transmission can begin.
COMPLETE CALLING SEQUENCE
DTMF Parameters
Digit
RAMA
R24XXX
R48XXX
0
8E
8F
44
45
2174
2F80
6184
7A80
1918
23AO
61B4
7A80
1
8E
BF
44
45
18C8
2AFC
61E8
7AFC
1296
2030
61E8
7AFC
2
8E
8F
44
45
18C8
2F80
61EB
7A80
1296
23AO
61E8
7A80
3
8E
8F
44
45
18C8
3483
61E8
79E3
1296
2763
61E8
79E3
4
BE
8F
44
45
1B60
2AFC
6250
7AFC
1488
2030
6250
7AFC
5
8E
8F
44
45
1B60
2F80
6250
7ABO
1488
23AO
6250
7A80
6
8E
8F
44
45
1B60
3483
6250
79E3
14B8
2763
6250
79E3
7
BE
8F
44
45
1E4A
2AFC
621A
7AFC
16BB
2030
621A
7AFC
8
8E
8F
44
45
1E4A
2F80
621A
7A80
16B8
23AO
621A
7ABO
9
8E
BF
44
45
1E4A
34B3
621A
79E3
16B8
2763
621A
79E3
A complete calling sequence consists of several steps
including modem configuration, telephone number selection, DTMF transmission, and answer tone detection. A
sample flow chart for implementing an auto-dialer in host
software is illustrated in Figure 3.
The auto-dialer routine may be entered at one of two
points; either AUTO DIAL or REDIAL. When entering at
AUTO DIAL, the host prompts the user to enter a phone
number, which is then stored in the phone number buffer.
When entering at REDIAL, the routine dials the number
previously stored in the phone number buffer and does not
issue a user prompt.
Interrupts not required during dialing are disabled to prevent errors in real time delays_ Interrupt status is saved to
allow restoring these interrupts when dialing is complete.
The current modem configuration is saved prior to selecting the tone configuration, then restored at the completion of the auto-dialer routine to allow data transfer.
The commands for off-hook and request coupler cut
through are typical of signals required by data access
arrangements that may be connected to the modem for
switched network operation.
Since the number to be dialed varies in length depending
on the requirements of various PBX equipment, domestic
telephone companies, and foreign PTTs, the number
buffer must allow for numbers of different length. The
method used in Figure 3 to determine the end of valid
bytes in the buffer is zero recognition. After the last digit
is entered, the carriage return must place a hexadecimal
00 (nul character) in the buffer. All other bytes must be
non-zero ASCII characters. Only numeric characters
(ASCII 30 through 39) are printed and dialed. Non-numeric
characters are tested for comma and nul. Comma causes
a 2-second pause in dialing to allow for known delays in
the telephone network or PBX. Nul ends the dialing portion of the routine and begins the answer tone detection
portion. All other characters are ignored.
5-131
D
Application Note
DTMF Dialing Using the R24XXX or R48XXX Modem
CHANGE RAMA (F:O-7)
Figure 1.
RAM Data Write Routine
5·132
DTMF Dialing Using the R24XXX or R48XXX Modem
Application Note
0«1)
INPUT
2
0<"(7)
2
0<'(4)
--001+{
} - - - -..... OUTPUT
TO THRESHOLD
COMPARATOR
TOET = 1 IF OUTPUT;;,: 118
TDET = 0 IF OUTPUT
1ST BI·QUAD FILTER
2ND BI.QUAD FILTER
< 118
ENERGY AVERAGING
NOTE: NUMBERS IN ( ) REFER TO NODE NUMBERS IN TABLE 4.
Figure 2.
Table 4.
Tone Detector Coefficients for 2100 Hz
R24XX
Node
1
2
3
4
5
6
7
8
Coefficient
Name
a
i31
{l2
a'
i3;
i32
a"
{l"
Tone Detector Diagram
tone detector can monitor call progress for dial tone, busy
signal or ringback tone. The detector filter must be
returned to detect different frequencies used in call prog·
ress signaling. Table 5 lists tones for various lines in the
Bell network. These call progress signals vary according
to the telephone networks of each country. For details on
tuning the tone detector for other frequencies, refer to
Application Note Order No. 668. That note refers to the
R96F filters but is also applicable to R24XXX and R48XXX
modems for coefficient calculation. When applying Appli·
cation Note 668 to R24XXX modems, the sample rate used
should be 7200 samples per second rather than 9600 sam·
pies per second.
R48XX
RAM A
Coefficient
Value
RAMA
Coefficient
Value
36
37
38
39
3A
3B
B6
B7
0198
EOF4
COC5
0198
0033
COC5
0020
7F01
38
39
3A
3B
3C
30
B8
B9
0198
1A4A
COC5
0198
175A
COC5
0020
7F01
The answer tone detection logic allows 30 seconds for
2100 Hz recognition. If answer tone is not recognized
within this time limit, the call is aborted. If answer tone
is recognized, the routine jumps to the data handling
software.
In OEM equipment that combines the features of a
modem with those of a telephone handset, the tone gener·
ators may be used to generate a caller reassurance tone
(or even music) while the caller is kept on hold. To gener·
ate a single tone, set one of the oscillators to zero fre·
quency or zero amplitude while the other oscillator is
keyed on by the RTSP bit. This technique is also applica·
ble for generating a 2100 Hz answer tone when the modem
is used to automatically answer a call. The parameters for
2100 Hz answer tone generation are listed in Table 6.
ADDED FEATURES
The application of modem tone generation and detection
to DTMF dialing and answer tone recognition can be
extended to include additional features. For example, the
5·133
Application Note
DTMF Dialing Using the R24XXX or R48XXX Modem
REQUEST PHONE NUMBER
FROM INPUT DEVICE
AND LOAD NUMBER BUFFER
GO TO REDIAL ROUTINE
SAVE INTERRUPT STATUS
AND DISABLE INTERRUPTS
SAVE MODEM'S CURRENT CONFIGURATION
AND SELECT TONE CONFIGURATION
SET TONE DETECT FILTER
COEFFICIENTS FOR 2100 Hz
SET DATA ACCESS ARRANGEMENT
(DAA) TO OFF·HOOK
REQUEST COUPLER CUT
THROUGH FROM DAA
START 3 SECOND TIMER
N
PRINT "NO COUPLER CUT THROUGH"
AND SET DAA TO ON·HOOK
PRINT "DIALING"
Figure 3.
Autodialer Flow Chart
5·134
Application Note
DTMF Dialing Using the R24XXX or R48XXX Modem
SELECT ONE SET OF FOUR
COEFFICIENTS FROM TABLE 3
BASED ON VALUE OF BYTE
STORE FOUR COEFFICIENTS
IN RAM USING RAM WRITE
ROUTINE OF FIGURE 1
Figure 3. Autodialer Flow Chart (Cont'd)
5-135
Application Note
DTMF Dialing Using the R24XXX or R48XXX Modem
N
Figure 3. Autodialer Flow Chart (Cont'd)
5·136
Application Note
DTMF Dialing Using the R24XXX or R48XXX Modem
Table 5.
Call Progress Signals
--
Use
Tone
Frequency (Hz)"
Precision Dial Tone
350
+440
Continuous
Dialing may commence
Old Dial Tones
600
+ 120 or 133, and
other combinations
Continuous
Dialing may commence
PrecIsion Busy
480
+620
0.5 Sec On
0.5 Sec. Off
Called Ime busy
Old Busy
600
+ 120
0.5 Sec On
0.5 Sec. Off
Called line busy
PreCIsion Reorder
480
+620
Old Reorder
600
+ 120
03 Sec. On }
0.2 Sec. Off
0.2 Sec. On }
0.3 Sec Off
0.25 Sec. On }
0.25 Sec. Off
PreciSion Audible
Ringmg
440
+480
2 Sec. On
4 Sec. Off
To calling customer
420
+ 40, and other
combinations
2 Sec. On
4 Sec. Off
To calling customer
03 Sec. On
Call waiting service; an
incoming call is waiting
On and Off 5 Times
per Sec.
To cause off-hook
customers to go
on-hook
Continuous
To cause off-hook
customers to go
on-hook
On 05 Sec. Every 15
Seconds
To Indicate call is being
recorded by distant
customer
r------------
Old Audible
Ringing
_.
Cali Waiting
PrecIsion Receiver
Off· Hook (ROH)
Precision High Tone
Old High Tone
Recorder
Connector Tone
;, A
Interruption Rates
I
Local
Reorder
Toll
Reorder
Toll
Local
All local sWitching paths
busy, all trunks busy, all
paths or trunks busy
--
440
1400
+2060
+2450
+2600
480
480, 400 or 540
1400
"+" Sign Indicates either superposition (precision tones) or modulation (old tones).
Table 6_ 2100 Hz Answer Tone Parameters
Frequency
RAMA
R24XXX
R48XXX
2100 Hz
8E
8F
44
45
4AAA
0000
5FFF
5FFF
3800
0000
5FFF
5FFF
5-137
5-138
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WASHINGTON, D.C.
Beacon North
103-F Carpenter Dr.
(Sterling, VA 22170)
(703) 478-2480
(See Rosemont, IIltnols)
WEST VIRGINIA
TENNESSEE
2074
MISSISSIPPI
VERMONT
Norcom, Inc.
Naudaln Associates
MICHIGAN
Quorum 3
7427 Parkcrest Ct
Salt Lake City, UT84121
(801) 943-9227
Ossmann Component Sales Corp.
300 Main St
Vestal, NY 13850
(607) 754-3264
TWX' 510252-1987
2029
Robert O. Whltasell & A.soclatel
408 Cedar Bluff Rd ,Ste 145
Knoxville, TN 37923
(615) 694·9476
TEXAS
NORTH CAROLINA
2031
2021
Norcom, Inc.
Currie, Peak and Frazier, Inc.
8330 Burnet Rd, Ste 106
Aus"n, TX 78758
(512) 451·2757
TWX. 910 874-1383
1212 Grove St
P.O. Box 5588
Greensboro, NC 27403
(919) 373-0380
2030
Norcom, Inc.
4450 Sigma Rd.
SUite 135
Dallas, TX 75234
(214) 386-4888
TWX' 910 860-5456
NORTH DAKOTA
Rockwell International
(See Rosemont, illinOIS)
OHIO
2022
Robert O. Wh Iteoell & AOloelatel
1172 West Galbraith
CmClnnatl, OH 45231
(513) 521-2290
2023
Robert O. Wh Itesell & ASloelatel
6000 West Creek Rd, Ste 21
Cleveland, OH 44131
(216) 447-9020
TWX 810427-2211
2024
Robert O. Wh itelell & ASloclates
6161 Busch Blvd.
SUite. 108
Columbus, OH 43229
(614) 888-9396
TWX. 801 337-2076
A-2
2032
Norcom, Inc.
8502 Tybor, Ste. 115
Houston, TX 77074
(713) 778-0392
TWX. 910 881-1056
2080
Norcom, Inc.
7110 Mountam Grove
San AntOniO, TX 78250
(512) 680-4513
UTAH
Round Valley Services
478 West 650 South
Orem, UT 84058
(801) 224-5773
Robert O. Whltelell & AeBoelates
(See CincinnatI OhiO)
WISCONSIN
2058
Larsen Associates Inc.
10855 W Potter Rd
Wauwatosa, WI 53226
(414) 258-0529
WYOMING
Quorum 3
(See Denver, Colorado)
CANADA
2036
Renmark Electronics Limited
180 Yorkland Blvd., Ste 1
Willowdale, Ontano
Canada M2J 1 R5
(416) 494-5445
Telex' 06 986 557 RENMARK TOR
2047
Renmark Electronics Limited
1445 Woodruffe Ave
Napean, Ottawa
Canada K2G 1WI
(613) 727-0320
AUSTRALIA
VSI ElectroniCs Ply. Limited
16 Dickson Ave.
Artarmon, NSW
2064 Australia
(02) 439-4655
TLX AA22846
FAX. (02) 439-6435
INDUSTRIAL DISTRIBUTORS- UNITED STATES/CANADA
The following Distributors stock Rockwell semiconductor and telecommunication products. If there is no distributor location close to you, call
the nearest Rockwell semiconductor products sales representative listed on the reverse page.
ALABAMA
1000
Hamllton/Avnet Electronics
4940 Research Dr N.W
Huntsville, AL 35805
(205) 837·7210
TWX. 810 726·2162
Quality Components
4900 University Sq., Ste. 20
Huntsville, AL 35816
(205) 830·1881
1188
Marshall Industries
33 ~ 3 Memonal Parkway South
Huntsville, AL 35801
(205) 881·9235
ARIZONA
1002
Hamilton/Avnet Electronics
505 So Madison Dr
Tempe, AZ 85281
(602) 231·5100 or894·1666
TWX 910 950-0077
1167
Marshall Industries
835 West 22nd Street
Tempe, AZ 85282
(602) 968·6 I 8 I
CALIFORNIA
Zeus West Anaheim
1130 Hawk Circle
Anaheim, CA 92807
(714) 632·6880
1156
Marshall Industries
9710 De Soto Avenue
Chatsworth, CA 91311
(818) 407·4100
1149
Hamilton/ Avnet
9650 De Soto Ave
Chatsworth, CA 91 31 1
(818) 700·6500
1004
Avnet Electronics
350 McCormick
Costa Mesa, CA 92626
(714) 754·6111
TWX 910595'2638
1005
Hamilton Electro Sales
3170 Pullman Sl
Costa Mesa, CA 92626
(714)641,4100
1003
Hamilton Electro Sales
10950 Washington Blvd.
Culver CIty, CA 90230
(213) 558·2000
1006
Hamilton/ Avnet Electronics
International Group
10950 WaShington Blvd.
Culver City, CA 90230
(213) 558·244 I
1148
Western Micro Technology Inc.
10040 Bubb Rd
Cupertino, CA 95014
(408) 725·1660
1159
Marshall Industries
9674 Telstar Avenue
EI Monte, CA 91731
(8 18) 442· 7204
Hamilton Electro Sales
1361·B West I 90th 51.
Gardena, CA 90248
(213) 217·6748
FLORIDA
1190
Marshall Industries
1 Morgan Avenue
Irvme, CA 9271 0
(714) 859·5050
1013
Hamilton/Avnet Electronics
6801 N W. I 51h Way
Fort Lauderdale, FL 33309
(305) 97 I ·2900
TWX. 510956·3097
Marshall Industries
336 Los Coches 51.
Mllpllas, CA 95035
(408) 943·4600
1186
Marshall Industries
1001 N W 62nd Street, #306~D
Ft Lauderdale, FL 33309
(305) 928·066 t
Hamllton/Avnet Electronics
3002 East G Street
Ontario, CA 91764
(714) 989·4602
1165
Marshall Industries
1172
4205 34th Street. S.W.
Orlando, FL 328 I I
(305) 84,., 878
Marshall Industries
3039 Kilgore Avenue, :# 140
Rancho Cordova, CA 95813
(916) 635·9700
1092
Hamilton/Avnet Electronics
4103 Northgate Blvd
Sacramento, CA 95834
(916) 925·2216
Zeus
1750 West Broadway
SUite 1114
OVlevo, FL 32765
(305) 365·3000
1014
Hamllton/Avnet Electronics
3197 Tech Dr. North
St Petersburg, FL 33702
(813) 576·3930
TWX: 810 863·0374
1007
Hamilton/Avnet Electronics
4545 VIew ridge Ave.
San Diego, CA 92123
(619) 571·7510
TWX. 910 335·1216
1173
Marshall Industries
10105 Carroll Canyon Rd.
San Diego, CA 92131
(619) 578·9600
Reptron
14501 McCormick Dr.
Tampa, FL 33625
(8 I 3) 855·4656
1146
Hamilton/ Avnet Electronics
6947 University Blvd.
Winter Park, FL 32792
(305) 628·3888
Zeus
1580 Old Oakland Rd., Ste. 205
San Jose. CA95131
(408) 998·5121
1008
Hamllton/Avnet Electronics
1175 Bordeaux Dr
Sunnyvale, CA 94086
(408) 743·3355
TWX' 910339·9332
1152
Image ElectroniCS
1342 Bell Ave.
Tustin, CA 92680
(714) 259·0900
GEORGIA
1015
Hamilton/Avnet Electronics
5825D Peachtree Corners E.
Norcross, GA 30092
(404) 447·7500
TWX: 810 776·0432
1176
Marshall Industries
4350·J International Blvd
Norcross, GA 30093
(404) 923·5750
COLORADO
1185
Marshall Industries
7000 North Broadway
Denver, CO 80221
(303) 451·8444
1009
Hamilton/Avnet Electronics
8765 E. Orchard Rd., Ste. 708
Englewood, CO 801 I 1
(303) 740·1000
TWX' 910935·0787
Quality Components
6145 Northbelt Pkwy. Ste. B
Norcross, GA 30071
(404) 449·9508
ILLINOIS
1016
Advent Electronics
71 10·16 N. Lyndon 51.
Rosemont, IL 60018
(312) 298'4210
CONNECTICUT
1017
Hamilton/Avnet Electronics
1130 Thorndale Ave
BensenVille. IL 601 06
(3 12) 860·8522
TWX 910227'0060
1011
Hamilton/ Avnet Electronics
Commerce Industrial Park
Commerce Dr.
Danbury, CT 068 I 0
(203) 797·2800
TWX. 7 I 0 456'9974
1012
J. V. Electronics
690 MaIO 5t.
East Haven, CT 06512
(203) 469·2321
1182
Marshall Industries
20 Sterling Or
Barnes Ind Park, N.
Post Office Box 200
Wallingford, CT 06492
(203) 265·3822
1180
Marshall Industries
1261 Wiley Road, #F
Schaumburg, IL 601 95
(312)490'0155
INDIANA
1036
Hamilton/Avnet Electronics
485 Gradle Dr.
Carmel, IN 46032
(317) 844·9333
TWX' 810 260'3966
A-3
1035
Advent Electronics
8446 Moller Rd
Indianapolis, IN 46268
(317) 872·4910
1189
Marshall Industries
6990 Corporate Dr.
Indianapolis, IN 46278
(317) 297·0483
IOWA
1086
Advent Electronics
682 58th Ave CI. 5 W
Cedar Rapids, IA 52404
(319) 363·0221
Hamilton/Avnet
915 33rd Ave., S.W
Cedar Rapids, IA 52404
(319) 362·4757
KANSAS
1191
Marshall Industries
8321 Melrose Dr
Lenexa, KS 66214
(913) 492-31 21
1037
Hamilton/ Avnet Electronics
9219 QUlvlra Rd
Overland, KS 6621 5
(913) 888-8900
TWX 910743'0005
MARYLAND
1039
Hamllton/Avnet Electronics
6822 Oak Hall Ln
Columb,., MD 21045
~1) 995·3550
X 710862·1861
Zeus
8930A Rt 108
ColumbIa, MD 20145
(301) 997·1 I 18
1161
Marshall Industries
8445 Helgerman Ct
Gaithersburg, MD 20877
(301) 840·9450
1075
Almo Electronics Corp.
8502 Dakota 0 r.
Gaithersburg, MD 20877
(301) 670·0090
MASSACHUSETTS
1179
Marshall Industries
One Wilshire Rd.
Burlington, MA 01803
(617) 658'08 I 0
Hamilton/Avnet
10~D Centennial Dr
Peabody, MA 01 960
(617) 531·7430
1084
Future ElectroniCS
133 Flanders Rd.
Westboro, MA 01581
(6 17) 366-2400
MICHIGAN
1043
Advent Electronics
24713 CrestvlewCt.
Farmington Hills, MI 48018
(313) 477·1650
1077
Hamilton/Avnet ElectroniCS
2215 29th St, s.E. A·5
Grand Rapids, MI49508
(6 16) 243·8805
TWX 810273·6921
1044
Hamllton/Avnst Electronics
32487 Schoolcraft Rd
Livonia, MI48150
(313) 522-4700
lWX: 810 242-8775
1162
Marshall Industries
31 OB7 Schoolcraft
livonia, M I 48150
(313) 525-5850
Reptron
34403 Glendale Rd.
Post Office Box 2788
livonia, M I 481 50
(313) 525-2700
MINNESOTA
1127
Voyager Electronics Corp.
7163 Commerce Circle West
Frrdley, MN 55432
(612) 571-7766
1047
Hamllton/Avnet Electronics
10300 Bren Rd. E.
Minnetonka, MN 55343
(612) 932-0600
lWX: 910 576-2720
1163
Marshall Industries
3800 Annapolis Ln.
Plymouth, MN 55441
(612) 559-221 1
MISSOURI
1048
Hamllton/Avnet Electronics
13743 Shoreline Ct.
Earth City, MO 63045
~~~ ~~6-i~~?0684
NEW HAMPSHIRE
Hamllton/Avnet Electronics
444 E. Industrral Park Dr.
Manchester, NH 031 03
(603) 624-9400
NEW JERSEY
1156
Pan American Electronics Inc.
59 Main Street
Bloomingdale, NH 07403
(201) 839-0077
1020
Hamilton/Avnet Electronics
1 Keystone Ave., Bldg. 36
Cherry Hill, NJ 08003
(609) 424-01 10
lWX: 710 940-0262
1078
Hamllton/Avnet Electronics
10 Industnal Rd.
Fairfield, NJ 07006
(201) 575-3390
lWX: 710 734-4388
1164
Marshall Industries
101 Fairfield Rd.
Fairfield, NJ 07006
(201) 882-0320
1166
Marshall Industries
102 Gaither Dr.
Mt. Laurel, NJ 08054
(609) 234-9100
1126
General Components Inc.
245-0 Clifton Ave.
West Berlin, NJ 08091
(609) 768-6767
NEW MEXICO
1184
Marshal' Industries
1022
Hamilton/Avnst Electronics
2524 Baylor Dr. S.E.
Albuquerque, NM 87106
(505) 765-1500
lWX: 910 989-0614
6212 Executive Blvd.
Dayton, OH 45424
(51 3) 236-8088
1181
MarshaJllnduBtrles
5905-B Harper Rd.
Solon, OH 44139
(21 B) 248-1 7~
1133
Hamllton/Avnst Electronics
777 Brooksedge Blvd.
Westerville, OH 43081
(614) 882-7004
NEW YORK
RAE Industrial Elsc_ Ltd.
Acaclan Express ltd.
61 Aero Dr.
Cheektowaga, NY 14225
c/o Jim McCullough
1183
Marshal"ndustrie.
2045 Chenault
Carrollton, TX 75008
(214) 233-5200
1052
Hamllton/Avnst Electronics
2111 W. Walnut Hill Ln.
Irving (Dallas), TX 75062
(21 4) 550-77 55
lWX: 910860-5929
1187
Marshall Industries
3698 Westchase Dr.
Houston, TX 77042
(713) 895-9200
(416) 736-1588
1114
Samlspeciallsts of America
564 Smith St.
OKLAHOMA
1113
Quality Components, Inc.
9934 East 21 st St. South
Tulsa, OK 74129
(918) 664-8812
Farmingdale, NY 11735
(516) 293-2710
FAX: (516) 293-2707
1025
Hamilton/Avnst Electronics
933 Motor Parkway
Hauppauge, LI, NY 1 1787
(516) 231-9800
lWX: 510224-6166
1192
Marshall Industries
2750serAve.
Hauppauge, LI, NY 1 1788
(516) 273-2424
OREGON
1150
Western Micro Technology Inc.
13770 S.w. 24th
Beaverton, OR 97005
(503) 629-2082
1169
Marshall Industries
8230 S.w. Nimbus Ave.
Beaverton, OR 97005
(503) 644-5050
1032
Hamilton/Avnet Electronics
6024 S. W. Jean Rd.
Bldg. C, Suite 10
Lake Oswego, OR 97034
(503) 635-8157
lWX: 910455-8179
Marshall Industries
129 Brown St.
Johnson City, NY 13790
(607) 798-1611
1024
Hamllton/Avnet Electronics
333 Metro Park
Rochester, NY 14623
(716) 475-9140
lWX:510253-5470
1171
Marshal' Industries
1280 Scottsville Rd.
Rochester, NY 14624
(716) 235-7620
1023
Hamllton/Avnet Electronics
103 Twin Oaks Dr.
Syracuse, NY 13206
(315) 437-2641
PENNSYLVANIA
1034
Almo Electronics
9815 Roosevelt Blvd.
Philadelphia, PA 1911 4 ~'.
(215) 698-4000
Hamllton/Avnet
2800 liberty Ave., Bldg. E
Pittsburgh, PA 15222
(412) 281-4150
1168
Marshall Industries
701 Alpha Drive, Ste. 240
Pittsburgh, PA 15238
(412) 963-0441
1033
E_C_I_
1569 W. King Sl
York, PA 17404
(717) 843-8971
NORTH CAROLINA
1027
Hamllton/Avnet Electronics
3510 Spring Forest Rd.
Raleigh, NC 27604
(919) 878-0810
lWX: 510 928-1836
1170
Marshall Industries
5221 North Blvd.
Raleigh, NC 27604
(919) 878-9882
TEXAS
1110
Quality Components, Inc.
4257 Kellway Circle
Addison, TX 75001
(214) 733-4300
lWX: 91 0 860-5459
1050
Hamllton/Avnet ElectroniCs
1807-A W. Braker Lane
Austin, TX 78758
(512) 837-891 1
lWX:910874-1319
1177
Marshall Industries
8504 Cross Park Dr.
Austin, TX 78758
(512) 837-1991
1112
Quality Components, Inc.
21 20-M Baker Ln.
Austin, TX 78758
~ 12) 835-0220
LX: 324930
Quality Components
2940-15 Trawick Rd.
Raleigh, NC 27604
(919) 876-7767
OHIO
1028
Hamilton/Avnet Electronics
4588 Emery Industrial Parkway
Cleveland, OH 44128
(21 6) 831-3500
lWX: 810 427-9452
1029
Hamilton/Avnet Electronics
954 Senate Dr.
P.O. Box 610
Dayton, OH 45459
(513) 433-6700
lWX 81 0450-2531
A·4
Zeus
1800 N. Glenville Dr., Ste. 120
Richardson, TX 75081
(214) 783-7010
Hamllton/Avnst Electronic
4850 Wright Rd.
Stafford, TX 77477
(713) 240-7898
1111
Quality Componenta, Inc.
1005 I ndustrral Blvd.
Sugarland, TX 77378
(713) 240-2255
UTAH
1059
HamlltonJAvnet Electronics
1585 West 2100 South
Salt Lake City, UT 84 1 19
(801) 972-2800
lWX: 910 925-4017
WASHINGTON
1060
Hamllton/Avnet Electronics
14212 N.E. 21stSt
Bellevue, WA 98007
(206) 643-3950
lWX: 910443-2469
1175
Marshall Industries
14102 N.E. 21st Street
Bellevue, WA 98007
(206) 747-9100
1149
Western Micro Technology Inc.
14636 N.E. 95th Street
Redmond, WA 98052
(206) 881-6737
WISCONSIN
1061
Hamllton/Avnet ElectroniCS
2975 Marrland Rd.
New Berlin, WI53151
(414) 784-4510
lWX:910262-1182
CANADA
1091
Hamllton/Avnet Electronics
2816 21st St. N.E.
Calgary, Alberta
Canada T2 E 6Z2
(403) 250-3586
lWX: 03-827642
1082
Cardinal Industrial Electrcnlcs Ltd.
10630 172nd Sl, P.O. Box 12000
Edmonton, Alberta
Canada T5J 2 P4
(403) 483-6266
Telex: 037-2372
RAE Industrial Elec. Ltd,
11680170 St.
Edmonton, Alberta
Canada T5S 1J7
(403) 451-4001
ROCKWELL SEMICONDUCTOR PRODUCTS SALES OFFICES-INTERNATIONAL
You can obtain expert applications assIstance. price quotations and delivery data from the Distributors and Sales Representatives listed below for Rockwell
semiconductor and telecommunication products. If there is no Rockwell distributor convenient to your country, please consider Hamilton/Avnet
International listed below.
EUROPE & MIDDLE EAST
AUSTRIA
0226
W. MoorGESMBH
Storchengasse 1/1/1
A-115Q Wlen
Austna
43 (222) 858·646
TLX·047-135701 moora
BELGIUM
0272
Mlcrotron International
Tremelobaan
131-2850 Keerbergen
Belgium
(016) 600586
TLX' 846-22606 mit ron b
DENMARK
0244
Micronor APS
Torvet 1
8600 Sllkeborg
Denmark
(45,6) 816522
TLX 63245 MICRONOR DK
FINLAND
0252
VALTAMATIC
Pakilantle61, P1 21
SF'00660 HelSinki 66
Fmland
(358-0) 742-011
TLX: 124440 VALTA SF
FRANCE
0223
System Contact
88, Avenue du General de Gaulle
67200 Eckbolshelm
France
(33·88) 782·089
TLX. 890266 Syconf
0259
ERN
237 rue de Fourney
78530 BUC France
(33-3) 956-0011
TLX.698627
0279
DATADIS
10-12 rue Emile Landnn
92100 Boulogne, France
(33-1) 605-6000
TLX. 201905
Rhonalco
4- rue Roger - Brechan
F·69003 Lyon
France
(33-7) 853.00 25
TLX: 380284
HOLLAND
Alcom Electronics BV
Esse Baan 1
Postbus 358, 2900 LJ
Capelle AID I)ssell
Holland
010·51 9533
TLX.26160
INDIA
4066
Semiconductor Complex Limited
Phase VIII SAS NAGAR-160059
Punjab, India
87265,87809,87585
TLX: 395270 LSI
ISRAEL
0255
Bynet Data Communications
8-Hanechoshet 8t
Ramat-Hachayal
Tel-AvIv 6971 0, Israel
(03) 498-811
TLX 35517
WEST GERMANY
Bltronlc GmBH
Dlngolfingerstr. 6
0.8000 Muenchen 80, Germany
(49·89) 496001
TLX 5212931 bit d
0245
Unltronlc GmBH
Munsterstr.338
PO. Box 330 429
4000 Dusseldorf 30
W. Germany
(49,211) 626364·67
TLX 8586434 umd d
ITALY
0260
Murata Erie
Via Melchiorre Glona, 66
T-20125 Milano, Italy
(39-2) 607 -3786
TWX. 330385
0237
Astronlc GmBH
Wmzererstr 47d.
8000 Munchen 40
MUnich, West Germany
(49·89) 309031
TLX: 5216187 a strd
NORWAY
0271
Satt Electronics
o H. Bangs Vel 17
Postboks 70
1322 Hovlk, Norway
(47,02) 123600
TLX. 72559 sail n
FAR EAST
AUSTRALIA/NEW ZEALAND
SPAIN
0239
Comelta SA.
Emllho Munoz 41
ESC 1, Planta 1, Nave 1-1-2
Madnd 17, Spain
(34-1) 754'3001
TLX: 42007 CETA E
4054
VSI Electronics
(Australia) Pty. Ltd.
26 Dickson Avenue
Artarmon, NSW 2064 Australia
P.O Box 578
Crows Nest, NSW 2065
Bnsbane, Australia
(02) 439-4655
FAX. (02) 439-6435
TLX: AA·22846
SWEDEN
SetomaAB
Box 3005
Delvaegen 12
S-17103 Solna, Sweden
(46-8) 820280
TLX 19389 BETOMA S
HONG KONG
Tektron Electronics (HK) Ltd.
1702 Bank Centre
636 Nathan Rd
Kowloon, Hong Kong
(852-3) 880629
TLX 38513 TEKH L
SWITZERLAND
0227
Aumann & Co. AG
Foerrlibuckstr 150
CH·8037 Zunch
SWitzerland
(41-1) 443-300
TLX: 822 966
JAPAN
0268
KS Semiconductor, Inc.
3-6-31-1 F Osaki Shmasgawaku
T141 Tokyo, Japan
03 (490) 0761-2
UNITED KINGDOM
0267
Steatite MicroelectroniCS Ltd.
Hagley House, Hagley Rd.
Blrmmgham 816 80W
England
(021) 454-2655
TLX: 337645
0269
Kanematsu Semiconductor Corp.
2-8-5 Hachobon
Chuo-Ku, Tokyo 104, Japan
(03) 551-7791
TLX: 252 3798 KSC J
0258
R.C.S. Microsystems Ltd.
The Kmgs Arms
141, Uxbndge Rd.
Hampton Hill, Middlesex
TW12 1 BL, England
(01) 879-2204
TLX: 8951470 RCS MIC
0216
Pelco Electronics Ltd.
Spnng Gardens
London Rd.
Romford, Essex
PM7 9LP, England
(44-708) 61911
TLX: 23984
0280
Abacus Electronics PLC
Abacus House
Bone Lane, Newbury
Berkshire, RG14 5SF, England
(0635) 30680
TLX:849343
0203
Kyokuto Boekl Kaisha, Ltd.
7th Floor, New Otemachl Bldg.
1-1, 2-chome, Otemachl, Chlyoda-ku
Tokyo, Japan
(03) 244-3803
TLX: J22440
0204
Kyokuto Boeki Kaisha, Ltd.
Rm.606
MalOichl Osaka Kalkan Kltakan
53, Dojlma-Funadaikumachl, Klta-ku
Osaka, Japan
(06) 344·1121
TLX c/o KBK's Tokyo Office
0266
Marubeni-Hytech Co. Ltd.
1-1, Higashilkebukuro
3 Chome, Toshlmaku
Tokyo, Japan
(81-3) 989-7810
TLX: J32547
A-S
0206
Matsushita Electric Trading Co.
p.e Box 18, Trade Center
32nd Floor, World Trade Center Bldg
4-' Hamamatsu-cho 2-chome
Mlnato-ku
Tokyo 105, Japan
(81-3) 435-4552
TLX: 522-8771 MUTOSK J
0207
Matsushita Electric Trading CO.
71 Kawaramachl,5-chome
Higashl-ku
Osaka 541, Japan
(06) 204-5563
TLX 522-8771
KOREA
0242
Unlstandard Corp.
757-1 Bang Bae-Dong
Kang-Nam Ku
Seoul, Korea
Mall Add.. CPO Box 7194 Seoul
TLX' K22116 "UNISr'
(82-2) 532-6815
NEW ZEALAND
0243
Microprocessor Development Ltd.
100 Pah Rd, Royal Oak
P.OB.24159
Aukland, New Zealand
(64·9) 653·119
TLX. NZ 60613
SINGAPORE
0262
Dynamar International Ltd.
12, Lorong Bakar Batu
Kolam Ayer Industrial Est
Smgapore RE 1334
7476188
TLX: 26283
TAIWAN
0213
Sertek International Inc.
3rd Floor, No. 135
Chien Kuo N Road, Sec 2:
Taipei, Taiwan, ROC
(021537·5091
TLX.13579
THAILAND
0253
Slam Teltech Co. Ltd.
75 SOl Rubia
Sukhum-Vlt 42
Prakanong, Bangkok
PO. Box2718
Thailand
(39) 02445054
TLI<. 82631 WHITCO TH
SOUTH AMERICA
ARGENTINA
0271
Control Digital S. R. L.
BME Mitre 688·4 to PISO of 409
1036 Buenos Aires, Argentina
54-1'33-3460
TLX- 24774
OTHER COUNTRIES
1006
Hamilton/Avnet Electronics
International Group
10950 Washington Blvd
Culver City, CA 90230
(213) 558-2441
RAE Industrial Elec. Ltd.
3455 Gardner Cou rt
Burnaby, British Columbia
Vancouver, Canada V5G 4J7
(604) 291·8866
Telex 04·356533
1072
Future Electronics, Inc.
1695 Boundary Rd
Vancouver, British Columbia
Canada V5K 4X7
(604) 294·1166
FAX: (604) 294·1206
RAE Induatrlal Elec. Ltd.
#103·11 Morris Dr.
Burnside Industnal Park
Dartmouth, Nova Scotia
Canada B3 B 1 M2
(902) 465·2350
1081
Future Electronlc8 Inc.
RAE Industrial Elec. Ltd.
760 Century St
Winnipeg, Manitoba
Canada R3H OM1
(204) 786·8401
RAE Induatrlal Elec. Ltd.
500 Norfinch Dr.
1063
Hamilton/Avnet Electronics
6845 Rexwood Rd., Units 3·5
Mississauga, Ontario
Canada L4 V 1R2
(416)677,7432
1064
Hamllton/Avnet Electronics
190 Colonnade Rd.
Nepean, Ontano
Canada K2E 7J5
(613) 226-1700
TWX: 053·4971
1070
82 Saint Regis Crescent North
Oownsview. Ontario
Canada M3J 1Z3
(416) 638·4771
1080
Future Electronics Inc.
237 Hymus Blvd.
Pointe Claire, Quebec
Canada H9 R 5C7
(514) 694·7710
Telex: 05·823554
1065
Hamilton/Avnet Electronics
2795 Halpern
'St laurent
Montreal, Quebec
Canada H4S 1M2
(514) 331·6443
Future Electronics Inc.
Baxter Center
1050 Baxter Rd
Ottawa. Ontario
Canada K2C 3P2
(613) 820·8313
Oownsview. Ontario
Canada M3N 1 Y4
(416) 736·1588
RAE Industrial Elec. Ltd.
15 Mount Royal Blvd.
P.O. Box821
Moncton, New Brunswick
Canada E1 C 8N6
(506) 857·8001
A-S
RAE Industrial EI.c. Ltd.
50 1·45A Street East
Saskatoon, Saskatchewan
Canada S7 H OW6
(306) 933·2888
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