1987_SGS_Motion_Control_Application_Manual 1987 SGS Motion Control Application Manual

User Manual: 1987_SGS_Motion_Control_Application_Manual

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Motion Control
Application Manual

January, 1987

TABLE OF CONTENTS

Page
SGS IN THE WORLD

4

INTRODUCTION

6

PRODUCT SELECTOR GUIDE

8

ALPHANUMERICAL INDEX

13

APPLICATION NOTES

21

DATASHEETS:
- Integrated circuits
- Discrete Power
- GS- D200

311

PACKAGES

1135

SGS OFFICES

1151

3

SGS IN NORTH AMERICA

WALTHAM (MA)

• f-L-e

~.-,-,POUGHKEEPS1E

(NY)

~

HAUPPAUGE (NY)

FT .LAUDERDALE (FL)

SGS IN ASIA/PACIFIC

* HEADQUARTERS

• SALES OFFICES

... FACTORIES

• DESIGN CENTERS

5

is used for the VB010 self protected switch
which features a 400V Power Darlington
capable of 10A output current with built-in
protection circuits.

tion you'll need to use them. The Motion
Control Application Manual also contains a
selection of SGS' innovative power supply
products which will be useful in your
SGS has also kept ahead in POWER MOS system.
transistors by exploiting high density cell
structures. The SGSP322HD has a reduced
chip area but equal overall performance to
the original SGSP322 so offers a cost reducDependable Delivery
tion for the user.
Advanced technology and innovation are
just two of the reasons for SGS'remarkable
growth performance. The third is manufacturing science - the ability to produce advanced products in high volumes, dependably, and with competitive quality & reliability. Just for bipolar linear and mixed
bipolar /MOS ICs SGS has four 5" wafer
fabs - in France, Italy and Singapore.
Another two state-of-the-art 5" wafer fabs
are dedicated to power transistor production. In addition, the companty has highlyautomated assembly facilities in Italy,
France, Malta, Malaysia and Singapore.
SGS also has local design centers in all major
semiconductor markets - USA, England,
France, West Germany, Singapore and Italy
- to speed the development of new products
to satisfy the special needs of your application. And a worldwide network of sales
offices and distributors means that SGS
technology is never far away_

TO-240 - The unique SGS combination of advanced chip technology in a truly "user friendly"
package, gives the solution to meet all high power
system requirements.

Moving up in power, the SGS150MA010D1
isolated TRANSPACK module containing
SGS POWER MOS transistors is designed for
high switching speed DC motor control
applications. On resistance is as low as
O.009D. and the easy drive and rugged
DMOS technology make this module ideal
for high power applications.
These advances do not stop with silicon
technology, SGS's established expertise in
packaging has led to the recent introduction
of a fully isolated package for power transistors. Used in place of the SOT-93 (TO-218),
the ISOWATT218™ provides guaranteed
isolation of 4k V DC and compliance with
VDE specifications for creepage distance and
clearance in electrical equipment.

New diffusion facilities give SGS the advantage in.
Service, Quality and cost. Sta.te-,of-the:..art 5"
wafer fabs are used for both linear' ICsand power
transistors.

All of these products are included in this
book, along with the application informa7

PRODUCT SELECTOR

Applications

DC MOTORS

f))

(Integrated Circuits)

Type and Functions
L290 - Tachometer Converter
L291 - 5 Bit D/A Converter and Position Amplifier
L292 - Switch-Mode Driver for DC Motors
L 149 - 4A Linear Driver
L 165 - 3A Power Operational Amplifier
L272/M - Dual Power Operational Amplifiers
L2720/2 - Low Drop Dual Power Operational Amplifiers
L293/E - Push-Pull Four Channel Drivers
L293C - Push-Pull Four Channel/Dual H-Bridge Driver
L293D - Push-PUll Four Channel Driver With Diodes
L298N - Dual Full-Bridge Driver
L9350 - Low Saturation Driver
TDA7272 - Full Bridge DC Motor Regulator
TDA8115 - Dual Motor Driver

DISPLAYS

M5450/1 - Led Display Drivers
M5480/81/82 - Led Display Drivers
L3654S - Printer Solenoid Driver
L60 1/2/3/4 - Darli ngton Arrays
ULN2001A/2A/3A/4A - Seven Darlington Arrays
ULQ2001 R/2R/3R/4R - Seven Darlington Arrays

SPECIAL FUNCTIONS

AM26LS31 - Quad High Speed Differential Line Driver
AM26LS32/3 - RS422 and RS423 Quad Differential Line Rec~ivers
MC1488 - RS232C Quad Line Driver
MC1489/A - Quad Line Receiver
DAC0806n/8 - 8 Bit D/A Converters
AM6012/A - 12 Bit High Speed Multypling D/A Converters
L6570A/B - 2-Channel Floppy Disk Read/Write Circuits

POWER SUPPLIES

L200 - Adjustable Voltage and Current Regulator
L296/P - High Current Switching Regulators
L387A - Very Low Drop 5V Regulator
L4901/2/3/4 - Dual 5V Regulators with Reset
L4920/1 - Very Low Drop Adjustable Regulators
L4941 - Very Low Drop 1A Regulator
L4960/2 - Power Switching Regulators
SG 1524/1525/1527/2524/2525/2527/3524/3525/3527 - Regu Iati ng Pu Ise
width modulator
TDA4601 - Switch-Mode Power Supply Controller
TDA8130/2 - Current Mode PWM Controllers
TL7700 series - Supply Voltage Supervisors
UC1840/2840/3840 - Programmable, Off-Line, PWM Controllers
UC1842/3/4/5 - UC2842/3/4/5 - UC3842/3/4/5 - Current Mode PWM
Controllers

I
14

I -Tl-

10Kn.

The oscillator provides pulses to set the two flipflops, which in turn cause the outputs to activate
the power actuator. Once the outputs have been
activated the current in the load starts to increase,
limited by the inductive characteristic of the load.

CURRENT CONTROL LOGIC
In these two circuits, the L6506 is used to sense
and control the current in each of the load wind-

Fig. 1 - Application circuit for Bipolar 2 phase stepper motor
·'W
L6505

LIS
CC
4d
RESET

S

~

\I

II

6 12

RI
7.5K

1~2

2K

7 13

01

814

02

2

03

OSC

Q SYNC
17

I

°tJ

REF2

1'1
13

16 REFI VSENSE2

RIC

GND

I

9

ENABLEB
5 INPUTI
7 INPUT2

12

10 INPUT3
12
INPUT4

II

04
VSENSEI

-

"

9
VSS
VS
ENABLE A

10

I

15

R4"

L298N 01

-

OUTPUT I

,0:'

,

03

-

, 04- 'IN493~

2

~

OUTPUT2 3
OUTPUn
OUTPUT4

SENSI SENS2
I
15

GNO
S

13

~

14

01 r-0~ r-0~ ,...o~ r-

IN4935

R')"

"-....r

CpA
R3
IK

__C3" ..I..C2"

-

...

RSI
0.5

RS2
0.5
• OPTIONAL COMPONENTS

CI
.1..
4 .7NFT

.L

59
- 342

57

Fig. 5 - Synchronizing multiple devices

the voltage across the motor during the recirculation time is much less than the power supply voltage. Figure 4 shows the ripple current for bipolar
motor applications using the L6506 and the L298.

Vee

When implementing a half step drive, both outputs
of the L6506 will be low during the half step of
one phase. This means a very long time is required
for the current in the "off" winding to decay
when driving bipolar motors.

RIC

:c

Alternately, the power stage (L298) may be
inhibited to put the output in the state and achieve
a faster current decay.

OSC

L6505

SYNC
MASTER

Since separate Vref inputs are provided for each
channel, each of the loads may be programmed
independently allowing the device to be used to
implement microstepping or applications with
different peak and hold currents. In this type of
application, changing the reference voltage (V ref )
will change the. load current, effectively implementing a transconductance amplifier.

RIC

OSC

L6505

SYNC
SLAVE
5-9345

Fig. 4 - Ripple current in Bipolar motors
In many applications the reverse recovery current
of the free wheeling diodes and of parasitic elements in the power stage will flow through the
sensing resistor in addition to the load current.
Also there is sometimes noise generated in the
system when the power stage is switched on.
These two sources of error can fool the current
limiting stage and make it appear to operate at a
subharmonic of the desired frequency. With the
proper selection of the oscillator components
this behavior can be avoided.

SYNCHRONIZING MULTIPLE DEVICES
Ground noise problems in multiple configurations
can be avoided by synchronizing the oscillators.
This may be done by connecting the sync pins of
each of the devices with the oscillato r output of
the master device and connecting the RIC pin of
the unused. oscillators to ground as shown in
Figure 5. The devices may be synchronized to
external circuits by applying synchronizing pulses
to the sync pins. It should be noted, however,
that the input pulse sets the minimum on time
of the outputs and will therefore set a minimum
output average current.

The design of the L6506 is such that the flipflops used in the device are set dominant so that
whenever the sync input is low the Q output of
the flip-flop will be high even if the reset is applied by the comparator at the same time. This
characteristic of the flip-flops can be used to make
the current sensing immune to the recovery currents and noise spikes that occur when the power
devices switch. If the sync pulse is longer than the
turn on delay time of the power stage, as shown in
Figure 6, these two sources of errors will be
ignored.

Fig. 6 - Load current and sync pulse

SELECTING THE OSCILLATOR COMPONENTS
When selecting the values for the external components for the oscillator one of the primary considerations is the operating frequency. In addition
there is another important consideration for these
components.
59

HIGH-POWER, DUAL-BRIDGE ICs
EASE STEPPER- MOTOR-DRIVE DESIGN
In addition to simplifying design problems, a family of dedicated chips improves steppermotor drive-circuit reliability by significantly reducing the component count.
The L293, L293E and L298N dual-bridge ICs (see
box, "Inside the dual-bridge ICs") significantly
reduce the problems encountered in the design of
stepper-motor drive circuitry. They can, for example, simplify the design and increase the effi-

ciency of constant--current choppers. And with a
single chip replacing the transistors and predriver
stages, circuit performance improves. Best of all,
the devices have applications in complex as well as
basic driver networks.

Fig. 1 - The simplest stepper-motor drive technique is the basic L/R configuration. Adding series resistors
and raising the supply to make an L/4R drive improves torque at high steps rates but reduces efficiency,
LOGIC
SUPPLY

6V(24V)

4 x 1N4935

A

3 OUT,

IN12

200130mH
B
I'C
OR
TRANSLATOR
LOGIC

6 OUT,
2·PHASE
BIPOLAR
STEPPER
MOTOR
(300 mA/PHASE)

C
11 OUT,

IN,10

EN.9

200/30mH

D
14 OUT,

IN,15

L293

4 x 1N4935

4,5, 12,13

NOTES:

~1?~C4R~~~rJl ~gg~~~~JJ~W~b~200 nSEC.

5-9325

61

IN SERIES WITH EACH WINDING AND
RAISE SUPPLY VOLTAGE TO 24V.

energized winding opposes the efforts of the next
winding in sequence,partially cancelling the torque.
You can minimize this effect by disabling a bridge
only when the winding it drives is turned off;
because the /:;. if/:;. t of an inductor equals E/L, disabl ing the bridge accelerates the current decay.
This action discharges the winding's stored energy
through its supply and maintains the terminal
voltage Eat Vs plus two diode drops. If you were
to leave the bridge enabled, the current would flow
to ground through one diode and one transistor,
and it would lower the terminal voltage. This
scheme doesn't apply with drives with two phases
on because no winding ever de-energizes.

MULTIPLE SUPPLIES BOOST
PERFORMANCE
A dual-level supply also improves the performance
of a basic L/R circuit. A high supply voltage yields
good torque characteristics when the motor is
running. A lower-than-rated voltage provides some
holding torque when the motor is at rest, thereby
saving power when the motor is idle.
Fig. 2 shows a suitable voltage-switch circuit. Rx
sets the holding current, which can be low because
a permanent magnet or hybrid stepper motor provides some holding torque at zero current. However,
make certain the L293's motor-supply input never
goes below the logic-supply voltage. While there's
no danger of damaging the device, it's impossible
to drive the output transistors correctly under such
conditions.

Fig. 2 - Switching the supply to a lower voltage
when the motor is idle saves current without
compromising driving power 24V

The dual bridge's enable inputs offer a means of
extending the chip's flexibility. For example, you
can connect them directly to the logic supply - no
resistors are needed - to enable the ch ip permanently. As an alternative, use the enable inputs to
disable the motor during the power-on reset
sequence.

lk
lN4935

...

lN4935
....--II~
-C::J--ol0V

In wave-drive and half-step modes, use the enable
inputs to increase torque at high speeds. When a
winding de-energizes, flux collapse is a function of
the current-decay rate. During this decay, the de-

5-9335

Fig. 3 - Maintaining a constant-average phase current this fixed-ripple chopper provides improved performance and efficiency V REF controls the phase current
5V

24V

t

?

T

A

3.3k

IN,

~

c

L(r

.3

IN,

IN,

EN,

1~

9rt-

8

r

OUT2

l.5M

1~3j

LfL-

l
370180 mH

19~
l/L,
L293E

17 14

~.6.'5.'6 ....

10k

5

18 OUT.

7

....

~2

4

.... -.:.

_

1.5M

10k

7~5j

10k
VAEF

~6
5V

2·PHASE

MOTOR
(280 rnA/PHASE)

13 OUT l

12

11

IN,

j

37 nfBO mH

BIPOLAR
STEPPER

3.3k

lN4148-

l

lN4148

~

~

1

EN.

lN4148

5V

3 OUT I

2

~

lN4148

4 x lN4935

lOV s

20V sa

1k

~£l
51

I

1
63'

J
.,.

1

.,.

5-9336

4 x lN4935

Often a }J.C controls the translator, setting the
direction line and providing a pulse for each
step. Software is thus simplified, and if you use
a programmed interrupt scheme, the }J.C is free
to handle other tasks. Fig. C describes an ab·
sOlute-positioning routine for a step with a
direction-control translator; Fig. 0 outlines
how programmed timer interrupts are used to

relieve the burden on the }.IC.
Two special cases call for hardware translation.
The first is in a system for which you have
already designed in control circuitry to provide
step and direction signals. The second case
involves single-quantity and small-run applica·
tions, in which the cost of a few ICs is a small
price to pay for simplified software.

Fig. C - For use with a hardware
translator this a absolute·positioning
routine sets the direction line and
sends the appropriate number of
step pulses.

NOTES:
ENTER WITH OESIRED POSITION
CURRENT POSiTiON IS IN REGISTER
OR MEMORY LOCATION

YES

NO

5-9333

Fig. D - To set a motor step rate,
used programmed timer interrupts
in place of software timing loops.

TIMER
INTERRUPT
SERVICE

5-9334

65

Fig. 5 - A special translator-chopper control circuit cuts the drivers components count to the minimum
5V

4 x MR851

12
CW/CCW

4

A

5

iNHT

6

B

STEP
19
HALF/FULL o--F~--"'TRANSLATOR
20
RESET

CONTROL
ENABLE

SYNC

11

2·PHASE
BIPOLAR
STEPPER
MOTOR

7 C

10

0-+'--.....
4 x MR851

5V
0.5

0.5

L297

5-9338

CONTROLLER IC REDUCES
COMPONENT COUNT

to a dual bridge. External component requirements
are minimal: and RC network to set the chopper
frequency and a resistive divider to establ ish the
comparator reference voltage (V ref).

If you're using a hardware translation and constantcurrent choppers, you can further reduce the component count by using a controller chip such as the
L297 - a 20-pin DIP that houses a translator and a
dual fixed-frequency chopper circuit. Under the
control of step and direction inputs, the L297
generates normal, wave-drive and half-step sequences.

To accommodate motors with a phase current as
great as 3.5A, replace the single dual-bridge IC
with two devices configured in parallel (input to
input, enable to enable, etcho form a single bridge.
It's extremely important that you pair the half
bridges - 1 with 4 and 2 with 3 - to ensure optimum current sharing.

As shown in Fig. 5, the controller connects directly

Reprinted from EDN. 11/24/83

© 1986

Cahners Publishing Company Division
of Reed Publishing USA.

67

INTRODUCING THE L297
STEPPER MOTOR CONTROLLER
The L297 integrates all the control circuitry required to control bipolar and unipolar stepper
motors. Used with a dual bridge driver such as the L298N forms a complete microprocessor-to-bipolar stepper motor interface. Unipolar stepper motor can be driven with an
L297 plus a quad darlington array. This note describes the operation of the circuit and
shows how it is used.
The L297 Stepper Motor Controller is primarily
intended for use with an L298N or L293E bridge
driver in stepper motor driving applications.

L297 and a special version called L297A. The
L297 A incorporates a step pulse doubler and is
designed specifically for floppy-disk head positioning applications.

It receives control signals from the system's controller, usually a microcomputer chip, and provides
all the necessary drive signals for the power stage.
Additionally, it includes two PWM chopper circuits
to regulate the current in the motor windings.

ADVANTAGES
The L297 + driver combination has many advantages: very few components are required (so
assembly costs are low, reliability high and little
space required), software development is simplified
and the burden on the micro is reduced. Further,
the choice of a two-chip approach gives a high
degree of flexibility - the L298N can be used on
its own for DC motors and the L297 can be used
with any power stage, including discrete power
devices (it provides 20mA drive for this purpose).

With a suitable power actuator the L297 drives two
phase bipolar permanent magnet motors, four
phase unipolar permanent magnet motors and four
phase variable reluctance motors. Moreover, it
handles normal, wave drive and half step drive
modes. (This is all explained in the section "Stepper
Motor Basics").
Two versions of the device are available: the regular

5V

Fig. 1 - In this typical configuration an L297 stepper
motor controller and L298
dual bridge driver combine
to form a complete microprocessor to bipolar stepper motor interface.

r

!lTEP CLOCK
HALF/FULL

CHOPPER
RATE

I

~TEP

DIRECTION

MCU

A

PHA~E

B

rr~'"

PHA5E C

ENA.BLE
C.tl~P~E.£I..!'fQD.E

PHA~E

PHA,5E 0

_•

__ H~~E____

STEPPER

MOTOR

L298N

WINDINGS

INHIBIT 1

L291

INHIBIT 2
RESET
SENSE 1

'-

SENSE2

1

"
LOAD

-

...

CURRENT
SENSE
RESISTORS

CURRENT
PROGRAM

...
69

.

~

5-5936

energized but in the opposite sense). This sequence
is known as "one phase on" full step or wave drive
mode. Only one phase is energized at any given
moment (figure 4al-

Fig. 3 - Greatly simplified, a bipolar permanent
magnet stepper motor consist of a rotating
magnet surrounded by stator poles as
shown.

The second possibility is to energize both phases
together, so that the rotor always aligns itself between two pole positions. Called "two-phase-on"
full step, this mode is the normal drive sequence
for a bipolar motor and gives the highest torque
(figure 4b).

A

The third option is to energize one phase, then two,
then one, etc., so that the motor moves in half step
increments. This sequence, known as half step
mode, halves the effective step angle of the motor
but gives a less regular torque (figure 4c).

0-+-.11//

For rotation in the opposite direction (counterclockwise) the same three sequences are used,
except of course that the order is reversed.
As shown in these diagrams the motor would have
a step angle of 90°. Real motors have multiple
poles to reduce the step angle to a few degrees but
the number of windings and the drive sequences
are unchanged. A typical bipolar stepper motor is
shown in figure 5.

B

Fig. 4 - The three drive sequences for a two phase bipolar stepper motor. Clockwise rotation is shown.
Fig. 4a - Wave drive (one phase on)
A-

A+

~
~

"'~

e

° ~ °
'/

B-

B+

5-5952

Fig. 4b - Two phase on drive

B-

B+

B+

B~_595J

Fig. 4c - Half step drive
A+

O~O
owe
B-

A+

AO

-~+

~+
y-e

~e
B-

BO

A-

-ft:\+

~e
B+

5-5938

71

therefore the sequence generated depends on the
state of the translator when fu II step mode is
selected (the HALF/FULL input brought low).

The output waveforms for this sequence are shown
in figure 10.
Note that two other signals, INH1 and TNH2 are
generated in this sequence. The purpose of these
signals is explained a little further on.
The full step modes are both obtained by skipping
alternate states in the eight-step sequence. What
happens is that the step clock bypasses the first
stage of the 3-bit counter in the translator. The
least significant bit of this counter is not affected
Fig. 8 -

If fu II step mode is selected when the translator is
at any odd-numbered state we get the two-phaseon full step sequence shown in figure 11.
By contrast, one-phase-on full step mode is obtained by selecting full step mode when the translator is at an even-numbered state (figure 12).

The L297 contains translator (phase sequence generator), a dual PWM chopper and output
con trollogic.
A
INHI B
C iNH2 D

HALF IFULL
STEP

.......- - - - f - U ENABLE
.......- - - - f - O CONTROL

DIRECTION
(CW/CCW)

0-

-

+---+--0 SYNC

HOME

GND

Fig. 9 - The eight step
master sequence
of the translator.
This corresponds
to half step mode
Clockwise rotation is indicated.

woo.
1001

0001

0101

1

8

HOME 0100

SENS 2

OSC.

Fig. 10- The output waveforms corresponding to the half step
sequence. The chopper action in not shown.
4

6

8

4

S

CLOCK

L

A

1000

2

Vr.,

SENS 1

B

6 0010

C

7

D

--,

r-

0110
INH 1

INH 2

U

U

U5-!t841

73

Fig. 13 - When a winding is switched off the inhibit input is activated to speed current decay. If this were
not done the current would recirculate through D2 and Q4 in this example. Dissipation in Rs
is also reduced.
Vs

r-,p-+--------I-c.,

~--,o--+-4-------(J

B

INHI
5-5945

SENSI

Rs

I

..J!
DRIVE CURRENT-·-·-~
RECIRCULATION - - - - - . .

In th is case when the voltage across Rs reaches
V REF the chopper flip flop is reset and i1ifR1
activated (brought low). INH1, remember, turns
off all four transistors therefore the current recirculates from ground, through D2, the winding and
D3 to V s' Discharged across the supply, which can
be up to 46V, the current decays very rapidly
(figure 18).

on this pin (figure 19). Subsequent L297s do not
need the oscillator components and use SYNC as a
clock input. An external clock may also be injected
at this terminal if an L297 must be synchronized to
other system components.

The usefulness of this second faster decay option
is fairly obvious; it allows fast operation with
bipolar motors and it is the only choice for unipolar motors. But why do we offer the slower
alternative, phase chopping?

Fig. 18-lnhibit chopper waveforms. Winding AB
is energized and CONTROL is low.
A

The answer is that we might be obliged to use a
low chopper rate with a motor that does not store
much energy in the windings. If the decay is very
fast the average motor current may be too low to
give an useful torque. Low chopper rates may, for
example, be imposed if there is a larger motor in
the same system. To avoid switching noise on the
ground plane all drivers should be synchronized
and the chopper rate is therefore determined by
the largest motor in the system.

B
CHOP

CHOP

iN'H1
SENSE
RESISTOR
CURRENT

Multiple L297s are synchronised easily using the
SYNC pin. This pin is the squarewave output of
the on-chip oscillator and the clock input for the
choppers. The first L297 is fitted with the oscillator components and outputs a squarewave signal

LOAD
CURRENT
FLIP
FLOP

RESET

77

-------- t;;.s~

;CAV

S_~946

Fig. 21 - This typical application shows an L297 and L298N driving a bipolar stepper motor wIth phase
currents up to 2A
36V
R

12 A
4

8
C
0

iNHi
iiiH2

10

STEPPER
MOTOR
WINDINGS

L298N
12

6
11

15
SENSEI
SENSE 2

RSI

RS2

RS1 RS2 = 0.5.n
01 to 08 = 2 Fast Diodes

VF';; 1,2V @ I = 2A
trr';; 200 ns

emitter connections which are connected to
sensing resistors (figure 221. Since the chopper acts
on the inhibit lines, four AND gates must be added
in this application.

made with discrete transistors. For currents up to
3.5A two L298N's with paralleled outputs may be
used.
For unipolar motors the best choice is a qU!ld
darlington array. The L702 can be used if the
choppers are not required but an L7150 or L7180
is preferred. These quad darlingtons have external

Also shown in the schematic is a zener diode in
series with the suppression diodes. This serves to
increase the voltage across which energy stored in

Fig. 22 - For unipolar motors a quad darlington array is coupled to the L297. Inhibit chopping is used
so the four AND gates must be added.
vs----------------~r_~--------~--------~--------_.

A

B

L-'0'--~r_-----J'4
~-----------------------

SENSI

79

SENS 2

PIN FUNCTIONS - L297 (continued)
NAME

7

C

8

FUNCTION

Motor phase C drive signal for power stage.
Active low inh ibit control for drive stages of C and D
phases. Same functions as INH 1.

D

Motor phase D drive signal for power stage.

10

ENABLE

Chip enable input. When low (inactive) INH1, INH2, A,
B, C and D are brought low.

11

CONTROL

Control input that defines action of chopper.
When low chopper acts on INH1 and INH2; when high
chopper acts on phase lines ABCD.

12

Vs

5V supply input.

9

13

Input for load current sense voltage from power stages
of phases C and D.

14

Input for load current sense voltage from power stages
of phases A and B.

15

V ref

Reference voltage for chopper circuit. A voltage applied
to this pin determines the peak load current.

16

OSC

An RC network (R to Vee, C to ground) connected to
this terminal determines the chopper rate. This terminal
is connected to ground on all but one device in synchronized multi - L297 configurations. f == 1/0.69 RC,
R> 10 Ul.

17

CW/CCW

Clockwise/counterclockwise direction control input.
Physical direction of motor rotation also depends on
connection of windings.
Synchronized internally therefore direction can be
changed at any time.
Step clock. An active low pulse on this input advances
the motor one increment. The step occurs on the rising
edge of th is signal.

18

19

HALF/FULL

Half/full step select input. When high selects half step
operation; when low selects full step operation. Onephase-on full step mode iS,obtained by selecting FULL
when the L297's translator is at an even-numbered state.
Two-phase-on full step mode is set by selecting FULL
when the translator is at an odd numbered position.
(The home position is designated state 1).
81

APPLICATIONS OF MONOLITHIC
BRIDGE DRIVERS
High power monolithic bridge drivers are an attractive replacement for discrete transistors
and half bridges in applications such as DC motor and stepper motor driving. This appli'cation guide describes three such devices - the L293, L293£ and L298 - and presents
practical examples of their application.

The L293, L293E and L298 each contain four each bridge to alldw the connection of current
push-pull power drivers which can be used in- sense resistors. The L293E has separate emitter
dependently or, more commonly, as two full connections for each channel; the L298 has two,
bridges. Each driver is controlled by a TTL-level one for each bridge.
logic input and each pair of drivers is equipped
with an enable input which controls a whole bridge. Figure 1 shows the internal structure of the L293,
All three devices feature a separate logic supply L293E and L298. The L293 and L293E are
input so that the logic can be run on a lower represented as four push pull drivers while the insupply voltage, reducing dissipation. This logic
ternal schematic is given for the L298. Though
supply is internally regulated.
they are drawn differently the L293E and L298
Additionally, the L293E and L298 are provided are identical in structure; the L293 differs in that it
with external connections to the lower emitters of does not have external emitter connections.

Fig. 1 - The L293, L293E and L298 contain four push pull drivers. Each driver is controlled by a logic
input and each pair (a bridge) is controlled by an enable input. Additionally, the L293E has
external emitter connections for each driver and the L298 has emitter connections for each
bridge.
V..

ENABLE A

IN 4

INI
ENABLE A 0---1"----,

L293

16

Vss

IN.

INI

OUT4

OUTI

OUr.

OUT I
SENSE I

' - - - - " + - 0 SENSE.

SENSE 2

,----'q---{) SENSE 3

OUT3

OUT 2

IN3

IN2

OUT 3

OUT 2

ENABLE B
S-~792

IN 3

IN2

'-----"-+--QENABLE B

Vs

~-S861

83

Fig. 3 -

Fig. 5 - For rotation in one direction DC motors
are driven by one channel and can be
connected to supply or ground.

This circuit protects a driver from output short circuits to ground.
R.IOKn
IN4148

Vl~

C =1.5 nF

Fig. 4 - Waveforms illustrating the short circuit
protection provided by the circuit of
fig. 3.

[

M1

M2

B

V 1nh

A

H

H

Fast motor
stop

H

Run

H

L

Run

L

Fast motor
stop

L

X

Free running
motor stop

X

Free running
motor stop

H = High

L= Low

X = Don't care

Fig. 6 - A bridge is used for bidirectional drive
of DC motors.

DC MOTOR DRIVING
In applications where rotation is always in the
same sense a single driver (half bridge) can be used
to drive a small DC motor. The motor may be connected either to supply or to ground as shown in
figure 5.

+yss

The only difference betwe'en these two alternatives
is that the control logic is inverted - a useful fact
to remember when minimising control logic.

L_.....:==:::;::::;;::;::;::;::~=r-C

Each device can drive four motors connected in
th is way. The maximum motor current is 1A for the
L293 and 2A for the L298N. However if several
motors are driven continuously care should be
taken to avoid exceeding the maximum power
dissipation of the package.

INPUTS

Each motor in this configuration is controlled by
its own logic input which gives two alternatives:
run and fast stop (the motor shorted by one of the
transistors) .
The enable/inhibit inputs also allow a free running
motor stop by turning off both transistors of the
driver. Since these inputs are common to two
channels (one bridge) this feature can only be used
when both channels are disabled together.
A full bridge configuration is used to drive DC
motors in both directions (figure 6). Using the
logic inputs of the two channels the motor can be

.1.4•5 ,12.13

5- 5165

V inh = H

FUNCTION

C = H;

D=L

Turn right

C = L;

D=H

Turn left

C=D
V inh = L
L= Low

C= X;
H = High

Vinh

Fast motor stop
D=X

Free running
motor stop

x = Don't care

made to run clockwise, run anticlockwise or stop
rapidly.
Again, the enable/inhibit input is used for a free
running stop - it turns off all four transistors of

85

Fig. 8 - This circuit illustrates PWM control of the motor speed. The speed of each motor is controlled
independently.

06
O.22#JF

.5V

02

R,

san

R2

22Kn

THRESHOLD

R3

\~'5VPP
Vp1
triangle
.......... 18 KHz

5 - 416312

STEPPER MOTOR DRIVING
Monolithic bridge drivers are extremely useful for
stepper motor driving because they simplify the
use of bipolar motors. This is an important point
since a bipolar stepper motor costs less than an
equivalent unipolar motor (it has fewer windings)
and gives more torque per unit volume, other
things being equal.
The basic configuration for bipolar stepper motor
driving is shown in figure 9. In this example it is
assumed that a su itable translator (phase sequence
generator) is connected to the four channel inputs.

At this point the comparator 'switches, disabling
the bridge. The current in the winding recirculates
through 05 and 06 until the voltage across R2 falls
below the lower threshold of the comparator. The
comparator then switches again and the cycle
repeats.

Fig. 9 - A single device can be used to drive a
two phase bipolar stepper motor.

Either an L293 or an L298N can be used in this
circuit; an L293E would be wasted compared to
an L293 because load current regulation, and
hence the sense resistor connection, is not used.
But load current regulation is highly desirable to
exploit the performance characteristics of the
motor. Using an L293E or L298N this can be implemented by adding an LM339 quad comparator
as shown in figure 10.

>Y.

1
os
1I

02

This is another circuit that requires an external
translator but it provides independent PWM
chopper regu lation of the current in each winding.
Looking at motor phase one, the comparator output is initially high, enabling the bridge through
pin 1.
The current in the motor winding rises until the
voltage across the sensing resistor R2 produces a
voltage at the inverting input of the comparator
equal to the voltage on the non-inverting input
(370 mY). This value is produced by the divider
Rl0/R" and by the hysteresis determined by R6
and R8.
87

'll

O.22IJF

0'
D.

'h

c.

I n this configuration the motor is controlled
through the L297. A step clock moves the motor
one increment, the CW/CCW" input controls the
direction and the HALF/FULL input selects half
step or normal operation. The input V ref is connected to a su itable voltage reference and sets the

peak winding current in the motor. The choppers
in the L297 can operate on the phase lines or the
inhibit lines, depending on the state of the logic
input called CONTROL.
For a more detailed description of the L297 see
"Introducing the L297 Stepper Motor Controller".

Fig. 11 - With a quad comparator both current regulation and short circuit protection can be obtained.
r-----------------------------------------------------~--------~--~--_4J+vs

20

I-----------------+-~--+_----------_O>

5~

r-~+_----------------~~--+_~--------_oV4

Vl

02

Jl

05

~1

Ll

07

04

V2
10

09

11

L293E

2xlN4148
010

011

2x1N4148
012

>S V
10
K.!l

.5Vo-----~=r----~

R17
10Kfi

10Kfi

10Kfi

Rll

R1S

R14

5-516611

89

SWITCH-MODE DRIVERS FOR SOLENOID DRIVING
This design guide describes the operation and applications of the L294 and L295 switchmode solenoid drivers. Integrating control circuitry and power stage on the same chip, these
devices replace complex discrete circuits, bringing space and cost savings.

operation and are mounted in SGS' Multiwatt ®
plastic package.

Many applications, particularly in computer peripherals, require a high power, fast solenoid driver
circuit. In the past these circuits have been realised
with discrete components because the high powers
required precluded the use of monolithic technology.

THE L294 SOLENOID DRIVER
The L294 is designed for solenoid driving applications where both very high speed and high current
are essential; needle and hammer driving in printer
mechanisms, for example. It delivers 4A with
supply voltages up to 46V, handling effective
powers up to 180W.

SGS has overcome this problem with a new high
power bipolar technology that uses an innovative
implanted isolation technique. This technology is
used to fabricate two switchmode solenoid driver
chips, the L294 and L295, which both incorporate
high power output stages and control circuitry .
. Both circu its are designed for efficient .switchmode

Shown in figure 1, the L294 is controlled by a TTL
- level logic input and the peak load current is

Fig. 1 - Internal block diagram of the L294 switchmode solenoid driver.

02

91

Fig. 4 - On-time limiter waveforms. After a period
defined by C2 the output is disabled
regardless of the state of ENABLE, protecting against overdriving.

dependently of the ENABLE input if the duration
of the input pulse exceeds a period set by the external capacitor C2 (figure 4). This circuit is reset
by taking the ENABLE input high. The on-time
limiter can be disabled by grounding pin 3.
Protection against overheating is incorporated in
the form of a thermal shutdown circuit which
disables the output stage when the junction temperature exceeds 150°C. The circuit restarts when
the temperatu re has fallen about 20° C.
The L294 is also protected against short circuits to
ground, to supply and across the load. Triggered
when the source stage current exceed 5A or the
sink stage current exceed 1 V IRs, the short circuit
protection block inhibits the output stage and sets
a flip flop which is supplied by a separate supply
voltage Vss' This flip flop is connected to the
diagnostic output and signals that all is not well a shorted solenOid, for example. The diagnostic
flip flop is reset by removing the supply V 5'
A LED can be connected to the diagnostic output
as shown in figure 5. If the diagnostic function is
not required the Vss supply can be omitted. The
short circuit protection, however, still functions,
even without V 55'

PIN 3

VOLTAGE

5-5890

PROTECTION
To protect the load and the L294 from overdriving
an on-time limiter inhibits the output stage in-

USING THE L294

Fig. 5 - Standard solenoid driving application of
the L294. Pin 1 must be connected to a
suitable reference voltage to set the peak
current.
+5V
+v.

.---t--r---..

L

The basic appl-ication circuit for the L294 is shown
in figure 5; a suggested layout is given in figure 6.
The circuit is complete except for the source of VI'
In most cases this will be provided by a simple
resistive divider dimensioned to set the desired
peak current. With a 0.2 51 sense resistor as shown,
the L294 has a transconductance of 1 A/V for Vi
above 600 mV. The device will not work with Vi
less than 450 mV and operation is not guaranteed
for Vi between 450 mV and 600 mV.

I

ZmH

I

RL
ZJl.

[
I

The on-time limiter delay - set by C2 - is approximately 120000 x C2. Pin 3 must be grounded
if the on-time limiter isn't used.
Switching frequency depends partly on the timing
network R1C1 and partly on the load characteristics.

01 : 3A Fast Diode
02 : 1 A Fast Diode

Fig. 6 - Suggested printed circuit board layout for the application circuit of figure 5.

GND

93

L295s can drive the four phases at a unipolar
stepper motor or the two phases of a bipolar
stepper motor in bridge configuration.

Figura 8 - Pin functions of the L294.

N°

FUNCTION

1

Solenoid supply voltage V s (12-46V).

2

Output, source stage.

3

On-time limiter time constant. A capacitor to ground sets delay period (120000 x
C2 seconds). On-time I imiter is disabled
by grounding this pin.

4

Supply input (5V) for diagnostic flip
flop.

5

Diagnostic output, open collector. Signals
intervention of latched short circuit
protection. Reset by removing pin 1
supply.

6

Ground.

7

Vi reference input. Peak output current
is proportional to Vi'
Transconductance is 1 A/V for RS = 0.2 nand
Vi;;' 600 mY.

8

9

Each channel of the L295 is controlled by a
TTL-level digital input and the peak load current
is programmed, independently for each channel,
by a voltage reference input. A chip enable input
is also provided to disable both channels together.

INSIDE THE L295
Internally the L295 (figure 9) bears little resemblance to the L294. Looking at channel one,
when the VINl input goes high the output transistors 01 and 02 are switched on (the enable
input EN is assumed to be active, i.e. low).
The current in the load then rises exponentially,
as shown in figure 10, until the voltage across the
external sense resistor RSl reaches the current
program reference voltage V refl'
The comparator COMP1 switches and sets the
flip flop FF1 which turns off the source transistor 01. The load current now recirculates through
D2-02-RSl and decays.
What happens next is determined by the oscillator components Rand C on pin 9. If these components are present the flip flop is reset by the
next clock pulse before the current decays very
far. The output stage is therefore turned on
again and the load current rises.

Timing. A parallel RC network from this
pin to ground sets the minimum recirculation time constant.
The capacitor must be 2.7-10 nF to
ensure stability.
The resistor must be greater than 10 kn.

When it reaches the peak value COMP1 switches
again, setting the flip flop and disabling the output stage. Th is process is repeated, regulating the
load current until V inl goes low. The output
stage is then disabled and the current falls off
rapidly, recirculating through
D1
and D2
(figure 10).

ENABLE. TTL-compatible logic input
that controls the solenoid current. The
solenoid is driven when this input is at a
low level. The on-time limiter overrides
enable.

10

Connection
resistor.

for

11

Output, sink stage.

load

current

If the oscillator components are omitted and pin
9 grounded the current simply decays slowly
until V inl goes low. The output stage is then
disabled and the load current recirculates through
D1 and D2. This case is illustrated by the waveforms of figure 11. Note that in this case the
peak current level is controlled.

sense

Unlike the L294, the switching frequency of the
current regulation loop is determined by the
oscillator components Rand C (the L294 is also
affected by the load). Typically, the switch ing
frequency will be 10-30 kHz. Another difference
between the two devices is that the L294 gives a
constant ripple, the L295 does not.

THE L295 DUAL SWITCHMODE DRIVER
The L295 is a dual switch mode solenoid driver
which handles up to 2.5A per channel at voltages
up to 46V - a total effective power handling of
220W. Compared to the L294 it offers a more
economical solution when 2.5A is sufficient
because there are two drivers per chip. Like the
L294 it features switch mode regulation of the
output current and thermal shutdown. Additionally it has a separate logic supply input so that
the logic can be run at a lower voltage, reducing
dissipation.

TWO LEVEL CONTROL
Since the peak load current is programmed by
the reference voltage (for each channel), two
level current control can be obtained by switching between two reference voltages. A high V ref
is selected initially to give a high initial current
peak. Then, after a suitable interval, V ref is reduced to give the lower holding current (figure
12). Two level current control is very useful for
solenoids which require a high initial current
peak for fast actuation.

Intended for inductive load driving, the L295 is
particularly suitable for solenoids and stepper
motors. One L295 drives two solenoids and two
95

Fig. 12 - Two level current control is obtained by
switching Vref between two values.

Figure 13 - Pin functions of the L295.

FUNCTION

N°

"~ [+"ref

i

I

iii

i:

1

Solenoid supply voltage, Vs (12-46V).

2

Channel one output, source stage.

3

Channel one output, sink stage.

4

R Sl ' Sense resistor connection, channel
one.

5

V refl . A voltage on this pin sets peak
current of channel one. If this pin is left
open or connected to V ss a defau It V ref
of 2.5V is assumed. An externally
applied Vref must be in the range 0.2
to 2V .

6

V inl . Logic input for channel one.
Driver is active when V inl is high and
EN low .

7

EN. Chip enable (active low). When high
both channels are disabled.

8

Ground.

9

Oscillator timing network. This pin is
grounded to produce a single peak.

10

V S5' Logic supply voltage, internally
regulated. (4.75 - 10V).

11

V in2 . Logic input for channel two.
Driver is active when V in 2 is high and
EN low.

12

V ref2 . Voltage input, controls peak current of channel two. If left open or connected V s an internal 2.5V reference
is assumed.
An externally applied V ref must be in
the range 0.2 to 2V.

13

RS2' Sense resistor connection. channel
two.

14

Channel two output, sink stage.

15

Channel two output, source stage.

• t

I

_!.-I-...,.--'-1.l--t-il
1

1
I

I

I

• _ _ _...:............-.1I "",

'I
I

I

I
1
1 I
1 I

.. t

,jJj--Ln-.l.:--'~....I:___nn

,t i

I

J....I..-L--L.._ _
• t

• t
5-5863

L295 APPLICATION HINTS
The basic application circuit of the L295 is shown
in figure 14. A suitable layout is given in figure 15.
Suitable values for the oscillator components, R
and C, can be found from the nomogram, figure
16. The value for the reference voltages depends on
the desired peak current and is equal to IpRs; it
must be in the range 0.2V to 2V.
If the Vref inputs are left open circuit the L295
assumes an internal default value of 2.5V giving a
peak current of 2.5/R s amperes.
The L295 can also be used to drive unipolar stepper motors. For a four phase motor two devices
are used, connected as shown in figure 17. This
circuit provides switchmode regulation of the load
current with a c!!.Qpper rate of about 25 kHz. The
enable inputs (EN, connected together) enable/
disable the whole circuit and the channel inputs
V lnl . . . V in4 are driven by a suitable translator
circuit. Phases 1 and 2 must not be energised together because they share the same sense resistor.
The same applies to channels 3 and 4. However,
'two phase on' drive is still possible for bifilar
motors where phases one and two represent one
winding and 3 & 4 the other, and also for variable
reluctance motors with phase 1 adjacent to phase
3 etc.
Two L295s could also be used to drive a bipolar
stepper motor in systems where a translator
already exists.
97

Fig. 17 - Two L295s, connected as shown, can be used to drive a four phase unipolar stepper motor.

EN

01,03,05,07 :lA FAST DIODES

02,04,06,08: 2A FAST DIODES

99

5-5892

SPEED CONTROL OF DC MOTORS
WITH THE L292 SWITCH-MODE DRIVER
Power dissipation in DC motor drive systems can be reduced considerably with an L292
switchmode driver. This application guide describes two speed control systems based on this
device; one voltage controlled and one controlled by a 6-bit binary word. Both examples
are designed for 60W motors equipped with tacho dynamos.

The L292 is a monolithic power IC which functions effectively as a power transconductance am·
plifier. It delivers a load current proportional to an
input voltage, handling up to 2A at 18-36V with a
bridge output stage. Completely self-contained, it
incorporates internal switchmode circuitry and all
the active components to form a current feedback
loop.
The L292 is designed primarily for use with an
L290 and L291 in DC motor servopositioning
applications. However, the L292 can be useful in a
wide range of applications as the two examples
here show. The first is a simple tachometer feedback circuit, the speed of which is controlled by a
DC voltage; direction is controlled by the polarity
of this Voltage. The second circuit is controlled
digitally and includes an L291 D/A converter.

Fig. 1 - Simplified circuit diagram of DC control
system
R2

Vi

2

Rl

Calculation of R1, R2, R3
Let us call:
ViM
nM
Kg

SYSTEM WITH DC CONTROL
In this system the control quantity is
variable between

will flow in the motor determining an acceleration
proportional to it.

the maximum control voltage value
the maximum speed allowed for the motor
voltage constant of the dynamo

dc voltage
By imposing that the balance condition be met in
correspondance to the maximum rotation speed
the following equation is obtained:

+ ViM and - ViM
Since the quantity under control is the speed of
the motor, it is required that it varies linearly in
function of the control voltage.
A simplified circuit diagram of the system is shown
in fig. 1.
The current 'I, proportional to the set voltage Vi,
and the current ' 2 , proportional to the speed of
the motor, are fed to the sum point of the error
amplifier. Assuming that the motor does not drain
current, the system is in a steady-state condition
whenever '1 = -1 2 ; as a matter of fact, in this case
the output from the error emplifier Vo is OV.
During transients, the voltage V 0 will assume a
value Vo = - R3 (11 + ' 2 ) and consequently, since
the L292 integrated circuit operates as a transconductance (G m ), a mean current Im= G m • Vo

101

'1

=-

ViM
'2; ~

=

Kg' nM
R2

Since R2 is the impedance which the tachometer
dynamo is loaded on to and its value is recommended by the manufacturer, it is possible from
the previous relationsh ip to determ ine the value
of R1.
Resistor R3 determines the system gain. It's best to
keep the gain as high as possible (and consequently
R3 as high as possible) to obtain a high response
speed of the system, even for small variations in
the control voltage. On the other hand, an excessive gain would cause excessive overshoot
around the balance conditions at the end of transients. Consequently, a trade-off must be made
between the two opposing requirements in select-

In this case too, the variation D. n is as much lower
as the error amplifier gain is higher.With the circuit
shown in fig. 2 D. n is approximately 30 turns/min.
with D. I = 800 mA, D. n = 0.037 turns/mA.min
approx.
It is possible to adopt a circuit which prevents the

variation in the number of turns in function of
motor current. The problem is to "sense" the current flowing through the motor and to send a
current proportional to it to the sum point of the
error amplifier. The complete circuit which includes, beside the voltage feed-back loop, also a
current feed-back loop, is illustrated in fig. 4.

Fig. 4 - Complete circuit with current feedback
R2
1.2Mfi

3.3 Kll

1:.' ~F

-10V

01.;- 04 { VF";; 1,2V@ I = 2A
trr ..;; 200 ns

In the integrated circuit L292, a current proportional to the mean current drained by the motor
flows between pin 5 and pin 7.
An operational amplifier amplifies the voltage drop
provoked by this current across a 510 .n resistor
and sends a current to the sum point wh ich is
consequently proportional to the mean current in
the motor, the value of which can be made vary by
acting on potentiometer P2. By properly adjusting
P2, a condition can be achieved in which the speed
does not change when the current drained by the
motor varies.

Fig. 5 - Output characteristic of the circuit in
fig. 4

,.00

(,p'mJ

1200

1

/

800

• 10

·8

-.

.

. .,

-

10 Vj(V)

_400

/

The discontinuity around the Origin, which was
present in the previous circuit (fig. 2), is practically
negligible in the circuit shown in fig. 4.
The characteristic n = f (Vi) relevant to the circuit
of fig. 4 is shown in fig. 5, and this characteristic
does not substantially change over the whole range
of currents allowed by the L292 (up to 2A).
In the circuit described above if the motor stall
condition is requested. it is preferable to act on the
inh ibits of the integrated circuit L292, for instance
by grounding pin 13, instead of adjusting potentiometer P1: as a matter of fact, the exact position of
this potentiometer is difficult to obtain, since the
characteristic crosses the axis Vi in one only point
(this means that n is only 0 for a very narrow
interval of Vi).

.800

Im~200mA.;.

2A

.1200
-~600

SYSTEM WITH DIGITAL CONTROL
In this system the speed information is given to the
circuit by a binary code made up of 5 information
bits plus one sign bit, which determines whether
the movement shall be clockwise or counterclockwise. For the circuit implementation, the
integrated circuits L291 (which includes a O/A
converter and two operational amplifiers) and
L292 are used.
A simplified circuit diagram is shown in fig. 6.

103

Fig. 8 - Output characteristic of the circuit in
fig. 7

Fig_ 9 - Translator circuit
.... KRlm

n

(rpm)

2000
A

+--C:J---....-I

1600
1200

800

8~----~=r----~----J

o

Speed code

- 32

- 2.

16

-16

2.

Resistors RA and RB must be high-precision
resistors in order to have output 0 with no 1m
current present. In the practical implementation,
resistors with an accuracy of 5% are used and the
ends of a potentiometer are interposed between
resistors R B and the output to the sum point of
the error amplifier is made through the cursor. The
gain of this current loop is proportional to the
ratio R3/R B . A complete circuit diagram is shown
in fig. 10.

32

I:lm:.200mA

2:lm=lA
-1200
-1600

-2000

S-S872

prevent that the speed vary in function of the
motor load, by adding a current loop in the control
circuit, by using the remaining operational amplifier available in the integrated circuit L291.
Since this amplifier has only the inverting input
available, while the non-inverting input is grounded, a circuit arrangement as schematically shown in
fig. 9 has been adopted in order to have an output
signal referred to ground, given an input signal referred to a reference voltage (in L292) of approximatelyaV.

Since, for reasons of gain, resistor RB must be
27 kn and, if connected to pin 7 of L292, should
have subtracted too much current by thus affecting
the correct operation of L292, it has been connected to pin 11, having the same potential as pin 7.
Consequently, the resistance value between pin 11
and ground has been mOdified, in order to maintain the switching frequency of L292 unchanged.
I n order to have a correct adjustment of potentiometer P1, it is enough to set the speed code (b 1
through bS high) and turn the cursor until the
motor stops.

a

The input versus output characteristic obtained
with the circuit of fig. 10 is indicated in fig. 11.

Fig. 10 - Complete circuit with current feedback

R2

1.2Kll.

2.7Kll

+Vs

R'

39K!l

lREF ~

9

12

b,
b2
b3

b.
b5

01+04 {VF';;;1,2V@I=2A
trr';;; 200 ns
5-4817/1

105

A DESIGNER'S GUIDE TO THE
l290/L291/L292 DC MOTOR SPEED/POSITION
CONTROL SYSTEM
The L290, L291 and L292 together form a complete microprocessor-controlled DC motor
servopositioning system that is both fast and accurate. This design guide presents a description of the system, detailed function descriptions of each device and application information.

The L290, L291 and L292 are primarily intended
for use with a DC motor and optical encoder in the
configuration shown schematically in figure 1. This
system is controlled by a microprocessor, or micro·
computer, which determines the optimum speed
profile for each movement and passes appropriate
commands to the L291, which contains the system's D/ A converter and error amplifiers. The

L291 generates a voltage control signal to drive the
L292 switchmode driver which powers the motor.
An optical encoder on the motor shaft provides
signals which are processed by the L290 tachometer converter to produce tacho voltage feedback
and position feedback signals for the L291 plus
distance/direction feedback signals for the control
micro.

Fig. 1 - The L290, L291 and L292 form a complete DC motor servopositioning system that connects
directly to microcomputer chips.
DIRECTION
SPEED DEMAND
WORD (5 BITS) ~

VELOCITY / POSITION
MODE SELECT

MOTOR CURR ENT
CONTROL VOLTAGE
(

L291
DIGITAL-ANALOG
I-_-,-+_~CONVERTER PLUSI----'-_ _~
ERROR AND
POSITION
AMPLIFIER

MCU

L 292
SWITCHMODE
MOTOR
DRIVER

-POSITION FEEDBACK
ABSOLUTE
POSITION
t+---J--TACHO VELOCITY FEEDBACK
SIGNAL FOR
'-+--+_-+-__
INITJALIZATIO,:.N--Ir""_-1.._....I--, DAC REFERENCE VOLTAGE

\

L290
TACHOMETER
CONVERTER
& REFERENCE
GENERATOR

DISTANCE/DIRECTION
FEEDBACK TO
MICROPROCESSOR

OPTICAL
ENCODER
SIGNALS

107

ONE PULSE
PER ROTATION
SIGNAL

5-5949

THE L290 TACHOMETER CONVERTER

TACHO =

The L290 tachometer converter processes the three
optical encoder signals FTA, FTB, FTF to generate
a tachometer voltage, a position signal and feedback signals for the microprocessor. It also generates a reference voltage for the system's D/A
converter.

dV AB
dt

Analytically, the tacho generation function can be
expressed as:

•

FTA
JFTAJ

_

dV AA
dt

FTB
.--JFTBJ

In the L290 (block diagram, figure 4) this function
is implemented by amplifying FTA and FTB in A1
and A2 to produce V AA and V AB' V AA and
V AB are differentiated by external RC networks to
give the signals V MA and VMB which are phase

Fig. 4 - The L290 processes the encoder signals, generating a tacho voltage and position signal for the
L291 plus feedback signals for the microprocessor. Additionallv, it generates a refence voltage
for the L291 's D/A converter.
OPTICAL ENCODER
SIGNALS

F"TF

FTS

FTA

o

SIF

FEEDBACK
SIGNALS

FO.
MICROPROCESSOR

I

STA

o

TACHO VOLTAGE
OUTPUT TO l291

POSITION

FEEDBACK
TO l291

Fig. 5 - These waveforms illustrate the generation
of the tacho voltage in the L290. Note
that the ripple is fourth harmonic. The
amplitude of TACHO is proportional to
the speed of rotation.

shifted and proportional in amplitude to the speed
of rotation. V MA and V MB are passed to multipliers, the second inputs of wh ich are the sign of
the other signal before differentiation.
The sign ( FTA or ~ is provided by the
J FTB J
J FTA J
comparators CS1 and CS2. Finally, the multiplier
outputs are summed.by A3 to give the tacho signal.
Figure 5 shows the waveforms for this process.

CLOCKWISE
OIRECTION
i
I

ANTICLOCKWISE
DIRECTION

YAA

YAa

This seemingly complex approach has three important advantages. First, since the peaks and nulls
of CSA and CSB tend to cancel out, the ripple is
very small. Secondly, the ripple frequency is the
fourth harmonic of the fundamental so it can be
filtered easily without limiting the bandwidth of
the speed loop. Finally, it is possible to acquire
tacho information much more rapidly, giving a
good response time and transient response.
Feedback signals for the microprocessor, STA, STB
and STF, are generated by squaring FTA, FTB and
FTF. STA and STB are used by the micro to keep
track of position and STF is used at initialization
to find the absolute position.

CS'
CS2
YMA

YMa

csa
c-f---:;k-+-rC=SA_TACHO

Position feedback for the L291 is obtained simply
from the output of A 1.
109

TACHO

Fig. 7 - The L292 switchmode driver receives a control voltage from the L291 and delivers a switch mode
regulated current to the motor.
CURRENT FEEDBACK
FROM MOTOR

' - r-c,,=onJ-..-=:t--,

SENSE
RESISTORS

R52...J
47nF

C
1

----------. 9---

CURRENT

~8~~~~L

:

... VIC>'6,,-_-[R=':t-~

FROM L291

InF

D4

'5.-

5~

ON

59

The L292 incorporates its own voltage reference
and all the functions required for closed loop current control of the motor. Further, it features two
enable inputs, one of which is useful to implement
a power on inhibit function.
The L292's output stage is a bridge configuration
capable of handling up to 2A at 36V. A full bridge
stage was chosen because it allows a supply voltage
to the motor effectively twice the voltage allowed
if a half bridge is used. A single supply was chosen
to avoid problems associated with pump-back
energy.

I n a double supply configuration, such as the
example in figure 8a, current flows for most of the
time through D1 and Q1. A certain amount of
power is thus taken from one supply and pumped
back into the other. Capacitor C1 is charged and
its voltage can rise excessively, risking damage to
the associated electronics.
By contrast, in a single supply configuration like
figure 8b the single supply capacitor participates in
both the conduction and recirculation phases. The
average current is such that power is always taken
from the supply and the problem of an uncontrolled increase in capacitor voltage does not arise.

Fig. 8 - A simple push pull output (a) needs a split supply and the device can be damaged by the voltage
built up on C1. The L292 has a bridge output to avoid these problems. Only one supply is needed
and the voltage across the single capacitor never rises excessively. Moreover, the motor can be
supplied with a voltage up to twice the voltage allowed with a half bridge.

a

b

I
111

Fig. 12 - Complete application circuit of the system.
FROM

ENCOOfR

l

~

~

R,
lKll
100",
100pF"

--114 '--11

_c,

'12

'-iH

..i.e3:

.J...cz

I

~

RZ
R)
IKn
1IU\.
100PFQ

1,6

:, L290

Cl~~

+20V

~t-4J_~

'"

'"oz.

0.211

L292

-~~~ll
3 SC2
4

I

SC3 OAe

5 SC4

FROM

""PROCESSOR

6 SCS
'1

eE2 eEl

!itGN._

12

.LIfI-it'1to

lSIUl

+¥.

GND

·Y.

01 -;- 04 1A Fast Diodes {

Fig. 13 - P.C. board and componentlayout (1: 1 scale)

0:

0
Vl
Vl

w
u
0

0:

"-

"'---

SCl
SC2
SC3
5C4
SCS
SIGN
STROB
STF
STB
STA

u

GND
FTF
FTA
FTB

w

GND

0:

w
0
0

z

-12 V
+12V

113

13
ON(H)

OFFIll

VF .;;; 1.2V @ I = 2A
trr';;; 200 ns

When the system is powered up the mechanical
subsystem may be in any position so the first step
is to initialize it. In applications where the optical
encoder never rotates more than one revolution the daisy wheel of a typewriter, for example this is simply done by rotating the motor slowly
until the STF signal (one-pulse-per-rotation) is
detected.
Where the optical encoder rotates more than once
the 'one-pulse-per-rotation' signal is not sufficient.
An example of this is the carriage positioning servo
of a computer printer. In this case the simplest
solution is to fit a microswitch on one of the
endstops. First the motor is run backwards slowly
until the carriage hits the endstop. Then it moves
forward until the STF Signal is detected. The
beauty of this solution is that the endstop microswitch does not need to be positioned accurately.

ADDING DISCRETE TRANSISTORS FOR
HIGHER POWER
In the basic application, the L292 driver delivers
2A to the motor at 36V. This is fairly impressive for
an integrated circuit but not enough for some applications - robots, machine tools etc. The basic
system can be expanded to accomodate these
applications by adding external power transistors
to the L292. This is preferable to simply adding a
discrete driver stage in place of the L292 because
the L292's current control loop is very useful.
F igu re 15 shows how fou r tra nsistors are added to
increase the current to 4, 6 or 8A, depending on
the choice of transistor. When coupled to the L290
and L291 this configuration appears to the system
asan L292.
The average motor current, 1m , is found from:
Vi 0.044
Im=

APPLICATION CIRCUITS
The complete circuit is shown in figure 12; a suitable layout for evaluation is given in figure 13.
Component values indicated are for a typical
system using a Sensor Technology STRE1601
encoder and a motor with a winding resistance of
5n and an inductance of 5 mH (this motor is
described fully in figure 17). How to calculate
values for other motors is explained further on.

where Vi is the input voltage and Rx is the value
of the sense resistors R7 and R8.
Suitable transistors for this configuration are indicated below:
HAl Vj(VI R x (m!:11

Figure14 explains what each component does and
what happens if it is varied. Maximum and minimum values are also indicated where appropriate.

01,02

03.04

01-04

4

9.1

100

B070B

B0707

2A Fast diodes

6

9.1

65

80908

B0907

3A Fast diodes

8

9.1

50

BOW52A

BOW51A

4A Fast diodes

Fig. 15 - For higher power external transistors are added to the L292. This circuit delivers up to 4A, if
2 BDW51 A and 2 BDW52A are used it can deliver 8A.

12

13
ON >3.2 V

OFF <

2V
5 - 486611

115

DESIGN CONSIDERATIONS
The application circuit of figure 12 will have to be
adapted in most cases to su it the desired performance, motor characteristics, mechanical system
characteristics and encoder characteristics. Essentially this adaptation consists of choosing appropriate values for the ten or so components that
determine the characteristics of the L290, L291
and L292.
The calculations include:
•

Calculation of maximum speed and acceleration;
useful both for defining the control algorithm
and setting the maximum speed.

•

Calculation of RS and R9 to set maximum
speed.

•

Laplace analysis of system to set CS, R 11, R 12,
R13 and R14.

•

Laplace analysis of L292 loop to set the sensing
resistors and C12, C13, R15, R16, R17.

•

Calculation of values for C4 and C6 to set max
level of tacho signal.

•

Calculation of values for R6 and R7 to set D/A
reference current.

•

Calculation of R20 to set desired switching
frequency.

It follows that for a given motor type and control
loop the acceleration can only be increased by increasing the motor current, 1m.
The characteristics of a typical motor are given in
figure 17. From this table we can see that:
KT = 4.3 N cm/A

(6.070z.in/A)

J m = 65 g • cm'

(0.92 x 10- 3 oz.in.s')

We also know that the maximum current supplied
by the L292 is 2A and that the moment of inertia
of the ,STR E 160 1 optical encoder, Joe' is 0.3x 10-'
oZ.ln.s .
The moment of inertia of the load JL, is unknown
but assume, for example, that Joe + JL '" 2 J m .
Therefore the maximum angular acceleration is:
6.07 x 2
a =-- - - - ' . ' 2xO.92x 10- 3
Fig. 17 -

= 6597.S rad/s'

The characteristics of a
motnr.

typical

Motor - Parameter

Value

UB B (V s)

1SV

C. emf. KE

4.5 mV/min'"

No (without load)

3S00 rpm

' 0m (without load)

190 mA

MAXIMUM ACCELERATION

T f (friction torque)

0.7 N em

For a permanent magnet DC motor the acceleration torque is related to the motor current by the
expression:

KT (motor constant)

4.3 N em/A

Amature moment of inertia

65 y. em:

RM of the motor

5.4

LM of the motor

5.5 mH

where:
is
is
is
is

the
the
the
the

motor current
motor torque constant
acceleration torque
total system friction torque

DC

n

MAXIMUM SPEED
The maximum speed can be found from:

The acceleration torque is related to angular acceleration and system inertia by:
Ta = (J m

+ Joe + J L )

a

is
is
is
is

the
the
the
the

moment of inertia of the motor
moment of inertia of the encoder
moment of inertia of the load
angular acceleration.

In a system of this type the friction torque T f is
normally very small and can be neglected. Therefore, combing these two expressions we can find
the angular acceleration from:

a =

KT

n

+ Rm 1m

where:

where:
Jm
Joe
JL
a

V 5 min= 2 V CEsat + RS 1m + Ke

E =

Ke n is the internally generated voltage
(EMF)

Ke

is the motor voltage constant

n

is the rotation speed of the motor.

For example, if Vs min = 20V
2 V CEsat + Rs 1m = 5V (from L292 datasheet)
Rm 1m = 10.SY (Rm = 5.4 n)
we obtain:
Ke

117

n

(E) = 4.2V

Fig. 18 - C4 and C6 value versus rotation speed
for various maximum tacho voltage
values.
G 4937

C.
(nF )

35

1
1

I

I"

There are two conversion factors, Ksp and KfJ.
They link the mechanical parameters (position and
speed) with the equ ivalent feedback signals for the
two loops. The values of Ksp and KfJ are deter·
mined by the encoder characteristics and the gain
parameters of the integrated circuits. The openloop and closed-loop gains are fixed by four ex·
ternal resistors:

I

1

1

1\,1\

30

1
!

H\
1\

25

l\~

1\
,

20

\
,

10

1

\:\

15

~\

I

"\ ,t-..""'-.
I'. l'..."--"""

1
I

I
1
300

'\ I

'\:\

2

600

~ I- ' -

1
,

i

I"i...~ .....l.

::"..1"

-

Vtacho DC. 5,V 6V 1 1 ,,V I
I
3
900

!
,

1200

The analysis is based on the angular speed !1. and
on the motor position fJ. The motor 'IS represented,
to a first approximation, by the current 1m and by
the acceleration torque, T a , which drives an inertial
load J.

sf-

I 1 1
5
6 f(KHz)-FTA
1500 1800 rpm

•

R ref - fixes the reference current (R6 + R7)

•

Rspeed - fixes the speed loop gain (RS + R9)

•

Rpos - controlsthe position loop gain( R12)

•

Rerr - controls the system loop gain (R13).

The stability both of the speed loop and of the
speed-position loop are defined by external components.
The fundamental characteristics of the speed control system can thus be determined by the designer.

LAPLACE ANALYSIS OF THE SYSTEM
Suitable values for the components R11,R12,R13,
R14 and CS can be found from a Laplace analysis
of the system. Figure 19 shows a simplified block
diagram of the system which will be useful for the
analysis.

Tsp is the time constant that determines the dominant pole of the speed loop and is determined by
CS, RS and R9
RS R9
TSp

= C8

RS+ R9

Fig. 19

(*)

See L292 datasheet for an accurate analysis of this block.

List of terms
Laplace variable
Motor torque constant
Acceleration torque
Total system friction torque
Total moment of inertia (J = Joe + J m + J L ).
Speed
119

: Angular position
: Conversion factor that links the
motor rotation speed and the T ACHO
signal.
: Conversion factor that Iinks the
motor position and the V pas signal.

and

If t, tl ll> t, t2 and V 5 = 20V we obtain:
=}

4
1)= 1- - - = 80%
20
In practice the efficiency will be slightly lower as a
results of dissipation in the signal processing circuit
(about lW at 20V) and the finite switching times
(about lW).

0.1 1m max =

f 1m max
Therefore there is a minimum inductance for the
motor which may not always be satisfied. If this is
the case, a series inductor should be added and the
value is found from:
Lseries =

If the power transferred to the motor is 40W, the
80% efficiency implies lOW. dissipated in the
bridge and a total dissipation of 12W. This gives an
actual efficiency of 77%. Since the L292's Multiwatt
package can dissipate up to 20W it is possible to
handle continuous powers in excess of 60W.

f 1m max

POSITION ACCURACY
EFFICIENCY AND POWER DISSIPATION
Neglecting the losses due to switching times and
the dissipation due to the motor current, the efficiency of the L292's bridge can be found from:
t, tl
V sat
t, tl
1)=1---t, tl - t, t2
V5
t, tl - t, t2
Voyer
Vs
where:
V over ~ 2V (2 V SE + RS 'm)
Vsat ~ 4V (2 VCEsat + 3 V BE )
t,

tl = transistor conduction period

t,

t2 = diode conduction period.

The main feature of the system L290, L291, L292
is the accurate positioning of the motor. In this
section we will analyse the influence of the offsets
of the three ICs on the positioning precision.
When the system is working in position mode, the
signal FTA coming from the optical encoder,
after suitable amplification, is sent to the summing
point of the error amplifier (L291). If there were
no offset and no friction, the motor would stop in
a position corresponding to the zero crossing of the
signal FTA,and then at the exact position required.
With a real system the motor stops in a position
where FT A has such a value to compensate the
offsets and the friction; as a consequence there is a
certain imprecision in the positioning. The block
diagram, fig. 20, shows the parts of the 3 ICs
involved in the offsets. First we will calculate the
amount of the offsets at the input of the IC L292
(point A of fig. 20).

Fig.20

L292

L -_ _ _ _ _ _---' 5·5965

121

V 5A ;

350 mV

~

V 6A ;

;

244mV

205

V A; 2.346V
V FTA ;

2.329·

~ .~.
120

15

;0.228V
12.6

encoder, we can note the speed of the motor is
not a linear function of the speed digital code
applied to L291. The diagram of fig. 21 shows
this function and it is evident that the speed increases more than a linear function, i.e. if the
speed code doubles, the speed of the motor becomes more than the double. The cause of this non
I inearity is the d ifferentiator network R4 C4 and
R5 C6 (see tfig. 22) that has not an ideal behaviour
at every frequency.

0.226

Fig. 22

0.4
If we consider an optical encoder with 200 tracksl
turn and a daisy wheel with 100 characters, the
phase between two consecutive characters is
a c ; 7200 , and then the maximum percentage
error we can have is.
€;

~
720

~!-XMA
~.L5

5-5964

• 100 ;:, 4.8%

From this numerical example we can see that the
main contribution to the positioning error is given
by the offset of the TACHO signal (V2A), other
big contributions are given by the input offset
voltage of L292 (V 5A ) and by the voltage necessary to compensate the dynamic friction of the
motor (V6A)' This last term is only determined by
the motor and can also have greater values.
The error we have calculated is the maximum possible and it happens when all the offsets have the
max value with the same sign, i.e. with a probability given by the product of the single probabilities. Considering as an example every offset
has a probability of 1% to assume the max value,
the probability the error assumes the max value is:

Fig. 21
G

"938

speed

IFTA

(rpm )

(KHz)

V.....

800

~.1

600

~

1) V MA ;
I" ;

V AA

sinl"

tg- 1 w R5 C6

2) V MA ;

V AA sin tg-

w ; 2
1

1r

f

w R5 C6

f ; frequency of the signal FT A
This last relation gives the amplitude of the signal
V MA ; it is evident there is not a linear function
between V MA and w, like V MA; Kw and the difference is greater if the product w R5 C6 doesn't
respect the disequation w R5 C6 <1 . , i.e. at high
frequencies.
The phase angle between V MA and V AA should
be 900 and then I" ; 0, in our case I" increases
with the frequency according to the equation
I" ; tg- 1 w R5C6, and influences the amplitude of
the output signal TACHO. In fig. 23 are shown the
waveforms that contribute to generate the TACHO
signal. A and B are the signals V AA and VAS in
phase with the input signals FTA and FTB. C and

2.66

Fig. 23

J#

V

400

1.33

~

B

. . .,v

200

A

0.66

c

/

l/
o

12

16

o

2. 4 speed code

SPEED ACCURACY
If we consider the complete system with L290L291-L292 driving a DC MOTOR with optical
123

5- 5962

ACCURACY DUE TO THE ENCODER

With the guaranteed values on the L291 data sheet
we can calculate for e4 the max value:

e4 =

21 !J.A
1.4 mA

• 100 = 1.5%

Another characteristic of a O/AC is the linearity,
that in our case is better than ± 1/2 LSB. This
value is sufficient to guarantee the monotonicity of
10 , and then of the speed of the motor, as a function of the input digital code. The precision of
± 1/2 LSB impl ies a spread of the speed at every
configuration of the input code of ± 1.61 % referred to the maximum speed. The max percentage
error we can have is then greater at low level speed
(± 50% at min speed) and has its minimum value at
the maximum speed (1.61%).

The amplitude of the signals FTA and FTB determines the value of the TACHO signal. This amplitude must be constant on the whole range of the
frequency. otherwise it is not possible to have a
linear function between the TACHO signal and the
frequency. The spread of the ampl itudes of the
two signals FTA and FTB between several encoder
can be compensated by adjusting the potentiometer R9 (see fig. 12). The phase between the two
signals should be 90°. If there is a constant difference from this value, a constant factor reduction of the TACHO signal results that can be compensated with the potentiometer R9. If the difference from 90° is random, also the reduction of
the TACHO signal is random in the same way.
and by means of R9 it is possible to compensate
only the mean value of that reduction.

125

DESIGNING WITH THE L296
MONOLITHIC POWER
SWITCHING REGULATOR
A cost-effective replacement for costly hybrids, the SGS L296 Power Switching Regulator
delivers 4A at an output voltage of 5.1 V to 40V and includes many popular supply features.
This comprehensive application guide explains how the device operates and how it is used.
Typical application circuits are also presented.

127

Fig. 2 - Principal circuit waveforms of the fig. 1 circuit.

OFF

0,

I

"-'''~'

I

--hd
I

'C

ON
tON

I

OFF
'OFF

h_

T

IQ
10

L

V

j

ON

I

OFF

P "Ipeak

.~Lf--

(l 6It(l
Ipeak ~

a)
..,
b)

..

t

-CS~ILL

c)

"t

n='~:'o)

Jl

d)

L--evF+V O )

g)

- -~cr-~
'J7 - - -V-~
- -

-. V

0

V

~

_6Q

c- C

h)

-~

___ Vo

5-6788

129

=

AIL

ill

where:

power absorbed by the system. Pi is given by po.
plus all the other system losses. The expression of
the efficiency becomes therefore the following:

(6)

T/

=- - - - - - - - - - -

(12)

Po + Psat + Po + PL + Pq + Psw

It follows therefore th at:
.

IL

=-

It)

VF + VO

~--...::...

L

The negative
fact that the
that VF may
OFF time the

DC LOSSES

sign may be interpretated with the
current is now decreasing. Assuming
be neglected against Vo. during the
following behaviour occurs:

Vo

IL=

L

Psat: saturation losses of the power transistor Q.
These losses increase as Vi decreases.
TON
Vo
Psat = Vsat • 10 - T = V sat 10 Vi

(8)

t

where

A Vo T
ulL = - - OFF

(9)

L

and V sat is the power
.

Po: losses due to the recirculation diode. These
losses increase as Vi increases. as in this case
the ON time of the diode is greater.
Vo
Vi - Vo
P O =VFlo - - - = V F lo ( l - - )
Vi
Vi

But. because

= 6.IL-

(Vi -

Vo
\Ii

transistor saturation at current 10

therefore:

6.1~

=

if follows that:

PL : losses due to the series resistance RS of the
coil

L
which allows us to calculate Vo:
TON
TON + TOFF

(15)

TON

V·-I

T

(10)

Pq :

losses due to the stand-bY current and to the
power driving current:

where T is the switching period.

TON
Pq -- V i I' 3q + V i I" 3 q
--

Expression (10) links the output voltage Vo to the
input voltage Vi and to the duty cycle. The relationship between the currents is the following:

where being:

(16)

T

• TON
looc
T

liOC =

(14)

where VF is the forward voltage of the recirculation diode at current 10 •

Vol TON

Vo = Vi

(13)

TON =~
T
Vi

it follows that:

Pq = Vi 1'3q + Vo 1"3q

in which:

at 0% duty cycle
1"3q

= 13q(100%d.c.)

-

13q (O%d.c.)

EFFICIENCY
The system efficiency is expressed by the following
formula:

SWITCHING LOSSES

17"/o=~100

P.w: switching losses of the power transistor:

Pi
where

Po=Volo

Ps w

is the outPut power to the load and Pi is the input

131

= V·I
10

tr + tf
-2T
-

The switching losses of the recirculation diode are

Calculating dvc and equalizing it to 6.vo , it follows
that:
" 2
"
__L_u._I:!.o_
(24)
for + 610
u.Vo =
C(Vj -Vol

L6.1 2

_ _0_

(25)

Power supply

for - 610

CVo
From these two expressions the dependence of overshoots and undershoots on the Land C values may
be observed. To minimize 6.vo it is therefore necessary to reduce the inductance value L and to increase the capacitance value C. Should other auxiliary functions be required in the circuit like reset or
crowbar protections and very variable loads may be
present, it is worthwhile to take special care for minimizing these overshoots, which could cause
spurious operation of the crowbar, and the undershoot, which could trigger the reset function.

The device is provided with an internal stabilized
power supply that, besides supplying the reference
voltage of 5.1 V for the whole system, also supplied
the internal analog blocks.
Special features of the voltage reference are its accuracy, temperature stability and high line rejection.
Through zener-zap trimming, the voltage is within
±2%limits.

Fig. 4 -Pin assignments of the L296.

~

CROWBAR DRIYE
RESET OUTPUT
RESET DELAV

'5

'4
13

,

~ESET

'0

9

8

7
6
5

DEVICE DESCRIPTION
Fig. 4 shows the package in which the device is
mounted and the pin function assignments.
The internal structure of the device is shown in
fig. 5. Each block will now be examined.

-$-~
I

INPUT

OSCILLA.TOR
FEEDBACK INPUT
FREo.UENCV COMPENSATION
GROUND
SYNC. INPUT
INHIBIT INPUT
SOfT-START
CURRENT LIMIT
SUPPLY VOLTAGE

"

OUTPUT
CROWBAR

INPUT

S-SU9f1

Tab conneoct.d to pin 8

Fig. 5 - Block diagram of the L296. In addition to the basic regulation loop the device includes functions
such as reset, crowbar and current limiting.

"

I
S

Q

INHIBIT
fLIP
FLOP _
Q

12
RESET

'3
5-5831,/2

INHIBIT
INPUT

133

RESET INPUT

'4

RESET OUTPUT

I

RESET DELAV

due to the switching delays of the comparator. This
inaccuracy in caused by an excessively short rise
time of the voltage. A capacitance value too high
gives rise to a charging time which is too long compared to the discharging time. An additional inaccuracy cause would be therefore present for the
switching frequency, now due to spread of the
charge current.
Th~ oscillation frequency is given by the following
formula:
1
(26)
fose =

Rose Case

PWM (see fig. 9)
The PWM signal is generated on the comparator
output; the triangular-shaped waveform and the
continuous signal coming from the output of the
transconductance error amplifier are sent to its
inputs. The PWM signal is then transferred to the
driving stage of the output power transistor.

\

SOFT START (see fig. 9)
Soft start is an essential function for correct startup, to prevent stresses and possible breakdown
from occurring in the power transistor and to obtain a monotonically increasing output voltage.
In particular, the L296, as itdoes not have any duty
cycle limitation and due to the type of current lim itation does not allow the output to be forced to a

steady state without the aid of the soft-start facility.
Soft-start operates at the start-up of the system,
after the inhibit has been activated, after an intervention of the current limitation and after the intervention of the thermal protection.
The soft-start function is realized through a capacitor connected to pin 5 which is charged at constant
current ("'" 100flA) up to a value of about VR E F.
DUring the charging time, through PNP transistor
058, the voltage on pin 9 is forced to increase with
the same rising speed as on pin 5. Starting from the
discharged capacitor condition (pin 5 voltage = OV)
the power transistor is in the OFF condition, as the
voltage on pin 9 is smaller than the minimum level
of the ramp voltage. As the capacitor is charged,
the PWM signal begins to be generated as soon as
the error amplifier output voltage crosses the ramp;
the power stage starts to switch with steadily increasing duty cycle. This behaviour is shown in
fig. 10. As soon as the steady condition is reached
the duty cycle sets itself to the right value due to
the effect of the feedback network while the softstart capacitor completes its charging to a value very
close to VREF.
The soft-start effect is determined, apart from the
switch-on time, when the current limitation operates, due to either an overload or a short circuit, to
keep the mean value of the current absorbed by the
power supply low.
Moreover from fig. 11 it may be observed that
since the voltage on pin 9 can decrease under the
minimum ramp level and increase over the maximum level no limitations have been provided on
the duty cycle, which therefore may vary between
o and 100%.

F ig_ 9 - Partial internal schematic showing PWM and soft start blocks_

p~

135

t start-up

=

Css (V r - 0.5V)

three devices shown in the figure. It is anyway difficult to establish an exact maximum number of
devices, as it depends on different conditions.

1550

where Css is the soft-start capacitor and Isso is the
charging current.
Considering as the soft-start time the time required
for the soft-start capacitor to charge from O.2V0.5V) to Vr - 0.5V, gives:

The first consideration concerns the accuracy which
must be achieved and maintained on the oscillation
frequency. Since the bias current on pin 7 is an output current, the sum of all the bias currents must
be much smaller than the capacitor discharge current in close proximity to the lower discharge threshold. Therefore, assuming Cosc
2.2 n F and
Rosc = 4.3 Kn, it follows that:

=

t55 =

C5S (Vr - 1.2)

(28)

Isso

1.2V

substituting Vr from (27) gives:

Vr = E e

-(1 -~)

Assuming that a 10% variation may be accepted,
it follows therefore that the number of synchronizable devices is given by:

Vi

substituting into (28) gives:

tss

~(E

e

= 280,uA

4.3 Kn

( ~~ -1)

N
-1.2)

=

28f.lA
Ibias max

This means that if the overall Ibias is too high it
may modify the discharging time of the capacitor.

1550

The synchronization function is available on pin 7,
this function allows the device to be switched at an
externally generated frequency (leaving pin 11
open), or to mutually synchronize several devices,
using one of them as master and the others as
slave (Fig. 12).

The second consideration concerns the layout
design.
In the presence of a great number of devices to be
synchronized, the lenght of the paths may become
significant and therefore the distributed inductance
introduced along the paths may begin to modify
the triangular shaped waveform, particularly the
rising edge which is very steep. This effect would affect the devices that are physically located more
distant from the master device.

This allows several devices to be operated at the same
frequency, avoiding undesirable intermodulation
phenomena. The number of mutually synchronizable devices is obviously much greater than the

The amplitude of the saw-tooth to be externally
connected must be within 0.5V and 3.5V, values
also representing the maximum swing of the error
amplifier output.

SYNCHRONIZATION

Fig. 12 - In multiple supplies several L296's can be synchronized as shown here.

L296

L296
11

7

esc

Ro se

T

r

L296
7

11

SYNC

esc

SYNC

1

I

1

11

esc

7

SYNC

I

I
5- ~976 J1

Case

137

Fig. 14a -

Current limiter waveforms.

I,

CURRENT

LIMITER
TRIGGERS

LIMIT
THRESHOLD

-

-

n

_____ m n

~ ~ ~G~'RCUIT

r---

-----

C"'"

I!
-"

I

I

:

I

I

•

t

I
I

I

i

I

,

!

.. '~
l! ~

.'I,

I

I

I

m

i

I'

____ -

-

n- -----

-

l'
t: 5ms/div

Fig. 14c - Current at pin 2 when the output is
short circuited.

t

-

is within the limits required to supply the microprocessor correctly.

Fig. 14b - Load current in short circuit conditions (Vi = 40v, L = 300 pH, f = 100 KHz)
I,

n

-----~-:mtfl-~-~-@H--- ---.

CURRENT

I

n

The reset function is realized through the use of 3
pins: the reset input pin 12, the reset delay pin 13
and the reset output pin 14. When the voltage on
pin 12 is smaller than 5V the comparator output is
high and the reset capacitor is not charged because
the transistor 0 is satured and the voltage on pin
14 is at low level, since 02 is saturated, too. When
the voltage on pin 12 goes above 5V, the transistor
o switches OFF and the capacitor can start to
charge through acurrent generator of about 100f.lA.
When the voltage on pin 13 goes above 4.5V the
outPut of the related comparator switches low and
the pin 14 goes high. As the outPut consists of an
open collector transistor, a pull-up external resistance is required. In contrast, when the reset input
voltage goes below 5V, less a hysteresis voltage of
about 100 mV, the comparator triggers again and
instantaneously sets the voltage on pin 14 low,
therefore forcing to saturation the 01 transistor,
that starts the rapid discharge of the capacitor.
Obviously, the reset delay is again present when
the voltage on pin 13 is allowed to go under 4.5V.
To achieve switching operations without uncertainties the two comparators have been provided
with an hysteresis of about 100 mV. In every operating condition the reset switching is guaranteed
with a minimum reset input of 4.75V, the value
required for correct operation of the microprocessor even in the presence of the minimum VREF
value.

RESET

Normally pin 12 is used connected to pin 10. When
it is connected to the output, the function may be
more properly called "'reset"'; on the other hand,
when it is connected through resistive divider, to
the input voltage, the function is called "'power
fail"'. Fig. 16 and fig. 17 show the two possible
usages.

The reset function is of great importance when the
device is used to supply microprocessors, logic devices, and so on. This function differentiates the
SGS L296 device from all previous devices. The
block diagram of the function is shown in fig. 15.
A reset signal is generated when the output voltage

The "'power-fail"' function is used to predict, with
a given advance, the drop of the regulator output
Voltage, due to main failures, which is enough to
save the data being processed into protected memory areas. Fig. 18 summarises the reset function
operation.

t: 5ms/div

139

CROWBAR
This protection function is realized by a completely
independent block, using pin 1 as input and pin 15
as output. It is used to prevent dangerous avervoltages from occurring when the output exceeds 20% of
rated value. Pin 15 is able to output a 100 mA current to be sent to the gate of a SCR which, triggering, short circuits either output or the input.
When connected to the input, as the SCR is triggered a fuse in series connected to power supply
is blown and to bring the system back to operation
manual intervention is requested. Figs. 19, 20 and

21 show the different configurations.
When the voltage on pin 1 exceeds by about 20%
the VREF value the output stage is activated, which
sends a current to the SCR gate, after a delay of
about 5 J1.sec to make the system insensitive to lowduration spikes. When activated, the output stage
delivers about 100mA; when not activated, it drains
about 5 mA and shows a low impedance to the SCR
gate to avoid uncorrect triggering due to random
noise. If the crowbar function is not used connect
pin 1 to ground.

Fig. 19 - Connection of crowbar circuit at output for 5. 1 V output applications.

L296

5-6775

Fig. 20 - Connection of crowbar circuit at output for output voltages above 5.1V.

Fig. 21 - Connection of crowbar circuit to protect input. When triggered, the SCR blows the fuse.

INHIBIT

THERMAL PROTECTION

The inhibit input (pin 6) is TTL compatible and is
activated when the voltage exceeds 2V and deactivated when the voltage goes under 0.8V. As may
be seen in the block diagram, the inhibit acts on
the power transistor, instantaMously switching it
off and also acts on the soft-start, discharging its
capacitor. When the function is unused, pin 6 must
be grounded.

The thermal protection function operates when the
junction temperature reaches 150°C; it acts directly
on the power stage, immediately switching it off,
and on the soft-start capacitor, discharging it. The
thermal protection is provided with hysteresis and,
therefore, after an intervention has occurred, it is
necessary to wait for the junction temperature to
decrease of about 30°C below the intervention
threshold.

141

Fig. 23 - Oscilloscope photographs showing main
waveforms of the figure 22 circuit.
i

r:a = !

IIiii

c= iiiii'I
~

I

szm
iii':!!!!
' II'

~

+

iii::! i:!"I

II II

The third component requiring care is the inductor.
Fig. 22a shows the part numbers of some types used
for testing. Besides having the required inductance
value, the coil has to show a very high saturation
current.
Therefore, a correct dimensioning requires a saturation current above the maximum value of 12L'
the current limit threshold.

U I '

lBIJ
II II '
II

n

ITc:'
.. :1

li.iII

I IIn

I

To achieve high saturation with ferrite cores an air
gap between the two core halves must be provided;
the air gap causes a leakage flux which is radiated in
the surrounding space. To better limit this phenomenon "pot cores" may be used, whose geometry
is such to better limit the flux radiated to the outside.
Using toroidal cores, for instance of Magnetic
58930-A2 moly-permalloy kind, both the requirements of high saturation and low leakage flux are
satisfied. The saturation is softer that the saturation
shown by the ferrite materials. The air gap is not
concentrated in one area, but is finely distributed
along the whole core; this gives the low leakage
flux value.

.

.: ~
W· ~

Id;;;
••

;;;;;;;

==

with trr = 100 ns or more is not recommended;
The photographs in fig. 25 show the effects on the
power current and on the voltage on pin 2, due to
the diodes showing different speeds. Diodes showing
trr greater than 35-50 ns will reduce the overall efficiency of the system, increasing the power dissipated by the device.

..

Careful selection of the external components therefore allows the rea1jzation of a power supply system
whose benefits are significant when compared to a
system with the same performance but realized with
the I inear technique.

t: 2lLs/div
The oscilloscope photographs of the main Waveforms are shown in fig. 23. The output voltage ripple D. Vo depends on the current ripple in the coil
arId on the performance of the output capacitor at
the switching frequency (100 kHz). A capacitor
suitable for this kind of application must have a
low ESA and be able to accept a high current ripple,
at the working frequency. For this application the
Aoederstein EKA series capacitors have been selected, designed for high frequency applications
(>200 kHz) and manufactured to show low ESR
value and to accept high current ripples. To minimize the effects of ESR, two 100 ILF/40V capacitors have been corinected in parallel. The behaviour
of the impedance as a function of frequency is
shown in fig. 24.
Also the selection of the catch diode requ ires
special care. The best choice is a Schottky diode
which minimizes the losses because of its smaller forward voltage drop and greater switching frequency rate. A possible limitation comes from
the backward voltage, that generally reaches 40V
max.
When the full input voltage range of the device is
required in this application it is possible to use
super fast diodes with 35 to 50 ns rated recovery
time, where no more problems on the backward
voltage occur (on the other hand, they show a
greater forward voltage). The use of slower diodes,
143

Fig. 24 - Typical impedance/frequency curves for
EKR capacitors.
10

"-

" ""

~
[a]

•

l"-

"

~

I'\.'" ~

!lOLl!

V"

f"..,

~ ~ ".
~

0.1

-----

•

220121

/~.

..........

t--

• I'

0,01

lk

T

10k

T

lOOk

Linear
Transformer
Heatsink

62 VA
0.8 ·C/W

advantages cooler operation brings.

Switching

If for some reason it is necessary to use higher supply voltages the switching technique, and hence the
L296, becomes even more advantageous.

30VA
11 °C/W

This comparison shows that the L296 switching
regulator allows a saving of roughly 50% on the
LOW COST APPLICATION AND
cost of the transformer and an impressive 80-90% PREREGULATOR
on the cost of the heatsink. Considering also Fig. 26 shows the low cost application of a 4A and
the extra functions integrated by the L296 the Va = 5.1Vpowersupply.Aminimumamountof
total cost of active and passive components is essential external components is required, which
roughly the same for both tYpes.
are necessary for correct operation. It is impossible
Finally, it is important to note that a lower power to save other components, specially the soft-start
dissipation means that the ambient temperature in capacitor. Without soft-start, the system cannot
the regulator enclosure can be lower - particularly reach the steady state and there is also a serious risk
when the circuit is enclosed in a box - with all the of damaging the device.

Fig. 26 - A minimal component count 5.1V/4A supplV.
1000,.,F/50V

r

11

2.2

I"F

300pH
4.3

.S.1V

KQ

9

10

I~

12
14
13

This application is very well suited not only as a
low-cost power supply, but also as pre-regulator for
post-regulators distributed in different circuit points,
or even on different boards (Fig. 27). The post-regulators may be selected among the low-drop tYpes,
like L4805 and L387 for example, still obtaining
a high efficiency, combined with an excellent regulation. The use of L387 device allows us to use also
the reset fu nction, useful to power a micropocessor.

values and high reliabilitY. The input filter capacitors must not be neglected because they have to
show excellent features, too, having to supply a
pulsed current, required by the device at the
switching frequency. The current ripple is rather
high, greater than the load current. For this application, two parallel connected 33001lF/50V EYF
(ROE) capacitors have been used.

POWER SUPPLY WITH MAINS
SWITCHING PREREGULATOR

POWER SUPPLY COMPLETE WITH
TRANSFORMER
Fig. 28 shows a power supply complete of transformer, bridge and filter, with regulation on the
output voltage from 5.1 V to 15V.
As already stated above, the output capacitors have
to show some speciale features, like low ESR and
high current ripple, to obtain low voltage ripple

When it is desirable to eliminate the 50/60 Hz
transformer - in portable or volume-limited equipment- a mains preregulator can be added to reduce
the input voltage to a level acceptable for the L296.
In this case the pre-regulator circuit is connected to
the primary of the transformer which now operates
at the switching frequency and is therefore smaller
and lighter.

145

Fig. 28A - A multiple output supply using a switching preregulator rather than a mains transformer.

POWER SUPPLY WITH 0 - 30V ADJUSTABLE VOLTAGE

ing through the divider may be varied. The new
equivalent circuit is shown in fig. 31.

When output voltages lower than 5V are required,
the circuit shown in fig. 29 may be used.
Calibration is performed by grounding the P1 slider. Acting on P2, the current which flows through
the 10 kO resistor is fixed at approximately 2.5mA
to obtain an output voltage of 30V. The equivalent
ci rcu it is sh own in fig. 30.

Reducing the current flowing, also the voltage drop
across the 10kO resistance is reduced, together
with Vo. When the current reaches zero, it follows
that Vo = VREF .. When the voltage on the slider
of P1 exceeds VREF, the current start to flow in
opposite direction and Vo begins to decrease below
5V.

Acting now on the slider of P1, the current flow-

When 11 x 10KO

= VREF

it follows that Vo

Fig. 29 - Variable 0-30 V supply illustrating how output voltages below 5.1 V are obtained.

147

= O.

Fig. 33 - Microcomputer supply with 5V, -5V, 12V and -12Voutputs.
Vi =JSV

FUSE

0----1~C~)>-~--~~--'
hllOO"F
50V
EVF

I

"

L296

..J.. *

L~I~2
.
lN5622

- 5.1 V

I

O.2A

100 }JF
EKR

+5.1"

L-------~~----~~------~~~)4A

1 Kll
RESET

----Q·-<~5-K-Il.------------------,N~H~B IT

TO PIN 6

'-ll

470/..1F

:r

11

*

SGS8R20 OR

BYW80

I

'IC5622

-12V

~Lo.2A
6.2Kll

T1OO}JF
...,EKR

L-_____+--+____---;

~21.~~

l
The two devices are mutually synchronized not to
give rise to intermodulation which could generate
unpleasant noise and, at the same time, a further
component saving is achieved.
The crowbar function is implemented on both 5V
and 12V outputs, using a single SCR connected to
'the input. The latter, by discharging to ground the
electrolytic filter capacitors, blows the fuse connected in series with the devices power supply. In
this way, should a faulty be present on either of
the main outputs, the supply is switched off for
whole system.

lOODj.JF

25V
EKR

To inhibit both the devices with a single input signal, it is possible to connect the two inhibit inputs
(pin 6) together; the 5K.!1 resistance is used when
the inhibit input is left open. If this input is not
used it must be grounded.
As may be noted in the diagram, to obtain the two
auxiliary voltages is very simple and cost-effective.
It is suggested that the diodes are fast types (trr<
50 nsec); should slower diodes be required some
more turns have to be added to the auxiliary winding.

149

MOTOR CONTROL
The L296 is also suitable for use in motor controls
applications. Fig. 36 shows how to use the device
to drive a motor with a maximum power of about
100W and provided with a tachometer generator
for a good speed control.

The circuits shown in fig. 38 and fig. 39 show how
current limitation may be realized in two different
ways: through a sensing resistor connected in series
with the collector of the external power transistor
or through a current transformer.

HIGHER CURRENT REGULATORS
It is possible to increase the output current to the
load above 4A through the use of an external power
transistor. Fig. 37 shows a suitable circuit. The frequency is around 40 kHz to prevent the device from
loosing excessive power due to switching on the
external power.

In the first case, the sensing resistor is a low value
resistor able to withstand the maximum load current required. The V CE of the power transistor is
higher than its V CEsat; when the resistor is connected in series to the collector V CE is reduced; consequently since the overall dissipated power is constant, the power dissipated by the sensing resistor is
subtracted from that dissipated by the power transistor. The values indicated in figs. 38 and 39 realize adjustable current limitation for load currents
around 10A.

Fig. 36 - With a tacho dynamo supplying feedback the L296 can be used as a motor speed controller.

+Vi
2x2200~F

I

L296
7-11

5
R2
'.7fJF
IOKll.

I
5- 6767

Fig. 37 - The output current may be increased by adding a power transistor as shown in this circuit.

11

IOKfl
+121/

r

33nF

VHE2401

2100P

151

2:

Fig. 40 - A step-up converter using a power MOS transistor.

D2

Vo=35V

1-------t'~_._-_._JY"Y'-~-I~_._-.__oO.5A

r

2x100,.,F

C7

40V

R7
33Kll

5-61110

Fig. 41 - Basic schematic for step-up configurations.

In this configuration, unli ke the step-down configuration, the peak current is not strictly related
to the load current. The energy stored in the coil is
successively discharged across the load when the
transistor switches OF F. To calculate the 10 load
current, the following procedure may be used:

~
2

L

I~eak = Vo

LAYOUT CONSIDERATIONS
Both for linear and switching power supplies when
the current exceeds 1 A a careful layout becomes
important to achieve a good regulation. The problem becomes more evident when designing switching regulators in which pulsed currents are over imposed on dc currents. In drawing the layout, therefore, special care has to be taken to separate ground
paths for signal currents and ground paths for load
currents, which generally showa much higher value.
When operating at high frequencies the path length
becomes extremely important. The paths introduce
distributed inductances, producing ringing phenom·
ena and radiating noise into the surrounding space.
The recirculation diode must be connected close to
pin 2, to avoid giving rise to dangerous extra negative voltages, due to the distributed inductance.
Fig. 43 and fig. 44 respectively show the electric
diagram and the associated layout which has been
realized taking these problems into account. Greater
care must be taken to follow these rules when two
or more mutually synchronized devices are used.

10 T

L I~eak
2Vo T
For a greater output power to be available, the
internal limitation must be replaced by an external
circuit to protect the external power devices and to
limit the current peak to a convenient value. A dual
comparator (LM393) with hysteresis is used to
avoid uncertainties when the current limitation
operates. The electric diagram is shown in fig. 42.

153

Fig. 43 - Typical application circuit showing how the signal and power grounds are connected.
RESET

R6
Vi

Rl

3

14

10

12

L 1

13
Cl
10,..F
63Y

R2
100

7

K.ll

C2

R8

C3

2.2,..F 2.2nF

G~O

R7

11

4.7

R3
43

Kn

Kn

~~~----------------+-----------------------------~--------~~~L-~GND
5-628012

INHIBIT

C7, C8 : EKR (ROE)

Suggested Inductor (l1)
Core Type
Maanetics 68930 - A2MPP
Thomson GUP 20x16x7
Siemens EC 36/17/10
(B6633& - G0500 - X127)

No
Turns

Wire
Geuge

Air
Gep

43
65

1.0mm.
0.8mm.

1 mm.

40

2 x 0.8 mm.

-

VOGT 250 IlH Toroidal coil, part number 5730501800

-

Resistor values for
standard output voltages
Vo
12V
15V
18V
24V

R8
4.7
4.7
4.7
4.7

kn
kn
kn
kn

R7
6.2
9.1
12
18

kn
kn
kn
kn

Fig. 44 - A suitable PCB layout for the figure 43 circuit realized in accordance with the suggestions in
the text (1 : 1 sea/e).

G NO l

,----t....

155

Fig. 50

Fig. 52 shows the trend of the temperature as a
function of the distance between two dissipating
elements whose dissipated power is fairly different
(ratio 1 to 4). This graph may be useful in application with two L296 synchronized.

Fig. 51

Te (OC)
70

65

50

-7

-10

- 5

:-3-2-1
'4

2

6

d (em)

7

s-

8

9

5516

Fig. 52

--T
- - - T~

150
140
130
120
,A

Pd: 2.5W

,

1-----__ ...... _-I

1

I

,

...... ---

70

60

I

-10

8

-5:,

---,

B

--'
--?'----,

I

,5

d (em)

''4

157

10
S - SS17

10

In the application a series RC network is recommended which gives high system gain at low frequency to ensure good precision and mains ripple rejection
and a lower gain at high frequencies to ensure stability of the system. Figure A2 shows the gain and
phase curves of the uncompensated error amplifier.
The amplifier has one pole at about 7 kHz and a
phase shift which reaches about - 90" at frequencies around 1 MHz.
The introduction of a series network RC Cc between the output and ground modifies the circuit
as shown in figure A3.
Figure A4 shows the gain and phase curves of the
compensated error amplifier.
Fig. A3 - Compensation
amplifier.

network

of the error

The DC gain must be considered equal to
Ao = gm Ro
PWM block and output stage:
GpWM

=~
Vet

LCFILTER:

GL

1 + s C' ESR
- ..,,------C - s2 LC + S C ESR + 1

where ESR is the equivalent series resistance of the
outPut capacitor which introduces a zero at high
frequencies, indispensable for system stability. Such
a filter introduces two poles at the angular frequency.
Wo = -------

v"LC

Refer to the literature for a more detailed analysis.
Feedback: consists of the block labelled

a = 1 when
and

Vo

R2

a= - - R1 + R2

Fig. A4 - Bode plot showing gain and phase of
compensated error amplifier.
- - - UNCOMPENSATED
- - COMPENSATED

,,

=VREF

a

(and therefore Vo

=5.1VI

when Vo >VREF

Fig. A5 - Block diagram used in stability calculation

VREF

,
5-6852
oJ)

~

ffi
~k-----~------~----~~----- 135

90

~

~

To analyse the stability we will use a Bode diagram.
The values of Land C necessary to obtain the requi red regulator outPut performance, once the frequency is fixed, are calculated with the following
formulae:

if
L
5-6857

C

CALCULATING THE STABILITY
For the stability calculation refer to the block diagram shown in figure A5.

(Vi -Vol Vo
Vi f 61L
(Vi -Vol Vo
8 L f2 6Vo

Since this filter introduces two poles at the angular
frequency

1

= vi LC

The transfer functions of the various blocks are rewritten as follows.

Wo

The simplified transfer function of the compensated
error amplifier is:

we place the zero of the Rc
place:

G EA

=

gm Zc

=

1 + s Rc Cc

gm ---=--~
s Cc

(g

1

---I

m - 2500

159

Wz

1

=----Rc Cc

c.: network in the same

generally found distributed along the strips of the
printed circuit board.
Fast switching of the power transistors tends to
cause ringing and oscillations as a result of the
parasitic elements. The use of a diode with a fast
reverse recovery time (trrl contributes to a reduction in the noise flowing by the current peak
generated when the diode is reverse biased.

Fig. B1 - EMI measurements with a capacitor connee ted across the primary transformer
with screen grounded (A) and floating (B)

80

Radiated interference is usually reduced by enclosing the regulator in a metal box.

70
60

To reduce conducted electromagnetic interference
(or radio frequency interferences - RF I) to the
levels permitted a suitably dimensioned filter is added on the supply line. The best method, generally,
to reduce conducted noise is to filter each output
terminal of the regulator. The use of a fixed switching frequency allows the use of a filter with a relatively narrow bandwidth. For off-line switching regulators this filter is usually costly and bulky. In
contrast, if the device is supplied from a 50/60 Hz
transformer the R F I fi Iter problem is greatly reduced.
Tests have been carried out at the laboratories of
Roederstein to determine the dimensions of a mains
supply filter which satisfies the VDE 0871/6.78,
class B standard. The measurements (see figs. B1
and B2) refer to the application with the L296 supplied with a filtered secondary voltage of about 30V,
with Vo = 5.1 V and 10 = 4A. The switching frequency is 100 kHz.

50
40
30
20
10
10KHz

30

100

Fig_ B2 - EMI results with the addition of an inductive filter on the mains input.

Figure B1 shows the results obtained by introducing on the transformer primary a 0.01 JJ.F/250Vclass X capacitor (type ERO F1772-310-20301. To
reduce interference further below the limit set by
the standards an additional inductive filter must be
added on the primary of the transformer.
Figure B2 shows the curves obtained by introducing
this inductive filter (type ERO F1753-210-124).

90
80
70
60
50
40
30
20

Measurements have also been performed beyond
30 MHz; the maximum value measured is still well
below the I imit curve.

161

10
10KHz

30

100

300

lMH'l.

10

30

DESIGNING MULTIPLE-OUTPUT
POWER SUPPLIES WITH THE L296 AND L4960
Multiple output supplies can be realized simply and economically using the SGS L296 and L4960 high
power switching regulators. This note describes several practical circuits of this type.

Most of the switching regulators produced today
have multiple outputs. The output voltages most
frequently used - at least for powers up to 50W are +5V -5V, +12V and -12V. In these supplies the
5V output is normally the output which delivers
the highest current and requires the highest precision. For the other voltages - particularly the
negative outputs - less precision (±5% ± 7% ) is
usually sufficient. Often, however, for high current
12V outputs better stabilization and greater
precision (typically ±4% - the output tolerance of
an L7800 series linear regulator) are required.
Multiple output supplies which satisfy these requirements can be realized using the SGS L296 and
L4960 high power switching regulator ICs, Several
practical supply designs are described below to
illustrate how these components are used to build
compact and inexpensive multi-output supplies.

DUAL OUTPUT 15W SUPPLY
Vol = 5V/3A, V02 = 12V/150mA
A single L296 is used in this application to produce
two outputs. The application circuit, Figure 1, illustrates how the second output (12V) is obtained
by adding a second winding to the output inductor. Energy is transferred to the secondary
during the recirculation period when the internal
power device of the L296 is OFF.
Since the 12\( output is not separated from the 5V
output fewer turns are necessary for the second
winding, therefore less copper is needed and load
regulation is improved.
In applications of this type it is a good rule to
ensure that the power drain on the auxiliary output is no more than 20-25% of the power delivered
by the main output.

163

Fig. 2 - Dual output DC-DC converter (5V/1.5A, 12V/100mA)
1 K.ll.

lnF

+12V

1000.uF
+15V

to

35 V

~

02

• N2

01

L4960

:r

I

SGS8R20
OR
BYWBO

220!-,F
I.OV
EKR

33nF
5-8051/1

Transformer: magnetics 58206, N1 = 30 turns, N2 = 40 turns

TABLE 2
Parameter
Output voltage
101 = 1.5A

VI = 25V
102 = 100mA

Output ripple

Vol

V02

Unit

5.050

12.010

[V]

50

30

[mV]

Line regulation
101 = 1.5A

15V E;; VIE;; 35V
102 = 100mA

7

75

[mV]

Li ne regu lation
101 = 500mA

15VE;;ViE;;35V
102 = 50mA

7

60

[mV]

Load regulation
101 = 0.5A ~ 1.5A

VI = 25V
102 = 100mA

3

100

[mV]

Load regulation
101 = 500mA

Vi = 25V
102 = 50mA

100mA

0

55

[mV]

Load regulation
101 = 1.5A

Vi = 25V
102 = 50mA

100mA

0

50

[mV]

Efficiency

Vi = 25V
101 = 1.5A
102 = 100mA

~

~

78

%

used.

TRIPLE OUTPUT 15W SUPPLY
Vol = 5V/3A, V02= 12V/100mA, Voa= -12V/100mA
Figure 3 shows how to obtain two auxiliary outputs (± 12V) which are isolated from the 5V
output. For this output power range an L296 is

To ensure good tracking of the 12V and -12V
outputs the secondary outputs in this application
should be bifilar wound.
This circuit operates at 50KHz and gives the performance indicated in Table 3.

165

Fig. 4 - Triple output DC-DCconverter(5V/1.5A 12V/50mA, -12V/50mA)
BYV 28-50
02

+15V to 35V

L-~!-----~--n-12V

L4960
~--------+-----------~+5V
220)JF

r

EKR
40V
5-605912

TABLE 4
Parameter

Output Voltage
101 =1.5A

VI = 25V
102 = 103 = 50mA

Output ripple

Vol

V02

V03

5.040

12.020

-12.020

[V)

60

30

30

[mV)

Unit

Line regulation
101 = 500mA

15",V,,,,35V
102 = 103 = 50mA

5

80

80

[mV)

Line regulation
101 = 1.5A

15",V,,,,35V
102 = 103 = 50mA

4

60

60

[mV)

Load regulation
101 = 0.5 -+ 1 .5A

VI = 25V
102 = 103 = 50mA

5

120

120

[mV)

Load regulation
10 = 1.5A
103 = 20 -+ 50mA

Vi = 25V
102 = 50mA
0

15

50

[mV)

Load regu lation
101 = 1.5A
102 = 20 -+ 50mA

Vi = 25V
103 = lOOmA
0

50

15

[mV)

70

Efficiency

167

%

of cost. DC-DC converters can, in fact, be realized
even by designers with little e.xperience and allows
the convenience of working' with low voltages,
Designing power supplies in the 30-40W range is Off-line switching supplies ~re only preferable
becoming increasingly difficult because it is here when the weight and size of t'Re mains transformer
that there is the greatest need to maintain per- in a DC-DC converter would be excessive.
formance levels and reduce costs. The application
proposed here is very competitive because it In this circuit, figure 6 two devices are used, an
exploits new ICs to reduce size, number of com- L296 and an L4960. The L296 is used, to supply a
5V output with a current of 3A and the auxiliary
ponents and assembly costs.
-5V /1 OOmA output and the L4960 is used to proThis solution, the DC-DC converter, compares very vide the 12V /1.5A output and the auxiliary -12V /
favourable with off-line switching supplies in terms 1OOmA output.

30W DC-DC CONVERTER

Fig. 6 - Multioutput DC-DC converter with L296 and L4960 (5V/3A, 12V/1. 5A, -12V/100mA, -5V/100mA)
20V :5.: Vi:$ 40V

:r

470

,.,F

Fig. 8
RESET

OUT

12

L296

I
CALCULATING THE POWER FAIL TIME the time when the input voltage falls to the miniThe 'power fail time' is defined as the time from
when the power fail output (pin 14) goes low to

mum level required to maintain the regulated
output (see Figure 9). From this definition we can
evaluate the energy balance.

Fig. 9

Vi

t•

I

I
I

p.f. WAVE FORM
(PIN 14)

"
"1

t PF

k

'I

i

r-----------------~

I

I
I

I
I
I

--t---t-OELAY RESET

~-807.4

Equating the expressions (1) and (2) gives:

The energy which the filter capacitor C supplies
to the operating device while it discharges is:
(1 )

The load drains a power of Po = Vo 10. Taking into
consideration the average efficiency 1) (derived
with the input between VI and V2), the power to
be supplied at the input of the device is:
P02 =

1/2 C (V I 2 ..: V 22) '=

~

• tPF

1)

where VI is the input voltage at which the voltage
on pin 12 reaches 5V (through the divider RI/R2);
V2 is the maximum input voltage below which
the device no longer regu lates.
Rearranging this expression to obtain C:

Po
1)

171

DUAL REGULATORS SIMPLIFY
MICRO SYSTEM SUPPLY DESIGN
Combining two 5V regulators and a reset circuit on a single chip, special purpose regulator
chips simplify the design of power supplies for microprocessor systems incorporating battery
backup RAMs or shadow-type NV RAMs.

Power supplies for microprocessor systems are
often complicated by the need to take care of the
special requ irements of non-volati Ie read/write
memory. Where battery backup CMOS RAMs are
used, for example, it is important to ensure that
the RAMs are disabled when the primary supply is
removed. And when shadow-type NV memory is
included the backup transfer must be initiated and
completed when the supply is interrupted. Designed
specifically for such applications, the SGS L4901,
and L4902 dual voltage regulators combine two 5V
regulators plus a reset circuit on a single chip, simplifying the designer's task.

with externally programmable timing which depends on the input voltage and the output of the
V 1 regu lator.
Functionally, the two devices are identical except
that the L4901 has separate inputs to the two
regulators and the L4902 has a common input plus
a disable input which controls the V2 output. (Fig.1)
Generally the V1 regulator is used to supply circuits which must be powered continuously volatile memory, a time-of-day clock and so on while the V2 output supplies other 5V circuits
which may be powered down when the equipment
is inactive.

Assembled in the SGS Heptawatt [TM] 7-lead
package, the L4901 and L4902 contain separate
voltage regulators rated at 5V/300mA (the "V1"
output) and 5V /400mA (the "V2" outputl.
Both the V1 and V2 regulators have an output
voltage precision of ± 2% and include protection
against output short circuits and 60V input transients. Also included on the ch ip is a reset circuit

The V1 output features a very low leakage current
at the output - less than 1ILA - to allow the use
a backup battery. The V1 regulator also features a
low quiescent current at the input (O.6mA typical)
to minimize battery drain in applications where the
V1 regulator is permanently connected to a battery
supply.

Fig. 1a - TWO 5V OUTPUTS - The L4901 Dual
Regulator provides 300mA and 400mA 5V outputs
and includes a microprocessor reset function.
This device is ideal for microprocessor systems
with battery backup or shadow RAM.

Vl IN

220,F

±

l4901

1-1________t-,=--oVl OUT

Fig. 1b - DISABLE INPUT-The L4902 is similar
to the L4901 but also features a disable input for
the V2 regulator.

L 4902

O'N_~~+____.____l

V2 IN

DISABLE
DISABLE

THERMAL
PROTECTION

173

1

Vl0UT

Fig. 4 - LOW LEAKAGE at the V1 output makes the L4901 ideal for battery backup operation.

IN1

~Y

O.22J.JF

.I

REG. 1

I
BACKUP
BATTERY

J.JP(3B75-2B75)

VID

OUT2

IN 2

WITH BATTERY

REG. 2

BACKUP

1 to10J.JF
4.7!JFI

I

RAM

RESET

Voo
CT .....

RESE TOUT

10nF I

RESET
5_1771

Fig. 5 - STANDBY - The L4902 can be used in applications where the supply is connected permanently
and the disable function used to turn off non-essential circuits in the standby state.

IN1

~TTERY

.:c.

4.7J.lF

1

7

REG.1

J.
I

!1!JF

3 V020lS

~

6

REG. 2

OUT 2

~ 1lolO1J1'

I
C~
I

Voo

OUT 1

I

J
I

Voo
OUT PORT

l

CMOS
CLOCK

IN PORT

CMOS
,",P WITH
VOLATILE
RAM

Voo
OTHER
LOGIC

~5Y

5

10nF

RESET OUT

1

RESET

5-7843

It is important to make sure that the RAMs are
disabled because the lithium cells used as backup
batteries have a high internal resistance. If the
RAMs were not forced into the low consumption
standby state the battery voltage could drop so low
that memory contents are corrupted. Moreover, to
prevent latch up, no input of a CMOS RAM should
ever be higher than the supply vol tage.

supply is removed, a function which the L4902's
reset output can perform. Since the L4902's reset
function depends on the INPUT voltage the power
fail condition is sensed early enough to guarantee
that the backup transfer will be successful.

IDEAL FOR SHADOW MEMORIES

I n figure 7 the reset output is forced low when the
input voltage falls below 6.3V or when the V1 output goes below 4.8V. This allows 10l-ls for the
backup transfer (with 10l-lF capacitors) which is
more than sufficient.

Another interesting application for the L4902 is
supplying a shadow-ram microcomputer chip like
the SGS M38SH72 where a fast non-volatile
memory is backed up on-chip by a slow EEPROM
(figure 7). For these chips it is important to ensure
that the backup command is generated when the

Similarly, the L4902 can be used with shadowtype RAMs such as the Xicor X2201. I n the figure
8 circuit a capacitor on the V1 input ensures that
the X2201 is powered during the transfer operation. When the input voltage is removed or goes
below 6.3V the L4902's reset output, connected to

175

Fig. 8 - SHADOW RAMs - The L4901's reset function also serves in svstems using shadow tvpe NV
RAMs like the X2201 to ensure that the backup transfer is executed correctlv.

VI

:r ",r

INI

Vs

OUT I 7

680

X2201

Ilo",r
L4901
OUT 2

IN2

~

6

S

DATA

ADDR£SS

IIOf'F
8085
R£S£T 5

CT

lonF

I

TRAP

GND

,

S_BOilS '1

Fig. 9 - With a CMOS Schmitt trigger and a few components a watchdog function can be added for
critical applications.

~----------------------------------~~------~~VDD

4.7}J F
~------~-----4------+-~----------------~RSTfP

rI
I
I

-------------1

OUTPUT
PORT

10KJl

JU1Jl
5-9363"

177

UC3842 PROVI DES LOW-COST
CURRENT-MODE CONTROL

The fundamental challenge of power supply design
is to simultaneously realize two conflicting objectives: good electrical performance and low cost.
The UC3842 is an integrated pulse width modulator (PWM) designed with both these objectives
in mind. This IC provides designers an inexpensive
controller with which they can obtain all the performance advantages of current-mode operation.
In addition, the UC3842 is optimized for efficient
power sequencing of off-line converters and for
driving increasingly popular POWERMOS.
This application note gives a functional description
of the UC3842 and suggests how to incorporate
the IC into practical power supplies. A review of
current-mode control and its benefits is included
and methods of avoiding common pitfalls dis-

cussed. The final section presents designs of two
power supplies utilizing UC3842 control.

CURRENT-MODE CONTROL
Figure 1 shows the two-loop current-mode control
system in a typical buck regulator application. A
clock signal initiates power pulses at a fixed frequency. The termination of each pulse occurs
when an analog of the inductor current reaches a
threshold established by the error signal. In this
way the error signal actually controls peak inductor current. This contrasts with conventional
schemes in which the error signal directly controls
pulse width without regard to inductor current.

Fig. 1 - Two-loop current-mode control system

~-1819

CLOCK
"ERROR

,.....,,....,,.....,

"SENSE

.....J LJ LJ L

LA1CH

-"L.Il...fL

OUTPUT

179

Current limiting is simplified with current-mode
control. Pulse-by-pulse limiting is, of course,
inherent in the control scheme. Furthermore, an
upper limit on the peak current can be established
by simply clamping the error voltage. Accurate
current limiting allows optimization of magnetic
and power semiconductor elements while ensuring
reliable supply operation.
Finally, current-mode controlled power stages can
be operated in parallel with equal current sharing.
This opens the possibility of a modular approach
to power supply design.

FUNCTIONAL DESCRIPTION
A block diagram of the UC3842 appears in Figure'4. This IC will operate from a low impedance
DC sou rce of 10V to 30V. Operation between 10V
and 16V requires a start-up bootstrap to a voltage
greater than 16V in order to overcome the undervoltage lockout. Vce is internally clamped to 34V
for operation from higher voltage current-limited
sources (Icc';; 30mA).

Under-Voltage Lockout (UVLO)
This circuit insures that Vec is adequate to make
the UC3842 fully operational before enabling the
output stage. Figure 5a shows that the UVLO turnon and turn-off thresholds are fixed internally at
16V and 10V respectively. The 6V hysteresis
prevents Vee oscillations during power sequencing.
Figure 5b shows supply current requirements.
Start-up current is less than 1mA for efficient
bootstrapping from the rectified input of an offline converter, as illust,'ated by Figure 6. During
normal circuit operation, Vee is developed from
auxiliary winding WAUX with Dl and CIN. At
start-up, however, CIN must be charged to 16V
through RIN. With a start-up current of 1mA, RIN
can be, as large as 100kn and still charge CI N when
VAC == 90V RMS (low line). Power dissipation in
RIN would then be less than 350mW even under
high line (VAC == 130V RMS) conditions.
During UVLO, the UC3842 output driver is biased
to a high impedance state. However, leakage currents (up to 10ILA), if not shunted to ground, could
pull high the gate of a POWERMOS. A 100kn shunt,
as showing in Figure 6, will hold the gate voltage
below 1V.

Fig. 5 (a) - Under-voltage lockout and (b) supply current requirements.

ICC

Vi

10V 16V

(a)

5_7707

(b)

Fig. 6 - Providing power to the UC3842

01

Vi

UC3842
OUT

GNO

f---.--\"-V
lOOKn

5-1821

181

unity (OdB) at f '" fswitchlngt4. This technique
insures converter stability while providing good
dynamic response.
Continuous-inductor-current boost and flyback
converters each have a right-half-plane zero in their
transfer function. An additional compensation pole
is needed to roll off loop gain at a frequency less
than that of the RHP zero. Rp and Cp in the circuit of Figure lOb provide this pole.
The EtA output will source O.5mA and sink 2mA.
A lower limit for Rf is given by:
R
f(MINI"

VElA QUT(MAXI- 2.5V
O.5mA

6V - 2.5V
O.5mA

7kn

EtA input bias current (2)lA max) flows through
RI. resulting in a DC error in output voltage (V o )
given by:
6. VO(MAX) = (2)lA) RI
It is therefore desirable to keep the value of Ri as
low as possible.
Figure 11 shows the open-loop frequency response
of the UC3842 EtA. The gain represent an upper
limit on the gain of the compensated EtA. Phase
lag increases rapidly as frequency exceeds 1MHz
due to second-order poles at - 10MHz and above.

Fig. 9 - UC3842 error amplifier

5-7708

Fig. 10 - (a) Error amplifier compensation addition pole and (b) needed for continuous
inductor-current boost ad flyback.

Fig. 11 - Error amplifier open-loop
response

frequency

G 'P88

PHASE
(0)

Gv
(dB)

RI

0

-45

-90

-135

(a)

2.5OV

-180

10

100

lK

10K

lOOK

1M

t(Hz)

Current Sensing and Limiting

(b)

The UC3842 current ser;;e input is configured as
shown in Figure 12. Current-to-voltage conversion
is done externally with ground-referenced resistor
RS. Under normal operation the peak voltage
across RS is controlled by the EtA according to

2.S0V

183

PWM Latch

Figures 15-17 show suggested circuits for driving
POWERMOS and bipolar transistors with the
UC3842 output. The simple curcuit of Figure 15
can be used when the control IC is not electrically
isolated from the power MOS. Series resistor Rl
provides damping for a parasitic tank circuit formed by the power MOS input capacitance and any
series wiring inductance. Resistor R2 shunts output
leakage currents (101lA maximum) to ground when
the under-voltage lockout is active. Figure 16
shows an isolated power MOS drive circuit which is
appropriate when the drive signal must be levelshifted or transmitted across an isolation boundary.
Bipolar transistors can be driven effectively with
the circuit of Figure 17. Resistors R 1 and R2 fix
the on-state base current. Capacitor Cl provides a
negative base current pulse to remove stored charge
at turn-off.

This flip-flop, shown in Figure 4, ensures that only
a single pulse appears at the UC3842 output in any
one oscillator period. Excessive power transistor
dissipation and potential saturation of magnetic
elements are thereby averted.

Shutdown Techniques
Shutdown of the UC3842 can be accomplished by
two methods; either raise pin 3 above 1 V or pull
pin 1 below 1 V. Either method causes the output
of the PWM comparator to be high (refer to block
diagram, Figure 4). The PWM latch is reset dominant so that the output will remain low until the
first clock pulse following removal of the shutdown signal at pin 1 or pin 3. As shown in Figure
18, an externally latched shutdown can be accomplished by adding an SCR which will be reset
by cycling Vee below the lower under-voltage
lockout threshold (10V). At this point all internal
bias is removed, allowing the SCR to reset.

Fig. 15 - Direct POWERMOS drive
12 to20V

V;

UC3842
OUT

Fig. 18 - Shutdown achieved by
a) Pulling pin 3 high
b) Pulling pin 1 Low

1-"6'---{'='O=SI-Jl_~_-\!
R'
R2

,QQKJl

GND

(a)

S-7826

Fig. 16 - Isolated POWERMOS drive
18 to 30V

FERROXCUBE
1811

LOO-lce

(b)
'KJl

,

'5v

COMP

UC3842

SHUTDOWN
'=>_1817

5-7711

Fig. 17 - Bipolar drive with negative turn-off bias
12to30V

AVOIDING COMMON PITFALLS
UC3842

R'

OUTr6~~=t--~_~J--~~

GNO

Current-mode controlled converters can exhibit
performance peculiarities under certain operating
conditions. This section explains these situations
and how to correct them when using the UC3842.

Slope Compensation Prevents
Instabilities
It is well documented that current-mode controlled
converters can exhibit subharmonic oscillations
185

Note that in order for the error amplifier to accurately replicate the ramp, ZF must be constant
over the frequency range fs to at least 3f s.
In order to eliminate this last constraint, an alternative method of slope compensation is shown in
Figures 19c and 20b. Here the artificial slope is
added to the cu rrent sense waveform rather than
subtracted from the control signal. The magnitude
of the added slope still relates to the downslope of
inductor current as described above. The requ irement for RSLOPE is now:
m-

f,VRAMP(
II tRAMP
Rf

RSLOPE

+

l~TRf

Rf
RSLOPE

-Rf

)--.9.2.(
- r/2

Rf

+

= Rf( ~~4

Rf
)
RSLOPE

RSLOPE

Rf ( RS (VFl.4NL
+ Vol

1)
T

RSLOPE loads the UC3842 RT/CT terminal so as
to cause a decrease in oscillator frequency. If
RSLOPE » RT then the frequency can be corrected by decreasing RT slightly. However, with
RSLOPE ;S 5 RT the linearity of the ramp degrades
noticeably, causing over-compensation of the
supply at low duty cycles. This can be avoided by
driving RSLOPE with an emitter-follower as shown
in Figure 21.

-1)

Fig. 20 - Slope compensation added (a) to control signal or (b) to current sense waveform

8 "REF

(a)

UC3842

5-7830

VREF

(b)

RI

Rl/e l

;L/N

l

RSE.NSE.

r

Cf

I

1
C

-

FROM EIA

UC3842
5-7831

187

The speed of the UC3842 current sense section CI RCUIT EXAMPLES
poses an additional constraint on maximum operating frequency. A maximum current sense delay 1, Off-Line Flyback
of 400ns represents 10% of the switching period at
250kHz and 20%at 500kHz. Magnetic components Figure 24 shows a 25W multiple-output off-line
must not saturate as the current continues to rise flyback regulator controlled with the UC3842.
during this delay period, and power semiconduc- This regulator is low in cost because it uses only
tors must be chosen to handle the resulting peak two magnetic elements, a primary-side voltage
currents. In short, above ~250kHz, may of the sensing technique, and an inexpensive control
advantages of higher.frequency operation are lost. circuit. Specifications are listed below.
SPECIFICATIONS:
Fig. 23 - Deadtime and maximum obtainable
duty-cycle vs. frequency with minimum
recommended CT.
[,-'3664

Input Voltage

95 V AC to 130 V AC
(50Hz/60Hz)

Output Voltage:

i

I

A. +5V, 5%: lA to 4A load
Ripple voltage: 50mV
P-P Max.

( 'I,)

CT~100bpF
100
6S0
600
SSO

"'"
MAX td

SOO

~

/

~

B. +12V, 3%: O.IA to
0.3A load
Ripple voltage: 100mV
P-P Max

i_

DUTV@lMINtd

9S

DUTV@> TVP td

-:::::- 90
~ ...... . /
....... ~I-....
8S

DUTV@MAXtd

I

~

.......r-..... ...........

4S0

.........

400
3S0
MINtd
300

100

~

-----+-

200

\

400

300

C. -12V, 3%0.IA to 0.3A
load
Ripple voltage: 100mV
P-P Max

80

7S

Line Isolation:

3750V

Switching Frequency:

40kHz

Efficiency

70%

70
6S

f(KHz)

@

full load:

Fig. 24 - 25Woff-line flyback regulator

-r--o+

T1

4.7It lW

USD73S

4700,..1
IOV

56Kfi

DC OUT SV 2 to5A

lN36\J

IW

lN3613

16V

~'''"

Q01~,o,.,F

T1: CDILCRAFT E-4140-6
PRIMARV-97TURN5
SINGLE AWG 24
SECONDARY -4 TURNS
4 PARAllEL AWG 22

20V

5
P

Vee
2

VFB

150~n

OUT

6

21Jl

I caMP

2.SKfi

CON TROL -9 TURNS
3 PARALLEl AWG 28

UC1S42
8

VREF

CUR

3

SEN

R,/e,

I

ISOLATION
BOUNDARY

GND

5-80'31

189

A 25W OFF-LINE
FL YBACK SWITCHING REGULATOR

INTRODUCTION
This note describes a low cost switching power
supply for applications requiring multiple output
voltages, e.g. personal computers, instruments,
etc . . . The discontinuous mode flyback regulator
used in this application provides good voltage
tracking between outputs, which allows the use of
primary side voltage sensing. This sensing technique reduces costs by eliminating the need for an
isolated secondary feedback loop.
The low cost, (8 pin) UC1842 current mode control
chip employed in this power supply provides performance advantages such as:
1) Fast transient response
2) Pulse by pulse current limiting
3) Stable operation
To simplify drive circuit requirements, a TO-220
power MOS SGSP369 is utilized for the power
switch. This switch is driven directly from the
output of the control ch ip.

Power Supply Specifications
1. I nput voltage:
60Hz)

95V AC to 130V AC (50Hz/

2. Output voltage:
A. +5V,±5%: 1At04Aload
Ripple voltage: 50mV P-P Max
B. +12V, ± 3%: 0.1 A to 0.3A load
Ripple voltage: 100mV P-P Max
C. -12V, ± 3%: 0.1A to 0.3A load
Ripple voltage: 100mV P-P Max.
3. Line Isolation: 3750V
4. Switching Frequency: 40KHz
5. Efficiency @ Full Load: 70%

Basic Circuit Operation
The 117VAC input line voltage is rectified and

smoothed to provide DC operating voltage for the
circuit. When power is initially applied to the circuit, capacitor C2 charges through R2. When the
voltage across C2 reaches a level of 16V the output
of IC1 is enabled, turning on power MOS Q1.
During the on time of Q1, energy is stored in the
air gap of transformer (inductor) T1. At this time
the polarity of the output windings is such that all
output rectifiers are reverse biased and no energy is
transferred. Primary current is sensed by a resistor,
R10, and compared to a fixed 1V reference inside
IC1. When this level is reached, Q1 is turned off
and the polarity of all transformer windings reverses, forward biasing the output rectifiers. All
the energy stored is now transferred to the output
capacitors. Many cycles of this store/release action
are needed to charge the outputs to their respective
voltages. Note that C2 must have enough energy
stored initially to keep the control circuitry operating until C4 is charged to a level of approximately
13V. The voltage across C4 is fed through a voltage
divider to the error amplifier (pin 2) and compared
to an internal 2.SV reference.
Energy stored in the leakage inductance of T1
causes a voltage spike whieh will be added to the
normal reset voltage across T1 when Q1 turns off.
The clamp consisting of 04, C9 and R12 limits
this voltage excursion from exceeding the BVOSS
rating of Q1. I n addition, a turn-off snubber made
up of 05, C8 and R11 keeps power dissipation in
Q1 low by delaying the voltage rise until drain current has decreased from its peak value. This snubber
also damps out any ringing which may occur due
to parasitics.
Less than 3.5% line and load regulation is achieved
by loading the output of the control winding Nc,
with R9. This resistor dissipates the leakage energy
associated with this winding. Note that R9 must
be isolated from R2 with diode 02, otherwise C2
could not charge to the 16V necessary for initial
start-up.
A small filter inductor in the 5V secondary is added
to reduce output ripple voltage to less than 5OmV.
This inductor also attenuates any high frequency
noise.

191

TYPICAL SWITCHING WAVEFORMS

Ton - Drive waveforms

T off - Drive waveforms

Upper trace: Ql - Gate to source voltage
Lower trace: Ql - Gate current

Upper trace: + 5V charging current
Lower trace: +5V output ripple voltage

Upper trace: Ql - Drain to source voltage
Lower trace: Primary current - 10

193

APPLYING THE UC1840
TO PROVIDE TOTAL CONTROL FOR
LOW-COST, PRIMARY-REFERENCED
SWITCHING POWER SYSTEMS
INTRODUCTION
There are many potential approaches to be considered in switch mode power supply design;
however, the contradictory requirements of minimum cost and compatibility with ever more demanding line isolation specifications make primary
control very attractive. Application of the UC1840
as a primary-side, off-line controller presents an

extremely cost-effective approach to supplying
isolated power from a widely varying input line
while maintaining a high degree of efficiency.
Primary control means referencing all of the control electronics along with the power switching
device on the input line side of an isolation transformer. An obvious advantage to this approach is
the simplified interface between the control and

Fig. 1 - The overall block diagram of the UC1840, an integrated circuit optimized for primary-side control of off-line switching power supplies.

,----------------------61'

VIN

SENSE

----~@RAMP

COMP
INV.INPut
N.1.INPUl

!-..

@--_

~
;>......- + - - - - - - - - - - - 1
RR.

~

START/UV

200._ j
HYSTERESIS

RESET

3.0V REF
EXT. STOP

@----.

O.V SENSE

 i4 04 has a typical value
of 10 /JA) we can say that
V ref
A1
Therefore

TO-3 - For professional and military use or where
good hermeticity is required.
The guaranteed junction-case thermal resistance is 4°C/W, while the junction-ambient
thermal resistance is 35°C/W.

V out

= -R2
- V ref + V ref = V ref
R1

R2
(1 + - - )
R1

In other words R 1 fixes the value of the current
circulating in R2 so R2 is determined.

227

Overload protection

Current limitation

The device has an overload protection circuit
which limits the current available.

The innovative feature of this device is the possi·
bility of acting on the current regulation loop, i.e.
of limiting the maximum current that can be
supplied to the desired value by using a simple
resistor (R3 in fig. 2). Obviously if R3 = 0 the
maximum output current is also the maximum
current that the device can supply because of its
internal limitation.

Referring to fig. 2, R24 operates as a current
sensor. When 3t the terminals of R24 there is a
voltage drop sufficient to make 020 conduct, 019
begins to draw current from the base of the power
transistor (darlington formed by 022 and 023)
and the output current is limited. The limit de·
pends on the current which 021 injects into the
base of 020. This current depends on the drop-out
and the temperature which explains the trend of
the curves in fig. 4.

The current loop consists of a comparator circuit
with fixed threshold whose value is Vsc' This com·
parator intervenes when 10 • R3 = V sc' hence
V
10 = __s_c_ (V sc is the voltage between pins 5 and
R3
2 with typical value of 0.45Vl.

Fig. 4
:-,-~-~--r

lo(max)
(Al
./. "

'i

!

I

-

~

Special attention has been given to the comparator
circuit in order to ensure that the device behaves as
a current generator with high output impedance.

:-~l

~

t
20,us
6Vo o 2'1,

I

I

1

duty-cycle='%

TYPICAL APPLICATIONS
Programmable current regulator
Fig. 5 shows the device used as current generator.
In this case the error amplifier is disabled by shortcircuiting pin 4 to ground.
Fig. 5
R

10

20

L 200

Thermal protection
The junction temperature of the device may reach
destructive levels during a short circuit at the out·
put or due to an abnormal increase in the ambient
temperature. To avoid having to use heatsinks
which are costly and bulky, a thermal protection
circuit has been introduced to limit the output
current so that the dissipated power does not bring
the junction temperature above the values allowed.
The operation of this circuit can be summarized
as follows.
In 017 there is a constant current equal to:
V ref

- V BE17

R17+R16

Therefore at Tj = 25°C 018 is off (since 600 mV is
needed for it to start conducting). Since the V BE
of a silicon transistor decreases by about 2 mV laC,
018 starts conducting at the junction temperature:

2

The output voltage can reach a maximum value
Vi - V drap ~ Vi - 2V (V drop depends on 101.

Fig. 6 shows the device connected as a voltage
regulator and the maximum output current is the
maximum current that the device can supply. The
output voltage V 0 is fixed using potentiometer R2.
The equation which gives the output voltage is as
follows:

The base of 018 is therefore biased at:
V ref - V BE17
V BElS R16 + R17
• R16 ~ 350 mV

J

V5- 2
10= --R--

Programmable voltage regulator

(V ref = 2.75V typ)

T· = .J!00-350 + 25 = 150°C

The output current lois fixed by means of R:

R2
Va = V ref (1 + - - I
Rl
By substituting the potentiometer with a fixed
resistor and choosing suitable values for R 1 and R2,
it is possible to obtain a wide range of fixed output
voltages.

229

The formula for calculating R is as follows:

Therefore the output reaches its nominal value
after the time ton:

Vi min - (Vo + V drQP )

R=

10

C
Where V drop is the minimum differential voltage
between the input and the output of the device at
current ' 0 . V in min is the minimum input voltage.
Vo is the output voltage and
the output current.

'0

With constant load, resistor R can be connected
between pins 1 and 2 of the IC instead of in series
with the input (fig. 10). In this way, part of the
load current flows through the device and part
through the resistor. This configuration can be
used when the minimum current by the load is:
V drop

10 min =

R

(instant by instant)

ton =

C·

(V o - 0.45)
0.45

CVo R
0.45

Light controller
Fig. 12 shows a circuit in which the output voltage
is controlled by the brightness of the surrounding
environment. Regulation is by means of a photoresistor in parallel with R 1. I n this case, the output
voltage increases as the brightness increases. The
opposite effect, i.e. dimming the light as the
ambient light increases, can be obtained by connecting the photoresistor in parallel with R2.

Fig. 12

Fig. 10
R

s- "51911

Soft start
When a slow rise time of the output voltage is required, the configuration in fig. 11 can be used. The
rise time can be found using the following formula:
CVo R
ton =
0.45
At switch on capacitor C is discharged and it keeps
the voltage at pin 2 low; or rather, since a voltage
of more than 0.45V cannot be generated between
pins 5 and 2, the Vo follows the voltage at pin 2 at
less than 0.45V.

The circuit is shown in fig. 13. The primary supply
is shown taken straight from the car battery
however it is worth noting that in a car there is
always the risk of dump voltages up to 120V and
it is recommended that some form of protection is
included against this.

Fig. 11
t=~
on

Light dimmer for car display
Although digital displays in cars are often more
aesthetically pleasing and frequently more easily
read they do have a problem. Under varying am·
bient light conditions they are either lost in the
background or alternatively appear so bright as to
distract the driver. With the system proposed here,
this problem is overcome by automatically adjust·
ing the display brightness during daylight condi·
tions and by giving the driver control over the
brightness during dusk and darkness conditions.

0.45

Capacitor C is charged by the constant current ic .

ic =
231

Under daylight conditions i.e. with sidelights off
and T1 not conducting the output of the device is
determined by the values of R1, R2 and the photoresitor (PTRI. The output voltage is given by
R2
V out = V ref (1 + - - - - PTRIIR 1
If the ambient light intensity is high, the resistance
of the photoresistor will be low and therefore
V out will be high. As the light decreases, so V out
decreases dimming the display to a suitable level.

The designer must take into account the dissipated
power and the SOA of the preregulation transistor.
For example, using the BOX53, the maximum
input voltage can reach 56V (fig. 16). In these
conditions we have 20V of V CEon the transistor
and with a load current of 2A the operation point
remains inside the SOA. The preregulation used in
fig. 16 reduces the ripple at the input of the device,
making it possible to obtain an output voltage with
negligible ripple.

to a potential other than zero; diode 01 provides
output shortcircuit protection (fig. 18).

Positive and negative voltage regulators
The circuit in fig. 19 provides positive and negative
balanced, stabilized voltages simultaneously. The
L200 regulator supplies the positive voltage while
the negative is obtained using an operational amplifier connected as follower with output current
booster.
Tracking of the positive voltage is achieved by
putting the non-inverting input to ground and
using the inverting input to measure the feedback
voltage coming from divider R 1-R2.

If high output voltages are also required, a second
zener, Vz, is used to refer the ground pin of an Ie
Fig. 18
Rsc

,

BOX53

r

I

2Kll

I

lY.2

3

::2"'Y
~O~F

A

r

~o,

36V

Vi

2

L 200

~ ()

The system is balanced when the inputs of the
operational amplifier are at the same voltage, or,
since one input is at fixed ground potential, when
the voltage of the intermediate point of the divider
goes to 0 Volts. This is only possible if the negative
voltage, on command· of the op-amp, goes to a
value which will make a current equal to that in
R 1 flows in R2. The ratio which expresses the
negative output voltage is:

vHmax)::.56 v.V z

51

o.~ i=

JR'

Vo

~F

V-= V+· ~
(If R2= R 1, we'll get V-= V+)
R1
Since the maximum supply voltage of the op amp
used is ± 22V, when pin 7 is connected to point B
output voltages up to about 18V can be obtained.
If on the other hand pin 7 is connected to point A,
much higher output voltages, up to about 30V,
be obtained since in this case the input voltage can
rise to 34V.

1

VZ
52911/2

Fig. 19
R"

Fig. 20 shows a diagram is which the L 165 power
op amp is used to produce the negative voltage. In
this case (as in fig. 19) the output voltage is limited
by the absolute maximum rating of the supply
voltage of the L 165 which is ± 18V. Therefore to
get a higher V out we must use a zener to keep the
device supply within the safety limits.

A:Vi(max):::!:34V

3

=~
N~

..;

•

.......
!!:!

-

... ~----------------~~----------------~----------------~~--------~------~~

,.;

~~-+-~--+-~-~-~1-4--+-~~1~+--+~~41--+

11.1111

11.211
11.411
VELCRAO/SEC)

11.611

11.811

1.1111
_111t3

249

Also it is possible to impose a delay between th~
end of one signal and the start of the complement,
essential to avoid the short circuit conditi.on on
the bridge. The transfer of the signal from the controller to the high side of the bridge is via Q5 and
QS. These transistors are power devices working in
the active zone with very low current and must
sustain a voltage 5V greater than the voltage
applied to the motor (fig. 11 a).
This solution avoids the use of a transformer and
is aimed towards the eventual integration of the
power stage. The drive of the transistors in the
bridge was realised with a simple integrated solu-

tion of the SGS L149, whose power for the high
side is referred to the voltage at the motor terminals
which follows the variations.
The power for the motor is provided by a full bridge
circuit permitting operation in all 4 quadrants.
The two half bridge TRANSPACK, SGS30DB04OD,
are built using darlingtons without integrated collector - emitter diodes which permits full use of
the fast freewheel diodes incorporated in the
power module and high frequency drive of the
motor. The voltage waveforms on the motor are
illustrated in photo 1.

Fig. 11a

+-_-f""'/o.IC1

R24 B1

~-c~~-------,

'--l

I
I
I
I

SLHQ50

Photo 2A - Ripple of 3A at 5KHz

Photo 1 - Motor voltage

V =50V/div
t = 10j.ls/div

1= O.5A/div
251

Study of the system behaviour
To analyse the maximum stress condition on the
bridge corresponding to possible operating conditions, the algorithm of acceleration, braking and
inversion of the speed were performed. The objective was to obtain the maximum performance
possible with the transistor s chosen for the bridge.

Photo 5 - The trend of the velocity with four
progressive steps of voltage at intervals
of 25ms (560 rpm/div)

The strategy followed was to choose a speed of
3000rpm analysing the time needed to reach the
speed.

Acceleration Tests
Firstly the motor was accelerated with a duty cycle
correspondi ng to the chosen speed (steadyacceleration with a drive signal duty cycle of 70%). The
result of this test is shown in photo 3 & 4.
Photo 3 - Trend of the speed with only voltage
changing (560 rpm/div)

Photo 6 - The trend of the current under the
conditions of photo 5 (5A/div)

Photo 4 - Trend of the current under the same
conditions as photo 3 (5A/div)

4 increases in duty cycle of 5% with a 25ms delay

Also a ramp of acceleration was tested imposing
between each (photo 5 & 6).
In this way the maximum current during acceleration is reduced to 20A without any significant
variation of the time to reach full speed.
Photo 7 - The trend of the speed with the drive
of figure 13 (560 rpm/div)

In photo 4 it is seen that the current reaches a
peak of 23A in a limited number of pulses and
then goes to full speed much more slowly, with a
current of 0.6A. Regarding the speed, the period
of the transition may be estimated as around 1.2s.
253

Photo 11 - Trend of velocity with a initial drive
to produce 3750 rpm followed after
160ms by a drive to produce 2250 rpm
and finally after 50ms by a drive to
produce 3000 rpm

Photo 12 - Trend of velocity (1090 radslsecldiv)

The behaviour of the relevant currents are shown
in photo 13 where points shown by the arrows
are relative to the transformation of the motor
into a generator.
V

DUTY CYCLE

Photo 13 - Current absorbed by the motor with
the described speed invertion (1OAldiv)

%

80

70
60

iI

ii
160

50

TIME (msacl

Speed Reversal
Having reached the maximum, the objective was to
achieve the maximum steady acceleration and to
estimate the time needed to achieve an inversion
of the speed passing from +3000rpm to -3000rpm
having supposed that this is the most critical
stress on the bridge.
There was first analysed the phenomena of braking
and it was seen that braking too quickly may
cause a change of function, making the motor a
generator and creating excess emitter base voltage
up to a situation intolerable for correct operation
of the bridge components.
This phenomena was taken into account to achieve
the most rapid braking possible without overstressing the bridge components.
We succeeded in this way to obtain a time, from
+3K to - 3K rpm, of about 500ms, as shown in
photo no. 12 where the achievment of a steady
state is not considered but only the transition
from one speed (0 another.

Both the tests of acceleration and speed reversal
were made with repetitive cycles, with appropriate
programmes in the Nanocomputer@ , for periods
of several hours without creating problems for
the SGS30DB040D.

Balance of the Bridge
The evaluation of the power absorbed by the
various parts of the system is analysed in the
following paragraph.
The estimates obtained give an indication of the
efficiency of the control system in that it permits
a ratio of the power absorbed to that of the motor.
The power was measured using the following
system (fig. 141.
The chosen conditions were:

255

Duty cycle of 76%
Average motor current 1.25A

Photo 16

Photo 19

The power dissipated during the turn-on phase
and the respective voltage and current waveforms
are shown in photos 17 & 1B.

Photo 20

Photo 17

The dissipation of the conduction phase is not
conveniently measured by the method used so it
was preferred to make an estimate.

Photo 18

At the average current of 1.25A from the charac·
teristic curves a V CE (sat) of O.BV is found.
PCOND • = 1.25A x O.BV x 0.76 = 0.76W
Taking into consideration that the conduction
phase is 76% of the full period:
The power dissipated in a transistor of the bridge
is thus:
PTO T = PON + POFF + PCOND = (4.1 + 2.57 +
+ 0.76) W = 7.43W

CONCLUSION
From the photo of the power it is possible also
to measure the energy dissipated. This corresponds
to an average power of:
PON = Ex F = 1B9.6j.LJ x 21700Hz = 4.1W
The power dissipated during the turn-off phases
and the respective waveforms are shown in photo
19 & 20.
The energy dissipated in this case is 11Bj.LJ thus:
POFF = E x F = 11B.5 x 21700 = 2.47W

During this work a study was made, both in theory
and application, of the control of a DC motor.
For this study, advantage was taken of the flexibility offered by using a microprocessor to make
many tests. This allowed a comprehensive analysis of
the behaviour of the SGS30DB045D TRANSPACK.
This involved the recreation of particularly heavy
operating conditions for the power circuitry,
which verified the excellent performance of the
TRANSPACK devices, above all in terms of
switching speed and low losses. Also studies
were made of a number of drive circuits for the
power transistors, useful for future projects.
257

APPENDIX A

(continued)

CLOSE (UNIT= 11 )
STOP
END
SUBROUTINE RKUTTA(N,X,Y,FUNC,H,XF,YF,CR,RA,XLA,FL,CM,E,RJ,
Kc,Kv,L,T,T1,T2)
DIMENSION Y (20),YI(2D),YF(20),D(20),A(S)
REAL KC,KV
A (1) • H/2
A (2) • A (1)
A (3) = H
- A (4) = H

A (S) .. A (2)

10

20

18

11
12
21

XF-X
DO 10 K=1,N
YF (K) .. Y (K)
YI (K) .. Y (K)
DO 20 J=1,4
CALL FUNC (XF,YI,N,D,CR,RA,XLA,FL,CM,E,RJ,Kc,Kv,L,T,T1,T2)
XF-X+A (J)
DO 20 K=1,N
Yl(K)=Y(K)+A(J)*D(K)
YF(K)=YF(K)+A(J+1)*O(K)/3
RETURN
END
SUBROUTINE FUNC (X,Y,N,D,CR,RA,XLA,FL,CM,E,RJ,Kc,Kv,L,T,T1,T2
DIMENSION Y (20),D (20)
REAL KC,KV
DO 16 M=O,(L-1)
IF(X-M*T).LE.T1) GO TO 11
IF«X-M*T).LE.(T1+T2)) GO TO 12
CONTINUE
VA-400.
GO TO 21
VA .. - 400.
GO TO 21
CONTINUE
D (1) .. (VA-E-RA*Y(1))/XLA
D (2) =(CM-CR)/RJ
RETURN
END

259

APPENDIX B (continued)

, dc motor control'
"tn addr c·b j COd'2 t e i line
1.
L

3
4
~'

J

6
7
8

9
10
11
12
13
14
is

16
17
18
19
:20
21
;.! :.~

23
~)4

25

26
27
28
29
~0

31
32
33
3,,:'

35
36
3/
38
39
40
41
4"
43
44
4S
46
41
48
49

..

~(1

51
52
1:: ....
.....1 .

.:>

~.(t
':;"L"

J.J

:16

57

D85F
0861
1)863
0865
[)866

31::02
26H'
2EFF
20
C265D8

D869

.. ,J

D8M
0860
086E
0871
0872
OS73
08/6

0878
D87A
087e
D87E
D87F
0881
D883
U88S
D88/
0888
D88E\
088e
D88F
0890
08'7'3
0894
D89!:5
D898
D899
1)8'1B
089E
D89F
08A0
D8Al
D8fl~'
D8A~

D8A6
D8A7
08A8
08A9
08AC
D8AD
D8AE
D8Bl
D8E\2
D8E',4
D8B"l
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D81:W
1)t::E'.A
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D8BF
1)8C0

')c.

C2631)8
30
C261D8
l'i

B7
C21COS
16FF
1E1F
0608
0E08
IA
0309
3E08
26FF
2EFF
20
C28708
25
C285D8
3D
C2831)8
/8
B7
CAACD8
78

58
:;'1

60
61
6'"
63
64

..

66
67
68
6'""/
70

d'2C
jp
dec
jp
ld
or
jiJ

init2

/4
/5

76
II

18
1'""/

loop4
loopS
'loop6

Id
ld
Id
"td
Id
.out
Id
Id
Id
dE!c

82

<2;.( i t3

l

nZ,loop3
h
nZ,loop2
a
nZ,loop1
a,c
a
n;::.ma I n
d,~ffh

e,lfh
b,0tih
c,08h
a,d
(p i od), a
a,08h
h,0ffh
1.0ffh
1

dE!C
jp

nZ,.loop5

d.=c

a

jp

nz.loop4

Id
or

a .. b

86
81

.iP

z, i nd6
d.b
05h
m. indS

81..~
~.

Id
:,ub
ip
d2C

88

.
93

94
9!:5
96
97
98

d8C

ind5

'i9

jp

Id

out.1
a,c
a
z,out1
a.c

sub
lP

m, indl

0D

101

1D

iD
1D

1013
10S'
110

d<2C
d<2c
d<2c
dec

l3C~;D8

lil

0D
iC
lC

112
113
114

.lP

Id
or

.iP

ind".7

d'2C

inc
inf:
261

b
d

d
d
out.1

B7
CAC5D8
79
D605
FABEliB

ind6

a

d<2C
d<2C
jp
d."c
inc
inc
Inc

100
101
102
103
104
105
106

/'i

~

t·5

D60~:';

05

source statement

b
d
d

d

~15h

C

e
e
t?

Dut1
c
<2
~

APPENDIX B (continued)
, de motor cotltrol'
addr obj code t e i line

In

1
2
3
4

0926
0928
092B

OnG

~

ono

6
7
B
9
10

092E
092F
0932
0933
0934
0930
0936
0939
093A

11

12
13
14
15
16
11
18
19
20

21
~!2

23
24
20
26
21

one.

09JE
093F
09'.1
0944
0945
0947
0949
0948
09'.0
09'.E
0951
09~2

D605
FAJ20'1
00
10
10
10
C33909
00
lC
IC
lC
C33909
/8
B/

CA4409
7A
0309
(;347D9
78
0309 .
3E01
:.!65F
2E~F

20
C24009
25
C24B09

2& 0'l55. 3D.
29
30
31
32
33
34
3!::;
36
37
38
39
4O
41
42
43
44
45
46
4l
48
49
50
51
1:0'

~)

'"'<_

53
54
5~

56

57

0956 C24'109
0959 79
095A 87
0951? (;20709
095E 16FF
0960 0604
0962 7A
0963 . 0309
0965 3Eco8
0967 26FF
0969 2EFF
0968 20
096C C26BL>9
,")C"
D96F ,;.,",
0970 C26't09
0973 3D
0974 C26709
0977 l8
0978 1:'.7
0979 CA8009
097C 05
D970 15
097E 15
097F 15
0980 7A
0981 0309
0983 3E01
0985 ~!65F
0987 2E5F

sourc", s t ateDleflt·

172

In

1/4

1/5
1/6
177
178
1"79
180
181
182
18j
184
Hl5

ind10

out2

186
187
188
1B9
1'10

191
192
1'13
194
1'15
196
1'17
198
15''1
200
201
202
203
204

e:·:i t9
exit7
loop13
loop14
loop15

init4

2~5

206
207
208
209
210
211
212
213
21',

loop1.6
loop17
loop18

215

216
21"7
218
219
~20

222
223

indl1

22~

226
227

228

05h

Id
d",c
jp
d",c
jp
d",c:.
;ip
ld
or
jp
Id
Id
Id
out
Id
ld
Id
d",c
.iP
d",c:
.ip
dec:

1~5fh
1

Id

jp

exit8

221
224

sub
jp
d,,,c
dec
dec
d",c
jp
dec
inc
inc
inc
jp
Id
Of'
jp
ld
out
jp
Id
out
Id

loopl'1
loop20
263

Id
or
jp
d,,,c
dec
d.;-,c
d",c
Id
out
Id
Id
Id

Dl,ind10
c
e
e
e
out2
c
e
e
e
out2
a,b
a
z. e>: i t9
a,d
(piod);a
"'}: i t7
al"e

(p i od), a
a,01h
h.5fh
nZ,loop15
h
nz,loop14
~

nz, loop13
a,C:
a
nZ,exit6
d,0ffh
b,04h
a,d
(piod),a
a.00h
h,0ffh
l,0ffh
1

nZ,loop18
h
nz,loopll
a
nz,loop16
a,b
a
z, i ndl1
b

d
d
d
a,d
arallel diode and if charge has been stored
in this junction it causes the greatest stress on the
device.
The transistor failure (disregarding the overstresses
induced on purpose), is in practice triggered by
more than the single switching phase described
above, it is more a series of subsequent stresses
at each switching cycle which leads the device
into a critical state. It is also easy to appreciate
that the failure concludes a phase of abnormal
heating in a concentrated spot on the chip.

269

PARALLELING TRANSPACK MODULES
A practical example

INTRODUCTION
The requirement for a higher current rating than
a single module can provide is not uncommon,
but the circu it designer probably questions the
practical feasibility of paralleling large transistor
modules such as the SGS TRANSPACK.

offer practically the same power switching capability. If a device is rated for a higher voltage, it
will consequently be rated for a lower current.
As a result, it is clear that the most common case
of paralleling occurs with high voltage parts.
The SGS30DA070D has been selected for this
example as it represents the highest current rating
in the high voltage range of TRANSPACK modules.

Although these device are more complex than
discrete transistors, in practice they can be paralleled quite easily, the main point to keep in mind
is current sharing between the paralleled modules
during turn-off when loaded inductively.

SGS30DA070D IN PARALLEL
THE MOST COMMON CASE
Different kinds of SGS TRANSPACK modules

Four modules were used for the practical investigation and the relevant hFE curves versus
Ie can be seen in Fig. 1.

Fig. 1 - h FE curves of four SGS30DA070D modules

hFE

D ____

1000

\ICE' 5 \lOlT

A=hFE @ 30A 3V TYP 60

.....
~~--: -.
~ "-

---- ---'-.~"
"

130
250

,.~
"

~

'--.~,

-.

10

o

100

(

o ...

-,~"-,,

100

B

5

10

20

30

271

50

~
".

100

Ie

The reverse bias safe operating area was obtained
using the test driving circuit shown in Fig. 5. The
RBSOA characteristics for a single module (Fig. 6)
and the three modules in parallel (Fig. 7) show
that the high voltage boundary is the same for both
arrangements.

devices which were not specifically selected for
the test. A further improvement can be achieved
if parts with very close hFE values are paralleled
together, ideally the three parts should remain
within a ± 10% hFE range.

Fig. 7 - RBSOA of the three devices in parallel

hFE matching ensures that the paralleled parts
have almost the same storage time and that none
of them supports the entire load current, during the
interval between turn-off of one module and
tu rn -off of the other two.

G

Ie

I

(A)
70

I

i

60

5955

-+-~

I

The high switching speed of SGS devices helps
to minimise any minor variations between matched
modules.

- -

II

50

II
I

i I I-I

,

I

30

-t-U-L

+

I

40

~

CONCLUSIONS

~

I

,,",'

20

,

~.
~

10

i

1
200

'00

600

800

1K

--

,

Care must be taken to ensure that current is
equally shared between paralleled modules and
layout is optimised to reduce stray inductance in
the interconnection leads.

i
I
I

12K VCE(Clamp)'V)

The addition of a 1.20 resistor in the test driving
circuit to limit the negative base current improves
the high voltage boundary of both RBSOA charac·
teristic curves, the dotted line corresponds to the
new boundary.

THE BEST CHOICE
This example demonstrates the performance of

The easiest way to ensure a fair sharing of the current is by adding a seperate speed up diode and
bias resistor network to each module. However,
this will not prevent the possibility of current
overshoot in one module during turn-off (as shown
in Fig. 4) so for optimum results it is best to ensure
current matching during turn-off.
The most practical way is to use parts with hFE
values within a ± 10% band for paralleled operation. SGS TRANSPACK power modules can
be supplied in gain groups to suit customer applications.

273

ROBUSTNESS OF HIGH VOLTAGE POWER
TRANSISTORS
INTRODUCTION

FORWARD BIAS SAFE OPERATING AREA

Most semiconductor manufacturers publish safe
operating area (SOA) curves of some form in
their data-sheets. These published curves are
intended to convey to the user, the electronic
equipment designer, a measure of the device
robustness. The forward bias safe operating area
(FBSOA) indicates the collector emitter voltage
and current capability with the base emitter
junction forward biased. The reverse bias safe
operating area (RBSOAI, as the name implies,
indicates the collector emitter voltage and current
capability with the base emitter junction reverse
biased. This curve is used to determine the locus
of the transistor operating point during the transition from forward biased conduction to the
cut-off state.

The forward bias safe area for the 5G5 BUX48/
SGS BUV48 transistor families is shown in figure
1. The curves apply for a case temperature of
25°C. The lower curve represents the continuous
conduction case, with collector current, Ic, limited
to 15 amps and collector emitter voltage, VCE
limited to 400V, or 450V for the 'A' part, 600V
for the 'B' part or 700V for the 'C' part. Beyond
the 15A 10V point on the curve, the current
rating falls in conformance to the maximum power
rating of the transistor. There are 2nd and 3rd
break points (charge of gradient) on the curve at
6A and O.2A. In these areas the transistor is no
longer limited by total power rating, but by
second breakdown.

Generally speaking, safe operating area curves
have been published for the transistor case temperature at 25°C. Derating is required, the amount
being dependent on the transistor operating temperature and the temperature derating factor. Different derating factors are applied by some manufacturers to different parts of the SOA curve,
depending on the failure mechanism which limits
the transistor performance in that area. Thus, it is
common to see both 'power derating' and 'ISlb
(second breakdown) derating' factors published.
Additions to the standard SOA curves are being
made as the capabilities and the understanding of
the process technology are improved. In particular,
extensions above the VSEO rating of the transistor
are seen in both FBS A and RBSOA curves to
indicate the transistor capability during 'switch-on'
and 'switch-off' transitions.

Fig. 1- BUX48/BUV48 forward bias safe operating
area

Non repetitive overload safe area curves are also
appearing, and these will be found particularly
useful in the motor control area However, a degree
of caution is necessary on the part of the design
engineer in interpratation of this additional information. The semiconductor manufacturer will
have defined the test conditions for which the
overload safe area curve applies. Disparitv between
the application circuit and the semiconductor
manufacturers test circuit, including any preconditioning, can cause significant differences in the
abilitv of the transistor to withstand an overload.

Ie
(A

!

le~PULS.

*PULSE DURATION

10

,•
,
, De OPERATION

·,,
·,

10".
100".
1m.
10m.

"

, leMAX eONT.

4

10'

FOR SINGLE N N
REPETITIVE PULSE

:\
~

,

JI:,BUY48/BUX48
II~UV48A IBUX48A

'f--

-,
10

,

..

10

,

·461

,

...

10 3

,

•

II

VeE (V)

The outer set of curves represent the pulse current
capability, as opposed to the DC capabilitv of the
transistor. The rating applies for a single pulse,
so that the dutY cycle effect and resulting temperature increase is discounted. All of these curves
are terminated at the VCEO rating (400V - 700V)
of the transistor. A small additional area, marked
275

Fig. 5 - Theoretical operating locus in FBSOA test
30/15

_

Ip~

Ve/Rz

Ie
Amps

ZO/10

returning the inductive energy stored in L to the
supply, VB' Resistor R3 connected in series with
the rectifier 01 shapes the load line and so determines the locus of the operating point of the
T.U.T. during 'turn off'. The peak voltage across
the T.U.T. will be:
VCEPk = VB

10/5

ZOO

400

+

ICPk • R3

+

VF 01

This simple equation neglects the effects of circuit
wiring inductance and the forward recovery time
of the rectifier, 01. Some adjustment in V B or R3
value may be required to compensate for these
effects. Figures 8 and 9 illustrate the locus of the
operating point of the T.U.T. during 'turn off'.

600
VCE Volts

SU-1438

Fig. 6 - Oscilloscope display of operating locus in
FBSOA test

Fig. 7 - Reverse bias safe area test circuit

GU 1210

,..

IC
12A

,

R3

01

'\

""
"

0
a)

VCE 600V

BUX48A

-5V
SU·I441

GU-l'Z3t

Fig. 8 - Theoretical operating loci in RBSOA
tests

IC
26A

'" ~
'\

Ie

......
0

Amps

High Current RBSOA Test

~
Turn 'off'

.... ......
VCE 600V

b) BUX98A
5lH4~9

The reverse bias SOA test is performed in 2 stages.
This is to achieve a 'best fit' to the SOA curve.
The first part of the test exercises the high current
RBSOA extending up to the V CEO for the transistor. The second part exercises the low current,
high voltage area extending to VCER' Figure 7.
Illustrates the test circuit. Switch 1 closes to turn
the T.U.T. 'on'. The condition time is controlled
to limit the peak collector current.
As switch 1 opens, switch 2 closes reverse biasi ng
the base emitter junction of the T.U.T. Following
the storage time delay, during which time the
excess charge in the collector base junction is
extracted, the collector emitter voltage rises instantaneously to VB when the rectifier, 01 conducts

277

Fig. 9 - Oscilloscope display of operating loci
in RBSOA test
GU 1232

~LJl
IC

~+++--tT· i--j~ i ft-~
ir.::r~~
I
I

I
~

i
a)

!

-Tl-+I---t---i---l
I
\! i I
!.J I I

11 A I

0

I

VCE400V

I

BUX48A High Current RBSOA

TECHNOLOGY RELIABILITY AND APPLICATIONS
OF SGS HIGH VOLTAGE NPN. TRANSISTORS

Introduction
The basic technology chosen for high voltage
(V CEO > 400V - V ceo > 600V) transistors is
fundamental to their in-circuit performance as well
as their "built-in" reliability.
Also the technology effects the wafer size which
may be used in production, as well as the yields.
In some cases also packaging options may be
restricted. These are important factors influencing
the price and availability for any semiconductor
device.

Subject
This note discusses the SGS Multiepitaxial Mesa
process used for a wide variety of industry standard
products as well as some innovative types.
This technology is illustrated in simplified form in
figure 1, figure 2 shows an actual cross section of
the edge of a die made up of several scanning
electron microscope pictures.

Fig. 1a - Multiepitaxial Mesa wafer simplified cross section
THERMAL OXIDE
P-VAPOX

AI

279

GLASS

!I-6954

mou nti ng in the package the fact that SGS cuts
the silicon outside the mesa and its glass filling,
eliminates the risk of mechanical damage to the
passivation.
As the sawing creates a short circuit at the edge of
the die from the collector to the field plate no
"flashover" can occu r in the package between
the header wh ich is at collector potential and the
top of the die, which in alternative half mesa technologies wi II be at base potential. The su rface is
covered with a thick oxide as previously mentioned
so no arcing occurs along the surface.
This process of passivation also ensures high
reliability in plastic packages.
This technology also allows wafers to be 100%
probe tested to high voltage specifications, an
important point for users of high voltage transistors
in chip form for hybrid assemblies.

handled allowing SGS to use 4" and 5" wafers
with ease.
Following diffusion is the etching of the mesa
which is filled with a very pure glass by an SGS
patented selective deposition process which avoids
any contaminants such as photoresist which may
not be entirely evaporated during the fusion of
the glass. The aluminium top metal is now deposited
and the pattern defined. The entire top of the
wafer is now protected by a thick deposited oxide
in which windows are opened for bonding the base
and emitter connecting wires.
Finally the wafer is reduced to the correct thickness,
removing the excess N+ silicon by grinding the
back of the wafer, after which the back is metallized.

Packaging
As the die must be separated from the wafer before

Fig. 3 - Section of Mesa with simulated equipotential lines

75,.um
20

LO

60

80

200,um

100 Tl).

5-8076

It may be seen that the introduction of a ballast

resistance in series with the base or the emitter
may reduce from J3 to J2 the current density in
the hot spot.
The emitter ballast resistance is generally obtained
by opening emitter contacts thinner than the
emitter strip (Fi'g. 4).
In this way it is possible to limit the current density
at the boundaries of the emitter. These resistances
show the drawback of increasing the saturation
voltage of the transistor by the amount VCEsat
= RE x Icsat.
On the other hand, the base ballast resistance is
obtained through a "N+ pocket" (in the case of
NPN), around the emitter area (see Fig. 5). This
N+ diffusion, being unbiased, can't be traversed
by the base current, that is therefore forced to
flow below the N + through a small section and, in
the case of a diffused base, encounters a higher
resistance on the way to the edge of the emitter.
In this way, it is possible to significantly improve
Is/b.
It should be noted that the SOA limits are temperature dependant and suitable derating must
be applied.

Fig. 4

287

For low VCE values, M is an insignificant factor,
being very close to 1. M increases when V CE is
increased according to the following expression:

M

=

(2)

1 - (V cE /BVC80) n

constant of silicon. When the collector current is
limited to low values, expression (3) becomes (q
being the electron charge):
(IE

qNo
e

ax

(4)

From expression (1) and (2) it is evident that
hFE depends on VCE, becoming infinite when
M x aF = 1 (BVCEO).

and the electric field behaviour is similar to that
shown in figure 10 for Jc = J'l.

The negative slope section, which is a feature of
the curves with 18 < 0 is due to the fact that aF
decreases at low values of the emitter current.

Fig. 10
CRITICAL FIELD
J'CR

During turn off with an inductive load, the transistor has to operate with negative base current and
a high value of Ic. It has often to reach a working
area above V CEO, remaining there all the time
required for the inductance to be discharged (see
Fig. 7). Fig. 8 shows the behaviours of Ic, VCE,
18 and the power dissipated by the transistor
during turn off.

E

/

/

I.

The area of the dissipated power corresponds to
the energy stored by the inductance 1/2 x Lx 12 ,
which is discharged into the transistor and this is
called second breakdown energy (Es/b).
Similarly to ISIb' the voltage drop due to the
reverse 18 flowing through the side resistance rbb'
makes the centre of the emitter strip more biased
than its periphery (Fig. 9). In this way, a current
concentration occurs at the emitter centre.

N+
SUBSTRATE
5-808.4

The voltage VC8 (= VcEI is that given by the area
of the E-X graph and is smaller than primary
breakdown voltage, due to the reaching of critical
field Ecr. I n the presence of significant values of
current density Jc, the expression (4) is modified
due to the n concentration of electrons flowing at
the speed V through the depletion layer.

Fig. 9

N
5-8083

Let's analyse the case of an NPN transistor with
diffused base and epitaxial collector, i.e. with
constant concentration ND of donors doping
particles.
Poisson's equation is recalled below:

aE
a v
ax
= -ax = -e2

pIx)

2

(3)

The X axis is normal to the silicon dice surface, p (x)
is the charge per unit volume, e is the dielectric

289

aE

q(ND - n)

ax

e

where n =

~
qV

(5)

At constant VC8, the area limited by E has to
remain constant. When Jc increases, the E-X slope
varies (J'2) until its sign is changed (J'3) and Ecr
is reached (J'cr). At this point avalanche multiplication occurs locally of electron - hole pairs
with an uncontrolled current increase and so
a strip is formed with a very high temperature that
gives rise to either crystal damage or silicon melting.
Possible crystal defects, metal ions, junction
disuniformities just further exagerate this phenomenon. The avalanche multiplication is a very fast
and very local ized process, therefore the device
remains externally cold. The Es/b behaviour isn't
practically influenced by the die bonding quality.
High Es/b values can be obtained with a proper
design of geometry, to limit the current crowding
and, most of all, by inserting a second epitaxial
layer N of intermediate doping between the collector and the substrate.
.
The intermediate layer creates the condition shown
in Fig. 11. When the current density increases
(J' 2) the electric field at the interface N-IN is in-

SGS HIGH VOLTAGE FAST RECOVERY DIODES
AND THEIR SWITCHING PERFORMANCE
INTRODUCTION

The TRANSPACK product range and
the internal diodes

SGS decided to introduce its line of power
switching modules in the TO-240 TRANSPACK
package.
To solve the problem of providing fast recovery
rectifiers capable of matching the high voltagel
high current of the transistor chips in the TO-240
package, SGS was able to exploit its technological
leadership in power semiconductors. The rectifiers
were fabricated by epitaxial growth with high
voltage termination structures.
SGS was the first in
epitaxial growth for
Its epitaxy capability,
of the fastest epitaxy

This report deals with the first three diode chips
developed, table 1 gives their main characteristics.

TABLE 1
Type

the industry to introduce
all its power transistors.
fully in house, makes use
reactors in the industry.

This note describes the switching behaviour of the
fast recovery rectifiers used in SGS TRANSPACK
power transistor modules and the SGS35R 120
series of diodes.
The turn-off and turn-on behaviour is described
and the characterization is oriented to the conditions of practical use.

IF (AI

VRRM

SGS35R80

35

800

SGS35R120

35

1200

SGS60R40

60

400

(VI

The second table below shows the TRANSPACK
product range and the relevant fast recovery
rectifier used in each device.

TABLE 2
Type

C/E diode

=D

SGS80DA020D
SGS40TA045
SGS40TA045D
SGS50DA045D
SGS25DB070D
SGS25DBOBOD
SGS30DB040D
SGS30DB045D
SGS30DA060D
SGS30DA070D
SGS50DB040D
SGS50DB045D
SGS15DB070D
SGS15DB080D

Quart
IHaif

Trans
IDarl

Q

D
T
T
D
D
D
D
D
D
D
0
D
D
D

Q
Q
Q

H
H
H
H
Q
Q

H
H
H
H

VCEO VCEX
(VI
(VI
200
450
450
450
700
800
400
450
600
700
400
450
700
800

IC(satl
(AI

Vc

80
40
40
50
25
25
30
30
30
30
50
50
15
15

2.0
2.0
2.0
2.5
3.0
3.0
3.0
3.0
2.5
2.5
3.5
3.0
3.0
3.0

300
850
850
850
1000
1200
500
600
1000
1200
500
600
1000
1200
291

sat

toff (,usl
at
Ib typo induct.
1
8
8
2
2.5
2.5
2
2
1.5
1.5
5.0
5.0
1.5
1.5

1.9
2.2
2.2
2.0
2.4
2.4
2.0
2.0
3.0
3.0
3.0
3.0
2.5
2.5

Diode
type
SGS60R40
none
SGS35R120
SGS35R120
SGS35R120
SGS45R80
SGS45R80
SGS45R80
SGS35R120
SGS35R120
SGS45R80
SGS45R80
SGS35R120
SGS35R120

Trr definition

In cases like that shown in Fig. 2, it is important
to consider that only tA is representative of the
duration of the power pu Ise that the recovery
of the diode induces in the transistor.

Figures 3 shows two possible definitions for the
recovery time, tA and tB' In practice trr is defined
as tB in the figure.
Fig. 3 - trr measurement methods

25%

SU'1076

Trr characterization

Photo 2 - Recovery times vs. di/dt at 40A for
SGS35R120

Photographs 1 and 2 show how different test
conditions (I F and di/dt) imply markedly different
results for t rr , for the same diode.
The blocking voltage V RM can be disregarded as
its influence on trr is not direct. di/dt is the significant factor and V RM is of importance only to
the extent where it modifies di/dt.
Photographs 3 to 5 show the behaviour of the SGS
fast recovery rectifier diodes in conditions representing the real environment in which the
devices are expected to work. For instance, tA for
SGS45R80 at 40A is 150ns. In a circuit like the
one in figure 4, with 40A current in the inductor,
the power pulse that the transistor must sustain
(lc peak x VeEl will last for 150ns.
The capacity that SGS transistors have to safely
absorb this energy is guaranteed in their FBSOA
diagram.

Photo 1 - Recovery times vs.
SGS35R120

IF = 40A; A: di/dt = 250A/J.lS;
B : di/dt = 100A/J.ls; V R = 30V;
t = 200ns/div; y = 10A/div

di/dt at 1A for
Photo 3 - trr for SGS45RBO

III

I

III

-"

Ii:::

i~

1=--

I~ I~

III

~

1=-

0:.

w,:r..

I~~ ~

~
.~ ~

I....

I
I

,
,

, IIiiI
'-..

... -

n'

I

IF = 1A; A: di/dt = 100A/J.ls;
B : di/dt = 50A/J.ls; C : di/dt = 25A!J.lS;
V R = 30V; t = 20ns/div; y = 1 A/div

IF = 40A; di/dt = 100J.lS; V R = 30V;
t = 200ns/div; y = 20A/div
293

Fig. 5 - Typical configurations for transistors switching

b)

a)

S[-0165

VFP and tFR definition

Fig. 7 - Direct overvoltage vs. di/dt

The turn-on phase of a diode in a practical situation is shown in Fig. 6.

GO-JOlt.{)
)

V FP is defined as the peak transient voltage.
For the same current, the turn-on overvoltage is
higher for diodes that can withstand a higher
reverse voltage. This can be seen in Fig. 7.

SG 35R 20

TC=12S'C
IF =IF(AV)

This is mainly related to the thicker epitaxial
layer needed to implement a higher reverse voltage
rating.

20

At the turn-on of a diode, a thicker epitaxial
layer causes a higher resistance, before the conductivity modulation by the minority carriers
takes place.

,/

,/

V
,/

V
/

10

/

£::; ~

SG ;JRI80

,....... 1--1-"'
~ ~RrO

/'

--

100

100

Fig. 6- Turn-on transient of the diode

T FR Characterization

VOIV)
IF

IOIV)

I
~

I n Fig. 8, the turn-on times, tf ' for the SGS
fast recovery rectifiers SGS45Rl{0, SGS35R 120
and SGS60R40 are shown as a function of di/dt.

/'

VFP

di/dt ' 40Alf's

tfr is defined as the time from the instant V F
becomes positive till the time V FP decreases to
+2V.

.VF

,
GU-1QIt7

V FP Characterization
Figs. 9 to 11 characterize V FP in all possible
di/dt conditions of practical use for the diodes
295

Fig. 12b -Bridge configuration for motor driving

Fig. 11 - Direct overvoltage vs. dildt

SGS4SR80

40

.JL

TC=12S'C

30

VittI

IF =40A

..,

20

.......

"..,

V

10

r-----

-{

I

V
./

I

V

I

100

200

I
I

300

-'

di/dt(AjJs)

SU-ICI,{j

Fig. 12c - Voltage and current waveforms with
reference to Fig. 12b

Via,

Vla2

t

V02

t

Gij-l048

v

= 5V/div; IF
t = 100ns/div

= 25A;

di/dt

= 200A/IJs
lei

~~......
l--

t

t
Fig. 12a - Final stage of power amplifier

5(-0164

If O 2 is a darlington, this negative voltage may be
enough to reverse bias (through the integrated
resistances of the darlington) the final transistor
and make it conduct a reverse current Ix.
The current Ix may be a significant proportion of
the current that is expected to flow only through
2 , and it can store a significant charge Or in the
final darlington transistor.

°

Vi (t)

V

The final darlington transistor base collector
junction acts as a slow recovery diode.

°

As a result, when 0 1 is again turned on, it senses
the behaviour of an 'equivalent 2 ' with a much
longer reverse recovery time. The peak current is
higher than expected,creating reliability hazards or
possibly the destruction of 0 1 .
SU-1041

SGS produces safe operating area diagrams
(FBSOA) which specify the maximum Velie
boundary for each device in the range so the

297

HANDLING AND MOUNTING ICs
IN PLASTIC POWER PACKAGES
Integrated circuits mounted in plastic power packages can be damaged, or reliability compromised, by inappropriate handling and mounting techniques. Avoiding these problems is
simple if you follow the suggestions in this section.
Advances in power package design have made it
possible to replace metal packages with more economical plastic packages in many high power applications. Most of SGS' power driver circuits, for
example, are mounted in the innovative MU L TI·
WATT® package, developed originally for high
power audio amplifiers. Though the intrinsic reliability of these packages is now excellent the use
of inappropriate techniques or unsuitable tools
during mechanical handling can affect the long
term reliability of the device, or even damage it.
With a few simple precautions, careful designers
and production engineers can eliminate these risks,
saving both time and money.

leads. In these processes it is important to avoid
straining the package and particularly the area
where the leads enter the encapsulating resin. If the
package/lead interface is strained the resistance to
humidity and thermal stress are compromised,
affecting reliability.
There are five basic rules to bear in mind:
•
•
•
•
•

BENDING AND CUTTING LEADS
The first danger area is bending and cutting the

Clamp the leads firmly between the package
and the bend/cut point (figure 1).
Bend the leads at least 3 mm from the package
(figure 2a).
Never bend the leads more than 90° and never
bend more than once (figure 2b).
Never bend the leads laterally (figure 2c).
Make sure that the bending/cutting tool does
not damage the leads.

Fig. 1 - Clamp the leads between the package and bend/cut point.

~

w
Plastic

!!

~

5-5393

Fig. 2 - Bend the leads at least 3 mm. from the package, never bend leads more than 90° and never
attempt to splay the leads out.
3.0min

WRONG

_-=-====':==:1
RIGHT

a

b

c
299

S _~370

Fig. 5- MULTIWATT, PENTAWATTandVERSAWA TT packages are attached to the heatsink with a single screw or a spring clip.

heatsink must be better than 50~m for PENTAWATT
and VERSAWATT packages and less than 40~m
for MULTIWATT packages.

Fig. 7 - The heatsink tab may be deformed if a
washer or a wide-headed screw is not
used.

heat-sink

Similar problems may arise if the screwhead is too
narrow compared to the hole in the heatsink
(figure 7).
The solution here is to use a washer to distribute
the pressure over a wider area. An alternative is to
use screws of the type shown in figure 8 wh ich
have a wide flat head. When self-tapping screws
are used it is also important to provide an outlet
for the material deformed as the thread is formed.
Poor contact will result if this is not done.Another
possible hazard arises when the hole in the heatsink
is formed with a punch: a circular depression may
be formed around the hole, leading to deformation
of the tab. This may be cured by using a washer
or by modifying the punch .

o

o .. .
.. ..

.

Fig. 8 - The recommended screw type looks like
this.

t

Fig. 6 - Contact thermal resistance depends on
tightening torque.
_~8J7

R'h
("OW)

~c:~l~~TT

0.8

0.6

"""

i'
0.4

"

~

~

t!!'hO",

'ili,on~ .J..

siliclne I

reas~ ap~ied

0.2

Torque (Kg/em)

(00"

Serious reliability problems can be encountered if
the heatsink and plrinted circuit board are not
rigidly connected. Either the heatsink must be
rigidly attached to the printed circuit board or
both must be securely attached to the chassis. If
this is not done the stresses and strains induced by
vibration will be applied to the device and in particular to the lead/resin interface. This problem is
more likely to arise when large boards and large
heatsinks are used or whenever the equipment is
subjected to heavy vibrations.

301

DEVELOPMENTS IN SURFACE MOUNTING PACKAGES
FOR POWER INTEGRATED CIRCUITS
Thermal dissipation is recognized as a major problem in Surface Mount Technology. New
. packages are needed, having good thermal characteristics and meeting the SMTrequirements:
reduced size, automatic placement compatibility with the SMT soldering systems.
In this paper, thermal data and measurement methods for the most popular SO and PLCC
packages are reviewed/ some new solutions for surface mountable medium power (up to 2W)
and high power (more than 2W) devices are presented.
INTRODUCTION
A number of problems have been met in introducing the high density. high reliability mass
production of SM systems. This can explain the
experimental work and the complex characterization activity of both ICs suppliers and users.
As discussed elsewhere 11/, the four main areas of
such activity are: standardization, quality, reo
liability after soldering on PC boards and power
dissipation.

A development activity is needed, to cover the
following points:
1) study of the relationship between thermal
resistance of the package and board characteristics (density, lay-out, dissipated power).
As it will be discussed later, this point cannot
be ignored, even at dissipation levels (0.5W
or less), typical of the "signal" packages like SO
and P LCC packages;
2) study of the thermal properties in pulsed
conditions, in order to avoid redundancy and
cost increase;

Fast progress has been made and more confidence
in the SM technology has been achieved in the
first three areas. For example, it was demonstrated
that the most common conditions used in double
wave soldering and vapour phase reflow soldering
do not affect the final reliability of SO packaged
devices (F ig. 1).

Moreover, a lack of standardized methodology
exists when the thermal parameters have to be
measured and compared.

On the contrary, referring to heat dissipation,
progress is less fast, even if this point can strongly
limit PERFORMANCE and COST of the system,
thus losing the two main advantages of the SM
technology, to a certain amount.

In the present paper the above mentioned points
are considered. The characterization activity
running in SGS is presented, together with experimental data and details on development of
new power packages.

3) development of new power packages with reduced thermal resistance and heat transfer
features.

303

Fig. 3 - Calibration curve for P432 sensing diode

is than possible to know the transistor T j , through
the junction temperature of the diode.

G-6107

t-q" -

The evaluation die can be cut in different sizes,
in order to quantify the effect of the die area on
the thermal resistance.

"

~~8

-~

::;..,;
i!J

~~

-i-

-

+

T

MEASUREMENT TECHNIQUE

+ +

The measurement technique is simple /2/ and does
not need to switch the power element from the
dissipation condition to the sensing condition,
thus offering a better accuracy if short pulses
are considered. Indeed, the same resolution cannot
be achieved with other test patterns, in which the
sensing diode is missing (as single power transistors
or diode, ICs substrate diode, etc.).

:-t-+

~:
.;
20

40

"

g.

..

,

".

'"

'"

The measurement circuit is shown in fig. 4. A DC
power supply or a pulse generator biases the
transistors in parallel; a fast voltmeter or a storage
oscilloscope records the diode V f. Resolution
better than 50ns is obtained with this circuit.

The test pattern design ensures that the diode is
positioned on the temperature plateau generated
when the two transistors are biased in parallel; it
Fig. 4 - Measurement circuit with P432
D. C.

D. C.

SUPPLY 1---...,

SUPPLY
FAST

DVM

STORAGE

SCOPE

~r

LJ

5- 946 6

UNMOUNTED (FLOATING) SAMPLES
In order to simulate the thermal behaviour of the
package in the worst condition (as in a high density,
double sided card), samples are connected to 8
thin wires, needed for biasing the two transistors
and the sensing diode. Measurement is performed
on such devices, suspended horizonthally in a
one cubic foot plastic box, to prevent draft.

test boards are obtained from the basic configuration of Fig. 5, as summarized in Tab. 1.
Table 1 - CHARACTERISTICS OF THE TEST
BOARDS FOR SO PACKAGE EVALUATION
Type
SM

SAMPLES SOLDERED ON TEST SUBSTRATES
In order to characterize the thermal properties of
parts mounted on a substrate, samples are reflow
soldered on ceramic and epoxy glass substrates.
For the evaluation of SO packages, the size of the
plastic FR4 test board is fixed while the copper
pattern lay-out can be changed. Seven different
305

Ix

Trace area
1000 sq. mils)

Heatsink

yes
136
no
136
no
21
no
50
10
71
93
no
1E
1F
102
no
- - ' - - - - - - - --- ----substrate: F R4
size:
00.9" x 0.8" x 0.056"

PCB 1 SGS
1B
1A
1C

j "'

Fig. 10 - Rth of on board 50-14 packages vs.
die area

Fig. 7 - Alloy 42 50-8, 14, 16 Rth on board

G-

6_610'J

-"

~

t-

----- r---.

t-- t-- so-'

~
I-

:u:tl.S:SM P

~

-"'r--- r---- ~
room .d

1.18

ALLOY 42 FRAtE

B18 SGS

~

11.21

o ..... d

SD-14

so-u:

on Sf' PCB1SG! board

B.3tl

e.se

B.4&

112

COPPER

e.60

0.7111

n .to:

.,

0.80

DIE AREA ( x 'EllUl 6q. mils)

DISSIPATEDPOt.ER(I.bU.)

THERMAL RESISTANCE OF 68 LEADS
PLCC PACKAGE
Fig. 8 - Rth of copper 50-14 with different
substrates
G-6",

Data concerning DC and pulsed conditions are
obtained for this package /3/. which has Jedec
outline and copper crame.

G- 6113

I'----

.........

r--.

r-- ,--..'-

n~

... .,.

'

-" Man

~

b...

t-- I--

'"PC 1800

boor

t--

SM PC 1 SO

boar

i2 iii

~

9

8.28 8.38 B.4B 8.511

~

~

§ iil
~

alum!. Ii

Dl551PA'T[D

ill

~

I

St1PC lA SG

B.tl!!

11 - Rth of "FLOATING" 68 lead PLCC

Fig.

II.S0 8.70 B.80
PDLER ( \.btl )

0.9a

1.00

~

1.1111

eI

~

i=
~
8,~

Fig. 9 - Rth of copper 50-14 vs. board trace area

B.40

e.~
1.00 1.~ 1.48
DISSIPATED POL£R ( !.btl )

a.~

1.60

1.SB

2.00

Fig. 12 - Rth of 68 lead PLCC mounted on board
(Die pad area A = 300x300 sq. mils; 8 = 425x
425 sq. mils)

6-6110

\

...._II·

Boa d

Pd

1\

"'l'---1--

8.2eq. inc:;h

'-

1-+

1+

I
~

~

6B
~
100
1~
1411
TRACE AREA ( x lilBB sq. mHr. )

160

,~

200

B.60

307

lose
2.00
DISSIPATED POt.[R ( IJall )

2.50

3.00

Fig. 17 - Medium power 33+11 lead PLCC frame

Fig. 16 - Medium power 50-20 frame

5- 9469

5-9468

Rthj-amb

90°C/W

Rthj-amb

55°C/W

Rthj-sUb

14°C/W

Rthj-SUb

12°C/W

Max die size

125x205 mils

Max. die size

195x195 mils

Fig. 18 - Typical application (2W) of PLCC+ 11 with external heatsink integrated are the printed board

Heat sink
on board

'j-

900

Additionally. the frame can be modified to incorporate dissipating 'fins' within the plastic body
for a further reduction of the junction-to-ambient
thermal resistance. In PLCC these fins are obtained
easily at the corner of the package by sacrificing
signal pins.
Due to availability of a high number of leads mils
in PLCC, the reduction of useful pins is not a
problem and junction to-ambient thermal resistances can be obtained in the range of 30-

40° C/W, for the dissipation of 1.5-2W without
any need of external heatsinks.

HIGH POWER SM PACKAGES
For IC's dissipating more than about 2W a different approach is needed.
One obvious solution is simply to form the leads
of standard power packages so that they can be

309

DATASHEETS

311

lIB.

PRELIMINARY DATA

QUAD HIGH SPEED DIFFERENTIAL LINE DRIVER
The circuit provides an enable and disable func·
tion common to all four drivers. The AM26LS31
features 3-state outputs and logical OR-ed complementary enable inputs. The inputs are all LS
compatible and are all one unit load.

• OUTPUT SKEW -2.0ns TYPICAL
•

INPUT TO OUTPUT DELAY -12ns

• OPERATION FROM SINGLE +5V SUPPLY
•

OUTPUTS
Vee = 0

WON'T

LOAD

LINE

WHEN

• OUTPUT SHORT-CIRCUIT PROTECTION
• COMPLEMENTARY OUTPUTS
•

MEETS THE REQUIREMENTS OF EIA
STANDARD RS-422

•

HIGH OUTPUT DRIVE CAPABILITY FOR
100n TERMINATED TRANSMISSION
LINES

DIP-16 Plastic (0.25)
and Ceramic

The AM26LS31 is a quad differential line driver,
designed for digital data transmission over bal·
anced lines. The AM26LS31 meets all the reo
quirements of EIA standard RS-422 imd federal
standard 1020. It is designed to provide unipolar
differential drive to twisted-pair or parallelwire transmission lines.

SO-16J

ABSOLUTE MAXIMUM RATINGS
Supply voltage
Input voltage
Output voltage
Storage temperature range

7
7
5.5
-65 to 150

Fig. 1 - Typical Application
TWO WIRE BALANCED SYSTEM RS422
ENABLE

I

I

I

I
I

I

DATA

_Zo

Zo~
I

I

I

1

DATA
OUTPUT

5-9165

313

12/86

THERMAL DATA

Rth j-amb

= -SSoC to 12SoC.

DIP-16
Plastic

80-16

max.

Thermal resistance junction-ambient

ELECTRICAL CHARACTERISTICS
Tamb

DIP-16
Ceramic

(The following conditions apply unless otherwise specified:
Vee = SV ± 100fa; Tamb
0 to + 70°C. Vee
SV ± SOfa)

Parameter

=

=

Test Conditions

Min.

Typ.
(Note 1)

2.5

3.2

Max.

Unit

V OH

Output HIGH Voltage

Vcc= Min •• 10H= -20mA

VOL

Output LOW Voltage

Vee= Min .• 10L= 20mA

VIH

Input HIGH Voltage

Vee= Min.

VIL

Input LOW Voltage

Vee= Max.

IlL

Input LOW Current

Vee= Max., VIN=O.4V

IIH

Input HIGH Current

Vee= Max., VIN= 2.7V

0.5

20

IJA

II

InPl!t Reverse Current

Vee= Max., VIN= 7.0V

0.001

0.1

mA

10

Off-State (High Impedance)
Output Current

Vee = Max.

VI

Input Clamp Voltage

Vee= Min., IIN= lSmA

0.32

V
0.5

V
V

2.0

-0.20

O.S

V

-0.36

mA

VO= 2.5V

0.5

20

Vo=0.5V

0.5

-20

IJA

-30

-O.S

-1.5

V

-60

-150

mA

Ise

Output Short Circuit Current

Vee= Max.

Icc

Power Supply Current

Vee= Max., all outputs disabled

60

SO

mA

tpLH

Input to Output

Vee= 5.0V, T amb = 25°C,

Load = Note 2

12

20

ns

tpHL

Input to Output

Vee= 5.0V. T amb = 25°C,

Load = Note 2

12

20

ns

Vee= 5.0V. T amb = 25°C.

Load=Note 2

2.0

6.0

ns

23

35

ns

SKEW Output to Output
Enable to Output

Vee= 5.0V, T amb = 25°C, CL = 10pF

tHZ

Enab Ie to Output

Vee= 5.0V, T amb = 25°C, CL= 10pF

17

30

ns

tZL

Enable to Output

Vee= 5.0V, T amb = 25°C.

Load=Note 2

35

45

ns

tZH

Enab Ie to Output

Vee= 5.0V. Tamb = 25°C,

Load=Note 2

30

40

ns

tLZ

Notes: 1. A typical values are Vee = 5.0V, Tamb = 25°C
2. CL =30pF, VIN = 1.3Vto VOUT= 1.3V, VpULSE=OVto +3.0V, See Below.

315

aB.

PRELIMINARY DATA

RS422 AND RS423 QUAD DIFFERENTIAL
LINE RECEIVERS
THE AM26LS32 MEETS ALL THE REQUIREMENTS OF RS-422 AND RS-423

The AM26LS33 features an input sensitivity of
500mV over the input voltage range of ± 15V.

•

6K MINIMUM INPUT IMPEDANCE

•

30mV INPUT HYSTERESIS

•

OPERATION FROM SINGLE +5V SUPPLY

•

FAIL SAFE INPUT-OUTPUT RELATIONSHIP. OUTPUT ALWAYS HIGH WHEN
INPUTS ARE OPEN

The AM26LS33 provide an enable and disable
function common to all four receivers. Both
parts feature 3-state outputs with 8mA sink
capability and incorporate a fail safe inputoutput relationship which keeps the outputs
high when the inputs are open.

•

THREE-STATE DRIVE, WITH CHOICE OF
COMPLEMENTARY OUTPUT ENABLES,
FOR RECEIVING DIRECTLY ONTO A
DATA BUS

•

•

DIP-16 Plastic (0.25)
and Ceramic

PROPAGATION DELAY 17ns TYPICAL

The AM26LS32 is quad line receiver designed to
meet the requirements of RS-422 'and RS-423,
and Federal Standards 1020 and 1030 for balanced and unbalanced digital data transmission.

SO-16J

The AM26LS32 features an input sensitivity
of 200mV over the input voltage range of ± 7V.

ABSOLUTE MAXIMUM RATINGS
V5
CM R
Vi
VE
los
Tstg

Supply voltage
Common mode range
Differential input voltage
Enable voltage
Output sink current
Storage temperature range

7
± 25
± 25
7
50
-65 to 150

V
V
V
V
mA

°c

Fig. 1 - Typical Applications
Two wire balanced system, RS-422
ENABLE

I

I

I

I

I

DATA

zo~

:'--zo

I

I

I

I

I

I

Single wire with common ground imbalanced system, RS-423
DATA

Zo-1I
50- 9116

317

12/86

ELECTRICAL CHARACTERISTICS (The following conditions apply unless otherwise specified: Tamb = _55°C
to

125°C, Vee

= 5V ± 10%; Tamb = 0 to 70°C,

Vee

= 5V ± 5%)

Parlmeter

VTH

Min. Typ. (1) MIX.

Test Conditions

Differential Input Voltage.

AM26lS32, -7V'; VeM .; +7V

-0.2

±0.06

+0.2

AM26lS33, -15V'; V eM '; +15V

-0.5

±0.12

+0.5

6.0

9.B

Unit

V

VOUT= VOL or VOH

RIN

Input Resistance

-15V'; VeM'; +15V (One input AC groundl

liN

Input Current (Under Testl

V IN = +15V, Other Input -15V'; VIN'; +15V

2.3

mA

liN

Input Current (Under Testl

VIN = -15V. Other input -15V'; VIN" +15V

-2.B

mA

VOH

Output HIGH Voltage

VOL

KG

Vee = Min.,11 VIN = +1.0V

COM'l

2.7

3.4

VENABCE = O.BV. 10H = -4401'A

Mil

2.5

3.4

Vee = Min., II V IN = -1.0V

10L =4.0mA

0.4

VENABLE = O.BV

10L =B.OmA

0.45

V

Output lOW Voltage

V

VIL

Enable lOW Voltage

VIH

Enable HIG H Voltage

VI

Enable Clamp Voltage

Vee = Min •• liN = -lBmA

10

Off-State (High Impedancel
Output Current

Vee= Max.

IlL

Enable lOW Current

IIH
II

O.B

V

-1.5

V

2.0

V

Vo = 2.4V

20

Vo = O.4V

-20

I'A

V IN = O.4V

-0.2

Enable HIGH Current

V IN = 2.7V

0.5

20

I'A

Enable Input High Current

VIN = 5.5V

1

100

I'A

Ise

Output Short Circuit Curro

Vo = OV, Vee = Max.,IIVIN = +1.0V

-50

-B5

mA

70

mA

-15

-0.36

mA

Icc

Power Supply Cu rrent

Vee = Max., All VIN = GND. Output Disabled

52

VHYST

Input Hysteresis

T amb = 25°C, Vee = 5.0V, V eM = OV

30

tpLH

Input to Output

Tamb = 25°C, Vee = 5.0V, CL = 15pF, see test condo below

17

25

ns

tpHL

Input to Output

Tamb = 25° C, Vee = 5.0V, CL = 15pF. see test condo below

17

25

ns

tLz

Enable to OUtput

Tamb = 25°C, Vee = 5.0V, CL = 5pF, see test condo below

20

30

ns

tHZ

Enable to Output

Tomb = 25°C, Vee = 5.0V. CL = 5pF, see test condo below

15

22

ns

tZL

Enable to Output.

T. mb = 25°C, Vee = 5.0V. CL = 15pF, .ee test condo below

15

22

ns

tZH

Enable to Output

Tomb = 25°C, Vee = 5.0V, CL = 15pF, see test condo below

15

22

ns

(1) All typical value. are Vee

= 5.0V,

T 1mb = 25°C

319

mV

9B.

PRELIMINARY DATA

12-BIT HIGH SPEED MULTIPLYING D/A CONVERTERS
The AM6012 is an industry standard monolithic 12-bit
digital-to analog converter. Complementary current
output and high speed multiplying capability make
the AM6012 useful in a wide range of applications
such as video displays, process control circuitry and
fast AID converters. The 6012 is the first DI A to
achieve 12-bit differential linearity without the use of
thin film resistors or active trimming. The 6012's unique circuit design insures monotonicity without the
precision trimming associated with most other 12-bit
DAC architectures.
The AM6012 is packaged in a 20-pin plastic DIP and
is SO-20L for surface mounting. Although tested and
specified at ± 15V, the AM6012 works well over a
wide range of power supply voltages. Performance
is essentially independent of supply voltage over the
range of + 5 volts, -12 volts to ± 18 volts. The
AM6012 series guarantees full 12-bit monotonicity for
all grades and differential nonlinearity as high as
0.012% (13 bits) for the A grades and 0.025% (12
bits) for the standard grades over the entire temperature range.
Guaranteed monotonicity and low cost make the
AM6012 an ideal choice for high volume applications
requiring fine local resolution. Typical applications include printer graphics and video displays. These applications need a minimum of 12 bits of resolution,
although conformance to an ideal straight line from
zero to full scale is less important.

BLOCK DIAGRAM

• ALL GRADES 12-BIT MONOTONIC OVER
TEMPERATURE
• DIFFERENTAL NONLINEARITY TO ±0.012%
(13 BITS) MAX OVER TEMPERATURE
(A GRADES)
• 250ns TYPICAL SETTLING TIME
• FULL SCALE CURRENT 4mA
• HIGH SPEED MULTIPLYING CAPABILITY
• TTLlCMOS/ECLlHTL COMPATIBLE
• HIGH OUTPUT COMPLIANCE: - 5V TO

+ 10V

• COMPLEMENTARY CURRENT OUTPUTS
• LOW POWER CONSUMPTION: 230mW

DIP-20 Plastic (X3P2)

MSB

SO-20L

LSB

B1

B2

2

B3

B4 B5 B6 B7 BB B9 B10 B11 B12

3

SEGMENT
AM6012

REFERENCE

20

R R R R
CODE SELECTED

NETWORK

+VS

0111 1111 1111

SEGMENT GENERATOR

17

A6tJIR-1

VEE
321

13

GND
11/86

ELECTRICAL CHARACTERISTICS
These specifications apply for Vs =
ge unless otherwise specified

+ 15V, VEE = -15V, IREF = 1.0mA, over the operating temperature ranAM6012A

Paramo

D.N.L.

AM6012

Min.

Typ.

Max.

Min.

Typ.

Max.

Units

Resolution

12

12

12

12

12

12

Bits

Monotonicity

12

12

12

12

12

12

Bits

-

-

±.012

-

-

±.025

%FS

13

-

12

-

-

Bits

-

-

±.05

-

-

±0.05

%FS

3.967

3.999

4.031

3.935

3.999

4.063

rnA

-

±5

±20

-

±10

±40

ppmoC

Description

Differential
Nonlinearity

Test Conditions

Deviation from ideal step size

N.L.

Nonlinearity

Deviation from ideal straight line

IFS

Full Scale Current

VREF= 1O.000V
R14= R15= 10.000k!l
TA = 25°C

TCIFS

Full Scale Temp.Co.

Voe

Output Voltage
Compliance

D.N.L. Specification guaranteed
over compliance range
ROUT> 10 megohme typo

IFSS

Full Scale
Symmetry

IFS-IFS

Izs

Zero Scale Current

-

-

±.OOO5

±.002

-5

-

+10

-5

-

±0.2

±1.0

-

±.OOl
-

±.004 %FSOC

+10

V

±0.4

±2.0

"A

-

-

0.10

-

-

0.10

"A

-

250

500

-

250

500

nSec

-

25

50

-

25

50

nSec
pF

IS

Setting Time

To ± 112 LSB, all bits ON or
OFF, TA =25°C

tpLH
tpHL

Propagation
Delay - all bits

50% to 50%

COUT

Output Capacitance

-

20

-

-

20

-

VIL

Logic "0"

-

-

0.8

-

-

0.8

VIH

Logic
Input
Levels

Logic "1"

2.0

-

-

2.0

-

-

liN

Logic Input Current

VIN=-5to +18V

-

-

40

-

-

40

"A

VIS

Logic Input Swing

VEE= -15V

-5

-

+18

-5

-

+18

V

IREF

Reference Current
Range

0.2

1.0

1.1

0.2

1.0

1.1

rnA

0

-0.5

-2.0

0

-0.5

-2.0

~A

1,5

Reference Bias
Current

323

V

APPLICATION INFORMATION
accuracy is often referred to as nonlinearity. The DAC
transfer function shown in Figure 1 has a bow that
results in a maximum relative accuracy error of 3LSB.
This must be distinguished from a differentiallinearityerror. Differential nonlinearity is the measure of
the variation in analog value, normalized to full scale, associated with 'a ILSB change in digital input
code.
For example, for a 4mA full scale output, a change
of ILSB in digital input code should result in a 0.98!LA
change in the analog output current
(ILSB = 4mA x 1/4096 = 0.98!LA). If in actual use,
however, a ILSB change in the input code results
ina change of only 0.24!LA (1/4LSB) in output current, the differential linearity error would be 0.74!LA
or 3/4LSB.
The AM6012 has very good differential linearity in
spite of the porr relative accuracy. Conversely, the
DAC of Figure 1 has very good relative accuracy
but poor differential linearity. The anomaly in the
middle of the transfer function is the result of a positive differential linearity error followed by a negative differential linearity error greater than 1LSB.
A negative output step for an increase in digital input code is referred to as nonmonotonic behavior.
In general, if a DAC has a differential linearity error specification greater than 1LSB, it may be nonmonotonic at one or more of the major carries. In
most case the worst differential linearity error will
occur at the MSB transition point.
As noted in the functional description, the 6012's
unique design minimizes differential linearity errors
at the transition points of the 3MSBs. This results
in a tight specification on maximum differential nonlinearity over temperature. Differential linearity is
verified on all AM6012s with 100% final testing.
In many converter applications, uniform step size
(or minimum differential linearity error) is more important than conformance to an ideal straight line.
Twelve-bit onverters are usually needed for high
resolution rather than high linearity as evidenced
by the fact that few transducers are more linear
than 0.1 %. This is also true in video graphics, where the human eye has difficulty discerning nonlinearity of less than 5%. The AM6012 is especially
well suited for these applications since it has inherently low differential linearity error.

FUNCTIONAL DESCRIPTION
The segmented design of the AM6012, shown in the
block diagram, insures that there are no significant
differential nonlinearities in the transfer characteristic. The eight major carries of the most significant
bits are not subject to the gross differential nonlinearities that can occasionally occur in an R-2R type
DAC. This advantage is due to the fundamentally different way that the current is handled in an AM6012.
In a conventional R-2R type DAC, when the input
code is increemented past a major carry, a current
representing the new code is substituted for the sum
of all the less significant bit currents that were previously on. To avoid any nonlinearities, the two total currents must be extremely well matched. In the
case of the MSB major carry in a 12-bit DAC, the
match must be better than one part in 2048 to maintain monotonicity. However, in the AM6012, a new
current is never substituted for the sum of several
smaller ones, but redirected through alternate channels and incremented one step at a time.
For example, consider the MSB carry in an AM6012.
In the initial state of 011111111111 as shown in the
block diagram, the switches in the segment generator are set in such a way that currents 10, II and 12
are steered directly into the noninverting output
lOUT. In addition, a portion of 13 is directed through
the 9-bit DAC that is controlled by the 9 least significant bits into lOUT. With the 9LSBs set to "I", all
of the 13 current is directed to lOUT except for the
11512 that goes to ground through the right-most
transistor in the 9-bit DAC. After the input word is
changed to 100000000000, the segment decoder
switch for 13 will be all the way to the right, the
switch for 14 will be in the middle, and all the switches in the 9-bit DAC will be to the left. lOUT will
be composed of 10, 11, 12 and 13. None of 14 will be
directed into lOUT until a higher code is reached. In
other words, 13 is now steered directly to lOUT instead of being divided by a factor of 511/512 in the
9-bit DAC. Since no major current substitution occurs, there is less chance of a large nonlinearity at
this transition than in a comparable R-2R DAC.
RELATIVE ACCURACY VS. DIFFERENTIAL NON·
LINEARITY
SGS defines relative accuracy as the maximum deviation of the actual, adjusted DAC output from the
ideal analog output (a straight line drawn between
the lowest code output voltage and the highest code output voltage) for any bit combination. Relative

325

APPLICATION INFORMATION (Continued)
Fastest operation can be octained by using short
leads, minimizing output capacitance and load resistor values, and by adequate bypassing at the supply, reference, and VLC terminals. Supplies do not
require large electrolytic bypass capacitors as the supply current drain is independent of input logic states; 0.1 p.F capacitors at the supply pins provide full
transient protection.

MULTIPLYING OPERATION
The AM6012 provides excellent multiplying performance with an extremely linear relationship between
IFS and IREF over a range of 1mA to 1p.A. Monotonic operation is maintained over a typical range of
IREF from 100p.A to 1.0mA.
REFERENCE AMPLIFIER COMPENSATION FOR
MULTIPLYING APPLICATIONS
AC reference applications will require the reference
amplifier to be compensated using a capacitor from
pin 16 to V - . The value of this capacitor depends
on the impedance presented to pin 14. For R14 values of 1.0, 2.5 and 5 Okll; minimum values of Cc
are 5, 12 and 25 pF. Larger values of R14 require
proportionately increased values of Cc for proper
phase margin (See Figure 4 and 5).
For fastest response to a pulse, low values of R14
enabling small Cc values should be used. If pin 14
is driven be a high impedance such as a transistor
current source, none of the above values will suffice and the amplifier must be heavily compensated which will decrease overall compensated which
will decrease overall bandwidth and slew rate. For
R14=1kll and CC=5pF, the refe'renee amplifier
slews at 4mAlms enabling a transition from
IREF = 0 to IREF = 1mA in 250ns.
Operation with pulse inputs to the reference amplifier may be accommodated by an alternate compensation scheme. This technique provides lowest
full scale transition times. An internal clamp allows
quick recovery of the reference amplifier from a cutoff (IREF = 0) condition. Full scale transition (0 to
1mA) occurs in 62.5ns when the equivalent impedance at pin 14 is SOOll and Cc = O. This yields a
reference slew rate of SmAIl'S which is relatively
independent of RIN and VIN values.

REFERENCE AMPLIFIER SETUP
The AM6012 is a multiplying Df A converter in which
the output current is the product of a digital number
and the input reference current. The reference current may be fixed or may vary from nearly zero to
+ 1.0mA. The full range output current is a linear
function of the reference current and is given by:

4095
IRF= --x4x(lREF)=3.999IREF,
4096
where IREF= 114
In positive reference applications, an external positive reference voltage forces current through R14 into
the VREF( +) terminal (pin 14) of the reference amplifier. Alternatively, a negative reference may be applied to VREF( -) at pin 15. Reference current flows
from ground through R14 into VREF(+) as in the
positive reference case. This negative reference
connection has the advantage of a very high impedance presented at pin 15. The voltage at pin
14 is equal to and tracks the voltage at pin 15 due
to the high gain of the internal reference amplifier.
R15 (nominally equal to R14) is used to cancel bias
current errors. (Figure 3).
Bipolar references may be accommodated byoffsetting VREF or pin 15. The negative commonmode range of the reference amplifier is given by:
VCM - = V - plus (IREF x 3kll) plus 1.SV. The positive common-mode range is V + less 1.23V.
When a DC reference is used, a reference bypass
capacitor is recommended. A 5.0V TIL logic supply is not recommended as a reference. If a regulated power supply is used as a reference, R14
should be split into two resistors with the junction
bypassed to ground with a 0.1p.F capacitor.
For most applications the tight relationship between
IREF and IFS will eliminate the need for trimming
IREF. If required, full scale trimming may be accomplished by adjusting the value of R14, or by
using a potentiometer for R14.

327

Fig. 4 . Minimum size compensation capacitor
IIFS=4mA. IREF=1.0mA)
R14(Ea~Km

Fig. 5 . Reference Amplifier Frequency response

(dB)

Cc(pF)

10

I

-1=

50
25

5
2
1
5

10

3

5
0

o

Note: A 0.01 /IF capacitor is recommended for fixed reference operation.

SMALL SIGNAL
LARGE SIGNAL

---- k,\
\1\

-3
-6

r'\
\'\

R14=2K I
Cc=10pF I
I

-1

0.1

0.01

1

10
(MHz)

A6012-11:: DI

Fig. 6 . Interfacing Circuits

Fig. 7 . Accomodating Bipolar Reference

CMOS
+ 15V

VREF +

470
RREF
lin

VIN

itA"

a

IREF

RIN

PIN 13

IREF > PEAK NEGATIVE SWING OF Iin

ECl
~REF

(+)

~

13K

"A"

RREF 14r---~ 18 10
~
AM6012

~

15

VIN HIGH INP UT

y:=.-o
f--:-:::-o

19 10

IMPEDANCE

a

VREF

PIN 13

6.2K
-

5.2V

329

(+)

MUST BE ABOVE PEAK POSITIVE SWING OF VIN

Fig. 9 . Basic Negative Reference Operation

VREF(-)

~

~

R15

AM6012

Fig. 10 - Recommended Full-scale Adjustment Circuit

~
/-:-;;-0

RREF

VREF
+ 5V

4.5K

39K

15L-------~ 19 10

10K

Fig. 11 - CRT Display Driver

+120V DC

6gv
COMMON
M DE LEVEL
"X" INPUT

"Y' INPUT

-

-+

10

fci

A60t2-5: : LI

Fig. 12 - 12-BIT High-Speed AID Converter

CLIICIC

LIB
+iIiV

ANAUIII IN

co-sOY)

+ lOY

II_OOOK

IEF

II 8001<

I

-

AM6012
COMP

SOIIF suF

SuF

vc+)

VI-)

331

At1f)I2-11: : LIB

fl.

PRELIMINARY DATA

8-BIT D/A CONVERTERS
±0.19% assure 8-bit monotonicity and linearity while
zero level output current of less than 4 p.A provides
8-bit zero accuracy for IREF~2 rnA. The power supply currents of the DAC0808 series are independent
of bit codes, and exhibits essentially constant device characteristics over the entire supply voltage
range.

• RELATIVE ACCURACY: ±0.19% ERROR MAXI-.
MUM (DAC0808)
• FULL SCALE CURRENT MATCH: ± 1 LSB TYP
• 7 AND 6-BIT ACCURACY AVAILABLE (DAC0807,
DAC0806)
• FAST SETTING TIME: 150 ns TYP

The DAC0808 will interface directly with popular TTL,
or CMOS logic levels, and is a direct replacement for
the MC1508/MC1408.

• NONINVERTING DIGITAL INPUTS ARE TTL
AND CMOS COMPATIBLE
• HIGH SPEED MULTIPLYING INPUT SLEW RATE: 8 mAIlls
• POWER SUPPLY VOLTAGE RANGE: ±4.5V to
±18V
• LOW POWER CONSUMPTION: 33 mW @±5V
The DAC0808 series is an 8-bit monolithic digital-toanalog converter (DAC) featuring a full scale output
current settling time of 150 ns while dissipating only
33 mW with ±5V supplies. No reference current
(lREF) trimming is required for most applications since the full scale output current is typically ± 1 LSB
of 255 IREF/256. Relative accuracies of better than

SO-16

DIP-16 Plastic (0.25)
and Ceramic

BLOCK DIAGRAM

+VS

Ai

A2

A3

A4

A5

AS

A7

AS

+U-~--+---~
VREF

DACOBOB-J

333

11/86

ELECTRICAL CHARACTERISTICS
rnA, TA=TMIN to TMAX and ali digital inputs at high logic level

(Vs=5V, VEE= -15V, VREF/R14 = 2
unless otherwise noted.)
Paramater
E,

Relative Accuracy (Error Relative
to Full Scale 10)
DAC0808L
(Note 1)
DAC0807LC/Dl
(Note 1)
DAC0806LC/Dl
Settling Time to Within 1/2 LSB
(Includes tPLH)

Test Conditions

Propagation Delay Time

MSB
VIH
VIL

Digital Input Logic Levels
High Level, Logic "1"
Low Level, Logic "0"

MSB

Digital Input Current
High Level
Low Level

VIH=SV
VIL=0.8V

Reference Input Bias Current
Output Current Range

(Figure 3)
(Figure 9)

SRIREF

Reference Current Siew Rate
Output Current Power Supply
Sensitivity

%
%
%
ns

100

ns
ppm/oC

(Figure 9)

2
0.8

VOC
VDC

0
-0.003

0.040
-0.8

rnA
rnA

-1

-3

(Figure 9)

/LA

0
0

2.0
2.0

2.1
4.2

rnA
rnA

1.9

1.99
0

2.1
4

rnA

-0.55,+0.4
-S.O ,+0.4

V
V

2.7

mAI/Ls
/LAN

VREF=2.000V.
R14=10001l
(Figure 9)
(Figure 9)

E,sO.19%, TA =2SoC

(Figure 14)

4

-SVsVEEs -16.SV
(Figure 9)

Power Supply Voltage Range
Vs
VEE

TA=2SoC (Figure 9)

All Bits High

30
±20

Power Supply Current (All Bits Low)
Is
lEE

Power Dissipation
All Bits Low

150

TA=2SoC (Figure 11)

VEE= -SV
VEE= -lSV, TA=2SoC

Output Current, All Bits Low
Output Voltage Compliance
VEE= -SV
VEE Below -10V

Unit

(Figure 11)

Output Full Scale Current Drift

Output Current

Max.

%

TA=2SoC (Note 2)

TClo

10

Typ.

±0.19
±0.39
±0.78

tpLH
tpHL

115

Min.

(Figure 10)

8
O.OS

2.3
-4.3
4.S
S.O
-4.S -lS
VS=SV,VEE= -SV
VS=SV,VEE= -lSV
VS=lSV,VEE= -SV
VS=lSV,VEE= -lSV

Note 1: All current switches are tested to guarantee at least 50% of rated current.
Note 2: All bits switched.
Note 3: Range control is not required.

335

33
106
90
160

22
-13
S.S
-16.S
170
30S

!LA

rnA

V
mW
mW
mW
mW

Test Circuits
FIGURE 9. Notation Definitions

+VS
13

VREF
A2

The resistor tied to pin 15 is to temperature compensate the bias current and may not be necessary for
all applications.

A3
A4

A5

IO=K ( A1 +A2+A3+A4 +A5 +A6+ A7 + A8 )
16 32 64 128 256
2
4
8

A6

where K == VREF
R14
and AN = "1" if AN is at high level
AN = "0" if AN is at low level

FIGURE 10. Relative Accuracy

At

Ir~~~~

t2 BIT I-v_o--o0_t...,o tOV

AB

B BIT 1--C:>--'+I++-o--1
C~T~I-~--~~H----_-~OUT

5-4019/1

345

3/85

THERMAL DATA
Rth j-case

Thermal resistance junction-case

max

ELECTRICAL CHARACTERISTICS (TJ = 25°C, Vs
Parameter
Vs

-

Test conditions

Min.

Typ.

lin

I nput current

Vs=±16V

Vi =OV

hFE

DC current gain

Vs=±16V

10=3A

Gy

Voltage gain

Vs=±16V

10 = 1.5A

VeEsat

Saturation voltage
(for each transistor)

lo=3A

Vos

Input offset voltage

Vs=±16V

V 1NH

Inhibit input voltage
(pins 1-3)

ON condition

200

Slew rate
Power bandwidth

V

/J A

-

1
3.5

V

0.3

V

± 0.3

V
± 1.8

I nhibit input resistance

SR

400

10000

6000

Unit

mA

30

OFF condition

B

Max.
± 20

Supply voltage
Vs= ± 16V

RINH

°C/W

= ± 16V)

Quiescent drain current

Id

3

Vo = ± 10V,d = 1%, R L =8n

2.0

Kn

30

VII's

200

KHz

APPLICATION INFORMATION
Fig. 1 - High slew-rate power operational amplifier (SR = 13VlJ,ts)
• 'Is
lN4001

4

R5

HI
C6

o.11lF

lN4001
-Vs

5-3934/1

347

aB.
3A POWER OPERATIONAL AMPLIFIER
•

OUTPUT CURRENT UP TO 3A

•

LARGE COMMON-MODE AND DIFFERENTIAL MODE RANGES

•

SOA PROTECTION

•

THERMAL PROTECTION

plies. The high gain and high output power capability provide superior performance wherever
an operational amplifier/power booster combination is required.

• ± 18V SUPPLY

Pentawatt®

The L165 is a monolithic integrated circuit in
Pentawatt® package, intended for use as power
operational amplifier in a wide range of applications, including servo amplifiers an.d power sup-

ORDERING NUMBER: L165V

ABSOLUTE MAXIMUM RATINGS

V,

Supply voltage
Upper power transistor VCE
Lower power transistor VCE
I nput voltage
Differential input voltage
Peak output current (internally limited)
Power dissipation at Tease = 90°C
Storage and junction temperature

Vs - V 4

V4

-

V3

Vi
Vi

10
Ptot
Tstg , Tj

± 18
36
36
V,
± 15
3.5
20
-40 to 150

V
V
V
V
A
W
°c

APPLICATION CIRCUITS
Fig. 1 - Gain> 10

Fig. 2 - Unity gain configuration

10KI1

IOKIl

IKIl

R2

S-I,J42

RI

349

12/86

ELECTRICAL CHARACTERISTICS (VS
Parameter
Vs

Supply voltage

Id

Quiescent drain current

Ib

I nput bias cu rrent

± 15V, Tj = 25°C unless otherwise specified)
Test conditions

Min.

Typ.

Max.

Unit

±18

V

40

60

rnA

0.2

1

IlA

±6

Vs = ± 18V
Vas

Input offset voltage

±2

±10

mV

los

Input offset current

±20

±200

nA

SR

Slew-Rate

Gv= 10

8

Gv= 1 (0)

6

VIlls

Output voltage swing

Va

f = 1 kHz

Ip = 0.3A
Ip = 3A

27
24

Vpp

f=10kHz

Ip = 0.3A
Ip =3A

27
23

Vpp

500

Kn

80

dB

2

IlV

100

pA

70

dB

Gv = 10

60

dB

G v = 100

40

dB

Input resistance (pin 1)

Ri

100
f = 1 KHz

Gv

Voltage gain (open loop)

eN

Input noise voltage
B = 10 to 10 000 Hz

iN

I nput noise current

CMR

Common mode rejection

Rg':; 10 Kn

SVR

Supply voltage rejection

Rg= 22 kn
VriPPJe= 0.5 Vrms
friPPJe= 100 Hz

Efficiency

11

Gv = 30 dB

f = 1 kHz lip = 1.6A; P0 = 5W
R L=4n IIp=3A;

Tsd

(0)

Thermal shut-down case
temperatu re

Po = 18W

70
60

Ptat = 12W

110

Ptot = 6W

130

Circuit of fig. 2

351

%
%
°C

Fig. 10- Motor current control circuit with external power transistors (Imotor

> 3.5A)

• Vs max36Y

36Kn.

10Kll.

Rl*

R2*

3.3 KA 2·'.
r--------~---~~~~~~----.------~-{R=7:::J----~~R8
Q,22pF

IOKfi

3.3Kfl

36Kfl
Vi =0 ... !BVo--C:::J_-4--{=J---------+-------C::J---~------------..J

01 to 04:

..L

n-iCJ-+-ov•

RJ
5-1,.12/,

Fig. 30- Light controller

363

• C VoR
0.45

II.

PRELIMINARY DATA

DUAL POWER OPERATIONAL AMPLIFIERS
•

OUTPUT CURRENT TO 1A

•

OPERATES AT LOW VOLTAGES

The high gain and high output power capability
provide superior performance whatever an operational amplifier /power booster combination is
required.

• SINGLE OR SPLIT SUPPLY
•

LARGE COMMON-MODE AND DIFFERENTIAL MODE RANGE

•

GROUND COMPATIBLE INPUTS

•

LOW SATURATION VOLTAGE

• THERMAL SHUTDOWN
The L272 and L272M are monolithic integrated
circuits in powerdip and minidip packages intended for use as power operational amplifiers in
a wide range of applications including servo amplifiers and power supplies, compact disc, VCR, etc.

Powerdip 8 + 8

Minidip Plastic

ORDERING NUMBERS:
L272

L272M

ABSOLUTE MAXIMUM RATINGS
Supply voltage
Input voltage
Differential input voltage
DC output current
Peak output current (non repetitive)
Power dissipation at Tamb = 80°C (L272), Tamb = 50°C (/-272M)
T case = 75°C (L272)
Storage and junction temperature

28
Vs
± Vs
1
1.5
1

V

A

A
W

5

W

-40 to 150

°c

BLOCK DIAGRAM

",

'.9-'6
L272M

L272

365

12/86

ELECTRICAL CHARACTERISTICS (Vs = 24V.
Parameter
Vs

Su pply voltage

Is

Quiescent drain current

Tamb

= 2SoC unless otherwise specified)

Test Conditions

Min.

Typ.

4

V0 =

Vs
2

Max.

Unit

28

V

Vs = 24V

8

12

mA

V s = 12V

7.5

11

mA

Ib

Input bias current

0.3

2.5

/JA

Vos

I nput offset voltage

15

60

mV

los

I nput offset current

50

250

mA

SR

Slew rate

B

Gain-l>andwidth product

RI

I nput resistance

Gy

O. L. voltage gain

1

V!/Js

350

KHz
KO

500
70

dB

f = 1KHz

50

dB

f = 100Hz

60

eN

Input noise voltage

B = 20KHz

10

/JV

IN

Input noise current

B = 20KHz

200

pA

CRR

Common Mode rejection

f = 1 KHz

60

75

dB

SVR

Supply voltage rejection
54

70
62
56

dB
dB
dB

23
22.5

V
V

60
60

dB
dB

0.5

%

145

·C

f = 100Hz

Vs =24V
Vs = ±12V
Vs = ± 6V

RG = 10KO
VR = 0.5V
Vo

Output voltage swing
Ip = 0.1A
Ip = 0.5A

Cs

Channel separation

d

Distortion

TSd

Thermal shutdown
junction temperature

f= 1KHz; RL = 100; Gv =3OdB
Vs = 24V
Vs = ± 6V
Gy = 30dB
RL = 00

f = 1KHz
Vs = 24V

367

21

APPLICATION SUGGESTION
NOTE

In order to avoid possible instability occurring
into final stage the usual suggestions for the
linear power stages are useful, as for instance:
- layout accuracy;

A 100nF capacitor corrected between supply
pins and ground;
boucherot cell (0.1 to 0.2/lF + 112 series) between outputs and ground or across the load.

Fig.9 - Bidirectional DC motor control with /lP compatible inputs

V51 = logic supply voltage
Must be V52

> V51

E 1, E2 = logic inputs

S_'!I931/1

Fig. 10 - Servocontrol for compact-clisc

REFLECTED
BEAM
LASER

S~9475/'

Fig. 11 - Compact-disc motor driver (1/2 section)

tv.

369

aB.
TACHOMETER CONVERTER
The L290, a monolithic LSI circuit a l6-lead
dual in-line plastic package, is intended for use
with the L29l and L292 which together from a
comp'lete 3-chip DC motor positioning system
for 'applications such as carriage/daisy-wheel
position control in typewriters.

DIP-16 Plastic
(0.4)

The L290/l/2 system can be directly controlled
by a microprocessor. The L290 integrates the
follqwing functions:
- tacho voltage generator (F/V converter)
reference voltage generator
- position pulse generator

ORDERING NUMBER: L290B

ABSOLUTE MAXIMUM RATINGS

vs

± 15
±7
1
-40 to +150

Supply voltage

Vi (FTA, FTB, FTF) Input signals

Ptot
Tstg' Tj

Total power dissipation Tamb = 700 e
Storage and junction temperature

V
V

w
°e

SYSTEM BLOCK DIAGRAM

L -_ _ _ _ _ _ _- - ' 5-4113

371

12/86

TEST CIRCUIT

3.2.5 K!l

FTA

16

14 I----+-!--{) STA
1 3/----+-!--{) 5 TB

L 290

FTB

FTF

/------ 7V

2.3

7

'lL

Low voltage input current
(pin 2, 7, 10, 15)

V IL = 1.5V

IIH

High voltage input current
(pin 2, 7, 10, 15)

2.3V .;; VIH .;; Vss -0.6V

V enL

Enable low voltage (pin 1,9)

V enH

Enable high voltage (pin 1,9)

mA

24

-0.3

Vss

mA

4

V

V

-10

/LA

100

/LA

-0.3

1.5

V

Vss';; 7V

2.3

Vss

> 7V

2.3

7

30

V
Vss
lenL

Low voltage enable current
current (pin 1, 9)

VenL

ienH

High voltage enable current
(pin 1,9)

2.3V .;; VenH .; Vss -0.6V

VCEsatH

Source output saturation
voltage (pins 3, 6, 11, 14)

10

=-

0.6A

VCEsatL

Sink output saturation
voltage (pins 3, 6, 11, 14)

'0

= + 0.6A

VF

Clamp diode forward voltage

10" 600 mA

1.3

V

tr

Rise time (")

0.1 to 0.9 Vo

250

ns

tf

Fall time (")

0.9 to 0.1 Vo

250

ns

ton

Turn-on delay (')

0.5 Vi to 0.5 Vo

750

ns

toff

Turn-off delay (")

0.5 Vi to 0.5 Vo

200

ns

(")

= 1.5V

See fig. 1

409

-30

-100

/LA

± 10

/LA

1.4

1.8

V

1.2

1.8

V

II.
SWITCH-MODE SOLENOID DRIVER
•

HIGH VOLTAGE OPERATION (UPTO 50V)

•

HIGH OUTPUT CURRENT CAPABILITY
(UP TO 4A)

•

LOW SATURATION VOLTAGE

and electronic typewriters. Power dissipation is
reduced by effecient switch mode operation. An
extra feature of the L294 is a latched diagnostic
output which indicates when the output is short
circuited.
The L294 is supplied in all-lead Multiwatt®
plastic power package.

• TTL-COMPATIBLE INPUT
• OUTPUT SHORT CIRCUIT PROTECTION
(TO GROUND, TO SUPPLY AND ACROSS
THE LOAD)
• THERMAL SHUTDOWN
• OVERDRIVING PROTECTION
•

Multiwatt 11

LATCHED DIAGNOSTIC OUTPUT

The L294 is a monolithic switchmode solenoid
driver designed for fast, high-current applications
such as hammer and needle driving in printers

ORDER CODE: L294

BLOCK DIAGRAM

02

11
SINK
STAGE

OUT

01

5- 501411

411

12/86

ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Vs =40V, Vss= 5V, Tamb =25°C,
unless otherwise specified).
Test conditions

Parameter

Min.

Typ.

Max.

Unit

46

V

30

Vs

Power supply voltage (pin 11

Operative condition

Id

Quiescent drain current (pin 1)

VENABLE= H

20

Vi;;' 0.6V;

70

Vss

Logic supply voltage (pin 4)

Iss

Quiescent logic supply current

Vi

I nput voltage (pin 7)

12

VENABLE= L

7

V

V OIAG = L

5

8

mA

DIAG output at high
impedance

10

100

IlA

4.5

Operating output

0.6

Non-operative output
I,

I nput current (pin 7)

0.45

'ENABLE
'Ioad/Vi

Enable input current (pin 9)
Transconductance

V

-1

Vi;;' 0.6V

IlA

-3

Vi .; 0.45V
VENABLE Enable input voltage (pin 9)

mA

Low level

-0.3

High level

2.4

0.8

VENABLE= L

-100

VENABLE- H

100

Rs= 0.2 n

Vi = 1V

0.95

1

1.05

Vi= 4V

0.97

1

1.03

V
IlA
A/V

Vsat H

Source output saturation
voltage

Ip=4A

1.7

V

V sat L

Sink output saturation
voltage

Ip=4A

2

V

V sat H+V sat L Total saturation voltage

------

4.5

Ip=4A
Vi'; 0.45V

1

V
mA

'Ieakage
K

Output leakage current

Rs= 0.2n;

On time limiter constant (0)

VENABLE- L

V OIAG

Diagnostic output voltage
(pin 5)

'OIAG= 10mA

0.4

V

'OIAG

Diagnostic leakage current
(pin 5)

V OIAG = 40V

10

IlA

V pin 8

OP AMP and OT A DC voltage
gain (00)

V pin 10- 100 to 800 mV

0.9

V

V pin 10
V SENS

Sensing voltage (pin 10) (000)

(0)
After a time interval t max = KC 2 , the output stages are disabled.
(00) See the block diagram.
(000) Allowed range of V SENS without the intervention of the short circuit protection.

413

120

5

CIRCUIT OPERATION (continued)
voltage at pin 1 and then by switching the device on again. After that, two cases are possible: the reason
for the "bad operation" is still present and the protection acts again; the reason has been removed and
the device starts to work properly.
Fig. 1 - Output current waveforms

Fig. 2 - Test and typical
application circuit

I load

,,1--1-----'"'-'''--''''1--VENABLE

a)

D1: 3A fast diode
D2: 1A fast diode

b)

Fig. 4 - Output saturation
voltages vs. peak output
current
,-,

Fig. 3 - Peak ou tpu t cu rrent
vs. input voltage

.. --

G-U'''1

Ip

'

l('

(A )

RS .. 0.2

V

Jl.

V

V

V

V

trr';; 200 ns

t

IV I

V

f---

--

~

-Vsat

/"

1.5

V-

V
V-

I

0.'

../

V-

/"
V-

../

V
VsatH

V

I
, IpCA)

Fig. 5 - Safe operating areas

Fig. 6 -

Turn-off phase
G•

(P~~~~~~!I~~~~~~

Ie

(A)

~

70011

'eE

(A )

(V)

I

1005

/

I

'"

,eE
"
30

\
,\e

--

20

\

I

I-'

II

\
I" .......

0.1 '--'---'---L..Ll-'-Ll.L..._'--.LJ--'-,Lll,JJ
10

100

VCEIV)

415

200

300

t (nsec)

aB.

PRELIMINARY DATA

DUAL SWITCH-MODE SOLENOID DRIVER
•

HIGH CURRENT CAPABILITY (UP TO
2.5A PER CHANNEL)

•

HIGH VOLTAGE OPERATION
46V FOR POWER STAGE)

•

HIGH EFFICIENCY SWITCHMODE OPERATION

•

REGULATED
JUSTABLE)

levels at the inputs and can drive 2 solenoids.
The output current is completely controlled by
means of a switching technique allowing very
efficient operation. Furthermore, it includes
an enable input and dual supplies (for interfacing
with peripherals running at a higher voltage than
the logic).

(UP TO

OUTPUT CURRENT (AD-

•

FEW EXTERNAL COMPONENTS

•

SEPARATE LOGIC SUPPLY

•

THERMAL PROTECTION

The L295 is particularly suitable for applications
such as hammer driving in matrix printers, step
motor driving and electromagnet controllers.

The L295 is a monolithic integrated circuit in
a 15-lead Multiwatt® package; it incorporates
all the functions for direct interfacing between
digital circuitry and inductive loads. The L295 is
designed to accept standard microprocessor logic

Multiwatt 15

ORDERING NUMBER: L295

ABSOLUTE MAXIMUM RATINGS
Vs
Vss
VEN,V i
V,ef
10

Supply voltage
Logic supply voltage
Enable and input voltage
Reference voltage
Peak output current (each channel)
- non repetitive (t = 100 J.Lsec)
- repetitive (80% on -20% off; t on = 10 ms)
- DC operation
Total power dissipation (at T case= 75°C)
Storage and junction temperature

APPLICATION CIRCUIT

+Vss

50
12

7
7

3

V
V
V
V

2

A
A
A

25
-40 to 150

W
°C

2.5

.v.

01

417

12/86

~

ELECTRICAL CHARACTERISTICS (Refer to the application circuit, Vss= 5V; Vs= 36V;
Tj = 25°C; L = low; H = high; unless otherwise specified)
Parameter
Vs

Supply Voltage

Vss

Logic Supply voltage

Id

Quiescent drain current

Test conditions

Min.

Typ.

Max.

Unit

12

46

V

4.75

10

V

Vs = 46V; ViI = Vi2= V EN = L

4

mA

Vss = 10V

46

mA

(from V s)
Iss

Quiescent drain current
(from V ss )

ViI. V i2

Input Voltage

Low

-0.3

0.8

High

2.2

7

Low

-0.3

0.8

High

2.7

7

V

V EN

Enable Input Voltage

V

IiI' 112

Input Current

ViI = Vi2= L

-100

ViI = Vi2= H

10

/LA

lEN

Enable Input Current

V EN = L

-100

V EN = H

10

/LA

V refl •
V ref2

Input Reference Voltage

Irefl •
I ref2

Input Reference Current

fosc

Oscillation Frequency

C = 3.9 nF;

R=9.1Kn

Transconductance (each ch.)

V ref = lV

Rs

V drop

Total output voltage drop
(each channel) (*)

10

V sens 1

External sensing resistors
voltage drop

_Ip__
V ref

Vsens 2

(*) V drop= VCEsat QI

0.2

= 2A

+ VCEsat Q2'

419

= 0.5n

2

V

-5

/LA

KHz

25
1.9

2

2.1

AN

2.8

3.6

V

2

V

The current increases until the voltage on the external sensing resistor, RSI ,reaches the reference voltage,
V refl . This peak current, Ipl' is given by:

At this point the comparator output, Comp1, sets the RS flip-flop, FF 1, that turns off the output
transistor, 01. The load current flowing through 02, 02, RS1 , decreases according to the law:
- R1 t
L1
where

VA

= VeEsat Q2 + Vsens• 1 + V02

If the oscillator pin (9) is connected to ground the load current falls to zero as shown in fig. 1.
At the time t2 the channell is disabled, by taking the inputs V in1 low and/or EN high, and the output
transistor 02 is turned off. The load current flows through 02 and 01 according to the law:

VB

1= (-R-1- + 1T2 ) e

- R1 t
L1

where
IT2 = current value at the time t 2 .
Fig. 2 in shows the current waveform obtained with an RC network connected between pin 9 and ground.
From to t1 the current increases as in fig. 1. A difference exists at the time t2 because the current starts
to increase again. At this time a pulse is produced by the oscillator circuit that resets the flip flop, FF1,
and switches on the output transistor, 01. The current increases until the drop on the sensing resistor
RSI is equal to V,efl (t 3 ) and the cycle repeats.
The switching frequency depends on the values of Rand C, as shown in fig. 4 and must be chosen in the
range 10 to 30 KHz.
It is possible with external hardware to change the reference voltage V ref in order to obtain a high peak
current Ip and a lower holding current Ih (see fig. 3).
The L295 is provided with a thermal protection that switches off all' the output transistors when the
junction temperature exceeds 150°C. The presence of a hysteresis circuit makes the IC work again after
a fall of the junction temperature of about 20°C.
The analog input Rins (V refl , V,ef2) can be left open or connected to Vss; in this case the circuit works
with an internal reference voltage of about 2.5V and the peak current in the load is fixed only by the
value of Rs:
I =
p

2.5

~

421

aB.

ADVANCE DATA

HIGH CURRENT SWITCHING REGULATORS
inhibit, thermal protection, a reset output for
microprocessors and a PWM comparator input
for synchronization in multichip configurations.

• 4A OUTPUT CURRENT
•

5.1V TO 40V OUTPUT VOLTAGE RANGE

•

0 TO 100% DUTY CYCLE RANGE

•

PRECISE (±2%) ON-CHIP REFERENCE

The L296P includes
limiting current.

The L296 and L296P are mounted in a 15-lead
Multiwatt® plastic power package and requires
very few external components.

• SWITCHING FREQUENCY UP TO 200KHz
•

VERY HIGH EFFICIENCY (UP TO 90%)

•

VERY FEW EXTERNAL COMPONENTS

Efficient operation at switching frequencies up
to 200KHz allows a reduction in the size and
cost of external filter components. A voltage
sense input and SCR drive output are provided
for optional crowbar overvoltage protection
with an external SCR.

• SOFT START
•
•

RESET OUTPUT
EXTERNAL PROGRAMMABLE LIMITING
CURRENT (L296P)

•

CONTROL CIRCUIT FOR CROWBAR SCR

•

INPUT FOR REMOTE INHIBIT AND SYNCHRONUS PWM

•

THERMAL SHUTDOWN·

external programmable

MUltiwatt®fP'
(15-lead),' . ,...
u

The L296 and L296P are stepdown power
switching regulators delivering 4A at a voltage
variable from 5.1V to 40V.

OROERING NUMBER,">

L296
L296P

Features of the devices include soft start, remote

L296HT
L296PHT

BLOCK DIAGRAM

This is advanced information· on a new product now in development or undergoing evaluation. Details are subject to change without notice.

423

12/86

PIN FUNCTIONS
NAME

FUNCTION

CROWBAR INPUT

Voltage sense input for crowbar overvoltage protection.
Normally connected to the feedback input thus trig·
gering the SCR when Vout exceeds nominal by 20%.
May also monitor the input and a voltage divider can be
added to increase the threshold. Connected to ground
when SCR not used.

2

OUTPUT

Regulator output.

3

SUPPL Y VOLTAGE

Unregulated voltage input. An internal regulator powers
the L296's internal logic.

4

CURRENT LIMIT

A resistor connected between this terminal and ground
sets the current limiter threshold.
If this terminal is left unconnected the threshold is
internally set (see electrical charateristics).

5

SOFT START

Soft start time constant. A capacitor is connected between this terminal and ground to define the soft start
time constant. This capacitor also determines the average
short circuit output current.

6

INHIBIT INPUT

TTL - level remote inhibit. A logic high level on this
input disables the device.

7

SYNC INPUT

Multiple L296s are synchronized by connecting the pin 7
inputs together and omitting the oscillator RC network
on all but one device.

8

GROUND

Common ground terminal.

9

FREQUENCY COMPENSATION

A series RC network connected between this terminal
and ground determines the regulation loop gain characteristics.

10

FEEDBACK INPUT

The feedback terminal of the regulation loop. The output is connected directly to this terminal for 5.1V operation; it is connected via a divider for higher voltages.

11

OSCILLATOR

A parallel RC network connected to this terminal determines the switching frequency. This pin must be connected to pin 7 input when the internal oscillator is used.
425

CIRCUIT OPERATION

(continued)

Fig. 1 - Reset output waveforms
OUTPUT NOW
STABLE,RESET
GOES HIGH
HYSTERE.SIS

AN INTERRUPTION
OF SUPPLY C..USES
RESET OF MICRO

t

~

_J ___ ~~=::-::-:~

I

AT POWER DOWN
MICRO IS INHIBITED
IMMEDIATELV

----- ----- - -

MONITORED
VOLTAGE

RESET
OUTPUT

Fig. 2 - Soft start waveforms
CLAMPED ERROR

OSCILLATOR
OUTPUT

AMP. OUTPUT

NOMINAL
ERROR AMP.
OUTPUT

OUTPUT
CURRENT

Fig. 3 - Current limiter waveforms
"

CURRENT

LIMITER
TRIGGERS

LIMIT

THRESHOLD

-

CURRENT

+...u.......

~ ~')t,G~IRCUIT

--------------

r--------------------n--------

-m-:.-Jfn-8~~-~&--- ---,-

.LO.LL..................L.L-._-!c-

427

1-

ELECTRICAL CHARACTERISTICS (continued)
Test Conditions

Parameter

SOFT START
IS so

50urce current

V 6 = OV,

V S = 3V

IS 51

5ink current

V6=3V,

Vs=3V

INHIBIT
V6L

Low input voltage

VI =9V to 46V

V6 H

High input voltage

V 7 = OV

-16L

Input current with low
input voltage

VI =9V to 46V

V6 = 0.8V

-16H

Input current with
high input voltage

V 7 =OV
51: 8
52: 8

V6 =2V

51: 8
52: 8

-0.3

0.8

2

5.5

V

6a

10

/loA

6a

3

/loA

6a

V

6c

V

6c

V

6a

ERROR AMPLIFIER
VgH

High level output volt.

VlO = 4.7V, 19 = 1OO/loA, 51 : A, 52: A

V gL

Low level output volt.

V10 = 5.3V, 19 = 100/loA, 51 : A, 52: E

3.5
0.5

Igsl

5ink output current

V 1 0 = 5.3V,

51: A,

52: 8

100

150

/loA

6c

-Igso

50urce output current

V10 = 4.7V,

51 :A,

52: D

100

150

/loA

6c

110

Input bias current

V 10 = 5.2V

51 : 8
51: 8,

VlO = 6.4V,
Gy

DC open loop Gain

Vg = 1V to 3V,

51: A,

L296P
52: C

46

2

10

/loA

6c

2

10

/loA

6c

d8

6c

/loA

6a

mA

6A

V ref
-50mV

V

6d

V bef
V ref
-15 mV -100mV

V

6d

V

6d

mV

6d

55

OSCILLATOR AND PWM COMPARATOR
-17

I nput bias current of
PWM comparator

V7 = 0.5V to 3.5V

-Ill

Oscillator source curro

Vll = 2V,

V 12 R

Rising threshold
voltage

VI = 9V to 46V,

V12 F

Falling threshold
voltage

5

51: A

52: 8

5

RESET
51: 8,

52: 8

4.75

V 13D

Delay threshold volt.

V 13 H

Delay threshold
voltage hysteresis

V14S

Output saturation volt.

114 = 16mA; V 12 = 4.7V; 51,52: 8

112

Input bias current

V12 = OV to V~ef'

-113 so Delay source current

V ref
V ref
-150mV -100mV

V 12 = 5.3V,

51: A,

52: 8

4.3

4.5

4.7

100

51 : 8,

52: 8

V 12 = 5.3V

70

V 12 = 4.7V

10

113s1

Delay sink current

V 13 = 3V
51: A
52: 8

114

Output leakage curro

VI=46V, V 12 =5.3V, 51:8, 52:A

429

0.4

V

6d

1

3

/loA

6d

110

140

"A

6d

mA

6d

/loA

6d

100

Fig. 6- DC test circu its

Fig.6a

Fig.6b

Fig.6c

I

10,..F
100IJA

'fl,. ,

Fig.6d

A B

52

'~'j@

oc

1,

V forVg~ lV
1-Set 10
t
2Va
2 - Change V 10 to Ob
l!.Vg
__
3 - Gy ~ lJ.V10
lJ.V lO

InVg~3 V

431

1

Fig. 16 - Switching fre·
quency vs. R 1 (see fig. 4)
G-

.

I

Fig. 17
Line transient
response (see fig. 4)

I

(KHz I

_.1--

_1. I I J
I

AV,
(mY)

I

"-

.

100

tJ"l5nF

I

!-~

100

I

1m

10

..

(m' I
50

f--f--

OUTPUT VOLTAGE
CHANGE

-100

1'\
51{ms)

..•

D.'

RI (K!I.)

Fig. 19 - Supply voltage
ripple rejection vs. free
quency (see fig. 4)
G_UZO
TTTTlITIr

'D

AVj.2VJ1h1:!o
V]dSV
VoaVref

'0

(VI

Fig. 20 - Dropout voltage
between pin 3 and pin 2 vs.
current at pin 2
."
I
-L

Fig. 21 - Dropout voltage
between pin 3 and pin 2 vs.
junction temperature G.wn"
"0
(V I

I

I

1o.. 2A

10

r-.

50

I

,0

I

,

20

10

10

11

I

I!

, II

; I
III.

100

1.6

--

1.2

~

12"4A

Tj"~'C

k:::-; ~2S.C

_k:::: ~ ........

.. t'...

1jl;.25"C

I.' I-I
-

12,,2.6

f-

I.,

0.'

tCHzl

Fig. 22 - Power dissipation
derating curve

3.5

12 (AI

-25

G-4917

"tOl

(WI

(WI

1

t:100KH z
YO"Vref

0

25

50

75

100

125

150

TJ(OCI

Fig. 24 - Power dissipation
(device only) vs. input volt·
age

Fig. 23 - Power dissipatiqn
(device only) vs. input volt·
age
G.S711

Ptot

~O,

(WI

1-~-+~I--+-~-+'~o._~hH",~-+~
Yo"VrtI

1--:=+

.

I

+

~

I

'.

10 ,,4.0.

I'{-z.

s~~.·.Ft ~
~'
It

I- ~

I-

I
I

r-..

•.

40

zo

1/

_100

10

{dO I

I

AVo

;;;;oF"!

.50

",'

.

f--- f-

- , - r--

I
I

'D
~I-

i-.- (AI

%"Vr~

VI ,,3511

LOAD CURRENT

40

l"

I

I

-

_. __.

CHANGE

\

,

'1111

Io
---(

OUTPUT \IOLTAGE

.0
C3"2.2"~

,

1.1.
~::';~I _

INPUT VOLTAGE

'1"-

"I:"

Fig. 18 - Load transient
response (see fig. 4)

G_~209

~S'2/1

"'''s

~-

~

'.

r-...::

~.l--

1

-s.

,,;>. t-)~
~w

'"

I

-

- :..

-

1o=2A

T

.. '

100

1.mb {OC}

10

15

20

25

MBRI045

T

1--~_-I-+-~-+-IBVW80

~!'-----< r----<

C2
2.2,,7

15
7

J1:'~
C3

iii:2.2n~ :

~

01

-11

R2

L1
~

300"H

~M

~;r

;3

Kiil

5

9

8

4

>----R5 15

JpF~~ ~C5-!!! :~~~
Kfi

33n~

pF

C7
C8
100"F 100"f

l """I~'F
\ /
Schottky
diode

[ R7
~

R8
[ 4.7

Kfi

I,m

V/

GOlD

'\.

GNO

)

C7, C8: EKR (ROE)

S-6za0/2

INHIBIT

(*1 Minimum value (10I'F) to avoid oscillations; ripple consideration leads to typical value of 1000l'F or higher
L 1: 58930 - MPP COGEMA 946044; GUP 20 CQGEMA 946045

SUGGESTED INDUCTOR (L 1)
Core Tvpe
Magnetics 58930 - A2MPP
Thomson GUP 20x16x7
Siemens EC 35/17/10
(86633& - G0500 - X 1 27)

No
Turns

Wire
Gauge

Air
Gap

43
65

1.0mm.
0.8mm.

1 mm.

40

2 x 0.8mm.

-

-

VOGT 250 I'H Toroidal coil, part number 5730501800

Resistor values for
standard output voltages
Va

12V
15V
18V
24V

Fig. 35 - P.C. board and component layout of the circuit of fig. 34 (1 : 1 scale)

GND

435

R8
4.7
4.7
4.7
4.7

kn
kn
kn
kn

R7
6.2
9.1
12
18

kn
kn
kn
kn

APPLICATION INFORMATION (continued)
Fig. 36 - A minimal 5.1V fixed regulator. Very few components are required
.tOV to.46V
INPUT

11

+5.1V

~------~--~JY~-.--~---o

'Fig. 37 - 12V/l0A Power supply
Yr=20Y to46Y

.12V

1

InF

6.2

Kn

4.7Kfi

437

APPLICATION INFORMATION (continued)
Fig. 40 - In multiple supplies several L296s
can be synchronized as shown.

Fig. 41 - Voltage sensing for remote load
300",H

A

,on
B

"

DSC

I

7

11

SYNC

DSC

j

I

7
SYNC

1

11

DSC

7
SYNC

RL

'0

I

C

,on
D

GND

5- 58 29/2

Fig. 42 - A 5.1V /15V/24V multiple supply. Note the synchronization of the three L296s.
+35V

5-582114

439

~vo

HOW TO OBTAIN BOTH RESET AND
POWER FAIL
Figure 46 illustrates how it is possible to obtain
at the same time both the power fail and reset
functions simply by adding one diode (0) and
one resistor (R).

immunity to the 100Hz ripple present on the
supply voltage.
Moreover, the power fail and reset delay time
are automatically locked to the soft start. Soft
start and delayed reset are thus two sequential
functions.

In this case the reset delay time (pin 13) can only
start when the output voltage is Va ;;;. VREF 100mV and the voltage across R2 is higher
than 4.5V.

The hysteresis resistor should be in the range
of about 100Kn and the pull-up resistor of
1 to 2.2Kn.

With the hysteresis resistor it is possible to fix
the input pin 12 hysteresis in order to increase

Fig.46
PULL- UP RESISTOR

3
,..-,"-----s--'I,---,14

~-...-{)VO=

2

L296

o

R

s- 9573

RESET OUT

441

5.1V

II.
STEPPER MOTOR CONTROLLERS

• NORMAL/WAVE DRIVE
• HALF/FULL STEP MODES
• CLOCKWISE/ANTICLOCKWISE RECTION
LOAD CURRENT REGULA• SWITCHMODE
TION
• PROGRAMMABLE LOAD CURRENT
EXTERNAL COMPONENTS
• FEW
RESET
& HOME OUTPUT
• ENABLEINPUT
INPUT
•
• STEP PULSE DOUBLER (L297A ONLY)

and on-chip PWM chopper circuits permit switch·
mode control of the current in the windings.
A feature of this device is that it requires only
clock, direction and mode input signals. Since
the phase are generated internally the burden on
the microprocessor, and the programmer, is
greatly reduced. Mounted in a 20-pin plastic
package, the L297 can be used with monolithic
bridge drives such as the L298N or L293E, or
with discrete transistors and darlingtons. The
L297 A also includes a clock pulse doubler.

01

DIP-20 Plastic
(0.4)

The L297 Stepper Motor Controller IC generates
four phase drive signals for two phase bipolar and
four phase unipolar step motors in microcom·
puter-controlled applications. The motor can be
driven in half step, normal and wave drive modes

ORDERING NUMBERS: L297-L297A

ABSOLUTE MAXIMUM RATINGS
Vs
Vi'

Ptot
T 519' T j

Supply voltage
I nput signals
Total power dissipation (T amb = 70°C)
Storage and junction temperature

10

V

7

V
W
°C

1
-40 to +150

TWO PHASE BIPOLAR STEPPER MOTOR CONTROL CIRCUIT
sv

J6V

STEPPER

MOTOR
WINDINGS

RSl RS2 ~ 0.5.\1

01 toOS= 2AFastdiodes {VF" 1.2V@
trr" 200 ns

5 .. 5846/4

1~2A

443

12/86

CONNECTION DIAGRAM
DOUBLER

20

RESET

GND

19

HALF/FUll

HOME

18

CLOCK

A

17

CW/CCW

16

OSC

L297A

INHl
B

INH 2

10

ENABLE

15

Vref

14

SENS 1

13

SENS 2

12

Vs

"

OIR-MEM

$M!\840

BLOCK DIAGRAM
A

~:g/FULL

INHl

8

C

i'NH2

o-+--------t

0

J----------lf----O ENABLE

REsET
DIRECTION

DIR-MEM

DOUBLER

GND

HOME

SENS 1 Vref

SENS 2

OSC.

THERMAL DATA
Rth j-amb

max.

Thermal resistance junction-ambient
445

80

°C/W

PIN FUNCTIONS -

L297(continued)

NAME

FUNCTION
Input for load current sense voltage from power stages
of phases A and B.

14

15

V,ef

Reference voltage for chopper circuit. A voltage applied
to this pin determines the peak load current.

16

OSC

An RC network (R to Vee, C to grou nd) connected to
this terminal determines the chopper rate. This terminal
is connected to ground on all but one device in synchronized multi - L297 configurations. f 2e 1/0.69 RC,
R> 10.kn.

17

CW/CCW

Clockwise/counterclockwise direction control input.
Physical direction of motor rotation also depends on
connection of windings.
Synchronized internally therefore direction can be
changed at any time.
Step clock. An active low pulse on this input advances
the motor one increment. The step occurs on the rising
edge of this signal.

18

19

20

HALF/FULL

Half/full step select input. When high selects half step
operation; when low selects full step operation. Onephase-on full step mode is obtained py selecting FULL
when the L297's translator is at an even-numbered state.
Two-phase-on full step mode is set by selecting FULL
when the translator is at an odd numbered position.
(The home position is designated state 1).
Reset input. An active low pulse on this input restores
the translator to the home position (state 1, ABCD =
0101).

447

MOTOR DRIVING PHASE SEQUENCES
The L297's translator generates phase sequences for normal drive, wave drive and half step modes. The
state sequences and output waveforms for these three modes are shown below. I n all cases the trans·
lator advances on the low to high transistion of CLOCK.
Clockwise rotation is indicated; for anticlockwise rotation the sequences are simply reversed. RESET
restores the translator to state 1, where ABCD = 0101.

Half step mode
Half step mode is selected by a high level on the HALF/FULL input.

k]
1001

4

0001

0101

2

1

A

1000

51010
B

6 0010

B

HOME 0100

L....-_ _ _~r__

7
0110

5_5841

Normal drive mode
Normal drive mode (also called "two-phase-on" drive) is selected by a low level on the HALF/FULL
input when the translator is at an odd numbered state (1, 3, 5 or 7). In this mode the INH1 and INH2
outputs remain high throughout.
.

A

1001

0101

7

0110

HOME
lNHl

o----------------------------------------~-

INH2 0------------------------------------------

449

ELECTRICAL CHARACTERISTICS

(continued)
Test conditions

Parameter
Vo

V lnh

Phase output voltage
(pins 4, 6, 7,9)
Inhibit output voltage
(pins 5, 8)

Min.

10 = 10mA

VOL

10 = 5mA

V OH

10 = 10mA

V inh L

Max.

Unit

0.4

V

3.9

V
0.4

3.9

V inh H

10 = 5mA

Typ.

V
V

Ileak

Leakage current
(pins 3, 11 *)

V CE= 7V

1

!J.A

V sat

Satu ration voltage
(pins 3, 11 *)

I =5mA

0.4

V

Voff

Comparators offset voltage
(pins 13, 14, 15)

V,ef = lV

5

mV

Ib

Comparator bias current
(pins 13, 14, 15)

-100

10

!J.A

V ref

I nput reference voltage
(pin 15)

0

3

tCLK

Clock time

0.5

!J.s

ts

Set up time

1

!J.s

tH

Hold time

4

!J.s

tR

Reset time

1

!J.s

tRCLK

Reset to clock delay

1

!J.s

* L297A only.

Fig. 1

V

\

J

~
1CLK
CWtCCW

\II

\I

J\.

HALF STEPt
FULL STEP

J\.

1S

~

\.
1R

/
451

1H

~ .. ~84S

1RCLK

,V

lIB.

PRELIMINARY DATA

DUAL FULL-BRIDGE DRIVER
•

of the input signals. The emitters of the lower
transistors of each bridge are connected together
and the corresponding external terminal can be
used for the connection of an external sensing
resistor. An additional supply input is provided
so that the logic works at a lower voltage.

POWER SUPPLY VOLTAGE UP TO 46V

• TOTAL DC CURRENT UP TO 4A
•

LOW SATURATION VOLTAGE

• OVERTEMPERATURE PROTECTION
•

LOGICAL "0" INPUT VOLTAGE UP TO
1.5V (HIGH NOISE IMMUNITY)

The L298N is an integrated monolithic circuit in
a 15-lead MUltiwatt® package. It is a high voltage, high current dual full-bridge driver designed
to accept standard TTL logic levels and drive
inductive loads such as relays, solenoids, DC
and stepping motors. Two inhibit inputs are
provided to disable the device independently

ABSOLUTE MAXIMUM RATINGS
Power supply
Logic supply voltage
Input and inhibit voltage
Peak output current (each channel)
non repetitive (t = 100 !ls)
- repetitive (80% on - 20% off; t on = 10 ms)
- DC operation
Sensing voltage
Total power dissipation (T case = 75°C)
Storage and junction temperature

50

V

7

V

-0.3 to 7

V

3
2.5

A
A
A
V
W
°C

2

-1 to 2.3
25
-40 to 150

STEPPER MOTOR CONTROL CIRCUIT
5V

CLOCK

18

6

36v

B

HALF/FUCL

RESET

"

ENABLE

10

20

J 02

L297

L298N

V,"

STEPPER

13 03

MOTOR

WINDINGS

14 04

"
SENSE 2
CONTROL

01 to 08:;: 2A Fast diodes

j

HOME
SYNC.

VF <;; 1.2V
trr';';;;

@

R51

1= 2A

R52

200 ns

453

12/86

Fig. 1 - Switching times test circuits

Vss=SV

Fig. la - Source Current Delay Times vs. Input or
Enable Chopper.

VS=4ZV

imax(2A)

5-585211

-t---~----------"7"---

Vi (4V)
50%
5_5853/\

Note: For INPUT chopper, set EN = H

Fig. 2 - Switching times test circuits

VS5=SV

Fig. 2a - Sink Current Delay Times vs. Input or
Enable Chopper.

VS=4ZV

Imax(2A)

-t---....- - - - -

90·,. -

VI (4V)
SO'/,
5-565':1'1

Note: For INPUT chopper, set EN = H

455

ELECTRICAL CHARACTERISTICS (continued)
Min.

Test conditio_ns

Parameter

\21

Typ.

/lS

0.5 Vi to 0.9 IL {31

0.7

/lS

0.9 IL to 0.1 IL \31

0.2

/lS

1.5

/lS

Source current rise time

0.1 IL to 0.9 IL

Ts (Vi)

Sink current turn-off delay

T6 (V,)

Sink current fall time

131

Sink current turn-on delay

0.5V i toO.1IL

Ta (Vi)

Sink current rise time

0.1ILtoO.91L (31

0.2

fc

Commutation frequency

IL = 2A

25

1)
2)
3)
•

Sensing voltage can be -1V for t " 50 /lsec; in steady state V sens min;;' -0.5V.
See fig. 1a.
See fig. 2a.
The correct sequence for power-on, is: 1. Vss on with EN = L - 2. Vs on - 3. EN = H
and for power-off 1. EN = L - 2. V 5 off - 3. V ss off

Fig. 4 - Bidirectional DC motor control

13

10

14

L------~

TO CONTROL

____I--"'___'-ovinh

15

CIRCUIT
01 TO 04: lA HI GH - SPEED 010 DE

INPUTS

V inh = H

FUNCTION

C= H;

D=L

Turn right

c= L;

D=H

Turn left

C=D
V inh = L·
L= Low

Unit

0.35

T4 (Vi)

T7 (Vi)

Max

C= X;

Fast motor stop
D=C

H = High

Free running
motor stop
X = Don't care

457

/lS
40

KHz

aB.

ADVANCE DATA

VERY LOW DROP 5V REGULATOR
•

PRECISE OUTPUT VOLTAGE (5V ± 4%)

•

VERY LOW DROPOUT VOLTAGE

•

OUTPUT CURRENT IN EXCESS OF 500mA

•

POWER-ON, POWER-OFF INFORMATION
(RESET FUNCTION)

•

HIGH NOISE IMMUNITY
DELAY CAPACITOR

ON

output makes the L387 A particularly suitable for
microprocessor system. This output provide a
reset pulse when power is applied (after a external programmable delay) and goes low when
power is removed inhibiting the microprocessor.
An hysteresis on reset delay capacitor raises
the immunity to the ground noise.

RESET

The L387 A is a very low drop voltage regulator
in a Pentawatt® package specially designed to
provide stabilized 5V supplies in consumer and
industrial applications. Thanks to its very low
input/output voltage drop this device is very
useful in battery powered equipment, reducing
consumption and prolonging battery life. A reset

Pentawatt®

ORDERING NUMBER: L387A

ABSOLUTE MAXIMUM RATINGS
Forward input voltage
Reverse input voltage
Positive transient voltage (t < 300ms)
Negative transient voltage (t < lOOms)
Operating junction temperature
Storage temperature

35 V
-18 V
60 V
-60 V
-40 to 150°C
-55to 150°C

TEST CIRCUIT
OUTPUT
VOLTAGE

IN

5

r..,
U
I

'

+5V

-r,

.J.!OOflF

*

RE ET
OUTPUT

• Min 331-'F and max. ESR';;; 3!l over temperature range
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

459

12/86

ELECTRICAL CHARACTERISTICS (Refer to the test circuit,

VI

otherwise specified)
Parameter

Test Conditions

Va

Output voltage

10 = 5mA to 500mA

Vi

Operating input voltage

(*)

c,V o

Line regulation

Vi = 6V to 26V

c,V o

Load regu lati on

10 = 5mA to 500mA

VI - Va

Dropout voltage

10 = 500mA

Iq

Quiescent cuttent

c,T

Max.

Unit

4.80

6

5.20

V

26

V

5

50

mV

15

60

mV

0.60

0.8

V

10
10
10
10
10

5
20
60
100
170

15
35
100
160
180

mA

=OmA
= 150mA
= 350mA
= 500mA
= 500mA

Temperature output t
voltage drift

SVR

Supply voltage rejection

Isc

Output short circuit
current

, VR

Reset output voltage

IR = 16mA

IR

Reset output leakage
current

Vain regulation

td

Delay time for reset
output

Cd = 100nF

VRT(off)

Reset threshold (delay
chargi ng cu rrent on)

IC4

Chargi ng cu rrent
(current generatod

CRT(on)

Reset threshold (low)

V4

Comparator threshold
(pin 4)

VH

Typ.

10 = 5mA

VI = 6.2V
c,V o

Min.

f=120Hz
V 1= 12V ± 5 Vpp

10 = 350mA
Co = 100/LF

mVtC

60

dB

0.8

Va

< 4.75V

1.5

A

0.8

V

50

/LA

30

4.75

V 4 = 3V

V o -O·15

10

ms

V o -O·04

V

30

/LA

V

V RT(off)
-10mV
Reset out = "0"

3.3

3.7

V

Reset out = "1"

3.7

4.3

V

Hysteresis voltage

(*) For a DC voltage 26

-0.5

500

< Vi < 35V the device is not operating
461

mV

aB.
DAR LlNGTON ARRAYS
EIGHT

•

OUTPUT CURRENT 400mA PER DRIVER
(500mA PEAK)

•

OUTPUT VOLTAGE 90V (VCE(SUS) = 70V)

L602

14-25V PMOS

•

INTEGRAL SUPPRESSION DIODES FOR
INDUCTIVE LOADS

L603

5V TTL, CMOS

L604

6 - 15V CMOS, PMOS

•

DARLINGTONS

PER

The four versions interface to all common logic
families:

•

PACKAGE

L601

OUTPUTS CAN BE PARALLELED FOR
HIGHER CURRENT

.

These versatile devices are useful for driving a
wide range of loads, including solenoids, relays
DC motors, LED dispalys, filament lamps, thermal
printheads and high power buffers.

• TTL / CMOS / PMOS / DTL COMPATIBLE
INPUTS
•

General purpose

The L601, L602, L603 and L604 are supplied
in 18 pin plastic DIP packages with a copper
leadframe to reduce thermal resistance.

INPUTS PINNED OPPOSITE OUTPUTS TO
SIMPLIFY LAYOUT

The L601, L602, L603 and L604 are high voltage, high current darlington arrays each containing eight open collector darlington pairs with
common emitters. Each channel is rated at 400
mA and can withstand peak currents of 500mA.
Suppression diodes are included for inductive
load driving and the inputs are pinned opposite
the outputs to simplify board layout.

DIP-18 Plastic
(U7P2)
ORDERING NUMBERS: L601B,
L602B,

L603B
L604B

ABSOLUTE MAXIMUM RATINGS
V CEX
Ic
Ic
Vi
Ii

Ptot
Top
T stg

90
V
0.4
A
0.5
A
30
V
25
mA
1.8
W
-25 to 150°C
-55 to 150
°C

Collector emitter voltage (input open)
Collector current
Collector peak current
Input voltage (for L602, L603 and L604)
Input current (for L601 only)
Total power dissipation a T amb = 25°C
Operating junction temperature
Storage temperature

SCHEMATIC DIAGRAM (L601 - One darlington only)
.--~-CCOM
~---+---- 1A

1.9

6

V
V

0.4
2.4

n

0.3

Jl.S

1

Jl.S

(0) Pulsed: pulse duration = 300 Jl.S, duty cycle = 1.5%.

Fig. 1 - Switching time

Fig. 3 - Peak collector current vs. duty cycle and number of outputs(L702B only)

Fig. 2 - ton and tOff test circu it

IOn.

Vi

0-----1

>--+---0

Jl2V

S-347111

v"
0.'

l;t

ff+

10'/.

469

JO'/.

,..,.

70'/.

!-DC.,.}

II.

ADVANCE DATA

LOW DROP DUAL POWER OPERATIONAL AMPLIFIERS

•
•
•
•
•
•
•
•

OUTPUT CURRENT TO lA

ticularly indicated for driving, inductive loads,
as motor and finds applications in compact-disc,
VCR automotive, etc.

OPERATES AT LOW VOLTAGES
SINGLE OR SPLIT SUPPLY

The high gain and high output power capability
provide superior performance whatever an operational amplifier/power booster combination is
required.

LARGE COMMON-MODE AND DIFFERENTIAL MODE RANGE
LOW INPUT OFFSET VOLTAGE
GROUND COMPATIBLE INPUTS
LOW SATURATION VOLTAGE
THERMAL SHUTDOWN

The L2720 and L2722 are monolithic integrated circuits in powerdip and minidip packages,
intended for use as power operational amplifiers
in a wide range of applications including servo
amplifiers and power supplies. They are par-

Powerdip 8 + 8

Minidip Plastic

ORDERING NUMBERS:
L2722

L2720

ABSOLUTE MAXIMUM RATINGS
Supply voltage
Peak supply voltage (50ms)
I nput voltage
Differential input voltage
DC output current
Peak output current (non repetitive)
Power dissipation at Tamb = 80°C (L2720), Tamb = 50°C (L2722)
T case = 75°C (L2720)
Storage and junction temperature

28
50

V
V

V.
± V.
1
1.5
1

5

A
A
W
W

-40 to 150

°c

BLOCK DIAGRAMS

L2720

L2722

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

471

12/f.k

ELECTRICAL CHARACTERISTICS (V.

= 24V,

Parameter
V.

Single supply voltage

V.

Spl it supply voltage

I.

Quiescent drain current

= 25°C unless otherwise specified)

Tamb

Test Conditions

Min.

Typ.

Max.

4

28

±2

± 14

Unit

V

Vo =

Vs

Vs = 24V

10

15

2

Vs = 8V

9

15

0.2

1

p.A

15

mV

50

nA

rnA

Ib

Input bias current

Vos

Input ollset voltage

los

Input ollset current

10

SR

Slew rate

2

V/p.s

B

Gain-bandwidth product

1.2

MHz

RI

Input resistance

Gv

D.L. voltage gain

Kn

SOO
I = 100Hz

70

80
dB

I = 1KHz

60

eN

Input noise voltage

IN

Input noise current

CMR

Common Mode rejection

I = 1KHz

SVR

Supply voltage rejection

I = 100Hz
RG = 10Kn
VR = O.SV

10

p.V

200

pA

66

84

dB

54

70
7S
81

dB
dB
dB

B = 22Hz to 22KHz

VOROP (HIGH)

Vs = 24V
Vs = ±12V
Vs = ± 6V
Ip = 100mA

0.7

Ip = 500mA

1.0

Ip = 100mA

0.3

Ip = SOOmA

0.5

Gv = 30dB
Vs = 24V
V. = ± 6V

60

V
1.5

Vs = ±2.SV to ± 12V
VOROP(LOW)

Cs

T.d

V

Channel separation

f = 1KHz;

RL = 10n;

Thermal shutdown
junction temperature

473

1.0

60

dB
dB

145

°c

APPLICATION SUGGESTION
In order to avoid possible instability occurring
into final stage the usual suggestions for the
linear power stages are useful, as for instance:
-

A 100nF capacitor corrected between supply
pins and ground;
boucherot cell (0.1 to 0.2/.lF + 1n series) between outputs and ground or across the load.

layout accuracy;

Fig. 8 - Bidirectional DC motor control with /.lP compatible inputs

E2

V 51 = logic supply voltage
Must be V 52

> V 51

E 1, E2 = logic inputs

Fig. 9 - Servocontrol for compact-disc

REFLECTED
BEAM
LASER

S-9Io15"

Fig. 10 - Compact-disc motor driver (1/2 section)

s~

9478'1

475

.Vs

Fig. 14 - VHS-VCR Motor control circuit

LOADING MOTOR
CASSETTE MOTOR

uP

fM\ CAPSTAN
\:V MOTOR

L2720

zs

®DRUM
M MOTOR

L2720

CAPST AN TACHO
DRUM POSITION
CTL
REC.PB.
REEL TACHO
RIGHT
LEFT
REEL TACHO

....

TDA
8114
RESET

0
0

477

VHS2::DIS

5-9482

II.

PRELIMINARY DATA

PRINTER SOLENOID DRIVER
The L3654S is a printer solenoid driver containing
ten open-collector driver outputs and a ten-bit
serial-in, parallel-out register.

clamped to ground internally at 50V to dissipate
stored energy in inductive loads.
The L3654S is supplied in a 16 lead dual in-line
plastic package, and its main fields of application comprise thermal printers, cash registers
and printing pocket calculators.

Data is clocked into the shift register serially
and transferred to the open-collector outputs
by an enable input. Serial input data is loaded
by the rising edge of the clock. A serial output
from the tenth bit is provided which changes
at the falling edge of the clock. This output is
not controlled by the enable input and remains
active at all time.

DIP-16 Plastic

(0.25)

The L3654S is pin to pin compatible with the standard L3654, but can work with Vs down to 4.75V.

ORDERING NUMBER: L3654S

Each output is rated at 250mA (sink) and is

ABSOLUTE MAXIMUM RATINGS
Vs
Vi

VE
10
Ig
Ptot
T stg , T j

Supply voltage
Input voltage
External supply voltage
Output current (single output)
Ground current
Total power dissipation (Tamb = 70°C)
Storage and junction temperature

9.5
9.5
45
0.4
4.0
1
-65 to 150

V
V
V
A
A
W
°C

BLOCK DIAGRAM
OUTPUT5
V
OUTPUT 1
EN ENABLE

V
DI

DATA
INPUT

s-

5013/1

479

12/86

ELECTRICAL CHARACTERISTICS

(V.

specified)
Parameter

= 5V,

VE = 30V, T amb = 0° to 70 0 e, unless otherwise

Test conditions

V.

Supply voltage

Is

Supply current

Min.
4.75

mA

V. = 9.5V

V EN = 2.6V
10 = 250 mA (each bit)

55

70

mA

40

V

1

mA

65

V

1.6

V

V E =40V

VEN=OV

Vz

I nternal clamp voltage

I z = 0.3A·

VEN=OV

VCE sat

Output saturation voltage

10 = 250 mA

V EN = 2.6V

VOl
V CLK
V EN

I nput logic levels
(pins 1,9,10)

101

Data input current

RIN

VOO

45

50

Low State (L)

0.8
V

High state (H)

2.6

V OI = 2.6V

T amb = 70°C

0.3

0.57
mA

T amb = O°C

0.57

V OI = lV

T amb = 70°C

220

V CLK = 2.6V

T amb = 70°C

0.2

0.75
IJA

0.33
mA

T amb = O°C

0.33

VCLK=lV

T amb = 70°C

125

V EN = 2.6V

T amb = 70°C

0.2

0.5
IJA

0.33
mA

T amb = O°C

0.33

VEN=lV

T amb = 70°C

125

Input pu II-down resistance
Clock input

T amb= 25°C

V CLK

Enable input

T amb = 25°C

V EN

< V.

8

Data input

T amb = 25°C

VOl

< V.

4.5

Low state (L)
VOI=OV

loo(pin 7)= 0

0.Q1

Output logic levels
(pin 7)

< V.

High state (H)
V DI = 2.6V
100 (pin 7) = -0.75 mA
Roo

V

40

Output leakage current
(each output)

lEN

9.5
27

IleaK

Enable input current

Unit

V EN = OV; Voo= OV

External operating supply
voltage

Clock input current

Max.

T amb = 25°C

VE

ICL~

Typ.

Output pull-down
resistance (pin 7)

VOI=OV

VOO=lV

• Pulsed: pulse duration = 3001Js, duty cycle - 2%

481

0.5
IJA

8

2.6

K.r2

0.5

V

3.4

V

14

K.r2

II.

PRELIMINARY DATA

DUAL 5V REGULATOR WITH RESET
• OUTPUT CURRENTS: 101 = 300mA
102 = 400mA
•

FIXED PRECISION OUTPUT VOLTAGE 5V
±2%

•

RESET FUNCTION CONTROLLED BY INPUT VOLTAGE AND OUTPUT 1 VOLTAGE

•

RESET FUNCi ION EXTERNALLY PROGRAMMABLE TIMING

•

RESET OUTPUT LEVEL RELATED TO
OUTPUT 2

•

• OUTPUT TRANSISTORS SOA PROTECTION
• SHORT CIRCUIT AND THERMAL OVERLOAD PROTECTION
The L4901 is a monolithic low drop dual 5V
regulator designed mainly for supplying microprocessor systems.
Reset and data save functions during switch onl
off can be realized.

• OUTPUT 2 INTERNALLY SWITCHED WITH
ACTIVE DISCHARGING
•

RESET OUTPUT HIGH

LOW LEAKAGE CURRENT, LESS THAN
1tlA AT OUTPUT 1

•

LOW QUIESCENT CURRENT

•

INPUT OVERVOLTAGE PROTECTION UP
TO 60V

Heptawatt

(INPUT 1)
ORDERING NUMBER: L4901

ABSOLUTE MAXIMUM RATINGS
DC input voltage
DC operating input voltage
Transient input overvoltage (t = 40ms)
Output current
Storage and junction temperature

24
20
60
internally limited
-40 to 150

V
V
V

BLOCK DIAGRAM

V,l

O-~r--':'I---r-L.!R~EG~.~lj--,~-r--"]=--o

Vol

:r
r::~=-"_~5~O RESET
L~~J-13'--

>

THERMAL DATA
Thermal resistance junction-case

max
485

4

ELECTRICAL CHARACTERISTICS (continued)
Test Conditions

Parameter
V RT

Reset threshold voltage

VRTH

Reset threshold hysteresis

VRH

Reset outPut voltage HIGH

'R

VRL

Reset output voltage LOW

'R

tRD

Reset pu Ise delay

Ct

td

Timing capacitor discharge
time

Ct

= 500"A
= -5mA
= 10nF
= 10nF

Min.

Typ.

Max.

V02 -O.15

4.9

V02 -OD5

V

V0 2-1

Unit

50

160

mV

4.12

V02

V

0.25

0.4

V

10

14

ms

20

"S

6

~ Thermal drift

_20°C ~ Tamb ~ 140°C

-0.8

0.3

+0.8

mVrC

~ Thermal drift

_20°C ~ Tamb ~ 140°C

-0.8

0.3

+0.8

mVrC

SVRl

f

54

84

t.T

t.T

Supply voltage rejection

SVR2

Supply voltage rejection

TJSD

Thermal shut down

=

0.5V
'0 ==100mA

100Hz

VR

50

dB

80

dB

150

°c

* The dropout voltage is defined as the difference between the input and the outPut voltage when the output voltage is
lowered of 25m V under constant output current condition.

APPLICATION INFORMATION
In power supplies for J..IP systems it is necessary
to provide power continuously to avoid loss
of information in memories and in time of day
clocks, or to save data when the primary supply
is removed. The L4901 makes it very easy to
supply such equipments; it provides two voltage
regulators (both 5V high precision) with separate inputs plus a reset output for the data save
function.

- an overload on the output 1 (VOl
- a switch off (V ,N < V,T - V,TH );

<

VRT );

and they start again as before when the con·
dition is removed.
An overload on output 2 does not switch Reg. 2
(V02 - VR = VCEsat ; 102 = , sc2 ) and does not
influence Reg. 1.
The VOl output features:

CIRCUIT OPERATION (see Fig. 1)

5V internal reference without voltage divider
between the output and the error comparator;
very low drop series regulator element utilizing current mirrors;

After switch on Reg. 1 saturates until VOl
rises to the nominal value.

,T

When the input 2 reaches V and the output 1
is higher than VRT the output 2 (V 02) switches
on and the reset output (V R ) also goes high after
a programmable time T RD (timing capacitor).

permit high output impedance and then very
low leakage current error even in power down
. condition.

V02 and VR are switched together at low level
when one of the following conditions occurs:

This output may therefore be used to supply
circuits continuously, such as volatile RAMs, al·
lowing the use of a back-up battery without a

- an input overvoltage

487

APPLICATION SUGGESTION (continued)
Fig.2
INI

REG.l

BATTERY

.I.

CMO$

,.,p WITH

VOLATI~E

RAM

REG. 2

I

i
OTHEfl
LOGIC
C3
10nF

I

@S')
L4901

5

RESET OUT

RESET

4
S,~7710

Fig. 3 - P.C. board component layout of fig. 2 (1 : 1 scale)

489

I 2

APPLICATION SUGGESTION (continued)
Fig.6

:c

INI

OUT I 7

680
I'f

2

L4901
OUT2 6

IN2

:r:

~

DATA

ADDRESS

5

fOf'F

8085

RE-5ET 5

TRAP

'S_BOSSI'

Fig. 7 - Quiescent current
(Reg. 1) vs. output 'current

Fig. 8 - Quiescent current
(Reg. 1) vs. input voltage
,

6_5195
IQl
(rnA)

IQI

laiD1

{mAl

{mA }

VI!1I12V

-

...-

f.--

/

2••

II

Fig. 10 - Regulator 1 output current and short circuit
current vs. input voltage

Fig. 11 - Regulator 2 output current and short circuit
current vs. input voltage

15

18

-

800

7.•
•••

1\

./"

,/

I.

........

\'

••

15

11

Vi

I'

L

-

I..

~

(V)

V

/" ;:- ~

\

•
•

20

9

12

15

491

II

..-

.VA

~

21

'Ii

50

,\
\\

10

6

SVR1

••

\

24 VI IV)

18

VI (V)

G '592411

"R

•
\

15

Fig. 12 - Supply voltage
rejection regulators 1 and 2
vs. input ripple frequence

80

\

0

3

12

IdB }

'00

1\\
12

,/

500

'\ ,\

Vlt (V)

...

I

ImA
I"

V

V

I
t2

700

'00

I

/'

•••

..

, - f--

V'

2••

100

I

,

101= IOZ~SrnA
Vil=V12

V

/

ImA }

5. .

- "

V1Z=O
Io1E5mA

--

f--

Fig. 9 - Total quiescent cur·
rent vs. input voltage

I.

I.'

II.

PRELIMINARY DATA

DUAL 5V REGULATOR WITH RESET
AND DISABLE FUNCTIONS
• OUTPUT CURRENTS:

101
102

•

= 300mA
= 400mA

INPUT OVERVOLTAGE PROTECTION UP
TO 60V

•

FIXED PRECISION OUTPUT VOLTAGE 5V
±20f0

• OUTPUT TRANSISTORS SOA PROTECTION

•

RESET FUNCTION CONTROLLED BY INPUT VOLTAGE AND OUTPUT 1 VOLTAGE

•

RESET FUNCTION EXTERNALLY PROGRAMMABLE TIMING

•

RESET OUTPUT LEVEL RELATED TO
OUTPUT 2

• SHORT CIRCUIT AND THERMAL OVERLOAD PROTECTION
The L4902 is a monolithic low drop dual 5V
regulator designed mainly for supplying microprocessor systems.
Reset and data save functions and remote switch
on/off control can be realized.

• OUTPUT 2 INTERNALLY SWITCHED WITH
ACTIVE DISCHARGING
• OUTPUT 2 DISABLE LOGICAL INPUT
•

LOW LEAKAGE CURRENT, LESS THAN
l#lA AT OUTPUT 1

•

RESET OUTPUT HIGH

Heptawatt
ORDERING NUMBER: L4902

ABSOLUTE MAXIMUM RATINGS
DC input voltage
DC operating input voltage
Transient input overvoltage (t = 40ms)
Output current
Storage and junction temperature

24
20
60
internally limited
-40 to 150

V
V
V

BLOCK DIAGRAM

015.

r:~=.,----t~o RESET

L:.:.::.:...J-;'''----C TIM ING
4

493

;-764013

12/86

CONNECTION DIAGRAM
(Top view)

--r--

~

$~

OUTPUT 1

6

OUTPUT 2

S

RESET
GROUND
DISABLE INPUT
TIMING CAPACITOR

•
J

Z

INPUT

~

S-76~1

PIN FUNCTIONS
NAME

FUNCTION

INPUT 1

Regulators common input.

2

TIMING CAPACITOR

If Reg. 2 is switched-ON the delay capacitor is charged
with a 5p.A constant current. When Reg. 2 is switched-OFF the delay capacitor is discharged.

3

V02 DISABLE INPUT

A high level (> VOT ) disable output Reg. 2.

4

GND

Common ground.

5

RESET OUTPUT

When pin 2 reaches 5V the reset output is switched high.
5V
Therefore tRo = Ct ( - - ) ; tRO (ms) = Ct (nF).
5p.A

6

OUTPUT 2

5V - 400mA regulator output. Enabled if Vo 1 > V RT'
DISABLE INPUT < VOT and VIN
VIT' If Reg. 2 is
switched-OFF the CO2 capacitor is discharged.

7

OUTPUT 1

5V - 300mA. Low leakage (in switch-OFF condition)
output.

>

THERMAL DATA
Thermal resistance junction-case

max
495

4

ELECTRICAL CHARACTERISTICS (continued)
Test Conditions

Parameter

Min.

TVp·

Max.

Unit

V02- 1

4.12

V02

V

0.25

0.4

V

10

14

ms

20

jots

VRH

Reset output voltage HIGH

IR = 500jotA

VRL

Reset output voltage LOW

IR = -5mA

tRo

Reset pulse delay

Ct = 10nF

td

Timing capacitor discharge
time

Ct

VOT

V 02 disable threshold voltage

1.25

10

V02 disable input current

-100
-2

aVOl

Thermal drift

.20°C'" Tamb '" 140°C

-0.8

0.3

0.8

Thermal drift

-20°C'" Tamb '" 140°C

-0.8

0.3

0.8

54

84

50

80

dB

150

°c

aT
aV02
aT
SVR1

Supply voltage rejection

SVR2

Supply voltage rejection

TJSO

Thermal shut down

6

= 10nF

Vo '" 0.4V
Vo;> 2.4V

f = 100Hz VR=0.5V 10 = 100mA

V

2.4

jotA
jotA
mV/oC

mV/oc
dB

* The dropout voltage

is defined as the difference between the input and the output voltage when the output voltage is
lowered of 25m V under constant output current condition.

APPLICATION INFORMATION
In power supplies for IJ.P systems it is necessary
to provide power continuously to avoid loss
of information in memories and in time of day
clocks, or to save data when the primary supply
is removed. The L4902 makes it very easy to
supply such equipments; it provides two voltage
regulators (both 5V high precision) with common
inputs plus a reset output for the data save function and a Reg. 2 output disable.

an input overvoltage;
an overload on the output 1 (VOl
a switch off (V IN < VIT - V1TH );

<

VRT );

and they start again as before when the condition is removed.
An overload on output 2 does not switch Reg. 2
(V02 - VR = VCEsat ; 102 = , sc2 ) and does not
influence Reg. 1.
The VOl output features:
- 5V internal reference without voltage divider
between the output and the error comparator
- very low drop series regulator element utilizing current mirrors

CIRCUIT OPERATION (see Fig. 1)
After switch on Reg. 1 saturates until VOl
rises to the nominal value.
When the input reaches VIT and the output 1
is higher than VRT the output 2 (V 02 ) switches
on and the reset output (V R ) also goes high after
a programmable time TRO (timing capacitor).

permit high output impedance and then very
low leakage current error in power down condition.
This output may therefore be used to supply
circuits continuously, such as volatile RAMs, allowing the use of a back-up battery without a
separation diode.

V02 and VR are switched together at low level
when one of the following conditions occurs:
- a high level (> VOT ) is applied on pin 3;
497

APPLICATION SUGGESTION (continued)
Fig. 2

,

INI

REG.I

~TTERY C~

1:.

7

OUT I

4.,,..FI

VOO

r,
~3

,..F

1

3 V020lS

~

REG. 2

6

:k

.1

YOO
OUT PORT

OUT 2
IlolO,..f

I"

I

IN PORT

I

OTHER
LOGIC

@SV

C:f2

L4902

RESET OUT

5

RESET

I.
5-784311

Fig. 3 -

p.e. board and component layout of the circuit of Fig. 2

GND

CMOS
,..p WITH
VOLATILE
RAM

Voo

-~

10nF

CMOS
CLOCK

DIS.

OUT2

499

(1 : 1 scale)

GND

APPLICATION SUGGESTION (continued)
Fig. 6 - Quiescent current
vs. output current

Fig. 7 - Quiescent current
vs. input voltage

Fig. 8 - Regulator 1 output
current and short circuit
current vs. input voltage

,,

G-566611

G-586SII

'Q

'mA

I

(mAl

Vj ,.12~
VOZHIGH

,..- ~

70 0

IOI·1a2~5mA

---YOZlOW

lL
)" 7
V -

,00

-

~'

I-

.-

f-7

60 0

-VozltGH

/1

I - --

I--"

f'~

I
'"
,/

0

30o

--- --

20 0

~-

-/'

\

"

'\ ,\

\\
\\

100

",.

.1\.

1
200

12

15."

Fig. 9 - Regulator 2 output
current and short circuit
current vs. input voltage

,

12

Yj (v)

Fig. 10 - Supply voltage
rejection regu lators 1 and 2
vs. input ripple frequence

.

SVR
(dB I

(mA )

800
70 0

1/

60 0
'00

I"

/

80

\

Is<

\

/ ' " I'\.

400

0

\

60

\

300
0

50

,I

10 0

\\
3

6

9

12

15

18

21

10

24 Vi (V)

501

SVRI

.SVR

~
'I

15

18

Vi (V)

ADVANCE DATA

DUAL 5V REGULATOR WITH RESET
AND DISABLE FUNCTIONS
• OUTPUT CURRENTS:

101
102

= 50mA
= 100mA

•

•

FIXED PRECISION OUTPUT VOLTAGE
5V ±2%

•

RESET FUNCTION CONTROLLED BY INPUT VOLTAGE AND OUTPUT 1 VOLTAGE

•

RESET FUNCTION EXTE RNALL Y PROGRAMMABLE TIMING

•

RESET OUTPUT LEVEL RELATED TO
OUTPUT 2

RESET OUTPUT LOW

• OUTPUT TRANSISTORS SOA PROTECTION
• SHORT CIRCUIT AND THERMAL OVERLOAD PROTECTION
The L4903 is a monolithic low drop dual 5V
regulator designed mainly for supplying microprocessor systems:
Reset. data save functions and remote switch
on/off control can be realized.

• OUTPUT 2 INTERNALLY SWITCHED WITH
ACTIVE DISCHARGING
• OUTPUT 2 DISABLE LOGICAL INPUT
•

LOW LEAKAGE CURRENT. LESS THAN
1pA AT OUTPUT 1

•

INPUT OVERVOL TAGE PROTECTION UP
TO 60V

Minidip Plastic
ORDERING NUMBER: L4903

ABSOLUTE MAXIMUM RATINGS
DC input voltage
DC operating input voltage
Transient input overvoltage (t = 40ms)
Power dissipation at Tamb = 50°C
Storage and junction temperature

24
20
60
1
-40 to 150

v
V
V
W

°c

BLOCK DIAGRAM
Vi I ().

I

8

REG. I

f'o

Vol

1
Vi2e:

DIS.8

2

5

J
I

REG. 2

1
DISABLE

II THERMAL
PROTECTION

.J;

7

~

6

DELAYED
RESET

3

.() Vo 2

r.

RESET

..£)TlMING

5-'416/2

..IS advanced information on a new product now in development or undergoing evaluation. Details are subject to change without

This

503

notice.

12/86

CONNECTION DIAGRAM
(Top view)
INPUT 1

8

OUTPUT 1

INPUT 2

7

OUTPUT 2

6

RESET
OUTPUT

TIMING
CAPACITOR

3

GND

5

V02
DISABLE
INPUT

5-9411

PIN FUNCTIONS
FUNCTION

NAME
INPUT 1

Low quiescent current SOmA regulator input.

2

INPUT 2

100mA regulator input.

3

TIMING CAPACITOR

If Reg. 2 is switched-ON the delay capacitor is charged
with a S/J.A constant current. When Reg. 2 is switchedOFF the delay capacitor is discharged.

4

GND

Common ground.

S

V 02 DISABLE INPUT

A high level (> VOT) disable output Reg. 2.

6

RESET OUTPUT

When pin 3 reaches SV the reset output is switched low.
SV
Therefore tRO = Ct (S/J.A); tRO (ms) = Ct (nF).

7

OUTPUT 2

SV - 100mA regulator output. Enabled if Vo 1 > V RT .
DISABLE INPUT < VOT and V ,N 2 > V'To If Reg. 2 is
switched OFF the CO2 capacitor is discharged.

8

OUTPUT 1

SV - SOmA regulator output with low leakage in switchOFF condition.

THERMAL DATA
Rthi-Pln
RthJ-amb

Thermal resistance junction-pin 4
Thermal resistance junction-ambient

max
max

505

70
100

ELECTRICAL CHARACTERISTICS (continued)
Test Conditions

Parameter

VRT

Reset threshold voltage

VRTH

Reset threshold hysteresis

VRH

Reset output voltage HIGH

VRL

Reset output voltage LOW

tRo

Reset pulse delay

td

Timing capacitor discharge
time

IR = 500ltA
IR = -5mA

Min.

Typ.

Max.

.V02-0.4

4.7

V02-0.2

V

50

160

mV
V

V02-1

Ct = 10nF
Ct = 10nF

6

Unit

4.12

V02

0.25

0.4

V

10

14

ms

20

ItS

1.25

V

VOT

V02 disable threshold voltage

10

V02 disable input current

Vo .. 0.4V
Vo ;. 2.4V

AVOl
AT

Thermal drift

-20°C .. Tamb .. 140°C

-0.8

0.3

0.8

mvrc

AV02
AT

Thermal drift

-20°C" Tamb .. 140°C

-0.8

0.3

0.8

mV/oC

SVRl

Supply voltage rejection

f= 100Hz VR=0.5V 10=50mA

54

84

dB

SVR2

Supply voltage rejection

10= l00mA

50

80

dB

2.4

-100
-2

itA
itA

Thermal shut down
150
°c
TJSO
• The dropout voltage is defined as the difference between the input and the output voltage when the output voltage is
lowered of 25mV under constant output current conditions.

APPLICATION INFORMATION

a high level. (> V OT ) is applied on pin 5;
an input overvoltage;
an overload on the output 1 (VOl < VRT );
a switch off (V IN
V IT - VITH );

In power supplies for }J.P systems it is necessary
to provide power continuously to avoid loss
of information in memories and in time of day
clocks, or to save data when the primary supply
is removed. The L4903 makes it very easy to
supply such equipments; it provides two voltage
regulators (both 5V high precision) with separate
inputs plus a reset output for the data save func·
tion and Reg. 2 output disable.

CIRCUIT OPERATION (see Fig.

<

and they start again as before when the condition is removed.
An overload on output 2 does not switch Reg. 2.
(V02 - V R = VcEsat ; 102 = Isc2 ) and does not
influence Reg. 1.
The VOl output features:
5V internal reference without voltage divider
between the output and the error comparator

1)

very low drop series regulator element utilizing current mirrors
permit high output impedance and then very
low leakage current error in power down conditions.
This output may therefore be used to supply
circuits continuously, such as volatile RAMs, allowing the use of, a back-up battery without a
separation diode.

After switch on Reg. 1 saturates until VOl rises
to the nominal value.
When the input 2 reaches VIT and the output 1
is higher than VRT the output 2 (V02 ) switches
on and the reset output (V R) goes low after
a programmable time T RO (timing capacitor).
V02 is switched at low level and V R at high level
when one of the following conditions occurs:
507

Fig. 3 - Quiescent current
(Reg. 1) vs. output current

Fig. 4 - Quiescent current
(Reg. 1) vs. input voltage
G_"7961~

'al
'mAl
V,2 ",0

101f.5mA

0. 0 ~-l---l--J.-j-l---+---+---I---+-+-+---I---+-+--l

V

/

V

V

/
20

12

15

18

Fig. 6 - Supply voltage rejection regulators 1 and 2
vs. input ripple frequence

Fig. 5 - Total quiescent
current vs. input voltage
G-586611

SY R

'0

'dB

(m. )

~!:~1;2l~

- V02 tIGH .

7

fT

- --

)

80

f-7

SVR1

OYR

~

70

1,.'1./

~"

[7

~

°

V

°
12

15

"

VII (V)

10

Vi (vi

509

10'

II.

ADVANCE DATA

DUAL 5V REGULATOR WITH RESET
• OUTPUT CURRENTS:

101 =
102 =

•

50mA
100mA

•

FIXED PRECISION OUTPUT VOLTAGE
5V ± 2%

•

RESET FUNCTION CONTROLLED BY INPUT VOLTAGE AND OUTPUT 1 VOLTAGE

•

RESET FUNCTION EXTERNALLY PROGRAMMABLE TIMING

•

RESET OUTPUT LEVEL RELATED TO
OUTPUT 2

• OUTPUT TRANSISTORS SOA PROTECTION
• SHORT CIRCUIT AND THERMAL OVERLOAD PROTECTION
The L4904 is a monolithic low drop dual 5V
regulator designed mainly for supplying microprocessor systems.
Reset and data save functions during switch on/
off can be realized.

• OUTPUT 2 INTERNALLY SWITCHED WITH
ACTIVE DISCHARGING
•

LOW LEAKAGE CURRENT, LESS THAN
1t.tA AT OUTPUT 1

•

LOW QUIESCENT CURRENT (INPUT 1)

•

INPUT OVERVOLTAGE PROTECTION UP
TO 60V

RESET OUTPUT HIGH

Minidip Plastic
ORDERING NUMBER: L4904

ABSOLUTE MAXIMUM RATINGS
DC input voltage
DC operating input voltage
Transient input overvoltage It = 40ms)
Output current
Power dissipation at Tamb = 50°C
Storage and junction temperature

24
20
60
internally limited
1
-40 to 150

V
V

V
W

°c

BLOCK DIAGRAM
L4904
Vi

IO--I-+---T--{!R~EG~.~IJ--r-t~r-D Vol

r:~=:-l-~~o RESET

L':':'::':'_j--r-D T I MI NG

4

5- 9411

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

511

12/86

CONNECTION DIAGRAM
(Top view)
INPUT 1
INPUT 2

GNO

4

7

OUTPUT 2

6

OUTPUT

5

N.C.

RESET

5''''2

PIN FUNCTIONS
NAME

FUNCTION

INPUT 1

Low quiescent current 50mA regulator input.

2

INPUT 2

100mA regulator input.

3

TIMING CAPACITOR

If Reg. 2 is switched-ON the delay capacitor is charged
with a 5IJ.A constant current. When Reg. 2 is switchedOFF the delay capacitor is discharged.

4

GND

Common ground.

6

RESET OUTPUT

When pin 3 reaches 5V the reset output is switched high.
5V
Therefore tRD = Ct ( - - ) ; tRD (ms) = Ct (nF).
5IJ.A

7

OUTPUT 2

5V - 100mA regulator output. Enabled if Vo 1 > V RT
and VIN 2
VIT' If Reg. 2 is switched-OFF the CO2
capacitor is discharged.

8

OUTPUT 1

5V - 50 rnA regulator output with low leakage in switchOFF condition.

>

THERMAL DATA
RthJ-amb

Thermal resistance junction-ambient

max
513

100

ELECTRICAL CHARACTERISTICS (continued)
Parameter

Test Conditions

VRT

Reset threshold voltage

VRTH

Reset threshold hysteresis

VRH

Reset output voltage HIGH

Min.

Typ.

Max.

Unit

V02-'>·15

4.9

V02-D.05

V

50

160

mV

4.12

V02

V

0.25

0.4

V

10

14

ms

20

I'S

IR

= 5ool'A

V02- 1

= -5mA
= 10nF

6

VRL

Reset output voltage LOW

'R

tRD

Reset pu Ise delay

Ct

td

Timing capacitor discharge
time

Ct=

aVOI
aT

Thermal drift

-20°C .. Tamb .. 140°C

-0.8

0.3

+0.8

mvfc

Thermal drift

-20°C .. Tamb .. 140°C

-0.8

0.3

+0.8

mvfc

54

84

aV02
aT
SVR1

10nF

Supply voltage rejection

SVR2

Supply voltage rejection

TJSD

Thermal shut down

10
f = 100Hz
VR = 0.5V

= 50mA

'0 = 100mA

50

dB

80

dB

150

°c

* The dropout voltage is defined as the difference between the input and the output voltage when the output voltage is
lowered of 25mV under constant output current condition.

APPLICATION INFORMATION
In power supplies for IlP systems it is necessary
to provide power continuously to avoid loss
of information in memories and in time of day
clocks, or to save data when the primary supply
is removed. The L4904 makes it very easy to
supply such equipments; it provides two voltage
regulators (booth 5V high preCision) with separ·
ate inputs plus a reset output for the data save
function.

- an overload on the output 1 (VOl
- a switch off (V ,N < V,T - V ,TH );

< V RT );

and they start again as before when the condition is removed.
An overload on output 2 does not switch Reg. 2
(V02 - V R = V CEsat ; 102 = Isc2 ) and does not
influence Reg. 1.
The VOl output features:
5V internal reference without voltage divider
between the output and the error comparator;

CIRCUIT OPERATION (see Fig. 1)
After switch on Reg. 1 saturates until VOl
rises to the nominal value.

very low drop series regulator element utilizing current mirrors;
permit high output impedance and then very
low leakage current error in power down condition.
This output may therefore be used to supply
circuits continuously, such as volatile RAMs, allowing the use of a back-up battery without a
separation diode. The VOl regulator also features

,T

When the input 2 reaches V and the output 1
is higher than VRT the output 2 (V02 ) switches
on and the reset output (V R ) also goes high after
a programmable time TRD (timing capacitor).
V02 and VR are switched together at low level
when one of the following conditions occurs:
- an input overvoltage
515

APPLICATION SUGGESTIONS (continued)
Application Circuits of a Microprocessor system (Fig. 2) or with data save battery (Fig. 3). The reset
output provide delayed rising front at the turn-off of the regulator 2.

Fig.2
IN1

REG.I

BATTERY

O.22~FI

.I.

2

REG. 2

I~FI
OTHER
LO.GIC
@SV

3

CT

L4904

lOnF I

6

RESET OUT

RESET

4
5- 9414

Fig. 3
INI
Y
0,,",

±

IN 2

I

2

I

I
L

REG. 1

I
I

8

~
]/..I
7

REG. 2

OUT I ILO I < I/..1A VOO
•

4'P'±

F

~l

-==~

OUTZ

:k
I

CMOS
CLOCK

VS8
BACKUP
BATTERY
VOO

I tol0~F
RESET

~P

WITH BATTERY
BACKUP
RAM

VOO

3

CTr
lonFI

J

L4904

1

6

RESE TOUT

5-941511

517

RESET

OTHER LOGIC
@ 5V

II.

PRELIMINARY DATA

VERY LOW DROP ADJUSTABLE REGULATOR
•

VERY LOW DROP VOLTAGE

•

ADJUSTABLE OUTPUT VOLTAGES FROM
1.25V TO 20V

•

400mA OUTPUT CURRENT

•

LOW QUIESCENT CURRENT

•

OVERVOLTAGE AND REVERSE VOL~
AGE PROTECTION

•

+60/-60 TRANSIENT PEAK VOLTAGE

•

SHORT CI RCU IT PROTECTION WITH
FOLDBACK CHARACTERISTICS

•

THERMAL SHUT-DOWN

A foldback current limiter protects against load
short circuits.
The output voltage is adjustable through an
external divider from 1.25V to 20V. The mini·
mum operating input voltage is 5.2V.
These regulators are designed for automotive,
industrial and consumer applications where low
consumption is particularly important.
In battery backup and standby applications the
low consumption of these devices extends bat·
tery life.

The L4920 and L4921 are adjustable voltage
regulators with a very low voltage drop (O.4V
typo at 0.4A), low quiescent current and com·
prehensive on-chip protection.

Minidip (4 + 4)

Pentawatt®

ORDERING NUMBERS:

These devices are protected against load dump
transients of ± 60V, input overvoltage, polarity
reversal and over heating.

L4920

L4921

BLOCK DIAGRAM

1

+_

~PREREGULATOR

.L

BANDGAP
REFERENCE
AND
ERROR

hI-1

DUMP

+

Rl

AI'rIFIER
L-~--------~--+-

I

OUTPUT

L

..

__

ADJUST
~~--O

LPROTECTIONJI-----...I~--------

I

THERMAL
PROTECTION

II

FOLDBACK
CURRENT
LIMITER

I
11------'

1

R2

GND

.'-

519

!I-7916/1

12/86

ELECTRICAL CHARACTERISTICS (For Vi

= 14.4V

Va

= 5V;

= 100~F;

R2

Max.

Unit

Va+0.7

26

V

5.2

26

V

1.25

1.30

V

lj

= 25°C;

C

=

6.2KQ unless otherwise noted)
Parameter

Operating input
voltage

Vi

Test Conditions

Va ~ 4.5V
10 =400mA
VREF" Vo < 4.5V
10 = 400mA

Min.

1.20

Typ.

VREF

Reference voltlige

5.2V < Vi < 26V
10" 400mA (")

I1Vo

Line regulation

Vo+1V ----4---+1--"--+-+--+-+--1----1--+---;

Fig. 9 - Reference voltage
(pin 10) vs. junction temperature

96 f--+_+---+-j-+-+--+_+-~

9.

110

1\

.0

\

-10
10

100

11(

10K

lOOK

1M

t IHzl

10

Fig. 13 - Switching frequency vs. R2 (see test
circuit)

15

20

25

Fig. 14 response

30

35

40

45

VI(Y)

-25

0

25

50

75

100 115

ISO TjI"'C1

Fig. 15 - Load transient
response

Line transient

G-60S0

t

(

(KHz )

LalD C!RRE1NT

, " "-"

..

100

(3.1.5nF

.Vof--+-+-+----1--t--+--+-+-~
(mY)
50

11111

1111

I.

50

OUTPUT VOLTAGE CHANGE

-or - =
--

I--'

I
OUTPUT VOLTAGE CHANGE

H~----il\t--r-'---,--'--'--+'_=___r_'_'__r-l---j

-50

CJ -2.2"F'

I.

-

-+-+--~-+-r-+_4--+----1~20

( AI

'"

-50 f--+-+_+-+--+--+-----1\VH

---t------j

1-

AVo
(mV )

i'

f-- +- -- f-- f-----'--

I

t Cms)

AI (K.D.)

549

05

1.5

t (ms)

~>'«""

•

"

'
,

j

'

~

'"

APPLICATION INFORMATION
Fig. 25 - Typical application circuit
L1

Vi
0--_---17

2

L4962
15
14

01
BVW98

4,5,12,13 11 10

Vo

150,uH

2x
220,uF

C6

40Y

C7

R4

C5
Cl
100J-'F 6lY

Rl
4.7 K.n.

GNO

GNO

s- 9340

C1' C6, C7: EKR (ROE)
D1: BYW98 OR VISK340 (SCHOTTKY)
SUGGESTED INDUCTORS (L1): MAGNETICS 58120 - A2MPP - 45 TURNS - WIRE GAUGE O.8mm (20AWG) COGEMA 946043
OR U15, GUP15, 60 TURNS lmm, AIR GAP O.8mm (20AWG) - COGEMA969051

Fig. 26 -

p.e. board and component layout of the circuit of Fig. 25 (1

: 1 scale)

Resistor valu. for
stand ant output 7 voltages

551

Vo

RS

R7

12V
15V
18V
24V

4.7Kn
4.7Kn
4.7Kn
4.7Kn

6.2Kn
9.1Kn
12Kn
18Kn

APPLICATION INFORMATION (continued)
Fig. 29 - DC-DC converter 5.1 V/4A, ± 12V/1 A. A suggestion how to synchronize a negative output
150}JH

L4962

+12V11A

L1
BYW98

2 x220fF
_~OV

EKR

6.2 K n.
4.7K

11.

L---~~~-r----------------------~~------~----------~~GNO

120pF

L4962

L3
BVW98

2x220"F
40Y

EKR

1500"F

EYF

5-934"2

L1, L3 = COGEMA946043 (969061)
L2 =COGEMA 946044 (946046)

Fig. 30 - In multiple supplies several
L4962s can be synchronized as shown

Fig. 31 - Preregulator for distributed supplies

L4962
10-40V

V,

14

,,

L4962

,I

L __

*

L2 and C2 are necessary to reduce the switching frequency spikes
when linear regulators are remote from L4962

553

SOLENOID CONTROLLER
•

DRIVES ONE OR TWO EXTERNAL DARL1NGTONS

•

DUAL AND SINGLE LEVEL CURRENT
CONTROL

match the requirements of the load and it allows
both simple and two level current control Moreover, the drive waveshape can be adjusted by
external components. Other features of the
device include thermal shutdown, a supply voltage range of 4.75-46V and TTL-compatible
inputs.

• SWITCHMODE CURRENT REGULATION
•

ADJUSTABLE PEAK DURATION

The L5832 is supplied in a 12 + 2 + 2 - lead
Powerdip package which uses the four center
pins to conduct heat to the PC board copper.

• WIDE SUPPLY RANGE (4.75-46V)
•

TTL-COMPATIBLE LOGIC INPUTS

•

THERMAL PROTECTION

The L5832 Solenoid Controller is designed for
use with one or two external darlington transistors in solenoid and relay driving applications.
The device is controlled by two logic inputs and
features switchmode regulation of the load current. A key feature of the L5832 is flexibility.
It can be used with a variety of darlingtons to

Powerdip
12 + 2 + 2

ORDERING NUMBER: L5832

ABSOLUTE MAXIMUM RATINGS
46
60

DC Supply voltage
(Positive transient voltage at pin 8)
Enable input voltage (pin 11)
I nput voltage (pin 10)
External reference voltage (pin 2)
Power dissipation (T case = 80°C)
Storage and junction temperature

7

7
2
5
-40 to 150

V
V
V
V
V

W
°C

APPLICATION CIRCUIT USING ONE DARLINGTON
Vee .5V';'45

r---O-----------.
_l,
i : 5K MSOK li
'r'
,

V,N

t----o--._---I10
,,
I
I

*39V 4.7
I'

Kll

R2

11

I

,I,

GND

L__ ~-+-~--~-~-~-~-----~
5-5986

555

12/86

PIN FUNCTIONS
NAME

FUNCTION

NC

Not connected. Must be left open circuit .

HOLDING CURRENT
CONTROL

A voltage applied to this pin sets the holding current
level. If left open circuit an internal 75 mV reference is
used and Ih = I p /6.

3

SENSING

Connection for load current sense resistor. Value sets the
maximum load current. Ip = 0.45/R s .

4

GROUND

Ground connection. With pins 5, 12 and 13 conducts
heat to printed circuit board copper.

5

GROUND

See pin 4.

6

C1

A capacitor connected between this pin and ground sets
the duration of the current peak (t2 in fig. 3).
If left open, the switchmode control of the peak is
suppressed. If grounded, the current does not fall to
the holding level.

7

DISCHARGE TIME
CONSTANT

A capacitor connected between this pin and ground sets
the duration of tOff (fig. 3). If grounded, switchmode
control is suppressed.

8

PNP DRIVING OUTPUT

Current drive output for external PNP darlington (for
recirculation). 1=35 I ref -

9

REFERENCE VOLTAGE

A resistor connected between th is pin and ground sets
the internal current reference, , ref . The recommended
value is 1.2 kn, giving ' ref = 1 rnA.

10

INPUT

TTL-compatible input. A high level on this pin activates
the output, driving the load.

11

INHIBIT

TTL-compatible inhibit input. A high level on this input
disables the output stages and logic circuitry, irrespective
of the state of pin 10.

12

GROUND

See pin 4.

13

GROUND

See pin 4.

14

SUPPLY VOLTAGE

Supply voltage input.

15

NPN DRIVING OUTPUT

Current drive for external NPN darlington (in series with
the load). I = 100 ' ref .

16

INTERNAL CLAMPING

Internal zener clamp available for fast turnoff.

N°

2

.

'\

557

APPLICATION INFORMATION
The L5832 solenoid controller is intended for use with one or two external darlington transistors to
drive inductive loads such as solenoids, relays, electric valves and DC motors.
Controlled by a logic input and an inhibit input (both TTL compatible), the device drives the external
darlington(s) to produce a load current waveform as shown in figure 3. This basic waveform shows that
the device produces an initial current peak followed by a lower holding current. Both the peak and
holding current levels are regulated by the L5832's switchmode circuitry.
The duration of the peak, the peak current level and holding current level can all be adjusted by external
components.
Moreover, by omitting C1, C2 or both it is possible to realize single-level current control, a transitory
peak followed by a regulated holding current or a simple peak (figure 1).

Fig. 1 - Components connected to pins 6 and 7 determine the load current waveshape
COMPONENTS ON
PINS6AND7

H

C1

I

7

~6002 I

H·I
~-600611

LOAD CURRENT
WAVEFORM

C2

cz

559

Fig. 3 - Waveforms of the typical application circuit of fig. 2.

'~~T 1-+----+:----------'---

CURRENT

(:~)

I

I

ton

toff

-~----~ ... ~

II
II

V,

~~~~~~IgR
(INTERNAL)

1--.----+-'""1J..,-t1
450:"

I

15 mV

I

J

I I

'I

I

'I

The discharge time constant (toff in figure 3) is set by a capacitor between pin 7 and ground and is found
from:
toff

=

12C2

~

The tOff and ton times are also related to the current ripple, /:;1:
t off-

where

L/:;I

--off

V

and ton =

L/:;I

VOff = Vdiode + V CEQ1 + RL IL
Von = Vs - V CEQ2 - V RS - RL IL
L = load inductance
R L = load resistance
/:; I = load current ripple.

Note that toff is the same for both the peak and holding currents.

561

Fig. 6 - Switch mode control of the current can be suppressed entirely by leaving pin 6 open and ground·
ing pin 7. The peak current is still controlled.

LOAD'LI
CURRENT~

'NPUT

V,nj

10 (A)

Q1

Q2

4

BDX54

BDX53

8

BDW94

BDW93

10

BDV64

BDV65
INHIBIT

~:

~

,

I

t

.
t

For fast turnoff an internal zener clamp is available on pin 16.
This is used with an external divider, R8 R9, as shown in figure 2. Suitable values can be found from:
15V + V BEQ2 + VRsense
VCQ2 ~ Vp;n

16 •

R9 + R8
R8

(V CQ2 is the voltage at the collector of Q2).
To ensure stability, a small capacitor (about 200 pF) must be connected between the base and collector
of Q2 when pin 16 is used.
For the application circuit of figure 7 toff = 12C2/1,ef, as before, and the current ripple is given by:
toff = -

L
R

In (lLP-l:.I)· RL +VL
I LP ' RL +VL

where V L is the voltage across the inductor during recirculation.
Note that if the load is a motor V L = Eg + V D.

'S-58B811

563

Fig. 8 - P.C. board and component layout of the circuit of fig. 7 (1: 1 scale)

Cs-oln

vee

GND

Fig.9 - Application circuit showing how two separate supplies can be used.
+Ys

LOAO

5V~r-------------

__,

D6

10

R3

L5832

IS
IKa

11

R2
lOK,Q

CI
GNDo---~--~~

C2

__-+__-+__~__~________~

C,-598411

565

Rl1

ADVANCE DATA

100V-1A, QUAD DMOS POWER SWITCH
The L6100, L6101 and L6102 are DMOS quad
transistor array realized with a new process called
Multipower-BCD which allows the integration
of multiple isolated DMOS transistors - plus
bipolar linear and CMOS logic circuits on a
single chip.
Each of the four power DMOS transistors is a
parallel combination of one thousand elementary
cells with a packing density in excess of 1600
cells/mm 2 •
The device is assembled in three package: 12+3+3
lead powerdip; ll-lead Multiwatt® and 15-lead
Multiwatt®.

••
Multiwatt-11
L6101

Multiwatt-15
L6102

ABSOLUTE MAXIMUM RATINGS
Drain-source voltage
Drain-gate voltage (RGS = 14KD)
Gate-source voltage
Drain current
- DC'operation
- Pulsed (300Jls, 1% duty cycle)
Storage and junction temperature range

100
100
+ 14 to -0.6

V
V
V

1
2.5
-40 to + 150

A
A

°c

SCHEMATIC DIAGRAM

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

567

12/86

ELECTRICAL CHARACTERISTICS (Tease = 25°C unless otherwise specified)
Parameter
BVOSS

Drain-source breakdown voltage

Test Conditions

Min.

= lmA
= OV

100

= lmA
= Vos

2

@

10

VGS

'\(C316 (TH)

Threshold voltage

@

10

VGS
IGSS

Gate-source leakage

@ VGSS

Ros (ON)

Static drain-source on-state
resistance

@ VGS

10

=

=

Typ.

Max.

V

4

V

1

/lA

1.2

n

10V

= 10V

lA

Fig. 2 - Normalized ON-reo
sistance vs. temperature
6-6090

Fig. 1 - Saturation charac·
teristics
6-6091
RD S

ID
(A I

10~

~

/

V "
I~ ~ l.- I-- ~
~~

I",!/
~ ~ .....

1.5

YGs a10V

10 "O.5A

6V

I~ ~
~ !iiIi"

v ...

./

V-

1/

5V

O. 5
V

=IoV

I~
4

-100

Vos(V)

-50

50

100 T j ("C)

Fig. 4 - Capacitance vs.
drain to source voltage

Fig. 3 - Transconductance
vs. drain current

6-'092

-6091
(p Fl

I

0

Tj=-Sst

J.---

/'"

5

c::~

! :;7"

T7)

240

25"t
lOD

160

150"<:

80

W

r\

\

\.

I--

\.

"-

569

-

CiSS

c ...
ens
16

Unit

24

32

Vos(Y)

lB.

ADVANCE DATA

1.5A DMOS FULL BRIDGE DRIVER
POWER SUPPLY VOLTAGE UP TO
• TOTAL
DC CURRENT UP TO 1.5A
• LOW SATURATION
VOLTAGE
• LOW POWER DISSIPATION
• NO CROSS CONDUCTION
•
• TTL COMPATIBLE INPUTS
• OVERTEMPERATURE PROTECTION

52V

The L6202 is assembled in a Powerdip 12+3+3
package an 18-lead DIP using the six center pins
to conduct heat to the PCB. Thanks to the very
high efficiency of the DMOS output stage no
external heatsink is necessary, even when operating at the full rated current and Voltage.

Realized with mixed bipolar/CMOS/DMOS technology, the L6202 is a full bridge driver for motor
control applications. Delivering up to 1.5A
output current at motor supply voltages up to
52V, the device uses DMOS output transistors
to obtain very high efficiency and fast switching
speed.

Powerdip 12 + 3 + 3

Each channel (half-bridge) of the device is controlled by a separate logic input, while a common
enable input controls both channels. All inputs
are TTL, CMOS and J.lC-compatible.

ORDERING NUMBER: L6202

BLOCK DIAGRAM
OUT 1 OUl2

o

ceOOT 2

18/------.

4,5,6,13,14,15
5"9392

Note: suggested value for GBOOT 1,2: 10nF

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

571

12/86

PIN FUNCTIONS
NAME

FUNCTION

SENSE

A resistance Rsense. connected to this pin. allows motor
current control.

2

ENABLE

Enable Input.
A logic low level on this pin switches off the DMOS
POWE R transistors.

3

NOT CONNECTED

4

GROUND

Common ground terminal.

5

GROUND

Common ground terminal.

6

GROUND

Common ground terminal.

7

NOT CONNECTED

8

OUT2

Output of the half bridge.

9

Vs

Supply voltage.

10

OUT 1

Output of the half bridge.

11

BOOT 1

A capacitor CBOOT 1. connected to this terminal allows
the upper DMOS transistor driving for high switching
frequencies.

12

IN 1

Input from the controller device.

13

GND

Common ground terminal.

14

GND

Common ground terminal

15

GND

Common ground terminal.

16

IN 2

Input from the controller device.

17

BOOT 2

A capacitor CeOOT 2. connected to this terminal. allow
the upper DMOS transistor driving for high switching
frequencies.

18

Vref

I nternal reference voltage.

573

In the boostrap circuit the external Ca capacitors
are charged to a voltage of about 10V when the
upper power transistor is OFF and the lower one
is ON. To guarantee efficient driving of the upper
power transistor in the conduction condition the
value of Cs must be greater than the value of the
input capacitance, CIN , of the power transistor
itself. Since the estimated value of the input capacity is about 1nF, Cs should be> = 10nF
to guarantee correct operation.

CIRCUIT OPERATION
The L6202 is a monolithic full bridge switching
motor driver realized in the new MultipowerBCD technology which allows the integration
of multiple, isolated DMOS power transistors
plus mixed CMOS/bipolar control circuits.
The power stage of the L6202 consists of four
N-channel DMOS transistors with an Ros (ON)
~ O.3Q over whole current range. Each tran·
sistor has an intrinsic drain-source diode. During
recirculation the behaviour of these diodes
depends on the operating mode.

An ON-OFF synchronisation circuit provides a
dead time (the period in which all four power
transistors are OFF) of 40ns, sufficient to
prevent simultaneous conduction with obvious
advantages in terms of power dissipation and of
spurious signals on the ground and in the sensing
resistors.

When one of the POWE R DMOS transistor is
ON it behaves almost symmetrically in terms of
current - like, in fact, a resistor with the value
Ros (ON) in parallel with the drain-source diode.

A thermal protection circuit has been included
that will disable the device if the junction temperature reaches 150°C. When the temperature
has fallen to a safe value the device restarts
under the control of the input and enable signals.
Fig. 1 - Intrinsic structures in the POWER DMOS
transistors
Vs

During recirculation with the ENABLE input
high, the voltage drop across the transistor is
Ros (ON) X IL for voltages less than O.7V and is
clamped at a voltage depending on the characteristics of the diode for greater voltages.
When the ENABLE input is low, the POWER
MOS is OFF and the diode carry the whole
recirculation.

0-----1

Although the device guarantees the absence of
cross-conduction, the presence of the intrinsic
diodes in the POWE R DMOS structure causes
the generation of current spikes on the sensing
terminals due to charge-discharge phenomena in
the capacitors C1 & C2 associated with the
drain source junctions (Fig. 1). When the output
switches from high to low a current spike is
generated associated with the capacitor C1. On
the low-to-high transition a spike ot the same
polarity is generated by C2, preceded by a spike
of the opposite polarity due to the charging of
the input capacity of the lower POWE R DMOS
transistor. (Fig.2)

C1

You!

~n

C2

5- 9/025

Fig. 2 - Current typical spikes on the sensing pin

To ensure that the POWER DMOS transistors
are driven correctly a gate-source voltage of
about 10V must be guaranteed for all of the
N-channel DMOS transistors. While there is no
problem in driving the lower POWER DMOS
devices (their source terminals are referred to
ground) it is necessary to provide a gate voltage
higher than the positive supply for the upper
transistors because they have the drain connected
to the supply itself.

You!

VS=42V

Ip ,O.5A
T=100ns

This obtained by a system that combines a
charge pump circuit, which assures correct DC
operation, with a boostrapping technique suitable for high switching frequencies.

lsense
~-9426

575

Fig. 7 - Bidirectional DC motor control

,N 1

12
"---<-_--r,

/,l--',,'-,-O-n , N 1

EN

L6202
TO

CONT~OL

CIRCUIT

INPUTS

VEN = H

FUNCTION

IN1 = H

IN2 = L

Turn r;ght

IN1 = L

IN2 = H

Turn left

IN1 = IN2
IN1 = X

VEN = L

L

Low

H

High

Fast motor stop
IN1 = IN2

Free running motor stop

X = Don't care

Fig. 8 - Application circuit

22Kn

12

10

18

IO.

22 ,uF

L297
10

L6202

11

17

,.

10
1,,5,6,13,14,15

CONTROL

SYNC

HOME

577

:r

O. 2Z ,uF

lIB.

ADVANCE DATA

3A DMOS FULL BRIDGE DRIVER
SUPPLY VOLTAGE UP TO
• OPERATING
52V
DC CURRENT UP TO 3A
• TOTAL
SATURATION VOLTAGE
• LOW
LOW
POWER DISSIPATION
• NO CROSS
CONDUCTION
• TTL COMPATIBLE
INPUTS
• OVER TEMPERATURE
PROTECTION
•

Each channel (half-bridge) of the device is controlled by a separate logic input, while a common
enable input controls both channels. All inputs
are TTL, CMOS and ~C-compatible.
The L6203 is assembled in a 11-lead Multiwatt®
package.

Realized with mixed bipolar/CMOS/DMOS technology, the L6203 is a full bridge driver for
motor control applications. Delivering up to 3A
output current at motor supply voltages up to
52V, the device uses DMOS output transistors to
obtain very high efficiency and fast switching
speed.

Multiwatt-11

ORDERING NUMBER: L6203

BLOCK DIAGRAM
OUT 1 OUT2

ENABLE .........P----t""""

11

GND
'51-9520

(*)

Suggested value for CaoOTl and CaOOT2: 10nF

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

579

12/86

PIN FUNCTIONS
NAME

OUT 2
2

FUNCTION

Output of the half bridge.
Supply voltage.

3

OUT 1

Output of the half bridge.

4

BOOT. 1

A capacitor CS1' connected to this terminal allows the
upper DMOS transistor driving for high switching frequencies.

5

IN 1

Input from the controller device.

6

GND

Common ground terminal.

7

IN 2

Input from the controller device.

8

BOOT. 2

A capacitor CS2 , connected to this terminal allows the
upper DMOS transistor driving for high switching'
frequencies.

9

V REF

Internal reference voltage.

10

SENSE

A resistance RSENSE, connected to this terminal, allows
motor current control.

11

ENABLE

Enable input.
A logic low level on this pin switches off the DMOS
power transistors.

581

CIRCUIT OPERATION
The L6203 is a monolithic full bridge switching
motor driver realized in the new MultipowerBCD technology which allows the integration of
multiple, isolated DMOS power transistors plus
mixed CMOS/bipolar control circuits.
The power stage of the L6203 consists of four
N-channel DMOS transistors with an Res (ONI
~ 0.3Q over the whole current rimge. Each
transistor has an intrinsic drain source diode.
During recirculation the behaviour of these
diodes depends on the operating mode.

lower one is ON. To guarantee efficient driving
of the upper power transistor in the conduction
condition, the value of C B must be greater than
the value of the input capacitance, CIN, of the
power transistor itself. Since the estimated value
of the input capacity is about 1nF, CB should
be > = 10nF to guarantee correct operation.
An ON-OFF synchronization circuit provides a
dead time (the period in which all four power
transistors are OFF) of 4Ons, sufficient to prevent simultaneous conduction with obvious
advantages in terms of power dissipation and
of spurious signals on the ground and in the
sensing resistors.
A thermal protection circuit has been included
that will disable the ~evice if the junction temperature reaches 150 C. When the temperature
has fallen to a safe value the device restarts
under the control of the input and enable signals.

When one of the POWE R DMOS transistors is
ON it bahaves almost symmetrically in terms
of current like, in fact, a resistor with the value
Res (ON) in parallel with the drain-source diode.
During recirculation with the ENABLE input
high, the voltage drop across the transistor is
Res (ON) x IL for voltages less than 0.7V and
is clamped at a voltage depending on the characteristics of the diode for greater voltages.
When the enable input is low, the POWER MOS
is off and the diode carry the whole recirculation.
Although the device guarantees the absence of
cross-conduction, the presence of the intrinsic
diodes in the POWE R MOS structure causes
the generation of current spikes on the sensing
pin due to charge-discharge phenomena in the
reverse capacitor, C1 & C2 associated with the
drain-source junctions (Fig. 1). When the output
switches from high to low, a current spike is
generated associated with the capacitor Cl. On
the low-to-high transition, a spike of the same
polarity is generated by C2, preceded by a
spike of the opposite polarity due to the charging
of the input capacity of the lower POWE R
DMOS transistor (Fig. 2).

Fig. 1 - Intrinsic structures in the POWER DMOS
transistors
v.

0---1

Cl

Vout

J:}n

cz

5-9£25

To ensure that the POWE R DMOS transistors are
driven correctly a gate-source voltage of about
10V must be guaranteed for all of the N-channel
DMOS transistors. While there is no problem in
driving the lower POWER DMOS devices (their
source terminals are referred to ground) it is
necessary to provide a gate voltage higher than
the positive supply for the upper transistors
because they have the drain connected to the
supply itself.

Fig. 2 - Typical current spikes on the sensing pin
Vout

VS=4ZV
lp.o.~A

T=100ns

This is obtained by a system that combines a

in

charge pump circuit, which assures correct DC
operation, with a boostrapping technique suitable for high switching frequencies.
In the boostrap circuit the external CB capacitors are charged to a voltage of about 10V
w hen the upper power transistor is OFF and the

I
I
I

Isense

"
i

~

T

\J

J,.

T
S-9·1.26

583

Fig, 7 - Bidirectionale DC motor control

n

'0 ~

L

IN 1

/1--1--0

0--1--1""--

EN

"

L6203
TO CONTROL
CIRCUIT

;UB

O.ZIl

Rs

FUNCTION

INPUTS

V EN = H

IN1 = H

IN2 = L

Turn right

IN1 = L

IN2 = H

Turn left

IN1 = IN2
VEN = L

L= Low

IN 2

IN1 = X

Fast motor stop
IN1 = IN2

H = High

Free running motor stop

X = Don't care

Fig, 8 - Application circuit
'Vs

5V

18nF

CB'

01
22Ke.
JJnF::J: C
11

GNO

L6203

02
IBnF

10
16

CB2

12

CW/CWW

:r.

INHl

O.22,uF

14

"51
L297
13

'0

L6203

iNH2

11

:r:::

O.2Z~F

5-9!>25

CONTROL

585

lB.

ADVANCE DATA

DUAL FULL BRIDGE DRIVER
•

emitters of the lower transistors of each bridge
are connected togheter and the corresponding
external terminal can be used for the connection
of an external sensing resistor. An additional
supply input is proliided so that the logic works
at a lower voltage.

POWER SUPPLY VOLTAGE UP TO 46V

•

LOW SATURATION VOLTAGE

•

OVERTEMPERATURE PROTECTION

•

LOGIC "0" INPUT VOLTAGE UP TO 1.5V
(HIGH NOISE IMMUNITY)

The L6207 is an integrated monolithic circuit
in a 15-lead multiwatt package. It is a high current dual full-bridge driver designed to accept
standard TTL logic levels and drive inductive
load such as relays, solenoids, DC and stepper
motors.

Multiwatt 15

Two inhibit inputs are provided to disable the
device independently of the input signals. The

ORDERING NUMBER: L6207

BLOCK DIAGRAM
DUll

OUT3

0012

OUTO

'Iss

Inl

12

InO

In2

10

In3

EnA

II

EnB

SENSE B

SENSE A

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

587

12/86

Fig. 1 - Switching times test circuit

Fig. la - Source current delay times vs. input chopper

+---..-----------,.---

Imax(1.25A)
90~.

-

S ~9302

~-930J

note: For INPUT chopper, set EN

=H

Fig. 2 - Switching time test circuits

VSS=5V

Fig. 2a - Sink current delay times vs. input chopper

VS·42V

Imax(1.25AI +--~----------:7'---

90'/. -

VI (4V)

so·/.

note: For INPUT chopper, set EN = H

589

ELECTRICAL CHARACTERISTICS (continued)
Parameter

Test Conditions

Min.

Typ.

Max.

Unit

T5 (VI)

Sink current turn-off delay

0.5 VI to 0.9 IL ("0)

0.7

ILs

T6 (VI)

Sink current fall time

0.9 IL to 0.1 IL ('.0)

0.2

ILs

Sink current turn on delay

0.5 VI to O.lIL (

)

1.5

ILs

T8 (VI)

Sink current rise time

0.1 IL to 0.9 IL (

)

0.2

ILs

fc

Commutation frequency

IL = 1.25A

n

(VI)

...
...

(**) See
(*) Sensing voltage can be -lV for t < 501Ls; in steady state Vsens min> -0.5V;
(1) The value of the current is related to only one channel
• The correct sequence for power on is:
1. Vss ON with EN = L
for power off is:
2. Vs ON
3. EN = H

Fig.3 - Bidirectional DC motor control
'Vs
~

D'

D3

D

'2

'-------4----+'''''-oVinh
TO CONTROL

CIRCUIT
01 TO 04:1"

HIGH~SPEEO

DIODE

TRUTH TABLE
INPUTS

VEN = H

FUNCTION

C = H

D = L

Turn right

C = L

D = H

Turn left

C = D
VEN = L
L = Low

C = X

H

High

Fast motor stop
D = X

X

591

Free running motor stop
Don't care

25

40

fig. 1a;

("0) See fig. 2a

1. EN = L
2. Vs ON
3. Vss OFF

KHz

ADVANCE DATA

3A FULL BRIDGE DRIVER WITH DIODES
•

SUPPLY VOLTAGE UP TO 46V

•

OUTPUT CURRENT UP TO 3A (4A PEAK)

•

SEPARATE CONNECTIONS FOR SUPPLIES
AND DIODES
FOR

An enable input allows all four transistors of
the bridge to be switched off independently
of the input commands.
Each half bridge can be connected to an external sense resistor and have a separate high
voltage supply.

EXTERNAL SENSE

•

CONNECTION
RESISTOR

•

LOW SATURATION VOLTAGE (3.5V TYP
AT 3A)

•

THERMAL SHUT DOWN WITH HYSTERESIS

•

J.!P COMPATIBLE LOGIC INPUTS W'TH
HIGH NOISE IMMUNITY

An additional supply input is provided so that
the logic can operate at a lower voltage, reducing
dissipation.

•

LOW LEAKAGE FAST RECOVERY DIODES

The device is equipped with a thermal protection
which, switches off the input and output stages
when the temperature reaches 150°C and switches
on with hysteresis when the temperature decreases.

•

NO CURRENT FROM HIGH VOLTAGE
SUPPLIES WHEN ENABLE PIN IS LOW

Another important feature
speed (less than 1.5J.!s).

is the switching

The L6209 is supplied in a 15-lead Multiwatt@
package.

The L6209 is a high voltage, high current fullbridge driver with internal fast recovery diodes.
The cathodes of the upper recirculation diodes
and the anodes of the lower ones are externally
available to allow flexibility in application.

Multiwatt-15

The device is designed to accept standard TTL
logic levels and drive inductive loads such as
relays, solenoids, DC motors and stepping
motors.

ORDER ING NUMBER: L6209

BLOCK DIAGRAM
Vss
13

12

10

15

SENSEI

Oll

Dll

!N2

14

SENSE2

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

593

12/86

Fig. 1 - Switching times test circuits

Fig. 1a - Source current delay times vs. input chopper

INPUT
Imax(lA) -I---~----------______- - -

ENABLE

~-929'

Note: For INPUT chopper, set EN = H
5-9293

Fig. 2 - Switching times test circuits

Fig.2a - Sink current delay times vs. input chopper
IL

Imax(lA) -1---__- - - - - - - - - - - " . . - - gO',. -

Vi (5V)

Note: For INPUT chopper, set EN

=H

SO·/.
50-9294

Fig. 3 - Switching times test circuits

Fig.3a - Source current delay times vs. enable chopper.
IL

Imax(3A) -j....--__----------~---

50-929'

Note: For enable chopper in this
configuration, set, INPUT = H
50-9295

595

ELECTRICAL CHARACTERISTICS (continued)
Parameter
VCE sat (Ll

Saturation voltage

Total drop

VCEsat

Diode forward voltage drop

VF

Test Conditions

Min.

Typ.

Max.

IL

=

IL

= 3A

IL

=

lA

2.1

3

IL

= 3A

3.5

4.5

10

=

10

=

lA

Unit

1
V

V

lA

1

3A

1.5

V

trr

Diode reverse recovery time

If = lA
IRM = 2.5A

tfr

Diode forward recovery time

Tl (VIN)

dlf/dt = -50A/JJs
V R = 42V

100

ns

dlf/dt = l00A/lls
If = lA
Measured at VF = lV

100

ns

Source current turn-off delay

0.5 Vi to 0.9 IL (2)

750

ns

T2 (VIN)

Source current fall time

0.9 IL to 0.1 IL (2)

430

ns

T3 (VIN)

Source current turn-on delay

0.5 VI to 0.1 IL (2)

1.1

IlS

T4 (VIN)

Source current rise time

0.1 IL to 0.9 IL (2)

500

ns

T5 (VIN)

Sink current turn-off delay

0.5 VI to 0.9 IL (3)

700

ns

T6 (VIN)

Sink current fall time

0.9 IL to 0.1 IL (3)

500

ns

T7 (VIN)

Sink current turn-on delay

0.5 Vi to 0.1 IL (3)

950

ns

T8 (VIN)

Sink current rise time

0.1 IL to 0.9 IL (3)

400

ns

T9 (V IN )

Source current turn-off delay

0.5 VI to 0.9 IL (4)

450

ns

Tl0 (VIN)

Source current fall time

0.9 IL to 0.1 IL (4)

250

ns

Tll (VIN)

Source current turn-on delay

0.5 VI to 0.1 IL (4)

550

ns

T12 (V IN )

Source current rise time

0.1 IL to 0.9 IL (4)

250

ns

T13 (VIN)

Sink current turn-off delay

0.5 VI to 0.9 IL (5)

350

ns

T14 (VIN)

Sink current fall time

0.9 IL to 0.1 IL (5)

200

ns

T15 (VIN)

Sink current turn-on delay

0.5 Vi to 0.1 IL (5)

800

ns

T16 (VIN)

Sink current rise time

0.1 IL to 0.9 IL (5)

200

fc

Com mutation frequency

IL

NOTE:

(1)
(2)
(3)
(4)
(5)

=

35

3A

Sensing voltage can be -lV for t .;;; 501lS; in steady state V sens min .. -0.5V
See fig. la. (INPUT chopper)
See fig. 2a. (I NPUT chopper)
See fig. 3a. (ENABLE chopper)
See fig. 4a. (ENABLE chopper)

597

ns
60

KHz

<;~;\~~I~]1~:t~,
ADVANCE DATA

DUAL

SCHOTTKY
OF

DIODE

•

MONOLITHIC ARRAY
SCHOTTKY DIODES

•

HIGH EFFICIENCY

•

4A PEAK CURRENT

•

LOW FORWARD VOLTAGE

•

FAST RECOVERY TIME

•

TWO SEPARATED DIODE BRIDGES

BRIDGE

EIGHT

due to low forward voltage drop and fast reverse
recovery time, are required.
The L6210 is available in a 16 Pin Powerdip
Package (12+2+2) designed for the 0 to 70°C
ambient temperature range.

The L6210 is a monolithic IC containing eight
Schottky diodes arranged as two separated
diode bridges.

Powerdip 12 + 2
(V6P2)

+2

This diodes connection makes this device versatile in many applications.
They are used particular in bipolar stepper motor
applications, where high efficient operation,

ORDERING NUMBER: L6210

ABSOLUTE MAXIMUM RATINGS
2
50

Repetitive forward current peak
Peak reverse voltage (per diode)
Operating ambient temperature
Storage temperature range

70

-55 to 150

BLOCK DIAGRAM
16,9.(')

(). 1.8

~

~

0

~~

~~

().2

~~

15

10

().7
~

~~

~~

.il

~~

11.14

(). 3,6
~

1.

S-9320/1

4,5,12,13
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

599

12/86

Fig. 2 - Forward voltage vs.
current

Fig. 1 - Reverse current vs.
voltage
ld

tAl

....::i

~~
T) ",lZS'C
fj=75'C,
0.3

!10-1

Ti",25'C

t----t--

0.1

"",,.C-V),

1/1
06

20

0.6

MOUNTING INSTRUCTIONS
During soldering the pin temperature must not
exceed 260°C and the soldering time must not
be longer then 12s. The external heatsink or
printed circuit copper area must be connected
to electrical ground.

The RthJ-amb of the L6210 can be reduced by
soldering the GND pins to a suitable copper
area of the printed circuit board as shown in
figure 3 or to an external heatsink (Figure 4).

Fig. 3 - Example of P.C. board copper area
which is used as heatsink

Fig. 4 - Example of an
external heatsink

P.C.BOARD

601

II.

ADVANCE DATA

HIGH CURRENT SOLENOID DRIVER
•

HIGH VOLTAGE OPERATION (UP TO 50V)

•

HIGH OUTPUT CURRENT CAPABILITY
(UP TO 6A)

•

LOW SATURATION VOLTAGE

such as hammer driving in printers and electronic
typewriters. Power dissipation is reduced by efficient switch-mode operation. An extra feature
of the L6212 is a latched diagnostic output
which indicates when the output is short circuit.
The L6212 is supplied in an 15-lead Multiwatt
plastic power package.

• TTL-COMPATIBLE INPUT
• OUTPUT SHORT CIRCUIT PROTECTION
(TO GROUND, TO SUPPLY AND ACROSS
THE LOAD)
• THERMAL SHUTDOWN
• OVERDRIVING PROTECTION
•

Multiwatt-15

LATCHED DIAGNOSTIC OUTPUT

The L6212 is a monolithic switch-mode solenoid
driver designed for fast, high-current applications

ORDERING NUMBER: L6212

BLOCK DIAGRAM
OIAG. OUT

+Vss

+Vs

C1
5-9300

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

603

12/86

ELECTRICAL CHARACTERISTICS

(Refer to the test circuit, V.

= 37V,

Vss

= 5V,

Tamb

25°C, unless otherwise specified)
Parameter
V.

Power supply voltage (Pin 1)

Id

Quiescent drain current

V"

Logic supply voltage (Pin 6)

Iss

Quiescent logic supply current

Test Conditions

Min.
12

V EN

=H

20

Vi ;. 0.6V

VEN

=

4.5
V OIAG

Input voltage (Pin 9)

=L

Operating output

Max.

Unit

46

V

30

mA

70

L

DIAG Output at high
impedance
Vi

Typ.

mA
7

V

5

8

mA

10

100

p.A

0.6

V

Non-operative output

0.45

V

-2
-5

p.A
p.A

0.8

V

-100
100

.p.A

2.5

V
V

Ii

Input current (Pin 9)

Vi ;. 0.6V
Vi" 0.45V

VENABLE

Enable input current (Pin 12)

Low level
High level

IENABLE

Enable input current

V EN
V EN

Vsat H

Source output saturation volt.

Ip

Vsat L

Sink output saturation volt.

lout

= 5.5A

2.5

V.at H + V,at L

Total satu ration voltage

lout

=

4.5

V

Ileakage

Output leakage current source
PNP

Vs = 45V
V J .. 0.45V

2

mA

Ileakage

Output leakage current sink
NPN

V, = 45V
Vi .. 0.45V

2

mA

0.4

V

10

p.A

10
1.5

p.A
mA

-0.3
2.4

=L
=H

VI
Ve

= 0.8V
= 2.4V

= 5.5A

=

5.5A

K

On time limiter constant (')

V EN

V OIAG

Diagnostic saturation voltage
(Pin 7)

IOIAG

120

IOJAG

Diagnostic leakage current
(Pin 7)

VOI AG

= 40V

Vpin 10

OP AMP DC voltage gain

V p in13

= 100

V pin 10

Ipin10

= lmA

Ipin10

Vpln 10
V pin 10

= 4V
= 2V

L

=

10mA

5

to 800mV

Vpin 13

'sense

Input bias current (Pin 13)

Vsense

Sensing voltage (Pin 14) (**)

4.5
Vg = V 13 = 0
V 13 = 0.9V

V

1
-1

IJ.A
0.9

(*) After a time interval t max = KC 2 • the output stages are disabled.
(.*) Allowed range of Vsense without the intervention of the short circuit protection.

605

V

CIRCUIT OPERATION
be chosen in the range 2.7 to 10nF for stability
reasons of the op amp).

The L6212 works as a transconductance amplifier: it can supply an output current directly proportional to an input voltage level (Vi)' Furthermore, it allows complete switching control of
the output current waveform (see Fig. 1).

After t 1 , the comparator switches again: the
output is confirmed by the voltage on the noninverting input, which reaches Vi again (hysteresis).

The following explanation refers to the Block
Diagram, to Fig. 1 and to the typical application circuit of Fig. 2.

Now the cycle starts again: t 2 , t4 and t6 have
the same characteristics as t r, while t3 and t5
are similar to t 1 . The peak current Ip depends
on Vi as shown in the typical transfer function
of Fig. 3.

The ton time is fixed by the width of the Enable
input signal (TTL compatible): it is active low
and enables the output stages "source" and
"sink". At the end of ton, the load current Iload
recirculates through Dl and D2, allowing fast
current turn-off.

It can be seen that for VI lower than 450mV
the device is not operating.
For Vi included between 450 and 600mV, the
operation is not guaranteed.

The rise time tr depends on the load characteristics, on VI and on the supply voltage value
(Vs, pin 1).

The other parts of the device have protection
and diagnostic functions. At pin 4 is connected
an external capacitor C2, charged at constant
current when the Enable is low.

During the ton time, Iload is converter into a
voltage signal by means of the external sensing
resistance Rs connected to pin 13. This signal,
amplified by the op amp charges the external
RC network at pin 10 (Rl, Cl). The voltage
at this pin is sensed by the inverting input of
a comparator. The voltage on the non-inverting
input of this one is fixed by the external voltage
Vi (pin 9).

After a time interval equal to K • Cl (K is
defined in the table of Electrical Characteristics
and has the dimensions of [2) the output stages
are switched off independently by the Input
signal.
This avoids the load being driven in conduction
for an excessive period of time (overdriving
protection) .

After, t r , the comparator switches and the output stage "source" is switched off. The comparator output is confirmed by the voltage on
the non-inverting input, which decreases of a
constant fraction of Vi (1/10), allowing hysteresis
operation. The current in the load now flows
through D2.

The action of this protection is shown in Fig.
1b. Note that the voltage ramp at pin 4 starts
whenever the Enable signal becomes active (low
state), regardless of the Input signal. To reset
pin 4 and to restore the normal conditions, pin
12 must return high. This protection can be
disabled by grounding pin 4.
In order to keep constant the energy delivered
to the load, when the supply voltage changes,
it's possible to modify the output maximum
peak current (Ip) by means the external voltage
divider R2 and R3 which "senses" the supply
voltage.

Two cases are possible: the time constant of the
recirculation phase is higher than Rl, Cl; the
time constant is lower than R 1, Cl. In the first
case, the voltage sensed on the non-inverting
input of the comparator is just the value proportional to Iload' In the second case, when the
current decreases too quickly, the comparator
senses the voltage signal stored in the R 1, Cl
network.

Ip is given by :

In the first case t1 depends on the load characteristics, while in the second case it depends
only on the value of R 1, Cl.

I

In other words, R 1, Cl fixed the minimum value
of t1 (t1 ;;' 1/10 Rl x Cl. Note that Cl should

p

Vi (R s + R2 + R3) - 5 Vs (R2 + Rs)
= ---'--=------:::--=:c=-=-::..-----'=5 R3 Rs

so the variation of Ip versus Vs is:
607

II.

ADVANCE DATA

STEPPER MOTOR DRIVER

•

BUILT-IN FAST RECOVERY DIODES

The power section of the device is a dual HBridge drive with internal clamp diodes for
current recirculation. To maintain the degree
of accuracy required for micro-stepping, the
motor current is internally sensed and compared
to the output of the D/ A converter.

•

OUTPUT CURRENT DIGITALLY PROGRAMMABLE

A monostable, programmed by and RC network
sets the motor current decay time.

•

6 BIT D/A CONVERTERS SET OUTPUT
CURRENT

The L6217 is supplied in a 44 pin PLCC with 11
of the 44 pins used for heatsinking.

•

THERMAL SHUTDOWN

•

MICROSTEPPING

•

BIPOLAR
400mA

•

LOW SATURATION VOLTAGE

OUTPUT CURRENT UP TO

The L6217 is a monolithic IC that controls and
drives both phases of a Bipolar Stepper Motor
with PWM control of the phase current. The
output current level of each phase is programmed
by a 6 bit D/A converter so that the device may
be used in full-step, half-step and micro-step applications. The inputs for the D/A converters and
the phase inputs to select the direction of current
flow are latched to minimize the interface to a
microprocessor.

PLCC44
(Plastic Chip-Carrier)
ORDERING NUMBER: L6217

BLOCK DIAGRAM
TTL ~l
INTERFACES

TESTA

PTA

(WITH DELAY)

PH

OUTPUT Al

33

MB 05o-="tl-t----r-t

o,o--"""N-f----.-+-l
03

36

l
A
T
C

H

02o-'-'N-f---r-t++-l

E
S

8
U

F
F
E

•

Ii BIT

OIA

S

0'

l B

cc"'&-+----r+-f-++-l

ooo"'N-f-...--f+-t++-l

CSf"o-'-D-++I+t++I

"__9."0_M~Dl

r -_ _ _ _ _ _ _ _ _ _ _ _
"_-2-,O~.

~NonlPIN5J

~~-~I:~F':UT

P18

RST

t

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

609

12/86

PIN FUNCTION DESCRIPTION
NAME

FUNCTION

Active low input resets the OfA latches to 0 and disables the
output.
38,39

00- 05

Data inputs for the OfA converter. (DO = LSB)
For a data input of 00, the corresponding outputs are held in the
off state.

44

AlB

Channel select for i~put data. Pin
high.

33

PH

Logic input selects direction of current flow in output bridge
from A1 (B1) to A2 (B2) for PH = 1.

42

9

AlB

selects channel A when

Active low input latches input data (DO - 05 and PH) into
input latch.
MRST OL

The capacitor on this pin programs the power on reset delay according to the formula:
td = (0.35) (C) 106
Power-on reset circuit output. (Micro reset signal).
This output remains low from power on until the delay capacitor
has charged past the delay threshold.

10

PtA

Pulse time A, an external parallel RC network tied to ground
defines toff time for channel A. (tOff = 0.69 R2C2).

11

PtB

Pulse time B, an external parallel RC network tied to ground
defines toll time for channel B. (toff = 0.69 R3C3).

5

Vref1n

Voltage applied to this point sets the reference for the Of A converter and threfore sets the maximum output current.
(See equation 1, next two pages).

18 to 28

Gnd

Ground connection and also conducts heat to the P.C. board.

40

GndO

Pin must be connected to ground.

2

VS1

Logic supply voltage

32

VSP

Motor supply voltage

611

ELECTRICAL CHARACTERISTICS (continued)
Parameter

Test Conditions

MONOSTABLE
tOff

Cutoff time

td

Turn-off delay

loff

Output leakage current

= 56KO
= 820pF

Rt
Ct

Data

= 00

37

27

(Hex)

J.LS

2

J.LS

100

J.LA

RESET CIRCUITRY
V th

Reset threshold voltage

3.9

4.1

Reset threshold hysteresis

70

100

7

10

= 2.5V
= 2.5V

Iso

Delay capacitor charging current

Vc

lsi

Delay capacitor discharge current

Vc

Vdth
V dhYS

Delay threshold voltage

101

Output leakage current

Vo

V.at

Output saturation of reset out

10

4.3
14

= 5V
= 2mA

J.LA
mA

10

Hysteresis voltage on delay threshold

V
mV

3.25

3.5

70

100

3.75

V
mV

200

J.LA

0.4

V

SOURCE DIODE -TRANSISTOR PAIRS
V.at

Saturation voltage

10 = 400mA

Vf

Diode forward voltage

10 = 400mA

SINK DIODE-TRANSISTOR PAIRS
V sat

Saturation voltage

10 = 400mA

Vf

Diode Forward voltage

10 = 400mA

AC CHARACTERISTICS
t.

Set-up time

100

ns

th

Hold time

500

ns

tw

Minimum input pulse width

600

ns

CIRCUIT OPERATION
The current control section of the L6217 is a
pulse width modulated control that senses the
motor current. When the motor current reaches
the peak programmed current the comparator
will trigger the monostable turning off the upper
transistors. After the toff time equal to 0.69 RC
the upper drivers are enabled again.

When the input data is 00, the output stages
are disabled by internal logic so that the output
current decays rapidly to zero.
An internal generated lockout time avoids the
use of an external RC network between the sensing resistor (RsA, R.B) and the corresponding
input (V.A, V.B), by disabling the comparator
sensing during the lockout time. This time is
typically 2.5ms.

The peak current is given by the equation:
Vref

4.69 •
D

Rsense

D

64

Input data (0 - 63)
613

Fig. 5 - Monostable voltage and motor current
repetitive steps.

Fig. 4 - Motor current (half step mode)

Fig. 6 - Reset waveforms

Vs ( min
Vth Hmax
Vth

H ----~~~--~-=--:-:-:-:-:J~-:-tlHV~S~TIEaRE~S~laS~~~----

Vth Hmin

RESET OUT
:

tD :

r---1

5-9268

615

aB.

ADVANCE DATA

STEPPER MOTOR DRIVER

•

LOW SATURATION VOLTAGE

•

BUILT-IN FAST RECOVERY DIODES

The power section of the device is a dual HBridge drive with internal clamp diodes for
current recirculation. To maintain the degree
of accuracy required for microstepping, the
motor current is internally sensed and compared
to the output of the 0/ A converter.

•

OUTPUT CURRENT DIGITALLY PROGRAMMABLE

A monostable, programmed by and RC network
sets the motor current decay time.

•

7 BIT D/A CONVERTERS SET OUTPUT
CURRENT

The L6217 A is supplied in a 44 pin in PLCC with
11 of the 44 pins used for heatsinking.

•

THERMAL SHUTDOWN

•

MICROSTEPPING

•

BIPOLAR
400mA

OUTPUT CURRENT UP TO

The L6217 A is a monolithic IC that controls and
drives both phases of a Bipolar Stepper Motor
with PWM control of the phase current. The
output current level of each phase is programmed
by a 7 bit D/A converter so that the device may
b~ used in full-step, half-step and micro-step applications. The inputs for the 0/ A converters and
the phase inputs to select the direction of current
flow are latched to minimize the interface to a
microprocessor.

PLCC 44
(Plastic Chip-Carrier)
ORDERING NUMBER: L6217A

BLOCK DIAGRAM
TTL

eL

PTA

INTERFACES

(WITH DELAY)

PH
I.t

33

B D6o""N-+----.-I

'{S]-t---.--H

DS02-S
04

02

36

38
39

ffiO-CU+t-t+++-H-l
STROBE~42U+t-t+++~-l

cso"""'u+t-t++++-+-l

AIB~D--H-t+++-H-1
TTl-l'l ~ I
INTERFACES
(NORMAL)

R:n~1~

______

~~

L -_ _ _ _ _ _ _ _ _ _ _-~

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

617

12/86

PIN FUNCTION DESCRIPTION
NAME

FUNCTION
Active low input resets the D/A latches to 0 and disables the
output.

40,34

DO- D6

Data inputs for the D/A converter. (DO = LSB)
For a data input of 00, the corresponding outputs are held in the
off state.

44

AlB

Channel select for input data. Pin AlB selects channel A when
high.

33

PH

Logic input selects direction of current flow in output bridge
fromA1 (B1) toA2 (B2) for PH = 1.

42

9

Active low input latches input data (DO - D5 and PH) into
input latch.
MRST DL

The capacitor on this pin programs the power on reset delay according to the formula:
td = (0.35) (C) 106
Power-on reset circuit output. (Micro reset signal).
This output remains low from power on until the delay capacitor
has charged past the delay threshold.

8

10

PtA

Pulse time A, an external parallel RC network tied to ground
defines toff time for channel A. (toff = 0.69 R2C2).

11

PtB

Pulse time B, an external parallel RC network tied to ground
defines toff time for channel B. (tOff = 0.69 R2C2)

5

Vrefln

Voltage applied to this point sets the reference for the D/A converter and threfore sets the maximum output current.
(See equation 1, next two pages).

Gnd

Ground connection and also conduct heat to the P.C. board.

2

VSI

Logic supply voltage

32

VSP

Motor supply voltage

16, 15
31,30

Out A1-A2'
B1-B2

H-Bridge outputs.

18 to 28

619

ELECTRICAL CHARACTERISTICS (continued)
Parameter

Test Conditions

MONOSTABLE
Cutoff time
toff
td
loff

Rt = 56Kn
= 820pF

Max.

Unit

37

p.s

2
100

p.s
p.A

4.1
100
10

4.3

3.5
100

3.75
200
0.4

V
mV
p.A
mA
V
mV
p.A
V

27

Ct

Turn-off delay
Output leakage current

Typ.

Min.

Data = 00 (Hex)

RESET CIRCUITRY
Vth
Reset threshold voltage
Reset threshold hysteresis
Delay capacitor charging current
Iso
Delay capacitor discharge current
151
Delay threshold voltage
Vdth
VdhyS
Hysteresis voltage on delay threshold
Output leakage current
101
Vsat
Output saturation of reset out

Vc
Vc

Vo
10

SOURCE DIODE-TRANSISTOR PAIRS
Saturation voltage
Diode forward voltage
Vf

rVsat

SINK DIODE-TRANSISTOR PAIRS
Saturation voltage
Vsat
Diode Forward voltage
Vf

r
r

= 2.5V
= 2.5V

14

= 5V
= 2mA
= 400mA
= 400mA

I

I

1.3
0.8

I

1.8
1.2

V
V

I

110 = 400mA
110 = 400mA

I

I

I

I

I

1.1
0.6

1.5
1.0

V
V

I
I

100
500
600

ns
ns
ns

110
110

r

3.9
70
7
10
3.25
70

I

I

AC CHARACTERISTICS
Set-up time
ts
Hold time
th
Minimum input pulse width
tw

I

I
I

I

CIRCUIT OPERATION
The current control section of the L6217 A is a
pulse width modulated control that senses the
motor current. When the motor current reaches
the peak programmed current the comparator
will trigger the monostable turning off the upper
transistors. After the toff time equal to 0.69 RC
the upper drivers are enabled again.

When the input data is 00, the output stages
are disabled by internal logic so that the output
current decays rapidly to zero.
An internal generated lockout time avoids the
use of an external RC network between the sens·
ing resistor (RsA, RsB) and the corresponding
input (V5 A, VsB), by disabling the comparator
sensing during the lockout time. This time is
typically 2.5ps.

The peak current is given by the equation:

.-D

4.69 • Rsense

o

128

Input data (0 - 7F H)

621

Fig. 4 - Motor current (half step model

Fig. 5 - Monostable voltage and motor current
for repetitive steps.

Fig. 6 - Reset waveforms
Vs \ min
Vth Hmax
Vth H

4.75V

----~-:~--~-~-:--:-:-:-:J~-:-~H!VS~T~E~R~E~S\~S~~~----

Vth Hmin

RESET OUT

to .

r----i

5-9268

623

aB.

ADVANCE DATA

QUAD DARLINGTON SWITCHES
of the four switches are commoned. Any number
of inputs and outputs of the same device may be
paralleled.

•

OUTPUT VOLTAGE TO 50V

•

OUTPUT CURRENT TO 1.8A

•

VERY LOW SATURATION VOLTAGE

Two versions are available: the L6221 A mounted
in a Powerdip 12+2+ 2 package and the L6221N
mounted in a 15-lead Multiwatt package.

• TTL COMPATIBLE INPUTS
• 'INTEGRAL FAST RECIRCULATION DIODES
The L6221 monolithic quad darlington switch
is designed for high current. high voltage switch·
ing applications. Each of the four switches is
controlled by a logic input and all four are con·
trolled by a common enable input. All inputs
are TTL-compatible for direct connection to
logic ci rcu its.

Powerdip 12 + 2
(V6P2)

Multiwatt 15

Each switch consists of an open-collector darling·
ton transistor plus a fast diode for switching
applications with inductive loads. The emitters

+2

ORDERING NUMBER:
L6221N
L6221 A

BLOCK DIAGRAMS
• Vs

• Vs

11
IN 1

r>-~--r_

r-~-_-+'-.,DOUT

1

INI

n--"-I~-'

,-....,...-_-;-"--0 OUT 1

CLAMP A

IN2 "-----'-'-'"-,

IN 3

r-~-"""-+---300mvpp
LOW LEVEL
ANALOG HALL
OUTPUT

s- 9316

• This signal may require filtering if chopped mode drive scheme is used.

653

Fig. 5 - Phase Detector State Diagram
RISING EDGE
ON PHASE DETECTO)
-INPUT
(REfERENCEI

RISING EDGE
ON PH~E DETECTOR
+ INPUT
(SENSE AMP)

C
•

•

OUTPUT •

I

~V

OUTpuT· 2.SV

I

OUTPUT. OV

DIGITAl. LOCK fIIIDICATOR HIGH DURING STATES 1. 2. 6. AND 7
S-94ZI

Fig. 6 - Suggested Loop Filter Configuration
R1

ROM REF.
UER

R3

Vln

R3

1 + S/wZ

R1

1 + S/wP

~____- 0 R4 Goes to OV
< 0 R4 Goes to 5.0V

lB.

ADVANCE DATA

HAMMER SOLENOID CONTROLLER
•

DRIVES FOUR DARLINGTONS WITH UP
TO 2.5mA DRIVE CURRENT

•

FEEDBACK LOOP
LINGTON CURRENT

•

PRESETTABLE CONDUCTION TIME

CONTROLS

•

LATCHED J,lC-COMPATIBLE INPUTS

•

DIAGNOSTIC CIRCUITRY

Fault conditions may be detected thanks to
diagnostic circuitry which allows the control
micro to read (serially) the load current status
of the external darlingtons.

DAR-

Assembled in a 20-pin DIP package, the L6503
operates on a single 5V supply and is suitable
for computer printers, solenoid valves and
similar applications.

Designed primarily for solenoid driving applications, the L6503 Hammer Solenoid Controller
includes all the circuitry needed to control four
darlington power devices or a quad darlington
array such as the SGS L7180.

DIP-20 Plastic

The device is controlled by four latched logic
inputs, which may be connected directly to a
microcomputer chip, plus an analog input which
sets the load current. Additionally, the conduction time of the outputs is controlled by a clock
input which drives internal timers.

(X3P2)

ORDERING NUMBER: L6503

BLOCK DIAGRAM

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

6V

lVOO

PIN FUNCTION DESCRIPTION

N°

NAME

FUNCTION

1

DATA

latches control command into the four inputs DEC1DEC4 on the high-low transition.

2

Vref

Analog reference input which sets the load current for
all four channels; when lower than 0.5V resets the
logic circuitry.

3

DEC2

Data input for channel 2. Data is latched on the highlow transition of the DATA input.

4

DEC1

Data input for channell.

5

IN

Input for diagnostic shift register used to cascade
several device.

6

CDE2

Channel 2 output (connect to base of darlington). Up
to 2.5mA drive.

7

RM2

Feedback input from sensing resistor of channel 2
darlington.

8

CDE1

Channel 1 output.

9

RM1

Feedback input for channell sense resistor.

10

GND

Ground.

11

DROP

Clock input for diagnostic register.

12

RM3

Feedback input for channel 3 sense resistor.

13

CDE3

Channel 3 output.

14

RM4

Feedback input for channel 4 sense resistor.

15

CDE4

Channel 4 output.

16

OUT

Output of diagnostic register.

17

DEC3

Input for channel 3.

18

DEC4

Input for channel 4.

19

ClK

Input for clock signal which sets conduction time
for all four channels. Ton = 128lfcLK .

20

V..

5V supply input voltage.

659

FUNCTIONAL DESCRIPTION
During the conduction period the load current
is controlled by feedback from a sense resistor
in the darlington's emitter and set by the voltage
applied to the V ref input. The current depends
on both the values of Vref and the sensing
resistor: I = V ref/Rsense'

The l6503 Hammer Solenoid Controller is
designed to control a quad darlington array,
such as the SGS l7180, in solenoid driving
applications.
Compatible with 5V microcomputer and peripheral chips, the l6503 is controlled .EY...!.our
logic inputs - one per channel (DEC1- DEC4) which are latched by a high-low transition on
the DATA input.

The control microcomputer may verify correct
operation of the complete drive subsystem
thanks to a diagnostic circuit in the l6503. A
four bit PISO shift register in the device monitors
the feedback signals from the four output darlingtons and may be read serially after each
command to check that the loads were driven.

When one of the channels is activated the corresponding darlington is driven, with up to
2.5mA drive current. The conduction period is
determined by the frequency applied to the ClK
input which clocks the 7-bit timer in each
channel. The conduction time is therefore 128/
fClK. Typically the ClK frequency will be of
the order of 100KHz but the l6503's internal
logic will operate at any clock rate within the
range of practical conduction times.

Typically, this register, clocked by the DROP
input, will be read a short time after each drive
command has been latched into the device.
The input of this register (I N) is available externally so that multiple devices may be cascaded.

Fig. 1 - Application diagram
+V •• j
,...-

-

-DECS

4

SO aND,

DEC2

3

S5 CDE4 15

S7

S3 CDE3

a

CDE2

7

DEC3
DEC4
AlP

DATA
CLK
DAOP

IN
OUT

-

+V.

j+VAEF

I!O 2

L71BO

...

..J

sa
S

L6503

sa
ss

I

.....J

CDE! S

8

--

~
..J .. 4
PI

a

5

sa
a

~
~

I..J

i-

S3

S4
7

S2 S4

l

I

SO

a

2

a

.L
AM4

AMS

) [ ) I)
...
661

S-9275

~
~®

Technology
and SelVice
ADVANCE DATA

SOLENOID CONTROLLER
•

SWITCH MODE CURRENT REGULATION

•

TTL COMPATIBLE LOGIC INPUTS

•

DRIVES ONE OR TWO EXTERNAL POWER
TRANSISTORS

•

VERY PRECISE ON-CHIP REFERENCE

•

ANALOG CURRENT CONTROL INPUT

•

ADJUSTABLE CURRENT RISE AND FALL
TIME CONTROL INDEPENDENT OF
SOLENOID SUPPLY VOLTAGE

•

UNDERVOLTAGE LOCKOUT

is controlled by three logic inputs and features
switchmode regulation of the load current. A
key feature of the device is that the rise and fall
time of the load current can be set by external
components. Additionally an analog input allows
the load current to be set by an external DC voltage. An undervoltage lockout circuit guarantees
the. output off state for switch on phase.

DIP-14 Plastic
(0.25)

Designed for use with one external power transistor, the L6504 drives the hammer solenoid in
daisywheel printers and typewrites. The device

ORDERING NUMBER: L6504

BLOCK DIAGRAM
+ VS
+VSS

10

LJ

1

CONTROL~------~

2

P---r---~==[}--~12

SOLENOID

ENABLE ;-r-~::d=>-~:::;:=:!:===~r'
ENABLE 3~_---,

REF IN

5-9393

5
R2

CURRENT
RISE TIME
ADJUST

RISE AND
FALL TIME

CURRENT
FALL TIME
ADJUST

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to c,",ange without notice.

663

12/86

PIN FUNCTION
NAME

FUNCTION

CONTROL

TTL compatible control input. A low level activates the
output, driving the load. Internal pull-up resistor.

2

ENABLE

TTL compatible enable input. A low level disables the
output stage.

3

ENABLE

TTL compatible enable input. A high level disables the
output stage.

4

R1

The value of this resistor sets slope of trailing edge of load
current.

5

R2

The value of this resistor sets slope of leading edge of
load current.

6

REFERENCE OUT

Output for internal reference voltage.

7

C2

The value of this capacitor set the duration of power transistor switch off time.

8

C1

The value of this capacitor sets slope of leading and trailing
edge of load current.

9

SENSING

Connection for load current sense resistor. Value sets the
maximum load current: I = Vref / Rs.

10

SUPPLY VOLTAGE

Supply voltage input.

11

REFERENCE IN

I nput for external reference voltage to control load current
by DC-level.

12

PNP DRIVING OUTPUT

Output to control external PNP-transistor for fast current
discharge.

13

NPN DRIVING OUTPUT

Output for basecharge and discharge of external power
transistor.

14

GROUND

Ground.

665

Fig. 1 - Timing diagram start phase
vel (Pin 8'

V""~
I

• t

APPLICATION INFORMATION
Fig. 2 - Free running load current leading and
trai Ii ng edge

Fig. 3

+VSS

L.J

1

CONTROL

L6504
C2

REF OUTIIN

::I:

OSCILL.
FREQ.

11
L--..----r-"-T-'

5

CURRENT
RISE TIME
ADJUST

14

CURRENT
FALL TIME
ADJUST

~-9394

667

APPLICATION INFORMATION (continued)
Fig.8 - Free running leading edge fast current
slope at trailing edge

Fig. 9

669

aB.

ADVANCE DATA

CURRENT CONTROLLER FOR STEPPING MOTORS
The L6506 is a linear integrated circuit designed
to sense and control the current in stepping
motors and similar devices. When used in conjunction with the L293, L298, L7150, or L7180,
the chip set forms a constant current drive for
an inductive load and performs all the interface
function from the control logic thru the power
stage.

DIP-18 Plastic
(U7P2)

Two or more devices may be synchronized using
the sync pin. In this mode of operation the
oscillator in the master chip sets the operating
frequency in all chips.

ORDERING NUMBER: L6506

VCC

BLOCK DIAGRAM
IN'

18

5

14
OUT'

IN 2

13

OUT 2

12

IN3

OUT3

IN4

8
11

OUT 4
POWER
ENABLE

15

17

VSENSE 2
REF.2

SYNC
10
16

RIC

VSENSE 1
REF. ,

9

05C.

GND

5-9283/2

This is advanced information on a new product now in development or undergoing e"aluation. Details are subject to change without notice.

671

12/86

ELECTRICAL CHARACTERISTICS

(Vee = 5.0V, Tamb = 25°C unless otherwise noted)

Test Conditions

Parameter

Vee

Supply voltage

lee

Quiescent supply current

Min.

Typ.

Max.

Unit

7

V

25

mA

3

V

± 5.0

mV

200

nA

1

p.A

1.5

p.s

± 20

mV

± 500

nA

4.5
Vee

= 7V

COMPARATOR SECTION
V IN

Input voltage range

V sense inputs

VIO

Input offset voltage

V IN

110

I nput Offset Cu rrent

liB

Input bias current
Response time

=

-0.3

l.4V

±

V REF

= l.4V

VSENS

= 0 to

0.8

5V

COMPARATOR SECTION PERFORMANCE (over operating temperature range)
V IO

Input offset voltage

110

Input offset current

V IN = l.4V

LOGiC SECTION (over operating temperature range) - (TTL compatible inputs & outputs)
VIH

I nput high voltage

VIL

Input low voltage

V OH

Output high voltage

2.0

Vee
10H

= 4.75V
= 400p.A

VOL

Output low voltage

Vee
10L

= 4.75V
= 4.0mA

10H

Output source current
Outputs 1 - 4

Vee

= 4.75V

Vs

V

0.8

V
V

2.5
3.5
0.25

0.4

2.75

V

mA

OSCILLATOR
f OSC

Frequency Range

V th L

Lower threshold voltage

O.33Vce

V

V th H

Higher threshold voltage

0.66Vce

V

Ri

I nternal discharge resistor

5

0.7

673

70

1

1.3

KHz

Kil

APPLICATIONS INFORMATION
The circuits shown in figures 2 and 3 use the
L6506 to implement constant current drives
for stepper motors. Figure 2 shows the L6506
used with the L298 to drive a 2 phase bipolar
motor. Figure 3 shows the L6506 used with the
L7180 to drive a 4 phase unipolar motor. The
peak current can be calculated using the equation:

I

-

The L6506 may be used to implement either full
step or half step drives. In the Gase of 2 phase
bipolar stepper motor applications, if a half
step drive is used, the bridge requires an additional input to disable the power stage during
the half step. If used in conjunction with the
L298 the enable inputs may be used for this
purpose.

V,ef

peak -

For quad darlington array in 4 phase unipolar
motor applications half step may be implemented
using the 4 phase inputs.

Rsense

The circuit of Fig. 2 can be used in applications
requiring different peak and hold current values
by modifying the reference voltage.

The L6506 may also be used to implement
microstepping of either bipolar or unipolar
motors.

Fig. 2 - Application circuit bipolar stepper motor driver
5V

36V
)

I

POR

~~~~~E

18
14

1-,
-

4

r- t -

,A~ j

12

r-r-

IO

3
13

L298

1- 8

22K

nl

[

:

L6506

L-6

022Kn

FE-

I

11 t - t - 12
~11

14
1

~ 17

10

~ 16

15
1

3.9n

..

2

13t-t - 7

PHASE 1 - 6
INPUTS 1 - 7

T 5V

~

4

9

5

15

8

.

9

I .L

j~j ~

~

RSENSEO

....

5-928511

675

.....

lB.

ADVANCE DATA

2-CHANNEL FLOPPY DISK READ/WRITE CIRCUITS
The L6570A/B are integrated circuits which
perform the functions of generating write signals
and amplifying and processing read signals reo
quired for a double sided floppy disk drive. The
L6570A features a gain of 85 min and the
L6570B of 300 min. All logic inputs and outputs
are TTL compatible and all timing is externally
programmable for maximum design flexibility.

• TWO GAIN VERSIONS (A AND B)
•

COMPATIBLE WITH 8", 5.25" AND 3.5"
DRIVES.

•

INTERNAL WRITE AND ERASE CURRENT
SOURCES, EXTERNALLY SET

•

INTERNAL
SOURCE

•

CONTROL SIGNALS
PATIBLE

•

TTL SE LECT AB LE
BOOST

•

OPERATES ON +12 AND +5V POWER
SUPPLIES

CENTER

TAP

VOLTAGE

ARE TTL COM-

DIP-28 Plastic
WRITE CURRENT
R: L6570A
L6570B

BLOCK DIAGRAM
18

11

19

5

12

28

6

9

~

17

16

 70mV

I"SON"

Supply current

Vi - \/j

Vcz

Voltage clamp at the
output of each channel

Icz = 1A

20

27

V

V ZS

Voltage clamp supply
protection

I z = 10mA

20

27

V

Hysteresis of the input

VIN = 20mV pp
I = 1 KHz

20

70

mV

comparator
16

I nput bias current

V+ = V-= OV

0.2

1

IlA

los

I nput offset current

V+ = V- = OV

± 20

± 200

nA

CMR

I nput common mode
range

V ST = 3.5V to 18V

0

V sr 1.6

V

ISC

Output short circuit

Vi - Vi ;;, 70mV; Vs= 6V;
Vs = 16V;

1.2
0.25

2.6
0.7

A
A

1

2.3

A

VIH

for L9305A
for L9305A

V 5 = 6 to 12V; lor L9305C
ICD

Driver transistor curr.

Vi- Vi;;, 70mV

OC

300

Pulsed (*)

600

mA

Tj

Thermal shut-down
threshold

145

°c

Tj

Thermal shut-down
hysteresis

15

°c

V C (sat)

On status saturation
voltage

10L

Output leakage current

Vi - Vi ;;, 70mV
ICD = 100mA
I COUT =1.2A
ICOUT = 1A

1

V

250
500

IlA
IlA

for L9305A
for L9305C
for L9305A
for L9305C

Vi - Vi ;;, 70mV

(*) TON <;; 2.5ms; repetition time;;' 30ms
(**) The maximum allowed supply voltage without limiting resistors is limited by the built-in protection zener diodes

(1)

see Vcz, VZS Spec. values
The L9305 has a SOA short circuit protection - (See Fig. 1).

697

8.

ADVANCE DATA

DUAL RELAY DRIVER
•

HIGH OUTPUT CURRENT

•

HYSTERESIS INPUT COMPARATOR WITH
WIDE RANGE COMMON MODE OPERATION AND GROUND COMPATIBLE INPUTS

•

SHORT CIRCUIT PROTECTION OF OUTPUT TO Vs (16V MAX. FOR L9306) AND
(12V MAX. FOR L9306C)

•

INTERNAL THERMAL PROTECTION
WITH HYSTERESIS

•

OVERVOL TAGE CLAMPING OF THE OUTPUT

•

SINGLE SUPPLY VOLTAGE FROM 3.5V
UP TO 18V

Particular care has been taken to protect the
device against destructive failures - short circuit
of outputs to V 5, output overvoltages, supply
overvo Itage.
A built in thermal shut-down switches off the
device when the IC's internal dissipation becomes
too great and the chip termperature exceeds a
setted security threshold.
A hysteresis input comparator increases the interface's noise immunity, allowing the correct
use also in critical environments as automotive
or industrial applications.

Minidip Plastic

The L9306 and L9306C are a monolithic interface
circuit with differential input comparator and
open collector output able to sink current specifically to drive high inductive loads, relays, d.c.
motors, electro valves etc.

ORDERING NUMBER: L9306
L9306C

BLOCK DIAGRAM

'N,

'N,

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

699

12/86

ELECTRICAL CHARACTERISTICS

=

(VST

14.4V, Tamb

= 25°C refer to block diagram unless

otherwise specified)
Test Cond itions

Parameter

V ST

Max.

Unit

18 (*)

V

5
18

8
30

mA
mA

23

27

V

0.8

1.4

V

300
250

550
550

700
1200

mA
mA

20

24

27

V

500

iJA

Vl - Vi ;;. 70mV
Vi - Vl ;;. 70mV
20

VZS

Voltage clamp - supply
protection -

IzS = 10mA

VCSAT

On status saturation voltage
voltage

Vi - Vl ;;. 70mV
for L9306
for L9306C

Output short circuit current
for each channel

Vi - Vl ;;. 70mV

Vcz

Voltage clamp at the
output - each channel

Icz = 300m A

10L

Output leakage current

Vl - Vi;;' 70mV
Tamb = 25°C

IsC

Typ.

3.5

Supply voltage

Is ust. by" Supply current
Is liON" Supply current

Min.

ICOUT= 300mA
ICOUT= 250m A

for L9306
for L9306C

Is

Input bias current

Vl = Vi = 0

0.2

1

iJA

los

Input offset current

Vl = Vi = 0

± 20

± 200

nA

VIH

Hysteresis of the input
comparator

VIN = 200mVpp
f = 1 kHz

20

70

mV

CMR

Input common mode range

VST = 3.5 to 18V

0

(*)

VST-l.6V

V

The maximum allowed supply voltage without limiting resistors is limited by the built-in protection zener diodes:
see Vcz, Vzs spec. values

701

lB.

ADVANCE DATA

SOLENOID DRIVERS
The L9335 and L9336 are monolithic integrated
constant current sink drivers with internal current sensing and precision stable output current.
The output current waveform for inductive load
with switching to the holding current level after
the peak current level has been reached is fitted
for driving fuel injectors.

• WIDE SUPPLY VOLTAGE RANGE 6 TO
24V
•

INTERNAL CURRENT SENSING

•

PRECISION OUTPUT CURRENT LEVELS
2.4A/O.6A (L9335) AND 4A/1A (L9336)

•

LOW OUTPUT SATURATION VOLTAGE
2.5V AT 10 = 1.5A (L9335) AND 3V AT
10 = 3A (L9336)

• WIDE OPERATION JUNCTION TEMPERATURE RANGE -40°C TO 150°C
•

MICROPROCESSOR COMPATIBLE INPUT

•

DISABLE INPUT APPLICABLE FOR
SWITCHING OFF DURING LOAD DUMP

•

INTERNAL COMPENSATION

•

INTERNAL SUPPLY STABILIZING ZENER
DIODE

Pentawatt

ORDERING NUMBER: L9335
L9336

BLOCK DIAGRAM

INPUT

JJP
INTERFACE

DISABLE

OUTPUT

I

2~

4
DISABLE

~

REFERENCE

rl

RSEN5E

Y

S-6509/2

G..ND
~

3

This is advanced information on a new product now in development or undergoing evalUation. Details are subject to change without notice.

703

12/86

PIN FUNCTION
NAME

FUNCTIONS

INPUT

Logical input. If high, output current sink stage is activated.

2

DISABLE

Voltage at this pin higher than the disable threshold disables
the output stage and reset the reference to the lop value.

3

GRUOND

Common ground terminal.

4

OUTPUT

Open collector output of the current sink darlington transistor.

5

SUPPLY

I nternal zener diode between pin 5 and 3 stabilizes the supply
voltage for the signal processing circuitry.

THERMAL DATA
4

max

Thermal resistance junction case

ELECTRICAL CHARACTERISTICS (V s = 14.4V; T J = 25°C, unless otherwise specified)
Test Conditions

Min.

Typ.

Max.

Unit

Vi = 5V

V 2 =0

1.74
3.4

2.3
4.2

2.8
5.1

A

Vi =5V

V2 = 0

0.51
0.95

0.6
1.1

0.69
1.25

A

1
1.5

2.5
3

V

1

mA

Parameter
lop

Output peak current (L9335)
(L9336)

10H

Output hold current

Vos

Output saturation voltage (L9335)
(L9336)

10 = 1.5A
10 =3 A

Vi = 5V
V2=0

10L

Output leakage current

Vi =0

V 2 =0

BVO

Output sustaining voltage

10 = 2mA; Vi = 0; V 2 =0

V IL

Input low voltage

V IH

Input high voltage

Ii

Input current

V 2T

Disable input threshold voltage

(L9335)
(L9336)

V2H

Disable input hysteresis

42

V
0.8

Vi =5V
1.25

1.5

450

iJ.A

1.75

V

50

loa

Disable input bias current

Vzo

Supply stabilizing zener

Is = 20m A

IQ

Quiescent current

Vs = 5.5V

705

6

V
V

2

mV
450

iJ.A

7.5

9

V

2.5

10

mA

aB.

ADVANCE DATA

SIX-SOLENOID DRIVER
DRIVES SIX INJECTOR SOLENOIDS
• CUTOFF
FUNCTION
• ADJUSTABLE
PEAK CURRENT
• INJECTOR STATUS
OUTPUT
• TTL-COMPATIBLE INPUTS
• LOW POWER CONSUMPTION
• WIDE TEMPERATURE RANGE
• HIGH DENSITY 12L/LINEAR TECHNOLOGY
•

and a single reference input sets the peak current
level. A status feedback output allows the control processor to monitor correct operation.
The L9342 is realized with a high density mixed
·12L/analog technology.
Features include low power consumption and a
wide operating temperature range.

Designed for multipoint fuel injection systems,
the L9342 Multipoint Injector Driver includes
six drivers for external darlingtons with TTLcompatible inputs and circuitry which controls
the peak current.
A separate logic input controls each driver. In
addition a common logic input enables all six

BLOCK DIAGRAM

DIP-24 Plastic

ORDERING NUMBER: L9342

+5V
24

CUTOff

0-'-1------,

1- - - - - - - - - - - - - - - -

-

-- -

---i

REFINJ

,,
,,
,,

:,

INI

Z3

OUrl

/-1--+1--1"",<; SoENS I
1
I ______________________
,51
L

,,
,
I

~

OUT 1
IN2

SoENS 2

our .)
IN'
N.C.
OUT 4

IN4
5ENS4
TEl
OUT' 5
IN.
5ENS5

our 6

IN6
L ___________________________ J

SoENS 6

L9J42

GNO

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

707

PIN FUNCTIONS
NAME

2

FUNCTION

CUTOFF

Enable input. When this pin is high the six drivers
are enabled. When this input is low all six outputs
are OFF, irrespective of the inputs.

REFINJ

Injector reference. A voltage applied to this pin
sets the peak current Ip = VREFINJ/Rs. The hold
.
Ip
current IS Ih = - -

6

3,4,5
7,9,10

IN1 -IN6

Injector logic inputs. The output at each driver is
active when its input i's high.

8

TEl

Injector test output; an open-collector output used
to monitor injector operation. This output b
inactive until the injector current reaches the peak
value. It remains active during the hold phase.

12,14,16
18,20,22

SENS1 - SENS2

Current sensing feed bach inputs for the six drivers.

13,15, 17
19,21,23

OUT1-0UT6

Outputs for power darlington driving.

ELECTRICAL CHARACTERISTICS (Vs = 5V; T J = 25°C, unless otherwise specified)
Parameter
Vs

Supply Voltage

Test Conditions

Min.

Typ.

Max.

Unit

4.75

5

5.25

V

Is

Supply Current

V IH

Input High Voltage

V IL

Input Low Voltage

'IH

Input High Current

V IH = 2.5V

IlL

Input Low Cu rrent

V IL = 0.4V

18

'0

Output Current

Va = 1.4V

36

50

mA

100

150

nA

I;

Input Current at pin 2

BV CEO

Collector emitter output voltage

RI

Input Resistance
(pin 1,3,4,5,7,9,10)

~

Peak to holding current ratio

15
2.5

mA
Vs
0.8

Ic = 10p.A

p.A

10

5.7

709

V
p.A

120

V

Kn

22

Ih

V

6

6.3

CIRCUIT OPERATION (continued)
Fig. 2 - Timing
CUTOFF

5-8199

Fig. 3 - Injector test timing

TEl

iLI
fi-t

l

I
I

j

5EN5

Ih

I
I

I
I
I

J

,
I

L

j
I

IN

-'

L
NORM

J

L

L J
OPEN

C.C.
5-8191

711

;/,,', \

'
'<. '< :'

,<,;,

ADVANCE DATA

LOW SATURATION DRIVER
•

LOW SATURATION VOLTAGE

No external components are required because
the output recirculation clamping zener is in·
cluded in the chip. This zener can withstand an
initial current of 550mA going down through
an 80mH and 25&1 load.

•

TTL COMPATIBLE INPUT

•

WIDE SUPPLY VOLTAGE

•

NO EXTERNAL COMPONENTS

•

INTERNAL RECIRCULATION PATH FOR
FAST DECAY OF INDUCTIVE LOAD
CURRENT

•

SHORT CIRCUIT PROTECTION

•

THERMALSHUTDOWN

•

LOAD DUMP AND REVERSE BATTERY
PROTECTION

•

FAILSAFE OPERATION: OUTPUT IS OFF
IF THE LOGIC INPUT IS LEFT OPEN

Other safety features of the device include
thermal shutdown, short circuit protection, a
supply voltage range of 4.5 - 24V and a shut
off condition of the output if the logic input
(pin 5) is left open.
ON and OFF delay times of 25JIs max in any
output status, including recirculating situation,
allows PWM use of L9350.

The L9350 is a monolithic integrated circuit
designed to drive grounded resistive, inductive
or mixed loads from the power supply positive
side. Very low stand-by current (1 OOJIA typ.)
and internally implemented protections against
load dump and reverse voltages make the device
very useful in automotive applications.

Pentawatt

ORDERING NUMBER: L9350

BLOCK DIAGRAM
SUPPLY

SUBSTRATE

INPUT

3

5

._ ..

~COMPARATOR ~u

_ _._

4

--------------~l:GND
s- '3253

This is advanced information on a new product row in development or undergoing evaluation. Details are subject to change without notice.

713

12/86

ELECTRICAL CHARACTERISTICS (Vs
Parameter

Vs

Operating supply voltage

VAH

I nput voltage High

Test Conditions

Vs

<

Input voltage Low

Ii

I nput current

O.S

II

Output leakage current

Vo = OV
VI < O.SV

V sat

Output saturation voltage

10

IQ

Quiescent current

Negative output zener
voltage

ton

Turn ON delay

Turn OFF delay

tde

Turn ON delay while
output is clamped

Max.

Unit

24

V

V

24V

<

Vi

<

20

5.5V

50

p.A

1

mA

Vs

= 24V

= 150mA

Vs

= 4.5V

0.3

0.6

V

10

= 400mA

Vs

= 14.4V

0.5

0.7

V

10

= 550mA

Vs

= 14.4V

0.7

1

V

1.5

A

VI> 2V

50

SO

mA

<

100

200

p.A

-30

-24

V

20

p.s

25

p.s

20

p.s

O.SV stand-by condition

L = SOmH
RL = 25n
on V I transition from "1" to "0"

Only resistive load RL
(Fig. 2)

tott

Typ.

O.S

VI
V zo

Min.

2

<

VAL

Output short circuit
current

unless otherwise specified)

4.5

4.5

Ise

= 14.4V. lj = +25°C.

= 25n

L = SOmH
RL = 25
any time during clamping internal
(Fig. 3)

For V s > 26 the device is not operating.

715

-36

Fig. 4 - 5V self-oscillating SMPS

VB- 6 TO 24V

Fig. 5 - DC stepper motor driver

5V

OSC 2 18
01
REF1
14
16
REF2 17
02
1.0 13
4

14
8
13
7
12

0

tn

1.0
~

11
510 15
6

Ii

..-I

C/)

Z

ru

C/)

Z

l.U

l.U

C/)

C/)

5 - 9557

717

PRELIMINARY DATA

LED DISPLAY DRIVERS
•

silicon gate technology. They are available in
40-pin dual in-line plastic packages.

M5450 34 OUTPUTS/15mA SINK

•

M5451 35 OUTPUTS/15mA SINK

•

CURRENT GENERATOR OUTPUTS (NO
EXTERNAL RESISTORS REQUIRED)

A single pin controls the LED display brightness
by setting a reference current through a variable
resistor connected to VDD or to a separate supply of 13.2V maximum.

• CONTINUOUS BRIGHTNESS CONTROL

The M5450 and M5451 are improved pin-to-pin
replacements of the NS MM 5450 and MM 5451.

• SERIAL DATA INPUT
•

ENABLE (ON M5450)

• WIDE SUPPLY VOLTAGE OPERATION
•

TTL COMPATIBILITY

Application examples:
•

MICROPROCESSOR DISPLAYS

•

INDUSTRIAL CONTROL INDICATOR

•

RELAY DRIVER

•

INSTRUMENTATION READOUTS

DIP-40 Plastic

ORDERIN.G NUMBERS: M5450 B7
M5451 B7

The M5450 and M5451 are monolithic MOS
integrated circuits produced with an N-channel

ABSOLUTE MAXIMUM RATINGS
V DD
VI
VO(off)
10
Ptot

Supply voltage
Input voltage
Off state output voltage
Output sink current
Total package power dissipation

Tj
Top
T 519

Junction temperature
Operating temperature range
Storage temperature range

-0.3 to 15
-0.3 to 15
15
40
at 25°C
at 85°C
150
-25 to 85
-65 to 150

V
V
V
mA
1W
560mW
°C
°C
°C

Stresses above those listed under" Absolute Maximum Ratings" may causes permanent damage to the device. This is a
stress rating only and functional operation of the device at these of any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

719

12/86

STATIC ELECTRICAL CHARACTERISTICS (T amb within operating range, Voo= 4.75V to
13.2V, V 55= OV, unless otherwise specified)
Parameter

Voo

Supply Voltage

100

Supply Current

VI

I nput Voltage
Logical "0" Level
Logical" 1" Level

Is

Brightness Input Current
(note 2)

Vs

Brightness Input Voltage
(pin 19)

VO(off)

Off State Out. Voltage

10

Out. Sink Current (note 3)
Segment OFF
Segment ON

fClock

Input Clock Frequency

10

Output Matching (note 1)

Test conditions

Min.

Typ.

Max.

Unit

13.2

V

7

mA

-0.3
2.2
Voo-2

0.8
Voo
Voo

V
V
V

0

0.75

mA

3

4.3

V

13.2

V

10

JlA

10
4
25

JlA
mA
mA

0.5

MHz

± 20

%

4.75
Voo= 13.2V

± 10 JlA input bias
4.75 .; V DO .; 5.25
Voo > 5.25

Input current = 750 JlA

Vo = 3V
Vo = lV (note 4)
Brightness In. = 0 JlA
Brightness In. = 100 JlA
Brightness In. = 750 JlA

0
2
12
0

2.7
15

Notes: 1. Output matching is calculated as the percent variation from 'MAX + IM IN 12.
2. With a fixed resistor on the brightness input some variation in brightness will occur from one device to
another.
'
3. Absolute maximum for each output should be limited to 40 mA.
4. The Vo voltage should be regulated by the user. See figures 5 and 6 for allowable Vo versus 10 operation.

FUNCTIONAL DESCRIPTION
Both the M5450 and the M5451 are specifically designed to operate 4 or 5"digit alphanumeric displays
with minimal interface with the display and the data source. Serial data transfer from the data source to
the display driver is accomplished with 2 signals, serial data and clock. Using a format of a leading "1"
followed by the 35 data bits allows data transfer without an additional load signal. The 35 data bits are
latched after the 36th bit is complete, thus· providing non-multiplexed, direct drive to the display.
Outputs change only if the serial data bits differ from the previous time.
Display brightness is determined by control of the output current LED displays.
A 1nF capacitor should be connected to brightness control, pin 19, to prevent possible oscillations.
A block diagram is shown in figure 1. For the M5450 a DATA ENABLE is used instead of the 35th
output. The DATA ENABLE input is a metal option for the M5450.
721

Fig. 3
CLOCK

DATA
300n5 MIN

DATA ENA8I.E
lOOns MIN

Fig.6

Fig. 5

Fig. 4
F'tot

(Vo)

(W)

Tamb=SS·C
Tj',lSO-C(MAX)

.8
2.4

.

20SEGM.

'"

1.8

• 4

'.2

l"

M.

'!.

JOSEGM.

.,

0.2

:5
20

40

60

lambC"C}

.0

16

20

24ILED (mA,)

rt+
o

4

TYPICAL APPLICATIONS
Basic electronically tuned Radio or TV system
LED DISPLAY

M5450
DISPLAY
DRIVER

PLL
SYNTHESIZER

5_5100

STATION
DETECT. ETC.

723

8

U

~

20

~

~

nu~~~

M5450
M5451
In this application R must be chosen taking into account the worst operating conditions.
R is determined by the maximum number of segments activated

R=

Vc - Vo

N

MAX

-Va

MIN

MAX' 10

The worst case condition for the device is when roughly half of the maximum number of segments
are activated.
It must be checked that the total power dissipation does not exceed the absolute maximum ratings
of the device.
In critical cases more resistors can be used in conjunction with groups of segments.
In this case the current variation in the single resistor is reduced and Ptot limited.

b)

5-5788

In this configuration the drop on the serial connected diodes is quite stable if the diodes are properly
chosen.
The total power dissipation of the IC depends, in a first approximation, only on the number of
segments activated.

c)

In this configuration V auT + Vo is constant. The total power dissipation of the IC depends only on
the number of segments activated.
725

aB.
LED DISPLAY DRIVER
•

3 DIGIT LED DRIVER (23 SEGMENTS)

•

CURRENT GENERATOR OUTPUTS (NO
RESISTORS REQUIRED)

•

CONTINUOUS

BRIGHTNESS

technology. It utilizes the M5451 die packaged in
a 28-pin plastic package making it ideal for a
3% digit dispaly. A single pin controls the LED
dispaly brightness by setting a reference current
through a variable resistor connected either to
Voo or to a separate supply of 13.2V maximum.

CONTROL

• SERIAL DATA INPUT
•

The M5480 is an improved pin-to-pin replacement of the NS MM 5480.

NO LOAD SIGNAL REQUIRED
SUPPLY VOLTAGE

•

WIDE

•

TTL COMPATIBILITY

OPERATION

Applications examples:
•

MICROPROCESSOR DISPALYS

•

INDUSTRIAL CONTROL INDICATION

•

RELAY DRIVER

•

INSTRUMENTATION READOUTS

DIP-28 Plastic

ORDERING NUMBER: M5480 B7

The M5480 is a monolithic MOS integrated
circuit produced with a N-channel silicon gate

ABSOLUTE MAXIMUM RATINGS
Voo
VI
Vo (off)
10
Ptot

Supply voltage
I nput voltage
Off state output voltage
Output sink current
Total package power dissipation

Tj
Top
Tstg

Junction temperature
Operating temperature range
Storage temperature range

-0.3 to
-0.3 to

15
15
15
40
at 25°C
at 85°C
150
-25 to 85
-65 to 150

V
V
V
rnA
940mW
490mW
°C
°C
°C

Stresses above those listed under" Absolute Maximum Ratings" may causes permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

727

12/86

STATIC ELECTRICAL CHARACTERISTICS (T amb within operating range, Voo= 4.75V to
13.2V, Vss= OV, unless otherwise specified)
Parameter
Voo

Supply Voltage

100

Supply Current

VI

Input Voltages
Logical "0" Level
Logical "1" Level

IB

Brightness Input Current
(note 2)

VB

Brightness Input
Voltage (pin 13)

VO(Off)

Off State Output Voltage

10

Output Sink Current
(note 3)
Segment OFF
Segment ON

fclock

Input Clock Frequency

10

Output Match ing (note 1)

Notes:

Test conditions

Min.

Typ.

Max.

Unit

13.2

V

7

mA

2.2
Voo-2

0.8
Voo
Voo

V
V
V

a

0.75

mA

3

4.3

V

13.2

V

10

}.LA

10
4
25

}.LA
mA
mA

0.5

MHz

± 20

%

4.75
Voo= 13.2V

± 10}.LA Input Bias
4.75'; V 00 .; 5.25
Voo > 5.25

I nput Current = 750 }.LA

Vo = 3V
Vo = lV (note 4)
Brightness In. = O}.LA
Brightness In. = 100}.LA
Brightness In. = 750}.LA

-0.3

a
2
12

a

2.7
15

1. Output matching is calculated as the percent variatiqn from I MAX + 1M IN12.
2. With a fixed resistor on the brightness input some variation in brightness will occur from one device to
another.
3. Absolute maximum for each output should be limited to 40 mAo
4. The Vo voltage should be regulated by the user.

FUNCTIONAL DESCRIPTION
The M5480 is specifically designed to operate 3% digit alphanumeric displays with minimal interface
with the display and the {lata source. Serial data transfer from the data source to the tlisplay driver is ac·
complished with 2 signals, serial data and clock. Using a format of a leading "1" followed by the 35 data
bits allows data transfer without an additional load signal. The 35 data bits are latched after the 36th bit
is complete, thus provid ing non-mu Itiplexed, direct drive to the display.
Outputs change only if the serial data bits differ from the previous time.
Display brightness is determined by control of the output current for LED displays. A 1 nF capacitor
should be connected to brightness control, pin 13, to prevent possible oscillations.
A block diagram is shown in figure 1. The output current is typically 20 times greater than the current
into pin 13, which is set by an external variable resistor.
There is an internal limiting resistor of 400n nominal value.
729

Fig. 4 - Serial Data Bus/Outputs Correspondence

TYPICAL APPLICATION
BASIC 3 1/2 Digit interface.

CLOCK DATA

POWER DISSIPATION OF THE IC
The power dissipation of the IC can be limited using different configurations.
a)

In this application R must be chosen taking into account the worst operating conditions.
R is determined by the maximum number of segments activated.

R=

Vc - V D
N

MAX -

V OUT

MAX·

ID

MIN

The worst case condition for the device is when roughly half of the maximum number of segrnents
are activated.
It must be checked that the total power dissipation does not exceed the absolute maximum ratings
of the dev ice.
I n critical cases more resistors can be used in conjunction with groups of segments.
In this case the current variation in the single resistor is reduced and Ptot limited.
731

lB.
LED DISPLAY DRIVER
•

2 DIGIT LED DRIVER (14 SEGMENTS)

•

CURRENT GENERATOR OUTPUTS (NO
RESISTOR REQUIRED)

•

CONTINUOUS

•

SERIAL DATA INPUT

•

DATA ENABLE

• WIDE

BRIGHTNESS

SUPPLY VOLTAGE

technology. It utilizes the M5450 die packaged
in a 20-pin plastic package copper frame, making
it ideal for a 2-digit display. A single pin controls
the LED display brightness by setting a reference
current through a variable resistor connected
either to Voo or to a separate supply of 13.2V
maximum.

CONTROL

The M5481 is an improved pin-to-pin replacement of the NS MM 5481.

OPERATION

TTL COMPATIBILITY

•

Application examples:
•

MICROPROCESSOR DISPLAYS

•

INDUSTRIAL CONTROL INDICATOR

•

RELAY DRIVER

•

INSTRUMENTATION READOUTS

DIP-20 Plastic
(0.25)

The M5481 is a monolithic MOS integrated
circuit produced with a N-channel silicon gate

ORDERING NUMBER: M5481 B7

ABSOLUTE MAXIMUM RATINGS

Ptot

Supply voltage
Input vo Itage
Off state output voltage
Output sink current
Total package power dissipation

Tj
Top
T st9

Junction temperature
Operating temperature range
Storage temperature range

Voo
VI
VO(Off)

10

-0.3 to
-0.3 to

15
V
15
V
V
15
40
rnA
at 25°C
1.5W
at 85°C 800mW
150
°C
-25 to 85
°C
-65 to 150
°C

Stresses above those listed under "Absolute Maximum Ratings" may causes permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

733

12/86

STATIC ELECTRICAL CHARACTERISTICS (T amb within operating range, Voo= 4.75V to
13.2V, Vss= OV, unless otherwise specified)
Parameter

Voo

Supply Voltage

100

Supply Current

VI

Input Voltages
Logical "0" Level
Logical ·'1" Level

IB

Brightness I nput Current
(note 2)

VB

Brightness Input
Voltage (pin 9)

VO(off)

Off State Output Voltage

10

Output Sink Current
(note 3)
Segment OFF
Segment ON

fClock

Input Clock Frequency

10

Output Matching (note 1)

Notes:

Test cond ition.

Min.

Typ.

Max.

Unit

13.2

V

7

mA

-0.3
2.2
Voo-2

0.8
Voo
Voo

V
V
V

0

0.75

mA

4.3

V

13.2

V

10

IJA

10
4
25

IJA
mA
mA

0.5

MHz

± 20

%

4.75
Voo= 13.2V
± lOIJA Input Bias
4.75';;; Voo';;; 5.25
Voo > 5.25

I nput Current = 750 IJA

Vo = 3V
V 0 = 1V (note 4)
Brightness In. = a IJA
Brightness In. = 100 IJA
Brightness In. ~ 750 IJA

3

a
2
12

a

2.7
15

1. Output matching is calculates as the percent variation from IMAX + 1M I N/2.
2. With a fixed resistor on the brightness input some variation in brightness will" occur from one device to

another.
3. Absolute maximum for each output should be limited to 40 mA ..
4. The Vo voltage should be regulated by the user.

FUNCTIONAL DESCRIPTION
The M5481 uses the M5450 die which is packaged to operate 2-digit alphanumeric displays with mini·
mal interface with the display and the data source. Serial data transfer from the data. source to the
display driver is accomplished with 2 signals, serial data and clock. Using a format of a leading" 1"
followed by the 35 data bits allows data transfer without an additional load signal.
The 35 data bits are latched after the 36th bit is complete, tHus providing non·-multiplexed, direct drive
to the display. Outputs change only if the serial data bits differ from the previous time. Display brightness is determined by control of the output current for LED displays. A 1 nF capacitor should be
connected to brightness control, pin 9, to prevent possible oscillations.
A block diagram is shown in figure 1. The output current is typically 20 times greater than the current
into pin 9, which is set by an external variable resistor.
These is an internal limiting resistor of 400n nominal value.
735

Fig. 4 - Serial Data Bus/Outputs Correspondence
~"""","f-+-+--+-+-+--+--t-f-t

! f,

1

H, j'" '4 :i· I;,j'1 101 !l 1HI) T)-o·l " '. 4 : j:, '; i S;;;:RTl
-+-+-+--t·-f-t-··19 ..18T;q;
j . _.
I·
I,
, 1 . . , . · · .J
x

X_J

~.-.L ~ I 7

6

5;

x

1x I x i x ~

4

I~

t ')

I I 1X •

x ;

X , X

1.

~r~_~

TYPICAL APPLICATION
BASIC electronically tuned TV system
LED DISPLAY

1;:1

11-

POWER DISSIPATION OF THE IC
The power dissipation of the IC can be limited using different configurations.

,vc
a)
R
~-~-------

VOUT

_.

r
5_5781

In this application R must be chosen taking into account the worst operating conditions.
R is determined by the maximum number of segments activated.
R=

Vc - V D MAX - Vo
N MAX' ID

MIN

-=--~.::.:..;;=-=-~=-.::.=.;'--

The worst case condition for the device is when roughly half of the maximum number of segments
are activated.
It must be checked that the total power dissipation does not exceed the absolute maximum ratings
of the device.
In critical cases more resistors can be used in conjunction with groups of segments. In this case the
current variation in the single resistor is reduced and Ptot limited.
737

II.

:-

LED DISPLAY DRIVER
•

2 DIGIT LED DRIVER (15 SEGMENTS)

•

CURRENT GENERATOR OUTPUTS (NO
RESISTOR REQUIRED)

•

CONTINUOUS

•

SERIAL DATA INPUT

• WIDE

BRIGHTNESS

SUPPLY

VOLTAGE

technology. It utilizes the M5450 die packaged
in a 20-pin plastic package copper frame, making
it ideal for a 2-digit display. A single pin controls
the LED display brightness by setting a reference
current through a variable resistor connected
either to Voo or to a separate supply of 13.2V
maximum.

CONTROL
OPERATION

• TTL COMPATIBILITY

Application examples:
•

MICROPROCESSOR DISPLAYS

•

INDUSTRIAL CONTROL INDICATOR

•

RELAY DRIVER

•

INSTRUMENTATION READOUTS

DIP-20 Plastic
(0.25)
ORDERING NUMBER: M5482 B7

The M5482 is a monolithic MOS integrated
circuit produced with an N-channel silicon gate

ABSOLUTE MAXIMUM RATINGS
V OD
V,
Vo (off)
Ptot

Supply voltage
I nput voltage
Off state output voltage
Output sink current
Total package power dissipation

Tj
Top
T stg

Junction temperature
Operating temperature range
Storage temperature range

10

V
15
V
15
V
15
40
mA
at 25°C
1.5W
at 85°C 800mW
150
°C
-25 to 85
°C
-65 to 150
°C

-0.3 to
-0.3 to

Stresses above those listed under "Absolute Maximum Ratings" may causes permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

739

12/86

STATIC ELECTRICAL CHARACTERISTICS (T amb within operating range, Voo= 4.75V to
13.2V, Vss= OV, unless otherwise specified)
Parameter
Voo

Supply Voltage

100

Supply Current

VI

Input Voltages
Logical "0" Level
Logical "1" Level

Is

Brightness Input Current
(note 2)

Vs

Brightness Input
Voltage (pin 9)

VO(off)

Off State Output Voltage

10

Output Sink Current
(note 3)
Segment OFF
Segment ON

fclock

Input Clock Frequency

10

Output Match ing (note 1)

Notes:

Test conditions

Max.

Unit

13.2

V

7

mA

-0.3
2.2
Voo-2

0.8
Voo
Voo

V
V
V

0

0.75

mA

4.3

V

13.2

V

Min.

Typ.

4.75
Voo= 13.2V
± 10 "A Input Bias
4.75';; Voo';; 5.25
Voo > 5".25

I nput Current = 750 "A

Vo = 3V
Vo = 1V (note 4)
Brightness In . = 0 "A
Brightness In. = 100 "A
Brightness In. = 750 "A

3

0
2
12
0

2.7
15

10

"A

10
4
25

"A
mA
rnA

0.5

MHz

±

20

%

1. Output matching is calculated as the percent variation from IMAX + I MIN /2.
2. With a fixed resistor on the brightness input some variation in brightness will occur from one device to
another.
3. Absolute maximum for each output should be limited to 40 rnA.
4. The Vo voltage should be regulated by the user.

FUNCTIONAL DESCRIPTION
The M5482 uses the M5451 die which is packaged to operate 2-digit alphanumeric displays with mini·
mal interface with the display and the data source. Serial data transfer from the data source to the
display driver is accomplished with 2 signals, serial data and clock. Using a format of a leading "1"
followed by the 35 data bits allows data transfer without an additional load signal.
The 35 data bits are latched after the 36th bit is complete, thus providing non··muitiplexed, direct drive
to the display. Outputs change only if the serial data bits differ from the previous time. Display bright·
ness is determined by control of the output current for LED displays. A 1 riF capacitor should be
connected to brightness control, pin 9, to prevent possible oscillations.

A block diagram is shown in figure 1. The output current is typically 20 times greater than the current
into pin 9, which is set by an external variable resistor.
There is an internal limiting resistor of 400Q nominal value.
741

Fig. 4 - Serial Data Bus/Outputs Correspondence

TYPICAL APPLICATION
BASIC electronically tuned TV system

LED DISPLAY

I -,

Ie

KEYBOARD

POWER DISSIPATION OF THE IC
The power dissipation of the IC can be limited using different configurations.
•vc
a)

,
Your

I
S_S787

In this application R must be chosen taking into account the worst operating conditions.
R is determined by the maximum number of segments activated.
R=

VC-VOMAX-VOMIN

-"'--":::"':~""'--~:'::':':'':'-

N MAX· 10
The worst case condition for the device is when roughly half of the maximum number of segments
are activated.
It must be checked that the total power dissipation does not exceed the absolute maximum ratings
of the device.
In critical cases more resistors can be used in conjunction with groups of segments. In this case the
current variation in the single resistor is reduced and Ptot limited.
743

II.
RS232C QUAD LINE DRIVER
•

CURRENT LIMITED OUTPUT ± 10mA TYP.

•

POWER-OFF SOURCE IMPEDANCE 300n
MIN.

•

SIMPLE SLEW RATE CONTROL WITH
EXTERNAL CAPACITOR

•

FLEXIBLE OPERATING SUPPLY RANGE

•

INPUTS ARE TTL AND jJ.P COMPATIBLE

formance with the specifications of E IA Standard
No. RS232C.

DIP-14 Plastic
and Ceramic

The MC1488 is a monolithic quad line driver
designed to interface data terminal equipment
with data communications equipment in con-

SO-14J

ORDERING NUMBER:MC1488P (Plastic DIP)
MC1488L (Ceramic DIP)
MC1488D (SO-14)

ABSOLUTE MAXIMUM RATINGS
Vs
VEE
VIR
Vo
T amb
Tst!!

Power supply voltage
Power supply voltage
Input voltage range
Output signal voltage
Operating ambient temperature
Storage temperature range

15
-15
-15";;V IR ";;7
± 15
o to 75
-65 to 150

V
V
V
V

°c
°c

Typical Application: RS232C data transmission
+'1,;

TTL

TTL

pP

pP

or

or

P-=----'
,.---,---.._/

RS-232C '-------=-1
CABLEAND
CONNECTOR

5-1776

745

12/86

ELECTRICAL CHARACTERISTICS (continued)
Parameter

Is

Positive supply current
(R,=~)

lEE

Negative supply current
(RL=~)

Pc

Power consumption

Test Conditions

Min.

Typ.

Max.

Unit Fig.

V,H = 1.SV
V,L = 0.8V
V,H = 1.SV
V,L = 0.8V
V,H = 1.SV
V,L =0.8V

Vs=SV
Vs= SV
Vs = 12V
Vs = 12V
Vs=15V
Vs = 15V

15
4.5
1S
5.5

20
6
25
7
34
12

mA

5

V,H = 1.SV
V,L = 0.8V
V,H = 1.SV
V,L = 0.8V
V,H = 1.SV
V ,L = 0.8V

VEE = -SV
VEE =-SV
VEE = -12V
VEE = -12V
VEE = -15V
VEE = -15V

-13

-17
-15
-23
-15
-34
-2.5

mA
/lA
mA
/lA
mA
mA

5

Vs=SV
Vs = 12V

VEE = -SV
VEE = -12V

333
576

mW

SWITCHING CHARACTERISTICS (V s

=± 9 ±

-18

1% V, VEE = -9 ±1% V, Tamb = 25°C)

tpLH

Propagation delay time

Z, = 3Kn and 15pF

275

350

ns

6

tTHL

Fall time

Z, = 3Kn and 15pF

45

75

ns

6

tpHL

Propagation delay time

Z, = 3Kn and 15pF

110

175

ns

6

tTLH

Rise time

Z, = 3Kn and 15pF

55

100

ns

6

• Maximum package power dissipation may be exceeded if all outputs are shorted simultaneously

TEST CIRCUITS
Fig. 1 - I nput current

Fig. 2 - Output voltage

747

Fig. 3 - Output short-circuit
current

APPLICATIONS INFORMATION
The Electronic Industries Association (EIA) has
released the RS232C specification detailing the
requirements for the interface between data
processing equipment. This standard specifies not
only the number and type of interface leads, but
also the voltage levels to be used. The MC1488
quad driver and its companion circuit, the
MC1489 quad receiver, provide a complete interface system between DTL or TTL logic levels
and the RS232C defined levels. The RS232C
requirements as applied to drivers are discussed
herein.

The interface driver is also required to withstand
an accidental short to any other conductor in an
interconnecting cable. The worst possible signal on
any conductor would be another driver using a
plus or minus l5V, 500mA source. The MC1488
is designed to indefinitely withstand such a short
to all four outputs in a package as long as the
power-supply voltages are greater than 9.0V (Le.,
Vs ;;. 9.0V; VEE .;;; -9.0V). In some powersupply designs, a loss of system power causes a
low impedance on the power-supply outputs.
When this occurs, a low impedance to ground
would exist at the power inputs to the MC1488
effectively shorting the 3000, output resistor to
ground. If all four outputs were then shorted to
plus or minus 15V, the power dissipation in these
resistors would be excessive. Therefore, if the
system is designed to permit low impedances to
ground at the power-supplies of the drivers, a
diode should be placed in each power-supply
lead to prevent over-heating in this fault condition. These two diodes, as shown in Figure 13,
could be used to decouple all the driver packages
in a system. (These same diodes will allow the
MC1488 to withstand momentary shorts to the
± 15V limits specified in the earlier Standard
RS232B). The addition of the diodes also permits
the MC1488 to withstand faults with power-supplies of less than the 9.0V stated above.

The required driver voltages are defined as between 5 and l5V in magnitude and are positive
for a logic "0" and negative for a logic" 1". These
voltages are so defined when the drivers are
terminated with a 3000 to 70000, resistor. The
MC1488 meets this voltage requirement by converting a DTL/TTL logic level into RS232C
levels with one stage of inversion.
The RS232C specification further requires that
during transitions, the driver output slew rate
must not exceed 30V per J.1S. The inherent slew
rate of the MC1488 is much too fast for this
requirement. The current limited output of the
device can be used to control this slew rate by
connecting a capacitor to each driver output. The
required capacitor can be easily determined by
using the relationship C = los x b,.T/b,.V from
which Figure 12 is derived. Accordingly, a 330pF
capacitor on each output will guarantee a worst
case slew rate of 30V per J.1S.

The maximum short-circuit current allowable
under fault conditions is more than guaranteed
by the previously mentioned 10mA output current limiting.

Fig. 12 - Slew rate vs. capacitance for Isc = 10mA
SR
(V)

Fig. 13 - Power supply protection to meet
power-off fault conditions

-

.
,

v•

10',
·~30YJlJsl

10

I

,

I
I ~333PF
,

10

,.

1

10

2

•• I

J

10

t

,

••

C (pF)

749

L...

II.
QUAD LINE RECEIVERS
•

INPUT RESISTANCE - 3.0K to 7.0Kn

•

INPUT SIGNAL RANGE - ± 30V

•

INPUT THRESHOLD
BUILT-IN

•

RESPONSE CONTROL:
a) LOGIC THRESHOLD SHIFTING
b) INPUT NOISE FILTERING

with data communications equipment in conformance with the specifications of EIAStandard
No. RS-232C.

HYSTERESIS

SO-14J

DIP-14 Plastic
and Ceramic

The MC1489 monolithic quad line receivers are
designed to interface data therminal equipment

ABSOLUTE MAXIMUM RATINGS

v5
VI
IOL
Ptot
Tamb
Tst9

Power supply voltage
Input voltage range
Output load current
Power dissipation
Operating ambient temperature
Storage temperature range

10
± 30
20
1
o to 75
-65 to 150

V
V
mA

W

°c
°c

ORDERING NUMBER: MC1489L, MC1489AL (DIP-14 Ceramic)
MC1489P, MC1489AP (DIP-14 Plastic)
MC1489D, MC1489AD (SO-14)
Typical Application: RS232C data transmission

TTL

TTL

or
MP

or
MP

S_7776

751

12/86

TEST CI RCUITS
Fig. 1 - Switching response

Fig. 2 - Response control node

Fig. 3 - Input current

.s.

."

V,

Ie
tTLHancltTHL
m"5ur~

RESPONSE NODE

V, 0------1

"

'1'0

10"10-90"1.

v,

C, capacitor is for noise filtering
R, resistor is for threshold shifting

Fig. 4 - Output short-circuit
current

Fig. 5 - Output voltage and input
threshold voltage

j

v,HLl
OPENO

'V,

Fig. 6 - Power supply
current
",

."

\/lLH

~
i

~

s.

I,

I,

"

\/t

VOH

Ii

"

"

TYPICAL CHARACTERISTICS (V s = 5V,Tamb = 25°C unless otherwise specified)
Fig. 7 - Input current

Fig. 8 - MC1489 input thre·
shold voltage adjustament

,.'"

I,

I
I
I /

ImA

Y
V

-2

-6

V
I

-8

/1
I-

Rr

SKn

I

V,h

~

.s.

v"Z

/

RT
13Kn
V,h

t--."

~
--

V,

I

IV)

·T

RT

l1Kn

~Vtt1

J:.

V,h

_sv

I

i

V1LH -VIHL

,

_I.
- 25 .20 .15 _10 -5

~w

•

1-'-

Fig. 9 - MC1489A inputthreshold voltage adjustment

0

5

10

IS

vi (v)

-3

_2

_1

"V;(V)

753

-3

-2

-H=t=H-I
4Vl(V}

APPLICATION INFORMATION (continued)
The response node may also be used as the
receiver input as long as the designer realizes that
he may not drive this node with a low impedance
source to a voltage greater than one diode above

gorund or less than one diode below ground. This
feature is demonstrated in Figure 11 where two
receivers are slaved to the same line that must
still meet the RS-232C impedance requirement.

Fig. 12 - Typical Turn-on
threshold vs. capacitance
from response control pin
toGND

Fig. 13 - Typical Turn-on
threshold vs. capacitance
from response control pin
to GND
834
&_~

v.

'v,

MC1489A

\ \ \
12pF\ 100PF\ \300PF\500 PF

1\\ \

I\.

"~ ~ ~

"

."'"

'00

10

Wens)

.00

'000

Fig. 14 - Typical paralleling of two MC1489/A receivers to meet RS-232C

.v.

,.---------------RESPONSE
CONTROL PIN
IN

8KA

+v. o-+--------~

I""
RESPONSE
CONTROl PIN

755

------,

WIns)

lIB.

ADVANCE DATA

STEPPER MOTOR DRIVER
The MC3479C is designed to drive a two-phase
stepper motor in the bipolar mode. The circuit
consists of four input selections a logic decoding/
sequencing section two driver stages for the
motor coils and an output to indicate the Phase
A drive state.

• SINGLE SUPPLY OPERATION +7.2V TO
+16.5V
• 350mA/COIL ORIVE CAPABILITY
• CLAMP DIOOES PROVIDED FOR BACKEMF SUPPRESSION
• SELECTABLE CW/CCW AND FULL/HALF
STEP OPERATION
• SELECTABLE HIGH/LOW OUTPUT
PEDANCE (HALF STEP MODE)

IM-

• TTL/CMOS COMPATIBLE INPUTS
•

Powerdip
12 + 2 + 2

INPUT HYSTERESIS: 250mV TYP.

• PHASE LOGIC CAN BE INITIALIZED TO
PHASE A
• PHASE A OUTPUT DRIVE STATE INDICATION

ORDERING NUMBER: MC3479C

BLOCK DIAGRAM

Vs

CLK

L2
VD

L3
FULl/HALF
STEP

L4

OIC
5-918111

BIAS/SET

GND

INPUT TRUTH TABLE
INPUT LOW

INPUT HIGH

CW/CCW

CW

CCW

F/HS

Full Step

Half Step

OIC

High Z

low Z

ClK

Positive Edge Triggered

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

757

12/86

PIN DESCRIPTION
NAME

SYMBOL

PINS

OEseR IPTION

POWER SUPPLY

Vs

16

Power supply pin for both the logic circuit
and the motor coil current. Voltage range is
7.2V to 16V.

GROUND

GND

4-5-12-13

Ground pins for the logic circuit and the motor
coil current. The physical configuration of the
pins dissipating heat from within the package.

CLAMP DIODE

Vo

DRIVER OUTPUTS

L1, L2
L3, L4

2-3
14-15

High current outputs for 'the motor coils. L1
and L2 are connected to one coil and L3 and
L4 to the other coil.

BIAS/SET

S/S

6

This pins is typically 0,7V below Vs. The current out of this pin (through a resistor to
ground) determines the maximum output sink
current, If the pin is opened (las < 5.0J.(A) the
outputs assume a high impedance condition
while the internal logic presets to a Phase A
condition.

CLOCK

CK

7

The positive edge of the clock input switches
the outputs to the next position. This input
has no effect if pin 6 is open.

FULl/HALF STEP

F/HS

9

When low (logic 0) each clock pulse will cause
the motor to rotate one full step.
When high, each clock pulse will cause the
motor to rotate one-half step.
(See fig. 4 for sequence).

CLOCKWISE
COUNTERCLOCKWISE

CW/CCW

10

This input allows reversing the rotation of
the rotation of the motor.
(See fig. 4 for sequence).

OUT IMPEDANCE
CONTROL

OIC

8

This input is relevant only in the half step
mode (pin 9 > 2V). When low (logic 0) the
two driver out of the non-energized coil will be
in a high impedance condition. When high the
same driver outputs will be at a low impedance
reference to Vs.
(See fig. 4).

PHASE A

Ph A

11

This outputs indicates (when low) that the
driver outputs are in the phase A condition
(L1 = L3 = V OHO ; L2 = L4 = VOLO)

This pin is used to protect the outputs where
large voltage spikes may occur as the motor
coils are switched. Typically a diode is connected between this pin and pin 16. See fig. 5.

759

AC SWITCHING CHARACTERISTICS (Tamb = 25°C; V M = 12V)
Parameter

Test Conditions

Min.

Typ.

0

Max.

Unit

30

KHz

ICK

Clock frequency

PWCKH

Clock pulse width

HIGH

10

IlS

PWCKl

Clock pulse width

LOW

20

IlS

tsu

Set-up time CW/CCW and F/HS

5

IlS

10

tHO

Hold time CW/CCW and -r/HS

tpCD

Propagation delay ClK-to driver out

8

IlS

tpBSD

Propagation delay Bias/set to driver output

1

IlS

tpHLA

Propagation delay ClK-to phase A lOW

12

IlS

tpLHA

Propagation delay CLK-to phase A HIGH

5

IlS

IlS

Fig. 1 - AC test circuit
·12v

lKfi

56Kn

lKfi
lKfi

BiASiSET
C/K

7

OIC

B

lKfi

MC3479C 14F-~=H
lKfi
lKfi

F/HS
13 11
CW/CCW

10

PHASE A
5-9183

Fig. 2 - BIAS/SET TIMING (refer to fig. 1)

Fig. 3 - CLOCK TIMING (refer to fig. 1)
CIK

VM
BIAS/SET
INPUT

ll-L4
OUTPUTS

F/HS

Ll-L4
OUTPUTS

3V------------__ ~~~~jr--------+_--

1.5V
CWiccw
INPUTS 0 _ _ _ _ _ _ _..../

\.._+-_J

S-9J8t,

i5HASrA
OUTPUTS

S-'"5

761

'-----,.-f---

Fig. 5 - Typical application circuit

r----;!;---+---~ LI r - - - - - -,

I

11

I~OR !

CLOCK
DIGITAL
INPUTS

DIRECTION

10

e:

MC3479C

I
I
I

FITIT/HALF

STEP

I

OUTPUT
IMPEDANCE

I

I

5-91B7

4049

763

II.

PRELIMINARY DATA

STEPPER MOTOR DRIVER
•

FULL STEP - HALF STEP - QUARTER
STEP OPERATING MODE
• BIPOLAR OUTPUT CURRENT UP TO lA
• FROM 10V UP TO 46V MOTOR SUPPLY
VOLTAGE
• LOW SATURATION VOLTAGE WITH INTEGRATED BOOTSTRAP
• BUILT IN FAST PROTECTION DIODES
• EXTERNALLY SELECTABLE CURRENT
LEVEL
• OUTPUT CURRENT LEVEL DIGITALLY
OR ANALOGUE CONTROLLED
• THERMAL PROTECTION WITH SOFT INTERVENTION
The PBL3717A is a monolithic IC which controls
and drives one phase of a bipolar stepper motor
with chopper control of the phase current. Current levels may be selected in three steps by
means of two logic inputs which select one of
three current comparators. When both of these
inputs are high the device is disabled. A separate
logic input controls the direction of current flow.

A monostable, programmed by an external RC
network, sets the current decay time.
The power section is a full H-bridge driver with
four internal clamp diodes for current recirculation. An external connection to the lower emitters is available for the insertion of a sensing
resistor. Two PBL3717As and few external
components form a complete stepper motor
drive subsystem.
The raccomended operating ambient temperature
range is from 0 to 70°C.
The PBL3717A is supplied in a 12 + 2 + 2 lead
Powerdip package.

Powerdip

12+2+ 2
ORDERING NUMBER: PBL3717A

BLOCK DIAGRAM
"

'0

PHASE

OUT B

Ys(B)

-----,

Vsso-J. - - I
REF.

V.CAl OUT A

~~~==~14~

111

I

I
I

I
I
I
I

IK'n.

I

I
1m

I

Ill.

I

I

I
I

I
I

I

I

GNOo-~,,---t..---------+.-Z-_-_-_-_-_-_-_--'_

COMPARATOR
'HP\IT

.......
TIME

765

.1L _ _ _ _ _ _ _

J

SENSE

RESISTOR

12/86

PIN FUNCTIONS
N°

NAME

FUNCTION

OUTPUT B

Output connection (with pin 15). The output stage is a
"H" bridge formed by four transistors and four diodes
suitable for switching applications.

2

PULSE TIME

A parallel RC network connected to this pin sets the
OFF time of the lower power transistors. The pulse
generator is a monostable triggered by the rising edge of
the output of the comparators (toff = 0.69 RTCTI.

3

SUPPLY VOLTAGE B

Supply voltage input for halp output stage.
see also pin 14.

4

GROUND

Ground connection. With pins 5,12 and 13 also conducts
heat from die to printed circuit copper.

5

GROUND

See pin 4.

6

LOGIC SUPPLY

Supply voltage input for logic circuitry.

7

INPUT 1

This pin and pin 9 (INPUT 0) are logic inputs which
select the outputs of the three comparators to set the
current level. Current also depends on the sensing resistor and reference voltage. See truth table.

8

PHASE

This TTL-compatible logic input sets the direction of
current flow through the 10ad.A high level causes current
to flow from OUTPUT A (source)to OUTPUT B (sink).
A schmitt trigger on this input provides good noise
immunity and a delay circuit prevents output stage short
circuits during switching.

9

INPUT 0

See INPUT 1 (pin 71.

10

COMPARATOR INPUT

Input connected to the three comparators. The voltage
across the sense resistor is feedback to this input through
the low pass filter Rc Cc The lower power transistor are disabled when the sense
voltage exceeds the reference voltage of the selected
comparator. When this occurs the current decays for a
time set by RT CT ,toff = 0.69 RT CT.

11

REFERENCE

A voltage applied to this pin sets the reference voltage
of the three comparators, this determining the output
current (also thus depending on Rs and the two inputs
INPUT 0 and INPUT 1).

12

GROUND

See pin 4.

767

Fig.2 - Waveforms with MA regulating (phase = 0)

..
t

v~rr

,

ELECTRICAL CHARACTERISTICS (Refer to the test circuit Vs = 36V, Vss= 5V, Tamb = 25°C
unless otherwise specified)
Parameter

Vs

Supply voltage
(pins 3,14)

Vss

Logic supply voltage
(pin 6)

Iss

Logic supply current
(pin 6)

IR

Referel]ce input current
(pin 111

Test cond itions

VR = 5V

769

Max.

Unit

10

46

V

4.75

5.25

V

7

15

mA

0.75

1

mA

Min.

Typ.

ELECTRICAL CHARACTERISTICS (continued)
Parameter

Test conditions

SINK DIODE-TRANSISTOR PAIR
V sat

Saturation voltage
(pins 1, 15)

1M = 0.5A

1.1

1.35

V

1M = lA

1.6

2.3

V

300

p.A

ILK

Leakage current

Vs = 46V

VF

Diode forward voltage

1M = 0.5A

1.1

1.5

IM= lA

1.4

2

APPLICATION CIRCUIT
Fig 3 - Two phase bipolar stepper motor driver

°ElF-

)Vss

Vs

1

C2:!:0.I}JF

I
II

IIA

6

7

lOA

CI

fTF

14

3

15 MAA

PBL3717A

9

PhA.
82

5

4

GND

Rlp
56
Kll.

:i~~
pF

RT
56
Kll.

ii~20
----<

8
lIB
lOB

Cc.;
820pF

I 12I 13I

5

4

~

lK1t
RS

Ill.

...

RS( Ill.

IMA

-

.fY'Y'\.

(
1MB (
(

EPPER
O~TOlOR

I~
RC

10

16

1~

PBL3717A

7
9

~

pF "

2

16 1 MBA

10

82~~~~

~CT

PhB

12

11I

,-----

FROM
}JPROCESSOR

13

MAB
11

3

6

I

14 15

I

771

5- 6748/1

V

APPLICATION INFORMATIONS
Fig. 3 shows a typical application in which two
PB L3717 A control a two phase bipolar stepper
motor.

both according to the sequence:
AB --+ B --+ AB

The logic inputs 10 and 11 set at three different
levels the amplitude of the current flowing in
the motor winding according to the truth table
of page 2. A high level on the "PHASE" logic
input sets the direction of that current from
output A to output B; a low level from output
B to output A.
It is recommended that unused inputs are tied to
pin 6 (V ss) or pin 4 (GND) as appropriate to
avoid noise problem.
The current levels can be varied continuously by
changing the ref. voltage on pin 11.

Quarter step operation
It is preferable to realize the quarter step operation at full power otherwise the steps will be
of very irregular size.
The extra quarter steps are added to the half
step sequence by putting one coil on half current according to the sequence.
A B --+ ~ B --+ B --+~ B --+ A B --+

2

Control of the motor
The stepper motor can rotate in either directions
according to the sequence of the input signals.
It is possible to obtain a full step, a half step and
a quarter step operation.

2

A!! --+ A etc.
2

Motor selection
As the PB L3717 A provides constant current
drive, with a switching operation, care must be
taken to select stepper motors with low hysteresis
losses to prevent motor over heat.

Full step operation
Both the windings of the stepper motor are
energized all the time with the same current
IMA = 1MB ,
10 and 11 remain fixed at whatever torque value
is requ ired.
Calling A the condition with winding A energized
in one direction and A in the other direction, the
sequence for full step rotation is:

A B --+ A B --+

A--+ AB --+ S --+ AS --+ A etc.

Like full step this can be done at any current
level; the torque is not constant but it is lower
when only one winding is energized
A coil is turned off by setting 10 and 11 both
high.

Programming

A B --+

--+

L-C filter
To reduce EMI and chopping losses in the motor
a low pass L-C filter can be inserted across the
outputs of the PB L3717 A as shown on the
following picture.

A B etc.

For the rotation in the other direction the sequence must be reversed.
In the full step operation the torque is constant
each step.

15

OUTA

L
MOTOR
WINDING
(LM,RM)

C

PBL3717A
OUTB

'j-7742

Half step operation

L -

Power is applied alternately to one winding then
773

10

LM

C~

4 • 10- 10
L

lB.
REGULATING PULSE WIDTH MODULATORS
•

COMPLETE PWM POWER CONTROL
CIRCUITRY

•

UNCOMMITTED OUTPUTS FOR SINGLEENDED OR PUSH PULL APPLICATIONS

•

LOW STANDBY CURRENT .. 8mA TYPICAL

•

OPERATION UP TO 300 KHz

pulse-width modulation techniques. The dual
alternating outputs allows either single-ended or
push-pull applications. Each device includes an
on-chip reference, error amplifier, programmable
oscillator, pulse-steering flip-flop, two uncommitted output transistors, a high-gain comparator,
and current-limiting and shut-down circuitry.

1 % MAXIMUM TEMPERATURE VARIATION OF REFERENCE VOLTAGE
The SG1524, SG2524, and SG3524 incorporate
on a single monolithic chip all the function required for the construction of regulating power supplies inverters or switching regulators. They can
also be used as the control element for high poweroutput applications. The SG1524 family was
designed for switching regulators of either
polarity, transformer-coupled dc-to-dc converters,
transformerless voltage doublers and polarity converter applications employing fixed-frequency,
•

DIP-16 Plastic (0.25)
and Ceramic

SO-16P

ORDERING NUMBERS: SG1524J - SG2524J - SG3524J (Ceramic)
SG2524N - SG3524N (Plastic)
SG2524P - SG3524P (SO-16P)

BLOCK DIAGRAM
YREF

~--~--------.------------+----~

16

12

13

tHy. INPUT
1 Q------r-.....

.. SENSE
4

1..--"I'1----{)

N.I.INPUT
2

-SENSE
S
llU1

SHUTDOWN

~--~~C=r------------------O 10

775

12/86

ELECTRICAL CHARACTERISTICS (Unless otherwise stated, these specifications apply for
TJ = -55°C to + 125°C for the SG1524, -25°C to + 85°C for the SG2524, and O°C to + 70°C for the
SG3524, VIN = 20V, and f = 20KHz).
Parameter

Test condition

REFERENCE SECTION
Output Voltage
VREF
!; VREF Line Regulation
!; VREF Load Regulation

5

5.2

5

5.4

V

V IN -8t040V

10

20

10

30

mV

50

20

50

mV

4.8

4.6

IL = Oto 20mA

20

Ripple Rejection

f = 120Hz, T· = 25"C

66

66

dB

Short Circuit Curr, Limit

V REF = 0, T· = 25"C

100

100

mA

1

0.3

1

%

Over Operating Temp. Range

0.3

Tj = 25°C, t = 1000 Hrs.

20

20

mV

Maximum Frequency

CT - 0.001 I' F. RT - 2kll

300

300

kHz

Initial Accuracy

RT and CT Constant

5

5

Voltage Stability

VIN = 8 to 40V, Tj = 25°C

1

1

Temperature Stability

Over Operating Temp. Range

2

2

Output Amplitude

Pin 3, T· = 25°C

3.5

3.5

Y

Output Pulse Width

CT = O.01I'F, T· = 25°C

0.5

0.5

I's

I::. VREF/!;TTemp. Stability
I::.VREF Long Term Stability

OSCILLATOR SECTION
f MAX

!::.fll::. T

%
%
%

ERROR AMPLI FIER SECTION
Vos

Input Offset Voltage

VCM = 2.5V

0.5

5

2

10

mV

Ib

Input Bias Current

V CM = 2,5V

2

10

2

10

I'A

Gv
CMV

Open Loop Volt. Gain
Common Mode Volt.

Tj = 2SoC

CMR

Comm. Mode Rejec.

Tj = 25°C

B

Small Signal Bandwidth

Av = OdB, Tj = 25°C

Vo

Output Voltage

TJ = 25°C

72

80

1.8

60
3.4

1.8

70

3.4
70

3.8

0.5

45

0

V
dB
MHz

3

3
0.5

dB

80

3.8

V

COMPARATOR SECTION
Duty-Cycle

% Each Output On

VIT

Input Threshold

Zero Duty-Cycle

VIT

Input Threshold

Maximum Duty-Cycle

Ib

Input Bias Current

0

45

%
V

1

1

3.5

3.5

V

1

1

I'A

CURRENT LIMITING SECTION
Pin 9 = 2V with Error Amplifier
Set for Max. Out, T· = 25"C
190

Sense Voltage
Sense Voltage T .C.
CMV

200

210

180

0.2

Common Mode Volt.

-1

200

220

0.2
+1

-1

mV
mVfC

+1

V

0.1

50

I'A

1

2

V

OUTPUT SECTION (Each Output)
Collector-Emitter Volt.
Collector Leackage Cur.

tr
tf
Ilq'

40
VCE = 40V

Saturation Voltage

Ic= 50mA

Emitter Out. Voltage

VIN = 20V

Rise Time

Rc= 2Kll, TJ = 25°C

Fa" time
Total Standby Curro

17

Rc= 2Kll, Tj= 25"C
I VIN - 40V

50

1

2

17

18
0.2

18

V

0.2

I's

0.1

0.1
I 8

10

(*) Excluding oscillator charging current, error and current limit dividers, and with outputs open.

777

V

40
0.1

8

I's
10

mA

outputs may be applied in a push-pull configuration in which their frequency is half that of
the base oscillator, or paralleled for single-ended
applications in which the frequency is equal to
that of the oscillator. The output of the error
amplifier shares a common input to the comparator with the current limiting and shutdown
circuitry and can be overridden by signals from
either of these inputs. This common point is
also available externally and may be employed to
control the gain of, or to compensate, the error
amplifier, or to provide additional control to
the regulator.
RECOMMENDED OPERATING CONDITIONS
8 to 40
V
Supply voltage V,N
0 to 20 mA
Reference Output Current
Current through CT Terminal -0.03 to -2 mA
1.8 to 100 Kn
Timing Resistor, RT
Timing Capacitor, CT
0.001 to 0.1
J.l.F
TYPICAL APPLICATIONS DATA
Oscillator
The oscillator controls the frequency of the
SG 1524 and is programmed by RT and CT according to the approximate formula:
f ""

1.18
RT CT

RT is in Kn
CT is inJ.l.F
f is in KHz
Pratical values of ~ fall between 0.001 and
O. lJ.1.F. Pratical values of RT fall between 1.8
and 100Kn. This results in a frequency range
typically from 120Hz to 500KHz.
where

Blanking
The output pulse of the oscillator is used as a
blanking pulse at the output. This pulse width is
controlled by the value of ~. If small values of
CT are required for frequency control, the
oscillator output pulse width may still be increased by applying a shunt capacitance of up to
100pF from pin 3 to 'ground. If still greater
dead-time is required, it should be accomplished
by limiting the maximum duty cycle by clamping
the output of the error amplifier. This can
easily be done with the circuit below:
Fig. 6

VREF
Comp

'6;}-----,

®

Gnd

'N9'6
~

•

5K,ll

5-6400

Synchronous Operation
When an external clock is desired, a clock pulse
of approximately 3V can be applied directly to
the oscillator output terminal. The impedance to ground at this point is approximately
2Kn. In this configuration RT ~ must be
selected for a clock period slightly greater than
that of the external clock.
If two more SG1524 regulators are to be operated
synchronously, all oscillator output terminals
should be tied together, all CT terminals connected to a single timing capacitor, and the
timing resistor connected to a single RT terminal.
The other RT terminals can be left open or
shorted to V REF' Minimum lead lengths should
be used between the CT terminals.

Fig. 7 - Push-pull transformer-coupled circuit.
+Z8V

+5V, SA

5 K.Jl
lmH

0--I1--+~----116

0-----IM'----l6 5G1524

141----~

10nF

10

r

lnF

0,'

..n.

~~_ _ _ _ _~~_2_0K~L-___- _ - -__
-~~~_ _
779

911.
REGULATING PULSE WIDTH MODULATORS
•
•

8 to 35V OPERATION
5.1V REFERENCE TRIMMED TO ± 1%

•

100Hz to 500KHz OSCILLATOR RANGE

• SEPARATE
MINAL

OSCILLATOR

SYNC

A shutdown terminal controls both the soft-start
circuity and the output stages, providing instantaneous turn off through the PWM latch
with pulsed shutdown, as well as soft-start
recycle with longer shutdown commands. These
functions are also controlled by an undervoltage
lockout which keeps the outputs off and the softstart capacitor discharged for sub-normal input
voltages. this lockout circuitry includes app~oxi­
mately 500mV of hysteresis for jitter-free operation. Another feature of these PWM circuits is a
latch following the comparator. Once a PWN pulses
has been terminated for any reason, the outputs
will remain off for the duration of the period.
The latch is reset with each clock pulse. The
output stages are totem-pole designs capable
of sourcing or sinking in excess of 200mA. The
SG1525A output stage features NOR logic,
giving a LOW output for an OFF state. The
SG1527A utilizes OR logic which results in a
HIGH output level when OFF.

TER-

•

ADJUSTABLE DEADTIME CONTROL

•

INTERNAL SOFT-START

•

PULSE-BY-PULSE SHUTDOWN

•

INPUT UNDERVOL TAGE LOCKOUT WITH
HYSTERESIS

•

LATCHING PWM TO PREVENT MULTIPLE
PULSES

• DUAL SOURCE/SINK OUTPUT DRIVERS
The SG 1525A/1527 A series of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts
count when used in designing all types ofswitching
power supplies. The on-chip + 5.1 V reference is
trimmed to ± 1% and the input common-mode
range of the error ampl ifier includes the reference
voltage eliminating external resistors. A sync
input to the oscillator allows multiple units to
be slaved or a single unit to be synchronized to
an external system clock. A single resistor between
the CT and the discharge terminals provide a
wide range of dead time adjustment. These devices also feature built-in soft-start circuitry
with only an external timing capacitor required.

DIP-16 Plastic (0.25)
and Ceramic

SO-16P

CONNECTION DIAGRAM AND ORDERING NUMBERS
(top view)
INV. INPUT

16

VREF

N.I.INPUT

15

-V,

SYNC

14

OUTPUT B

SG1525A

-

SG1525AJ

13

Vo

SG1527A

-

SG1527AJ

-

12

GROUND

OSC.OUTPUT

4

CT

11

RT
DISCHARGE
SOFT - START

10

8

--Type

OUTPUT A
SHUTDOWN

Plastic DIP Ceramic DIP

SO-16P

SG2525A

SG2525AN

SG2525AJ

SG2525AP

SG2527A

SG2527AN

SG2527AJ

SG2527AP

SG3525A

SG3525AN

SG3525AJ

SG3525AP

SG3527A

SG3527AN

SG3527AJ

SG3527AP

CaMp.

s- 64110

781

12/86

ELECTRICAL CHARACTERISTICS (V,

20V, and over operating temperature, unless other-

wise specified)

Test cond itions

Parameter

SG 1525A/2525A
SG 1527 A/2527 A

SG3525A
SG3527A

Unit

Min. !TYP.! Max. Min.! TYP.! Max.

REFERENCE SECTION
5.2

V

20

10

20

mV

20

50

20

50

mV

20

50

20

50

mV

5.25

V

Vi =S to 35V

10

IL = 0 to 20 mA
Over operating range

Tj = 25°C

lIVREF

Line regulation

lIVREF

Load regu lation

Total output
variation

Line, load and temperature

Short circuit
current

VREF= 0

*

Output noise
voltage

lIVREF*

Long term stability

*

5.1

5.15

Output voltage

t,VREF/t,T* Temp. stability

5.05

5.1

VREF

5.2

5

5

4.95

SO

100

SO

100

mA

10Hz'; f.; 10kHz, Tj=25°C

40

200

40

200

"Vrms

Tj = 125°C, 1000 hrs

20

50

20

50

mV

±2

± 6

±2

±6

%

± 0.3

± 1

± 1

±2

%

± 3

± 6

± 3

±6

%

120

Hz

Tj = 25°C

OSCILLATOR SECTION**

•

..

I nitial accuracy

Tj = 25°C

Voltage stability

Vi =S to 35V

MllIT*

Temp. stability

Over operating range

fMIN

Minim. frequency

RT = 200 K!1

CT= 0.1 "F

fMAX

Maxim. frequency

RT= 2 K!1

CT= 470pF

Current mirror

IRT= 2 mA

•

* •

Clock amplitude

* •

Clock width

Tj = 25°C

Sy nc threshold
Sync voltage = 3.5V

Sync input current

120

KHz

400

400

2

3

3.5

1

0.3

0.5

1

,,5

2

2.8

1.2

2

2.S

V

1

2.5

1

2.5

mA

0.5

5

2

10

mV

2

3

3.5

0.3

0.5

1.2

2.2

2.2

mA

1.7

1.7

V

ERROR AMPLIFIER SECTION (V CM = 5.1V)

Ivos

I nput offset voltage

I
783

ELECTRICAL CHARACTERISTICS (continued)
SG 1525A/2525A
SG 1527A/2527 A

SG3525A
SG3527A

Min. !TYP.! Max.

Min.! TYP.! Max.

I Slnk = 20 mA

0.2

0.4

0.2

0.4

V

Islnk = 100 mA

1

2

1

2

V

Parameter

Test conditions

OUTPUT DRIVERS (Each output) (V e
Output low level

Output high level

=

Unit

20V)

Isource = 20 mA

18

19

18

19

V

Isource = 100 mA

17

18

17

18

V

Under-voltage
lockout

V comp and Vss = high

6

7

6

7

Ie

Collector leakage

Vc = 35V

t r"

Rise time

CL= 1 nF,

Tj = 25°C

100

600

tf"

Fall time

CL = 1 nF,

Tj = 25°C

50

14

8

V

200

/lA

100

600

ns

300

50

300

ns

20

14

20

mA

8

200

TOTAL STANDBY CURRENT
Supply current
"

These parameters, although guaranteed over the recommended operating conditions, are not 100%tested in production.

e Tested at fosc= 40 KHz (RT = 3.6 Kn, CT = O.l/lF, RD = On). APproximate oscillator frequency is defined by:
f =
1
• DC transconductance (gM) relates to DC open-loop voltage gain (G y ) according to the following equation: Gy = gM RL
where RL is the resistance from pin 9 to ground. The minimum gM specification is used to calculate minimum Gy
when the error amplifier output is loaded.

RECOMMENDED OPERATING CONDITIONS (.)
Input voltage (VI)
Collector supply voltage (V cl
Sink/source load current (steady state)
Sink/source load current (peak)
Reference load current
Oscillator frequency range
Oscillator timing resistor
Oscillator timing capacitor
Dead time resistor range

8 to 35 V
4.5 to 35 V
o to 100 mA
to 400 mA
Oto 20 mA
100 Hz to 400 KHz
2 Kn to 150 Kn
0.001 J.1F to 0.1 J.1F
to 500

o

o

(e) Range over which the device is functional and parameter limits are guaranteed.

785

n

L.

Fig. 1 - Oscillator charge
time vs. AT and CT
·T

(KJl )

,. -~·1
I I
1/1/
,. " VV ~ .IAf L
~

2.

-r-.~
~~

~r-'--ron~-,~~~~

VCE

(I\)

f' )

~ :%~

"''I'

~L

J

,,;

WI

.,...,. SOURC£SAU ....\Inti

:"

5

II
Yj .. 2OY

/VV,
V, VV

~ ~ o~
~VV VV

2

Fig. 3 - SG1525A output
saturation characteristics

Fig. 2 - Oscillator discharge
time vs. AD and CT

10 20

so

100 200 500 11M 2n11 H,...)

0.2

0.5

Fig. 4 - Error amplifier
voltage gain and phase vs.
frequency
0,
I
f"

1

2

5

'0

20

50

""'.)

-

////

~~

0.01

SINK SAT,

•.1

'01. /

III
I~(A)

Fig. 5 - SG 1525A error ampl ifier

)

'0

6.

'.

~

Vi ,,20Y

IMn

3001(0

~

'00

:N'

lOKD

V.11,Ift bftow
20 ~nwill~i"tolimillh.
m,.. imumduty tyet.

I
I
Ti-l..
I
L
100

11(

~

I
I PHASE
L
lOt(

10011.

"-

"'101

-

180'
110'

360·

{(Hz'

PRINCIPLES OF OPERATION
SHUTDOWN OPTIONS (See Block Diagram)
immediately set providing the fastest turn-off
signal to the outputs; and a 150 p.A current sink
begins to discharge the external soft-start capacitor. If the shutdown command is short, the
PWM signal is terminated without significant
discharge of the soft-start capacitor, thus,
allowing, for example, a convenient implementation of pulse-by-pulse current limiting. Holding
Pin 10 high for a longer duration, however, will
ultimately discharge this external capacitor,
recycling slow turn-on upon release.
Pin 10 should not be left floating as noise pickup
could conceivably interrupt normal operation.

Since both the compensation and soft-start
terminals (Pins 9 and 8) have current source
pull-ups, either can readily accept a pull-down
signal which only has to sink a maximum of 100
p.A to turn off the outputs. This is subject to the
added requirement of discharging whatever
external capacitance may be attached to these
pins.
An alternate approach is the use of the shutdown
circuitry of Pin 10 which has been improved to
enhance the available shutdown options. Acti·
vating this circuit by applying a positive signal on
Pin 10 performs two functions: the PWM latch is

787

Fig.7

Fig.8
"V'ii

TO OUTPUT
FILTER

A

11

5G1525A
B 14

GNO
12
5-6418
5-6.1,1711

For single-ended supplies, the driver outputs are
grounded. The Vc terminal is switched to ground
by the totem-pole source transistors on alternate
oscillator cycles.

In conventional push-pull bipolar designs, for·
ward base drive is controlled by RI -R3. Rapid
turn-off times for the power devices are ach ieved
with speed-up capacitors CI and C2 .

Fig.9

Fig. 10
.vs o--------~-----.

SG 1525A

5G 1525A

,"

B

02

14

s-

The low source impedance of the output drivers
provides rapid charging of Power Mos input
capacitance while minimizing external com·
ponents.

789

6347

Low power transformers can be driven directly
by the SG 1525A. Automatic reset occurs during
dead time, when both ends of the primary
winding are switched to ground.

SWITCH-MODE POWER SUPPLY CONTROLLER
voltage stability even at high load changes: this
IC can be used not only in TV receivers and
video recorders but also in power supplies in
Hi-Fi sets and active speakers.

•

LOW START -UP CUR RENT

•

DIRECT
CONTROL
TRANSISTOR

•

COLLECTOR CURRENT PROPORTIONAL
TO BASE-CURRENT INPUT

•

REVERSE-GOING LINEAR
CHARACTERISTIC CURVE.

OF

SWITCHING

~

OVERLOAD

T~

The TDA4601 is a monolithic integrated circuit
designed to regulate and control the switching
transistor of a switching power supply.
Because of its wide operational range and high

Powerdip (9 + 9)

ORDERING NUMBER: TDA4601 (SiP-g)
TDA4601 B (9 + 9)

BLOCK DIAGRAM

8

START- UP
CIRCUIT

VOLTAGE
CONTROL

5-7891

791

12/86

ELECTRICAL CHARACTERISTICS
Parameter
Vg

(T amb = 25°C)
Test Conditions

Operating supply voltage.
range

Min.

Typ.

Max.

Unit

18

V

1.5
2.4

0.5
2.0
3.2

mA
mA
mA

11.8

12.3

V

7.8

Start condition (according to test circuit of fig. 1)
Ig

Vg

Supply current
(V 1 not yet switched on)

Vg
Vg
Vg

= 2V
= 5V
= 10V

Switch threshold (VI)

Normal operation (Vg

11

= 10V, V cont = -10V, V clock = ±O.5V. f = 20KHz, duty cycle 1:2 after switch on)
= -10V
= OV

Ig

Supply current

Vcont
Vcont

V ref

Voltage reference at pin 1

11 <0.1 rnA
11 = 5 rnA

V3

Control voltage

Vcont

= OV

V4

Collector current simulation
voltage

Vcont

= OV (see Note

t:.V 4

Collector current simulation
voltage

Vcont = OV to -10V
(see note 1)

V5

External protection
threshold

V7

Pin 7 output voltage

Vcont

= OV
= OV

(see note 1)

Va

Pin 8 output voltage

V cont

Va

Pin 8 output voltage
change

Vcont OV to -10V
(see note 1)

V2

Feedback voltage

(see note 1)

TKI

Reference voltage
temperatu re coeffic.

Protection operation (V 9

1)

(see note 1)

110
50

135
75

160
100

mA
mA

4
4

4.2
4.2

4.5
4.4

V
V

2.3

2.6

2.9

V

1.8

2.2

2.5

V

0.3

0.4

0.5

V

6

7

8

V

2.7

3.3

4.0

V

2.7

3.4

4.0

V

1.6

2

2.4

V

0.2

V

10-'

11K

= 10V; V cont = -10V; VcloCk = ± O,5V; f = 20KHz; duty cycle 1 : 2)

19

Supply current

v 5 .;; 1.8V

14

22

28

mA

V7

SWitch-off voltage

V 5 ';; 1.8V

1.3

1.5

1.8

V

1.8

2.1

2.5

V

V4

793

Fig. 2 - Test and appl ication circu it

lN4007

10kl1./3W

1.5A

BY258/200

,,
, ,I
,
I
I
:
I
, ,

-----,

9
7

15

13

II
I AZV

1___________________________________ _

16

12

6

2 SHe

270

pF

56
kl1.

25V

18V

150V

VI
5-1901/2

1) C limits the max. collector current of BU508 at overshooting the permissible output power.
2) Adjustment of secondary voltage.
3) Must be discharged before IC change.

795

Fig. 3 - Frequency vs. output power (test circuit of
fig. 2).

Fig. 4 - Efficiency vs.
output power test circuit
of fig. 2).

,

,./"1.,

0

'0 0

'"
60

80

f\

"-

40

I

60

i"--

V

I

1--__
'0

20

20

40

60

80

20

Fig. 6 - Output voltage
V2 (mains change) (test
circuit of fig. 2).

40

60

",'"
,,,
'50

....... f-"'"
.......

'49

f-"'"

k-'

80

100 200 300 400 500600 100800900

Fig. 7 - Example of a PC heatsink (35°CIW)

'52

148

Fig. 5 - Load character·
istics V2-f (lq2) (test cir·
cuit of fig. 2).

V

141
150 160 170 180 190 200 2\0 220 230 240 Vmains(V)

797

loz(mA)

ADVANCE DATA

HIGH PERFORMANCE MOTOR SPEED R.EGULATOR
• TACHIMETRIC SPEED REGULATION WITH
NO NEED FOR AN EXTERNAL SPEED
PICK-UP

TDA7272 is an high performance motor speed
controller for small power DC motors as used
in cassette players.

• VII SUPPLEMENTARY PREREGULATION

Using the motor as a digital tachogenerator
itself the performance of true tacho controlled
systems is reached.

• DIGITAL CONTROL OF DIRECTION AND
MOTOR STOP

A dual loop control circuit provides long term
stability and fast settling behaviour.

• SEPARATE SPEED ADJUSTMENT
• 5V TO 18V OPERATING SUPPLY VOLTAGE
•

1A PEAK OUTPUT CURRENT

• OUTPUT CLAMP DIODES INCLUDED

Powerdip
(16 + 2 + 2)

.• SHORT CIRCUIT CURRENT PROTECTION
• THERMAL
TERESIS

SHUT

DOWN

WITH

HYSORDERING NUMBER: TDA7272

• DUMP PROTECTION (40V)

BLOCK DIAGRAM
3

19

2

20

11

13

14

17

18

5,6,15,16

8 10

~-9485

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

799

12/86

TEST CIRCUIT
51
+Vs

52

V3

C1
000
pF

50

I

R1
15K
14

2

13

11

1

9
12

TDA7272
19 20

18

10 5

17

5-9487

ELECTRICAL CHARACTERISTICS (Tamb
Parameter
Vs

Operating supply voltage

Is

Supply current

= 25°C; Vs = 13.5V

Test Conditions

unless otherwise specified)

Min.

Typ.

5

5

No load

Max.

Unit

18

V

12

mA

OUTPUT STAG E
10

Output current pulse

10

Output current continuous

V lO- 9,12

Voltage drop

10

=

250mA

1.2

1.5

V

Vll- 9,12

Voltage drop

10

=

250mA

1.7

2

V

801

1

A

250

mA

OPERATING PRINCIPLE

limited on principle by the resolution in time of
the tachometer, this control principle offers a
poor reaction time for motors with a low number
of poles. The realized circuit is extended by a
second feed forward loop in order to improve
such system by a fast auxiliary control path.

The TDA7272 novel applied solution is based on
a tachometer control system without using such
extra tachometer system. The information of the
actual motor speed is extracted from the motor
itself. A DC motor with an odd number of poles
generates a motor current which contains a fixed
number of discontinuitues within each rotation.
(6 for the 3 pole motor example on Fig. 1)

This additional path senses the mean output
current and varies the output voltage according
to the voltage drop across the inner motor resistance. Apart from a current averaging filter,
there is no delay in such loop and a fast settling
behaviour is reached in addition to the long term
speed motor accuracy.

Deriving this inherent speed information from
the motor cu rrent, it can be used as a replacement of a low resolution AC tachometer system.
Because the settling time of the control loop is

Fig. 1 - Equivalent of a 3 pole DC motor (a) and typical motor current waveform (b)
lm-

E

L

R

(a)

1m

( b)

5 - 9494

BLOCK DESCRIPTION

current magnitude and duration T, are adjustable
by external elements CT and RT.

The principle structure of the element is shown
in Fig. 2. As to be seen, the motor speed information is derived from the motor current
sense drop across the resistor As; capacitor CD
together with the input impedance of 500n at
pin 1 realizes a high pass filter.

The monostable is retriggerable; th is fu nction
prevents the system from fau It stabilization at
higher harmonics of the nominal frequency.
The speed programming current is generated
by two separate external adjustable current
sources. A corresponding digital input signal
enables each current source for left or right
rotation direction. Resistor RP1 and RP2 define
the speed, the logical inputs are at pin 18 and 19.

This pin is internally biased at 25mV, each negative zero transition switches the input comparator. A 10mV hysteresis improves the noise
immunity.
The trigger circuit is followed by an internal
delay time differentiator.

At the inverting input (pin 14) of the main amplifier the reference current is compared with the
pulsed monostable output current.

Thus, the system becomes widely independent
of the applied waveform at pin 1, the differentiator triggers a monostable circuit which provides a constant current duration. Both, output

For the correct motor speed, the reference current matches the mean value of the pulsed
monostable current. In this condition the charge
of the feedback capacitor becomes constant.

803

PIN FUNCTION AND APPLICATION
INFORMATION

The biasing of the pin 1 is 25mV with a hys·
teresis of 10mV. So the sensing resistance must
be chosen high enough in order to obtain a
negative spike of the least 30mV on pin 1, also
with minimum variation of motor current:

Pin 1
Trigger input. Receives a proper voltage which
contains the information of the motor speed.
The waveform can be derived directly by the
motor current (Fig. 3). The external resistor
generates a proper voltage drop. Together with
the input resistance at pin 1 [ R'N (1) = 500n ]
the external capacitor CD realize a high pass
filter which differentiates the commutation
spikes of the motor current. The trigger level is
OV.

30mV
Rs ; ; ; . - - - - b.I MoT min.
Such value can be too much high for the preregulation stage V-I and it could be necessary to
split them into 2 series resistors Rs = RS1 + RS2
(see fig. 4) as explained on pin 8 section.
Fig. 4

Fig.3

Co

5-9495

(mV)

VII
REG

Vp1N1

25

The information can be taken also from an
external tachogenerator. Fig. 5 shows various
sources connections:
10
1(5)

the input signal mustn't be lower than -O.7V.

5-9496

Fig. 5

TTL-MOS

5- 9498/1

PHOTOTRANSISTOR
TACHO
805

MAGNETIC
TACHO

Fig. 10

The low pass-filter R L , CL must be calculated in
order to reduce the ripple of the motor commutation at least 20dB. Another example of
possible pins 10-8 connections is showed on
Fig. 9. A choke can be used in order to reduce
the radiation.
Fig.9

8

10

5- 9502

Pin 10
4.7}JF

I

Common sense output. From this pin the output
current of the bridge configuration (motor
current) is fed into Rs external resistor in order
to generate a proper voltage drop.

5-9503/1

The drop is supplied into pin 1 for tachometric
control and into pin 8 for V /1 control (See pin 1
and pin 8 sections).

Pin 9

Output motor left. The four power transistors
are realized as darlington structures. The arrangement is controlled by the logic status at
pins 18 and 19.

Pin 11

Supply voltage.
Pin 12

As before explained (see block description), in
the normal left or rig~t mode one of the lower
darlington becomes saturated whereas the other
remains open. The upper half of the bridge
operates in the linear mode.

Output motor right. (See pin 9 section)
Pin 13

Output main amplifier. The voltage on this pin
results from the tachometric speed control and
feed s th e ou tpu t stage.

In stop condition both upper bridge darlingtons
are off and both lower are on. In the high output
impedance state the bridge is switched completelyoff.

The value of the capacitor CF (Fig. 4), connected
from pins 13 and 14, must be chosen low enough
in order to obtain a short reaction time of the
tachometric loop, and high enough in order to
reduce the output ripple.

Connecting the motor between pins 9 and 12
both left or right rotation can be obtained. If
only one rotation sense is used the motor can be
connected at only one output, by using only the
upper bridge half. Two motors can be connected
each at the each output: in such case they will
work alternatively (See Application Section).

A compromise is reached when the ripple voltage
(peak-to-peak) V ROP is equal to 0.1 VMOTOR:

CT

CF = 2.3 - - (1

The internal diodes, together with the collector
substrate diodes, protect the output from inductive voltage spikes during the transition
phase.

V R1P

with
807

V R1P

=

VFEM

+

'MOT •

10

RT

---I
Rp

RMOT

and

Fig. 14

Fig. 15

3

s- 9 504
5-9509

Pin 14
Inverting input of main amplifier. In this pin the
current reference programmed at pins 20, 17 is
compared with the current from the monostable
(stream of rectangular pulses).

Fig. 16

In steady-state condition (constant motor speed)
the values are equal and the capacitor CF voltage is constant.
This means for the speed n (mi n -1) :
n =

10.435
CT m Rp

where "m" is the number of collector segments.
(poles)

Fig. 17

The non inverting input of the main amplifier is
internally connected to a reference voltage (2.3V).
Pin 15
Ground.
Pin 16
Ground.
Pin 17
Left speed adjustment. The voltage at this pin
is fixed to a reference value of O.BV. A resistor
from this pin and ground (Fig. 14) fixes the
reference current which will be compared with
the medium output current of the monostable
in order to fix the speed of the motor at the
programmed value. The correct value of Rp
would be:
10.435
Rp = CT • ni • n'

Fig.1B

n = motor speed, (min -1)
m = poles number
B09

Fig. 21 - Tacho only speed regulation
F

lor:

CT

I

14

13

11

9

12

C

E

R2
5 -9469/1

Fig. 22 - One direction reg. of one motor, or alternatively of two motors

rJ:F

Al>--+---'

F
B

5-9490

811

(:~~~~~~l~?:

::;;I?~:~1~;M!!./j'!~~:;~~~~~//:'Y/it~~>'i::'·~:~

Fig. 25 -- High current TOA7272 + 2 x L 149 application

Fig. 24 -- Speed regulation
versus supply voltage
(Circuit of Fig. 20)

ilf·'·H-++-H-++-H-+++-H--I

-0.2

-0.4

H++H-++t---I-++,...H--I

H-++-H-++--H-+++-I-+-1

10

15

~~-------Cf-----~~
s- 91091

Fig. 26 -- In connection with a presettable counter and I/O peripheral the TOA7272 controls the speed
through a 0/A converter

I

Z B430 CTC
17

ZC
2 ClK

TOA7272
13

j
,

ZC
ClK

14
18

Z8420 PIO

SPEED
CONTROL

OUTPUT
PORT

DAC
0808

5-9.493

813

aB.

ADVANCE DATA

DUAL MOTOR DRIVER
•

which realizes two independent programmable
current sources. The device is well suited for
motor driving applications such ~as reel motors
in video recorders. A wide supply voltage range
perm its battery operation.

HIGH OUTPUT CURRENT, EACH CHANNEL UP TO 1A

• WIDE SUPPLY
UP TO 28V

VOLTAGE

RANGE, 4V

• SHORT CIRCUIT PROTECTION
• SAFE OPERATING
LIMITING

AREA

CURRENT

• TEMPERATURE SHUT DOWN WITH HYSTERESIS
•

Heptawatt

HIGH INPUT IMPEDANCE

• GROUND COMPATIBLE INPUT
ORDERING NUMBER: TDA8115

The TDA8115 is a monolithic integrated circuit

BLOCK DIAGRAM

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

815

4/86

ELECTRICAL CHARACTERISTICS (T amb = 25°C. unless otherwise specified)
Parameter

Test Conditions

Min.

Vs

Supply voltage

IQ

Quiescent current

10

Output current range

VIR

Input voltage range

0

VOS

Positive input offset for current
starting point

50

Typ.

4
2

60

Max.

Unit

23

V

5

mA

1

A

Vs -3

V

80

mV

Thermal shut down

150

Hysteresis

20

·c
·c

1.4
0.4

A
A

Output cu rrent limit

IL

Vs = 10V
Vs = 20V

Ib

Input bias current

Vsat

Saturation voltage

Rs

Bond resistance

1.4

lOUT =0.9A

1

/loA

2

V

60

Fig. 1 - Transconductance characteristic

mO

Fig. 2 - Max output current vs. supply voltage (SOA)
10
(A)

'0

(A)

1

1.l.f----,.

O~~~--------~--~

40mV

lV

Vs (V)

5- 8711

with.

10 =

s- 8712
V IN - 40mV
(RS + 60mO)

817

lIB.

ADV ANCE DATA

FOUR PHASE BRUSHLESS MOTOR DRIVER
• WIDE OPERATING VOLTAGE RANGE 6V
TO 14V

The TDA 8116 is a monolithic integrated circuit
in bipolar technology.

•

HIGH CURRENT CAPABILITY UP TO 1A

•

OUTPUT DC CURRENTS UP TO O.4A

It is intended for driving a four phase brush less
video head motor in microcomputer controlled
servo systems.

• TWO LOGICAL INPUTS FOR THE CODED
COMUNICATION SIGNAL
•

LIMITED SLEW RATE OF THE OUTPUT
VOLTAGE

•

ANALOG INPUT WITH FIXED VOLTAGE
GAIN

•

INTEGRATED FLYBACK
EACH OUTPUT

•

THERMAL PROTECTION

DIODES

Powerdip

12 + 2 + 2

AT
ORDERING NUMBER: TDA 8116

BLOCK DIAGRAM

D/A

}JP

This i.1 advanced information on 8 new product now in development or undergoing evaluation. Details are subject to change without notice.

819

12/86

THERMAL DATA
Parameter
TJsTD
TJsDH
Rth J-c:ase
RthJ...mb

Thermal
Thermal
Thermal
Thermal

Min.

Typ.

Parameter

Unit

14
80

°c
°c
°C/W
°C/W

150
20

shut down threshold
shut down hysteresis
resistance junction-ground pins
resistance junction-ambient

ELECTRICAL CHARACTERISTICS 16V

Max.

< Vs < 14V. TJ =
Tilt Conditions

25°C. unless otherwise specified)
Min.

Typ.

Max.

Unit

14

V

VsoP

Operating sypply voltage
range

Vso

Sou rce stage satu rati on
voltage

VIN =5V
10=0.4A

10= lA

1.4
1

2
1.4

V
V

Va

Sink stage saturation
voltage

VIN=5V
10=0.4A

10=lA

1.4
1

2
1.4

V
V

Av

Voltage gain

VIN-1V

RL. =500

VINth

Input voltage threshold

IN

Input current

VIN

Input voltage operating
voltage range

VX.v High

Control input HIGH level

Ix. V High

Control input HIGH current

Vx. v L.ow

Control input LOW level

6

VIN=5V

2.5

2.75

3.0

V

0.6

0.7

0.8

V

-5

-1

+5

pA

Vs -1

V

0
1.7

2.4

VIN=5V

V IN =0.4V

7

V

20

IJA

0.3

0.8

V

-20

20

IJA

Ix. V Low

Control input LOW current

VEN L.ow

Enable input LOW level

-0.3

1.5

V

V EN High

Enable input HIGH level

2.4

7

V

lEN Low

Enable input LOW current

VEN=OV

-20

-40

IJA

lEN High

Enable input HIGH current

V EN =5V

1

IJA

VHX. V. EN

Control and enable inputs
hysteresis

150

mV

dVout
dt

Output voltage slope

Cl.2 = 10nF

6

V/ms

hOSTI

Starting output current

V IN =5V
Vs= 12V

IS

Ouiescent supply current

VIN=O

Is

Supply current

VIN=5V

821

1

A

3

5

mA

8

15

mA

II.

ADVANCE DATA

CURRENT MODE PWM CONTROLLER
•

FEW EXTERNAL COMPONENTS

•

FIXED FREQUENCY OPERATION

•

HIGH CURRENT TOTEM POLE OUTPUT

•

INTERNALLY TRIMMED BAND GAP REFERENCE

•

DOUBLE PULSE SUPPRESSION

•

PULSE-BY~PULSE

CURRENT

features to implement off line, fixed frequency
current mode control schemes with a minimal
external parts cou nt.
The advantages for this tecniQue can be measured
in improved line regulation, enhanced load
regulation and a simplier control loop.
Protection circuitry includes buit-in under voltage lockout, pulse-by-pulse current limiting and
an antimagnetization circuit.

LIMITING

•

LOW START UP CURRENT « 1mA)

•

UNDER VOLTAGE LOCKOUT

• ANTIMAGNETIZATION CIRCUIT
•

EXTERNAL

DUTY-CYCLE

Plastic Minidip

LIMITATION

Designed primarily for TV/Monitor applications,
the TDA8130 control IC provides the necessary

ORDERING NUMBER: TDA8130

BLOCK DIAGRAM

4

This is advanced information on a new product now in development or undergoing evaluation. De-tails are subject to change without notice.

823

12/86

//.~;:tJ!':~'~~5';t

", ";/1

"N/"J

"',/i.',>·,>i,,·,C

ELECTRICAL CHARACTERISTICS (Vs = 8V, Tamb = 25°C)
Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Vs

Operating supply voltage

After start-up

8

V

Is

Supply current
(without load)

Vs =8V
after start-up

20

mA

Vst

Start-up threshold

8.4

V

Vso

Switch-off threshold

5.6

V

151

Supply current before
start-up

Vr

Internal supply voltage

3.2

V

Va

Reference voltage

1.2

V

Vb

Current limiter threshold

0.75

V

Vc

Flyback sense threshold

0.4

V

fa

Oscillator free running
frequency

40

kHz

fm

Maximum oscillator free
running frequency

Voh

Sou rce satu ration
voltage

10 = 100mA

Vol

Sink saturation voltage

10 = 0.5A

1

with C = 3.3nF
R = 3.3Kil

kHz

100

825

mA

0.8

V

1

V

Fig. 4 - Printed circuit and component layout of the-circuit of fig. 3 (1 : 1 scale)

ir.

>

.-..
ID

N
N

.,o
oil
U

+
827

L

II.

I

ADVANCE DATA

CURRENT MODE PWM CONTROLLER
•
•

HIGH CURRENT TOTEM POLE OUTPUT

•

INTERNALLY TRIMMED BAND GAP REFERENCE

•

DOUBLE PULSE SUPPRESSION

•

PULSE-BY-PULSE CURRENT LIMITING

•

LOW START UP CURRENT « 1mA)

•

UNDER VOLTAGE LOCKOUT

•

ANTI MAGNETIZATION CIRCUIT

•

EXTERNAL DUTY CYCLE LIMITATION

•

RAMP GENERATOR WITH
NIZATION FACILITY

•

ENABLE INPUT

•
•

Designed primarily for TV/Monitor applications,
the TDA8132 control IC provides the necessary
features to implement off line, fixed frequency
current mode control schemes with a minimal
external parts count. The advantages of this
technique can be measured in improved line regulation, enhanced load regulation and a simplier
control loop. Protection circuitry includes
built-in under voltage, lockout, phase-by-pulse
current limiting and an anti magnetization circuit.

FIXED FREQUENCY OPERATION

SYNCHRO-

DIP-14 Plastic

OVER AND UNDER VOLTAGE DETEC• TORS
ORDERING NUMBER: TDA8132

OVERLOAD IDENTIFICATION

BLOCK DIAGRAM

'4

This is advanced information on a new product now in development or undergoing evaluation. De.tails are subject to change without notice.

829

12/86

ELECTRICAL CHARACTERISTICS (Vs = 8V, Tamb = 25°C)

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Vs

Operating supply voltage

After start-up

8

V

Is

Supply current
(without load)

Vs=8V
after start-up

20

mA

Vst

Start-up threshold

8.4

V

Vso

SWitch-off threshold

5.6

V

151

Supply cu rrent before
start-up

Vr

Internal supply voltage

3.2

V

Va

Reference voltage

1.2

V

Vb

Current limiter threshold

0.75

V

Vc

Flyback sense threshold

0.4

V

fo

Oscillator free running
frequency

40

kHz

fm

Maximum oscillator free
running frequency

Voh

Source saturation voltage

10 = 100mA

0.8

V

Vol

Sink saturation voltage

10 = 0.5A

1.5

V

Isync

Synchronous input current
(positive going)

Vov

Over-voltage threshold

Vuv
Va

1

with C = 3.3nF
R = 3.3Kn

mA

kHz

100

p.A

100

1.2

V

Under-voltage threshold

0.75

V

Enable threshold

0.5

V

831

Fig. 5 - Output voltages vs.
12V output current (1012)

Fig. 4 - Output voltages vs.
5V output current (105)

G~971

6·5916

Vo

vo

I

I' J

IV 1

I

,

-

VREG

,

,

t--

"'

17

10

---

"

/

0",

10

IVoJ
v..,

,,/

:5~

J

h.

vo'

'0'

I'

/

0.5

833

1

15

2

2.5

J

3.5

41012 (1\)

II.
SUPPLY VOLTAGE SUPERVISORS
delay that delays the return of the reset outputs
to their inactive states. Since the time delay
for most microcomputers and microprocessors is
in the order of several machine cycles, the device
internal time delay is determined by an external
time delay is determined by an external capacitor
connected to the CT input (pin 3).
td = 1.3 X 104 x CT
Where: CT is in farads (F) and td is in seconds(s)
In addition, when the supply voltage drops below
the nominal value, the outputs will be active
until the supply voltage returns to the nominal
value. An external capacitor (typically 0.1IlF)
must be connected to the REF output (pin 1) to
reduce the influence of fast transients in the
supply voltage.
The TL7700AI series is characterized for operation from _25°C to 85°C; the TL7700AC series
is characterized from O°C to 70°C.

• POWER-ON RESET GENERATOR
• AUTOMATIC RESET GENERATION AFTER
VOLTAGE DROP
• WIDE SUPPLY VOLTAGE RANGE ... 3V
.TO 18V
• PRECISION VOLTAGE SENSOR
• TEMPERATURE-COMPENSATED
AGE REFERENCE

VOLT-

• TRUE AND COMPLEMENT RESET OUTPUTS
•

EXTERNALLY ADJUSTABLE PULSE
WIDTH

The TL7700A series are monolithic integrated
circuit supply voltage supervisors specifically
designed for use as reset controllers in microcomputer and microprocessor systems. During
power-up the device tests the supply voltage and
keeps the RESET and RESET outputs active (high
and low, respectively) as long as the supply
voltage has not reached its nominal voltage value.
Taking RESIN low has the same effect. To
ensure that the microcomputer system has reset,
the TL7700A then initiates an internal time

Plastic Minidip

SO-B

BLOCK DIAGRAM

RESET

CT.
5EN5E
INPUT
RI*

R2*

RESiN
~--------------4----------+~REF

GNO

5-8037

*TL7702A Rl = 00, R2 = open;TL7705A Rl =7.BKO, R2 = 10KO; TL7709A Rl = 19.7KO, R2 = 10KO; TL7712A
Rl = 32.7KO, R2 = 10KO; TL7715A Rl = 43.4KO, R2 = 10KO

835

12/86

THERMAL DATA
Rth j-amb

Thermal resistance junction-ambient

120

max.

ELECTRICAL CHARACTERISTICS These specifications unless otherwise specified, apply for:
Tamb

=

-40 to 85°C (TL77XXAI); Tamb

=

0 to 70°C (TL77XXAC)
Test Conditions 11)

Parameter
VOH

High-level output voltage at RESET

IOH = -16mA

VOL

Low-level ou ,put voltage at RESET

IOL= 16mA

Vref

Reference voltage

Tamb = 25°C

VT

Threshold Voltage at
SENSE input

Min.

Typ.

Max.

Vs-1.5

Unit
V

0.4

V
V

2.48

2.53

2.58

TL7702A

2.48

2.53

2.58

TL7705A

4.5

4.55

4.6

Vs = 3.6V to 18V
TL7709A

7.5

7.6

7.7

10.6

10.8

11.0

V

Tamb = 25°C
TL7712A

VT

Threshold voltage at
SENSE input

TL7715A

13.2

13.5

13.8

TL7702A

2.45

2.53

2.58

TL7705A

4.45

4.55

4.6

TL7709A

7.4

7.6

7.7

TL7712A

10.4

10.8

11.0

TL7715A

13.0

13.5

13.8

Vs = 3.6V to 18V

VT+, VT-

Hysteresis (2) at
SENSE input

TL7702A

V

10

TL7705A

15
Vs = 3.6V to 18V

TL7709A

20

mV

Tamb = 25°C
TL7712A

35

TL7715A
II

Input current at RESIN input

45
Vi = 2.4V to Vs

20

Vi = O.4V

< VI < Vs -1.5V

-100

II

Input current at SENSE input

IOH

High-level output current at RESET

Vo= 18V

50

IOL

Low-level output current at RESET

Vo=OV

-50

Is

Supply current

All inputs and out. open

TL7702A

Vref

0.5

1.8

2

3

/lA

mA

1. All characteristics are measured with C = O.l/lF from Pin 1 to GND, and with C = O.l/lF from Pin 3 to GND
2. Hysteresis is the difference between the positive going input threshold voltage. VT+, and the negative going input
threshold voltage, VT-.

837

II.

PRELIMINARY DATA

PROGRAMMABLE, OFF-LINE, PWM CONTROLLER
•

•
•
•
•

•
•
•
•
•
•
•
•

a wide input voltage range.
In addition to startup and normal regulating
PWM functions, these devices offer built-in protection from over-voltage, under-voltage, and
over-current fault conditions. This monitoring
circuitry contains the added features that any
fault will initiate a complete shutdown with
provisions for either latch off or automatic
restart. In the latch-off mode. the controller may
be started and stopped with external pulsed or
steady-state commands.
Other performance features of these devices include a 1% accurate reference, provision for
slow-turn-on and duty-cycle limiting, and highspeed pulse-by-pulse current limiting in addition
to current fault shutdown.
The UC 1840's PWM output stage includes a latch
to insure only a single pulse per period and is
designed to optimize the turn off of an external
switching device by conducting during the "OF F"
time with a capability for both high peak current
and low saturation voltage. These devices are
available in an l8-pin dual-in-line plastic or
ceramic package.
The UC1840 is characterized for operation over
the full military temperature range of -55°C to
+ 125°C. The UC2840 and UC3840 are designed
for operation from -25°C to +85°C and aoc to
+ 70°C, respectively.

ALL CONTROL, DRIVING, MONITORING,
AND PROTECTION FUNCTIONS INCLUDED
LOW-CURRENT, OFF-LINE START CIRCUIT
FEED-FORWARD LINE REGULATION
OVER 4 TO 1 INPUT RANGE
PWM LATCH FOR SINGLE PULSE PER
PERIOD
PULSE-BY-PULSE CURRENT LIMITING
PLUS SHUTDOWN FOR OVER-CURRENT
FAULT
NO START-UP OR SHUTDOWN TRANSIENTS
SLOW TURN-ON AND MAXIMUM DUTYCYCLE CLAMP
SHUTDOWN UPON OVER- OR UNDERVOLTAGE SENSING
LATCH OFF OR CONTINUOUS RETRY
AFTER FAULT
REMOTE,PULSE-COMMANDABLE START/
STOP
PWM OUTPUT SWITCH USABLE TO 1A
PEAK CURRENT
1% REFERENCE ACCURACY
500 kHz OPERATION

Although containing most of the features required by all types of switching power supply
controllers, the UC1840 family has been optimized for highly-efficient boot-strapped primaryside operation in forward or flyback power converters. Two important features for this mode are
a starting circuit which requires little current
from the primary input voltage and feed-forward
control for constant volt-second operation over

DIP-18 Plastic
(U7P2)
and Ceramic

CONNECTION DIAGRAM AND ORDERING NUMBERS
(top view)
COMPENSATION
START I

o II

,

"

uv

SENSE

STOP

rNV INPUT

"
"

THRESHOLD
CURRENT SENSE

Type

11

Plastic

Ceramic

UC1840

-

UC1840J

UC2840

UC2840N

UC2840J

UC3840

UC3840N

UC3840J

+Vr SUPPLY

GROUND

13

SLOW-START

RT' CT

5 II REF

DRIVER BIAS

RESET

CURRENT

NON INY INPUT

PWM

OUTPUT
V\ SENSE

10

RAMP

839

12/86

THERMAL DATA
Rth

j-amb

Thermal resistance junction-ambient

max

80

°C/W

FUNCTIONAL DESCRIPTION
Name

Function

PWM CONTROL
OSCILLATOR

Generates a fixed-frequency internal clock from an external RT
and CT.
Frequency

=

Kc

RTC T
0.3 log (C T X 1012 ).
RAMP GENERATOR

where Kc is a first-order correction factor ""

Develops a linear ramp with a slope defined externally by

~dv
t

sense v;ltage • CR is normally selected .;;;; ~ and
RR

R

its value will have some effect upon valley voltage.
C R terminal can be used as an input port for current mode control.
ERROR AMPLIFIER

Conventional operational amplifier for closed-loop gain and phase
compensation.
Low output impedance: unity-gain stable.

REFERENCE GENERATOR

Precision 5.0V for internal and external usage to 50 mAo
Tracking 3.0V reference for internal usage only with nominal
accuracy of ± 2%.
40V clamp zener for chip O.V. protection, 100mA maximum current.

PWM COMPARATOR

Generates output pulse which starts at termination of clock pulse
and ends when the ramp input crosses the lowest of two positive
inputs.

PWM LATCH

Terminates the PWM output pulse when set by inputs from either
the PWM comparator, the pulse-by-pulse current limit comparator,
or the error latch. Resets with each internal clock pulse.

PWM OUTPUT SWITCH

Transistor capable of sinking current to ground which is off during
the PWM on-time and turns on to terminate the power pulse. Current capacity is 400mA· saturated with peak capacitance discharge
in excess of one amp.
841

ELECTRICAL CHARACTERISTICS (Refer to the test circuit. Unless otherwise stated, these
specifications apply for Ti = -55 to + 125°C for the UC1840, -25°C to + 85°C for the UC2840 and
o to 70u C for the UC3840; Vi = 20V, RT = 20Kn, ~ = 0.001 I1F, CR = 0.001 I1F, current limit
threshold = 200mV
Parameter

UC1840
UC2840

Test conditions
Min.

I

Typ.

I

UC3840
Max.

Min.

I

Typ.

Units

I

Max.

POWER INPUTS
1ST

Start-up current
"Start-up current
T.C.

Vi
Tj

~
~

30V,
25°C

Pin

Ii

Operating current

Vi

Supply O.V. clamp

Ii

~
~

2.5V,

Pin 2- 2.5V

Vi - 30V,

Vsov

2~

Pin

30V,

2~

3.5V

20m A

4

5.5

4

5.5

rnA

-0.1

-0.2

-0.1

-0.2

%tc

5

10

15

5

10

15

mA

33

40

45

33

40

48

V

4.9

REFERENCE SECTION
V REF

Reference voltage

T j ~ 25°C

5

5.05

5

5.1

V

!1VREF

Line regulation

Vi - 8 to 30V

10

15

10

20

mV

IL - 0 to 20 mA

10

20

10

!1VREF Load regulation
EV REF /!1T" Temperat. coeft.
Isc

Short circuit curro

4.95

Over op. temp. range
V REF~ 0, T j

~

30

mV

± 0.4

mV/oC

-80

-100

mA

50

55

KHz

0.5

1

%

± 0.8

%rC

± 0.4

25°C

-80

-100

50

53

0.5

1

OSCILLATOR
fs

Nominal frequency

Tj

Voltage stability

Vi - 8 to 30V

" Temperature coeff.
fs(max)

Maxim. frequency

~

25°C

47

Over op. temp. range
RT~

2K!1,

CT~

45

±0.8

330pF

500

KHz

500

RAMP GENERATOR
Ramp current min.

ISENSE~

Ramp current max.

ISENSE- 1 rnA

-0.9

-0.95

0.3

0.5

0.7

0.3

0.5

0.7

V

Clamping level

3.9

4.2

4.5

3.9

4.2

4.5

V

0.5

5

2

10

mV

0.5

2

1

5

)LA

0.5

)LA

-11

-10)LA

Ramp valley
Ramp peak

-14

-11
-0.9

-14

)LA
rnA

-0.95

ERROR AMPLIFIER
Vos

I nput offset voltage

Ib

I nput bias current

los
Gv

I nput offset current

VCM~5V

0.5

Open loop gain

!1Vo~

1 to 3V

60

Output swing (max
Out';; Ramp peak
-100 mV)

Minimum total range

0.3

CMR

Common mode
rejection

Vq,1~

70

80

70

80

dB

SVR

Supply voltage
rejection

Vi -8 to 30V

40

50

40

50

dB

1.5 to 5.5V

843

60

66
3.5

dB

66

0.3

3.5

V

··UC1840
UC2840
UC3840

Fig. 1 - Open loop test circuit
SUPPLV
valTAGE

RR )IOOK11

1.

RS )180Kll Roc
I.
V,N

SLOW ST. 8 _~o

16 VREF.

RT

~'h~

J:'nF,-----

CT:;-RI lOKll

DRIY. BIAS 14

11YIN SENSE

OR L:1Kfi

MONITOR

GNO 13

10 RAMP

----

STOP 4

3.0Y SENS

CR~

:I!:nF

COMP.
I

RESET 5

INY.

N.!.

C/LH

e/l(+)

11

18

6

7

l~PWMI~

J

10KA

ADJ.

[

Start voltage = 3 ( R1 + R2 + R3 ) + 0.2 R1 = 12\1
R2 + R3

r--r-r--r-r--,.-,-"=::"

m l---'-t.::--m-:.,..,:f.:----+--+----+-+--1---l

43
K11

2KH

10
K1l.
SENS
__ CURRENT
TEST

Current limit = 200 mV
Current fault voltage = 600 mV
Duty cycle clamp = 50%

= 8V

Fig. 3 - PWM Output saturation voltage

Fig. 2 - Start U.V. hysteresis
current
·IH

[

O.V. fau/tvo/tage = 3 ( R1 + R2 + R3 ) = 32V
R3

Nomina/ frequency = __1__ = 50 kHz
RTCT

("A)

'8
011

--

5-1412

U.V. fault voltage = 3 ( R 1 + R2 + R3 )
R2 + R3

...

~

VREF

Io.,,..F

OUTPUT

UC1840

2 START I UV

....

+

PWM OUT 12

9 Rr/er

RZ[ 9Kll

R3[ 3Kll

Cs

Fig. 4 - Oscillator frequency

VCEIsil.l I
(VI

vin:20V
LOWOUTV-C~Lf.

~o~-f'~n~·2~·=2.~'+__+-+__+-+__+

PULSE TEST

I-

UC3840max

./

L.:::::

r-r--- Ti,,-5S'C
TJ=ZS'C

UCJ8loOmin

"'1.-:..."'-+-I--+--1--+----+-+--1
1M 1---+-+--+-+--+--+----+----1

. ISO

100

(' ~

11/

L--L_L--L_L--L_~-L~

-so

-25

2S

50

75

100

Tj {-CI

I••

......

f- I-:: P

..

,

845

300

,"00 lo(mA)

5

10

20

50

100 200

RrCKnl

APPLICATION INFORMATION (continued)
In this application (see Fig. 8) complete control
is maintained on the primary side. Control power
is provided by RIN and CIN during start-up, and
by a primary-referenced low voltage winding.
N2, for efficient operation after start. The error
amplifier loop is closed to regulate the DC
voltage from N2 with other outputs following
through their magnetic coupling - a task made
even easier with the UC1840's feed-forward line

regulation.
The UC1840 will readily accept digital start/stop
commands transmitted from the secondary side
by means of optical couplers.
Not shown are protective snubbers or additional
interface circuitry which may be required by the
choice of the high-voltage switch, Os, or the application.

Fig. 9 - Power sequencing functions
B

o

E

I

I

I

I

I

HI J
I I I

MNO
I I I

ORS
I I I

I I I
H I J.

I I I
M NO

Q

'c
(NOTE 1)

DRIVER
BIAS
SLOWSTART
PWM
OUTPUT

EXT
STOP

RESET

DE

Notes:

I

I

I

R 5

I
U

I
V

1. VC represents an analog of the output voltage generated by a primary-referenced secondary winding on the
power transformer. It is the voltage monitored by the start/U.V. comparator and, in most cases, is the supply
voltage, VI, for the UC1840.
2. Although input to External Stop, Pin 4, is shown, results are the same for any fault input which sets the
Error Latch.

Power Frequency Functions
Time

A
B
C
D
E
F

Initial turn-on, Vc rises with light load
Start threshold. Driver Bias loads Vc
Operating PWM regulates Vc
Stop input sets Error Latch turning off
PWM
U.V. low threshold. Error Latch remain set
Start turns on Driver Bias bus Error Latch
still set

G
H}

Vc and Driver Bias continue to cycle

I
J

Stop command removed
Error Latch reset at U.V. low threshold
Start threshold now removes slow-start
clamp

K

Time

Event

L
M
N

Return to normal run state
Reset Latch set signal removed
Error Latch set with momentary fault
Error Latch does not reset as Reset Latch
is reset

PO}

Vc and Driver Bias recycle with no turn-on

R

Reset Latch set is set with momentary
Reset signal
Vc must complete cycle to turn-on
Start and Err.:>r Latches reset
Normal start initiated
Return to normal run state

o

S
T
U
V

847

Event

II.

ADVANCE DATA

CURRENT MODE PWM CONTROLLER
FOR OFF-LINE AND DC TO
• OPTIMIZED
DC CONVERTERS
LOW START-UP CURRENT
1mA)
• AUTOMATIC
FEED
FORWARD
COMPEN• SATION
CURRENT LIMITING
• PULSE-BY-PULSE
ENHANCED
LOAD
RESPONSE CHARAC• TERISTICS
UNDER-VOLTAGE LOCKOUT WITH HYS• TERESIS
PULSE SUPPRESSION
• DOUBLE
HIGH
CURRENT
TOTEM POLE OUTPUT
• INTERNALLY TRIMMED
BANDGAP REF• ERENCE

insure latched operation, a PWM comparator
which also provides current limit control, and a
totem pole output stage designed to source or
sink high peak current. The output stage, suitable
for driving N-Channel MOSFETs, is low in the
off-state.

«

•

500KHz OPERATION

•

LOW Ro ERROR AMP

Differences between members of this family are
the under-voltage lockout thresholds and maximum duty cycle ranges. The UC1842 and UC1844
have UVLO thresholds of 16V (on) and 10V
(off), ideally suited to off-line applications. The
corresponding thresholds for the UC1843 and
UC1845 are 8.5V and 7.9V. The UC1842 and
UC1843 can operate to duty cycles approaching
100%. A range of zero to < 50% is obtained by
the UC1844 and UC1845 by the addition of an
internal toggle flip flop which blanks the output
off every other clock cycle.

The UC1842/3/4/5 family of control ICs provides the necessary features to implement offline or DC to DC fixed frequency current mode
control schemes with a minimal external parts
count. Internally implemented circuits include
under voltage lockout featuring start-up current
less than 1mA, a precision reference trimmed
for accuracy at the error amp input, logic to

Minidip Plastic
and Ceramic

50-14

DIP-14 Plastic

BLOCK DIAGRAM (Toggle flip flop used only in UC1844 and UC1845)
Vi

(W 6
5(9)

VREF
5V
SOmA

GROUND

VFe

02 _(3_)~--17

1 (1)
COMP o---~~~~.-J
3 (5)

CURRENT
SENSE

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

849

12/86

THERMAL DATA

Rtn J-amb

Thermal resistance junction-ambient

Ceramic
Minidip

Plastic
Minidip

DIP-14
Plastic

SO-14

200°CIW

100°CIW

100°C/W

165°CIW

ELECTRICAL CHARACTERISTICS (Unless otherwise stated, these specifications apply for -55';; Tamb .;; 125°C
for UC184X; -25 .;; T amb ';; 85°C for UC284X; 0';; T amb ';; 70°C for UC384X; VI
15V (Note 5); RT
10K; C T
3.3nF)

=

=

UC184X
UC284X

UC384X

Min. [ TyP.[ Max.

Min. [ Typ. [ Max.

4.95

4.90

Test Conditions

Parameter

=

Unit

REFERENCE SECTION
VREF

Output voltage

Tl.= 25°C

l.IV REF

Line regulation

12V .. Vi" 25V

l.IVREF

Load regulation

1 .. 1o " 20m A

l.IVREF/l.IT

Temperature stability

(Note 2)

10= lmA

Total output variation

Line, Load, Temperature (Note 21

eN

Output noise voltage

10Hz .. I .. 10KHz

Long term stability

Tamb = 125°C. 1000 Hrs (Note 2)

Ise

Output short circuit

5.00

5.05

6

20

V

20

mV

6

25

6

25

mV

0.4

0.2

0.4

mV(C

5.1

4.82

50

-30

5.10

6

0.2
4.9

TJ = 25°C (Note 21

5.00

5.18
50

5

25

-100

-180

-30

52

57

47

0.2

1

V
p.V

5

25

mV

-100

-180

mA

52

57

KHz

0.2

1

%

OSCILLATOR SECTION
15

V4

Initial accuracy

T J = 25°C (Note 61

Voltage stability

12 .. VI .. 25V

Temperature stability

TMIN .. T amb .. T MAX (Note 2)

Amplitude

VpIN 4 peak to peak

47

5

5

%

1.7

1.7

V

ERROR AMP SECTION
V2

Input voltage

Ib

Input bias current

2.45

AVOL

2 .. Vo .. 4V

65

90

65

90

dB

B

Unity gain bandwidth

(Note 2)

0.7

1

0.7

1

MHz

SVR

Supply voltage rejection

12 .. VI" 25V

60

70

60

70

dB

10

Output sink current

Vp'IN 2 = 2.7V

VPIN 1 = 1.1V

2

6

2

6

mA

10

Output source current

VpIN 2 = 2.3V

VpINl = 5V

-0.5

-0.8

-0.5

-0.8

mA

VOUT High

VpIN 2 = 2.3V; R L = 15Kn to ground

5

6

5

6

VOUT Low

V pIN 2 = 2.7V, RL = 15Kn to Pin 8

VpIN 1 = 2.5V

851

2.50

2.55

-0.3

-1

0.7

1.1

2.42

2.50

2.58

V

-0.3

-2

p.A

0.7

V
1.1

V

Fig. 1 - Error amp configuration
2.5"

Error amp can source or sink up to O.5mA

Fig.2 - Under voltage lockout

UC1Bl,2 UCla,,)
UC1B44 UC184S

16V

8.4V

10V

7.6V

During Under-Voltage Lockout, the output driver
is biased to sink minor amounts of current. Pin 6
should be shunted to ground with a bleeder

resistor to prevent activating the power switch
with extraneous leakage currents.

Fig. 3 - Current sense circuit

PEAK CURRENT (Is) IS DETERMINED BY THE FORMULA
ISmax '"

S-i709/1

~
Rs

A SMALL RC FILTER MAY BE REQUIRED TO SUPPRESS SWITCH TRANSIENTS.

853

Fig. 10 - Shutdown techniques

1 COMP

5-711211

Shutdown of the UC1842 can be accomplished
by two methods; either raise pin 3 above 1V or
pull pin 1 below a voltage two diode drops above
ground. Either method cause the output of the
PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that
the output will remain low until the next clock

cycle after the shutdown condition at pins 1 and/
or 3 is removed. In one example, an externally
latched shutdown may be accomplished by
adding an SCR which will be reset by cycling
VI below the lower UVLO threshold. At this
point the reference turns off, allowing the SCR
to reset.

Fig. 11 - Off-line flyback regulator
RI SJl

117VAC

D.

DI

USC94S

el1

lW

4700,uF
R2
56Kfl

' - - - - '_ _ _....._---{) COMMON

2w

,.~_--___,.----o 12VJQ.3A

R4

471HI.

RJ

r------1-----0COMMON

20K!}

2
RS 1501(0

'-----*'=o:+----0- 12V/O'JA

..LC:S OPF
600V

R7 22A

05

R81KQ

O.Q1,uF

lNJ613
Rl3

RIO

20Kfi

o.S5n

'"

2.7Kll
2w

,w

5. Output Voltage:
A. +5V, ±5%: 1A to 4A load
Ripple voltage: 50mV pop Max.
B. +12V,±3%: 0.1AtoO.3Aload
Ripple voltage: 100mV P-P Max.
C. -12V,±3%: 0.1AtoO.3Aload
Ripple voltage: 100mV P-P Max.

Power Supply Specifications
1. Input Voltage:

95VAC to 130VAC
(50Hz/60Hz)
2. Line Isolation:
3750V
3. Switching Frequency:
40KHz
4. Efficiency @ Full Load: 70%
855

aB.

ULN2tJO'tA ULN2003A
ULN2002AULN2004A

SEVEN DARLINGTON ARRAYS
•

SEVEN DARLINGTONS PER PACKAGE

•

OUTPUT CURRENT 500mA PER DRIVER
(600mA PEAK)

ULN2002A

14-25V PMOS

•

OUTPUT VOLTAGE 50V

ULN2003A

5V TTL, CMOS

•

INTEGRAL SUPPRESSION DIODES FOR
INDUCTIVE LOADS

ULN2004A

6-15V CMOS, PMOS

•

OUTPUTS CAN BE PARALLELED FOR
HIGHER CURRENT

•

TTL!CMOS/PMOS/DTL COMPATIBLE
PUTS

•

INPUTS PINNED OPPOSITE OUTPUTS TO
SIMPLIFY LAYOUT

ULN2001A

General purpose, DTL, TTL,
PMOS, CMOS

These versatile devices are useful for driving a
wide range of loads including solenoids, relays
DC motors, LED displays filament lamps, thermal printheads and high power buffers.

IN-

The U LN200 1A/2002A/2003A and 2004A are
supplied in 16 pin plastic DIP packages with a
copper leadframe to reduce thermal resistance.
They are available also in small outline package
(SO-16) as U LN2001 D/2002D/2003D/2004D.

The ULN2001A, ULN2002A, ULN2003A and
ULN2004A are high voltage, high current darlington arrays each containing seven open collector darlington pairs with common emitters.
Each channel is rated at 500mA and can withstand
peak currents of 600mA. Suppression diodes are
included for inductive load driving and the inputs are pinned opposite the outputs to simplify
board layout.
The four versions interface to all common logic
families:

DIP-16 Plastic (0.25)

SO-16

ORDERING NUMBER:
ULN2001A!2A/3A/4A (DIP-16)
ULN2001 D/2D/3D/4D (SO-16)

ABSOLUTE MAXIMUM RATINGS
Vo

Vln
Ie
Ib
Tamb
T stg

TJ

Output voltage
Input voltage (for ULN2002A/D - 2003A/D - 2004A/D)
Continuous collector current
Continuous base current
Operating ambient temperature range
Storage temperature range
Junction temperature

857

50
30
500
25
-20 to 85
-55 to 150
150

12/86

THERMAL DATA
Rth j-amb

DIP-16

Thermal resistance junction-ambient

ELECTRICAL CHARACTERISTICS
Parameter
ICEX

Output leakage cu rrent

max

(Tamb

= 25°C unless otherwise specified)

Test conditions
VCE = 50V
Tamb = 70°C
Tamb = 70°C
for ULN2002A
VCE = 50V
for ULN2004A
VCE = 50V

Max.

Unit Fig.

VCE = 50V

50
100

f.lA
f.lA

1a
1a

Vj =6V

500

f.lA

1b

Vj =1V

500

f.lA

1b

0.9
1.1
1.3

1.1
1.3
1.6

V
V
V

2
2
2

0.82
0.93
0.35
1

1.25
1.35
0.5
1.45

mA
mA
mA
mA

3
3
3
3

f.lA

4

VCE(sat)

Collector-emitter
satu rati on vol tage

Ic = 100mA
Ic = 200m A
Ic = 350mA

18 = 250 f.lA
18 = 350 f.lA
18 = 500 f.lA

Ij(on)

Input current

for ULN2002A
for ULN2003A
for ULN2004A
Vj=12V

Vj = 17V
Vj = 3.85V
Vj =5V

Ij (off)

Input current

Tamb = 70°C

IC = 500 f.lA

Vj(on)

Input voltage

for U LN2002A
VCE = 2V
for ULN2003A
VCE =2V
VCE = 2V
VCE=2V
for U LN2004A
VCE=2V
VCE=2V
VCE=2V
VCE =2V

hFE

DC forward cu rrent gai n

Cj

Input capacitance

tpLH

Tu rn-on delay time

tpHL
IR

VF

SO-16

for ULN2001A
VCE=2V

Min.

50

Typ.

65

Ic=300mA

13

V

5

Ic=200mA
Ic=250mA
Ic =300 mA

2.4
2.7
3

V
V
V

5
5
5

Ic=125mA
Ic =200 mA
Ic=275mA
Ic=350mA

5
6
7
8

V
V
V
V

5
5
5
5

-

2

Ic = 350 mA

1000
15

25

pF

-

0.5 Vj to 0.5 Va

0.25

1

f.ls

-

Turn-off delay time

0.5 Vj to 0.5 Va

0.25

1

f.ls

-

Clamp diode leakage
current

VR = 50V
Tamb =70°C

50
100

f.lA
f.lA

6
6

Clamp diode forward
voltage

IF=350mA

2

V

7

VR = 50V
1.7

859

91.
50V - 1.5A QUAD DARLINGTON SWITCHES
•

35V measured at 100mA. The ULN2064B,
ULN2066B, ULN2068B and ULN2070B contain
integral suppression diodes for inductive loads
have common emitters. The ULN2074B and
ULN2076B feature isolated darlington pinouts
and are intended for applications such as emitter
follower configurations. Inputs of the ULN2064B,
ULN2068B and ULN2074B are compatible with
popular 5V logic families and the ULN2066B
and ULN2076B are compatible with 6-15V CMOS
and PMOS. Types ULN2068B and ULN2070B
include a predriver stage to reduce loading on
the control logic.

OUTPUT CURRENT TO 1.5A EACH DARLINGTON

•

MINIMUM BREAKDOWN 50V

•

SUSTAINING VOLTAGE AT LEAST 35V

•

INTEGRAL SUPPRESSION DIODES
(ULN2064B, ULN2066B, ULN2068B AND
ULN2070B)

•

ISOLATED DARLINGTON
(ULN2074B, ULN2076B)

•

VERSIONS COMPATIBLE WITH
POPULAR LOGIC FAMILIES

PINOUT
ALL

Designed to interface logic to a wide variety
of high current, high voltage loads, these devices
each contain four NPN darlington switches
delivering up to 1.5A with a specified minimum
breakdown of 50V and a sustaining voltage of

Powerdip

12 + 2 + 2

ABSOLUTE MAXIMUM RATINGS
V CEX
V CE (sus)

10
VI

II
Vs

Output voltage
Output sustaining voltage
Output current
Input voltage
for ULN2066B/70B/74B/76B
for ULN2064B/68B
Input current
Supply voltage for U LN2068B
for ULN2070B
Power dissipation: at Tamb = 90°C
at Tamb = 70°C
Operating ambient temperature range
Storage temperature

CONNECTION DIAGRAM (Top view) and

,

,.

C

C

2

15

NC

B

3

,.

B

K

50
35
1.75
30
15
25
10
20
4.3
1
-20 to 85
-55 to 150

V
V

A
V
V

mA

V
V
W
W

°c
°c

ORDERING NUMBERS

,.

C

15

,.

"

,.

,

E

2

15

B

3

,.

GNd 4

13 GNO

GND

4

13

GNO

SUB ii

13

SUB

GNO 5

12 GNO

GNO

5

12

GNO

5UB

12

SUB

•

11

C

7

10

K

•

B

5

11

11
NC

NC

7

10

E

1

10

5 - 5 ~ 2J

ULN2064B
ULN2066B

ULN2068B
ULN2070B

861

ULN2074B
ULN2076B

12/86

SCHEMATIC DIAGRAM

..;---+---0 c
I
I

*
I

.....
I

5- 59 2 2

ULN2068B : RIN = 2.5 kn
ULN2070B : RIN = 11.6 kn

ELECTRICAL CHARACTERISTICS
Tamb = 25°C unless otherwise specified)

leEX

5V for ULN2068B, Vs

Test conditions

Parameter
Output leakage current

(Vs =

for ULN2068B-ULN2070B
Ie = 100mA
Vi = O.4V

V CE(sat) Collector-emitter
satu ration voltage

for ULN2068B
le=500mA
Ie = 750mA
le= 1A
Ie = 1.25A
for ULN2070B
Ie = 500mA
Ie = 750mA
Ic = 1A
Ic = 1.25A

Input current

Vi(on)

Input voltage

Is

Supply current

for
for
for
for

ULN2068B
ULN2068B
ULN207UB
ULN2070B

Turn-on delav time

0.5Vj to 0.5Vo

tpHL

Turn-off delay time

0.5Vj to 0.5Vo

IR

Clamp diode leakage
current
Clamp diooe forward
voltage

Typ.

12V for ULN2070B,

Max.

Unit.

Fig.

100
500

JlA
JlA

1

V

2

35

Vi
Vi
Vi
Vi

=
=
=
=

2.75V
2.75V
2.75V
2.75V

1.1
1.2
1.3
1.4

V
V
V
V

Vi
Vi
Vi
Vi

=
=
=
=

5V
5V
5V
5V

1.1
1.2
1.3
1.4

V
V
V
V

Vi
Vi
Vi
VI

=
=
=
=

2.75V
3.75V
5V
12V

550
1000
400
1250

JlA
JlA
JlA
JlA

2.75
5

V
V

6

mA

4.5

mA

Ie -1.5A
VeE - 2V
for ULN2068B
for ULN2U70B
for ULN2068B
Ie = 500mA
Vi = 2.75V
for ULN2070B
IC = 500mA
Vi = 5V

tpLH

VF

Min.

for ULN2U68B-ULN2070B
VeE = 50V
VeE = 50V
Tamb = 70°C

V CE(sus) Collector-emitter
sustaining voltage

li(on)

Rs = 900n
Rs = 3.4 KHn

2

4

5

8
1

JlS

1.5

JlS

for ULN2068B-ULN2070B
VR = 50V
VR = 50V
Tamb = 70°C

50
100

JlA
/J A

6

IF = 1A
IF = 1.5A

1.75
2

V
V

7

Ic = 1.25A

863

TEST CI RCUITS
Fig.2

Fig.3

OPEN

OPEN

5- 5927

Fig. 4

OPEN

OPEN

Fig.6

VR

iJA
'R

OPEN

5-1986

5-5727
5-1987

Fig.7

Fig. 8

865

Vs

OPEN

1

MOUNTING INSTRUCTIONS
The Rthj-amb can be reduced by soldering the GND pins to a suitable copper area of the printed circuit
board (Fig. 14) or to an external heatsink (Fig. 15).
The diagram of figure 16 shows the maximum dissipable power Ptot and the Rth j-amb as a function of
the side "Q" of two equal square copper areas having a thickness of 35,u (1.4 mils).
During soldering the pins temperature must not exceed 260°C and the soldering time must not be longer
than 12 seconds.
The external heatsink or printed circuit copper area must be connected to electrical ground.

Fig. 14 - Example of P.C. board copper area which is
used as heatsink.
~OPPER

AREA 35>"

Fig. 15 - External heatsink
mouting example

THICKNESS

p. C. BOARD

"ot

Fig. 16 - Maximum dissipable power and junction to
ambient thermal resistance
vs. side "Q"
G-1558

Fig. 17 - Maximum allowable power dissipation vs.
ambient temperature

RIh

(WI

( -C/W)

80

I\,
Rth j-amb

t'-..

•

-

l"- t--

..-~ r.-/ Ptot

r-

,

(lamb"" 70·C)

10

1
I
'0

10

30

40

I (mm)

-50

867

50

100

Tambrt:l

PRELIMINARY DATA

80V - 1.5A QUAD DARLINGTON SWITCHES
•

and U LN2071 B contain integral suppression
diodes for inductive loads and have common
emitters; the ULN2075B and U LN2077B feature
isolated darlington pinouts and are intended for
applications such as emitter follower configurations. Inputs of the ULN2065B, ULN2069B
and ULN2075B are compatible with popular 5V
logic families and the ULN2067B, ULN2071 Band
U LN2077B are compatible with 6-15 CMOS and
PMOS. The ULN2069B and ULN2071B include
a predriver stage to provide extragain, reducing
the load on control logic.

OUTPUT CURRENT TO 1.5A EACH DARLINGTON

•

MINIMUM BREAKDOWN 80V

•

SUSTAINING VOLTAGE AT LEAST 50V

•

INTEGRAL SUPPRESSION DIODES
(ULN2065B, ULN2067B, ULN2069B AND
ULN2071B)

•

ISOLATED DARLINGTON
(ULN2075B AND ULN2077B)

•

VERSIONS COMPATIBLE WITH
POPULAR LOGIC FAMILIES

PINOUT
ALL

Designed to interface logic to a wide variety
of high current, high voltage loads, th;ese devices
each contain four NPN darlington switches
delivering up to 1.5A with a specified minimum
breakdown of 80V and a sustaining voltage of
50V. The ULN2065B, ULN2067B, ULN2069B

Powerdip

12 + 2 + 2

ABSOLUTE MAXIMUM RATINGS
VCEX
VCE (sus)

10
Vi
Ii
Vs
Ptot
Tamb
T stg

Output voltage
Output sustaining voltage
Output current
Input voltage for ULN2075B - 2077B
for ULN2067B - 2071B
for U LN2065B - 2069B
I nput cu rrent
Supply voltage for ULN2069B
for U LN2071 B
Power dissipation: at T pins = 90°C
at Tamb = 70°C
Operating ambient temperature range
Storage temperature

CONNECTIONS DIAGRAMS (Top view) and

80
50
1.75
60
30
15
25

10
20
4.3
1
-20 to 85
-55 to 150

ORDERING NUMBERS

K

'1t--r~-i4~-II16

C

1t---r~-i4~-II16

C

2

15

NC

1S

B

C

3

\4

B

GNO 4

13

GND

GNO

4

13

GND

GNO 5

12 GNO

GND

5

12

GNO

B

•

11

C

7

10

N C

7

10

K

.I\--------~-+---II

ULN2065B
ULN2067B

NC

V
V
A
V
V
V
mA
V
V
W
W
°c
°c

1

"

5 - 5923

5-5925

ULN2069B
ULN2071B

ULN2075B
ULN2077B

869

12/86

SCHEMATIC DIAGRAM

r-~--oK

~---+----o

B

c

I
I

I

--*
I
I

5-59ZZ

ULN2069B : RIN = 2.5 kn,
ULN2071 B : RIN = 11.6 kn,

Rs = 900n
Rs = 3.4 kn

ELECTRICAL CHARACTERISTICS (Vs = 5V for ULN2069B, Vs

12V for ULN2071B,

Tamb = 25°C unless otherwise specified)

Test conditions

Parameter
ICEX

Output leakage current

for ULN2069B-ULN2071B
VCE = 80V
VCE = 80V
Tamb = 70°C

V CE(sus) Collector-emitter
sustaining voltage

for ULN2069B-ULN2071B
Ic = 100mA
Vi = 0.4V

V CE(sat) Collector-emitter
saturation voltage

for ULN2069B
Ic=500mA
Ic = 750mA
Ic = 1A
Ie = 1.25A
Ic= 1.5A
for ULN2071B
Ic = 500mA
Ic = 750mA
Ic= 1A
I c =1.25A
Ic= 1.5A

li(on)

Input current

Vi(on)

I nput voltage

Is

Supply current

for
for
for
for

Typ.

Max.

Unit.

Fig.

100
500

JlA
JlA

1

V

2

2

50

Vi =
Vi=
Vi =
Vi =
Vi =

2.75V
2.75V
2.75V
2.75V
2.75V

1.1
1.2
1.3
1.4
1.5

V
V
V
V
V

Vi
Vi
Vi
Vi
Vi

=
=
=
=
=

5V
5V
5V
5V
5V

1.1
1.2
1.3
1.4
1.5

V
V
V
V
V

ULN2069B Vi
ULN2069B Vi
ULN2071B Vi
ULN2071B Vi

=
=
=
=

2.75V
3.75V
5V
12V

550
1000
400
1250

JlA
JlA
JlA
JlA

4

2.75
5

V

5

6

mA

4.5

mA

VeE - 2V
for ULN2069B
for ULN2071B

I c -1.5A

for ULN2069B
Ic = 500mA
Vi = 2.75V
for ULN2071B
Ic = 500mA
Vi = 5V

tpLH

Turn-on delay time

0.5Vi to 0.5Vo

tpHL

Turn-off delay time

0.5Vi to 0.5Vo

IR

Clamp diode leakage

VF

Min.

8
1

JlS

1.5

JlS

current

for ULN2069B-ULN2071B
VR = 80V
VR = 80V
Tamb = 70°C

50
100

JlA
JlA

6

Clamp diode forward
voltage

IF= 1A
IF= 1.5A

1.75
2

V
V

7

Ic= 1.25A

871

TEST CIRCUITS
Fig.2

Fig.3

OPEN

Fig.6

OPEN

Fig.4

OPEN

OPEN

5 - 5727

5-1986
5 -1987

Fig.7

s- 5928

Fig. 9 - Input current as a
function of input voltage

Fig. 10 - Input current as a
function of input voltage

,;
(mAl

1.5

2.0

25

3.0

3.S

4.0

4.5

Fig. 11 - Collector current as
a function of input current
Ie

I---+c.~hd--+--+--

5.0 Vi(V)

(A'

~-+---+-~--+-~-+--~~

1.0

873

1.0

3.0

II (mA)

II.
EIGHT DARLINGTON ARRAYS
EIGHT DARLINGTONS WITH COMMON
• EMITTERS
CURRENT TO 500mA
• OUTPUT
OUTPUT
TO 50V
• INTEGRALVOLTAGE
SUPPRESSION
DIODES
• VERSIONS FOR ALL POPULAR
LOGIC
• FAMILIES
•

OUTPUT CAN BE PARALLELED

•

INPUTS PINNED OPPOSITE OUTPUTS TO
SIMPLIFY BOARD LAYOUT

designed for general purpose applications with a
current limit resistor; the ULN2802A has a
10.5Kn input resistor and zener for 14-25V
PMOS; the ULN2803A has a 2.7Kn input
resistor for 5V TTL and CMOS; the ULN2804A
has a 1O.5Kn input resistor for 6·15V CMOS and
the ULN2805A is designed to sink a minimum
of 350mA for standard and Schottky TTL where
higher output current is required.
All types are supplied in a 18-lead plastic DIP
with a copper lead from and feature the con·
venient input-opposite-output pinout to simplify
board layout,

The U LN2801 A -U LN2805A each contain eight
darlington transistors with common emitters and
integral suppression diodes for inductive loads.
Each darlington features a peak load current
rating of 600mA (500mA continuous) and can
withstand at least 50V in the off state. Outputs
may be paralleled for higher current capability.

DIP-18 Plastic
(U7P2)

Five versions are available to simplify interfacing
to standard logic families: the ULN2801A is

CONNECTION DIAGRAM
(top view)
IN 1

1

>-____--~118

OUT 1

IN

2

2

>-____-I-~117

OUT 2

IN

3

3

>----.----4-1116

OUT 3

IN 4

4

>-____

-I-~115

OUT 4

IN 5

5

>-____-I-~114

OUT 5

IN 6

>-____---l-~113

OUT 6

IN 7

'>-_._--+---1112

OUT 7

">--...-~-Illl

OUT 8

IN 8

8

GND
50-349011

875

12/86

THERMAL DATA
Rth j-amb

max

Thermal resistance junction-ambient

ELECTRICAL CHARACTERISTICS (Tamb =
Parameter
I CEX

Output leakage current

VCE(sat) Coliector-eJIlitter
saturation voltage
li(on)

Input current

25°C

Min.

Typ.

V CE = 50V
T amb = 70°C
V CE = 50V
Tam"b= 70°C
for ULN 2802A
V CE = 50V
Vi =6V
for U LN 2804A
V CE = 50V
Vi = 1V
Is = 250)JA
Is = 350)JA
Is = 500)JA

for ULN 2802A Vi
for ULN 2803A Vi
for ULN 2804A Vi
Vi
for ULN 2805A Vi

li(off)

Input current

T amb = 70°C

Vi(on)

Input voltage

for ULN 2802A
V CE= 2V
for ULN 2803A
V CE = 2V
V CE = 2V
V CE= 2V
for ULN 2804A
V CE= 2V
V CE= 2V
V CE= 2V
V CE = 2V
for ULN 2805A
V CE = 2V

=
=
=
=
=

17V
3.85V
5V
12V
3V

I C =500)JA

50

Fig.

50
100

)JA
)JA

1a
1a

500

)JA

1b

)JA

1b

1.1
1.3
1.6

V
V
V

2

0.82
0.93
0.35
1
1.5

1.25
1.35
0.5
1.45
2.4

mA
mA
mA
mA
mA

3

)JA

4

65

Ic=300mA

13

V

Ic = 200 mA
Ic = 250 mA
Ic=300mA

2.4
2.7
3

V
V
V

Ic=125mA
Ic=200mA
Ic=275mA
Ic=350mA

5
6
7
8

V
V
V
V

Ic=350mA

2.4

V
-

2

15

25

pF

-

1

)Js

-

Ci

I nput capacitance

tpLH

Turn-on delay time

0.5 Vi to 0.5 Vo

0.25

tpHL

Turn-off delay time

0.5 Vi to 0.5 Vo

0.25

IR

Clamp diode leakage

V R = 50V
T amb = 70°C

Clamp diode forward
voltage

Unit

500

DC forward current gain

VF

Max.

0.9
1.1
1.3

hFE

current

°C/W

unless otherwise specified)

Test conditions

Ic=100mA
Ic = 200 mA
Ic = 350 mA

55

for ULN 2801A
V CE= 2V
Ic = 350 mA

1000

V R = 50V
1.7

IF = 350 mA

877

5

1

)JS

-

50
100

)JA
)JA

6

2

V

7

Fig. 8 - Collector current as
a function of saturation
voltage
G-UH
"

(mA J

Fig. 9 - Collector current as
a function of input current
G-"21

,

P,

I

(mA

(W

I

Fig. 10 - Allowable average
power dissipation as a function of ambient temperature
G-4'24

'I--

2.0
.00

V

/

'0

~

.,;,t"p>-/

'00

200

0.5

1/

20 0

plEVlcl LI~IT

1\

1.5

/

~I

.<:...

\~

/

1.0

1/
/.

\

0.5

REQUIRED
INPUT CURRENT
1/ f-- MAX.

/

.....~/

1/

R.~~

~

/

',J,ff-I,,>
/ "/-1/h"

f-

\

\

\

/
200

1.0

Fig. 11 - Peak collector current as a function of duty
cycle

'0

'00

Fig. 13 - I nput current as a
tunction of input voltage
(for ULN 2802A)
6-"121

Fig. 12 - Peak collector current as a function of duty
cycle

'e

i I

(mA I

,"0

'00

)..

'\

1\\\

REeOM"ENO:~~ ~M-----'+-------'

L----<:~--___1

1 GROUNO
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

885

12/86

lB.

ADVANCE DATA

AN INTELLIGENT HIGH VOLTAGE DUTY CYCLE
CONTROLLER FOR D.C. MOTOR CONTROL
AND INDUCTIVE LOAD DRIVER APPLICATIONS
•

CONTROL CIRCUIT AND POWER ON ONE
CHIP

•

3A OUTPUT CURRENT

•

INTEGRATED 450V POWER DARLINGTON

•

PROGRAMMABLE DRIVER CURRENT

The VB100 is mounted in all-lead Multiwatt®
plastic power package and requires very few
external components.
The VB100 can be used as a D.C. motor controller
and driver or as a high voltage inductive load
driver, the output voltage duty cycle is adjusted
as a function of the input control Voltage, at a
frequency set by a stable internal sawtooth
generator.

• SWITCHING FREQUENCY UP TO 100KHz
•

THERMAL SHUTDOWN

•

COMPARATOR INPUT PROTECTION

•

HIGH IMPEDANCE DIFFERENTIAL INPUTS

•

DUTY CYCLE
WITHIN 1.5%

•

MINIMUM EXTERNAL COMPONENTS

CONTROL

A built-in thermal shutdown circuit switches off
the power darlington whenever the junction temperature exceeds an internally set value.

LINEARITY

The VB100 is an intelligent duty cycle controller
with a high Voltage, high current open collector
darlington output.
Multiwatt-11 ®

Features of the device include programmable
driver current, thermal protection, high impedence differential input, integrated protection
at comparator inputs and switching frequency
up to 100KHz.

ORDERING NUMBER: VB100

BLOCK DIAGRAM

+300V

§fril~rf Vs <>-----...,.-.---=]-----,
SUPPLY

+5

BIAj"-S-O+++-J
A H----++-~::..J

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

887

12/86

1-

aB.
HIGH CURRENT, HIGH SPEED, HIGH POWER TRANSISTOR
The BU R50 is a silicon multiepitaxial planar NPN transistor in modified Jedec TO-3 metal
case, the BU R50S is the same type in Jedec TO-3 metal case, intended for use, in switching
and linear applications in military and industrial equipment.

ABSOLUTE MAXIMUM RATINGS
Collector-base voltage (I E = 0)
Collector-emitter voltage (I B= 0)
Emitter-base voltage (I c=O)
Collector current
Collector peak current (t p=1 0 ms)
Base current
Total power dissipation at T case~25"C
Storage temperature
Junction temperature

:
4

200

v

125

V
V
A
A
A
W
"C
"C

10

70
100
20
350

-65 to 200
200

INTERNAL SCHEMATIC DlAGR:

MECHANICAL DATA

Dimensions in mm
Collector connected to case

Collector connected to case

.-4.1,280
c ~··oda6'i

889

10/84

ELECTRICAL CHARACTERISTICS (continued)
Parameter
ton

Turn-on time
(fig. 2)

ts

Storage time
(fig. 2)

If

Fall time
(fig. 2)

Min. Typ. Max.

Test conditions
I c =70A
Vcc=60V

Clamped Esib
Q)lIector current
(fig. 1)

0.5 1.2

I B1 =7A

I c =70A
I B2 =-7A

Unit
~s

0.82

2

~s

0.1

0.5

~s

I B1 =7A
V cc=60V

70

VClam8=125V
L=5 O~H

A

... Pulsed: pulse duration =300 ~s. duty cycle :52%

Safe operating areas

Derating curves
(j,

I

I

b-i

I

f+--

I

~~

I

,~j'

----W-'

-n-t

"

RWEf,I~~~Ep~~E

::!I

10"

,

I
, 68

1111
6

•

10

I
102

) 52

11

r-t-.

'tE
Collector current
(fig. 1)

* Pulsed: pulse duration

B1

Min. Typ. Max.

=SA

I B1 =SA
V cc=100V

0.3S

1

fJ.S

0.9

2

fJ.S

0.24 0.6

fJ.S

A

SO

V c,am8=200V
L =S OfJ.H

Unit

=300 fJ.S, duty cycle ""2%

Safe operating areas

Derating curves
G 3902

Ie

8

(A)

,

8

,
10' 8

I

IcMix pu~:lD

PULSE OPER~TK)N ,.

::1

: Ic~~_~9fH.

,
10

DCCf'ERATION

o'~sb

i lXI~s" I-~+
.........

!l~

Oms

1\

"
4~._
,

Ims

I
I

i,

!

8

ii'

~~TWlvtfu~

\

j

i

I

8

6~

'~

fit:,;
, 5'

\

,

,1----

I II
,

10

~

68

la'

It
,

68

o

veE (V)

897

50

100

150

Tease ('e)

Base-emitter saturation voltage

Saturated switching characteristics
G 3897

G 3896

t

f=:
(}JS )8
f-----

V8E(sat )

I

(V)

- -

~t=

hFE "10

+

1.5

r--

~~
125"

-

I

4

.-

4

10- 1

f-

,

68

1

f-

10

I

-

I'-.

.....

'c---- I"-

,.

6 S

_.--

i

-- r-- ~
-- -- - r---- .

S=--

'/

,...-

o

......:.

/j

/L

----

0.5

t~-I

,

I

-30'C

-iT

f--

Vee "'OOV -Tease :;:25°C~- -

hFE "'0

.....
.....

ton _

,./

tf

,./fo'"

~

,

6 ,

6

le(A)

Saturated switching characteristics

6 8
Ie (A)

S

Transition frequency
G-3899

t

fT

O)JS) B

(MHz)

veE "5V
f:;:lMHz

20

-....r"I
V
10

./

./

6

10

10-'

899

S

6

S

Ie

(A)

II.

BUR52

HIGH CURRENT, HIGH SPEED, HIGH POWER TRANSISTOR
The BUR 52 is a silicon multiepitaxial planar NPN transistor in modified Jedec TO-3
metal case, intended for use in switching and linear applications in military and industrial equipment.

ABSOLUTE MAXIMUM RATINGS
Collector-base voltage ( I E = 0)
Collector-emitter voltage ( I B = 0)
Emitter-base voltage (I c= 0)
Collector current
Collector peak current (t p=1 0 ms)
Base current
Total power dissipation at T case:s:25°C
storage temperature
Junction temperature

INTERNAL SCHEMATIC

350
V
250
V
10
V
60
A
80
A
16
A
350
W
-65 to 200°C
200
°C

DlAGR~~:

MECHANICAL DATA

Dimensions in mm

Collector connected .to case

4.2


Chllector current
(fig. 1)

Unit

1.2

2

j.lS

0.20

0.6

j.lS

40

V clam =250V
L =5 OJ.lH

A

• Pulsed: pulse duration =300 j.lS, duty cycle ~2%

Derating curves

Safe operating areas

Ill' 8

,

4

I

leW:x ~k!d

PLl.SE, a

+- -+-

I

ATION'

fJS

IX)

leMA)( "1-"'1-

-

-- --

VS

'"

lms

~

D OPERATION
10

G. J665

G 3883

Ie ,
(A) ,

,
8

'--

10

~~

ms

...:: ,~(

" ....... . . ..:::~O

\

~JfII.JtEPU.~

\

........

0.5

•

- f-- 4

• B

2

4

6 B

......

N~-I-

~
2

...... ......
,~~

t-...~~_:::~

\
10·'a

.......

2

4

I

6 8

o

10

903

50

100

i'..

Saturated switching characteristics

Base-emitter saturation voltage
G-3696

G 3897

VBE (sal)I--+-++++++++----f--++lM-fIl--I-f-f-+II-I/1l

hFE = 10
Vee =1001/
Tease :25°C

(V)

hFE 010 +++H+rj--+-++t+++++--+-+ItIt--'lfttl
1,5

I""'"" r-;;

~--~~~H+il~~o~·-+~++~~-4~,~~

r-

1--+-+++++ ~J<'4--++l+l-l-l+----1-JV'-E-l-H+Hl
11"~

I-- t---,

---

0.5

"'-

17

".........

4

4

6 8

,

6 8

10

1

....

Ion

V

If

l.--'

6

8

6 8
Ie (A)

10

Transition frequency

G 3898

~~

hFE

-

=10
Vee =100V

"
i

---4
i

i

I

!

G 3899

E

fT
lIcE =5V

(MHz)

Tcase=125°C

~

f:1 MHz

!

; II] ~
!
II

I

1

20

''KJ

: i:

:

i

'

1

....

-+-

::-:-t
- ..

.;-

+cy

--~

I\..

'''';''''

!

"'-

I

II

"....... > i
I j II

!Ion

'"

68

le(A)

Saturated switching characteristics

~-

.

............ .........,

I--+-t-t'i"mff--~-- "-

10- 1

Is

/.i

-,

,/1

10

JhVi

./

./

'"

~

1,If

10

I

o
Ie (A)

6

10- 1

905

8

6

8

Ie

(A)

II.

ADVANCE DATA

ADVANCE DATA
HIGH VOLTAGE POWER SWITCH
The BUW22, BUW22A are silicon miltiepitaxial mesa PNP transistor, in Jedec TO-3, metal
case, particularly intended for high voltage, fast switching applications.
The BUW22P, BUW22AP are mounted in TO-220 plastic package.

ABSOLUTE MAXIMUM RATINGS
VCES
V CEO
VEBO
Ic
ICM
IB
IBM

Ptot
Tstg

Tj

Collector-emitter voltage (V BE = 0)
Collector-emitter voltage (I B = 0)
Emitter-base voltage (lc = 0)
Collector current
Collector peak current (t p ..;;; 10ms)
Base current
Base peak current (t p ..;;; 101T)s)
Total power dissipation at Tcase ..;;; 25°C
Storage temperature
Junction temperature

BUW22/P

BUW22A/P

-400V
-350V
-5V

-450V
-400V
-7V

-6A
-SA
-2A
-4A
(TO-3) 75W
(TO-220) 60W
-65 to 175°C
-65 to 150°C
175°C
150°C

INTERNAL SCHEMATIC DIAGRAM

MECHANICAL DATA

.~:

Dimensions in mm

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

9ID

1W~

G-5523

Safe operating areas
(BUW22AP - BUW22P)

G-5524

Safe operating areas
(BUW22 - BUW22A)

Ie 8
6
(A)
4
2

10

,

Ie MAX PULSED
B
6

4

10ms

Ie M,A\CONT.

I

2

'PULSE OPERATI'ONf*1

II

lms 10}JS

\.

D e OPERATION
8
6
4

1\

\

,
\.i\
\.

~

*fOR SINGLE NON
REPETITIVE PULSE

I

8UW22- r-8UW22A I-2

4

6 8

10

909

I

I

Base-emitter saturation voltage

Base-emitter on voltage

G

V8E(sal )

G 5530

5521

1111

(V)

III

(V)

TCaMa-40·C i'...
2S'C
125'C

-- -_........

...

~

...

.........

-

0.5

1111
1111

V8E(on )

...
"" ""

can '-~r.g ........

12S'C ~ ~I

~II"

,l'il)

\

r\.

....'"/ ,

~

---

0.5

hFE"'

o

,

--

VCE .2V

o
10'

I
(1")

10'

IC (A)

Switching times resistive load (test
circuit fig. 1)
G - 5551

'/0

VCC .-250V
hFE .5
181 .1 82
Tcase a25-C

"....

Switching times percentage variation
vs. T case
G -5531
RESISTIVE
IC = 3A

180

160

Is

-

I

tt

....

--

10'

,~

.."....

,

'c(A)

911

-

7

/" .... ..-:::: .."..
/
~~

120

[t.. I-'"

100

o

LOAD

o

25

50

75

'!II

/
Ion

I.

........

TEST CI RCUITS
Fig. 1
-Vee

Vi

5-7019

Fig. 2

- 6V

1.5 mH

5-7020

913

2.2

n
t-I.....-"""'. -Vee

1-

aB.
HIGH VOLTAGE POWER SWITCH
• FAST SWITCHING APPLICATIONS
• INDUSTRIAL APPLICATION
The BUW32/A. BUW32P/AP and SGSIW32/A are silicon multiepitaxial mesa PNP transistors mounted respectively in TO-3 metal case, SOT-93 plastic
package and ISOWATT218 fully isolated package.

TO-3

50T·93 (T0-218)

150WATT218
INTERNAL SCHEMATIC DIAGRAM

ABSOLUTE MAXIMUM RATINGS

TO-3
SOT·93
ISOWATT218

V CES
V CEO
V EBO
Ic
Is

Collector-emitter voltage (V BE = 0)
Collector-emitter voltage (lSE = 0)
Emitter-base voltage (lc = 0)
Collector current
Base current

VI so
Ptot
T stg
Tj

Isolation voltage (DC)
Total dissipation at Tc ~ 25°C
Storage temperature
Max. operating junction temperature

BUW32
BUW32P
SGSIW32

BUW32A
BUW32AP
SGSIW32A

-400
-350
-5

-450
-400
-7

TO-3
125
-65 to 175
175
915

-10
- 5
SOT-93

V
V
V
A
A

ISOWATT218
4000
V
105
50
W
-65 to 150 -65 to 150°C
150
150
°C
11/86

THERMAL RESISTANCE OF THE ISOWATT218
The junction to case thermal resistance of 2.5
°CIW for the ISOWATI218 package may seem
quite high at first glance but if compared to
a conventional SOT -93 (TO-218) package
with a 0.1 mm mica insulating washer, the differences are marginal. The 0.1 mm isolating
washer gives 1500V to 2000V DC isolation
for the SOT-93 package, SGS guarantee
4000V DC isolation for the ISOWATT 218.

Fig. 1

The comparison in fig. 1 shows the dynamic
thermal resistance of both devices mounted
using a thermal compound. The test illustrate
that the ISOWATT218 has an Rth very close
to that of conventional SOT -93 (TO-218) and
any small increase is more than compensated
for by the convenience of the ISOWATT218
package. The collector to heatsink capacitance of the ISOWATI218 is typically 17pF.

103,--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'O"'u:..:..,,'-"'92......,
Zth
(OCM)

101

THERMAL IMPEDANCE - TIME
WITH A SMALL HEATSINK
1$(}.oiATT218

x

SOT-93

•

mica thickness - 0.1 mm
10

li)3
TIME(secl

Safe operating areas

DC current gain

Safe operating areas

Tc.;lY'~125·C

5'C

l-~o"Cl

"

r
,

~

I

t:-T

'

1~
...

•

I

,,'
917

...............

-+-. , ' :--...
- ~:5t-'1-

!

.... -.. F£

-

~

t-

T

II

-- .-.

r-fT ~1
-Ie

(A)

TEST CIRCUITS
Fig. 1

-Vee

Vi

Fig. 2
- 6V

1.5mH

0
100/olF
I'6V

02
Vi

+6V

5-7020

919

2.211

-vee

BUW42/BUW42A
BUW42P/BUW42AP
SGSIW42/SGSIW42A

HIGH VOLTAGE POWER SWITCH
• FAST SWITCHING APPLICATIONS
• INDUSTRIAL APPLICATION
The BUW42/A, BUW42P/AP and SGSIW42/A are silicon multiepitaxial mesa PNP transistors mounted respectively in TO-3 metal case, SOT -93 plastic
package and ISOWATT218 fully isolated package.

T0-3

SOT-93 (T0-218)

ISOWATI218
INTERNAL SCHEMATIC DIAGRAM

ABSOLUTE MAXIMUM RATINGS

TO-3
50T-93
150WATT218

V CES
V CEO
V EBO
Ic
ICM
'B

Collector-emitter voltage (VBE = 0)
Collector-emitter voltage (lBE = 0)
Emitter-base voltage (Ie = 0)
Collector current
Collector peak current
Base current

VISO
Ptot
Tstg
Tj

Isolation voltage (DC)
Total dissipation at Tc ,.; 25°C
Storage temperature
Max. operating junction temperature

BUW42
BUW42P
5G51W42

BUW42A
BUW42AP
5G51W42A

-400
-350
-5

-450
-400
-7

TO-3
150
-65 to 175
175
921

-15
-30
-10
SOT-93

V
V
V
A
A
A

ISOWATT218

4000
V
105
W
50
-65 to 150 -65 to 150°C
150
150
°C
11/86

THERMAL RESISTANCE OF THE ISOWATT218
The junction to case thermal resistance of 2.5
°CM! for the ISOWATT218 package may seem
quite high at first glance but if compared to
a conventional SOT-93 (TO-218) package
with a 0.1 mm mica insulating washer, the differences are marginal. The 0.1 mm isolating
washer gives 1500V to 2000V DC isolation
for the SOT-93 package, SGS guarantee
4000V DC isolation for the ISOWATT 218.

The comparison in fig. 1 shows the dynamic
thermal resistance of both devices mounted
using a thermal compound. The test illustrate
that the ISOWATT218 has an Rth very close
to that of conventional SOT-93 (TO-218) and
any small increase is more than compensated
for by the convenience of the ISOWATT218
package. The collector to heatsink capacitance of the ISOWATT218 is typically 17pF.

103r-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-'G~u:.!.
...'""2.!..9-,

Fig. 1

Zth
(OeM)

1rt

THERMAL IMPEDANCE - TIME
WITH A SMALL HEATSINK
ISOWATT218

•

SOT-n

•

mica thickness - 0,1 mm

10

1Q3
TIME(secl

Safe operating areas

Safe operating area
G-5SUII

(;1: Ie MAX PULSED
I

---++++H-4-XlO;"~

10 I I
o

-;ULSE

MAX CONT I

EEE
'''~m!I

~~~ATlON*'J-±
1m,s

DC current gain

Yce: a5V

~s

~~ "1_:-,;:: .c"

.-

1111

.---.

,.'
923

10

'efA)

BUX481 BUX48A
BUV48/BUV48A
SGSIV481 SGSIV48A

HIGH VOLTAGE POWER SWITCH
• DC, AC MOTOR CONTROL
\ -,

• SWITCH MODE POWER SUPPLY
The BUX48, BUX48A, BUV48, BUV48A, SGSIV48
and SGSIV48A are multiepitaxial mesa NPN transistors mounted in respectively in TO-3 metal case,
SOT-93 plastic package and ISOWATT218 fully isolated package.
They are particularly intended for switching applications directly from the 220V and 380V mains.

91
T0-3

SOT-93 (TO-218)

ISOWATT218
INTERNAL SCHEMATIC DIAGRAM

ABSOLUTE MAXIMUM RATINGS

TO·3
SOT-93
ISOWATT218

V CES
VCER
VCEO
V EBO
Ic
ICM
Icp
IB
IBM

Collector-emitter voltage (V BE = 0)
Collector-emitter voltage (R BE = 10m
Collector-emitter voltage (lBE = 0)
Emitter-base voltage (lc = 0)
Collector current
Collector peak current Icp (tp ,.; 5 ms)
Collector peak current non rep. (tp ,.; 20 /Ls)
Base current
Base peak current (tp ,.; 5 ms)

VI SO
Ptot
T stg
Tj

Isolation voltage (DC)
Total dissipation at Tc ,.; 25°C
Storage temperature
Max. operating junction temperature

BUX48
BUV48
SGSIV48

BUX48A
BUV48A
SGSIV48A

850
850
400

1000
1000
450

TO·3
175
-65 to 200
200
925

7
15
30
55
4
20
SOT-93

V
V
V
V
A
A
A
A
A

ISOWATT218
4000
V
'125
50
W •.
-65 to 150 -65 to 150°C
150
150
°C
11/86

L

BUX48/BUX48A.
BUV48IBUV48A

·s:GSj.VMl/SGStV48A

ELECTRICAL CHARACTERISTICS
Parameter

(Tease = 25°C unless otherwise specified)

Test conditions

RESISTIVE LOAD
ton

ts

tf

Turn-on time

Storage time

Fall time

for BUX48/BUV48/SGSIV48
Vee = 150 V Ie = 10 A
IS1 = 2 A
for BUX48A/BUV48A/SGSIV48A
Vee = 150 V Ie = 8 A
IS1 = 1.6 A
for BUX48/BUV48/SGSIV48
Vee = 150 V Ie = 10 A
IS1 = -ls2 = 2 A
for BUX48A/BUV48A/SGSIV48A
Vee = 150 V Ie = 8 A
IS1 = -IS2 = 1.6 A
for BUX48/BUV48/SGSIV48
Vee = 150 V Ie = 10 A
IS1 = -IS2 = 2 A
for BUX48A/BUV 48A/SGSIV 48A
Vee = 150 V Ie = 8 A
IS1 = -IS2 = 1.6 A

1

JLs

1

JLs

3

JLS

3

JLS

0.8

JLS

0.8

JLs

5

JLs
JLs

5

,.s
,.S

0.4

,.s
,.s

0.4

,.s
,.S

INDUCTIVE LOAD
ts

tf

Storage time

Fall time

for BUX48/BUV48/SGSIV48
Vee = 300 V Ie = 10A
Ls = 3JLH
V SE = -5 V
IS1 = 2 A
same Te = 125°C
for BUX48A/BUV48A/SGSIV48A
Vee = 300 V Ie = 8 A
Ls = 3,.H
V SE = -5 V
IS1 = 1.6 A
sameTe = 125°C
for BUX48/BUV48/SGSIV48
Vee = 300 V Ie = 10 A
Ls = 3,.H
V SE = -5 V
IS1 = 2 A
same Te = 125°C
for BUX48A/BUV48A/SGSIV48A
Vee = 300 V Ie = 8 A
Ls = 3,.H
V SE = -5 V
IS1 = 1.6 A
same Te = 125°C

927

2.7

3

0.16

0.13

BUX48/ BUX48A
BUV48/BUV48A
SGSIV48/SGSIV48A

DC current gain

Forward biased accidental
overload area test circuit.

Forward biased accidental
overload area

Vo

lCSM rTTT--r"--'---rTT 1-,-,,-rrrrn

")
80
?O

"

••

20

""

50

100

200

I
---+-

f--

I

I

3.'

"

300

. •..

LelA)

Collector current spread
vs. base emitter voltage

Collector-emitter
saturation voltage

Saturation voltages

~5

,.,
Ie

'''H-+++-H-++i

j

i

t

:;~:s;::5v.C!

I

-·1 conf 'de1'l<:l'l"'h9S"/.
<0

Ie (A)

Switching times vs.
collector current with Is
constant

Switching times
percentage variation vs.
case temperature

~-+-~.

! ~-

0.8

0.9

Switching times with and
without antisaturation
network (See fig.6 )

G-SUl

'"

)

260

'.

I;:.

Vee ,,200 V

r- 181 "-1e2 "JA
r- L "SOpH
Ie ='OA

/
0.2

H-+-+++-AH-Io........f-H-i
~

'00
10

12

Ie (A)

2S

~

.....

/. ,/

/

'/

-- -

so

y

/

tp=20,us

7S

929

/

>
10

12

'CIA)

BUX48/BUX48A
BUV48/BUV48A
5G81V48/5G51V48A

Fig. 5 - Switching times test circuit on resistive load.

Vee

m
~"TJ

60439

I

Vi

5- 6600

Fig.6 - Switching timestest circuit on inductive load, with and without antisaturation network
.6V

~I100~
16V

Vi

~l~-

1.5mH

2.211.

02

01

I-~

150.n

-6V

S - 6601

01, 02 - Fast recovery diodes
Q1, Q2 - Transistors SGS: 2N5191, 2N5195

931

aB.
HIGH VOLTAGE POWER SWITCHING
•

INDUSTRIAL APPLICATIONS

The BUX48B, BUX48C, BUV48B, BUV48C and
SGSIV48C are multiepitaxial mesa NPN transistors mounted respectively in TO-3 metal case
SOT-93 plastic package and ISOWATT218 fully
isolated package.
They are particularly intended for switching and
industrial appl ications from single and threephase mains.

TO-3

SOT-93 (TO-218)

ISOWATI218
INTERNAL SCHEMATIC DIAGRAM

TO-3
50T-93
150WATT218

ABSOLUTE MAXIMUM RATINGS

VCER
V CES
VCEO
V ESO
Ic
ICM
Icp
Is
ISM

Collector-emitter voltage (R SE = 10m
Collector-emitter voltage (VSE = 0)
Collector-emitter voltage (Is = 0)
Emitter-base voltage (lc = 0)
Collector current
Collector peak current (tp ..;; 5 ms)
Collector peak current non rep. (tp ..;; 2Ol's)
Base peak current
Base peak current (tp ..;; 5 ms)

V ISO
Ptot

Isolation voltage (DC)
Total dissipation at Tc ..;; 25°C
Storage temperature
Max. operating junction temperature

BUX48B
BUV48B

BUX48C
BUV48C
5G51V48C

1200
1200
600

1200
1200
700

TO-3

T stg
Tj

175
-65 to 200
200

933

7
15
30
55
4
20
SOT-93

V
V
V
V

A
A
A
A
A

ISOWATT218
4000
V
120
50
W
-65 to 150 -65 to 150 DC
150
150
°C
11/86

THERMAL RESISTANCE OF THE ISOWATT218
The junction to case thermal resistance of 2.5
°C/W for ttle ISOWATT218 package may seem
quite high at first glance but if compared to
a conventional SOT-93 (TO-218) package
with a 0.1 mm mica insulating washer, the differences are marginal. The 0.1 mm isolating
washer gives 1500V to 2000V DC isolation
for the SOT-93 package, SGS guarantee
4000V DC isolation for the ISOWATT 218.

Fig. 1

The comparison in fig. 1 shows the dynamic
thermal resistance of both devices mounted
using a thermal compound. The test illustrate
that the ISOWATT218 has an Rth very close
to that of conventional SOT-93 (TO-218) and
any small increase is more than compensated
for by the convenience of the ISOWATT218
package. The collector to heatsink capacitance of the ISOWATT218 is typically 17pF.

103, -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-'0"'u:..:.
...""29"--,

ZItl

(tlWl

102

THERMAL IMPEDANCE - TIME
WITH A SMALL HEATSINK
IS(Jw'ATT216

It

SOT-93

•

mica thickness - 0,1 mm
10

lli'
TIME(secl

Safe operating areas

DC current gain

Safe operating areas

...

, ~~
Tc

'cE

-

._I-C
~v

'0 _

,..,
935

""'\
_

L

BUX48B/BUX48C
BUV48B/BUV48C
SGSIV48C

Forward biased accidental
overload area

Clamped reverse bias safe
operating areas
18 :

.-..... -.,.
~

~

~

; t

1--+ • t

,

__ .I

5UU 4()~ 'lV.

JOe)

bUU 'UO fjUO

",-~"acnp(Vl

Fig. 2 - Switching times test circuit on resistive load.
'ee

o

~101-'F

..,..

.~,

'lL

J

"
I

(,

Fig.3 - Switching times test circuit on inductive load, with and without antisaturation network

15 .... 1-1
r~""

..

2211.

{

1-.,.

D2

D1, D2 - Fast recovery diodes
01, Q2 - Transistors SGS: 2N5191, 2N5195

937

lB.

ADVANCE DATA

HIGH VOLTAGE FAST SWITCHING
The BUX98 and BUX98A are silicon multiepitaxial mesa NPN transistors in Jedec TO-3
metal-case intended for use in switching and industrial applications from single and threephase mains operation.

ABSOLUTE MAXIMUM RATINGS
VCER

VCES

VCEO
V ESO
Ic
ICM

Icp
Is
IBM

Ptot
Tstg
Tj

Collector-emitter voltage (R SE = 10n)
Collector-base voltage (V BE = 0)
Collector-emitter voltage (Is = 0)
Emitter-base voltage (Ic = 0)
Collector current
Collector peak current (t p < 5ms)
Collector peak current non rep. (t p < 20/ls)
Base current
Base peak current (t p < 5ms)
Total power dissipation at T case < 25°C
Storage temperature
Junction temperature

BUX98

BUX98A

850V
850V
400V

1000V
1000V
450V
7V

30A
60A
80A
8A
30A
250W
-65 to 200°C
200°C

INTERNAL SCHEMATIC DIAGRAM

MECHANICAL DATA

'4:

Dimensions in mm

Collector connected to case
8.7m.i1X
17max

11.7

TO-3
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

939

10/84

911.

BUX98C

HIGH VOLTAGE SWITCH
The BUX98C, is a multiepitaxial mesa NPN transistors in Jedec TO-3 metal-case intended
for use in switching and industrial applications from single and three-phase mains operation.

ABSOLUTE MAXIMUM RATINGS
VCER

V CES
V CEO

VEBO
Ic
ICM

Icp
IB
IBM

Ptot
T st9

Tj

Collector-emitter voltage (R BE = 10n)
Collector-base voltage (V BE = 0)
Collector-emitter voltage (I B = 0)
Emitter-base voltage (I C = 0)
Collector current
Collector peak current (tp < 5ms)
Collector peak current non repetitive (tp < 20).15)
Base current
Base peak current (tp < 5ms)
Total power dissipation at Tcase < 25°C
Storage temperature
Junction temperature

1200
1200
700
7
30
60
80
8
30
250
-65 to 200
200

V
V
V
V
A
A
A
A
A

W
°c
°c

INTERNAL SCHEMATIC DIAGRAM

.~:

MECHANICAL DATA

Dimensions in mm

Col/ector connected to case

TO-3

941

6/84

BUX98C

G- 5'3911

Safe operati ng areas

IC

IC MAX PULSED PULSE OPERATION

(Al

10

10 !Js
100}Js

IC MAX CONT. i'-

" l\.

I

8

~

DC OPERATION

l!Js
10ms

""

-

-+wm-\-+
,-++H-I+II-+-+++++++I

I III
4

'8

4

6 B .3

10

DC current gain

-

G 5437

vCE(sal )

,
,

(V)

= 5V

VCE

1111111
I .1'" \5A

11111 \

I

lOA \15A

~ lOA

10

,

1\

•,f--4

,

6 B

Collector-emitter saturation voltage
ct- 54:11

10

4

2

10

,
1\\

I.,

II
,

I i

I
,

'I

I

II I

I

ii'

li'l

,

i

I
,

i

,

I

I'

I

68

10

' I

Iii
'-

-,

,

,\

10

"

468

0.1

IC (A)

943

10

IS (A)

II.
HIGH SPEED SWITCHING APPLICATIONS
SECONDARY RECTIFICATION
• VOLTAGE RANGE: 50V - 200V
• AVERAGE CURRENT: 7.6A
• VERY LOW REVERSE RECOVERY
TIME: trr 35ns

DIOWATTl

• VERY LOW SWITCHING LOSSES
• LOW NOISE TURN-OFF SWITCHING
A
K

Typical applications include secondary rectification in high frequency switching power supplies and freewheel diodes in
stepper motor control systems.

K--t+-- A

ABSOLUTE MAXIMUM RATINGS
BYW29

VRRM
VRWM
VR
IFRM
IF(AV)
IFSM

PtQt
Tstg
Tj

Peak repetitive reverse voltage
Working peak reverse voltage
Continuous reverse voltage
Repetitive peak forward current (t= 1OILS)
Average forward current Tcase = 70°C
(switching operation, 0=0.5)
Surge non repetitive forward current (t= 10ms)
Total dissipation at Tcase = 70°C
Storage temperature
Max. junction temperature

945

-50

-100

-150

-200

50
50
50

100
100
100

150
150
150

200
200
200

V
V
V

80

A

7.6
80
18
-40 to 150
150

A
A
W
°C
°C

3/86

II.
MOTOR CONTROL. SWITCH REGULATORS
The MJE13006, MJE13007 and MJE13007A are silicon multiepitaxial mesa NPN transistors.
They are mounted in Jedec TO-220 plastic package, intended for use in motor controls,
switching regulator's etc.

ABSOLUTE MAXIMUM RATINGS
VCEO
VCEV

V EBO

Ic
ICM
IB
IBM
IE
IEM

Ptot
T stg

Tj

MJE13006

Collector-emitter voltage (VB = 0)
Collector-emitter voltage
Emitter-base voltage (lc = Q)
Collector current
Collector peak current
Base current
Base peak current
Emitter current
Emitter peak current
Total power dissipation at T case :;::; 25°C
Storage temperature
Junction temperature

300V
600V

MJE13007 MJE13007A
400V
700V
9V
8A

400V
850V

l6A
4A
8A

l2A
24A
80W
-65 to 150°C
150°C

INTERNAL SCHEMATIC DIAGRAM

MECHANICAL DATA

Dimensions in mm

Collector connected to tab.

3.B5

.7

TO-220

947

2/84

ELECTRICAL CHARACTERISTICS (Continued)
Parameter

Test conditions

RESISTIVE SWITCHING TIMES (Fig. 2)
ton

Turn-on time

Vcc=125V

ts

Storage time

IS1=-ls2=lA

tf

Fall time

tp = 25/Ls Duty Cycle

Ic=5A

0.7 /Ls
3 /LS

< 1%

0.7 /Ls

INDUCTIVE SWITCHING TIMES (Fig. 1)
tf

Fall time

* Pulsed: pulse duration
Safe operating areas

Vcc= 125V
lSI = 1A
tp = 25/Ls Duty
Tcase=l00°C
Vcc= 125V
lSI = 1A
tp = 25/Ls Duty
~300/Ls,

duty cycle

Ie
(A)

~

cycle < 1%
0.6 /LS

Ic=5A
cycle ~ 1%

1.5%

8

-:-1-

6
4

,

I

I e MAX PULSED
10

0.3 /LS

Ic=5A

PULSE OPERATION

leMl x to~+.1110mU
B
6

6'

.
\

"
..

~

- ,
,

10-1

*

lm~ 100

*

'\

'\

'\. \

FOR SINGLE NON
REPETITIVE PULSE

8

I

10- 2

,

,

6 8

10

949

MJE13006
MJE13007
MJEI3007A
•

8

I
,

,

8

MJE13006!

··MJE13007
!;.

Collector current spread vs. base emitter
voltage

MJ~13007A

Switching times resistive load
(See fig. 2)

'e
(AI

=

VeE 1.5V

Confidence level =90°/0

12
10

._-

t---t----t-- -t,.-::=!~tt::=-:=_=_

1--1""-=+-~--.-~

Switching times percentage variation vs.
case temperature

./.

Go

LU.-

Ion

o

0.8

8

- 52t.6
-----

1/

hFCS

'e (A I

Switching times inductive load
(See fig. 1)

ResistivE' load

Vee = 15QV

-

:1

'Bl = -'B2
'e=SA

J

t'l

/ V

/

100

~~
25

~V

-~

50

,/

75

/V
V

....... V

V

V'
1---

--

1.5

100

951

c--4.5

7.5

9

Ie (AI

MJE13006
MJE13001
','MJEt3007A

Fig. 1 - Switching times test circuit on inductive load, with and without antisaturation network

0--=

+6V

1.5 mH

2.2.fl

I 16 v

100~F

-6V

~I1~OI'F
16V

S - 6601

D1, D2 - Fast recovery diodes
01,02 - Transistors SGS: 2N5191, 2N5195

Fig. 2 - Switching times test circuit on resistive load.

Vee
0--8D439

5- 6600

953

Fig. 6 - Remarks to

VeElsat)

dyn. test circuit (fig. 4)

90'"

VCElsatidyn
VCE(sa! )

5- 660 3

The speed-up capacitor decreases the VeE Isatl dyn. as shown in diagram (figure 6).
The 50nF capacitor modifies the shape of base current with a overshoot.

955

lIB.
HIGH SPEED SWITCHING APPLICATIONS
SECONDARY RECTIFICATION
• VOLTAGE RANGE: 50V - 200V
• AVERAGE CURRENT: 8A
• VERY LOW REVERSE RECOVERY
TIME: trr 35ns

DIOWATTl

• VERY LOW SWITCHING LOSSES
• LOW NOISE TURN-OFF SWITCHING
K

Typical applications include secondary rectification in high frequency switching power supplies and freewheel diodes in
stepper motor control systems.

K---K-- A

ABSOLUTE MAXIMUM RATINGS
SGS

IFSM

Peak repetitive reverse voltage
Working peak reverse voltage
Continuous reverse voltage
Repetitive peak forward current (t = 101ts)
Average forward current Tease = 70°C
(switching operation, 0=0.5)
Surge non repetitive forward current (t = 10ms)

Ptot
Tstg
Tj

Total dissipation at Tease = 70°C
Storage temperature
Max. operating junction temperature

VRRM
VRWM
VR
IFRM
IF(AV)

957

8R05

8Rl0

8R15

8R20

50
50
50

100
100
100

150
150
150

200
200
200

V
V
V

100

A

8

A
A

80
50
-65 to 150
150

W

DC
DC

3/86

Fig. 4 Recovery time and peak reverse current vs. IF

Fig. 5 Recovered charge vs. diF/dt

GC-02

trrlns)

I

35

I

I
10M

:.--

30

GC-02B2

I

~.8A

1.

1/5A
I

60

-

--

, 2A

50

./

I---

~-

I

40

,

,/

./

30

,

0.5

25

Z

T.IOO·C

20

~

...

25°C I.oIIII!!!

20

o

2

3

4

V
~

10

:~~

V 5A

2A

~IA

:;...f-"

o

6

10

Fig. 6 Recovery time vs. diF/dt

100

Fig. 7 Recovery time vs. diF/dt

GC 03'21

GC-0281

t"lns)

40

70

Tc=25°C

Tc=IOODC

60

I

30
50

40
30

:,..

"'.8A

... --=:::::".
~

-5A
-......: 2A
IA

20

~IF·8A
5A
I'-...
1" ~A

10

20
10

10

o

100

959

10

100

d\,/dIiA/ps'

SGS1.5DB070D
SGS15DB080D
TRANSPACK NPN POWER DARLINGTON MODULE
APPLICATIONS:

These products are silicon NPN power darlingtons in half bridge configuration for industrial switching applications with three-phase mains operation.

ISOLATED POWER MODULE (15KVA - 375W)

FAST FREEWHEEL DIODES

ABSOLUTE MAXIMUM RATINGS
V CBO
VCES
VCEX
VCEO
V CEOL
V EBO
Ic
ICM
Icp
IB
IBP
T stg
Tj
Tj

SGS15DB070D SGS15DB080D

Collector-base voltage (IE = 0)
Collector-emitter voltage (VBE = 0)
Collector-emitter voltage (V BE = -1 .5V)
Collector-emitter voltage (lB = 0)
Overload switch-off at 1.5 times Ic (sat)'
Emitter-base voltage (Ic = 0)
Collector current
Collector peak cu rrent (tp < 10 ms)
Collector peak current non repetitive (tp<20 ~s)
Base current
Base peak current non repetitive (tp<20 ~s)
Storage temperature
Max. operating junction temperature (continuous)
Max. operating junction temperature (1 minute)

INTERNAL SCHEMATIC
DIAGRAM

1000
1000
1000
700

1200
1200
1200
800
650
7
23
60
100
6
30
-4010150
150
175

MECHANICAL DATA

i

~SCREW

I

ZINC PLATED M5,IO
. _LOCK WASHER
'WASHER
ZINC PLATED

l"

.

U?:, , t
I

, I'

DC
DC
DC

Dimensions in mm

BOLT ZtNC PLATED M5,IS

l,

I
I

V
V
V
V
V
V
A
A
A
A
A

I

.:.,

fASTON 3.7,14.5 TINNED BRASS

a;1""+"" I~ 140
cqn HEXAGONAL

R, typo 10

NUT ZINC PLATED MS'3.5

Q

R2 typo 50 Q
INTERAX'S TOl..LERANCE

961

±

0.3

TO-240AA

08/85

ELECTRICAL CHARACTERISTICS
Parameter

trr
I,m

I',m

(Continued)

Test Conditions

Diode reverse
recovery time
Diode reverse
recovery current

I, = 15 A

Diode forward
current

t = lms

Min. Typ. Max. Unit

0.20 0.5

di/dt = 100Al!-,s

12

160

f.tS

A

A

INSULATION TESTING
The insulation between the live parts and the base plate of TO-240 is tested before delivery for one
second at 2500 V a.c.
If this test is repeated by the user either as a goods inwards check or as a test of the final equipment, in accordance with IEC Publication 146 (1973), clause 492.1 or DIN 57558 part 1NDE 0558
part 1/8.77, section 5.7.9., only a voltage slowly increasing up to the above value should be used.
If the voltage is applied for one minute as recommended by the above standards then the specified
value of 2000 V should be taken.
During the test all electrical terminals including the drive terminals must be connected with each
other in order to avoid damage by inductively or capacitively induced voltage transients. The test
voltage is applied between the connected terminals and the base plate.

Safe operating areas for each section
GC

lel/iI

02~9

6

PULSE OPER ATION

*

Ie MAX PULSED

Ie

~s

MAX CONT.
:-...IOO~s

I II

Id,
6

m
Ims

DC OPERATION

*

'\

"\

For single non
repetetive pulse

IOms

I'\.

lCJ~
6

SGSI5DB070D
SGSI5DB080D 4

963

6

e 102

2

"6

e VcE(Vl

SGS15DB070D
SGS15DB080D

Collector overload SOA (see fig. 1)

Ic(A)

.1--- -f--

...- -- - i--+-+--+-~

_._j.- +-

100

rr
I

80

1---II -

-t

RBE=27~"l
tp=20)ls

I

.

L

30

o

o

--r:: ---400

200

600

I

--'--1-20

-

I

I

10

!

t- - -

I

a
800

0

VCE (V)

r

I

~-

TJ ~125°C
RBE =27.\<
tp"20 )ls

--

11

I

!

-+---

::~~=:r=-=,=-~r=~=
r-l

I

. -----l---T:-t-i

~ ~t-·---

I

I

! 1

-- - - - - j

40

--I---i

-

H -". . .-'. . - r- --- ---T:'~1250C

60

Base overload SOA (see fig. 1)

200

400

600

800

VCE(V)

Switching times inductive load (see fig. 3)

Reverse biased SOA (see fig. 2)

-:.-

.-

."
-

coo

- _.

Vcl=300V
L'5QOpH
hFE'lO
VBEoff=-5V

-

_._-

ts .. 125°C

-

:::::::: ::

ts",25°C

.: -::-:-.-

·~-·r-

..~

-

--_.

,.-i-i-H
~l--~

0.1

o

200

400

600

800 1000

1200

Vc1arnp(Vl

965

~

....

- -I
f..--' ...-

~

.::::r:::.t

- ; -_.

H

I

~C

12

Ic(AI

Fig. 2 RBSOA TEST CIRCUIT
RBSOA test circuit has been driven by
the switching times test circuit
with

RS2

=

O.

RBSOA sensitivity to Tj variations
is very limited, so that the limits shown

tp adjusted for

can be kept valid at ambient temperature

nominal ic

as well.

ic / ib = 10

Vclomp

SC-0002

Fig. 3 Switching times test circuit

Vcc=250V

SC-OI60

967

aB.
HIGH SPEED SWITCHING APPLICATIONS
• VOLTAGE RANGE: 50V--->200V
• AVERAGE CURRENT: 16A
• VERY LOW REVERSE RECOVERY
TIME: trr 35ns

TO-220
~~

• VERY LOW SWITCHING LOSSES

~.

• LOW NOISE TURN-OFF SWITCHING

VERSAWATT

KA1

A2

Typical applications include secondary rectification in high frequency switching power supplies.

ABSOLUTE MAXIMUM RATINGS
SGS
16DR05 16DR10 16DR15 16DR20
VRRM
VRWM
VR
IFRM
IF(AV)
IFSM

Ptot
Tstg
Tj

Peak repetitive reverse voltage
Working peak reverse voltage
Continuous reverse voltage
Repetitive peak forward current (t = lO",s)
Average forward current T case = 70°C
(switching operation, Ii = 0.5)
Surge non repetitive forward current (t = 10ms)
Total dissipation at T case = 70°C
Storage temperatu re
Max. operating junction temperature

969

50
50
50

100
100
100

150
150
150

200
200
200

V
V
V

120

A

16
100
70
-65 to 150
150

A
A
W
°C
°C

3/86

Fig. 4 Recovery time and peak reverse current vs. IF
GC-0283

Fig. 5 Recovered time vs. diF/dt

IIMIA)

GC-0281

t';fns)

I. 5

-'"

30

70

IlM

f- f- f-

~-

.....

50

~

'"

./

25

T••IOO·C

60
I

40
0.5
30

,...
f=:::
~

~1r·aA
5A
.......: 2A

20

3

2

5

4

6

7

o

10
10

'rIA)

Fig. 6 Recovery charge vs. diF/dt

GC 0321

trrlns)

",.SA

70

1'/5A

I

60

40
Tc=25°C

2A

50

I

30

40
30

IJ

,

i.:

T.IOO·C
,~. ;

20

~

25°C
10

1r·8A
-5A

:~~

,2A
IA

20

V 5A
V

;

.6

10

o

dio/dt IAlps)

Fig. 7 Recovery time vs. diF/dt
GC-0282

Q,lnC)

100

2A
i,..--IA

10

1.oiII!I!!:;..
o

100

971

10

100

dl,.-/dtIA/ps)

II.

SGS20ROS
SGS20R10
SGS20R15
SGS20R20
ADVANCE DATA

HIGH SPEED SWITCHING APPLICATIONS
SECONDARY RECTIFICATION
• VOLTAGE RANGE: 50V-+200V
• AVERAGE CURRENT: 20A
• VERY LOW REVERSE RECOVERY
TIME: trr 35ns

DO·220

DIOWATT1

• VERY LOW SWITCHING LOSSES
• LOW NOISE TURN-OFF SWITCHING
K

Typical applications include secondary rectification in high frequency switching power supplies and freewheel diodes in
stepper motor control systems.

K-K-A

ABSOLUTE MAXIMUM RATINGS
SGS

IFSM

Peak repetitive reverse voltage
Working peak reverse voltage
Continuous reverse voltage
Repetitive peak forward current (t = 101's)
Average forward current T case = 70°C
(switching operation, b = 0.5)
Surge non repetitive forward current (t= 10ms)

Ptot
T stg
Tj

Total dissipation at T case = 70°C
Storage temperature
Max. operating junction temperature

VRRM
VRWM
VR
IFRM
IF(AV)

20R05

20R10

20R15

20R20

50
50
50

100
100
100

150
150
150

200
200
200

V
V
V

250

A

20
200
60
-65 to 150
150

A
A
W
°C
°C

This advanced information on a new products now in development or undergoing evaluation. Details are subject to change without notice.

.

973

3/86

II.
TRANSPACK NPN POWER DARLINGTON MODULE
APPLICATIONS:

The SGS25DB070D and SGS25DB080D are silicon NPN power fast darlingtons in half bridge configuration for industrial switching applications with
three-phase mains operation.

ISOLATED POWER MODULE (24KVA-375W)

FAST FREEWHEEL DIODES

ABSOLUTE MAXIMUM RATINGS

SGS25DB070D SGS25DB080D

VCBO Collector-base voltage (IE = 0)
VCES Collector-emitter voltage (VBE = 0)
VCEX Collector-emitter voltage (VBE = -1.5V)
VCEO Collector-emitter voltage (IB = 0)
VCEOL Overload switch-off at 1.5 times Ic (saW
VEBO Emitter-base voltage (Ic = 0)
Ic
Collector current
ICM
Collector peak current (1p<10 ms)
Icp
Collector peak current non repetitive (1p<20 !AS)
IB
Base current
IBP
Base peak current non repetitive (tp<20 !AS)
Tstg Storage temperature
Tj
Max. operating junction temperature (continuous)
Tj
Max. operating junction temperature (1 minute)

INTERNAL SCHEMATIC
DIAGRAM

1000
1000
1000
700

1200
1200
1200
800
650
7
37
80
150
9
30
-40t0150
150
175

MECHANICAL DATA

.t.i* .;.

IIIlLTZIMC~ATEIHI.5XI8

.

.

~
•

V
A
A
A
A
A
°C
°C
°C

Dimensions in mm
..

CR£W ZINC

PLA'rEIHlI5XIO

LOCi< WASHER
WASHER

I

..

ZINC PLA

iji FASTQN 3.7.14.5 TINNEDIiRASS

28

.8.4

V
V
V
V

.TJ:IJ:lIl

I

I

~ED

r;'i

m
I.P*J
~

HEXAGON"L I'IlIT ZINC PLA ED t.15'3.5

R, typ 10 Q

R2typ 50 Q

975

08/85

SGS25DB070D
SGS25DB080D

ELECTRICAL CHARACTERISTICS
Parameter

(Continued)
Min. Typ. Max. Unit

Test Conditions

Vf

Diode forward
voltage

If = 25 A
If = 25 A T j = 125°C

1.4
1.4

2

V
V

trr

Diode reverse
recovery time
Diode reverse
recovery time

If = 25 A dildt = 100AlftS

0.2

0.5

fls

Diode forward
current

t = 1ms

Irm

Ifrm

12

200

A

A

INSULATION TESTING
The insulation between the live parts and the base plate of TO-240 is tested before delivery for one
second at 2500 V a.c.
If this test is repeated by the user either as a goods inwards check or as a test of the final equipment, in accordance with IEC Publication 146 (1973), clause 492.1 or DIN 57558 part 1IVDE 0558
part 1/8.77, section 5.7.9., only a voltage slowly increasing up to the above value should be used.
If the voltage is applied for one minute as recommended by the above standards then the specified
value of 2000 V should be taken.
During the test all electrical terminals including the drive terminals must be connected with each
other in order to avoid damage by inductively or capacitively induced voltage transients. The test
voltage is applied between the connected terminals and the base plate.
Safe operating areas for each section

DC current gain

6

977

8

10

• le lAI

Typical VF versus -Ie

Reverse biased SOA (see fig. 2)
-Vee (V)
2.5

GC" 0241

IclA

I

37

GC-0009

I
I

30

r- TVBEoff=-5V
J$25°C

20

IV

1.5

Tj·25°C

A

.........::
-./

\

JO

SGS25DB070D
SGS25DB080D

......
o

400

800

:.,.....

I

/

Tj "'125 0 C

.....,
1200

Vc1amplV)

0.5
100

50

10

-lc(A)

Switching times inductive load (see fig. 3)

Switching times inductive load vs
junc temp
% 200

tt-~f

Vcl=300V
Ic=I5A

-

VBEoff =-5V

-

L'500)'H

I

hFE"'IO
VBEoff=-5V

//
V
./ /'"

~V

:: :: :: ::

/

---

/

25

L'500pH

/

J50

--

75

100

r--

--

ts=25 D C

~
I-

---

l - i.-

125

--

ts"'125°C

t.
0.1

50

-

Vcl=300V

-

/

hFE'IO

100

GC-0041

GC"()042

TjI"C)

979

....-;/

~H
6

.....

H I-""

I I

-- I

--/

~C

12

le(A)

Fig. 2 RBSOA TEST CIRCUIT
RBSOA test circuit has been driven by
the switching times test circuit
with

RS2 ~

O.

RBSOA sensitivity to Tj variations
is very limited, so that the limits shown
can be kept valid at ambient temperature

tp adjusted for

as well.

nominal ic
ic / ib

=10

Vclamp

SC-0002

Fig. 3 Switching times test circuit

-1.5V

L=500J-lH

Vcc=250V

,I

L __

SC-OI60

981

II,

"f

,',,';r?/,.,:(, '.";~ ~::>;:':. :,/",\?>

8GS300:' .

S.GS30DAv.A':

.'W'Wjjj.i

TRANSPACK NPN POWER DARLINGTON MODULE
APPLICATIONS:

These products are silicon NPN power darlingtons for industrial switching
applications with three-phase mains operation.

ISOLATED POWER MODULE (30KVA - 375W)

I

ABSOLUTE MAXIMUM RATINGS

SGS30DA060D SGS30DA070D

VCBO Collector-base voltage (IE = 0)
VCES Collector-emitter voltage (VBE = 0)
VCEX Collector-emitter voltage (V BE = -1.5V)
VCEO Collector-emitter voltage (IB = 0)
VCEOL Overload switch-off at 1.5 times Ic (sat)'
VEBO Emitter-base voltage (Ic = 0)
Ic
Collector current
ICM
Collector peak current (tp<10 ms)
Icp
Collector peak current non repetitive (tp<20 !IS)
~

~~~

IBP
Tstg
Tj
Tj

Base peak current non repetitive (tp<20 !IS)
Storage temperature
Max. operating junction temperature (continuous)
Max. operating junction temperature (1 minute)

INTERNAL SCHEMATIC
DIAGRAM

FAST FREEWHEEL DIODE

1000
1000
1000
600

1200
1200
1200
700
650
7
45
120
200
3
20
- 40 to 150
150
175

MECHANICAL DATA

983

V
V
V
V
V
V
A
A
A
A
A
°C
°C
°C

Dimensions in mm

08/85

I

L

ELECTRICAL CHARACTERISTICS
Parameter

Test Conditions

V,

Diode forward
voltage

I, = 30 A

t"

Diode reverse
recovery time
Diode reverse
recovery current

I,

Diode forward
current

t

Irm

I'rm

(Continued)

= 30A

Min. Typ. Max. Unit

Tj = 25°C
Tj = 125°C
di/dt

= 100A/IAS

1.4
1.4

2

V
V

0.2

0.5

f.ls

10

= 1ms

200

A

A

INSULATION TESTING
The insulation between the live parts and the base plate of TO-240 is tested before delivery for one
second at 2500 V a.c.
If this test is repeated by the user either as a goods inwards check or as a test of the final equipment, in accordance with IEC Publication 146 (1973), clause 492.1 or DIN 57558 part 1NDE 0558,
section 5.7.9., only a voltage slowly increasing up to the above value should be used. If the voltage
is applied for one minute as recommended by the above standards then the specified value of 2000
V should be taken.
During the test all electrical terminals including the drive terminals must be connected with each
other in order to avoid damage by inductively or capacitively induced voltage transients. The test
voltage is applied between the connected terminals and the base plate.
Safe operating areas

~~!_II~~~~I~~§jGC~O~25~7

Ic(AI

------'-__ L_L_LLH

JO:
6

,

r---1

PULSE OPERATION

*

~C~MA~X~PU~L~S~EP~~~~~~~AI~~~~'~
Ie MAX CONT.

40ps

100us

10l

~1!!!~"\IIII"-!!r-~llm~SII

r P C OPERATION

*
10:o[;~I~I~
1111~BII~~!Ijo,m-sll
For single netl1
II;
repetetlve
pulse

~~II~'II!"\_II

~

10:
'
SGS30PA060P
10_21----'-....J....l...I...J....L..Lll---,---"S:..::G:::S3::.;0:..::D::;:A.::.0.:.;70""P--,--'-'..LLL.1J
100

"6

8

101

4

985

6

6

102

2

,

"

VcE(VI

SGS30PA060P
s,~$3aDAa70P

Collector overload SOA (see fig. 1)

Base overload SOA (see fig. 1)
6C·00l0

lelA) 30

GC-OOIt

IblAl30

25

200

20

I!IO

tp'20~S

RBE 11:1 150 ohm
RBE2·27olwn

r-- -

r-- r -

T··I25"C

100

tp' 20)lS
RBEI=150ohm
RBE2=27ohm

T"'I2!l'C

10

50

o

o
o

200

400

600

1000

BOO

1200

o

400

200

600

1000

800

VeE (V)

Reverse biased SOA (see fig. 2)

Switching times inductive load (see fig. 3)
GC 0233

lelA )

1200
VCE(V)

GC 0013

t()I'~

. f--

.... 12!5°C

H-r

f40

VSEofe-5V
T I<125'C

~

~

~

fSr,oc

..... ~ ..... f-

tf=125°C

30

tf=2!5°C

20

oI

..... ""

~;...-

II
Vcl=300V

hFE=20

f- SGS30DA060D

10

o

" "'
200

400

600

800

VBEoff =-5V

SGS30DA070D

..,
j

1000

I

I
I

I I

II

0.0 I

1200

10

987

20

30

lelA)

Fig. 2 RBSOA TEST CIRCUIT
RBSOA test circuit has been driven by
the switching times test circuit
with RB2 = O.
RBSOA sensitivity to Tj variations
is very limited, so that the limits shown

tp adjusted for

can be kept valid at ambient temperature
as well.

nominal ie
ie l ib =20

Velamp

SC-0002

Fig. 3 Switching times test circuit.

Vec=50V
L=500 )'H

tPJL

D.U.T.

-5V

Velamp
300V

SC-0003

989

SGS30DB040ti···
SGS30:0B0450~'

lIB.

",

',"

,:",,',

-

.

-f!'

1<',:,

TRANSPACK NPN POWER DARLINGTON MODULE
APPLICATIONS:

These products are silicon NPN power fast darlingtons in half bridge configuration for industrial switching applications from the mains.
FAST FREEWHEEL DIODES

ISOLATED POWER MODULE (15KVA - 375W)

ABSOLUTE MAXIMUM RATINGS

SGS30DB040D SGS30DB045D

VCBO Collector-base voltage (IE = 0)
VCES Collector-emitter voltage (VBE = 0)
VCEX Collector-emitter voltage (VBE = -1.5V)
VCEO Collector-emitter voltage (lB = 0)
VCEOL Overload switch-of! at 1.5 times Ic (sal)'
VEBO Emitter-base voltage (Ic = 0)
Ic
Collector current
ICM
Collector peak current (tp<1 0 ms)
Icp
Collector peak current non repetitive (tp<20 f.ts)
IB
Base current
IBP
Base peak current non repetitive (tp<20 f.ts)
T sig Storage temperature
Max. operating junction temperature (continuous)
Tj
Max. operating junction temperature (1 minute)
Tj

INTERNAL SCHEMATIC
DIAGRAM

500
500
500
400

600
600
600
450

"

°C
°C
°C

Dimensions in mm

I

I

li=1'°'r'"tI~
a:fn

I

.. '-- ...

..... WASHER

~~''''

R1 typo

A
A
A
A
A

BOLT ZINC PLATED MSxl8
-L 1SCREW ZINC PLATED M5xlO
[,~LOCK WASHER

i ,

4

V
V

400
7
45
60
200
6
10
-40t0150
150
175

MECHANICAL DATA

,

V
V
V
V

ZINC PLATED

tdQ
II I

HEXAGONAL NUT ZINC PLAtED M5k3.5

80 Q

R2 typo 150 Q
INTERAXIS TOLLERANCE 1: 0.3

991

TO-240AA

08/85

SGS30DB040D
S(I$3QDB04SD
ELECTRICAL CHARACTERISTICS
Parameter
Diode forward
voltage

If

=

trr

Diode reverse
recovery time
Diode reverse
recovery current

If

= 30A

Diode forward
current

t

Ifrm

Min. Typ. Max. Unit

Test Conditions

Vf

I,m

(Continued)

30 A

Tj
Tj
di/dt

=

=
=

25°C
125°C

100Al[ts

1.30
1.20

2.0

V
V

0.20

0.5

[ts

10

=

250

1ms

A

A

INSULATION TESTING
The insulation between the live parts and the base plate of TO-240 is tested before delivery for one
second at 2500 V a.c.
If this test is repeated by the user either as a goods inwards check or as a test of the final equipment, in accordance with IEC Publication 146 (1973), clause 492.1 or DIN 57558 part 1/8.77, section
5.7.9., only a voltage slowly increasing up to the above value should be used. If the voltage is applied for one minute as recommended by the above standards then the specified value of 2000 V
Should be taken.
Durirg the test all electrical terminals including the drive terminals must be connected with each
other in order to avoid damage by inductively or capacitively induced voltage transients. The test
volta\.e is applied between the connected terminals and the base plate.
Safe operating areas for each section
GC~D258

)

Ie MAX
PULSED

W

~-~:-;"-::-.-

Ie MAX
CONT.

10' e
&

"==F~"

PULSE OPERATION

~ ~ir+

U

I

40~s

IOO~~
..

ffiF .. ::31<

*

Ims

DC OPERATION

* tor

single non

repetetive pulse

r-- FF

~

:i
--

!\..
...-IOms

'\. "r"-SGS30DB040D
SGS30DB045D 4

6

a 101

,

&

e
VcEIVI

993

Collector overload SOA (see fig. 1)

Base overload SOA (see fig. 1)

GC 0020/1

le(A)

GC 0021

19 (A)

14
12
200
10

e

t--- f-SGS 30060400
Tj =125 D C

RSE=27!:l
tp=20)ls

100

I--

SGS 30080400

i'-SGS 30060450
TJ-'125 D C

4

SGS 30 0 80450

RaE =27.a

--

tp· 20)"

300

500

400

100

600

Reverse biased SOA (see fig. 2)

200

300

400

VCEIV)

Switching times inductive load (see fig. 3)
GC 0234

lelA )

40

30

f- -

VBEoff=-5V

TjEl25'C

20

\

10

II

SGS30DB040D
SGS30DB045D

r-.-t I
I
o

100

200

300

400

500

600

700

VdomplV)

995

10

20

30

40

le(A)

L

Fig. 2 RBSOA TEST CIRCUIT
RBSOA test circuit has been driven by
the switching times test circuit
with

RB2 ~

O.

RBSOA sensitivity to Ti variations

tp adjusted for

is very limited, so that the limits shown
can be kept valid at ambient temperature

nominal ic

as well.

ic / ib =20

Vclamp

SC-0002

Fig. 3 Switching times test circuit.

-L5V

L=500)JH

Vcc=250V

1-5V
SC-OISO

997

II.

ADVANCE DATA

TRANSPACK N·CHANNEL POWER MOS MODULE
APPLICATIONS:

The SGS30MA050D1 is a N-Channel POWER MOS MODULE for industrial applications (quarter bridge configuration).

ISOLATED POWER MODULE (15KVA - 375W)

ABSOLUTE MAXIMUM RATINGS

SGS30MA050D1

VOS
Drain-source voltage (VGS = 0)
VOGR Drain-gate voltage (RGS = 20 KQ)
VGS Gate-source voltage
10
Drain current (continuous) T c = 25 °C
10M
Drain current (tp < 10 ms, repetitive)
10LM
Drain current (tp = 20I-lS, not repetitive)
PIal
Total dissipation at T c < 25 °C
Derating factor
Tslg
Storage temperature
Tj
Max. operating junction temperature (continuous)
Tj
Max. operating junction temperature (1 minute)

INTERNAL SCHEMATIC
DIAGRAM

INTERNAL FREEWHEEL DIODE

500
500
±20
30
45
75
300
3
-55 to 150
150
175

MECHANICAL DATA

V
V
V
A
A
A
W
Wf'C
°C
°C
°C
Dimensions in mm

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

999

08/85

L

ELECTRICAL CHARACTERISTICS
Parameter

(Continued)

Test Conditions

SOURCE DRAIN DIODE (see note B)
Iso
ISOM

Source-drain current
(continuous)
Source-drain current
(pulsed)

Vso

Forward on voltage

Iso = 30 A VGS = 0

trr

Reverse recovery
time

Iso = 30 A VGS = 0
di/dt = 150 A/Ils

30

A

45

A

2

V
ns

600

Note A: switching times inductive load have been tested by the circuit shown in fig. 1 (by paralleling
the load with SGS fast recovery diode ... ).
Typical waveforms obtained for Vo and 10 are schematically shown here below.

lo-Vo at turn-on

lo-V o at turn-off
GC 0273

GC~0274

\
v0

\
I

l

vo

:/

V'
1/\
\\
1\

Note that dildt does not depend on the perfomances of the freewheeling diode, but on the D.U.T. and
its drive circuit only.

1001

lIB.

ADVANCE OAT A

N-CHANNEL POWER MOS TRANSISTORS
HIGH SPEED SWITCHING APPLICATIONS

Voss

RDS (on)

10

SOOV

0.160

3SA

• ISOLATED POWERMOS MODULE
• HIGH POWER
• FAST SWITCHING
• EASY DRIVE

TO-240AA

• EASY TO PARALLEL
INDUSTRIAL APPLICATION:
• SWITCHING MODE POWER SUPPLIES

INTERNAL SCHEMATIC DIAGRAM

• UNINTERRUPTIBLE POWER SUPPLIES
N-Channel enhancement mode POWERMOS field effect transistors. Easy drive and fast switching of these TRANSPACK modules make them ideal for high
power, high speed switching applications.
Typical applications include DC motor control (speed,
soft start and torque). AC motor control (variable frequency control) switching mode power supplies,
uninterruptible power supplies, DC/DC convertors
and high frequency welding equipment.
The large RBSOA and absence of second breakdown
in POWERMOS make these TRANSPACK modules
very rugged. This, together with the isolated package with its optimised thermal performance, make these modules extremely effective in high power
application.

ABSOLUTE MAXIMUM RATINGS
V DS
V DGR
V GS
ID
IDM
IDLM

Ptot
T stg
Tj

SGS30MAOSOD1

Drain-source voltage (V GS = 0)
Drain-gate voltage (R GS = 20KQ)
Gate-sou rce voltage
Drain current (continuous) Te = 25°C
Drain current (t p ::;; 10 ms, repetitive)
Drain current, (tp = 20",s, not repetitive)
Total dissipation at Tease <25°C
Derating factor
Storage temperature
Max. operating junction temperature (continuous)

500
500
± 20
35
50
80
400
3.2
-55 to 150
150

V
V
V
A
A
A
W
W/oC
°C
°C

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

1003

06/86

ELECTRICAL CHARACTERISTICS
Parameter

Test conditions

SOURCE DRAIN DIODE
Iso
ISOM

(continued)

(see note B)

Source-Drain current
(continuous)
Source-Drain current
(pulsed)
V GS = 0

Vso

Forward on voltage

Iso = 35A

trr

Reverse recovery
time

dildt = 150A/!-,s
V GS = 0

Iso = 30A

35

A

50

A

2
600

V
ns

INSULATION TESTING
The insulation between the live parts and the base plate of TO-240 is tested before delivery for one
second at 2500 V a.c.
If this test is repeated by the user either as a good inwards check or as a test of the final equipment,
in accordance with lEe Publication 146 (1973). clause 492.1 or DIN 57558 part 1/VDE 0558, part
1/8.77, section 5.7.9., only a voltage slowly increasing up to the above standards then the specified
value of 2000 V should be taken.
During the test all electrical terminals including the drive terminals must be connected with each other
in order to avoid damage by inductively or capacitively induced voltage transients. The test voltage
is applied between the connected terminals and the base plate.
Note A: switching times inductive load have been tested by the circuit shown in fig. 1 (by
paralleling the load with SGS fast recovery diode SGS45R80).
Typical waveforms obtained for Vo and 10 are schematically shown here below.
lo-V o at turn-on

lo-Vo at turn-off

-I

+--+-+-"i'f--f----

-

-

-

f-

~-

-1l...1=---11-1--- ---- . -+ c-I-

b

1----.

.-- - - , -

-

~

t-

Note that dildt does not depend on the performances of the freewheeling diode, but on the D.U.T.
and its drive circuit only.

1005

II.

ADVANCE DATA

HIGH SPEED SWITCHING APPLICATIONS
• VOLTAGE RANGE: 1200V
• AVERAGE CURRENT: 35A
• VERY LOW REVERSE RECOVERY
TIME: trr 150ns

DIOWATT2

• VERY LOW SWITCHING LOSSES
• LOW NOISE TURN-OFF SWITCHING
K

Typical applications include freewheel diodes in motor control systems.

K-t+-A

ABSOLUTE MAXIMUM RATINGS
VRRM
VRWM
VR
IFRM
IF(AV)
IFSM
Ptot
T stg
Tj

Peak repetitive reverse voltage
Working peak reverse voltage
Continuous reverse voltage
Repetitive peak forward current (t = lO",s)
Average forward current Tease = 70 DC
(switching operation, 0 = 0.5)
Surge non repetitive forward current (t= 10ms)
Total dissipation at Tease = 70 D

e

Storage temperature
Max. operating junction temperature

V
V
V

1200
1200
1200
500

A

35
350
90
-65 to 150
150

A
A
W
DC
DC

This advanced information on a new products now in development or undergoing evaluation. Details are subject to change without notice.

1007

3/86

II.

S,GS40TA045
SQS4.OTA045D

TRANSPACK NPN POWER TRANSISTOR MODULE
APPLICATIONS:

These products are silicon NPN power transistors for industrial switching
applications from the mains.

ISOLATED POWER MODULE (30KVA - 375W)

I

ABSOLUTE MAXIMUM RATINGS

SGS40TA045

VCBO Collector-base voltage (IE = 0)
VCES Collector-emitter voltage (VBE = 0)
VCEX Collector-emitter voltage (VBE = -1.5V)
VCEO Collector-emitter voltage (IB = 0)
VCEOL Overload switch-off at 1.5 times Ic (sat)"
VEBO Emitter-base voltage (Ic = 0)
Collector current
Ic
ICM
Collector peak current (tp<10 ms)
Icp
Collector peak current non repetitive(tp<20 !-Is)
IB
Base current
IBP
Base peak current non repetitive (tp<20 !-Is)
Tstg Storage temperature
Tj
Max. operating junction temperature (continuous)
Tj
Max. operating junction temperature (1 minute)

INTERNAL SCHEMATIC
DIAGRAM

FAST FREEWHEEL DIODE (0 - suffix)

SGS40TA045D

850
850
850
450
500
7
60
120
300
12
50
-40to150
150
175

MECHANICAL DATA

V
V
V
V
V
V
A
A
A
A
A
°C
°C
°C

Dimensions in mm

3--v12
16 ~

1009

08/85

SGS40TA045
SGS40TA045D

ELECTRICAL CHARACTERISTICS
Parameter

Vf

trr
Irm

Ifrm

(Continued)

Test Conditions

= 40 A Tj = 25°C

Diode forward
voltage

If

Diode reverse
recovery time
Diode reverse
recovery cu rrent

I, = 40A

Diode forward
current

t

Min. Typ. Max. Unit

for SGS40TA045D

TJ = 125°C

1.50 2.0
1.55

V
V

0.20

[-Is

0.5

di/dt = 100Al[-ls for SGS40TA045D
10

= 1ms for SGS40TA045D

250

A

A

INSULATION TESTING
The insulation between the live parts and the base plate of TO-240 is tested before delivery for one
second at 2500 V a.c.
If this test is repeated by the user either as a goods inwards check or as a test of the final equipment, in accordance with IEC Publication 146 (1973), clause 492.1 or DIN 57558 part 1IVDE 0558,
section 5.7.9., only a voltage slowly increasing up to the above value should be used. If the voltage
is applied for one minute as recommended by the above standards then the specified value of 2000
V should be taken.
During the test all electrical terminals including the drive terminals must be connected with each
other in order to avoid damage by inductively or capacitively induced voltage transients. The test
voltage is applied between the connected terminals and the base plate.
Safe operating areas

1011

Base overload SOA (see fig. 1)

Collector overload SOA (see fig. 1)

,c-

IeIAI r---r_,----,_-,_,.--,_-,_,.---"G!fC-"'02m,6

56

400~-+-+-~,-~-+--4-~-~-+~

300
40

tp=20us

200

-

tp= 20 )Is

RSE ·27c
30 f - - Tj"125"C

RBE=270
T~125°C

20

100
10

0

200

400

o

600

o

k:: ~

V -"

30

-

f--

-

f--

hFE '5

/

VaEoff'· 5V

Ic=40A

1=
f-

... v

140

./
le(AI

1013

V

/

/

180

1 =25°C

40

VCE(V)

Vcl=300V

I
20

600

GC-0058

If

VSEoff a-ev

10

500

tr- I25°C

Vcl'3OQV
hFE'5

aoI

400

260

t.-2S·C

220

al

300

%300

s·",·

pi-"'"

200

Switching times inductive load vs
junco temp.

Switching times inductive load (see fig. 3)

. -....

100

V

I

/

Is

100
50

75

100

125

Tj("C)

Fig. 2 RBSOA TEST CIRCUIT
RBSOA test circuit has been driven by
the switching times test circuit
with

RB2 =

O.

RBSOA sensitivity to Tj variations
is very limited, so that the limits shown

tp adjusted for

can be kept valid at ambient temperature
as well.

nominal ic

ic / ib =5

Vclamp

SC-0002

Fig. 3 Switching times test circuit.

Vcc=50V
L= 100 }'H

tPJL

D,U.T.

-5V

Vclamp
300V

SC-0003

1015

II.

ADVANCE DATA

HIGH SPEED SWITCHING APPLICATIONS
• VOLTAGE RANGE: 800V
• AVERAGE CURRENT: 45A
• VERY LOW REVERSE RECOVERY
TIME: trr 125ns

DIOWATI2

• VERY LOW SWITCHING LOSSES
• LOW NOISE TURN-OFF SWITCHING
K

Typical applications include freewheel diodes in motor control systems.

K-K-A

ABSOLUTE MAXIMUM RATINGS
VRRM
VRWM
VR
IFRM
IF(AV)
IFSM

Ptot
T stg
Tj

Peak repetitive reverse voltage
Working peak reverse voltage
Continuous reverse voltage
Repetitive peak forward current (t = 10pS)
Average forward current Tcase=70oC
(switching operation, 6= 0.5)
Surge non repetitive forward current (t= 10ms)
Total dissipation at Tease = 70°C
Storage temperature
Max. operating junction temperature

800
800
800
600

V

45
450

A
A
W
°C
°C

90
-65 to 150
150

V
V

A

This advanced information on a new products now in development or undergoing evaluation. Details are subject to change withoyt notice.

1017

3/86

TRANSPACK NPN POWER DARLINGTON MODULE
APPLICATIONS:

The product is a silicon NPN power darlington for industrial switching applications from the mains.

ISOLATED POWER MODULE (37KVA - 375W)

I

ABSOLUTE MAXIMUM RATINGS
VCBO
VCES
VCEX
VCEO
VCEOL
VEBO
Ic
ICM
Icp
IB
IBP
Ts1g
Tj
Tj

SGS5ODA045D

Collector-base voltage (IE = 0)
Collector-emitter voltage (VBE = 0)
Collector-emitter voltage (V BE = -1 .5V)
Collector-emitter voltage (lB = 0)
Overload switch-off at 1.5 times Ic (sat)"
Emitter-base voltage (Ic = 0)
Collector current
Collector peak current (tp<1 0 ms)
Collector peak current non repetitive (tp<20 [ls)
Base current
Base peak current non repetitive (tp<20 [ls)
Storage temperature
Max. operating junction temperature (continuous)
Max. operating junction temperature (1 minute)

INTERNAL SCHEMATIC
DIAGRAM

FAST FREEWHEEL DIODE

850
850
850
450
500
7
75
120
300
3
10
-40t0150
150
175

MECHANICAL DATA

1019

V
V
V
V
V
V
A
A
A
A
A

°C
°C
°C

Dimensions in mm

08/85

SGSSODA04SD

ELECTRICAL CHARACTERISTICS
Parameter
Diode forward
voltage

I, = 50 A

trr

Diode reverse
recovery time
Diode reverse
recovery current

1,= 50A

Diode forward
current

t = 1ms

I',m

Min. Typ. Max. Unit

Test Conditions

V,

Irm

(Continued)

Tj = 25°C
Tj = 125°C
dildt = 100Al!-ls

1.60 2.2
1.70

V
V

0.20 0.5

!-Is

12

250

A

A

INSULATION TESTING
The insulation betweel\. the live parts and the base plate of TO·240 is tested before delivery for one
second at 2500 V a.c.
If this test is repeated by the user either as a goods inwards check or as a test of the final equipment, in accordance with IEC Publication 146 (1973), clause 492.1 or DIN 57558 part 1NDE 0558,
part 1/8.77, section 5.7.9., only a voltage slowly increasing up to the above value should be used.
If the voltage is applied for one minute as recommended by the above standards then the specified
value of 2000 V should be taken.
During the test all electrical terminals including the drive terminals must be connected with each
other in order to avoid damage by inductively or capacitively induced voltage transients. The test
voltage is applied between the connected terminals and the base plate.

Safe operating areas
GC 0261

Icl~ )

,
6

2

PULSE OPERATION
Ie MAX PULSED /

100 s-pti

Ie MAX
CONT.

40

1m.

2

10'

*t:tttt1

"--------------

102B

DC OPERATION

f-"\

'\.

B

6

*

For single non
repetetive pulse

,

100

"\

IOms

..

,E

6

1=

,
.

r2

",.:-,"

-

I

..

F

1+

I

1021

SGS5ODA045f)

Collector overload SOA (see fig. 1)

Base-emitter saturation voltage

OC-0030

I.(A)

G -0028

VBElsat)

IV)

~

~ ~ P""

~

:.- ~ / / .....

TJ'-40

...y. r"" V '"

hFE·25

Tj'2~

/

'p'20)"

I--

ReEl =150Q

r--

RaE2 '270

Tj=125"C

Tj<125"C

o
50

O.

Reverse biased SOA (see fig. 2)

Switching times inductive load (see fig. 3)
~.)

GC 0232

IeIAI

lelA!

GC-0033

10

,
-f-

70

60

r- -

c-

f-- -

r-

~

50
VBEoff=-5V

TI"125'C

40

---

'F

-c;

1/

0.1

f-- _.

20

"200

400

,'1

tf=25"C

1

'1-

--

hFE '25
VBEo!! '-5V

10

1023

=
=
-

I

0.01

600 800 1000

I

Vel =300V

1\

10

'f" 25 'C

I

V ,/

f-- f-- f--.
. p.- i=-

,;.;;ii

..-

~

30

o

~

ts=125"C

ts=25"C

20

30

40

50

lo(A)

Fig. 2 RBSOA TEST CIRCUIT
RBSOA test circuit has been driven by
the switching times test circuit
with

RB2 =

O.

RBSOA sensitivity to Tj variations

tp adjusted for

is very limited, so that the limits shown
can be kept valid at ambient temperature

nominal ic

as well.

ic / ib

=25

Vclamp

SC-0002

Fig. 3 Switching times test circuit.

tpIl

L=100)lH

D.U.T.

Vclamp
300V
External
speed-up diode

SC-0004

1025

II.
TRANSPACK NPN POWER DARLINGTON MODULE
APPLICATIONS:

The SGS50DB040D and SGS50DB045D are silicon NPN power fast darlingtons in half bridge configuration for industrial switching applications from
the mains.

ISOLATED POWER MODULE (26KVA-375W)

FAST FREEWHEEL DIODES

ABSOLUTE MAXIMUM RATINGS

SGS50DB040D SGS50BD045D

VCBO Collector-base voltage (IE = 0)
VCES Collector-emitter voltage (VaE = 0)
VCEX Collector-emitter voltage (VaE = -1.5V)
VCEO Collector-emitter voltage (Ia = 0)
VCEOL Overload switch-off at 1.5 times Ie (sat)"
VEao Emitter-base voltage (Ie = 0)
Ie
Collector current
leM
Collector peak current (lp<1 0 ms)
Icp
Collector peak current non repetitive (lp<20 IJS)
la
Base current
lap
Base peak current non repetitive (tp<20 IJS)
Tstg Storage temperature
Max. operating junction temperature (continuous)
Tj
Tj
Max. operating junction temperature (1 minute)

INTERNAL SCHEMATIC
DIAGRAM

500
500
500
400
400
7
75
120
250
10
20
- 40 to 150
150
175

MECHANICAL DATA

~

T

Dimensions in mm

ZINC PLATED M5>18
EW ZINC I'LAjIO MhlO
KWASHER

i ,

~SHERI:l\tllCPLATIlD

ij FASTON' 3.7114,5 TIIfIEO BRAS!!

6

2S>

rJ' "
4

V
V
V
V
V
V
A
A
A
A
A
°C
°C
°C

600
600
600
450

lIjD HEXAGONA~

'1"10""

,~
NUT ZINC Pl;A lID MIi.M

TO-240AA

1027

08/85

L

,

ELECTRICAL CHARACTERISTICS
Parameter

Vf

t"
Irm

Ifrm

(Continued)

Test Conditions

Diode forward
voltage

If
If

= 50A
= 50 A

Tj

Diode reverse
recovery time
Diode reverse
recovery time

If

= 50 A

dildt

Diode forward
current

t

Min. Typ. Max. Unit

= 125°C
= 100Alf.ls

1.4
1.5

2

V
V

0.2

0.5

f.lS

10

= lms

A

250

A

INSULATION TESTING
The insulation between the live parts and the base plate of TO·240 is tested before delivery for one
second at 2500 V a.c.
If this test is repeated by the user either as a goods inwards check or as a test of the 'final equip·
ment, in accordance with IEC Publication 146 (1973), clause 492.1 or DIN 57558 part llVDE 0558
part 1/8.77, section 5.7.9., only a voltage slowly increasing up to the above value should be used.
If the voltage is applied for one minute as recommended by the above standards then the specified
value of 2000 V should be taken.
During the test ali electrical terminals including the drive terminals must be connected with each
other in order to avoid damage by inductively or capacitively induced voltage transients. The test
voltage is applied between the connected terminals and the base plate.
Safe operating areas for each section

DC current gain
GC 0270

Jt·

..J..
"

,

'I'
VCE =51

I

la' ,
6

/ . ::::::: ~
~~ ~~

I

100

,

100

TI=125°C/

;1
IO-~

TI=25 0 C/"

6

V

r;=-40 0 C
10
I

1029

6

810

•

'ielAI

SGS50DB040D
$G$50DB045D

Typical VF versus

Reverse biased SOA (see fig. 2)

~Ic

GC-0268

Ic lAI
.......

70

GC-OOI9

~.

60

2

50
40
30

\.5

r-r-

V BEotf=-5V

A

T J

-

f--

o

GC04
- 0 9

It,(A)

tp-.20)lS

f-- -

RSEI-150Q

-

RBE2=27c
Tj .. 125·C

RBE2-27g

f--

TJ-

11.

TO-3

2.5

(sim. to TO-218) SOT -93

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

1059

10/84

SGS10004
SGS10004P
SGS10005
SGS10005P

ELECTRICAL CHARACTERISTICS (continued)
Parameter
V/

Diode forward voltage

Test conditions

Min. Typ. Max. Unit

IF = lOA

3

V

5

-

h fe

COB

Small-signal current
gain

Ic = lA
VCE = 10V
f test = lMHz

Output capacitance

V CB = 10V IE = 0
f test = 100MHz

ton

Turn-on time

tr

tf

-

10

100

325

pF

0.22

0.8

JlS

Rise Time

Vec=250V Ie =8A
IBI = -IB2 = 400mA
V BE (Off) = 5V

0.6

1.5

JlS

Fall time

tp = 50Jls duty cycle';;;; 2%

0.15

0.5

JlS

--~

* Pulsed: pulse duration = 300Jls duty cycle = 1.5% .

1061

8.
HIGH VOLTAGE, HIGH POWER, FAST SWITCHING
• INTEGRATED SPEED-UP DIODE
• MOTOR CONTROLS
The SGSDOOO31, SGSOOO30 and SGSID312 are silicon multiepitaxial planar NPN transistors in monolithic darlington configuration with integrated
speed-up diode, mounted respectively in Jedec TO-3
metal case, SOT-93 plastic package and
ISOWATT218 fully isolated package.
No parasitic collector-emitter diode, so that an external fast recovery free wheeling diode can be
added.
They are particulary suitable as output stage in high
power, fast switching applications.

T0-3

SOT-93 (TQ-218)

ISOWATT218
INTERNAL SCHEMA TIC DIAGRAM

,----- -

I

I

I

-.J

ABSOLUTE MAXIMUM RATINGS
V CER
V CEO
Ic
leM
IB
IBM

Collector-emitter voltage (RBE = 50 ohm)
Collector-emitter voltage (lB = 0)
Collector current
Collector peak current (tp ~ 1Oms)
Base current
Base peak current (tp ~ 10ms)

VISO
Ptot
Tstg
Tj

Isolation voltage (DC)
Total dissipation at Tc ~ 25°C
Storage temperature
Max. operating junction temperature

TO·3

1063

150
-65 to 175
175

600
400
28
40
6
12
SOT·93

V
V
A
A
A
A
ISOWATT218

V
4000
125
50
W
-65 to 150 -65 to 150°C
150
150
°C
11/86

THERMAL RESISTANCE OF THE ISOWATT218
The junction to case thermal resistance of 2.5

°C/W for the ISOWATT218 package may seem
quite high at first glance but if compared to
a conventional SOT-93 (TO-218) package
with a 0.1 mm mica insulating washer, the differences are marginal. The 0.1 mm isolating
washer gives 1500V to 2000V DC isolation
for the SOT-93 package, SGS guarantee
4000V DC isolation for the ISOWATT218.

The comparison in fig. 1 ,shows the dynamic
thermal resistance of both devices mounted
using a thermal compound. The test illustrates
that the ISOWATT218 has an Rth very close
to that of conventional SOT-93 (TO-218) and
any small increase is more than compensated
for by the convenience of the ISOWATT~18
package. The collector to heatsink capaCitance of the ISOWATT218 is typically 17pF.

10l ,..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...:G=.U."'..-':.:.29:.......,

Fig. 1

ZIh
(OCIWl

102

THERMAL IMPEDANCE - TIME
WI TH A SMALL HEATSINK
ISOWATT218

'"

SOHl

•

mica thickness - 0,1 mm
10

1iJl
TIME(secl

Safe operating area
(TO -3)

,~',: .,,".'
"

~~~~D'

DC current gain
hFE

PUI.. . D

K"

...

l~

C

-

'--

,.'

VeE" V

./

~E.s~~

'\
~-

\.

lOJ

,.

.

,.

r--

Tc,I5.... ZS"'C

I
10

'0'
1065

'cIA)

Clamped reverse bias safe
operating areas

TEST CIRCUIT
Fig. 2

32

vee

--r-+--r-r-+-1--j--1-~-~

80439
Tca.. =125°C

20

200

ZL

n

24r-+-+--r-r-+-1--rV~~=,-5~V,-~
-1--+-+-+-~--+-+---<1--+-1

I

Vo

1\

\

200

400

r
600

Vi

80440

47P l' F

s- 6600

1067

I
I-

HIGH VOLTAGE, HIGH POWER, FAST SWITCHING
• INTEGRATED SPEED-UP DIODE
• MOTOR CONTROLS
The SGSD310, SGSD311 and SGSID311 are silicon
multiepitaxial planar NPN transistors in monolithic darlington configuration with integrated speed-up diode, mounted respectively in Jedec TO-3 metal case,
SOT-93 plastic package and ISOWATT218 fully isolated package.
No parasitic collector-emitter diode, so that an external fast recovery free wheeling diode can be
added.
They are particulary suitable as output stage in high
power, fast switching applications.

T0-3

SOT·93 (T0-218)

ISOWATI218
INTERNAL SCHEMATIC DIAGRAM

ABSOLUTE MAXIMUM RATINGS
VCER
VCEO
Ic
ICM
IB
IBM

Collector-emitter voltage (R BE = 50 ohm)
Collector-emitter voltage (lB = 0)
Collector current
Collector peak current (tp ,.; 10ms)
Base current
Base peak current (tp ,.; 10ms)

Visa
Ptat
Tstg
Tj

Isolation voltage (DC)
Total dissipation at Tc ,.; 25 a C
Storage temperature
Max. operating junction temperature

TO-3

1069

150
-65 to 175
175

600
400
28
40
6
12
SOT-93

V
V
A
A
A
A

ISOWATT218
4000
V
125
W
50
-65 to 150 -65 to 150 ac
ac
150
150
11/86

L

THERMAL RESISTANCE OF THE ISOWATT218
The junction to case thermal resistance of 2.5

The comparison in fig. 1 shows the dynamic

°CIW ·for the ISOWATT218 package may seem thermal resistance of both devices mounted
quite high at first glance but if compared to
a conventional SOT-93 (TO-218) package
with a 0.1 mm mica insulating washer, the differences are marginal. The 0.1 mm isolating
washer gives 1500V to 2000V DC isolation
for the SOT-93 package, SGS guarantee
4000V DC isolation for the ISOWATT218.

using a thermal compound. The test illustrates
that the ISOWATT218 has an Rth very close
to that of conventional SOT-93 (TO-218) and
any small increase is more than compensated
for by the convenience of the ISOWATT218
package. The collector to heatsink capacitance of the ISOWATT218 is typically 17pF.

,01y-_ _ _ _ _ _._ _ _ _ _ _ _ _ _ _ _ _

Fig. 1

ZItl

..

~G!'=lU.:,!;~1.!_..,

THERMAL IMPEDANCE - TIME
WI TH A SMALL HEATSINK

("eM

,rI

ISOWATT218

•

SOHl

•

mica thickness -

0,1 mm

'0

,Q3
TIME(seci

Safe operating area
(TO-3)

Ic'~~~:~IP§ill

1,._..
{AI:~IcM.u
I

PULSEO

Safe operating area
(SOT -93/ISOWA TT218l ,"
I(,IAJ.

: Ie MAX

~

! !1!:'~

"

,r~·T-"f-. ;.::~:...'

PULSE.D .. PULS.~_ ~~T~~

ICMAA

tONtOC

IO"'--,~~,:U,--!,-'-!."",~,;"-+-,+'i..lJ"
10

10J

1071

.

DC current gain

Clamped reverse bias safe
operating areas

TEST CIRCUIT
Fig. 2

Vee
o--------~~~~~

60439

200

n

24

20~+-+-~-r-+-4--~+-+-~

12

I--+--+--+----,\--+---j-I--+--+--I

1\

\

200

400

600

800

VC[(V)

son

470 fJ F

s-

1073

6600

lB.
HIGH SPEED SWITCHING APPLICATIONS
These products are diffused multi-cell silicon gate
N-Channel enhancement mode Power-Mos field
effect transistors.

ABSOLUTE MAXIMUM RATINGS

Voss

ROSION)

10

50V/60V

0.130

10A

SOT-82
TO-220
SOT-93
TO-3

Drain-source voltage (V GS = 0)
Drain gate voltage (R GS = 20Kn)
Gate-source voltage
Drain current (continuous) at Tease = 2SoC
at Tease = 100°C
Drain current (pulsed)
Drain inductive current, clamped

Tstg

lj

Total power dissipation at Tease .;;; 2SoC
Derating factor
Storage temperature
Junction temperature

SGSP221
SGSP321
SGSP421
SGSPS21

SGSP222
SGSP322
SGSP422
SGSP522

60V
60V

50V
SOV
±20V
10A
6.5A
40A
40A

SOT-82
50W
0.4Wf'C

TO-220/S0T93/TO-3
75W
0.6Wf'C

-55 to 150°C
150°C

(e) Pulse width limited by safe operating area

INTERNAL SCHEMATIC

DIAG:~

s

MECHANICAL DATA

Dimensions in mm

Drain connected to case

Drain connected to tab

Drain connected to tab

Drain connected to tab

TO-3

(sim.to TO-218)SOT-93

TO-220

SOT-82

1075

9/85

ELECTRICAL CHARACTERISTICS (Continued)
Test conditions

Parameter

SWITCHING
td(on)
tr
td(off)
tf

Turn-on delay time
Rise time
Turn-off delay time
Fall time

Vj = 10V
Vee = 25V
10 = 5A
Rj =50,Q
(see test circuit)

30
130
80
130

ns
ns
ns
ns

SOURCE DRAIN DIODE

150M (e)

SOljrce-drain current
Source-drain current
(pulsed)

Vso

Forward on voltage

Iso

V GS

=0

ton
trr

Turn-on time
Reverse recovery time

di/dt = 25A/fJ$
Iso = 10A
V GS

=0

Iso

= 10A

Pulsed: pulse duration';;;; 300 fJ$. duty cycle';;;; 2%
(e) Pulse width limited by safe operating area

1077

60
100

10
40

A
A

1.4

V
ns
ns

!-

II.
HIGH SPEED SWITCHING APPLICATIONS
These products are diffused multi-cell silicon gate
N-Channel enhancement mode Power-Mos field
effect transistors.

ABSOLUTE MAXIMUM RATINGS

ROSION)

10

200V

0.330

10A

250V

0.450

10A

T0-220
SOT-93
TO-3

Drain-source voltage (V GS = 0)
Drain-gate voltage (R GS = 20Kn)
Gate-source voltage
Drain current (continuous) Tease = 25°C
Tease = 100°C
Drain current (pulsed)
Drain inductive current, clamped

Tstg
Tj

Voss

SGSP363
SGSP463
SGSP563

SGSP367
SGSP467
SGSP567

250V
250V

200V
200V
±20V

lOA
6.4A
40A
40A

TO-220
SOT -93/TO-3
100W
125W
125W
0.8Wf'C
lW/oC lW/oC
- 55 to 1500 C
150°C

Total power dissipation T case = 25°C
Derating factor
Storage temperature
Junction temperature

(e) Pulse width limited by safe operating area

INTERNAL SCHEMATIC DlAGR,~

MECHANICAL DATA

Drain connected to tab

5

Dimensions in mm

Drain connected to case

Drain connected to tab

G ---':l~r.
_--;k';;;-iL - t

o

....... ----Mi.

5

(sim. to TO-218) SOT -93

TO-3

1079

TO-220

9/85

ELECTRICAL CHARACTERISTICS (continued)
Parameter

Test conditions

DYNAMIC
C;ss
C oss
Crss

I nput capacitance
Output capacitance
Reverse transfer
Capacitance

Vos=25V
V GS = 0

f = 1 MHz

980
200
80

1200
260
100

pF
pF
pF

SWITCHING
td (on)
t,
td (off)
tf

Turn-on delay time
Rise time
Turn-off delay time
Fall time

Vee = 25V

V j = 10V
= 5A
Rj =15 Q
(see test circuit)

ID

10
25
50
32

ns
ns
ns
ns

SOURCE DRAIN DIODE
Iso
IsDMO

Source drain current
Source drain current
(pulsed)

Vso

Forward on voltage

Iso =10A

V GS = 0

ton
t"

Turn-on time
Reverse recovery time

lOA

V GS = 0

di/dt = 100A/Ms

ISD =

* Pulsed: pulse duration.;; 300J.Ls, duty cycle.;; 0.2%
(.) Pulse. width limited by safe operating area

1081

130
250

10
40

A
A

1.3

V

ns
ns

aB.
HIGH SPEED SWITCHING APPLICATIONS
RoS (on)

10

350/400 V

1 ()

6A

450 V

1.5 ()

6A

Voss

• HIGH VOLTAGE - FOR ELECTRONIC
LAMP BALLAST

T0-220

• ULTRA FAST SWITCHING

SOT·93 (T0-218)

• EASY DRIVE - REDUCES COST AND SIZE

INDUSTRIAL APPLICATIONS:
• ELECTRONIC LAMP BALLAST
• DC SWITCH
N-Channel enhancement mode POWERMOS field
effect transistors. Easy drive and very fast switching times make these POWERMOS transistors ideal
for high speed switching applications.
Applications include DC switch, constant current
source, ultrasonic equipment and electronic
ballast for fluorescent lamps.
The package range for this device includes the
isolated case ISOWATT218. This provides isolation to 2500V ac, 4000V dc and the creepage
distance requirement of VDE, IEC and UL
specifications.

ABSOLUTE MAXIMUM RATINGS

VOS
V OGR
V GS
10
10M(.)
10LM

V ISO
Ptot
T stg
Tj

TO·220
SOT·93
ISOWATT218
TO·3

Drain-source voltage (VGS = 0)
Drain-gate voltage (RGS = 20KO)
Gate-source voltage
Drain current (continuous) Te = 25°C
at Te = 100°C
Drain current (pulsed)
Drain inductive current, clamped

by

safe operating area.

INTERNAL SCHEMATIC DIAGRAM
D

,~
5

SGSP364
SGSP464
SGSIP464
SGSP564

SGSP365 SGSP366
SGSP465 SGSP466
SGSIP465 SGSIP466
SGSP565 SGSP566

450
450

400
350
400
350
± 20
6
4
24
24
TO-220 SOT-93 ISOWATI218 TO-3

4000

Isolation voltage (DC)
Total dissipation at Tease = 25°C
Derating factor
Storage temperature
Max. operating junction temperature

(.) Pulse width limited

T0-3

ISOWATT218

100
0.8

1083

50
125
0.4
1
-55 to 150
150

V
V
V
A
A
A
A

V
125 W
1 W/oC
°C
°C

11/86

ELECTRICAL CHARACTERISTICS (continued)
Parameter

Test conditions

DYNAMIC
gfs

Forward
transconductance

Ciss
Coss
Crss

Input capacitance
Output capacitance
Reverse transfer
capacitance

CO-HS

Drain-Heatsink
capacitance

Vos = 25V

10 = 3A

Vos = 25V
V GS = 0

f = 1 MHz

780
150
100

1000
200
130

pF
pF
pF

VO-HS = 25V f = 1 MHz

19

23

pF

Vee = 250V
10= 3A
Vi = 10V
Ri = 100
(see test circuit)

30
30
100
50

mho

3

SWITCHING
td(on)
tr
td(off)
tf

Turn-on time
Rise time
Turn off delay time
Fall time

ns
ns
ns
ns

SOURCE DRAIN DIODE
Source-Drain current
Iso
ISOM (e) Source-Drain current
(pulsed)
Vso

Forward on voltage

Iso = 6A

ton
trr

Turn-on time
Reverse recovery
time

V GS = 0
Iso = 6A
di/dt = 25AIp.s

V GS = 0

* Pulsed: Pulse duration = 300IlS, duty cycle 1.5%
(e) Pulse width limited by safe operating area

1085

250
350

6
24

A
A

1.2

V
ns
ns

HIGH SPEED SWITCHING APPLICATIONS
Voss

Ros

(on)

500V

1.5 Q

550V

2.5 Q

10

'.~
~ ....

SA
SA

~.

..•.....

.

.

• HIGH VOLTAGE - FOR ELECTRONIC LAMP
BALLAST AND SMPS

SOT·93 (TO·218)

TO·220

• ULTRA FAST SWITCHING - UP TO 200KHz
OPERATIONS
• EASY DRIVE - REDUCES COST AND SIZE
INDUSTRIAL APPLICATIONS:
• SMPS
• ELECTRONIC LAMP BALLAST

N-Channel enhancement mode POWER MOS field effect transistors. Easy drive and very fast switching
times make these POWER MOS transistors ideal for
high speed switching applications.
Applications include DC switch, constant current
source, ultrasonic equipment electronic ripple control and electronic ballast for fluorescent lamps.
The package range for this devices includes the isolated case ISOWATT218. This provides isolation to
2500V ac, 4000V dc and the creepage distance requirement of VDE, IEC, and UL specifications.

ABSOLUTE MAXIMUM RATINGS

V DS
V DGR
V GS
ID

TO·220
SOT·93
ISOWATT218
TO·3

INTERNAL SCHEMATIC DIAGRAM

s

SGSP368
SGSP468
SGSIP468
SGSP568

SGSP369
SGSP469
SGSIP469
SGSP569

550
550

500
500

Drain-source voltage (VGS = 0)
Drain-gate voltage (R GS = 20KQ)
Gate-source voltage
Drain current (continuous) Tc = 25 DC
at Tc = 100 D C
Drain current (pulsed)
Drain inductive current, clamped

1087

V
V
V
A
A
A
A

±

20
5
3.2
20
20

TO-220
Isolation voltage (DC)
Total dissipation at Tease
25 DC
Derating factor
Storage temperature
Max. operating junction temperature
(el Pulse width limited by safe operating area.

TO-3

ISOWATT218

• DC SWITCH

100
0.8

SOT-93 ISOWATT218
4000
125
50
0.4
-55 to 150
150

TO-3
V
125 W
1 W/DC
DC
DC
11/86

1-

ELECTRICAL CHARACTERISTICS
Parameter

(continued)

Test conditions

SWITCHING
td (onl
tr
td(offl
tf

Turn-on time
Rise time
Turn off delay time
Fa" time

Vcc=250V lo=2.5A
Vi = 10V Ri = 100
(see test circuit)

30
15
80

ns
ns
ns
ns

40

SOURCE DRAIN DIODE
150M (.)

Source-Drain current
Source-Drain current
(pulsed)

Vso

Forward on voltage

Iso = 5A

ton
t"

Turn-on time
Reverse recovery
time

Iso = 5A V GS = 0
di/dt = 150A/p.S

Iso

• Pulsed: Pulse duration

= 300/l1s.

duty cycle

V GS = 0

1.5%

(-I Pulse width limited by safe operating area

1089

85
320

5
20

A
A

1.15

V
ns
ns

aB.

PRELIMINARY DATA

N-CHANNEL POWER MOS TRANSISTORS
HIGH SPEED SWITCHING APPLICATIONS
These products are diffused multi-cells silicon gate
N-Channel enhancement mode Power-Mos field
effect transistors.

Voss

ROS

60V

0.040

40A

50V

0.040

40A

10

(on)

TO-220

q

• HIGH CURRENT

SOT-93

TO-3

• VERY LOW THERMAL RESISTANCE
• VERY LOW ON-LOSSES

INTERNAL SCHEMATIC DIAGRAM

• EASY DRIVE
AUTOMOTIVE APPLICATIONS
• POWER ACTUATORS

o

,~
5

ABSOLUTE MAXIMUM RATINGS
VOS
V OGR
V GS
10
10M(-)
10LM

Ptot
T stg
Tj

TO-220
SOT-93
TO-J

Drain-source voltage (V GS = 0)
Drain-gate voltage (R GS = 20KO)
Gate-source voltage
Drain current (continuous) Tease = 25 ° C
at
Tease = 100 0 C
Drain current (pulsed)
Drain inductive current, clamped
Total dissipation at
Tease = 25°C
Derating factor
Storage temperature
Max. operating junction temperature

SGSP386
SGSP486
SGSP586

SGSP387
SGSP487
SGSP587

60
60

50
50
±20
40
25
120
120
125
1
-55 to 150
150

V
V
V
A
A
A
A
W
W/oC
°C
°C

• Pulse width limited by safe operating area

1091

03/86

ELECTRICAL CHARACTERISTICS
Parameter

(continued)

Test conditions

SWITCHING
td lonl
t,
td loff!
tf

Turn-on delay time
Rise time
Turn-off delay time
Fall time

Vee = 30V 10= 15A
VGs= 10V RGs= 500
(see test circuit)

40
150
150
180

ns
ns
ns
ns

SOURCE DRAIN DIODE
Source-Drain current
Iso
150M (e) Source-Drain current
(pulsed)
Vso

Forwaed on voltage

VGs=O

Iso = 40A

trr

Reverse recovery
time
Reverse recovered
charge

Iso = 40A

di/dt = 100 A/f.-Is

Orr

* Pulsed: Pulse duration = 300 f.-IS, duty cycle 1.5%
(e)

Pulse width limited by safe operating area.

1093

40
120

A
A

1.8

V

80

ns

0.2

f.-IC

II.
HIGH SPEED SWITCHING APPLICATIONS
Voss

RoS (on)

10

200 V

0.17

n
0.22 n

20 A

250 V

20 A

• 200-250V - FOR TELECOMS APPLlCAr:IONS
•

HIGH CURRENT - FOR PULSED LASER DRIVES

•

ULTRA FAST SWITCHING

•

EASY

DRIVE -

ISOWATT218

SOT-93 (T0-218)

REDUCES COST AND SIZE

INDUSTRAIL APPLICATIONS:
• SWITCH ING MODE POWER SUPPLY
•

MOTOR CONTROL FOR ROBOTICS

N-Channel enhancement mode POWERMOS field effect transistors. Easy drive and fast switching times
make these POWERMOS transistors ideal for high
speed switching applications.
Typical applications include electronics, laser diode
drivers, UPS, SMPS, ~C/DC, DC switch for telecoms
and electronic vehicle drivers.
The package range for this device includes the isolated case ISOWATT218. This provides isolation to
2500V ac, 4000V dc and the creepage requirements
of VDE, IEC and UL specifications.

T0-3
INTERNAL SCHEMATIC DIAGRAM

5

ABSOLUTE MAXIMUM RATINGS

Vos
V OGR
V GS
10
10M(·)
10LM

VIsa
Ptot
Tstg
Tj
'0)

SOT·93
ISOWATT218
TO·3

Drain-source voltage (VGS = 0)
Drain-gate voltage (R GS = 20KO)
Gate-source voltage
Drain current (continuous) Te = 25°C
at Te = 100°C
Drain current (pulsed)
Drain inductive current, clamped
Isolation voltage (DC)
Total dissipation at Tease
25°C
Derating factor
Storage temperature
Max. operating junction temperature

Pulse width limited

=

by

safe operating area.

1095

SGSP473
SGSIP473
SGSP573

SGSP477
SGSIP477
SGSP577

250
250

200
200

""'iJ

V
20
V
20
A
13
A
80
A
80
A
SOT-93 ISOWATT218 TO-3
4000
V
150
W
150
50
0.4
1.2 W/oC
1.2
-55 to 150
°C
150
°C

±

ELECTRICAL CHARACTERISTICS
Parameter

(continued)

Test conditions

DYNAMIC
gfs

Forward
transconductance

Ciss
Coss
Crss

Input capacitance
Output capacitance
Reverse transfer
capacitance

C O-HS

Drain-Heatsink
capacitance

Vos = 25V

10 = lOA

VOS = 25V
V GS = 0

f = 1 MHz

mho

8

1900 2200
450 550
200 260

V O-HS = 25V f = 1 MHz

19

Vcc= 75V
10= lOA
Vi = 10V
Ri = 100
(see test circuit)

30
25
90
20

23

pF
pF
pF

pF

SWITCHING
td(on)
tr
td(off)
tf

Turn-on time
Rise time
Turn off delay time
Fall time

ns
ns
ns
ns

SOURCE DRAIN DIODE
Source-Drain current
Iso
ISOM (e) Source-Drain current
(pulsed)
V GS = 0

Vso

Forward on voltage

Iso = 20A

ton
trr

Turn-on time
Reverse recovery
time

V GS = 0
Iso = 18A
di/dt = 100Af-'S

* Pulsed: Pulse duration = 300 fLS, duty cycle 1.5%
(e) Pulse width limited by safe operating area

1097

300
300

20
80

A
A

1.3

V
ns
ns

II.
HIGH SPEED SWITCHING APPLICATIONS
Voss

RoS

10

(on)

350/400 V

0.55 [)

12 A

450 V

0.7 [)

12 A

• HIGH VOLTAGE - FOR OFF-LINE SMPS
• HIGH CURRENT - FOR UP TO 350W

SOT-93 (T0-218)

• ULTRA FAST SWITCHING - FOR OPERATION
AT ~ 100KHz

ISOWATI218

Q

• EASY DRIVE - REDUCES SIZE AND COST
INOUSTRIAL APPLICATIONS:

II

• SWITCHING MODE POWER SUPPLIES
• MOTOR CONTROLS

TO-3

N-Channel enhancement mode POWERMOS field effect transistors. Fast switching and easy drive make these POWERMOS transistors ideal for high
voltage switching applications.
These applications include electronic welders, switched mode power supplies and sonar equipment.
The package range for this devices includes the isolated case ISOWATT218. This provides isolation to
2500V ac, 4000V dc and the creepeage distance
requirement of VDE, IEC and UL specifications.

INTERNAL SCHEMATIC DIAGRAM
D

,~
5

ABSOLUTE MAXIMUM RATINGS

Vos
V OGR
V GS
10
10M(·)
10LM

Visa
Ptot
T stg
Tj
(0)

SOT-93
ISOWATT218
TO-3

Drain-source voltage (V GS = 0)
Drain-gate voltage (R GS = 20KO)
Gate-source voltage
Drain current (continuous) Tc = 25°C
at Tc = 100°C
Drain current (pulsed)
Drain inductive current, clamped
Isolation voltage (DC)
Total dissipation at Tease = 25°C
Derating factor
Storage temperature
Max. operating junction temperature

Pulse width limited

by

safe operating area.

1099

SGSP474 SGSP475
SGSIP474 SGSIP475
SGSP574 SGSP575
450
450

400
400
± 20
12

SGSP476
SGSIP476
SGSP576
350
350

7.6
48
48
SOT-93 ISOWATT218
4000
150
50
1.2
0.4
-55 to 150
150

V
V
V
A
A
A
A

TO-3
V
150
W
1.2 W/oC
°C
°C
11/86

L
SGSP474/P475/476
SGSIP474/1P475/1P476
SGSP574/P575/P576

ELECTRICAL CHARACTERISTICS
Parameter

(continued)

Test conditions

DYNAMIC
gfs

Forward
transconductance

Ciss
Coss
Crss

Input capacitance
Output capacitance
Reverse transfer
capacitance

C O-HS

Drain-Heatsink
capacitance

Vos = 25V 10 = 6A

Vos = 25V f= 1 MHz
V GS = 0
V O-HS = 25V f = 1 MHz

mho

6

1600 2100
300 390
200 260

19

23

pF
pF
pF

pF

SWITCHING
td(on)
tr
td(off)
tf

Turn-on time
Rise time
Turn off delay time
Fall time

Vee = 100V 10= 6A
Vi = 10V Ri = 4.70
(see test circuit)

20
25
70
20

ns
ns
ns
ns

SOURCE DRAIN DIODE
Source-Drain current
Iso
'ISOM (e) Source-Drain current
(pulsed)
Vso

Forward on voltage

Iso = 12A

ton
t"

Turn-on time
Reverse recovery
time

Iso = 12A V GS = 0
di/dt = 25A fLS

V GS = 0

* Pulsed: Pulse duration = 300 fLS, duty cycle 1.5%
(e) Pulse width limited by safe operating area

1101

700
800

12
48

A
A

1.2

V
ns
ns

II.
HIGH SPEED SWITCHING APPLICATIONS
Voss

Ros

(on)

10

500V

0.7 Q

10A

550V

1Q

10A

• HIGH VOLTAGE - 500 FOR OFF-LINE SMPS
• HIGH CURRENT - 10A FOR UP 350W SMPS

ISOWATT218

SOT-93 (T0-218)

• ULTRA FAST SWITCHING - FOR OPERATION
AT ~ 100KHz
• EASY DRIVE - REDUCES COST AND SIZE
INDUSTRIAL APPLICATION:
• SWITCHING MODE POWER SUPPLIES
• MOTOR CONTROL

T0-3

N-Channel enhancement mode POWER MOS field effect transistors. Easy drive and very fast switching
times make these POWER MOS transistors ideal for
high speed switching applications.
Typical apliillications include switched mode power
supplies, uninteruptable power supplies and motor
speed control.
The package range for this devices includes the isolated case ISOWATT218. This provides isolation to
2500V ac, 4000V dc and the creepage distance requirement of VDE, IEC, and UL specifications.

ABSOLUTE MAXIMUM RATINGS

VOS
V OGA
V GS
10
10M(.)
10LM

V ISO
Ptot
Tstg
Tj

SOT·93
ISOWATT218
TO-3

Drain-source voltage (V GS = 0)
Drain-gate voltage (R GS = 20KQ)
Gate-source voltage
Drain current (continuous) Te = 25°C
at Te = 100°C
Drain current (pulsed)
Drain inductive current, clamped
Isolation voltage (DC)
Total dissipation at Tease = 25°C
Derating factor
Storage temperature
Max. operating junction temperature

I-I Pulse width limited

by

INTERNAL SCHEMATIC DIAGRAM

5

SGSP478
SGSIP478
SGSP578

SGSP479
SGSIP479
SGSP579

550
550

500
500

±

V
V
V
A
A
A
A

20
10
6.3
40
40
SOT-93IS0WATT218
TO-3
4000
V
150
50
150
W
1.2 W/oC
1.2
0.4
-55 to 150
°C
150
°C

safe operating area.
1103

11/86

ELECTRICAL CHARACTERISTICS (continued)
Parameter

Test conditions

SWITCHING
td (on)
tr
td(off)
~

Turn-on time
Rise time
Turn off delay time
Fail time

Vcc=250V 10= 5A
Vi = 10V Ri = 100
(see test circuit)

25
30
80
20

ns
ns
ns
ns

SOURCE DRAIN DIODE
Source-Drain current
Iso
ISOM (e) Source-Drain current
(pulsed)
Vso

Forward on voltage

Iso = 10A V GS = 0

ton
ttr

Turn-on time
Reverse recovery
time

Iso = 10A V GS = 0
di/dt = 100A/".s

• Pulsed: Pulse duration = 300/1'5. duty cycle 1. 5%
(0) Pulse width limited by safe operating area

1105

75
500

10
40

A
A

1.15

V
ns
ns

II.

ADVANCE DATA

HIGH SPEED SWITCHING APPLICATIONS
Voss

RoS (on)

10

200V

0.1000

19A

• FULLY ISOLATED PACKAGE
• 200 VOLTS - FOR SMPS UPS AND DC/DC
CONVERTERS
• ULTRA FAST SWITCHING
• EASY DRIVE - REDUCES EQUIPMENT SIZE
AND COST
INDUSTRIAL APPLICATIONS:
• DC/DC CONVERTERS
• MOTOR CONTROLS
• ROBOTICS
N-Channel enhancement mode POWER MOS field effect transistors. Easy drive, very fast switching times and simple mounting make these POWER MOS
transistors ideal for high speed switching applications
in a wide range of equipment.
The ISOWATT218 package requires only simple single hole mounting and provides isolation to 2500V
ac, 4000V dc. and meets with the creepage distance requirements of VDE, IEC, and UL specifications.
The package thermal characteristics are optimised to
provide the best isolation with excellent thermal
coupling.

ISOWATT218

INTERNAL SCHEMATIC DIAGRAM

5

ABSOLUTE MAXIMUM RATINGS
Drain-source voltage (VGS = 0)
Drain-gate voltage (RGS = 1 MQ)
Drain current (continuous) Tc = 25 DC
Tc = 100 D C
Drain current (pulsed)
Gate-source voltage
Total dissipation at Tc .;;;25 DC
Total dissipation at Tc = 100DC
Junction to case - linear derating factor
Junction to ambient - linear derating factor
Storage temperature
Tstg
Max. operating junction temperature
Tj
Lead Temperature - 1/16" from case for 10s
Vos
V OGR
10

200
200
±19
±12
±120
±40
70
28
0.56
0.029
-55 to 150
150
300

V
V
A
A
A
V
W
W
W/DC
W/DC
DC
DC
DC

(.) Pulse width limited by safe Dperating area.
This is advanced information on a new product in development or undergoing evaluation. Details are subject to change without notice.

1107

11/86

L

ELECTRICAL CHARACTERISTICS (continued)
Parameter

Test conditions

SWITCHING
td (on)
tr
td(off)
~

Turn-on time
Rise time
Turn off delay time
Fall time

Voo= 750Vlo= 16A
Vgen = 10V Rg = 50
Ri = 4.50

25
60
85
38

35
100
125
100

ns
ns
ns
ns

19
12
120

A
A
A

1.6

2.0

V

150

400

ns

SOURCE DRAIN DIODE
Iso

Source-Drain current

150M (0)

Source-Drain current
(pulsed)

Vso *

Forward on voltage

V GS = 0

t"

Reverse recovery

Iso = 19A di/dt = 100A/p.s

Te = 100 0 e

* Pulsed: Pulse duration = 3001lS, duty cycle 2%
(.) Pulse width limited by safe operating area

1109

Iso = 28A

B.

ADVANCE DATA

HIGH SPEED SWITCHING APPLICATIONS
Voss
SOOV

RoS

(on)

0.4S0

10

SA

•
•
•
•

FULLY ISOLATED PACKAGE
HIGH VOLTAGE - FOR OFF-LINE SMPS
HIGH CURRENT - 8A FOR UP TO 1200W SMPS
ULTRA FAST SWITCHING - FOR OPERATION
AT~ 100KHz
• EASY DRIVE - REDUCES EQUIPMENT SIZE
AND COST
INOUSTRIAL APPLICATIONS:
• SWITCHING MODE POWER SUPPLIES
• MOTOR CONTROLS
N-Channel enhancement mode POWER MOS field
effect transistors. Easy drive, very fast switching times and simple mounting make these POWER MOS
transistors ideal for high speed switching applications
in a wide range of equipment.
The ISOWATT218 package requires only simple single hole mounting and provides isolation to 2500V
ac, 4000V dc. and meets with the creepage distance requirements of VDE, IEC, and UL specifications.
The package thermal characteristics are optimised
to provide the best isolation with excellent thermal
coupling.

ISOWATT218

INTERNAL SCHEMATIC DIAGRAM

5

ABSOLUTE MAXIMUM RATINGS
Vos
V OGR
10

Drain-source voltage (VGS = 0)
Drain-gate voltage (R GS = 1 MQ)
Drain current (continuous) Tc = 25°C
Tc = 100°C
Drain current (pulsed)
Gate-source voltage
Total dissipation at Tc ~ 25°C
Total dissipation at Tc = 100° C
Junction to case - linear derating factor
Junction to ambient - linear derating factor
Storage. temperature
T stg
Tj
Max. operating junction temperature
Lead Temperature - 1/16" from case for 10s

500
500
±8
±5
±52
±40
70
28
0.56
0.029
-55 to 150
150
300

V
V
A
A
A
V
W
W
W/oC
W/oC
°C
°C
°C

(0) Pulse width limited by safe operating area.

This is advanced information on a new product in development or undergoing evaluation. Details are subject to change without notice.

1111

11/86

ELECTRICAL CHARACTERISTICS
Parameter

(continued)

Test conditions

SWITCHING
Turn-on time
Rise time
Turn off delay time
Fall time

td lonl
tr
tdloffl
tf

V 00 = 21 OV 10 = 7 A
Vgen = 10V Rg = 5Q
Rj = 300

25
25
75
31

40
50
150
70

ns
ns
ns
ns

S
5
52

A
A
A

SOURCE DRAIN DIODE
Source-Drain current

Iso

Tc = 100°C
ISOM 1 1 Source-Drain current
(pulsed)
0

V so *

Forward on voltage

V GS = 0

Iso = 12A

1.2

1.5

V

trr

Reverse recovery

Iso = SA

di/dt = 100A/JLs

400

600

ns

* Pulsed: Pulse duration = 300J.1s, duty cycle 2%
(e) Pulse width limited by safe operating area

1113

am
System$
gu®

0

0

lDllWll$ll©[flJ

SWITCH MODE BIPOLAR STEPPER MOTOR DRIVER
MODULE
The GS-D200 is a complete controller and driver for bipolar stepper motors that directly
interfaces a microprocessor and two phase permanent magnet motors.
The motor current is controlled in a chopping mode up to 2 A. High flexibility in use
is provided by GS-D200 that, furthermore, reduces the burden on the microprocessor
and simplifies the software development in a complete microprocessor controlled
stepper motor system.

FEATURES
• No external component required

Ii Normal, wave, half step drive capability
•
•
•
•
•
•
•
•
•

Inputs TTUCMOS compatible
Chopper regulation of motor current
Programmable motor current (2 A max)
Wide voltage range (10-46 V)
Selectable slowlfast current decay
Synchronization for multiple application .....
Remote inhibiUenable
Home position indicator
Overtemperature protection

Order Number: GS-D200

ABSOWTE MAXIMUM RATINGS
Vs

Supply voltage (pin 18)

48 V

Vss

Supply voltage (pin 12)

7V

10

Peak output current

Tstg

Storage temperature range

-40 to + 1OsoC

Tcop

Operating case temperature range

-20 to +

Recommended maximum operating input voltage is 46

2A
8SoC

v.

THERMAL DATA
Rth (c-a) case-ambient thermal resistance
1115

Max

S.O °C/W
12/86

m

"
c:

r------

I :Vs

D1'--l_ _
1 O>--=G:.:N=SYNC

__ I

A

RESET

B

B

e

4 -

COMBINATIONAL
LOGIC

HALF/FULL

o

E
F

o

**

018

~

---017
16

-

o

".J

I"~

I

CW/CC' ..

T

11111

·re

~:D

•

R sense
Q

s::::

o"T1

I I II I .10

OSC

~

80---

Q
UJ
15

PHD

,)

10 0 CONTROL
11

o

6

"

HOME

---+

U

m

o
c

G
H

STEP,..!'

m

z

I PHA
PHB

~

r-

\.,

I,

---014

G

6

~

o
o

ENABLE
I,SET

~
R sense
12 0

Vss

J JJJJJI

I
L __

II

! I GND2013

__...J
S~9446

-T

PIN FUNCTIONS (Continued)
PIN

FUNCTION

14-0

Phase 0 output

15-C

Phase C output

16-8

Phase 8 output

17-A

Phase A output

18-V s

Module supply voltage~ Maximum voltage must not exceed 46 V.

ELECTRICAL CHARACTERISTICS (Tamb = 25°C unless otherwise specified)
Parameter

Test Conditions

Min

Vs

Supply Voltage

Pin 18

10

Vss

Supply Voltage

Pin 12

4.75

Is

Quiescent
Supply Current

Pin 18
lout =0

Iss

Quiescent
Supply Current

Pin 12. All inputs high
Vss=5V
lout =0

Vi

Input Voltage

Pin 3, 4, 6, 7, 10

Max

Unit

46

V

5

5.25

15

20

rnA

Vs=42V

low
high

rnA

60
0.8
Vss

V
V

0.6
10

rnA
pA

0.8
Vss

V
V

Ven=low
Ven =high

0.6
10

rnA
pA

low
high

0.4
Vss

V
V

Ii

Input Current

Pin 3, 4, 6, 7, 10

Ven

Enable Input
Voltage

Pin 11

Enable Input
Current

Pin 11

len

Typ

2.0

V1=low
Vi=high
low
high

2.0

V home Home Output
Voltage

Pin 5
Ihome =5mA

V sat

Source Saturat.
Voltage

Pin 14, 15, 16, 17

lo=1A

1.8

V

V sat

Sink Saturat.
Voltage

Pin 14,15,16,17

lo=1A

1.8

V

fc

Chopper Freq.

17
1119

KHz

MODULE OPERATION
The GS-D200 is a complete bipolar stepper motor driver that incorporates all the
small signal and power functions to directly interface a microprocessor and a two
phase permanent magnet motor (see the typical application). Very few information
must be delivered by the microprocessor to the module:
-

step clock
direction (clockwise or counterclockwise)
mode (half or full step)
reset and enable
current decay (slow or fast)

Based on this information, the module generates the proper four phases sequence
to directly drive a two phase bipolar motor. Therefore the GS-D200 greatly simplifies the task of the microprocessor and of the system programmer.
No external component is needed to operate the GS-D200. However, to add flexibility in use, some internally set functions can be modified externally, like the maximum current flowing through the motor windings and the switching frequency of
the current chopper, by addition of few inexpensive passive components (resistor
and capacitor).
If any of logic input is left open, the module forces them to high level.
The GS-D200 is housed in a metal case that provides heatsink and shielding against
radiated EMI. The thermal resistance case to ambient is about 5 °CIW. This means
that for each watt of internal power dissipation the case temperature is + 5°C above ambient temperature. It is reccomended to keep the case temperature below
85°C in operating conditions.
According to ambient temperature and/or to power dissipation, an additional heatsink may be required: the mounting of optional heatsink is made easy by the four
holes provided on the top of the metal case.
•
The GS-D200 incorporates a thermal protection that switches off the power stages
when the junction temperature of active components reaches 150°C.
To keep the power dissipation to a minimum, two level supply voltages must be
applied to the module: 5 V for logic functions and Vs from 10 to 46 V for power
section.

1121

A2 - TWO-PHASE-ON or NORMAL DRIVE
This mode gives the highest torque since two windings are energized at any given
time according to the sequence (for clockwise rotation)
AB & CD; CD & BA; BA & DC; DC & AB
Fig. 3 shows the sequence and the corresponding position of the rotor.

B-

B.

B.

Fig. 3 - Two-phase-on (normal mode) drive

B5_5953

A3 - HALF STEP DRIVE
This sequence halves the effective step angle of the motor but gives a less regular
torque being one winding or two windings alternatively energized. Eight steps are
required for a complete revolution of the rotor.
The sequence is:
AB; AB & CD; CD; CD & BA; BA; BA & DC; DC; DC & AB
as shown in fig. 4.
A-

~.

~c
B-

B-

B·

A+

~.It:\­

~c
B-

Fig. 4 - Half step sequence.

5-5938

By the configurations of fig. 2,3,4 the motor would have a step angle of 90° (or 45°
in half step). Real motors have multiple poles pairs to reduce the step angle to a
few degrees but the number of windings (two) and the drive sequence are unchanged.
1123

CLOCK

A

B

C

o
ABCO =0101
HOME POSITION

s.

1001

s-

s.

s-

5-9450

Fig. 6 - Two-phase-on (normal mode) drive
8

A

L

B

c
I

~__~__-+!__~r---

o
ABCD=OOO1

1000

0010

I
I

0100

I

DJihC~ D~f

O-~-o~yO~O
B~

eO

B.

Fig. 7 . One·phase-on (Wave mode) drive.

1125

5-9451

When the CONTROL input is forced low, the decay is fast as shown in fig. 9.

,,·,:·h n n n

Vs -Pin18

'> - -r----i- - -H- --H- - -r-:

.. t

lh'lt1iHJI

(Vd ,
Vson..

I

Vs+Vd

--

i

---

I

---

I
I

I
I
- -I
I

(Vs.t,~.. t
Vsons.)

I

I

I

I

'AB

I

I

:

I

I

I
I

I

I

I

I

I
I

I

I

- - drive current (Q,,02 ON)
- - - -

recirculation current
02 OFF, 0" D2 ON)

(a,.

Fig. 9 • Chopper control with fast decay

The CONTROL input is provided on GS-0200 to allow maximum flexibility in application.
If the GS-0200 must drive a large motor that does not store much energy in the
windings, the chopper frequency must be decreased: this is easily obtained by connecting an external capacitor between OSC pin and GN01.
In these conditions a fast decay (CONTROL LOW) would impose a low average current and the torque could be inadequate. By selecting CONTROL HIGH, the average current is increased thanks to the slow decay.

E - MODULE PROGRAMMING
When no external component is used, the GS-0200 is set at the following conditions:
loutpeak == 1 A
fc chopper frequency == 17 KHz
By addition of inexpensive passive components the working conditions can be modified as follows.
1127

Minimum Value of R2 is 10 kO.
This current programmability can be used in half step sequence to increase the
current when only one phase is on: a more regular torque is so obtained.
E2 • CHOPPER FREQUENCY PROGRAMMING
The chopper frequency is internally set at about 17 KHz. This frequency can be
changed by addition of external components as follows.
To increase the chopper frequency a resistor R3 must be connected between
pin and V•• as shown in fig. 12.

ase

Vss

12

GS-D200

osc

8

'------~S-~945":":".

Fig. 12 - Chopper frequency increase

The new chopper frequency is given by:
fc= 17 (1

+~)
R3

KHz

where R3 is in KO

For example, if Vss=5 V and R3=,18 KO, fc == 34 KHz
To decrease the chopper frequency a capacitor
pin and GND1 as shown in fig. 13.

c

e must be connected between ase

GS-D200
5-1451

Fig. 13 - Chopper frequency decrease.

The new chopper frequency is given by:
fc = _.::.80;:.:.c:,5_ KHz

4.7+e

For example, if V5S = 5 V and

e = 4. 7nF, fc
1129

where

e is in nF

== 8.5 KHz.

!-

10KO

Vss

'oSET

8

OSC
SYNC

TO LARGE MOTOR
(2A)

GS - D200
MASTER

I

10

8

OSC
SYNC

CONTROL

TO SMALL MOTOR

(lA)

GS - D200
SLAVE
10

CONTROL

5_9459

Fig. 15 - Multimotor synchronization. Large and small motors. Slow current decay.

G - THERMAL OPERATING CONDITIONS
In many cases the GS-0200 module does not require any additional cooling because the dimensions and the shape of the metal box are studied to offer the minimum
possible thermal resistance case-to-ambient for a given volume.
It should be remembered that the GS-0200 module is a power device and, depending on ambient temperature, an additional heath-sink or forced ventilation or both
may be required to keep the unit within safe temperature range. (Tcasemax<85°C
during operation).
The concept of maximum operating ambient temperature is totally meaningless when
dealing with power components because the maximum operating ambient temperature depends on how a power device is used.
What can be unambiguously defined is the case temperature of the GS-0200 module.
To calculate the maximum case temperature of the module in a particular applicative environment the designer must know the following data:
-

Input voltage
Motor phase current
Motor phase resistance
Maximum ambient temperature

From these data it is easy to determine whether an additional heath-sink is required or not, and the relevant size i.e. the thermal resistance.
The step by step calculation is shown for the following example:
V in = 40 V, Iphase = 1 A, Rph Phase resistance = 10

n,

Max. Tamb = 50 °C

G1. Calculate the power dissipated by the indexer logic and the level shifter (see
electrical characteristics):
Plogic =(5 V· 60 mA) + (40 V· 20 mA)=1.1 W
1131

G4.5 HALF STEP. The power sequence, one phase ON, two phase ON forces the
power dissipation to be 1.5 times higher than in WAVE MODE when the motor is
running. In stall condition the worst case for power dissipation is with two phase
ON i.e. a power dissipation as in NORMAL MODE.
The following table summarizes the power dissipations of the output power stage
of the GS-D200 when running for this example:
Wave

Normal

Half Step

Fast Decay

3.19 W

6.38W

6.38W

Slow Decay

3.30W

6.60W

6.60W

G5. Calculate the total power dissipation for the GS-D200:
Ptot = PlogiC + Ppw
In this example, for slow decay and normal mode
Ptot =1.1 +6.6=7.7 W
G6. The case temperature can now be calculated:
Tcase=Tamb+(ptot. Rth ) =55+(7.7.5)=93.5 °C
G7. If the calculated case temperature exceedes the maximum allowed case temperature, as in this example, an external heat-sink is required and the thermal resistance can be calculated according to:

and then

Rth tet = Tcmax - Tamb
Plet

85 - 55
7.7

Rth - Rth lel
Rth - Rth tot

5 • 3.9

Rthhs

=3.9°CIW

= 17.7°CIW

5 - 3.9

The following table gives the thermal resistance of some commercially available
heath-sinks that fit on the GS-D200 module.

Manufacturer

Part Number

Rth (OC/W)

Mounting

Thermalloy

6177

3

Horizontal

Thermalloy

6152

4

Vertical

Thermalloy

6111

10

Vertical

Fischer

SK18

Vertical

Assman

V5440

3
4

Assman

V5382

4

Horizontal

1133

Vertical

PACKAGES

1135

1-

PACKAGES
80-16

~\u u ~

Ut,m

lQJ§max

80-16 Jedec

uu u
8.89
lomax

80-16P

1137

UWgM""~I "-FIC~
_

6.2m..

OJ

PACKAGES
8 lead Plastic Minidip

~

PO01-F4

W

8 lead Ceramic Minidip

~Ti'
~~

B~
I

M

0J.6

lJLJ-

0.8
1§L

254
.

M

~

U
14 lead Plastic Dip

I

2D~'

[:::::1
1139

PACKAGES
. Dip (V6P2)
16 lead Plastic rdip (V6P2)
)
812++8 2lead
POW: Powerdip (V6P2
+ 2 lea

P001-V6P2

16- Iea d Ceramic Dip

20~'

I

t:::::]

~
L:t
PO!l7-D3

. Dip
18 lead Plastic
dip(0.4)

9 + 9 lead Power

8
w
1141

PACKAGES
20 lead Plastic Dip (0.4)
16 + 2 + 2 lead Powerdip

2443

I

0 ..

.

!

~::::::::J
20 lead Plastic Dip (X3P2)

24 lead Plastic Dip

-EJ
'.

15.2101&68

32,zm" -_..

n

,

1143

13

"

POU-A6

PACKAGES
DIOWATT2

A-

K
1095!O.15

TO-220 lies)

TO-220 (Discrete Power)
4.emox

C
E.

1145

PACKAGES
HEPTAWATT
Horizontal Version

15.a maa

Vertical Version

SIP-9
0.4

13

2~

0.5
1.27

3.3

20.32

2',8 max

1147

P03o.AP

PACKAGES
ISOWATT218

r

o

L

SO-USI

ISOWATT5

TO 3
262~'

10.9

1149

8.7'""
1.7 max

11.7

SGS OFFICES
INTERNATIONAL HEADQUARTERS
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Via C. Olivetti 2, - 20041 Agrate Brianza-Italy
Tel.: 039 - 65551
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Teletax: 039-6555700
AUSTRALIA
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Tel.: 02-4385388
Telex: AA177651 SGS AUS
Teletax: 02-4393962
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Tel.: 040 - 433566
Telex: 51186 SGSEI NL
Teletax: 040-448824
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Telex: 620653 SGSATE I

JAPAN
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Teletax: 03-3787683
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Seoul 121
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Tel.: 02-7167472/3
Telex: K 29998
Teletax: 02-7167409

PEOPLE'S REPUBLIC OF CHINA
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Rm 5011, Beijing Hotel,
Tel: 01-507766
Telex: 201285 SGSBJ
SINGAPORE
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Tel.: 4821411
Telex: RS 55201 ESGIES
Teletax: 4820240
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Representative Office
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Tel.: 01 - 7337043
Telex: 41414
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Telex: 28895
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Tel.: 02-7728203
Telex: 10310 ESGIE TWN
Teletax: 02-7413837
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Planar House, Walton Street
Tel.: 0296 - 395977
Telex: 051 - 83245
Teletax: 0296-28203

1151

U.S.A.
SGS Semiconductor Corporation
Phoenix, AZ 85022
1000 East Bell Road
Tel.: (602) 867-6100
Telex: 249976 SGSPH UR
Sales Offices:
Hauppauge, NY 11788
330 Motor Parkway
Suite 100
Tel.: (516) 435-1050
Telex: 221275 SGSHA UR
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Suite J
Tel. (714) 863-1222
Telex: 277793 SGSOR UR
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850 East Central Parkway
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Tel.: (214) 881-0848
Telex: 203997 SGSDA UR
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201 South Avenue
Suite 206
Tel.: (914) 473-2255
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Tel.: (408) 727-3404
Telex: 278833 SGSSA UR
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600 North Meacham Road
Tel.: (312) 490-1890
Telex: 210159 SGSCH UR
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21411 Civic Center Dr. 309
Mark Plaza Bldg.
Tel.: (313) 358-4250
Telex: 810-224-4664 "MGA DET SOFD"
Waltham, MA 02154
240 Bear Hill Road
Tel.: (617) 890-6688
Telex: 200297 SGSWH U R

WEST GERMANY
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Tel.: 08092-690
Telex: 05 27378
Teletax: 08092-3964
Sales Offices:
3012 Langenhagen
Hans Boeckler Str., 2
Tel.: 0511 - 789881
Telex: 923195
8500 Nurnberg 40
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eingang Wilhelminenstr.
Tel.: 0911 - 464071
Telex: 626243
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Seitnerstrasse, 42
Tel.: 089 - 793 0662
Telex: 5215784
7000 Stuttgart 31
Loewenmarkt, 5
Tel.: 0711 - 881101
Telex: 723625



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