1987_Siemens_Consumer_IC_Data_Book 1987 Siemens Consumer IC Data Book
User Manual: 1987_Siemens_Consumer_IC_Data_Book
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SIEMENS
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Consumer IC
Data Book 1987/88
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Contents
Summary of Types
Cross Reference Guide
General Information
Technical Data
Package Outlines
Siemens Sales Offices
2
Consumer
Ie
Data Book 1987/88
3
4
Contents
5
6
Table of Contents
Summary of Types
Page
1.1
1.2
Types in alphanumerical order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11
Types by application order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13
2
General Information
2.1
2.2
2.3
2.4
2.5
2.6
Type Designation Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Mounting Instructions ..............................................
Processing Guidelines for ICs ........................................
Data Classification................................................
Quality Assurance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Summary of terms and symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3
Technical Data.................................................... 37
4
Package Outlines .................................................. 927
5
Listing of Siemens Sales and Rep Offices .............................. 945
21
21
25
28
28
33
7
8
Summary of Types
9
10
Summary of Types
1.1
Types in Alphanumerical Order
HKZ 101
S041 P
S 042 P
S 178A
S 353
S576A
S576 B
S576C
S576D
S 1353
S2353
SAB 0600
SAB 0601
SAB 0602
SAE0700
SDA0808A;B
SDA 2008
SDA2040
SDA 2060
SDA2080
SDA2082
SDA 2110
SDA 2112·2
SDA 2120
SDA 2131
SDA2208·2
SDA 2211
SDA2506
SDA 2516
SDA2526
SDA 3112
SDA3202
SDA3203
SDA 4212
SDA5200 N
SDA 5200 S
SDA6020
SDA8005
SDA8010
SLE5001
SLE5002
TBA 120S
TBA 120T
TBA 120 U
TBB042 G
TBB200
Page
Hall·effect vane switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 37
FM IF amplifier and demodulator ......................... 43
Mixer ................................................ 49
Video pulse generator .................................. 55
Programmable diode matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 65
Electronic dimmer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 71
Electronic dimmer ..................................... 71
Electronic dimmer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 71
Electronic switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 71
Programmable diode matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 65
Programmable diode matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 65
Three tone chime. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 81
Single tone chime. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 81
Dual tone chime ....................................... 81
Audible signal device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 89
8 bit/15 itS ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 95
IR transmitter ......................................... 103
Microcontroller (4k ROM) ................................ 121
Microcontroller (6k ROM) ................................ 121
Microcontroller (8k ROM) ................................ 121
Microcontroller ........................................ 131
Microcontroller ........................................ 145
Video PLL ............................................ 153
120 MHz radio PLL ..................................... 165
Static LED driver ...................................... 179
IR transmitter ......................................... 185
Prescaler 1:64 ......................................... 195
128 x 8 EEPROM ...................................... 201
128 x 8 EEPROM IIC bus ................................ 207
256 x 8 EEPROM IIC bus ................................ 213
Video PLL ............................................ 221
1.3 GHz Video PLL IIC bus ............................... 231
1.3 GHz Video PLL ..................................... 243
Prescaler 1:64/256 ..................................... 255
6 bit AID converter ..................................... 263
6 bit AID converter ..................................... 269
6 bit AID converter ..................................... 275
8 bit D/A converter ..................................... 281
8 bit AID converter ..................................... 293
IR transmitter ......................................... 307
IR receiver ........................................... 307
FM IF amplifier & demodulator ........................... 319
FM IF amplifier & demodulator ........................... 327
FM IF amplifier & demodulator ........................... 327
Mixer ................................................ 337
PLL frequency synthesizer .............................. 343
11
Summary of Types
Page
TBB469
TBB 1469
TBB 2469 G
TCA 105 B;G
TCA205A
TCA 205 K
TCA 305 A;G
TCA355 B;G
TCA345 A
TCA365 A
TCA440
TCA 785
TCA 955
TCA 965
TCA 1365
TCA 1560
TCA 1561
TCA 2365
TCA 4500 A
TCA 4511
TDA 1037
TDA4001
TDA 4010
-,·TDA 4050 B
TDA 4060
TDA4210-3
TDA 4282 T
TDA4292
TDA 4600-3
TDA4601 ;D
TDA4605
TDA4814
TDA4918A
TDA4919G
TDA4930
TDA4935
TDA5400-2
TDA5660 P
TDA 5660 X
TDA5830-2
TDA5835
TDA5850
TDA 6000
TDA6200
.<-
12
FM receiver ............................................ 359
FM receiver ............................................ 365
FM receiver ............................................ 369
Threshold switch ....................................... 373
Proximity switch ........................................ 379
Proximity switch ........................................ 379
Proximity switch ........................................ 385
Proximity switch ........................................ 385
Threshold switch ....................................... 393
Power op amp .......................................... 397
AM receiver ............................................ 407
Phase controller ........................................ 425
Speed controller ........................................ 441
Window discriminator ................................... 447
Power op amp .......................................... 459
Stepper motor driver ..................................... 469
Stepper motor driver ..................................... 469
Dual power op amp ...................................... 485
FM stereo decoder ...................................... 495
FM PLL stereo decoder .................................. 499
Audio power amp ....................................... 507
AM receiver ............................................ 517
AM receiver ....................................... : .... 525
IR preamplifier ......................................... 533
IR preamplifier ......................................... 539
FM I F for car radios ..................................... 541
Quasi parallel IF ........................................ 547
DC stereo tone control ................................... 553
SMPS controller ........................................ 573
SMPS controller ........................................ 589
SMPS controller ........................................ 615
Sinewave controller ..................................... 635
Push-pull SMPS controller. ............................... 647
Single-ended SMPS ..................................... 659
Audio power amp 2 x 10W ................................ 671
Audio power amp 2 x 15W ................................ 685
Video IF w/AFC ......................................... 699
VHF/UHF modulator ..................................... 705
TDA 5660P in SO-20 package .............................. 749
Video IF & Q-P sound .................................... 759
Video IF & Q-P w/AFC .................................... 775
Video switch ........................................... 791
Video IF w/synch demodulator ............................ 795
Sound control, IIC bus ................................... 799
Summary of Types
Page
TOE 4060
TOE 4061
TFA 1001 W
TLB 4902 F
TLE 3101
TLE 3102
TLE 3103
TLE 3104
TLE 4201 A
TLE 4201 S
TLE 4901 F;K
TLE 4903 F
TUA 1574
TUA2000-4
TUA 2005
UAA 170
UAA 180
IR Preamp ............................................. 307
IR Preamp w/demodulator ................................ 307
Photodiode w/amplifier .................................. 815
Hall-effect switch ....................................... 827
Phase controller ........................................ 833
Phase controller ........................................ 845
Phase controller. ....................................... 847
Phase controller ........................................ 848
DC motor driver ......................................... 853
DC motor driver ......................................... 853
Hall-effect switch ....................................... 863
Hall-effect switch ....................................... 869
FM tuner IC ............................................ 875
VHF tuner IC 400 MHz ................................... 881
VHF tuner IC 700 MHz ................................... 899
LED driver for dot display ................................. 911
LED driver for bar display ................................. 919
1.2 Applications Order
1.2.1 les for Industrial Applications
Power Operational Amplifiers
TCA 365 A
TCA 1365
TCA2365 ;A
Power op amp .......................................... 397
Power op amp .......................................... 459
Dual power op amp ...................................... 485
Threshold Switches
TCA 105 B;G
TCA 345 A
TCA 965
Threshold switch ....................................... 373
Threshold switch ....................................... 393
Window discriminator ................................... 447
Switched Mode Power Supply
TDA4600-3
TDA4061; 0
TDA4605
TDA4814
TDA4918A
TDA4919 G
SMPS controller ........................................ 573
SMPS controller ........................................ 589
SMPS controller ........................................ 615
Sinewave controller ..................................... 635
Push-pull SMPS control .................................. 647
Single-ended SMPS ..................................... 659
13
Summary of Types
Page
Control of Thyristors and Triacs
TCA 785
TLE3101
TLE 3102
TLE3103
TLE3104
S 576 A;B;C
S576 D
Phase controller. ....................................... 425
Phase controller ........................................ 833
Phase controller ........................................ 845
Phase controller ........................................ 847
Phase controller ........................................ 848
Electronic dimmer ...................................... 71
Electronic switch....................................... 71
Data Converters
SDA 0808 A;B
SDA 5200 N
SDA 5200 S
SDA 6020
SDA 8005
SDA 8010
8
6
6
6
8
8
bit/15 /lS ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 95
bit AID converter ...................................... 263
bit AID converter ...................................... 269
bit AID converter ...................................... 275
bit D/A converter ...................................... 281
bit AID converter ...................................... 293
Audible Signal Devices
SAB 0600
SAB 0601
SAB 0602
SAE0700
Three tone chime. . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Single tone chime .......................................
Dual tone chime ........................................
Audible signal device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
81
81
81
89
IC's for Radio Communications
TBB042 G
TBB200 ;G
TBB469
TBB 1469
TBB 2469G
S353
S 1353
S2353
Mixer ................................................. 337
PLL frequency synthesizer ................................ 343
FM receiver ............................................ 359
FM receiver ............................................ 365
FM receiver ............................................ 369
Programmable diode matrix ............................... 65
Programmable diode matrix. . . . . . . . . . . . . ... . . . . . . . . . . . . . . .. 65
Programmable diode matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 65
DC Motor Control
TCA 955;K
TLE 4201 A;S
TCA 1560
TCA 1561
14
Speed controller. ....................................... 441
DC motor driver ......................................... 853
Stepper motor driver ..................................... 469
Stepper motor driver ..................................... 469
Summary of Types
Page
Sensors, Hall·Effect, Proximity Switches
TFA 1001 W
TLB4902 F
TLE 4901 F
TLE 4903 F
HKZ 101
TCA 205A;K
TCA 305A;B
Photodiode w/amplifier .................................. 815
Hall-effect switch ....................................... 827
Hall-effect switch ....................................... 863
Hall-effect switch ....................................... 869
Hall-effect vane switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 37
Proximity switch ........................................ 379
Proximity switch ........................................ 385
Miscellaneous Industrial
SLE 5001
SLE 5002
S 178A
TDE 4060/61
IR Key transmitter ....................................... 307
IR Key receiver ......................................... 307
Video pulse generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 55
IR Preamplifier ......................................... 307
1.2_2 IC's for Entertainment Applications
TV Tuners
TUA 2000-4
TUA 2005
VHF tuner IC 400 MHz ................................... 881
VHF tuner IC 700 MHz ................................... 899
IR Remote Control
SDA2008
SDA 2208-2
TDA4050 B
TDA4060
IR
IR
IR
IR
transmitter .......................................... 103
transmitter .......................................... 185
preamplifier ......................................... 533
preamplifier ......................................... 539
Prescalers
SDA 2211
SDA 4212
Prescaler 1:64 .......................................... 195
Prescaler 1:64/256 . ...................................... 255
Video PPL:s
SDA 2112-2
SDA3112
SDA3202
SDA3203
Video PLL ............................................. 153
Video PLL ............................................. 221
1.3 GHz video PLL IIC bus ................................ 231
1.3 GHz video PLL. ...................................... 243
15
Summary of Types
Page
Single Chip Microcomputer
SDA2040
SDA 2060
SDA2080
SDA2082
SDA 2110
Microcontroller (4k ROM) ................................. 121
Microcontroller (6k ROM) ................................. 121
Microcontroller (8k ROM) ................................. 121
Microcontroller ......................................... 131
Microcontroller ......................................... 145
Nonvolatile Memories
SDA 2506
SDA 2516
SDA 2526
128 x 8 EEPROM ........................................ 201
128 x 8 EEPROM IIC bus .................................. 207
256 x 8 EEPROM IIC bus ................................. 213
Display Drivers
SDA 2131
UAA 170
UAA 180
Static LED driver ........................................ 179
LED driver for dot display ................................. 911
LED driver for bar display ................................. 919
Video Sound IF
TDA 4282 T
TDA 5400·2
TDA 5830-2
TDA 5835
TDA 5850
TDA 6000
Quasi parallel IF ........................................ 553
Video IF w/AFC ......................................... 699
Video IF & Q.p sound .................................... 759
Video IF & Q-P w/AFC .................................... 775
Video switch ............................................ 791
Video IF w/synch demodulator ............................ 795
Miscellaneous Entertainment
TDA 5660 P
TDA 5660 X
VHF/UHF modulator ..................................... 705
VHF/UHF modulator ..................................... 749
SMPS Control
TDA 4600-3
TDA 4601;0
TDA 4605
SMPS controller ........................................ 573
SMPS controller. ....................................... 589
SMPS controller ........................................ 615
Radio Tuners
S042 P
TUA 1574
SDA 2120
16
Mixer ........................... , ..................... 49
FM tuner IC ............................................ 875
120 MHz radio PLL ...................................... 165
Summary of Types
Page
Radio IF
S 041 P
TCA440
TDA 4001
TDA 4010
TDA 4210-3
FM
AM
AM
AM
FM
IF amplifier & demodulator ............................ 43
receiver ............................................ 407
receiver ............................................ 517
receiver ............................................ 525
I F for car radios ..................................... 541
FM Stereo Decoders
TCA 4500 A
TCA 4511
FM Stereo decoder ...................................... 495
FM PLL stereo decoder .................................. 499
Audio Power Amplifiers
TDA 1037
TDA4930
TDA4935
Audio power amplifier ................................... 507
Audio power amplifier 2 x 10W ............................. 671
Audio power amplifier 2 x 15W ............................. 685
ToneNolume Control
TDA4292
TDA6200
DC Stereo tone control ................................... 553
Sound control, IIC bus ................................... 799
17
18
General Information
19
20
General Information
2.1
Type-designation code for les
IC type designations are based on the European Pro Electron system. The code
system is explained in the Pro Electron brochure D 15*), edition 1985.
*) Available from Pro Electron, Avenue Louise, 430 (B.12)
B-1060 Brussels, Belgium
2.2
2.2.1
Mounting instructions
Plastic package
The pins of the cases are bent downwards by an angle of 90° and fit into holes
with a diameter of between 0.7 and 0.9 mm spaced 2.54 mm apart. The dimension x is
given in the corresponding drawing.
The bottom of the package will not touch the PC board after insertion because
the pins have shoulders just below the package (see figure 1).
After insertion of the package into the PC board it is advisable to bend the ends
of two pins at an angle of approx. 30° to the board so that the package does not
have to be pressed down during soldering. Plastic packages are soldered on that
side of the PCB facing away from the package.
The maximum permissible soldering temperature is 300°C (max. 5 s) for manual
soldering and 260°C (max. 10 s) for dip soldering and wave soldering.
fuijij
q, 0.8
-¢'-~¢.
--I2S4~
Ti n Solder
-tIr
-<1>
Dimensions in mm
Figure 1
2.2.2
Power package with 5, 7, or 9 pins
Power packages generally have wider pins than stated in paragraph 2.2.1, meaning
that the hole diameter on the PCB must be between 1.1 and 1.8 mm. If the pins
are bent, there should be no stress between the pins and the package. The
minimum distance between the package and the bending point is 2 mm.
Refer to paragraph 2.2.1 for soldering temperatures.
21
General Information
2.2.3
Plastic packages (SO and PLCC) for surface mounting (5MD)
Iron soldering:
soldering temperature 300°C for max. 5 s;
minimum distance between package and soldering point
1.5mm
package temperature max. 150°C; no mechanical stress
on the pins
Vapor phase soldering: soldering temperature 215°C, max. soldering time 30 s
Wave soldering:
(pins and package
are dipped into
the tin bath)
2.2.4
soldering temperature 260°C, max. soldering time 3 s.
5 H 8 DIN 41873 and similar packages
The package may be mounted in any position. The ends of the pins may be kinked
up to a distance of 1.5 mm from the bottom of the package to suit the hole spacing
(fig. 2).
Pins that are too long should be clipped before soldering.
Iron or dip soldering may be employed.
Maximum soldering duration for dip soldering at 250°C bath temperature
at 300°C bath temperature
for iron soldering at 250°C iron temperature
at 300°C iron temperature
at 350°C iron temperature
Bending radius
0.5mm
Tin solder
iii' 4> w--~ 0.5 to 0.6
-$-
+
iI'l:+Ja
Figure 2
22
Dimensions in mm
tmax =
5s
t max = 4 s
t max = 15 s
tmax = 12 s
tmax = 8 s
General Information
2.2.5
Other points to note
Ensure that no current is able to flow between the solder bath or soldering iron
and the PCB. It is advisable to ground the pins that are to be soldered as well as
the solder bath or soldering iron.
When they are being prepared and inserted in a PCB, circuits should be protected
against static charging. Under no circumstances may the components be removed
or inserted whilst the operating voltage is switched on.
The increase in chip temperature during the soldering process results in a temporary
increase in electrostatic sensitivity of integrated circuits. Special precautions should
therefore be taken against line transients, e.g. through the switching of inductances
on magnetic chutes, etc.
2.2.6
MIKROPACK (SMO)
MIKROPACK components are delivered on film reels.
Mounting suggestions
a) We recommend vapor phase soldering: soldering temperature 215°C, soldering time
max. 30 s
b) For prototypes and small quantities (up to approximately 50.0 items/y), the hot table
soldering method can also be used (fig. 3).
MIKROPACK
~
~
Metallization (conductor)
Substrate
Cover
/
Hot table
Figure 3
Required equipment and accessories
• cutting device
• hot table, temperature regulated (e.g. Weld-Equip, Unitek)
• stereo microscope (e.g. Wild, Zeiss, magnification 6 ... 40 times)
• substrate material: epoxy resin; hard paper; ceramic (thick thin film)
Soldering data
•
•
•
•
•
soldering temperature: 210°C max.
solder coating on substrate: PblSn (e.g. 60/40) wave-tinned or electrodeposited
soldering time: approx. 10 s
flux: e.g. colo phony, dissolved in alcohol
cleaning agents (as required): e.g. Freon TP-35, TE, TF
23
General Information
c) For large quantities (e.g. more than 50.0 items/y) bar soldering is also suitable.
Suction hole
Clamp
Solderi ng bar
~:-=~~~~~~.fi~~~~1
MIKROPACK
Tinned conductor
Substrate
~
Figure 4
Required equipment
•
•
soldering equipment (e.g. Weld-Equip, Farco, Jade)
substrate material: epoxy resin; hard paper; flexible materials, e.g. polyamide
Soldering data
•
•
•
•
•
24
soldering temperature: 210 DC max.
solder coating on the substrate: Pb/Sn (e.g. 60/40), wave-tinned or electrodeposited
soldering time: approx. 2 s
flux: e.g. colophony dissolved in alcohol
cleaning agents (as required): e.g. Freon TP-35, TE, TF
"
.......
General Information
2.3
Processing guidelines for les
Integrated circuits (ICs) are electrostatic-sensitive (ESS) devices. the requirement
for greater packing density has led to increasingly small structures on semiconductor chips, with the result that today every IC, whether bipolar, MOS, or
CMOS, has to be protected against electrostatics.
MOS and CMOS devices generally have integrated protective circuits and it is
hardly possible any more for them to be destroyed by purely static electricity.
On the other hand, there is acute danger from electrostatic discharges (ESD).
Of the multitude of possible sources of discharge, charged devices should be
mentioned in addition to charged persons. With low-resistive discharges it is possible
for peak power amounting to kilowatts to be produced.
For the protection of devices the following principles should be observed:
a) Reduction of charging voltage, below 200 V if possible.
Means which are effective here are an increase in relative humidity to ~ 60%
and the replacement of highly charging plastics by antistatic materials.
b) With every kind of contact with the device pins a charge equalization is to be
expected. This should always be highly resistive (ideally R = 10 6 to 10 8 Q).
All in all this means that ICs call for special handling, because uncontrolled charges,
voltages from ungrounded equipment or persons, surge voltage spikes and similar
influences can destroy a device. Even if devices have protective circuits (e.g. protective diodes) on their inputs, the following guidelines for their handling should
nevertheless be observed.
2.3.1
Identification
The packing of ESS devices is provided with the following label by the manufacturer: ~
2.3.2
Scope
The guidelines apply to the storage, transport, testing, and processing of all kinds
of ICs, equipped and soldered circuit boards that comprise such components.
2.3.3
Handling of devices
1. ICs must be left in their containers until they are processed.
2. ICs may only be handled at specially equipped work stations. These stations
must have work surfaces covered with a conductive material of the order of
10 6 to 10 9 Q/cm.
3. With humidity of > 50% a coat of pure cotton is sufficient. In the case of
chargeable synthetic fibers the clothing should be worn close-fitting. The wrist
strap must be worn snugly on the skin and be grounded across a resistor
of 50 to 100 kQ.
25
General Information
4. If conductive floors, R = 5 x 10 4 to 10 7 Q are provided, further protection can
be achieved by using so-called MOS chairs and shoes with a conductive sole
(R"" 105 to 107 Q).
5. All transport containers for ESS devices and assembled circuit boards must
first be brought to the same potential by being placed on the work surface or
touched by the operator before the individual devices may be handled. The
potential equalization should be across a resistor of 10 6 to 108 Q.
6. When loading machines and production devices it should be noted that the
devices come out of the transport magazine charged and can be damaged if
they touch metal, e.g. machine parts.
Example 1) conductive (black) tubes.
The devices may be destroyed in the tube by charged persons
or come out of the tube charged if this is emptied by a charged
person.
Conductive tubes may only be handled at ESS work stations
(high-resistance work-station and person grounding).
Example 2) anti-static (transparent) tubes.
The devices cannot be destroyed by charged persons in the tube
(there may be a rare exception in the case of custom ICs with
unprotected gate pins). The devices can be endangered as in 1)
when the tube is emptied if the latter, especially at low humidity, is
no longer sufficiently anti-static after a long period of storage
(> 1 year).
In both cases damage can be avoided by discharging the devices, across a
grounded adapter of high-resistance material ("" 10 6 to 10 8 Q/cm) between the
tube and the machine.
The use of metal tubes - especially of anodized aluminum - is not advisable
because of the danger of low-resistance device discharge.
2.3.4
Storage
ESS devices should only be stored in identified locations provided for the purpose.
During storage the devices should remain in the packing in which they are supplied.
The storage temperature should not exceed 60 ac,
2.3.5
Transport
ESS devices in approved packing tubes should only be transported in suitable
containers of conductive or longterm anti-static-treated plastic or possibly unvarnished wood. Containers of high-charging plastic or very low-resistance materials
are in like manner unsuitable.
Transfer cars and their rollers should exhibit adequate electrical conductivity
(R < 106 Q). Sliding contacts and grounding chains will not reliably eliminate
charges.
26
General Information
2.3.6
Incoming inspection
In incoming inspection the above guidelines should be observed. Otherwise any
right to refund or replacement if devices fail inspection may be lost.
2.3.7
Material and mounting
1. The drive belts of machines used for the processing of the devices, in as much
as they come into contact with them (e.g. bending and cutting machines,
conveyor belts), should be treated with anti-static spray (e.g. anti-static spray
100 from Kontaktchemie). It is better, however, to avoid the contact completely.
2. If ESS devices have to be soldered or desoldered manually, soldering irons
with thyristor control may not be used. Siemens EMI-suppression capacitors
of the type B 81711-B31 ... -B36 have pr~JVen very effective against line transients.
3. Circuit boards fitted and soldered with ESS devices are always to be considered as endangered.
2.3.8
Electrical tests
1. The devices should be processed with observation of these guidelines. Before
assembled and soldered circuit boards are tested, remove any shorting rings.
2. Test sockets must not be conducting any voltage when individual devices or
assembled circuit boards are inserted or withdrawn, unless works' specifications state otherwise. Ensure that the test devices do not produce any
voltage spikes, either when being turned on and off in normal operation or if
the power fuse blows or other fuses respond.
3. Signal voltages may only be applied to the inputs of ICs when or after the
supply voltage is turned on. They must be disconnected before or when the
supply voltage is turned off.
4. Observe any notes and instructions in the respective data books.
2.3.9
Packing of assembled PC boards or flatpack units
The packing material should exhibit low volume conductivity:
105 Q/cm < p < 1010 Q/cm.
In most cases - especially with humidity of > 40% - this requirement is fulfilled
by simple corrugated board. Better protection is obtained with bags of conductive
polyethylene foam (e.g. RCAS 1200 from Richmond of Redlands, California).
One should always ensure that boards cannot touch.
In special cases it may be necessary to provide protection against strong electric
fields, such as can be generated by conveyor belts for example. For this purpose
a sheath of aluminum foil is recommended, although direct contact between the
film and the PCB must be avoided. Cardboard boxes with an aluminum-foil lining,
such as those used for shipping our devices, are available from Laber of Munich.
27
General Information
2.3.10
Ultrasonic cleaning of ICs
The following recommendation applies to plastic packages. For cavity packages
(metal and also ceramic) separate regulations have to be observed.
Freon and isopropyl alcohol (trade name: propanol) can be used as solvents.
These solvents can also be used for plastic packages because they do not eat
into the plastic material.
An ultrasonic bath in double halfwave operation is advisable because of the low
component stress.
The ultrasonic limits are as follows:
sound frequency
f > 40 kHz
exposure
t < 2 min
alternating sound pressure p < 0.29 bar
N <0.5 W/cm2/liter
sound power
2.4
Data classification
Maximum ratings
Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
Characteristics
The listed characteristics are ensured over the operating range of the integrated
circuit. Typical characteristics specify mean values expected over the production
spread. If !lot otherwise specified, typical characteristics will apply at TA = 25°C
and for the given supply voltage.
Operating range
In the operating range the functions given in the circuit description will be fulfilled.
2.5
2.5.1
Quality Assurance
Quality Assurance System
The high quality and reliability of integrated circuits from Siemens is the result
of a carefully arranged production which is systematically checked and controlled
at each production stage.
The procedures are subject to a quality assurance system; full details are given
in the brochure 'Siemens Quality Assurance System -Integrated Circuits' (SQS-IC).
28
;::
....
General Information
Figure 1 shows the most important stages of the "sos-Ie". A quality assurance (OA) department which is independent of production and development, is responsible for the selected
control measures, acceptance procedures, and information feedback loops. This department
has state-of-the-art test and measuring equipment at its disposal, works according to
approved methods of statistical quality control, and is provided with facilities for accelerated
life and environmental tests used for both qualification and routine monitoring tests.
The latest methods and equipment for preparation and analysis are employed to achieve
continuity of quality and reliability.
Qualification Stages
Quality Control stages
Incoming Inspection
Parts
Auxiliaries
Materials
In - process Control
Physical Parameters
Dimensions
Visual Inspection
1st lot Acceptance Test
In-process Control
Bonding
Dimensions
2nd lot Acceptance Test
3rd lot Acceptance Test
Product
Development
Testing
Departments
Conformance Inspectiont-_ _- .
(Attributes I
Figure 1
29
General Information
2.5.2 Conformance
Each integrated circuit is subjected to a final test at the end of the production process.
These tests are carried out by computer-controlled, automatic test systems because hundreds
of thousands of operating conditions as well as a large number of static and dynamic
parameters have to be considered. Moreover, the test systems are extremely reliable and
reproducible. The quality assurance department carries out a final check in the form of a
lot-by-Iot sampling inspection to additionally ensure this minimum percent defectives as well
as the acceptable quality level (AQL). Sampling inspection is performed in accordance
with the inspection plans of DIN 40080, as well as of the identical MIL-STD-105 or lEe 410.
The table shows the results of such sampling inspections performed with hundreds of
thousands of les during 1985. These results correspond to the average outgoing quality
(AOQ), and are specified as defectives per million (DPM).
Inoperatives
AOQ
(DPM)
Sum of
electrical
defectives
AOQ
(DPM)
Sum of
mechanical
defectives
AOQ
(DPM)
SSI/MSI
::;; 1000 gate fu nctions
40
200
100
LSIIVLSI
L 1000 gate fu nctions
120
400
200
2.5.3 Reliability
2.5.3.1 Measures Taken during Development
The reliability of les is already considerably influenced at the development stage. Siemens
has, therefore, fixed certain design standards for the development of circuit and layout,
specifying e.g. minimum width and spacing of conductive layers on a chip, dimensions
and electrical parameters of protective circuits for electrostatic charge, etc. An examination
with the aid of carefully arranged programs operated on large-scale computers, guarantees
the immediate identification and elimination of unintentional violations of these design
standards.
2.5.3.2 In-Process Control during Production
The manufacturing of integrated circuits comprises several hundred production steps.
As each step is to be executed with utmost accuracy, the in-process control is of outstanding importance. Some processes require more than a hundred different test measures.
The tests have been arranged such that the individual process steps can be reproduced
continuously.
30
General Information
The decreasing failure rates reflect the never ending effort in this direction; in the course
of the years they have been reduced considerably despite an immense rise in the IC's
complexity.
So in 1985 the typical random failure rates estimated for accelerated life tests with almost
2 million ICs of all complexities are found to be around 80 fit.
2.5.3.3 Reliability Monitoring
The general course of the IC's failure rate versus time is shown by a so-called "bathtub"
curve (figure 2). The failure rate has its peak during the first few operating hours (early
failure period). After the early failure period has decayed, the "constant" failure rate
period starts during which the failures may occur at an approximately uniform rate. This
period ends with a repeated rise of the curve during the wear-out failure period. For ICs,
however, the latter period usually lies far beyond the service life specified for the individual
equipment.
Failure Rate
A.
Early
Failure
Period
Constant Failure Rate Period
//
Wear -Out
Failure
Period
Operating Hours -
Figure 2
Reliability tests for ICs are usually destructive examinations. They are, therefore, carried
out with samples. Most failure mechanisms can be accelerated by means of higher
temperatures. Due to the temperature dependence of the failure mechanisms, it is possible
to simulate future operational behavior within a short time by applying high temperatures;
this is called life test.
31
General Information
The acceleration factor B for the life test can be obtained from the Arrhenius equation
(~
~
exp ( EA
_ -L
k
7;
T2 ')
where T2 is the temperature at which the life test is performed, 7; is the assumed operating
temperature, and k is the Boltzmann constant.
B
=
Important for factor B is the activation energy EA- It lies between 0.3 and 1.3 eV and differs
considerably for individual failure mechanisms.
For all Siemens ICs, the reliability data from life tests is converted to an operating temperature of TA = 40°C, assuming an average activation energy of 0.4 eV. The acceleration
factor for life tests at 125°C is thus 24, compared with operational behavior. This method
considers also failure mechanisms with 'Iow activation energy, i.e. which are only slightly
accelerated by the temperature effect.
Various reliability tests are periodically perfo~med with IC types that are representative of a
certain production line - this is described in the brochure "SOS-IC". Such tests are e.g. humidity test at 85°C and 85% relative humidity, pressure cooker test, as well as life tests up to
1000 hours and more, Test results are available in the form of summary reports.
32
General Infonnation
2.6 Summary of terms and symbols in alphabetical order
A,B
AC
AF
AM
B
C
C;, C1
CCLK , C",
ClK
DC
D
f
M
FM
f;, fl
fq, fo
G
G
GND
Hy
Hz
i, I
/, i
Is
IF
k
K
L
m
M
m
MW
N,n
0
OSC
P,Pv
Ptot
pp
q,Q
Q,QB
R
Rth JC
Rth
sc
Rth SA
RF
Indices for limit value
Alternating current
Audio frequency
Amplitude modulation
Bandwidth
Capacitance
Input capacitance
Clock capacitor
Clock
Di rect cu rrent
Differential
Frequency
Frequency deviation
Frequency modulation
Input frequency
Output frequency
Gain
giga (10 9 )
Ground
Hysteresis
Cycles per second (Hertz)
Input
Current
Current consumption
Intermediate frequency
kilo (10 3 )
Kelvin
Inductance
Milli (10- 3 )
Mega (10 6)
Modulation factor
Medium wave
Noise
Offset
Oscillator
Power dissipation
Max. perm. power dissipation
Peak-to-peak
Output
Q-factor
Resistance
Thermal resistance Uunction-case)
Thermal resistance (system-case)
Thermal resistance (system-air)
Radio frequency
33
General Information
S+N
----,;J
T
T
TC
TA
Tstg
7j
tH
tl
tn
tn+l
tp
tpd
tp Hl
tp LH
tpi
tp 0
tp R
tp s
tp ClK
tp z
ts
tT
tt
to
tTHL
tTLH
THD
V
V. v
VHY
Vi. VI
Vq • Vo
VR
Vs
W
Z
Z
34
Signal-to-noise ratio
Cycle time
Temperature
Temperature coefficient
Time
Ambient temperature in operation
Storage temperature
Junction temperature
Hold time
Input pulse dUration
Instant prior to clock pulse
Instant after clock pulse
Average pulse transit time
Pulse delay time
HL pulse transit time
LH pulse transit time
Input pulse duration
Output pulse duration
Reset pulse duration
Set pulse duration
Clock pulse duration
Count pulse duration
Set-up time
Signal transition time
Dead time
Output pulse duration
HL transition time
LH transition time
Total harmonic distortion
Volt
Voltage, general
Hysteresis voltage
Input voltage
Output voltage
Reverse voltage
Supply voltage
Watt
Impedance
Zener
Technical Data
35
36
Hall-Effect Vane Switch
HKZ101
The Hall-effect vane switch HKZ 101 is a contactless switch consisting of a monolithic integrated Hall-effect circuit and a special magnetic circuit hermetically sealed in a plastic package.
The switch is actuated by a shoft-iron vane which is passed through the air gap between
magnet and Hall sensor.
The main application field is in cars, i.e. as a breakerless trigger in electronic ignition systems.
Numerous industrial applications can be found in control engineering, especially in those
areas where switches must operate maintenance-free under harsh environmetal conditions
(e.g. rpm sensor, limit switch, position sensor, speed measurement, shaft encoder, scanning
of coding disks, etc.).
Features
CD Contactless switch with open collector output (40 mAl
GIl Static switching
(lJ) High switching frequency
• Hermetically sealed with plastic
~ Unaffected by dirt, light, vibration
• Large temperature and voltage range
• Integrated overvoltage protection
@ High interference immunity
Special package
green black
(a)
11»
(OV)
Change to 130:3mm in preparation
37
HKZ101
Function
The Hall-effect switch is actuated by a soft-iron vane that passes through the air gap between
magnet and Hall-effect sensor. The vane short-circuits the magnetic flux before the Hall-effect
sensor, as shown in figure 1. The open collector output is conductive (LOW) when the vane is
outside the air gap, and blocks (HIGH) when the vane is introduced into the air gap. The output
remains HIGH as long as the vane remains in the air gap. This static function does not require
a minimum operating frequency. The output signal shape is independent of the operating
frequency.
The circuit features integrated overvoltage protection against most of the voltage peaks occurring in automotive and industrial applications. The output stage has a Schmitt trigger
characteristic. Most electronic circuits can be driven directly due to the open collector output
current of max. 40 mA.
Principle of operation
@)
Hall IC
Fe Flux conductors
a) Magnetic flux through the
Hall-effect switch
with no vane
in the gap
Case
Magnet
Fe
Fe vane
==~~.
b) Magnetic flux
short-circuited by
the soft-iron
vane
Figure 1
Mechanical characteristics
The Hall-effect vane switch is hermetically sealed in a special plastic, so that it can also be used
under harsh environmental conditions. The package is waterproof, vibration-resistant and resistant to gasoline, oil and salt. Two tubular rivets are incorporated in the package to mount
the sensor on its carrier plate. The circuit has three flexible leads for power supply and output.
38
HKZ101
Application notes
The output current of the "open collector" must be limited to the maximum permissible
value by a load resistor adapted to the application.
For optimum efficiency of the integrated overvoltage protection, it is suggested that a resistor of approx. 100 Q be provided in the component's power supply to limit the current.
1
1001'l
red
40mA max.
green
black
Maximum ratings
Supply voltage
Test conditions
Vs
Tamb
Output voltage in OFF-state
Inverse supply current
(limited externally)
Output current
Inverse output current
Ambient temperature
during operation
Storage temperature
Thermal resistance (system-air)
Upper
limit A
-1.2
24
30
30
200
V
V
V
mA
mA
mA
=25 DC
-0.8
Va
-Is
Lower
limitS
Tamb~ 80 DC
t~1 h
without vane
Tamb
-40
40
30
135
Tstg
-40
150
DC
170
K/W
Ia
-Ia
RthSA
DC
Operating range
Ambient temperature
Supply voltage
Vane1): thickness
width
gap length
immersion depth
gap height
Tamb
Vs
a
b
c
h
d
-40
4.5
0.5
8
8
4.6
17.3-h
130
24
9
DC
V
mm
mm
mm
mm
mm
1) see figure 3
39
HKZ101
Test conditions
Characteristics
Vs=5Vt018V;
Tamb = -30°C to 130 °C
Output saturation .
voltage
Output reverse current
Supply current
Delay time
tLH, tHL
without vane
10 =40 mA
Tamb =-30 to 110°C
Tamb -110 to 130°C
with vane
without vane
10=40 mA
Vsz
Vso
Is= 16 mA
15=16 mA
Vosat
lOR
Is
Lower
limitS
Upper
limit A
0.4
0.6
10
12
1
V
V
42
42
V
V
\lA
mA
\ls
Overvoltage protection
- Supply voltage (Vs)
- Output (V0)
32
32
Switching point characteristics
Definitions
In most applications, the switching point is set exactly by mechanical adjustment, thus
compensating all mechanical tolerances in the system including the scatter of the Hall-effect
vane switch. For the function of the device in operation, only the deviations of those
characteristics depending on temperature and operating voltage are important.
The characteristic values of the switching points are, therefore, not directly referred to the
mechanical dimensions of the vane switch, but to an electrically defined symmetry Bo
according to formula 1):
1) Bo = (ONlelt + OFFlelt + ONright + OFFrlght): 4
Bo = Ao±0.3 mm
The definition of the operate and release points is shown in figure 2.
Operate point fON is obtained by subtracting the measured ON operate value from the
reference point Bo:
2) fON = ONright - Bo = Bo - ONlef!
The release point fOFF is calculated from the difference between the appropriate ON and
OFF points:
3) fOFF = ONright - OFF right - OFFlelt - ONlelt
fON 0 and fOFF 0 are the switching points measured for the individual component under
normal conditions (Vs = 12 V, Tamb = 25°C) within the characteristic device deviation
The deviations of the operate and release points are defined according to 4):
4) MON = fON - fON 0
L1 fOFF = fOFF - fOFFO
40
HKZ101
Switching point definitions
Ao
I
Soft iron vane
/
I
0
on
': I
0
A 0= Mechanical symmetry axis
Bo =Electrical symmetry axis
Bo
I
UU!
I--Bo=Ao~ O.3mm
PIii?
E uu
VQt~
:I :
OFF,
ON,
. ht
foff~
fon
....--
ton
left
. ,foff
ONI IOFIi
; I:
: I:i:
2m?!
p?lll
v. t~
I:
Q
I 1a?l2?
VQt~
I
Will
Bo
Figure 2
41
HKZ101
Mechanical measurement conditions
a) Measuring vane (material:soft iron)
b) Immersion depth
otff
Fe vane
I
Figure 3
Switching point characteristics
Vane: a =0.75 mm, b =8 mm, c = 10 mm
Position: center of air gap
Vs =5 V to 18 V
Test conditions
Lower
limitS
typ
Upper
limit A
0.85
-0.4
-0.2
-0.4
1.54
-0.8
-0.4
-0.8
1.45
+0.15
+0.15
+0.2
2.54
+0.3
+0.3
+0.4
2.05
+0.7
+0.4
+0.7
3.54
1.4
0.8
1.4
HKZ 101
Operate point
Deviations
.1fON
Release point
Deviations
.1fOFF
42
fONO
fOFFO
Vs=12 V, T amb =25°C
= -30 to 25°C
Tamb = 25 to 80°C
Tamb = 80 to 130°C
Vs = 12 V, Tamb = 25°C
Tamb = -30 to 25°C
Tamb = 25 to 80°C
Tamb = 80 to 130°C
Tamb
mm
mm
mm
mm
mm
mm
mm
mm
5041 P
FM IF Amplifier with Demodulator
DIP 16
S 041 P is a symmetrical, six-stage amplifier with symmetrical coincidence demodulator for amplifying, limiting, and demodulating frequency-modulated signals. The Ie is particularly suited for
sets where low current consumption is of importance, or where major supply fluctuations occur.
The pin configuration corresponds to the well-known TBA 120. Pin 5 of S 041 P, however,
is not connected internally. These types are especially suited for applications in narrow-band
FM systems (455 kHz) and in conventional or standard FM IF systems (10.7 MHz).
Features
•
•
•
•
Good limiting properties
Wide voltage range
Low current consumption
Few external components
Maximum ratings
Supply voltage
Junction temperature
Storage temperature range
V
Tstg
15
150
-40 to 125
Rth SA
90
K/W
Vs
7j
°C
°C
Thermal resistance (system-air)
S 041 P
Operating range
Supply voltage range
Frequency range
Ambient temperature range
Vs
f;
Tamb
14 to 15
o to 35
-25 to 85
1
~HZ
°C
43
5041 P
Characteristics (VS
= 12 V, Q approx. 35,
Current consumption
AF output voltage
(f; = 10.7 MHz, Llf = ± 50 kHz, V; = 1 0 mV)
Total harmonic distortion
(f; = 10.7 MHz, Llf= ± 50 kHz, V; =10 mV)
'mod
= 1 kHz,
Tamb
Is
Vq rms
= 25°C)
min
typ
max
4.0
100
5.4
170
6.8
rnA
mV
0.55
1.0
%
THO
Deviation of AF output voltage
(VS =15 V~ 4 V, f; =10.7 MHz,
M = ± 50 kHz)
Input voltage for limiting
(f;=10.7 MHz, Llf=±50 kHz)
dB
1.5
30
IF voltage gain (f; =10.7 MHz)
IF output voltagE'! for limiting
60
~V
dB
68
(each output)
Vqpp
130
mV
Input impedance f; = 10.7 MHz
f; = 455 kHz
Output resistance (pin 8)
Voltage drop at AF ballast resistance
AM suppression
(V; = 10 mV, M= ± 50 kHz, m = 30%)
Z;
Z;
20/2
kO/pF
kOlpF
kO
V
dB
3.5
Rq
V11 - B
aAM
All connections mentioned in the index refer to S 041 P (e.g. V11 )
Test circuit
10nF
f;
V,
=10.7MHz
14
>---tr--.-----O---l
12 turns
0.25 CuLS
44
50/4
5
1.5
60
8.5
o
~.
c
;:;:
0.
11
~)
~
12x
700Q
'--
~>
Sk(l
l:d
~~-l~~~'- K>~K ~~>r<>
SkQ
5k(l
5kQi
5.5 1.7
kQ kQ
4.2kQ
)J
I'
5k(l
1.7kQ
I
3.6kQ
3.6kQ
iii
3
[ 6kQ
SkQ
4.2kQ
5kQ
iii'
ce
I
5.5kQ
1.5
kQ
14
4
13
SkQ
10
~Q
~
___ J
26 9
en
o
~
U1
::
'tI
S041 P
Application circuit for 10.7 MHz (FM IF)
and 455 kHz (narrow-band FM)
Data in parentheses for 455kHz (narrow-bond FM)
Coils
46
10.7 MHz
455 kHz
15 turns/0.15 CuLS
12 turns/0.25 CuLS
041-2165
71.5 turns/12 x 0,04 CuLS
71.5 turns/12 x 0.04 CuLS
o 41-2393 of Messrs. Vogt
5041 P
Current consumption
versus supply voltage
mA
10
9
I
AF output voltage and total
harmonic distortion versus
supply voltage
f;=10.7 MHz; d(=±50 kHz
mV fmod = 1 kHz; Q approx. 35
%
250
5
IAFrms
......
.
6
~.
V
150
I
V
i-""
I
100
__ mean value f- - - max value f-'-
II
V ~
AF
~.
....
4
200
..
3
-- t---
--~
~
-
2
-
-
f-
n f---
---
50
THD
o
o
o
15V
10
-~
I-"
o
o
10
4
12
14 16 V
- - - VS
DC output voltage difference
versus supply voltage
(without signal)
V
Input voltage for limiting
versus supply voltage
f;= 10.7 MHz; Jf=± 50 kHz
~V f mod = 1 kHz; Q approx. 35
3
160
---
V; lim 140
1
120
2
----
100
I
./
I
80
V
60 f----
I
40
--
\
---
-
I
r-
I
r--
I
......
20
o
o
2
4
6
8
10
12
_Vs
14 16 V
o
o
---
4
1=
10
-I
--I
12
14
16 V
47
8041 P
AM suppression versus
supply voltage
fj =10.7 MHz; L1f= ± 50 kHz;
\II=10mV,fmod =1 kHz,m=30%
AF output voltage and total
harmonic distortion versus Q-factor
Vs =12 V; 1;=10.7 MHz,
M=±50 kHz, fmod =1 kHz
0/0
1.S
dB
80
aAM 70
I
mV
300
THO
60
I
,
50
/ 'T'
to
ZOO
,AFmsj
/
40
30
LL
0.5
100
~ .-"" T~O", a2
20
10
THO gei erafor 1= 0.3 %
0
0
0
2
4
6
8
10
12
-Vs
48
14 16 V
o
10
20
o
30
40
50
- a factor
Mixer
S042P
DIP 14
Symmetrical mixer for frequencies up to 200 MHz. It can be driven by an extemal source or by the
built-in oscillator. The input signals are suppressed at the outputs. In addition to the
usual mixer applications in receivers, converters, and demodulators for AM and FM, the
S 042 P can also be used as electronic polarity switches, multipliers, etc.
Features
•
•
•
•
•
Versatile application
Wide range of supply voltage
Few external components
High conversion transconductance
Low noise figure
Maximum ratings
Supply voltage
Junction temperature
Storage temperature range
7j
Thermal resistance (system-air) S 042 P:
Rlh SA
Vs
Tslg
15
150
-40 to 125
90
V
DC
DC
K/W
Operating range
Supply voltage range
Ambient temperature range
Vs
Tamb
14 to 15
-15 to 70
I ~C
49
S042P
Characteristics (VS = 12 V,
Tamb
= 25°C)
Current consumption
Output current
Output current difference
Supply current
Power gain
(f; = 100 MHz, fosc = 11 0.7 MHz)
Breakdown voltage
(l2.3=10mA; V7 . S =OV)
Output capacitance
Conversion transconductance
(f=455 kHz)
Noise figure
min
typ
max
2.15
0.52
Is
Gp
1.4
0.36
-60
0.7
14
2.9
0.68
60
1.6
V2, V3
25
Is = 12 + 13 + Is
12=13
13-12
C2. M,C3 - M
S=~=
V7 -VR
13
VrV~
NF
All connections mentioned in the index refer to S 042 P (e.g. 12)
Test circuit
\Is = 12V
~ F= 10.7 MHz
T
~.A.AAA.r-'
10n F
3/3 t urns
'osc -110.7 MHz
Connections in parentheses apply to S 042 E
50
1.1
16.5
rnA
rnA
rnA
rnA
dB
V
6
pF
5
mS
17
I dB
5042 P
Circuit diagram
2
3
8kQ
7 0----+------,
2.2kQ
2.2k\1
8~~-----------4----~
11o---_r-~~~----+_-------_r--__.
13 O---_r-j--~_{
1.4kQ
-+-I-____- - - - o 1,4,6,9,14
L - - - - - - - - - - - -____
12
10
A galvanic connection between pins 7 and 8 and pins 11 and 13 through coupling windings
is recommended.
Between pins 10 and 14 (ground) and between pins 12 and 14, one resistance each of at
least 220 Q may be connected to increase the currents and thus the conversion transconductance. Pins 10 and 12 may be connected through any impedance. In case of a direct
connection between pins 10 and 12, the resistance from this pin to 14 may be at least
100 Q. Depending on the layout, a capacitor (10 to 50 pF) may be required between pins 7
and 8 to prevent oscillations in the VHF band.
51
S042P
Output current versus
supply voltage
Total current consumption
versus supply voltage
~A
rnA
4
800 r-T------,-,----,---,---,---,-,----,--,--,
IfF
-1 J f-"',,""-' '· -;;;--tt
_.....
I
--+~ ~ --::;~~1
I"
. . . . . v V......... ' .............f~~---
..... ...
~
i
-~~-
4 5 6 7
- -f---
8 9 10 11 12 13 14 15 V
Power gain versus
supply voltage
Ul'
!iI/....-r-
--
,-- -
J --
.,.... ~I
i
I
!
i
12
10
1+,
I
I
I
I
- 111-
I
I
I'
I,
i
-
!
--t+-
~-
-
' I
i
-r
-
-
8
6
4 5 6 7 8 9 10 11 12 13 14 15V
-~
52
f-,,~"':::.r---l---I-t----I- - - -e500 I-I---II---+-r'"'""----k-l-~.-+--l-I----I-,-l-'-A
600,...
400
1--I--+~+--+-tt~t~t1
:~ ~=I-=---+-+~Bm
-!
4 5 6 7 8 9 Wn
~
13
-~
-Vs
dB
18
f
//
I,~
J'
-.-
~=~mO~~-4-4-+-+~~~~
~ ~V
SOUP
Application circuits
VHF mixer with inductive tuning
Mixer for remote control receivers
without oscillator
10.7MHz
il MH:
I
I
I
I
I
I
L ___ _
For overtone crystals an adequate
inductance is recommended between
pins 10 and 12 to avoid oscillations to the
fundamental tone.
Mixer for short-wave application
in self-oscillating operation
10nF
~II--~H--' 460kHz
1nF
m:,
Differential amplifier with internal neutralization, also suited for use as limiter
for frequencies up to 50 MHz or at
higher currents up to 100 MHz
1.6 ... 4.8 MHz
1,4,6,9,14
I
I
I
i
I
I
L .. ~-YY""'---"
4.7nF
6 turns
18 turns
L_____ ~ 4Oru,"'
53
54
S178A
Video Pulse Generator
DIP 28
The S 178 A is an MOS circuit using p-channel metal-gate-technology with enhancement and
depletion transistors, featuring the following technical characteristics:
The video pulse generator produces the sync, control, and erase signals required for the
control of cameras, mixers, and other equipment.
The following signals are generated:
•
•
•
•
•
•
•
Gating signal A
Sync signal S
Horizontal pulse H
Vertical pulse V
Terminal pulse Kt
Horizontal gating pulse A (H)
Double line frequency H/2 }
half vertical frequency VR
~ H/2
•
Vidicon gating signal VA
+ VR signal with external signal mixing
Features
All pulses are derived digitally from an input frequency corresponding to a pulse scheme, with
a duty cycle of 1 : 1.
Pulse width according to latest CCIR and EIA standards.
The following 6 pulse schemes have been programmed permanently (by 3-bit coding and line
number coding):
525 lines (60 Hz)
625 lines (50 Hz)
735 lines (60 Hz)
875 lines (50 Hz)
1023 lines (60 Hz)
1249 lines (50 Hz)
required
required
required
required
required
required
input frequency
input frequency
input frequency
input frequency
input frequency
input frequency
1.008
1.000
1.4112
1.400
1.96416
1.9984
MHz
MHz
MHz
MHz
MHz
MHz
Deviating from the above, any line number between 512 and 1535 lines may be programmed.
It should be noted, however, that a frame frequency of 50 Hz (partial picture duration 20 ms)
or 60 Hz (16.66) is achieved.
Within the operating frequency it is, however, possible to mix any standard position with any
line number.
The following relation applies:
Input frequency f\ = 64: line period H
= 32: line number Z x frame frequency ff'
Not for new design
55
S178A
Pin configuration
top view
Line
number
codinq
Vss
28 A signal
29/2 10
27
28
26 A{H) signal
V pulse
27
4
26
5
24 N
25
6
23 Nc
25 N'}
B
24
Pulse scheme
coding
22 Kt pubo=
23
8
21 S signal
22
9
20 H pulse
21
10
19
20
11
18 S{H) input
VR input
12
17 Clock input
VA signal
SlY) input 13
16 H/2 frequency output
VR output 14
15 Voo
Block diagram
~.
i
-.-.-.-.--.-.-.-.-.-.-.-.-.-.-.-.~
i
I
i
In putlclock)
f requen,cy
Horizontal
counter
64:1
i
I---------
Pulse-width
logic
f--------oo
H
program
I
I-------
I
i
Clock
gri-l
.c
I
'" I
~
2
c
>-
x
w
Vertical counter
or
line counter
Combination
of
H and V
,
H/2
J---------
Pulse-width
and
subsequent
logic
program
f----------
V
f----.
I
~
R=
1535: 1
3-bit coding tor
pulse scheme
A signal
S signal
VA signal
VR pulse
I
i
program
L·t·H·H·,·-·-·-ltf--·_·_·_·_·_·_·_·_
512~
10-bit binary code for
number oj lines
56
I
Combination
logic
H. pulse
HI2 frequency
output
A(H) signal
K t pulse
J
V pulse
S178A
Maximum ratings
Supply voltage
Voltage at all inputs
Input current
(VI =0.3 V; Vss=OV)
Output current
referred
to Vss =0 V
Characteristics
Tstg
0.3
0.3
100
V
V
Il A
-100
2
125
125
75
Il A
mA
-55
-25
Tamb
Test conditions
°C
°C
°C
typ
Upper
limit A
10
60
10.5
70
V
mA
Vss
-Voo+5.5
V
V
TTLGND+0.4
V
V
LPS GND-0.7
LPS GND+O.4
V
V
Vss -2.6
Voo
Voo+1
Lower
limit S
9.5
-Voo
Joo
Inputs
H input voltage
L input voltage
-12
-20
Tj
=25°C
Supply voltage
Supply current
Upper
limit A
IOH
IOl
Junction temperature
Storage temperature
Ambient temperature during operation
Tamb
Voo
VI
II
Lower
limitS
direct control
with TTL output
level
Vss -1.5
-VDD
VIH
Vil
Outputs
H output voltage
L output voltage
VOH
VOL
H output voltage
L output voltage
VOH
VOL
H output voltage
L output voltage
Signal transition time
of outputs
Input frequency
Propagation delay time
VOH
VOL
tT
when loaded
with one TTL input
JOH =-40 IlA
JOl =1.6 mA
when loaded with
2 LPS inputs:
JOH =-40 IlA
JOl =0.8 mA
for capacitive
load only:
Vss -2.6
when loaded with
2 LPS inputs
felK
tp
Vss -2.6
TTLGND-0.7
clock slope signal output
1
0.2
100
V
V
ns
2
0.4
MHz
Il s
57
S178A
Interface to 75 Q cable
A driver stage is required as the pulse generator outputs can be loaded with one TTL input,
each. The circuit is to be designed according to the diagram below.
As a driver stage for the 75 Q coaxial cable, the TTL circuit 75453 (maximum output current
300 mA; pulse delay 11 ns) is recommended.
~S'OV
OV OV
OV
OV
Ij~+---T--I~~7==_-ooU:
I -----Y~
VDD • -10V
-5V
S 178A outputs
75453
75\1 cable
Programming list for line number coding
Pin number
2
3
4
Line number
29
28
L
L
1023
1022
H
H
H
H
H
H
H
H
H
H
1249
1248
L
L
L
L
525
524
625
624
735
734
875
874
58
7
8
9
10
11
25
24
23
25
24
23
22
21
20
NA
Ns
Nc
L
L
L
L
H
H
H
L
H
L
H
L
L
L
L
H
H
H
L
L
L
H
L
H
H
L
L
H
H
H
H
H
H
L
L
L
L
L
L
H
L
H
H
H
H
H
L
L
H
H
H
H
H
H
H
L
L
H
H
L
L
L
H
H
H
H
H
H
L
L
H
L
L
L
L
L
L
H
L
H
H
H
H
L
H
L
H
5
6
27
26
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
T-
Second field 120msl
line
frequency
H
----------l~
Reference.
no output
~rrh~~rnnr
I
( I" I I " I III
H pulse
ryj ;I ' I' , ,
I
V.
VA signal
V pulse
~~
~tu-rl~W~
AIHI
Kt
---
tumnn1~~
I
H12 Sync.
First field 120msl
HH "1
tjniJ
•
A signal
.
H/2
I
I
_
·lklHI
S signal.
.~+~s. "'
AIVI160o.l
I
12SHI
2.S~s Jts~s ~S~ I 2.5~s 14.5~S
~rr--L r- j ~:I
I
5campensD.t~ng Sinterrupting
pulses
,
I ·"t""
Fl'
U
I
pulses of the
SIVI
5 compensating
pulses
I
,
-:
if
1':::T:
~ID
..0'
0)
N
en
S'
m
I' 1*11' ' Ir' , .;;~~'I Ii"! .~~
!
I JF'rl~'I
'600.0~S
rlI'
I
I
I II
;.AIHI
ru--in1
If'---
trui
I
H/2
A IVI
I
12SHI
I
AIHI'
Ahr1rt-
I II
T J ru---r-n-
II
5 compensating Sinterrupting Scompensating
puLses
pulses of the pulses
SIVI
Input frequency: " • lHHz
"Internally shifted AIHI
....tn
~
01
CD
~
~
Pulse width table for the programmed line numbers
525
f= 1.008 MHz
to = 0.49603/Ls
Pin
No.
/Ls
-
Line period H
,H/2 synchronization
625
f= 1.000MHz
to = 0.5/Ls
to /Ls
128
63.492
735
f= 1.4112MHz
to = 0.3543/Ls
to
to /Ls
64.00
128
875
f= 1.400 MHz
to = 0.3514/Ls
/LS
to /LS
·128 32.583
128 45.7142
45.3514
1023
f= 1.96416 MHz
to = 0.25456/Ls
1249
f= 1.9984MHz
to = 0.2502/Ls
to /LS
128
to
128
32.025.6
31.75
64
32.00
64
22.68
64
22.86
64
16.29
64
16.01
20
H pulse
6.45
13
7.0
14
4.96
14
4.99
14
2.54
10
2.5
10
26
Horizontal
gatingA(H"j
10.91
22
12.0
24
7.08
20
8.57
24
7.13
28
6.0
24
21
Horizontal
synchronization S (H)
4.46
9
9
2.83
7
2.85
7
2.54
10
2.5
10
16
4.5
64
20
Front porch
1.48
3
1.5
3
1.06
3
1.07
3
0.76
3
0.75
3
21
Equalizing pulses
2.48
5
2.5
5
1.414
4
1.42
4
1.02
4
1.00
4
21
Interruption ofthe
4.46
V-synchronization pulse
9
4.5
9
2.48
7
2.5
7
1.78
7
1.75
7
22
Terminal pulse Kt
1.49
3
19
Vidicon
gating VA (H)
9.42
19
19
Vidicon
gati ng V A (V)
15H
+
19to
15H
28
Vertical
gatingA(V)
20H
+
22to
25H
14
VRsignal
27
Vpulse
21
Number of pre- and
post equalizing pulses
15.87
32
1
2
0.7
2
0.71
2
1.53
6
1.5
6
19
6.73
19
6.78
19
4.83
19
4.75
19
+
19to
20H
+
19to
20H
+
19to
30H
+
19to
30H
+
19to
+
24to
30H
+
20to 30H
+
24to
40H
+
28to
40H
+
24to
32
8.15
32
8.01
9.5
16.0
32
11.34
32
11.43
9.5H
10H
14.5H
15H
6
5
6
5
20H
6
32
20H
6
Duty cycle f, = 50%!..... = 2 to
f,
CJ)
......
~
00
»
S178A
Line programming
Any line number between 512 and 1535 lines is binary-programmable. A binary "1" is applied
to the pins 2° to 29 with condition Vss ~ V1 ~ Vss - 1.5 V and a binary "0" with Voo ::;V1 ::; Vss
- 4.5 V. The correct programming of the MSB 210 is carried out automatically via pin 29 within
the line number range of 512 to 1535.
Uneven line numbers (interlaced scanning method)
The binary form of the desired line number is switched to the corresponding pins.
Even line numbers
The desired line number is reduced by 1 and the binary form is switched to pins 20 to 29 ,
the LSB (2°) is switched invertedly.
Functional description
The principal units of the pulse generator are the horizontal and the vertical counter (see block
diagram). The horizontal counter, divider ratio 64 :1, divides the input frequency down to twice
the line frequency H/ 2 .
An additional logic ensures, that a defined condition of the switching stages is submitted to
the counter after a maximum of one picture change. The vertical counter is externally programmable to a defined line number.
Due to the external 3-bit enconding, the desired pulse scheme is programmed internally;
i.e. the appropriate switching units for realizing the H and V program, are enabled. The pulses
are now fed either directly to the outside, or are logically mixed and masked in the combination logic. The pulse start or the pulse widths, respectively occur at H/2 sync defined
according to time. In the case of even line numbers, only the first field appears for all pulse
schemes, preceded by a VR pulse.
In the case of uneven line numbers with first and second fields (interlaced scanning), the VR
pulse precedes only the first field.
According to the CCIR standard, the first field starts, when the leading edge of the V pulse is
synchronous with the leading edge of A (H).
61
5178A
External synchronization with H/2
+ VR or S signal
For video mixing and cross-fading, the BAS signals of the individual cameras or video recorders must be sycnrhonized, i.e. correspond in line and picture. In the case of external synchronization, these two components must be contained in the external signal: either the horizontal
and vertical frequency in the case of the S signal: S (H) and S (V), or S (H), and half of the
vertical frequency (H/ 2 + VR).
At the beginning of the leading edge, short pulses must be derived from these two H and V
components, and thereby the defined setting of the horizontal and the vertical counter is
accomplished.
(Standard value: H component 300 ns < clock period
V component 1 IJ.s < H/ 2 )
Because of the time deviation of the front edges of the line frequency Hand S (H), which is
1.5 periods of ihe inpui frequency, ihe i-Iorizoniai counier wouid be set incorrectiy. For this
reason, an input S (H) has been selected for the horizontal component, which sets the counter
to the correct position when activated.
The same is valid for the vertical components of H/2 + VR and the S signal. The first frame
frequency pulse follows 2.5 or 3 line periods behind the VR pulse, depending on the scheme.
The two inputs provided for the pulses from VR or S (V), respectively, and the correspondingly
encoded line scheme enable a proper setting of the vertical counter. Through the possibility
of a defined setting of the counters it is ensured that a proper standard pulse scheme is
obtained at the outputs even in the case of external synchronization involving different phase
conditions of the synchronization signals.
Note:
At the time of setting the horizontal counter to a defined position, the phase relation of the
input frequency is undefined and consequently the tolerance of the synchronization would
be one clock period (Le. s 1IJ.s for 625 lines). By means of an external phase synchronization
circuit with frequency multiplication, the input clock can be derived from the vertical component and, thereby, a defined phase relation of the reset pulse achieved relative to the input
clock. Hence a common line deviation Qitter) of < 20 ns absolute value can be achieved.
Control
The pulse generator derives the required pulses from the output frequency. As additionally
half a clock period is used for the generation of the pulse widths, and as both the leading
and trailing edges are used, an input duty cycle of 1 : 1 is required.
It is, therefore, recommended to operate the quartz oscillator at twice the input frequency and
to divide it 2 : 1 by an external stage, thereby obtaining an accurate duty cycle of 1 : 1Inputs which are not used must be connected to Vss (H level).
62
S178A
Control with TTL
I
#{'~
-5V
I
V
I
S178A
I
TTL
00'
-10V
A TV clock generator, externally synchronizable, using the integrated
video pulse generator S 178 A.
+5V
[ 1kll
Oscillator
blocking
-
}kll
~I'~~
-
1MHz
~
22 Kt
5
~
6
S
Kt
V
A
7
~
,ll
~
~
S 178 A
Nc
NB
NA
10 HEF 4050
9
12
11
27 V
15
14
28 A
I~ A(H)
13
~
c-11
i~ t--
2°
22
H
21 S
~
4
H
S(H)
20
1
H/2
Input {S(V)
VR
19
VA signal
1~
VR
17 Clock
~
2
Voo
16 H/2
4
S(V)
input.
external
~
cL t--
23~ t-24
el-
2s~
26~
27~ t-2B~ t-29~
Vss
.J-
8
1
I
&
=[j1/4 74 LSOO
-5V
63
64
5 353
51353
52353
Programmable Diode Matrix
DIP 28
DIP 14
5014
This S 353 contains 160 diodes arranged in a 10 x 16 matrix. The S 1353 contains 32 diodes
arranged in a 4x8 matrix, the S 2353 contains 42 diodes arranged in a 7 x6 matrix.
For programming, an NiCr fuse is connected in series with the diode.
The matrix is primarily suitable:
1. to replace the extensive wiring in preselection switches. Instead of the multipole wired
switch, a single-pole model can be used. Switch and matrix are connected in series.
2. to be used as encoder, decoder, and recorder. The matrix is connected before or behind
the appropriate components, or connected between them. The electrical level is only
changed by the value of one diode voltage. The electrical connection remains.
3. The component requires MaS handling to avoid undesired programming.
One of the most important applications is e.g., to enable the programming of frequencies
or line numbers, respectively, in conjunction with the PLL component S 187 and the video
pulse generator S 178 A.
Maximum ratings of the individual diodes including fuse
Lower
limit B
Reverse voltage
Voltage between
I and as, Q and 0 5 1)
Forward current
Programming current
Junction temperature
Storage temperature
Ambient temperature range
I)
vo';; \'I; Va; example: if \'I.
Va are positive
VA
20
VIO, Voo
a
IF
Iprog
7j
Tstg
TA
-40
-25
Upper
limit A
V
20
2
70
125
125
70
V
mA
mA
°C
°C
°C
as must be grounded.
65
8 353
81353
82353
Electrical characteristics of the individual diodes including fuse
TA = 25 °C, if not otherwise specified
Reverse voltage
Forward voltage
Reverse current I-Q
Reverse current l-os1)
Programming current
Resistance of the suitably
programmed fuse
Capacitance I-Q
Recovery time
VR
VF
IR
IRa
Iprog
R
C
frr
1) Reverse current of a single substrate diode
66
Test
conditions
Lower
limit B
I R= 100 !-LA
I F= 1 mA
I F=50 !-LA
20
Upper
limit A
1.0
V
V
V
0.8
0.85
V
10
100
500
70
nA
nA
mA
9
MQ
pF
ns
1.5
TA =-25°C
IF = 15 !-LA
TA =-10°C
VR=10 V
V,= 10 V
Va=20V
V,=OV
Va =-2 V
IVa-V,I~5V
VR=2 V
h=200 !-LA
VRmax =2 V
RL =1 kQ
Test at
VR=OV
typ
50
20
6
13
25
5 353
51353
52353
Programming conditions and simple programming circuit
Using the circuit shown. the matrix can be programmed in the following manner:
1. observe MOS handling
2. connect pin Os (substrate) to ground via a -2 V voltage source
3. connect desired input I to ground using switch S 1
4. select desired output Q with switch S2
5. trigger programming process with button T3
6. the specified voltage source with 18 V to 20 V must be suited for a load of at least
300 Q (fuse resistance). and must have a rise time from 0 V to 20 V of 1 Ils
7. only one fuse may be programmed at a time
8. a current pulse duration of 5 ms to 10 ms is sufficient for programming.
$+~--~~
1a'20V
I
t
S2
l~±t~~nmn
~I" 1
~SUb.lpinOs
67
5353
Pin configuration
top view
016
28
27
26
25
24
23
22
21
20
19
18
17
16
• 03
15
[::::::::::::]
1
2
3
Os
11
12
4
13
5
14
6
7
15
16
8
17
9
18
10
19
11
110
12
T
13
01
14
02
Circuit
11
12
110
13
'---+---=---1-
---"'----------1-~---__oQ 1
r8>!-
~[;>t- ----~
0;<;>--;-8>!- -----~----SJ.. IL8>!- ----- -----,--------------------
t
'-----"'---=<----------'0.------0016
Note: Inputs must not be open VI
Test pin T must not be connected.
68
< Va
S1353
Pin configuration
(top view)
01
14
02 03
13 12
T
11
04
10
as
9
06
8
[~~5:::]
1234567
07 Os 11 I 2 13 I 4 08
Circuit
11
12
14
~----~------------~--~~~Q1
~~--~-------------r--~~~Q2
r~
I
°rt~
Li)!'--------+---·----------------'-~Q8
Note: Inputs must not be open
\tI/-
'---'--~------------------~~Q6
Note: Inputs must not be open
V; 400 ms), the conduction angle will be varied
continuously. It runs across its control loop in approximately 7 s (e.g. bright-dark-bright) and
continues this sequence until the finger is removed from the sensor.
The following process is carried out to enable an easy operation also in the lower brightness
range: the phase control angle is controlled such that during the run across the control loops,
the lamp brightness varies approximately physiological-linearly with the operating time,
and rests for a short period when a minimum brightness is reached.
The conduction angle can be controlled in the half wave range between 35 0 and 152 0 by
.
means of the sync input circuitry (R 2 , C4 ) specified in the application example.
By increasing the RC time constant it is possible to shift the control range towards smaller
conduction angles (effects the minimum brightness).
74
5 576 A, B,C
55760
Control behavior
The three versions S 576 A, S, C, differ in their control behavior.
S 576 A With turning on, the maximum brightness is always set; with dimming, control is
started from the minimum brightness. With repeated dimming, control is carried
out in the same direction (e.g. "brighter").
S 576 B With turning off, the selected brightness is stored and again set when the switch is
turned on. Dimming starts at that stored value and the control direction is reversed
with repeated dimming.
S 576 C With turning on, the maximum brightness is always set; with dimming, control is
started from the minimum brightness. The control direction is reversed with repeated
dimming.
Control behavior of the electronic dimmers S 576 A, B, C
(schematic)
~
S
l..O.-n.-O-O
ex 180'
I
I
I
I
I
I
1
I
:
I
I
I
150'
I
I
:
!
I
I
I
1
®
I rnno=J
S~
Sensor
S576A
90'
:
: I
I
I
I
I
I
':
:
:
I
i
I I
I
I
I
I
I
I
I
VLO
------r---+~--~--+---~-I
I
I
I
VLmc.x
I
VLmin
VL=O
30'
OL-~~--~~-------------r--~--+-~--~-L
VLO
180'
ex 150'
Vlmax
190'
I 30'
@
O~~--~-r~---------------r---T'-~--~--;-~
180'
ex 150'
S576C
t
I
VL
t
S576 B
©
VL
Vlmin
VL=O
VLO V
L
Lma
V
'
90'
30'
OL-~~--+-~-,--.-,--.-,--,-,--,~-L,--.-L
3
4
5
6
8
9
10
11
12 13
14 15
I
Vlmin
VL=O
5
-t
(){ Conduction angle
VL Lamp voltage
5 Control signal: S Sensor touched
(- <0.45;->0.45 I
5 Sensor not touched
A S 576 A
B S 576 B
( S 576 C
Figure 1
75
S 576 A, B, C
S5760
2. Light switch 5 576 D (see figure 2)
Upon touching the sensor area (> 50 ms) the lamp is turned on or off alternatively with
maximum brightness. The switching process is activated at the start of touching.
Dimming or turning off the light via the clock input is also possible, as in the case with the
dimmer.
Control behavior of the electronic light switch 5 576 D (schematic)
~J
0
,
I
,
I
r:::1
30·
0
I
I
I
2
3
4
I
5
i
I
6
7
--f
ex Conduction angle
Vl Lamp vol tage
S Control signal:
S Sensor touched
S Sensor not touched
Figure 2
External circuitry (see figure 3)
The suggested circuit design of S 576 performs the following functions:
•
current supply for the circuit (R1, C2 , D 1, D 2, C 3)
•
filtered signal for synchronization of the internal time base (PLL circuit) with line frequency
(R2' C 4)
•
•
protection of the user (Ra, Rg)
sensitivity setting of the sensor (R 7 )
•
current limitation in the case of incorrect polarization of the extension (R 5 , Rs).
Both resistors can be omitted if no extension is connected. In this case. pin 6 must be
interconnected with VDD (pin 7).
•
D 3: reduction of positive voltages which may arise during the triggered state at the gate
of some triacs, to values below Vss + 0.5 V (refer to characteristic data). If suitable triacs
are used, diode D 3 can be omitted. (This feature of the triac depends on the anode current
and on the internal resistance between G and A 1, and can be measured and specified by
the manufacturer).
76
5 576 A, B,e
55760
Application circuit S 576
Phase
r-
Si
I
I
-------,
I
2A
I
I
I
I
220Vacl
50Hz
[,
©
I
I
5
1.5H(/
15IJF
IO.250V
ac
I
I Dr (BZX831
15
I
R, [2
I
1k(//1WO.2IJF BAY 61
L ___ _ 250Vac_
6 R6
®
470k(/
47IJF
16Vdc
Ra
I
I
R9
47 I
H(/
4.7
H(/
-15V
R\
120k(/
O.4W
400W
Hp
Electron.
extension
Extensions
At 110V/60 Hz line
[2 :O.68IJF/160V ac
-'
Sensor
central unit
Figure 3
Extensions
All switching and control functions can also be performed from extensions which are connected to an extension input reserved for this purpose. The central unit and the extensions are
equivalent. Electronic sensor switches or mechanical pushbutton switches can be connected
to the extensions. During operation, H potential must be applied to the extension input for
both line half waves.
An electronic circuit suitable for this purpose, is shown in the application example (figure 4).
The circuit operates as return delay and takes over the triggering of the switching transistors
during the negative line half wave.
•
•
•
Response time approx. 2 ms
Return delay time approx. 30 ms
Protection against incorrect polarization (R1' D 1, Si)
77
8576 A, B, C
85760
Application circuit: electronic extension
®Phase
,-----I
Si
I
O.032A
fast
I
I
I
I
!
®
10nF
03
BZX97
01
BZY971
C1B
.,~21O~
C6 VB
I
I
BAY 61
"F
I
~:---~t~~_J
Central unit with S 576
Sensor
Figure 4
Wireless remote control
The connection of a wireless remote control to the extension is very easy. All functions of the
S 576 can be performed with the aid of a single transmission channel.
Slumber switch (clock input)
In the unused state, the clock input is short-circuited to Vss. A slumber switch can be
obtained by applying an externally generated clock to this input. Each H L transition decrements the count of the internal brightness memory by one step. When the minimum
brightness is reached, the clock turns the circuit to the OFF-state.
78
5576 A, B, C
55760
The application example (figure 5) shows an oscillator circuit which can also be connected
to the power supply of the electronic dimmer or light switch by means of S 576.
The oscillator is enabled by touching the slumber switch sensor. Touching of the dimmer
sensor disables the oscillator and, thereby, interrupts the automatic system.
Circuitry
• Oscillator with CMOS gates
• T 1 and T 2 provide a steep switching transition at the input of gate G 3 in order to
minimize current consumption « 100 IJ.A)
• Setting of the clock frequency and thus setting of the dimming time with the RC network
(Rs, C 2 )
• Sensitivity setting of the sensor area (R 1)
Application circuit: S 576 with a slumber switch
Phase
1...
47MQ
BC237B
220Voc
50 Hz
I
I
I
I
I
lt
L
Mp
5
7
4.7MQ
I
I
47MQ
---Sensor
central unit
I
I
I
I
I
I
__ J
Sensor
slumber switch
Figure 5
79
S576A, a,c
S5760
Interference immunity
A digitally determined immunity period of approximately 50 ms ensures a high interference
immunity against electrical variations on the control inputs, and allows simultaneously an
almost delay-free operation.
Due to the special logic of the extension input, even large ground capacitances of the control
line will not lead to interference.
In the case of line interruption, the set switching state with the recommended external
circuitry remains stored for about 1 s. After line interruptions for longer periods the circuit
turns into the OFF-state.
General information
All stated time specifications refer to a line frequency of 50 Hz. In the case of a line frequency
of SO Hz, the peiiods are shoil:€:ned accordingiy.
80
SAB0600
SAB0601
SAB0602
Three-Tone Chime
Single-Tone Chime
Dual-Tone Chime
DIPS
Three·tone chime SAB 0600
This Ie generates the tone sequence of a 3·tone chime. The sound pattern is created by
three harmonically tuned frequencies which are switched in succession to a summing point
and decay individually in amplitude.
The tone color is adjusted by an external Re network (RJ,
can be connected directly via a 100 ~F capacitor.
e
j,
and
e 2). An 8 Q loudspeaker
An appropriate design of the loudspeaker housing (shaped as tube or horn) enhances the
volume and tone quality and contributes to a pleasant, melodious sound.
Features
•
•
•
•
Melodious sound
Few components required
Integrated output stage for 8 Q loudspeaker
Standby current < 1 ~A
Single.tone chime SAB 0601 and dual·tone chime SAB 0602
The two variants SAB 0601 and SAB 0602 were derived from type SAB 0600 by suppressing
the last two tones or last tone, respectively, of the three-tone sequence. The SAB 0600 data
applies correspondingly.
Maximum ratings
Lower
IimitB
Upper
limit A
Supply voltage
Input voltage at E
Neg. input current at E
Load resistance at Q
Current consumption at
start of tone sequence } refer to
end of tone sequence
measurement circuit
Oscillator frequency at C
(due to power dissipation)
-0.5
-0.5
11
Vs
2
Thermal resistance (system-air)
90
35
ISM
Junction temperature
Storage temperature
V
mA
Q
7
Iso
fosc
v
6
150
125
-55
120
RthSA
rnA
rnA
kHz
_°C
°C
K/W
Operating range
Supply voltage
Ambient temperature
Oscillator frequency at C
Vs
Tamb
fosc
Ii
1
11
70
100
Iv°c
kHz
81
SAB0600
SAB0601
SAB0602
Characteristics
typ
max
10
35
Po
Vopp
<1
20
0.16
2.8
..1VOM
±5
min
Vs~7 V to 10 V; Tamb =25 °c
Standby input current
Supply current with open output
Max. output power at 8 Q (tone 3)
Max. output voltage at Q (tone 3)
Deviation of the max. individual
amplitudes referred to tone 3
Frequency variation of basic
oscillator with R1• C1 = const.
Triggering voltage at E
Input current at E (VE = 6 V)
Noise voltage immunity at E
Triggering delay at '0 = 13.2 kHz
(td varies in inverse proportion to ' 0)
Min. vaiue of external load resistor
Max. value of external load resistor
82
10
Iso
VE
IE
1.5
500
VENpp
td
2
R1
R1
W
4.0
Vs
700
0.3
5
1
10
100
V
%
±5
..1fo
IlA
mA
%
V
IlA
V
ms
IkQ
kQ
SAB0600
SAB 0601
SAB 0602
Measurement circuit
SAB 0600
3a
2 Vs
4 GND
I
~-{1=k=~}- _ _ _ _
Jaw-type probe
Rt
Storage
OS( Is = f(f}
[tT100~F
Figure 1
Integral current consumption in the measurement circuit
mA
120
ISH
80
"r
60
..........
r-.....
/Max.permissible limit value
~ ..........
V""
40
Typical run
at ~ =lOY and
'ose =13.2 kHz
20
o
=90mA
o
3
~
~
4
~ r-.....
.............
~
Iso =35mA
r-:-
r--
6
8
9
10 s
-f
Figure 2
83
SAB0600
SAB0601
SAB 0602
Block diagram
Vs
---~..----_--<..-----------~-----4---~
E
Power supply
>'s+
6.4V+--C=::J--~
R
Digital tone generation
I
Figure 3
84
SAB0600
SAB0601
SAB 0602
Typical application circuit
E 1
L [2 100nF
R,
Vs
~~------------------~2
R 33kll
7.. 11V
5
Figure 4
Functional description
The three frequencies - 660 Hz, 550 Hz, and 440 Hz - are obtained by dividing the output of
a 13.2 kHz oscillator. One of these three frequencies is divided again to obtain the time base
for the tone-decay process. From this time base, 4-bit D/A converters (one for each tone)
generate the decay voltage with which the three tones are successively activated and, overlapping each other, are attenuated. The basic frequency is determined by an external RC
network (pins R and C).
The output stage can drive an 8 Q loudspeaker with approximately 0.16 W via 100 IlF. The
output voltage is of square shape. To obtain a melodions output tone as required, the
higher harmonics may be reduced by shunting pin L through a suitable capacitor to ground.
The output volume can be regulated here by means of a potentiometer.
The circuit only draws current in the active state, and automatically switches off after the
tones have decayed. The circuit is activated by a short pulse, between 1.5 V and Vs in
amplitude, applied to the triggering connection E (pin 1). If the trigger voltage is still, or again,
present when the tones have decayed, the three tones are repeated.
The circuit is not activated when a trigger pulse on E is shorter than 2 ms (interference
suppression).
To prevent triggering of the circuit by cross-talk voltages, especially in case of long input
lines, the noise voltage peaks should be limited to 0.3 V at the IC input. For this purpose
the control line (possibly in front of a series resistor) can be shunted to ground through a
suitable capacitor.
85
SAB 0600
SAB 0601
SAB0602
Application for ac and dc triggering (figure 5)
The input can alternatively be triggered with direct or alternating current. An internal diode
circuit hereby short-circuits the input for negative halfwaves.
The peak voltage of the positive halfwave is added to the battery voltage. A series resistor
must be connected into the trigger line to limit the voltage at input E (pin 1) to a maximum
value equal to Vs.
The minimum input current at pin E of the SAB 0600 (pin 1) is 500 iJA at 6 V. If the voltage
drop occurring at 500 iJA at the series resistor R3 (figure 5) amounts to at least the ac peak
voltage between A and B (liAS -), the Ie will be safe.
R
The formula
VAS
-
max.
500 iJA
3 min -
determines the !o'.JI!er limit fer H3 .
The upper limit for R3 is determined by the lowest trigger voltage between A and 0 (pin 4).
In the application shown in figure 5, this will be the battery voltage if the device is also to be
operated independently of the bell system (triggering by short circuit of A and B).
For reliable triggering, the SAB 0600 requires a current of at least 50 iJA with approx. 1.5 V
at pin E. Assuming this current, the voltage drop at R3 must, therefore, not exceed Vs - 1.5 V.
R
The formula
_
VS
3 max -
-1.5 V
50 iJA
min.
results in the upper limit for R 3 •
Calculation example for the circuit in figure 5
max.
VAS rms =
max. VAS
25 V
35.4 V
=
= 25 V x v'2 = 35.4 V
70.8 kO
500 iJA
min. Vs= 6 V
(The operating range of the SAB 0600 may extend to 6 V for individual components).
=
6 V -1.5 = 90 kO
50 iJA
In this example, a value of 82 kO ± 10% would be suitable for R3 .
86
SAB 0600
SAB 0601
SAB 0602
Circuit for SAB 0600 application in home chime installations utilizing
ac and dc triggering; adjustable sound and volume
c0
:;::
E
~
N
.!:
0
~OJ
<..7
C
C
OJ
E
<0
"'[J
8
OJ
.3
..c
>
>-
0
d
r:-
~d
.D
.e
r:d
'"'"
~
-
]
::l
"0
'"
E
.D
ai
..c.
.~
d
:z
c::
~I
§
:;::
0
c
~
:::c
«
co
Figure 5
PCB layout information: Because of the high peak currents at Vs , Q, and 0 (ground) and to
avoid RF oscillations, the lines should be designed in a flatspread way or as star pattern.
Star points are the terminals of capacitor C 4 .
87
SAB 0600
SAB 0601
SAB 0602
Further details regarding the circuit in figure 5
Because an ohmic contact between A and B causes triggering of the chime, no bell may be
connected in parallel to the chime. However, paralleling several chimes does not cause any
problems.
In older batteries, the higher internal resistance of the battery may cause voltage drops
becoming apparent as distortions. C4 serves as a buffer element expanding the service life of
the battery.
The trigger line connected to pin A acts - in open state - as antenna for noise pulses which
could trigger the chime unintentionally. Capacitor Cs will largely suppress such interference.
If there is the risk of incorrect polarity connection when changing the battery, the battery
line should be protected by a diode.
For the selection of components, the following recommendations are given:
Capacitors:
C1 :
C2 :
C3 :
C 4:
C s , C6 :
4.7
100
100
100
330
nF/~
10 V, ±
10 V, ±
5%; e.g. MKT
20%; e.g. MKT
IlF/~6.3 V, ± 100/-10%; e.g. aluminum electrolytic
IlF/~ 10 V, + ,100/-10%; e.g. aluminum electrolytic
nF/~ 50 V, + 100/-20%; e.g, ceramic
nF/~
Resistors:
R3:
R1:
88
82 kQ/0.1 W, ± 10%, carbon film resistor
When a fixed resistor is used, 0.1 W ± 5% metal film resistor.
SAE0700
Audible Signal Device
DIP8
The audible signal device SAE 0700 generates two tone frequencies in a ratio of approx. 1.4 : 1
that follow one another in a periodic sequence. The tone frequency can be varied throughout
a range between 100 Hz and 15 kHz by an external resistor. The switching frequency of
0.5 to 50 Hz is set by an external capacitor. The SAE 0700 can be used to drive either a
loudspeaker or a piezo-ceramic transducer. The SAE 0700 can be supplied with voltage in
two ways:
1. rms ac voltage from 10 V
2. dc voltage from 9 to 25 V
The SAE 0700 issues the tone sequence for as long as the supply voltage is applied. After
application of the supply voltage, the tone sequence commences with the higher of the two
tones.
Features
•
•
•
•
Direct ac-voltage feeding possible through integrated bridge rectifier
Integrated overvoltage protection through Z diode, approx. 28 V
Bridge rectifier provides for protection against incorrect polarity in dc operation
Few external components (one resistor and one capacitor minimum)
Block diagram (with external components for dc supply)
7 Va(
I
Bridge rectifier
tic 18
Vs
~~~
1
VAC
2
Threshold
circuit
~I
Switching
frequency
Tone
frequency
generator
generator
SAE 0700
Output
stage
I
2 GND
3
res
r
~
Va
~ resonator
Pieza
4
R,
Figure 1
89
SAE0700
Functional description
The audible signal device SAE 0700 (see blcok diagram, fig. 1) includes the following functional
blocks:
•
•
•
•
•
bridge (for voltage supply) and overvoltage protection
threshold circuit
switching-frequency generator
tone-frequency generator
output stage
Bridge rectifier: The bridge rectifier enables direct feeding with ac voltage or dc voltage
(independent of polarity). DC-voltage supply without integrated bridge is also possible via
pins VDc and GND.
If the vo!t8.ge is s!JppHed via the bridge, the input vc!tage V8 i ehcL:!d be d:mensioncd such
that at least 9 V appear at the pin VDC (also with output loading). It should also be noted that
in the case of voltage supply via the bridge, the maximum output current has to be. limited
to 50 mA.
Response of the SAE 0700 as a result of spikes on the AC line is prevented by a built-in
initial resistance R 1N1. In a voltageless condition RINI provides for discharging the storage
capacitor of VDC to ground.
The Z diode following the bridge serves as overvoltage protection. The bridge circuitry shown
in figure 2 efficiently protects the SAE 0700 against damage as a result of the following
voltage values:
overvoltages in acc. with VDE 0433 (2 kV - 10/700 ~s)
ac voltages up to 220 Vl50 Hz for a duration of 30 s
•
•
O.lIJ F
a
HI
10kl1
t---+-------C:J------,
8 VA(1
7 Voc
.-~~-r~~--~-,
Vab
I
..16k1111700Hz
Figure 2
90
SAE0700
Threshold circuit: With a threshold voltage of typically 8.6 V this ensures that the SAE 0700
is not activated by noise pulses.
Switching-frequency generator: This switches periodically between the two frequencies
produced by the tone-frequency generator. Wiring with a capacitor Cs produces a switching
frequency fs according to the following formula:
fs [Hz]
=
750
C [nF] ± 25%
(valid from 0.5 to 50 Hz)
Tone-frequency generator: This generates a squarewave voltage with the two tone frequencies fT1 and fT2 . The basic frequency fT1 and the second tone frequency fT2 are calculated according to the following formulae:
fn [Hz]
2.72 X 10 4
± 25%
R [kQ]
=
fT2 [Hz] =
fT1
(valid from 0.1 to 15 kHz)
x (0.725 ± 5%)
The tone-frequency generator is temperature-compensated for better stability.
Output stage: This boosts the generated tone voltage for direct driving of a piezo-ceramic
transducer or a loudspeaker, possibly across a dropping resistor.
Pin configuration
Pin No.
Symbol
Function
1
2
3
4
5
6
7
8
VA.C 2
GND
AC-voltage input
Ground
Connection for capacitor Cs
Connection for resistor RT
Output
Not connected
DC-voltage input
AC-voltage input
Cs
RT
Q
N.C.
VDC
VAC1
91
SAE0700
Maximum ratings
Voltage at pin 7
Voltage at pin 3
Voltage at pin 4
Output voltage at pin 5
AC voltage at pin 8 and 1
(peak value)
Input current of bridge
AC input current of bridge
Output current
(50 f.ls, duty cycle 1 : 10)
Output current
Total power dissipation (Tamb = 25°C)
JU!lct!on temperat!..!!'"e
Storage temperature
Thermal resistance (system-air)
VDC
V32
V42
Va
Lower
limit
Upper limit
-0.5
-0.5
-0.5
-0.5
26
5.5
7
Voc+ 0.5
V
V
V
V
-50
28
50
25
V
mA
mA
100
50
0.8
mA
mA
VAC
181
181
rms
10
-100
I orms
Ptot
Tstg
R thSA
W
I;25
«::n
T
'J
1-
40
I:g
120
K/W
Operating range
Supply voltage
Tone frequency
Ambient temperature
VDC
tTl
Tamb
Characteristics
Tamb = -25°C to 85°C
Test conditions
I-25
~.1
Lower
limit B
1
15
25
85
1
typ
Upper
limit A
~HZ
°C
Current consumption
I Dc
VDC = 9 V to 25 V,
wlo load
1.5
1.8
mA
Switching threshold
Initial resistance
VOGON/OFF
RINI
8.6
4.7
9
6
V
kQ
Output-voltage swing
Tone frequency
tT 1
8
see characteristic,
3.5
figure 3
VDc -3.7
Io=± 10 mA
VDc =15 V, V32 =OV,
1.275
RT = 16 kQ
Voc=15 V, Cs =100 nF 5.6
1.31
VDc -3
1.700
2.125
V
kHz
7.5
1.38
9.4
1.45
Switching frequency
Tone frequency ratio
Temperature
coefficient of tone
freq uencies
92
Va
ts
tTllt12
TC f
8 x 10-4
Hz
K-l
SAE 0700
Characteristic curves
Current consumption versus
supply voltage VDC
without output load
Tone frequencies IT 1 and fT 2
versus resistance RT
kHz
10
rnA
3
\
fn
fTI
~
I
f Tl : fTI =1.31
.~-
f-
I-
~r
f-.f:!
\
"\r\
.~/
~
0.5
.il
1\
-..s.
-
II
0.2
oI
o
0.1
30 V
10
1
5
10
20
50
100kll
-RT
Switching frequency Is versus
capacitance C s
Hz
100
50
-~
&i
'\~
,
10
.,,"
5
,,"-"'\'\
--
&..
~~
i
~
1
10
100
5
1000nF
- Cs
93
94
8 Bit CMOS Analog-to-Digital Converters
with 8-Channel Multiplexers
Preliminary Data
SDA0808 A
SDA0808 B
DIP 28
The SDA 0808 A;B is a monolithic CMOS device with a single supply of 5 V DC, 8 bit analog to
digital converter, 8·channel analog multiplexer and microprocessor compatible control logic
and 8 bit data bus. It is a pin to pin compatible device to the data acquisition component ADC
0808/0809.
The SDA 0808 A;B has the method of successive approximation with a capacitor network as
the conversion technique. The converter features a temperature stabilized differential
comparator, a·channel multiplexer for a analog inputs and a sample & hold circuit. The device
needs no external offset or gain adjustments. Easy interfacing to microprocessors is provided
by 3 bit addresslatch, 8 bit data'outputlatch and a bit TRI STATE databus.
Features
• Resolution a bits
• Total unadjusted error ±
1/2 LSB
• No missing codes
• Conversion time 15/Ls
• Single supply 5 V DC
• a·channel multiplexer with latched control logic
• Easy interface to all microprocessors, or operates stand alone
• 0 V to 5 V analog input voltage range
• No offset or gain adjust required
• Latched TRI STATE output
~ Oututs meet TTL voltage level specifications
• CMOS low power consumption
• 2a pin P·DIP standard package
95
SDA0808A
SDA0808 B
Pin Designation
Pin No.
Function
Symbol
1 to 5
6
7
8
9
10
11
12
13
14 to 15
17 to 21
22
23 to 25
26 to 28
Analog inputs
Start of conversion
End of conversion
Digital output signal
Output enable
External clock input
Pos. supply voltage
Pos. reference voltage
Ground
Neg. reference voltage
Digital output signals
Address latch enable
Address inputs
Analog inputs
AIN3toAIN7
SOC
EOC
2- 5
OEN
ClK
VDD
REF(+)
GND
REF(-)
2- 8 t02- 1
ALE
ADD 2 to ADDO
AINOtoAIN2
Pin Configuration
(top view)
AIN 3
96
28
AIN 2
AIN4
2
27
AIN 1
AIN 5
3
26
AIN 0
AIN 6
4
25
ADDO
AIN 7
5
24
ADD 1
SOC
6
23
ADD2
EOC
7
22
ALE
2- 5
8
21
2- 1 (MSB)
OEN
9
20
2-2
ClK
10
19
2- 3
VDD
11
18
2-4
REF(+)
12
17
2- 8 (lSB)
GND
13
16
REF(-)
2-7
14
15
2- 6
SDA0808A
SDA0808 B
Functional Description
The Converter
The converter is partitioned into 3 major sections: An approx. 50 pF capacitor network as a
sample & hold circut, the successive approximation register and the comparator. The
capacitor network includes a correction, so that the first output transition occurs when the
analog signal has reached + 1/2 LSB.
The AID converter's successive approximation register (SAR) is reset on the positive edge of
the start of the conversion (SOC) pulse. The conversion is begun after the falling edge of the
start of conversion pulse with the next rising edge of the external clock signal. A conversion
in progress will be interrupted by a new start of conversion pulse.
The logical end of conversion output (EOC) will go low after the rising edge of the start of
conversion pulse. It is set to logical one with the first rising edge of the external clk after the
internal latch pulse. The autozeroed, high resolution, low drift comparator makes the AID
converter extremely insensitive to temperature errors.
AID Converter Timing
After a conversion has been started, the analog voltage at the selected input channel is
sampled for 10 external clock cycles which will then be held at the sampled level for the rest
of the conversion time. The external analog source must be strong enough to source the
current in order to load the sample & hold capacitance, being approximately 50 pF, within
those 10 clock cycles.
Conversion of the sampled analog voltage takes place between the 11th and 18th clock cycle
after sampling has been completed. In the 19th clock cycle the converted result is moved to
the output data latch. With the leading edge of the 20th clock cycle the end of conversion
signal is set.
97
SDA0808A
SDA0808 B
Multiplexer
The device provides eight multiplexed analog input channels. A particular input channel is
selected by using the address decoder.
Table I shows the input states for the address lines to select any channel. The address is
latched on the low to high transition of the ALE signal.
Table I:
Address lines
Selected Analog Channel
AD2
AD 1
ADO
AIN
L
L
L
A!NO
L
L
H
AIN 1
L
H
L
AIN2
L
H
H
AIN3
H
L
L
AIN4
H
L
H
AIN5
H
H
L
AIN6
H
H
H
AIN7
Absolute maximum ratings
Supply voltage (see Note 1)
Input voltage range
Continuous total power dissipation
(at or below 25°C free-air temperature range)
Operating free-air temperature range
SDA0808A
SDA0808S
Storage temperature range
TA
TA
Note 1: All voltage values are with respect to network ground terminal
98
Lower
limitS
Upper
limit A
-0.3
6.5
Vee
-40
-40
-65
+
0.3
V
V
875
mW
85
125
150
°C
°C
°C
SDA 0808 A
SDA0808 B
Recommended operating conditions
Vee = 5V; TA= 25°C
Supply voltage
Positive reference voltage
Negative reference voltage
Differential reference voltage
Start pulse duration
Address load control pulse width
Address setup time
Address hold time
Clock frequency
test condo
min
typ
max
unit
Vcc
VAEF+ (see Note 3)
VAEF
SDA0808A
SDA0808 B
,:~,
Clock
Start Conversion
50%
,
j,'~--------------
..... ' tw(S)
,
Address Latch
Enable
,, ''
:+-:---+, tw(ALE)
~Address stable
Address
50%~50%
tsu i...........; ;;'th~;;""------------,......-..,..-
I
,
Analog Input
I
X
.-----------
Analog Value
4
!X
i
Input Stable
----:.::::::~~I
Multiplex Output
I
(Internal)
_ _ _'....:
Analog Value
i!
~",5_0_0;'_o___
,,
,
End of Conversion
,
,,,
'+-: td(EOC) -+:
:4
X, . - - - - - - - - - -
'---------------------
y 50%
:
teenv - - - - - - - -....
.:
_______________
-J , ,
50%
Output Enable
ten
Latch Outputs
HIZState
102
+I'....
':
,
+: .....
: tdis
90%(
~
10% "'-_ _ 10%
J
SDA2008
Infrared Remote Control Transmitter
DIP 18
The SDA 2008 IC represents a follow-on development of the infrared transmitter IC SAB 3210.
It includes a disconnectable 8-stage divider, thus enabling the oscillator to operate up to
500 kHz with a ceramic oscillator instead of an LC circuit.
Features
•
•
Complete security of the keyboard against operating errors
Instruction extension up to 60 instructions is possible by using diodes
and by means of a shift key (keyboard changeover)
•
•
Start bit programmable by external voltage
Wide supply voltage range between 5 V and 16 V
•
Low current consumption, typically 3 mAo The battery can be switched off
by an external transistor
•
No external colum n resistors necessary
Maximum ratings
all voltages referred to Voo
=
Supply voltage
Input voltage
Power dissipation per output
Total power dissipation
Storage temperature range
0V
Vss
Vi
Pq
Ptot
Tstg
18
18
100
500
-40 to 125
V
V
mW
mW
°C
Operating range
referred to Voo = 0 V
Supply voltage
Supply voltage 1)
Ambient temperature
Vss 1
Vss 1
TA
15 to 16
5.5 to 16
to 70
a
I
~C
1) Instruction extension with diodes
103
SDA2008
Characteristics
all voltages referred to Voo
min
Supply current
(outputs not connected)
Leakage current, total current
of outputs Ca, Cb, Cc, Cd, ETA, IRA
(refer to test circuit)
Is
typ
max
3
7
rnA
!-LA
12,3,4,5.7,8
Inputs
Oscillator input ClK I
Operating frequency
with prescaler
Operating frequency for externai ciock
with disconnected prescaler
f17
T17
1160
I ~u
1~60 1kHz
I KHz
I
(U
IRA remote control signal output
H output voltage
(refer to test circuit)
1=4 rnA; Vss = V
H resistor with respect to Vss
6
VqH8
Vss-5
V
RqH8
100
Q
ETA switch-on transistor output
H output current
Vq7 =Vss -4 V
104
l qH7
1100
110000 1!-LA
SDA2008
Row input 1 to 8 (internal pull-high resistors)
Instructions can be transmitted by connecting the respective row input with the corresponding column output (refer to instruction set). Operating errors, such as connecting
more than one respective row and column are recognized and transmission is interrupted.
Only exception: instruction extension with row 8 (see input, keyboard).
The connection can include as max. resistance a silicon diode junction in forward direction
and a 100 Q resistance in series. Minimum resistance is zero.
ETA input
The ETA input is connected to the supply voltage via the base-emitter diode of the NPN
switching transistor for normal transmitting operations.
PPIN program input
If the PPIN input is joined with the corresponding column output or with the IRA output
(in this case = 33 kQ $ R1RA $47 kCl) the output mode can be changed in accordance with
the table "PPIN connections".
Example
v.
,--- S
33 kO $ RIRA $ 47 kO
R1R2 $100 Q
01, 02 = \.'1 $ 0-8 V atIF = 0.1 rnA
and hmln
RIRA
CQ
2
L
IRA 8
SDA 2008
PPIN
/2
18
~17 D2
~
D1
105
SDA2008
Description of function
The SDA 2008 Ie operates as a transmitter for the infrared remote control system IR 60.
The PMOS circuit contains a control output for an NPN transistor which deactivates the
supply voltage if the keyboard is not activated (Le. no row is in "low" state).
Input, keyboard
The transmitter contains an input matrix of 8 rows and 4 columns. In order to input an
instruction, a row must be connected to a column. Thus, the transmitter is switched on and
the appropriate instruction is sent. Without further measures it is possible to issue up to
32 instructions. The instruction set can be extended up to 60 either with the aid of additional diodes (for this purpose 2 diodes are required for each 4 additional instructions)
or up to 62 instructions with a shift key. In both cases the additional connection (diodes to
row 8 or shift key) is necessary prior to issuing the first instruction - after that the originally
allocated instruction is sent independent of the additional connection.
As a fifth matrix column, - Vs can be used to input the instructions 40 to 47 (without
external diode connection using only one key, each).
Operating error
The circuit includes a security lock against multi-operations (several keys are depressed
simultaneously). An exception is the double operation inside a column with one of the
rows 1 to 7 and row 8, since this combination is used in order to extend the instruction set
with the aid of diodes. After transmission of the first infrared instruction after the startbit,
this double operation is locked as well.
Start instruction, end instruction
After the switch-on, the instruction No. 62 is issued as start instruction thus indicating to
the receiver the start of the instruction transmission.
In case of an operating error, this instruction is generated by the security lock. If the key
or keys are released, the selected instruction is sent once more (depending upon the
exact instant of release) while the instruction No. 62 is sent once as stop before the supply
voltage is switched off. Safety measures prevent to change an instruction to any other than
instruction No. 62.
Output
The transmitter encodes the input in bi-phase code (refer to timing diagram). Prior to the
6 information bits, a presignal and a startbit which can be selected via PPIN, are sent. The
presignal enables proper control of the preamplifier on the receiver side, whereas the
startbit is used for receiver discrimination. Thus it is possible to control a TV set and a
radio in one room independently of each other with the same remote control system.
The output signal is carried at 1/16 of the clock frequency (fcLK,/16) and a pulse duty
factor of 1: 4. With the help of corresponding wiring of the program input PPIN, the carrier
can be switched off. Thus any other external carrier can be used.
106
SDA2008
Instruction interval
The interval between two given instructions (except the start instruction) is approximately
12 times the instruction length (incl. presignal) or 35536 ClKI clocks, respectively. This
interval can be reduced to 30976 ClKI clocks in order to obtain diminished instruction
intervals at lower clock frequencies.
Operation at low clock frequency
The prescaler (divide by 8) can be switched off. Thus, operation is possible at a clock
frequency of approx. 500 kHz or 62.5 kHz, as required. The prescaler can only be switched
off if - at low resistance - the IRA output is not forced to low (by means of a base-emitter
space), e.g. in the case of wiring for front-end control.
Operation without switching transistor
During operations with a fixed supply voltage (ETA = low), the columns a to d are periodically
interrogated (H pulse) in the normal sequence (as if an instruction is emitted) in order to
permit an external synchronization.
After the supply voltage began to rise at 0 V, the flow of control is brought into a definite
state and starts column interrogation. After having recognized a row in the "low" state, the
flow of control is reset - then the flow corresponds until disconnection to the flow present
during battery operations. After transmission has ended, the flow of control continues column
interrogation, however, without any further output to IRA.
MultitransmiHer operation
Without great increase in external circuitry, it is possible to cascade two SDA 2008 ICs so
that they can be multiplexed to give out the instructions. For this purpose, the automatic
resetting of the flow control and the instruction register are utilized which become effective
as soon as both columns a and b are on high.
107
SDA2008
PPIN connections
Connect with:
Function
Column a
Shift into second instruction group
(bitF="1")
Shortened instruction intervai
Startbit = "0"
No carrier of the IRA signal
Bridging the prescaler
Column b
Column c
Column d
IRA
(In the case of combinations of these functions, decoupling with diodes according to figure
PPIN connection is necessary).
ETA connection
ETA = VDD
ETA to base of the
voltage commutation
transistor
108
Operation at constant supply voltage.
If no row is set to "low", IRA is without output, however permanent
column interrogation.
Normal battery operation including disconnection of the supply
voltage after the end instruction at open row combination.
SDA2008
Instroction set
No diodes at row 8
unshifted
No diodes at row 8
shifted
With diodes at row 8
unsh ifted/sh ifted
Instr.
No.
Code
FED CSA
Key
Instr.
No.
Code
FED CSA
Instr.
No.
Code
FED CSA
Key
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
000
000
000
000
000
000
000
000
001
001
001
001
001
001
001
001
010
010
010
010
010
010
010
010
011
011
011
011
011
011
011
011
la
lb
lc
ld
2a
2b
2c
2d
3a
3b
3c
3d
4a
4b
4c
4d
5a
5b
5c
5d
6a
6b
6c
6d
7a
7b
7c
7d
8a
8b
8c
8d
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
62
100
100
100
100
100
100
100
100
101
101
101
101
101
101
101
101
110
110
110
110
110
110
110
110
111
111
111
111
111
111
111
111
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
100
100
100
100
100
100
100
100
101
101
101
101
101
101
101
101
110
110
110
110
110
110
110
110
111
111
111
111
81a
81b
81c
81d
82a
82b
82c
82d
83a
83b
83c
83d
84a
84b
84c
84d
85a
85b
85c
85d
86a
86b
86c
86d
87a
87b
87c
87d
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
~~
g}
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
end instructions
Special group
unshifted/shifted
Instr.
No.
Code
FED CSA
Key
40
41
42
43
44
45
46
47
101
101
101
101
101
101
101
101
lL
2L
3L
4L
5L
6L
7L
8L
000
001
010
011
100
101
110
111
109
SDA2008
Instruction interval (prescaler switched on)
Interval
Interval in
elKI clocks
Interval in ms
felKI = 500 kHz
Normal
65536
approx.131
Reduced
30976
approx.62
PPIN connected to
column b
X
Definition of the instruction interval
~
1 4 - - - - - Instruction Interval
Hints for special functions
c:
0
e
~
"E0 '"
Q)
~~
o Q)
.s:as
Q) '"
"0'"
c:
0
·iii
u
o0
.-
E"O
~
c: 0
Q).-
,"0
.~ Q)
E:O
'"
as
c: U
...
"E
as
.E
c: _
==
0
0
0>.=as
~
"e
oQi
Q;j::
-c: ...
as
0 ....
~j::
1-«
E"O
Q) 0
a:E
Start bit changeover
X
X
X
X
Shift into second group
X
X
X
X
Diode matrix
X
X
X
X
Special instruction group
X
X
X
X
No carrier
X
X
Bridged prescaler
X
... ....
Q)
Shortened instruction interval
~u.
X
.0
>Q)
...
.l<
i
Q)
c.
>-
l-
Q)
:0
as
EEE
as0>0
110
'E"
o u
Q)
0.2
Q) 0
EE
.- Q)
as
0>
j::
I- ...
X
X
X
X
X
X
X
X
X
X
X
.e:u c:
_0
·i
.-
X
X
X
Q)
...J ...
X
X
~
"'"6,E
-0
X
No debounce delay
Special connection
e
... c:
SDA2008
Pin description
Pin
Function
1
Vss. +supply voltage
Column a
Column b
Column c
Columnd
VDD • -supply voltage
ETA (switch-on transistor output)
IRA (infrared output)
Row 1
Row 2
Row 3
Row 4
Row 5
Row 6
Row 7
Row 8
ClKI (oscillator input)
PPIN (programming input)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Oscillator connection
2)
1)
Cc
ClKI
SDA 2008
17
ClKI ~1:..-7_ _~
SDA 2008
Vss
Cc ;:: 10nF
111
SDA2008
Leakage current, total current (test circuit)
1
-2
>-- 3
>-- 4
>--
5
18
SDA 2008
'---- - 6
>--
¢r
1 ....
I~ -1~A t
Vq =-10V
t
17
16
15
14
13
12
11
7
8
'-9__________1~O~
'-_-______
~
_
___..J
TA = 25°(
IRA remote control signal output (test circuit)
~6V
V<5V
Vss
SDA 2008
VOD
6
OV
112
8
IRA
t
1= 4mA
SDA2008
Biphase coding from instruction 011001
Isignal
Pre-
I
I
:
Start Bitl
I
11
"1"
Bit A
"0"
Bit B
"1 "
Bit c
"1"
Bit 0
"0"
Bit E
"0"
Bit F
"1"
I
H
IRA
21
IRA
H
L
11~
Def: for ·0" and ·1"
21~
~
1) with Carrier
2) without Carrier
"0"
Exact Pulse Train of a Burst for 1):
(withT=~
fCLK! '
or T=_2_1
fCLK!
113
SDA2008
Actuating a key (e.g. 1a), fClKI = 500 kHz
H
Row 1 l
t
""Jnll-------......Jnl-....--------Bouncing
ETA
HJUlj
L
Column a:
I
I
_--.J!'-______. . . Jn
L _ _ _ _ _ _ _ _ __
I
IRA
H
L
I
I
Presignal
'..nn
-...;..1_____---J·IIIUJUlIIUIUIUIUIIL..__
Start Bit
:
I
I
o
fClKI
= 500 kHz
~~K~
I 1-1- - - - - - - , 1
H --L
Column a: __
Ii
L-
jL-_______1WL---------Instruction No. 0
I
i
End Instruction No. 62
m mmmmmmm I I
m m1m mn
L -.-----lIL.JIUIUIUIUIUIUI~ ~1L.JIUlIiUIUIUIUI'r-H
:
:..
I
114
30
-tims
I~II~
Row 1
IRA
I
I
20
10
Releasing a key (1a),
ETA
Start Instruction No. 62
1m nmmmmm
1
131 ms
.
t
:
-II
,
10ms
.:
I
I
SDA2008
Instruction interval,
r
felKI
= 500 kHz
Actuating a Key
o 1~
_____2~~____~5~_______7~(__~
I
I
Column
Interrogation
LH
IRA
[SBJ_sB-'-_---"-rx1~_----l
1 - ._
.......
PPIN at IRA (bridged prescaler)
o~
u' 1><1
125
150
felKI
=
62.5 kHz
175
200
~~I------~I------~I------~I~
---- t/rns
300
____~_
~'~
i
InterColumn
rogation
IRA
- - - Urns
200
175
I
i
H
I
L
I i--______---L.!=IjI_SB.....L____---"V\!'--''--__--I
r::1
1":"'71
PPIN at column b (shortened instruction interval)
felKI
= 500 kHz
--- Urns
I
I
o ~------2L~------5LP------7L(------10LIO------1~L5----Column
Interrogation LH
IRA
IXl
______--'rxl
.......
_----"R_SB
______
1-.
S8: -Instruction No. 62
115
SDA2008
PPIN connection
Shiff
Interval
Start Bit
(artier
DeCOuP,~ng Diodes
....
a.-
"
J
-v
....
v
....
Prescaler
a.-
18
PPIN
2 CCl
IRA ~~----
3 (b
4 (c
5 Cd
SDA 2008
9 R1
10 R2
11 R3
7
lA
"Do
ETA
22k)l
12 R4
13 R5
14 R6
15 R7
16 R8
1
+Vs~
116
. ClKI
~O~
SDA2008
Extension for 60 instructions with additional diodes
Quiescent Level
High
~
r---
4 Columns, Quiescent Level Low
"iii
c:
0
~ ~ ~
"
0
a: ..:a:
o
co
....
87
86
~ ~ ~
VI VI
~
~
~
6
85
VI
84
4
83
3
82
2
81
~
~
VI
VI
../1
../1
../1
../1
~
5
~
~
~
../~
~
../1
/1
../1
/1
../~
~
../]
/[
Vi
../1
../1
../1
../1
Vt
~
~
~
~
~
~
~
~
~
VI
VI
VI
Vi VI
../1
../1
../1
VI ~
17
\7
lz
17
7
~ i7
lz
~
L
co
0
0
N
j
;$
«
Cl
V1
L~
l
L~
~ ~
VI Vi
i>
L---
117
SDA2008
-Vs as fifth matrix column
2 Co
3 Cb
4 Cc
5 Cd
Instruction
No;
/
..,
SDA 2008
9 R1
41 -+~
__+-~~__~-+~__+-~____10~ R2
42-+~~~-+__r-~-+~~~-+____~
11 R3
12
43-+~~~-+__r-~-+~~~-+____~
R4
13
44-+~~1-~__~~-+~~4-~____~
RS
14 R6
45-+~__+-~-+~~1-~~~~__~
15
46-+~~~-+__r-~-+~~~-+____~
R7
47-+~~~~__r-~-+~~4--+____~
16 R8
Special Instruction Group
118
SDA2008
Application circuit
Be 238
I
ETA
2 (Cl
22kSl
6
Iioo
3 (b
4 (,
1)
5 [~
-r-
IRA 8
I
9VI
I
..L.
2200~F
B(338
SDA 2008
+
9 R1
10 R2
11 R3
12 R4
13 RS
14 R6
15 R7
Vss
1
1) Shift key
2) Connection for shortened instruction interval
3) Start bit changeover
If only one of these three possibilities is used, no diode is required.
119
)
120
Application-Oriented Single-Chip Microcomputers
SDA2040
SDA2060
SDA2080
DIP 40
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Upgraded 8-bit CPU as compared to SAB 8051
+5V supply voltage
On-chip 4 Kl6Kl8Kbyte ROM
128 byte internal RAM
64 Kbyte RAM can be connected externally
(internal and external RAM can be used simultaneously)
1 J.ls internal cycle with 12 MHz clock frequency
34 bidirectional I/O ports:
- two 8-bit ports
- one 8-bit multifunction port
- one 8-bit port with 15 mA current sink per output
(suited for direct LED MUX control)
One serial 12C bus interface (2-bit port open drain) suited for multi-master operation
Input for direct modulated digital infrared signal processing
(optimum carrier frequency is approx. 30 kHz)
Powerful interrupt structure with 5 sources and 2 hierarchylevels
Instruction set downward-compatible with existing programs for SDA 2010/2030/2110
Power-down mode with internal RAM data retention and reduced power consumption
Two 16-bit timers/counters
Instructions for direct multiplication or division, execution time only 4 J.ls
Boolean processor implementable for pure controlling tasks
Circuit description
The three components SDA 2040/2060/2080 are identical with respect to pin configuration
and functions, they differ, however, in the size of the program memory.
This enables an individual matching to system requirements.
Software development is supported in two ways:
1) Replacement of functions with SDA 2082 and external program memory.
Note: Usability of ports PO and P2 is limited.
2) Replacement of functions and emulation with bond out chip SDA 3080 and piggyback.
A Siemens microcomputer development system (e.g. SME 232) can be used for SDA2040/60/80
program development and system testing. Powerful edit, assembler and debug programs
are available.
121
SDA2040
SDA2060
SDA2080
The SDA 2040/60/80, a successor type to the SAB 8051, belongs to the family of single-chip
microcomputers, for which the operational emphasis is no longer placed on pure numeric
control functions.
The SDA 2040/60/80, specially developed for entertainment electronic applications, can be
recommended especially for those applications, where lowest component costs and high
quantities are an essential requirement.
Architecture and instruction set are based on the SAB 8051 microcomputer. In the same
manner as the SAB 8051, the SDA 2040/60/80 possesses a number of features that facilitate
programming:
- variable allocation of RAM
- unrestricted stack location in RAM
- 4 register
banks
6. •• _ _
:_.L __
_ _ _ _ :_1
-
~...,t::vli:1I
Lt _ _ _ _ _
lUI I\.iLlUI I I
t::yl~lt:1
- memory mapped I/O
Individually addressable bits and a Boolean processor enable the programmer to improve
software performance. Numeric problems can be solved in binary or in BCD arithmetic.
The large number of instructions for processing binary functions also plays a part in increasing
the performance of the computer as a controller. All of these features, when used appropriately, lead to a reduction of peripheral hardware, to a simplification of the software, and
thus, to a reduction of development and component cost.
The SDA 2040/60/80 contains a 4K16K18Kbyte program memory (ROM), an internal
128 byte RAM (an additional 64 Kbyte can be added externally, ref. SDA 2082 application
example), two 16-bit timers/counters, a nested interrupt structure with two priority levels,
and an integrated oscillator. Additionally, the computer can address 64 Kbyte of external
data memory. The 34 digital I/O ports comprise four 8-bit ports and a serial interface with
data and clock lines. The serial I/O interface fully complies with the FC multimaster protocol.
The IR input P3.0 can process modulated signals with a carrier frequency of approx. 30 kHz.
It contains a digital demodulator for deriving the envelope curve of modulated and inverted
digital signals. As the digital demodulator is software enabled and disabled, it is also possible
to use the IR port as a normal digital, quasi-bidirectional I/O port. The multifunction port P3
comprises two interrupt inputs and two counter inputs.
The instruction set, consisting of 49 one-byte, 46 two-byte, and 16 three-byte instructions,
ensures efficient utilization of program memory. If a 12 MHz crystal is used, the execution
time for the instructions is either 1 J.Ls or 2 J.Ls. The execution time for the very complex
instructions for "multiply" and "divide" is only 4 J.Ls. Information about the number of bytes
and the execution time can be found in the instruction set summary for the SDA 2040/60/80.
Maximum ratings
Voltage between any pin and ground
Total power dissipation
Storage temperature range
V
Ptot
Tstg
-0.5 to 7
2
-40 to 125
V
W
5 ±10%
V
o to 70
°C
°C
Operating range
Supply voltage
Ambient temperature
122
vee
TA
SDA2040
SDA2060
SDA2080
DC characteristics
TA =Oto70°C; Vcc =5V±10%; Vss=OV
L input voltage
(aliinputsexceptXTAL2,P4)
L input voltage (XTAL 2)
L input voltage (P 4)
H input voltage
(except XTAL 2, RSTIVpo, P 4)
H input voltage (XTAL 2)
H input voltage (RST)
H input voltage (Vpo)
H input voltage (P 4)
L output voltage (port 0)
L output voltage (port 0)
L output voltage (ports 1, 2 and 3)
L output voltage (ALE)
L output voltage (port1)
L output voltage (port 4)
H output voltage (ports 1, 2 and 3)
H output voltage (port 0 and ALE)
Current of internal pull-up resistance
(P 1, P2, P3)
Leakage current of outputs
Current consumption
(all outputs disconnected)
Current consumption (power-down mode)
Capacitance of inputs/outputs
Test conditions
min
max
iii L1
iii L2
-0.5
-0.5
-0.5
0.8
0.6
1.5
V
V
V
iii H
iii H1
iii H2
iii H3
iii H4
2.0
2.5
2.5
4.5
3.0
Vcc+ 0.5
Vcc+ 0.5
Vcc+ 0.5
5.5
Vcc+0.5
0.45
1.0
0.45
0.45
1.0
0.4
V
V
V
V
V
V
V
V
V
V
V
V
V
!-LA
± 10
!-LA
rnA
\ilL
Vq L
Vq L1
Vq L2
Vq L2
Vq L3
Vq L4
Vq H
Vq H1
Vcc- O
ILQ
IqL =3.2A
I qL1 = 15 rnA
IqL2 ~ 1.6 rnA
I qL2 -3.2 rnA
I qL3 =7.5 rnA
IqL4 -3.0 rnA
IqH --80 !-LA
I qH1 =-400 !-LA
0.45 V = \liN = Vcc
hQ 1
0.45 V =
2.4
2.4
-800
\liN - Vcc
Icc
I po
CIQ
150
20
10
Vcc-OV
'c-1 MHz
rnA
pF
AC characteristics
TA =Oto 70°C; Vcc=5 V ± 10%; Vss =0 V
CL - 100 pF (for port 0, and ALE output)
CL = 80 pF (for all other outputs)
Maximum ratings
Cycle time of oscillator
Min. cycle period
ALE pulse width
RD pulse width
WR pulse width
LCL
y
HLL
LRH
LWH
Variable clock
1/tCLCL =1.2-12 MHz
12 MHz clock
min
max
min
83
12 tCLCL
2 tCLCL -40
6 tCLCL -100
6 tCLCL -100
833.3
12 tCLCL
83
1000
127
400
400
max
ns
ns
ns
ns
ns
123
SDA2040
SDA2060
SDA2080
Pin configuration
Pl.0
40 Vee
P 1.1
2
39 P 0.0
P 1.2
3
38 P 0.1
P1.3
4
37 P 0.2
Pl.4
5
36 P 0.3
Pl.5
6
35 P 0.4
P1.6
7
34 PO.5
P1.7
8
33 P 0.6
9
32 PO.7
RSTIV PD
IR P3.0 10
P3.1 11
30 P2.7
P3.2 12
29 P2.6
iNTl P 3.3 13
28 P2.5
INTO
To
124
31 ALE
P3.4 14
27 P 2.4
f1 P3.5 15
26 P2.3
WR
P 3.6 16
25 P 2.2
RD
P3.7 17
24 P 2.1
XTAL 2 18
23 P 2.0
XTAL 1 19
22 P4.1
SCL
Vss 20
21 P4.0
SDA
SDA2040
SDA2060
SDA2080
Pin description
Symbol
Function
Vss
GNDOV
Vee
+5V
Port 0
Bidirectional 8-bit port with 3.2 rnA current sink at 0.45 V and 15 rnA current
sink at 1.0 V for direct LED control (static or MUX operation).
Port 1
Bidirectional 8-bit port with 1.6 rnA current sink at 0.45 Vand 7.5 rnA current
sink at 1.0 V for direct LED display.
Port 2
Bidirectional 8-bit port with 1.6 rnA current sink at 0.45 V.
Port 3
Bidirectional 8-bit port with 1.6 rnA current sink at 0.45 V. Also includes
the inputs of the interrupt and timer controls. For a program-controlled
enabling of the function, the corresponding latch must be active high.
The allocation of the special function registers is as follows:
- 1R
- INT 0
- INT 1
- TO
-T1
- WR
- RD
(P 3.0) Input of the digital demodulator to generate an envelope
curve of a standard modulated IR signal (inverted)
(P 3.2) Input for interrupt 0 or for enabling/disabling the counter
inputT 0
(P 3.3) Input for interrupt 1 or for enabling/disabling the counter
input T 1
(P 3.4) Counter input T 0
(P 3.5) Counter input T 1
(P 3.6) Write strobe for external data memory (RAM)
(P 3.7) Read strobe for external data memory
Port 4
Bidirectional 2-bit port with open drain outputs, with 3 rnA current sink at 0.4 V.
Port 2 contains a bidirectional serial interface with DATA (SDA, pin 21)
and CLOCK line (SCL, pin 22). The serial interface fully meets the requirements of the 12C bus protocol.
RSTIVPD
At a connected supply voltage Vee = 5 V, an edge transition from low to high
(at approximately 3 V) resets the SDA 2040/60/80, i.e. the user program
starts with address O.
When VPD = high (approx. +5V), a drop in Vee triggers the processor's
transition Into the power-down mode. In this case, a current supply of max.
20 rnA is provided to the RAM via pin RSTIVPD ' In the case VPD = 0 Vand
Vee = 5 V, the RAM is supplied via Vee.
ALE
Address Latch Enable output for controlling external memory access during
normal operation.
XTAL1
Oscillator input for crystal operation. For external clock source connect
to Vss.
XTAL2
Oscillator output; required when crystal is used. Input during external clock
supply.
125
SDA2040
SDA2060
SDA2080
SDA 2040/SDA 2060/SDA 2080 instruction set
Arithmetic operations
Mnemonic
Description
Bytes
Cycles
ADDA, Rn
ADD A, direct
ADDA,@Ri
ADD A, # data
ADDCA, Rn
ADDC A, direct
ADDCA.@Ri
ADDC C. # data
Add register to Accumulator
Add direct byte to Accumulator
Add indirect RAM to Accumulator
Add immediate data to Accumulator
Add register to Accumulator with Carry flag
Add direct byte to A with Carry flag
Add indirect RAM to A with Carry flag
Add immediate data to A with Carry flag
~
Ilhtr!!:to,..t r.o."io+or
\A,ifh Rnrrnul
_ .........................
.._ . frnrn
.......... ,A.........
__ .0 ........
Subtract direct byte from A with Borrow
Subtract indirect RAM from A with Borrow
Subtract immediate data from A with Borrow
Increment Accumulator
Increment register
Increment direct byte
Increment indirect RAM
Decrement Accumulator
Decrement register
Decrement direct byte
Decrement indirect RAM
Increment Data Pointer
Multiply A&B
DivideA&B
Decimal Adjust Accumulator
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
4
1
Q.I n:Ul A
---_.",.,
r'n
SUBB A. direct
SUBBA.@Ri
SUBB A. # data
INCA
INCRn
INC direct
INC@Ri
DEC A
DECRn
DEC direct
DEC@ Ri
INC DPTR
MULAB
DIVAB
DAA
126
~._
SDA2040
SDA2060
SDA2080
SOA 2040/S0A 2060/S0A 2080 instruction set
Logical operations
Mnemonic
Description
ANLA, Rn
ANL A, direct
ANLA,@ Ri
ANLA, # data
ANL direct, A
ANL direct, # data
ORLA, Rn
ORL A, direct
ORLA,@Ri
ORLA, # data
ORL direct, A
ORL direct, # data
XRLA, Rn
XRL A, direct
XRLA,@ Ri
XRLA, # data
XRL direct, A
XRL direct, # data
CRLA
CPLA
RLA
RLCA
RRA
RRCA
SWAP A
AND register to Accumulator
AND direct byte to Accumulator
AND indirect RAM to Accumulator
AND immediate data to Accumulator
AND Accumulator to direct byte
AND immediate data to direct byte
OR register to Accumulator
OR direct byte to Accumulator
OR indirect RAM to Accumulator
OR immediate data to Accumulator
OR Accumulator to direct byte
OR immediate data to direct byte
Exclusive-OR register to Accumulator
Exclusive-OR direct byte to Accumulator
Exclusive-OR indirect RAM to Accumulator
Exclusive-OR immediate data to Accumulator
Exclusive-OR Accumulatur to direct byte
Exclusive-OR immediate data to direct byte
Clear Accumulator
Complement Accumulator
Rotate Accumulator left
Rotate A left thorugh the Carry flag
Rotate Accumulator right
Rotate A right through the Carry flag
Swap nibbles within the Accumulator
Bytes
Cycles
1
1
1
1
1
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
1
1
1
1
1
2
1
1
1
1
1
2
2
3
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
127
SDA2040
SDA2060
SDA2080
SDA 2040/SDA 2060/SDA 2080 instruction set
Data transfer operations
Mnemonic
Description
MOVA, Rn
MOV A, direct
MOVA,@Ri
MOVA, # data
MOVRn,A
MOV Rn, direct
MOV Rn, # data
MOV direct, A
MOV direct, Rn
MOV direct, direct
MOV direct, @ Ri
MOV direct, # data
MOV@ Ri,A
MOV @ Ri, direct
MOV @ Ri, # data
MOV DPTR, # data 16
MOVC A@ A + DPTR
MOVCA@A+PC
MOVXA,@ Ri
MOVX A, @ DPTR
MOVX@Ri,A
MOVX @ DPTR, A
PUSH direct
POP direct
XCH A, Rn
XCH A, direct
XCHA,@Ri
XCHDA,@Ri
Move register to Accumulator
Move direct byte to Accumulator
Move indirect RAM to Accumulator
Move immediate data to Accumulator
Move Accumulator to register
Move direct byte to register
Move immediate data to register
Move Accumulator to direct byte
Move register to direct byte
Move direct byte to direct byte
Move indirect RAM to direct byte
Move immediate data to direct byte
Move Accumulator to indirect RAM
Move direct byte to indirect RAM
Move immediate data to indirect RAM
Load Data Pointer with a 16-bit constant
Move Code byte relative to DPTR to Accumulator
Move Code byte relative to PC to Accumulator
Move External RAM (8-bit addr) to Accumulator
Move External RAM (16-bit addr) to Accumulator
Move A to External RAM (8-bit addr)
Move A to External RAM (16-bit addr)
Push direct byte onto stack
Pop direct byte from stack
Exchange register with Accumulator
Exchange direct byte with Accumulator
Exchange indirect RAM with Accumulator
Exchange low-order digital indirect RAM with A
128
Bytes
Cycles
1
1
1
1
1
1
2
1
2
1
2
2
2
2
3
2
3
2
1
1
2
2
2
2
1
1
2
2
3
2
1
1
1
1
1
1
2
2
1
2
1
1
1
2
2
2
2
2
2
2
2
2
1
1
1
1
SDA2040
SDA2060
SDA2080
SDA 2040/SDA 2060/SDA 2080 instruction set
Boolean variable manipulation
Mnemonic
Description
CLRC
CLR bit
SETBC
SETB bit
CPLC
CPL bit
ANLC, bit
ANLC,Ibit
ORLC, bit
ORL C,Ibit
MOVC, bit
MOV bit,C
Clear Carry flag
Clear direct bit
Set Carry flag
Set direct bit
Complement Carry flag
Complement direct bit
AND direct bit to Carry flag
AND complement of direct bit to Carry
OR direct bit to Carry flag
OR complement of direct bit to Carry
Move direct bit to Carry flag
Move Carry flag to direct bit
Bytes
Cycles
1
1
1
1
1
1
1
2
1
2
1
2
2
2
2
2
2
2
2
2
2
2
1
2
129
SDA2040
SDA2060
SDA2080
SDA 2040/SDA 2060/SDA 2080 instruction set
Program control operations
Mnemonic
Description
ACALL addr 11
LCALL addr 16
RET
RETI
AJMPaddr 11
LJMPaddr 16
SJMP rei
JMP@ A+DPTR
JZ rei
JNZ rei
JC rei
JNC rei
JB bit, rei
JNB bit, rei
JBC bit, rei
CJNE A, direct, rei
CJNE A, # data, rei
CJNE Rn, # data, rei
CJNE @ Ri, # data, rei
DJNZRn, rei
DJNZ direct, rei
NOP
Absolute subroutine call
Long subroutine call
Return from subroutine
Return from interrupt
Absolute jump
Long jump
Short jump (relative addr)
Jump indirect relative to the DPTR
Jump if Accumulator is zero
Jump if Accumulator is not zero
Jump if Carry flag is set
Jump if Carry flag is not set
Jump if direct bit set
Jump if direct bit not set
Jump if direct bit is set and clear bit
Compare direct to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to register and jump if not equal
Compare immediate to indirect and jump if not equal
Decrement direct and jump if not zero
Decrement direct and jump if not zero
No operation
Bytes
Cycles
2
2
2
2
2
2
2
2
2
3
1
1
2
3
2
1
2
2
2
2
3
3
3
3
3
3
3
2
3
1
2
2
2
2
2
2
2
2
2
2
2
2
2
1
Symbols and abbreviations
A
adr
CNT
DA
data
P
Pp
130
Accumulator
11-bit program memory address
Event counter
D/A converter indication
8-bit binary number
Mnemonic for "in page" operation
Port label (p = 0-3)
Rr
Sn
T
TO,T1
#
@
Register label (r=0-7)
S interface label (n = 0; 1)
Timer
Test 0, test 1
Refers to immediate data
Refers to indirect addressing
Application-Oriented Single-Chip Microcomputer
SDA2082
PLCC44
Features
• Upgraded 8-bit CPU as compared to SAB 8051
• +5 V supply voltage
• Program memory either 8 Kbyte internal ROM
or 64 Kbyte external ROM
• Data memory
128 byte internal RAM
64 Kbyte RAM can be connected externally
(internal and external RAM can be used simultaneously)
• 1 !-Is internal cycle with 12 MHz clock frequency
• 34 bidirectional 110 ports:
- two 8-bit ports
- one 8-bit multifunction port
- one 8-bit port with 15 mA current sink per output (suited for direct LED MUX control)
- one serial1 2C bus interface, suited for mUlti-master operation
• Input for direct modulated digital infrared signal processing
(optimum carrier frequency is approx. 30 kHz)
• Powerful interrupt structure with 5 sources and 2 hierarchy levels
• Instruction set downward-compatible with existing programs for SDA 2010/2030/2110
• Power-down mode with internal RAM data retention and reduced power consumption
• 16-bit timerlcounter operation
• Instructions for direct multiplication or division, execution time only 4 !-Is
• Boolean processor implementable for pure controlling tasks
Circuit description
A special application of the SDA 2082 lies in program development support for the
SDA 2040/60/80, the circuitry is shown in the application examples described in the
following.
A Siemens microcomputer development system (e.g. SME 232) can be used for SDA 2082
program developmentand system testing. Powerful edit, assembler and debug programs are
available.
An additional application of the SDA 2082 arises for individual control tasks and small
quantity series, for which the development of a user-specific program for SDA 2040/60/80
operation is too expensive. An external program memory can be put to good use in this case,
also offering short development times and more flexible possibilities for application.
Architecture and instruction set are based on the SAB 8051 microcomputer. In the same
manner as the SAB 8051, the SDA 2082 possesses a number of features that facilitate
programming:
-
variable allocation of RAM
unrestricted stack location in RAM
4 register banks
special function register
memory mapped 1/0
131
SDA2082
Individually addressable bits and a Boolean processor enable the programmer to improve
software performance. Numeric problems can be solved in binary or in BCD arithmetic.
The large number of instructions for processing biriaryfunctions also plays a part in increasing
the performance of the computer as a controller. All of these features, when used appropriately, lead to a reduction of peripheral hardware, to a simplification of the software, and
thus, to a reduction of development and component cost.
The SDA 2082 contains an on-chip 8 Kbyte program memory. Operation is optionally with
internal program memory (EA = high, pin 35) or external (EA = low, pin 35). Furthermore,
the SDA 2082 contains an internal 128 byte RAM (an additional 64 Kbyte can be added
externally, ref. application example), two 16-bit timers/counters, a nested interrupt structure
with tWo priority levels, and an integrated oscillator. Additionally, the computer can address
64 Kbyte of external data memory. The 34 digital I/O ports comprise four 8-bit ports and a
serial interface with data and clock lines. The serial I/O interface fully complies with the
12C multimaster protocol. The IR input P3.0 can process modulated signals with a carrier
frequency of approx. 30 kHz. It contains a digital demodulator for deriving the envelope
curve of modulated and inverted digital signals. As the digital demodulator is software enabled
and disabled, it is also possible to use the IR port as a normal digital, quasi-bidirectional
. I/O port. The multifunction port P3 comprises two interrupt inputs and two counter inputs.
The instruction set, consisting of 49 one-byte, 46 two-byte, and 16 three-byte instructions,
ensures efficient utilization of program memory. If a 12 MHz cyrstal is used, the execution
time for the instructions is either 1 J.1s or 2 J.1s. The execution time for the very complex
instructions for "multiply" and "divide" is only 4 J.1s. Information about the number of bytes
and the execution time can be found in the SDA 2082.instruction set summary.
Maximum ratings
Voltage between any pin and ground
Total power dissipation
Storage temperature range
V
Ptot
Tstg
-0.5 to 7
2
-40 to 125
W
Vee
TA
o to 70
5±10%
V
V
°C
Operating range
Supply voltage
Ambient temperature
132
°C
SDA2082
DC characteristics
TA =Oto 70°C; Vcc=5 V ±10%; Vss =0 V
L input voltage
(all inputs except XTAL 2, P 4)
L input voltage (XTAL 2)
L input voltage (P 4)
H input voltage
(except XTAL 2, AST/Vpo, P 4)
H input voltage (XTAL 2)
H input voltage (AST)
H input voltage (Vpo)
H input voltage (P 4)
L output voltage (port 0)
L output voltage (port 0)
L output voltage
(ports 1, 2, 3, PSEN and ALE)
L output voltage (port 1)
L output voltage (port 4)
H output voltage (ports 1, 2 and 3)
H output voltage (port 0, PSEN and ALE)
Current of internal pull-up resistance
(P 1, P 2, P 3)
Leakage current of outputs
Current consumption
(all outputs disconnected)
Current consumption (power-down mode)
Capacitance of inputs/outputs
Test conditions
min
max
VlL
Vlu
VI L2
-0.5
-0.5
-0.5
0.8
0.6
1.5
V
V
V
VlH
VI Hl
VI H2
VI H3
VI H4
VqL
VqL1
VqL2
2.0
2.5
2.5
4.5
3.0
Vcc+ 0.5
Vcc+ 0.5
Vcc+ 0.5
V
V
V
V
V
V
V
V
Vcc- O
5.5
Vcc+ 0.5
I qL -3.2 A
I qL1 -15mA
I qL2 -1.6 rnA
0.45
1.0
0.45
1.0
0.4
lLQ
I qL3 -7.5 rnA
I qL4 -3.0 rnA
IqH --60 f1A
Iq Hl = -400 f1A
0.45 V,;; VlN - Vcc
V
V
V
V
f1A
lLOl
0.45 V,;; YIN
± 10
f1A
rnA
VqL3
VqL4
VqH
VqH1
=
2.4
2.4
-800
Vcc
150
Icc
lpo
CIQ
Vcc - 0 V, Vpo = 5 V
fc -1 MHz
20
10
rnA
pF
AC characteristics
TA = 0 to 70°C; Vcc = 5 V ± 10%; Vss = 0 V
CL = 100 pF (for port 0, ALE and PSEN output)
CL = 80 pF (for all other outputs)
Maximum ratings
Cycle time of oscillator
Min. cycle period
ALE pulse width
AD pulse width
WA pulse width
LCL
y
HLL
LRH
LWH
Variable clock
1/tCLCL =1.2-12 MHz
12 MHz clock
min
max
min
83
12 tCLCL
2 tCLCL -40
6 tCLCL -100
6 tCLCL-100
633.3
12 tCLCL
83
1000
127
400
400
max
ns
ns
ns
ns
ns
133
SDA2082
Pin configuration
P1.4 P1.3 P1.2 P1.1 P1.0 N.C. Vee PO.O PO.l PO.2 PO.3
Pl.S
PO.4
Pl.6
PO.5
P1.7
PO.6
RSTIVPD
PO.?
In n':l n
11"\
r
EA
..J.V
N.C.
ALE
P 3.1
PSEN
INT 0 P3.2
P2.7
iNf1 P3.3
P2.6
TO PH
P2.S
P2.4
P3.6 P3.7 XTALXTAL Vss P4.0 P4.1 P2.0 P2.1 P2.2 P2.3
W 1m
134
2
1
SDA SCL
SDA2082
Pin description
Symbol
Vss
Vee
Port 0
Function
GNDOV
+5V
Bidirectional 8-bit port with open drain outputs with 3.2 rnA current sink at
0.45 V and 15 rnA current sink at 1.0 V for direct lED control (static or
MUX operation).
Port 1
Bidirectional 8-bit port with 1.6 rnA current sink at 0.45 V and 7.5 rnA current
sink at 1.0 V for direct lED display.
Port 2
Bidirectional 8-bit port with 1.6 rnA current sink at 0.45 V.
Port 3
Bidirectional 8-bit port with 1.6 rnA current sink at 0.45 V. Also includes
the inputs of the various interrupt and time controls. For a program-controlled
enabling of the function, the corresponding latch must be active high.
Allocation of the special function registers is as follows:
- IR
- INT 0
- INT 1
- TO
-IT
- WR
- RD
(P 3.0) Input of the digital demodulator to generate an envelope
curve of a standard modulated IR signal
(P 3.2) Input for interrupt 0 or for enabling/disabling the counter
inputT 0
(P 3.3) Input for interrupt 1 or for enabling/disabling the counter
input T 1
(P 3.4) Counter input T 0
(P 3.5) Counter input T 1
(P3.6) Write strobe for external data memory (RAM)
(P 3.7) Read strobe for external data memory
Port 4
Bidirectional 2-bit port with 3 rnA current sink at 0.4 V. Port 2 contains a
bidirectional, serial interface with DATA (SDA, pin 21) and CLOCK line
(SCl, pin 22). The serial interfaces fully meet the requirements of the
FC bus protocol.
RST/Vpo
At a connected supply voltage Vee = 5 V, an edge transition from low to high
(at approximately 3 V) resets the SDA 2082, i.e. the user program starts
with address O.
When Vpo = high (approx. +5V), a drop in Vee triggers the processor's
transition into the power-down mode. In this case, a current supply of max.
20 rnA is provided to the RAM via pin RSTlVpo• In the case Vpo = 0 V and
Vee = 5 V, the RAM is supplied via Vee.
ALE
Address latch Enable output for controlling external memory access during
normal operation.
XTAl1
Oscillator input. Crystal or external source can be used
XTAl2
Oscillator output; required when
PSEN
EA
Program Store Enable output fo'r external memory access
~'rystal
is used
External Access input; selects programm memory operating mode
EA high means internal program memory (8 Kbytes),
EA low means external program memory (max. 64 Kbytes)
135
~
>
'C
+5V
l
=t-
+5V
o
=k10~F
:s
~
10
Reset
I P4.0 (SOA)
• P4.1 (SCll
44
Vee
Vss
--J
1/0
P 1.0
--.l Pl.l
---.!± P 1.2
---,---2 P1.3
~ P1.4
--1, P1.5
~ P1.6
---.2. P1.7
---11
~
P2.0 l2..
P2.1 r?L
P2.2 ~
P2.3 28
P2.4
P2.5 30
P2.6 ~*
P2.7 r=--
~}
SDA 2082
132
PO.O
PO.1
P3.2( INTO)
PO.2
P3.3 (iNfT)
PO.3
P3.4(fOf
PO.4
P3.5(ffi
PO.5
P3.6 (WR)
PO.6
P3.7(RO)
PO.7
XTAL 1 XTAL 2 EA ALE PSEN
20
35
F1
34 33
P3.0 (IR)
~ P11
~
~
1/0
~
~
~
----12.
+r
20
Vee
HD~
1.2 ...12MHz
3~Wo~F
1
43
42
41
40
39
38
37
36
~
GNO
1
01 0
DO 0 19
2 011
DO 1 18
17
3.
012SAB
8282002
4
16
013
DO 3
5 014
004 15
6
14
DIS
DOS
13
~ 016.
DO 6
~ 017
DO 7 12
STB
11
+r
24
Vee
=
I»
3
'5!.
CD
..
0-
GNO
(I)
g
1 A7
2 A6
3 AS
4 A4
5 A3
6 A2
7 A1
8 AO
N
0
A11 ~
A10 ~
A9 ~
A8 ~
SAB 2732 A
OE
J2
r,
00
N
~
::r
.j:Io
~
l
=
CD
3
. 9
00
10 01
11 02
13
03
14 04
15 05
16
06
17 07
!!t
'C
a
CQ
iil
3
3
OElVpp
r
o
~
CE
1
8
0
-<
en
c
):a
I\)
_L
0
co
I\)
):0
'tI
"2+5V
$
~
+5V
10
Reset
2~ P4.0 (SOA)
• P4.1 (SCll
3
~
44
Vee
P2.0 ~
P2.1 ~
P 2.2 ~
28
P2.3
P2.4 29
P2.5
P 2.6 ~*
P 2.7 ~
~
----!!
---2
~}
--'J
SDA
2082
"
UR)
---u11 P3.0
P3.1
110
+r
20
Vee
Vss
~ P 1.0
Pl.l
Pl.2
P1.3
110
~ Pl.4
Pl.5
~ Pl.6
--.-..2 Pl.7
....
PO.O
PO.l
~ P3.2( INTO)
PO.2
---:J5 P3.3(iNff)
PO.3
P3.4(TO )
PO.4
p3.5(n)
PO.5
P3.6(WR)
PO.6
--= P3.7(RO)
PO.7
XTALl XTAL 2 EA ALE PSEN
21
20 35
34 33
1
,2. ..12 MHz
16
17
18
19
43
42
41
40
39
38
37
36
Hot
Ln. ~1-
~
r
lO IlF
30P~PF
4,7kQ
~-
+5V
~
GNO
1 010
000 19
2 011
DO 1 18
3 012
DO 2 17
4
16
003
013SAB 8282
~ 014
. 004 15
14
~ DIS
DDS
016
006 13
8 017
007 12
..--:r
STB
11
+5V
11 127
Vpp J5GM
~
l28
Vee GNO
i
0
:::J
E
3
l
...0g
(I)
3 A7
4 A6
5 AS
6 A4
7 A3
8 A2
9
10 A1
AO
~
SAB
OE
I
2764
1100
12 01
13 02
15 03
16 04
17 05
18 06
19 07
A12 ~
All .lLAl0 ~'
A9 ~
A8 ~
011
..
II.)
!§.
:r
011
~
1II
i
3.
N.c. ~
!!!.
'tI
a
CQ
DE
122
iil
3
3
II
IT
1
0
~
~
en
g
~
co
~
SDA2082
Application example for SDA 2082 with additional 256 byte external RAM and port expander
.5V
8.2kQ
10
23
Reset
24 P4.0 (SDA)
P4.1(SCL)
r
oot
VO{
2
3 P 1.0
. P 1.1
4
5 Pl.2
6 P1.3
7 P1.4
8 P1.5
9 P 1.6
P1.7
11
13
14
15
16
17
18
19
.5V
~101lF
44
Vce
.5V
P 2.0 25
I>
• 26
• 1..1
P 2.2 27
P 2.3 28
29
P 2.4
30
P2.5
31
P2.6
32
P2.7
~
SDA 2082
PO.O
PO.l
PO.2
PO.3
P3.3(~T1)
PO.4
P3.4 (!2)
PO.5
P3.5(~
PO.6
P3.6 (WR)
PO.7
P3.7 (RD)
XTAL 1 XTAL 2 fA ALE PSEN
21
20
35 35 33
P3.0 (IR)
P3.1 _
P3.2 (INT 0)
43
42
41
40
39
38
37
36
I
'I
}ro
7
12
13
14
15
16
17
18
19
r-l
20
21
PAO
PA 1 22
23
PA 2
24
PA3
PA4 25
26
PA 5
27
PA6
28
PA 7
101M
ADO
AD 1
AD2
AD3
AD4
ADS
AD 6
AD 7
SAB 8155
256 x 8
RAM
37
PC 0
38
PC 1
39
PC 2
1
PC 3
2
PC 4
5
PC 5
29
PBO
30
PB 1
31
PB2
32
PB3
PB4 33
34
PB 5
35
PB6
36
PB 7
~
Timer
138
1/0
SDA2082
SOA 2082 instruction set
Arithmetic operations
Mnemonic
Description
ADD A, Rn
ADD A, direct
ADDA,@ Ri
ADDA, # data
ADDCA, Rn
AD DC A, direct
ADDCA,@Ri
ADDC C, # data
SUBBA, Rn
SUBB A, direct
SUBBA,@ Ri
SUBB A, # data
INCA
INC Rn
INC direct
INC@Ri
DEC A
DEC Rn
DEC direct
DEC@ Ri
INC DPTR
MULAB
DIVAB
DAA
Add register to Accumulator
Add direct byte to Accumulator
Add indirect RAM to Accumulator
Add immediate data to Accumulator
Add register to Accumulator with Carry flag
Add direct byte to A with Carry flag
Add indirect RAM to A with Carry flag
Add immediate data to A with Carry flag
Subtract register from A with Borrow
Subtract direct byte from A with Borrow
Subtract indirect RAM from A with Borrow
Subtract immediate data from A with Borrow
Increment Accumulator
Increment register
Increment direct byte
Increment indirect RAM
Decrement Accumulator
Decrement register
Decrement direct byte
Decrement indirect RAM
Increment Data Pointer
Multiply A&B
DivideA&B
Decimal Adjust Accumulator
Bytes
Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
2
4
4
1
139
SDA2082
SOA 2082 instruction set
Logical operations
Mnemonic
Description
ANLA, Rn
ANL A, direct
ANLA,@ Ri
ANLA, # data
ANL direct, A
ANL direct, # data
ORLA, Rn
ORL A, direct
ORLA,@Ri
AND register to Accumulator
AND direct byte to Accumulator
AND indirect RAM to Accumulator
AND immediate data to Accumulator
AND Accumulator to direct byte
AND immediate data to direct byte
OR register to Accumulator
OR direct byte to Accumulator
OR indirect RAM to Accumulator
on immediate data to Accun-Iulatof
OR Accumulator to direct byte
OR immediate data to direct byte
Exclusive-OR register to Accumulator
Exclusive-OR direct byte to Accumulator
Exclusive-OR indirect RAM to Accumulator
Exclusive-OR immediate data to Accumulator
Exclusive-OR Accumulator to direct byte
Exclusive-OR immediate data to direct
Clear Accumulator
Complement Accumulator
Rotate Accumulator left
Rotate A left through the Carry flag
Rotate Accumulator right
Rotate A right through Carry flag
Swap nibbles within the Accumulator
nOI
_. 'L.. I A'r
++
Tr
r-I~"'",
U,"",L~
ORL direct, A
ORL direct, # data
XRLA, Rn
XRL A, direct
XRLA,@ Ri
XRLA,# data
XRL direct, A
XRL direct, # data
CLRA
CPLA
RLA
RLCA
RRA
RRCA
SWAP A
140
Bytes
Cycles
1
1
1
1
1
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
2
1
1
1
i
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
SDA2082
SOA 2082 instruction set
Data transfer operations
Mnemonic
Description
MOVA, Rn
MOV A, direct
MOVA,@Ri
MOVA, # data
MOVRn,A
MOV Rn, direct
MOV Rn, # data
MOV direct, A
MOV direct, Rn
MOV direct, direct
MOV direct, @ Ri
MOV direct, # data
MOV@Ri,A
MOV @ Ri, direct
MOV @ Ri, # data
MOV DPTR, # data 16
MOVCA@ A+DPTR
MOVCA@A+PC
MOVXA,@ Ri
MOVX A, @ DPTR
MOVX@Ri,A
MOVX @ DPTR, A
PUSH direct
POP direct
XCHA, Rn
XCH A, direct
XCHA,@Ri
XCHDA,@Ri
Move register to Accumulator
Move direct byte to Accumulator
Move indirect RAM to Accumulator
Move immediate data to Accumulator
Move Accumulator to register
Move direct byte to register
Move immediate data to register
Move Accumulator to direct byte
Move register to direct byte
Move direct byte to direct byte
Move indirect RAM to direct byte
Move immediate data to direct byte
Move Accumulator to indirect RAM
Move direct byte to indirect RAM
Move immediate data to indirect RAM
Load Data Pointer with a 16-bit constant
Move Code byte relative to DPTR to Accumulator
Move Code byte relative to PC to Accumulator
Move External RAM (8-bit addr) to Accumulator
Move External RAM (16-bit addr) to Accumulator
Move A to External RAM (8-bit addr)
Move A to External RAM (16-bit addr)
Push direct byte onto stack
Pop direct byte from stack
Exchange register with Accumulator
Exchange direct byte with Accumulator
Exchange indirect RAM with Accumulator
Exchange low-order digital indirect RAM with A
Bytes
Cycles
1
1
1
1
1
1
2
1
2
1
2
2
2
2
3
2
3
2
1
1
2
2
2
2
1
1
2
2
3
2
1
1
1
1
1
1
2
2
1
2
1
1
1
2
2
2
2
2
2
2
2
2
1
1
1
1
141
SDA2082
SDA 2082 instruction set
Boolean variable manipulation
Mnemonic
Description
CLRC
CLR bit
SETBC
SETB bit
CPLC
CPL bit
ANLC, bit
ANL C,/bit
ORLC, bit
nOI "I,",U·
_I' .... "',/U.'
MOVC, bit
MOVbit,C
142
Clear Carry flag
Clear direct bit
Set Carry flag
Set direct bit
Complement Carry flag
Complement direct bit
AND direct bit to Carry flag
AND complement of direct bit to Carry
OR direct bit to Carry flag
OR COfilpiemeni of direct bit to Carry
Move direct bit to Carry flag
Move carry flag to direct bit
Bytes
Cycles
1
1
1
1
1
1
1
2
1
2
1
2
2
2
2
2
2
2
2
2
2
2
1
2
SDA2082
SDA 2082 instruction set
Program control operations
Mnemonic
Description
Bytes
Cycles
ACALL addr 11
LCALL addr 16
RET
RETI
AJMPaddr 11
LJMPaddr 16
SJMP rei
JMP@A+DPTR
JZ rei
JNZ rei
JC rei
JNC rei
JB bit, rei
JNB bit, rei
JBC bit, rei
CJNE A, direct, rei
CJNE A, # data, rei
CJNE Rn, # data, rei
CJNE @ Ri, # data, rei
DJNZ Rn, rei
DJNZ direct, rei
NOP
Absolute subroutine call
Long subroutine call
Return from subroutine
Return from interrupt
Absolute jump
Long jump
Short jump (relative addr)
Jump indirect relative to the DPTR
Jump if Accumulator is zero
Jump if Accumulator is not zero
Jump if Carry flag is set
Jump if Carry flag is not set
Jump if direct bit set
Jump if direct bit not set
Jump if direct bit is set and clear bit
Compare direct to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to register and jump if not equal
Compare immediate to indirect and jump if not equal
Decrement register and jump if not zero
Decrement direct and jump if not zero
No operation
2
3
2
2
2
2
3
3
3
3
3
3
3
2
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
2
3
2
1
Symbols and abbreviations
A
adr
CNT
DA
data
P
Pp
Accumulator
11-bit program memory address
Event counter
D/A converter indication
8-bit binary number
Mnemonic for "in page" operation
Port label (p = 0-3)
Rr
Sn
T
TO, T1
#
@
Register label (r = 0-7)
S interface label (n = 0; 1)
Timer
Test 0, test 1
Refers to immediate data
Refers to indirect addressing
143
144
Application-Qriented Single -Chip Microcomputer
for Special Cost-Critical Applications
SOA 2110
DIP 28
Features
•
•
•
•
•
•
•
•
•
•
•
8-bit CPU, ROM, RAM, I/O
in a DIP 28 package
2'1 digital I/O lines
one serial interface
ont;! 8-bit interface
two 4-bit interfaces
one 1-bit interface
two test inputs
1 Kbyte ROM
40 byte RAM
7.5 j..ts cycle time at 4 MHz crystal frequency -1 or 2 cycles per instruction
Zero passage detector
Interface for modulated digital signal
Interval timer/counter
+5 V supply voltage
RAM standby operation
SAB 8048 instruction subset
Circuit description 1)
The SDA 2110 introduces a new generation of highly economic single-chip computers with
appiication-specific control functions. Considerable cost savings can be realized during
the development and production stages, because the emphasis on specific applications
reduces at the same time the number of additionally required hardware and simplifies
the software tasks. Although the SDA 2110 was designed for electronic entertainment devices,
it is equally suitable for mass-produced applications requiring highly economic components.
The SDA 2110 is eqipped with a 1 Kbyte program memory (ROM) and 40 byte data memory
(RAM), which can be used in "standby" operation during heavily reduced output losses.
The 21 digital I/O lines include one 8-bit port, two 4-bit ports, two test inputs, one serial
interface and one single bit interface. Test input TO processes signals modulated with
approx. 30 kHz and is equipped with a digital demodulator, which derives the envelope
curve from the modulated digital signal. Since the digital demodulator forwards an unmodulated signal without changing it, test input TO can also function as a normal digital
input during operation with standard H/L levels. Test input T1 includes a zero passage
(crossing) detector and can also serve as a normal digital input. A data and pulse line
comprise the serial interface. The component is equipped with its own oscillator and
timer/counter.
1) Detailed description is available upon request
145
SDA2110
The instruction set includes 66 instructions (1-2 bytes) which can be processed in max.
2 cycles. Numerical problems can be processed in either binary or BCO arithmetic mode.
The large number of bit-handling instructions increases the efficiency of the controller
functions.
Program development and system testing for the SOA 2110 is carried out on the SME
development system with the SOA 2110 emulator board EMB U21. The EMB U21 emulator
consists of one 2K EPROM (SAB 2716) as well as a 40 pin socket which is used to insert
an SAB 8035L type microprocessor or the ICE 48 plug. In addition, the EMB U21 contains
all the necessary hardware to simulate the serial and parallel interfaces of the SOA 2110.
A 28 wire cable is used to connect the U21 emulator with the user system.
A version without ROM (SOA 3110) is available which enables in-house software developments on an SME device.
Maximum ratings
Supply voltage range
Voltage between any pin and ground
Total power dissipation
Storage temperature range
Vee
V
Ptot
Tstg
-0.5 to 7
-0.5 to 7
1
-40 to 125
V
V
W
5 ±10%
V
DC
Operating range
Supply voltage
Ambient temperature
146
Vee
TA
o to 70
DC
SDA2110
DC characteristics
TA =
ooe to 70 oe, Vee =
L input voltage
H input voltage
H input voltage
H input voltage
L output voltage
L output voltage
H output voltage
H output voltage
H input current
L input current
Input voltage at T1
Zero passage detector
current consumption
VSB
=5V ±10%; Vss = OV
(Ports, SSO, SSl, RESET, TO, Tl, Xl)
(Ports, SSO, SSl)
Vee = 5.0 V ± 10%
(Ports, SSO, SS 1)
Vee = 6.0 V ±0.5 V
(RESET, Xl, TO, Tl)
(Ports, ALE)
I qL =1.6mA
(SSO, SSl, SCPO, SCP1)
IqL =4 mA
(Ports, ALE)
I qH =50 f.lA
(SSO, SSl, SCP1)
IqH = 150 f.lA
(TO, T1)
II;H = Vee
(Ports, SSO, SSl)
II;L =0.45 V
(Gj = 1 f.lF) (peak-to-peak)
min
max
II;L
II;H
-0.5
2.0
0.8
Vee
V
V
II; HI
2.4
Vee
V
II; H2
VqL
3.5
Vee
0.45
V
V
0.45
V
VqL1
VqH
2.4
V
VqH1
2.4
V
10
f.lA
340
f.lA
Vn
3
V
Icc
60
mA
50
f.ls
i;H
-i;L
30
AC characteristics
TA =O°Cto 70 oe, Vcc = VsB =5 V ±10%; Vss =0 V
Cycle time
tc
10
tALE
1.3
Ll fosc
-20
t MTO
60
fTR
30
fTI
0.03
3 MHz crystal = 10 f.ls
ALE pulse width
f.ls
t c =10f.ls
Oscillator frequency deviation
+20
%
f=2.5 MHz, R=15 kQ
Length of an unmodulated signal at the TO test input
3 MHz crystal
Frequency of a modulated signal at the TO test input
3 MHz crystal
Frequency range of the zero passage detector (input Tl)
f.ls
35
kHz
kHz
147
SOA 2110
Pin description
Pin
Symbol
Function
28
Vee
VS B
14
Vss
X1, X2
+5V
+ 5 V standby supply
GNDOV
Connection for crystal or similar
15,16
4-11
18-21
PO 0-7
22-25
26
P20-3
P30-3
SSO
~I
".,
SSI
2
17
SCP1
RESET
3
TO
13
T1
12
ALE
148
Quasi-bidirectional 8-bit port
Quasi-bidirectional 4-bit port
Quasi-bidirectional 4-bit port
1-bit interface I/O pin
Seriai interface S 1 I/O pin
Serial interface S1 clock pulse
Reset input for computer initialization (active H).
Resets program counter, erases the status FFs,
sets all digital outputs to H state.
Input that can be tested with the conditional jump
instruction JTO and JNTO. The input contains a digital
demodulator and can be used for the separation of the
envelope curve from a modulated signal.
Input that can be tested with the conditional jump
instruction JT1 and JNT1. Serves simultaneously as an
external counter input. (Selection of functions with
instruction STRT CNT). The input can also be used for
zero passage recognition of low frequency alternating
voltages.
This output generates one clock pulse signal per cycle.
SDA2110
SOA 2110 instruction set
0
§
:::J
E
:::J
C,)
C,)
«
Mnemonic
Description
Bytes
Cycles
Hexadecimal
opcode
ADDA, Rr
ADD A,@ R
ADD A, # data
AD DC A, Rr
AD DC A,@ R
AD DC A, # data
ANLA, Rr
ANLA,@R
ANL A, # data
ORLA, Rr
ORLA,@R
ORLA, # data
XRLA, Rr
XRLA,@R
XRLA, # data
INCA
DEC A
CLRA
CPLA
DAA
SWAP A
RLA
RLCA
RRA
RRCA
Add register to A
Add data memory to A
Add immediate to A
Add register with carry
Add data memory with carry
Add immediate with carry
And register to A
And data memory to A
And immediate to A
Or register to A
Or data memory to A
Or immediate to A
Exclusive Or register to A
Exclusive Or data memory to A
Exclusive Or immediate to A
Increment A
Decrement A
Clear A
Complement A
Decimal adjust A
Swap nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A right through carry
1
1
1
1
2
2
1
1
1
1
2
2
1
1
2
1
1
2
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
2
1
1
2
1
1
1
1
1
1
1
1
1
1
68-6F
60-61
03
78-7F
70-71
13
58-SF
50-51
53
48-4F
40-41
43
DB-OF
00-01
03
17
07
27
37
57
47
E7
F7
77
67
149
SDA2110
SDA 2110 instruction set
0
:::::
'"
Q)
Mnemonic
Description
Bytes
Cycles
Hexadecimal
opcode
INA, Pp
OUTPp,A
IN A, S1
INA,SO
OUTS1,A
OUTSO,A
Input port to A
Output A to port
Input serial port to AO
Input 1 bit port to AO
Output AO to serial port
Output AO to 1-bit port
1
1
1
1
1
1
2
2
2
2
2
2
08,OC,OD
90, 3C, 3D
OF
DE
3F
3E
CALL
Jump to subroutine
1
2
RET
Return
1
2
14,34,54,74,
94, 84, D4, F4,
83
JMP adr
Jump unconditional
2
2
JMPP@A
DJNZ Rr, adr
1
2
2
2
JC adr
JNC adr
JZadr
JNZ adr
JTO adr
JNTO adr
JT1 adr
JNT1 adr
JTF adr
Jump indirect
Decrement register and
jump on R not zero
Jump on carry = 1
Jump on carry = 0
Jump on A zero
Jump on A not zero
Jump onTO= 1
Jump onTO= 0
Jump on T1 = 1
Jump on T1 = 0
Jump on timer flag
04, 24, 44, 64,
84, A4, C4, E4
B3
E8-EF
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
F6
E6
C6
96
36
26
56
46
16
CLRC
CPLC
Clear carry
Complement carry
1
1
1
1
97
A7
Ie::
.o~
we
::J~
'"
Q)
.c
u
e::
~
In
'til"
OJ
u:
150
SDA2110
SDA 2110 instruction set
II)
e:
0
:g
2
1il
.~
'""
'*
e:
~
I-
Mnemonic
Description
Bytes
Cycles
Hexadecimal
opcode
MOVA, Rr
MOVA,@R
MOVA, # data
MOVRr,A
MOV@R,A
MOV Rr, # data
MOV@R, # data
XCHA, Rr
XCHA,@R
XCHDA,@R
MOVPA,@A
Move register to A
Move data memory to A
Move immediate to A
Move A to register
Move A to data memory
Move immediate to register
Move immediate to data memory
Exchange A and register
Exchange A and data memory
Exchange nibble of A and register
Move to A from current page
1
1
2
1
1
2
2
1
1
1
1
1
1
2
1
1
2
2
1
1
1
2
F8-FF
FO-F1
23
A8-AF
AO-A1
B8-BF
BO-B1
28-2F
20-21
30-31
A3
Read timer/counter
Load timer/counter
Start timer
Start counter
Stop timer/counter
1
1
1
1
1
1
1
1
1
1
42
62
55
45
65
INC@R
Increment register
Increment data memory
1
1
1
1
18-1F
10-11
NOP
No operation
1
1
00
MOVA, T
'"" MOVT,A
lI)al
STRTT
ale:
E::l STRTCNT
._0
1-(.") STOP TCNT
....
...
II)
~
12 INCRr
al.!!1
C:0l
~
Symbols and abbreviations
A
adr
CNT
data
P
Pp
Accumulator
10-bit program memory address
Event counter
8-bit binary number
Mnemonic for "in page" operation
Port label (p = 0, 2, 3)
Register label (r = 0-7)
S interlace label (n = 0; 1)
Timer
T
TO, T1 Test 0, Test 1
#
Refers to immediate data
@
Refers to indirect addressing
Rr
Sn
151
152
TV PLL for 125 kHz Resolution
SDA2112-2
DIP 18
The SDA 2112-2 is fabricated in ASBC technology. In connection with a VCO (tuner) and
a high-speed 1 :64 divider, it forms a digitally programmable phase-locked loop .for TV sets
designed to use the PLL frequency sythesis tuning principle. The PLL enables crystalcontrolled setting of the tuner oscillator frequency for a 125 kHz resolution in the frequency
bands 11111, IV, and V.
A serial interface provides for simple connection to a microprocessor. The latter loads the
programmable divider and the band-selection outputs with the appropriate information.
Features
• No external integrator necessary
• Internal buffer
• Microprocessor compatible
153
SDA2112-2
Maximum ratings
Supply voltage
pin 18
I -0.3 to 7.5
VS1
Inputs
Q 1. Q 2. F.
F
pin 1. 2. 15.16
CPL. IFO. PLE
pin 7. 8.10
Outputs
UHF. VHF. Bd 1/111
pin 3. 4. 5
eLK (pili 6)
LDM (pin 17)
+ 0.2
V
VI
-0.3 to VS1
VI
-0.3 to 5.5
V
Va
-0.3 t016
V
Vs
-0.3 io
3
-0.3 to
3
-0.3 to
1
-0.3 to
-0.3 to
8
140
V
mA
V
mA
V
mA
V
V
mA
°C
°C
Is
V17
117
LOCK IND (pin 12)
PD(pin14)
Vo (pin 11)
OSC (pin 13)
Iv
V12
114
Vll
V13
1 13
Junction temperature
Storage temperature range
7j
Thermal resistance (system-air)
RthSA
Tstg
i6
7.5
VS1 +0.2
33
VS1 +0.2
-40 to 125
80
K/W
Operating range
Supply voltage range
Input frequency
Divider factor
Crystal frequency
Tuning voltage
Ambient temperature
154
VS1
fF.F
N
fa
Vo
TA
4.5 to 7.15
16
256 to 8191
3
0.3 to 33
o to 70
V
MHz
MHz
V
°C
SDA2112-2
Characteristics
Vs1 =5V;TA=25°C
Test
circuit
Supply current, pin 18
Oscillator output, pin 13
RL2 =3.5 kG
OSC
RL2 =3.5 kG
Signal inputs FIF, pin 15, 16
Input voltage
Input current
V15 = 5 V ,
Input sensitivity (peak-to-peak)
Sine push-pull f = 16 MHz
Bus inputs CPl, IFO, PlE, pin 7, 8, 10
Upper threshold voltage
lower threshold voltage
Hysteresis
H input current
V7H =5 V
L input current
V7L =0.4 V
Band selection outputs UHF, VHF, Bd 1/111
pins 3, 4, 5
Reverse current
V3H =15 V
Forward current (current drain)
Imin
I typ
20
is1
V13H
4
V13L
4
max
35
mA
V
0.7
V
4.5
V15H
V15L
115
4.1
3.8
VS1+0.2
Vs1 -O.1
50
V
V
j.iA
V15 .16
300
1200
mV
1.6
1.0
V
V
V
j.iA
V7u
V71
LlV7
hH
2
2
2
2
1.0
0.5
III
2
-50
hH
3
hL
3
0.8
VSH
4
14
VSL
4
V11
5
0.3
~4
5
-150
114
5
-450
1.3
0.7
0.6
8
j.iA
10
j.iA
1.7
mA
2V~ V3~15V
Clock output ClK, pin 6
H output voltage
Vs3 =15V
L output voltage
RL1 =6.8 kG
Tuning section VD , PO, pins 11, 14
Tuning voltage
Vs2 =33 V
Charge-pump current
PLLlocked
PLL unlocked
V
1.5
V
32.5
V
±100
150
j.iA
±300
450
j.iA
155
SDA2112-2
Characteristics (cont'd)
VS1 =15 V;
TA
=25°C
Test
circuit
min
5
5
2.8
typ
max
Lock indication, pin 12
H output voltage
L output voltage
V12H
V12l
0.4
V
V
117
10
IlA
V17 l
0.4
V
Carry synchronous divider LDM
Pin 17 (open collector)
Reverse current
V17H =5V
L output voltage
R, =5 kQ
Switching times
IFO, PLE
Set-up time
Hold time
CLK
H pulse width
L pulse width
HL transition time
RL1 =6.8 kQ
LH transition time
Cu =50 pF
CPL
H pulse width
L pulse width
OSC
H pulse width
L pulse width
HL transition time
Rl2 =3.5 kQ
LH transition time
CL2 =8 pF
156
ts
tH
tTH
tTL
tTHl
2
2
4
4
4
tTlH
2
2
0.5
0
1.5
Ils
133
tOHl
4
4
4
tOlH
4
tOH
tOl
8.0
8.0
0
2
2
tClH
Ils
Ils
Ils
Ils
Ils
2
2
tCH
1.5
1.5
1.5
1.5
Ils
Ils
200
20
ns
ns
ns
50
ns
SDA 2112-2
Circuit description (refer to block diagram)
F, F
lDM
IFO
CPl
PlE
A switchable 16/17 counter is triggered by the ECl signal inputs F/F. The counter,
in connection with a 4-bit and a 9-bit programmable, synchronous counter, forms
a programmable, 13-bit synchronous divider using the dual-modulus technique,
the 4-bit counter controlling the switch over from 16 to 17. Divider ratios of
N = 256 to 8191 are possible. For test purposes the carry of the synchronous
divider is available at the lDM output (open collector).
The 16-bit shift register and latch is subdivided into 13 bits for storing the divider
ratio Nand 3 bits for controlling the three band-selection outputs.
The telegram is shifted in via the serial data input IFO with the Hl edge of the
shift clock CPl when the enable input PlE is also on high level. First the complement
of the divider ratio N, beginning with the lSB, is inserted in binary code, followed
by the three control bits for the band-selection switching (see truth table). The 16-bit
latch takes the data from the shift register when the enable input PlE is on low
level.
01,02 The IC includes a crystal-controlled, 3-MHz clock oscillator. The output signal is
divided down to 1.953125 kHz (reference signal) by a 1/1536 reference divider.
OSC
The oscillator frequency appears at the TTL output OSC.
ClK
The clock of 62.5 kHz is available at the open-collector output ClK.
PO
The divided input signal is compared with the reference signal in a digital phase
detector. If the falling edge of the input signal appears prior to the falling edge
ot the reference signal, the DOWN output of the phase detector turns to high
level for the duration of this phase difference. In the reverse case the UP output turns
to high level. If the two signals are in phase, both outputs remain at low level.
The UP/DOWN outputs control the two current sources [+ und [- (charge pump).
If the two outputs are low (Pll locked), the charge-pump output PO will turn to
the high-impedance state (TRISTATE).
lOCK
IND
An l signal appears at the lOCK IND output if frequency and phase are
synchronous. The current sources [+ and [- are then reduced from 300 to 100 iJA.
VD
The current pulses generated by the charge pump are integrated to form the
tuning voltage by means of an active lowpass filter (external pull-up resistor to
supply VS2 and external RC circuitry). The dc output signal appears at VD and
serves as a tuning voltage for the VCO.
UHF
VHF
Bd 1/111
The band-selection outputs (UHF, VHF, Bd 11111) contain current drains with open
collectors. In this way PNP transistors working as band-selection switches can be
connected directly without current-limiting resistors (see application circuit).
157
SDA2112·2
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
158
Symbol
Function
Q2
Q1
Crystal·
Crystal
UHF
VHF
Bd 1/111
ClK
CPl
IFO
GND
PLE
Vo
LOCK IND
OSC
VpD
F
F
LDM
VS1
} Band selection outputs
Clock output
Clock input
Data input
Ground
Shift register enabie input
Tuning voltage
lock indication output
Oscillator output
Phase detector voltage
Inverted input
Input
Carry
Supply voltage
SDA2112-2
Block diagram
Vs,
GNO
OSC
62.5kHz
0.1
LOCKINO
PO
0.2
(,
L...-_-----I/
1.953125 kHz
Vo
Tuning
Voltage
LOM
16-8il SR
+ Memory
~
Interface 10
VHF
UHF
BdlllIl
IlP
159
SDA2112-2
Computation for loop filter
P
=Prescaler
= Programmable divider
= Pump current
/p
Kvco =Tuner slope
R,C, = Loop filter
=jC,xPxN
Loop bandwidth: wR
Attenuation: (= 0.5
N
/p x Kvco
X
wR x R xC,
Example for channel 47:
P=64;
N=5760;
/p=100 ~A;
Kvco =18.7 MHz/V;
C, = 330 nF;
W R = 124 Hz;
fn = 20 Hz;
(= 0.675
Postfiiter: Kt=iO KQ;
R=33 kQ
Ct =4( nt-
Standard dimensioning: C2 = ClIS
Vs ,=5V;
VS2=33V;
VS3=12V;
R2 toR 4 =22kQ;
RL =22kQ
Application circuit
[r
f;
Tuner
H
'IF
Divider: 64
'osc
3MHz
.~1
Vvancap
RL
VS2
Q2
Q1
[,
1
2
F
16
F
15
PO 14
13
PLLIC
SOA 2112-2
160
18
DS(
IFO
10
PLE
(PL
Serial Interface to Ile
SDA2112-2
Truth table
Input "IFO" bit
Meaning
Outputs
2 13
214
2 15
Bdl/lll
VHF
UHF
H
H
L
H
H
L
"UHF"
H
L
H
H
L
H
"Bd IIVHF"
L
L
H
L
L
H
"Bd IIIIVHF"
L
H
H
L
H
H
"Bd IIIIVHF"
At positive logic, the "IFO" bits 2° ... 212 complement the dual code from divider ratio N.
Pulse diagram
I• I
PLE
"-='------'
ILSB
MSB
I
I-- Divider Ratio N ----J
.~~
n
~L
LSB
- - H: LHH LHLHL L LHHILL
20
I
12 13
N= 1874. BdmlVHF
I'------v-----------'I
liFO Evaluated by CPL and PLE
I
I
I
161
SDA2112-2
Pulse djagram
162
SDA2112-2
Test and measurement circuits
5V
18
V16
116 16
V15
115 15
Signal
Inputs
Push-Pull
5 kR
Carry
SYNC Divider
Test circuit 1
40kQ
17,8,10
V7, 8, 10
7,8,10
V3 , 4, ~5---01]0:-,4::.:,5-+3:::..,4.c::'s=____-----..
CPLIIFO/PLE
BUS Inputs
Band
Selection
Outputs
110Q
40krl
Test circuit 2
Test circuit 3
163
SOA 2112-2
Test and measurement circuits
Crystal
Os~jilator
h
OutputCLK
Test circuit 4
HD3M Hz
18pF
3kll
33V
22kll
V"
I"
_--+-~--+_,
11
Tuning Section
Inputs/Outputs
V
1'4
'4----~1~4r---------~
Test circuit 5
164
2,2 kll
120 MHz PLL for AM/FM Receivers
SDA2120
DIP 22
The SDA 2120 contains the complete digital section (reference oscillator, 20-bit shift register
with memory, programmable divider, band select outputs as well as a phase detector, two
charge pumps, one current multiplier, and two amplifiers) for tuning an AM/FM receiver
by PLL frequency synthesis.
A serial interface facilitates connection to a microprocessor. The microprocessor will load
the divider, the band select outputs, and the current multiplier with the suitable information.
Features
•
•
•
Integrated prescaler
Switch-selectable from AM to FM
High frequency resolution FM =12.5 kHz, AM = 0.5 kHz
Maximum ratings
Supply voltage
Tuning supply voltage
IFO, PLE, CPL
Band select: UKW, SW, MW, LW
AM,FM
F
Input current amplifier
Output current amplifier
Junction temperature
Storage temperature range
Thermal resistance (system-air)
V
V
V
V
V
V
Tstg
7.5
32
5.5
18
5.5
5.5
500
7
140
-40 to 125
RthSA
65
K/W
Vs
4.5 to 5.5
-25 to 85
>100
10
120
2 116383
4097 I 16383
V
Vs
VSAMlVsFM
ViH
Vas
VAM/FM
VF
i;v
IDAM/FM
~
j.lA
mA
°C
°C
Operating range
Supply voltage
Ambient temperature range
Resistance for charge pump current 1)
Input frequency input AM
Input frequency input FM
Prescaler factor LW/MW
Prescaler factor SW/UKW
1) Multiplication factor M
Tamb
Rr
fiAM
fiFM
NLW/MW
NSW/UKW
°C
kQ
MHz
MHz
= 15
165
SDA2120
Characteristics (Vs = 5 V; Tamb = 25 °el
min
Supply current
L tuning voltage VtunAMlVtunFM (lOL = 2.5 mAl
H tuning voltage VtunAM(VS2 = 32 V)
H tuning voltage VtunFM (VS2 = 32 V)
Is
Sensitivity input AM (I = 10 MHz)
Sensitivity input FM (I = 120 MHz)
VIAMrms
ViFMrms
Input resistance input AM
(1= 10 MHz; ViAMrms = 100 mY)
Input resistance input FM
(1=120 MHz; VIFMrms=100 mY)
input capacitance, input AM/FM
RiAM
VOL
VtunHAM
VtunHFM
typ
max
60
0.5
30
30
10
20
mA
V
V
V
mV
mV
kQ
0.5
RIFM
Ci
kQ
I pF
14
Inputs IFO, PLE, CPL
Upper threshold voltage
Lower threshold voltage
H input current
L input current
VSu
VS1
IiH
IiL
2.01)
0.81)
8
-50
V
V
IlA
IlA
BS outputs: UKW, SW, MW, LW
(Vpp = 15 V)
(0.5 V ::;; Vpp = 15 V)
I qH
IqL
10.8
10
1 3.0
lilA
mA
0.7
5
V
V
IlV
1
±500
IlV
IlA
±5
nA
11.2
Oscillator output F
(lFH =-100 IlA)
(lFL = 100 IlA)
Residual ripple of the tuning voltage
(I = 0-1 kHz, test bandwidth 10Hz)
(I = 1-50 kHz, test bandwidth 100 Hz)
Charge pump output current AM/FM
(R 1 =130 kQ, M=15,
IqAI tested against 2.5 V) tristate
VqFH
VqFL
VlunAM
4.5
VtunFM
IqAI
Switching times
IFO, PLE
Set-up time for enable
Set-up time for data
Hold time for enable
Hold time for data
tSE
tso
tHE
tHO
0.3
0.4
3
3
Ils
Ils
Ils
Ils
CPL
H pulse width
L pulse width
tCH
tCL
I~
Ills
IlS
F
H pulse width
L pulse width
H/L transition time (CL2 = 10 pF)
LlH transition time (C L2 = 10 pF)
1) Values apply throughout the operational range.
166
tFH
tFL
tFHL
tFLH
200
300
20
50
ns
ns
ns
ns
SDA2120
Truth table
Function
"IFO"
214
bit
215
Band select outputs
LW MW SW UKW
fref/kHz
Active
input
Active
output
LW
MW
SW
UKW
L
L
H
H
L
H
L
H
H
H
H
H
0.5
0.5
0.5
12.5
AM
AM
AM
FM
AIAM
AI AM
AI AM
AIFM
H
L
H
H
H
H
L
H
H
H
H
L
Pulse diagram
iL
I
1
I
I
~
i
I
2° i
1
I
1
I
1
1
iLSB
I
1
1
1
I
i
MSB I
I
iLSB MSBi
Divider rutio --+l
~
I MW Current:
N =1930
I1
ill
I
i
1
1
10.[
1215
I
1
I
12 19
I
t
First shifted bit
167
SDA2120
Pulse diagram
Set-up and hold times
IFO
PLE
CPL
168
SDA2120
Circuit description
The component contains a 14 bit programmable synchronous divider (% P, % M, % S), which
divides the frequency of a signal pending at input AM, or FM resp. by the factor N=2 ... 16383
(LW/MW), or N = 4097...16383 (SWIVHF). The buffered inputs AM and FM can be directly
connected to the VCO via capacitors due to their own prevoltage generation.
The input sensitivity of the inputs is 10 mVrms (AM) or 20 Vrms (FM). The frequency divider
input can be switched optionally to AM or FM per software switch. While the LW/MW signal
is divided into a pure synchronous divider,. the SWIVHF signal is divided into a modulo two
divider followed by a synchronous divider. The shift register with latch, with a depth of
20 bits, is divided into 14 bits to store the divider ratio N of the synchronous divider;
2 bits to control the four band select outputs (VHF, SW, MW, LW); 4 bits for the current
multiplier to select the optimum current for the charge pump.
The divider ratio N, the band selection, as well as the information for the current multiplier
are loaded into the 20 bit shift register via the serial data input IFO. First, the complement
of the divider ratio, beginning with the least significant bit, is loaded in a binary encoded
form. This is followed by the band select control bits SBO und SBl (refer to table), finished
by the information bits for the current multiplier. During FM operation, they are loaded in
binary encoded form beginning with the LSB, during which the bit sequence 0000 is not
permissible. During AM operation, the complement of the information bit is loaded in
binary encoded form beginning with the LSB, during which the bit sequence 1111 is not
permissible. The information is loaded with the HL slope of the shift pulse CPL. Acceptance
of the data at the IFO input can only take place during the H state of the enable input PLE.
The 20 bit latch accepts the data from the shift register during the L state of the enable
input PLE. The component is equipped with its own crystal-controlled 4 MHz pulse oscillator.
A square-wave signal of 2 MHz derived from the pulse oscillator is available at output F,
which can be used for the synchronization of peripheral devices (e.g. microprocessor).
The output F is to be connected to ground in order to provide a high signal-to-noise ratio.
The oscillator output signal (fosc = 4 MHz) is divided down to 0.5 kHz or 12.5 kHz respectively,
by a switch-selectable reference divider (reference signal). The reference divider is switched
by the same signal that also switches the inputs. The divided input signal is compared with
the reference signal in a digital phase detector. If the falling edge of the divided input signal
appears prior to the falling edge of the reference signal, the DOWN output of the phase
detector goes into the H state for the duration of the phase difference. In the opposite
case, the output UP goes into the L state. If both signals are in phase, the DOWN output
remains in the L state and output UP in the H state.
169
SDA2120
The outputs UP/DOWN control the two current sources 1+ and 1- (charge pump). If output
UP is in the L state, current source 1+ is activated; if output DOWN is in the H state, current
source 1- is in effect. If DOWN is in the L state and UP is in the H state, the charge pump
output changes into a high-ohmic state (TRI STATE). The current pulses generated by
the charge pump are integrated with the aid of an active low pass (external FET op amp
with RC circuitry). The DC output signal of the low pass is available at the FET op amp
output and serves as tuning voltage for the VCO. If there are minor requirements to be
met regarding the signal-to-noise ratio, an internal amplifier with a series-connected external
darlington transistor can be used instead of the external FET op amp. The output stage
of the internal amplifier comprises a transistor with open-collector output. The external
collector resistor can then be connected to voltages up to 30 V. The output transistor is
dimensioned such that a voltage drop of 0.5 V occurs at a 2.5 mA collector current.
The corflponeni coniains two separate charge pumps and two separate amplifiers. Only
one charge pump is active at a time. The switch-over is achieved by the same signal that
also switches the AM/FM inputs. Thus, separate low passes can be set up for AM and FM.
The output current of both charge pumps (source current = sink current) is M x L M is the
multiplication factor that is given by the information bits for the current multiplier, M being
an integer and 1 :s; M:S; 15. I is the basic current of the charge pump that is set by means of
an external resistor between pin Ire! and Vs. As the software monitors the current, a fast
transient response of the PLL during band limit peaks and range changes (recharging
the low pass) can be achieved, as well as a high signal-to-noise ratio in the steady state. The
delay time between phase detector input and charge pump output is typically 20 ns. The
phase detector with charge pump gain depends on the selected charge pump output current
and is calculated as follows:
K,=~[~]
o 4:n: rad·
The wiring of the charge pump output AI has to ensure that the DC voltage value at the
output varies only.j)etween 1.2 V and 3.8 V (e.g. by applying a reference voltage of approx.
2.5 V when using the external operational amplifier. The band select outputs contain current
drains (~L = 0.8 to 3.0 mAl with open collectors, in order to be able to switch voltages
greater than the supply voltage of the component (5 V). Thus the transistors, operating
as band select switches, can be directly driven without current limiting resistors (refer to
application circuit).
During operation, pin 2 (N.C.) must be connected to ground.
170
SDA2120
Supplements to the circuit description
Relationship between IFO bits of current multiplier and multiplication factor for the output
current of the charge pump.
IFOBIT
2 16
217
218
2 19
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
Multiplication
factor M
FM
Multiplication
factor M
AM
0
1
2
3
4
5
15
14
13
12
11
10
6
7
8
9
9
8
7
6
10
11
12
13
14
15
5
4
3
2
1
0
171
SOA 2120
Pin configuration
Pin No.
Symbol
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
10
21
22
EVAM
Amplifier input AM
N.C.
Charge pump output AM
Signal input VHF
Signal input SW/MW/LW
Supply voltage
Crystal
Crystal
Band select output VHF
8and se~ect output LV"!
Oscillator output
Band select output MW
Band select output SW
Data input
Shift register input
Enable input for shift register
Ground
Current adjustment for charge pump
Tuning voltage FM
Amplifier input FM
Charge pump output FM
Tuning voltage AM
172
AI AM
FM
AM
Vs
02
01
UKW
LW
F
MW
SW
IFO
CPL
PLE
GND
I ret
Viun FM
EVFM
AIFM
ViunAM
SDA2120
Block diagram
r -______________________________________-+1~1
Vs
F
01
02
__+-~3 AIAM
QJ
FM
(UKW)
VI
4
"
.c
a.
I
BS UKW
SW
MW
LW
AM
13
ref
EVAM
12
V\unAM
10
EVFM
MWfLW
5
vtunFM
6
PLE
UP
8
MSB
16
SBO SB1
20 bit latch
20
IFO
CPL
14
15
20 bit shift register
17 GND
173
SDA2120
Circuitry of inputs and outputs (schematic)
Bnnd select outputs (BS)
IqL
AM/FM
Amplifier
inputs
? V~
? Vs
,....---0
Vtu1r
EV
Vret
AM/FM
T
20PF
Chnrge
Vs
Vs
pump
Vs
~
Vs
BS
JlDOWN
1fup
AI
.r----:-
L __
174
To the
n.chnrge pump
SDA2120
Test circuit for residual ripple of the FM tuning voltage
Serial interface to the
~C
Current multiplication
factor H =1
IFO
(Pl
.5V
PlE
Vs
Rr
BB 304
fi-1
Oscillator
I ref
FM
SDA 2120
+5V
470
~F
01
lOkI?
68kl?
HnF
140kl?
TT1~F
=4MHz
02
T l0nF
~
lBpF
AIFM
T lnF
10kQ
FM post filter
2.2kQ
T
oj
47nF
GND
0) The mentioned filter constants are only approximate values.
They have to be matched to the actual tuner by the user.
175
SDA2120
Test circuit for charge pump output current
$eriQI interfQce to the lie
+5V
AI I. chQr e pump
SDA 2120
f'
Ql
OJ
FM
Q2
4HHz
2.2kr!
!v
100nF
AM
R
GND
I I
,12.5v
To activate the "charge pump", there must be a difference between the frequency of the
AM/FM inputs and the frequency of the !le.
176
SDA2120
Application circuit
470~F
Serial interface to the ~C
16
FM IF
IFD
CPL
PLE
r-_~~_ _~_ _ _ _ _~4 FM
10nF
V. 6
s
+12V
1)
H_---._ _ _-.:2:.:. j1 AI FM
UKW
I ref
18
FM tuner
FM filter
F 11
SDA 2120
L-~_ _+-~
Tuning voltage FM
AM IF
0.1
r--~I~---4-----~AM
100nF
8
~4MH;
+12V
0.2 7
SW,MW,
LW
SW/MW/LW
18pF
.~_~o-_ _ _3~ AI AM
tuner
AM filter
Tuning voltage AM
BS 1-4 NC GND
4
9,10,12, 13
Band selection
2
17
4
Band select switch
1) Double FET operating amplifier: MC 34002, CA 3240, TL 082, LF 353 or similar types.
2) The filter values must be matched to the actual tuner by the user.
177
178
Static LED Display Driver with Blanking Capability
SDA2131
DIP 22
The SDA 2131 includes a static display driver for 16 LEDs featuring a 10 mA output current,
each. The serial data interface enables a simple connection to the microcomputer.
Features
•
•
•
•
Integrated load resistances, thus few external components are required
Number of LEDs software-selectable
Blanking capability through DC-controlled input
Simple connection to a microcomputer
Maximum ratings
Supply voltage range
Input voltage range
Output voltage range (outputs blocked)
(pins 1 to 3, 9 to 16, 18 to 22)
Input voltage C range
Junction temperature
Storage temperature range
Thermal resistance (system-air)
-0.3 to 7
-0.3 to 7
-0.3 to 7
V
V
V
V
Tstg
-0.3 to Vs
150
-40 t0125
RthSA
65
K/W
Vs ?
V[4.5.6
VqH
VC8
7j
°C
°C
The anode voltage of the LEDs and the number of simultaneously active outputs should
be selected so that a total power dissipation of 800 mW in the IC is not exceeded.
Operating range
Supply voltage range
Ambient temperature range
4.5 to 5.5
1
o to 70
179
SDA2131
Characteristics (VS = 5 V;
Tamb
= 25°C)
typ
max
157
10
15
mA
IS7
2.5
3.5
mA
1.4
2.0
1
V
IlA
10
IlA
12.5
mA
10
IlA
2.7
0.9
V
mA
min
Supply current (all lEDs ON)
(Iq =10 mAl
Quiescent current
(lq =0; e = "l")
. Switching voltage
H input current
(VH=5.5 V)
l input current
(VL =0.4 V)
Output current (Vq = 2.9 V)
(pins 1 to 3, 9 to 16,18 to 22)
Ouiput ieakage current (Vq = Vsl
(pins 1 to 3, 9 to 16,18 to 22)
SWitching voltage e
H input current e
(VHB =5 V)
l input current e
(VLB=OV)
H input current e
(at switching voltage)
Switching times
elK (pin 5) H pulse width
l pulse width
D (pin 4)
E (Pin 6)
A
Set-up time
Hold tiJoe
Set-up time
Hold time
H pulse width
l pulse width
Set-up time
Hold time
delay time
VS4. 5,6
I H4 ,5,6
0.8
-h4,5,6
Iq
8
10
IqJ
VSB
1.5
IHB
2.1
0.6
IlA
-hB
15
IHB
tHCLK
tLCLK
tSCLK
thCLK
tso
thO
tHE
tLE
tSE
thE
tA
1
2
0
0
0.5
0.5
50
0.5
1.5
1
10
IlA
Ils
Ils
Ils
Ils
Ils
Ils
Ils
Ils
Ils
Ils
Ils
Circuit description
A serial interface consisting of data input D, enable input E, and clock input ClK, to connect
the IC to a microprocessor. The 16 bit information (UH" at input D corresponds to the current
flow at outputs A 1 to A 16) is loaded into a 16 bit shift register via the serial data input,
beginning with lSB. Data transfer is initiated by the Hl slope of the clock pulse at ClK.
The data transfer D can take place only during the H state of the enable input E. A buffer
accepts the data from the shift register during the Hl slope of the enable input. The buffer
directly drives the outputs A 1 to A 16.
The output is limited by an internal resistor of 290 Q.
Through input C the outputs can be switched off (VCB = 0 V).
The inputs D, E, and ClK, and the input C are TTL-compatible.
180
SOA 2131
Block diagram
16 outputs
AL A16
+
Vs
7
16
Blanking ( _8-1-c::::J--t
input
Data
0
Enable
E
(lock
CLK
4
6
5
17
GND
Internal ci rcuitry
of an output A:
A
250Q
40Q
181
SOA 2131
Pulse diagram
Acceptance in memory
and displays
Enable of data input
~I
~,
L
EJ
: LSB
MSS:
: L
I
1
H
o i'L..LJ
:
:,
I
("I
1/
I
I,
I
!~
H
I
I
J
I
i
~
I
:
L
I
I
~
C_"--tJ I---l ~
: t '
I
[
H
I,
[,
I
i~ ! !:
,........ ,........
I
L
,
,
I
---l
,i
I
--I
H
L
I
,
~
L H
I
I
I:
:,
l :
i
!
:
--J
"
,
I
--'
I
--J
I
L
L
I
I
I
!
rtr'
! !
I
--.J
I
~
w u u u u u u u u
I
L
I
L
I
I
I
1
I
,
iii
I
I
I
--1
----1
-------'
H
i
I
I
Ll
I:
: I
:I
fTl-++_
i,
;:,
I
I I
I
r ,
u~
First shifted bit
f'
Last shifted bit
Memory contents after the falling edge of E
LSB
MSB
LHHLLHHLLHLLLLHL
The first information shifted to D with eLK is displayed at A 1.
Pulse diagram
~------------------~------~E------------~~
------------------------------------------\
Al ~ A16
182
SDA2131
Application circuit 1
2 digit 7 -segment display
+5V green LEOs: without series resistor
red LED s : series resistor 3.3 Q
fl/
t'
,-, ,-,
C•. C•.
8
Vs
3
to ~p
ALAS
39kl1
A9 ... A16
SDA 2131
0
E
[LK
22IJF/16V
Application:
Display characters are blanked
while a TV set is turned on
Application circuit 2
Point display (1 of 16 diodes illuminated)
+5V
, ~------------~ 17~
16 LEOs
Vs
3
0
A1
A16
SDA 2131
E
[LK
1
183
SDA 2131
Pin configuration
Pin No.
Symbol
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A14
A15
A16
0
CLK
E
Vs
C
A1
A2
A3
A4
A5
A6
A7
A8
GND
A9
A10
A11
A12
A13
Output 14 for LED cathode
Output 15 for LED cathode
Output 16 for LED cathode
Input for data
Input for clock
Input for enable
Supply voltage
Input for blanking
Output 1 for LED cathode
17
18
19
20
21
22
184
("\I ....... I.~ I") oJ ....... 1 L'1""It. __ ... 1-_...1_
_"" .. ,..,UL '" IVI L.L..LI l"ClllIUUt:
Output 3 for LED cathode
Output 4 for LED cathode
Output 5 for LED cathode
Output 6 for LED cathode
Output 7 for LED cathode
Output 8 for LED cathode
Ground
Output 9 for LED cathode
Output 10 for LED cathode
Output 11 for LED cathode
Output 12 for LED cathode
Output 13 for LED cathode
SDA2208-2
IR Remote Control Transmitter with IR Diode Driver
DIP 20
The SDA 2208 is designed as a remote control transmitter for direct driving of infrared
transmitter diodes. The instructions are generated by an input matrix (Le. keyboard) in the
form of biphase codes. Distributed over 8 levels, there are a max. of 512 instructions available.
Maximum ratings
Supply voltage range
Matrix rows
Matrix columns
Programming pin (PPIN)
Oscillator input (ClKI)
Infrared output (IRA)
inhibiled
in operation
Junctiofl temperature
Storage·temperature range
Thermal resistance
(system-air)
Vs
Vrow
Veol
Vpp
lliose
-0.3 to 10.5
-0.3 to Us
-0.3 to Us
-0.3 to Us
-0.3 to 2
V
V
V
V
V
Vq
Vq
7j
Tstg
-0.3 to 10.5
-0.3 to 8
150
-40 to 125
V
V
°C
°C
RthSA
60
K/W
4 to 10
o to 70
430 to 530
V
°C
kHz
Operating range
Supply voltage
Ambient temperature
Oscillator frequency
Characteristics
Vs =7 V; TA =25°C
min
Current consumption")
transmitting phase
stal1dby mode
Is
Is
Output current IRA
2V15 pF
CL=60 pF
Input level
(" Input sensitivity")
70 MHz
80 MHz
120 MHz
250 MHz
600 MHz
1000 MHz
1100 MHz
1200 MHz.
1300 Mhz
Is
typ
max
23
29
mA
1.2
dBm
dBm
Vq
0.5
0.35
VI
-26
-27
-30
-32
-27
-27
-27
-21
-15
dBm
3
-In __
~
UDIII
"3
dBm
dBm
dBm
dBm
dBm
dBm
dBm
3
3
3
3
3
3
Circuit description
The pre-amplifier of the IC features symmetrical push-pull outputs. If one of the signal inputs
is in an asymmetrical driving mode the other input should be grounded by a capacitor 1.5 nF)
with low series inductivity.The pre-scaler of the IC consists of several status controlled master
slave flip flops with a 1:64 scaling rate.
The asymmetrical push-pull outputs of the pre-scaler have been designed with an internal
resistance of 50011 each. The DC voltage level of the outputs is connected to the supply voltage
Vs (output "high" = Vs). The typical shift is 1 Vpp.
r
Pin configuration
Pin-No.
Function
1
N.C.
Input 11
Input 12
Ground
N.C.
Output 02
Output 01
Supply voltage Vs
2
3
4
5
6
7
8
196
Pre-scaler 1 :64 for 1 GHz with low current consumption
SDA 2211
Block diagram
.....
C\J
a
a
oE
o..c
LOO
oE
O..c
LOO
""C
c:
:::I
0~
(.!J
'
T'""
',CE
VH=5.25 V
min
typ
max
4.75
5
5.25
3
0.8
2.4
V
mA
V
V
10
IlA
Data output D (open drain)
VL =0.8 V
VH=5.25 V
IL
IH
0.5
mA
10
IlA
CiocK puise H
before/after CE transition
before/after 0 change
~
2.5
<1>L
<1>L
<1>L
5
5
OH
OL
2.5
2.5
LIt
2.5
ter
twr
10
10
60
2.5
Data D
before/after trailing edge
Time between rising and
trailing edge
CE referenced to 0
Erase time
Write time
20
20
Data transfer and chip control
The total data transfer between the conlrol processor and the FPROM requires three lines,
each of which has several functions:
a) Data line D
-
bidirectional serial data transfer
serial address input
clocked input of control information
direct control input
b) Clock line
- data, address, and control bit input
- data output
- start of readout with transfer of data from memory into shift register and/or start of
data change during reprogramming
c) Chip enable line CE
- chip reset and data input (active high)
- chip enable (active low)
202
SDA2506
Prior to chip enable, the data, address, and control information is clocked via the bidirectional
data bus. During the reprogramming and read process, this data is retained in the shift
register up to the second clock pulse. The following data formats must be entered:
a) Read memory: one a-bit control word comprising:
- 7 address bits AO to A6 (AO goes first as LSB)
- 1 control bit, SB = "0", after A6
b) Reprogram memory: (erase and/or write operation)
16-bit input information comprising:
- a bits, DO to D7 new memory information (DO goes first as LSB)
- 7 bits, AO to A6 address information (AO as LSB goes first after 07)
- 1 bit, control information, SB = "1 ", after A6
Read (figure 1)
Subsequent to data input and with SB = "0", the read process of the selected word address
is started when CE changes from "1" to "0". The information on the data line is not effective
during chip enable.
With the first clock pulse after CE = "0", the data word of the selected memory address
is transferred into the shift register. After the first tLOWmin
tHO;STA
tLOwmin
tHIGH min
tSU;STA
t>tHIGHmin
4.7 ~s
4 ~s
t> tLOwmin
tR
tF
t>O ~s
t>250 ns
t<1 ~s
t<300 ns
tSU;STO
t> tLOWmin
tHO; OAT
tsu; OAT
The minimum time the bus must be free before a new transmission
can start
Start condition hold time
Clock LOW period
Clock HIGH period
Start condition set-up time, only valid for reported start code
Data hold time
Data set-up time
Rise time of both the SDA and SCL line
Fall time of both the SDA and SCL line
Stop condition set-up time
Note:
All values refer to IIIH and IIIL levels.
211
SDA2516
Control word input read
a) complete (with word address input)
[ST I
CS/E
IAsl
WA
IAsl ST
CS/A
DA
IAs\
IAml
n Bytes
t
DA
\1
I
11
I
SP
Last Byte
Automatic Incrementation
of the Word Address
~
b) shortened
(read starts with last
used word address)
ST
CS/A
DA
IAsl
IAml
n Byies
DA
Last Byte
Control word input program
ST
CS/E
IAsl
WA
(reprogramming starts
after this stop condition)
IAsl SP
DE
IAsl
Control word table
2
3
4
5
6
7
8
9
(Acknowledge)
1
1
0
0
CS2
eS2
A3
03
03
eS1
eS1
A2
02
02
eso
eso
A1
01
01
0
0
A6
06
06
0
0
A4
0
X
1
1
A5
05
05
through
through
through
through
through
Clock No.
CS/E
eS/A
WA
OE
OA
07
07
04
04
1
AO
00
00
Control word input key:
eS/E
eS/A
WA
OE
OA
00 to 07
ST
SP
As
Am
eso, eS1, eS2
AO toA6
Figure 3
212
Chip select for data input into memory
Chip select for data output out of memory
Memory word address
Data word for memory
Data word read out of memory
Data bits
Start condition
Stop condition
Acknowledge bit from memory
Acknowledge bit from master
Chip select bits
Memory word address bits
0
0
0
memory
memory
memory
memory
master
SP
Nonvolatile Memory 2 Kbit
E2Prom with PC Bus Interface
SDA2526
Preliminary Data
DIPS
General characteristics
• Word-organized reprogrammable nonvolatile memory
in n-channel-floating-gate technology (E2PROM)
• 256 x 8 bit organization
• Supply voltage 5 V
• Serial 2-line data bus for data input and output (Fe bus)
• Reprogramming mode, 15 ms erase/write cycle
o Reprogramming by means of chip-internal control without
external control
• Data retention in excess of 10 years
• More than 10· reprogramming cycles per address
Maximum ratings*
Supply voltage range
I nput voltage range
Power dissipation
Storage temperature range
Thermal resistance
(System-air)
Vee
Vi
Pv
Tstg
RthSA
-0.3 t06
- 0.3 to 6
50
- 40t0125
V
V
mW
100
KIW
°C
Range of operation
Supply voltage
Ambient temperature
Vee
Tamb
4.75t05.25
o to 70
V
V
• not valid for input CS21TP in Test mode - full deletion
213
SDA2526
Characteristics
min
5.25
V
mA
V
V
t'H
1.5
Voo
10
p.A
tal
tOH
3.0
10
mA
jJ.A
V
V
t'H
0.2
Voo
100
p.A
'SCl
100
kHz
30
10
ms
pF
50
13
V
Voo
too
Inputs SCUSDA
Low level
High level
High current (V,H
V,l
V,H
Output SDA
Low current (Val 0.4 V)
Leakage current (VOH
VOo max)
=
=
Inputs CSO, CS1, CS21TP
High current
Clock frequency
Reprogramming duration
(erasing and writing)
Input capacity
Full deletion duration
(test mode full selection)
Condition
V,l
V,H
4.75
3.0
4.5
15
t prog
C,
tED
Vcs·"lTP
11
Pin Configuration
Pin
Symbol
Function
1
2
3
4
Ground
5
6
7
8
SDA
SCL
(Ground)
Chip select input
Chip select input
Chip select!
Test operation control
Data line }
Clock line
PC bus
N.C.
Supply voltage
214
csa
CS1
CS2!TP
Voo
max
8
Supply voltage
Supply current
= VOO max)
typ
12
ms
SDA2526
FC bus interface (fig. 1 and 2)
The FC bus has been designed as a bidirectional2-line bus fortransferring data between different
integrated circuits. Toward this end, the component is comprised of a serial data line SDA and a
serial clock line SCL. Both lines require an external pull-up resistor to Voo (open drain output
stages).
The different operational stages of the FC bus are described in fig. 1. In the quiescent condition
both output lines SDA and SCL are on the logical potential "1", inhibiting the output stages. As
long as SCL remains on "1'; changes in the information on the data bus indicate the beginning
and/or the end of data transfers between two integrated circuits. During actual data transfers,
however, information on the data bus will change only if the clock output SCL lies on "0:' With
respect to SDA, changes provide either a start condition (from "1" to "0'') or a stop condition (from
"0" to "1"). The information on SDA continues to be valid as long as SCL remains on "1':
In conjunction with the FC bus system, it is possible to operate the memory in a dual capacity
as receiver and transmitter (slave receiver(listener) or slave transmitter(talker». Between a start
and a stop condition, information is always transmitted in byte-organized form (8 bits each).lfthe
chip select conditions have been met, the memroy places the SDA line on "0" between the trailing edge of the eighth transmission pulse and the ninth acknowledge clock pulse to signal reception
confirmation. Whiledata is being transmitted, the data output will change into a high impedance
mode, if the master receiver leaves the SDA output on "1" during the acknowledge clock pulse.
The signal process required forthe operation of the FC bus has been summarized in fig. 2 (highspeed-mode).
Control functions of the FC bus
Via the 12C bus the memory is controlled by the controller (master) during two operating modes:
a) read-out cycle and b) the reprogramming cycle, including the erasing and writing of a memory
address. In both operating modes the controller functioning as transmitter has to provide 3 bytes
and an additional acknowledge clock on the bus after the start condition.
In addition tothe standard read-out cycle, a rapid read-out mode has been provided which enables
the reading of data immediately after the salve addresses have been entered. In order to read the
memory at least 8 additional clock pulses are required prior to the stop condition. With respect
to programming, the active programming process will be started by the stop condition if the data
has been entered.
With a3 bit chip select word (CSO, CS1, CS2), which can be coded externally, it is possible forthe
user to individually address 8 memory components connected in parallel. The chip select requirements have been met, when the chip select bits CSO, CS1, CS2 of the external chip select
word logically correspond with the chi p select information made available via the 12C bus signal.
215
SDA2526
Memory read-out
The first two control words are entered during 18 SCL pulses. Subsequently, the memory is adjusted for read-out by resetting the start condition and by entering a third control word. During the
ninth acknowledge clock, the information stored in the memory is transferred in parallel mode
to the interal data register. Subsequent to the trailing edge of the acknowledge clock, the data
output is in the low impedance mode, and the first data bit can be read. With each shift clock an
additional data bit is forwarded to the output. After reading a byte, the internal address counter
is automatically increased by 1 through the "acknowledge" of the selected listener. In this manner, a random number of memory locations can be read in successive order. In conjunction with
address 127 an overflow to address 0 is initiated. With the stop condition the data output returns
to the high impedance mode, and the internal control logic of the memory is reset from the read
state into the quiescent state.
rv~emCiri
repruyrflfnfflirlQ
The reprogramming cycle of a memory word is comprised of an erase and write process. During
the erase process, each bit of the selected word is.brought into the "1" state, while "0" states are
generated during the write process based on the information in the internal data register, that is
to say, in accordance with the third entered control word.
Afterthe 27th and last clock of the control word input, the active programming operation is started
by the stop condition. Regulated via internal chip control, the active programming operation can
be interrupted by renewed addressing via SCL and SDA.
The duration of the reprogramming mode is based on spreads between units and data samples.
Therefore, with standard supply voltages, the erase/write process may extend over max. 30 ms or,
more typically, 15 ms. After the data word has been entered without write request (write request:
data bit in the data register has been set on "0'), the write mode is suppressed, resulting in a shortened programming time (refer to rapid read-out mode). Should in an already erased memory address (all bits are on logic 1) be subsequently programmed, the erase mode will also be suppressed, leading again to a shortened reprogramming time.
216
SDA2526
Switch-on mode and chip reset
After the supply voltage Voo has been connected, the data output will be in the high impedance
mode. As a rule, the first operating mode to be entered should be the read-out process of a word
address, since the chip does not accept the reprogramming mode immediately after activation
of the supply voltage. Subsequent to data output and the stop condition, the intemal control logic
is reset. However, in the case of a subsequent active programming operation, the stop condition
will not reset the control logic.
Test mode total erase
The address register is loaded with address 0, the data register with FF(hex) by entering the control
word "programming". However, immediately priorto generating the stop condition, input CS2rrp
is connected from OV to 12V. The subsequent stop condition triggers a full deletion procedure which
has to be performed under the component address 0 (CSa = L, CS1 = L, CS2 = L). When the full
deletion procedure is completed, input CS2rrP must be connected from 12V to OV again.
217
SDA2526
Operational states of the 12C bus
,-----------------------,
:
I
I
SDA
I
I
SCL
,
IL _______________________ JI
Start
Data Transmission with Acknowledge Bit
Stop
Figure 1
Timing conditions for the 12C bus (high-speed mode)
SDA
SCL
SDA
tsu, SIA
tsu, SID
Figure 2
t> tLQWmin
tHD;STA
t>tHIGHmin
tLOWmin
4.7 Ils
tHIGH min
41ls
tSU;STA
t> tLQWmin
tF
t>O Ils
t>250 ns
t<1 Ils
t<300 ns
tSU;STO
t> tLOWmin
tHD;DAT
tSU;DAT
tA
The minimum time the bus must be free before a new transmission
can start
Start condition hold time
Clock LOW period
Clock HIGH period
Start condition set-up time, only valid for reported start code
Data hold time
Data set-up time
Rise time of both the SDA and SCL line
Fall time of both the SDA and SCL line
Stop condition set-up time
Note:
All values refer to
218
\-IH and \-IL levels.
SDA 2526
----------------------------------------------------------Control word input read
a) complete (with word address input)
[~il __~~=:G_sL_1_w_A---------lI_AS-'-I_s_T-LI_C_S/_A----"---IA_s_It:::==D=A=:+-IAml
n Bytes
SP
DA
I
t-
Last Byte
Automatic Incrementation
of the Word Address
~
b) shortened
(read starts with last
used word address)
ST
CS/A
DA
IAsl
IAml
n Bytes
DA
11
I
SP
Last Byte
Control word input program
[ST
[~S/E
IASI
WA
DE
IASI
IAsl
(reprogramming starts
after this stop condition)
SP
Control word table
Clock No.
CS/E
CS/A
WA
DE
OA
I
1
1
X
07
07
2
3
4
5
6
7
8
9
(Acknowledge)
0
0
A6
06
06
1
A5
05
05
0
0
A4
04
04
CS2
CS2
A3
03
03
CS1
C81
A2
02
02
CSO
CSO
A1
01
01
0
1
AO
00
00
0
0
0
0
0
through
through
through
through
through
memory
memory
memory
memory
master
Control word input key:
CS/E
CS/A
WA
OE
OA
00 to 07
ST
SP
As
Am
CSO, CS 1, CS2
AO to A6
Chip select for data input into memory
Chip select for data output out of memory
Memory word address
Oata word for memory
Oata word read out of memory
Oata bits
Start condition
Stop condition
Acknowledge bit from memory
Acknowledge bit from master
Chip select bits
Memory word address bits
Figure 3
219
220
TVPLL
SDA3112
DIP 18
The SDA 3112 is produced in ASBC technology. In connection with VCO (tuner) and a fast prescaler
(prescaler factor 1:64), it represents a digitally programmable PLL for a TV set with frequency synthesis tuning. The PLL enables a crystal exact adjustment of the tuner oscillator frequencies for
the TV ranges band III1IVN in 125 kHz resolution (frequency range: 128to 2000 MHz). A serial interface enables a simple connection to a microprocessor. This microprocessor loads the prescaler
and band selection outputs with the appropriate information. At the output LOCK the PLL supplies a state information (locked/released).
Features
• No need for an external integrator
• Noise free telegram transmission
• Integration time constant controlled by software
• Microprocessor compatible
Maximum ratings
Supply voltage
Inputs
Q1, Q2, I ref
IFO, CPL, PLE
PLE
F,T
Outputs
PD
UD
BS1~BS5
--
Vs
-0.3 to 7.5
V
VI
-0.3
-0.3
-0.3
-0.3
V
V
V
V
VI
VI
VI
Va
Va
IaL
Va
to
to
to
to
Vs
Vs -to.5
7.8
Vs + 0.5
-0.3 to Vs
-0.3 to 33
-7
-0.3 to 16
-1 to 5
V
V
mA
V
mA
LOCK
Internal pull-up RL = 3 k(l
Junction temperature
Storage temperature range
Ia
Tstg
140
-55 to 150
DC
DC
Thermal resistance (system-air)
RthSA
80
K/W
Vs
4.5 to 5.5
32
1024 to 16383
80
V
fF,ff
N
RI
VD
0.3 to 33
V
Tamb
Ot085
DC
Tj
Operating range
Supply voltage range
Input frequency
Divider ratio
Resistance for, I ref
I ref = (Vs -o.8)RI
Tuning voltage range
open collector
Ambient temperature range
MHz
kO
221
SDA 3112
Characteristics (VS =
5 V ± 0.5 V;
Tamb
Supply current
Crystal frequency Series C = 18 pi
Signal inputs FiF
Input voltage
Input current
V 16 =5 V
Input sensitivity at
sine push-pull1triggering ; f= 32 MHz
Inputs (IFO, CPL, PLE)
Upper threshold voltage
Lower threshold voltage
Input current
VSH =5 V
VSl = 0.4 V
VSL= 0.8 V
Band select outputs (8S1 .... 8S5)
Reverse current
V 3H =15V
Current drain
2 V;;; V3 ;;; 15 V
Tuning section PO, UD, Iref> LOCK
Charge pump current
Ipump = 10 x Irej; RI = 120 kO; Vs = 5V
Tuning voltage
1 15L = 1.5 mA
Reverse current
V 15H =33V
Reference current
ext.R =120 kO
Output voltage
in!. RL =3 kO
II2H=-100flA
112L =100 flA
IFO, PLE
Set-up time for
release
data
Hold time for:
release
data
CPL
H pulse width
L pulse width
222
=
0 to 70 DC)
Is
min
typ
max
15
22
4
35
fq
V16H
V16l
3.92
3.8
1 16
V 16
120
VSH
VSl
2.4
mA
MHz
Vs + 0.12 V
V
Vs
50
p.A
1200
mVpp
0.8
V
V
ISH
ISl
tSL
8
-550
-500
flA
flA
I3H
10
flA
p.A
I3H
0.5
3
mA
1 13
±250
±550
flA
V 15L
0.3
V
I 15H
20
flA
40
flA
114
30
V12H
4.5
V12L
V
0.7
V
tVE
tVD
2
2
fls
fls
tHE
tHD
2
2
fls
fls
tCH
teL
2
2
fls
fls
SOA 3112
Circuit description
Triggered by the ECI inputs FIF a switchable32133counteroperates as a 14 bit synchronous prescaler
in the dual modulus method by combining it with a5 and 9 bit programmable synchronous counter.
In this combination the5 bit counter controls the switch·overfrom 32to 33(block diagram 1). Dividing
ratios of N= 1024 to 16383 are possible.
The 18 bit deep shift register latch is subdivided into 14 bits for storing the dividing ratio N, as well
as 1 bit for selecting the pump current and 3 bits for controlling the5 band selection outputs.
The telegram is inserted over the serial data input IFO with the H·L slope of the shift clock CPL,
when the enable input is set at H. Beginning with LSB, the complement of the dividing ratio is in·
serted in binary code, then the select bit 214 for the pump current and the band selection control
bits 215 , 216 , 2" (please refer to enclosed table).
An integrated control circuit checks the world length (18 bit) of the data telegram. The 18 bit latch
accepts the data from the shift register during the L state of the enable input PLE.
A4 MHz crystal controlled clock oscillator has been integrated in the Ie. An internal reference divider
divides the output signal of the crystal oscillator(fose = 4 MHz) by 2048 resulting in 1.953125 kHz
(reference signal), providing a frequency resolution of 125 kHz by means of the asynchronous per·
manent prescaler (dividing factor 1:64).
In a digital phase detector the divided VCO input signal is compared with the reference signal.
If the falling slope of the VCO input signal appears before the falling slope of the reference signal,
the output DOWN of the phase detector will be in the H state for the duration of the phase difference. However, if above signal sequence is reversed, the output UP will be in the H state instead.
The outputs UP/DOWN control the two current sources I + and 1- (charge pump). In case both
outputs are in the Lstate, the charge pump output will be in the high impedance mode (TRI-STATE).
Information with respect to either the H or Lstate wi II be provided atthe LOCK output by the logical
"NOR" of the outputs UPIDOWN.
The output current of the charge pump (source current = drain current) is adjusted by an external
resistor between pin Iret and Vee. In addition, this output current can be generated by the control
bit forthe pump current at the same value or at a value increased by a factor of 10 (refer to enclosed table).
The current pulses generated by the charge pump are integrated into the tuning voltage by means
of an active low pass filter (on-chip loop amplifier and external RC circuit). The dc output signal
of the low pass filter is available at Vo and is used as tuning voltage for the VCo. In order to provide tuning voltages higher than Vee = 5 V, the output stage of the amplifier consists of a transistor
with an open collector. The external collector resistor can be connected to voltages up to 33 V.
=
To switch voltages higher than Vs 5 V, the band selection outputs (BS1, BS2, BS3, BS4, BS5) include current drains with open collectors. It is therefore possible to directly connect transistors
operating as band selection switches without the use of current limiting resistors (please refer
to enclosed application current).
223
SDA3112
Pin configuration
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
224
Symbol
Function
01
02
BS1
BS2
BS3
BS4
BS5
PLE
GND
CPL
IFO
LOCK
PD
Crystal
Crystal
Standard switchover output
Band selection output BS
Band selection output VHF
Band selection output UHF
Band selection output 1/111
Release input for shift register
Ground
Iref
VD
F
F
Vs
Q;hiH ,..1,...,,...(,
- ....
~
nlll~o
................ , .. 1"' ..............
inr\l.+
"'1'-''"''
Data input
Lock output
Amplifier inputlcharge pump output
Current adjustment for charge pump
Tuning voltage output
Signal input
Signal input
Supply voltage
SOA 3112
Loop-filter calculations
Loop bandwidth:
Attenuation
j/p x
= prescaler
=
=
=
=
Kvco =W
C1 X P x N
R
1/2xWRXRxCl=~
programmable divider ratio
pump current
tuner voltage characteristic
loop filter
Example for channel 47:
P = 64
N = 11520
Ip = 200 IlA
SVGO = 18.7 MHzlV
R = 33 kQ
C1 = 330 nF
= 124 Hz
fR = 20 Hz
~ = 0.675
Standard dimensioning: C2 "" C1/5
WR
Block diagram
Vs
GNO
LOCK
PO
32V
22kn
'-
t
.&
QJ
SDA 3112
F
VD
'0
QJ
5V
VI
o
.c
Tuning
voltage
0..
20.. _________________ 213
18 bit SR
~
Interface to ~p
+
memory .with
214
as decoder
iii
oa
225
SDA3112
Truth Table
"IFO" bit 214
Pump Current fp
L
H
fret
10 X fret
, "IFO" bit
2'5
2'6
217
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
=
=
Band selection outputs (L conducting,
H blocking)
BS1
BS2
BS3
BS4
BS5
L
L
L
L
H
H
H
H
L
L
L
H
L
H
H
H
H
H
L
L
H
H
L
H
L
H
L
H
H
H
L
H
H
H
L
H
H
Pulse diagram
CPL
L
(FO
I
I
Ii L H
:LSB
f---I
I
2°
First bit
226
Prescaler ratio
N= 1930
H
L
H
SOA 3112
Pulse diagram
Set-up and hold times
IFO
PLE
CPL
227
SOA 3112
Test and measurement circuits
5V
bus inputs
PLECPL IFO
18
V16
[16
10k0
16
Ii:
[17
V17
[8,10,11
8,10,11
PIN 8,10,11
17
Signal
inputs
push-pull
Test circuit 2
Test circuit 1
PIN
V
[3,4,5,6,7
3,4,5,6,7
3.4,5,6.7
Band selection
1100
Test circuit 3
228
10kll
SDA3112
Test and measurement circuits
1 kll
1 kll
115PF
4MHz
1 PIN 1
4MHz=
T '1----=-¢------------+-------4
'---i
PIN 2
18pF
Crystal oscillator
Test circuit 4
5V
f
10*I"f
120kll
lref
5 kll
I"
V"
14
33V
:;!
~
z
z
a:
a:
22kll
V,S
1'5
15
30kll
Tuning section
inputs/outputs
3kll
1'2
12
V13
V'2
In
P!
13
PIN 13
z
a:
Test circuit 5
229
SDA3112
Application circuit
Design proposal
RI = 120 kQ (/p = 35/350 f.lA)
RL = 22 kQ, R2 .. . R4 = 22 kQ
Loop filter: R = 33 kQ, C, = 330 nF, C 2 = 47 nF
Post filter (in the tuner): Rr = 10 kQ, Cr = 47 nF
~
Tuner
HH ~
lose
Vs
VSJ
4 MHz
0
RL
RI
01
F
02
F
lret
[,
LOCK
PO
'Fa
PLL IC
SDA 3112
Vtun
CPL
1ii
VS1
PLE
"'
~
i;j
"'
Rl
VHF
230
GNO
Serial interface to ~C
1.3 GHz PLL with PC Bus
SDA3202
DIP 18
Combined with a VCO (tuner), the SDA 3203 comprises a digital programmable phaselocked loop for television devices designed to use the PLL frequency synthesis tuning
principle.
The PLL provides a crystal-stable frequency for tuner oscillators between 16 ... 1300 MHz
in the 62.5 kHz raster. By including an external prescaler 1/2, the component can also
be used for synthesizing applications of up to 2.4 GHz (e.g. satellite receivers). As a result,
the resolution is doubled to 125 kHz. The tuning process is controlled via an FC bus by
the microprocessor.
Features
•
•
•
•
•
Low current consumption
Message transmission via 12C bus
4 software-controlled outputs
Cost-effective and space-saving design
Prescaler output frequency is free from interference radiation
Circuit description
Tuning section (refer to block diagram)
UHFIVHF
The tuner signal is capacitively coupled at the UHFIVHF input and subsequently
amplified.
REF
The reference input REF should be disabled by a capacitor of low series
inductance. The amplified signal passes through an asynchronous divider with
a fixed ratio of P = 8 and an adjustable divider N = 256 ... 32767. Subsequent
to this process, the signal is compared in a digital frequency phase detector
with a reference frequency fREF = 7.8125 kHz.
01, 02
This frequency has been derived from a 4 MHz crystal oscillator (pin 01, 02)
by dividing its output signal byO=512.
PO, Vo
The phase detector includes two outputs UP and DOWN which control the two
current sources 1+ and 1- of a charge pump. If the negative edge of the divided
VCO signal appears prior to the negative edge of the reference signal, the current
sourceI+ will pulsate for the duration of the phase difference. However, during the
reversed sequence of the negative edges, thecurrentsourceI-wili beginto pulsate.
If both signals are in phase, the charge pump output PD changes into the high
impedance state (PLL in lock). An active low pass filter (internal amplifier,
external output transistor at Vo, and RC combination) integrates the current
pulses as the tuning voltage for the VCO.
With the control bit 5 I the pump current can be switched between two values
per software. Through this switch-over, the control characteristics of the PLL
during lock-in can be changed, i.e. varying tuner characteristics in the various TV
bands can be adjusted.
231
SDA3202
PO .. P3
The software-controllable outputs PO, P1, P2 and P3 can drive external PNP
transistors (internal current limit) which operate as band selection switch.
P4 .. P7
The open collector outputs P4, P5, P6, P7 can be used for a variety of different
applications.
PC bus interface
SCl, SDA
Vs , GND
232
An asynchronous bidirectional data bus is used for data transfer between the
processor and the PlL. As a rule, the clock pulse is supplied by the processor
(input SCl), while pin SDA operates as input or output depending on the
direction of data flow (open collector, external pull-up resistor).
The data from the processor pass through an 12C bus control. Depending on their
function, the data are subsequently filed in registers (latch 0-3). If the bus is
free, both lines will be in the marking state (SDA, SCl are High). Each message
begins with the start conditions of SOA returning into low, while SCl remains
in High. All additional information transfer takes place during SCl = low and
the data is forwarded to the control with the positive clock edge. However, if
SDA returns to High, while SCl is in High, the message is ended since the Pll
acknowledges a stop condition.
For the following, also refer to table "logic allocation".
All messages are transmitted byte-by-byte, followed by a 9. clock pulse, while
the control returns the SDA line to low (acknowledge conditions). The first
byte is comprised of 7 address bits. These are used by the processor to select
the Pll from several peripheral components (chip-select). The 8. bit is always
low.
In the data portion of the message the 1. bit of the 1. or 3. data byte determines
whether a divider ratio or a control information is to follow. In each case, the
2. byte of the same data type or a stop condition has to follow the 1. byte.
When the supply voltage is injected, a Power on Reset circuit prevents the Pll
from setting the SDA line at low which would disable the bus.
SDA3202
Maximum ratings
Supply voltage
Output PD
Crystal Q1
Crystal Q2
Bus inpuUoutput SDA
Bus input SCL
Port output P7
Port output P6
Port output P5
Port output P4
Vs
V,
V2
V3
V4
Vs
Vs
V7
Va
Ve
Remarks
min
max
-0.3
-0.3
-0.3
-0.3
-0.3
6
Vs
Vs
Vs
Vs
V
V
V
V
V
-0.3
-0.3
-0.3
-0.3
-0.3
Vs
16
16
16
16
V
V
V
V
V
-0.3
-0.3
-0.3
-0.3
-0.3
16
16
16
16
2.5
V
V
V
V
V
2.5
Vs
5
V
V
rnA
open collector
open
open
open
open
Port output P3
Port output P2
Port output P1
Port output PO
Signal input UHFNHF
V,o
V"
V'2
V'3
Reference input REF
Output active filter Vo
Bus output SDA
V,s
V,a
14L
-0.3
-0.3
-1
Port output P7
Port output P6
Port output P5
Port output P4
IsL
hL
IsL
leL
-1
-1
-1
-1
5
5
5
5
rnA
rnA
rnA
rnA
Junction temperature
Storage tern perature range
Thermal resistance (system-air)
7j
T.'9
-40
125
125
80
°C
°C
16
5.5
80
1300
V
°C
MHz
MHz
256
32767
V,s
R'hSA
collector
collector
collector
collector
K/W
Operating range
Supply voltage
Ambient temperature
Input frequency
Crystal frequency
Divider factor
4.5
o
4
233
SDA3202
Characteristics
Vs =5 V; TA =25°C
Current consumption
Crystal frequency
Test
conditions
Test
circuit
Is
'2,3
Series capacitance 18 pF
min
typ
max
35
3.99975
55
4.000
75
4.00025
mA
MHz
Input sensitivity UHFNHF
a1S
a1S
alS
Band selection outputs PO... P3
'1S= 70 .... 500 MHz
t1S = 500 ... 1000 MHz.
'1S = 1100, MHz
2
2
2
-27/10
-24/14
-20/22
3/315
3/315
3/315
dBm/*
dBml*
dBm/*
0.7
10
1.5
I1A
mA
10
0.5
I1A
V
±300
±75
2.5
I1A
I1A
V
100
I1A
mV
5.5
1.5
50
-100
V
V
I1A
I1A
6
6
10
0.4
/LA
V
6
6
1
0.3
I1s
I1s
100
kHz
I1s
I1s
(current sinks with
internal resistcJ.nce
Leakage current
Sink current
I13H
I13L
RI =12 kQ)
V13H =13.5V
\<13H=12V
3
3
ISH
VSL
(switch with
open collector)
VSH = 13.5V
ISL =1.7mA
4
4
Port outputs P4 ... P7
Leakage current
Residual voltage
Phase detector output PO
(VS =5 V)
Charge pump current
Charge pump current
Output voltage
5 I=High; V1 =2 V
5I=Low; V1 =2 V
locked
5
5
5
±90
±22
1.5
Test modus TO = 1
PO = Tristate
\<1s=0.8V; 114 =90 I1A
V1L=OV
5
5
-500
VSH = Vs
VSL =OV
6
6
6
6
I1H
I1H
VIL
Active filter output Vo
Output current
Output voltage
I 1s
\<1s
±220
±50
Bus inputs SCL, SOA
Input voltage
Input current
VSH
VSL
ISH
ISL
3
Output SDA (open collector)
Output voltage
14H
RL=5.5kO
V4L
I4L =2 mA
Edges SCL, SOA
Rise time
Fall time
tR
tF
Shift register clock pulse SCL
Frequency
H-pulse width
L-pulse width
*) listed as mV,ms with 500
234
ts
tSHIGH
tSLOW
6
6
6
0
4
4
SDA3202
Characteristics (cont'd.)
Test
conditions
typ
Test
circuit
min
max
6
6
4
4
j.ls
j.ls
6
6
4
4
j.ls
j.ls
6
6
0.3
0
j.ls
j.ls
Start
Set-up time
Hold time
tSUSTA
tHDSTA
STOP
Set-up time
Bus free time
tSUSTO
tSUF
Data transfer
Set-up time
Hold time
tSUDAT
tHDDAT
Pin description
Pin
Symbol
Function
1
PO
2
3
4
5
6
7
8
9
Q1
Input for active filter/output for charge pump
Crystal
Crystal
Data I/O for 12C bus
Clock input for FC bus
Port output (open collector)
Port output (open collector)
Port output (open collector)
Port output (open collector)
Port output (current sink)
Port output (current sink)
Port output (current sink)
Port output (current sink)
Supply voltage
Signal input
Amplifier-reference input
Ground
Output of active filter
10
11
12
Q2
SOA
SCl
P7
P6
P5
P4
P3
P2
P1
13
PO
14
15
16
17
Vs
18
VD
UHFNHF
REF
GNO
235
m
~
8
O'l
117
Divider
1/160'1/17
P=8
2101
18 PF±
4MHZ9
31 Q2
OSC
4MHz
H
L-J I
I
Divider
~
L
I
I
GNO
;II;'
114
CL
iii'
I
cc
Dl
Vs
3
-'1/128
1/136
J+= UP
l1-Bit Main
Phase
Counter
Frequencty
7,81;: kHz
'REF
Com"",. 0'
-A-W
I~
11
PO 11
Vol18
J-=OOWN
rf
8-Bit Bus
51 SCL
41~O~
f------J
12C Bus
Control
,,
n
TO !Tristate I
PO IP1 IP2 IP3 IP4
13 112 111 110 19
8
17
16
51
en
~
Co)
~
N
SDA3202
Measurement circuit 1
14
114
o---~~~--~----------------~~--~---~
4 pF
4pF
Crystal Oscillator
to Reference Divider
01
18 PF
I
125 pA
4 MHz c::J
02
125pA
17
o---------~~---------------+--------GND
Measurement circuit 2
Calibration of signal generator
Signal
Generator
50 Q
*
6dB
Attenuation
Link
*
Q
Output
~easurement
Device
50 Q
.5V
Measurement of input sensitivity
14
1.5nF
r-------,
15
*
Signal
Generator
50 Q
Test mode: T1
*
=
High
6dB
Attenuation
Link
SDA 3202 6
17
GND
Frequency
Counter
• no cable
237
SDA3202
Measurement circuit 3
13
113 12 kQ
V13o------L~___,
valid for PO .. P3
Measurement circuit 4
valid for P4 .. P7
Measurement circuit 5
I,
~ o-~~----.
238
SDA3202
Measurement circuit 6a
Fe bus time diagram
Set-up time (Start)
Hold time (Start)
H-pulse width (Clock)
L-pulse width (Clock)
Set-up time (Data transfer)
Hold time (Data transfer)
Set-up time (Stop)
Bus free time
Fall time
Rise time
tSUSTA
tHDSTA
tHIGH
tLOW
tSUDAT
tHDDAT
tSUSTO
tauF
tF
tR
Above times are referenced to lliH and VjL values
Measurement circuit 6 b
30 kQ
SCL
Is
lS0Q
Vso--~":'--CJ---{
SDA
'Ison
V.o--CH--{
239
SDA3202
Application circuit
Tuner
f'F
free
~
1nF
fose
47~
10kQ
Vs
}------iVo
GND
PLL
SDA 3202
15V
SCl
SDA
from iJC
loop Filter
[2
[,
~
Computation for loop filter
Loop bandwidth: wR = / [p x Kveo
C, xPxN
Attenuation:
~ = 0.5 X WR x R X C,
P
N
=Prescaler
= Progr. divider
Ip
= Pump current
Kvco =Tuner slope
R,C, = Loop filter
Example for channel 47
P = 8; N = 11520; [p =100 !-LA; Kvco =18.7 MHz/V; R = 22 kQ; C 1 =180 nF
WR = 336 Hz; fn = 54 Hz; ~ = 0.67
Standard dimensioning: C 2
240
= C'/5
SDA3202
Description of function, application and circuit
Logic allocation
A = Acknowledge
MSB
Address byte
0
0
0
0
0
A
Prog. di)lider
byte 1
0
n14
n13
n12
n11
n10
n9
n8
A
Prog. divider
byte 2
n7
n6
n5
n4
n3
n2
n1
nO
A
51
T1
TO
0
A
P6
P5
P4
PO
A
Control info
byte 1
P7
Control info
byte 2
P3
P2
P1
Divider ratio:
N =16384x n14+8192 x n13+4096 x n12+2046 x n11 +1024 x n10+512x n9+256xn8+
+ 128 x n7 + 64 x n6 + 32 x n5 + 16 x n4 + 8 x n3 + 4 x n2 + 2 x n1 + nO
Band selection:
P3 ... PO = 1
Current sink is active
Port outputs:
P7 ... P4 = 1
Open collector output is active
Switch-over of pump current:
51
= 1
High current
Test mode:
T1,TO
T1
TO
=0,0
=1
=1
Normal operation
P6 = 'REF; P7 = Cy
Tristate charge pump
241
SDA3202
Pulse diagram
- - - - Addressing--------c/-ACK-I-1. Byte-I-ACK-I-2. Byte-/-ACK-t-3. Byte-I-ACK-I-4.Byte-I-ACK-1
,-----,C,-- ~
C
~
C
r= ~
~
I
JL..rlJL JL..rlJL JL..rlJL..JlJU
START 1
3
4
5
6
MESSAGE SAMPLES
Start-Adr-Tv1-Tv2-St1-St2-Stop
Start-Adr-St1-St2-Tv1-Tv2-Stop
Start-Adr-Tv1-Tv2-St1-Stop
Start-Adr-St1-St2-Tv1-Stop
Start-Adr-Tv1-Tv2-Stop
Start-Adr-St1-St2-Stop
Start-Adr-Tv1-Stop
Start-Adr-St1-Stop
Start
Adr
Tv1
Tv2
St1
St2
Stop
242
= start condition
= addressing
= divider ratio 1. byte
= divider ratio 2. byte
= control word 1. byte
= control word 2. byte
= stop condition
9
8
9
8
9
8
9
9 STOP
1.3 GHz PLL with 3-Wire Bus
SDA3203
DIP 20
Combined with a VCO (tuner), the SDA 3203 comprises a digital programmable phaselocked loop for television devices designed to use the PLL frequency synthesis tuning
principle.
The PLL provides a crystal-stable frequency for tuner oscillators between 16 ... 1300 MHz
in the 62.5 kHz raster. By including an external prescaler 1/2, the component can also
be used for synthesizing applications of up to 2.4 GHz (e.g. satellite receivers). As a result,
the resolution is doubled to 125 kHz. The tuning process is controlled via a 3-wire bus
by the microprocessor.
Features
• Low current consumption
• Message transmission via a 3-wire bus
• 4 software-controlled outputs
• Cost-effective and space-saving design
• Prescaler output frequency is free from interference radiation
243
SDA3203
Circuit Description
Tuning section (refer to block diagram)
UHFIVHF
The tuner signal is capacitively coupled at the UHFIVHF input and subsequently
amplified.
REF
The reference input REF should be disabled by a capacitor of low series
inductance. The amplified signal passes through an asynchronous divider with a
fixed ratio of P = 8. An anti-oscillation circuitry prevents the first divider stage
from oscillating when the input signal is missing. As a result, the PLL maintains
the correct control direction should the tuner oscillation be terminated.
Subsequently, a switchable 16/17 counter is activated. The combination of this
counter with a 4-bit and 10-bit programmable counter provides an adjustable
divider operating in the dual modulus mode. The A-bit cou"ter drives the switchover from 17 to 16. Divider ratios of N = 256 ... 16383 are possible. The divided
signal is compared in a digital frequency phase detector with a frequency
'REF = 7.8125 kHz. This frequency has been derived from a 4 M Hz crystal oscillator
(pin 01, 02) by dividing its output signal by Q = 512.
01,02
PO, Vo
The phase detector includes two outputs UP and DOWN which control the current
sourcesI+ and 1- of a charge pump. If the negative edge of the divided VCO signal
appears prior to the negative edge of the reference signal, the current sourceI+wili
pulsate for the duration of the phase difference. However, during the reversed
sequence of the negative edges, the current source I-will begin to pulsate.
If both signals are in phase, the charge pump output PO changes into the high
impedance state (PLL in lock). An active low pass filter (internal amplifier, external
output transistor at Vo, and RC combination) integrates the current pulses as
the tuning voltage for the VCO.
P1 ... P4
The software-controllable outputs P1, P2, P3 and P4 drive the external PNP
transistors (internal current limiting) which operate as band selection switch.
TVSAT
In the TVSAT mode (pin TVSAT = 0 V), the message bit for P1 becomes the
15. divider bit providing divider ratios of N = 256 ... 32767.
3-wire bus interface (refer to description of functions)
DATA
CLOCK
ENABLE
Via the serial data input DATA the message is read into an 18-bit deep shift
register with the positive edge of the CLOCK supplied by the processor when the
ENABLE input is also in High. To further ensure the prevention of interference
products, a format control discards all messages which exceed eigtheen clock
pulses during the Enable-High cycle.
Beginning with the MSB, the four band selection control bits for the port outputs
and the divider ratio are inserted in binary code. An 18-bit latch accepts the data
from the shift register with the negative edge of the Enable pulse.
244
SDA3203
TEST1
kHz 62.5
During standard operation TEST1 = Low an eight-fold reference frequency
62.5 kHz is present at pin kHz 62.5 During test operation TEST 1 = High, a distiction is made between test mode 1 (ENABLE = Low) and test mode 2 (ENABLE
=High).
DATA
CLOCK
kHz 62.S
Shift data
Output progr. divider
Input phase detector
var. frequency
Shift clock
Output ref. divider
Input phase detector
ref. frequency
62.5 kHz
62.5 kHz
1/128 (fixed)
Operating mode
Standard operation
Test mode 1
Test mode 2
Maximum ratings
Supply voltage
Test input TEST1
ENABLE
DATA
CLOCK
Vs
V,
V2
V3
13
V4
14
V6
V7
Vg
V10
V"
V'2
V'3
V14
V's
V20
V
7j
Crystal Q1
Crystal Q2
Output active filter UD
Output charge pump PD
Port output P1
Port output P2
Port output P3
Port output P4
Signal input UHFIVHF
Reference input REF
Output 62.5 kHz
Junction temperature
Storage temperature range
Tstg
Thermal resistance (system-air)
RthSA
min
max
-0.3
-0.3
-0.3
-0.3
Vs
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-40
6
125
125
V
V
V
V
rnA
V
rnA
V
V
V
V
V
V
V
V
V
V
V
°C
°C
60
K/W
5.5
70
1300
4
32767
V
°C
MHz
MHz
6
6
3
6
3
Vs
Vs
Vs
Vs
16
16
16
16
3
3
Vs
Operating range
Supply voltage
Ambient temperature
Input frequency
Crystal frequency
Divider factor
Vs
TA
t'5
t6.7
N
4.5
0
16
256
245
SDA3203
Characteristics
Vs =5 V;
TA =25°C
Current consumption
Crystal freque,ncy
Test
conditions
Test
circuit
Vs=5V
Series capacity
18 pF
Is
f 6 •7
min
typ
max
20
50
70
4
mA
MHz
3/315
3/315
3/315
dBml*)
dBml*)
dBml*)
V
10
1.5
IJ,A
mA
±220
2.5
0.2
IJ,A
V
IJ,A
Input sensitivity UHFNHF
=80-100 MHz
=100-1000 MHz
f15 =1300MHz
UHFNHF and REF
not connected
a15
a15
a15
Input dc voltage
f15
f15
V15
2
2
2
2
-24/14
-27/10
-15/40
2
Band selection outputs P1 ... P4
Leakage current
Sink current
IllH
IllL
(current sinks with
internal resistance
RI = 12 kQ)
V,lH=13.5V
V11L = 12V
3
3
0.7
1.0
Vs=5V
lock in
lock in
lock in
5
5
5
±90
1.5
-0.2
±150
Phase detector output PO
Pump current
Output voltage
Leakage current
110
V10
110
Active filter output Vo
Output current
19
I
Vo =0.8 V
I 5
I 500
IIJ,A
Test input TEST1
Input voltage
V1H
V1L
Input current
I1H
V1H =5V
V1L =OV
IlL
6
6
6
6
3
Vs
0.8
50
-100
V
V
IJ,A
IJ,A
0.4
5.5
V
V
IJ,A
5.5
200
V
IJ,A
Test outputs CLOCK, DATA
(open collector)
Output voltage
Leakage current
V2L
V2H
12H
12L =1 mA
V2H =5V
6
6
6
I
10
I
Output 62.5 kHz
(current sink with open collector)
Output voltage
Output current
0) listed as mV rms with 50 Q
246
V20
120
I
4
4
0.4
100
=.
SDA3203
Characteristics (cont'd.)
Bus inputs CLOCK,
DATA, ENABLE
Input voltage
Test
conditions
Test
circuit
min
3
12H
12L
V2H =5V
V2L =OV
6
6
6
6
tSUDAT
V2H
V2L
Input current
typ
max
Vs
0.8
50
-100
V
V
iJ.A
iJ.A
Data transfer
Set-up time
Hold time
tHDDAT
DATA
DATA
6
6
2
2
iJ.s
iJ.s
CLOCK
H-pulse width
tHIGH
CLOCK
6
2
iJ.s
tSUEN
ENABLE
ENABLE
6
6
ENABLE
Set-up time
Hold time
tHDEN
I~ I
iJ.s
iJ.s
Pin description
Pin
Symbol
Function
1
2
3
4
5
6
TEST1
ENABLE
DATA
CLOCK
N.C.
01
02
N.C.
Test input 1
Enable input - shift register
Data input - shift register
Clock input - shift register
VD
Auxiliary output for active filter
Phase detector output
Port output
Port output
Port output
Port output
Sigrial input
Ground
Amplifier-reference input
Supply voltage
Switch-over TVSAT range
62.5 kHz outpuVtest output
7
8
9
10
11
12
13
14
15
16
17
PO
P1
P2
P3
P4
UHFNHF
GND
REF
18
19
20
TVSAT
kHz 62.5
Vs
Crystal
Crystal
247
I\)
III
.I>OJ
i5'
()
~
c.
iii'
17 REF
IGNO
P-IOM'"
15 UHFI _
VHF
I
I
P=8
18 pF
4 MHz
t
r
1 I 128
~
y
I
r
~
ll-Bit Main
Counter
6 Ql
OSC
4MHz
H
7,8125 kHz
Q=512
I
iil
3
J+ = UP
1/128
1/136
1,4-Bit SwallowCounter
CQ
I Vs
CY
,.,"
Frequency
~
c'm''''m'~1
fREF
62,5 kHz
PO 10
1-= DOWN
7
I
I
14-Bit Latch Divider Ratio
+
4 Clock.11
Format
Control
3 Data
1
~~
18-Bit Shift Register
VD 9
-
~
r
TV SAT 19
11
L-n
1,-
Test Circuit:
Standard
Operation
Test Mode 1
Test Mode 2
2 Enable
4-Bit Latch Band
Selector
Pl
P2
P3
P4
Test 1
62,5 kHz
N.C.
N.C.
11
12
13
14
1
20
8
5
en
g
Co)
I\)
oCo)
SDA3203
Measurement circuit 1
18
Is
o-----~--~------------~~--~--Vs
4 pF
4 pF
2,5kR
~-------j---
__ to Reference
,---~~----__
Divider
Crystal Oscillator
6
01
18 pF:r:
125>LA
4MHz=
02
125 >LA
1.6kR
16
o----------+------------~~------GND
Measurement circuit 2
Calibration of signal generator
Signal
Generator
50 Q
Output
Measurement
Device
6 dB
*
Attenuation
Link
*
Q50R
+5V
Measurement of input sensitivity
18
1.5 nF
15
Signal
Generator
50 Q
*
6 dB
Attenuation
Link
*
SDA3203
17
20
Frequency
Counter
16
• no cable
GND
Test mode 2
249
SDA3203
Measurement circuit 3
11
valid for P1 .. P4
I" 12 kQ
V11 o----....-C:::::J-___.
Measurement circuit 4
20
ho 150Q
Vzoo-----..,;:-C:::::J----.
62.5 kHz Output
Measurement circuit 5
10
110
150Q
v, OO----.,;.;...---1Ll-----.
2kQ
9
250
19
150Q
Charge Pump Outputs PO, Vo
SDA3203
Measurement circuit 6a
12C bus time diagram
Enable
90%
Data
~~~~ ~_U_",~~~_OO_A
Clock
tSUEN
tHDEN
tHIGH
tSUDAT
tHDDAT
__
__________
Set-up time (Enable)
Hold time (Enable)
H pulse width (Clock)
Set-up time (Data transfer)
Hold time (Data transfer)
Measurement circuit 6 b
23kQ
Test 1
Enable
150Q
Vi. 0----1"-'--1'
Clock
Data
150Q
v,.o-----f--..........;;....r
251
SDA3203
Application circuit
Tuner
free
IIF
~
1nF
lose
47~
1
10 kf1
33V
1nF
39 nF
~22kQ r-1~
+18 PF
4MHZ+
T
Q2 UHFIVHF REF
Q1
PO
Vs
GND
PLL
SDA 3203
VD
Clock
15V
N
Data
Enable
I
-'"
Loop Filter
[2
ur~
~
L -_ _+-__________
,
[1
Computation for loop filter
Ip x Kveo
Loop bandwidth: wR = /
Attenuation:
C1 xPxN
X !AlR x R X C 1
~ = 0.5
=Prescaler
= Progr. divider
= Pump current
= Tuner slope
=Loop filter
Example for channel 47
P=8; N=11520; Jp =100 !-LA; Kveo=18.7 MHz!V; R=22 kQ; C 1 =180 nF
!AlR = 336 Hz; fn = 54 Hz; ~ = 0.67
Standard dimensioning: C2 = C1I5
252
SDA3203
Pulse diagram
13
14
15
16
0
1
17
18
Clock
0
.J
P4
Enable J
Data
P3
1
0
LJL..-..J
P2 P1/n14 n13 n12
Divider ratio
n11 n10
n9
n8
n7
n6
n5
n4
L.Jl
n3
n2
0
n1
nO
L
N= n13 x 8192 +n12 x 4096 + n11 x 2048 +n10 x 1024 +
+ n9 x 512 + n8 x 256 + n7 x 128 + n6 x 64 + n5 x 32 +
+n4x16+n3x8+n2x4+n1x2+nO
Example: N=11508
Band selection
P1 .. P4 = 1 Current sinks are active
VCO (tuner) frequency
fvco = 8 x N x 7.8125 kHz
Example: fvco = 719.25 MHz
TVSAT = N.C. bit 4 is P1
TVSAT=OV bit4 is n 14
253
254
Prescaler 1:64/1:256 for 1.2 GHz
SDA4212
Preliminary Data
DIPS
The SDA 4212 has been designed for application in television receivers operating according to
the frequency synthesis tuning principle. The component includes a preamplifier and an ECl
prescalerstage with symmetrical ECl push·pull outputs. It can be operated with a prescaler ratio
of 1:64 or 1:256.
The component has been designed for a max. input frequency of 1.2 GHz.
Features:
• Pin programmable prescaler ratio of 1:64 or 1:256
• Symmetrical push·pull input
• Low harmonic wave
• Minimal current consumption of 23 mA
Circuit Description
The preamplifierofthecomponent has been designed with symmetrical push·pull inputs. During
the asymmetrical drive of one of the inputs, the other input has to be decoupled to ground by a
a capacitor (approx. 1.5 nF) of low series inductance.
The prescaler stage of the component is comprised of several status controlled master slave
flipflops. Their prescaler ratio can be set with the switch-over input M as follows:
M to Vs=1:64
M to ground =1:256
The symmetrical push-pull outputs of the prescaler include an internal resistor of 5000 each. The
dc voltage level at the outputs is connected to the supply voltage Vs (output "High" Vs). Typical
output deviation is 1.0 Vpp.
=
The harmonic wave in the outputs are very low. The typical output modulation is 0.6 Vpp.
255
SDA4212
Maximum Ratings
Maximum ratings cannot be exceeded without causing irreversible damage
to the integrated ciruit.
Pos.
1
2
3
4
5
6
7
8
9
10
11
Maximum rating for
Tamb ~ 25°C
Symbol
min
max
dim
Supply voltage
Input voltage
(pin 2, pin 3)
Output voltage
(pin 6, pin 7)
Output current
(pin 6, pin 7)
Input voltage
(pin 5)
Junction temperature
Storage temperature
Thermal resistance:
system-air
system-air
Overload resistance
(ESD protection single
discharge of 220 pF
capacitor through a 1kO
resistor to each pin)
Vs
VI
-0.3
6
2.5
V
Vpp
Vo
Vs
V
-/0
10
mA
VM
-0.3
Vs
V
Tj
Tstg
-55
125
125
°C
°C
K!W
-600
180
115
1000
RthSA
RthSA
VMOS
KIW
V
remarks
mini 8-package
DIP8-package
not required pins
float; pin 4 always
to ground
Functional Range
Within the functional range, the integrated circuit operates as described; deviations from the
characteristic data are possible.
Pos.
2
3
256
Functional range
Symbol
min
max
dim
Supply voltage
Input frequency
Ambient temperature
Vs
f
4.5
70
0
5.5
1200
80
V
MHz
°C
Tamb
remarks
SDA4212
Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit.
Typical characteristics specify mean values expected over the production spread. If not stated
otherwise, typical characteristics will apply at tamb =25°C and the listed supply voltage.
Pos. Parameter
Symbol Test conditions
Supply voltage
Ambient temperature
Min
Typ
Max
Dim
23.5
29.5
mA
31315
31315
3/315
3/315
31315
31315
3/315
3/315
dBm/mV
dBm/mV
dBm/mv
dBm/mV
dBm/mV
dBm/mV
dBm/mV
dBm/mV
Vs= 12V
Tv=25°C
1 Current consumption Is
2 Input level
("input sensitivity")
Test
circuit
VI
3 Output voll. deviation Va
inputs decoupled
outputs enabled;
M enabled
70MHz
80MHz
120 MHz
250 MHz
600 MHz
1000 MHz
1100 MHz
1200 MHz
- 26111
- 27/10
-30/7
-32/5.5
- 27110
- 27110
-22/18
-15/40
CL~15pF;
0.4
0.6
Vpp
fS1000 MHz
4 DC voltage offset
5 M·input current
-=-:-------l
Comparator
stages
Strobe
Register
1st encoding (AND)
2 nd encoding (OR)
I
8
------f--o
- Vs ()--=+I----j
I
I
I
____________ J1
IL _________ _
1
15
01
264
02
03
04
05
06
Do
+ Vs
SDA5200N
Transfer characteristic and truth table
!
00~06
05 04 03 02
H
L
L
L
l
l
l
H
H
H
H
H
IH
L
H
H
H
H
H
l
L
I
~
I -- f---L
L
L
L
L
L
L
L
L
L
I
L
L
L
L
L
-ii
--
± 114 LSB
01
H
L
L
H
L
L
I--:-
..X
/
p
I
I
t
.%
IX
0
1..
2
I
62
,
I
63
64
a
-"V
+ 64
~
Pin configuration
top view
052
Do
06
05
04
03
02
01
16
15
14
13
12
11
10
9
[::::::]
4
051 +VIR
5
6
7
VIA -VIR ~hyStrobe +VS
Pin
Symbol
1
2
3
4
5
6
7
8
9 to 14
15
16
+VIR
VIA
-VIR
Vlhy
Strobe
+Vs
-Vs
01 to 06
Do
OS1
OS2
8
-VS
Function
Digital ground 1
Positive reference voltage (+2 V)
Analog signal input (max. +2 V; -3 V)
Negative reference voltage (-3 V)
Hysteresis control (9 V to +2.5 V)
Strobe input (ECL)
Positive supply voltage (+5 V)
Negative supply voltage (-5.2 V)
Data outputs, bits 1 to 6 (ECl)
Overflow output
Digital ground 2
265
SDA5200N
Maximum ratings
Supply voltage
Supply voltage
Input voltages
Strobe
Hysteresis control
Voltage difference
Ambient temperature
Ju nction temperature
Storage temperature
+Vs
-Vs
VIA. +VIR• -VIR
Thermal resistance
System-air
RthSA
Vstrobe
Vlhy
OSI-0S2
TA
Upper
limit A
-0.3
-6.0
-3.5
-Vs
0
-0.5
0
6.0
0.3
2.5
0
3.0
0.5
70
125
125
V
V
V
V
V
V
°C
°C
°C
85
K/W
~
-55
Tstg
Characteristics
Power supply
Pos. supply voltage
Neg. supply voltage
Current consumption
at +Vs =+5.0 V. VIA;:;; -VIR
at -Vs = -5.2 V. VIA;:;; -VIR
Lower
limit B
+Vs
-Vs
Lower
limitB
typ
Upper
limit A
4.5
-5.7
5.0
-5.2
5.5
-4.7
V
V
50
55
80
80
rnA
rnA
+VIRmax
5
V
V
V
V
V
500
500
Il A
nA
Is+
Is-
Analog section
Signal input
Max. input voltage
VI Rmax = I (+ VI Rm.x) ...;. (-VI Rmin) I
VI Afor 6 bit resolution
VI Afor 1/2 LSB linearity
VIA for 1/4 LSB linearity
Input current
at VIA =+VIR
at VIA < -VIR
Input capacitance
at VIA < -VIR
VI Amax
-VI Rmin
1.2
2.4
IIA
IIA
0.3
0.6
1.2
150
-500
pF
25
CIA
Reference inputs
Pos. reference voltage
Neg. reference voltage
Reference resistance
+VIR
-VIR
25
.
1--3.0
Rref
96
VIH
V1l
IIH
III
-1.1
-2.0
1.128
1~.5
195
I~
Digital section
Strobe input
H input voltage
L input voltage
H input current
L-input current
Data outputs (100 Q to -2 V)
H output voltage
L output voltage
266
VOH
VOL
1-
1.1
-2.0
-0.9
-1.7
6
6
1-
0 .9
-1.7
-0.6
-1.6
50
50
1-
0.7
-1.5
V
V
Il A
Il A
I~
SDA5200N
Characteristics (cont'd)
Lower
limit B
Dynamic parameters
Aperture time
Aperture jitter
Strobe
Signal transition time
Signal transition time
Strobe frequency
Max. slew rate
bandwidth (-3 dB)
typ
2
25
5
12
12
td
tstrobe
tdHOld
td Sel
'strobe
100
0.5
140
B
Pulse diagram of strobe input
and data outputs
Signal input
Upper
limit A
17
17
ns
ps
ns
ns
ns
MHz
V/ns
MHz
Input current versus input voltage
max
II.
t
min
.J--Jf_---+-----+---
267
SDA5200 N
Measurement circuit
Analog ground Digital ground
470n
(latch
son
051
Analog
input
Os, 16
oo~----------~-------+--~
Qo
VIA
06
Q6
• VIR
05
QS
"!J..l'
04
Strobe
03
Q3
• Vs
02
Q2
100nF
Strobe
To memorv
and computer
100nf
Ql
- Vs
son
100nF
h lOon
-2V
T
Tl00nF
Ground plane
Application circuit
7 bit AID converter with SDA 5200 Sand SDA 5200 N
1
Do
00
SDA
5200S
--
-
01 - -
- VIR
riVREF
+ VIR
Do
06
SDA
5200N
01
268
05
04
03
02
~
AIN Strobe
07
06
1
- VIR
01
6-Bit Analog/Digital Converter
SDA5200 S
DIC 16
The SDA 5200 S is an ultrafast 6 bit AID converter with overflow output. It has been designed
as terminating device for a 7 bit or 8 bit AID converter comprising several cascaded ICs
(refer to application circuit), or exclusively for 6 bit operation.
Apart from a guaranteed strobe frequency of 100 MHz and an excellent linearity, the SDA
5200 S is outstanding for a broad analog bandwidth which - from the analog side - enables
application up to the limit of the Nyquist theorem.
The SDA 5200 Sis pin-compatible to the ICs SDA 5010, SDA 6020, and SDA 5200 N (differing
output code in the overflow).
Features
•
•
•
•
•
•
•
•
•
•
•
•
Strobe frequency 100 MHz
6 bit resolution (1.6%)
Overflow output (7th bit)
Broad analog bandwidth (140 MHz)
High slew rate of the input stages (typ. 0.5 V/ns)
Processing of analog signals up to the Nyquist limit
Linearity ± 1/4 lSB
No sample and hold required
Dynamic driving of reference inputs for analog addition and multiplication
Power dissipation 550 mW
ECl compatible
logic-compatible supply voltage + 5 V; - 5.2 V
The following versions 11 are available upon request:
•
•
IC with a nonlinear conversion characteristic of a given characteristic curve
IC with any output code (e.g. gray code)
1) Conditions upon request.
269
SDA 5200 S
Block diagram
r------------------ -------------------,
3
4:
R,
Rl
R63
R64
R65
12
- VIR <>---7-,-----(==r--.--(::::Jr-.-c-- - - - - - - - - - -·=r-T--C::-J-~--c::::J-~o___1=}_--'I~ + VIR
I
I
I
5I
iI
VIhy<>---'+-----i
I
I
Comparator
I
I
stages
Strobe
,
I
Register
I
I
1 st encoding (AND!
2 nd encoding lOR)
8 '-:- - - j
- Vs 0--.::..
17
,
-----'-I'----000 Vs
I
I
IL ____ _
_ ________ ....JI
15
Os,
270
OSl
01
02
03
04
05
06
Do
SDA5200 S
Transfer characteristic and truth table
!1/4 LSB
I---100Q
~----------~~~~~~~-o-2V
100nF T
Tl00nF
Ground plane
Application circuit
7 bit AID converter with SDA 5200 Sand SDA 5200 N
L
Do
Do
SDA
5200S
I---
~
Dl~
-VIR
rJv'"
+ VIR .....,
00
07
06
SDA
5200N
>--
T
274
03
02
01
A IN Strobe
05
04
- VIR
01
6 Bit Analog Digital Converter
SDA 6020
ole 16
The SDA 6020 is an ultrafast ND converter with 6 bit resolution. In addition to a
scanning frequency of typically 50 MHz and excellent linearity. the SDA 6020 has the
following outstanding features:
•
•
•
•
•
•
•
6-bit resolution (1.6%). simple expansion to 8 bits
± 1/4 lSB linearity
No sample and hold required
Dynamic driving of reference inputs for analog addition and multiplication
ECl compatible (ECl - TTL matching possible. e.g. with SH 100.255)
low power dissipation 450 mW
logic compatible supply voltage +5 V; -5.2 V
Maximum ratings
Supply voltage
Supply voltage
Input voltages
Strobe
Hysteresis control
Voltage difference
Operating temperature
Storage temperature
+Vs
-Vs
VIA. +VlR• -VIR
VStrobe
VIH
OA-OO
Tamb
Ts
lower
limit B
Upper
limit A
Unit
-0.3
-6.0
-3.0
-Vs
0
-0.5
0
-55
6.0
0.3
3.0
0
3.0
0.5
70
125
V
V
V
V
V
V
°C
°C
275
SDA6020
0S2
16
Pin configuration
top view
00
15
06
14
05
13
04 03
12 11
02
10
01
9
[J=:I]
2
Pin
6
s
Function
OSl
Digital ground
Positive ref!:lrence voitage « + 2.5 V)
Analog signal input (max. ± 2.5 V)
Negative reference voltage (> - 2.5 V)
Hysteresis control (0 V to + 2.5 V)
Strobe input (ECl)
Positive supply voltage (+ 5V)
Negative supply voltage (- 5.2 V)
Data outputs, bits 1 to 6 (ECl)
Overflow
Digital ground of output stages
I
"lR
VIA
-VIR
4
5
6
7
8
9 to 14
5
Symbol
..LII
2
3
4
VI hy
Strobe
+Vs
-Vs
15
D1 to D6
Do
16
OS2
Block diagram
r-- ---------------------------------,
Overflow
63
Do
62
VIA 0-- --
tI
I
I
II
06
05
Memory
and
Comparator stages
04
encoder sta.ges
-----------
J-<>03
__________ _
02
I
01
I
I
I
I
------------
I
I
I
I
L
I ________________________________ _
- V1R
276
V1hy
strobe
SDA6020
Characteristics
Lower
limit B
typ
Upper
limit A
4.5
-5.7
5.0
-5.2
5.5
-4.7
V
V
30
55
60
80
rnA
rnA
+VIAmax
5
V
V
V
V
V
800
10
10
iJ.A
iJ.A
iJ.A
35
pF
Power supply
Positive supply voltage
Negative supply voltage
Current consumption
at+Vs =+5.0V; VIA"; -VIA
at-Vs =-5.2 V; VIA ";-VIA
+Vs
-Vs
Is
Is
Analog section
TA =25°C; +Vs =5 V; -Vs =5.2 V
Signal input
Maximum input voltage
VIAmax= I (+VIAmax)-(-VIAmin)
VI A for 6-bit resolution
VIA for 1/2 LSB linearity
VIA for 1/4 LSB linearity
Input current
at VI A = +VI A in sample mode
at VI A < -VI A in sample mode
-VIA < VIA < +VIA in hold mode
Input capacitance
at VIA < -VIA
VIAmax
-VI R min
VIA
VIA
VIA
1.2
2.4
IIA
IIA
IIA
-10
-10
0.3
0.6
1.2
200
CIA
Reference inputs
Positive reference voltage
Negative reference voltage
Reference resistance
+VIA
-VIA
64 R
2
1--2.5
96
1~.5
1128
256
I~
Digital section
Strobe input
H input voltage
L input voltage
H input current
L input current
VIH
VIL
IIH
IlL
Data outputs (100 Q to -2 V)
H output voltage
L output voltage
VOH
VOL
-1.1
-2.0
5
5
1-
1.1
-2.0
-0.9
-1.7
30
30
1-
0 .9
-1.7
-0.6
-1.5
100
100
1-
0 .6
-1.5
V
V
iJ.A
iJ. A
10
277
SDA 6020
Pulse diagram of strobe inputs
and data output
Input current versus input voltage
Strobe input
11 undefined
output levels
Test circuit
Digi tal ground
"I"
~
---l~H
~
..
f
0+--------=+-
Ul00pF
~.
l~J
10~H
~
I-- +VlR
11
Do
100nF
Analog
input
~OJl_H_
--+-- V'A
11
06
=f:l00nF
0-
11
-VIR
OS f - -
VH
0,
Strobe
03
+Vs
Dl
11
r----~
1
100nF= ~
8
t50~
100nF
T T
-I... ...I...
100nF
Groundplane
"Lines effected as Mi(r~trip
278
-Vs
Overflow
0,
-n--r-+I
I I
9
J
)
11
i---------"rr-r'---~~--I___l +1'.01
IV
L---------f_--+-!+v,.f,s
041------+--+--+--+----<> 04
031-----++-+----<> 03
==[5
Analo~
Gro!lnd
AIN.:'\
O+---i---......-t--lA IN.
;.-'
021------+--+--+----<> 02
1111--...._1--.....--+-(~5=0
Q:J--<4--lA IN
0 1 1 - - - - - - -.....-+----001
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1
~
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OOf_------~--~DO
-V,el---'"VV"V"'------I---l-V,ef
I-------------+-!-Vrof,s
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Str 2£o+---~~_+__:.s_tr_2___~_EE_'Df----.rvv"'-----... VEE 0
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304
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Data
Analog Signal
r-v~
Data
SDA 8010
~
Am
Graphic
Output
Control
(DEMUXI
o~
~
"cr
3
max.50MHz
~lV
Data
100 MHz
Clock
Address
Processor
System
Memory
en
g
co
8
g
<:)
w
~
o
P>
Thermospot
system
Power supply
3
'C
C
It
~
c
Supply and
reference
voltage
Temperature
Pulse generator
Programmable
voltage sources
II
Digital
oscilloscope
.r
i
Analog input
~rv
~
AID
'C
Digital output signals
_____....' signals
A/
Strobe
signal
logic analyzer
Pulse generator
and signal
processing
Fundion
generator
'strobe
Synthesized
signal generator
A- --]W@
Plotter
Pulse width
control
hp 9845
computer
Floppy disk
~
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o
Remote·Control System
SLE 5001/SLE 5002
TOE 4060ITOE 4061
Preliminary Data
Type
Function
Package
SLE5001
SLE5001 K
SLE5001 W
Transmitter
Transmitter
Transmitter
DIP40
Mikropack
PLCC44
SLE 5002
SLE5002 K
SLE5002W
Receiver
Receiver
Receiver
DIP40
Mikropack
PLCC44
TDE4060
TDE 4060 G
TDE 4061
TDE 4061 G
Pre-amplifier
Pre-amplifier
Pre-amplifier with Demodulator
Preamplifier with Demodulator
DIPB
SOB
DIP 14
SO 14
The CMOS components SLE 5001 and SLE 5002 have been designed as transmitter and receiver
for an electronic remote-control system_ The system offers over and above the usual characteristics,
an almost unlimited number of channels.
Since both transmitter and receiver are available in Micropack, the smallest possible dimensions
are attainable. The data from the transmitter to the receiver can be sent by the following means,
according to the peripheral hardware:
• Infrared (cost effective)
• Galvanic connection (wire)
• Inductive coupling (Transformer principle)
• Radio
• Ultrasound
If infrared is chosen the IR-Pre-amplifier TDA 4060fTDE 4061 will be an important component to
be considered.
Main System Characteristics
09.7 million different channels available
• CMOS technology
• Micropack housing
• Dynamic or static receiver operating-mode
• Minimum external component count
• High interference and operational reliability
• Power-on reset
o Standby operationlWake up mode
307
Remote-Control System
SLE 5001/SLE 5002
TOE 4060ITOE 4061
Transmitter SLE 5001: (Fig. 2)
The SLE 5001 is a mask-encoded CMOS component.
On applying the operating voltage a power·on·reset occurs, and the transmitter enters stand·by
operation. The instructions, entered by means of a push·button matrix, are converted into a 4·byte
long impulse diagram and sent out via the output stage. The component requires a matrix to be
provided with 10 row connections (P27 to P36) and 4 columns (P21 to P24).
Entering of an instruction is by means of a push·button which connects a row input with a col·
umn input. Pressure on the key activates the oscillator and the corresponding impulse message
is sent out.
A 20 msec. software controlled key debounce is contained in the program. After a brief touch of
the key the component delivers the corresponding codeword to the IR output stage.
In Fig. 1 thetiming principle of the IR data transmission is shown.
An IR channel message consists of 4 bytes (of 8 bits each). In front of each byte a synchronising
pulse is sent. Following each transmitted byte there is a pause, during which the newly received
byte can be stored (1.5 msec.). The totallR transmission is 36 bits. [(1 + 8) - 4].
Each databit is modulated by a carrier frequency (125 kHz) and sent out as an infrared light pulse
by means of an IRED (SFH 484). A databit consists of 12 IR pulses each of 2.4 I'-S duration, and
with a peak current value of about 2A. The beginning of the next bit to be transmitted is at least
1.5 ms. later. There is therefore a maximum average transmission current of about 38 mA (12 • 2.5
I'-s 11500 I'-s) • 2000 mA. During a logic bit "0" there is no output. In the worst possible case (all
bits "1'') a data word of 4 bytes will require a battery capacity of 2 mAs (12 • 2.4l'-s • 200 mA • 36).
308
1
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:::::-k-~
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I
3
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Vee
A
I
14
+ Supply voltage ¥:
~.
.::-
I
o
CD
(:)
o::I
2-
CJ)
-
~
CD
3
Received Data
RC1
10
CD
3
TDE4061
RC2
-D/ND
Greg
Cs
Ground
4
Vss
N
'N
III
r
-I
C
m
./lIo.
o
~
w
en
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r
.
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m
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cp
w
f!
$
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Cil
Ii>
3
+ Supply voltage
Igl
16
N:g
:::: ~ ~
I"
LL
L._ _ _ _-,llnfra
Vee
A
I
T1A
6
7
TDE4060
.--t--..,..--lIRc2
4
5
C",I-_ __
CSI-I-
3
I
OB 10
OAI
OBI 9
AA
AB 12
BB 11
CBI 13
BA
CAl
GND
61
EE
OA
8
0
::::I
2-
:T
CD
:e
til
3
III
""-i
iil
iii
c
C4528
14
.--_ _-._ _ _ _-lIRC1
Vss
T1B
CD
...
CD
"C
c
-"...
3
0
en
'<
UI
+'~
+~C/)
~
(jj"
:::a
CD
CD
3
Received Data
0
Do
c
iii"
...
0
'---Ih~-'---,
220pF
Values in parentheses apply to 10.7 MHz
Application circuit with ceramic filter (Murata)
For good adjacent channel suppression the ceramic filter should be combined with an
LC network.
.15V
Filter
o
C,
C2
L,
R,
R2
Sound IF
in TV sets
Sound IF in TV sets
of American Std.
FM IF in radio
mono sets
FM IF in RF
stereo sets
1.5 nF
22 nF
8 turns, 0.15 CuL
2.2 nF
22 nF
8 turns, 0.15 CuL
470 pF
22 nF
8 turns, 0.15 CuL
1 kg
SFE 4.5 MA
330 g
SFE 10.7
330 pF
470 pF
12 turns, 0.15 CuL
1 kg
330 g
SFE 10.7
680 Q .
Filter (Murata) SFE 5.5 MA
323
TBA120S
AF output voltage
versus supply voltage
fz = 5.5 MHz; LIf=± 50 kHz,
fmod =1 kHz; Vi =10 mV
Total harmonic distortion
versus input voltage
Vs = 12 V; fz = 5.5 MHz; Llf=± 50 kHz;
fmod = 1 kHz; OB approx. 45
%
V
2D,----,----,-----,----.
12
y'15I-----t-----t-----+f----j
i\
1.01-----t-----t---/----t----,..---I
r\
4
0.51-----+---F----b,c----t------j
15
10
5
20V
--------. Vi rms
AF output voltage and total harmonic
distortion v. frequency deviation
Vs = 12 V; fz = 5.5 MHz; fmod =1 kHz
Vi = 10 mY; OB approx. 45
%
1.5
,/
15
AF output voltage and total harmonic
distortion versus OB factor
Vs=12V; Llf=±50kHz;
fmod =l kHz; Vi =10mV
%
V
1. 2
II
/
0
/
I
t--VAF
/
1.0
/
/
10
Q8
/
"'THO
/
/
II
0.5
/
II
I
/
.0
/
/
o.4
/
J
10~ ~V
10 3
_Vs
/
/
/
/
/
If-THO
1
/'
V
o
50
100 kHz
o
10
20
30
40
-OB
324
I
/
/
/
o.2
./
/
THO
VAF
50
TBA120S
DC output voltage
versus supply voltage
Current consumption
versus supply voltage
rnA
V
12
25
/7
/
i
/
/
10
,,
//
Is
V,
//
/
/
t
,,/
V>
/
15
V
~/
~'
/
10
~/
o
o
/
20
15
V
V
0
10
/
10
20 V
20 V
15
-1'5
dB
o
VAF rms -10
!
-20
Volume control
versus potentiometer resistance
Vs =12 V; fz = 5.5 MHz; M=±50 kHz
fmod =1 kHz; Vi =10 mV
'-'---~--~~-.r-~
o
It~ ~~ ~~
~-l----l--I-++-/---1-l-t-------j
~--i------I-+-I-
~~V
li~ l'-N
-30
~-l---I-..JhHr--I-l---!-------j
~&!1
IJ~ l'-I\
-40
~o.l~~V
groups
Rpot
- 50 ~+--I--I-+-:'-I--IIfor 30 dB
-50
~~~'~f
"
o.ttenuo.tion
_60
-70
Gr. n1.9 to 2.2 kQ
m2.1 to 2.5 kQ
IV 2.4 to 2.9 kQ
V 2.8 to 3.3 kQ
~I-4+-1-+-l----I--+--
-60
LiI--LLLL...L..-L-L_ _ _I-------J
o
1
2
4
-Rpot
5 kl1
V
~
&~
I)~ 1\~ l\
__
- 30 1---1-----1
-40
Volume control
versus voltage to pin 5
Vs=12V; fz=5.5 MHz;M=±50 kHz
dB fmod = 1 kHz; OB approx. 45
-70
'"
j~ ~~~
1.2
1.4
1.6
1.8
2.0
2.2 2.4
V
-1-$
325
TBA120S
dB
70
AM suppression versus supply voltage
fz = 5.5 MHz; M=± 50 kHz; f mod = 1 kHz
m = 30%; as approx. 45
AM suppression versus input voltage
Vs =12 V; fz = 5.5 MHz; fmod =1 kHz
Os approx. 45
dB
70
I I
I/i ~lOm~
r:
III
60
II
~
df,,50kHz
m,30%
,300jJV
50
J
r-)I
40
40
30
30
20
11
./
I
I
!
dt ,,50kHz
m,80%
I
0
I
10
10
o
o
2 4
6 B 10 12 14 16 18 20 V
-Vs
-Virms
Input voltage for limiting
versus supply voltage
fz '3'-5.5 MHz; LI f=± 50 kHz;
fmod = 1 kHz; as approx. 45
AF output voltage
versus input voltage
Vs =12 V; f mod =1 kHz; Os approx. 45
mV
1400
jN
40
0
I\.
""-
~
mV
1100
VAFrms 55MHz
~
111111
11111111
II
!IIIIII
111111111
I I
fT 5.5 MHz . .1 t" 50 kHz
t'.
')'d8
1111'
(start I~': limiting)
11200
1/
1000
111111 It I 111111
3d8
(start,ft limiting)
20
'111111
1111111
800 -
Pi 1111111
11111
fr1O.7MHz . .1k75 kHz -
1000
800
700
600
500
I
400
10
600
300
200
o
o
326
10
15
20 V
400
1
10
I
IiFrmslO.7
900
100
105 ~V
"Hz
TBA120T
TBA120 U
FM IF Amplifier and Demodulator
DIP 16
The symmetrical 8-stage amplifier with syn,metrical coincidence demodulator for amplifying,
limiting, and demodulating frequency-modulated signals, is especially suited for the sound IF
units in TV sets. In addition to the controlled AF output, an uncontrolled AF output and
an AF input for the connection of video recorders is available.
Features
• Outstanding limiting qualities
• Few external components
• Terminal for video recorder
• AF output voltage independent of supply voltage
• Insensitive to hum
• Very little residual IF
TBA 120 T: Input and demodulator matched to ceramic resonators
TBA 120 U: Input and demodulator matched to LC networks.
Maximum ratings
Supply voltage
Voltage
Current
Junction temperature
Storage temperature range
14
Thermal resistance (system-air)
Tstg
5
150
-40 to 125
V
V
rnA
DC
DC
RthSA
90
K/W
Vs
Vs
1j
18
6
Operating range
Supply voltage range
Ambient temperature range
Frequency range
Vs
Tomb
f
11ot018
-15 to 70
o to 12
DC
IV
MHz
327
TBA120T'
TBA120 U
Characteristics (Vs = 12 V;
Tamb -
25 °C,
Current consumption
IF voltage gain Vs/V14
IF output voltage with limiting at each output
Output resistance
as approi<. 45, (IF = 5.5 MHz)
min
typ
max
Is
G.
9.5
17.5
Vqpp
175
0.8
0.8
1.4
6
20.
13.5
68
250
1.1
1.1
2.0
12
4.0
4.9
4.8
20
30
7.5
30
70
85
Rqa
Rq12
Input resistance
Internal resistance
DC level of output signal
(Vi=O)
Stabilized voltage
Residual IF voltage without deemphasis
AF gain (AF not attenuated)
Attenuation (R4-5 - 5 kC; R 5 _1 -13 kC)
Range of volume control
RI3
RI4
Va
V12
V4
3.4
4.4
4.2
Va
V12
ValV3
VAFa
VAFamax
VAFamin
Resistance
Input voltage for limiting
(.:If=±50 kHz; fmod -1 kHz)
Hum suppression
R4_51)
Signal-to-noise ratio (V1-1 0 mY)
Noise voltage (in acc. with DIN 45405)
Input impedance
aSJN
1
Vlilm
30
ValVl1
V121V11
35
30
85
80
325
1.4
1.4
2.6
16
4.7
6.3
5.3
8.5
40
10
60
5.4
R q 7-9
dB
dB
70
Vn
rnA
dB
mV
kC
kC
kC
Q
V
V
V
mV
mV
kC
Il V
dB
dB
dB
Il V
kC
TBA 120 T only:
AF output voltage
(.:If=±50 kHz; fmod =1 kHz)
Input impedance
AM suppression
(V1-500 IlV;.:I f=±50 kHz; m=30%;
fmod =1 kHz)
Bridging resistance
Varma
V12rms
650
400
1100
1000
800/5
ZI
aAM
900
650
50
60
mV
mV
C/pF
dB
kC
R 13-14
TBA 120 U only:
AF output voltage
(.:If=±50 kHz; VI -10 mY;
fmod =1 kHz; THO -4%)
Input impedance (fl - 5.5 MHz)
AM suppression
(.:If=±50 kHz; Vi - 500 IlV;
fmod =1 kHz;m=30%)
Total harmonic distortion
(.:If=±25 kHz; Vi -10 mY; fmod -1 kHz)
Varma
V12rms
850
600
ZI
15/6
40/4.5
aAM
50
60
THO
1) If DC volume control is not used, pin 4 has to be connected directly to Din n
328
1200
1000
1.3
1700
1600
mV
mV
kC/pF
dB
2.5
%
TBA120 T
TBA120 U
Block diagram
1kl1
,-------------·---+---------{==)-----+---<>12
~F
uncontrolle(
1kl1
;-C:::=:J-+--<>S
~F
controlled
14 o--j-_--tJ
11
SOOl1
50kl1
HOkl1i
1kl1
1kl1
10
4 Vref=4.BV
lion1y IBA 120 I
2Jonly TBA 120 U
329
TBA120 T
TBA120U
Test circuit (5.5 MHz)
22nF
50\1
3
1-11---+-_14
1.snFD
22nF
t
TBA120U
j::PF
t
TBA 120T
L=8 turns, 0.15 CuL
330
TBA 120T
TBA 120 U
Application circuit TBA 120 U for 5.5 MHz
+\1; VAF
~F
~F
uncontr. controlled
1113X2.2~F
~47nF
L 1 : 20 turns 15xO.05 CuLS; Q o approx. 73
L2 : 9 turns 0.25 CuLS; Q o approx. 40
Coil assembly Vogt 041 - 2165 (2438)
without cup core
Application circuit TBA 120 T for 5.5 MHz
.
+
vs
v
I'AF I'AF
AF uncontr (ontroUed
1113x2.2~F
1) Omitting the electrolytic capacitor 47 j.1F at pin 11 changes the volume-control range.
331
TBA120 T
TBA120U
Z voltage versus supply voltage
AF output voltage
versus supply voltage
dB
5
V
5,0
4,6
/'
f-""
:--
~
-
..-
/'
(
,I
VB
..-
-- -
I
-2
f--
Recommended range
of operailng voltage
-3
4,2
kV12- f--
--
-4
-5
4,0
6
10
12
14
16
10
18 V
--Vs
12
OdS ~ 710mV rms
Current consumption
versus supply voltage
V
14
16
AF output voltage and current
consumption versus ambient
temperature
mA
18
14,6
4,4
14,4
I 3,6
V
.....- ........
....V
12
Is
14.21
14,0
3,2
2,8
2,4
I---
Va
-- - -
13,8
~
........
2,0
13,2
13,0
0,8
12,8
r-= , - V,2
12,6
0,4
o
1012141618V
-Vs
332
r-- 13,6
13,4
1,6
1,2
10
mA
4,8
Va't24 ,O
14
ISV
-Vs
12,4
lt2
-20 -10
0
10 20 30 40 50 60 70·C
- - - . Tomb
TBA120 T
TBA120U
AF output voltage and disturbance voltage versus input voltage
(Input wired with SFE 5.5 MAlMurata)
TBA 120 U
dB
• 10
tI -
o
J{=! 50 kHz/HO=1.5%; AF oUlpul volloge wilh deemphosis
20
/
/"
-30
- 40
I--
- 50
I
-...
lAM
I
I
o
\
-70
s~~preJsion '
~
_
f\\
m=80%
i
,
Vd
"'- ~ /
- 80
dB -"Vi
I
200 mV rms ot 60 n. -
I
- "J"-....
- 60
- 90
1
-70 -60 -50 -40 -30 -20 -10
-90/
fB 10
_
30~
V
moO
-JmodTHZ
-100
OdS. 770 mV rms
AF output voltage-and disturbance voltage versus input voltage
(Input 60 Q impedance broadband)
dB
'10
o
~f-l0
TBA 120 U
'I
I - 20
/
- 30
It
.1.
-
- 50
- 60
t
200m~
l-ff=~~5kHtTHD=kwiihde~::hO~'S
,
.......
"-'\ ""['\,.
- 70
1
J.
_\/
.........
-(mOdr kHZ ,
-100
i
I'd
'I'-..
- 80
-
I
AM suppression
'/ \ ""- ~
1'\.II"""
- 40
- 90
T
V~J {",50 kHz/HD=3% ~with deeiPhosiS
V
dB --,-.. V,
-90~ V70 -60.-50 -40 \"30 -20 -10
I
I
I
Tl
ot pinl4-
!
~O~V
m= 80% I
m= ,30 %
-
I
moO
I
OdS =770 mVrms
333
TBA120 T
TBA120 U
AF output voltage (pin 8), disturbance voltage, and total harmonic distortion
versus input voltage
dB
·10
Vd
i
~\
f'"\
I.
!
hr-.,
lO
40
~o
tl I
AM suppression
"-
\
fmo~ =lkHz
with eOA 5,5 Me
-90 with deemphasis
1
-100
OdBn70mVrms
I
12
-~Vi
11 THO
10
1
9
I
I'\.
-70
~,dBI, 200m V
I
±
1\
-60
10 '10
.J
\\\... \
I
-50
-80
60
V
-20
-40
70
90 /
-10
-30
AF out put voltage
4f=! 50kHz ,THO=3'/.
~F8 0
TBA 120T %
13
Vd
.... 1--
r-"
"'- I'-...
/
.........
\
m= 80%
L
i-- m=30%
1
30pV
m=O
THO
I
Total harmonic distortion versus volume control
%
10
i
THO
t
I
I
:
....__noise
lincl. misurin am1lifier)1
!
I
I
~
\~
,"-'
odB
~
I
I
I
VAf8 =900 mV across IFlpin 14)
/
I
...
-,
I
'----- c---
OdB ~ Ii.F8=1.15C
[Ipin 3)
I
.;
~-o
-110 -100 -90 -BO -70 -60 -50 -40 -30 -20 -10
10
20
30
_4~F
334
40 dB
i
TBA120 T
TBA120 U
Spread
AF output voltage (pin 8) versus potentiometer resistance and
versus ratio of resistance
TBA120T/U
dB 2
2,6
2.4
2.2
/'
/'
V
/7 /
-30
-40
7
/
-50
4
r
/
/,V
1/
- 60
1/
-70
41S
...-
V /
t
I
2.B
./
-10
V
A 8 -20
3.2_.!!'ill.R
5
5kQ
}OkQ - I---
/
/I
rJ
- 80
~~t
7
-90
-100
-110
o
05
1
1.5
2 2.5
3
3.5
4
4.5
5
6
5.5
With 47 fJ.F electrolytic capacitor at pin 11 to ground -
6.5 7
Rx
7.5kQ
AF output voltage (pin 8) versus voltage fed into pin 5
dB
I
AF
o 49
~5kll
l1Bkll
I'Ar -10
t
5
8
'mil I
~
Vi'
TBA120T/U
p~j-
1:7.I Vpot
-20
/
Vs
V4
7
-30
/
-40
7
-50
II
-50
-70
-so
0
7
5V
-V
335
TBA120 T
TBA 120 U
Circuit for direct connection to video recorders
Video
recorder
mn
13
BA 127
Vs
;::
=
~
w
.12v1 ee
14)
1k.Q
22~F
HOV)
12
82011
Be 308
~
.E
8.2 kl1
1.8kl1
47011
1kn
1kl1
'-----------------4~AF
amplifier
Socket (1): Switching voltage: at playback +12 V
at recording: free
Socket (4): Simultaneous input and output for AF
Function
When the switching voltage is applied, the emitter follower BC 238 is blocked at the output,
and the buffer stage BC 308 is switched on. A preemphasis is included to balance the
deemphasis at the AF output. The IF amplifier becomes inoperable by means of the diode
BA 127 and the 47 kO resistor. The remote-controlled volume regulator in the TBA 120 T/U is
used for recording and playback.
336
Mixer
TBB042G
5014
The TBB 042 G is a symmetrical mixer applicable for frequencies up to 200 MHz. It can
be driven either by an external source or by a built-in oscillator.
Common applications are in receivers, converters, and demodulators for AM and FM
signals.
Features
•
•
•
•
•
Wide range of supply voltage
Few external components
High conversion transconductance
High pulse strength
Lownoise
337
Mixer
TBB 042 G
Maximum ratings
Supply voltage
Junction temperature
Storage temperature range
Thermal resistance (system - air)
Vs
1j
15
V
150
°C
Tstg
-40 to 125
RthSA
125
°C
K/W
Operating range
Supply voltage range
Vs
Ambient temperature range
TA
14to 15
-1'5 to 70
I ~C
Characteristics
Vs = 12 V, TA = 25°C
Current consumption
Output current
Is
= 12 + 13 + 15
12 = 13
Output current difference
Supply current
Power gain
(f; = 100 MHz, fosc = 110.7 MHz)
Breakdown voltage
(12 ,3 = 1 0 mA; V7,s = 0 V)
Output capacitance
Conversion transductance
(f= 455 kHz)
Noise figure
338
typo
max.
1.4
0.36
2.15
0.52
2.9
0.68
mA
mA
60
mA
13 -12
15
0.7
1.1
Gp
14
16.5
V2 , V3
25
-60
1.6
mA
dB
V
6
pF
13
V7 -Vs
5
mS
NF
7
dB
CZ•M, C3-M
S=~
V7 -Vs
min.
TBB 042 G
Mixer
Vs
= i2 V
Test circuit
f" =10,7 MHz
10nF
r--j
p
fasc =
3/3 turns
110.7 MHz
Application circuit
Mixer for remote control receiver
self-oscillating
+Vs
10nF
1"
r--i~-+---.
: 460 kHz
I "F
27,12 MHz
fasc
= 26,66
MHz
For harmonic crystals, an inductor between pins 9 and 11 which will prevent oscillations on the fundamental is recommended.
339
TBB 042 G
Circuit diagram
4
, j ' _ k l l- - - ,
I
2,2kll
2,2kll
10~-+-------~-----+------~---,
I
L.....I
}J
12~-+--t---~--{
1.4kll
-t---\----+------o 1. 5. B.13. 14
6
11
It is recommendable to establish a galvanic connection between pins 6 and 7 and pins 10
and 12 through coupling windings.
A resistor of at least 220 Q may be connected between pins 9 and 14 (GND) and pins 11
and 14 to increase the currents and thus the conversion transconductance. Pins 9 and 11
may be connected via any impedance. In case of a direct connection between pins 9 and 11
the resistance from this connection to pin 14 may be at least 100 Q. Depending on the
layout, a capacitor (10 to 50 pF) may be required between pins 6 and 7 to prevent
oscillations in the VHF band.
340
Mixer
TBB 042 G
Total current consumption
versus supply voltage
Output current
versus supply voltage
~A
mA
4
800
,
,;
3
,;
/Z:I3 700
1 600 ..... .... -
,;
,;
2
""'" ""
,,'" ""
/
""'" ......
""
""'"
..... ...
."
o
4
","
"" ""
500
V
...... ""
I400
...
-I-'
-
.... -
- --
~-
10-
t-
1--
_......
-I-'
.-- .-
<-,
.-
300
'
200
,;
100
5 6 7 8 9 10 11 12 13 14 15 V
o
4 5 6 7 8
9 10 11 12 13 14 15 V
Power gain
versus supply voltage
dB
18
i.--- l-
VV
"" ""
t-
-
i--""
12
10
8
64 5
6 7 8 9 10 11 12 13 14 15 V
-Vs
341
342
PLL Frequency Synthesizer
Preliminary data
TBB200
TBB200 G
DIP 14
SO 14
TBB 200 is a CMOS IC which has been especially developed for use in radio equipment.
It is suited to simple frequency synthesis as well as to dual modulus synthesis.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Bit serial control with 2 lines (12C bus)
Modulus switching
Voltage doubler for high phase-detector output voltage
Direct VCO control without op amp
High input sensitivity (10 mV), high input frequencies (70 MHz) in single modulus operation
Low supply voltage, wide temperature range
Standby circuit
Extremely fast phase-detector with very short anti-backlash pulse
Large dividing ratios
127
- A divider 1 to
- N divider 3 to 4095
- R divider 3 to 65535
Switchable phase-detector polarity
Switchable phase-detector retuning rate of rise
PORT output addressable via 12C bus
- for prescaler standby
- for prescaler programming (128 or 64)
12C bus is a patented bus system of Philips.
343
TBB200
TBB200 G
Circuit description .
TBB 200 is a complex PLL component in CMOS technology for processor controlled
frequehcy synthesis. Pin SID selects Single or Dual modulus operation. Functions and
dividihg ratios are selected via an 12C bus interface at pins SDA and SCL. An output port
PRT permits control (e.g. standby) of additional circuitry. The reference frequency is applied
at input RI; its maximum value is 30 MHz. The VCO frequency is applied at input FI. Its maximum value in single modulus operation is 70 MHz and in dual modulus operation 30 MHz.
The PLL cali be operated optionally with or without internal voltage doubler, depending on
the required frequency variation (Varicap). For operation with voltage doubler, a capacitance of typo 1 IlF (MKH) must be connected at pin C. C must be grounded when the voltage
doubler is not in use. Output PD supplies the phase detector signal with especially short
anti-backlash pulses to neutralize even the smallest phase deviations. Polarity and current
of the PD output can be switched via the FC bus. Output LD supplies a static lock detector
signal, and output FV the divided VCO frequency. LD and FV are open drain outputs.
For test purposes, a switch-on reset is provided, which is discontinued by the first H pulse
at RI. In the reset state, the dividers are switched to the programming mode.
Mode
S/D
Single modulus
Dual modulus
L
H
344
TBB200
TBB 200 G
Pin configuration
(top view)
V~L;
14
LD
RI
13
C
SID
12
GNO 1
SDA
11
PO
SCL
10
FV
PRT
GNO 2
MOD
FI
Pin description
Pin
1
2
3
4
I
I Symbol
8
9
10
11
12
VDD
RI
SID
SDA
SCL
PRT
MOD
FI
GND2
FV
PO
GND 1
13
14
LD
5
6
7
-i-j'
C
-t_
Function -------
--------------------
I Supply voltage
Reference frequency
Operating mode (single modulus/dual modulus)
12C bus data
12C bus clock
FC PORT
Modulus control
VCO frequency
Ground
Comparison frequency
Phase detector
Ground
Voltage-doubling capacitance
Lock detector
345
w
OJ
c5)
+4
1+ 8)
R[
SDA
1f(
!16-Bit R Counter
Latch
Enable
Frequency
Volt. Doubler
OnlOff
(lock
~>
l
1
U
l6-Bit Latch
!
l6-Bit SIR
T/R
r2(
PRT
L:1
W
Interface
2:]
S",db,
PO
SIDI
Polarity
7-Bit SIR
'(/
7-Bit Latch
, ~>
~7-Bit
-
ACounter
~
~
I ---I
1
1.
f--
r
t>
GND 2
I
I
GND 1
Voo
1
l2-Bit SIR
~>
l2-Bit Latch
~>
12 - Bit N Counter
l~
, I
r
o
:I\"
I
C.
iii"
ce
I
iil
3
II
Voltage
Doubler
'--
Phase
Dete dor
f----
PO
Lock
Detector
-
LD
.t'';.
Data
SCL
0"
I
Control
Logic
MOD
1
I
I
fR
L.::,....
.---.~
I
J
I
FVN
-4-4
I
mm
mm
1\)1\)
00
00
G)
ij
TBB200
TBB200G
Characteristics
Test
conditions
min
max
Input signals SOA, SCl
H input voltage
L input voltage
Input capacitance
Input current
0.7 x Voo
0
VIH
VIL
CI
11M
VI = Voo
Voo
0.3 X Voo
10
10
V
V
pF
f-lA
Input signal S/O
Input voltage
L input voltage
Input capacitance
Input current
0.7 x Voo
0
VIH
VIL
CI
11M
VI = Voo
V'rms
Voo =4.5 V
(sine)
Voo
0.3 X Voo
10
10
V
V
pF
f-lA
Input signal RI
Input
Input
Input
Input
frequency
voltage
capacitance
current
30
500
10
10
CI
11M
VI = Voo
V1rms
Voo =4.5 V
(sine)
VI = Voo
MHz
mV
pF
f-lA
Input signal FI (dual modulus)
Input frequency
Input voltage
Input current
Input capacitance
11M
30
50
10
10
CI
MHz
mV
f-lA
pF
Input signal FI (single modulus)
Input
Input
Input
Input
Input
frequency
voltage
capacitance
current
frequency
V'rms
CI
Voo =4.5 V
(sine)
f
VI = Voo
Voo =3 V
Val
10 =3.0 mA
11M
70
10
10
10
35
MHz
mV
pF
f-lA
MHz
Output signal SOA, lO
(open-drain output)
L output voltage
Voo =3 V
C L =400 pF
I 0.4
IV
347
TBB200
TBB200G
Maximum ratings
min
Supply voltage
Input voltage
Output voltage at C
Power dissipation per output
Total power dissipation
Storage temperature
V'M2
-0.3
-0.3
-Voo
Po
Ptot
Tstg
-50
Voo
3
Voo
ViM,
typ
max
6
Voo +0.3
0
10
300
125
Notes
V
V
V
mW
mW
Exception: C
(internally
generated)
°C
Operating range
Supply voltage
Supply current
Supply current:
standby FI RI
Supply current:
standpy counter
Supply current:
standby counter
Supply current:
standby counter
Ambient temperature
5
100
5.5
7
100
V
mA
flA
100
4
mA
VF1
100
3
mA
VFt lms = 100 mV
100
2
mA
VF1 lms = 500 mV
TA
-40
85
°C
Current measurement excluding output circuitry and voltage doubling.
348
rms =
10 mV
TBB200
TBB200 G
Characteristics
Voo = 4.5 V to 5.5 V; TA = -40 to 85°C
Test
conditions
min
max
Output signal PO
(Tri-state output)
H current mode
L current mode
Tri-state
IOH
IOl
103
Output signal FV N
(Open-drain output)
L output voltage
L output pulse width
Vpo 1 Voo I, 25 DC
Vql
IOl =1 mA
Cl =20 pF
tOWl = lfFI
VOH
VOL
IOH =0.5 mA
IOl =0.5 mA
±1
±0.1
50
mA
mA
nA
0.4
V
0.4
V
V
Output signal MOD, PRT
H output voltage
L output voltage
Voo-O.4
Output current MOD*
H output current
IOl
I Voo=3 V
tIR
tIF
tIW
Voo -5 V
Voo=5 V
Voo=5 V
5
5
10
ns
ns
ns
tIR
tIF
tIW
tIW
Voo =5 V
Voo=5V
Voo=5 V
dual modulus
5
5
10
10
ns
ns
ns
ns
tIW
single modulus
5
ns
I 500
I IlA
Dynamic characteristics
Voo =5 V; TA =-40 to 85°C
Input signal RI
Rise time
Fall time
Pulse width
Input signal FI
Rise time
Fall time
Pulse width
Voo=5V
Voo -5 V
Pulse diagram
~"~-~!---t=~-=l----
V1L ------
------------
---------
-------------
-------
• Status bit 8 via 12C bus: 1
349
TBB200
TBB200G
Dynamic Characteristics
Vs =5 V; TA =-40
to 85°C
Test
conditions
min
max
Output signal PRT
Rise time
Fall time
tOR
tOF
VDD = 5 V. CL = 30 pF
VDD = 5 V. CL = 30 pF
Il s
Il s
Output signal FV
Fall time
tOF
IV
DD
= 5 V. CL = 20 pF
I
I 20
I ns
Output signal MOD
Rise time
Fall time
Delay lime
L-H to FI
Delay time
H-L 10 FI
tOF
t DOLH
VDD = 5 V. CL = 30 pF
VDD = 5 V. CL = 30 pF
VDD = 5 V. CL = 30 pF
10
10
25
ns
ns
ns
tODHL
VDD = 5 V. CL = 30 pF
15
ns
tOR
Pulse diagram
~=---------::--------~ 1==
~
~: ----=----~--------------v.
--~--
-----------
'""~
---------- --------- --------------S;,oo'"
'"""'
~
~: ----------- -=----------------------------------~-----------
Signal MOD
V. ----------- ---------------------------------- -----------
350
oj
~
IT
fi
~
~
en
3
I:
- - - Main Address
•
Sub Address
I •
I
.. I •
I
I
I
I
I
SDA
,
,,
,,
I
,,
,
(...........
~_
(Ii
:
i
2-
!.
,.,. I
I
I
I
I
I
,
I
,
I
,
'
iI
I
I
I IOutput i :
i I second , I
I
IData Word",,"" J L.........
I I
"
,I
_
r-----:
----
I
,,
i
ISTART CONDITION :
,SDAt. whenSCL=H i
,
I
I
I
I
.... ........... ..,
~
i'I
I
: Output first Data Word
from Master to Slave
,
I
l. ....
..
II
i
SCL
~
'0
Data
I
Output nth Data Word
"
"
I( . . ,I
"
IAcknowledg~
j L
: Sia ve :
I
L_
-----
,,
--------, r---:I
---
---.....
i
I
I
I
,
,
,
,
,
I
!
i i
,
I
i ' ''
, i,
i
)
----__
--- -.,
,STOP CONDITION I
~DA~when SCL=H
(//" , / ,"~
----..,
i
:
,Select: Read I Write ,Acknowledge from Slave: : Acknowledge from Slave
iL=Output from Master I Ready Confirmation
"lPrompt for further Output)1
I
STOP CONDITION
SDA Changes while
SCL= H
i
I
:
I
INa-Acknowledge I
I
Slave
I
-1-1
mm
mm
~~
00
~
Q
TBB200
TBB200G
Transmission protocol for programming
SDA
IC
A
D
D
R
E
S
S
SUB
A
D
D
R
E
S
S
Single
modulus
Start
1
2
5
6
7
8
1
0
0
0
1
0
0
ACK
1
2
0
0
3
a
4
0
1
0
0
0
3
4
5
6
7
8
R/W
ACK
1
S 2
T 3
A 4
T 5
U 6
S 7
Dual
modulus
8
Status bit
0
-;,2
off
push pull
High--on
on
pos.
1 rnA
-;,4
on
current source-'
standby
•• matched to TBB 202
••• PORT output state
352
0
0
0
a
1
0
1
0
PORT
Counter
FI, RI
PD Polarity
PD Current
Voltage-Doubler Frequency
Voltage-Doubler Status
Modulus Output
ACK
Stop
Low***
oW
oW
neg.
0.1 mA
1
1
0
0
0
1
1
0
TBB200
TBB200G
Transmission protocol for programming
R Counter
SDA
Single
Modulus
A
D
D
R
E
S
S
A
D
D
R
A
T
U
S
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
0
0
0
1
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
2
3
4
5
6
7
8
A
T
U
S
R/W
0
0
0
1
0
0
ACK
1
R/W
1
2
3
4
5
6
7
8
ACK
S
T
Dual Modulus
Start
0
0
0
0
0
1
0
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
MSB
C
0
U
N
T
E
2
3
4
5
6
7
8
R/W
4
0
0
5
6
7
8
ACK
Stop
LSB
~
MSB
N
0
U
N
T
E
R
LSB
S
T
A
T
U
S
X = don't care
1
0
0
0
0
0
1
2
3
4
5
6
7
8
R/W
0
~
MSB
N
ACK
C
Stop
R
R/W
2
3
ACK
ACK
2
3
4
5
6
7
8
ACK
1
0
0
0
ACK
0
0
0
0
ACK
R
AlN Counter
Single Modulus
Start
ACK
S
T
SDA
Start
ACK
S
U
B
N Counter
SDA
Dual
Modulus
1
2
3
4
5
6
7
8
ACK
C
0
U
N
T
E
R
LSB
1
IT]
2
3
4
5
6
7
8
MSB
A
C
0
U
N
T
E
ACK
R
Stop
LSB
353
TBB200
TBB200G
Clock frequency
Inactive time prior to next transmission
Start condition hold time
(first CLOCK pulse is generated after this time period)
Clock LOW phase
Clock HIGH phase
DATA set-up time
SDA and SCL signal rise time
SDA and SCL signal fall time
SCL pulse set-up time with Stop condition
Status programming set-up time (SID)
PRT delay time relative to Stop condition
min
max
'SCl
tHO; OAT
t BUF
0
0
4.7
100
tHO; STA
tl
tH
tsu; OAT
tR
tF
tSU;STO
tso
tOPRT
4.0
4.7
4.0
250
1
300
4.7
500
500
All times with reference to specified input levels VlH and Vll.
Pulse diagrams for 12C bus, SID, PRT
r-'
I
I
I
I
SDA
I
I
I
SCL
L.
J
STOP
-l+--'~f=
__
PR_T
354
kHz
f.ls
f.ls
f.ls
f.ls
f.ls
ns
f.ls
ns
f.ls
ns
f.ls
TBB200
TBB200 G
Application circuits
I'C
Bu~
___ _
SDA SCL
Voo
Prescaler
Cc
Cs
[,
H
= Coupling Capacitance
= Blocking Capacitance
Operation: dual modulus (fmax = 30 MHz at FI)
Voo
TBB 200
GND 2 FI
,------,
I
I
' - - - - - - - i Prescalerl-------'
IL ______ ...II
Operation: single modulus (fmax = 70 MHz at FI)
CF: loop filter capacitance
355
TBB200
TBB200 G
Application circuits VCO coupling
Voo
TBB 200
GNO 1
r-------,
PO
yeO
[F
I
I
I
I
I
O~Vpo~Voo
I
VPD
L---~--------~---L~_~_~
__4 ____
i
J
Operation without voltage doubler (status bit 7 = 0)
Operation with voltage doubler (status bit 7 = 1)
CF: loop filter capacitance
356
S' l:>
-"
:::r"
~P
ID ::
AF
1
11 C SUS
SDA SCL
SDA SCL
GND 2
TSS 200
RI
MOD PRT
GND 2
FI
00'
:s:::;;j
:t !:!,
~
2
:J ::;:
ID III
ID
I
< 30 MHz
cog
0-
...0'
LD
SID
Co
0'
~
'p,e;
PO
TSB 200
FI
iil
Vao
PRT
c
'6'
3
ID
a
III
;;j
Co
iilCo
[[
0'
to
Standby Functions
GND
Q
MOD
[c
I
r
Prescaler
Vs
[c = Coupling Capacitance
[8 = Blocking Capacitance
w
(]I
-J
-- to Port Control Cincuits
[8
H
--
~
,-
--~
It
iD
":::ro
;;j
ID
_llF
I
Receiving Frequency
Transmitting Frequency
-f-f
alai
alai
NN
00
00
C)
TBB 200
TBB200 G
Pulse diagram
Phase detector
(~!
RI
~_---,n,-_--,n,-_--,n,-
__
iv
(F! N I
;ri~;t:~:~t--_...Jn
N Chann:-
1
"I
JI----+--- (Polarity Pas.)
PO
;ri-~::~:~ It---...,J
nl--__+-___ (Polarity
N Chann:tJ
"I
LO
u
358
u
Neg.)
FM Receiver Ie
TBB469
DIP 22
The TBB 469 is an FM narrow-band Ie pc.rticularly intended for radio receivers. It is suited
for the conversion, limiting, demodulation, and AF processing of an FM-modulated signal.
The input signal is routed via an RF amplifier to a crystal-contrOlled mixer. The IF signal is
routed via an external selection to an adjustable limiter amplifier followed by a coincidence
demodulator. The AF signal is routed via a low pass to an AF amplifier. Gain and frequency
response of the first amplifier can be set externally. The second amplifier contains the volume
control and a muting input for additional field strength-dependent regulation.
Maximum ratings
Supply voltage
Load current of V. tab
Junction temperature
Storage temperature
Thermal resistance (system-air)
Vs
Istab
Lower
limit
Upper
Umit
0
0
15
50
125
125
V
j.lA
70
KfW
7j
Tstg
-55
RthSA
Operating range
Supply voltage
Ambient temperature
Vs
Tamb
1:'30
112
80
°C
°C
I~C
359
TBB 469
Characteristics
Vs
= 4.5 V; TA = -30 OCto 60 °C
Supply current
Reference voltage
Test
conditions .
Lower
limit
typ
Upper
limit
1.9
3.0
2.2
5.0
2.5
mA
V
36
42
48
dB
Is
Vs';b
RF prestage
Voltage gain
Gv
Input impedance
Noise figure
Zi
11 =10 ... 50 MHz1)
(-3 dB)
NF
101/3
6
kQllpF
dB
20
kQ
kHz
fLV
IF limiter amplifier at LI f =
± 2.8 kHz, fi IF = 455 kHz
fmod = 1 kHz, Vi IFrms = 10 mV; Q factor approx. 15:
Input resistance
IF bandwidth
Limiter threshold
Setting range of the
limiter threshold
AM suppression
Signal-to-noise ratio
Field strength
AF output voltage
Min. load resistance
AF bandwidth
Total harmonic distortion
RI
BIF
VqAF1 =-3 dB
500
Vlimrrps
LlVlim
AMS
aSIN
V10
V10
VQAF1
Rq,
BAF
THO
V10 = 0 VIVstab
m=30%
14
40
10
20
20
22
40
VilF=OV
Vi IF = 10 mV
VqAF1 =-3 dB
100
0.8
30
300
20
1.2
60
dB
dB
dB
mV
V
mV
Q
kHz
35
1
2
%
37
43
dB
kQ
kQ
dB
AF amplifier 2
Voltage gain
Min. load resistance
Input impedance
Signal-to-noi!le ratio
Total harmonic distortion 1)
Gy
Rq2
RI
aSIN
THO
ViAF=1mV
Gy
V2 =OV,V,,=1V
THO = 10%
31
1
10
40
2
%
AF amplifier 3
Voltage gain
Max. output voltage
Min. load resistance
Total harmonic distortion
Volume control range
Muting depth
Disturbance voltage
in acc. with DIN 45405 2)
VqAF3rmS
Rq3
THO
LlGvol
M
ltd
1) dependent on external components
2) AQL-2.5
360
10
300
kQ
5
2
80
V4 =OV/1 V
Rmute = 00
Rmute =0
V2 = 1/2 Vstab
3
20
dB
mV
6
26
30
%
dB
10
40
dB
dB
fLVos
:I>
'C
IF
-,-O.I~F
'E.
Vstnb
.1
O.1~F
~r
I
---
c::
o
::;,
Filler
Q)
(
o
L-----. 1.5 kQ
011=1
22
~'
c
112
;:;:
I
180kfl II
80
111kQ
/
"
+
Capacitors:
(= (erQmic
S= STYROFLEX
CD Neosid
filler
5161
@Neosid filter
5828
Q) MurQIQ
(FW 4550
111 V,lab
mnF
I
10kfl
Limiter
threshold
12kQ
~An
w
~
VqAF2
VqAF1
Field strength
iii1D
m
3:
R1
v,,,
Vstab
0)
m
~.
VilF
Vs
47nF
~
1
-a
CD
:::I
S!.
12
c
PO:
~180
ykll
Capacitors:
i
C = Ceramic
S =STYROFLEX
F-Film
I
x
I
-l----L
T
0)Toko Std. Coil
LMC 4100A with
Resonance:455 kHz
~
---I
Q,;"105
(}) Neosid FII ter
BV 5828
Resonance: 455kHz
Q:; 100
v,
~
(})
Volume
j
~
j
~
~j
tl~F
--~.------.----
1..
~AF3
VqAF2
~AFl
~
1 kll.
T
1 c-L
~.
\-iAF
9F;~~~9th
R\>19kll
/~
1.
11 LJI
11"".
Limiter
Threshold
1
~
m
,j:IIo
m
~
TBB469
AF Output voltage Vq AF 3 with reference to 775 m Vrms and field strength output voltage
VqF versus input voltage V; RF
VS
4.5 V.
=
V
1,5
(mod =
1 kHz
dB
1
o
1
-10
Vq,AF l
~~
~ VqAF J
Vq F
t
-20
-30 Mute off
1,0
-40 Mute on
-50
L1i=! 2,8kHz
I
~[
71
-f
---::::::-" r... .....
'\.-,
"
Mute depth min.
(PIN 20 fpei) /
-60
,
l7
,,,
~:
'"
I
I
I
_··---1-- .----
pression)
........
1.......
-J-L--
1-.
VqAF l
I
I
.t1rOI
V"','
o
-- f---
.t1f=0;m=0,3'
I
-90
-
VqF
- - VqAFl- (AM sup- .
,/'"
,,
Muteo}
-70 Mute depth max.
(PIN 20 OV)
-80
0,5
,,
~
f---
-100
5 10'
-ViRF
Mixer output voltage Vq IF with reference to 775 mVrms at 18 kQ versus input level Pi RF
VS =4.5 V
dB
20
Vq IF
o
-10
-20
-30
7
-40
-90
7
-80
V
17
-70
-60
v
-50
V
-40
-30
-20
-10
o
10dBm
363
TBB469
IF Limiter characteristic
Vs =4.5 V,
'mod
=1 kHz
dB
-10.--------,--,----,---
-20
(Referred
to 175m V",,,)
VqAF1
~------t__::===~~~~~$~~~~~~~~~
df=H'8k~HZ:
-30~-~~_+-~f_-+_---~-----_r--
_40~L---~-,~,~-_+----- +------r-----J
d f=O
-80
I
L -_ _ _---'_ _ _ _----'-;:
10°
10'
10'
10'
AF Output voltage Vq AF3 with reference to 775 mVrms versus control voltage ViL
Vs =4.5 V,
'mod
=1 kHz
dB
o
-........
-10
VqAF l
-20
I
........
~
-30
i
"~
"-
-40
"'-
-50
-60
I
I
j
'"
-70
-80
""
l~
~
I
-90
-100
o
0,1
0,2
0,3
0,4
0,5
0,6
0,7
O,B
0,9.
V,l
364
l,OV
FM Receiver Ie
TBB1469
DIP 16
The TBB 1469 is an FM narrow-band Ie particularly intended for radio receivers. It is suited
for the conversion, limiting, demodulation, and AF processing of an FM-modulated signal.
The input signal is routed via an AF amplifier to a crystal-controlled mixer. The IF signal is
routed via an external selection to a limiter amplifier followed by a coincidence demodulator.
The AF signal is routed via a low pass to an externally adjustable AF amplifier. ESD protective
diodes are internally connected to the RF inputs.
Maximum ratings
Supply voltage
Load current
Junction temperature
Storage temperature
I Stab
7j
Thermal resistance (system-air)
RthSA
Vs
Tstg
Lower
limit
Upper
limit
0
0
15
50
125
125
V
85
K/W
-40
IlA
°C
°C
Operating range
Supply voltage
Ambient temperature
Vs
Tamb
1:30
112
80
I ~C
365
T881469
Characteristics
Vs=4.5V; Tamb=-30°C to 60 °C
Supply current
Reference voltage
Test
conditions
Lower
limit
typ
Upper
limit
1.4
2.7
1.9
4.0
2.6
mA
V
36
42
48
dB
Is
Vstab
RFprestage
Voltage gain
Gv
Input impedance
Noise figure
Z;
10113
NF
6
'1=10 ... 50 MHzl)
(-3 dB)
kQllpF
dB
IF limiter amplifier at A f - ± 2.8 kHz, f; IF = 455 kHz
fmod = 1 kHz, '" IFrms -10 mY; Q factor approx. 15
Input resistance
IF bandwidth
limiter threshold
AM suppression
AF output voltage
Min. load resistance
Total harmonic distortion
Signal-to-noise ratio
AF bandwidth
20
R;
BIF
VqAF1 =-3 dB
500
m=30%
40
30
300
10
Vlimrms
AMS
VqaF1
Rq
THD
8S/N
BAF
VqAF1 =-3 dB
20
Gv
RL
RI
aSIN
ViAF=1 mV
31
1
10
30
60
1
40
35
2
37
43
kQ
kHz
I-IV
dB
mV
Q
%
dB
kHz
AF amplifier
Voltage gain
Min. load resistance
Input impedance
Signal-to-noise ratio
1) dependent on external components
366
40
dB
kQ
kQ
dB
VjRF
1 I
T01flF C
>
Vs
VstQb
27.12 MHz
""2-
470Q
~
~1flFC
TO.1flF C
16
o
:::I
()
9
~i"
c
Vstab
;:;:
Filter
lflF
1aokQ
/
l.SkQ
,/H
CFW 4550
(Muroto)
+
1S
kQ
Capacitors:
C = Ceramic
S = STYROFLEX
180kQ
+
8
100kQ
1kQ
68flH
c..:>
Q)
~
~AF2
1SkQ
at
....m
,f:ao
~AF'
m
c.>
~~
To.l~FC
16
rq IF .. s
V,tab
ViRF
1
27.12 MHz
crystal
TO.l~F
(
rD~
~
~"'F
~d ~mlb~
T
!!I.
9,
n
c:
;::;:
01uFC
47nF .. 5011
180H~11
I
I
/
+
kl~Dm
V \J
11nn .. c:
I
T
I
A
I I I I
Capacitors:
C =Ceramic
S = STYROFLEX
CD Taka Std. coil
8
10k\')
v..AF2
0
~AFl
0
ViAF2
T
VilF
47nF
LMC 4100A with
cap. approx. 150pF
resonance: 455kHz
Qo"'105
(1) Neosid filter
BV 5961
resonance: 455kHz
Q,;" 100
aII:D
.....
~
a)
CQ
FM Receiver Ie
TBB2469G
SO·20L
The TBB 2469 G is an FM narrow-band Ie particularly intended for radio receivers. It is
suited for the conversion, limiting, demodulation, and AF processing of an FM-modulated
signal.
The input signal is routed via an HF amplifier to a crystal-controlled mixer. The IF signal
is routed via an external selection, to a limiter amplifier followed by a coincidence demodulator. The AF signal is routed via a low pass to an AF amplifier. Gain and frequency
response of the first amplifier can be set externally. The second amplifier contains the
volume control.
Maximum ratings
Supply voltage
Load current of Vstah
Junction temperature
Storage temperature
Vs
IStab
1j
Tstg
Thermal resistance (system-air)
RthSA
Lower
limit
Upper
limit
o
o
15
50
125
125
V
120
K!W
-40
IlA
°C
°C
Operating range
Supply voltage
Ambient temperature
Vs
Tamb
112
80
I~c
Pin configuration
top view
Ground
1
19 V; RF
Volume
18 Crystal
Vq AF 3
Muting input 4
Vq
AFZ
S
17 Crystal
16 Vstab
Phase shifter
1S Vq IF
Phase sh ifter
14 Vs
Vq AF 1 8
13 Bias
9
12 Bias
Vi
AFZ
Field strength 10
369
TBB2469 G
Characteristics
at Vs=4.5V, Tamb=-30°C to 60°C
Current consumption
Reference voltage
Test
conditions
Lower
limit
typ
Upper
limit
1.4
3.0
1.9
5.0
2.6
mA
V
36
42
48
dB
Is
VSlab
RFprestage
Voltage gain
Gv
Input impedance
Noise figure
Zj
NF
fj =10 ... 50 MHzl)
(-3 dB)
kQllpF
dB
10113
6
IF limiter amplifier atL!f= ± 2.8 kHz, f11F =455 kHz l)
fmod = 1 kHz, Vi IFrms = 10 mV, Q factor appro 15
Input resistance
IF bandwidth
AM suppression
Signal-lo-noise ralio
Field strength
AF output voltage
Min. load resistance
AF bandwidth
Total harmonic distortion 1)
20
Ri
BIF
VqAF1 =-3 dB
AMS
m=30%
500
40
40
asm
V10
V10
VqAF1
100
ViIF=OV
ViIF= 10 mV
Rq1
BAF
THO
VqAF1 =-3 dB
Gv
ViAF1 =1 mV
30
300
20
1.9
60
35
1
2
kQ
kHz
dB
dB
mV
V
mV
Q
kHz
%
AF amplifier 2
Voltage gain
Min. load resistance
Input impedance
Signal-to-noise ratio
Total harmonic distortion 1)
dB
kQ
kQ
dB
37
1
10
Rq2
Ri
40
2
aS/N
THO
%
AF amplifier 3
Voltage gain
Max. output voltage
Min. load resistance
Total harmonic distortion1)
Volume control range
Noise voltage in acc.
with DIN 45405 2)
V 2 = 0 V, V11 = 1 V
VqAF3rms THO = 10%
Vn
370
300
5
Rq3
THO
LlGvol
1) dependent on external components
2)AQL~2.5
10
Gv
2
80
V2 = 112 VSlab
20
50
dB
mV
kQ
%
dB
f.LVos
Vi
RF
VstQb
1-
1 1
T0.1~FC
O.1~F(
:t-
I
_.
T0.1~FC
""g
Filter
1.5kll
20
_ al
S-::I
1
11
n
Vstnb
~.
,,
M
/
C
III
::0:
180kll
Capacitors,
x
( :; Ceramic
S = STYROFLEX
CD Neosid
fitter
5161
d) Neosid filter
5828
al Murata
CFW 4550
Vstab
10nF
T
d)~
10kll
1~F 6.8kll
12kll
V,AFl
~AF2
~AF1
Muting
threshold
RI > 19 kll
Field strength
-t
III
III
I\)
~
0)
(,)
--.j
~
CD
G)
;J
1
',..
c;}
!!lll.
Vstnb
~"'" T''''''
n
c
;:;:
20
Vstob
180 kl1
/
180
kl1
Capacitors:
C=Ceramic
S = STYROFLEX
x
G) Taka Std. coil
LMC 4100A with
cap. apprax. lS0pF
resonance:455kHz
ao-l0S
(1) Neasid filter
BV S961
resonance :455kHz
ao-l00
Field
strength
Vstab
47kl1
R;>19kl1
i22~F
Volume N 47kl1
V.qAf3
1
l~FT
100kl1
~AF2
q Af1
~AF
til
m
N
.j::Io
en
CD
C)
Threshold Switch
TCA105; B; G
The TCA 105 contains an oscillator stage, a threshold switch, and two anti-valent output
stages. These ICs are especially suitable for application in proximity switches, light barriers,
and other contactless switching applications.
Features
•
•
•
•
Wide range of supply voltage, 4.5 to 30 V
High output current, 50 mA
TTL-compatible
Triggerable with dc signal
Maximum ratings
Supply voltage
Output voltage (pin 4, pin 5)
Output current
Switching frequency
Input voltage
Junction temperature
Storage temperature range
Thermal resistance (system-air)
TCA 105. TCA 105 B
TCA 105 G
Vs
Vo
10
fs
VI
Tj
TS'g
Rth SA
TCA 105; G
TCA 105 B
30
30
50
40
20
20
50
40
~
~
O'}
O'}
125
-55 to 125
125
-55 to 125
115
115
200
R'h SA
1 200
1
Vs
14.75 to 30
-25 to 85
1 to 4.5
14.75 to 20
-25 to 85
1 to 4.5
V
V
mA
kHz
V
°C
°C
I~w
K/W
Operating range
Supply voltage
Ambient temperature
Oscillating frequency
TA
fosc
IV°C
MHz
') Negative input voltages are not permitted
373
TCA105; B;G
Characteristics
Static measurement, pins 3 and 1 interconnected
Vs = 12 V; TA=25°C; Rc=5.6 kQ
Supply current
Input threshold voltage with
compensation resistor Rc
Input threshold current
Hysteresis
L output voltage (fa = 16 mAl
H output voltage
Reverse current, Vs = 30 V and/or 20 V
L output voltage (Ia = 50 mAl
Switching time in TIL operation
(fa = 16 mAl
min
Is
VI
II
300
VhY
Va L
VaH
Ia H
20
typ
max
3.4
5
mA
400
-60
35
0.25
480
mV
Il A
mV
V
50
0.35
corresponds to Vs
I ~.7
Va L
t
1.15
60
Il A
V
Il s
1
Pin configurations
TeA 105, TeA 105 B
- Vs
TeA 105 G
- Vs
IT
10
6fVS
Input
Input 1 2
5 Output 2
Input
Input 2 3
4 Output 1
374
TCA105; B;G
Measurement circuit
Inp ut o----"*---'
Circuit diagram
+~&-------------~~--~--------~--~------~------------,
375
TeA 105; B; G
Application examples
Inductive slot switch or proximity switch
2nF
n,
2
TCA
5
3
105
4
Typical dimensioning values:
L
500pF
SIFERRIT® pot cores. 9 mm dia.
Ordering code S65935-A-X25
Cu litz wire 12xO.04 mm
Metal sheet damps
Slot switch:
Number of turns: n = 2 x 25
Distance between pot core halves:
2.5 to 3.5 mm
oscillation
Proximity switch:
Number of turns: n1 = 8. n2
Distance: 2 to 3 mm
Light-operated switch (switching amplifier for phototransistor SPY 61)
BPY
6111~
376
leA
105
= 40
TeA 105j Bj G
Application example
Voltage monitor
lO 37 lO 30B
mA
Current consumption
Supply current versus
supply voltage
TA = 25 DC; RL = 00
L output voltage versus
output current
TA =25 D C; Vs = 12 V
V
5
3
II
II
'-----
Vs o 12 V
TA =Z5D C
Rlo ~
TA o25°C
V-
J
1/
I-""
10
15
20
25
30 V
-Vs
377
TCA105j BjG
Input current versus
ambient temperature
Switching threshold
Input voltage versus
ambient temperature
Vs=12V;Rc=5.6kQ
~A
mY Vs=12V;Rc=0
BOO
"
70
'"
Vs=12Y
Re=OIi
'\.,.
f
r-....
'\..
750
"
"'r-...
60
r-...
"'r-...
-
"-
........
Vs=12Y
Re= 5.6kll
"' '\..
'\
700
"-
650
-25
'"
~
"'r-...
"'r-...
50
40
25
75
50
85°C
50
25
-25
75
85 ° C
Switching threshold
Input voltage versus
supply voltage
Switching threshold
Input voltage versus
ambient temperature
mV TA =25°C;Rc =5.6kQ
450
mV
500
-IOn-threshold 450
-
~JVs=12V I.
Re =4.7kQ
/
.011- threshold
-r --
3;
~ .....
-
.....
0\\ - Inresnold
--
On-threshold ---
I
Vs =12V
_~400 -IRe =5.6kQ ............ "1 ........
_/... .... r-....
350
-25
378
On-Inresno 1d
400
350
-
TA '25°[
Rc 5.5 kll
"'Off-thresholdt-
25
50
75 85°(
300
10
1520
2530V
-Vs
Proximity Switch
TCA20SA; K
This Ie is intended for applications in inductive proximity switches. The outputs switch when
the oscillation is damped, e.g. by the approach of a metal object.
Operation schematic
Oscillator nat damped
r-t--t---o Q
Oscillator damped
Features
•
•
•
•
•
•
Large supply voltage range
High output current
Antivalent outputs
Adjustable switching distance
Adjustable hysteresis
Turn-on delay
379
TCA205A;K
Maximum ratings
Supply voltage
Output voltage
Output current
Junction temperature
Storage temperature range
Ts,g
30
30
50
125
-55 to 125
V
V
mA
°C
°C
R'hSA
85
K/W
Vs
Va
10
7j
Thermal resistance (system-air) TCA 205 A
Operating range
Supply voltage
Ambient temperature
Vs
TA
Characteristics
Test
conditions
Vs =12 V; TA =25°C
Open-loop supply
current consumption
L output voltage per output
H output current per output
Integrating capacitance
Internal resistance at 3
Threshold voltage at 3
Distance adjustment }
circuit 1
Hysteresis adjustment
Distance adjustment }
circuit 2
Hysteresis adjustment
Turn-on delay
Oscillating frequency
Switching frequency without C 1
Is
VOL
VOL
IOH
C1
Rj3
VS3
Rdi
Rhy
Rdi
Rhy
tdon
fosc
ts
Lower
limitS
open pins
IOL =5 mA
IOL =50 mA
VOH =30 V
Rhy -
00
Rdi -
00
typ
1
0.8
1.25
200
1) Parallel connection of Rhy to Rdl may at least amount to 6 kG
380
14.75 to 30
-25 to 85
10
350
1.3
1
Upper
limit A
2
1
1.5
10
660
1.5
6
0
61)
61)
200
0.015
~C
mA
V
V
Il A
nF
kQ
V
kQ
kQ
kQ
kQ
ms/llF
1.5
5
MHz
kHz
TCA205A; K
Pin configurations
TCA205A
TCA205 K
Ground
14 Hysteresis
Distance
13 Oscillator
Integrating
capacitance
12 Oscill ator
4
11
Q ourpur
10
Ground
(l
+ Vs
Ground
1
2
0 [
0
0
0
14 Hysteresis
Disrance
Integrating
capac itance
3
0
0
12 Oscillator
0.
9 Turn - on delay
Ground
50
13 Oscillator
011 .vs
0
60
9 Turn-on delay
07
output
Block diagram
9 Turn-on delay
cz
Delay
IL
V::ontrol
I
1
12
OS(
13
Oscillator
Rectifier
~ I--
---8*-
Threshold
l-
I
r-r--
Driver
w-)-
f------o
7 Output
(l
5 Output
0:
[>
switch
~
1
TeA 205
1
Distance
14
Hysteresis
3 Integrating
capacitance
1,6 Ground
381
TCA205A; K
Schematic circuit diagrams
Turn-on delay
Oscillator
t--------
Demodulator
Threshold
switch
13
12
Integrating capacitor
Output
transistors
14
Outputs
5.7
382
TCA 205 A; K
Application circuit
with 1 coil as proximity switch __ _
with 2 coils as slot switch _ . _ . _ .
11
05C1
12
,
I
a
TCA 205
05C 2 13
L'o
as
Lo, Co
Rdi
Rhy
C1
Co
oscillator
distance adjustment
hysteresis adjustment
integrating capacitor
delay capacitor
The resistance of distance and hysteresis
may be applied as follows:
Rdi
and Rhy , for proximity switch TCA 205 A; K
1. Series hysteresis
2. Parallel hysteresis
2
2
TCA 205
14
TCA 205 14
...
Circuit 1 is more suitable for proximity switches with oscillator frequencies of f > 200 kHz
to 300 kHz, and small distances. Circuit 2 is more favorable for AF proximity switches having
larger distances. This is due to the lower Rhy values enabled by circuit 1 (min. 0 G) compared
with circuit 2 (min. 6 kG). Starting at frequencies of 200 kHz, high Rhy values effect in addition
to the hysteresis also the oscillator phase. Practical applications, however, require little phase
response to receive a clear evaluation.
383
TCA20SA; K
Application example for a proximity switch
Coil data
pot core
865939-A-X22
coil former
865940-A-M1
o = 25 mm x 8.9 mm
L =642 j.LH
n = 100 CuLS 30 x 0.05
Measuring plate
30 mm x 30 mm x 1 mm, Fe
Circuitry
= 56 to 200 kQ, metal layer
Rhy = 00
Co = 1500 pF, STYROFLEX
f = 162 kHz
Rdi
Switching distance versus
ambient temperature
~
off
_on
--
12
Rdi= 200kl/
-
-I
10
9 ---- ---- --- i-----t---
I
1
- 40
384
-20
I
_ I
I
Rdi - 5[6 kl/ I
20
40
~-::;I
on
60
80 DC
J
circuit 2
Proximity Switch
TCA305A;G
TCA355 B;G
DIP 14; 50·1 ....
DIPS; 50·S
The devices TCA 305 and TCA 355 contain all the functions necessary to design inductive
proximity switches. By approaching a standard metal plate to the coil, the resonant circuit
is damped and the outputs are switched.
Operation schematic: see TCA 205
The types TCA 305 and TCA 355 have been developed from the type TCA 205 and are
outstanding for the following characteristics:
Lower open-loop current consumption; Is < 1 mA
Lower output saturation voltage
The temperature dependency of the switching distance is lower and the compensation
of the resonant circuit TC (temperature coefficient) is more easily possible.
The sensitivity is greater, so that larger switching distances are possible and coils of
inferior quality can be used.
The switching hysteresis remains constant as regards temperature, supply voltage and
switching distance.
The TCA 305 even functions without external integrating capacitance. With an external
capacitance (or with RC combination) good noise suppression can be achieved.
The outputs are temporarily short-circuit proof (approx. 10 s to 1 min depending on the
package)
The outputs are disabled when Vs < approx. 4.5 V and they are enabled when the
oscillator is working steadily (from Vs min = 5 V)
Higher switching frequencies can be obtained.
Miniature packages
Logic functions
Oscillator
not damped
damped
Outputs
Q
Q
H
L
H
L
385
TCA305A;G
TCA355B;G
Pin configuration
TCA305A
TCA355B
GND
14 Hysteresis
GND
8 Hysteresis
Distance
13 Oscillator
12 Oscillator
Distance
Integrating 3
Capacitancf
7 Oscillator
Integrating
Capacitance
6
Vs
li
5
Q
4
Q Output
11
Vs
Output
4
Turn-on
Delay
GND
Q Output
8
TCA305G
TCA355G
GND
Hysteresis
Distance
Integrating
Capacitance
Oscillator
Distance
Oscillator
Integrating 3
Capacitanc e
0. Output 4
.Vs
'[ Output
GND
Q
386
Output
10 VREF
Output
VREf
Turn-on Delay
GND
8 Hysteresis
2
7 Oscillator
6 Vs
5 QOutput
TCA305AjG
TCA355 B,G
Block diagram
~
'{ontrol
I
Oscillator
OS (
2)
-.,.0-
-
Rectifier
Threshold
Driver
""*
J
!>
n
switch
Output
a
Output
l'.i
~
Delay
.JL..
Distance
Hysteresis
Integrating
capacitance
1)
Turn-on delay
l
GND
1) TCA 305 only
2) Connected internally in case of TCA 355
387
TCA305A
TCA305G
Maximum ratings
Vs
Va
Ia
Supply voltage
Output voltage
Output current
Distance. hysteresis resistance
Capacitances
Junction temperature
Storage temperature range
T.1g
R1hSA
R1hSA
85
140
KIW
Vs
5to 30
0.015 to 1.5
-25 to 85
V
MHz
DC
Rdlo Rhy
C(. Cd
1j
Thermal resistance (system-air) TCA 305 A
TCA 305 G
V
V
mA
35
35
50
0
5
125
-55 to 125
0
J.lF
DC
DC
KlW
Operating range
Supply voltage
Oscillator frequency
Ambient temperature
fosc
TA
Characteristics
Vs =12
V.
TA =-25°C to
Open-loop current consumption
Reference voltage
L output voltage
per output
H output current
per output
Threshold at 3
Hysteresis at 3
Turn-on delay
Switching frequency w/o C 1
388
Test
conditions
85°C
Is
V,ef
Val
Val
Val
IaH
Lower
IimitB
outputs open
I,ef<10 J.lA
I al =5mA
Ial =25mA
Ial -50mA
VaH -30V
0.6
3.2
0.04
0.10
0.22
VS3
\lhy
tdon
f.
TA =25 DC
typ
0.4
-25%
2.1
0.5
600
Upper
limit A
1.0
0.15
0.35
0.75
10
mA
V
V
V
V
J.lA
0.6
-25%
5
V
V
mS/J.lF
kHz
TCA355 B
TCA355G
Maximum ratings
Supply voltage
Output voltage
Output current
Distance, hysteresis resistance
Junction temperature
Storage temperature range
V
V
rnA
Tstg
35
35
50
0
125
-55 to 125
10
Thermal resistance (system-air) TCA 355 B
TCA355G
RthSA
RthSA
135
200
K/W
K/W
Vs
lose
5to 30
0.015 to 1.5
-25 to 85
V
MHz
°C
Vs
Vo
Rd ;, Rhy
~
Q
°C
°C
Operating range
Supply voltage
Oscillator frequency
Ambient temperature
TA
Characteristics
Vs =12 V; TA =-25 to 85°C
Lower
limit B
Test
conditions
Open-loop current consumption
L output voltage
per output
Is
H output reverse current
per output
Threshold at 3
Hysteresis at 3
Switching frequency wlo C]
IOH
outputs open
IOL =5 rnA
IOL =25 rnA
IOL =50 rnA
VOH =30 V
VOL
VO'L
VOL
VS3
Vhy
typ
0.6
0.04
0.10
0.22
0.4
Is
2.1
0.5
Upper
limit A
1.0
0.15
0.35
0.75
10
0.6
5
rnA
V
V
V
~A
V
V
kHz
Standard turn-on delay referred to TA = 25°C
10
8
4
1
0.8
0.6
---
---- -
approx.1%/K
0.4
0.2
0.1
-30
-20
-10
10
20
30
40
SO
60
70
--lA
80°C
389
TCA305A,G
TCA355 B,G
Schematic circuit diagrams
Oscillator
Turn-on delay for TCA 305
9
t - - - - - - - - - - Demodulator
Output
transistors
Threshold
switch
GND
13
12
14
1(GND)
Integrating capacitor
Outputs
Rc
Demodulator
5.7
approx. 1.8V
1
Teinternal
3
390
ff
TCA305A,G
TCA355B,G
Application circuits
Vs
Vs
1,·
12
Q
TCA 305
13
Lo
5
J""d
Q
[0
Rhy
RI
Rd,
0
T[I
r
Vs
Vs
Is
6
7 -<> Q
~R'
TCA 355
5
1
Lo
2
[IT
3
[0
Os
IT
Rhy
1nF
391
TCA305A;G
TCA305B;G
La, Co
Resonant circuit
Rhy
Hysteresis adjustment
Rdi
Distance adjustment
D
Temperature compensation of the resonant circuit;
possibly with series resistance for the purpose of adjustment.
The diode is not absolutely necessary.
Whether it is used or not depends on the temperature coefficient
of the resonant circuit.
R1; C1
Integration element
Cd
Delay capacitor
Dimensioning examples in accordance with CENELEC Standard (flush)
Ferrite pot core
Number of turns
Cross section of wire
La
Co (STYROFLEX@)
fosc
Sn
RA (Metal)
Cd
M 12
M18
M30
M33 (7.35x3.6) mm
100
0.1 CuL
206j.LH
1000 pF
appro 350 kHz
4mm
8.2 kQ+330 Q
100 nF
N22 (14.4x7.5) mm
80
20xO.05
268j.LH
1.2nF
appro 280 kHz
8mm
33kQ
100nF
N22 (25x8.9) mm
100
10xO.1
585 f.lH
3.3 nF
appr. 115 kHz
15mm
22 kQ +2.7 kQ
100nF
Note:
At pin 3 (integrating capacitance) we recommend a capacitor of typo 1 nF. To increase
noise immunity this capacitor can be substituted by an RC circuit with, e.g., RI = 1 MQ
and C1 =10 nF.
392
Threshold Switches
TCA345 A
DIP4
Threshold switches featuring linear, supply voltage-dependent threshold values. Inductive
loads may be switched at the output without protective diode.
Features
•
•
•
•
•
TIL-compatible
High output current
Very high input impedance
Good stability due to hysteresis
Few external components
Pin configurations
TCA345A
Input 1 D 4 0 u tput
2
3 Ground
393
TCA 345 A
Maximum ratings
Supply voltage
Output current
Input voltage
Inductance at the output
Storage temperature range
Junction temperature
VI
La
Thermal resistance (system-air) TCA 345 A
TCA345W
Tot9
Tj
10
70
o to Vs
500
-55 to 125
125
V
mA
V
mH
°C
°C
RthSA
RthSA
140
200
KlW
KlW
Vs
10
Operating range
Supply voltage range
Ambient temperature range
Tamb
Characteristics
Tamb=25°C
min
Current consumption at output current
Ia=OmA; Vs=2V
=5V
Ia=40mA; Vs=2V
=5V
L output voltage at 10 = 40 mA
Vs=2V
Output reverse current Va = 10 V
Switching threshold (Vs = 2 to 10 V)1l
Linearity error of the switching threshold
(referred to Vs = 2 V)
Hysteresis (in % of Vs) Vs = 2 V
Hysteresis (in % of Vs) Vs = 5 V
Hysteresis (in % of Vs) Vs = 10 V
Input current
Z voltage via output
Temperature response of
switching threshold
1) measured with increasing inputvo'tage
394
Vs
ISH
ISH
ISL
ISL
VOL
12 to 10
-25 to 85
max
0.55
1.35
1.85
7.00
150
0.80
2.00
3.00
9.00
300
mA
mA
mA
mA
mV
30
0.69xVs
IJ.A
V
3.0
15
%
%
0.63xVs
0.66xVs
,:lV,
,:lV,
,:lVI
6.0
6.0
6.0
10
20
20
10
13.6
V
11.0
~C
typ
IaH
V,
II
1
30
%
%
30
15.0
nA
V
ppm/K
TCA345A
Circuit diagram
Test circuit
,---~--9
Output
Input
Ground
Application circuits
Twilight switch
(switches on light at nightfall)
Triangle-square converter
.----~----~---o.~
,-------~----~----o.~
Relay
ill
~--~---~~------~oO
Clock generator
100 ~F
tantalum
cup.
Relay (150 Q)
27kQ
L------+---------~OO
395
TCA345A
Current consumption ISH versus
supply voltage
mA Io=OmA
Current consumption ISL versus
supply voltage
mA 10=40 mA
3.0
20
II
r
I
2.5
J
/
J
2.0
)
)
1.5
10
17
/
1/
1.0
0.5
[7
1/
/
L output voltage versus
output current
mV
250
II
I
v)
~V
Val
)
200
Vs =2
Hysteresis
IJ
17
10 V
6
-Vs
Switching threshold
Input voltage versus
supply voltage
I~
/
V
10 V
SWitch-off
V
V
[7
1/
V
./
SWitch-on
150
jV
/
50
V
/; lI--Vs -3V
100
/ 1/
r;;
\/
VI
j
W
/1
V
10 V
10
20
30
40
50
-/a
396
60
70 mA
Power Operational Amplifier
TCA365 A
TO·220
The TCA 365A is a power op amp in a plastic package which is similar to TO-220. At a
maximum supply voltage of ± 21 V, the IC delivers a high output current of 3.5 A. The op amp
is protected against thermal overload and short circuits.
Features
•
•
•
•
•
High peak output current, up to 3.5 A
High supply voltage, up to 42 V
Thermal overload protection
Internal power limitation
DC voltage short-circuit proof to +vs and -Vs
Applications
•
•
•
Power comparator
Power Schmitt trigger
Speed control of dc motors
Pin configuration
+Input
>,-4_--<> Output
-Input
Pin 3 is electrically connected to cooling fin.
397
TCA365A
Maximum ratings
Supply voltage
Differential input voltage
Supply current
Ground current (min.lmax.)
Output voltage
Peak output current
Junction temperature
Storage temperature range
Total power dissipation (at Tc = 85°C)
Thermal resistance (system-case)
Vs
±21
V10
±Vs
Vo
Vs +1
10
Ptot
3.5
150
-50 to 150
13
V
V
A
A
V
A
°C
°C
W
Is
4.0
-4.0 to +3.5
RthSC
5
K/W
Vs
±3to ±20
-25 to 85
20
V
°C
dB
IGNO
~
Tstg
Operating range
Supply voltage
Case temperature
Voltage gain
398
Tc
GVm1n
I
TCA365 A
Characteristics
Vs =±15 V; Tc=25°C
Open-loop supply
current consumption
Input offset voltage
Input offset currel'!t
l!1put current
Output voltage
RL = 12 e, f = 1 kHz
RL = 4 e, f = 1 kHz
Input resistance
f= 1 kHz
Open-loop voltage gain
f~100 Hz
Common-mode input voltage range
Common-mode rejection
Supply voltage rejection
Temperature coefficient of VIa
-25 ~ Tc~85°C
Temperature coefficient of 110
-25 ~Tc~85°C
SI!lw rate of VQ for
non-inverting operation
Slew rate of VQ for
inverting operation
Disturbance voltage
referred to input DIN 45405
Short-circuit current
(51 closed)
(52 closed)
Test
circuit
Is
VIa
110
II
1
2
3
3
VQpP
VQpp
4
RI
min
typ
max
20
40
10
100
1
-10
-100
0.2
IlJA
mV
nA
IiA
13.5
13.0
5
V
V
4
±13.0
±12.5
1
Gvo
5
70
!l0
dB
VIC
kCMR
kSVR
aVlo
6
6
+13/-15
+13.5/-15.1
70
-70
80
-80
50
V
dB
dB
IiV/K
ana
3
0.4
nAlK
SR
8
2
VIliS
SR
9
Vd
1
2
2
Isc
Isc
7
2
0.75
-0.75
Me
5
VIliS
IiV
A
A
399
TCA365 A
Test circuits
Figure 1
Open-loop supply current consumption, disturbance voltage
ls
SI
lsc
100kQ
lQ
S2
10kQ
I'ro"
10kSl
51 and 52 as shown
unless otherwise specified
-Vs
Figure 2
Input offset voltage, temperature coefficient of VIO
+Vs
>--_--.....,.---0 Va
4.7kQ
47Q
400
47Q
lSI
T
220nF
Va= 100 VIO
TCA 365 A
Figure 3
Input offset current; input current, temperature coefficient of I ro
1MIl
51
11!
t..SV
I
4.7kl!
T120"F
100 I!
81 open - 82 closed:
Ir-= ~
82 open - 81 closed:
Ir+=
81 open - 82 open:
Iro=
1MO
Va
1MO
Va
1MO
81 closed - 82 closed: offset alignment
Figure 4
Output voltage, input resistance
5
6
3
4.7kl!
42.3kl!
11!
Rl
T
220nF
8 closed:
to measure Vapp
8 open/closed: to measure Rr
401
TCA365 A
Figure 5
Open-loop voltage gain
.Vs
Gvo '"'1201og101X
lOkQ
100kQ
Vi
10kQ
100n
10kn
IQ
10Q
f=100Hz
Figure 6
Common-mode voltage gain Gvc
Common-mode rejection kCMR (dB) - Gvo (dB) - Gvc (dB)
4.7kQ
3V
>-_--......
10Q
---- Vs:30V
kSVR = 20 log
1000~F
r -_ _
+--I4='~
LI VQ
[dB]
GvxLlVs
100H,
1000IJF
>---+---1IIf---+----<> Vc
8.2n
T
220nF
Figure 8
Slew rate for non-inverting operation
Vs:30V
330n
1000~F
10kn
15V!O.3V
10kn
330n
1n
8.2n
91kn
f
20nF
403
TCA365 A
Figure 9
Slew rete for inverting operetion
100Hl
1000~F
H1
l5VtO.3V
8.Hl
f
404
20nF
TCA 365 A
Safe operating area of output stage
Output current versus collector
emitter voltage
A Tc=25°C
4 ,---,---,---,---,---,
Maximum permissible power
dissipation versus case temperature
W
25
Ie
t
1\
31Mi~ift---+----+--1-----l
\
15
~
\
10
1\
\
5
20
10
30
40
50 V
o
-25
0
25
50
Supply current versus
supply voltage
Tc=25°C
nA
250
15
V
V
V
,/
5
50
2
t.
6
150 0
(
-
.......
l -I-
I
100
o
--
150
10
o
\
Vs =±15 V
r-
V
/
t
125
Input current versus
ambient temperature
rnA
25
20
100
\
-Tc
-VCE
Is
75
r-
8 10 12 14 16 18 20 V
o
-25
o
25
50
75
100
O(
405
Power Operational Amplifier
TCA365A
Open-loop voltage gain
versus frequency
dB
100
Phase response versus frequency
Tc=25°C; Vs=±15 V
Tc=25°C; Vs =±15V
lBO
90
T:
V
160
~
II
-'{1 140
f\
--
60
t
1\
120
I
100
!--'V
50
BO
40
\
!i
40
20
\
10
o
10'
10 2
10 J
10'
20
105 10 6
-f
o
10 2
107 Hz
10 4
10 J
10 5
10 6
-f
Saturation voltage versus
output current
V
j
60
30
Common-mode rejection versus
case temperature
Tc=25°C
Vs =±15 V
dB
5
90
kCMR
1
/
./
.,,/
V
V
75
3
-fa
406
\
\
[\.
I
BO I
V
o
o
85
4A
1\
'\
I
Ii
-25
I
f'\.
1\
o
25
50
"
75
100°C
AM Receiver Circuit
TCA440
DIP 16
AM receiver circuit for LW, MW, and SW in battery and line operated radio receivers. It
includes an RF prestage with AGC, a balanced mixer, separate oscillator, and an IF amplifier
with AGC. Because of its internal stabilization, all characteristics are largely independent of the
supply voltage. For use in high quality radio sets the TDA 4001 should be preferred to the
TCA440.
Features
•
•
•
•
•
•
Separately controlled prestage
Multiplicative push-pull mixer with separate oscillator
High large signal capability from 4.5 V supply voltage on
100 dB feedback control range in 5 stages
Direct connection for tuning meter
Few external components
Maximum ratings
V
7j
15
-40 to 125
150
RthSA
120
K/W
Supply voltage
Storage temperature range
Junction temperature
Tstg
Thermal resistance (system-air)
Vs
·C
·C
Operating range
Supply voltage
Ambient temperature
Vs
TA
14.5 to 15
-15 to 80
1
~c
407
TCA440
Characteristics
Vs = 9 V; TA = 25 °C; fiRF = 600 kHz; f mod = 1 kHz
Total current consumption
LlVAF = 6 dB
RF level deviation for
LlVAF = 10 dB
m=80%
Is
LlG RF
LlG RF
10.5
65
80
mA
dB
dB
140
260
350
mV
mV
mV
50
100
130
mV
mV
mV
AF output voltage for V, RF
(symm. measured at 1-2)
for m =80%
for m=30%
V,RF = 20 IJ.V
V,RF= 1 mV
V,RF=500 mV
VAFrms
V,RF= 2O IJ.V
V,RF= 1 mV
ViRF=500 mV
VAFrms
VAFrms
VAFrms
VAFrms
VAFrms
Input sensitivity
(measured at 60 Q, f, RF = 1 MHz, m = 30% /0%, RG = 540 0)
at signal-to-noise ratio .9.~N=6dB
(in acc. with DIN 45405)
V,RF
S~N =26dB
V,RF
S+N =58 dB
N
V. RF
IJ.V
7
IJ.V
mV
RF stage
Input frequency range
Output frequency flF =fosc -f,RF
Control range
Input voltage (for 600 kHz, m = 80%)
for overdrive (THD AF = 10%),
symmetrically measured at pins 1 and 2
(mean carrier .value)
IF suppression between 1-2 and 15
RF input impedance
a) unsymmetrical coupling
at
GRFmax
at G RFmm
b) symmetrical coupling
at GRFm3x
at G RFmm
Mixer output impedance
(pins 15 or 16)
408
o to 50
460
38
MHz
kHz
dB
alF
2.6
0.5
'20
V
V
dB
Z,
Z,
2/5
2.2/1.5
kQ/pF
kQ/pF
Z,
Z,
Zq
145
4.5/1.5
I 250/4.5
kQ/pF
kQ/pF
kQ/pF
f,RF
flF
Ll Gv
VIRFPP
VIRFrms
TCA440
IF stage
Input frequency range
LlG v
Control range at 460 kHz
Input voltage (mean carrier value)
at Gmin for overdrive
(THD AF =10%), measured at pin 12
(60 Q to ground, tifF = 460 kHz, m = SO%;
tmod =
o to 2
MHz
62
dB
200
mV
mV
mV
mV
mV
1 kHz)
AF output voltage for Vi IF at 60 ~ (pin 12)
1Ii1F=30JlV, m=SO%;tmod =1 kHz
iii IF = 3 mV, m = SO%; tmod = 1 kHz
VilF =3mV,
m=30%;tmod =1 kHz
Vi IF = 200 JlV; m = 30%, tiF =455 kHz; tqAF = 1 kHz
V7 AFrms
50
200
70
35 to 60
IF input impedance (unsymm. coupling)
Zi
3/3
kQ/pF
IF output impedance
Zq7
200/S
kQ/pF
V7 AFrms
V7 AF rms
V7 AFrms
Tuning meter
Recommended instruments: 500 ~A (Ri = 800 kQ)
or 300 JlA (Ri = 1.5 kQ)
The Ie offers a tuning meter voltage of 600 mV EMF max. with a source impedance of
approx. 400 Q.
409
TCA440
Measurement circuit for output voltage
8V
47nF
5011
455kHz
47nF
16
14
10
TCA 440
4
3x
100nF
5
39kll
8
VqAF
-----Coil Assembly Vogl 041-2519
400
47pF
1M
410
TWO'
Q
.
n
c
Co
iii'
III
ii1
3
15
16
R,
R,
R,
D1
e:,
m
01
~
~1
03
04
R,
?1
I ,,"
[
~ 1~ ,W
R"
R,}1
14
R14
R'l
C-
R-"
I
-
-
11
1312
R,"
R'i,
R!!,
~,
e,
'"
'"
Dl ~
~~
T14
--
,-
016
R"
--c=
017
R"~,6TZ;;t-
T*
r.. ;;T-gr
~
> 1*";;;
~
e,
Tn
~
'h
T19
-
R2'_'
',1-
T*
e,
~2
~11r,r 1;',T3~-
R"
.~
T20 T21
Rp
R,
T3 RJ
~~Ri
-VTI
H(T4
R"
R"
RN
R"
013
014
!"
R"
~
018
:,,-
020
R"
R"
R",
021
015
R"
r'
R,.
R"
RN
R"
R 1j
Rl6
jR"
R39
R4~
--Ki
~18
Rl,s
R49
R"
R;o
R"
T17
Rn
RS1
10
~
~
~
~
.j>.
o
~
~
t;:~~~~~:J;~ ~~~ ,~~
TCA440
Block diagram
---,
-tT-
iii Necessary
I
I
+Vs
4.5 to 15 V
I
I
I
L-
-~~~;.;~t;~~~------~~~I~FSS~mgglee
fil,IVI
+
412
AA11B
,-----------~----~----~~--------~---------o+9V
s::
m
I/)
B
J
1
2
4
6
9
12
1B
3
ID
=
i
T~;~~ Meijer ~15PF
-- ---:
H'-~370~A
n[Turns]
c
Cil
5,
a:
I
RG [Q]
,
~ ________ JMuro.to. SF 455 D
15
60
240
540
l,2kll
2,2kll
4,Bkll
~'
III
;!;
AA 118
»0
DI
OVqAF
9
~
iii'
ID
iil
go
Vi R F 0 > - - t - - - - - - - - - - - . J
Zi = 6011
T
l,Bkll
8,2kll
Ll-L2 M 25 pot core
L3-Ll1 with coil assembly Vogi 041-2519
~
c;S
25~F
T
[
Ll 2+6 turns 6x12xO.04 Cu LS
L2 n turns 0.15 Cu L
L3 90 turns 12xO.04 Cu LS
L4 35 turns 12xO.04 Cu LS
L5 15 turns 0.10 Cu L
Ls 70 turns 12xO.04 Cu LS
L7 35 turns 12xO.04 Cu LS
La 60 turns 12xO.04 Cu LS
LlO 22 turns 12 x 0.04 Cu LS
Ll1 68 turns 0.06 CuL
Switch
A
B
C
off
Ion
off
separate prestage control
.
~
AA 118
Kl
I
r=L
I
r
I
I
l>
'0
o+Vs
"2-
o·
I»
c:
0
:::I
(D
2.2kll
><
I»
°r Tuning Meter ~7PF
'\'"
-~
Lo,r
3
'0
~( ~-~~--~MuratQ
330pF
--
-s::
iD
....0
SF 4550
L
I _______ _ J
I
==
~
;:;:
'::I'
AA 118
I
I
VAF
I
I
~
""
01:0
I
I
0
I
I
ViRFO
2x100nF
T
8.2 k12
T
T25~F
L 1-L 2 with coil assembly Vogt D21-2375.1
L3 -L 11 with coil assembly Vogt D41-2519
105 turns
7 turns
80 turns
35 turns
15 turns
20 turns
50 turns
LlO 22 turns
Ll1 400 turns
L1
L2
L3
L4
L5
La
L9
12xO.04 Cu LS
0.10 Cu L
12xO.04 Cu LS
12 xO.04 Cu LS
0.10 Cu L
12xO.04 Cu LS
12 xO.04 Cu LS
12xO.04 Cu LS
0.06 Cu LS
~
:J>
~
TCA440
Prestage control TCA 440
mV
j
600
~
_+~
HI--------<·9V
soo
100nF
~ 1400
300
f
Vi
100
=600 kHz Un mod.
V15 =460kHz Unmod.
O+---~~---r----~--~------
o
10
20
30
-
40
dB
Attenuation ~6v
The input ist not power matched and can be driven with a higher resistance. The selected Vi
ensures a constant V15 (50 mV peak-to-peak).
IF control
mV
+1',
f
8.
:l!!
800
700
600
500
~ 400
:gc:
Q
,>!..........-B>I---.-_-< ~
300
0
3.3nF
!!: 200
100
10
20
30
40
50
-
The selected V1F (469 kHz;
m-
60
dB
Attenuation ~6v
80%; 'mod -1 kHz) ensures a constant VAF (200 mV. rms).
415
TCA440
AF output voltage versus RF input voltage
...--
Measured Symmetrically at 1 and 2
O~~~~_~~~-L~~~I~I~I~II=liilllL-~I~I~II~IIII~IIII~I~~
10- 3
10- 2
10-1
10 0
10 1
10 2
10 3 mV
-V;RF
Example for medium wave applications
AF output voltage versus output frequency
Total harmonic distortion versus modulation
frequency
mVrms
%
150
.'
.i\
"
i\
75
-without Detuning
--3kHz Detuning
I
i
.....
\( ..
0.5
416
15
THO
\
"
10
\
t
~HO'~
-20
5
50
25
Passband characteristic versus input
frequency, measured from input to
output of the circuit
\
n
f. -f
THO
rFj
o
10kHz
-40
1432
1440
1448
1456
1464 1472 kHz
_f
TCA440
Total harmonic distortion versus detuning (parameter: modulation frequency)
Vs = 9 V
tose = 1.455 MHz ± LIt
m = 30%
fiRF=1 MHz
f1F =455 kHz
ViRF =20 mV rms
%
14
7 '""
J
THO 12
f
10
/
8
1kHz
I
~
II '\
y/ ~ r-2kHz
I'\~
~ J...'-" ....
o
-10
\
/
__\ f\
~
2
V 1\
-.-
/~
7 \
~HZ
6
4
-
-8
-6
-4
-2
. 1kHz
4
_
10kHz
8
Detuning Llf
Total harmonic distortion versus detuning (parameter: RF input voltage)
0/0
r-
B
.
200
~5
-..;;;:
4 2
~
~
/. ~
l--
I
I ~igure 20: V;RF =20mVrms
Figure 200: ~RF =200mVrms
2;
.-
~~
7
~
/
~
J
Figure 2: V;RF =2mVrms
m =80%
7
/ \ /
17
--
I/~
l7
I
!
2
Vj
\.
\ 1'... ........ ~
\
,,- / '
~
lLL-- ~
o
-10
-8
-6
-4
-2
2
4
_
8
10kHz
Detuning Llf
417
TCA440
AF output voltage and noise
figure versus RF input voltage
switching position 6011
Y
/
20
10
P"'"
~ Vi--'j..-
50
~ "/,,-/
~
V
/
II
I
l
---
t--
:
~~151l
Gil
/v
I
V vV'
V
L
I
101
418
10 2
-I\RF at
10 2 mV,m.
YiRF at
6011
103 mV
6011
TCA440
Application example for MW
Prestage control is derived from IF control
r------+--------+---o----~.__---------------------o
+4,5 .... 15 V
2,2 kl1
100nF
T
47pF
'/\-1
Lt-f---~J
330pF
~[~3201
Murata SF 4550
AA 118
I
I
I
I
4e =370pF i
I
12 kl1
I
~RF~------------------1
T
5 ~F
2xl00 nF
T
T
1,8k 11
370~A
/
Ll-L2 With Coil Assembly Vogt D 21-2375.1
L3-Lll With Coil Assembly Vogt D 41-2519
1,5 kl1
105 turns
7 turns
80 turns
L4 35 turns
L5 15 turns
La 20 turns
Lg 50 turns
LlO 22 turns
Lll 400 turns
Ll
L2
L3
12xO.04 Cu
0.10 Cu
12xO.04 Cu
12 xO.04 Cu
0.10 Cu
12xO.04 Cu
12 xO.04 Cu
12xO.04 Cu
0.04 Cu
LS
L
LS
LS
L
LS
LS
LS
L
419
TCA440
Test figures for application example for MW
Total harmonic distortion and AF output voltage
versus RF input voltage
measured symmetrically at pins 1 and 2
fi = 1 MHz, f mod = 1 kHz, flF = 455 kHz, Vs = 9 V
420
TCA440
Application example for MW using BB 113 varicap diodes
.----+---+----+---+------------<>+vs (4.5-15V)
100nF
T
330pF
330pF
12k\1
I
100 nF
10nF
I
L, - L2 With Coil Assembly Vagt 021-2375.1
L3 -L '1 With Coil Assembly Vagt 041-2519
Vlu,,= 8.5V -
f, =800kHz
Vlun= 30 V -~ =1620kHz
T
5~F
L, 105 turns 12xO.04 Cu LS
L2
7 turns
0.10 Cu LS
L3 80 turns 12 x 0.04 Cu LS
L4 35 turns 12xO.04 Cu LS
L5 15 turns
0.10 Cu LS
La 20 turns 12xO.04 Cu LS
Lg 50 turns 12xO.04 Cu LS
L10 22 turns 12xO.04 Cu LS
L11 400 turns
0.06 Cu L
421
TCA440
Conversion transconductance versus oscillator voltage
mS
35
[
/
20
,Y
f--
I
V
15
V
I
S
v
II
l 2
l 2
I
r-
f'F = 455kHz
V5 = +9V
V J = OmV
f-----
100 mVrm ,
_
422
=~-~
V _ - V _
Vi = Cons!. = 1 mV at Pin 1
fi = 1MHz; m =0 %
f 05(= 1.455MHz
-c----
10
1Vrm ,
Vose at 5 (4 With Capacitance to Ground)
TCA440
Measured values for application example for MW using diode BB 113
AF output voltage and total harmonic distortion versus RF input voltage
'i = 1 MHz;
Imod = 1 kHz; IIF = 455 kHz
Vs = 9 V; ViRF symmetrically measured at pins 1 and 2
mVrms
%
Tuning meter voltage versus IF control voltage
(parameter: impedance of tuning meter)
mV
600
~~---.-,--,---,-.---.----,
1-10 500
I
400
300 1--+---t--I----t-rY'-l-*--t------1
Example for moving coil instruments
100 1--+----H-r-I7'---t----t---j------t------1
o '""""~-'-__'----'---__'__'----'------'
o
200
400
600
800 mV
Ri
Full-service deflection
1.5 kQ
1.5 kQ
2 kQ
350 Q
100
170
200
500
~A
~A
~A
~A
423
424
TeA 785
Phase Control
DIP16
This phase control IC is intended to control thyristors, triacs, and transistors. The trigger
pulses can be shifted within a phase angle between 0° and 180°. Typical applications
include converter circuits, AC controllers and three-phase current controllers.
This IC replaces the previous types TCA 780 and TCA 780 0
Features
•
•
•
•
•
•
•
•
Reliable recognition of zero passage
Large application scope
May be used as zero point switch
LSL compatible
Three-phase operation possible (3 ICs)
Output current 250 mA
Large ramp current range
Large temperature range
Pin configuration
top view
Pin No.
Vs
a2 al
L
[12
V11
[10
R9
16
15
13
12
11
10
9
14
[::::::]
OS
2
Q2
3
4
au
Ul
5
6 7
VSYN ( I QZ
8
Vstab
1
2
3
4
5
6
Symbol
Function
Os
Ground
Output 2 inverted
Output U
Output 1 inverted
Synchronous voltage
Inhibit
Output Z
Reference voltage
Ramp resistance
Ramp capacitance
Control voltage
Pulse extension
Long pulse
Output 1
Output 2
Supply voltage
02
OU
01
VSYNC
I
10
11
12
13
OZ
Vstab
Rg
ClO
VII
C12
L
14
15
01
02
16
Vs
7
8
9
425
TCA 785
Functional description
The synchronization signal is obtained via a high-ohmic resistance from the line voltage
(voltage Vs). A zero voltage detector evaluates the zero passages and transfers them to
the synchronization register.
This synchronization register controls a ramp generator the capacitor ClO of which is
charged by a constant current (determined by Rg). If the ramp voltage VlO exceeds the
control voltage V11 (triggering angle
C') _. (t)
Co 0
o0 (I)
c
iil
3
CD
...
:I
6~
9.
10kQ
14
Sl
4
52
r15
53
2
S4
3
S5
ac
;:;:
....
'---'
~Vs
S6
iND 1
U-II>
.::...9~
.:1
.... 0
::> ., 'T1 ::> 0
w· Co ...
;; Jl ~
.<;: S· 3
:tI_m
:::r II>
.
(,)
(,)
~~
I
I\)
<
:::r
19~
10
8
o
+VB
1
C,o
11
OV to
Vramp
(peak)
rf~o~111"
I.!
0... Vs
Vs
Vs
0... Vs
~
3>
;t
U1
TeA 785
Test all<1 measurement circuits
Measurement circuit 2
Pin
2,3,4,7,
14,15
I
Va.
(V,al)
1
The residual pins are connected as in measurement circuit 1
Measurement circuit 3
Pin
14,15
The residual pins are connected as in measurement circuit 1
434
TeA 785
Measurement circuit 4
Vs/mV
+ -..------..-
v
100kQ
Pin 5
II
Vs
1kQ
Residual pins are connected as in measurement circuit 1
The 10 IlF capacitor at pin 5 serves only for test purposes
Measurement circuit 5
+
Measurement circuit 6
Pin 3
Pin 11
+--------11-"----00.5 V
T,
Pin 1
435
TCA 785
Inhibit 6
Long pulse 13
----1r---t-- +
12 kQ
ZD
6.5
Outputs
Pulse extension 12
Reference voltage 8
---.--...-+
;---t---oQ
436
TCA 785
Additional circuit description
Application examples
Triac control for up to 50 mA gate trigger current
Load
~
4.7kQ
B~61
15
Tc
v~17
L~AY
20V~
470
~F
61
~5V
1~~.i= L~
BAY
61
1.
14
!:..
13
5
*
TeA 785
12
TX(10M60~
2s
~
B~Y61
2.2~F(MKH)
-+-c::J----~ l-fokQ
1-1_1
Q22~~
250v..
"-
150Q
2
2:"iI&
10
22kQ[
[10
100kQ
[12
==?
O.l~F== ~
47
h
150
nF pF
Mp
A phase control with a diretly controlled triac is shown in the figure. The triggering angle of
the triac can be adjusted continuously between 00 and 1800 with the aid of an external
potentiometer. During the positive half wave of the line voltage, the triac receives a positive
gate pulse from the Ie output pin 15. During the negative half wave, it receives also a
positive trigger pulse from pin 14. Trigger pulse width is approx. 100 I1s.
437
TeA 785
Fully controlled AC power controller
Circuit for two high-power thyristors
o:~
i'l
"
r--------i-------,
j
I
IL ____v
____ J
i
L/1
1
1
1
I' --.J
1
1
i'-J
'I
g~
'Of
I
---- ---
II
~
I>:
:::
r - - - - I--~C:-- - - - - - - - - 1------------~c:
N.x
_~.x
8
~
:=
.
. "N
~
,£'
:=
=~
.-;r-
___ E
I"
_m
0",
~
~~~
-CD ....
c
c~
~
E
I
8 ~
~ ~~=
~
II~
~0
:-;;-
c:
f.
r
CD
=F=~
II
~
::::
F=~y~
II
~
'-.JJI.~
::J
==~
~I
~
- J~
II'::;
.....
0
~==
~
\!!
;:!
II'"
N
I~
II~
II
N.~
..2:
L{~
~
~
d
P
-
---~S2---
>
~
TCA 785
N
m
~
....
."
...
.,
I
1
I
I
~CD."
I
~:;;
~
L
li'l
~
~
1------------....
7~
I
I
I
~I--CO
- - - - - -.....
-.J
c
~~
£.~
I
Shown is the possibility to trigger two anti paralleled thyristors with one IC TCA 785. The
trigger pulses can be shifted continuously within a phase angle between 0 0 and 1800 by
means of a potentiometer. During the negative line half wave the trigger pulse of pin 14 is
fed to the relevant thyristor via a trigger pulse transformer. During the positive line half wave,
the gate of the second thyristor is triggered by a trigger pulse transformer at pin 15.
438
() ::c
o
III
:I -
~b'
4.7kQ
RSYNC
9W
2.S
220kQ
~---
1N4005
02
!f.
0.47~F:~
22 Vac
10' ~F :
16 de
F,
1]0-
t1L-
1
15
l
1SV
BAY BAY
61 61
14
,.,
BAY61
2200
BAY 61
2200
5
-.I
co
12
1I1
]
10
~
9
'---O.1.~F:
~ :I
1P'2,
:I. III
R,
.
n,
F2.2~F
=
11
6
-Co III_.
... IP
~-a
'<:::r
13
l>
Iv
2.2kQ
,--
n,
III .
1N4001
c,. c"
~ R,~ =~;~~ ~F
100kO }y
III III
SIP
Cil
, - !-
tT
:::!.
C.
IC
2.2kO
IP
~.
tI
\ \
c
;::;:
Th1 Th2
22kQ
2.0
O'a
.. a
0=
~ ~
01
~
4.7kQ
-i
.!!
.v,
'------4-----.
2.B
v,
:!!.
..
~
:I.
IC
IC
...IP
"5.
..
III
Hp
IP
iil
:I
a...
3IP
III
:I
C.
c.
-l>-
~
;'
!l
~
.....
co
J>
c.n
-I'-I'-
R
o---r-
'OJ;
a
o
III
ID
b
== :;:
... 0
RSYNC
220kn
4.7kn
9W
2x55i 0 0440
,-------,------ + Va
lN4005
02
~a
~
iii·
a=
"ID
101
00.
iil
0.47~F*
220Va,
1000~F
16Vdc
+f
~
15
1
15Vi
i
fBAytBAY
61
61
I
j
i
l
-I
f'"'I
l>
.....,
co
lI'I
14
BAY 61
220n
BAY 61
220n
VI
:i.
ce.
ID
4.7kn
-c
::T
Rl
III
VI
ID
C"
n~'1
13
--:r.:-
12 .,..2.2~F
11
10kn
10
ID
n,
!1.
a
]T1.
~~--~------~~
§:
IN 4001
Th1 ITh2
~
22kn
0.1 pF
~
cc
LJ.--.6- vo
=? R,~..f..w
.1:"
147nF]iSop
100kn
MPo~L=====--
_____
2xBSt 01046
!i.
s:
l..
:::!.
cc
cc
...
ID
'0
C
if
~
:::I
a-
3
ID
iil
0...
f
-I
~
~
UI
TCA955
Speed Controller
DIP 16
The TCA 955 is suited for the speed control of dc motors. The principle corresponds to a
clocked control. Outstanding features are its high control accuracy, its large supply voltage
range, and the possible current saving. Additionally, the IC features a battery voltage indicator.
Typical applications
Speed controi in
•
•
•
•
•
tape recorders
cassette recorders
record players
movie cameras
control system drivers
Maximum ratings
Supply voltage
Supply voltage
(pin 11 and pin 15 connected)
Output current pin 16
Output current pin 12
(LED output)
Power dissipation, LED output
Junction temperature
Storage temperature range
Thermal resistance (system-air)
Vs
16
V
Vs
6
200
15
V
mA
mA
mW
T stg
150
125
-55 to 125
RthSA
85
K/W
Vs
2 to 6
V
Vs
4.8 to 16.0
V
Tamb
-25 to 85
DC
10
10 LED
POLED
7j
DC
DC
Operating range
With internal short-circuit stabilization
(pin 11 and pin 15 connected)
With internal stabilization
(VS to pin 15)
Ambient temperature range
441
TCA955
Characteristics
Tamb
min
typ
max
Vstab
2.75
8.3
15.5
3.00
12.0
24.0
3.30
VI
LlVI
0.46
=25 °C; Vs =2.2 V to 16.0 V
Controller
Current consumption Vs = 4.8 V
Vs= 16 V
Stabilized voltage
Vs = 4.8 V to 16 V
Input threshold (pin 3)
to ground
Hysteresis of input threshold
Offset voltage (pin 3 to pin 2)
Input current (pin 3)
Output transistor saturation voltage
10= 50 rnA
10=100 rnA
Output transistor cutoff current
Duty cycle - control range 1)
Rated rpm 2)
Is
Is
X VII
Voffset
0.485
0.015
11
X VII
X VII
II
0.84
0.92
Vasal
Vasal
IOH
v
n
0
12,55
14,85
p ·R I ·C 2
P 'R I ,C2
Error in rpm with
duty cycle contrl 3) from 0 to 1
0.51
0.03
20
1
rnA
rnA
V
X VII
X VII
V
V
mV
!-LA
V
V
!-LA
1.00
1.25
30
1
17,64
rpm
P 'R I ,C2
0,224
N· p
'C
%
Switching oscillator
Frequency
Average voltage pin 10
Voltage pin 11
peak to peak
Voosc
Voosc
2) p = number of pole pairs of the tachometer generator.
3) in applications without switching oscillator.
442
0,4 . R2 ·C4
0.48 X VII
0.18 X VII
Hz
V
V
TCA955
Battery voltage indicator
min
VIcn
VIc«
Vhy
II
VQLED
Threshold voltage
Hysteresis
Input current
Saturation voltage
LED output')
typ
max
1.5
V
V
mV
1.0
220
0.2
0.5
+ 500 x ILED
flA
V
Formulae:
Rate rpm
n=
Switching frequency f =
14,85
P 'R, . C2
~
30
[rpm]
[Hz]
in operation without switching oscillator.
Reference value
Precharging voltage at C3
(pin 6 and pin 7 connected)
1) A protective resistor of 500 fl
V,ef = 0.44 X Vll [V]
VF = 0.87 x V,ef [V]
± 20% is integrated inside the IC.
443
TCA955
Block diagram for speed control with TeA 955
R2
[4
~ VstQb ..----E.;:J---~---I~--I
OHa 471lF
:
Tanta~.!"_-[::J- __
R3
1
.....-~--,II
I
[3
617
+
8 19
Actual/
value
33 nF
:10
'Reference
value
Vs =0.44 V,tQb
3
RPM
2
14
12
I
~LD40
I
!
t
+Vs
Dimensioning notes
1. The internal voltage stabilization offers the following advantages:
- operation with highly varying supply voltage,
- wide range of supply voltage.
2. In order to receive pulses with a steady duty cycle at the output, symmetrical pulses must
be applied to the input.
3. It is recommended to use multipole tachometer generators as this improves the accuracy
of control and possibly the power consumption.
4. The power consumption can considerably be reduced by means of the switching frequency
oscillator at low electric motor time constants.
5. Higher accuracy can be obtained by using a second-order filter instead of C3 .
6. When using rapidly starting motors, the precharge circuitry reduces overshoots.
444
TCA955
Saturation voltage of output transistor
Output voltage versus output current
Rpm versus ambient temperature
Vs = 12 V; A, x C2 -100 Ils
%
0.50
..."
V
0.8
./
.-.......
dn
n
r 0.25
V
V
Vs -12 V
\
0.6
R,xCz"100~s-
" "-
~
"-
0.4
-0.25
"-
"\.
~
0.2
200 mA
150
100
50
-0.50
-25
25
50
75
100°C
-lamb
Current consumption
versus supply voltage
mA Tamb = 25°C; lq = 0 mA
Rpm versus supply voltage
Tamb = 25°C; R, x C 2 = 100 Ils
%
18
0.6
T.mb " 25°(
I WithJut
intJrnol
stabilization
I
I
/
I
/-
/
I
I
I
I
"
!ambo
with internal
sta~zation f-- -
V
with internal
stabilization -
I -
/
10
6
/
I
12
t-- R"C2=100~s
-0,2 t--
25°C
I
1
without internal
stabilization
F
I
I
-0,4
4
10 12 14
-VS
16 V
-0,6
o
6
10
12
14
16 V
-Vs
445
446
Window Discriminator
TCA965
DIP 14
The TeA 965 window discriminator is particularly suited for control systems as follow-up
and adjusting control device with dead space. It can also be used In measuring systems
for the selection of elements whose dc values should remain within tolerated deviations
from required values.
Pin configuration
...... 1
148
A2
BC
o3
12 Inhibit B
Inhibit A 4
adjust-~ 5
able
reI
10 ~t"r
to
adlu~:t Vrel
V6 6
V7 7
8 V
6
447
TCA965
Maximum ratings
Supply voltage
Input voltage difference between inputs 6. 7 and 8
Input voltage (pin 9)
Output current (pin 2. 3. 13. 14)
Stabilized voltage
output current (pin 10)
Junction temperature
Storage temperature range
Thermal resistane (system-air)
27
15
30
50
V
V
V
mA
Tstg
10
125
-55 to 125
mA
°C
°C
RthSA
80
K/W
Vs
VI
VI
Ia
Ia
1j
Operating range
Supply voltage range
Ambient temperature range
Vs
14.75 to 27
-25 to 85
Tamb
1
~C
Characteristics
Test conditions
Vs = 10 V; Tamb =25 °C
Current consumption
Input current (pin 6. 7. 8)
Input current (pin 9)
Input offset voltage
(pin 6/8. pin 7/8)
Input voltage range (pin 6. 7. 8)
Is
II
-II
Input voltage range (pin 9)
VI
Differential input voltage
LlVI <13V
max
-20
5
20
400
± 10
7
50
3000
20
mA
nA
nA
mV
Vs -l.0
V
1.5
50
~
2.8
5.5
13
13
3.2
6.5
2
V6-(Va-Vg)
(Va+ Vg)-V7
Reference voltage
Stabilized voltage
Temperature coefficient of
reference voltage
Vs
I,ef=O
\'10
Vs>7.9V
Sensitivity of reference voltage
to supply voltage variations
Output reverse current
L output voltage
Ll Vs
Ll Vs
IaH
VaL
Hysteresis (window edges)
Inhibit threshold1)
Inhibit current
V4 • 12
14 • 12
Vhy
3.0
6
0.5
aVs
1) Inhibition occurs if pin 4 and 12 are grounded.
448
typ
V2 • V13 = VaH
VIO
VI
min
18
22
1.5
-100
V
V
V
V
mV/K
3
Ia=10mA
Ia=40mA
mV
10
200
800
35
mV/v
j.1A
mV
mV
mV
V
j.1A
TCA965
Block diagram
10
V7
Lower
window edge
V,tab =2 x Veef
2
4
Inhibit
Va
Window center
12
Half
window
width
V.
t
l-'91
9
V6
Inhibit
9
14
6
Upper window
edge
449
TCA965
Schematic circuit diagrams
Inputs
Pin 9
Pin 6. 7. 8
Pin 4. 12
Outputs
Pin 2. 3. 13. 14
Pin 5.10
R
t--+--o 10
Q
20kl1
]---+--+--<>
20kl1
450
5
TCA965
Suggestions for application
The window discriminator analyzes the input voltage with reference to two limits that are
input as voltages. The window, within which the circuit reacts »well« can be input either by
an upper (V6) and a lower limit (V7), or by the window center (Vs) and depending upon that,
by a voltage .£lV, (Vg), which corresponds to half window width and is available to ground.
A Schmitt trigger characteristic with a small hysteresis is effective at the switching points.
Four output signals are available having the following meanings: input signal inside, outside
the window (good, bad), too high, too low. All outputs have open collectors that can carry
up to 50 mA for the control of small relays, lamps, LEOs. All the usual logic families
can be driven directly requiring only few external components.
Additionally, the Ie contains a reference voltage source with adjustable amplifier {Vred for
the generation of various reference voltages (Vstab) for the inputs. The reference voltage
source is, to a large extent, independent of temperature and supply voltage. For stabilization
purposes, it requires a capacitor of up to 10 !-IF (electrolytic capacitor) to ground at pin 10.
Truth table (for block diagram in connection with application circuit I and II).
V,
Outputs
Application circuit I
Application circuit II
V,= Va
Va< (V7- V9)
Va> (V6+V9)
(V6+ Vg ) > VB> (V7- Vg )
V6+ Vg- - -upper
V,=V617
V617 > (Va+ Vg )
V617 < (Va- Vg )
window edge
V7- V9 - - -lower
window edge
(V6+V9)-(V7- Vg)--
(VB+ V9 ) > V617 > (VB- Vg)
VB- - -window center
Vg-
-
-halfwindowwidth
(to ground)
pin
2
14
13
3
L(H)
H(H)
H(L)
L(H)'1
H(H)
L(H)
H(L)
L(H)21
H
H
L
H
Values in brackets referto
external inhibition via pin 4
and pin 12
11 inhibition pin 4to ground
21inhibition pin 12toground
- - -window width
451
TCA965
Application circuit I
Outputs: pin
pin
pin
pin
2 »below«
3 »outside«
13 »inside«
14 »above«
,--------------,
I
I
I
I
I
I
I
I
+Vs
-~
S1
'2
n
10
S2 S3
l1412
I
I
6
r2-4----;Q2
~
1-"-3-4----;Q3
7
TCA 965
T'3
im
V;~-c=r~~-+----~6
1-'1,,-3+-----1 Q13
I
I
I
I
Q14
1-'14"'-+_ _ _-1 Q14
I
I
9
L _____,___ _ ---~
Outputs
VQ
I~i i
r-------+I--~PI-n~2
I below
o
I
I
I
I
I
hnn
-i
o~
I
I
I
I
o
---'------.A
I
I
V7: lower threshold
Vs: upper threshold
V9: OV
VI: at pin 8
Outputs pin 2 and pin 14 can be
inhibited externally and are then H.
I
I
I
V7
V6
Lower
Upper
window edge
v. - 0
452
Inside
utside
Pin 3
~
--.:- V
o
above
~O
VJ - VB
Input voltage
TCA965
Application circuit II
Outputs: pin
pin
pin
pin
2 »above«
3 »outside«
13 »inside«
14 »below«
,-------------,
I
I
S1
C
S2S3T'
(2
I
I
108. 11412
+Vs
I
I
8
I
I
IL-<__- - - I Q3
I
I
em
TeA 965
~+-------I
I
I
I
I
Q13
Q14
Il:!-------j Q14
I
I
L_______ _ ----~
Outputs
VQ
1
I
I
+-_...,1,..---::
__
:
I
II
a
0
1
~
I
Pln14
below
1
:
:
I
I
I
above
~
I
I
I
1
VB: window center
V9: ± half window width
VI: pin 6 and pin 7 connected
Pln13
~
a
:
Inside
I
I
Vg
i
Vg
I outside
~L.iful
I
I
I
I
1
VB-V9
~B
VB'V9
lower
I
Upper
window edge
-t-I'v
a
i
I
L i
a--.J · i·
Outputs pin 2 and pin 14 can be
inhibited externally and are then H.
•
~=V617
Input voltage
I
I
Window center
453
TCA965
Examples of circuit-board design for application circuits I and II
The inputs of the TCA 965 window discriminator have a Schmitt-trigger characteristic.
With an input voltage that crosses the switching threshold very slowly there is nevertheless
a risk of the output concerned going into oscillation before it clearly assumes the new
switching state. The following circuit boards were designed specially to allow for this factor
and offer a maximum possible safeguard against oscillations.
The causes of the undesired response are as follows:
1. Feedback effect of the switched load on the window-edge voltage through loading or
unloading of the supply Voltage.
2. Hum voltages that are superimposed on the input signal or the window-edge voltages
derived from the supply voltage.
3. Unfavorable routing of the tracks on the circuit board with the voltage dividers for
the window edges connected to a point of the grounding that alters in potential as a
result of load variations. Pin 1 of the TCA 965 can take a load current of 2 x 50 mA to
ground.
Remedies for 1
Boundary conditions for non-oscillating operation
Application circuit I
Vs = k . Vs, V7 = k' . Vs
Application circuit II
Va = k . Vs , Vg = k' . Vs
Condition
k· LlVs < Vhymin
k' . LlVs < Vhy min
Condition
(k + k') . LlVs <
Vhymin
If these conditions are not fulfilled, no holding up of the window-edge voltages with capacitors
will help. Instead one of the following three measures must be taken:
use of Vstab for deriving the window-edge voltages,
•
isolation of the supply voltage V's for the load from the supply voltage Vs of the TCA 965,
•
increase of the edge hysteresis according to the technical note on the TCA 965.
454
TCA965
Remedies for 2
Boundary condition
Vhum pp/2
<
Vhy min
What decides fulfilment of the boundary condition is, depending on the particular application
circuit, the sum of the hum voltages affecting the comparator concerned. The following
interference suppression measures are suggested:
filtering of the input and window-edge voltage,
increase of the edge hysteresis 1).
Remedies for 3
The circuit-board suggestions for the two application circuits have optimal grounding to the
voltage dividers for the window edges with filtering of the supply voltage directly on the IC.
If several of the above-mentioned causes occur simultaneously, the remedies should be
applied in the given sequence.
Output wiring
There are additional driver stages at the outputs of the TCA 965 as shown in the following
diagram for switching load currents up to 1 A (outputs 0)
- - - - - - - - - - - - ,I.Vs
TeA 965
I
I
10.
I!>50mA
Is1A
R~
1) Outputs 2. 3.13.14
455
TCA965
Circuit board and component layout
Application circuit I
02
03
014
013
456
TeA 965
Circuit board and component layout
Application circuit"
.L
a2
a3
a14
a13
457
458
Power Operational Amplifier
Preliminary data
TCA1365
TO·220
The TCA 1365 is a power op amp in a plastic power package similar to TO 220. At maximum
supply voltage of ± 21 V it delivers a high output current of 3.5 A. The op amp is protected
against short circuits and thermal overload.
Features
•
•
•
•
•
•
•
•
High peak output current up to 3.5 A
High supply voltage LIp to 42 V
Suitable
to gain of 1
Thermal overldad protection
Iniernal power limitihg
External compensation
Inhibit input (TIL-compatible)
DC short-circuit protection to +Vs and -Vs
up
Applications
• Power comparator
• Power Schmitt-trigger
.. Speed control of dc motors
I} Power buffer
Pin configuration
Compensation
+Input
~---o
Output
-Input
Inhibit
Pin 4 is electrically connected to cooling fin.
459
TCA1365
Maximum ratings
Supply voltage
Differential input voltage
Supply current
Ground current (min.lmax.)
Output voltage
Peak output current
Current pin 3, 7
Junction temperature
Storage temperature range
Power dissipation
(at Tc = 85°C)
Thermal resistance (system-case)
Vs
±21
V1D
±Vs
Is
IGND
4.0
-4.0 to +3.5
Va
la
13•7
7j
Vs +1
V
V
A
A
V
A
mA
°C
°C
Tstg
Ptot
3.5
5
150
-50 to 150
13
RthSC
5
K1W
Vs
±3 to ±20
-25 to 85
V
°C
W
Operating range
Supply voltage
Case temperature
460
Tc
TCA1365
Characteristics
Test
circuit
Vs =±15V, Tc=25°C
Open-loop supply current consumption
Input offset voltage
Input offset current
Input current
Output voltage
RL = 12 C, ( = 1 kHz
RL = 4 C, ( = 1 kHz
Input resistance
(=1 kHz
Open-loop voltage gain
(= 100 Hz
Common-mode input voltage
Common-mode rejection
Supply voltage rejection
Temperature coefficient
of VIO -25 ~ Tc~85·C
Temperature coefficient
of 110 -25 ~ Tc~85·C
Slew rate of Vo for noninverting operation
Slew rate of Vo for
inverting operation
Disturbance voltage
referred to input DIN 45405
Short-circuit current
(S1 closed)
(S2 closed)
Open-loop supply current consumption
(S3 open; V3 ~ 2 V)3)
Is
VIO
110
II
1
2
3
3
Vopp
Vopp
4
RI
min
typ
max
20
40
10
100
1
-10
-100
0.2
mA
mV
nA
IJ.A
4
±13.0
±12.5
1
±13.5
±13.0
5
V
V
MC
G vo
5
70
80
dB
~c
kCMR
kSVR
aVlo
6
6
7
2
+13/-15
70
-70
+13.5/-15.1
80
-80
50
V
dB
dB
IJ.V/K
ano
3
0.4
nA/K
SR
8
0.5
V/lJ.s
SR
9
Vd
1
0.5
2
Isc
Isc
Is
5
VllJ.s
IJ.V
0.75
-0.75
1.5
3.5
A
A
mA
2
30
0.5
5
50
Inhibit input (pin 3)
V3 for amp off }
V3 for amp on
3)
Turn-on time lo~ 1 A
Turn-off time Io~ 1 A
1) 53 open
2) 54 closed
3) referred to
V30H
2
V30n
tdon
fdoff
~}1)
IJ.s}
j.Ls
2)
-Vs
461
TCA1365
Test circuits
Figure 1
Open-loop supply current consumption; disturbance voltage
Va
Is
51
I s(
10
100k0
Ft
S2
10k0
200nF
10k0
- Vs
Figure 2
10
T
220nF
4711
- Vs
462
Sl to S4 as shown
unless otherwise specified
Input offset voltage, temperature coefficient of VIO
>--_--~----<>VQ
4711
7,50
Va = 100 VIO
TCA1365
Test circuits
Figure 3
Input offset current; input current, temperature coefficient of 110
+Vs
51
220 pF
>----4>---1~---o
4,5V
I
Va
4,7kl1
1220"'
10011
81 open - 82 closed: 11- = 1
:0
~
82 open -81 closed:
II+=~
81 open - 82 open:
110 = 1v~O
1 M..
81 closed - 82 closed: offset alignment
Figure 4
Output voltage, input resistance
+
Vs
T
220nF
-Vs
8 closed:
to measure VQpp
8 open/closed: to measure RI
463
TCA1365
Test circuits
figureS
Open-loop voltage gain
+Vs
10kQ
V;
Gvo
100kQ
-I 20 log 101 .!SL
I
VI
10kQ
100Q
Va
10kQ
lQ
8,2Q
10Q
1
20nF
,= 100Hz
Figure 6
-Vs
Common-mode voltage gain Gvc
Common-mode rejection kCMR (dB) - Gvo (dB) --Gvc (dB)
+Vs
3V
'.100Hz
464
-Vs
TCA1365
Test circuits
Figure 7
Supply-voltage rejection
5611
.----c:::J------~-~IIr--~---<>~
47\1
111
8,211
T
220nF
Figure 8
Slew rate for non-inverting operation
, - - - - - - - t - - - - - - - - - o Vs= 30V
33011
220pF
10kl1
15VtO,3V
10kl1
33011
91 kl1
8,211
465
TCA1365
Test circuit
Figure 9
Slew rate for inverting operation
100kll
220pF
10kll
1000 ~F
III
15V±O,3V
T
220nF..L
466
8,20
TCA1365
Safe o~erating area of output stage
Output current versus collector
emitter voltage
A
Maximum permissible power
dissipation versus
case temperature
te =25°C
W
4~-~-~--_-~-~
25
10
P.y 20
t
t
1\
'\
15
\
10
1\
\
5
10
20
30
40
so
1\
\
o
V
25
-25
50
Is
t
75
mA Te =25°C
Input current versus
case temperature
nA Vs =±15V
25
250
v
20
V
100
125
150 °
--Te
-VeE
Supply current versus
supply voltage
\
r- I-Ir 200
I-- t--..
..... 1--
I-- t--
Vl/
15
1/
150
17
10
I
---- -
100
-- j--- j---
50
I
o
o
2
4
6
8 10 12 14 16 18 20 V
-±Vs
o
-25
o
25
50
75
100
°c
--Te
467
TCA1365
Open-loop voltage gain
versus frequency
Phase response
versus frequency
dB Tc=25°C; Vs-±15V
Tc =25°C; Vs =±15 V
100
180
90
160
T::
-rp 11.0
1\
1 120
1
100
2
1.0
3
1\
V
~
10 3
10'
I)
~k
20
1\
10 2
I)
1.0
10
10'
1
60
20
o
112
80
1\
30
II
J
60
50
II
o
10 5 10 6
-f
10 2
107 Hz
10 3
10 4
10 5
10 6
107 Hz
---f
1: C5-6 =220 pF; 2: C5-6 = 100 pF; 3: C5-6 =0 pF
Saturation voltage versus
output current
Common-mode rejection
versus case temperature
V Tc=25°C
dB Vs =±15 V
5
+VS-Vo
90
or
-vsfVO I.
1\
\
1,\
v
1\
80
V
1"-
___ l",,)'"
V
468
"
75
o
o
4A
-In
-25
I\.
o
25
I'-
50
-Tc
75
100°C
Stepper Motor Drivers
Preliminary data
TCA1560
TCA 1561
DIP18
SIP9
The TCA 1560/61 is a bipolar monolithic IC designed to control the motor current in one phase of
a bipolar stepper motor.
It has TIL compatible logic inputs and contains a full-bridge driver with integrated, high-speed
clamp diodes and chopper·operated dynamic motor current limiting. The nominal current is infinitely variable up to 2 A with a control voltage. Using minimum external components and asingle
supply voltage, two TCA 15611Cs form a complete and directly MC·drivable system for two-phase
bipolar stepper motors. TCA 1560 in DIP 18 package is functionally identical but with an output
current up to 1A.
Features
•
•
•
•
2 A peak current
high-speed integrated clamp diodes
low saturation voltages
thermal overload protection with hysteresis
469
TCA1560
Pin configuration
(top view)
Q1
18
Phase Input
17
Enable Input
16
Actual Current
4
15
GND
Vs
14
GND
13
Sync Input IRC
12
Nominal Current Input
11
Q2
9
Must be Connected
to Pin 6
10
Pin description
Pin
1
2
3
4
5
6
7
8
9
10-18
470
Function
Output 01
Phase input
Enable input
Actual current
Supply voltage
GND
Sync inpuVRC
Nominal current input
Output 02
Ground: must be connected to pin 6
TeA 1561
Pin configuration
01
1
Phase Input
Enable Input
Actual Current
4
GND
o
Sync Input / RC
Nominal Current Input
02
Pin description
Pin
Function
1
Output 01
Phase input
Enable input
Actual current
Supply voltage
2
3
4
5
6
7
8
9
GND
Sync inputiRC
Nominal current input
Output 02
The cooling fin is connected internally to pin 6 (ground),
471
TCA1560
Maximum ratings
Supply voltage, pin 5
Supply current, pin 5
Is
Output voltage, pins 1, 9
Output peak current, pins 1, 9
10
Vs
Va
Input voltage, pins 2, 3, 7, 8
Output current, pin 4
Voltage, pin 4
14
Ground current, pin 6
16
Chip temperature
Storage temperature
VI
V4
Tc
Tslg
min
max
-0.3
0
45
1.25
V
A
-1.5
-1
Vs +1.5
1
V
A
-0.3
-0.003
-0.3
1.25
5
-40
150 1)
125
DC
DC
70
15
K/W
K/W
38
85
5
V
DC
V
6
V
A
V
A
Thermal resistance
System-environment
System-package
(measured at pin 14)
RthSA
RthSC
Operating range
Supply voltage, pin 5
Package temperature
Input voltage, pins 2, 3, 7
1)
Vs
Tc
VI
10
-25
ICs provide optimal reliability and service life if the junction temperature does not exceed 125°C in operation.
Operation up to the maximum permissible limit of the junction temperature at 150 °C is possible in principle. It
should be noted, however, that exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
472
TCA1560
Characteristics
Tc =25°C; Vs=24V
Test conditions
Supply current, pin 5
Standby current consumption, pin 5
Is
Is
VI3 = VIH
VI3 = VIL
VOH
VOL
lIas I
110 I =0.5 A
110 I =0.5 A
tT
figure 1
ID= 1 A
min
typ
max
18
0.5
30
1
mA
mA
1.7
1.1
300
1.0
1.4
V
V
Outputs, pins 1, 9
Output voltage: source
Output voltage: sink
Reverse current
Phase dead time
Forward voltage of clamp diodes
VD
0.3
0.1
~A
~s
V
Inputs: enable, pin 3
and phase, pin 2
H input voltage
L input voltage
H input current
L input current
Rise and fall time
VIH
VIL
IIH
-IlL
V
V
2
VIH =5 V
VIL =0 V
0.8
100
100
2
50
tro t f
~A
~A
~s
Nominal current, pin 8
Regulating range
Input current
Input offset voltage
VI8
-118
V'(8_4)
0
VI8 =OV
figure 5
I
I
V
2
5
0
I
~A
I
mV
Actual current, pin 4
Regulating range
Turn-off delay
V'4
td
1 figure 3
10
12
2
3
V
100
0.9
2
2.0
0.8
kHz
~s
Sync input/RC, pin 7
Sync frequency
Duty cycle
Rise and fall time
Output current, pin 7
Trigger threshold, pin 7
Charging limit C7
Off period
Dynamic input resistance, pin 7
v
t r, t f
duty cycle: 0.5
f=40 kHz
-107
VL7
1.2
figure 2
2.2
VG7
Is
Ri7
1
0.1
figure 4
V7 =1.5V
1.6
0.6
2.4
~s
mA
V
V
64
~s
1
kQ
473
TeA 1561
Maximum ratings
min
max
-0.3
0
45
2.5
V
A
Supply voltage, pin 5
Supply current, pin 5
Is
Output voltage, pins 1, 9
Output peak current, pins 1, 91)
Ia
-2
-2
Vs +1.5
2
V
A
Input voltage, pins 2, 3, 7, 8
Output current, pin 4
Voltage, pin 4
VI
14
V4
-0.3
-0.003
-0.3
6
2.5
5
V
A
V
Vs
Va
Ground current, pin 6
16
2
A
Chip temperature 2)
Storage temperature
Tc
Tstg
150
125
°C
°C
Thermal resistance
System-environment
System-package
RthSA
RthSC
70
8
KlW
KlW
-40
Operating range
Supply voltage, pin 5
Package temperature
Input voltage, pins 2, 3, 7
10
-25
38
85
5
1) In case of chopper operation with peak currents exceeding 1 A, one (liode per output (pin "
9) has to be
connected with the cathode to the supply voltage (pin 5)
The reverse-recovery time 01 diodes must not exceed 200 ns.
2) )Cs provide optimal reliability and service lile if the junction temperature Ques not exceed 125 'c in operation.
Operation up to the maximum permissible limit of the junction temperature at 150 'C is possible in principle.
It should be noted, however, that exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
474
TCA 1561
Characteristics
Tc =25°C; Vs =24 V
Test conditions
Supply current, pin 5
Standby current consumption, pin 5
min
= VIH
Is
Is
V I3
VOH
IIo l=0.3A
I 10 I = 1.3 A
110 I =0.3 A
110 I = 1.3 A
V I3
typ
max
18
0.5
30
rnA
rnA
1.6
1.9
1.0
1.4
300
1.0
1.4
V
V
V
V
f.LA
f.Ls
V
0.8
100
100
2
V
V
f.LA
f.LA
f.Ls
Outputs, pin 1, 9
Output voltage: source
Output voltage: source
Output voltage: sink
Output voltage: sink
Reverse current
Phase dead time
Forward voltage of clamp diodes
VOH
VOL
VOL
I los I
figure 1
10= 1 A
IT
VD
0.3
0.1
Inputs: enable, pin 3
and phase, pin 2
H input voltage
L input voltage
H input current
L input current
Rise and fall time
2
VIH
VIL
IIH
VIH = 5 V
VIL =0 V
-IlL
50
Ir,lf
Nominal current, pin 8
Regulating range
Input current
Input offset voltage
0
V I8
-118
=0 V
figure 5
2
5
V I8
VI 18-41
I
I
0
I
I
V
f.LA
mV
Actual current, pin 4
Regulating range
Turn-off delay
V I4
Id
I
0
figure 3
1
12
2
3
V
f.Ls
100
0.9
2
2.0
0.8
kHz
Sync inpuVRC, pin 7
Sync frequency
Duty cycle
Rise and fall time
Output current, pin 7
Trigger threshold, pin 7
Charging limit C7
Off period
Dynamic input resistance, pin 7
v
duty cycle: 0.5
1=40 kHz
1
0.1
Ir, If
-107
Vt7
1.2
figure 2
2.2
V G7
Is
R;7
figure 4
V7 = 1.5 V
1.6
0.6
2.4
64
J.ls
rnA
V
V
J.ls
kQ
475
TCA1560
TCA1561
Circuit description
Outputs
Outputs 01, 02 (pins 1, 9) are fed by push-pull output stages. The two integrated clamp
diodes, referred to ground or supply voltage respectively, protect the IC against flyback
voltages from an inductive load.
Enable
Outputs 01 and 02 are turned off when voltage \.13 sO.8 V is applied to pin 3. The supply
current then decreases, typically to 500 i-lA. The same occurs if pin 3 is open. The sink
transistors are turned on when \.'13 ~2 V.
Phase
The voltage at pin 2 determines the phase position of the output current. Output 01 acts as
sink for Vl2 sO.8 V and as source for 1\2 ~ 2 V.
Similarly output 02 acts as
sink when \.12 ~2 Vand
source when \.12 sO.8 V
The sink transistors are current-chopped. An internal circuit avoids undesired cross-over
currents at phase change.
Nominal current input
The peak current in the motor winding is determined by the voltage at pin 8. A comparator
compares this with the voltage drop at the actual current sensor at pin 4. If the nominal
current is exceeded, the output sink transistors are turned off by a logic circuit.
Sync inpuVRC
Outputs are turned on by a signal at pin 7. Two operation modes are possible:
Synchronizing by a fed-in TTL signal or free running with the external RC combination.
Free-running operation
When the supply voltage is applied, capacitor C7 at pin 7 charges to a limiting voltage,
typically 2.4 V. With increasing current in the motor winding, the voltage rises at the actual
current sensor R4 (pin 4). After exceeding the predetermined value at the nominal current
input (pin 8) the comparator, in conjunction with pulse suppression, resets an RS flip-flop.
The logic turns off sink transistors T3 and T4. C7 ceases charging and the parallel resistance R7 then discharges C7 . The sink transistors remain turned off until the lower
threshold voltage of the Schmitt trigger is reached. This off period is thus controlled by the
time constant ts = R7 X C7• After the lower trigger threshold has been passed, the
monoflop is triggered by the falling edge of the Schmitt trigger output and, provided the
voltage at the actual current sensor (pin 4) is lower than the ndihinal value at pin 8, the RS
flip-flop is reset. The logic circuit then turns on the sink transistor T3 or T4 and recharges
capacitor C7• If the voltage at pin 4 rises above the comparator value at pin 8, the sink
transistors T3 and T4 are turned off again. Turn-on cannot be repeated until capacitor
C7 has discharged to the lower trigger threshold, the discharge time being a function of
R7 and C7 ·
476
TCA1560
TCA1561
Synchronous operation
If a TIL level sync signal is fed to pin 7, the negative edge sets the RS flip-flop, via the
Schmitt trigger/monoflop combination, provided that the voltage at pin 4 is below the
nominal value at pin 8. As in the free-running operation mode, the relevant output
transistors become conducting. Similarly they are cut off by resetting the RS flip-flop once
the voltage at pin 4 is higher than the nominal value at pin 8.
Pulse suppression
In all cases the pulse suppression circuit eliminates positive pulses, typically of 0.5 f.ls
duration, .at pin 4. These can result from cross-over currents in chopper operation through
the integrated clamp diodes. As a result, the voltage at pin 4 rises well above the nominal
value, and without pulse suppression this would lead to dynamic current limiting. The
duration of these basically unavoidable cross-over currents is of the same order of magnitude
as the reverse-recovery time of the clamp diodes.
Temperature safeguard
If the temperature of the Ie rises to unacceptably high levels, the final stages are turned
off.
477
:!;j
+24V
TTL Level
10mV
R4 >O Q
low voltage level, input open
= high voltage level
=
transistor turned off
= transistor conducting
..
=
/
=
transistor conducting with current limiting turned on
output high ohmic
479
TCA1560
TCA 1561
Pulse diagram 1
Phase dead time
Pin3T:~
VIZ
Pin2
t
H
,....--------...,
1
L----I
\ tr=tf~50ns
Val
Pin 1
t
~----------------1.----------50%
Vaz
Pin 9
t
~--------~------~--50%
V..
Pin t.
t
~----~~--------~----~~--50%
_t
Figure 1
480
TCA1560
TCA 1561
Pulse diagram 2
Trigger threshold
-f
Figure 2
Turn-off delay
Val
Pin 9
t
50%
-f
Pin 4
Rise Time
;?:50 mVllls
-f
Figure 3
481
TCA1560
TCA 1561
Off period ts
= f(C 7)
liS
~
1000,----.-------.----.-----,------,,----,------,
R7 =100 kfl
56 kfl 27 kfl
1
500~--~------~--~----+_--~~~~+-~--~
200~--_+------+_----~~_+~~--~--~~----~
100 \------f-------+---.~_+_----,l-'-------_+_+-The typical Off- Peri od
is Calculated
from the Equation:
50 \------f-----:-r---+-?L--+-----,l-'--+----- t, =R7" [7" In ( VG7 .f. Vl7 )
t,'" ~'[7' 1,4
20~~_+-,~--~--~~--_+------+_--~------~
OL-~_L~~
_ _L-___ L_ _ _ _L __ _ _ __ L_ _ _ _L __ _ _ _~
0,1
0,5
10
Figure 4
Control range, input offset voltage
Pin 8
Tov
tI =+1~0m~v~::::;;;.,.,
4
Pin 4
r___
-10 mV
Pin 9
Figure 5
482
--f-I
-t
20 nF
TCA1560
TCA 1561
Application circuit
+24 V
+ Vs
VlA
Enable 3
5
1 01
VIA
Phase 2
Nominal
Current 8
TeA 1560
rCA 1561
A
9 02_
TTL Drive
Signals
HI
+ Vs
VlS
Enable 3
- IA
5
1 01
VIS
Phase
VIS
Nominal
Current 8
2
TeA 1560
TCA1561
B
Isl
9 02
0
Hl
483
TCA1560
TCA1561
Pulse diagram for application circuit
H
VlA
U
L
---
U
L
U
U
---
VlA
H
V2S
~---,gJ
L
toi~
U
---
H
VlS
IX!
I8L
_=- ----c><:I
______r~~~~~~~~~~~~~~__-_-__-__J_~
IX!
IX!
IX!
_________________________
oil-""""--------'...,..---------r-L-~--r---'--
ItA
-0.5
-- -
lL...-_.....I
[f'~j------Lr==J--~,_----~.~r=------------~L---~_r----._~----~~
-~~~
=tJ
[
I
Standby
484
Half-Step Driving 1=
- -
0-.'6 A
I
Half-Step Driving!: 1A
Dual Power Operational Amplifier
TCA 2365; A
Preliminary data
SIP9
DIP 18
The TCA 2365 is a dual power op amp in a SIP 9 package. The IC contains two identical op amps,
each supplying a high output current of 2.5 A at supply voltages between ± 4 V and ± 15 V. Both
amplifiers can be disconnected simultaneously (tristate; ZQ '" 4 kn) via an inhibit input. Integrated
protective circuits protect the outputs against short circuit to + Vs and - Vs and prevent ather·
mal overloading of the IC.
Features
Applications
•
•
•
•
•
•
,. Power comparator
• Power Schmit! trigger
• Speed control of dc motors
High output current of 2 times 2.5 A
Large supply voltage range, B V to 32 V
High slew rate 4 V/J.1s
Outputs entirely protected (dc short-circuit proof)
Thermal overload protection
Inhibit input enables "tristate" outputs
Pin configuration TCA 2365 (TCA 2365 A)
- Input 1
+
Input 1
Ampl
output 1
Amp 2
Output 2
3
Inhibit input
- Input 2
+
Input 2
4 (10-1BI
Pin 4 is electrically connected to cooling fin.
(Establish external connection between pin 4 and pin 10-18)
485
TCA2365;A
Maximum ratings
Supply voltage
t=QO ms
Differential input voltage
Output voltllge range
Peak outPLIt current
Supply current
Junction temperature
Storage temperature range
Thermal resistance
System-air
System-case
TCA2365
TCA2365~
Vs
Vs
± 16
± 1&
±16
±18
V
"io
±Vs
±Vs
-Vs -1 to +Vs +1
V
V
Ia
Is
±2.5
5.5
150
-55 to 150
A
A
Tstg
±2.5
5.5
150
-55 to 150
RthSA
RthSc
65
6
60
10
KlW
KlW
Vs
Tc
±4to±15
-25 to a5
±4to±15
-25 tp 85
V
DC
GVmin
10
10
dB
Va
7j
Y
DC
DC
Operating range
Supply voltage
Case temperature
(Ptot = 10.0 Wl
Voltage gain
486
TCA2365jA
Characteristics
Test
circuit
Vs =±10 V; Tc -25°C
Open-loop supply current consumption
Sl in position 1
Sl in position 2
Input offset voltage
Input offset current
Input current
Output voltage
RL = 120;#-1 kHz
RL = 40;#-1 kHz
RL -470 0; # - 50 kHz
Input resistance
(#-1 kHz)
Open-loop voltage gain
(#-100 Hz)
Common-mode input voltage range
Common-mode rejection
Supply voltage rejection
Temperature coefficient of VIO
-25 DC STcS+S5DC
Temperature coefficient of 1 10
-25 DC STcS+S5DC
Slew rate of Vq
for non-inverting operation·
Slew rate of Vq
for inverting operation·
Disturbance voltage referred to Input
Inhibit input
(referred to -Vs)
Va for IC turned off
Va for IC turned on
"""j
T"m""
111;91>1~
Turn-off lIme
I 11;9/<1 A
typ
max
30
5
50
8
10
100
1
11
1
1
2
3
3
VQPP
VQPP
VQPP
RI
4
4
4
4
±8.5
±8.0
±9.0
±S.5
±6.0
5
V
V
V
MO
Gvo
5
70
SO
dB
VIC
6
6
+71-10
+7.5/-10.5
70
70
80
SO
50
V
dB
dB
ILV/K
Is
ISM
VIO
1 10
kCMR
ksvR
-10
-100
0.25
rnA
rnA
mV
nA
ILA
IlVIO
7
2
11110
3
0.4
nA/K
SR
S
4
V/lLs
SR
9
4
Vd
1
3
V/lLs
ILV
Va oil
Vaon
tdon
referred
to Vaoff/on
S2 and S3 in position 2
min
t dOff
1.0
6
0
3.0
2
5
V
V
ILs
15
30
ILs
487
TCA2365;A
Test circuits
Figure 1
Open-loop supply current consumption, disturbance voltage, turn-off voltage
+
Vs
10kS'l
I
220nF
,--
5
2
10kS'l
3
1
~~
10kll
7
r-----t...-J"
I
100 kll
~
V
~
52
1
Val
53
9
Va9
V
4 10-18
100 kll r
1S'l
10 kill
T
Switch as drawn unless otherwise specified
488
[ 1S'l
220nF
1 4 S'l
~
TCA 2365; A
Test circuits
Figure 2
Input offset voltage, temperature coefficient of VIO
r--------j +
1
I
rCA 2365;A
>-~
__
~_---o
111
4.7 kll
4m
I
1
Va
T
220nF
- Vs
Va =100 x VIa
Figure 3
Input offset current, input current, temperature coefficient of 110
1MII
Sl
>----+--0 Va
111
4.5V
I
T
4.7kll
220nF
10011
- Vs
81 open - 82 closed:
11- = _V0 -
82 open - 81 closed:
11+ = ~
81 open - 82 open:
110 = 1V~Q
lMO
1 MO
81 closed - 82 closed: offset alignment
489
TCA2365jA
Test circuits
Figure 4
Output Yoltage, input resistance
T
1
4,7 kl1
S closed :
to measure
220nF
Va pp
S open / closed: to measure RI
Figure 5
Open-loop Yoltage gain
+Vs
10kn
100kn
V,
10kl1
lOOn
Va.
10kl1
111
T
1011
f=100Hz
-Vs
Gvo = 1 20x1 ogl0l
490
220nF
~I
8,211
TCA2365;A
Test circuits
Figure 6
Common mode voltage gain G vc
Common mode rejection kCMR (dB) = G vo (dB) - Gvc (dB)
+ Vs
4.7 krl
- 1
10rl
"2"
Va
TCA2365;A
8.2r1
1(/
T
220nF
f=100 Hz
Figure 7
- Vs
Supply voltage rejection
56r1
,---c:::J--------1>------jII--~-------+-1-lllf--o-----, VQ
8.2Q
T
220nF
220nF
8.2rl
TCA2365;A
mA
Supply current
supply voltage
Is
Input current versus
ambient temperature
and ISM versus
nA
250
50
.......
[s
I
l"- I'-,..,
40
I'- I''//
30
/
V
V
20
150
100
50
10
--
I-I--
o
r-....
o
2 4
6
o
8 10 12 14 16 18 20 V
-25
o
25
50
75
100 DC
--_._--- tVs
Open-loop voltage gain
versus frequency
dB Tc=25 DC; Vs=±10V
100
r
6
90
80
r\
70
60
50
40
\
30
20
1\
10
--f
493
TCA~365;A
Phase response versus
frequency
deg,TC -25°C; Vs-±10V
210
Common-mode rejection
versus ambient temperature
dB
90
- cp 180
t 150
85
120
\
II
\
1\
90
80
II
60
\
1/
\
30
75
- 25
o
25
1\
\
1\
75
50
100
O(
-f
Max. permissible power dissipation
versus case temperature
W
25
Max. permissible powllr dissipation
versus case temperature
TCA2365
TCA2365 A
W
25
~ot
~ot
20
t
20
\
.",
1\
15
15
\
\
10
10
\
\
'"I'"
'"'"
5
\
o
-25
494
\
25
50
75
100 125 150 0 (
-Tc
a
-25
a
25
50
75
'"
I'"
100 125 150 0 (
TCA 4500 A
Stereo Decoder
DIP 16
The TCA 4500 A is a phase-locked loop stereo decoder which Incorporates a variable channel separation control. In this IC, the sensitivity to the third harmonics of both the pilot and
subcarrier frequencies has been eliminated due to the use of appropriate, digitally generated
waveforms in the phase-locked loop and decoder sections.
Features
• Low distortion
• Excellent rejection of ARI subcarrier and pilot tone harmonics
• No need for coils
Maximum ratings
V
V
TSl9
16
30
100
10
150
-40 to 125
R1hSA
90
K/W
Supply voltage
Lamp drive voltage (lamp OFF)
Lamp current
Channel separation control voltage
.Junction temperature
Storage temperature range
h
Thermal resistance (system-air)
Vs
V7
V11
7j
mA
V
DC
DC
Operating range
Supply voltage range
Ambient temperature range
Vs
Tomb
18 to 16
-25 to 85
I~C
495
TCA4500A
Characteristics
(VS
=12 V;
Tomb -25°C; "'(MPX) -2.5 Vpp; fmod -1
kHz; Vpllot -10% \1;)
min
Current consumption (17 - 0)
1'6
Stereo channel separation
unadjusted
optimized on other channel
a
aopt
30
40
Monaural voltage gain
THO at 2.5 Vpp
THO at 1.5 Vpp
G
THD
THD
0.8
Signal-to-noise ratio in acc. with DIN 45405
rms value 20 Hz -15 kHz
Frequency rejection 19 kHz
38kHz
Pilot tone harmonic rejection 57 kHz ARI
Subcarrier harmonic rejection 76 kHz
114 kHz
152 kHz
aSIN
aSIN
Input voltage for stereo switching threshold
(19 kHz input signal for lamp "ON"
Hysteresis for stereo switching threshold
Quiescent output voltage change
with mono/stereo switching
Channel separation control voltage
3 dB separation
30 dB separation
Minimum channel separation (Vtt - 0 V)
Monaural channel inbalance (pilot tone off)
Hum suppression
Input resistance
Output resistance
Channel separation control current
Capture range
496
typ
max
35
a
a
a
a
a
a
mA
dB
dB
1.2
0.3
0.2
%
%
85
90
31
50
60
45
50
50
dB
dB
dB
dB
dB
dB
dB
dB
16
6
20
H
mV
dB
.1Vqlo .1Vq,
5
20
mV
Vl1
0.7
1.7
Vltrms
Vl1
12
1
0.3
a
.1Vql.r
ahum
55
Rlt
Rq4,R q5
50
100
±5
dB
dB
dB
kO
0
-300
Itl
.1 fifo
V
V
~A
%
TCA 4500 A
Measurement circuit
Channel
separation control
[8
Stereo
~
Mono
0.221lF
16
12
15
11
10
9
6
1
8
TeA 4500 A
2
3
[6
4
5 Cr
~
Stereo
'/ LED
6.2nF
S.lkn
R7
680n
S.lkn
Vql
Vqr
+ Vs
Pin configuration
Pin No.
Function
1
2
3
4
5
6
7
8
9
10
11
12
Input
Preamplifier output
Left amplifier input
Left channel output
Right channel output
Right amplifier input
Stereo indicator lamp
Ground
Switching threshold
Switching threshold
19 kHz output/channel separation control
Modulator input
Loop filter
Loop filter
Oscillator RC network
Supply voltage + Vs
13
14
15
16
497
~
J>.
co
"
(Xl
i
::I
n
+15V
Stereo
threshold
t~Stereo
indicutor lamp
5601'1
~::;:
4701'1
r-~~------~'~~+15V
~---r-I,III--f--<> Vq r;gh'
100kQ
~
I
I:
f
100kQ
VQteft
-t
~
~
U1
g
l>
TCA4511
PLL Stereo Decoder
DIP 18
The TeA 4511 decodes the transmitter side stereo information in both L and A channels.
Stereo transmission is shown by means of an indicator lamp. A continual blending of mono
and stereo signals is possible. The switching frequencies are controlled by a phase-locked
loop. The stereo decoder can be used in time multiplex (switching) or in frequency multiplex
(matrix) mode of operation.
Features
•
•
•
•
Good channel separation
No need for coils
Automatically adjustable bandwidth
Good suppression of ARI subcarrier and pilot tone harmonics
Maximum ratings
Supply voltage
Lamp voltage
Current for stereo indicator lamp
(V'8 ·ILP;;;' 300 mW)
Minimum values at all pins
Junction temperature
Storage temperature range
Thermal resistance (system-air)
(junction-case)
Vs
VLP
ILP
V
1j
Tstg
R thSA
RthJC
18
18
50
V
V
mA
0
150
-40 to 125
V
°C
°C
78
45
KJW
K/W
Operating range
Supply voltage range
Ambient temperature range
Vs
Tomb
18 to 18
-25 to 85
I ~C
499
TCA4511
Characte.istics farswildl opendion (VS -12 V; Tamb = 25 DC)
min
Total current (FM operation)
81 closed
Total current (AM operation)
81 open
Lamp current adjustment range
(V,8 'ILP~300 mW)
Lamp current short circuit
(V,8 'IIP~300 mW)
typ
max
Is
14
20
mA
Is
10
15
rnA
25
mA
50
mA
1.6
V
V
kg
kg
V
lIP
10
lIP
Input amplifier
Op amp input signal
Op amp output signal1)
Input resistance
Feedback resistance
Reference voltage
V'6PP
V14pp
RI
RF
V16
90
125
10
1.75
VqAFpp
0.9
1.2
1.6
V
VqAFpp
0.45
0.6
0.8
V
1.5
2
kg
V'3
Stereo matrix
Output voltage (stereo)'.6)
for modulated output
Output voltage (mono)2.6)
L or R modulated
Output resistance
Crosstalk attenutation1)
(fAF -1 kHz)
Reduction 19 kHz Test circuit 1
Reduction 38 kHz Test circuit 1
Reduction 57 kHz Test circuit 1
Reduction 76 kHz Test circuit 1
Hum suppresslon3)
Noise voltage 4)
Total harmonic distortion1.6)
(fAF -1 kHz)
Channel balance2)
SWitching noise mono/stereo
S1 closed/open
Rq
8cR
34
40
dB
a19
a38
a57
a76
30
30
30
30
40
32
40
45
40
45
dB
dB
dB
dB
dB
8hum
Vqn
30
THO
80
0.5
jLV
%
B
.dVg,.d V,o
0.5
60
dB
mV
±2.0
18
kg
kHz
kHz
kg
Oscillator
Output resistance for fosc measurement
Oscillator basic frequency
Capture and hold range1)
Balancin9 resistance
(fosc -19 kHz)
Function of the oscillator
S1 closed
Switch off of the osclllator8)
S10pen
Function of the oscillator (118 -10 mAl
500
R8
fosc
Rose
±0.4
13
V18
1.0
fCtH
V18
V'8
200
19
±1
V
0.4
0.9
V
V
TCA4511
Characteristics for switch operation (VS = 12 V;
Tamb
= 25 0c) (cont'd)
min
typ
max
0.5
0.7
3.3
0.9
Phase comparisons
Input voltage1)
Input resistance
Input voltage
V5pp
R5
V5Pp
1.6
V
kQ
V
55
mV
Stereo switch
Threshold stereo ON5)
(f=19 kHz)
Threshold stereo OFF5)
(f=19 kHz)
Hysteresis
30
ViPTpp
ViPTpp
12
15
Hy
3
6
abl
1;4
mV
9
dB
9
I dB
dB
Mono/stereo blending
Mono (VH =Va = 0.5 V)7)
8tereo (VH = Va = 0.9 VF)
1)
abl
1
6
1
Vi pp = 1.2 V MPX; VH ;:; 1 V; 81 closed; fAF = 1 kHz
2) Vipp =1.2VMPX;
81 open; fAF=1 kHz
3) Vs = 12 V + Vn; Vnrms = 200 mY; 200 Hz
4) CCIR DIN 45405; unweighted; 81 open
5) 81 closed
6) After TP with fco = 6.5 kHz; reduction 36 dB/octave
7) V16PP =0.75VMPX;81 closed;fAF=1 kHz
a) The oscillator is switched off, if pin 18 is connected with a voltage;;; 0.4 V or 81 is open.
501
TCA4511
Circuit description (switching operation)
The MPX input signal is corrected in amplitude and phase by an operational amplifier. For
this purpose an RC circuit is connected at pin 15.
Subsequently, the (L+R) and (L-R) signals are processed in separate stages. The (L-R)
signal is demodulated and can be reduced by the factor a through mono/stereo blending.
In the final matrix circuit the aggregate signal (L+R) is added to the demodulated signal a
(L -R) according to the following formulae:
(L+R) + a (L-R) - L(Ha) + R(1-a)
(L+R) - a (L-R) - L(1-a) + R(Ha)
as;
Mono
as;
Blending
1
Stereo
The generated output signals are then forwarded to two external RC low-passes for deemphasis.
The required frequency to demodulate the L - R signal is obtained by a phase-locked loop
(PLL) from the divider. By means of a pilot tone applied to pin 5, the oscillator is synchronized
by phase comparison 1. An additional phase comparison 2 provides mono or stereo information.
Based on this information, the indicator lamp is activated and lights up when a sufficiently
strong signal is present at the input. Moreover, the (L - R) reduction is eliminated.
If switch S1 is open, the IC switches the oscillator off, whereby the stereo switch and the
mono/stereo blending suppress the L - R signal. The supply current is thus reduced. Also,
since the oscillator does not resonate when switch S1 is open, AM receiver signals can be
forwarded without interference via the IC.
If pin 8 is not connected, the oscillator frequency can be measured. For normal operating
functions, the blending voltage VH is applied to pin 8 or pin 8 must be blocked by a capacitor.
Otherwise, cross-talk is affected by the oscillator frequency.
502
TCA4511
Pin configuration
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Function
Ground
Oscillator RC
TP phase comparison 1
TP phase comparison 1
Pilot tone (PT) input
TP phase comparison 2
TP phase comparison 2
fosc outputiSt-Mo blending VH
Output L
Output R
(L+R) input
(L-R) input
Reference voltage
Output op amp
- input op amp
+ input op amp
Supply voltage
Lamp connection/oscillator switch
503
TCA4511
Block diagram
Lamp
Osc switch
18
MPX
Vs
17
input
16
Correction
Op amp
output
RC
15
14
Vrer
13
Inputs
12
11
Output
10
L-R
R
1.5~11
R
1.5kl1
TCA 4511
Re
200kl1
Oscillator
RC
504
4
TP
phase
comparison 1
6
TP
phase
comparison 2
'ascI VH
Output
TCA4511
Test circuit
Switching operation
• Vs=12V
TCA 4511
3 100nF 4
5
8
9
33nF
10nF
V; = ( L.R I • (L - R )HT
•
H
PT
L = 100 %; R = 0 % or
R= 100%; L= 0%
51 open =AM
51 closed =FM
505
TCA4511
Application circuit
Switching operation
+ Vs =12V
S1
R
VHPX
J..
47011
..L
..,...
330nF ~
LED
33nF
3.3kll
~
I
18
17
16
115
14
11
13
10
rCA 4511
2
3
4
7
5
8
~
10nF
S 1 open =AM
S 1 closed =FM
506
33nF
AF Power Amplifier Ie with Thermal Shutdown
TDA1037
SIP9
AF power amplifier designed for a wide range of supply voltages to enable versatile
application in entertainment electronics. The amplifier operates in the push-pull B mode
and is available in the SIP 9 package. The integrated shutdown protects the Ie from
overheating.
Features
•
•
•
•
Wide supply voltage range: 4 V to 28 V
High output power up to 8 W
Large output current up to 2.5 A
Simple mounting
Maximum ratings
Supply voltage
RL ~16
RL ~
RL ~
Q
8Q
4Q
Output peak current (not repetitive)
Output current (repetitive)
Junction temperature 1)
Storage temperature range
Thermal resistance
junction-case
system-air
Vs
Vs
Vs
/q
/q
Tj
Tstg
R thJC
R thSA
V
V
V
A
A
30
24
20
3.5
2.5
150
-40 to 125
°C
°C
112
70
I K/W
K/W
14 to 28
-25 to 85
1
Operating range
Supply voltage
Ambient temperature
Vs
TA
~C
0) May not be exceeded even as instantaneous value.
507
TDA1037
Characteristics
with reference to test circuit
1. \Is = 12 V; RL = 4 0; C 1 = 1000 IlF; fl =1 kHz; TA = 25 DC
Quiescent output voltage
Quiescent drain current
Input DC current
Output power THO = 1%
Vq2
min
typ
max
5.4
6.0
12
0.4
3.5
4.5
6.6
20
4
40
80
43
13+14
/;a
Pq
Pq
2.5
3.5
Voltage gain (closed loop)
Voltage gain (open loop)
Gv
Gvo
37
Total harmonic distortion (Pq = 0.05 to 2.5 W)
Noise voltage referred to input
(t; = 3 Hz to 20 kHz)
Disturbance voltage in acc. with
DIN 45405 referred to input
Hum suppression (thum ~100 Hz)
Frequency range (-3 dB)
C4~ 560 pF
C4 = 1000 pF
THO
Vn
0.2
3.8
Vd
2.5
48
THO = 10%
Input resistance
Bhum
40
40
W
W
10
dB
dB
%
Il Vs
Il V
dB
20.000
10.000
5
RiB
V
mA
IlA
Hz
Hz
Mel
2. Vs=24V;RL=160;C1=220IlF;f;=1 kHz; TA=25 DC
Quiescent output voltage
Quiescent drain current
Input DC current
Output power THO = 1%
THO = 10%
Vq2
11
13+14
/;B
Pq
Pq
4.5
12
18
0.8
3.5
5.0
13
30
8
40
80
43
dB
dB
0.5
15
%
Il Vs
Voltage gain (closed loop)
Voltage gain (open loop)
Gv
Gvo
Total harmonic distortion (Pq = 0.05 to 3 W)
Noise voltage with reference to input
t; =3 Hz to 20 kHz
Disturbance voltage in acc. with
DIN 45405 referred to input
Hum suppression (thum = 100 Hz)
THO
Vn
0.2
5
Vd
3.8
40
Bhum
Frequency range (-3 dB)
C4 = 560 pF
C4 =1000 pF
Input resistance
508
37
40
40
Ria
W
W
!-IV
dB
20.000
10.000
5
V
mA
IlA
I"'
Hz
Mel
TDA1037
Circuit diagram
.-~~--~--+---~~------+_--~~3
6o---------~~_+--+_~~--_+--_+--_+--~~--------~--o2
7o----------+--+_~
R,
8o--C:::::J--{
1.7kO
9o-------+-~~~--+_~_4--~----+_~----------------__o9
Measurement circuit
.---.--------------0.12 V/.24 V
1000
lOOIlF
9
4Q/16Q
100
kQ
S Closed for Noise Measurement
509
TDA1037
Application circuit
T 100~F
30V
100kl1
Vs
12 V
18 V
24 V
40
80
160
220 jJ.F
510
'max
10 kHz
20 kHz
1000 pF
560 pF
TDA1037
Output power versus supply voltage
THO =10%; RL =4,8,16 Q; f=l kHz
W
w
Max. power dissipation versus supply
voltage at sine-shaped driving
f=l kHz;R L =4,8,16Q,THO-10%
I
I-RL -4Q
p
I
I
J J6Q
I I
I I
I
II
I I
) 16Q
I I
I 1I /
5
4
3
!RL=4Q
I
4
/
a
VjV
J ~V
I 11/
// V
V
4
/ / J
VV
/ / I
lL16Q
II /
o
~
12
16
20
24
4
28 V
,;'
8
12
--~
W
4
80
/
/
I
I
1/
JI
1/
2
/'
IJ
1/ r-
"
~
60
/,j
/
f.I f
40
.~--.
":01
q22 ~r-
i
~=12
-
20
8
4
o
-Pq
5
w
/X
10
13+14
'(
16
/f/
12
4
26 V
V
24
20
1/
II- -- - \S=24V,RL=16Q_
V,RL = 4Q
o
24
28
3
I
o
20
Quiescent drain current,
quiescent current of output transistors,
quiescent output voltage
versus supply voltage
rnA
V
16
32
%
'"
16
-~
Total power dissipation and efficiency
versus output power
THO =10%; f= 1 kHz
f- ~Ol"
aQ
J
3
If I
2
II
r6
tl
6
VI
11,/
V
II
~~
/
-
,
_'r« r-
4
2
o
o
4
a
12
16
20
24
28 V
-~
511
TDA1037
Hum suppression versus feedback resistance
'hum
-100 Hz; C s -100 !-IF
a: input short-circuited
b: input open
odB
o
20
40
100
80
60
-t
-10
8hjUm -20
--- ---
-30
,t'--., a
-40
- Rf
120
140
160 11
-- -
Vs=12V
RL=411
r-- r--
"b'- r:::::- ~
-SO
-60
o
-10
If, =24 V
ar:~~
~
---
b' F::::: ~
-40
RL=16Q
-f-
-SO
-60 - -
Max. total power dissipation versus ambient
temperature
W
6
- i --- f--
I
--j f-
4
r--
\
-_ ..
RthJC
- i f--- ._- ---
'\
--
3
~ f--I
---
--
\
f---
\
2
. . . . r---. RthSA
I
I
----
o
-40
512
o
40
\
" ".1.
60
'\
120
160 0 (
1-- e---
TDA1037
Total harmonic distortion
versus output power
f-1 kHz
%
10
THD
I
I
1111
9
I
Vs=12V/4Ik
8
7
5
4
3
~=24 V/1611-~1
2
I
I,
1.'
o
Total harmonic distortion versus frequency
\
Pq=3W
Pq=SOmW
/
~=12V,RL=4Q
r-..
~ ~JIIIII
o
/
5
THD 4
t:
o
.-
l\
Pq= 3W"
Pq=SOmW
~I
~=24V.R =16f!
V
1111
10'
_f
513
TDA1037
Voltage gain versus frequency
Vs =12V;R L =4C
dB
50
i
Gv
"'
-3dB
40
VI
30
I
-3dB
I
20
I
I
1
10
I
I
Ii
o
10. 2
I
'--
1Q1 2·10'
3.5.10- 2 10·'
-,
Bandwidth C3 versus feedback resistance
Vs =12 V; RL = 4 C,Gv -40 dB
C, =5 ·C4
nF
10'
B=~ I-
L..-
j..oJ..-
'8=20kH~
---
I-
17
I
I
:
,
I
-RF
514
10 2 kHz
TDA1037
Output power and voltage gain versus
feedback resistance and input voltage
Vs = 12 V; RL = 4 Q; f = 1 kHz
Q
100
90
RF
t
I
80
,
I
Uv \
70
1/
60
I
V
50
j
VP=50mW
40
/
30
./
20
IJ
/
/
II
P=4W
\
/
10
0
101
10°
I
I
10°
101
-Vi
I
-uv
102 mV
I
10 2 dB
Output power versus feedback resistance and input voltage
Vs=24V;RL=16Q;f=1 kHz
II
100
90
fF
I
80
-
I
/
70
60
L
/
VP=4W
jP=50mw
50
/
40
30
II
20
II
10
o
10°
-Vi
515
516
AM Receiver Ie with Demodulator
TDA4001
DIP 18
The TDA 4001 has been designed to convert, amplify, and demodulate AM signals. In addition,
the component provides a search tuning stop pulse.
Features
• Internal demodulation
• Search tuning stop signal
• Low total harmonic distortion
• Minimal IF leakage at the AF output
• 2-stage integrated low pass filter
Maximum ratings
Supply voltage
Junction temperature
Storage temperature range
Vs
~
Tstg
15
150
-40 to 125
V
°C
°C
Thermal resistance (system-air)
RthSA
70
K/W
Operating range
Supply voltage
Ambient temperature
Vs
TA
17 to 15
-25 to 85
1
~C
517
TDA4001
Characteristics
Vs -12V; TA ==25°C; ViRFrms=1 mV; Rg =50 V; fiRF=1 MHz;
min
referred to measurement circuit
Current consumption
AF output voltage
m=0.8%
m=0.3%
ViRFrms = 151lV; m =0.8%
2019 (..!6.) V1-VqAF at30mV
V2 V2 -VqAF at 1 mV
Total harmonic distortion
m=0.8%
m=0.3%
ViRFrms = 30 mY; m = 0.8 %
Signal-to-noise ratio
m-0.3; ViRFrms=10 IlV
m-0.3; ViRFrms=1 mV
Reference voltage
Oscillator voltage
Counter output voltage
Input impedance RF input
IF amplifier
AFC offset current without signal
AFC offset current in the whole control range
AFC output current
flRF-l MHz ±3 kHz
Search tuning stop output current
Search tuning stop output voltage
Search tuning stop output voltage
ViRF=OV
fIRF>1 MHz+3kHz
fiRF <1 MHz-3 kHz
VqAFrms
150
THO
THO
THO
S+N
N
S+N
N
320
3
rnA
mV
mV
mV
dB
2
1
5
%
%
%
6
dB
46
dB
4.8
100
100
V
mV
mV
kWpF
kC/pF
IlA
IlA
IlA
Vstab
Voscpp
VqCpp
ZiRF
ZIIF
IAFc
.1IAFc
IAFc
10/1.5
3.3/1.5
I q13
2
±10
±10
±80
0.4
Vq13
Vq13
VQ13
Vq13
max
15
800
300
Is
VqAFrms
VqAFrms
typ
11
11
11
rnA
V
V
V
V
Additional data with respect to application')
IF suppression
3 dB limit frequency of the integrated TP
Conversion gain
AGC IF amplifier
Control range (.1 VqAF = 6 dB)
Input sensitivity
VqAFatViRF~07; VqAFat V1RF =1 mV
81F
fG
Gc
VilFrms
a
ViRFrms
40
5
30
100
60
30
dB
kHz
dB
IlV
dB
IlV
Circuit description
The impedance converter forwards the input Signal ViRF to the symmetrical double balanced
mixer. Subsequently the signal is converted to IF with the amplitude-controlled oscillator.
An external filter forwards the IF signal to the controlled IF amplifier. The amplifier IF signal
and the carrier signal will be converted to AF in the subsequent synchronous demodulator (SO).
The 2-stage low pass filter forwards the available AF to the AF output. Via an additional
limiter amplifier (LA). theAF uses the carrier signal to control the coincidence demodulator (CD).
The output signal of the COincidence demodulator provides the stop pulse during exact
tuning and sufficient field strength.
1) Data does not apply to series measurement processes.
518
II
roo
"U»
II
3
"0
!ill
:::l
II
0
0
~a.~
n> "U 0
n> -
.:J
o '"
CD
o
g
<
CD
'"
»
3
3,3kil
100nF
100 nF_ 100 nF_
qAF
'Flcontro;ojF
V
I--j
l2:uE=
+~vs sl V~StabA[F[ I
ID
0'
L
5,6kll. 10 kll.
o
22 nF
10nF'
T r~~Qo"
1 kll.
100 IF Tank
460 kHz CirCUit
"iii'c.
I.Q
iil
3
01
"0
~
17
16
15
14
12
13
11
10
CD
~
:::I
C.
3
Rl
UI
~
c
iil
3
CD
...
[FW 455 0
:::I
!:l,
c:l
c
;:;:
470 II.
68 fJH
Z =3,3 kll.
w 1: w1 =70: 26
:';'
CD
W1
W1
1
I~1F~
fJ 115Tur
1,8nF
f---1
100pF
56011.
T
1fJF
100nF
V,HF
VStab4,B V
lose ~ 1,455 MHz
+Vs
f8kll.
[:~"'
-t
C
l>
.j::>.
0
0
...!.
TDA4001
Oscillator frequency versus current consumption
rnA
kHz
1457
25
1456
?
Is
I
I
15
1455
"-
f olse
7
If
10
o
5
10
15
-Vs
Total harmonic distortion versus modulation factor
Vs -15V; fmod -1 kHz; VI -1 mV
%
3.0
!]
J
)
IJ
1/
1.5
';
V
~
l/
_.v
1.0
l/
II
0.5
o
o
20
40
60
80
-m
520
100 %
1454
20 V
r
TDA4001
Derivation of the AM-5L stop criterion
S CUive Simulation
(Pin 12)
Q
VREF
I
I
I
I
Comparator
Threshold A
-------L-------~I
I
I
I
I
I
I
I
I
..1f - Stop Bandwidth
~..1f:I
I
I
I
f
I
I
v. =Output Voltage, Window
I
I
I
A
Discriminator A
f
VIF
IF Selection
(e.g. CFW 455)
___ Comparator
Threshold B
f
Va
~
_ Output Voltage, Window
a - Discriminator B
d
f
IsTS
e
IsTs = VA • VB
Search Tuning Stop Pulse
(Pin 13)
521
TDA4001
AF output voltage, total harmonic distortion, search tuning stop versus input voltage
Vs =15V,fmod =1 kHz,fi =1 MHz
OdB;775mV{rms)
V
15
dB
%
o
rI
V
-10
-40
-50
.bV
5
'"
1
I
---
II
-80
r"-
~AF(r=O%)
-
"")
I
4
--
.....
- ' , THO"
!-VsT
-90
-100
THO
6
1
-70
o
f--
V ,j.. .....
-60
5
8
VqAF{ m= 80 %)
If
:
F_ 20
-30
10
1/'"
I
I
o
5 10'
-Vi
AF output Voltage, total harmonic distortion, search tuning stop versus input voltage
Vs =15 V; fmod =1 kHz, f=1 MHz
OdB; 775 mV (rms)
V
dB
%
8
15
.... t--
-10
VST
I
qAF
V,t
10
~20
/
-30
-40
-50
J
1
1
I"'" r"-i'-.
1 I
-60
II
,
I
-80
I
-90
,
-100
1VsT
\
\
4
~r--....
VqAF(m=O%)
2
..... ~
V-V
I
I
o
5 10'
_Vi
522
THO
6
_I
~V
-70
o
~AF{m=30%)
/f"
1
>
'a
'2.
100nF
1--/
+v~rV)
680(l
I
47nF
I
:1
~r
c
::;:
I
1.2k(l
I
I
I
'.Vp'
-.~-- I
I
I
6..
rk\l~kQ~ O~~
Ferrite
~e!)d l
1100nF
47mH)'
Ir~'l:Y::'
~
n
18
O,33mH
Input
CON
i.o
I
T
~
I
100 nF 150k(l
I
1120
,.,~'"o> '-;1 f"";'
520pF
68
22k(l 1 330(l1l k(l
r-1.~~ i
L_
6 22pFi
I
-··
T
1 BV
Tuning Voltage
1
O,l~F
Ker.
r>
Counter (PLL)
g
~
(JI
~
o
g
(J1
I\)
.j>.
~
JZ
CD
c
c- eo
c·
3
::III
<
..,CD
CD
0
CD
<'
..,CD
S·
0'
()
III
o·
~
'C
iii
~
~.
:T
Counter
68kll
8,2kQ
.
22jlF -c::J-
-
~I
Tuning Voltage
ms;---'
~ -I....
10pF
I ~ :Y 330Q
nkl'l~~
--It.:.:.::!:: :
W10kQ~ 8 'i L!'TJ.2,~~;FT ~2~;----J470PF
-I....
TBB1331A
g
-lll-:
!ffil-II....
~ sT ~
-III-
·E,7kQI
r-------:
yO. kQ
'
22 kQ
..L.
<:>
~
-.-
0'<
L ______ J
100nF-UBC 238 Bn
..JIL
o 22)JF
~
o
~
til
8
.
t;
>
Q)
z
~.if ~ ~-I
II
-........... u..
I
I
,
I
t
:
:
I
I
I
I
"
I
J
SFZ455 A
I
1
,
I
1'i:;1
1
.,...
I
,
I
L__ '-_-'
~ -j~
I
I
...
'
I
62
•
----.....--c::::::J--
10kQ
120pF
c:
J,'c:
:~
3'
co
!!l.
0
"C
"C
C
en
CD
1330 1-'1'1
I
1 2 kQ
I,
::::J
150k~1--. ~I=§..
1 g~~~~
,
2"
9.Q
T
"I 82 kQ
l00nF
fr:iu..
0::r
I
,J,}jlF.
D.f'BF\61
~
-u- ~ ~~.
O.8pF
l?;N •.
r---, r----' J.,;.~~Q
I
33kl'lL..-----..1
I
.
100 IlE.tL
I -c::::J.,
..L.1'
S6pF T
2,2nF
~ ~ r-----'~
?ttIN 'f('1 :'1 :~,
r----.,
T
.0
Q)
lVF~
,---16-22pF"
~a
...:t
«
""~f11J BC 238 B-IftfJF
~
10kl'l 0
~ co
-c:::r- 100nF
1.,SIlF.
'T 100nF
..L...L.
10kl1~
100nF
220Q
.J..
CD
III
'4.7mH
B(23880
r--l·
1:47pf I N~ I'033 F .
--u--- I en I ' V
~
(J)
-
~ ~
tn
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4
Input
a>
'"
g
~
o
g
AM-receiver for AM-stereo
Preliminary Data
TDA4010
DIP 18
'Compare to TDA 4001 the TDA 4010 is an extended AM·receiver. This type is suitable for applica·
tions in car radios.
The IF·output VIQF is at pin 15.
Features
• Internal demodulation
o Search tuning stop signal
o Low total harmonic distortion
o Minimal IF leakage at the AF output
• 2'stage ingrated low pass
o Standard IF·output
Function description
The monolithic integrated bipolar receiver has been designed to convert, amplify and demodulate
AM· signals. In addition, the component provides a search tuning pulse.
The search tuning stop pulses are processed from the input signal.
The standard AM·IF signal is available at the output of the IR·receiver.
Circuit description
The impedance converter forwards the input signal ViRFtothe symmetrical double balanced mixer.
Subsequently the signal is converted to IF with the amplitude'controlled oscillator. An external
filter forwards the IF signal to the controlled IF amplifier. The amplifier IF signal and the carrier
signal will be converted to AF in the subsequent synchronous demodulator. The 2'stage low pass
filter forwards the available AF to the AF output.
Via an additional limiter amplifier (LA), the AF uses the carrier signal to control the coincidence
demodulator(CO). The output signal of the coincidence demodulator provides the stop pulse during
exact tuning and sufficient field strength.
525
TDA4010
Maximum Ratings
Maximum ratings cannot be exceeded without causing irreversible damage
to the Integrated clrult.
Pos.
1
2
3
4
Maximum rating for
Tamb= 25"C
Symbol
Operating voltage
Current consumption
Junction temperature
Storage temperature
Vs
Is
TJ
Ts
Thermal resistance
5
chip ambient
6
chip package
min
max
dim
V
mA
-40
15.6
33.0
150
+ 125
78
K1W
RthSlJ
remarks
°C
°C
RthSG
Functional Range
Within the functional range, the integrated circuit operates as described; deviations from the
characteristic data are possible.
Pos.
Maximum rating for
Tamb = 25°C
1
2
Operating voltage
Temperature range
526
Symbol
min
max
dim
VBatt
7
-25
15
+85
V
A6
°C
remarks
TDA4010
Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit.
Typical characteristics specify mean values expected over the production spread. If not stated
otherwise, typical characteristics will apply at tamb =25°C and the listed supply voltage.
Pos. Parameter
Symbol Test conditions
Test
circuit
Min
Typ
Dim
Vs= 12V
Tv=25°C
Supply voltage
Ambient temperature
1 Current consumption Is
2 Reference voltage
VSTAB
3 IF·output voltage
VqNF
4 Total harmonic
5 I F-output voltage
VqNF
6 Input sensitivity
ViHF
m=0.8
m=0.3
k
m=0.3
20 • Ig (VqNF/30mV:
15
4.8
800
VqNF for ViHF =
1mV-3dB
S+N m=0.3
N
ViHF = 10/lVeff
S+N m=0.3 ViHF=1mV
ratio
8 Signal-to-noise
9 Oscillator voltage
VOse
10 Counteroutputvoltage VqZ
11 Control range
a
(Ll. VqlF = 6dB)
12 3dB limit frequency
of the integrated TP
'g
mA
V
mVeff
2%
%
m=0.8
VqNF/1mV
7 Signal-to-noise
Max
+3
dB
30
6
/lVeff
dB
46
100
60
dB
mVss
mVss
dB
5
kHz
100
527
TDA4010
Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit.
Typical characteristics specify mean values expected over the production spread. If not stated
otherwise, typical characteristics will apply at tamb =25°C and the listed supply voltage.
Pos. Parameter
Symbol Test conditions
Supply voltage
AmbIent temperature
13
14
15
16
17
18
19
20
21
22
23
24
528
IR-suppression
Conversion gain
IF-output Pin 15
AFC-Offset current
without signal
AFC-Offset current
over control range
AFC-current
SLS-output voltage
SLS-output voltage
SLS-output voltage
SLS-output voltage
Input impedance
Input impedance
Test
circuit
Min
Typ
Max
Dim
Vs=12V
Tv = 25°C
40
AIF
Vm
VqlF
/AFC
10
±10
l1/AFC
/AFC
V'2
V'2
V'2
V'2
ZIHF
ZniF
dB
dB
melf
p.A
30
fIHF=1MHz±3kHz
fZF=455kHz
FZF=OV
fZF>455kHz + 3kHz
fZF>455kHz - 3kHz
Pln3,4
Pin 18
11
11
11
± 10
p.A
±80
0.4
p.A
V
V
C
V
10/1.5
3.3/1.5
kfl/lpF
kflllpF
IXJ
0'
C'I
""iii"
Q.
ce
Dl
3
CFW
~
::r.
c.n
~
-I
g
g
o
TDA4010
Pin configuration
Pin-Nr_
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
pin function
Ground
Mixer output, IF-circuit
RF-input
RF-input
VStap
Oscillator
Supply voltage
counter output
FM-Demodulator circuit IF-circuit
FM-Demodulator circuit IF-circuit
AFC-output
Search tuning stop output
AF-output
IF-time constant
min. IF-output
IF-AP follow up device
IF-AP follow up device
IF-input
18
2
530
17
3
16
4
15
5
14
6
13
7
12
8
11
9
10
3(1)
III
en
S
:i"
o
co
a"
§:
3,3k
CFW
~
2.2n
l,Sk
15k
-l
~
.j::,
9
o
<.ll
~
r:'Z-;,~;o,~
532
Infrared Preamplifier
TDA4050 B
DIPS
The TDA 4050 B is suitable for use as infrared preamplifier in remote control facilities for radio
and TV sets.
The IC includes a controlled driver stage with subsequent amplifier stage as well as an
amplifier for the threshold value. The circuit is largely balanced.
Features
•
•
•
•
•
Internal AGC
Superior large signal stability
Short-circuit proof signal output
Simple connection for an active band filter
Few external components
Maximum ratings
Supply voltage
Junction temperature
Storage temperature range
Vs
161)
150
-40 to 125
V
~
Tstg
Thermal resistance (system-air)
RthSA
140
KlW
°C
°C
Operating range
Supply voltage range
Ambient temperature range
Input frequency range
Vs
Tamb
fi
19o toto 70
16
o to 100
IV°C
kHz
1} intermittently 17.5 V
533
TDA4050B
Characteristics (VS = 15 V;
Current consumption
(RL~ 10
Tamb =
kO)
25°C;
fiR
= 31 kHz) referred to measurement circuit
16
min
typ
max
6
9
12
mA
85
\-LV
\-LV
Input voltage for control start
Input voltage for output signal
varms
Filter output voltage (in control range)
V4rms
350
450
550
mV
Gain
Gain
G4/S
G3/4
74
77
21
85
dB
dB
.1G
74
1325
1.5
1.9
2.1
77
85
1525
2.1
2.45
2.6
dB
mV
mV
V
V
2.8
Total control range
Control voltage without input signal
Control voltage (VS rms = 100 IlV)
Control voltage (vs rms = 10 mV)
Control voltage (VS rms = 1 V)
50
varma
V2
V2
V2
V2
1425
Operating points
Output current (V3 = Vs)
Output dc voltage for L level
Output dc voltage for H level
Charge current
(VS rms = 100 mV; V 2 = 1.6 V)
Discharge current
(VS rms from 1 mV to 0)
(T=50 ms)
V 4/517
13
V3L
V3H
-12
14.6
0.4
1.0
V
mA
mV
V
mA
12
0.4
3.0
Il A
Input resistance
Output resistance
Rated resistance of the double-T
network at pin 4
(unbalanced to ground)
RiS
RQ3
R4
2.2
20
150
1.8
10
2
Pin configuration
Pin No.
Function
1
Ground
Connection for capacitance for prestage control
Output threshold amplifier
Output active filter
Input active filter
Supply voltage, positive
Unlocking of operating point control
Signal input
2
3
4
5
6
7
8
534
500
kO
kO
kO
s:
(1)
+Vs=lSV
III
In
C
4.7~F
H
lSnF ,6800
~J--5---,Signal
input
iil
3(1)
...
8
::I
(')
~.
S:
III
::I
Q.
3.3 kll
1.5nF
C1'
0"
(')
;0;Q.
iii"
(Q
3.3nF
H
6.8 kO
iil
3
1.8kO
27kO
TDA 40508
330
./"-
-/2
T ~"
=
I
1 ~3.3kO
lUKl1
I,
1-
.4
13
f'
--I
t
,
,
.
,
"ff :, "
2. 2pF
Signal
output
h
V4 , /
100kO
I---t
V4
01
v.:>
01
lSV
f1.5nF
g-I
.j::o
0
UI
0
OJ
:i"
t1I
~
»
0'C
~'C
I
2.2kll
IIT =
I
I 8~
- - 10)JF
SignQI input
~"' l)JF
7i'
'
6
r-=
()!;l
:5" c!:
'CO
I 10)JF
O<~
T,----5
0
I: :::II
....
(J) n
_.
(\)n
-I:
~;:;:
I
~
:::II
33kll
56kll
~A
,,
100mH ~:,
BP104
:;:: l.SnF
22nF
~I
- Irk t7
3.3nF
I-t
1.8kll
kll
"
3311
3.3kll
3
SignQI output
4
l.SnF
g
8
g
m
TDA4050 B
Application circuit II
without coil
1.5kl'l
~----------------r-----~-c=r--~--~----~+Vs
I
I
I
I
I
82kl'l I
10kl'l
I
:
~
BAW76!
BP104
1MI'l
6.8nF
3.9kl'l
3.3nF
~
3.9kl'l
27kl'l
.
E
T~:
1.5nF
390kl'l
R-D-R
Notes
Circuit I uses an LC resonant circuit and is of superior quality due to its high selectivity
feature (approx. 3 kHz bandwidth at -3 dB).
Circuit 2 offers the lower cost solution without coil inc!. broadband input selection. Higher
requirements as to steady radiation and large signal stability can be met by means of
resistor-diode-resistor connection (RDR).
537
538
IR Pre-amplifier
TDA4060
DIP8
Preliminary Data
The TDA 4060 is a pre-amplifier suitable for use in radio, TV, automotive and other electronics
systems where infrared signal transmission is utilized.
Features
• Low voltage operation
• Wide operating frequency
• Few external components
Maximum Ratings
Supply voltage
Junction temp.
Storage temp. range
Vs
TI
Ts
7
150
- 40 to + 125
v
Vs
Tamb
3.5-6.5
-40to+110
20 - 200
v
°C
°C
Operating range
Supply voltage
Ambient temp.
Input freq.
'I
°C
kHz
Additional data available on request.
539
01
III
o"""
6"
:tI
:0\'"
;
n
Co
iii·
ce
D1
3
:§.
1
~
~
\I)
Vs
3
"2-
::;:
...
CD"
"2-
n·
output
Input
low noise
amplifier
(regulated)
band pass
filter
driver
J
Creg
I
s»
'C
<:""
Infra-red
receiver diode
"tJ
'--
11
d
Fl~
-
~
T
~
-
f-
f-
:£
==
~
{]
----
H:::J-jf
=1=
;:::
----
558
~II
r---
....J
1
I
~
::'!.L
II:
:;>
==
LrI
~
ID
1\1
III
C
;
3
VL
(fl
Vs
~L
Vs
,~51"" "o't. J Lo, I
i
(fl
I\J
:::J
'C
0
(J)
;::;:
o·
kl1 47fJF
:::J
I\J
c.
c
24
5"
23
t2
10
:::J
6BnF
~15kl1
~120
19
118
17
16
...n
ID
3.3nF
Band
Width
::I
C~~~.,~ T
o
t L
~ VVq15
q14
VqL
::;.
n
c
;::;:
113
0
iii'
m
I
3
m
n
TDA 4292
III
(J)
c
CD
3
m
3VREF
1 ~~6
151[1o'"
'
7
'~
f" 5j"" T1r ,
4.7fJ F
"0'
VT
VB
V;R
"0'
q12
±=?V
Vq11
15kl1
Physiology
--,- 330nF
~I
I
o
VqR
3,3nF
g
.s:a
I\)
(J1
(J1
co
CD
I\)
TDA4292
Application circuit
Base
BalVolume
22
kQ
24
+Vs
'"'"I:" 1.,,1 TL",
22
kQ
23
OutpulL
820
Q
68nF
15kQ
19
20
22
18
17
16
8
9
TDA 4292
2
6
4
7
10
11
12
VREF
330nF
r"
Treble
560
68nF
22
kQ
Bass
22
15kQ
f" ""'T 1f"'
820
Q
kQ
InpulR
Physiology
3,3nF
OutpulR
TDA4292
Bass and treble control
83 closed, 84 open
dB Vs = 15 V; Virms = 1 V
-15 ,---Max. Trebles
Max. Basses
V
"- ......
o
,;"
/
-5
~,;'
-
Linear
Position
r-....,
-10
\~in. Trebles
Min. Basses
-15
10Hz
100Hz
1kHz
10
10kHz
- - f .I
Bass and treble control
83 closed, 84 open
Vs =15V; Vlrms=1 V
dB
15
Max. Trebles
~in. Basses
10
/
"- r--- ....
o
~ ...
............ 1'
.........
/
-5
Linear
Position
'r-.
-10
~:n. Trebles
~x·1 B~i~~~
-15
10Hz
100Hz
1kHz
-----
10kHz
10
~
561
TDA4292
Treble control
83 closed, 84 open
dB Vs=15V; V;rms=1 V
15
1
f; = 15kH:1------ --- f---- --_.
--
f = 20 Hz
'/ I
~
\1
-5
~ = 1kHz
1--- -
-15
V
--_.-
-10 1----
I
--
lL
V
r------- - -
OJ
OS
0_2
~ ,5kHZ
I~ .--
7 (19)
--
rT
1,8nF
J I
t--- I--"
0.1
H-
1/..--
1---- f-----
o
y
0.4
0.6
0.7
0.8
--V1
1.0 V1
0.9
Bass control
83 closed, 84 open
dB Vs =15V; Virms=1 V
15
40Hz
/
,
/
~
-10
~
o
0.2
100Hz
,...1kHz
5(21} 6(20}
LUT
I--"V
0.1
68nF
0.3
0.4
0.5
0.6
I
I
0.7
0_8
- - VJ
562
-
15kHz
- //
/""
-5
-15
j
V
0,9
1.0 V1
TDA4292
Physiological volume control
Vs = 15 V; Virms = 1 V
dB
.
-- -
10
--_.
-
1--- i--f-- 1--
I..-
i-
V
........... l-
-30
I/
.........
..... t--.
-40
"
r.....
-50
-60
I
-70
V
1-
V
--- V
~
./
Volume control with physiology
Vs = 15 V; Virms =1 V
dB
o
./
-10
V t/j
V ~V
f = 40Hz ./ V~ b7
7
v~
P\ h r~
/
r~::
I
-40
-50
"-
/ ' 17#
-60
/ ~
-70
r7 V
/ I
-90
o
0.1
0.2
~1(15J ~12(14J
~"fj =15kHz
t? f; =1kHz_
/
-80
W
/.V
rr;
OJ
~
0.4
0.5
: ;:330
nF_
22 kl1
3,~,nF
1kl1
'~2onL
0.6
I
I
0.7
0.8
Q
I
0.9
lO
~
--V24
563
TDA4292
Balance
83 closed, 84 open
dB Vs = 15 V; Virms = 1 V 0 dB
15
-----
10
Vq
-"-----
r -5
-
:--- ...........
V
L ~
I
-10
V
"//
-30
-35
Vq1111
" - f---"
_.
- 20
- 25
--
"'>-
1-" ----
Vq14115
-15
r-
/
V
- --
0.1
. r----"-----
-
0.2
f---
"""-""
'" "-
'\
"-
"--"I
03
0.4
-r---~
0.5
0.6
.. -
I
---
-----
0.7
0.8
~
0.9
1.0 V,
----- V 13
Base width
Vs = 15 V; Virms = 1 V
dB
4
I IIII
I Input Signal
o
!:d~~IJ3°1c
Vq
r -4
-
-- -
\
i
-3dB
-8
-12
-16
IfiliI!
--
0
I IIII
Antiphase Signal
/
I
/
J
9(17)
II
]}5kll
I
...
;;;;;0 22nF
-20
-24
10Hz
100Hz
1kHz
10kHz
~~
564
10
TDA4292
Disturbance voltage spacing
83 closed, 84 open
dB Vs =15V;V;rms=300mV
100
90
Teo ~
as.N
t
~ .~
~~ ~
60
so ~ ~ ~~
70
40
~ '~ I~~
la .Yo
30
20
10
o
o
~ ~~~~ 'vRMS (20Hz ... 20kHz)
~:tJ~~~ ~
~ ~ I~ ~ I~ t-...
~~~ ~ ~
-10
-20
-30 -40
-so
-60
-70 -80
_ VQ
-90 -100dB
565
TDA4292
Base width circuits
..I. 22nF
1.
15kl"l
17
TDA 4292
9
15kl"l
T
22nF
a) Stereo reception
i.e. normal linear frequency response and stereo sensation with closely spaced loudspeakers.
With the base width ON the base-width effect has a time constant of 22 nF/15 kQ,
i.e. the subjective spacing between the loudspeakers is greater.
b) Mono reception (with base width ON)
Normal linear frequency response and mono sensation.
With the base width ON there is a deemphasis of approx. -5 dBtrom about 300 Hz onwards.
This causes slight treble deemphasis and the acoustic impression is duller and somewhat
quieter.
Stereo and Mono Reception
Without Base Width
Output
Signal
t
Mono Reception With Base Width
300Hz
-----f
Effect: At mono signal: trebles approx. -5 dB
At stereo signal: cross-talk over 300 Hz
566
~.
TDA4292
2.
TDA 4292
a) Stereo reception and base width ON
The trebles are emphasized from 300 Hz onwards by up to +5 dB (time constant 8.2 kQ
and 4 nF), i.e. with the base width switched on there is simultaneously a slight change
in the timbre of the acoustic impression.
b) Mono reception and base width ON
Switching on the base width produces no change at all in the acoustic impression.
Stereo Reception
With Base Width
Output
Signal
I
Stereo Reception Without Base
Width. Mono Reception With and
Without Base Width
300 Hz
-f
Effect: At mono signal: no influence
At stereo signal: trebles approx. +5 dB
567
TDA 4292
3.
17
22nF
TDA 4292
15krl
a) Stereo reception and base width ON
From 300 Hz onwards emphasis of the trebles by +2.5 dB with the corresponding time
constants.
b) Mono reception and base width ON
From about 300 Hz onwards deemphasis by about -2.5 dB.
With the corresponding time constants this produces a slight loss of treble and makes
the acoustic impression darker and quieter.
Stereo Reception
With Base Width
Mono and Stereo ReI - - - - - E - - - - - - - - - - - c e p t i o n Without Base
Width
Mono Reception
With Base Width
_-------"c:.:;.;..;;;;
300 Hz
_f
Effect: At mono signal: trebles approx. -2.5 dB
At stereo signal: trebles approx. +2.5 dB
568
TDA4292
Physiological volume control (loudness) versus frequency and capacitance values Cx
Gv deviations for different capacitances (R L at output 1 MQ).
dB
)1Tllill~
-10
470nF
464nF
.
H---r I HCnTm-j
-
220nF-,f.-.-l------1--'-l-l-I-r4.~1
330nF
334nF 223nF
i
!
4.57nF
I
3.36nF 2.58nF
\
I
~
'\
\
-90
-100
1--+--4~~ ~-+_+--+_+++++---+-
-110
10 4 kHz
Physiological volume control (loudness) versus frequency and load resistance R
Output loaded with R (C y = 3.3 nF; C x = 680 nF).
dB
I:Tn
I
~J
iI
~I'
Vq -10
-20
-30
-40
-50
f---+-Rt ~i+-- -~ f1MIi 10~1i' •
/1 I i :
f-....: j5l:: ].
I
I
I
I
I Ii
i
1
---
OdB
J
I
. Ii
In
I
1111 [1
I
I
II III
• III Ii
I
ill
HJ==
Volume Control -30dB
Physiology .. ON ..
!
Vq
t
-30
-40
10 2
10 3
10 4 kHz
569
TDA4292
Bass and treble control versus frequency
Gv deviations for different capacitances (load at output 1 MQl
dB
570
TDA4292
Alteration of frequency response through component tolerances
•
•
•
•
Bass control
Capacitor
Pin 21/20 - 5/6
C =68 nF
68 nF-20%
68 nF
68 nF+20%
Gv =+ 1.5 dB
Gv = 0 dB
Gv =-1 dB
f= 100 Hz
Capacitor
Pin19-7
C= 1.8 nF
1.8 nF-20%
1.8 nF
1.8 nF+20%
Gv =-1 dB
Gv = 0 dB
Gv =+1.5dB
f= 10 kHz
Treble control
Physiology network
Capacitor for bass emphasis
Cx =330 nF
330 nF-30%
330 nF
330 nF+40%
f= 100 Hz
Gv =-3dB
Gv = o dB
Gv =+2dB
Capacitor for treble emphasis
Cy=3.3 nF
3.3 nF-20%
3.3 nF
3.3 nF+40%
Gv = 1 dB
Gv = o dB
Gv =+2 dB
f= 10 kHz
Gv =-5
Gv =-2.5
Gv =-1
Gv =- 0.5
Gv = 0
f= 20 Hz
Terminating resistor
RA = 10 kQ
RA = 22 kQ
RA = 47 kQ
= 100 kQ
RA =
1MQ
RA
dB
dB
dB
dB
dB
571
572
r::::;;;o-
ControllC for Switched-Mode Power Supplies
Preliminary data
TDA4600-3
SIP9
The integrated circuit TDA 4600-3 is designed for driving, controlling, and protecting the
switching transistor in self-oscillating flyback converter power supplies. In addition to its
application in TV receivers and video tape recorders, this IC can also be used in hifi devices
and active loud speakers due to its wide control range and high voltage stability.
•
•
•
•
Direct control of the switching transistor
Low start-up current
Reversing linear overload characteristic
Base current drive proportional to collector current
Description of function
This IC is designed for driving a bipolar power transistor and for performing all necessary
control and protective functions in self-oscillating flyback converter power supplies. Owing
to the IC's outstanding voltage stability, which is maintained even at major load fluctuations,
the IC is suited for consumer as well as for industrial applications. The rectified line voltage
is applied to the series connection of the power transistor and the primary winding of the
flyback transformer. During the on-phase of the transistor, energy is stored in the primary
winding and released to the consumer via the secondary winding.
The IC controls the power transistor in such a way that the secondary voltage is kept at
a constant value independently of changes in the line voltage or load. The control information
required is derived from the rectified line voltage during the on-phase as well as from a
secondary winding during the off-phase.
Load differences are compensated by altering the frequency, line voltage fluctuations are
additionally counteracted by changing the pulse duty factor. This results in the following
load-dependent modes of the SMPS:
- Open-loop or small load: Secondary voltage slightly above the desired value
- Control:
Load-independent secondary voltage
- Overload:
In case of a secondary overload or short circuit, the secondary
voltage is decreased at the point of return as a function of the
load current, following a reversing characteristic.
573
TDA4600-3
Description of use
A flyback converter designed for color TV sets, applicable between 30 Wand 120 Wand
for line voltages ranging from 160 V to 270 V, is described on one of the following pages.
On the subsequent pages the major pulses and diagrams can be found. The line voltage
is rectified by bridge rectifier Gr1 and smoothed by C3 . During start-up the IC current is
supplied via the combination Gr2+R l1 while, in the post-transient condition, it is additionally
supplied via winding 13/11 and rectifier Gr3. The size of filter capacitor Cg determines the
turn-on behavior.
Switching transistor T1 is a BU 208. Parallel capacitance Cll and primary winding 1/7 form
a resonant circuit, thus limiting the frequency and amplitude of collector-emitter voltage
overshoots upon turn-off of n. R12 , Gr4, C10, R15 and Dr2 are elements to improve the
switching behavior of T1.
The inductance of the primary winding determines the current increase in T1. This sawtoothshaped current rise is simulated at network R5CS and applied to pin 4 of the IC. Depending
of the dimensions of the primary inductance, timing element R5CS is to be adapted to the
current rise angle in T1. Thus, during the on-phase, the IC receives control information at
pin 4 in the form of the simulated energy content of the primary winding as a function
of the line voltage versus time.
Fluctuations at pin 3 are recognized by control winding 9/15. This measure requires fixed
coupling to secondary winding 2/16. The control winding is also used for feedback and
permits self-oscillating conditions in parallel circuit C11 /primary inductance if power
transistor T1 is blocked. In this way the maximum open-loop frequency is determined.
The control voltage required at pin 3 is rectified by diode Gr5 and smoothed by capacitor C6 •
Furthermore, resistor Rs and C6 form a timing element. Due to these circumstances, fast
changes in the control voltage are filtered out, i.e. the controlling element does not respond
until several periods have occured. The secondary voltage can be set by means of the
voltage divider formed of resistors Ry, R 6, R3 and R 2 • Reason: in the IC the control voltage
at pin 3 is compared with a stable, internal reference voltage.
According to the result of this comparison, frequency and pulse duty factor are corrected
until the secondary voltage selected by Ry has established itself.
In the case of overload or short circuit on the secondary side, only a small voltage portion
is passed to control winding 9/15; the reference voltage at pin 1 becomes directly active
at control input pin 3 and activates an overload amplifier (point of return). which drives
power transistor T1 down to a smaller pulse duty factor. The line power output is reduced
to 6 VA.
For all operating ranges of the SMPS, the zero passages of the voltage at the control winding
contain information on pulse duty factor and switching frequency of switching transistor T1,
or on the open-loop frequency. Conditioning of the corresponding signal at pin 2 is performed
by series resistor R4 , and by integrated limiter diodes. Timing network RSC 4 suppresses HF
spikes at pin 2.
574
TIDA4S00-3
Before the line voltage drops below its minimum value, the SMPS must be switched off in
order to obtain defined on/off conditions. Winding 11/13 is configured in such a way that
the voltage at pin 9 changes linearly with the rectified line voltage. The IC goes into
on-state if Vg ~12.3 V, and into off-state if Vg:S; 5.7 V. The drive of the power transistor will
be blocked as soon as Vg :S; 6.7 V.
Pin 5 is connected to pin 9 via resistor R g, since the IC's output is not enabled until
voltages V5 ~2.7 V prevail.
On the secondary side start-up voltages from V'sec to V 4sec are available. If switch S1 is put into
open position, standby is set automatically, with a secondary effective power of approx. 3 W
being tapped from winding 12/16. Resistors R'3 and R'4 form a basic load of voltages
V'sec and V 2sec . They contribute to maintaining standby conditions, i.e. Vsec rise :S; 20%.
Capacitors C'2 through C'5 prevent spikes caused by reversing rectifiers Gr6 and Gr9.
The secondary voltages are smoothed by the charging electrolytic capacitors C'6 through C,g.
After the line voltage has been applied at time to, the following voltages start to increase:
- Vg according to the half-cycle charge via R".
- V4 to V4 max (typ. 6.2 V)
- V5 to the value determined by Rg
In this case the current consumption of the IC is smaller than 3.2 mA. If Vg reaches the
threshold 12.3 V, the IC will switch on the reference voltage of pin 1. The current consumption
rises to typically 80 mA. The primary current voltage transformer adjusts V 4 down to VREF/2
and the start pulse generator produces the start pulse. Feedback to pin 2 starts a subsequent
pulse and so forth.
The width of all pulses, including the start pulse, is controlled by the control voltage at pin 3.
During turn-on the control voltage corresponds to standby conditions, i.e. V3 = VREF/2 + 50 mV.
The IC begins with narrow pulses, which become wider depending on the feedback control
voltage. Instantly, the IC operates in the control mode. The control loop is in a post-transient
state. If, during start-up, voltage Vg drops below the turn-off threshold Vg :S; 7.8 V, the startup phase will be terminated (pin 8 is switched to Low). Since the IC remains in the on-state,
Vg drops further to Vg:S; 5.7 V. The IC switches to the off-state, Vg is now able to rise again
and a new start-up phase may begin. After the IC has been started, it will operate in the
control mode. The voltage at pin 3 is typically VREF/2 + 0.2 V.
If the output is loaded, the control amplifier allows wider charge pulses to occur (Va = H).
The peak value of the voltage at pin 4 rises to V4 = VREF• Upon an increase in the secondary
load the overload amplifier begins adjusting the pulse width down. Since altering of the
pulse width is reversed, this is referred to as the reverse point of the SMPS or point of
return. In case of a short circuit on the secondary side, the overload amplifier will adjust
the pulse width to typically 1.6 ~s and reduces the pulse duty factor to < 1 : 100. The SMPS
decreases the line power consumption to typically 6 VA. A small pulse duty factor entails
a drop in supply voltage Vg below the threshold Vg :S; 6.7 V causing a drive interrupt of the
switching transistor and a continued drop of supply voltage V g. If supply voltage Vg:S; 5.7 V,
the IC is turned off and enters into a new start-up phase.
575
TDA4600-3
This intermittent periodic duty operation is continued until the short circuit on the secondary
'side has been eliminated.
If the secondary side is unloaded (standby), the control pulse width becomes narrower.
The frequency rises. During open-loop operation the approximate natural frequency of the
system (75 kHz) is obtained; pulse duty factor 1 :11. The rise of the secondary voltages
is approx. 20%. If resistors R131R14 were absent, the IC would have to perform adjustment
beyond the natural frequency of the system, with the zero passage identification only
recognizing every 2nd, 3rd or 4th zero passage as a pulse start, i.e. the frequency would
divide down to the 2nd, 3rd or 4th subharmonic. The pulse duty factor is thus diminished
to 1 : 22, 1 : 33, or 1 : 44, respectively. The pulse width remains constant at approx. 1.2 j.l.sec.
A certain small pulse duty factor causes supply voltage V9 to drop below the threshold
voltage V9 ::;: 6.7 V. Then, the interrogation intermittent periodic duty operation begins as already
described for the short circuit case. Constant open-loop operation will not continue until
resistors R131R14 have been loaded.
576
TDA4600-3
Circuit description
Pin 1 :
Reference voltage output, overload-protected.
= 5 mA. All modules, excluding the IC's output stage, are supplied by the
internal reference voltage.
I 1max
Pin 2:
The zero passage identification driving the control logic identifies the discharged
status of the transformer at the zero passage of voltage V2 from negative to positive
values and enables the logic for pulse start, which is driven by trigger start.
Pin 3:
The control voltage supplied to this pin is compared with two stable reference
potentials in the control amplifier, in overload identification and during standby.
The outputs of these stages operate onto the trigger hold, thus terminating the
pulse.
Pin 4:
A voltage proportional to the collector current of the switching transistor is generated
on the basis of the external RC combination in conjunction with the collector
current simulation block. This voltage introduces the beginning of a pulse at a stable
voltage via trigger start and determines at a second stable voltage (reverse point)
the absolute maximum pulse (with respect to time length) in trigger hold. At the
same time the rise angle of the voltage proportional to the collector current of the
switching transistor is impressed onto the base current amplifier, and, in accordance
with the smallest current amplification B of the switching transistor to be expected,
the base of the switching transistor is driven via pin 8.
Pin 5:
If a voltage :?2.7 V is applied, the control logic is enabled via the trigger. Pins 7/8
are driven by the coupling capacitor charge circuit and the base current. In case
a voltage ~ 1.8 V prevails, base current switch-off pin 7 is clamped at a voltage
V7 ~1.3 V; driving of the switching transistor is impossible. The IC will not be
enabled again until the voltage at pin 9 has dropped below 5.7 V, the IC has
been turned off and the SMPS has entered a new start-up phase.
Pin 6:
GND
Pin 7/8:
Via the voltage controller and the coupling capacitor charge circuit, the output
stage of the IC is dc-adjusted to the switching transistor. The switching transistor
is driven via a base current amplifier and pin 8, while it is blocked via the basic
current switch-off and pin 7.
Pin 9:
Current supply of the IC.
577
TDA4600-3
Maximum ratings
Supply voltage
min
max
Vg
0
20
V
VI
V2
V3
V4
Vs
V7
Vs
0
-0.6
0
0
0
0
0
6
0.6
3
8
8
Vg
Vg
V
V
V
V
V
V
V
~2
~3
~4
-5
-3
0
5
3
5
1.5
0
125
125
mA
mA
mA
A
A
DC
DC
70
15
KIW
18
85
V
DC
Voltages
Reference output
Identification input
Control amplifier
Collector current simulation
Blockil']g input
Base current cut-off point
Base current amplifier output
Currents
Feedback zero passage
Control amplifier
Collector current simulation
Base current cut-off point
Base current amplifier output
Junction temperature
Storage temperature range
Thermal resistances
junction-air
junction-case
I q7
Iqs
~
Tstg
0
-1.5
-40
R thJA
RthJC
KlW
Operating range
Supply voltage
Case temperature
578
Vg
Tc
7.8
0
TDA4600·3
Characteristics
TA = 25 °G; according to measurement circuit 1 and diagram
min
typ
max
11.0
1.5
2.4
11.8
0.5
2.0
3.2
12.3
Start operation
Current consumption (V, not yet switched on)
Vg = 2V
Vg = 5V
Vg=10 V
Switching point for V1
Ig
Ig
Ig
Vg
mA
·mA
mA
V
Normal operation
Vg =10 V; Veont =-10 V; Veloek = ±0.5 V; f=20 kHz; pulse duty factor 1:2 after switch-on
Current consumption
Veont =-10V
Veont=OV
Reference voltage
11 <0.1 mA
11 =5 mA
Temperature coefficient of reference voltage
Control voltage Veont =0 V
Collector current simulation voltage
Veont=O V
Veont =0 V/-l0 V
Blocking input voltage
Output voltages
Veont=O V
Veont=O V
Veont =0 V/-l0 V
Feedback voltage
Ig
Ig
110
50
135
75
160
110
mA
rnA
V1
V1
TC 1
V3
4.0
4.0
4.2
4.2
4.5
4.4
2.3
2.6
2.9
V
V
11K
V
V4*)
.d V4*)
Vs
1.8
0.3
6.0
2.2
0.4
7.0
2.5
0.5
8.0
V
V
V
Vq7*)
VqB*)
LlVqB*)
V2
2.7
2.7
1.6
3.3
3.4
2.0
0.2
4.0
4.0
2.4
V
V
V
V
10-3
Protective operation
Vg =10 V; v.,ont =-10 V; Veloek = ±0.5 V; f=20 kHz; pulse duty factor 1:2
Current consumption
Vs < 1.8 V
Turn-off voltage
Vs<1.8 V
Turn-off voltage
Vs<1.8 V
External blocking input
Enable voltage
Veonl=O V
Blocking voltage
Veont=O V
Supply voltage blocked for VB
Veonl=O V
V1 turned off (if Vg is further decreased)
Ig
14
22
28
mA
Vq7
1.3
1.5
1.8
V
V4
1.8
2.1
2.5
V
2.4
2.7
V
Vs
Vs
1.8
2.2
Vg
6.7
0.3
7.4
0.6
LlVg
V
7.8
1.0
V
V
0) DC component only
579
TDA4600-3
Characteristics
TA = 25 °C; according to measurement circuit 2
Test conditions
Turn-on time
(secondary voltage)
Voltage change
(83 = closed)
Sound output power
(82 = closed)
Standby operation
(81 =open)
min
ton
typ
max
350
450
ms
L1V2 sec
.1N3 =20 W
100
500
mV
L1V2 sec
.1N2 =15 W
500
1000
mV
20
75
10
30
L1V2 sec
8ec. useful load = 3W
70
f
Nprimary
V
kHz
12
VA
Pin description
Pin
Designation
Function
1
VREF output
The IC adjusts the secondary voltage of the SMPS
to a multiple of the reference voltage VREF•
2
Zero passage identification
Input for oscillator feedback. After build-up, each
zero passage of the feedback voltage (rising edge)
triggers an output pulse at pin 8. The trigger threshold
is typically -30 mV.
3
Control amplifier and
overload amplifier input
Information input for secondary voltage. The output
pulse width at pin 8 is adapted to the load on the
secondary side by comparing the control voltage
gained from the control winding of the transformer
to the reference voltage (normal, overload; .shortcircuit, open-loop operation).
4
Collector current
simulation
Information input for primary voltage. The rise of
the primary current in the primary winding is
simulated as voltage increase at pin 4 by means
of an external RC element. If a value derived from
the control voltage at pin 3 is reached, the compensating pulse at pin 8 is terminated. The RC element
serves for setting the maximum power at the point of
return. In this point, the amplitude of the sawtoothshaped voltage at pin 4 rises to the value ot VREF•
580
TDA4600-3
Pin
Designation
Function
5
Protective input
For response of the oscillator a voltage of at
least 2.7 V must be applied at pin 5. In case of
disturbance, an additional secondary pulse at pin 8
is prevented if the voltage drops below 1.8 V,
which is the protective threshold value.
6
Ground
The capacitor at pin 4 is to be directly connected
to pin 6. The primary current of the transformer is
not to be routed through this connection.
7
DC voltage output for
charging coupling
capacitor
Current sink after an output pulse and charging
source for the coupling capacitor before an output
pulse.
8
Pulse output drive of
switching transistor
Current source for output pulse.
The output current is adjusted according to the
voltage rise at pin 4 with the aid of the resistor
between pins 7 and 8. Thus, oversaturation of the
external power transistor is prevented.
9
Current supply
For start-up of the SMPS the following conditions
must be met:
- The reference voltage at pin 1 is turned off
- Subsequently, at pin 9, a rise of the supply
voltage up to a value exceeding 12.3 V
- At pin 5 the voltage is above 2.7 V.
During operation the supply voltage is monitored
for undervoltage.
For values below 6.7 V the output pulses at pin 8
are blocked and for values below 5.7 V the
reference voltage is turned off as an additional
measure. These are the preconditions for a new
oscillator start-up.
581
TDA4600-3
Block diagram
I
TDA 4600-3
H
Control
Amplifier
Start-Up
Circuit
~
I
~ f---
Overload
Identification
!
Reference
Voltage
j
II
J
I
Standby
Operation
Voltage
Control
I
l-
,
r1
Zero Passage ~
Identification
U~~llector
3
582
I
,
Trigger
Start
Hold
r
Amplifier
ICoupling-C
Charging
Circuit
I
Base Current
Shut-Down
1
Control
Logic
curren1
imulation
4
J
. - Base Current I--------
Ext. Blocking
Alternatives
T
5
I
T
6
f--
~
8
9
TDA4600-3
Measurement circuit 1
o
TDA 4600-3
3
4
8
22 pF
10llF
1 kQ
20kQ
VREF
IIlF
11
Vc10ck
Vcontrol
r"~
1N 4003
100 kQ
V9
f"
583
TDA4600-3
Measurement circuit 2
220 Vac
~.7nFlr'-'4.7nF
r.
o
'l .Jil'I,I--+-+--4
II,
B250/[1000
I
/
[2540
I _V~
j2.7110
!
I
1\/
]
+
TDA 4600-3
1
220rnFI31
220>1
1....2 kll
In
22 pF
.--+-
3
1~
100~F/25V
In
1.25A[~
.---.
,I I'
~~k>1121
'>17BY 295/450
, I
1N4007"''''' 100 ~F/25 V
,.;.
II
m
,I I'
I '
I I
10 nF 11 I
'
1~F/35V
~
IU
10k>1 [}2 k>1
270 kll
, I
I '
I !
\~1N4007
7068>1 !1!N22 9
~l
100 k>1
IU
I
_.J
2
v
II
IS 1472-K
111378108 d,BY258/200
P
LJ
B,-U_2_0~8- t - - - ,
2'~lnF
"
I
"
9x
15
13x
11
x 1
LLine Isolation
AZV
6j::'!c
16
+270 PF
470 ~F
12
4
\17~d0258/ +270 PF 'S7~ci0258/ +270 PF 'S7~ci0258/
H~
(1) Limits Ie max of BU 208 if
permissible output
power is exceeded
6
470 ~F
H~
47 ~F
H~
x 2
+270 PF
\~~60258/
22 ~F
H~
,
~
100 k>1
-c::J-
18V
25V
150V
200V
(2) Adjustment of secondary - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(3)
~~~~;c':'::':~;:" ::::1~-~;- ~~-~~_:= "--__~"
584
TDA4600-3
Application circuit
220Vac
o
TDA 4600-3
2
[,
lR9
~~
R4
10 kfl
17 ~ !1:~r2 9
4
3
~:N22
)100 kQ
0,6811
[lR6
)12 kfl
100~FIU25V
C
Rs
II'
G 4=~[1O
~
>- ~--~J-~----+-~~~Ul~~~v~
270k11
I
~:
_ ..J
i
~ine Is?latio.n
10 nF 11 I
IN 4007 U
Rl1
100~F/25V
pr 1
1I~1472-K
B78108
G 3
n .. Bhs8/200
~T1
.-7
[4
i
i
~~10R7 kQI21
I
1~~~35V
I
A
,-BU_20...
8>-+-_~
~1'
II
8,llnF
I
9x
7
(1) Limits Ie max of BU 208 if
permissible output
power is exceeded
(2) Adjustment of secondary
voltage
18V
25V
150V
200V
------------------------------------
(3) Must be discharged
before Ie change
~>-tl_,S_kQr-_
V3sec
585
TDA4600-3
Supplements to test and measurement circuit 2
Load characteristic
-.
V Output voltage versus output current
160
... . ..-. ... .-. . . . ... ... .-. . -. . . .-
~.
140
""
.:/V'
120
Vline 180V "
Vline 220V, '-
"" 100
0
~
.e'"
Cl
"0
>
:;
.9-
"
Vline 250V
80
./
60
J
'/ /
~
,/
~.
V
;l
.,
0
40
./
20
../
o
o
200
400
600
1000
800
-
Output current
1200mA
/q sec
V Output voltage versus line voltage
151
150
~
~
~
'"
Cl
,-
~ 149
g
/1-""
:;
.9-
o"
.".......
148
V
~
V
~
V
.".......
V
1£.7
150
170
190
210
230
-
586
Line voltage
250
V
TDA4600-3
Measurement diagram for overload operation, measurement circuit 1
VclOCk
Vj
t +O'~t~
+-____+-_
_ _ _ _ _I -_ _ _ _
>L S
-0,5
-f
t l~~------
IllJ1L
d
,lr'
10
I
I
I
20
30
40
>LS
-f
I
I
I
SO
60
70
>Ls
-f
- - Vcont~-10V
_ . - V cont ~O V
587
588
ControllCs for Switched-Mode Power Supplies
TDA4601
TDA4601 D
SIP9
DIP 18
The integrated circuit TDA 4601/0 is designed for driving, controlling and protecting the
switching transistor in self-osci"ating flyback converter power supplies as we" as for
protecting the overall power supply unit. In case of disturbance, the rise of the secondary
voltage is prevented. In addition to the Ie's application range including TV receivers, video
tape recorders, hifi devices and active loudspeakers, it can also be used in power supply
units for professional applications due to its wide control range and high voltage stability
during increased load changes.
Features
•
•
•
•
•
Direct control of the switching transistor
Low start-up current
Reversing linear overload characteristic
Base current drive proportional to collector current
Protective circuit for case of disturbance
589
TDA4601
TDA4601 D
Maximum ratings
Supply voltage
min
max
Vg
0
20
V1
V2
V3
V4
V5
V7
Vg
0
-0.6
0
0
0
0
0
6
0.6
Iv
Voltages
Reference output
Zero passage identification
Control amplifier
Collector current simulation
Blocking input
Base current cut-off point
Base current amplifier output
3
8
8
Vg
Vg
V
V
V
V
V
V
V
Currents
Zero passage identification
Control amplifier
Collector current simulation
Blocking input
Base current cut-off pOint
Base current amplifier output
Junction temperature
Storage temperature range
Thermal resistances:
TDA 4601
system-air
system-case
TDA 4601
system-air 1)
system-air 2)
TDA 4601 D
TDA 4601 D
li2
li3
li4
li5
Iq7
lqg
-5
5
-3
3
0
0
-1
-1.5
5
5
1.5
0
125
125
1j
mA
mA
mA
mA
A
A
°C
°C
Tstg
-40
RthSA
70
15
KlW
KlW
RthSA1
60
44
KlW
KlW
Vg
Tc
TA
o to 85
o to 70
7.8 to 18
V
°C
°C
RthSC
R thSA
Operating range
Supply voltage
TDA4601
Case temperature
Ambient temperature range 3 ) TDA 4601 D
1) "'_"'''' ..... 1"" ............
__ n ..... k __ ........ : ...... _ .•• ___ .1 __ _ .. ...i _ _ _
..., ........... ""''''' ......... _ ......................................... .......... "'~ ~ ... ,Ia. .... ...
2) Case soldered on PC board with copper-clad 35 11m layer, COOling surface 25 cm 2
3) RthSA1
590
= 44 K/W and Pv = 1 W
TDA4601
TDA4601D
Characteristics
TA =25°C
according to measurement circuit 1 and diagram
min
typ
max
11.0
1.5
2.4
11.8
0.5
2.0
3.2
12.3
mA
mA
mA
V
19
110
50
135
75
160
100
mA
mA
V,
V,
4.0
4.0
4.2
4.2
4.5
4.4
V
V
TC,
V3
2.3
10-3
2.6
2.9
11K
V
V/)
..:iVl)
Vs
1.8
0.3
6.0
2.2
0.4
7.0
2.5
0.5
8.0
V
V
V
Vq7 *)
Vqs *)
..:iVqa
V2*)
2.7
2.7
1.6
3.3
3.4
2.0
0.2
4.0
4.0
2.4
V
V
V
V
19
14
22
28
mA
Vq7
1.3
1.5
1.8
V
V4
1.8
2.1
2.5
V
Vs
"2-0 .1
V,
.YL
Vg
6.7
2
7.4
7.8
V
..:iVg
0.3
0.6
1.0
V
Start operation
Current consumption (V, not yet switched on)
Vg = 2 V
Vg = 5V
Vg =10 V
Switching point for V,
Ig
Ig
Ig
Vg
Normal operation
Vg =10
V; Veont =-10 V; Veloek = ±0.5 V; f = 20 kHz;
duty cycle 1 :2 after switch-on
Current consumption
Veont =-10V
Veont-OV
Reference voltage
I, <0.1 mA
I, =5 mA
Temperature coefficient of
reference voltage
Control voltage Veont = 0 V
Collector current simulation voltage
Veont=O V
Veont =0 V/-10 V
Clamping voltage
Output voltages
Veont=O V
Veont=O V
Veont =0 V/-10 V
Feedback voltage
Ig
Protective operation
Vg =10
V; Veont =-10 V; ""lOCk = ±0.5 V; f = 20 kHz;
duty cycle 1 : 2
Current consumption
Vs <1.9 V
Switch -off voltage
Vs <1.9 V
Switch-off voltage
Vs <1.9 V
Blocking input
Blocking voltage
Veont=O V
Supply voltage blocked for Va
Veont=O V
Vi off (with further reduction of Vg)
V
0) DC component only
591
TDA4601
TDA4601 D
Characteristics
TA = 25 °C; according to measurement circuit 2
typ
max
ton
350
450
ms
dV2sec
100
500
mV
dV2sec
500
1000
mV
20
75
10
30
V
kHz
VA
min
Switching time (secondary voltage)
Voltage variation
S3 = closed
dN3 =20 W
Voltage deviation
S2 = closed
dN 2 =15 W
Standby operation
S1 =open
secondary useful load = 3 W
dV2sec
f
70
Nprimary
12
The cooling conditions have to be optimized with regard to maximum ratings (TA ; 1j; RthJC ;
RthSA)·
Circuit description
The TDA 4601 is designed for driving, controlling and protecting the switching transistor
in flyback converter power supplies during start-up, normal and overload operations as well
as during disturbed operation. In case of disturbance the drive of the switching transistor
is inhibited and a secondary voltage rise is prevented.
I. Start-up
The start-up procedures (on-mode) include three consecutive operating phases as follows:
1. Build-up of internal reference voltage
The internal reference voltage supplies the voltage regulator and effects charging of the
coupling electrolytic capacitor connected to the switching transistor. Current consumption
will remain at Ig < 3.2 rnA with a supply voltage up to Vg approx. 12 V.
2. Enabling of .internal voltage - reference voltage V;
=4 V
Simultaneously with Vg reaching approx. 12 V, an internal voltage becomes available,
providing all component elements, with the exception of the control logic, with a thermally
stable and overload-resistant current supply.
3. Enabling of control logic
In conjunction with the generation of the reference voltage, the current supply for the
control logic is activated by means of an additional stabilization circuit. The integrated
circuit is then ready for operation.
The above described start-up phases are necessary for ensuring the charging of the coupling
eieGiroiytic capacitor, wmcn In turn supplies the switching transistor. Only then is it possible
to ensure that the transistor switches accurately.
592
TDA4601
TDA4601 D
II. Normal operating mode/control operating mode
At the input of pin 2 the zero passages of the frequency provided by the feedback coil
are registered and forwarded to the control logic. Pin 3 (control input, overload and standby
identification) receives the rectified amplitude fluctuations of the feedback coil. The control amplifier operates with an input voltage of approx. 2 V and a current of approx. 1.4 mAo
Depending on the internal voltage reference, the overload identification limits in conjunction
with collector current simulator pin 4 the operating range of the control amplifier. The collector current is simulated by an external RC combination present at pin 4 and internally set
threshold voltages. The largest possible collector current applicable with the switching
transistor (point of return) increases in proportion to the increased capacitance (10 nF).
Thus the required operating range of the control amplifier is established. The range of control
lies between a dc voltage clamped at 2 V and a sawtooth-shaped rising ac voltage, which
can vary up to a max. amplitude of 4 V (reference voltage). During secondary load reduction to
approx. 20 W, the switching frequency is increased (approx. 50 kHz) at an almost constant
pulse duty factor (1 :3). During additional secondary load decreases to approx. 1 W, the
switching frequency increases to approx. 70 kHz and pulse duty factor to approx. 1 :11. At
the same time collector peak current is reduced to < 1 A.
The output levels of the control amplifier as well as those of the overload identification
and collector current simulator are compared in the trigger and forwarded to the control
logic. Via pin 5 it Is possible to externally inhibit the operations of the IC. The output at
pin 8 will be inhibited when voltages of::,; V2EF -0.1 V are present at pin 5.
Flipflops for controlling the base current amplifier and the base current shut-down are set in
the control logic depending on the start-up circuit, the zero passage identification as well
as on the enabling by the trigger. The base current amplifier forwards the sawtooth-spahed V4
voltage to the output of pin 8. A current feedback with an external resistor (R = 0.68 Q) is
present between pin 8 and pin 7. The applied value of the resistor determines the max.
amplitude of the base driving current for the switching transistor.
III. Protective operating mode
The base current shut-down activated by the control logic clamps the output of pin 7 to 1.6 V.
As a result, the drive of the switching transistor is inhibited. This protective measure is
enabled if the supply voltage at pin 9 reaches a value::,; 6.7 V or if voltages of
are present at pin 5.
V~F
-0.1 V
In case of short-circuits occurring in the secondary windings of the switched-mode power
supply, the illtegrated circuit continuously monitors the fault conditions. During secondary,
completely load-free operation only a small pulse duty factor is set. As a result the total
power consumption of the power supply is held at N = 6 ... 10 W during both operating
modes. After the output has been inhibited for a voltage supply of ::,; 6.7 V, the reference
voltage (4 V) is switched off if the voltage supply is further reduced by .:1Vg = 0.6 V.
593
TDA4601
TDA4601D
Protective operating mode at pin 5 in case of disturbance
The protection against disturbances such as primary undervoltages and/or secondary overvoltages (e.g. by changes in the component parameters for the switched-mode power supply)
is realized as follows:
•
Protective operating mode with continuous fault condition monitoring
In case of disturbance the output pulses at pin 8 are inhibited by falling below the protective
threshold V5 , with a typical value of V/2. As a result ·current consumption is reduced
(Ig ~ 14 mA at Vg = 10 V).
With a corresponding high-impedance start-up resistor"), supply voltage Vg will fall below
the minimum shut-down threshold (5.7 V) for reference voltage V 1 • V1 will be switched off
and current consumption is further reduced to Ig $; 3.2 mA at Vg $; 10 V.
Because of these reductions in current consumption, the supply voltage can rise again to reach
the switch-on threshold of Vg ~ 12.3 V. The protective threshold at pin 5 (is released and the
power supply is again ready for operation.
In case of continuing problems of disturbance (V5 $; V1/2 -0.1 V) the switch-on mode is
interrupted by the periodic protective operating mode described above, i.e. pin 8 is inhibited
and Vg is falling, etc.
Block diagram
,
Start-Up
Circuit
-1
Control
Amplifier
Ir-
Standby
Operation
J
~
I
Overload
Identification
~-
Zero Passage
Identification
f- J
I
t
~I
Ii
Voltage
Control
•
Reference
Voltage
•
I
t
0) in application circuit 1 10 kQ/3 W
594
Trigger
Start
Hold
~
I
Control
Logic
Collector Current
Simulation
t
4
I
r,
~"M c,"'"'
Amplifier
Coupling-C-.
Charging
Circuit
I
Base Current
Switch-Off
I
Ext. Trigger
Blocking Function
t
T
f--~
TDA4601
TDA4601 D
IV. Switch-on in the wide range power supply (90 Vac to 270 Vac)
(application circuit 2)
Self-oscillating flyback-converters designed as wide range power supplies require a power
source independent of the rectified line voltage for TDA 4601. Therefore the winding polarity
of winding 11/13 corresponds to the secondary side of the flyback converter transformer.
Start-up is not as smooth as with an immediately available supply voltage, because TDA 4601
has to be supplied by the start-up circuit until the entire secondary load has been charged.
This leads to long switch-on times, especially if low line voltages are applied.
However, the switch-on time can be shortened by applying the special start-up circuit (dotted
line). The uncontrolled phase of feedback control winding 15/9 is used for activating purposes.
Subsequent to activation, the transistor T1 begins to block when winding 11/13 generates
the current supply for TDA 4601. Therefore, the control circuit cannot be influenced during
operation.
Pin description
Pin
Function
2
3
4
5
6
7
8
9
10-18
VREF output
Zero passage identification
Input control amplifier, overload amplifier
Collector current simulation
Connection for additional protective circuit
Ground (rigidly connected to substrate mounting plate)
DC outupt for charging coupling capacitor
Pulse output-driving of switching transistor
Supply voltage
Ground (TDA 4601 D only)
595
TDA4601
TDA4601 D
Circuit diagram
596
TDA4601
TDA4601 D
Test and measurement circuit 1
o
TDA 4601
4
R,
Rs
R4
2.2 kl1
R3
20kl1
[3
'fi
~
VREF
1,
100 kl1
10kl1
J
C,
"I~F
10nF .l.. V
+
T_
[a
lO
08
U9
Vconl
Vclock
[9Tl0~F
Rs ""
2711
Test diagram: overload operation
V
Vclock
1+0~5
I
10
20 l30
-0,5
V4
I
30
.... ' '---
2
I
40
J
60
70
80
-
____ t
~s
Veonl~-10V
---- Veont ~ 0
+------------------------------~s
VB
8
r
6
4
rr,---
I
I
I
I
I
I
I
2)!.,
-t
I
I
I
I
I
I
I
~
~----------------------------~s
--t
597
TDA4601
TDA4601D
Test and measurement circuit 2
~---~
4,7nF
220 Vac
o
11~.7nF.-l--+==j:-::::j-'
r----
I
I.
I
12,7\1
I
i
I
I
I
1
B 2501
1-----------
[1000
TOA 4601
1N4007
I I
~i I
~l 1
"I .
:J 1
I
I
1
1
I
I
I
___I
BY 25B/200
2,2 nF
lJI~~~~~~~~7~9:*~;:i:~~~==~1~3~*~:i~~ii:1~1i:~*1
L.Line Isolati~ __ . _ . _ _ _ _ _ . _
BY 25BI
270 pF
800
18V
1) Limits Ie max of BU 208
if the permissible
output power is exceeded
2) Adjustment of secondary
voltage
3) Must be discharged
before Ie change
-
-
598
-
25V
56kl1
150V
100kl1
I
6200V
-----------------------------------------
10011
5611
S1
r===~-120;==32===~-:,~~=S2===~S1
=="J]
~
·Protective circuit against rise of secondary
voltage in case of disturbance
3311
~
1.5kl1
V1 sec
TDA4601
TDA4601D
Notes on application circuit 1
Protective circuit against secondary voltage rise even in case of disturbance
During standby this circuit type is necessary only under certain conditions. If switch 81 is
open and the secondary side is loaded with no more than 1 to 5 W, a secondary voltage
overshoot of approx. 20% will occur.
In case of disturbance (e.g. if the potentiometer is loosely contacted resulting in 10 kQ (2),
if the capacitor exhibits a 1 J.1F loss in capacitance, or if the 2 kQ resistor increases to a
high-impedance value of 32 kQ), the protective effect of the standard turn-off is not active
before the point of return has been reached. The result is that during disturbance energy
is pumped into the secondary side, which will not ease off before reaching the point of return
and, in the worst case, entails an instantaneous doubling of the voltage to 300 V (endangering
the secondary electrolytic capacitors).
This additional protective circuit, which identifies the energy surge as voltage overshoot,
is directly active at control winding 9/15. Through the 56 Q resistor and the 1N4001 rectifier
the negative portion is deducted and stored in the 10 J.1F capacitor. If the amplitude exceeds
the voltage of Z-diode BZX 83/39, pin 5 is drawn below the turn-off threshold, inhibiting
further control pulses at pin 8. During disturbance conditions the voltage overshoot on the
secondary side will assume maximum values of approx. 30%.
599
TDA4601
TDA4601D
Supplements to test and measurement circuit 2
Frequency versus output power
kHz
100
80
1,.,
'-'
60
"II>
:\.
""'-
~
0-
e
u..
40
~
..........
r-. r--...
;
20
o
20
40
-----60
80
100
120 W
Output power _ _ _
Efficiency versus output power
%
100
I,.,
80
"
in
60
'-'
/
II>
·0
40
20
V
V
/
/
I
I
o
20
40
60
80
100
Output p o w e r -
600
120 W
TDA4601
TDA4601 D
Supplements to test and measurement circuit 2
Load characteristicsV2sec = f (I2sec )
V
160
-- -- -- -
1-,
--
-
140
t
/) ~
120
"" ~/
,, , //'
,/( V
250V
o
~
~ 100
Q)
Cl
.l!!
g
"/,
BO
""
Vline lllDV --; /.
:J
C.
:;
o
- '\.',
--,
-- -
60
Vi
Vline 220V
/ l.1"
/b
40
6'
;'~
20
o
line
,~
~'
~
o
100
200
300
400
500
600
700
BOO
900
Output current 12sec
1000 1100
1200 rnA
-~
V Output volta9.e V2sec (Line change)
151
r
150
o
::
~
Q)
Cl
./
Jl! 149
g
:;
c.
:;
o
/
14B
/
V
~
V
V
v
V
V
V
147
150
160
170
1BO
190
200
210
220
230
240
250
260 V
Line voltage -
601
TDA4601
TDA4601 D
Application circuit 2
Wide range from 80 to 270 Vac
80 to 270 Vac
~r'lll
.7nFlil-rll~·7nF
! i
V.
!
b
(2540
-~+
11
iKt,
! I
!
I
i
I
In
Si 1.25A
~F~~V
100
47ci~F31
non
[
:J.&l
~
7
8
~
[ 12
kn
2il
1>-
47nF 11
',i
BY
360
i
8.2l F
II
....:c::5-
(~8
2.7kn
100~F/25V
~
2x
II
10k~ J
UI
.A ~TC-J29
9
IIN22
047Q
V"
1~Fri~5V
'In
IU
~100~FJ25V
IN 4007
I
17
1.5flH
~
II
i
270 kll
i
i
-------.r
c..!2
UBU208
I
-=
I
Hif
lD139
'Il BY36O
B~231
.
5.\[
kn
OV
BY 299
100n[
'Il BY360
\
"-----
15 x
3311
13
11
'--'
r
4·irF
lr
x9
x5
!L-.Line. Isolation
. . .
16
1) Limits Ie max of BU 208,
if permissible output
power is' exceeded.
2) Adjustment of
secondary voltage.
3) Must be discharged
.before Ie change.
14
1
1000 ~F
r-1~
AZV
2210
4
x
12
O.1n
270PFt BYW29
f--O
602
6
II
~
I
i
I
i
5
H~
270kn
i
I
i
i
i
4
3
10kn[
i
i
_.J
2
IU
I
I
TDA 4601
1
i
I
"
0
B2501
C1000
270 PF t BY299
270 PFV BY298~
~O~
n~F
r-1~v,
TDA4601
TDA4601 D
Notes on application circuit 2
Wide range SMPS
Filtering of the rectified ac voltage has been increased up to 470 [IF to ensure a constant
and hum-free supply at lIIine = 80 Vac. The stabilized phase is tapped for supplying the IC.
In order to ensure good start-up conditions for the SMPS in the low voltage range, the
non-stabilized phase of winding 13/15 is used as a starting aid (BD 139). which is turned
off after start-up by means of Z diode C12.
In comparison to the 220 Vac standard circuit, however, the collector-emitter circuit had to
be altered to improve the switching behavior of BU 208 for the entire voltage range (80 to
270 Vac.) Diode BY 231 is necessary to prevent inverse operation of BU 208 and may be
integrated for switching times with a secondary power < 75 W (BU 208 D).
Compared to the IC TDA 4600-2, the TDA 4601 has been improved in turn-off during undervoltage at pin 5. The TDA 4601 is additionally provided with a differential amplifier input
at pin 5 enabling precise turn-off at the output of pin 8 accompanied by hysteresis. For
wide range SMPS, TDA 4601 is recommendable instead of TDA 4600-2. If a constant quality
standard like that of the standard circuit is to be maintained, wide range SMPS (80 to
270 Vac) with secondary power of 120 W can only be implemented at the expense of time.
603
TDA4601
TDA4601D
Thermal resistance
Standardized, ambient-related thermal resistance
copper-clad cooling area (35 Ilm copper cladding)
R thJA
RthJAl
(I = 0) = 60 KlW
TA
=70°C
Pd
=1 W
PC board in vertical position
Circuit in vertical position
Still air
1,0 , - - - - - - - - - , - - - - - - - - - - ,
R thJA11!L
RthJA (/-0)
0,9
0,8
RthJAl
R thJA
=
f (I)
0,6
50
100 mm
-I
604
versus lateral length I of a square
TDA4601
TDA4601D
Further application circuits
Application circuit 3
220 Vac
14.7nFl~·~:4.7nF
~!II' I!.
.
.!
I
I
. /
v.
B2501
Cl000
C2540
b
ii ij2.7nl -I\/---t>I- +
l
i L-+-+--_+_---'
i i
i i
I i
j
i
i i
i i
i
o
/
TDA 4601
1-,1""--"::'2r-""'3"'-'""4'--"'5---"6---:7:.---,Sr--9.......
A ~TC-)29
2.7kn
1,2SA
10kll[
27O'iill
i
I
i
1 ~F~~5V
[ 12
kll
~
~_+-10_0--l~~
8 2nF 11
"ii'
II
Jtokll21
=i=100~F/25V
~
L~
UI
8·~tF
BY 258/20
~I7BY360
II
) 1001l
15
1~._._._._._._._._._._.~::::::::::~
~1~3:x::::::::::~1~1~x 1 AZV
-'-'-'-'-'-'-'-'-'-'-'6i:j('9x
L.,.~~~o~i~._.
7
......
x2
16
BY 25S/SOO
270 pF
1) Limits Ic max of BU 208
if permissible output
power is exceeded.
2) Adjustment of
secondary voltage.
3) Must be discharged
before Ie change.
470~F
200V
lBV
~
1.5 kll
V, sec
605
TDA4601
TDA4601D
Notes on application circuit 3
Fully insulated, clamp-contacted
start-up currents
PTe thermistor suitable for SMPS applications at increased
The newly developed PTe thermistor Q631 OO-P2462-J29 is designed for applications in SMPS
as well as in various other electronic circuits, which, for example, receive the supply voltage
directly from the rectified line voltage and require an increased current during turn-on. Used
in the flyback converter power supply of TV sets, an application proved millions of times
over, the new PTe thermistor in the auxiliary circuit branch has resulted in a power saving
of no less than 2 W. This increase in efficiency has a highly favorable effect on the standby
operation of TV sets.
The required turn-on current needs only 6 to 8 s until the operating temperature of the PTe
thermistor is reached. Low thermal capacitance of the PTe thermistor allows the circuit
to be operated again after no more than 2 s. Another positive feature is the improved shortcircuit strength. The clamp contacts permit more or less unlimited switching operations
and thus guarantee high reliability. A flame-retardant plastic package and smarr dimensions
are additional advantages of this newly developed PTe thermistor.
Technical data
Breakdown voltage at TA = 60°C
Resistance at TA = 25°C
Resistance tolerance
Trip current (typ.)
Residual current at VA max
Max. application voltage
Reference temperature (typ)
Temperature coefficient (typ)
Max. operating current
Storage temperature range
606
VSDrms
R25
LlR25
IK
IR
Vop max rms
Tref
TC
Imax
Tstg
350
5
25
20
2
265
190
26
0.1
-25 to 125
V
kQ
%
mA
mA
V
°C
%/K
A
°C
TDA4601
TDA4601 D
Application circuit 4
220 Vac
bqF~4'7nF
I
I
.
i2.7 n
i i
i i
i
i
i
i
!
B2501
(1000
~ (2540
-I'Y+
0
P
TDA 4601
1
2
3
4
100~F/~V
22d~F 3)
1.2kl.!
IU
1,25A
10kn[
2ml.!
i
i
H~5V
I
i
i
_.-.i
i Line Isolation
L._._._._._.
~
Yp:Tc...-J29
IIN22
0681.! II
~
2~
100~rri25V
[ 5,6
kl.!
IU
68nF l )
'-II
II
Y,okl.! 2)
=i=100~F/25V
flN~J07
I~~1472-K
B78108
~I7BY 295/450
22IIF
II
~
U
[ 331.!
L BY 258/20
BU508A
112,2 nF
II
9x
7
16
13 x
15
6
12
270 PF t
) Limits Ie max of BU 508 A
if permissible output
power is exceeded.
2 ) Adjustment of
secondary voltage.
3 ) Must be discharged
before Ie change.
/I
9
II
~~
cd
~
8
7
100kn
~
i
i
i i
i i
i i
i i
6
5
100pF
220n
In
"'
"
11
4
~~
270pF
~~
18V
25V
33n
AZV
.- i-:j{'x2 6
~Y258/600 F t ~Y258/600 :~ tPY258/600
270pF
x1
:t
270pF
~t;-
~~
~ 150V
~
BY2 58/800
200 v
1,5kQ
~>--i:::::::J--'
607
TDA4601
TDA4601D
Notes on application circuit 4
Improved load control and short-circuit characteristics
Turn-on is the same as for circuit 3.
To make the price more attractive, switching transistor au 50BA was selected.
To ensure optimum standby conditions, the capacitance between pins 2 and 3 was increased
to 100 pF.
Z diode C6.2 transfers control voltageLlVcont directly to pin 3 resulting in improved load
control.
Design and coupling conditions of various flyback transformers were sometimes a reason
for overshoot spectra, which, despite the RC attenuating element 33 Q x 22 nF and the
10 kQ resistor, even penetrated across the feedback winding 9/15 to the zero passage
indicator input (pin 2) and activated double and multiple pulses in the IC. Double and multiple
pulses, however, lead to magnetic saturation in the flyback transformer and thus increase
the risk of damaging the switched-mode power supply.
The larger the quantities of power to be passed, the more easily overshoots are generated.
This can be observed around the point of return. The switched-mode power supply, however,
reduces its own power to a minimum for all cases of overload or short-circuit A series
resonant circuit, whose' resonance corresponds to the transformer's self-oscillation, was
created through combination of the 4.7 IJ.H inductance and the 22 nF capacitance. This
resonant circuit short-circuits overshoots via a 33 Q resistor.
(f =
608
1
2ny[C
approx. 500 kHz)
TDA4601
TDA4601D
Application circuit 5
220Vac
9PE
I
I
I
I
I
II
2x
47mH
Si 2A
Dn
330nF
I~
TDA 4601 D
4
8
6
9
II
I
INn
2211
I I
ro--
100~F/25V ~w
in
II
r
2.2, F 150 ~H
II
3,~,nF
33011[
270kl1
II
[ 33011
L~
__________~4X::::::~3Jl
x 1 TO
~--~x9
~____~----~~
I
r~,~---.
~
1) Limits Ie max of BLU--50-8-A----+---~'-I-L--./----5'
if permissible output
voltage is exceeded.
TL 431
2) Adjustment of
secondary voltage.
3) Must be discharged
before Ie change.
4) Optional use,
~
depending on safety class:
Safety class II 1 nF only
Safety class I with non-fused
grounded conductor 3.3 nF only
10 ~
BYW72~~
BY360~
~~
~~
1'1
CNY1Hl
4 r -------,1
7 I
:
f
3012
flL4
[ 47011
r"\
~
1000pF l
f--\~
100~ }.3 kl1
47Oi1
,....,2::
~
LI'iiJ121 2,2 k11
12V
41V
609
TDA4601
TDA4601D
Notes on application circuit 5
Highly stable secondary side
Power supplies for commercial purposes require highly constant low voltages and high
currents which, on the basis of the flyback converter principle, can be realized only under
certain conditions, but, on the other hand, are implemented for economical reasons. An
electrically isolated flyback converter with a highly stable secondary side must receive the
control information from this secondary side. There are only two possibilities of meeting
this requirement: either through a transformer which is magnetically isolated from the flyback
converter or by means of an optocoupler. The development of CNY 17 has enabled the
manufacture of a component suitable for electrical isolation and characterized by high
reliability and long-term stability.
The IC TDA 4601 0 is the sucessor of the TDA 4600 D. It is compatible with its predecessor
in all operational functions and in the control of a self-oscillating flyback converter. Pin 3 is
the input for the control information, where the latter is compared with the reference voltage
prevailing at pin 1 and the control information from the optocoupler and subsequently
transformed into a frequency/pulse width control.
The previous feedback and control information winding is not necessary. The feedback
information (zero passage) is obtained from winding 3/4 - supply winding. The time constant
chain 330 0/3.3 nF and 330 0/2.2 nF was implemented in series with 150 J.LH to prevent
interference at pin 2. The LC element forms a series resonant circuit for overshoots of the
flyback converter and short-circuits them.
610
TDA4601
TDA4601D
Application circuit 6
Non-Fused
Grounded
Conductor
?
90 to 260 Vac
JL
330nF
I 2~1
I
47mH
1~
V
K23I~ Y
B2501
151
P
( 1000
(2540
~
f-j~
16
17
121
111
Y
2
3
4
1.2 kl1
5
6
7
8
IIN22
5.6 kl1
~
Hf-
~'
IU
100~rn125V
10 [ 12
kl1
kl1
2~
~Okn2)
II
'" =100~F/16V
flN~07
2
II
1~~~5V
I
UI
' BY360
3,3nF
~
IU
47nFl)
"JL
68~r!!.
Jlnf"
~ PTC. .. -J29
9
I I
100pF
22011
Si 0.5A ~
101
TDA 46010
1
100~~~V
13
141
2,2~H
~
JL
II
270kn
-( 11
......
[ 5,1 kl1
~~ov
loon
1~
3,3nF
J
2
1
639
BY360
U
BY360
BU508A
--2,21pF
II
1
N2
5t urns
560.Q
-
~
I
I
I
L+
2,2nF
1) Limits /,Cmax of BU 508 A
if permi ssible output
power is exceeded.
2) Adjustm ent of secondary
voltage.
3) Must be discharged
before IC chan g e.
6x
2
5
x3
x1
11/12
10
1
x4
AZV
2196
270PFt I7BYW72
270 PF t 7BY360
1---0
4
~
10~F
1000~F
I---/~-<
I---/~
V2 44V110mA
V, 12V/2A
611
TDA4601
TDA4601 D
Notes on application circuit 6
Wide range plug SMPS up to 30 W
Due to their volume and weight, plug SMPS have so far been limited to a restricted primary
voltage and a secondary power of no more than 6 W.
The line-isolated wide range flyback converter presented here has a variable frequency and
is capable of producing a secondary power of 30 W. It is characterized by a compact
design with an approx. weight of 400· g. The entire line voltage range of 90 to 260 Vac
is stabilized to ± 1.5% on the secondary side. Load fluctuations between 0.1 and 2 A
are regulated to within 5%. The output (secondary side) is overload, short-circuit, and openloop proof.
612
TDA4601
TDA4601 D
Application circuit 7
90 to 260 V ac
o
p
TDA 4601
3
4
8
,;I
9
~TC. -J 29
"
IIN22
047<;) II
o--b-
1,5~H
L
1
~
16
1) Limits Ie max of BU 208
if permissible output
power is exceeded.
2) Adjustment of secondary
voltage.
3) Must be discharged
before Ie change.
14
1
iJ
BYW29
1000 ~F
f-lV3
II
x4
12
J
0.1<;)
270P F
/----D
J
BY 360
270PF~
270 PF t 17BY299
BY298~
470~F
22~F
f--j~
f--j~V2
V1
613
TDA4601
TDA4601 D
Notes on application circuit 7
Wide range SMPS with reducing peak collector current Ie BU 208 for rising line voltage
(variable point of return)
Wide range SMPS have to be dimensioned at line voltages of 90 to 260 Vac. The difference
between the maximum collector current Ie BU 208 max and the largest possible limit current
Ie BU 208 limit which causes magnetic saturation of the flyback transformer and flows through
the primary inductance winding 5/7 is to be determined atVaCmin (Ie BU 3081imit~ 1.2 X IeBU208max).
Then, the transmissible power of the flyback transformer and its value at Vac max is to be
determined. In the standard circuit the collector current Ie BU 208 max is almost constant at
the point of return independently of the line voltage. The transmissible power on the
secondary side, however, increases at the point of return in proportion to the rising rectified
line voltage applied (figures 1 and 2).
In the wide range SMPS a line voltage ratio of 270/90 = 3/1 is obtained causing doubling
of the transmissible power on the secondary side, i.e. in the wide range SMPS a flyback
transformer had to be implemented that was much too large.
The point of return protecting the SMPS against overloads or short circuits, is derived from
the time constant at pin 4 r 4 = 270 kQ x 4.7 nF. Thus, the largest possible pulse width
is determined.
With the introduction of the 33 kQ resistor this time constant is reduced as a function of
the control voltage applied to winding 13/15, rectified by diode BY 360 and filtered by
the 1 ~F capacitance, which means that the pulse time becomes shorter. By means of the
Z diode C18 the line voltage level can be defined at which the influence of the time constant
correction becomes noticeable. The change in the rectified voltage of winding 13/15 is
proportional to the change in the rectified line voltage.
At the point of return Ie BU 208 the peak collector current has been reduced with the aid of
the given values from 5.2 A at 90 Vac to 3.3 A at 270 Vac. The transmissible power at the
point of return remains stable between 125 and 270 Vac due to the set activation point of
the point of return correction (unbroken curve in fig. 2).
614
TDA4605
SMPS IC for Control of SIPMOS Transistors
DIPS
Preliminary data
This IC is designed for controlling an MOS power transistor and performing all necessary
protective and control functions in self-oscillating flyback converter power supplies. Owing
to the IC's outstanding voltage stability, which is maintained even at substantial fluctuations,
the IC is suited for consumer as well as for industrial applications.
•
•
Direct control of the switching transistor
Reversing linear overload characteristic
Description of function
The power transistor and primary winding of the flyback transformer, which are connected
in series, receive direct supply of the input voltage. During the on-phase of the transistor,
energy is stored in the primary winding and during the off-phase it is released to the
consumer via the secondary winding. The IC controls the power transistor in such a way
that the secondary voltages are kept at constant values independently of input or load
changes. The control information required is obtained from the input voltage during the
on-phase and from a control winding (secondary winding) during the off-phase. Load
differences are compensated by altering the frequency, input voltage fluctuations are
additionally counteracted by altering the pulse duty factor. This results in the following loaddependent modes of the SMPS:
- Open-loop or small load: output voltage slightly above set value
- Control:
load-independent output voltage
in case of overload or short-circuit, the secondary voltage is
- Overload:
decreased from the point of return as a function of the load
current, following a reversing characteristic
Typical values of pulse duty factor v, switching frequency f and duration of primary phase t
of the power transistor:
Mode
v
flkHz
tillS
Open-loop
Small load (5 W)
Control mode (30-100 W)
Reversing point 150 W
Short-circuit
0.1
0.33
0.33
<0.5
0.02
150
80
40
20
1.5
0.7
2.5
5.6
<25
<15
615
TDA4605
Description of use
A flyback converter designed for color TV sets, applicable between 30 Wand 120 Wand
for line voltages ranging from 90 to 140 V, is shown in one of the following figures. On the
subsequent pages the major pulses can be found.
The line voltage is rectified by bridge rectifier Gr1 and smoothed by C3 .
During start-up the IC current is supplied via resistors R2 and R3 , and in the post-transient
condition it is additionally supplied via winding 13/11 and rectifier D3. The size of filter
capacitor Cs determines the turn-on behavior.
Switching transistor T1 is a BUZ 45. Parallel capacitance Cg and primary winding 1/7 form
a resonant circuit, thus limiting the frequency and amplitude of drain-source voltage overshoots during turn-off of T1. Self-oscillation is attenuated by R14 • Diode D5 limits positive
overshoots. R'2 prevents static charging of the gate of T1. D1 improves the turn-off behavior.
The current rise in T1 is determined by the inductance of the primary winding. This sawtoothshaped rise is simulated at network R7 C 4 and applied to pin 2 of the IC.
Depending on the dimensioning of the primary inductance, timing element R 7 C 4 is to be
adapted to the current rise angle in T1. Thus, during the on-phase, the IC receives the
control information in the form of the simulated energy content of the primary winding
at pin 2 as a function of line voltage versus time.
The control deviation at pin 1 is recorded by control winding 9/15. This measure requires
fixed coupling with the secondary winding 2/16. The control winding is also used for feedback
and permits self-oscillation of the parallel circuit Cg/primary inductance if the power transistor
is inhibited. Thus, the maximum possible open-loop frequency is determined.
The control voltage required for pin 1 is rectified by diode D4 and smoothed by capacitor C7 •
Furthermore, R'3 and Ce form a timing element, which serves for filtering fast changes in
the control voltage, i.e. the final element does not become active until several periods have
occurred. By means of the voltage divider formed of resistors Re, R g, RlO , the secondary
voltage can be set. Reason: in the IC the control voltage produced at pin 1 is compared
with a stable, internal reference voltage.
According to the result of this comparison, frequency and pulse duty factor are corrected
until the secondary voltage selected by RlO has established itself. For all operating modes
of the SMPS, the zero passages of the voltage at the control winding contain information
on pulse duty factor and switching frequency of the switching transistor T1, or the open-loop
frequency. Conditioning of the corresponding signal at pin 8 is performed by series resistor R11 and by integrated limiter diodes.
An SMPS based on these principles would have a point of return dependent on the line
voltage. With respect to the distance to the saturation point, the transformer must be
dimensioned for maximum power, i.e. for maximum line voltage and the power then occurring
at the point of return.
616
TDA4605
In order to keep the size of the transformer as small as possible, the IC makes the point
of return largely independent of the rectified line voltage. If necessary, the reverse point
correction of the IC can be altered by a network from pin 7 to ground. The information
on the line voltage is applied to pin 3. Before the line voltage falls below as minimum
value, the SMPS must be turned off by the IC in order to obtain defined turn-off conditions.
During undervoltage, the information required for turn-off is applied to pin 3 via the resistive
divider R4IRs. On the secondary side the output voltages II; sec to V4 sec are available. If the
secondary side is further deloaded, standby is set automatically. Resistor R1S forms a basic
load of voltage II; sec and contributes to maintaining standby conditions (Vsec rise 20%).
Capacitors C10 and C13 prevent spikes generated by reversing the rectifiers 07 through 09.
The secondary voltages are smoothed by charging electrolytic capacitors C14 through C17•
617
TDA4605
Circuit description
Pin 1
In the control and overload amplifier. the control voltage supplied to this pin is
compared with two stable, internal reference potentials - in the control and overload
mode with Veant, in the case of a short-circuit with Vshort. The output of this stage
operates on the stop comparator.
Pin 2
By means of the external RC combination in conjunction with the primary current
voltage converter, a voltage is generated which is proportional to the collector
current of the switching transistor. Controlled by the control logic and referred to
the internal stable voltage V2S ' the output of this converter operates on the stop
comparator and the output stage. If voltage V2 exceeds the output voltage of the
control amplifier, the control logic is set back by the stop comparator and, as a
result, the output of pin 5 is put to low potential. Other inputs for the logic stage
are the output for the start pulse generator with a stable reference potential Vst
as well as the operating voltage monitoring.
Pin 3
The applied, scaled down primary voltage stabilizes the point of return. Furthermore,
in case of undervoltage, the control logic is blocked by comparison with the internal
stable voltage Vv in the primary voltage monitoring block.
Pin 4
GND
Pin 5
In the output stage the output signals generated by the control logic are converted
into driving suitable for MaS power transistors.
Pin 6
For the operating voltage monitoring, a stable internal reference voltage VREF and
the switching thresholds V6A , V6!; V6 max and V6 min are derived from the supply
voltage at pin 6. VREF is the basis for all reference magnitudes (Veanh VShort' V4S ' Vst).
If V6 > V6E , VREF is switched on; if V6 < V6A , it is turned off. Furthermore, the control
logic is enabled only with V6 min < V6 < V6 max.
Pin 7
In the reverse point correction block, the rectified, scaled down line voltage of
pin 3 serves for correction. If required, the correction can be altered by a network
from pin 7 to ground. The output of this block influences the primary current voltage
converter and stop comparator stages.
Pin 8
The zero passage detector, which drives the control logic block, recognizes the
discharged state of the transformer by means of the zero passage of voltage Vg
from positive to negative values and enables the control logic for the pulse start.
At the end of the pulse parasitic oscillations at pin 8 may occur (ringing of transformer),
which cannot cause a new pulse start (double pulse) however, since an internal
circuit makes the zero passage detector inactive for a limited period of time.
618
TDA4605
1. Start-up behavior
On page 61 the start-up behavior of the application circuit is illustrated for a line voltage
that is barely above the value for undervoltage.
After application of the line voltage at the point in time to, the following voltages build up:
- V6 according to the hallwave charge across R2 and R3
- V2 to V2rnax (typ. 6.2 V)
- V3 to the value given by divider R41Rs
The current consumption of the Ie in this mode of operation is smaller than 1.5 mA.
When V6 reaches the threshold V6E (time t1), the Ie turns on the internal reference voltage.
The current consumption increases to typically 12 mA. The primary-current voltage transformer
reduces V2 to V28 and between time ts and t6 the start-pulse generator will produce the start
pulse. The feedback at pin B starts the next pulse and so on. All pulses, including the
start pulse, are controlled in width by the control voltage at pin 1. Upon turn-on this
corresponds to the case of short-circuit, i.e. V1 = 0 V. Thus, the Ie starts with "short-circuit
pulses" that widen according to the feed-back control voltage. The Ie operates in the point
of return. Afterwards the peak values rapidly drop to V2 because the Ie is operating in the
control range. The control loop is stabilized. If voltage V6 falls below the cutout threshold
V6rnin before the point of return is reached, the start will be interrupted (pin 5 goes Low).
The Ie remains turned on, so V6 drops further to V6A- Then the Ie turns off, V6 can build
up again (time (4 ) and a new turn-on attempt begins at time t1 . If the rectified line ac voltage
(primary voltage) breaks down because of the load, V3 can, as happens at time t3 , fall
below V3A (turn-on attempt with undervoltage). The primary-voltage monitoring then clamps
V3 to V3S until the Ie turns off (V6 < V6A ). Then a new turn-on attempt is started at time t 1 •
2. Control, overload and open-circuit behavior
When the Ie has started up, it operates in the control range. The voltage on pin 1 is typically
400 mV.
When the output is loaded, the control amplifier permits wider charge pulses (Vs = H).
The peak value of the voltage at pin 2 increases to V2Srnax' If the secondary load is increased
further, the overload amplifier will start to reduce the pulse width. Because the change in
pulse width reverses, this is called the point of return of the power supply. The Ie supply
voltage V6 is directly proportional to the secondary voltage, so it breaks down according
to the overload control response. II V6 lalls below the value V6rnin , the Ie will go into sampling
operation. The time constant of the halfwave start-up is relatively large, so the short-circuit
power remains small. The overload amplifier reduces to the pulse width tpsh ' This pulse
width must remain possible so that the Ie can start without any problems from the virtual
short-circuit, i.e. the turn-on with V1 = O.
If the load is reduced on the secondary side, the charge pulses (Vs = H) become narrower.
The frequency increases up to the natural frequency of the system. If the load is reduced
further, the secondary voltages build up to V6 • At V6 = V6rnax the logic is blocked. The Ie goes
into sampling operation. Thus the circuit is absolutely open-circuit-proof.
3. Overtemperature response
An integrated temperature cutout blocks the logic if the chip temperature becomes inadmissibly
high. The Ie automatically samples the temperature and starts as soon as it drops to an
admissible level.
619
TDA4605
Maximum ratings
min
max
V1
V2
V3
Vs
V6
V7
Vs
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
3
11
12
13
14
Is
16
-3
-3
-3
-1.5
-1.5
-0.Q1
-3
-3
1
3
3
Remarks
Voltages
Pin
Pin
Pin
Pin
Pin
Pin
Pin
1
2
3
5
6
7
8
V6
20
V
V
V
V
V
V
V
Supply voltage
Currents
Pin 1
Pin 2
Pin 3
Pin4
Pin 5
Pin 6
Pin 7
Pin 8
Junction temperature
Storage temperature range
Ir
Is
1j
Totg
-40
1.5
1.5
1
3
mA
mA
mA
A
A
A
mA
mA
125
125
°C
°C
100
70
K/W
K/W
15
85
V
°C
Thermal resistances
junction-air
junction-case
measured at pin 4
RthJA
RthJC
Operating range
Supply voltage
Case temperature
620
V6
Tc
7.5
-20
tp~50 ~s;v ~0.5
tp5:50
tp5:50
~s;v
~s;v
5:0.5
5:0.5
TDA4605
Characteristics
Measuremen
circuit
typ
max
0.5
0.75
rnA
1
12
6.5
1.5
13
7
rnA
V
V
IsE
12
16
rnA
IsA
10
TA =25°C
min
Start-up hysteresis
Start-up current consumption
Vs=5V
Start-up current consumption
Vs=8 V
Turn-on voltage
Turn-off voltage
Turn-on current
Vs = VBE
Turn-off current
VB = VBA
Voltage limiter
(VB = 10 V, IC turned off)
at pin 2 (VB < VB E)
12 = 1 rnA
at pin 3 (VB < VsE)
13 = 1 rnA
I S/5
Isla
VSE
11
6
VBA
rnA
V4max
5.6
6.6
7.6
V
Vsmax
5.6
6.6
7.6
V
Control range
Control input voltage
Gain in control range
d (V2S - V2B )
G cont =
G cont
2
2
V2B
2
V2 S max
2
3
V
Vw
V1L
400
150
2
mV
mV
Gover
2
2
2
V1
2
360
mV
11
2
-140
flA
V20ver
2
3.0
V
V2sh
2
2.7
V
tp over
2
8.5
flS
tp sh
2
7.5
fls
Is
2
12
rnA
Is
2
10
rnA
V1cont
400
-400
mV
dV1
Primary-current simulation voltage
Basic value
Maximum peak value
G1 = V1eont (2 V/Veont)
V
Overload and short-circuit operation
Overload range upper limit
Overload range lower limit
Gain in overload range
d(V2s - V2B)
Gover =
dV1
Input voltage in overload range
Veont = 3.5 V
Input current in short-circuit operation
Veont =0 V
Peak value in overload range
Veent =3.5 V
Peak value in short-circuit operation
Veent =0 V
Output pulse width in overload range
Veent =3.5 V
Output pulse width in short-circuit operation
Veent =0 V
Current consumption in overload range
Veent =3.5 V
Current consumption in short-circuit
operation
Veent =0 V
621
TDA4605
Characteristics
TA =25°C
Measurement
circuit
min
typ
max
Generally valid data
(Vs = 10 V)
Point-ol-return correction
Point-ol-return
correction voltage
V3'=5V; V2'=OV
Point-ol-return
correction current
V3' =5 V; V2' =0 V
V7
2
14
5
V
-460
IlA
0.7
-0.2
2
V
V
Il s
Zero-passage detector voltage
Positive value
Negative value
Delay between Vs and V2
VSP
VSN
td4
2
2
2
Output-stage data
Saturation voltages
S in setting 1
of upper transistor
Is =-1.5 A
Vsatu
2
V
01 lower transistor
15 =+1.5 A
VsatL
2
V
Slew rate of output voltage
Rising edge
Vcont =3.5 V
+dV5 /dt
2
10
V/lls
Falling edge
Vcont =3.5 V
-dV5 /dt
2
50
V/lls
622
~
....
TDA4605
Characteristics
TA =25°C
Measurement
circuit
min
typ
2
0.3
0.5
14
15
max
Protective circuits
1. Undervoltage protection
for Vs:
voltage on pin 5 = V5min
when Vs < VSmin
(with Vsmin = VSA + LlVs)
LlVs
2. Overvoltage protection
for Vs:
voltage on pin 5 = V5min
when Vs < VSmax
3. Undervoltage protection
for Vline:
voltage on pin 5 = V5min
when V3> V3A
V2 ' =0 V
V3A
4. Overtemperature:
chip temperature at which
IC switches V5 to V5min
1j
Voltage on pin 3 after response
of protective function
(V3 is clamped until Vs < VsA )
13 =3 mA
V3
0.2
Sampling current consumption
V3 = V2 =0 V
Is
12
VSmax
V
16
V
V
2
°C
125
0.4
V
mA
623
TDA4605
Characteristics
Measurement
circuit
min
typ
max
Normal operation
(lIi'n. -220 V; S1, S2, S3, S4 closed)
1. Secondary voltage
2. Secondary voltage
3. Secondary voltage
4. Secondary voltage
V,s
V2S
V3S
V4S
3
3
3
3
95
26
15
8.5
V
V
V
V
Turn-on time for
secondary voltages
ton
3
120
ms
Voltage alteration
between S5 open and S5 closed
AV,s
3
100
500
mV
Load variation cross-talk
Voltage alteration
between S6 open and S6 closed
AV,s
3
500
1000
mV
AV,s
3
3
3
20
80
10
30
f
Ppr1m
V
kHz
VA
l,smax
3
Al,5max
3
Standby operation
(lIi'n. = 220 V; p.ee :;;; 2 W)
Voltage build-up
Frequency
Power consumption
Point-of-return stability
Max. secondary current
(secondary pOint of return)
S1 closed l,smax is set with R17
V,s=85V
Relative alteration of I, Smax
80 V< lIi'ne<140 V
75
A
1.85
±10
/
624
15
%
TDA4605
Block diagram
2
4
Vcont
625
TDA4605
Pin description
Pin
Designation
Function
1
Control voltage
Information input for secondary voltage. By comparison of the control voltage derived from the control
winding of the transformer with the internal reference
voltage the output pulse width at pin 5 is matched
to the load on the secondary side (normal, overload,
short-circuit, open-circuit).
2
Primary-current
simulation
Information input for primary voltage. The primarycurrent rise in the primary winding is simulated as a
voltage rise at pin 2 by means of an external RC network. When a value derived from the control voltage
at pin 1 is reached, the output pulse at pin 5 is
terminated. The maximum power in the point of return
is set with the RC network.
3
Undervoltage detector
Input for primary-voltage monitoring. The IC is cut
out upon line undervoltage by comparison with an
internal reference. The voltage at pin 3 is used for
point-of-return correction.
4
Ground
5
Output
Push-pull C output supplies ± 1.5 A for fast charge
reversal of the gate capacitances of the power MOS
transistor.
6
Supply voltage
Input for the supply voltage. From this a stable internal
reference VREF and the switching thresholds VaA , VaE,
Vamax and Vamin for monitoring of the operating voltage
are derived. VREF is turned on for Va < VaE and turned
off for V6 < VaA •
The logic is only enabled for Vamin < Va < Vamax .
7
Point-of-return
correction
Input for point-of-return correction. The network on
this pin to ground influences internal correction
(slope and response).
8
Zero-passage
detector
Input for oscillator feedback. After build-up each zero
passage of the feedback voltage (falling edge) triggers
an output pulse at pin 5. The trigger threshold is
typo +50 mV.
626
TDA4605
Measurement circuit 1
TDA 4605
4
S'
~r
Vcont
91011
Vsatu = V6 - V5
Vsatl = V5
,---~------------------------~~----~~+~
20kll
10kll
1kll
10011 ~-+----=,
TDA 4605
10 kll
3
6
4
5
10 nF
H
627
(J)
I\)
(Xl
I
F1
a
R::B
2,SA
Vline = 80 to
140 Vac
1
4~
• C1750
I
:!:
::
III
["[211~.7nF
T
7
Tr 1 similar to
AZV2100
III
c:
;
V1 sec
:
I1~2~~N~~~
D7
_ _~
TBYVI
258
3
I, -.
...::s
(1)
(')
~r
['0
-11270 pF
c:
::;:
to)
V2sec
D8
:
13
•
T (;»I
["
11
-11270 pF
•
---i*-
~
100Q
[8
~6j7~
I
f5
R"
D
10kll
[,
14nF
~_ ['5
I
470llF
I
I "."
i
["
~I
D10
12
BY 258
[13
Discharge C3
before IC Cha nge
Line solation
R"
24Q
30W
'C
"2-
2,5A
\IIine -80 to
140 Vac
lAir r r
I
------
7
III
III
-%V
Vsec1 -nom. 800 mA
33kn
R Isec 1 _ max. 1100 mA
'5
07
BY 258
0
2
Tr 1 similar to
AZV 2100
13
o·
::::I
o
~.
c
;:;:
270 pF
I
03
[
I
I
I
I
I
I
4
110
08
1>1
0
BY 258
Vsec2 -26 V
Isec2 - nom. 100 mA
-
max. 1200 mA
[,
100 ~F
11
04
R13
100n
>l
f
Vsec3 -15 V
nom. 1000 mA
0 Isec 3 -
[8
8,2 nF
[9
14nF
Discharge C 3
before IC Change
~
~
(J)
'"co
en
o
U1
TDA4605
Diagram
IJ
1\
Start
-t
.... ..,,,
~
x
~
h
,,
\
"""'---1\
_t
Stop
s
I
"
---,--,
,
I
I
I
,
1
I
-t
10
... 1
t
1'''' •
V
V . . . ·•
I
•
•
I
I
I•
-t
\
~
-t
630
TDA4605
Diagram
I
Magnified Extract
for TimeL! t
iVa
ifv -+---,.............,
a
VSmin -+----I--.!1
VSA -l--+---+--i------JI
I
I
I
I
I
i
i V8N-I--I--------l~
_ti
-t
V2
!t
~smax~r__H~~~~~-~-+__+~~
V28 -I---+-------l-
-t
631
TDA4605
1. Start-up hysteresis
16/B+-----t---=..,...~
16/s+--~-~
2. Operation in measurement circuit 2
1V
10
-1V
r
20
30
40
SOilS
'"""""----....I_t
VBP
+-+---------+---------+----t
Vz
tI VZsmaxi=========~===;;;;o>J
VZK
V2Bt:======+~_~++==-
-t
dVs
\
+dT=
\
t
\ _ d Vs _ VSmax • VSmin
\
\
\
dt·
Vs min::t=======::f::::l=~=l:=====
-t
632
VSmax-VSmin
tf
TDA4605
Efficiency 1] versus
secondary power P 1 S
Frequency f versus secondary
powerP,S
kHz
100
Vac =140 V
f
I
\.\
60
-
I
80 '.
\\
\ ","
I\,. " ./
60
I
Vac =140 V -
40
Vac=80 V "
20
i'-.. " ....
"""
I
40
....
r......
Measurement Circuit
P2S =P 3S = P4S =0 W
1
1
100
50
,
-
20
Measurement Circuit3
P2S = P3S =P4S =OW
. I~
.1
50
200 W
150
100
150
-P,S
Peak collector current Ic max
of switching transistor
versus primary voltage ~ine
Secondary voltage V, S versus
secondary current I 1S
V
120
V,s
t
100
80
200 W
- P,S
A
10
'"
I
Vac =140 V_
"-
1\\
Vac=11~
............
60
4
40
20
Measurement Circuit 3
P2S = P3S = P4S =OW
1
0,8
1,2
0,4
Measurement Circuit
P2S =P3 s =P4S =0 W
V,S =1110 V 1
1
T
1,6
2,0 A
- V,S
80
100
120
140
160 V
- - - - - Viine
633
634
TDA4814
IC for Sinusoidal Line-Current Consumption
DIP 14
This device contains the components for designing a switched-mode power supply with
sinusoidal line-current consumption. Sinusoidal line current is drawn from the supply
network in particular when there is high power consumption. One possible application is
in electronic ballasts for fluorescent lamps, especially when a large number of these lamps
are concentrated on one supply point. This IC is additionally suitable for general driving of
switched-mode power supplies. The possibility of regulating the output voltage will enable
operation on different line voltages (110 Vac/220 Vac) without any switchover.
A monitoring circuit makes it possible to control various turn-on and turn-off functions of
different units of equipment.
Pin configuration
Pin description
(top view)
Pin
°s
14 IDET
QD
13
Q
OpAmpllM2
Vs
3
12 -I Dp Amp
- 1 CDMP
4
11 1 M1
10 1 STOP
+1 op Amp/VREF
1 START
NL
6
9
Q
STOP
Q
START
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Function
Ground Os
Driver output QD
Supply voltage Vs
Negative comparator
input -I COMP
Positive input Op Amp/VREF
Start input I START
N.C.
Start output Q START
Stop output Q STOP
Stop input I STOP
Multiplier input M1 IM1
Negative input Op Amp
Op Amp output/multiplier
input M2 Q Op Ampll M2
Detector input I DET
635
TDA4814
Circuit description
The IC switches from standby to full current consumption when the turn-on threshold on
Vs is exceeded. Turn-off is controlied by hysteresis. The integrated Z diode limits the
voltage on Vs when impressed current is fed.
The operational amplifier (op amp) can be wired as a control amplifier. It will then compare
the divided output voltage VQ to a reference voltage VREF that is stable with temperature.
The output voltage of the op amp that is produced in this way is multiplied by a sinemagnitude voltage in the multiplier (M). At the output of the latter a sine-magnitude voltage
then appears that is variable in amplitude. This nominal voltage is applied to the plus input
of the comparator. The nominal voltage at the multiplier output can then be compared via
the comparator to a voltage derived from the actual line current. The output of the
comparator feeds the reference signal via a logic circuit to the driver that switches the
SIPMOS transistor. No current gaps may appear in the choke, otherwise the line current
would no longer be sinusoidal. To achieve that, the detector input I DET senses when the
choke current has fallen to zero after turn-off of the SIPrv".)S transistor. This ensures that
the SIPMOS transistor does not turn on too early and that no current gaps occur.
When the detector input I DET is on High potential, the SIPMOS driver output QD is blocked.
At the same time the flipflop can be set by the comparator.
When I DET is Low, the Q output is enabled and can be disabled again by the comparator
by resetting the flipflop.
Consequently the choke is always currentless when the SIPMOS transistor turns on and no
current gaps appear in the choke.
Driver output QD for SIPMOS transistors
The output driver is designed as a push-pull stage. There is a resistor of 10 Q in series with
the output for the purpose of current limiting. Between Q and ground there is a resistor of
10 kQ. This keeps the SIPMOS transistor reliably turned off during standby.
The Q output is additionally connected to the supply voltage Vs and to ground by way of
diodes.
When the supply voltage to the switched-mode power supply is turned on, the diode
towards Vs conducts the capacitive displacement currents from the gate of the SIPMOS
transistor into the smooting capacitor on Vs. The voltage Vs may not exceed 0.7 V if the
SIPMOS transistor is to remain turned off.
The diode towards ground clamps negative voltages on Q to -0.7 V. Capacitive currents
produced by voltage incursion on the drain of the SIPMOS transistor are thus able to flow
away unhindered.
Reference voltage (VREF)
The reference-voltage source is highly stable with temperature. It can be used if additional,
external components are wired.
636
TDA4814
Monitoring circuit (I START, 1STOP, Q START, Q STOP)
The monitoring circuit guarantees the secure operation of a unit of equipment. Any
circuitry that is shut down because of a fault, for instance, cannot be started up again until
the monitoring start (I START/Q START) has turned on and a positive voltage pulse has
been impressed on Q START.
If there is a defect present, the monitoring stop (I STOP/Q STOP) will turn on and shut
down either the entire unit or simply the circuitry that has to be protected. No restart is
then possible until the hold current impressed on 1 START or I STOP has been interrupted
(e.g. by a power-down).
637
TDA4814
Maximum ratings
Supply voltage
Vs
Notes
Lower
limitS
Upper
limit A
Vz == Z voltage
-0.3
Vz
V
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
0
-0.3
-10
33
33
6
6
33
6
300
Vs
10
V
V
V
V
V
V
mA
V
mA
-0.3
-0.3
-10
-0.3
0.9
-10
25
33
3
6
6
10
V
V
V
V
V
mA
Inputs
Comparator
OpAmp
Multiplier
Output Op Amp
Z current Vs GND
Driver output
Q clamping diodes
Input
START
STOP
Output START
STOP
Detector input
Detector clamping diodes
VICOMP
V-ICOMP
VIOPAmp
V-IOPAmp
VM1
VQOp Ampl 1M2
1z
VQ
1QO
VI START
VI STOP
VOSTART
VOSTOP
VIDET
1IDET
Observe Pmax
VQ> Vs or
Vo<-0.3 V
see characteristics
see characteristics
VIDET > 6 Vor
VIDET <0.9 V
Capacitance at I START
to ground
CI START
150
flF
Junction temperature
Storage temperature
1j
Tstg
125
125
DC
DC
Thermal resistance
system-air
RthSA
65
KlW
VSON
Vz
V
0
-300
-25
200
300
85
mA
mA
DC
-55
Operating range
Supply voltage
Vs
Z current
Driver current
Operating temperature
100
638
lz
TA
Values for Vs ON, Vz:
see characteristics
Observe Pmax
TDA4814
Characteristics (VS ON * < Vs
< Vz ; -25 DC < TA < +85 DC)
typ
Lower
limit B
Upper
limit A
Current consumption
Without load on driver Q
and VREF ; Q Low
o V 6 V or VOET <0.9 V
1.3
VOETH
VOETL
VShy
- IOET
0.9S
SO
IOET
-3
1.6
V
300
V
mV
Il A
3
mA
S
For explanations refer to page 642.
641
TDA4814
Characteristics (Vs ON * < Vs < Vz ; -25°C < TA < +85 DC)
Lower
limit B
typ
Upper
limit A
200
500
Delay times
Input comparator
-+ Q21
ns
1) Calculation of the output voltage VOM : VOM = C . VM1 1) • VM2 2) in V.
The voltages VM1 11 and VM2 2) are referred to the particular reference level.
2) Step functions at comparator input
..1VCOMP
=-100 mV ~..1VCOMP =+100 mV.
3) The turn-on voltage of I sTOP exceeds the turn-on voltage of
*)
ISTART
by at least 3 V.
VSON means that VSH has been exceeded but that the voltage is still greater than VSL .
642
TDA4814
Use and advantages of Ie TDA 4814 in
SM~S
and electronic ballasts
1 Switched mode power supplies
The "active harmonics filter" consists of a rectifier arrangement in a bridge circuit followed
by an up-converter. Through a controller action it is possible to draw a virtually sinusoidal
current from the single-phase line and produce a regulated dc voltage at the output.
In the case of an SMPS with conventional line rectification it is possible to achieve a power
factor (ratio of active power to apparent power) of 0.5 to 0.7. The active harmonics filter
serves for improving the power factor, which reaches a value of almost 1, and for reducing
the load on the line produced by harmonics. The losses caused by the active harmonics
filter are more than compensated by the fact that a subsequent converter can constantly
be operated at an optimal operating point because of the input control of the operating
voltage.
The extra effort that is necessary, compared to an SMPS without an active harmonics filter,
is made good upwards of about 500 W by savings elsewhere (e.g. smaller smoothing
capacitance and transistors of a higher resistance in the SMPS). With the wide-ranging
power supplies that are in increasing demand, i.e. power supplies that can work on a line of
90 through 240 Vac without any sfwitching changes, the power pay-off limit reduces
markedly.
2 Electronic ballasts for fluorescent lamps
The VDE and the EVUs require of industrial consumers that they take "sinusoidal current"
from the line, i.e. exhibit a purely ohmic response. This is the case with incandescent
lamps, cooker rings and heating fixtures.
In all electronic devices with rectification and a CR load the current drain is pulsed, i.e.
afflicted by a large harmonic content and impermissible according to VDE. The reflected
current ripple can interfere with installations for AF power-line carrier control for instance,
i.e. lead to faulty switching. The harmonic content of the current consequently may not
exceed certain values.
The line current for a ballast operating with a stable fluorescent lamp must be such that the
share of harmonics in relation to the fundamental does not exceed the values given in
table 1.
643
TDA4814
Table 1
Line-current harmonic; content in acc. with VOE 0712, part 2
Harmonics
3rd harmonic
5th harmonic
7th harmonic
9th harmonic
11 th harmonic
13th harmonic
and higher
Permissible
harmonic content1)
In%
).
25x0.9
7
4
3
2
1) ). is the power factor
The values given here are achieved using the TDA 4814 to drive a SIPMOS in an upconverter regulating circuit.
644
TDA4814
Application example
Electronic ballast
~--~--~--~------------~+---~~
~
*
1
>
0
N
.
::;
>
~
->
0
:z
'"
0
c
~
Remark
Kindly note that the SIEMENS AG holds patents on electronic ballasts for fluorescent lamps,
published in "Siemens Energy and Automation", Vol. II, No.2, March/April 1985
645
646
Ie for Push-Pull Switched-Mode Power Supplies
with SIPMOS Driver Output
TDA4918 A
DIP 20
Preliminary data
This versatile switched-mode power supply control Ie for the control of SIPMOS power
transistors comprises digital and analog functions. These functions are required in the
design of high quality flyback and forward converters in single-phase and push-pull
operation in normal, half-bridge and full bridge circuits. The component can also be used
for single-ended voltage multipliers and speed-controlled motors. Malfunctions in the
electrical operation of the switched-mode power supply are recognized by the comparators in the SMPS Ie and activate protective functions.
Pin configuration
(top view)
20 GND a v
GND Q SIP
SIP 1
2
19 QOpAmp/IK 1
2
3
18 I OpAmp H
Vs Q SIP
4
17 10pAmp
Vs
5
16
start
6
15 +1 DYN
Q
Q SIP
Csoft
14
[T
-IDYNKS
KS
RR
RT
8
13 I uv K 4
[R
9
12 I ov K 3
1St 10
11
(+)
VREF
647
TDA4918 A
Pin names.
Pin no.
Function
1
2
GND Q SIP
Output SIPMOS driver Q SIP 1
3
Output SIPMOS driver Q SIP 2
4
5
Supply voltage VSQSIP
Supply voltage Vs
6
Soft start Csoft start
7
8
veo CT
veo RT
9
Ramp generator CR
10
Input standby 1St
11
12
Input overvoltage K 3
13
Input undervoltage K 4
14
15
16
17
Ramp generator RR
Input dynamic current limitation K 5 (+)
18
19
Input operational amplifier (-)
Output operational amplifier Q OpAmp/1 eOMP K 1
20
GND 0 V
648
Reference voltage VREF
Input dynamic current limitation K 5 (-)
Input operational amplifier (+)
TDA4918 A
Circuit description
The various functional units of the component and their interaction are described in the
following.
Supply voltage Vs
The IC enables the two outputs not before the turn-on threshold (VSON ) at Vs is exceeded.
The duty cycle (active time/disable time) at the enabled outputs can then rise from zero to
the value set with K 1 in the time specified by the soft start.
An undervoltage at the standby input causes the current consumption Is to remain at the
very low standby current level independent of the voltage Vs.
Voltage controlled oscillator (VCO)
The VCO is connected with the capacitor CT and the resistor RT • The charge current at CT
flows continuously and is set with resistor RT• The discharge current is active during the
discharge of CT and is set internally.
In the typical mode of operation the duration of the rising edge is considerably greater
than that of the falling edge. During the falling edge the VCO passes a trigger signal to the
ramp generator thus discharging the ramp generator capacitance. Additionally, the
trigger signal is routed to other parts of the IC.
Ramp generator
The ramp generator is controlled by the VCO and operates at the same frequency as the
VCO. The duration of the ramp generator falling edge must be shorter than the VCO fall
time. Only then do the ramp generator upper and lower switching levels reach their rated
values.
To control the pulse width at the output, the voltage of the ramp generator rising edge is
compared with an externally adjustable dc voltage at comparator K 1. The slope of the
rising edge is adjusted via the current by means of RR' This provides the possibility of an
additional superimposed control of the output duty cycle. This control capability (feedforward control) permits the compensation of known interference (e.g. input voltage
ripple). A superimposed load current control (current mode control) however, can also
be implemented.
Push-pull flipflop
The push-pull flipflop is switched by the falling edge of the VCO. This ensures that only
one output of the two push-pull outputs is enabled at a time.
Comparator K1 (duty cycle control)
The two plus inputs of the comparator are switched such that the lower plus level is always
compared with the level of the minus input. As soon as the voltage of the rising sawtooth
edge (minus input) exceeds the lower level of the two plus inputs, the currently active
output is disabled via the turn-off flipflop. The "high"-duration of the respectively active
output can thus be infinitely varied. As the frequency remains constant, this process
corresponds to a change in duty cycle.
649
TDA 4918 A
Operational amplifier (op amp)
The op amp is a high quality operational amplifier. It can be used in the control circuit to
transmit the amplified variations of the voltage to be regulated to the free plus input of
comparator K 1. A voltage change is thus converted to a duty cycle change.
Turn-off flipflop
The falling edge of the veo causesa pulse attheturn-offflipflop set input. It can, however,
only be actually set if no reset signal is pending. With the turn-off flipflop set, the two outputs are enabled and one of them can be active. Upon an error signal from K 5 or upon a
turn-off signal from K 1 the flipflop disables the outputs.
Z diode
The Z diode limits the voltage at capacitor Csottstart to a maximum of 5 V. The ramp generator voltage can reach 5.5 V. For an appropriate slope of the rising ramp generator edge, the
duty cycle can be limited to a desired maximum value. This can be a possible advantage in
flyback converter operation.
Comparator K2
The comparator has its switching threshold at 1.5 Vat the plus input, and with its output
sets the error flipflop if the voltage at capacitor C solt start is below 1.5 V. The error flipflop,
however, will only accept the set pulse if no reset pulse (error) is pending. This prevents a
restart of the outputs as long as an error signal is pending.
Soft start
The lower of the two voltages at the K1 plus inputs - compared with the ramp generator
voltage - is a measure for the duty cycle at the output. At component turn-on, the voltage
at capacitor Csoltstart is equal to 0 V. As long as no error exists, the capacitor will be charged
to the maximum value of 5 V with a current of 6 iJA.
In the case of an error, CSOf! start is discharged with a current of 2 iJA. The currently active
output, however, is immediately disabled by the error flipflop. Below a charge voltage of
1.5 V, a set signal is pending at the error flipflop and the outputs are enabled if no reset
signal is pending at the same time. As the minimum ramp generator voltage, however, is
1.8 V, the duty cycle atthe outputs is actually only increased slowly and continuously after
the voltage at C solt start exceeds 1.8 V.
Error flipflop
Error signals, routed to the error flipflop reset input, cause an immediate disabling of the
output (low), and after elimination of the error, a restart of the component by soft start.
Comparators K3 (overvoltage). VREF overcurrent. Vs undervoltage
These are error detectors that on error, cause the error flipflop to immediately disable the
outputs. After elimination of the error, the duty cycle is raised again using the soft start.
Upon overvoltage. a current is impressedat the input of K 3, that can be used to enable an
adjustable hysteresis or a holding function.
650
TDA4918 A
Comparator K4 (undervoltage)
Comparator K4 switches with an adjustable hysteresis. The value of the hysteresis is
derived from the internal resistance of the external control source and the current
impressed internally at the input of K 4. In theundervoltage case, the set current flows into
the component in the technical direction of current flow.
In the error case (undervoltage). both outputs are disabled. The component restarts by soft
start.
Comparator K5 (dynamic current limiter)
K 5 serves to recognize overcurrents at the switching transistors. Both inputs of the
comparator are externally accessible. After elimination of the error, the outputs are
enabled with the VCO trigger pulse at the turn-off flipflop. The delay time between
occurrence of an error and disabling of the outputs is only approximately 250 ns.
Standby input (I St)
This input switches with voltage and current hysteresis. The voltage levels for switching
from standby to active operation can be set with an external voltage divider between Vs
- standby input - ground.
Reference voltage (VREF )
The reference voltage source is a highly constant source with regard to its temperature
behavior. It can be used for the external wiring of the op amp; the error comparators, the
ramp generator, or other external components.
SIPMOS driver output (QSIP)
The two outputs operate in the push-pull mode. They are active high. The duration during
which one of the outputs is active, can be varied infinitely. The duration of the falling edge
at the frequency generator is equal to the minimum duration during which both outputs
are simultaneously low.
The output driver is designed as a push-pull stage. The output current is internally limited
to the specified values.
A 10 kQ resistor is connected between the output and ground. This resistor holds the
SIPMOS transistor reliably disabled during standby operation (undervoltage at I St.)
Output QSIP is connected with the supply voltage
VSQSIP
and with ground via diodes.
The diode connected to VSQSIP routes the capacitive shift currents from the SIPMOS
transistor gate to the filter capacitor at VSQSIP during turning on the SMPS supply voltage.
The voltage at VSQSIP can reach approximately 2.3 V without the SIPMOS transistor being
turned on.
The diode connected to ground connects negative voltages at QSIP to -0.7 V. This
provides an unimpeded flow off of capacitive currents occurring during voltage breakdown at the SIPMOS transistor drain connection.
For supply voltages starting at approx. 2 V, both outputs are active low in the disabled
state. The function of the diode connected to VSQSIP is then taken over by the pull-down
source.
651
TDA4918 A
Maximum ratings
Lower
limit B
Upper
limit A
Vs
-0.3
33
V
VCT' VRT
leT
-0.3
6
3
V
mA
Voltage at CRIRR
VCR' VRR
-0.3
6
V
6
6
V
Vs
10
V
6
125
125
63
Supply voltage
Inputs K1, OpAmp, K3, K4, K5, 1St
Frequency generato'r (VeO)
Voltage at RTf CT
VCT > 6 V
Ramp generator
Reference voltage
V REF
Output Op Amp
Vaopamp
Driver output QSIP1)
Va SIP
QSIP clamp diodes at QSIP
VasIP > Vs or VaslP < -0.3 V
Soft start
I aslP
-0.3
-0.3
-0.3
-10
Vc soft sta rt
-0.3
Junction temperature 2 )
7j
Storage temperature
T stg
Thermal resistance (system-air)
RthSA
-65
V
mA
V
°e
°e
KfW
Operating range
Supply voltage 3 )
Vs
VSON
Driver current at QSIP 1, 2
IaslP
-1000
Frequency generator (VeO)
Ramp generator
fveo
fR
Ambient temperature
TA
-40
30
+300
300
300
85
1) With this, the max. power dissipation or junction temperature must be taken into account!
') At a planned max. operating time of 70 000 hours a continuous max. junction temperature of 150°C is
permitted.
3) For Vs ON values refer to characteristic data.
652
V
mA
kHz
kHz
°e
TDA4918 A
Characteristics
V SON ') < Vs < 30 V; TA = -40 to + 85°e
Test conditions
Current consumption
without load at V REF
QOP, QSIP 1. 2
Is
Standby operation
1st
Hysteresis at Vs
Turn-on threshold for
Vs rising
Turn-off threshold for
Vs falling
VSH
Reference voltage
Voltage
Load current
Voltage change
Voltage change
Temperature response
Reponse threshold for
I REF overcurrent
Short-circuit current
V REF
8_3
Von-THR;::: Von-THR H
tJ.VREF
= 1 mA
TA = 25°e
Vs = 15 V
IREF
2.475
2.5
0
Vs ± 20%
IREF ± 20%
-0.3
tJ.VREF/tJ.T
20
mA
2
mA
9.6
V
V REF
= 0 V
Vs ± 20%
CT = 0.2 nF
RT = 50 kQ
TA = 25°e
V
2.525
V
3
10
mA
mV
5
+0.3
mV
7
10
lov
Isc
Upper
limit A
7.6
-/REF
tJ.VREF
typ
CT = 1 nF
frequency
generator with
100 kHz
V SL
Frequency generator (VeO)
Frequency range
fvco
Frequency change
tJ.f/fo
Tolerance
tJ.f/fo
I)
Lower
limit B
-5
mV/K
mA
mA
300
kHz
+5
%
%
v. ON means that V. HIGH has been exceeded, while V. LOW has not yet been exceeded.
653
TDA4918 A
Characteristics
VSON < Vs < 30 V; TA = -40 to
+ 85°C
Test conditions
Lower
limit B
0
Charging current for
CT (perm.)
= current at pin RT
IRT
I RT =
Discharging current for CT
I dch
internally fixed
1)
CT range
Upper switching threshold
Lower switching threshold
VREF/RT
2.1
typ
Upper
limit A
3
3.9
mA
0.2
1000
5
2
Vu
III
mA
nF
V
V
Ramp generator
Frequency range
fR
Maximum voltage at CR
V CRH
Minimum voltage at CR
VCRl
Charging current for CR
(perm) = current at pin RR
Ich
Discharging current for CR
I dch
Ratio I RPI I CR
charge
Comparator K 1
Input current
11K!
Turn-off delay time 2 )
(signal transit time input K 1
to QSIP)
Common-mode input
voltage range
VIC
1)
300
5.5
1.7
V RR approx.
0.7 V
0
internally fixed
2.8
IRR
= 0.5 mA
0.95
0
1.8
4
kHz
V
1.9
V
3
mA
5.2
mA
1.05
2
IJA
500
ns
5.5
V
CT = 0.2 nF corresponds to a fall time of 0.2 ~s (± 30%) if the discharge current largely exceeds the charge current.
The fall time equals the minimum dead time at the output.
= -100 mV....r+ II V = + 100 mV. for transit time from input comparator to Q SIP
2) Step function II V
654
TDA4918 A
Characteristics
V SON < Vs < 30 V; TA = -40 to +85°C
Test conditions
Lower
limit B
typ
60
80
Pin 10 n.c.
-10
Upper
limit A
Operational amplifier
Open-loop voltage gain
Input offset voltage
Input current
Common-mode input
voltage range
Output current
Gvo
Vlo
-Ilopamp
dB
+10
mV
2
IJA
V
Vic
0
4
Ioopamp
0
2
rnA
0.5
5.5
V
o mAVSON
VQL
Output current
IOSI?
-l oslP
V
Vs-3
1.8
1.4
V
V
700
1000
mA
mA
6.3
6.9
7.5
V
5.6
6.2
6.8
V
25
5
32
IJA
IJA
Input standby 1St
Turn-on threshold for
VISt rising
Turn-off threshold for
Vistfalling
Hysteresis current
VIStH
VIStL
-IHvStH
[ HyStL
Vlst> VIStH
VISt < VIStL
18
1) Dynamic maximum current during rising of falling edge
') Step function VRE , = -100 mV -r+ VREF = +100 mV } for transit time from
t. V = -100 mV ___ t. V = + 100 mV
input comparator to QSIP
3) Step function
656
TDA4918 A
Pulse diagram
VCT V Voltage at CT
S
t /
\ / ~/ \ / ~~
0
Voltage alt CR
VCR
V
--"
V
l,B
0
VOT
t
t~
VI
v
C soft sta rt
lV
VIK2 (+)
lV
llL
Voltage at QSIP 1
V
1
0
Hi
I--
lI
I
-rn
Voltage at aSIP2 ~ax. Possible
Duty Cycle
r-I
at VI rated
V02 V
t
Vi rated>
.' '.'-'
VI >
f s,~
: ::
1
0
O,ST
V
I
1T
l,ST
Soft Start - Error - ON/OFF
VSsoft start
I
t-
z
S 0
Ol~+-~------~UU
o
1 2
__~~LL__~__
t_
657
Ol
tD
(J1
(»
0"
o
~
c..
V,OSIP
t , t I
1
2 aSIPl
ar
CO
a;
3
IK 1/aOp 19 Input Comparator K 1
Output
opamp
..,
_IOp-,-lBoq.:==--'-'17
• I OP
OpAmp'
- ·70pen
+ /"
Collector
~
I
I
outputOSIPZ:
active H L
~
1 I 13 a SIP 2
_________ -.J
Supply Voltage
1___
I
I
I
I
I
1 GNOOSIP
+ Vs
n" .. r .... rr .. n+
+Vs
Reference Voltage +VAEF
11 + VAEF
~__~I~n~pu~t~S~t~an~d~b-,-Y-,-(~IS~t~I____________~l,,-O 1St
1St =L - I H , I S I
I 10~F
=25 ~A
IHyISt
Soft Start
-6--Csoftu3n
T1~F
lov
Overvoltage
Undervoltage
~
13
luv
Dyn. Current
limitation
15
+/OYN
,
16
-IOYN
-I
C
l>
0l=Io
....
00
CD
»
TDA4919 G
S020L
Preliminary data
This versatile single-phase switched-mode power supply control Ie for the direct control
of SIPMOS power transistors comprises digital and analog functions. These functions are
required in the design of high quality flyback, forward, and choke converters with
switching frequencies up to 300 kHz. The Ie can also be used for single-ended voltage
multipliers and speed-controlled motors. Malfunctions in the electrical operation of the
switched-mode power supply are recognized by the comparators in the SMPS Ie and
activate protective fu nctions.
Pin configuration
(top view)
20 GND 0 v
GND Q SIP
N.C.
19
Q OpAmp/1 K 1
18 I OpAmp (-I
Q SIP
VSQSIP
4
17
10pAmp
Vs
5
16
-IOYN K5
start
6
15
+IOYNK5
[r
7
14
RR
Rr
8
13 I uv K 4
[R
9
12 I ov K 3
Csolt
1St 10
11
(+1
VREF
659
TDA4919 G
Pin names
Pin no.
Function
GND QSIP
2
N.C.
3
SIPMOS driver Q SIP
4
Supply voltage
VSQSIP
5
Supply voltage Vs
6
7
Soft start Csoft start
VCO CT
8
9
10
11
12
VCO RT
Ramp generator CR
Input standby 1St
Reference voltage VREF
Input overvoltage K 3
13
Input undervoltage K 4
14
15
Ramp generator RR
Input dynamic current limitation (+) K 5
16
17
Input dynamic current limitation (-) K 5
Input operational amplifier (+)
18
Input operational amplifier (-)
19
Output operational amplifier/input comparator K 1
20
GND 0 V
660
TDA4919 G
Circuit description
The various functional units of the component and their interaction are described in the
following.
Supply voltage Vs
The Ie enables the output not before the turn-on threshold (VSON ) at Vs is exceeded. The
duty cycle (active time/disable time) at the output can then rise from zero to the value set
with K 1 in the time specified by the soft start.
An undervoltage at the standby input causes the current consumption Is to remain at the
very low standby current level independent of the voltage Vs.
Voltage controlled oscillator (VCO)
The veo is connected with the capacitor CT and the resistor RT • The charge current at CT
flows continuously and is set with resistor RT• The discharge current is active during the
discharge of CT and is set internally.
In the typical mode of operation the duration of the rising edge is considerably greater
than that of the falling edge. During the falling edge the veo passes a trigger signal to the
ramp generator thus discharging the ramp generator capacitance. Additionally, the
trigger signal is routed to other parts of the Ie.
Ramp generator
The ramp generator is controlled by the veo and operates at the same frequency as the
veo. The duration of the ramp generator falling edge must be shorter than the veo fall
time. Only then do the ramp generator upper and lower switching levels reach their rated
values.
To control the pulse width at the output, the voltage of the ramp generator rising edge is
compared with an externally adjustable dc voltage at comparator K 1. The slope of the
rising edge is adjusted via the current by means of RR. This provides the possibility of an
additional superimposed control of the output duty cycle. This control capability (feedforward control) permits the compensation of known interference (e.g. input voltage
ripple). A superimposed load current control (current mode control) however, can also
be implemented.
Comparator K1 (duty cycle control)
The two plus inputs of the comparator are switched such that the lower plus level is always
compared with the level of the minus input. As soon as the voltage of the rising sawtooth
edge (minus input) exceeds the lower level of the two plus inputs, the output is disabled via
the turn-off flipflop. The "high"-duration of the output can thus be infinitely varied. As the
frequency remains constant, this process corresponds to a change in duty cycle.
Operational amplifier (Op Amp)
The op amp is a high quality operational amplifier. It can be used in the control circuit to
transmit the amplified variations of the voltage to be regulated to the free plus input of
comparator K 1. A voltage change is thus converted to a duty cycle change.
661
TDA4919 G
Turn-off flipflop
The falling edge of the veo causes a pulse at the turn-off flipflop set input. It can, however,
only be actually set if no reset signal is pending. With the turn-off flipflop set, the output is
enabled and can be active. Upon an error signal from K 5 or upon a turn-off signal from K 1
the flipflop disables the output.
Z diode
The Z diode limits the voltage at capacitor esollSlarl to a maximum of 5 V. The ramp generator voltage can reach 5.5 V. For an appropriate slope of the rising ramp generator edge, the
duty cycle can be limited to a desired maximum value. This can be a possible advantage in
flyback converter operation.
Comparator K2
The comparator has its switching threshold at 1.5 Vat the plus input, and with its output
sets the error flipflop if the voltage at capacitor e soft slarl is below 1.5 V. The error flipflop,
however, will only accept the set pulse if no reset pulse (error) is pending. This prevents a
restart of the output as long as an error signal is pending.
Soft start
The lower of the two voltages at the K 1 plus inputs - compared with the ramp generator
voltage - is a measure for the duty cycle at the output. At component turn-on, the voltage
at capacitor eSOllSlarl is equal to 0 V. As long as no error exists, the capacitor will be charged
to the maximum value of 5 V with a current of 6 JJA.
In the case of an error, esollstart is discharged with a current of 2 jJA. The output, however, is
immediately disabled by the error flipflop. Belowa charge voltage of 1.5 V, a set signal is
pending at the error flipflop and the output is enabled if no reset signal is pending at the
same time. As the minimum ramp generator voltage, however, is 1.8 V, the duty cycle at
the outputs is actually only increased slowly and continuously after the voltage at esoftstarl
exceeds 1.8 V.
Error flipflop
Error signals, routed to the error flipflop reset input, cause an immediate disabling of the
output (low), and after elimination of the error, a restart of the component by soft start.
Comparators K3 (overvoltage), VREF overcurrent, Vs undervoltage
These are error detectors that on error, cause the error flipflop to immediately disable the
output. After elimination of the error, the duty cycle is raised again using the soft start.
Upon overvoltage, a current is impressed at the inputs of K 3 and K4, that can be used to
enable an adjustable hysteresis or a holding function.
662
TDA4919 G
Comparator K4 (undervoltage)
Comparator K4 switches with an adjustable hysteresis. The value of the hysteresis is
derived from the internal resistance of the external control source and the current
impressed internally at the input of K 4. In the undervoltage case, the set currentflows into
the component in the technical direction of current flow.
In the error case (undervoltage). the output is disabled. The component restarts by soft
start.
Comparator K5 (dynamic current limiter)
K5 serves to recognize overcurrents at the switching transistor. Both inputs of the
comparator are externally accessible. After elimination of the error, the output is enabled
with the VCO trigger pulse at the turn-off flipflop. The delay time between occurrence of
an error and disabling of the output is only approximately 250 ns.
Standby input (I St)
This input switches with voltage and current hysteresis. The voltage levels for switching
from standby to active operation can be set with an external voltage divider between Vs standby input - ground.
Reference voltage (VREF)
The reference voltage source is a highly constant source with regard to its temperature
behavior. It can be used for the external wiring of the op amp; the error comparators, the
ramp generator, or other external components.
SIPMOS driver output (QSIP)
The output is active high. The duration during which the output is active, can be varied
infinitely. The duration of the falling edge at the frequency generator is equal to the
minimum duration during which the output is low (dead time).
The output driver is designed as a push-pull stage. The output current is internally limited
to the specified values.
A 10 kQ resistor is connected between the output and ground. This resistor holds the
SIPMOS transistor reliably disabled during standby operation (undervoltage at I St.)
Output QSIP is connected with the supply voltage
VSQSIP
and with ground via diodes.
The diode connected to VSQSIP routes the capacitive shift currents from the SIPMOS
transistor gate to the filter capacitor at VSQSIP during turning on the SMPS supply voltage.
The voltage at VSQSIP can reach approximately 2.3 V without the SIPMOS transistor being
turned on.
The diode connected to ground connects negative voltages at QSIP to -0.7 V. This
provides an unimpeded flow off of capacitive currents occurring during voltage breakdown at the SIPMOS transistor drain connection.
For supply voltages starting at approx. 2 V, the output is active low in the disabled state.
The function of the diode connected to VSQSIP is then taken over by the pull-down source.
663
TDA4919 G
Maximum ratings
Lower
limit B
Upper
limit A
Vs
-0.3
33
V
VCT' VRT
ICT
-0.3
6
3
V
mA
VCR'
-0.3
6
V
Supply voltage
Inputs K 1, Op Amp, K 3, K4, K 5, 1St
Frequency generator (VeO)
Voltage at RT/CT
VCT> 6 V
Ramp generator
Voltage at
CR/R R
V RR
Reference voltage
V REF
-0.3
6
V
Output Op Amp
VQapamp> 6 V
Driver output QSlpl)
VQapamp
-0.3
I Qapamp
6
2
V
mA
V QS1P
-0.3
Vs
V
QSIP clamp diodes at QSIP
V QS1P > Vs or V QS1P < -0.3 V
I QS1P
-10
10
mA
Soft start
Vc saft start
I C saft sta rt
-0.3
6
V
100
125
iJ A
°e
Vcsaftstart> 6 V
Junction temperature
7j
Storage temperature
T stg
Thermal resistance (system-air)
(SO-20 L)
RthSA
-65
125
°e
90
K/W
Operating range
Supply voltage 2 )
Driver current at QSIP
Take Pmax into account!
Frequency generator (VeO)
Vs
V SON
30
V
laslP
-1000
+300
mA
300
kHz
Ramp generator
fvco
fR
Ambient temperature
TA
-40
300
kHz
85
°e
1) With this, the max. power dissipation or junction temperature must be taken into account.
') For Vs ON values refer to characteristic data.
664
TDA4919 G
Characteristics
V SON ') < Vs < 30 V; TA
= -40
to + 85°C
Test conditions
Lower
limit B
typ
Upper
limit A
Current consumption
without load at VREF
QOP, QSIP
Is
Standby operation
Ist
CT = 1 nF
frequency
generator with
100 kHz
20
mA
2
mA
9.6
V
Hysteresis at Vs
Turn-on threshold for
Vs rising
VSH
Turn-off threshold for
Vs falling
VSL
8.3
Von-THR;:::: Von-THR H
7.6
V
Reference voltage
Voltage
VREF
TA
Vs
Load current
Voltage change
-IREF
ll.VREF
Voltage change
ll. VREF
Temperature response
ll.VREF/ll.T
= 1 mA
= 25°C
= 15 V
IREF
2.475
2.5
0
Vs ± 20%
lREF
±
20%
-0.3
2.525
V
3
mA
10
mV
5
mV
+0.3
mV/K
Reponse threshold for
I REF overcurrent
Iov
Short-circuit current
Ise
1) V SON
means that
VSHIGH
VREF
has been exceeded, while
=0
V SLOW
V
7
mA
10
mA
has not yet been exceeded.
665
TDA4919 G
Characteristics
V SON < Vs < 30 V; TA
= -40
to + 85°C
Test conditions
Lower
limit B
typ
Upper
limit A
Frequency generator (VCO)
Frequency range
300
Frequency change
fvco
Mlfo
Tolerance
Mlfo
CT = 0.2 nF
RT = 50 kG
TA = 25°C
-5
Charging current for
CT (perm.)
= current at pin RT
IRT
I dch
I RT = VREF/RT
internally fixed
0
Discharging current for CT
I)
0.2
CT range
Upper switching threshold
Lower switching threshold
Vs ± 20%
kHz
%
2.1
+5
mA
3
3.9
1000
5
2
Vu
~
%
mA
nF
V
V
Ramp generator
Frequency range
fR
Maximum voltage at CR
V CRH
Minimum voltage at CR
V CRl
Charging current for CR
(perm) = current at pin RR
I ch
Discharging current for CR
Ratio I RRI IcR
I dch
300
5.5
1.7
V RR approx.
0.7 V
0
internally fixed
2.8
IRR
charge
= 0.5 mA
0.95
kHz
V
1.8
1.9
V
3
mA
4
5.2
mA
1.05
Comparator K1
Input current
II KI
Turn-off delay time 2 )
(signal transit time input K 1
to QSIP)
Common-mode input
voltage range
VIC
0
2
IJA
500
ns
5.5
V
1) CT = 0.2 nF cDrrespDnds tD a fall time Df 0.2 ~s (± 30%) if the discharge current largely exceeds the IDad current.
The fall time equals the minimum dead time at the DutpUt.
2) Step functiDn 11 V = -100 mV...r-> 11 V = +100 mV, fDr transit time from input cDmparatDr tD QSIP
666
TDA4919 G
Characteristics
VsaN Vsw
10
15
20
0.1
J.lA
J.lA
3
J.lS
For footnotes refer to page 666.
667
TDA4919 G
Characteristics
VSON < Vs <30 V; TA = -40 to +85°C
Test conditions
Lower
limit B
typ
Upper
limit A
Overvoltage K3
Input current
Switching voltage
0.2
-I'K3
Vsw
VREF
+20mV
VREF
-20mV
lurn-off delay time 2)
Hysteresis current
-I Hy3H
-I Hy3L
VI - K3J > Vsw
VI - K3J < Vsw
7
Vs-3
10
iJ A
V
3
iJs
13
0.1
iJ A
iJ A
Output driver QSIP
Output voltage high
VOH
I os,P = -300 mA
Output voltage low
VOL
VOL
I os,P
-I os,P
I osIP =+300mA
IoslP = +1 0 mA
Output current
V
1.8
1.4
V
V
mAl)
mAl)
COSIP = 10 nF
500
300
700
1000
Vs > VSON
6.3
6.9
7.5
V
5.6
6.2
6.8
V
25
5
32
iJ A
iJ A
Input standby 1St
Turn-on threshold for
VISt rising
Turn-off threshold for
V,stfalling
Hysteresis current
VIStH
VIStL
-IHystH
I HyStL
VISt > VIStH
VISt < VIStL
1) Dynamic maximum current during rising or falling edge
2)
Step function VREF
3) Step function II V
668
= -100 mV -r-
= -100
18
VREF = +100 mV } for transit time from
mV.J-> II V = + 100 mV
input comparator to Q SIP
TDA4919 G
Pulse diagram
vo Itage at
CT
1\/ \ / \ /
/
Voltage at CR
~>
/
1,8
/
VI rated
> VI
IJ
""r~
I
,
£
.....
/1
/"
Vc soft start
/
tV l/
Ul
/
I
o
__ Max. Possible
Duty Cycle
at VI rated
Voltage at
QSIP
VaS IP V
t
-Lr
I
1
o
r-"'"""1
II
: ::
O,ST
1T
--
!
,..-
1,ST
I
Ll..-t
Soft Start - Error - ON/OFF
1 2
-t
669
~
o
.11;
III
0-
n
;II;"
----t--- i
III
~
3
t-_~-+-__+I--+I-=--J ~C~i~e H
I
120 ~A
op amp
...
II .... VsaslP
II)
IK 1/Q OP 19 1Input Comparator K1
Output
a.
iii"
(,Q
I ' g~~p
Input
-lOP 18IOpAmp(-1
.IOP 171-~""·"'·'
I
20 GND aSIP
OV
Internal
I•
Supply
Supply Voltage
+ Vs
+ VREF
I
J
Reference Voltage
11
Input Standby (I St)
110
+ Vs
+VREF
1,5V
lSI
=
L - IH,I5I= 25 ~A
I
10pF
lSI
IHylSt
Soft Start
6
If~oF'"''
Overvoltage
,12
Iov
Undervoltage
13
Iuv
Oyn. Current
Limitation
IHI'L
115
+IOYN
16
1
-IOYN
-I
~
~
CD
~
CD
(i)
TDA4930
Stereo/Bridge AF Amplifier 2 x 10 W/20 W
SIP9
The TDA 4930 can be applied as a class B stereo amplifier or mono amplifier in bridge
configuration for AF signals. In addition, the component is provided with a protective circuitry
against overtemperature and overload.
Features
•
•
•
•
Universal application as stereo amplifier or mono amplifier in bridge configuration
Wide supply voltage range
Minimum of external components
Outputs AC and DC short-circuit resistant
Maximum ratings
Supply voltage
Output peak current
Input voltage range
Junction temperature
Storage temperature range
Thermal resistance (system-case)
Vs
11 ; 19 pp
V2 ; V3 ; V7
7j
Ts1g
R1hJC
32
2.5
-0.3 to Vs
150
-40 to 125
I6
V
A
V
°c
°c
IKlW
Operating range
Supply voltage
RL~8 Q
Vs
RL=4 Q
Case temperature
Pv = 10
Vs
Tc
W
8 to 26
8 to 22
-20 to 85
I~c
671
TDA4930
Characteristics
Vs =19
V; TA =25°C
Test
circuit
Quiescent current (V; = 0)
Output voltage (V; = 0)
Input resistance 1)
Output power (f = 1 kHz)
min
typ
max
9
30
9,5
20
60
10
7
9
8
10
W
W
14
18
16
20
W
W
40
46
dB
15
Vq9 ;1
R17 ;3
rM
V
kQ
- stereo operation
THD= 1%
THD=10%
PqS ;1
Pq9 ;1
- bridge operation
THD= 1%
THD=10%
Pq9 ;1
Pq9 ;1
Line hum suppression 2)
fr = 100 Hz; V, =0.5 V
ahum
Current consumption
I5
1.5
A
11
70
%
Total harmonic distortion
P9/1 = 0.05 to 6 W
f; =40 Hz to 15 kHz
THD
0.2
Cross-talk rejection
f; =1 kHz; Ps or P1 =10 W
Transmission range 3 )
Disturbance voltage (B = 30 Hz to 20 kHz)
in acc. with DIN 45405 referred to inpu(4)
Noise voltage (CCIR filter)
in accordance with DIN 45405
referred to the input4 )
Difference in transmission measure
acr
50
2
2
P9 =P1 =10 W; f; =1 kHz
Efficiency
P9 =P1 =10 W; f; =1 kHz
0.5
dB
.
40 Hz to 60 kHz
5
B
Vd
I1 V
15
Vn
%
I1 Vs
.1G v
dB
P9 =P1 =7W
f; = 40 Hz to 20 kHz
Voltage gain stereo
Voltage gain bridge configuration
Gv
Gv
1
2
30
36
DC output voltage at
active DC protection
if S1/9 is closed; Vs ;;'10 V
Vq9 ;1
2
0.15
1) S2a(b) open/closed
2) S1a(b) and S3 in position 2
3) PS/1 - 6 W; -3 dB referred to 1 kHz
4) S1a(b) in position 2
672
dB
dB
0.30
V
TDA4930
Circuit description
The IC contains 2 complete amplifiers and can be used for a wide variety of applications
with a minimum of external circuitry.
The TDA 4930 can be applied as stereo amplifier or amplifier in bridge configuration for
operating voltages ranging between 8 V and 26 V, with speakerload impedance from 1 to 16 Q.
The prestages are differential amplifiers with strong negative feedback. Internal frequency
compensation in the driver amplifier limits the gain-bandwidth product to 4.5 MHz.
The power output stages are comprised of quasi PNP transistors (small saturation voltage).
Each power element is equipped with an independent protective circuit, rendering the outputs
of the amplifiers AC and DC short-circuit resistant.
A DC protective circuit of the outputs prevents overloading of the loudspeakers, if ground
connections become apparent during bridge operations. To avoid overheating, a temperature
fuse affecting both amplifiers prevents current supply to the power output stages during
inadmissibly high chip temperatures.
As a special economic feature, the negative feedback resistances for Gv = 30 dB and the
input voltage reference divider have been integrated.
Pin description
Pin
Function
1
3
4
Output right channel
Inverting input right channel
(more than 22 kQ)
Non-inverting input right channel
GND
5
+Vs
6
7
8
GND
Non-inverting input left channel
Line hum suppression right and left channel
Output left channel
2
9
673
TDA4930
Block diagram
~
t
30,6 R
22kl")
*
~~
~~~
V
V
Prestage
7
4--
1
20kl")
+Vs 5
Power
Supply
and
OverTemperature
Protection
H~m
-ine Hum
3uppression 8
Suppression
~ircuit
r-
r-
Protection
Circuit
+Input 3
Right
~
22kl")
b>-8>~;~
Prestage
r- Dnver
J22kn
IL
=i=
R
3Q.6R
II
DC Output
Protective
Circuit
r--
4.6
GND
Protection
Circuit
J20kl")
674
Output
Left
r-V
+ Input
Left
-Input 2
Right
9
~ S(f
Driver
~~
J
Output
Right
TDA4930
Test and measurement circuit
1. Stereo operation
TDA 4930
Power Supply
+
-
15,3kQ
22kQ
115,3 kQ
22kQ
500QI
20kQ
8
5
=i= 1fJF 220 nF
4;6
~ 2,2 mF= ==
2 3
1
==2,2mF ==220nF
[ 4Q
[}OkQ =i=10nF
1fJF=i=
1Q
10nF== 10kQI)
V; _
-
2
S1 ;:-0o-1'---_--l2COCkQI--~
1;;:
II;
2
'--I~CO=kQ}---.----,<1:Y(S1 b
II
~1
1~t
UI
+Vs
GND
675
TDA4930
Test and measurement circuit
2. Bridge operation
TDA 4930
Power Supply
+
-
15,3 kQ ]
15,3 kQ
~
~
246 Q
500Q ]
~
[l15.3 kQ
22kQ
~
~~==r-~
SOD QO
(J1 kl!
L -_ _~_ _~_ _~_ _~_ _~_ _~~
9
8
5
4;6
22 kQ
~
1
~r-~--1-_~t::8=Q~-1---1--~~~
100 flF =i=
220nF==
==220nF
1 pF=:=
If;
'-----{-I------+---+-------+---+---+-------------'
UI
+Vs
676
GND
::--=:;7"
TDA4930
Application circuit
1. Stereo operation
TDA 4930
. - -~
r-V
I
Power Supply
+
/+
-I
t---
~ r--
>----
15.3 kl1
15.3 kl1
( 15.3 kl1
- ~
~
~
~
50011
24611 Jl1kl1
50011(
22 kl1[J
20 kl1
20kl1
7
22 OnF = P[4
9
220nF
==[,
R,
10
5
>-------,
1000flF
[L '"
4;6
8
~OflF
~~"" [5=
""
~R'
[7
1
== ~[L
R'~
2 3
[2= =
220nF
[J =
p220 nF
1O[ ]R2
== 100 nF
~
II;
+Vs
GND
Vi
VS
RL
[L
19V
411
26V
811
OOOflF 470flF
677
TDA4930
Layout/Plug-in loc~tion plan
I
11
Lt.-C:r. -1~.1~ell
T
T
c ."!,,,
J£4
c..l.l
. 00
'00+
-00, 0
00- - -00
o
678
1
TDA4930
Application circuit
2. Bridge operation (only one channel)
TDA 4930
~
-
/- r--
Power Supply
/
~ t--
-
+
~
1S,3 krlrJ
1S,3krl
[}S,3 krl
~
~
~
~
SOOrl[)
246
riO
~
SOOrl J
[}krl
~
[a
J
~
~
~
7
22krl
9
S
8
4;6
2 3
1
= = 220nF
220 nF = ~
[7
220 nF = ~[1
1r1[ JR 1
RL
[2
R2
100 ~F == 1=[3
[4
= = 220nF
220 nF= ~[6
Hl
11100nF
II
1000
I
I
~F
nI
Vs
RL
1 19V l 26VJ
I 8r1 I 16r1 I
~;
GND
679
TDA4930
Layout/Plug-in location plan
680
TDA4930
Quiescent current versus
supply voltage
Typical operating range of the
final transistors adjusted by
internal protective circuits
A (SOA = Safe Operating Area)
2,5
2,375 ~/ I~
rnA
50
Ie
t
35
V
30
/,V
/'
/'
IL f/
V
2,0
1,625
1,5
16
20
24
28
32 V
lI'
f = 1kHz
RL = 411
Dynamic
Straight
o '//r
o 5
10
15
''-:;
~
'//r
20
25
~
35 V
30
/
//
V VI
I .IV
Output power versus
W supply voltage
12
V
fLL
RL= 811
i/ V
THD=10%
V
/
THD=10%
/
/
/
Vy/
,/
J
V
f =1kHz
T RL = 411- rTHD=l%
/'
V ././
4
V
/ /
/
\'
'//\ ~~~.u/26V
Stereo operation
!
6
~
~ SOA '/' ~
;-
Stereo operation
Output power versus
W supply voltage
10
4
'\ ''\
:;-
0,5
12
\
\
I
8
Dynamic Straight
lor 4 Q/19V
.~
_\
~\
1,0
/'
25
20
~l ~
./
,/
/
V-f =1 kHz I-RL = 811
THD=l%
V
~ f/
o
8
o
10
12
14
16
18
20 V
16
18
20
22
24
26V
681
TDA4930
Bridge operation
Stereo operation
Output power versus
W supply voltage
20
Pq
t
Total harmonic distortion
II
f :lkHz
RL: all
16
THO: 10%
/
Vs: 26 V
f : 1 kHz
II[7V
RL :
J
12
V 1I
I/1/
7V
~
o
o
V
f : 1kHz
l-
RL : 811
4
HO: 1%
1/ /
2
C;
10
an
6
1I j 17
a
4
% versus output power
10
12
14
16
18
20 V
U
o
o
4
12
8
16 W
-Vs
Stereo operation
Stereo operation
Total harmonic distortion versus
% output power
W versus output power
10
6
Power dissipation (each channel)
I---I---
I
II
IT
VS : 19V
f : 1kHz- IIRL : 4n
6
j
I
1/
4
3
4
r--..
V
/
Vs : 19V
f : 1kHz
RL : 4n
'"
l""- I-
I
2
!
o
o
)
2
4
6
8
- Pq
682
lOW
o
o
4
6
a
10 W
TDA4930
Stereo operation
Stereo operation
Power dissipation (each channel)
W versus output power
6
=I-
V
l---H....
i ___
,7
4
I
I
1--.;---
N-.
I
~
I
I
---H
I
I
+
!
I
+
t-+--c-
Ii
I
I
Vs = 19V
80
RL = 412
I I
V
20
/'
i
If
I
10
4
12 W
I
1/
:
i
1
/V
40
o
Stereo operation
o
4
Stereo operation
W versus supply voltage
100
5
Power dissipation (each channel)
r
II
,
,
,
4
./
40
20
o
I- [1
rl
i7
)7
/
V
V
1/
Vs = 26V
f = 1kHz
RL = 812
I
THD=l%J
V
II
I
I
-,--
V
Vf =lkHz
RL = 812
I /
V
V
THD-l%
I
/
i
o
I
V
[7
i
f =1kHz
RL =412
I
f---
10 W
8
Efficiency versus output
% power
60
V'
/'
/'
!.
.
I
V
60
,.
I----c--
= 1kHz
f
I
= lkHzT
RL = 812 I '
f
I
o
o
~
Vs = 26V
7)
t
i-t-
I
!
I
ll_L 1":
!
-, i
y-
T T
-fl
1-.
Efficiency versus output
% power
100
4
12 W
o
8
12
16
20
24
28 V
-Vs
683
TDA4930
Stereo operation
Stereo operation
Supply current (one channel
A modulated) versus output power
1,0
Is
t
Vs = 19V
f =lkHz
RL = 411
O,B
V
0,6
V
/
1/
V V
1/
0,4
0,2
il
III
°°
Total harmonic distortion
% versus frequency
10
1
1/
~
,
1
Vs = 19V
RL = 411
2
~
Pq = 8WV
VV
Vs = 26V_ f-f = 1 kHz
RL = BlI- f-
[7
I
THO 5
0,5
0,2
4
6
8
10
Pq =7W
l--'
0,1
2
V
V
IIIII
12W
10 4 Hz
-f
Line hum suppression versus
dB frequency
Cross-talk rejection
dB versus frequency
,
50
17
70
,
a e,
I
t
~
40
\
Vs= 19V
RL= 411
Rs= 10kll
V,= 0,5V
,
"'
U- "
"II
11111,
.If ,
V1!
ill
r\
I
IV
,
,
i
iI
30
50
i
\
-f
I
,
\il i'
' 1\
I'
I
,
Pq=BW ,
:
II
I--
' I
i '\:
I
!'
i
684
' ,'.,
I', ,
J
60
~~.
'Vs =19V
RL=4 l i t -
I
I
I
i
hl 1\
I Pq = lOW
'\
I I
I I
-f
\
TDA4935
Stereo/Bridge AF Amplifier 2 x 15 W/30 W
SIP9
The TDA 4935 can be applied as a class 8 stereo amplifier or mono amplifier in bridge
configuration for AF signals. In addition, the component is provided with a protective circuitry
against overtemperature and overload.
Features
• Universal application as stereo amplifier or mono amplifier in bridge configuration
• Wide supply voltage range
• Minimum of external components
Maximum ratings
Supply voltage
Output peak current
Input voltage range
Junction temperature
Storage temperature rang'e
Thermal resistance (system-case)
Tstg
32
2.8
-0.3 to Vs
150
-40 to 125
V
A
V
°C
°C
RthJC
4
K/W
Vs
Vs
Vs
Tc
8 to 30
8 to 24
-20 to 85
V
V
°C
Vs
11 ; 19
V2 ; V3 ; V7
7j
Operating range
Supply voltage
RL~8 Q
RL=4 Q
Case temperature
Pv =15 W
685
TDA4935
Characteristics
Vs =24 V;
Tc =25°C
Quiescent current
Test
circuit
min
Is
typ
max
40
80
mA
12
13
V
Vi =0
Output voltage
11
Vq1 ;g
Vi =0
Input resistance 1 )
R;3;7
Output power
f=l kHz
- stereo operation
THO = 1%
P q1 ;g
THO=10%
Pq1 ;g
- bridge operation
THO = 1%
Pq1 ;g
THO=10%
Pq1 ;g
Line hum suppression 2 )
ahum
fR = 100 Hz; VR = 0.5 V
Current consumption
Is
Pg =P 1 =15W;f;=1 kHz
Efficiency
1]
Pg =P 1 = 10 W; f; = 1 kHz
Total harmonic distortion
THO
Pg/1 =0.05 -10 W
f; =40 Hz to 15 kHz
Cross-talk rejection
a er
fj = 1 kHz;
p9 orP1 =15W
Transmission range 3 )
B
Disturbance voltage (B =30 Hz to 20 kHz) Vd
in acc. with DIN 45405
referred to input4 )
Noise voltage (CCIR filter)
Vn
in acc. with DIN 45405
referred to the input 4 )
Difference in transmission measure
LlG v
P9 =P1 =10 W
fj =40 Hz to 20 kHz
Voltage gain
stereo
Gv
bridge configuration
Gv
S2a(b) open/closed
S1a(b) and S3 in position 2
3) P9/1 - 6 W; -3 dB referred to 1 kHz
4) S1a(b) in position 2
1)
2)
686
2
2
1
20
kQ
10
13
12
15
W
W
20
26
40
24
30
46
W
W
1.8
A
70
%
0.2
dB
0.5
50
40 Hz to 60 kHz
5
15
%
dB
~V
~Vs
dB
1
2
30
36
dB
dB
TDA4935
Circuit description
The Ie contains 2 complete amplifiers and can be used for a wide variety of applications
with a minimum of external circuitry.
The TDA 4935 can be applied as stereo amplifier or amplifier in bridge configuration for
operating voltages ranging between 8 V and 26 V.
The prestages are differential amplifiers with strong negative feedback. Internal frequency
compensation in the driver amplifier limits the gain-bandwidth product to 4.5 MHz.
The power output stages are comprised of quasi PNP transistors (small saturation voltage).
To avoid overheating, a temperature fuse affecting both amplifiers prevents current supply
to the power output stages during inadmissibly high chip temperatures.
As a special economic feature, the negative feedback resistances for G v =30 dB and the input
voltage reference divider have been integrated.
Pin description
Pin
Function
1
Output right channel
Inverting input right channel
(more than 22 kQ)
Non-inverting input right channel
GND
+Vs
GND
Non-inverting input left channel
Line hum suppression right and left channel
Output left channel
2
3
4
5
6
7
8
9
687
TDA4935
Block diagram
R
30,6R
>--........--19
Output
Left
+ Input 7 1--_--1
Left
20kQ
+Vs 5
1--+----+-----1
Hum
8 I--~---I SupLine Hum
pression
Suppression
Circuit
Power
Supply
and
Temperature
Pro-
1------------1
4,6
GND
tection
20kQ
+ Input 3 1--.......---1
>--_._---l1
Right
-lnput 2
Right
Output
Right
22kQ
R
688
30,6R
TDA4935
Test and measurement circuit
1. Stereo operation
TDA 4935
Power Supply
22 kQ
2k
20kQ
7
6
5
8
3
20kQ
20kQ
S2a
2
4;6
.--L-J-__-~S lb
1000 ~F
GND
689
TDA4935
Test and measurement circuit
2. Bridge operation
TDA 4935
r---..-- 0
di/df< 0
Video output voltage (pos.)
RL =00
Sync pulse level
DC voltage V 2 = 4 V; V17I1S = 0
Output current
to ground through R
to plus V3 = 7 V
Video output voltage (neg.) (R L =00)
Sync pulse level
DC voltage (V2 = 4 V; V17I1S = 0)
Output current
to ground through R
to plus V 4 = V 13
V 13
Vq4pp
3.0
V 4/12
V 13 -2.0
V 4/12
V 13
1q4
-5.0
+1.0
mA
mA
Bvideo
1.8/2
6.6/2
20
150
150
10
6.0
kQ/pF
kQ/pF
kQ
Q
Q
mV
MHz
a
45
dB
lq4
-5.3
Additional application data 1)
Input impedance
Output impedance
AFC input impedance
Output resistance
Output resistance
Residual IF (baSic frequency)
Video bandwidth (-3 dB)
Intermodulation ratio with
reference to fcc
(sound-color-beat frequency)
1) not measured
700
Zi17118
Zq10J11
Zi8/9
Rq3
Rq4
V 3 ; V4
TDAS400-2
Circuit description
The integrated circuit is comprised of a 4-stage controlled AM amplifier, a limiter and mixer
for synchronous demodulation of the video signals as well as an FM demodulator to generate
positive or negative AFC voltages. In addition, an amplifier for both the positive and negative
video output signal is included. The positive video signal together with the positive flyback
pulse are used for gated control.
o
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Function
Gating pulse
Time constant AGC
Positive video output
Negative video output
AFC polarity switch
AFC output
White level adjustment
AFC circuit
AFC circuit
Tank circuit
Tank circuit
GND
Supply voltage
Reference voltage
Tuner AGC
Delayed AGC output
Video IF input
Video IF input
701
TDAS400-2
Block diagram
Tuner
Control
18
17
15
16
13
12
4
Jl
702
Iv
~
J\
AFC
+/Vs
White Level
11
10
q
3:
Tuner
Control
Delayed
Tuner
Control
IIIIn
C
V. tab
~
+Vs
l!l
n
~r
c
22nF
50Q
18
17
;::;:
100nF
H
16
H
15
14
22pF
13
12
11
6
7
8
10
TDA 5400-2
2
4
5
V-I J'\
1 kQ
Jl
I I
I I
LJ
"
""oc.:>
68~'---l
H
-'-I22onF
AFCOFF
CuLSO.25 mm
7.5 Turns
AFC
Video.
Video-
./-AFC
AFC
White Level
g
(J1
~
o
o
N
704
Modulator for TV, Video and Sound Signals
TDA5660 P
DIP18
The monolithically integrated circuit TDA 5660 P is especially suitable as modulator for
the 48 to 860 MHz frequency range and is applied e.g. in video recorders, cable converters,
TV converter installations, demodulators, video generators, video security systems, amateur
TV applications, as well as personal computers.
•
•
•
•
•
•
•
•
•
•
•
•
•
Synchronizing level-clamping circuit
Peak white value gain control
Continuous adjustment of modulation index for positive and negative modulation
Dynamic residual carrier setting
FM sound modulator
AM sound modulator
Picture carrier to sound carrier adjustment
Symmetrical mixer output
Symmetrical oscillator with own RF ground
Low radiation
Superior frequency stability of main oscillator
Superior frequency stability of sound oscillator
Internal reference voltage
Circuit description
Via pin 1, the sound signal is capacitively coupled to the AF input for the FM modulation
of the oscillator. An external circuitry sets the preemphasis. This signal is forwarded to a
mixer which is influenced by the AM modulation input of pin 16. The picture to sound carrier
ratio can be changed by connecting an external voltage to pin 16, which deviates from the
internal reference voltage. In case, the sound carrier should not be FM but AM modulated,
pin 1 should be connected to pin 2, while the AF signal is capacitively coupled to pin 16.
Through an additional external dc voltage at pin 16, the set AM modulation index can be
changed by overriding the internally adjusted control voltage for a fixed AM modulation index.
At the output of the above described mixer the FM and/or AM modulated sound signal is
added to the video signal and mixed with the oscillator signal in the RF mixer. A parallel
resonant circuit is connected to the sound carrier oscillator at pin 17, 18. The unloaded Q of
the resonant circuit must be Q = 25 and the parallel resistor RT = 6.8 kQ to ensure a
picture to sound carrier ratio of 12.5 dB. At the same time, the capacitative and/or inductive
reactance for the resonance frequency should have a value of Xc "" XL "" 800 Q.
The video signal with the negative synchronous level is capacitively connected to pin 10.
The internal clamping circuit is referenced to the synchronizing level. Should the video
signal change by 6 dB, this change will be compensated by the resonant circuit which is
set to the peak white value. At pin 11, the current pulses of the peak white detector are
filtered through the capacitor which also determines the control time constant. When pin 12
is connected to ground, the RF carrier switches from negative to positive video modulation.
705
TDA5660 P
With the variable resistor of R = 00 •••• 0 Q at pin 12, the modulation depth, beginning with
R = 00 and a negative modulation of m OIN = 80%, can be increased to m OIN = 100% and
continued with a positive modulation of m o/P = 100% down to m o/P = 88% with R = 0 Q.
The internal reference voltage has to be capacitively blocked at pin 2.
The amplifier of the RF oscillator is. available at pins 3-7. The oscillator operates as a
symmetrical ECO circuit. The capacitive reactance for the resonance frequency should
be Xc "" 70 Q between pins 3, 4 and 6, 7 and Xc "" 26 Q between pins 4, 6. In order to
set the required residual carrier suppression, pin 9 is used to compensate for any dynamic
asymmetry of the RF mixer during high frequencies of > 300 MHz. The oscillator chip ground,
pin 5, should be connected to ground at the oscillator resonant circuit shielding. Via pin 3
and 7 an external oscillator signal can be injected inductively or capacitively. The
peripheral layout of the pc board should be provided with a minimum shielding attenuation
of approx. 80 dB between the oscillator pins 3-7 and the modulator outputs 13-15.
For optimum residual carrier suppression, the symmetric mixer outputs at pins 13, 15 should
be connected to a matched balanced-to-unbalanced broadband transformer with excellent
phase precision at 0 and 180 degrees, e.g. a Guanella transformer. The transmission loss
should be less than 3 dB. In addition, an LC low pass filter combination is required at the
output. The cut-off frequency of the low pass filter combination must exceed the maximum
operating frequency.
If the application circuit according to figure 1, 2 is used, a multiplication factor V/RF
(application) = V/RF (data sheet) 3.9 must be used to convert a 300 Q symmetrical
impe:dance to an asymmetrical impedance of 75 Q for the stated RF output voltage Vq of
the type specification in order to ensure a transmission attenuation of 0 dB for the balancedto-unbalanced mixer.
706
TDA5660 P
Maximum ratings
Remarks
min
max
-0.3
0
14.5
2
V
mA
V2 +2
1
1.5
V
V
V
Supply voltage
Current from pin 2
-12
Voltage at pin 1
Voltage at pin 9
Voltage at pin 10
Vl
Vg
VlO pp
V2 -2
-4
Capacitance at pin 2
Capacitance at pin 11
Voltage at pin 12
Voltage at pin 13
Voltage at pin 15
Voltage at pin 16
C2
Cll
V12
V13
V16
0
0
-0.3
V2
V2
V2 -1.5
100
15
1.4
Vs
Vs
V2 +1.5
nF
I!F
V
V
V
V
Junction temperature
Storage temperature
~
Tstg
-40
150
125
°C
°C
Thermal resistance (system-air)
RthSA
80
KlW
Vs
~5
V2 -7 to 8 V
Vs = 9.5 to 13.5 V
Vs = 9.5 to 13.5 V
only via C
(max.11!F)
Vs = 9.5 to 13.5 V
Only the external circuitry shown
in application circuits
1 and 2 may be connected
to pins 3, 4, 6, 7,17 and 18
Operating range
Supply voltage
Video input frequency
Sound input frequency
Output frequency
Vs
fVtDEO
fAF
fq
9.5
0
0
48
13.5
5
20
860
V
MHz
kHz
MHz
Ambient temperature
Sound oscillator
Voltage at pin 13, 15
TA
fosc
0
4
V2
70
7
Vs
°C
MHz
V
~3.l5
depending on the
oscillator circuitry
at pins 3-7
707
..
-
~
TDA5660 P
Characteristics
Vs = 11 V; TA =25°C
Current consumption
18
Reference voltage
V2
Oscillator frequency range lose
Turn-on start-up drift
.1 lose
Frequency drift as
function of Vs
-.1lose
Video
at pin
Video
at pin
-110
input current
10
input voltage
10
Modulation depth
VVIOEO pp = 1 V; IVIOEO ~
200 kHz sine signal
Output impedance
RF output voltage
Modulation signal in
neg. modulation
pin 12 open
Output capacitance
V10 pp
mOIN
mOIP
Z13;Z15
VQrms
Figure
min
typ
max
12 =0 mA
1; 2
1; 2
22
7
48
30
7.5
40
8
860
mA
V
MHz
1; 2
1; 2
1; 2
0
0
0
-50
-200
-500
-500
kHz
kHz
5
-150
0
150
10
kHz
flA
at coupling capac.
C~l flF
Ileak~ ±0.3 flA
neg. mod.
pos. mod.
21;22
0.7
1.4
V
1; 16
2;16
75
83
80
88
85
93
%
%
static
Ch 40
24
1b
10
2.5
3.5
5.5
kQ
mV
25
0.5
2.0
pF
0~I2~ 1
mA
External circuitry
adjusted to
frequency
TCvalue of
capacitor in osc.
circuit is 0; drift is
referenced only to
self-heating of the
component
1=0.5-10s;
TA =const.
Ch 30
Ch40
Vs =9.5-13.5 V
TA =const.
Ch 40
ClO~l flF
C13 =C 15
S parameter at pins
3,4 and 6, 7
RF output phase
«13.15
RF output voltage
.1Vq
change; adjustment
range
RF output voltage change .1Vq
RF output voltage change .1Vq
Oscillator interference FM
caused by AM modulation and
coupling of the modulator
output with the oscillator
resonant circuit;
VVIOEO pp = 1 V;
IVIOEO = 10kHz; sine signal
Ch 30
Ch 40
708
Test conditions
26
140
1=543.25-623.25
.11=80 MHz
Ch 30-Ch 40
1= 100-300 MHz
1=48-100 MHz
1
6
6
0
0
0
1; 9
1; 9
0
0
180
5
7
220
degrees
1.5
1.5
1.5
dB
dB
dB
15
21
kHz
kHz
TDA5660 P
Characteristics
Vs =11 V; TA =25°C
Intermodulation ratio
Harmonic wave ratio
aMR
aH
Harmonic wave ratio
Harmonic wave ratio
aH
aH
Sound carrier ratio
Color picture to sound
carrier ratio
ap/s
ap
All remaining harmonic
waves
a
Amplitude response of
the video signal
av
Residual carrier
suppression
Static mixer balance
characteristic
Dynamic mixer balance
characteristics
Stability of set
modulation depth
aR
Stability of set
modulation depth
Stability of set
modulation depth
Stability of set
modulation depth
Test conditions
Figure
Ip+1.07 MHz
Ip +8.8 MHz without video
signal 19, 20, 21 unmodulated
video and sound carrier,
measured with the spectrum
analyzer as difference between
video carrier signal level and
sideband signal level without
video and sound modulation.
Ip+2ls
Ip +31s
Vq with spectrum analyzer;
loaded Q factor Q L of the sound
oscillator resonant circuit
adjusted by Rs to provide the
required picture to sound carrier
ratio of 12.5 dB; Rs = 6.8 kQ;
Q u = 25 of the sound oscillator
circuit.
1;7; 15 54
1; 7;15 35
75
dB
dB
1; 7
1; 7
48
48
dB
dB
Ip +4.4 MHz (dependent on
video signal)
Multiple of fundamental wave
of picture carrier, without video
signal, measured with spectrum
analyzer;
'p/s = 523.25-623.25 MHz
VVIOEO pp = 1 V with additional
modulation 1=15 kHz-5 MHz
sine signal between black
and white
1; 13
0
1; 12
32
21; 23
-100
6
LImo
1= 100 ... 300 MHz
6
LI mo
TA =0-60·C; Vs = 12 V
LImo
typ
12.5
17
max
15
15
LImo
11,3 rms
35
42
1;7; 17 10
1
With adjustment at pin 9
Ch 30 ... Ch 40
V g adjusted to LI V13/15
minimum
V g adjusted to V13 rms
minimum
Video input voltage changes
with sine signals
I =0.2 MHz; LlVVIDEOpp = 1 V
± 3 dB; Ch 30 ... Ch 40;
Vs = 12 V; TA =const
1=48 ... 100 MHz
LlV13/15
min
21;23
dB
dB
dB
1.5
dB
0
+100
mV
0
10
mV
±2.5 %
±2.5 %
2
±4
%
±2.5 %
709
TDA5660 P
Characteristics
Vs
=11
V;
TA=25°C
Test conditions
Stability of set
modulation depth
Interference product
ratio sound in video;
sound carrier FM mod.
Signal-to-noise ratio in
video; sound carrier
unmodulated
Interference product
ratio sound in video
sound carrier AM mOd.
Umweighted FM noise level
ratio video in sound;
FuBK test picture as
video signal
Unweighted FM noise level
ratio video in sound
min
typ
max
aSIP
Vs =9.5-13;5V;
TA=const.
Ch 30 ... Ch40
1; 11
48
60
dB
aNiP
Ch 30 ... Ch40
1; 11
48
74
dB
aSIP
Ch 30 ... Ch40
1; 11
20
33
dB
apls
Ch39
1a;8
48
54
dB
apls
Ch 39; test picture VU
G-Y; UN
Ch 39; color bar
Ch 39; uniform red level
Ch 39; uniform white level
Ch 39; test pattern
Ch 39; white bar
Ch 39; bar
Ch 39; 20T/2T
Ch 39; 30% white level
Ch 39; 250 kHz
Ch 39; multiburst
Ch 39; ramp
2;8
48
56
dB
2;8
2;8
2;8
2;8
2;8
2;8
2;8
2;8
2;8
2;8
2;8
1a;8
46
48
45
48
46
45
43
48
46
46
44
48
52
58
51
55
52
50.8
49
58
52
53
50
54
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
LlmD
Signal-to-noise ratio of
sound oscillator
Differential gain
as/N
Differential phase
Period required for peak
white detector to reach
steady state for full
modulation depth with
1 white pulse per half
frame with control in
steady state
I"
Co
I
FM Sound Oscillator
~
.".
C,lamping
circUit
Modulator Output Buffer Stage
I
iii'
(,Q
iil
3
~
+AM\
Sound
Input
:
{
/-~
Sound /
Carrier
V
~~
<
AM Sound
Modulator
Video
Buffer
Stage
~
Oscillator Buffer Stage
I
I
Vslab
4~~
~<
Input
AmplifierFM
'1
~-LJ
2
3
==
~~K1
n-
==
5
V\
>-
Oscillator
4
Gain
Index
6
7
!ReSid~
Carrier
Adjustm,
8
91
g-t
CI1
m
-.J
en
o
W
"'0
TDA5660 P
Test and measurement circuit 1
for FM sound carrier and negative video modulation
Anzac 183-4
5.5 MHz
Sound Oscillator Tank
Circuit
RT 6.8kn
33pF
18
17
TDA 5660 P
22kn 2
~
220kQ
1
3
220pF ...JlOnF
2.2pF
Relerence7.5V
O.S~FT
FMAFlnput
_
!17pF
rPF
L
_
BBSOS B
10nF
H
47kQ
+Vd
Channel 30 ... 40
Figure 1
714
H
Vs =9.5-13.5 V
_
~22PF1~_~~22PF
47kQ
9
10nF
33 kQ
Dynamic Residual
Carrier Adjustment
(II Required)
at Pin 2
TDA5660 P
Test and measurement circuit 1
for FM sound carrier and negative video modulation
Anzac 183-4
5.5 MHz
Sound Oscillator Tank
Circuit
33pF
18
17
TDA 5660 P
9
I
22 k(l
I I
O,5pF
FM AF Input
"cF
J"' !
P
F
r
10nF
H
47 k(l
H
VPF
',7pF
Vs =9.5-13.5 V
Reference 7.5 V
22PF
1nF
BBSO~SB 22pF
10nF
H
Dynamic Residual
Carrier Adjustment
(If Required)
47 k(l
+ Vd
Channel 30 ... 40
VDN 10 ... 28
at Pin 2
Figure 1a
715
TDA5660 P
Test and measurement circuit 1
for FM sound carrier and negative video modulation
1--~-lMeasuremen
Anzac 183-4
Receiver
5.5 MHz
Sound Oscillator Tank
Circuit
RT 6.8kll
33 pF
18
I
17
1nF
16
15
14
13
TDA 5660 P
2
TI 1
i
22kll
05
• ~F
2 2PF
.
10 nF
FM AF Input Reference 7.5
V
2,7pF
---j~
~
8
10nF
H
2 2PF
.
Vs =9.5-13.5 V
L,
22PF
BB50~5B 22pF
~
47 kll
10nF
H
47 kll
+Vd
Channel 30 ... 40
VoIV 10 ... 28
Figure 1 b
716
at Pin 2
TDA5660 P
Test and measurement circuit 2
for FM sound carrier and negative video modulation
5.5 MHz
Sound Oscillator Tank
Circuit
Circuitry Identical
to Measurement
Circuit 1
RT6.8kl1
33pF
18
17
TDA 5660 P
10nF
10nF
I
1
P
2.2 F
Reference 7.5 V
!2'7~
H
I::~9'5_13'5V
25kl1
"--------1_f-------~
,.-
nPFT
47>oQ
L
1~22PF
B:~SB H~mo
33 kl1
Dynamic Residual
Carrier Adjustment
(If Required)
"'""'
Channel 30 .. .40
Figure 2
717
TDA5660 P
AM sound modulation measurement
Broadband Amplifier 30 dB; e.g
OM 361 Fa. Philips
---
RF Input
Vq
Pin 9
Vg --3.4 ~
Test Circuit 2
AF Input
Modulation
Measurement DevicE
e.g. FAM by R&S
Filter: 30 Hz-20 kHz
Detector:
(P+P)/2 Type of
Modulation: AM
AM AF Input
VAFrms
Sound Generator
fAF-1 kHz
Figure 3
718
Measurement of AF
Input Level
TDA5660 P
AM sound carrier modulation index versus
AF input voltage at pin 16
%
100
50
/
/
V
/
V
/
v
1,5 V
0,5
--VAFrms
Figure 4a
AM sound carrier modulation index versus
dc voltage offset at pin 16
VAF rms '= 0.6 V; LlVi6/2 (V) = V2 - Vi6
%
100
.,/
50
/
o
-1
/
/
/
/
V
-0,5
o
0,5 V
Figure 4b
719
TDA5660 P
Measurement circuits
10
10nF
H
9
10 j.lA or 0.3 j.lA
Figure 5
r--------------i
I~
~I
I
I
I
II 1213
I
I
I 14
I
I
IL ______________ I
~
TDA 5660 P
14
1nF
]
SOQ
623. 2S MHz
300 MHz
100 MHz
~
Refer to Characteristics Specifications
T
I
Adjusted to Calibration
Frequency
Remaining External Circuitry as Fig. 1
16
l
1nF
SOQ
6 dB
6dB
C
0
H 183-4
A
B
aRF=-10dBm
H
~
SOQ
Figure 6
720
TDA5660P
Frequency spectrum above the video carrier, measured at clamp VQ with a spectrum analyzer
,....
I"'"
12,5 dB
17 dB
-
BTO
1,07 MHz
FT 4,43MHz
TT 5,5 MHz
2* FT 8,8 MHz
2*TT 11 MHz
3*TT 16,5 MHz
Figure 7
8T - Video Carrier
FT - Frequency Carrier
n - Sou nd Carrier
721
TDA5660 P
Description of the measurement configuration to measure the noise voltage, video in sound
Audio Input
with 50 f!s Deemphasis
Measurement
Demodulator
Modulation
1----o-----lMeasurement Device
Audio Output e.g. FAM by R&S
e.g. AFM2 by R&S
Filter: 30 Hz-20 kHz
Detector: RMS · f f
Broadband Amplifier
20 dB e.g. OM 361
Fa. Philips
Test Board According
to Test Circuit la
atPin 1
FM sound input
270 mVrms
H
H
f--o Adjustment Voltage, Oscillator Adjusted to Ch39
Video input
1--'-V!!.lPJIP'--_--l
L...:.
FuBK or Other Test
Pictures.
S.G.
Video Generator
e.g. VG 1000 Fa.
Grundig
Sound Generator at Modulation Frequency fAF ~ 400 Hz
Figure 8
A signal of VAF rms = 270 mV and f = 0.4 kHz, corresponding to a nominal
deviation of 30 kHz, is connected to the sound input, and the demodulated
AF reference level at the audio measurement device is defined as 0 dB.
No video signal is pending.
Measurement: 1) The AF signal is switched off and the FuBK video signal is connected to
the video input with VVIDEODD =1 V. The audio level in relation to the reference
calibration level is measured as ratio a pls = 20 log (VFUBIJI (Vnominal)'
2) AF and video signal are switched off. The noise ratio in relation to the
AF reference calibration level is measured as signal-to-noise ratio aSIN'
Calibration:
722
TDA5660 P
Description of the measurement configuration to measure the oscillator interference FM
Broadband Amplifier 30 dB; e.g.
OM 361 from Philips
RF Input
Modulation
Measurement
1-----0---1 Device
e.g. FAM from R&S
Vo =10 V; Ch 30
Vo = 27 V; Ch 40
Vo-
Vq
Filter: 300 Hz-20 kHz
Detector: (P+P)/2
FM Setting
H
Modulator Test Object
according
to Measurement Circuit 1
Video Connection
Audio Output
Channel 1
Oscillograph for
Visual Control
Channel 2
t
+-_.....J
Ex.
Triggering
I--- + Vs Supply
H
Sound Generator
'VIO = 10 kHzSine Signal
VVID pp =
1V
Figure 9
723
TDA5660 P
Description of the measurement configuration to measure the total harmonic distortion
during FM operation of the sound carrier
Broadband Amplifier 30 dB; e.g.
OM 361 from Philips
Modulation
Audio
1-----1 Measurement Device r - RF
e.g. FAM from R&S
Filter: 30 Hz-20 kHz
Detector: (P+P)/2 or PEAK CCIR
with 50 IJ.s Preemphasis
Test circuit 1
or 2 for AM
Pin 9 Is Set at max. 5.5
MHz Signal at Output
by Connecting Vg = -3.9 V
Sound Input
t.
Vo = 0 V Connected; Oscillation Is Ended
VAFrms=1 V
Output
Harmonic
Distortion
e.g. Analyser
RKF 10 from R&J<;
f=0.05-12 kHz
Figure 10
724
Input
TDA5660 P
Description of the measurement configuration to measure the total harmonic distortion
during FM operation of the sound carrier
Broadband Amplifier 30 dB; e.g.
OM 361 from Philips
Modulation
1-..."",..--1 Measurement Device ~
RF
e.g. FAM from R&S
FM Range Measurem.
Filter: 30 Hz-20 kHz
Detector: (P+P)/2
Pin 9 Is Set at max.
5.5 MHz Signal
at Output
by Connecting Vg ~ -3.9 V
Test Circuit 1a
Sound Input
FM'"I
. .
VO ~ 0 V Connected, Oscillatoon Is Ended
VAF rms = var.
Output
AF Generator with
THDS;0.05%
e.g. CR-116
Figure 10a
725
TDA5660 P
Description of the measurement configuration to measure the sound and/or noise in video
during FM and/or AM sound carrier modulation
Modulation
, - - - - - - 1 Measurement
DeYice
e.g. FAM from R&S
Broadband Amplifier
30 dB e.g. OM 361
from Philips
Sound Generator
VAF (rms) = 1 V
fAF = 1 kHz
AM Sound
Input
Test Circuit 1
FM Sound Input
Sound
Generator
VAF (rms) = 1 V
fAF=1 kHz
Video Input
Video Signal
VVIDpp=1 V
f Y1D = 100 kHz
Sine Signal
Figure 11
Calibration:
AF signals are switched off; video signal is pending at the video input; device
to measure modulation set at AM is adjusted to video carrier; filter:
300 Hz ... 200 kHz; detector (P+P)/2; resulting modulation index is defined
as my=O dB.
Measurement: 1) Measurement of interference product ratio sound in video during FM
modulation of the sound carrier: AF signal is connected to FM sound
input; video signal is switched off; device to measure modulation is set
to AM; filter: 300 Hz ... 3 kHz; detector: (P+P)/2; a ratio of a s/p = 20 log
my/s/mV) is derived from the resulting modulation index my/s.
2) Measurement of interference product ratio sound in video during AM
modulation of sound carrier: AF signal is connected to AM sound input;
otherwise identical with measurement 1.
3) Measurement of signal-to-noise ratio in video without AM/FM modulation
of sound carrier: AF signals are switched off; video signal is switched off;
control voltage at pin 11 is clamped to value present during connected
video signal; modulation device is set to AM; filter: 300 Hz ... 3 kHz; detector:
RMS -12; readout in dB to reference level of calibration is as/po
726
TDA5660P
Description of the measurement configuration to measure the residual carrier suppression
Video
Measurement
Demodulator
e.g.AMF2
Test Circuit 1
Oscilloscope
A Voltage of V,2 = 0.4 V Is Connected to
Pin 12 for Setting Overmodulation
aV =2010g VRIVv (dB)
Superimposed 4.43 MHz Burst Signal
Video Signal Generator
VVIDpp=1 V
e.g. Tektronix 148
Adjust Cp in Circuit 1 and Dynamic Residual Carrier Suppression to Suppression Maximum.
Figure 12
727
TDA5660 P
Description of the measurement configuration to measure the video amplitude response
Measurement
Demodulator
e.g.AMF2
from R&S
Oscilloscope
Demodulated Video Signal
Test Circuit 1
aV = 2010g VminlVmax (dB)
Video Input
Video Signal Generator
VVID pp =1 V
e.g. PM5570 from Philips
Line Sync Signal
Trigger Input
Sine Generator
15 kHz-5 MHz Can
Be Wobbled
e.g. TM503 from Tektronix
Triggered by Line
Sync Signal
Figure 13
728
TDA5660 P
Static modulation characteristic of the FM sound modulator
kHz
300
TDA 5660 P
Q=25
~
33pF
II
II
-3
Qu
fTOSC
V1
Vz
-2
=25; RT =6.B K
= 5.5 MHz at .1V1/Z = 0 V
=
=
-300
Voltage at Pin 1
Voltage at Pin 2
V1 =7.5 V
Figure 14
Description of the measurement configuration to measure the 1.07 MHz moires
T
Spectrum Analyser
(e.g, 8566 A from HP)
-
12,5dB
54dB
17dB
:
FT
Vq
TT
FT
:
BT
TT
1--1,07 MHz~
Test Circuit 1
Video Input
Sound Generator
(Sine Signal)
f =4,43 MHz
VV1D pp = 250 mV: Frequency carrier level lies below the activation point of the video amplitude control and
has been set to provide a ratio of 17 dB with respect to the video carrier.
Figure 15
729
TDA5660 P
Modulation index during negative video modulation and/or the voltage at pin 12 versus
current at pin 12
v
100
\
\
\
75
\
\
\
\
/'
50
/
/
.....
,
/
'
.............
......
_-
0,8
0,7
--
-
V'2/M
-<.
.......... .......
0,6
0,5
50
150
100
~A
- - 112
Figure16a
Modulation depth is calculated as mD = (2 x m)/(1 + m) from the modulation index.
Prerequisite is a sine-shaped modulation,
mN = modulation index for negative modulation
m p = modulation index for positive modulation
If a resistor is connected to ground at pin 12 to adjust modulation depth, the resistor is
calculated as R'2/M = (V12IM)/ [,2)'
730
TDA5660 P
Modulation index during positive video modulation and/or the voltage at pin 12 versus
current at pin 12
mV
100
~
-100
//
/"
~
75
//
/,,/
~
////"-
/"
///
/'-.
/"
V12/M
//
/
~
~
///
50
450
Vi2/M
//
500
550
50
"
100
600
~A
---/12
Figure 16
Modulation depth is calculated as mo = (2 x m)/(1 + m) from the modulation index.
Prerequisite is a sine-shaped modulation.
mN = modulation index for negative modulation
mp = modulation index for positive modulation
If a resistor is connected to ground at pin 12 to adjust modulation depth, the resistor is
calculated as R12/M = (V12IM)/ [d·
731
TDA5660 P
Picture to sound carrier ratio versus dc voltage offset at pin 16
unloaded Q factor of resonant circuit Q u = 25, RT = 6.8 k; f = 5.5 MHz.
The picture to sound carrier ratio of 8 P/S
external voltage at pin 16.
=
13 dB was set via the loaded Q factor QL without
dB
20~--------~--------~--------'---------~
ap/S
!
-1.5
-1
__________L __ _ _ _ _ _ _ _
-0.5
0
~
OL-________- L________
~
10~--------4---------~~--------~--------~
0,5 v
Figure 17
To adjust the picture to sound carrier ratio, a component was used with a resistance of
typo 11.5 kQ at pins 17,18.
The loaded Q factor of the resonant circuit was derived from the internal resistance R17I18
connected in parallel with the external resistor Rs.
732
TDA5660 P
Measurement of the sound oscillator FM deviation without preemphasis and deemphasis;
1 kHz; modulation deviation, sensitivity (MAF )/(L1VAF ) = 0.38 kHz/mY; VAF = var;
detector (P+P)/2; AF filter 30 Hz to 20 kHz, measurement in accordance with CCIR 468-2
DIN 45405; test circuit 1a.
fAF =
kHz
10 3
5
Is
v-
1102
c
0
~
"a;
5
./
./
0
./
::i:
u..
V
101
5
./
.,......V"
/'
5
5
Voltage at Pin 1 -
5
V1 rms
Figure 18
733
TDA5660 P
Measurement of the sound oscillator FM deviation without preemphasis and deemphasis;
fAF = 1 kHz; modulation deviation, sensitivity (LlfAF)/(.WAF) = 0.38 kHz/mV; VAF = var;
detector (P+P)/2; AF filter 30 Hz to 20 kHz, measurement in accordance with CCIR 468-2
DIN 45405; test circuit 1 a
5
THO
110'
5
/
5
5
5
Voltage at Pin 1 -
Figure 18a
734
V, rms
T[)A 5550 P
Sound oscillator harmonic distortion without preemphasis and deemphasis;
AF signal routed in at pin 1; AF amplitude = 150 mVrms ; AF filter 30 Hz to 20 kHz;
detector (P+P)/2; measurement in accordance with CCIR 468-2 DIN 45405; test circuit 1a
r
5
1\
\
5
5
5
10 4
----------<:>
f sOlJ.nd
Figure 18b
735
TDA5660 P
Sound oscillator frequency without preemphasis and deemphasis;
AF signal routed in at pin 1; AF amplitude = 150 mV,ms; AF filter 30 Hz to 20 kHz;
detector (P+P)/2; measurement in accordance with CCIR 46'8-2 DIN 45405; test circuit 1a
5
f
I
5
5
5
~ fsound
Figure l8c
736
TDA5660 P
Sound oscillator frequency with pre-/deemphasisj
AF filter 30 Hz to 20 kHz; measurement in accordance with CCIR 468-2 DIN 45405;
test circuit 1; VAF = 1 Vrm •
THOf
1
I
10
jletector (P+P)/2
1
<:
.,0
'>'"
0'"
::;:
Detector CCIR
5
LL.
0
10
5
II II
10-1
10 1
5
\
5
5
~fsound
Figure18d
737
TDA5660 P
Description of the measurement configuration to measure the video signal control
characteristics and the dynamic signal suppression in video frequencies
Vs -12 V
Digital
Voltmeter
TDA 5660 P
7
r
8
10nF
33 kr!
C>----O
-3.9 V in Fig. 22
+Vs=12 V
25 k{l
Adjustment for Dynamic Signal
Suppression in Video Frequencies
Figure 19
738
TDA5660 P
Characteristic of the video signal control circuit
mV
V
=r::- -
90
,/
a) V13 rms = f (V1Q rms);
b) Vll = f (V1Q rms);
3
fmod = 100 kHz
V9 =3.9 V
Vll
Vll
!;;;;;;
I
:-....
tV13rms
70
60
o
o
100
200
300
400
500
600mV
+
700 mVpp
Figure 20
Static and dynamic mi:cer test with respect to balance characteristics
based on a typical component
mV
15
mV
+200
V13/15 =
.,.
7r
1'\
~
/
\\..
1\
o
+ 100
J
I
\ \..
5
1\
\
I
V13/1 5
V13rm ,
f (V9)
V13 rms = f (V9)
f= 10 kHz
j
o
""" 'II: r7
I
\ II \
\
1\
.""
-100
V13/15"-
I
I
0,5
-200
1V
Figure 21
739
-".TDA5660 P
Measurement of the static output impedance
,-----..-----o·+Vs
13
.1 VIS
ZIS= tHIS
.1 VIJ
Z13 = .1/IJ
12
II
--l,--;?l-----------I
--T-------I
:
I
I
I
I
i--.1v---i
I
I
I
I
I
I
I
I
9,5
I
I
13,5
- - V13 (V1S )
Figure 22
740
TDA5660 P
Output circuit S parameter
S Parameter
S'5
S13
H
I---{!
lnF
181
171
161
1I
15
1M
:=lnF
121
13
111
101
P
Typ. output capacity is approx. 1 pF
270·
180· -+-+++--t-HH-t-+--t"-CH-t-+-+++-+-+--'t-
90·
Figure 23
741
TDA5660 P
Oscillator section S parameter
Pin30r7
J
-
Lpin40rs
4
lnF lnF
1nFT ]'nF
~________~__ Optional
Pin 5 0 > - - - - - - 0 Pin 5
S"
Szz
270·
180·
---I--t-./-~-+++-H:-r:H-t--r-/H-;IT
90'
Figure 24
742
TDA5660 P
r
Application circuit 1
Signal Output
1nF
+Vs
u---~
Ls ... L9 Balun Transformer with
Ferrite Core
5.5 MHz
Sound Oscillator Circuit
33 pf
18
17
TDA 5660 P
22kfl
220 kfl
''''I
1
10"F
','pF
Reference 7.5 V
TO,SjJF
FMAF'"~l
I
7
8
10nf
H
9
1nf
H
2, 2 pF
3,9 pF
-nO.
~
Vs=9.5-13.5V
F~ B~~B4::
10nF
H
at Pin 2
+Vd
Channel 30 ... 40
VO/V 10 ... 28
743
TDA5660P
Application circuit 2
r
Signal Output
1nF
Ls .. ·L9 Balun Transformer with
Ferrite Core
5.5 MHz
+Vs
Sound Oscillator Circuit
RT 6.8kl'l
751'l Video
39pF
18
10~F~~O.5~F
17
16
13
15
12
TDA 5660 P
3
4
f--i
L,
10nF
220pF ]OnF
Vs =9.5-13.5 V
Reference 7.5 V
TO.5PF
FM AF Input
27PF~47PF~27PF
885058
47kl'l
",
10nF
47kl'l
J--f
Channel 3
744
9
8
+Vd
TDA5660 P
Application circuit 3
Ls ... Lg Balun Transformer with
Ferrite Core
5.5 MHz
Sound Oscillator Circuit
+Vs
RT 6.8 kll
La
33pF
18
L9
17
rOA 5660 P
4
2
220pF
220kll
r
7
5
Quartz
22kll
0
L111
L2211 pF
FM AF Input
9
10nF
H
10nF
18 pF
Reference 7.5 V
TO.5~F
8
Vs =9.5-13.5 V
Symmetrical Oscillator Layout
Harmonic Crystal
Operated in Series Resonance
TV IF 38.9 MHz
IF Filter Neosid
1) 2 Turns
2) 12 Turns
745
TDA5660 P
Application circuit 4
-IH
5.5 MHz
Sound Oscillator Circuit
Signal Output
1nF
L6
... L9 Balun Transformer
with Ferrite Core
+Vs
RT 6,8kQ
75Q
I
33pF
A
vider::.;
0,5 ~F
10flF
18
16
17
15
11
10
8
9
TDA 5660 P
4
2
220 kQ
220 pF
FMAFlnput
746
10nF
T.
TO,5 flF
7
120pF
22kQ
=
10nF
H
I
}Quartz
33 pF
Vs=9.5V-13.5V
to Pin 2
Residual Carrier Adjustment
If Required
TDA5660 P
Application circuit 5
~ Signal Output
5.5 MHz
Sound Oscillator Circuit
1nF
+Vs
Ls ... Lq Balun
Transformer
with Ferrite Core
RT6,8kO
I
33pF.
18
17
16
15
750
Videe
10 !IF
11·
10
0,5 !IF
8
9
TDA 5660 P
1
7
2
2:'~ 10".
I
'----1
T O,S
!IF
FM AF Input
Alternative 2:
. Series Crystal Oscillator with
Harmonic Crystal
Good Oscillating Characteristics
TV IF 38.9 MHz
T~;:
L
10nF
H
r47PF
toPin2
Residua! Carrier Adjustment
If Required
747
..,..
-..J
-LH Signal Output
I. 10nF
.CfJ
+Vs
1t
:c"2-
.1nF
~
Set
Modulation Depth
o::::I
Ls ... Lg Balun Transformer
with Ferrite Core
()
~.
c
;::;:
en
1nF
Dual Audio Stereo Signal
5.5+5.75 MHz
1:
I
5011
II
,
_
VHFf17/18 ~10mV,m
10~17 t" ~
:li'
~
~" LJ
LlY
I
TDA 5660 P
7
12
8
10nF
22kll
2.2pF
220p> i"OF
=r .
It
iV'~9.OV-13.5V
39 pF
.
'-----,.
T
o. 5flF
FM AF Input
H
-'-22pF
Dynamic
Residual Carrier Adjustment
If Required
47kll
10nF
H
47kll
U'I
C»
C»
o
Vd
Channel 30 ... 40
VON 10 ... 28
g
at Pin 2
"1:11
'J
Modulator for TV, Video and Sound Signals
TDA 5660 X
5020
The monolithically integrated circuit TDA 5660 X is especially suitable as modulator for
the 48 to 860 MHz frequency range and is applied e.g. in video recorders, cable converters,
TV converter installations, demodulators, video generators, video security systems, amateur
TV applications, as well as personal computers.
•
•
•
•
•
•
•
It
Synchronizing level-clamping circuit
Peak white value gain control
Continuous adjustment of modulation index for positive and negative modulation
Dynamic residual carrier setting
FM sound modulator
Picture carrier to sound carrier adjustment
Symmetrical mixer output
Symmetrical oscillator with own RF ground
I:'f) Low radiation
@ Superior frequency stability of main oscillator
61» Superior frequency stability of sound oscillator
o Internal reference voltage
Circuit description
Via pin 2, the sound signal is capacitively coupled to the AF input for the FM modulation
of the oscillator. An external circuitry sets the preemphasis. This signal is forwarded to a
mixer. At the output of the mixer the FM modulated sound signal is added to the video
signal and mixed with the oscillator signal in the RF mixer. A parallel resonant circuit is
connected to the sound carrier oscillator at pin 18, 19. The unloaded Q of the resonant
circuit must be Q = 25 and the parallel resistor Rr = 6.8 kQ to esnure a picture to sound
carrier ratio of 12.5 dB. At the same time, the capacitative and/or inductive reactance for
the resonance frequency should have a value of Xc "" XL "" 800 Q.
The video signal with the negative synchronous level is capacitively connected to pin 10.
The internal clamping circuit is referenc.ed to the synchronizing level. Should the video
signal change by 6 dB, this change will be compensated by the resonant circuit which is
set to the peak white value. At pin 12, the current pulses of the peak white detector are
filtered through the capacitor which also determines the control time constant. When pin 13
is connected to ground, the RF carrier switches from negative to positive video modulation.
749
TDA5660 X
With the variable resistor of R =00 .... 0 Q at pin 13 the modulation depth, beginning with
R = 00 and a negative modulation of m OIN = 80%, can be increased to m OIN = 100% and
continued with a positive modulation of m o/P = 100% down to m o/P = 88% with R = 0 Q.
The internal reference voltage has to be capacitively blocked at pin 2.
The amplifier of the RF oscillator is available at pins 4-8. The oscillator operates as a
symmetrical ECO circuit. The capacitive reactance for the resonance frequency should
be Xc '" 70 Q between pins 4,5 and 7,8 and Xc '" 26 Q between pins 5, 7. In order to
set the required residual carrier suppression, pin 10 is used to compensate for any dynamic
asymmetry of the RF mixer during high frequencies of > 300 MHz. The oscillator chip ground,
pin 6, should be connected to ground at the oscillator resonant circuit shielding. Via pin 4
and 8 an external oscillator signal can be injected inductively or capacitively. The
peripheral layout of the pc board should be provided with a minilTium shielding attenuation
of approx. 80 dB between the oscillator pins 4-8 and the modulator outputs 14-16.
For optimum residual carrier suppression, the symmetric mixer outputs at pins 14-16 should
be connected to a matched balanced-to-unbalanced broadband ·transfonller with excellent
phase precision at 0 and 180 degrees, e.g. a Guanella transformer. The transmission loss
should be less than 3 dB. In addition, an LC low pass filter combination is required at the
output. The cut-off frequency of the low pass filter combination must exceed the maximum
operating frequency.
If the application circuit according to figure 1, 2 is used, a multiplication. factor V/RF
(application) = VlRF (data sheet) 3.9 must be used to convert a 300 Q symmetrical
impedance to an asymmetrical impedance of 75 Q for the stated RF output voltage Vq of
the type specification in order to ensure a transmission attenuation of 0 dB for the balancedto-unbalanced mixer.
750
TDA5660X
Maximum ratings
Supply voltage
Current from pin 2
-12
Voltage at pin 1
Voltage at pin 9
Voltage at pin 10
V1
Vg
VlOPP
Capacitance at pin 2
Capacitance at pin 11
Voltage at pin 12
Voltage at pin 13
Voltage at pin 15
Voltage at pin 16
C2
Vs
ell
V12
V,3
V15
V16
min
max
-0.3
0
14.5
2
V
mA
V2 -2
V2 +2
-4
1
1.5
V
V
V
Remarks
0
0
-0.3
100
15
1.4
V2
V2
V2 -1.5
Vs
Vs
V2 +1.5
nF
IlF
V
V
V
V
-40
150
125
°C
°C
80
K/W
9.5
0
0
48
13.5
5
20
860
V
MHz
kHz
MHz
0
4
70
7
V2
Vs
°C
MHz
V
V2 =7 to 8 V
Vs = 9.5 to 13.5 V
Vs = 9.5 to 13.5 V
only via C
(max.lllF)
Vs = 9.5 to 13.5 V
Only the external circuitry shown
in application circuits
1 and 2 may be connected
to pins 3. 4. 6. 7. 17 and 18
Junction temperature
Storage temperature
Ts1g
Thermal resistance (system-air)
RlhSA
~
Operating range
Supply voltage
Video input frequency
Sound input frequency
Output frequency
fq
Ambient temperature
Sound oscillator
Voltage at pin 13. 15
fosc
V13 ,15
Vs
fVIDEO
fAF
TA
depending on the
oscillator circuitry
at pins 3-7
751
TDA5660X
Characteristics
Vs
= 11 V; TA =25°C
Current consumption
Ie
Reference voltage
V2
Oscillator frequency range fosc
Turn-on start-up drift
Llfosc
Frequency drift as
function of Vs
-.1fose
Video input current
at pin 10
Video input voltage
at pin 10
-110
Modulation depth
VVIDEOpp = 1 V; fVIDEO200 kHz sine signal
Output impedance
RF output voltage
Modulation signal in
neg. modulation
pin 12 open
Output capaCitance
mDIN
V10pp
mDfP
Z13;Z15
Vqrms
Figure
min
typ
max
12 =0 mA
0!S:12 !S:1 mA
External circuitry
adjusted to
frequency
TC value of
capacitor in OSC.
circuit is 0; drift is
referenced only to
self-heating of the
component
t =0.5-10 s;
TA ="Const.
Ch30
Ch 40
Vs -9.5-13.5 V
TA =const.
Ch40
C10!S:11J-F
1; 2
1; 2
22
7
48
30
7.5
40
8
860
mA
V
MHz
1;2
1;2
1; 2
0
0
0
-50
-200
-500
-500
kHz
kHz
5
-150
0
150
10
kHz
IJ-A
at coupling capac.
C!S:1 IJ-F
~.ak!S: ± 0.3 }LA
neg. mod.
pos. mod.
21;22
0.7
1.4
V
1; 16
2;16
75
83
80
88
85
93
%
%
static
Ch40
24
1b
10
2.5
3.5
5.5
kO
mV
25
0.5
2.0
pF
C13 -C 15
S parameter at pins
3,4 and 6, 7
RF output phase
«'3.15
RF output voltage
LlVq
change; adjustment
range
RF output voltage change LlVq
RF output voltage change LlVq
Oscillator interference FM
caused by AM modulation and
coupling of the modulator
output with the oscillator
resonant circuit;
VVIDEOpp = 1 V;
fVIDEO = 10 kHz; sine signal
Ch 30
Ch 40
752
Test conditions
26
140
f = 543.25-623.25
Llf-80 MHz
Ch 30-Ch 40
f = 100-300 MHz
f=48-100MHz
1
6
6
0
0
0
1; 9
1;9
0
0
180
5
7
220
degrees
1.5
1.5
1.5
dB
dB
dB
15
21
kHz
kHz
TDA5660X
Characteristics
Vs=11V;TA=25 D C
Intermodulation ratio
Harmonic wave ratio
aMR
aH
Harmonic wave ratio
Harmonic wave ratio
aH
aH
Sound carrier ratio
Color picture to sound
carrier ratio
ap/s
ap
All remaining harmonic
waves
a
Amplitude response of
the video signal
av
Residual carrier
suppression
Static mixer balance
characteristic
Dynamic mixer balance
characteristics
Stability of set
modulation depth
aR
Stability of set
modulation depth
Stability of set
modulation depth
Stability of set
modulation depth
LlV,3115
Vi3 rms
LImo
LImo
typ
Test conditions
Figure
fp+l.07 MHz
fp +8.8 MHz without video
signal 19, 20, 21 unmodulated
video and sound carrier,
measured with the spectrum
analyzer as difference between
video carrier signal level and
sideband signal level without
video and sound modulation.
fp +2fs
f p+3fs
Vq with spectru m analyzer;
loaded Q factor Q L of the sou nd
oscillator resonant circuit
adjusted by Rs to provide the
required picture to sou nd carrier
ratio of 12.5 dB; Rs = 6.8 kQ;
Q u = 25 of the sound oscillator
circuit.
1; 7; 15 54
1; 7; 15 35
75
dB
dB
1; 7
1; 7
35
42
48
48
dB
dB
1; 7; 17 10
1
17
fp +4.4 MHz (dependent on
video signal)
Multiple of fundamental wave
of picture carrier, without video
signal, measured with spectrum
analyzer;
f p/s = 523.25-623.25 MHz
VVIOEO pp = 1 V with additional
modulation f = 15 kHz-5 MHz
sine signal between black
and white
With adjustment at pin 9
Ch 30 ... Ch 40
Vg adjusted to LIV,3J,5
minimum
Vg adjusted to V,3 rms
minimum
Video input voltage changes
with sine signals
f = 0.2 MHz; LlVVIOEO pp = 1 V
± 3 dB; Ch 30 ... Ch 40;
Vs = 12 V; TA =const.
LImo
f=48 ... 100MHz
f = 100 ... 300 MHz
LImo
TA =0-60°C; Vs = 12 V
min
12.5
max
15
15
dB
dB
dB
1; 13
0
1; 12
32
21; 23
-100 0
21;23
0
1.5
dB
+100
mV
10
mV
±2.5 %
6
6
1
2
±2.5 %
±4
%
±2.5 %
753
TDA5660X
Characteristics
Vs
=11 V;
TA =25°C
Test conditions
Stability of set
modulation depth
Interference product
ratio sound in video;
sound carrier FM mod.
Signal-to-noise ratio in
video; sound carrier
unmodulated
Unweighted FM noise level
ratio video in sound;
FuBK test picture as
video signal
Unweighted FM noise level
ratio video in sound
Signal-to-noise ratio of
sound oscillator
Differential gain
Differential phase
Period required for peak
white detector to reach
steady state for full
modulation depth with
1 white pulse per half
frame with control in
steady state
754
Figure
min
typ
max
aS/P
Vs =9.5-13; 5 V;
TA=const
Ch 30 ... Ch40
1; 11
48
60
dB
aN/P
Ch30 ... Ch40
1; 11
48
74
dB
ap/s
Ch39
1a;8
48
54
dB
ap/s
Ch 39; test picture VU
G-Y;UN
Ch 39; color bar
Ch 39; uniform red level
Ch 39; uniform white level
Ch 39; test pattern
Ch 39; white bar
Ch39;bar
Ch 39; 20T/2T
Ch 39; 30% white level
Ch 39; 250 kHz
Ch 39; multiburst
Ch39;ramp
2;8
48
56
dB
2;8
2;8
2;8
2;8
2;8
2;8
2;8
2;8
2;8
2;8
2;8
1a;8
46
48
45
48
46
45
43
48
46
46
44
48
52
58
51
55
52
50.8
49
58
52
53
50
54
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
LImo
aSIN
Gdif
±2.5
measured with measurement demodulator,
video test signals
and vector scope
q>dif
t
Catpin11 =10!LF;
Ile.k~2 !LA
6
%
10
%
15
50
%
!L s
TDA5660 X
Characteristics
Vs =11 V; TA =25°C
Test conditions
fs/Osc
Unloaded Q factor
of resonant circuit
Q u = 25; resonance
frequency 5.66 MHz
Turn-on start-up drift
Llfs/oSC
Sound oscillator frequency
operating voltage
Llfs/Osc
Capacitor TC value
in sound oscillator'
circuit is 0, drift is
based only on
component heating
TA =const.;
fs/Osc = 5.5 MHz
Vs =9.5-13.5 V;
fs/Osc =5.5 MHz;
TA =const.; Q u = 25
19; 19a
V1 rms = 150 mV
1.
FM mod. harmonic distortion
THDFM
Audio preamplifier input
Z1
impedance (dyn.); FM operation
FM sound modulator, static
Llfs/Osc
modulation characteristic
FM sound modulation
characteristic (dynamic)
min
Video blanking
signal content is
uniform white level
Setting time for video signal
change from 0 Vpp to 1.4 Vpp
Setting time for video
blanking signal from 100%
white level to 42% grey level
with subsequent rise in grey
level to 71 % of video blanking
signal (due to decontrol
process)
Sound oscillator frequency
range
Figure
Llf M/LlV1
LlV1/2 = V1-V2 =±1V;
fs/Osc = 5.5 MHz;
Q u =25
typ
max
120
500
f.ls
2.25
5
s
7
MHz
5
15
kHz
5
15
kHz
0.6
1.5
%
kQ
4
200
1; 14
±210
±270
±330
kHz
la; lOa
0.3
0.38
0.46
kHz/
mV
755
13
-..j
$
~
()
;0\"
a.
Di"
ea
:a
iil
3
Oscillator Buffer Stage ~I-----------------,
VStab
Sound
Residual
Carrier
Adjustrn.
3
4
5
6
7
8
9
g
UI
(7)
~
><
TDA5660X
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Function
GND
AF input for FM modulation
Intenal reference voltage
Symmetrical oscillator input
Symmetrical oscillator output
Oscillator ground
Symmetrical oscillator output
Symmetrical oscillator input
Supply voltage
Dynamic residual carrier adjustment
Video input with clamping
Connection for smoothing capacitor for video control loop
Switch for positive and negative modulation
as well as for residual carrier control
Symmetrical RF output
GND
Symmetrical RF output
N.C.
Sound oscillator symmetrical input for tank circuit
Sound oscillator symmetrical input for tank circuit
N.C.
757
TDA5660X
Measurement circuit
+Vs
TDA 5660 X
2
22krl
4
3
7
8
H
I
10nF
L3
FM AF Reference
Input
10
10nF
5pF
0.5 11FT
9
7.5V
Vs - 9.5 ...13.5 V
39 pF
L,
BB50q27 PF
H4
2.7krl
47 krl
Channel 2
758
to Pin
3
Video IIF Ie with VTR Connection
and Quasi-Parallel Sound
TDA5830-2
DIP 22
Video IF section
Controlled AM broadband amplifier with synchronous demodulator, video amplifier, VTR input
and output, and AGC voltage generation for the video IF amplifier and tuner.
Quasi-parallel sound section
Controlled AM broadband amplifier with quadrature demodulator, sound carrier output, and
internal AGC voltage generation.
The TDA 5830-2 is especially suitable for application with black and white or color television
receivers and/or VTR systems with PNP/MOS tuners for TV standards with negative video
modulation and FM sound.
Circuit description
The video IF section is comprised of a 4-stage controllable AM amplifier, a limiter, and a
mixer for the synchronous demodulation of video signals as well as an amplifier for the
positive video output signal.
The positive video signal is used for gated control. In addition, the IC includes a standard
VTR connection via an external transistor. The delayed tuner AGC is generated by a threshold
amplifier driven by the control voltage.
The quasi-parallel sound section also includes a 4-stage AM amplifier, a limiter, and a
mixer for the quadrature demodulation of the 1st sound IF with subsequent sound carrier
output for the 2nd sound IF. The control voltage is generated by a peak value rectifier
from the 1st sound IF signal.
759
TDAS830-2
Maximum ratings
min
Supply voltage
VI
Max. de voltage
Max. de voltage
Max. de current
Max. de voltage
Max. de voltage
Max. de current
Max. de current
Max. de voltage
Max. de voltage
Max. de voltage
Max. de voltage
Max. de current
V2. 3
V5
V4
0
-2
15
VS• 7
Va. 9
lID
-Ill
V12
V13 . 14
V15 ,16
VIa, 19, 20
121
Junction temperature
Storage tem perature range
7j
Thermal resistance (system-air)
RthSA
Tst9
V5
0
-1
-1
-10
0
0
0
-1
-40
max
13
V
VI
VI
V
V
2
mA
VI
VI
V
V
3
3
mA
mA
VI
VI
VI
V
V
V
V
2
mA
150
125
°C
°C
55
KIW
12.6
75
70
V
V,
Operating range
Supply voltage
IF frequency
Ambient temperature
760
Vs
flF
TA
10.5
15
0
MHz
°C
c::;;r.
TDAS830-2
Characteristics
Vs =12 V; TA =25°C
Current consumption
Stab. reference voltage
Test conditions
min
11
V5/22
typ
max
95
6.7
7.0
rnA
V
Video IF
Control current for tuner
Tuner AGC threshold
Gating pulse voltage
Input voltage at Gmax
AGC range
IF control voltage
Video output voltage
Sync pulse level
DC voltage
V 13 =4 V; V15/16 =0 V
Output current
V12
V12
Vi 15/16
.1G
V13/22
V13/22
Vq11 pp
V 11I22
Video amplifier
(VTR playback)
0
4.0
-10
pos. gating pulse
neg. gate pulse
V11 pp =:3 V
G max
Gmin
RL =00
Vq 10 pp
V10122
to grou nd via R
to plus V 11 =7 V
VTR record. RL =
VTR record. RL =
V10/22
1 q10
1 q10
VTR recording
VTR playback
to ground via R
to plus V10 = V 1
Vvideo
V=V11IVg;
V10/22
4.0
V1
30
60
-4.0
60
0
4.0
3.0
2.0
00
5.3
-5.0
+2.0
2.0
00
V 1 -1.6
V 11I22
1q 11
1q11
VTR output voltage (neg.)
Sync pulse level
DC voltage
~3:$;5 V; ~5/16 =0 V
DC voltage V13 = 8 V
Output current
4.5
114
V4/22
rnA
V
V
V
IJ.V
dB
V
V
V
V
V
rnA
rnA
V
V
~-3.8
V 1 -O.9
V
V
rnA
rnA
-5.0
+1.0
3.0
Vg pp =1 V
Quasi-parallel sound
Sound carrier output voltage
Input voltage at Gmax
AGC range
Signal-to-noise-ratio
White/staircase signal
Black picture
V 21
Vi18/19
.1G
Vive=l mV
Vise =300 ~V
V 21 = V 21 -3 dB
V21 = V 21 ±3 dB
IEC 468
Peak weighting
mV
10
50
60
100
~V
dB
61
66
dB
dB
10
1
50
20
dB
kHz
kHz
mV
Test conditions
Video carrier/sound carrier
Modulation frequency
Frequency deviation
IF input voltage
761
TDAS830-2
Characteristics
Vs =12 V; TA =25°C
Test conditions
min
typ
max
Design-related characteristics
Input impedance
Zi18/19
Output impedance
Zq2/3
6.6/2
150
10
6.0
50
Zq6/7
Output resistance
Residual IF (fundamental wave)
Video bandwidth (-3 dB)
Intermodulation ratio
with reference to fcc
Output resistance
IF control voltage
R11
V 11
Bvideo
aiM
Rq21
V 20122
V20/22
kQ/pF
kQ/pF
kQ/pF
kQ/pF
Q
mV
MHz
dB
1.812
1.812
6.6/2
Zi15/16
sound color
interference
200
Gmax
G min
0
4
Q
V
V
Alignment procedures
a) Video IF
At a video carrier input level of V;5/16 rms = 10 mV and a superimposed AGC voltage of
V13 = 3 V, the demodulator tank circuit is preliminary aligned so that the demodulated video
signal ~1 pp reaches its maximum output level at the positive video output. Any suitable video
test signal can be used for modulation. Subsequently, the AGC voltage V;3 is reduced until
the video signal equals approx. 3 V (peak-to-peak). By fine-aligning the d~rnodulator tank
circuit, the maximum output level of the video signal is reached. The flat response characteristic of the demodulator ensures a non-critical alignment procedure.
b) QPS
At an input signal of V;8/19 rms = 10 mV, the demodulator tank circuit is preliminarily aligned
until a max. AM suppression of the demodulated video signal V21 is reached at the sound
carrier output. A video signal critical for the sound-interference ratio should be used for
modulation (white/staircase, FuBK). Subsequent fine-aligning is performed by measuring the
sound-interference ratio at the output of a FM demodulator and fine-aligning the demodulator
tank circuit for a max. interference ratio. If several sound carriers are used in a device, the
sound carrier with the lowest level should be used for alignment purposes.
762
TDAS830-2
Pin description
Pin
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Supply voltage
Demodulator tank circuit QPS
Demodulator tank circuit QPS
Tuner AGe threshold
Reference voltage
Demodulator tank circuit video IF
Demodulator tank circuit video IF
White level setting
VTR input
VTR output
Video output
Gating pulse input
AGe time constant video IF
Delayed tuner AGe
Video IF input
Video IF input
GND
QPS IF input
QPS IF input
AGe time constant QPS
Sound carrier output
GND
18
19
20
21
22
763
TDAS830-2
Block diagram
Tuner
SC
AGC
I1JlF
22
21
22onF
VTR
RIP
"iHor
1
20
12
<
2
22pF
11
3
7511
+Vs
764
WL
VTR
+Vs Video+
TDA5830-2
Measurement circuit
Tuner
AGC
Vi IF
VqSC
",,1,",1
~
------------------100Q
VVTR
1,,0"
100Q
Gating
Pulse
22nF
22
21
20
19
18
17
16
14
15
13
12
10
11
TDA 5830 - 2
2
3
4
6
22pF
8
22pF
WL
100nF
.Vs
12.5 Turns
CuLS 0.25 mm
Video Carrier
I
O",VREF
VREF
.
1470nFT
12.5 Turns
CuLS 0.25 mm
Video Carrier
VVTR
SOQ
VqVTR
Vq video
765
»
--.I
0)
10VTR
2 IF
61F
1
'C
~~OfSFE
1 5,5MHz
m
"2-
~.
100pF
:
~
I
O·
:::I
n
SAWG3203
n
J.pF
22 121 10
p
~~"i 1.
22
13
..li2~F
16
1=115 114
4
19
47kl1
470nF=l=
39kl1
~"
12
,
.
T
W1N4148
l¥"
18
113
;::;:
. 10 ~F
1
7
1l U""
16,
,~~F
15' 14
113
112
.'
SCL
rll'!,oSDA
TBA 130-2
22pF
100
nF
CVBS Input
lBT17
T.
TDA 5830-2
~1 ~3
47~FT
119
1
~220nF
r=
~i"
c
I
*,lN4148
-F 210
100nF F 210
Q7511
21
CVBSOutput
~7511
BC~.
CVBS
~~I1_
-I
g
31
18/321341101 133
4/512OT28
*) L ~ 10 Turns, 0,2 CuL, Q L = 25
*) STYROFLEX Capacitor
e.g. with Vogi Coil Assembly 5171200000
C1I
CD
.~
~
TDAS830-2
Demodulator tank circuit QPS
12.5 Turns/O.2 CuL
0 0 ~ 50
22pF
fa =38,9MHz;B=1,SMHz
2
To Limiter
and Mixer
Form Control Amplifier
Tuner AGe threshold and output
r---~----~----------o-------~---
1
I
1
8
9
1/
4
-../
13
1
1
...L
...J....
-,-
I
1
I
I
..L
I
1
I
1
1
i
I
1
I
J
I
/0 0
1
1
1
1
1
1
I
i
14
r---------~---~---+-~
I
~
J
J
...L
I
6
To
Tuner
J
J
...L
767
TDAS830-2
Reference voltage
,
5
VREF = 6.7 V± 5%
~--6--.-., i1oad:O;; 2 rnA
I
6
22
I
I
I
....I...
Demodulator tank circuit video IF
12.5 Turns/O.2 CuL
Qo ~ 50
22pF
f o =38.9MHz;8:1.5MHz
To Limiter
and Mixer
From Control Amplifier
768
TDAS830-2
Positive video output
11
AGe time constant video IF
V",6V
typo 6V
From Video
Amplifier
~ +Idischarge
f ldB '" 1MHz
13 ~-Icharge
---,
I
I
I
I
2mA
u1s
=!= 220nF
I
I
I
To Control
Amplifier
22
...L
From Gated Control
Pas. Video
769
TDA5830·2
Gating pulse input
12
12 kQ
S,6kQ
22
IF input video IF
IFinputQPS
V=6V
1kQ
1kl"1
15 (18)0----1--4--1(
16(1910----+----+---4::
2,2kQ
2,2kQ
1,SkQ
22O---------------~
770
TDAS830-2
VTR interface
2R
R
-.,
V::6V
I
I
I
I
I
800~A
I
I
I
10
13
+-----I
9
I _____ _
L
From Demodulator
AGe time constant QPS
i-I
t
I
I
I
I
I
I
I
I
-i=w;---i
Control
I
Amplifier
I
I
I
IL __
'--------.rnax. 7 rnA
I
r---~--020
t
To Control Amplifier
771
TDA5830-2
Sound carrier output QPS
200 \l
+----c:=:J---o21
1mA
AGe time constant QPS
Zero Carrier
Level
5.3 V
Pin 7 Open
T
Vvideo pp
Sync
Level
2.0 V
772
1
TDAS830-2
Measurement configuration
Spectrum
Analyser
(SAW 351 0)
(SAW 361 S)
Test signal: fvc => 38.9 MHz with test signal modulated with 10% residual carrier;
sound carrier -13 dB (transmitter side)
Intermodualtion ratio
a 1M = 20 I09
V.ldeo (f-1 MHz)
...,..,---"-'':''''::''''-'-'''='-V.ldeo (f - fSC - fCC)
The 50% IRE signal with ± 50% IRE color carrier corresponds to Cyan with 75% color
saturation.
773
774
Video IF IC with Quasi-Parallel Sound and AFC
TDA5835
DIP 22
Video IF section
Controlled AM broadband amplifier with synchronous demodulator, video amplifier, and
AGC voltage generation for the video IF amplifier and tuner.
Quasi-parallel sou!ld section
Controlled AM brQadband amplifier with quadrature demodulator, sound carrier output,
internal AGC volta!:je generation, and an AFC section which can be disabled.
The TDA 5835 is especially suitable for application with black and white or color television
receivers and/or VTR systems with PNP/MOS tuners for TV standards with negative video
modulation and FM sound.
Circuit description
The video IF section is comprised of a 4-stage controllable AM amplifier, a limiter, and a
mixer for the synchronous demodulation of video signals as well as an amplifier for the
positive video output signal. The positive signal is used for gated control and a threshold
amplifier to derive the delayed tuner AGC from the AGC voltage.
The quasi-parallel sound section also includes a 4-stage AM amplifier, a limiter, and a
mixer for the quadrature demodulation of the 1st sound IF with subsequent sound carrier
output for the 1st sound IF. The control voltage is generated by a peak value rectifier from
the 2nd sound IF signal. The quasi-parallel sound also drives the AFC section.
775
TDA5835
Maximum ratings
min
max
Supply voltage
VI
13
V
Max. de voltage
Max. de voltage
Max. de voltage
Max. de voltage
Max. de current
Max. de voltage
Max. de current
Max. de voltage
Max. de voltage
Max. de voltage
Max. de voltage
Max. 'dc current
V2. 3
Va
VI
V4 .
0
VI
V8
VI
0
-2
2
2
V
V
V
V
mA
V
mA
V
V
V
V
mA
150
125
DC
DC
55
KJW
12.6
75
70
V
MHZ
Junction tem perature
Storage tem perature range
Thermal resistance (system-air)
V5,6
V7
18
V9,10
-Ill
V12
V13 ,14,15
V16,18
V19 ,20
121
V8
VI
-1
-10
0
0
0
-1
3
7j
Tstg
VI
-40
: RthSA
VI
VI
VI
VI
Operating range
Supply voltage
IF frequency
Ambient temperature
776
Vs
'IF
TA
10.5
15
0
DC
TDA5835
Characteristics
Vs =12
V; TA =25°C
Current consumption
Stab. reference voltage
Test conditions
min
I,
V8J22
typ
max
102
6.7
134
7.0
rnA
V
Video IF
Control current for tuner
Tuner AGC threshold
Gating pulse voltage
114
4.5
V7I22
V,2
V ,2
pos. gating pulse
neg. gating pulse
V pp =3 V
Input voltage at Gmax
AGC range
IF control voltage
V; 1S/16
LlG
V,3/22
V,3/22
Gmax
Gmin
Video output voltage
Sync pulse level
DC voltage
V,3 =4 V; V,S/16 =0 V
Output current
Vq11
RL =00
pp
Sound carrier output voltage
Vq21
\II pc =
Input voltage at Gmax
AGC range
Signal-to-noise-ratio
White/staircase signal
Black picture
\11,8/,9
AFC output current
AFC
OFF
ON
5.3
-5.0
+2.0
±1
V
rnA
rnA
rnA
V,
-4.0
60
0
4.0
V,,/22
to ground via R
to plus 11" = 7 V
dildfO
11 kl1
21
= 47
100nF
Stop
15kl1
~"' •.• ==
TDA 6200
YrT1'1Q- ~l:
, J:, J:
22
g
3 ;:;:
~f11
4
~ c
330
1wF nF0
2
~
470nF
68kTI
I
a.§i.
.12V
VREf
47
47
~F
19
>
.12V
TDA 6600
1
14
LED Tone 1
LED Tone 2
--- rl:
3,9nF
~O
~F
24
2,2mH
~~
AF2
30
38
(1
1
13
~4
"0'
T
AFROutp.
18kSl 10'I F
-d:'
T
22nF
I~
22kl1
==
1SnF 13nF
I
-I
g
O'l
I\)
(Xl
w
o
o
814
Photodiode with Amplifier
TFA1001 W
MIN 6
The bipolar IC TFA 1001 W contains a photodiode and an amplifier. At its output (open NPN
collector), the TFA 1001 W supplies a current directly proportional to the illuminance. Another
pin permits a linearized characteristic curve at low illuminances and can be used to inhibit
the output.
Application
•
•
•
•
•
•
•
Exposure meters
Exposure control systems
Electronic flashes
Optical follow-up control
Smoke detectors
Linear optocouplers
Color identification
Features
•
•
•
•
•
•
High sensitivity
High output current linearity
Good spectral sensitivity
Low current consumption
Wide modulation range
Large operating voltage range
Pin configuration
RadiQnt-sensitive
area on the chip
Frequency
1
compensation
c::==::::j
Adjustment,lnhibit 2
c::===!
1===:::JV,tQb
2
I=====:J Output
815
TFA1001 W
Maximum ratings
Supply voltage
Output current
Power dissipation
Junction temperature
Storage temperature
Thermal resistance (system-air)
-40
15
50
200
100
85
V
mA
mW
°C
°C
250
KIW
Vs
Ptot
1j
T,tg
RthSA
Lower
IimitB
supply voltage applied to pin 5
816
Upper
limit A
10
Characteristics at Tamb = 25 °C,
Supply voltage
Current consumption at E. = 0 Ix
Ambient temperature (during operation)
Illuminance
Sensitivity in range
E. = 1 Ix to 1000 Ix
Output current at
E.=0.05Ix
E.= 1 Ix
E.=1000 Ix
E.=5000 Ix
Stabilized voltage at pin 6
Supply voltage dependence of
stabilized voltage V'tab
Temperature dependence of
stabilized voltage V'tab
Lower
limitB
Is
2.5
-10
Tamb
E.
0
S
2.5
Vs
Upper
limit A
typ
5
15
1
70
5000
V
mA
·C
Ix
7.5
\lA/Ix
c,
Ia
10
Ia
10
2.5
2.5
V'tab
1.2
..1Vstabh1Vs
..1V'tab/..1Tamb
0.25..
5
5
25
1.35
.7.5
7.5
1.5
\lA
\lA
mA
mA
V
2
mVIV
-0.3
mV/oC
TFA1001W
Photocurrent versus illuminance
10.
5
1--
I--
f
r-
-----
c--
I
5
I
iI
iJ
5
,
I
'I
I
5
i
V
5
f~~t:~nda,WL~~~,clI'Y
I
IJi
1
r=;
ex i~~~~~l~a~~~~!~;~
5
II
10-'
10. 2
5 10·'
5 10°
817
TFA1001 W
Possible applications of TFA 1001 Was light/current transducer
1) for operating voltage 2.5 to 15 V
+Vs
(2.515 Vl
TFA 1001 W
6
4 -fa
3
2) for low operating voltage 1.2 to 1.5 V
TFA 1001 W
6
3
~
+Vs
(lL1.5Vl
5
4-fo
3) for especially low illuminance down to 0.01 Ix
+Vs
(2.5. 15Vl
TFA 1001 W
5
4 -fa
In case of low illuminance (see characteristic: output current versus illuminance), the output
current can be balanced by means of the adjustment control R1• The lower range of the
output characteristic can be linearized even more by setting a dark current of about 5 nA.
818
TFA1001 W
Dynamic behavior
1MQ
TfA 1001W
6
2
4
The dynamic behavior can be influenced at connection 2 by connecting capacitors.
dB
+10
"-
-5
"',
""- 'I'
'I'-
[=10nF
-10
A= flf)
f v=lOlx
-15
f =0
,
"-
-20
"-
-25
5
10'
"
"
2 Hz
-f
Attenuation A =
10 (f)
10(f=0)
819
TFA1001 W
Inhibiting the output
s
~
3
5 +Vs
4
The output can be inhibited by connecting the balancing input with the stabilized voltage
(switch, PNP transistor, FEn.
820
TFA1001 W
Relative spectral sensitivity
versus wavelength
%
100
\,
(
II
60
/
40
/
/
1\
\
\
V
\
1
20
\
o
600
400
BOO
-it
1000
nm
Relative output current
versus ambient temperature
in range Ev = 1 Ix to 1000 Ix
Output current
versus supply voltage
1.4
1.0
-~
0.8
BO
~
~
60
40
0.6
20
o
o
-20
20
40
60
80
--Tomb
100 .(
o
2
4
6
8
10
n
~
~
V
-Vs
821
TFA1001 W
Application examples
Simple threshold switch with TAB 1453 A op amp
The illustration shows a simple threshold switch as can, for example, be used in cameras to
change the aperture or indicate the illuminance. Operational amplifier TAB 1453 A serves as
comparator. It has a PNP input and is able to operate at very low supply voltage.
The output is an open collector which can switch currents up to 70 mA.
Since the stabilized voltage at pin 6 is used as reference voltage, the circuit is highly independent of the supply voltage.
822
TFA1001W
ShuHer speed or exposure control
Vs 125,15V)
1.35 V
TFA '001 W
6
10Mn
P
10kn
2
3
~
[
4
The illustration above shows a light/time control which can, e.g. be used to control the shutter
speed in cameras or for exposure time control in enlargers. This circuit operates also largely
independently of the supply voltage. A further essential advantage is, that for the major part
of the exposure time the comparator input current is insignificant as the corresponding input
transistor remains fully off-state. By means of potentiometer P, the operating range can be
extended to lower illuminance values. Opening the switch starts the exposure, and capacitor C is charged from pin 4 of the photo IC. The comparator switches if the voltage Vc falls
below the reference voltage determined by resistors R1 and R2 . The relationship between
illuminance and time is defined by capacitor C and precision adjustment is possible by
means of V1; V" however, must not become less than 0.4 V.
823
TFA1001 W
The dark current may be set in the circuit by means of potentiometer P. For this purpose,
capacitor C is removed. P is then adjusted in darkness such that the output of the comparator
is just blocked. Capacitor C is then inserted. (See illustration below).
Comparator
output voltage
Angle of rotation of P
Final setting
Schematic circuit diagram for an electronic flash control
1MQ
3
~
5
[
Rl
4
to flash
disconnection
R2
TFA 1001 W can also be used for electronic flash control. It must, however, be ensured that
the illuminance does not exceed 5 klx; use a grey filter if necessary. To be able to control very
short times, it is useful to connect an additional capacitor to pin 1.
824
TFA1001W
Comb~ed aperture and exposure control
TFA 1001 W
Shutter R,
contact
5
3
Shutter
4
Aperture
switch
The aperture and exposure control may be combined, with the information for aperture
switching being taken from the total current of the photo Ie (voltage drop at R5).
Aperture follow-up control for cine cameras
r-------------------~------------~--o+~
1.3SV
TFA 1001 W
...1
2
3
R3
~
R1
5
4
The op amp compares the voltage drop at R3 , generated by the photoelectric current, with
a reference voltage derived from the stabilized voltage, and controls the aperture via motor M.
825
TFA1001W
Ught/frequency transducer
+\15
2.5V,"SV
15n~
K22 y'okQ [ 12kQ [ lHQ
"
~
10HQ
2
~
~
~+4
150Q
10kQ
)lkQ
ln~
~
)lkQ
I7BAW 76
Sensitivity: approx. 1;100 Hz/Ix
Range:
4 Hz to 400000 Hz
•
•
•
•
•
High resolution
Fully temperature-compensated
Wide operating voltage range
High operating voltage suppression
Wide dynamic range (5 decades)
Particularly suitable for digital processing.
826
2.7pF
.
Ji
-.1 TFA 1001W i.
-1
l.¥
-roo
lee 177
-
~-
25kQ
[)lkQ
=
I
3.3kQ
2 ....... ~AW76
•
6
TAe 1453 5
3_
/4
[ 6SQI
5.6
kQ
I
r
1~d.
Output
l~
~
""-"-l
TLB4902 F
Integrated Hall-Effect Switch
for Alternating Magnetic Field
Preliminary data
Plastic Flat Pack
The Hall-effect Ie TLB 4902 F is a static contactless switch operated by an alternating
magnetic field. The outputs are switched to the conducting state by the south pole of the
magnetic field and are blocked by its north pole.
The Ie is particularly intended as rpm sensor in consumer applications or as commutation
sensor in brushless dc motors.
Features
•
•
•
Low switching thresholds
Miniature plastic package
Suited to low cost applications
Pin configuration
Sensor Position
-.
~
0
~
-t~
3_1_
Pin description
Pin
Symbol
Function
1
Vs
2
3
GND
Supply voltage
Ground
Output
Q
I
~~1 ~a
Vs GND
Dimensions in mm
827
TLB4902F
Block diagram
~ 1~---------------.
~-------i
Schmitt
Trigger
Amplifier
GND2~--------------~------~-------------------
828
3 Output
TLB4902 F
Maximum ratings
TA =70°C
Supply voltage
Output current
Junction temperature
Storage temperature
Thermal resistance
system-air
Flux density
Output voltage
BBoN
Ia = 16 mA
Ia=5 mA
Ia=5 rnA
B Hy
tHL
min
mA
°e
typ
max
17
25
mT21
mT
mT
mT
5
15
10
mT
Il A
2
3
5.5
6.5
0.4
1
1
mA
mA
2
-17
-25
2
TA
Va sat
Test
circuit
V
=25°e
2
0.3
0.5
V
Il s
Il s
Reliability and life time of the IC are assured as long as the junction temperature does not exceed 125 'C. Though
operation of the IC at the given max. junction temperature of 150 'c is possible a continuous operation at this rating
could nevertheless impair the reliability of the IC considerably.
1) The magnetic parameters are specified for a homogenous magnetic field at the sensor center as per fig. 3
2)1mT=10G
829
TLB4902F
Measurement circuits
8
10MQ
Figure 1
8
1-=--+-........- - 0 Va
Figure 2
Figure 3
830
TLB4902F
Application circuit
For optimum efficiency of the integrated overvoltage protection, it is suggested, that a
resistance Rs of approx. 100 Q be provided in the component's power supply to limit
the current.
Figure 4
Pulse diagram
I
I
I
I
I
;--r----[BOrF
I
va I
tI
I
-f
I
I
I
I
I
I
I
I
I
I
I
I
:
I
I
L
I
11
_f
Figure 5
~ux densi~=*=Q
L
B>BoN
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.........
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,
,.--,<:;
842
......
• 't
.........
=~
•.'
............rI
r
•
TLE 3101
Schematic circuit diagram for motor control using TLE 3101
The tachogenerator provides a voltage which is rectified and stabilized, and then fed to
input Vcontrolo
:;(1<1
.c
0...
?1
~
Cl?
,....;;:....,
?
....
N
c~
r
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/,
~1
'-
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OJ
~
>
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";;:
"0
UJ
+
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"c,
0
--'
rlH
~.
(!) :>,.8
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--;,......,
J'
N
cJ
I
A
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d
e
~
~
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V1
c., ....
£:
0
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:..
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·-U--I
5
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Z
:z
>-..,
>-
.:1
~
Ak~
...£
Vl~
:>.
""
..,
~H
'"
"',..,
Vl
I
....
I
I
In
IU
i5.
a.
:::J
~:::
VI
OJ
CI
E
>
"0
........
;:
'";!
L~
\!!
~
~
-
.....
-1
~
\ ..
:2
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:§;:
;:!:
~
r
I
843
844
TLE 3102
The TLE 3102 with on-chip op amp for external use is particularly suitable as a speed
controller with P, PI, or PIO characteristic; the op amp serves as adjustable gain amplifier.
An actual value which is proportional to speed can be formed by rectification of the tacho
amplitude.
Pin configuration
Pin No.
Function
Pin No.
1
2
3
4
5
6
7
Ground
Triac trigger output
Rs
8
9
10
11
12
13
14
Cs
Output Q 1, op amp
- input op amp
+ input op amp
Function
Vs
Vl
:l:
~
ci'
,.;::::....,
~
VI
1'1
N
.~
r--'--
...
G/
>
'i:
'0
+
v
'c,
0
.....
In
.
IU
a
e
~'"
~'l
-
.L
'7
...r:=t- -I
'---
'-''"
....
.c
"-
~
0
0
-
i1:1
,...,
II
~
u
Z
>III
II
,..z
U
VI
~
CD
.£
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>.
Ci.
...:t
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0.
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CI
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;g
0
or-
m
,~
r:;:
>
'"
i
UJ
-l
~
~
w
~
~
r-
850
'"
03
n'u.
TLE 3104
Current synchronization in case of inductive load control using TLE 3104
Particularly in case of phase control of inductive loads, such as transformers and shadedpole motors, there is a risk of half-wave operation as a result of the phase shift between
voltage and current. In order to avoid this condition, the synchronization resistor is connected to A 2 of the triac (this method cannot be applied in the event of severe brush
sparking of the motor).
TlE 3104
I
7 VREF
I
l
"I
100kQ
~
'Ct
Voltage supply
Sawtooth
j I
..
loglc+drlver
II
1
lfo~
R,
11011
I
145Vr
.L
Vs
5
1
~ 100pF
16V-
51 k Q
R,
18 kl1
1N 4005
0,
SYNC
8
180 kQ
Rs'lll.(
Rs
3
21nF
[s
V..,max
4
6
T
TXD
10K~~ ~1
1.1 Mil
~
=;: ~o1tt_
15011
1W
t
'"
0
~
:;
1
Notes:
The pulse width selected for the trigger pulse must be so great that the triac reaches its
holding current, even with a great phase angle (critical: positive half-wave). For this reason,
it may be necessary to select a lower value for the ac line series resistor.
The sync pulse must be at least twice as wide as the trigger pulse (see also page 323 and
page 327/para. 4).
851
852
DC Motor Driver
TLE 4201 A
TLE 4201 S
DIP 18
SIP9
The TLE 4201 IC is a dual comparator that is particularly suitable as a driver for reversible
dc motors and may also be used as a versatile power driver.
The push-pull power-output stages work in a switch mode and can be combined into a full
bridge configuration.
The driving of the comparators may be analog in the form of a window discriminator, or it
can be accomplished very simply with digital logic.
Typical applications are follow-up controls, servo drives, servo motors, drive mechanisms,
etc.
Features
•
•
•
•
•
•
•
•
Max. output current 2.5 A
Open-loop gain 80 dB typo
PNP input stages
Large common-mode input-voltage range
Wide control range
Low saturation voltages
SOA protective circuit
Temperature protection
The TLE 4201 IC comes in two different packages: with the SIP 9 package it is possible to
remove the heat by way of a cooling fin to a suitable heatsink, whereas with the DIP 18-L9
package the pins 10 through 18 are thermally linked to the chip and provide for heat dissipation
by way of the circuit board.
853
TLE4201 A
TLE 4201 S
Block diagram
Supply
5
3
J95kr2
~
Inputs
OdB
~1
2
Divider
potential 6
~
Amp 1
v(
Power
limiter
and
temperature
protection
TLE 4201
------<
~
o
~"-.t Amp 2
Inputs
dB
BOdS
V
/
]87kr2
4
GND
Figure 1
854
1 Output Q1
9 Output Q2
TLE4201 A
TLE4201 S
Pin configuration
TLE4201 A
TLE4201 S
Pin No.
Pin No.
Function
1
1
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
Output of 1st amplifier
Inverting input of 1st amplifier
Non-inverting input of 1st amplifier
Ground
Supply voltage
Divider potential
Non-inverting input of 2nd amplifier
Inverting input of 2nd amplifier
Output of 2nd amplifier
Ground; to be connected to pin 4
10 to 18
Circuit description
The Ie contains two amplifiers featuring a typical open-loop voltage gain of 80 dB at 500 Hz.
The input stages are PNP differential amplifiers. This results in a common-mode input voltage
range from 0 V to almost the value of Vs , and in a maximum input differential voltage of I Vs I.
To obtain low saturation voltages, the sink transistor (lower transistor) of the push-pull AB
output stage is internally bootstrapped. An SON protective circuit protects the Ie against
motor short circuits and ground short circuits. An internal overtemperature protection protects
the Ie against overheating in case of failure due to insufficient cooling or overload.
For logic control, a divider potential of approx. Vs/2 is available at pin 6 (see application
circuit 2). This makes the Ie particularly suitable for digital circuits, as power driver.
Application
Figure 2 shows a window discriminator operation with the control voltage VI.
The window within which the motor is to stop is set by R2 .
Figure 3 shows driving by logic inputs A and B. The motor is controlled according to the
following truth table.
B
Output
L
L
L
H
H
L
H
H
Motor stopped (slowed down)
Motor turns right
Motor turns left
Motor stopped (slowed down)
A
855
TLE4201 A
TLE4201 S
Application circuits
Operated as window discriminator
~-------+-------------------o+~
5
51kQ
[
100nF
9
Digital control
lor input signals applies: H ~ 0.6 Vs
L~0.3 Vs
~--------+-~------a+Vs
,5
A 0-___-=3+_-1
2
6
TLE 4201
B 0-_+-..!.7+_-l
9
8
Figure 3
856
.M
12V I O.3A
TLE4201 A
TLE4201 S
Maximum ratings
Tease =
Upper
limit A
Lower
IimitB
-35°C to 85°C
Supply voltage
Supply voltage (I!> 50 ms)
Output current
Voltage of pins 2. 3. 6. 7. 8
Voltage of pins 1. 9
Junction temperature
Storage temperature
10
Thermal resistance
TLE 4201 S: system-air
system-case
TLE 4201 A: system-air1)
system-PC board1)
150
125
V
V
A
V
V
°C
°C
65
8
60
44 1)
K/W
K/W
K/W
K/W
17
V
°C
dB
25
36
2.5
Vs
Vs
V
V
7j
-0.3
-0.3
Tstg
-55
Vs
R thJA
R thJC
RfuJA
RthJA1
Operating range
Supply voltage
Case temperature
Voltage gain
(at negative feedback with external components)
Vs
Tease
Gv
3.5
-35
25
85
~
Characteristics
Vs =13 V. Tease = 25°C
Test
conditions
Supply current
Open-loop voltage gain
Input resistance
Saturation voltages.
source operation
RI
sink operation
VQ20
Rise time of Va
Fall time of Va
Turn-on delay time
Turn-off delay time
Input current
(pins 2.3.7.8)
Input offset voltage
f,
ff
fon
foff
Is
Gvo
Va10
II
VIO
Lower
IimitB
Figure 4: S = 1
f=500 Hz
f= 1 kHz
1
Figure 5:
~
1
Ia=0.3A
1
I Q = 1.0 A
2
IQ =-0.3A
2
I Q =-1.0 A
Figure 4 and 6
Figure 4 and 6
Figure 4 and 6
Figure 4 and 6
Figure 5
V2•3, 7,8- 0
Figure 7
-20
typ
Upper
limit A
mA
dB
20
80
5
30
1.0
1.2
0.35
0.7
1.5
1.5
3.0
1.5
1.1
1.6
0.5
1.0
V
V
V
V
!-Is
!-Is
!-Is
!-Is
1,5
3.0
20
!-I A
mV
MQ
1) see figure 8
857
TLE4201 A
TLE4201 S
Test circuits
+ Vs
5
1
00 IJ F
2
SOOQ
o
1
500Q
r
OOnF
220nF
f-i
3
6
lSQ
Va
TLE 4201
9W
8
9
1~
I
f---;
7
220nF
51kQ
Figure 4
+Vs
5
lOOIJF
1
2
6
~~ . _.~2
TLE 4201
~1
lOW
8
9
JV
Q2
4
L _________ _
858
I
I
I
I
7
Figure 5
OonF
Val
Sl
2
r
:
~~~~~~±~~~~~~~~_J
TLE 4201 A
TLE 4201 S
Pulse diagram
0.5 VI
/
\
/
\
v
0.9 Va
Va
0.5 Va
f
/
0.1 Va
/
\
/I
-.J
-
ton
tr -
l-
-
-
toff
1\
1\
tf
L
l-
Figure 6
859
TLE 4201 A
TLE4201 S
Test and measurement circuit
+ VS/2
4.9SkQ
1
S
1100 x
2
Vro
VIO
t
free
TLE 4201
7
VIa
~
9
8
1100 X VIO
4
4.9SkQ
lOOIlF
SOQ
SOQ
- VS/2
Figure 7
860
I
TLE4201 A
TLE4201 S
Thermal resistance of TLE 4201 A
Thermal resistance, junction-air, Rth JA 1 (standard) versus side length I of a square copperclad cooling surface (35 11m copper plate)
Rth JA
0) - 60 KJW
Tamb:S; 70 0 e
Pv-1 W
(/-
substrate vertical
circuit vertical
static air
1.0
~----~----~
0.6
I------J-...----~
RthJAlIl1
RthJAII=OI
f
o
Figure 8
so
100 mm
1-
861
862
Integrated Hall-Effect Switch
for Alternating Magnetic Field
TLE4901 F
TLE4901 K
Preliminary data
The Hall-effect Ie TLE 4901 is a static contactless switch operated by an alternating magnetic
field. The outputs are switched fu the conducting state by the south pole of the magnetic
field and blocked by its north pole.
The Ie includes an integrated overvoltage protection against most of the transients occurring
in automotive and industrial applications.
The Ie is particularly intended as rpm sensor or shaft encoder. The Ie along with a multiple
pole ring magnet is especially suited to high-speed applications: speedometer, pickups,
rpm indicators, angle indicators, e.tc.
Features
•
•
•
•
Low switching thresholds
High interference immunity
Overvoltage protection
Large temperature range
863
TLE4901 F
TLE4901 K
Pin configurations
TLE4901 F
TLE4901 K
Sensor Position
Q
Q
VsGNDQ
Dimensions in mm
Pin description
TLE4901 F
TLE4901 K
Pin
Symbol
Function
Pin
Symbol
Function
1
Vs
GND
Q
Supply voltage
Ground
Output
1
2
3
Vs
Q
GND
Supply voltage
Output
Ground
2
3
864
TLE4901 F
TLE4901 K
Block diagram
VI 11--_---,
GND
.---_---13 Output
2~~~~~-------------+-------------------·--~
Protection
Circuit
Protection
Circuit
865
TLE4901 F
TLE4901 K
Maximum ratings
TA
=-30 to 125°C
Supply voltage
Output current
Junction temperature
Storage temperature
Thermal resistance
system-air
Flux density
Output voltage
BBoN
10 -10 mA
la- 1OmA
10 -10 mA
2
min
typ
max
15
15
10
mT3)
mT
mT
mT
mT
mT
mT
mT
IJ.A
13
14
0.4
1
1
mA
mA
V
IJ.s
IJ.s
20
22
25
-20
-22
-25
2
4
An optimal reliability and life time of the IC are assured as long as the junction temperature does not exceed 125°C.
Though operation of the IC at the given max. junction temperature of 150°C Is possible a continuous operation at
this rating could nevertheless impair the reliability of the IC considerably.
I) Thermal resistance of TlE 4901 K depends on type of mounting.
2) The magnetic parameters are specified for a homogenous magnetic field at the sensor center as per fig. 3.
3)lmT-l0G
866
TLE4901 F
TLE4901 K
Measurement circuits
B
Figure 1
110
,
eDt
1
--
2
~----oV
"
1
Figure 2
Figure 3
867
nE4901 F
TLE4901 K
Application circuit
i-=--+--+---o Vc
For optimum efficiency of the integrated overvoltage protection, it is suggested that a
resistance Rs of approx. 1000 be provided in the component's power supply to limit the
current.
Figure 4
Pulse diagram
I
I
-r-----
-I
I
IBor
I
i
I'I~
figureS
868
L
-I
TLE4903 F
Integrated Hall-Effect Switch
for Unipolar Magnetic Field
Plastic Flat·Pack
Preliminary data
The integrated Hall-effect switch TLE 4903 F is a contactless "normally-off" switch operated
by a magnetic field. The open collector output is switched to conducting state by the south
pole of the magnetic field.
The Ie is provided with an integrated overvoltage protection against most of the transients
occurring in automotive and industrial applications.
Features
•
•
•
•
Low switching thresholds
High interference immunity
Overvoltage protection
Large temperature range
Pin configuration
Sensor Position
~
0
~.
-t~
3_1_
Pin description
Pin
Symbol
Function
1
Vs
GND
Supply voltage
Ground
Output
2
3
Q
I
~~11
Vs GNOQ
Dimensions in mm
869
TLE4903 F
Block diagram
V,11--......---,
GND
2r-~~~~------------~-------------------~--~
Protection
Circuit
870
r----.-----j
Protection
Circuit
3 Output
TLE4903 F
Maximum ratings
TA =-30 to 125°C
Supply voltage
Output current
Junction temperature
<70000 h
Storage temperature
Thermal resistance
system-air
Aux density
Output voltage
min
max
30
40
150
V
125
°C
240
K/W
Vs
-1.2
10
7j
-40
Totg
-55
R thSA
B
Va
-00
mA
°C
+00
30
V
30
25
125
mA
°C
Operating range
Supply voltage
Output current
Ambient temperature
Vs
10
TA
1
43
•
-30
V
Characteristics
Vs -14 V; TA =-30 to 125°C
Test conditions
Magnetic flux densityl)
Operate point
Release point
BON
BOFF
Hysteresis
BON-BoFF
Output leakage current
BHy
Supply current
Is
Output saturation voltage
Rise time
Fall time
tLH
10Ik
VOoat
tHL
TA -Oto70°C
TA --30 to 100°C
TA --30 to 125°C
TA -Ot070°C
TA --30t0100°C
TA --30 to 125°C
Test
circuit
2
2
2
BBoN
10 -30 mA
2
10-10mA
10 -10 mA
min
24
18
17
17
11
10
7
typ
max
46
52
53
31
37
38
15
mT2)
mT
mT
mT
mT
mT
mT
10
I-IA
13
14
0.4
1
1
mA
mA
V
I-Is
I-Is
Reliability and IIle time 01 the IC are assured as long as the Juncllon temperature does not exceed 125 ·C. Though
operation 01 the IC at the given max. Juncllon temperature 01 150·C Is possible, a continuous operation at this rating
could nevertheless impair the reliability 01 the IC considerably.
1) The magnetic parameters are specilled lor a homogenous magnetic field at the sensor center as per Ilg. 3.
2) 1 mT-l0G
871
TLE4903 F
Measurement circuits
B
Figure 1
B
Figure 2
Figure 3
872
TLE4903 F
Application circuit
Vs
For optimum efficiency of the integrated overvoltage protection, it is suggested that a
resistance Rs of approx. 100 Q be provided in the component's power supply to limit the
current.
Figure 4
Pulse diagram
I
I
I
I
I
I T-----
IBT
I
I
I
I
I'H
I
I
I
I
I
I
I
I
-t
I
I
I
I
L
_t
FigureS
873
874
TUA 1574
FM TunerlC
DIP 18
Preliminary Data
The TUA 1574 has been designed as monolithic integrated tuner with strictly symmetrical RF parts
for use in car radios and home receivers. In addition the Ie provides a pre-stage control by means
of narrow and wideband information and IF post amplification.
Features
• double-balanced mixer
• AGe generation
• strictly symmetrical RF parts
• Stand-by switch
• decoupled counter output
Description of function and applications
Description of functions:
The TUA 1574 has been designed as a monolithic integrated tuner with strictly symmetrical RF
parts for use in car radios and home receivers. In addition the Ie rovides a pre-stage control by
means of narrow and wideband information and an IF post amplificication_
double-balanced mixer
AGe generation
o strictly symmetrical RF parts
• stand-by switch
• decoupled counter output
o
o
Description of applications:
The TUA 1574 is especially suitable for use in car radios and home receivers with pre-stage control and distributed IF selection_
Description of circuitry:
The integrated circuit includes an oscillator with symmetrical input, buffered output and a double balanced mixer for frequency conversion. The resulting IF is post-amplified in a linear IF driver_
The AGe stage integrated for pre-stage control generates combined wide and narrowband information. The Ie also includes a reference voltage source and a stand-by switch_
Maximum Ratings
Exceeded maximum ratings cause irreversible damage to the Ie.
Pas.
1
2
3
4
5
Maximum rating for
ambient temperature
Tamb = + 25°C
Symbol
min
max
-0.3
Supply voltage
+13.5
V1s
Mixer
+25
V16, V17
-0.3
Stand-by switch
+ 13.5
V1l
Reference voltage
-0.3
+7
Vs
Currents: all pins are short-circuit protected against ground.
unit
v
V
V
V
875
TUA 1574
Functional Range
Within the functional range, the IC operates as described; deviations from the characteristic
data are possible.
Pos.
1
2
functional range
Symbol
min
max
unit
Supply voltage
Ambient temperature
V'5
7
Tamb
-25
12
85
V
°C
Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit.
Typical characteristics specify mean values expected over the production spread. If not stated
otherwise, typical characteristics will apply at tamb =25°C and Vs 58.5V.
Pos.
Parameter
Symbol
Current Consumption
(without mixer)
Reference voltage
1,5
2
Mixer
3
Third order
4
Noise figure
5
Mixer gain
Oscillator
6
DC characteristics
7
DC characteristics
Interference
8
9
Output signal 750
10
Output signal open
11
Output impedance
Control voltage generation
12
Control voltage
for prestage
13
Output current
Measurement
circuit
Min
Typ
Max
Unit
14
23
28
mA
Ip3
F
V
V7, Vs
UB
M
4.2
V
115
11
14
dB/JlV
dB
dB
1.3
2
2.2
V
V
25
Vg
Rg
V,s
0.5
Hz
MV.ff
110
2.9
mVelf
(VP-0.3)
0.3
-/,s
50
I,s
2 ... 5
V'2
500
kO
V
JlA
(V3=Oor V,2=550V
and V,s = Vp/2)
14
Output current
(V3 =2V and V'2 =1V)
15
Narrowband-control
threshold when
V3=2V)
876
mA
mV
TUA 1574
Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit.
Typical characteristics specify mean values expected over the production spread. If not stated
otherwise, typical characteristics will apply at tamb =25°C and Vs 58.5V.
Pes.
16
Parameter
Symbol
Wide band control
threshold when
V12=0.7V
Measurement
circuit
ViHFEMK2
Min
Typ
Max
Unit
19
mV
1.2
3.5
300
13
300
3
30
6.5
V
V
Linear IF amplifier
17
18
19
20
21
22
23
24
25
26
Input DC voltage
Output DC voltage
Input resistance
Input capacitance
Output impedance
Output capacitance
Voltage gain
Noise figure
at Rs=300n
Reference voltage
Stand·by
V13,14
V10
Ri13
Ci13
R10
Cm
Gv
F
Vs
Vn
4.2
3.3 ... VS
n
pF
n
pF
dB
dB
V
V
877
TUA 1574
Block diagram
H
u,
u,
o
o
H
TUA 1574
Inband-AGC
STANO-B
switch
decoupling
oscillatoroutp·ut
symIF-output
878
widebandAGe
TUA 1574
Pin functions
Pin 1/2:
RF input for mixer:
low impedance (basic circuitry) input directly to the mixer pair.
Pin 3:
Input for wideband information:
RF signal is present after pre-stage selection. Strong adjacent channel transmitter
activates control.
Pin 4:
Ground:
Decoupling should be referenced to this pin.
Pin 5:
Reference voltage:
To be decouple to pin 4.
Pin 61718: Oscillator:
3 point oscillator with low levels especially for tuning vector diodes.
Pin 9:
Decoupled oscillator output:
Buffered output specially designed for synthesizer.
Pin 10:
Output IR driver:
Output with 3000 corresponding to impedance of conventional IF ceramic filters.
Pin 11:
Stand-by switch:
The tuner is activated when this pin is tied to ground.
Pin 12:
Input for narrowband information:
Field strength information of inband signal is forwarded to this pin for use in prestage control.
Pin 13/14: IF driver input:
IF Signal is forwarded to mixer via selection.
Pin 15:
Supply voltage:
Pin should be RF decoupled against pin 4.
Pin 16/17: Mixer output:
Symmetrical open collector output.
Pin 18:
C output:
Output can be used as current output (pin diodes)
or as voltage output (for bipolar
andlor field effect transistors.
879
TUA 1574
Application circuit
Vs
from IF-part
I
TUA 1574
STAND - BY
SWITCH
I
I
'--------,..
PLL
VTun
880
lVTuner Ie
TUA2000-4
DIP 16
The TUA 2000-4 is a monolithically integrated circuit and suitable as a tuner for the VHF
range up to 400 MHz, e.g. for TV tuners.
RFsection
•
•
•
Few external components
Stable oscillator frequency and amplitude with very low interference radiation
Optimal rejection of oscillator and input frequencies at the IF output due to a decoupled
active ring mixer circuit
• High interference voltage resistance
• High-impedance mixer input, for symmetrical and asymmetrical connections
• IF post-amplifier for the UHF IF signal
IF section
•
•
•
Optimal cross-talk rejection
Large signal-modulation range
Low noise figure with wide minimum over large load-impedance range
881
TUA2000-4
Maximum ratings
Supply voltage range
V3 :$:VS
Reference voltage
VS;;>:V3
Voltage at pin 1. 2
V3:$: V1.2
Voltage at pin 8. 9
V3 :$:Va. 9
Voltage at pin 14
VI4 :$:VS
AC voltage at pin 4. 5. 6.11. 12.13.15
Junction temperature
Storage temperature range
Vs
-0.3 to 16.5
V
V3
-0.3 to 8.3
V
11,.2
-0.3 to 16.5
V
VS . 9
-0.3 to 16.5
V
V14
-0.3 to 16.5
V
Vrms
7j
oto 0.5
Tstg
150
-40 to 125
V
°C
°C
Thermal resistance (system -air)
RthSA
80
KlW
9 to 15
7.2 to 8.2
10 to 400
10 to 400
10 to 400
10 to 400
V
V
MHz
MHz
MHz
MHz
9 to 15
10 to 400
10 to 400
Oto 70
V
MHz
MHz
°C
Only the specified external circuitry may be applied to pins 4. 5. 6. 11. 12. 13. 15.
Operating range
Supply voltage
Reference voltage
Input frequency - mixer section
Input frequency of the UHF IF amplifier
Input frequency of the SAW amplifier
Oscillator am plifier
depending on the oscillator
circuitry at pin 4. 5
Voltage at pin 1. 2. 8. 9
Output frequency of the mixer/UHF
Output frequency of the SAW amplifier
Ambient temperature
882
Vs
V3
fM
12/1~
fUHF11
f lF15
'OSC4.5
Vt• 2•a. 9
'IF M/UHF 8/9
'IF 1. 2
TA
TUA2000-4
Characteristics
Vs =12 V; V3 =7.5 V; TA =25°C
Total current consumption
114 =0; V3 =7.2 V; Vs =9 V
114=0; Vs=12V
Current consumption at pin 3
min
typ
max
37
40
14
49
52
19
60
64
25
mA
mA
mA
100
IJA
200
IJA
7
Vs
V
0
3
V
110.1.2. B. 9.3
13
114 =0
Output characteristic
!JIB. 9
VB• 9 =9-15V; V3=7.8V
Output characteristic
!JI1.2
V1. 2 =9-15 V; V3 =7.8 V
UHF switching voltage
V14UHF
VI (u) = -25 dBm
Voz-5 dBm; 'IF =36.15 MHz
VHF switching voltage
V14 VHF
VI (u) = -25 dBm
Vo~-30 dBm;'1F = 36.15 MHz
Mixer gain
G60
Bd I; VI (RF) =-40 dBm;
'RF =60 MHz; 'IF = 36.15 MHz;
RG12/13 = 100 Q;
refer to response characteristic page 750
Mixer gain
G220
Bd III; VI (RF) =-40 dBm;
'IF = 36.15 MHz; RG 12113 = 100 Q;
refer to response characteristic page 751
Mixer noise
NF60
Bd I. white noise
RG 12113 = 100 Q; refer to response characteristic page 750
Mixer noise
NF 220
Bd III; white noise
RG 12/13 = 100 Q; refer to response characteristic page 751
Gain UHF input
VUHF
VI (u) =-40 dBm; V14 = Vs = 12 V
'RFU = 'IF = 36.15 MHz;
RG11 =200 Q; refer to response characteristic page 751
Noise figure UHF input
NFuHF
V14 = Vs =12 V; white noise
RG 11 = 200 Q; refer to response characteristic page 751
Oscillator turn-on drift
'osc
VD= 28 V; t = 0-500 ms;
Bd II; 'osc=216 MHz
Oscillator turn-on drift
'osc
VD=28 V; t =0-10 s;
Bd II; 'osc=216 MHz
25
27
29
dB
25
27
29
dB
13
dB
14
dB
35
dB
7
dB
-10
-250
kHz
-10
-450
kHz
31
33
883
TUA2000-4
min
typ
max
Additional application data
3
kQ
pF
Vint (EMF/2) rms
2.7
2
3.9
2.2
3.4
38
mV
Vint (EMF/2) rms
30
mV
R12113
Differential input resistance 1)
Differential input capacitance1)
IF input resistance 1)
IF input capacitance 1)
UHF input resistance 1)
UHF input capacitance1)
Interference voltage resistance Bd 12)
mN=l%; mint=80%;
fint = fN ± 15 MHz
fmod =1 kHz; fN =65 MHz
refer to response characteristic
Interference voltage resistance Bd 11 2 )
mN = 1%; mint = 80%;
fint = fN ±15 MHz
f mod = 1 kHz; fN = 220 MHz
refer to response characteristic
C12/13
R15
C15
Rl1
C11
kQ
pF
kQ
pF
Note on characteristics
Due to quasi no-load of the transformer output and 2x50 Q source impedance. the interference voltage at pins 12/13 is calculated by
\l;nt 12/13
'"
\l;nt (sourco/2) X 2
1) Measured S parameter values converted to Y parameters
2) See: Measurement configuration to measure cross modulation
884
x {2
TUA2000-4
Circuit description
The TUA 2000-4 contains a symmetrical mixer input, as well as a multiplicative mixer. The
oscillator amplitude is regulated. All oscillator operating currents and voltages are stabilized,
so that the oscillator's amplitude and frequency are largely independent of temperature
and operating voltage changes.
The IF amplifier has been provided with a high impedance input.
The output has two open collector connections.
During UHF operation, oscillator and mixer are switched off and the UHF IF input coupling
stage is activated.
RFsection
•
•
•
•
•
•
Few external components
Stable oscillator frequency and amplitude with very low interference radiation
Optimal rejection of oscillator and input frequencies at the IF output due to a decoupled
active ring mixer circuit
High interference voltage resistance
High-impedance mixer input, for symmetrical and asymmetrical connections
IF post-amplifier for the UHF IF signal
IF section
•
•
•
Optimal cross-talk rejection
Large signal-modulation range
Low noise figure with wide minimum over large load-impedance range
885
TUA2000-4
Plug-in location plan
PCB layout of test and measurement circuit 1
886
TUA2000-4
Block diagram
16
15
14
3,3k!1
13
12
11
10
9
3,3k!1
TUA 2000-4
2
4
5
6
887
TUA2000-4
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
q
14
15
16
888
Function
"Open collector" output of the IF SAW driver
"Open collector" output of the IF SAW driver
Input for external reference voltage
Low-ohmic collector output to the high reference point of a parallel
resonant circuit
High-ohmic base input to the high reference point of a parallel
resonant circuit
Oscillator signal output for counter connection
GND
"Open collector" output of the mixer
"Open collector" output ofthe mixer
Supply voltage
Asymmetrical IF signal input for the UHF IF signal
Mixer high-impedance differential input
Mixer high-impedance differential input
Switching voltage input for the VHF-UHF switch selection
Asymmetrical signal input of the IF SAW amplifier
GND
TUA2000-4
Test and measurement circuit 1
I
[,
R,
10
9
L7
TUA 2000-4
[2
L8
L_
3
1['0
4
5
['8
8
['9
R2
01
02
. :r.
:r
~
X1
V
URV 4
R3 .
VO
T[2'
R_
0
I[,_
l"
ill
05
R"
II
50n
['5
r
L3
H
[13
Choke
R6
R7
T["
889
TUA2000-4
Notes on test and measurement circuit 1
Response of passband curve for operation in VHF band I
fRF =60 MHz ±10 MHz; V'4 -0 V; Vi (REF)--40 dBm; ref. level =-10 dBm
gain test point fRF - 60 MHz; flF - 36.15 MHz
2dB/div
V I'-...
...........
I
7
\
II
-
---
1--"
I
.
7
'--
7
CENTER
RES
36.15 MHz
BW 300 kHz
\
l--~
t-
)
\
.
--
---,...
1\-\
~
1\
VBW3MHz
SPAN 20,00 MHz
SWP 75 s
Explanations to diagrams
2 dB/div
Center 36,15 MHz.
RES BW 300 kHz
VBW 3 MHz
SPAN 20.00 MHz
SWP 75
Ref. level
890
= 2 dB/division of Y axis
= center frequency of display at IF =
36,15 MHz
= resolution bandwidth of spectrum analyzer is 300 kHz in its IF section
= video bandwidth in IF section of spectrum analyzer is 3 MHz
= overall display range of diagram is 20 MHz, i.e. 2 MHz/division on X axis
= sweep time on X axis is 75 s
== reference level is top horizontal line of diagram
TUA2000-4
Notes on test and measurement circuit 1
Response of passband curve for operation in VHF band III
=220 MHz±10 MHz; V14 =OV; Vi (RF) =-40 dBm; ref. level =-10 dBm
gain test point fRF = 220 MHz; 'IF = 36.15 MHz
f RF
I,..,
2dB/div
.........
r-
I,.-.."
.~
/
/
1/
I-- -
1·- -
\ ._. '\
-~--
/
I
/
\
1
!
!
I
--\
/
CENTER
RES
36,15 MHz
BW 300 kHz
\
SPAN 20,00 MHz
SWP 75 s
VBW 3 MHz
Response of passband curve for operation in VHF IF position
= 36.15 MHz ± 10 MHz; V, 4 = 12 V; \II (RF) = -40 dBm; ref. level = 0 dBm
gain test point f RFU = 'IF = 36.15 MHz
f RFU
2dB/div
I--- V
I
/
\
1/
,
1\
/
\
/
36,15MHz
BW300kHz
\
l
/
CENTER
RES
\
VBW 3 MHz
SPAN 20,00MHz
SWP 755
891
TUA2000-4
Notes on test and measurement circuit 1
Between pin 4 -C18 - 01 - 02 -C19 - pin 5 ensure
minimal lead inductance for the suppression of parasitic
series resonance outside the oscillator's useful band.
Transformer Tr 1:
Transformer Tr 2:
Tr 1 = anzac = HH-1 09 30 to 500 MHz
C=oo;R gc =50Q
0=180 0 ;Rgo=50Q
50/200 Q unbalanced
3 turns bifilar on core material
B62152-A7-X1
Attenuator: X1 = 6 dB
Bd I
Bdll
Bd III
58 to 85 MHz
110t0216MHz
200 to 400 MHz
I
II
III
Band I
-12V
X
X
Band II
-12V
+12V
X
Band III
-12V
+12V
+12V
892
TUA2000-4
Notes on test and measurement circuit 1
Part list
Resistors:
Diodes:
IC:
R,
R2
R3
R4
R5
01 -88505 G
02-88609
03-88609
04-8A282
05-8A282
06 - 8ZX 97 C 75 V
TUA2000-4
Rs
R7
Re
Rg
10 Q
47 kQ
47 kQ
10 kQ
2.2 kQ
-100 kQ
-100 kQ
-100 kQ
-400 Q
2.2 kQ
Coils:
R,,-
capacitors:
C,
1 nF
C2
15 pF
C3
1 nF
C4
10 pF
C5
47 pF
Cs
1 nF
C7
1 nF
Cs
1 nF
Cg
1 nF
C,o - 10 nF
C" - 82 pF
C'2 2.2 pF
C'3 1 nF
C'4 1 nF
C'5 1 nF
C'6 -150 pF
C 17 - 27 pF
C,s 6.8 pF
C,g - 33 pF
C20 1 nF
C2, - 10 nF
Chip capacitor
STYROFLEX
STYROFLEX
STYROFLEX
STYROFLEX
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
Chip capacitor
L, - 4 turns; core 0 2 mm; wire 0 0.5 mm; CuL
L3 - 5 turns; core 0 4 mm; wire 0 0.5 mm; CuL
L3 - 9 turns; core 0 4 mm; wire 0 0.5 mm; CuL
L" L2, L3 - air-core coils
L4 - 2.5 turns; CuLs wire 0 0.25 mm
Ls - 2*6 turns; CuLs wire 0 0.25 mm
L7 -15 turns; CuLs wire 0 0.25 mm
L5 - 2*4.5 turns; CuLs wire 0.25 mm
L6 - 3 turns; CuLs wire 0 0.25 mm
Coil formers of L4IL e, L7 , L51Ls
Vogt filter set 10*12
5140500000
Catalog p. 41-8
Chokes:
Ch -10 I1H
(Trapezoidal cap.)
(Chip capacitor)
(Chip capacitor)
(Chip capacitor)
Please note that the chip
capacitors may be damaged if
the board is subjected to
mechanical stress; thus
overall functioning can no
longer be guaranteed.
Ouring the operating mode the PC board is adjusted without the socket. When the socket
is inserted in the socket connector, the parameters for the oscillator frequency and amplitude
as well as gain and noise will change.
893
TUA2000-4
Test and measurement circuit 2
S Parameter
Measurement Device
Zo= 50 (1
S 11
S Parameter
Measurement Device
S Parameter
Measurement Device
Zo = 50 (1
511,512,521, S22
c---
Zo=50(1
511
Vs
10nF
H
H
1
t
H
=
1nF
15
114
]
:=lnF
13
t
H:
H
1nF t11nF
12
11
10
19
7
1
TUA 2000-4
11
2
3
14
15
16
8
±10nF
V3~7.5V
--
For the determination of the input admitlancevalues of pins 11, 12,13, 15
894
t~t '
i,
i,
i,
BB 50S B
[,
05
-IVpF
OlG
I
RIO R,O
33kQ 100kO
16 F...... C
p
1
R9n Ril
33kflLJ.7kQ
TO~F
I~
47 pFT
R,<.
R16
1100
100
'C
'2.
lpF
tr
C!:
B8S05B~D12
i"
6PF
[
l>
H
27pF
~
['t l tF!'''I'OO~I! tl;~or~rDT1D
f-
["
R"
220
in
10
33kll
i"
[,
09~_~r~PF
R,
4,7Pf9=C,
["
lO
'!["
}" ~
()
~r
t:
;:;:
P
....L
L~
~
i"
470PfICv"
Cr.
,"F~["
,-----
33kflllR18
R,
~
ml,
(
o:s
4,7nFI["~
I
L
02 iKBB609
~
47k{lIIR l1
27 pF...,... ["1
~
i,
,-t----
loF
II
R,
13301ill1
i,
I
~1, I.,~loF
VR
nr
R"O 220nR"G d[IlOR"
82001
470 HI
["
~'PFI[" 0"2l'1!.3.Y:.!
88609 rl~
!:!:.c."
J
lOflH31
"I
1-'
H
I
"'" ':'l
VpFn[Ja
Ht--Y
R"
4,7kO
010
6860"
!2,7kO ~011
LlI.i FL16
R .J....cZ6
4.71~(jTlnF
I ~3l
HH-----1
r ["
10pF
..J.. I
133 PF
:
,
lnFlc20
3.3kflIIR))
I HI["
4,1nF
IBIIJII
i4
)fl H
,
i6,BpH
R"
1---------+--+-+~---_I-----+12V
4,?pF!(jr.
--'[21,
470fl
IF
c!
l>
I\)
.~
'"
g~
'"
.
0«
a
~
~
1
II
0
~~
""
·e:S
ow
c
.9
";::
E \&/
1;\
A
.....
t
I- F-o
.c
S
~
N
I
~
,/
903
TUA2005
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
904
Function
Low-impedance symmetrical output of SAW driver
Low-impedance symmetrical output of SAW driver
anti-phased to pin 1
GND
High-impedance input of oscillator amplifier
Low-impedance output of oscillator amplifier
Oscillator signal output for PLL systems with possible
open collector output
Blocking capacitor for controlling oscillator amplitude
Symmetrical mixer output
Symmetrical mixer output anti-phased to pin 8
Switching voltage input for VHF/UHF switch-over
High-impedance asymmetrical RF input for UHF IF signal
High-impedance symmetrical RF input of VHF mixer
High-impedance symmetrical RF input of VHF mixer,
anti-phased to pin 12
Supply voltage
Blocking point of internal reference voltage
High-impedance asymmetrical IF input of SAW driver
Signal Generator
3:
(I)
Signal Generator
I»
Ul
50n
.----.
H
'---'
...J::::
(I)
H
3(I)
ao
::;'
o
+Vs
J::::
;:;:
VHFIUHF
10 pF
Switch-Over
Hh
=l=10nF
16
15
14
p
=l==1nF
=l=1nF
13
12
=1= 1nF
11
HH
10
=!=15pF
1:
4
5
8
6
33pF
47kll
47 kll
I10nF
I
II
Switching
Voltage Bd 1/111
I
10nF
I
I
~-y~ ____ J
Tuning voltage +VD
~...L
I
+
Al201
1
S WI°t c hO109 S ectlon
° can be
Added if Required
I
01
Y
!
,'~
o
9
TUA 2005
2
<0
9 --9-~
~
I\)
o
o
U1
TUA2005
Measurement circuit 2
+Vs=12V
10nF
H
SAW Driver
TUA2005
1
SAW
Filter
Zo =75(1
The input reflection factor 5 16 is measured at 36.5 MHz for computing the parallel equivalent
circuit.
Measurement circuit 3
+Vs =12 V
10nF
SAW Driver
TUA 2005
Is
IT
=36.5 MHz
= 1 kHz
ms =80%
THO ~0.4%
Ra =50 Q
906
H
G 3203
The input capacitance of
the SAW filter is
compensated with
this coil
TUA2005
Measurement circuit 4
+Vs-12V
10nF
H
SAW Driver
TUA2005
1
Transformer
1 nF
r=-:--:-_...,50n--200ni----lII----6---l
Device to
Measure
Noise Figure
'i"
e.. h 8970A
J..
I
G 3203
The input capacitance
of the SAW filter
is compensated
with this coil
Measurement circuit 5
+Vs=12V
10nF
H
SAW Driver
TUA2005
1
1nF
16
SAW Filter
OFWG3203
fa
1nF
1nF
Network Analyzer
o
The 4-pole matrix SII. S12. S21' S22
is measured at 36.5 MHz for
computing the "It equivalent circuit
907
TUA2005
Measurement circuit 6
+Vs=12V
1
±10nF
I
(I
I 10mH
I
110m H
==1nF
==1n F
I
19
TUA 2005
18
I
Network Analyzer
The 4-pole matrix 581 , 582 • 591 , 592 is measured at 100 MHz
for computing the output capacitance.
908
TUA2005
Measurement circuit 7
Measurement of static output impedance
v
A l--...--o+Vs
8
LI 1.183
Z83= Llla3
A
LI V93
Z93= LlI93
12
V
--J-----------~
11--r-~
I
!
I
r-LlV----j
1
I
9,5
I
I
13,5
------ V93 ( V83 )
IV)
909
910
LED Driver for Light Spot Displays
UAA170
DIP 16
IC for driving 16 light emitting diodes. Depending on the input voltage, the individual LEOs
are driven within one row in form of a light spot. The UAA 170 provides a linear relation
between control voltage and the driven LED.
By using an appropriate circuitry, the brightness of the LEOs can be varied and the crossing
over of the light spot can be set between "smooth" and "abrupt". By connecting two ICs in
parallel, up to 30 LEOs can be driven.
Maximum ratings
Supply voltage
Input voltages
Load current
Junction temperature
Storage temperature range
Thermal resistance (system-air)
Tstg
5
150
-40 to 125
V
V
rnA
°C
°C
RthSA
90
K/W
Vs
V11 , V12 , V13
114
1j
18
6
Operating range
Supply voltage range (LED red)1)
Ambient temperature range
Vs
Tomb
111t018
-25 to 85
1
~C
1) The lower limit only applies to a forward voltage of the LEDs of approx. 1.5 V (red LEDs); the lower limit increases with
higher forward voltage
911
UAA170
Characteristics (VS = 12 V; Tamb = 25 °e)
min
typ
max
2
-2
-2
4
10
111
112 ,113
mA
IlA
IlA
Voltage difference
Voltage difference for
smooth light transition
Voltage difference for
abrupt light transition
Voltage difference
Ll V12/13
1.4
6
V
LlV12/13
1.4
V
LlV12/13
4
4
V
V
Stabilized voltage 114 = 300 IlA
114 =
5 mA
V14
V14
4.5
Reference input voltage
Vrefmax
1.4
0
Is
Current consumption (114 = 0; 116 = 0)
Control input current
Reference input current
LlV12/13
5
Vrefmin
Tolerance of forward voltages of
LEOs, mutually
Output current for LEOs
LlVo
L:10
Test circuit
10kll
+12V
[~
16
115
14
P
13
T12
11
10
r;-
5
6
7
8
UAA 170
1~
'fL.L
2
3
~t-
>-rft-~ ~>->-~
_LIl.l~':'l
4
,IF'-
,l
'----
912
,IF'
25
6
V
V
6
4.6
0.5
V
V
V
mA
UAA 170
Scale display with light emitting diodes
Scale displays by means of a wandering light spot are particularly suitable for indicating
approximate values. Applications of this kind are level sensors, VU-meters, tachometers,
radio scales etc. When applying the displays in measuring equipment, multicolored light
emitting diodes can be used as range limitation. Ring scales are obtained by a circular
arrangement of the diodes. The IC UAA 170 has especially been developed for driving a
scale of 16 LEOs.
The input voltages at pins 11, 12 and 13 are freely selectable between 0 and 6 V. Any kind
of adjustment becomes possible by suitable voltage drivers. The DC value Vcontrol is always
assigned to a certain spot of the diode chain.
The voltage difference between pins 12 and 13 thereby corresponds to the possible indication
range. .1V1211 3 defines at the same time the light transition between two diodes. With
.1V12/13 approx. 1.4 V, the light point glides smoothly along the scale. With increasing voltage
difference, the passage becomes more abrupt. With .1V12/13 approx. 4 V, the light point
jumps from diode to diode.
Input voltages beyond the selected indication range cause the diodes 01 or 016 respectively, to light up, identifying only that the range has been exceeded.
Block diagram
V,
Vstab
15
14
Vref max
13
Vref min
12
Vc.ontrol
11
Vs
10
Matrix
T
1
Ground
4
6
8
913
UAA170
Indication for smooth transition UAA 170
r--1.4V--016
015
I
014
013
'" 012
8 011
~ 010
00 9
~ 08
o7
o6
o5
o4
o3
o2
o1
=
Vrefmax Vcontrol max
Vcontrot
Vrefmin= Vcontrot min
Indication for abrupt transition UAA 170
4.0V
----
gl~l
014
...0-
...0-
013
-0-
'" 012
8 011
-' 010
...0...0...0-
09
~ 0 8
o7
't;
-0-
....
-0-
o6
o5
o3
o2
...0...0-
04
01
...0...0-0.
-
r-
--))
~tfmin= Vcontrol min
914
~ontrot
vref max= ~ontro' max
UAA170
Brightness control
Phototrnnsistor
or resistor
as required
16
UAA 170
Pins 14, 15, and 16 serve to determine the diode current. Corresponding to the desired
light intensity, the forward current of the diodes is linearly variable in the range If approx.
o to 50 mA. The resistance at pin 15 defines the adjusting range. The resistances between
pin 14 and 16 determine the current.
With the aid of a phototransistor, such as BP 101, the light intensity of the LEOs can be
adjusted to the light fluctuations of the environment.
Diode current versus base emitter resistance
Vs = 12 V; Tamb = 25°C; V14 = 5.4 V; red LEOs
rnA
50~-~--
~~-~-~---~~~~-~-4~---4--4--+---
I
30
o
o
10
20
30
40
50
60
70
-Ra
915
UAA 170
Operation of less than 16 LEOs
Control of 9 LEOs
161
1
1
1
1
1
~
UAA 170
11
L
r
r
461
1
r;-
~8
1-'
+V
Control of 11 LEOs
1
161
~
1
11"LD 461
916
1-
1
1
1
1
1
[;-
UAA 170
~L
1
rlr
,L
,~
~
3xSA 127
8
UAA170
Application circuit for the control of 30 LEOs with 2 x UAA 170
Range of control voltage Vcont,ol = 0 to 5 V
Voltage difference V,2/,3 = 2 x 1.2 V = 2.4 V
Since the diodes 016 or 017 are permanently lit when the maximum or minimum voltages
V,3 or V,2 adjusted by R3• R4• Rs. are exceeded or fall short the diodes should be covered.
if necessary.
VcantrGl
o to+sv
10k!!
56kQ
6.2kll
22kQ
Vs
.12V
22kQ
I
I
~~
R,
56k!!
T"
lOkQ
lkQ
15
16
14
P
12
1l
10
11
r;-
r-o
Dl2
l2_ LD461
~h~
5
4
L
6
~QIT
1
I I I
I
1,6
15
1'4
P
UAA 170
1
lkQ
'l
D171
8
1
D16
Il
12
11
10
r;-
5
6
~
8
UAA 170
z
}
krT
'-d~
4
QIf~
Dll
The figure shows an expansion of the circuit to 30 diodes with 2 ICs UAA 170. The diodes
016 or 017 light permanently. when the reciprocal absolute ratings are exceeded. They
should be covered. The reference voltage .dV12I13 = 2 x 1.2 = 2.4 V is derived from a stabilized
dc voltage of typo 5 V available at pin 14. A resistance of 6.2 kQ provides an overlapping of
the ranges in order to ensure a smooth transition from 015 to 018. The control voltage Veont,ol
is forwarded in a parallel mode to pins 11 via a divider R, : R2 • The voltage divider is to be
dimensioned according to the desired input voltage. With a divider current of 1= 100 IlA
and a control voltage of Veont,ol = 10 V, the following is valid:
R2
=
R -
,-
L1 V,2/,3 .. 2.4
I
0.1
Veont,ol - .a
I
= 24 kQ and
v, 2/13 =
7.6
0.1
= 76 kQ
The nearest standard value is R,
step is then
10 V
.aVcont,ot
= 30
= 75 kQ. The voltage difference for switching an incremental
=O.16V.
917
918
LED Driver for Light Band Displays
UAA180
DIP 18
Integrated circuit for driving 12 light emitting diodes. Corresponding to the input voltage the
LEOs forming a light band are controlled similar to a thermometer scale.
By using an appropriate circuitry the brightness of the LEOs can be varied and the light
passage between two adjacent LEOs can be arranged between "smooth" and "abrupt".
Maximum ratings
Supply voltage
Input voltage
Vs
Va
V16
V17
6
6
6
Storage temperature range
Junction temperature
Ts1g
~
-40 to 125
150
V
V
V
V
°C
°C
Thermal resistance (system-air)
R1hSA
78
K1W
18
Operating range
Supply voltage range
Ambient temperature range
Vs
Tamb
11ot018
-25 to 85
1
~C
919
UAA180
Characteristics (VS = 12 V,
Tamb
= 25°C) .
typ
max
~8
5.5
8.2
13
116
117
0.3
0.3
0.3
min
Current consumption (12 = 0)
(without LED current)
Input currents
(V3-V16 < 2 V)
Voltage difference for
smooth light transition
Voltage difference for
abrupt light transition
Diode current per diode
Tolerance of LED forward voltages
I!A
I!A
I!A
V
V 16/3
V
mA
V
4
V16/3
10
10
.1Vo
Measurement circuit
+12V
j
18
10
k~ ~ RS[
100
kll
J1kll
.1:
920
" "
I
.....
10
UAA 180
1MlI ]
I
P,
v
T
1
Ii
"
light band test
brightness test
~OOkll
mA
L
."v IV....
....
v
v
UAA 180
Scale display with light emitting diodes
Scale displays by means of a growing light band are particularly suitable for the measuring
of approximate values. Applications of this kind are level sensors, VU meters, tachometers,
field strength indicators etc. When applying the displays in measuring equipment, multicolored LEDs can be used as range limitation.
The voltage difference between pins 16 and 3 thereby corresponds to the possible indication range . .::lV16/3 defines at the same time the light passage between two diodes. With
.::lV16/3 ~ 1 V, the light band glides smoothly along the scale. With increasing voltage difference,
the passage becomes more abrupt. With .::lV16/3 approx. 4 V, the light band jumps from diode
to diode.
Each quartet must consist of identical diodes in orderto maintain its functional characteristics.
It is therefore possible to design the first and third quartet as diodes emitting the color
red and the second quartet as diodes emitting the color green to delineate a certain
operational area.
Pin 2 serves to determine the diode current. Corresponding to the desired light intensity,
the forward current of the diodes is variably linear in the range I, approx. 0 to 10 rnA.
Application circuit 1 shows the possibility of designing this resistance, adjustable by means
of a phototransistor BP 101, in order to adapt the light intensity to changing ambient
brightness. The adjusting range of the diode current lies between I, approx. 5 rnA (BP 101
not lit) and I, approx. 10 rnA (BP 101 fully lit). If pin 2 is open the diode current is 10 rnA.
Block diagram
15
14
13
12
11
4
10
I
I
I
LED driver unit
I
L ________ _
1
-:r~,,: 1:-I ,:":[ i
Supply unit
1
~r-,,~~~rr~
1
!
1
3 V ret max
Vcontrol.17
Vref min 16
1~
_1- - - - - -- - - -- - - - tI Test data recording and processin
1 st row
2nd row
3 rd row
921
UAA180
Application circuit 1
Vret min + Vs
V[ontrDI
//
//
2x LD 466
.......
.... ... lV....
" ... ... ... ... ... "
IV "
" " II"
v
18
~
17
16
R[ }Mrl P
v
15 14 13
v
v
12
11
7
8L
v
v
10
UAA 180
BP101 I
1
.
2
3
4
5
6
JR
.10
+ V,ef max
Depending on the actual maximum ratings, the resistances R1 to R7 can be varied widely
as follows:
R3= 8200
R4 =
56 kO
R5 = 220 kO
Rs= 2.2 kO ... 100 kO
If a quartet does not need the full number of display diodes and if the first wired diodes
shall be left luminous at full driving, bridges have to be inserted replacing the missing LEOs.
Otherwise the first diodes of the quartet switch off when their display range is exceeded.
922
UAA180
Application circuit 2 '
for cascading several UAA 180 ICs (up to 7)
L
>
LP.
'"'+
l~
"E
l=-
)(
I
0-
I
LP.
I
co
.-
~
I
)
[
«
«
::::l
lP.
LP.
LL
T~
C>
~
I
I
LP.
LP.
LP.
L---
LL
J
LP.
lP.
P.
L
I
0-
I
Lt>
co
.-
«
«
LP.
LP.
T~
[
::::l
I
~
L=-
I
C>
I
~
I
..
LP.
LP.
LP.
LP.
~~
g
+.
923
UAA 180
Application circuit 3
for field strength indication
+12V
lkll
S.6V
TCA 440 or
TDA 1046, TDA 1047
924
Package Outlines
925
926
Package Outlines
Plastic plug-in package 20 A 8 DIN 41866
8 pins, DIP
Plastic plug-in package 20 A 14 DIN 41866
14 pins, DIP
1,5max
045,0.1
o,~
'=:1
2,54
8
5
~,.,."
~b
h
~bx
17,6_0,3
Approx. weight 0.7 g
Approx. weight 1.1 g
Plastic plug-in package 20 A 16 DIN 41866
16 pins, DIP
Plastic plug-in package 20 A 18 DIN 41866
18 pins, DIP
20.2-0.3
Approx. weight 1.2 g
8 0.4mox
IT ~ - ~ - - - - 9' 0.4mox
1----22.7_0.3---ii---
Approx. weight 1.3 g
Dimensions in mm
927
Package Outlines
Plastic plug-in package 20 A 20 DIN 41866
20 pins, DIP
.5:
~;17,6tO'21
~=----I-i---~----r~f§
0,45.0·1
2,54
1,5mox :::1,2
20
11
10
0,4mox
1-----25.3.0.2---"r---
Approx. weight 1.5 g
Plastic plug-in package 20 D 22 DIN 41 866
22 pins. DIP
r-
!(i
c: ~--j
10.16'01
~=---.
--.--I--~-~--""'.~ ~
0.45,0.1 1.5max
22
2.54
t
=1.2
12
I
9
- ·01
I
I0.16. ',Z-j
11
0.4mox
Approx. weight 2.1 9
Dimensions in mm
928
Package Outlines
Plastic plug-in package 20 B 24 DIN 41866
24 pins, DIP
12
0.4mox
1------31.9_0.4 ------114--Approx. weight 2.5 g
Plastic plug-in package 20 B 28 DIN 41866
28 pins, DIP
----~.=~)(
<~0~
~
o
m
d
.
----if-2.54
1.5 max
28
0.45 -0.1
--l
r-
15.24
,O.I---:
I
~
.,.;
0,45
Dimensions in mm
Approx. weight 1.1 g
931
Package Outlines
Piggyback
I ~-.,.,
I
I
-
!I
rh"·
-..,
•1
I I I I I Jill II ! I rill i
-
~
o45,0,1
~
1,0,1:: 1 3
_..0...-"':;;'
Jt f
-
1--------~51,3-1---------<~
1-----31_1-----1
21
40
+++
+++
20
Dimensions in mm
Special package
') Change to 130 ± 3 mm
in preparation
green block
(Q)
Approx. weight 8.5 g
932
(OV)
Package Outlines
Plastic package
44 pins, PLCC
1
44
I
{j}
i
.-.-.t-----.
I
m
,..:.~ r-~
';E
t::~
. . . . . ~~"""I....,...,...=W
-iLJL
1,27
0,B1max
4,3B,Q3
Plastic package
68 pins, PLCC
168
i
------+-_._.
'ill
!
!
1,27
0,81 max
I
;
Dimensions in mm
933
Package Outlines
Ceramic package
68 pins, C-CC
1-----24,4_0,5 --~
17
Identification for Pin 1
Ceramic package
88 pins, PGA
88
-033,4_ 0,7-----<-1
934
Dimensions in mm
Package Outlines
Plastic power package, similar to TO-220
Plastic power package, similar to TO-220
(with cooling strip and 5 pins)
(with cooling strip and 5 pins)
4xt7=6.8
4.1.7=6.8
Approx. weight 2.1 g
Approx. weight 2.1 g
Transparent plastic miniature package
Spins
Plastic power package, similar to TO-220
(with cooling strip and 7 pins)
1.3,0 2
···-fOoi···
I'
II
;
Radiantsensitive
area
Approx. weight 0.1 g
Approx. weight 2.1 g
Dimensions in mm
935
Package Outlines
Plastic package, P-DIP,4 pins
20 A 4 DIN 41866
.
Plastic package, P-DIP, 6 pins,
20 A 6 DIN 41866
Approx. weight 0.5 g
Approx. weight 0.7 g
Plastic package, P-DIP, 8 pins
20 A DIN 41866
Plastic package, P-DIP, 14 pins
20 A 14 DIN 41866
4
10_0.2 . 0.4mox
Approx. weight 0:7 g
17• 6-0.3 _
7
0.4mox
Approx. weight 1.1 g
Dimensions in mm
936
Package Outlines
Ceramic package, C-OIP. 16 pins
.
1m
I
~~ 0_1.
~rt~.f:l
N
I
--I
f-.~
lIT""
.-1
2.54 15max 0.45<0.1 ~1.3
16
~I
I 0.25'°.1 11---17.62,0.6 f-.--.
9
fr_I~~~;:q
Approx. weight 1.4 g
Ceramic package, C-OIP. 24 pins
24
13
)
0
1
f--·--31.5.15
12
Dimensions in mm
Approx. weight 3 g
937
Package Outlines
Ceramic package, C-DIP. 40 pins
0.25,0.1
I
1S.21t'0.6~
ItO
~
iO
1
51.5-1.5
Approx. weight 6.8 g
Plastic ftatpack, 3 pins
Plastic ftatpack, 4 pins
c:
0.25. 0.1
lU--
~1
....iii
..!/
T
L
0.25,0.1
Approx. weight 0.5 g
Dimensions in mm
938
Package Outlines
Miniature plastic package
6 pins
Miniature plastic package
8 pins
Approx. weight 0.1 g
Approx. weight 0.15 g
Miniature plastic package (SMD)
6 pins (similar to SO 6)
Miniature plastic package (SMD)
8 pins (similar to SO 8)
0.2
0.2max
---II. . 0.21---
~
!-I
E
b
~5
Approx. weight 0.1 g
Approx. weight 0.15 g
Dimensions in mm
939
Package Outlines
Miniature plastic package (SMD)
14 pins (SO 14)
Approx. weight 0.13 g
Miniature plastic package (SMD)
20 pins (SO 20 L)
Approx. weight 0.6 g
Dimensions in mm
940
Package Outlines
MIKROPACK (SMD)
MIKROPACKs are delivered exclusively in taped form.
Dimensions of perforation in acc. with DIN 15851, sheet 2 (Super 8)
TCA205 K
TLE4901 K
0.6 max
11
N
N
0.6max
14-
0_03mln
0.03 min
CD
---- 4 ---
TCA955K
0.45
0.6max
0.03 min
Dimensions In mm
941
Package Outlines
Packaging tubes
I
!
!
!
'
I
I
'
!
!
!
,.
!
,
!
[l'---==--=----=--=-----if- - - -n=5=2~~29-'"-9=-I- -I- 9-9= +-i- 9-~-~-,*--4J
SIEMENS
ANTISTATIC ~
----400'0,5 - - -
_
B,--I
1-----13.'0 =1 3 0 - - 1
-~+-+~-+~++-+-+~~+-:+-~..-+
-.-~--'--~----'------~----~--.--~-~-
--
942
-,-~
357,0.5 - - - -
B ---;
,- -----13.12=156 - - - - - - . ;
Siemens Sales Offices
943
Siemens/Semiconductor Group
REGIONAL SALES OFFICE
Eastern Region
Central Region
Western Region
Siemens Components,lnc.
P.O. Box 1483
119 Russell Street
Littleton, MA 01460
(617) 486·0331
Siemens Components, Inc.
5600 North River Rd. #735
Rosemont, IL 60018
(312) 692·6000
Siemens Components, Inc.
625 The City Drive South, Ste. 320
Orange, CA 92668
(714) 385·1274
Siemens Components,lnc.
103 Carnegie Center
Princeton, NJ 08540
(609) 987·0083
Siemens Components, Inc.
1105 Schrock Road, Ste. #204
Columbus, Ohio 43229
(614) 433-7500
Siemens Components, Inc.
19000 Homestead Road
Cupertino, CA 95014
(408) 725·3586
Siemens Components, Inc.
6575 The Corners Pkwy., Ste. 210
Norcross, GA 30092
(404) 449·3981
Siemens Components, Inc.
3003 LBJ Freeway, #204
Dallas, TX 75234
(214) 620·2294
SEMICONDUCTOR REPRESENTATIVES
Eastern Region
Central Region
Western Region
Anchor Engineering
188 Needham Street
Newton Upper Falls, MA 02164
(617) 964·6205
Cahill·Schmltz·Cahill, Inc.
315 North Pierce Street
SI. Paul, MN 55104
(612) 646-7217
Centaur Corporation
20720 Ventura Blvd., #280
Woodland Hills, CA 91364
(818) 704·1655
ADI
P.O. Box 30, Hwy. 301 South
Smithfield, NC 27577
(919) 934·8136
Electro Reps, Inc.
7240 Shade Land Station, Ste. 275
Indianapolis, IN 46256
(317) 842·7202
Mission Ridge Marketing
2102 Business Center Dr., Ste. 214
Irvine, CA 92715
(714) 253·4626
Delta Technical Sales
3901 Commerce Drive
Willow Wood Office Center
Willow Grove, PA 19090
(215) 657·7250
KMA Sales Company
2360 North 124th Street
Milwaukee, WI 53226
(414) 259·1771
Varigon San Diego, Inc.
4805 Mercury Street, Ste. L
San Diego, CA 92111
(619) 576·0100
KMA Sales Company
5105 Tollview Drive, Ste. 275
Rolling Meadows, IL 60008
(312) 398·5300
Lange Sales, Inc.
1500 W. Canal Court, Bldg. 4, Ste. 100
Littleton, CO 80120
(303) 795-3600
Advanced Technical Sales
601 North Mur·len, Ste. B
Olathe, KS 66062
(913) 782-8702
Micro Sales, Inc.
2122112th Ave. Northeast, Ste. B
Bellevue, WA 98004
(206) 451·0568
Advanced Technical Sales
1810 Craig Road, Ste. 125
SI. louis, MO 63146
(314) 878·2921
Micro Sales, Inc.
17575 Southwest Tualatin Valley Hwy. #210
Aloha, OR 97006
(503) 642·1818
Advanced Technical Sales
375 Collins Road Northeast
Cedar Rapids, IA 52402
(319) 365-3150
F·PSales
7301·C Jefferson Northeast
Albuquerque, NM 87109
(505) 345·5553
Advanced Technical Sales
9550 E. Lincoln #609
Wichita, KS 67207
(316) 682·2769
Westrep
2432 West Peoria, Ste. 1061B
Phoenix, AZ 85029
(602) 997-8899
OXI, Inc.
501 First Ave. North, Ste. 504
SI. Petersburg, FL 33701
(813) 894·4556
OXI, INc.
2833 The Palm Court
Orlando, FL 32809
(813) 894·4556
OXI,lnc.
2020 West McNab Rd., Ste. 101
FI. Lauderdale, FL 33309
(305) 978·0120
Klamco Electronics
Box 29191 65th Inf. Station
Rio Piedras, PR 00929
(809) 752·6169
Emtec Sales
299 Ridgedale Avenue
East Hanover, NJ 07936
(201) 428-0600
EM A, Inc.
309 Jordan Lane Northwest
Huntsville, AL 35805
(205) 830-4030
Enco Marketing, Inc.
1565 North Woodard Ave.
Terrace No.6
Bloomfield Hills, MI 48013
(313) 642·0203
EM A, Inc.
620 Colonial Park Drive
Roswell, GA 30075
(404) 992·7240
Electronic Salesmasters
24100 Chargrin Boulevard
Beachwood, OH 44122
(216) 831·9555
D.G. Reps
1447 York Road, Ste. 401
Lutherville, MD 21093
(301) 583·1360
CompTech Sales, Inc.
2221 Madison Drive, Ste. B
Arlington, TX 76011
(817) 265-6007
Ossmann Associates, Inc.
6666 Old Collamer Rd.
E. Syracuse, NY 13057
(315) 437·7052
CompTech Sales, Inc.
4135 S. 100th East Ave., Ste. 101
Tulsa, OK 74146·3635
(918) 622·7744
Ossmann ASSOCiates, Inc.
280 Metro Park
Rochester, NY 14623
(716) 424·4460
CompTech Sales, Inc.
9100 S.w. Freeway, Ste. 227
Houston, TX 77074
(713) 776-8330
CompTech Sales, Inc.
12701 Research Blvd., Ste. H
Austin, TX 78759
(512) 33 HI922
The information contained here has been carefully reviewed and is believed to be accurate. However, due to the possibility of
unseen inaccuracies, no responsibility is assumed. This literature does not convey to the purchaser of electronic devices any
license under the patent rights of the manufacturer.
The information contained here has been carefully
reviewed and is believed to be accurate. However,
due to the possibility of unseen inaccuracies. no
responsibility is assumed.
This literature does not convey to the purchaser of
electronic devices any license under the patent
rights of any manufacturer.
Issued by IC Standard Products
2191 Laurelwood Road, Santa Clara, CA 95054 (408) 980-4500
Siemens Components, Inc.
CG/2000·299·121A
BAN 10M 7187 Printed in U.S.A.
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