1987 Signetics Linear Data Manual Vol 3 Video
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Indianapolis Division
6990 Corporate Drive
Indianapolis. IN 46278
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,Electronics Group
Claude Michael Group
(317) 297-0483
, (800) 538-2596
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Linear
Data Manual
Volume 3:
Video
DISTRIBUTED BY
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Signefics
Linear Products
1987 linear
Data Manual
Volume 3:
Video
Signetics reserves the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in
order to improve design and/or performance. Signetics assumes no responsibility or
liability for the use of any of these products, conveys no license or title under any
patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work
right infringement, unless otherwise specified. Applications that are described herein
for any of these products are for illustrative purposes only. Signetics makes no
representation or warranty that such applications will be suitable for the specified use
without further testing or modification.
LIFE SUPPORT APPLICATIONS
Signetics' Products are not designed for use in life support appliances, devices, or
systems where malfunction of a Signetics Product can reasonably be expected to
result in a personal injury. Signetics' customers using or selling Signetics' Products
for use in such applications do so at their own risk and agree to fully indemnify
Signetics for any damages resulting in such improper use or sale.
Signetics registers eligible circuits under
the Semiconductor Chip Protection Act.
© Copyright 1987 Signetics Corporation
All rights reserved.
Signetics
Preface
Linear Products
The Linear Division, one of four
Signetics product divisions, is a major
supplier of a broad line of linear integrated circuits ranging from high performance application specific designs to
many of the more popular industry standard devices.
A fifth Signetics division, the Military
Division, provides military-grade integrated circuits, including Linear. Please consult the Signetics Military data book for
information on such devices.
Employing Signetics' high quality processing and screening standards, the
Linear Division is dedicated to providing
high-quality linear products to our customers worldwide.
The three 1987 Linear Data and Applications Manuals provide extensive technical data and application information for a
February 1987
broad range of products serving the
needs of a wide variety of markets.
Volume 1 - Communications:
Contains data and application information concerning our radio and audio
circuits, compandors, phase-locked
loops, compact disc circuits, and ICs for
RF communication, telephony and modem applications.
Volume 2 -
Industrial:
Contains data and application information concerning our data conversion
products (analog-to-digital and digital-toanalog), sample-and-hold circuits, comparators, driver/receiver ICs, amplifiers,
position measurement devices, power
conversion and control ICs and music/
speech synthesizers.
Volume 3 -
Video:
Contains data and application information concerning our video products. This
iii
includes tuning, video IF and audio IF
circuits, sync processors/generators,
color decoders and encoders, video processing ICs, vertical deflection circuits,
Videotex and Teletext ICs and power
supply controllers for video applications.
Each volume contains extensive product-specific application information. In
addition there are selector guides and
product-specific symbols and definitions
to facilitate the selection and understanding of Linear products. A functional
Table of Contents for each of the three
volumes and a complete product and
application note listing is also included.
Although every effort has been made to
ensure the accuracy of information in
these manuals, Signetics assumes no
liability for inadvertent errors.
Your suggestions for improvement in
future editions are welcome.
Signe1ics
I
Product Status
Linear Products
DEFINITIONS
Datal Sheet
Identification
Product Status
Definition
This data sheet contains the design target or goal
()bJect/WI Specfflt:affon
Formative or In Dellgn
PrelImInary SpecI_
Preproduction Product
specifications for product development Specifications may
change in any manner without notice.
This data sheet contains preliminary data and supplementary
data will be published at a later date. Slgnetlcs reserves the
right to make changes at any time without notice in order to
Improve design and supply the best possible product.
_ , SpeclftClJlIon
Full Production
ThIs data sheet contains Final Specifications. Signetics
reserves. the right to make changes at any time without
notice in order to improve design and supply the best
possible product
February 1987
iv
Signetics
Volume 3
Video
Linear Products
Preface
Product Status
Section 1:
GENERAL INFORMATION
Section 2:
QUALITY AND RELIABILITY
Section 3:
12 C SMALL AREA NETWORKS
Section 4:
TUNING SYSTEMS
Tuner Control Peripherals
Tuning Circuits
Prescalers
Tuner IC
Section 5:
REMOTE-CONTROL SYSTEMS
Section 6:
TELEVISION SUBSYSTEMS
Section 7:
VIDEO IF
Section 8:
SOUND IF AND SPECIAL AUDIO PROCESSING
Section 9:
SYNCH PROCESSING AND GENERATION
Section 10: COLOR DECODING AND ENCODING
Section 11: SPECIAL-PURPOSE VIDEO PROCESSING
Video Modulator/Demodulator
AID Converters
0/ A Converters
Switching
High Frequency Amplifiers
CCD Memory
Section 12: VERTICAL DEFLECTION
Section 13: VIDEOTEX/TELETEXT
Section 14: SWITCHED-MODE POWER SUPPLIES FOR TV/MONITOR
Section 15: PACKAGE INFORMATION
Section 16: SALES OFFICES
February 1987
v
Signetics
Section 1
General Information
Linear Products
INDEX
Contents of Volume 3, ViDEO .........................................................................1-3
Alphanumeric Listing of all Linear Products ........................................................ 1-7
Application Note Listing
- by Product Group ................................................................................... 1-13
-by Part Number ..................................................................................... 1-16
Outline of Contents of Volume 1, COMMUNICATIONS ........................................ 1-19
Outline of Contents of Volume 3, INDUSTRIAL ................................................. 1-20
Cross Reference Guide by Company .............................................................. 1-21
SO Availability List ...................................................................................... 1-24
Ordering Information .................................................................................... 1-26
•
Signetics
•
Volume 3:
Video
Table of Contents
Linear Products
Preface .............................................................................................................................. . .... .. ... ... ..... ..... ... .. . . .
Product Status........................................................................................................................ .. .. ...... .. ..... .. ... .. . . .
Outline of Contents .............................................................................................................................. . ..... ... .. . ..
iii
iv
v
Section 1 - General Information
Contents of Volume 3, VIDEO ................................................................................................................................
Alphanumeric Listing of all Linear Products................................................................................................................
Application Note Listing
- by Product Group .............................................................................................................................. ..............
- by Part Number ...............................................................................................................................................
Outline of Contents of Volume 1, COMMUNICATIONS .................................................................................................
Outline of Contents of Volume 2, INDUSTRIAL ..... ......... ... .... ... ..... ... ................ ... ..... ..... ....... ...... ....... ........... ........ ......
Cross Reference Guide by Company....................................................................................................................... .
SO Availability List........................................................................................................................... ....................
Ordering Information .............................................................................................................................. ...............
1-13
1-16
1-19
1-20
1-21
1-24
1-26
Section 2 - Quality and Reliability
Quality and Reliability....................................................................................................................... .......... .. . . . ... ...
2-3
1-3
1-7
Section 3 - Small Area Networks
SMALL AREA NETWORKS
Introduction to 12C........................................................................................................................... .................. ...
3-3
12C Bus Specifications................................................................................................................ .... .. .... . . .. .. . . .. . .. . ...
3-4
AN16B
The Inter-Integrated Circuit (12c) Serial Bus: Theory and Practical Considerations. .......... .......... ... ... .... ... 3-16
PCF2100
4-Segment LCD Duplex Driver .................................................................................................... (Vol 2)
PCF2111
64-Segment LCD Duplex Driver .................................................................................................. (Vol 2)
PCF2112
32-Segment LCD Static Driver .................................................................................................... (Vol 2)
PCFB200
Single-Chip CMOS Male/Female Speech Synthesizer ....................................................................... (Vol 1)
PCF8570
256 X 8 Static RAM.................................................................................................................
4-3
PCF8571
1k Serial RAM ........................................................................................................................ 4·12
PCF8573
Clock/Timer With 12C Interface................................................................................................... 4-21
PCF8574
8·Bit Remote I/O Expander....... ........ ............... ...... ............................. ........... ........... ... ... .......... 4·33
PCF8576
Universal LCD Driver for Low Multiplex Rates ................................................................................ (Vol 2)
PCF8577
32·/64-Segment LCD Driver for Automotive ................................................................................... (Vol 2)
PCF8591
8·Bit A/D and DI A Converter ................. :................................................................................... (Vol 2)
SAA1057
PLL Radio Tuning Circuit ........................................................................................................... (Vol 1)
SAA1060
32·Segment LED Driver ............................................................................................................. (Vol 2)
SAA1061
16-Segment LED Driver ............................................................................................................. (Vol 2)
SAA3028
IR Receiver...................................................................................................................... ...... 5·47
SAB3013
6·Function Analog Memory (6·Bit 0/ A Converter) ........................................................................... 4-45
SAB3035
FLL TV Tuning Circuit (Eight D/ A Converters) ............................................................................... 4·50
FLL TV Tuning Circuit .............................................................................................................. 4·65
SAB3036
FLL TV Tuning Circuit (Four D/A Converters) ................................................................................ 4-75
SAB3037
14·Bit D/A Converter-Serial lriput. ............................................................................................ (Vol 1)
TDA1540P, D
TDA8400
Frequency Synthesizer.............................................................................................................. 4-88
TDA8440
AudiolVideo Switch.................................................................................................................. 11·80
TDAB442
I/O Expander .......................................................................................................................... 10·101
TDA8443
RGB/YUV Matrix Switch ............................................................................................................ 10·107
TEA1017
13·Bit Series·to·Paraliel Converter ................................................................................................ (Vol 2)
TEA6000
FM IF System and Computer Interface Circuit ................................................................................ (Vol 1)
February 1987
1-3
Signetics Linear Products
Contents
Volume 3: Video
Section 4 - Tuning Systems
TUNER CONTROL PERIPHERALS
PCF8570
256 X 8 Static RAM.................................................................................................................
PCF8571
1K Serial RAM........................................................................................................................
PCF8573
Clock/Calendar With Serial I/O...................................................................................................
PCF8574
8-Bit Remote I/O Expander............................................ ...........................................................
12C CMOS EEPROM (256 X 8) ..................................................................................................
PCF8582
SAB3013
Hex 6-Bit D/ A Converter................................................................. ..........................................
4-3
4-12
4-21
4-33
4-41
4-45
TUNING CIRCUITS
SAB3035
AN157
SAB3036
SAB3037
TDA8400
FLL Tuning and Control Circuit (Eight D/ A Converters) ................................................................... .
Microcomputer Peripheral IC Tunes and Controls a TV Set (SAB3035) .............................................. .
FLL Tuning and Control Circuit .................................................................................................. .
FLL Tuning and Control Circuit (Four D/ A Converters) ................................................................... .
FLL Tuning Circuit With Prescaler .............................................................................................. .
4-50
4-61
4-65
4-75
4-86
PRESCALERS
SABl164/65
SAB1256
1GHz Divide-by-64 Prescaler ..................................................................................................... .
1GHz Divide-by-256 Prescaler .................................................................................................... .
4-92
4-97
TUNER IC (MONOLITHIC)
TDA5030A
VHF Mixer-Oscillator Circuit (VHF Tuner IC) .................................................................................. 4-102
VHF, Hyperband, and UHF Mixer-Oscillator With IF Amp .................................................................. 4-106
TDA5230
Section 5 - Remote Control Systems
SAF1032P
SAF1039P
SAA3004
AN1731
SAA3006
SAA3027
SAA3028
TDA3047
TDA3048
AN 172
AN 173
Remote Control Receiver..........................................................................................................
Remote Control Transmitter ................................................................................................. ;.....
IR Transmitter (448 Commands)..................................................................................................
Low Power Remote Control IR Transmitter and Receiver (SAA3004) ..................................................
IR Transmitter (2K Commands, Low Voltage)............ ...... .......... ........ .................. ........ .............. .....
IR Transmitter (RC-5) ...............................................................................................................
IR Remote Control Transcoder With 12C........................ ................................ .............. ............ .....
IR Preamplifier........................................................................................................................
IR Preamplifier................................................................................................................... .....
Circuit Description of the IR Receiver TDA304 7/3048......................................................................
TDA3047 and TDA3048: Low Power Preamplifiers for IR Remote Control Systems...................... ..........
5-3
5-3
5-13
5-20
5-29
5·38
5-47
5-52
5-56
5-60
5-62
Section 6 - Television Subsystems
TDA4501
TDA4502
TDA4503
TDA4505
Small-Signal
Small-Signal
Small-Signal
Small-Signal
Subsystem
Subsystem
Subsystem
Subsystem
IC for Color TV .......................................................................................
IC for Color TV With Video Switch..............................................................
for Monochrome TV .................................................................................
IC for Color TV .......................................................................................
6-3
6-13
6-15
6-24
Video IF Amplifier and Demodulator, AFT, NPN Tuners...... .......... .................... .................... ...........
Video IF Amplifier and Demodulator, AFT, PNP Tuners....................................................................
Mulitstandard Video IF Amplifier and Demodulator ............ ..............................................................
7-3
7-8
7-14
Section 7 - Video IF
TDA2540
TDA2541
TDA2549
Section 8 - Sound IF and Special Audio Decoding
TBA 120
TDA2545A
TDA2546A
TDA2555
IF Amplilier and Demodulator .................. ............................ ........................ .......................... .....
Quasi-Split Sound IF System......................................................................................................
Quasi-Split Sound IF and Sound Demodulator.......... ...................................... .............. ..................
Dual TV Sound Demodulator......................................................................................................
8-3
8-8
8-11
8-15
Section 9 - SYNC Processing and Generation
TDA2577A
TDA2578A
AN162
AN1621
TDA2579
TDA2593
TDA2594
TDA2595
AN158
TDA8432
February 1987
Sync Circuit With Vertical Oscillator and Driver (With Negative Horizontal Output)..................................
Sync Circuit With Vertical Oscillator and Driver (With Negative Horizontal Output)..................................
A Versatile High-Resolution Monochrome Data and Graphics Display Unit................ .............. ..............
TDA2578A and TDA3651 PCB Layout Directives...... .................. ...................... ..............................
Synchronization Circuit (With Horizontal Output)........ .......... .............................. ...... ...... ............ ......
Horizontal Combination..............................................................................................................
Horizontal Combination..............................................................................................................
Horizontal Combination..............................................................................................................
Features of the TDA2595 Synchronization Processor.......... ........ .....................................................
Deflection Processor With 12 C Bus..............................................................................................
1-4
9-3
9-14
9-25
9-30
9-31
9-41
9-46
9-51
9-57
9-62
Signetics Linear Products
Contents
Volume 3: Video
Section 10 - Color Decoding and Encoding
AN155/A
Multi-Standard Color Decoder With Picture Improvement .................................................................. 10-3
TDA3505
Chroma Control Circuit.............................................................................................................. 10-11
TDA3563
NTSC Decoder With RGB Inputs ................................................................................................ 10-18
AN156
Application of the NTSC Decoder: TDA3563..................................................... ............................. 10-25
TDA3564
NTSC Decoder ........................................................................................................................ 10-38
TDA3566
PAL/NTSC Decoder With RGB Inputs .......................................................................................... 10-47
TDA3567
NTSC Color Decoder................................................................................................................ 10-60
TDA4555/56
Multistandard Color Decoder...................................................................................................... 10-67
Single-Chip Multi-Standard Color Decoder TDA4555/4556 ................................................................. 10-73
AN1551
Color Transient Improvement Circuit (CTI) ........................................................ ............................. 10-82
TDA4565
NTSC Color Difference Decoder ................................................................................................. 10-86
TDA4570
TDA4580
Video Control Combination Circuit With Automatic Cut-off Control ...................................................... 10-91
TDA8442
Quad DAC With 12C Interface .................................................................................................... 10-101
RGB/YUV Switch ..................................................................................................................... 10-107
TDA8443/8443A
TEA2000
NTSC/PAL Color Encoder ......................................................................................................... 10-116
Applications of the TEA2000 Digital RGB Color Encoder. ................................................................. 10-121
AN1561
Section 11 - Special Purpose Video Processing
VIDEO MODULATOR/DEMODULATOR
TDA6800
Video Modulator Circuit...................................................... .......................... ........................ .....
NE568
150MHz Phase-Locked Loop......................................................................................................
11-3
11-6
AID CONVERTERS
7-Bit AID Converter ................................................................................................................. 11-14
PNA7509
An Amplifying, Level Shifting Interface for the PNA7509 Video AID Converter ...................................... 11-20
AN108
8-Bit Analog-to-Digital Converter.................................................................................................. 11-21
TDA5703
D/ A CONVERTERS
NE5150/5151/5152
AN1081
PNA7518
TDA5702
Triple 4-Bit RGB Video 01 A Converter With and Without Memory......................................................
NE5150/51/52 Family of Video DIA Converters .............................................................................
8-Bit Mulitplying DAC ................................................................................................................
8-Bit Digital-to-Analog Converter..................................................................................................
SWITCHING
TDA8440
Video and Audio Switch IC........................................................................................................ 11-60
11-25
11-32
11-52
11-56
HIGH FREQUENCY AMPLIFIERS
Video
NE5204
NE/SAlSE5205
NE/SE5539
AN140
NE5592
NE/SE592
AN141
I1A733/C
Wide-band High-Frequency Amplifier ............................................................................................ 11-66
Wide-band High-Frequency Amplifier................................... ......................... ................................ 11-77
Ultra-High Frequency Operational Amplifier.................................................................................... 11-89
Compensation Techniques for Use With the NE/SE5539.................................................................. 11-97
Video Amplifier ........................................................................................................................ 11-103
Video Amplifier ........................................................................................................................ 11-109
Using the NE592/5592 Video Amplifier. ........................................................................................ 11-118
Differential Video Amplifier ......................................................................................................... 11-123
CCD MEMORY
SAA9001
317K Bit CCD Memory ............................................................................................................. 11-129
Section 12 - Vertical Deflection
TDA2653A
Vertical Deflection.................................................................................................................... 12-3
TDA3651A13653
Vertical Deflection.......................................................... .......................................................... 12-9
TDA3652
Vertical Deflection.................................................................................................................... 12-16
TDA3654
Vertical Deflection Output Circuit................................................................................................. 12-20
Section 13 - Videotex/Teletext
AN153
The 5-Chip Set Teletext Decoder ........................... .......... ...........................................................
AN154
Teletext Decoders: Keeping Up With the Latest Technology Advances................................................
SAA5025
Teletext Timing Chain for 525-Line System ...................................................................................
SAA5030
Teletext Video Input Processor ...................................................................................................
SAA5040
Teletext Acquisition and Control Circuit.. .......................................................................................
SAA5045
Gearing and Address LogiC Array for USA Teletext (GALA)... ............. ............. .................................
SAA5050/55
Teletext Character Generator........................................... .......................... ......................... ... .....
SAA5230
Teletext Video Processor...........................................................................................................
SAA5350
Single-Chip Color CRT Controlier (625-Line System)........................................................................
AN152
SAA5350: A Single-Chip CRT Controlier .......................................................................................
February 1987
1-5
13-3
13-8
13-14
13-25
13-32
13-44
13-48
13-61
13-67
13-89
•
Signetics Linear Products
Contents
Volume 3: Video
Section 14-SMPS for TV/Monitor
TDA2582
TEA 1039
Control Circuit for Power Supplies............................................................................................... 14-3
Control Circuit for Switched-Mode Power Supply............................................................................. 14-12
Section 15 - Packaging Information
Substrate Design Guidelines for Surface Mounted Devices ........................................................... :................................
Test and Repair ...................................................................................................................................................
Fluxing and Cleaning ................................................................................................................................ ............
Thermal Considerations for Surface-Mounted Devices...................................................................................................
Package Outlines for Prefixes ADC, AM, CA, DAC, LF, LM, MC, NE, SA, SE, SG, 1lA, and ULN .........................................
Package Outlines for Prefixes HEF, OM, MEA, PCD, PCF, PNA, SAA, SAB, SAF, TBA, TCA, TDA, TDD and TEA ...................
15-3
15-14
15-17
15-22
15-35
15-52
Section 16 - Sales Office Listings
Sales Office Listings ...................................................................................................................................... " . . .. .
February 1987
1-6
16-3
Signetics
Alphanumeric
Product list
Linear Products
Vol 1
ADC0801/2/3/4/5
ADC0820
AM6012
CA3089
DAC-08 Series
DAC800
HEF4750V
HEF4751V
ICM7555
LF198
LF298
LF398
LM111
LM119
LM124
LM139/A
LM158
LM193/A
LM211
LM219
LM224
LM239/A
LM258
LM293/A
LM311
LM319
LM324
LM339/A
LM358
LM393/A
LM1870
LM2901
LM2903
MC1408-7
MC1408-8
MC1458
MC1488
MC1489/A
MC1496
MC1508-8
MC1558
MC3302
MC3303
MC3361
MC3403
MC3410
MC3410C
MC3503
MC3510
NE/SE521
NE/SE522
NE/SE527
NE/SE529
NE/SE530
NE/SE531
February 1987
8-Bit CMOS AID Converter
8-Bit CMOS AID Converter
12-Bit Multiplying 0/ A Converter
FM IF System
8-Bit High-Speed Multiplying D/A Converter
12-Bit 0/ A Converter
Frequency Synthesizer
Universal Divider
CMOS Timer
Sample-and-Hold Amplifier
Sample-and-Hold Amplifier
Sample-and-Hold Amplifier
Voltage Comparator
Dual Voltage Comparator
Low Power Quad Operational Amplifier
Quad Voltage Comparator
Low Power Dual Operational Amplifier
Low Power Dual Voltage Comparator
Voltage Comparator
Dual Voltage Comparator
Low Power Quad Operational Amplifier
Quad Voltage Comparator
Low Power Dual Operational Amplifier
Low Power Dual Voltage Comparator
Voltage Comparator
Dual Voltage Comparator
Low Power Quad Operational Amplifier
Quad Voltage Comparator
Low Power Dual Operational Amplifier
Low Power Dual Voltage Comparator
Stereo Demodulator With Blend
Quad Voltage Comparator
Low Power Dual Voltage Comparator
8-Bit Multiplying 0/ A Converter
8-Bit Multiplying 0/ A Converter
General Purpose Operational Amplifier
Quad Line Driver
Quad Line Receivers
Balanced Modulator/Demodulator
8-Bit Multiplying 0/ A Converter
General Purpose Operational Amplifier
Quad Voltage Comparator
Quad Low Power Operational Amplifier
Low Power FM IF
Quad Low Power !Jperational Amplifier
10-Bit High-Speed Multiplying 0/ A Converter
10-Bit High-Speed Multiplying 0/ A Converter
Quad Low Power Operational Amplifier
10-Bit High-Speed Multiplying 0/ A Converter
High-Speed Dual Differential Comparator/Sense Amp
High-Speed Dual Differential Comparator/Sense Amp
Voltage Comparator
Voltage Comparator
High Slew Rate Operational Amplifier
High Slew Rate Operational Amplifier
1-7
Vol 2
5-11
5-18
5-100
4-110
5-111
5-124
4-174
4-184
7-3
5-317
5-317
5-317
5-254
5-257
4-29
5-263
4-123
5-271
5-254
5-257
4-29
5-263
4-123
5-271
5-254
5-257
4-29
5-263
4-123
5-271
7-114
5-4
5-8
4-60
5-263
5-271
5-130
5-130
4-34
6-4
6-8
5-130
4-34
5-263
4-40
4-116
4-40
5-136
5-136
4-40
5-136
5-285
5-290
5-296
5-301
4-53
4-60
Vol 3
Signetics Linear Products
Alphanumeric Product list
Vol 1
NE/SA532
NE/SE538
NE542
NE544
NE/SE555
NE/SAlSE556/1
NE/SAlSE558
NE/SE564
NE/SE565
NE/SE566
NE/SE567
NE568
NE570
NE/SA571
NE/SA572
NE575
NE587
NE589
NE590
NE591
NE/SE592
NE/SA594
NE602
NE604
NE605
NE612
NE614
NE645
NE646
NE648
NE649
NE650
NE/SE4558
NE/SE5018
NE/SE5019
NE5020
NE/SE5030
NE5034
NE5036
NE5037
NE5044
NE5045
NE5050
NE5060
NE5080
NE5081
NE5090
NE/SAlSE51 05/ A
NE/SE5118
NE/SE5119
NE5150
NE5151
NE5152
NE5170
NE5180
NE5181
NE5204
NE/SAlSE5205
NE/SA5212
NE/SA5230
NE5240
NE/SE5410
NE/SE5512
February 1987
Low Power Dual Operational Amplifier
High Slew Rate Operational Amplifier
Dual Low-Noise Preamplifier
Servo Amplifier
Timer
Dual Timer
Quad Timer
Phase-Locked Loop
Phase-Locked Loop
Function Generator
Tone Decoder/Phase-Locked Loop
150MHz Phase-Locked Loop
Compandor
Compandor
Programmable Analog Compandor
Low Voltage Compandor
LED Decoder/Driver
LED Decoder/Driver
Addressable Peripheral Drivers
Addressable Peripheral Drivers
Video Amplifier
Vacuum Fluorescent Display Driver
Low Power VHF Mixer/Oscillator
Low Power FM IF System (Independent IF Amp)
Low Power FM IF System
Low Power VHF Mixer/Oscillator
Low Power FM IF System (Independent IF Amp)
Dolby Noise Reduction Circuit
Dolby Noise Reduction Circuit
Low Voltage Dolby Noise Reduction Circuit
Low Voltage Dolby Noise Reduction Circuit
Dolby B-Type Noise Reduction Circuit
Dual General Purpose Operational Amplifier
8-Bit Microprocessor-Compatible D/A Converter
8-Bit Microprocessor-Compatible D/ A Converter
10-Bit Microprocessor-Compatible DJ A Converter
10-Bit High-Speed Microprocessor-Compatible A/D
8-Bit High-Speed AID Converter
6-Bit A/D Converter (Serial Output)
6-Bit AID Converter (Parallel Outputs)
Programmable Seven-Channel RC Encoder
Seven-Channel RC Decoder
Power Line Modem
Sample-and-Hold Circuit
High-Speed FSK Modem Transmitter
High-Speed FSK Modem Receiver
Addressable Relay Driver
12-Bit High-Speed Comparator
8-Bit Microprocessor-Compatible D/ A Converter
8-Bit Microprocessor-Compatible D/ A Converter
RGB Video D/ A Converter
RGB Video D/A Converter
RGB Video D/ A Converter
Octal Line Driver
Octal Line Receiver
Octal Line Receiver
Wideband High Frequency Amplifier
Wideband High Frequency Amplifier
Transimpedance Amplifier
Low Voltage Operational Amplifier
Dolby Digital Audio Decoder
10-Bit High-Speed Multiplying D/ A Converter
Dual High Performance Operational Amplifier
1-8
Vol 2
Vol 3
4-123
4-68
7-167
8-34
7-47
7-32
7-38
4-257
4-291
4-304
4-313
4-333
4-357
4-357
4-364
4-373
4-46
4-69
4-119
4-142
4-90
4-146
7-230
7-230
7-235
7-235
7-240
11-6
6-49
6-59
6-34
6-34
4-231
6-74
11-109
4-178
4-201
4-48
5-144
5-150
5-156
5-31
5-36
5-43
5-50
8-4
8-16
5-26
5-322
5-44
5-48
5-14
5-21
5-21
4-3
4-14
5-63
6-28
5-277
5-164
5-169
5-181
5-181
5-181
6-14
6-21
6-21
4-155
4-166
4-267
4-109
7-226
5-208
4-75
11-25
11-25
11-25
11-66
11-77
Signetics Linear Products
Alphanumeric Product list
Vol 1
NE/SE5514
NE5517/A
NE5520
NE/SE5521
NE/SE55321 A
NE5533/A
NE5534A
NE/SE5535
NE/SE5537
NE/SE5539
NE/SE5560
NE/SE5561
NE/SAlSE5562
NE5568
NE/SAlSE5570
NE5592
NE5900
OM8210
PCD3310
PCD3311
PCD3312
PCD3315
PCD3360
PCF1303
PCF2100
PCF2111
PCF2112
PCF8200
PCF8566
PCF8570
PCF8571
PCF8573
PCF8574
PCF8576
PCF8577
PCF8582
PCF8591
PNA7509
PNA7518
SA532
SA534
SA556/1
SA558
SA571
SA572
SA594
SA723C
SA741C
SA747C
SA1458
SA5205
SA5212
SA5230
SA5534A
SA5562
SA5570
SAA1027
SAA1057
SAA1060
SAA1061
SAA1099
SAA3004,T
SAA3006
February 1987
Quad High Performance Operational Amplifier
Dual Operational Transconductance Amplifier
LVDT Signal Conditioner
LVDT Signal Conditioner
Internally-Compensated Dual Low-Noise Operational Amp
Single and Dual Low-Noise Operational Amp
Single and Dual Low-Noise Operational Amp
Dual High Slew Rate Op Amp
Sample-and-Hold Amplifier
Ultra High Frequency Operational Amplifier
Switched-Mode Power Supply Control Circuit
Switched-Mode Power Supply Control Circuit
SMPS Control Circuit, Single Output
Switched-Mode Power Supply Controller
Three-Phase Brushless DC Motor Driver
Video Amplifier
Call Progress Decoder
Speech Encoding and Editing System
Pulse and DTMF Dialer With Redial
DTMF/Modem/Musical Tone Generator
DTMF/Modem/Musical Tone Generator
CMOS Redial and Repertory Dialer
Programmable Multi-Tone Telephone Ringer
18-Element LCD Bar Graph LCD Driver
LCD Duplex Driver
LCD Duplex Driver
LCD Driver
Single-Chip CMOS Male/Female Speech Synthesizer
Universal LCD Driver for Low Multiplex Rates
256 X 8 Static RAM
1K Serial RAM
Clock/Calendar With Serial I/O
8-Bit Remote I/O Expander
Universal LCD Driver for Low Multiplex Rates
32/64 Segment LCD Driver for Automotive
12C CMOS EPROM (256 X 8)
8-Bit AID and 01 A Converter
7-Bit AID Converter
8-Bit Multiplying DAC
Low Power Dual Operational Amplifier
Low Power Quad Operational Amplifier
Dual Timer
Quad Timer
Compandor
Programmable Analog Compandor
Vacuum Fluorescent Display Driver
Precision Voltage Regulator
General Purpose Operational Amplifier
Dual Operational Amplifier
General Purpose Operational Amplifier
Wide-band High Frequency Amplifier
Transimpedance Amplifier
Low Voltage Operational Amplifier
Single and Dual Low-Noise Operational Amp
SMPS Control Circuit, Single Output
Three-Phase Brushless DC Motor Driver
Stepper Motor Driver
PLL Radio Tuning Circuit
LED Display Interface
Output Port Expander
Stereo Sound Generator for Sound Effects and Music
IR Transmitter (448 Commands)
IR Transmitter (2K Commands, Low Voltage)
1-9
4-26
4-40
6-3
8-3
6-10
6-24
6-24
6-37
6-45
Vol 2
4-81
4-251
5-338
5-358
4-87
4-93
4-93
4-129
5-327
4-211
8-67
8-86
8-97
8-129
8-45
4-225
Vol 3
11-89
11-103
6-79
6-83
6-90
6-95
8-6
6-100
7-12
7-24
6-120
6-141
4-3
4'12
4-21
4-33
4-41
5-59
5-71
5-217
4-123
4-29
7-32
7-38
11-14
11-52
4-357
4-364
4-14
5-63
6-74
8-211
4-142
4-148
4-34
4-166
4-267
4-109
4-93
8-97
8-45
8-49
11-77
4-193
6-152
6-155
8-16
5-13
5-29
Signetics Linear Products
Alphanumeric Product List
Vol 1
SAA3027
SAA3028
SAA5025D
SAA5030
SAA5040
SAA5045
SAA5050
SAA5055
SAA5230
SAA5350
SAA7210
SAA7220
SAA9001
SABl164
SABl165
SAB1256
SAB3013
SAB3035
SAB3036
SAB3037
SAF1032P
SAF1039P
SE521
SE522
SE527
SE529
SE530
SE531
SE532
SE538
SE555
SE555C
SE556-1C
SE556/-1
SE558
SE564
SE565
SE566
SE567
SE592
SE4558
SE5018
SE5019
SE5030
SE5118
SE5119
SE5205
SE5212
SE541 0
SE5512
SE5514
SE5521
SE5532/A
SE5534A
SE5535
SE5537
SE5539
SE5560
SE5561
SE5562
SE5570
SG1524C
SG2524C
February 1987
IR Transmitter
IR Remote Control Transcoder With 12C
Teletext Timing Chain for 525-Line System
Teletext Video Input Processor
Teletext Acquisition and Control Circuit
Gearing and Address Logic Array (GALA)
Teletext Character Generator
Teletext Character Generator
Teletext Video Processor
Single-Chip Color CRT Controller (625-Line System)
Compact Disk Decoder
Digital Filter and Interpolator for Compact Disk
317k-Bit CCD Memory
1GHz Divide-by-64 Prescaler
1GHz Divide-by-64 Prescaler
1GHz Divide-by-256 Prescaler
Hex 6-Bit 0/ A Converter
FLL Tuning and Control Circuit (Eight 0/ A Converters)
FLL Tuning and Control Circuit
FLL Tuning and Control Circuit (Four 0/ A Converters)
Remote Control Receiver
Remote Control Transmitter
High-Speed Dual Differential Comparator/Sense Amp
High-Speed Dual Differential Comparator/Sense Amp
Voltage Comparator
Voltage Comparator
High Slew Rate Operational Amplifier
High Slew Rate Operational Amplifier
Low Power Dual Operational Amplifier
High Slew Rate Operational Amplifier
Timer
Timer
Dual Timer
Dual Timer
Quad Timer
Phase-Locked Loop
Phase-Locked Loop
Function Generator
Tone Decoder/Phase-Locked Loop
Video Amplifier
Dual General Purpose Operational Amplifier
8-Bit Microprocessor-Compatible 0/ A Converter
8-Bit Microprocessor-Compatible 0/ A Converter
10-Bit High-Speed Microprocessor-Compatible AID Converter
8-Bit Microprocessor-Compatible 0/ A Converter
8-Bit Microprocessor-Compatible 0/A Converter
Wide-band High Frequency Amplifier
Transimpedance Amplifier
10-Bit High-Speed Multiplying 0/A Converter
Dual High Performance Operational Amplifier
Quad High Performance Operational Amplifier
LVDT Signal Conditioner
Internally-Compensated Dual Low-Noise Operational Amp
Single and Dual Low-Noise Operational Amp
Dual High Slew Rate Op Amp
Sample-and-Hold Amplifier
Ultra High-Frequency Operational Amplifier
Switched-Mode Power Supply Control Circuit
Switched-Mode Power Supply Control Circuit
SMPS Control Circuit, Single Output
Three-Phase Brushless DC Motor Driver
Improved SMPS Push-Pull Controller
Improved SMPS Push-Pull Controller
1-10
Vol 2
Vol 3
5-38
5-47
13-14
13-25
13-32
13-44
13-48
13-48
13-61
13-67
7-329
7-343
11-129
4-92
4-92
4-97
4-45
4-50
4-65
4-75
5-3
5-3
4-163
4-163
4-168
5-285
5-290
5-296
5-301
4-53
4-60
4-123
4-68
7-47
7-47
7-32
7-32
7-38
4-257
4-291
4-304
4-313
4-46
4-14
5-63
4-26
4-231
4-48
5-144
5-150
5-31
5-164
5-169
4-166
4-267
5-208
4-75
4-81
5-358
4-87
4-93
4-129
5-327
4-211
8-67
8-86
8-97
8-45
8-131
8-131
11-109
11-77
11-89
Signetlcs Linear Products
Alphanumeric Product List
Vol 1
SG3524
SG3524C
SG3526A
TBA120
TCA520
TDA1001B
TDA1005A
TDA10l0A
TDA10llA
TDA1013A
TDA1015
TDA1020
TDA1023
TDA1029
TDA1072A
TDA1074A
TDA1510
TDA1512
TDA1514
TDA1515A
TDA1520A
TDA1521
TDA1522
TDA1524A
TDA1534
TDA1535
TDAl540
TDA1541
TDA1574
TDA1576
TDA1578A
TDA1721
TDA2540
TDA2541
TDA2545A
TDA2546A
TDA2549
TDA2555
TDA2577A
TDA2578A
TDA2579
TDA2582
TDA2593
TDA2594
TDA2595
TDA2611A
TDA2653A
TDA3047,T
TDA3048,T
TDA3505
TDA3563
TDA3564
TDA3566
TDA3567
TDA3651A
TDA3652
TDA3653
TDA3654
TDA3810
TDA4501
TDA4502
TDA4503
February 1987
SMPS Control Circuit
Improved SMPS Push-Pull Controller
Switched-Mode Power Supply Control Circuits
IF Amplifier and Demodulator
Operational Amplifier (Low Voltage)
Interference Suppressor
Frequency Multiplex PLL Stereo Decoder
6W Audio Amplifier With Preamplifier
2 to 6W Audio Power Amplifier With Preamplifier
4W Audio Amplifier With DC Volume Control
1 to 4W Audio Amplifier With Preamplifier
12W Audio Amplifier With Preamplifier
Time-Proportional Triac Trigger
Stereo Audio Switch
AM Receiver Circuit
DC-Controlled Dual Potentiometers
2 X 12W Audio Amplifier
12 to 20W Audio Amplifier
40W High-Performance Hi-Fi Amplifier
24W BTL Audio Amplifier
20W Hi-Fi Audio Amplifier
2 X 12W Hi-Fi Audio Power Amplifier
Stereo Cassette Preamplifier
Stereo-Tone/Volume Control Circuit
14-Bit AID Converter, Serial Output
High Performance Sample and Hold Amplifier With Resolution to
16 Bits
14-Bit DAC - Serial Output
16-Bit Dual 0/ A Converter, Serial Output
FM Front End IC (VHF Mixer and Oscillator)
FM IF System
PLL Stereo Decoder
8-Bit Multiplying 0/A Converter
Video IF Amplifier and Demodulator, AFT, NPN Tuners
Video IF Amplifier and Demodulator, AFT, PNP Tuners
Quasi-Split Sound IF System
Quasi-Split Sound IF and Sound Demodulator
Multistandard Video IF Amplifier and Demodulator
Dual TV Sound Demodulator
Sync Circuit With Vertical Oscillator and Driver
Sync Circuit With Vertical Oscillator and Driver
Synchronization Circuit
Control Circuit for Power Supplies
Horizontal Combination
Horizontal Combination
Horizontal Combination
5W Audio Output Amplifier
Vertical Deflection Circuit With Oscillator
IR Preamplifier
IR Preamplifier
Chroma Control Circuit
NTSC Decoder With RGB Inputs
NTSC Decoder
PALINTSC Decoder With RGB Inputs
NTSC Color Decoder
Vertical Deflection
Vertical Deflection
Vertical Deflection
Vertical Deflection
Spatial, Stereo, Pseudo-Stereo Processor
Small Signal Subsystem IC for Color TV
Complete Video IF IC With Vertical and Horizontal Sync
Small Signal Subsystem for Monochrome TV
1-11
Vol 2
Vol 3
8-184
8-131
8-192
8-3
4-138
7-43
7-119
7-246
7-251
7-255
7-267
7-272
8-243
7-180
7-3
7-189
7-276
7-288
7-293
7-296
7-307
7-317
7-174
7-196
5-78
7-355
7-360
4-96
4-156
7-129
5-335
5-221
5-233
5-239
7-3
7-8
8-8
8-11
7-14
8-15
9-3
9-14
9-31
14-3
9-41
9-46
9-51
7-332
12-3
5-52
5-56
10-11
10-18
10-38
10-47
10-60
12-9
12-16
12-9
12-20
7-204
6-3
6-13
6-15
•
Signetics Linear Products
Alphanumeric Product list
Vol 1
TDA4505
TDA4555
TDA4565
TDA4570
TDA4580
TDA5030A
TDA5040
TDA5230
TDA5702
TDA5703
TDA5708
TDA5709
TDA6800
TDA7000
TDA7010T
TDA7021T
TDA7040T
TDA7050
TDA8400
TDA8432
TDA8440
TDA8442
TDA8443/A
TDA8444
TDD1742
TEA1017
TEAl 039
TEA1046A
TEAl 060
TEA1061
TEAl 067
TEAl 068
TEAl 075
TEAl 080
TEA2000
TEA5550
TEA5560
TEA5570
TEA5580
TEA5581
TEA6000
TEA6300
UC1842
UC2842
UC3842C
ULN2003
ULN2004
jlA723
jlA723C
jlA733
jlA733/C
jlA741
jlA741C
jlA747
jlA747C
jlA758
February 1987
Small Signal Subsystem IC for Color TV
Multistandard Color Decoder
Color Transient Improvement Circuit (CTI)
NTSC Color Difference Decoder
Video Control Combination Circuit With Automatic Cut-Off Control
VHF Mixer-Oscillator (VHF Tuner IC)
Brushless DC Motor Driver
VHF/UHF Mixer-Oscillator
8-Bit Dig~al-to-Analog Converter
8-Bit Analog-to-Digital Converter
Photo Diode Signal Processor
Radial Error Signal Processor
Video Modulator Circuit
Single-Chip FM Radio Circuit
Single-Chip FM Radio Circuit (SO Package)
Single Chip FM Radio Circu~
PLL Stereo Decoder (Low Voltage)
Low Voltage Mono/Stereo Power Amplifier
FLL Tuning Circuit With Prescaler
Deflection Processor With 12C Bus
Video/ Audio Switch
Quad DAC With 12C Interface
RGB/YUV Switch Inputs
Octuple 6-Bit 0/ A Converter With 12C Bus
CMOS Frequency Synthesizer
13-Bit Serial-to-Parallel Converter
Control Circuit for Switched-Mode Power Supply
Transmission Interface With DTMF
Telephone Transmission Circuit With Dialer Interface
Telephone Transmission Circuit With Dialer Interface
Low Voltage Transmission IC With Dialer Interface
Low Voltage Transmission IC With Dialer Interface
DTMF Generator for Telephone Dialing
Supply IC for Telephone Peripherals
Digital RGB to NTSC/PAL Encoder
AM Radio Circuit
FM IF System
AM/FM Radio Receiver Circuit
PLL Stereo Decoder
PLL Stereo Decoder
FM IF System and Computer Interface (MUSTI) Circuit
12 C Active Tone Controller With Source Inputs
Current Mode PWM Controller
Current Mode PWM Controller
Current Mode PWM Controller
High Voltage/Current Darlington Transistor Array
High Voltage/Current Darlington Transistor Array
Precision Voltage Regulator
Precision Voltage Regulator
Differential Video Amplifier
Differential Video Amplifier
General Purpose Operational Amplifier
General Purpose Operational Amplifier
Dual Operational Amplifier
Dual Operational Amplifier
FM Stereo Multiplex Decoder Phase-Locked Loop
1-12
Vol 2
Vol 3
6-24
10-67
10-82
.10-86
10-91
4-102
4-102
8-57
4-106
5-243
5-84
4-106
11-56
11-21
7-366
7-368
11-3
7-49
7-85
7-90
7-138
7-326
4-220
4-86
9-62
11-60
10-101
10-107
7-210
5-247
4-226
6-158
8-203
14-12
6-53
6-65
6-65
6-76
6-114
6-125
6-135
10-116
7-26
7-96
7-34
7-144
7-147
7-104
7-216
8-216
8-216
8-216
6-42
6-42
8-211
8-211
4-245
4-245
4-142
4-142
4-148
4-148
7-154
11-123
11-123
Signetics
Application Notes
by Product Group
Linear Products
Vol 1
Vol 2
Vol 3
4-34
4-55
4-75
4-79
4-87
4-130
4-140
4-219
4-240
11-97
11-118
Signal Processing
AN140
AN141
AN198
AN1981
AN1982
AN199
AN1991
Compensation Techniques for Use With the SE/NE5539
Using the NE592/5592 Video Amplifier
Designing With SAlNE602
New Low Power Single Sideband Circuits (NE602)
Applying the Oscillator of the NE602 in Low Power Mixer Applications
Designing With the NE/SA604
Audio Decibel Level Detector With Meter Driver
4-189
4-199
Frequency Synthesis
AN196
AN197
Single-Chip Synthesizer For Radio Tuning
Analysis and Basic Application of the SAA1057 (VBA8101)
4-201
4-208
Phase-Locked Loops
AN1??
AN178
AN179
AN180
AN1081
AN181
AN182
AN183
AN184
AN185
AN186
AN187
AN188
An Overview of Phase-Locked Loops (PLL)
Modeling the PLL
Circuit Description of the NE564
The NE564: Frequency Synthesis
10.8MHz FSK Decoder With the NE564
A 6MHz FSK Converter Design Example for the NE564
Clock Regenerator With Crystal Controlled Phase-Locked VCO
Circuit Description of the NE565
Typical Applications With NE565
Circuit Description of the NE566
Waveform Generators With the NE566
Circuit Description of the NE567 Tone Decoder
Selected Circuits Using the NE567
4-236
4-241
4-266
4-273
4-277
4-280
4-282
4-297
4-301
4-309
4-310
4-325
4-330
Applications for Compandors: NE570/571/SA571
Automatic Level Control: NE572
Compander Cookbook
4-341
4-372
4-350
Compandors
AN174
AN175
AN176
Line Drivers/Receivers
AN113
AN195
AN1950
AN1951
Applications Using the MC1488/1489 Line Drivers and Receivers
Applications Using the NE5080/5081
Exploring the Possibilities in Data Communications
NE5050: Power Line Modem Application Board Cookbook
5-11
5-52
5-60
5-30
Telephony
AN1942
AN1943
TEA 1067: Application of the Low Voltage Versatile Transmission Circuit
TEA 1067: Supply of Peripheral Circuits With the TEA 1067 Speech Circuit
6-88
6-108
TDA 1072A: Integrated AM Receiver
Designing With the SA/NE602
New Low Power Single Sideband Circuits (NE602)
Applying the Oscillator of the NE602 in Low Power Mixer Applications
Stereo Decoder Applications Using the "A758
A Complete FM Radio on a Chip
TDA7000 for Narrow-Band FM-Reception
Designing With the SAlNE604
Audio Decibel Level Detector With Meter Driver (NE604)
7-15
4-75
4-79
4-87
7-159
7-54
7-69
7-130
7-140
Radio Circuits
AN1961
AN198
AN1981
AN1982
AN191
AN192
AN193
AN199
AN1991
February 1987
1-13
6-11
Signetics linear Products
Application Notes by Product Group
Vol 1
Vol 2
Vol 3
Audio Circuits
AN14B
AN14Bl
AN149
AN1491
AN190
Audio Amplifier With TDA1013
Car Radio Audio Power Amplifiers up to 20W With the TDA1515
20W Hi-Fi Power Amplifier With the TDA 1520A
Car Radio Audio Power Amplifiers up to 24W With the TDA1510
Applications of Low Noise Stereo Amplifiers: NE542
7-25B
7-300
7-312
7-2BO
7-171
Operational Amplifiers
AN142
AN144
AN1441
AN1511
AN160
AN164
AN165
AN166
Audio Circuits Using the NE5532/33/34
Applications for the NE5512 and NE5514
Applications for the NE5514
Low Voltage Gated Generator: NE5230
Applications for the MC3403
Explanation of Noise
Integrated Operational Amplifier Theory
Basic Feedback Theory
4-101
4-7B
4-B4
4-121
4-45
4-6
4-16
4-25
High Frequency Amps
AN199
AN1991
Designing With the NE/SA604
Audio Decibel Level Detector Wnh Meter Driver
4-130
4-140
4-169
4-199
4-34
4-55
4-219
4-240
Video Amps
AN140
AN141
Compensation Techniques for Use With the SE/NE5539
Using the NE592/5592 Video Amplifier
11-97
11-116
Transconductance
AN145
NE5517: General Description and Applications for Use With the NE5517/A
Transconductance Amplifier
4-264
Data Conversion
AN100
AN10l
AN105
AN106
AN10B
AN10Bl
ANt09
AN110
An Overview of Data Converters
Basic DACs
Digital Attenuator
Using the DACOB Without a Negative Supply
An Amplifiying, Level Shifting Interface for the PNA7507 Video DI A Converter
NE5150/51/52: Family of Video D/A Converters
Microprocessor-Compatible DACs
Monolithic 14-Bit DAC With B5dB SIN RatiO
5-3
5-91
5-96
5-123
5-77
5-16B
5-174
5-226
Applications for the NE521/522/527/529
5-306
Comparators
AN116
Position Measurement
ANI1B
ANl1Bl
ANllB2
LVDT Signal Conditioner: Applications Using the NE5520
NE5521 in a Modulated Light Source Design Application
NE5521 in Multi-faceted Applications
5-343
5-363
5-367
Line Drivers/Receivers
AN113
Applications Using the MC14BB/14B9 Line Drivers and Receivers
5-11
6-11
Display Drivers
AN112
LED Decoder Drivers: Using the NE5B7 and NE5B9
Serlal-ta-Parallel Converters
AN103
6-6B
6-163
13-Bit Serial-tO-Parallel Converter
Timers
AN170
AN171
February 19B7
NE555 and NE556 Applications
NE55B Applications
7-53
7-42
1-14
11-20
11-32
Signetlcs Unear Products
Application Notes by Product Group
Vol 1
Vol 2
Vol 3
Motor Control and Sensor Circuits
AN127
AN131
AN1311
AN132
AN133
AN1341
Using the SAA1027 With Airpax Four-Phase Stepper Motors
Applications Using the NE5044 Encoder
Low Cost AID Conversion Using the NE5044
Applications Using the NE5045 Decoder
Applications Using the NE544 Servo Amplifier
Control System for Home Computer Robotics
8-52
8-12
8-14
8-22
8-40
8-23
Switched-Mode Power Supply
AN120
AN121
AN122
AN123
AN124
AN125
AN126
AN1261
AN128
AN1291
An Overview of SMPS
Forward Converter Application Using the NE5560
NE5560 Push-Pull Regulator Application
NE5561 Applications
External Synchronization for the NE5561
Progress in SMPS Magnetic Component Optimization
Applications Using the SG3524
High Frequency Ferrite Power Transformer and Choke
Introduction to the Series-Resonant Power Supply
TDA1023: Design of Time-Proportional Temperature Controls
8-62
8-82
8-83
8-91
8-96
8-225
8-190
8-138
8-235
8-251
Tuning Circuits
AN157
Microcomputer Peripheral IC Tunes and Controls a TV Set: SAB3035
4-61
Remote Control System
AN172
AN173
AN1731
Circuit Description of the Infrared Receiver TDA3047/TDA3048
Low Power Preamplifiers for IR Remote Control Systems
SAA3004: Low Power Remote Control IR Transmitter and Receiver
Preamplifiers
5-60
5-62
5-20
Synch Processing and Generator
AN158
AN162
AN1621
Features of the TDA2595 Synchronization Processor
A Versatile High-Resolution Monochrome Data and Graphics
Directives for a Print Layout Design on Behalf of the
IC Combination TDA2578A and TDA3651
Color Decoding and Encoding
AN155/A
AN1551
AN156
AN1561
Multi-Standard Color Decoder With Picture Improvement
Single-Chip Multi-Standard Color Decoder TDA4555/4556
Application of the NTSC Decoder: TDA3563
Application of the TEA2000 Color Encoder
9-57
9-25
9-30
10-3
10-73
10-25
10-121
Videotex/Teletext
AN152
AN153
AN154
February 1987
A Single-Chip CRT Controller
The 5 Chip Set Teletext Decoder
Teletext Decoders: Keeping up With the Latest Technology Advances
1-15
13-89
13-3
13-8
I by Part Numbers
Application Notes
Signetics
Linear Products
DAC08
MC1488
MC1489/A
MC1496/1596
AN106:
ANl13:
ANl13:
AN189:
MC3403
NE5044
AN160:
AN131:
AN1311:
AN1341:
AN132:
AN1951:
NE5045
NE5050
NE5080/5081
NE5517
AN195:
AN1950:
AN1081:
ANl16:
AN118:
AN1511:
AN116:
ANl16:
AN1511:
AN190:
AN133:
ANl44:
AN1441:
AN145:
NE5520
ANl18:
NE5521
AN1181:
NE5532/33/34
NE5539
ANl182:
AN142:
AN140:
NE5150/51 152
NE521
NE522
NE5230
NE527
NE529
NE531
NE542
NE544
NE5512/5514
NE555
NE556
NE/SE5560
AN170:
AN170:
AN121:
AN122:
AN125:
NE/SE5561
AN123:
AN124:
AN125:
NE/SE5562
AN125:
NE/SE5568
AN125:
NE558
NE564
AN171:
AN179:
AN180:
AN1801:
AN181:
February 1987
Using the DAC08 Without a Negative Supply
Using the MC1488/89 Line Drivers and Receivers
Using the MC1488/89 Line Drivers and Receivers
Balanced ModulatorIDemodulator Applications Using
the MC1496/1596
Applications for the MC3403
Applications Using the NE5044 Encoder
Low Cost AID Conversion Using the NE5044
Control System for Home Computer and Robotics
Applications Using the NE5045 Decoder
NE5050: Power Line Modem Application Board
Cookbook
Applications Using the NE5080, NE5081
Exploring the PossibilHies in Data Communications
NE5150/51152 Family of Video D/A Converters
Applications for the NE521/522/527/529
Applications for the NE521/522/527/529
Low Voltage Gated Generator: NE5230
Applications for the NE521/522/527/529
Applications for the NE521/522/527/529
Low Voltage Gated Generator: NE5230
Applications of Low Noise Stereo Amplifiers: NE542
Applications Using the NE544 Servo Amplijier
Applications for the NE5512
Applications for the NE5514
NE5517: General Description and Applications for
Use With the NE5517/A Transconductance Amplifier
LVDT Signal Conditioner: Applications Using the
NE5520
NE5521 in a Modulated Light Source Design
Application
NE5521 in Multi·faceted Applications
AudiO Circuits Using the NE5532/33/34
Compensation Techniques for Use With the
SE/NE5539
NE555 and NE556 Applications
NE555 and NE556 Applications
Forward Converter Application Using the NE5560
NE5560 Push·Pull Regulator Application
Progress in SMPS Magnetic Component
Optimization
NE5561 Applications
External Synchronization for the NE5561
Progress in SMPS Magnetic Component
Optimization
Progress in SMPS Magnetic Component
Optimization
Progress in SMPS Magnetic Component
Optimization
NE558 Applications
Circuit Description of the NE564
The NE564: Frequency Synthesis
10.8MHz FSK Decoder With the NE564
A 6MHz FSK Converter Design Example for the
NE564
1-16
Vol 1
Vol 2
5·11
5·11
5·123
6·11
6·11
Vol 3
4·64
4-45
8·12
8·14
8·23
8·22
5·30
5·52
5·60
5·188
5·306
5·306
4·121
5-306
5-306
4·121
11-32
7·171
8·40
4·78
4-84
4·264
5·343
5·363
5-367
4·101
4·34
4·219
7·53
7·53
8·82
8·83
8·225
8·91
8·96
8·225
8·225
8·225
7-42
4·266
4·273
4·277
4·280
11·97
Signetics Unear Products
Application Notes by Part Numbers
Vol 1
NE564
AN182:
NE565
AN183:
AN184:
AN185:
AN186:
AN187:
AN188:
AN174:
AN175:
AN112:
AN141:
AN198:
AN1981:
AN1982:
NE566
NE567
NE570/571/SA571
NE572
NE587/589
NE592/5592
NE/SA602
NE/SA604
AN199:
AN1991:
PCF8570
AN167:
PNA7509
AN108:
SAA1027
AN127:
SAA1057
SAA3004
AN196:
AN197:
AN1731:
SAA5025D
SAA5030
SAA5040
SAA5045
SAA5050
SAA5230
AN153:
AN153:
AN153:
AN153:
AN153:
AN154:
SAA5240
AN154:
SAA5350
SAB3035
AN152:
AN157:
SG1524C
AN1261:
SG3524C
AN1261:
AN125:
TDA1013A
TDA1023
TDA1072A
TDA1510
AN126:
AN148:
AN1291:
AN1961:
AN1491:
TDA1515
AN1481:
TDA1520A
TDAI540
TDA2578
AN149:
ANll0:
AN1621:
TDA2595
TDA2595
AN158:
AN162:
February 1987
Clock Regenerator With Crystal Controlled
Phase-Locked VCO
Circuit Description of the NE565
FSK Demodulator With NE565
Circuit Description of the NE566
Waveform Generators With the NE566
Circuit Description of the NE567 Tone Decoder
Selected Circuits Using the NE567
Applications for Compandors: NE570/571/SA571
Automatic Level Control: NE572
LED Decoder Drivers: Using the NE587 and NE589
Using the NE592/5592 Video Amplifier
Designing With the NE/SA602
New Low Power Single Sideband Circuits (NE602)
Applying the Oscillator of the NE602 in Low Power
Mixer Applications
Designing With the NE/SA604
Audio Decibel Level Detector With Meter Driver
(NE602)
PCF8570: Twisted-Pair Bus Carries Speech, Data,
Text and Images
An Amplifying, Level Shifting Interface for the
PNA7509 Video D/A Converter
Using the SAA1027 With Airpax Four-Phase Stepper
Motors
Single-Chip Synthesizer for Radio Tuning
Analysis and Basic Application of the SAA1057
SAA3004: Low Power Remote Control IR
Transmitter and Receiver Preamplifiers
The 5 Chip Set Teletext Decoder
The 5 Chip Set Teletext Decoder
The 5 Chip Set Teletext Decoder
The 5 Chip Set Teletext Decoder
The 5 Chip Set Teletext Decoder
Teletext Decoders: Keeping Up With the Latest
Technology Advances
Teletext Decoders: Keeping Up With the Latest
Technology Advances
SAA5350: A Single-Chip CRT Controller
Microcomputer Peripheral IC Tunes and Controls a
TV Set
High Frequency Ferrite Power Transformer and
Choke
High Frequency Ferrite Power Transformer and
Choke
Progress in SMPS Magnetic Component
Optimization
Applications Using the SG3524
Audio Amplifier With TDA1013A
Design of Time-Proportional Temperature Controls
TDA1072A: Integrated AM Receiver
Car Radio Audio Power Amplifiers Up to 24W With
the TDA1510
Car Radio Audio Power Amplifiers Up to 20W With
the TDA1515
20W Hi-Fi Power Amplifier With the TDA 1520A
Monolithic 14-Bit DAC With 85dB SIN Ratio
Directives for a Print Layout Design on Behalf of
the IC Combination TDA2578A and TDA3651
Features of the TDA2595 Synchronization Processor
A Versatile High-Resolution Monochrome Data and
Graphics Display Unit
1-17
Vol 2
Vol 3
6-68
4-240
11-118
4-282
4-297
4-301
4-309
4-310
4-325
4-330
4-341
4-372
4-55
4-75
4-79
4-87
4-130
4-189
4-140
4-199
5-77
11-20
8-52
4-201
4-208
5-20
13-3
13-3
13-3
13-3
13-3
13-8
13-8
13-89
4-61
8-138
8-138
8-225
8-190
7-258
8-251
7-15
7-280
7-300
7-312
5-226
9-30
9-57
9-25
Signetics Linear Products
Application Notes by Part Numbers
Vol 1
TDA2653
AN162
TDA3047
AN172:
AN173:
TDA3048
AN172:
AN173:
TDA3505
AN155/A:
TDA3563
TDA3651
AN156:
AN1621:
TDA4555
AN155/A:
AN1551:
TDA7000
TEA1017
TEA1067
AN192:
AN193:
AN103:
AN1942:
AN1943:
TEA2000
pA758
February 1987
AN1561:
AN191:
A Versatile High-Resolution Monochrome Data and
Graphics Display Unit
Circuit Description of the Infrared Receiver
Low Power Preamplifiers for IR Remote Control
Systems
Circuit Description of the Infrared Receiver
Low Power Preamplifiers for IR Remote Control
Systems
Multi-Standard Color Decoder With Picture
Improvement
Application of the NTSC Decoder: TDA3563
Directives for a Print Layout Design on Behalf of
the IC Combination TDA2578A and TDA3651
Multi-Standard Color Decoder With Picture
Improvement
Single-Chip Multi-Standard Color Decoder TDA4555/
4556
A Complete FM Radio on a Chip
TDA7000 for Narrowband FM Reception
13-Bit Serial-to-Parallel Converter
TEA1067: Application of the Low Voltage Versatile
Transmission Circuit
TEA 1067: Supply of Peripheral Circuits With the
TEA 1067 Speech Circuit
Application of the TEA2000 Color Encoder
Stereo Decoder Applications Using the pA758
1-18
Vol 2
Vol 3
9-25
5-60
5-62
5-60
5-62
10-30
10-25
9-30
10-3
10-73
7-54
7-69
6-88
6-108
10-121
7-159
Signetics
Outline:
Volume 1
Communications
Linear Products
Preface
Product Status
Section 1:
GENERAL INFORMATION
Section 2:
QUALITY AND RELIABILITY
Section 3:
12 C SMALL AREA NETWORKS
Section 4:
RF COMMUNICATIONS
Signal Processing
Frequency Synthesis
Phase-Locked Loops
Compandors
Section 5:
DATA COMMUNICATIONS
Line Drivers/Receivers
Modems
Fiber Optics
Section 6:
TELECOMMUNICATIONS
Compandors
Phase-Locked Loops
Telephony
Section 7:
RADIO/AUDIO
Radio Circuits
Audio Circuits
Compact Disk
Section 8:
SPEECH/AUDIO SYNTHESIS
Section 9:
PACKAGE INFORMATION
Section 10: SALES OFFICES
February 1987
1·19
Signe1ics
I
Outline:
Volume 2
Industrial
Linear Products
Preface
Product Status
Section 1:
GENERAL INFORMATION
Section 2:
QUALITY AND RELIABILITY
Section 3:
12 C SMALL AREA NETWORKS
Section 4:
AMPLIFIERS
Operational
High Frequency
Transconductance
Fiber Optics
Section 5:
DATA CONVERSION
Analog-to-Digital
Digital-to-Analog
Comparators
Sample-and-Hold
Position Measurement
Section 6:
INTERFACE
Line Drivers/Receivers
Peripheral Drivers
Display Drivers
Serial-to-Parallel Converters
Section 7:
TIMERS
Section 8:
POWER CONVERSION/CONTROL
Section 9:
PACKAGE INFORMATION
Section 10: SALES OFFICES
February 1987
1-20
Cross Reference Guide
Signetics
Pin-for-Pin Functionally-Compatible*
Cross Reference by Competitor
Linear Products
Competitor
Signetics
Competitor Part Number Part Number
AMD
Datel
Exar
Fairchild
AM6012F
DAC·OSAF
DAC·OSCN
DAC·OSCF
DAC·OSEN
DAC·OSEF
DAC·OSHN
DAC·OSHF
DAC·OSF
LF19SH
SE5537H
LF39SH
NE5537H
LF39SD
NE5537D
LF39SN
NE5537N
NE5534/AF
NE5534/AF
SE5534/AF
NE5020N
NE501SN
SE5019F
SE501SF
o to
-55
o to
o to
o to
o to
o to
o to
-55
-55
-55
o to
o to
o to
o to
o to
o to
o to
o to
-55
o to
o to
-55
-55
+70
to + 125
+70
+70
+70
+70
+70
+70
to + 125
to +125
to +125
+70
+70
+70
+70
+70
+70
+70
+70
to +125
+70
+70
to +125
to 125
Ceramic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Ceramic
Metal Can
Metal Can
Metal Can
Metal Can
SO
SO
Plastic
Plastic
Ceramic
Ceramic
Ceramic
Plastic
Plastic
Ceramic
Ceramic
XR·5532/A N NE5532/AF
XA·5532/A P NE5532/AN
o to
o to
o to
o to
o to
o to
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Ceramic
Plastic
Ceramic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Ceramic
Plastic
Ceramic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Metal Can
Plastic
AM6012DC
DAC·OSAO
DAC·OSCN
DAC·OSCO
DAC·OSEN
DAC·OSEO
DAC·OSHN
DAC·OSHO
DAC·OSO
LF19SH
LF19SH
LF39SH
LF39SH
LF39SL
LF39SL
LF39SN
LF39SN
AM·453·2
AM·453·2C
AM·453·2M
DAC·UP10BC
DAC·UPSBC
DAC·UPSBM
DAC·UPSBO
XA·L567CN
NE567F
XA·L567CP
NE567N
XA·55341 A CN NE55341AF
XA·55341 A CP NE55341 AN
XA·55341 A M SE55341 AF
XA·55SCN
NE55SF
XA·55SCP
NE55SN
XA·55SM
SE55SF
XA·1524N
SG3524F
XA·1524P
SG3524N
XA·2524P
SG3524N
XA·3524N
SG3524F
XA·3524P
SG3524N
-55
o to
o to
-55
o to
o to
o to
o to
o to
+70
+70
+70
+70
+70
+70
to +125
+70
+70
to + 125
+70
+70
+70
+70
+70
DAC·OSF
MC140SF
MC140SN
DAC·OSEF
DAC·OSAF
MC145SN
MC14SSF
MC14SSN
MC14S9/AF
MC14S9/AN
NE5537H
NE5537N
o to
o to
o to
o to
o to
o to
o to
o to
o to
o to
o to
o to
+70
+70
+70
+70
+70
+70
+70
+70
+70
+70
+70
+70
1JA0SO/DA
IJAOS01CDC
IJAOS01CPC
IJAOS01EDC
IJAOS01EPC
1JA145STC
1JA14SSDC
1JA14SSPC
1JA14S9/A PC
1JA14S9/A PC
1JA19SHM
1JA19SAM
Competitor
Signetics
Competitor Part Number Part Number
Temperature
Range ('C)
Package
-40
-40
o to
o to
o to
-40
-40
o to
o to
o to
o to
-55
-55
o to
o to
to +S5
to +S5
+70
+70
+70
to +S5
to +S5
+70
+70
+70
+70
to + 125
to + 125
+70
+70
Ceramic
Plastic
Ceramic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Metal Can
Plastic
Plastic
Plastic
1JA723DC
1JA723DM
1JA723HC
1JA723PC
1JA733DC
1JA733DM
1JA733PC
1JA741NM
1JA741AC
1JA741TC
1JA747DC
1JA747PC
1JA9667DC
1JA9667PC
1JA966SDC
1JA966SPC
LM2901F
LM2901N
LM311F
LM324F
LM324N
MC3302F
MC3302N
LM339/AF
LM339/AN
MC3403F
MC3403N
SE5537H
SE5537N
NE555N
NE556·tN,
NE556N
1JA723CF
1JA723F
1JA723CH
1JA723CN
Pf.733F
1JA733F
1JA733N
1JA741N
1JA741CF
1JA741CN
1JA747CF
1JA747CN
ULN2003F
ULN2003N
ULN2004F
ULN2004N
o to
-55
o to
o to
o to
-55
o to
-55
o to
o to
o to
o to
o to
o to
o to
o to
+70
to +125
+70
+70
+70
to + 125
+70
to +125
+70
+70
+70
+70
+70
+70
+70
+70
Ceramic
Ceramic
Metal Can
Plastic
Ceramic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Harris
HA·2539
HA·2420·2/SB
HA·2425N
HA·2425B
HA1·5102·2
HA1·5135·2
HA1·5135·5
HA3·51 02·5
HA1·5202·5
HA·5320B
NE5539
SE5060F
NE5060N
NE5060F
SE5532/AF
SE5534/AF
NE5534/AF
NE5532/AN
NE5532/AF
NE5060F
o to
-55
o to
o to
-55
-55
o to
o to
o to
o to
+70
to + 125
+70
+70
to + 125
to +125
+70
+70
+70
+70
Plastic
Ceramic
Plastic
Ceramic
Ceramic
Ceramic
Ceramic
Plastic
Ceramic
Ceramic
Intersll
ADCOS03LCD ADCOB03·1 LCF -40 to + S5
ADCOS04
ADCOB04·1 CN o to +70
ADCOS05
ADCOB05·1 LCN -40 to + S5
Motorola
DAC·OSCD
DAC·OBCO
DAC·OBED
DAC·OBEF
DAC·OBHO
DAC·OBO
1JA2901DC
1JA2901PC
1JA311AC
1JA324DC
1JA324PC
1JA3302DC
1JA3302PC
1JA339/ADC
1JA339/APC
1JA3403DC
1JA3403PC
1JA39SHC
1JA39SAC
1JA555TC
1JA556PC
1-21
Temperature
Range ('C)
Package
DAC·OBCN
DAC·OBCF
DAC·OSEN
DAC-OBEF
DAC-OBHF
DAC·OBF
o to
o to
o to
o to
o to
+70
+70
+70
+70
+70
-55 to + 125
Ceramic
Plastic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Ceramic
Ceramic
Signetics Unear Products
Cross Reference Guide
Competitor
Signetics
Competitor Part Number Part Number
LM2901N
LM311J-8
LM311N
LM324J
LM324N
LM339/A J
LM339/A N
LM358N
LM393A1J
LM393A1N
MC1408L
MC1408P
MC1488L
MC1488P
MC1489/A L
MC1489/A P
MC1496L
MC1496P
MC3302L
MC3302P
MC3361D
MC3361P
MC3403L
MC3403P
MC3410CL
MC3410L
National
Temperature
Range (OC)
Package
MC3510L
NE592F
NE592F
NE592N
NE565N
SE592F
SE592F
SE592H
LM2901N
LM311F
LM311N
LM324F
LM324N
LM339/AF
LM339/AN
LM358N
LM393/AF
LM393/AN
MC1408F
MC1408N
MC1488F
MC1488N
MC1489/AF
MC1489/AN
MC1496F
MC1496N
MC3302F
MC3302N
MC3361D
MC3361N
MC3403F
MC3403N
MC3410CF
MC3410F
NE541 OF
SE5410F
NE592F-8
NE592F-14
NE592N
NE565N
SE592F-8
SE592F-14
SE592H
-40 to +85
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
-40 to +85
-40 to +85
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
-55 to +125
-55 to +125
-55 to + 125
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
SO
Plastic
Ceramic
Plastic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Plastic
Plastic
Ceramic
Ceramic
Metal Can
ADC0803F
ADC0803N
ADC0805
ADC0820BCN
ADC0820CCN
ADC0820BCD
ADC0820CCD
ADC0820BD
ADC0820CD
DAC0800LCJ
DAC0800LJ
DAC0800LCN
DAC0801LCJ
DAC0801 LCN
DAC0802LJ
DAC0802LCJ
DAC0802LCN
DAC0806LCJ
DAC0806LCN
DAC0807LCJ
DAC0807LCN
DAC0808LCJ
ADC0803-1 LCF
ADC0803-1 LCN
ADC0805-1 LCN
ADC0820BNEN
ADC0820C~EN
ADC0820BSAN
ADC0820CSAN
ADC0820BSEF
ADC0820CSEF
DAC-08EF
DAC-08F
DAC-08EN
DAC-08CF
DAC-08CN
DAC-08AF
DAC-08HF
DAC-08HN
MC1408-6F
MC1408-6N
MC1408-7F
MC1408-7N
MC1408F
-40 to +85
-40 to +85
-40 to + 85
o to +70
o to +70
-40 to .j.85
-40 to +85
-55 to +125
-55 to + 125
o to +70
-55 to +125
o to +70
o to +70
o to +70
-55 to +125
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
Ceramic
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
Ceramic
Ceramic
Ceramic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Competitor
Signetlcs
Competitor Part Number Part Number
,
1-22
DAC0808LCN
DAC0808LD
LF198H
LF398H
LF398N
LMI3600AN
LMI3600N
LM1458N
LM161H
LM161J
LM2524J
LM2524N
LM2901N
LM2903N
LM3089
LM319J
LM319N
LM324J
LM324N
LM324AD
LM324AN
LM339/AJ
LM339/AN
LM3524J
LM3524N
LM358H
LM358N
LM361H
LM361J
LM361N
LM393/AN
LM555J
LM555N
LM556J
LM556N
LM556CJ
LM556CN
LM565CN
LM566N
LM566CN
LM567CN
LM733CN
LM741CJ
LM741CN
LM741J
LM741N
LM747CJ
LM747CN
LM747J
LM747N
UC3842D
UC3842J
UC3842N
UC2842D
UC2842J
UC2842N
UC1842J
UC1842N
MC1408N
MC1408F
SE5537H
NE5537H
NE5537N
NE5517N
NE5517N
MC1458N
SE529H
SE529F
SG3524F
SG3524N
LM2901N
LM2903N
CA3089N
LM319F
LM319N
LM324F
LM324N
LM324AD
LM324AN
LM339/AF
LM339/AN
SG3524F
SG3524N
LM358H
LM358N
NE529H
NE529D
NE529N
LM393/AN
NE555F
NE555N
SE556-1F
SE556-1N
NE556-1F
NE556-1N
NE565N
SE566N
NE566N
NE567N
jJA733CN
jJA741CF
jJA741CN
jJA741F
jJA741N
jJA747CF
jJA747CN.
1l747F
jJA747N
UC3842D
UC3842FE
UC3842N
UC2842D
UC2842FE
UC2842N
UC1842FE
UCI842N
Temperature
Range (OC)
Package
o to
o to
+70
+70
-55 to + 125
o to +70
o to +70
o to +70
o to +70
o to +70
-55 to +125
-55 to +125
o to +70
o to +70
-40 to +85
-40 to +85
-55 to +125
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
-55 to +125
-55 to +125
o to +70
o to +70
o to +70
-55 to +125
o to +70
o to +70
o to +70
o to +70
o to +70
-55 to +125
-55 to +125
o to +70
o to +70
-55 to +125
-55 to + 125
o to +70
o to +70
o to +70
o to +70
o to .+70
o to +70
-55 to.+125
-55 to +125
Plastic
Ceramic
Metal can
Metal can
Plastic
Plastic
Plastic
Plastic
Metal Can
Ceramic
Ceramic
Plastic
Plastic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Metal Can
Plastic
Metal can
SO
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Signetics Linear Products
Cross Reference Guide
Competitor
Signetics
Competitor Part Number Part Number
Temperature
Range (OC)
Package
NEC
IlPC1571C
NE571N
o to +70
Plastic
PM)
CMP-05GP
CMP-05CZ
CMP-05BZ
CMP-05GZ
CMP-05FZ
DAC1408A-6P
DAC1408A-6Q
DAC1408A-7N
DAC1408A-7Q
DAC1408A-8N
DAC1408A-8Q
DAC1508A-8Q
DAC312FR
OP27BZ
OP27CZ
PM747Y
SMP-10AY
SMP-10EY
SMP-11AY
SMP-11EY
NE5105N
SE5105F
SE5105F
SA5105N
SA5105N
MC1408-6N
MC1408-6F
MC1408-7N
MC1408-7F
MC1408-8N
MC1408-8F
MC1408-8F
AM6012F
SE5534AFE
SE5534FE
J.lA747N
SE5060F
NE5060N
SE5060F
NE5060N
o to
-55
-55
-40
-40
o to
o to
o to
o to
o to
o to
-55
o to
-55
-55
-55
-55
o to
-55
o to
+70
to + 125
to + 125
to +85
to +85
+70
+70
+70
+70
+70
+70
to + 125
+70
to + 125
to +125
to + 125
to +125
+70
to + 125
+70
Plastic
Ceramic
Ceramic
Plastic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
RC4805DE
RC4805EDE
RM4805DE
RM4805ADE
RC5532! A DE
RC5532! A NB
RC5534!A DE
RC5534! A NB
RM5532! A DE
RM5534! A DE
NE5105N
NE5105AN
SE5105F
SE5105AF
NE5532!AF
NE5532! AN
NE5534!AF
NE5534! AN
SE5532! AF
SE5534! AF
o to
o to
-55
-55
o to
o to
o to
o to
-55
-55
+70
+70
to + 125
to + 125
+70
+70
+70
+70
to + 125
to +125
Plastic
Plastic
Ceramic
Ceramic
Silicon
General
SG3524J
SG3526N
SG3524F
SG3526N
o to +70
o to +70
Ceramic
Plastic
Sprague
UDN6118A
UDN6118R
ULN8142M
ULN8160A
ULN8160R
ULN8161M
ULN8168M
ULN8564A
ULN8564R
ULS8564R
SA594N
SA594F
UC3842N
NE5560N
NE5560F
NE5561N
NE5568N
NE564N
NE564F
SE564F
-40
-40
o to
o to
o to
o to
o to
o to
o to
-55
to +85
to +85
+70
+70
+70
+70
+70
+70
+70
to + 125
Plastic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Plastic
Plastic
Ceramic
Ceramic
TI
ADC0803N
ADC0804CN
ADC0805N
LM111J
LM311D
ADC0803-1 LCN -40
ADC0804-1 CN o to
ADC0805-1 LCN -40
LM111F
-55
LM311D
o to
to + 85
+70
to + 85
to +125
+70
Plastic
Plastic
Plastic
Ceramic
Plastic
Raytheon
Signetlcs
Competitor
Competitor Part Number Part Number
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Ceramic
Unitrode
Temperature
Range (OC)
Package
LM311J
LM311JG
LM324D
LM324J
LM339!AJ
LM339!AN
LM358P
LM393!A P
MC1458P
NE5532! A JG
NE5532!A P
NE5534!A JG
NE5534!A P
NE555JG
NE555P
NE556D
NE556J
NE556N
NE592
NE592A
NE592J
NE592N
SA556D
SE5534!A JG
SE555JG
SE556J
SE556N
SE592
SE592J
SE592N
SN55107AJ
SN55108AJ
SN75107AJ
SN75107AN
SN75108AJ
SN75108AN
SN75188J
SN75188N
SN75189AJ
SN75189AN
SN75189J
SN75189N
TL592A
TL592P
J.lA723CJ
J.lA723CN
J.lA723MJ
J.lA723MU
LM311F
LM311FE
LM324N
LM324F
LM339!AF
LM339!AN
LM358N
LM393!AN
MC1458N
NE5532! AF
NE5532!AN
NE5534!AF
NE5534!AN
NE555N
NE555N
NE556N
NE556-1F
NE556-1 N
NE592N14
NE592F14
NE592F
NE592N-14
SA556N
SE5534!AF
SE555N
SE556-1F
SE556-1N
SE592N14
SE592F-14
SE592N-14
NE521F
SE522F
NE521F
NE521N
NE522F
NE522N
MC1488F
MC1488N
MC1489AF
MC1489AN
MC1489F
MC1489A
NE592F14
NE592NB
J.lA723CF
J.lA723CN
J.lA723F
J.lA723D
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
-40 to +85
-55 to + 125
-55 to +125
-55 to + 125
-55 to +125
-55 to + 125
-55 to + 125
-55 to + 125
o to +70
-55 to +125
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
-55 to + 125
-55 to + 125
Ceramic
Ceramic
Plastic
Ceramic
Ceramic
Plastic
Plastic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Plastic
Plastic
Plastic
Ceramic
Plastic
Plastic
UC3524J
UC3524N
SG3524F
SG3524N
o to +70
o to +70
Ceramic
Plastic
Ceramic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
SO
'THERE MAY BE PARAMETRIC DIFFERENCES BETWEEN SIGNETICS'
PARTS AND THOSE OF THE COMPETITION.
1-23
Signetics
I so Availability
List
Linear Products
PART
NUMBER
SMD
PACKAGE
ADC0820D
*DAC08ED
*LF398D
LM1870D
LM2901D
LM2903D
LM311D
LM319D
SOL-20
SO-16
SO-14
SOL-20
SO-14
SO-8
SO-8
SO-14
LM324AD
LM324D
LM339D
LM358AD
LM358D
LM393D
*MC1408-8D
MC1458D
MC1488D
MC1489D
MC1489AD
MC3302D
MC3361D
MC3403D
SO-14
SO-14
SO-14
SO-8
SO-8
SO-8
SO-16
SO-8
SO-14
SO-14
SO-14
SO-14
SOL-16
SO-14
NE4558D
*NE5018D
*NE5019D
*NE5036D
NE5037D
NE5044D
SO-8
SOL-24
SOL-24
SO-14
SO-16
SO-16
NE5045D
NE5090D
NE5105/AD
SO-16
SOL-16
SO-8
NE5170A
NE5180A
NE5204D
NE5205D
NE521D
PLCC-28
PLCC-28
SO-8
SO-8
SO-14
NE5212D8
SO-8
NE522D
SO-14
NE5230D
NE527D
SO-8
SO-14
NE529D
SO-14
February 1987
PART
NUMBER
DESCRIPTION
8-Bit CMOS AID
8-Bit DI A Converter
Sample-and-Hold Amp
Stereo Demodulator
Quad Volt Comparator
Dual Volt Comparator
Voltage Comparator
High-Speed Dual
Comparator
Quad Op Amp
Quad Op Amp
Quad Volt Comparator
Dual Op Amp
Dual Op Amp
Dual Comparator
8-Bit DI A Converter
Dual Op Amp
Quad Line Driver
Quad Line Receiver
Quad Line Receiver
Quad Volt Comparator
Low Power FM IF
Quad Low Power Op
Amp
Dual Op Amp
8-Bit DI A Converter
8-Bit DI A Converter
6-Bit AI D Converter
6-Bit AID Converter
Prog 7-Channel
Encoder
7-Channel Decoder
Address Relay Driver
High-Speed
Comparator
Octal Line Driver
Octal Line Receiver
High-Frequency Amp
High-Frequency Amp
High-Speed Dual
Comparator
Transimedance
Amplifier
High-Speed Dual
Comparator
Low Voltage Op Amp
High-Speed
Comparator
High-Speed
Comparator
1·24
SMD
PACKAGE
NE532D
*NE544D
*NE5512D
*NE5514D
NE5517D
NE5520D
*NE5532D
SO-8
SOL-16
SO-8
SOL-16
SO-16
SOL-16
SOL-16
*NE5533D
NE5534AD
NE5534D
NE5537D
NE5539D
SOL-16
SO-8
SO-8
SO-14
SO-14
NE555D
NE556D
NE5560D
NE5561D
NE5562D
NE5568D
NE558D
NE5592D
NE564D
*NE565D
NE566D
NE567D
NE568D
NE571D
NE572D
*NE587D
SO-8
SO-14
SO-16
SO-8
SOL-20
SO-8
SOL-16
SO-14
SO-16
SO-14
SO-8
SO-8
SOL-20
SOL-16
SOL-16
SOL-20
*NE589D
SOL-20
NE5900D
NE592D14
NE592D8
NE592HD14
NE592HD8
*NE594D
NE602D
SOL-16
SO-14
SO-8
SO-14
SO-8
SOL-20
SO-8
NE604D
SO-16
NE605
NE612D
SOL-20
SO-8
NE614D
SO-16
*PCD3311TD
SO-16
DESCRIPTION
Dual Op Amp
Servo Amp
Dual Hi-Perf Op Amp
Quad Hi-Perf Op Amp
Dual Hi-Perf Amp
LVDT Signal Cond Ckt
Dual Low-Noise Op
Amp
Low-Noise Op Amp
Low-Noise Op Amp
Low-Noise Op Amp
Sample-and-Hold Amp
Hi-Freq Amp
Wideband
Single Timer
Dual Timer
SMPS Control Ckt
SMPS Control Ckt
SMPS Control Ckt
SMPS Control Ckt
Quad Timer
Dual Video Amp
Hi-Frequency PLL
Phase Locked Loop
Function Generator
Tone Decoder PLL
PLL
Compandor
Prog Compandor
7 Seq LED Driver
(Anode)
7 Seq LED Driver
(Cath)
Call Progress Decoder
Video Amp
Video Amp
Hi-Gain Video Amp
Hi-Gain Video Amp
Vac Fluor Disp Driver
Double Bal Mixer/
Oscillator
Low Power FM IF
System
FM IF System
Double Balanced
Mixer/Oscillator
Low Power FM IF
System
DTMF/Melody
Generator
Signetics Linear Products
SO Availability List
PART
NUMBER
SMD
PACKAGE
PCD3312TD
SO-8
PCD3315TD
PCD3360TD
PCF2100TD
SOL-28
SO-16
SOL-28
PCF2111TD
VSO-40
PCF2112TD
VSO-40
PCF8570TD
PCF8571TD
PCF8573TD
PCF8574TD
PCF8576TD
PCF8577TD
SO-8
SO-8
SO-16
SO-16
VSO-56
VSO-40
SA5105/AD
SO-8
SA5230D
SA5212D8
SA532D
SA534D
SA555D
SA571D
SA572D
'SA594D
SA602D
SO-8
SO-8
SO-8
SO-14
SO-8
SOL-16
SOL-16
SOL-20
SO-8
SA604D
SO-16
PART
NUMBER
DESCRIPTION
DTMF/Melody
Generator With ICC
Repertory Pulse Dial
Progress Tone Ringer
LCD Duplex Driver
(40)
LCD Duplex Driver
(64)
LCD Duplex Driver
(32)
Static RAM (256 X 8)
1K Serial RAM
Clock/Timer
Remote 1/0 Expander
MUX/Static Driver
32-/64-Segment LCD
Driver
High-Speed
Comparator
Low Voltage Op Amp
Transimpedance Amp
Dual Op Amp
Dual Op Amp
Single Timer
Compandor
Compandor
Vac Fluor Disp Driver
Double Bal Mixer I
Oscillator
Lower Power FM IF
System
SMD
PACKAGE
SAA3004TD
SG3524D
TDA1001BTD
TDA1005ATD
TDA3047TD
TDA3048TD
TDA5040TD
SOL-20
SO-16
SO-16
SO-16
SO-16
SO-16
SO-8
TDA7010TD
TDA7050TD
TDD1742TD
ULN2003D
ULN2004D
pA723CD
pA741 CD
pA747CD
SO-16
SO-8
SOL-28
SO-16
SO-16
SO-14
SO-8
SO-14
DESCRIPTION
RIC Transmitter
SMPS Control Circuit
Noise Suppressor
Stereo Decoder
IR Preamp
IR Preamp
Brushless DC Motor
Driver
FM Radio Circuit
Mono/Stereo Amp
Frequency Synthesizer
Transistor Array
Transistor Array
Voltage Regulator
Single Op Amp
Dual Op Amp
NOTE:
*Non-standard pinout.
UNDER DEVELOPMENT
PART
NUMBER
26LS31D
26LS32D
26LS33D
26LS29D
26LS30D
SMD
PACKAGE
SO-16
SO-16
SO-16
SO-16
SO-16
DESCRIPTION
RS-422
RS-422
RS-422
RS-423
RS-423
Line
Line
Line
Line
Line
NOTE:
For information regarding additional SO products released since the publication of this document, contact your local Signetics Sales Office.
February 1987
1-25
Driver
Receiver
Receiver
Driver
Receiver
•
Signetics
I
Ordering Information
~
_
__
..... ___
~!!!!_
_ _
_
A...... ..........
A
.....
~
A
.......
A
ICM, LF, LM, MC, NE, OP, SA,
SE, SG, pA, UC, ULN
Linear Products
Signetics' Linear integrated circuit products may be ordered by contacting either
the local Signetics sales office, Signetics
representatives and/or Signetics authorized distributors. A complete listing is
located in the back of this manual.
Table 1. Part Number Description
PART NUMBER
CROSS REF
PART NO.
!':! E.£..~z.l'!
PRODUCT
FAMILY
LF398
LIN
Minimum Factory Order:
PRODUCT
DESCRIPTION
C-HOdA""
Description of
Product Function
Commercial Product:
$1000 per order
$250 per line item per order
Military Product:
$250 per line item per order
~ Linear Product Family
Table 1 provides part number information concerning Signetics originated
products.
Table 2 is a cross reference of both the
old and new package suffixes for all
presently existing types, while Tables 3
and 4 provide appropriate explanations
on the various prefixes employed in the
part number descriptions.
- - Package Descriptions -
See Table 2
Device Number
Device Family and Temperature Range Prefix Tables 3 & 4
As noted in Table 3, Signetics defines
device operating temperature range by
the appropriate prefix. It should be not·
ed, however, that an SE prefix (-55°C to
+ 125°C) indicates only the operating
temperature range of a device and not
its military qualification status. The military qualification status of any Linear
product can be determined by either
looking in the Military Data Manual and/
or contacting your local sales office.
February 1987
.......
Tor t'reTlxes AU\.., , AIVI, \..,A, UA\.."
1-26
See
Signetics Linear Products
Ordering Information
Table 2. Package Descriptions
OLD
NEW
A. AA
A
N
N-14
B. BA
N
D
F
F
I,IK
I
K
H
H
L
NA, NX
N
Q, R
Q
T, TA
U
V
XA
XC
XC
XL, XF
H
U
N
N
N
N
N
A
EC
FE
February 1987
PACKAGE
DESCRIPTION
14-lead plastic DIP
14-lead plastic DIP
(selected analog
products only)
16-lead plastic DIP
Microminiature
package (SO)
14-. 16-, 18-, 22-,
and 24-lead
ceramic DIP
(Cerdip)
14-, 16-, 18-, 22-,
28-, and 4-lead
ceramic DIP
10-lead TO-100
10-lead high-profile
T0-100 can
24-lead plastic DIP
10-, 14-, 16-, and
24-lead ceramic
flat
8-lead TO-99
SIP plastic power
8-lead plastic DIP
18-lead plastic DIP
20-Iead plastic DIP
22-lead plastic DIP
28-lead plastic DIP
PLCC
TO-46 header
8-lead ceramic DIP
Table 3. Signetics Prefix and
Device Temperature
PREFIX
DEVICE TEMPERATURE
RANGE
NE
SE
SA
o to +70'C
-55'C to + 125'C
-40'C to +85'C
Table 4. Industry Standard Prefix
PREFIX
ADC
AM
CA
DAC
ICM
LF
LM
MC
NE
OP
SA
SE
SG
IlA
UC
ULN
DEVICE FAMILY
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
1·27
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Signetics
I
Ordering Information
fOi Prefixes HE, OM, MA, ME,
PC, PN, SA, TB, TC, TO, TE
Linear Products
Signetics' integrated circuit products
may be ordered by contacting either the
local Signetics sales office, Signetics
representatives and/or Signetics authorized distributors.
Minimum Factory Order:
Commercial Product:
Table 1_ Part Number Description
PART
NUMBER
PRODUCT
FAMILY
..!..D...A~~ll
N
PRODUCT
DESCRIPTION
lLiN.
L::~cr::::fi::
Product Function
$ 1000 per order
Product Family Linear
$ 2S0 per line item per order
Table 1 provides part number information concerning Signetics/Philips integrated circuits.
Table 2 provides package suffixes and
descriptions for all presently existing
types. Letters following the device number not used in Table 2 are considered
to be part of the device number.
Table 3 provides explanations on the
various prefixes employed in the part
number descriptions. As noted in Table
3, Signetics/Philips device operating
temperature is defined by the appropriate prefix.
OPERATING TEMPERATURE:
The third letter of the prefix, in a threeletter prefix, is the temperature designator.
The letters A to F give information about
the operating temperature:
A: Temperature range not specified.
See data sheet.
e.g. TDA2541 N
B: 0 to +70°C
e.g. PCBB573PN
C: -S5°C to + 12SoC
e.g. PCC2111 PN
D: -2SoC to + 70°C
e.g. PCDB571 PN
E: -2SoC to +BSoC
e.g. PCE2111 PN
F: -40°C to +BSoC
e.g. PCF2111 PN
February 1987
Package Description - See Table 2A
' - - -__-Device Number
Device Family and Temperature Range Prefix
See Table 3A
Table 2. Package Description
SUFFIX
PN
PACKAGE DESCRIPTION
8-, 14-, 16-, 18-, 20-, 24-, 28-, 40-lead plastic DIP
Microminiature Package (SO)
14-, 16-, 18-, 22-, 24-lead ceramic DIP
Single in-line plastic (SIP) and SIP power packages
TD
DF
U
Table 3. Device Prefix
PREFIX
DEVICE FAMILY
HEx
OM
MAx
MEx
CMOS circuit
Linear circuit
Microcomputer
Microcomputer peripheral
PCx
PNx
CMOS circuit
NMOS circuit
SAx
TBx
TCx
TDx
TEx
Digital
Linear
Linear
Linear
Linear
1-28
circuit
circuit
circuit
circuit
circuit
Signefics
Section 2
Quality and Reliability
Linear Products
INDEX
Signetics Zero Defects..............................................................................
Linear Division Quality and Reliability ...................... :.... ..... ..... ..... ......... ........
Linear Division Product Flow......................................................................
2-3
2-5
2-8
"Given the increasingly intense competitive
pressures our customers face, they should
demand nothing less than zero defects
from every IC vendor. We now know that
zero defects is an achievable goal. Why
should IC customers pay for errors?"
Norman Neumann
President
Signetics Corporation
Signetics
Quality and Reliability
•
Linear Products
SIGNETICS' ZERO DEFECTS
PROGRAM
In recent years, American industry has demanded increased product quality of its IC
suppliers in order to meet growing international competitive pressures. As a result of this
quality focus, it is becoming clear that what
was once thought to be unattainable - zero
defects - is, in fact, achievable.
"catching" defects, but on preventing them
from ever occurring. This strong preventive
focus, which demands that quality be "built-in"
rather than "inspected in," includes a much
greater attention to ongoing communication on
quality-related issues. At Signetics, a focus on
this cooperative approach has resulted in better service to all customers and the development of two innovative customerIvendor programs: Ship-te-Stock and Self-Qual.
The IC supplier committed to a standard of
zero defects provides a competitive advantage to today's electronics OEM. That advantage can be summed up in four words:
reduced cost of ownership. As IC customers
look beyond purchase price to the total cost
of doing business with a vendor, it is apparent
that the quality-conscious supplier represents
a viable cost reduction resource. Consistently
high quality circuits reduce requirements for
expensive test equipment and personnel, and
allow for smaller inventories, less rework, and
fewer field failures.
As a result of their partiCipation in the Ship-toStock Program, many of our customers have
eliminated costly incoming testing on selected ICs. We will work together with any customer interested to establish a Ship-to-Stock
Program, and identify the products to be
Included in the program and finalize all necessary terms and conditions. From that point,
the specified products can go directly from
the receiving dock to the assembly line or into
inventory. Signetics then provides, free of
charge, monthly reports on those products.
REDUCING THE COST OF
OWNERSHIP THROUGH TOTAL
QUALITY PERFORMANCE
In our efforts to continually reduce cost of
ownership, we are now using the experience
we have gained with Ship-to-Stock to begin
developing a Just-in-Time Program. With Justin-Time, products will be delivered to the
receiving dock just as they are needed, permitting continuous-flow manufacturing and eliminating the need for expensive inventories.
Quality involves more than just IC's that work.
It also includes cost-saving advantages that
come with error-free service - on-time delivery of the right quantity of the right product at
the agreed-upon price. Beyond the product,
you want to know you can place an order and
feel confident that no administrative problems
will arise to tie up your time and personnel.
Today, as a result of Signetics' growing
appreciation of the concern with cost of
ownership, our quality improvement efforts
extend out from the traditional areas of product conformance into every administrative
function, including order entry, scheduling,
delivery, shipping, and invoicing. Driving this
process is a Corporate Quality Improvement
Team, comprised of the president and his
staff, which oversees the activities of 30 other
Quality Improvement Teams throughout the
company.
CUSTOMER/VENDOR
COOPERATION IS AT THE
HEART OF ZERO DEFECTS
AND REDUCED COSTS
Working to a zero defects standard requires
that emphasis be consistently placed, not on
February 1987
Uke Ship-to-Stock, our Self-Qual Program
employs a cooperative approach based on
ongoing information exchange. At Signetics,
formal qualification procedures are required
for all new or changed materials, processes,
products, and facilities. Prior to 1983, we
created our qualification programs independently. Our major customers would then test
samples to confirm our findings. Now, under
the new Self-Qual Program, customers can
be directly involved in the prequalification
stage. When we feel we have a promising
enhancement to offer, customers will be invited to participate in the development of the
qualification plan. This eliminates the need to
duplicate expensive qualification testing and
also adds another dimension to our ongoing
efforts to build in quality.
PRODUCT RELIABILITY:
QUALITY OVER TIME IS THE
GOAL
Our concern with product reliability has developed from communication with many customers. In discussions, these customers have
2-3
emphasized the high cost of field failures,
both in terms of dollars and reputations in the
marketplace.
In response to these concerns, we have
placed an emphasis on improving product
reliability. As a result of this effort, our product
reliability has improved more than fourfold in
a five-year period (see Figure 1). A key
program, SURE (Systematic and Uniform Reliability Evaluation), highlights the significant
progress made in this critical area.
SURE was first instituted in 1964 as the core
reliability measurement for all Signetics products. In 1980, as a first major step toward
improving product reliability, SURE was enhanced by increasing sampling frequency and
size and by extending stress tests. As a result
of these improvements, most of our major
customers now utilize SURE data with no
requests for additional reliability testing.
WE WANT TO WORK WITH
YOU
At Signetics, we know that our success depends on our ability to support all our customers with the defect-free, higher density, higher
performance products needed to compete
effectively in today's demanding business
environment. To achieve this goal, quality in
another arena - that of communicationsis vital. Here are some specific ways we can
maintain an ongoing dialogue and information
exchange between your company and ours
on the quality issue:
• Periodical face-to-face exchanges of
data and quality improvement ideas
between the customer and Signetics
can help prevent problems bafore they
occur.
• Test correlation data is very useful. Une
pull information and field failure reports
also help us improve product
performance.
• When a problem occurs, provide us as
soon as possible with whatever specific
data you have. This will assist us in
taking prompt corrective action.
Quality products are, in large measure, the
result of quality communication. By working
together, by opening up channels through
which we can talk openly to each other, we
will insure the creation of the innovative,
reliable, cost effective products that help
insure a competitive edge.
Signetics Unear Products
QI_ln_!ih,1
n_n,,0
_ Doli,..hll;t.,
n."" 11'-1 IJII II Y
~r-------------------------?=====~-
1984
1985
1988
lIME FRAME
1987
1988
1888
1880
0.,,,,,,,
Figure 1
QUALITY AND RELIABILITY
ASSURANCE
LINEAR PRODUCT QUALITY
• Customer liaison
Signetics has put together a winning process
for the manufacturing of Linear Integrated
Circuits. The circuits produced by our Linear
Division must meet rigid criteria as defined in
our design rules and as evaluated through
product characterization over the device operating temperature range. Product conformance to specification is measured throughout the manufacturing cycle. Our standard is
Zero Defects and our customers' statistics
and awards for outstanding product quality
demonstrste our advance toward this goal.
The result of this continual involvement at all
stages of production enables us to provide
feedback to refine present and future designs, manufacturing processes, and test
methodology to enhance both the quality and
reliability of the products delivered to our
customers.
Nowhere is this more evident than at our
Electrical Outgoing Product Assurance inspection gate. Over the past six years, the
measured defect level at the first submission
to Product Assurance for Linear products has
dropped from over 4000PPM (0.4%) to under
150PPM (0.015%) (see Figure 2). Signetics
Signetics' Linear Division Quality and Reliability Assurance Department is involved in all
stages of the production of our Linear ICs:
• Product Design and Process
Development
• Wafer Fabrication
• Assembly
• Inspection and Test
• Product Reliability Monitoring
February 1987
2·4
calls the first submittal to a Product or Quality
Assurance gate our Estimated Process Quality or EPQ. It is an internal measure used to
drive our Quality Improvement Programs toward our goal of Zero Defects. All product
acceptance sampling plans have zero as their
acceptance criteria. Only shipments that
demonstrste zero defects during these acceptance tests may be shipped to our customers. This is in accordance with our commHment to our Zero Defect policy.
The results from our Quality Improvement
Program have allowed Signetics to take the
industry leadership position with its Zero Detects Limited Warranty policy. No longer is it
necessary to negotiate a mutually acceptable
AQL between buyer and Signetics. Signetics
will replace any lot in which a customer finds
one verified defective part.
Signetics Linear Products
Quality and Reliability
rooo,------------------------------------------.
4200
Figure 2. Electrical Estimated Process Quality (EPQ)
QUALITY DATABASE
REPORTING SYSTEM - QA05
The capabilities of our manufacturing process
are measured and the results are recorded
through our corporate-wide QA05 database
system. The QA05 system collects the results
on all finished lots and feeds this data back to
concerned organizations where appropriate
corrective actions can be taken. The QA05
reports Estimated Process Quality (EPQ) data
which are the sample inspection results for
first submittal lots to Quality Assurance in·
spection for electrical, visual/mechanical,
hermeticity, and documentation. Data from
this system is available upon request and is
distributed routinely to our customers who
have formally adopted our Ship·to-Stock program.
SIGNETICS' SHIP-TO-STOCK
PROGRAM
Ship-to-Stock is a joint program between
Signetics and a customer which formally
certifies specific parts to go directly into
inventory or to the assembly line from the
February 1987
customer's receiving dock without incoming
inspection. This program was developed at
the request of several major customers after
they had worked with us and had a chance to
experience the data exchange and joint corrective action that occurs as part of our
quality improvement program.
The key elements of the Ship-to·Stock pro·
gram are:
• Signetics and customer agree on a list
of products to be certified, complete
device correlation, and sign a
specification.
• The product Estimated Product Quality
(EPQ) must be 300ppm or less for the
past 3 months.
• Signetics will share Quality (QA05) and
Reliability data on a regular basis.
• Signetics will alert Ship-to-Stock
customers of any changes in quality or
reliability which could adversely impact
their product.
Any customer interested in the benefits of the
Ship-to-Stock program should contact his
2-5
local Signetics sales office for a brochure and
further details.
RELIABILITY BEGINS WITH THE
DESIGN
Quality and reliability must begin with design.
No amount of ex1ra testing or inspection will
produce reliable ICs from a design that is
inherently unreliable. Signetics follows very
strict design and layout practices with its
circuits. To eliminate the possibility of metal
migration, current density in any path cannot
exceed 5 X 10 5 amps/cm 2. Layout rules are
followed to minimize the possibility of shorts,
circuit anomalies, and SCR type latch-up
effects. All circuit designs are computerchecked using the latest CAD software for
adherence to design rules. Simulations are
performed for functionality and parametric
performance over the full operating ranges of
voltage and temperature before going to
production. These steps allow us to meet
device specifications not only the first time,
but also every time thereafter.
•
Signetics Linear Products
Quality Gild Reiiabiiity
PRODUCT CHARACTERIZATION
Before a new design is released, the characterization phase is completed to insure that
the distribution of parameters resulting from
lot-to-Iot variations is well within specified
limits. Such extensive characterization data
also provides a basis for identifying unique
application-related problems which are not
part of normal data sheet guarantees.
PRODUCT QUALIFICATION
Linear products are subjected to rigorous
qualification procedures for all new products
or redesigns to current products. Qualification
testing consists of:
• High Temperature Operating Life:
TJ = 150°C, 1000 hours, static bias
• High Temperature Storage Life:
TJ = 150°C, 1000 hours, unbiased
• Temperature Humidity Biased Life:
85°C, 85% relative humidity, 1000
hours, static bias
• Pressure Cooker:
15 psig, 121°C, 192 hours, unbiased
• Thermal Shock:
-65°C to + 150°C, 300 cycles, 5 minute
dwell, liquid to liquid, unbiased
Formal qualification procedures are required
for all new or changed products, processes,
and facilities. These procedures ensure the
high level of product reliability our customers
expect. New facilities are qualified by corporate groups as well as by the quality organizations of specific units that will operate in the
facility. After qualification, products manufactured by the new facility are subjected to
highly accelerated environmental stresses to
ensure that they can meet rigorous failure
rate requirements. New or changed processes are similarly qualified.
ONGOING RELIABILITY
ASSESSMENT PROGRAMS
The SURE Program
The SURE (Systematic and Uniform Reliability Evaluation) program audits products from
each of Signetics Linear Division's process
families: Low Voltage, Medium Voltage, High
Voltage, and Dual-Layer Metal, under a variety of accelerated stress conditions. This
program, first introduced in 1964, has evolved
to suit changing product complexities and
performance requirements.
The Audit Program
Samples are selected from each process
family every four weeks and are subjected to
each of the following stresses:
• High Temperature Operating Life:
TJ = 150°C, 1000 hours, static bias
• High Temperature Storage Life:
TJ = 150°C, 1000 hours, unbiased
• Temperature Humidity Biased Life:
85°C, 85% relative humidity, 1000
hours, static bias
• Pressure Cooker:
20 psig, 127°C, 72 hours, unbiased
• Thermal Shock:
_65°C to + 150°C, 300 cycles, 5 minute
dwell, liquid-to-liquid, unbiased
• Temperature Cycling:
-65°C to + 150°C, 1000 cycles, 10
minute dwell, air-to-air, unbiased
The Product Monitor Program
In addition, each Signetics assembly plant
performs Pressure Cooker and Thermal
Shock SURE Product Monitor stresses on a
weekly basis on each molded package by pin
count per the same conditions as the SURE
Program.
Product Reliability Reports
The data from these test matrices provides a
basic understanding of product capability, an
indication of major failure mechanisms, and
an estimated failure rate resulting from each
stress. This data is compiled periodically and
is available to customers upon request.
February 1987
2·6
Many customers use this information in lieu of
running their own qualification tests, thereby
eliminating time-consuming and costly additional testing.
Reliability Engineering
In addition to the product performance moni·
tors encompassed in the Linear SURE program, Signetics' Corporate and Division Reliability Engineering departments sustain a
broad range of evaluation and qualification
activities.
Included in the engineering process are:
• Evaluation and qualification of new or
changed materials, assembly/wafer-fab
processes and equipment, product
designs, facilities, and subcontractors.
• Device or generic group failure rate
studies.
• Advanced environmental stress
development.
• Failure mechanism characterization and
corrective action/prevention reporting.
The environmental stresses utilized in the
engineering programs are similar to those
utilized for the SURE monitor; however, more
highly-accelerated conditions and extended
durations typify these engineering projects.
Additional stress systems such as biased
pressure pot, power-temperature cycling, and
cycle-biased temperature-humidity, are also
included in some evaluation programs.
Failure Analysis
The SURE Program and the Reliability Engineering Program both include failure analysis
activities and are complemented by corporate, divisional, and plant failure analysis
departments. These engineering units provide a service to our customers who desire
detailed failure analysis support, who in turn
provide Signetics with the technical understanding of the failure modes and mechanisms actually experienced in service. This
information is essential in our ongoing effort
to accelerate and improve our understanding
of product failure mechanisms and their prevention.
Signetics Linear Products
Quality and Reliability
LINEAR DIVISION LINEAR PROCESS FLOW
0------------
I
0------------
SCANNING ELECTRON MICROSCOPE CONTROL
Wafers are sampled daily by the Quality Control laboratory from each fabrication area and sub)ected
to SEM analysis. This process control reveals manufacturing defects such as contact and oxide step
coverage in the melalization process which may result in early failures.
DIE SORr VISUAL ACCEPTANCE
Product is inspected lor defects caused during fabrication, wafer testing, or Ihe mechanical scnbe
and break operation. Defects SUCh as scratches, smears and glassivated bonding pads are included
in the lot acceptance criteria.
DIE ATIACH AND WIRE BONDING
The latest automated equipment is used under statistical process control program.
o _______ _ ____
PRE·SEAL VISUAL ACCEPTANCE
ProdtJct is inspected to detect any damage incurred at the die attach and wire bonding stations.
Defects SUCh as scratches, contamination and smeared ball borlds are Included in the lot acceptance
criteria.
_ _ _ _ _ _ _ _ _ _ SEAL TESTS
Hermetic package seal integrity is ensured by 100% and fine gross leak testing.
SYMBOL
Devices are marked with the Signetics logo, device number and period date code of assembly or
custom symbol per individual specification requirements.
_ _ _ _ _ _ _ _ 100% PRODUCTION ELECTRICAL TESTING
Every device is tested to all data sheet parameters guaranteeing temperature specifications,
BURN·IN (SUPR 11 LEVEL B OPTION)
Devices are burned in for 21 !lours at ISS"C maximum Junction Temperature,
100% PRODUCTION ELECTRICAL TESTING
Every device is tested to all data sheet parameters guaranteeing temperature specifications.
_ _ _ _ _ _ _ _ VISUAL
All products are visually inspected per the requirements specified in Signetics' or customer
documents,
_ _ _ _ _ _ _ _
FINAL QUALITY ASSURANCE GATE
The final QA inspection step guarantees the specified mechanical and electrical AQL's. Every ship"
ment is sealed and identified by QA personnel.
February 1987
2-7
•
Signetics
Section 3
Small Area Networks
Linear Products
•
INDEX
Introduction to 12 C ...................................................................................
12C Bus Specification................................................................................
AN166
The Inter-Integrated Circuit (12C) Serial Bus: Theory and
Practical Considerations.......................................................
3-3
3-4
3-16
Signetics
Introduction to 12C
Linear Products
THE 12 C CONCEPT
The Inter-IC bus (12C) is a 2-wire serial bus
designed to provide the facilities of a small
area network, not only between the circuits of
one system, but also between different systems; e.g., teletext and tuning.
Philips/Signetics manufactures many devices
with built-in 12C interface capability, any of
which can be connected in a system by
simply "clipping" it to the 12C bus. Hence, any
collection of these devices around the 12C
bus is known as "clips."
The 12C bus consists of two bidirectional
lines: the Serial Data (SDA) line and the Serial
Clock (SCl) line. The output stages of devices connected to the bus (these devices
could be NMOS, CMOS, 12 C, TTL, ... ) must
have an open-drain or open-collector in order
to perform the wired-AND function. Data on
February 1987
the 12 C bus can be transferred at a rate up to
100kbits/sec. The physical bus length is
limited to 13 feet and the number of devices
connected to the bus is solely dependent on
the limiting bus capacitance of 400pF.
The inherent synchronization process, built
into the 12 C bus structure using the wiredAND technique, not only allows fast devices
to communicate with slower ones, but also
eliminates the "Carrier Sense Multiple Access/Collision Detect" (CSMAlCD) effect
found in some local area networks, such as
Ethernet.
Master-slave relationships exist on the 12 C
bus; however, there is no central master.
Therefore, a device addressed as a slave
during one data transfer could possibly be the
master for the next data transfer. Devices are
also free to transmit or receive data during a
transfer.
To summarize, the 12C bus eliminates interfacing problems. Since any peripheral device
can be added or taken away without affecting
any other devices connected to the bus, the
12C bus enables the system designer to build
various configurations using the same basic
architecture.
Application areas for the 12 C bus include:
Video Equipment
Audio Equipment
Computer Terminals
Home Appliances
Telephony
Automotive
Instrumentation
Industrial Control
3-3
•
Signetics
I"
....
.
~
~peCITICaTIOn
Linear Products
INTRODUCTION
For 8-bit applications, such as those requiring
single-chip microcomputers, certain design
criteria can be established:
• A complete system usually consists
of at least one microcomputer and
other peripheral devices, such as
memories and 1/0 expanders.
• The cost of connecting the various
devices within the system must be
kept to a minimum.
• Such a system usually performs a
control function and does not require
high-speed data transfer.
• Overall efficiency depends on the
devices chosen and the
Interconnecting bus structure.
In order to produce a system to satisfy these
criteria, a serial bus structure is needed.
Although serial buses don't have the throughput capability of parallel buses, they do require less wiring and fewer connecting pins.
However, a bus is not merely an interconnecting wire, it embodies all the formats and
procedures for communication within the system.
Devices communicating with each other on a
serial bus must have some form of protocol
which avoids all possibilities of confusion,
data loss and blockage of information. Fast
devices must be able to communicate with
slow devices. The system must not be dependent on the devices connected to it, otherwise modifications or improvements would be
impossible. A procedure has also to be resolved to decide which device will be in
control of the bus and when. And if different
devices with different clock speeds are connected to the bus, the bus clock source must
be defined.
a receiver, while a memory can both receive
and transmit data. In addition to transmitters
and receivers, devices can also be considered as masters or slaves when performing
data transfers (see Table 1). A master is the
device which initiates a data transfer on the
bus and generates the clock signals to permit
that transfer. At that time, any device addressed is considered a slave.
The 12C bus is a multi-master bus. This means
that more than one device capable of controlling the bus can be connected to it. As
masters are usually microcomputers, let's
consider the case of a data transfer between
two microcomputers connected to the 12 C
bus (Figure 1). This highlights the masterslave and receiver-transmitter relationships to
be found on the 12 C bus. It should be noted
that these relationships are not permanent,
but only depend on the direction of data
transfer at that time. The transfer of data
would follow in this way:
1) Suppose microcomputer A wants to send
information to microcomputer B
- microcomputer A (master) addresses
microcomputer B (slave)
- microcomputer A (master transmitter)
sends data to microcomputer B (slave
receiver)
- microcomputer A terminates the
transfer.
2) " microcomputer A wants to receive information from microcomputer B
- microcomputer A (master) addresses
microcomputer B (slave)
- microcomputer A (master receiver)
receives data from microcomputer B
(slave transmitter)
- microcomputer A terminates the
transfer.
Even in this case, the master (microcomputer
A) generates the timing and terminates the
transfer.
The possibility of more than one microcomputer being connected to the 12C bus means
that more than one master could try to initiate
a data transfer at the same time. To avoid the
chaos that might ensue from such an event,
an arbitration procedure has been developed.
This procedure relies on the wired-AND connection of all devices to the 12C bus.
" two or more masters try to put information
on to the bus, the first to produce a one when
the other produces a zero will lose the
arbitration. The clock signals during arbitration are a synchronized combination of the
clocks generated by the masters using the
wired-AND connection to the SCl line (for
more detailed information concerning arbitration see Arbitration and Clock Generation).
Generation of clock signals on the 12 C bus is
always the responsibility of master devices;
each master generates its own clock signals
when transferring data on the bus. Bus clock
signals from a master can only be altered
when they are stretched by a slow slave
All these criteria are involved in the specification of the 12C bus.
THE 12C BUS CONCEPT
Any manufacturing process (NMOS, CMOS,
12l) can be supported by the 12C bus. Two
wires (SDA - serial data, SCl - serial clock)
carry information between the devices connected to the bus. Each device is recognized
by a unique address - whether it is a microcomputer, LCD driver, memory or keyboard
interface - and can operate as either a transmitter or receiver, depending on the function
of the device. Obviously an LCD driver is only
February 1987
Figure 1. Typical 12C Bus Configuration
3-4
Signetlcs Linear Products
12C Bus Specification
Table 1. Definition of 12C Bus Terminology
TERM
device holding down the clock line or by
another master when arbitration takes place.
DESCRIPTION
Transmitter
The device which sends data to the bus
Receiver
The device which receives data from the bus
Master
The device which initiates a transfer, generates clock
signals and terminates a transfer
Slave
The device addressed by a master
Multi-master
More than one master can attempt to control the
bus at the same time without corrupting the message
Arbitration
Procedure to ensure that if more than one master
simultaneously tries to control the bus, only one is
allowed to do so and the message is not corrupted
Synchronization
Procedure to synchronize the clock signals of two or
more devices
GENERAL CHARACTERISTICS
Both SDA and SCl are bidirectional lines,
connected to a positive supply voltage via a
pull·up resistor (see Figure 2). When the bus
is free, both lines are High. The output stages
of devices connected to the bus must have
an open·drain or open·collector in order to
perform the wired-AND function. Data on the
12C bus can be transferred at a rate up to
100kbit/s. The number of devices connected
to the bus is solely dependent on the limiting
bus capacitance of 400pF.
BIT TRANSFER
--?--~---
SDA
+voo
(SERIAL DATA LINE)
(SERIALCLDCK UNE)
~L~------~~------t----+------~---------+---
r-----I
II I
r-----I
II ~LK1
-I
-I
I
I
I
~LK
I
I
SCLK2--.l
--.l
o~
I
I
DATA
IN
I
I
I
I
I
I
I
I
I
OUT
SCLK
IN
DATA
IN
I
II _______________ ..JI IL _______________ ...lI
IN
DEVlCE1
DEVICE 2
Figure 2. Connection of Devices to the 12 C Bus
I
SDA
~L
Start and Stop Conditions
Within the procedure of the 12C bus, unique
situations arise which are defined as start and
stop conditions (see Figure 4).
A High-to-low transition of the SDA line while
SCL is High is one such unique case. This
situation indicates a start condition.
I
A low-to-High transition of the SDA line while
SCl is High defines a stop condition.
~~
Start and stop conditions are always generated by the master. The bus is considered to be
busy after the start condition. The bus is
considered to be free again a certain time
after the stop condition. This bus free situation will be described later in detail.
I
DATA UNE
I
STABLE:
DATA VALID
I
I
I
CHANGE
I
OF DATA
ALLDWED
I
I
Figure 3. Bit Transfer on the 12 C Bus
C~
SDA-f'l
I
~L-~
L:J
r~
"---I
START CONDITION
:1tI
SDA
I
rtj-SCL
'--/ L~J
STOP CONDITION
Detection of start and stop conditions by
devices connected to the bus is easy if they
possess the necessary interfacing hardware.
However, microcomputers with no such interface have to sample the SDA line at least
twice per clock period in order to sense the
transition.
TRANSFERRING DATA
Byte Format
Every byte put on the SDA line must be 8 bits
long. The number of bytes that can be
transmitted per transfer is unrestricted. Each
byte must be followed by an acknowledge bit.
Figure 4. Start and Stop Conditions
February 1987
Data Validity
The data on the SDA line must be stable
during the High period of the clock. The High
or low state of the data line can only change
when the clock signal on the SCl line is low
(Figure 3).
(r-l---t--!>Ch~
I
I
Due to the variety of different technology
devices (CMOS, NMOS, 12 l) which can be
connected to the 12 C bus, the levels of the
logical 0 (low) and 1 (High) are not fixed and
depend on the appropriate level of VDD (see
Electrical Specifications). One clock pulse is
generated for each data bit transferred.
3-5
•
Signetics Linear Products
12C Bus Specification
r-l
SDAN-i:XX
I
I
I
I
I
I
I
I
MS8
I
I
I
BYTE COMPLETE,
INTERRUPT WITHIN RECEIVER
I
I
I
CLOCK UNE HELD lJJW WHILE
INTERRUPTS ARE SERVICED
~ ~
is
iV'V2y
L_...l
SCL-t---i
START
CONDITION
Figure 5. Data Transfer on the 12C Bus
DATAOUTPUT
BYTRANSMITTER
-R
II
I
I
I
I
:T:~~~ I
I
I
I
I
I
I
SCrill\-C:
I
I
S
~::x
X
/ _ _ _...J
~I_I.
'-___
_
/
_ _oJ
(~
~
I
I
L.:~
t
START
CONDITION
CLOCK PULSE FOR
ACKNOWLEDGEMENT
Figure 6. Acknowledge on the 12C Bus
Data is transferred with the most significant
bit (MSB) first (Figure 5). If a receiving device
cannot receive another complete byte of data
until it has performed some other function, for
example, to service an internal interrupt, it
can hold the clock line SCl low to force the
transmitter into a wait state. Data transfer
then continues when the receiver is ready for
another byte of data and releases the clock
line SCL.
In some cases, it is permitted to use a
different format from the 12 C bus format, such
as CBUS compatible devices. A message
which starts with such an address can be
terminated by the generation of a stop condi·
tion, even during the transmission of a byte.
In this case, no acknowledge is generated.
Acknowledge
Data transfer with acknowledge is obligatory.
The acknowledge-related clock pulse is generated by the master. The transmitting device
releases the SDA line (High) during the ac·
knowledge clock pulse.
February 1987
The receiving device has to pull down the
SDA line during the acknowledge clock pulse
so that the SDA line is stable low during the
high period of this clock pulse (Figure 6). Of
course, setup and hold times must also be
taken into account and these will be de·
scribed in the Timing section.
Usually, a receiver which has been addressed
is obliged to generate an acknowledge after
each byte has been received (except when
the message starts with a CBUS address.
When a slave receiver does not acknowledge
on the slave address, for example, because it
is unable to receive while it is performing
some real·time function, the data line must be
left High by the slave. The master can then
generate a STOP condition to abort the
transfer.
If a slave receiver does acknowledge the
slave address, but some time later in the
transfer cannot receive any more data bytes,
the master must again abort the transfer. This
is indicated by the slave not generating the
acknowledge on the first byte following. The
3-6
slave leaves the data line High and the
master generates the STOP condition.
In the case of a master receiver involved in a
transfer, it must signal an end of data to the
slave transmitter by not generating an ac·
knowledge on the last byte that was clocked
out of the slave. The slave transmitter must
release the data line to allow the master to
generate the STOP condition.
ARBITRATION AND CLOCK
GENERATION
Synchronization
All masters generate their own clock on the
SCl line to transfer messages on the 12 C bus.
Data is only valid during the clock High period
on the SCl line; therefore, a defined clock is
needed if the bit·by·bit arbitration procedure
is to take place.
Clock synchronization is performed using the
wired·AND connection of devices to the SCl
LINE. This means that a High·to·low transi·
Signetics Linear Products
12C Bus Specification
1_
1
ClK
1
____
~~
____
STAHr COUNTING
WAIT -l-...!I~HPERIOD
STATE
1
--...,
~r------------~------
Arbitration can carry on through many bits.
The first stage of arbitration is the comparison
of the address bits. If the masters are each
trying to address the same device. arbitration
continues into a comparison of the data.
Because address and data information is
used on the 12C bus for the arbitration. no
information is lost during this process.
ClK
2 ____
A master which loses the arbitration can
generate clock pulses until the end of the
byte in which it loses the arbitration.
SCl
If a master does lose arbitration during the
addressing stage. it is possible that the winning master is trying to address it. Therefore.
the losing master must switch over immediately to its slave receiver mode.
+-__~_,~~--____--------..r-+_~-----~--~--
Figure 7. Clock Synchronization During the Arbitration Procedure
TRANSMITTER 1 LOSES ARBITRATION
DATA1~SDA
DATA
1
DATA
2,L·'-.Jc~--~--'-------r---{·------+-'----~
SDA
SCl
Use of the Clock Synchronizing
Mechanism as a Handshake
Figure 8. Arbitration Procedure of Two Masters
tion on the Sel line will affect the devices
concerned. causing them to start counting off
their low period. Once a device clock has
gone low it will hold the SCl line in that state
until the clock High state is reached (Figure
7). However. the low-to-High change in this
device clock may not change the state of the
SCl line if another device
clock is still within its low period. Therefore.
SCl will be held low by the device with the
longest low period. Devices with shorter low
periods enter a High wait state during this
time.
When all devices concerned have counted off
their low period. the clock line will be released and go High. There will then be no
difference between the device clocks and the
February 1987
Figure 8 shows the arbitration procedure for
two masters. Of course more may be involved. depending on how many masters are
connected to the bus. The moment there is a
difference between the internal data level of
the master generating DATA 1 and the actual
level on the SDA line. its data output is
switched off. which means that a High output
level is then connected to the bus. This will
not affect the data transfer initiated by the
winning master. As control of the 12 C bus is
decided solely on the address and data sent
by competing masters. there is no central
master. nor any order of priority on the bus.
state of the Sel line and all of them will start
counting their High periods. The first device
to complete its High period will again pull the
Sel line low.
In this way. a synchronized SCl clock is
generated for which the low period is determined by the device with the longest clock
low period while the High period on Sel is
determined by the device with the shortest
clock High period.
Arbitration
Arbitration takes place on the SDA line in
such a way that the master which transmits a
High level. while another master transmits a
low level. will switch off its DATA output
stage since the level on the bus does not
correspond to its own level.
3-7
In addition to being used during the arbitration
procedure. the clock synchronization mechanism can be used to enable receiving devices
to cope with fast data transfers. either on a
byte or bit level.
On the byte level. a device may be able to
receive bytes of data at a fast rate. but needs
more time to store a received byte or prepare
another byte to be transmitted. Slave devices
can then hold the SCl line low. after reception and acknowledge of a byte. to force the
master into a wait state until the slave is
ready for the next byte transfer in a type of
handshake procedure.
On the bit level. a device such as a microcomputer without a hardware 12C interface
on-Chip can slow down the bus clock by
extending each clock low period. In this way.
the speed of any master is adapted to the
internal operating rate of this device.
Signetics Unear Products
12C Bus Specification
FORMATS
Data transfers foliow the format shown in
Figure 9. After the start condition, a slave
address is sent. This address is 7 bits long;
the eighth bit is a data direction bit (R/W). A
zero indicates a transmission (WRITE); a one
indicates a request for data (READ). A data
transfer is always terminated by a stop condition generated by the master. However, if a
master still wishes to communicate on the
bus, it can generate another start condition,
and address another slave without first generating a stop condition. Various combinations
of read/write formats are then possible within
such a transfer.
At the moment of the first acknowledge, the
master transmitter becomes a master receiv-
er and the slave receiver becomes a slave
transmitter. This acknowledge is stili generated by the slave.
The stop condition is generated by the master.
During a change of direction within a transfer,
the start condition and the slave address are
both repeated, but with the R/W bit reversed.
Figure 9. A Complete Data Transfer
Possible Data Transfer Formats are:
a) Master transmitter transmits to slave
receiver. Direction is not changed.
S
SLAVE ADDRESS
A
A
DATA
DATA
P
A
II
A = ACKNOWLEDGE
S=START
P-STOP
b) Master reads slave immediately after
first byte.
R/W
'O'(WRITE)
DATA TRANSFERRED
+ ACKNOWLEDGE)
(n BYTES
S
SLAVE ADDRESS
R/W
A
DATA
DATA
A
A
P
12
~'(READ)
DATA TRANSFERRED
+ ACKNOWLEDGE)
(n BYTES
c) Combined formats.
I s I SLAVE ADDRESS I R/W I A I DATA I A I s I SLAVE ADDRESS I R/W I A I DATA I A I p I
READ OR
WRITE
J
J lLtP
~p
(n BYTES
(n BYTES
+ ACKNOWLEDGE)
+ ACKNOWLEDGE)
READ OR
WRITE
DIRECTION OF
TRANSFER MAY
CHANGE AT
THIS POINT
NOTES:
1. Combined formats can be used, for example, to control a sarial memory. During the first data byte, the internal memory location has to be written. After the start condition is repeated.
data can then be transferred.
2. All decisions on auto-increment or decrement of previously accessed memory locations, etc., are taken by the designer of the device.
3, Each byte is followed by an acknowledge as Indicated by the A blocks in the sequence.
4. r2c devices have to reset their bus logic on receipt of a start condition so that they all anticipate the sending of a slave address.
February 1987
3-8
Signetics linear Products
12C Bus Specification
ADDRESSING
The first byte aiter the start condition determines which slave will be selected by the
master. Usually, this first byte follows that
start procedure. The exception is the general
call address which can address all devices.
When this address is used, all devices
should, in theory, respond with an acknowledge, although devices can be made to
ignore this address. The second byte of the
general call address then defines the action
to be taken.
Definition of Bits in the First
Byte
The first seven bits of this byte make up the
slave address (Figure 10). The eighth bit
(LSB -least significant bit) determines the
direction of the message. A zero on the least
significant position of the first byte means that
the master will write information to a selected
slave; a one in this position means that the
master will read information from the slave.
MSB
-SLAVEADDRESS-
o
I0 I0
A
FIRST BYTE
X
X
X
X
X
x
x
LSB
I
B
A
SECONDBVTE
(GENERAL CALL ADDRESS)
Figure 11_ General Call Address Format
H'06'
I S I woo' I A I H'02' I A I ABCDQOO I X I A I ABCDOO1 I X I A I ABCD010 I X I A I p I
Figure 12. Sequence of a Programming Master
bilities in group 1111 will also only be used for
extension purposes but are not yet allocated.
The combination OOOOXXX has been defined
as a special group. The following addresses
have been allocated:
FIRST BYTE
Slave
Address
edge this address and behave as a slave
receiver. The second and following bytes will
be acknowledged by every slave receiver
capable of handling this data. A slave which
cannot process one of these bytes must
ignore it by not acknowledging.
The meaning of the general call address is
always specified in the second byte (Figure
11).
R/W
Figure 10_ The First Byte After the
Start Procedure
0000
0000
000
000
0
1
General call address
Start byte
There are two cases to consider:
1. When the least significant bit B is a zero.
2. When the least significant bit B is a one.
When an address is sent, each device in a
system compares the first 7 bits after the start
condition with its own address. If there is a
match, the device will consider itself addressed by the master as a slave receiver or
slave transmitter, depending on the R/W bit.
0000
0000
001
010
X
X
CBUS address
Address reserved for
different bus format
When B is a zero, the second byte has the
following definition:
0000
0000
0000
0000
0000
all
100
101
110
111
X
X
X
X
X
The slave address can be made up of a fixed
and a programmable part. Since it is expected
that identical ICs will be used more than once
in a system, the programmable part of the
slave address enables the maximum possible
number of such devices to be connected to
the 12C bus. The number of programmable
address bits of a device depends on the
number of pins available. For example, if a
device has 4 fixed and 3 programmable
address bits, a total of eight identical devices
can be connected to the same bus.
12 C
The
bus committee is available to coordinate allocation of 12 C addresses.
The bit combination 1111 XXX of the slave
address is reserved for future extension purposes.
The address 1111111 is reserved as the
extension address. This means that the addressing procedure will be continued in the
next byte(s). Devices that do not use the
extended addressing do not react at the
reception of this byte. The seven other possi-
February 1987
}, '" "'00'
No device is allowed to acknowledge at the
reception of the start byte.
The CBUS address has been reserved to
enable the intermixing of CBUS and 12C
devices in one system. 12 C bus devices are
not allowed to respond at the reception of this
address.
The address reserved for a different bus
format is included to enable the mixing of 12 C
and other protocols. Only 12C devices that are
able to work with such formats and protocols
are allowed to respond to this address.
General Call Address
The general call address should be used to
address every device connected to the 12C
bus. However, if a device does not need any
of the data supplied within the general call
structure, it can ignore this address by not
acknowledging. If a device does require data
from a general call address, it will acknowl-
3-9
00000110 (H'06') Reset and write the programmable part of slave
address by software and
hardware. On receiving this
two-byte sequence, all devices (designed to respond
to the general call address)
will reset and take in the
programmable part of their
address.
Precautions must be taken
to ensure that a device is
not pulling down the SDA
or SCL line after applying
the supply voltage, since
these low levels would
block the bus.
00000010 (H'02') Write slave address by
software only. All devices
which obtain the programmable part of their address
by software (and which
have been designed to respond to the general call
address) will enter a mode
in which they can be programmed. The device will
not reset.
•
Signetics Linear Products
12C Bus Specification
An example of a data transfer of a programming master is shown in Figure 12 (ABCD
represents the fixed part of the address).
(8)
s
00000100 (H'04') Write slave address by
hardware only. All devices
which define the programmable part of their address
by hardware (and which respond to the general call
address) will latch this programmable part at the reception of this two-byte sequence. The device will not
. reset.
oooooooo
A
I
S
I
DATA
I
A
P
,
P
I
(n BYTES + ACKNOWLEDGE)
SlAVEADDR H/WMASrER
R/W
I I
A
DUMPADDRFORH/WMASrER
IX I
A
I
WRITE
a. Configuring master sends dump address to hardware master
s
DUMPADDR FROM H/W MASrER
I
R/VI
IA
I
WRITE
II
+ ACKNOWLEDGE)
(n BYTES
AFQ3570S
When B is a one, the two-byte sequence is a
hardware general call. This means that the
sequence is transmitted by a hardware master device, such as a keyboard scanner,
which cannot be programmed to transmit a
desired slave address. Since a hardware
master does not know in advance to which
device the message must be transferred, it
can only generate this hardware general call
and its own address, thereby identifying itself
to the system (Figure 13).
February 1987
A
1/
BYTE
The remaining codes have not been fixed and
devices must ignore these codes.
Start Byte
Microcomputers can be connected to the 12C
bus in two ways. If an on-chip hardware 12C
bus interface is present, the microcomputer
can be programmed to be interrupted only by
requests from the bus. When the device
possesses no such interface, it must constantly monitor the bus via software. Obvious-
DATA
Figure 13. Data Transfer From Hardware Master Transmitter
Sequences of programming procedure are
published in the appropriate device data
sheets.
In some systems an alternative could be that
the hardware master transmitter is brought in
the slave receiver mode after the system
reset. In this way, a system configuring master can tell the hardware master transmitter
(which is now in slave receiver mode) to
which address data must be sent (Figure 14).
After this programming procedure, the hardware master remains in the master transmitter mode.
A
SECOND
GENERAL
CALL ADDRESS
00000000 (H'OO') This code is not allowed to
be used as the second
byte.
The seven bits remaining in the second byte
contain the device address of the hardware
master. This address is recognized by an
intelligent device, such as a microcomputer,
connected to the bus which will then direct
the information coming from the hardware
master. If the hardware master can also act
as a slave, the slave address is identical to
the master address.
I
1
MASrER ADDRESS
b. Hardware master dumps data to selected slave device
Figure 14. Data Transfer of Hardware Master Transmitter Capable of Dumping
Data Directly to Slave Devices
ri
1\!
??
SOA
I
I
SCL"ji\.
I. I V
/
ri
!\l-
ACK~~~DGE
I
(H)
I
JHi _i
r;\. r;\.
r;\ J;:\. J;:\.
. V - \...r.(-f . V - VACKV
L -1
LSr-1
S
!----STARTBYTEOOOOOOO1-!
Figure 15. Start Byte Procedure
Iy, the more times the microcomputer monitors, or polls, the bus, the less time it can
spend carrying out its intended function.
Therefore, there is a difference in speed
between fast hardware devices and the relatively slow microcomputer which relies on
software polling.
In this case, data transfer can be preceded by
a start procedure which is much longer than
normal (Figure 15). The start procedure consists of:
a)
b)
c)
d)
A start condition, (S)
A start byte 00000001
An acknowledge clock pulse
A repeated start condition, (Sr)
After the start condition (S) has been transmitted by a master requiring bus access, the
3-10
start byte (00000001) is transmitted. Another
microcomputer can therefore sample the
SDA line on a low sampling rate until one of
the seven zeros in the start byte is detected.
After detection of this Low level on the SDA
line, the microcomputer is then able to switch
to a higher sampling rate in order to find the
second start condition (Sr) which is then used
for synchronization.
A hardware receiver will reset at the reception
of the second start condition (Sr) and will
therefore ignore the start byte.
After the start byte, an acknowledge-related
clock pulse is generated. This is present only
to conform with the byte handling format used
on the bus. No device is allowed to acknowledge the start byte.
Signelics Linear Products
12C Bus Specification
r,
I
~
I I
r..,
~I--------------------J
8M
I
I I
~
I
sec
I
I
DCENII
I
-rL8~J~I------------------------I-L-J---L-J---J
CO~~ON
A;~~:ss
~:
12
L ________________________________~I
I
~
I I
I I
II
L~
LDA;B~~LSE CO~~ON
n DATA BITS
ACK
RELATED
CLOCK PULSE
Figure 16. Data Format of Transmissions With CBUS Receiver/Transmitter
CBUS Compatibility
Existing CBUS receivers can be connected to
the 12C bus. In this case, a third line called
DLEN has to be connected and the acknowl·
edge bit omitted. Normally, 12C transmissions
are multiples of 8·bit bytes; however, CBUS
devices have different formats.
In a mixed bus structure, 12C devices are not
allowed to respond on the CBUS message.
For this reason, a special CBUS address
(0000001 X) has been reserved. No 12 C device will respond to this address. After the
transmission of the CBUS address, the DLEN
line can be made active and transmission,
according to the CBUS format, can be performed (Figure 16).
V 001-4=5V:t100/0
SDA--~-;----~+-----~r---~--r---~-;-
SCl----~------4-----
__~----__~----~--
Figure 17. Fixed Input Level Devices Connected to the 12C Bus
Voo = e.g. 3V
After the stop condition, all devices are again
ready to accept data.
Master transmitters are allowed to generate
CBUS formats after having sent the CBUS
address. Such a transmission is terminated
by a stop condition, recognized by all devices.
In the low speed mode, full 8-bit bytes must
always be transmitted and the timing of the
DLEN signal adapted.
If the CBUS configuration is known and no
expansion with CBUS devices is foreseen,
the user is allowed to adapt the hold time to
the specific requirements of device(s) used.
ELECTRICAL SPECIFICATIONS
OF INPUTS AND OUTPUTS OF
12C DEVICES
The 12 C bus allows communication between
devices made in different technologies which
might also use different supply voltages.
For devices with fixed input levels, operating
on a supply voltage of + 5V ± 10%, the following levels have been defined:
Vilmax = 1.5V (maximum input Low
voltage)
February 1987
SDA--4--;----4-+-----~t_--~~r----4_;-SCl-----+----~
______
~------+-----_1_
Figure 18. Devices With a Wide Range of Supply Voltages Connected
to the 12 C Bus
VIHmin = 3V (minimum input High
voltage)
Devices operating on a fixed supply voltage
different from + 5V (e.g. 12L), must also have
these input levels of 1.5V and 3V for Vil and
VIH, respectively.
For devices operating over a wide range of
supply voltages (e.g. CMOS), the following
levels have been defined:
Vilmax = 0.3V DD (maximum input Low
voltage)
VIHmin = 0.7VDD (minimum input High
voltage)
For both groups of devices, the maximum
output Low value has been defined:
VO lmax = OAV (max. output voltage Low)
at 3mA sink current
3-11
The maximum low-level input current at
VOlmax of both the SDA pin and the SCL pin
of an 12C device is -101lA, including the
leakage current of a possible output stage.
The maximum high·level input current at
0.9VDD of both the SDA pin and SCL pin of an
12C device is 10llA, including the leakage
current of a possible output stage.
The maximum capacitance of both the SDA
pin and the SCL pin of an 12 C device is 10pF.
Devices with fixed input levels can each have
their own power supply of + 5V ± 10%. Pullup resistors can be connected to any supply
(see Figure 17).
However, the devices with input levels related
to VDD must have one common supply line to
which the pull-up resistor is also connected
(see Figure 18).
..
Signetlcs Linear Products
J2
C Bus Specification
When devices with fixed input levels are
mixed with devices with Voo-related levels,
the latter devices have to be connected to
one common supply line of +5V ± 10% along
with the pull-up resistors (Figure 19).
VDDI =5V :1:10%
Rp
VDD2 =5V:t100/0
vDOS=SV:t1O%
Rp
Input levels are defined in such a way that:
1. The noise margin on the Low level is 0.1
Voo·
2. The noise margin on the High level is 0.2
Voo·
3. Series resistors (Rs) up to 300n can be
used for flash-over protection against high
voltage spikes on the SDA and SCL line
(due to flash-over of a TV picture tube, for
example) (Figure 20).
~.~--+---~----~--~~--~~__
__+-______~L----
----~~----~----
Figure 19. Devices With Voo Related Levels Mixed With Fixed Input Level
Devices on the I C Bus
Voo
The maximum bus capacitance per wire is
400pF. This includes the capacitance of the
wire itself and the capacitance of the pins
connected to it.
I O~CE I I D~CE I
R.
TIMING
SOA
The clock on the 12C bus has a minimum Low
period of 4.71-'s and a minimum High period of
41-'s. Masters in this mode can generate a bus
clock with a frequency from 0 to 100kHz.
~L
All devices connected to the bus must be
able to follow transfers with frequencies up to
100kHz, either by being able to transmit or
receive at that speed or by applying the clock
synchronization procedure which will force
the master into a wait state and stretch the
Low periods. In the latter case the frequency
is reduced.
Figure 21 shows the timing requirements in
detail. A description of the abbreviations used
is shown in Table 2. All timing references are
at VILmax and VILmin.
r
vI"
Rs
R.
R.
Rp
LD05650S
Figure 20. Serial Resistors (Rs) for Protection Against High Voltage
LOW-SPEED MODE
Data Format and Timing
As explained previously, there is a difference
in speed on the 12C bus between fast hardware devices and the relatively slow microcomputer which relies on software polling.
For this reason a low speed mode is available
on the 12C bus to allow these microcomputers
to poll the bus less often.
The bus clock in this mode has a Low period
of 130l-'s ± 251-'s and a High period of
390l-'s ± 251-'s, resulting in a clock frequency
of approx. 2kHz. The duty cycle of the clock
has this Low-to-High ratio to allow for more
efficient use of microcomputers without an
on-chip hardware 12C bus interface. In this
mode also, data transfer with acknowledge is
obligatory. The maximum number of bytes
transferred is not limited (Figure 22).
Start and Stop Conditions
In the low-speed mode, data transfer is preceded by the start procedure.
Figure 21_ Timing Requirements for the 12C Bus
February 1987
Rp
3-12
Signetics Linear Products
12C Bus Specification
Table 2. Timing Requirement for the 12C Bus
LIMITS
SYMBOL
UNIT
PARAMETER
fSCL
SCl clock frequency
tauF
Time the bus must be free before a new transmission can start
tHO; STA
Hold time start condition. After this period the first clock pulse is generated
tLOW
tHIGH
tsu; STA
tHO; OAT
Min
Max
0
100
J.1S
4
J.ls
The low period of the clock
4.7
J.ls
The High period of the clock
4
J.ls
Setup time for start condition (Only relevant for a repeated start condition)
4.7
J.lS
Hold
for
for
o·
5
J.1S
J.lS
time DATA
CBUS compatible masters
12 C devices
250
tsu; OAT
Setup time DATA
tR
Rise time of both SDA and SCl lines
tF
Fall time of both SOA and SCl lines
tsu; STO
Setup time for stop condition
ns
1
300
4.7
Figure 22. Data Transfer Low·Speed Mode
$1M
I
I
I
I
I
I
-+..--...j
LS.J
IttD; srA
~
1----tHIGH----1
Figure 23. Timing Low·Speed Mode
February 1987
3·13
J.lS
ns
J.lS
NOTES:
All values referenced to V1H and VIL levels .
• Note that a transmitter must internally provide a hold time to bridge the undefined region (300n5 max.) of the falling edge of
SCL
kHz
4.7
sel.
•
Signetlcs Linear Products
12C Bus Specification
LOW SPEED MODE
CLOCK
DUTY CYCLE
START BYTE
MAX. NO. OF BYTES
PREMATURE TERMINATION OF TRANSFER
ACKNOWLEDGE CLOCK BIT
ACKNOWLEDGEMENT OF SLAVES
tLOW = 130I.LS ± 25I.Ls
tHIGH = 3901.LS ± 25I.Ls
1:3 Low-to-High (Duty cycle of
clock generator)
0000 0001
UNRESTRICTED
NOT ALLOWED
ALWAYS PROVIDED
OBLIGATORY
In this mode, a transfer cannot be terminated
during the transmission of a by1e.
The bus is considered busy after the first start
condition. It is considered free again one
minimum clock Low period, 1051.Ls, after the
detection of the stop condition. Figure 23
shows the timing requirements in detail, Table
3 explains the abbreviations.
Table 3. Timing Low Speed Mode
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Max
tSUF
Time the bus must be free before a new transmission can start
105
I.LS
tHO; STA
Hold time start condition. After this period the first clock pulse is generated
365
!.IS
tHo; STA
Hold time (repeated start condition only)
210
tLOW
The Low period of the clock
105
155
I.Ls
tHIGH
The High period of the clock
365
415
!.Is
tsu: STA
Setup time for start condition (Only relevant for a repeated start condition)
105
155
!.IS
tHO; tOAT
Hold time DATA
for CBUS compatible masters
for 12C devices
O'
tsu; OAT
Setup time DATA
250
tR
Rise time of both SDA and SCL lines
tF
Fall time of both SDA and SCL lines
tsu; STO
Setup time for stop condition
I.Ls
5
I.Ls
I.LS
ns
1
105
300
ns
155
p.s
NOTES:
All values referenced to V,H and V,L levels.
.. Note that a transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.
February 1987
3-14
I.Ls
Signetics Linear Products
12C Bus Specification
APPENDIX A
Maximum and minimum values of the pull-up
resistors Rp and series resistors Rs (See
Figure 20).
In a 12C bus system these values depend on
the following parameters:
- Supply voltage
- Bus capacitance
- Number of devices (input current + leakage current)
1) The supply voltage limits the minimum value of the Rp resistor due
to the specified 3mA as minimum
sink current of the output stages,
at OAV as maximum low voltage.
In Graph 1, VDD against Rpmin is
"hown.
In Graph 2, Rsmax against Rp is shown.
2) The bus capacitance is the total capacitance of wire, connections, and
pins. This capacitance limits the maximum value of Rp because of the
specified rise time of 1MS.
In Graph 3. the bus capacitance - RPmax
relationship is shown.
3) The maximum high-level input current
of each input! output connection has a
specified value of 10p.A max. Due to
the desired noise margin of 0.2 VDD
for the high level, this input current
limits the maximum value of Rp. This
limit is dependent on VDD.
In Graph 4 the total high-level input current - RPmax relationship is shown.
~
20
~
~
a:
w
3
400
/
Q"
1200
1600
!i:Ii
0
0
\
16
./Rs=O
MAX.R~~
Graph 1
The desired noise margin of 0.1 VDD for the
low level limits the maximum value of Rs.
I:,..
@VDD-j
o
D
100
-.....::::
300
BUS CAPACITANCE (pF)
Graph 3
February 1987
60
120
160
200
Graph 4
~
o
40
TOTAL HIGH LEVEL INPUT CURRENT (,.A)
,
V
12
:Ii
:Ii
:::>
Graph 2
/MAX.Rs
o
12
~
MAXIMUM VALUE Rs <0>
:/: ~
~
600
16
3·15
--=
400
12C LICENSE
Purchase of Signetics or Philips 12C components conveys a license under the Philips 12C
patent rights to use these components in an
12C system, provided that the system conforms to the 12C standard specification as
defined by Philips.
•
Signetics
AN168
The Inter-Integrated Circuit (12C)
Serial Bus: Theory and
Practical Consideration
Linear Products
Author: Carl Fenger
INTRODUCTION
The 12C (Inter-IC) bus is becoming a popular
concept which implements an innovative serial bus protocol that needs to be understood.
On the hardware level 12C is a collection of
microcomputers (MAB8400, PCD3343,
83C3S1, 84CXX) and peripherals (lCD/lED
drivers, RAM, ROM, clock/timer, AID, D/ A,
IR transcoder, I/O, DTMF generator, and
various tuning circuits) that communicate serially over a two-wire bus, serial data (SDA)
and serial clock (SCl). The 12C structure is
optimized for hardware simplicity. Parallel
address and data buses inherent in conventional systems are replaced by a serial protocol that transmits both address and bidirectional data over a 2-line bus. This means that
interconnecting wires are reduced to a minimum; only Vee, ground and the two-wire bus
are required to link the controller(s) with the
peripherals or other controllers. This results in
reduced chip size, pin count, and interconnections. An 12C system is therefore smaller,
simpler, and cheaper to implement than its
parallel counterpart.
The data rate of the 12C bus makes it suited
for systems that do not require high speed.
An 12C controller is well suited for use in
systems such as television controllers, telephone sets, appliances, displays or applications involving human interface. Typically an
12C system might be used in a control function where digitally-controllable elements are
adjusted and monitored via a central processor.
The 12 C bus is an innovative hardware interface which provides the software designer
the flexibility to create a truly multi-master
environment. Built into the serial interface of
the controllers are status registers which
monitor all possible bus conditions: bus free/
busy, bus contention, slave acknowledgement, and bus interference. Thus an 12 C
system might include several controllers on
the same bus each with the ability to asynchronously communicate with peripherals or
each other. This provision also provides expandability for future add-on controllers. (The
12C system is also ideal for use in environments where the bus is subject to noise.
Distorted transmissions are immediately detected by the hardware and the information
presented to the software.) A slave acknowl-
February 1987
Application Note
edgement on every byte also facilitates data
integrity.
An 12C system can be as simple or sophisticated as the operating environment demands. Whether in a single master or multimaster system, noisy or 'safe', correct system operation can be insured under software
control.
CONTROLLERS
Currently the family of 12 C controllers include
the MAB8400, and the PCD 3343 (the
PCD3343 is basically a CMOS version of the
MAB8400). The MAB8400 is based on the
8048 architecture with the 12C interface builtin. The instruction set for the MAB8400 is
similar to the 8048, with a few instructions
added and a few deleted. Tables 1 and 2
summarize the differences.
Programs for the MAB8400 and PCD 3343
may be assembled on an 8048-assembler
using the macros listed in Appendix A. The
serial 110 instructions involve moving data to
and from the SO, SI, and S2 serial 110 control
registers. The block diagram of the 12C interface is shown in Figure 1.
SERIAL I/O INTERFACE
A block diagram of the Serial Input/Output
(SIO) is shown in Figure 1. The clock line of
the serial bus (SCl) has exclusive use of Pin
3, while the Serial Data (SDA) line shares Pin
2 with parallel 110 signal P23 of port 2.
Consequently, only three I/O lines are available for port 2 when the 12C interface is
enabled.
Communication between the microcomputer
and interface takes place via the internal bus
of the microcomputer and the Serial Interrupt
Request line. Four registers are used to store
data and information controlling the operation
of the interface:
• data shift register SO
• address register SO'
• status register S 1
• clock control register S2.
THE 12C BUS INTERFACE:
SERIAL CONTROL REGISTERS
SO, S1
All serial 12 C transfers occur between the
accumulator and register SO. The 12C hardware takes care of clocking outlin the data,
and receiving/generating an acknowledge. In
addition, the state of the 12C bus is controlled
and monitored via the bus control register SI.
A definition of the registers is as follows:
Data Shift Register SO - SO is the data shift
register used to perform the conversion between serial and parallel data format. All
transmissions or receptions take place
through register SO MSB first. All 12 C bus
receptions or transmissions involve moving
data tolfrom the accumulator from/to SO.
Table 1. MAB8400 Family Instructions not in the MAB8048 Instruction Set
SERIAL I/O
MOV A,Sn
MOV Sn,A
MOV Sn,#data
EN SI
DIS SI
REGISTER
CONTROL
DEC @Rr
DJNZ @Rr,addr
SEl MB2
SEl MB3
CONDITIONAL
BRANCH
JNTF addr
Table 2. MAB8048 Instructions not in the MAB8400 Family Instruction Set
DATA MOVES
FLAGS
MOVX A,@R
MOVX @R,A
MOVP3 A,@A
MOVD A,P
MPVD P,A
ANlD P,A
ORlO P,A
ClR
CPl
ClR
CPl
FO
FO
Fl
Fl
BRANCH
"JNI addr
JFO addr
JFl addr
"replaced by
JTO, JNTO
3-16
CONTROL
ENTOClK
Signetics Linear Products
Application Note
The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration
BIT 7
AN168
ADDRESS REGISTER
INTREQ
r
8400
INTERRUPT
LOGIC
ENSI
DISSI
WRSO
~~__L--~-?~~~__~--L~S--rRDSO
INITIALIZE
(Pin 11)
o
•
PIN
LRB
RESET
INTERNAL MICROCOMPUTER BUS
BIT7
MST TRX BB
RD S1
S1
I"----INTERNAL CLOCK
Figure 1. Block Diagram of the MAB8400 SIO Interface
Address Register SO' - In multi-master
systems, this register is loaded with a control·
ler's slave address. When activated,
(ALS = 0), the hardware will recognize when
it is being addressed by setting the AAS
(Addressed As Slave) flag. This provision
allows a master to be treated as a slave by
other masters on the bus.
'
Status Register S1 - S1 is the bus status
register. To control the SIO interface, infor·
mation is written to the register. The lower 4
bits in S1 serve dual purposes; when written
to, the control bits ESO, BC2, BC1, BCO are
programmed (Enable Serial Output and a 3·
bit counter which indicates the current num·
ber of bits left in a serial transfer). When
reading the lower four bits, we obtain the
February 1987
status information AL, AAS, ADO, LRB (Arbi·
tration Lost, Addressed As Slave, Address
Zero (the general call has been received), the
Last Received Bit (usually the acknowledge
bit». The upper 4 bits are the MST, TRX, BB,
and PIN control bits (Master, Transmitter, Bus
Busy, and Pending Interrupt Not). These bits
define what role the controller has at any
particular time. The values of the master and
transmitter bits define the controller as either
a master or slave (a master initiates a transfer
and generates the serial clock; a slave does
not), and as a transmitter or receiver. Bus
Busy keeps track of whether the bus is free or
not, and is set and reset by the 'Start' and
'Stop' conditions which will be defined. Pend·
ing Interrupt Not is reset after the completion
3-17
of a byte transfer + acknowledge, and can be
polled to indicate when a serial transfer has
been completed. An alternative to polling the
PIN bit is to enable the serial interrupt; upon
completion of a byte transfer, an interrupt will
vector program control to location 07H.
SERIAL CLOCKI ACKNOWLEDGE
CONTROL REGISTER S2
Register S2 contains the clock-control register and acknowledge mode bit. Bits
S20 - S24 program the bus clock speed. Bit
S26 programs the acknowledge or not-acknowledge mode (1/0). The various 12C bus
clock speed possibilities are shown in
Table 3.
•
Signetics Linear Products
Application Note
The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration
Table 3. Clock Pulse
Frequency Control
When Using a 4.43MHz Crystal
HEX
S20-S24
CODE
a
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18"
19"
1A"
1B"
1C
1D
1E
1F
APPROX.
DIVISOR
fCLOCK
(kHz)
Not Allowed
39
114
45
98
51
87
63
70
75
59
87
51
99
45
123
36
147
30
171
26
195
23
243
18
291
15
339
13
387
11
483
9.2
579
7.7
675
6.6
771
5.8
963
4.6
1155
3.8
1347
3.3
1539
2.9
1923
2.3
2307
1.9
2691
1.7
3075
1.4
3843
1.2
4611
1.0
5379
0.8
6147
0.7
AN168
The losing Master is now configured as a
slave which could be addressed during this
very same cycle. These provisions allow for a
number of microcomputers to exist on the
same bus. With properly written subroutines,
software for anyone of the controllers may
regard other masters as transparent.
12C PROTOCOL AND
ASSEMBLY LANGUAGE
EXAMPLES
12C data transfers follow a well-defined protocol. A transfer always takes place between a
master and a slave. Currently a microcomputer can be master or slave, while the 'CLIPS'
peripherals are always slaves. In a 'bus-free'
condition, both SCl and SDA lines are kept
logical high by external pull-up resistors. All
bus transfers are bounded by a 'Start' and a
'Stop' condition. A 'Start' condition is defined
as the SDA line making a high-to-Iow transition while the Sel line Is high. At this point,
the internal hardware on all slaves are activated and are prepared to clock-in the next 8
bits and interpret it as a 7-bit address and a
R/Vii control bit (MSB first). All slaves have an
internal address (most have 2 - 3 programmable address bits) which is then compared
with the received address. The slave that
recognized its address will respond by pulling
the data line low during a ninth clock generated by the master (all 12 C byte transfers
require the master to generate 8 clock pulses
plus a ninth acknowledge-related clock
pulse). The slave-acknowledge will be registered by the master as a '0' appearing in the
lRB (last Received Bit) position of the S1
serial 1/0 status register. If this bit is high
after a transfer attempt, this indicates that a
slave did not acknowledge, and that the
transfer should be repeated.
After the desired slave has acknowledged its
address, it is ready to either send or receive
data in response to the master's driving
clock. All other slaves have withdrawn from
the bus. In addition, for multi-master systems,
the start condition has set the' Bus Busy' bit
of the serial 110 register S1 on all masters on
the bus. This gives a software indication to
other masters that the bus is in use and to
wait until the bus is free before attempting an
access.
There are two types of 12 C peripherals that
now must be defined: there are those with
only a chip address such as the 1/0 expander, PCF8574, and those with a chip address
plus an internal address such as the static
RAM, PCF8570. Thus after sending a start
condition, address, and R/Vii bit, we must
take into account what type of slave is being
addressed. In the case of a slave with only a
chip address, we have already indicated its
address and data direction (R/Vii) and are
therefore ready to send or receive data. This
is performed by the master generating bursts
of 9 clock pulses for each byte that is sent or
received. The transaction for writing one byte
to a slave with a chip address only is shown in
Figure 3.
In this transfer, all bus activity is invoked by
writing the appropriate control byte to the
serial 110 control register S1, and by moving
data tolfrom the serial bus buffer register SO.
Coming from a known state (MOV S1,#18HSlave, Receiver, Bus not Busy) we first load
the serial 1/0 buffer SO with the desired
·only values that may bo used in the low speed mode
(ASC;1).
Vce
These speeds represent the frequency of the
serial clock bursts and do not reflect the
speed of the processor's main clock (i.e. it
controls the bus speed and has no effect on
the CPU's execution speed).
SCl
SoA
BUS. ARBITRATION
Due to the wire-AND configuration of the 12C
bus, and the self-synchronizing clock circuitry
of 12C masters, controllers with varying clock
speeds can access the bus without clock
contention. During arbitration, the resultant
clock on the bus will have a low period equal
to the longest of the low periods; the high
period will equal the shortest of the high
periods. Similarly, when two masters attempt
to drive the data line simultaneously, the data
is 'ANDed', the master generating a low while
the other is driving a high will win arbitration.
The resultant bus level will be low, and the
loser will withdraw from the bus and set its
'Arbitration lost' flag (S1 bit 3).
February 1987
MAB
8400
PCF
8574
RAM (128-BYTE)
I/O EXPANoOR
AooR" '40'H
Figure 2. Schematic for Assembly Examples
3-18
AooR" 'AO'H
Signetics Linear Products
Application Note
The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration
AN168
RD!WR
I
SDA
I
I'
I
I
I
~------ACKNOWLEDGE-----~
I
~~-----4r-
SCL
I
I
ADDRESS '40H'
I START
I CONDITION
I
I
I
I
I
I
I STOP
I CONDITION
I
I
I
1
MOV S1,#18H
MOV SO,#40H
MOV S1,#OF8H
CALL ACKWT:
MOV A,#2AH
MOV SO,A - - - - - - - '
CALL ACKWT:
MOV S1,#OD8H - - - - - - - '
;Initialize S1-Slave, Receiver, Bus not
;Busy, Enable Serial 1/0.
;Preload SO with Slave's address &
;RiW bit.
;Invoke start condition & slave address
;(Master, Transmitter, Bus Busy, Enable
;Serial 1/0, Bit Counter = 000).
;Check for transmission complete, ack.
;received, no arbitration, etc.
;Get a data byte.
;Transmit data byte.
;Wait for transmission complete again.
;Generate Stop condition
;(Master, Transmitter, Bus not Busy).
Figure 3
slave's address (MOV Sa,#40H). To transmit
this preceded by a start condition, we must
first examine the control register S1, which,
after initialization, looks like this:
MASBUS
TER TRANS BUSY
PIN
ESO
BC'
BC1
BCO
I1 Ia Ia Ia I
To transmit to a slave, the Master, Transmitter, Bus Busy, PIN (Pending Interrupt Not),
and ESO (Enable Serial Output) must be set
to a 1. This results in an 'F8H' being written to
S1. This word defines the controller as a
Master Transmitter, invokes the transfer by
setting the' Bus Busy' bit, clears the Pending
Interrupt Not (an inverted flag indicating the
completion of a complete byte transfer), and
activates the serial output logic by setting the
Enable Serial Output (ESO) bit.
BIT COUNTER S12, S11, S10
BC2, BC1, and BCO comprise a bit-counter
which indicates to the logic how long the
word is to be clocked out over the serial data
line. By setting this to a aaOH, we are telling it
February 1987
to produce 9 clocks (8 bits plus an acknowledge clock) for this transfer. The bit counter
will then count off each bit as it is transmitted.
The bit counter possibilities are shown in
Table 4.
Thus the bit counter keeps track of the
number of clock pulses remaining in a serial
transfer. Additionally, there is a not-acknowledge mode (controlled through bit 6 of clock
control register S2) which inhibits the acknowledge clock pulse, allowing the possibility of straight serial transfer. We may thus
define the word size for a serial transfer (by
pre loading BC2, BC1, BCa with the appropriate control number), with or without an acknowledge-related clock pulse being generated. This makes the controller able to transmit
serial data to most any serial device regardless of its protocol (e.g., C-bus devices).
CHECKING FOR SLAVE
ACKNOWLEDGE
After a 'Start' condition and address have
been issued, the selected slave will have
recognized and acknowledged its address by
Table 4_ Binary Numbers in Bit-Count Locations BC2, BC1 and BCQ
BC2
BC1
a
a
a
a
1
1
1
1
a
1
1
a
a
1
1
a
3-19
BCa
1
a
1
a
1
a
1
a
BITS/BYTE
WITHOUT ACK
BITS/BYTE
WITH ACK
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
•
Application Note
Signetics Linear Products
The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration
pulling the data line low during the ninth clock
pulse. During this period, the software (which
runs on the processor's 4MHz clock) will
have been either waiting for the transfer to be
completed by polling the PIN bit in S1 which
goes low on completion of a transfer/reception (whose length is defined by the preloaded Bit-counter value), or by the hardware
in Serial Interrupt mode. The serial interrupt
(vectored to 07H) is enabled via the EN SI
(enable serial interrupt) instruction.
At the point when PIN goes low (or the serial
interrupt is received) the 9-bit transfer has
been completed. The acknowledgement bit
will now be in the LRB position of register S1,
and may be checked in the routine' ACKWT'
(Wait for Acknowledge) as shown in Figure 4.
This routing must go one step further in multimaster systems; the possibility of an Arbitration Lost situation may occur if other masters
are present on the bus. This condition may be
detected by checking the 'AL' bit (bit 3). If
arbitration has been lost, provisions for reattempting the transmission should be taken.
If arbitration is lost, there is the possibility that
the controller is being addressed as a Slave.
If this condition is to be recognized, we must
test on the 'AAS' bit (bit 2). A 'General Call'
address (OOH) has also been defined as an
'all-call' address for all slaves; bit 1, ADO,
must be tested if this feature is to be recognized by a Master.
After a successful address transfer/acknowledge, the slave is ready to be sent its data.
The instruction MOV SO,A will now automatically send the contents of the accumulator
out on the bus. After calling the ACKWT
routine once more, we are ready to terminate
the transfer. The Stop condition is created by
the instruction 'MOV S1, #ODBH'. This resets the bus-busy bit, which tells the hardware to generate a Stop - the data line
makes a low-to-high transition while the clock
remains high. All bus-busy flags on other
masters on the bus are reset by this signal.
The transfer is now complete - PCFB574
I/O Expandor will transfer the serial data
stream to its B output pins and latch them
until further update.
February 19B 7
ACKWT:
AN168
;Get bus status word
;from SI.
;Poll the PIN bit
;until it goes low
;indicating transfer
;completed
;Jump to BUSERR
;routine if acknowledge
;not received.
;transfer complete,
;acknowledge received - return.
MOV A,S1
JB4 ACKWT
JBO BUSERR
RET
Figure 4
MASTER READS ONE BYTE
FROM SLAVE
A read operation is a similar process; the
address, however, will be 41 H, the LSB
indicating to the I/O device that a read is to
be performed. During the data portion of a
read, the 110 port B574 will transmit the
contents of its latches in response to the
clock generated by the master. The Master/
Receiver in this case generates a low-level
acknowledge on reception of each byte (a
'positive' acknowledge). Upon completion of
a read, the master must generate a 'negative'
acknowledge during the ninth clock to indicate to the slaves that the read operation is
finished. This is necessary because an arbitrary number of bytes may be read within the
same transfer. A negative acknowledge consists of a high signal on the data line during
the ninth clock of the last byte to be read. To
accomplish this, the master B400 must leave
the acknowledge mode just before the final
byte, read the final byte (producing only B
clock pulses), program the bit-counter with
001 (preparing for a one-bit negative acknowledge pulse), and simply move the contents of SO to the accumulator. This final
instruction accomplishes two things simultaneously: it transfers the final byte to the
accumulator and produces one clock pulse
on the SCL line. The structure of the serial
110 register SO is such that a read from it
causes a double-buffered transfer from the
12 C bus to SO, while the original contents of
SO are transferred to the accumulator. Because the number of clocks produced on the
bus is determined by the control number in
the Bit Counter, by presetting it to 001, only
3-20
one clock is generated. At this point in time
the slave is still waiting for an acknowledge;
the bus is high due to the pull-up, as single
clock pulse in this condition is interpreted as
a 'negative' acknowledge. The slave has now
been informed that reading is completed; a
Stop condition is now generated as before.
The read process (one byte from a slave with
only a chip address) is shown in Figure 5.
Signetics Linear Products
Application Note
The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration
AN168
RD
SDA
II
ACKNOWLEDGE
SCL
I START
I CONDITION
I STOP
I CONDITION
I
I
I
MOV S1.#18H
MOV SO.#41H
MOV S1.#OF8H
CALL ACKWT
WAIT:
MOV S2.#01H
MOV SO.A--.....J
MOV A.S1
JB4 Wait
MOV S1.#OA9H
MOV A.SO - - - - - '
MOV S1.#OD8H
;Initialize serial 1/0 control
;register.
;Preload serial register SO
;with slave address and RD
;control bit.
;Send address to bus along with
;start condition.
:Wait for acknowledge (as
;before).
;Leave acknowledge mode.
;Read data from slave to SO.
;Test for byte received by
;testing S1 PIN bit.
;Wait until PIN received.
;Set Bit Counter to 1 and
;become a receiver (A9 =
;Mst.Rec.Bus Busy.Bit Coutner =
;001).
;Move data to accumulator and
;clock out a negative
;acknowledge.
;Generate Stop Condition.
Figure 5
February 1987
3-21
Application Note
Signetics Linear Products
The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration
AN168
COMMUNICATION WITH PERIPHERAL REQUIREO
MOVS1,#18H
MOV SO, #OAOH
MOV 51, #OF8H
CALL ACKWT
MOVA,#OOH
MOVSO,A
CALL ACKWT
MOV S1,#18H
MOVA,#OA1H
MOV SO,A
MOV S1,#OF8H
CALL ACKWT
MOV A,SO
CALL ACKWT
MOVA,SO
CALL ACKWT
MOV RO,A
MOVA,SO
CALL ACKWT
MOV R1,A
MOV S2,#01H
MOVA,SO
WAIT1:
MOV R2,A
MOVA,SI
JB4 WAITI
MOV SI,#OD8H
MOV S2,#41H
Figure 6, Flowchart for Reading/Writing One Byte to an 12C
Peripheral; Single-Master, Single-Address Slave
These examples apply to a slave with a chip
address - more than one byte can be written/read within the same transfer; however,
this option is more applicable to 12 C devices
with sub-addresses such as the static RAMs
or Clock/Calendar. In the case of these types
of devices, a slightly different protocol is
used. The RAM, for example, requires a chip
address and an internal memory location
before it can deliver or accept a byte of
information. During a write operation, this is
February 1987
;Initialize bus-status register
;Master, Transmitter,
;Bus-not-Busy, Enable SIO.
;Load SO with RAM's chip
;address.
;Start condo and transmit
;address.
;Wait until address received.
;Set up for transmitting RAM
;Iocation address.
;Transmit first RAM address.
;Wait.
;Set up for a repeated Start
;condition.
;Get RAM chip address & RD bit.
;Send out to bus
;preceded by repeated Start.
;Wait.
;First data byte to SO.
;Wait.
;Second data byte to SO.
;And First data byte to Acc.
;Wait.
;Save first byte in RO.
;Third data byte to SO
;and second data byte to Acc.
;Wait.
;Save second data byte
;in R1.
;Leave ack. mode.
;Bit Counter=OOI for neg ack.
;Third data byte to acc
;negative ack. generated.
;Save third data byte in R2.
;Get bus status.
;Wait until transfer complete.
;Stop condition.
;Restore acknowledge mode.
Figure 7
done by simply writing the secondary address
right after the chip address - the peripheral
is designed to interpret the second byte as an
internal address. In the case of a Read
operation, the slave peripheral must send
data back to the Master after it has been
addressed and sub-addressed. To accomplish this, first the Start, Address, and Subaddress is transmitted. Then we have a
repeated start condition to reverse the direc·
tion of the data transfer, followed by the chip
3-22
address and RD, then a data string (w/
acknowledges). This repeated Start does not
affect other peripherals - they have been
deactivated and will not reactivate until a
Stop condition is detected. 12 C peripherals
are equipped with auto·incrementing logic
which will automatically transmit or receive
data in consecutive (increasing) locations.
For example, to read 3 consecutive bytes to
PCB8571 RAM locations 00, 01 and 02, we
use the following format as shown in Figure 7.
Signetics Linear Products
Application Note
The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration
This routine reads the contents of location 00,
01 and 02 of the PCBB571 12B-byte RAM and
puts them in registers RO, R1, and R2. The
auto-incrementing feature allows the programmer to Indicate only a starting location,
then read an arbitrary block of consecutive
memory addresses. The WAIT 1 loop is
required to poll for the completion of the final
byte because the ACKWT routine will not
recognize the negative acknowledge as a
valid condition.
February 1987
BUS ERROR CONDITIONS:
ACKNOWLEDGE NOT RECEIVED
In the above routines, should a slave fail to
acknowledge, the condition is detected during the 'ACKWT' routine. The occurrence
may indicate one of two conditions: the slave
has failed to operate, or a bus disturbance
has occurred. The software response to either event is dependent on the system application. In either case, the 'BusErr' routine
should reinitialize the bus by issuing a 'Stop'
condition. Provision may then be taken to
3·23
AN168
repeat the transfer an arbitrary number of
times. Should the symptom persist, either an
error condition will be entered, or a backup
device can be activated.
These sample routines represent single-master systems. A more detailed analysis of multimaster/noisy environment systems will be
treated in further application notes. Examples
of more complex systems can be found in the
'Software Examples' manual; publication
939B 615 70011.
•
Signetics Linear Products
Application Note
The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration
APPENDIX A
Only the 8048 assembler is capable of assembling MAB8400 source code when it has
at least a "DATA" or "Define Byte" assembler directive, possibly in combination with a
MACRO facility.
AN168
The new instructions can be simply defined
by MACROs. The instructions which are not
in the MAB8400 should not be in the
MAB8400 source program.
An example of a macro definitions list is given
here for the Intel Macro Assembler.
This list can be copied in front of a MAB8400
source program; the new instructions are
added to the MAB8400 source program by
calling the MACRO via its name in the opcode field and (if required) followed by an
operand in the operand field.
MACRO DEFINITIONS
LINE
SOURCE STATEMENT
1 $MACROFILE
2 ;MACROS FOR 8048 ASSEMBLER RECOGNITION
3 ;OF 8400 COMMANDS
4
MOVSOA
5
DB 3CH
6
ENDM
MOVASO
7
8
DB OCH
9
ENDM
10
MOVS1A
11
DB 3DH
12
ENDM
13
MOVAS1
14
DB ODH
15
ENDM
16
MOVS2A
17
DB 3EH
18
ENDM
19
MOVSO
20
DB 9CH,L
21
ENDM
22
MOVS1
23
DB 9DH,L
24
ENDM
25
MOVS2
26
DB 9EH,L
27
ENDM
2B
ENSI
29
DB 85H
30
ENDM
31
DISSI
32
33
34;
35; PORT 0 INSTRUCTIONS:
36;
37
38
39;
40
41
42
43;
44
45
46
47;
48
49
50
51;
February 1987
MACRO
;MOV SO,A
MACRO
;MOV A,SO
MACRO
;MOV S1,A
MACRO
;MOV A,Sl
MACRO
;MOV S2,A
MACRO L
;MOV SO,#DATA
MACRO L
;MOV Sl,#DATA
MACRO L
;MOV S2,#DATA
MACRO
;EN SI
MACRO
;DIS SI (Disable serial
interrupt)
DB
ENDM
95H
INAPO
DB
ENDM
MACRO
OBH
;IN A,PO
OUTPOA
DB
ENDM
MACRO
38H
;OUTL PO,A
ORLPO
DB
ENDM
MACRO L
88H,L
;ORL PO,#DATA
ANLPO
DB
ENDM
MACRO L
98H,L
;ANL PO,#DATA
3-24
Signetics Linear Products
Application Note
The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration
AN168
MACRO DEFINITIONS (Continued)
LINE
SOURCE STATEMENT
52; DATA MEMORY INSTRUCTIONS:
53
DECARO
DB
ENDM
MACRO
OCOH
;DEC @RO
DECAR1
DB
ENDM
MACRO
OC1H
;DEC @R1
SELMB2
DB
ENDM
MACRO
OA5H
;SEL MB2
SELMB3
DB
ENDM
MACRO
OB5H
;SEL MB3
DJNZAO
DB
EN OM
MACRO L
;DJNZ @RO,ADDR
OEOH,L AND OFFH
MACRO L
;DJNZ @R1,ADDR
OE1H,L AND OFFH
77
DJNZA1
DB
ENOM
78;
79
JNTF
MACRO L
DB
EN OM
06H,L AND OFFH
54
55
56;
57
58
59
60;
61; SELECT MEMORY BANK INSTRUCTIONS:
62
63
64
65;
66
67
68
69;
70; CONDITIONAL JUMP INSTRUCTIONS:
71
72
73
74;
75
76
80
81
82
83; END OF MACRO DEFINITIONS
February 1987
3·25
;JUMP IF TIMERFLAG IS
NON ZERO
•
Signetics linear Products
Application Note
The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration
AN168
THE 8400 INSTRUCTIONS BUILT FROM THE MACRO LIST
LOC/OBJ
LINE
0000
OOOOOC
0001 00
00023C
0003 3D
0004 3E
0005 9C
0006 56
0007 90
0008 9F
0009 9E
OOOA E8
OOOB 85
OOOC 95
000008
OOOE 38
OOOF 88
0010 5A
0011 98
0012 2F
0013 CO
0014 C1
0015 A5
0016 B5
0017 EO
SOURCE STATEMENT
2
3+
4
5+
6
7+
8
9+
10
11 +
12
ORG 0
MOVASO
DB
MOVAS1
DB
MOVSOA
DB
MOVS1A
DB
MOVS2A
DB
MOVSO
13 +
DB
9CH,56H
14
MOVS1
9FH
15 +
DB
9DH,9FH
16
MOVS2
OE8H
17 +
DB
9EH,OE8H
18
19 +
20
21 +
22
23+
24
25+
26
27+
ENS1
DB
DISSI
DB
INAPO
DB
OUTPOA
DB
ORLPO
DB
28
29+
ANLPO
DB
30
31 +
32
33 +
34
35+
36
37+
38
DECARO
DB
DECAR1
DB
SELMB2
DB
SELMB3
DB
OJ NZAO
39+
DB
OEOH,567H AND
OFFH
40
DJNZA1
OEFEH
41 +
DB
OE1 H,OEFEH AND
OFFH
42
43 +
JNTF
DB
789H
06H, 789H AND
OFFH
44
END
;MACRO for MOV A,SO
OCH
;MACRO for MOV A,S1
ODH
;MACRO for MOV SO,A
3CH
;MACRO For MOV S1,A
3DH
;MACRO For MOV S2,A
3EH
56H
;MACRO For MOV SO,
#56H
;MACRO for MOV S1,
#9FH
;MACRO for MOV S2,
#OE8H
;MACRO for EN S1
85H
;MACRO for DIS SI
95H
;MACRO for IN A,PO
08H
;MACRO for OUTL PO,A
38H
5AH
88H,5AH
2FH
98H,2FH
;MACRO for ORL PO,A
;MACRO for ANL PO,A
;MACRO for DEC @RO
OCOH
;MACRO for DEC @R1
OC1H
;MACRO for SEL MB2
OA5H
;MACRO for SEL MB3
OB5H
567H
;MACRO for DJNZ @RO,
567H
0019 67
0019 E1
;MACRO for DJNZ @R1,
OEFEH
001A FE
001B 06
001C 89
February 1987
3-26
;MACRO for JNTF 789H
Signetics
Section 4
Tuning Systems
Linear Products
•
INDEX
TUNER CONTROL PERIPHERALS
PCF8570
256 X 8 Static RAM............................. ..............................
PCF8571
lk Serial RAM...................................................................
PCF8573
Clock/Calendar With Serial I/O.............................................
PCF8574
B-Bit Remote I/O Expander .......................... ............ ...... ......
PCF8582
12C CMOS EEPROM (256 X 8) .......................... .......... .........
SAB3013
Hex 6-Bit O/A Converter .....................................................
TUNING CIRCUITS
SAB3035
FLL Tuning and Control Circuit (Eight 0/ A Converters) ..............
AN157
Microcomputer Peripheral IC Tunes and Controls a TV Set
(SAB3035) (TPOg7).............................................................
SAB3036
FLL Tuning and Control Circuit .............................................
SAB3037
FLL Tuning and Control Circuit (Four 0/ A Converters)...............
TDA8400
FLL Tuning Circuit With Prescaler..........................................
PRESCALERS
SAB1164/65
SAB1256
1GHz Oivide-by-64 Prescaier.................................................
1GHz Oivide-by-256 Prescaler...............................................
4-3
4-12
4-21
4-33
4-41
4-45
4-50
4-61
4-65
4-75
4-86
4-92
4-97
TUNER IC (MONOLITHIC)
TDA5030A
VHF Mixer-Oscillator Circuit (VHF Tuner IC) ............................. 4-102
TDA5230
VHF, Hyperband, and UHF Mixer-Oscillator With IF Amp ............ 4-106
PCF8570
Signetics
256 X 8 Static RAM
Product Specification
Linear Products
DESCRIPTION
FEATURES
• Operating supply voltage: 2.5V to
The PCF8570 is a low power 2048-bit
static CMOS RAM organized as 256
words by 8-bits. Addresses and data are
transferred serially via a two-line bidirectional bus (12C). The built-in word address register is incremented automatically after each written or read data byte.
Three address pins - AO, A 1, and A2 are used for programming the hardware
address, allowing the use of up to eight
devices connected to the bus without
additional hardware.
PIN CONFIGURATION
N, D Packages
6V
• Low data retention voltage: min.
1.0V
• Low standby current: max. 5/lA
• Power saving mode: typo 50nA
• Serial input/output bus (1 2C)
• Address by 3 hardware address
pins
• Automatic word address
incrementing
• 8·lead DIP package
APPLICATIONS
• Telephony RAM expansion for
stored numbers in repertory
dialing (e.g., PCD3343
applications)
• Radio and television channel
presets
• Video cassette recorder
• General purpose RAM expansion
for the microcomputer families
MAB8400 and PCF84COO
:0'::r
A23
Vss
8SCL
4
5 SDA
lOPYIEW
~~
SYMBOL
~
J
DESCRIPTION
Address inputs
Vss
Negative supply
SOA
Serial data line
SCL
TEST
Voo
}12C b S
Serial clock line
U
Test Input for test speed-up; must
be connected to Vss when not in
use. (Power saving mode, see
Figures 12 and 13)
Positive supply
ORDERING INFORMATION
TEMPERATURE RANGE
ORDER CODE
B·Pin PlastiC DIP (SOT·97A)
DESCRIPTION
-40·C to + 85·C
PCFB570PN
B-Pin Plastic SO (SO-Bl; SOT·176)
-40·C to + B5·C
PCFB570TD
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
Voo
Supply voltage range (Pin B)
-O.B to +8.0
V
VI
Voltage range on any input
-O.B to Voo +O.B
V
±II
DC input current (any input)
10
mA
±Io
DC output current (any output)
10
mA
±Ioo; Iss
Supply current (Pin 4 or Pin B)
50
mA
I',-OT
Power dissipation per package
300
mW
Po
Power diSSipation per output
50
mW
TSTG
Storage temperature range
-65 to +150
·C
TA
Operating ambient temperature range
-40 to +B5
·C
December 2, 19B6
4-3
853-1051 B6702
•
Signetics Uneer Products
Product Specification
PCF8570
256 X 8 Static RAM
BLOCK DIAGRAM
AIJ~-+--------
__---,
M~~----------,
~o-~----------------,
VDD
o-~-----I
vsso-:+--,
TESf
SOO7_
DC ELECTRICAL C.HARACTERISTICS Voo = 2.5 to 6V; vss = OV; TA = -40·C to + 65·C, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
TyP
Max
Supply
Voo
Supply voltage
100
1000
1000
Supply current at fSCl = 100kHz; V,
operating
standby
standby at T A = -25 to + 70·C
VPOR
Power-on reset voltage level I
2.5
= Vss
·6
V
200
15
5
p.A
p.A
p.A
2.3
V
V
or Voo
1.5
1.9
Input SeL; Input/output SDA
V,l
Input voltage LOW2
-0.8
0.3 X Voo
V,H
Input voltage HIGH2
0.7 X Voo
Voo+ 0.8
10l
Output current LOW at VOL a O.4V
3
V
rnA
10H
Output leakage current HIGH at VOH = Voo
250
±I,
Input leakage current (AO, Al, A2) at V, = Voo or Vss
250
nA
fSCl
Clock frequency (Figure 5)
100
kHz
7
pF
100
ns
C,
Input capacitance (SCL, SDA) at V, = VSS
tsw
Tolerable spike width on bus
0
nA
LOW Voo data retention
VOOR
Supply voltage for data retention
6
V
100R
Supply current at VOOR = 1V
1
5
p.A
100R
Supply current at VOOR = 1V; T A = -25 to + 70·C
2
p.A
400
nA
Power saving mode
100R
Supply current at TA = 25·C; TEST = VOOR
50
NOTES:
1. The power-on resm circuit resms the 120 bus logic when Vee < VPOR.
2.11 the Input voltages are a diode voltage above or below the supply voltage Vee or Vss an input current will flow; this currenl musl nol exceed ± O.SmA.
December 2, 1986
4-4
Signetics Unear Products
Product Specification
PCF8570
256 X 8 Static RAM
CHARACTERISTICS OF THE 12C
BUS
The 12C bus is for 2-way, 2-line communication between different ICs or modules. The
two lines are a serial data line (SDA) and a
SDA
serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up
resistor when connected to the output stages
of a device. Data transfer may be initiated
only when the bus is not busy.
Bit Transfer
One data bit is transferred during each clock
pulse. The data on the SDA line must remain
stable during the HIGH period of the clock
pulse, as changes in the data line at this time
will be interpreted as control signals .
•
--I./--:--.,.......JX,,---'O------t:~~_~
~
SCL
I CHANGE I
DATAUNE
srABLE:
DATAVAUD
I
OFDATA
I
I ALLOWED I
Figure 1_ Bit Transfer
Start and Stop Conditions
Both data and clock lines remain HIGH when
the bus is not busy. A HIGH-to-LOW transi-
~-,
I
I
SDA"'"
seL
--':1
I
I
I
I
I
I
I
I
I
I
s
I
L_.J
tion of the data line while the clock is HIGH is
defined as the start condition (S). A LOW-toHIGH transition of the data line while the
(P).
I
I
I-- SDA
r~
\
::
'----I
clock is HIGH is defined as the stop condition
11
\
I
I
I
I
I
I
I
I
I
p
I
I
1:!-SCL
L_.J
srART CONDmON
STOPCONDmON
Figure 2_ Definition of Start and Stop Conditions
System Configuration
A device generating a message is a "transmitter"; a device receiving a message is the
"receiver". The device that controls the message is the "master" and the devices which
are controlled by the master are the
"slaves".
SDA-----4~--------~--------~--------~--------~--
SCL--~--+-----~~~------1-~~-----+--+-----~~-+---
Figure 3_ System Configuration
December 2, 1986
4-5
Signetics Linear Products
Product Specification
256 X 8 Static RAM
PCF8570
Acknowledge
The number of data bytes transferred between the start and stop conditions from
transmitter to receiver is not limited. Each
byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level
put on the bus by the transmitter whereas the
master generates an extra acknowledge re-
lated clock pulse. A slave receiver which is
addressed must generate an acknowledge
after the reception of each byte. Also a
master must generate an acknowledge after
the reception of each byte that has been
clocked out. of the slave transmitter. The
device that acknowledges has to pull down
the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW.
During the HIGH period of the acknowledge
related clock pulse, setup and hold times
must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the
last byte that has been clocked out of the
slave. In this event the transmitter must leave
the data line HIGH to enable the master to
generate a stop condition.
ClOCK PULSE FOR
ACKNOWLEDGEMENT
START
CONDmON
I
SCLFROM
MASTER
I
I
I
DATA OUTPUT
SYTRANsMmER
'"""'IL
/ _ _.JX" - _ _ _>C.~
l'.......I.:.....
.....A
/
s
DATA OUTPUT
SYRECEIVER
Figure 4. Acknowledge on the 12 C Bus
Timing Specifications
Within the 12C bus specifications a highspeed mode and a low-speed mode are
defined. The device operates in both modes
and the timing requirements are as follows:
SOA
High-Speed Mode
Masters generate a bus clock with a maximum frequency of 100kHz. Detailed timing is
shown in Figure 5.
seL
SOA
Where:
taUF
tHO;
ISTA
lLOWSmin
tHtGHmin
tsu;
leo;
tSTA
tOAT
t~tLOWmin
t ~tHIGHmin
4.7115
4/lS
t~tLOWmin
t ...
OJ,l.S
The minimum time the bus must be free before a new transmission can start
Start condition hold time
Clock LOW period
Clock HIGH period
Start condition set-up time; only valid for repeated start code
Data hold time
t ~ 250n5
Data satup lime
tR
t~1J1S
tF
t ~300ns
l~tLOWmln
Rise time of both the SOA and SCl line
Fall time of both the SDA and SCl line
Stop condition setup time
tSU:
tDAT
tsu;
tsTo
NOTE:
AU the timing values refer to VrH and V1L levels with a voltage swing of Vss to Voo.
Figure 5. Timing of the High-Speed Mode
December 2, 1986
4-6
Signetics Linear Products
Product Specification
256 X 8 Static RAM
SDA
PCF8570
'
V ---LOL--J:3:I\L--~
... __ 1,
__
__ J:
__
t __
~
-.-
J
----- -- ------- --
START ADDRESS
-.....RIW
ACK
ACK
DATA
CONDITION
-..-..--.....-START ADDRESS
RIW
ACK
STOP
CONDITION
Where:
Clock IlOWm1n
\;IGHmln
4.7JlS
4JLS
The dashed line is the acknowledgement of the receiver
Mark-la-space ratio
1:1 (LOW-la-HIGH)
Maximum number of bytes
Unrestricted
Premature termination of transfer
Allowed by generation of STOP condition
Acknowledge clock bit
Must be provided by the master
Figure 6. Complete Data Transfer In the High-Speed Mode
Low-Speed Mode
Masters generate a bus clock with a maximum frequency of 2kHz; a minimum LOW
period of 1051'S and a minimum HIGH period
of 3651's. The mark-to-space ratio is 1:3
LOW-to-HIGH. Detailed timing is shown in
Figure 7.
SDA
IF
SCL
I----IHIOHI----I
SDA
Where:
laUF
tHO, tSTA
tLOW
tHIGH
tsu,
ISlA
tHO, tOAT
t ~ 105/.1S (tLOWmin)
t ~ 365ps (tHIGHrnin)
130 IJS± 25IJs
390 /.IS± 25IJs
1301JS± 25ps·
t;> 01'5
tsu. tOAT
t~250ns
IF
t~ 1/.1S
t ~ 300ns
130ps± 25ps
...
tsu. tSTO
NOTES:
All the timing values refer to VIH and Vil levels with a voltage swing of Vss to Voo_
For definitions see high-speed mode.
"Only valid for repeated start code.
Figure 7. Timing of the Low-Speed Mode
December 2. 1986
4-7
•
Signetics Linear Products
Product Specification
256 X 8 Static RAM
PCF8570
\r
--\J\l\J
SCL-v-\j-START
CON DIllON
START BYTE
DUMMY
REPEATED
START
ACKNOWLEDGE
CONDmON
ADDRESS
Where:
Clock tlOWmfn
1301lS± 251-18
tHIGHmin
390"". 25""
Mark-ta-space ratio
Start byte
Maximum number of bytes
Premature termination of transfer
Acknowledge clock bit
1:3 (LOW-Io-HIGH)
0000 0001
6
Not allowed
Must be provided by master
Figure 8. Complete Data Transfer In Low-Speed Mode
December 2, 1986
4-8
ACKNOWLEDGE
STOP
CONDITION
Signetics linear Products
Product Specification
256 X 8 Static RAM
PCF8570
Bus Protocol
Before any data is transmitted on the 12C bus,
the device which should respond is ad-
dressed first. The addressing is always done
with the first byte transmitted alter the start
procedure. The 12C bus configuration for dif-
ACKNOWLEDGE
FROM SLAVE
S
SLAVE ADDRESS
ferent PCFB570 READ and WRITE cycles is
shown in Figure 9.
ACKNOWLEDGE
FROM SLAVE
WORD ADDRESS
RIW
A
ACKNOWLEDGE
FROM SLAVE
•
OATA
~NBVTES
AUTO INCREMENT
MEMORY WORD ADDRESS
a. Master Transmits to Slave Receiver (WRITE Mode)
ACKNOWLEDGE
FROM SLAVE
SLAVE ADDRESS
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
WORD ADDRESS
RIW
ACKNOWLEDGE
FROM MASTER
OATA
SLAVE ADDRESS
RIW
AT THIS MOMENT MASTER
TRANSMITTER BECOMES
MASTER RECEIVER AND !-------'
PCF8583 SLAVE RECEIVER
BECOMES SLAVE TRANSMITTER
NBYlES
AUTO INCREMENT
WORD ADDRESS
NO ACKNOWLEDGE
FROM MASTER
I
AUTO INCREMENT
WORD ADDRESS
b. Master Reads After Setting Word Address (WRITE Word Address; READ Data)
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROMMASrER
NO ACKNOWLEDGE
FROM MASTER
I
S
SLAVE ADDRESS
1
I
RIW
A
DATA
~NBVTES
AUTO INCREMENT
WORD ADDRESS
AJJfO INCREMENT
WORD ADDRESS
c. Master Reads Slave Immediately After First Byte (READ Mode)
Figure 9
December 2, 19B6
4-9
Signetics Unear Products
Product Specification
PCF8570
256 X 8 Static RAM
APPLICATION INFORMATION
The PCF8570 slave address has a fixed
combination 1010 as group 1, while group 2 is
fully programmable (see Figure 10.)
NOTE:
PCF8570A version:
~
slave address AO state is X (don't care); however. the hardware address AO Input must stili be connected to Vss or VOO.
Figure 10. PCF8570 Address
VDD
'MASrER
SCL TRANSMnTER
VDD
Al
0
A2
.".
PCF8570
SCL
'010'
TEST
.".
.".
VDD
AD
VDD
"c.:::"
SCL t--t--i
UP 10 8 PCF8570
WITHOUT ADDmoNAL
HARDWARE
Al
A2 TEST
10VDD
AD
VDD
SCL
Al
PC':
A2 TEST
t--t--+
R
R
R: PUU,UP RESISlOR
....+ ___~
R~ 1• .,le
ClUB
SDA SCL
(J2cBU$)
NOTE:
AD, A1, and J.:J. Inputs must be connected to Voo or Vss but not left open.
Figure, 11. PCF8570 Application Diagram
December 2, 1986
4-10
Product Specification
Signetics Linear Products
256 X 8 Static RAM
PCF8570
POWER SAVING MODE
With the condition TEST = VDDR, the
PCF8570 goes into the power saving mode.
!------POWERSAVINGMODE-----!OPERAnNG MODE
--~====~eOR
. r - _.....- _ VOO
=~~::l!fI::::= ~60R
. . - _.....--VOO
=~=::l~::::= ~60R
,.-----VOO
___~=========-----'
~60R
,.-----100
'-----------------'
loos
Figure 12. Timing for Power Saving Mode
+5V
r.:I\
'CI
~I
B
MICROCOMPUTER
5
t-
B
t7
t----
SDA
VOO
A2
SCL
TESr
PCDB571
A1
AO
3
I-2
1
Vss
~4
-=
NOTE!
1. In the operating mode, TEST'" O.
2. In the power saving mode, TEST
>=
VODR'
Figure 13. Application Example for Power Saving Mode
December 2, 1986
4-11
-:i- (Nled)
~e"
J
•
PCF8571
Signetics
1K Serial RAM
Product Specification
Linear Products
PIN CONFIGURATION
DESCRIPTION
FEATURES
The PCF8571 is a low power 1024-bit
static CMOS RAM organized as 128
words by 8 bits. Addresses and data are
transferred serially via a two-line bidirectional bus (12C). The built-in word address register is incremented automatically after each written or read data byte.
Three address pins - AO, A 1, and A2 are used for programming the hardware
address, allowing the use of up to eight
devices connected to the bus without
additional hardware.
• Operating supply voltage:
2.5V to 6V
• Low data retention voltage:
mln.1.0V
• Low standby current:
max.5iJA
• Power saving mode:
typ.50nA
• Serial input/output bus (1 2C)
• Address by 3 hardware address
pins
• Automatic word address
incrementing
• 8-lead DIP package
M0
N, D Packages
8V
A2 3
Vss
4
SCL
5 SDA
TOP VIEW
~~.
SYMBOL
AO
Al
J
DESCRIPTION
Address inputs
A2
vss
SDA
seL
TEST
APPLICATIONS
Voo
• Telephony
RAM expansion for stored
numbers in repertory dialing
(e.g., PCD3340 applications)
DD
7 TEST
Al 2
Negative supply
Ser!al data li~e
]r2c bus
Senal clock line
Test input for test speed-up; must
be connected to Vss when not in
use. (Power saving mode, see
Figures 12 and 13)
Positive supply
• Radio and television
channel presets
• Video cassette recorder
• General purpose
RAM expansion for the
micro-computer families MAB8400
and PCF84COO
ORDERING INFORMATION
TEMPERATURE RANGE
ORDER CODE
8·Pin Plastic DIP (SOT·97A)
DESCRIPTION
-25·C to + 70·C
PCF8571PN
8·Pin Plastic SO (VSO·8; SOT·176)
-25·C to + 70·C
PCF8571TD
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
UNIT
Voo
Supply voltage range (Pin 8)
PARAMETER
-0.8 to +8.0
V
VI
Voltage range on any input
-0.8 to Voo +0.8
V
±II
DC input current (any input)
10
mA
mA
±Io
DC output current (any output)
10
± 100; Iss
Supply current (Pin 4 or Pin 8)
50
mA
300
mW
PTOT
Power dissipation per package
Po
Power dissipation per output
50
mW
TSTG
Storage temperature range
-65 to + 150
·C
TA
Operating ambient temperature range
-25 to +70
·C
December 2, 1986
4-12
853·1036 86701
Signetics Linear Products
Product Specification
1K Serial RAM
PCF8571
BLOCK DIAGRAM
•
Mo-~---------------------,
Mo-~--------------------,
~o--r----------------.
SCLo--i------~~
SDAo-~----r_~1L~~~
0--=-1---------1
Vss o--o-t-----,
V DD
TEST
DC ELECTRICAL CHARACTERISTICS
voo = 2.5 to 6V; Vss = OV; T A = -25'C to + 70'C, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
Supply
Vao
Supply voltage
100
1000
Supply current at fSCL
operating
standby
VPOA
Power-on reset voltage level at VSCL = VSOA = Voo 1
2.5
= 100kHz;
6
V
200
5
p.A
p.A
2.3
V
VI = Vss or Voo
1.5
1.9
Input SCL; Input/output SDA
VIL
Input voltage lOW2
-0.8
0.3 X Voo
V
VIH
Input voltage HIGH 2
0.7 X Voo
Voo + 0.8
V
IOL
Output current lOW at VOL = O.4V
IOH
Output leakage current HIGH at VOH = Voo
100
±II
Input leakage current (AO, A1, A2) at VI = Voo or VSS
100
nA
fSCL
Clock frequency (Figure 5)
100
kHz
3
mA
0
CI
Input capacitance (SCl, SDA) at VI = Vss
tsw
Tolerable spike width on bus
nA
7
pF
100
ns
2
p.A
200
nA
LOW Voo data retention
VOOA
Supply voltage for data retention
100A
Supply current at VOOA
1
V
= 1V
Power saving mode (Figure 12)
loos
Supply current at TA = 25'C; TEST = AO
= A 1 = A2 = VOOA
50
NOTES:
1. The power-on reset circuit resets the 12C bus logic when Voo < VPOR.
2. If the input voltages are a diode voltage above or below the supply voltage Yoo or Vss an input current will flow: this current must not exceed ± O.SmA.
December 2, 1986
4-13
Signetics Linear Products
Product Specification
PCF8571
1K Serial RAM
CHARACTERISTICS OF
THE 12c BUS
The 120 bus is for 2-way, 2-line communication between different lOs or modules. The
two lines are a serial data line (SDA) and a
serial clock line (SOL). Both lines must be
connected to a positive supply via a pull-up
resistor when connected to the output stages
of a device. Data transfer may be initiated
only when the bus is not busy.
Bit Transfer
One data bit is transferred during each clock
pulse. The data on the SDA line must remain
stable during the HIGH period of the clock
pulse, as changes in the data line at this time
will be interpreted as control Signals.
S~-LI_~____~X~~~I__~_
SCL
~TAUNE
STABLE:
DATAVAUD
I
CHANGE
I
I OF~TA I
I ALLOWED I
Figure 1. Bit Transfer
Start and Stop Conditions
Both data and clock lines remain HIGH when
the bus is not busy. A HIGH-to-lOW transi-
tion of the data line while the clock is HIGH is
defined as the start condition (S). A lOW-toHIGH transition of the data line while the
clock is HIGH is defined as the stop condition
(P).
~--,
r-~
s~ -? I \'--!-I__-'-I____~: '" ____\...J...____+-J
11 I ~ s~
I
I
I
I
____~I_~I-~L---
I I I~
\'-__-If-
SCL
P
SCL
L_.J
START CONDmON
SlOP CONDITION
Figure 2. Definition of Start and Stop Conditions
System Configuration
A device generating a message is a "transmitter"; a device receiving a message is the
"receiver". The device that controls the message is the "master" and the devices which
are controlled by the master are the
"slaves".
~----~------~------~r-------~------~--
SCL--~~~----~--~----~--+-----~--+-----~--~--
Figure 3. System Configuration
December 2, 1986
4-14
Signetics Linear Products
Product Specification
1K Serial RAM
PCF8571
During the HIGH period of the acknowledge
related clock pulse, set-up and hold times
must be taken into account. A master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the
last byte that has been clocked out of the
slave. In this event the transmitter must leave
the data line HIGH to enable the master to
generate a stop condition.
lated clock pulse. A slave receiver which is
addressed must generate an acknowledge
after the reception of each byte. Also, a
master must generate an acknowledge after
the reception of each byte that has been
clocked out of the slave transmitter. The
device that acknowledges has to pull down
the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW.
Acknowledge
The number of data bytes transferred between the start and stop conditions from
transmitter to receiver is not limited. Each
byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level
put on the bus by the transmitter, whereas the
master generates an extra acknowledge re-
ClDCK PULSE FOR
ACKNOWLEDGEMENT
START
CONDITION
~
SCL FROM
MASTER
DATA OUTPUT
BYTRANSMIITER
,.L
--
I
I
I
~
1'.
8 \...../
X::X
/ r---\J
A. . . __......
9 "--
/
S
DATA OUTPUT
BYRECElVER
Figure 4. Acknowledgement on the 12C Bus
Timing Specifications
Within the 12C bus specifications a highspeed mode and a low-speed mode are
defined. The PCF8571 operates in both
modes and the timing requirements are as
follows:
High-Speed Mode
Masters generate a bus clock with a maximum frequency of 100kHz. Detailed timing is
shown in Figure 5.
SDA
SCL
SDA
Where:
tSUF
tHO. tSlA
t~tLOWmln
t;;;'tHIGHmin
4.7jJ.s
tLOWmin
tH1GHmin
tsu. tsTA
4""
t >tLOWrnin
tHO. IOAT
tsu. IOAT
t ;;'250n5
t>OjJ.S
IR
t<1pS
IF
t "'300ns
\SU. tS10
t>tLOWmin
The minimum time the bus must be free before a new transmission can start
Start condition hold time
Clock LOW period
Clock HIGH period
Start condition setup time; only valid for repeated start code
Data hold time
Data setup time
Rise time of both the SOA and sel line
Fall time of both the SOA and SCL line
Stop condition setup time
NOTE:
All the timing values refer to VIH and VIL levels with a voltage swing of Vss to Voo-
Figure 5. Timing of the High-Speed Mode
December 2, 1986
4-15
•
Product Specification
Signetics Linear Products
PCF8571
1K Serial RAM
SDA
'
V ---~--r:rT\L--~
... __ 1•
__
... __ .1:
__
\. __
..6
---
- - . - -..- --.-
START ADDRESS
RIW
ACK
~--~---
-
ACK
DATA
CONDITION
-.- - . . START
ADDRESS
-----RIW
ACK
-...STOP
CONDITION
Where:
Clock ILOWmJn
tHIGHmln
4.7~
4JtS
The dashed line is the acknowledgement of the receiver
Mark-la-space ratio
1:1 (LOW-la-HIGH)
Maximum number of bytes
Unrestricted
Premature termination of transfer
Allowed by generation of STOP condition
Acknowledge clock bit
Must be provided by the master
Figure 6. Complete Data Transfer In the High-Speed Mode
Low-Speed Mode
Masters generate a bus clock with a maximum frequency of 2kHz; a minimum LOW
period of 10511S and a minimum HIGH period
of 36511S. The mark-to-space ratio is 1:3
LOW-to-HIGH. Detailed timing is shown in
Figure 7.
SDA
SCL
1 - - - - IH1GH
-----!
SDA
Where:
leUF
tHO, ISTA
tLOW
tHIGH
tSTA
tsu,
tHO, loAT
tOAT
tsu.
'R
'tsu.
F tsTO
t
t
> 1051lS
(IWwmin)
> 365115 (tHJGHmin)
130.us ± 25",5
390l-fS ± 25ps
130llS ± 25ps*
• ;. OJ'S
t ~ 250n5
t .::::;; 1,u.s
t .::s;;; 300n5
130,us ± 25/lS
NOTES:
All the timing values refer to VIH and VIL levels with a voltage swing of Vss to VDD.
For definitions see high-speed mode.
*Only valid for repeated start code.
Figure 7. Timing of the Low-Speed Mode
December 2, 1986
4-16
Signetics Linear Products
Product Specification
1K Serial RAM
SDA \
SCL
PCF8571
\r
\...-._ _ _ _ -1I
-v-v--START BYTE
START
CONDITION
Where:
Clock tLOWmin
tHIGHmln
Mark-to-space ratio
Start byte
Maximum number of bytes
Premature termination of transfer
Acknowledge clock bit
--\.J\.J\.J
DUMMY
REPEATED
ACKNOWLEDGE
START
CONDITION
ADDRESS
130118 ± 25~
± 25115
:mojJ.S
1:3 (LOW-l0-HIGH)
0000 0001
6
Not allowed
Must be provided by master
Figure 8. Complete Data Transfer In the Low-Speed Mode
December 2, 1986
4-17
ACKNOWLEDGE
STOP
CONDITION
•
Signetlcs Linear Products
Product Specification
PCF8571
1K Serial RAM
Bus Protocol
Before any data is transmitted on the 12C bus,
the device which should respond is ad-
dressed first. The addressing is always done
with the first byte transmitted after the start
procedure. The 12C bus configuration for dif-
ferent PCF8571 READ and WRITE cycles is
shown in Figure 9.
I8
L -NBYTES
At1TO INCREMENT
MEMORY WORD ADDRESS
a. Master Transmits to Slave Receiver (WRITE mode)
ACKNOWLEDGE
FROM SlAVE
ACKNOWI.EIJ(lE
ACKNOWlEDGE
FROM SlAVE
FROMSLAYE
WORD ADDRESS
ACKNOWLEDGE
FROM MASTER
J
A
SLAve ADDRESS
R/Vi
AT
THIS MOMENT
MAS1'ER
TRANSMITTER
BECOMES
MASTER RecBVER AND
1
A
DATA
~
.. /W
N BYTES
AUTO INCREMENT
PCF 8S11 SLAVE RECEIVER
BECOMES SLAVE TRANSMITTER
WORD ADDRESS
,
NO ACKNOWLEDGE
FROM MASTER
b. Master Reads After Setting Word Address (WRITE Word Address; READ Data)
s
I
,
,
ACKNOWLEDGE
ACKNOWLEDGE
FROIISt,AVe
FROIiMASTER
AUTO INCREMENT
WORD ADDRESS
c. Master Reads Slave Immediately After First Byte (READ Mode)
NOTE:
X ... don't care bit
Figure 9
December 2, 1986
4-18
,
NO ACKNOWLEDGE
FROM MASTER
Signetics Linear Products
Product Specification
1K Serial RAM
PCF8571
APPLICATION INFORMATION
The PCF8571 slave address has a fixed
combination 1010 as group I, while group 2 is
fully programmable (see Figure 10),
•
1 0 l ' I 0 I A21 A1 I AO IR/wl
~GROUP1~GROUP2~
l'
Figure 10. PCF8571 Address
VDD
MASTER
SCL TRANSMITTER
AO
VOD
A1
P~s;.n
SCLi--l-i
A2 TEST
VDD
VDD
AO
A1
PCF8571
scLi--l-i
~1I10'
UPT08PCF8571
WITHOUT ADDITIONAL
HARDWARE
A2 TEST
VDD
lOVOD
PCF
VDD
VDD
VDD
AO
A1
VDD
A2 TEST
P~~71
SCL
t - - t -..
R
R: PULL·UP RESISTOR
t--t---.....I R= "'SE
Caus
SDA SCL
o"c BUS)
NOTES:
AO, A1, and A2 inputs must be connected to Voo or Vss but not left open.
Figure 11. PCF8571 Application Diagram
December 2, 1986
4-19
Signetics Unear Products
Product Specification
PCF8571
1K Serial RAM
POWER SAVING MODE
With the condition TEST = A2 = A 1
= AO = VDDR. the PCF8571 goes into the
power saving mode.
POWER SAVING MODE
- - - - - I OPERATING MODE
-i'====~e""
TEST
SOL
~,--\.
-- -
_-~Ir--VDD
...'so.
SM
I O _.. T--VDD
:.
\.
==:::1I~==~e""
\!.:::::::::::::::::::::: .....L,.-----~e""
VDD
VDD _________
,
~.------
~-------IDD
1_
__________ .....L
Figure 12. Timing for Power Saving Mode
+5V
!O\
fl
~
8
MICROCOMPUTER
5
II-
8
SM
VDD
A2
SOL
PCF8S7'I
7
t-
A1
AD
TEST
.!...2
1
+
!
Vss
~4
":"
TCI5541S
NOTES:
1. In the operating mode, TEST - 0 (AD, A1, - 0; A2 - 1).
2. In the power saving mode, TEST'" AO ... A1 - A2 ... VODR.
Figure 13. Application Example for Power Saving Mode
December 2. 1986
4-20
PCF8573
Signetics
Clock/Calendar With Serial I/O
Product Specification
Linear Products
DESCRIPTION
FEATURES
The PCF8573 is a low threshold, monolithic CMOS circuit that functions as a
real-time clock/calendar in the Inter IC
(l2C) bus-oriented microcomputer systems. The device includes an addressable time counter and alarm register,
both for minutes, hours, days and
months. Three special control! status
flags, COMP, POWF and NODA, are
also available. Information is transferred
serially via a two-lin bidirectional bus
(l2C). Back-up for the clock during supply interruptions is provided by a 1.2V
nickel cadmium battery. The time base is
generated from a 32.768kHz crystalcontrolled oscillator.
• Serial input/output bus (12C)
Interface for minutes, hours,
days and months
• Additional pulse outputs for
seconds and minutes
• Alarm register for presetting a
time for alarm or remote
switching functions
• Battery back-up for clock
function during supply
interruption
• Crystal oscillator control
(32.76BkHz)
PIN CONFIGURATION
N, D Packages
VDD
V ss ,
oseo
ascI
TEST
FSET
TOP VIEW
C010281S
PIN NO.
APPLICATIONS
1
2
3
4
5
6
• Automotive
• Telephony
TEMPERATURE RANGE
ORDER CODE
16-Pin Plastic DIP (SOT-38)
-40'C to + 85'C
PCF8573PN
16,Pin Plastic SOL (SOT-162A)
-40'C to + 85'C
PCF8573T
PARAMETER
RATING
UNIT
-0,3 to 8
V
VSS2
Supply voltage range (1 2 C interface)
-0.3 to 8
V
liN
Input current
10
mA
lOUT
Output current
10
mA
PD
Maximum power dissipation per package
200
mW
TA
Operating ambient temperature range
-40 to +85
TSTG
Storage temperature range
-65 to +150
'c
'c
February 10, 1987
SCl
EXTPF
~:~::: ~~~k li~~9 ) 12C bus
Enable power fail flag
PFIN
Power fail flag input
VSS2
Negative supply 2 (1 2C
interface)
MIN
10
SEC
One pulse per minute
output
One pulse per second
11
12
FSET
TEST
Oscillator tuning output
Test input; must be
13
14
15
16
ascI
OSCO
Oscillator Input
output
when not in use
Supply voltage range (clock)
VDD
CaMP
SOA
DESCRIPTION
Address input
Address input
Comparator output
connected to VSS2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
AO
A1
input
ORDERING INFORMATION
DESCRIPTION
SYMBOL
4-21
Vss 1
VDD
Oscillator input/output
Negative supply 1 (clock)
Common positive supply
853-1170 87544
•
Product Specification
Signetics Linear Products
PCF8573
Clock/Calendar With Serial I/O
BLOCK DIAGRAM
FSET
MIN
SEC
10
16
1.SV
OSCO 14
32.768 kHz
c:J
13
OSCILLATOR
OSCI
CT
TIME COUNTER
SCL
G
AD
February 10, 1987
LEVEL SHIFTER
A1
4-22
Signetics Linear Products
Product Specification
Clock/Calendar With Serial I/O
PCF8573
DC ELECTRICAL CHARACTERISTICS Vss 2 = OV; TA = -40 to + 85·C, unless otherwise specified. Typical values at
TA = + 25·C.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
Supply
Voo- VSS2
Supply voltage (1 2C interface)
2.5
5
s.o
V
VOO-VSS1
Supply voltage (clock)
1.1
1.5
(Voo- VSS2)
V
-ISS1
-ISS1
Supply current VSS1
at Voo - VSS1 = 1.5V
at Voo - Vss 1 = 5V
3
12
10
50
p.A
p.A
-lsS2
Supply current Vss2
at Voo - VSS2 = 5V
(10 = OmA on all outputs)
50
IlA
Inputs SCL, SDA, AO, A1, TEST
VIH
Input voltage HIGH
VIL
Input voltage LOW
± II
Input leakage current
at VI = VSS2 to Voo
0.7
x
V
Voo
0.3 X Voo
V
1
p.A
Inputs EXTPF, PFIN
VIH-VSS1
Input voltage HIGH
VIL - Vss1
Input voltage LOW
±II
±II
0.7
x
V
(Voo - VSS1)
0
Input leakage current
at VI = VSS1 to Voo
at TA = 25·C;
VI = Vss1 to Voo
0.3 X (Voo - VSS1)
V
1
p.A
0.1
p.A
Outputs SEC, MIN, COMP, FSET (normal buffer outputs)
VOH
VOH
VOL
VOL
Output voltage HIGH
at Voo - VSS2 = 2.5V;
-10 = 0.1mA
at Voo - Vss2 = 4 to SV;
-10=0.5mA
Voo-O.4
V
Voo-O.4
V
Output voltage LOW
at Voo - Vss2 = 2.5V;
10 = 0.3mA
at Voo - VSS2 = 4 to SV;
10 = 1.SmA
0.4
V
0.4
V
0.4
V
1
IlA
Output SDA (N-Channel open drain)
VOL
Output 'ON': 10 = 3mA
at Voo - Vss2 = 2.5 to SV
10
Output 'OFF' (leakage current)
at Voo - VSS2 = SV; Vo = 6V
Internal Threshold Voltage
VTH1
Power failure detection
1
1.2
1.4
V
VTH2
Power 'ON' reset
at VSCL = VSOA = Voo
1.5
2.0
2.5
V
February 10, 1987
4·23
•
Product Specification
Signetics Linear Products
PCF8573
Clock/Calendar With Serial I/O
AC ELECTRICAL CHARACTERISTICS Vss2 = OV; TA = -40 to + 85°C, unless otherwise specified. Typical values at
TA = + 25°C.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
Rise and Fall Times of Input Signals
tA, tF
Input EXTPF
tA, tF
Input PFIN
tA
tF
Input signals except EXTPF and PFIN
between VIL and VIH levels
rise time
fall time
1
/lS
00
IlS
1
0.3
Ils
Ils
Frequency at SeL
tLOW
at Voo - Vss2 = 4 to 6V
Pulse width LOW (see Figures 7 and 9
4.7
tHIGH
Pulse width HIGH (see Figures 7 and 9
4
tl
Noise suppression time constant at SCL and SDA input
clN
Input capacitance (SCL, SDA)
0.25
Ils
Ils
1
2.5
IlS
7
pF
Oscillator
COUT
Integrated oscillator capacitance
40
pF
RF
Oscillator feedback resistance
3
Mn
f/fosc
Oscillator stability for:
£>(Voo - Vss 1) = 100mV
at Voo - Vss 1 = 1.55V;
TA = 25"C
2 X 10-6
Quartz crystal parameters
Frequency
= 32.768 kHz
Rs
Series resistance
CL
Parallel capacitance
CT
Trimmer capacitance
February 10, 1987
40
5
4-24
kn
pF
9
25
pF
Signetics Linear Products
Product Specification
Clock/Calendar With Serial I/O
PCF8573
--+-1ri====="
SDA--L-/--r--!
I
i
SCL
DATA LINE
STABLE:
DATA VALID
---~
•
I ~~~A~! I
I ALLOWED I
Figure 1. Bit Transfer
Table 1. Cycle Length of the Time Counter
UNIT
Minutes
Hours
Days
Months
NUMBER OF BITS
COUNTING CYCLE
7
6
6
00 to 59
00 to 23
01 to 28
5
01 to 30
01 to 31
01 to 12
CARRY FOR FOLLOWING
UNIT
59
23
28
or 29
30
31
12
.....
.....
.....
.....
.....
.....
.....
CONTENT OF MONTH COUNTER
00
00
01
01
01
01
01
I
2 (see note)
4, 6, 9, 11
1, 3, 5, 7, 8, 10, 12
NOTE: Day counter may be set to 29 by a write transmission with EXECUTE ADDRESS.
FUNCTIONAL DESCRIPTION
Oscillator
The PCF8573 has an integrated crystal·controlled oscillator which provides the time base
for the prescaler. The frequency is determined by a single 32.768kHz crystal connected between OSCI and OSCO. A trimmer is
connected between OSCI and VDD.
Table 2. Power Fail Selection
EXTPF
0
0
1
1
PFIN
0
1
0
1
FUNCTION
Power fail is sensed internally
Test mode
Power fail is sensed externally
No power fail sensed
NOTE:
0: connected to Vss 1 (LOW)
1: connected to VDD (HIGH)
Prescaler and Time Counter
The prescaler provides a 128Hz signal at the
FSET output for fine adjustment of the crystal
oscillator without loading it. The prescaler
also generates a pulse once a second to
advance the seconds counter. The carry of
the prescaler and the seconds counter are
available at the outputs SEC and MIN, respectively, and are also readable via the 12C
bus. The mark-to-space ratio of both signals
is 1:1. The time counter is advanced one
count by the falling edge of output signal MIN.
A transition from HIGH to LOW of output
signal SEC triggers MIN to change state. The
time counter counts minutes, hours, days and
months, and provides a full calendar function
which needs to be corrected once every four
years. Cycle lengths are shown in Table 1.
Alarm Register
The alarm register is a 24-bit memory. It
stores the time-point for the next setting of
the status flag COMPo Details of writing and
reading of the alarm register are included in
the description of the characteristics of the
12C bus.
February 10, 1987
Comparator
The comparator compares the contents of
the alarm register and the time counter, each
with a length of 24 bits. When these contents
are equal, the flag COMP will be set 4ms after
the falling edge of MIN. This set condition
occurs once at the beginning of each minute.
This information is latched, but can be
cleared by an instruction via the 12C bus. A
clear instruction may be transmitted immediately after the flag is set, and then it will be
executed. Flag COMP information is also
available at the output COMP. The comparison may be based upon hours and minutes
only if the internal flag NODA (no date) is se\.
Flag NODA can be set and cleared by separate instructions via the 12C bus, but it is
undefined until the first set or clear instruction
has been received. Both COMP and NODA
flags are readable via the 12C bus.
Power On/Power Fail Detection
If the voltage VDD - Vss 1 falls below a certain
value, the operation of the clock becomes
undefined. Thus, a warning signal is required
to indicate that faultless operation of the
clock is not guaranteed. This information is
4-25
latched in a flag called POWF (Power Fail)
and remains latched after restoration of the
correct supply voltage until a write procedure
with EXECUTIVE ADDRESS has been received. The flag POWF can be set by an
internally-generated power fail level-discriminator signal for application with (VDD - VSS1)
greater than VTH1, or by an externally-generated power fail signal for application with
(VDD- VSS1) less than VTHI' The external
signal must be applied to the input PFIN. The
input stage operates with signals of any slow
rise and fall times. Internally-or externallycontrolled POWF can be selected by input
EXTPF as shown in Table 2.
The external power fail control operates by
absence of the VDD - Vss2 supply. Therefore,
the input levels applied to PFIN and EXTPF
must be within the range of VDD - Vss 1. A
LOW level at PFIN indicates a power fail.
POWF is readable via the 12C bus. A poweron reset for the 12C bus control is generated
on-chip when the supply voltage VDD - VSS2
is less than VTH2'
Signetics Linear Products
Product Specification
PCF8573
Clock/Calendar With Serial I/O
Interface Level Shifters
Bit Transfer (see Figure 1)
The level shifters adjust the 5V operating
voltage (Voo - Vss 2) of the microcontroller to
the internal supply voltage (Voo - VSS1) of the
clock/calendar. The oscillator and counter
are not influenced by the Voo - VSS2 supply
voltage. If the voltage Voo - VSS2 is absent
(VSS2 = Voo) the output signal of the level
shifter is HIGH because Voo is the common
node of the Voo - Vss2 and the Voo - Vss l
supplies. Because the level shifters invert the
input signal, the internal circuit behaves as if
a lOW signal is present on the inputs. FSET,
SEC, MIN and COMP are CMOS push-pull
output stages. The driving capability of these
outputs is lost when the supply voltage
Voo - VSS2 = O.
One data bit is transferred during each clock
pulse. The data on the SDA line must remain
stable during the HIGH period of the clock
pulse as changes in the data line at this time
will be interpreted as control signals.
Start and Stop Conditions
(see Figure 2)
Both data and clock lines remain HIGH when
the bus is not busy. A HIGH-to-lOW transition of the data line while the clock is HIGH is
defined as the start condition (S). A lOW-toHIGH transition of the data line while the
clock is HIGH is defined as the stop condition
(P).
System Configuration
(see Figure 3)
A device generating a message is a "transmitter", a device receiving a message is the
"receiver". The device that controls the message is the" master" and the devices which
are controlled by the master are the
"slaves".
CHARACTERISTICS OF THE 12C
BUS
The 12 C bus is for 2-way, 2-line communication between different ICs or modules. The
two lines are a serial data line (SDA) and a
serial clock line (SCl). Both lines must be
connected to a positive supply via a pull-up
resistor when connected to the output stages
of a device. Data transfer may be initiated
only when the bus is not busy.
Acknowledge (see Figure 4)
The number of data bytes transferred between the start and stop conditions from
transmitter to receiver is not limited. Each
byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level
r--,
SDA
SCL
put on the bus by the transmitter whereas the
master generates an extra acknowledge-related clock pulse. A slave receiver which is
addressed must generate an acknowledge
after the reception of each byte. Also a
master must generate an acknowledge after
the reception of each byte that has been
clocked out of the slave transmitter. The
device that acknowledges has to pull down
the SDA line during the acknowledge clock
pulse. So that the SDA line is stable lOW
during the HIGH period of the acknowledge
related clock pulse, setup and hold times
must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the
last byte that has been clocked out of the
slave. In this event, the transmitter must leave
the data line HIGH to enable the master to
generate a stop condition (see Figures 11
and 12).
Timing SpeCifications
Within the 12C bus specifications a highspeed mode and a low-speed mode are
defined. The PCF8573 operates in both
modes and the timing requirements are as
follows:
High-Speed Mode - Masters generate a
bus clock with a maximum frequency of
100kHz. Detailed timing is shown in Figure 5.
r--,
--l\.'--+i----r='----==~---.....Jo.--.....,....-__i!..Jr:_-I
I
I
I
Il s iI
IL... _ _ -JI
\
'----Jr--~,\
.
___'/
START
I p iI
I
IL _ _ ......I
SOA
SCL
STOP
cONomoN
cONomoN
Figure 2. Definition of Start and Stop Conditions
SOA----------~------------~------------~----------~~------------t__
SCL--1-------~----~-------4------~------+_----~------~----_1~------~
Figure 3. System Configuration
February 10, 1987
4-26
Signetics Linear Products
Product Speclflcotlon
PCF8573
Clock/Calendar With Serial I/O
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
CONDITION
t
I
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
--~
I
I
I
-"\!~I.._.L/____
X-_-_X
X
....J
1.._ _ _ _•
/
•_ _ _ _..1.
S
DATA OUTPUT
BY RECEIVER
Figure 4. Acknowledgement on the 12C Bus
SDA
SCL
SDA
Where:
IBUF
ftio.
ISTA
tl..OWmin
ttilGHmln
t>tLOWmin
t~tHIGHmjn
4.71JS
41'S
Isu. IsTA
t~tLOWmin
tHO. tOAT
tA
POI'S
t~ 250n5
1<1115
IF
1<300ns
!su. IsTe
t~tLOWmin
ISU. loAT
The minimum time the bus must be free before a new transmission can start
Start condition hold time
Clock LOW period
Clock HIGH period
Start condition setup time, only valid for repeated start code
Data hold time
Data setup tima
Rise time of both the SOA and Sel line
Fall time of both the SOA and Sel line
Stop condition setup time
NOTE:
1. All the values refer to VIH and VII.. levels with a voltage swing of Voo to VSS2.
Figure 5. Timing of the High-Speed Mode
February 10, 1987
4-27
•
Signetics Linear Products
Product Specification
PCF8573
Clock/Calendar With Serial I/O
SDA
\\. __ ..
.. __ J I
__
,, __ J I
__
\J --'---.C7C--~--~
L.-.-J I
START
ADDRESS
CONDITION
I
L...-.-...J L...-...-I
RiW
....._ _ _ _ _--', L....--.-J
ACK
DATA
ACK
L-...J
I
!
START
ADDRESS
CONDITION
L....-...-.I
RlW
~
ACK
L..-J
STOP
Where:
4.7ps
Clock tLOWmin
tHIGHmin
41JS
The dashed line is the acknowledgement of the receiver
Mark-la-space ratIo
1:1 (LOW-to-HIGH)
Max. number of bytes
unrestricted
Premature termination of transfer
allowed by generation of STOP condition
Acknowledge clock bit
must be provided by the master
Figure 6. Complete Data Transfer In the High-Speed Mode
Low-Speed Mode - Masters generate a
bus clock with a maximum frequency of 2kHz;
a minimum LOW period of 105118 end a
minimum HIGH period of 36511S. The mark-to-
space ratio is 1:3 LOW-to-HIGH. Detailed
timing is shown in Figure 7.
SOL
I - - - - - IHIBH- - - - " '
BOA
Where:
tauF
tHO. tSTA
lLOW
I ;'105pS (tLOWml,)
t:> 3651'8 (tHIGHmin>
130ps±25ps
390pS ±25j1S
130ps±25j1S"
1tiIGH
tsu. tSTA
tHO. teAT
!sUIIOAT
1 > 250n8
In
t-<:1ps
IF
!su.
ISTO
I;'OpS
1<300ns
130pS± 251'S
·Only vafid for repeated start code.
NOTE:
1. All the values refer to V,H and V,L levels with a voltage swing of Voo to VSS2i for definitions see high-speed mode.
Figure 7. Timing of the Low-Speed Mode
February 10, 1987
4·28
Signetics Linear Products
Product Specification
Clock/Calendar With Serial I/O
SDA \
SCL
l - - ._ _ _ _ _
PCF8573
-1J
--\J\J\J
--v--\j-START
CONDITION
START BYTE
ADDRESS
DUMMY
REPEATED
ACKNOWLEDGE
START
CONDITION
ACKNOWLEDGE
STOP
CONDITION
Where:
130llS ± 2S.us
390J.Ls± 25Jls
1:3 (LOW·la-HIGH)
0000 0001
Clock tLOWmin
tHIGHmin
Mark-ta-space ratio
Start byte
Maximum number of bytes
Premature termination of transfer
Acknowledge clock bit
6
not allowed
must be provided by master
NOTE:
1. The general characteristics and detailed specification of the 12C bus are described in a separate data sheet
(serial data buses) in handbook: ICs for digital systems in radio. audio and video equipment.
Figure 8. Complete Data Transfer In the Low-Speed Mode
ADDRESSING
Before any data is transmitted on the 12C bus,
the device which should respond is addressed first. The addressing is always done
with the first byte transmitted after the start
procedure.
MSB
I
The subaddress bits AO and A 1 correspond
to the two hardware address pins AO and A1
which allows the device to have 1 of 4
different addresses.
1, 1 0 1, 1 0 1 A1 1 AO 1ruW
Clock/Calendar READ/WRITE
Cycles
The 12C bus configuration for different clock/
calendar READ and WRITE cycles is shown
in Figures 10 and 11.
The write cycle is used to set the time
counter, the alarm register and the flags. The
transmission of the clock/calendar address is
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
followed by the MODE-POINTER-WORD
which contains a CONTROL-nibble (Table 3)
and an ADDRESS-nibble (Table 4). The ADDRESS-nibble is valid only if the preceding
CONTROL-nibble is set to EXECUTE ADDRESS. The third transmitted word contains
the data to be written into the time counter or
alarm register.
ACKNOWLEDGE
FROM SLAVE
Figure 10. Master Transmitter Transmits to Clock/Calendar Slave Receiver
February 10, 1987
I
Figure 9. Slave Address
Slave Address
The clock/calendar acts as a slave receiver
or slave transmitter. Therefore, the clock
signal SCL is only an input signal, but the data
signal SDA is a bidirectional line. The clock
calendar slave address is shown in Figure 9.
1
LSB
4-29
Product Specification
Signetics Linear Products
PCF8573
Clock/Calendar With Serial I/O
Table 3. CONTROL-nibble
C2 C1
co
FUNCTION
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
Execute address
Read control/status flags
Reset prescaler, including seconds counter; without carry for minute
counter
Time adjust, with carry for minute counter 1
Reset NODA flag
Set NODA flag
Reset COMP flag
At the end of each data word the address bits
B1, BO will be incremented automatically
provided the preceding CONTROL-nibble is
set to EXECUTE ADDRESS. There is no
carry to B2.
Table 5 shows the placement of the BCD
upper and lower digits in the DATA byte for
writing into the addressed part of the time
counter and alarm register, respectively.
Acknowledgement response of the clock calendar as slave receiver is shown in Table 6.
NOTE:
1.11 the seconds counter is below 30 there is no carry. This causes a time adjustment of max. -30 sec. From
the count 30 there is a carry which adjusts the time by max. + 30 sec.
Table 4. ADDRESS-nibble
B2 B1 BO ADDRESSED TO:
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Time counter hours
Time counter minutes
Time counter days
Time counter months
Alarm register hours
Alarm register minutes
Alarm register days
Alarm register months
Table 5. Placement of BCD Digits in the DATA Byte
DATA
MSB
LSB
UPPER DIGIT
LOWER DIGIT
UD
UC
UB
UA
LD
LC
LB
LA
ADDRESSED TO:
X
X
X
X
X
D
X
X
D
D
0
X
0
0
0
0
D
D
D
0
D
D
0
D
0
0
0
D
D
D
0
0
Hours
Minutes
Days
Months
NOTE:
1. Where "X" is the don't care bit and "0" is the data bit.
ACKNOWLEDGE
ACKNOWLEDGE
FROM SLAVE
FROM MASTER
t
-
DATA
AT THIS MOMENT MASTER
TRANSMITTER BECOMES
MASTER RECEIVER AND
CLOCK/CALENDAR
BECOMES SLAVE TRANSMITIER
~t(n
AUTO INCREMENT
OF 81,80
A
AUTO INCREMENT
OF 81, SO
NOTE:
Figure 11. Master Transmitter Reads Clock/Calendar After Setting Mode Pointer
4-30
DATA
1) B V T E s - i - ' nth
The master receivor must signal an end-of-data to the slave transmitter by not generating an acknowledge on
the last byte that has been clocked a'-!t of the slave.
February 10, 1987
NO ACKNOWLEDGe<1)
lSB. Msa
BYTE~
Signetics Linear Products
Product Specification
Clock/Calendar With Serial I/O
PCF8573
II
NOTE:
The master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave.
Figure 12. Master Reads Clock/Calendar Immediately After First Byte
To read the addressed part of the time
counter and alarm register, plus information
from specified control/status flags, the BCD
digits in the DATA byte are organized as
shown in Table 7.
The status of the MODE·POINTER·WORD
concerning the CONTROL·nibble remains un·
Table 6. Slave Receiver Acknowledgement
ACKNOWLEDGE ON BYTE
MODE POINTER
C2
C1
CO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
0
0
0
1
1
0
1
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
82
81
80
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Address
Mode pointer
Data
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
no
yes
yes
yes
yes
yes
yes
no
no
yes
no
no
no
no
no
no
no
no
no
NOTE:
1. Where "X" is the don't care bit.
Table 7. Organization of the BCD Digits in the DATA Byte
MSB
LSB
DATA
UPPER DIGIT
LOWER DIGIT
ADDRESSED TO:
UD
UC
US
UA
LD
LC
LB
LA
0
0
0
0
0
D
0
0
D
D
D
0
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
0
0
NODA
COMP
POWF
. ..
Hours
Minutes
Days
Months
Control/status flags
NOTES:
1. Where: "0" is the data bit, • = minutes, **
February 10, 1987
= seconds.
4-31
changed until a write to MODE POINTER
conditon occurs.
Signetics Linear Products
Product Specification
PCF8573
Clock/Calendar With Serial I/O
APPLICATION INFORMATION
~1-~--~~IH~--~------o+5V
R: PULL-UP RESISTOR
R
R
SDA
Voo
MASTER DeVICE
MICROCONTROLLER
PCD8571
SCL
128 x 8-BIT STATIC CMOS RAM
Vss
DLEN1
PCE2111
64 LCD
SEGMENT DRIVER
PFIN
PCF8573
SCLI-----+-+-+
R2
R3
'--r-'
DETECTION CIRCUIT
WITH VERY HIGH
IMPEDANCE
Reh: RESISTOR FOR
PERMANENT CHARGING
8oo3461S
Figure 13. Application Example of the PCF8573 Clock/Calendar
+5Vo--'--~--~--~~~--1-----~-----------'------'
R
R
t-~--------------~--+---------------t-~--~SDA
+-~~-r-----------'--~--~----------9-~~-r--~SCL
SCL SDA Voo
c,.
AO PCF8573
Al
TEST
PF IN
EXTPF
MASTER
MICROCONTROLLER
Vss
-=-
-=-
PCD8571
V••
-=-
-=-
-=-
Figure 14. Application Example of the PCF8573 With Common VSS1 and VSS2 Supply
February 10, 1987
4-32
PCF8574
Signetics
a-Bit Remote I/O Expander
Product Specification
Linear Products
FEATURES
• Operating supply voltage: 2_5V to
6V
• Low standby current
consumption: max. 10pA
• Bidirectional expander
• Open-drain Interrupt output
• 8-bit remote I/O port for the 12C
bus
• Peripheral for the MAB8400 and
PCF8500 microcomputer families
• Latched outputs with high
current drive capability for
directly driving LEOs
• Address by 3 hardware address
pins for use of up to 8 devices
(up to 16 possible with mask
option)
The PCF8574 has low current consumption and includes latched outputs with
high current drive .capability for directly
driving LEDs. It also possesses an interrupt line (INn which is connected to the
interrupt logic of the microcomputer on
the 12C bus. By sending an interrupt
signal on this line, the remote 110 can
inform the microcomputer if there is
incoming data on its ports without having
to communicate via the 12C bus. This
means that the PCF8574 can remain a
simple slave device.
•
PIN CONFIGURATION
DESCRIPTION
The PCF8574 is a single-chip silicon
gate CMOS circuit. It provides remote
1/0 expansion for the MAB8400 and
PCF8500 microcomputer families via the
two-line serial bidirectional bus (12C). It
can also interface microcomputers without a serial interface to the 12C bus (as a
slave function only). The device consists
of an 8-bit quasi-bidirectional port and an
12C interface.
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
16-Pin Plastic DIP (SOT-36)
-40·C to +65·C
PCF6574PN
16-Pin Plastic SO package
(S016L; SOT-162A)
-40·C to + 65·C
PCF6574TD
N, D Packages
lOP VIEW
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SYMBOL
AD
A1
A2
J
~J
P2
P3
COO"".
DESCRIPTION
Address inputs
8-bit quasi-bidirectional
I/O ports
vss
P4
P5
P6
P7
J
1FIT
SCL
SOA
voo
8-blt quasi-bidirectional
I/O ports
Interrupt output
Serial clock line
Serial data line
POSitive supply
ABSOLUTE MAXIMUM RATINGS
RATING
UNIT
Supply voltage range
-0.5 to +7
V
VI
Input voltage range (any pin)
Vss-0.5 to
Voo + 0.5
V
SYMBOL
Voo
PARAMETER
±II
DC current into any input
20
rnA
±Io
DC current into any output
25
rnA
±Ioo; Iss
Voo or Vss current
100
rnA
PlOT
Total power dissipation
400
mW
Po
Power dissipation per output
100
mW
TSlG
Storage temperature range
-65 to +150
·C
TA
Operating ambient temperature range
-40 to +65
·C
December 2, 1966
4-33
653-1037 66701
Product Specification
Signetics Linear Products
PCF8574
8-Bit Remote I/O Expander
BLOCK DIAGRAM
PCF8574
INT
13
AD
PO
A1
P1
A2
P2
14
P3
SCL
15
SDA
P4
P5
P6
P7
VDD~~--------~::::::l
WRrrEPU~Eo-~-----------------r~J>__l~~
SHIFT~~~:r~~ 0-+----....
FF
~----~~ R Q~--------------~~
+---1r-.....--~-!- PO
TO
P7
'---+----......~- Vss
Q
FF
READ PULSE
o--=:::;L./--t-----t c, R
TO o--------------------------J.---====lD----------.~TO
DATA
SHIFT REGISTER
INTERRUPT
LOGIC
Figure 1. Simplified Schematic Diagram of Each Port
December 2, 1986
4·34
Signetics Linear Products
Product Specification
8-Bit Remote I/O Expander
PCF8574
DC ELECTRICAL CHARACTERISTICS Voo = 2.5 to 6V; Vss = oV; TA = -40·C to + a5·C, unless otherwise specified.
liMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
Supply (Pin 16)
Voo
Supply voltage
100
1000
Supply current at Voo
operating
standby
VREF
Power-on reset voltage level 1
2.5
= 6V;
6
V
100
10
p.A
p.A
204
V
V
no load, inputs at Voo , Vss
1.3
Input Sel; Input/output SOA (Pins 14; 15)
VIL
Input voltage lOW
-0.5V
0.3Voo
VIH
Input voltage HIGH
0.7Voo
Voo +0.5
10L
Output current lOW at VOL
= OAV
3
V
mA
IILlI
Input! output leakage current
100
nA
fseL
Clock frequency (See Figure 6)
100
kHz
ts
Tolerable spike width at SCl and SDA input
CI
Input capacitance (SCl, SDA) at VI
= Vss
100
ns
7
pF
I/O ports (Pins 4 to 7; 9 to 12)
VIL
Input voltage lOW
-0.5V
0.3Voo
V
VIH
Input voltage HIGH
0.7Voo
Voo+ 0.5V
V
±IIHL
Maximum allowed input current through protection diode at
VI;;'VOO or ';;Vss
400
p.A
10L
Output current LOW at VOL = 1V; Voo
-IOH
Output current HIGH at VOH
-IOHt
Transient pull-up current HIGH during acknowledge
(see Figure 14) at VOH = Vss
CliO
Input!output capacitance
= Vss
= 2.5V
5
(current source only)
30
mA
100
300
0.5
p.A
mA
10
pF
4
I'S
Port timing; CL';; 100pF (see Figures 10 and 11)
tpv
Output data valid
tps
Input data setup
0
I'S
tpH
Input data hold
4
I'S
Interrupt INT (Pin 13)
10L
Output current lOW at VOL = OAV
IIOHI
Output current HIGH at VOH
1.6
= Voo
mA
100
nA
4
4
"s
/1S
-0.5V
O.3Voo
V
O.7Voo
Voo + O.5V
V
100
nA
INT timing; CL';; 100pF (see Figure 11)
tlv
tlR
Input data valid
Reset delay
Select Inputs AO, A 1, A2 (Pins 1 to 3)
VIH
Input voltage lOW
VIH
Input voltage HIGH
lid
Input leakage current at VI
= Voo
or Vss
NOTE:
1. The power-on reset circuit resets the 12C bus logic with Voo
December 2, 1986
< VREF
and sets all ports to logic 1 (input mode with current source to Voo).
4-35
•
Signetics Unear Products
Product Specification
8-Bit Remote I/O Expander
CHARACTERISTICS OF THE 12c
BUS
The 12C bus is for 2-way, 2-line communication between different ICs or modules. The
two lines are a serial data line (SDA) and a
SDA
PCF8574
serial clock line (SCl). Both lines must be
connected to a positive supply via a pull-up
resistor when connected to the output stages
of a device. Data transfer may be' initiated
only when .the bus is not busy.
Bit Transfer
One data bit is transferred during each clock
pulse. The data on the SDA line must remain
stable during the HIGH period of the clock
pulse, as changes in the data line at this time
will be interpreted as control signals.
_I,--~_~X'--:---~:~~--ll..-
~
SOL
DATAUNE
STABlE:
DATAVAUD
I
CHANGE
I
I OFDA'DI I
I ALLOWED I
Figure 2_ Bit Transfer
Start and Stop Conditions
Both data and clock lines remain HIGH when
the bus is not busy. A HIGH-to-lOW transi-
SDA
-,
~~
I
II I
.1 ____
~I
tion of the data line while the clock is HIGH is
defined as the start condition (S). A lOW-toHIGH transition of the data line while the
I______ ::
~
~~
\
_______
~
clock is HIGH is defined as the stop condition
(P).
________
rJr~
II
~IJ
III
SDA
,.______~I----~I--~
\'-_--J/
SOL
IPI
1!- SOL
L_.J
STARTCONDmoN
STOP CONDITION
WF18510S
Figure 3_ DeflnHlon of Start and Stop Conditions
System Configuration
A device generating a message is a "transmitter"; a device receiving a message is the
"receiver". The device that controls the message is the "master" and the devices which
are controlled by the master are the
"slaves".
SDA----.-------~----~~----._----~--SOL-~-;----1_-r---_4~_+---_.-4_---~~~--
Figure 4, System Configuration
December 2, 1988
4-36
Signetics Unear Products
Product Specification
8-Bit Remote I/O Expander
PCF8574
lated clock pulse. A slave receiver which is
addressed must generate an acknowledge
after the reception of each byte. Also, a
master must generate an acknowledge after
the reception of each byte that has been
clocked out of the slave transmitter. The
device that acknowledges has to pull down
the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW
Acknowledge
The number of data bytes transferred between the start and stop conditions from
transmitter to receiver is not limited. Each
byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level
put on the bus by the transmitter whereas the
master generates an extra acknowledge re-
during the HIGH period of the acknowledge.
Related clock pulse, setup and hold times
must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the
last byte that has been clocked out of the
slave. In this event the transmitter must leave
the data line HIGH to enable the master to
generate a stop condition.
START
CONDITION
I
SCLFROM
MASTER
I
I
I
DATAOUTPUT
BY TRANSMITTER
X
~
1\1--1./ ___...... ,,____
S
DATA OUTPUT
BY RECEIVER
Figure 5. Acknowledgement on the 12C Bus
Timing Specifications
Within the 12C bus specifications a highspeed mode and a low-speed mode are
defined. The PCF8574 operates in both
modes and the timing requirements are as
follows:
High-Speed Mode
Masters generate a bus clock with a maximum frequency of 100kHz. Detailed timing is
shown in Figure 6.
SOA
seL
SOA
Where:
IBUF
t;;,.tLOWmin
tHO; ISTA
tLOWmln
tHIGHmln
t;;"tHIGHmin
Isu: 1sT.
t;;..tLOWmin
tHO: tDAT
4.71018
4~s
t"O~
tsUi tDAT
1>250n8
tR
tF
t';1~
t<300ns
tsu; tsTO
t;;a.tLOWmin
The minimum time the bus must be free before a new transmission can start
Start condition hold time
Clock LOW period
Clock HIGH period
Start condition set-up time; only valid for repeated start code
Data hold time
Data setup time
Rise time of both the SOA and Sel line
Fall time of both the SOA and SCL line
Stop condition setup time
NOTE:
All the values refer to V,H and VIL levels with a voltage swing of Vss to Vco.
Figure 6_ Timing of the High-Speed Mode
December 2, 1986
4-37
Signetics Linear Products
Product Specification
8-Bit Remote I/O Expander
SDA
PCF8574
•
V ---L.J::JL--rr:T\.L--~
.. __ 1•
__
,-__ .I;
__
\. __ J
-.,..;
-------.-..-
- . - - . - -..-
START ADDRESS
CONDmON
R/'ii
DATA
ACK
•
""--"
START
ACt<
---ADDRESS
- . - - . . - -..R/'ii
ACK
SlOP
CONDmON
WF'.....
Where:
Clock tl.OWmin
4.71JS
IHIGHmin
4ps
The dashed line is the acknowledgement of the receiver
Mark-to-space ratio
Maximum number of bytes
Premature tennination of transfer
Acknowledge clock bit
1:1 (LOW-la-HIGH)
Unrestricted
Allowed by generation of STOP condition
Must be provided by the master
Figure 7. Complete Data Transfer In the Hlgh·Speed Mode
Low-Speed Mode
Masters generate a bus clock with a maxi·
mum frequency of 2kHz; a minimum LOW
period of 105jlS and a minimum HIGH period
of 365jlS. The mark·ta-space ratio is 1:3
LOW·to·HIGH. Detailed timing is shown in
Figure 8.
SDA
SCL
1+---·0""'----1
SDA
Where:
taUF
IttD: IsTA
It.ow
t;;' tOS,.. (tLOWmI..J
t;;' 365,.. (Itt'GHmW
t30,... 25,..
tHIGH
390ps± 25ps
Isu: IsTA
Itt.,; toAT
Isu: !oAT
1 > 250n8
'"
IF
Isu: taro
t30,... 25,..'
t;;'Ops
t DLEN
400
ns
tSULD
Setup time
DLEN -> CLB (load pulse)
1000
ns
November 14, 1986
Measured with a voltage swing of
minimum VIH - VIL
4-47
•
Signetlcs Linear Products
Product Specification
SAB3013
Hex 6-Bit DAC
~~----------------------------~OO%
10%
V,H
ClB
---+-='1"::::::----"'-
V,L-----..j...;~
V,H
OATA
V,L
-----+-+-l--.... . . =~-++...".~I'
---+++--'''''='--+-I--t''-
ENABLE
DATA
DATA
DISABLE
LOAD
Figure 1. CBUS Timing
OLEN
CLB
DATA
SYSTEM
ADDRESS
MEMORY
ADDRESS
ANALOG VALUE
WF18700S
Figure 2. Waveforms Showing a CBUS Transmission
November 14. 1986
4-48
Signetics Linear Products
Product Specification
SAB3013
Hex 6-Bit DAC
FUNCTIONAL DESCRIPTION
The SAB3013 is designed to deliver analog
values in microcomputer-controlled television
receivers and radio receivers. The circuit comprises an analog memory and 01 A converter
for six analog functions with a 6-bit resolution
for each. The information for the analog memory is transferred by the microcomputer via an
asynchronous serial data bus.
The SAB3013 accomplishes a word format
recognition, so it is able to operate one
common data bus together with circuits having different word formats.
The data word of the microcomputer used for
the SAB3013 consists of information for addressing the appropriate SAB3013 circuit (2
bits), for addressing the analog memories
concerned (3 bits) and processing of the
wanted analog value (6 bits). The address of
the circuit is externally programmable via two
inputs. It is possible to address up to four
SAB3013 circuits via one common bus.
The built-in oscillator can be used for a frequency between 30kHz and l.4MHz. The analog values are generated as a pulse pattern
with a repetition rate of fClK/64 (maximum
21.8kHz at fClK = l.4MHz), and the analog
November 14, 1986
values are determined by the ratio of the
HIGH-time and the cycle time. A OC voltage
proportional to the analog value is obtained by
means of an external integration network (Iowpass filter).
HANDLING
Inputs and outputs are protected against
electrostatic charge in normal handling. However, to be totally safe, it is desirable to take
normal precautions appropriate to handling
MaS devices.
• The start-bit must be LOW
• The system address bits must be
A = SAA and B = SAB
• The analog address must be valid
The data word for the SAB3013 consists of
the following bits (see Figure 2):
1 start-bit
2 system address bits (A and B)
3 address bits for selection of the required
analog memory
6 data bits for processing the analog value
ADDRESS INPUTS (SAA, SAB)
OPERATION DESCRIPTION
The data input is achieved serially via the
inputs OATA, OLEN and CLB. Clock pulses
have to be applied at input CLB for data
processing at input OATA. Oata processing is
only possible when OLEN = HIGH. The data
from the data buffer is loaded directly into the
output latch on receipt of a load pulse at input
CLB (OLEN = LOW), provided the following
conditions are met:
• 12 clock pulses must be received at
input CLB (word format control) during
transmission (OLEN = HIGH)
4-49
The address of the SAB3013 is programmed
at the inputs SAA and SAB. These inputs
must be defined and not left open-circuit.
Reset
The circuit internally generates a reset cycle
with a duration of one clock cycle after switching on the supply. If a spike on the supply is
likely to destroy data, a reset signal will be
generated. All analog memories are set to
50% (analog value 32/64) after the reset
cycle. The supply voltage rise dVDD/dt must be
maximum O.5V1p.s and minimum 0.2V1p.s.
•
SAB3035
Signetics
FLL Tuning and Control Circuit
Product Specification
Linear Products
DESCRIPTION
The SAB3035 provides closed-loop digital tuning of TV receivers, with or without
AFC, as required. It also controls up to 8
analog functions, 4 general purpose I/O
ports, and 4 high-current outputs for
tuner band selection.
The IC is used in conjunction with a
microcomputer from the MAB8400 family and is controlled via a two-wire, bidirectional 12C bus.
FEATURES
• Combined analog and digital
circuitry minimizes the number of
additional interfacing components
required
• Frequency measurement with
resolution of 50kHz
• Selectable prescaler divisor of 64
or 256
• 32V tuning voltage amplifier
• 4 high-current outputs for direct
band selection
• 8 static digital-to-analog
converters (OACs) for control of
analog functions
• Four general purpose Inputl
output (I/O) ports
• Tuning with control of speed and
direction
• Tuning with or without AFC
• Single-pin, 4MHz on-chip
OSCillator
• 12C bus slave transceiver
PIN CONFIGURATION
N Package
DAC3
OAC2
CACI
DACD
osc
FOIY
P13
P12
P11
APPLICATIONS
Pl0
• Satellite receivers
• Television receivers
• CATV converters
vcc,
VCC1
TUN
TOP VIEW
C011950S
PIN NO.
5
6
7
8
9
10
DAC4
DAC5
OAC6
DAC7
SDA
SCL
P20
P21
P22
P23
11
AFC+
12
la
AFCTI
I.
15
16
17
GND
TUN
Vee,
VCC3
18
19
20
21
22
Pl0
Pl1
P12
P13
VCC2
23
2.
25
26
27
28
FDIV
OSC
DACO
DACI
DAC2
DAC3
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
-20'C to + 70'C
SAB3035N
28-Pin Plastic DIP (SOT-l17)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
UNIT
-0.3 to + 18
-0.3 to + 18
-0.3 to +36
V
V
V
-0.3 to + 18
-0.3 to + 18
-0.3 to +18
-0.3 to VCCI '
-0.3 to VCC, 2
-0.3 to Vcca'
-0.3 to VCC2 2
-0.3 to Vcc, I
-0.3 to +5
-0.3 to VCCI I
V
V
V
V
V
V
V
V
V
V
PARAMETER
VCCI
VCC2
Vcca
Supply voltage ranges:
(Pin 16)
(Pin 22)
(Pin 17)
VSOA
VSCL
VCC2X
VAFC+. AFCVTI
VTUN
VCC1X
VFOIV
VOSC
VOACX
Input/output voltage ranges:
(Pin 5)
(Pin 6)
(Pins 7 to 10)
(Pins 11 and 12)
(Pin 13)
(Pin 15)
(Pins 18 to 21)
(Pin 23)
(Pin 24)
(Pins 1 to 4 and 25 to 28)
•
DESCRIPTION
SYMBOL
}
Outputs of static DACs
Serial data line
Serial clock line
}r c bus
2
}
General purpose
input! output ports
1
AFC inputs
Tuning voltage amplifier inverting
input
PTOT
Total power dissipation
1000
mW
TSTG
Storage temperature range
-65 to + 150
'C
TA
Operating ambient temperature range
-20 to +70
'C
Ground
Tuning voltage amplifier output
+ 12V
+ 32V
supply voltage
supply for tuning voltage
ampUfier
}
High-current band-selection
output ports
Positive supply for high-current
band-selection output circuits
Input from prescaler
Crystal oscillator input
}
Outputs of static DACs
NOTES:
1. Pin voltage may exceed supply voltage if current is limited to 10mA.
2. Pin voltage must not exceed 18V but may exceed VCC2 if current is limited to 200mA.
December 2. 1986
4-50
853-1031 86698
Signetics Linear Products
Product Specification
SAB3035
FLL Tuning and Control Circuit
BLOCK DIAGRAM
Vee.
f1
Cl
osc
PRESCALER
VCC2
FD'V
'4
Veel
23
Vea
[E]
.,
ffi]
••
PORT1
SA83035
TUNER
CONTROL
CIRCUIT
SOAo-,..-oOj
I!EJ
SCLo-+--i
(E]
o-';':.I-_-HJP23~ D'1PJ :::tiaZl
,.
18
I
"
TUNING CONTROL CIRCUIT
I TD'R "
PORT 2
CONTROL CIRCUIT
IIFCT
I
rElGm
DEl
,.
TUN
C ONT
AFC>
"
T'
lIFe.
December 2, 1986
4-51
Signetics linear Products
Product Specification
SAB3035
FLL Tuning and Control Circuit
DC AND AC ELECTRICAL CHARACTERISTICS
TA ~ 25·C; VCC1, VCC2, Vcca at typical voltages, unless otherwise
specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
VCCl
VCC2
Vcca
Supply voltages
10.5
4.7
30
12
13
32
13.5
16
35
V
V
V
ICCl
ICC2
Icca
Supply currents (no outputs loaded)
20
0
0.2
32
50
0.1
2
rnA
rnA
mA
ICC2A
IccaA
Additional supply currents (A)
See Note 1
-2
0.2
IOHP1X
2
rnA
rnA
PTOT
Total power dissipation
TA
Operating ambient temperature
0.6
400
mW
·C
-20
+70
3
VCC1- 1
V
-0.3
1.5
V
#JA
#JA
12C bus Inputs/outputs SDA input (Pin 5) SCL input (Pin 6)
VIH
Input voltage HIGH 2
VIL
Input voltage LOW
IIH
Input current HIGH 2
10
IlL
Input current LOW2
10
VOL
Output voltage LOW at IOL ~ 3mA
IOL
Maximum output sink current
SDA output (Pin 5, open-collector)
0.4
5
V
rnA
Open-collector I/O ports P20, P21, P22, P23 (Pins 7 to 10, open-collector)
VIH
Input voltage HIGH
2
16
V
VIL
Input voltage LOW
-0.3
0.8
V
#JA
#JA
IIH
Input current HIGH
25
-IlL
Input current LOW
25
VOL
Output voltage LOW at IOL ~ 2mA
IOL
Maximum output sink current
0.4
V
rnA
4
AFC amplifier Inputs AFC+, AFC- (Pins 11, 12)
Transconductance for input voltages up to 1V differential:
AFCSl
0
0
1
1
gOO
gOl
g10
gll
AFCS2
0
1
0
1
100
15
30
60
250
25
50
100
Tolerance of transconductance multiplying factor (2, 4, or 8)
when correction-in-band is used
-20
VIOFF
Input offset voltage
-75
VCOM
Common-mode input voltage
CMRR
Common-mode rejection ratio
50
PSRR
Power supply (VCC1) rejection ratio
50
II
Input current
~Mg
December 2, 1986
3
800
35
70
140
#JAN
#JAN
#JAN
+20
%
+75
mV
VCCl- 2.5
V
dB
dB
500
4-52
nAN
nA
Signetics Uneer Products
Product Specification
SAB3035
FLL Tuning and Control Circuit
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) TA = 25°C; VCC1, VCC2, Vccs at typical voltage, unless
otherwise specified.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
Tuning voltage amplifier Input TI, output TUN (Pins 13, 15)
Maximum output voltage at ILOAD = ± 2.5mA
VTUN
Vccs- 1.6
Vccs- O.4
V
Minimum output voltage at ILOAD = ± 2.5mA:
VTMOO
VTM10
VTMll
VTMII
a
1
1
-ITUNH
Maximum output source current
ITUNL
Maximum output sink current
ITI
Input bias current
PSRR
Power supply Vccs rejection ratio
VTMIO
a
a
1
300
450
650
2.5
500
650
900
mV
mV
mV
B
rnA
rnA
40
-5
+5
60
nA
dB
Minimum charge IT to tuning voltage amplifier
TUHNI
a
a
1
1
CHao
CHOI
CH10
CHll
TUHNO
a
1
a
1
Tolerance of charge (or .:lVTUN) multiplying factor when COIB
and/or TUS are used
.:lCH
0.4
4
15
130
1
8
30
250
-20
1.7
14
48
370
vAl/J-s
vA/lJ.S
vAl/J-s
vA/lJ.S
+20
%
5.1
41
160
1220
vA
vA
vA
vA
+15
%
0.4
V
200
rnA
Maximum current I into tuning amplifier
TUHNI
a
a
1
1
ITOO
ITOI
IT10
ITlI
TUHNO
a
1
a
1
1.7
15
65
530
3.5
29
110
875
Correctlon-In-band
Tolerance of correction-in-band levels 12V, 18V, and 24V
.:lVCIB
-15
Band-select output ports Pia, Pll, P12, P13 (Pins 18 to 21)
VOH
Output voltage HIGH at -IOH = 50mAs
VOL
Output voltage LOW at IOL = 2mA
-IOH
Maximum output source currentS
IOL
Maximum output sink current
V
VCC2- 0.6
130
rnA
5
FDIV Input (Pin 23)
VFDIV
(P·P)
Input voltage (peak-to-peak value) tRISE and tFALL .;;; 40ns
0.1
2
V
Duty cyrile
40
60
%
fMAX
Maximum input frequency
ZI
Input impedance
14.5
8
MHz
kn
CI
Input capacitance
5
pF
OSC Input (Pin 24)
Rx
Crystal resistance at resonance (4MHz)
December 2, 1986
150
4·53
n
•
Signetics linear Products
Product Specification
SAB3035
Fll Tuning and Control Circuit
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) TA - 25"C; vcc" VCC2, VCC3 at typical voltage, unless
otherwise specified.
LIMITS
UNIT
PARAMETER
SYMBOL
Min
Typ
Max
DAC outputs 0 to 7 (Pins 25 to 28 and 1 to 4)
VOH
Maximum output voltage (no load) atVCCI = 12V"
10
11.5
VOL
Minimum output voltage (no load) at VCCI = 12V"
0.1
1
V
V
tNo
Positive value of smallest step (1 least significant bH)
0
350
mV
Deviation from linearity
0.5
V
Zo
Output impedance at ILOAO - ± 2mA
70
n
-IOH
Maximum output source current
6
rnA
IOL
Maximum output sink current
rnA
8
PoweHiown reset
Vpo
Maximum supply voltage VCCI at which power-down reset is
active
tR
VCCI rise time during power-up (up to Vpo)
7.5
9.5
5
V
lIS
Voltage level for valId module address
VVAOO
VVAOI
VVAIO
VVAII
Voltage level at P20 (Pin 7) for valid module address
function of MAl, MAO
MAl
MAO
0
0
0
1
1
0
1
1
as
a
-0.3
-0.3
2.5
VCCI- 0.3
16
0.8
Vccl- 2
VCCI
V
V
V
V
NOTES:
I. For each band-select ou1pUt which Is programmed at logic I, sourcing a current 10HP'X, the additional supply currents (A) shown must be added to
ICC2 and 1003, respectively.
2. If VCC, < tV, the input current Is limited to IOIlA at input vol1ages up to 16V.
3. At continuous opsration the output current should not exceed SOmA. When the output is short-circuHad to ground for ssveral seconds, the device may
be damaged.
4. Values are proportional to Vcc,.
December 2, 1986
4-54
Signetics Linear Products
Product Specification
SAB3035
FLL Tuning and Control Circuit
FUNCTIONAL DESCRIPTION
The SAS3035 is a monolithic computer interface which provides tuning and control functions and operates in conjunction with a
microcomputer via an 12C bus.
Tuning
This is performed using frequency-locked
loop digital control. Data corresponding to the
required tuner frequency is stored in a 15-bit
frequency buffer. The actual tuner frequency,
divided by a factor of 256 (or by 64) by a
prescaler, is applied via a gate to a 15-bit
frequency counter. This input (FDIV) is measured over a period controlled by a time
reference counter and is compared with the
contents of the frequency buffer. The result of
the comparison is used to control the tuning
voltage so that the tuner frequency equals
the contents of the frequency buffer multiplied by 50kHz within a programmable tuning
window (TUW).
The system cycles over a period of 6Ams (or
2.56ms), controlled by the time reference
counter which is clocked by an on-chip 4MHz
reference oscillator. Regulation of the tuning
voltage is performed by a charge pump frequency-locked loop system. The charge IT
flowing into the tuning voltage amplifier is
controlled by the tuning counter, 3-bit DAC,
and the charge pump circuit. The charge IT is
linear with the frequency deviation fl.f in steps
of 50kHz. For loop gain control, the relationship fl.IT I fl.f is programmable. In the normal
mode (when control bits TUHNO and TUHN1
are both at logic 1, see OPERATION), the
minimum charge IT at fl.f = 50kHz equals
250pAi p.s (typical).
Sy programming the tuning sensitivity bits
(TUS), the charge IT can be doubled up to 6
times. If correction-in-band (COIS) is programmed, the charge can be further doubled
up to three times in relation to the tuning
voltage level. From this, the maximum charge
IT at fl.f=50kHz equals 26 X 23 X 250pAi p.s
(typical).
The maximum tuning current I is 875p.A
(typical). In the tuning-hold (TUHN) mode
(TUHN is Active-LOW), the tuning current I is
reduced and, as a consequence, the charge
into the tuning amplifier is also reduced.
1
mab
The minimum tuning voltage which can be
generated during digital tuning is programmable by VTMI to prevent the tuner from being
driven into an unspecified low tuning voltage
region.
The AFC has programmable polarity and
transconductance; the latter can be doubled
up to 3 times, depending on the tuning
voltage level if correction-in-band is used.
Eight 6-bit digital-to-analog convertersDACO to DAC7 - are provided for analog
control.
The direction of tuning is programmable by
using control bits TDIRD (tuning direction
down) and TDIRU (tuning direction up). If a
tuner enters a region in which oscillation
stops, then, providing the prescaler remains
stable, no FDIV signal is supplied to CITAC. In
this situation the system will tune up, moving
away from frequency lock-in. This situation is
avoided by setting TDIRD which causes the
system to tune down. In normal operation
TDIRD must be cleared.
CITAC goes into the power-down reset mode
when VCC1 is below 8.5V (typical). In this
mode all registers are set to a defined state.
Reset can also be programmed.
If a tuner stops oscillating and the prescaler
becomes unstable by going into self-oscillation at a very high frequency, the system will
INSTRUCTION BYTE
MA
L_
I,
I,
I,
mlb
RIW
Figure 1. 12C Bus Write Format
December 2, 1986
Setting both TDIRD and TDIRU causes the
digital tuning to be interrupted and AFC to be
switched on.
An in-lock situation can be detected by reading FLOCK. When the tuner oscillator frequency is within the programmable tuning
window (TUW), FLOCK is set to logic 1. If the
frequency is also within the programmable
AFC hold range (AFCR), which always occurs
if AFCR is wider than TUW, control bit AFCT
can be set to logic 1. When set, digital tuning
will be switched off, AFC will be switched on
and FLOCK will stay at logic 1 as long as the
oscillator frequency is within AFCR. If the
frequency of the tuning oscillator does not
remain within AFCR, AFCT is cleared automatically and the system reverts to digital
tuning. To be able to detect this situation, the
occurrence of positive and negative transitions in the FLOCK signal can be read (FLI
1Nand FLlON). AFCT can also be cleared by
programming the AFCT bit to logic O.
MODULE ADDRESS
MA
react by tuning down, moving away from
frequency lock-in. To overcome this, the system can be forced to tune up at the lowest
sensitivity (TUS) value, by setting TDIRU.
4·55
Control
For tuner band selection there are four outputs-P10 to P13-which are capable of
sourcing up to 50mA at a voltage drop of less
than 600mV with respect to the separate
power supply input VCC2
For additional digital control, four open-collector 1/0 ports - P20 to P23 - are provided. Ports P22 and P23 are capable of detecting positive and negative transitions in their
input signals. With the aid of port P20, up to
three independent module addresses can be
programmed.
Reset
OPERATION
Write
CITAC is controlled via a bidirectional twowire 12C bus. For programming, a module
address, R/W bit (logic 0), an instruction byte,
and a datal control byte, are written into
CITAC in the format shown in Figure 1.
DATA/CONTROL BYTE
•
Product Specification
Signetics Linear Products
FlL Tuning and Control Circuit
The module address bits MAl, MAO are used
to give a 2·bit module address as a function
of the voltage at port P20 as shown in
Table 1.
SAB3035
Table 1. Valid Module Addresses
Acknowledge (A) is generated by CITAC only
when a valid address is received and the
device is not in the power-down reset mode
(VCCl > 8.SV (typical».
Tuning
MAl
MAO
P20
0
0
1
1
0
1
0
1
Don't care
GND
Y2 Veel
Veel
Table 2. Tuning Current Control
Tuning is controlled by the instruction and
data/control bytes as shown in Figure 2.
Frequency
Frequency is set when Bit 17 of the instruction
byte is set to logic 1; the remainder of this
byte together with the data/control byte are
loaded into the frequency buffer. The frequency to which the tuner oscillator is regulated equals the decimal representation of the
lS-bit word multiplied by SOkHz. All frequency
bits are set to logic 1 at reset.
TUHN1
TUHNO
TYP.IMAX
(IlA)
TYP.ITMIN
TYP. AVTUNmln at CINT = l!'F
()lA/I'S)
(!'V)
0
0
1
1
0
1
0
1
3.S 1
29
110
875
l'
8
30
250
l'
8
30
2S0
NOTE:
1. Values after reset.
During tuning but before lock-in, the highest
current value should be selected. After lock-in
the current may be reduced to decrease the
tuning voltage ripple.
Tuning Hold
The TUHN bits are used to decrease the
maximum tuning current and, as a consequence, the minimum charge IT (at
Af = SOkHz) into the tuning amplifier.
The lowest current value should not be used
for tuning due to the input bias current of the
DATA/CONTROL BYTE
INSTRUCTION BYTE
I,
FRED
TenD
TeD1
-
I,
Is
I,
I,
I,
I,
Fl'
F13
F12
F11
F10
F9
I.
F8
-
0,
0,
0,
0,
F.
F.
F7
F6
F5
VTMIO
AFCR1
AFCRO TUHNl
VTMI1
COIB1
COIBO
AFCS1
Figure 2. Tuning Control Format
4-56
Os
AFCT
TCD2
December 2, 1986
tuning voltage amplifier (maximum SnA).
However, it is good practice to program the
lowest current value during tuner band
switching.
a,
0,
DO
F2
F1
FO
TUHNO
TUW1
TUWO
AFCSO
TUS'
TUS1
TUSO
AFCP
FDIVM
TDIRD
TOIRU
Signetics Linear Products
Product Specification
FLL Tuning and Control Circuit
SAB3035
Table 3. Minimum Charge IT as a Function of TUS t.f
TUHNO Logic 1; TUHN1 Logic 1
=
=
TUS2
TUS1
TUSO
TYP.ITMIN
(mA/lls)
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0.25 1
0.5
1
2
4
8
16
= 50kHz;
TYP. AVTUNmln at CINT
(mV)
=11lF
0.25 1
0.5
1
2
4
8
16
Correctlon·ln·Band
This control is used to correct the loop gain 01
the tuning system to reduce in·band varia·
tions due to a non·linear voltage/frequency
characteristic of the tuner. Correction·in·band
(COl B) controls the time T of the charge
equation IT and takes into account the tuning
voltage VTUN to give charge multiplying fac·
tors as shown in Table 4.
NOTE:
1. Values after reset.
Table 4. Programming Correction-In-Band
COIB1
COIBO
0
0
1
1
0
1
0
1
The transconductance multiplying lactor 01
the AFC amplifier is similar when COIB is
used, except for the lowest transconductance
which is not affected.
CHARGE MULTIPLYING FACTORS AT
TYPICAL VALUES OF VTUN AT:
< 12V
12 to 18V
18 to 24V
> 24V
11
1
1
1
11
1
1
2
11
1
2
4
11
2
4
8
NOTE:
1. Values after reset.
Table 5. Tuning Window Programming
TUW1
TUWO
IAI I (kHz)
TUNING WINDOW (kHz)
0
0
1
0
1
0
01
50
150
01
100
300
NOTE:
1. Values after reset.
Table 6. AFC Hold Range Programming
AFCRl
AFCRO
IAI I (kHz)
AFC HOLD RANGE (kHz)
0
0
1
0
1
0
01
350
750
01
700
1500
NOTE:
1. Values after reset.
Table 7. Transconductance Programming
AFCS1
AFCSO
TYP. TRANSCONDUCTANCE (IlA/V)
0
0
1
1
0
1
0
1
0.25 1
25
50
100
NOTE:
1. Value after reset.
December 2, 1986
4-57
Tuning Sensitivity
To be able to program an optimum loop gain,
the charge IT can be programmed by chang·
ing T using tuning sensitivity (TUS). Table 3
shows the minimum charge IT obtained by
programming the TUS bits at AI=50kHz;
TUHNO and TUHNl = logic 1.
Tuning Window
Digital tuning is interrupted and FLOCK is set
to logic 1 (in·lock) when the absolute devia·
tion IAfl between the tuner oscillator frequen·
cy and the programmed frequency is smaller
than the programmed TUW value (see Table
5). If IAfl is up to 50kHz above the values
listed in Table 5, it is possible for the system
to be locked depending on the phase rela·
tionship between FDIV and the reference
counter.
AFC
When AFCT is set to logic 1 it will not be
cleared and the AFC will remain on as long as
IAfl is less than the value programmed for the
AFC hold range AFCR (see Table 6). It is
possible for the AFC to remain on for values
of up to 50kHz more than the programmed
value depending on the phase relationship
between FDIV and the reference counter.
Transconductance
The transconductance (g) of the AFC amplifier
is programmed via the AFC sensitivity bits
AFCS as shown in Table 7.
•
Product Specification
Signetics linear Products
SAB3035
FLL Tuning and Control Circuit
INSTRUCTION BYTE
:~
"
•
"
"
:
•
1
:
DATA/CONTROL BYTE
"
"
•
"
•
1
: : : :
X.
'0
"
• •
XI
:
X.
I
D,
D.
D.
D,
P23
P22
P21
P2.
AX.
AX.
D,
D,
Do
PI'
PI'
P11
PI.
AX.
AX.
AXI
AX.
D,
Figure 3. Control Programming
MODULE ADDRESS
I s l'
1
• • •
MA
1
PORT INFORMATION
TUNINGJRESET INFORMATION
~A
1
I I
•
A
I I I
•I I
A
A
l§'~
~:::
RiWJ
P
MMASTER
PI20
PI21
P'22
FLION
FLl1N
PI23
FLOCK
P22ION
FROM CITAC
P22/1 N
P23fON
P23J1
FRO M MASTER
Figure 4. Information Byte Format
AFC Polarity
If a positive differential input voltage is applied to the (switched on) AFC amplifier, the
tuning voltage VTUN falls when the AFC
polarity bit AFCP is at logic 0 (value after
reset). At AFCP = logic 1, VTUN rises.
Table 8. Frequency Measuring Window Programming
Minimum Tuning Voltage
Both minimum tuning voltage control bits,
VTMll and VTMIO, are at logic 0 after reset.
Further details are given in the DC Electrical
Characteristics table.
NOTE:
1. Values after reset.
FDIVM
PRESCALER DIVISION
FACTOR
CYCLE PERIOD
(ms)
MEASURING WINDOW
(ms)
0
1
256
64
6.4 '
2.56
5.12 '
1.28
trol) are shown in Figure 3, together with the
corresponding data/control bytes. Control is
implemented as follows:
Frequency Measuring Window
The frequency measuring window which is
programmed must correspond with the division factor of the prescaler in use (see
Table 8).
P13, P12, Pl1, Pl0 - Band select outputs. If
a logic 1 is programmed on any of the POD
bits D3 to Do, the relevant output goes HIGH.
All outputs are LOW after reset.
Tuning Direction
Both tuning direction bits, TDIRU (up) and
TDIRD (down), are at logic 0 after reset.
P23, P22, P21, P20 - Open-collector 110
ports. If a logic 0 is programmed on any of the
POD bits D7 to D4 , the relevant output is
forced LOW. All outputs are at logic 1 after
reset (high impedance state).
Control
The instruction bytes POD (port output data)
and DACX (digital-to-analog converter con-
December 2, 1986
DACX - Digital-to-analog converters. The
digital-to-analog converter selected corre-
4-58
sponds to the decimal equivalent of the
DACX bits X2, Xl, XO. The output voltage of
the selected DAC is set by programming the
bits AX5 to AXO; the lowest output voltage is
programmed with all data AX5 to AXO at logic
0, or after reset has been activated.
Read
Information is read from CITAC when the R/
W bit is set to logic 1. An acknowledge must
be generated by the master after each data
byte to allow transmission to continue. If no
acknowledge is generated by the master, the
slave (CITAC) stops transmitting. The format
of the information bytes is shown in Figure 4.
Signetics Linear Products
Product Specification
FLL Tuning and Control Circuit
SAB3035
Tuning/Reset Information Bits
GENERAL CALL ADDRESS
FLOCK - Set to logic 1 when the tuning
oscillator frequency is within the programmed
tuning window.
FL/1N - Set to logic 0 (Active-LOW) when
FLOCK changes from 0 to 1 and is reset to
logic 1 automatically after tuning information
has been read.
FL/ON - As for FL/1 N, but is set to logic 0
when FLOCK changes from 1 to O.
FOV - Indicates frequency overflow. When
the tuner oscillator frequency is too high with
respect to the programmed frequency, FOV is
at logic 1, and when too low, FOV is at logic
O. FOV is not valid when TDIRU and/or
TDIRD are set to logic 1.
RESN - Set to logic 0 (Active-LOW) by a
programmed reset or a power-down reset. It
is reset to logic 1 automatically after tuning/
reset information has been read.
MWN - MWN (frequency measuring window,
Active-LOW) is at logic 1 for a period of
1.28ms, during which time the results of
frequency measurement are processed. This
time is independent of the cycle period.
During the remaining time, MWN is at logic 0
and the received frequency is measured.
When slightly different frequencies are programmed repeatedly and AFC is switched on,
the received frequency can be measured
using FOV and FLOCK. To prevent the frequency counter and frequency buffer being
loaded at the same time, frequency should be
programmed only during the period of
MWN = logic O.
Port Information Bits
P23/1N, P22/1N - Set to logic 0 (ActiveLOW) at a LOW-to-HIGH transition in the
input voltage on P23 and P22, respectively.
Both are reset to logic 1 after the port
information has been read.
P23/0N, P22/0N - As for P23/1 Nand P22/
1N, but are set to logic 0 at a HIGH-to-LOW
transition.
Figure 5, Reset Programming
•
12C BUS TIMING (Figure 6)
12 C bus load conditions are as follows:
4k.l1 pull-up resistor to + 5V; 200pF capacitor to GND.
All values are referred to VIH = 3V and VIL = 1.5V.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
tBUF
Bus free before start
4
j.IS
tsu, tSTA
Start condition setup time
4
1.15
tHD, tSTA
Start condition hold time
4
j.IS
tLOW
SCL, SDA LOW period
4
1.15
tHIGH
SCL HIGH period
4
tR
SCL, SDA rise time
1
j.IS
tF
SCL, SDA fall time
0.3
1.15
tsu, tDAT
Data setup time (write)
1
I.IS
tHD, tDAT
Data hold time (write)
1
I.Is
tsu, tCAC
Acknowledge (from CITAC) setup time
tHD, tCAC
Acknowledge (from CITAC) hold time
0
tsu, tsTO
Stop condition setup time
4
tsu, tRDA
Data setup time (read)
tHD, tRDA
Data hold time (read)
0
j.IS
tsu, tMAC
Acknowledge (from master) setup time
1
I.Is
tHD, tMAC
Acknowledge (from master) hold time
2
I.IS
Reset
4-59
j.IS
I.Is
1.15
2
Timings tsu. tDAT and tHO. tDAT deviate from the 12C bus speCification.
After reset has been activated, transmission may only be started after a 50llS delay.
The programming to reset all registers is
shown in Figure 5. Reset is activated only at
data byte HEX06. Acknowledge is generated
at every byte, provided that CITAC is not in
the power-down reset mode. After the general call address byte, transmission of more
than one data byte is not allowed.
I.IS
2
NOTE:
P123, P121, P120, PI - Indicate input voltage
levels at P23, P22, P21, and P20, respectively. A logic 1 indicates a HIGH input level.
December 2, 1986
HEX06
1.15
Signetics Linear Products
Product Specification
SAB3035
FLL Tuning and Control Circuit
SDA
(WRITE)
sel
SDA
(R~) -------------------+-z~--------+_~F3~----------~~--------~~
Figure 6. 12C Bus Timing SAB3035
December 2, 1986
4-60
Signetics
AN157
Microcomputer Peripheral Ie
Tunes and Controls a TV Set
Application Note
Linear Products
Author: K.H. Seidler
The necessity for television set manufacturers to reduce costs, provide more features,
simplify tuning and incorporate remote control
has led to a need for all-electronic digital
tuning and control circuits. Naturally enough,
component manufacturers would prefer to
meet the need with a dedicated integrated
system which they can make in large quantities. This, however, is impractical because it
would not allow the set manufacturers to
satisfy the widely varying requirements of the
TV market. The most suitable system is
therefore one controlled by a standard microcomputer (e.g., one from the MAB/SCN8400
family), so that the variants can be accommodated by software. The only additional components that then need to be separately
integrated are those required for interfacing
and for performing functions that cannot be
handled by the microcomputer because of
speed, voltage or power consumption considerations. To minimize costs and maximize
performance, however, the partitioning of the
remaining functions and their allocation to
various integrated circuits peripheral to the
microcomputer must be carefully considered.
• Charge pump and 30V tuning-voltage
amplifier
• AFC amplifier
• Logic circuitry for programming the
currents for the charge pump and AFC
amplifier
• Four high-current band switches
• Four general-purpose I/O ports for
additional control functions
• A single-pin crystal-controlled 4MHz
reference oscillator
• Receiving/transmitting logic for the 2wire 12C bus
• Eight static DACs for control of analog
functions associated with the picture
and sound.
FUNCTIONAL DESCRIPTION
12C Bus
The SAB3035 is microcomputer-controlled
via an asynchronous, Inter-IC (l2C) bus. The
bus is a two-wire, bidirectional serial interconnect which allows integrated circuits to communicate with each other and pass control
and data from one IC to another. The communication commences after a start code incorporating an IC address and ceases on receipt
of a stop code. Every byte of transmitted data
must be acknowledged by the IC that receives it. Data to be read must be clocked out
of the IC by the microcomputer. The address
byte includes a control bit which defines the
read/write mode.
o
analog
control
Figure 1 illustrates the control and tuning
functions in a basic TV set, and shows how
the circuitry is positioned within the cabinet.
Some of the functions are concentrated
around the microcomputer and mounted
close to the front panel to reduce the cost of
the wiring to the local keyboard and displays.
The tuning and analog controls are on the
main chassis. The only link between the
microcomputer and the main chassis is a 2wire bidirectional 12C bus which allows the
microcomputer to read tuning status and
other information from the main chassis, and to
write data regarding required frequency and
analog control settings to the main chassis.
The foregoing considerations have led to the
design of the SAB3035 integrated Computer
Interface for Tuning and Analog Control (CITAC). The SAB3035 is an 12C bus-compatible
microcomputer peripheral IC for digital frequency-locked loop (FLL) tuning and control
of analog functions associated with the TV
picture and sound. This is shown in block
form in Figure 2. The IC incorporates a
frequency synthesizer using the charge pump
FLL principle and contains the following circuits:
• 15-bit frequency counter with a
resolution of 50kHz
February 1987
,-----,
L':===~ ~
~
TELETEXT
DECODER
II
I
L- _ _ _ _ ....J
CHASSIS
CONTROL P
___ . infrared
_ tf link
__________
A~L_
remote
ke\ltloard
Figure 1. Basic TV Control System
4-61
•
Application Note
Signetics Linear Products
Microcomputer Peripheral IC Tunes
and Controls a TV Set
AN157
22
AFC+ 11
AFC- 12
18 PIG
19 Pl1
-"0"'5C'+"":..--_-1 REFERENCi COUNTER
OSCILLATOR
,
ZERO DETECTION
TUNiNG CONTROL
15-BIT
TUNING COUNTER
SAB3Q35
Figure 2. Block Diagram of the SAB3035
Frequency Synthesis Tuning
System
Vtuning
Figure 3 is the block diagram of the frequency
synthesizing system comprising a frequency·
locked loop (FLL) and an external prescaler
which divides the frequency of the voltage·
controlled local oscillator in the TV tuner by
64 or 256. The tuning section comprises a 15·
bit programmable frequency counter, a 15·bit
tuning counter, tuning control and zero detec·
tion logic, a reference counter and a charge
pump followed by a low·pass filter amplifier.
15-BIT
TUNING COUNTER
1S-81T
FREQUENCY
COUNTER
Figure 3. Block Diagram of the SAB3035
February 1987
4-62
FDIV Input accepts frequency-divided local
oscillator signals with a level of more than
100mV and a frequency of up to 16MHz. The
frequency measurement period is defined by
passing the internally·amplified signal from
FDIV through a gate which is controlled by
the reference counter. The reference counter
is driven by a crystal·controlled oscillator, the
low level output of which is almost free from
high·order harmonics. This oscillator also
generates the internal clock for the IC. Before
starting the frequency measurement cycle,
the 15 bits of data in the latch register, which
represent the required local oscillator frequency, are loaded into the frequency count·
er. Pulses from the prescaler then decrement
the frequency counter for the duration of the
measurement period.
Application Note
Signetics Linear Products
Microcomputer Peripheral IC Tunes
and Controls a TV Set
AN157
The contents of the frequency counter at the
end of the measurement period indicate
whether or not the frequency of the local
oscillator in the tuner is the same as the
desired frequency, which was preloaded into
the frequency counter. If the frequency counter contents is zero after the measurement
period, a flag (FLOCK), which can be read by
the microcomputer serial bus, is set to indicate that the local-oscillator is correctly
tuned.
A frequency counter contents of other than
zero at the end of the measurement period
indicates that the tuner local oscillator frequency is either too high (contents below
zero) or too low (contents above zero). If it is
too high, an overflow flag which initiates the
"tuning down" function is set. To generate
the tuning voltage correction, the tuning
counter is loaded with the remaining contents
of the frequency counter at the end of the
measurement period, and then decremented
to zero by an internal clock. The duration of
the pulse applied to the charge pump is
proportional to the time taken to decrement
the tuning counter to zero, and therefore also
proportional to the tuning error. The frequency correction has a resolution of 50kHz.
The frequency measurement method of tuning used in the SAB3035 can also be easily
combined with analog AFC to allow tracking
of a drifting transmitter frequency within a
limited range. The required tuning mode (with
or without AFC) is selected and controlled by
software. By not testing some of the LSBs of
the contents of the frequency counter, tune-in
"windows" of ± 100kHz or ± 200kHz can be
defined. The corresponding AFC "windows"
are ± 400kHz or ± 800kHz. The SAB3035 also
contains the AFC control logic and amplifier.
To allow matching to a wide variety of tuners,
the tuning loop gain and tuning speed can be
adjusted over a wide range. To minimize
sound on picture, a "tuning hold" mode is
selectable in which the charge pump and
AFC currents can be reduced when correct
tuning has been achieved.
Bandswitching
The IC also incorporates four 50 mA current
sources with outputs at ports Pl0 to P13 for
executing band switching instructions from
the microcomputer. Bandswitching data is
stored in the data output register. The supply
voltage for the current sources is derived
from a separate input (V CC2) and is therefore
independent of the logic supply voltage
(VCC1)'
February 1987
I
NOTES:
Decreasing frequency (top)
Increasing frequency (bottom)
Figure 4. Using Some of the Selectable Charge Pump Currents
for Making 50kHz Tuning Steps In the UHF Band
I/O Ports
ACKNOWLEDGEMENTS
There are four bidirectional ports P20 to P23
for additional control signals to or from the TV
receiver. Typical examples of these additional
controls are stereo/ dual sound, search tuning
and switching for external video sources. The
output data for ports P20 to P23 is stored in
the port data register.
Special thanks are due to F.A.v.d.Kerkhof
and B.Strassenburg for their contributions,
and to M.F.Geurts for the electrical design of
the SAB3035.
Input data must be present during the read
cycle. Two of the inputs are edge-triggered.
Each input signal transition is stored and can
be read by the microcomputer via the serial
data bus. The stored data is cleared after
each read cycle.
Analog Controls
The SAB3035 includes eight static DACs for
controlling analog functions associated with
the TV picture and sound (volume, tone,
brightness, contrast, color saturation, etc.).
External RC networks are not necessary to
complete the D/ A conversion. The control
data for the DACs is derived from the serial
data bus and stored in eight 6-bit latch
registers. The output voltage range at DACO
to DAC7 is O.5V to 10.5V and can be adjusted
in 64 increments.
4-63
REFERENCES
1. "SAB3035 (CITAC) eine universelle Mikrocoumputer-Pheripherie-IS fur Fernseh-Abstimm-und-Bedienkonzept", Valvo Technical Information 820128.
2. Windsor, B., "Universal-IC fur die Pheripherie", Funkschau 1982, Heft 14.
3. v.d.Kerkhof, FAM., "Microcomputer-controlled tuning and control systems for TV" ,
Electronic Components and Applications,
Vol. 1, No.4, August 1979.
4. "DICS digital tuning system for tv receivers", Philips Techn. Information 024, ordering code 9399 110 32401.
5. "Comprehensive remote control system for
TV", Philips Techn. Information 048, ordering code 9398 034 80011.
6. Seidler, K.H. and von Vignau, R., "Digitales
Abstimm-system", Funkschau, Heft 5,
1976.
Signetics Linear Products
Application Note
Microcomputer Peripheral IC Tunes
and Controls a TV Set
AN157
sound
OAel
OAe3
OACS
OAe7
DACO
DAC2
DAC4
OAC6
ANALOG OUTPUTS 1O,6V to 10,5V)
switch
stop
search
I/O PORTS
Figure 5. This Typical Example of the SAB3035 In a TV Tuning and Control System Shows how the Peripheral
Components Have Been Reduced to Three Capacitors, a Resistor and a 4MHz Crystal
NOTE:
Originally published as Technical Publication 097, Electronic Components and Applications, Vol. 5 No.2, February, 1983, the Netherlands.
February 1987
4-64
SAB3036
Signetics
FLL Tuning and Control Circuit
Product Specification
Linear Products
DESCRIPTION
• 4 high-current outputs for direct
band selection
• Four general purpose Inputl
output (1/0) ports
• Tuning with control of speed and
direction
• Tuning with or without AFC
• Single-pin, 4MHz on-chip
oscillator
• 12C bus slave transceiver
The SAB3036 provides closed-loop digital tuning of TV receivers, with or without
AFC, as required. It also controls 4
general purpose I/O ports and 4 highcurrent outputs for tuner band selection.
The IC is used in conjunction with a
microcomputer from the MAB8400 family and is controlled via a two-wire, bidirectional 12C bus.
FEATURES
PIN CONFIGURATION
N Package
APPLICATIONS
• Combined analog and digital
circuitry minimizes the number of
additional interfacing components
required
• Frequency measurement with
resolution of 50kHz
• Selectable prescaler divisor of 64
or 256
• 32V tuning voltage amplifier
• TV receivers
• Satellite receivers
• CATV converters
TOP VIEW
CCllQ6ClS
PIN NO.
SYMBOL
P20
P21
P22/AFC+
P23/AFCVcc,
TI
GND
TUN
Vcca
ORDERING INFORMATION
DESCRIPTION
} General purpose
Input/output ports
} General purpose Input/ou1put
ports and AFC inputs
+ 12V supply voltage
Tuning VOltage amplifier
Inverting Input
Ground
Tuning voltage amplifier output
+ 32V supply for tuning
voltage amplifier
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
-20·C to + 70·C
SAB3036N
18-Pin Plastic DIP (SOT-l02HE)
10
11
12
13
14
Pl0
Pll
P12
P13
VCC2
15
16
17
18
FDIV
OSC
SOA
SCL
PARAMETER
VCCI
VCC2
VeC3
Supply voltage ranges:
(Pin 5)
(Pin 14)
(Pin 9)
VSOA
VSCL
VP20, P21
VP22, P23, AFC
VTI
VTUN
VP1X
VFOIV
Vose
Input/output voltage ranges:
(Pin 17)
(Pin 18)
(Pins 1 and 2)
(Pins 3 and 4)
(Pin 6)
(Pin 8)
(Pins 10 to 13)
(Pin 15)
(Pin 16)
Positive supply for high-current
band-selection output
ABSOLUTE MAXIMUM RATINGS
SYMBOL
J output
High..u,,"nl band-selection
ports
circuits
RATING
UNIT
-0.3 to +18
-0.3 to +18
-0.3 to +36
V
V
V
-0.3 to +18
-0.3 to +18
-0.3 to +18
-0.3 to VCCI 1
-0.3 10 Vecl 1
-0.3 to VCC3
-0.3 to Vec2 2
-0.3 to Vecl 1
-0.3 to +5
V
V
V
V
V
V
V
V
V
PTOT
Total power dissipation
1000
mW
TSTG
Storage temperature range
-65 to +150
·C
TA
Operating ambient temperature range
-20 to +70
·C
Input from prescaler
Crystal oscinator Input
serial data line
serfal clock line JI'c
bus
NOTES:
1. Pin voltage may exceed supply voltage if current is limited to IOmA.
2. Pin voltage must not exceed 18V but may exceed VCC2 H current is limited to 200mA.
December 2, 1986
4-65
853-1032 86698
Signetics Linear Products
Product Specification
FLL Tuning and Control Circuit
SAB3036
BLOCK DIAGRAM
Yeel
•
_D
':"
fl
~
.---
osc
7
PRESCALER
YCC2
FDrv
'I
vr:
;--"VCCJ
y,.
,S
~Vcc,
I
POWER·DOWN
DETECTOR
SDA
SCL
17
,.
,,<:
OSCILLATOR
3
•
[E]
BUS
READ
-0
~~~R=l11
L..:_:;...J
TIME
-&,;_.:.1
..(P221
"pi221 r p2v. ,
-....1,,;_:..11,,;_:..1
15--BIT
..
r- FOV-'
'FwCi(1
_~a.:._=
•
r- FlI
-,
_...J
TUNING CONTROL CIRCUIT
[!Ell AFal
PORT 2
CONTROL ClnCUIT
~IAFCRI
I
I
DIVJSOR
SELECTOR
12-81T
TUNING COUNTER
I I
~
3-BIT
CAC
I
I
VCC3
I
I
I JUHN I
T
I
CHARGE
PUMP
.
IT
AFC
AJ'C-
TUNING
VOLTAGE
AMPLIFIER
I
AMPLlFlER~
AFCP
AFCS
I
I
4-66
ml!l
I
CIRCUIT
I
CORRECTIONIN-BAND
•
TUN
VCC~
AFe+
December 2, 1986
r
~..
15-BIT
FREQUENCY COUNTER
,.
-mD [P~D ::!i321
[E]
''{
~
'P2t"" ,.pj21'
11
'0
FREQUENCY BUFFER
ffi!l
{!!2] [o>2~
[![]
CD
GATE
I FOrVM I
TUNER
CONTROL
CIRCUIT
~!!l
REFERENCE
COUNTER
,.
,.
PORT 1
SA83036
~
ADC
,
•
[E]
REFERENCE
C 1NT
•
n
~
Signetics Linear Products
Product Specification
SAB3036
FLL Tuning and Control Circuit
DC AND AC ELECTRICAL CHARACTERISTICS TA = 25'C; VCC1, VCC2, VCC3 at typical voltages, unless otherwise
specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
VCC1
VCC2
VCC3
Supply voltages
10.5
4.7
30
12
13
32
13.5
16
35
V
V
V
Icc1
ICC2
ICC3
Supply currents (no outputs loaded)
14
0
0.2
23
40
0.1
2
rnA
rnA
rnA
ICC2A
ICC3A
Additional supply currents (A) 1
IOHP1X
2
rnA
rnA
ProT
Total power dissipation
TA
Operating ambient temperature
0.6
-2
0.2
300
mW
-20
+70
'C
3
VCC1 -1
V
-0.3
1.5
V
12C bus Inputs/outputs SDA input (Pin 17); SCL input (Pin 18)
VIH
Input voltage HIGH 2
VIL
Input voltage LOW
IIH
Input current HIGH 2
10
/lA
IlL
Input current LOW 2
10
IlA
VOL
Output voltage LOW at IOL = 3mA
IOL
Maximum output sink current
SDA output (Pin 17, open-collector)
0.4
V
rnA
5
Open-collector I/O ports P20, P21, P22, P23 (Pins 1 to 4, open-collector)
VIH
Input voltage HIGH (P20, P21)
2
16
VIH
Input voltage HIGH (P22, P23) AFC switched off
2
VCC1- 2
V
VIL
Input voltage LOW
-0.3
0.8
V
V
IIH
Input current HIGH
25
IlA
-IlL
Input current LOW
25
IlA
VOL
Output voltage LOW at IOL
IOL
Maximum output sink current
= 2mA
0.4
4
V
rnA
AFC amplifier Inputs AFC+, AFC- (Pins 3, 4)
900
901
910
911
Transconductance for input voltage up to 1V differential:
AFCS1
AFCS2
0
0
0
1
1
0
1
1
100
15
30
60
250
25
50
100
/lA1V
/lA1V
/lA1V
+20
%
mV
Tolerance of transconductance multiplying factor (2, 4 or 8)
when correction-in-band is used
-20
VIOFF
Input offset voltage
-75
+75
VCOM
Common-mode input voltage
3
VCC1-2.5
CMRR
Common-mode rejection ratio
50
PSRR
Power supply (VCC1) rejection ratio
50
II
Input current (P22 and P23 programmed HIGH)
.:lM g
December 2, 1986
V
dB
dB
500
4-67
nAIV
800
35
70
140
nA
I
Signetics Linear Products
Product Specification
SAB3036
FLL Tuning and Control Circuit
DC AND AC ELECTRICAL CHARACTERISTICS (Continued)
TA = 25"C; VCC1, VCC2, vccs at typical voltages, unless
otherwise specified.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
Tuning voltage amplifier Input TI, output TUN (Pins 6, 8)
= ± 2.5mA
= ± 2.5mA:
VTUN
Maximum output voltage at ILOAD
VTMOO
VTM10
VTMll
Minimum output voltage at ILOAD
VTMll
VTMIO
0
0
1
0
1
1
-ITUNH
Maximum output source current
ITUNL
Maximum output sink current
ITI
Input bias current
PSRR
Power supply (Vccs) rejection ratio
CHoo
CHol
CH 10
CHll
Minimum charge IT to tuning voltage amplifier
TUHNl
TUHNO
0
0
0
1
1
0
1
1
DoCH
ITOO
ITOl
ITlO
ITll
Vccs-l.6
Vccs- O.4
300
450
650
500
650
900
2.5
8
+5
60
0.4
4
15
130
Tolerance of charge (or DoVTUN) multiplying factor when COIB
and lor TUS are used
Maximum current I into tuning amplifier
TUHNl
TUHNO
0
0
0
1
1
0
1
1
1
8
30
250
-20
1.7
15
65
530
3.5
29
110
875
mV
mV
mV
mA
mA
40
-5
V
nA
dB
1.7
14
48
370
pAl/ls
pAl/ls
/lA1/ls
pAl/ls
+20
%
5.1
41
160
1220
/lA
/lA
/lA
/lA
+15
%
Correction-in-band
DoVCIB
Tolerance of correction-in-band levels 12V, 18V and 24V
-15
Band-select output ports Pl0, Pll, P12, P13 (Pins 10 to 13)
VOH
Output voltage HIGH at -IOH
= 50mAs
VOL
Output voltage LOW at IOL = 2mA
-IOH
Maximum output source currentS
IOL
Maximum output sink current
V
VCC2- 0.6
130
0.4
V
200
mA
5
mA
FDIV input (Pin 15)
Input voltage (peak-to-peak value)
(tRISE and tFALL";; 40ns)
0.1
2
V
Duty cycle
40
60
%
fMAX
Maximum input frequency
16
ZI
Input impedance
8
k!l
CI
Input capacitance
5
pF
VFDIV (P-P)
December 2, 1986
4-68
MHz
Product Specification
Signetics Linear Products
FLL Tuning and Control Circuit
SAB3036
DC AND AC ELECTRICAL CHARACTERISTICS (Continued)
TA = 25'C; VCC1, VCC2, VCC3 at typical voltages, unless
otherwise specified.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
OSC Input (Pin 24)
Crystal resistance at resonance (4MHz)
Rx
150
n
9.5
V
Power-down reset
VPD
Maximum supply voltage VCCl at which power-down reset is
active
tR
VCCl rise time during power-up (up to VPD)
7.5
5
jlS
Voltage level for valid module address
Voltage level at P20 (Pin 1) for valid module address as a
function of MA 1, MAO
MA1
MAO
0
0
0
1
1
0
1
1
VVAOO
VVAOl
VVA10
VVAll
-0.3
-0.3
2.5
VCCl -0.3
16
0.8
VCCl- 2
VCCl
V
V
V
V
NOTES:
1. For each band-select output which is programmed at logic 1, sourcing a current IOHP1X, the additional supply currents (A) shown must be added to
ICC2 and lec3, respectively.
2. If Vcc,
< lV, the input current is limited to 10ILA at input voltages up to l6V.
3. At continuous operation the output current should not exceed SOmA. When the output is short-circuited to ground for several seconds the device may
be damaged.
4. Values are proportional to VCC1.
December 2, 1986
4-69
Signetics Linear Products
Product Specification
SAB3036
FLL Tuning and Control Circuit
FUNCTIONAL DESCRIPTION
The SAB3036 is a monolithic computer interface which provides tuning and control functions and operates in conjunction with a
microcomputer via an 12C bus.
Tuning
This is performed using frequency-locked
loop digital control. Data corresponding to the
required tuner frequency is stored in a IS-bit
frequency buffer. The actual tuner frequency,
divided by a factor of 256 (or by 64) by a
prescaler, is applied via a gate to a IS-bit
frequency counter. This input (FDIV) is measured over a period controlled by a time
reference counter and is compared with the
contents of the frequency buffer. The result of
the comparison is used to control the tuning
voltage so that the tuner frequency equals
the contents of the frequency buffer multiplied by 50kHz within a programmable tuning
window (TUW).
The system cycles over a period of 6Ams (or
2.56ms), controlled by the time reference
counter which is clocked by an on-chip 4MHz
reference oscillator. Regulation of the tuning
voltage is performed by a charge pump frequency-locked loop system. The charge IT
flowing into the tuning voltage amplifier is
controlled by the tuning counter, 3-bit DAC
and the charge pump circuil. The charge IT is
linear with the frequency deviation .::If in steps
of 50kHz. For loop gain control, the relationship .::lIT/.::If is programmable. In the normal
mode (when control bits TUHNO and TUHNI
are both at logic I, see OPERATION), the
minimum charge IT at .::If = 50kHz equals
250j.tA j.LS (typical).
By programming the tuning sensitivity bits
(TUS), the charge IT can be doubled up to 6
times. If correction-in-band (COIB) is programmed, the charge can be further doubled
up to three times in relation to the tuning
voltage level. From this, the maximum charge
IT at .::If = 50kHz equals 26 X 23 X 250j.LAj.Ls
(typical).
The maximum tuning current I is 875j.tA
(typical). In the tuning-hold (TUHN) mode
(TUHN is Active-LOW), the tuning current I is
reduced and as a consequence the charge
into the tuning amplifier is also reduced.
An in-lock situation can be detected by reading FLOCK. When the tuner oscillator frequency is within the programmable tuning
window (TUW), FLOCK is set to logic I. If the
frequency is also within the programmable
AFC hold range (AFCR), which always occurs
if AFCR is wider than TUW, control bit AFCT
can be set to logic I. When set, digital tuning
will be switched off, AFC will be switched on
and FLOCK will stay at logic I as long as the
oscillator frequency is within AFCR. If the
frequency of the tuning oscillator does not
remain within AFCR, AFCT is cleared automatically and the system reverts to digital
tuning. To be able to detect this situation, the
occurrence of positive and negative transitions in the FLOCK signal can be read (FL/
I Nand FLlON). AFCT can also be cleared by
programming the AFCT bit to logic o.
The AFC has programmable polarity and
transconductance; the latter can be doubled
up to 3 times, depending on the tuning
voltage level if correction-in-band is used.
The direction of tuning is programmable by
using control bits TDIRD (tuning direction
down) and TDIRU (tuning direction up). If a
tuner enters a region in which oscillation
stops, then, providing the prescaler remains
stable, no FDIV signal is supplied to CITAC. In
this situation the system will tune up, moving
away from frequency lock-in. This situation is
avoided by setting TDIRD which causes the
system to tune down. In normal operation
TDIRD must be cleared.
If a tuner stops oscillating and the prescaler
becomes unstable by going into self-oscillation at a very high frequency, the system will
INSTRUCTION BYTE
MODULE ADDRESS
mob
MA
MA
1
0
LRiW
m.b
msb
Figure 1. 12C Bus Write Format
December 2, 1986
4-70
Setting both TDIRD and TDIRU causes the
digital tuning to be interrupted and AFC to be
switched on.
The minimum tuning voltage which can be
generated during digital tuning is programmable by VTMI to prevent the tuner being driven
into an unspecified low tuning voltage region.
Control
For tuner band selection there are four outputs-PIO to Pl3-which are capable of
sourcing up to SOmA at a voltage drop of less
than 600mV with respect to the separate
power supply input VCC2.
For additional digital control, four open-collector 110 ports - P20 to P23 - are provided. Ports P22 and P23 are capable of detecting positive and negative transitions in their
input signals and are connected with the
AFC+ and AFC- inputs, respectively. The
AFC amplifier must be switched off when P22
and/or P23 are used. When AFC is used, P22
and P23 must be programmed HIGH (high
impedance state). With the aid of port P20, up
to three independent module addresses can
be programmed.
Reset
CITAC goes into the power-down reset mode
when VCC1 is below 8.5V (typical). In this
mode all registers are set to a defined state.
Reset can also be programmed.
OPERATION
Write
CITAC is controlled via a bidirectional twowire 12C bus. For programming, a module
address, R/W bit (logic 0), an instruction byte
and a data/control byte are written into CITAC in the format shown in Figure I.
DATA/CONTROL BYTE
"
"
react by tuning down, moving away from
frequency lock-in. To overcome this, the system can be forced to tune up at the lowest
sensitivity (TUS) value, by setting TDIRU.
Signetics Linear Products
Product Specification
FLL Tuning and Control Circuit
The module address bits MA1, MAO are used
to give a 2-bit module address as a function
of the voltage at port P20 as shown in
Table 1.
SAB3036
Table 1. Valid Module Addresses
MA1
MAO
P20
0
0
1
1
0
1
0
1
Don't care
GND
Y2 VCCI
VCCI
Acknowledge (A) is generated by CITAC only
when a valid address is received and the
device is not in the power-down reset mode
(VCCI > 6.5V (typical».
Tuning
Tuning is controlled by the instruction and
data/control bytes as shown in Figure 2.
Table 2. Tuning Current Control
Frequency
Frequency is set when Bit 17 of the instruction
byte is set to logic 1; the remainder of this
byte together with the data/ control byte are
loaded into the frequency buffer. The frequency to which the tuner oscillator is regulated equals the decimal representation of the
15-bit word multiplied by 50kHz. All frequency
bits are set to logic 1 at reset.
TUHN1
TUHNO
TYP.IMAX
(jLA)
TYP.ITMIN
(1lA/jLs)
TYP. AVTUNmln at CINT = 1jLF
(jLV)
0
0
1
1
0
1
0
1
3.51
29
110
675
11
6
30
250
11
8
30
250
NOTE:
1. Values after reset.
Table 3. Minimum Charge IT as a Function of TUS Af
TUHNO = Logic 1; TUHN1 = Logic 1
Tuning Hold
The TUHN bits. are used to decrease the
maximum tuning current and, as a consequence, the minimum charge IT (at
Af = 50kHz) into the tuning amplifier.
During tuning but before lock-in, the highest
current value should be selected.
After lock-in the current may be reduced to
decrease the tuning voltage ripple.
The lowest current value should not be used
for tuning due to the input bias current of the
tuning voltage amplifier (maximum 5nA).
However, it is good practice to program the
lowest current value during tuner band
switching.
=50kHz;
TUS2
TUS1
TUSO
TYP.ITMIN
(mAIllS)
TYP. AVTuNmln at CINT = 1jLF
(mY)
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0.251
0.5
1
2
4
6
16
0.251
0.5
1
2
4
8
16
NOTE:
1. Values after reset.
Tuning Sensitivity
To be able to program an optimum loop gain,
the charge IT can be programmed by changing T using tuning sensitivity (TUS). Table 3
shows the minimum charge IT obtained by
programming the TUS bits at Af = 50kHz;
TUHNO and TUHN1 = logic 1.
OATAICONTROL BYTE
INSTRUCTION BYTE
17
FREO
TCDI
-
I.
I,
I,
Fl'
Fl'
F12
13
FI1
12
I,
I.
F'O
F9
FB
TCDD
07
D.
03
F.
F.
F7
F6
F5
VTMIO
AFCRI
AFCRO TUHNI
VTMll
COIBI
COIBO
AFCSI
Figure 2. Tuning Control Format
4-71
D.
AFCT
TCD2
December 2, 1966
0,
O2
0,
F2
Fl
TUHNO TUWl
Do
FO
TUWO
AFCSO
TUS2
TUSI
TUSO
AFCP
FDIVM
TDIRD
TDIRU
•
Signetics Linear. Products
Product Specification
FLL Tuning and Control Circuit
Correctlon-In-Band
This control is used to correct the loop gain of
the tuning system to reduce in-band variations due to a non-linear voltage/frequency
characteristic of the tuner. Correction-in-band
(COIB) controls the time T of the charge
equation IT and takes into account the tuning
voltage YTUN to give charge multiplying factors as shown in Table 4.
The transconductance multiplying factor of
the AFC amplifier Is similar when COIB is
used, except for the lowest transconductance
which is not affected.
Tuning Window
Digital tuning is interrupted and FLOCK is set
to logic 1 (in-lock) when the absolute deviation 1At! between the tuner oscillator frequency and the programmed frequency is smaller
than the programmed TUW value (see Table
5). If 1At! Is up to 50kHz above the values
listed in Table 5, it is possible for the system
to be locked depending on the phase relationship between FDIY and the reference
counter.
AFC
When AFCT is set to logic 1 it will not be
cleared and the AFC will remain on as long as
IAII is less than the value programmed for the
AFC hold range AFCR (see Table 6). It is
possible for the AFC to remain on for values
of up to 50kHz more than the programmed
value depending on the phase relationship
between FDIY and the reference counter.
Transconductance
The transconductance (g) of the AFC amplifier Is programmed via the AFC sensitivity bits
AFCS as shown in Table 7.
AFC Polarity
If a positive differential input voltage is applied to the (switched on) AFC amplifier, the
tuning voltage YT1JN falls when the AFC
polarity bit AFCP is at logic 0 (value after
reset). At AFCP - logic 1, YTUN rises.
Minimum Tuning Voltage
Both minimum tuning voltage control bits,
YTMll and YTMIO, are at logic 0 after resel
Further details are given in CHARACTERISTICS.
Frequency Measuring Window
The frequency measuring window which is
programmed must correspond with the division factor of the prescaler in use
(see Table 8).
SAB3036
Table 4. Programming Correction-In-Band
COIBl
COIBO
0
0
1
1
0
1
0
1
< 12V
12 to 18V
18 to 24V
>24V
11
1
1
1
11
1
1
2
11
1
2
4
11
2
4
8
NOTE:
1. Values after reset
Table 5. Tuning Window Programming
TUWl
TUWO
1.1f1 (kHz)
TUNING WINDOW (kHz)
0
0
1
0
1
0
01
50
150
01
100
300
NOTE:
1. Values after reset.
Table 6. AFC Hold Range Programming
AFCRl
AFCRO
0
0
1
0
1
0
IAfl
(kHz)
AFC HOLD RANGE (kHz)
01
350
750
01
700
1500
NOTE:
1. Values after reset.
Table 7. Transconductance Programming
AFCSl
AFCSO
0
0
1
1
0
1
0
1
TYP. TRANSCONDUCTANCE
(MA/~
0.251
25
50
100
NOTE:
1. Yalue after reset.
Table 8. Frequency Measuring WindOW Programming
FDIVM PRESCALER DIVISION FACTOR
0
1
256
64
NOTE:
1. Values after reset.
Tuning Direction
Both tuning direction bits, TDIRU (up) and
TDIRD (down), are at logic 0 after reset.
December 2, 1986
CHARGE MULTIPLYING FACTORS AT TYPICAL
VALUES OF VTUN AT:
4-72
CYCLE PERIOD
(ms)
MEASURING WINDOW
(ms)
6.41
2.56
5.121
1.28
Signettcs Linear Products
Product Specification
FLL Tuning and Control Circuit
SAB3036
Control
AF047DOS
P13, P12, P11, P10 - Band select outputs. If
a logic 1 is programmed on any of the POD
bits D3 to Do, the relevant output goes HIGH.
All outputs are LOW after reset.
Figure 3. Control Programming
FL/ON - As for FL/1N but is set to logic 0
when FLOCK changes from 1 to O.
P23, P22, P21, P20 - Open-collector I/O
ports. If a logic 0 is programmed on any of the
POD bits D7 to D4, the relevant output is
forced LOW. All outputs are at logic 1 after
reset (high impedance state).
FOV - Indicates frequency overflow. When
the tuner oscillator frequency is too high with
respect to the programmed frequency, FOV is
at logic 1, and when too low, FOV is at logic
O. FOV is not valid when TDIRU and/or
TDIRD are set to logic 1.
Read
Information is read from CITAC when the R/W
bit is set to logic 1. An acknowledge must be
generated by the master after each data byte
to allow transmission to continue. If no acknowledge is generated by the master the
slave (CITAC) stops transmitting. The format of
the information bytes is shown in Figure 4.
RESN - Set to logic 0 (Active-LOW) by a
programmed reset or a power-down reset. It
is reset to logic 1 automatically after tuning/
reset information has been read.
MWN - MWN (frequency measuring window,
Active-LOW) is at logic 1 for a period of
1.28ms, during which time the results of
frequency measurement are processed. This
time is independent of the cycle period.
During the remaining time, MWN is at logic 0
and the received frequency is measured.
Tuning/Reset Information Bits
FLOCK - Set to logic 1 when the tuning
oscillator frequency is within the programmed
tuning window.
FLI1N - Set to logic 0 (Active-LOW) when
FLOCK changes from 0 to 1 and is reset to
logic 1 automatically after tuning information
has been read.
When slightly different frequencies are programmed repeatedly and AFC is switched on,
the received frequency can be measured
using FOV and FLOCK. To prevent the frequency counter and frequency buffer being
MODULE ADDRESS
TUNINGIRESET INFORMAnON
s.,
L
S
11 1
0
0
0
MA
1
DATA/CONTROL BYTE
INSTRUCTION BYTE
The instruction byte POD (port output data) is
shown in Figure 3, together with the corresponding data/ control byte. Control is implemented as follows:
~A
1
8&
85
84
B3
82
1
AJ
RJWJ
loaded at the same time, frequency should be
programmed only during the period of
MWN = logic O.
Port Information Bits
P23/1N, P22/1N - Set to logic 0 (ActiveLOW) at a LOW-to-HIGH transition in the
input voltage on P23 and P22, respectively.
Both are reset to logic 1 after the port
information has been read.
P23/0N, P22/DN - As for P23/1N and P22/
1N but are set to logic 0 at a HIGH-to-LOW
transition.
P123, P122, P121, P120 - Indicate input
voltage levels at P23, P22, P21 and P20,
respectively. A logic 1 indicates a HIGH input
level.
Reset
The programming to reset all registers is
shown in Figure 5. Reset is activated only at
date byte HEX06. Acknowledge is generated
at every byte, provided that CITAC is not in
the power-down-reset mode. After the general call address byte, transmission of more
than one data byte is not allowed.
PORT INFORMAnON
81
80
0
o
I I pi
L!::~RO
I 1
A
A
L!:=
MIIASTER
Pl20
Pl21
-FOV
Pl22
FLiON
FLl1N
Pl23
FLOCK
P22IIlN
P22J1 N
FROMCITAC
P23ION
P23I1 N
FROMMASTER
AF04110S
Figure 4. Information Byte Format
GENERAL CALL ADDRESS
HEXOS
-
.....
Figure 5. Reset Programming
December 2, 1986
4-73
•
Signetics Unear Products
Product Specification
SAB3036
FLL Tuning and Control Circuit
12c Bus Timing
12 C bus load condiflons are as follows:
4kn pull-up resistor to
+ 5V; 200pF capacitor to GND.
All values are referred to VIH = 3V and VIL = 1.5V.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
tBUF
Bus free before start
4
lIS
tSU. tSTA
Start condition setup time
4
lIS
tHD. IsTA
Start condition hold time
4
jlS
tLCW
SCl, SDA LOW period
4
jlS
tHIGH
SCL HIGH period
4
tR
SCL. SDA rise time
1
jlS
tF
SCL. SDA fall lime
0.3
jlS
Isu. tOAT
Data setup time (write)
1
tHO. tOAT
Data hold time (write)
1
tsu. tCAC
Acknowledge (from CITAC) setup time
!cAc
jlS
jlS
jlS
2
jlS
Acknowledge (from CITAC) hold time
0
Isu. Isro
Stop condition setup time
4
Isu. tROA
Data setup lime (read)
tHO. tROA
Data hold lime (read)
0
jlS
Isu. !MAC
Acknowledge (from master) setup time
1
jlS
tHO. tMAC
Acknowledge (from master) hold time
2
jlS
tHO.
lIS
jlS
2
jlS
NOTE:
1. Timings Isu. 10AT and tHO. tOAT deviate from the I"C bus specification.
After reset has been activated. transmission may only be started after a 5011S delay.
BOA
(WRITE)
SCL
BOA
(A~) ------------------~~~------1r~~~----------~_r------_r1l
Figure 6_ 12
December 2. 1986
e
Bus Timing SAB3036
4-74
SAB3037
Signetics
FLL Tuning and Control Circuit
Product Specification
Linear Products
DESCRIPTION
The SAB3037 provides closed-loop digital tuning of TV receivers, with or without
AFC, as required. It also controls up to 4
analog functions, 4 general purpose I/O
ports and 4 high-current outputs for
tuner band selection.
The IC is used in conjunction with a
microcomputer from the MAB8400 family and is controlled via a two-wire, bidirectional 12C bus.
FEATURES
• Combined analog and digital
circuitry minimizes the number of
additional interfacing components
required
• Frequency measurement with
resolution of 50kHz
• Selectable prescaler divisor of 64
or 256
co 32V tuning voltage amplifier
• 4 high-current outputs for direct
band selection
• 4 static digital to analog
convertors (DACs) for control of
analog functions
• Four general purpose input/
output (I/O) ports
.. Tuning with control of speed and
direction
.. Tuning with or without AFC
.. Single-pin, 4MHz on-chip
oscillator
.. 12C bus slave transceiver
PIN CONFIGURATION
N Package
APPLICATIONS
.. TV receivers
o Satellite receivers
.. CATV converters
TOP VIEW
CD11970$
PIN NO. SYMBOL
DAC3
SDA
SCL
P20
P21
P22
P23
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
24-Pin Plastic DIP (SOT-101A)
-20°C to + 70°C
SAB3037N
AFC+
10
AFCTI
DESCRIPTION
Output of static DAC
Serial data line
Serial clock line
}
12 C bus
}
General purpose
input/output ports
}
AFC inputs
Tuning voltage amplifier inverting
input
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VCCI
VCC2
VCC3
PARAMETER
Supply voltage ranges:
(Pin 13)
(Pin 19)
(Pin 14)
RATING
UNIT
-0.3 to + 18
-0.3 to + 18
-0.3 to +36
V
V
V
VSDA
VSCL
VP2X
VAFC+. AFCVTI
VTUN
VP1X
VFDIV
Vose
VDACX
Input! output voltage ranges:
(Pin 2)
(Pin 3)
(Pins 4 to 7)
(Pins 8 and 9)
(Pin 10)
(Pin 12)
(Pins 15 to 18)
(Pin 20)
(Pin 21)
(Pins 1 and 22 to 24)
PTOT
Total power dissipation
TSTG
Storage temperature range
TA
Operating ambient temperature range
-20 to +70
°C
-0.3 to +18
-0.3 to +18
-0.3 to +18
-0.3 to VCC1 1
-0.3 to VCC1 1
-0.3 to VCC3 3
-0.3 to Vce2 3
-0.3 to VeC1 1
-0.3 to +5
-0.3 to Vec 1
V
V
V
V
V
V
V
V
V
V
1000
mW
-65 to +150
°C
11
12
13
14
GND
TUN
VCC1
VCC3
15
16
17
18
19
P10
P11
P12
P13
VCC2
20
21
22
23
24
FDIV
OSC
DACO
DAC1
DAC2
Ground
Tuning voltage amplifier output
+ 12V supply voltage
+ 32V supply for tuning voltage
amplifier
}
High-current band-selection output
ports
Positive supply for high-current
band-selection output circuits
Input from prescaler
Crystal oscillator input
}
Outputs of static DACs
NOTES:
1. Pin voltage may exceed supply voltage if current is limited to lOrnA.
2. Pin voltage must not exceed 18V but may exceed VCC2 if current is limited to 200mA.
December 2, 1986
4-75
853-1057 86703
Product Specification
Signetics Linear Products
SAB3037
FLL Tuning and Control Circuit
BLOCK DIAGRAM
f1
CJ
PRESCAI.ER
VC02
FDIV
VCC3
20
VCOl
(ffiJ
SAB3037
I.
17
PORT ,
CONTROL
CIRCUIT
I!EI
.DAo-=t--~
IE]
seL o-=t---I
TUNER
I.
,.
CD
o-,... . . . .
[Pl[J
I
~ill C~!J
cP!!l~!~
o--+<.....-tiJ'ru ~D CP!~
C~v::J U~c]J C~:J
'2
TUNING CONTROL CIRCUIT
1TOI. II AFCT 1
PORT 2
~1'1§J
CONTROL CIRCUIT
@EI
,.
TUN
C INT
,.
AFC+
TI
AFC-
December 2, 1986
4-76
Product Specification
Signetics Linear Products
SAB3037
FLl Tuning and Control Circuit
DC AND AC ELECTRICAL CHARACTERISTICS
TA = 25°C; Vccr, VCC2, VCC3 at typical voltages, unless otherwise
specified.
LIMITS
SYMBOL
UNIT
PARAMETER
VCCl
VCC2
VCC3
Supply voltages
ICCl
ICC2
ICC3
Supply currents (no outputs loaded)
ICC2A
ICC3A
Additional supply currents (A) 1
PTOT
Total power dissipation
TA
Operating ambient temperature
Min
Typ
Max
10.5
4.7
30
12
13
32
13.5
16
35
V
V
V
18
30
0.2
0.6
45
0.1
2
mA
mA
mA
IOHP1X
2
mA
mA
a
-2
0.2
380
mW
-20
+70
°C
3
Vcc-l
V
-0.3
1.5
V
12C bus Inputs/outputs SDA input (Pin 2); SCL input (Pin 3)
VIH
Input voltage HIGH 2
V/L
Input voltage LOW
IIH
Input current HIGH 2
10
pA
Input current LOW2
10
pA
IlL
SDA output (Pin 2, open-collector)
= 3mA
VOL
Output voltage LOW at IOL
IOL
Maximum output sink current
0.4
V
mA
5
Open-collector I/O ports P20, P21, P22, P23 (Pins 4 to 7, open-collector)
VIH
Input voltage HIGH
2
16
V
VIL
Input voltage LOW
-0.3
0.8
V
IIH
Input current HIGH
25
pA
-IlL
Input current LOW
25
p.A
VOL
Output voltage LOW at IOL
IOL
Maximum output sink current
= 2mA
0.4
4
V
mA
AFC amplifier Inputs AFC+, AFC- (Pins 8, 9)
Transconductance for input voltages up to 1V differential:
AFCS2
AFCSl
a
a
gOO
gOl
g10
gll
1
1
a
100
15
30
60
1
a
1
250
25
50
100
Tolerance of transconductance multiplying factor (2, 4 or 8)
when correction-in-band is used
-20
V/OFF
Input offset voltage
-75
VCOM
Common-mode input voltage
CMRR
Common-mode rejection ratio
50
PSRR
Power supply (VCC1) rejection ratio
50
II
Input current
AM g
December 2, 1986
3
800
35
70
140
nAIV
+20
%
+75
mV
VCCl- 2.5
V
dB
dB
500
4-77
pAlV
pAlV
pAlV
nA
I
Product Specification
Signetics linear Products
SAB3037
Fll Tuning and Control Circuit
DC AND AC ELECTRICAL CHARACTERISTICS (Continued)
TA = 25°C; VCC1, VCC2, VCC3 at typical voltages, unless
otherwise specified.
LIMITS
UNIT
PARAMETER
SYMBOL
Min
Typ
Max
Tuning voltage amplifier Input TI, output TUN (Pins 10, 12)
= ± 2.5mA
VCC3-1.6
VTUN
Maximum output voltage at ILOAD
VTMOO
VTM10
VTM11
Minimum output voltage at ILOAD = ± 2.SmA:
VTMII
VTMIO
0
0
1
0
1
1
300
450
650
-ITUNH
Maximum output source current
2.5
ITUNL
Maximum output sink current
ITI
Input bias current
PSRR
Power supply VCC3 rejection ratio
CHoo
CH01
CH10
CH11
Minimum charge IT to tuning voltage amplifier
TUHNI
TUHNO
0
0
0
1
1
0
1
1
8
-5
0.4
4
15
130
+5
1
8
30
250
-20
1.7
15
65
530
3.5
29
110
875
V
mV
mV
mV
mA
mA
60
Maximum current I into luning amplifier
TUHNO
TUHNI
0
0
0
1
1
0
1
1
ITOO
IT01
IT10
IT11
500
650
900
40
Tolerance of charge (or 8.5V (typical».
Tuning
MA1
MAO
P20
0
0
1
1
0
1
0
1
Don't care
GND
Y2 Vee,
Vee,
Table 2. Tuning Current Control
Tuning is controlled by the instruction and
data/control by1es as shown in Figure 2.
Frequency
Frequency is set when Bit 17 of the instruction
by1e is set to logic 1; the remainder of this
bYte together with the data/ control by1e are
loaded into the frequency buffer. The frequency to which the tuner oscillator is regulated equals the decimal representation of the
15-bit word multiplied by 50kHz. All frequency
bits are set to logic 1 at reset.
TUHN1
TUHNO
TYP. IMAX
(f.lA)
TYP.ITMIN
(f.lAlf.ls)
TYP. ilVTUNmln at CINT = 1f.lF
(f.lV)
0
0
1
1
0
1
0
1
3.5'
29
110
875
l'
8
30
250
l'
8
30
250
NOTE:
1. Values after reset.
During tuning but before lock-in, the highest
current value should be selected. After lock-in
the current may be reduced to decrease the
tuning voltage ripple.
Tuning Hold
The TUHN bits are used to decrease the
maximum tuning current and, as a consequence, the minimum charge IT (at
ilf = 50kHz) into the tuning amplifier.
The lowest current value should not be used
for tuning due to the input bias current of the
DATA/CONTROL BYTE
INSTRUCTION BYTE
"
FREC
I,
Fl.
"
"
F13
F12
"
Fll
D,
"
D.
"
'0
D,
FlO
F9
Fa
F7
F6
F5
F'
F3
F2
Fl
FO
AfCT
VTMIO
AFCR1
AFCRO
TUHN1
TUHNO
TUW1
TUWO
VTMI1
COIB1
COIBO
TeD1
TeDD
TCD2
Figure 2. Tuning Control Format
December 2, 1986
tuning voltage amplifier (maximum 5nA).
However, it is good practice to program the
lowest current value during tuner band
switching.
4-81
D,
D,
D,
D,
AFCS1
DO
AFCSO
TUS2
TUS1
TUSO
AFCP
FDIVM
TDIRD
TDIRU
•
Product Specification
Signetics Linear Products
,SAB3037
FlL Tuning and Control Circuit
Table 3. Minimum Charge IT as a Function of TUS Ilf = 50kHz;
TUHNO Logic 1; TUHN1 Logic 1
=
=
TUS2
TUS1
TUSO
TYP.ITMIN
(mAIlls)
TYP. AVTUNmln at CINT = 11lF
(mV)
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0.25 1
0.5
1
2
4
8
16
0.25 1
0.5
1
2
4
8
16
Correction·ln·Band
This control is used to correct the loop gain of
the tuning system to reduce in-band variations due to a non-linear voltage/frequency
characteristic of the tuner. Correction-in-band
(COl B) controls the time T of the charge
equation IT and takes into account the tuning
voltage VTUN to give charge multiplying factors as shown in Table 4.
NOTE:
1. Values after reset.
Table 4. Programming Correction-In-Band
COIB1
0
0
1
1
The transconductance multiplying factor of
the AFC amplifier is similar when COIB is
used, except for the lowest transconductance
which is not affected.
CHARGE MULTIPLYING FACTORS AT
TYPICAL VALUES OF VTUN AT:
COIBO
0
1
0
1
< 12V
12 to 18V
18 to 24V
> 24V
11
1
1
1
11
1
1
2
11
1
2
4
11
2
4
8
NOTE:
1. Values after reset.
Table 5. Tuning Window Programming
TUW1
TUWO
I Af I (kHz)
TUNING WINDOW (kHz)
0
0
1
0
1
0
01
50
150
01
100
300
NOTE:
1. Values after reset.
Table 6. AFC Hold Range Programming
AFCR1
AFCRO
I Af I (kHz)
AFC HOLD RANGE (kHz)
0
0
1
0
1
0
01
350
750
01
700
1500
NOTE:
1. Values after reset.
Table 7. Transconductance Programming
AFCS1
AFCSO
TYP. TRANSCONDUCTANCE (IlAlV)
0
0
1
1
0
1
0
1
0.25 1
25
50
100
NOTE:
1. Values after reset.
December 2, 1986
4-82
Tuning Sensitivity
To be able to program an optimum loop gain,
the charge IT can be programmed by chang·
ing T using tuning sensitivity (TUS). Table 3
shows the minimum charge IT obtained by
programming the TUS bits at Af = 50kHz;
TUHNO and TUHN1 = logic 1.
Tuning Window
Digital tuning is interrupted and FLOCK is set
to logic 1 (in-lock) when the absolute deviation IAfl between the tuner oscillator frequency and the programmed frequency is smaller
than the programmed TUW value (see Table
5). If IAII is up to 50kHz above the values
listed in Table 5, it is possible for the system
to be locked depending on the phase relationship between FDIV and the reference
counter.
AFC
When AFCT is set to logic 1 it will not be
cleared and the AFC will remain on as long as
IAfl is less than the value programmed for the
AFC hold range AFCR (see Table 6). It is
possible for the AFC to remain on for values
of up to 50kHz more than the programmed
value depending on the phase relationship
between FDIV and the reference counter.
Transconductance
The transconductance (9) of the AFC amplifier is programmed via the AFC sensitivity bits
AFCS as shown in Table 7.
Signetics Linear Products
Product Specification
FLL Tuning and Control Circuit
SAB3037
INSTRUCTION BYTE
"
"
"
'.
"
0
1
0
1
OAC~ : :
POO~
DATA/CONTROL BYTE
'2
"
"
0
: : : :
:
II
0
0
XO
X1
0,
0,
0,
D.
0,
O2
0,
P23
P22
P21
P20
P13
P12
P11
AX5
AX_
AX3
AX2
AX1
0,
P10
AXO
I
Figure 3. Control Programming
MODULE ADDRESS
I 1,
s
, ,
,
0
0
, , ,I
RiWJ
MA
PORT INFORMATION
TUNINGIRESET INfORMATION
MA
A
6
B5
B4
B
, , ,
B
B
I
0
m~WN
0
I I I
'I I
A
A
p
l§-
MASTER
Pl20
RESN
PI21
FOV
P.22
FUON
FU1N
PI23
FLOCK
P22I
P221'
FROMCITAC
P23/ON
P2311 N
FROM MASTER
Figure 4. Information Byte Format
AFC Polarity
If a positive differential input voltage is applied to the (switched-on) AFC amplifier, the
tuning voltage VTUN falls when the AFC
polarity bit AFCP is at logic 0 (value after
reset). At AFCP = logic 1, VTUN rises.
Minimum Tuning Voltage
Both minimum tuning voltage control bits,
VTMI1 and VTMIO, are at logic 0 after reset.
Further details are given in the DC Electrical
Characteristics table.
Frequency Measuring Window
The frequency measuring window which is
programmed must correspond with the division factor of the prescaler in use
(see Table 8).
Tuning Direction
Both tuning direction bits, TDIRU (up) and
TDIRD (down), are at logic 0 after reset.
Control
The instruction bytes POD (port output data)
and DACX (digital-to-analog converter con-
December 2, 1986
Table 8. Frequency Measuring Window Programming
FDIVM
PRESCALER DIVISION
FACTOR
CYCLE PERIOD
(ms)
MEASURING WINDOW
(ms)
0
1
256
64
6.4'
2.56
5.12 '
1.28
NOTE:
1. Values after reset.
trol) are shown in Figure 5, together with the
corresponding datal control bytes. Control is
implemented as follows:
P13, P12, P11, P10 - Band select outputs. If
a logic 1 is programmed on any of the POD
bits 0 3 to Do, the relevant output goes High.
All outputs are Low after reset.
P23, P22, P21, P20 - Open-collector 1/0
ports. If a logic 0 is programmed on any of the
POD bits D7 to D4 , the relevant output is
forced LOW. All outputs are at logic 1 after
reset (high impedance state).
DACX - Digital-to-analog converters. The
digital-to-analog converter selected corre-
4-B3
sponds to the decimal equivalent of the
DACX bits X1, XO. The output voltage of the
selected DAC is set by programming the bits
AX5 to AXO; the lowest output voltage is
programmed with all data AX5 to AXO at logic
0, or after reset has been activated.
Read
Information is read from CITAC when the
R/W bit is set to logic 1. An acknowledge
must be generated by the master after each
data byte to allow transmission to continue. If
no acknowledge is generated by the master,
the slave (CITAC) stops transmitting. The
format of the information bytes is shown in
Figure 4.
•
Signetics Linear Products
Product Specification
SAB3037
FLL Tuning and Control Circuit
Tuning/Reset Information Bits
FL/1N - Set to logic 0 (Active-LOW) when
FLOCK changes from 0 to 1 and is reset to
logic 1 automatically after tuning information
has been read.
FL/ON - As for FL/1 N but is set to logic 0
when FLOCK changes from 1 to O.
FOV - Indicates frequency overflow. When
the tuner oscillator frequency is too high with
respect to the programmed frequency. FOV is
at logic 1. and when too low. FOV is at logic
O. FOV is not valid when TDIRU and lor
TDIRD are set to logic 1.
RESN - Set to logic 0 (Active-LOW) by a
programmed reset or a power-down-reset. It
is reset to logic 1 automatically after tuningl
reset information has been read.
MWN - MWN (frequency measuring window.
Active-LOW) is at logic 1 for a period of
1.28ms. during which time the results of
frequency measurement are processed. This
time is independent of the cycle period.
During the remaining time. MWN is at logic 0
and the received frequency is measured.
When slightly different frequencies are programmed repeatedly and AFC is switched on.
the received frequency can be measured
using FOV and FLOCK. To prevent the frequency counter and frequency buffer being
loaded at the same time. frequency should be
programmed only during the period of
MWN = logic O.
Port Information Bits
P23/1N, P22/1N - Set to logic 0 (ActiveLOW) at a LOW-to-HIGH transition in the
input voltage on P23 and P22. respectively.
Both are reset to logic 1 after the port
information has been read.
P23/0N, P22/0N - As for P23/1 Nand P221
1N but are set to logic 0 at a HIGH-to-LOW
transition.
AF04690S
Figure 5. Reset Programming
12C BUS TIMING (Figure 6)
12C bus load conditions are as follows:
4ka pull·up resistor to + 5V; 200pF capacitor to GND.
All values are referred to VIH
= 3V
and VIL
= 1.5V.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
tauF
Bus free before start
4
iJS
tsu. tSTA
Start condition setup time
4
iJS
tHO. tSTA
Start condition hold time
4
iJS
tLOw
SCL. SDA LOW period
4
IlS
tHIGH
SCL HIGH period
4
tR
SCL. SDA rise time
tF
SCL. SDA fall time
tsu. tOAT
Data setup time (write)
1
1
iJS
1
0.3
iJS
IlS
iJS
tHO. tOAT
Data hold time (write)
tsu. tCAc
Acknowledge (from CITAC) setup time
tHO. tCAC
Acknowledge (from CITAC) hold time
0
tsu. tSTO
Stop condition setup time
4
tsu. tROA
Data setup time (read)
tHD. tROA
Data hold time (read)
0
IlS
tsu. tMAC
Acknowledge (from master) setup time
1
IlS
tHO. tMAC
Acknowledge (from master) hold time
2
iJS
Ils
2
iJS
2
1. Timings !SU. tOAT and tHO. tOAT deviate from the 12e bus specification.
After reset has been activated. transmission may only be started after a SOIlS delay.
Reset
The programming to reset all registers is
shown in Figure 5. Reset is activated only at
data byte HEX 06. Acknowledge is generated
at every byte. provided that CITAC is not in
the power-down reset mode. After the general call address byte. transmission of more
than one data byte is not allowed.
4-84
IlS
iJS
NOTE:
P123, P122, P121, PI20 - Indicate input
voltage levels at P23. P22. P21 and P20.
respectively. A logic 1 indicates a HIGH input
level.
December 2. 1986
HEX08
GENERAL CALL ADDRESS
FLOCK - Set to logic 1 when the tuning
oscillator frequency is within the programmed
tuning window.
iJS
Product Specification
Signetlcs Linear Products
SAB3037
FLL Tuning and Control Circuit
SDA
(WRITE)
•
SCL
SDA
(READ)
Figure 6. 12 C Bus Timing SAB3037
December 2, 1986
4·85
TDA8400
Signetics
FLL Tuning Circuit With
Prescaler
Product Specification
Linear Products
DESCRIPTION
FEATURES
The TDA8400 provides closed-loop digital tuning of TV receivers, with or without
AFC, as required. It comprises a 1.1 GHz
prescaler, with the divide-by-64 ratio,
which drives a tuning interface providing
a tuning voltage of 33V (maximum) via
an external output transistor. The
TDA8400 can also drive external PNP
transistors to provide 4 high-current outputs for tuner band selection.
• Combined analog and digital
circuitry minimizes the number of
additional interfacing components
required
• Frequency measurement with
resolution of 50kHz
• On-chip prescaler
• Tuning voltage amplifier
• 4 high-current outputs for direct
band selection
• Tuning with control of speed
• Tuning with or without AFC
• Single-pin, 4MHz, on-Chip
oscillator
• 12C bus slave transceiver
The IC can be used in conjunction with a
microcomputer from the MAB8400 family and is controlled via a two-wire, bidirectional 12C bus.
PIN CONFIGURATION
APPLICATIONS
N Package
TOP VIEW
~~
1
2
3
PO
SCL
SDA
TUN
TI
18-Pin DIP (SOT -1 02 HE, KE)
o to
Vccs
Vccp
VN
PARAMETER
Supply voltage:
(Pin 10)
(Pin 15)
13
14
AFC+
OUP
Vccp
17
veo+
veo-
Output from presealer (test)
+ 5V supply voltage (prescaler)2
TDA8400N
15
16
18
GND
Ground
RATING
UNIT
6
6
6
V
V
V
350
mW
Storage temperature range
-65 to + 150
"C
Operating ambient temperature range
-10 to +80
"C
Input/output voltage (each pin)
PTOT
Total power dissipation
TSTG
TA
February 12,1987
Serial clock line) [2C bus
Serial data tine
Tuning voltage amplifier output
Tuning voltage amplifier inverting
input
+ 5V supply voltage (synthesizer)
Crystal oscillator input
ORDER CODE
ABSOLUTE MAXIMUM RATINGS
SYMBOL
High-current band-selection
output ports
ose
70"C
4-86
Vccs
DESCRIPTION
Input synthesizer (test)1
10
11
12
ORDERING INFORMATION
TEMPERATURE RANGE
INS
P3
P2
Pl
• TV receivers
• Satellite receivers
• CATV converters
DESCRIPTION
SYMBOL
AFC-
AFC amplifier inputs
Inputs to prescaler
NOTES:
1. Connected to ground for application.
2. Left open-circuit for application.
853-117487583
Signetics Linear Products
Product Specification
TDA8400
FLL Tuning Circuit With Prescaler
BLOCK DIAGRAM
Vccs
II
[=:l4MHz
vco-
VCo.
l' esc
16
17
15
•
TDA8400
14
t-------;:::::::::::::~--------~~-ooup
SDA
CD
0--'-+__.....
15·81T
FREQUENCY BUFFER
SCL 0 - , - - 1
+-------------~----------------_1r_-oONS
BANOSWITCHES
... 12V
p,
P3
rE>lJ
1E~!g)
I AFCTI
I AFCF
rICl
TUNING CONTROL CIRCUIT
PORT
CONTROL CIRCUIT
I
rmm
3DV
12-81T
TUNING COUNTER
AFC+0-~13~--------------------------------------------~~--i
AFC_o-~I'~------------------------------------------~~~~
February 12, 1987
4-87
TO
"rUN
Signetics Linear Products
Product Specification
TDA8400
FLL Tuning Circuit With Prescaler
DC ELECTRICAL CHARACTERISTICS TA = 25·C; vccs, VccP at typical voltages, unless otherwise specified.
LIMITS
PARAMETER
SYMBOL
Vccs
VccP
Supply voltage
Synthesizer (Pin 10)
Prescaler (Pin 15)
Iccs
Iccp
Supply current
Synthesizer (Pin 10)
Prescaler (Pin 15)
UNIT
Min
Typ
Max
4.5
4.5
5
5
5.5
5.5
12
43
V
V
rnA
rnA
PTOT
Total power dissipation
TA
Operating ambient temperature range
0
+70
·C
TSTG
Operating storage temperature range
-10
+85
·C
V
mW
275
12C bus Inputs/outputs Inputs: SDA (Pin 7); SCl (Pin 6)
VIH
Input voltage HIGH
3.1
5.5
VIL
Input voltage lOW
-0.3
1.6
V
IIH
Input current HIGH
10
pA
Input current LOW
10
pA
IlL
SDA output (Pin 7, open-collector)
VOL
Output voltage LOW at IOL = 3mA
IOL
Output sink current
0.4
V
5
rnA
+5
nA
Tuning voltage amplifier Input TI, output TUN (Pins 9, 8)
ITI
Input bias current
-5
-ITUNL
Output current LOW at VTUN = O.4V
20
CHo
CHI
Minimum charge IT to tuning amplifier
TUHN=O
TUHN= 1
5
125
pAops
pAops
Maximum current I into tuning amplHier
TUHN=O
TUHN= 1
18
440
pA
pA
ITO
1T1
pA
AFC amplifier (Inputs AFC+, AFC- Pins 13, 12)
VOIF
Differential input voltage
1
V
5
10
15
pAN
50
70
pAN
gl
Transconductance at AFCS = 1
90
Transconductance at AFCS - 0
30
VCM
Common mode input voltage
2.5
CMRR
Common mode rejection ratio
50
PSRR
Power supply (VCCl) rejection ratio
50
II
Input current
VCC1- 1
V
dB
dB
1
pA
1.2
10
rnA
pA
Main band-selection output ports PO, PI, P2, P3 (Pins 5 to 2, open-collector)
lasLl
lasHl
Output sink current
LOW impedance
HIGH impedance
February 12, 1987
0.8
4-88
1
Signetics Linear Products
Product Speclflcatlon
TDA8400
FLL Tuning Circuit With Prescaler
DC ELECTRICAL CHARACTERISTICS (Continued) TA = 25°C; Vccs, VccP at typical voltages, unless otherwise specified.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
Presealer Inputs (VCO+ Pin 16; VCO- Pin 17)
VI(RMS)
VI(RMS)
VI(RMS)
VI(RMS)
VI(RMS)
VI(RMS)
Input differential voltage (RMS value)
at f=70MHz
at f= 150MHz
at f= 300M Hz
at f= 500MHz
at f=900MHz
atf=1.1GHz
17.5
10
10
10
10
25
200
200
200
200
200
200
mV
mV
mV
mV
mV
mV
fl
Input frequency
0.07
1.1
GHz
150
n
4
V
OSC Input (Pin 11)
RXTAL
Crystal resistance at resonance (4MHz)
Power-down reset
VPD
Maximum supply voltage VCC 1 at which power-down reset is
active
3
Voltage level for valid module address
Voltage level PO (Pin 5) for valid module address as a function
of MA1, MAO
VVA01
VVA10
VVA11
MA1
MAO
0
0
1
1
0
1
0
1
FUNCTIONAL DESCRIPTION
Prescaler
The integrated prescaler has a divide-by-64
ratio with a maximum input frequency of
1.1 GHz. It will oscillate in the absence of an
input Signal within the frequency range of
800MHz to 1.1GHz.
Tuning
This is performed using frequency-locked loop
digital control. Data corresponding to the required tuner frequency is stored in the 15-bit
frequency buffer. The actual tuner· frequency
(1.1 GHz maximum) is applied to the circuit on
the two complementary inputs VCO+ and
VCO- which drive the integrated prescaler.
The resulting frequency (FDIV) is measured
over a period controlled by a time reference
counter and fed via a gate to a 15-bit frequency counter where it is compared to the contents of the frequency buffer. The result of the
comparison is used to control the tuning
voltage so that the tuner frequency equals the
contents of the frequency buffer multiplied by
50kHz within a programmable tuning window
(TUW).
The system cycles over a period of 2.56ms,
controlled by the time reference counter which
is clocked by an on-chip 4MHz reference
oscillator. Regulation of the tuning voltage is
performed by a charge pump frequencyFebruary 12, 1987
I
-':'r r"
2.4
Vccs-0.3
locked loop system. The charge IT flowing into
the tuning voltage amplifier (external capacitance CINT = 0.5/lF) is controlled by the tuning
counter, 3-bit DAC, and the charge pump
circuit. The charge IT is linear with the frequency deviation af in steps of 50kHz. For
loop gain control, the relationship alTI af is
programmable. In the normal mode (control bit
TUHN = logic 1; see Table 2) the minimum
charge IT at af = 50kHz equals 125/lA'/ls
(typ.).
By programming the tuning sensitivity bits
(TUS; see Table 3) the charge IT can be
doubled up to 6 times. From this, the maximum charge IT at af = 50kHz equals
26 X 125/lA'/lS (typ.). The maximum tuning
current I is 440/lA, while T is limited to the
duration of the tuning cycle (2.56ms).
In the tuning-hold mode (TUHN = logic 0) the
tuning current I is reduced, and, as a consequence, the charge into the tuning amplifier is
also reduced. An in-lock situation can be
detected by reading FLOCK. The TDAB400
can be programmed to tune in the digital mode
or the AFC mode by setting AFCF. In the
digital mode (AFCF = logiC 0), the tuning window is programmable through the TUW flag.
When the tuner oscillator frequency is within
the programmable tuning window (TUW),
FLOCK is set to logic 1.
4-89
I
UM
Vccs-1.6
Vccs
V
V
V
In the AFC mode, FLOCK will remain at logic 1
provided the tuner frequency is within a
± 800kHz hold range. Switching from digital
mode to AFC mode is determined by the
microcontroller (AFCF flag). Switching from
AFC mode to digital mode can be determined
by the microcontroller, but if the frequency of
the tuning oscillator does not remain within the
hold range, the system automatically reverts
to digital tuning. Switching back to the AFC
mode will then have to be effected externally
again. The tuning mode can be checked by
reading the AFCT flag.
The occurence of positive and negative transitions in the FLOCK signal can be read by FLI
1Nand FL/ON. The AFC amplifier has programmable transconductance to 2 predefined
values.
Control
For tuner band selection there are four output
ports, PO to P3, which are capable of driving
external PNP transistors (open collector) as
current sources. Output port PO can also be
used as valid address input with an active
level determined by module address bits MAO
and MA1.
Reset
The TDA8400 goes into the power-down reset
mode when VCC1 is below 3V (typ.). In this
mode all registers are set to a defined state.
•
Signetics Linear Products
Product Specification
TDA8400
FLL Tuning Circuit With Prescaler
INSTRUCTIDN BYTE
MODULE ADDRESS
MA
S
MA
l
MBB
A
17
I.
I,
Is
I_
I.
DATA/CONTRDL BYTE
I,
A
I.
D7 D.
Ds D,
D_
D_
IISB
IISB
RiW
Figure 1. 12C Bus Write Format
DATA/CONTROL BYTE
INSTRUCTION BYTE
17
FREQ
TCDO
TCDl
0
TEST
0
-
I.
Is
I,
I-
I_
I,
I.
D7
D.
Ds
D,
D_
D_
D,
D.
F14
F13
F12
Fll
FlO
F9
F8
F7
F6
F5
F4
F3
F2
Fl
FO
TUW
AFCS
AFCF
TUHN
TUS2
TUSl
TUSO
P3
P2
Pl
PO
0
0
0
0
0
0
AF04720S
Figure 2. Tuning Control Format
OPERATION
Write
Table 2. Tuning Current Control
The TDA8400 is controlled via a bidirectional
two·wire 12C bus; additional information on the
12 C bus is available on request.
For programming. a module address, A/Vi bit
(logic 0), an instruction byte, and a datal
control byte are written into the device in the
format shown in Figure 1.
The module address bits MAl, MAO are used to
give a 2·bit module address as a function of the
voltage at port input PO as shown in Table 1.
Table 1. Valid Module Addresses
PO
Don't care
GND
1t2 Vees
Vees
MAt
MAO
0
0
1
1
0
1
0
1
Acknowledge (A) is generated by the TDA8400
only when a valid address is received and the
device is not in the power-down reset mode.
Tuning
Tuning is controlled by the instruction and
datal control bytes as shown in Figure 2.
Frequency
Frequency is set when Bit 17 of the inst,ruction
byte is set to logic 1; the remaining bits of this
byte are processed as being data. Instruction
bytes are fully decoded. All frequency bits are
set to logic 1 and control bits to logic 0 at reset.
The test instruction byte cannot be used for
any other purpose.
February 12, 1987
TUHN
TYP.IMAX
(IIA)
TYP.ITMIN
0
1
181
440
5'
125
(1IAIps)
NOTE:
1. Values after reset.
Tuning Hold
The TUHN bit is used to decrease the maxi·
mum tuning current (I) and, as a consequence,
the minimum charge IT (at Ll.f = 50kHz) into the
tuning amplifier.
Tuning Sensitivity
To be able to program an optimum loop gain,
the charge IT can be programmed by changing
T using tuning sensitivity (TUS). Table 3 shows
the minimum charge IT obtained by programming the TUS bits at Ll.f = 50kHz; TUHN =
logiC 1.
Table 3. Minimum Charge IT as
a Function of TUS
TUS2
TUS1
TUSO
TYP.
ITMIN
(mA'ps)
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0.125
0.25
0.5
1
2
4
8
NOTE:
The minimum tuning pulse is 2p.s.
4-90
Tuning Mode
AFCF determines whether the TDA8400 has to
tune in the digital mode or the AFC mode as
shown in Table 4.
Table 4. Selection of Tuning
Mode as a Function of
AFCF
AFCF
TUNING MODE
0
1
Digital
AFC
If the tuner oscillator frequency comes out of
the hold range when in the AFC mode, the
device will automatically switch to digital tuning
and AFCF is reset to logic O.
Tuning Window
In the digital tuning mode TUW determines the
tuning window (see Table 5) and the device is
said to be in the "in-lock" situation.
Table 5. Tuning Window
Programming
TUW
TUNING WINDOW (kHz)
0
1
0
±200
Signetics Linear Products
Product Specification
TDA8400
FLL Tuning Circuit With Prescaler
Transconductance
The transconductance (g) of the AFC amplifier is programmed via the AFC sensitivity bit
AFCS as shown in Table 6.
Table 6. Transconductance
Programming
AFCS
TYP. TRANSCONDUCTANCE
().lA/V)
1
0
10
50
PNP transistor will conduct and the relevant
output goes LOW. All outputs are HIGH after
reset.
Read
Information is read from the TDA8400 when
the R/W bit is set to logic 1. Only one
information byte is sent from the device. No
acknowledge is required from the master
after transmitting. The format of the information byte is shown in Figure 3.
Tuning/Reset Information Bits
Band Selection Control Ports
(PX)
For band selection control, there are four
output ports, PO to P3, which are capable of
driving external PNP transistors (open collector) as current sources. If a logic 1 is programmed on any of the PX bits PO to P3, the
FLOCK - Set to logic 1 when the tuning
oscillator frequency is within the programmed
tuning window (TUW) in the digital tuning
mode, or within the ± 800kHz AFC hold range
in the AFC mode.
FL/1N - Set to logic 0 (Active-LOW) when
FLOCK changes from 0 to 1 and is reset to
logic 1 automatically after tuning information
has been read.
FL/ON - Same as for FLl1 N but it is set to
logic 0 when FLOCK changes from 1 to O.
FOV - Indicates frequency overflow. When
the tuner oscillator frequency is too high with
respect to the programmed frequency, FOV is
at logic 1, and, when too low, FOV is at logic
O.
RESN - Set to logic 0 (active Low) by a
power-down reset. It is reset to logic 1
automatically after tuning/reset information
has been read.
MWN - MWN (frequency measuring window,
Active-LOW) is at logic 1 for a period of
1.28ms, during which time the results of
frequency measurement are processed. During the remaining time, MWN is at logic 0 and
the received frequency is measured.
AFCT - AFCT (tuning mode flag) is set to
logic 1 when the TDA8400 is in AFC mode
and reset to logic 0 when in the digital mode.
TUNING/RESET INFORMATION
MOOULE ADDRESS
MAMA11AI
I
I
tJ:::=
~
~FOV
FWDN
L----------FW1N
L------------FLOCK
L--------------FROMTDAMOO
Figure 3. Information Byte Format
February 12, 1987
4-91
•
SAB1164/65
Signetics
1GHz Divide-by-64 Prescaler
Product Specification
Linear Products
DESCRIPTION
FEATURES
This silicon monolithic integrated circuit
is a prescaler in current-mode logic. It
contains an amplifier, a divide-by-64
scaler and an output stage. It has been
designed to be driven by a sinusoidal
signal from the local oscillator of a
television tuner, with frequencies from
70MHz up to 1GHz, for a supply voltage
of 5V ± 10% and an ambient temperature of 0 to 70'C. It features a high
sensitivity and low harmonic contents of
the output signal.
• 3mV (typ) sensitivity
• Differential inputs
• AC Input coupling; Internally
based
• Outputs edge·controlled for low
RFI
• Power consumption: 210mW (typ)
• Minl·DIP package
• Low output impedance (SAB1165)
PIN CONFIGURATION
IC08VCC
C12
TQL
C2
3
8 QH
VEE
4
TOP
VIEW
5
VEE
APPLICATIONS
• PLL or FLL tuning systems, FM/
communications/TV
• Frequency counters
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
8-Pin Plastic DIP (SOT-97A)
o to
+70'C
SAB1164N
8-Pin Plastic DIP (SOT-97A)
o to
+70'C
SAB1165N
BLOCK DIAGRAM
Vee
8
I
C1
C2
0-2.
o---!.
[>
r--
c
I
Q
f--
+64
r--(j'
Qf--
I
I
4
[> r-.!....o
r-.!-..o
5
NOTE:
Divide-by·64 = 6 binary dividers
December 2, 1986
4·92
853-1026 86699
Signetics Linear Products
Product Speclficotion
1GHz Divide-by-64 Prescaler
SAB1164/65
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
Vee
Supply voltage (DC)
VI
Input voltage
RATING
7
a to
UNIT
V
Vee
V
TSTG
Storage temperature range
-65 to + 125
'C
TJ
Junction temperature
125
'C
eeA
Thermal resistance from crystal to
ambient
120
'C/W
DC ELECTRICAL CHARACTERISTICS VEE = OV (ground); Vee = 5V; TA = 25'C, unless otherwise specified.
The circuit has been designed to meet the DC specifications as shown below, after thermal equilibrium has been established. The circuit is in a
test socket or mounted on a printed-circuit board.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
VOH
VOL
Output voltage
HIGH level
LOW level
Icc
Supply current
Typ
42
Max
Vee
Vee- O.B
V
V
50
mA
AC ELECTRICAL CHARACTERISTICS VEE = OV (ground); Vee = 5V± 10%; TA = a to + 70'C
LIMITS
SYMBOL
PARAMETER
UNIT
Min
VI(RMS)
Input voltage RMS value (see Figure 2)
input frequency 70MHz
150MHz
300MHz
500MHz
900MHz
lGHz
Typ
Max
9
4
3
3
2
3
17.5
10
10
10
10
17.5
mV
mV
mV
mV
mV
mV
200
mV
VI(RMS)
Input overload voltage RMS value
input frequency range 70MHz up to lGHz
VO(P-P)
Output voltage swing
Ro
Ro
Output resistance
SAB1164
SAB1165
tJ.Vo
Output unbalance
tTLH
Output rise time 1
f l = lGHz
25
ns
tTHL
Output fall time 1
fl= lGHz
25
ns
O.B
1
V
1
0.5
kn
kn
0.1
V
NOTE:
1. Between 10% and 90% of observed waveform.
FUNCTIONAL DESCRIPTION
The circuit contains an amplifier, a divide-by64 scaler and an output stage. It has been
designed to be driven by a sinusoidal signal
from the local oscillator of a TV tuner, with
frequencies from 70MHz up to 1GHz, for a
supply voltage of 5V ± 10% and an ambient
temperature of a to + 70'C.
December 2, 19B6
The inputs are differential and are internally
biased to permit capacitive coupling. For
asymmetrical drive the unused input should
be connected to ground via a capacitor.
The output differential stage has two complementary outputs. The output voltage edges
are slowed down internally to reduce the
harmonic contents of the signal.
The first divider stage will oscillate in the
absence of an input signal; an input signal
within the specified range will suppress this
oscillation.
Wide, low-impedance ground connections
and a short capacitive bypass from the Vee
pin to ground are recommended.
4·93
•
Product Specification
Signetics Linear Products
SAB1164j65
1GHz Divide-by-64 Prescaler
HYBRID JUNCTION
1000
r----Di~V)
+
}
~SClLLDSCOPE
50
GUARANTEED
OPERATING AREA
10
4,5
t-----------------------~----~------~v~~ov
1
500
'"
I
1200
',(MHz)
NOTES:
Cables must be son coaxial.
The capacitors are leadless ceramic (multilayer capacitors) of 10nF.
All connections to the device and to the meier must be kept short and 01 approximately equal lengths.
Hybrid junction is ANZAC H·183·4 or similar.
Figure 1. Test Circuit for Defining Input Voltage
December 2, 1986
o
4-94
Figure 2. Typical Sensitivity Curve
Under Nominal Conditions
Signetics Linear Products
Product Specification
SAB1164j65
1GHz Divide-by-64 Prescaler
•
NOTE:
VI(RMS) = 25mV: Vee"" 5V; reference value"" son.
Figure 3. Smith Chart of Typical Input Impedance
December 2, 1986
4-95
Signetics Unear Products
Product Specification
1GHz Divide-by-64 Prescaler
SAB1164/65
1k
1k
}~VlDER8
DI~I
+-________~____~
~3__
n..--+--c
LI"--I----+-....J
"""'OS
NOTES:
1. SABl164: Rl-R2-1kSl; 1-1rnA
2. SAB1165: R1-R2-0.5kll; 1-2mA
3. Vcc-5V
FIgure 4. Input Stage
Figure 5. Output Stage
>fOnH
,......,..
t
Vcc·SY
±U7"F
fOnF
8
:~)
fOnF
2
8
~~~
7
Q
I
110TUNINQ
SYSI'EM
rr
~
(lWISI"ED LEADS)
v.. =ov
Te''''''
NOTE:
TV tuning system. The output peak-to-peak YOItage is about
w.
Figure 6. Circuit Diagram
December 2, 1986
4-96
SAB1256
Signetics
1GHz Divide-by-256 Prescaler
Product Specification
Linear Products
PIN CONFIGURATION
DESCRIPTION
FEATURES
This silicon monolithic integrated circuit
is a prescaler in current-mode logic. It
contains an amplifier, a divide-by-256
scaler and an output stage. It has been
designed to be driven by a sinusoidal
signal from the local oscillator of a
television tuner, with frequencies from
70MHz up to 1GHz, for a supply voltage
of 5V± 10% and an ambient temperature
of 0 to 70·C. It features a high sensitivity
and low harmonic contents of the output
signal.
• 3mV (typ.) sensitivity
• AC Input coupling, Internally
biased
• Outputs edge-controlled for low
RFI
• 235mV typical power dissipation
• Low output Impedance"'1kU
N Package
IC08VCC
C12
7QL
C23
80t!
VEE
4
5
VEE
TOP VIEW
APPLICATIONS
• PLL or FLL tuning systems,
FM/communicatlons/TV
• Frequency counters
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
o to
8-Pin Plastic DIP (SOT-97)
ORDER CODE
70·e
SAB1256N
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
Vee
Supply voltage (DC)
VI
Input voltage
UNIT
RATING
7
V
o to Vee
V
-65 to +150
TSTG
Storage temperature range
TJ
Junction temperature
125
·e
·e
OCA
Thermal resistance from crystal to
ambient
120
·e/w
BLOCK DIAGRAM
Vee
8
I
C1
C2
o---!
o--!
[>
I
Qr--
-c
+256
UI--
-"C"
.!....o
~
I
I
4
[>
5
Boo79508
NOTE:
Oivide-by-256 - 8 binary dividers.
December 2, 1986
4-97
853-1052 86702
•
Signetics Linear Products
Product Specification
1GHz Divide-by-256 Prescaler
SAB1256
DC ELECTRICAL CHARACTERISTICS VEE = OV (ground); Vce = 5V; TA = 25°C, unless otherwise specified. The circuit has
been designed to meet the DC specifications as shown below, after thermal
equilibrium has been established. The circuit is in a test socket or mounted on a
printed-circuit board.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
VOH
Typ
Output voltage
HIGH level
VOL
LOW level
lee
Supply current
Max
Vee
47
V
Vee- O.B
V
55
mA
AC ELECTRICAL CHARACTERISTICS VEE=OV (ground); Vee=5V±10%; TA=ooe to +70 oe.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
VI(RMS)
Input voltage RMS value (see Figure 2)
Input Irequency 70MHz
150MHz
300MHz
500MHz
900MHz
1GHz
Typ
Max
9
4
3
3
2
3
17.5
10
10
10
10
17.5
mV
mV
mV
mV
mV
mV
200
mV
VI(RMS)
Input overload voltage RMS value
input Irequency range 70MHz to 1GHz
Vo(P-P)
Output voltage swing
Ro
Output resistance
f!,vo
Output unbalance
tTLH
Output rise time 1
II = 1GHz
40
ns
tTHL
Output lall time
II = 1GHz
40
ns
O.B
1
V
1
kst
0.1
V
NOTE:
1. Between 10% and 90% of observed waveform.
FUNCTIONAL DESCRIPTION
The circuit contains an amplifier, a divide-by256 scaler and an output stage. It has been
designed to be driven by a sinusoidal signal
from the local oscillator of a TV tuner, with
frequencies from 70MHz up to 1GHz, for a
supply voltage of 5V ± 10% and an ambient
temperature of 0 to 70°C.
December 2, 1986
The inputs are differential and are internally
biased to permit capacitive coupling. For
asymmetrical drive the unused input should
be connected to ground via a capacitor.
The output differential stage has two complementary outputs. The output voltage edges
are slowed down internally to reduce the
harmonic contents of the signal.
The first divider stage will oscillate in the
absence of an input signal; an input signal
within the specified range will suppress this
oscillation.
Wide, low-impedance ground connections
and a short capacitive bypass from the Vee
pin to ground are recommended.
4-98
Signetics Linear Products
Product Specification
1GHz Divide-by-256 Prescaler
SAB1256
HYBRID JUNcnON
}
~SCIL1DSCOPE
50
"5
t---------------------~----~------Oy~.Oy
NOTES:
Cables must be 50n coaxial.
The capacitors are Isadless ceramic (multi-layer capacitors) of 10nF.
All connections to the device and to the meter must be kept short and of approximately equal lengths.
Hybrid junction is ANZAC H-183-4 or similar.
Figure 1. Test Circuit for Defining Input Voltage
1000
~ 100
.5.
i
>"
I- GUARANTEED
I=~P~~IN~ AREA
10
1
I
I I
o
"
I
1200
Figure 2. Typical Sensitivity Curve
Under Nominal Conditions
December 2, 1986
4-99
Product Specification
Signetics Unear Products
SAB1256
1GHz Divide-by-256 Prescaler
NOTE:
VI(RMS) - 25mVj Vee "" 5V; reference value" son
Figure 3. SmIth Chart of TypIcal Input Impedance
December 2. 1986
4-100
Product Specification
Signetics Linear Products
SAB1256
1GHz Divide-by-256 Prescaler
1k
}
DIFFERENTIAL
INPUTS
I
2k
I
~VIDERS
2k
3
--~---------r--~
JL-+-!..
u--+--t------'
' - - - -....-----t.:....-oVEE
NOTE:
Vee = 5V; I"" 1mA.
Figure 5. Output Stage
Figure 4. Input Stage
>1OnH
.--~---frr~--~~----~~VCC=5V
:;r:10nF
10nF
~~~ )r--Qt__-l--il
I
TOTUNING
SYSrEM
10nF
t---
(TWISTED LEADS)
+-------------.....- -.....------0 VEE=OV
NOTE:
Application in a television tuning system. The output
peak~to·peak
voltage is about 1V.
Figure 6. Circuit Diagram
December 2, 1986
4-101
TDA5030A
Signetics
VHF MixerjOsciliator Circuit
Product Specification
Linear Products
DESCRIPTION
FEATURES
The TDA5030A performs the VHF mixer,
VHF oscillator, SAW filter IF amplifier,
and UHF IF amplifier functions in television tuners.
• A balanced VHF mixer
• An amplitude-controlled VHF
local oscillator
• A surface acoustic wave filter IF
amplifier
• A UHF IF preamplifier
• A buffer stage for driving an
external prescaler with the local
oscillator signal
PIN CONFIGURATIONS
• A voltage stabilizer
• A UHF/VHF switching circuit
N Package
DECOUP
1
VHF INPUT 2
1
DECOUP
MIX/IF PREAMP
(UHF) OUTPUT
MIX/IF PREAMP
12 SWITCH INPUT
(UHF) OUTPUT
IFAMP
INPUT
IF AMP
INPUT
11
g:~~~
10
~tA~~T
TOP VIEW
APPLICATIONS
• Mixer/oscillator
• TV tuners
D Package
• CATV
• LAN
• Demodulator
VHFDECOUP
1
VHF INPUT
2
IFAMP
DECOUP
ORDERING INFORMATION
IF PREAMP
INPUT
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
18-Pin Plastic DIP (SOT-102A)
- 25°C to
+ 85°C
TDA5030AN
20-Pin Plastic SO DIP (SOT-163A)
- 25°C to
+ 85°C
TDA5030ATD
NC
6
MIXnF PREAMP
14
(UHF) OUTPUT
MIX/IF PREAMP
(UHF) OUTPUT
IFAMP
osc OUTPUT
13 SWITCH INPUT
12
INPUT
IFAMP
INPUT
g.A~~T
IFAMP
OUTPUT
lOP VIEW
BLOCK DIAGRAM
18
I
OSCINPUT
4
16
VHF
LOCAL
OSCILLATOR
j15
t
I
I
I
I
BUFFERED
OSCILLATOR
OUTPUT
I
I
SAW FILTER
IF AMPLIFIER
I
13
TDA5030A
2
1
I
VHF
MIXER
l--
~
I
UHF IF
PREAMPLIFIER
J-
I
5
4
!3,14
r
7
6
8
9
11
STABILIZER
AND
SWITCH
10
I
12
NOTE,
Pinout is for 18-pin N package.
January 14, 1987
4-102
853-1150 87202
Product Specification
Signetics Linear Products
TDA5030A
VHF Mixer/Oscillator Circuit
UHF/VHF
SWITCH
Vee
1.5pF
9,
r
J
J
1nF
1nF
!DCAL OSCILLAtOR OUTPUT
1nF
-=
18
17
16
15
10
TOA5030
lnF
270
VHF INPUT 0 - - - - - - - '
IF INPUT O > - - - - - - - - - - - - _ - - l
27PF~
Figure 1. Test Circuit
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
Vee
Supply voltage (Pin 15)
VI
Input voltage (Pin 1, 2, 4, and 5)
RATING
UNIT
14
V
o to 5
V
V12
Switching voltage (Pin 12)
o to Vee+0.3
V
-110, 11, 13
Output currents
10
mA
tss
Storage-circuit time on outputs
(Pin 10 and 11)
10
s
·C
TSTG
Storage temperature range
-65 to +150
TA
Operating ambient temperature range
-25 to +85
·C
TJ
Junction temperature
+125
·C
OJA
Thermal resistance from junction to
ambient
+55
·C/W
January 14, 1987
4·103
~27PF
270
I
Signetics Linear Products
Product Specification
TDA5030A
VHF Mixer/Oscillator Circuit
DC AND AC ELECTRICAL CHARACTERISTICS
Measured in circu~ of Figure 1; Vee = 12V; TA = 25°C, unless otherwise
specified.
LIMITS
PARAMETER
SYMBOL
UNIT
Min
Typ
Max
Supply
Vee
Supply voltage
lee
Supply current
V12
Sw~hing
voltage VHF
V12
Sw~ching
voltage UHF
112
Switching current UHF
13.2
V
55
mA
0
2.5
V
9.5
Vee+ 0•3
V
0.7
rnA
470
MHz
9
10
12
dB
dB
dB
10
42
VHF mixer Oncluding IF amplifier)
fR
Frequency range
NF
Noise figure (Pin 2)
50MHz
225MHz
300MHz
7.5
9
10
Optimum source admittance (Pin 2)
50MHz
225MHz
300MHz
0.5
1.1
1.2
ms
ms
ms
Input conductance (Pin 2)
50MHz
225MHz
300MHz
0.23
0.5
0.67
ms
ms
ms
G
GI
50
CI
Input capacitance (Pin 2)
50MHz
V2.:J
Input voltage for 1% cross-modulation
On channel); Rp > 1kn; tuned circuit
with Cp 22pF; fRES 36MHz ,
V2-14
Input voltage for 10kHz pulling (in channel) at < 300MHz
100
Av
Voltage gain
22.5
=
97
2.5
pF
99
dBIlV
=
dBIlV
24.5
26.5
dB
UHF preamplifier (including IF amplifier)
GI
Input conductance (Pin 5)
0.3
CI
Input capacitance (Pin 5)
3.0
NF
Noise figure
VS.14
Input voltage for 1% cross-modulation (in channel)
Av
Voltage gain
Gs
Optimum source admittance
January 14, 1987
5
88
90
31.5
33.5
3.3
4·104
ms
pF
6
dB
dBIlV
35.5
dB
ms
Signetlcs Linear Products
Product Specification
VHF Mixer/Oscillator Circuit
TDA5030A
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) Measured in circuit of Figure 1; Vcc=12V; TA =25°C,
unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
VHF mixer
YC2-S, 7
Conversion transadmittance
5.7
ms
Zo
Output impedance
1.6
kn
VHF oscillator
fR
Frequency range
520
MHz
Ilf
Frequency shift
IlVcc = 10%; 70 to 330M Hz
200
kHz
Ilf
Frequency drift
IlT = 15k; 70 to 330MHz
250
kHz
Ilf
Frequency drift from 5sec to 15min after switching on
200
kHz
70
SAW filter IF amplifier
ZB,9
Input impedance
ZlO, 11 = 2kn, f = 36MHz
ZB, 9-10, 11
Transimpedance
Z10, 11
Output impedance
ZB, 9 = 1.6kn; f = 36M Hz
340+j100
n
2.2
kn
50+j40
n
20
20
mV
mV
90
n
VHF local oscillator buffer stage
V13
V13
Output voltage
RL = 75n; f < 100MHz
RL = 75n; f> 100MHz
14
10
Z13
Output impedance
f = 100MHz
RF
--(RF+LO)
RF signal on LO output; RL = 50n; VI = 1V; f <: 225MHz
January 14, 1987
4-105
10
dB
•
TDA5230
Signetics
VHF, Hyperband, and UHF
MixerjOsciliator With IF Amp
Preliminary Specification
Linear Products
DESCRIPTION
FEATURES
The TDA5230 consists of three (VHF,
Hyperband, UHF) mixer/oscillators, and
an IF Amplifier Circuit for TV tuner or
communication front end designs. The
integration of these functions within one
IC facilitates the construction of a complex tuner design with higher performance and fewer components than circuitry using discrete transistors.
• Balanced mixer for VHF having a
common emitter input
• Amplitude-controlled oscillator for
VHF
• Balanced mixer for hyperband &
UHF with common base input
• Balanced hyperband & UHF
oscillator
• Balanced mixer for UHF with
common base input
• SAW filter preamplifier with a
75n output impedance
• Buffer stage for drive of a
prescaler with the oscillator
signal (VHF only)
• Voltage stabilizer for oscillator
stability
• Band switch circuit
PIN CONFIGURATION
APPLICATIONS
• CATV
• Communication receiver
• TV tuners
• Data communication
ORDERING INFORMATION
DESCRIPTION
24-Pin Plastic DIP (SOT-137)
February 1987
TEMPERATURE RANGE
ORDER CODE
-25°C to + 80°C
TDA5230D
4-106
D Package
VHFOSC
(BASE IN)
VHFL.O.
OUT
VHFOSC
(COLLECT IN)
HVPERBAND
OSCIN
22 HYPERBAND
IN
21 HYPERBAND
IN
HYPERBAND
OSCIN
UHFOSC
(BASE IN)
UHFOSC
(COLLECT IN)
UHFOSC
(COLLECT IN)
UHFOSC
(BASE IN)
lOP VIEW
Preliminary Specification
Signetics Linear Products
TDA5230
VHF, Hyperband, and UHF Mixer/Oscillator With IF Amp
BLOCK DIAGRAM
1
4
3
12
~
9
8
7
G
5
L
-
VHF
OSC
v- t1~ V
HYPERB.
esc
1.7k
T
t
I
I
I
I
I
T
--
1k
UHF
esc
1k
--
~
I
I
I
I
r
I
TDA5230
r
r-
~
r
--
.j~
-=-
IF
AMPL
>~
~
L........,
SWITCH-=-
MIXER
MIXER
MIXER
.j~
-=-
VV IVV ~
VV
f-~V
~
>--
I
I
12
11
j
:nr
VHF
r
5k
5k
24
23
I-
~
~
ff - ~ff ~
L
HYPERB.
STAGE
L
*
eCSTAB +
INTERNAL
BIASINGS
l..--
UHF
STAGE
r
22
21
-J,20
19
18
t
16
15
14
-
13
BD08681S
February 1987
4-107
•
"T1
<
::J:
."
::J:
:t;
'2"
..
C"
-<
~I
co
CI
PI
.----;I~
R1
102
,
o·y
i
"'?D3
I
~
~
o=~
Tn
i: IF::
SK
'
~R1O
4:"" {RO
1.-+--+1_,
...
=C11
T. ' " '
C5
R2
- - , C6
!0
II
I:
t.
~R"
±co I
I~=ES
I: VH~ ~
r
"U
0
f}
c
P-
LS
O
IF
'01
11
8'"
:::J
~OUTPUT
C20
r;J
c
:::J
an.
0-
VHF
:::J
(l)
:!:
....
(j)
SK2
en
<6.
c
::J:
_021
12
:::J
a.
12Y
"~
,
~.
0
en
Q.
en
0-+
....0
~
':j
I" I':" 114 1 glLS
I L9~t"1 I %C2A I~C231 1"22
,7
r t1
..
=r::"
10 C27-28 OR C29-30
t
50
"-~
=
":'
-=-
1
t
C29
HYBRID
I
-:;:- :;:C28
=;==
13
I
1 ..._._
50
"
»
3
u
"U
"'"
~
-I
NOTES:
1. L6 - L7 is a matching transformer (n = L7JL6 = 6). Terminated with son, it simulates the impedance of a saw-filter on Pins 11 -12.
2. em is the simulated maximum allowable input capacitance of the saw-filter, which is 18pF if the capacitance between the leads to Pins 11 -12 is < 4pF.
S. In the application em, L6 and L7 must be replaced by a saw-filter and an inductance across its input which tunes out the total capacitance between the pins if no Ie has been connected.
4. This circuit is mounted on the V-H-U p.b.c. number: 3373.
Figure 1. Test Circuit for All Band VHF·UHF Mixer Oscillation IC TDA5230
~:
0
-<
~
U
(,.)
0
I\)
0
en
~
~
:!:
0
:::J
Preliminary Specification
Signetics Linear Products
VHF, Hyperband, and UHF Mixer/Oscillator With IF Amp
TDA5230
Component Values of Circuit in Figure 1
Resistors
Rl =
R2=
R3 =
R4=
R5 =
47kQ
18Q
4.7kQ
1.2kQ
47kQ
R6 = 100Q Rll = lkQ
R7 = 22kQ R12 = 2.2kQ
R8 = 22kQ R13 = 22kQ
R9 = 2.2kQR14 = 2.2kQ
RIO = 22kQR15 = 2.2kQ
R16 = 10Q (SMO)
Capacitors
Cl
C2
C3
C4
CS
C6
C7
C8
C9
Cl0
=
=
=
=
=
=
=
=
=
=
1/lF-40V
lnF
82pF (N750)
lnF
1.8pF (N750)
1.8pF (N750)
lnF
lnF
lnF
lnF
Cll
C12
C13
C14
C15
C16
C17
C18
C19
C20
=
=
=
=
=
=
=
=
=
=
12pF (N750)
lnF
1.5pF (SMO)
1.5pF (SMO)
lnF
S.6pF (SMO)
100pF (SMO)
1.5pF (SMO)
1.5pF (SMO)
lnF
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
=
=
=
=
=
=
=
=
=
=
lnF
lnF
15pF (N750)
15pF (N750)
lnF
lnF
lnF
lnF
lnF
lnF
Diodes and IC
01 = 889098
02 = 8A482
03 = 889098
04 = 884058
Calls
L1 =
L2 =
L3 =
L4 =
LS =
wire
2.51 ",3
6.S1 f
Frequency variation with supply voltage,
Temperature and spread of IC properties
at fNOM = 36kHz3
lose
Oscillator current drain
at fNOM = 36kHz
November 14, 1986
120
5-4
kHz
1.3
0.15fNOM
kHz
2.5
rnA
Signetics Linear Products
Product Specification
SAF1032P/1039P
RIC Receiver; RIC Transmitter
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
Voo
T A = 0 to + 85"C, unless otherwise specified.
Vee
(V)
SAF1032
TA
(0C)
Recommended supply voltage
UNIT
Min
Typ
8
Max
10
V
50
300
p.A
p.A
1
mA
V
V
Supply current
100
Quiescent
10
10
25
85
100
Operating; 10 = 0;
at OSCI frequency of 100kHz
10
Ali
1
Inputs
VIH
VIL
DATA; OSCI, HOLD; TVOT4
Input voltage HIGH
Input voltage LOW
8 to 10
8 to 10
Ali
Ali
0.7Voo
0
Voo
0.2Voo
VTI
VTD
MAIN; tripping levels
Input voltage increasing
Input voltage decreasing
5 to 10
5 to 10
Ali
Ali
OAVOO
O·1Voo
0.9Voo
0.6Voo
V
II
Input current; ali inputs except TVOT
10
25
1
p.A
tR, tF
Input signal rise and fali times
(10% and 90% Voo)
ali inputs except MAIN
8 to 10
Ali
5
!lS
8
10
Ali
Ali
10
mA
p.A
10- 5
Outputs
10L
10L
Program selection: BINAIB/C/D
Auxiliary: SELA/B/C/D
Analog: L30T; L20T; L10T TVOT4
Ali open·drain n·channel
output current LOW at VOL = OAV
output leakage current at Va = Vss to Voo
1.6
NOTES:
1. The keyboard inputs (TRX, TRY, TRSL) are not voltage driven (see Application Information Diagram, Figure 5).
If one key is depressed, the circuit generates the corresponding code. The number of keys depressed at a time, and this being recognized by the circuit as an illegal
operation, depends on the supply voltage VDD and the leakage current (between device and printed circuit board) externally applied to the keyboard inputs.
If no leakage is assumed, the circuit recognizes an operation as illegal for any number of keys> 1 depressed at the same time with VOD = 7V. At a leakage due to a
1Mn resistor connected to each keyboard input and returned to either VDD or Vss, the circuit recognizes at least 2 keys depressed at a time with Voo = 7V.
The highest permissible values of the contact series resistance of the keyboard switches is 500!1
2. Inhibit output transistor disabled.
3. ~f is the width of the distribution curve at 20 points (0 = standard deviation).
4. Terminal rvOT is input for manual ON. When applying a LOW level rvor becomes an output carrying a LOW level.
November 14, 1986
5-5
•
Signetics Linear Products
product Specification
SAF1032P/1039P
RIC Receiver; RIC Transmitter
BLOCK DIAGRAM OF SAF1039P TRANSMITTER
SAF1039P
TRXO
TRXi
TRX2
TRxa
TRYO
TRY1
TRY2
TRY3
TALS
1
5
2
ENCODING
rr
3
•
15
~}
INPUT
CONTROL
~7
"
~
13
12
OSCILLATOR
11
!'6
•
voo
TR01
10
7
TR02 TROS
TRDT
OUTPUT
GATING
6
TlNH
SCALER
27
!8
v,,
OPERATING PRINCIPLES
The data to be transmitted are arranged as
serial information with a fixed pattern (see
Figure 1), in which the data bit locations Bo to
B4 represent the generated key command
code. To cope with IR (infrared) interferences
of other sources, a selective data transmission is present. Each transmitted bit has a
burst of 26 oscillator periods.
Before any operation will be executed in the
receiver/decoder chip, the transmitted data
must be accepted twice in sequence. This
means the start code must be recognized
each time a data word is applied and comparison must be true between the data bits of
two successively received data words. If both
requirements are met, one group of binary
output buffers will be loaded with a code
defined by the stored data bits, and an
internal operation can also take place (See
operating code table).
The contents of the 3 analog function registers are available on the three outputs in a
pulse code versus time modulation format
after D-to-A (digital-to-analog) conversion.
The proper analog levels can be obtained by
using simple integrated networks. For local
control a second transmitter chip (SAF1039P)
is used (see Figure 4).
TIMING CONSIDERATIONS
The transmitter and receiver operate at different oscillator frequencies. Due to the design
neither frequency is very critical, but correlation between them must exist. Calculation of
these timing requirements shows the following.
11~:~-------STARTCODE--------~~~--------DATABrrs--------~~
~._.-
____________________-,ONEDATAWORD~=-__________________~
32)( 10 = 32 x~m$(2)
It
NOTES:
1. To = 1 clock period = 128 oscillator periods.
2. fT in kHz.
Figure 1. Pattern for Data to be Transmitted
With a tolerance of ± 10% on the oscillator
frequency (fT) of the transmitter, the receiver
oscillator frequency (fR = 3 X 'T) must be
kept constant with a tolerance of ± 20%.
On the other hand, the data pulse generated
by the pulse stretcher circuit (at the receiver
side) may vary ± 25% in duration.
GENERAL DESCRIPTION OF
THE SAF1039P TRANSMITTER
Any keyboard activity on the inputs TRXO to
TRX3, TRYO to TRY3 and TRSL will be
November 14, 1986
5-6
detected. For a legal key depression, one key
down at a time (one TRX and TRY input
activated), the oscillator starts running and a
data word, as shown above, is generated and
supplied to the output TROT. II none, or more
than 2 inputs are activated at the same time,
the input detection logic of the chip will
generate an overall reset and the oscillator
stops running (no legal key operation).
This means that lor each key-bounce the
logic will be reset, and by releaSing a key the
transmitted data are stopped at once.
Signetics Linear Products
Product Specification
SAF1032P/1039P
RIC Receiver; RIC Transmitter
OPERATION MODE
The minimum key contact time required is the
duration of two data words. The on-chip
oscillator is frequency-controlled with the external components R1 and C1 (see circuit
Figure 3); the addition of resistor R2 means
that the oscillator frequency is virtually independent of supply voltage variations. A complete data word is arranged as shown in
Figure 1, and has a length of 32 X Toms,
where To = 27 1fT.
DATA
MODE
FUNCTION OF TINH
Unmodulated: LOCAL operation
Modulated: REMOTE control
1
2
Output, external pull-up resistor to Voo
Input, connected to Vss
GENERAL DESCRIPTION OF
THE SAF1032P RECEIVER/
DECODER
the start code and compares the stored data
bits with the new data bits accepted.
The logic circuitry of the receiver I decoder
chip is divided into four main parts as shown
in the Block Diagram.
This part stores the program selection code
in the output group (BINF) and memorizes it
for condition HOLD = LOW.
Part I
It puts the functional code to output group
(SELF) during data accept time, and decodes
the internally-used analog commands (ANDEC).
Part II
This part decodes the applied DATA information into logic '1' and '0'. It also recognizes
BLOCK DIAGRAM OF SAF1032P RECEIVER/DECODER
7
HOLD
10
II
6
5
4
BINARY OUTPUT
FLAGS (BINF)
17
Il
16
15
14
BINARY SELECT
FLAGS (SELF)
I
II
I
BUFFER
REGISTER
(BFR)
II
ANALOG
DECODER
(ANDEC)
I
DATA SHIFT
REGISTER
(SRDT)
DATA
I
I
ANALOG
CONVERSION
(D/A)
LINEAR 2
REGISTER
(LlN2)
f-
CONVERSION
REGISTER
(LlN3)
I
t
II t
TIMER COUNTER
(CTIM)
I
f-
November 14, 1986
1
L30T
III
'<.
COMPARATOR
COUNTER
(COMP)
IV
II
II
I
MAIN
FLAG
(MAINF)
+
TV ON/OFF
FLAG
(TVONF)
I
I
I
12
8
MAIN
TVOT
+
PRESET
FLAG
(PREST)
Vss
5-7
L20T
(D/A)
!9
!'B
2
DIGITAL TO
ANALOG
CONVERSION
SAF1032P
voo
L10T
(D/A)
BIT COUNTER
(BITC)
'0'/'1' DETECTOR
START CODE
OETECTION
(CSTO)
ANALOG
~
COMPARATOR
(KOM)
3
DIGITAL TO
t
I
11
DIGITAL TO
f-
LINEAR 3
I
~;
LINEAR 1
REGISTER
(LlNl)
13
OSCI
•
Product Specification
Signetics Linear Products
SAF1 032P11 039P
RIC Receiver; RIC Transmitter
Part III
This part controls the analog function registers (each 6 bits long), and connects the
contents of the three registers to the analog
outputs by means of 0/A conversion. Ouring
sound mute, output L1OT will be forced to
HIGH level.
Part IV
This part keeps track of correct power 'ON'
operation, and puts chip in 'standby' condition at supply voltage interruptions.
The logic design is dynamic and synchronous
with the clock frequency (OSCI), while the
required control timing signals are derived
from the bit counter (BITC).
Operation
Serial information applied to the OATA input
will be translated into logic '1' and '0' by
means of a time ratio detector.
After recognizing the start code (CSTO) of
the data word, the data bits will be loaded into
the data shift register (SROT). At the first
trailing edge of the following data word, a
comparison (KOM) takes place between the
contents of SROT and the buffer register
(BFR). If SROT equals BFR, the required
operation will be executed under control of
the comparator counter (COMP).
As shown in the operating code table on the
next page, the 4-bit wide binary output buffer
(BINF) will be loaded for BFRO = '0', while for
BFRO = '1' the binary output buffer (SELF),
also 4-bits wide, will be activated during the
data accept time.
At the same time operations involving the
internal commands are executed. The contents of the analog function registers (each 6
bits long) are controlled over 63 steps, with
minimum and maximum detection, while the
0/ A conversion results in a pulsed output
ANALOG
OIJTPUT
(50% CONTENTS)
I
Figure 2_ Analog Output Pulses
November 14, 1986
5-8
signal with a conversion period of 384 clock
periods (see Figure 2).
First power ON will always put the chip in the
standby position. This results in an internal
clearing of all logic circuitry and a 50%
presetting of the contents of the analog
registers (analog base value). The program
selection '1' code will also be prepared and
all the outputs will be nonactive (see operating output code table).
From standby, the chip can be made operational via a program selection command,
generated LOCAL or via REMOTE, or directly
by forcing the TV ON/OFF output (TVOT) to
zero for at least 2 clock periods of the
oscillator frequency.
For POWER-ON RESET, a negative-going
pulse should be applied to input MAIN, when
VDD is stabilized and pulse width
LOW;;'100J-lS.
Signetics Unear Products
Product Specification
SAF1032P/1039P
RIC Receiver; RIC Transmitter
OPERATING CODE TABLE
KEY·MATRIX
POSITION
BUFFER
BFR
BINF
(BIN.)
SELF
(SEL.)
FUNCTION
TRX.
TRY.
TRSL
0
1
2
3
4
A
B
C
0
A
B
C
0
0
0
0
0
1
1
1
1
0
2
3
0
1
2
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Program
Select + ON
2
2
2
2
3
3
3
3
0
1
2
3
0
1
2
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Program
Select + ON
0
0
0
0
1
1
1
1
0
1
2
3
0
1
2
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
1
1
1
1
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
1
1
1
1
0
1
1
1
Analog base
Reg. (UN3) + 1
Reg. (LlN2) + 1
Reg. (LlN1) + 1
OFF
Reg. (UN3) - 1
Reg. (LlN2) - 1
Reg. (LlN1)-1
2
2
2
2
3
3
3
3
0
1
2
3
0
1
2
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
Mute (set/reset)
1
X
X
X
NOTE:
Reset mute also on program select codes, (UN1) ± 1. and analog base.
OPERATING OUTPUT CODE
(BIN.)
(SEL.)
(L.OT)
TVOT
Standby OFF via remote
ON - 'not hold' condition
non·operating
ON - 'hold' condition
non·operating
November 14, 1986
A
B
C
0
A
B
C
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
1
X
X
X
0
X
X
X
X
1
1
1
1
X
X
X
0
1
5·9
2
3
t",w '""-"
•
Signetlcs Linear Products
Product Specification
RIC Receiver; RIC Transmitter
SAF1032P/1039P
+
9V
S: SATURATION
B: BRIGHTNESS
V: VOLUME
Figure 3. Interconnection Diagram of Transmitter Circuit SAF1039P in a
Remote Control System for a Television Receiver With 12 Programs
November 14. 1986
5-10
Product Specification
Signetics Linear Products
SAF1 032P11 039P
RIC Receiver; RIC Transmitter
lnF
..-------+---....
VDD(+W)
Pu.....
STlI£TCHER
(2 x "4 HEF4011B)
BPW34
OSCILLATOR
(2 x 1/4 HEF401 tB)
~~--+----+--~~~~-~-~-~---~----~-------+----+4-~--~vu
+1"
10K
, -.....-vW---o+ 12V
HOLD
DATA
IWN
OSCI
lSOpF
(2%)
I!!] E!!l E!) E;]
I!!] I!!] [!!]I!!]
~I!!] ~~
El
G~
[IJITJ[]
SELD
( sac
NC
SELB
SELA
Voo
,.
15
10k
V,.
8INA
12
14
10t1
TVOT
11
13
10k
BlNB
SAF
l002P
•
BINC
BIND
"
,.
17
3
t
FOR INTERFACE
SEE FIGURE 5
Figure 4. Interconnection Diagram Showing the SAF1032P and SAF1039P Used in a TV Control System
November 14, 1986
5-11
•
Signetics Linear Products
Product Specification
SAF1 032P11 039P
RIC Receiver; RIC Transmitter
Voo
+12V
VOLUME
{PIN 5: TBA750
10k
10k
Voo
+12V
10k
150k
10k
lOOk
lk
BRIGHTNESS
(PIN 11: TDA2560)
18k
Voo
+12V
33k
Voo
39k
..---'VII'v-__
TO PIN 9 OF TDA2581
t--_.....
TO PIN 4 OF TDA2581
47k
Figure 5. Additional Circuits from Outputs L 10T(1), L20T(2), L30T(3) and TVOT(4) of the SAF1032P In Circuit of Figure 4
November 14. 1986
5·12
SAA3004
Signetics
Infrared Transmitter
Product Specification
Linear Products
DESCRIPTION
FEATURES
The SAA3004 transmitter Ie is designed
for infrared remote control systems. It
has a total of 448 commands which are
divided into 7 subsystem groups with 64
commands each. The subsystem code
may be selected by a press button, a
slider switch or hard wired.
• Flashed or modulated
transmission
• 7 subsystem addresses
• Up to 64 commands per
subsystem address
• High·current remote output at
Voo 6V HOH 40mA)
• Low number of additional
components
• Key release detection by toggle
bits
• Very low standby current
« 2/lA)
• Operational current < 2mA at 6V
supply
• Wide supply voltage range
(4 to 11V)
• Ceramic resonator controlled
frequency (typ. 450kHz)
• Encapsulation: 20·lead plastic DIP
or 20·lead plastic mini·pack
(50·20)
PIN CONFIGURATION
=
The SAA3004 generates the pattern for
driving the output stage. These patterns
are pulse distance coded. The pulses
are infrared flashes or modulated. The
transmission mode is defined in conjunction with the subsystem address. Modulated pulses allow receivers with narrowband preamplifiers for improved noise
rejection to be used. Flashed pulses
require a wide-band preamplifier within
the receiver.
N, D Packages
•
=
APPLICATIONS
• TV
• Audio
lOPYlEW
CD1.2OOQS
PIN NO.
1
2
3
4
5
6
7
6
9
10
11
12
13
14
15
16
17
18
19
ORDERING INFORMATION
20
TEMPERATURE RANGE
ORDER CODE
20-Pin Plastic DIP (SOT-146Cl)
-20·C to + 70·C
SAA3004PN
20-Pin Plastic SOL (SOT-163AC3)
- 20·C to + 70·C
SAA3004TD
DESCRIPTION
OSCI
v..
SYMBOL
REMO
-)
-)
SEN5N
SEN4N
SEN3N
SEN2N
SEN1N
SENON
V
__
AORM
esci
esee
DRV1N
DRV2N
ORV3N
DRV4N
DRV5N
ORVaN
Voo
DESCRIPTION
Remote data output
Key mabix sense inputs
Address mode control input
Ground
Oscillator Input
Oscillator output
Key matrix drive outputs
Positive supply
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
-0.5 to +15
V
V
Voo
Supply voltage range
VI
Input voltage range
-0.5 to Voo + 0.5
Vo
Output voltage range
-0.5 to Voo + 0.5
V
±I
DC current into any input or output
10
mA
-I(REMO)M
Peak REMO output current
during 1Oj.lS; duty factor = 1%
300
rnA
PrOT
Power dissipation per package
for TA = -20 to +70·C
200
mW
TSTG
Storage temperature range
-65 to +150
·C
TA
Operating ambient temperature range
-20 to +70
·C
December 2, 1986
5·13
853-1027 86699
Product Specification
Signetics Linear Products
Infrared Transmitter
SAA3004
DC ELECTRICAL CHARACTERISTICS Vss= oV; TA=25°C, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Voo (V)
Min
Voo
Supply voltage
TA = 0 to +70°.c
Typ
4
100
100
Supply current; active
fosc = 455kHz;
AEMO output unloaded
6
9
100
100
Supply current; inactive
(stand-by mode)
TA = 25°C
6
9
fosc
Oscillator frequency (ceramic resonator)
4 to 11
Max
11
rnA
rnA
1
3
400
V
2
2
1JA
1JA
500
kHz
Keyboard matrix
Inputs SENON to SEN6N
VIL
Input voltage LOW
4 to 11
VIH
Input voltage HIGH
4 to 11
-II
-II
Input current
VI=OV
4
11
II
Input leakage current
VI = Voo
0.2 X Voo
10
30
V
V
0.8 X Voo
100
300
1JA
1JA
11
1
1JA
Outputs DAVON to DRV6N
VOL
VOL
Output voltage "ON"
10 = 0.1 rnA
10 = 1.0mA
4
11
0.3
0.5
V
V
10
Output current "OFF"
Vo= l1V
11
10
1JA
Control Input ADRM
VIL
Input voltage LOW
VIH
Input voltage HIGH
0.8 X Voo
V
V
0.2 X Voo
Input current
(switched P-and N-channel pull-up/pull-down)
IlL
IlL
Pull-up active
standby voltage: OV
4
11
10
30
100
300
IIH
IIH
Pull-down active
standby voltage: Voo
4
11
10
30
100
300
3
6
1JA
1JA
1JA
1JA
Data output REMO
VOH
VOH
Output voltage HIGH
-IOH=40mA
6
9
VOL
VOL
Output voltage LOW
10L =0.3mA
6
9
II
Input current
ascI at Voo
6
VOH
Output voltage HIGH
-IOL=O.lmA
VOL
Output voltage LOW
10H =O.lmA
V
V
0.2
0.1
V
V
2.7
1JA
6
Voo-0.6
V
6
0.6
V
OSCillator
December 2, 1986
5-14
0.8
Product Specification
Signetics Linear Products
SAA3004
Infrared Transmitter
1
~
a:
c
1 :;
z z~
a::
13
7 [}
~
If If J!
/.5 If If If If
~23 1/ If If If
V3' 1/ If If V
lf39 1/ 1/ V If
/47 f If If ,f
lfss j V If If
V63 j If If V
~ ~o
If If VB
lfV J/'6
lflf [j24
If V V32
f .} lf40
j V f .. D2~J
.f If f56
SENON
8
SEN1N
7
SEN2N
6
SEN3N
5
SEN4N
4
SEN5N
3
SEN6N
2
~
z~
a:
z~
c:
a:
cae
0
14
15
16
z~
a:
c
17
z~
a:
c
18
19
•
ADRM
9
·OPTIONAL DIODES
'j
Y
'j
~
'j
6/
"
' , _ ADDRESS
1 1 1 1
SELECTION
Figure 1. Transmitter With SAA3004
INPUTS AND OUTPUTS
Key Matrix Inputs and Outputs
(DRVON to DRV6N and SENON
to SEN6i11)
The transmitter keyboard is arranged as a
scanned matrix. The matrix consists of 7
driver outputs and 7 sense inputs as shown in
Figure 1. The driver outputs DRVON to
DRV6N are open-drain N-channel transistors
and they are conductive in the stand-by
mode. The 7 sense inputs (8ENON to
8EN6N) enable the generation of 56 command codes. With 2 external diodes all 64
commands are addressable. The sense inputs have P-channel pull-up transistors, so
that they are HIGH until they are pulled LOW
by connecting them to an output via a key
depression to initiate a code transmission.
Address Mode Input (ADRM)
The subsystem address and the transmission
mode are defined by connecting the ADRM
input to one or more driver outputs (DRVON
to DRV6N) of the key matrix. If more than one
driver is connected to ADRM, they must be
decoupled by a diode. This allows the definiDecember 2, 1986
tion of seven subsystem addresses as shown
in Table 3. If driver DRV6N is connected to
ADRM the data output format of REMO is
modulated or if not connected, flashed.
address 2 by connecting DRV1 N to ADRM. If
now DRV3N is added to ADRM by a key or a
switch, the transmitted subsystem address
changes to 4.
The ADRM input has switched pull-up and
pull-down loads. In the stand-by mode only
the pull-down device is active. Whether
ADRM is open (subsystem address 0, flashed
mode) or connected to the driver outputs, this
input is LOW and will not cause unwanted
dissipation. When the transmitter becomes
active by pressing a key, the pull-down device
is switched off and the pull-up device is
switched on, so that the applied driver signals
are sensed for the decoding of the subsystem
address and the mode of transmission.
A change of the subsystem address will not
start a transmission.
The arrangement of the subsystem address
coding is such that only the driver DRVnN
with the highest number (n) defines the subsystem address, e.g., if driver DRV2N and
DRV4N are connected to ADRM, only
DRVN4N will define the subsystem address.
This option can be used in transmitters for
more than one subsystem address. The
transmitter may be hard-wired for subsystem
5-15
Remote Control Signal Output
(REMO)
The REMO signal output stage is a push-pull
type. In the HIGH state a bipolar emitterfollower allows a high output current. The
timing of the data output format is listed in
Tables 1 and 2.
The information is defined by the distance tb
between the leading edges of the flashed
pulses or the first edge of the modulated
pulses (see Figure 3).
The format of the output data is given in
Figures 2 and 3. In the flashed transmission
mode, the data word starts with two toggle
bits, T1 and TO, followed by three bits for
defining the subsystem address 82, 81 and
80, and six bits F, E, D, C, B and A, which are
defined by the selected key.
Signetics linear Products
Product Specification
Infrared Transmitter
SAA3004
In the modulated transmission mode the first
toggle bit, T1, is replaced by a constant
reference time bit (REF). This can be used as
a reference time for the decoding sequence.
The toggle bits function as an indication for
the decoder that the next instruction has to
be considered as a new command.
The codes for the subsystem address and the
selected key are given in Tables 3 and 4.
Oscillator Input/Output (OSCI
and OSCO)
The external components must be connected
to these pins when using an oscillator with a
ceramic resonator. The oscillator frequency
may vary between 400kHz and 500kHz as
defined by the resonator.
FUNCTIONAL DESCRIPTION
Keyboard Operation
one or more of the sense inputs (SENnN) are
tied to ground. This will start the power-up
sequence. First the oscillator is activated and
after the debounce time tos (see Figure 4) the
output drivers (DRVON to DRV6N) become
active successively.
Within the first scan cycle the transmission
mode, the applied subsystem address and
the selected command code are sensed and
loaded into an internal data latch. In contradiction to the command code the subsystem
address is sensed only within the first scan
cycle. If the applied subsystem address is
changed while the command key is pressed,
the transmitted subsystem address is not
altered.
In a multiple keystroke sequence (see Figure
5), the command code is always altered in
accordance with the sensed key.
Multiple Keystroke Protection
In the standby mode all drivers (DRVON to
DRV6N) are on. Whenever a key is pressed,
at the same time, the circuit will not generate
a new output at REMO (see Figure 5). In case
of a multiple keystroke the scan repetition
rate is increased to detect the release of a
key as soon as possible.
There are two restrictions caused by the
special structure of the keyboard matrix:
• The keys switching to ground (code
numbers 7, 15, 23, 31, 39, 47, 55 and
63) and the keys connected to SEN5N
and SEN6N are not covered completely
by the multiple key protection. If one
sense input is switched to ground,
further keys on the same sense line are
ignored.
• SEN5N and SEN6N are not protected
against multiple keystroke on the same
driver line, because this condition has
been used for the definition of
additional codes (code numbers 56 to
63).
The keyboard is protected against multiple
keystrokes. If more than one key is pressed
REMO
BrTS:
S2
o
DATA:
TOGGLE BITS
S1
1
SUB-SYSTEM ADDRESS
t==tbl~tbl~tbO~
REMO :
so
o
---+-j
I..-tpw
COMMAND
41STWO:DI~
tw
JIL-]~IL.JIIIIUIIIIL.JIIIIUIIIIL..JIIIUIIIIUIIIIL.JIIIIUIIIUIIIIL___---lI~IIILJIIIIL
so
81TS:REF
DATA: 1
TO
1
------ ------
REFERENCE TOGGL.E BIT
52
0
51
1
0
FED
1
00
--------~-------SUB-SYSTEM ADDRESS
C
B
A
00
COMMAND
NOTES:
a. Flashed mode: transmission with 2 toggle bits and 3 address bits, followed by 6 command bits (pulses are flashed).
b. Modulated mode: transmission with reference time. toggle bit and 3 address bits, followed by 6 command bits (pulses are modulated).
Figure 2. Data Format of REMO Output; REF = Reference Time; TO and T1 = Toggle Bits;
SO, S1 and S2 = System Address; A, B, C, D, E, and F = Command Bits
December 2, 1986
5-16
Signetics Linear Products
Product Specification
Infrared Transmitter
REYO
SAA3004
:J1. . .-:-_________________ ---1L->i~.~~--~tp--------------------tb,----------------------~~1
REWO
NOTES:
1. Flashed pulse.
2. Modulated pulse {tpw = (5 X tM)
•
+ tMH-
Figure 3. REMO Output Waveform
_
KEY RE::::: .nfD
"~~--------------""II"""III
KEY BOUNCING
~tREL----I
[-- -- -
U
__
IL
NEWKEV
OFF
ORVnN
seAN'~-------
REUO
oseo
:J1Il_W;_
Figure 4. Single Key-Stroke Sequence
Output Sequence (Data Format)
The output operation will start when the
selected code is found. A burst of pulses.
including the latched address and command
codes. is generated at the output REMO as
long as a key is pressed. The format of the
December 2, 1966
output pulse train is given in Figures 2 and 3.
The operation is terminated by releasing the
key or if more than one key is pressed at the
same time. Once a sequence is started. the
transmitted words will always be completed
after the key is released.
5-17
The toggle bits TO and T1 are incremented if
the key is released for a minimum time tREL
(see Figure 4). The toggle bits remain unchanged within a multiple keystroke sequence.
Product Specification
Signetlcs Linear Products
SAA3004
Infrared Transmitter
NOTES:
1. Scan rate multiple key-stroke: tSM'" 6 to 10 X
2. For toa. tST and tw see Figure 4.
to.
Figure 5. Multiple Key-Stroke Sequence
Table 2. Pulse Train Separation
Table 1. Pulse Train Timing
to
(ms)
tp
(liS)
Flashed
2.53
8.8
Modulated
2.53
MODE
tM
(liS)
tML
(liS)
tw
(ms)
tMH
(lIS)
Logic "0"
Logic "1"
Reference time
121
26.4
121
8.8
17.6
NOTES:
lose
tp
tM
tML
tMH
lo
tw
Toggle bit time
tose ~ 2.2/1s
Flashed pulse width
Modulation period
Modulation period LOW
Modulation period HIGH
Basic unit of pulse distance
Word distance
455kHz
4 X lose
12 X lose
8 X lose
4 X tose
1152 X tose
55 296 X lose
Table 3. Transmission Mode and Subsystem Address Election
F
L
A
S
H
E
D
M
0
D
U
L
A
T
E
D
DRIVER DRVnN
FOR n=
SUBSYSTEM
ADDRESS
MODE
2
#
S2
Sl
SO
0
0
1
2
3
4
5
6
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
X
X
X
X
X
x
x
x
0
X
X
X
X
X
0
1
2
3
4
5
6
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
3
5
6
x
0
0
X
0
0
0
0
X
X
X
0
0
0
0
X
X
0
X
0
x
x
x
x
0
X
X
X
X
X
~ Connected to ADRM
- Not connected to ADRM
- Don't care
December 2, 1986
4
0
NOTES:
o
Blank
X
(tB)
CODE
5-18
0
0
0
0
ts
2 X to
3 X to
3 x to
2 x to or
3 X to
Signetics Linear Products
Product Specification
SAA3004
Infrared Transmitter
Table 4. Key Codes
MATRIX
DRIVE
MATRIX
SENSE
DRVON
DRV1N
DRV2N
DRV3N
DRV4N
DRV5N
DRV6N
VSS
SENON
SENON
SENON
SENON
SENON
SENON
SENON
SENON
1
1
1
1
1
1
SEN1N
SEN2N
SEN3N
SEN4N
SEN5N
SEN6N
SEN5N
and
SEN6N
1
CODE
F
E
D
C
B
A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
1
1
1
0
0
0
0
1
1
MATRIX
POSITION
0
1
2
3
4
5
6
7
1
0
1
1
0
1
0
2
2
2
2
2
2
8
16
24
32
40
48
1
2
56 to 63
1
0
to
to
to
to
to
to
15
23
31
39
47
55
NOTES:
1. The complete matrix drive as shown above for SENON is also applicable for the matrix sense inputs
SEN1N to SEN6N and the combined SEN5N/SEN6N,
2. The C. B and A codes are identical to SENON as given above.
December 2, 1986
5-19
The subsystem address and the transmission
modes are defined by connecting the ADRM
input to one or more driver outputs (DRVON
to DRV6N) of the key matrix, If more than one
driver is connected to ADRM, they must be
decoupled by a diode.
•
Signetics
AN1731
Low-Power Remote Control IR
Transmitter and Receiver
Application Note
Linear Products
LOW-POWER IR TRANSMITTER
SAA3004
The SAA3004 is a new MaS transmitter IC for
infrared remote control systems in which the
received commands are decoded by a microcomputer. It can transmit up to 448 commands, divided into 7 subsystem groups of 64
commands each and is therefore suitable for
single or multi-system use. To allow remote
control systems with a variety of ranges,
noise immunities, and costs to be built, two
operating modes are available: unmodulated
(single pulse per bit) or modulated (burst of 6
pulses per bit). The subsystem address and
mode of operation may be selected by keyboard contacts for multi-system use, or may
be hard-wired for single system use. The
output from the SAA3004 is Pulse Distance
Modulated (PDM) for maximum power economy and the high level of output current
available (40mA with a 6V supply) allows the
IC to drive an IR LED via a very simple
amplifier using a single external transistor.
Compared with earlier IR transmitter ICs, the
SAA3004 operates over a much wider supply
voltage range (4V to 11V), consumes less
current during operation (1 mA typical with a
6V supply), has a lower standby current
( < 2pA), and requires a minimum number of
external components. The low current consumption is largely due to the fairly low
oscillator frequency (455kHz).
Transmission Formats
The formats of the two transmission modes
are shown in Figure 1.
At least one complete 11-bit word is generated for each legal detected keystroke. The
logic state of a bit is defined by the interval
between consecutive output pulses or bursts,
measured from leading edge to leading edge.
The word is repeated as long as a key
remains pressed. When a key is released, the
transmission ceases as soon as the current
word has been transmitted.
In the unmodulated mode, only one pulse per
bit is generated and passed to output pin
REMO. For this mode, the IR preamplifier in
the receiver can be a broadband type and
therefore inexpensive. However, the interference immunity and range of the remote
control will not be as high as that for a
transmitter in the modulated mode in conjunction with a narrow-band IR receiver.
of about 38kHz. Since this frequency lies
between the first and second harmonics of
the TV line frequency, a narrow-band IR
receiver tuned to 38kHz should be used in the
equipment being controlled. Although such a
receiver is more expensive than a broadband
one, the remote control will be less sensitive
to interference and will have a longer range.
However, if these requirements are not stringent, a broadband receiver could also be
used to receive transmissions in the modulated mode.
Remote control systems normally detect a
command continuously from the moment it is
received. To distinguish between multiple
keystrokes and new commands, it is then
necessary to detect the length of the transmitted data words. The disadvantage of this
method is that a repeated command can be
seen as a new one if the data stream is
interrupted by an external influence. In the
SAA3004, this problem is eliminated by incorporating toggle bits in the data stream. The
toggle bits change state after each key release according to the truth table given in
Table 1. The toggle bits therefore inform the
remote control receiver that new data is
arriving so that the microcomputer can easily
distinguish between new data words and
repeated ones. It can also count the number
of identical commands if they are issued more
than once in sequence. This is an important
facility for selection of Teletext pages with
repeated digits, resetting clock/calendars
and programming VCRs.
Figure 1a is a pulse diagram of the output
signal from the SAA3004 in the unmodulated
mode. The data word consists of 2 toggle bits
(T1 and TO), 3 address bits (S2, S1, and SO)
and 6 command bits (F, E, D, C, B, and A).
Toggle Bit T1 provides additional protection
against interference. If the second keystroke
in a sequence of three is disturbed, the
decoding part of the receiver will recognize
the same data twice; the fact that T1 has
changed state will indicate that a new command is being transmitted.
Figure 2 shows the timing of a single bit for
each transmission mode.
A complete message always consists of 12
pulses, the timing of which is directly related
to the oscillator period tose. The pulse timing
data for fose = 455kHz is as follows.
In the modulated mode, each bit is transmitted as a burst of 6 pulses at a repetition rate
February 1987
5-20
Oscillator period
Pulse width
tosc ~ 2.2/1s
vcc ~ tMH - 4tosc - 8.8/1s
Low period of modula~ tML = BtOSG
tion pulses
Modulated pulse burst
= 17.6p.s
tM _ 12tosc ~ 26.4/15
period
Duration of modulated
pulse burst
tpw=64tosc=141Ils
Interval between pulses to = 1152tosc = 2.53ms
Data word repetition
tw= 48To=
period
Logic '0' pulse or burst t
spaCing
80
Logic '1' pulse or burst t
spacing
121ms
_ 2T _ 5.06ms
0
_ 3T -7.6ms
B1
a
The data word format and timing shown in
Figure 1b for the modulated mode of transmission is the same as that previously described
for the unmodulated mode. In this case, however, each bit consists of a 141 /1S burst of 6
pulses, and toggle bit T1 is replaced by a
reference pulse with a permanent logic 1, the
timing of which is (tREF = tBt = 7.6ms). This
allows a lower stability oscillator to be used in
the transmitter because tREF can be used as a
reference for decoding in the equipment being
controlled.
Functional Description of the
SAA3004
A detailed functional block diagram of the
SAA3004 is given in Figure 3 and the key
sequencing diagram is given in Figure 4,
which shows that, during standby, all the drive
outputs are LOW. When a keystroke is detected (one or more sense inputs LOW) by
the sense detector, the sequence control
block enables the oscillator which starts to
generate clock pulses. The oscillator increments the scan counter which, after debouncing time (tOB > 4To) has elapsed, sequentially
activates the drive outputs at intervals of
tose/?2 (158/1s for fose = 455kHz). See Figure 5.
The activated key position is stored in the
data memory together with the subsystem
address (determined by which of the drive
outputs 1 - 5 is connected to ADRM) and the
output mode (whether or not drive output 6 is
connected to ADRM). However, unlike the
command code, the subsystem address is
only sensed during the first scan cycle and
does not cause any output when it is
changed. The stored data, together with the
toggle bits, are applied to the data multiplexer, the serial output from which is converted
into the correct pulse distances by the modulation counter. The pulses are then fed to
Application Note
Signetics Linear Products
Low-Power Remote Control IR Transmi1ier and Receiver
AN1731
rr+~--------------------------------------IW --------------------------------------~.~I
~tbO~tbl______J
I
REUO
BITS:
OATA;
I
T1
TO
a
",STWOR02NOWORO"
I
S2
TOGGLE BITS
so
SI
o
1
::I-"
I
I
o
1
SUB-SYSTEM ADDRESS
COMMAND
a. Unmodulated Transmission Mode
I==tbl~tbl~tbO+i
REMO :
~
'lSTWOR:I~
Iw
l1-tpw
JlIIL-JI~L_JIIIIUIIIIL_JIIIIUIIIIL.JIIIUIUIIIL_JIIIIUIIIUIIIL_ ___---J11111LJlt
BITS: REF
DATA:
1
TO
1
-.--.-
REFERENCE TOGGLE BIT
52
a
51
so
1
0
FED
C
B
1
1
00
a
A
COMMAND
SUB-SYSTEM ADDRESS
b. Modulated Transmission Mode
Figure 1. Transmission Format at Output REMO
REMO
:-111-7"--------------- _---1LI
-J ,k-I,
I~---~-------------------tb,----------------------.~
a. Unmodulated Transmission Mode
REMO
In standby, the drive lines are LOW and the
sense lines are HIGH. A scan cycle starts as
soon as one of the sense inputs is forced
LOW by a keystroke. If the keystroke is
detected as being legal (only one key
pressed), the appropriate command is decoded according to the scheme in Table 2,
and the correct data word is fed to output
REMO. Bits ABC in Table 2 indicate which of
the seven driver outputs is activated and bits
DEF indicate which of the seven sense inputs
has detected a LOW level.
b. Modulated Transmission Mode
Figure 2. Timing of a Single Bit at Output REMO
output REMO via the output modulator. After
a key is released, the oscillator stops and the
circuits return to the standby state to con·
serve battery power as soon as the output
sequence is completed.
The 5AA3004 has built·in protection against
multiple keystrokes (two or more keys
pressed at a time). In this event, the IC reacts
as shown in Figure 6. At the end of any
current output sequence, output REMO becomes inactive, and the keyboard scanning
interval tw = 121 ms is reduced to tSM (about
20ms). This ensures that a key release is
detected as soon as possible. Also, the
toggle bits remain unchanged during multiple
keystrokes.
February 1987
Table 1. Sequence of Toggle Bits
KEY SEQUENCE
TO
n
n+1
n+2
n+3
n+4
n+5
a
a
1
a
T1
a
a
A Practical IR Transmitter
An example of a complete IR remote control
transmitter is given in Figure 7.
5-21
Forty-nine of the keys (7 X 7 matrix) are
connected directly between driver lines
DRVON to DRV6N and sense lines 5ENON to
5EN6N. Expanding the keyboard for 64 commands is done in three steps. First, seven
keys are added to switch each of the sense
lines to ground. Next, seven keys are added
to switch each of the drive lines to 5EN5N
and 5EN6N via diodes D, and D2. The final
key is added to switch sense lines 5EN5N
and 5EN6N to ground via diodes D, and D2.
Address mode input ADRM selects the subsystem address and determines the transmission mode (modulated or unmodulated). The
subsystem address and mode of operation
depend on which of the seven drive lines is
connected to ADRM as shown in Table 3.
The address is selected either by closing an
address switch to connect a drive output to
input ADRM before pressing a command key,
or by installing a permanent link between one
of the drive outputs and input ADRM. With no
address selected, the basic address (address
bits 52, 51, and 50 all equal 1) is automatically generated.
Mode selection is made via a link between
drive line DRV6N and input ADRM. The
•
Signetics Linear Products
Application Note
Low-Power Remote Control IR Transmitter and Receiver
AN1731
DRVON
DRV1N
DRV2N
DRV3N
OSCI
DRV4N
osco
DRVSN
DRV8N
REMO
SENON
SEN2N
SEN1 N
SEN4N
SEN3N
ADRM
SEN8N
SENSN
Figure 3. Block Diagram of Remote Control Transmitter SAA3004
.m]
rIirr------('nTi
1l1l
~tREL~
KEYBOUNCING
KEY
CLOSED
RELEASED
~
[- -- -- -- --I (
NEW KEY
•
OFF
CRVnN
REUO
NOTE:
I
To = 1152tosc. debounce time lOB""' 4 to 9 X
to,
start time tsT D 5 to 10 X
to,
minimum release time tREL'"
to.
Figure 4. Single Keystroke Sequence
transmission is modulated with the link fitted
or unmodulated without it.
Capacitors C1 and C2 associated with the
oscillator must be chosen with regard to low
current consumption and quick starting over
the whole supply voltage range.
February 1987
The output stage of the SAA3004 shown in
Figure 8 provides a current output of up to
40mA with a 6V supply, sufficient to drive a
very Simple single transistor amplifier to provide current for an infrared LED. When the
output stage is driven by a HIGH level, the
NPN transistor conducts and pulls output pin
5-22
REMO HIGH (3V min. with a 6V supply).
When the output stage is driven by a LOW
level, the NPN transistor is turned off and the
n-channel output FET conducts and pulls
output pin REMO LOW (200mV maximum
with a 6V supply). In this state, the output
stage can sink a typical current of 300MA.
Signetics Linear Products
Application Note
Low-Power Remote Control IR Transmitter and Receiver
DAVON
--I'''''' !-.Jr------IUr-----I
I
J
DRV'N...]
I.
L
I
U
L
'. ··~ANI~"V~-___J.I
Figure 5. Timing at Outputs DRVDN to DRV6N
Table 2. Key Codes
MATRIX
pos.
a
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
February 1987
F
E
CODE
D C
a a a
0 0 a
0 a 0
0 0 a
B
A
0
0
1
MATRIX
POS.
F
E
32
33
34
35
36
37
38
39
1
1
1
1
1
1
1
1
a
a
a
a
0
0
1
1
1
1
1
1
1
1
1
a
a
a
a
a
a
a
1
1
1
1
1
1
1
1
0
0
0
0
0
0
a a
0 a
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
40
41
42
43
44
45
46
47
0
0
a a
0 a
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
48
49
50
51
52
53
54
55
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0 a a
a a 1
0
1 a
56
57
58
59
60
61
62
63
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
a a
a
0
a
a
0
a
a
0
a
0
a
a
0
a
0
a
0
0
0
a
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
a 0
a a
0
1
1
1
1
1
1
a
1
a a
a 1
1 a
1
1
a a
a 1
1
1
0
1
a a
a 1
1 a
1
1
a
a
1
1
1
1
a a
a 1
1 a
1
1
CODE
D C
a 0
a a
a 0
a a
0 a 1
0 a 1
a a 1
0
0
0
0
1
1
1
1
a
AN1731
0
a
0
1
1
1
1
0
0
0
a
a
a
0
0
0
0
0
1
1
1
1
a
1
1
1
1
1
1
1
1
5-23
a
0
0
a
1
1
1
1
B
A
0
0
1
1
0
0
1
1
a
1
a
1
a
1
a
1
a a
0
1
1
0
a
1
a
1
0
1
1
1
a
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
a
1
1
0
0
1
1
1
0
1
0
1
0
1
a
1
•
Signetics Unear Products
Application Note
Low-Power Remote Control IR Transmitter and Receiver
AN1731
KEY A
KEY.
DRVnN
NOTE:
10 =- 1152tosc. debounce time tDe = 4 to 9 X
to,
scan rate 15M'" 6 to 10 X
to.
FIgure 6. Multiple Keystroke Sequence
Table 3. Transmission Mode and Subsystem Address Selection
OUTPUT FORMAT
unmodulated
modulated
SUBSYSTEM ADDRESS
No.
82
81
80
1
1
1
1
DRIVE OUTPUT DRVnN n
0
2
0
0
0
X
3
0
0
1
4
0
1
0
5
0
1
1
-
6
1
0
0
7
1
0
1
1
1
1
1
2
0
0
0
3
0
0
1
4
0
1
0
5
0
1
1
6
1
0
0
7
1
0
1
1
2
3
4
5
=
6
X
-
X
-
X
- - -
-
-
X
-
-
X
X
x
-
X
X
X
- - X
- - -
X
X
X
-
- X
- -
X
-
-
X
X
NOTES:
X Connected to ADRM.
- Allowed connection to ADRM without any influence on the subsystem address.
Power Consumption
Considerations
The intensity of IR radiation IE, and therefore
the transmitter range, is proportional to the
LED forward current IF. The peak value of IF
in the circuit of Figure 7 is determined by the
value of emitter resistor RE and is given by:
However, since the output is pulsed, the
battery life is mainly determined by the average value of the forward current. This averFebruary 1987
age LED current is the peak current multiplied
by the duty factor of the output signal. The
duty factor is the ratio of the total HIGH time
of a data word (12 pulses each of width
Tp = 8.81'S) to the data word repetition period
(tw = 121 ms).
data word is therefore six times that for the
unmodulated mode so that the duty factor is
multiplied by six.
In the modulated mode, the average LED
current is therefore:
In the unmodulated mode, the average LED
current is:
In the modulated mode, each pulse is a burst
of six 8.811S pulses. The total HIGH time of a
5-24
At first glance, the higher required average
current for the modulated mode makes it
appear unattractive because of increased
battery drain. However, if a narrow-band receiver is used with a modulated transmitter,
Signetics Linear Products
Application Note
low-Power Remote Control IR Transmitter and Receiver
11.
o
>
ct
....
N
z
>
c::
..,
z
>
ct
13
'J V
V
V23lf' If
V3' V V
If..lf If
If'7 If If
V55 f I
lf63 If I
17
lf15 If
V V V l{a
V l? V l{a
If lflf ;,.
If lflf 12.
If If If V f32
If If VV /40
If If VI f .. D2~
If I V If /56
V
V
If
If
'G~ 'G~ ·G~
'G~ ·G~ 'G~
~
0/ 'I 'I 0/ 0/ 0/ _
1 f 1 Y1 ? 1
I
SENaN
8
SEN1N
7
SEN2N
6
SEN3N
5
SEN4N
4
SENSN
3
SEN6N
2
14
..,.
z
>
0::
000
z
>
a:
0
15
0
16
z
>
IX
c
In
17
AN1731
z
>
LX
--
5
4
3
zo
Y:1
DECODER
I
6
Z3
Z2
I
MODE
SELECTION
I
1
ZT
26
KEYBOARD
ENCODER
25
24
23
22
21
COMMAND
AND
SYSTEM
ADDRESS
17
LATCH
13
16
15
KEYBOARD
DRIVER
DECODER
I
J
OUTPUT
8
DATA
December 2, 1986
12
11
10
PARALLEL
TO SERIAL
CONVERTER
9
r r
7
MDATA
5-30
DRO
DR1
DR2
DR3
DR4
DRS
DR6
DR7
Signetics Linear Products
Product Specification
SAA3006
Infrared Transmitter
DC ELECTRICAL CHARACTERISTICS
Vss = OV; T = -25 to 85°C, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Voo (V)
Min
Voo
Supply voltage
2
Typ
Max
7
V
10
pA
Supply current
at 10 = OmA for all outputs;
XO to X7 and Z3 at Voo;
all other inputs at Voo or Vss;
excluding leakage current from open·
drain N·channel outputs
100
TA = 25°C
7
Inputs
Keyboard inputs X and Z with P-channel pull-up transistors
-II
Input current (each input) at
VI = OV; TP = SSM = LOW
2 to 7
10
SOO
I1A
VIH
Input voltage HIGH
2 to 7
0.7 X Voo
VDD
V
VIL
Input voltage LOW
2 to 7
0
0.3 X VDD
V
IIR
-IIR
Input leakage current at TA = 25°C;
TP= HIGH;
VI = 7V
VI=OV
1
1
I1A
pA
SSM, TP1 and TP2
VIH
Input voltage HIGH
2 to 7
0.7 X VDD
VDD
V
VIL
Input voltage LOW
2 to 7
0
0.3 X VDD
V
IIR
-IIR
Input leakage current at TA = 25°C;
VI = 7V
VI=OV
1
1
I1A
I1A
2
I1A
OSC
-II
Input leakage current at T A = 25°C;
VI = OV; TP1 = HIGH; Z2 = Z3 = LOW
2 to 7
Outputs DATA and MDATA
VOH
Output voltage HIGH at -IOH = O.4mA
2 to 7
VOL
Output voltage LOW at 10L = O.SmA
2 to 7
V
VDD -0.3
0.3
V
lOR
-lOR
Output leakage current at:
Vo= 7V
Vo=OV
10
20
I1A
pA
lOR
-lOR
TA = 25°C;
Vo= 7V
Vo=OV
1
2
/1A
2 to 7
0.3
V
7
10
pA
1
I1A
pA
ORO to DR?, TP2
VOL
lOR
lOR
Output voltage LOW at 10L = 0.3mA
Output leakage current
at Vo=7V
at Vo = 7V;
TA = 25°C
December 2, 1986
5-31
I
Product Specification
Signetics Linear Products
SAA3006
Infrared Transmitter
DC ELECTRICAL CHARACTERISTICS (Continued) vss = OV; T = -25 to 85·C, unless otherwise specified.
LIMITS
PARAMETER
SYMBOL
UNIT
Voo (V)
Min
Typ
Max
OSC
Oscillator current at OSC = Voo
7
fosc
Maximum oscillator frequency at CL = 40pF
(Figures 4 and 5)
2
fosc
Free-running oscillator frequency
at TA = 25·C
2
lose
4.5
30
p.A
450
kHz
120
kHz
Oscillator
117
'( ~ ~ ~ ~ ~
\15
~4 ~13
[\12
~
~22 ~1
~ ,\9 ,\8
(4)
r\
i\
r\7
~
22
~6
23
~4
24
[\40 26
,\7
\36
~35
1\26 r\25
[\34 \33
~47
\46 \.45 \44 \.43
~2 ~1
1\55
\.54 \53 \52
~63
\,62
[\50 ~ r\48
1\58 ~7 \56
1\,39 Ls,38
~7
~61
\60 ~59
~
~6
,
~
~5
\.14
~3 ~2
~4
[':-3
I' I,
\11
25
27
1
3
~ ~
4
~O
~19
\8
\.30 \.29 \28
\,27
'\.28 \25
\21
~32
'( ~ ~
\20
~23 \22
31
\51
21
~
[\30 \29 [\28
~1
(3)
~1 ~O
ORO
~7 ~6
5:4
5
6
10
/16
DR1
13
DR3
15
DR2
12
DR4
11
DR5
X1
X2
X3
X4
X5
SAA3OO6
X6
X7
zo
ZI
Z2
Z3
rr r rr
TP1
DATA
TP2
MDATA
9
(1)
NOTES:
Control inputs for operating modes, lest modes and reset.
Remote signal outputs.
Keyboard command code matrix 8 X B.
Keyboard system code matrix 4 X 8,
Figure 1. Keyboard Interconnection
December 2, 1986
9
DR7
XO
SSM
1.
2.
3.
4.
10
DR6
5-32
(2)
osc
J::
0
Signetics Linear Products
Product Specification
SAA3006
Infrared Transmitter
FUNCTIONAL DESCRIPTION
Combined System Mode
(SSM = LOW)
The X and Z lines are active-HIGH in the
quiescent state. Legal key operation either in
the X-DR or Z-DR matrix starts the debounce
cycle. When the contact is made for two bit
times without interruption, the oscillator enable signal is latched and the key may be
released. Interruption within the two bit times
resets the internal action. At the end of the
debounce time, the DR outputs are switched
off and two scan cycles are started, switching
on the DR-outputs one by one. When a Z or X
input senses a LOW level, a latch enable
signal is fed to the system address or command latches, depending on whether sensing
was found in the Z or X input matrix. After
latching a system address number, the device
will generate the last command (I.e., all command bits '1') in the chosen system as long
as the key is pressed. Latching of a command
number causes the device to generate this
command together with the system address
number stored in the system address latch.
Releasing the key will reset the internal action
if no data is transmitted at that time. Once the
transmission is started, the signal will be
finished completely.
Single System Mode
(SSM HIGH)
=
The X lines are active-HIGH in the quiescent
state; the pull-up transistors of the Z lines are
switched off and the inputs are disabled. Only
legal key operation in the X-DR matrix starts
the debounce cycle. When the contact is
made for two bit times without interruption,
the oscillator enable signal is latched and the
key may be released. Interruption within the
two bit times resets the internal action. At the
end of the debounce time, the pull-up transistors in the X lines are switched off. Those in
the Z lines are switched on during the first
scan cycle. The wired connection in the Z
matrix is then translated into a system address number and stored in the system ad-
dress latch. At the end of the first scan cycle
the pull-up transistors in the Z lines are
switched off and the inputs are disabled
again, while the transistors in the X lines are
switched on. The second scan cycle produces the command number which, after
latching, is transmitted together with the system address number.
transmitted in biphase; definitions of logical
'1' and '0' are given in Figure 3.
The code consists of four parts:
• Start part formed by 2 bits (two times a
logical '1')
• Control part formed by 1 bit
• System part formed by 5 bits
Inputs
The command inputs XO to X7 carry a logical
'1' in the quiescent state by means of an
internal pull-up transistor. When SSM is LOW,
the system inputs ZO to Z3 also carry a logical
'1' in the quiescent state by means of an
internal pull-up transistor.
When SSM is HIGH, the transistors are
switched off and no current flows via the
wired connection in the Z-DR matrix.
Oscillator
The oscillator is formed by a ceramic resonator (cataloq number 2422 540 98021 or
equivalent) feeding the single-pin input OSC.
Direct connection is made for supply voltages
in the range 2 to 5.25V but it is necessary to
fit a 10kn resistor in series with the resonator
when using supply voltages in the range 2.6
to 7V.
Key Release Detection
An extra control bit is added which will be
complemented after key release. In this way
the decoder gets an indication that shows if
the next code is to be considered as a new
command. This is very important for multidigit entry (e.g., by channel numbers or TeletextlViewdata pages). The control bit will only
be complemented after finishing at least one
code transmission. The scan cycles are repeated before every code transmission, so
that, even by 'takeover' of key operation
during the code transmission, the correct
system and command numbers are generated.
• Command part formed by 6 bits.
The output MOATA carries the same information as output DATA but is modulated on a
carrier frequency of 1,t12 the oscillator frequency, so that each bit is presented as a burst of
32 pulses. To reduce power consumption, the
carrier frequency has a 25% duty cycle.
In the quiescent state, both outputs are nonconducting (3-state outputs). The scan drivers ORO to DR7 are of the open-drain Nchannel type and are conducting in the quiescent state of the circuit. After a legal key
operation all the driver outputs go into the
high ohmic state; a scanning procedure is
then started so that the outputs are switched
into the conducting state one after the other.
Reset Action
The circuit will be reset immediately when a
key release occurs during:
• Debounce time
• Between two codes.
When a key release occurs during scanning
of the matrix, a reset action will be accomplished if:
• The key is released while one of the driver
outputs is in the low-ohmic '0' state
• The key is released before detection of that
key
• There is no wired connection in the Z-DR
matrix while SSM is HIGH.
Outputs
Test Pin
The output DATA carries the generated information according to the format given in Figure 2 and Tables 2 and 3. The code is
The test pins TP1 and TP2 are used for
testing in conjunction with inputs Z2 and Z3
as shown in Table 1.
Table 1. Test Functions
TP1
TP2
Z2
Z3
LOW
LOW
HIGH
HIGH
LOW
HIGH
Output fose 6
Output fose 6
Matrix input
Matrix input
LOW
HIGH
Matrix input
Matrix input
LOW
HIGH
December 2, 1986
5-33
FUNCTION
Normal
Scan + output frequency 6 times faster than normal
Reset
Output frequency 3 X 27 faster than normal
•
Product Specification
Signetics Linear Products
Infrared Transmitter
SAA3006
KEY ACTIVITIES
1 CODE
Every connection of one X input and one DR
output is recognized as a legal keyboard
operation and causes the device to generate
the corresponding code.
Msa
j
Activating more than one X input at a time is
an illegal keyboard operation and no circuit
action is taken (oscillator does not start).
When SSM is LOW, every connection of one
Z input and one DR output is recognized as a
legal keyboard operation and causes the
device to generate the corresponding code.
Activating two or more Z inputs, or Z inputs
and X inputs, at one time is an illegal key·
board operation and no circuit action is taken.
When SSM is HIGH, a wired connection must
be made between a Z input and a DR output.
If no connection is made, the code is not
generated.
JI
LSB MSB
f--..:"_ .1.
I--
""1.'::"
~:NnME
~:~ -1-~------DATA WOROTlME=14BITTIMES
2 coDes SUCCESSIVELY
I'-
_ ________
REPETmON TIME=64 BIT TIMES
When one X or Z input is connected to more
than one DR output, the last scan signal is
considered legal.
Figure 2. DATA Output Format (RC-5)
The maximum allowable value of the contact
series resistance of the keyboard switches is
7kSl
f - - -.....~---i
DIGITAL ~'
t
DIGITAL "0'
1---1BITTIME-
NOTE:
1, Bit time ... 3 X 28 X tosc (typically 1.778ms) where tosc is the oscillator period time.
Figure 3. Blphase Transmission Code
December 2, 1986
:1
CONTROL arT
5-34
I
~
2ND
CODE
Signetles Linear Products
Product Specification
SAA3006
Infrared Transmitter
Table 2. Command Matrix X-DR
CODE
NO
0
0
1
2
3
4
5
6
7
1
2
X-LINES
X
3
4
•
•
•
•
5
6
7
0
•
1
•
2
•
•
•
•
•
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
December 2, 1986
•
•
••
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
DR-LINES
DR
3
4
•
•
•
•
•
•
•
••
•
5-35
•
•
6
•
7
•
•
•
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
•
•
•
0
•
•
•
•
•
5
COMMAND BITS
C
1
4
3
2
•
•
•
•
•
•
I
Signetics Linear Products
Product Specification
Infrared Transmitter
SAA3006
Table 2. Command Matrix X-DR (Continued)
CODE
NO
0
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
December 2, 1986
1
2
X·LlNES
X
3
4
5
6
7
•
0
•
•
•
•
•
•
•
•
5
COMMAND BITS
C
4
3
2
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DR·LlNES
DR
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
•
•
•
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
5·36
3
•
•
•
•
4
•
•
•
•
5
•
•
•
•
6
•
•
•
•
7
•
•
•
•
Signetics Linear Products
Product Specification
Infrared Transmitter
SAA3006
Table 3. System Matrix Z-DR
SYSTEM
NO
Z-LINES
Z
1
2
0
•
•
•
•
•
•
•
•
0
1
2
3
4
5
6
7
3
0
•
•
•
•
•
•
•
•
•
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
•
•
•
•
•
•
•
•
•
•
24
25
26
27
28
29
30
31
•
•
•
•
•
•
•
•
•
1
•
•
•
•
2
•
•
•
•
DR-LINES
DR
3
4
•
5
•
•
•
•
•
•
•
•
6
•
•
•
•
•
•
•
7
•
•
•
•
4
SYSTEM BITS
S
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
------1r-----~-- VDD
llIUl
1\
~
ffi
ga:
osc
"-
..
"TYP
I
o
o
3
SAA3008
ORO 17
......
o
z
DATA
18
XO 21
zo
"'- ......
....I.-,
V,;D;;,DJ.,2_8_ _ _ _
r--..
__
~--~_--+--~-
___
V~
100
Figure 5. Test Circuit for Measurement of Maximum Oscillator Frequency
Figure 4. Typical Normalized Input
Frequency as a Function of the
Load (Keyboard) Capacitance
HANDLING
Inputs and outputs are protected against elec·
trostatic charge in normal handling. However,
to be totally safe, it is desirable to take normal
precautions appropriate to handling MOS devices.
December 2, 1986
5-37
I
SAA3027
Signetics
Infrared Remote Control
Transmitter (RC-5)
Product Specification
Linear Products
DESCRIPTION
FEATURES
The SAA3027 is intended for a general
purpose (RC-5) infrared remote control
system. The device can generate 2048
different commands and utilizes a keyboard with a single-pole switch per key.
The commands are arranged so that 32
systems can be addressed, each system
containing 64 different commands.
• Transmitter for 32 X 64
commands
• One transmitter controls 32
systems
• Very low current consumption
• For infrared transmission link
• Transmission by biphase
technique
• Short transmission times; speedup of system reaction time
• LC oscillator; no crystal required
• Input protection
• Test mode facility
The circuit response to legal (one key
pressed at a time) and illegal (more than
one key pressed at a time) keyboard
operation is specified later in this publication (see KEY ACTIVITIES).
PIN CONFIGURATION
N Package
DR8
DRS
APPLICATION
DR4
• Remote control systems
DR3
DR1
V..
DR2
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
-25'e to + 85'e
SAA3027PN
28-Pin Plastic DIP (SOT-117)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
-0.5 to +15
V
-0.5 to (Voo + 0.5)
V
10
mA
Voo
Supply voltage range with respect to
Vss
VI
Input voltage range
±II
Input current
Vo
Output voltage range
-0.5 to (Voo + 0.5)
V
±Io
Output current
10
mA
Po
Power dissipation output oseo
50
mW
Po
Power dissipation per output (all other
outputs)
PIN
NO.
1
21
22
23
24
25
26
27
2
3
4
5
6
7
8
9
10
11
100
mW
17
Total power dissipation per package
200
mW
TA
Operating ambient temperature range
-25 to +85
'e
TSTG
Storage temperature range
-65 to + 150
'e
December 2, 1986
lOP VIEW
12
13
15
16
PTOT
5-38
DRO
14
18
19
20
28
DESCRIPTION
SYMBOL
X7
XO
X1
X2
X3
X4
X5
X6
SSM
ZO
Z1
Z2
Z3
MDATA J
DATA
DR7
DR6
DR5
DR4
DR3
DR2
DR1
ORO
vss
OSCI
TP
OSCO
voo
I
I
Keyboard command inputs with
P.channel pull-up transistors
System mode selection input
}
Keyboard system inputs with
P-channel pull-up transistors
Remote signal outputs
(3-5tats outputs)
Scan driver outputs with opendrain N-channel transistors
Negative supply (ground)
Oscillator input
Test pin
Oscillator output
Positive supply
853-1030 86699
Product Specification
Signetics Unear Products
SAA3027
Infrared Remote Control Transmitter (RC-5)
BLOCK DIAGRAM
SAA3027
OSCI
DSCC
TP
18
I
I
I
OSCilLATOR
I
20
19
1
1
TEST
MODE
1
I
1
-,
MASTER
RESET
GENERATOR
•
I
2
SSM
Z3
Z2
ZI
ZD
MODE
SELECTION
DECODER
I
8
CCNTROl
UNIT
I---
2"
DMDER
I---
5
4
-,
3
1
'1J
X8
X5
X4
X3
X2
X1
xo
27
28
KEYBOARD
ENCODER
25
24
22
21
I
1
1
OUTPUT
8
DATA
December 2, 1986
17
COMMAND
AND
SYSrEM
ADDRESS
LATCH
23
PARAllEL
TO SERIAL
CONVERTER
18
15
KEYBOARD
DRIVER
DECODER
-I
5·39
11
9
1
VDD
MDATA
12
10
t t
7
13
ORO
DR1
DR2
DR3
DR4
DRS
DR8
DR7
Signetics Linear Products
Product Specification
Infrared Remote Control Transmitter (RC-5)
SAA3027
DC AND AC ELECTRICAL CHARACTERISTICS Vss = OV; TA = -25°C to 85°C, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Voo (V)
Typ
Min
Voo
Supply voltage
4.75
Max
12.6
V
10
jJA
300
jJA
Supply current
at 10 = OmA for all outputs;
XO to X7 and Z3 at Voo;
all other inputs at Voo or Vss;
excluding leakage current from open
drain N-channel outputs;
TA = 25°C
100
12.6
Inputs
Keyboard inputs X and Z with P-channel pull-up transistors
-II
Input current (each input) at VI = OV;
TP= SSM = LOW
VIH
VIL
IIR
-IIR
Input leakage current
at TA = 25°C; TP = HIGH;
VI = 12.6V
VI=OV
4.75 to 12.6
10
Input voltage HIGH
4.75 to 12.6
0.7 X Voo
Voo
V
Input voltage LOW
4.75 to 12.6
0
0.3 X Voo
V
1
1
jJA
jJA
"
12.6
12.6
SSM, TP and OSCI inputs
VIH
Input voltage HIGH
4.75 to 12.6
0.7 X Voo
Voo
V
VIL
Input voltage LOW
4.75 to 12.6
0
0.3 X Voo
V
IIR
-IIR
Input leakage current at TA = 25°C;
VI = 12.6V
VI=OV
1
1
jJA
jJA
12.6
12.6
Outputs
DATA, MDATA
VOH
Output voltage HIGH at -IOH = 0.8mA
4.75 to 12.6
VOL
Output voltage LOW at 10L = 0.8mA
4.75 to 12.6
0.4
V
12.6
12.6
10
20
jJA
jJA
12.6
12.6
1
2
p.A
jJA
4.75 to 12.6
0.4
V
12.6
10
jJA
12.6
1
p.A
lOR
-lOR
lOR
-lOR
Output leakage current at:
Vo= 12.6V
Vo=OV
TA = 25°C;
Vo= 12.6V
Vo=OV
Voo -0.6
V
DR!! to DR7 outputs
VOL
Output voltage LOW at IOL = 0.35mA
lOR
Output leakage current
at Vo= 12.6V
at Va = 12.6V;
TA = 25°C
lOR
OSCO output
VOH
Output voltage HIGH
at -IOH = 0.2mA; OSCI = Vss
4.75 to 12.6
VOL
Output voltage LOW
at -IOL = 0.45mA; OSCI = Voo
4.75 to 12.6
Voo-0.6
0.5
Oscillator
fosel
V
V
~
Maximum oscillator frequency
at CL = 40pF (Figures 4 and 5)
fosel
fosel
December 2, 1986
4.75
6
12.6
5-40
75
120
300
72
72
72
kHz
kHz
kHz
Signetics Linear Products
Product Specification
SAA3027
Infrared Remote Control Transmitter (RC-5)
Handling
Inputs and outputs are protected against
electrostatic charge in normal handling. However, to be totally safe, it is desirable to take
normal precautions appropriate to handling
MOS devices.
~ ~ ~ ~ ~ ~
f\: 1\
~5 ~4 ~3
f\12 f\:1
r\0
~ ~
~23 ~22 ~1
f\20 1'\9
[\6
['\7 ['\6
~31 1\30
~29 ~28 ~7
1\39 1\36
~37 1\36
(3)
:\,54
~63 ~G2
i\3S 1\34
1\44 1\43 1\42
[\24 24
25
1\41
1\40
26
1\53 1\52 1\51 1\50
~9 1\46
27
~60 ~59 ~S6
1<7 1\56
1
[\61
~4
I,
~3
I,
f'~ ~
1\1S 1\14 [\13 1\12 1\11 1\10 1\9
1\0
1\8
1\23 1\22 1\21 1\20 ~19 1\18 [\17 [\16
\31\,30
23
[\32
~6 ~5
~7 I,
(4)
22
~33
1\47 1\46 1\45
1\55
1\26 I\S
\29 \.28
~27
\26
\25 V4
116
DR1
117
DRO
21
3
4
5
8
13
DR3
1S
DR2
12
DR4
11
DRS
10
DR6
9
DR7
xo
X1
X2
X3
X4
XS
X6
SAA3027
X7
ZD
Z1
Z2
Z3
TP
SSM
DATA
MDATA
rrrr
----..-
(I)
oseo
OSCI
18
20
,..{<
..1
:r-
..1
(2)
NOTES:
(1) Programming inputs for operating modes, test mode and reset.
(2) Remote signal outputs.
(3) Keyboard command code matrix 8 X B.
(4) Keyboard system code matrix 4 X B.
Figure 1. Keyboard Interconnection
FUNCTIONAL DESCRIPTION
Combined System Mode
(SSM = LOW)
The X and Z-lines are active HIGH in the
quiescent state. Legal key operation either in
the X-DR or Z-DR matrix starts the debounce
cycle. When the contact is made for two bit
times without interruption, the oscillator-enable signal is latched and the key may be
December 2, 1986
released. Interruption within the two bit times
resets the internal action. At the end of the
debounce time, the DR-outputs are switched
off and two scan cycles are started, switching
on the DR-outputs one by one. When a Z or
X-input senses a LOW level, a latch-enable
signal is fed to the system address or command latches; depending on whether sensing
was found in the Z or X-input matrix. After
latching a system address number, the device
5-41
will generate the last command (i.e., all command bits '1') in the chosen system as long
as the key is pressed. Latching of a command
number causes the device to generate this
command together with the system address
number stored in the system address latch.
Releasing the key will reset the internal action
if no data is transmitted at that time. Once the
transmission is started, the signal will be
finished completely.
•
Signetics Linear Products
Product
SAA3027
Infrared Remote Control Transmitter (RC-5)
Single System Mode
(SSM = HIGH)
The X-lines are active HIGH in the quiescent
state; the pull-up transistors of the Z-lines are
switched off and the inputs are disabled. Only
legal key operation in the X-DR matrix starts
the debounce cycle. When the contact is
made for two bit times without interruption,
the oscillator-enable signal is latched and the
key may be released. Interruption within the
two bit times resets the internal action. At the
end of the debounce time, the pull-up transistors in the X-lines are switched off; those in
the Z-lines are switched on during the first
scan cycle. The wired connection in the Zmatrix is then translated into a system address number and stored in the system address latch. At the end of the first scan cycle
the pull-up transistors in the Z-lines are
switched off and the inputs are disabled
again, while the transistors in the X-lines are
switched on. The second scan cycle produces the command number which, after
latching, is transmitted together with the system address number.
Inputs
The command inputs XO to X7 carry a logical
'1' in the quiescent state by means of an
internal pull-up transistor. When SSM is LOW,
the system inputs ZO to Z3 also carry a logical
'1' in the quiescent state by means of an
internal pull-up transistor.
When SSM is HIGH, the transistors are
switched off and no current flows via the
wired connection in the Z-DR matrix.
Oscillator
OSCI and OSCO are the input/output, respectively, of a two-pin oscillator. The oscillator is formed externally by one inductor and
two capacitors and operates at 72kHz (typical).
digit entry (e.g. by channel numbers or TeletextlViewdata pages). The control bit will only
be complemented after finishing at least one
code transmission. The scan cycles are repeated before every code transmission, so
that, even by 'take-over' of key operation
during code transmission, the correct system
and command numbers are generated.
Outputs
The output DATA carries the generated information according to the format given in Figure 2 and Tables 1 and 2. The code is
transmitted in biphase; definitions of logical
'1' and '0' are given in Figure 3.
The code consists of four parts:
• Start part formed by 2 bits (two times a
logical '1')
• Control part formed by 1 bit
• System part formed by 5 bits
• Command part formed by 6 bits
The output MDATA carries the same information as output DATA but is modulated on a
carrier frequency of half the oscillator frequency, so that each bit is presented as a
burst of 32 oscillator periods. To reduce
power consumption, the carrier frequency has
a 25% duty cycle.
In the quiescent state, both outputs are nonconducting (3-state outputs). The scan drivers ORO to DR7 are of the open drain Nchannel type and are conducting in the quiescent state of the circuit. After a legal key
operation, a scanning procedure is started so
that they are switched into the conducting
state one after the other.
Reset Action
The circuit will be reset immediately when a
key release occurs during:
Spec~lcatlon
• The key is released while one of the driver
outputs is in the low-ohmic '0' state;
• The key is released before detection of that
key;
• There is no wired connection in the Z-DR
matrix while SSM Is HIGH.
Test Pin
The test pin TP is an input which can be used
for testing purposes.
When LOW, the circuit operates normally.
When HIGH, all pull-up transistors are
switched off, the control bit is set to zero and
the output data is 26 times faster than normal.
When Z2 = Z3 = LOW, the counter will be
reset to zero.
Key Activities
Every connection of one X-input and one DRoutput is recognized as a legal keyboard
operation and causes the device to generate
the corresponding code.
Activaiing more than one X-input at a time is
an illegal keyboard operation and no circuit
action is taken (oscillator does not start).
When SSM is LOW, every connection of one
Z-input and one DR-output is recognized as a
legal keyboard operation and causes the
device to generate the corresponding code.
Activating two or more Z-inputs, or Z-inputs
and X-inputs, at one time is an illegal keyboard operation and no circuit action is taken.
When SSM is HIGH, a wired connection must
be made between a Z-input and a DR-output.
If no connection is made, the code is not
generated.
When one X or Z-input is connected to more
than one DR-output, the last scan signal is
considered legal.
Key-Release Detection
• Debounce time
An extra control bit is added which will be
complemented after key-release. In this way
the decoder gets an indication that shows if
the next code is to be considered as a new
command. This is very important for multi-
• Between two codes
The maximum allowable value of the contact
series resistance of the keyboard switches is
When a key release occurs during scanning
of the matrix, a reset action will be accomplished if:
Z2 or Z3 must be connected to VDD to avoid
unwanted supply cu"ent.
December 2, 1986
5-42
10kn
Signetics Linear Products
Product Specification
SAA3027
Infrared Remote Control Transmitter (RC-5)
1 CODE
•
2 CODES SUCCESSIVELY
1-'
2ND
,
REPETlTlONTIME=64 BITTIMES
- -----------------1-
Figure 2. DATA Output Format (RC-S)
t
DIGITAL ~.
DIGITAL '0.
!--1BITTIME-
NOTE:
1. Bit Time .. 27 X Tosc
0;;
1.77Bms (Typical), where Tosc is the oscillator period time.
Figure 3. Blphase Transmission Code
December 2. 1986
5-43
CODE
Product Specification
Signetics Linear Products
SAA3027
Infrared Remote Control Transmitter (RC-5)
Table 1. Command Matrix X-DR
CODE
NO
X·LINES
0
0
1
2
3
4
5
6
7
1
2
3
•
•
•
4
5
6
7
0
•
1
•
•
•
2
•
3
•
•
•
•
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
December 2, 1986
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
5
COMMAND BITS
C
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DR·LlNES
DR
X
•
•
•
5-44
•
•
•
4
•
•
•
•
5
•
•
•
•
6
•
•
•
•
7
•
•
•
•
0
Product Specification
Signetics Linear Products
SAA3027
Infrared Remote Control Transmitter (RC-5)
Table 1. Command Matrix X-DR (Continued)
CODE
NO
X·L1NES
X
0
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
December 2, 1986
1
2
3
4
5
6
7
•
•
•
•
•
•
•
•
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
•
•
•
•
5-45
2
•
•
•
•
DR·LINES
DR
4
3
•
•
•
•
•
•
•
•
5
•
•
•
•
6
•
•
•
•
7
•
•
•
•
5
COMMAND BITS
C
4
3
2
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
•
Signetics Linear Products
Product Specification
SAA3027
Infrared Remote Control Transmitter (RC-5)
Table 2. System Matrix Z-DR
SYSTEM
NO
0
Z·LINES
Z
1
2
3
•
•
0
1
2
3
4
5
6
7
0
•
•
•
•
•
•
•
8
9
10
11
12
13
14
15
•
•
•
•
•
•
•
•
•
16
17
18
19
20
21
22
23
•
•
•
•
•
•
•
•
24
25
26
27
28
29
30
31
•
•
•
•
•
•
•
1
•
•
•
•
2
•
•
•
•
DR·LINES
DR
3
4
•
5
•
•
•
•
•
•
•
•
•
•
•
•
•
•
6
•
•
•
•
7
•
•
•
•
4
SYSTEM BITS
S
1
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
------1>------,.....-- VDD
JlM
1\
OSCI
\
I"\, TYP
I"
o
o
"-
18
XO 21
V,:D;:;D.l..28
_ _ _ _--I-,
DATA
,.... r--.
100
Figure 5. Test Circuit for Measurement of Maximum Oscillator Frequency
Figure 4. Typical Normalized Input
Frequency as a Function of the
Load (Keyboard) Capacitance
December 2, 1986
5·46
SAA3028
Signetics
Infra red Receiver
Product Specification
Linear Products
PIN CONFIGURATION
DESCRIPTION
FEATURES
The SAA302B is intended for use in
general purpose (RC-5) remote control
systems. The main function of this integrated circuit is to convert RC-5 biphase
coded signals into equivalent binary values. Two input circuits are available: one
for RC-5 coded signals only; the other
selectable to accept RC-5 coded signals
only, or RC-5 (extended) coded signals
only. The input used is that at which an
active code is first detected. Coded
signals not in RC-5/RC-5(ext) format are
rejected. Data input and output is by
serial transfer, the output interface being
compatible for 12 C bus operation.
• Converts RC-5 or RC-5(ext)
biphase coded signals into binary
equivalents
• Two data inputs:
one fixed (RC-5); one selectable
(RC-5/RC-5(ext»
• Rejects all codes not in RC-5/
RC-5(elCt) format
.. 12 C output interface capability
o Power-off facility
o Master/slave addressable for
multi-transmitter/receiver
applications in RC-5(ext) mode
.. Power-on reset for defined startup
N Package
ENB
po
DATA1
DATA 2
TOP VIEW
CDl2040$
PIN NO. SYMBOL
DESCRIPTION
1
DAV
Data valid output with open drain
N-channel transistor
APPLICATION
.. Remote control systems
6
7
8
9
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
16-Pin Plastic DIP (SOT-38Z)
-25'C to 85'C
SAA3028N
10
11
12
13
14
15
16
BLOCK DIAGRAM
RCS
DAV
OSCI
MAO}
MA1
MA2
RC5
OSCI
OSCO
Master address inputs
Data 2 input select
Oscillator input
Oscillator output
Negative supply (ground)
Vss
SCl
Ser~al clock .Iine } 12C bus
SDA
Senal data line
OAT A 2 Data 2 input
DATA 1 Data 1 input
PO
Power·off signal output with open
drain N-channel transistor
ENB
Enable input
Set standby input
SSB
Positive supply (+ 5V)
Voo
OSCO
12
DATA 10---1--1
11
10
~--1'--OSDA
DATA20--r-~L-~~~~
MAD MA1 MA2
December 2, 1986
SSB ENB
po
5-47
853-1028 86699
•
Product Specification
Signetics Linear Products
SAA3028
Infrared Receiver
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
VDD
Supply voltage range with respect to Vss
VI
Input voltage range
±II
Input current
Vo
Output voltage range
±Io
Output current
Po
UNIT
-0.5 to + 15
V
-0.5 to (VDD + 0.5)
V1
10
rnA
-0.5 to (VDD + 0.5)
V1
10
rnA
Power dissipation output OSCO
50
mW
Po
Power dissipation per output (all other outputs)
100
mW
PTOT
Total power dissipation per package
200
mW
TA
Operating ambient temperature range
-25 to +85
'C
TSTG
Storage temperature range
-55 to +150
'C
NOTE:
1. Voo+ 0.5 not to exceed 15V.
DC ELECTRICAL CHARACTERISTICS Vss=OV; TA = -25'C to 85'C, unless otherwise specified.
LIMITS
SYMBOL
UNIT
VDD (V)
PARAMETER
Min
4.5
VDD
Supply voltage
IDD
Supply current; quiescent at TA = 25'C
5.5
Typ
Max
5.5
V
200
p.A
VDD
V
Inputs MAO, MAl, MA2, DATA I, DATA 2, RC5, SCl, ENB, SSB, OSCI
VIH
Input voltage HIGH
4.5 to 5.5
VIL
Input voltage lOW
4.5 to 5.5
II
Input leakage current at VI = 5.5V; TA = 25'C
5.5
1
p.A
-II
Input leakage current at VI = OV; TA = 25'C
5.5
1
p.A
4.5 to 5.5
0.4
V
5.5
1
p.A
0.7 X VDD
0
V
0.3 X VDD
Outputs DAV, PO
VOL
Output voltage lOW at IOL = 1.6mA
lOR
Output leakage current at Vo = 5.5V; TA = 25'C
OSCO
VOH
Output voltage HIGH at -IOH = 0.2mA
4.5 to 5.5
VOL
Output voltage lOW at IOL = 0.3mA
4.5 to 5.5
0.4
V
lOR
lOR
Output leakage current at TA = 25'C ;
Vo=5.5V
Vo=OV
5.5
5.5
1
1
p.A
p.A
VDD-0.5
V
SDO
VOL
Output voltage lOW at IOL = 2mA
4.5 to 5.5
0.4
lOR
Output leakage current at Vo = 5.5V; TA = 25'C
5.5
1
Maximum oscillator frequency (Figure 6)
4.75
I
V
p.A
Oscillator
fosci
HANDLING
Inputs and outputs are protected against
electrostatic charge in normal handling. How-
December 2, 1986
500
ever, to be totally safe, it is desirable to take
normal precautions appropriate to handling
MOS devices.
5-48
kHz
Signetics Linear Products
Product Specification
Infrared Receiver
SAA3028
DATA 2: This input performs according to
the logic state of the select input
RC5. When RC5 = HIGH, DATA 2
input will accept only RC-5 coded
signals. When RC5 = LOW, DATA
2 input will accept only RC-5(ext)
coded signals.
FUNCTIONAL DESCRIPTION
Input Function
The two data inputs are accepted into the
buffer as follows:
DATA 1: Only biphase coded signals
which conform to the RC-5 format
are accepted at this input.
The input detector selects the input, DATA 1
or DATA 2, in which a HIGH-to-LOW transi-
tion is first detected. The selected input is
then accepted by the buffer for code conversion. All signals received that are not in the
RC-5 or RC-5(ext) format are rejected.
Formats of RC-5 and RC-5(ext) biphase coded signals are shown in Figures 1 and 2,
respectively; the codes commence from the
left of the formats shown. The bit-times of the
biphase codes are defined in Figure 3.
I I
START
r~~j
CONTROL
i-----------------DATAWORDTlME=1SBITTIMES------------------j-
NOTE:
Stop time
=
1.5 bit-times (nominal).
Figure 1. RC-5 Code Format: the First Start Bit is Used Only for Detection and Input Gain-Setting
REPEATG RESET STANDBY
NOT
DEFINED
---START
FUNCTION
SLAV~ ADDRESS
MASTER
ADDRESS
DATA
CONTROL
i - - - - - - - - - - - - - - - - D A T A WORDTIME=30 BIT TIMES
NOTE:
Stop time = 1.5 bit-timos (nominal).
Figure 2. RC-5 (extended) Code Format: the First Start Bit is Used Only for Detection and Input Gain-Setting
1-----1.---1
t
DIGITAL l'
DIGITAL '0'
!---1BITTIME-
NOTE:
RC-5 bit-time
=
27 X tose = 1.77Bms (typical), RC-5(ext) bit-time = 26 X tose = O.89ms (typical), where tosc "" the oscillator period time.
Figure 3. Blphase Code Definition
December 2, 1986
5-49
•
Signetics Linear Products
Product Specification
SAA3028
Infrared Receiver
More information is added to the input data
held in the buffer in order to make it suitable
for transmission via the 12 C interface. The
information now held in the buffer is as shown
in the table.
RC-S BUFFER CONTENTS
•
•
•
•
•
•
1
1
1
1
5
6
Data valid indicator
Format indicator
Input indicator
Control
Address data
Command data
Bit
Bit
Bit
Bit
Bits
Bits
RC-S(EXT) BUFFER CONTENTS
•
•
•
•
•
•
•
Data valid indicator
Format indicator
Input indicator
Master address
Control
Slave address
Data
1
1
1
3
8
8
8
Bit
Bit
Bit
Bits
Bits
Bits
Bits
The information assembled in the buffer is subjected to the following controls before
being made available at the 12 C interface:
ENB = HIGH
Enables the set standby input SSB.
SSB = LOW
Causes power-off output PO to go HIGH.
PO= HIGH
This occurs when the set standby input SSB = LOW and allows the
existing values in the buffer to be overwritten by the new binary equivalent values. After ENB = LOW, SSB is don't care.
PO= LOW
This occurs according to the type of code being processed, as follows:
RC-5: When the binary equivalent value is transferred to the buffer.
RC-5(ext): When the reset standby bit is active and the master address
bits are equal in value to the MAO, MA 1, MA2 inputs.
At power-on, PO is reset to LOW.
DAV = HIGH
This occurs when the buffer contents ari valid. If the buffer is not
empty, or an output transfer is taking place, then the new binary values
are discarded.
Output Function
The data is assembled in the buffer in the
format shown in Figure 4 for RC-5 binary
equivalent values, or in the format shown in
Figure 5 for RC-5(ext) binary equivalent values. The data is output serially, starting from
the left of the formats shown in Figures 4 and
5.
----~----_DATA2----~----DATA3----_+-----
t
CONTROL BIT
INPUTlNDICAroR: 0 = DATA lINPU-r, 1= DATA 2 INPUT
The output signal DAV, derived in the buffer
from the data valid bit, is provided to facilitate
use of the transcoder on an interrupt basis.
This output is reset to LOW during power-on.
FORMATINDICAroR:O=RC-5
DATA VALID = 0; DATA NOT VALID = 1
Figure 4. RC-S Binary Equivalent Value Format
The 12C interface allows transmission on a
bidirectional, two-wire 12C bus. The interface
is a slave transmitter with a built-in slave
address, having a fixed 7-bit binary value of
0100110. Serial output of the slave address
onto the 12C bus starts from the left-hand bit.
----~-----DATA2----~----DATA3----~-----
~
RESET
STANDBY
INPUT INDICAroR: 0 = DATA lINPU-r, 1= DATA 2 INPUT
FORMAT INDICAroR: 1= RC - 5 (EXl]
DATA VALlD=O; DATA NOT VALID =1
Figure S. RC-S(ext) Binary Equivalent Value Format
December 2, 1986
5-50
Signetics Linear Products
Product Specification
Infrared Receiver
SAA3028
Oscillator
The oscillator can comprise a ceramic resonator circuit as shown in Figure 6. The typical
frequency of oscillation is 455kHz.
15nF
rt--,.---t----o OSCI
~ERAMIC
lTt=J RESONAlOR
•
15nF
~1--4----4----o osco
NOTE:
(1) Catalog number of ceramic resonator: 2422 540 98008.
Figure 6. Oscillator Circuit
FUNCTIONAL DESCRIPTION
12C Bus Transmission
Formats for 12C transmission in low-and highspeed modes are shown respectively in
Figures 7 and 8.
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM MASTER
ACKNOWLEDGE FROM RECEIVER
(=MASTER)
NOTES:
When R/W bit"" 0, the slave generates a NACK (negative acknowledge), leaves the data line HIGH and waits for a stop (P) condition.
When the receiver generates a NACK, the slave leaves the data line HIGH and waits for P (the slave acting as if all data has been transmitted).
When all data has been transmitted, the data line remains HIGH and the slave waits for P.
Figure 7. Format for Transmission In 12C Low-Speed Mode
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE FROM RECEIVER
(=MASTER)
NOTES:
When A/IN bit"" 0, the slave generates a NACK (negative acknowledge), leaves the data line HIGH and waits for a stop (P) condition.
When the receiver generates a NACK, the slave leaves the data line HIGH and waits for P (the slave acting as if all data has been transmitted).
When all data has been transmitted, the data line remains HIGH and the slave waits for P.
Figure 8. Format for Transmission In 12C High-Speed Mode
December 2, 1986
5-51
TDA3047
Signetics
IR Preamplifier
Product Specification
Linear Products
DESCRIPTION
FEATURES
The TDA3047 is for infrared reception
with low power consumption.
• HF amplifier with a control range
of 66dB
• Synchronous demodulator and
reference amplifier
PIN CONFIGURATION
• AGC detector
• Pulse shaper
• Q-factor killing of the input
selectivity, which is controlled by
the AGC circuit
• Input voltage limiter
D, N Packages
INPUT SIGNAl
1
INPUT SIGNAL
2
15 INPUT SIGNAL
Q FACTOR IN
3
14 Q FACTOR IN
FEEDBACK CAP IN
4
13 FEEDBACK CAP IN
FEEDBACK CAP IN
5
12
~~~~Ti'"rJ'ME
FEEDBACK CAP IN 6
11
~~~~~~PER
COILINPUT
7
TOP
view
APPLICATION
• IR remote control systems
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
16-Pin Plastic DIP (SOT-38)
-25°C to + 125°C
TDA3047N
o to +70°C
TDA3047TD
16-Pin Plastic SO (SOT-l09A)
ORDER CODE
BLOCK DIAGRAM
4
135
6
7
10
12
March 2, 1987
16
11
5-52
853-1195 87842
Product Specification
Signetics Linear Products
TDA3047
IR Preamplifier
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
Vcc
Supply voltage (Pin 8)
111
Output current pulse shaper (Pin 11)
V2-15
V4-13
V5-6
V7 - 10
V9-ll
Voltages
Pins 2
Pins 4
Pins 5
Pins 7
Pins 9
RATING
UNIT
13.2
V
10
mA
4.5
4.5
4.5
4.5
4.5
V
V
V
V
V
between pins 1
and 15
and 13
and 6
and 10
and 11
TSTG
Storage temperature range
-65 to +150
'C
TA
Operating ambient temperature range
-25 to + 125
'C
•
NOTE:
1. All pins except Pin 11 are short·circuit protected.
DC ELECTRICAL CHARACTERISTICS Vce = V8 = 5V;
TA
= 25'C,
measured in Figure 3, unless otherwise specified.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
Supply (Pin 8)
Vee
lee
= 18
Supply voltage
4.65
5.0
5.35
V
Supply current
1.2
2.1
3.0
mA
15
25
5
p.V
p.V
200
mV
Controlled HF amplifier (Pins 2 and 15)
V2-15(P.P)
V2- 15(P.P)
Minimum input signal (peak-to-peak value)
at f = 36kHz 1
at f = 36kHz2
AGC control range (without a-killing)
V2-15(P.P)
60
Input signal for correct operation (peak-to-peak value)3
= 114 < 0.5p.A) peak-to-peak value)
= 13 = max.) (peak-to-peak value)
V2- 15(P.P)
a-killing inactive (13
V2.15(P.P)
a-killing active (114
66
0.02
dB
140
28
a-killing range
p.V
mV
Figure 1
Inputs
V2
Input voltage (Pin 2)
2.25
2.45
2.65
V15
Input voltage (Pin 15)
2.25
2.45
2.65
V
R2-15
Input resistance (Pin 2)
10
15
20
kS1
C2-15
Input capacitance (Pin 2)
Vl - 16
Input limiting (Pin 1) at 11
3
= 3mA
V
pF
0.8
0.9
V
Outputs
= 75p.A
= 75p.A
-V9_8
Output voltage HIGH (Pin 9) at -Ig
0.1
0.5
V
Vg
Output voltage LOW (Pin 9) at Ig
0.1
0.5
V
-Ig
-Ig
-Ig
Output current; output voltage HIGH
at Vg = 4.5V
at Vg = 3.0V
at Vg = 1.0V
Ig
R7 - 10
March 2, 1987
75
75
75
120
130
140
Output current; output voltage LOW at Vg = 0.5V
75
120
Output resistance between Pins 7 and 10
3.1
4.7
5-53
p.A
p.A
p.A
p.A
6.2
kS1
Product Specification
Signetics Linear Products
TDA3047
IR Preamplifier
DC ELECTRICAL CHARACTERISTICS (Continued) vcc = va = 5V; TA = 25'C, measured in Figure 3, unless otherwise
specified.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
4.05
V
Pulse shaper (Pin 11)
V1 1
Trigger level in positive direction
(voltage Pin 9 changes from HIGH to LOW)
3.75
3.9
V 11
Trigger level in negative direction
(voltage Pin 9 changes from LOW to HIGH)
3.4
3.55
3.7
V
LlV11
Hysteresis of trigger levels
0.25
0.35
0.45
V
AGe detector (Pin 12)
-112
112
AGC capacitor charge current
3.3
4.7
6.1
/lA
AGC capacitor discharge current
67
100
133
/lA
2.5
7.5
15
/lA
2.5
7.5
15
/lA
Q-factor killer (Pins 3 and 14)
= 2V
-13
Output current (Pin 3) at V 12 - 16
-114
Output current (Pin 14) at V12 - 16 = 2V
NOTES:
1. Voltage Pin 9 is HIGH; -19 = 75/lA.
2. Voltage Pin 9 remains LOW.
3. Undistorted output pulse with 100% AM input.
FUNCTIONAL DESCRIPTION
General
The circuit operates from a 5V supply and has
a current consumption of 2mA. The output is
a current source which can drive or suppress
current of > 75/lA with a voltage swing of
4.5V. The Q-killer circuit eliminates distortion
of the output pulses due to the decay of the
tuned input circuit at high input voltages. The
input circuit is protected against signals of
> 600mV by an input limiter. The typical input
is an AM signal at a frequency of 36kHz.
Figures 2 and 3 show the circuit diagrams for
the application of narrow-band and wide-band
receivers, respectively. Circuit description of
the eight sections shown in the Siock Diagram are given below.
Controlled HF Amplifier
The input signal is amplified by the gaincontrolled amplifier. This circuit comprises
three DC amplifier stages connected in cascade. The overall gain of the circuit is approximately 83dS and the gain control range is in
the order of 6SdS. Gain control is initially
active in the second amplifier stage and is
transferred to the first stage as limiting in the
second stage occurs, thus maintaining optimum signal-to-noise ratio. Offset voltages in
the DC coupled amplifier are minimized by
two negative feedback loops. These also
allow the circuit to have some series resis-
March 2, 1987
tance of the decoupling capacitor. The output
Signal of the amplifier is applied to the reference amplifier and to the synchronous demodulator inputs.
Reference Amplifier
The reference amplifier amplifies and limits
the input signal. The voltage gain is approximately OdS. The output signal of this amplifier
is applied to the synchronous demodulator.
Synchronous Demodulator
In the synchronous demodulator, the input
signal and reference signal are multiplied.
The demodulator output current is 25/lA
peak-to-peak. The output signal of the demodulator is fed to the input of the AGC
detector and to the input of the pulse-shaper
circuil.
AGC Detector
The AGC detector comprises two NPN transistors operating as a differential pair. The top
level of the output signal from the synchronous demodulator is detected by the AGC
circuit. Noise pulses are integrated by an
internal capacitor. The output signal is amplified and applied to the first and second
stages of the amplifier and to the Q-factor
killer circuil.
Pulse-Shaper
The pulse-shaper comprises two NPN transistors operating as a differential pair con-
5-54
nected in parallel with the AGC differential
pair. The slicing level of the pulse shaper is
lower than the slicing level of the AGC
detector. The output of the pulse-shaper is
determined by the voltage of the capacitor
connected to Pin 11 which is applied directly
to the output buffer.
Output Buffer
The voltage of the pulse-shaper capacitor is
fed to the base of the first transistor of a
differential pair. To obtain a correct RC-5
code, a hysteresis circuit protects the output
against spikes. The output at Pin 9 is active
HIGH.
Q-factor Killer
Figure 2 shows the Q-factor killer in the
narrow-band application. In this application it
is necessary to decrease the Q-factor of the
input selectivity particularly when large input
signals occur at Pins 2 and 15. In the narrowband application the output of the Q-factor
killer can be directly coupled to the input; Pin
3 to Pin 2, and Pin 14 to Pin 15.
Input Limiter
In the narrow-band application, high voltage
peaks can occur on the input of the selectivity
circuit. The input limiter limits these voltage
peaks to approximately 0.7V. Limiting is 0.9V
maximum at 11 = 3mA.
Product Specification
Signetics Linear Products
TDA3047
IR Preamplifier
22
.---.--------------..---'V\fV--- vs= 5.0 VOLT
fO = 36kHz
~ 100"..F_ _ _ _ _--.
II
6.8nF
I--'
o
0.01
0.1
10
100
' - - - - - - - O A T A OUT
V2-1S(mV)
NOTES:
NOTE:
13, 14 ;s measured to ground, V2-15(P.P) is a symmet-
1.0"'16
2. Q"'6
Figure 2. Narrow-Band Receiver Using TDA3047
rical square wave. Measured in Figure 3; Vee = 5V.
Figure 1. Typical Q-Factor Killer
Current (Pins 3 and 14) as a
Function of the Peak-to· Peak
Input Voltage (V2-15)
22
....--"I\fV--- Vs =5.0 VOLT
,--::~=-::-----------
fo:;: 36kHz
12K
BPW~
2.2nF
50
NOTE:
For better sensitivity, both 12kn resistors may have a higher value.
Figure 3. Wide-Band Receiver With TDA3047
March 2, 1987
5-55
•
TDA3048
Signetics
IR Preamplifier
Product Specification
Linear Products
PIN CONFIGURATION
DESCRIPTION
FEATURES
The TDA3048 is for infrared reception
with low power consumption.
• HF amplifier with a control range
of 66dB
• Synchronous demodulator and
reference amplifier
• AGC detector
• Pulse shaper
• Q·factor killing of the input
selectivity, which is controlled by
the AGC circuit
• Input voltage limiter
D, N Packages
INPUT SIGNAL
1
INPUT SIGNAL
2
1S INPUT SIGNAL
Q FACTOR IN 3
FEEDBACK CAP IN 4
13 FEEDBACK CAP IN
FEEDBACK CAP IN 5
12
~~~~~~ME
FEEDBACK CAP IN 6
11
:;~~~I~~~ER
COIL INPUT 7
TOP VIEW
APPLICATION
• IR Remote control systems
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
16·Pin Plastic DIP (SOT-38)
ORDER CODE
_25°C to + 125°C
TDA3048N
o to +70°C
TDA3048TD
16-Pin Plastic SO (SOT-109A)
BLOCK DIAGRAM
4
135
6
7
8
10
2
9
15
3
14
12
November 14, 1986
11
5·56
16
853-0926 86562
Signetics Linear Products
Product Specification
TDA3048
IR Preamplifier
FUNCTIONAL DESCRIPTION
General
The circuit operates from a 5V supply and has
a current consumption of 2mA. The output is
a current source which can drive or suppress
a current of > 75p.A with a voltage swing of
4.5V. The Q·killer circuit eliminates distortion
of the output pulses due to the decay of the
tuned input circuit at high input voltages. The
input circuit is protected against signals of
> 600mV by an input limiter. The typical input
is an AM signal at a frequency of 36kHz.
Figures 2 and 3 show the circuit diagrams for
the application of narrow-band and wide-band
receivers, respectively. Circuit description of
the eight sections shown in the Block Diagram are given below.
Controlled HF Amplifier
The input signal is amplified by the gaincontrolled amplifier. This circuit comprises
three DC amplifier stages connected in cascade. The overall gain of the circuit is approximately 83dB and the gain control range is in
the order of 66dB. Gain control is initially
active in the second amplifier stage and is
transferred to the first stage as limiting in the
second stage occurs, thus maintaining optimum signal-to-noise ratio. Offset voltages in
the DC coupled amplifier are minimized by
two negative feedback loops. These also
allow the circuit to have some series resis-
tance of the decoupling capacitor. The output
signal of the amplifier is applied to the reference amplifier and to the synchronous demodulator inputs.
Reference Amplifier
The reference amplifier amplifies and limits
the input signal. The voltage gain is approximately OdB. The output signal of this amplifier
is applied to the synchronous demodulator.
Synchronous Demodulator
In the synchronous demodulator, the input
signal and reference signal are multiplied.
The demodulator output current is 25p.A
peak-to-peak. The output signal of the demodulator is fed to the input of the AGC
detector and to the input of the pulse-shaper
circuil.
AGC Detector
The AGC detector comprises two NPN transistors operating as a differential pair. The top
level of the output signal from the synchronous demodulator is detected by the AGC
circuil. Noise pulses are integrated by an
internal capacitor. The output signal is amplified and applied to the first and second
stages of the amplifier and to the Q-factor
killer circuil.
Pulse-Shaper
The pulse-shaper comprises two NPN transistors operating as a differential pair con-
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
Vcc
Supply voltage (Pin 8)
1"
Output current pulse shaper (Pin 11)
V2 - 1S
V4-13
VS_6
V7 - 10
V9-11
Voltages
Pins 2
Pins 4
Pins 5
Pins 7
Pins 9
between pins 1
and 15
and 13
and 6
and 10
and 11
RATING
UNIT
13.2
V
10
mA
4.5
4.5
4.5
4.5
4.5
V
V
V
V
V
TSTG
Storage temperature range
-65 to + 150
°C
TA
Operating ambient temperature range
-25 to +125
°C
NOTE:
1. All pins except Pin 11 are short-circuit protected.
November 14, 1986
5-57
nected in parallel with the AGC differential
pair. The slicing level of the pulse shaper is
lower than the slicing level of the AGC
detector. The output of the pulse-shaper is
determined by the voltage of the capacitor
connected to Pin 11, which is applied directly
to the output buffer.
Output Buffer
The voltage of the pulse-shaper capacitor is
fed to the base of the first transistor of a
differential pair. To obtain a correct RC-5
code, a hysteresis circuit protects the output
against spikes. The output at Pin 9 is active
LOW.
Q-Factor Killer
Figure 2 shows the Q-factor killer in the
narrow-band application. In this application it
is necessary to decrease the Q-factor of the
input selectivity particularly when large input
signals occur at Pins 2 and 15. In the narrowband application the output of the Q-factor
killer can be directly coupled to the input; Pin
3 to Pin 2 and Pin 14 to Pin 15.
Input Limiter
In the narrow-band application, high voltage
peaks can occur on the input of the selectivity
circuil. The input limiter limits these voltage
peaks to approximately 0.7V. Limiting is 0.9V
max. at 1, = 3mA.
•
Signetics Linear Products
Product Specification
TDA3048
IR Preamplifier
DC ELECTRICAL CHARACTERISTICS Vcc = Vs = 5V; TA = 25'C; measured in Figure 3, unless otherwise specified.
LIMITS
PARAMETER
SYMBOL
UNIT
Min
Typ
Max
Supply (Pin 8)
Vcc
Supply voltage
4.65
5.0
5.35
V
Icc
Supply current
1.2
2.1
3.0
rnA
15
25
5
/lV
/lV
200
mV
Controlled HF amplifier (Pins 2 and 15)
V2- 15
V2-15
Minimum input signal (peak-to-peak value)
at f = 36kHz1
at 1 = 36kHz2
AGC control range (without Q-killing)
60
V2-15
Input signal for correct operation (peak-to-peak value)s
V2-15
Q-killing inactive (Is = 114
V2-15
Q-killing active (114 = Is = max.) (peak-to-peak) value
< 0.5/lA)
66
0.02
dB
140
(peak-to-peak value)
28
Q-killing range
/lV
mV
See Figure 1
Inputs
V2
Input voltage (Pin 2)
2.25
2.45
2.65
V15
Input voltage (Pin 15)
2.25
2.45
2.65
V
R2-15
Input resistance (Pin 2)
10
15
20
kn
3
V
C2-15
Input capacitance (Pin 2)
V'_'6
Input limiting (Pin 1) at I, = 3mA
0.8
0.9
pF
V
-Vg-S
Output voltage HIGH (Pin 9) at -Ig = 75/lA
0.1
0.5
V
Vg
Output voltage LOW (Pin 9) at Ig = 75/lA
0.1
0.5
V
19
Ig
19
Output current; output voltage LOW
-Vg_S = 4.5V
-Vg_S = 3.0V
-Vg_S = 1.0V
Outputs
75
75
75
120
130
140
/lA
/lA
/lA
-Ig
Output current; output voltage HIGH
-Vg_S = 0.5V
75
120
R7-10
Output resistance between Pins 7 and 10
3.1
4.7
6.2
kn
4.05
V
/lA
Pulse shaper (Pin 11)
Vll
Trigger level in positive direction
(voltage Pin 9 changes from HIGH to LOW)
3.75
3.9
V"
Trigger level in negative direction
(voltage Pin 9 changes from LOW to HIGH)
3.4
3.55
3.7
V
AV"
Hysteresis 01 trigger levels
0.25
0.35
0.45
V
AGC detector (Pin 12)
-112
AGC capacitor charge current
3.3
4.7
6.1
/lA
1'2
AGC capacitor discharge current
67
100
133
/lA
a·factor killar (Pins 3 and 14)
-13
Output current (Pin 3) at V, 2 = 2V
2.5
7.5
15
/lA
-1'4
Output current (Pin 14) at V'2 = 2V
2.5
7.5
15
/lA
NOTES:
1. Voltage Pin 9 is LOW; I. - 75/lA.
2. Voltage Pin 9 remains HIGH.
3. Undistorted output pulse with 100% AM Input.
November 14, 1986
5-58
Signetics Linear Products
Product Specification
IR Preamplifier
TDA3048
22
r---.-------------~--~~---VS=5~VOLT
~100~F
,.----...,
/
47
6.BnF
nF
o
0.01
0.1
10
100
'--------OATA OUT
V2-1S(mV)
NOTE:
13,1419 measured to ground, V2-15(P-P) is a symmet·
rleal square wave measured in Figure 3; Vee" 5V.
NOTE:
Nl .. 3.21
N2-1
0-16
Figure 1. Typical Q-Factor Killer
Current (Pins 3 and 14) as a
Function of the Peak-to-Peak
Input Voltage
Figure 2. Narrow-Band Receiver Using TDA3048
22
r--__"""':-:-=-----------....--'V\I\r--- Vs= 5.0 VOLT
12K
BPW~
2.2nF
50
NOTE:
For better sensitivity both 12kn resistors may have a higher value.
Figure 3. Wide-Band Receiver With TDA3048
November 14, 1986
5-59
•
AN172
Signetics
Circuit Description of the
Infrared Receiver TDA3047/
TDA3048
Linear Products
Application Note
INTRODUCTION
• Less periphery and no adjustment
points
• Total spread on pulse widening < 10%
by a standard RC·5 signal.
As a successor of the current integrated
circuits TCA440 and NE555 for receiving
infrared remote-controlled signals, a new integrated circuit has been developed.
Besides, the IC is also suitable to be used in a
RC-5 extended receiver and in a wide band
receiver.
Author: A.J.E. Bretveld
In comparison with the TCA440-NE555 combination, this IC is aimed to have a higher
replacement value and improved performance. The TDA3048 is equal to the
TDA3047 except for the polarity of the output
signal.
A standard bipolar process with single layer
interconnect and without collector wall has
been used.
Due to the low currents, a collector wall is not
necessary.
FUNCTIONAL DESCRIPTION OF
THE BLOCK PARTS
GENERAL DESIGN
CONSIDERATIONS
The target of this development is to make a
receiver integrated circuit for infrared remotecontrolled signals which functions optimally in
a narrow-band application.
This integrated circuit shall have the following
advantages in comparison with the present
TCA440-NE555 combination:
• A higher replacement value
• A considerable saving of the current
consumption
• An improvement of the specification
(less spread)
4
lS
r ,··
Figure 1 shows the block diagram of the
TDA3047 and TDA3048.
Amplifier
The input signal is amplified by the gaincontrolled amplifier. The output signal of the
amplifier is fed to the synchronous demodulator inputs and to the reference amplifier.
Reference Amplifier
The reference amplifier amplifies and limits
the input signal. The output signal of this
amplifier is fed to the synchronous demodulator.
135
Synchronous Demodulator
In the synchronous demodulator, the input
signal and reference signal are multiplied.
The output signal of the demodulator is fed to
the input of a pulse·shaper circuit and to the
input of the AGC circuit.
AGC Circuit
The output signal of the synchronous demodulator is fed to the AGC circuit. The top level
of the signal is detected by the AGC detector.
Noise pulses are integrated by an internal
capacitor. The output signal from the AGC
detector is amplified and supplied to the first
and second stage of the amplifier and to the
Q-killing circuit.
Pulse-shaper Circuit
The output of the synchronous demodulator
is also fed to the pulse-shaper circuit. The
slicing level of the pulse-shaper is lower than
the slicing level of the AGC detector.
The output of the pulse-shaper is fed to the
output buffer.
Output Buffer
The output buffer gives for the TDA3047 an
active-high level and for the TDA3048 an
active-low level on the output pin. To obtain a
correct RC-5 code a hysteresis circuit protects the output against spikes.
10
"L-__. -__~ _. • L-______~
14
12
11
Figure 1. Block Diagram of the TDA3047/3048
February 1987
5-60
16
Application Note
Signetlcs Linear Products
Circuit Description of the Infrared Receiver TDA3047/TDA3048
Q-Killing Circuit
In the narrow-band application it is necessary
to degenerate the Q of the input selectivity
particularly when large signals occur at the
input
The output of the Q-killing circuit can be
directly coupled to the input
AN172
APPLICATION
The narrow-band application diagram has
been given in Figure 2 and a lower performance wide-band application diagram in
Figure 3.
Input Voltage Limiter
In the narrow-band application high voltage
peaks can occur on the input selectivity. The
input limiter limits these voltage peaks to
about O.7V.
22
.-----<~-------------<~----'Wlr_--Vs =
5.0 VOLT
. I 100p,-F_ _ _ _ _-,
BPW,
50,
47
nF
6.8nF
~-----·DATAOUT
Figure 2_ Narrow-Band Application Diagram of the TDA3047/3048
22
.----:!"=-::----------....---'w...-- Vs =5.0 VOLT
12K
BPW~
2.2nF
50
~------DATAOUT
Figure 3_ Wide-Band Application Diagram of the TDA 3047/3048
February 1987
5-61
•
Signetics
AN173
Low Power Preamplifiers for IR
Remote Control Systems
Application Note
Linear Products
INTRODUCTION
The monolithic integrated bipolar circuits
TDA3047 and TDA304B are amplifiers intended for use in infrared remote control systems.
Both circuits are excellent and applicable as
narrow-band amplifiers, especially for those
types of remote control concepts which use
the modulated transmission technique. Under
certain conditions both ICs are also applicable as broadband amplifiers. The only difference between the ICs is polarity of the output
signal. This type of IR amplifier offers the
following advantages:
• Low power consumption, typically
10.5mV
• Gain-controlled amplijication, control
range 6edB
• High amplification factor,
ensures a long range
> BOdB,
• Great stability in signal handling
• Demodulation via a synchronous
demodulator
• Automatic limitation of large input
Signals, 600mV
• Independenl of large input amplitude
variations with a Q-killer
• Applicable as narrow-or broadband
amplifier
This circuit proves to be a reliable device with
regard to interference from other IR sources
such as light bulbs, etc.
The automatic gain control (AGC) ensures
very good stability in amplification of large or
low input signals, which correspond to short
or long distances from transmitter to receiver.
FUNCTIONAL DESCRIPTION
The functional block diagram is shown in
Figure 1. The input signal is applied to the
gain-controlled multi:stage differential preamplifier, capacitively-coupled via C2 and Ca.
The capacitors C4 and C5 stabilize the differential preamplifier. Hereafter the signal is fed
to a synchronous demodulator and the reference amplifier, which limits the input signal.
After multiplication of the input and reference
signal by the demodulator, the signal is applied to a pulse-shaper, whose time constant
is controlled by Ca. The same signal is also
used for the feedback loop, resulting in an
automatic gain control defined by the amplitude of the input signal. The AGC acquisition
time is set by C7. The Q-killer limits the
amplification of the tuned input circuit in
conjunction with input amplitude. In this way
the behavior of this device on large amplitude
variations ensures a great stability in the
signal handling. A maximum input limitation is
achieved via the amplitude limiter, typically
activated by a 600mV input signal.
The differential preamplifier has, in principle,
two stages, as shown in Figure 2. Each stage
is stabilized via an external feedback capacitor. Both define the lower boundary of the
frequency, with the greatest influence from C4
because stage 1 has the highest gain. Both
capacitors should be specified so that interference from low frequencies is suppressed.
For instance, bulbs radiate infrared frequencies at (n)(100Hz).
The highest boundary in frequency of this
amplifier is greater than 1MHz and is given by
the internal capacitance of this device.
IR AMPLIFIER
For remote control systems two different
types of amplifiers are available. Both are
described in the following sections.
Narrow-Band Amplifier
The diagram of Figure 3 shows the
TDA3047148 in such an application. Pin 15,
one of the differential inputs, is grounded for
AC, while the second input, Pin 2, is connect-
c.
9
"
t'
Figure 1. F:.mctlonal Block Diagram
February 19B7
5-62
OUTPUT
,.
80014208
Signetics Linear Products
Application Note
AN173
Low Power Preamplifiers for IR Remote Control Systems
rH4
This frequency (fa) is equal to 37.5kHz for the
SAA3004 transmitting chip. The RC combination of 47>2 and O.33/lF suppresses the
unwanted current variations caused by the
supply line.
c.
-H13
5
6
a
TDA3047
(TDA3048)
.......
.......
1>
15
The of the tuned input circuit is practically
defined by the transformer ratio and the input
resistor RIN of the IC. The effect of RIN to the
quality Olaf the coil is negligible, because
RIN is relatively low (typically 16k>2).
<2
./'
/
V1=56dB
V2=26dB
The transformer ratio must be adjusted for
small signals, so that the range is hardly
influenced by component spread and/or tolerances in frequency at both sides in the
system. The
can be calculated from:
a
a ----!..---~ /C1 L!I1
Figure 2
RL1V
47
r---------------------------~~--~--~~--VS=5V
+
33
"F~
t+ RpV C,
where RL1 is the ohmic resistance of the coil
and the parallel resistor Rp = n2 RIN1.
With the component values shown in Figure 4
and a given RL1 = 125>2, RIN = 16kn., the
factor a is calculated as 0= 13. The bandwidth is now known from
fa
Ilf = - = 2.9kHz
6.8
470
nF
pF
The ratio is n = C1a + C1b
Clb
Figure 3
~
With values of C1a = 2.2nF, Clb = 560pF and
Ll = 40mH, about the same input quality will
be obtained.
if
""""
The AGC acquisition time and the time constant of the pulse-shaper are defined by the
capacitors C7 and Ca, respectively. The time
constant at Pin 12 equals the length of a
received data bit and Ca delays the pulseshaper output to the output stage.
14~'5
The as of the tuned circuit of the synchronous demodulator is practically given by the
internal resistance, RIN2, between Pins 7 and
10 and is calculated from
,
:
Clb
c,
~
f"
(TDA3CI4a)
,
L
~
TCOl530S
Figure 4
ed to the tuned input circuit via a capacitor of
O.056/lF. The input voltage is taken with a
transformer ratio N = 1:3. Direct coupling to
the top will only lower the quality a factor of
the tuned input circuit, due to the relatively
low input resistor, RIN, of the IC.
The selectivity is obtained with the tuned
input circuit and strongly reduces IR interierences. The effect of direct IR radiation is also
February 1967
a
The transformer ratio can also be realized
with two capacitors in series, as shown in
Figure 4, where the total capacity is equal to
the required one.
avoided. Due to the low ohmic resistance of
the coil, the IR receiving diode will never
become saturated. The center frequency of
the input tank must be equal to the modulation frequency of the transmitter used.
For this frequency (fa) the input tank has a
high impedance. Small variations of the current of the IR receiving diode at fa result
directly in large input signals.
5-63
Os=--------~------
./Ca
1~1L2
RL2V-;-"+-V~
L2 Rln2
Cs
with 12n. for RL2 and 5kn. for RIN, as"'" 7.
The quality as is continuously limited. With a
relatively high value for as, the acquisition
time will be increased and this will delay the
pulse edges. By amplification of "biphase"
modulated signals, disturbances could occur
in the decoding. For correct decoding of
•
Signetlcs Linear Products
Application Note
Low Power Preamplifiers for IR Remote Control Systems
47
r---------------------------~--t+~~~~~~--V.=5V
"F~
12K
AN173
ses, each of B.BIlS width. In the modulated
output mode, each active output stage has a
burst of 6 clock periods.
The ground wave of this output, with a
frequency of 3BkHz, contains the IR power
generated.
10nF
2.2
nF
'------g~~
The greatest sensitivity is realized with a
narrow-band amplifier, whose tuned input circuit is selected for this ground wave frequency.
In the unmodulated transmission mode, the
single output pulse represents a continuous
frequency spectrum, in which the generated
IR power is divided. A broadband amplifier is
then required.
TC01540S
Figure 5
"biphase" coded data, a nearly exact position of the pulse edges is required.
Broadband Amplifier
The application as broadband amplifier is
shown in Figure 5. The IR receiving diode is
now positioned between both differential inputs, while the series resistors of 12kn are
the work resistors. The Q killer and Amplitude
Limiter do not have any function here and are
not used. Also the resonance frequency, fo,
of the tuned demodulator circuit equals the
modulation frequency of the remote transmitter.
The charge current to capacHor Ca is equal to
IlVcs
Ics= (Cs)Tt
where Ilt is the charge time and Il VCs is the
voltage increment. ICa is generated by an
internal current source.
The voltage increment at Cs is proportional to
Ilt, with ICs constant and expressed as
(lcs)(llt)
IlVcs=-c;The pulse width, Ilt, of the demodulated
signal must be large enough that VCs exceeds the threshold voltage of the pulseshapero
Given the format of the received data, Cs will
have different values
I
Pulse Width
SAA3004
B.BIlS
I
Ca
2.2nF
A 2.2nF capacitor in the SAA3004 remote
control system is an optimum one.
February 19B7
The SAA3004, used in unmodulated mode,
has a pulse width of B.BIlS. Cs must have a
low value so that the threshold voltage of the
pulse-shaper is exceeded. On the other hand,
if Cs becomes too small, interference pulses
will easily trigger the pulse-shaper. The selection of Cs is a compromise between the
sensitivHy of the amplifier and the immunity
against interference. Such a compromise is a
2.2nF capacitor for the unmodulated mode of
the SAA3004, including the tolerances of the
internal current sources. Given the technology, small tolerances are not possible.
Correct operation can not be guaranteed for
the combination of a small pulse width (B.BIlS)
and a low source current. However, practical
tests did show that correct operation of the
SAA3004, in the unmodulated mode In combination with this type of preamplifier, can be
realized.
CONSIDERATIONS FOR
AMPLIFIER SELECTION
The narrow- or broadband application is defined by the following points:
• Modulation mode of the transmitter
• Requirements for the reach in distance
• Reliability (insensitivity to interference)
• Price-attractive total remote control
system
Either modulated or unmodulated data transmission is possible with the SAA3004.
In the unmodulated mode, the logic representation of the data word is defined by the time
intervals between the generated output pul-
5-64
The greatest range, with constant-current
through the IR transmission diode(s), will be
obtained with a narrow-band amplifier, because the signal-to-noise ratio is the largest
value.
When IR interference is absent, the combination of modulated transmission mode and the
narrow-band amplifier is the most preferable.
With lower requirements for the reliability,
less range, etc., the broadband amplifier is
the most effective solution for both types of
modulation modes.
RANGE
To give some idea what range can be expected, a number of measurements are made
with the remote transmitters SAA3004.
With Various IR Output Powers
Transmitter SAA3004 drives 1 IR-transmitting
diode with a peak current IC~2A. In the
modulated mode, the power product per bit
equals
(m) (IF) (n) (tp)
where m = number of diodes, n = number of
pulses per bit, and tp = pulse width.
The power product for each bit is:
• Modulated mode (m) (IF) (n) (tp) = (1)
(2) (6) (B.B) = lOellA/sec
• Unmodulated mode (m) (IF) (n) (tp) = (1)
(2) (1) (B.B) = lBIlA/sec
This power product is proportional to the
generated IR power. Table 1 indicates the
results of the measurements. Optic lenses
will increase the distances about 10%.
With Equal Output Power
These measurements are done with one
tranSrTlitting diode for each transmitter type
Application Note
Signetics Linear Products
Low Power Preamplifiers for IR Remote Control Systems
Table 1. Distance Reach With Various Power Products
AN 173
the loss of power in the transmitter is of
subordinate importance.
SAA3004
Modulated
Unmodulated
106).lA/sec
18).lA/sec
Narrow-band
Ca = 4.7nF
25mt
11mt
Broadband
Ca = 2.2nF
16mt
12mt
Power product
Table 2. Distance Reach With Constant Power Product of
18MA/sec
Modulated
Unmodulated
Narrow-band
Ca = 4.7nF
11mt
11mt
Broadband
Ca = 2.2nF
8mt
12mt
Table 3. Application Possibilities
SAA3004
Unmodulated
Modulated
Narrow-band
No sense; no selectivity
Great distance reach, high selectivity, reliable
Broadband
Function only possible
with small width output
pulse; less reliable
Low reach, low selectivity; interference.
a.
b.
Results of the Measurements
The results of the measurements can be
summarized as follows:
February 1987
c.
In comparison with older types of preamplifiers, the power consumption is enormously
reduced. For instance, the TDB2033 consumed 204mW at 12V supply, while the
TDA3047/48 only takes 10mW at 5V supply,
which is very useful for "standby" mode. A
second advantage is the 5V supply which can
also be used by the decoding microcomputer.
POSSIBLE APPLICATION
COMBINATIONS
SAA3004
and the power product/bit constant at
18).lA/sec. Table 2 is comprised of the results
from these measurements.
POWER DISSIPATION
Only the combinations "modulated and
narrow-band amplifier" are reasonable.
With the peak current IF through one IRtransmitting diode, the range with one IR
diode is limited.
A maximum range is obtained using the
modulated mode of data transmitting, but
5-65
In Table 3, the different combinations are
given for remote control systems operating in
the modulated or un modulated mode.
OUTPUT SIGNAL
As indicated in the introduction, the TDA3047
has an active-high output signal, while an
active-low output is generated by the
TDA3048. This choice in polarity is made
available for maximum cooperation with the
decoding part. II, for example, an 8048 microcomputer is used on interrupt level, with
active-low at input INT, the TDA3048 is then
the correct amplifier. II the INT input is activeHigh, the TDA3047 outputs the proper high
level.
PC BOARD DESIGN
Special attention must be given to the placement of Cs. The greatest distance must be
realized between the position of this capacitor
and the inputs 2 and/or 15. Ground connections and screening must also be done with
great accuracy.
•
Signetics
Section 6
Television Subsystems
Linear Products
INDEX
TDA4501
TDA4502
TDA4503
TDA4505, A, B
Small· Signal
Small·Signal
Small·Signal
Small·Signal
Subsystem
Subsystem
Subsystem
Subsystem
IC for Color TV................................
IC for Color TV With Video Switch.......
for Monochrome TV ..........................
IC for Color TV................................
6·3
6·13
6·15
6·24
•
TDA4501
Signetics
Small-Signal Subsystem IC
for Color TV
Product Specification
Linear Products
DESCRIPTION
FEATURES
The integration into a single package of
all small-signal functions (except the
tuner) required for color TV reception is
achieved in the TDA4501. The only additional circuits needed to complete the
receiver are a tuner, the deflection output stages, and a color decoder. The
TDA3563 or 67, NTSC color decoder,
and TDA3653, vertical output, are ideal
complements for the TDA4501.
• Vision IF amplifier with
synchronous demodulator
• AGC detector for negative
modulation
• AGC output to tuner
• AFC circuit
• Video and audio preamplifiers
• Sound IF amplifier and
demodulator
• Choice of sound volume control
or horizontal oscillator starting
function
• Horizontal synchronization circuit
with two control loops
• Triggered divider system for
vertical synchronization and
sawtooth generation giving
automatic amplitude adjustment
for 50 or 60Hz vertical signal
• Transmitter identification circuit
with mute output
• Sandcastle pulse generator
The IC includes a vision IF amplifier with
synchronous demodulator and AFC circuit, an AGC detector with tuner output,
an integral three-level sandcastle pulse
generator, and fully synchronized vertical and horizontal drive outputs. A triggered vertical divider automatically
adapts to a 50 or 60Hz vertical signal
and eliminates the need for an external
vertical frequency control.
Signal strength-dependent, time constant switches in the horizontal phase
detector make external VCR switching
unnecessary.
PIN CONFIGURATION
N Package
AGC
TAKEOVER
RAMP
'ZI SANDCASrLE
OUT2
GEN
VERTDRIVE 3
VERT
FEEDBACK
TUNER
AGC
24
~WrROL
22 COINDET
DECOUP
21 SYNC DEMOD
c~c~t~
~~g
sg~J~
11
13
14
ltIPVIEW
APPLICATION
Sound signals are demodulated and amplified within the IC in a circuit which
includes volume control and muting.
• Color TV
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
-25·C to +65·C
TDA4501N
28-Pin Plastic DIP (SOT-117)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
VCC=V7-S
Supply voltage (Pin 7)
13.2
V
1.7
W
PTOT
Total power dissipation
TA
Operating ambient temperature range
-25 to +65
·C
TSTG
Storage temperature range
-65 to +150
·C
December 2, 1986
6-3
853-1061 86703
I
Signetics Linear Products
Product Specification
TDA4501
Small-Signal Subsystem IC for Color TV
BLOCK DIAGRAM
20
21
17
15
14
13
B0081918
December 2. 1986
6-4
Product Specification
Signetlcs Linear Products
TDA4501
Small-Signal Subsystem IC for Color N
DC AND AC ELECTRICAL CHARACTERISTICS Vce = V7_6 = 10.5V; TA = 25'C, unless otherwise specilied.
LIMITS
UNIT
PARAMETER
SYMBOL
Min
Typ
Max
9.5
10.5
13.2
Supplies
V
Vee
Supply voltage (Pin 7)
Icc
Supply current (Pin 7)
120
V11_6
Supply voltage (Pin 11)
10.5
V
111
Supply current (Pin 11) lor horizontal oscillator start
6
mA
mA
Vision IF amplifier (Pins 8 and 9)
VS_9
Input sensitivity at 38.9MHz1
VS-9
Input sensitivity at 45.75MHz1
90
MV
RS-9
Differential input resistance (Pin 8 to 9)
1.3
kr!
CS-9
40
70
120
MV
Differential input capacitance (Pin 8 to 9)
5
pF
AGC range
60
dB
70
mV
1
dB
4.5
V
V
50
VS-9
Maximum input signal
fJ.V17_6
Expansion 01 output signal lor 50dB variation 01 input signal with
VS-9 at 150MV (OdB)
Video amplifier
V17_6
Output level lor zero signal input
(zero point 01 switched demodulator)
V17-6
Output Signal top sync level 2
1.4
V17-6(P.P)
Amplitude 01 video output signal (peak-to-peak value)
2.8
V
117(INn
Internal bias current 01 output transistor (NPN emitter-Iollower)
2.0
rnA
BW
Bandwidth 01 demodulated output signal
6
MHz
dG17
Differential gain (Figure 3)
6
%
dp
Differential phase (Figure 3)
4
1.4
SIN
SIN
%
10
Video non-linearity complete video signal amplitude
%
Intermodulation (Figure 4) at gain control = 45dB
1= 1.1 MHz; blue;
1= 1.1 MHz; yellow;
1= 3.3MHz; blue;
1= 3.3MHz; yellow
55
50
60
55
60
54
66
59
dB
dB
dB
dB
Signal-to-noise ratioS
Zs=75Q
VI = 10mV
End 01 gain control range
50
50
54
56
dB
dB
Residual carrier signal
7
30
mV
Residual 2nd harmonic 01 carrier signal
3
30
mV
December 2, 19S6
6-5
I
Product Specification
Signetics Linear Products
TDA4501
Small-Signal Subsystem IC for Color TV
DC AND AC ELECTRICAL CHARACTERISTICS (Continued)
vcc = V7 _6 = 10.5V; TA = 25°C, unless otherwise
specified.
LIMITS
UNIT
PARAMETER
SYMBOL
Min
Typ
Max
Tuner AGC 4
Vl _ 6
Take-over voltage (Pin 1) for positive-going tuner AGC
(NPN tuner)
Vl - 6(RMS)
Starting point takeover; V = 5V
V
3.5
0.4
2
mV
mV
8
V
Vl-6(RMS)
Vl-6
Take-over voltage (Pin 1) for negative-going tuner AGC
(PNP tuner)
Vl - 6(RMS)
Starting point takeover; V = 9.5V
Vl -6(RMS)
Starting point takeover; V = 5.6V
50
70
mV
2
3
mA
15 MAX
Maximum output swing
VS-6(SAT)
Output saturation voltage I = 2mA
15
Leakage current
Ll.VI
Input signal variation complete tuner control
50
70
Starting point takeover; V = 1.2V
0.3
2
300
0.5
2
mV
mV
1
pA
4
dB
AFC circuit (Pin 18)5
V18 - 6(P-P)
AFC output voltage swing
± 118
Available output current
9
10
Control steepness
100% picture carrier
10% picture carrier
V18-6
Output voltage at nominal tuning of the reference-tuned circuit
V18-6
Output voltage without input signal
20
40
15
2.7
5.25
80
mY/kHz
mY/kHz
8.5
V
5.25
,
V
mA
1
V
Sound circuit
V1SLlM
Input limiting voltage
Vo = Vo maximum -3dB; QL = 16
fAF = 1kHz; fc = 5.5MHz
400
p.V
R1S -6
Input resistance VI(RMS) = 1mV
2.6
kn
C1S -6
Input capacitance VI(RMS) = 1mV
6
pF
AMR
AMR
AM rejection (Figures 7 and 8)
VI = 10mV
VI =50mV
35
43
dB
dB
320
mV
150
n
V12-6(RMS)
AF output signal Ll.f = 7.5kHz; minimum distortion
Z12-6
AF output impedance
THO
Total harmonic distortion Ll.f = 27.5kHz
1
%
RR
RR
Ripple rejection
fK = 100Hz, volume control 20dB
when muted
22
26
dB
dB
V12-6
Output voltage Mute condition
2.6
V
SIN
Signal-to-noise ratio weighted noise (CCIR 468)
47
dB
December 2, 1986
6-6
220
Signetics Linear Products
Product Specification
TDA4501
Small-Signal Subsystem IC for Color TV
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) vee = V7 - 6 = 10.5V; TA = 25°C, unless otherwise
specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
Volume control
V11-6
Voltage (Pin 11 disconnected)
4.B
V
111
Current (Pin 11 short-circuited)
1
mA
R11 - 6
External control resistor
10
kQ
Suppression output signal during Mute condition
66
dB
Horizontal synchronization
Slicing level sync separator
30
%
Holding range PLL
BOO
1100
Catching range PLL
600
1000
Hz
2
3
6
kHz//ls
kHz//ls
kHz//ls
Control sensitivity
video-to-oscillator; at weak signal
at strong signal during scan
during vertical retrace and during catching
1500
Hz
Second control loop (positive edge)
Ato/Ata
Control sensitivity
300
/ls
to
Control range
25
/ls
Phase adjustment via second control loop;
control sensitivity
maximum allowed phase shift
25
±2
MA//ls
/ls
15,625
Hz
Horizontal oscillator (Pin 23)
fFA
Free-running frequency
R = 35kQ; C = 2.7nF
Spread with fixed external components
AfFA
Frequency variation due to change of supply voltage from
B to 12V
AfFA
Frequency variation with temperature
AfFA
Maximum frequency shift
AfFA
Maximum frequency deviation (V7-6
a
4
%
0.5
%
1 X 10- 4
= BV)
K- 1
10
%
10
%
Horizontal output (Pin 26)
V26 - 6
Output voltage HIGH
13.2
V
V26 - 6
Output voltage at which protection commences
15.8
V
V26-6
Output voltage LOW at 126
00
Duty cycle of horizontal output signal
45
%
tA, tF
Rise and fall times of output pulse
150
ns
December 2, 1986
= 10mA
0.3
6-7
0.5
V
•
Signetics Linear Products
Product Specification
TDA4501
Small-Signal Subsystem IC for Color TV
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) vcc = V7-6 = 10.5V; TA = 25°C, unless otherwise
specified.
LIMITS
PARAMETER
SYMBOL
UNIT
Typ
Min
Max
Flyback Input and sandcastle output
mA
127
Input current required during flyback pulse
0.1
V27-6
Output voltage during burst key pulse
7.5
V27-6
Output voltage during horizontal blanking
3.5
4.0
4.5
V27-6
Output voltage during vertical blanking
1.8
2.2
2.6
V
Width of burst key pulse
3.1
3.5
3.9
IJ.s
Width of horizontal blanking pulse
2
V
V
flyback pulse width
Width of vertical blanking pulse
50Hz working
60Hz working
Delay between start of sync pulse at video output and rising
edge of burst key pulse
21
17
lines
lines
5.2
IJ.s
Coincidence detector mute output (Pin 22)
V22 - 6
Voltage for in-sync condition
9.5
V22-6
Voltage for no-sync condition no signal
1.0
1.5
V
V22-6
Switching level to switch phase detector from slow to fast
5.3
5.8
V
4.9
Fast-to-slow hysteresis
V
V
1
V22-6
SWitching level to activate mute function (transmitter
identification)
2.25
2.5
2.75
122(P-P)
Output current for in-sync condition (peak-to-peak value)
0.7
1.0
mA
V
Vertical ramp generator (Pin 2)
12
Input current during scan
12
mA
12
Discharge current during retrace
0.5
mA
V2_6
Minimum voltage
1.5
V
Vertical output (Pin 3)
Is
Output current
RS-6
Output impedance
10
mA
400
n
3
1.2
V
V
Feedback Input (Pin 4)
V4_6
V4_6(P_P)
Input voltage
DC component
AC component (peak-to-peak value)
14
Input current
12
Internal precorrection to samooth
6
Deviation amplitude 50/60Hz
3. Signal-to-noise ratio equals 2010g
VN(RMS) at B = 5MHz
4. Starting point tuner takeover NPN current I.SmA;
5. V'(RMS) = 10mV; see Figure 1; Q-factor = 36.
December 2, 1986
%
5
NOTES:
1. Typical value taken at starting level of AGe.
2. Signal with negative-going sync, maximum white level 10% of the maximum sync amplitude (see Figure 2).
Vo(black-to-white)
6-8
p.A
%
Signetics Linear Products
Product Specification
Small-Signal Subsystem IC for Color TV
FUNCTIONAL DESCRIPTION
IF Amplifier, Demodulator, and
AFC
The IF amplifier has a symmetrical input (Pins
8 and 9), the input impedance of which is
suitable for SAW filtering to be used. The
synchronous demodulator and the AFC circuit
share an external reference tuned circuit
(Pins 20 and 21). An internal RC network
provides the necessary phase-shifting for
AFC operation. The AFC circuit provides a
control voltage output with a swing greater
than 9V from Pin 18.
AGC Circuit
Gating of the AGC detector is performed to
reduce sensitivity of the IF amplifier to external electrical noise. The AGC time constant is
provided by an RC circuit connected to Pin
19. Tuner AGC voltage is supplied from Pin 5
and is suitable for tuners with PNP or NPN RF
stages. The sense of the AGC (to increase in
a positive or negative direction) and the point
of tuner take-over are preset by the voltage
level at Pin 1.
Video Amplifier
The signal through the video amplifier comprises video and sound information; therefore, no gating of the video amplifier is
performed during flyback periods.
December 2, 1986
TDA4501
Sound Circuit and Horizontal
Oscillator Starting Function
the system works in the 60Hz mode; otherwise, 50Hz working is chosen.
The input to the sound IF amplifier is obtained
by a bandpass filter coupling from the video
output (Pin 17). The sound is demodulated
and passed via a dual-function volurne control stage to the audio output amplifier. The
volume control function is obtained by connecting a variable resistor (10kn) between
Pin 11 and ground, or by supplying Pin 11 with
a variable voltage. Sound output is suppressed by an internal mute signal when no
input signal is present.
A narrow window is opened when 15 approved sync pulses have been detected.
Divider ratio between 522 and 528 switches
to 60Hz mode; between 622 and 628
switches to 50Hz mode.
The horizontal oscillator starting function is
obtained by supplying Pin 11 with a current of
6mA during the switching-on period. The IC
then uses this current to generate drive
pulses for the horizontal deflection. For this
application, the main supply voltage for the IC
can be obtained from the horizontal deflection circuit.
Vertical Divider System
A triggered divider system is used to synchronize the vertical drive waveforms, adjusting
automatically to 50 or 60Hz working. A large
window (search window) is opened between
counts of 488 and 722; when a separated
vertical sync pulse occurs before count 576,
6-9
The vertical blanking pulse is also generated
via the divider system by adding the antitopflutter pulse and the blanking pulse.
Line Phase Detector
The circuit has three operating conditions:
a. Strong input signal and synchronized.
b. Weak signal and synchronized.
c. Non-synchronized (weak and strong) signal.
The input signal condition is obtained from
the AGC circuit.
DC Volume Control/Horizontal
Oscillator Start
The operation depends on the application.
When during switch-on no current is supplied,
Pin 11 will act as volume control. When a
current of 6mA is applied, the volume control
is set to maximum and the circuit will generate drive pulses for the horizontal deflection.
•
Product Specification
Signetics Linear Products
TDA4501
Small-Signal Subsystem IC for Color TV
22k
47k
,.. :..>--
47k
22k
+
+
82k
.
~~F
AGC
28
I
2
Z7
r
I
....
HORIZONTAL FLYBACK
DRIVE
VERTICAL
SANDCASTLE
2.7k
220nF
VERTICAL
+
I
28
3
-=
HORIZONTAL DRIVE
880k
I
25
4
FEEDBACK
+
BBnF
820
BBnF
24
5
TUNERAGC
I
6
.,r-
1.8k
+I~
2.?nF
82k
7
Vcc+
I
23
II
27k
22nF
IF INPUT
i~
JIC-~
.L
I
TDA4501
201r
Uk
+mpF~Uk
330k
h
i~
+
AFC
~
,.--s
13
mk
T
18
17
I ..
15
'f
BBPF
~~F
Figure 1. Application Diagram
1.00V
0.95V
O.30V
6-10
I, SFE
5.5MB
I
Figure 2. Video Output Signal
2.2k
.J.-
~I
-=
December 2, 1986
II-+
I
~~F
1pF
+
mk
12
~
180k
I
19
....lOk
~PF
L-
21
11
AUDIO
OUTPUT
1O~
....
22
i~
....
~7k
Uk
820k
+
1
880
VIDEO
our
Signetics Linear Products
Product Specification
Small-Signal Subsystem IC for Color TV
TDA4501
1.00V
O.86V
O.72V
O.58V
O.44V
O.30V
10 12
22
28
3238
4ll
44
48
5258
6064""
OP1S06QS
Figure 3. EBU Test Signal Waveform (Line 330)
-3.2dB
•
-10dB
-13.2dB
-13.2dB
T
-lB
SC CC
PC
SC CC
PC
YELlDW
BLUE
SC: SOUND CARRIER LEVEL
CC: CHROMINANCECARRIER LEVEL
PC: PICTURE CARRIER LEVEL
ALL WITH RESPECT TO TOP SYNC LEVEL
OPl6030S
Figure 4. Input Signal Conditions
PC
GENERATOR
38.9MHz
SC
GENERATOR
33.4MHz
K?CC
GENERATOR
34.5 MHz
ATIENUATOR
r
t--
TEST
CIRCUIT
;---1
i
SPECTRUM
ANALVZER
0+
GAIN SETTING ADJUSTED
FOR BWE;V16 =2.5V
B0092805
Figure 5. Test Setup Intermodulalion
December 2. 1986
6-11
Signetlcs Linear Products
Product Specification
TDA4501
Small-Signal Subsystem IC for Color TV
60
,.
40
20
o
-20
-40
-60
V,(dB)
Figure 6. SIN Ratio as a Function of
the Input Voltage
Figure 7. Test Setup AM Suppression
50
/
......
45
-20
/
//
iii
:s
z
o
~ 40
V
iil
a:
""
iii
/
/
-40
:s
.:f -60
/
35
30
,..,
-60
/
-100
o
20
40
60
V15 (mV)
60
100
/
o
0.4
0.8
1.2
1.6
2.0
2.4
V,M
QP15910S
Figure 8. AM Rejection
December 2. 19B6
Figure 9. Volume Control
Characteristics
6-12
TDA4502
Signetics
Small-Signal Subsystem IC for
Color TV With Video Switch
Objective Specification
Linear Products
DESCRIPTION
The TDA4502 is a TV subsystem circuit
intended to be used in color TV receivers. It is similar to the TDA4505, with the
exception that it has no sound IF circuit
or audio preamplifiers. Instead, it has a
video switching input circuit for switching
an external video signal.
FEATURES
• Vision IF amplifier with
synchronous demodulator
• AGC detector suited for negative
modulation
•
•
•
•
Tuner AGC
AFC circuit with on/off switch
Video preamplifier
Video switch for an external
video signal
• Horizontal synchronization circuit
with two control loops
• Vertical synchronization (divider
system) and sawtooth generation
• Sand castle pulse generation
PIN CONFIGURATION
AGC
TAKEOVER
VERT
RAMPGEN
VERT DRIVE 3
VERT
FEEDBACK
TUNER
AGC
Vee
•
7
VISION
IFIN
VISION
IFIN
DECOUPCAP
c~~fiIl~t~
11
EXTERNAL
VIDEO IN
MUTE
SWITCHING
VIDEO OUT
TOP VIEW
February 1987
6-13
Objective Specification
Signetics Linear Products
Small-Signal Subsystem IC for Color TV With Video Switch
BLOCK DIAGRAM
February 1987
6-14
TDA4502
TDA4503
Signetics
Small-Signal Subsystem for
Monochrome TV
Product Specification
Linear Products
DESCRIPTION
The TDA4503 combines all small-signal
functions (except the tuner) which are
required for monochrome TV receivers.
For a complete monochrome TV receiver only power output stages are required
to be added for horizontal and vertical
deflection, video and sound. This part is
designed to work with the TDA3561,
Vertical Output IC.
The TDA4503 can also be used in low
cost color television receivers.
FEATURES
• Vertical sync separator and
oscillator
• Video preamplifier
• AGC detector
• Sync separator
• Horizontal synchronization
• Vision IF amplifier and
synchronous demodulator
• Tuner AGC
• AFC circuit
• Sound IF amplifier and
demodulator
• Audio preamplifier with DC
volume control
• Gate pulse generator
APPLICATIONS
• Television receiver
• CATV converter
PIN CONFIGURATION
VERTOSCIN
1
VERT DRIVE
01lT
VERT DRIVE
FEEDBACK
TUNER
25 HORIZ PHASE
DETFlU'ER
TAKEOVER IN
FLYBACK
24
PULSE IN
AGCOIIT
10 TUNER
~~J:.~T
VOL CONTROL 11
lOP VIEW
ORDERING INFORMATION
DESCRIPTION
28-Pin Plastic DIP (SOT-117)
March 2, 1987
TEMPERATURE RANGE
ORDER CODE
-25°C to +65°C
TDA4503N
6-15
853-119487841
•
Product Specification
Signetics Unear Products
TDA4503
Small-Signal Subsystem for Monochrome TV
BLOCK DIAGRAM
lIII
17
21
•
TDA4603
~ r-
AFC DETECtOR
a OUTPUT
STAGE
-
10°
PHASE SHIFT
VIDEO
AMPUFIER
-
~
18
I
o-! ro-! r-
IFAMPUFIER
OVERlOAD
DETEClOR
a fEED.
BACKSTAGE
I
28
~
~ I-
AGe
DETEC10R
1
I
-
I
o-!
o-!
I
..
GENERAtOR
+
..
TUNER
TAK60VER
CIRCUIT
,
~
-
I
March 2, 1987
HORIZONTAL
OSCILUOOR
,
~27
SOUND AMP
UMITER&
FEEDBACK
STAGE
-
SOUND
SYNCHRONOUS
DEMODUUOOR
,
-
-
MUTE
VERTICAL
OSCILUOOR
'----'
,
VERTICAL
OUTPUT I
FEEDBACK
STAGE
6-16
1
~2
l- ~
~
,
AUDIO
OUTPUT
AMPUFIER
I-3
I- ..!!.o
+
IIOWME
CONTROL
I
22
~~
19
VERTICAL
SYNC
SEPARAtOR
I
23
FIIl'ER
f
HORIZONTAL
DRIVE
OUTPUT STAGE
TUNER AGe
OUTPUT STAGE
~8
COINCIDENCE
DETECtOR
PHASE DETECTOR
&
AFCSTAGE
G.VEPULSE
LOWPASS
28
,
I
-
I
SYNC
SEPARAtOR
t
25
SYNCHRONOUS
DEMODUUOOR
~ 12
I- .!!..o
Product Specification
Signetics Linear Products
TDA4503
Small-Signal Subsystem for Monochrome TV
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
VCC=V7 _ 10
Supply voltage (Pin 7)
13.2
V
PTOT
Total power dissipation
1.7
W
TA
Operating ambient temperature range
-25 to +65
'C
TSTG
Storage temperature range
-65 to +150
'C
DC AND AC ELECTRICAL CHARACTERISTICS
V7 - 10 = 10.5V; V22-10 = 10.5V; TA = 25'C, unless otherwise specified.
LIMITS
PARAMETER
SYMBOL
UNIT
Min
Typ
Max
9.5
10.5
13.2
V
82
100
mA
10.5
13.2
V
5
6.5
mA
920
1150
mW
80
120
!LV
Supplies
V7-10
Supply voltage (Pin 7)
17
Supply current (Pin 7)
V22-10
Supply voltage (Pin 22)
122
Supply current (Pin 22) 1
PTOT
Total power dissipation
9.5
Vision IF amplifier (Pins 8 and 9)
VB-9
Input sensitivity at 38.9 MHz2
VB_9
Input sensitivity at 45.75 MHz2
90
!LV
RB_9
Differential input resistance (Pin 8 to 9)
1.3
kn
CB_9
40
Differential input capacitance (Pin 8 to 9)
5
pF
AGC range
59
dB
70
mV
VB-9
Maximum input signal
b,V17 -10
Expansion 01 output signal (Pin 17) lor 50dB variation 01 input signal
(Pins 8 and 9)3
50
0.5
1.0
dB
Video ampllfler 4
V17-10
Output level lor zero signal input (zero point of switched demodulator)
4.2
4.5
4.8
V
V17 -10
Output signal top sync level 5
1.25
1.45
1.65
V
V17-10(P.P)
Amplitude 01 video output signal (peak-to-peak value)
2.4
2.7
3.0
117(INT)
Internal bias current 01 output transistor (NPN emitter-loll ower)
1.4
2.0
mA
V
BW
Bandwidth 01 demodulated output signal
5
MHz
G17
Differential gain6 (Figure 5)
6
%
Differential phase6 (Figure 5)
4
Video non-linearity over total video amplitude (peak white to black)
SIN
SIN
SIN
March 2, 1987
%
10
%
Intermodulation (Figures 6 and 7) at gain control = 45dB
1= 1.1MHz; blue
I = 1.1 MHz; yellow
I = 3.3MHz; blue
I = 3.3MHz; yellow
55
50
60
55
60
54
66
59
dB
dB
dB
dB
Signal-to-noise rati0 7
at VI = 10mV
at end 01 AGC range
50
50
54
56
dB
dB
as a lunction 01 input signal
see Figure 8
Residual AM 01 intercarrier output signalB
5
10
%
Residual carrier signal
7
30
mV
Residual 2nd harmonic 01 carrier signal
3
30
mV
6-17
•
Signetics Linear Products
Product Specification
TDA4503
Small-Signal Subsystem for Monochrome TV
DC AND AC ELECTRICAL CHARACTERISTICS (Continued)
V 7 -10
= 10.SV;
V 22 -10
= 10.SV;
TA = 2S'C, unless
otherwise specified.
LIMITS
UNIT
PARAMETER
SYMBOL
Min
Typ
Max
Tuner AGC 9
V4-10
Takeover voltage (Pin 4) for positive-going tuner AGC (NPN tuner)
3.S
VS-9(RMS)
Starting point takeover at V4 -1 0 = SV (RMS value)
0.4
VS-9(RMS)
Starting point takeover at V 4 _ 10 = 1.2V (RMS value)
V4-10
Takeover voltage (Pin 1) for negative-going tuner AGC (PNP tuner)
VS-9(RMS)
Starting point takeover at V4 -10
VS-9(RMS)
Starting point takeover at V4-10 = S.6V (RMS value)
SO
70
mV
16MAX
Maximum tuner AGC output swing
2
3
rnA
V6-10(SAn
Output saturation voltage at 16 = 2mA
16
Leakage current at Pin 6
LlVS_9
Input signal variation required for complete tuner control
= 9.SV
SO
V
2.0
70
mV
8
0.3
(RMS value)
V
2.0
300
O.S
2
mV
mV
mV
1
pA
4
dB
AFC circuit (Pin 16)10
V16-10(P.P)
AFC output voltage swing (peak-to-peak value)
±116
Available output current
9
10
1
Control steepness at
100% picture carrier
10% picture carrier
20
V16-10
Output voltage at nominal tuning of the reference-tuned circuit
V16-10
Output voltage without input signal
40
15
80
mY/kHz
mY/kHz
8.5
V
5.25
2.7
6.0
V
rnA
V
Sound circuit
V15L1M
Input limiting voltage 11 (RMS value) at Vo
R15-10
Input resistance at VI(RMS)
C15-10
Input capacitance at
AMR
AMR
= Vo
MAX-3dB
= 1mV
VI(RMS) = 1mV
AM rejection (Figures 7 and 8) at
VI= 10mV
VI = 50mV
2
mV
2.6
kn
6
pF
35
43
dB
dB
320
mV
150
n
V12-6(RMS)
AF output signal 12 (RMS value)
Z12-10
AF output impedance
THD
Total harmonic distortion12
1
%
RR
RR
Ripple rejection at
fK = 100Hz, volume control 20dB
when muted
22
26
dB
dB
V12-10
Output voltage in mute condition
2.6
V
SIN
Signal-to-noise-ratio; weighted noise (CCIR 468)
47
dB
220
Volume control
V11-10
Voltage (Pin 11 disconnected)
111
Current (Pin 11 connected to ground)
R11 -10
March 2, 1987
6.9
V
1
rnA
External control resistor13
5
kn
Suppression of output signal during mute condition
66
dB
6-18
Product Specification
Signetics Linear Products
Small-Signal Subsystem for Monochrome TV
DC AND AC ELECTRICAL CHARACTERISTICS (Continued)
TDA4503
V7-10 = 10.5V; V22-10 = 10.5V; TA = 25·C, unless
otherwise specified.
LIMITS
PARAMETER
SYMBOL
UNIT
Min
Typ
Max
Phase-locked loop holding range
±800
±1100
Phase-locked loop catching range
±600
1000
Hz
2.3
kHz/j.lS
3
I'S
Horizontal synchronization
Slicing level sync separator14
30
Control sensitivity video to f1yback lS
Delay belween leading edge of sync pulse and zero cross-over of
sawtooth (Pin 5)
%
±1500
Hz
Horizontal oscillator (Pin 23)
fFR
Free-running frequency; R = 35kU; C = 2.7nF
15,626
Spread with fixed external components
Hz
4
%
~fFR
Frequency variation due to change of supply voltage from 8 to 12V
TC
Temperature coefficient
~fFR
Maximum frequency shift
10
%
~fFR
Maximum frequency deviation (V7-10 = 8V)
10
%
0
0.5
1 X 10-
%
·C- 1
Horizontal output (Pin 27)
5
mA
127
Output current
R27
Output impedance
200
n
V27-10
V27-22
Output voltage at 127 = 5mA
1.4
2.5
V
V
a
Duty factor of horizontal output signal 16
tR, tF
Rise and fall times of output pulse
0.35
0.40
0.45
400
%
ns
Flyback Input (Pin 5)
Vs
Amplitude of input pulse
Vs
Voltage at which gate pulse generator changes state 17
2
4
6
0
V
V
Coincidence detector mute output (Pin 28)18
V
V28-10
Voltage for in-sync condition
9.5
V28-10
Voltage for no-sync condition (no input signal)
1.0
1.5
V
V28-10
Voltage level for phase detector to switch from slow to fast
4.1
4.5
V
3.7
Fast-to-slow hysteresis
1
V28-10
Voltage level to activate mute function (transmitter identification)
2.25
2.5
122(p_p)
Output current for in-sync condition (peak-to-peak value)
0.7
1.0
March 2, 1987
6-19
V
2.75
V
mA
•
Signetics Unear Products
Product Specification
Small-Signal Subsystem for Monochrome TV
DC AND AC ELECTRICAL CHARACTERISTICS (Continued)
TDA4503
V7-10 = 10.5V; V22-10
otherwise specified.
= 10.5V;
TA
= 25°C,
unless
LIMITS
PARAMETER
SYMBOL
UNIT
Min
Typ
Max
Vertical oscillator (Pin 1)
fFR
Free-running frequency at C = 220nF; R = 560kO
47.5
Spread with fixed external components
Hz
4
Holding range at nominal frequency
52.5
2 X 10-
TC
Temperature coefficient
AfFR
Frequency variation due to change of supply voltage from
9.5 to 12V
11
Leakage current at Pin 1
%
Hz
3
°C- 1
5
%
1.6
pA
Vertical output (Pin 2)
12
Output current
R2
Output resistance
1
1.3
mA
2
kO
Feedback Input (Pin 3)
V3-10
V3- 1o(P.P)
Input voltage
DC component
AC component (peak-ta-peak value)
13
Input current
AI3
Non-linearity of deflector current at V7.10
4.0
= 10.5V
Delay between leading edge of vertical sync and start of vertical
oscillator flyback
6
5.0
1.2
5.5
V
V
12
pA
2.5
%
10
p.s
NOTES:
1. The horizontal oscillator can be started by supplying a current of 6mA to Pin 22. Taking this current from the mains rectifier allows the positive
supply voltage to Pin 7 to be derived from the horizontal output stage (the load current of Pin 27 Is additional to the 6mA quoted).
2. At start of AGC.
3. Measured with Oda = 200/N.
4. Measured at 10mV (RMS) top sync output signal.
5. Signal with negativ&-going sync; top white = 10% of the top sync amplitude.
6. Measured with test line as shown in Figure 3. The differential gain is expressed as a percentage of the difference in peak amplitudes between the
.Iargest and smallest values relative to the subcarrier amplitude at blanking level. The differential phase is defined as the difference in degrees
between the largest and smallest phase angles.
7. Measured with a source impedanca of 75n.
Signal-to· noise ratio
= 20100
Va black·to·white
V'(RMS) at a
= 5MHz
8. Measured with a sawtooth-modulated input signal: m = 90%; V'(RMS) = 10mV;
Amplitude modulation =
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
Vo SC at top sync-Va SC at white
Va SC at top sync + Va SC at white
X 100%.
(SC - sound carrier)
Starting point of tuner take-over for an NPN tuner Is when 16 = 1.8mA, and for a PNP tuner is when 16 = 0.2mA.
Measured at VB-geRMS) = 10mV and Pin 16 loaded with 2 X 100kn between V7 and ground. Reference tuned circuit O-factor = 36.
Reference tuned circuit Q-factor = 16; audio frequency = 1kHz; carrier frequency = 5.5 MHz.
The demodulator tuned circuit must be tuned for minimum distortion; output Signal Is measured at Ll.f -7.5kHz; other measurements are at
Ll.f = 27.5kHz.
Volume control can be realized by a variable resistor (5kn) connected between Pin 11 and ground, or by a variable voltage direct to Pin 11 (the
low value of input impedanca to Pin 11 must be taken into account).
The sync separator Is nOise-gated; the slicing level is referred to the top sync level and is independent of the video signal. The value stated Is a
percentage of the sync pulse amplitude, the level being dependent on external resistors connected to Pin 26.
The phase detector current is increased by a factor of seven during catching and when the phase detector is switched to 'fast' via Pin 28, thus
ensuring a wide catching range and a high dynamic loop gain.
The negative gOing edge initiates switching·off of the line output transistor (simultaneous driver).
The circuit requires an Integrated flyback pulse. Gate pulses for AGC and coincidence detectors are obtained from the sawtooth waveform.
The functions of in·sync, out-of·sync, and transmitter Identification are combined on Pin 28. For the recaption of VCR signals, V2S must be fixed
between 3V and 4.5V so that the time constant is fast and sound information is presarved.
March 2, 1987
6-20
Signetics Linear Products
Product Specification
TDA4503
Small-Signal Subsystem for Monochrome N
FUNCTIONAL DESCRIPTION
Video Amplifier
IF Amplifier, Demodulator, and
AFC
The video signal output from Pin 17 has a
peak-to-peak value of 3V (top sync level = 1.5V) and carries negative-going sync. In
order to retain sound information at Pin 17,
the video signal is not blanked during flyback
periods.
The IF amplifier operates with symmetrical
inputs at Pins Band 9 and has an input
impedance suitable for SAW filter application.
The amplifier sensitivity gives a peak-to-peak
output voltage of 3V for an RMS input of
701lV. The demodulator and the AFC circuit
share an external reference tuned circuit
(Pins 20 and 21) and an internal RC network
provides the phase-shifting necessary for
AFC operation. The AFC circuit provides a
control voltage output with a (typical) swing of
9V from Pin 16 (Vcc = 10.5V).
AGC Circuit
Gating of the AGC detector is performed to
reduce sensitivity of the IF amplifier to external electrical noise. The AGC time constant is
provided by an RC network connected to Pin
24. The typical gain control range of the IF
amplifier is 60dS. Tuner AGC voltage is
supplied from Pin 6 and is suitable for tuners
with PNP or NPN RF stages. The sense of
the AGC (to increase in a positive or negative
direction) and the point of tuner takeover are
preset by the voltage level at Pin 4 (V 4 = 3.5V
(typ.) for positive AGC; V4 = BV (typ.) for
negative AGC).
March 2, 19B7
Sound Circuit
The sound IF signal present at the video
output (Pin 17) is coupled to the sound circuit
by a bandpass filter to Pin 15. The sound
circuit has an amplifier-limiter stage, a synchronous demodulator with reference tuned
circuit at Pin 13, a volume control stage, and
an output amplifier. The volume control has a
range of approximately BOdS and the audio
output signal at maximum volume and with
Llof = 7.5kHz is 320mV (RMS value). The
sound output signal is suppressed when no
input signal is detected.
Synchronization Circuits
The sync separator sliCing level is determined
by an external resistor network at Pin 26. The
slicing level is referred to the top sync level
and the recommended value for slicing is
30%. Internal protection from electrical noise
is included.
A gated phase detector compares the phase
of the separated sync pulses with a sawtooth
waveform obtained from the flyback pulse at
6-21
Pin 5. In sync and out-of-sync conditions are
detected by the coincidence detector at Pin
2B (this circuit also gives transmitter identification). During the out-of-sync condition, gating of the phase detector is switched off and
the output current from the phase detector
increases to give the detector a short timeconstant and thus a fast response. This
condition can be imposed by clamping the
voltage at Pin 2B to 3.5V for the reception of
VCR signals.
The horizontal oscillator frequency is controlled by the output voltage of the phase
detector circuit. The horizontal drive output
from Pin 27 has a duty factor of 40%.
Vertical sync pulses are separated by an
internal integrating network and are used to
trigger the vertical oscillator. A comparator
circuit compares the vertical sawtooth waveform, generated by the vertical oscillator, with
feedback from the deflection coils, and
supplies the drive voltage for the output stage
at Pin 2.
Power Supplies
The main supply is to Pin 7 (positive supply)
and Pin 10 (ground). The horizontal oscillator
is supplied from Pin 22 to facilitate starting of
the oscillator from a high-voltage rail. A special ground connection at Pin 19 is used by
critical voltage dividers in the feedback loops
of the vision and sound IF circuits.
II
Signetics Linear Products
Product Specification
TDA4503
Small-Signal Subsystem for Monochrome TV
V~R~~~-------------I
F~DMCK------------~~
680k
26
l-_--'110~---~+
68nF
820k
22k
+~
4
~~22nF
25
24"::"
330k
~-.--~~--------~+
1.F
~22nF
TUNERAGC
+~
68nF
I
FL~~~~ __~~____1-~~
1O~
1k
'-----..,+ f--:L
23
~--------......---t
Uk
27k
"::"
1k
Vee 0---------....---1
TDA4503
IF INPUT
~~
______________~~~ONTAL
21
22nF
~nF
{o
0>-----111--1
10
19
11
18
lOnF
1--'----111-- - - ' l
~1~7________1-______."::"WDEO
O~~~~____________1-i2
W
OUTPUT
1.2nF
nF13
1.3k
22nF 14
1
Figure 1. Application Circuit Diagram
1.00V
1.00V
O.95V
O.88V
O.72V
O.58V
o.44V
O.30V
D.3OV
10 12
Figure 2. Video Output Signal
March 2, 1987
22
26
82 38
40
44
48
52
58
Figure 3. EBU Test Signal Line 330
6-22
80 64
.s
Signetics Linear Products
Product Specification
Small-Signal Subsystem for Monochrome TV
TDA4503
-3.2dS
60
.....
-10dS
-13.2dB
-13.2dS
40
T
sc CC
or
:e.
T
z
20
sc cc
PC
BWE
V
iii
PC
YEL1DW
o
sc: SOUND CARRIER LEVel
-40
-60
CC: CHROMINANCE CARRIER LEVel
-20
Vo(dS)
pc; PICTURE CARRIER LEVEl
ALL WITH RESPECTlO lOP SYNC LEVEL
Figure 6. Signal-ta-Noise Ratio as a
Function of Input Voltage
OPl603DS
Figure 4. Input Signal Conditions for Intermodulation Test
50
PC
GENERAlOR
38.9MHz
1/ f--"
45
l / I-'
;'
+
sc
GENERAtoR
33.4MHz
ATTENUAlOR
f--
TESr
r
.i
0+
30
GAIN SETTING ADJUsrED
FOR aWE; VlI = 2.5V
Vo at 4.4MHz
Value at 3.3MHz = 20109
Vo at 1.1MHz
V
o
40
60
V15 (mV)
20
100
60
OP159QOS
BDOB280S
NOTE:
/
35
CC
GENERAlOR
34.5MHz
Value at 1.1 MHz"" 20log
/
SPECTRUM
ANALYZER
f--
CIRcurr
Figure 8. Typical Amplitude Modulation
Rejection Curve
+ 3.6dB;
Vo at 4.4MHz
I-'""
Vo at 3.3MHz
Figure 5. Circuit for Intermodulatlon Test
1/
-20
/
V
j
-60
-100 ~
o
D.4
D.8
1.2
1.6
2.0
2.4
V,M
Figure 9. Volume Control Characteristic
Figure 7. Circuit for Amplitude Modulation Rejection Test
March 2, 1987
6-23
•
TDA4505
Signetics
Small-Signal Subsystem IC for
Color TV
Preliminary Specification
Linear Products
PIN CONFIGURATION
DESCRIPTION
FEATURES
The TDA4505 is a TV subsystem circuit
intended to be used for base-band demodulation applications. This circuit consists of all small-signal functions (except
the tuner) required for a quality color
television receiver. The only additional
circuits needed to complete a receiver
are a tuner, the deflection output stages,
and a color decoder. The TDA3563 or
67, NTSC color decoder, and the
TDA3654 vertical output, are ideal complements for the TDA4505.
• Vision IF amplifier with
synchronous demodulator
• Tuner AGC (negative-going
control voltage with Increasing
signal)
• AGC detector for negative
modulation
• AFC circuit
• Video preamplifier
• Sound IF amplifier, demodulator
and preamplifier
• DC volume control
• Horizontal synchronization circuit
with two control loops
• Extra time constant switches In
the horizontal phase detector
• Vertical synchronization (divider
system) and sawtooth generation
with automatic amplitude
adjustment for 50 or 60Hz
• Three-level sand castle pulse
generation
APPLICATIONS
• Color television receiver
• CATV converters
• Base-band processing
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
28-Pin Plastic DIP (SOT-117)
-25'C to + 65'C
TDA4505N
28-Pin Plastic DIP (SOT-117)
-25'C to + 65'C
TDA4505AN
28-Pin Plastic DIP (SOT-117)
-25'C to +65'C
TDA4505BN
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
Vce
Supply voltage (Pin 7)
13.2
V
2.3
W
PTOT
Total power dissipation
TA
Operating ambient temperature range
-25 to +65
'C
TSTG
Storage temperature range
-65 to +150
°C
February 1987
6-24
N Package
AGe
TAKEOVER
VERT
RAMPGEN
VERT DRIVE
3
VERTFB
4
TUNERAOC
5
VISION IF IN
gg~~g
IFD~~~
25 SYNC SEPARATOR
22
g~~'t~ET
2
SYNCDEMOD
9
1
AGCDET
1
AFCOUT
1
VIDEO OUT
13
14
~--..lOPYlEW
Signetics Linear Products
Preliminary Specification
TDA4505
Small-Signal Subsystem IC for Color TV
BLOCK DIAGRAM
+v
28
23
24
25
•
20
February 1987
17
21
6-25
15
l'
13
Signetics linear Products
Preliminary Specification
TDA4505
Small-Signal Subsystem IC for Color TV
DC AND AC ELECTRICAL CHARACTERISTICS vee = V7-6 = 12V; TA = 25°C, unless otherwise specified.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
12
13.2
Supplies
V7_6
Supply voltage (Pin 7)
17
Supply current (Pin 7)
9.5
135
V11-6
Supply voltage (Pin 11)1
8.6
111
Supply current (Pin 11) for horizontal oscillator start
V
mA
V
6
8
mA
100
140
/lV
Vision IF amplifier (Pins 8 and 9)
60
VS-9
Input sensitivity 38.9MHz on set AGC
VS-9
45.75MHz on set AGC
RS-9
Differential input resistance (Pin 8 to 9)
CS- 9
Differential input capacitance (Pin 8 to 9)
GS- 9
Gain control range
56
60
dB
VS_9
Maximum input signal
50
100
mV
i!N 17 -6
Expansion of output signal for 50dB variation of input signal
with VS-9 at 150/lV (OdB)
1
dB
5.8
V
120
800
1300
/lV
1800
5
.\1
pF
Video amplifier measured at top sync input signal voltage (RMS value) of 10mV
V17 - 6
Output level for zero signal input
(zero pOint of switched demodulator)
V17 -6
Output signal top sync level 2
V17 -6(P.P)
Amplitude of video output signal (peak-to-peak value)
117(IND
Internal bias current of output transistor (NPN emitter-follower)
2.7
1.4
2.9
3.1
V
2.6
V
2.0
mA
BW
Bandwidth of demodulated output signal
G17
Differential gain (Figure 3)3
4
10
MHz
%
5V
V25-6 = OV
±af
Holding range PLL
±af
Catching range PLL
1100
600
Control sensitivityB
video to oscillator; at weak signal
at strong signal during scan
during vertical retrace and catching
1500
Hz
1000
Hz
2.5
3.75
7.5
kHz/I-'s
kHz/j.tS
kHz/I-'s
Second control loop (positive edge)
ato/ato
Contro' sensitivity R28 _ 6 = see Figure 1
50
to
Control range
25
j.tS
Control sensitivity
25
p.A/j.tS
Maximum allowed phase shift
±2
I-'S
Phase adjustment (via second control loop)
a
Horizontal oscillator (Pin 23)
fFR
Free-running frequency R = 34kn; C = 2.7nF
af
Spread with fixed external components
15,625
afFR
Frequency variation due to change of supply voltage
from 9.5 to 13.2V
TC
Frequency variation with temperature
afFR
Maximum frequency shift
afFR
Maximum frequency deviation at start H-out
Hz
0.4
4
%
0
0.5
%
1 X 10-4
0C- 1
10
%
10
%
8
Horizontal output (Pin 26)
V26-6
Output voltage high level
13.2
V
V26-6
Output voltage at which protection commences
15.8
V
0.5
V
0.15
V26-6
Output voltage low at 126 = 10mA
d
Duty cycle of horizontal output signal at tp
tR
Rise time of output pulse
260
ns
tF
Fall time of output pulse
100
ns
February 1987
z
10l-'s
6-28
0.45
Signetics Linear Products
Preliminary Specification
Small-Signal Subsystem IC for Color TV
TDA4505
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) vee = V7 -6 = 12V; TA = 25°C, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
Flyback input and sandcastle output 9
127
Input current required during flyback pulse
V27-6
Output voltage during burst key pulse
0.1
8
9.0
V27-6
Output voltage during horizontal blanking
4
4.35
5
V
V27-6
Output voltage during vertical blanking
2.1
2.5
2.9
V
tw
Width of burst key pulse (60Hz)
3.1
3.5
3.9
f.lS
tw
Width of burst key pulse (50Hz)
3.6
4.0
4.4
f.lS
Width of horizontal blanking pulse
2
rnA
V
flyback pulse width
Width of vertical blanking pulse
50Hz divider in search window
60Hz divider in search window
50Hz divider in narrow window
60Hz divider in narrow window
21
25
21
lines
lines
lines
lines
5.2
f.ls
17
Delay between start of sync pulse at video output and rising
edge of burst key pulse
Coincidence detector mute output 10
V22-6
Voltage for in-sync condition
10.3
V
V22-6
Voltage for no-sync condition no signal
1.5
V
V22-6
Switching level to switch off the AFC
6.4
V
V22-6
Hysteresis AFC switch
0.4
V
V22-6
Switching level to activate mute function
(transmitter identification)
2.4
V
V22-6
Hysteresis Mute function
122(P_P)
Charge current in sync condition 4.7f.ls
122(P_P)
Discharge current in sync condition 1.3f.ls
0.7
0.5
V
1.0
rnA
0.5
rnA
Vertical ramp generator 11
12
Input current during scan
0.5
12
Discharge current during retrace
0.4
V2 _ 6{P_P)
Sawtooth amplitude
0.8
2
f.lA
rnA
1.1
V
7
rnA
Vertical output (Pin 3)
Is
Output current
VS-6
Maximum output voltage
5.7
V
3.3
1.2
V
V
Feedback Input (Pin 4)
V4-6
V4_6{P_P)
Input voltage
DC component
AC component (peak-to-peak value)
14
Input current
/ltp
Internal precorrection to sawtooth
5
Deviation amplitude SO/60Hz
a
12
f.lA
%
2
%
Vertical guard 12
/lV 4 _ 6
/lV 4 _6
February 1987
Active at a deviation with respect to the DC feedback level;
V27 -6 = 2.5V;
at switching level low
at switching level high
6-29
1.3
1.9
V
V
I
Signetics Linear Products
Preliminary Specification
Small-Signal Subsystem IC for Color TV
TDA4505
NOTES:
1. Pin 11 has a double function. When during switch-on a current of 6mA is supplied to this pin, this current is used to start the horizontal oscillator.
The main supply can then be obtained from the horizontal deflection stage. When no current is supplied to this pin it can be used as volume
control. The indicated maximum value is the current at which all IGs will start. Higher currents are allowed: the excess current is bypassed to
ground.
2. Signal with negative-going sync top white 10% of the top sync amplitude (Figure 2).
3. Measured according to the test line given in Figure 3.
- The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and smallest value relative to the
subcarrier amplitude at blanking level.
- The differential phase is defined as the difference in degrees between the largest and smallest phase angle.
4. This figure is valid for the complete video signal amplitude (peak white to black).
5. The SIN = 20 log VOUT BLACK-TO-WHITE
VN(AMSI at B = 5MHz
6. The AFC control voltage IS obtained by multiplying the IF-output signal (which is also used to drive the synchronous demodulator) with a reference
carrier. This reference carrier is obtained from the demodulator tuned circuit via a 90° phase shift network. The IF-output signal has an asymmetrical
frequency spectrum with respect to the carrier frequency. To avoid problems due to this asymmetrical signal, the AFC circuit is gated by means of
an internally generated gating pulse. As a result the detector is operative only during black level at a constant carrier amplitude which contains no
additional side bands. As a result the AFC output voltage contains no video infonnalion.
At very weak input signals, the driver signal for the AFC circuit will contain a lot of noise. This noise signal has again an asymmetrical frequency
spectrum and this will cause an offset of the AFC output voltage. To avoid problems due to this effect, the AFC is switched off when the AGC is
controlled to maximum gain.
The measured figures are obtained at an input sign RMS voltage of 10mV and the AFC output loaded with 2 times 220kU between +Vs and
ground. The unloaded a-factor of the reference tuned circuit is 70. The AFC is switched off when no signal is detected by the coincidence detector
or when the voltage at Pin 22 is between 1.2V and 6AV. This can be realized by a resistor of 68kU connected between Pin 22 and ground.
7. The slicing level can be varied by changing the value of R17 -25. A higher resistor value results in a larger value of the minimum sync pulse
amplitude. The slicing level is independent of the video information.
8. Frequency control is obtained by supplying a correction current to the oscillator RC-network via a resistor, connected between the phase 1 detector
output and the oscillator network. The oscillator can be adjusted to the right frequency in one of the two following ways:
a) Interrupt R23 - 24.
b) Short circuit the sync separator bias network (Pin 25) to + Vcc.
To avoid the need of a VCR switch, the time constant of phase detector at strong input signal is sufficient short to get a stable picture during VCR
playback. During the vertical retrace period, the time constant is even shorter so that the head errors of the VCR are compensated at the beginning
of the scan. Only at weak signal conditions (information derived from the AGe circuit) is the time constant increased to obtain a good noise
immunity.
9. The flyback input and sandcastle output have been combined on one pin.
The flyback pulse is clamped to a level of 4.5V. The minimum current to drive the second control loop is 0.1 rnA.
10. The functions in-sync/out-of-sync and transmitter identification have been combined on this pin. The capaCitor is charged during the sync pulse and
discharged during the time difference between gating and sync pulse.
11. The vertical scan is synchronized by means of a divider system. Therefore no adjustment is required for the ramp generator. The divider detects
whether the incoming signal has a vertical frequency of 50 or 60Hz and corrects the vertical amplitude.
1.2. To avoid screenburn due to a collapse of the vertical deflection, a continuous blanking level is inserted into the sandcastle pulse when the feedback
voltage of the vertical deflection is not within the specified limits.
13. Starting point tuner takeover at 1 = 0.2mA. Takeover to be adjusted with a potentiometer of 47kU.
February 1967
6-30
Preliminary Specification
Signetics Linear Products
Small-Signal Subsystem IC for Color TV
FUNCTIONAL DESCRIPTION
IF Amplifier, Demodulator, and
AFC
The IF amplifier has a symmetrical input (Pins
8 and 9). The synchronous demodulator and
the AFC circuit share an external reference
tuned circuit (Pins 20 and 21). An internal RCnetwork provides the necessary phase-shifting for AFC operation. The AFC circuit is
gated by means of an internally generated
gating pulse. As a result, the AFC output
voltage contains no video information. The
AFC circuit provides a control voltage output
with a swing greater than 10V from Pin 18.
respect to the sync pulse. That can only be
realized when a second loop is used.
The windows are activated via an up/down
counter.
Horizontal Phase Detector
The counter increases its counter value with
1 for each time the separated vertical sync.
pulse is within the search window. When it is
not, the counter value is lowered with 1.
The circuit has the following operating conditions:
a.
AGC Circuit
Gating of the AGC detector is performed to
reduce sensitivity of the IF amplifier to external electrical noise. The AGC time constant is
provided by an RC circuit connected to Pin
19. The point of tuner take-over is preset by
the voltage level at Pin 1.
DC Volume Control/Horizontal
Oscillator Start
The circuit can be used with a DC volume
control or with a starting possibility of the
horizontal oscillator. The operation depends
on the application. When during switch-on no
current is supplied to Pin 11, this pin will act
as volume control. When a current of SmA is
supplied to Pin 11, the volume control is set
to a fixed output signal and the IC will
generate drive pulses for the horizontal deflection. The main supply of the IC can then
be derived from the horizontal deflection.
Horizontal Synchronization
The video input signal (positive video) is
connected to Pin 25.
The horizontal synchronization has two controlloops. This has been introduced because
a sandcastle pulse had to be generated. An
accurate timing of the burstkey pulse can be
made in an easy way when the oscillator
sawtooth is used. Therefore, the phase of this
sawtooth must have a fixed relation with
February 1987
The different working modes of the divider
system are specified below.
a. Large (search) window: divider ratio between 488 and 722.
This mode is valid for the following conditions:
1. Divider is locking for a new transmitter.
2. Divider ratio found, not within the narrow
window limits.
Weak signal. In this condition the time
constant is doubled compared with the
previous condition. Furthermore, the
phase detector is gated when the oscillator is synchronized. This ensures a stable
display which is not disturbed by the
noise in the video signal.
3. Non-standard TV signal condition detected
while a double or enlarged vertical sync
pulse is still found after the internallygenerated anti-topflutter pulse has ended.
This means a vertical sync pulse width
larger than 10 clock pulses (50Hz) viz. 12
clock pulses (60Hz).
c.
Not synchronized (weak signal). In this
condition the time constant during scan
and vertical retrace are the same as
during scan in condition a.
In general this mode is activated for video
tape recorders operating in the feature trick
mode. When the wide vertical sync. pulses
are detected, the vertical ramp generator is
decoupled from the horizontal oscillator. As
a consequence, the retrace time of this
ramp generator is now determined by the
external capacitor and the discharge current. This decoupling prevents instability of
the picture due to irregular incoming signals (variable number of lines per field).
Video Amplifier
The input to the sound IF amplifier is obtained
by a band-pass filter coupling from the video
output (Pin 17). The sound is demodulated
and passed via a dual-function volume control stage to the audio output amplifier. The
volume control function is obtained by connecting a variable resistor (5kfl) between Pin
11 and ground, or by supplying Pin 11 with a
variable voltage. Sound output is suppressed
by an internal mute signal when no TV signal
is identified.
Strong input signal, synchronized or not
synchronized. (The input signal condition
is obtained from the AGC-circuit, the insync/out-of-sync from the coincidence
detector). In this condition the time constant is optimal for VCR playback; i.e.,
fast time constant during the vertical
retrace (to be able to correct head-errors
of the VCR) and such a time constant
during scan that fluctuations of the sync
are corrected. In this condition the phase
detector is not gated.
b.
The signal through the video amplifier comprises video and sound information.
Sound Circuit and Horizontal
Oscillator Starting Function
TDA4505
Vertical Sync Pulse
The vertical sync pulse integrator will not be
disturbed when the vertical sync pulses have
a width of only 10,"s with a separation of
22,"s. This type of vertical sync pulses are
generated by certain video tapes with anticopy guard.
Vertical Ramp Generator
To avoid problems during VCR-playback in
the so-called feature modes (fast or slow),
the vertical ramp generator is not coupled to
the horizontal oscillator when such signals
are received. For normal signals the coupling
between vertical ramp generator and horizontal oscillator is maintained. This ensures a
reliable interface.
Vertical Divider System
The IC embodies a synchronized divider system for generating the vertical sawtooth at
Pin 2. The divider system has an internal
frequency doubling circuit, so the horizontal
oscillator is working at its normal line frequency; one line period equals 2 clock pulses.
Due to the divider system no vertical frequency adjustment is needed. The divider has a
discriminator window for automatically switching over from the 60Hz to 50Hz system.
When the trigger pulse comes before line 576
the system works in the 60Hz mode, otherwise 50Hz mode is chosen. The divider system operates with 2 different divider reset
windows for maximum interference/disturbance protection.
6-31
4. Up/down counter value of the divider system operating in the narrow window mode
drops below count S.
b. Narrow window: divider ratio between
522 - 528 (60Hz) or 622 - 628 (50Hz).
The divider system switches over to this
mode when the up/ down counter has
reached its maximum value of 15 approved
vertical sync pulses. When the divider operates in this mode and a vertical sync
pulse is missing within the window, the
divider is reset at the end of the window
and the counter value is lowered with 1. At
a counter value below 6, the divider system
switches over the large window mode. The
divider system also generates the so-called
anti-topflutter pulse which inhibits the
phase 1 detector during the vertical sync
pulse. The width of this pulse depends on
the divider mode. For the divider mode a
the start is generated at the reset of the
divider. In mode b the anti-topflutter pulse
starts at the beginning of the first equalizing pulse.
The anti-topflutter pulse ends at count 10 for
50Hz and count 12 for 60Hz. The vertical
II
Signetics Linear Products
Preliminary Specification
TDA4505
Small-Signal Subsystem IC for Color TV
blanking pulse is also generated via the
divider system. The start is at the reset of the
divider while the blanking pulse width is 34
(17 lines) for 60Hz and at count 42 (21 lines)
for 50Hz systems.
The vertical blanking pulse generated at the
sandcastle output Pin 27 is made by adding
the anti-topflutter pulse and the blanking
pulse. In this way the vertical blanking pulse
starts at the beginning of the first equalizing
pulse when the divider operates in the b
mode. The total length of the vertical blanking
in this condition is 21 lines in the 60Hz mode
and 25 lines in the 50Hz mode.
parts (like AGe gating) can remain active.
When external signals are applied to the sync
separator, the connections between the two
parts must be interrupted. This can be. obtained by connecting Pin 22 to ground.
Application When External
Video Signals Have to Be
Synchronized
The input of the sync separator is externally
available. For the normal application, the
video output signal (Pin 17) is AC-coupled to
this input (see Figure 2). It is possible to
interrupt this connection and to drive the sync
separator from another source; e.g., a teletext
decoder in serial mode or a signal coming
from the PT-plug. When a teletext decoder is
applied, the IF-amplifier and synchronization
circuit are running in the same phase so that
the various connections between the two
This results in the following condition:
- AGC detector is not gated.
- AFC circuit is active.
- Mute circuit not active so that the
sound channel remains switched-on.
- The first phase detector has an
optimal time constant for external
video sources.
47k
+
82k
22nF
~820k
~w
~7k
"
Uk
1
27
+o-------~~----.---~
/
~~F
28
HORIZONTAL FLYBACK
SANDCASrLE
2.7k
+
2S
HORIZONTAL DRIVE
VER~R~~~___________________3~
F~~~~
2k
2S
____________________~4
lSOpF
B8nF
24
TUNERAGC
Vee
+
5
---------------------1
r
IFINPUT~
~I li~
"':'"
22nF
I.
10""
27k
10'!.,.
22nF
1.~~_!
.,£:0
2.7nF
23
7
22
B8k
201r
C
......
........
0--
21
TDA4S0S
..
+_Il
82k
Clr--
0.47""
l.8k
0----------------------1
+
AFCSWlTCH
f100PF
~3.3k
I"F
10
+11-330k
19
220k
11
+
.
220k
O~~ _------------------1~2i
2.7k
w~
1
"::'"
22nF
14
-
17~
18
~
AFC
2.2k
~
~
1
: :B8pF "
~~F
I~I--_---'
-;;1
-
J5.SMB I
680
Figure 1. Application Diagram
February 1987
+
18
6-32
VIDEO
OUT
Signetics linear Products
PreliminalY Specification
Small-Signal Subsystem IC for Color TV
TDA4505
100%
100%
95%
86%
72%
58%
44%
30%
30%
""
Figure 3. E.B.U. Test Signal Waveform (Line 330)
Figure 2. Video Output Signal
PC
GENERAlOR
38.9 MHz
ATIENUAlOR
TEST
CIRCUIT
SPECTRUM
ANALYZER
.-------~~~.--------o+
GAIN SETIING ADJUSTED
1_
FOR BLUE
NOTES:
Vo at 4.4MHz
Value at 1.1 MHz; 20109
+ 3.6dB.
Vo at 1.1MHz
Vo at 44 MHz
Value at 3 3MHz, 20Iog~---
Vo at 3.3MHz
Figure 4. Test Setup Intermodulation
GO
.......
20
o
-GO
-20
-4a
V,(dB)
Figure 5. SIN Ratio as a Function of
the Input Voltage
February 19B7
Figure 6. Test Setup AM Suppression
6·33
•
Preliminary Specification
Signetics Linear Products
TDA4505
Small-Signal Subsystem IC for Color TV
50
45
V
./
iD
:s
~
40
30
-100
20
40
60
V15 (mV)
80
100
,/
o
J
0.4
J
0.8
1.2
1.6
2.0
2.4
VI (V)
Figure 7. AM Rejection
February 1987
-60
-60
V
o
V
:s
~
V
35
V
iii -40
1/
iii
0:
v
-20
,/
z
0
...-
Figure 8. Volume Control Characteristics
6·34
Signetics
Section 7
Video/IF
Linear Products
INDEX
TDA2540
TDA2541
TDA2549
Video IF Amplifier and Demodulator, AFT, NPN Tuners •.•.••.•.•.•..
Video IF Amplifier and Demodulator, AFT, PNP Tuners ......•.......
Multistandard Video IF Amplifier and Demodulator •..•.•.•....•........
7-3
7-8
7-14
•
TDA2540
Signetics
Video IF/ AFT
Product Specification
Linear Products
PIN CONFIGURATION
DESCRIPTION
FEATURES
The TDA2540 is an IF amplifier and
demodulator circuit for color and blackand-white television receivers using
NPN tuners.
• Gain-controlled, wide-band
amplifier, providing complete IF
gain
• Synchronous demodulator
• White spot inverter
• Video preamplifier with noise
protection
• AFC circuit which can be
switched onloff by a DC level,
e.g., during tuning
• AGC circuit with noise gating
• Tuner AGC output (NPN tuners)
• VCR switch, which switches off
the video output; e.g., for
insertion of a VCR playback
signal
N Package
DECOUP
2
AGCADJ
3
TUNERAGC
4
AFCSWIN
6
11 Vee
t61~
~~~OD
DEMOD
10
COIL
REF AMP
REF AMP
TUNEDCIR --._ _ _......-- TUNEDCIR
TOP VIEW
APPLICATIONS
• Blacklwhite and color TV
recelverslmonitors
• Video cassette recorders (VCRs)
• CATV converters
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
16·Pin Plastic DIP (SOT·38)
-25·e to + 60·e
TDA2540N
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
Vl1 V4 -
13
13
PTOT
Supply voltage
Tuner AGe voltage
Total power dissipation
RATING
UNIT
13.2
V
12
V
900
mW
TSTG
Storage temperature range
-65 to + 125
·e
TA
Operating ambient temperature range
-25 to +60
·e
January 14, 1987
7-3
853·114087201
•
Product Specification
Signetics Linear Products
TDA2540
Video IF/AFT
BLOCK DIAGRAM
~J,~ r-
f
~I- 9
15
r-
r-
~
~
REFERENCE
AMPUFIER
f;-il-..
?- -..
>
10
lK
AFC
SYNCHRONOUS
DEMODULATOR
r-
t
I
...
......
SYNCHRONOUS
DEMODULATOR
t~
IF INPUT
18
~
GAIN
CONTROLLED
IFAMPUFIER
-
VIDEO
PREAMPLIFIER
3mAl
......
t--
TUNER
AGC
OUTPUT
r-
AGC DETECTORI
NOISE INVERTER
4
3
14
,.---
+ TUNERAGC
TAKE-OVER
1
"--
1
January 14, 1987
WHITE SPOT
INVERTER
1I
7-4
tIVCR
~
I-
AFC
OUTPUT
5
AFC
OUTPUT
6
AFC
SWncH
12
VIDEO
OUTPUT
-~
Signetics Linear Products
Product Specification
TDA2540
Video IF/AFT
ELECTRICAL CHARACTERISTICS (Measured in Figure 4) The following characteristics are measured at TA = 25°C;
V ll -13 = 12V; f = 38.9MHz, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
V11 - 13
Supply voltage range
Vl - 16(RMS)
IF input voltage for onset of AGC (RMS value)
Iz l - 16 1
Differential input impedance CL = 2pF
V12 - 13
Zero-signal output level
V12 - 13
Top sync output level
Gv
IF voltage gain control range
10.2
2.9
Typ
Max
12
13.2
V
100
150
p.V
2
kn
6±0.3
Vl
3.07
3.2
V
64
dB
6
MHz
58
dB 2
BW
Bandwidth of video amplifier (3dB)
SIN
Signal-to-noise ratio at VI
dG
Differential gain
4
10
%
d'l'
Differential phase 1
2
10
degrees
= 10mV
Intermodulation at 1.1 MHz: blue 3
yellow3
at 3.3MHz4
46
46
46
Carrier Signal at video output
60
50
54
4
30
mV
2nd harmonic of carrier at video output
20
30
mV
White spot inverter threshold level (Figure 3)
6.6
V
White spot insertion level (Figure 3)
4.7
V
Noise inverter threshold level (Figure 3)
1.8
V
Noise insertion level (Figure 3)
3.8
V
V14 - 13
External video switch (VCR) switches off the output
14
Tuner AGC output current range
10
V4- 13
Tuner AGC output voltage at 14 = 10mA
14
Tuner AGC output leakage current V14-13
.:l.VS_ 13
Maximum AFC output voltage swing
.:l.f
Detuning for AFC output voltage swing of 10V
VS-13
AFC zero-signal output voltage (minimum gain)
V6- 13
AFC switches on at:
V6- 13
AFC switches off at:
= 5V;
V4 - 13 = 12V
10
4
3.2
NOTES:
1. So-called 'projected zero point', e.g., with switched demodulator.
3. 20109
Vo black-to-white
VN(RMS)at B ~ 5MHz
Vo at 4.4MHz
Vo at 1.1MHz
+ 3.6dB.
Vo at 4.4MHz
4. 20109 Vo at 3.3MHi
January 14, 1987
7-5
1.1
V
0
mA
0.3
V
15
p.A
100
200
kHz
kHz
11
100
2. SIN
dB
dB
dB
6
V
8
V
3
V
1.5
V
•
Signetics Linear Products
Product
TDA2540
Video IF/AFT
-3.2dB
-1OdB
-13.2dB
-13.2dB
SPECTRUM FOR
YELlOW
T
sc
co
SPECTRUM FOR
BWE
-30dB
I
sc
PC
co
PC
QP,.,.,.
NOTES:
SC: Sound carrier level
CO: Chrominance carr"aer
PC: Picture carrier level
J
With respect to top sync level
FIgure 1. Input Conditions for Intermodulatlon Measurements;
Standard Color Bar With 75% Contrast
PC
GENERATOR
38J1MHz
sc
TES1"
CIRCUIT
ATTENUATOR
GENERATOR
33.4MHz
co
GENERATOR
34.5MHz
1
":"
SPECTRUM
ANALYlER
'IM...- - - - O +12V
MANUAL GAIN CONTROL:
ADJUSTED FOR BWE:V12-13=4V
Figure 2. Test Setup for Intermodulatlon
WH~R~J~~= - 8 . 8 - 1 - - - - - - - - - - - - i
ZERO-SIGNAL LEVEL,
WHITE LEVEL (COlA) -
5.7
8
WHITESPCJrINS~~ - 4 . 7 - + - - + - - - - - - - = _ " ..
NOISE INSERTION LEVEL -
3.11
TOP SYNC LEVEL - 3.G7· 3
TH~~~= -1.8~I-------!
nME
Figure 3. Video Output Waveform Showing White Spot and Noise Inverter Threshold Levels
January 14, 1987
Spec~lcatlon
7-6
Signetics Linear Products
Product Specification
Video IF/AFT
TDA2540
+28V
+12V
~
i1=-R
~: 47k
3.3k
39k
270k
1k
..
i1=-
lOOk ;
QFI:.FeF
+
47k
68k
2.2M
TUNING VOLTAGE
TUNERAGC
AFCSWITCH
330
f1"F
-= 10nF
~1PF
o-J'
1
2
3
4
6
5
7
8
L1
L2
I" 1-1
IF INPUT
TDA2540
1.5nF
56pF
I
I
I
I
I
I
16
15
14
o-J
4:
3
12
11
10
lOOpF
r-i
L
10nF
I" "I
9
I
I
I
L
i
I
I
I
T 1PF
+12V
[>"J
J.2.7nF
~ 10nF
330nF
+
J. 68"F
VIDEO
OUTPUT
NOTES:
a of L1 and L2;::;: eo; f "" 38.9MHz
Figure 4. Typical Application Circuit Diagram
Ir,
12
12
70
~
\
\
j
/
50
/
/
V
\
II
!(MHz)
/
\
(OdB=100"V)
-100
38.9
+100
kHz
MHz
kHz
Figure 5. AFC Output Voltage (VS-13) as a Function of the Frequency
January 14. 19B7
/
30
\
o
-4 -3 -2 -1 38.9 +1 +2 +3 +4
i.--
7-7
10
o
20
40
so
V1-•• (dB)
Figure 6. Signal-to-Noise Ratio as a
Function of the Input Voltage (V 1-16)
•
TDA2541
Signetics
Video IF/AFT
Product Specification
Linear Products
DESCRIPTION
The TDA2541 is an IF amplifier and
demodulator circuit for color and blackand-white television receivers using PNP
tuners.
FEATURES
• Galn·controlled wlde·band
amplifier, providing complete IF
gain
• Synchronous demodulator
• White spot Inverter
• Video preamplifier with noise
protection
• AFC circuit which can be
switched on/off by a DC level,
e.g., during tuning
• AGC circuit with noise gating
• Tuner AGC output (PNP tuners)
• VCR switch, which switches off
the video output; e.g., for
Insertion of a VCR playback
signal
PIN CONFIGURATION
N Package
TUNERAGC
4
AFCSWIN
8
1
AFC
DEMOD COIL
REF AMP
TUNEDCIR ........_ _ _
..r-
Vee
AFC
DEMOD COIL
REF AMP
TUNEDClR
10PVlEW
C012100s
APPLICATIONS
• Black/white and color TV
receivers
• Video cassette recorders (VCRs)
• CATV converters
ORDERING INFORMATION
DESCRIPTION
16·Pin Plastic DIP (SOT·38)
TEMPERATURE RANGE
ORDER CODE
-25·C to +60·C
TDA2541N
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
Vcc
Supply voltage
V4 -13
Tuner AGC voltage
PTOT
Total power dissipation
RATING
UNIT
13.2
V
12
V
900
mW
TSTG
Storage temperature range
-65 to +150
·C
TA
Operating ambient temperature range
-25 to +60
·C
December 2. 1986
7·8
853-1059 86703
Signetics Unear Products
Product Specification
TDA2541
Video IF/AFT
BLOCK DIAGRAM
f;-n-
II
2
..
15
~ f013
,f"
~I-- 10
9
r-
r---
,....
~
..~
1
r-
r~
IF INPUT
.......
18
....
~
REFERENCE
AMPUFIER
(l- f-
~
~
1
AFC
-K
SYNCHRONOUS
DEMODULA1OR
!
r-
SYNCHRONOUS
DEMODULAmR
r-
r--
GAIN
CONTROUED
IFAMPUFIER
AGC DETECtORI
NOISE INVERTER
3
VIDEO
PREAMPUFIER
~
3mAi
AFC
OUTPUT
8
AFC
SWRCH
12
VIDEO
OUTPUT
-
WHITESPOI'
INVERTER
14
+ lVNERAIIC
TAK&OVEII
1
'-"
I
-t
6
TIIA3540
TDA3S41
4
-
r-
AFC
OUl1'UT
t
+~
lVNER
AIIC
0UI1'UT
f-
rr
i
8008171S
December 2, 1986
7-9
Signetlcs Linear Products
Product Specification
TDA2541
Video IF/AFT
DC ELECTRICAL CHARACTERISTICS (Measured in Figure 4) TA = 2SoC; VII - 13 = 12V; f = 38.9MHz, unless otherwise
specified.
LIMITS
SYMBOL
UNIT
PARAMETER
Vec
Supply voltage range
VI-16(RMS)
IF input voltage for onset of AGC (RMS value)
IZI-161
Differential input impedance CL 2PF
V12-13
Zero-signal output level
V12-13
Top sync output level
Av
IF voltage gain control range
Max
10.2
12.0
13.2
V
100
ISO
IJV
kn
2
2.9
3.07
VI
3.2
V
64
dB
6
MHz
58
dB2
Differential gain
4
10
%
%
Differential phase
2
10
BW
Bandwidth of video amplifier (3dB)
Signal-to-noise ratio at VI
dG
dip
= 10mV
Intermodulation at 1.1 MHz: blue 1
yellow1
at 3.3MHz2
46
46
46
dB
dB
dB
60
SO
54
Carrier signal at video output
4
30
mV
2nd harmonic of carrier at video output
20
30
mV
WhHe spot inverter threshold level (Figure 3)
6.6
V
White spot insertion level (Figure 3)
4.7
V
Noise inverter threshold level (Figure 3)
1.8
V
Noise insertion level (Figure 3)
3.8
V14-13
External video switch (VCR) switches off the output at:
14
Tuner AGC output current range
V4- 13
Tuner AGC output voltage at 14 = 10mA
14
Tuner AGC output leakage current V14 -13
.IlVs_13
Maximum AFC output voltage swing
.Ilf
Detuning for AFC output voltage swing of 10V
VS-13
AFC zero-signal output voltage (minimum gain)
V6-13
AFC switches on at:
V6-13
AFC switches off at:
0
= ltV;
V4 -13
4
V
10
mA
V
15
IJA
100
200
kHz
6
8
V
1.5
V
11
V
3.2
1. So-called 'projected zero point', e.g., with switched demodulator.
Vo black-te-white
VN(RMS) at 8 = 5MHz
December 2, 1986
V
1.1
0.3
= 12V
10
NOTES:
a
Typ
6±0.3
SIN
2. SIN
Min
7·10
Signetics Unear Products
Product Specification
TDA2541
Video IF/AFT
-3.2dB
-10dB
-13.2dB
-13.2dB
SPECTRUM FOR
-30dB
I
sc
CC
SPECTRUM FOR
BWE
-30dB
YELLOW
I
sc
PC
CC
PC
OPl6G40S
Figure 1. Input Conditions for Intermodulatlon Measurements; Standard Color Bar With 75% Contrast
PC
GENERATOR
38.9MHz
sc
ATTENUATOR
GENERAlOR
33.4MHz
TEST
CIRCUIT
SPECTRUM
ANALVZER
r---------~~~.--------O+~v
cc
GENERATOR
1
":"
MANUALGAINCONTROL:
ADJUSTED FOR BWE:V12_13 =4V
34.5MHz
BOO","'"
NOTES:
1. 20 log
Vo at 4.4MHz
Vo at 1.1MHz
+ 3.6dS
2. 20 log :,:Vo::..c;:al:..,4::,.4:c'M:c'H:=Z
Vo at 3.3MHz
Figure 2. Test Setup for Intermodulation
December 2, 1986
7·11
Signetics Linear Products
Product Specification
TDA2541
Video IF/AFT
WHf~R~S~J~~~~~~ -
6.6-1f----------57 6
ZERO-SIGNAL LEVEL, _
WHITE LEVEL (CCIR)
.
WHITEsparINSE~~~ -4.7-1f--+------=_.....
NOISE INSERTION LEVEL -
3.8
TOP SYNC LEVEL - 3.07· 3+--· L-..I
2
TH~~~~~~= _ts_"f-_
_ _ _ __
TIME
Figure 3. Video Output Waveform Showing White Spot and Noise Inverter Threshold Levels
+28V
+12V
r:}*
... : 47k
Uk
39k
270k
1k
66k
47k
2.2M
;---1---+--+----'.""'-"'------.... TUNINGVOLJAGE
----+----4----4---+
TUNERAGC ....
;-----------------oAFCSWITCH
330
1pF
IF INPUT
TDA2541
1.snF:;:
10nF
~.I-+-----J
16
15
14
~3
:
12
11
56pF
10
1pF
-
;----1---0 +12V
1.Sk
~2.7nF ~33OnF
VIDEO
OUTPUT
Figure 4. Typical Application Circuit Diagram; Q of L 1 and L2 '" 80; fo
December 2, 1986
7-12
= 38.9MHz
Signetics Linear Products
Product Specification
TDA2541
Video IF/AFT
12
12
I,h
70
\,
/
1/
V
o
r1
1\
,'-
-
-4 -3 -2 -1 38.9 +1 +2 +3 +4
• (MHz)
/"
,
/
(OdB=loo.V)
10
38.9
MHz
/
30
\
-100
kHz
/
50
1\
If
~
+100
kHz
Figure 5. AFC Output Voltage (Vs -13) as a Function of the Frequency
o
eo
Figure 6. Signal-to-Noise Ratio as a
Function of the Input Voltage (VI -16)
I
December 2, 1986
7-13
TDA2549
Signetics
Multistandard Video
IFjDemodulator
Product Specification
Linear Products
DESCRIPTION
• Auxiliary video input and output
(7Sll)
• Video switch to select between
auxiliary video input signal and
demodulated video signal
• AFC circuit with onloff switch
and Inverter switch
• AGC circuit for positive
modulation (mean level) and
negative modulation (noise gate)
• AGC output for controlling
MOSFET tuners
The TDA2549 is a complete IF circuit
with AFC, AGC, demodulation, and video preamplification facilities for multistandard television receivers. It is capable
of handling positively and negatively
modulated video signals in both color
and black/white receivers.
FEATURES
• Gain-controlled wide-band
amplifier providing complete IF
gain
• Synchronous demodulator for
positive and negative modulation
• Video preamplifier with noise
protection for negative
modulation
APPLICATIONS
PIN CONFIGURATION
N Package
24
23 VlDEOSW
ENABLE
POLARITYSW
aND
(SUBSTRATE)
TOPSYNDET
4
FBDECOUP
5
21 Vee
AFCDEMOD
COIL
19
18
FBDECOUP
T¥:K~~
~g~m
• NTSC/PAL/SECAM TV receiverl
monitors
• Multistandard VCR
• CATV converters
~f~PIN
VIDEO
PREAMP OUT
MOD
L~~
VlDE~~~
17
l!u~~J>CIR
l!u~~J>CIR
~~ODCOIL
9
10
14 ¢llri-:~~~=~:..rll--':""X-:-oo,.
.
-~>---'l/'''''""k--r::J~
....I-[../
-l::
=,--=
IF,
AF,
o----il-----t----;~~~"----------+i'--_ _ _
QUADRATURE
DEMODULAlOR
S-STAGE
LIMITING AMPLIFIER
TIlA25S5
---::-f----i~'.......,>-:-----...---.r-::x:--;---,r- ~
IF. O - - - -.....
+
+
lk
~~~v~IIII~~~~r-~
:1:T
'8
1~v---+-~-l:1:--+0.
l
90·
L-j 11-+---+
4
14
SUPPLY
J
15
+12V
February 24, 1987
8-15
853-0215 87735
Signetics linear Products
Product Specification
TDA2555
Dual TV Sound Demodulator Circuit
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
Vee
Supply voltage (Pins 13 and 15)
13.2
V
PTOT
Total power dissipation
400
mW
TSTG
Storage temperature range
-65 to + 150
DC
TA
Operating ambient temperature
o to
+70
DC
DC ELECTRICAL CHARACTERISTICS VCC=V13, 15-14= 12V; TA=25 DC; f=5.5MHz; fMl=lkHz; ~f=±30kHz;
VI (RMS) = 5mV, see Test Circuit Figure 1, voltages with respect to ground (Pin 14),
unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Vee
Supply voltage (Pins 13 and 15)
113,15
Supply current
10.8
Typ
Max
12.0
13.2
V
mA
24.5
V12, 17(RMS)
Input voltage (RMS value) for start of limiting
V12,17.14
Maximum input voltage
200
mV
VI
DC voltage at inputs-Pins 10, 11, 12, 16, 17, and 18 to 14
2.0
V
AMS
AM suppression
fM(FM) = 70Hz; ~f = ± 30kHz
fM(AM) = 1kHz; m = 30%
50
dB
V2.B-14
AF output voltage RMS value
350
mV
V2,B-14
DC voltage at outputs Pins 2 and 8
RL
Output lead resistance Pins 2 and 8
THO
Total harmonic distortion
RI
Internal de-emphasis resistance Pins 1 and 9
ex
Channel separation
February 24, 1987
100
3.7
V
10
kn
0.1
1.0
60
8-16
p.V
%
kn
dB
Product Specification
Signetics Linear Products
TDA2555
Dual TV Sound Demodulator Circuit
IF,
f
IF,
+12V
f
O.1• F
O.1• F
50
50
16
TDA2555
r
47nF
1nF
1nF
1k
1k
AF,
22pF
8 E J 2 2 P F 22pF
1nF J
8E
1nF
Uk
Uk
Figure 1. Test Circuit
February 24, 1987
47nF
AF,
22PF
8-17
r
•
Signetics
Section 9
SYNC Processing and
Generation
Linear Products
INDEX
TDA2577A
TDA2578A
AN162
AN1621
TDA2579
TDA2593
TDA2594
TDA2595
AN158
TDA8432
Sync Circuit With Vertical Oscillator and Driver
(With Negative Horizontal Output) ..........................................
Sync Circuit With Vertical Oscillator and Driver
(Negative Horizontal Output) .................................................
A Versatile High·Resolution Monochrome Data and
Graphics Display Unit............................. .............................
TDA2578A and TDA3651 PCB Layout Directives.................... ...
Synchronization Circuit (With Horizontal Output) ........................
Horizontal Combination........................................................
Horizontal Combination........................................................
Horizontal Combination........................................................
Features of the TDA2595 Synchronization Processor.................
Deflection Processor With 12 C Bus........................................
9·3
9·14
9·25
9·30
9·31
9·41
9·46
9·51
9·57
9·62
•
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
i
I
I
I
I
I
I
I
I
I
I
I
I
TDA2577A
Signetics
Sync Circuit With Vertical
Oscillator and Driver
Product Specification
Linear Products
DESCRIPTION
The TDA2577A separates the vertical
and horizontal sync pulses from the
composite TV video signal and uses
them to synchronize horizontal and vertical oscillators.
FEATURES
• Horizontal sync separator and
noise Inverter
• Horizontal oscillator
• Horizontal output stage
• Horizontal phase detector (sync
to oscillator)
• Time constant switch for phase
detector (fast time constant
during catching)
• Slow time constant for noise-only
conditions
• Time constant externally
switchable (e.g., fast for VCR)
• Inhibit of horizontal phase
detector and video transmitter
Identification circuit during
vertical oscillator flyback
• Second phase detector (0,02) for
storage compensation of
horizontal deflection stage
• Sandcastle pulse generator (3
levels)
• Video transmitter identification
circuit
• Stabilizer and supply circuit for
starting the horizontal oscillator
and output stage directly from
the supply voltage
• Duty factor of horizontal output
pulse is 50% when flyback pulse
is absent
• Vertical sync separator
• Bandgap 6.5V reference voltage
for vertical oscillator and
comparator
• Synchronized vertical oscillator/
sawtooth generator (synchronization inhibited when no video
transmitter is detected)
• Internal circuit for 3% parabolic
precorrection of the oscillator/
sawtooth generator. Comparator
supplied with precorrected
sawtooth and external feedback
input
• Vertical comparator with internal
3% precorrection circuit for
vertical oscillator/sawtooth
generator
• Vertical driver stage
• Vertical blanking pulse generator
with external adjustment of pulse
duration (50Hz: 21 linesj 60Hz: 17
lines)
• Vertical guard circuit
PIN CONFIGURATION
N Package
VERTOUT
1
17
VERT
FEEDBACK
VERTFREQ
COINDET
~~cam-E
HORIZOSC
ADJ
START V IN
VERT SYNC
15
SEP
HORIZOSC
PHASE DET
• OUT
HORIZ
13
SYNCSEP
HORIZ
PHASEDru~
~~~T~I~r.:
FLYBK PULSE IN
SYNCSEP
8
TOP VIEW
•
APPLICATIONS
• Video monitors
• TV receivers
• Video processing
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
18-Pin Plastic DIP (SOT-102HE)
-25°C to +65°C
TDA2577AN
January 14, 1987
9-3
853-1151 87202
Signetlcs Linear Products
Product Specification
Sync Circuit With Vertical Oscillator and Driver
TDA2577A
BLOCK DIAGRAM
HORIZONTAL FREQUENCY
1O,F
I,F
-F+
4.7k
82 22,F
150nF
+~.,r
820
...
ADJUSTMENT
+I-:L
~TOPIN16
10k
4.71JF
·,s>4mA
I.
+12V
100~F
UnF
+~
~
1.
10
9
-=-
VIDEO INPUT
1IV
HORIZONTAL
1k
SEPARATOR
SYNC
~"PF
r
100liF
18
NOISE
INVERTER
COINCIDENCE
DETECTOR
13
V1DEO
TRAN~ITTER
IDENnFICATION
VCR
12k
TDA2577A
TO PIN 10
(+12V)
3 100k
I
680nF
220k
+-
VERTICAL FREQUENCY
ADJUSTMENT
January 14, 1987
3.9
....
InF
..r ..
A .....
SANDCASTLE
VERTICAL- VERTICAL OUTPUT PULSE
FEEDBACK
9..4
DRIVE
VERTICAL
BLANKING
/SwrrCH
14
17
I
-=
47
nF
:
::~ : : ffi
SOISOHz
A
'f'
HORIZONTAL FLYBACK-=
PULSE
Product Specification
Signetics Unear Products
TDA2577A
Sync Circuit With Vertical Oscillator and Driver
COINCIDENCE DETECTOR
VERTICAL DRIVE
TDA3651
(PIN 1)
+12V
I
I
+6.7 V
i
67
6.8k 1
~10nF
.I,
8.2k
----~-----=----:::..-------~
.i
VERTICAL COMPARATOR
r--·-·~~~~~~;;~;;~;,::~-;------
4.7 k
!
VERTICAL
FEEDBACK
+12 V
8.
OSCILLATORI
iI
2.7k
F.9nF
17
..r- A
-----------::---~-----------j
VERTICAL OSCILLATORlSAWTOOTH GENERATOR
"
, k
r'WI,...,.""'1r--t--.,...----"'V\,.....--t::
COMPOSITE
VIDEO
220k
-....
SANDCASTLE
OUTPUT PULSE
i
i
i
-=
-= -=
_
I·-·---~~~;.;;;,.-;;~I;;·-·---·--
I
i
-=
----------------------------1
VERTICAL SYNC SEPARATOR
i
+12V
COMPOSlTE
SYNC
•
•
I'
,
1
I
i
+12V
(PIN 10)
r·-·---·--;.~-;~~~~;-~~;-·-·-·--
i
56'
I
i
i
23.
i
i
-=---------------------------------------------------------=
DFOe87OS
Figure 1_ TDA2577A Circuit Diagram
January 14, 1987
9-5
Signetics Linear Products
Product Specification
Sync Circuit With Vertical Oscillator and Driver
TDA2577A
,.,...
.-.-.-----.-.-.-.-.-.---.-.~--.-----.-.-.-.-----.---.-.VIDEO INPUTINOISE INVERTER
.4 Y DURING
.TART-UP
INPUT
COMPOSITE
SYNC
,.
PHASE DETECTOR ""2
I
+1ZY
VIDEO
i
i
i
•
2k
PULSE
!HORIZONTAL
FLYBACK ---
I
'''pF~
iI
r"i
-;;-D~~T~~S;;";';;; ;;-N-T;;-~A~~-;~;,:~ ~~~;
._-_._---_._:_---_._-_._.-1
.1ZV
+12V
I
HORIZONTAL SYNC SEPARATOR
i
+12V
,;f
SLICED
;~NM;OSITE
i
!
I
t-"I---~
i
IDENTIFICATION
!
~.-------------.-.-.-.------
4.7 k
--·-~----;~;;~,;_R--------·--i
O.2T04mA
HORIZONTAL FLYBACK
'2
i
i
+12 V
COMPOSITE
SYNC
HORIZONTAL
i
FLYBACK
I
i
SYNC
.-.-.--::...--....::~~!£.~-------.-i
REFERENCE
i
SLOW PHASE DETECTOR""
i
VOLTAGE OV 2Y
r'-' -._--- -;;~;;~~~~~;~_;_.-.-.---.
OSp~~: __ !_
I
HORIZOSC!
I
,F
I
~NV~~----------+---~~~-=~_=
REF
i
•
VOLTAGE
2.7 V
I
i
i
'5V
_ _
_
--·-------------------------'7'-----------------------.-.GROUND
T0A2577A
SUPPLY SWITCH
Figure 1. TDA2577A Circuit Diagram (Continued)
January 14, 1987
9-6
TO PIN 16
Signetics linear Products
Product Specification
Sync Circuit With Vertical Oscillator and Driver
TDA2577A
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
8
rnA
116
Start current (Pin 16)
Vee = V10-9
Supply voltage (Pin 10)
13.2
V
PTOT
Total power dissipation
1.1
W
TSTG
Storage temperature range
-65 to +150
'C
TA
Operating ambient temperature range
-25 to +65
'C
eJA
Thermal resistance from junction to
ambient in free air
50
'C/W
DC ELECTRICAL CHARACTERISTICS 116=5mA; Vee=12V; TA=25'C, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
8.7
9.5
V
55
70
rnA
12
13.2
V
V
Supply
116
Supply current at Pin 16
V16-9
Stabilized supply voltage (Pin 16)
110
Supply current (Pin 10)
Vcc = V10-9
Supply voltage (Pin 10)
4
8.0
10
8
rnA
Video Input (Pin 5)
VS-9
Top-sync level
VS-9(P.P)
Sync pulse amplitude (peak-to-peak value) 1
Slicing level
t1
1.5
3.1
3.75
0.15
0.6
1
V
35
50
65
%
Delay between video input and detector output
0.35
IlS
Noise gate (Pin 5)
VS-9
Switching level
0.7
1
V
First control loop (sync to oscillator; Pin 8)
Llf
Holding range
Ll!
Catching range
±800
±600
Control sensitivity video with respect to oscillator, burst key,
and flyback pulse
for slow time constant
for fast time constant
800
Hz
1100
1
275
Hz
kHzIllS
kHzl/ls
Second control loop (horizontal output to flyback; Pin 14)
LltD/Llto
Control sensitivity; static2
tD
Control range
400
1
Controlled edge
IlSIIlS
50
IlS
negative
Phase adjustment (via 2nd control loop; Pin 14)
±114
Control sensitivity
25
Maximum permissible control current
0
MAIllS
50
MA
Horizontal oscillator (Pin 15)
fosc
Frequency (no sync)
Llfose
Frequency spread (Cosc = 2.2nF; Rose = 40kn)
Llfose
Frequency deviation between starting point of output signal
and stabilized condition
Te
Temperature coefficient
January 14, 1987
Hz
15625
6
1 X 10- 4
9-7
4
%
8
%
'C
•
Signetics Linear Products
Product SpeclficaHon
TDA2577A
Sync Circuit With Vertical Oscillator and Driver
DC ELECTRICAL CHARACTERISTICS (Continued) 116 = 5mA; Vee = 12V; TA = 25°C, unless olherwise specified.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max,
Horizontal output (Pin 11)
V11-9
Output voltage; high level
V11-9
Voltage at which protection starts
V11-9
Output voltage; low level
start condition at 111 = lOrnA
V11-9
6
Il
13.2
V
15.8
V
0.3
0.5
V
0.3
0.5
V
13
normal condition at 111 = 40mA
Duty factor of output signal during starting (no phase shift;
voltage at Pin 11 Low)
Duty factor of output signal without flyback pulse
%
65
45
50
55
%
negative
Controlled edge
Duration of output pulse (see Figure 2)
ps
to + 10+2.5
Sandcastle output pulse (Pin 17)
V17_9
V17_9
V17-9
tp
Output voltage during:
burst key
horizontal blanking
vertical blanking
10
4.2
2
4.6
2.5
5
3
V
V
V
Pulse duration
burst key
3.6
4
4.4
IlS
flyback pulse3
horizontal blanking
vertical blanking
for 50Hz application (-112 : 0 to 0.1 rnA)
for 60Hz application (-112 : typo 0.2mA)
I:!
Delay between the start of the sync at the video input and
the rising edge of the burst key pulse
4.8
5.2
21
17
lines
lines
5.6
ps
Coincidence detector; video transmitter Identification circuit; time constant switches (Pin 18); see also Figure 1
±118
Detector output current
300
pA
V18-9
Voltage during noise4
0.3
V
V18-9
Voltage level for in-sync condition
7.5
V1B-9
Switching level slow-Io-fast
V1B-9
V18-9
Switching level
mute function active; '1'1 fast,to-slow
vertical period counter
3 periods fast
V18-9
Switching level slow-to-fast (locking)
mute function inactive
V18-9
V18-9
January 14, 1987
V
3.2
3.5
3.8
V
1.0
1.2
1.4
V
0.08
0.12
0.16
V
1.5
1.7
1.9
V
Switching level fast-to-slow (locking)
4.7
5.0
5.3
V
Switching level for VCR (fast time constant)
without mute function
8.2
8.6
9
V
9-8
Product Specification
Signetics Linear Products
TDA2577A
Sync Circuit With Vertical Oscillator and Driver
DC ELECTRICAL CHARACTERISTICS (Continued) 116 = 5mA; Vcc = 12V; TA = 25°C, unless otherwise specified.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
Video transmitter Identification output (Pin 13)
V13-9
Output voltage active (no sync) at 113 = 1rnA
10
11
V13 - 9
Output voltage active (no sync) at 113 = 5mA
7
10
V13-9
Output voltage inactive
V
V
0.1
0.5
V
0.6
0.8
rnA
4
rnA
VCR switching (Pin 13)
113
Input current for fast time constant phase detector <1'1, with
mute function active
0.4
Flyback input pulse (Pin 12)
V12 - 9
Switching level
112
Input current
1
V12-9(P.P)
Input pulse amplitude (peak·to-peak value)
R12 - 9
Input resistance
2.7
kQ
to
Delay time of sync pulse (measured in <1'1) to flyback at
switching level; tFL = 12p.S2 (see also Figure 3)
1.3
p.s
0.2
V
12
V
Duration of vertical blanking pulse (Pin 12)
-112
-112
Required input current (negative)
for 50Hz application; 21 lines blanking
for 60Hz application; 17 lines blanking
-112
Maximum allowed input current
0.15
0.2
0.3
0.1
rnA
rnA
rnA
0.4
rnA
Vertical sawtooth generator (Pin 3)
fs
Vertical frequency (no sync)
Ilfs
Frequency spread (Cose
46
= 680nF;
Rose
= 180kQ;
Hz
4
at +26V)
Synchronization range
22
13
Input current at V3 _ 9 = 6V
Ilfs
Frequency shift for Vee
Te
Temperature coefficient
= 10
%
2
0.2
to 13V
%
p.A
%
°C- 1
1 X 10- 4
Comparator (Pin 2)
V2 _ 9
V2_9(P_P)
12
Input voltage
DC level AC level (peak-to-peak value)
4.0
4.4
1.6
Input current at V2_ 9 = 6V
Saw100th internal precorrection (parabolic convex)
4.8
V
V
2
p.A
3
%
Vertical output stage; emitter-follower (Pin 1)
Vl-9
Output voltage at 11
11
Output current
= 10mA
3.2
3.6
5
V
20
rnA
3.3
6.3
V
V
Vertical guard circuit
V2 _ 9
V2 _ 9
Activating voltage levels (vertical blanking level is 2.5V)
switching level Low
switching level High
2.7
5.4
NOTES:
1. Up to 1Vp_p the slicing level is constant; at amplitudes exceeding 1Vp_p, the slicing level will increase.
2. to = delay between negative transient of horizontal output pulse and the rising edge of the flyback pulse.
to = delay between the rising edge of the flyback pulse and the start of the current in '1'1 (Pin 8).
3. The duration of the flyback pulse is measured at the input switching level, which is about 1V(tFU.
4. Depends on DC level at Pin 5; value given applicable for Vs_. '" 5V.
January 14, 1987
9-9
3
5.8
I
Product Specification
Signetics Linear Products
TDA2577A
Sync Circuit With Vertical Oscillator and Driver
APPLICATION INFORMATION
The TDA2577A generates the signal for driving the horizontal deflection output circuit. It
also contains a synchronized vertical sawtooth generator for direct drive of the vertical
deflection output stage.
The horizontal oscillator and output stage can
start operating on a very low supply current
(1 , 6;;' 4mA), which can be taken directly from
the supply line. Therefore, it is possible to
derive the main supply (Pin 10) from the
horizontal deflection output stage. The duty
factor of the horizontal output signal is about
65% during the starting-up procedure. After
starting up, the second phase detector ('1'2) is
activated to control the timing of the negativegoing edge of the horizontal output signal.
v'~'1
IN-SYNC CONDITION
SLOW
rp,
FAST MODE;
...... WITHOUT MUTE FUNCTION
-
-
loP, FAST - - . .
",SLOW} ""
FAST VCR MODE:
WITH MUTE fUNCTION
NOISE ONLY
Figure 2. Voltage Levels at Pin 18 (V,8-9)
The slicing level of the horizontal sync separator is independent of the amplitude of the
sync pulse at the input. The resistor between
Pins 6 and 7 determines its value. A 4.7kn
resistor gives a slicing level at the middle of
the sync pulse. The nominal top sync level at
the input is 3.1V. The amplitude selective
noise inverter is activated at a level of 0.7V.
waveform with its rising edge refering to the
top of the horizontal oscillator signal. In the
second loop, the phase of the flyback pulse is
compared to another reference waveform,
the timing of which is such that the top of the
flyback pulse is situated symmetrically on the
horizontal blanking interval of the video signal. Therefore, the first loop can be designed
for a good noise immunity, whereas the
second loop can be as fast as desired for
compensation of switch-off delays in the
horizontal output stage.
Good stability is obtained by means of the
two control loops. In the first loop, the phase
of the horizontal sync signal is compared to a
The first phase detector is gated with a pulse
derived from the horizontal oscillator signal.
This gating (slow time constant) is switched
A bandgap reference voltage (6.5V) is provided for supply and reference of the vertical
oscillator and comparator stage.
NORMAL MODE
off during catching. Also, the output current of
the phase detector is increased fivefold during the catching time and VCR conditions
(fast time constant). The first phase detector
is inhibited during the retrace time of the
vertical oscillator.
The in-sync, out-of-sync, or no-video condition is detected by the video transmitter
identification/ coincidence detector circuit
(Pin 1B). The voltage on Pin 1B defines the
time constant and gating of the first phase
detector. The relationship between this voltage and the various switching levels is shown
in Figure 2. The complete survey of the
switching actions is given in Table 1.
Table 1_ Switching Levels at Pin 18
FIRST PHASE DETECTOR '1'1
VOLTAGE AT
PIN 18
Time Constant
MUTE OUTPUT
AT PIN 13
RECEIVING CONDITIONS
Gating
On
Slow
7.5V
7.5 to
3.5 to
1.2 to
0.1 to
1.7 to
3.5V
1.2V
O.lV
1.7V
5.0V
5.0 to 7.5V
B.7V
Fast
X
X
On
Off
X
X
.
X
X
X
X
X
X
X
X
X
X
.
X
X
X
X
X
X
X
X
X
X
Off
Video signal detected
Video signal detected
Video signal detected
Noise only
New video signal detected
Horizontal oscillator locked
VCR playback with mute function
Horizontal oscillator locked
VCR playback without mute function
Where: • = 3 vertical periods.
The stability of displayed video information
(e.g., channel number) during noise-only conditions is improved by the first phase detector
time constant being set to slow.
The average voltage level of the video input
on Pin 5 during noise-only conditions should
not exceed 5.5V. Otherwise, the time constant switch may be set to fast due to the
average voltage level on Pin 1B dropping
below 0.1V. When the voltage on Pin 1B
drops below 100mV, a counter is activated
which sets the time constant switch to fast,
January 14, 19B7
and not gated for 3 vertical periods. This
condition occurs when a new video signal is
present at Pin 5. When the horizontal oscillator is locked, the voltage on Pin 1B increases.
Nominally, a level of 5V is reached within
15ms (1 vertical period). The mute switching
level of 1.2V is reached within 5ms
(C'B = 47nF). If the video transmitter identification circuit is required to operate under
VCR playback conditions, the first phase
detector can be set to fast by connecting a
resistor of 1BOkn between Pin 1Band
9-10
ground. Also, a current of 0.6mA into Pin 13
sets the first phase detector to fast without
affecting the mute output function (active
High with no video signal detected). For VCR
playback without mute function, the first
phase detector can be set to fast by connecting a resistor of 1kn to the supply (Pin 10).
The supply for the horizontal oscillator (Pin
15) and horizontal output stage (Pin 11) is
derived from the voltage at Pin 16 during the
start condition. The horizontal output signal
starts at a nominal supply current into Pin 16
Signetics Linear Products
Product Specification
Sync Circuit With Vertical Oscillator and Driver
of 3.5mA, which will result in a supply voltage
of about 5.5V (for guaranteed operation of all
devices 116 > 4mA). It is possible that the
main supply voltage at Pin lOis OV during
starting, so the main supply of the Ie can be
taken from the horizontal deflection output
stage. The start of the other Ie functions
depends on the value of the main supply
voltage at Pin 10. At 5.5V, all Ie functions
start operating except the second phase
detector (oscillator to flyback pulse). The
output voltage of the second phase detector
at Pin 14 is clamped by means of an internally-loaded NPN emitter-follower. This ensures
that the duty factor of the horizontal output
signal (Pin 11) remains at about 65%. The
second phase detector will close if the supply
voltage at Pin 10 reaches B.BV. At this value,
the supply current for the horizontal oscillator
and output stage is delivered by Pin 10, which
also causes the voltage at Pin 16 to change
to a stabilized B.7V. This change switches off
the NPN emitter-follower at Pin 14 and activates the second phase detector. The supply
voltage for the horizontal oscillator will, however, still be referred to the stabilized voltage
at Pin 16, and the duty factor of the output
signal at Pin 12 is at the value required by the
delay at the horizontal deflection stage. Thus,
switch-off delays in the horizontal output
stage are compensated. When no horizontal
flyback signal is detected, the duty factor of
the horizontal output signal is 50%.
Horizontal picture shift is possible by externally charging or discharging the 47nF capacitor
connected to Pin 14.
The Ie also contains a synchronized vertical
oscillator/sawtooth generator. The oscillator
Signal is connected to the internal comparator
(the other side of which is connected to Pin 2)
via an inverter and amplitude divider stage.
The output of the comparator drives an emitter-follower output stage at Pin 1. For a linear
sawtooth in the oscillator, the load resistor at
Pin 3 should be connected to a voltage
source of 26V or higher. The sawtooth amplitude is not influenced by the main supply at
Pin 10. The feedback signal is applied to Pin 2
and compared to the sawtooth signal at Pin 3.
For an economical feedback circuit with less
picture bounce, the sawtooth signal is internally precorrected by 3% (convex) referred to
Pin 2. The linearity of the vertical deflection
current depends upon the oscillator signal at
Pin 3 and the feedback signal at Pin- 2.
Synchronization of the vertical oscillator is
inhibited when the mute output is present at
Pin 13.
To minimize the influence of the horizontal
part on the vertical part, a 6.5V bandgap
reference source is provided for supply and
reference of the vertical oscillator and comparator.
The sandcastle pulse, generated at Pin 17,
has three different voltage levels. The highest
level (ltV) can be used for burst gating and
black level clamping. The second level (4.6V)
is obtained from the horizontal flyback pulse
at Pin 12 and used for horizontal blanking.
The third level (2.5V) is used for vertical
blanking and is derived by counting the horizontal frequency pulses. For 50Hz, the blanking pulse duration is 21 lines and for 60Hz it is
17 lines. The blanking pulse duration is set by
the negative voltage value of the horizontal
flyback pulse at Pin 12.
The Ie also incorporates a vertical guard
circuit which monitors the vertical feedback
signal at Pin 2. If this level is below 3V or
higher than 5.BV, the guard circuit will insert a
continuous level of 2.5V into the sandcastle
output signal. This will result in complete
blanking of the screen if the sandcastle pulse
is used for blanking in the TV set.
I
VIDEO SIGNAL
(PINS)
'" DETECTOR
OUTPUT CURRENT
(PIN 8)
HORIZONTAL
OSCILLATOR SIGNAL
(PIN IS)
HORIZONTAL
OUTPUT SIGNAL
(PIN 11)
SWITCH-OFF DELAY
HORIZONTAL OUTPUT STAGE
FLVBACK PULSE
(PIN 12)
IP2DETECTOR
OUTPUT CURRENT
(PIN 1.)
SANOCASTLE
PULSE
(PIN 17)
Figure 3. Timing Diagram of the TDA2577 A
January 14, 19B7
TDA2577A
9-11
Signetics Linear Products
Product Specification
Sync Circuit With Vertical Oscillator and Driver
TDA2577A
HORIZONTAL
FLVBACK
+12 V
J\.
HORIZONTAL
DRIVE
>O.2mA
SAND CASTLE PULSE
MUTE
r-_+-----f--~~~<~4~.0~mA~--_+--------------~~~_t----o~
>4mA
1k
6.8
12
k
220
nF
10
12
11
17
16
13
18
TDA2577A
100
k
150 +
10
~PF ~"F
l
'OADJo
":" (HORIZONTAL)
fOADJ.
(VERTICAL)
VIDEO
680
nF*
220
k
VERTICAL
FEEDBACK
VERTICAL
DRIVE
+ FROM PINg
TOA3651
Figure 4. Typical Application Circuit Diagram; lor Combination 01 the TDA2577A with the TDA3651 (see Figure 6)
F
33 k
TO PIN
180k
14~
TDA2577A
+12V
47k
Figure 5. Circuit Configuration at Pin 14 lor Phase Adjustment
January 14, 1987
9-12
Signetics Linear Products
Product Specification
TDA2577A
Sync Circuit With Vertical Oscillator and Driver
TDA3051
~
1
10 nF
-:li
3
1
.11
5
6
1
390 PF L
6.8k
330
VERTICAL DRIVE
(FROM PIN 1 TDA2511A)
VERTICAL
DEFLECTION
COILS
AT1236/20
100 IJF
NC
+11-
G~
8
9
410
BAX12A '::"
47nF
+
Uk
J220.F
41k
~UNEARITY
1k
VERTICAL FEEDBACK
(PIN 2 TDA2571A)
:
±3SnF
+
+28 V
Uk
SHIFT
21
:
6.8.F
1000IJF
(16 V)
21k
1.2
100
AMPLITUDE
-
Figure 6. Typical Application Circuit Diagram of the TDA3651 (Vertical Output) When Used In Combination With the
TDA2577A (90°C Application)
January 14, 1987
9-13
•
TDA2578A
Signetics
Sync Circuit With Vertical
Oscillator and Driver
Product Specification
Linear Products
DESCRIPTION
The TDA2578A separates the vertical
and horizontal sync pulses from the
composite TV video signal and uses
them to synchronize horizontal and vertical oscillators.
FEATURES
• Horizontal sync separator and
noise Inverter
• Horizontal oscillator
• Horizontal output stage
• Horizontal phase detector (syncto-OSCillator)
• Time constant switch for phase
detector (fast time constant
during catching)
• Slow time constant for noise-only
conditions
• Time constant. externally
switchable (e.g., fast for VCR)
• Inhibit of horizontal phase
detector and video transmitter
Identification circuit during
vertical oscillator flyback
• Second phase detector (..,2) for
storage compensation of
horizontal deflection stage
• Sandcastle pulse generator (3
levels)
• Video transmitter identification
circuit
• Stabilizer and supply circuit for
starting the horizontal oscillator
and output stage directly from
the power line rectifier
• Duty factor of horizontal output
pulse is 50% when flyback pulse
is absent
• Vertical sync separator
• Bandgap 6.5V reference voltage
for vertical oscillator and
comparator
• Synchronized vertical oscillatorl
sawtooth generator
(synchronization Inhibited when
no video transmitter Is detected)
• Internal circuit for 6% parabolic
pre-correction of the oscillatorl
sawtooth generator. Comparator
supplied with pre-corrected
sawtooth and external feedback
input
• Vertical driver stage
• Vertical blanking pulse generator
• 50/60Hz detector
• 50/60Hz identification output
• Automatic amplitude adjustment
for 60Hz
• Automatic adjustment of blanking
pulse duration (50Hz: 21 lines;
60Hz: 17 lines)
• Vertical guard circuit
PIN CONFIGURATION
VERTOUT
1
VERT
FEEDBACK
VERTFREQ
SANDCASTLE
PULSE OUT
HORIZOSC
STARTVIN
ADJ
VERT SYNC
SE.
PHASE DET
20UT
XMITIOOUT/
VCRSWtTCH
HORIZ
SYNCSEP
HORIZ
SYNCSE,
PHASEOrtJ 8
12
FLYBK PULSE IN
11
HORIZOUT
TOP VIEW
APPLICATIONS
• Video terminals
• Television
ORDERING INFORMATION
DESCRIPTION
18-Pin Plastic DIP (SOT-l02HE)
January 14, 1987
TEMPERATURE RANGE
ORDER CODE
-2S0C to + 6S0C
TDA2S78A
9-14
8S3-114787202
Signetics Linear Products
Product Specification
TDA2578A
Sync Circuit With Vertical Oscillator and Driver
BLOCK DIAGRAM
HORIZONTAL FREQUENCY
ADJUSTMENT
10~F
-F
1J.!F
4.7 k
82
22 $-IF
150 nF
-"IV'r-o--'W'--'l+ ~ ~
820
+f-::L
30k
~TOPIN16
1-'-0+
4.7
,.--+-'V
4 •7""k->oM..-H
~F
·16>4mA
+12V
100l-'F
q,
2.7nF
+~
10
16
15
9"::"
VIDEO INPUT
~w......~-"-f--;~ HORi~~~TAL
1k
150
J_ pF
SEPARATOR
NOISE
INVERTER
(.. 12V)
January 14, 1987
17
100k
TO PIN 10
.J.
10 J. 0.2 rnA
47nF
< 4.0 mA
A
HORIZONTAL FLYBACK
PULSE
I
Signetics Unear Products
Product Specification
TDA2578A
Sync Circuit With Vertical Oscillator and Driver
VERTICAL DRIVE
+12 V
,,
+6.7 V
TD.l3&51
(PIN 1)
,.i
,
&.8k ,
-t
6.2k
1OnF
COINCIDENCE DETECTOR
.-....:::-.-.-=-.-.~.-.-~-.~
.
VERTICAL CO"""""TDR
,
r~-·--~~~~~~~~~;;:-r'"o-;·-----
4.7k
i
VERTICAL
FEEDBACK
+12 V
15k
8k
OSCILLATOR'
i
2.7k
.f1.anF
17
or· A
i
.-.-.-.-.--::-.-~.----------j
VERTlCAL OSCILUTDRlSAWTDOTH GENERATDR
"
, k
r'M..,...,f--t--.,...-----¥.I'r--t:
COMPOSITE
VIDEO
220k
i
ii
.....
SANDCASTLE
OUTPUT PUl.SE
_ _
_
I------~-;-~~;~;,.-;;~;;;--------
i
i
-=----------------------------1
,
VERTICAL SYNC SEPARATOR
,
I
+12V
I
CO"=TEj
i
i
+12 V
(PIN 10)
r--------~~-;;;~;;;~~~-;;..--------
i
i
i
51k
23k
i
i
-=-=i
-=----------------------------------------------------------
._70S
Figure la_ TDA2578A Circuit Diagram
January 14, 1987
9·16
Signetics Linear Products
Product Specification
TDA2578A
Sync Circuit With Vertical Oscillator and Driver
"":
--·-·-·~-~I~-;U·T;~;;;';~~~------!:;~;I~~----;~';E-~;~T~;;;--------+12 V
VIDEO
INPUT
COMPOSITE
,.
SYNC
!
I
i
i
~4.1nF
OSC REF __
•
2.
14
START-UP
PULSE
!HORIZONTAL
FLY BACK - - -
I
i
+12V
i
~
," ~~-;T~~~;;~~ ;~";T;;-C-A~~-;:~~~ ~~~T---_. __ -.:_.:.._-----=-----_._.-!
I
HORIZONTAL SYNC SEPARATOR
MUTE &
50/60 Hz
IDENTIFICATION
+12 V
1~+---=+-------<1......,
50/SO Hz
L____ .______ .::-:':r~. ___ ._._. ___ _
4.7 k
HORIZONTAL
SYNC SLICER
O.2T04mA
FLYBA~K
12
i>12 V
I
COMPOSITE
SYNC
HORIZONTAL
FLYBACK
I
82
_
i
HORIZONTAL
OUTPUT
PROTECTION
i
~NC
--.-.--:....-.--=:~!'~~~~-.-----._i
i
SLOW PHASE DETECTOR "'1
REFERENCE
2V
VOLTAGE OV 2V
i
•
(-- -. _._. -;;-~;;;;~:,:~~~;~; -- ._._-_.
osc REF ___ _
PULSE
TO PIN 16
•
SANOCASTLE
HORIZ OSC!
I
SYNC---
41J.
nF
HORIZONTAL
DRIVE
REF
•
VOLTAGE
15V
I
i
i
_ _ FLYBACK '" -=- -=·_·_-_·_·_·_·_·_·_·_---------1·_-_·_·_·_-_·_-_·_·_·_·----2.1V
GROUND
TOA2578A
SUPPLY SWITCH
~--------------------~--------------------~
Figure 1b. TDA2578A Circuit Diagram
January 14. 1987
TO PIN 16
I
9-17
+12V
10
q
220JJF
+
I
Signetics Linear Products
Product Specification
Sync Circuit With Vertical Oscillator and Driver
TDA2578A
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
8
rnA
116
Start current (Pin 16)
Vce = V10-9
Supply voltage (Pin 10)
13.2
V
PTOT
Total power dissipation
1.1
W
TSTG
Storage temperature range
-55 to + 150
'C
TA
Operating ambient temperature range
-25 to +65
'C
6J A
Thermal resistance from junction to
ambient in free air
50
'C
DC AND AC ELECTRICAL CHARACTERISTICS 116 = 5mA; Vee = 12V; TA = 25'C, unless otherwise specified.
LIMITS
UNIT
PARAMETER
SYMBOL
Min
Typ
Max
8.7
9.5
V
55
70
rnA
12
13.2
V
V
Supply
116
Supply current at Pin 16
4
V16-9
Stabilized supply voltage (Pin 16)
8
110
Supply current (Pin 10)
Vee = V10-9
Supply voltage (Pin 10)
10
8
rnA
Video Input (Pin 5)
VS_9
Top-sync level
VS_9(P_P)
Sync pulse amplitude (peak-to-peak value) 1
Slicing level
t1
1.5
3.1
3.75
0.15
0.6
1
V
35
50
65
%
Delay between video input and detector output
0.35
!-IS
Noise gate (Pin 5)
VS-9
0.7
Switching level
1
V
1100
Hz
First control loop (sync to OSCillator; Pin 8)
. 4mA). It is possible that the
main supply voltage at Pin lOis OV during
starting, so the main supply of the IC can be
taken from the horizontal deflection output
stage. The start of the other IC functions
depends on the value of the main supply
voltage at Pin 10. At 5.5V, all IC functions
I
Signetics Unear Products
Product Specification
Sync Circuit With Vertical Oscillator and Driver
start operating except the second phase
detector (oscillator to flyback pulse). The
output voltage of the second phase detector
at Pin 14 is clamped by means of an internally-loaded NPN emitter-follower. This ensures
that the duty factor of the horizontal output
signal (Pin 11) remains at about 6S%. The
second phase detector will close if the supply
voltage at Pin 10. reaches 8.8V. At this value,
the supply current for the horizontal oscillator
and output stage is delivered by Pin 10, which
also causes the voltage at Pin 16 to change
to a stabilized 8.7V. This change switches off
the NPN emitter-follower at Pin14 and activates the second phase detector. The supply
voltage for the horizontal oscillator will, however, still be referred to the stabilized voltage
at Pin 16, and the duty factor of the output
signal at Pin 12 is at the value required by the
delay at the horizontal deflection stage. Thus,
switch-off delays in the horizontal output
stage are compensated. When no horizontal
f1yback signal is detected, the duty factor of
the horizontal output signal is SO%.
Horizontal picture shift is possible by externally charging or discharging the 47nF capacitor
connected to Pin 14.
The IC also contains a synchronized vertical
oscillator/sawtooth generator. The oscillator
signal is connected to the intemal comparator
(the other side of which is connected to Pin
2), via an inverter and amplitude divider
stage. The output of the comparator drives an
emitter-follower output stage at Pin 1. For a
linear sawtooth in the oscillator, the load
resistor at Pin 3 should be connected to a
voltage source of 26V or higher. The sawtooth amplitude is not influenced by the main
supply at Pin 10. The feedback signal is
applied to Pin 2 and compared to the sawtooth signal at Pin 3. For an economical
feedback circuit with less picture bounce, the
sawtooth signal is internally pre-corrected by
6% (convex) referred to Pin 2. The linearity of
the vertical deflection current depends upon
the oscillator signal at Pin 3 and the feedback
Signal at Pin 2.
Synchronization of the vertical oscillator is
inhibited when the mute output is present at
Pin 13.
VIDEO SIGNAL
(PINS)
." DETECTOR
oUTPUT CURRENT
(PIN 8)
HORIZONTAL
OSCILLATOR SIGNAL
(PIN 15)
HORIZONTAL
OUTPUT SIGNAL
(PIN 11)
SWITCH.QFF DELAY
HORIZONTAL OUTPUT STAGE
FLY BACK PULSE
(PIN 12)
",DETECTOR
OUTPUT CURRENT
(PIN 14)
SANDCASTLE
PULSE
(PIN 17)
Figure 3. Timing Diagram of the TDA2578A
January 14, 1987
9-22
TDA2578A
To minimize the influence of the horizontal
part on the vertical part, a 6.7V bandgap
reference source is provided for supply and
reference of the vertical oscillator and comparator.
The sand castle pulse, generated at Pin 17,
has three different voltage levels. The highest
level (11 V) can be used for burst gating and
black level clamping. The second level (4.6V)
is obtained from the horizontal f1yback pulse
at Pin 12 and used for horizontal blanking.
The third level (2.SV) is used for vertical
blanking and is derived by counting the horizontal frequency pulses. For SOHz the blanking pulse duration is 21 lines, and for 60Hz it
is 17 lines. The blanking pulse duration and
sawtooth amplitude is automatically adjusted
via the SO/60Hz detector.
The IC also incorporates a vertical guard
circuit which monitors the vertical feedback
signal at Pin 2. If this level is below 3.3SV or
higher than 5.1SV, the guard circuit will insert
a continuous level of 2.SV into the sandcastJe
output signal. This will result in complete
blanking of the screen if the sand castle pulse
is used for blanking in the TV set.
Product Specification
Signetics Linear Products
Sync Circuit With Vertical Oscillator and Driver
TDA2578A
APPLICATION INFORMATION (Continued)
HORIZONTAL
FlYBACK
+12 V
SANDCASTLE PULSE
MUTE AND
SO/60HZ
IDENTIFICATION
>O.2mA
..
<4.0 rnA
1\
HORIZONTAL
DRIVE
r-+----+~--~~~_+-f----------~~_r--~V+
r,o
+"F
10
1k
>4mA
1:
1: ~
TnF L-InF
114
115
I'B
G.B
30k
k
220
2.7
~"F
~
11
r-
-flL.. ~
4.7 k
15 k
12
13
17
16
TDA257BA
S
7 4.7 k
B2
4
'---1,
100
k
1k
150 +
10
~PF ~"F
SG k
22~
~J
1'"j '0 ADJ.
(HORIZONTAL)
fOAOJ.
(VERTICAL)
fJ
VERTICAL
FEEDBACK
VERTICAL
DRIVE
+26 V (1)
VIDEO
NOTE:
1. ~ 26V for linear scan.
Figure 4. Typical Application Circuit Diagram; for Application of the TDA2578A With the TDA3651 - See Figure 7
F
33 k
TO PIN
1BOk
14~
TDA2578A
+12V
47k
lk
TOPIN~
lB
TDA2578A
,~1~O..k
I100nF~
NOTES,
1 kn resistor between Pin 18 and + 12V: without
muto function.
1BOkn between Pin 18 and ground: with mute
function.
Figure 5. Circuit Configuration at
Pin 14 for Phase Adjustment
January 14, 1987
Figure 6. Circuit Configuration at
Pin 18 for VCR Mode
9-23
I
Signetics Linear Products
Product Specification
TDA2578A
Sync Circuit With Vertical Oscillator and Driver
APPLICATION INFORMATION (Continued)
TDA3651
r
~
1
10nf
~
. l7
5
6
1
NC
330
VERTICAL
DEFLECTION
COILS
AT1236/20
47k
9
470
-::-
47nF
+
J;:220.F
8.2k
1k "LINEARITY
VERTICAL FEEDBACK
(PIN 2 TDA2578A)
8
U--
G~AX1~
Uk
VERTICAL DRIVE
(FROM PIN 1 TDA2578A)
100 pF
+
+26 V
Uk
SHIFT
27
+
6.8.F
1000pF
(16 V)
100
1.2
±3.9nF
27k
AMPLITUDE
-'
Figure 7. Typical Application Circuit Diagram of the TDA3651 (Vertical Output) When Used In Combination With the
TDA2578A, (90· Application)
January 14, 1987
9-24
Signetics
AN162
A Versatile High-Resolution
Monochrome Data and
Graphics Display Unit
Linear Products
Application Note
INTRODUCTION
The Data and Graphics Display (DGD) unit,
(also referred to as a Video Display Unit), is
built for wide ranging applications. It cons i sts
of a very high resolution CRT paired with
precision deflection coils and all the associated display circuitry, as shown in Figure 1.
Using the same printed circuit board and
components, it can easily be adapted to
operate over a wide range of line and field
frequencies with different flyback times in
either horizontal (landscape) or vertical (portrait) format.
The possible applications of this unit range
from video games to high·resolution displays.
However, it is as a computer terminal display
device that the DGD will be most useful.
Normally, it is the logic design that determines all the parameters to be specified in a
computer system, and it is only when the
logic circuitry has been finalized that a suitable display is sought. Consequently, the
display must be tailormade for the application. There are no signs of any standardization in the future. For this reason the DGD
has been designed to allow different dedicat-
ed display units to be built up very simply from
one basic design.
The DGD is a straightforward and efficient
design which will operate with line frequencies of between 15 and 70kHz and field
frequencies of 50 to 100Hz, interlaced or noninterlaced. All the design features combine to
provide the resolution required for very high
density displays (up to 1.5 million picture
elements per page). They also ensure a
sharp picture right to the screen corners, and
allow operation at high horizontal line frequencies without undue temperature rise. A
diode-split transformer provides combined
line scan and EHT and it is this component
which allows changes in line frequency and
flyback time to be accomplished very easily.
NOTE:
EHT stands for extreme haute-tension, or extreme high
voltage.
GENERAL DESCRIPTION
Figure 2 shows a block diagram of the DGD
unit and its auxiliary circuits. (The unit is to the
right of the broken line, with the auxiliary
circuits to the left.) The circuit diagram is
shown in Figure 3.
Both line scanning and EHT are provided by a
purpose-built diode-split transformer. It is the
flexibility of this device which produces the
extreme versatility of the DGD unit as a whole
and allows operation of the wide range of line
frequencies and flyback times. In addition, all
auxiliary power supply requirements are obtained from the same transformer. The primary is provided with several taps, each of which
corresponds to a different peak voltage and
hence flyback time. By careful positioning of
these transformer primary taps, and by utilizing both parallel and series connection of the
line deflection coils, a wide variety of f1yback
times can be accomodated in steps. Each
step allows sensible values of f1yback ratio for
the different line frequencies. Apart from the
selection of the correct transformer tap, the
only other components that may need to be
changed in order to use a different line
frequency are the oscillator timing capacitor
C6, S-correction capacitor C22, base drive
resistor R52, linearity control L1, and heater
resistor RB4 (see Figure 3).
Although deflection defocusing has been minimized by careful design of the line deflection
coils, there is still some focusing action in the
deflection process. Also, there is a difference
between the electron beam path lengths for
axial beams and those deflected to the tube
corners. These effects combine to produce a
change in focus requirements from the center
to the edges of the picture tube. To overcome
this, dynamic focus is employed. The active
dynamic focus circuit applies parabolic cor-
Figure 1. DGD Unit
February 19B7
The normal DGD requirements of good raster
geometry and minimal loss of display quality
between the screen center and corners are
even more important in high-definition systems. To ensure a display offering the best
possible resolution over the whole line frequency range, the unit uses high·quality purpose-designed deflection coils type AT1039.
These are paired with either the 12 in (M31326) or 15 in (M38·32B) picture tubes. These
coils have been designed using recently developed techniques to give good deflection
performance and raster geometry suitable for
correction by built-in magnets. For the 12 in
tube, type AT1039/03 deflection coils are
used. Two types of coil are available for the
15 in tube, the AT1039/00 which has been
optimized for portrait (vertical) formats and
the AT1039/01 for landscape (horizontal)
displays. Terminations to each coil are
brought out separately to allow for both series
and parallel connections.
9-25
•
Application Note
Signetics Linear Products
A Versatile High-Resolution Monochrome
Data and Graphics Display Unit
1V video
AN162
auxiliary circuits
main circuit
VIOEO
PREAMPLIFIER
VIDEO
OUTPUT
SSV HT
video 0-------------------0-'"
LINE
DRIVER
•. h.t. 17kV
LINE OUTPUT
STAGE
AT4043/64
TTL
....ve line
inputs
sync
DYNAMIC
FOCUS
SYNC
INVERTER
LINE
OSCILLATOR
-~~~~eo-
FIELO
TIMEBASE
________________~
TOA2595
:~~
TDA2653A
o__________________________~~~--------------------J
POWER
SUPPLY
Figure 2. DGD Unit Block Diagram
rection in both the line and field directions to
give precise focus over the wHole raster.
Because the electron gun is a unipotential
type, the tube has a fairly flat focus characteristic. The amplitude of the dynamic focus can
therefore be preset and adjustment is unnecessary.
Width control is accomplished with a seriesparallel inductance arrangement which does
not affect the flyback time or EHT. Adjustable
picture shift is supplied in both the line and
field directions by passing DC through the
appropriate deflection coils.
The TDA2595 line oscillator combination IC
provides the correct waveforms to drive the
line output transistor via a transformer-coupled driver stage. This IC includes both the
line oscillator and coincidence detector, a line
flyback pulse, obtained from the collector of
the line output transistor TR2, is required for
phase detection. A protection circuit which
turns off the output drive if the voltage at Pin
B is either below 4 or above BV is used to
provide overvoltage protection for the line
output stage.
February 19B7
All the field timebase functions are converted
by the TDA2653A IC. It takes a positive-going
field sync input at TIL level and drives the
impedance-matched AT-l 039 deflection coils
in series connection. A field blanking pulse,
which may be used for screen burn protection, is available from Pin 2. The Ie is
contained in a 13-lead DIP plastic power
encapsulation type SOT-141, which offers
straightforward heats inking.
An em iller-driven video output stage is used
with output transistor TR6 and driver TR7.
The collector load resistors RB7 and RBB with
peaking coil L5 and some compensation in
the emiller circuit ensure a bandwidth of
60MHz at 35V, measured at the cathode. In
order to minimize stray capacitance, the video
amplifier is placed on the tube-base printed
circuit board close to the cathode pin of the
tube. The 55V HT (High Tension) line is
provided from the line output stage.
The unit will accept video input at TIL level
with positive-going field sync and negativegoing line sync. However, inputs at other
levels and polarities may be accepted
by using the auxiliary circuits, as shown in
Figure 2.
9-26
The main HT line input will depend upon the
line frequency and varies from about 30 to
150V. If lower values of HT are preferred, a
floating tap will accommodate a series boosted circuit arrangement.
A 12V supply is required at all frequencies.
The total power consumption of the unit is
about 40W.
Standard measures are taken to protect the
circuitry in the event of a picture tube flashover. Spark gaps for all picture tube pins are
provided and all are returned to a single point
which is, in turn, connected to the outside
aquadag layer of the tube and the common
earth point.
To achieve a satisfactory stable display with
good linearity and one that is free from
undesirable modulation, well recognized procedures should be adopted with regard to
printed circuit board layout. It is essential that
each individual circuit block has its own
grounding system connected to a central
point on the main printed circuit board which
is, in turn, connected to the chassis. Circuit
layout within the individual blocks may also be
critical.
Signetlcs Linear Products
Application Note
A Versatile High-Resolution Monochrome
Data and Graphics Display Unit
AN162
Table 1. DGD Unit Specifications
Picture tube
12 in M31·326 series
15 in M3B·32B series
Deflection coils
AT1039 series
Une output transformer
AT2076/B4
Character display
Up
Une frequency
landscape format
portrait format
15 to 50kHz
15 to 70kHz
Field frequency
non·interlaced or interlaced
50
EHT
17kV
to 1.5 X 106 pixels
to 100Hz
Une linearity
Better than 3%
Field linearity
Better than 3%
Raster breathing
(0 to 100!lA)
Better than 2%
Une flyback time
3 to 91'S
Field flyback time
0.6ms
Video bandwidth
(at 35V output measured
at the cathode)
Input signals
Power input
60MHz
Positive field sync at TTL level, negative
line sync at TTL level, video input at TTL level
40W total
30 to 150V 36W
12V 4W
Originally published as "Technical Publication 115," ELCOMA, The Netherlands, 1983.
February 19B7
9-27
•
Signetics Linear Products
Application Note
A Versatile High-Resolution Monochrome
Data and Graphics Display Unit
_.JLn.
AN162
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February 1987
9-28
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Signetics Linear Products
Application Note
A Versatile High-Resolution Monochrome
Data and Graphics Display Unit
l- -
AN162
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Figure 3. Data and Graphics Display Unit Circuit Diagram (Continued)
February 1987
9-29
~
•
Signetics
AN1621
TDA2578A/TDA3651 PCB Layout
Directives
Application Note
Linear Products
The TDA2578A is a sync separator and
horizontal/vertical synchronization circuit
while the TDA3651 is a vertical deflection
output driver.
This application note covers general directives for the circuit and PCB layout to achieve
stable horizontal time stability and correct
vertical interface.
The TDA2578A combines both a horizontal
oscillator/PLL and a vertical oscillator/PLL.
When used in conjunction with a TDA3651
vertical driver, high system loop gains are
involved. This requires careful atlention to
ground points and consideration to magnetic
fields within the receiver/monitor design.
GENERAL PCB LAYOUT
DIRECTIVES
• Each IC and discrete component should
be surrounded by a good ground plane
(See Figure 1).
• The ground plane should not be a
complete closed-loop. This is to avoid
ground plane-induced currents created
by magnetic fields.
• All circuit peripheral components should
be connected to the ground plane.
• All high current points should be
grounded on another ground plane
(double-sided PCB).
• Each IC circuit should have its own
common "solid" ground point and
should be connected to the other
circuitry so that no "strange" ground
plane currents are injected.
• Input leads should be short and direct
to avoid cross-coupling by both
electrostatic and electromagnetic fields.
• A small value resistor in series with
input leads can decrease flashover IC
failure problems
• Position components with respect to
leakage fields of the horizontal line
output transformer.
February 1987
TDA2578A PCB
CONSIDERATION
TDA3651 PCB LAYOUT
CONSIDERATIONS
• Grounding point of vertical oscillator
timing capacitor (Pin 3 & ground) should
be connected to the Pin 9 ground pin,
not via a PCB trace which carries either
large horizontal line currents or video
information.
• The vertical feedback voltage input (Pin
2) decoupling capacitor should be
connected to the same PCB trace as
the vertical oscillator timing capacitor.
• The vertical deflection current loop
should be short and be of low
impedance, i.e., ample PCB traces on
Pin 5 deflection coil, coupling capacitor,
and connection to the feedback resistor
on Pin 4.
• Damping components and horizontal line
suppression across the yoke deflection
coil should be located as close as
possible to the deflection coil connector.
• The vertical feedback input (Pin 2) has
a very high input impedance; therefore,
the scaling resistors should be situated
close to Pin 2 to prevent parasitic
capacitive horizontal line cross-coupling.
• Horizontal line information modulated on
the vertical waveform at Pin 5 should
not exceed 1Vp.p. This is usually
caused by:
1. Inductive & capacitive coupling across
the yoke coils.
2. Capacitive coupling within vertical control loop.
3. Inductive magnetic coupling.
4. Supply voltage variations.
• The vertical integrator capacitor (Pin 4)
can carry high peak currents up to
30mA during vertical interval. Therefore
it should be firmly grounded to Pin 9,
not, however, by the same ground PCB
trace as used by the vertical oscillator
timing capacitor.
• The TDA2578A horizontal output (Pin
11) to drive the base of the horizontal
output transistor should be restricted to
30mA peak. This prevents disturbing
voltage drops on the TDA2578A ground
lead which can result in an offset
voltage to the vertical comparator.
• Special atlention is required when
capacitive coupling is used to drive the
horizontal output transistor.
• Vertical interlace is strongly influenced
by parasitic signals when coincidence
occurs between the vertical oscillator
flyback and the horizontal blanking
interval. Coincidence is determined by
slicing in the vertical integrator and the
pre-adjustment of the vertical oscillator.
• Decoupling of the supply voltages (Pins
10 and 16) should be kept as short
and direct to the ground pin (Pin 9) as
possible. Ripple on the supplies should
be less than 1%.
9-30
• Vertical input (Pin 1) requires a bypass
capacitor of 10pF to ground (Pin 2) to
suppress the IC current noise.
• Feedback capacitance of 220pF from
Pin 1 (input) and Pin 5 (output)
improves loop stability.
• Supply voltage decoupling (Pin 9)
should be connected directly to ground
(Pin 4).
• The supply to both the TDA2578A and
the TDA3651 should be decoupled at
the source to remove any extraneous
noise.
GENERAL
GROUND
PLANE ~
CONCEPT
~
~
I
CIRCUIT
I
Figure 1. General Ground Plane
Concept
TDA2579
Signetics
Synchronization Circuit
Product Specification
Linear Products
DESCRIPTION
The TDA2579 generates and synchronizes horizontal and vertical signals. The
device has a 3-level sandcastie output, a
transmitter identification signal and also
50/60Hz identification.
FEATURES
• Horizontal phase detector, (sync
to osc), sync separator and
noise inverter
• Triple current source In the
phase detector with automatic
selection
• Inhibit of horizontal phase
detector and video transmitter
identification
• Second phase detector for
storage compensation of the
horizontal output stage
• Stabilized direct starting of the
horizontal oscillator and output
stage
• Horizontal output pulse with
constant duty cycle value of
29}.1s
• Duty factor of the horizontal
output pulse is 50% when
horizontal fly back pulse is absent
• Internal vertical sync separator
and two Integration selection
times
• Divider system with three
different reset enable windows
• Synchronization Is set to 628
divider ratio when no vertical
sync pulses and no video
transmitter is identified
• Vertical comparator with a low
DC feedback signal
• 50/60Hz identification output
combined with mute function
• Automatic amplitude adjustment
for 50 and 60Hz and blanking
pulse duration
PIN CONFIGURATION
N Package
VERT OUT
1
16 ~~:TICIRCUIT
VERT
RAMP GEN
SOURCE
CURRENT
VIDEOIN
14 PHASE ADJUST
5
SYNC SEP 6
NOISE INV
7
PHASE OET
8
11 HORIZ DRIVE
TOP VIEW
•
APPLICATIONS
• Video terminals
• Television
• Video tape recorder
ORDERING INFORMATION
DESCRIPTION
16-Pin Plastic DIP (SOT-102HE)
November 14, 1986
TEMPERATURE
RANGE
ORDER CODE
o to +70°C
TDA2579N
9-31
853-0972 86554
Signetics Linear Products
Product Specification
Synchronization Circuit
TDA2579
BLOCK DIAGRAM
4.7~F
•
VIDEO
'200'..[""1
1k
-
SIGNAL
INPUT
vv
150nF
820
i-----oTOPIN16*
lOI'F
pf-+--WV-,+I q
4.71<
15
~iI'"~"-'w.......-'t--I
'-----'
r-++T--o~~~~ONTAL
lOPlN1S
TOA2579
"
...r-
A .. 1...
SANDCASTLE
OUTPUT
'OOk
TO VERTICAL DEFlECTION
CURRENT MEASURING RESISTOR
12
VERTICAl..
DRIVE
FLYBACK
PULse
INPUT
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
10
mA
116
Start current
V10
Supply voltage
13.2
V
PTOT
Power dissipation
1.2
W
TSTG
Storage temperature
-65 to + 150
DC
TA
Operating ambient temperature
-25 to +65
DC
(JJA
Thermal resistance from junction to
ambient in free air
50
DC/W
November 14, 1986
9-32
rIO""'
Signetics Linear Products
Product Specification
TDA2579
Synchronization Circuit
DC AND AC ELECTRICAL CHARACTERISTICS
TA = 25°C; 116 = 6.5mA; V10 = 12V, unless otherwise specified. Voltage
measurements are taken with respect to Pin 9 (ground).
LIMITS
PARAMETER
SYMBOL
UNIT
Min
Typ
Max
Supply
116
Supply current, Pin 16
V10 = OV
6.5
10
mA
116
Supply current, Pin 16
V10 = 9.5V
2.5
10
mA
V16
Stabilized voltage, Pin 16
8.1
110
Current consumption, Pin 10
Vee
Supply voltage range, Pin 10
9.5
8.7
9.3
V
68
85
mA
12
13.2
V
Video Input (Pin 5)
Vs
Top sync. level
1.5
3.1
3.75
V
Vs
Sync. pulse amplitude1
0.1
0.6
1
Vee
Slicing level 2
35
50
65
%
Delay between video input and de\. output (see also Figure 2)
0.2
0.3
0.5
MS
Sync. pulse noise level detector circuit active
600
mVTT
3
dB
Sync. Pulse
Noise level detector circuit hysteresis
Noise gate (Pin 5)
Vs
Switching level
+0.7
+1
V
First control loop (Pin 8) (Horizontal osc. to sync.)
.a.f
Holding range
.a.f
Catching range
±800
±600
Hz
±800
± 1100
Hz
Control sensitivity video
with respect to burstkey and flyback pulse
Slow time constant
2.5
kHz/MS
Normal time constant
10
kHz/MS
Fast time constant
5
kHz/MS
Phase modulation due to hum on the supply line Pin 103
0.2
MS/VTT
Phase modulation due to hum on input current Pin 163
0.08
Ms/mATT
Second control loop (Pin 14) (Horizontal flyback to horizontal oscillator)
.a.t.l/.a.1o
Control sensitivity
tD = 10MS
tD
Control range
1
tD
Control range for constant duty cycle horizontal output
1
200
Controlled edge of horizontal output signal Pin 11
300
600
I'S
> 45
I's
29 (-t flyback pulse)
positive
Phase adjustment (Pin 14) (via second control loop)
Control sensitivity
tD= 10J1S
114
±60
Maximum allowed control current
November 14, 1986
MAIl's
25
9-33
MA
•
Signetics Linear Products
Product Specification
TDA2579
Synchronization Circuit
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) TA = 25·C; 1'6 - 6.5mA; V,o = 12V, unless otherwise
specified. Voltage measurements are taken with respect
to Pin 9 (ground).
LIMITS
PARAMETER
SYMBOL
UNIT
Min
Typ
Max
Horizontal oscillator (pIn 15) (C = 2.7nF; Rosc = 33kO
f
Frequency (no sync.)
af
Spread (fixed external component, no sync.)
15625
af
Frequency deviation between starting point output signal and
stabilized condition
+5
TC
Temperature coefficient
10
Hz
±4
%
+8
%
·C
Horizontal output (Pin 11) (Open-collector)
V"
Output voltage high
V"
Start voltage protection Ontemal zener diode)
1'6
Low input current Pin 16 protection output enabled
V"
Output voltage low start condition (I"
13.2
13
= lOrnA)
Duty cycle output current during starting 1'6 = 6.SmA
V"
55
Output voltage low normal condition (I" = 25mA)
Duty cycle output current without flyback pulse Pin 12
45
Duration of the output pulse high to = BIlS
27
V
15.8
V
5.5
6.5
mA
0.1
0.5
V
65
75
%
0.3
0.5
V
50
55
%
29
31
IlS
positive
Controlled edge
Temperature coefficient horizontal output pulse
-0.05
IlS,.C
Sandcastle output signal (pIn 17) (ILOAO = 1rnA)
V17
V17
V17
V17
tp
V'2
Output voltage during:
burstkey
horizontal blanking
vertical blanking
9.75
4.1
2
10.6
4.5
2.5
Zero level output voltage
ISINK = 0.5mA
Pulse width:
burstkey
horizontal blanking
Phase pOSition burstkey
Time between middle synchronization pulse at Pin 5 and start
burst at Pin 17
Time between start sync. pulse and end of burst pulse, Pin 17
November 14, 19B6
9-34
4.9
3
V
V
V
0.7
V
3.45
3.75
1
4.1
IlS
V
2.3
2.7
3.1
j.tS
9.2
IlS
Product Specification
Signetics Linear Products
TDA2579
Synchronization Circuit
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) TA = 25°C; 11B = 6.5mA; V10 = 12V, unless otherwise
specified. Voltage measurements are taken with respect
to Pin 9 (ground).
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
Coincidence detector, video transmitter identification circuit and time constant switching levels (see also Figure 1)
118
Detector output current
0.25
mA
V18
Voltage level for in sync. condition ('1'1 normal)
6.5
V
V18
Voltage for noisy sync. pulse ('1'1 slow and gated)
10
V
V18
Voltage level for noise only5
V18
Switching level normal-to-fast
3.2
3.5
3.8
V
V18
Switching level
Mute output active and fast-to-slow
1.0
1.2
1.4
V
V18
Switching level frame period counter (3 periods fast)
0.08
0.12
0.16
V
V18
Switching level
Siow-to-fast (locking)
Mute output inactive
1.5
1.7
1.9
V
V18
Switching level fast-to-normal (locking)
4.7
5.0
5.3
V
V18
Switching level normal-to-slow (gated sync. pulse)
7.4
7.8
8.2
V
0.15
0.32
V
5
rnA
1
/lA
8.1
V
9
0.3
V
Video transmitter identification output (Pin 13)
V13
Output voltage active (no sync., 113
113
Sink current active (no sync.), V13
113
Output current inactive (sync. 50Hz)
= 2mA)
< lV
SO/60Hz identification (Pin 13) (R 13 positive supply 15kn)
V13
V13
Emitter-follower, PNP
2 X fH
60Hz: - - < 576 voltage
fV
2 X fH
50Hz: - - > 576 voltage
fV
7.2
7.65
V
VlO
Flyback input pulse (Pin 12)
V12
Switching level
112
Input current
V12
Input pulse
RIN
Input resistance
V
+1
+0.2
+4
mA
12
Vce
3
kn
2.5
/lS
Pulse width charge current
26
clock
pulses
Charge current
3
mA
Phase position without shift
tD
Time between the middle of the sync. pulse at Pin 5 and the
middle of the horizontal blanking pulse of Pin 17
Vertical ramp generator (Pin 3)
13
Top level ramp signat voltage
V3
Divider in 50Hz modeB
5.1
5.5
5.9
V
V3
Divider in 60Hz modeB
4.35
4.7
5.05
V
Ramp amplitude C3 = 150nF,
R4 = 330kn, 50HzB
R4 = 330kn, 60HzB
November 14, 1986
3.1
2.5
9-35
Vee
Vee
•
Product Specification
Signetics Linear Products
TDA2579
Synchronization Circuit
DC AND AC ELECTRICAL CHARACTERISTICS (Continued)
TA = 25°C; 116 = 6.5mA; v10 = 12V, unless otherwise
specified. Voltage measurements are taken with respect
to Pin 9 (ground).
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
6.6
7.1
7.6
V
55
IlA
Current source (Pin 4)
= 201lA
V4.9
Output voltage 14
14
Allowed current range
TC
TC
TC
Temperature coefficient output voltage
14 = 20llA
14 = 40llA
14 = 501lA
10
Comparator (Pin 2) Ca = 150nF; R4
V2 - 9
V2 - 9
10- 6rC
1O- 6/ o C
10Bre
+50
+20
-40
= 330kn
Input voltage
DC level 6
AC level
0.9
1
0.8
Deviation amplitude 50/60Hz
1.1
V
Vee
2.5
%
Vertical output stage, Pin 1 (NPN) emitter follower
V1 -9
Output voltage 10 Pin 1
Rs
Sync. separator resistor
= + 1.5mA
4.8
Continuous sink current
Vertical guard circuit (Pin 2) Active (V 17
V2
Switching level lows
V2
Switching level high6
5.2
0.25
mA
= 2.5V)
> 1.7
< 0.3
1.9
2.1
V
0.4
0.5
V
1. Up to Wp.p the slicing level is constant, at amplitudes exceeding 1Vp.p the slicing level will increase.
2. The slicing level is fixed by the formula:
5.3 + Rs
X
100%
(Rs value in kU)
3. Measured between Pin 5 and sandcastle output Pin 17.
4. Divider in search (large) mode:
start: reset divider = start vertical sync. plus 1 clock pulse
stop:
2 X fH
n=
n=
--r::;2 X fH
--r::;-
> 576 clock pulse 42
< 576 clock pulse 34
Divider in small window mode:
start: clock pulse 517 (60Hz) clock pulse 619 (50Hz)
stop: clock pulse 34 (60Hz) clock pulse 42 (50Hz)
5. Depends on De level of Pin 5, given value is valid for V5'" 5V.
6. Value related to internal zener diode reference voltage source spread includes the complete spread of reference voltage.
November 14, 1986
V
n
NOTES:
P=~
5.6
160
9-36
Signetics Linear Products
Product Specification
Synchronization Circuit
TDA2579
FUNCTIONAL DESCRIPTION
Vertical Part (Pins 1, 2, 3, 4)
The Ie embodies a synchronized divider system for generating the vertical sawtooth at
Pin 3. The divider system has an internal
frequency doubling circuit, so the horizontal
oscillator is working at its normal line frequency and one line period equals 2 clock pulses.
Due to the divider system, no vertical frequency adjustment is needed. The divider has
a discriminator window for automatically
switching over from the 60Hz to 50Hz system.
The divider system operates with 3 different
divider reset windows for maximum interference/disturbance protection.
The windows are activated via an up/down
counter. The counter increases its counter
value by 1 for each time the separated
vertical sync. pulse is within the searched
window. The count is reduced by 1 when the
vertical sync. pulse is not present.
Large (Search) Window: Divider
Ratio Between 488 and 722
This mode is valid for the following conditions:
1. Divider is looking for a new transmitter.
2. Divider ratio found, not within the narrow
window limits.
3. Non-standard TV-signal condition detected
while a double or enlarged vertical sync.
pulse is still found after the internallygenerated antitop flutter pulse has ended.
This means a vertical sync. pulse width
larger than 8 clock pulses (50Hz), that is,
10 clock pulses (60Hz). In general this
mode is activated for video tape recorders
operating in the featureltrick mode.
4. Up/down counter value of the divider system operating in the narrow window mode
drops below count 1.
5. Externally setting. This can be reached by
loading Pin 18 with a resistor of 180kn to
earth or connecting a 3.6V diode stabistor
between Pin 18 and ground.
Narrow Window: Divider Ratio
Between 522 - 528 (60Hz) or
622 - 628 (50Hz).
The divider system switches over to this
mode when the up/down counter has
reached its maximum value of 12 approved
vertical sync. pulses. When the divider operates in this mode and a vertical sync. pulse is
missing within the window, the divider is reset
at the end of the window and the counter
value is lowered by 1. At a counter value
below count 1 the divider system switches
over to the large window mode.
MIDDLE OF THE
HORIZONTAL SYNC PULSE
VIDEO SIGNAL
(PIN 5)
<1'1 DETECTOR
OUTPUT CURRENT
(PIN 8)
HORIZONTAL
OSCILLATOR SIGNAL
(PIN '5)
HORIZONTAL
OUTPUT SIGNAL
(PIN 11)
FLYBACK PULSE
(PIN '2)
• I
SWITCHING LEVEL
OV
';2 DETECTOR
OUTPUT CURRENT
(PIN '5)
i--I-+-----<\jllV
SANDCASTLE PULSE
(PIN '7)
HORIZONTAL BLANKING
Fl"""
:
:
I
:
LOIVIDER IN
SEARCH
WINDOW
MODE
;.... ~~i~ DIVIDER
--l
j
.""--c
12JLs
50Hz: 42 CLOCK PULSES
60Hz: 34 CLOCK PULSES
<\j4.5V
<\j2.5V
~g~~~ :~ gtgg~ ~~t~~~
Figure 1. Timing Diagram of the TDA2579
Standard TV Norm
When the up/down counter has reached its
maximum value of 12 in the narrow window
mode, the information applied to the up/down
counter is changed such that the standard
divider ratio value is tested. When the counter
has reached a value of 14, the divider system
is changed over to the standard divider ratio
mode. In this mode the divider is always reset
at the standard value even if the vertical sync.
pulse is missing. A missed vertical sync. pulse
lowers the counter value by 1. When the
counter reaches the value of 10, the divider
system is switched over to the large window
mode. The standard TV norm condition gives
maximum protection for video recorders playing tapes with anti-copy guards.
No TV Transmitter Found: (Pin
18 < 1.2V)
In this condition, only noise is present, the
divider is reset to count 628. In this way a
November 14, 1986
~~S
9-37
stable picture display at normal height is
achieved.
Video Tape Recorders in
Feature Mode
It should be noted that some VTRs operating
in the feature modes, such as picture search,
generate such distorted pictures that the no
TV transmitter detection circuit can be activated as Pin V's drops below 1.2V. This
would imply a rollowing picture (condition d).
In general, VTR machines use a reinserted
vertical sync. pulse in the feature mode.
Therefore, the divider system has been made
such that the automatic reset of the divider at
count 628 when V's is below 1.2V is inhibited
when a vertical sync. pulse is detected.
The divider system also generates the antitop flutter pulse which inhibits the phase 1
detector during the vertical sync. pulse. The
width of this pulse depends on the divider
mode. For the divider mode 1I, the start is
•
Slgnetics Linear Products
Product Specification
Synchronization Circuit
generated at the reset of the divider. In
modes!1 and g, the anti-top flutter pulse starts
at the beginning of the first equalizing pulse.
The anti-top flutter pulse ends at count 8 for
50Hz and count 10 for 60Hz. The vertical
blanking pulse is also generated via the
divider system. The start is at the reset of the
divider while the blanking pulse ends at count
34 (17 lines for 60Hz, and at count 42 (21
lines) for 50Hz systems. The vertical blanking
pulse generated at the sandcastle output Pin
17 is made by adding the anti-top flutter pulse
and the blank pulse. In this way the vertical
blanking pulse starts at the beginning of the
first equalizing pulse when the divider operates in the !1 or g mode. For generating a
vertical linear sawtooth voltage a capacitor
should be connected to Pin 3. The recommended value is 150nF to 330nF (see Block
Diagram).
The capacitor is charged via an internal
current source starting at the reset of the
divider system. The voltage on the capacitor
is monitored by a comparator which is activated also at reset. When the capacitor has
reached a voltage value of 5.5V for the 50Hz
system or 4.7V for the 60Hz system the
voltage is kept constant until the charging
period ends. The charge period width is 26
clock pulses. At clock pulse 26 the comparator is switched off and the capacitor is discharged by an NPN transistor current source,
the value of which can be set by an external
resistor between Pin 4 and ground (Pin 9). Pin
4 is connected to a PNP transistor current
source which determines the current of the
NPN current source. The PNP current source
on Pin 4 is connected to an internal zener
diode reference voltage which has a typical
voltage of '" 7.1V. The recommended operating current range is 10 to 50pA. The resistance at pin R4 should be 140 to 700kn. By
using a double current mirror concept the
vertical sawtooth pre-correction can be set on
the desired value by means of external components between Pin 4 and Pin 3, or. by
connecting the Pin 4 resistor to the vertical
current measuring resistor of the vertical
output stage. The vertical amplitude is set by
the current of Pin 4. The vertical feedback
voltage of the output stage has to be applied
to Pin 2. For the normal amplitude adjustment
the values are DC = IV and AC = 0.8V. Due
to the automatic system adaption both values
are valid for 50Hz and 60Hz.
The low DC-voltage value improves the picture bounce behaviour as less parabola compensation is necessary. Even a fully DCcoupled feedback circuit is possible.
Vertical Guard
The IC also contains a vertical guard circuit.
This circuit monitors the vertical feedback
signal on Pin 2. When the level on Pin 2 is
below O.4V or higher than 1.9V, the guard
November 14, 1986
TDA2579
circuit inserts a continuous level of 2.5V in the
sandcastle output signal of Pin 17. This
results in the blanking of the picture displayed, thus preventing a burnt-in horizontal
line. The guard levels specified refer to the
zener diode reference voltage source level.
Driver Output
The driver output is at Pin 1, it can deliver a
drive current of 1.5mA at 5V output. The
internal impedance is about 150n. The output pin is also connected to an internal
current source with a sinking current of
0.25mA.
Sync. Separator, Phase
Detector and TV Station
Identification, (Pins 5, 6, 7, 8,
and 18)
The video input signal is connected to Pin 5.
The sync. separator is designed such that the
slicing level is independent of the amplitude
of the sync. pulse. The black level is measured and stored in the capacitor at Pin 7.
The slicing level value is stored in the capacitor at Pin 6. The slicing level value can be
chosen by the value of the external resistor
between Pins 6 and 7. The value is given by
the formula:
RS x 100
P = - - - (Rs value in kn)
5.3 + Rs
Where Rs is the resistor between Pins 6 and
7 and top sync. level equals 100%. The
recommended resistor value is 5.6kn.
Black Level Detector
A gating signal is used for the black level
detector. This signal is composed of an
internal horizontal reference pulse with a duty
cycle of 50% and the flyback pulse at Pin 12.
In this way the TV transmitter identification
operates also for all DC conditions at input
Pin 5 (no video modulation, plain carrier only).
During the frame interval the slicing level
detector is inhibited by a signal which starts
with the anti-top flutter pulse and ends with
the reset vertical divider circuit. In this way
shift of the slicing level due to the vertical
sync. signal is reduced and separation of the
vertical sync. pulse is improved.
Noise Inverter
An internal noise inverter is activated when
the video level at Pin 5 drops below 0.7V. The
IC embodies also a built-in sync. pulse noise
level detection circuit. This circuit is directly
connected to Pin 5 and measures the noise
level at the middle of the horizontal sync.
pulse. When a noise level of 600mVp.p is
detected, a counter circuit is activated. A
video input signal is processed as "acceptable noise-free" when 12 out of 16 sync.
pulses have a noise level below 600mV for
two succeeding frame periods. The sync.
9-38
pulses are processed during a 16 line width
gating period generated by the divider system. The measuring circuit has a built-in noise
level hysteresis of about 150mV ('" 3dB).
When the "acceptable noise-free" condition
is found, the phase detector of Pin 8 is
switched to not-gated and normal time constant. When a higher sync. pulse noise level
is found, the phase detector is switched over
to slow time constant and gated sync. pulse
phase detection, At the same time the integration time of the vertical sync. pulse separator is adapted.
Phase Detector
The phase detector circuit is connected to Pin
8. This circuit consists of 3 separate phase
detectors which are activated depending on
the voltage of Pin 18 and the state of the
sync. pulse noise detection circuit.
All three phase detectors are activated during
the vertical blanking period, this with the
exception of the anti-top flutter pulse period,
and the separated vertical sync. pulse time.
As a result, phase jumps in the video signal
related to video head takeover of video recorders are quickly restored within the vertical
blanking period. At the end of the blanking
period, the phase detector time constant is
lowered by 2.5 times. In this way no need for
external VTR time constant switching exists,
so all station numbers are suitable for signals
from VTR, video games or home computers.
For quick locking of a new TV station starting
from a noise-only signal condition (normal
time constant), a special circuit is incorporated. A new TV station which is not locked to
the horizontal oscillator will result in a voltage
drop below 0.1 V at Pin 18. This will activate a
frame period counter which switches the
phase detector to fast for 3 frame periods.
Horizontal Oscillator
The horizontal oscillator will now lock to the
new TV station and as a result, the voltage on
Pin 18 will increase to about 6.5V. When Pin
18 reaches a level of 1.8V the mute output
transistor of Pin 13 is switched off and the
divider is set to the large window. In general
the mute signal is switched off within 5ms (pin
CIS = 47nF) after reception of a new TV
Signal. When the voltage on Pin 18 reaches a
level of 5V, usually within 15ms, the frame
counter is switched off and the time constant
is switched from fast to normal.
If the new TV station is weak, the sync. noise
detector is activated. This will result in a
changeover of Pin 18 voltage from 7V to '"
1OV. When Pin 18 exceeds the level of 7.8V
the phase detector is switched to slow time
constant and gated sync. pulse condition.
Signetics Linear Products
Product Specification
Synchronization Circuit
When desired, most conditions of the phase
detector can also be set by external means in
the following way;
a. Fast time constant TV transmitter identification circuit not active, connect Pin 18 to
earth (Pin 9).
TDA2579
y
MUTE
(PIN 13)
}
",
GATING
'1'1 DETECTOR
b. Fast time constant TV transmitter identifi·
cation circuit active, connect a resistor of
180kn between Pin 18 and ground.
This condition can also be set by using a
3.6V stabistor diode instead of a resistor.
c. Slow time constant, (with exception of
frame blanking period), connect Pin 18 via
a resistor of 10kn to +12V, Pin 10. In this
condition the transmitter identification circuit is not active.
d. No switching to slow time constant desired
(transmitter identification circuit active),
connect a 6.8V zener diode between Pin
18 and ground.
Figure 2 illustrates the operation of the 3
phase detector circuits.
Supply (Pins 9, 10 and 16)
The IC has been designed such that the
horizontal oscillator and output stage can
start operating by application of a very low
supply current into Pin 16.
The horizontal oscillator starts at a supply
current of about 4.5mA. The horizontal output
stage is forced into the non-conducting stage
until the supply current has a typical value of
5.5mA. The circuit has been designed so that
after starting the horizontal output function a
current drop of "" 1mA is allowed. The starting circuit gives the possibility to derive the
main supply (Pin 10), from the horizontal
output stage. The horizontal output signal can
also be used as the oscillator signal for
synchronized switch-mode power supplies.
The maximum allowed starting current is
10mA. The main supply should be connected
to Pin 10, and Pin 9 should be used as
ground. When the voltage on Pin 10 increases from zero to its final value (typically
12V) a part of the supply current of the
starting circuit is taken from Pin 10 via internal
diodes, and the voltage on Pin 16 will stabilize
to a typical value of 8.7V.
In stabilized condition (Pin V10 > 9.5V) the
minimum required supply current to Pin 16 is
"" 2.5mA. All other IC functions are switched
on via the main supply voltage on Pin 10.
When the voltage on Pin 10 reaches a value
of "" 7V the horizontal phase detector circuit
is activated and the vertical ramp on Pin 3 is
started. The second phase detector circuit
and burst pulse circuit are started when the
voltage on Pin 10 reaches the stabilized
voltage value of Pin 16 which is typically 8.7V.
For clOSing the second phase detector loop,
a flyback pulse must be applied to Pin 12.
November 14, 1986
., DETECTOR
18"'" O.4mA
'1'2 DETECTOR
18"" O.4mA
'f'3 detector
Is= 1mA
f\~
I\.
B
A
VOLTAGE
(PIN 18)
O.1V
I
c
1.2V
1
1.8V
l\
D
\
E
3.5V
I
sv
F
G
8.5V
Figure 2. Timing Diagram, Phase Detectors.
When no flyback is detected, the duty cycle
of the horizontal output stage is 50%.
For remote switch-off Pin 16 can be connected to ground (via an NPN transistor with a
series resistor of "" 500n) which switches off
the horizontal output.
Horizontal Oscillator, Horizontal
Output Transistor, and Second
Phase Detector (Pins 11, 12, 14
and 15)
The horizontal oscillator is connected to Pin
15. The frequency is set by an external RC
combination between Pin 15 and ground, Pin
9. The open collector horizontal output stage
is connected to Pin 11. An internal zener
diode configuration limits the open voltage of
Pin 11 to "" 14.5V.
The horizontal output transistor at Pin 11 is
blocked until the current into Pin 16 reaches a
value of "" 5.5mA.
A higher current results in a horizontal output
signal at Pin 11, which starts with a duty cycle
of "" 35% HIGH.
The duty cycle is set by an internal current
source-loaded NPN emitter-follower stage
connected to Pin 14 during starting. When Pin
16 changes over to voltage stabilization, the
NPN emitter-follower and current source load
at Pin 14 are switched off and the second
phase detector circuit is activated, provided a
horizontal flyback pulse is present at Pin 12.
When no flyback pulse is detected at Pin 12
the duty cycle of the horizontal output stage is
set to 50%.
The phase detector circuit at Pin 14 compensates for storage time in the horizontal deflec·
tion output stage. The horizontal output pulse
9-39
duration in 29j1S HIGH for storage times
between 1j1S and 17 j.lS (29j1S flyback pulse of
12j1S). A higher storage time increases the
HIGH time. Horizontal picture shift is possible
by forcing an external charge or discharge
current into the capacitor of Pin 14.
Mute Output and 50/60Hz
Identification (PIn 13)
The collector of an NPN transistor is connected to Pin 13. When the voltage on Pin 18
drops below 1.2V (no TV transmitter) the NPN
transistor is switched ON.
When the voltage on Pin 18 increases to a
level of "" 1.8V (new TV transmitter found) the
NPN transistor is switched OFF.
Pin 13 has also the possibility for 50/60Hz
identification. This function is available when
Pin 13 is connected to Pin 10 (+ 12V) via an
external pull-up resistor of 10 - 20kn. When
no TV transmitter is identified, the voltage on
Pin 13 will be LOW « 0.5V). When a TV
transmitter with a divider ratio> 576 (50Hz) is
detected the output voltage of Pin 13 is HIGH
(+12).
When a TV transmitter with a divider ratio < 576 (60Hz) is found an internal PNP
transistor with its emitter connected to Pin 13
will force this pin output voltage down to ""
7.5V.
Sandcastle Output (Pin 17)
The sandcastle output pulse generated at Pin
17, has three different voltage levels. The
highest level, (11V), can be used for burst
gating and black level clamping. The second
level, (4.5V), is obtained from the horizontal
flyback pulse at Pin 12, and is used for
horizontal blanking. The third level, (2.5V), is
used for vertical blanking and is derived via
•
Signetics Linear Products
Product Specification
TDA2579
Synchronization Circuit
the vertical divider system. For 50Hz the
blanking pulse duration is 42 clock pulses and
for 60Hz it is 34 clock pulses started from the
vertical divider reset. For TV signals which
have a divider ratio between 622 and 628 or
522 and 528 the blanking pulse is started at
the first equalizing pulse.
TYPICAL APPLICATION
r---------------------------------,
470
2k
VERTICAL DRIVE
(FROM PIN 1 TDA2579)
VERTlf~~ ~~~~~~~ O - -___p--___p--w\-.....- - ;
+26V
1.0
Figure 3
November 14, 1986
9-40
TDA2593
Signetics
Horizontal Combination
Product Specification
Linear Products
DESCRIPTION
The TDA2593 is a monolithic integrated
circuit intended for use in color television
receivers in combination with TDA2510,
TDA2520, TDA2560 as well as with
TDA3505, TDA3510, and TDA3520.
FEATURES
• Horizontal oscillator based on
the threshold switching principle
• Phase comparison between sync
pulse and oscillator voltage (,,01)
• Internal key pulse for phase
detector (,,01) (additional noise
limiting)
• Phase comparison between line
flyback pulse and oscillator
voltage (,,02)
• Larger catching range obtained
by coincidence detector (,,03;
between sync and key pulse)
• Switch for changing the filter
characteristic and the gate circuit
(VCR operation)
• Sync separator
• Noise separator
• Vertical sync separator and
output stage
• Color burst keying and line
flyback blanking pulse generator
• Phase shifter for the output
pulse
• Output pulse duration switching
• Output stage with separate
supply voltage for direct drive of
thyristor deflection circuits
•. Low supply voltage protection
PIN CONFIGURATION
N Package
Vee 1
15 ~~FREQ
TRIG
PULSE IN
LINE
PULSE OUT
PULSEDUR
SWITCH
PHASE
SHIFTER
FBPULSEIN
6
BLANK
PULSE OUT
VERT SYNC
PULSE OUT - ._ _ _.....-lOP VIEW
•
APPLICATIONS
• Video monitors
• TV receivers
ORDERING INFORMATION
DESCRIPTION
16·Pin Plastic DIP (SOT·38)
January 14, 1987
TEMPERATURE RANGE
ORDER CODE
-20·C to + 70·C
TDA2593N
9-41
853·0031 87195
Signetics linear Products
Product Specification
TDA2593
Horizontal Combination
BLOCK DIAGRAM
+{PINt POINT A)
PULSE DURATION
_+__
VlDEOINPUT_......
v\'-u.
I
...pF
...
...
_ _-i10
UM
12
aSk
~ICoSCRose
12k
22M
0A7,*,
':'
-I~
,,.
.IHOR'FCIACurr
+(PIN1:POINT A)
!O.ael'F
FREOENCY
~01
~. FOR loADJUBr
BC0875O$
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
UNIT
Vl-16
V2-16
Supply voltage
at Pin 1 (voltage source)
at Pin 2
PARAMETER
13.2
18
V
V
V4-16
±VS-16
±V1O-16
Vll-16
Voltages
Pin 4
Pin 9
Pin 10
Pin 11
13.2
6
6
13.2
V
V
V
V
650
mA
400
mA
1
10
10
2
mA
mA
mA
mA
14
±16
-17
111
Currents
Pins 2 and 3 (thyristor driving)
(peak value)
Pins 2 and 3 (transistor driving)
(peak value)
Pin 4
Pin 6
Pin 7
Pin 11
PrOT
Total power dissipation
TSTa
Storage temperature range
TA
Operating ambient temperature range
12M. -13M
12M. -13M
January 14. 1987
800
mW
-25 to +125
·C
-20 to +70
·C
9-42
Product Specification
Signetics Linear Products
TDA2593
Horizontal Combination
DC AND AC ELECTRICAL CHARACTERISTICS at Vce = 12V; TA = 25'C; measured in Block Diagram.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
Sync separator
V9-16
Input switching voltage
Ig
Input keying current
Ig
Ig
Ig
Switch off current
V9 - 16(P.P)
Input signal (peak-to-peak value)
0.8
5
V
100
p.A
Input leakage current at Vg -16 = -5V
1
p.A
Input switching current
5
p.A
100
150
3
p.A
4
Vl
100
p.A
Noise separator
V1O - 16
Input switching voltage
110
Input keying current
110
Input switching current
110
Input leakage current at Vl0-16 =-5V
VlO - 16(P-P)
Input signal (peak-to-peak value)
VlO - 16(P-P)
Permissible superimposed noise signal (peak-to-peak value)
V
1.4
5
100
150
3
p.A
1
p.A
4
Vl
7
V
2
rnA
Line flyback pulse
16
Input current
V6- 16
Input switching voltage
V6- 16
Input limiting voltage
0.02
1
1.4
-0.7
V
+1.4
V
Switching on VCR
Vl1 -16
Vl1 - 16
-111
111
o to 2.5
9 to Vl-16
Input voltage
V
V
200
2
Input current
p.A
rnA
Pulse duration switch for t = 7/1s (thyristor driving)
V4- 16
Input voltage
14
Input current
9.4 to Vl -16
200
V
/1A
Pulse duration switch for t = 14/15 + to (transistor driving)
V4- 16
Input voltage
0
-14
Input current
200
3.5
V
/1A
Pulse duration switch for t=O; V3 _ 16=0 or input Pin 4 open
V4- 16
Input voltage
14
Input current
5.4
0
6.6
V
0
/1A
Vertical sync pulse (positive-going)
Va-16(p-P)
Output voltage (peak-to-peak value)
11
V
Ra
Output resistance
2
kn
tON
Delay between leading edge of input and output signal
15
/15
tOFF
Delay between trailing edge of input and output signal
Ion
/15
January 14, 1987
10
9-43
•
Signetics Linear Products
Product Specification
Horizontal Combination
TDA2593
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) at
Vee = 12V; TA = 25°C; measured in Block Diagram.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
Burst gating pulse (positive-going)
V7-16(P-P)
Output voltage (peak-to-peak value)
R7
Output resistance
10
tp
Pulse duration; V7 -16
t
Phase relation between middle of sync pulse at the input and
the leading edge of the burst gating pulse; V7 -16 = 7V
17
Output trailing edge current
= 7V
11
V
70
.11
3.7
4
4.3
I1 s
I1S
2.15
2.65
3.15
2
I1 s
mA
Line flyback-blanking pulse (positive-going)
V7-16(P-P)
Output voltage (peak-to-peak value)
5
V
R7
Output resistance
70
.11
17
Output trailing edge current
2
mA
4
Line drive pulse (positive-going)
VS-16(P-Pj
Output voltage (peak-to-peak value)
10.5
V
Rs
Rs
Output resistance
for leading edge of line pulse
for trailing edge of line pulse
2.5
20
.11
.11
tp
Pulse duration (thyristor driving) V4 -16
tp
Pulse duration (transistor driving) V4 - 16
Vl - 16
Supply voltage for switching off the output pulse
= 9.4 to V 1_ 16 V
= a to 4V; tFP = 1211S
5.5
7
B.5
I1S
14 + tD
I1S2
4
V
2.6
p.ss
Overall phase relation
t
Phase relation between middle of sync pulse and the middle of
the flyback pulse
IAtl
Tolerance of phase relation
Als/At
The adjustment of the overall phase relation and consequently
the leading edge of the line drive occurs automatically by phase
control B.2V 6
ilf
Catching and holding range (B2kO between Pins 13 and 15)
±7BO
Hz
il(ilf)
Spread of catching and holding range
±10
%4
high ohmic
low ohmic
Control sensitivity
kHz/l's
2
Phase comparison '1'2 and phase shifter
V5-16
Control voltage range
±15M
Control current (peak value)
1
R5
Output resistance
at V5-16 = 5.4 to 7.6V7
at V5-16 < 5.4 or > 7.6V
B
5.4
7.6
V
mA
high ohmic
kO
15
Input leakage current
V5 -16 = 5.4 to 7.6V
5
ji.A
tD
Permissible delay between leading edge of output
pulse and leading edge of flyback pulse (tFP = 121's)
15
I'S
iltl iltD
Static control error
0.2
%
6
V
Coincidence detector '1'3
V11 - 16
Output voltage
111M
-111M
Output current (peak value)
without coincidence
with coincidence
0.5
0.1
0.5
mA
mA
Time constant switch
V12 - 16
Output voltage
± 112
Output current (limited)
R12
R12
Output resistance
at V11 - 16 = 2.5 to 7V
at V11-16< 1.5V or>9V
6
V
1
mA
0.1
60
kO
kO
7.5
1'5
Internal gating pulse
tp
Pulse duration
NOTES:
1. Permissible range 1 to 7V.
2. to = switch-off delay of line output stage.
3. Line flyback pulse duration tFP
= 12p.s.
4. Excluding external component tolerances.
5. Current source.
6. Emitter-follower.
7. Current source.
January 14, 19B7
9-45
•
Signetics
TDA2594
Horizontal Combination
Product Specification
Linear Products
DESCRIPTION
The TDA2594 is a monolithic integrated
circuit intended for use in color television
receivers.
FEATURES
• Horizontal oscillator based on
the threshold switching principle
• Phase comparison between sync
pulse and oscillator voltage ("oj)
• Internal key pulse for phase
detector (,,01) (additional noise
limiting)
• Phase comparison between line
flyback pulse and oscillator
voltage (,,02)
• Larger catching range obtained
by coincidence detector (,,03
between sync and key pulse)
• Switch for changing the filter
characteristic and the gate circuit
(VCR operation)
• Sync separator
• Noise separator
• Vertical sync separator and
output stage
• Color burst keying and line
flyback blanking pulse generator
and clamp circuit for vertical
blanking
• Phase shifter for the output
pulse
• Output pulse duration for
transistor reflection systems
• External switching off of the line
trigger pulse
• Output stage with separate
supply voltage
• Low supply voltage protection
• Transmitter identification and
muting circuit, and vertical sync
switch-off
PIN CONFIGURATION
N Package
Vee
1
GROUND
LINE TRIGGER
17 OSCILLATOR
PULSE IN
LINE DRIVE
PULSE
PULSE
our
15 PHASE COMP 1
swrrCH~OFF
S~I~~~
5
FLYBACK
PULSE
BLANKING
14
~=ig~ST
13
:~~~~T~IN
PULSE
YERTp~~~
8
MUTE OUTPUT
9
TOP VIEW
APPLICATIONS
• Video processing
• Television receivers
• Video monitors
• Sync separator
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
18-Pin Plastic DIP (80T-10208)
- 20·C to + 70·C
TOA2594N
February 12, 1987
9-46
853-1180 87585
Signetics Linear Products
Product Specification
TDA2594
Horizontal Combination
BLOCK DIAGRAM
LOW: NO
TV TRA/NSMITTER FLy~I!~
PULSE
VERTICAL
p~I:~ ..n:~~V
Ys
h
3mA
BURSTKEYI
>11V BLANKING
}
_4.5V PULSE
-~v
TO LINE
A~~E
,.
FLYBACK
PULSE
(15)
;uUNE TRIGGER PULSE
•
OUTPUT STAGE
TDA2594
,.
.f,l
I
.~
, v1'1"1.5k-=- ADJ.'
Vl0~ol-n-F""""'=~-.JY"""-t---':'
1>Ok
10nF
(3V)-
L-.....f::
Rose
OR
ro Vs
f
680nF
~'00PF
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
V'_'8=Vs
V2- 1 8
Supply voltage
at Pin 1 (voltage source)
at Pin 2
V4-'8
V9-'8
-V9-,8
±V11_'8
±V'2-'8
V'3-'8
12M, -13M
14
±Is
-17
19
113
Voltages
Pin 4
Pin 9
Pin 11
Pin 12
Pin 13
Currents
Pins 2 and 3 (transistor driving)
(peak value)
Pin 4
Pin 6
Pin 7
Pin 9
Pin 13
RATING
UNIT
13.2
18
V
V
13.2
18
0.5
13.2
V
V
V
V
V
V
400
mA
1
10
5
10
2
mA
mA
mA
mA
mA
6
6
PTOT
Total power dissipation
800
mW
TSTG
Storage temperature range
-25 to +125
·C
TA
Operating ambient temperature range
-20 to +70
·C
February 12, 1987
9-47
•
Signeties Linear Products
Product Specification
TDA2594
Horizontal Combination
DC AND AC ELECTRICAL CHARACTERISTICS at
V l _ 18=12V; TA =
25°C; measured in Block Diagram.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
Sync separator (Pin 11)
Vll-1B
Input switching voltage
111
Input keying current
111
Input leakage current at V11-18
111
Input switching current
111
Switch off current
V 11 - 1B(P.P)
Input signal (peak-to-peak value)
0.8
= -5V
100
V
100
5
1
p.A
5
p.A
150
3
p.A
p.A
4
Vl
100
p.A
1
p.A
4
Vl
7
V
Noise separator (Pin 12)
V12-1B
Input switching voltage
112
Input keying current
112
Input switching current
112
Input leakage current at V 12 -lB
V12 -18(P·P)
Input signal (peak-to-peak value)
V 12 - 1B(P.P)
Permissible superimposed noise signal (peak-to-peak value)
1.4
5
100
V
150
= -5V
3
I1A
Line flyback pulse (Pin 6)
Is
Input current
VS-18
Input switching voltage
VS-18
Input limiting voltage
0.02
mA
1
1.4
V
-0.7
+1.4
V
0
2.5
9 to Vs
V
V
200
2
p.A
mA
Switching on VCR (Pin 13)
V13-18
Input voltage
-1 13
or. 113
Input current
Pulse switching off (Pin 4) For t
V4-18
Input voltage
14
Input current
= 0;
input Pin 4 open or V3-18
=0
5.4
6.6
0
V
p.A
Vertical sync pulse (Pin 8) (positive-going)
V8-18(P-P)
Output voltage (peak-to-peak value)
R8
Output resistance
ioN
Delay between leading edge of input and output signal
IoFF
Delay between trailing edge of input and output signal
Vl0-18
Switching off the vertical sync pulse
10
11
V
2
kn
15
I1s
tON
I1s
3
V
Burst key pulse (Pin 7) (positive-going)
V7-18
Output voltage
R7
Output resistance
10
= 7V
tp
Pulse duration; V 7 -18
t
Phase relation between middle of sync pulse at the input and
the leading edge of the burst key pulse; V7 -1 8 = 7V
17
Output trailing edge current
V7-18
Saturation voltage during line scan
February 12, 1987
9-48
11
V
70
n
3.7
4
4.3
I1S
2.15
2.65
3.15
I1S
2
2
mA
1
V
Product Specification
Signetics Linear Products
TDA2594
Horizontal Combination
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) at V1-1B = 12V; TA = 25°C; measured in Block Diagram.
LIMITS
UNIT
PARAMETER
SYMBOL
Min
Typ
Max
Line flyback-blanking pulse (Pin 7) (positive-going)
4.9
4.1
V7-1B
Output voltage
R7
Output resistance
17
Output trailing edge current
V
70
n
2
mA
Field flyback/blanklng pulse (Pin 7)
V7-1B
Output voltage with externally forced in current
17 = 2.4 to 3.6mA
R7
Output resistance at 17
3
2
= 3mA
V
n
70
TV transmitter identification output (Pin 9) (open-collector)
V9 _ 1B
Output voltage at Ig
Rg
Output resistance at Ig
Ig
Output current at V10 - 18;;> 3V; TV transmitter identified
= 3mA; no TV transmitter
= 3mA; no TV transmitter
0.5
V
100
n
5
pA
TV transmitter identification (Pin 10)
When receiving a TV signal, the voltage V10- 18 will change
from<1V to;;>7V
Line drive pulse (positive-going)
V3- 18(P-P)
Output voltage (peak-to-peak value)
10
V
R3
Output resistance
for leading edge of line pulse
for trailing edge of line pulse
2.5
20
n
n
tp
Pulse duration (transistor driving)
V4- 18 = 0 to 3.5V; -14 ;;>200pA; tFP
V1-18
Supply voltage for switching off the output pulse
14 + tD
= 12Jls
JlS2
4
V
2.6
JlS3
30
pAIJls
Overall phase relation
fl.t
Phase relation between middle of sync pulse
and the middle of the flyback pulse
The adjustment of the overall phase relation and consequently
the leading edge of the line drive pulse occurs automatically by
phase control
PULSE
CD
PR01C,l1ON
OUTPUT STAGE
FOR VERTICAL
PROTECTION
pos. lEVEL:
_ _ _ __.6
STAGE
BV
(OPEN-
NEG. LEVEL: 4V
COLlECTOR)
I-
•
CD
0,
.
VERT. SYNC
SEPARTOR
HORIZONTAL
SYNC
SEPARATOR
VERT. SYNC
PULSE
INTEGRATION
~~
GENERATION
OF COMPOSITE
SYNC SLICING
LEVEL
(50% OF SYNC)
~
5
K
~
~
I----
SUPPRESSION
c
N"
o
g
OJ
~
~
c
@-
M sJ~p~~~,I>N
GENERTION
(OPEN-
COLLECTOR)
~
0-
S"
o-+-
0"
HOR. PULSE
GENERATOR
'--
PHAS: SHFIT
<,
t--
J.-
COINCIDENCE
PULse
GENERATOR
r:_UL_S_E...J..I_.....,
KEYING
COMPENSATION
GE:~~~~ON
CO°,fTRbL
ERROR
(7.5}.'8)
BLACK LEVEL
DETERMINATION
•
VIDEO
AMPLIFIER
TV
TRANSMITTER
IDENTIFICATION
1-,
~I
TDA2595
...
VOLTAGE
FOLLOWER
(AS A FUNCTION
OF V13_S)
COINCIDENCE
DETECTOR
"
13
10
220nF
o
::J
~-
::J
HORIZONTAL
0p~T~~T
S.
...r:::::::;-t1i1!K ~ KEYING
.--
'---
I
LINE FLYBACK
CONTROL
<,
DRIVE
(OPEN-
OJ
o...
t
J
I--
CS-V)
HORIZONTAL
l>
en
«5'
3
OUTPUT STAGE
PHASE
DETECTOR
COLLECTOR)
n
GATE
(5-V}..K
GATE
COMPOSITE
SYNC SWITCH
r-;:::±
FOR
SUPPLY
VOLTAGE
SENSOR
~
:0
iii:
~
1
~
r
VERTICAL SYNC
f--+
I---
11 :"F
nPHASE
4 ____ MO"p~L~lS.Q ___
LOWfTlVE
OUTPUT STAGE
--'-
v
LOAD
SENSOR
SWITCH
(PIN 9)
f.--
--r-
ll~
THRESHOLD
SANDCASTlE
OUTPUT STAGE
FOR BURST
GATING Be
HORJVERT.
BLANKING
~
HORIZONTAL
_
MUTING
CIRCUIT
SYNC OR
COMPOSITE
SYNC
.... >O.5V
37
1
I.
_2.5V
MUTE
OUTtP~ .-29",
r1
---"",4.5V
~
I\)
"V
UHE FLVBACK
PULSE
::c
I~
COMPOSITE VIDEO
JDOF-t
\'OSC
1 n
ADJUSTMEN7
I'°°1?
t=----l
-=
-=
"
J
VCR SWITCH
17
4 7n
• ,
rROUND OR V,cl
V+
100'
17'
1
r
820
118
VV\
,..-------
-4.7"'
r
10nF
560nF
"U
o
680
D-
-I
~
01
-0
01
c
n.
~
~
ao
OJ
Signetics Linear Products
Product Specification
TDA2595
Horizontal Combination
ABSOLUTE MAXIMUM RATINGS
SYMBOL
DESCRIPTION
RATING
UNIT
13.2
V
V1;4;7 - 5
VS;13;1S-5
V11-5
Voltages at:
Pins 1, 4 and 7
Pins 8, 13 and 18
Pin 11 (range)
18
Vee
-0.5 to +6
V
V
V
11
±12M
14
±ISM
17
Is
Ig
±1 1s
Currents at:
Pin 1
Pin 2 (peak value)
Pin 4
Pin 6 (peak value)
Pin 7
Pin 8 (range)
Pin 9 (range)
Pin 18
10
10
100
6
10
-5 to + 1
-10 to +3
10
mA
mA
mA
mA
mA
mA
mA
mA
PTOT
Total power dissipation
800
mW
TSTG
Storage temperature range
-65 to +150
°C
TA
Operating ambient temperature range
-20 to +70
°C
V15 - 5 = Vcc
Supply voltage (Pin 15)
DC AND AC ELECTRICAL CHARACTERISTICS Vee = 12V; TA = 25°C, unless otherwise specified.
LIMITS
PARAMETER
SYMBOL
UNIT
Min
Typ
Max
1
3
Composite video Input and sync separator (Pin 11) (internal black level determination)
V11 -5(P-P)
Input signal (positive video;
standard signal; peak-to-peak value)
0.2
V11 - 5(P-P)
Sync pulse amplitude (independent of video content)
50
RG
Generator resistance
111
-111
-111
Input current during
Video
Sync pulse
Black level
V
mV
200
n
5
40
30
p.A
p.A
p.A
12
170
p.A
p.A
Composite sync generation (Pin 10) horizontal slicing level at 50% of the sync pulse amplitude
110
-110
Capacitor current during
Video
Sync pulse
Vertical sync pulse generation (Pin 9) slicing level at 25% (50% between black level and horizontal slicing level)
V9 _ 5
Output voltage
tp
Pulse duration
190
IlS
tD
Delay with respect to the vertical
sync pulse (leading edge)
45
IlS
November 14, 1986
10
V
Pulse-mode control
Output current for vertical sync pulse (dual integrated)
No current applied at Pin 9
Output current for horizontal and vertical sync pulse
(non-integrated separated signal)
Current applied via a resistor of
15kn from Vee to Pin 9
9-53
..
Product Specification
Signetics Linear Products
TDA2595
Horizontal Combination
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) Vcc = 12V; TA = 25°C, unless otherwise specified.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
r
Typ
Max
Horizontal oscillator (Pins 14 and 16)
kHz
fosc
Frequency; free-running
V14-S
Reference voltage for fose
6
V
afose/Ll.I14
Frequency control sensitivity
31
Hz/l.LA
afose
Adjustment range of circuit Figure 1
afose
Spread of frequency
afose/fose
aV1S-S/V1S-S
afose
TC
15.625
±10
%
5
Frequency dependency (excluding tolerance of external
components)
with supply voltage (Vee = 12V)
±0.05
-1 16
116
Capacitor current during:
Charging
Discharging
tR
tF
Sawtooth voltage timing (Pin 14)
Rise time
Fall time
%
10
± 10- 4
with supply voltage drop of 5V
with temperature
%
%
oc;-l
1024
313
I.LA
49
15
I.Ls
I.LS
!.LA
Horizontal output pulse (Pin 4)
V4-S
Output voltage Low at 14 = 30mA
tp
Pulse duration (High)
Vee
Supply voltage for switching off the output pulse (Pin 15)
0.5
V
29 ± 1.5
I.LS
4
V
Phase comparison ""1 (Pin 17)
3.55
V17-S
Control voltage range
117
Leakage current at V17-S
± 117
Control current for external time constant switch
± 117
Control current at V18-S = V1S-S
and V13 _ S <2V or V13_S>9.5V
± 117
Control current at V18-S
S"
afose
afose
Horizontal oscillator control
Control sensitivity
Catching and holding range
Spread of catching and holding range
= 3.55
= V1S-S
to 8.3V
1.8
and V13-S
= 2.9
=2
to 9.5V
I.LA
2.2
rnA
1.8
2
mA
2.2
6
Internal keying pulse at V13-S
V13-S
V13-S
Time constant switch
Slow time constant
Fast time constant
±V17-18
Impedance converter offset voltage (slow time constant)
R18 - S
Output resistance
Slow time constant
R18-S
Fast time constant
November 14, 1986
V
1
8
tp
118
2
8.3
to 9.5V
9.5
2
rnA
±680
±10
kHz/I.Ls
Hz
%
7.5
I.LS
2
9.5
V
V
3
mV
10
Q
1
I.LA
high
impedance
Leakage current
9-54
Signetics Linear Products
Product Specification
TDA2595
Horizontal Combination
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) vee = 12V; TA = 25°C, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
Coincidence detector <1'3 (Pin 13)
V13-5
V13 - 5
V13-5
Output voltage
without coincidence with composite video signal
without coincidence without composite video signal (noise)
With coincidence with composite video signal
113
-113
Output current
without coincidence with composite video signal
with coincidence with composite video signal
113
I13(av)
Switching current
at V13-5 = Vee-0.5V
at V13-5 = 0.5V (average value)
6
V
V
V
50
300
IlA
1
2
pA
100
tOO
pA
IlA
Phase comparison 2.15V
Ismax
Maximum output current at V6-5
< 3V
2.5
3
V
2.3
mA
3.3
mA
TV transmitter Identification (Pin 12)
V12 - 5
V12 - 5
Output voltage
no TV transmitter
TV transmitter identified
1
7
V
V
Mute output (Pin 7)
V7- 5
Output voltage at
R7-5
Output resistance at 17 = 3mA; no TV transmitter
17
Output leakage current at V12 _ 5 > 3V;
TV transmitter identified
17
= 3mA; no TV transmitter
0.5
V
100
.\1
5
p.A
Protection circuit (beam currentlEHT voltage protection) (Pin 8)
VS_5
No-load voltage for Is = 0 (operative condition)
6
V
VS-5
Threshold at positive-going voltage
8 ±0.8
V
VS-5
Threshold at negative-going voltage
4 ±OA
V
± Is
Current limiting for VS-5 = 1 to 8.5V
60
p.A
RS_5
Input resistance for VS-5 > 8.5V
3
k.\1
t.J
Response delay of threshold switch
10
I1S
Control output of line flyback pulse control (Pin 1)
Vl -5sat
Saturation voltage at standard operation;
11
Output leakage current in case of break in transmission
11
=3mA
0.5
V
5
p.A
NOTES:
1. Phase comparison between horizontal oscillator and the line flyback pulse. Generation of a phase-modulated (1
DET.
1
LOOP
FILTER
HOR
OSC
<1>3
L....o
DET.
OSCILLATOR vs SYNC
loss of sync
4>2
FLYBACK vs OSCILLATOR
storage time variations; video shift
.,
COINCIDENCE DETECTOR
fast/slow ¢1 loop switch
Figure 1
February 1987
HORIZONTAL
DRIVE
FAST/SLOW
V
1/>1
PHASE
SHIFT
9-57
<1>2
DET.
I-
Application Note
Signetics Linear Products
Features of the TDA2595 Synchronization Processor
,
TIMING REFERENCE
tfJ, DETECTOR CURRENT
I
--------~~:----~------------I
I----(:=::-;==:t\==;:-------.l=::::::j
4
,
4 - - -, VIDEO
~
IDENTIFICATION PULSE
I
._UR_S_T_K~__~_L_S_E___~~-2.:~,(:I·::::;4:-=-=-i::~L-------
_____
\
I
r-
I
I
¢2 TIMING REFERENCE
455 -/
~I--------------,
~~;'=======~11~==~==4!:,======~11~~~~~~=.~!R~~~R~A~CE~
~I
.
----iiI---_
I I - - '
(/>2 DETECTOR CURRENT
Figure 2. Timing Diagram
February 1987
9-58
-
AN158
Signetics Linear Products
Application Note
Features of the TDA2595 Synchronization Processor
SYNC SEPARATOR
Adaptive sync separator to slice H-sync at
50% and V-sync at 25% independent on
sync-amplitude. This is to insure immunity
against deteriorated sync impulses. The black
level is stored on a capacitor which is fed to
the positive video-signal (source impedance
200>2) into Pin 11. The slicing level is detected internally and stored in a capacitor at
Pin 12.
The internal vertical integrator has a delay of
451's and is of the double-slope type to avoid
jitter and to improve noise immunity.
VERTICAL/COMPOSITE SYNC
The output stage at Pin 9 delivers a positive
vertical pulse or a positive composite sync
signal if the current drain is higher than 3mA.
If no TV transmitter is detected, the output is
switched to ground. The source impedance is
low-ohmic.
15kHz VCO
The veo is a current controlled ramp oscillator with 491's rise time and 151's fall time. The
timing capacitor is connected to Pin 16; the
control current has to be fed into Pin 14.
to ground, ground is electrically disconnected
from Pin 17.
To achieve a small phase adjustment a small
current may be injected into Pin 3.
If the oscillator is locked in and Pin 13 not
connected to ground, Pin 18 switches to high
impedance and thus the loop filter to the
"long" time-constant.
The aim of having two different thresholds at
the flyback input is to determine the performance of the 1>2 loop, e.g., a straight vertical
center line, by the amplitude of the applied
flyback pulse without affecting the blanking
time.
By switching loop gain or loop time-constant,
the lock in condition of the oscillator is not
disturbed. This enables a fast search tuning
using the TV transmitter identification (mute)
as a search stop.
To increase noise immunity the phase detector is inhibited during horizontal retrace and
vertical retrace if the oscillator is locked in
and Pin 13 not connected to ground or V+.
COINCIDENCE DETECTOR rt>3
The coincidence circuit detects whether there
is coincidence between the H-sync pulse and
a 81'S impulse generated by the yeo. The
capacitor at Pin 13 is discharged continuously
by 81'S current pulses of 501lA. If there is
coincidence, the capacitor is additionally
charged by H-sync pulses of 3501lA.
If the voltage at Pin 13 exceeds 3V, the loop
gain is reduced and the loop time constant is
switched to the "long" value.
While adjusting fa, Pin 12 should be connected to ground.
If the voltage exceeds 4.5V, the phase detector 1>1 is gated to improve noise immunity.
The oscillator generates the following Signals
(see timing diagram Figure 2):
MUTE CIRCUIT
- timing reference for 1>1
- gating pulse for 1>1
- reference pulse for video identification
circuit and coincidence detector 1>3
- burst keying pulse
- time reference for 1>2
rt>1 PHASE CONTROL
The phase control 1>1 compares the 1>1 timing
reference of the veo with the center of the
H-sync signal and converts the time difference into a proportional current at Pin 17.
The external low-pass filter at Pin 17 determines the time constant and the catching and
tracking range of the yeo.
If Pin 18 is connected to the V +, the loop
gain is increased 4 times as long as the
oscillator is not locked in or Pin 13 is connected to ground or V+ (VeR switch).
If Pin 18 is connected as shown in the circuit
diagram, Pin 18 has the same voltage as Pin
17 as long as the oscillator is not locked in or
Pin 13 is connected to ground. Due to this the
"long" time constant connected from Pin 18
February 1987
AN158
The mute circuit detects whether there is
coincidence between the H-sync impulse and
a 81'S impulse generated by the yeo. The
capacitor at Pin 12 is discharged during syncpulses of 501lA and by 81'S current pulses of
501lA. If there is coincidence, the capacitor is
additionally charged by H-sync pulses of
4501lA.
If the voltage at Pin 12 exceeds 4V, mute is
released and the mute output at Pin 7 is
switched to high impedance. Although the
coincidence detector 1>3 and the mute circuit
act similarly, separate circuits have been
chosen. This is to gain in design flexibility as
far as the time constants are related and to
keep the mute function alive independently
on the VeR switch.
rt>2 PHASE CONTROL
The phase control 1>2 compares the center of
the positive flyback pulse at Pin 2 at a
threshold of 3V with the 1>2 timing reference.
The time difference is converted into a proportional current at Pin 3. Loop gain and timeconstant are influenced by the external components at Pin 3. The voltage at Pin 3 in turn
controls the phase shift.
9-59
SUPER SANDCASTLE
For burst keying and vertical and horizontal
blanking there is a 3 level pulse at Pin 6.
The burst keying part is driven from the veo
and is 41'S wide. Due to its small tolerances in
widths and phase it keys the burst very
exactly and is suitable as black level clamping
pulse.
The blanking part is derived from the line
flyback pulse at Pin 2 at a threshold of 0.2V. If
no flyback is applied to Pin 2, there will be
continuous blanking level superimposed by
the burst keying pulse.
The frame blanking part has to be fed in
externally as a 2mA current.
HORIZONTAL DRIVE
The H-drive output is an open-collector output at Pin 4. The output pulse has a constant
aspect ratio of 45.3% off and 54.7% on
dependent upon the line frequency. An internal guard logic insures that there will be high
level during flyback. The output is inhibited by
the protection circuit also if the supply voltage
is below 4V. In both cases the line flyback
vanishes and by this the spot suppressor is
activated.
SPOT SUPPRESSOR
The spot suppressor is an open collector
output at Pin 1. If no flyback impulses are
detected at Pin 2, the output switches to high
impedance and remains there as long as the
flyback pulses are missing even if the supply
voltage vanishes during that time.
PROTECTION CIRCUIT
The protection circuit is activated if the voltage at Pin 8 exceeds 8V or decreases below
4V. One of both thresholds may be used (as
indicated in Figures 4a and b) to have X-ray
protection or overcurrent protection.
If activated, the H-drive is inhibited by this and
the line flyback vanishes and in turn the spot
suppressor is activated.
The protection circuit is reset if the supply
voltage decreases below 4V, e.g., the set is
switched off.
II
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Signetics Linear Products
Application Note
Features of the TDA2595 Synchronization Processor
AN158
TOA25959-8----fI.~_ _......-.lJ"8V
I'"
~
INPUT X-RAY PROTECTION
a. Input X-ray Protection
v+
TOA2595o}'-8---I~tI~:I---""'-U';4V
b. Input Over Current Protection
Figure 4
II
February 1987
9-61
Signetics
TDA8432
Computer-Controlled Deflection
Processor for Video Displays
Objective Specification
Linear Products
PIN CONFIGURATION
DESCRIPTION
FEATURES
The TDA8432 is an 12 C bus-controlled
deflection processor (analog picture geometry processor) which contains the
control and drive functions of the deflection circuits in a computer-controlled TV
(CCTV) or monitor. This IC replaces all
picture geometry settings which are performed manually during manufacturing.
The alignment of 10 picture geometry
parameters for the vertical and horizontal deflection is accomplished by means
of a microcontroller via the 12C bus.
Furthermore, it eliminates the external
components needed for adjusting the
horizontal frequency and phase position,
vertical linearity, picture height, eastwest parabola, and picture width. The
east-west shaping circuit is also eliminated. Provisions have been incorporated
to make several sync processor
(TDA2579 and TDA2595) functions 12C
bus-controllable.
• 12C bus interface for all functions
• Input for vertical sync from sync
processor
• Vertical sawtooth generator with
frequency-independent amplitude
• Vertical output stage with
feedback input for driving a
vertical deflection amplifier
• East-west raster correction drive
output
• EHT modulation input, providing
optimum picture geometry
compensation for static and
dynamic EHT load variations
• 12C bus-controlled alignment of
10 deflection parameters
• Provisions for contrOlling a sync
processing IC which does not
have an 12C bus interface,
including:
- Two digital-to-analog converters
for alignment of the freerunning horizontal frequency
and horizontal phase position
- An I/O pin enabling computer
alignment of the free-running
horizontal frequency
- A speCial purpose 4-level
output for time constant
switching of the horizontal
phase-locked loop
- A special purpose 3-level input
for detection of the mute
function and the 50Hz/60Hz
state of the sync processor
• A switchable output (e_g_, for
contrOlling a video source
selector)
APPLICATIONS
• Video monitors
• Color TV receivers
February 1987
9-62
VBLANKOUT
3
IREFRES
4
VFBCAP
5
~WsV'~~
~A2s~
O:~~e~
_~
U.ADJU~
I~~~~
6
8 GND2
7
8
9
17
~~FFOR
16
:y,g't~
10
15
~BUS)
11
1
3l'tBUS)
lOP VIEW
Objective Specification
Signetics Linear Products
TDA8432
Computer-Controlled Deflection Processor for Video Displays
BLOCK DIAGRAM
OUT
110
10
Vee
IN
DACe
17
+12V
11
12
r---~---~~~13~~ GROUND
TEST
L _________J-i.:..:....-O
18
GROUND
12x
DAC
SCl o-_1.;.:5+---I~
14
SDA ....-1"'"6+-.....-1
Ao o--""'-t~
I'CBUS
19
>----+--. EWORIVE
GEOMETRY
CONTROL
22
23
20
>---t--VORIVE
21
EHT-COMP
VFEEOBACK
II
February 1987
9·63
Objective Specification
Signetics Linear Products
Computer-Controlled Deflection Processor for Video Displays
TDA8432
ABSOLUTE MAXIMUM RATINGS
SYMBOL
Vcc
RATING
UNIT
Supply voltage (Pin 17)
14
V
Switching voltage (Pin 5)
8
V
-10
mA
PARAMETER
Output currents of each pin to ground (Pins 11 and 12)
10
sec
-55 to + 150
°C
Operating temperature
-25 to 80
°C
TJ
Junction temperature
+150
°C
OJA
Thermal resistance
75
°C/W
Maximum short-circuit time outputs
TSTG
Storage temperature
TA
RECOMMENDED OPERATING CONDITIONS In application circuit Figure 1 at TA = 25°C and
Vcc
= 12V, unless otherwise
specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Vcc
Supply voltage (Pins 17 - 20, 10)
Icc
Supply current (Pin 17)
Typ
10
42
Max
13.2
V
55
mA
Switching voltage VHF (Pin 5)
0
1.5
V
Switching voltage hyperband
2
3.5
V
Switching voltage UHF (Pin 5)
4
5
V
0.2
mA
Switching current UHF (Pin 15)
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
VHF mixer including IF, measurement In circuit of Figure 1
fR
Frequency range: printed circuit board
50
300
MHz
9
10
12
dB
dB
dB
Noise Figure 1 (Pin 23) 50MHz
225MHz
300M Hz
7.5
9
10
Optimum source admittance (Pin 23) 50MHz
225MHz
300MHz
0.5
1.1
1.2
mmho
mmho
mmho
Input conductance (Pin 23) 50MHz
225M Hz
300M Hz
0.23
0.5
0.67
mmho
mmho
mmho
CIN
Input capacitance (Pin 23) 50MHz - 300MHz
VIN
Input voltage for 1% X mod in channel (Pin 23)
97
VIN
Input voltage for 10kHz pulling (in channel) (Pin 23)
100
108
Av
Voltage gain
22
24.5
= 2010g
(V11-121V23) (Pins 11-12, 23)
2
pF
100
dBILV
dB/N
27
dB
VHF mixer
Conversion transadmittance mixer = SC = 1151V23
(Pins 15, 16-23)
February 1987
= -1161V23
3.8
mmho
Output admittance mixer (Pins 15 - 16)
0.1
mmho
Output capacitance mixer (Pins 15 - 16)
2
pF
9-64
Objective Specification
Signetics Linear Products
TDA8432
Computer-Controlled Deflection Processor for Video Displays
DC ELECTRICAL CHARACTERISTICS (Continued)
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
VHF oscillator
fR
330
MHz
Shift VB = 10%; 70 to 330MHz
200
kHz
Drift T = 15"; 70 to 330MHz
250
kHz
Drift from 5 seconds to 15 minutes after switching on
200
kHz
470
MHz
10
10
dB
dB
Frequency range
70
Hyperband mixer Including IF (measured in circuit of Figure 12) (measurements with hybrid)
fR
Frequency range
300
Noise figure (Pins 21, 22) 300MHz
470MHz
8
8
Input reflection coefficient (Pins 21, 22) 300M Hz iS11i5
phase
470MHz iS11i
phase
Input available power Pav for 1% X-mod
in-channel (Pins 21, 22)
300M Hz
470MHz
10kHz pulling (in-channel) (Pins 21, 22) 470MHz
N + 5 -1 MHz pulling 3 (Pins 21, 22) 470MHz
Gain =
34
34
dB
deg
dB
deg
-19
-19
dBm
dBm
-11
-29
dBm
dBm
40
40
dB
dB
520
MHz
Shift AVB= 5%
400
kHz
Drift AT= 15"
500
kHz
Drift from 5 seconds to 15 minutes after switching on
600
kHz
4
300M Hz
470MHz
-4.4
+162
-4.7
+ 151
37
37
Hyperband oscillator
Frequency range (MHz)
330
Input reflection coefficient (Pins 4 - 5) iS11i
at f = 330MHz
phase
TBD
TBD
dB
deg
UHF mixer including IF (Pins 18 and 19) (measured in circuit of Figure 12) (measurements with hybrid)
Frequency range
Noise figure
Input reflection coefficient
Input available power PAV for
1% X-mod in-channel
10kHz pulling (in-channel)
N + 5 -1MHz pulling 3
Gain =
February 1987
4
470
470MHz
860M Hz
8
9
860
MHz
10
11
dB
dB
-4
+157
-4.2
+138
470MHz iS11i
phase
860M Hz
phase
470MHz
860MHz
9-65
deg
-19
-19
dBm
dBm
-42
-10
-35
dBm
dBm
34
34
37
37
470MHz
860MHz
860MHz
820MHz
deg
40
40
dB
dB
•
Objective Specification
Signetics Linear Products
TDA8432
Computer-Controlled Deflection Processor for Video Displays
DC ELECTRICAL CHARACTERISTICS (Continued)
LIMITS
UNIT
PARAMETER
SYMBOL
Min
Typ
Max
UHF oscillator
900
MHz
Shift Ll.Vs= 5%
400
kHz
Drift LI.T = 25'C to 40'C
500
kHz
Drift from 5 seconds to 15 minutes after switching on
300
kHz
Frequency range (MHz)
fR
500
IF amplifier
'n)
Ml
.
.
measured at 36M Hz, differentially
S12
S22
Mod
Phase
-0.5
12
-1
160
dB/deg
dB/deg
-41
-7.9
-5.2
13.7
dB/deg
dB/deg
37
100
LO output (Pin 2)
Output voltage into 75Q
Output reflection coefficient
f ';;330MHz
14
(VHF position) S22
(Hyperband and UHF) at 500MHz
TBD
TBD
Spurious Signal on LO output wrt· LO output signal, measured in
75Q with RF signal level at Pin 24 1V .;; 225M Hz
0.3V 225MHz - 300M Hz
-10
dB
Harmonics of LO signal wrt LO signal, measured in 75Q
-10
dB
NOTES:
1.
2.
3.
4.
5.
6.
The Pins 2, 5, 11, 12, 13, 14 withstand the ESD test.
Measured with an input circuit for optimum noise figurs.
The values have been corrected for hybrid and cable losses. The symmetrical output impendance of the hybrid is 1DOn.
The input level of an N + 5 -1 MHz signal which is just visible (Amtsblatt 69).
The gain is defined as the transducer gain measured in Figure 1 + the voltage transformation ratio of L6-L7. The ratio is 6:1 (16dB).
All S parameters are referred to a 50.11 system.
C3
I~
T
NOTES:
Component values: F = 50MHz
F>= 225MHz
F.,. 300MHz
L1~L2~
C1 =
C2=
C3 ~
RM""
Electrical parameters of the circuit are (for appropriate impedance and selectivity)
Insertion loss
VSWR without IC
VSWR with IC
Impedance of tuned circuit without
IC at VSWR = 1
Image suppression
Output impedance (source for IC)
Figure 1
February 1987
mV
dB/deg
dB/deg
9-66
Signetics
Section 10
C%r Decoding and Encoding
Linear Products
AN155A
TDA3505
TDA3563
AN156
TDA3564
TDA3566
TDA3567
TDA4555f56
AN1551
TDA4565
TDA4570
TDA4580
TDA8442
TDA8443f
8443A
TEA2000
AN1561
INDEX
Multi-Standard Color Decoder With Picture Improvement............. 10-3
Chroma Control Circuit........................................................ 10-11
NTSC Decoder With RGB Inputs ........................................... 10-18
Application of the NTSC Decoder: TDA3563 ............................ 10-25
NTSC Decoder.................................................................. 10-38
PAL/NTSC Decoder With RGB Inputs .................................... 10-47
NTSC Color Decoder.......................................................... 10-60
Multi-standard Color Decoder................................................ 10-67
Single-Chip Multi-standard Color Decoder TDA4555/4556............ 10-73
Color Transient Improvement Circuit (CTI)................................ 10-82
NTSC Color Difference Decoder............................................ 10-86
Video Control Combination Circuit With Automatic
Cut-Off Control.................................................................. 10-91
Quad DAC With 12 C Interface ............................................... 10-1 01
RGB/YUV Switch ............................................................... 10-1 07
NTSC/PAL Color Encoder .................................................... 10-116
Applications of the TEA2000 Digital RGB Color Encoder ............ 10-121
•
Signetics
AN155A
Multi-Standard Color Decoder
With Picture Improvement
Application Note
Linear Products
The decoder concept presented here comprises a multi-standard color decoder and a
video combination. The concept can also be
extended by means of a picture improvement
circuit.
A brief overview will first be given to clarify
this arrangement. Figure 1 shows the block
diagram of a complete color decoder from the
CVBS interface up to the picture tube. There
are switchable filters for separation of the
luminance and chrominance signals from one
another. Only one IC is necessary for the
demodulation of four color standards.
The output signals are the standard-independent color difference signals (B-Y) and (R-Y),
i.e., U and V. The baseband signals (i.e., color
difference signals and luminance signal Y)
can either be directly supplied to the video
combination or they can be supplied via a
signal processor IC as shown here.
The video combination comprises all functions for advanced video signal processing.
The RGB output signals of the IC can be fed
to the video final stages directly.
The interface selected in this decoder concept, with the baseband signals as input
signals of the video combination, also permits
new circuit concepts to be introduced; e.g.,
the delay line which is required for PAL and
SECAM can be realized with CCD lines.
Picture improvement circuits with picture
memories can also be added.
The single-chip multi-standard decoder
TDA45551TDA4556 is examined fully in
AN1551. Please refer to AN1551 for application information.
The Color Transient Improvement (CTI) IC
which is incorporated in Figure 1 was also
developed for this interface. Two functions
are integrated in this circuit: a transient improvement for a better picture, and a Y delay
line in gyrator technique to replace the previously-required wound line.
The Video Combination
IC-TDA3505
In the past, multi-standard color decoders
(MSD) have been built up with a number of
integrated circuits. Parallel working concepts
are known, and also transcoder concepts
speCially for PAL and SECAM. The decoders
of the various standards require circuit blocks
of the same type; this applies in particular to
the quadrature amplitude modulation standards (QAM standards) PAL and NTSC, but
also to a large extent to the FM standard
SECAM. Therefore, an obvious approach for
the integration of a multi-standard decoder on
one chip is to make use of as many circuit
blocks as possible in common for the different standards in order to minimize the components and, also, the crystal area required.
Under the condition of automatic standard
identification, as is already the state of the art
for present MSD concepts, mUltiple utilization
of the circuit blocks can only be realized if
automatic standard identification is effected
by sequential standard scanning. A system of
this kind gives the great advantage that the
entire decoder, including the filters, can be
designed in the optimum way for the individual standards.
The video combination IC incorporates all
setting functions for color picture reproduction. A black current stabilizing circuit is
provided. This saves three tuning operations
and also automatically regulates operatingpoint changes due to warming up after
switch-on and to aging.
RGB signal inputs are provided for signal
supply from RGB sources via the audiolvideo
plug, e.g., from cameras or from internal
teletext decoders.
Figure 2 shows the block diagram of the input
part of this IC. The two color difference
signals -(R-Y) and -(B-Y) are fed in via
capacitors and clamped in the input stages to
reference values. After the saturation control
stages, the - (G-Y) signal is generated with
the (G-Y) matrix. These color difference signals, together with the Y-signal which is also
clamped in the input stage, are converted to
the R, G, and B signals in the R, G, and B
matrix.
EXTERNAL AGD - SIGNALS
SWITCHING
VOLTAGE
SWITCHING VOLTAGES
cvas
.......A--..
R
G
B
C:~c
AND
C...OMATRAPS
PAL
NTSC
CONTRAST
BRIGHTNESS
BD01191S
Figure 1_ Block Diagram of the Multi-5tandard Color Decoder
February 1987
10-3
..
Signetics Linear Products
Application Note
AN 155A
Multi-Standard Color Decoder With Picture Improvement
RGB-iNPUT SIGNALS
1Vpp
-{B-Y)1I
-11-++--"--++'"
1.33Vpp
v....GNAL
15
-I'~"'-~~--~------~
v'V
OASYpp
1.
11
2-4.3V
SWITCHING
SATURATION
VOLTAGE
25
2_~V
CONTRAST
1~3V
_~
BRIGHTNESS SANDCASTLE
CONTR. VOLT CONTROL
OUTPUT FOR
VOLTAGE
CONTR.YOLT
PULSE
PEAK&EAM
CURAENTLlMmNG
800126.2$
Figure 2. Front Part of the Video Combination TDA3505
Switching stages. together with a switching
matrix and a driver stage for the switching,
permit the choice between the picture signals
from the color difference and Y inputs, or
from the R, G, B inputs. When the R, G, B
signals from the R, G, B inputs are selected,
they are added to the black levels, which are
simultaneously Inserted. The switching times
between blanking, insertion, and changeover
are about SOns and are so small that there
are no visible errors in the picture. If the RGB
inputs are constantly connected, synchronization with the other signals is not necessary.
The signals also pass through the contrastand brightness-control stages. A peak beam
current limitation can be effected via an input
to a threshold level switching circuit. The
threshold level circuit then reduces the contrast-control voltage. Average beam current
limitation is effected directly via the contrastcontrol voltage, whereby under certain circumstances the brightness control Is also
reduced via an internal diode.
All the pulses required in the IC, and especially for the black current stabilization which will
be explained later, are derived from the
sandcastle pulse.
Signal processing is effected in parallel in
three R, G, B channels and, therefore, the
description and explanation will continue to
be limited to the R channel.
Figure 3 shows the functional block diagram
of the black current stabilizer. The R signal is
blanked out and a measuring pulse is inserted
February 1987
for the black current measurement. A subsequent limiter stage prevents overdriving of the
video final stages. A control stage is provided
for white-point adjustment, which can be
effected by means of a DC setting voltage.
There is an adding stage in which the voltage
from the black current stabilization circuit is
added to the R signal. The output stage of the
IC can feed the video final stage directly. Its
output voltage is supplied via a PNP measuring transistor to the cathode of the CRT. The
collector circuit includes a measuring resistor
at which voltage drops occur at the respec·
tive sequential measuring times; these are
due on the one hand to any leakage currents
which occur and on the other hand to dark
current with leakage currents. These voltages
are given to the IC. Following a buffer stage,
the measurement voltage for the leakage
currents is stored on the capacitor CL. Switch
SL is only closed at the time when the signal
is blanked and. no signal current can flow.
During the black level measurement time, a
reference voltage of O.SV is subtracted from
the voltage to be measured and then compared in a comparator circuit with the stored
voltage for the leakage currents. Switch Sd is
only closed during the black measurement
time and closes the control loop. Capacitor
Cd stores the control voltage.
A dark current of 10JJA is not too small for
reliable evaluation and not too big, so that if it
is in the right time position no disturbing
effects are visible on the screen.
10-4
Insertion of the measurement pulses and
their evaluation is sequential; this means that
from the measuring resistor through the measurement input and leakage current storage
up to and including the comparator circuit,
these circuits only have to be realized once
and are used for all three channels.
Figure 4 shows the time positions of the
various measurement pulse insertions and
evaluations. The measurement pulses are
after the vertical flyback pulse and are thus
above the upper picture edge in the overscan.
The R, G, B signals are blanked up to the
inserted measurement pulses. The leakage
current of all channels is measured in the line
before the first measurement pulse. This is
followed by the measurement pulses and
their evaluation in the sequence red, green,
blue.
A comprehensive application diagram with
the video combination TDA3S0S and the
video final stages is shown in Figure S.
For two sets of external RG B inputs and
larger video input bandwidth, the TDA4S80
can be used In place of the TDA3S0S (see
Figure 6).
The Color Transient
Improvement IC - TDA4565
A complete multi-standard decoder can be
built with the two ICs described above. A third
IC, which can be interconnected in the color
difference interface, can be used for color
Application Note
Signetics Linear Products
Multi-Standard Color Decoder With Picture Improvement
AN155A
G
j
MEASURING
RESISTOR
(ONLVONE)
Im:::1k+ll
MEASURING INPUT
(ONLY ONE FOR THE THREE CHANNELS)
R-OUTPUT
28
A-SIGNAL
FROM THE
FRONT PART
OF THE TDA 3S05
28
Z7
O_12V
r
WHITE POINT
CONTR.VOLT
_
-
vL
Cd
STORAGE CAPACITOR
FOR DARK CURRENT
"R" CHANNEL
II
CL
STORAGE CAPACITOR
FOR THE LEAKAGE CURRENT
"':" (ONLV ONE FOR THE THREE CHANNELS)
Figure 3. Functional Block Diagram for the Dark Current Stabilization With the Video Combination TDA3505 (R-channel)
3
A
AI A A
~I
:~I
A
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
YIDEOSIGNAL
WITH VERTICAL
BLANKING PERIOD
A A A A A A A A A A A A A A A A A
____
O-~
--1
=DBA=='~D=F~n~NIT~0~F~M=~==U~R~IN=G~P~U=~='=S(=20~L=IN='=S)~_____
r;----~:~
Ma
____
J 1 .---In.
. - . M.
III
~~&:Q PU}L:::::
GREEN
BLUE
I,
:1
:,
_. . . __~II~I;;;;;;=-;;;=-;=-;=-;=-;;;;~;;;;;;;;=-;;;_-~_-~~~~~_-~:::-!______
-----1:1'11------------.. . .
;.
•i
22 UNES
VERTICALBLANKING
PULSE
(FROM VERTICAL Ie)
UNES _____________!------------VERTICALFLYBACKPEAIOD
Figure 4. Position of the Measuring Lines of the Video Combination TDA3505
The Color Transient
Improvement IC - TDA4565
A complete multi-standard decoder can be
built with the two ICs described above. A third
IC, which can be interconnected in the color
difference interface, can be used for color
picture improvements by means of transient
improvement of the color difference signals.
In Figure 7, the signal characteristics a) and
b) show a transient in the Y and color
difference signal. The rise time of the color
February 1987
difference signal is longer, corresponding to
the smaller bandwidth. A delay line in the Y
channel coordinates the centers of the transients as shown in Figure 7c.
7d. It is now clear that - as shown in Figure
7e - a correspondingly longer delay is necessary for the Y signal in order to achieve
coincidence of the transients.
In deviation from the previous signal processing, with the Color Transient Improvement IC,
the color difference transient does Dot occur
until the input signal transient is finished, but
then occurs with a steepness corresponding
to that of the Y signal. The characteristic of
this color difference signal is shown in Figure
Color signal transmiSSions, especially of test
pictures coming via this CTI circuit, appear on
the screen with the same color definition as
RGB transmissions.
10-5
Figure 8 gives an explanation of the CTI
function: the simplified circuits are shown on
the left and the signals occurring at these are
•
Application Note
Signetics Linear Products
Multi-Standard Color Decoder With Picture Improvement
AN155A
SIGNALS TO CATHODES OF CRT
-11---------
-0 - - -
--------'ii""--
RC!
1.8K
I
I
r-J
I
II
I
I
~-I
I
I
I PEAK
BEAM
CURRENT
ILIMmNG
330nF
..c-l
4
c•
I
';"RQ2
5 Bo
180
I
22,F
22,H
Vp-12V I
SANDCASlU!-
I
5 +Up
VPI-200V
1
~
~
r
I
Wa 22
w.
I
I
21
H2O
PUl.SE
i
RGBot:
INPUTS GII---,--"''-=--j
A
II--~.LL...:'---l
_IR_Y)I"'I,,"7_ _-t___+~~r'-=",--j
Fa 18
y 15
I
OAOUNOh
I
I
I
~
8.21<;
10K
3.91(
C,
L__________ ..:..-_ J
22,F
R,
I AVERAGE
BEAM
I
_______ .J
:::t.r::I~':i
Figure 5. Application Diagram for the Video Combination TDA3505 and the Video Final Stages
February 1967
10-6
Application Note
Signetics Linear Products
Multi-Standard Color Decoder With Picture Improvement
AN155A
RGB - SIGNAL INPUTS
1--"
" ---1
G---j
B ---1
SWITCHING VOLTAGES
f--G
I--B
FSW2
FSW1
VIOEO
FINAL STAGES
eves
SWITCHABLE
CHROMA FILTERS
C
AND
CHROMA mAPS
PAL
NTSC
CONTRAST
BRIGHTNESS
Figure 6. Multi-Standard Decoder Using the TDA4580
SIGNALS WITH FASTEST TRANSIENT
GIVEN BV THE STANOARD:
V-SIGNAL WITHOUT DELAV
CD-SIGNAL (NORMAL)
V-SIGNAL
WITH NORMAL DELAV TO ADAPT
THE MIDDLES OF THE TRANSIENTS
•
CD·SIGNAL
TRANSIENT IMPROVED
-+~----------~~
V·SIGNAL
WITH LONGER DELAV TO ADAPT
THE MIDDLES OF THE TRANSIENTS
:,.-- -- -- -- -.\...j.
800ns ---1-.."
,(
0.2
0.4
0.6
0.8
1.0
1.2
"s
Figure 7. Y-delay Time for CD Signals With and Without Transient Improvement
shown on the right. Part" A" shows a color
difference input signal with a fast positive
transient corresponding to the maximum
bandwidth of the color difference signal.
The subsequent negative signal characteristics are slower. In this circuit, the input signal
is supplied after an impedance transformer
via a switch and a further impedance transformer to the output. A storage capacitor is
connected between the switch and the output
impedance transformer, and is charged by
the input impedance transformer in accordance with the signal characteristic.
Processing of the switching signal is affected
by differentiation of the color difference signal, followed by full-wave rectification. Figure
February 1987
Bb shows the signals obtained in this way,
which are supplied to a comparator via a
high-pass filter. A diode at the high-pass filter
reduces the charge reversal time and, thus,
the dead time for generation of a switching
signal for transients following in rapid succession. A comparator with threshold voltage
generates a switching voltage as shown in
Figure Bd from the signal of Bc when the
threshold voltage is exceeded, and this triggers the switch. The switch is thus opened at
the beginning of a transient and the voltage is
maintained by the storage capacitor at the
time before the transient. After completion of
a fast transient, the switch is closed and the
capacitor's charge is changed in approximately 150ns to the voltage after the tran-
10-7
sient. The effect of a slower transient characteristic is shown in the second part of the
signal in Figure Bc. Only a small part is'
affected. For even slower characteristics, the
differential quotient is so small that the
threshold voltage is no longer exceeded and
there is no effect on the signal. Thus, for the
most part, only transients having a steepness
approaching the system limit are improved,
whereas slower signal characteristics remain
unchanged.
Figure 10 shows the entire block diagram with
external circuitry of the eTI Ie.
The lower eTI section affects signal processing for the two color difference signals in
parallel circuits, as already described. Only
Signetics Uneer Products
Application Note
Multi-Standard Color Decoder With Picture Improvement
one switching signal forming stage is incorporated, and this is triggered by the differentiating stage of the two channels. Thus, the
signal switches will always work in parallel, so
that transient improvement is also parallel in
the two channels.
The transient-improved color difference signals require a longer Y signal delay line with a
delay time of up to j OOOns, which is additionally realized in thislC in gyrator tec/lnique.
A selection capability has been incorporated
for the delay time, by means of a switching
I
STDRAGE
CAPACITOR
voltage, since the total required delay time is
dependent on the overall television receiver
concept. The delay line comprises a total of
11 gyrator all-pass elements with a delay time
of 90ns each, making a total of 990ns. The
group delay and frequency behavior of the
gyrator delay line is very good up to 5MHz.
A switching stage permits optional by-pass of
one, two, or three of these elements, so that
a minimum of B X 90ns = 720ns is effective.
The transient improvement of the color difference signal makes coincidence errors with
CD-OUTPUT
SIGNAL
TRANSIENT
IMPROVED
Figure 8_ Function of CTI
February 19B7
10-8
AN 155A
respect to the Y signal especially visible. A
slight increase in delay time by 45n8 has
therefore been provided for fine tuning, working via an IC pin to be connected to ground.
A signal tapping is available before the last
delay element for a further picture improvement capability by means of deflection modulation.
Figure 11 depicts the circuit diagram of the
TDA4565.
Signetics Linear Products
Application Note
Multi-Standard Color Decoder With Picture Improvement
AN155A
+12V
VI""
1.5-12V
........Y
'~Y
• ..:LIIY
- (R·Y)IN
,.....
.....
Td12117
.....
.....
715..
.
IF OPEN
UK
2'fo
COLOR TRANSIENT IMPROVEMENT
~~'--C>--~----~~~~~~~~--~~~-~~~
O.33pF
(I
'-----f:'-lDO~
'-----f.'-l,..~
STORAGE
CAPACITOR
NOTE:
• The TDA4565 is a high-performance TDA4560.
Figure 9. Block Diagram of Picture-Improvement Ie TDA4S6S*
February 1987
10-9
•
Signetics Linear Products
Application Note
Multi-Standard Color Decoder With Picture Improvement
V15f18
AN155A
112117
9.5.M12V 1035nl
6.5._8.5V 945ns
I 0
X -45n8
3.S•..S.SV 855ns
0_2.5 V
765 ns
I =CONNECTED
x= DISCONNECTED
YIN----o------------------------------------------------,
I
-(8-Y) IN ----
~
~
SATURATION
CONTROL
_ "'"
•
•
I~
MA~RIX
(B-y)
CONTRAST
CONTROL
r---t~
I-f+
B~~.:'::ci'LSSI-----BLUE
~~~~~~'~8~~C-U~M-PI-N-G~I~~::~~~~~~~'~=tI~y:=t1~~~:~:1~~~!;t~~;~::l>~~~ 1t-___L-_-_-t~ C-ui=M~p:IN~G=P=U~ E_
CUMPINLE£JPU~E
y~V)
t
V)g~~~~~~~'~5~~C~U~M~PI~NG~~______~----~
(O.45V~p)
J,.
~1Lr'
r-~I (t'\4.4V
'~I
DRIVER FOR
SIGNAL
~
r-
V10dB
.6
SATURATION
CONTROL VOLTAGE
(2T04.3V)
January 14. 1987
AMPLIFIER
1_
t
16
Vee
(+12V)
_
-
SWITCHES
t
~4
6"
INPUT FOR SIGNAL
SWITCHING VOLTAGE
~
I
THRESHOLD
DETECTOR
CURRENT
SOURCE
__
I'
,-<"-------~--+tI~-4
t
••
625
CONTROL INPUT
FOR PEAK BEAM
CURRENT LIMITING
CONTRAST
CONTROL
VOLTAGE
(2
10-12
TO 4.3V)
20
BRIGHTNESS
CONTROL
VOLTAGE
~T03V)
Signeties linear Products
Product Specification
TDA3505
Chroma Control Circuit
BLOCK DIAGRAM (PART B)
WHITE POINT ADJUSTMENT
r:;b. ~
(0 TO 12V)
23
RED _
BLANKING
__
INSERTION
OF BLACK
CURRENT
MEASURING
r-----.
FORCUT.QFF
2T4 CONTROL
21
L
.J
L-,
CONTR. •
AMPLIFIER
~ STORAGE CAPACITORS
...L-=-..L-=...1..-=
22
1...J
RED
':.M
PULSE
GREEN - - .
BLANKING
-.
-
CONTR.
AMPLIFIER
INSERTION
~~:~~ r-'"
MEASURING
BLUE -
BLANKING
i-
M~~~~JG
PULSE
-
V~'
CONVERTER
H+V
'. AT.
r+ Jtt
CONTROL E
~~_~
51-1
t t
~ HI-____" ~: :.: ;.:23: ~"'(1)(~'!IL
-'Mf:
CLAMPING
PULSE
GREEN
COMPARATOR
~
Jl
-
CONTR.
AMPLIFIER
INSERTION
OF BLACK
STAGE
c'~'J-I--w-~l
PULSE
t
g~:~~OlLED
+
+
ii
* i
COMPXATOR CONTRJLCURRENT
LlNE24(1)
CONVERTER
(3x)
R
-=
+
COU:rER
SANDCASTlE
SlHINotAND I
LINES 21 TO 24(1)
L_D_ET_EtC_TO_R.J--':'HI[:!~~F~~~~;;~:~R~===~LI~NE~21~(~~[:!!:~I=C:LA~M~P:'N:G=:!J
I
I ~
±
t
SANDCASTtE
PULSE
CLAMPING
I
JL
J
OF VERTICAL
n-__ 4.5V
BLANKING PULSE
'"\;-"L;Q 2.5V
r- -=
SYMBOL
24
PARAMETER
Supply voltage
V26 - 24
V25 - 24
V1O-24
V11 -24
V16, 19, 20-24
V21 , 22, 23-24
No external
DC voltage
Voltages with respect to Pin 24
Pin 26
Pin 25
Pin 10
Pin 11
Pins 16, 19, 20
Pins 21, 22, 23
Pins 1, 3, 5; 2, 4, 28; 7, 8, 9;
12, 13, 14; 15, 17, 18; 27
-1 1,3,5
119
120
-1 25
Currents
Pins 1, 3, 5
Pin 19
Pin 20
Pin 25
RATING
UNIT
13.2
V
Vee
Vee
Vee
-0.5 to 3
0.5 Vee
Vee
V
V
V
V
V
V
3
10
5
5
rnA
rnA
rnA
rnA
PTOT
Total power dissipation
1.7
W
TSTG
Storage temperature range
-65 to + 150
'C
TA
Operating ambient temperature range
-20 to +70
'C
January 14, 1987
~ciL~~~~ERIVED
FROM LEAKAGE
CURRENT OF RLOAD
~~~;~JT~F
26
(ROAGORB)
-=
CURRENT" INFORMATION
ABSOLUTE MAXIMUM RATINGS
Vee = V6 -
~
B
~7 SlORAGEOF"LEAKAGE
(1) AFTER START
b!O __ 8V
..J •• r
CIRCUIT
PULSE
G
10-13
•
Signetics Uneer Products
Product Specification
TDA3505
Chroma Control Circuit
DC ELECTRICAL CHARACTERISTICS The following characteristics are measured in a circuit similar to Figure 1;
Vee = 12V; TA = 25°C; VI8-24(P-P) -1_33V; VI7-24(P-P) = 1_05V; VI5-24(P-P) = 0.45V;
VI2,13,14-24(P-P) = 1V. unless otherwise specified_
LIMITS
SYMBO~
UNIT
PARAMETER
Min
Vcc = VS -24
Supply voltage range
18= lee
Supply current
Typ
Max
13_2
10_8
V
85
mA
V
Color difference Inputs
VI8-24(P-P)
-(B-Y) input signal at Pin 18 (peak-to-peak value)
1-33
V 17 - 24(P-P)
-(A-Y) input signal at Pin 17 (peak-to-peak value)
1-05
117,18
Input current during scanning
A17, 18-24
Input resistance
V17, 18-24
VI6-24
V18-24
VI6-24
116
V
1
k,Q
100
4_2
Internal DC voltage due to clamping
Saturation control at Pin 16
control voltage range for a change of
saturation from - 20dB to + 6dS
control voltage for attenuation > 40dB
nominal saturation (6dB below maximum)
input current
pA
2.1
V
4_3
V
1-8
V
V
pA
3_1
20
(G-Y) matrix
V(G-V) - -0_51 V(R-V)
-0_19 V(B-V)
Matrixed according to the equation
Luminance amplifier (Pin 15)
V15 - 24(P-P)
Composite video input signal (peak-to-peak value)
A15-24
Input resistance
V15-24
Internal DC voltage
115
Input current during scanning
0.45
V
k,Q
100
2_7
V
1
pA
0_9
3
0.4
V
V
-100
+200
pA
1
1
V
V
pA
4_3
V
2
V
V
pA
RGB channels
VII-24
VII-24
Signal switching input voltage for insertion (Pin 11)
on level
off level
111
Input current
V12, 13, 14-24(P-P)
V12, 13, 14-24
112,13,14
Signal insertion (Pin 12: blue; Pin 13: green; Pin 14: red)
external AGB input signal (black-to-white values)
internal DC voltage due to clamping2
Input current during scanning
VI9-24
V19-24
V19-24
119
January 14. 1987
Contrast control (Pin 19)
control voltage range for a change of
contrast from -18dB to +3dB
nominal contrast (3dB below maximum)
control voltage for -6dB
Input current at V25-24 ~6V
10-14
4.4
2
3_6
2_8
Signetics Linear Products
Product Specification
Chroma Control Circuit
TDA3505
DC ELECTRICAL CHARACTERISTICS (Continued) The following characteristics are measured in a circuit similar to
Figure 1: Vce = 12V: TA = 25'C: V,8 - 24(P.P) = 1.33V:
V17 - 24(P.P) = 1.05V: V,5 - 24(P.P) = 0.45V: V,2.13,,4-24(P.P) = 1V, unless
otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
V25 - 24
R25-24
1'9
V2O.24
-120
V2O .24
e.V2O - 24
Peak beam current limiting (Pin 25)
internal DC bias voltage
input resistance
input current at contrast control input
at V25-24 = 5.1V
Brightness control (Pin 20)
control voltage range
input current
control voltage for nominal black level which
equals the inserted artificial black level
change of black level in the control range
related to the nominal luminance signal (black-white)
Typ
Max
5.5
10
V
kQ
17
1
mA
3
V
10
2
p.A
V
50
%
-25
120
%
%
AC voltage gain 3
at V21 , 22, 23-24 = S.SV
at V21 , 22, 23-24=OV
at V21 , 22, 23-24 = 12V
100
60
140
%
%
%
Input resistance
20
kQ
Internal signal limiting
signal limiting for nominal luminance
(black to white = 100%)
black
white
White point adjustment (Pin 21: blue; Pin 22: green; Pin 23: red)
R21, 22, 23 -24
Emitter-follower outputs (Pin 1: red; Pin 3: green; Pin 5: blue)
At nominal contrast, saturation, and white point adiustment
V
V
"
"
3, 5-24(P·P)
Output voltage (black-to·white signal, positive)
3, 5-24
Black level without automatic cut-off control
(V28, 2, 4-24 = 10V)
ISOURCE
Internal current source
Cut-off current control range
3, 5-24
"
Automatic cut-off control (Pin 26)
-e.V
2
V
6.7
V
3
rnA
4.6
V
The measurement occurs in the following lines after start of the vertical blanking pulse:
line 21: measurement of leakage current
line 22: measurement of red cut-off current
line 23: measurement of green cut-off current
line 24: measurement of blue cut-off current
V26-24
e.V26 _ 24
January 14, 1987
Input voltage range
+6.5
0
Voltage difference between cut-off current
measurement and leakage current4
measurementS
Input 26 switches to ground during horizontal flyback
10-15
0.7
V
V
•
Signetics Linear Products
Product Specification
Chroma Control Circuit
TDA3505
DC ELECTRICAL CHARACTERISTICS (Continued) The following characteristics are measured in a circuit similar to
Figure 1; Vee = 12V; TA = 2SOC; VI8 - 24(P.P) = 1.33V;
V17-24(P.P) = 1.0SV; VI5-24(P.P) = O.4SV; VI2,13,14-24(P.P) = tV, unless
otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
Gain data
At nominal contrast, saturation, and white point adjustment
Gl, 3, 5-15
Voltage gain with respect to V·input (Pin IS)
dl, 3, 5-15
Frequency response (0 to SMHz)
G5-18 = GI-17
Voltage gain with respect to color difference
inputs (Pins 17 and 18)
d5-18 = dl-17
Frequency response (0 to 2MHz)
GI-14=G3-13=G5-12
Voltage gain of inserted signals
dl-14 = d3-13 = d5-12
Frequency response (0 to 6MHz)
dB
16
3
6
dB
dB
3
dB
dB
6
3
dB
3
S
V
V
V
V
1
110
V
p.A
Sandeastle detector (Pin 10)
VlO-24
Vl0-24
VlO-24
VlO-24
Vl0-24
-110
There are 3 internal thresholds (proportional to VCc>6,
The following amplitudes are required for separating the
various pulses:
horizontal and vertical blanking pulses7
horizontal pulse
clamping pulse8
DC voltage for artificial black level
(scan and flyback)
no keying
input current
2
4
7,S
7.S
NOTES:
I. For saturated color bar with 75% of maximum amplitude.
2. VII - 24 < OAV during clamping time: the black levels of the inserted RGB signals are clamped on the black levels of the internal RGB signals.
V11 _ 24 > 0.9V during clamping time: the black levels of the inserted signals are clamped on an intemal DC voltage.
Correct clamping of the external AGB signals is only possible when they are synchronous with the sandcastle pulse.
3. With input Pins 21, 22, and 23 not connected, an internal bias voltage of 5.5V is supplied.
4. Black level of measured channel is nominal; the other two channels are blanked to ultra·black.
5. All three channels blanked to ultra·black.
The cut·off control cycle occurs when the vertical blanking part of the sandcastie pulse contains more than 3 line pulses.
The intemal signal blanking continues until the end of the last measurement line.
The vertical blanking pulse is not allowed to contain more than 34 line pulses; otherwise, another control cycle begins.
6. The thresholds are for
horizontal and vertical blanking: V, 0 _ 24 = 1.5V
horizontal pulse:
V'O-24 = 3.5V
clamping pulse:
V'O-24 = 7.0V
7. Blanking to ultra·black (-25%).
8. Pulse duration;' 3.5ps.
January 14, 1987
10·16
Signetics Linear Products
Product Specification
Chroma Control Circuit
TDA3505
-R
-G
-8
+aav---nYY~'---~~--~----r-------------~----~--~r-------------~----,
+12V---t--~~---r--~~~~---+----t----t---------t--~~--~---+----1----+----'
5IJO
..
+12V
..
ZI
r
22,H
SAN~A
~
SIGNAL
SWITCH
i. .
330nF
180
5
22nF
7
2 2 , -F P
22nF
r
~I
24
BRIGHTNESS
01012V
TDA3606
22nF
r ,.
,.
11
18
U3V..
22nF 12
17
1.05V..
22nF 13
18
22nF 14
15
1V
I
Q1Yp.p
I
R1Vp.p
CONTRAST
OT012V
-(..V)
-(R-V)
I
B1V"",
~.k
23
ElL.
PULR
25
SATURA110N
OT012V
y
I-=- 22nF
100nF
~V COMPOS/TI!
VIDEO SIGNAL)
+12V
8.2"
10k
BEAM CURRENT
(ACIUAL YAWE!
TC2O«1S
NOTES:
1. When supplied via a 750 line.
2. Capacitor value depends on circuit layout.
Figure 1. Typical Application Circuit Diagram Using the TDA3505
January 14. 1987
10-17
•
TDA3563
Signetics
NTSC Decoder With RGB Inputs
Product Specification
Linear Products
DESCRIPTION
FEATURES
The TDA3563 is a monolithic, integrated
color decoder for the NTSC standard. It
combines all functions required for the
identification and demodulation of NTSC
signals. Furthermore, it contains a luminance amplifier, and an RGB matrix and
amplifier. These amplifiers supply signals up to 5.3V peak-to-peak (picture
information) enabling direct drive of the
output stages. The circuit also contains
inputs for data insertion, analog as well
as digital, which can be used for Teletext
information, channel number display,
etc.
• Single-chip chroma & luminance
processor
• ACC with peak detector
• DC control settings
• External linear RGB Inputs
• High level RGB outputs
• No black level disturbance when
nonsync external RGB signals
are available on the inputs
• Luminance signal with clamp
• Black current stabilizer
• On-chip hue control
PIN CONFIGURATION
APPLICATIONS
•
•
•
•
•
N Package
Vee
28 CHROMAMP
OUT
1
ACCDET
SiHCAP
CHROM
IN
PEAK
DET
DECOUP
5
SAT
CONTROL
CON
CONTROL
SANDCASTLE
IN
INSERTION
CIRSWITCH
LUMINANCE
SIGNAL IN
BRIGHTNESS
CONTROL
22 REF SIGNAL
PHASEADJ
21 g~g~fN
20 BLACK LEVEL
CLAMP CAP
19
g~~~I£EL
18
g~~~~~pEL
REDOUT
Video monitors and displays
Text display systems
Television receivers
Graphic systems
Video processing
REDIN
TOP VIEW
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
_25°C to + 65°C
TDA3563N
28-Pin Plastic DIP (SOT-117)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
Vcc
= V,-27
ProT
PARAMETER
RATING
UNIT
Supply voltage (Pin 1)
13.2
V
Total power dissipation
1.7
W
TSTG
Storage temperature range
-65 to +150
°C
TA
Operating ambient temperature range
-25 to +65
°C
()JA
Thermal resistance from junction to
ambient (in free-air)
50
°C/W
February 12, 1987
10-18
853-118487586
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Product Specification
Signetics linear Products
TDA3563
NTSC Decoder With RGB Inputs
DC AND AC ELECTRICAL CHARACTERISTICS vee = Vl - 27 = 12V; TA = 25"C, unless otherwise specified.
LIMITS
UNIT
PARAMETER
SYMBOL
Min
Typ
Max
Supply (Pin 1)
Vee = Vl-27
Supply voltage
lee=ll
Supply current
PTOr
Total power dissipation
10
12
13.2
V
85
115
mA
1
1.4
W
+3
dB
15
p.A
1100
mV
Luminance amplifier
V10 - 27(P-P)
Input voltage 1 (peak-to-peak value)
0.45
-17
Contrast control range (see Figure 1)
1.2
Control voltage for an attenuation of 40dB
17
V
Contrast control input current
V
Chromlnance amplifier
V3-27(P-P)
Input voltage2 (peak-to-peak value)
55
ACC control range
30
550
dB
Change of the burst signal at the output over the whole control
range
1
Output voltage3 (peak-to-peak value) at a burst Signal of 0.3V
peak-to-peak
0.15
V28-27
Maximum output voltage range (peak-to-peak value); RL = 2kn
4
"'28_3
Frequency response between 0 and 5MHz
V28 - 27
V
V
-2
dB
20
p.A
10
mA
5
Hz
deg
50
Saturation control range (see Figure 2)
Is
Saturation control input current
Iz28 - 27 1
Output impedance of chrominance amplifier
128
Output current
dB
dB
25
n
Reference part
~f
!!.
'/
1-
1
o
VOCPIN 11
a. Control Characteristic of the Brightness Control
100
50
I'-.
i\
50
\ \1'-Voc PIN 20
b. Control Characteristic of the Hue Control
Figure 5
February 1987
10-31
•
Signetics Linear Products
Application Note
Application of the NTSC Decoder: TDA3563
~W\
,
AN156
~
\.- W\
1"see/DIV.
2v/DIV.
v
\I
\J
10 "sec/DIV.
2v/DIV.
II
200kHz BAR SIGNAL
a
o
........
-10
!ll
'" \
1\
-20
-30
II
/
,.-
-40
-50
o
2
3
SWEEP SIGNAL 0 to 5MHz
b
Figure 6. Contour Correction
February 1987
10-32
4
5
Signetics Unser Products
Application Note
Application of the NTSC Decoder: TDA3563
AN156
CHROMINANCE
~~
r
21
CONTRAST
CONTROL
VOLTAGE
LlNILOG
CONVERTER
SATURATION
CONTROL
VOLTAGE
GATED
CONTRAST
CONTROL
CHROMINANCE
~~~~
-jl-'=+-+--...I:...
GATED
SATURATION
CONTROL
FROMA.C.C.
DETECTOR
A.C.C.
VOLTAGE
PEAK
DETECTOR
KILLER
DETECTOR
KILLER
VOLTAGE
J
Figure 7. Chromlnance Channel
February 1987
10-33
,a,,,...
•
Signetics Linear Products
Application Note
Application of the NTSC Decoder: TDA3563
AN156
BIASING
CAPACITOR 5
(R-V)
L-_-+---I--1_-. REF.
(B-V)
REF.
TOPEAKANO
KILLER DET.
BIASING 23
CAPACITOR
~
Figure 8. Chromlnance Reference Circuits
February 1987
10·34
Application Note
Signetlcs Linear Products
AN156
Application of the NTSC Decoder: TDA3563
SANDCASTLE
PULSE
INPUT
7Vt--------+-------,
1.5
V
1.2
V
PULSE
PROCESSOR
CHROMA~--
__________
~
______________
(a-V)
OEM.
TO
B MATRIX
(G-V)
MATRIX
TO
GMATRIX
-+~~
TO
R MATRIX
22
CONTROL
VOLTAGE
-'IR-V)
Figure 9. Chromlnance Reference Circuits (Continued)
160
140
120
100
.......
\
~
VOCPIN 18
Figure 10. Control Characteristic of the Phase of the (R-V) Reference Signal, (B-V) Phase Is Equal to Zero
February 1987
10-35
•
Application Note
Signetics Linear Products
AN156
Application of the NTSC Decoder: TDA3563
1
EXTERNAL
R.G.B.
SIGNAL
13.15.17
v
BLACK LEVEL
CLI.MPING
CAPACITOR
20,19,18
2.7
V
-+--+--+--.
(C-V)
R.G.B.
~-=--+-... ~I~~A~T
12,14,16
R.G.B.
OUTPUT
STAGES
VIDEO/
DATA
IiWITCHING
CIRCUIT
BRIGHTNESS
CONTROL
CIRCUIT
PEAK WHITE
DETECTOR
TO CONTRAST
CONTROL CIRCUIT
VIDEO/
DATA
SWITCH
BRIGHTNESS
CONTROL
VOLTAGE
f
11
I
Figure 11. Video Control Circuits
February 1987
10-36
Signetics Linear Products
Application Note
Application of the NTSC Decoder: TDA3563
APPENDIX I
Conversion of a full-swing control voltage
range (from zero up to VSUPPLY) into a
restricted control voltage range of VLOW to
VHIGH:
The resistors R1, R2 and Rs, as a function of
the source impedance Rs of the network, are
defined by the following formula:
first define a source impedance Rs
Vs
Rl=---X Rs
VS-VH
Vs
v,
R2
=
v;: X Rs
.,
Vs
• Rs=---X Rs
VH-VL
.,
APPENDIX II
Temporary Information,
Concerning TDA3563 Versions
Up to N6
Alternative Adjustment
Procedure for the Reference
Oscillator of the TDA3563
Using the normal frequency adjustment procedure for the reference oscillator of the
AN156
TDA3563, i.e., setting the saturation control
voltage (Pin 6) to 12V (unkilling and unlocking
of the reference oscillator), and adjusting the
trimmer capacitor for minimum rolling of color
bars on the TV screen, the adjustment is
disturbed by an internal defect of the burst
phase detector.
If the reference frequency is adjusted in this
way, it results into a frequency deviation of
about 1kHz when removing the 12V connection at the saturation control input. So this
frequency adjustment of the oscillator of the
TDA3563, N6 cannot be used.
Therefore an alternative adjustment procedure is developed:
The X-tal has now a fixed capacitor of 12pF in
series to ground, instead of the trimmer
capacitor. The frequency adjustment is done
via current injection into the burst phase
detector (Pin 24).
The reference oscillator is made free-running
by removing the burst information out of the
chrominance signal.
ADJUSTMENT PROCEDURE FOR THE REFERENCE OSCILLATOR
OF THE TDA3565, N5
PIN3o-j~
10nF
BC547
PIN 8
ANDCASTLE
PULSE
10K
s.
1. Connect an Electronic Switch to Pin 3.
(Removing the burst Information)
12V
PIN1~PIN2
10K
PIN2:±10V
PIN 4: ±6V (VIA INTERNAL CIRCUIT)
2. Connect a Resistor of 10kn Between Pin 2 and 12V Supply Line.
(Color killer off and ACC control to minimum)
r-----o
PIN 30----1
56-100pF
PIN 21
3. Connect a Capacitor of 56 to 100pF Between Pins 3 and 21.
(Input signal at the demodulator Input will be without any burst Information)
PIN 24
12V
4. Frequency Adjustment of the Oscillator.
(Adjust the potentiometer for minimum roiling of color bars at the TV screen)
February 19B7
10-37
•
TDA3564
Signetics
NTSC Decoder
Product Specification
Linear Products
DESCRIPTION
FEATURES
The TDA3564 is a monolithic integrated
decoder for the NTSC color television
standards. It combines all functions required for the demodulation of NTSC
signals. Furthermore, it contains a luminance amplifier and an RGB matrix and
amplifier. These amplifiers supply output
signals up to 5Vp _ p (picture information)
enabling direct drive of the discrete output stages.
• Single-chip chroma and
luminance processor
• ACC with peak detector
• DC control settings
• High-level RGB outputs
• Luminance signal with clamp
• Black current stabilizer
• On-chip hue control
PIN CONFIGURATION
Vee
1
ACCDET
S/HCAP
CHROMA
IN
PEAK
DET
DECOUPCAP
5
CONTRAST
18 ~ij~~GftrL
CONT
SANDCASTLE
g:g~~N
PULSE
LUMINANCE
16 g~~ '&'(,EL
IN
PEAKING
15 BWEOUT
CAP
PEAKING
CONTROL
BRIGHTNESS
CONTROL ---._ _ _.......
17
APPLICATIONS
• Video monitors and displays
• Television receivers
• Video processing
ORDERING INFORMATION
TOP VIEW
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
-25·C to +65·C
TDA3564N
24-Pin Plastic DIP (SOT-101A)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
Vcc = V1 - 23
Supply voltage (Pin 1)
13.2
V
ProT
Total power dissipation
1.7
W
-65 to + 150
·C
-25 to +65
·C
50
·C/W
TSTG
Storage temperature range
TA
Operating ambient temperature range
{)JA
Thermal resistance from junction to
ambient (in free air)
January 14, 1987
10-38
853-1149 87202
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Product Specification
Signetics linear Products
TDA3564
NTSC Decoder
DC AND AC ELECTRICAL CHARACTERISTICS Vcc = Vl - 23 = 12V; TA = 25°C, unless otherwise
spec~ied.
LIMITS
PARAMETER
SYMBOL
Min
Typ
Max
12
13.2
I
UNIT
Supply (Pin 1)
Vee = Vl-23
Supply voltage
Icc=ll
Supply current
PTOT
Total power dissipation
8
V
85
mA
1
W
Luminance amplifier (Pin 9)
V9-23(P.P)
Input voltage 1 (peak·to·peak value)
V9-23
Input level before clipping
19
Input current
0.15
Contrast control range (see Figure 1)
-17
2
V
1
p.A
+3
dB
15
p.A
1.2
Control voltage for an attenuation of 40dB
17
mV
450
Input current contrast control
V
Peaking of luminance signal
I Z10-231
200
Output impedance (Pin 10)
Vll-23
Control voltage for peaking adjustment (Pin 11)
IZl1 - 23 1
Input impedance (Pin 11)
n
3
Ratio of internal/external current when Pin 10 is short·circuited
2-4
V
10
kn
Chromlnance amplifier (Pin 3)
V3-23(P.P)
Input voltage2 (peak·to·peak value)
IZ3- 23 1
Input impedance
8
C3-23
Input capacitance
4
55
550
1100
kn
6
30
ACC control range
pF
dB
1
Change of the burst signal at the output over the whole control range
Gain at nominal contrast/saturation Pin 3 to Pin 24 3
mV
13
dB
dB
V24-23(P.P)
Output voltage3 (peak·to·peak value) at a burst signal of 300mVp.p
240
mV
V24-23(P.P)
Maximum output voltage range (Pin 24) (peak·to·peak value)
1-7
V
d
Distortion of chrominance amplifier at V24-23(P.P) = 0.5V (output)
up to V3-23(P.P) = 1V (input)
"'24_3
Frequency response between 0 and 5MHz
%
-2
dB
dB
Input current saturation control (Pin 6)
20
p.A
Tracking between luminance and chrominance contrast control
2
dB
Cross·coupling between luminance and chrominance amplifier"
-46
dB
SIN
Signal·to·noise ratio at nominal input signalS
Ll.t/>
Phase shift between burst and chrominance at nominal contrast/
saturation
IZ24 - 23 1
Output impedance of chrominance amplifier
124
Output current
January 14, 1987
5
50
Saturation control range (see Figure 2)
16
3
56
dB
±5
deg
10
mA
25
10-40
n
Product Specification
Signetics Linear Products
TDA3564
NTSC Decoder
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) Vce=VI-23=12V; TA=25°C, unless otherwise specified.
LIMITS
UNIT
PARAMETER
SYMBOL
Min
Typ
500
700
Max
Reference part
M
Phase-locked loop
Catching range6
Phase shift for ± 400Hz deviation of fose6
TCase
afase
R22-23
C22 - 23
Oscillator
Temperature coefficient of oscillator frequency6
Frequency variation when supply voltage increases from 10 to 13.2V6
Input resistance (Pin 22)
Input capacitance (Pin 22)
V2-23
V2-23
V2-23
V2-23
ACC generation (Pin 2)
Control voltage at nominal input signal
Control voltage without chrominance input
Color-off voltage
Color-on voltage
V4_23
Voltage at Pin 4 at nominal input signal
af
5
Hz
deg
10
Hz/oC
Hz
n
pF
-1.5
40
300
V
V
V
V
5.3
2.8
3.4
3.6
Change in burst amplitude with supply voltage
independent
5.2
Hue control
Control range
V
±50
Control voltage range
deg
see Figure 4
V
320
mV
2
kn
Demodulator part
V17 - 23(P-P)
Input burst signal amplitude (Pin 17) (peak-to-peak value)
IZ 17 - 23 1
Input impedance (Pin 17)7
V15-23
V13-23
V14-23
V13-23
V14-23
Ratio of demodulated signals (B-Y)/(R-V)
1.1
(G-V)/(R-Y); no (B-V) signal
0.26
(G-Y)/(B-Y); no (R-Y) signal
0.22
VI5-23
Frequency response between 0 and 1MHz
-3
40
Cross-talk between color difference signals
~
Control range reference signal (R-Y) demodulator (Pin 18)8
dB
dB
see Figure 5
deg
5
V
5.25
V
RGB matrix and amplifiers
VI3,14,
15-23(P·P)
Output voltage (peak-to-peak value) at nominal input signal
(black-to-white)3
VI 3-23(P-P)
Output voltage at Pin 13 (peak-to-peak value) at nominal contrast!
saturation and no luminance signal to (R-Y)
V13. 14, 15- 23
Maximum peak-white level9
113.14.15
Maximum output current (Pins 13, 14, 15)
V13, 14, 15-23
Output black level voltage for a brightness control voltage at
Pin 12 of 2V
g
9.3
V
10
rnA
2.7
Black level shift with vision contents
V
40
Brightness control voltage range
January 14, 1987
9.6
see Figure 3
10-41
mV
V
•
Signetics Linear Products
Product Specification
TDA3564
NTSC Decoder
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) Vec = VI -23 = 12V; TA = 25°C, unless otherwise
spec~ied.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
112
Brightness control input current
AVIAT
AV
Variation of black level
with temperature
with contrast
Typ
5
IlA
1
100
mVloC
mV
10
%
20
mV
0
20
mV
2.1
2.3
0.35
10
Relative spread between the R, G, and B output signals
Relative black level variation between the three channels during
variation of contrast, brightness, and supply voltage
0
Differential black level drift over a temperature range of 40°C
Blanking level at the RGB outputs
1.9
V
Difference in blanking level of the three channels
0
mV
Differential drift of the blanking levels over a temperature range of 40°C
0
rnA
AVBl
Vce
--X-AVec
VBl
Tracking of output black level with supply voltage
SIN
Signal-to-noise ratio of output signals5
1Z13. 14. 15-231
Max
1.1
62
dB
Residual 7.1 MHz signal and higher harmonics at the RGB outputs
(peak-to-peak value)
75
Output impedance of RGB outputs
50
Frequency response of total luminance and RGB amplifier circuits for
f= 0 to 5MHz
150
mV
n
-3
dB
V
Sandcastle Input (Pin 8)
Ve-23
Level at which the RGB blanking is activated
Ve-23
Level at which burst gating and clamping pulse are separated
to
Delay between black level clamping and burst gating pulse
-Ie
Ie
Ie
Input current
at Ve-23 = 0 to 1V
at Ve-23 = 1 to 8.5V
at Ve-23 = 8.5 to 12V
1
i.5
2
6.5
7
7.5
0.4
V
IlS
1
rnA
2
rnA
20
IlA
NOTES:
1. Signal with the negative-going sync; amplitude includes sync amplijude.
2. Indicated is a signal for a color bar with 75% saturation; chrominance-to-burst ratio is 2.2:1.
3. Nominal contrast is specified as the maximum contrast -3dS and nominal saturation as the maximum saturation -6dS.
4. Cross coupling is measured under the following conditions:
• Input signals nominal
• Contrast and saturation such that nominal output signals are obtained
• The signals at the output at which no signal should be available must be compared to the nominal output signal at that output.
5. The signal-to-noise ratio is defined as peak-to-peak signal with respect to RMS noise.
6. All frequency variations are referred to 3.58MHz carrier frequency.
7. These signal amplijudes are determined by the ACC circuit of the reference part.
8. When Pin 18 is open circuit, the phase shift between the (R-Y) and (B-Y) reference carrier is 115·. This phase shift can be varied by changing the
voltage applied to Pin 18.
9. If the typical voltage for this wMe level is exceeded, the output voltage is reduced by discharging the capaCitor at Pin 7 (contrast control); discharge
current is I.SmA.
FUNCTIONAL DESCRIPTION
Luminance Amplifier
The luminance amplifier is voltage driven and
requires an input signal of 450mVp_p (positive
video). The luminance delay line must be
connected between the IF amplifier and the
decoder. The input signal is AC-coupled to
the input (Pin 9).
January 14, 1987
The black level at the output of the preamplifier is clamped to a fixed DC level by the black
level clamping circuit. The high input impedance of the luminance amplifier minimizes
disturbance of the input signal black level by
the source impedance (delay line matching
resistors).
During clamping, the low-input impedance
reduces noise and residual signals. After
10-42
clamping, the signal is fed to a peaking stage.
The overshoot is defined by the capacitor
connected to Pin 10 and the peaking is
adjusted by the control voltage at Pin 11.
The peaking stage is followed by a contrast
control stage. The contrast control voltage
range (Pin 7) is nominally-17to +3dB. The
linear relationship between the contrast-control voltage and the gain is shown in Figure 1.
Signetics Unear Products
Product Specification
TDA3564
NTSC Decoder
Chrominance Amplifier
The chrominance amplifier has an asymmetrical input. The input signal must be ACcoupled (Pin 3) and have a minimum amplitude of SSmVp_p. The gain control stage has
a control range in excess of 30dB, the maximum input signal must not exceed 1.1Vp_p,
otherwise clipping of the input signal will
occur. From the gain control stage the chrominance Signal is fed to the saturation and
contrast control stages. Chrominance and
luminance contrast control stages are directly
coupled to obtain good tracking. Saturation is
linearly controlled via Pin 6 (see Figure 2).
The control voltage range is 2V to 4V, the
input impedance is High, and the saturation
control range is in excess of SOdB. The burst
signal is not affected by saturation control.
The output signal at Pin 24 is AC coupled to
the demodulators via Pin 17.
Oscillator and ACC Detector
The 7.16MHz reference oscillator operates at
twice the subcarrier frequency. The reference
signals for the (R-Y) and (B-Y) demodulators,
burst-phase detector, and ACC detector are
obtained via the divide-by-2 circuit, which
provides a 90· phase shift The oscillator is
controlled by the burst phase detector, which
is gated with the narrow part of the sandcastie pulse (Pin 8). As the burst phase detector
has an asymmetrical output, the oscillator can
be adjusted by changing the voltage of the
output (Pin 21) via a high-ohmic resistor. The
capacitor in series with the oscillator crystal
must then have a fixed value. When Pin 6
(saturation control) is connected to the positive supply line, the burst signal is suppressed
and the color killer is overruled. This position
can therefore be used for adjustment of the
oscillator. The adjustment is visible on the
screen.
January 14, 1987
The hue control is obtained by changing the
phase of the input Signal of the burst phase
detector with respect to the chrominance
signal applied to the demodulators. This
phase shift is obtained by generating a 90·
shifted sine wave via a Miller integrator (biased via Pin 19) which is mixed with the
original burst signal. A control circuit is required in the 90· phase shift circuit to make
the chrominance voltage independent of the
hue setting. The control circuit is decoupled
by· a capacitor connected to Pin 5.
As the shifted burst signal is synchronously
demodulated in a separate ACC detector to
generate the ACC voltage, it is not affected
by the hue control. The output pulses of this
detector are peak detected (Pin 4) to control
the gain of the chrominance amplifier, thus
preventing blooming-up of the color during
weak signal reception. This ensures reliable
operation of the color killer. During color
killing, the color channel is blOCked by switching off saturation control and the demodulators.
Demodulators
The (R-Y) and (B-Y) demodulators are driven
by the chrominance signal (Pin 24) and the
reference signals from the 7.16MHz divider
circuit. The phase angle between the two
reference carriers is 115·. This is achieved by
the (R-Y) demodulator receiving an additional
phase shift by mixing the two signals from the
divider circuit. The phase shift of 115· can be
varied between 90· and 140· by changing the
bias voltage at Pin 18. The demodulator
output signals are fed to Rand B matrix
circuits and to the (G-Y) matrix to provide the
(G-Y) Signal which is applied to the G matrix.
The demodulator circuits are killed and
blanked by bypassing the input signals.
10-43
RGB Matrix and Amplifiers
The three matrix and amplifier circuits are
identical and only one circuit will be described. The luminance and the color difference signals are added in the matrix circuit to
obtain the color signal. Output signals are
SVp.p (black-white) for the following nominal
input signals and control settings.
• Luminance 450mVp.p
• Chrominance 5S0mVp.p (burst-tochrominance ratio of the input 1:2, 2)
• Contrast -3dB maximum
• Saturation -6dB maximum
The maximum output voltage is approximately 7Vp.p.
The black level of the blue channel is compared to a variable external reference level
(Pin 12) which provides brightness control.
The brightness control range is 1V to 3.2V
(see Figure 3). The control voltage is stored in
a capacitor (connected to Pin 16) and controls the black level at the output (Pin 15)
between 2V and 4V, via a change of the level
of the luminance signal before matrixing.
NOTE:
Black levels of up to approximately 6V are possible,
but amplitude of the output signal is reduced to
3Vp.p.
If the output signal surpasses the level of 9V,
the peak white limiter circuit becomes active
and reduces the output signal via the contrast
control.
Blanking of RGB Signals
The RGB Signals can be blanked via the
sandcastle input (Pin 8). A slicing level of
1.5V is used for this blanking function, so that
the wide part of the sandcastle pulse is
separated from the remainder of the pulse.
During blanking, a level of + 2V is available at
the output.
•
Signetics Linear Products
Product Specification
NTSC Decoder
TDA3564
100
100
Ir.
r/I
17
'Ii
I
I I
1/1.
'U!
'ti
;f!
I
I
If/I
- -1--
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W
-V.I
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OPI7021S
FIgure 1. Contrast Control
Voltage Range
FIgure 2. SaturatIon Control
Voltage Range
,50
...
80
40
;\
C130
-80
,
t-- I2
r-..
~110
\
-40
r-..
i
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10
3
6
0""",'
FIgure 4. Hue Control Voltage Range
January 14, 1987
FIgure 5. Phase ShIft Between (R-V)
and (B-V) as a FunctIon of V,8-23
10-44
FIgure 3. Brlghtnesa Control
Voltage Rsnge
Product Specification
Signetics Linear Products
TDA3564
NTSC Decoder
APPLICATION CIRCUIT FOR TDA3564 NTSC COLOR DECODER
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OUTPUT SIGNALS
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12k
22nF
180
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180
180
-=
220pF
AVERAGE
BEAM CURRENT
14
13
12
lOOk
68k
33k
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120k
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10k
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•
Signetics Linear Products
Product Specification
TDA3564
NTSC Decoder
NTSC DECODER N 2500
NOTES:
L1 "" L2 pH TOKO 7P mat.
Controls:
1. Saturation
2. Contrast
3. Peaking
4. Brightness
5. IIQ (R·Y)
6. Hue
7, Osc. freq.
January 14, 1987
10-46
TDA3566
Signetics
PAL/NTSC Decoder With RGB
Inputs
Product Specification
Linear Products
DESCRIPTION
The TDA3566 is a monolithic, integrated
decoder for the PAL ® and/or NTSC
color television standards. It combines
all functions required for the identification and demodulation of PAL/NTSC
signals. Furthermore, it contains a luminance amplifier, and an RGB matrix and
amplifier. These amplifiers supply output
signals up to 4V p_p (picture information)
enabling direct drive of the discrete output stages. The circuit also contains
separate inputs for data insertion, analog as well as digital, which can be used
for text display systems (e.g., Teletext/
broadcast antiope), channel number display, etc.
FEATURES
• No black level disturbance when
nonsynchronized external RGB
signals are available on the
inputs
• NTSC capability with hue control
• Single-chip chroma and
luminance processor
• ACC with peak detector
• DC control settings
• External linear or digital RGB
inputs
• High-level RGB outputs
• Luminance signal with clamp
• On-chip hue control for NTSC
APPLICATIONS
•
•
•
•
•
• A black current stabilizer which
controls the black currents of
the three electron guns to a
level low enough to omit the
black level adjustment
• Contrast control of inserted RGB
signals
PIN CONFIGURATION
N Package
vee
28 CHROMA
AMP OUT
1
ACCDET
S/HCAP
PEAKDET
3
CHROMA
IN
SATURATION
CONTROL
CONTRAST
CONTROL
SANOCASTLE
PULSE IN
LUMINANCE
IN
INSERTION
SWITCH
BLACK LEVEL
25 BURST PHASE
DETOUT
24 BURsr PHASE
DETOur
23
22
21 ~~~~WL
20 BLACK LEVEL
CLAMP CAP
18
m~~'I!AP
~~~~FO
18
~N~fRTION
19
CLAMP CAP
BRlg~J~~~
11
INSERT~6~
12
REDOUT
Video monitors and displays
Text display systems
TV receivers
Graphic systems
Video processing
g~~g~f'N.
g~~g~fN.
TOP VIEW
II
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
-25'C to + 70'C
TDA3566N
28-Pin Plastic DIP (SOT -117)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
= V1-27
PARAMETER
RATING
UNIT
Supply voltage (Pin 1)
13.2
V
PTOT
Total power dissipation
1.7
W
TSTG
Storage temperature range
-65 to +150
'C
TA
Operating ambient temperature range
-25 to +70
'C
8JA
Thermal resistance from junction to
ambient (in free air)
40
'C/W
Vce
®pAL is a registered trademark of Monolithic Memories, Inc.
February 12, 1987
10-47
853-1189 87586
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Product Specification
Signetics Linear Products
TDA3566
PAl/NTSC Decoder With RGB Inputs
DC AND AC ELECTRICAL CHARACTERISTICS vee = V1- 27 = 12V; TA = 25'C, unless otherwise specified.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
Supply (Pin 1)
= V1- 27
lee = 11
Supply voltage
PTOT
Total power dissipation
Vee
10.8
Supply current
12
13.2
V
80
110
mA
0.95
1.3
W
0.45
0.63
V
1
V
1
p.A
Luminance amplifier (Pin 8)
V8-27(P.P)
Input voltage 1 (peak-to-peak value)
V8- 27
Input level before clipping
18
0.1
Input current
-15
Contrast control range (see Figure 1)
17
Input current contrast control
+5
dB
15
p.A
1100
mV
Chrominance amplifier (Pin 4)
V4-27(P-P)
Input voltage2 (peak-to-peak value)
Iz4 _ 27 1
Input impedance (Pin 4)
C4- 27
Input capacitance
40
10
30
tlV
Change of the burst signal at the output over the whole control range
Av
Gain at nominal contrast/saturation Pin 4 to Pin 28 3
V28 - 27(P-P)
Maximum output voltage range (peak-to-peak value); RL = 2kn
1
d
Distortion of chrominance amplifier at V28 _ 27(P-P)
V4 _ 27(P.P) = 1V (input)
= 2V
4
dB
dB
5
V
Frequency response between 0 and 5MHz
Cross-coupling between luminance and chrominance amplifier4
Signal-to-noise ratio at nominal input signal 5
tl 0.9V
46
10
dB
Sandcaatle Input (Pin 7)
V7-27
Level at which the RGB blanking is activated
1
1.5
2
V
3
3.5
4
V
6.5
7.0
7.5
V
V7- 27
Level at which the horizontal pulses are separated
V7-27
Level at which burst gating and clamping pulse are separated
to
Delay between black level clamping and burst gating pulse
-17
17
17
Input current
at V7-27 =0 to 1V
at V7_27 = 1 to 8.5V
at V7-27 = 8.5 to 12V
0.6
JJS
mA
1
50
2
mA
/lA
Black current stabilization (Pin 18)
V18-27
Bias voltage (DC)
3.5
5
7.0
V
AV
Difference between Input voltage for 'black' current and leakage
current
0.35
0.5
0.65
V
118
Input current during 'black' current
1
iJA
118
Input current during scan
10
mA
V
V1B-27
Internal limiting at Pin 10
8.5
9
9.5
V18-27
Switching threshold for 'black' current control ON
7.6
8
8.4
V
R18-27
Input resistance during scan
1
1.5
2
kO
TBD
nA
110,20.21
Input current during scan at Pins 10, 20, and 21 (DC)
Maximum charge! discharge current during measuring time
February 12, 1987
10-52
1
nA
Product Specitication
Signetics Linear Products
TDA3566
PALjNTSC Decoder With RGB Inputs
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) vee = V1-27 = 12V; TA = 25°C, unless otherwise specified.
LIMITS
PARAMETER
SYMBOL
Min
I
Typ
l
B.B
j
UNIT
Max
NTSC
V24-25
Level at which the PALINTSC switch is activated (Pins 24 and 25)
124+ 2S(AV)
Average output current 12
75
Hue control
I
90
I
I
9.2
V
105
p.A
see Figure 4
NOTES:
1. Signal with the negative-going sync; amplitude includes sync amplitude.
2. Indicated is a signal for a color bar with 75% saturation; chrominance to burst ratio is 2.2:1.
3. Nominal contrast is specified as the maximum contrast- 5dB and nominal saturation as the maximum saturation - 6dB.
4. Cross coupling is measured under the following condition: input signal nominal, contrast and saturation such that nominal output signals are obtained.
The signals at the output at which no signal should be available must be compared with the nominal output signal at that outpu\.
5. The signal-to-noise ratio is defined as peak-to-peak signal with respect to RMS noise.
6. All frequency variations are referred to 4.4MHz carrier frequency.
7. These signal amplitudes are determined by the ACC circuit of the reference part.
8. The demodulators are driven by a chrominance signal of equal amplitude for the (R-Y) and the (B-Y) components. The phase of the (R-Y)
chrominance signal equals the phase of the (R-Y) reference signal. This also applies to the (B-Y) signals.
9. This value depends on the gain setting of the RGB output amplifiers and the drift of the picture tube guns. Higher black level values are possible
(up to 5V), but in that application the amplitude of the output signal Is reduced.
10. The variation of the black-level during brightness control in the three different channels is direclly dependent on the gain of each channel.
Discoloration during adjustment of contrast and brightness does not occur because amplitude and the black-level change with brightness control are
directly related.
11. This difference occurs when the source impedance of the data signals is 150!"! and the black level clamp pulse width is 41's (sandcaslle pulse). For
a lower impedance the difference will be lower.
12. The voltage at Pins 24 and 25 can be changed by connecting the load resistors (10k!"! in this application) to the slider bar of the hue control
potentiometer (see Figure 7). When the transistor is switched on, the voltage at Pins 24 and 25 is reduced below 9V, and the circuit is switched to
NTSC mode. The width of the bUrst gate is assumed to be 4,.. typical.
•
February 12, 19B7
10-53
Signetics Linear Products
Product Specification
PAl/NTSC Decoder With RGB Inputs
FUNCTIONAL DESCRIPTION
The TDA3566 is a further development of the
TDA3562A. It has the same pinning and
almost the same application. The differences
between the TDA3562A and the TDA3566
are as follows:
• The NTSC application has largely been
simplified. In the case of NTSC, the chroma
signal is now internally coupled to the
demodulators, ACC, and phase detectors.
The chroma output signal (Pin 28) is
suppressed in this case. It follows that the
external switches and filters which are
needed for the TDA3562A are not needed
for the TDA3566. Furthermore, there is no
difference between the ampl~ude of the
color output signals in the PAL or NTSC
mode. The PALINTSC switch and the hue
control of the TDA3566 and the TDA3562A
are identical.
• The switch-on and the switch-off behavior
of the TDA3566 has been improved. This
has been obtained by suppressing the
output signals during the switch-on and
switch-off periods.
• The clamp capacitors connected to the
Pins 10, 20, and 21 can be reduced to
100nF for the TDA3566. The clamp
capacitors also receive a pre-bias voltage
to avoid colored background during switchon.
• The crystal oscillator circuit has been
changed to prevent parasitic oscillations on
the third overtone of the crystal. This has
the consequence that optimal tuning
capacitance must be reduced to 10pF.
Luminance Amplifier
The luminance amplifier is voltage driven and
requires an input signal of 450mV peak-topeak (positive video). The luminance delay
line must be connected between the IF amplifier and the decoder. The input signal is AC
coupled to the input (Pin 8). After emplification, the black level at the output of the
preamplifier is clamped to a fixed DC level by
the black clamping circuit. During three line
periods after vertical blanking, the luminance
signal is blanked out and the black level
reference voltage is Inserted by a switching
circuit. This black level reference voltage is
controlled via Pin 11 (brightness). At the
same time, the RGB signals are clamped.
Noise and residual signals have no influence
during clamping; thus, simple internal clamping circuitry is used.
Chrominance Amplifiers
The chrominance amplifier has an asymmetrical input. The input signal must be AC coupled (Pin 4) and have a minimum amplitude of
40mVp.p. The gain control stage has a control range in excess of 30dB; the maximum
input Signal must not exceed 1.1 Vp.p or
clipping of the input signal will occur. From
February 12, 1987
the gain-control stage, the chrominance signal is fed to the saturation control stage.
Saturation is linear controlled via Pin 5. The
control voltage range is 2 to 4V, the input
impedance is high, and the saturation control
range is in excess of 50dB. The burst signal is
not affected by saturation control. The signal
is then fed to a gated amplifier which has a
12dB higher gain during the chrominance
signal. As a result, the Signal at the output
(Pin 28) has a burst-to-chrominance ratio
which is 6dB lower than that of the input
signal when the saturation control is set at
-6dB. The chrominance output signal is fed
to the delay line and, after matrixing, is
applied to the demodulator input pins (Pins 22
and 23). These signals are fed to the burst
phase detector. In the case of NTSC, the
chroma signal is internally coupled to the
demodulators, ACC, and phase detector.
Oscillator and Identification
Circuit
The burst phase detector is gated with the
narrow part of the sandcastle pulse (Pin 7). In
the detector, the (R-V) and (B-V) signals are
added to provide the compos~e burst signal
again. This composite signal is compared to
the oscillator signal divided-by-2 «R-V) reference signal). The control voltage is available
at Pins 24 and 25, and is also applied to the
8.8MHz oscillator. The 4.4MHz signal is obtained via the divide-by-2 circuit, which generates both the (B-V) and (R-V) reference
signals and provides a 90' phase shift between them.
The flip-flop is driven by pulses obtained from
the sandcastle detector. For the identification
of the phase at PAL mode, the (R-V) reference signal coming from the PAL switch is
compared to the vertical signal (R-V) of the
PAL delay line. This is carried out in the H/2
detector, which is gated during burst. When
the phase is incorrect, the flip-flop gets a
reset from the identification circuit. When the
phase is correct, the output voltage of the HI
2 detector is directly related to the burst
amplitude so that this voltage can be used for
the ACC. To avoid 'blooming-up' of the picture under weak input signal conditions, the
ACC voltage is generated by peak detection
of the H/2 detector output signal.
The killer and identification circuits get their
information from a gated output signal of the
H/2 detector. Killing is obtained via the saturation control stage and the demodulators to
obtain good suppression. The time constant
of the saturation control (Pin 5) provides a
delayed sw~ch-on after killing.
Adjustment of the oscillator is achieved by
variation of the burst phase detector load
resistance between Pins 24 and 25 (see
Figure 6). W~h this application, the trimmer
capacitor in series with the 8.8MHz crystal
10-54
TDA3566
(Pin 26) can be replaced by a fixed value
capacitor to compensate for imbalance of the
phase detector.
Demodulator
The (R-V) and (B-Y) demodulators are driven
by the color difference signals from the delayline matrix circuit and the reference signals
from the 8.8MHz divider circuii. The (R-Y)
reference signal is fed via the PAL-switch.
The output signals are fed to the Rand B
matrix circuits and to the (G-Y) matrix to
provide the (G-V) Signal which is applied to
the G matrix. The demodulation circuits are
killed and blanked by bypassing the input
Signals.
NTSC Mode
The NTSC mode is switched on when the
voltage at the burst phase detector outputs
(Pins 24 and 25) is adjusted below 9V. To
ensure reliable application, the phase detector load resistors are external. When the
TDA3566 Is used only for PAL, these two
33kn resistors must be connected to + 12V
(see Figure 6). For PALINTSC application,
the value of each resistor must be reduced to
10kn and connected to the slider of a potentiometer (see Figure 7). The switching transistor brings the voltage at Pins 24 and 25 below
9V, which switches the circuit to the NTSC
mode. The position of the PAL flip-flop ensures that the correct phase of the (R-Y)
reference signal is supplied to the (R-V)
demodulator. The drive to the H/2 detector is
now provided by the (B-V) reference signal.
(In the PAL mode it is driven by the (R-V)
reference signal.)
Hue control is realized by changing the phase
of the reference drive to the burst phase
detector. This is achieved by varying the
voltage at Pins 24 and 25 between 7.5V and
8.5V, nominal pos~ion 8.0V. The hue control
characteristic is shown in Figure 4.
RGB Matrix and Amplifiers
The three matrix and amplifier circuits are
identical and only one circuit will be described. The luminance and the color difference signals are added in the matrix circuit to
obtain the color signal, which is then fed to
the contrast control stage. The contrast control voltage is supplied to Pin 6 (high-input
impedance). The control range is + 3dB to
-17dB nominal. The relationship between the
control voltage and the gain is linear (see
Figure 1).
During the 3-line period after blanking, a
pulse is inserted at the output of the contrast
control stage. The amplitude of this pulse is
varied by a control voltage at Pin 11. This
applies a variable offset to the normal black
level, thus providing brightness control. The
brightness control range is 1V to 3V.
Product Specification
Signetics Linear Products
TDA3566
PALjNTSC Decoder With RGB Inputs
While this offset level is present, the 'blackcurrent' input impedance (Pin 18) is high and
the internal clamp circuit is activated. The
clamp circuit then compares the reference
voltage at Pin 19 with the voltage developed
across the external resistor network RA and
Rs (Pin 18) which is provided by picture tube
beam current. The output of the comparator
is stored in capacitors connected from Pins
10, 20, and 21 to ground, which controls the
black level at the output. The reference
voltage is composed by the resistor divider
network and the leakage current of the picture tube into this bleeder. During vertical
blanking, this voltage is stored in the capacitor connected to Pin 19, which ensures that
the leakage current of the CRT does not
influence the black current measurement.
beam current stabilizer is not used, it is
possible to stabilize the black levels at the
outputs, which in this application must be
connected to the black current measuring
input (Pin 18) via a resistor network.
Data Insertion
Each color amplifier has a separate input for
data insertion. A 1Vp_p input signal provides a
4Vp_p output signal. To avoid the 'black-level'
of the inserted signal differing from the black
level of the normal video signal, the data is
clamped to the black level of the luminance
signal. Therefore, AC coupling is required for
the data inputs.
To avoid a disturbance of the blanking level
due to the clamping circuit, the source impedance of the driver circuit must not exceed
150n.
The RGB output signals can never exceed a
level of 10V. When the signal tends to exceed
this level, the output signal is clipped. The
black level at the outputs (Pins 13, 15, and
17) will be about 3V. This level depends on
the spread of the guns of the picture tube. If a
100
J
The data insertion circuit is activated by the
data blanking input (Pin 9). When the voltage
at this pin exceeds a level of 0.9V, the RGB
matrix circuits are switched off and the data
amplifiers are switched on. To avoid colored
edges, the data blanking switching time is
short.
The amplitude of the data output signals is
controlled by the contrast control at Pin 6.
The black level is equal to the video black
level and can be varied between 2 and 4V
(nominal condition) by the brightness control
voltage at Pin 11. Non-synchronized data
signals do not disturb the black level of the
internal signals.
Blanking of RGB and Data
Signals
Both the RGB and data signals can be
blanked via the sandcastie input (Pin 7). A
slicing level of 1.5V is used for this blanking
function, so that the wide part of the sandcastie pulse is separated from the remainder of
the pulse. During blanking, a level of + 1V is
available at the output. To prevent parasitic
oscillations on the third overtone of the crystal, the optimal tuning capacitance should be
10pF.
100
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3
27
VS_ 27 (V)
M
Figure 1. Contrast Control Voltage Range
Figure 2. Saturation Control Voltage Range
60
2
v
40
V
20
/
~
/
1\
\
;--
-20
/
-1
V
-2
II
[//
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-40
-60
o
r\
7.5
8.5
8.0
V24;.5-.7
M
OP18130S
Figure 3, Difference Between Black Level and Measuring
Level at the RGB Outputs (~V) as a Function of the
Brightness Control Input Voltage (VII-27)
February 12, 1987
Figure 4, Hue Control Voltage Range
10-55
f
UNES~__ _
~
(V+3H)
---.r-------.r-----
BLANKING PULSE
(BL1)
--.JnL---I.----
BLANKING PULSE
(BL2)
n
r-----.J L---I
~
~
~
VERTICAL BlANKING (V)
BLACK
LEVEL
REFERENCE
VOLTAGE
BLANKING PULSE (BL3)
..c:
Z
I ~t-----IT---,
,
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8l
INSERTION PULSE (3L)
(CONTROL VIA PIN 11)
BLACK CURRENT
INFORMATION PULSE (M)
(PIN 18)
c:
----------------"T'"--I
I
I I·
( I)
nn.n.1------
~'-------! I n. . . _____
II II
n~-------
CLAMP PULSE (LO)
CLAMP PULSE (Ll)
CLAMP PULSE (L2)
I
CLAMP PULSE (L3)
I
RETlIACE MUST
BE COMPLETED
n'---------
I
I
t t
END OF VERTICAL SYNC
FROM TDA2579
= 21 '" 2 UNE PERIODS
Rgure 5. TIming Diagram for Black Current Stabilizing
~
&
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2
~
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I DL700· I
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S470
120k
+12V
t
Uk
47k
BLACK
CURRENT
+12V INFORMATION
~
10k
BRIGHTNESS
10k
ADJUST
33k>
+
~
BAW62
33k
3-LEVEL
SANOCASTLE
PULSE
....
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c=JB.BMHz
c:
(1)
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c:
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lose
0
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B2k
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RED
GREEN
BLUE
:::c
AVERAGE
BEAM
CURRENT
(j)
+12V
::J
10k
CONTRAST
17
C?
01
.....
-=-
11
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C
-+
en
TDA3566
+12V
fi
6Bk
~lf~'T J -t46~H Il~ ·
75
lk
R-
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75
--
B
DATA INPUTS
-=NOTE:
·01700 AMPEREX CORP
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Figure 6. Application Diagram Showing the TDA3566 for a PAL Decoder
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BLACK
CURRENT
INFORMATION
RA
82k
130k
__
~
1k
~+12V
nF
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+12V
47k
23
3-LEVEL
SANDCASTLE
PULSE
7
22
10k
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10k
BLUE
17
11
CD
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(j)
AVERAGE
BEAM
CURRENT
+12V
GREEN
:;0
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18
a.
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BAW62
RED
26
10k
BRIGHlNESS
2. ) l1V; vertical identification and artificial black level.
VS-2 = 5 to 7V; horizontal identification and artificial black level.
Figure B. PAL/SECAM Application Circuit Diagram Using the TDA3590 and TDA3566
February 12, 1987
10-59
•
TDA3567
Signetics
NTSC Color Decoder
Product Specification
Linear Products
PIN CONFIGURATION
DESCRIPTION
FEATURES
The TDA3567 is a monolithic integrated
decoder for the NTSC color television
standards. It combines all functions required for the demodulation of NTSC
signals. Furthermore, it contains a luminance amplifier, and an RGB-matrix and
amplifier. These amplifiers supply output
signals up to 5V p_p (picture information)
enabling direct drive of the discrete output stages.
• Single-chip chroma and
luminance processor
• ACC with peak detector
• DC control settings
• High-level RGB outputs
• Luminance signal with clamp
• Requires few external
components
• On-chip hue control circuit
DETEct8;
CHRO~=g~
2
3
ACC DETECTOR
S/H CAPACITOR
SATURATION
CONTROL
CONTRAST
CONTROL
~~~~~~
7
LUMI~S~ 8
BRlg~~~ 9
APPLICATIONS
• Video monitors and displays
• TV receivers
• Video processing
....1
'---_
R OUTPUT
TOP VIEW
ORDERING INFORMATION
DESCRIPTION
18-Pin Plastic DIP (SOT-l02HE)
February 12, 1987
TEMPERATURE RANGE
-25°C to
ORDER CODE
+65°C
TDA3567N
10-60
853-117887585
Signetics Linear Products
Product Specification
NTSC Color Decoder
TDA3567
BLOCK DIAGRAM
REO OUTPUT
GREEN OUTPUT
BLUE OUTPUT
SANDCASTLE
7
PULSE
1\
TDA3567
15
!330 nF
HUE
B0Q9651S
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
VCC=V1-17
Supply voltage
13.2
V
PTOT
Total power dissipation
1.7
W
TSTG
Storage temperature range
-25 to +150
TA
Operating ambient temperature range
-25 to +65
°C
°C
OJA
Thermal resistance from junction to
ambient (in free-air)
50
°C/W
February 12, 1987
10-61
•
Signetics Unear Products
Product Specification
TDA3567
NTSC Color Decoder
DC AND AC ELECTRICAL CHARACTERISTICS Vee = V1-17 = 12V; TA = 25°C, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
Min
Typ
Max
12
13.2
Supply
VCC=V1-17
Supply voltage
Icc=11
Supply current
PTOT
Total power dissipation
9
V
65
rnA
0.78
W
450
mV
Luminance Input signal
Va-17(p-P)
Input voltage 1 (peak-to-peak value)
Va-17
Input voltage level before clipping occurs in the
Input stage
la
Pin 8
1
Input current
0.15
Contrast control range
17
Input current contrast control
17
Input current when the peak white limiter is
active
R7-17
Input resistance
See Figure 1
-17
For VS- 17 < 6V
0.5
VS- 17 = 2.5V
5.5
VS-17 > 6V
1.4
2
V
1
tJA
+3
dB
15
tJA
mA
2.6
kG
Peaking of luminance signal
IZ13 - 17 1
Output impedance
Pin 13
200
Ratio of internal!external current when Pin 13 is
short-circuited
G
3
Chromlnance amplifier
V3-17(P-P)
Input signal amplitude2 (peak-to-peak value)
V3-17(P-P)
Input signal amplitude before clipping occurs in
the input stage (peak-to-peak value)
Pin 3
550
mV
1.1
V
Minimum burst signal amplitude within the ACC
control range (peak-to-peak)
35
mV
ACC control range
30
dB
AV
Change of the burst signal at the output for the
complete control range
IZ3- 17 1
Input impedance
Pin 3
C3_17
Input capacitance
Pin 3
Saturation control range
15
Input current saturation control
IZ5- 17 1
IZ5 _ 17 1
IZ5 _ 17 1
Input impedance
See Figure 3
6
8
10
kG
4
6
pF
dB
1
20
p.A
V5_17=6V to 10V
1.4
2
2.6
kG
1.4
2
2.6
kG
For V5 - 17 > 10V
0.7
1
1.3
kG
1
2
dB
-50
-46
dB
Input impedance when the color killer is active
Tracking between luminance and chrominance
contrast
dB
50
For V5_17>6V
Input impedance
+1
For 10dB of control
Cross-coupling between luminance and
chrominance amplifier"
Reference part phase-locked loop
Af
Catching range
A
Phase shift for 400Hz deviation of the carrier
frequency
February 12, 1987
±400
10-62
±500
Hz
5
deg
Signetics Linear Products
Product Specification
NTSC Color Decoder
TDA3567
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) vcc = Vl-17 = 12V; TA = 25°C, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
CONDITIONS
Min
Typ
Max
Oscillator
TCosc
Temperature coefficient of oscillator frequency
Ll.fOSC9
Frequency deviation
R16 - 17
Input resistance
Pin 16
C22 - 17
Input capacitance
Pin 16
Ll.Vcc=±10%
260
1.5
2.5
Hz/oC
150
250
Hz
360
460
n
10
pF
ACC generation
V4-17
Voltage at Pin 4 nominal input signal
4
V
V4- 17
Voltage at Pin 4 without burst input
1.9
V
V4- 17
Color-off voltage
2.5
V
V4-17
Color-on voltage
2.8
V
Change in burst amplitude with temperature
0.1
%/oC
Change in burst amplitude with 10% supply
voltage change
0
%N
Voltage at Pin 2 at nominal input signal
5
V
V2- 17
Hue control
Control voltage range
see Figure 4
114
Input current
for V15_17<5V
lz14-171
Input impedance
for V15 _ 17 >5V
1.5
0.5
20
JJA
2.5
3.5
kn
Demodulation part
Ratio of demodulation signals (measured at the
various outputs) 7
V10-17
V12 - 17
(R-Y)/(B-Y); no (R-Y) signal
-0.42
--
(R-Y)/(B-Y); color bar signal
1.4
Vl1 - 17
-
(G-Y)/(R-Y); no (B-Y) signal
-0.25
(G-Y)/ (B-V); no (R-Y) signal
-0.11
V lO _ 17
•
V12 - 17
V12 - 17
Vl1 - 17
-V12-17
o to
Frequency response
0.7MHz
-3
dB
6
V
RGB matrix and amplifier
VlO, 11, 12-17(P-P)
at nominal luminance
input signal and
nominal contrast
(peak-to-peak value)
black-white
Output signal amplitude3
V12 - 17(P-P)
Output signal amplitude of the "blue" channel
VlO, 11, 12-7
Maximum peak-white levels
February 12, 1987
4
at nominal contrast
and saturation
control setting and
no luminance signal
to Ihe inpul (B-Y)
signal (peak-la-peak
value)
3.8
9
10·63
5
9.3
V
9.6
V
Signetics Linear Products
Product Specification
NTSC Color Decoder
TDA3567
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) VCC=Vl_17=12V; TA=25°C, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
CONDITIONS
Min
Typ
Maximum output current
110, 11, 12-17
Difference in the black level between the three
channels
Black level shift with vision content
10
Brightness control voltage range
19
Brightness control input current
VIT
Black level variation with temperature
eN
f!,v
Relative variation in black level between the
three channels
eN
Differential drift of black level over a temperature
range of 40°C
(
VBl
Ll.Vee
600
mV
40
mV
-50
I'A
1
mVloC
75
200
mV
10
%
0
20
mV
0
20
mV
1.95
2.15
2.35
V
1
1.05
1.1
during variations of
contrast (10dB),
brightness (± IV), and
supply voltage
(±10%)
Blanking level at the RGB outputs
Vec
mA
0.15
Black level variation with contrast control
Ll.VBl
10
see Figure 3
Relative spread between the three output signals
VBl
Max
--x--
Tracking of output black levels with supply
voltage
SIN
Signal-to-noise ratio of output signals 5
VR(P-PI
Residual 3.58MHz in RGB outputs (peak-to-peak
value)
50
75
mV
VR(P_PI
Residual 7.1 MHz and higher harmonics in the
RGB outputs (peak-to-peak value)
50
75
mV
50
n
-3
dB
tz10, 11, 12-17
1
62
dB
RGB output impedance
Frequency response of total luminance and RGB
amplifier circuits
o to
5MHz
Sandcastle Input
V7-17
Level at which the RGB blanking is activated
1
1.5
2
V
V7-17
Level at which burst gate clamping pulses are
separated
6.5
7
7.5
V
to
Delay between black level clamping and burst
gating pulse
300
375
450
ns
-1
-40
2
mA
-20
17
17
17
V7_17=0 to tv
V7-17 = 1 to 8.5V
V7 - 17 = 8.5 to 12V
Input currents
IJA
mA
NOTES:
1. Signal with negative-going sync; amplitude includes sync pulse amplitude.
2. Indicated is a signal for color bar with 75% saturation. so the chrominance-to-bursl ratio is 2.2:1.
3. Nominal contrast is specified as maximum contrast -3d8 and nominal saturation as maximum saturation -10dB.
4. Cross-coupling is measured under the following conditions:
• input Signals nominal
• contrast and saturation such that nominal output signals are obtained
• the signals at the output at which no signal should be available must be compared with the nominal output signal at that output.
5. The signal-te-noise ratio is specified as peak-ta-peak signal with respect to RMS noise.
6. When this level is exceeded, the amplifier of the output signal is reduced via a discharge of the capacitor on Pin 7 (contrast control). Discharge
current is 5.SmA.
7. These matrixed values are found by measuring the ratio of the various output signals. The values are derived from the matrix equations given in the
section 'FUNCTIONAL DESCRIPTION'.
February 12, 1987
10-64
Signetics Linear Products
Product Specification
NTSC Color Decoder
FUNCTIONAL DESCRIPTION
Luminance Amplifier
The luminance amplifier is voltage driven and
requires an input signal of 450mVp.p 1. The
luminance delay line must be connected between the IF amplifier and the decoder. The
input signal must be AC coupled to the input
Pin 8.
The black level clamp circuit of the RGB
amplifiers uses the coupling capacitor as a
storage capacitor. After clamping, the signal
is fed to a peaking stage. The RC network
connected to Pin 13 is used to define the
amount of overshoot.
The peaking stage is followed by a contrast
control stage. The control voltage has to be
supplied to Pin 6. The control voltage range is
nominally -17 to + 3dB. The linear curve of
the contrast control voltage is shown in
Figure 1.
Chrominance Amplifier
TDA3567
the small spreads of the IC. The free-running
frequency of the oscillator can be checked by
connecting the saturation control (Pin 5) to
the positive supply line. Then the loop is
opened so that the frequency can be measured. The oscillator has an internal gainlimiting stage which controls the gain to unity,
so that internal signals are sinusoidal. This
prevents the generation of higher harmonics
of the subcarrier signals. The burst signal is
compared to a O· reference signal by the
burst amplitude detector, and is then amplified and fed to a peak detector for ACC and
to a sample-and·hold circuit which drives the
color-killer circuit. The reference signal for the
burst phase detector is provided by the 90·
phase·shifted signal. An RC network is used
to obtain the required catching range and
noise immunity for the output voltage of the
burst phase detector.
The hue control is obtained by mixing oscillator signals with a phase of O· and 90· before
they are fed to the (R-Y) and (B-Y) demodulators. The 90· phase-shifted signal is provided
by a Miller integrator (biased by Pin 18). As
the hue control is independent of the PLL, the
control will react without time delay on the
control voltage changes.
The chrominance amplifier has an asymmetrical input. The input signal at Pin 3 must be AC
coupled, and must have an amplitude of
550mVp.p. The gain control stage has a
control range in excess of 30dB, the maximum input signal should not exceed 1.1Vp_p,
otherwise clipping of the input signal will
occur. From the gain control stage, the chrominance signal is fed to the saturation and
contrast control stages. Chrominance and
luminance control stages are directly coupled
to obtain good tracking. The saturation is
linearly controlled via Pin 5. The control
voltage range is 2V to 4V. The impedance is
high and the saturation control range is in
excess of 50dB. The burst signal is not
affected by contrast or saturation control.
After the amplification and control stages, the
chrominance signal is internally fed to the (RY) and (B-Y) demodulators, burst phase, and
ACC detectors.
The demodulators are driven by the amplified
and controlled chrominance signals; the reference signals are obtained from the hue
control circuit. In nominal hue control position, the phase angle of (R-Y) reference
signal is 0·; the phase angle of the (B·Y)
reference signal is 90·.
OSCillator and ACC Circuit
(B-Y)matrixed = (B-Y)IN
The 3.58MHz reference oscillator operates at
the subcarrier frequency. The crystal must be
connected between Pin 16 and ground. The
oscillator does not require adjustment due to
Demodulator Circuits
For flesh-tone corrections, the demodulated
(R-Y) signal is matrixed with the demodulated
(B·Y) signal according to the following equations:
(R-Y)matrixed = 1.61 (R-Y)IN-0.42 (B-Y)IN
(G-Y)matrixed
= 0.43
(R-Y)IN -0.11 (B·Y)IN
NOTE:
1. Signal with negative-going sync; amplitude includes sync pulse amplitude.
February 12, 1987
10-65
In these equations (R-Y)IN and (B-Y)IN indicate the color difference signal amplitudes
when the chrominance signal is demodulated
with a phase difference between the R-Y and
B-Y demodulator of 90· and a gain ratio B-YI
R-Y= 1.78.
RGB Matrix Circuit and
Amplifiers
The three matrix and amplifier circuits are
identical. The luminance signal and the color
difference signals are added in the matrix
circuit to obtain the color signal.
Output signals are 5Vp.p (black-white) for the
following nominal input signals and control
settings:
• Luminance 450mVp.p
• Chrominance 550mVp.p (burst-tochrominance ratio of the input 1:2.2)
• Contrast -3dB (maximum)
• Saturation -10dB (maximum)
The maximum available output voltage is
approximately 7Vp.p. The black level of the
red channel is compared to a variable external reference level (Pin 9), which provides the
brightness control. The control loop is closed
via the luminance input.
The luminance input is varied to control the
black level control; therefore, the green and
blue outputs will follow any variation of the
red output. The output of the black control
can be varied between 2V to 4V. The corresponding brightness control voltage is shown
in Figure 3.
If the output signal surpasses the level of 9V,
the peak white limiter circuit becomes active
and reduces the output signal via the contrast
control.
Blanking of RGB Signals
A slicing level of about 1.5V is used for this
blanking function, so that the wide part of the
sandcastle pulse is separated from the rest of
the pulse. During blanking, a level of + 2V is
available at the output.
•
Signetics Linear Products
Product Speclflcotlon
NTSC Color Decoder
TDA3567
100
'I,
~
,IfJ
50
'f·
-' /
j,
~
"
100
I.r;r
l'l.
If,
"
I I
Ii," IfI
50
'I.
l/if
1-' r-
~
o I-o
--._,-
'f
!,
o
4
U
o
2
3
V._;7 (V)
VO-l? (V)
4
5
OP18150S
Figure. 1. Contrast Control Voltage Range
Figure 2. Saturation Control Voltage Range
60
40
L... ;;::;
20
...
~~~r
;..::;~
i/
I
k:~c;;.
/
"-
~- f-:::,
-20
/I
-40
-60
1.8
2.2
2.6
3.0
3.4
3.8
4.2
V15- 17 IV)
OPI8t81S
OP1811l1S
Figure 3. Brightness Control Voltage Range
10
R
Figure 4. Hue Control Voltage Range
r-----..,I---""VII'Y---o
9
o------t
BRlGHTlIESS
lk
OUTPUT G
f!j,~~IIINANCE
11
o------f
100nF
~....r-I\... SANDCASTLE
PULSE
12
B o-------~-t
t----""'_-o
t----""'--o
6
CONTRAST
SATURAT10N
~glF-=-
HUE 0 -_ _ _ _ _~15_t
~I
-i~DF
CHROIlINANCE
10nFL.......f~
3.58 11Hz
17
~~-=2.2,.F
r-___
-=-
ill~~18_t
~1~_ _ _ _~V~
10nF ' -_______..1
Figure 5. Application Diagram
February 12, 1987
10-66
TDA4555/56
Signetics
Multistandard Color Decoder
Product Specification
Linear Products
DESCRIPTION
The TDA4555 and TDA4556 are monolithic, integrated, multi standard color decoders for the PAL@, SECAM, NTSC
3.58MHz and NTSC 4.43MHz standards.
The difference between the TDA4555
and the TDA4556 is the polarity of the
color difference output signals (B-Y) and
(R-Y).
FEATURES
Chrominance Part
.. Gain-controlled chrominance
amplifier for PAL, SECAM, and
NTSC
• ACC rectifier circuits (PALINTSC,
SECAM)
.. Burst blanking (PAL) in front of
641-'s glass delay line
II Chrominance output stage for
driving the 641-'s glass delay line
(PAL, SECAM)
,. Limiter stages for direct and
delayed SECAM signal
• SECAM permutator
Demodulator Part
• Flyback blanking incorporated in
the two synchronous
demodulators (PAL, NTSC)
G PAL switch
G Internal PAL matrix
.. Two quadrature demodulators
with external reference-tuned
circuits (SECAM)
• Internal filtering of residual
carrier
• De-emphasis (SECAM)
• Insertion of reference voltages
as achromatic value (SECAM) in
the (B-Y) and (R-Y) color
difference output stages
(blanking)
Identification Part
• Automatic standard recognition
by sequential inquiry
• Delay for color-on and scanningon
• Reliable SECAM identification by
PAL priority circuit
• Forced switch-on of a standard
• Four switching voltages for
chrominance filters, traps, and
crystals
• Two identification circuits for
PAL/SECAM (H/2) and NTSC
• PAL/SECAM flip-flop
• SECAM identification mode
switch (horizontal, vertical, or
combined horizontal and vertical)
• Crystal OSCillator with divider
stages and PLL circuitry (PAL,
NTSC) for double color
subcarrier frequency
PIN CONFIGURATION
(R-Y)OUT
1
SEC~~E~P~
2
(B-V) OUT
3
SECA~~~ 4
SEC~~F(g-Jt 5
SEC~~E~~
6
SEC::'F(~U'1
7
SECA~~~-~ 8
GND
21 PALtSECAM 10
9
20 NTSC 10
DELAVS~~OL~~
10
19
DEJ;~~~
11
18
~~~~~~
12
17
~~~SJ~~
~~~OlOSC
~M~vTg~~T~H
15
~'~~~~~N
OUT
Vee 13
~~~~&l ~3~
14
L....-._....
TOP VIEW
•
• HUE control (NTSC)
.. Service switch
APPLICATIONS
• Video monitors
• Video processing
• TV receivers
ORDERING INFORMATION
DESCRIPTION
28·Pin Plastic DIP (80T-117)
TEMPERATURE RANGE
o to
ORDER CODE
+70·C
TDA4555N
PAL® is a registered trademark of Monolithic Memories, Inc.
February 12, 1987
10-67
853-1188 87586
s:
c
L5
I .....
:::;:
~
::J
en
.0
::J
~
!fi
a.
o
a
()
o
....o
o
CHROIINANCE INPUT
10TO~Vp.p
COIFOSITE
VIDEO
INPUT
IV (p-p)
CD
o
o
TDA4555 - (A-V)
TDA4550 + (R-V)
a.
CD
....
l.osv...
COLOR
DIFFERENCE
OllTPlITS
.....
'?
0)
1.33Vp..p
TDA4555 - (II-V)
TDA4858 + (B-Y)
ex>
.....
(A) COLOR ON; HUE OFF
(e) COLOR ON; BURST OFF
+IZV
~
(TI
(TI
01
0.
~
[
en
~
a
ci"
::J
Product Specification
Signetics linear Products
Multistandard Color Decoder
TDA4555j56
ABSOLUTE MAXIMUM RATINGS
SYMBOL
Vce
= V13-9
PARAMETER
RATING
UNIT
13.2
V
o to Vee
V
Supply voltage (Pin 13)
Vn _ 9
Voltage range at Pins 10, 11, 17, 23,
24, 25, 26, 27, 28, to Pin 9 (ground)
112
Current at Pin 12
8
mA
112M
Peak value
15
mA
PTOT
Total power dissipation
1.4
W
TSTG
Storage temperature range
-65 to +150
°C
TA
Operating ambient temperature range
o to +70
°C
DC AND AC ELECTRICAL CHARACTERISTICS Vee = V13-9 = 12V; TA = 25°C; measured in Block Diagram, unless
otherwise specified.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
Supply (Pin 13)
Vee = V13 - 9
Supply voltage range
lee = 113
Supply current
10.8
13.2
65
V
mA
Chromlnance part
V15-9(P.P)
1Z15-91
Chrominance input signal (Pin 15)
input voltage with 75% color bar signal (peak-to-peak value)
input impedance
V12-9(P.P)
I Z12-91
V12-9
Chrominance output signal (Pin 12)
output voltage (peak-to-peak value)
output impedance (NPN emitter-follower)
DC output voltage
110
R10-9
Input for delayed signal (Pin 10)
DC input current
input resistance
20
2.3
100
3.3
200
mV
kSl.
20
SI.
1.6
V
8.2
V
10
f,1A
kSl.
10
Demodulator part (PALINTSC)
1.05V ±2dB
1.33V ±2dB
V
V
V1-9(P.P)
V3-9(P.P)
Color difference output signals output voltage
(proportional to V13 -9) (peak-to-peak value)
TDA4555
- (R-Y) signal (Pin 1)
- (B-Y) signal (Pin 3)
TDA4556
+ (R-Y) signal (Pin 1)
+ (B-Y) signal (Pin 3)
1.05V ±2dB
1.33V ±2dB
V
V
V1/3 -9
Ratio of color difference output signals (R-Y)/(B-Y)
0.79 ± 10%
V1,3-9(P.P)
Residual carrier (subcarrier frequency)
(peak-to·peak value)
V1 -9(P·P)
V3_9(P.P)
30
V1,3-9(P.P)
Residual carrier (PAL only) (peak-to-peak value)
V1 _ 9(P_P)
H/2 ripple at (R-Y) output (Pin 1)
(peak-to-peak value) without input signal
V1,3-9
IZ1,3-91
February 12, 1987
DC output voltage NPN emitter-follower with
internal current source of 0.3mA
output impedance
10-69
mV
mV
10
10
mV
150
SI.
7.7
V
•
Signetics Linear Products
Product Specification
Multistandard Color Decoder
TDA4555j56
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) VCC=V13_9=12V; TA=25°C; measured in Block
Diagram, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
Demodulator part (SECAM)
Vl-9(P-P)
V3-9(P_P)
Vl-9(P-P)
V3-9(P_P)
Color difference signals1 output voltage (proportional to V13-9)
(peak-to-peak value)
TDA4555
- (A-Yj signal (Pin 1)
- (B-Y) signal (Pin 3)
TDA4556
+ (A-Y) signal (Pin 1)
+ (B-Y) signal (Pin 3)
1.05
1.33
V
V
1.05
1.33
V
V
0.792 ± 10%
V1I3-9
Aatio of color difference output signals (A-Yj/(B-Y)
Vl,3-9(P.P)
Aesidual carrier (4 to 5MHz) (peak-to-peak value)
20
30
mV
Vl.3-9(P-P)
Aesidual carrier (8 to 10MHz) (peak-to-peak value)
20
30
mV
Vl.3-9(P-P)
H/2 ripple at (A-Y) (B-Y) outputs (Pins 1 and 3)
(peak-to-peak value) with fo signals
20
mV
Vl.3-9
DC output voltage
tJ>
+tJ>
Phase shift of reference carrier
at V17_9=2V
at V17_9=3V
at V17_9=4V
A17 - 9
Input resistance
Service position
V17-9
V17_9
Switching voltage (Pin 17)
burst OFF; color ON (for oscillator adjustment)
Hue control OFF; color ON (for forced color ON)
0.5
6
V
V
Crystal oscillator (Pin 19)
A19-9
;.r,-
C
(II-V)
22pF
c:
3:
SECAII REFERENCE
::J
Co
C
a
Uk
COLOR DIFFERENCE
OUTPUTS
lDA4555: - (II-V)
lDA4555: - (A-V)
TDA4558: + ell-V)
TDA4556: + (....Y)
c
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IDENTIFtcAT10N
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.
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CHROMINANCE
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FIgure 1. AppllcaUon DIagram
~
AN1551
Signetics
Single-Chip Multistandard
Color Decoder TDA4555/
TDA4556
Linear Products
Application Note
In areas where 1V transmissions to more
than one color standard can be received,
color receivers are required which can handle
multistandard transmissions without additional manual switching. This requirement will
greatly increase with the introduction of satellite 1V.
difference Signals -(R-Y) and -(B-Y) and the
luminance signal (Y) into the RGB signals.
The TDA3505 also incorporates the saturation, contrast, and brightness control circuits
and allows for the insertion of external RGB
signals. Finally, the processed video signals
are applied, via the RGB output stage, to the
picture tube.
a common chassis. Automatic selection of
the required standard has been made more
reliable and the maximum time required for
identification and switching is a little over half
a second.
When reception is difficult because signals
are weak, noisy, or badly distorted, the automatic standard recognition (ASR) can be
switched off and the standard chosen manually.
Such receivers have, in the past, incorporated
a multi standard color decoder (MSD) using
several integrated circuits to automatically
select the standard of the received signal.
However, the growing need for these MSDs
makes it economically and technically desirable to incorporate all the active parts in one
IC and to reduce, as far as possible, the
external circuitry.
The new MSD can decode color 1V signals
transmitted according to the following standards:
Although the ICs are capable of processing
multi standard signals, their performance is as
high as that for single-standard decoders.
1. NTSC standards with any color subcarrier
frequency, for example:
- NTSC-M (fa = 3.579545MHz), referred to
as NTSC-3.5.
Figure 1 is a block diagram of a typical
multi standard color decoder incorporating the
TDA4555.
This publication describes two new singlechip MSDs using bipolar technology, the
TDA4555 and TDA4556. The ICs are similar
except for the polarity of the color difference
signals at the output. The TDA4555 provides
-(R-Y) and -(B-Y) signals; the TDA4556
provides + (R-Y) and + (B-Y) signals. Only the
TDA4555 will be described.
- Non-standard NTSC systems, for example
with fa = fOPAl = 4.43361 MHz.
This is a de facto standard used for VCR
signals in some European communities and
the Middle East, and is referred to as NTSC
4.43. As the color subcarrier frequency is
the same as that of the normal PAL system, the same crystal can be used without
switching in the reference oscillator for
both systems.
The composite video input signal (CVBS) is
fed via switchable filters to the input of the
MSD. The filters separate the chrominance
and luminance Signals according to the standard selected and are controlled by the ASR
circuit within the TDA4555.
Since all the active parts of the MSD are in a
single IC, the design and layout of the printed
circuit board is considerably simplified and
assembly cost is reduced. The greater reliability of "wiring on silicon" increases the
overall reliability of the decoder and reduction
of external circuitry simplifies assembly.
Chrominance signals from the filters are AC
coupled to the input of the TDA4555, which
produces the color difference outputs that
are, in turn, AC coupled to the Color Transient
Improvement (CTI) TDA4565. This IC also
contains an adjustable luminance delay-line
(Y) formed by gyrators, so a conventional
wirewound delay line is not needed.
The ICs are universally applicable and allow
the design of a range of 1V receivers having
The signals are then fed to the Video Combination IC, TDA3505, which converts the color
RGB -
2. PAL standard, characterized by phase reversal of the (R-Y) signal on alternate scan
lines. The color subcarrier frequency for
normal PAL is 4.43361875MHz.
3. SECAM, characterized by transmission of
the color difference signals (R-Y) and (B-Y)
on alternate scan lines and frequency mod-
SIGNAL INPUTS
~"
"-1
G
SWITCHING VOLTAGES
B
f--G
----l
--l
~B
FSW1
FSW2
VIDEO
FINAL STAGES
eVBS
SWITCHABLE
CHROMA FILTERS
AND
C
VIOEO
COMBINATION
G
TOA458O
CHROMA TRAPS
PAL
NTSC
SATURATION
l
L'
DARK CURRENT
SANDCASTLE PULSE
CONTRAST
BRIGHTNESS
Figure 1. Block Diagram of a Color Decoder
February 1987
10-73
II
Signetics Linear Products
Application Note
Single-Chip Multistandard
Color Decoder TDA4555/TDA4556
ulation of the color subcarriers. The frequency of the color signals may vary between 3.900MHz and 4.756MHz. The frequencies of the color subcarriers are:
fOB = 4.250MHz for a "blue line"
fOR = 4.40625MHz for a "red line".
With these capabilities, the new decoders can
handle most of the color TV transmissions
used in the world.
DESIGN CONSIDERATIONS
To minimize the number of integrated components and reduce the required crystal area
and power dissipation of the MSD, the same
sections of the IC are used, where possible,
for several standards. For example:
• the gain-controlled input stages
• the common switching pulse generators
• the PAL and NTSC quadrature
demodulators and oscillators
• the PAL and SECAM delay line
• the common driver stage preceding the
delay lines
• part of the stage following the delay
line and the demodulator
The number of connections are kept to a
minimum compatible with the required functions. With the new ICs, the reference oscillator, its filter, and the SECAM identification
circuit, each require only a single pin. The
sandcastle pulse is the only external pulse
signal. These, and other measures, allow the
TDA4555 chip to be housed in a 28-lead
SO-117 encapsulation, despite the many
functions it performs.
There are three alternative approaches to
multi-standard color decoder design.
1. Separate parallel-connected decoders
for each standard with the appropriate
output selected by switching. This is the
principle used in the three-standard decoder comprised of the TDA3510 for
PAL, TDA3520 for SECAM, and
TDA3570 for NTSC. The color ON/OFF
switch voltages generated in each decoder are used for automatic switching of
the standards, and each decoder has to
be kept at least partially activated.
2. A single PAL decoder can be switched to
handle NTSC signals. SECAM signals are
converted into quasi-PAL signals by a
SECAM-PAL transcoder. The PAL decoder derives the color-difference signals
from this quasi-PAL signal. An example
of this approach is the circuit using the
single-chip PAL decoder TDA3562A with
NTSC option and one of the SECAM
circuits, TDA3590, TDA3590A, or
TDA3591.
3. The methods described in 1 and 2 are
not suited to a single-chip MSD because
February 1987
AN1551
the multiple use of circuit blocks is limited. A much better usage can be obtained
if the standards are scanned sequentially. In this approach, the decoder circuit,
including the filters at the input, is
switched to decode each standard in
turn. The switching continues until the
standard recognition circuit (SRC) indicates that the standard of the received
signal corresponds to the standard of
decoding selected at that moment. The
scanning procedure is restarted if the
standard of the input signal changes
because of tuning to another transmitter
or switching to an external signal source.
The same thing applie~ if the signal
temporarily becomes too weak or disappears. A major advantage of sequential
standard switching is that it allows the
complete decoder, including the external
filters at its input, to be optimized for
each standard. This is why the TDA4555
and TDA4556 are designed in this manner.
TDA4555 CIRCUIT
DESCRIPTION
Figure 2 is the circuit of a multi standard color
decoder using TDA4555/TDA4556.
Pulse Generation
The IC only requires a single sandcastle pulse
at Pin 24 for the generation of all internal
pulses (e.g., burst key, horizontal, and vertical
blanking pulses). The sandcastle pulse levels
are > 8V for the burst key, 4.5V for horizontal
blanking, and 2.5V for vertical blanking.
Level detectors in the sandcastle pulse detector separate the three levels which are
used to generate the required key pulse and
clamp pulses.
Standard Control Circuit
A special System Control and Standard Scanning circuit (SCSS) provides the 4 switching
voltages to set the MSD to the desired
standard.
As long as no color standard is recognized,
the SCSS circuit switches the decoder sequentially to the PAL, SECAM, NTSC-3.58
and NTSC-4.43 standards. If the standard of
the received signal is not recognized after
four field periods (80ms), the next decoding
system is activated. This time interval, also
called the standard scanning period, is a
good compromise between fast switch-on of
the color, and effective interference suppression with noisy signals. The maximum time
between the start of scanning and switching
on the color is 360ms, including the color
switch-on delay of two field periods. However,
in the TDA4555, a PAL priority circuit is
incorporated to improve the reliability for
10-74
SECAM, so the scanning can last for another
two scanning periods (520ms maximum).
After recognition of a SECAM signal, the
information is stored and the decoding is
switched to PAL. A second SECAM recognition is only provided if no PAL recognition
occurs. This gives reliable SECAM recognition when the SECAM-PAL transcoding at the
source (e.g., in cable systems) is not perfect,
or when PAL signals are distorted by reflections so that they simulate SECAM signals.
With b/w signals, the scanning is continuous
and the color is kept switched off because
there is no standard recognition.
The switching voltage corresponding to the
recognized standard ramps from 2.5V to 6V
during scanning while the remaining switching
voltages are held at O.5V maximum.
These 4 voltages are used to switch the filters
at the inputs, the crystals of the reference
oscillators, and the color subcarrier traps, and
also to indicate the recognized standard (e.g.,
by LEDs).
To prevent unnecessary restarting of scanning because of momentary disturbances
(e.g., short-term interruptions of the color
signal), the TDA4555 incorporates a delay of
two field periods (40ms) before scanning can
start.
Finally, the IC allows the automatic standard
recognition (ASR) to be switched off by forcing one of the decoding modes by applying at
least 9V to Pin 28 for PAL; Pin 27 for SECAM;
Pin 26 for NTSC-3.58; and Pin 25 for NTSC4.43. These pins also serve as outputs for the
internally-generated switch voltages which indicate the selected standard.
Color Signal Control
The MSD must provide color-difference output signals with an amplitude referred to a
given test signal, despite amplitude variations
(within limits) of the color input Signal. This is
required to maintain a fixed amplitude relationship between the luminance signal (Y)
and the color-difference signals, independent
of different IF filters or receiver detuning. The
TDA4555/56 incorporates an Automatic Color Control circuit (ACC) for this purpose.
In the case of PAL and NTSC, the reference
for the control is the burst amplitude. For
SECAM, the complete color signal is used.
The color signal is AC-coupled, via Pin 15, to
a gain-controlled amplifier and the control
voltage is obtained by in-phase synchronous
demodulation of the burst or the color Signal.
This approach has the advantage that the
same demodulator, having only one external
capacitor at Pin 16, can be used for all
standards and also results in noise reduction
with noisy signals. Unwanted increase of
saturation with noisy signals (color bright-up
Signetics Linear Products
Application Note
Single-Chip Multistandard
Color Decoder TDA4555/TDA4556
effect) is prevented without an extra peak
detector being required.
In-phase synchronous demodulation has the
advantage that it is independent of synchronization and the state of the decoder, so the
color gain can settle quickly and the color
standard scanning period is therefore short.
Special low-distortion symmetrical circuits
were chosen for the gain-control stage and
the following amplifier stage so that H/2
components in the color-difference channel
are reduced as far as possible during SECAM
reception. Biasing of the color gain-control
stage is stabilized by a DC feedback loop
decoupled by an external capacitor at Pin 14.
The nominal amplitude of the color input
signal at Pin 15 is 1OOmVp_p for a 75% colorbar signal. It may vary between 10mVp.p and
200mVp.p. This range is chosen so that, for a
normal 1Vp_p composite video signal at the
input to the filters, transformation is not required.
For PAL and NTSC decoding, the amplitudecontrolled color signal, including its burst, is
then fed to the SRC, reference generation,
and burst blanking stages. The output of the
latter stage is applied to the color signal
demodulators and the delay-line driver stage.
Standard Recognition Circuit
The SRC tells the SCSS whether the activated decoding mode is the same as that of the
incoming signal. This task is performed using
the signals occurring during the back porch of
horizontal blanking.
For SECAM, it is necessary to distinguish
between line (H) identification signals of carrier frequency at the back porch and field (V)
identification (special lines carrying identification signals during the field blanking period).
The standard recognition comprises the following parts: a phase discriminator which
compares the burst phase of PAL and NTSC
signals with the internal reference signal, a
frequency discriminator for generating an H/2
signal during SECAM reception, an H/2 demodulator for PAL and SECAM signals, and
the logic circuits for the final recognition.
The two phase discriminators for PAL and
NTSC signals are supplied with the color
signal, and the amplitude-controlled burst.
The phase detector for the PAL signals uses
the (R-Y) reference signal for the phase
comparison; the NTSC phase detector uses
the (B-Y) reference signal. Both reference
signals are generated by dividing the reference oscillator output. When the correct signals are received, the phase discriminators
output the demodulated burst signal for standard recognition.
The discriminator for generating the H/2
signal comprises an internal phase discrimiFebruary 1987
AN1551
nator and an external phase-shift circuit,
known as the SECAM identification reference, connected to Pin 22.
The polarity of the PAL and SECAM phase
discriminator output signals is reversed
line-sequentially. With PAL, this is caused by
a change of phase of the burst at linefrequency. With SECAM, it is the result of the
color subcarrier frequency changing at line
frequency.
Since the signal is changing polarity, it is of no
use for the following circuitry. Therefore, the
discriminator output signals are fed to the
H/2 demodulator which line-sequentially reverses the signal polarity. The pulses are then
integrated by external capacitors connected
to Pin 21 (PAL and SECAM discriminator
output) and to Pin 20 (NTSC phase discriminator output). The voltages on these capacitors are the identification signals which are
used by the comparator and logic circuits to
derive the control signals. They are dependent on the standard of the incoming signal
and on the activated decoding standard and
are composed of an internal biasing at half
the supply voltage (6V) and a contribution
from the identification signal. In the following
explanation, only the latter part tJ.V20 and
tJ.V21 is considered.
a. When the decoder is set to PAL, the
frequency of the reference signal is about
4.43MHz. The NTSC discriminator is
switched off and the voltage at C20 is only
the bias voltage. The H/2 demodulator is
therefore driven by the output of the PAL
discriminator. The output of the SECAM
discriminator is not used. With a PAL signal
at the input, the H/2 demodulator delivers
pulses with equal polarity so that capacitor
C21 is charged to tJ.V 21 if the reference
oscillator is correctly locked.
With an NTSC-4.43 input signal, the H/2
modulator provides no pulses or, in case of
phase faults, small pulses with a linesequentially changing polarity. The latter is
caused by the constant burst phase of
NTSC signals which is line-sequentially
reversed by the H/2 demodulator. The
average charge current of C21 is, therefore,
zero, and the capacitor voltage equals the
biasing voltage.
When a SECAM or NTSC-3.58 signal is
received, the difference between the burst
and fa frequency is so large that the phase
changes very rapidly and, as a result, the
H/2 pulses are irregular. This causes the
average charge current of C21 to be zero.
b. When the decoder is set to NTSC-4.43, the
PAL and NTSC-4.4 phase discriminator is
activated and the SECAM frequency discriminator is switched off. The PAL phase
10-75
discriminator and the H/2 demodulator operate as previously described.
With an NTSC-4.43 signal at the input, the
output of the NTSC phase discriminator
consists of pulses with the same polarity
because the burst of the NTSC signal and
the reference signal (B-Y) have the same
phase.
With a PAL input signal, the NTSC phase
discriminator also outputs pulses with the
same polarity, because the PAL burst comprises a component which is stable in the
negative (B-Y) direction for each line. Capacitor C20 at the output of the NTSC
phase discriminator is therefore charged by
an NTSC-4.43, as well as a PAL, input
signal, although the decoder is set to the
NTSC-4.43 mode.
With NTSC-3.58 and SECAM signals, the
average output current of the NTSC phase
discriminator is zero (tJ.V20 = 0) because
the frequency of the burst of the carrier
frequency does not match that of the
reference.
c. When the decoder is set to NTSC-3.58, the
oscillator circuit (including dividers) generates reference signals of about 3.58MHz
and the SECAM frequency discriminator is
switched off. The NTSC-3.58 phase discriminator provides demodulated burst pulses with constant polarity. At the H/2
demodulator output, no pulses, or, in case
of phase faults, small pulses with alternating polarity, appear as in the NTSC-4.43
mode.
For all other color input signals (PAL,
SECAM, NTSC-4.43), the large difference
between burst or carrier frequency and
reference signal frequency prevents defined discriminator output pulses. As a
result, the average charge currents of capaCitor C20 and C21 are zero.
d. When decoding SECAM, the H/2 demodulator obtains its signals from the SECAM
discriminator. The output of the PAL phase
discriminator is not used and the NTSC
phase discriminator is switched off so no
output signal is available (tJ.V20 = 0).
For SECAM decoding, a frequency discriminator in the recognition block is active. H/2
pulses with line-alternating polarity occur
when the frequency of the applied signal is
alternately higher and lower than the resonant frequency fRES of the SECAM identification circuit.
fRES
= (fOB + fOR)/2==4.43MHz
Therefore, the output of the H/2 demodulator is a train of equal polarity pulses charging the capacitor C21 . For PAL, NTSC-3.58
and NTSC-4.43 signals, the burst frequency is constant so the output of the frequen-
•
Application Note
Signetics Linear Products
Single-Chip Multistandard
Color Decoder TDA4555 jTDA4556
AN1551
l5
10"H
SECA'"
IDENTlACATION
REFERENCE
IDENTIFICATION
SECAM
SELECTION
6V = HORIZONTAL
+ VERTICAL
12V VERTICAl.
fl-~
L7
10J..(H
=
CHROMiNANCE INPUT
10 TO 200mVp..p
EnF
lnF
14
23
11k
120pF
~nF EnF
22
21
1
TOA4555 - (R-V)
TOA4556 + (R.Y)
1.0SVp.p
COLOR
DIFFERENCE
OUTPUTS
l.33Vp.p
TDA4555 - (B-Y)
T0A4556 + (S-V)
SE;~ ......H+-'::I-"-1+-l
:~~::~
[
(
~
TDA4555
TDA4556
lOV S'MTCHING
VOLTAGE FOR
FORCED
STANDARD
SEmNG
INDICATION OF
SELECTED
STANDARD
17
3.3k
24
6.ak
''''
10k
HUE
NTSC
3.58MHz
PAL
NTSC
4.43MHz
+12V
SERVICE
SWITCH
It
A-
ay
__ -===-2:5V 4.SV
INPUT
-OV
SANDCASTLE
PULSE
(A) COLOR ON; HUE OFF
(e) COLOA ON; BURST OFF
+6Y
Figure 2. Block Diagram and Peripheral Circuitry
cy discriminator consists of unipolar pulses
and the H/2 demodulator outputs alternating polarity pulses. The average charge
current of capacitor C21 is therefore zero
(lN21 =0).
The TDA4555 is designed so that identification of SECAM Signals can be performed as
required by using the special signals in each
field blanking period (V-identification) or the
February 1987
burst signal at the back porch (H-identification), or both signals at the same time (H + Vident). The required standard is selected by
applying the appropriate voltage to Pin 23 as
follows:
V23
< 2V
V23
> 10V
(e.g., ground), H-identification
(e.g., VSUPPLY), V-identification
V23 = SV or floating, H + V-identification.
10-76
V-identification is more reliable than the Hidentification because the identification signals are longer and have a greater frequency
deviation (Ll.f',B = 3.9MHz; Ll.f',R = 4.75SMHz).
With H-identification, only the normal carrier
signal at the end of the back porch is available for identification. When it is required to
transmit other information during the fieldblanking period, several transmitters (e.g.,in
France) stop transmitting the V-identification
Signetics Linear Products
Application Note
Single-Chip Multistandard
Color Decoder TDA4555/TDA4556
signals. However, the TDA4555 can easily be
adapted to such system changes.
AN1551
The two crystals for the reference oscillator
are both connected between Pin 19 and
ground via a switch circuit comprising two
transistors driven by the external standard
switch voltages. To prevent interference, the
oscillator is switched off during SECAM decoding.
Table 1 summarizes the foregoing. For b/w
signals, the average charge current is zero,
so no standard is recognized and the scanning is continuous.
Generation of PAL and NTSC
Reference Signals
Color Signal Demodulators
Demodulation of the color signals is performed in the same way as in single standard
predecessors.
For demodulation and identification of the
quadrature amplitude-modulated PAL and
NTSC color signals, the reference signals
Ref(R-Y) and Ref(B-Y) are needed. These
signals are derived from the transmitted burst
by a PLL which comprises a voltage-controlled oscillator (VCO), a 2:1 frequency divider, and a phase discriminator. The oscillator
frequency is twice the subcarrier frequency
(2fo) and the circuit has the advantage that
the two quadrature reference signals are
available at the output of the divider.
In the PAL decoding mode, the burst signal is
removed from the color signal derived from
the gain-controlled chroma amplifier to prevent disturbances caused by reflections in the
glass delay-line delayed by other than a
single line period. The color signal is applied
to an 18dB amplifier and driver stage (emitterfollower) which compensate for the "worstcase" loss in the external delay-line circuit.
Color subcarrier signals CSCR.Y and CSCs.y
are separated by the delay line connected to
Pin 12 and terminated at both input and
output. Direct and delayed signals are
matched by a potentiometer in the output
termination. Phase matching can be obtained
with coils L5 and Ls, which compensate the
delay-line capacitances.
With PAL and NTSC, the phase discriminator
compares the (R-Y) reference signal and the
burst. The burst and the color signal obtained
from the ACC stage are applied to the discriminator directly for PAL and via the hue
control for NTSC. In the hue control block,
the phase of the burst signal can be shifted
± 30° by an external voltage of between 2V
and 4V at Pin 17. This voltage is derived from
the supply by a simple resistor network. Pin
17 also receives the voltage from the "service" switch. If V17 is less than 1V (e.g.,
ground), the color is forced ON and the
oscillator free runs because the burst is
switched OFF. The oscillator frequency can
be adjusted with the trimmers in series with
the crystals. If V17 is greater than 6V (e.g., the
supply voltage), the color is forced ON and
the hue control is switched OFF.
The delayed signal is taken from the potentiometer slider and fed to the internal matrix via
Pin 10, where the direct and delayed signal
are added and subtracted to obtain the separated color subcarriers CSCR.Y and CSCs_Y.
The matrixing is very simple because the
demodulators have symmetrical differential
inputs and the direct color signal is available
in both polarities. Signals of one polarity are
applied to one of the (B-Y) demodulator
inputs, and signals of the other polarity to one
of the (R-Y) demodulator inputs. The remaining input of both demodulators is supplied
with the delayed signal. Unlike previous PAL
decoders, the PAL switch is located just in
front of the (R-Y) demodulator, i.e., in the
CSCR_Y signal path.
The phase discriminator, which provides a
VCO control voltage which depends on the
phase difference between burst and reference signal, is activated by a burst key pulse.
The control voltage is filtered by an external
second-order, low-pass filter connected to
Pin 18.
The actual color signal demodulators are
conventional synchronous types comprising
an analog multiplying differential stage with a
current source in the emitter circuit and balanced, cross-coupled switching stages in the
collector circuit. The latter are driven by
reference signals Ref(R-Y) or Ref(B-Y) and
one or both analog inputs receive the color
signal CSC(R.Y) or CSC(S_y). The color-difference signals CD, obtained after demodulation, are blanked during the line blanking
interval to provide signals with clean levels.
For NTSC decoding, the color signal is demodulated in a similar manner except that
only the direct (undelayed) signal is used. The
PAL switch in the CSC(R.Y) path is not used.
For reception of the line sequential SECAM
color signals, a parallel-crossover switch
(" permutator") is required before the demodulators. This permutator alternately feeds
both demodulators with a direct and (via the
external delay line) a delayed color signal of
the same subcarrier frequency.
After the permutator, both color channels
incorporate a limiter stage to eliminate amplitude modulation. The color signals are demodulated by quadrature demodulators, each
comprising an internal multiplier and an external single-tuned phase-shift circuit, known as
the SECAM reference circuit. These reference circuits, connected to Pins 5.6 and 7.8,
cause a phase shift of about 90° for the
unmodulated subcarrier frequency. Thus, for
unmodulated subcarrier signals, there is no
output apart from the biasing voltage. The
SECAM reference circuits are adjusted by La
and Lg so that the reference levels appear at
the CD outputs when the subcarrier is unmodulated or when the color is switched off.
In each color-difference channel, the demodulators are followed by internal low-pass deemphasis networks which remove the unwanted high-frequency components (harmonics of reference and color signals).
The color-difference signals pass, via the
output emitter-followers with current sources
Table 1. Charge on Storage CapaCitors C20 and C2 1 for Combinations of Input Signals
and Decoding Mode
STANDARD OF THE COLOR INPUT SIGNAL
DECODING
MODE
PAL
NTSC-4.43
NTSC-3.58
SECAM
PAL
NTSC-4.433
NTSC-3.588
SECAM
B/W
C 20
C 21
C20
C 21
C 20
C 21
C20
C21
C 20
C21
O·
O·
0
0
0
O·
0
0
0
0
o·
0
O·
0
0
0
0
o·
+
+
+
0
0
0
0
0
0
0
0
0
0
0
+
0
+
O·
0
0
O·
+
NOTES:
o average charge current IAV ~ 0, flVc ~ 0, Vc ~
h
supply
average charge current IAV > 0, ~VC > 0 (assuming correct locking of the reference oscillator and proper switching of the H/2 demodulators)
... NTSC phase discriminators switched off
+
February 1987
10-77
•
Signetics Linear Products
Application Note
Single-Chip Multistandard
Color Decoder TDA4555/TDA4556
AN1551
3x2N3904
(6)
CHROMA
OUTPlIT
2.2k
"::"
PAL
(::\
1(15)
SECAM
~6)
NTSC3.58
(17)
NTSC4.43
(18)
STANDARD
SWITCHING
VOLTAGES
~
Y.PALINTSC
3)(15k
27pF \
68
4x2N3904
560
V-SIGNAL
SWITCHING
STAGES
SECAM
BELL ALTER
(10)
'--.....- .....--t-- V-SlGNAL
MONOCHROME
22k
22k
(5,7,9,11,12)
NUMBERS IN PARENTHESES ARETHE CONNECTION NR. OFTHE PC BOARD.
Figure 3. Input Filters and Standard Switching
in their emitter circuits, to Pins 1 and 3, no
matter what decoding mode is selected. They
have the following nominal amplitudes referred to a 7S% saturated color bar:
V(R.Y)
= 1.0SVp_p; V(S_V) = 1.33Vp_p.
For the TDA4555, the polarity of the signals is
negative and therefore suitable for input to
the video combination family TDA3500 (except TDA3506).
The TDA4556 is similar to the TDA4555
except for the positive polarity of the
TDA4556 color difference output signals.
February 19B7
Therefore, this TDA4556 can be used with
the Video Combination TDA3506.
APPLICATION
CONSIDERATIONS
Circuit Example
Figure 2 is a tested circuit of a multistandard
decoder. A more detailed circuit of the input
filters is shown in Figure 3. These filters
separate the luminance signal (Y) from the
color signals for the four decoding modes.
10-78
The same filters can be used for PAL and
NTSC-4.43 signals since they have a similar
frequency spectrum. For SECAM signals, it is
possible to use the 4.43MHz subcarrier trap
of the PALINTSC-4.43 filter, but it is then
necessary to add a trap tuned to about
4.05MHz in the Y channel. This filter suppresses the color signal components below
about 4.2MHz, which mainly occur during the
"blue SECAM line".
The filter circuits for PAL and NTSC signals
are based on a separation filter which also
equalizes phase delay. This means that, be-
Application Note
Signetics Linear Products
Single-Chip Multistandard
Color Decoder TDA4555/TDA4556
AN1551
Table 2. Coil Data for the Multistandard Decoder of Figure 2 and Figure 3
COIL NO
INDUCTANCE
(IlH)
Q
TOKO TYPE NO. 1
NO. OF
TURNS
COLOR
USE
FIGURE
L1 /L1a
5.5
> 90
(4.43MHz)
119 LNS-A 4449 AH
8+8
Yellow
Separation filter
3
L2/LK
L2a/LKa
12.5
> 90
(4.43MHz)
119 LNS-A 4451 DY
24/1
Green
Color bandpass
filter
3
L3
L3a
66
60
(2.52MHz)
KANS-K 4087 HU
19 + 46
Violet
Phase delay
correction
3
L4
3.8
60
(4.43MHz)
113 CNS-2 K 843 EG
17
(= 14 +3)
Red
Bell filter
3
Ls, L6, L7
10
> 80
(4.43MHz)
119 LN-A 3753 GO
11 + 11
Blue
Decoder board
and SECAM trap
for fOB
2
L10
10
> 80
(4.43MHz)
119 LN-A 3753 GO
11 + 11
Blue
PAL/NTSC trap
3
La, Lg
12
> 80
119 LN-A 3753 GO
12 + 12
Blue
Decoder board
2
NOTE:
1. Toko America, Mt. Prospect, IL 312/297-0070
sides separating the luminance and color
signals, the impulse response of the luminance channel is improved and has symmetrical overshoots, giving the impression of
better resolution on the screen. This type of
filter is only given as an example. Simpler
filters can also be used. The SECAM circuit
contains the obligatory "bell" filter. Coil data
for the circuit shown in Figure 3 is given in
Table 2.
Figure 4 shows oscillograms of the luminance
and color filtering in the three signal paths. It
can be seen that the color passband in the
PAL and NTSC decoding mode has its minimum just below the color subcarrier frequency. This means that the lower sideband of the
color signal is mainly used and, as a result,
the filter may have a narrower bandwidth.
Generally, the upper sideband of the color
signal is already attenuated by the IF filter.
The passband of the filter in the SECAM color
signal path has the required "bell" shape as
shown in Figure 4c.
Depending on the decoding mode, the luminance signal is fed from the appropriate filter,
via the luminance delay line, to the video
combination IC, and the color signal is fed via
a small coupling capacitor (220pF) to input
Pin 15 of the decoder IC.
Emitter-followers in the color signal path provide the required switching. There is one for
each mode, PAL/NTSC-4.43, NTSC-3.58,
and SECAM, feeding a common emitterresistor. Three more emitter-followers in the
luminance signal path are combined with a
fourth which supplies the unfiltered video
signal to the video combination IC during b/w
reception, or while the standards are being
scanned. The video signals are applied to the
bases of the transistor switches via coupling
capacitors, the switch voltages being supplied via resistor-diode networks. The fourth
transistor switch in the luminance channel
has fixed-base biasing of about 4.4V.
From the low-pass characteristics of the luminance channels, it follows that the subcarriers
(4.43MHz for PALINTSC-4.43 and 3.58MHz
for NTSC-3.58) and the unmodulated carrier
frequency (fOB ~ 4.41 MHz for SECAM) are
strongly attenuated. Additionally, low-pass filter (L1OC20) of the SECAM luminance channel resonates at about 4.05MHz which provides the required attenuation of frequencies
below 4.2MHz for modulated carriers.
The resistors in parallel with the SECAM
tuned circuits determine their Q and therefore
the conversion efficiency (dV1df) of the demodulators in the SECAM mode and can be
used to set the nominal output values of the
CD signals (with a color bar signal). The
switch transistors for the oscillator crystals at
Pin 19 have their collectors connected, via
10kn reSistors, to the supply line. Because
they are either fully conducting or completely
cutoff and the voltages are low (12V max.),
the type of transistor is not critical.
All three separation filters are fed with the
CVBS input signal via an emitter-follower
(transistor BC548B). Therefore, the complete
decoder has a high input resistance and the
filters are driven for a low impedance Signal
source.
The standard control voltage outputs (Pins 25
to 28) can deliver a current of 3mA which is
insufficient to drive a LED to indicate the
standard to which the circuit is set. An additional transistor amplifier such as that shown
in Figure 5 is therefore required. Resistor Rcs
February 1987
10-79
determines the current through the LED, and
RBS limits the maximum base current.
If an indication is provided for each of the
standard switch voltages, then it is easy to
establish which standard, if any, is recognized. When all the diodes light up in sequence, the circuit is still scanning and no
standard has been recognized.
Alignment of the Input Filter
The alignment of both the PAL/NTSC-4.43
and NTSC-3.58 separation filters consists of
three procedures for each separation filter.
1. Alignment of the Color Bandpass
Apply a sweep signal [f = 3.5MHz (4MHz);
t.f~± 3MHz (± 3MHz) to the filter input
(PCB Pin 8). Connect an oscilloscope to
PCB Pin 6 and make the filter output
available at IC Pin 6 by applying an external
switch voltage to the appropriate switch
transistor. Adjust L2(L2al for maximum output at 3.45MHz (4.2MHz).
2. Alignment of the Compensation
Circuit
Apply a 3.58MHz (4.43MHz) subcarrier to
the filter input (PCB Pin 8) and adjust
L1(L1a) so that the voltage at the Youtput
of the filter is minimum. This Y output can
be measured at the 470n (560n) terminating resistor, or at PCB Pin 10, if the proper
switch transistor is activated by an external
switch Voltage.
3_ Alignment of the Phase Delay
Equalizer
Apply a 16 100kHz square wave to the
filter input (PCB Pin 8) and connect an
oscilloscope to the output of the luminance
filter (470n or 560n terminating resistor).
II
Application Note
Signetics linear Products
Single-Chip Multistandard
Color Decoder TDA4555/TDA4556
AN1551
mended that the filter be included in the test
Signal path when aligning L3/L3o. In practice,
a square wave-modulated IF signal should be
applied to the input of the IF circuit for this
adjustment.
Filter L1OC10 attenuates the SECAM color
signal in the luminance channel below
4.2MHz. L10 is adjusted so that an applied
4.05MHz signal has minimum amplitude at
the output of the SECAM Y-filter (terminating
resistor 3.3kn, or PCB Pin 10, if an external
switch voltage is applied to the appropriate
input).
2
3
!(MHz)
a. PALINTSC-4.43 (fa = 4.433MHz)
-..L
5dB
T 1---+---t+----+---tH---l
2
3
!(MHz)
b. NTSC-3.58 (fa = 3.579MHz)
2
3
!(MHz)
=
c. SECAM (fOB 4.250MHz,
fOR = 4.406MHz), "Bell" Filter
(fRES = 4.286MHz)
Figure 4. Amplitude-frequency
Characteristics of Input Filter
Alternatively, the oscilloscope can be connected to PCB Pin 10, if an external switch
voltage is applied to the appropriate input.
Adjust coil L3(L3'> to obtain a symmetrical
overshoot at the leading and trailing edges
of the pulse.
Because the Impulse response of a receiver
also depends on the IF filter, it Is recomFebruary 1987
To align the SECAM "bell" filter, a SECAM
color bar is applied to the filter input (PCB Pin
8) and an external switch voltage (e.g., the
supply voltage) to PCB Pin 16 to force the
SECAM decoding mode. L4 is then adjusted
for minimum amplitude-modulation of the filtered color signal (PCB Pin 6).
To locate the coils to be adjusted, it is useful
to color code them as shown in Table 2 and
Figure 3.
VCC<+12V)
SWITCHING
VOLTAGE
VST
22k
RSS
Figure 5. Example of Standard
Indicator Circuit
output signal (IC Pin 1 or PCB Pin 14) using
an oscilloscope, or, observing the picturetube screen, minimize the PAL structure (pairing of the lines).
Special test patterns can also be used for
delay line adjustment.
Decoder Alignment
Finally, remove the external switching voltage
applied to Pin 28 and put the service switch in
the mid (normal) position.
PAL and NTSC-4.43 Signals
Force the PAL decoding mode by an external
voltage exceeding 9V (e.g., the supply voltage) applied to Pin 28 of the IC (or PCB Pin
15) and apply a PAL color signal (e.g., color
bar) to the filter input, PCB Pin 8. Connect IC
Pin 17 to ground with the service switch. The
color is forced ON and the oscillator is freerunning because the PLL oscillator circuit
does not receive the burst.
NTSC-3.58 Signals
In this case, only the 7.16MHz oscillator has
to be adjusted. Force the circuit to the NTSC3.58 decoding mode by connecting IC Pin 26
or PCB Pin 17 to the supply voltage. Apply an
NTSC 3.58 color signal to the filter input (PCB
Pin 8). Connect IC Pin 17 to ground with the
service switch. The color is forced ON and
the oscillator is free-running because the PLL
oscillator does not receive burst signals.
Adjust the trimmer in series with the 8.8MHz
crystal for minimum color rolling. Alternatively, observe the color-difference signals at IC
output Pins 1 and 3 and minimize the beat
frequency with the trimmer. This 8.8MHz
oscillator adjustment is also valid for the
decoder in NTSC-4.43 mode.
Adjust the trimmer in series with the 7.16MHz
crystal for minimum color rolling. Alternatively, observe the CD signals at the IC output
Pins 1 and 3 and minimize the beat frequency.
To adjust the phase of the delay-line decoder,
apply a PAL color bar signal to the input of
the circuit (PCB Pin 8) with the service switch
in its normal (middle) position. Adjust Ls and
La to minimize amplitude differences of each
color bar in the (B-Y) output signal (IC Pin 3 or
PCB Pin 13).
Alternatively, minimize the PAL structure
(pairing of the lines) observed on the
screen. If the adjustment range of Ls is too
small, adjust La.
To adjust the amplitude of the delay-line
decoder, apply an NTSC-4.43 color bar signal
to the input of the circuit (PCB Pin 8) and
connect IC Pin 17 to the supply line with the
service switch. The color is forced ON and
the hue control is switched off. Adjust the
220.11 potentiometer connected to Pin 4 of
the DL711 delay line for minimum amplitude
differences of each color bar in the (R-Y)
10-80
Finally, remove the connection between PCB
Pin 17 and the supply voltage and put the
service switch back to its mid position.
Alignment for SECAM Signals
Force the circuit in the SECAM decoding
mode by connecting the supply voltage to IC
Pin 27 (or PCB Pin 16). Apply a SECAM color
bar to the filter input (PCB Pin 8).
Connect IC Pin 23 (or PCB Pin 20) to the
supply line to activate the H-identification.
Connect a high-impedance (> 10Mn) voltmeter between IC Pin 21 and ground. Adjust
coil L7 for the maximum voltage at IC Pin 21.
Observe the - (R-Y) output signal at IC Pin 1
(PCB Pin 14) with an oscilloscope. Adjust La
so that the levels of the black and white bars
are in accordance with the level inserted
during blanking.
Observe the -(B-Y) output signal at IC Pin 3
(PCB Pin 13) with an oscilloscope. Adjust L9
Application Note
Signetics Linear Products
Single-Chip Multistandard
Color Decoder TDA4555/TDA4556
so that the levels of the black and white bars
are in accordance with the levels inserted
during blanking.
Use of the PC Board for a
PAL-Only Decoder With the
AN1551
TDA4555/TDA4556 can be used as a single
standard decoder (e.g., a NTSC-only decoder), but the "pin-aligned" TDA4570 is a
cheaper alternative. The connections of the
TDA4570 and those of the TDA4555 are
shown in Figure 6. Apart from the omission of
TDA4510
many peripheral components, only small
changes in the external circuitry are needed.
NOTE:
This application not8, written by Klaus Juhnke and
published as Technical Publication 169 by ELCOMA
in 1985, has been revised and edited.
To efficiently manufacture a family of receivers, based on the same main PC board, the
Figure 6
•
February 1987
10-B1
TDA4565
Signetics
Color Transient Improvement
Circuit
Product Specification
Linear Products
DESCRIPTION
FEATURES
The TDA4565 is a monolithic integrated
circuit for color transient improvement
(CTI) and luminance delay line in gyrator
technique in color television receivers.
• Color transient improvement for
color difference signals (R-V) and
(B-V) with transient detecting,
storage, and switching stages
resulting in high transients of
color difference output signals
• A luminance signal path (V)
which substitutes the
conventional V-delay coil with an
integrated V-delay line
• Switchable delay time from 690ns
to 1005ns In steps of 45ns
• Two V output signals; one of
180ns less delay
PIN CONFIGURATION
(R-Y) IN
1
18 GND
17
f~~~NANCE
OIFF CAP 3
16
8Wr~~~~~D
DIFF CAP 4
15 gi~rxTlME
STOR~~~ 6
13
~W?rg~lAY
(B-Y) OUT
7
12
~~~~~NCE
(R·Y) OUT
6
11
~~~~Y(E~~TbELAY
STOR~~~ -...
9
_ _..rTOP VIEW
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
18·Pin Plastic DIP (SOT-102CS)
o to
ORDER CODE
+70'C
TDA4565N
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
Vcc = V, O- , 8
Supply voltage (Pin 10)
Vn - 18
V" - 8
'
V17 - 18
Voltage ranges to Pin 18
(ground)
at Pins 1, 2, 12, and 15
at Pin 11
a1 Pin 17
V7 - S
V8 - 9
Voltage ranges
at Pin 7 to Pin 6
at Pin 8 to Pin 9
± Is, 9
17,8.11.12
Currents
at Pins 6, 9
at Pins 7, 8. 11, and 12
PTOT
Total power dissipation
TSTG
Storage temperature range
TA
Operating ambient temperature
range
RATING
UNIT
13.2
V
o to Vee
o to (Vec-3V)
o to 7
V
V
V
o to 5
o to 5
V
V
15
rnA
1.1
W
-25 to +150
'C
o to +70
'C
NOTE:
DC potential not published for Pins 3. 4. 5, 6, 9. 13, and 14.
February 12. 1987
10-82
853-1179 87585
Signetics Linear Products
Product Specification
TDA4565
Color Transient Improvement Circuit
BLOCK DIAGRAM
Vee
(+12V)
10
TDA4565
IN~~~~~~~ -i
(V)
12
YOUTPUT
11
YOUTPUT
>---1-(1.,)
17
330nF
'--------;>-+.... (10 -
180n8)
I--r>--f-'" (RoV)
OUTPUT
Hf-D>--If-I.. (B-y)
OUTPUT
COLOR DIFFERENCE
INPUT SIGNALS
(B-V)
2
-i1-+-+----1---+
__-D+__--l
330nF
•
February 12, 1987
10-83
Product Specification
Signetics Linear Products
Color Transient Improvement Circuit
TDA4565
DC ELECTRICAL CHARACTERISTICS Vcc = V10 - 18 = 12V; TA = 25°C; measured in application circuit Figure 1, unless
otherwise specified.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
12
13.2
V
35
50
rnA
Supply (Pin 10)
VCC=Vl0-18
Supply voltage
Icc = 110
Supply current
10.8
Color difference channels (Pins 1 and 2)
Vl - 18
(A-V) input voltage (peak-to-peak value) 75% color bar signal
1.05
V
V2-18
(B-V) input voltage (peak-to-peak value) 75% color bar signal
1.33
V
A1. 2- 18
Input resistance
12
k,Q
V1. 2- 18
Internal bias (input)
4.3
V
5V) switches
the color on, the hue-control is
switched off, and the output
signals can be observed
• Sand castle pulse detector for
burst gate, - line and + line
vertical blanking pulse detection;
the vertical part of the
sandcastle pulse is needed for
the internal color-on and coloroff delay
• Pulse processing part which shall
prevent a premature switching on
of the color; the color-on delay,
two or three field periods after
identification of the NTSC signal,
is achieved by a counter. The
color is switched off
immediately, or, at the latest,
one field period after
disappearance of the
identification voltage
PIN CONFIGURATION
N Package
-(R.Y)IN
16~~'
ru~FE
1
15
12 PLL
11
Vee
~~A~~~
7
FEE= - ,_ _ _......9_ CHROMA IN
lOP VIEW
• - (B-V) and - (R-V) signal output
stages; the output stages are
low-resistance NPN emitterfollowers
• Separate color switching output
APPLICATIONS
• Video processing
• TV receivers
• Graphic systems
Demodulator part:
o Two synchronous demodulators
for the (B-V) and (R-V) signals,
which incorporate stages for
blanking during line- and fieldflyback
• Internal filtering of the residual
carrier in the demodulated color
difference signals
• Color switching stages controlled
by the pulse processing part in
front of the output stages
ORDERING INFORMATION
DESCRIPTION
16-Pin Plastic DIP (SOT-38)
February 12, 1987
TEMPERATURE RANGE
ORDER CODE
TDA4570N
10-86
853-1185 87586
;;r
III
r-
0-
2
-<'"
0
-I
CJ)
'"
()
5>
C)
()
0
1"
C
co
O:J
....
rl22nF
NC
p'0nF
NC
Vee
:tJ
= 12V
>
iii:
WORKING P&NTI
STABIUZATION- 18
Z
0
0
.....
0
en
ea:J
<1>
g
Q
"a
u
c
@-
=ii
CD
.....
CD
::J
()
o--.j
-(R-V)
O.33J.lF
tI-IAC.!!!.l~.j..I--_ _I~1 1
BT
CD
0
CD
()
1
0
Q.
CD
.....
....
o
Co
-...!
t
22nF
1.
~ ilOENTIFICATION
-(B-V)
A
SANOCASTLE
INPUT PULSE
12~n~F
V
330nF
5.1k
10k
-=-
-=
"a
NOTES,
(A) Color ON: Hue OFF.
(8) Color ON: Hue OFF; fa adjustment.
u
-I
o
$:
01
"o
II
c
<:len
1)
<1>
o
=;;
O-
S.
6:J
Signetics Linear Products
Product Specification
NTSC Color Difference Decoder
TDA4570
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
10.8 to 13.2
V
5
5
rnA
rnA
VCC=V7-S
Supply voltage range
-11,2
-116
Currents
at Pins 1 and 2
at Pin 16
OJA
Thermal resistance
80
·C/W
ProT
Total power dissipation
800
mW
TSTG
Storage temperature range
-65 to + 150
·C
TA
Operating ambient temperature range
o to
+70
·C
DC ELECTRICAL CHARACTERISTICS Vce = 12V; TA = 25·C; measured in Figure 1, unless otherwise specified.
LIMITS
PARAMETER
SYMBOL
UNIT
Min
17
Supply current
Typ
Max
50
rnA
Chromlnance part
V9_S(P_P)
Input voltage range (peak-to-peak value)
V9-S(P_P)
Nominal input voltage (peak-to-peak values)
with 75% color bar signal
100
mV
Z9_S
Input impedance
3.3
kn.
C9-S
Input capacitance
4
pF
10
400
mV
Oscillator and control voltage part
fo
Oscillator frequency for subcarrier frequency of 3.58MHz
7.16
MHz
R1S-S
Input resistance
350
n.
Af
Catching range
(depending on RC network between Pins 12 and 3)
±300
Hz
V14 - S
V14 - S
V14-S
Control voltage
without burst signal
color switching threshold
hysteresis of color switching
tD ON
Color-on delay
3
Field
period
tD OFF
Color-off delay
1
Field
period
-1 16
V16-S
V16-S
Color-switching output (open NPN emitter)
output current
color-on voltage
color-off voltage
6
6.6
150
V
V
mV
5
rnA
V
V
5
Degree
6
0
Hue control and service switches
I/>
Phase shift of reference carrier relative to the
input signal V11 _ S = 3V
-I/>
I/>
Phase shift of reference carrier relative to phase
at Vl l _3=3V V11_S=2V
V11_S=4V
-5
0
30
30
Internal source (open pin)
Degree
Degree
3
V
V11-S
First service position
(PLL is inactive for oscillator adjustment, color ON, hue OFF)
0
1
V
V11-S
Second service position (color ON; hue OFF)
5
Vee
V
February 12, 1987
10-88
Product Specification
Signetics Linear Products
TDA4570
NTSC Color Difference Decoder
DC ELECTRICAL CHARACTERISTICS (Continued) vee = 12V; TA = 25°C; measured in Figure 1, unless otherwise
specified.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
Color difference output signals (peak-to-peak value)
- (R-Y) signal
- (B-Y) signal
0.84
1.06
1.05
1.33
1.32
1.67
Ratio of color difference output signals (R-Y)/(B-Y)
0.71
0.79
0.87
Demodulator part
V1_3(P_P)
V2-3(P-P)
V1 _ 3
V
V
V2-3
V1,2-3
DC voltage at color difference outputs
V1,2-3(P.P)
V1,2-3(P-P)
Residual carrier at color differe nce outputs
(1 X subcarrier frequency)
(2 X subcarrier frequency)
7.7
V
20
30
mV
mV
Sandcastle pulse detector
The sandcastle pulse is compared to three internal threshold levels, which are proportional to the supply voltage.
V15-3
V15-3(P-P)
V15-3
V15 -3(P-P)
V15-3
V15-3(P-P)
Thresholds:
Field- and line-pulse separation; pulse on
Required pulse amplitude
Line-pulse separation; pulse on
Required pulse amplitude
Burst-pulse separation; pulse on
Required pulse amplitude
V15-3
Input voltage during horizontal scanning
1.1
V
-1 15
Input current
100
p.A
1.3
2
3.3
4.1
6.6
7.7
1.6
2.5
3.6
4.5
7.1
1.9
3
3.9
4.9
7.6
V
V
V
V
V
V
•
February 12, 19B7
10-89
Signetics Linear Products
Product Specification
NTSC Color Difference Decoder
TDA4570
SERVICE SWITCH
(a) COLOR ON; HUE OFF
(e) COLOR ON; BURST OFF
18k
6.Bk
3.3k
SERVICE
SWITCH
INPUT
SANDCASTLE
PULSE
(ei(b)!(a)
A-
8V
_ =--4.SV
-OV 2.SV
10k
HUE
+12V +12V
COLOR KILLER VOLTAGE
COLOR OFF s O.SV
COLOR ON 0.5 xVCC
22nF
Vee = 12V
-(R-Y)
1.05Vp.p
-(S-Y)
1.35Vp.p
NOTE:
Crystal frequency"" 7.16MHz; resonance resistance
son;
load capacitance 20pF, dynamic capacitance 22pF and static capacitance S.5pF.
Figure 1
February 12, 19B7
10-90
~
DC
FEEDBACK
ACC
TDA4580
Signefics
Video Control Combination
Circuit With Automatic Cut-Off
Control
Linear Products
Product Specification
DESCRIPTION
The TDA4580 is a monolithic integrated
circuit which performs video control
functions in television receivers with a
color difference interface. For example,
it operates in conjunction with the multistandard color decoder TDA4555. The
required input signals are: luminance
and negative color difference -(R-Y) and
-(B-Y), and a 3-level sandcastJe pulse
for control purposes. Analog RGB signals can be inserted from two sources,
one of which has full performance adjustment possibilities. RGB output signals are available for driving the video
output stages. This circuit provides automatic cut-off control of the picture tube.
FEATURES
o Capacitive coupling of the color
difference, luminance, and RGB
input signals with black level
clamping
• Two sets of analog RGB inputs
via fast switch 1 and fast switch
2
• First RGB inputs and fast switch
1 in accordance with
peri television connector
specification
• Saturation, contrast, and
brightness control acting on first
RGB inputs
o Brightness control acting on
second RGB inputs
........
IDEIOC1OOOl I
~--+-FASr-o...S\YI1CM'
Y1==o-j "
U5Vp.D
,;t~o-jl171
I I
I -
IE>-tf-...f-a-L. 1 L J I.I""!'!.RASTI
/
I';'
/I>-t+I-N I L II IOO!'!.RASTI
~ -=~o l I I I
I
18PdoN~_U... ~Iy~A~
I I I I~I! i I I IBlAN~N.l1
[1
,I
I
I
I'
= IT1
h J
I
OUTPUT
ENCE
ll~ I
__
__
BLANKINO
:-:-
I
IU,-- "'1
fTI
s~
8.
Q.
~
I
OQ:
~ ~
__
OIITPur
3::J
..... =to
o· ~ g3
I IS::O
8LANKlN1l1:-:-wOtnPurmo, ~IWI
R.Y
~~
,';':~o-II "I
r·
£Q
c:::::<'§
5 -- CD
..... Q.
=t
=r 9V
10
kQ
119
Control current into contrast input (Pin 19) during peak drive
V1, 2, or 3-24> V9- 24
20
rnA
V
Average beam current limiting input (Pin 25)5
V25 - 24
Start of contrast reduction at maximum contrast setting
8.5
AV25_24
Input range for full contrast reduction
1.0
V
R25
Input resistance at V25-24 < 6V
2.2
kQ
Saturation control input (Pin 16) (saturation control acts on CD signals or RGB1 signals, respectively)
V16 - 24
Maximum saturation
4
V
V16 - 24
Nominal saturation (6dB below maximum)
3
V
Attenuation of saturation at V16 _24 = 1.8V
(related to maximum at 100kHz)
116
Input current at V16 - 24
50
dB
= 1.8 to 4V
10
/1A
Brightness control Input (Pin 20)6, 7
V2O - 24
Control voltage range
-1 20
Input current at V20 - 24
V20-24
1
= 1 to 3V
Control voltage for nominal brightness
Change of black level in the control range related to the
nominal output signal (black/white) for AV20_24 = 1V
V2O - 24
January 14, 1987
Signal swilched off and black level equal 10 cui-off level
10-94
11.5
3
V
10
/lA
2.2
V
33
%
V
Signetics Linear Products
Product Specification
Video Control Combination Circuit
With Automatic Cut-Off Control
TDA4580
DC ELECTRICAL CHARACTERISTICS (Continued) Vee = 12V; TA = 25°C; measured in a circuit similar to Figure 2 at
nominal settings (saturation, contrast, brightness), no beam current
or peak drive limiting; all voltages with respect to Pin 24 (ground),
unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
Y, (R-Y), (B-Y)/RGB-Matrix S
PAL matrix (VS-24
= ;;;; 4.5V)
Matrixed according to the equation
V(G _ V) = -0.51V(R _ V) -0.19V(S _ V)
NTSC matrix (VS-24
= ;;. 5.5V)
(Adaption for NTSC-FCC primaries, nominal hue control set
on -5°C)
Matrixed according to the equation
V(G_ V)8 = -0043V(R _ V) - O.IIV(S_ V)
VIR _ V)8 = 1.57V(R_ V) - 0041V(S_ V)
VI(S_V)8 = VIS-V)
RGB2 inputs (Teletext) (R2 Pin 23, G2 Pin 22, B2 Pin 21)2
(RGB signals controlled by brightness control)
V21, 22, 23-24
Input signal for 100% output signals (black to white value)
121. 22, 23
Input current during scanning
121, 22, 23
Input resistance
1
V
0.3
5
p.A
Mn
Signal switch 2 input (Pin 28)
Input voltage level for insertion of Y,
CD signals or RGBI signals, respectively
V28 -24
V28-24
RGB signals from matrix 9
RGB2 signals 9
R28.24
Internal resistor to ground
004
3.0
0.9
10
V
V
kn
Automatic cut-off control input (Pin 26) (Leakage current measuring time and Insertion of RGB cut-off measuring linessee Figure 3; types of ultra-black level- see Figure 1,)10
V26 - 24
Allowed maximum external DC bias voltage
Ll. V26-24
Voltage difference between cut-off current measurement and
leakage current measurement
5.5
V1, 3, 5-24
Warm-up test pulse
V26-24
Threshold for warm-up detector
V
0.5
V
V9_24 8
V
8
V
Storage input for leakage current (Pin 27)
R27
Internal resistance during leakage current measuring time
(current limiting at 127 = 0.2mA)
11271
Input current except during cut-off control cycle
400
n
0.5
flA
Storage Inputs for automatic cut-off control (Pins 2, 4, 7)
0.3
112,4,71
Charge and discharge currents
112, 4, 71
Input currents of storage inputs out of control time
January 14, 1987
10-95
mA
0.1
flA
•
Signetics Linear Products
Product Specification
Video Control Combination Circuit
With Automatic Cut-Off Control
TDA4580
DC ELECTRICAL CHARACTERISTICS (Continued) Vec = 12V; TA = 25°C; measured in a circuit similar to Figure 2 at
nominal settings (saturation, contrast, brightness), no beam current
or peak drive limiting; all voltages with respect to Pin 24 (ground),
unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
Switching voltage input for PAL matrix and vertical blanking
period of
25 lines
22 lines
18 lines
1.5
3.5
0
2
4
0.5
2.5
4.5
VS-24
NTSC matrix and vertical blanking period of 18 lines
5.5
6
Is
Input current
Switch Input for PALINTSC matrix and vertical blanking time (Pin 8)11
VS-24
VS-24
VS-24
V
V
V
12
V
50
p.A
3.0
5.0
V
V
V
100
p.A
10
%
Sandcastle pulse detector (Pin 10)12
VIO-24
Vl0-24
VIO-24
tD
The following amplitudes are required for separating the
various pulses:
horizontal and vertical blanking pulses
horizontal pulses for counter logic
clamping pulses
delay of leading edge of clamping pulse
-1 10
Input current at VIO - 24 = OV
2.0
4.0
7.5
2.5
4.5
1
/1S
Outputs for positive RGB signals (RO Pin 1, GO Pin 3, BO Pin 5)13
V1. 3. 5-24
Nominal signal amplitude (black/white)
3
Spreads between channels
V
V1, 3, 5-24
Maximum signal amplitude (black/white)
11, 3, 5
Internal current source
Rl, 3,5
Output resistance
VI, 3, 5-24
Minimum output voltage
1
V
V1, 3. 5-24
Maximum output voltage
10
V
4
V
3
160
rnA
220
n
Horizontal and vertical blanking to ultra-black level 2, related
to nominal signal black level in percentage of nominal signal
amplitude
45
55
%
Vertical blanking to ultra-black levell, related to cut-off
measuring level in percentage of nominal signal amplitude
25
35
%
Recommendation:
Range for cut-off measuring level 1.5 to 5.0V;
nominal value at 3V 14
Gain data15
d
Frequency response of Y path (0 to 8MHz)
Pins 1, 3, and 5 to Pin 15
3
dB
d
Frequency response of CD path (0 to 8MHz)
Pin 1 to Pin 17 = Pin 5 to Pin 18
3
dB
d
Frequency response of RGBI path (0 to 8MHz)
Pin 1 to Pin 14 = Pin 3 to Pin 13
= Pin 5 to Pin 12
3
dB
d
Frequency response of RGB2 path (0 to 10MHz)
Pin 1 to Pin 23 = Pin 3 to Pin 22
= Pin 5 to Pin 21
3
dB
January 14, 1987
10-96
Signetics Linear Products
Product Specification
Video Control Combination Circuit
With Automatic Cut-Off Control
TDA4580
NOTES:
1. The value of the color difference input signals, -(B-Y) and -(R-y), is given for saturated color bar with 75% of maximum amplitude.
2. Capacitive coupled to a low ohmic source; recommended value soon (maximum).
3. At Pin 19 for V19 _24 :S;;;2.0V, no further decrease of contrast is possible.
4. The peak drive limiting of output signals is achieved by contrast reduction. The limiting level of the output signals is equal to the voltage V. _ 24.
adjustable in the range 5 to 11V. After exceeding the adjusted limiting level at peak drive. limiter will not be active during the first line.
5. The average beam current limiting acts on contrast and at minimum contrast on brightness (the external contrast voltage at Pin 19 is not affected).
6. At nominal brightness the black level at the oulput is 0.3V ("'-10% of nominal signal amplitude) below the measuring level.
7. The internal control voltage can never be more positive than O.7V above the internal contrast voltage.
8. Matrix equation
: oulput of NTSC decoder of PAL type demodulating axis and amplitudes
VIR_V). VIB-Y)
: for NTSC modified CD signals; equivalent to demodulation with the following axes
VIG-Y)·. VIR-Y)·. VIB-y)'
and amplification factors:
(B - V)' demodulator axis
0'
(R - Y)' demodulator axis
115' (PAL 90')
1.97 (PAL 1.14)
(R - V)' amplification factor
(B - Y)' amplification factor
2.03 (PAL 2.03)
VIG-Y)' = -0.27VIR_Y)· -0.22VIB_V)··
9. During clamping time. in each channel the black level of the inserted signal is clamped on the black level of the internal signal behind the matrix
(dependent on brightness control).
10. During warm-up time of the picture tube. the RGB outputs (Pins 1. 3. and 5) are blanked to minimum output voltage. An inserted white pulse during
the vertical flyback is used for beam current detection. If the beam current exceeds the threshold of the warm-up detector at Pin 26. the cut-off
current control starts operating. but the video signal is still blanked. After IIIn-in of the cut-off current control loop. the video signal will be released.
The first measuring pulse occurs in the first complete line after the end of the vertical part of the sandcastle pulse. The absolute minimum vertical
part must contain 9 line-pulses. The cycle time of the counter is 63 lines. When the vertical pulse is longer than 61 lines. the IC is reset to the
switch-on condition. In this event the video signal is blanked and the RGB outputs are blanked to minimum output voltage as during warm-up time.
During leakage current measurement. all three channels are blanked to ultra-black level 1. With the measuring level only In the controlled channel.
the other two channels are blanked to ultra-black level 1. The brightness control shifts both the signal black level and the ultra-black level 2. The
brightness control is disabled from line 4 to the end of the last measuring line (see Figure 1).
With the most adverse conditions (maximum brightness and minimum black level 2) the blanking level is located 30% of nominal signal amplitude
below the cut-off measuring level.
11. The given blanking times are valid for the vertical part of the sandeaslle pulse of 9 to 15 lines. If the vertical part is longer and the cut-off lines are
outside the vertical blanking period of 18. 22. or 25 lines. respectively. the blanking of the signal ends with the end of the last of the three cut-off
measuring pulses as shown in Figure 3.
12. The sandcaslle pulse is compared with three internal thresholds (proportional to Vcc) to separate the various pulses. The internal pulses are
generated when the input pulse at Pin 10 exceeds the thresholds. The thresholds are for.
• Horizontal and vertical blanking
V'O-24 = 1.5V
• Horizontal pulse
V'O-24 = 3.5V
• Clamping pulse
V'O-24 = 7.0V
13. The outputs at Pins 1, 3, and 5 are emitter-followers with current sources and emitter protection resistors.
14. The value of the cut-off control range for the positive RGB output signals is given for a nominal output signal. If the signal amplitude is reduced. the
cut-off range can be increased.
15. The gain data is given for a nominal setting of the contrast and saturation controls. measured without load at the RGB oulputs (Pins 1. 3. and 5).
BRIGHTNESS
-----NOMINAL
..........•.. •..• .............. MAXIMUM
••••••••• _•••• MINIMUM
UIJ"RA-SLACK
LEVEL2
~--------~--------------------------~~~~R~~~:~NAL
~----------------------~-----------------------UIJ"RA-BLACKL~1
WF18NO$
Figure 1. Types of Ultra-Black Levels
January 14, 1987
10-97
•
Product Specification
Signetics Linear Products
Video Control Combination Circuit
With Automatic Cut-Off Control
TDA4580
-R
-G
-B
YCCl(+200V) -------....,.-----t----..,-.----+--~__,
Yoo(+uV)--~-----_+----_+--4r-1_---_t--~-t_---+_-1r-_r-_,
GREEN
BWE
OUTPUT
OUTPUT
srAGE
srAGE
18k
820
820
'N4148
2.2k
Uk
820
1.8k
Uk
BC558
lOOnF
~------r--+~--~--_+_~--_+~~
B
G
CIJT.OFF
CONTROL
NOTE:
1. Capacitor value depends on circuit layout.
Figure 2a. Part of Typical Application Circuit Diagram Using the TDA4580; Continued in Figure 2b
January 14, 1987
10-98
BEAM
CURRENT
UMmNO
Product Specification
Signetics Linear Products
Video Control Combination Circuit
With Automatic Cut-Off Control
TDA4580
FAST SWIlCH 2
1--.,..-:,----+-..---- ONTERNALSOURCE)
OIlY
I - - - - i f - - - r _ _ - - - - R2~V}
10nF
1-----11-1- - r _ _ - - - - G2~V}
SIGNAL INSERTION
ONTERNAL SOURCE)
10nF
!-=---II-I---1r-----B2~V}
~---------,~-k--~~~~NE~
I------~--"""'/\r-- ~~~~
22nF
+ 14•7"5..-:-
1----11-1- - - - - - - - 1~:V~p }CD
1
22nF
-(R·y) SIGNALS
1.05Vp.p
47nF
SATURATION
(2T04v)
~ DELAYED
WMINANCE
o.45Vp.p
Figure 2b. Part of Typical Application Circuit Diagram Using the TDA4580; Continued from Figure 2a
January 14, 1987
10-99
•
Signetics Linear Products
Product Specification
Video Control Combination Circuit
With Automatic Cut-Off Control
821 622 623 624 625
9
10
11
TDA4580
12
f3
14
~5
16
17
18
19
I
~
NOTES:
1. Vertical part of sandcastle pulse starts with equalizing pulses and ends with flyback.
2, Blanking period of 25 complete lines.
3, Leakage measuring period (LM).
4. Vertical part of sandcastte pulse starts and ends with flyback .
. 5. Blanking period of 22 complete lines.
6. Sianking period of 18 complete lines.
7. Cut-off measuring line for red signal (MR).
8, Cut-off measuring line for green signal (MG).
9. Cut-off measuring line for blue signal (MS).
Figure 3. Blanking and Measuring Lines
January 14. 19B7
10·100
20
21
22 23
24 25
28
Z1
28
TDA8442
Signetics
Quad DAC With 12C Interface
Product Specification
Linear Products
PIN CONFIGURATION
DESCRIPTION
FEATURES
The TOA8442 consists of four 6-bit 01 A
converters and 3 output ports. This IC
was designed to provide 12C control, by
replacing the potentiometers, for the
TOA3560-series single-chip color decoders. Control of the IC is performed
via the two-line, bidirectional 12C bus.
• 6-bit resolution
• 3 output ports
• 12 C control
N Package
APPLICATIONS
•
•
•
12C interface control
System control
Switching
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
-20·C to + 70·C
TDA8442N
16-Pin Plastic DIP (SOT-38)
lOP VIEW
CD12650S
ABSOLUTE MAXIMUM RATINGS
RATING
UNIT
Vcc
Supply voltage range (Pin 9)
-0.3 to +13.2
V
VSDA
VSCL
VCC2
VCC2N
VCC1
VDAX
Input/output voltage ranges
(Pin 4)
(Pin 5)
(Pin 6)
(Pin 12)
(Pin 11)
(Pins 1 to 3 and Pin 16)
-0.3 to
-0.3 to
-0.3 to
-0.3 to
-0.3 to
-0.3 to
V
V
V
V
V
V
I',-OT
Total power dissipation
TA
Operating ambient temperature range
TSTG
Storage temperature range .
SYMBOL
PARAMETER
+13.2
+13.2
Vcc 1
Vcc 1
Vcc 1
Vcc 1
1
W
-20 to +70
·C
-65 to +150
·C
PIN NO. SYMBOL
DESCRIPTION
DAC1
Analog output 1
I
2
DAC2
Analog output 2
3
OAC3
Analog output 3
4
SOA
Serial data line
1'<: b
Sel
Serial clock line
us
5
P2
Port 2 NPN collector output
6
with internal pull-up resistor
Not connected
7
NC
Supply return (ground)
8
GND
9
Positive supply voltage
Vee
10
NC
Not connected
11
PI
Port 1 open NPN emitter
J
output
12
13
14
15
16
P2N
Ne
Ne
Ne
DACO
Inverted P2 output
Not connected
Not connected
Not connected
Analog output 0
NOTE:
I. Pin voltage may exceed Vcc if Ihe currenl in thai pin is Iimiled 10 lOrnA.
February 12, 1987
10-101
853-1176 87584
..
Signetics Linear Products
Product Specification
Quad DAC With 12C Interface
TDA8442
BLOCK DIAGRAM
19
TDA8442
~
POWER·DOWN
DETECTOR
DACO
.2! f-
DIGITAl·TO-ANALOG
CONVERTER
DACO
DAC1
...2 -
DIGITAl·TO·ANALOG
CONVERTER
~ r-
DIGITAl·TO·ANAlDG
CONVERTER
.2- -
DlGITAl·TO·ANAlDG
CONVERTER
DAC3
DAC1
f-
DAC3
DAC2
r-
I I
DACX
POD
12CBUS
SLAVE
RECEIVER
I+-
t
t
SDA
SCl
.4
February 12, 1987
OUTPUT PORT
-
OUTPUT PORT
P2N
12
L-.
OUTPUT PORT
P1
11
P2
fI
DAC2
f- .!..- P2
,...-
10-102
b
S
l8
P2N
P1
Signetics Linear Products
Product Specification
Quad DAC With 12C Interface
TDA8442
DC AND AC ELECTRICAL CHARACTERISTICS TA = + 25'C; Vee = 12V, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
10.8
12
13.2
Supplies
Vcc
Supply voltage (Pin 9)
Icc
Supply currents (no outputs loaded) (Pin 9)
12
V
mA
12 C bus Inputs SDA (Pin 4) and SCl (Pin 5)
VIH
Input voltage High 1
VIL
Input voltage Low
3
Vcc- 1
V
-0.3
1.5
V
IIH
Input current High 1
10
p.A
IlL
Input current Low1
10
p.A
12 C bus output SDA (Pin 4) (open-collector)
VOL
Output voltage Low at 10L = 3.0mA
10L
Maximum output sink current
0.4
5
V
mA
Ports P2 and P2N (Pins 6 and 12) (NPN collector output with pull-up resistor to Vecl
Ro
Internal pull·up resistor to Vee
VOL
Output voltage Low at 10L = 2mA
5
10L
Maximum output sink current
10
15
0.4
2
kn
V
mA
5
Port P1 (Pin 11) (open NPN emitter output)
10H
Output current High at 0 < Vo
10L
Output leakage current at 0 < Vo
< Vee - 1.5V
< VccV
14
mA
100
p.A
Dlgltal-to-analog outputs Output DACO (Pin 16)
VOMAX
Maximum output voltage (unloaded)2
VOMIN
Minimum output voltage (unloaded)2
VOLSB
Positive value of smallest step2 (1 LSB)
Zo
Output impedance at -2
-IOH
Maximum output source current
2
10L
Maximum output sink current
2
3
V
0
Deviation from linearity
< 10 < +2mA
1
V
100
mV
150
mV
70
n
6
mA
8
mA
Output DAC1 (Pin 1)
VOMAX
Maximum output voltage (unloaded)2
VOMIN
Minimum output voltage (unloaded)2
VOLSB
Positive value of smallest step2 (1 LSB)
4
V
0
1.7
V
120
mV
Deviation from linearity
170
mV
Zo
Output impedance at -2 < 10 < + 2mA
70
n
-IOH
Maximum output source current
2
6
mA
10L
Maximum output sink current
2
February 12, 1987
10-103
8
mA
•
Signetics Linear Products
Product Specification
Quad DAC With 12C Interface
TDA8442
DC AND AC ELECTRICAL CHARACTERISTICS (Continued)
TA = + 25°C; Vee = 12V, unless otherwise specified.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
Output DAC2 (Pin 2)
VOMAX
Maximum output voltage (unloaded)2
VOMIN
Minimum output voltage (unloaded)2
VOLSB
Positive value of smallest step2 (1 LSB)
V
4
0
Deviation from linearity
< 10 < +2mA
Zo
Output impedance at -2
-IOH
Maximum output source current
2
10L
Maximum output sink current
2
1.7
V
120
mV
170
mV
70
n
6
rnA
rnA
8
Output DAC3 (Pin 3)
VOMAX
Maximum output voltage (unloaded)2
VOMIN
Minimum output voltage (unloaded)2
VOLSB
Positive value of smallest step2 (1 LSB)
Zo
Output impedance at -2
-IOH
Maximum output source current
2
10L
Maximum output sink current
2
V
10
0
Deviation from linearity
< 10 < +2mA
1
V
350
mV
0.50
V
70
n
6
rnA
rnA
8
Power-down reset
Veeo
Maximum value of Vee at which power-down reset is active
6
tA
Rise time of Vee during power-on (Vee rising from OV to Veeo)
5
NOTES:
I. If Vee < tV, the input current is limited to IOpA at input voltages up to 13.2V.
2. Values are proportional to Vcc.
February 12, 1987
10-104
10
V
/1S
Product Specification
Signetics Linear Products
Quad DAC With 12C Interface
TDA8442
FUNCTIONAL DESCRIPTION
Reset
Control
The power-down reset mode occurs whenever the positive supply voltage falls below 8.5V
(typical) and resets all registers to a defined
state.
Analog control is facilitated by four 6-bit
digital-to-analog converters (DACO to DAC3).
The values of the output voltages from the
DACs are set via the 12C bus.
The high-current output port (Pl) is suitable
for switching between internal and external
RGB signals. It is an open NPN emitter output
capable of sourcing 14mA (minimum).
The two output ports (P2 and P2N) can be
used for NTSC/PAL switching. These are
NPN collector outputs with internal pull-up
resistors of 10kU (typical). Both outputs are
capable of sinking up to 2mA with a voltage
drop of less than 400mV. If one output is
programmed to be Low, the other output will
be High, and vice versa.
OPERATION
Write
12C
The TDA8442 is controlled via the
bus.
Programming of the TDA8442 is performed
using the format shown in Figure 1.
Acknowledge (A) is generated by the
TDA8442 only when a valid address is received and the device is not in the powerdown reset mode (Vcc> 8.5V (typ».
Control
Control is implemented by the instruction
bytes POD (port output data) and DACX
INSTRUCTION BYTE
MODULE ADDRESS
(digital-to-analog converter control), and the
corresponding datal control bytes (see Figure
2).
POD Bit PI -If a '1' is programmed, the Pl
output is forced High. If a '0' is programmed,
or after a power-down reset, the PI output is
Low (high-impedance state).
POD Bit P2/P2N - If a '1' is programmed,
the P2 output goes High and the P2N output
goes Low. If a '0' is programmed, and after a
power-down reset, the P2 output is Low and
the P2N output is High.
DAX Bits AX5 to AXO - The digital-toanalog converter selected corresponds to the
decimal equivalent of the two bits Xl and XO.
The output voltage of the selected DAC is
programmed using Bits AX5 to AXO, the
lowest value being all AX5 to AXO data at '0',
or when power-down reset has been activated.
DATA/CONTROL BYTE
s
MSB
LR/W
MSB
MSB
-."s
Figure 1. TDA8442 Programming Format
INSTRUCTION BYTE
DATA/CONTROL BYTE
Figure 2. Control Programming
February 12, 1987
10-105
..
Product Specification
Signetics Unear Products
Quad DAC With 12C Interface
12
c
TDA8442
BUS TIMING
Bus loading conditions: 4kn pull-up resistor to + 5V; 200pF capacitor to GND.
All values are referred to VIH = 3V and Vll ~ 1.5V.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
tSUF
Bus free before start
4
JJs
tsu. tSTA
Start condition setup time
4
JJS
tHO. IsTA
Start condition hold time
4
JJS
tlOW
low period Sel. SDA
4
JJS
tHIGH
High period Sel
4
JJs
tR
Rise time Sel. SDA
1
JJS
tF
Fall time Sel. SDA
0.30
JJS
Isu. tOAT
Data setup time (write)
0.25
JJS
tHO. tOAT
Data hold time (write)
0
JJs
tsu. tACK
Acknowledge (from TDA8442) setup time
tHO. tACK
Acknowledge (from TDA8442) hold time
0
JJS
tsu. lSTo
Stop condition setup time
4
JJS
2
JJs
SOA
(WRITE)
sel
WF18781$
NOTE:
Reference levels are 10 and 90%.
Figure 3. 12C Bus Timing, TDA8442
February 12. 1987
10·106
TDA8443, TDA8443A
Signetics
RGB/YUV Switch
Preliminary Specification
Linear Products
DESCRIPTION
FEATURES
The TDA8443/8443A is intended to be
used in color TV sets which have more
than one base-band video source. The
IC has two sets of inputs. The first
(Inputs 1) is intended for the internal
video signals (R-Y), Y, (B-Y), and the
associated synchronization pulse coming from the color decoder; the second
(Inputs 2) is intended for external video
signals R, G, B, and the associated
synchronization pulse coming from the
accessory inputs. The latter ones (Inputs
2) can also consist of the video signals
(R-Y), Y, (B-Y), and the associated synchronization pulse. The RGB signals at
Inputs 2 can also be matrixed internally
into the luminance signal Y and the
color-difference signals (R-Y) and (B-Y)
before they become available at the
outputs. By means of 12C bus mode or
manual control (control by DC voltages),
one of these inputs can be selected and
will be available at the outputs. The IC
contains three pins for programming the
sub-address; this means that within one
TV set the system can be expanded up
to seven ICs. The TDA8443 is designed
to be used with the CCTV levels, while
the TDA8443A is designed to be used
for the standard decoder signal levels.
• Two RGB/YUV selectable
clamped inputs with associated
sync
PIN CONFIGURATION
• An RGB/YUV matrix
• 3-State switching with an OFF
state
• Four amplifiers with selectable
gain
• Fast switching to allow for mixed
mode
• 12Cor non-1 2C mode (control by
DC voltages)
• Slave receiver in the 12C mode
• External OFF command
• System expansion possible up to
7 devices
ORDER CODE
o to +70'C
TDA8443N
24-Pin Plastic DIP (SOT-101)
o to +70'C
TDA8443AN
ABSOLUTE MAXIMUM RATINGS
PARAMETER
TSTG
Storage temperature range
TA
Operating ambient temperature range
V18-7
Supply voltage
PD
Total power dissipation
UNIT
'C
o to
+70
'C
V
W
Maximum junction temperature
Input voltage range
lOMAX
Maximum output current
February 1987
RATING
-65 to +150
14
VSDA
VSCL
FAST
SWITCH IN
RGB/YUV IN 6Q 4
RGB/YUV IN 6Q 5
RGB/YUV IN 6Q 6
REGULAlOR
DECOUP
lOP VIEW
..
TEMPERATURE RANGE
TJMAX
SYNCIN6Q 2
• TV receivers
• Video switching
24-Pin Plastic DIP (SOT-101)
SYMBOL
SELECTION
IN
APPLICATIONS
ORDERING INFORMATION
DESCRIPTION
N Package
Pin 13
14
other pins
125
'C
-0.3 to 14
-0.3 to 14
-0.3 to Vcc+ 0.3
V
V
V
TBD
mA
10-107
Preliminary Specification
Signetics Linear Products
TDA8443, TDA8443A
RGBfYUV Switch
BLOCK DIAGRAM
OUTPUT
so
\l15
~pI
Vec
_8_
_R_
-(S-V)
-(~~
II
19
CLAMP
liND
n
I~ 22
SYNC
23
CAP
~.
~
--'r----- Foo-----t+---------...Jr-
I"C BUS
INTERFACEJDECOOER
,....-----++++-----IT
I
SUPPLY
1l
t
,---
i
CL
11
Y
10
-(A-V)
INPUTS 1 FROM
f
f~ fl~
-
l
I
CLAMP
PULSE
liEN.
~-Citt
9
ON
8
SYNC
I
67
INT.
SUPPLY
8
8
a:v
I
5
..!!...
Y
4
R
R:Y
A3
F8
INPUTS 2 FAOII
ACCESSORY INPUT
COLOR DECODER
February 1987
'
MATRIX
~~
12
-(S-V)
\-r~-T
10-108
rA2
SYNC
.1. 1
SEL
Preliminary Specification
Signetics Unear Products
TDA8443, TDA8443A
RGB jYUV Switch
DC ELECTRICAL CHARACTERISTICS TA = 25'C and Vec = 12V, unless otherwise specified.
LIMITS
SYMBOL
UNIT
PARAMETER
Typ
Max
13.2
V
TBF
TBF
rnA
Absolute gain difference with respect to programmed value
0
10
%
Relative gain difference between any 2 channels of one input
0
5
%
p.A
Min
V 18 -7
Supply voltage
118
Supply current
10
RGB/YUV channels
liN
Input current
TBF
0.3
ZOUT
Output impedance
TBF
30
n
3dB bandwidth (mode 0 or 2)
10
MHz
3dB bandwidth mode 1
10
MHz
Mutual time difference at output if all inputs of one source are
connected together
Maximum output amplitude of YUV signals
TBF
25
ns
Vp_p
2.8
Crosstalk between inputs of same source, at 5MHz 1
-30
dB
Crosstalk between different sources
-50
dB
Isolation (OFF state) at 10MHz
50
dB
Differential gain at nominal output signals:
R-Y = 1.05Vp_p
B-Y = 1.33Vp.p
Y = 0.34Vp.p
SIN
Signal-to-noise ratio at nominal input
BW
Bandwidth
10
%
dB
50
= 5MHz2
Supply voltage rejection 3
50
dB
5.3
DC level of outputs during clamp
V
Sync channels
Gain difference with respect to programmed value
BW
TBF
3dB bandwidth
Input amplitude of sync pulse for proper operation of clamp
pulse generator
ZOUT
10
0.2
Maximum output amplitude (undistorted)
2.5
DC level on top of sync pulse at output
TBF
MHz
2.5
TBF
Output impedance
%
30
Vp_p
n
Vp_p
1.8
TBF
V
V
12C bus inputs/outputs
SDA input (Pin 13)
SCL input (Pin 14)
VIH
Input voltage High
3
Vcc
VIL
Input voltage Low
-0.3
1.5
V
IIH
Input current High
10
p.A
Input current Low
10
p.A
IlL
SDA output (open-collector)
VOL
Output voltage Low at IO-L = 3mA
IOL
Maximum output sink current
February 1987
0.4
5
10-109
V
rnA
II
Signetics Linear Products
Preliminary Specification
TDA8443, TDA8443A
RGB/yUV Switch
DC ELECTRICAL CHARACTERISTICS (Continued) TA = 25°C and VCC = 12V, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
Sub-address Inputa SO (Pin 15), S1 (Pin 16), S2 (Pin 17)
VIH
Input voltage High
3
Vee
VIL
Input voltage Low
-0.3
0.4
V
IIH
Input current High
TBF
pA
IlL
Input current Low
TBF
pA
V
V
Fast switching pin
VS_7
V3 _ 7
Input voltage High
1
3
Input voltage Low
-0.3
0.4
V
13
Input current High
TBF
pA
pA
13
Input current Low
TBF
Switching delay4
TBF
Switching time 4
TBF
SEL pin
VI_7
Input voltage High
3
Vee
V
VI-7
Input voltage Low
-0.3
0.4
V
11
Input current High
TBF
pA
11
Input current Low
TBF
pA
V
ON pin
V9-7
Input voltage High
3
Vee
Vg_ 7
Input voltage Low
-0.3
1.5
V
Ig
Input current High
TBF
pA
Ig
Input current Low
TBF
pA
NOTES:
1. Crosstalk is defined as the ratio between the output signal originating from another input and the nominal output Signal on the same output.
2. SIN
= 2010g
VoP.p
Va noise RMS B = SMHz
3. Supply voltage rejection
= 2010g
VR supply
--'-'--'-'-'VRon output
4. Fast switching input signal
Output signal: YUV
Input : OV input I, mode 2
0.7SV RGB input 2, mode 1
-.d-.. .---tI••----SWTcHNG
I
I
I
·ilt::~:~. ~-
DELAY----...
I
I~==~--------------------~T\-II
50~rO%
I 40%=r
i
----=....;.;~~.~I.,:"'.>------SWITCHING T l M E - - - -.........I-+1.1--
February 1987
10-110
Preliminary Specification
Signetics Linear Products
TDA8443, TDA8443A
RGB fYUV Switch
FUNCTIONAL DESCRIPTION
The circuit contains two sets of inputs: input 1
from the color decoder (color difference signals), and input 2 from the accessory input,
RGB, or possibly YUV, both with associated
synchronization inputs.
12C BUS MODE
The protocol for the TDAB443 for
mode is:
12C
STA
A6
A5
A4
A3
A2
A1
AO
R/W
The inputs are clamped, thus the clamp pulse
is internally derived from the sync signals.
The outputs can be made high-ohmic (OFF)
R/W
AO
I AC I D7 I D6 I D5
fixed address bits
Sub-address bit set by S2
Sub-address bit set by Sl
Sub-address bit set by SO
Read/Write bit (= a only write mode allowed)
D4
D3
D2
D1
DO
AC
STO
Acknowledge, generated by the TDAB443
MOD1
MODO
mode control bits, see Table 2
I
AC
D7
D6
D5
D4
D3
D2
D1
DO
Star! condition
~J
Control
The circuit can be controlled by an 12 C bus or
directly by DC voltages. The fast switching
input can be operated by Pin 16 of the
accessory input.
bus
I A6 I A5 I A4 I A3 I A2 I A1
STA
in order to be able to put several circuits in
parallel.
In the RGB mode, the signals are matrixed
internally to color difference signals for further processing in a control circuit (e.g.,
TDAB461).
.
~~
} gain control bits, see Table 4
GO
PRIOR, priority bit
ON/OFF bit
ON/OFF active bit
Table 1. Sub-Addressing
ADDRESS SELECT PINS
SLAVE ADDRESS BITS
A2
A1
AO
S2
Sl
SO
a
a
a
a
a
a
a
GND
GND
GND
1
GND
GND
Vcc
1
a
GND
Vce
GND
1
1
GND
Vee
Vee
1
a
Vee
GND
GND
1
a
a
1
Vee
GND
Vee
1
1
a
Vee
Vee
GND
1
1
1
Vee
Vee
Vec
NOTE:
Non-1 2 C bus operation, see Table 5.
Table 2. Mode Control
MOD1
MODO
a
a
a
1
1
1
MODE
FUNCTION
a
Inputs 2 are selected directly
1
1
Inputs 2 are selected via RGBIYUV matrix
a
2
Inputs 1 are selected directly
3
Reserved; not to be used
Table 3. Priority Fast Switching Action
PRIOR
FS
a
x
1
1
OAV
1-3V
February 19B7
MODE SELECTED
As set by mode control (Table 2)
Mode 2
Mode 1 if mode 1 is selected
Mode a if mode a or 2 is selected
10-111
•
Signetics Linear Products
Preliminary Specification
TDA8443, TDA8443A
RGBjYUV Switch
Table 4. Gain Settings (see Block Diagram)
TDA8443A1C3
TDA8443/C3
G2
G1
GO
A1
A2, A3, A4
81,83
81,83
82
0
0
0
1
1
-0.6
-1
0.45
0
0
1
1
1
1
1
1
0
1
0
Reserved; not to be used
0
1
1
1
1
-0.6
-1
0.45
1
0
0
2
2
-0.6
-1
0.45
1
0
1
2
1
1
1
1
1
1
0
2
2
1
1
1
t
1
1
2
1
-0.6
-1
0.45
NOTES:
Matrix eguations: relations between output and input signals of the matrix
Y = 0.3R + 0.59V + O.IIB
R-Y = 0.7R -0.59V-0.llB
B-Y = -0.3R - 0.59V+ 0.89B
ON BIT
ON
FUNCTION
0
OFF, no output signal, outputs high-ohmic
1
ON, normal functioning
OFFACT-ON (Pin 9) Function
OFFACT
ON
0
0
L
H
1
X
February 1987
FUNCTIONING
OFF
In accordance with last defined D7 - Dl (may be entered
while OFF = L)
In accordance with last defined D7 - Dl
10-112
Signetlcs Linear Products
Preliminary Specification
TDA8443, TDA8443A
RGBjYUV Switch
POWER-ON RESET
When the circuit is switched on in the 12C
mode, bits DO - D7 are set to zero.
Table 5. Non-1 2C Bus Mode (S2
CONTROL
SDA
SCL
SEL
= S1 = SO = 0)
GAIN SETTINGS
MODE
SWITCHED
BY FS
TDA8443
TDA8443A
A1
A4, A3, A2
B1, B3
B1, B3
B2
L
L
L
2/0
1
1
1
1
1
L
L
H
2/0
1
2
1
1
1
L
H
L
2/1
1
1
-0.6
-1
0.45
L
H
H
2/0
1
1
-0.6
-1
0.45
H
L
L
2/0
2
1
1
1
1
H
L
H
2/0
2
2
1
1
1
H
H
L
2/1
2
1
-0.6
-1
0.45
H
H
H
2/0
2
1
-0.6
-1
0.45
Fast Switching Input
FS
!.2.,-_ _...,..._ _ _ _, -_ _ _....,.._ _ _....,.._ _ _ _ _ _ _ _ _ _..;.+12=,V
1I
4
r-i---'
Inc I
I~
L_"i
___ I
'50"F toonF
6V
GND
38.
680
2%
...J
-=-
'
~T~onF
GND
"
'-C'"HR""O"'M""A---"'V"'
c c- '
o-_ _ _ _ _......,'~8 R/ILTER
RAMP ~
,
J
2
LUMINANCE 7
GO
RGB
DATA
INPUTS
,.
OUTPUT
3
.
::b
DL'
rvvv-.
910
T
LUMINANCE 8
G'
INPUT
*
--t.1-=J2
4
0------..\80
5
i
100p.F
JlOV
330PF '%
R'
UM'622
ONLY~
TEA2000
3
B'
Ir.----_f_
MODULATOR
M
VIDEO OUTPUT
16 _ _
¥+_.
RX
COMPOSITE 6
cOMPsmco-------~ CSYNC
UHFIVHF
J
'7
COMPBLKo-------~ CBlNK
~
PAlINTSC
1
O- - t - - - 6 -J1_....,9 GND
1
XTALA
n
~
~D~
r·
2.2.
IN914
XTALB
6PF
~
I
100p.F
,OV
,.
MPF
SYMBOL
COMPONENT
SOURCE
L
Inductor
TOKO
C
Capacitor
-=TC20350S
TYPE
NTSC
16"H Q
= 100
100pF
DL,
Delay line
PHILIPS
DL330
DL,
Delay line
PHILIPS
DL270
XTAL
Crystal
UM1632
ASTEC
PAL
15"H Q
= 100
62pF
330"s
2701'S
7,159,090Hz
8,667,236Hz
M
Modulator
UM1632
UM1233
Jl
Jumper
Jumpered
Open
J2
Jumper
Jumper
Open
Rx
Resistor
750
510
Rx
Resistor
510
430
Figure 2. TEA2000 Evaluation System
February 1987
10·124
Signetics Linear Products
Application Note
Applications of the Digital RGB Color Encoder TEA2000
AN1561
TO COLOR ENCODER
FROM DISPLAV GENERATOR
B L A N K I N G W A V E F O R M - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - . CBLNK
COMPOSITE SYNC
•
CSVNC
1
DISPLAV DATA
(4 BITS)
2
1
4
1
MULTIPLEXER
74LS157
0,
Ao
V.
3
Vb
A,
748189
RAM
Vo
A2
16x4BITS
V.
A,
O2
03
2
,......2..
~
0,
WE 0,
0 3 O2
0,
1t
SELECT
-
0,
Ao
748189
RAM
L-.-.- A,
Az
O2
B,
16 x 4 BITS
A,
Ao A, Az A,
RAM ADDRESS
TO LOAD PALETTE
WE
O2
t
06
WRITE
ADDRESS
SELECT
0,
tt
Os
RAM DATA
TO LOAD PALETTE
SIGNALS REQUIRED TO LOAD PALETTE
Figure 3. Diagram of Color Palette, 16 Colors Out of 64, System
February 1987
0403020..
PULSE
10-125
•
Signetics Linear Products
Application Note
Applications of the Digital RGB Color Encoder TEA2000
COMPOSITE VIDEO
OUTPUT
G--+.:.....~
B--...,~""",
TEA2000
CBLNK---.......
CSYNC ----1t-.......
FIELD AND
LlNESVNC
SEPARATOR
Figure 4. Basic Block Diagram for Phase Locking to Horizontal Line Rate
This application note was edited from MuUard MTH8502.
Application of the TEA2000 Color Encoder by
R.C. Eason and J.A. Tijou. June 10, 1985.
February 1987
10-126
AN1561
Signefics
Section 11
Special-Purpose Video
Processing
Linear Products
INDEX
VIDEO MODULATOR/DEMODULATOR
TDA68DD
Video Modulator Circuit........................................................
150MHz Phase-Locked Loop ................................................
NE568
11-3
11-6
AID CONVERTERS
PNA75D9
7-Bit AID Converter. ........................................................... 11-14
AN108
An Amplifying, Level-Shifting Interface for the PNA7509 Video
A/D Converter................................................................... 11-20
TDA57D3
Analog-to-Digital Converter ................................................... 11-21
D/ A CONVERTERS
NE515D/
Triple 4-Bit RGB Video D/A Converter
5151/5152
With and Without Memory ....................................................
AN1D81
NE5150/51/52 Family of Video D/A Converters .......................
PNA7518
B-Bit Multiplying DAC ..........................................................
TDA57D2
B-Bit Digital-to-Analog Converter............................................
SWITCHING
TDA8440
11-25
11-32
11-52
11-56
Video and Audio Switch IC .................................................. 11-60
HIGH FREQUENCY AMPLIFIERS
Video
NE5204
NE/SAI
SE52D5
NE/SE5539
AN140
NE5592
NE/SE592
AN141
p.A733/C
Wide-band High-Frequency Amplifier....................................... 11-66
Wide-band High-Frequency Amplifier ....................................... 11-77
Ultra-High Frequency Operational Amplifier............................... 11-B9
Compensation Techniques for Use With the NE/SE5539 ..... ....... 11-97
Video Amplifier .................................................................. 11-1 03
Video Amplifier .................................................................. 11-1 09
Using the NE592/5592 Video Amplifier ................................... 11-11B
Differential Video Amplifier .................................................... 11-123
CCD MEMORY
SAA9DD1
317k Bit CCD Memory ........................................................ 11-129
•
TDA6800
Signetics
Video Modulator Circuit
Product Specification
Linear Products
0
PIN CONFIGURATION
DESCRIPTION
FEATURES
The TDA6800 is a modulator circuit for
modulation of video signals on a VHF/
UHF carrier. The circuit requires a 5V
power supply and few external components for the negative modulation mode.
For positive modulation an external
clamp circuit is required. This circuit can
be used as a general-purpose modulator
without additional external components.
• Balanced modulator
• Symmetrical oscillator
• Video clamp circuit for negative
modulation
• Frequency range 50 to 800MHz
APPLICATIONS
N, 0 Packages
SOUND
INTER·
CARRIER
IN
0~1:~~~
0~1:~~~
GND
• Video modulators
• General-purpose modulators
8
VlDEOIN
2
7
RF OUT
3
6 RFOUT
4
S Vee
TDPVlEW
• Computers
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
8-Pin Plastic DIP (SOT-97A)
-25'C to 85'C
ORDER CODE
TDA6800N
8-Pin Plastic SO (SOT-96A)
-25'C to + 85'C
TDA6800TD
BLOCK DIAGRAM
RF
OUTPUT
7
SOUND
INTERCARRIER
RF
OUTPUT
6
+sv
Is
1
INPUT
MODULATOR
VIDEO INPUT
8
CLAMP
OSCiLLATOR
3
2
OSCILLATOR
TANK CIRcurr
January 14, 1987
11-3
t
853-1148 87202
Signetics Linear Products
Product Specification
TDA6800
Video Modulator Circuit
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
Vee
Supply voltage
7
V
Va_4
Input voltage
4
V
V6, 7-4
Output voltage
9
V
-65 to +150
·C
TSTG
Storage temperature
TJ
Junction temperature
TA
Operating ambient temperature range
()JA
125
'c
-65 to +85
·C
260
120
'C/W
·C/W
Thermal resistance Irom junction to
ambient in Iree air
TDA6800T
TDA6800
DC AND AC ELECTRICAL CHARACTERISTICS Vee = 5V; TA = 25'C; unless otherwise specilied.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Vee
Supply voltage range
Typ
4.5
Max
5.5
V
13
rnA
Icc
Supply current consumption
Va(p.P)
Video input voltage
Ra
Input impedance
Va
Voltage (DC) at video input (clamp voltage)
1.4
V1
Voltage (DC) at sound input
2.5
V
V6 - 7
Output voltage I = 50MHz; Rl = 75n
13
mV
V6 - 7
Output voltage 1= 600MHz; Rl = 75n
10
~
Differential gain
10
%
Il¢
Oifferential phase
10
deg.
IlF
Frequency shift VB = 5%, 1= 600MHz
9
1
V
30
Intermodulation 1 (1.1 MHz)
kn
-80
V
mV
-60
dB
100
kHz
IlF
Frequency shift VB = 5%, I = 800M Hz
IlF
Frequency drift 25 to 40'C
100
kHz
IlF
Frequency drift 15 to 55'C
300
kHz
TBD
kHz
Positive modulation (see Figure 2)
VA
Residual carrier voltage
a:
Cross modulation2
NOTES:
1. Input signal:
2.
DC 0.45V (VB-4 = 1.85V)
4.4MHz; input voltage (P-P)
5.5MHz; input voltage (P-P)
0.1
= O.SV
= 1.26V
measured with respect to picture carrier. at f =- 600MHz.
Input signal: DC I V (VB _ 4 = 3.5V)
5.5MHz AM modulated, 1M - 100kHz
m = 0.8; input voltage (P-P) - 2.27V (including modulation)
measured with respect to the picture carrier, at f = 600MHz.
January 14, 1987
11-4
2,5
%
0,25
%
Signetics Linear Products
Product Specification
TDA6800
Video Modulator Circuit
VIDEO----II-----------,
Irm;RC~~: - - - - f
300
----+------ Vee; 5V
330k
j..::..........
r
·CLOSE TO OUTPUT
TRANSFORMER
Figure 1. Application for Negative Modulation
VIDEO----II----------y--A
INTERC':~~~ - - - - f
300
330k
............----+------ Vee; 5V
r
·CLOSE TO OUTPUT
TRANSFORMER
•
Figure 2. Application for Positive Modulation
MODULATION
Ir--.!
H~
7
~330k
~
6
-fr-'"~n.
5
Vee; 5V
±
·CLOSE TO OUTPUT
TRANSFORMER
Figure 3. Application for General-Purpose Modulation
January 14, 1987
11-5
TC21001S
NE568
Signetics
150MHz Phase-Locked Loop
Preliminary Specification
Linear Products
DESCRIPTION
FEATURES
The NE568 is a monolithic phase-locked
loop (PLL) which operates from 1Hz to
frequencies in excess of 150MHz. The
integrated circuit consists of a limiting
amplifier, a current-controlled oscillator
(lCO), a phase detector, a level shift
circuit, VII and IIV converters, an output
buffer, and bias circuitry with temperature and frequency compensating characteristics. The design of the NE568 is
particularly well-suited for demodulation
of FM signals with extremely large deviation in systems which require a highly
linear output. In satellite receiver applications with a 70MHz IF, the NE568 will
demodulate ± 10% deviations with less
than 4.0% non-linearity (1.5% typical). In
addition to high linearity, the circuit has a
loop filter which can be configured with
series or shunt elements to optimize
loop dynamic performance. The NE568
is available in 20-pin dual in-line and 20pin SO (surface-mounted) plastic packages.
• Operation to 150MHz
• High linearity buffered output
• Series or shunt loop filter
component capability
• Temperature compensated
PIN CONFIGURATION
D, N Packages
APPLICATIONS
•
•
•
•
Satellite receivers
Fiber-optic video links
VHF FSK demodulators
Clock recovery
INPBYP
VIN
TOP VIEW
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
o to
o to
20-Pin Plastic SOL Package
20-Pin Plastic DIP
ORDER CODE
+70·C
NE568D
+70·C
NE568N
BLOCK DIAGRAM
LF1
LF2
LF3
LF4
11
10
GND2
February 1987
GND!
TCAP1
TCAP2
GND!
11-6
VCC1
REFBVP
PNPBVP
INPBVP
Signetics Linear Products
Preliminary Specification
NE568
150MHz Phase-Locked Loop
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
PARAMETER
Vee
Supply voltage
TA
Operating free-air ambient temperature range
6
o to
+70
UNIT
V
·C
·C
TJ
Junction temperature
TSTG
Storage temperature range
-65 to +150
·C
PDMAX
Maximum power dissipation
500
mW
ELECTRICAL
CHARACTERISTICS
The electrical characteristics listed below are
actual tests (unless otherwise stated) per-
+150
formed on each device with an automatic IC
tester prior to shipment. Performance of the
device in automated test setup is not necessarily optimum. The NE566 is layout-sensitive.
Evaluation of performance for correlation to
the data sheet should be done with the circuit
and layout of Figures 1 - 3 with the evaluation
unit soldered in place. (Do not use a socketl)
DC ELECTRICAL CHARACTERISTICS TA = 25·C, Vee = 5V, fo = 70MHz, Test Circuit Figure 1,
fiN = -20dBm, R4 =
on
(ground), unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Min
Vee
Supply voltage
Icc
Supply current
4.75
Typ
Max
5
5.25
V
60
75
mA
•
February 1967
11·7
Preliminary Specification
Signetics Linear Products
NE568
150MHz Phase-Locked Loop
AC ELECTRICAL CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
UNIT
TEST CONDITIONS
Min
fosc
1.5
mVp_p
dBm'
MHz
fol7
Dev = ± 10%, Input = -20dBm
Dev = ±20%, Input = -20dBm
Dev = ± 20%, Input = + 10dBm
4.0
5.5
5.5
%
Lock range 2
Input = -20dBm
±25
±35
% of fo
Capture range 2
Input = -20dBm
±20
±30
% of fo
100
ppmfOC
Figure 1
TC of fo
RIN
MHz
2000
+10
50
_20 1
Demodulated bandwidth
Non-linearityS
Max
150
Maximum oscillator operating frequency3
Input signal level
BW
Typ
Input resistance 4
1
Output impedance
Demodulated VOUT
AM rejection
fo
Distribu1ion6
fo
Drift with supply
Dev = ± 20% of fo
measured at Pin 4
0.45
VIN = -20dBm (30% AM)
OdBm (30% AM)
referred to ± 20% deviation
Centered at 70MHz, R2 = 1.2kn,
C2 = 17pF, R4 = on
(C2 + CSTRAY = 20pF)
4.75V to 5.25V
-15
kn
6
n
0.52
Vp_p
30
50
dB
0
1
+15
%
%IV
NOTES:
1.
2.
3.
4.
5.
Signal level to assure all published parameters. Device will continue to function at lower levels with varying performance.
Limits are set symmetrical to fo. Actual characteristics may have asymmetry beyond the specified limits.
Not 100% tested, but guaranteed by design.
Input impedance depends on package and layout capaCitance. See Figures 4 and 5.
Linearity is tested with incremental changes in input frequency and measurement of the DC output voltage at Pin 14 (Vour). Nonlinearity is then
calculated from a straight line over the deviation range specified.
6. Free-running frequency is measured as feedthrough to Pin 14 (Vour) with no input signal applied.
February 1987
11-8
Signetics Linear Products
Preliminary Specification
NE568
150MHz Phase-Locked Loop
~C1
veC2
LFl
GND2
LF2
GND1
LF3
':"
':"
II
RFCI
TCAP1
LF4
TCAP2
FREQAOJ
C2
NES68
GND1
OUTFILT
VeCl
REPBYP
Vee
PNPBYP
TCAOJ1
INPBYP
~C7
Figure 1. Test and Application Circuit
•
February 1987
11-9
Signetics Linear Products
Preliminary Specification
150MHz Phase-locked loop
FUNCTIONAL DESCRIPTION
The NE568 is a high-performance phaselocked loop (PLL). The circuit consists of
conventional PLL elements, with special circuitry for linearized demodulated output, and
high-frequency performance. The process
used has NPN transistors with fT > 6GHz.
The high gain and bandwidth of these transistors make careful attention to layout and
bypass critical for optimum performance. The
performance of the PLL cannot be evaluated
independent of the layout. The use of the
application layout in this data sheet and
surface-mount capacitors are highly recommended as a starting paint.
The input to the PLL is through a limiting
amplifier with a gain of 200. The input of this
amplifier is differential (Pins 10 and 11). For
single-ended applications, the input must be
coupled through a DC-blocking capacitor with
low impedance at the frequency of interest.
The single-ended input is normally applied to
Pin 11 with Pin 10 AC-bypassed with a lowimpedance capacitor. The input impedance is
characteristically slightly above soon. Impedance match is not necessary, but loading the
signal source should be avoided. When the
source is 50 or 75n, a DC-blocking capacitor
is usually all that is needed.
Input amplification is low enough to assure
reasonable response time in the case of large
signals, but high enough for good AM rejection. After amplification, the input signal
drives one port of a multiplier-cell phase
detector. The other port is driven by the
current-controlled oscillator (ICO). The output
of the phase comparator is a voltage proportional to the phase difference of the input and
February 1987
NE568
ICO signals. The error signal is filtered with a
low-pass filter to provide a DC-correction
voltage, and this voltage is converted to a
current which is applied to the ICO, shifting
the frequency in the direction which causes
the input and ICO to have a 90° phase
relationship.
The oscillator is a current-controlled multivibrator. The current control affects the charge!
discharge rate of the timing capacitor. It is
common for this type of oscillator to be
referred to as a voltage-controlled oscillator
(VCO), because the output of the phase
comparator and the loop filter is a voltage. To
control the frequency of an integrated ICO
multivibrator, the control signal must be conditioned by a voltage-to-current converter. In
the NE568, special circuitry predistorts the
control signal to make the change in frequency a linear function over a large controlvoltage range.
The free-running frequency of the oscillator
depends on the value of the timing capacitor
connected between Pins 4 and 5. The value
of the timing capacitor depends on internal
resistive components and current sources.
When A2 = 1.2kn and A4 = on, a very close
approximation of the correct capacitor value
is:
0.0014
C'=-- F
fo
where
C' = C2 + CSTRAY.
The temperature-compensation resistor, A4,
affects the actual value of capacitance. This
equation is normalized to 70MHz. See Figure
6 for correction factors.
11-10
The loop filter determines the dynamic characteristics of the loop. In most PLLs, the
phase detector outputs are internally connected to the ICO inputs. The NE5S8 was
designed with filter output to input connections from Pins 20 (rJ> DET) to 17 (ICO), and
Pins 19 (rJ> DET) to 18 (lCO) external. This
allows the use of both series and shunt loopfilter elements. The loop constants are:
Ko = 0.127V!Aadian (Phase Detector
Constant)
Aadians
Ko = 4.2 X 109 - - - (ICO Constant)
V-sec
The loop filter determines the general characteristics of the loop. Capacitors Cg, C1Q, and
resistor At, control the transient output of the
phase detector. Capacitor Cg suppresses
70MHz feedthrough by interaction with lOOn
load resistors internal to the phase detector.
Cg
1
21T (50)(fo)
F
At 70MHz, the calculated value is 45pF.
Empirical results with the test and application
board were improved when a 56pF capacitor
was used.
The natural frequency for the loop filter is set
by CtO and At. If the center frequency of the
loop is 70MHz and the full demodulated
bandwidth is desired, i.e., fBW = fol7
= 10MHz, and a value for At is chosen, the
value of C1Q can be calculated.
Signetics Linear Products
Preliminary Specification
150MHz Phase-locked loop
NE568
PARTS LIST AND LAYOUT 70MHz APPLICATION NE568D
C,
100nF
±10%
Ceramic chip
1206
0805
C2'
18pF
±2%
Ceramic chip
cl
34pF
±2%
Ceramic OR chip
C3
100nF
±10%
Ceramic chip
1206
C4
100nF
±10%
Ceramic chip
1206
Cs
6.81lF
±10%
Tantalum
35V
C6
100nF
± 10%
Ceramic chip
1206
1206
C7
100nF
±10%
Ceramic chip
Ca
100nF
±10%
Ceramic chip
1206
Cg
56pF
±2%
Ceramic chip
0805 or 1206
C' 0
560pF
±2%
Ceramic chip
0805 or 1206
C11
47pF
±2%
Ceramic chip
0805 or 1206
C '2
100nF
± 10%
Ceramic chip
1206
C '3
100nF
±10%
Ceramic chip
1206
R,
27n
± 10%
Chip
YaW
R2
2kn
Trim pot
YaW
R 33
43n
±10%
Chip
YaW
R44
4.5kn
±10%
Chip
YaW
RS3
50n
± 10%
Chip
YaW
RFC,5
10llH
±10%
Surface mount
RFC25
10llH
±10%
Surface mount
NOTES:
+ eSTRAY ~ 20pF.
= 36pF for temperature-compensated configuration
3. For SOn setup. R, ~ 62n, R3 ~ 7Sn for 75n application.
4. For test configuration R4 ~ on (GND) and e 2 ~ 18pF.
1.
e2
2. C 2 + eSTRAY
with R4
= 4.5kn.
5. On chip resistors Gumpers) may be substituted with minor degradation of performance.
For the test circuit, R, was chosen to be 27n.
The calculated value of C10 is 590pF; 560pF
was chosen as a production value. (In actual
satellite receiver applications, improved video
with low carrier/noise has been observed
with a wider loop-filter bandwidth.)
A typical application of the NE568 is demodulation of FM signals. In this mode of operation, a second single-pole filter is available at
Pin 15 to minimize high frequency feedthrough to the output. The roll-off frequency is
set by an internal resistor of 350n ± 20%,
and an external capacitor from Pin 15 to
ground. The value of the capacitor is:
C~
1
21T (350)f Bw
Two final components complete the active
part of the circuitry. A resistor from Pin 12 to
ground sets the temperature stability of the
circuit, and a potentiometer from Pin 16 to
ground permits fine tuning of the free-running
oscillator frequency. The Pin 16 potentiometer is normally 1.2kn. Adjusting this resistance controls current sources which affect
the charge and discharge rates of the timing
capacitor and, thus, the frequency. The value
of the temperature stability resistor is chosen
from the graph in Figure 6.
The final consideration is bypass capacitors
for the supply lines. The capacitors should be
ceramic chips, preferably surface-mount
types. They must be kept very close to the
device. The capacitors from Pins 8 and 9
return to VCG1 before being bypassed with a
separate capacitor to ground. This assures
that no differential loops are created which
might cause instability. The layouts for the
test circuits are recommended.
(Shown at 82% of original size.)
a. Component Side Top of Board
b. Bac;k of Board
NOTES:
1. Board is laid out for King BNG Connector PIN KC-79-243-M06 or equivalent. Mount on bottom (back) of board. Add stand-off in each corner.
2. Back and top side ground must be connected at 8 point minimum.
Figure 2
February 1987
11-11
F
Signetics Linear Products
Preliminary Specification
150MHz Phase-Locked Loop
NE568
PARTS LIST AND LAYOUT 70MHz APPLICATION NE568N
C1
100nF
±10%
Ceramic chip
C2 1
17pF
±2%
Ceramic OR chip
50V
50V
cl
34pF
±2%
Ceramic chip
0805
C3
100nF
±10%
Ceramic chip
50V
C4
100nF
±10%
Ceramic chip
50V
Cs
6.8/lF
±10%
Tantalum
35V
C6
100nF
±10%
Ceramic OR chip
50V
C7
100nF
±10%
Ceramic chip
50V
Ca
100nF
±10%
Ceramic chip
50V
C9
56pF
±2%
Ceramic chip
SOV
ClO
560pF
±2%
Ceramic chip
50V
Cll
47pF
±2%
Ceramic OR chip
50V
C12
100nF
±10%
Ceramic OR chip
50V
C13
100nF
±10%
Ceramic OR chip
50V
R1
27n
±10%
Carbon
Y4W
R2
2kn
R33
43n
±10%
Trim pot
Carbon
Y4W
R44
4.5kn
±10%
Carbon
Y4W
Carbon
Y4W
Rs3
50n
±10%
RFC1
10/lH
±10%
RFC2
10/lH
±10%
NOTES:
1. e 2 + eSTRAY = 20pF for test configuration with R4 = 0.11.
2. 2 = 34pF for temperature-compansated configuration with R4 = 4.5k.l1.
3. For 50.11 setup. R t = 62.11; Ra = 75.11 for 75.11 applications.
4. For test configuration R4 = 0.11 (GND) and e 2 = 17pF.
e
.
••
,.... ••
• ••
.;.
-
"."
(Shown at 82% of original size.)
III!
~&ll
mn·m··. o
':'
• • .-...- •
I __• e
•
I
::ll)
.~ ~
--
,.,
~
1!111
a_ Component Side for Leaded Components
b_ Solder Side of Board and Chip Capacitors
NOTES:
1. Board is laid out for King BNC Connector PIN KC-79-243-M06 or equivalent mounted on the component side of the board.
2. Component side and solder side ground planes must be connected at 8 points minimum.
Figure 3
February 1987
-_ ..
11-12
Preliminary Specification
Signetlcs Linear Products
NE568
150MHz Phase-Locked Loop
1.25E3
7k
1~r-----~------'------'
1.0E3
~ t=1-:::::~"~;;:-'_"
.-...,,\:-+---l
"\
i
0.0
100.0
FREQUENCY (MHz)
250.0
"
76.29
75
... 73.17
...~.
·v V '-
lk
/
o
O.O~----~------~----~
1.0
10.0
100.0
1.0E3
o
C,=60pF
Y
-I 1
10 20 30 40 50 60 70 60 90 100
fI.rc(PINl2)Y8'.
FREQUENCY (MHz)
Figure 5. NES68 Input Impedance With
CP = 1.49pF 20-Pln Dual In-Line Plastic
Package
Figure 6
4.0
II\.
/
i. 70.6070
"-
3.5
'" "-
g 68.09
66.09
65
64.48
~/lh
1.15
N
I}
I
3.Q
V
r---..
II3J)
1.05 1.10
t- V
/
2k C,=lJPF
"-
o
60
-I
~ 3k
\------1-------+"'----1
C ~17PFI
prN12=GND
"-
C.=47pF
e;.
\
Figure 4. NES68 Input Impedance With
CP = O.SpF 20-Pln SO Package
60
78.72
z
~ soo.or------+----~\~\--'\----'
~
250.0
'.
r-
~ 4k
,~\.
RI~\\
Co
i\
10.0
C,~34~F
5k
75D.01.OE3
z,. \
1.0
6k
2.5
1.20 US UO 1.35 1.40
FREQ.ADJ(Icll)
o
10 20 30 40 50 60 70 60 90 100 110 120
TYPICAL OUTPIIT LINEARITY
71.64 68.71 67.28 114.54 112.08 58.70 51.55 55.53
OP17060S
'cclmAl
·27.33 ·27A4 ·27.56 ·27.83 ·:18.10 ·28.50 .28.97 .29.48
Yeo LEVEL IdBm)
OPl8010S
Figure 7. Typical Veo Frequency
February 1987
YS R2
Figure 8. Typical Output Unearlty
Adjustment
11-13
•
Signetics
PNA7509
7-Bit Analog-to-Digital
Converter
Preliminary Specification
Linear Products
DESCRIPTION
FEATURES
The PNA7509 is a monolithic NMOS 7bit analog-to-digital converter designed
for video applications. The device converts the analog input signal into 7-bit
binary coded digital words at a sampling
rate of 22M Hz.
• 7-blt resolution
• 22MHz clock frequency
• No external sample and hold
required
• High Input Impedance
• Binary or two's complement
3-State TTL outputs
• Overflow and underflow 3-State
TTL outputs
• Low reference current (2501lA
typ.)
• Positive supply voltages (+5V,
+10V)
.
The circuit comprises 129 comparators,
a reference resistor chain, combining
logic, transcoder stages, and TTL output
buffers which are positive edge-triggered
and can be switched into 3-8tate mode.
The digital output is selectable in two's
complement or binary coding.
The use of separate outputs for overflow
and underflow detection facilitates fullscale driving.
_. ..-
PIN CONFIGURATION
D, N Packages
voo
VDD
NC
CE2
V... L
v..
CEi
UNFL
• Low power consumption (400mW
typ.)
• Available In SO Package
arro
BITS
BLOCK DIAGRAM
BIT 1
BITZ
'CLK
v••
DGND
REFERENCE
IIGIf
lV.....
CLOCK INPUT TWO'8 ......".
COIIPLI!IIENT
'cud
IIITCI
mea
--
. DESCRIPTION
V,N
AGND
Voo
VREFH
8TC
OVFL
bn 6
bn 5
bn 4
bit 3
bn 2
Voo
DGND
Analog voltage input
Analog ground
Positive supply voltage (+ 5V)
Reference voltage HIGH
Select two's complement
4
7 lISa
BlTI
BITS
,.
ROM
12'1'x 7
BIT,
DIGITAL
BIT.
VOL""'
.
CIUTPUTS
(VO)
11
I.
II
BIT.
,.
'eLK
bit 1
bit 0
UNFL
mIT
overflow
Most-slgnificant bn (MSB)
POBniVe supply voltage (+ 5V)
Digital ground
22MHz clock input
Least·slgnlficant bn (LSB)
Underflow
V••
Chip enable Input 1
Back bias output
VREFL
Reference voltage LOW
CE2
NC
Voo
VDO
Chip enable input 2
Not connected
poonlve supply voltage (+ 5V)
POsitive supply voltage (+ 10V)
BIT 1
APPLICATIONS
BlTO
-
•
•
•
•
•
17 LOB
lD06701$
February 1987
SYMBOL
1
2
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
OVERFLOW
..
PIN NO.
11-14
High-speed AID conversion
Video signal digitizing
Radar pulse analysis
High energy physics research
Transient signal analysis
Preliminary Specification
Signetics Uneer Products
PNA7509
7-Bit Analog-to-Digital Converter
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
24-Pin Plastic DIP
24-Pin Plastic SO (SOT-101)
o to
o to
ORDER CODE
+70·C
PNA7509N
+70·C
PNA7509D
ABSOLUTE MAXIMUM RATINGS
RATING
UNIT
Voo
Supply voltage range (Pins 3, 12, 23)
7
V
Voo
Supply voltage range (Pin 24)
12
V
VIN
Input voltage range
7
V
VOUT
Output current
5
mA
400
mW
-65 to +150
·C
SYMBOL
PARAMETER
Po
Power dissipation
TSTG
Storage temperature range
TA
Operating ambient temperature range
o to
+70
·C
•
February 1987
11-15
Signetics Linear Products
Preliminary Specification
7-Bit Analog-to-Digital Converter
PNA7509
DC ELECTRICAL CHARACTERISTICS Voo = V3, 12, 23-13 = 4,5 to 5.5V; Voo = V24 -2 = 9.5 to 10.5V; CBB = 100nF; TA = 0
to + 70·C, unless otherwise specified.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
Supply
Voo
Voo
Supply voltage (Pins 3, 12, 23)
Supply voltage (Pin 24)
100
100
Supply current (Pins 3, 12, 23)
Supply current (Pin 24)
4.5
9.5
5.5
10.5
V
V
60
10
TBD
TBD
rnA
rnA
Reference voltages
VREFL
VREFH
Reference voltage LOW (Pin 20)
Reference voltage HIGH (Pin 4)
2.4
5.0
2.5
5.1
2.6
5.2
V
V
IREF
Reference current
175
250
375
rnA
-0.3
3.0
0.8
5.5
V
V
0
2.0
0.8
5.5
V
V
TBD
TBD
100
100
/lA
/lA
10
/lA
Inputs
VIL
VIH
VIL
VIH
-15,21
118
III
Clock input (Pin 14)
Input voltage LOW
Input voltage HIGH
Digital input levels (Pins 5, 18, 21)"
Input voltage LOW
Input voltage HIGH
Input current
at Vs, 21-13=OV
at V18_13=5V
Input leakage current
(except Pins 5, 18, 21)
Analog Input levels (Pin 1)
at VREFL = 2.5V; VREFH = 5.1V
VIN
VIN
VI-VREFL
VI-VREFH
Input voltage amplitude
(peak-to-peak value)
Input voltage (underflow)
Input voltage (overflow)
Offset input voltage (underflow)
Offset input voltage (overflow)
C1,2
Input capacitance
VIN p.p
2.6
V
2.5
5.1
10
-10
V
V
mV
mV
TBD
60
pF
0
-0.4
V
2.4
Voo
V
Outputs
VOL
VOH
Digital voltage outputs
(Pins 6 to 11 and 15 to 17)
Output voltage LOW
at 10=2mA
Output voltage HIGH
at -10 = 0.5mA
·When Pm 5 IS LOW, binary coding IS selected.
When Pin 5 is HIGH, two's complement is selected.
If Pins 5, 18 and 21 are open-circuit. Pins 5, 21 are HIGH and Pin 18 is LOW.
For output coding see Table 1; for mode selection see Table 2.
February 1987
11-16
Signetics Linear Products
Preliminary Specification
7-Bit Analog-to-Digital Converter
AC ELECTRICAL CHARACTERISTICS
PNA7509
voo = V3, 12,23-13 = 4.5 to 5.5V; Voo = V24 -2 = 9.5 to 10.5V; VREFL = 2.5V;
VREFH = 5.1V; ICLK = 22MHz; Css = 100nF; T A = 0 to + 70'C, unless otherwise
specilied.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
Timing (see also Figure 1)
fCLK
tLOW
tHIGH
Clock input (Pin 14)
clock Irequency
clock cycle time LOW
clock cycle time HIGH
tR
tF
Input rise and lall times 1
rise time
lall time
BW
dG
dp
PE
SIN
10
12nd
13rd
14th
15th
16th
17th
10
12nd
13rd
14th
15th
f6th
17th
tHOLO
to
lev
tpo
tOT
COL
INL
DNL
1
20
20
Analog input1
Bandwidth (- 3 dB)
at VI _ 2(P.P) = 2.2V
Differential gain
at II = ,,;; 4.5MHz2
Differential phase
at II = ,,;; 4.5MHz2
Phase error
at II = ,,;; 4.5MHz3
Signal-to-noise ratio
at VI _ 2(P.P) = 2.2V;
II = ";;4.5MHz; B = ± 1 MHz
Harmonics
at VI - 2(P_P) = 2.2V;
II = 3.6MHz
Fundamental
2nd harmonic
3rd harmonic
4th harmonic
5th harmonic
6th harmonic
7th harmonic
Harmonics
at VI - 2(P.P) = 2.2V;
fl = 4.5MHz
Fundamental
2nd harmonic
3rd harmonic
4th harmonic
5th harmonic
6th harmonic
7th harmonic
Digital outputs 2, 4
Output hold time
Output delay time
Internal delay
Propagation delay time
at leLK = 20.25MHz
3-State delay time (see Figure 2)
Capacitive output load 2
Transfer function
Non-linearity
integral
differential
22
MHz
ns
ns
3
3
ns
ns
10
MHz
5
%
5
deg
±10
deg
36
6
154
tSF
0
dB
0
0
tbd
tbd
tbd
tbd
tbd
tbd
dB
dB
dB
dB
dB
dB
dB
0
0
tbd
tbd
tbd
tbd
tbd
tbd
dB
dB
dB
dB
dB
dB
dB
15
20
3
28
ns
ns
clocks
10
176
20
15
ns
ns
pF
±1
LSB
LSB
± 1/2 = 0.4%
NOTES:
1. Clock input rise and fall times are at the maximum clock frequency (10% and 90% levels).
2. Low frequency sine wave (peak-to-peak value of the analog input voltage at VIN = 1.BV) amplitude modulated with a sine wave voltage (V IN = O.7V) at
fl ~4.5MHz.
3. Sine wave voltage with increasing amplitude at 11 ~ 4.5MHz (minimum amplitude VIN = O.25V; maximum amplitude VIN = 2.5V).
4. The timing values of the digital output Pins 6 to 11 and 15 to 17 are measured with the clock input reference level at 1.5V.
February 1987
11-17
•
Preliminary Specification
Signeties Linear Products
PNA7509
7-Bit Analog-to-Digital Converter
Table 1. Output Coding (VREFL = 2.5V; VREFH
= 5.1V)
BINARY
Bit 6-Bit 0
Table 2. Mode Selection
TWO's
COMPLEMENT
Bit 6- Bit 0
CEl CE2
STEP
Vl,2
(Typ)
UNFL
OVFL
Underflow
0
1
< 2.51
2.51
2.53
1
0
0
0
0
0
0 0 0 0 0 0 0 1 0 0 0 0 0 0
0 0 0 0 0 0 0 1 0 0 0 0 0 0
0 0 0 0 0 0 1 1 0 0 0 0 0 1
126
127
Overflow
5.03
5.05
>5.07
0
0
0
0
0
1
1 1 1 1 1 1 0 0 1 1 1 1 1 0
X
0
0
1
1
1
BIT 0
to BIT 6
High
impedance
Active
High
impedance
CLOCK INPUT
- - t - - f - - - REFERENCE LEVEL
(PIn 14)
(1.5V)
ANALOG INPUT
(PIn 1)
- - 2.4V
DIGITAL OUTPUTS
to 11 and 1510 17)
--OAV
Figure 1. Timing Diagram
CHIP ENABLE
INPUTCE2
_ _ _ _ _ _ _ _ REFERENCE LEVEL
(1.5V)
(Pin 21)
_=""~.-- 2AV
DIGITAL OUTPUTS
(PIns 6
to 11 and 15 to 17) " " " " " " . ,
" " ' ' ' ' ' ' ' ' ' ' ' ' ' - - MV
Figure 2. Timing Diagram for 3·Slale Delay
February 1987
High
impedance
Active
Active
1 1 1 1 1 1 1 0 1 1 1 1 1 1
1 1 1 1 1 1 1 0 1 1 1 1 1 1
CLOCK INPUT
(PIns 6
UNFL,OVFL
11·18
Signetics Linear Products
Preliminary Specification
7-Bit Analog-to-Digital Converter
,,
PNA7509
OVFL
B7
B6
V,N
as
~,
O.11L F
- ....
B4
PNA7509
B3
1O.uF LM336
~
F ~ ~-:
B2
2k·2Ok
Bl
~~
BO
CEl
1
I
CE2 OVFL
-
V,N
10k
PNA7509
CEl
-
~
1
Figure 3
•
February 1987
11-19
Signetics
AN108
An Amplifying, Level-Shifting
Interface for the PNA7509
Video AID Converter
Linear Products
Application Note
Author: Nick Gray
the effects of any stray capacitance. If AI is
arbitrarily chosen. AF is found to be
The NE5539 is well-suited for use as a levelshifting amplifier at the input of the PNA7509
video speed analog-to-digital converter. Designing this circuit is straightforward and relatively simple.
The first step is to determine the gain that is
required. Since the PNA7509 requires a maximum input of 5.0 VDC and a minimum input of
2.5VDC the required amplifier gain is
where VMAX is the maximum level of the
amplifier input signal. and VMIN is the minimum level of the amplifier input signal.
This gain must be greater than unity as the
gain of a non-inverting amplifier such as this
is
Av = I + (AF/AI).
The ratio of AF to AI is then
AF/AI=Av- l .
The task is now to select AF and AI. These
resistors should be low enough to swamp out
The required offset voltage. Yo. is then found
to be
Vo = VMAX - [(5 - VMAX) (AI/AF)]·
Because the NE5539 input cannot be driven
closer to its negative supply than about 4.7V.
that negative supply must be -4.7V or more
negative in order to accommodate an input
signal whose minimum potential is OV. The
NE5539 output must never come any closer
to the supply rail than about 5.5V. and the
maximum output required to drive the
PNA7509 is 5V. so the positive supply must
be at least 5 + 5.5V. or 10.5V. If we use
standard power supply potentials of + 12V
and -5V. this would satisfy these requirements. except we must insure that the negative supply is at least as negative as - 4. 7V.
Tests have been conducted that indicate
satisfactory operation with the positive supply
between 10.5V and 13.5V. and the negative
supply between -4.7V and -5.7V. Furthermore. because the NE5539 is sensitive to
unbalance in the supplies. it is necessary to
insure that its Pin 7 potential is close to
halfway between the positive and the negative supply. Two resistors and an op amp
driving Pin 7 nicely provide this balance.
Another op amp is used to set the offset
voltage.
The three diodes are used to drop the 12V
supply to 10V for the PNA7509. If available
and desired. a separate 10V supply could be
used without the diodes.
Other components are shown for the convenience of the user. The potentiometer at Pin 5
of the NE5514 is used to adjust Yo. The
potentiometer at Pin 12 of the NE5514 sets
the voltage at the low end of the PNA7509
reference ladder. so is a zero-scale adjustment. The potentiometer at Pin 3 of the
NE5514 sets the high end voltage on the
PNA7509 reference ladder and is. effectively.
a full-scale adjustment. It is also possible to
use a signal divider at the NE5539 input for
full-scale adjustment. AF can also be made
variable to provide full-scale adjustment. Care
should be exercised. however. when introducing potentiometers into feedback loops or
into high-frequency signal paths.
The NE5514 was chosen for its low input
offset voltage temperature coefficient.
.,.
",.
0.1
~1 ".
-=-
1.'
OFL
20
(Z.s.)
MSO
R,
R,
2.7K
10
PNA7S07
11
15
16
SIG.IN.@-t-....;j,"--+""---!j
LSO
UFL
13
19
",.
01
J
14
15MHz
TTL CLOCK
-5'
-5'
NOTE:
·Pln 5 should be grounded for binary output, or tied to a logiC high for two's complement output.
February 1987
11-20
TDA5703
Signetics
Analog-to-Digital Converter
Preliminary Specification
Linear Products
DESCRIPTION
The TDA5703 is an a-bit analog-to-digital converter (ADC) designed for video
and professional applications. The
TDA5703 converts the analog input signal into a-bit binary-coded digital words
at a sampling rate of up to 25M Hz.
FEATURES
•
•
•
•
8-bit binary coded resolution
Digitizing rates up to 25MHz
Internal reference
Only 3 external capacitors
required
• Two voltage supply connections:
-analog +5V
- digital + 5V
• 1V full-scale analog input (75U
external resistor tied to VCC1)
• Full-scale bandwidth; 10.5MHz at
3dB
• Low power consumption;
typically 250mW
PIN CONFIGURATION
N Package
NC
NC
NC
• 24-lead plastic DIP
NC
BIT 8
APPLICATION
BIT7
• Video data conversion
BIT 2
BIT 3
ORDERING INFORMATION
DOND
DESCRIPTION
TEMPERATURE RANGE
24-Pin Plastic DIP (SOT-l01 BE17)
o to
ORDER CODE
+ 70·e
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
VCCI
VCC2
Supply voltages
at Pin 4
at Pin 6
8
8
V
V
VIN
Input voltage
at Pins 1 and 5
8
V
lOUT
10
Output current
at Pins 9, 10, 11, 13,
14, 15, 16 and 17
10
mA
TSTG
Storage temperature range
TJ
Junction temperature
TA
Operating ambient temperature range
February 1987
TOP VIEW
TDA5703N
-65 to + 150
·e
+125
·e
o to +70
·e
11-21
PIN
NO.
1
2
3
SYMBOL
V,
AGND
AIR
VCC1
felK
VCC2
NC
NC
Bit 1
Bit 2
Bit 3
DGND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
NC
NC
NC
NC
C,
C,
24
C,
DESCRIPTION
Analog voltage input
Analog ground
Analog input reference
Analog supply voltage
Clock input
Digital supply voltage
Not connected
Not connected
Least significant bit (LSB)
Digital ground
Most significant bit (MSB)
Not connoctod
Not connected
Not connected
Not connected
Oecoupling for internal
reference
•
Signetics Linear Products
Preliminary Specification
Analog-to-Digital Converter
TDA5703
BLOCK DIAGRAM
24
C.
V,
23
22
GND
C,
C,
AoR
Vcco
'elK
VeC2
}NC
NC
NC
LSB BIT1
BIU
BIT 3
DOND
10
GRAY CODE 10 BINARY
CODE REGlsrERS
OUTPUT INTERFACES
11
12
TDA5703
February 1987
11-22
17
18
15
14
13
BIT8 MSB
BIT 7
BITS
BITS
BIT4
Preliminary Specification
Signetics Unear Products
TDA5703
Analog-to-Digital Converter
DC ELECTRICAL CHARACTERISTICS
VCCl = VCC2 = 4.75 to 5.25V; T A = 25°C, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
TEST CONDITIONS
Min
Typ
Max
Supply
VCCl
Analog supply voltage
Pin 4
4.75
5.0
5.25
VCC2
Digital supply voltage
Pin 6
4.75
5.0
5.25
V
V
rnA
ICCl
Analog supply current
Pin 4
60
Icc2
Digital supply current
Pin 6
110
rnA
8
bits
Res
Resolution
Digital input levels 1
VIH
Input voltage HIGH
VIL
Input voltage LOW
IIH
Input current HIGH
IlL
Input current LOW
V
2.2
-7
0.8
V
70
jJA
-.35
A
Analog input levels
BW
Absolute linearity
Vl
-1.0
+1.0
Differential linearity
Vl
-0.5
+0.5
1dB
3dB
Bandwidth
Differential phase
Differential gain
Fo
= 25MHz,
6.0
measured with TDA5702
Offset error
LSB
LSB
6.0
10
mHz
mHz
1
2.5
°C
17
mV
%
RIN
Input resistance
80
kn
CIN
Input capacitance
5.5
pF
Digital output levels (10 = 10mA)
VOH
Output voltage HIGH
VOL
Output voltage LOW
Co
External capacitance
2.4
V
0.45
0.40
100
Cl, C2, C3
V
nF
Temperature
TA
Operating ambient temperature
range
AC ELECTRICAL CHARACTERISTICS
0
+70
°C
VCCl = VCC2 = 4.75 to 5.25V; TA = 25°C, unless otherwise specified.
LIMITS
PARAMETER
SYMBOL
TEST CONDITIONS
UNIT
Min
Typ
Max
Timing
25
MHz
fc
Maximum conversion rate
tDELAY
Aperture delayl
19
tD
Digital output delay1
24
tpWH
Pulse width conversion HIGH l
20
ns
tpWL
Pulse width conversion LOW l
20
ns
NOTE:
1. See Timing Diagram, Figure 1
February 1987
11-23
ns
ns
•
Signetics Linear Products
Preliminary Specification
Analog-fo-Digifal Converter
TDA5703
EXTERNAl.
CIDCK
INTERNAl.
ClOCK
ANA1DG
INPUT
DIGITAL
OUTPUT
Figure 1. Timing Diagram
February 1987
11-24
NE5150/5151/5152
Signetics
Triple 4-Bit RGB 0/A Converter
With and Without Memory
Preliminary Specification
Linear Products
DESCRIPTION
The NE5150/5151/5152 are triple 4-bit
DACs intended for use in graphic display
systems. They are a high performance - yet cost effective - means of
interfacing digital memory and a CRT.
The NE5150/5152 are single integrated
circuit chips containing special input buffers, an ECl static RAM, high-speed
latches, and three 4-bit DACs. The input
buffers are user-selectable as either
ECl or TTL compatible for the NE5150.
The NE5152 is similar to the NE5150,
but is TTL compatible only, and operates
off of a single + 5V supply. The RAM is
organized as 16 X 12, so that 16 "color
words" can be down-loaded from the
pixel memory into the chip memory.
Each 12-bit word represents 4 bits of
red, 4 bits of green and 4 bits of blue
information. This system gives 4096
possible colors. The RAM is fast enough
to completely reload during the horizontal retrace time. The latches resynchronize the digital data to the DACs to
prevent glitches. The DACs include all
the composite video functions to make
the output waveforms meet RS-170 and
RS-343 standards, and produce 1Vp.p
into 75n. The composite functions (reference white, bright, blank, and sync)
are latched to prevent screen-edge distortions generally found on "video
DACs." External components are kept
to an absolute minimum (bypass capacitors only as needed) by including all
reference generation circuitry and termination resistors on-Chip, by building in
high-frequency PSRR (eliminating separate VEES and costly power supplies and
filtering), and by using a single-ended
clock. The guaranteed maximum operating frequency for the NE5150/5152 is
110MHz over the commercial termperature range. The devices are housed in a
standard 24-pin package and consume
less than 1W of power.
PIN CONFIGURATIONS
NE5150 F Package
The NE5151 is a simplified version of
the NE5150, including all functions except the memory. Maximum operating
frequency is 150MHz.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Single-chip
On-board ECl static RAM
4096 colors
ECl and TTL compatible
110MHz update rate (NE5150,
5152)
150MHz update rate (NE5151)
low power and cost
Drives 75n cable directly
Internal reference
40dB PSRR
No external components
necessary
toP VIEW
NE5151 F Package
APPLICATIONS
•
•
•
•
Bit-mapped graphics
Super high-speed DAC
Home computers
Raster-scan displays
lOP VIEW
NE5152 F Package
OO(MSB)
1
AO(MSB)
5
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
24-Pin Ceramic DIP
O°C to +70°C
NE5150F
24-Pin Ceramic DIP
O°C to +70°C
NE5151F
24-Pin Ceramic DIP
O°C to +70°C
NE5152F
WHITE 7
TOP VIEW
February 1987
11-25
II
Signetlcs linear Products
Preliminary Specification
Triple 4-Bit RGB Dj A Converter
With and Without Memory
NE5150j5151j5152
BLOCK DIAGRAMS
NE5150
NE5151
Vcc (6)
Vee (6)
(21)BO
AaNO(12)
(20)81
DONO (16)
~9)B2
VEE (14)
(18)83
STROBE(17)
WHITE (7)
AoND(12)
SYNC (10)
BLANK (9)
BRIGHT(8)
°OND(16)
VEE (14)
STROBE~7)
WHITE (7)
SYNC (10)
BLANK (9)
BRIGHT (8)
(11)
GREEN
(13)
RED
(15)
BLUE
NE5152
(11)
GREEN
February 1987
11-26
(13)
RED
(15)
BLUE
Signetics Linear Products
Preliminary Specification
Triple 4-Bit RGB OJA Converter
With and Without Memory
NE5150j5151j5152
ABSOLUTE MAXIMUM RATINGS
SYMBOL
TA
TSTG
Vcc
VEE
PARAMETER
Temperature range
Operating
Storage
RATING
UNIT
o to +70
-65 to + 150
°C
°C
7.0
-7.0
V
V
5.5
-0.5
0.0
o to VEE
V
V
V
V
Power supply
Logic levels
TIL-high
TIL-low
ECL-high
ECL-Iow
DC ELECTRICAL CHARACTERISTICS Vcc=+5V (TIL), OV (ECL), VEE=-5V, 0°C2 internal termination resistors. Can directly drive 75>2 cable and should
be terminated at the display end of the line
with 75>2. Output voltage range is approximately OV to -1V, independent of whether
the digital inputs are ECl or TTL compatible.
All outputs are simultaneously affected by the
WHITE, BLANK or BRIGHT commands. Only
the GREEN channel carries SYNC information.
NOTE:
There are 100 IRE units from WHITE to BLANK
One IRE unit is approximately 7.1 mY. Full·scale is
90 IRE units and 10 IRE units is is of full·scale (e.g.,
BRIGHT function).
Pins 19, 20, 21: WRITEs, WRITER, WRITEG'
Write enable commands for each of the three
16 X 4 memories. When all write commands
are high, then the READ operation is selected. This is the normal display mode. To write
data into. memory, the write enable pin is
taken low. Data DO - D3 will be written into
address AO - A3 of each memory when its
corresponding write enable pin goes low.
Pin 17: STROBE. The strobe signal is the
main system clock and is used for resynchronizing digital signals to the DACs. Preventing data skew eliminates glitches which
would otherwise become visible color distortions on a CRT display. The strobe command
has no special drive requirements and is TTL
or ECl compatible.
Pins 12, 16: AGND, DGND. Both Analog and
Digital ground carry a me.::irr.um of approximately 100mA of DC current. For proper
operation, the difference voltage between
AGND and DGND should be no greater than
50mV, preferably less.
Pin 14: VEE' The negative power supply is the
main chip power source. Vec is cnly used for
TTL input buffers. As is usual, good bypassing techniques should be used. The chip itself
has a good deal cf power supply rejection well up into the VHF frequency range - so
no elaborate power supply filtering is necessary.
Pin 18: NC. This unused pin should be tied
high or low.
11-29
•
Signetics Linear Products
PrelimlnolY Specification
Triple 4-Bit RGB D/ A Converter
With and Without Memory
NE5150/5151/5152
NE5150/5152 TIMING DIAGRAMS
ADDRESS
COMPOSITE
DATA
STROBE
WRITE ENABLE
ADDRESS
DAC OU11'llT
Read Cycle
NE5151 PIN DESCRIPTION AND
TIMING DIAGRAM
Write Cycle
NE5151 TIMING DIAGRAM
The eleven digital inputs 00 - OS, AO - AS,
WRITE G/R/B, and the unused Pin 18 of the
NE5150 are replaced in the NE5151 with the
three 4-bit OAC digital inputs GO - GS,
RO - R3, and BO - B3. Ali other pin functions
(e.g., composite functions, power supplies,
strobe, etc.) are identical to the NE5150.
COMPOSITE
STROBE
NE5152 PIN DESCRIPTION
DATA BITS
The NE5152 is a TIL-compatible-only version
of the NE5150, operating off of a single + 5V
supply. Vcc Pins 6, 12 and 16 should be
connected to + 5V and Pin 14 to OV. OAC
output is referenced to Vee.
DACOUTPI/f
NE5150/NE5151INE5152 LOGIC TABLE
SYNC
BLANK
WHITE
BRIGHT
DATA
ADDRESS
OUTPUT3
1
1
0
0
0
0
0
0
0
0
X
X
X
X
X
X
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
-10SlmV
-960mV
-746mV
-674mV
-71mV
OmV
-674mV
-60SmV
-71mV
OmV
1
1
0
0
0
0
0
0
1
1
0
0
0
0
[0000]
[0000]
[1111]
[1111]
Note
Note
Note
Note
2
2
2
2
CONDITION
SYNC 1
Enhanced SYNCI
BLANK
Enhanced BLANK
WHITE
Enhanced WHITE
BLACK (FS)
Enhanced BLACK (EFS)
WHITE (ZS)
Enhanced WHITE (EZS)
NOTES:
1. Green channel output only. RED and BLUE will output BLANK or Enhanced BLANK under these conditions.
2. For the NE5150/5152 the DATA column represents lhe memory data accessed by the specific address. For the NE5151, the DATA is the direct digital inputs.
3. Note output voltages in Logic Table are referenced to Vee for the NE5152 only.
February 1987
11-30
Preliminary Specification
Signetics Linear Products
Triple 4-Bit RGB D j A Converter
With and Without Memory
NE5150j5151j5152
COMPOSITE VIDEO WAVEFORM
February 1987
11·31
Signetics
AN1081
NE5150j51j52 Family of Video
Digital-to-Analog Converters
Application Note
Linear Products
Author: Michael J. Sedayao
INTRODUCTION
Raster-scan systems and bit-mapped graphics are here to stay. For a computer to be of
use, it needs an interactive means of communicating with the user. So for every computer,
whether it is a 10MFLOP (millions of floatingpoint operations per second) supercomputer
or a home computer for playing video games,
some type of terminal or graphics display
device is needed. Not long ago, inputs to the
computer were made using stacks of Hollerith
cards pushed into a hopper and then read
into the computer. Results would then come
from a printer. The hardcopy results were
exactly what they looked like: final judgment
from the computer. In order to respond, it was
back to the punch-card machine. Needless to
say, debugging programs became quite laborious. This problem led to the interactive
display, allowing the user to enter information
and see the results immediately. A new age in
computing had arrived.
The areas of word processing, on-screen
circuit simulation, and computer graphics developed with great rapidity. As technology
improved, so did the ability to make larger
displays having more colors and better resolution. As software developed, so did techniques such as windowing, the use of icons,
and the ability to use graphic input devices
such as mouses, light pens, and joysticks.
Three-dimensional images and photographic
quality reproduction soon followed.
Of the different technologies, how did raster
scanning predominate over other forms?
What differentiates bit-mapped graphics systems from character or vector-map systems?
In the following sections it will become clear
how technology and economics drove the
market and, consequently, product development.
Displays: Raster, Vector
Refresh, Storage Tube
A raster is technically a display of horizontal
lines. How the display is created is what
makes it unique. An electron beam generated
by a CRT (Cathode Ray Tube) and containing
video information, starts at the top left of the
screen and traces a path to the right part of
the screen (see Figure 1). It makes a slight
angle as it travels across. The gun is then
turned off as the beam rapidly returns to tlie
left. It then repeats this zig-zag path until it
reaches the bottom of the screen. The gun is
again tumed off as the beam travels back to
February 1987
the top of the screen. This entire process is
repeated from 30 to 60 times per second so
flicker is decreased (motion pictures or film
typically display 24 images per second). What
the electron beam has done is scanned its
information onto the screen. This process is
called raster scanning.
Figure 1. Raster-Scanned Display
All television sets display information in this
manner. For television sets in the United
States, the screen is redrawn 30 times per
second. Additionally, the screen is interlaced,
meaning that every other line is scanned and
then the lines in between are scanned. This
gives the illusion that the image is continuous.
Since the television sets have 525 lines,
262.5 lines are scanned first (the odd field)
and then the other 262.5 (the even field) are
scanned. To visualize this, consider a 21-line
system (see Figure 2). Scanning occurs at the
above-mentioned 30Hz rate which is also
known as the frame rate. Two fields (odd and
even) equal one frame. Scanning 525 lines 30
times a second equals 15,750 horizontal lines
scanned in a second. This is called the
horizontal scan frequency. These are standard in the U.S., coming under the standard
known as NTSC (National Television Standards Committee). In Europe, television has
625 lines and has a frame rate of 25Hz, or
half the power line frequency, 50Hz.
Vector refresh displays, or stroke-writers,
work on the principle that one line is the base
unit of information. Each line then corresponds to a vector. Instead of scanning
continuously, information is drawn line-byline, hence the name stroke-writer. These
systems off-load the refreshing tasks to spe-
11-32
cial hardware, making the system slightly
more cost-effective. Still, during the 1960's
making them proved too expensive for everyday applications.
In 1971, Tek1ronix introduced the Direct View
Storage Tube (DVST) for displaying and interfacing graphic data. It was based on oscilloscope techniques, storing information in a
special, long-persistence phosphor which
coats the inside of the screen. The display
resolution is limited only by the phosphor
grain size and the quality of the deflection
circuitry. Although inexpensive, these devices
were fine for oscilloscopes in the lab, but too
cumbersome for fully interactive work. When
the screen would redraw itself after the entry
of new information, the sudden disappearance and reappearance was almost like looking at the light of a camera flashbulb. Another
problem with the storage refresh screen was
that when new information entered, it would
write directly over the existing information.
Only upon refreshing the screen would the
new information be clear and readable. In
many cases, the annoyance did not justify the
low cost.
Bit-Mapped Graphics
In a bit-mapped graphics system, the screen
is divided into individual elements called pixels, short for picture elements. When they say
"bit-mapped", each pixel corresponds to a
bit, or, in most cases, an address or memory
location. This is what differentiates television
from bit-mapped computer displays. Although
both systems use raster scanning techniques,
the information transmitted on television is
continuous - a stream of analog information
between horizontal sync pulses (the pulses
used to denote the beginning and end of a
horizontal line) - whereas in bit-mapped systems, each line is divided into discrete elements (the aforementioned pixels). The approximation of analog images would then be
determined by the pixel density or screen
resolution. As an example, Figure 3 shows a
line approximated by a finite number of pixels.
The lines seem to staircase rather than flow
because of the enlargement of the pixels. The
effect is known in some computer graphics
circles as "jaggies", short for jagged edges.
So, with more pixels, better resolution is
possible. This is not without a price, though.
Since each pixel corresponds to a memory
location, memory cost rises dramatically as
pixel resolution increases. Drawing speed
Signetics Linear Products
Application Note
NE5150j51j52 Family of Video Digifal-fo-Analog Converters
means that there are 4 bit·planes and each
pixel would have to pierce all four planes to
give the proper information (see Figure 4) .
This is a fairly quick way to draw the screen
since the data goes directly from the bit·map
to the DAC (Digital/Analog Converter; DAC is
singular here since the display is mono·
chrome) .
.....................
......................
................. .. --
------_................. :;.......
..."
11
......................
••~ .......-r..-:-.::•••.••
13
10
12
15
14
17
16
18
19
D
B
- - HORIZONTAL TRACES
•••••••••• HORIZONTAL RETRACES
- - VERTICAL FLYBACK TIME
HTRACES
DEFLECTING
SIGNAL
AMPLITUDE
HRETRACES
~----VTRACE_I VI~VTRACE_ V
RETRACE
TIMERETRACE
NOTES:
A sample scanning pattern for 21 interlaced lines per frame and 10V2 lines per field. The corresponding H and V
sawtooth deflection waveforms are shown below pattern. Starting at point A, the scanning motion continues through B,
e, and D, and back to A again.
Figure 2. Interlaced Raster for 21-Llne System
Figure 3. Ideal Line and Its Discrete Pixel Representation
must also increase since more pixels have to
be drawn to maintain the ;;. 30Hz frame rate
needed to avoid flicker. Clearly then, the
increase in bit·mapped graphics systems can
be tied to the continuing price reductions in
memory, specifically, the Dynamic Random
Access Memory (DRAM). Fortunately, as the
price has dropped, the memory size has not
stood still. The last 14 years have seen size
increases from 4k to 16k, 16k to 64k, 64k to
256k, and now, 256k to 1M bits of memory.
One might expect to see DRAMs on the order
of 4Mb within 2 to 3 years. Additionally, the
February 1987
continuing development of video RAMs can·
not be ignored.
A bit·mapped system might be described in
one of three ways. First, assume the display
is monochrome and that each pixel can be
represented by a certain number, for in·
stance, 4 bits of information. This means that
there are 24 = 16 possible values of shading.
Each bit of information can be represented by
a "plane" of information. The plane would
correspond to the area that was mapped by
the pixels, namely the drawing area or dis·
play. Imagine an 8 X 8 pixel display. This
11-33
AN1081
A direct conversion system for color is the
second step. This is just an upgrade of the
first case. Instead of 4 bit·planes, there are
12: three sets of the 4 planes for the three
primary colors red, green, and blue. The
advantage here is that there are now
212 = 4096 different colors, but the corre·
sponding disadvantage is that the memory
requirement has tripled. For more bit resolu·
tion per pixel, the associated memory de·
mands increase by 3 times the pixel size
times n, where n is the additional bit of
resolution per pixel.
The third type of bit·map system uses a color
look·up table (CLUT) as the driver for the
display. The operation is straightforward. As
the controller scans the bit·map each time it
comes upon a pixel, it retrieves the bits which
are then decoded into an address. This
address is a pointer to the look·up table
where sixteen 12-bit words (colors) are stored
(see Figure 5). Once selected, that word is
then sent to the color DACs and, from there,
to the screen. The idea is similar to that of
having cache memory in a computer, a fast
memory used when the information in the
memory is frequently accessed. Note that the
bit·planes grow as n for 2n additional colors
while memory grows for 3n in the direct
conversion case, a definite savings in memo·
ry.
The limitation in this case is that only 16
colors can be displayed at a time. In some
systems, however, the CLUT is fast enough
to be reloaded during the horizontal retrace
time (CLUT size is sometimes referred to as
the maximum number of colors that can be
displayed on one horizontal line). This is
especially important if the image is to simu·
late a smooth motion such as the rotation of a
merry·go·round or the movement of an object
with mirrored surfaces. In most cases, 16
colors is sufficient for any single display. 64
colors (6 bit·planes) is ex1remely good. 256
colors (8 bit·planes) is definitely a lUXUry.
It's clear that the memory speed and memory
density, which are direct functions of the color
and screen resolution, playa large part in the
feasibility of a bit·mapped system. For that
reason, the enormous gains and technologi·
cal advancements in the field of memory
design have made bit·mapped raster·scan
graphic systems the best choice for both cost
and performance.
•
Signetics Linear Products
Application Note
NE5150j51j52 Family of Video Digifal-fo-Analog Converters
AN1081
Display resolution determines how many pixels can be projected onto the monitor at any
one time. (Actually, only one pixel is displayed
on the screen at a time, in rapid succession).
Table 1 shows commonly-used screen resolutions corresponding to various applications.
PLANEO_~
However, since each pixel must correspond
to a memory element, the more pixels per
screen the faster the DAC and video RAM
must be in order to write the information to
the screen fast enough to avoid flicker. This
imposes speed requirements that have to be
satisfied.
Figure 4. Monochrome Bit-Map With Direct Conversion to Display
PLANE3
III-WORD COlOR lOOK UP TABLE
PLANE2
REDCLUT
GREENCLUT
o
1
2
3
4
5
6
7
6
9
10
11
12
13
14
15
PLANE 1
PLANE 0
BIT PLANES
§~~g~~
BWECLUT
(PIXELISORANGE)
Figure 5. Color Bit-Map With 16-Word Color Look-Up Table
ISSUES FOR GRAPHIC DISPLAY
SYSTEMS
Making the DAC Fit the
Application
When designing graphic display systems,
there are many decisions to be made in
specifying the hardware and software needed
for a system. What kind of speed is necessary
in a given application? What kind of resolution
will the users of the system require? Is color
needed or will monochrome be adequate? If
color, how many colors? Will images be
viewed in two or three dimensions? How
much memory is needed? How should the
microprocessor/CRT controller/video DAC/
frame buffer be matched with the rest of the
February 1987
system? What's the best type of software for
a particular application? and on and on...
These questions could form the subject of an
entire book and so will not be discussed in
detail. This section will, however, discuss the
few issues needed in the selection of the
proper video DAC for a system.
Display Resolution vs Bit Resolution
When the quality of a display terminal is being
evaluated, one primary consideration is the
kind of resolution it has. There are two
different types of resolution: display resolution, which is determined by the monitor and
cannot be changed by the design; and bit
resolution, which is dependent on the design
of the video DAC used.
11-34
The other type of resolution, bit resolution,
depends on the type of DAC used. The
number of bits converted also determines the
size of the color palette which is the number
of possible colors that can be displayed. This
should not be confused with the number of
colors displayed at once (see Section on
Color Look-Up Tables). Assuming that the
monitor is an RGB-type, the bit resolution, n,
must be multiplied by 3 to get the total bit
resolution, 3n. Taking this number as 23n
gives the size of our color palette. Table 2
shows common bit sizes for video DACs with
their corresponding palettes.
It should be clear that, if imaging is the goal, a
higher bit resolution gives access to the
assorted tones and mix1ures of colors that
make color graphics as realistic as possible.
The major problems associated with higherresolution DACs are that they are larger and
more complex than lower-resolution DACs
and tend to take longer for their signals to
settle. This has a direct effect on selection of
the proper DAC for a particular system because of the DAC's bandwidth and because
of the need to weigh advantages and disadvantages of higher and lower bit resolutions.
For a low-end personal computer graphics
screen on which the pixels can actually be
seen at arm's length, it makes little sense to
have a bit resolution that shows flesh tones
because the benefit of the large palette is
defeated by a screen that shows jagged
edges. On the other hand, having a high
screen resolution with a limited amount of
colors does not defeat the purpose in the
same way-if many colors aren't needed.
Integrated circuit layout, for instance, may not
require thousands of colors - only enough to
distinguish 12 - 15 masks; but sharply defined edges and zooming ability are needed
to examine the circuit. The need for this user
could be a bit resolution of 2 (64 colors) and a
display resolution of 1024 X 1280.
For all this talk of colors and bit resolution,
monochrome should not be totally ignored.
After ali, people got along fine with black and
white TV for years before color came along.
For applications such as word processing or
Signetics Linear Products
Application Note
NE5150j51j52 Family of Video Digital-fo-Analog Converters
Table 1. Display Resolutions With Applications
DISPLAY RESOLUTION
For the screen resolutions noted earlier, a
new table can be generated for the minimum
DAC speed required (see Figure 8).
APPLICATION
250 X 500
Low-end personal computers (home computers)
640 X 480
High-end personal computers
600 X 800
Next-generation personal computers
768 X 576
AN1081
Next-generation personal computers
1024 X 800
Workstations
1024 X 1024
High-end workstations
1024 X 1280
High-end graphics terminals (CAE/CAD)
1024 X 1500
High-end graphics terminals (3-D Imaging)
1500 X 1500
High-end graphics terminals
2048 X 2048
High-end graphics terminals (photo quality)
Table 2. Bit Resolution With Palette Size
BITS/DAC
RGB
PALETTE SIZE
1
3
8
Digital RGB, "rainbow colors"
APPLICATION
2
6
64
Some home and personal computers
For the 60Hz frame rate, the screen is probably not interlaced. Interlacing the screen at
30Hz would give the same effect because
interlacing gives the illusion that the screen is
being refreshed at a faster rate. The DAC
would only have to operate at a quarter of the
speed of the 60Hz non-interlaced rate because only half of the lines are being drawn at
a speed that's half the 60Hz frame rate. This
is how scanning operates under the NTSC
television standard. The FCC says that televisions can't refresh the screen faster than
30Hz, so interlacing was developed to get
around it. There are no such restrictions in
graphics monitors. In fact, there are monitors
that have horizontal scan rates as much as 4
times faster (65kHz) than that for television
(15.75kHz).
Color Look-Up Tables: Yes or
No?
1024 X 1024
1,049,000
85MHz
As mentioned in the Bit·Mapped Graphics
section, graphic systems may have direct
conversion from a bit-map or they can use
color look-up tables (CLUTs). It should be
pointed out that one is not necessarily faster
than the other. Speed depends primarily on
the system. A fast CLUT is of no use if the
external frame buffer can't load a new set of
colors into the CLUT during the retrace time
(horizontal or vertical). A video DAC without
the CLUT may be faster since it can bypass
the memory accesses needed for the CLUT,
but, as seen in the Bit-Mapped Graphics
section, the extra cost of the bit-planes (1
million additional bits for a 1024 X 1024 display) may be excessive, and accessing the
additional planes may produce some design
problems.
1024 X 1280
1,311,000
105MHz
If a CLUT is needed, the size of the CLUT
1024 X 1500
1,536,000
125MHz
1500 X 1500
2,250,000
180MHz
2048 X 2048
4,195,000
330M Hz
4
12
4096
6
18
262,144
8
24
16,777,216
Color workstations, CAD/CAE
High-end CAD/CAE, medical imaging
Photographic quality reproduction
Table 3. Display Resolution With Minimum DAC Speed
DISPLAY RESOLUTION
# PIXELS
MINIMUM DAC SPEED
250 X 500
125,000
10MHz
640 X 480
308,000
25MHz
600 X 800
480,000
38M Hz
768 X 576
443,000
35MHz
1024 X 800
820,000
65MHz
circuit design, monochrome is fine, To
achieve different shades of black and white,
no chrominance operation is necessary. All of
the bit resolution can be done with one DAC
to operate on the luminance, or brightness
signal. In this case, the brightness resolution
can be said to be 2n Remember, the decision
to go with color or monochrome does not rest
upon the designers of the graphics board. A
monitor is either color or monochrome to
begin with. Adding a color video DAC won't
change that.
DAC Speed
The DAC's update rate or bandwidth is a
crucial consideration in choosing a DAC if the
type of monitor has already been specified.
February 1987
For raster-scan systems, a few calculations
can be made to determine the minimum
speed required for the DAC.
First of all, assume that the screen needs to
be refreshed at 60Hz to avoid flicker. To
account for the electron beam going back to
the top to start the next frame, assume that
the retrace time is 30% of the drawing time.
Multiply the frame rate by 1.3 to account for
the retrace. Thus, the minimum bandwidth for
the DAC would be determined by the following formula:
Speed (Hz)
= 1.3 (retrace factor)
# pixels X 60Hz (frame
X
11-35
rate)
should also be a major consideration. Each
bit-plane added requires 2n more memory
cells. Constraints on die-size and power requirements become apparent. Also, one must
ask whether one needs 16, 32, 64, 128, or
256 colors on every line. This depends on the
color resolution desired for the entire screen.
An easy way to determine the system needs
is to picture the most common scene that
would be displayed. The general rule is that
the more complex and three-dimensional the
images that are required, the more variations
and shading are needed to truly represent
them. Conversely, if the image is simple and
two-dimensional, fewer colors would be needed. An example of the former would be
geological formations. For the latter, consider
the colors of flags of the world's nations.
Almost all of them can be displayed with a
CLUT of 16 colors. Remember, this refers to
the number of colors needed at anyone time.
•
Signetics Linear Products
Application Note
NE5150/51/52 Family of Video Digifal-fo-Analog Converters
No flag has more than 16 colors. The range
of colors available for display after CLUT
refresh depends on the color resolution or the
number of data bits for each pixel.
Gamma Correction
A problem encountered in both television
systems and in display monitors in general is
the gamma effect. This is due to the nonlinear
relationship between light output and the
signal voltage applied to a cathode-ray tube.
Although it would be desirable to have the
luminous output of the phosphors on the
display to vary directly with the changes in the
signal applied to it, they usually do not. Each
monitor has its own characteristic, but the
international convention is to assume that the
fractional value of the luminous output can be
approximated by raising the percentage of
display signal input to the 2.2 power. For
example, a 60% of full-scale input signal will
result in 33% of the full-scale luminous output
(0.6 2 .2 = 0.33).
In Figure 6, the monitor does not respond
linearly for a linear input Signal. Adding a
gamma correction circuit can take care of this
problem.
1,0
-:1J
0.9
....
:::>
Q.
....
:::>
,/
0.8
0.7
GAMMA
cORREcn~N
/'
0.6
V
7'" f-- &,
0.3
0.2 II
0.1
o
o
/
/
/
:~S~:~E-
I I
I
/
/
/
,/
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
SIGNALINPUT
Figure 6. Monitor and System
Response With Gamma Correction
In the television industry, correction for this
non-linearity takes place at the camera as the
image is recorded. The camera takes the 2.2
root of its full-scale fractional value. This
cancels the gamma effect and produces a
linear system response.
In graphics systems for which the image is
generated from digital information, DACs convert the digital information into a voltage that
drives the guns of the CRT. Basically, the
systems designer has three choices:
1. Correct for gamma in the software. This
can be done by using the 2.2 power/root
compensation to pixel values before they
are stored into the frame buffer. This
could be an expensive addition to the
software and might slow the overall sysFebruary 1967
2. Apply analog gamma correction in the
hardware. The correction factor could be
done with additional circuitry to the output of the DAC before it drives the
monitor. As mentioned before, this presents an additional hardware overhead.
This is not done, however, without some
risks. Since every monitor has individual
characteristics, the resulting correction
would not look the same on every monitor.
3. Ignore the whole subject and accept the
non-linearity of the luminous output as a
characteristic of the system. Since most
graphics applications are for the generation of images for specific problems and
not for the lifelike reproduction of scenes
(although it would be desirable), a gamma correction mechanism is unnecessary.
This last approach seems to be the most
prevalent solution since few, if any, DACs
contain gamma correction circuitry. When
graphics software designers select their colors, they do so for the best visual performance. This fine-tuning for colors and shading is really software gamma correction because they can select the digital information
needed for colors and intenSity and see the
results from the other side of the monitor.
/
0.5
i
3
/
*'.':W
/l ~~
~
0 0.4 I-/-.-J.#~
z
0
........ / j
tem because of the added computation
time.
CIRCUIT FEATURES AND
OPERATION
This section covers the basic features and
operation of the NE5150/51 152. The first two
sections briefly discuss RS-170 and RS343A, the standards for color and monochrome video systems. The next section
covers the composite video signal (CVS) that
is specified in the two previous standards.
RS-343A and RS-170
RS-170, the Electrical Performance Standards for Monochrome Television Studio Facilities, and RS-343A, the Electrical Performance Standards for High Resolution Monochrome Closed Circuit Television Cameras,
were issued in November 1957 and September 1969, respectively, by the EIA (Electronic
Industries Association). The specifications
outlined in RS-343A determine the voltage
levels required for the part.
Composite Video Signal
Shown in Figure 7 is a section of a composite
video signal. With the exception of the
BRIGHT function, the levels and tolerances
are specified by RS-343A.
Sync, Blank, and Setup
The sync signal is situated 266mV (40 IRE)
below the blanking level which lies 714mV
11-36
AN1081
(100 IRE) below the reference white level
(next section). The sync signal synchronizes
the monitor horizontal and vertical scanning.
This, and the rest of the composite video
signal, is not to be confused with the composite sync signal which is often used for a
combined horizontal and vertical sync signal.
The blank level lies just below the reference
black level, separated by an amount known
as the setup. The difference between reference white and the blanking level is defined
as 100 IRE. Applying the blanking level voltage to the monitor input will reduce the CRT
electron beam current so that there will be no
visible trace of the electron gun on the
phosphor.
For televiSion, the setup is defined as the
ratio between the reference white and the
reference black level measured from the
blanking level. It is usually expressed as a
percentage. Basically, it's the difference between the reference black level and the
composite blanking level. RS-343A has set
the limits of the setup as 7.5 ± 5 IRE. Any
value between 2.5 to 12.5% of the blanked
picture signal can be designated as the setup
(2.5-12.5 IRE or 17.65-69.25mV). Since
the full-scale range of the video Signal represents 100 IRE, a percentage of the signal is
synonymous with its IRE value. For the
NE5150, the setup is 71mV or 10 IRE.
Reference Black and White
Reference black and white correspond to the
signal levels for a maximum limit of black and
white peaks. White corresponds to having all
color guns on and black to having all guns off.
The gray scale, which refers to the rest of the
color values and contains a majority of the
signal information, is defined by the amplitude
between reference white and reference
black. Since the reference white to blanking
level is fixed at 100 IRE, the reference black
level is determined by the setup. Since the
setup can be between 2.5 and 12.5 IRE, the
gray scale range must reflect those tolerances and so has a range of 92.5 ± 5 IRE
(660.5mV ± 35.7mV).
To allow for a BRIGHT function, the NE51501
51/52 family of video DACs were designed
for a full-scale range (blank to reference
white) of 675mV (about 94 IRE) and a grayscale range of 643mV (about 90 IRE). Using
the BRIGHT function adds 71 mV (10 IRE) to
the reference white value.
For instance; in a 12-bit system like the
NE5150/51 152, using 4 bits/DAC would enable us to resolve the gray scale range into
16 parts. For the NE5150, that would be
about 40.1 mV (5.6 IRE) = 1 LSB. For 6 bits,
64 parts could be resolved, and for 6 bits, 256
parts.
Signetics Linear Products
Application Note
AN1081
NE5150j51j52 Family of Video Digital-to-Analog Converters
-
TT
1V
I
ENHANCED WHITE(BRIGHT)
-l-REFERENCEWH'TE
GRAYSCALE
(VIDEO)
714mV
92.5 :t:5IRE
~OOIRE)
+
SETUP {lREFERENCEBLACK
(7.5 ±5IRE) \ -COMPOSITE BLANKING
(SYNC)
2B6mV (40IRE)
LBACKPORCH
---L.
-SVNCLEVEL
Figure 7. RS·343A Video and Sync Levels
SYNC
GREEN
NE5150/NE5151INE5152 LOGIC TABLE
SYNC
1
1
a
a
a
a
a
a
a
a
BLANK WHITE BRIGHT DATA
X
X
1
1
a
a
a
a
a
a
X
X
X
X
1
1
a
a
a
a
a
ADDRESS
AaND
OUTPUT3
a
X
X
X
X
X
X
[0000)
X
X
X
X
X
X
Note 2
-1031mV
-960mV
-746mV
-674mV
-71mV
OmV
-674mV
1
[0000]
Note 2
-603mV
a
[1111]
Note 2
-71mV
1
[1111]
Note 2
OmV
1
a
1
a
1
CONDITION
TOP VIEW
SYNC1
Enhanced SYNC1
BLANK
Enhanced BLANK
WHITE
Enhanced WHITE
BLACK (FS)
Enhanced BLACK
(EFS)
WHITE (ZS)
Enhanced WHITE
(EZS)
R1
R2
R3
80 (MSB)
B1
B2
Ba
STROBE
NOTES:
1. Green channel output only. RED and BLUE will output BLANK or ENHANCED BLANK (BRIGHT ON) under
these conditions.
2. For the NE5150/5152, the DATA column represents the memory data accessed by the specific address. For
the NE5151, the DATA is the direct digital inputs.
BLUE
SYNC
GREEN
3. Note output voltages in Logic Table are referenced to Vee for the NE5152 only.
AaND
Device Description and
Operation
Corresponding to the RS-343A requirements
outlined in the previous section, the logic
table indicates the output voltages given the
digital inputs shown. Although the output
voltages for the DACs are shown, the user
should also know what is happening to the
circuit and how the priority given to each
function influences the output. [All ones
(1111) is called zero-scale (ZS) and all zeroes
(0000) is called full-scale (FS).)
The BLANK command presets all the latches
to all zeroes (0000) and sends the output to
its blanking level of 100 ± 5 IRE below reference white (-71 mY) or about -746mV. When
BRIGHT is on (a '1 'I, the output is raised 10
IRE (71mV or Y9th of full-scale) to -674mV.
BLANK overrides WHITE and is overridden
by SYNC.
The WHITE command presets the latches to
all ones (1111) and outputs -71mV to all
DACs. When the BRIGHT command is on,
this value is raised to OV. WHITE will be
overridden by both SYNC and BLANK.
February 1987
The SYNC command presets all of the
latches to zeroes and turns on the BLANK
switch. In addition, it turns on a 40 IRE switch
(drops voltage 286mV) in the GREEN channel only. So the GREEN channel sits at 140
IRE down and the RED and BLUE channels
will be 100 IRE below ground.
TOP VIEW
D1
D2
D3
The BRIGHT command turns off one current
switch within the circuit and adds 10 IRE
(71 mY) to the output levels of all three guns.
This comes in handy if using a cursor (optional blinking) to brighten other parts of the
screen. This switch cannot be overridden by
any other switch.
Referring to the pinouts of both the NE51501
52 and the NE5151 (see Figure 9), there are
additional considerations.
The WRITEG, WRITER, and WRITEs pins are
the write enable pins for each of the 16 X 4
memories in the CLUT. When these pins are
pulled High, the memory is then in the READ
mode. This is the normal mode of operation.
To write to the memory, one of the pins must
be pulled Low. The data on DO - D3 will then
be written to the memory location AD - A3 of
the corresponding WRITE pin.
11·37
STROBE
SYNC
GREEN
GND
vee
RED
TOP VIEW
Figure 8. Pinouts of NE5150/52 and
NE5151
STROBE is the main system clock and synchronizes all digital operations on the DAC.
•
Signeties Linear Products
Application Note
NE5150/51/52 Family of Video Digifal-fo-Analog Converters
The strobe is ECl and TTL compatible and
demands no special drive requirements. The
positive edge of STROBE clocks the latches.
Using Different Logic and Supply
Voltages
Different users have different needs. Some
have access to dual supplies, other only to
single-ended supplies. Signal logic may be
TTL or ECL. In any case or configuration, the
NES1S0/Sl/S2 family can be used. The following configurations cover most cases.
The GREEN, RED, and BLUE pins are the
analog outputs of the DACs. The DACs are
voltage output and need no external components (7Sfl resistors are on-chip). The output
voltage range is approximately 0 to -1 V and
is independent of the input logic (either TTL
or ECl).
Explanation of the configurations are as follows:
The DATA and ADDRESS bits are designated
so that DO and AO represent the most significant data and address bits (MSB), respectively. Similarly, D3 and A3 correspond to the
least significant data and address bits (lSB).
Since the NE51S1 has no ClUT, there is no
need for the address pins (4) or the write
enable pins (3). Adding the NC (no connection) pin (1) gives the eight additional input
pins for two 4-bit DACs. The original data bus
now carries the logic for the RED gun.
A. Case A shows a basic ECl configuration
for the NES150 and NESI51. The signal
voltage is basic ECl with a -1.3V threshold and is powered from ground and -SV
(or -S.2V). Since the TTL buffers are no
longer needed, Vee is tied to analog and
digital ground (AGND and DGND), excluding
the buffers from the circuit.
B. In some cases, people use ECl logic but
run it off a single supply, + SV and ground.
In this case, operation is the same except
that the supplies are shifted up SV. In this
new ECl mode, the threshold -1.3V is
moved up by SV to + 3.7V. ECl operation
is not available for the NES1S2.
Analog and digital ground (AGND and DGND)
should always be connected together in any
configuration and should not have more than
SOmV of potential between them to insure
proper operation of the device. The next
section will cover connection of Vee and VEE,
in addition to AGND and DGND, on different
system configurations.
C. For TTL operation in the NES1S0 and
NES1Sl, dual supplies are normally needed. If available, standard TTL-level signals
with a + I.4V threshold (between a logic 'I'
low of 2.0V and a logic '0' High of 0.8V)
can be connected directly.
D. In some situations, a dual supply is not
available. Single-supply TTL operation is
made possible by making similar connections and by pulling up the inputs of each
pin with a 10kfl resistor connected to
Vee = + 5V. This is necessary because the
threshold is now 3.7V.
E. Case (D) necessitated the construction of
the NE5152, which has only one mode
using a single 5V supply and accepts TTL
inputs. AGND and DGND become VeeA and
VeeD and are tied to Vee.
In some cases, a single supply is used and
the internal ECl mode has been shifted up
to the positive supply; the output voltage
will be swinging from OV to -IV, but,
referenced from Vee = +SV, it will swing
from SV to 4V. If the monitor accepts only
positive sync pulses or video information,
DC-offsetting the outputs or AC-coupling
them with I/lF capacitors would make the
signal acceptable to the monitor.
Since the outputs have internal 7Sfl resistors,
the monitor should have a 7Sfl resistor to
ground in order to doubly-terminate the cable
and to prevent reflections.
Unused Inputs
For ECl mode (NES1S0), any unused inputs,
regardless of desired permanent stage,
should be tied to a fixed-level output of an
unused gate.
+5V
ECl
ECl
AN1081
Vee
DIGITAL
INPUTS
AoNO
DONO
VTH =3.7V
-SOR 5.2V
(B)
(A)
TTL
TTL
voo
NE5150
NE5151
+5V
+5V
+5V
TTL
Vee
D)GITAl
INPUTS
Vee
VeCA
VCCD
VTH
NE5150
NE5151
(C)
-SOR -5.2V
=3.7V
VTH =1.4V
NE5152
(D)
(E)
Figure 9. Video DAC Modes of Operation
February 1987
Voo
NE5150
NE5151
11-38
Application Note
Signetics Unear Products
NE5150/51/52 Family of Video Digital-to-Analog Converters
AN1081
BLOCK DIAGRAMS
NE5151
NE5150
AO A1 A2 A3 DO 01 02 03
(5) (4) (3) (2) (1) (24)(23)(22)
Ved6)
(21)BO
"<;NO(12)
(20)B1
OONO(16)
~9)B2
VEE (14)
(18)B3
STROBE~7)
Ve d6)
WHITE(7)
"<;NO(12)
SYNC (10)
DONO (16)
BLANK (9)
VEE (14)
BRIGHT (8)
STROBE (17)
(11)
WHITE (7)
GREEN
SYNC (10)
BLANK (9)
BRIGHT (8)
(11)
GREEN
(13)
RED
~5)
BLUE
NE5152
AO A1 A2A3 DO D1 02 03
(5) (4) (3) (2) (~(24)(23)(22)
•
Vee (6,12,16)
GNO~4)
STROBE (17)
WHITE(7)
SYNC~O)
BLANK (9)
BRIGHT (8)
~1)
~3)
(15)
GREEN
RED
BLUE
Figure 10. NE5150/51/52 Block Diagrams
February 1987
11-39
Signetics Linear Products
Application Note
NE5150j51j52 Family of Video Digifal-fo-Analog Converters
AN1081
Circuit Description
As can be seen from the block diagrams in
Figure 13, the only difference between the
NE5150/52 and the NE5151 is the lack of a
color look-up table on the NE5151. Bypassing
the CLUT with its assorted address decoding,
sense amplifiers, and read/write logic enables it to not only use 200mW less power,
but also to increase its update rate to
150MHz.
A
~-----~----~~-UV
The NE5151 is basically the same die as the
NE5150/52, with the exception of a metal
mask option that permits it to bypass all of the
circuitry associated with the CLUT. It is also
bonded differently to enable all 12 bits to be
loaded into the DAC at anyone time instead
of being multiplexed 4 bits at a time to the
NE5150/52 CLUT.
DAC Reference
The need for separate references for the
DACs resulted from the problems associated
with glitching and crosstalk between the
DACs. When one DAC maintains a constant
value through pixel updates, while another
undergoes major transitions such as the 1111
to 0000 on/off switching of currents through
the DAC, feedthrough can be expected if all 3
DACs derive their reference voltage from the
same source. Having separate references
solves this problem. It also isolates the DACs
from each other and the other parts of the
circuit.
The reasons for choosing the DAC shown in
Figure 12 are its simplicity, the bandgap's
insensitivity to temperature variations, and its
excellent supply rejection (PSRR) through
high frequencies. It consists of a PTAT current source supplying a bandgap reference.
The output of the bandgap is approximately
-1.2V.
To provide the bias for the different current
sources on each of the DAC stages, the
circuit uses a control amplifier that provides
negative feedback to maintain its stability. BIT
and its complement drive the differential pair
that (along with OS2) makes up one part of
the DAC. The bandgap drives the current
sources through the control amplifier. If the
bias line voltage should rise or fall, the
negative feedback in the OSI and OS3 current path would correct for it.
The control amplifier consists of a transconductance stage driving an emitter-follower.
The output of the emitter-follower provides a
low-output impedance line that drives OS4.
The inclusion of OS4 prevents switching transients from degrading settling time. The control amplifier has a 60MHz unity-gain bandwidth, providing power supply rejection up
into the VHF range.
February 1987
3k
4k
30
VEE
0--+---------'
Figure 11_ Bandgap Reference for DAC (1 of 3)
Dlgltal-to-Analog Converters
The three DACs consist of differential pairs
that are switched on or off depending on the
value of the bits. Each of the transistors
switches a different amount of current depending on the significance of each bit (see
Figure 13). Although only one transistor is
shown for each bit, the circuit actually has
several transistors in parallel to get the required current. In this case, B3 is the least
significant bit since it switches the least
amount of current and would produce the
smallest voltage drop across the 75>1. load
resistor. The reverse is true for BO, the most
significant bit, since it draws the most current.
So for all bits low, 0000, all of the current
would go through the load resistor, bringing
the output voltage to its lowest point. If all
three DACs are low, this would correspond to
reference BLACK. All bits high, or 1111, shunt
current away from the load and leave the
output voltage at reference WHITE. Different
combinations of bits give 16 values between
WHITE and BLACK. One additional 2mA
switch is turned on by the input value of
BRIGHT, which level-shifts the output by Y9th
the full-scale value, or about 10%. The
BLANK and SYNC pins work in a similar
manner. Refer to the Logic Table beside
Figure 8 for the output voltages for each of
these functions.
Some of the problems associated with DACs
can be attributed to switching glitches, usually
measured in terms of glitch energy. Glitching
occurs when digital switching of the transistors causes spikes onto the collectors of the
11-40
current sources to each of the differential
pairs. These current spikes charge the collector-base capaCitance, CJC, of the collector
transistor, and result in a slower settling time.
The asymmetrical turn-on/ off behavior of bipolar transistors and mismatched load bitwiring capacitances also contribute to glitches. This can also be seen as an overshoot of
the waveform, a "glitch" on the rising or
falling edge of what should look like a square
wave. Signals that overshoot the desired
analog output level consequently take longer
to settle to their final value. The measure of
this overshoot is the glitch energy, usually
given in pV-sec. The units do not actually
work out as units of energy or Joules, which is
C-V (Coulomb-Volts), but result from measuring the area of the glitch [Area = Height
(V) X Width (psec)].
The NE5150/51/52 resolves this problem by
putting the current sources in series with
another set of transistors (see Figure 14). The
stage below the differential pair is then biased
by a low-impedance line which reduces the
effect of the current spiking. The biasing for
the lower transistor comes from the control
amplifier mentioned in the DAC Reference
Section.
Video DAC Timing
For the NE5150 and NE5152, the presence
of the memory dictates both a READ and a
WRITE cycle, whereas the NE5151 needs
only one diagram. The explanation of each of
the waveforms can be found in the timing
glossary. For the guaranteed specifications,
the user is referred to the data sheet.
Application Note
Signetics Linear Products
AN1081
NE5150/51/52 Family of Video Digital-to-Analog Converters
NE5150/52 (With CLUT)
In the NE5150/52 READ cycle, the GOMPOSITE signal refers to either the WHITE,
BRIGHT, BLANK, or SYNG signals. The read
composite hold time, tRCH, is defined from the
rising edge of the strobe to the end of the
composite pulse. This is the required time the
composite signal must remain on the bus for
latching. The time between the end of the
composite pulse to the next rising edge of the
strobe defines the read composite setup time,
tRCS' This is the same as the read address
setup time, tRAS' The read DAG delay time,
tRDD, is the propagation time of the signal
through the device clocked from the strobe to
the 50% change of the DAG output.
Rl
300
This timing diagram is similar to the READ
cycle of the NE5150/52 with the exception
that addresses are not clocked to the GLUT;
instead, data bits are sent directly to the
DACs. In this case, tDH is analogous to the
address hold time in the NE5150/52. All
other definitions are analogous to the earlier
READ case.
WORKSTATION APPLICATION
Introduction
This section describes the design of a color
graphics interface for the Modula, Inc. Lilith
Workstation. The workstation initially loads 16
colors (it only requires 16) into the NE5150's
color look-up table. After the colors are loaded, the workstation then generates addresses
to the look-up table. The entire color range
(4096) is not required in this application.
February 1987
t----+--
VOUT
..l---iE--=~--
BIAS
BIAS
BANDGAP
(-1.2V)
CONTROL
AMPLIFIER
In the WRITE cycle, tWAS, the write address
setup time is defined by the start of address
to the falling edge of the write enable strobe.
At the end of this time, data can be written to
the GLUT. Both ADDRESS and DATA must
remain latched until they reach the rising
edge of the WRITE ENABLE. This defines the
WRITE ENABLE pulse width, tWEW' The data
should also be latched at the same time as
the address. The start of the data (and
address) to the end of the write enable pulse
is defined as tWDS, or the write data setup
time. After the write pulse finishes, an address and data hold time is also specified.
NE5151 (No CLUT)
Since the NE5151 has no memory for the
signal to propagate through, it typically has a
faster conversion time. As can be seen from
the pinouts, the three 4-bit words enter the
DAG simultaneously as opposed to the sequential 4-bit loading scheme used in the
NE5150/52. With no memory, there's no
need for READ or WRITE cycles and so there
is only one standard timing diagram. (See
Figure 16).
RL
75
'-------t:
QS4
-----+-----.V~
Figure 12. Negative Feedback Referenced to Bandgap
Ar-~-------------------------------------------,
RL
75
Vour
B3
BIAS o--1~=-----IE:--;;;;------J:::--:;;,-------t:.
v••
o---~-------+
_______ ______-J
~
Figure 13. Simplified Schematic of DAC (1 of 3)
The LILITH Workstation
The Lilith Workstation is a 16-bit workstation
manufactured by Modula, Inc. It was originally
designed by Niklaus Wirth and his students at
the Swiss Federal Institute of Technology
(ETH). The Lilith is a Modula-2 computing
engine. In its original package, the Lilith
includes 256kB of memory, a 15MB Winchester disk drive, a floppy disk, a mouse, and an
832 X 640 monochrome graphics tube.
The Signetics Logic DeSign Group in Orem,
Utah, has modified the Lilith by adding 2MB of
memory and a high-resolution 1024 X 1024
color monitor. The changes made to the Lilith
graphics section comprise the bulk of this
application description. Benchmarks of the
11-41
modified workstation have shown that its
performance on applications ranging from
matrix multiplications to complete circuit analysis is approximately half as fast as a VAX
111780 minicomputer. In addition to the circuit simulator used, the Signetics-modified
Lilith also supports a layout editor, SLED, that
uses about 10,000 lines of Modula-2 source
code. More detailed information on the Lilith
can be obtained from the manufacturer and
from the articles listed in the reference section.
For the purposes of this application, it is
sufficient to know that the Lilith contains a 16bit data bus for interaction with the
SCC63484 Advanced CRT Controller and a
•
Application Note
Signetics Linear Products
NE5150j51j52 Family of Video Digital-to-Analog Converters
AN1081
14-bit bus that is used to initialize the color
look-up table in the NE5150 video DAC.
Read/write, I/O lines, CLOCK, data acknowledge, and chip select signals are also sent to
the SCC63484 for data and control purposes.
Software Aspects (Pascal and Modula-2)
Modula-2 is a superset of Pascal. Anyone
with a working knowledge of Pascal should
have no trouble programming a Lilith workstation or in understanding the initialization program outlined in this section. Some noteworthy features about Modula-2 and its influence
on the architecture of the Lilith (the Mmachine) is the fact that the Lilith instruction
set (M-code) has only 256 carefully chosen
instructions. This limits any instruction to alB
length and increases the speed of operation.
The Modula-2 language constructs map neatly to M-code. There are no excess instructions to add extra baggage. For additional
details, the reader is referred to the August
1984 issue of BYTE magazine that contains
several good articles on Modula-2.
Considering each '1' as ON and each '0' as
OFF, the binary values for each color can be
specified for each of the respective guns.
Starting from the top, all guns OFF = BLACK.
Similarly, all guns ON corresponds to word 7,
WHITE. In the software definition module
used to load the values, two constants were
declared: black = 0 and white = 15. These
correspond to the addresses shown in the
table and were predefined because of their
frequent use. Single guns completely ON give
1, 2, and 4 - the primary colors RED,
GREEN, and BLUE, respectively.
VEE
----+------
Figure 14. Low-Z Bias Line to Improve Settling Time of DAC
ADDRESS
DATA
WRITE ENABLE
Figure 15. NE5150/52 READ and WRITE Cycle Timing Diagrams
System Hardware
The basic system configuration for the color
graphics interface is shown below. The Lilith
workstation sends data to the SCC63484 and
the NE5150. The information sent to the
NE5150 is the data for the CLUT initialization.
Control signals are sent to the ACRTC. The
ACRTC in turn controls the video DAC. The
frame buffer sends and receives data (via an
address/data buffer stage) to and from the
ACRTC for video DAC addressing. The
ACRTC also provides horizontal and vertical
sync to the CRT while the video DAC supplies
the video information. One stage not shown is
the address and data buffering for the frame
buffer and the pixel stage. This stage, in
addition to assorted logic and timing chips,
merely facilitates functionality between the
major blocks shown in Figure 22.
The host microprocessor, system memory,
and DMA control are local to the workstation
and will not be described. The horizontal and
vertical deflection sections are local to the
CRT and will also be omitted. The rest of this
section supplies an overall parts list and then
describes each of the graphics blocks in
somewhat greater detail. Although the actual
February 1987
COMPOSITE
STROBE
DATA BITS
DACOUTPUT
Figure 16. NE5151 Timing Diagram
pin numbers have been omitted, the functionality of each' pin is shown for understanding.
For actual pinouts and more detailed information, refer to the appropriate data sheet.
Parts List
The following parts were used in the design of
the color graphics interface (the actual quantity of each part is not listed). The "F"
11-42
designation stands for Signetics FAST·type
logic.
• NE5150 Video DAC
• SCC63484 Advanced CRT Controller
• MB85103-10 64k X 8 Dynamic RAM
modules (Fujitsu)
• 7404 Hex Inverter
• 7432 2-lnput NAND Gate
Signetics Unear Products
Application Note
NE5150/51/52 Family of Video Digital-to-Analog Converters
.7474 Dual D-Type Flip-Flop
co 74123 Dual Retriggerable Monostable
Multivibrator
• 74138 l-of-8 Decoder/Demultiplexer
• 74F139 Dual l-of-4 Decoder/Multiplexer
• 74F157 Quad 2-lnput Data Selector/
Multiplexer (Non-Inverted)
• 74F166 8-Bit Serial/Parallel-In, SerialOut Shift Register
• 74F245 Octal Transceiver (3-State)
• 74F373 Octal Transparent Latch
.. 7905 5V Voltage Regulator
• Ml00l 40MHz Crystal (MF Electronics)
• 74F161 4-Bit Binary Counter
• 74F164 8-Bit Serial-In/Parallel-Out Shift
Register
PC Board Layout Considerations
Whenever dealing with high-frequency systems, analog or digital, care must be taken
with PC board layout in order to insure good,
AN1081
reliable operation. Video DACs are hybrid
devices in the sense that they are both
analog and digital. They are also run at
frequencies well into the RF range. This
makes them especially susceptible to RF
interference and different types of radiation.
Signal traces should be kept as short as
possible and 90· turns should be avoided.
Power supplies should have adequate decoupiing.
DATA
(CWTDATA)
HOST
MICROPRocessOR
"'.--"::':===---.,...1
Figure 17. Block Diagram of Color Graphics Interface
More details are provided in the reference
section under Reference Number 4, "Getting
the Best Performance From Your Video Digital-to-Analog Converter".
Table 4. Colors with Corresponding Bit Values
WORD #
a
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Functional Description
The interface is designed to drive a Mitsubishi
C-6919 or 6920 19-inch monitor. The monitor
has 1024 X 1024 display resolution. Of
these, 1024 X 768 pixels are actually drawn,
giving us about 790,000 pixels, and, according to our earlier formulas, requiring a DAC
with a conversion frequency of about 62MHz.
That, however, assumes a non-interlaced
display with a frame rate of 60Hz. This
application uses a 30Hz interlaced display
and so it needs only one-fourth that speed
since it is drawing half as many lines at half of
the frame rate. The pixel clOCk is derived from
a 40MHz crystal. Other timing signals are also
derived from the same crystal.
COLOR
BLACK
RED
GREEN
YELLOW
BLUE
VIOLET
TURQUOISE
WHITE
GREY
ORANGE
AVOCADO
LIME
NAVY
ROUGE
LAVENDER
PEA
BLUE
GREEN
RED
0000
0000
0000
0000
1111
1111
1111
1111
1010
0000
0000
0101
1111
1000
1111
1000
0000
0000
1111
1111
0000
0000
1111
1111
1010
1000
1010
1111
1000
0000
1111
1111
0000
1111
0000
1111
0000
1111
0000
1111
10tO
1111
1000
1111
1000
1111
1000
1000
NOTE:
The colors listed are for an application example only. The colors were randomly ordered and their gun and bit
values in no way represent the de facto standard values or colors.
February 1987
11-43
•
Application Note
Signetics Unear Products
AN1081
NE5150/51/52 Family of Video Digital-fo-Analog Converters
ADVANCED CRT CONTROLLER
VCC~+5V=r.
The Signetics SCC63484 is a state·of-the-art
device ideal for controlling raster-scan-type
CRTs. It is a CMOS VLSI system that can
control both text and graphics. One of the
advantages of this part is its ability to do onboard graphic processing in its Drawing and
Display Processor, relieving some of the computational overhead from the Lilith.
~'ULL
PUu,up
r~m~
Figure 18. Circuit for Pull·Up to Vce
The interface uses a 512kByte frame buffer
that is organized as 64k by 64·bit words.
Within each 16-bit block of memory (1 of 4
per word), there are 4 pixels of 4 bits each.
Each bit supplies an address to the Color
Look-Up Table in the Video DAC. The interface shifts out 64-bits or 16 pixels of information during each display cycle.
In each of the following schematics certain
pins have been pulled up to Vce, indicated by
an arrow. For each arrow pointing to PULLUP, the connection goes into the pull-up
circuit shown below.
Another attractive feature of the part is its
flexibility. It has three different operating
modes: character only, graphic only, and
multiplexed character/graphic mode. In addition, it offers three scanning modes: noninterlace, interlace sync (this application), and
interlace sync and video modes. With 2MB of
graphic memory and a maximum drawing
speed of 2 million pixels/second, it can supply the information to almost any type of highresolution display (4096 X 4096 pixels maximum).
For additional information on the command
set and a full listing of features, please refer
to the data sheet and user's manual. This
application note will concentrate on only the
interconnections relevant to this application.
In this configuration (Figure 19), the
SCC63484 Graphics Controller provides the
horizontal and vertical sync pulses to the CRT
and important timing pulses to the address
and data buffers. It supplies timing to the
frame buffer, the pixel-shifting stage, and to
CPULL is used for decoupling any power line
ripple. Each point has a similar circuit.
the frame buffer through direct and logical
modifications made to the following system
outputs:
1. MRD-Memory Read or the Bus Direction Control Line. This determines the
bus direction for the Frame Buffer Data
Bus.
2. DRAW - the Drawing/Refresh Cycle
pin. This differentiates between drawing
cycles and CRT display refresh cycles.
3. AS - Address Strobe. This provides the
address strobe for demultiplexing the
frame buffer/data bus (MADO/MAD15).
4. MCYC - Memory Clock. Provides the
frame buffer memory access timing.
Equal to one-half the frequency of 2CLK
signal.
5. DISPl - Display Enable Timing. This is a
programmable display enable timing signal used to selectively enable, disable,
and blank logical screens.
6. MADO - MAD15 - Address and Data
Bus. Multiplexed frame buffer address/
data bus.
7. MA16, MA 17 - Address Bits/Rasier Address Outputs. Gives the higher-order
address bits for graphic screens and the
raster address outputs for character
screens. (lower 2 bits of MA16-MA19).
Vee. +5V
"lOOk
V=+5V
cc
. Cexr
lOPULL.lJP
RD1 74123
A:i
iii
"::"
iiACK
iiSYNC
RES
VSYNC
BUSO-BUS15
DST
1/0..
FROM
}lOCRT
DISPI
DISPI
00-D15
SCC63484 MRD
R/W
DRAW
MRD
16
RS
AS
cs
MAOO-MAD15
iiiiAW
AS
MC"IC
MC"IC
lOPUL!.,UP
lOADDRESS
AND DATA
BUFFERINIl
16
ULrrH
jj
E3
E2
iii
I/OA1
1I0Al
1/0..
74138
I
2CLK
(FROM TlMINIl)
c~
cs"
cs"
2CLK
MA16
MA16
MA17
MA17
lfE5150
"::"
"',.",.
Figure 19. SCC63484 Advanced CRT Controller
February 1987
11-44
Application Note
Signetics Linear Products
NE5150j51j52 Family of Video Digifal-fo-Analog Converters
The 2CLK signal provides the main clock
input to the SCC63484 and is derived from
the pixel clock (see System Timing).
The ACRTC also provides horizontal and
vertical sync pulses directly to the CRT via
the HSYNC and VSYNC outputs.
In Figure 19, the 16-bit bus of the Lilith is
connected directly to the data inputs. The
Lilith also provides a write signal (DST) to the
R/W input. The first I/O line (IIOAO) is
connected to the RS (Register Select) input.
In addition, there is a high-order I/O bank
select, three lower-order address lines, and a
negative true I/O clock that, used with the
74138 Decoder, selects one of 4 devices: the
ACRTC or 3 areas in the NE5150's color
look-up table.
On the ACRTC, a 74123 one-shot produces a
reset pulse (RES) on power-up. The Data
Acknowledge pin is not used and is pulled up
to Vee.
AN1081
ADDRESS AND DATA
BUFFERING
The address and data buffer stage provides
an interface between the SCC63484 and the
rest of the circuit. This stage takes the
address/ data lines MADO - MAD15 and separates them into two blocks. The 74F373
latches the upper bank for the addresses; this
is the first bank. The second bank consists of
74F245 transceivers in the lower bank for the
data.
~o-----~>o----~----------------------------------,
ENABLE
ENABLE
QOI---~--""'::';;"..,
74F373
QO-Q7
74F373 011----+-...;;::.:.:;
TO
nMING
MAA8-MAA15
MAAO-MAA7
MACe
MCYC
.--------loa
TO
TIMING
74F139
311----------,
28
11
FROM
SCC63484
•
MAI»-MAD7
16
16
MAI»-MAD15
MAD8-MAD15
MRDo----------1 1---4-----1
TO VIDEO RAM
AND PIXEL SHIFTING
Figure 20. Address and Data Buffering
February 1987
11-45
Signetics Unear Products
Application Note
NE5150/51/52 Family of Video Digital-to-Analog Converters
The 74F373s are used to latch the addresses
at the beginning of every memory cycle. The
latches are enabled by the AS signal coming
from the ACRTC. Since the ACRTC is configured to increment its display addresses by
four between display cycles, 4 words or 64
bits are shifted out every cycle. For modifying
memory cycles, the two lower address lines
are used to enable one of four sets of 74F245
transceivers (2 per set). Enabling is performed by the 74F139 Decoder. The signal
that clocks the decoder is a combination of
MCYC (Memory Cycle) and DRAW, that results in a new signal, MACC. This signal is
also used in the timing block.
ments grows exceedingly complicated as the
number of components grows. It becomes
even more apparent when the components
are individual systems with their own set of
timing considerations. In our case, this means
the Lilith, the ACRTC, and the frame buffer.
Figure 21 shows the many elements it takes
to generate the timing signals for the system.
In the middle of the diagram, there are two
74F164 8-bit serial-in/parallel-out shift registers that count the timing states for the rest of
the interface. The Address Strobe (AS) signal, coming from the ACRTC, starts and ends
this timing train. Because of the pulse width of
AS, many states at the end of the train are
unusable. The video RAM FiAS signal (Row
Address Strobe) starts at the beginning of
State 1, and terminates as AS goes Low,
activating the register's MR (Master Reset).
The precharge requirement of RAS is met by
the AS pulse width.
The transceiver outputs are now written into
the frame buffer. From there, they will be sent
to the pixel-shifting stage and then to the
DAC. Each set of four 4-bit pixels in a serial
string of displayed pixels is contained in a
different block of memory. This is the reason
the two lower-order address signals are used
to select one of the four banks in the Video
RAM (frame buffer).
The 74F157 Multiplexers are connected in
such a way that the lower-order addresses
are used for the video RAM row addresses
(the 157 on top). At the beginning of State 3,
the higher-order addresses are presented at
the Video RAM address inputs as the column
address. At State 5 the CAS signal becomes
SYSTEM TIMING
In a system as complicated as a graphics
display board, the timing of the various ele-
AN1081
valid. Because of changes in the data hold
(WRITE cycle) and data setup (READ cycle)
of the ACRTC, the timing edge of CAS might
have to be changed to insure proper operation.
MRD (Memory Read) along with a combination of MCYC and DRAW from the Address
and Data Buffer called MACC, are used with
the two lowest-order address lines from the
74F373s (MAAO and MAA1) to write-select
one of the four memory planes (this memory
plane runs orthogonal to the bit-planes discussed earlier). Because this signal comes
well before the CAS signal, this qualifies as
an early WRITE cycle, allowing the use of
DRAMs with Data-In and Data Out signals
connected together.
Using two flip-flops, the output of the lower
shift register generates the PE (Parallel Enable) signal for the pixel-shifting stage. Because it is clocked from the fifth point in the
shifter, this pulse occurs between States 10
and 11.
The upper left-hand corner of Figure 21
shows the creation of the 2CLK signal derived from the 40MHz pixel clock by using a
74Ft61 Counter that performs a divide-byeight operation.
TOPULL·UP
10
""'---------o
lIAS } TO
DSa,b aD I--OOC_......
CP
CP
10
t--i>o--'WIo-------oO liAS
VIDEO
RAM
Q2
2CLK
(DeLK)
L_~=~~j:===:::t-o lIE
Ai
FROM ADDRESS/ {
DATA BUFFER
AND SCC63484
PIXa.
SHIFnNG
MACe
MRD
~---ISa.ECT
Eij
14F139
AOb
MAAO
MAAI
iib-3b
WEi-Wf4
TO
VIDEO
RAM
14Pt51
'!lI-Yd
.-----'---1-"--'''-1 lO-3/a,b
Alb
ENABLE
MAA8, 14,1, '15, 8, MAli, 9, MAI1
Figure 21. Components for System Timing
February 1987
TO
11-46
I=::;iC=:>
TO
VIDEO
RAM
Signetics Unear Products
Application Note
AN1081
NE5150/51/52 Family of Video Digifal-fo-Analog Converters
speeds. These modules are SIPs (single inline packages) and were used because of
space considerations. Each module consists
of eight 64k X l-bit DRAMs, giving eight
modules of 64k X 8 or a 64k x 64 buffer.
This buffer is divided into four sections
(64k X 16) that represent the four bits of
address that are shifted out to the NE5150's
CLUT.
pixel are shifted out simultaneously before
going to the 74F157 multiplexer. From there,
they address the colors of the CLUT on the
Video DAC.
PIXEL SHIFTING
The pixel-shifting stage consists of 8 very fast
74F166 Shift Registers divided into 4 banks,
one for each address bit. These shift registers
have maximum operating frequencies of
120MHz.
VIDEO RAM
The data comes from the address and data
buffering and the video RAM. The PE (Parallel Enable Input) signal from the system
timing block activates the register, while the
pixel clock, DCLK, strobes each of the registers. All chips are permanently enabled by
grounding their chip enable (CE) pins. The
master reset (MR) is permanently disabled by
tying it to a pull-up.
The phrase "Video RAM" refers to a set of
dynamic RAMs used as the memory section
in this application. It is not meant to be
confused with the Video RAM which is a
dedicated device for video applications.
One can see how the frame buffer is set up to
shift out data to the pixel shifter. The memory
is divided into 4 banks that are write-selected
by the WEl - WE4 pulses. Two modules
(64k X 16 bits) make up one bank. This
makes up the four 16-bit words that are
shifted out. But where is the information for
each pixel? Taking the 1st bank as an example, it can be divided into 4 quadrants:
The Video RAM or frame buffer section
consists of 8 Fujitsu MB85103-10 modules.
The 10 suffix signals a lOOns row access
time. The cycle time is about 200ns, or about
5MHz. This is fine because only the pixel
clock has to travel at the high screen draw
The connection between the registers and
the memory is such that all the bits of each
PE
DCLK
rNC-
~
os
PE
CP
MR
I
TO PULL·UP
~
os
PE
I-f--
CP
07
74Fl66
U
DO-D7
CEI1
M4D12,8,4,O
8 M3D12,8,4,O
16
I"
NC-
DS
~
PE
CP
MR
it
CE
q
jf
00-07
I"
os
PE
74P166
~~ CP
00-07
~
CE
q.
TOPULL.-UP
07
-.J.f
CE
I--
i1
M2D13, 9, 5, 18 M1D13,9,S,1
M4Dl3,9,5,l
8 M3Dl3, 9, 6, 1
16
07
MR
07
00-07
MR
74Fl66
M2D12,8,4,0
8 M1D12,8,4,O
TOPULL·UP
74F166
TOPULloUP
/
I"
FROM
ADDRESS AND DATA
BUFFERING AND
FRAME BUFFER
NC-
os
MR
~
PE
74Fl66
CP
DS
07
00-07
it
CE
q. r-
~
PE
~ CP
rNC-
os
MR
'---
PE
74P166
CP
-n
q
74P166
00-07
CE
q.
DS
'-- PE
L....-
M4D1S, 11, 7,3
8 M3D1S, 11, 7, 3
CP
TOPULL·UP
MR
07
74Fl66
00-07
-.J.f
11-47
CEh
3
M2D15,11, 7,
8 M1D1S, 11, 7,3
Figure 22. Shift Registers for Pixel-Shifting
February 1987
r-O DCJr3
07
I
TO PULL·UP
CE
DOT2
TOPULL·UP
M2D14, 10, 6, 2
8 M1D14,lO,6,2
07
DO-D7
MR
-.J.f
M4D14, 10, 6, 2
8 M3D14, 10, 8, 2
16
16
I"
TOPULL·UP
Lo DOrO
L---o DOI'1
TO
74P157
•
Signetics Linear Products
Application Note
NE5150/51/52 Family of Video Digital-to-Analog Converters
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Vss
Vcc
DQO
*"
DQ1
GG-
~
M11lO
M1D1
1GIG-
-
~
M1D8
MlOO
IGIG-
M21lO
M2D1
GG-
M2D8
M200
IGIG-
MallO
M3D1
GG-
M3D8
M300
,~
G-
M4D8
M4D1
.~
M400
~
A7
AS
A4
IG1G-
DQ2
DQ3
M1D2
M1D3
GG-
M1D10
M1D11
GG-
M2D2
M2D3
iGIG-
WEt
WE
M2D1O
M2D11
wn
IGIG-
M3D2
M3D3
MA7
MAS
~
MAC
~
M3D1O
M3D11
I~
M4D2
M4D3
I~
~
I~
~
IGIG-
DQ4
DOS
M1D4
M1D5
GG-
M1D12
M1D13
GG-
M2D4
M2D5
IGIG-
M2D12
M2D13
~
M3D4
M3DS
~
A2
GG-
DQ6
DQ7
~
-
M1D8
M1D7
GG-
-
M1D14
M1D15
I;;
IG....
M3D13
GG-
M4D4
M4D5
IGIG-
M2D8
M2D7
I~
M4D12
M4D1
MA2
MAIl
I:::
I~
RAS
l~
MAlI
M3D12
I~
.~
All
I;;
m
MA3
I~
All
M4D1
M4on
MAl
I~
A3
CA!
~
WEI
Al
=+sv
ccr
V,
I- M41lO
I~
CA!
Vss
-
-:::
-
~
AN1081
RAS
M2D14
G-
M3D8
M2D15
..~
M3D7
I~
L:::.
....
IG-
l~
M3D14
M3D1S
~
.::.
L:.
M4D6
M4D7
GG-
M4D14
M4D1
-
Figure 23. Memory Configuration to Store Pixels
M1DO-M1D3, M1D4-M1D7,
M1D8-M1D11, and M1D12-M1D15. Each
of these quadrants represents a dot. By
tracking each dot in parallel back to the shift
February 1987
register in the pixel·shifting stage, they turn
out to be each of the four quadrants in
parallel. Comparing diagrams reveals the
same to be true for each of the quadrants in
11-48
each of the four banks of memory. Each
quadrant, then, corresponds to one pixel, and
all of the pixels for one bank are written out to
the shift register during a write cycle.
Signetics Linear Products
Application Note
AN1081
NE5150/51/52 Family of Video Digifal-fo-Analog Converters
VIDEO DAC INTERFACE
The interface to the NE5150 is shown in
Figure 24. The 8·bit data bus comes from the
lower 8 bits of the Lilith. The low 4 bits are
connected directly to the Video DAC data
inputs. Bits 4-7 are tied to the 74F157
Multiplexer. This provides the address to the
CLUT when it is initialized.
The other set of inputs to the multiplexer
comes from the pixel·shifting stage. After the
the BLANKing signal. Both of these signals
come from the ACRTC and the system timing
section. The WHITE, BRIGHT, and SYNC
inputs are not utilized and are connected to
ground. VEE is run off a 7905 voltage regulator powered by a -12V power supply.
first CLUT initialization, all of the addresses
come from the pixel·shifter. The inverters,
NAND gates, and OR gates are used to delay
the write pulses WRR, WRG, and WRB so
that they fit into the address setup window.
The chip select pulses come from the 74F138
which are selected by the Lilith. I/OCLK
clocks the 74138 and the OR gates for the
chip select.
The capacitors to the monitor and voltage
regulator are polarized with the positive end
to the monitor for the RGB outputs and to
ground for the regulator. The regulator uses
Tantalum capacitors.
DCLK drives the STROBE of the DAC and
clocks the two D·type flip-flops which provide
r-----1~--------t--lOPULL-UP
FROM {--O--------------I
SCC63484 DISPI
TIM~g DCLKo------------1___~
(74F74)
Vee= +5V
BUS3-BUSO
4
1lO-D3
~OM[::::~~~~::::::::::::::::::::::~t:::::::~
'------,f-...,
Vee STROBE
LILITH
BLANK
lA-1D
YA-YDI====:;t===:JI
RED
AO-A3
GREEN
BLUE
NES150
WHITE
74F157
~~: [:::::~::4::::~~ OA-OD
SHIFTING
tl=-
BRIGHT
SELECT
WRR
SYNC
•
"oND
DaND
L-_ _ _.... VEE = -5V
I/OCLKo------------------....J
-~Vo--------------------J
60095618
FIgure 24. NE5150 Video DAC Interface
February 1987
11-49
Signetics Linear Products
Application Note
NE5150/51/52 Family of Video Digital-to-Analog Converters
GLOSSARY
This glossary consists of three parts: a section for graphics terminology, one for the
timing of the NE5150 used in the Lilith workstation application, and a list of references. For
the glossary section, many analogies are
made with television to clarify some terminology.
GRAPHICS TERMINOLOGY
ACRTC - Short for Advanced CRT Controller. A device that helps to interface a microprocessor or microcomputer with a monitor.
Advanced refers to the Signetics ACRTC, the
SCC63484, called advanced because of its
ability to do most of its graphics computations
on-board, thus relieving some of the workload
from the microprocessor and increasing its
overall efficiency.
Bit-Map, Bit-Plane - A memory representation in which one or more bits correspond to a
pixel. For each bit used in the representation
of a pixel, there is a plane on which it can be
mapped. To represent each pixel by 4 bits, 4
bit planes are needed. This is the case
whether the bits store the actual data for the
pixel or hold the address of the memory
location containing the data.
Blanking - The process of turning off an
electron gun so that it leaves no trace on the
screen as it returns to the left or top of the
screen in a raster-scan system. Applies to
both television sets and monitors. The period
for the blanking is defined as the horizontal
blanking and the vertical blanking interval for
their respective cases.
CRT - Short for Cathode Ray Tube, a type
of electron tube that produces an electron
beam that strikes the phosphor-coated
screen, causing that screen to emit light.
Chromlnance - The color information supplied in a signal. While this information has to
be extracted by color decoders in television
(via phase differencing with a fixed-frequency
subcarrier), in computer monitors and bitmapped systems it is supplied digitally and
then converted to analog to directly drive
color guns.
Color Look-up Table - Sometimes referred
to as the ClUT, it is associated with a Video
DAC and speeds system access of oftenused colors. The time savings results because a color can be generated by sending a
ClUT address to the DAC instead of loading
a word from external memory. Current ClUTs
range in size from 16 to 256 words. Word
length depends on the bit resolution of the
DAC.
DAC - Short for Digital-to-Analog Converter.
Most DACs have a single output. Some have
February 1987
as many as eight. RGB Video DACs have
three - one for each of the primary colors.
Video DACs typically operate at very high
speeds since they have to supply a new piece
of information for each pixel on the screen at
rates of 30 to 80 times per second.
ECl - Short for Emitter-Coupled-logic. A
fast, non-saturating form of bipolar logic that
usually operates from 0 to -5.2V. It has a
threshold of -1.3V.
Frame Buffer - Sometimes used interchangeably with video RAM. A frame buffer is
a large, fast-access store of memory that
contains the digital information necessary to
display part or all of a display. It is used in
conjunction with bit-mapped graphic systems.
It actually "stores" the bit-plane.
Glitch Energy - The area displaced by an
analog signal as it overshoots or undershoots
its ideal value. This is a problem usually found
in DACs. Units are usually given in pV-s.
When glitch energy is high, settling times tend
to be longer and may result in visual color
aberrations on the screen.
Hue - The actual color(s) on a monitor. The
hue depends on the frequency of the light
striking the human eye. For television transmission, it is determined by the video signal's
phase difference with a color subcarrier reference frequency. For computer graphics systems, it is determined by the combination of
binary values applied to the DAC. The resolution of hue/colors is determined by the bit
length of each word of information.
Lilith - The brand name of the workstation
manufactured by Modulo, Inc. of Provo, UT.
luminance - The brightness information in
a video Signal. A black and white (monochrome) monitor displays only variations in
brightness. Only a luminance signal is being
manipulated. The same holds true for television. Although chrominance information is
also present in a television signal, B/W TV
sets do not have the necessary decoders.
Modula-2 - A language that is the superset
of Pascal. This was also invented by Niklaus
Wirth of the Swiss Technological Institute.
NTSC - Short for the National Television
Standards Committee, the ruling body for
television standards in the United States.
Other countries also use this standard as is,
or with a different frequency for the color
subcarrier.
Orthogonal - Defined as being mutually
perpendicular. The product of Iwoorthogonal
vectors is zero. In bit-mapped systems, the bit
length of a word lies orthogonal to the plane
itself. Hence, each plane supplies only one bit
of information for each pixel.
11-50
AN1081
Pixel - Short for "picture element". The
smallest resolvable element on a graphics
display. Each pixel usually corresponds to at
least one bit. The entire display is made up of
a map of pixels. The term bit-map comes
from the bit association. There is no equivalent in television. What is seen is the true
analog representation of what is being recorded by a camera and then retraced on
horizontal lines.
Raster-Scan - The form of visual display
transmission used in all television sets and in
most monitors. It consists of an electron
beam tracing a path from left-to-right while
going top-to-bottom.
Saturation - The "deepness" of a color.
Usually depends on the amplitude of the color
Signal in television systems. Red and pink are
the same hue, but red is actually more
saturated than pink. In graphics systems,
there is no true equivalent. Changing bitvalues changes the color itself. The closest
analogy would be to raise or lower the voltages on all three color guns simultaneously
(the BRIGHT function on the NE5150/51/
52). This WOUld, however, depending on the
amplitude change, give the impression of
brightening or dimming the color (changing
luminance) rather than saturating it.
Sync - The voltage level specified in RS343A as being 140 IRE (1 V) below the
enhanced white level (ground). It is also 40
IRE (286mV) below the blanking level. Generically it is also used to refer to vertical and
horizontal sync pulses that synchronize the
timing and movement of the electron beam
on a CRT. It should not be confused with
"composite sync".
Teletext - A form of data transmission via
television signals. In many cases, digital information is sent during the vertical blanking
interval (VB I). In some cases, it is sent during
every retrace. This is known as full-field
teletext.
TTL - Short for Transistor-Transistor logic.
It has a threshold voltage of approximately
lAV and is the most widely-used form of logic
in the world today.
DEFINITIONS FOR NE5150/511
52 TIMING DIAGRAMS
This section contains explanations for the
NE5150/51152 Video DAC's timing diagram
specifications. For the typical, minimum, and
maximum values, please refer to Signetics'
data sheet.
tWAS -
Write Address Setup (NE5150/52)
tWAH -
Write Address Hold (NE5150/52)
tWDS -
Write Data Setup (NE5150/52)
Signetics Linear Products
Application Note
NE5150j51j52 Family of Video Digifal-fo-Analog Converters
Write Data Hold (NE5150/52)
tR -
tWEw-Write Enable Pulse Width
(NE5150/52)
tWOH -
ts -
tRcs -
Read Composite Setup (NE5150/52)
REFERENCES
The following books, articles, notes, and
correspondences were used in the preparation of this application note.
1. Raster Graphics Handbook, 2nd edition,
by the Conrac Corporation
2. "Trends in Graphics Hardware", paper
by Randall R. Bird, Genisco Computers
Corporation; presented at WESCON '85
3. Basic Television and Video Systems, 5th
edition, by Bernard Grob,. McGraw-Hili
4. Getting the Best Performance from Video
Digital-to-Analog Converters, (AN-I) by
Dennis Packard, Brooktree Corporation,
San Diego
5. "A Cost-Effective Custom CAD System" ,
paper by R.C. Burton, D.G. Brewer, R.E.
DAC Rise Time (NE5151)
DAC Full-Scale Settling Time (NE5151)
6.
tRCH -
Read Composite Hold (NE5150/52)
tRAS -
Read Address Setup (NE5150/52)
tRAH -
Read Address Hold (NE5150/52)
tRsW - Read Strobe Pulse Width
(NE5150/52)
tROD tcs -
Read DAC Delay (NE5150/52)
Composite Setup (NE5151)
tCH -
Composite Hold (NE5151)
tos -
Data bits Setup (NE5151)
tOH -
Data bits Hold (NE5151)
tsw -
Strobe Pulse Width (NE5151)
too - DAC Delay (NE5151)
7.
8.
9.
AN1081
Penman, and R. Schilimoeller, Computer
Science Department, Brigham Young
University and Signetics Corporation
"Lilith and Modula-2", by Richard Ohran,
Byte Magazine, pgs. 181 -192; August
1984
"Monolithic Color Palette Fills in the
Picture for High-Speed Graphics", by
Steven Sidman and John C. Kuklewicz,
Electronic Design; November 29, 1984
EIA Standard RS-343A: Electrical Performance Standards for High-Resolution
Monochrome Closed-Circuit Television
Camera, by the Video Engineering Department of the Electronic Industries Association; September, 1969
"A Single-Chip RGB Digital-to-Analog
Converter with High-Speed Color-Map
Memory", by W. Mack and M. Horowitz,
Digest of the International Conference on
Consumer Electronics, p. 90; 1985
•
February 1987
11-51
PNA7518
Signetics
a-Bit Multiplying DAC
Product Specification
Linear Products
DESCRIPTION
FEATURES
The PNA7518 is an NMOS 8-bit multiplying digital-to-analog converter (DAC) designed for video applications. The device
converts a digital input signal into a
voltage-equivalent analog output at a
sampling rate of 30MHz.
• TTL input levels
• Positive edge-triggered
• Analog voltage output at 30M Hz
sampling rate
• Binary or two's complement
input
• Output voltage accuracy to
within ± 12 of the Input LSB
The input signal is latched, then fed to a
decoder which switches a transfer gate
array (1 out of 256) to select the appropriate analog signal from a resistor
chain. Two external reference voltages
supply the resistor chain.
The input latches are positive edgetriggered. The output impedance is approximately O.5kn, depending upon the
applied digital code. An additional operational amplifier is required for the full
bandwidth. Two's complement is selected when STC (Pin 11) is HIGH or is not
connected.
PIN CONFIGURATION
APPLICATIONS
•
•
•
•
Video data conversion
CRT displays
Waveform/test signal generation
Color/black-and-whlte graphics
SYMBOL
VAO
•
5
6
7
8
9
10
11
12
13
TEMPERATURE RANGE
16-Pin Plastic DIP (SOT-38WE-1)
TOP VIEW
PIN NO.
VralL
ORDERING INFORMATION
DESCRIPTION
N Package
ORDER CODE
o to +70°C
PNA7518N
"
15
16
bitbit 3]
2
bit 1
bit 0
Vaa
V"
DESCRIPTION
Analog output voltage
Reference voltage lOW
Digital voltage inputs (VI)
Least-significant bit (lSB)
Back bias
Ground
feLK
STC
Reference voltage HIGH
Clock input
Select two's complement
Most-significant bit (MSB)
bit 6
bit 5
Digital voltage inputs (VI)
VrelH
bit 7]
bit 4
Voo
Positive supply voltage
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
UNIT
Voo
Supply voltage range (Pin 16)
PARAMETER
-0.5 to +7
V
VI
Input voltage range (Pins 3, 4, 5, 6,
11, 12, 13, 14 and 15)
-0.5 to +7
V
VAO
Output voltage range (Pin 1)
-0.5 to +7
V
ProT
Total power dissipation
400
mW
-65 to + 150
°C
TSTG
Storage temperature range
TA
Operating ambient temperature range
October 10, 1986
o to
+70
11-52
°C
853-0897 85942
Product Specification
Signetics Unear Products
PNA7518
8-Bit Multiplying DAC
BLOCK DIAGRAM
DIGITAL VOLTAGE INPUT (V,)
BIT BIT BIT BIT BIT BIT BIT BIT ( +5 V)
SELECT
TWO'S
COMPL EMENT
(STC)
o
1
11 LSB 6
CLCCKINPUT
(I CLK )
10
Y
2
5
3
4
4
5
6
7
Voe
MSB
16
15 14 13 12
3
INPUT BUFFER/LATCH x "
~"Jr
DECODER
~
9
256
PNA7518
h
rL
I
I
I
REFERENCE
VOLTAGE
INPUTS
,
1
-~
2
~
ANALCG
VOLTAGE
OUTPUT
(VAO)
~
~
'-100 TO 150nF
I
-!- 7
?
!"
HANDLING
Inputs and outputs are protected against
electrostatic charge in normal handling, However, to be totally safe, it is desirable to take
normal precautions appropriate to handling
MOS devices.
•
CLOCK
ANALOG
OUTPUT
1---------lpO>---------I-Figure 1. Switching Characteristics
October 10, 1986
11-53
Signetics Linear Products
Product Specification
PNA7518
8-Bit Multiplying DAC
DC ELECTRICAL CHARACTERISTICS Voo = 4.5 to 5.5; Vss = OV; CBB = 100nF; TA = 0 to + 70·C, unless otherwise
specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
5
5.5
V
50
80
mA
V
Supply (Pin 16)
VDO
Supply voltage
100
Supply current
4.5
Reference voltages
VREFL
Reference voltage LOW (Pin 2)
-0.1
+2.1
VREFH
Reference voltage HIGH (Pin 9)
-0.1
+2.1
V
RREF
Reference ladder
150
300
Q
VIL
VIH
Digital input levels (TTL) 1
input voltage LOW
input voltage HIGH
input leakage current
0
2.0
O.B
5.25
10
V
V
p.A
VIL
VIH
Clock input (Pin (0)
input voltage LOW
input voltage HIGH
input leakage current
0
2.0
0.8
5.25
10
V
V
p.A
230
Inputs
'l
'll
Output
VAO
Analog voltage output (Pin 1)
at RL = 200 kQ)
BW
Bandwidth (-3 dB) at CL
=6
0
pF
2
V
12
MHz
Output transients (glitches)2
VG
Glitch occurring at step 7F-80 (HEX):
maximum amplitude for 1 LSB change area
3
23
LSB
LSB ns
VG
Glitch occurring at step OO-AA (HEX):
maximum amplitude for 1 LSB change area
5
41
LSB
LSB ns
PTOr
Total power dissipation
300
mW
October 10, 1986
11-54
Signetics Linear Products
Product Specification
8-Bit Multiplying DAC
PNA7518
AC ELECTRICAL CHARACTERISTICS VDD = 4.5 to 5.5; Vss = OV; CBB = 100nF; TA = 0 to + 70'C, unless otherwise
specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
fClK
tpWH
tPWl
tR
tF
Clock input (Pin 10)
frequency
pulse width HIGH
pulse width LOW
input rise time at fClK = 30MHz
input fall time at fClK = 30MHz
Typ
1
10
10
Max
30
3
3
MHz
ns
ns
ns
ns
Switching characteristics (Figure 1)
tsu.
tDAT
Data setup time
3
ns
tHD,
tDAT
Data hold time
4
ns
tpD
Propagation delay time, input to output
iclK + 22
tClK + 30
ns
tS1
Settling time; 10 to 90% full-scale change;
Cl = 6pF; Rl = 200kil
13
20
ns
tS2
Settling time to ± 1 LSB;
Cl = 6pF; Rl = 200kil
40
± Y2
LSB
Linearity at Rl
= 200kil;
Va
tClK+15
= 2Vp_p
ns
Influence of clock frequency2
Cross-talk at 2 X fClK
amplitude
area
2
8
LSB
LSB ns
NOTES:
1. Inputs Bit 0 to 8it 7 are positive edge-triggered and STe.
2. Measured at VREFH - VREFL = 2.0 V; 1 X LSB = 7.SmV. The energy equivalent of output transients is given as the area contained by the graph of output amplitude
(LSB) against time (ns). The glitch area is independent of the value of VREF. Glitch amplitudes and clock cross-talk can be reduced by using a shielded printed
circuit board (see Pin Configuration).
•
October 10, 1986
11-55
TDA5702
Signetics
a-Bit Digital-to-Analog
Converter
Preliminary Specification
Linear Products
DESCRIPTION
FEATURES
The TDA5702 is an 8-bit digital to analog
converter (DAC) designed for video and
professional applications. The TDA5702
converts the 8-bit binary-coded digital
words into an analog output signal at a
sampling rate of 25M Hz. The design of
the TDA5702 has eliminated the need
for an operational amplifier, buffer and
deglitching circuit at the analog output.
•
•
•
•
PIN CONFIGURATION
S-bit accuracy
Internal input register
TTL compatible digital signals
Two voltage supply connections:
-analog +5V
- digital + 5V
• Two complementary outputs
N Package
(VOUT, VOUT)
• No deglitching circuit required
• Low power consumption;
typically 300mW
lOP VIEW
• 16-lead plastiC DIP
APPLICATIONS
•
•
•
•
PIN NO.
1
Video data conversion
Color/black-and-white graphics
CRT displays
Waveform/test signal generation
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
o to +70'C
TDA5702N
16-Pin Plastic DIP (SOT-38)
7
B
9
10
11
12
13
14
15
16
SYMBOL
DESCRIPTION
REF
Current reference loop
decoupling
AGND Analog ground
Bit 3
Bit 4
25MHz clock input
felK
DGND Sigital ground
Bit 8
Most significant bit (MSB)
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
VCC2
~
VCC1
Least significant bit (lSB)
Digital supply voltage
Analog voltage output
Complementary analog voltage
output
Analog supply voltage
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
VCC2
VCC1
Supply voltage
at Pin 13
at Pin 16
VIN
Input voltage
at Pins 3, 4, 5, 7, 8, 9, 10, 11 and 12
TSTG
Storage temperature range
TJ
Junction temperature
TA
Operating ambient temperature range
November 14, 1986
RATING
UNIT
8
8
V
V
8
V
-65 to +150
'c
'c
'c
+125
o to
+70
11-56
853-0976 86551
Preliminary Specification
Signetics Linear Products
TDA5702
8-Bit Digital-to-Analog Converter
BLOCK DIAGRAM
r---------------------~----~---4r__t1~S-o~~
REFO-~~----------------,
AGNO
15
v;.;;-
i'
VOUT
DGNO
":"
feLK
BIT 3
INPUT
INTERFACES
BIT'
MSB BITS
13
LSB 12
11
10
9
BIT 7
Vee.
BIT1
BIT2
BITS
BIT 6
TDA5702
•
November 14, 1986
11-57
Preliminary Specification
Signetics Linear Products
TDA5702
8-Bit Digital-to-Analog Converter
DC ELECTRICAL CHARACTERISTICS
VCC1 = VCC2 = 4.75 to 5.25V, TA = 0 to + 70·C, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
TEST CONDITIONS
Min
Typ
Max
Supply
VCC2
Digital supply voltage
Pin 13
4.75
5.0
5.25
Vcel
Analog supply voltage
Pin 16
4.75
5.0
5.25
V
IC02
Digital supply current
Pin 13
25
34
43
rnA
ICCI
Analog supply current
Pin 16
20
27
34
Res
Resolution
V
rnA
bits
8
Digital Input levels
2.2
V
VIH
Input voltage HIGH
VIL
Input voltage LOW
0.8
10
V
IJA
IIH
Input current HIGH
IlL
Input current LOW
-1.5
rnA
IlL
Clock Input current LOW
-1.0
rnA
Outputs2
to
VFS
Full-scale voltage
with respect
Vzs
Zero offset voltage
with respect to Vee
Vee
1.43
1.6
1.75
V
10
25
mV
Absolute linearity
V14, VIS
-0.5
+0.5
LSB
Differential linearity
V14, VIS
-0.5
+0.5
LSB
R16-14
Output resistance
75
n
Cl
External capacitance
100
nF
NOTES:
1. See Agure 3.
2. See Agure 2.
3. See Figure 1.
AC ELECTRICAL CHARACTERISTICS
VCCI ~ VCC2 = 4.75 to 5.25V, TA = 0 to + 70·C, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Min
Typ
Max
Timing
25
fe
Maximum conversion rate
los
Data tum-on delay1
taET1
Transient settling time
It:!
tSET2
Transient settling time
to
Transient output (glitch) energy
MHz
10
ns
LSB
30
ns
1 LSB
20
ns
+50
LSB ns
tpw
Pulse width3
10
tau
Data setup time
4
ns
tH
Data hold time
6
ns
NOTE:
1. See Figure 1.
November 14, 1986
11-58
ns
Preliminary Specification
Signetics Linear Products
TDA5702
8-Bit Digital-to-Analog Converter
DATA
CLOCK
OUTPUT
Figure 1. Timing Diagram
E
VCCI
75
VOIIT
+I
AGND
Figure 2. Equivalent Analog Output Circuit
.---OVCC2
3.5k
DATA
.
0--+01
....1---+
....
~
~ ..
~,
'----ODGND
Figure 3. Equivalent Digital Input Circuit
November 14. 1986
11·59
•
TDA8440
Signetics
Video and Audio Switch
Ie
Product Specification
Linear Products
DESCRIPTION
The TDA8440 is a versatile video/audio
switch, intended to be used in applications equipped with video/audio inputs.
It provides two 3-State switches for audio channels and one 3-State switch for
the video channel and a video amplifier
with selectable gain (times 1 or times 2).
The integrated circuit can be controlled
via a bidirectional 12C bus or it can be
controlled directly by DC switching signals. Sufficient sub-addressing is provided for the 12C bus mode.
FEATURES
• Combined analog and digital
circuitry gives maximum flexibility
In channel switching
• 3-State switches for all channels
• Selectable gain for the video
channels
• Sub-addressing facility
• 12C bus or non-1 2C bus mode
(controlled by DC voltages)
• Slave receiver In the 12C bus
mode
• External OFF command
• System expansion possible up to
7 devices (14 sources)
• Static short-circuit proof outputs
PIN CONFIGURATION
N Package
VlDEOIlIN 1
OFF
FUNCTION IN
VIDEO IINPUT
3
AUDIOI.IN 5
AUDIO II. IN
BYPASS 8
AUDiOIAIN _9...._ _ _..J-lOP VIEW
APPLICATIONS
• TYRO
• Video and audio switching
• Television
• CATV
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
18-Pin Plastic DIP (SOT-l02)
o to
ORDER CODE
70·C
TDA8440N
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
14
V
Vcc
Supply voltage Pin 15
VSDA
VSCl
VOFF
Vso
VS 1
VS2
Input
Pin
Pin
Pin
Pin
Pin
Pin
-1 16
Video output current Pin 16
50
rnA
TSTG
Storage temperature range
-65 to +150
·C
TA
Operating ambient temperature range
TJ
Junction temperature
8JA
Thermal resistance from junction to
ambient in free-air
February 12, 1987
voltage
17
18
2
11
13
6
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
to
to
to
to
to
to
Vcc
Vee
Vee
Vee
Vee
Vcc
o to
+0.3
+0.3
+0.3
+0.3
+0.3
+0.3
+70
V
V
V
V
V
V
·C
+150
·C
50
·C/W
11-60
853-1172 87583
Product Specification
Signetics Linear Products
Video and Audio Switch
Ie
TDA8440
BLOCK DIAGRAM AND TEST CIRCUIT
rr.,.+-i---i
rl-:-+--I--I
rl-:-+-t--I
1k
AUDIOI.
-=
AUDIOII.
-=
AUDIO I.
r
-=
AUDIO II.
-=
1k
1k
1k
D.47_F
9
+
101;.;.1_ _ _ _ _ So
0.47.F
VIDEOII
75
+
AUDIO BOUT
fk
OA7_F
13
I------s.
100nF
16
....--t---~r. VIDEOOUT
100nF
~I--ir--I
-=
r-r
14 1D.F
~DEOI ~I--+---i
-=
AUDIO A OUT
fk
D.47.F 10
1-:-+-'--1---1
75
r-r-
12 1D.F
-=
1",F
I
1-'-----50
+
17
18
OFF
SDA
}
I'cBUS
L~=~r--r-- SCL
1-_+1:;.5_ _ _ _ _ Vee
-=
NOTE:
SO, 51, 52, and OFF (Pins 11, 13, 6, and 2) connected to Vee or GND. If more than 1 device is used, the outputs and Pin 8 (bias decoupling of the audio inputs) may be connected In
parallel.
February 12, 1987
11-61
..
Signetics Linear Products
Product Specification
Video and Audio Switch
Ie
TDA8440
DC ELECTRICAL CHARACTERISTICS TA - 25°C; Vee = 12V, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
Supply
V'S-4
Supply voltage
I,s
Supply current (without load)
10
13.2
V
37
50
rnA
Video switch
C,C3
Input coupling capacitor
100
A3_'6
A3_'6
Voltage gain (times 1; SCL = L)
(times 2; SCL = H)
-1
+5
0
+6
+1
+7
dB
dB
nF
A'_'6
A'_'6
Voltage gain (times 1; SCL = L)
(times 2; SCL = H)
-1
+5
0
+6
+1
+7
dB
dB
V
V3-4
Input video signal amplitude (gain times 1)
4.5
V'_4
Input video signal amplitude (gain times 1)
4.5
Z'6_4
Output impedance
Z'6_4
Output impedance in 'OFF' state
100
k.Il
Isolation (off-state) (fo = 5MHz)
60
dB
S/S+N
Signal-to-noise rati0 2
60
V'6-4
Output top-sync level
2.4
G
Differential gain
V
n
7
dB
2.8
3.2
V
3
%
V'6_4
Minimum crosstalk attenuation'
60
RR
Supply voltage rejectiona
36
dB
dB
BW
Bandwidth (ldB)
10
MHz
ex
Crosstalk attenuation lor interference caused by bus signals
(source impedance 75n)
60
db
Audio switch "A" and "B"
V9_4 (RMS)
V'0-4 (RMS)
VS_4 (RMS)
V7_4 (RMS)
Z9_4
Z'0_4
ZS-4
Z7_4
2
2
2
2
Input signal level
50
50
50
50
Input impedance
Z'2-4
Z'4-4
Output impedance
Z'4-4
Output impedance (off-state)
kn
kn
kn
kn
10
10
100
-1
-1
-1
-1
V9_'2
V'0-'2
VS_'4
V7_'4
Voltage gain
Isolation (off-state) (I = 20kHz)
90
S/S+N
Signal-to-noise rati04
90
THO
Total harmonic distortion6
February 12, 1987
100
100
100
100
n
n
kn
0
0
0
0
+1
+1
+1
+1
dB
dB
dB
dB
dB
dB
0.1
11-62
V
V
V
V
%
Product Specification
Signetics Linear Products
Video and Audio Switch
Ie
TDA8440
DC ELECTRICAL CHARACTERISTICS (Continued) TA ~ 25'C; vee ~ 12V, unless otherwise specilied.
LIMITS
UNIT
PARAMETER
SYMBOL
Min
Crosstalk attenuation lor interferences
caused by video signalsS
Weighted
Unweighted
0:
0:
0:
Typ
Max
80
80
dB
dB
Crosstalk attenuation lor interferences caused by sinusoidal
sound signals5
80
dB
Crosstalk attenuation for interferences caused by the bus
signal (weighted) (source impedance ~ 1k.l1)
80
dB
RR
Supply voltage rejection
50
dB
BW
Bandwidth (-1 dB)
50
kHz
12C bus inputs/outputs SOA (Pin 17) and SCl (Pin 18)
V
VIH
Input voltage HIGH
3
Vee
VIL
Input voltage lOW
-0.3
+1.5
V
IIH
Input current HIGH 7
10
/1 A
!1A
IlL
Input current LOW 7
10
VOL
Output voltage LOW at IOL ~ 3mA
0.4
IOL
Maximum output sink current
CI
Capacitance 01 SDA and SCl inputs, Pins 17 and 18
5
V
rnA
10
pF
Sub-address inputs So (Pin 11), SI (Pin 13), S2 (Pin 6)
VIH
Input voltage HIGH
3
Vee
V
VIL
Input voltage LOW
-0.3
+0.4
V
IIH
Input current HIGH
IlL
Input current LOW
-50
10
/1 A
0
!1A
OFF input (Pin 2)
VIH
Input voltage HIGH
+3
Vee
V
VIL
Input voltage LOW
-0.3
+0.4
V
IIH
Input current HIGH
20
/1 A
IlL
Input current LOW
2
/1 A
-10
NOTES:
1. Caused by drive on any other input at maximum level, measured in B = 5MHz, source impedance for the used input 7551,
VOUT
crosstalk = 2010g - - - .
VIN max
2. SIN = 2010g Vo video noise (P - P) (2V).
Vo noise AMS B = 5MHz
VA supply
3. Supply voltage ripple rejection = 2010g
at I = max. 100kHz.
VA on output
Vo nominal (0.5V)
4. SIN = 2010g
.
Vo noise B = 20kHz
5. Caused by drive of any other input at maximum level, measured in B = 20kHz, source impedance of the used input = 1k.Q,
VOUT
crosstalk = 2010g - - - according to DIN 45405 (CCIR 468).
VIN
max
6. I = 20Hz to 20kHz.
7. Also if the supply is switched off.
February 12, 1987
11-63
•
Signetics Unear Products
Product Specification
Ie
Video and Audio Switch
AC ELECTRICAL CHARACTERISTICS
TDA8440
12C bus load condHions are as follows: 4kn pull-up resistor to +5V; 200pF to GND_
All values are referred to VIH = 3V and VIL - 1.5V.
LIMITS
UNIT
PARAMETER
SYMBOL
Min
Typ
Max
tBUF
Bus free before start
4
jlS
Is (STA)
Start condition setup time
4
jlS
IH
Start condition hold time
4
jlS
SCl. SDA lOW period
4
jlS
tHIGH
SCL, HIGH period
4
tR
SCl. SDA rise time
1
jlS
tF
SCl. SDA fall time
0.3
jlS
Is (OAT)
Data setup time (write)
1
jlS
tH (OAT)
Data hold time (write)
1
ps
ts (CAC)
Acknowledge (from TDA8440) setup time
tH (CAC)
Acknowledge (from TDA8440) hold time
0
jlS
Is (STO)
Stop condition setup time
4
jlS
(STA)
tLOW
Table 1. Sub-Addressing
SUB-ADDRESS
S2
S,
So
l
l
l
l
H
H
H
l
l
H
H
l
l
H
l
H
l
H
l
H
l
H
H
H
A2
A,
Ao
0
0
0
0
1
1
0
0
1
0
1
0
1
0
0
0
1
1
1
0
1
non 12C
addressable
FUNCTIONAL DESCRIPTION
The TDA8440 is a monolithic system of
switches and can be used in CTV receivers
equipped with an auxiliary vid~o/audio plug.
The IC incorporates 3-State switches which
comprise:
a) An electronic video swHch wHh selectable
gain (times 1 or times 2) jor switching
between an internal video signal (from the
IF amplifier) with an auxiliary Input signal.
February 12. 1987
ps
2
b) Two electronic audio switches. for two
sound channels (stereo or dual language).
for switching between internal audio
sources and' signals from the auxiliary video/ audio plug.
A selection can be made between two input
signals and an OFF-state. The OFF-state is
necessary if more than one TDA8440 device
is used.
The SDA and SCl pins can be connected to
the 12C bus or to DC switching voltages.
Inputs So (Pin 11). S, (Pin 13). and S2 (Pin 6)
are used for selection of sub-addresses or'
switching to the non-1 2C mode. Inputs So. S,.
and S2 can be connected to the supply
voltage (H) or to ground (l). In this way. no
peripheral components are required for selection.
NON-1 2C BUS CONTROL
If the TDA8440 switching device has to be
operated via the auxiliary video/audio plug.
inputs S2. S,. and So must be connected to
the supply line (12V).
11-64
ps
The sources (internal and external) and the
gain of the video amplifier can be selected via
the SDA and SCl pins with the switching
voltage from the auxiliary video/ audio plug:
• Sources I are selected if SDA = 12V
(external source)
• Sources " are selected If SDA = OV (TV
mode)
• Video amplifier gain is 2 X if SCl = 12V
(external source)
• Video amplifier gain is 1 X if SCl = OV
(TV mode)
If more than one TDA8440 device is used in
the non-12C bus system. the OFF pin can be
used to switch off the desired devices. This
can be done via the 12V switching voltage on
the plug.
• All switches are in the OFF position if
OFF=H (12V)
• All switches are in the selected position
via SDA and SCl pins if OFF = l (OV)
12C BUS CONTROL
Detailed information on the 12C bus is available on request.
Signetlcs Linear Products
Product Specification
Video and Audio Switch
Ie
TDA8440
Table 2. TDA8440 12C Bus Protocol
Do
STA
= start condition
~:
:
A3
A2
A,
Ao
R/W
AC
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D,
D,
Do
Do
STO
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
~
1 Fixed
AC
STO
address bits
1
sub-address bit, fixed via S2 input
sub-address bi~ fixed via S, input
sub-address bit, fixed via So input
read/write bit (has to be 0, only write mode allowed)
acknowledge bit (= 0) generated by the TDA8440
1 audio la is selected to audio output a
0 audio la is not selected
1 audio lIa is selected to audio output a
0 audio lIa is not selected
1 audio Ib is selected to audio output b
0 audio Ib output is not selected
1 audio lib is selected to audio output b
0 audio lib is not selected
1 video I is selected to video output
0 video I is not selected
1 video II is selected to video output
0 video II is not selected
1 video amplifier gain is times 2
0 video amplifier gain is times 1
1 OFF-input inactive
0 OFF-input active
stop condition
Do/OFF Gating
OFF input
Do
o (off
input active)
0
H
L
1 (off input inactive)
1
H
L
OFF FUNCTION
With the OFF input all outputs can be
switched off (high ohmic mode), depending
on the value of Do.
Power-on Reset
The circuit is provided with a power-on reset
function.
Outputs
OFF
In accordance with last defined
D7 - D, (may be entered while
OFF=HIGH)
In accordance with D7 - D,
In accordance with D7 - D,
When the power supply is switched on, an
internal pulse will be generated that will reset
the internal memory SQ. In the initial state all
the switches will be in the off position and the
OFF input is active (D7 - Do = 0), (1 2C mode).
In the non-1 2C mode, positions are defined via
SDA and SCL input voltages.
SDA
(WRITE)
SCL
Figure 1. 12 C Bus Timing Diagram
February 12, 1987
11·65
When the power supply decreases below 5V,
a pulse will be generated and the internal
memory will be reset. The behavior of the
switches will be the same as described
above.
•
Signetics
NE/SA5204
Wide-band High-Frequency
Amplifier
Product Specification
Linear Products
DESCRIPTION
The NE/SAS204 is a high-frequency
amplifier with a fixed insertion gain of
20dB. The gain is flat to ± O.SdB from DC
to 200M Hz. The -3dB bandwidth is
greater than 3S0MHz. This performance
makes the amplifier ideal for cable TV
applications. The NE/SAS204 operates
with a single supply of 6V, and only
draws 25mA of supply current, which is
much less than comparable hybrid parts.
The noise figure is 4.8dB in a 7S,n
system and 6dB in a SO,n system.
The NE/SA5204 is a relaxed version of
the NES20S. Minimum guaranteed bandwidth is relaxed to 350MHz and the "S"
parameter MinIMax limits are specified
as typicals only.
Until now, most RF or high-frequency
designers had to settle for discrete or
hybrid solutions to their amplification
problems. Most of these solutions required trade-offs that the designer had
to accept in order to use high-frequency
gain stages. These include high power
consumption, large component count,
transformers, large packages with heat
sinks, and high part cost. The NE/
SAS204 solves these problems by incorporating a wideband amplifier on a single
monolithic chip.
The part is well matched to 50 or 75,n
input and output impedances. The
standing wave ratios in SO and 7S,n
systems do not exceed 1.S on either the
input or output over the entire DC to
3S0MHz operating range.
No external components are needed
other than AC-coupling capacitors because the NE/SAS204 is internally compensated and matched to 50 and 75,n.
The amplifier has very good distortion
specifications, with second and thirdorder intermodulation intercepts of
+ 24dBm and + 17dBm, respectively, at
100MHz.
The part is well matched for SO,n test
equipment such as signal generators,
oscilloscopes, frequency counters, and
all kinds of signal analyzers. Other applications at 50,n include mobile radio, CB
radio, and data/video transmission in
fiber optiCS, as well as broadband LANs
and telecom systems. A gain greater
than 20dB can be achieved by cascading additional NE/SA5204s in series as
required, without any degradation in amplifier stability.
FEATURES
• 200MHz (min.), ± O.SdB bandwidth
• 20dB Insertion gain
• 4.8dB (6dB) noise figure
Zo 7S,n (Zo So,n)
• No external components required
• Input and output Impedances
matched to SOI7S,n systems
• Surface-mount package available
• Cascadable
=
=
PIN CONFIGURATION
N, D Packages
TOP VIEW
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
Antenna amplifiers
Amplified splitters
Signal generators
Frequency counters
Oscilloscopes
Signal analyzers
Broadband LANs
Networks
Modems
Mobile radio
CB radio
Telecommunications
Since the part is a small, monolithic IC
die, problems such as stray capacitance
are minimized. The die size is small
enough to fit into a very cost-effective 8pin small-outline (SO) package to further
reduce parasitic effects.
ORDERING INFORMATION
DESCRIPTION
8·Pin Plastic DIP
8·Pin Plastic SO package
February 12, 1987
TEMPERATURE RANGE
ORDER CODE
o to +70·C
NE5204N
-40 to +85·C
SA5204N
o to +70·C
NE5204D
-40 to +85·C
SA5204D
11-66
853-1191 87586
Signetics Linear Products
Product Specification
Wide-band High-Frequency Amplifier
NEjSA5204
ABSOLUTE MAXIMUM RATINGS
SYMBOl.
PARAMETER
RATING
UNIT
Vce
Supply voltage
9
V
VIN
AC input voltage
5
Vp_p
TA
Operating ambient temperature range
NE grade
SA grade
o to +70
-40 to +65
'C
'C
1160
760
mW
mW
PD
Maximum power dissipation1, 2
T A = 25'C (still-air)
N package
o package
TJ
Junction temperature
TSTG
Storage temperature range
TSOLD
Lead temperature
(soldering 60s)
150
'C
-55 to +150
'C
300
'C
NOTES:
1. Derate above 25°C, at the following rates
N package at 9.3mWrC
o package at 6.2mWI'C.
2. See "Power Dissipation Considerations" section.
EQUIVALENT SCHEMATIC
Vec
R2
Flo
VOUT
Q.
Q2
R,
V,N 0----.-----'[:
RE2
February 12, 1967
11-67
•
Product Specification
Signetics Linear Products
NEjSA5204
Wide-band High-Frequency Amplifier
DC ELECTRICAL CHARACTERISTICS at Vce = 6V, Zs = ZL = Zo = 50Q and TA = 25°C, in all packages, unless otherwise
specified.
LIMITS
SYMBOL
PARAMETER
UNIT
TEST CONDITIONS
Min
Vee
Operating supply voltage range
Over temperature
5
Icc
Supply current
Over temperature
19
S21
Insertion gain
= 100MHz, over temperature
f = 100MHz
16
S11
f
Input return loss
S22
S12
Isolation
BW
Bandwidth
BW
Bandwidth
19
22
dB
dB
27
dB
DC -550MHz
12
dB
= 100MHz
-25
dB
-18
dB
±0.5dB
200
350
MHz
-3dB
350
550
MHz
4.8
dB
= 100MHz
f = 100MHz
f = 100MHz
f = 100MHz
f
1dB gain compression
rnA
= 100MHz
DC -550MHz
Saturated output power
V
31
dB
f
Noise figure (50Q)
8
24
12
f
Noise figure (75Q)
Max
25
DC -550MHz
Output return loss
Typ
6.0
dB
+7.0
dBm
+4.0
dBm
Third-order intermodulation
intercept (output)
f
= 100MHz
+17
dBm
Second-order intermodulation
intercept (output)
f
= 100MHz
+24
dBm
35
34
<
E
32
30
~
26
i3
..~
~
Zo=500
TA=25°C
VCC=8V
VCC=7V
v"cc=6V
VCC=5V
24
A'I.'
,~", ~ ~
~
22
20
18
5
16
5
5.5
6.5
10'
7.5
8 102
Figure 2_ Noise Figure vs Frequency
Figure 1. Supply Current vs Supply Voltage
February 12, 1987
6
FREQUENCV-MHz
SUPPLY VOLTAGE-V
11-68
I.
Signetics Linear Products
Product Specification
NE/SA5204
Wide-band High-Frequency Amplifier
25
25
Vcc~~1=
VCC=7V"7
Vec=6V
VCc=5V
I--Zo=500
I - - TA=25·C
6
"'l
~
'"
"
"\:
z
o
'"~
15 -VCC=8V
-Zo=soo
10
8 102
6
10'
FREQUENCY-MHz
E
111
6
l~
VCC=7V
10
9
Vee=BV
,;...
.!.
Vee=SV
~
...
1
0
~
g :~
r---
Vee=7V
r---
Vce=6V
-3 r-Zo=500
1
0
-S
6
8 102
6
6
10'
...
35
30
V
cI
z
0
0
/
20
w
0
II:
...w
20
w
15
~
II:
TA=25°C
Zo=soo
c
9
c
II:
TA=25°C
rZo=500
-
5
10
4
POWER SUPPLY VOlTAGE-V
10
POWER SUPPLY VOlTAGE-V
Figure 7. SecQnd-Order Output Intercept vs Supply Voltage
February 12, 1987
/
10
V
i"..o"
...
I
4
I-'
II:
:;:
10
25
0-
/
15
w
'"
...'j'
."
/
25
w
0
•
30
E
W
C
II:
....
8 102
111
0-
...~
"-
Figure 6. 1dB Gain Compression vs Frequency
40
w
II:
"- r-..
FREQUENCY-MHz
111
0
II:
'"
'"
-6
8103
Figure 5. Saturated Output PQwer vs Frequency
E
........
.....
-4
FREQUENCY-MHz
...I
-
Vce=5V
r---Zo=50n
-3 r - - TA=250C
-5
-6
~
--
4
: I;;;""-
.......
......
g:~
10'
8 103
6
Vce=6V
VCC=8V
g
...
102
Figure 4. Insertion Gain vs Frequency (5 21)
!
~
•
FREQUENCY-MHz
Figure 3. InsertiQn Gain vs Frequency (5 21 )
11
10
9
8
7
..,
T..,=85°C
ii:w
10
10'
4O"1~1~
-
T!=
TA-2S·C
l20
11-69
Figure 8. Third-Order Intercept vs Supply Voltage
Signetics Linear Products
Product Specification
NE/SA5204
Wide-band High-Frequency Amplifier
•• 0
••0
1.9
1.9
1.8
1.8
TA=25°C
1.7
VCC=6V
'"
'"
it 1.6
VJ
it 1.6
VJ
>
l-
~
>
1.5
::>
0. 1.4
1.3
1.7
1.5
::>
0.
1.4
::>
0 1.3
I-
=
I-
20=750
1••
e-- Zo=750
1••
1.1 -20=500
1.1
1.0
10'
•
•
8 102
!-- 20=500
1.0
10'
8103
6
Figure 9. Input VSWR vs Frequency
Figure
40
",'8
35
"''''
30
"1
I",
"'0
0 ....
.... z
z'"
"'::>
::>1-
::>0.
0.1z::>
-0
10.
r---...
-15
""I~
r----
'"
1
~~ OUTPUT
ZO=50n
TA=25°C
VCC=6V
2":'20
I~
VCC=6V
Zo = 500
TA=2j O C
''"o"
..J
INPJ~ ~ ~
15
- -25
1-
6
-30
10'
8102
FREQUENCY-MHz
Figure
11.
25
-
VCc=~V-\
20
~
~
~
-
8 102
Figure 12. Isolation vs Frequency (5'2)
VCC=~V ""'
.,
6
VCc=~V
VCC=5V -
15
~
-
.,....., ~V
FREQUENCY-MHz
Input (S,d and Output (522 ) Return Loss vs
Frequency
.5
1
Output VSWR vs Frequency
-10
25
I-w
w'"
"'I- 20
1-::>
8 102
FREQUENCY-MHz
FREQUENCY -MHz
/
TA=
'i''"z
20
r ...,
"
TA= 85°C
0
••
~
w 15 -20=750
-VCC=6V
'"~
Zo=750
f-
~
;;:
z
""-
-400Jl- f-
T~= 25·C
TA=2SoC
10
10
10'
•
10'
• 10'
8 102
6
8 103
Figure 14. Insertion Gain vs Frequency (5 21 )
Figure 13. Insertion Gain vs Frequency (S.d
February 12, 1987
6
FREQUENCY-MHz
FREQUENCY-MHz
11-70
Signetics Linear Products
Product Specification
Wide-band High-Frequency Amplifier
THEORY OF OPERATION
The design is based on the use of multiple
feedback loops to provide wide-band gain
together with good noise figure and terminal
impedance matches. Referring to the circuit
schematic ir. Figure 15, the gain is set primarily by the equation:
Your
v;;;-
NEjSA5204
The DC input voltage level VIN can be determined by the equation:
(3)
where REI = 12n, VSE = O.BV, ICI = 5mA
and IC3 = 7mA (currents rated at Vcc = 6V).
(1)
Under the above conditions, VIN is approximately equal to 1V.
which is series-shunt feedback. There is also
shunt-series feedback due to RF2 and RE2
which aids in producing wide-band terminal
impedances without the need for low value
input shunting resistors that would degrade
the noise figure. For optimum noise performance, REI and the base resistance of 0,
are kept as low as possible, while RF2 is
maximized.
Level shifting is achieved by emitter-follower
03 and diode 0 4 , which provide shunt feedback to the emitter of 0, via RFI. The use of
an emitter-follower buffer in this feedback
loop essentially eliminates problems of shuntfeedback loading on the output. The value of
RFI = 140n is chosen to give the desired
nominal gain. The DC output voltage Your
can be determined by:
=
(RFI + RE1)/REl
The noise figure is given by the following
equation:
[rb+RE1+~]} dB
NF = 10Log [ 1 + _ _ _ _-=2"'q"'ICl
Ro
(2)
where ICI = 5.5mA, REI = 12n, rb = 130n,
KT Iq = 26mV at 25'C and Ro = 50 for a 50n
system and 75 for a 75n system.
Your = Vcc - (IC2+ Ics)R2,
where Vcc = 6V, R2
IC6 = 5mA.
= 225n,
(4)
IC2 = 7mA and
From here, it can be seen that the output
voltage is approximately 3.3V to give relatively equal positive and negative output swings.
Diode 05 is included for bias purposes to
allow direct coupling of RF2 to the base of 0,.
The dual feedback loops stabilize the DC
operating point of the amplifier.
The output stage is a Darlington pair (06 and
02) which increases the DC bias voltage on
the input stage (0,) to a more desirable
value, and also increases the feedback loop
gain. Resistor Ro optimizes the output VSWR
(Voltage Standing Wave Ratio). Inductors L,
and L2 are bondwire and lead inductances
which are roughly 3nH. These improve the
high-frequency impedance matches at input
and output by partially resonating with 0.5pF
of pad and package capacitance.
POWER DISSIPATION
CONSIDERATIONS
When using the part at elevated temperature,
the engineer should consider the power dissipation capabilities of each package.
At the nominal supply voltage of 6V, the
typical supply current is 25mA (30mA max).
For operation at supply voltages other than
6V, see Figure 1 for lac versus Vcc curves.
The supply current is inversely proportional to
temperature and varies no more than 1rnA
between 25'C and either temperature extreme. The change is 0.1 % per 'C over the
range.
The recommended operating temperature
ranges are air-mount specifications. Better
heat-sinking benefits can be realized by
mounting the SO and N package bodies
against the PC board plane.
vee
R,
650
R,
225
RO
J------.----+-....10""'...rYr'n...-{)
Vour
3nH
V,N
RE'
12
RE'
12
"'""'''''''
Figure 15. Schematic Diagram
February 12, 1987
11-71
•
Signetics Unear Products
Product Specification
NE/SA5204
Wide-band High-Frequency Amplifier
PC BOARD MOUNTING
In order to realize satisfactory mounting of the
NE5204 to a PC board, certain techniques
need to be utilized. The board must be
double-sided with copper and all pins must be
soldered to their respective areas (i.e., all
GND and Vee pins on the package). The
power supply should be decoupled with a
capacitor as close to the Vcc pins as possible, and an RF choke should be inserted
between the supply and the device. Caution
should be exercised in the connection of
input and output pins. Standard microstrlp
should be observed wherever possible. There
should be no solder bumps or burrs or any
obstructions in the signal path to cause
launching problems. The path should be as
straight as possible and lead lengths as short
as possible from the part to the cable connection. Another important consideration is that
the input and output should be AC-coupled.
This is because at Vcc = 6V, the input is
approximately at 1V while the output is at
3.3V. The output must be decoupled into a
low-impedance system, or the DC bias on the
output of the amplifier will be loaded down,
causing loss of output power. The easiest
way to decouple the entire amplifier is by
soldering a high-frequency chip capacitor directly to the input and output pins of the
device. This circuit is shown in Figure 16.
Follow these recommendations to get the
best frequency response and noise immunity.
The board design is as important as the
integrated circuit design itself.
Both of the evaluation boards that will be
discussed next do not have input and output
capacitors because it is assumed the user will
use AC-coupled test systems. Chip or foil
capacitors can easily be inserted between the
part and connector if the board trace is
removed.
8-LEAD MINI-PACK; PLASTIC (90-8; SOT-96A)
" q,
;-i
""
II
0 0 tJ 0
CAPACllOA HOLE
Vcc PLANE
OUTPUT
GNDPLANE
GNDPLANE
SONCKAGE
HOLE BACKSIDE
SONCKAIIE
HOl.E TOPSIDE
Bono..
lOP
GNDFLANGE
SMA CONNECTOR
Figure 17. PC Board Layout for NE5204 Evaluation
TCOII511S
Figure 16_ Circuit Schematic for
Coupling and Power Supply Decoupllng
February 12, 1987
n
il
11-72
Signetics Linear Products
Product Specification
NEjSA5204
Wide-band High-Frequency Amplifier
tion around its side to isolate Vee and ground.
The square hole is for the SO package which
is put in upside-down through the bottom of
the board so that the leads are kept in
position for soldering. Both holes are just
slightly larger than the capacitor and IC to
provide for a tight fit.
50n EVALUATION BOARD
The evaluation board layout shown in Figure
17 produces excellent results. The board is to
scale and is for the SO package. Both top
and bottom are copper clad and the ground
planes are bonded together through 50n
SMA cable connectors. These are solder
mounted on the sides of the board so that the
signal traces line up straight to the connector
signal pins.
This board should be tested in a system with
50n input and output impedance for correct
operation.
Solid copper tubing is soldered through the
flange holes between the two connectors for
increased strength and grounding characteristics. Two- or four-hole flanges can be used.
A flat, round decoupling capacitor is placed in
the board's round hole and soldered between
the bottom Vce plane and the top side
ground. The capacitor is as thin or thinner
than the PC board thickness and has insula-
75n EVALUATION BOARD
Another evaluation board is shown in Figure
18. This system uses the same PC board as
presented in Figure 17, but makes use of 75n
female N-type connectors. The board is
mounted in a nickel plated box' that is used
to support the N-type connectors. This is an
n
excellent way to test the part for cable TV
applications. Again, the board should be tested in a system with 75n input- and outputimpedance for correct operation.
NOTE:
"The box and connectors are available as a "MODPACK SYSTEM" from the ANZAC division of
ADAMS-RUSSELL CO., INC., 80 Cambridge Street,
Burlington, MA 01803.
SCATTERING PARAMETERS
The primary specifications for the NE5204
are listed as S-parameters. S-parameters are
measurements of incident and reflected currents and voltages between the source, amplifier, and load as well as transmission
losses. The parameters for a two-port network are defined in Figure 19.
FEEDTHRU
0.489
(11.9)
MODEL 7014
1084
(27.5)
0 . 3 : . i t O . 0 6 2 TYP
(9.5)
(1.6)
0.750
(19.1)
O.984L--!
(24.9)
BOTTOM VIEW
Figure 18. 7Sn N-Type Connector System
February 12, 1987
l l.I
r-
0.200 (5.1) TYP
Q.290 (7.4) TYP
[0·
7014-1 (BNC)
7014-2 (THC)
7014-3 (TYPE H)
7014-4 (SMA)
11-73
•
Signetics Linear Products
Product Specification
Wide-band High-Frequency Amplifier
NEjSA5204
S" - INPUT RETURN LOSS
s"
•
··1
S,. -
POWER REFLECTED
FROM INPUT PORT
I~
S,. "VTRANSDUCER POWER GAIN
POWER AVAILABLE FROM
GENERATOR AT INPUT PORT
S" -
FORWARD TRANSMISSION LOSS
OR INSERTION GAIN
S" -
OUTPUT RETURN LOSS
POWER REFLECTED
FROM OUTPUT PORT
REVERSE TRANSMISSION LOSS
OR ISOLATION
POWER AVAILABLE FROM
GENERATOR AT OUTPUT PORT
REVERSE TRANSDUCER
POWER GAIN
s"
a. Two-Port Network Defined
b.
Figure 19
son
5ystem
7Sn 5ystem
2.
VCC=8V
vcc· 7V
=
vcc=~v
Vcc· sv
!----- Zo·7SO
,. 1.'
•
• 10J
2
,.1.'r---
e '10'
FREQUENCY-MHz
a. Insertion Gain vs Frequency (52,)
,
• 102
• 1()3
b. Insertion Gain vs Frequency (521)
-,a
I
-1'
1
ill
zo",l son
~
_r-I........... ~II
I
- 2.
-3.
1.'
6
:I.
8 102
6
-,.
I
~~~!!~C
2-20
~
8
FREQUENCY-MHz
-1.
"
T,,=2S-C
z
Q -20
~
~
-2'
-30
8103
FREQUENCY-MHz
,--
'.'
/1/
VCC=6V
20=750
YA=2r C
V
• '102
FREQUENCY - MHz
I
'1()3
0P0481OS
4.
c. Isolation vs Frequency (5'2)
d. 5'2 Isolation vs Frequency
40
3.
"~ 3.
ig
Ii!!
ti 2'
"'. .." 2. r---~I!:
III ill 3'
""'"
I I
3.
OUTPUT
s§
~
~'"
2.
II! a:
2•
~
Vcc· IV
Zo.soo
~~
.iEig~~.. ,.
INP~~ ~r.
-
TA 11: 2rC
!g 1.
,.,.,
-'z
I
• 1()2
,.,.'
., ',()3
FREQUENCY-MHz
~
INPIT
;g~;:~
I
- ~~
TA=2S·C
• ',03
I 8,02
FREQUENCY -
e. Input (5,,) and Output (522) Return Loss. vs
Frequency
MHz
f. Input (5,,) and Output (522) Return Loss vs
Frequency
Figure 20
February 12, 1987
-- "'
r--- -OUTPUT
11-74
Product Specification
Signetics Linear Products
NE/SA5204
Wide-band High-Frequency Amplifier
Actual S-parameter measurements, using an
HP network analyzer (model 8505A) and an
HP S-parameter tester (models 8503A1B),
are shown in Figure 20, These were obtained
with the device mounted in a PC board as
described in Figures 17 and 18.
For 50n system measurements, SMA connectors were used. The 75n data was obtained using N-connectors.
Values for Figure 20 are measured and specified in the data sheet to ease adaptation and
comparison of the NE5204 to other highfrequency amplifiers. The most important parameter is S21. It is defined as the square root
of the power gain, and, in decibels, is equal to
voltage gain as shown below:
Also measured on the same system are the
respective voltage standing-wave ratios.
These are shown in Figure 21. The VSWR
can be seen to be below 1.5 across the entire
operational frequency range.
Relationships exist between the input and
output return losses and the voltage standing
wave ratios. These relationships are as follows:
INPUT RETURN LOSS = S"dB
S11dB = 20Log 1S11 1
OUTPUT RETURN LOSS
S22dB = 20Log 1S221
INPUT VSWR =
= S22dB
11 + S111
-I--I';;; 1.5
1-S"
Zo = ZIN = ZOUT for the NE5204
PIN
VIN 2 ~I
=-
NE5204
~
Zo
2
~OpOUT-_ VOUT
--
Zo
Zo
0
VOUT 2
POUT
---z;VIN
11 + S221
-I- - I ,;;; 1.5
1 -S22
1dB GAIN COMPRESSION AND
SATURATED OUTPUT POWER
VOUT 2
:. - - = - - 2 - = - - 2 - = PI
PIN
OUTPUT VSWR =
VIN
The 1dB gain compression is a measurement
of the output power level where the smallsignal insertion gain magnitude decreases
1dB from its low power value. The decrease
is due to non-linearities in the amplifier, an
indication of the point of transition between
small-signal operation and the large-signal
mode.
Zo
= VI 2
PI = Insertion
PI
Power Gain
VI = Insertion Voltage Gain
Measured value for the
NE5204 = 1S21 12 = 100
The saturated output power is a measure of
the amplifier's ability to deliver power into an
external load. It is the value of the amplifier's
output power when the input is heavily overdriven. This includes the sum of the power in
all harmonics.
In decibels:
PI(dB)
VI(dB)
= 10Log
= 20Log
:. PI (dB)
1S21 12 = 20dB
S21
= 20dB
= VI(dB) = S21(dB) = 20dB
2.0
1.'
1.8
1.7
II:
3: 1.6
> 1.5
...'"
::J
0-
liO
1.4
1.3
INTERMODULATION INTERCEPT
TESTS
The intermodulation intercept is an expression of the low level linearity of the amplifier.
The intermodulation ratio is the difference in
dB between the fundamental oulput signal
level and the generated distortion product
level. The relationship between intercept and
intermodulation ratio is illustrated in Figure
22, which shows product output levels plotted
versus the level of the fundamental output for
two equal strength output signals at different
frequencies. The upper line shows the fundamental output plotted against itself with a 1dB
to 1dB slope. The second and third order
products lie below the fundamentals and
exhibit a 2:1 and 3:1 slope, respectively.
The intercept point for either product is the
intersection of the extensions of the product
curve with the fundamental output.
The intercept pOint is determined by measuring the intermodulation ratio at a single output
level and projecting along the appropriate
product slope to the point of intersection with
the fundamental. When the intercept point is
known, the intermodulation ratio can be determined by the reverse process. The second-order IMR is equal to the difference
between the second-order intercept and the
fundamental output level. The third-order IMR
is equal to twice the difference between the
third-order intercept and the fundamental output level. These are expressed as:
IP2
= POUT + IMR2
+ IMR3/2
IP3 = POUT
where POUT is the power level in dBm of each
of a pair of equal level fundamental output
signals, IP2 and IP3 are the second- and thirdorder output intercepts in dBm, and IMR2 and
IMR3 are the second- and third- order intermodulation ratios in dB. The intermodulation
intercept is an indicator of intermodulation
performance only in the small-signal operat-
2.0
1.'
1.8
II: 1.7
3:
'">.... 1.6
1.5
::J
=
0....
1.'
0 1.3
r-- Zo =75!l
1.2
1.1 f-- ZOo son
1.0
10'
::J
Zo=750
1.'
1.1 r- Zo = 500
1.0
10'
6
8 102
FREQUENCY-MHz
6
8 102
FREQUENCY-MHz
b_ Output VSWR vs Frequency
a, Input VSWR vs Frequency
Figure 21_ Input/Output VSWR vs Frequency
February 12, 1987
11-75
6
8 103
•
Signetics Linear Products
Product Specification
NEjSA5204
Wide-band High-Frequency Amplifier
ing range of the amplifier. Above some output
level which is below the 1dB compression
point, the active device moves into largesignal operation. At this point, the intermodulation products no longer follow the straightline output slopes, and the intercept description is no longer valid. It is therefore important
to measure IP2 and IPs at output levels well
below 1dB compression. One must be careful, however, not to select levels which are
too low, because the test equipment may not
be able to recover the signal from the noise.
For the NE5204, an output level of ,.10.5dBm
was chosen with fundamental frequencies of
100.000 and 100.01 MHz, respectively.
+30
....w
.....
...::>~'O
0
PO~NT
i
RESPONSE .......
-10
/
-20
-30
lL
-40
-60
POINT
V ~
V1
/ J-. RESrONjE J----- 2ND ORDER
RESPONSE
I
I
/
-50
~~fE~~~~~
~1
I
FUNOAMENTAl
.... E
--
')fj
1 dB
COMPRESSION
+10
>
w
',I-
THIRD ORDER
INTERCEPT POINT
+20
3RO ORDER
L
-40 -30
-20
-10
0
+10 +20 +30 T40
INPUT LEVEL
dBm
ADDITIONAL READING ON
SCATTERING PARAMETERS
For more information regarding S-parameters, please refer to High-Frequency Amplifiers; by Ralph S. Carson of the University of
Missouri, Rolla, Copyright 1985, published by
John Wiley & Sons, Inc.
February 12, 1987
Figure 22
S-Parameter Techniques for Faster, More
Accurate Network Design, HP App Note 95-1,
Richard W. Anderson, 1967, HP Journal.
11-76
S-Parameter Design, HP App Note 154, 1972.
Signetics
NE/SA/SE5205
Wide-band High-Frequency
Amplifier
Product Specification
Linear Products
DESCRIPTION
The NE/SA/SE5205 is a High Frequency Amplifier with a fixed insertion gain of
20dB. The gain is flat to ± 0.5dB from DC
to 450MHz, and the -3dB bandwidth is
greater than 600MHz in the EC package.
This performance makes the amplifier
ideal for cable TV applications. For lower
frequency applications, the part is also
available in industrial standard dual inline and small outline packages. The
NE/SA/SE5205 operates with a single
supply of 6V, and only draws 25mA of
supply current, which is much less than
comparable hybrid parts. The noise figure is 4.8dB in a 75n system and 6dB in
a 50n system.
Until now, most RF or high frequency
designers had to settle for discrete or
hybrid solutions to their amplification
problems. Most of these solutions required trade-offs that the designer had
to accept in order to use high frequency
gain stages. These include high power
consumption, large component count,
transformers, large packages with heat
sinks, and high part cost. The NE/SAI
SE5205 solves these problems by incorporating a wide-band amplifier on a single monolithic chip.
The part is well matched to 50 or 75n
input and output impedances. The
Standing Wave Ratios in 50 and 75n
systems do not exceed 1.5 on either the
input or output from DC to the -3dB
bandwidth limit.
75n. The amplifier has very good distortion specifications, with second and
third-order intermodulation intercepts of
+ 24dBm and + 17dBm respectively at
100MHz.
The device is ideally suited for 75n
cable television applications such as
decoder boxes, satellite receiver I decoders, and front-end amplifiers for TV receivers. It is also useful for amplified
splitters and antenna amplifiers.
The part is matched well for 50n test
equipment such as signal generators,
oscilloscopes, frequency counters and
all kinds of signal analyzers. Other applications at 50n include mobile radio, CB
radio and data/video transmission in
fiber optics, as well as broad-band LANs
and telecom systems. A gain greater
than 20dB can be achieved by cascading additional NE/SAlSE5205s in series
as required, without any degradation in
amplifier stability.
N, FE, D Packages
TOP VIEW
EC Package
NOTE:
Tab denotes Pin 1.
FEATURES
• 650MHz bandwidth
• 20dB insertion gain
• 4.8dB (6dB) noise figure
Zo 75n (Zo 50n)
• No external components required
• Input and output impedances
matched to 50/75n systems
• Surface mount package available
• Excellent performance in cable
TV 75n systems
=
=
•
APPLICATIONS
Since the part is a small monolithic IC
die, problems such as stray capacitance
are minimized. The die size is small
enough to fit into a very cost-effective 8pin small-outline (SO) package to further
reduce parasitic effects. A TO-46 metal
can is also available that has a case
connection for RF grounding which increases the -3dB frequency to 650MHz.
The metal can and Cerdip package are
hermetically sealed, and can operate
over the full -55°C to + 125°C range.
•
•
•
•
•
•
•
•
•
75n cable TV decoder boxes
Antenna amplifiers
Amplified splitters
Signal generators
Frequency counters
Oscilloscopes
Signal analyzers
Broad-band LANs
Fiber-optics
No external components are needed
other than AC coupling capacitors because the NE/SAlSE5205 is internally
compensated and matched to 50 and
•
•
•
•
Modems
Mobile radio
CB radio
Telecommunications
February 12, 1987
PIN CONFIGURATIONS
11-77
853-0058 87583
Signetics Linear Products
Product Specification
NEjSAjSE5205
Wide-band High-Frequency Amplifier
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
o to
o to
o to
o to
8-Pin Plastic SO
8-Pin Metal can
4-Pin Cerdip
8-Pin Plastic DIP
ORDER CODE
+70°C
NE5205D
+70°C
NE5205EC
+70°C
NE5205FE
+70°C·
NE5205N
8-Pin Plastic SO
-40°C to +85°C
SA5205D
8-Pin Plastic DIP
-40°C to + 85°C
SA5205N
8-Pin Cerdip
-40°C to + 85°C
SA5205FE
8-Pin Cerdip
_55°C to + 125°C
SE5205FE
EQUIVALENT SCHEMATIC
Vee
RO
:l--~--._-~>--_"IIIV_---() Vour
t----+----i:.
0,
0,
V,N 0 - - -.......- ( " 0,
RE'
R"
February 12, 1987
11-78
Signetics Linear Products
Product Specification
NEjSAjSE5205
Wide-band High-Frequency Amplifier
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
Vce
Supply voltage
9
V
VAe
AC input voltage
5
Vp_p
TA
Operating ambient temperature range
NE grade
SA grade
SE grade
o to +70
-40 to +85
-55 to + 125
'C
'C
'C
780
1160
780
1250
mW
mW
mW
mW
PD
Maximum power dissipation,
T A = 25'C (still-air) 1, 2
FE package
N package
D package
EC package
NOTES:
1. Derate above 25°C, at the following rates:
FE package at 6.2mW
N package at 9.3mWrC
D package at 6.2mW/'C
EC package at 10.0mW/'C
2. See "Power Dissipation Considerations" section.
rc
DC ELECTRICAL CHARACTERISTICS at Vee = 6V, Zs = ZL = Zo = 50n and TA = 25'C, in all packages, unless otherwise
specified.
SE5205
SYMBOL
PARAMETER
NE/SA/SE5205
TEST CONDITIONS
UNIT
Min
Typ
Max
Min
6.5
6.5
5
5
Operating supply voltage range
Over temperature
5
5
Icc
Supply current
Over temperature
20
19
24
30
31
20
19
S21
Insertion gain
f = 100MHz
Over temperature
17
16.5
19
21
21.5
17
16.5
SII
Input return loss
f
= 100MHz
D, N, FE
DC - fMAX D, N, FE
SII
Input return loss
f
= 100MHz
25
12
Output return loss
f
= 100MHz
S22
Output return loss
f
= 100MHz
Isolation
f
27
February 12, 1987
12
19
21
21.5
dB
dB
dB
-25
-18
dB
dB
26
-18
dB
dB
12
-25
dB
dB
10
= 100MHz
11-79
mA
mA
27
EC package
DC-fMAX
30
31
24
DC-FMAX
S12
24
10
D, N, FE
DC-fMAX
V
V
25
EC package
Max
8
8
12
DC-fMAX EC
S22
Typ
dB
dB
•
Product Specification
Signetlcs linear Products
NE/SA/SE5205
Wide-band High-Frequency Amplifier
DC ELECTRICAL CHARACTERISTICS at Vee = 6V, Zs = ZL = Zo = son and TA = 2SoC, in all packages, unless otherwise
specified.
NE/SAlSE5205
SE5205
SYMBOL
PARAMETER
UNIT
TEST CONDITIONS
Min
Typ
Max
Typ
Min
Max
4S0
MHz
BW
Bandwidth
±O.SdB D, N
fMAX
Bandwidth
-3dB D, N
fMAX
Bandwidth
±0.5dB EC
300
SOD
MHz
fMAX
Bandwidth
±0.5dB FE
300
300
MHz
fMAX
Bandwidth
-3dB EC
fMAX
Bandwidth
-3dB FE
Noise figure (75n)
= 100MHz
f = 100MHz
f = 100MHz
f = 100MHz
f = 100MHz
= 100MHz
SSO
Saturated output power
1dB gain compression
Third·order intermodulation
intercept (output)
f
Second·order intermodulation
intercept (output)
MHz
600
MHz
400
400
f
Noise figure (50n)
MHz
4.8
4.8
6.0
6.0
dB
+7.0
+7.0
dBm
+4.0
+4.0
dBm
+17
+17
dBm
+24
+24
dBm
I I
I I
34
Zo = 500
TA",25°C
.JVCC=8V
L
Vpc=?V
Ycc .. SV
VCCaSV
,.I.
5
5.5
•. 5
•
7.5
~~
8
• 102
FREQUENCY-MHz
Figure I. Supply Current vs Supply Voltage
Figure 2. Noise Figure vs Frequency
11
25
10
9
VCC!8V
'll
t:-
VCC=7y~r-
I 20
z
~
VCC=6V
VCC=5V
i!5
ii!;
/,.,IA
I I
10'
SUPPLY VOLTAGE-V
~ I.
en
1--0."-
dB
VCC=7V
8
7
Vcc=6V
E
'"
6
Vcc=5V
VCC=BV
1
~ -1o
:>
r--Zo='OO
I--- TA =25°C
o -2
-3 r-Zo-SOO
-4 -TA=25 0 C
10
-5
10'
-6
6
8 102
FREQUENCY-MHz
6
e
102
FREQUENCY-MHz
Figure 3. Insertion Gain vs Frequency (S21)
February 12, 1987
10'
Figure 4. Insertion Gain vs Frequency (S21l
11-80
Signetics Linear Products
Product Specification
Wide-band High-Frequency Amplifier
II
10
9
8
E
7
III
6
r S
ill 4
~ 23
oJ
.... I
Q.
0
-I
0 -2
-3 -Zo=50D
-4 -TA=2S"C
-S
-8
10'
Vcc=7V
NEjSAjSE5205
Vcc=6V
....
~
'"
....
•
• ,g2
•
8103
30
"'
/
'i'
.....
Ii:w
U
II:
....w
II:
1/
20
w
c
TA=2SoC
Zo = SOD
IS
C
II:
/
10
'"
6
7
8
TA=25°C
Zo = 500
r- -
I I
1 1
1 I
....X
4
10
9
10
POWER SUPPLY VOLTAGE-V
POWER SUPPLY VOLTAGE-V
Figure 7. Second-Order Output Intercept vs
Supply Voltage
Figure 8. Third-Order Intercept vs
Supply Voltage
2.0
2.0
1.9
1.9
1.8
1.8
1.7
II:
~
1.6
II>
>
> 1.S
....
....
'"....
Q.
1.4
'"0
1.3 =_Zo= 7SD
1.2
1.1
1/
I
.....
5
4
Q.
io'
0
L
IS
20
II:
10
'"
8 10'
25
i!:
W
II>
i!:
•
Figure 6. ldB Gain Compression vs Frequency
3S
....
II>
.....
_
30
W
II:
~
t--Zo-500
TA=2S"C
r--
E
i!: 2S
0
.......
III
W
U
.......
VCc=SV
FREQUENCY-MHz
40
Q.
~
z
.....
t;;-
10'
III
II:
W
C
II:
Vee 6V
0
-4
-5
-8
Figure 5. Saturated Output Power vs Frequency
'"~
I
-3
FREQUENCY-MHz
U
II:
Vcc-7V
~ :~
'"
E
VCC=8V
8
~i
Vc -SV
'"
10
9
r-.Ii ~ r--
Vcc=8V
1.7
1.8
1.5
1.4
1.3
'--Zo=7S0
1.2
r-- Zo=SOD
1.0
10'
6
1.1 r-Zo- SOO
1.0
10'
8 102
• • 192
FREQUENCY-MHz
FREQUENCY-MHz
OP04730S
Figure 9. Input VSWR vs Frequency
February 12. 1987
Figure 10. Output VSWR vs Frequency
11-81
Signetics Unear Products
Product Specification
NE/SA/SE5205
Wide-band High-Frequency Amplifier
,
40
it
35
~g
30
J~
-'z
Za:
a:", 25
2.0
1.9
'.8
""'OII~
::II-
~~
!;s
... I!:
1:&
20
t--
Vcc=6V
Zo=50n
TA=2j"C
~
~ to.....
......
'"0
I::I
INPU~ ~ "'\
-
15
10
10'
~
UT
~ ..... OUT
6
1.7
1.6
1.5
1.4
1.3
-Zo=750
1.2
1.1 '--Zo=50n
1.0
10'
8 102
• • 103
• • 102
FREQUENCY-MHz
. FREQUENCY -MHz
0"'''""
Figure 11. Input (S,,) and Output (S22) Return Loss vs
Frequency
Figure 12. Isolation vs Frequency (S'2)
25
25
VCC=8V ......
VCC=r'=
TA= -55°C
TA= 250CJJ
~ ",
VCc=~V
-
~
oJ I
VCC=5V
,0
1":'-
TA= 85°C
TA=125°C -~
~
"
10
'0'
--
-Zo=750
-VCC=6V
11
Zo=750
TA=25°C
• • 102
FREQUENCY-MHz
'0'
• • 102
FREQUENCY-MHz
OPOoI17OS
Figure 14. Insertion Gain vs Frequency (S2,)
Figure 13. Insertion Gain vs Frequency (S2,)
February 12, 1987
11-82
Product Specification
Signetics Linear Products
NEjSAjSE5205
Wide-band High-Frequency Amplifier
THEORY OF OPERATION
The design is based on the use of multiple
feedback loops to provide wide-band gain
together with good noise figure and terminal
impedance matches. Referring to the circuit
schematic in Figure 15, the gain is set primarily by the equation:
VOUT
V;; = (RFl
+ RE1)/REl
(1)
which is series-shunt feedback. There is also
shunt-series feedback due to RF2 and RE2
which aids in producing wideband terminal
impedances without the need for low value
input shunting resistors that would degrade
the noise figure. For optimum noise performance, REl and the base resistance of 01
are kept as low as possible while RF2 is
maximized.
The noise figure is given by the following
equation:
NF=
10 Log {
1+
[rb + REl +
~]J
2q lCl
dB (2)
Ro
where ICl = 5.5mA, REl = 12n, rb = 1S0n,
KT /q = 26mV at 25°C and Ro = 50 for a 50n
system and 75 for a 75n system.
The DC input voltage level V1N can be determined by the equation:
where REl = 12n, VBE = O.BV, ic1 = 5mA
and IC3 = 7mA (currents rated at Vcc = 6V).
Under the above conditions, V1N is approximately equal to 1V.
Level shifting is achieved by emitter-follower
03 and diode 04 which provide shunt feedback to the emitter of 01 via RF1. The use of
an emitter-follower buffer in this feedback
loop essentially eliminates problems of shunt
feedback loading on the output. The value of
RFl = 140n is chosen to give the desired
nominal gain. The DC output voltage VOUT
can be determined by:
where Vcc
Ics = 5mA.
= 6V, R2 = 225n, IC2 = 7mA and
From here it can be seen that the output
voltage is approximately S.SV to give relatively equal positive and negative output swings.
Diode 05 is included for bias purposes to
allow direct coupling of RF2 to the base of 01.
The dual feedback loops stabilize the DC
operating point of the amplifier.
The output stage is a Darlington pair (Os and
O2) which increases the DC bias voltage on
the input stage (01) to a more desirable
value, and also increases the feedback loop
gain. Resistor Ro optimizes the output VSWR
(Voltage Standing Wave Ratio). Inductors Ll
and L2 are bondwire and lead inductances
which are roughly SnH. These improve the
high frequency impedance matches at input
and output by partially resonating with 0.5pF
of pad and package capacitance.
POWER DISSIPATION
CONSIDERATIONS
When using the part at elevated temperature,
the engineer should consider the power dissipation capabilities of each package.
At the nominal supply voltage of 6V, the
typical supply current is 25mA (SOmA Max).
For operation at supply voltages other than
6V, see Figure 1 for Icc versus Vcc curves.
The supply current is inversely proportional to
temperature and varies no more than 1rnA
between 25°C and either temperature extreme. The change is 0.1 % per °C over the
range.
The recommended operating temperature
ranges are air-mount specifications. Better
heat sinking benefits can be realized by
mounting the 0 and EC package body against
the PC board plane.
PC BOARD MOUNTING
In order to realize satisfactory mounting of the
NE5205 to a PC board, certain techniques
need to be utilized. The board must be
double-sided with copper and all pins must be
soldered to their respective areas (i.e., all
vee
R,
650
Ro
VOUT
10
0,
Figure 15. Schematic Diagram
February 12, 19B7
11-83
3nH
•
Signetics Linear Products
Product Specification
NEjSAjSE5205
Wide-band High-Frequency Amplifier
GND and Vcc pins on the SO package). In
addition, if the EC package is used, the case
should be soldered to the ground plane. The
power supply should be decoupled with a
capacitor as close to the Vee pins as possible
and an RF choke should be inserted between
the supply and the device. Caution should be
exercised in the connection of input and
output pins. Standard microstrip should be
observed wherever possible. There should be
no solder bumps or burrs or any obstructions
in the signal path to cause launching problems. The path should be as straight as
possible and lead lengths as short as possible from the part to the cable connection.
Another important consideration is that the
input and output should be AC coupled. This
is because at Vee = 6V, the input is approximately at 1V while the output is at 3.3V. The
output must be decoupled into a low impedance system or the DC bias on the output of
the amplifier will be loaded down causing loss
of output power. The easiest way to decouple
the entire amplifier is by soldering a high
frequency chip capacitor directly to the input
and output pins of the device. This circuit is
shown in Figure 16. Follow these recommendations to get the best frequency response
and noise immunity. The board design is as
important as the integrated circuit design
itself.
vcc
f--oVOUT
AC
COUPLING
CAPACITOR
Figure 16. Circuit Schematic
for Coupling and Power Supply
Decoupling
8-LEAD MINI-PACK; PLASTIC (SO-8; SOT-96A)
~
February 12, 1987
n n
:1 n
-~~I
5i
I'
I
[J
• I:
0 [J 0
CAPACITOR HOLE (0.25-)
50n EVALUATION BOARD
Solid copper tubing is soldered through the
flange holes between the two connectors for
increased strength and grounding characteristics. Two or four hole flanges can be used.
A flat round decoupling capacitor is placed in
the board's round hole and soldered between
the bottom Vce plane and the top side
ground. The capacitor is as thin or thinner
than the PC board thickness and has insulation around its side to isolate Vee and ground.
The square hole is for the SO package which
is put in upside down through the bottom of
the board so that the leads are kept in
~
,
Both of the evaluation boards that will be
discussed next do not have input and output
capacitors because it is assumed the user will
use AC coupled test systems. Chip or foil
capacitors can easily be inserted between the
part and connector if the board trace is
removed.
The evaluation board layout shown in Figure
17 produces excellent results. The board is to
scale and is for the SO package but can be
used for the EC package as well. Both top
and bottom are copper clad and the ground
planes are bonded together through SOn
SMA cable connectors. These are solder
mounted on the sides of the board so that the
signal traces line up straight to the connector
signal pins.
r:
Vee PLANE
OUTPUT
PLANE
INPUT
GNDPLANE
SO PACKAGE
HOLE BACKSIDE
SO PACKAGE
HOLE TOPSIDE
BOTTOM
TOP
GND FlANGE
SMA CONNECTOR
Figure 17. BC Board Layout for NE/SA/SES20S Evaluation
11-84
Signetics Linear Products
Product Specification
Wide-band High-Frequency Amplifier
position for soldering. Both holes are just
slightly larger than the capacitor and IC to
provide for a tight fit.
presented in Figure 17, but makes use of 75n
female N-type connectors. The board is
mounted in a nickel plated box' that is used
to support the N-type connectors. This is an
excellent way to test the part for cable TV
applications. Again, the board should be tested in a system with 75n input and output
impedance for correct operation.
This board should be tested in a system with
50n input and output impedance for correct
operation.
7sn
NEjSAjSE5205
EVALUATION BOARD
'"The box and connectors are available as a "MOO-
PACK SYSTEM" from the ANZAC division of
Another evaluation board is shown in Figure
18. This system uses the same PC board as
ADAMS-RUSSELL CO .. INC .. 80 Cambridge Street.
Burlington. MA 01803.
SCATTERING PARAMETERS
The primary specifications for the NE/SAI
SE5205 are listed as S-parameters. S-parameters are measurements of incident and reflected currents and voltages between the
source, amplifier and load as well as transmission losses. The parameters for a two-port
network are defined in Figure 19.
FEEDTHRU
0.469
MODEL 7014
11I
(11.9)!
1.084
(27.5)
701 .., (BNC)
701 ..2 (THC)
701 ..3 (TYPE N)
7111 .... (SMA)
0.750
TYP
(1.6)
0.290 (7.4) TYP
Oo984L-...J
(24.9)
(19_1)
Figure 18_ 7Sn N-Type Connector System
'"I
s"
a
..
I~
s"
Figure 19a. Two·Port Network Defined
February 12, 1987
0.200 (5.1) TYP
[Of
D.3:.iCD.062
(9.5)
l 1£
r-
11-85
•
Signetics Linear Products
Product Specification
NEjSAjSES20S
Wide-band High-Frequency Amplifier
S" -
INPUT RETURN LOSS
S21 -
POWER REFLECTED
FROM INPUT PORT
S21 "VTRANSDUCER POWER GAIN
POWER AVAILABLE FROM
GENERATOR AT INPUT PORT
S'2 -
Actual S-parameter measurements using an
HP network analyzer (model 8505A) and an
HP S-parameter tester (models 8503A1B) are
shown in Figure 20. These were obtained with
the device mounted in a PC board as described in Figures 17 and 18.
FORWARD TRANSMISSION LOSS
OR INSERTION GAIN
S22 -
OUTPUT RETURN LOSS
For 50n system measurements, SMA connectors were used. The 75n data was obtained using N-connectors.
POWER REFLECTED
FROM OUTPUT PORT
REVERSE TRANSMISSION LOSS
OR ISOLATION
POWER AVAILABLE FROM
GENERATOR AT OUTPUT PORT
REVERSE TRANSDUCER
POWER GAIN
Values for the figures below are measured
and specified in the data sheet to ease
adaptation and comparison of the NE/SAI
SE5205 to other high frequency amplifiers.
Figure 19b
7sn System
son 8ystem
25
2.
=-"-
Vee- BV
VCC~8V
'Zi'
Vee-7V=;-
2.
vCC- ~V
m
2'
;;:
VCC:=6V
YCC=5V
f-- 20=50D
15
~TA=25°C
"
Z
0
"
'"~
VCC=5V
r---
t--
I.
I.'
II
II
FREQUENCY-MHz
a. Insertion Gain vs Frequency (821)
b. Insertion Gain vs Frequency (8 21)
-I'
I
-15
"'i'
!II
Z
TA=25°C
VCC=6V -
Q -20
g
f....-
I
-2.
-3',.'
6
8 102
-15
I
zo=l son
Z
Q -20
f--'
g
f-...Y
~
I
- 2. r--
c. Isolation vs Frequency (8 12)
Zo:
6
~~
z"
2'
~~
·0
/
6 8,03
8,02
d. 812 Isolation vs Frequency
,,!II
3'
25
V
~
4'
.........
!l!'"
3.
09
~z
0:"
"1-
TA=2r C
/
FREQUENCY - MHz
4'
"'I
I",
VCC=6V
Zo:::7Si1
-3' ",
FREQUENCY-MHz
,,!II
8 102
FREQUENCY-MHz
-I'
~
Zo =750
TA =2S o C
" ,.'
8 102
"
"
"""
Vcc=~V
~
w 15
-
o~
3'
3'
Zo:
25
""I
I",
~
"0
"''''
!'oo.. OUTPUT
:~
VCC=6V
20=500
15
I - - I- OUTPUT
t'-.
~w
Wo:
0:11-"
"0.
0.1-
'NPJ,~ ':-J.r-..
TA=2r e
-- "'
~z
0:"
"1-
?:g
2.
1NPrT
VCC=6V
20=750
15
1/
X
TA=25°C
10
I.'
6
8 1()2
II
" '0'
8,03
FREQUENCY-MHz
e. Input (811) and Output (8 22) Return Loss vs
Frequency
8 102
FREQUENCY - MHz
f. Input (S11) and Output (822) Return Loss vs
Frequency
Figure 20
February 12, 1987
II
11-86
Product Specification
Signetics Linear Products
Wide-band High-Frequency Amplifier
The most important parameter is S2,. It is
defined as the square root of the power gain,
and, in decibels, is equal to voltage gain as
shown below:
V,N2
0-
P'N=-Zo
OUTPUT RETURN LOSS = S22dB
S22dB = 20 Log I S22 I
)NPUT VSWR =
2
VOUT
POUT=-['-0
Zo
Zo
0-
to 1dB slope. The second and third order
products lie below the fundamentals and
exhibit a 2:1 and 3:1 slope, respectively.
INPUT RETURN LOSS = S"dB
S11dB = 20 Log I S111
Zo = Z,N = ZOUT for the NE/SA/SE5205
NE/SAI Ln
SE5205 I ~
NE/SA/SE5205
11 +s,,1
-I--I";; 1.5
I-S"
OUTPUT VSWR =
VO UT 2
POUT
VOUT 2
. --=--=--=P,
.. P'N
V,N 2
V,N 2
z;;-
The intercept point for either product is the
intersection of the extensions of the product
curve with the fundamental output.
11 + S221
-I--I";; 1.5
I-S22
1dB GAIN COMPRESSION AND
SATURATED OUTPUT POWER
The 1dB gain compression is a measurement
of the output power level where the smallsignal insertion gain magnitude decreases
1dB from its low power value. The decrease
is due to nonlinearities in the amplifier, an
indication of the point of transition between
small-signal operation and the large signal
mode.
Zo
P,=V, 2
P, = Insertion Power Gain
V, = Insertion Voltage Gain
Measured value for the
NE/SAlSE5205 = I s2,12 = 100
The saturated output power is a measure of
the amplifier's ability to deliver power into an
external load. It is the value of the amplifier's
output power when the input is heavily overdriven. This includes the sum of the power in
all harmonics.
In decibels:
P'(dB) = 10 Log IS2, 12 = 20dB
INTERMODULATION INTERCEPT
TESTS
V'(dB) = 20 Log S2, = 20dB
The intermodulation intercept is an expression of the low level linearity of the amplifier.
The intermodulation ratio is the difference in
dB between the fundamental output signal
level and the generated distortion product
level. The relationship between intercept and
intermodulation ratio is illustrated in Figure
22, which shows product output levels plotted
versus the level of the fundamental output for
two equal strength output signals at different
frequencies. The upper line shows the fundamental output plotted against itself with a 1dB
:. P'(dB) = V'(dB) = S2, (dB) = 20dB
Also measured on the same system are the
respective voltage standing wave ratios.
These are shown in Figure 21. The VSWR
can be seen to be below 1.5 across the entire
operational frequency range.
Relationships exist between the input and
output return losses and the voltage standing
wave ratios. These relationships are as follows:
The intercept point is determined by measuring the intermodulation ratio at a single output
level and projecting along the appropriate
product slope to the point of intersection with
the fundamental. When the intercept point is
known, the intermodulation ratio can be determined by the reverse process. The second
order IMR is equal to the difference between
the second order intercept and the fundamental output level. The third order IMR is
equal to twice the difference between the
third order intercept and the fundamental
output level. These are expressed as:
IP2 = POUT + IMR2
IP3 = POUT + IMR3/2
where POUT is the power level in dBm of each
of a pair of equal level fundamental output
signals, IP2 and IP3 are the second and third
order output intercepts in dBm, and IMR2 and
IMR3 are the second and third order intermodulation ratios in dB. The intermodulation
intercept is an indicator of intermodulation
performance only in the small signal operating range of the amplifier. Above some output
level which is below the 1dB compression
point, the active device moves into largesignal o·peration. At this point the intermodulation products no longer follow the straight
line output slopes, and the intercept description is no longer valid. It is therefore important
to measure IP2 and IP 3 at output levels well
below 1dB compression. One must be careful, however, not to select too low levels
because the test equipment may not be able
to recover the signal from the noise. For the
NE/SA/SE5205 we have chosen an output
level of -10.5dBm with fundamental frequencies of 100.000 and 100.01 MHz, respectively.
2 .•
I.'
I.'
I .•
'.8
1.7
~
~
1.6
1.3
1.7
~
1,6
;;
1.5
::
1.4
>
1.5
~;!; I.'
r:r::
=
Zo=750
I.'
I.'
1.1 -2o_50D
1.1I-- Z0=5OO
I .•
I.'
6
1102
8
I .•
I.'
8,()3
FREQUENCV-MHz
6
a_ Input VSWR vs Frequency
b. Output VSWR vs Frequency
Figure 21. Input/Output VSWR vs Frequency
February 12, 1987
8 102
FREQUENCV -MHz
11-87
•
Signetics Linear Products
Product Specification
NE/SA/SE5205
Wide-band High-Frequency Amplifier
ADDITIONAL READING ON
SCATTERING PARAMETERS
For more information regarding S-parameters, please refer to High-Frequency Amplifiers by Ralph S. Carson of the University of
Missouri, Rolla, Copyright 1985; published by
John Wiley & Sons, Inc.
"S-Parameter Techniques for Faster, More
Accurate Network Design", HP App Note 951, Richard W. Anderson, 1967, HP Journal.
"S-Parameler Design", HP App Note 154,
1972.
+30
THIRD ORDER
INTERCEPT POINT
+20
"'E
1 dB
+10 1-70MPRESSION
POINT
I
I
I
FUNDAMENTAL
RESPONSE .......
~
-10
0
-20
l:!'"w
........
...::>
-30
-40
.~
'; ~~~~E~~~~~
POINT
'7
V /.
rt
/
V-so
-60
/ II-
/
j
-40 -30
-20
I
'-
RES1PONjE
-10
Figure 22
11-88
I
3RD ORDER
0
INPUT LEVEL
dBm
February 12, 1987
1-
--2 DO DER
RESPONSE
+10 +20 T30 T40
NEjSE5539
Signetics
Ultra-High Frequency
Operational Amplifier
Product Specification
Linear Products
PIN CONFIGURATION
DESCRIPTION
FEATURES
The NE/SE5539 is a very wide bandwidth, high slew rate, monolithic operational amplifier for use in video amplifiers, RF amplifiers, and extremely high
slew rate amplifiers.
• Gain bandwidth product: 1.2GHz
at 17dB
Emitter-follower inputs provide a true
differential high input impedance device.
Proper external compensation will allow
design operation over a wide range of
closed-loop gains, both inverting and
non-inverting, to meet specific design
requirements.
•
•
•
•
Slew rate: GOO/V liS
Full power response: 48MHz
AVOL: 52dB typical
350M Hz unity gain
+ INPUT
1
-VSUPPLY
3
12 FREQUENCY
COMPENSATION
VosAdj/AvAdj 5
APPLICATIONS
•
•
•
•
D, F, N Packages
Fast pulse amplifiers
RF oscillators
Fast sample and hold
High gain video amplifiers
(BW > 20MHz)
TOP VIEW
ORDERING INFORMATION
DESCRIPTION
ORDER CODE
TEMPERATURE RANGE
o to
o to
o to
14-Pin Plastic DIP
14-Pin Plastic SO
14·Pin Cerdip
+70'C
NE5539N
+70'C
NE5539D
+70'C
NE5539F
14-Pin Plastic DIP
-55'C to + 125'C
SE5539N
14-Pin Cerdip
-55'C to + 125'C
SE5539F
ABSOLUTE MAXIMUM RATINGS'
PARAMETER
SYMBOL
RATING
UNIT
Vcc
Supply voltage
±12
V
PD
Internal power dissipation
550
mW
TSTG
Storage temperature range
-65 to + 150
'C
TJ
Max junction temperature
150
'C
TA
Operating temperature range
NE
SE
o to 70
-55 to + 125
'C
'C
300
'C
TSOLD
Lead temperature (10sec max)
•
NOTE:
1. Differential input voltage should not exceed O.25V to prevent excessive input bias current and
common-mode voltage 2.5V. These voltage limits may be exceeded if current is limited to less
than lOrnA.
October 10, 1986
11-89
853·0814 85931
Product Specification
Signetics Linear Products
NEjSE5539
Ultra-High Frequency Operational Amplifier
EQUIVALENT CIRCUIT
(12) FREOUENCY COMPo
(101
+Vcc
1-114
INVEATING INPUT
V
1+)1
r-...
NO N-INYEATINQ
K
INPUT
e--F >
"
I""'~
?-
V
.......
r---o
(8) OUTPUT
2.21<
(7)GNa
J
.......
H:::
~
(3) -Vee
5
DC ELECTRICAL CHARACTERISTICS Vcc = ± 8V, T A = 25'C, unless otherwise specified.
SE5539
SYMBOL
UNIT
Min
Vas
Input offset voltage
Va
= OV,
Rs
= 100.11
Typ
Max
Over temp
2
5
= 25'C
2
3
Over temp
0.1
3
= 25'C
0.1
1
TA
Input offset current
TA
Input bias current
CMRR
Common-mode rejection ratio
25
= 25'C
5
13
RIN
Input impedance
ROUT
Output impedance
October 10, 1986
/lVrC
2
5
/lA
nAl'C
20
10
nArC
80
dB
100
100
kn
10
10
.11
10
11-90
5
p.A
.::lls/.::lT
Over temp
2.5
0.5
6
F = 1 kHz, Rs = lOOn, VCM ± 1.7V
Max
5
Over temp
TA
Typ
mV
0.5
.::llos/.::lT
Is
Min
5
l!,vosl/lT
los
NE5539
TEST CONDITIONS
PARAMETER
70
80
70
80
70
dB
Signetics Linear Products
Product Specification
NEjSE5539
Ultra-High Frequency Operational Amplifier
DC ELECTRICAL CHARACTERISTICS (Continued) Vee=±8V, TA=2S C, unless otherwise specified.
D
SE5539
SYMBOL
PARAMETER
UNIT
Min
VOUT
Output voltage swing
RL = IS0n to GND and
470n to -Vcc
Over temp
VOUT
Output voltage swing
RL=2kn to
GND
TA = 2S D C
Icc+
Positive supply current
Icc-
Negative supply current
PSRR
Power supply rejection ratio
AVOL
Large signal voltage gain
AVOL
Large signal voltage gain
AVOL
Large signal voltage gain
NE5539
TEST CONDITIONS
Va =0, R1 =
00
Va = 0, R1 =
00
Typ
Max
Typ
+ Swing
+2.3 +2.7
-Swing
-1.7 -2.2
+ Swing
+2.3 +3.0
-Swing
-1.S -2.1
+ Swing
+2.S +3.1
-Swing
-2.0 -2.7
14
18
14
17
Over temp
11
15
TA = 25 D C
11
14
Over temp
300
1000
14
18
11
15
200
1000
47
52
57
47
52
57
TA = 25 D C
Va = +2.3V, -1.7V
RL = 150n to GND, 470n to -Vee
TA = 25 D C
Va = + 2.SV, -2.OV
RL = 2kn to GND
Over temp
46
TA = 25 D C
48
V
V
TA = 25 D C
Vo=+2.3V, -1.7V
RL=2n to GND
Max
Ii
Over temp
e..vcc = ± 1V
Min
rnA
rnA
/JVIV
dB
dB
60
53
dB
58
DC ELECTRICAL CHARACTERISTICS Vcc = ± 6V, TA = 25 C, unless otherwise specified.
D
SESS39
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Min
Vas
Input ollset voltage
los
Input ollset current
18
Input bias current
CMRR
Common-mode rejection ratio
Icc+
Positive supply current
lee-
Negative supply current
PSRR
Power supply rejection ratio
2
5
TA = 25 D C
2
3
Over temp
0.1
3
TA = 25 D C
0.1
1
Over temp
5
20
TA = 25 D C
4
10
70
85
Over temp
VOUT
Output voltage swing
TA = 2S D C
October 10, 1986
11-91
mV
IJ.A
IJ.A
dB
Over temp
11
14
TA = 25 D C
11
13
Over temp
8
11
TA = 25 D C
8
10
Over temp
300
1000
rnA
rnA
/JVIV
TA = 25 D C
RL = 150n to GND
and 390n to -Vee
Max
Over temp
VCM=±1.3V, Rs=100n
!!.vee= ±IV
Typ
+ Swing
+1.4
-Swing
-1.1
-1.7
+ Swing
+1.5
+2.0
-Swing
-1.4
-1.8
+2.0
V
•
Signetlcs Unear Products
Product Specification
NE/SE5539
Ultra-High Frequency Operational Amplifier
AC ELECTRICAL CHARACTERISTICS
VOC = ± 8V, RL = 15051 to GND & 47051 to -Voc, unless otherwise specified.
SE5539
SYMBOL
PARAMETER
UNIT
Min
BW
NE5539
TEST CONDITIONS
Typ
Max
Min
Typ
Max
Gain bandwidth product
ACL = 7, Vo = 0.1 Vp.p
1200
1200
MHz
Small-signal bandwidth
AcL = 2, RL = 150511
110
110
MHz
Is
Settling time
AcL
RL = 150511
15
15
ns
SR
Slew rate
ACL = 2, RL = 150511
600
600
V/jJS
tpD
= 2,
Propagation delay
ACL = 2, RL = 150511
7
7
ns
Full power response
ACL = 2, RL = 150511
48
48
MHz
Full power response
Av = 7, RL = 150511
20
20
MHz
Input noise voltage
Rs= 5051
4
4
nV/YHz
NOTE:
1. External compensation.
AC ELECTRICAL CHARACTERISTICS
Vcc = ± 6V, RL = 15051 to GND and 39051 to -Voc, unless otherwise specified.
SE5539
SYMBOL
PARAMETER
UNIT
TEST CONDITIONS
Min
BW
Typ
Max
Gain bandwidth product
AcL=7
700
MHz
Small-signal bandwidth
ACL = 21
120
MHz
ts
Settling time
AcL =21
23
ns
SR
Slew rate
ACL =21
330
V/jJS
Propagation delay
ACL =21
4.5
ns
Full power response
ACL =21
20
MHz
tpD
NOTE:
1. External compensation.
TYPICAL PERFORMANCE CURVES
NE5539 Open-Loop Phase
NE5539 Open-Loop Gain
dBH-HttHtttllHrtH1tH1l!I-++1I-1lHHtIlI
: mIItl+J:ltm~ttW
rJ'
....
goo
4OH-HttHttHtF'l~1tH1l!I-++1I-1lHHtIlI
3OH-tttttttttllH-tfI'!Iot!1l!I-++1I-1lH-+I!ll
20
,80"
-
H-tttltttlfttl-HtHttIltll:+tItl!-HtIH
'0 H-tttltttlfttl-HtHttItlll-"N::Itl!-HtIH
vrJ'
'M'"
October 10, 1986
,......
,....
0P051aos
11-92
l00M"z
,.'"
Product Specification
Signetics Linear Products
NEjSE5539
Ultra-High Frequency Operational Amplifier
TYPICAL PERFORMANCE CURVES (Continued)
Power Bandwidth (SE)
Power Bandwidth (NE)
,
....m1A
\
3dBB.W.
r--
3
'\'0.
\
GAIN (-2)
::::8V
vec"
AI. "" 211:11
,
"'_
,
~
3d8 B.W.
,-
"
Vee'" ::::511
RL
= 1500
i""'--
G.... (-2)
\
lOUHz
FREQUENCY IN CYCLES PER SECOND
3(lO....
FREQUENCY'" CYCl.ES PEA SECOND
SE5539 Open-Loop Gain vs Frequency
Power Bandwidth
3.04V
"""""'"
~,
I
"'
~
<0
~------------+---~~~----~----~
I
\.
~
VCc z
::::
-
5V
\.
r\.
GAIN (-7)
RL'" 150!1
"-
Rt. = nell
....
r....L---------------~--------------~--~~
"
FAEQ4.JEHCY IN CYCL£S PER SECOND
Gain Bandwidth Product vs Frequency
SE5539 Open-Loop Phase vs Frequency
,
Av
I
= Xl0
3dBB
AV
X7.S
I
J
TH
I
~
~
3dB~IDTH
" ....
",....
FREQUENCY IN CYCLES PER SECOND
I
" ....
FREQUENCY IN CYCl.ES PER SECOND
NOTE
Indicate. typical
dlatribuUon -65-C
October 10, 1986
~
TA .:s; 12S·C
11-93
Vee:: ::::6V
RL = 150\1
"'" WJ".
II
Signetlcs Linear Products
Product Specification
NE/SE5539
Ultra-High Frequency Operational Amplifier
CIRCUIT LAYOUT
CONSIDERATIONS
As may be expected for an ultra-high frequency, wide gain bandwidth amplifier, the physi-
example utilizing a 26dB non-inverting amp is
shown in Figure 1.
cal circuit layout is extremely critical. Breadboarding is not recommended. A doublesided copper-clad printed cirucit board will
result in more favorable system operation. An
RF
OPTIONAL
OFFSET
ADJ.
+v o--:-,N';---o-v
Rs
R4
7'
R31
[ 1
~----t-~~~---ov~ ~5~J
R,
7'
T0087-40S
NOTES:
R, - 75n 5% CARBON
R2 - 75n 5% CARBON
R, - 75n 5% CARBON
R4 - 36k 5% CARBON
Rs - 20k TRIMPOT (CERMET]
RF - 1.5k (2BdB GAIN)
R, - 470n 5% CARBON
TOp Plane Copperl
(Component Side)
RFC 3T # 26 BUSSWIRE ON
FERROXCUBE VK 200 09/3B CORE
BYPASS CAPACITORS
1nF CERAMIC
(MEPCO OR EQUIV.)
Component Side
(Component Layout)
-v
§
••
0,0
\Ii 00.
00.
10
C.
§
NE 5539
w/comp.
Jb
~
+v
Q:Io
0
.0
•
0
0
•
Vo
DfOSltOS
NOTES:
(X) indicates ground connection to top plane.
-Rs is on bottom side.
NOTE:
Bond edges of top and bottom ground plane copper.
Figure 1. 28dB Non-Inverting Amp Sample PC Layout
October 10, 1966
11-94
Bottom Plane
Copperl
Signetics Linear Products
Product Specification
Ultra-High Frequency Operational Amplifier
NE5539 COLOR VIDEO
AMPLIFIER
The NE5539 wideband operational amplifier
is easily adapted for use as a color video
amplifier. A typical circuit is shown in Figure 2
along with vector-scope 1 photographs showing the amplifier differential gain and phase
response to a standard five-step modulated
staircase linearity signal (Figures 3, 4 and 5).
As can be seen in Figure 4, the gain varies
less than 0.5% from the bottom to the top of
the staircase. The maximum differential
phase shown in Figure 5 is approximately
+0.1°.
NEjSE5539
750
75
+V
~
".F
1 _ _ 6dBLOSS-1
75
V..
75
470
The amplifier circuit was optimized for a 75,n
input and output termination impedance with
a gain of approximately 10 (20dB).
-V
NOTE:
1. The input signal was 200mV and the output 2V.
Vee was ±8V.
Figure 2_ NE5539 Video Amplifier
Figure 3. Input Signal
Figure 4. Differential Gain
< 0_5%
NOTE:
1. Instruments used for these measurements were Tektronix, 146 NTSC test signal generator, 520A NTSC vectorscope, and 1480 waveform monitor.
October 10, 1986
11-95
•
Signetics Linear Products
Product Specification
NE/SE5539
Ultra-High Frequency Operational Amplifier
PHASE
ERROR
Figure 5. Differential Phase
+ 0.10
APPLICATIONS
+8V
Z,N-SOO ~--'>M-~--!.f
470
118
87
1K
2K
-1.5pF
Figure 6. Non-Inverting Follower
+8V
Figure 7. Inverting Follower
October 10, 1986
11-96
AN140
SigneHcs
Compensation Techniques for
Use With the NEjSE5539
Application Note
Linear Products
NE5539 DESCRIPTION
The Signetics NE/SE5539 ultra-high frequency operational amplifier is one of the fastest
monolithic amplifiers made today. With a unity
gain bandwidth of 350MHz and a slew rate of
600V/ MS, it is second to none. Therefore, it is
understandable that to attain this speed,
standard internal compensation would have
to be left out of its design. As a consequence,
the op amp is not unconditionally stable for all
closed-loop gains and must be externally
compensated for gains below 17dB. Properly
done, compensation need not limit slew rate.
The following will explain how to use the
methods available with the NE/SE5539.
LEAD AND LAG-LEAD
COMPENSATION
A useful method for compensating the device
for closed-loop gains below seven is to use
lag-lead and lead networks as shown in
Figure 1. The lead network is primarily concerned with compensating for loss of phase
margin caused by distributed board capacitance and input capacitance, while lag-lead is
mainly for optimizing transient response.
Lead compensation modifies the feedback
network and adds a zero to the overall
transfer function. This increases the phase,
but does not greatly change the gain magnitude. This zero improves the phase margin.
To determine components, it can be shown
that the optimal conditions for amplifier stability occur when:
However, when the stability criteria is obtained, it should be noted that the actual
bandwidth of the closed-loop amplifier will be
reduced. Based on using a double-sided copper-clad printed circuit board with a distributed capacitance of 3.5pF and a unity gain
configuration, CLEAD would be 3.5pF. Another
way of stating the relationship between the
distributed capacitance closed-loop gain and
the lead compensation capacitor is:
When bandwidth is of primary concern, the
lead compensation will usually be adequate.
For closed-loop gains less than seven, laglead compensation is necessary for stability.
If transient response is also a factor in design,
a lag-lead compensation network may be
necessary (Reference Figure 1). For practical
applications, the following equations can be
used to determine proper lag-lead components:
r--II--
.:;:.
V,N
(7)
where
(8)
therefore,
(9)
and
(10)
LAG-LEAD
COMPENSATION
WILL CONTROL
GAIN PEAKING
GAIN
(5)
Using the above equation will insure a closedloop gain of seven above the network break
70MHz
a. Closed-Loop Inverting Gain of
Seven Gain-Phase Response
(Uncompensated)
CF
COIST
JLEAD
r--II--
Rl
o·
-80
•
.......COMPENSATED
-120
VOUT
VOUT
~UNCOMPENSATED~
-200
V,N
INVERTING
."
-40
RF
-160
LAG LEAD RL
'::'
1I'(GBW)
WLAG = - - 5 - Rad/Sec
Therefore,
.:;:.
r
(6)
(4)
CLEAD
RF
211'(GBW)
WLAG '" --1-0- Rad/Sec
(2)
(1)
CDrSl
frequency. CLAG may now be approximated
using:
-240
NON·INVERTING
7~
-260
1MHz
10MHz
100MHz
NOTES:
CL=Cl.A(3
RL"" RLAG
February 1987
b_ Open-Loop Phase
Figure 1_ Standard Lag-Lead Compensation
11-97
Figure 2
lGHz
•
Signetics Linear Products
Application Note
Compensation Techniques for Use With the NE/SE5539
This method adds a pole and zero to the
transfer function of the device, causing the
actual open-loop gain and phase curve to be
reshaped, thus creating a progressive improvement above the critical frequency where
phase changes rapidly. (Near 70MHz, see
Figures 2a and 2b.) But also, the lag-lead
network can be adjusted to optimize gain
peaking for transient responses. Therefore,
rise time, overshoot, and settling time can be
changed for various closed-loop gains. The
result of using this technique is shown for a
pulse amplifier in Figure 3.
SMALL SIGNAL RESPONSE
OUTPUT
200mV
p.p
l00mv/DIV
INPUT
100mV
lOnalDIV
p.p
AN140
Figure 3. Compensated Pulse Response
cc
VOUT
VOUT
VI. o------
o·
~
..
.,w
:x:
..........
OdB
.......
---
r-
.........
180 0
='
270 350
!(MHz)
-l~
Co
Rc
RI
ALTERNATE
LOWERS OFFSET
a. Open-Loop Gain - No
Compensation (Computer
Simulation)
a. Pin 12 Compensation Showing Internal Connections - Inverting
----1"--
i
11
\
I
1\
\.
\I
1\
:[\1
INPUT
I
I
5nslDIV
OUTPUT
b. Closed-Loop Non-Inverting
Response - No Compensation
(Computer SimulatlonOscillation Is Evident)
'Figure 11
To indicate the accuracy of this system, the
actual open-loop gain is compared to the
computer plots in Figures 14 and 15. The real
payoff for this system is that once a credible
simulation is achieved, any outside circuit can
be modeled around the op amp. This would
be used to check for feasibility before breadboarding in the lab. The internal circuit can be
treated like a black box and the outside circuit
program altered to whatever application the
user would like to examine.
February 19B7
-l~
RI
Co
Rc
ALTERNATE
LOWERS OFFSET
b. Pin 12 Compensation Showing Internal Connections - Non-Inverting
Figure 12
11-101
Application Note
Signetics linear Products
AN140
Compensation Techniques for Use With the NEjSE5539
46
"
..........
1-0.
-
I"...
..........
INPUT
is
"
I
140' "
-
44
...... f...
>
OdB
.....
'"
OUTPUT
..........
OdB
"
"'
""-
92'
,---
,
250350
150
5ns/DIV
I (MHz)
a. Open-Loop Pin 12 CompensationRc = 200n, Cc = 1pF,
(Computer Simulation)
b. Closed-Loop Non-Inverting Pulse
Response - Rc 200n, Cc 1pF,
Av = 3 (Computer
Simulallon - Underdamped)
=
=
c. Open-Loop Pin 12 CompensationRc 200n, Cc 2pF (Computer
Simulallon)
=
I
43
OUTPUT
>
~E
\
\
li!
=
O~TP~T
I"...
1
..........
I PUT
.......... OdB
I.'>
73'
I---
>
is
;;
'\
E
I"
\1\
1\
INPUT
li!
I
":,\
~
7S
5ns/OlV
350
f (MHz)
d. Closed-Loop Non-Inverting Pulse
Response - Rc 200n, Cc 2pF, Av 3
(Computer Simulation - Critically-Damped)
=
350
'(MHz)
=
=
e. Open-Loop Pin 12 CompensallonRc 200n, Cc 3pF,
(Computer Simulation)
=
=
5nsJDIV
f. Closed-Loop Non-Inverting Pulse
Response - Rc 200n, Cc 3pF, Av 3
(Computer Simulation - Overdamped)
=
=
=
Figure 13
1. J. Millman and C. C. Halkias: Integrated
Electronics: Analog and Digital Circuits and
Systems, McGraw-Hili Book Company, New
York, 1972.
120
100
80
60
40
-
a;-
55
s
2. A. Vladimirescu, Kaihe Zhang, A. R. Newton, D. O. Peterson, A. Sanquiovanni-Vincenlelli: "Spice Version 2G," University of California, Berkeley, California, August 10, 1981.
>
'"
""'-
20
.......
I (MHz)
-20
1MHz
10MHz
100MHz 350 1GHz
Figure 14. Actual Open-Loop Gain
Measured in Lab
February 1987
Figure 15. Computer-Generated
Open-Loop Gain
11-102
3. Signetics: Analog Data Manual 1983,
Signetics Corporation, Sunnyvale, California
1983.
NE5592
Signetics
Video Amplifier
Product Specification
Linear Products
DESCRIPTION
FEATURES
The NE5592 is a dual monolithic, twostage, differential output, wideband video amplifier. It offers a fixed gain of 400
without external components and an
adjustable gain from 400 to 0 with one
external resistor. The input stage has
been designed so that with the addition
of a few external reactive elements between the gain select terminals, the
circuit can function as a high-pass, lowpass, or band-pass filter. This feature
makes the circuit ideal for use as a video
or pulse amplifier in communications,
magnetic memories, display, video recorder systems, and floppy disk head
amplifiers.
•
•
•
•
PIN CONFIGURATION
120MHz bandwidth
Adjustable gain from 0 to 400
Adjustable pass band
No frequency compensation
required
• Wave shaping with minimal
external components
D, N Packages
APPLICATIONS
• Floppy disk head amplifier
• Video amplifier
• Pulse amplifier in
communications
• Magnetic memory
• Video recorder systems
TOP VIEW
ORDERING INFORMATION
DESCRIPTION
14-Pin Plastic DIP
14-Pin SO package
TEMPERATURE RANGE
o to
o to
ORDER CODE
70°C
NE5592N
70°C
NE5592D
EQUIVALENT CIRCUIT
r---~-----'------~--~------~-----?--~+v
+----+-,,==I-I------+----.....I/VI~..,..--_t---o
•
OUTPUT 1
INPUT 1
OUTPUT 2
G
0"
L-__~----~------~----------~--~--~
October 10, 1986
11-103
-v
853-0888 85933
Product Specification
Signetics Unear Products
NE5592
Video Amplifier
ABSOLUTE MAXIMUM RATINGS TA = 25·C, unless otherwise specified.
RATING
UNIT
Vee
Supply voltage
±8
V
VIN
Differential input voltage
±5
V
VCM
Common mode Input voltage
±6
V
lOUT
Output current
10
mA
TA
Operating temperature range
NE5592
o to +70
·C
TSTG
Storage temperature range
Po
Power dissipation
SYMBOL
PARAMETER
-65 to +150
·C
500
mW
DC ELECTRICAL CHARACTERISTICS TA = + 25·C, Vss = ± 6V, VCM = 0, unless otherwise specified. Recommended
operating supply voltage is Vs = ± 6.0V, and gain select pins are connected together.
LIMITS
PARAMETER
SYMBOL
Differential voltage gain
UNITS
TEST CONDITIONS
RL = 2kn. VOUT = 3Vp.p
i
Min
Typ
Max
400
480
600
3
14
Input resistance
CIN
Input capacitance
2.5
los
Input offset current
0.3
3
IBIAS
Input bias current
5
20
Input noise voltage
VIN
BW 1kHz to 10MHz
CMRR
Common-mode rejection ratio
PSRR
Supply voltage rejection ratio
Channel separation
Vos
Output offset voltage
gain select pins open
VCM
Output common-mode voltage
VOUT
Output differential voltage swing
ROUT
Output resistance
Icc
Power supply current
(total for both sides)
October 10, 1986
pF
dB
dB
dB
V
60
93
87
avs= ± 0.5V
50
85
VOUT = lVp_p; f = 100kHz
(output referenced) RL = 1k!2
65
RL =
RL =
11-104
00
dB
1.5
0.75
2.4
3.1
3.4
3.0
4.0
V
20
!2
00
00
75
0.5
0.25
00
RL =2k!2
p.A
nV/YHz
VCM ± lV, f < 100kHz
VCM ± lV, f = 5MHz
RL =
RL =
p.A
4
±1.0
Input voltage range
VIV
k!2
RIN
35
44
V
V
V
rnA
Signetics Linear Products
Product Specification
NE5592
Video Amplifier
DC ELECTRICAL CHARACTERISTICS
Vss = ± 6V, VCM = 0, O°C";;; TA";;; 70°C, unless otherwise specified. Recommended
operating supply voltage is Vs = ± 6.0V, and gain select pins are connected together.
LIMITS
PARAMETER
SYMBOL
Differential voltage gain
UNITS
TEST CONDITIONS
RL = 2kn, VOUT = 3Vp.p
Min
Typ
Max
350
430
600
1
11
VIV
RIN
Input resistance
los
Input offset current
5
p.A
ISlAS
Input bias current
30
p.A
VIN
Input voltage range
CMRR
Common-mode rejection ratio
PSRR
Supply voltage rejection ratio
Channel separation
Vos
Output offset voltage
gain select pins connected
together
gain select pins open
VOUT
Output differential voltage swing
Icc
Power supply current
(total for both sides)
AC ELECTRICAL CHARACTERISTICS
kn
± 1.0
V
VCM ± 1V, f < 100kHz
Rs=
55
dB
!:J.Vs = ± 0.5V
50
dB
Your = 1Vp_p; f = 100kHz
(output referenced) RL = 1kn
RL =
00
RL =
00
RL =2kn
RL =
75
dB
1.5
V
1.0
V
2.8
V
47
00
rnA
TA = + 25°C, Vss = ± 6V, VCM = 0, unless otherwise specified. Recommended
operating supply voltage Vs = ± 6.0V. Gain select pins connected together.
LIMITS
PARAMETER
SYMBOL
TEST CONDITIONS
UNITS
Min
BW
Bandwidth
tR
Rise time
tpD
Propagation delay
October 10, 1986
VOUT = 1Vp_p
Typ
Max
25
20
MHz
12
ns
15
VOUT = lVp_p
11·105
7.5
ns
•
Signetics Linear Products
Product Specification
Video Amplifier
NE5592
TYPICAL PERFORMANCE CHARACTERISTICS
Common-Mode Rejection Ratio
as a Function of Frequency
Output Voltage Swing as a
Function of Frequency
Channel Separation as a
Function of Frequency
1100
:
~
i!
RL I:: 1 k!l:
~
"
40
~
lis = •
VIN = 2V pop
0
106
105
V
1
I.·
107
FREQUENCY - Hz
o
I.'
Differential Overdrive
Recovery Time
¥! ~ i56:f-
w 40
>
a:
w
>
~
35
,
w
a: 20
w
15
Q
10
a:
w
>
r-~L J ,~
1.6
~
-- -- -- -- -,,;;V
o
0
80
120
160
=
>
:t6V
- --1--1~s ~ ±13V
-- -
II'
- -- -- -- -- -- --
-15-10-5 0
40
1.6
1.4
I
0.4
S 0.2 -
r- i-'"
Pulse Response as a
Function of Temperature
I
Vs = ±8V
Vs
~
=
g
0.4
0.2
o
:t6V
RL. = lkO
I
TA = DOC
1
...
~
Vs
1. 2
0.8
0.6
~
r-
r,
-0.2
-0.4
-15-10-5
5 10 15 20 25 30 35
TIME· ns
200
20
10
1S
V· =VR(VOlTS)
10·
I
::: 1.2
~ 0.8
... 0.6
./
I
1.4 rTA = 25°C
~
30
0
u 25
105
10 15
107
FREQUENCY· Hz
Pulse Response as a
Function of Supply Voltage
50
~ 45
,.;:
-V
Vs = :t6Y
TA .,. 25"C
20
....
'0
~
30
i!
osc TO asc
15
7.
!:
I
,. I.
~
20
Vs = ±6V
RL = lkO
T. = 25'C
0
I
T.
I
T.
=2S"C_
I
=I7OOC-
I-++L
5 10 15 20 25 30 35
TIME - ns
DIFFERENTIAL INPUT VOLTAGE· mV
Voltage Gain as a
Function of Temperature
1. S
ID
'?
!i
"~
l\ =,~~'=
•
o.
Vs
RL
!5 •s
TA = O'C
-T. = 25'C
~ 2D
-ITAI
!:i
-0.
~ -1.2
I
o
10
20 30 40 50
TEMPERATURE: '"C
60
70
.....
I"l
"
!i30
w
-0.
= ±6V
= 11eO
~ 50
~ 40
O. 4
-1.6
60
v.' • .'sv-
1. 2
Voltage Gain as a
Function of Supply Voltage
Gain vs Frequency as a
Function of Temperature
10
10'
"""~
1
~
0
w- 1
~
itF
~
>
1111
I 1111
10'
107
108
FREQUENCY· Hz
F = 100kHz
T. = 25'C
10'
",
"""
-2
'/
-3
!.I
-4
-5
-6
3
SUPPLY VOLTAGE· V
October 10, 1986
11-106
Signetics Linear Products
Product Specification
Video Amplifier
NE5592
TYPICAL PERFORMANCE CHARACTERISTICS
...
ID
z
:c
1111 I
TA = 250C
At. =,Idl
Vs = ±IV
50
Vs = ±6V
40
N
Vs = uv
"w
"~ 30
RL
~
!!;
~,
l'-
0
> 20
3D
60
;j
90
120
tl
'50
'0'
107
10'
~
'"
:::0
U
>-
it
"
"
VS:::I :t:6V
Vs = ±3V
I
1111
,
"
10-1
10'
'0
FREQUENCY· Hz
Supply Current as a
Function of Supply Voltage
50
Vs
TA
= ±6Y
....
I-""
u 20
ii
TA = 25"C
" "
;;#
V
:::0
!5
In
Output Voltage Swing and Sink
Current as a Function of Supply
Voltage
= 25'C
i!i30
r-..
33
32
107
101S
=- 25-':
= :t1lV
FREQUENCY· Hz
-
...
!z34
w
Vs
'0
,
'0'
Supply Current as a
Function of Temperature
35
TAo
"
Vs = :t8Y
180
...~ 2'0
10&
1kO
::I
1'\
240
'0
....
TAo = 25-':
D
~
Voltage Gain as a
Function of RADJ
Phase vs Frequency as a
Function of Supply Voltage
Gain vs Frequency as a
Function of Supply Voltage
60
(Continued)
;'
IL
~
AI!
-
~
,
10
0 1 0 2 0 3 0 4 0 506070
TEMPERATURE - "C
7
o
3
•
5
6
7
SUPPLY VOLTAG~· ±V
SUPPLY VOLTAGE. ±V
OP187OO5
Output Voltage Swing as a
Function of Load Resistance
0'117208
Input Resistance as a
Function of Temperature
Input Noise Voltage as a
Function of Frequency
25
J..
eo
i 3
..:!I
..~~
Vs = :t:6V
TA ... 2SOC
GAIN'
Vs = ±6V
,..
= 1000
V
J
1
'0'
vs. :t:eY
V
II
2
o
TA • 25-C
0
'0'
LOAD RESISTANCE· OHMS
,..
'0
"
V
,
0'0203040
50
TEMPERATURE· 'C
6070
'0' ,.. ,.. ,..
FREQUENCY· H2
OP1'7111S
October 10, 1986
11-107
•
Signetics Linear Products
Product Specification
NE5592
Video Amplifier
TEST CIRCUITS TA = 25°C, unless otherwise specified.
O.2pF
O.2.uF
.ln~~"F
11
51
Octobsr 10, 1966
51
O.2pF
-t-----,
51
'
11-108
51
R.dj
lK
lK
NEjSE592
Signetics
Video Amplifier
Product Specification
Linear Products
DESCRIPTION
FEATURES
The NE/SE592 is a monolithic, twostage, differential output, wide band video amplifier. It offers fixed gains of 100
and 400 without external components
and adjustable gains from 400 to 0 with
one external resistor. The input stage
has been designed so that with the
addition of a few external reactive elements between the gain select terminals, the circuit can function as a highpass, low-pass, or band-pass filter. This
feature makes the circuit ideal for use as
a video or pulse amplifier in communications, magnetic memories, display, video
recorder systems, and floppy disk head
amplifiers. Now available in an a-pin
version with fixed gain of 400 without
external components and adjustable
gain from 400 to 0 with one external
resistor.
•
•
•
•
PIN CONFIGURATIONS
120MHz bandwidth
Adjustable gains from 0 to 400
Adjustable pass band
No frequency compensation
required
• Wave shaping with minimal
external components
D, F, N Packages
INPUT 2
INPUT 1
1
He
G2A GAIN
SELECT
G1A GAIN
SELECT
APPLICATIONS
V·
• Floppy disk head amplifier
• Video amplifier
• Pulse amplifier in
communications
• Magnetic memory
• Video recorder systems
OUTPUT 2
7
TOP VIEW
H Package"
G2A GAIN SELECT
INPUT 2
G2B GAIN
EQUIVALENT CIRCUIT
SELECT
r----,------~-----,----~------~r_----.___o+v
vNOTES:
Pin 5 connected to case.
*Metal cans (H) not recommended for new designs.
008
D, F, N, Packages
~--~--~~f-~------+-----~~~~----4---o0UTPUTl
INPUT 1
OUTPUT 2
INPUT 2
G$,=Etd~
v-
2
7
INPUT 1
~~tE~~N
3
6
V+
OUTPUT 2 4
5
OUTPUT 1
TOP VIEW
~---+-----4--------~-----------4----+--o-V
November 6, 1986
11-109
853-0911 86387
•
Product Specification
Signetics Linear Products
NE/SE592
Video Amplifier
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
o to
o to
14-Pin Plastic DIP
14-Pin Cerdip
14-Pin Cerdip
ORDER CODE
+70'C
NE592N14
+70'C
NE592F14
SE592F14
-55'C to +125'C
o to
o to
14-Pin SO
8-Pin Plastic Dip
8-Pin Cerdip
+70'C
NE592D14
+70'C
NE592N8
SE592F8
-55'C to + 125'C
o to
o to
8-Pin SO
10-Lead Metal Can
10-Lead Metal Can
+70'C
NE592D8
+70'C
NE592H
-55'C to + 125'C
SE592H
NOTE:
Also N8, N14, 08 and 014 package parts available in "High" gain version by adding "H" before package
designation, as: NE592H08.
ABSOLUTE MAXIMUM RATINGS TA = + 25'C, unless otherwise specified,
SYMBOL
RATING
UNIT
Vcc
Supply voltage
PARAMETER
±8
V
Y,N
Differential input voltage
±5
V
VCM
Common-mode input voltage
±6
V
lOUT
Output current
10
mA
TA
Operating temperature range
SE592
NE592
-55 to + 125
o to +70
'C
'C
TSTG
Storage temperature range
-65 to + 150
'C
Po
Power dissipation
500
mW
November 6, 1986
11·110
Signetlcs Linear Products
Product Specification
NEjSE592
Video Amplifier
DC ELECTRICAL CHARACTERISTICS T A = + 25'C, Vss = ± 6V, VCM = 0, unless otherwise specified. Recommended
operating supply voltages Vs = ± 6.0V. All specifications apply to both standard and
high gain parts unless noted differently.
NE592
SYMBOL
AVOL
PARAMETER
Differential voltage gain,
standard part
Gain 11
Gain 22,4
RL = 2k.l1, VO UT = 3Vp.p
High gain part
RIN
Input resistance
Gain 11
Gain 22• 4
GIN
Input capacitance2
los
Input offset current
ISlAS
Input bias current
VNOISE
Input noise voltage
SE592
TEST CONDITIONS
UNIT
Min
Typ
Max
Min
Typ
Max
250
80
400
100
600
120
300
90
400
100
500
110
400
500
600
10
4.0
30
Gain 24
VIV
20
2.0
BW 1kHz to 10MHz
4.0
30
k.l1
k.l1
2.0
pF
0.4
5.0
0.4
3.0
9.0
30
9.0
20
12
12
p.A
p.A
/lVRMS
VIN
Input voltage range
GMRR
Gammon-mode rejection ratio
Gain 24
Gain 24
VCM± 1V, f < 100kHz
VCM± 1V, f = 5MHz
60
86
60
60
86
60
dB
dB
PSRR
Supply voltage rejection ratio
Gain 24
f!.Vs=±0.5V
50
70
50
70
dB
VOS
Output
Gain
Gain
Gain
offset voltage
1
24
33
VCM
Output common-mode voltage
VOUT
Output voltage swing
differential
ROUT
Output resistance
Icc
Power supply current
± 1.0
VIV
VIV
RL =
RL =
RL =
RL =
0.35
1.5
1.5
0.75
2.4
2.9
3.4
3.0
4.0
00
00
00
00
RL=2k.l1
20
RL =
00
NOTES:
1. Gain select Pins G 1A and G1B connected together.
2. Gain select Pins G2A and G28 connected together.
3. All gain select pins open.
4. Applies to 10- and 14-pin versions only.
November 6, 1986
±1.0
11-111
18
V
0.35
1.5
1.0
0.75
2.4
2.9
3.4
3.0
4.0
18
V
V
.11
20
24
V
V
V
24
mA
Product Specification
Signetics Linear Products
Video Amplifier
NE/SE592
DC ELECTRICAL CHARACTERISTICS Vss = ±6V, VCM = 0, O'C":TA ":70'C for NE592; -55'C":TA": 125'C for SE592,
unless otherwise specified. Recommended operating supply voltages Vs = ± 6.0V. All
specifications apply to both standard and high gain parts unless noted differently.
NE592
SYMBOL
PARAMETER
UNIT
Min
AVOL
Differential voltage gain,
standard part
Gain l'
Gain 22,4
SE592
TEST CONDITIONS
RL = 2kn, VOUT = 3Vp.p
Typ
250
80
Min
600
120
200
80
Typ
Max
VIV
400
RIN
Input resistance
Gain 2 2,4
8.0
los
Input offset current
6.0
5.0
ISlAS
Input bias current
40
40
VIN
Input voltage range
Common-mode rejection ratio
Gain 24
PSRR
Supply voltage rejection ratio
Gain 24
Vos
Output
Gain
Gain
Gain
offset voltage
1
24
33
VOUT
Output voltage swing
differential
Icc
Power supply current
< 100kHz
VCM± lV, f
.
1.0
~
"~
0.8
~
0.'
0
0.'
:il
J.
w '.0
"""~
3.0
S
'.0
~
0
,
1.0
0
.
1
"
I'
1.'
50
1.0
V
V
0.'
0 0
-
20
0.4
60
••
DIFFERENTIAL INPUT VOLTAGE-mY
Voltage Gain as a
Function of Temperature
-5
0
20
'"
25
35
=
TA =
RL:: lkO
1
oa elz
0.'
T_A( 2S"C
li
0.6
TA" 70 0
- e-
e
0.4
0.'
5
15
GAIN 2
Vs
:t6Y
"
-0.2
10
10
TlME-n.
1
1.0
= :t3V
I
-0.4_ 15
.
0
1.'
~
80 100 120 140 160 180 200
-.
1.4
-0.2
40
-0.4
-15 -10
II
1.8
I
V
V
Vs =
Vs
0.6
V
I-
JI
Pulse Response as a
Function of Temperature
VS:: %8\1
20
10
500 1000
I ~:I~ :S"C
I At. =lkn
1.4
'"
~~~I
-0.2
50 100
1.'
Vs = 16\1
TA=ZS"C
GAIN 2
V
s
Pulse Response as a
Function of Supply Voltage
70
=lK
~V
~ 0.'
FREQUENCY-MHz
Differential Overdrive
Recovery Time
40
Al
1.'
I
~
~! ~ 2:t5~~
1.'
>'t.
FREQUENCY-Hz
60
1.'
= :t8Y
T,,=~C
'.0 t--+lI-H.....,f-H-tt-i-A L=1klt
Vs
y "1--I:itH-t-ttH-ttH-t~:: ~~~
o .. H-ttH~..tI-H-ttH-t+l-H-t
Pulse Response
7.0 ....--T1rTl---,r-rTTT-,-........,.,.-,
100 r-rTTr-r-rTTr-r--rTT1""TG
""""N'"""--'
10
1S
TIME-ns
20
2S
30
3S
-0.4
15
10
0
5
5
10
15
25
~
~
Voltage Gain as a
Function of Supply Voltage
Gain vs Frequency as a
Function of Temperature
1.10
Vs
=
:1:6\1
Ys'" t6Y
1.08
50 t--t-l-tt-i-I-tH--t-l~~I~ ~k II
1.06
1.04
-"-
1.02
1.00
"'-l!..
0.118
0.96
0.92
0.90
",m~~ww
"'
...
0
10
November 6, 1966
TA=2SC C
1.3
1.'
1
:- r-...
~/~
~ ~~~I-
:::::-
'" t-+-t+t-+---t-t1I+-\"'4-\\-I-+tt-f
1-+i-++-t-~
~~
0
3
~
5.•
..
~§
'"
,1./
'40
II
1/
V
iii "
"
.. ,..
-2.
,,~
i!:i5
~
:-...
TA= 2SoC
Oc
iii
"
7••
TA= SOC
.
1.
r""- ......
U 17
iii
.H ,.
21
11
10
0'
0'
21
i
Output Voltage and Current
Swing as a Function
Supply Voltage
Supply Currant as a
Supply Voltage
Function
Y :: :l:8Y
1Mn
'00'
RADrfl
Ql'lM521S
.....,..
..
,
Vs"
I
F
...!t~.7 ~r
30
~
!"
0'
'000
....
I'~t=
TA,= 2S-C
~
I!l
~
Voltage Gain as a
RADJ (Figure 3)
Function
Voltage Gain
Adjust Circuit
,.
'00
14.
0_
11-114
·,
10
'00
"
SOURCE RESISTANCE-a
".
0"'_
Signetics Linear Products
Product Specification
NEjSE592
Video Amplifier
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Phase Shift as a
Function of Frequency
f'
-.....
GAIN 2
~!: 21S~"c
"
-so
"
-150
I'.
\
-250
~\
-300
-3SO
1
2
3
4
5
6
1
fREQUENCY-MHz
8
9
Voltage Gain as a
Function of Frequency
10
..
\\
-2"
I"
T A = 25°C, unless
otherwise specified.
~!: ;5~~
'Y.-.s;
.....,
-25 0
TEST CIRCUITS
Phase Shift as a
Function of Frequency
10
1
100
\\
1000
FREQUENCY-MHz
Voltage Gain as a
Function of Frequency
(All Gain Select Pins Open)
60
"
i!Al ~ 1KJ!
:s~"c
Vs= t6V
TA= 25°C
='
GAIN 1
40
"""'"
OAIH2
20
GAIN 3
V"\
~\
/
\\
0
10
100
FREQUENCY-MHz
\\
'\
V
V
\
/
1
\
10
FREQUENCY-MHz
•
November 6, 1986
11-115
Signetics Linear Products
Product Specification
Video Amplifier
NEjSE592
TYPICAL APPLICATIONS
v,
-.
NOTE:
vo(s)
V,(s)
1.4 X 104
"'--Z(8) + 2re
~
1.4 X 104
Z(s) +32
Basic Configuration
..
..
Q
O.h'
T
T
V.
O.2~F
AMPLITUDE:
PltIQUINCY:
UPPd
RUD HUD
I
-.
DI,,... INTIATOIi/AMPU:'..
-.
ZERO CRO"ING DETECTOR
NOTE:
For frequency F1
VoS!'1.4 X
Disc/Tape Phase-Modulated Readback Systems
November 6, 1986
11-116
<
BAND PASS
R
[~+ 1R/~J
4
LOW PASS
R
L
~
c
4
1.4 x 10'[
L
s2
[_S_J
s 1/RC
+
s
R/L s
+ +
J
1/LC
L
~
BAND REJECT
1.4X104
R
s2+1/LC
[
s2 + 1/LC
NOTE:
In the networks above, the R value used is assumed to include 2re. or approximately 32U
November 6, 1986
11-117
+
s/RC
]
Signetics
AN141
Using the NEjSE592 Video
Amplifier
Application Note
Linear Products
VIDEO AMPLIFIER PRODUCTS
NE/SE592 Video Amplifier
The 592 is a two-stage differential output,
wide-band video amplifier with voltage gains
as high as 400 and bandwidths up to
120MHz.
Three basic gain options are provided. Fixed
gains of 400 and 100 result from shorting
together gain select pins G'A - G'B and
G2A - G2B, respectively. As shown by Figure
I, the emitter circuits of the differential pair
return through independent current sources.
This topology allows no gain in the input
stage if all gain select pins are left open.
Thus, the third gain option of tying an external
resistance across the gain select pins allows
the user to select any desired gain from 0 to
400VIV. The advantages of this configuration
will be covered in greater detail under the
filter application section.
Three factors should be pointed out at this
time:
1. The gains specified are differential. Singleended gains are one-half the stated value.
2. The circuit 3dB bandwidths are a function
of and are inversely proportional to the gain
settings.
3. The differential input impedance is an inverse function of the gain setting.
In applications where the signal source is a
transformer or magnetic transducer, the input
bias current required by the 592 may be
passed directly through the source to ground.
Where capacitive coupling is to be used, the
base inputs must be returned to ground
through a resistor to provide a DC path for the
bias current.
Due to offset currents, the selection of the
input bias resistors is a compromise. To
reduce the loading on the source, the resistors should be large, but to minimize the
output DC offset, they should be
small- ideally on. Their maximum value is
set by the maximum allowable output offset
and may be determined as follows:
1. Define the allowable output offset (assume
1.5V).
February 1987
Table 1. Video Amplifier Comparison .File
PARAMETER
NE/SE592
Bandwidth (MHz)
120
120
Gain
0,100,400
10,100,400
RIN (k)
4-30
4-250
Vp_p (Va)
4.0
4.0
2. Subtract the maximum 592 output offset
(from the data sheet). This gives the output
offset allowed as a function of input offset
currents (1.5V - 1.0V = 0.5V).
3. Divide by the circuit gain (assume 100).
This refers the output offset to the input.
4. The maximum input resistor size is:
Input Offset Voltage
RMAX = Max Input Offset Current
(1)
0.005V
733
Filters
As mentioned earlier, the emitter circuit of the
NE592 includes two current sources.
Since the stage gain is calculated by dividing
the collector load impedance by the emitter
impedance, the high impedance contributed
by the current sources causes the stage gain
to be zero with all gain select pins open. As
shown by the gain vs. frequency graph of
Figure 3, the overall gain at low frequencies is
a negative 4BdB.
Higher frequencies cause higher gain due to
distributed parasitic capacitive reactance.
This reactance in the first stage emitter circuit
causes increasing stage gain until at 10M Hz
the gain is OdB, or unity.
5JJA
= 1.00kn
Of paramount importance during the design
of the NE592 device was bandwidth. In a
monolithic device, this precludes the use of
PNP transistors and standard level-shifting
techniques used in lower frequency devices.
Thus, without the aid of level shifting, the
output common-mode voltage present on the
NE592 is typically 2.9V. Most applications,
therefore, require capacitive coupling to the
load. An exception to the rule is a differential
amplifier with an input common-mode range
greater than + 2.9V as shown in Figure 2. In
this circuit, the NE592 drives a NE5tl B
transistor array connected as a differential
cascode amplifier. This amplifier is capable of
differential output voltages of 4BVp.p with a
3dB bandwidth of approximately 10MHz (depending on the capacitive load). For optimum
operation, Rl is set for a no-signal level of
+ 18V. The emitter resistors, RE, were selected to give the cascode amplifier a differential
gain of 10. The gain of the composite amplifier is adjusted at the gain selected point of the
NE592.
11-118
Referring to Figure 4, the impedance seen
looking across the emitter structure includes
small r. of each transistor.
Any calculations of impedance networks
across the emitters then must incl ude this
quantity. The collector current level is approximately 2mA, causing the quantity of 2 r. to
be approximately 32n. Overall device gain is
thus given by
Vo(s) = 1.4 X 104
VIN(S)
Z(S)
+ 32
(2)
where Z(S) can be resistance or a reactive
impedance. Table 2 summarizes the possible
configurations to produce low, high, and
bandpass filters. The emitter impedance is
made to vary as a function of frequency by
using capacitors or inductors to alter the
frequency response. Included also in Table 2
is the gain calculation to determine the voltage gain as a function of frequency.
Application Note
Signetics Linear Products
AN141
Using the NEjSE592 Video Amplifier
+30V
t---------+~-Ol OUTPUTS
I ~~~~PEAK
GIA
INPUT o---jH~--."....N
G2A
-6V
NOTE:
An resistor values are in ohms.
NOTE:
All resistor values are in ohms.
Figure 2. Video Amplifier With High Level Differential Output
Figure 1. 592 Input Structure
Table 2. Filter Networks
Vs" '8V
R
~
/
/
/
L
~
1\
\
LOW
PASS
1.4X104
---L
[s+lR/L]
AF03770S
\
/
c
R
~I
0
~
c
L
~j-----<)
With the addition of a capacitor across the
gain select terminals, the NE592 becomes a
differentiator. The primary advantage of using
the emitter circuit to accomplish differentiation is the retention of the high common
mode noise rejection. Disc file playback systems rely heavily upon this common-mode
rejection for proper operation. Figure 5 shows
a differential amplifier configuration with
transfer function.
Disc File Decoding
In recovering data from disc or drum files,
several steps must be taken to precondition
1.4 X 104
---R
[s +
BAND
PASS
x 104
----
BAND
REJECT
----
~/RC]
1.4
L
[S2 + R/L: + 1/LC ]
AF03790S
L
Differentiation
HIGH
PASS
AF03780S
R
Figure 3. Voltage Gain as a Function
of Frequency (All Gain Select
Pins Open)
February 1987
Va(s) TRANSFER
Vl(S) FUNCTION
FILTER
TYPE
Z NETWORK
l,,";>ri C
~
1.4X104 [
S2+ 1/LC
]
S2 + 1/LC + s/RC
R
AF03750S
NOTE: In the networks above, the R value used IS assumed to Include 2 fe, or approximately 32n.
the linear data. The NE592 video amplifier,
coupled with the BT20 bidirectional one-shot,
provides all the signal conditioning necessary
for phase-encoded data.
When data is recorded on a disc, drum or
tape system, the readback will be a Gaussian
shaped pulse with the peak of the pulse
corresponding to the actual recorded transi-
11-119
tion point. This readback signal is usually
5001lVp.p to 3mVp.p for oxide coated disc
files and 1 to 20mVp.p for nickel-cobalt disc
files. In order to accurately reproduce the
data stream originally written on the disc
memory, the time of peak point of the Gaussian readback signal must be determined.
II
Application Note
Signetics Linear Products
AN141
Using the NEjSE592 Video Amplifier
..
ed because the NE592 has no gain at DC due
to the capacitance across the gain select
terminals.
..
O.2IJF
V,
The output of the first stage amplifier is
routed to a linear phase shift low-pass filter.
The filter is a single-stage constant K filter,
with a characteristic impedance of 200n.
Calculations for the filter are as follows:
T
vo
VI
r
O.2.1'F
-6
-6
NOTE:
Z(8)
+ 2re
NOTES:
For frequency F,
1.4 X 104
Z(s)
where
R = characteristic impedance (n)
TClD070S
Vo{s) = 1.4 X 104
V, (5)
L = 2Ft"",
C=Y"",
< < 1/21J'(S2)C
Vo~1.4 X 104C~
+ 32
where
we = cut-off frequency (radians/sec)
dT
All resistor values are in ohms.
Figure 4. Basic Gain Configuration
for NE592, N 14
Figure 5. Differential With High
Common-Mode Noise Rejection
The classical approach to peak time determination is to differentiate the input signal.
Differentiation results in a voltage proportional to the slope of the input signal. The zerocrossing point of the differentiator, therefore,
will occur when the input signal is at a peak.
Using a zero-crossing detector and one-shot,
therefore, results in pulses occurring at the
input peak points.
A circuit which provides the preconditioning
described above is shown in Figure 6. Read·
back data is applied directly to the input of the
first NE592. This amplifier functions as a
wide-band AC-coupled amplifier with a gain of
100. The NE592 is excellent for this use
because of its high phase linearity, high gain
and ability to directly couple the unit with the
readback head. By direct coupling of readback head to amplifier, no matched terminating resistors are required and the excellent
common-mode rejection ratio of the amplifier
is preserved. DC components are also reject-
The second NE592 is utilized as a low noise
differentiator/amplifier stage. The NE592 is
excellent in this application because it allows
differentiation with excellent common-mode
noise rejection.
The output of the differentiator/amplifier is
connected to the 8T20 bidirectional monostable unit to provide the proper pulses al the
zero-crossing paints of the differentiator.
The circuit in Figure 6 was tested w~h an
input Signal approximating that of a readback
signal. The results are shown in Figure 8.
4mH
r---~----------------------------------~------~nn~-----.--------------~~V
4mH
r---~--------------------------~-.------JYrrL-
____~__~________~~~V
-=--o
ol--.....
8T20
CLR
X100AC
PRE·AMPLIFIER
LINEAR PHASE
DIFFERENTIA TOR
LOW PASS FILTER
BIDIRECTIONAL
ONE·SHOT
NOTE:
All resistor values are in ohms
Figure 6. 5MHz Phase-Encoded Data Read Circuitry
February 1987
11-120
DIGITAL
OUTPUTS
Signetics Linear Products
Application Note
Using the NEjSE592 Video Amplifier
AN141
+6V
lK
2.7K
10jJF
2.7K
J
o.'PF
0.1 pF
o-Jt---f-----~
+
51
MC'4N
51
12
1.
10
1K
.1
4.7K
56K
0.1
-:
-:
-:
lK
lK
-6V
NOTE:
All resistor values are in ohms
Figure 7. Wide-band AGe Amplifier
Automatic Gain Control
The NE592 can also be connected in con·
junction with a MC1496 balanced modulator
to form an excellent automatic gain control
system.
The signal is fed to the signal input of the
MC1496 and RC·coupled to the NE592. Un·
balancing the carrier input of the MC1496
causes the signal to pass through unatlenuat·
ed. Rectifying and filtering one of the NE592
outputs produces a DC signal which is pro·
portional to the AC signal amplitude. After
filtering; this control signal is applied to the
MC1496 causing its gain to change.
February 1987
II
11-121
Application Note
Signetics Linear Products
Using the NEjSE592 Video Amplifier
IV
I\. fI.
I I I
I
II
J~ \.
'I
,v
,.,.. "" I
~
rv \.
r"\
f'I f.
I I
V
V I-
/
I
PRE·AMPUFIER OUTPUT
IOOmv/DIY.
DlFFERENnAlOR
2OOmV/DIV.
,.,..
nME BASE 2OO ../DlY.
~
....
~
JH'I
;L U 'J'
l1f I
[J
"'I,j
PRE·AMP AND DlFFERENTIAlOR
SUPER IMPOSED
Url
BOTH 2OOmV/DIv'
TIME SASE 2t)Ons/DIV,
t
rn
I J V
,, ,
IV
I I I
\ooj
~ III..
~
I~
rr
,
IUU
I'"
I I
J I I
\.011
DIFFERENTIATOR
2OOmV/DIY.
8T20 Q OUTPUT
2V1DIV.
TIME BASE200na/DIY.
Figure 8. Test Results of Disc File Decoder Circuit
February 1987
11-122
AN141
p.A733/733C
Signetics
Differential Video Amplifier
Product Specification
Linear Products
PIN CONFIGURATION
DESCRIPTION
FEATURES
The 733 is a monolithic differential input,
differential output, wide-band video amplifier. It offers fixed gains of 10, 100, or
400 without external components, and
adjustable gains from 10 to 400 by the
use of an external resistor. No external
frequency compensation components
are required for any gain option. Gain
stability, wide bandwidth, and low phase
distortion are obtained through use of
the classic series-shunt feedback from
the emitter-follower outputs to the inputs
of the second stage. The emitter-follower outputs provide low output impedance, and enable the device to drive
capacitive loads. The 733 is intended for
use as a high-performance video and
pulse amplifier in communications, magnetic memories, display and video recorder systems.
• 120MHz bandwidth
• 250kn. input resistance
• Selectable gains of 10, 100, and
400
• No frequency compensation
required
• MIL-STO-SS3A, B, C available
F, N Packages
INPUT 2
G~~~EA~~
G 18 GAIN
SELECT
1
12
3
4
11
~~tE~~IN
~~tE~~IN
V·
APPLICATIONS
• Video amplifier
• Pulse amplifier in
communications
• Magnetic memories
• Video recorder systems
OUTPUT 2
7
TOP VIEW
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE
ORDER CODE
14·Pin Ceramic DIP
-55'C to +125'C
IlA733F
14·Pin Plastic DIP
-55'C to +125'C
jlA733N
o to
o to
14·Pin Plastic DIP
14·Pin Ceramic DIP
+70'C
jlA733CN
+70'C
IlA733CF
•
CIRCUIT SCHEMATIC
r---~--------~---4r---~----~----~-Ov·
INPUT 1
+----+-OOUTPUT 1
G,.
{
OUTPUT 2
GAIN
SELECT
December 2, 1986
G,.
11-123
853·1064 86704
Signetics Linear Products
Product Specification
pA.733/733C
Differential Video Amplifier
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
UNIT
VDIFF
Differential input voltage
PARAMETER
±5
V
VCM
Common-mode input voltage
±6
V
Vee
Supply voltage
±8
V
lOUT
Output current
10
rnA
TJ
Junction temperature
+150
'C
TSTG
Storage temperature range
-65 to + 150
'C
TA
Operating ambient temperature range
/lA733C
!1A733
o to +70
-55 to +125
'C
'C
1190
1420
mW
mW
PMAX
Maximum power dissipation 1
25'C ambient temperature (still-air)
F package
N package
NOTE:
1. The following derating factors should be applied above 2S'C:
F package at 9.SmWrc
N package at II.4mW rc.
DC ELECTRICAL CHARACTERISTICS TA = + 25'C, Vs = ± 6V, VCM = 0, unless otherwise specified. Recommended
operating supply voltages Vs = ± 6.0V.
/lA733C
SYMBOL
PARAMETER
Differential voltage gain
Gain 12
Gain 22
Gain 33
BW
tR
tpD
RIN
UNIT
Min
Typ
Max
Min
Typ
Max
250
80
8
400
100
10
600
120
12
300
90
9
400
100
10
500
110
11
RI = 2kQ, VOUT = 3Vp.p
Bandwidth
Gain 11
Gain 22
Gain 33
40
90
120
Rise time
Gain 11
Gain 22
Gain 33
VOUT = lVp_p
Propagation delay
Gain 11
Gain 22
Gain 33
VOUT = Wp_p
Input resistance
Gain 12
Gain 22
Gain 33
Input capacitance2
!1A733
TEST CONDITIONS
10
Gain 2
40
90
120
MHz
MHz
MHz
10.5
4.5
2.5
12
10.5
4.5
2.5
10
ns
ns
ns
7.5
6.0
3.6
10
7.5
6.0
3.6
10
ns
ns
ns
4.0
30
250
20
2.0
4.0
30
250
kQ
kQ
kQ
2.0
pF
los
Input offset current
0.4
5.0
0.4
3.0
ISlAS
Input bias current
9.0
30
9.0
20
VNOISE
Input noise voltage
VIN
Input voltage range
CMRR
Common-mode rejection ratio
Gain 2
Gain 2
SVRR
Supply voltage rejection ratio
Gain 2
December 2, 1986
BW = 1kHz to 10MHz
VIV
VIV
VIV
t2
± 1.0
12
± 1.0
!1A
!1A
/lVRMS
V
VCM = ± W, f';; 100kHz
VCM=±W, f=5MHz
60
86
60
60
86
60
dB
dB
AVs= ±0.5V
50
70
50
70
dB
11-124
Signetics Unear Products
Product Specification
Differential Video Amplifier
pA733/733C
DC ELECTRICAL CHARACTERISTICS (Continued) T A = + 25·C, Vs = ± SV, VCM = 0, unless otherwise specified.
Recommended operating supply voltages Vs = ± S.OV.
!lA733C
SYMBOL
PARAMETER
UNIT
Min
Output offset voltage
Gain 11
Gain 2 and 32, 3
VCM
Output common-mode voltage
Output voltage swing,
differential
ISINK
Output sink current
ROUT
Output resistance
Icc
Power supply current
Typ
Max
O.S
0.35
1.5
1.5
3.4
Min
Typ
Max
O.S
0.35
1.5
1.0
3.4
RL = oc
V
V
RL = oc
2.4
2.9
2.4
2.9
RL = 2k,Q
3.0
4.0
3.0
4.0
Vp_p
2.5
3.S
2.5
3.S
rnA
20
RL = oc
THE FOLLOWING SPECIFICATIONS APPLY OVER TEMPERATURE
Differential voltage gain
Gain 11
Gain 22
Gain3
!lA733
TEST CONDITIONS
16
,Q
20
24
O·C';;TA ';;70·C
16
V
24
rnA
-55·C';; TA';; 125·C
RI = 2k,Q, VOUT = 3Vp_p
250
60
6
SOO
120
12
200
60
6
SOO
120
12
VIV
VIV
VIV
RIN
Input resistance
Gain 22
los
Input offset current
S
5
!lA
IBIAS
Input bias current
40
40
!lA
VIN
Input voltage range
CMRR
Common-mode rejection ratio
Gain 2
VCM=±V, F';;100kHz
SVRR
Supply voltage rejection ratio
Gain 2
!;.VS = ±0.5V
Vos
Output offset voltage
Gain 11
Gain 2 and 32, 3
RL = oc
VOIFF
Output voltage swing,
differential
RL = 2k,Q
ISINK
Output sink current
Icc
Power supply current
6
± 1.0
V
50
50
dB
SO
SO
dB
2.6
1. Gain select pins GIA and G1B connected together.
2. Gain select pins G2A and G2B connected together.
3. All gain select pins open.
11-125
I.S
1.2
rnA
2.2
27
V
V
Vp_p
2.5
2.5
NOTES:
December 2, 1965
±1.0
I.S
1.5
RL±oc
k,Q
6
27
rnA
•
Signetlcs Linear Products
Product Specification
pA733/733C
Differential Video Amplifier
TYPICAL PERFORMANCE CHARACTERISTICS
Phase Shift as a
Function of Frequency
I'
Phase Shift as a
Function of Frequency
•
GAIN 2
Va= :tIY
TA=
25"'c
.
Vo- .~
T .... C
f'lii ~
-10
Voltage Gain as a
Function of Frequency
VI'" tlY
1\
['.
I'
I'
-25 0
1
2
3
4
5
8
7
•
9
10
-OlD
FREQUENCY-MHz
,
~
5
10
.
.....
\~.
-300
flL'"'lIIn
......
~
i'..
,,,=2I'"C
,
\
-
-,. ,
""000
10 100
FREQUENCY-MHz
~
-~~
I
""000
10
10 100
FREQUI!NCY-IIHI
........
Common Mode Rejection
Ratio as a Function
of Frequency
Output Voltage Swing
as a Function
of Frequency
'00 r-r"TTr-r-,"TTT""1-,..".....="..,..
...
GAIN 2
....
i ..
~
z
8:
i5AI-+!f-H'-I--HHi-lf-H~-l
70
g ~r;~~-i~~-i~r;-+~~
:
~r;~~-i~~-+~~-+~~
i
~r;~~-i~~-i~r;-+~~
8'·r;~rt-ttH-r~~f-f+~
·,..;-,..u.",,;;!...:::-,..u.~'M~..u."'~.M;:-L.L.IJL.:,:!aoM
I
1.0
. ...
1--hf-H,..-f--HflkI-If-H-H-l
~u
IUI-+if-H~f--HHi-\-lf-H~-l
~0.2
I···
~
D.'
-D.2
... ...
-OA
·,~~~s~,~.~~~~,~~~~,~
FREQUENCY-MHz
ifirlI
~
,.• 1-+!f-H-f--HHi--lf-H~-l
•• ..
V... ,t1V
TA=2I"C
RL= 111:0
,...
1.2
1-+i1-+l....Io.::I-IHi-jf-H-H-I
4 .•
50
Pulse Response
1.4
".I--hf-Hi-I--HHii-1- T"a2S·C
RL .. ,1dl
0
a:
'.1
Vs", :taw
Vs= :tav
TA:: UOC
........
-15 -10 -I
0
5
10
15
20
15 20
31
TIIIIE-,..
FREQUENCY-MHz
."""'"
Pulse Response
as a Function
of Supply Voltege
Differential Overdrive
Recovery Time
70
~
i
~
0
~
~
.
'A
.
1/
v,=
"II
/
3D
,..
I ,,,=.fl
GAIN 2
e
I
I"L
-'.0
Va= :taw
,
V
50
I ,.
0
Vs'" :l:av
TA= 2SOC
GAIN 2
U
lc ,..
"!;
e ...
IV
I
~
-
o0
--'
0
J
V
-u
20 40 80 10 100 120 '40 110 11. 200
DIFFEIiENTIAllNPUT VOL TAGE-rnV
-OA
1/
TA( 21 C
-f-
II TA= 711
OA
D.2
J
-D.2
-11 - 0 - I
0
5
W
U
m _
~
a
nUE-ns
........
December 2, 1986
RL = 1kO
T.=OCIJ
.~
= 'OY
::~~.v
I
I
I
1A
I
~
Pulse Response
as a Function
Of Temperature
........
11-126
-O~'110
-
-I
0
510112025:1Oas
llM1 __
--
Signetics Linear Products
Product Specification
Differential Video Amplifier
pA733/733C
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Voltage Gain
as a Function
01 Temperature
..
..
•.
,
1.10
Va= tev
1.01
1."
a I'..
3
1.04
-
w
~ 1.02
~ 1.00
i'..
-
f--
~O.H
"-
iO,N
'M
0,(12
0
10
1.'
z
z
0
GAIN~-
~F
""- "If Vo
Voltage on any pin, except Vee (Pin 4)
and MO (Pin 21), with respect to Vss
Vee
Back-bias voltage
10
DC output current (sink or source)
TA
Operating ambient temperature range
(under DC operating conditions)
TSTG
Storage temperature range
PTOT
Total power dissipation per package
February 12, 1987
VBB
TEST
RATING
UNIT
7
V
min. -7
V
10
mA
8
10
Voo
o to 60
'c
11
AD
18
19
MI,
MAN
20
21
22
Me
MO
Vss
24
MIS
25
MI,
'c
1
W
11-129
Back-bias supply voltage (to be
connected to Pin 4)
Back-bias supply voltage (to be
connected to Pin 1)
Control input for testing
purposes only. It is internally
connected to Vss via a 1kn
(approx.) resistor and needs no
MG
-65 to +150
DESCRIPTION
A2
A1
external connection
Memory gating input
Control input for additional
internal delay
Positive supply voltage
Control input for additional
internal delay
Control input for additional
internal delay
Memory input 2
Memory recirculate control.
Recirculation is activated when
MRN is Low
Memory clock input
Memory output
Negative supply voltage
(ground)
Memory input select; selects
MI1 or MI2
Memory input 1
853-1187 87586
•
Signetics Linear Products
Product Specification
SAA9001
317k Bit CCD Memory
BLOCK DIAGRAM
MIS
24
MRN
MG
TEST
A2 A1 AD
7
19
10 11
MC 20
ADDRESS
OT07
VARIABLE
DELAY
CCD
MEMORY
ARRAY
294 x 1080
OoTYPE
OoTYPE
FLIP·
FLOP
FUPFLOP
CAPACITANCE
SYMBOL
MAX
UNIT
CI
Data inputs MI" MI2 (Pins 25 and 18)
9
pF
Cc
Clock input MC (Pin 20)
9
pF
CG
Gating input MG (Pin 6)
9
pF
Co
Data output MO (Pin 21)
9
pF
CRN
Recirculation control MRN (Pin 19)
9
pF
CIS
Input select control MIS (Pin 24)
9
pF
CA
Delay program inputs AO, A1, A2 (Pins 11, 10, and 7)
9
pF
PARAMETER
February 12, 1987
11-130
D-TVPE
FUP·
FLOP
Signetics Linear Products
Product Specification
SM9001
317k Bit CCD Memory
DC OPERATING CONDITIONS
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
Voo
Supply voltage range
4.75
5.25
V
Vss
Back-bias supply range
-3.65
-3.35
V
VIL
Input voltage Low
-1.0
+O.B
V
VIH
Input voltage High
2.0
6.0
V
DC ELECTRICAL CHARACTERISTICS TA = 0 to + 60'C; Voo = 4.75 to 5.25V; Vss = -3.5 ± 0.15V; output not loaded.
unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
ILl
Input leakage current at Vl = GND to Voo:
Mil; M12; MC; MG; AO; A1; A2; MRN; MIS
Typ
Max
10
!1A
100
Power supply current from VOD at f = 21.3MHz
70
rnA
VOL
Output voltage Low at IOL = 4mA
0.4
V
VOH
Output voltage High at IOH = -1 rnA
2.4
V
AC TEST CONDITIONS
PARAMETER
Input pulse levels
Rise and fall times between O.B and 2.0V (tR. tF)
clock input MC
data inputs Mil. M1 2; gating input MG;
control inputs AO. A1. A2. MIS. MRN
Timing reference levels
clock input MC
data inputs Mil. M1 2; gating input MG
data output MO
Output load
February 12. 19B7
LIMIT
UNIT
0.6 and 2.4
V
<:3
ns
;;'3
ns
1.5
O.B or 2.0
O.B or 2.0
V
V
V
see Figure 4
11-131
•
Signetics Linear Products
Product Specification
SAA9001
317k Bit CCD Memory
AC ELECTRICAL CHARACTERISTICS
SYMBOL
TA
=0
to + 60°C; Voo
= 4.75
to S.2SV; Vee
= -3.S± 0.15V.
LIMITS
PARAMETER
Min
Typ
Max
UNIT
fCl
Clock frequency 1
tCl
Clock Low time
16
tCH
Clock High time
16
tR
Recirculation time 1
tGW
Waiting time (gating Low/High time)2
tGC
Gating setup time
7.5
ns
tCG
Gating hold time
0.5
ns
tiC
Data setup time
7.5
ns
tCI
Data hold time
0.5
ns
tOH
Output hold time
5.0
too
Output delay time
tAH
Output invalid after address change
tAD
Address valid after address change3
tMRN5U
Recirculation setup time 4
tMI55U
Input select setup timeS
21.3
MHz
ns
ns
27
ms
1100
/.Is
ns
23.5
0
ns
f.lS
7 clock
pulses + 1
/.IS
0
1
/.IS
0
1 clock
pulse + 1
/.Is
NOTES:
1. The maximum recirculation time must never be exceeded by any combination of low frequency gating and! or waiting time.
2. Every 1300/1s. at least three blocks of 1080 bits must be transferred to the output. This means that immediately after a wait of 1100/1s, three blocks
must be shifted out.
3. A change in delay will cause invalid data at the output for the time tAD.
4. After a change of MRN, the signal recirculation path is not switched before tMANSU'
5. After a change of MIS, data at the input is invalid for tMISSU.
February 12, 1967
11-132
Signetics Linear Products
Product Specification
317k Bit CCO Memory
SAA9001
FUNCTIONAL DESCRIPTION
Operation
The memory array is organized to handle data
in blocks of 1080 bits and has a capacity of
294 data blocks. The structure of the memory
array provides fast, serial data input and
output, with parallel transfer of data blocks
through the memory. Memory input and output are controlled by the memory gating
(MG); the serial output is initiated by the rising
edge of MG, and the storage of the data
present in the memory's input register is
performed on the falling edge of MG. In
normal operation, one cycle of MG is an
uninterrupted High level of at least 1080 clock
periods (-4 or + 3 clock periods) followed by
a Low level of at least 32 clock periods. Input,
output, and gating signals are all referred to
the rising edge of the memory clock (MC).
The internal recirculation facility is activated
when the control input MRN is Low.
Memory output
Output is enabled when MG is High and data
is clocked serially from the memory. Referring
to Figure 1, the first rising clock edge after the
positive transition of MG is defined as clock
pulse "0". If the delay control address is
A2 = AI = AO = 0, then the first bit of the
output is valid at clock pulse" 17" (the delay
of 17 clock periods is due to internal multiplexing of the data in the memory).
The output delay can be increased by the
values shown in Table 1 using the internal
delay line controlled by AO, AI, and A2.
Data input
Data to be stored is directed to the memory
from either Mil or MI2 as selected by the
control input MIS (see Table 2). The Mil input
is delayed by one clock period.
Table 2. Input Selection
CONTROL INPUT
MEMORY INPUT
MIS=O
MIS=1
Mil
MI2
Table 1. Additional Delay
Control
DELAY
ADDRESS
A2
AI
AO
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
ADDITIONAL DELAY
(CLOCK PERIODS)
0
1
2
3
4
5
6
7
Input data is clocked serially into the input
register of the CCD memory. When the negative transition of MG occurs, the 1080 bits of
data present in the input register are entered
into the memory array. If the interval of
MG = High is not an exact multiple of eight
clock periods, the timing of the negative
transition of MG is internally rounded to be an
exact multiple of eight clock periods. Note
that the data path from input Mil has a delay
of one clock period and the path from MI2 is
direct.
GATING MG
CLOCK MC
~~~~~i
MEMORV
INPUT
f\-f\--r-IL----~----.FlFLf\_
MO
MI
~
m___ =~~{*H~
FIRST OF
1080 BITS
~
I
~
I
I
Figure 1. Memory Input and Output Data Timings With Respect to the Memory Clock (MC) for a Memory Gating (MG) High
Period that Is a Multiple of 8 Clock Periods (no Internal Rounding of Gating Period)
February 12, 1987
11-133
•
Signetics Linear Products
Product Specification
SAA9001
317k Bit CCD Memory
The length of the MG = High interval required
for internal and external recirculation of data
is determined as shown in Figure 2. The
positive transition of MG (waveform 1) initiates the serial transfer of data from the output
register. Due to multiplexing in the memory,
valid data is available after 16 clock periods
(waveform 2). After a delay of "A" clock
periods, determined by AO, A 1, and A2 (waveform 3), and a one-clock period delay via a 0type flip-flop, the valid data is available at the
output pin MO (waveform 4).
Incoming data can be delayed by two
amounts: RP (waveform 5), a phase shift
introduced when the data is recirculated
through an external processing circuit, and 10
(waveform 6), a one-clock period delay when
input Mil is selected. The negative transition
of MG, internally rounded to a multiple of
eight clock periods (waveform 7), initiates
storage of the last 1080 bits presented at the
memory input (waveform 6). Therefore, the
MG = High interval is 16 + A + 1 + RP +
10 + 1080 clock periods, and this figure is
GATE RISING EOGE
rounded to a multiple of eight. From this,
(A + 1 + RP + 10) modulo 8 = O.
During internal recirculation of the data
(MRN = Low), the three D-type flip-flops in
the recirculation path give RP a value of three
clock periods and 10 will be zero. Consequently, the variable delay should be programmed for a delay of A = 4 for proper data
retention, i.e.. (4 + 1 + 3 + 0) modulo 8 = O.
In conclusion, to store 1080 bits of valid data
and to retrieve at the output 1080 valid data
bits, the MG = High interval must be at least
1076 clock periods followed by an MG = Low
interval of at least 32 clock periods. The
MG = Low interval can be reduced to a minimum of 24 clock periods when MG = High is
a multiple of eight clock periods.
periods. If the MG = High interval is a multiple
of eight clock periods during fast gating, the
MG = Low interval can be reduced to 24
clock periods (min.); otherwise, the
MG = Low interval must be at least 32 clock
periods. The output data is not valid during
fast gating and during the first two data
blocks at the output after fast gating has
ceased. No valid data is clocked into the input
register of the CCD memory during fast gating.
Slow Gating
The transfer of data can be decelerated by
using slow gating. For this, the MG = High or
MG = Low interval is extended to the maximum waiting time (tGw),
Fast Gating
HANDLING
Fast gating is a method of accelerating the
internal transfer of data through the memory
at the expense of valid data, and is therefore
useful for skipping unwanted data blocks. The
MG = High interval for fast gating is less than
1076 clock periods to a minimum of 360 clock
Inputs and outputs are protected against
electrostatic charge in normal handling. However, to be totally safe, it is desirable to take
normal precautions appropriate to handling
MOS devices.
I
0
_16---J
CCD MEMORY ARRAY
OUTPUT REGISTER
OUTPUT FROM
VARIABLE DELAY
J
I
-H-
0
I
CD
-111VAUD DATA
OUTPUT (MO)
I
0
j.--RP----J
DATA INPUT
(MI, OR MI,)
~
-11-
CCD MEMORY ARRAY
INPUT REGISTER
I
0
I
CD
10
--.JI·
~I
1080
GATE FALLING EOGE
111111111
MULTIPLE OF8
--t
.1
0
1- 8
WF20260S
Figure 2. Determination of Memory Gating High Period
February 12, 1987
11-134
Product Specification
Signetics Linear Products
317k Bit CCD Memory
SAA9001
CCD MEMORY
ARRAY
MO
400
MO~
PROCESSING CIRCUIT
OUTPUT
INPUT
~n
Figure 4. Output Load
Figure 3. Recirculation via an External Circuit
CLOCK
MC
-.....,.-·1
INPUT
Mil OR MI2
OUTPUT
MO
GAn~~
--:--'7"-.....
_-1.'GC I-
-.1(. . . .______
WF20270S
Figure 5. Timing Waveforms for Gating and I/O
DELAY AO,
ADDRESS
AI, A2 _ _ _ __
~
~~'AH~'AD
OUTPUT
MO _ _ _ _ _ _ __
Figure 6, Timing Waveforms for Address Setup and Hold
February 12, 1987
11-135
•
Signetics
Section 12
Vertical Deflection
Linear Products
INDEX
TDA2653A
TDA3651 AI
3653
TDA3652
TDA3654
Vertical Deflection .....•........................................................
12-3
Vertical Deflection .............................................................. 12-9
Vertical Deflection .................................................•............ 12-16
Vertical Deflection Output Circuit........................................... 12-20
II
TDA2653A
Signetics
Vertical Deflection
Product Specification
Linear Products
PIN CONFIGURATION
DESCRIPTION
FEATURES
The TDA2653A is a monolithic integrated circuit for vertical deflection in video
monitors and large screen color television receivers, e.g. 30AX and PIL-S4
systems.
• Oscillator; switch capability for
50Hz/60Hz operation
• Synchronization circuit
• Blanking pulse generator with
guard circuit
• Sawtooth generator with buffer
stage
• Preamplifier with fed-out inputs
• Output stage with thermal and
short-circuit protection
U Package
12 SYNC IN/BLANKING OUT
11 SAwroorHGENOUT
10 PREAMP INPUT
POsmVE SUPPLY OF
OUTPUT STAGE
7 FBGENOUT
6 GROUND
• Flyback generator
• Voltage stabilizer
5 POSmvESUPPLYVcc
4 REFVOIJ"AGE
APPLICATIONS
3 SAWTOOTH CAP
• Video monitor
• Television receiver
1 OSCCAP
2
fvmt~I~~VOLTAGE
lOP VIEW
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE
RANGE
ORDER CODE
13·Pin Plastic SIP power package (SOT-1418)
-20·C to +85·C
TD,A2653AU
November 14, 1986
12-3
853-0098 86561
Signetics Linear Products
Product Specification
TDA2653A
Vertical Deflection
BLOCK DIAGRAM
TDA2653A
I
t
BLANKING
PULSE
GENERAtoR
GUARD
CIRCUIT
J
FREQUENCY
DETECtoR
OSCILLAtoR
•
t
BUFFER
SYNC
1
'---
~~
I
OUTPUT STAGEI
THERMAL &
SHORT·CIRCUIT
PROTECTION
I
FLYBACK
GENERAtoR
SAWTOOTH
GENERAlOR
VOLTAGE
STABILIZER
t
I
1
n
t
FREQUENCY
6
5
4
3
2
1
f2 ~EAR.
f----'M-
7
rrtG\
8
I ~,
~
'CI~
J
-=-
G~
Q~
SYNC PULSE
INPUT
BLANKING PULSE
OUTPUT
JL
f}
1+
~.
..L
~
:k
f
+Vcc
4..L
AMPUTUDE
NOTE:
1. Condition for Pin 12: LOW voltage level.,. 50Hz; HIGH voltage level = 60Hz.
November 14, 1986
:
12·4
13
(1)
:
~
COIL
12
--11
10
9
-=-
f---<
+
~
I
Product Specification
Signetics linear Products
TDA2653A
Vertical Deflection
PIN NO.
I, 13
2
3
4
5
6
7
8
9
10
11
12
DESCRIPTION
Oscillator
The oscillator frequency is determined by a potentiometer at Pin 1 and a capacitor at Pin 13.
Sync input/blanking output
Combination of sync input and blanking output. The oscillator has to be synchronized by a positive·going pulse between
IV and 12V. The integrated frequency detector delivers a switching level at Pin 12.
The blanking pulse amplitude is 20V with a load of 1mAo
Sawtooth generator output
The sawtooth signal is fed via a buffer stage to Pin 3. It delivers the signal which is used for linearity control, and
drive of the preamplifier. The sawtooth is applied via a shaping network to Pin 11 (linearity) and via a resistor to Pin 4
(preamplifier).
Preamplifier input
The DC voltage is proportional to the output voltage (DC feedback). The AC voltage is proportional to the sum of the
buffered sawtooth voltage at Pin 3 and the voltage, with opposite polarity, at the feedback resistor (AC feedback).
Positive supply of output stage
This supply is obtained from the flyback generator. An electrolytic capacitor between Pins 7 and 5, and a diode
between Pins 5 and 9 have to be connected for proper operation of the f1yback generator.
Output of class·S power stage
The vertical deflection coil is connected to this pin, via a series connection of a coupling capacitor and a feedback
resistor, to ground.
Flyback generator output
An electrolytic capacitor has to be connected between Pins 7 and 5 to complete the f1yback generator.
Negative supply (ground)
Negative supply of output stage and small signal part.
Positive supply
The supply voltage at this pin is used to supply the f1yback generator, voltage stabilizer, blanking pulse generator and
buffer stage.
Reference voltage of preamplifier
External adjustment and decoupling of reference voltage of the preamplifier.
Sawtooth capacitor
This sawtooth capacitor has been split to realize linearity control.
50Hz/60Hz switching level
This pin delivers a LOW voltage level for 50Hz and a HIGH voltage level for 60Hz. The amplitudes of the sawtooth
signals can be made equal for 50Hz and 60Hz with these levels.
ABSOLUTE MAXIMUM RATINGS
RATING
UNIT
Vg =VCC
Supply voltage (Pin 9)
40
V
Vs
Supply voltage output stage (Pin 5)
58
V
7
7
24
58
0
40
V
V
V
V
V
V
0
1
10
0
5
1.2
1.5
50
1
3
0
mA
mA
mA
mA
mA
A
A
mA
mA
mA
mA
Storage temperature range
-25 to +150
°C
Operating ambient temperature range
-20 to limiting
value
°C
SYMBOL
Voltages
V3
V13
V4 ; 10
Vs
-Vs
V7; 11
100
50
150
NOTE:
8HA Includes OMBH which ;s expected when heatsink
compound is used. 8JMB
5°C/W.
-<
Figure 1. Total Power Dissipation
Currents
11
-11
±12
IP3
-13
17
-17
111
-111
112
-112
TSTG
TA
PARAMETER
Pin 3
Pin 13
Pins 4 and 10
Pin 6
Pins 7 and 11
Pin 1
Pin 2
Pin 3
Pin 7
Pin 11
Pin 12
NOTES:
1. Pins 5, 6 and 8: internally limited by the short-circuit protection circuit.
2. Total power dissipation: internally limited by the thermal protection circuit.
November 14, 1986
12-5
•
Product Specification
Signetlcs Linear Products
TDA2653A
Vertical Deflection
DC ELECTRICAL CHARACTERISTICS TA = 2S·C, unless otherwise specified.
LIMITS
UNIT
PARAMETER
SYMBOL
Min
V9= VCC
Supply voltage
9
V6
V6
Output voltage
at -16=1.lA
at 16= 1.lA
Vs--2.2
Typ
Max
SO
Vs-l.9
1.S
1.6
V
V
V7
Flyback generator output voltage at -16 = 1.1 A
± 16
Peak output current
1.2
A
±
Flyback generator peak current
1.2
A
'7
V
Vcc-2.2
Feedback
-14, 10
Input quiescent current
0.1
iJ.A
Synchronization
V2
Sync input pulse
12
1
28
Tracking range
V
%
Oscillator/sawtooth generator
V1
V3
V11
Oscillator frequency control input voltage
6
9
V
Sawtooth generator output voltage
0
0
VCC-1
VCC-2
V
V
0
-2
4
mA
p.A
mA
-13
Sawtooth generator output current
+SO
111
(Afll)/ ATCASE
Oscillator temperature dependency
TCASE = 20 to 100·C
(Aflf)/AVs
Oscillator voltage dependency
Vs=10 to SOV
104
·C
4 X 104
y-1
Blanking pulse generator
V2
Output voltage at Vs = 24V; 12 = 1mA
-12
Output current
R2
Output resistance
ts
18.5
V
S
Blanking pulse duration at 50Hz sync
mA
410
n
1.4
± 0.07
ms
50Hz/60Hz switch capability
V12
Saturation voltage; LOW voltage level
1
V
112
Output leakage current
1
iJ.A
November 14, 1986
12-6
Product Specification
Signetlcs Linear Products
Vertical Deflection
TDA2653A
47k
lOOk
FREQUENCY
r.~
47k
lN4148
(2.)
47k
3.3k
~
J
Uk
lk
lOnF
JL..rL
SYNC BLANKING
680
0.56
AMPL
~
120
(I)
~
100
NOTES:
1. Condition for Pin 12: LOW voltage level"" 50Hz; HIGH voltage level- 60Hz.
2. The values given in parentheses and the dotted components are valid for the PIL-S4 system.
Figure 2. Typical Vertical Deflection Circuit for 30AX System (26V)
•
November 14, 1986
12-7
Product Specification
Signetlcs Linear Products
TDA2653A
Vertical Deflection
2
10
11
12
*'
tOO.F
270k
toOk
470nF
22k
FREQUENCY
47k
toO
nF
-=lN4148-=
BC558
(2x)
180k
lN4148
5.6M
(2x)
1
4.7k
lk
toO
10nF
270k
lk
SL ..rt.
E/W
DRIVE
15k
-=
10k
-=
33k
PICTURE
CENTRING
-=
Uk
10k
tOO
AMPL
SYNC BLANKING
8.8
470.F
8.8
+
+VCCf=28V
+VCC2=12V
NOTES:
1. Condition for Pin 12: LOW voltage level"" 50Hz; HIGH voltage level" 60Hz.
2. VCC1 ... 26V, VCC2 - 12V in Quasi-bridge Connection.
Figure 3. Typical Vertical Deflection Circuit for 30AX System
Data Measured in Figures 2 and 3
PARAMETER
SYMBOL
30AX
SYSTEM
(26V)
(Figure 2)
30AX
SYSTEM
(26 V/12V)
(Figure 3)
PIL·S4
SYSTEM
(Figure 2)
VS1
V52
System supply voltages
typ
typ
26
26
12
26V
-V
151
152
System supply currents
typ
typ
315
330
-35
195mA
-rnA
V6_8
Output voltage
typ
14
14.6
13.5V
V6_8
Output voltage (peak value)
typ
42
42
49V
16IP'P)
Deflection current (peak-to-peak value)
typ
2.2
2.2
1.32A
tFL
Flyback time
typ
1
0.9
Urns
Pror
Total power dissipation per package
typ
max
4.1
4.8
4
4.8
3W
3.4W1
f
Oscillator frequency unsynchronized
typ
46.5
46.5
46.5Hz
NOTE:
1. Calculated with LlVs = +5% and LlAYOKE = -7%.
November 14, 1986
12·8
Signetics
TDA3651A/3653
Vertical Deflection
Product Specification
Linear Products
DESCRIPTION
FEATURES
The TDA3651A is a vertical deflection
output circuit for drive of various deflection systems with deflector currents up
to 2A peak-to-peak.
• Driver
• Output stage
• Thermal protection and output
stage protection
• Flyback generator
• Voltage stabilizer
PIN CONFIGURATIONS
TDA3653
A Package
1 INPUT VOLTAGE
3 INPUT VOLTAGE
APPLICATIONS
5 OUTPUT VOLTAGE
• Video terminals
• Television
6 FLYBACK GENERATOR
7 GUARD CIRCUIT
ORDERING INFORMATION
DESCRIPTION
9-Pin Plastic SIP (SOT-131B)
9-Pin Plastic SIP (SOT-157B)
9-Pin Plastic SIP (SOT-nOB)
8 FLYBACK GENERATOR
TEMPERATURE RANGE
o to
o to
o to
9 SUPPLY VOLTAGE
ORDER CODE
+70·C
TDA3651A
+70·C
TDA3651AQ
+70·C
TDA3653A
TOP VIEW
CD10341S
TDA3651
A Package
1 INPUT VOLTAGE
3 INPUT VOLTAGE
5 OUTPUT VOLTAGE
6 FLYBACK GENERATOR
7 VOLTAGE STABILIZER
8 FLYBACK GENERATOR
9 SUPPLY VOLTAGE
TOP VIEW
TDA3651
AQ Package
(SIL BENT)
1
INPUT VOLTAGE
3
INPUT VOLTAGE
5
OUTPUT VOLTAGE
6
FLYBACK GENERATOR
7 VOLTAGE STABILIZER
8 FLYBACK GENERATOR
9 SUPPLY VOLTAGE
TOP VIEW
~
November 14, 1986
12-9
= BENT LEADS
853-0974 86554
•
Signetics Linear Products
Product Specification
TDA3651A/3653
Vertical Deflection
BLOCK DIAGRAM TDA3651A/AQ
..--------r----~~v+
input
FUNCTIONAL DESCRIPTION
Output Stage and Protection
Circuit
Pin 5 is the output pin. The supply for the
output stage is fed to Pin 6 and the output
stage ground is connected to Pin 4. The
output transistors of the Class-B output stage
can each deliver 1A maximum. The 'upper'
power transistor is protected against shortcircuit currents to ground, whereas during
flyback, the 'lower' power transistor is protected against too high voltages which may
occur during adjustments.
Moreover, the output transistors have been
given extra solidity by means of special measures in the internal circuit layout.
A thermal protection circuit is incorporated to
protect the IC against too high dissipation.
November 14, 1986
This circuit is 'active' at 175°C and then
reduces the deflection current to such a value
that the dissipation cannot increase.
Driver and Switching Circuit
Pin 1 is the input for the driver of the output
stage. The signal at Pin 1 is also applied to
Pin 3 which is the input of a switching circuit.
When the flyback starts, this switching circuit
rapidly turns off the lower output stage and so
limits the turn-off dissipation. It also allows a
quick start of the flyback generator. Pin 3 is
connected externally to Pin I, in order to
allow for different applications in which Pin 3
is driven separate from Pin 1.
Flyback Generator
The capacitor at Pin 6 is charged to a
maximum voltage, which is equal to the
supply voltage Vee (Pin 9), during scan.
12-10
When the flyback starts and the voltage at
the output pin (Pin 5) exceeds the supply
voltage (Pin 9), the flyback generator is activated. The Vee is connected in series (via Pin
8) with the voltage across the capacitor.
The voltage at the supply pin (Pin 6) 01 the
output stage will then be maximum twice Vee.
Lower voltages can be chosen by changing
the value of the external resistor at Pin 8.
Voltage Stabilizer
The internal voltage stabilizer provides a
stabilized supply of 6V for drive of the output
stage, so the drive current of the output stage
is not affected by supply voltage variations.
The stabilized voltage is available at Pin 7.
A decoupling capacitor of 2.211F can be
connected to this pin.
Product Speclflcotlon
Signetics Uneor Products
Vertical Deflection
TDA3651A/3653
ABSOLUTE MAXIMUM RATINGS
RATING
SYMBOL
UNIT
PARAMETER
3651
3653
55
50
55
Vee
60
40
60
Vee
5.6
V
V
V
0.75
1.5
-0.75
+0.85
-1.5
+1.6
0.75
1.5
-0.75
±0.85
-1.5
+1.6
A
AI
-65 to +150
-25 to +65
-25 to +150
-65 to +150
-25 to +65
-25 to +150
·C
·C
·C
Voltage (Pins 4 and 2 externally connected to ground)
VS-4
V9_4=VCC
VS- 4
VI-2; VS_2
V7-2
Output voltage (Pin 5)
Supply voltage (Pin 9)
Supply voltage output stage (Pin 6)
Input voltage (Pins 1 and 3)
External voltage (Pin 7)
V
Currents
±ISRM
±ISSM
18SM
18SM
Repetitive peak output current (Pin 5)
Non-repetitive peak output current (Pin 5)
Repetitive peak flyback generator
output current (Pin 8)
Non-repetitive peak flyback generator
output current (Pin 8)
A
A
A
At
Temperatures
TSTG
TA
TJ
Storage temperature range
Operating ambient temperature range
Operating junction temperature range
NOTE:
t. Non-repetitive du1y factor maximum 3.3%.
DC ELECTRICAL CHARACTERISTICS
T A = 25·C; Vcc = 26V; Pins 4 and 2 externally connected to ground. unless otherwise specified.
3653
3651
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
Min
Typ
Max
Is(p.p)
Output current (peak-to-peak value)
1.2
1.5
1.2
1.5
A
-18
Flyback generator output current
0.7
0.85
0.7
0.85
A
18
Flyback generator output current
0.6
0.75
0.6
0.75
A
60
V
Output voltages
VS-4M
Peak voltage during flyback
-Vs-Ssat
Saturation voltage to supply at
-15 = lA (3651); 0.6A (3653)
55
2.5
3.0
2.3
2.8
V
VS-4sat
Saturation voltage to ground at
-Is = 1A (3651); 0.6A (3653)
2.5
3.0
1.7
2.2
V
-Vs-Ssat
Saturation voltage to supply at -Is = 0.75A
2.2
2.7
2.5
3.0
V
VS-4sat
Saturation voltage
2.2
2.7
2.0
2.5
V
40
V
60
V
to ground at Is = 0.75A
Supply
V9-2
Supply voltage
VS-4
Supply voltage output stage
10
50
10
55
9
19
Supply current (no load and no quiescent current)
14
Quiescent Current (see Figure 1)
10
mA
12
38
25
mA
25
Variation of quiescent current with temperature
November 14. 1986
20
52
-0.04
12-11
6
40
-0.04
mA
•
Signetics Unear Products
Product Specification
TDA3651A/3653
Vertical Deflection
DC ELECTRICAL CHARACTERISTICS (Continued) TA = 25°C; Vee = 26V; Pins 4 and 2 externally connected to ground.
unless otherwise specified.
3653
3651
SYMBOL
PARAMETER
Min
Typ
Max
Min
Typ
Max
I
UNIT
Flyback ganerator
V9-Bsat
saturation voltage at -Ia = 1.1A (3651); 0.85A (3653)
1.6
2.1
1.6
2.1
V
Va-9sat
saturation voltage at la = 1A (3651); 0.75A (3653)
2.5
3.0
2.3
2.8
V
V9-Bsat
Saturation voltage at la = 0.85A (3651); 0.7A (3653)
1.4
1.9
1.4
1.9
V
Va-9sat
Saturation voltage at la = 0.75A (3651); 0.6A (3653)
2.3
2.8
2.2
2.7
V
250
100
5
100
pA
pA
VS-9
Flyback generator active if
-Ia
Leakage current
4
4
V
I,
Input current for ± 15 -1A (3651); 1.5A (3653)
175
2.30
380
1300
V,_2
Input voltage during scan
0.9
1.9
2.7
3.2
V
'3
Input current during scan
0.01
2.5
.01
.52
rnA
V3-2
Input voltage during scan
0.9
Vee
0.9
Vee
V
V3-2
Input voltage during flyback
0
200
250
mV
V7-2
Voltage at Pin 7
5.6
V
'7
Load current of Pin 7
V7-2
Unloaded voltage at Pin 7 during flyback
TJ
Junction temperature of switching on the thermal
protection
9JMB
Thermal resistance from junction to mounting base
5.5
6.1
6.6
4.4
5.0
15
V
15
158
V
175
192
3
4
°C
10
12
°C/W
see
Figure
3
Po
Power dissipation
Go
Open·loop gain at 1kHz; RL = 1kn
36
42
dB
fA
Frequency response (- 3dB); R = 1kn
60
40
kHz
NOTE:
1. The maximum supply voltage should be chosen such that during flybeck the voltage at Pin 5 does not exceed 5SV.
November 14. 1986
12·12
Product Specification
Signetics Linear Products
Vertical Deflection
TDA3651A/3653
75
20
INFINITE HEATSINK
MAX
50
OHA - 8°CIW
!
lYP
".s_.
b
10
.t
MIN
25
NO HEATSINK
0
0
0
25
50
0
50
100
150
TA(,C)
Vee
Figure 1. Quiescent Current 14 as a
Function of Supply Voltage Vee
Figure 2. Power Derating Curves
APPLICATION INFORMATION The following application data are measured in a
typical application as shown in Figures 3 and 4.
Deflection current (including 6% overscan)
peak-to-peak value
Is(p.p) typo 0.87 A
Supply voltage
Total supply current
V9 -4 typo 26V
ITOT typo 148mA
Peak output voltage during flyback
VS-4M
< 50V
Saturation voltage to supply
typo 2.0V
VS-6sal < 2.5V
Saturation voltage to ground
typo 2.0V
VS- 4sa1 < 2.5V
typo 0.95ms
til < 1.2ms
Flyback time
Total power dissipation in IC
PTOT typo 2.5W
Operating ambient temperature
TA
< 65'C
•
November 14, 1986
12-13
Signetics Unear Products
Product Specification
Vertical Deflection
TDA3651AJ3653
TDA3651A
1
{.2
5
3
4.4
390 pF ..,.
Il
1
6
"
1100nF
ve rtical drive
(from p in 1 TDA2578A)
+
"
BAX12A~
6.8K
VERTICAL
DEFLECTION
COILS
AT1236/20
10K
r
+
+
;;
4.7 IlF
8.2 K
..,.
r
4.7
+
(pin 3
TDA2578A)
12K
~.8nF
~
lK
+
220llF
vertical
feedback
(pin 2
TDA2578A)
9
8
n.c.17
+26V
1500llF
(16V)
1.2
100
amplitude
TC214108
NOTE:
Deflection coils AT1236/20: L - 29mH. R -13.6Sl; deflection current without overscan Is 0.82 Ap.p and EHT voltage Is 25kV.
Figure 3. Typical Application Circuit Diagram of the TDA3651A (Vertical Output),
When Used In Combination With the TDA2578A (See Figure 5)
November 14, 1986
12·14
Signetics Linear Products
Product Specification
TDA3651A/3653
Vertical Deflection
horizontal
flyback
+ 12V
sandcastle pulse
f\
horizontal
drive
..J L
...r---A_··L
mute
>0.2mA
<4.0mA
v+
~'*L £l
>4mA
r---
1K
; - I---<
~O
+ !iF
10
2.2
nF
6.8
K
36K
~
11
4.7 K
12
13
220
1:0
~+!iF
""'+:
14
15
I!
1:
4
F
16
17
TDA2578A
9~
8
7
4.7 K
6
4
51
~
820
4.7!iF
71--- +10 nF I
56K
J
-=-
I'F
+::!:: 22
J!i F
100
K
K
+
150
PF
J
1
II'F
+
680..1.
nF ~
F
J!i
10
220
K
I
~~
1
~
1
82
150
2
3
foadi.
(horizontal)
_
(vertical)
J
I
vertIcal
feedback
vertical
drive
+ from pin 9
TDA3651A
video
Figure 4. Typical Application Circuit Diagram; for Combination of the TDA2578A With the TDA3651A (See Figure 3)
F
1K
33 K
to pin
180 K
14
~
TDA2578A
+12V
tOl~in
47K
~
~}I'F
+12V
TDA2578A
220 K
NOTES:
1kn resistor between Pin 18 and +12V: without mute function.
220kn between Pin 1B and ground: with mute function.
Figure 5. Circuit Configuration at Pin 14
for Phase Adjustment
November 14, 1986
Figure 6. Circuit Configuration at Pin 18 for VCR Mode
12-15
TDA3652
Signetics
Vertical Deflection
Product Specification
Linear Products
DESCRIPTION
FEATURES
The TDA3652 is an integrated power
output circuit for vertical deflection in
systems with deflection currents up to
3Ap_p.
• Driver
• Output stage and protection
circuits
• Flyback generator
• Voltage stabilizer
PIN CONFIGURATION
U Package
1 INPUT
SWIlCHING
CIRCUIT
OUT SfAGE
GND
APPLICATIONS
• Video monitors
• TV receivers
8 OUT SfAGE
VOLTAGE
SfABIUZER
ORDERING INFORMATION
DESCRIPTION
8 FLYBACK GENERAlOR
TEMPERATURE RANGE
ORDER CODE
9-Pin Plastic SIP (SOT-131 B)
-25°C to +65°C
TDA3652U
9-Pin Plastic SIP Bent to DIP
(SOT-157B)
-25°C to +65°C
TDA3652QU
lOP VIEW
BLOCK DIAGRAM
TO
FEEDBACK
INPUT
February 12, 1987
12-16
853-1186 87586
Product Specification
Signetics Unear Products
TDA3652
Vertical Deflection
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
Voltages (Pins 4 and 2 externally connected to ground)
Output voltage (Pin 5)
55
V
V9_4 = Vee Supply voltage (Pin 9)
40
V
VS_4
VS_4
Supply voltage output stage (Pin 6)
55
V
VI_2
Driver input voltage (Pin 1)
Vee
VI
V3-2
Switching circuit input voltage (Pin 3)
5.6
V
Currents
± ISRM
Repetitive peak output current (Pin 5)
1.5
A
±ISSM
Non-repetitive peak output current (Pin 5)
3
A2
ISRM
Repetitive peak flyback generator output
current (Pin 8)
-1.5
+1.6
A
A
± ISSM
Non-repetitive peak flyback generator output
current (Pin 8)
3
A2
Temperatures
TSTG
Storage temperature range
-65 to +150
·C
TA
Operating ambient temperature range
-25 to +65
·C
TJ
Operating junction temperature range
-25 to +150
·C
NOTES:
1. The maximum input voltage should not exceed the supply voltage Nee at Pin 9). In most
applications Pin 1 is connected to Pin 3; the maximum input voltage should then not exceed
5.6V.
2. Non~repetitive duty factor maximum 3.3%.
II
February 12, 1987
12-17
Product Specification
Signetics Linear Products.
TDA3652
Vertical Deflection
DC AND AC ELECTRICAL CHARACTERISTICS
Vee = 26V; TA = 25'C; Pins 4 and 2 externally connected to ground,
unless otherwise specified.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
Supply
Vee
Supply voltage (Pin 9)
VS-4
Supply voltage output stage (Pin 6)
40
V1
55
v1
9
12
mA
40
65
10
lee
Supply current (no load and no quiescent current) (Pin 9)
14
Quiescent current (see Figure 1)
61 4
Variation of quiescent current with temperature
25
-0.04
mA
mA/'C
Output current
Is(p.p)
Output current (Pin 5) (peak-to-peak value)
2.5
3.0
A
-Ia
Output current flyback generator (Pin 8)
1.35
1.6
A
la
Output current flyback generator (Pin 8)
1.25
1.5
A
Output voltage
VS-4M
Peak voltage during flyback
55
V
-VS- 6SAT
Saturation voltage to supply at -15
2.5
3.0
V
VS- 4SAT
Saturation voltage to
2.5
3.0
V
-VS-SSAT
Saturation voltage to
2.2
2.7
V
VS- 4SAT
Saturation voltage to
2.2
2.7
V
= 1.5A
ground at 15 = 1.5A
supply at -15 = lA
ground at 15 = 1A
Flyback generator
V9-aSAT
Va-9SAT
= 1.6A
la = 1.5A
-Ia = 1.1 A
18 = 1A
Saturation voltage at -18
1.6
2.1
V
Saturation voltage at
2.5
3.0
V
1.4
1.9
V
2.3
2.8
V
5
100
/J. A
190
240
400
iJ.A
2.0
V9-aSAT
Saturation voltage at
Va- 9SAT
Saturation voltage at
VS-9
Flyback generator active
-18
Leakage current at Pin 8
11(p.p)
Input current for 15
Vl-2
Input voltage during scan (Pin 1)
1.3
3.5
V
13
Input current during scan (Pin 3)
0.01
2.5
mA
V3_2
Input voltage during scan (Pin 3)
0.9
5.6
V
V3-2
Input voltage during flyback (Pin 3)
0
0,2
V
= 4A
V
4
at Pin 1 (peak-to-peak value)
General data
TJ
Junction temperature of switching on the thermal protection
OJMB
Thermal resistance from junction to mounting base
158
175
192
'C
4
'C/W
PTOT
Total power dissipation
see Figure 2
Go
Open-loop gain at 1kHz
36
dB
fR
Frequency response (-3dB) at RL = 1kn
50
kHz
NOTE:
1. The maximum supply voltage should be chosen such that during flyback the voltage at Pin 5 does not exceed S5V.
February 12, 1987
12-18
Product Specification
Signetics Linear Products
TDA3652
Vertical Deflection
80
25
~. /
,/"
60
,/"
20
lYP
/'
e,... -
V
./
-~
MIN
--.....--
20
o
20
r
l
INFINITE
HEATSINK
I
--40
~
.......
r--. I
'-.
t!J:H
o
8'eJW
60
V+(V)
o
TSlN~i
n
o
50
I
to-.
\
I'!...
100
150
65
TA I'C)
QP18200S
Figure 1. Quiescent Current (14 as a
Function of Supply Voltage (Vee)
APPLICATION INFORMATION
The function is described beside the corre·
sponding pin number.
1 Driver - This is the input for the driver of
the output stage.
2 Negative Supply (Ground)
3 Switching Circuit - This pin is normally
connected externally to Pin 1. It is also
possible to use this pin to drive the switching
circuit for different applications. This switching circuit rapidly turns off the lower output
stage at the end of scan and also allows for a
quick start of the flyback generator.
4 Output Stage Ground
5, 6 Output Stage and Protection Circuits
- Pin 5 is the output pin and Pin 6 is the
Figure 2. Power Derating Curve
output stage supply pin. The output stage is a
class-B type with each transistor capable of
delivering 1.5A maximum. The "upper" output transistor is protected against short·circuit
currents to ground. The base of the "lower"
power transistor is connected to ground duro
ing flyback and so it is protected against too
high flyback pulses which may occur during
adjustments. In addition, the output transistors are protected by a special layout of the
internal circuit. The circuit is protected ther·
mally against excessive dissipation by a cir·
cuit which operates at temperatures of 175°C
and upwards, causing the output current to
drop to a value such that the dissipation
cannot increase.
7 Voltage Stabilizer - The internal voltage
stabilizer provides a stabilized supply voltage
of 6V for drive of the output stage, so the
drive current is not influenced by the various
voltages of different applications.
8, 9 Flyback Generator - Pin 8 is the
output pin of the flyback generator. Depending on the value of the external resistor at Pin
8, the capacitor at Pin 6 will be charged to a
fixed level during the scan period. The maximum height of the level is equal to the supply
voltage at Pin 9 {Ved. When the flyback
starts and the flyback pulse at Pin 5 exceeds
the supply voltage, the flyback generator is
activated and then the supply voltage is
connected in series (via Pin 8) with the
voltage across the capacitor. The voltage at
the supply pin (Pin 6) of the output stage will
then be not more than twice the supply
voltage.
II
February 12, 1987
12-19
TDA3654
Signetics
Vertical Deflection Output
Circuit
Product Specification
Linear Products
DESCRIPTION
FEATURES
The TDA3654 is a full-performance vertical deflection output circuit in a 9-lead,
single in-line encapsulation. The circuit
is intended for direct drive of the deflection coils and it can be used for a wide
range of 90· and 110· deflection systems.
• Direct drive to the deflection
colis
.90· and 110· deflection system
• Internal blanking guard circuit
• Internal voltage stabilizer
PIN CONFIGURATION
The TDA3654 is provided with a guard
circuit which blanks the picture tube
screen in case of absence of the deflection current.
• Video monitors
• TV receivers
U Package
INPUT 1
GND 2
SW1J.~'t1~I~
STAre&~
APPLICATIONS
3
4
OUTPUT 5
OUTPUT STAGE
SUPPLY INPUT
STXg:.~~~
GE~~~g~
7
8
ORDERING INFORMATION
TOPYIEW
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
9-Pin Plastic SIP (SOT-131B)
-25·C to + 60·C
TDA3654U
9-Pin Plastic SIP (SOT-157)
-25·C to +60·C
TDA3654AU
BLOCK DIAGRAM
r------------------------------4~----~~--+v~
+
TDA3654
THERMAL
AND
SOAR
PROTECTION
INPUT
TO
OUTPUT
STAGE
I--.....--lf!:-.-+. FEEDBACK
--+--=-t--+t
February 12, 1987
12-20
853-1183 87585
Signetics Linear Products
Product Specification
TDA3654
Vertical Deflection Output Circuit
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
Voltages
VS_4
V9 _4
Output voltage
60
V
Supply voltage
40
V
VS- 4
Supply voltage output stage
60
V
Vl
Input voltage
VS-4
V
V3_2
Input voltage switching circuit
VS-4
V
V7_2
External voltage at Pin 7
5.6
V
±ISRM
Repetitive peak output current
1.5
A
±ISSM
Non-repetitive peak output current1
3
A
ISRM
Repetitive peak output current of
flyback generator
+1.5
-1.6
A
A
±ISSM
Non-repetitive peak output current of
flyback generator1
3
A
-
2
Currents
Temperatures
TSTG
Storage temperature range
-65 to +150
·C
TA
Operating ambient temperature range
(see Figure 2)
-25 to +60
·C
TJ
Operating junction temperature range
-25 to + 150
·C
OJMB
Thermal resistance
4
·C/W
NOTE:
1. Pins 2 and 4 are externally connected to ground.
..
February 12, 1987
12-21
Signetics Linear Products
Product Specification
TDA3654
Vertical Deflection Output Circuit
DC AND AC ELECTRICAL CHARACTERISTICS
TA = 25'C, supply voltage (V9-4) = 26V, unless otherwise stated.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
Supply
V9-4
Supply voltage, Pin 92
V6-4
Supply voltage output stage
16+ 19
Supply current, Pins 6 and 93
35
14
Quiescent current 4
25
TC
Variation of quiescent current with temperature
10
40
V
60
V
55
65
rnA
40
65
rnA
mAl'C
-0.04
Output current
Is(p.p)
+Ia(p.p)
-Ia(p.p)
Output current, Pin 5 (peak-to-peak)
2.5
3
A
Output current flyback generator, Pin 8
1.25
1.35
1.5
1.6
A
A
60
V
Output voltage
VS_4
Peak voltage during flyback
V6-S(SAn
VS-6(SAn
V6- S(SAn
VS- 6(SAn
Saturation voltage to supply
at Is = -1.5A
at Is = 1.5As
at Is = -1.2A
at Is = 1.2As
2.5
2.5
2.2
2.3
3.2
3.2
2.7
2.8
V
V
V
V
VS- 4(SAn
VS-4(SAT)
Saturation voltage to ground
at Is = 1.2A
at Is = 1.5A
2.2
2.5
2.7
3.2
V
V
1.6
2.3
1.4
2.2
2.1
3
1.9
2.7
V
V
V
V
5
100
p.A
Flyback generator
V9-a(SAT)
Va-9(SAT)
V9-a(SAT)
Va- 9(SAT)
Saturation voltage
at la = -1.6A
at la = 1.5As
at la = -1.3A
at la= 1.2As
-Ia
Leakage current at Pin 8
VS_9
Flyback generator active IF
4
V
Input
11
Input current, Pin I, for 15 = 1.5A
0.33
0.55
V1_2
Input voltage during scan, Pin 1
2.35
3
13
Input current, Pin 3, during scan6
0.03
0.8
rnA
V
rnA
V3_2
Input voltage, Pin 3, during scan 6
V9_4
V
V1 _ 2
Input voltage, Pin I, during flyback
250
mV
V3 _2
Input voltage, Pin 3, during flyback
250
mV
V
Guard circuit
V7 _2
Output voltage, Pin 7, RL = 100kn9
4.1
4.5
5.5
V7-2
Output voltage, Pin 7, at IL = 0.5mA 9
3.4
3.9
5.1
V
RI7
Internal series resistance of Pin 7
0.95
1.35
1.7
kn
VS-2
Guard circuit activates 7
1.0
V
192
'C
General data
TJ
February 12, 1987
Thermal protection activation range
158
12-22
175
Signetics Linear Products
Product Specification
TDA3654
Vertical Deflection Output Circuit
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) TA = 25°C, supply voltage (V9_4) = 26V, unless otherwise
stated.
J
LIMITS
SYMBOL
PARAMETER
Min
Typ
I
Max
3.5
I
4
UNIT
Thermal resistance
OJMB
From junction to mounting base
PTOT
Power dissipation
Go
Open-loop gain at 1kHzB
33
fA
Frequency response, _3dB 1O
60
°G/W
see Figure 2
I
I
dB
kHz
NOTES:
1. Non-repetitive duty factor 3,3%,
2. The maximum supply voltage should be chosen so that during f1yback the voltage at Pin 5 does not exceed 60V.
When VS_4 is 13V and no load at Pin 5.
4. See Figure 3.
5. Duty cycle, d = 5% or d = 0.05.
3.
6.
7.
S.
9.
When Pin 3 is driven separately from Pin 1.
During normal operation the voltage VS- 2 may not be lower than 1.5V.
RL = sn; IL = 125mARMS
If guard circuit is active.
10. With a 22pF capacitor between Pins 1 and 5.
FUNCTIONAL DESCRIPTION
Driver and Switching Circuit
Output Stage and Protection
Circuits
Pin 1 is the input for the driver of the output
stage. The signal at Pin 1 is also applied to
Pin 3 which is the input of a switching circuit
(Pins 1 and 3 are externally connected). This
switching circuit rapidly turns off the lower
output stage when the flyback starts, and
therefore, allows a quick start of the flyback
generator. The maximum required input signal
for the maximum output current peak-to-peak
value of 3A is only 3V; the sum of the currents
in Pins 1 and 3 is then maximum 1rnA.
The output stage consists of two Darlington
configurations in class B arrangement. Each
output transistor can deliver 1.5A maximum
and the VCEO is 60V. Protection of the output
stage is such that the operation of the transistors remains well within the SOA area in all
circumstances at the output pin (Pin 5). This
is obtained by the cooperation of the thermal
protection circuit, the current-voltage detector, and the short-circuit protection. Special
measures in the internal circuit layout give the
output transistors extra solidity; this is illustrated in Figure 4, where typical SOA curves
of the lower output transistors are given. The
same curves also apply for the upper output
device. The supply for the output stage is fed
to Pin 6 and the output stage ground is
connected to Pin 4.
February 12, 1987
Flyback Generator
During scan, the capacitor between Pins 6
and 8 is charged to a level which is dependent on the value of the resistor at Pin 8 (see
Block Diagram). When the flyback starts and
the voltage at the output pin (Pin 5) exceeds
the supply voltage, the flyback generator is
activated.
The supply voltage is then connected in
series, via Pin 8, with the voltage across the
12-23
capacitor during the flyback period. This implies that during scan the supply voltage can
be reduced to the required scan voltage plus
saturation voltage of the output transistors.
The amplitude of the flyback voltage can be
chosen by changing the value of the external
resistor at Pin 8. It should be noted that the
application is chosen such that the lowest
voltage at Pin 8 is > 1.5V during normal
operation.
Guard Circuit
When there is no deflection current, for any
reason, the voltage at Pin 8 becomes less
than 1V and the guard circuit will produce a
DC voltage at Pin 7. This voltage can be used
to blank the picture tube so that the screen
will not burn in.
Voltage Stabilizer
The internal voltage stabilizer provides a
stabilized supply of 6V to drive the output
stage, so the drive current is not affected by
supply voltage variations.
II
Product Specification
Signetics Linear Products
TDA3654
Vertical Deflection Output Circuit
TDA3654
C8
R11
110nF
R12
560
Uk
R6
VERnCAL DRIVE
470
(FROM PIN 1 TDA2578A)
VERnCAL
DEFLEcnON
COILS
+26V
R2
RIO
620
+
Rl
Cl
R4
Figure 1. Application Diagram
80
20
I INFINITE HEATSINK
I
16
I
~ 12
j
"'r-.
\
HEATSINK I
8"C/W
I
N-...
80
IIII
I
100
,
\
,\
o
160
o
10
30
20
Vee = Vg_ 4 (V)
I---
..... :...-- .....
40
so
Figure 3. Quiescent Current as a Function
of the Supply Voltage
Figure 2. Power Derating Curve
February 12. 1987
,.- ~
MI~
-I!---
20
-
.,./
po
TYP
~\
I
n-t-I-Ll
o
--
\
"i- ,
NO HEATSINK I
o
,.- /
~
12-24
Signetics Linear Products
Product Specification
TDA3654
Vertical Deflection Output Circuit
CURVE
1
2
3
4
5
6
7
6
9
'.
0
DC
10ms
10ms
1ms
lms
lms
lms
O.2ms
O.2ms
0.5
0.25
0.5
0.25
0.05
0.05
0.1
0.1
10
PEAK
JUNCTION
TEMPERATURE
ICSM
150'C
150'C
r-
1234567-
89
0..,
ICRM
150"C
150"C
150'C
150"C
160'C
150'C
160'C
~~
0.5
0.1
1
100
Figure 4. Typical SOA of Lower Output Transistor
•
February 12, 1987
12·25
Signetics
Section 13
Videotex/Teletext
Linear Products
INDEX
AN153
AN154
SAA5025
SAA5030
SAA5040
SAA5045
SAA5050/55
SAA5230
SAA5350
AN152
The 5-Chip Set Teletext Decoder ...........................................
Teletext Decoders: Keeping Up With the Latest Technology
Advances..........................................................................
Teletext Timing Chain for 525-Line System ...............................
Teletext Video Input Processor ..............................................
Teletext Acquisition and Control Circuil.. ..................................
Gearing and Address Logic Array for USA Teletext (GALA) .........
Teletext Character Generator .................................................
Teletext Video Processor ......................................................
Single-Chip Color CRT Controller (625-Line System) ...................
SAA5350: A Single-Chip CRT Controller ...................................
13-3
13-8
13-14
13-25
13-32
13-44
13-48
13-61
13-67
13-89
•
Signetics
AN153
The 5-Chip Set Teletext
Decoder
Application Note
Linear Products
Author: D. S. Hobbs
SYSTEM REQUIREMENTS
The current 525-line (modified U.K.) Teletext
system differs in a few respects from the 625line system for which the U.K. chip set was
designed. These are:
(a) Data Rate 5.727272Mb/s.
(b) Data bytes per data line 32.
(c) Gearing bit system for routing data to
RAM.
(d) Approximately 200 display lines available
for text with normal raster geometry.
These are catered for in the decoder described below so that the 625-line chip set is
presented with signals which it can interpret
correctly and provide a suitable display for
general use.
Data Rate (a) and (b)
(a) To accomodate the lower data rate the
clock coil and tuning capacitor in the
SAA5020 video input processor circuit
are redesigned.
(b) The write enable (WOK) signal from TAC
(SAA5040) to the RAM is limited to 32
data bytes in GALA.
Gearing Bit System (c)
This is accomodated in the Gearing and
Address Logic chip (GALA). Since 40 characters per row are displayed, whereas only 32
are transmitted per data line, a routing system
is used to position character data in RAM as it
is received.
The left hand part of the display is built up by
32 byte rows of data positioned in RAM by
transmitted ROW addresses. The right hand
side of the display is 'filled-in' by 4 sequential
groups of 8 characters sent as one data line
but stored in RAM as the last 8 bytes of 4
sequential rows. A gearing bit in the magazine
number/row address group (see Table 1) is
set to 'I' if fill-in information is being transmitted and to '0' if left hand rows are sent. The
ROW address of the data line containing the
gearing bit set to 'I' determines the starting
ROW number for the fill-in operation. For
ROW zero start, a ROW address for ROW
February 1987
number 1 is employed since ROW zero can
only be used for header information. The
presence of the gearing bit set = 1 together
with ROW address number 1 is detected in
GALA.
From Table 1 it will be seen that the gearing
bit occupies the position occupied by the
most significant bit of the magazine number in
the 625 system. In order to allow the Teletext
Acquisition Chip (TAC, SAA5040B) to acquire
data from such lines the gearing bit is detected by GALA and converted always to
zero. This preserves the magazine number as
that set by the two least significant bits. The
number of magazines available using the
present decoder is 4. (Subsequent development of new chip sets will allow expansion of
these by using header coding at present
deSignated as time coded page information
and detected as such by the 625-line TAC).
Display Compression (d)
In order to allow the display of 40 characters
per row and 24 rows on a 525-line raster, a
compression technique has been developed
which only requires 192 active TV line pairs
(interlaced). The character shape is essentially unchanged from the 625-line set but the
row timing is now only every 8 TV lines
instead of every 10. This is achieved using a
special 525-line standard timing chip
(SAA5025D), to drive the same TRaM
(SAA5050) as is used in the 625-line decoder.
DECODER BLOCK SCHEMATIC
Figure 1 shows the basic decoder elements in
block form, made up of dedicated chips
SAA5025D,SAA5030,SAA5040B, SAA5045
(GALA) and SAA5050 together with RAM.
These are divided into functional areas to
simplify the decoder description. Only the
most important interconnections are shown in
order to reduce complexity.
Inputs to the system are the video input to the
Video Input Processor (VIP) and remote control signals (see Appendix' A'), to (TAC) and
(TRaM).
13-3
Outputs consist of R, G and B, blanking, Y
and superimpose control. These allow flexible
interfacing with the TV set video drive system
(see Appendix B).
Video Input Processor
(SAA5030)
This chip (VIP) performs mainly analog functions concerned with extracting the data signal from the TV set video and presenting it in
a suitable form to the Teletext Acquisition
Chip (TAC, SAA5040B).
VIP also provides a phase-locked crystal
oscillator at 384MHz horizontal line rate, i.e.,
6.041957MHz. This frequency is divided
down in the Timing Chip (TIC, SAA5025D) to
produce all the line- and field-related timing
waveform locked to the input video sync
pulses. As ancillary to this function, VIP
includes a sync separator to provide field rate
sync to TIC.
Data is sliced in VIP by an adaptive slicer
referenced to peak detectors. This is followed
by Data Clock regeneration in a DC circuit. A
data latch driven internally supplies latched
data, correctly phased with the Data Clock, to
TAC.
Gearing and Address Logie
Array (GALA) SAA5045
Due to the system differences between 525and 625-line Teletext, the data from VIP must
be modified before it is presented to the
Teletext Acquisition Chip (TAC, SAA5040B).
The presence of a gearing bit set to 'I' or '0'
is detected in GALA and the data is delayed
for one byte period in a shift register. This
allows the inversion of the gearing bit, if
required, to avoid confusion in the decoding
of the magazine number (see paragraph on
Gearing Bit System).
GALA includes a bistable which is set or not
set, according to the state of the gearing bit.
This is held for the duration of each data line
and reset before the next. Also included in
GALA are RAM address and read/write control functions.
•
Application Note
Signetics Linear Products
AN153
The 5-Chip Set Teletext Decoder
Table 1. Data Line Coding for 525-Line Teletext (U.K. Modified) System Characteristics Current for
Operating Systems 1982
CLOCK RUN IN
ICLOCK RUN IN IFRAMING CODE
MAGAZINE AND ROW ADDRESS
DATA
DATA
1 0 1 0 1 0 1 0 11 0 1 0 1 0 1 011 1 1 0 0 1 0 0
P 20 P 21 P 22 P 20 P 21 P 22 P 23 P 24 Do D1 D2 D3 D4 D5 D6 D7 Do
~
~
Cl
c:
DATA RATE 5.727272Mb/s
(364 H = 8/5 COLOR SC)
DATA PERIOD = 174.6ns
H PERIOD = 63.551's
32 BYTES DATA/LINE
32/8 SYSTEM 24 ROWS 40 CHARACTERS
E
E
.~
·E
Cl
E
'"~ g ffi
·E l2'
.~
Cl
E
.§
Cl
.~
g
'" ::;;'" J:'" ::;;'" J:'" " J:'"
J:
~
"0
"0
Cl Cl
Cl Cl Cl
~
Cl Cl
~
Operation Normal As For 625
Except Write RAM ENABLE (DATA)
Limiled To 32 Bytes_
Conversion
Coding When
Gearing Bit = 1
REMOTECTL.
D--r----
0
LO
~
ffi
.5
RECEIVER
VIDEO lIP
DISPLAY
2.8Ypp
INTERFACE
TIMING
CONTROL
Figure 1. S-Chlp Decoder Block Schematic
February 1987
LO
'" '" ...
iii ffi
~ ~ "
>
.5 .5 .5
~
f - - - Start CRI 9.5 Microsec. From Sync 0
(Operation Normal As For 625)
...
'"
'"
(!l
iii
KEYPAD
g
~
II)
II)
13-4
Cl
Application Note
Signetics Linear Products
The 5-Chip Set Teletext Decoder
Teletext Acquisition and Control
(TAC, SAA5040B)
Data from GALA is clocked into TAC, by the
data clock (5.727272MHz), where it is decoded byte-by-byte to provide character and
control data for the storage in RAM. Row
addresses are decoded after Hamming
checks and issued to the RAM address
system. A column address clock for writing
into RAM during data lines (WACK) is also
generated at byte (character) rate. Parity
checking is carried out to produce write
enable pulses (WOK) for each correctly received character to be written into RAM.
Header (row zero) information is also decoded and Hamming checked in TAC so that
only the data relating to the page called up by
the remote-control system (Key Pad input of
required page number) is written into RAM.
Clearing functions are also controlled by
Header and Remote Control input data, to
clear the RAM.
Selected page number information is written
into RAM by TAC during an unused TV line
between the end of data entry (DEW) and the
start of the text display period. When doubleheight characters are requested (via remote
control), TAC issues commands to the timing
chain (TIC) and display device (TRaM). Similarly, the system controls for TEXT or TV or
MIXED (Text + TV), are issued by TAC as
picture ON (PO) and display enable (DE) to
VIP and TRaM.
Timing Chain (TIC, SAA5025D)
The timing of line and field rate functions
together with display dot clock are derived
from the VIP crystal oscillator (6.041957MHz)
signal fed to TIC. This ·signal is counted down
to line rate (+384) and field rate, phaselocked to the incoming TV syncs. A composite sync waveform (AHS) is also generated
which free-runs (under crystal control) to
allow display of text to continue after the TV
signal has ended. This is known as 'afterhours sync'.
Row addresses for the display period are
generated in TIC (Ao through AI) together
with a column count (character rate) clock
(RACK). The row addresses are stepped from
zero to twenty-three at one-eighth of TV line
rate, giving 24 rows at 8 lines/row in each
field (60 fields/sec). This address information
for reading RAM is multiplexed with the writing address information under control of a
field rate signal generated by TIC, called
DEW or data entry window. This is timed to
occur on TV lines 10 through 19, inclusive,
which are the lines in the vertical interval
during which data is accepted. The DEW
signal controls data entry in TAC, and also
the address tri-state switches.
February 1987
AN153
Signals fed back from TIC to VI P are used to
reset the data slicer system and to enable
rapid phase-locking of the crystal oscillator. A
buffered dot rate clock at crystal frequency is
issued by TIC to drive the display generators
in TRaM. The display area on the TV raster is
controlled by the LOSE (load output shift
register enable) signal from TIC which occurs
on all active text lines.
When double-height characters are called up
by control signals from TAC, originated at the
Key Pad, the row addresses are stepped at
half-rate and the top or bottom of the display
is selected by the T /B signal. This resets the
row address counter in TIC to start at row
zero, or twelve of the text display.
Address Logic (GALA)
The address logic in GALA contains column
address counters for the character rate address generation, a multiplexer for address
combining, and an address latch/step function for the gearing system. Since the teletext
address structure for transmission and display contains five row address bits and six
column address bits, these must be reduced
to a total of ten bits to suit conventional RAM
structures. This is achieved in GALA by
multiplexing the row and column addresses.
During the input of data lines, containing a
gearing bit set to '1', a multiplexer causes the
row address to be indexed every 8 bytes. The
multiplexer is transparent to addresses during
data lines containing a gearing bit set to zero.
The row addresses from TAC go to the GALA
and are multiplexed with the display row
addresses under control of DEW, by tristates
in TIC and TAC.
Random Access Memory (RAM)
Character data from TAC is stored in a page
display memory with a capacity of 1024 8-bit
bytes. Of these, only 960 bytes of 7-bit length
are actually used. Data is written in during
acquisition from TAC and read out during
display to TRaM, under control of write
enable and chip select signals, generated
from the WOK and DE signals from TAC via
GALA. A common input/output bus structure
is used in the devices employed in this
decoder. Conflict of signal direction is avoided in the WOK/DE gating arrangement in
GALA.
Display Compression (50250)
The drive signals from TIC (5025D) to TRaM
during the display period are organized so
that suitably-shaped characters are generated by TRaM on an 8 TV line pair per row
basis. Since TRaM is primarily intended for
10 line pairs per row operation, it is necessary
to provide effectively 10 drive pulses per row
per field, although output dot data is only
required on eight of these in each field. The
compression logic in TIC (5025D) inserts
additional step pulses during the horizontal
13-5
sync interval to keep the internal counters in
TRaM in the correct sequence. A further
operation included is the blanking of the
display during the same period to avoid spurious 'dots' on the TV tube. Character rounding
normally employed in the TRaM character
generator is also controlled to obtain the
best-shaped 'compressed' characters.
Teletext Read Only Memory
(TROM, SAA5050)
This device contains the read only memory
and character generating system which produces the text display (and graphics) characters. It is controlled by direct input remotecontrol signals (Key Pad-originated), and by
transmitted controls via TAC. Timing of the
display system is controlled by signals from
TIC, and the actual display data is read in
from the page memory RAM.
Output signals for R, G, B, Y, Blanking and
superimpose are available by open-collector
transistor output buffers. These are interfaced
to the regular TV video drive system via 75n
emitter-followers in this decoder. However, it
is simple to obtain outputs at different impedance levels by the emitter-follower input/
output components or by substituting TIL
buffers with input pull-up resistors. Interfacing
will differ for different setmakers, but the 75n
1V p.p system is flexible in allowing long
connections between the decoder and the
video circuits of the TV.
FUNCTIONAL LOGIC
INTERCONNECTION SCHEMATIC
The complete decoder is built on a doublesided PCB with Molex 0.1" pitch plug connectors. Supplies required are 150mA at 12V and
250mA at 5V ± 5%. The supply rails are
decoupled by distributed discrete 100nF capacitors not shown on the circuit diagram.
PCB layout is only critical in the analog area
surrounding VIP where connections must be
kept short and ground paths sensibly routed.
Good video frequency practice is followed in
this area to ensure minimum radiation of
interference and suppression of local oscillatory effects.
VIP Circuit
IC4, the SAA5030 device, has a number of
discrete resistors and capacitors connected
to it to define operating levels and frequencies. Tuning capacitors C17, CIS, CIS, C12,
and C13 should all be of high-grade RF tuning
types. The crystal
is of similar grade to a
color sub-carrier crystal in that it needs good
setting stability with the possibility of being
'pulled' by about ± 750Hz for phase-locked
operation.
xn
The center frequency is 6.041957MHz when
series-connected with a load capacitance of
30pF. Capacitor C17 and coil L2 form a
•
Application Note
Signetics Linear Products
The 5-Chip Set Teletext Decoder
rejector circuit to avoid oscillation outside the
correct frequency range of the crystal.
Inductor L1 and capacitor C15 form the data
clock recovery-tuned circuit. A coil Q-factor of
greater than 50 is essential for good clock
recovery. A component with an unloaded Q of
90 is commonly employed. The clock coil is
tuned on test by applying a video signal at Pin
3 of PL3 containing data lines with pseudorandom data at 5.727272MHz preferably
throughout the normal display period for ease
of observation on an oscilloscope. This
should be connected to Pin 18 of VIP.
The coil is adjusted for minimum jitter of the
clock falling edge, which should occur approximately at the center of the 'eye' pattern
formed by syncing the source data on another trace of the oscilloscope. For best results,
it is preferable to trigger the oscilloscope from
the data clock of the generator used to form
the test data.
Phase-Locking Adjustments For Sync
The series-tuning capacitor, C19, is used to
adjust the center frequency of the crystal
oscillator which determines horizontal (line)
frequency phase-lock, whereas R10 is adjusted for field sync lock.
The crystal circuit is adjusted first while observing an input video signal at Pin 3 of PL3,
together with a line frequency signal such as
that on VIP Pin 5 (,sandcastle waveform').
Connecting Pin 1 of VIP directly to the 12V
rail allows the oscillator to free-run, and
shunting the filter capacitor C1 with a 5.6M.I1
resistor gives a preferred initial offset. C19 is
then adjusted to obtain a stationary relationship between the two signals. The test connections on Pin 1 of VIP and C1 should be
removed when the two waveforms are to
remain solidly locked in phase.
Field sync adjustment can then be carried out
by adjusting R10 while observing the output of
(FS) at Pin 13 of VIP together with the field
February 1987
AN153
sync of the incoming video. When correctly
adjusted, the rising edge of (FS) should be
half-way along the second broad pulse of the
field sync pattern of the input video. This
adjustment is important to ensure the correct
selection of data lines in the vertical interval
by the DEW signal. Field lock in the wrong
position may cause the loss of one or more
data lines.
The adjustments of the decoder are now
complete; all subsequent areas of operation
are controlled by digital systems.
Input and Output Requirements of VIP
The video input from the TV should be
2.8Vp.p at Pin 3 of PL3 and its DC level notp.p
greater than 7V. If higher, the electrolytic
capacitor C5 (lI'F) may be reverse-biased
and cause maloperation of the DC restoration
circuit in VIP.
Sync Output Signals
The TV set may be synchronized via VIP if a
synchronized display is required from AHS
when the TV signal disappears. This is obtained from Pin 2 of PL3. The polarity can be
set by connecting resistor R1 (1.5k.l1) via link
(LPI) to + 12V or OV for negative- or positivegoing syncs, respectively.
TAC (SAA5040B)
Data from GALA is clocked into TAC Pin 2 by
the data clock at Pin 3, and also, from GALA.
When correct data is received write enable
pulses are issued from Pin 15 (WOK). This is
an indication that Hamming codes and parity
are correct. Data is output in parallel from
Pins 16 through 22 to RAM, while row address Ao through A4 are supplied by Pins
23 -27.
Internal Data Writing to RAM
Selected page numbers, called up by the
remote-control Key Pad input, are written into
the row zero position in RAM, together with
indications such as 'HOLD' and timed-page
'time'. This function occurs during TV line
13-6
number 37 only. At this time the display
enable (DE) output Pin 9 is held low and WOK
pulses are emitted at Pin 15 in two groups of
8, corresponding to the first and last eight
character spaces in row zero. Since this
function occurs outside of the DEW period,
the column counters are driven by read address pulses (RACK) from TIC.
Character Generator, TROM
(SAA5050)
The character generator IC, (SAA5050) receives data from RAM during the display
period (TV lines 48 to 239, inclusive) and
internally decodes the data to generate characters or control functions. TROM receives
direct remote-control information on Pins 3
(DATA) and 11 (DUM) which control such
functions as MIX (TV + text), and conceal!
reveal.
Control of display onloff (DE) and doubleheight are received from TAC on Pins 28 and
15, together with picture-on (PON), Pin 27.
TROM outputs control signals to TIC from Pin
16 when 'Transmitted Large Characters'
(TLC) are called up by transmitted data
codes.
The video output of TROM consists of R, G
and B signals at Pins 24, 23 and 22 (opencollector) and a Y Signal, Pin 21 (opencollector). Blanking is obtained at Pin 25
(open-collector) to switch the TV video on
and off under control of Signals decoded in
TROM.
Superimpose signals from Pin 2 are used to
modify the contrast setting of the TV video
when MIX mode is called up (by remotecontrol or News Flash). This output Pin must
be connected via a pull-up resistor of 1Ok.l1 to
the + 5V rail, whether its output is used or not.
The R, G, B, Y and Blanking output buffers
will drive interface circuits directly, if required,
provided that the open-circuit output voltage
does not exceed 13.2V maximum.
Signetics Linear Products
Application Note
The 5-Chip Set Teletext Decoder
AN153
~
i-f.r·"
1-flJ "
i-fJ
~~I'N
TROMOUTPUT
POWER
525·Llne 5·Chlp Decoder
February 1987
13·7
Signetics
AN154
Teletext Decoders: Keeping Up
With the Latest Technology
Advances
Linear Products
Author: Nabil G. Damouny
Application Note
bidirectional lines: the Serial Data (SDA) line
and the Serial Clock (SCl) line.
ABSTRACT
The new generation teletext decoder, unlike
its predecessor introduced in 1976, is user
programmable under the control of a general
purpose microcomputer or microprocessor.
The new decoder is programmable to operate
in the Vertical Blanking Interval (VBI) or full
field teletext mode of operation. It can, simultaneously, acquire multi-pages resulting in a
much faster system response time.
The new teletext decoder is 12C bus controlled; therefore it is easy to integrate into
any digitally-controlled 12C bus system. The
modular nature of the 12C bus architecture
allows the system deSigner to add to or
delete from his or her system various function
blocks. The teletext decoder can be treated
as one of these blocks.
INTRODUCTION
Integrated Circuit (IC) technology has
marched a long way since the advent of the
first generation teletext decoder in 1976.
Some improvements and new features can
now be economically incorporated in the
second generation decoder while keeping the
chip count even lower than its first generation
counterpart.
The new generation teletext decoder is microcomputer (or microprocessor) controlled.
It is user programmable and therefore more
flexible and friendlier to use. Today, virtually
every system is microprocessor controlled.
The microprocessor controls various special
purpose peripheral chips, each controlling
one or more functions of the overall system.
One of these peripheral chips can control the
television tuning function while another chip
can control the teletext acquisition and display function. The system can be designed in
a modular fashion so that modules performing different functions can be added to or
deleted from the system with minimal effort.
The Inter-IC (12C) bus has been designed to
achieve modularity. Bus interfacing problems
are eliminated by integrating all the necessary
bus handshake logic in the on-Chip silicon.
The 12C bus is a serial bus consisting of two
THE NEW GENERATION
TELETEXT DECODER
The new generation teletext decoder consists
of a super data slicer (the Video Input Processer - VI P), the teletext controller chip, multipage memory, and a general purpose microcomputer (see Figure 1):
The microcomputer communicates with the
teletext controller via the 12 C. The microcomputer can be either a master or a slave; the
teletext controller chip is a slave-only device.
The new teletext controller is an 12C peripheral and belongs to the large "CLIPS" family.
The new 12 C teletext decoder can be integrated in a system where a single microcomputer
is used. The microcomputer is the only master and controls other system functions in
addition to the teletext decoder, simultaneously (see Figure 2). On the other hand,
since 12C bus concept allows modularity, a
multi-master system can be easily implemented (see Figure 3).
In the single master system, the system
designer should allow for possible future
software (and, consequently, memory) expansion. This is necessary to allow future system
expansion. In the multi-master case, only one
microcomputer is shown to receive and decode remote control commands. This microcomputer will then communicate the different
commands to other microcomputers via the
12C bus.
Microcomputers with built-in 12C bus interface
are available today. The instruction set is
based on that of the industry standard 8048
microcomputer family.
The New Teletext Decoder
Acquisition Circuitry
The teletext decoder accepts as input a
composite video baseband signal. This signal
is readily available in a TV set (to be discussed later). Digital data is inserted in the
Vertical Blanking Interval (VBI) or into, virtually, all available TV lines (full-field). The acquisition Circuitry can be programmed to operate
in the VBI or in a full-field mode. Full-field
teletext is a useful feature contributing to a
very fast system response time but, obvious-
1984 IEEE Reprinted with permission from IEEE
transactions on Consumer electronics Volume CE-
30, Number 3, page 429-436, August 1984
February 1987
13-8
Iy, does not permit any video information to
be transmitted.
Since high-speed teletext digital data (data
rate is 6.93MHz in Europe and only 5.72MHz
in North America due to bandwidth limitation)
is transmitted via broadcast information, a
high performance data slicer is essential to
have at the receiving end.
The video input processor should have good
data slicing capability in the presence of
echoes, noise, and co-channel interference.
The device should provide compensation for
high-frequency losses and be able to regenerate the clock from the digital data. The
digital data can have different rates, as mentioned above. Other desirable features that
the video input processor might have include:
providing a mechanism by which it is easy to
lock to a VCR; having a minimal number of
external components/adjustments required;
being able to accept many levels of peak-topeak amplitudes of the composite video input; and last, but not least, consuming low
power.
Digital data and its associated clock (Figure
4) can now be presented by the video input
processor in a nice clean form to the teletext
controller chip.
The teletext controller is looking for the page
addressing information, imbedded in the page
header - row number 0 - to find a match
with the prespecified page number requested
by the user via the remote control keypad.
When a page address match is found, this
page is captured and stored in page memory.
In order to speed up the system response
time and to make it friendlier to use, the
acquisition circuitry is designed to capture
four teletext pages simultaneously. Four independent acquisition circuits co-exist on the
teletext controller and are able to capture four
pages simultaneously. The four acquired
pages can be specified, by the user program,
to be the requested page plus the next three
sequential pages or the requested page plus
the next three linked pages as specified by
the linking information received in ghost row
number 27.
The teletext controller can then support up to
8k bytes of memory. " ghost rows are to be
received and decoded for, 2k bytes of memory will be needed per teletext page.
Signetics Linear Products
Application Note
Teletext Decoders: Keeping Up
With the latest Technology Advances
AN154
VIDEO
INPUT
r-----,
I
I
I
I
I
I
I
I
RGB
I
IL _ _ _ _
It is worth noting that the fixed format, World
System Teletext, is virtually error free. This is
due to the simple fact that a one-to-one
correspondence exists between transmission
codes, acquisition memory, display memory,
and the actual display position on the screen.
Due to the fact that teletext information is
being constantly cycled through the system,
an error received during one cycle can be
automatically corrected during a subsequent
cycle.
The New Teletext Decoder
Display Circuitry
~
REMOTE CONTROL
HANDSET
Figure 1. Computer-Controlled Teletext (CCT) Decoder Block Diagram
Since four pages can be acquired and stored
in the acquisition memory simultaneously, but
only one page can be displayed at a time, a
display chapter register, residing on the teletext controller chip, is user programmable to
select which acquired page is to be displayed.
The display memory is, physically, the same
as the acquisition memory. Ghost rows are
not displayable and the display consists of 25
rows, (the 25th row contains locally generated status information), 40 characters each.
The character cell occupies a 12 X 10 dot
matrix, giving nicely shaped characters at
12MHz dot rate. The display could be interlaced or non-interlaced.
There are four control functions that can be
individually turned on or off under user software control. These are: TV picture, text,
background, and contrast reduction. Boxed
text information in a TV picture can be displayed by specifying the "Start box", "End
box" control characters.
Figure 2. Centralized Control Structure
l2Csus
TO OTHER
r--------
MODULES
I
I
I
--------,
I
I
L ________________
I
~
The teletext controller provides RGB outputs
as well as a blanking output and a contrast
reduction output. These outputs can be used
as they are or a video buffer stage can be
added (see Figure 4). This stage consists of
emitter followers and clamping diodes. The
diodes clamp the upper voltage values to a
potential suitable for the particular TV receiver's contrast control. The blanking output is a
combined box and dot blanking (full screen).
The contrast reduction output is used for
implementing more readable mixed (text over
video) displays or to implement subtitles in
reduced contrast boxes.
If a composite video display is desirable, a
single chip multi-standard color encoder is
available to produce PAL or NTSC compatible displays.
TELETEXT DECODER MODULE
Figure 3. Distributed Control Architecture
The new acquisition circuitry can be programmed to receive the normal 7-bit plus one
parity bit or 8-bit byte data. This is useful
when a more sophisticated error correction
scheme (such as CRG) needs to be implemented. The 8-bit mode is also instrumental
February 1987
in implementing the "telesoitware" concept.
Through telesoitware, computer programs
can be down-loaded and acquired as teletext
information.
13-9
It is important to note that the new teletext
decoder provides a secure means to synchronize the incoming video with the resulting
text/video display. In addition, the decoder
generates a composite sync signal that is
suitable for driving the display time base;
•
Signetics Linear Products
Application Note
Teletext Decoders: Keeping Up
With the Latest Technology Advances
AN154
THE 12C BUS - GENERAL
CONCEPT
Many system applications do not require very
fast data transfer offered by the traditional
parallel schemes.
As shown in Figure 5, a typical microcomputer-controlled television receiver using a parallel bus type architecture implies a large
number of interconnects, devices with a large
number of pinouts and a bigger layout area.
Since many applications do not necessarily
need the speed offered by parallel bus type
architecture, an economical, easy to implement solution can be used. Figure 6 depicts
the television receiver block diagram designed around the 2-wire 12 C serial bus.
VIDEO
INPUT
PROCESSOR
Figure 4. Teletext Decoder - Detailed Block Diagram
Many devices have been implemented with
on-chip 12C bus interface logic. These devices
communicate through the 2-wire serial bus.
The system designer will no longer worry
about the communication interface between
the different blocks in his or her system and
can now concentrate on the more important
issues: the function/system requirements.
Devices with built-in 12C bus interface can be
added to or· deleted from the system by
simply "clipping" them to the common 2-wire
bus. The only limitation is the bus capacitance of 400pF. Hence a collection of these
devices is known as "CLIPS".
The 12C bus consists of 2 bidirectional lines,
the Serial Data (SDA) line and the Serial
Clock (SCl) line. Devices with built-in 12C bus
interface can be implemented in any technology, i.e., NMOS, CMOS, 12 l, TIL, etc. These
devices are connected together (wired-AND)
to form an 12C bus-based system, provided
that they all exhibit an open collector output
at each of their respective SDA and SCl
lines.
Figure 5. Conventional Microcomputer Controlled TV Receiver Block Diagram
The 12 C bus concept allows a flexible master/
slave relationship. to exist. A device master
during the present bus cycle can be a device
slave during the following bus cycle.
An 12C bus cycle starts with a START condition (see Figures 7 and 8). A 7-bit device
(slave) address is then sent followed by a
single bit to determine the direction of the
data transfer. A ninth clock pulse is then
generated by the master device to allow the
addressed receiver to acknowledge reception
of this byte. Now any number of 8-bit data
transfers can take place with the receiver
acknowledging each byte after it has been
received. At the end of the data transfer, the
device master generates a STOP condition.
The 12C bus USeS the wired-AND concept to
achieve clock synchronization and proper
arbitration between different device masters
in the system. If two device masters start
bidding for the bus simultaneously by generating the start condition, they will both be
February 1987
SDA
.c
SCL
I 11-'
KEYBOARD
REMOTE
CONTROL II
DECODER
___ J
Figure 6. Block Diagram TV Receiver 12C Based
driving the SDA and the SCl lines. Clock
synchronization is easily achieved through
the wired-AND connection. The resulting
clock will have a lOW period determined by
the device master with the longest clock lOW
period. The HIGH period of the resulting clock
is determined by the device master with the
shortest clock HIGH period.
13-10
Arbitration procedure in an 12C bus system is
also easy to implement. Keep in mind that all
devices are wire-ANDed and that a master
device driving the SDA line will sample that
line during the same clock period. In Figure 9
master device 1 is driving the data line HIGH
but the resulting SDA line is lOW (due to
master device 2) and so transmitter 1 loses
Signetics Linear Products
Application Note
Teletext Decoders: Keeping Up
With the latest Technology Advances
arbitration, after detecting that condition, and
prepares itself as a slave that could be
addressed during this very same cycle. Note
that no time is wasted for the arbitration
procedure since both address and data information is used to determine the winning bus
master.
It is very comforting to know that all of the
functions above have been implemented on
all of the "CLIPS" peripherals. This allows
system designers to implement modular ar·
chitectures and build systems around the
various available function blocks. Each function block, in its simplest form, can be one of
the "CLIPS" peripherals.
AN154
In Figure 10, the digital portion of the TV
chassis is depicted to be 12C controlled.
Some of the function blocks can be imple·
mented with a single chip belonging to the
"CLIPS" peripheral set. For example, the
tuning function, as well as controlling the
various analog signals, is implemented using
one of the "CLIPS" peripherals. Non·volatile
serial memory devices (1 2C bus compatible)
as well as LCD display drivers are readily
available and can be, as explained earlier,
clipped to the 12C bus.
11
1
Teletext Decoder as a Set-Top
Adapter
Teletext service can be incorporated in exist·
ing TV receivers through the addition of a set·
top adapter. The set·top adapter concept is
familiar through the use of the CATV cable
converter boxes. The set·top adapter con·
cept will offer the average consumer teletext
and cable TV service as well as a remote
control feature. This is true even though his or
her existing TV is, at present, not remotely
controlled.
11
1
8
11
111
~··~·~·~·~---------4·+··--·I~·~·~··----~r'~'~I~'------'r'~'~I~'~'~1
NUMBEROFl
BITS
7
8
~1-s~I-S~--VE-A-DD-R-ES-s~I~--~I~A-rI-D-~-A-r1-A~I-D-A-~-rl-A~I-p-'I
TELETEXT DECODER - SYSTEM
INTEGRATION
TV Receiver With Built-In
Teletext Decoder
Teletext decoders, in general, can be easily
integrated into TV receivers. In reality, TV
receivers can be considered a natural home
to house teletext decoders. The input to the
teletext decoder is composite video, base·
band signal which is already available at the
output of the demodulator stage in a typical
TV receiver (see Figure 10). The output of the
teletext decoder consists of RGB signals,
blanking and contrast reduction/control signals. The signals are of open·collector type
and can be easily manipulated. A simple
video output circuit might be needed at the
output of the teletext decoder, the purpose of
which is to provide the buffer/drive capability
and the appropriate voltage level control
suitable for the TV receiver under consideration. These signals can then be combined
with the existing RGB and contrast control
Signals available at the output of the TV video
amplifier stage.
S=START
A = ACKNOWLEDGE
P=STDP
Figure 7. Typical 12 C Data Transfer
,...,
"---A ..A..-J
I I
DATA OUTPUT I
BY RECEIVER I
SCL FROM
MASTER
l I
M
i 8,\..-.1,---..,---..
\J ~
1
2
,"_oJ
START
CONDITION
"----/
r:-\
__ - f
r:-\
8 " - - / _9 " -
I
CLOCK PULSE
FOR
ACKNOWLEDGEMENT
Figure 8. Acknowledgement on the 12C Bus
TRANSMmER 1 LOSES
ARBITRATION
DATAl =SDA
--------------
DATA 2
SDA
SCL
Figure 9. 12C Bus Arbitration Procedure of Two Masters
February 1987
r
--~
I
I
/
DATAl
v--v-_-_"VI
DATA OUTPUT BYj"\ I /
TRANSMITTER i \.~.I-,,_,-_ _ _
13-11
•
Signetics Linear Products
Application Note
Teletext Decoders: Keeping Up
With the Latest Technology Advances
Figure 11 depicts a set-top adapter block
diagram. The switch can be used to inhibit the
teletext feature, if necessary. On the other
hand when switching at high speed, this
switch can be used to implement a superimposed text over video feature.
AN154
SUMMARY
The newly introduced teletext decoder is
discussed. The decoder is microcomputercontrolled so it is user-programmable. The
teletext controller chip belongs to the diversified number of 12C bus peripherals, known as
"CLIPS", and therefore can be easily integrated in an 12C bus controlled digital system.
The new decoder performs well under poor
signal conditions, it can work in either VBI or
full-field mode, it offers an easy, effective way
to implement the "telesoftware" concept, it
can acquire multi-telatext pages simultaneously resulting in a fast system response
time and is capable of displaying interlaced or
non-interlaced type displays. In addition to all
of the above, the new teletext decoder is
RFAGC
FILTER
BAND
AUDIO
SOUND
IF,
DEMODULATOR
VIDEO
SELECTION
AND
llJNING
VOLTAGE
VIDEO
DETECTOR,
AMPUFIER
HORIZONTAL
AND VERTICAL
TIME BASE
PLUS RASTER
CORRECTION
Figure 10. TV Receiver Block Diagram
TO T.V.
RECEIVER
Figure 11. Teletext Set-Top Adapter
February 1987
13-12
Signetics Linear Products
Application Note
Teletext Decoders: Keeping Up
With the Latest Technology Advances
easy to integrate into a TV receiver or as a
set-top adapter.
REFERENCES
1.
AN154
2.
LSI Circuits for Teletext and Viewdata,
Mullard Technical Publication M81-0001,
1981.
3.
4.
"12C Bus Specification", Signetics Corporation, 1984.
Computer Controlled Teletext, User Manual, N.V. Philips, 1984.
Basic Television - Principles and Servicing, Grob, McGraw Hill, 4th Edition .
•
February 1987
13-13
SAA5025
Signetics
Teletext Timing Chain for USA
525-Line System
Product Specification
Linear Products
DESCRIPTION
The SAA5025 is aMOS N-channel integrated circuit which performs the timing
functions for a Teletext system. It provides the necessary timing signals to
extract data from a memory and produce
a display according to the USA 525-line
television standard (system M).
The SAA5025 may be used in conjunction with the SAA5030 (Teletext video
processor; VIP) the SAA5050 (Teletext
character generator; TROM), the
SAA5040B (Teletext acquisition control;
TAG) and the SAA5045 (Gearing and
Address Logic Array; GALA).
FEATURES
• Designed to operate with USA
525-lIne television standard
(system M)
• For 24 row (8 TV lines per
row) X 40 character display
• Big character select input for
double-height characters
• Composite sync signal output for
display time-base synchronization
DESCRIPTION
APPLICATIONS
Teletext
Telecaptioning
Videotex
Phase-locking with Incoming
video (when used with SAA5030)
• Composite sync generator
• Low cost display systems (when
used with SAA5050 series)
TEMPERATURE RANGE
ORDER CODE
- 20°C to + 70°C
SAA5025DN
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
UNIT
VDD
Supply voltage range
PARAMETER
-0.3 to +7.5
V
VI
Input voltage range 1
-0.3 to +7.5
V
VOHZ
High-impedance state output voltage
-0.3 to + 7.5
V
VODD
Open-drain output voltage
-0.3 to + 13.2
V
Electrostatic charge protection on all inputs and
outputs2, 3
1000
V
PTOT
Total power dissipation per package
275
mW
TA
Operating ambient temperature range
-20 to +70
°C
TSTG
Storage temperature range
-65 to + 150
·C
NOTES:
1. See also characteristics on F6 input and Figure B.
2. Equivalent to discharging a 250pF capacitor through a 1kn series resistor.
3. N.B.: the SAA5025 is not protected agains1 TV tube flash-over.
4. All outputs are TTL compatible.
January 14, 1987
N Package
•
•
•
•
ORDERING INFORMATION.
28-Pin Plastic DIP (SOT-117D)
PIN CONFIGURATION
13-14
FS
TOP VIEW
CD12310S
PIN NO.
1
2
3
4
5
6
SYMBOL
Afffi
DE
FLA
X 100%.
Figure B. Recommended 6MHz Interface Circuitry Between the SAA5025
and the SAA5030 (Input F6)
13 FS Field (Picture) Sync Input - This
Input accepts a positive-going pulse of approximately 1601'S duration. Its leading edge
occurs during the second half of line one on
even fields (half picture) and correspondingly
in odd fieldS (other half picture). It is ignored
during the odd field.
14 CRS Character Rounding Select Output - The output signal starts High during
the even field (lines 1 to 263), goes Low after
the first LOSE pulse, again High after the
second LOSE pulse, then Low after the sixth
LOSE pulse, and finally High at the end of the
seventh LOSE pulse. This sequence repeats
every 8 lines (every row) for the entire display
period (see also Figure 3). For the odd field
(lines 264 to 525) CRS starts High, goes Low
after the second LOSE pulse, again High
after the fifth LOSE pulse, then Low after the
seventh LOSE pulse and finally High at the
end of the eighth LOSE pulse. This sequence
repeats every 8 lines (every row) for the entire
display period (see also Figure 3).
15 VDD Positive Supply -
(+5V)
16 LOSE Load Output Shift Register Enable Output - This is a positive-going output
pulse of 39.72jls duration commencing
13.411'S from start of line valid during line 47
to 238 inclusive, for the even field. A step-
13-23
pulse starting at the count of 3 character rate
clock pulses (Fl) after the second and seventh LOSE pulses and at the count of 3
character rate clock pulses repeated every
row is included. For the odd field, the LOSE
pulse is preceded by a pre-pulse of 7jls
duration commencing 7.411'S in line 20, and
has a step-pulse after the fifth and eighth
pulse, repeated every row (see also Figure 3).
17 DEW Data Entry Window Output This output defines the period during which
data may be exlracted from the incoming
television signal. It is High during lines 7 to 18
inclusive for the even fields and line 270 to
281 inclusive for the odd fields. The positivegoing pulse has a duration of 762.671"S and
commences at 6.95jls from the start of the
line (see also Figure 2).
18 DEN Display Enable Output - The output pulse is positive-going at 13.5jls from the
start of a line to 56.5jls and is active during
line 47 to 238 Inclusive if the DE input is High.
If the DE input is Low, the DEN is held in the
Low state.
19 TLC Transmitted Large Characters Input - When this input is Low, it enables rows
of double-height characters to be displayed
as required. Large characters descend into
the next memory row address location. 'i'TI5 is
•
Signetics Unear Products
Product Specification
Teletext Timing Chain for USA 525-Line System
always High (i.e., small) for the first line of a
row, even if it contains large characters.
bottom half of the page is also displayed with
double-height characters.
20 HIE High Impedance Enable Input When this input is in the High state, it will
force the RACK and memory row address
output into the high-impedance state. For
normal Teletext operation, this input should
be connected to the DEW output (Pin 17).
23 to 27 Ao to A4 Memory Row Address
Outputs (3-State) - These binary count
outputs sequencing from 00000 (count 0) to
address 10111 (count 23) for the 40 X 24
format.
21 BCS Big Character Select Input - For
normal size character display, this input signal
must be High while a Low gives double-height
characters.
22 1'IB ToplBottom Select Input - When
both 80S and 'fIB are Low, the top half of a
page is displayed with double-height characters. If 'fIB Is High and BCS is Low, the
January 14, 1987
The binary count changes every 6 TV lines
per row in the display period of line 47 to 236
inclusive for the 24-row display. The count
changes between 6.5ps and 9.0j.tS during the
line period.
28 RACK Read Address Clock Output This is the read address clock output to the
SAA5045 (GALA) column address counter
during the display period. It consists of 39
positive pulses at the 1.007MHz rate starting
13-24
SAA5025
at 13.57ps from the start of the line period
with the last negative edge occurring at
51.6j.tS. This sequence is active on line 45 to
236 inclusive. RACK is delayed by two Fl
clock periods for the whole of the field when
input DE is Low for the whole of line 39. On
lines 19 to 44 inclusive, output RACK is
permanently delayed by two Fl clock periods,
unaffected by DE.
NOTES:
1. In the big character top mode the memory row
address count Is 0 to 11, and in the big character
bottom mode the count is 12 to 23.
Each big character row is equal to 16 television
lines.
2. The memory row addresses are held Low for one
line period starting 6.5jlS to 91'S from the beginning of line 36 which Is only valid in the big
character bottom mode.
SAA5030
Signetics
Teletext Video Processor
Product Specification
Linear Products
DESCRIPTION
FEATURES
The SAA5030 is a monolithic bipolar
integrated circuit used for teletext video
processing. It is one of a package of four
circuits to be used in teletext TV data
systems. The SAA5030 extracts data
and data clock information from the
television composite video signal and
feeds this to the Acquisition and Control
Circuit SAA5040. A 6MHz crystal-controlled, phase-locked oscillator is incorporated which drives the Timing Chain
Circuit SAA5020. An adaptive sync separator is also provided which derives line
and field sync pulses from the input
video in order to synchronize the timing
chain.
• Slices digital data embedded In
the composite video signal
• Generates a synchronized clock
for the sliced data
• Generates a system display
clock, locked with the incoming
video signal
• On-chip signal quality detector
• On-chip adaptive sync separator
PIN CONFIGURATION
N Package
APPLICATIONS
• Teletext
• Data slicer
• Phase-locking with Incoming
video (when used with
SAA5025D)
• Telecaptlonlng
TOP VIEW
C0123205
PIN NO.
SYMBOL
TCSP
TCLR
FLR
ORDERING INFORMATION
DESCRIPTION
24-Pin Plastic DIP
TEMPERATURE RANGE
ORDER CODE
-20·C to + 70·C·
SAA5030N
GND
1'[/l:B§
F6
TCPD
8
BLOCK DIAGRAM
9
10
11
12
13
14
15
16
17
TOSAA5040
18
19
20
21
22
F61
F6Q
PO
AIlS
SYNQ
FS
FSST
CSS
VI
Vee
F7
DA'fA
CA
LCLK
CCLK
Cl
::~~
23
24
0--+----+
CIS
C25
DESCRIPTION
To signal presence time
constant components
Una reset time constant
Fast line reset output
Ground (OV)
Sandcastle input
6MHz output
To phase detector time
constant components
6MHz crystal oscillator input
6MHz crystal oscillator output
Picture-on input
After-hours sync input
Sync output to TV
Field sync output
Field sync separator timing
To sync separator capacitor
Composite video input
+ 12V supply
Clock output
Data output
Clock phase capacitor
.Clock regenerating coil
To clock pulse timing
capacitor
Peak detector capacitor pin
Peak detector capacitor pin
II
January 14, 1987
SYNC FROM
6MHzCLOCK
SAA5020
(SAA5025)
TOSAA5020
(SAA5025)
13-25
853-1145 87202
Signetics Linear Products
Product Specification
SAA5030
Teletext Video Processor
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
Vcc
Supply voltage V,7.4
13.2
V
VI
VI
VI
Input voltages VS·4
V, 0""
Vl1·4
9
Vcc
7.5
V
V
V
TSTG
Storage temperature range
-55 to + 150
·C
TA
Operating ambient temperature range
-20 to +70
·C
DC AND AC ELECTRICAL CHARACTERISTICS
At TA = 25·C, Vcc = 12V, and with external components as shown in
Figure 3, unless otherwise stated.
LIMITS
PARAMETER
SYMBOL
Vcc
Supply voltage
Icc
Supply current (Vcc = 12.0V)
UNIT
Min
Typ
Max
10.8
12.0
13.2
110
V
mA
Video Input and sync separator
V16VIOEO(P.p)
Video input amplitude (sync to white); see Figure 2
IZsl
Source impedance, f
2.0
1.4
= 100kHz
V16SYNC(P.P)
Sync amplitude
to
Delay through sync separator
to
Delay between field sync datum at Pin 12 and the leading edge
of separated field sync at Pin 13 ' (see Figure 2)
0.07
0.7
3.0
V
250
n
1.0
0.5
32
48
V
IJS
62
IJS
0.5
V
Field sync output
= 20/lA)
= 100iJA)
VOL
Vo (Low) (1,3
VOH
Vo (High) (-1'3
fF6
Frequency
2.4
V
6.0
MHz
Holding range
1.5
3.0
kHz
Catching range
1.5
3.0
kHz
0.3
mVlns
2
deg/mV
Control sensitivity of phase detector measured as voltage at Pin
7 with respect to phase difference between separated syncs
and phase·locked pulse PL
Control sensitivity of oscillator measured as change in 6MHz
phase shift from Pin 8 to Pin 9 with respect to voltage at
Pin 7
Gain of sustaining amplifier, V9_B measured with input voltage
of 100mVp.p and phase detector immobilized
Output voltage of 6MHz signal at Pin 6, measured into 20pF
load capacitance; peak·to·peak value
tR, tF
January 14, 1987
Output rise and fall times at Pin 6 into 20pF load
13-26
2.5
VIV
5.5
V
30
ns
Signetics Uneor Products
Product Specification
Teletext Video Processor
SAA5030
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) At TA ~ 25°C, Vcc = 12V, and with external components as
shown in Figure 3, unless otherwise stated.
LIMITS
PARAMETER
SYMBOL
UNIT
Min
Typ
Max
Data slicer and clock regenerator
Teletext data input amplitude, Pin 16 (see Figure 2);
peak-to-peak value2
Data input amplitude at Pin 16 required to enable amplitude
gate flip-flop; peak-to-peak value
Attack rate, measured at Pins 23 and 24 with a step to Pin 16
(positive)
(negative)
Decay rate, measured at Pins 23 and 24 with a step input to
Pin 16
48
Width of clock coil drive pulses from Pin 21 when clock
amplitude is not being controlled 3
Clock hangover measured at Pin 18 as the time the clock coil
continues ringing after the end of data4
V
0.46
V
15
9
V/Jls
V/Jls
100
144
40
mV/Jls
ns
Clock
Periods
20
Clock and data output voltages at Pins 18 and 19 measured
with 20pF load capacitance; peak-to-peak value
tR, tF
1.1
5.5
Output rise and fall times at Pins 18 and 19 into 20pF loads
V
30
ns
Sandcastle Input
Sandcastle detector thresholds, Pin 5
phase-locked pulse (PL) on
phase-locked pulse off
blanking pulse (CBB) on
blanking pulse off
5.5
V
V
V
V
2.0
V
V
2
3
4.5
Dual polarity sync buffer
After-hours sync (AHS) pulse input Pin 11
threshold for AHS active
threshold for AHS off
1.0
Picture-on (PO) input, Pin 10
threshold for PO active
threshold for PO off
2.0
V
V
1
V
3
mA
1.0
Sync output, Pin 12
AHS output with Pin 10 < 1V5; peak-to-peak value
composite sync output with Pin 10 > 2v5• 6; peak-to-peak
value
output current
0.7
0.7
V
•
January 14, 1987
13-27
Signetics Linear Products
Product Specification
SAA5030
Teletext Video Processor
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) At TA = 25°C, Vee = 12V, and wtth external components as
shown in Figure 3, unless otherwise stated.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
Line reset and signal presence detectors
Schmitt trigger threshold on Pin 2 to inhibit line reset output at
Pin 3 (syncs cOincident)
6.2
V
Schmitt trigger threshold on Pin 2 to permit line reset output at
Pin 3 (syncs non cOincident)
7.8
V
Line reset output VOL (13
= 201lA)
0.5
Line reset output VOH (- 13 = 1001lA)
2.4
V
V
Signal presence Schmitt trigger threshold on Pin 2 below which
the circuit accepts the input signal
6.0
V
Signal presence Schmitt trigger threshold on Pin 2 above which
the input signal is rejected
6.3
V
Cl
27.5
pF
Co
6.8
pF
CL
20
pF
Crystal-controlled, phase-locked oscillator
Trimability (CL increased to 30pF)
Hz
750
Fundamental ESR
50
n
NOTES:
1. This is measured with the dual polarity buffer external resistor connected to give negative-going syncs. The measurement is made after adjustment of
the potential divider at Pin 14 for optimum delay.
2. The teletext data input contains binary elements as a two-level NRZ signal shaped by a raised cosine filter. The bit rate is 6.9375Mbitls. The use of
odd parity for the B-bit bytes ensures that there are never more than 14-bit periods between each data transition.
3. This is measured by replacing the clock coil with a small value resistor.
4. This must be measured with the clock coil tuned and using a clock-cracker signal into Pin 16. The clock-cracker is a teletext waveform consisting of
only one data transition in each byte.
5. With the external resistor connected to the ground rail, syncs are positive-going centered on + 2.3V. With the resistor connected to the supply rail,
syncs are negative-going centered on +9.7V.
6. When the composite sync is being delivered, the level is substantially the same as that at the video input.
January 14, 1987
13-28
Signetics Linear Products
Product Specification
Teletext Video Processor
APPLICATION DATA
The function is quoted against the corresponding pin number
Signal Presence Time Constant - A
capacitor and a resistor connected in parallel between this pin and supply determine
the delay in operation of the signal presence detector.
2 Line Reset Time Constant - A capacitor
between this pin and supply integrates
current pulses from the coincidence detector; the resultant level is used to determine
whether to allow FLR pulses (see Pin 3).
3 Fast Line Reset Output (FLR) - Positivegoing sync pulses are produced at this
output if the coincidence detector shows
no coincidence between the syncs separated from the incoming video and the eBB
waveform from the timing chain circuit
SAA5020. These pulses are sent to the
timing chain circuit and are used to reset its
counters, so as to effect rapid lock-up of
the phase-locked loop.
4 Ground (OV)
5 Sandcastle Input (PL and CBB) - This
input accepts a sand castle waveform
which is formed from PI and eBB from the
timing chain SAA5020. PI is obtained by
slicing the waveform at 2.5V, and this,
together with separated sync, are inputs to
the phase detector which forms part of the
phase-locked loop. When the loop has
locked up, the edges of PI are nominally
2Jls before and 2JlS after the leading edge
of separated line syncs.
eBB is obtained by slicing the waveform at
5V, and is used to prevent the data slicer
from being offset by the color burst.
6 6MHz Output (F6) - This is the output of
the crystal oscillator (see Pins 8 and 9),
SAA5030
and is taken to the timing chain circuit
SAA5020 via a series capacitor.
7 Phase Detector Time Constant - The
integrating components for the phase detector of the phase-locked loop are connected between this pin and supply.
8,9 6MHz Crystal - A 6MHz crystal in
series with a trimmer capacitor is connected between these pins. It forms part
of an oscillator whose frequency is controlled by the voltage on Pin 7, which
forms part of the phase-locked loop.
10 Picture On Input (PO) - The PO signal,
from the acquisition and control circuits
SAA5040 series, is fed to this input and is
used to determine whether the input video
(Pin 16) or the AHS waveform (Pin 11)
appears at Pin 12.
11 After Hours Sync (AHS) - A composite
sync waveform AHS is generated in the
timing chain circuit SAA5020 and is used
to synchronize the TV (see Pin 10).
12 Sync Output to TV - The input video of
AHS is available at this output dependent
on whether the PO signal is High or Low.
In addition, either signal may be positivegoing or negative-going, dependent on
whether the load resistor at this output is
connected to ground or supply.
13 Field Sync Output (FS) - A pulse,
derived from the input video by the field
sync separator, which is used to reset the
line counter in the timing chain circuit
SAA5020.
14 Field Sync Separator Timing - A capacitor and adjusting network is connected to this pin and forms the integrator of
the field sync separator.
16 Composite Video Input (VI) - The composite video is fed to this input via a
coupling capacitor.
17 Supply Voltage (+ 12V)
18 Clock Output - The regenerated clock,
after extraction from the teletext data, is
fed out to the acquisition and control
circuits SAA5040 series via a series capacitor.
19 Data Output - The teletext data is sliced
off the video waveform, squared up, and
latched within the SAA5030. The latched
output is fed to the acquisition and control
circuits SAA5040 series via a series capacitor.
20 Clock Decoupling - A 1nF capacitor
between Pin 20 and ground is required for
clock decoupling.
21 Clock Regenerator Coil - A high-Q
parallel tuned circuit is connected between this pin and an external potential
divider. The coil is part of the clock
regeneration circuit (see Pin 22).
22 Clock Pulse Timing Capacitor - Short
pulses are derived from both edges of
data with the aid of a capaCitor connected
to this pin. The resulting pulses are fed, as
a current, into the clock coil connected to
Pin 21. Resulting oscillations are limited
and taken to the acquisition and control
circuits SAA5040 series via Pin 18.
23, 24 Peak Detector CapaCitors - The
teletext data is sliced with an automatic
data slicer, having a slicing level at the
mid-point of two peak detectors working
on the video signal. Storage capacitors
are connected to these pins for the negative and positive peak detectors.
15 Sync Separator Capacitor - A capacitor connected to this pin forms part of the
adaptive sync separator.
•
January 14, 1987
13-29
Signetlcs Linear Products
Product Specification
Teletext Video Processor
SAA5030
TOSAA5040
DATA
+12V
AELDSYNCTO
SAA5020 (SAA5025)
CLOCK
.J'L..-880
t~·e~H IOfc33OpF
Q o =90
1,nF
,. f-
InF
33k
1,nF
l33OpF147PF
23
22
21
19
20
:
1.21<
1.21<
~~
24
~
InF
J3'~F
I~F
+
~
r;;- r,;-
~16
*G
C
15
14
NO
I~F
VIDEO
+ r o FROM
TV
13
SAA5030
3
2
I
4
LT
~6MHz L
t
5-~F
~
,.,
Uk
-
i..-
8.8k
.--100k
+T
10",F
T
100nF
UNERESETTO
SAAS020
(SAA5025)
am
COMPOsrrE
SYNC TO TV
Ik
Pi:
FROM
SAAS020
T
InF
&MHz TO SAAS020
(SAA5025)
(SAA6025)
Figure 1. Peripheral Circuit
January 14, 1987
'---
(5
1.5k
13-30
r
,
L
J
6&pF
T+'~F f+'O~F -=
8.8k
8.8k
12
10
6
5
po FROM
SAA5040
JUUl
I (1.5k ALTERNAllYE
I FOR NEGATIVE S YNC)
I
I
1Ilf1r
-AHS FROM
SAA5020
(SAA5025)
Product Specification
Signetics Linear Products
SAA5030
Teletext Video Processor
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ZERO CARRIER 3V
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PEAK WHITE 2AV
I
.._ _ _ _ _ _ _ _ _ _ _ PEAK TELETEXT I.8ZV
----I
COLOR BURST
~~...J-i------------ BLACKD.72V
U..::::_______-----
SYNCDV
WFI9420S
Figure 2. PBrt of Teletext Line, With Burst Showing Nominal Levels
2.351'8
EQUALIZING
PULSE
FlELO SYNC
BROAD PULSE
_DA_TU_M
___
SE...
PjATION 4.71'8
LEADING EDGE OF FlELO
SYNC PULSE
Figure 3. Details of Idealized Composite Sync Weveform
..
January 14, 1987
13-31
Signetics
SAA5040
Teletext Acquisition and
Control Circuit
Product Specification
Linear Products
DESCRIPTION
The SAA5040A, SAA5040B, SAA5040C,
SAA5041, SAA5042 and SAA5043 form
the SAA5040 series of MOS N-channel
integrated circuits. They perform the
control, data acquisition and data routing
functions of the teletext system. The
circuits differ in the on-screen display
that is provided and in the decoding of
the remote-control commands. The
functions of the circuits are detailed in
Tables 1, 2 and 3; throughout the remainder of the data, the SAA5040 is
referred to when the complete series of
circuits is being described.
The SAA5040 is a 28-lead device which
receives serial teletext data and clock
signals from the remote-control systems
incorporating the SAA5012 or SAB3022,
SAB3023 decoder circuits. The
SAA5040 selects the required page information and feeds it in parallel form to
the teletext page memory.
The SAA5040 works in conjunction with
the SAA5020 timing chain and the
SAA5050 series of character generators.
The circuit consists of two main sections.
a. Data acquisition section
The basic input to this section is the
serial teletext data stream DATA from
the SAA5030 video processor circuit.
This data stream is clocked at a
6.9375MHz clock rate (F7) from the
SAA5030. The incoming data stream
is processed and sorted so that the
page of data selected by the user is
written as 7-bit parallel words into the
system memory. Hamming and parity
checks are performed on the incoming data to reduce errors. Provision is
also made to process the control bits
in the page header.
b. Control section
The basic input to this section is the 7bit serial data (DATA) from the remote
control decoder circuit such as the
SAA5012 or SAB3012. This is clocked
by the DUM signal.
February 12, 1987
The remote-control commands are decoded and the control functions are
stored.
PIN CONFIGURATION
N Package
Full details of the remote-control commands used in the various SAA5040
series options are given in Tables 1, 2
and 3. The control section also writes
data into the page memory independently of the data acquisition section. This
gives an on-screen display of certain
user-selected functions such as page
number and program name.
The 3-State data and address outputs to
the system memory are set to high
impedance state if certain remote-control commands are received (e.g., viewdata mode). This is to allow another
circuit to access the memory. using the
same address and data lines. The address lines are also high impedance
while the acquisition and control circuit is
not writing into the memory.
Further information on the control of the
complete teletext system is available.
The circuit is designed in accordance
with the September 1976 Broadcast Teletext specification published by BBC/
IBAIBREMA.
A typical circuit diagram of a teletext
decoder is shown in Figure 5.
FEATURES
• Converts serial data Into parallel
• Performs error detection and
correction
• Generates memory control
signals
• Interfaces to the remote-control
system
WoK
TOP VIEW
C012330S
PIN NO.
1
2
3
4
5
6
7
B
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SYMBOL
DESCRIPTION
Ground
Vss
DATA
F7
NC
DUM
Data input from SAA5030
Clock input from SAA5030
Not connected
Remote·control clock input
Remote-control data input
Data entry window input
llAIii
DEW
PO
Picture-on output
DE
Display enable output
Big character select output
Top/bottom output
General line reset input
iiCS
i/B
lmi
1MHz clock input
+5V supply
F1
~
Write O.K. output
D7
D6
D5
D4
D3
D2
D1
3-State outputs to
data bus
A4
AS
A2
A1
AO
WACK
1
3-State outputs to row
address bus
Write address clock output
APPLICATIONS
• Teletext
• Data acquisition
ORDERING INFORMATION
DESCRIPTION
28-Pin Plastic DIP
13-32
TEMPERATURE RANGE
ORDER CODE
-20·e to + 70·e
SAA5040BN
853-117387563
Signetics Unear Products
Product Specification
Teletext Acquisition and Control Circuit
SAA5040
BLOCK DIAGRAM
v,,
DUM
ilATA GLii
12
SAAS040
F1
DEW
PO
DE
BCS
TOROWj:
ADDRESS
A2
BUS
A3
~-r~-J~---VB
Milr=====:
WACK
n
SERIAL TO
PARALLEL
CONVERSION
AND
FRAMING CODE
o - : t____-+______~__~D~~~Er~~IO~N~~
DATAo--t~~~~~~~~~~__________~~~~~~~__________-J
22 21 20 19 18 17 16
D1 D2 D3 DC D5 D6 D7
TO DATA BUS
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
UNIT
Voo
Supply voltage (Pin 14)
PARAMETER
-0.3 to 7.5
V
VI
Input voltage (all inputs)
-0.3 to 7.5
V
Vos
Output voltage (Pin 8)
-0.3 to 13.2
V
Vo
Output voltage (all other outputs)
TSTG
TA
,~
-0.3 to 7.5
V
Storage temperature range
-65 to +125
Operating ambient temperature range
-20 to +70
·C
·C
February 12, 1987
13-33
Signetics Linear Products
Product Specification
Teletext Acquisition and Control Circuit
DC AND AC ELECTRICAL CHARACTERISTICS
SAA5040
TAm 25°C and Voo = 5V. unless otherwise stated.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Voo
Supply voltage (Pin 14)
100
Supply current
Typ
Max
5.5
V
80
120
rnA
5.5
V
4.5
F7 DATA (Pin 2). F7 CLOCK (Pin 3)
VIH
Input voltage; High
VIL
Input voltage; Low 1
0.5
V
tR
Rise time
30
ns
3.5
tF
Fall time
RI
Input resistance (measured at 4V)
CI
Input capacitance
2
30
ns
18
Mil
7
pF
V
Fl (Pin 13)
VIH
Input voltage; High
2.4
Voo
VIL
Input voltage; Low
0
0.6
V
tR
Rise time
50
ns
tF
Fall time
30
ns
CI
Input capacitance
7
pF
IIR
Input leakage current (VI = 0 to 5.5V)
10
jJA
V
DLiM (Pin 5). DATA (Pin 6), DEW (Pin 7),
cm:i (Pin 12)
VIH
Input voltage; High
2.0
Voo
VIL
Input voltage; Low
0
0.8
V
CI
Input capacitance
7
pF
IIR
Input leakage current (VI
10
jJA
=0
to 5.5V)
DE (Pin 9), BCS (Pin 10), TIB (Pin 11) (with internal pull-up to Voo)
VOL
Output voltage; Low (IOL - 400jJA)
VOH
Output voltage; High -IOH = 5011A for Pin 9
-IOH = 30jJA for Pin 10
-IOH = 20jJA for Pin 11
tR
tF
0
0.5
V
VOO
Voo
Voo
V
V
V
Output voltage rise time
10
lAS
Output voltage fall time
1
lAS
Co
Output capacitance
7
pF
-10
Output current wHh output in High state (Vo = 0.5V)
50
500
jJA
2.4
2.4
2.4
PO (Pin 8) (with internal pull-up to Voo)
VOL
Output voltage; Low (IOL = 1401IA)
0
0.5
V
VOH
Output voltage; High (-IOH = 50jJA)
2.4
Voo
V
tR. tF
Output rise and fall time (CL = 40pF)3
10
lAS
Co
Output capacitance
7
pF
-10
Output current with output in High state (Vo - 0.5V)
500
jJA
February 12. 1987
13·34
50
Product Specification
Signetics Linear Products
Teletext Acquisition and Control Circuit
SAA5040
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) TA = 25°C and VDD = 5V, unless otherwise stated.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
01 to 07 (Pins 16 to 22) (3-State)
VOL
Output voltage; Low (IOL = 100!lA)
VOH
Output voltage; High (IOH
tR, tF
Output rise and fall time
± IOROFF
Co
0
0.5
2.4
Voo
V
100
ns
Output leakage current in 'OFF' state (Vo = 0 to 5.5V)
10
!lA
Output capacitance
7
pF
0
0.5
V
2.4
VDD
V
50
100
ns
ns
500
!lA
7
pF
0
0.5
V
2.4
VDD
V
ns
ns
= -1 00!lA)
(CL = 40pF)3
V
WOK (Pin 15) (3-State with internal pull-up to VDD)
VOL
Output voltage; Low (lOL = 400!lA)
VOH
Output voltage; High (-IOH
tR,
tF
Output voltage rise time
Output voltage fall time
± IOROFF
Output current with 3-State 'OFF' (Vo = 0.5V)
Co
Output capacitance
= 200!lA)
I
(CL = 80pF)3
80
WACK (Pin 28) (3-State)
VOL
Output voltage; Low (IOL = 1.6mA)
VOH
Output voltage; High (-IOH
tR
tF
Output voltage rise time
Output voltage fall time
I
50
300
± IOROFF
Output leakage current in 'OFF' state (Vo = 0 to 5.5V)
10
!lA
Co
Output capacitance
7
pF
0
0.5
V
2.4
VDD
V
300
ns
10
!lA
7
pF
0
0.5
V
2.4
VDD
V
300
ns
10
!lA
7
pF
= -1 00!lA)
(CL = 40pF)3
AO to A2 (Pins 25 to 27) (3-State)
VOL
Output voltage; Low (IOL = 200!lA)
VOH
Output voltage; High (-IOH
tR, tF
Output rise and fall time
± IOROFF
Output leakage current in 'OFF' state (Vo
Co
Output capacitance
= 200!lA)
(CL = 90pF)3
=0
to 5.5V)
A3 and A4 (Pins 23 and 24) (3-State)
VOL
Output voltage; Low (IOL = 1.6mA)
VOH
Output voltage; High (-IOH
tR, tF
Output rise and fall time
+IOROFF
Output leakage current in 'OFF' state (Vo
Co
Output capacitance
= 200!lA)
(CL = 40pF)3
=0
to 5.5V)
TIMING CHARACTERISTICS
Teletext data and clock (F7 DATA + F7 CLOCK)2 (Figure 1)
TF7
F7 Clock cycle time
144
F7 Clock duty cycle (High-to-Low)
30
tsu
F7 Clock to data setup time
60
ns
tHOLD
F7 Clock to data hold time
40
ns
February 12, 1987
13-35
ns
70
%
•
Product Specification
Signetics Linear Products
SAA5040
Teletext Acquisition and Control Circuit
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) TA = 25°C and VDD = 5V, unless otherwise stated.
LIMITS
UNIT
PARAMETER
SYMBOL
Min
Typ
Max
Control DATA and clock (DATA + DUM)3
tCH
DUM Clock High time 4
6.5
8
tCL
DUM Clock Low time
3.5
8
tsu
DUM to DATA setup time
0
14
).IS
tHOLD
DUM to DATA hold time
8
14
).IS
).IS
60
).IS
Writing teletext data Into memory during DEW (Figure 3)
ns
tWACK
WACK cycle time
1150
tAWW
WACK rising edge to WOK falling edge
250
450
ns
tWRw
WACK rising edge to WOK rising edge
150
310
ns
tWPD
WOK pulse width
300
tDw
Data output setup time
330
ns
tDH
Data output hold time
0
ns
tRAW
Row address setup time before first
190
ns
tRwR
Row address valid time after last
0
ns
WOK
WOK
ns
TIMING CHARACTERISTICS
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
Writing header Information Into memory during TV line 40 (Figure 4)
This arrangement is a combined phasing of the SAA5040 and
the SAA5020 and is therefore referred to Fl input. The first
WOK is related to Fl No 14 h from the SAA5020
TF,
Fl clock cycle time
1000
tWF
Time from Fl to WOK falling edge
300
500
ns
tFW
TIme from Fl to WOK rising edge
0
120
ns
tDw
Data output setup time
330
ns
tDH
Data output hold time
0
ns
NOTES:
1.
2.
3.
4.
These inputs may be AC-coupled. Minimum rating is -O.3V, but the input may be taken more negative if AC·coupled.
Transition times measured between 0.5 and 3.SV levels. Delay times are measured from 1.5V level.
Transition times measured between 0.8 and 2.0V levels. Delay times are measured from 1.5V level.
There is no maximum DUM cycle time, provided the DUM duty cycle is such that tel MAX requirement is not exceeded.
February 12, 1987
13-36
ns
Signetics Linear Products
Product Specification
Teletext Acquisition and Control Circuit
__---,
SAA5040
1---tF7;='=~
F7CLOCK
F7 DATA
Figure 1. Teletext Data Timing
Figure 2. Remote Control Data Input Timing
Figure 3. Writing Teletext Data Into Memory During DEW
F1 PERIOD NO 14
15
16
F1
DATA
OUTPUT _ _ _ _- '
NOTE:
Memory row address is valid from
~
F1 period No 14 for complete line.
Figure 4. Writing Data Into Memory During TV Line 40
February 12, 1987
13-37
•
Signetics Linear Products
Product Specification
Teletext Acquisition and Control Circuit
APPLICATION DATA
The function is quoted against the corresponding pin number.
1 Vss Ground -
OV.
2 DATA Data Input from SAA5030 - This
input is a serial data stream of broadcast
teletext data from the SAA5030 video processor, the data being at a rate of 6.9375MHz.
This input from the SAA5030 is AC-coupled
with internal DC restoration of the signal
levels.
3 F7 Clock Input from SAA5030 - This
input is a 6.9375MHz clock from the
SAA5030 video processor which is used to
clock the teletext data acquisition circuitry.
The positive edge of this clock is nominally at
the center of each teletext data bit.
This input from the SAA5030 is AC-coupled
with internal DC restoration of the signal
levels.
5 DLIM Remote-Control Clock Input This input from the remote-control receiverdecoder is used to clock remote-control data
into the SAA5040. The positive-going edge of
every second clock pulse is nominally in the
center of each remote control data bit.
6 DATA Remote Control Data - This input
is a 7-bit serial data stream from the remotecontrol receiver-decoder.
This data contains the teletext and viewdata
remote-control user functions. The nominal
data rate is 32MS/bit. The remote-control
commands used in the SAA5040 series are
shown in Tables 1, 2, and 3.
7 DEW Data Entry Window - This input
from the SAA5020 Timing Chain defines the
period during which received teletext data
may be accepted by the SAA5040. This
signal is also used to enable the five memory
address outputs (Pins 23 to 27) and the 7-bit
parallel data outputs (Pins 16 to 22).
8 PO Picture On - This output to the
SAA5012, SAA5030 and SAA5050 circuits is
a static level used for the selection of TV
picture video 'on' or 'off'. The output is High
for TV picture 'ON', Low for TV picture 'OFF'.
The output has an internal pull-up to Voo.
9 DE Display Enable - This output to the
SAA5050 teletext character generator is used
to enable the teletext display.
The output is High for display enabled, Low
for display disabled.
The output is also forced to the Low state
during the DEW and TV line 40 periods and
when a teletext page is cleared.
control the writing of valid data into the
system memory. The signal is Low to write,
and is in the high impedance state when
viewdata is selected. The 3-State buffer is
enabled at the same time as the data outputs
(see below). An internal pull-up device prevents the output from floating into the Low
state when the 3-State buffer is OFF.
16, 17, 18, 19, 20, 21, 22 07 to 01, Data
Outputs - These 3-State outputs are the 7bit parallel data outputs to the system memory. The outputs are enabled at the following
times:
a.
During the data entry window (DEW) to
write teletext data into the memory. The
data rate is 867kB per second and is
derived from the teletext data clock.
b.
During TV line 40 for encoded status
information about user commands (e.g.,
program number), to be written into the
memory. This period is known as EDIL
(encoded data insertion line). The data
rate is 1MB per second and is derived
from the 1MHz display clock F1.
c.
When the page is cleared. In this case,
the data output is forced to the space
code (0100000) during the display period
for one field. This data is held at the
space code from either TV line 40 (if page
clear is caused by user command), or the
received teletext data line causing the
clear function, until the start of the data
entry window (DEW) of the next field.
The output has an internal pull-up to Voo.
10 BCS Big Character Select - This output
to the SAA5020 timing chain and to the
SAA5050 character generator is used to select double height character format under
user control. The output is High for normal
height characters, Low for double height
characters. It is also forced to the High state
on page clear. The output has an internal pullup to Voo.
11 f /B Top/Bottom - This output to the
SAA5020 timing cl)ain is used to select
whether top or bottom half page is being
viewed. The output is High for bottom half
page and Low for top half page. It is also
forced to the Low state on page clear. The
output has an internal pull-up to Voo.
12 GLR General Line Reset - This input
from the SAA5020 timing chain is used as a
reset signal for internal control and display
counter.
13 F1 - This input is a 1MHz clock signal
from the SAA5020 timing chain used to clock
internal remote-control processing and encoding circuits.
14 VDD + 5V Supply - This is the power
supply input to the circuit.
15 WOK Write O.K_ - This 3-State output
signal to the system memory is used to
February 12, 1987
SAA5040
13-38
23, 24, 25, 26, 27 A4 to AO Memory Ad·
dresses - These 3-State outputs are the 5bit row address to the page memory. This
address specifies in which of 24 rows the
teletext data is to be written. The outputs are
enabled during the data entry period (DEW).
28 WACK Write Address Clock - This 3State output is used to clock the memory
address counter during the data entry period
(DEW). The output is enabled only during this
period. The positive-going edge of WACK is
used to clock the address counter.
Product Specification
Signetics Linear Products
SAA5040
Teletext Acquisition and Control Circuit
Table 1. Remote-Control Commands Used In the SAA5040A/SAA5040B/SAA5040C/SAA50438
CODE
TELETEXT MODE (~= 1, b6
TELEVISION MODE (b7 = bs = 0)7
bs
b. b3 b2 bl
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
= 0)7
RESET1
TV/ON
STATUS
Gives program display.
Gives program display.
TIME
Gives time display.
STATUS
HOLD
Program/header displayS
Stops reception of teletext9
DISPLAY CANCEL3
TAPE
Resets to small characters
TIMED PAGE OFF
TIMED PAGE ON
NUMBERS'. 6
PROGRAMS2
1
2
3
4
5
6
7
8
9
0
SMALL CHARACTERS
LARGE CHARACTERS TOP HALF PAGE
LARGE CHARACTERS BOnOM HALF PAGE
SUPERIMPOSE6
TELETEXTIONs
NOTES:
1. Reset clears the page memory, sets page number to 100 and time code to 00.00 and resets timed page and display cancel modes.
2. Program names are displayed for 5s in a box at the top left of the screen in large charecters. Program commands clear the page memory except in
timed page mode.
The following boxed information is displayed:
REMOTE·CONTROL
COMMAND
b s b. ba b2 bl
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
SAA5040A
BBCl
BBC2
lTV
4
5
6
7
VCR
9
10
11
12
SAA5040B
SAA5040C
Gives no
status
box
BBCl
lTV
BBC2
BBCl
lTV
VTR
BBCl
lTV
BBC2
BBCl
lTV
VTR
SAA5043
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
1
2
3
4
5
6
7
8
9
0
10
11
3. Display cancel removes the text and restores the television picture. The device then reacts to any update indicator on the selected psge. An updated newsflash or
subtiUe is displayed immediately. When an updated normal page arrives, the page number only is displayed In a box at the top left 01 the screen. The full page of
text can then be displayed when required, using the teletext/on command.
4. Three number commands in sequence request a new page, and four number commands select a new time code in timed page mode. When a new psge has been
requested, the page header turns green and the page numbers roll until the new page is captured.
5. The teletext/on command resets display cancel, hold, and superimpose modes.
6. Status, timed page on, timed page off, numbers, superimpose, and teletext/on commands all reset to top hall psge and produce a box around the header,lor 5s.
This allows the header to be seen il the television picture is on (e.g. newsllash or display cancel modes).
7. In viewdata mode (b7 = be = 1) the device is disabled and teletext cannot be received. All 3·State outputs are high impedance.
February 12, 1987
13-39
•
Product Specification
Signetics Linear Products
SM5040
Teletext Acquisition and Control Circuit
8. Table 1 shows code required for functions specified. The device requires the inverse of these codes i.e., 67 to 61, The code is transmitted serially in the following
order: b" b" b2, b3, b 4, b5, b6.
9. When hold node is selected, 'HOLD' is displayed in green at the top right of the screen.
10.A 'P' is displayed before the page number at the top left of the screen (e.g., P123).
Table 2. Remote-Control Commands Used in the SAA5041 9
CODE
TELEVISION MODE (b7
bs
b4 b3 b2 b,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1 '
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TIME
=b6 =0)8
TELETEXT MODE (b7
=1, b6 =0)8
STATUS Gives header and time display.6
TIMED PAGE On/off toggle function.
Gives time display
TELETEXT RESET '
NUMBERS 2 ,7
PROGRAMS'o
0
1
2
3
4
5
6
7
6
9
SMALL CHARACTERS
LARGE CHARACTERS Top/bottom toggle function
HOLD Stops reception of teletext - toggle functionS
DISPLAY CANCEL4
SUPERIMPOSE
NORMAL DISPLAYs
NOTES:
1. The teletext reset command clears the page memory, selects Page 100, goes to small characters, and resets hold, timed page, and display cancel
modes.
2. Three number commands in sequence request a new page, and four number commands select a new time code in timeo page mode. When a new
page has been requested, the page header turns green and the page numbers roll until the new page is captured.
3. When hold mode is selected, 'HALT' is displayed in green at the top right of the screen.
4. Display cancel removes the text and restores the television picture. The 5AA5041 then reacts to any update indicator on the selected page. An
updated newsflash or subtitle is displayed immediately. When an updated normal page arrives, the page number only is displayed in a box at the
top left of the screen. The full page of text can then be displayed when required, using the normal display command.
5. The normal display command resets display cancel, hold, and superimpose modes.
6. Status, timed page, numbers, hold, superimpose, and normal display commands all reset to top half page and produce a box around the header for
five seconds. This allows the header to be seen even if the television picture is on (e.g., newsflash or display cancel modes).
7. An '5' is displayed before the page number at the top left of the screen (e.g., 5123).
8. In view data mode (b7 = b6 = 1) the 5AA5041 is disabled and teletext cannot be received. All 3-5tate outputs are high impedance.
9. Table 2 shows code required for functions specified. The 5AA5041 requires the inverse of these codes, Le., b7 to b,. The code is transmitted
serially in the following order: b7, b b2, b3, b4, b5, b 6.
"
10. Clear memory occurs except in timed page mode.
February 12, 1987
13-40
Product Specification
Signetics Linear Products
Teletext Acquisition and Control Circuit
SAA5040
Table 3. Remote-Control Commands Used in the SAA5042 9
CODE
TELEVISION MODE (b7
bs
b4
ba b 2 b1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
= b s = 0)8
TELETEXT MODE (b7
= 1,
bs = 0)8
RESET 1
STATUS
HOLD
TIME
Gives header and time displayS
Stops reception of teletext-toggle function 3
Gives time display
SMALL CHARACTERS
LARGE CHARACTERS TOP HALF PAGE
LARGE CHARACTERS BOnOM HALF PAGE
DISPLAY CANCEL/RECALL4
DISPLAY RECALL
NUMBERS 2,7
PROGRAMS 1O
0
1
2
3
4
5
6
7
8
9
TIMED PAGE On/Off toggle function
CLEAR MEMORY
LONG TERM STORE/SMALL CHARACTERS
SUPERIMPOSE
TELETEXT IONs
NOTES:
1. Reset clears the page memory, sets page number to 100 and time code to 00.00, and resets timed page and display cancel modes.
2. Three number commands in sequence request a new page, and four number commands select a new time code in timed page mode. When a new
page has been requested, the page header turns green and the page numbers roll until the new page is captured.
3. When hold mode is selected, 'STOP' is displayed in green at the top right of the screen.
4. Display cancel/recall removes the text and restores the television picture. The SAA5042 then reacts to any update indicator on the selected page.
An updated newsflash or subtitle is displayed immediately. When an updated normal page arrives, the page number only is displayed in a box at the
top left of the screen. The same command will then cause a normal page to be displayed, but will cancel a newsflash or subtitle page. Alternatively,
text can then be recalled by using the teletext! on command.
5. The teletext/on command resets display cancel, hold, and superimpose modes.
6. Status, timed page, numbers, superimpose, and teletext/on commands all reset to top half page and produce a box around the header for five
seconds. This allows the header to be seen even if the television picture is on (e.g., newsflash or display cancel modes).
7. A 'P' is displayed before the page number at the top left of the screen (e.g., 5123).
8. In view data mode (b7 = bs = 1) the SAAS042 is disabled and teletext cannot be received. All 3-State outputs are high impedance.
9. Table 3 shows code required for functions specified. The SAAS042 requires the inverse of these codes, i.e., b7 to b1. The code is transmitted
serially in the following order: b7, b" b2, bo, b4 , b5, bs.
10. Clear memory occurs except in timed page mode.
February 12, 1987
13-41
Product Specification
Signetics Linear Products
SAA5040
Teletext Acquisition and Control Circuit
~
L,
10J.'H
~@
~iF
C11
68pF
-=9 22 2' 20 19
DE 01 D2 DO D4
• DATi
5
FROMl
REMOTE
CONTROL
~
8
nF
--
:
c, '-----i,
2
T. r.-
~~~2
R4
DA~
IC'
AHs
SYNC OUT ~
(POSmvE)
F6
22
~Lr
:0= Ic:\.~
:=~1. ~~
C6
.7
pF
r:
23
C7
T1nF T
R5
e10
'DOnF
1.5k
PO
R'3
6.8k
C20
'nF
18
RS
14
6
AD A1
27
28
A2 A3 A4WAC~
25 2. 23 28
,.
~
, . 20 2' 22 23 2.
18 17
=r/S BCS DEW AO A, A2 A3 A4RA~
PL
GiJf
+5V
~6 CBij
1C3
FLR
HIE
,0
SAA5020
FS
TIC
5
AHS
CRS
2
F6
TRS
~ Fl
LOSE
e
-¥
:~~8
+C16
R9
33k
'"F
~O
SYNC
C2'
,nF
l!!-
-
'0/(
t-- t-
C'5
T~·3
nF
R11
1.2k
_F
roo
C'7
R,O
R,2
nF
Uk
,.ok
Figure 5. Typical Circuit Diagram of a Teletext Decoder
February 12, 1987
7
f2
ft
;tnc
3
FLR
FS '3
11
SAA5030
VIP
24
C,.
'nF
_6.8
~,.
7
';.F
VJD~~ ~r.!:
;14 RS
CIJJ.f
17
'0
R7
6.BI<
;.F
~6MHZ
C4
Gv
PO
iiCS DEW
~
,.
SAA5D40
TAC
11
~~
65FF
+C3
"r"'0
'ODIc _F
R'
1.Sk
'5
07~L~
1C2
F'
TID
!~
:=~F
17 16
06
2
DATA
3
F7
+12V
R2
DUM
'8
os
13-42
~
TIi3
r"'-
Signetlcs Linear Products
Product Specification
Teletext Acquisition and Control Circuit
1C4
74LS02
SAA5040
CS~+5V
L--"r.IL..JI--'~'.-"T.g.;~"7=-'
1
••
•
" "
13
I•
•
-----;
•
•
1C8
5
~
~
RAM
17
I.
~
-=-
-
74LS83A
*··
L..,===~==~"
~
" 7• t'
1'0
,.
2114
~7}l13
11/
\\\
'-------,
v
31.
1C8 7.LS161
·CL
7
15
'~5~
CK
9
I" "
13
I.
1C7 7.LS1.,
CK
-: L-:;:;"t"----=i::::•...IJ/ - : ,
10
WE
~
r------"
-.w
-=-
cs
RAM
g+.~\\\\
IC5
13
•
13
~
r----f.
7
9
6
2
15 +5V
.--.1.:........0.:::"-':"'"""".., 5
I.
ICO
~
2114
•
"
10
CS WE
~t
CK
••
10
12 _
------~------+-----------------~~------------------~~GLR
9
07
~
------.. . .----------------------------------------------~::::t:
~
TLC
06
B
os
7
6
5
D4
03
02
4 1.8
D1
DE 1"280:-_ _-'
le10
------------------------------------------------------~1;;j4
SAA~50
DUM
------------------------------------------------------~1i:f9
CRS
--------~--------------------------------------------~.!H. TR.
--------------------------------------------------------'~ LOSE
"
1---------'
iiiiA " •.--________....J
2
SUPERIMPOSE
~BC~S~PO~~Fl~Y~~B~G~~R~~~~~~~~~
15 'Z1
20
21
22
23
BLANKING
Figure 5. Typical Circuit Diagram of a Teletext Decoder (Continued)
February 12, 19B7
13-43
24 2S-:¥
..
SAA5045
Signetics
Gearing and Address Logic
Array for USA Teletext
Product Specification
Linear Products
PIN CONFIGURATION
DESCRIPTION
FEATURES
The SAA5045 is a PCF0700 CMOS
process gate array designed to interface
the SAA5040B Teletext Acquisition Control (TAC) IC to the SAA5030 Video
Processor (VIP) data output for modified
UK standard 525-line Teletext. It also
provides an address interface between
SAA5040B, SAA5025D Teletext Timing
Chain for USA 525-line system (USTIC)
and the page memory RAM. The memory interface includes read/write control
compatible with the geared 32 + 8 transmission system at 5.727272MHz data
rate employed in the modified UK system.
• Implements the gearing function,
allowing 40 characters/row
display
• Generates memory control
signals
• Gate array-based Implementation
N Package
APPLICATION
• Teletext
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
28-Pin Plastic DIP (SOT-II7D)
-20·C to + 70·C
SM5045N
TOP VIEW
CDl2340S
PIN
SYMBOL
NO.
4
S
6
7
8
9
10
11
12
13
14
lS
16
December 2, 1986
13-44
WRACK
AO
Al
A2
A3
A4
DEW
~
FS.7 DATA
FS.7
CLOCK
W<5R
c::s
DE
Vss
DKS.7
DAS.7
17
WE
18
19
20
21
22
23
24
2S
26
27
28
M9
M8
M7
M6
MS
M4
M3
AA2
Ml
MO
Voo
DESCRIPTION
Input clock to column counter
}
Row address system inputs
Data entry window input
General line reset starting output
5,7MHz data output
5.7MHz clock output
Write enable input
Chip select output
Display enable input
Ground
5.7MHz data clock input
5.7MHz data input
Write enable output
Memory address outputs
Positive supply
(+4.SV 10 +S.SV)
853-1055 86703
Product Specification
Signetics Linear Products
SAA5045
Gearing and Address Logic Array for USA Teletext
BLOCK DIAGRAM
SAAS045
AO
Al
A2
A3
A4
B(~:~WB=O
MUXI
2
--- ...
3
->::::.
r-~i-
4
C5 = 0IA
MUx;t(
I""""'(iijQ
rr;r
27
-,.--....' -~---l
I I
26
25
r-;-:~7;-;-
\/V/{~~
x. ,
~:XXX)cA
'Y:.
X " '\'ii
I l'-;t7;;";
5
6
24
;E
I
I
GJ
I
WRACK
Gt:Rs
DEW
DK 5.7
DA5.7
WoK
DE
o-...!.
1-
GO
--IMUX2,
G1 ,','
AA3
AA4
RAM
ADDRESS
BUS
22
AAS
21
AA6
~
HCO Cl C2C3C4C5
L
COLU M~~ONTROL
20
19
16
I
/'-~----+----CTRL
AA7
AA6
AA9
EN
vD;U+
+
8
7
GB
15
o-!!.
.......-- .......
~
CTRL
AAI
AA2
23
/~~/..,l-.:~,"",
..----.
AAO
H
+ +
FRAMING
CODE
DETECTOR
=1
+
GEARING.
BIT
DETECTOR
DELAY
EOUAUZER
~ HI
DATA
PROCESSOR
11
9
11
-I
13
I- ~
READ/WRITE-t
LOGIC
F5.7
CLOCK
F5.7
DATA
~ We
~ cs
•
December 2, 1986
13-45
Signetics Linear Products
Product Specification
Gearing and Address Logic Array for USA Teletext
SYSTEM CONTENT
Functionally the chip contains two main sections which operate during the acquisition and
display periods.
Gearing Control Section
The data from the SAA5030 (VIP) and data
clock are processed to detect the presence
of the gearing bit and convert the data for
correct operation of the SAA5040B (TAG).
Data and clock outputs to the TAC are
internally compensated for processing delays, so that correct clocking-in of data is
ensured.
The address output buffers are 3-State devices controlled by the line reset signal (Pin 8;
GLRS). During the horizontal flyback period,
the address pins are 3-State to allow alternative addressing for customized applications.
Read/Write Control to RAM
An internal counter prevents overwriting if
more than 32 character WOK pulses are
received from TAC due to poor transmission
conditions. Two control outputs, one for
read/write (WE) and the other for chip select
(CS), are provided to eliminate conflicts on
the input/output RAM bus.
Addressing Section
Framing Code Detection
Column counters are included, which operate
from the WACK (TAG) and RACK (USTIG)
column clock signals during acquisition and
display respectively.
When a valid data line is received and the
framing code is detected in the gearing section, then flag pulses (pair of pulses) are
available at output WE, before the CS output
is driven Low for normal writing into the RAM.
If a framing-code-present signal is required, it
can be obtained by gating WE and CS outputs such that an output from the WE, when
output CS is High indicates the detection of a
framing code; N.B., each framing code produces a pair of pulses.
Five row-address input circuits (pins AO to A4)
are provided for (TAG) and (USTIC) address
outputs. These are multiplexed with the column address from the internal counters for
correct mapping of the RAM via ten output
address pins (AAO to AA9). During acquisition, the multiplexer is controlled by. the
gearing bit detection to give correct assembly
of the 40-character per row page structure.
COLUMN
OT031
~
'"
+
~
11"---------
t
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
28
SM5045
RAM ADDRESS CONTROL
The Block Diagram shows that the ten RAM
address outputs are controlled by a multiplexer (MUX3) which interchanges the two groups
of five address lines when a gearing bit equal
to logic "1" is received during data input.
During display, MUX3 is switched by Bit 6 of
the column counter. MUX1, which is switched
by the gearing bit, controls stepping of the
row address when fill-in rows are received.
MUX2 is switched by either the gearing bit or
Bit 6 of the column counter to access the part
of RAM storing the last eight bytes of each
row of data.
The mapping of the 1024-byte RAM is shown
in Figure 1. Area" A" stores data corresponding to the left-hand side (32 bytes wide) of the
display and area "B" stores the remainder for
the right-hand side.
Access to the RAM for custom operations
can be made during the time that GLRS (Pin
8) is Low, which causes all ten address
buffers to be in the open state. It should be
noted that GLRS Low also resets the column
counters and the gearing-bit detection system
to logic "0". This normally occurs during the
horizontal interval (between 5 and 811S) after
the horizontal sync pulse falling edge.
AAS_AM
o-
l:I::l
:r:r
00
n
"''''
W
ROW 1
!II
S~
in~~
~oz
!D:~~
~XOO
AREA 'A'
(24 ROWS x 32 BYTES)
LEFT-HAND PART OF DISPLAV
COLUMN COUNT 0 TO 31
DATA INPUT WITH GEAR BIT
0
=
=
1
1
a::U)W O
«::toa:
ozO
",,,'o:f~ II
~~1i5
1
;;:.~
"
1
ex:
ROW 23
30
'--..l!
DFOfl580S
Figure 1. Memory Map for the SAA5045 Address System
December 2, 1986
13-46
Signetlcs Linear Products
Product Specification
SAA5045
Gearing and Address logic Array for USA Teletext
APPLICATION INFORMATION
The function is described against the corresponding pin number.
1 WRACK Input Clock to Column Counter
- Input clock to column counter during data
input or display; WACK from SAA5040B
(TAG) or RACK from SAA5025D (USTIC).
2 to 6 AD to A4 Row Address System
Inputs - Inputs to row address system
during data input or display. Row address
numbers greater than 0 to 23 disable writing
to the RAM during input.
7 DEW Data Entry Window Input - Data
entry window input enables gearing bit detection and data processing part of system.
8 GLRS General Line Reset Starting Output -Input from the SAA5025D is a negative
reset pulse at line rate for column counters
and gearing system. When this input is Low, it
opens 3-State address buffers.
9 F5.7 DATA 5_7MHz Data Output - Data
output at 5.7MHz rate to SAA5040B (TAC)
during the data acquisition period when DEW
is High.
10 F5.7 CLOCK 5.7MHz Clock Output Data clock output at 5.7MHz rate to
SAA5040B (TAC), synchronized to data at Pin
9 (F5.7 DATA).
11 WOK Write Enable Input - Write enable
input from SAA5040B (TAC) during data acquisition, when correct data is received, for
RAM write/read control (via output WE; Pin
17).
12 CS Chip Select Output - Output to drive
the RAM chip enable during data input and
display periods controlled by the display enable output (DE) and write O.K. (WOK) output
of the SAA5040B (TAC), avoiding input/output bus conflict.
13 DE Display Enable Input - Display enable input from SAA5040B (TAC) to control
CS.
14 Vss -
Ground.
15 DK5.7 5.7MHz Data Clock Input - Data
clock input at 5.7MHz rate from the SAA5030
(VIP); this pin is capacitively-coupled with a
DC restoring diode and is externally connected to Vss.
16 DA5.7 5.7MHz Data Input - Data input
at 5.7MHz rate from SAA5030 (VIP); this pin
is capacitively-coupled with a DC restoring
diode and is externally connected to V55.
17 WE Write Enable Output - Write enable
output to control RAM write/read. This output
is the gated and delay version of the WOK
from the SAA5040B, but limited to 32. A pair
of pulses which are possible before the
WACK count is equal to 32. A pair of pulses
on this output precedes the Wl5K pulses,
while CS is High whenever a framing code is
detected.
18 to 27 AA9 to AAD Memory Address
Outputs - Memory address outputs; 3-State
buffered outputs, open when GLRS is Low for
auxiliary access to the RAM address bus if
required.
N.B.: AA9 and AA8 are simultaneously High
whenever a gear bit with logic "1" is
received during DEW is High. This enables detection of gearing bit reception,
following GLRS reset on each line,
which always resets AAO to AA9 to logiC
"0".
28 VDD Positive Supply (4.5V to 5.5V)
NOTE:
Input pins other than 15 and 16 have internal 15k!}
pull-up resistors for compaUbility with SAA5025D
and SAA5040B output signal ranges. Pins 15 and 16
are CM05 inputs for DC restored drive from the
5AA5030 (VIp) clock and data output signals.
V1DEO
INPUT
DISPLAY
INTERFACE
2.8Vp _ p
Figure 2. Schematic Diagram of the 5-Chlp Decoder
December 2, 1986
13-47
Signe1ics
SAA5050j55
Teletext Character Generator
Product Specification
Linear Products
DESCRIPTION
The SAA5050 series of MOS N-channel
integrated circuits provides the video
drive signals to the television receiver
necessary to produce the teletext/viewdata display.
The SAA5050 is a 28-pin device which
incorporates a fast access character
generator ROM (4.3kbits), the logic decoding for all the teletext control characters and decoding for some of the remote control functions. The circuit generates 96 alphanumeric and 64 graphic
characters. In addition there are 32 control characters which determine the nature of the display.
The SAA5050 is suitable for direct connection to the SAA5010, SAA5012,
SAA5020 and SAA5040 Series integrated circuits.
The basic input to the SAA5050 is the
character data from the teletext page
memory. This is a 7-bit code. Each
character code defines a dot matrix
pattern. The character period is 11LS and
the character dot rate is 6MHz. The
timings are derived from the two external
input clocks F1 (1 MHz) and TR6 (6MHz)
which are amplified and re-synchronized
internally. Each character rectangle is 6
dots wide by 10 TV lines high. One dot
space is left between adjacent characters, and there is one line space left
between rows. Alphanumeric characters
are generated on a 5 X 9 matrix, allowing space for descending characters.
Each of the 64 graphic characters is
decoded to form a 2 X 3 block arrangement which occupies the complete
6 X 10 dot matrix (Figure 7). Graphics
characters may be either contiguous or
separated (Figure 8). The alphanumeric
characters are character rounded, i.e, a
half dot is inserted before or after a
whole dot in the presence of a diagonal
in a character matrix.
of the PO and DE inputs and the box
control characters (see Table 3).
PIN CONFIGURATION
The monochrome data signal can be
used to inlay characters into the television video. The use of the 32 control
characters provides information on the
nature of the display, e.g., color. These
are also used to provide other facilities
such as 'concealed display' and flashing
words, etc. The full character set is given
in Table 1.
FEATURES
• On-chip character ROM
• Contains 'character rounding'
facility
• Interprets remote control
commands
• Video output consists of R, G, B
and Y open-collector
• Provides a 'Blanking' output
• Provides a 'Superimpose' output
for use In 'Mix-mode' type
displays
TOP VIEW
OO1235OS
TOP VIEW
APPLICATIONS
• Teletext
• Videotex
• Low cost character generator
• Display systems with windowing,
boxing, and text overlay
capabilities
• Telecaptlonlng
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
28·Pin Plastic DIP (SOT-117)
-20·C to
+ 70·C
SAA5050N
28-Pin Plastic DIP (SOT-117)
-20·C to
+ 70·C
SAA5055N
The character video output signals comprise a monochrome signal and RGB
signals for a color receiver. A blanking
output Signal Is provided to blank out the
television video signal under the control
February 25, 1987
13-48
853·0268 87779
Signetlcs Unear Products
Product Specification
Teletext Character Generator
SAA5050/55
BLOCK DIAGRAM
DI
D2
D3
14
15
INPUT
BUFFER
D4
D5
CRS
BCs
D6
D7
TLC
B
G
R
2G
LOSE
DEW
CONTROL
CHARACTER
DETECTION
AND STORE·
16
FI
TR6
COLOR
MULTIPLEXER
SI
Y07.~~~------------~
B~N~~4---------------------~
DE
DATA DUM GLR
PO
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
Voltages (with respect to Pin 1)
Voo
Supply voltage (Pin 18)
-0.3 to 7.5
V
VI
Input voltages
(all inputs + input/output)
-0.3 to 7.5
V
VOl 6
Vo
Output voltage (Pin 16)
(all other output s)
-0.3 to 75
-0.3 to 14.0
V
V
Temperature
TSTG
Storage temperature range
-20 to +125
·C
TA
Operating ambient temperature range
-20 to +70
·C
February 25, 1987
13-49
Signetics Linear Products
Product Specification
Teletext Character Generator
SAA5050j55
DC AND AC ELECTRICAL CHARACTERISTICS TA = 25°C and Voo =
5V, unless otherwise stated.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Voo
Supply voltage (Pin 1B)
100
Supply current
Typ
Max
5.5
V
B5
160
mA
4.5
Inputs
Character data D1 to D7 (Pins 4 to 10)
VIH
Input voltage; High
2.S5
Voo
V
Vil
Input voltage; Low
0
O.S
V
Clock Inputs F1 (Pin 20) TR6 (Pin 19)
VIH
Input voltage; High
2.S5
Voo
V
Vil
Input voltage; Low
0
O.S
V
Logic Inputs DATA (Pin 3), DLiM (Pin 11), GLR (Pin 12) DEW (Pin 13), CRS (Pin 14), BCS (Pin 15), LOSE (Pin 26),
PO (Pin 27), DE (Pin 28)
VIH
Input voltage; High
2
Voo
V
Vil
Input voltage; Low
0
O.B
V
10
IlA
7
pF
All Inputs
IIR
Input leakage current (VI
CI
Input capacitance
= 5.5V)
Outputs
Character video outputs + blanking output (open-draln)3 B- (Pin 22), G- (Pin 23), R- (Pin 24), Y- (Pin 21), blanking (Pin 25)
VOL
Output voltage; Low (IOl = 2mA)
0.5
V
VOL
Output voltage; Low (IOl = 4mA)
1.0
V
VOL
Output voltage; Low (IOl = SmA)
2.0
V
VOH
Output voltage; HighS
Cl
Output load capacitance
13.2
V
15
pF
30
ns
20
ns
0
0.5
V
2.4
Voo
V
Voo
tF
Output fall time 1
dtF
Variation of fall time between any outputs 1
0
TLC (Pin 16)
VOL
Output voltage; Low (IOl = 1001lA)
VOH
Output voltage; High (-IOH
Cl
Output load capacitance
30
pF
tR
Output rise time
Measured between O.BV and 2.0V levels
1.0
Il s
tF
Output fall time
Measured between O.BV and 2.0V levels
1.0
iJ.S
February 25, 19B7
= 1001lA)
13-50
Signetics Linear Products
Product Specification
SAA5050j55
Teletext Character Generator
DC AND AC ELECTRICAL CHARACTERISTICS (Continued)
TA = 25'C and Voo = 5V, unless otherwise stated.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
Input/output
SI (Pin 2) (open-drain)
V'H
Input voltage; High
2.0
6.5
V
V'L
Input voltage; Low
0
0.8
V
10
!1A
7
pF
V
= 5.5V)
I'A
Input leakage current (V,
C,
Input capacitance
VOL
Output voltage; Low (lOL = OAmA)
0
0.5
VOL
Output voltage; Low (IOL
= 1.3mA)
0
1.0
V
CL
Output load capacitance
45
pF
VOH
Output voltage; High state2
6.5
V
Character data timing (Figure 2)
to
TR6 rising edge 10 F1 falling edge
fTR6
TR6 frequency
6
TR6 mark/space ratio
fFl
60
6
40:60
F1 frequency
60:40
1
F1 mark/space ratio
40:60
Icos
Data setup time
80
teoH
Data hold time
100
teoG
tCOA
Delay time - character in/
character data at outputs
1 Graphics
MHz
60:40
ns
ns
2.6
2.767
Alphanumerics
ns
MHz
/1s
/1s
Display period timing (Figure 3)
tLDH
F1 falling edge to LOSE rising edge
0
250
tLDL
F1 falling edge to LOSE falling edge
0
250
lOON
LOSE rising edge to 'Display on'
2.6
/1s
tooFF
LOSE falling edge to 'Display off'
2.6
/1s
lop
'Display period'
40
/1s
ns
ns
Line rate timing (Figure 4)
tOGL
F1 rising edge to GLR falling edge
0
200
tOGH
F1 rising edge to GLR rising edge
0
200
tGLP
GLR Low time
IGLR
tLSL
ns
ns
1
/1s
Line start' to GLR falling edge
5
/1s
Line start' to LOSE rising edge
14.5
/1s
tLLS
LOSE falling edge to Line start'
9.5
/1s
tLNP
Line period
64
/1S
tLHP
LOSE High time
40
/1s
February 25, 1987
13-51
•
Product Specification
Signetics Linear Products
Teletext Character Generator
SAA5050j55
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) TA = 25°C and Voo = 5V, unless otherwise stated.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Remote data Input timing (Figure 6) Assuming Fl period
= l/ls
and GLR period
Typ
Max
= 64/ls
tCH
DUM clock High time 4
6.5
B
tCl
DUM clock Low time
3.5
B
tos
DATA to DUM setup time
0
14
/lS
tOH
DUM to DATA hold time
B
14
J.lS
/lS
60
/ls
NOTES:
* Taken as falling edge of 'line sync' pulse.
1. Fall time, tF and .1tF. are defined as shown and are measured using the circuit shown below:
tF is measured between the 9V and 1V levels.
.6.tF is the maximum time difference between outputs.
2.
3.
4.
5.
Recommended pull-up resister for Si is 18kil.
The R, G, B, Y, and blanking outputs are protected against short circuit to supply rails.
There is no maximum DUM cycle time, provided the DUM duty cycle is such that the tCl max requirement is not exceeded.
With maximum pull-up voltage applied to R, G, B, and BLAN outputs the leakage current will not exceed 20/AA with the outputs in the off state.
+12V
3k
OUTPUT
PIN
9~
CLAMP
Q9
+1
+1
February 25, 1987
r
15pF
vo•
13-52
Signetics Linear Products
Product Specification
Teletext Character Generator
SPECIAL FEATURES
Flash Oscillator
The circuit generates a 0.75Hz signal with a
3:1 on/off ratio to provide the flashing character facility.
Power-On Reset
When the supply voltage is switched on, the
character generator will reset to TV, conceal,
and not superimpose modes.
Character Rounding
The character rounding function is different
for the small and double height characters. In
both cases the ROM is accessed twice during
the character period of 11J.s. The dot information of two rows is then compared to detect
the presence of any diagonal in the character
matrix and to determine the positioning of the
character rounding half dots.
For small characters, rounding is always referenced in the same direction (i.e., row before
in even fields and row after in odd fields as
determined by the CRS signal).
For double height characters, rounding is
always referenced alternately up and down,
changing every line using an internally-generated signal. (The CRS signal is '0' for the odd
field and' l' for the even field of an interlaced
TV picture).
Graphics Decoder
The 64 graphic characters are decoded directly from the character data inputs and
appear on a 2 X 3 matrix. Figure 7 gives
details of the graphics decoding.
APPLICATION DATA
The function is quoted against the corresponding pin numbers.
1 Vss Ground -
OV.
2 Sl Superimpose - This is a dual purpose
input! output pin. The output is an open drain
transistor (capable of sinking current to Vss),
which is in the conducting state when superimpose mode is selected. This allows contrast reduction of the TV picture in superimpose mode, if required. If the pin is held low,
the internal 'TV mode' flip-flop is held in the
'text' state. This is for VDU applications when
the remote control is not used.
February 25, 1987
SAA5050j55
3 DATA Remote Control Data - This
input accepts a 7-bil serial data stream from
the remote control decoder. This data contains the teletext and viewdata remote control
functions. The nominal data rate is 32IJ.s!bit.
The command codes used in the SAA5050
are shown in Table 2.
4, 5, 6, 7, 8, 9, 10 D1 to D7 Character Data
- These inputs accept a 7-bit parallel data
code from the page memory. This data selects the alphanumeric characters, the graphics characters and the control characters.
The alphanumeric addresses are ROM column addresses, the graphics and control data
are decoded internally.
11 DLiM - This input receives a clock
signal from the remote control decoder and
this signal is used to clock remote control
data into the SAA5050. The positive-going
edge of every second clock pulse is nominally
in the center of each remote control data bit
(Figure 6).
12 GLR General Line Reset - This input
Signal from the SAA5020 Timing Chain is
required for internal synchronization of remote control data signals.
13 DEW Data Entry Window - This input
signal from the SAA5020 Timing Chain is
required to reset the internal ROM row address counter prior to the display period. It is
also used internally to derive the 'flash' period.
14 CRS Character Rounding Select This input signal from the SAA5020 Timing
Chain is required for correct character rounding of displayed characters (normal height
characters only).
15 BCS Big Character Select - This input
from the SAA5040 Teletext Acquisition and
Control device allows selection of large characters by remote control.
16 TLC Transmitted Large Characters This output to the SAA5020 Timing Chain
enables double height characters to be displayed as a result of control characters stored
in the page memory.
18 Vee + 5V Supply - This is the power
supply input to the circuit.
13-53
19 TR6 - This input is a 6MHz signal from
the SAA5020 Timing Chain used as a character dot rate clock.
20 F1 - This input is a 1MHz equal mark!
space ratio signal from the SAA5020 Timing
Chain. It is used to latch the 7-bit parallel
character data into the input latches. It is also
used to synchronize an internal divide-by-6
counter. The F1 signal is internally synchronized with TR6.
21 Y Output - This is a video output signal
which is active in the high state containing
character dot information for TV display. The
output is an open drain transistor capable of
sinking current to Vss.
22, 23, 24 B, G, R Outputs - These are
the Blue, Green and Red Character video
outputs to the TV display circuits. They are
active high and contain both character and
background color information. The outputs
are open drain transistors capable of sinking
current to Vss.
25 BLAN Blanking - This active high output signal provides TV picture video blanking.
It is active for the duration of a box when
Picture On and Display Enable are high. It is
also activated permanently for normal teletext
display when no TV picture is required (PO
low). The output is an open drain transistor
capable of sinking current to Vss. Full details
are given in Table 3.
26 LOSE Load Output Shift Register Enable - This input signal from the SAA5020
Timing Chain resets the internal control character flip-flops prior to the start of each
display line. It also defines the character
display period.
27 PO Picture On - This input signal from
the SAA5040 Teletext Acquisition and Control device is used to control the character
video and blanking outputs. When PO is high,
only text in boxes is displayed unless in
superimpose mode. The input is high for TV
picture video on, low for picture off (see Table
3).
28 DE Display Enable - This input signal
from the SAA5040 Teletext Acquisition and
Control device is used to enable the teletext
display. The input is high for teletext display
enabled. Low for display cancelled (see Table
3).
II
Signetics Linear Products
Product Specification
SM5050j55
Teletext Character Generator
TR6
4=
0
F1
~~o.~8v~____J;I
1.5V
CHARACTER
DATA INPUTS
01-07
I
'n' DISPI.AY ~
--------------I..~. CHARACTER
PERIOD
FOR GRAPHICS
I
CHARACTER 'n'
1 - - - - - - - - - - - - - - 1 c o . ---------------i.~ DISP~~:ERIOD
ALPHANUMERICS
Figure 2. Character Data Timing (for Typical 40-Character Display)
F1
LOSE
DISPI.AY
PERIOD
I--------'Op - - - - - - - - - - + \
Figure 3. Character Period Timing (for Typical 40-Character Display)
F1
~
2.0Vrr-
\\...2:!!..J/
GLR
\
1
GLR
LOSE
I
I \ U~--------------------h;
/
I LI
+
1.SV
'GLR
M r-
I
1
'OLP
!
1.SV
1.SV
I0
(LINE START)"
NOTE:
*Taken as falling edge of line sync pulse.
Figure 4. Line Rate Clocks (for Line Period of 64/18)
February 25, 1987
l!-_--+l__
ILSL--........,..I..
o O - - - - - - - - - - I L H P - - - - - - - - - i..~1
I
11-o01-------"-------ILNP-------------'----<·>-I1
~ILLS "I
13-54
Signetics Linear Products
Product Specification
Teletext Character Generator
n
6
DEW
_ _- - - '
CRS
SAA5050/55
n
318
22
L-_ _ _ _ _ _ _ _--'
335
L-_ _
'-----------------------...JI
NUMBERS REFER TO
TYPICAL TV LINE NUMBER
313
Figure 5. Field Rate Clocks (for Field Period of 20ms, 3121'2 Lines per Field)
Figure 6. Remote Control Input Timing
i
!I
b,
b.
b3
b4
b,
b-,
1
10TV
1
NOTES:
Each cell is illuminated if the particular 'bit' (bt. b2, b3, b4, bs. or b7) is a '1'.
For graphics characters bs is always a '1' (see Table 1).
Figure 7. Graphics Character
II
February 25, 1987
13-55
Signetics Linear Products
Product Specification
SAA5050j55
Teletext Character Generator
KEY
ALPHANUMERICS AND
GRAPHICS 'SPACE'
CHARACTER 0000010
ALPHANUMERICS
CHARACTER 1011010
ALPHANUMERICS OR
BLAST-THROUGH
ALPHANUMERICS
CHARACTER 0001001
ALPHANUMERICS
CHARACTER 1111111
CONTIGUOUS GRAPHICS
CHARACTER 0110111
SEPARATED GRAPHICS
CHARACTER 0110111
SEPARATED GRAPHICS
CHARACTER 1111111
CONTIGUOUS GRAPHICS
CHARACTER 1111111
II
I
f---+--I
I
I
r--4---I
I
I
Figure 8. Character Format
February 25. 1987
13-56
~ BACKGROUND
~COLOR
D
DISPLAY
COLOR
Product Specification
Signetics Linear Products
SAA5050j55
Teletext Character Generator
Table 1. Character Data Input Decoding
o
0,
o
2
, 0
I
20
,
o
"
"
3 : 30
7 : 70
00 00
00 0 1
oio
10
I
0\0 1 1
i
011 00
I
I
oi'
011 01
5
10
6
oil , ,
7
i
I
I
I
,!O 0 0
'1 00 ,
lio 1 0
,10
1 ,
I
, , 00
, , 0'
, , , 0
l' , ,
NOTES:
Control characters shown in columns 0 and 1 are normally displayed as spaces.
The SAA505Q character set is shown as example. Details of character sets afe given in Figures 9 and 10.
•
These control characters afe reserved for compatability with other data codes,
•• These control characters are presumed before each row begins.
Codes may be referred to by their column and row, e.g., 2/5 refers to %.
D
Character rectangle
Black represents display color.
White represents background.
February 25, 1987
13-57
•
Signetics Linear Products
Product Specification
Teletext Character Generator
SAA5050j55
Table 2. Remote Control Command Codes Used in the SAA5050
b7
b6
bs
CODE
b4
0
X
X
1
X
X
1
0
1
1
0
1
0
X
X
1
1
X
1
X
0
1
X
0
Any command apart
b2
ba
X
X
X
X
X
X
1
1
1
1
1
1
X
X
X
X
X
X
0
1
1
1
0
1
from reveal set
bl
X
X
0
1
X
X
0
1
COMMAND
FUNCTION
Allows text on top row of display only
Allows text throughout display period
Sets Superimpose mode
Resets Superimpose mode
Resets Superimpose mode
Resets Superimpose mode
Reveals for time-out3
Sets Reveal mode3
Resets Reveal mode3
'TV' mode
'Text' mode
Superimpose
Teletext
'TV' mode
Viewdata mode
Reveal
Reveal set
NOTES:
x = Don't care.
1. When the power is applied, the SAA5050 is set into the 'TV' mode and reset out of Superimpose and Reveal modes.
2. 'Text' mode is selected when Si (Pin 2) is held low.
3. Reveal mode allows display of text previously concealed by 'conceal display' control characters.
Table 3. Conditions Affecting Display3
INPUTS
Picture On
(PO)
(a)
(b)
(c)
(d)
(e)
(f)
(g)
1
0
0
1
1
1
1
CONTROL DATA
OUTPUTS
Display Enable
(DE)
Superimpose
Mode
Box
Text Display Enabled
(i.e., R, G, B, Y outputs)
Blanking
0
1
0
1
1
1
1
1 or 0
1 or 0
1 or 0
0
1
1
0
1 or 0
1 or 0
1 or 0
0
0
1
1
0
1
02
0
1
1
1
0
1
1
0
0
1
1
NOTES:
1. For TV mode (Picture On = 'I', Superimpose mode not allowed) rows (a), (d), and (g) of Table 3 refer to display row 0 only. For all other rows text
display is disabled and Blanking = '0'.
2. The R, G, 8 outputs may contain character and background color information. The only exception is that background colors are inhibited when
Blanking = '0'.
3, Valid during display period only (see Figure 5); otherwise no character or background information is displayed as blanking is determined by the Picture
On. (No blanking if PO = '1 ').
February 25, 1987
13·58
Signetics Linear Products
Product Specification
Teletext Character Generator
SAA5050j55
Figure 9. SAA5050 Character Set (English)
February 25, 1987
13-59
Signetics Linear Products
Product Specification
Teletext Character Generator
SAA5050/55
Figure 10. SAA5050 Character Set (US ASCII)
February 25. 1987
13-60
SAA5230
Signetics
Teletext Video Processor
Product Specification
Linear Products
PIN CONFIGURATION
DESCRIPTION
FEATURES
The SAA5230 is a bipolar integrated
circuit intended as a successor to
SAA5030. It extracts teletext data from
the video signal, regenerates teletext
clock, and synchronizes the text display
to the television syncs. The integrated
circuit is intended to work in conjunction
with CCT (SAA5040, Computer Controlled Teletext), EUROM SAA5350 or
other compatible devices.
• Adaptive data slicer
• Data clock regenerator
• Sync separator, line phase
detector, and 6MHz VCO forming
display phase-locked loop (PLL)
• Performs all of the functions of
the SAA5030 except field sync.
integration and signal quality
detection
• When used with the SAA5240, a
microprocessor-controlled
teletext/data acquisition system
can be easily implemented
• Good data slicing capability in
the presence of echoes and
noise with high-frequency loss
compensation
• On-chip clock regeneration
circuitry can operate with
different data rates
• On-chip PLL allows display to be
easily lOCked to a VCR
• Minimal number of external
components/ adjustments
N Package
SYNC OUT
1
L~~EIOS~L
2
HFFILTER
3
STORE HF
4
STORE
AMPLITUDE
ZERO SLl~~~
23
EX DATA IN 7
~tfrlt'h CAP
22 fJ-NDCASTlE
DATA
TIMING
STORE
PHASE
TOP VIEW
APPLICATIONS
• Teletext
• Data sliCing and clock
regeneration
• Phase locking with incoming
video
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
-25°C to + 70°C
SAA5230N
28-Pin Plastic DIP (SOT-117)
II
ABSOLUTE MAXIMUM RATINGS
SYMBOL
Vec
PARAMETER
Supply voltage (Pin 16)
RATING
UNIT
13.2
V
TSTG
Storage temperature range
-65 to +150
°C
TA
Operating ambient temperature range
-25 to +70
°C
January 14, 1987
13-61
853-1144 87202
Signetics Linear Products
Product Specification
SAA5230
Teletext Video Processor
BLOCK DIAGRAM
January 14, 1987
13-62
Signetics Linear Products
Product Specification
SAA523 0
Teletext Video Processor
DC AND AC ELECTRICAL CHARACTERISTICS Vcc=12V; TA = 25°C with external components as shown in Figure 1,
unless otherwise specified.
LIMITS
SYMBOL
UNIT
PARAMETER
Vee
Supply voltage
Icc
Supply current
Min
Typ
Max
10.8
12.0
13.2
70
V
mA
Video Input and sync separator
V27 -13(P·P)
V27 -13(P·P)
Video input amplitude (sync to white)
Pin 2 Low
Pin 2 High
12 s1
Source impedance
V27 -13(P·P)
Sync amplitude
0.7
1.75
1
2.5
1.4
3.5
V
V
250
n
1
V
V
Video level select input
V2- 13
Input voltage Low
0
0.8
V2- 13
Input voltage High
2.0
5.5
V
12
Input current Low
0
-150
p.A
12
Input current High
0
1
mA
Text composite sync input (TCS)
V28 - 13
Input voltage Low
0
0.8
V
V28 - 13
Input voltage High
2.0
7.0
V
Scan composite sync Input (SCS)
V28 - 13
Input voltage Low
0
1.5
V
V28 - 13
Input voltage High
3.5
7.0
V
-100
+5
IlA
IlA
V
Select video sync from Pin 1
128
128
Input current
VI = 0 to 7V
VI = 10V to Vee
-40
-5
-70
Video composite sync output (VCS)
V25-13
Output voltage Low
0
0.4
V25 - 13
Output voltage High
2.4
5.5
V
125
Output DC current Low
0.5
mA
125
Output DC current High
-1.5
mA
tD
Sync separator delay time
0.5
Il s
Dual polarity buffer output
V1(p.P)
TCS sync amplitude
V1(p.P)
Video sync amplitude
11
Output current
V1
V1
DC output voltage
RL to ground (OV)
RL to Vee (12V)
January 14, 1987
0.45
-3
1.4
10.1
13-63
V
1
V
+3
mA
V
V
•
Signetics Linear Products
Product Specification
Teletext Video Processor
SAA523 0
DC AND AC ELECTRICAL CHARACTERISTICS (Continued) vee = 12V; TA = 25°C with external components as
shown in Figure 1, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
Sandcastle input
V22
V22
Phase-lock pulse
PL on (Low)
PL off (High)
0
3.9
3
5.5
V
V
V22
V22
Blanking pulse
CBB on (Low)
CBB off (High)
0
1.0
0.5
5.5
V
V
122
Input current
-10
+10
p.A
PLL
tp
tp
line sync timing
pulse width (using composite video)
pulse width (using scan composite sync)
tp
Pulse duration
period PL must be Low to make VCO free-run
2
3
Ils
IlS
100
IlS
SMHz-VCO (FS)
V17(p.P)
AC output voltage
1
V17 -13
DC output voltage
4
8
V
tR, tF
Rise and fall time
20
40
ns
C17 - 13
Load capacitance
40
pF
2
3
V
VCR
V1O - 13
VCR-mode on (Low)
0
0.8
V
VlO - 13
VCR-mode off (High)
2.0
Vee
V
110
Input current
-10
+10
!1A
Data amplitude of video input
Pin 2 Low
Pin 2 High
0.30
0.75
0.46
1.15
0.70
1.75
V
V
3
4
V
Data slicer
V27
V27
Teletext clock output
V14(P.P)
AC output voltage
2
V14 - 13
DC output voltage
4
CL
Load capacitance
tR, tF
Rise and fall times
tD
Delay of falling edge relative to other edges of TID
8
V
40
pF
20
30
45
ns
-20
0
+20
ns
3.0
4.0
V
Teletext data output
V1S(P_P)
AC output voltage
2.0
V1S- 13
DC output voltage
4
CL
Load capacitance
tR =tF
Rise and fall times
January 14, 1987
20
13-64
30
8
V
40
pF
45
ns
Signetics Linear Products
Product Specification
Teletext Video Processor
SAA5230
vc c
r--j~
r--jl":"
S.BnF
470
·ff
3.3k
'"F
47nF
H~
~h-
SANDCASTLE
INPUT
1.2k
~68
470nF
COMPOSITE
VIDEO
INPUT
"
28
127
1,"F
26
1m
pF
25
24
vcs
F6
pF
~ '0
56k
23
'2
SYNC OUT . - 4 - -
21
'0
,. 13"H I,
TTD
50
18
17
'6
1'5
pF
27
SAA5230
~'
1
~'.'k
I
.b
I'
I
1
~~~~~ I
LEVEL I
-!'5T
,14701" !I pF,!IPF
7
270
IPFI"FIPFI"F
SELECT..J:.
x =13.875MHz
DATA
'0
11
112
100
T
~3
114
D~"
TTC
;.~ XTAL
r.
13.87SMHz
1SPF
INPUT
Figure 1_ Test and Application Circuit
APPLICATION DATA
The function is quoted against the corresponding pin number.
1 Sync output to TV - Output with dual
polarity buffer, a load resistor to OV or + 12V
selects positive-going or negative-going
syncs.
2 Video Input Level Select - Low level
selects 1V input video level. With no connection, level floats High, selecting 2.5V level.
3 HF Filter - A capacitor connected to this
pin filters the video signal for the HF loss
compensator.
4 Store HF - The HF amplitude is stored by
a capacitor connected to this pin.
5 Store Amplitude - Store capacitor stores
the amplitude for the adaptive data slicer.
S Store Zero Level - Store capacitor
stores the zero level for the adaptive data
slicer.
7 External Data Input - Current input for
sliced teletext data from external device.
Active High level (current), low impedance
input.
8 Data Timing - A capacitor is connected
to this pin for timing of the adaptive data
9 Store Phase - A capacitor connected to
this pin stores the output signal from the
clock phase detector.
10 Video Tape Recorder Mode (VCR) Signal input to command PLL into (short time
constant mode), enable text to synchronize to
a video tape recorder. Active is Low. If not
connected, the level is High.
11 Crystal - A 13.875MHz crystal (2 X
data rate) in series with a capacitor is connected to this pin.
12 Clock Filter - A filter for the clock signal
is connected to this pin (6.938MHz).
13 Ground (OV)
14 Teletext Clock Output - TIC for CCT
(Computer Controlled Teletext).
15 Teletext Data Output -
TID for CCT.
1S Supply Voltage Vce +12V.
Typical value
17 F6 - 6MHz output clock for timing and
sandcast\e generation in CCT.
18 Oscillator Output (SMHz) - A seriesresonant circuit is connected between this pin
and Pin 20 to control the nominal frequency
of the VCO.
slicer.
January 14, 1987
13-65
19 Filter 2 - A filter for the line phase
detector is connected to this pin. The filter
has a short time constant and is used in video
recorder mode and while the loop is locking
up.
20 Oscillator Input (SMHz) -
See Pin 18.
21 Filter 1 - A long time constant filter for
the line phase detector is connected to this
pin.
22 Sandcastle Input - This input accepts a
sandcastle waveform, which is formed from
PL and CBB from the CCT. For signal timing,
see Figure 2.
23 Pulse Timing Resistor - A connected
resistor defines the current for the pulse
generator.
24 Pulse Timing CapaCitor - A connected
capacitor is used for timing of the pulse
generator.
25 VCS Output - Video composite sync
output signal for CCT.
26 Black Level - A capacitor connected to
this pin stores the black level for the adaptive
sync separator.
27 Composite Video Input - The composite video is fed to this input via a clamp
capacitor.
•
Product Specification
Signetics Linear Products
SAA5230
Teletext Video Processor
sync circuit. SGS is expected if there is no
load resistor at Pin t.
28 Sync Input - Input for text composite
sync (TGS) from GGT or SGS from external
VIDEO
SIGNAL
(PIN 27)
SANDCASTLE
INPUT
(PIN 22)
LJ
l
SV
-~----~------------~--~--------------------~========~:
..- - . . . . . I..
o 1.5
I
4.7
8.5
33.5
Figure 2. Sand castle Waveform and Timing
January t 4. t 987
13-66
Signetics
SAA5350
Single-Chip Color CRT
Controller (625-Line System)
Product Specification
Linear Products
DESCRIPTION
The SAA5350 EUROM1 is a single-chip
VLSI NMOS CRT controller capable of
handling all display functions required by
the CEPT videotex terminal, model A4.
Only minimal hardware is required to
produce a videotex terminal using EUROM - the simplest configuration
needs just a microcontroller and 4kB of
display memory.
FEATURES
• Minimal additional hardware
required
• Screen formats of 40/80
character by 1-to-25 row display
• 512 alphanumeric or graphic
characters on-chip or extendable
off-chip
• Serial attribute storage (STACK)
and parallel attribute storage
• Dynamically redefinable character
(ORCS) capability over full field
• Interfaces with 8/16-bit
microprocessors with optional
direct memory access
• On-chip scroll map minimizes
data to be transferred when
scrolling
• On-chip color map RAM followed
by three non-linear digital-toanalog converters which
compensate for CRT non-linearity
• Memory interface capable of
• Programmable local status row
• Three synchronization modes:
PIN CONFIGURATION
N Package
- stand-alone: built-in oscillator operating
with an external 6MHz crystal
Vee
RtW(S/R)
- simple slave: directly synchronized from
AS
the source of text composite sync
OR
- phase-locked slave: indirect synchroni-
zation allows picture-in·text displays
(e.g., VCRIVLP video with text overlay)
• On-Chip timing composite sync
output
• Zoom feature which allows the
height of any group of rows to
be increased to enhance legibility
DTAcK
LOS
UDS
FSJDDA
TCS
A10/D9
F6
APPLICATIONS
• Videotex
• Teletext
• Microprocessor-controlled display
systems
• General purpose CRT controller
applications
• Display systems requiring the
display of text, graphics, and
analog video in the same video
frame
F1/6
AB/D7
A7/D6
SAND
A6/0S
CLKO
A5/04
Oii
A4/D3
VDS
A3/D2
A2JDl
A1JDO
Vss
TOP VIEW
ORDERING INFORMATION
,----------------,-----------r--------,
I -_ _ _D_E_S_C_R_I_P_TI_O_N_ _ _ _I-_T_EM_P_ER_A_T_U_R_E_R_A_N_G_E_+-_O_R_D_E_R_C_O_D_E--j
40-Pin Plastic DIP (SOT-129)
-20"C to +70"C
SAA5350N
'--______--'--_____..L..._ _ _ _ _ _ _ _ _- - '_ _ _ _ _ _--'
supporting multi-page terminals.
EUROM can access up to 128kB
of display memory
• Programmable cursor
NOTE:
1. For a 525-line system, please use the SM5355. Data sheets are available upon request.
NOTICE: The SAA5350 will be replaced during 1987 by an upgraded SAA5351. Please consult factory for production status
January 14, 1987
13-67
853-1141 87201
•
Signetics Unear Products
Product Specification
Single-Chip Color CRT Controller (625-Line System)
SAA5350
PIN DESCRIPTIONS
PIN NO.
SYMBOL
1
TEST
2
BUFEN
3
RE
4 to 19
A16 to A1/D15 to DO
DESCRIPTION
Input to be connected to Vss
Buffer enable input to the 8·bit link·through buffer
Register enable input. This enables A1 to A6 and UDS as inputs, and D8 to D15
as input/ outputs
Multiplexed address and data bus input/outputs. These pins also function as the B·
bit link·through buffer
20
Vss
Ground (OY)
21
REF
Analog reference input
22
23
24
iJ
Analog outputs (signals are gamma·corrected)
25
VDS
Switching output for dot, screen (row), box, and window video data; for use when
video signal is present (e.g., from TV, VLP, alpha + photographic layer). This output
is Low for TV display and High for text and will interface directly with a number of
color decoder ICs (e.g., TDA3560, TDA3505)
26
OD
Output disable causing R, G, B, and VDS outputs to go to high·impedance state.
Can be used at dot·rate
27
CLKO
12MHz clock output for hard·copy dot synchronization (referenced to output dots)
28
SAND
Sandcastle feedback output for SAA5230 teletext video processor or other circuit.
Used when the display must be locked to the video source (e.g., VLP). The
phase-lock part of the sandcastle waveform can be disabled to allow free·running
of the SAA5230 phase·locked loop
29
F1/6
30
F6
31
VCS/OSCO
32
TCS
33
FS/DDA
34
UDS
35
LDS
36
DTACK
37
38
BR
AS
39
R/W (S/R)
40
VDD
January 14, 1987
1MHz or 6MHz output
6MHz clock input (e.g., from SAA5230). Internal AC coupling is provided.
Video composite sync input (e.g., from SAA5230) for phase reference of vertical
display timing when locking to a video source (e.g., VLP) or in stand·alone sync
mode, output from internal oscillator circuit (fixed frequency)
Text composite sync input/output depending on master/slave status
Field sync pulse output or defined·display·area flag output (both referenced to
output dots)
Upper data strobe input/output
Lower data strobe output
Data transfer acknowledge (open drain output)
Bus request to microprocessor (open drain output)
Address strobe output to external address latches
Read/write input/output. Also serves as send/receive for the link·through buffer
Positive supply voltage (+ 5Y)
13-68
Signetics Linear Products
Product Specification
Single-Chip Color CRT Controller (625-Line System)
SAA5350
BLOCK DIAGRAM
SAND
CLKO
BUFEN
F1/6
TCS
RJW (SIR)
As
FiE
TEST
VCSI
OSCO
DRCS DOT &
MODE DATA
SHIFT REGISTER
COLQRMAP
ROM
DOT DATA
ROW BUFFER
ATTRIBUTE
LOGIC
DIGITAL-TO-
CHARACTER
ANALOG
CONVERTER
ROM
25
VDS
24
R
23
G
21
REF
26
00
22
B
•
January 14, 1987
13-69
Product Specification
Signetics Linear Products
Single-Chip Color CRT Controller (625-Line System)
SAA5350
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
UNIT
Voo
Supply voltage range (Pin 40)
PARAMETER
-0.3 to +7.5
V
VIMAX
Maximum input voltage (except F6,
TCS, REF)
-0.3 to +7.5
V
VIMAX
Maximum input voltage (F6, TCS)
-0.3 to + 10.0
V
VREF
Maximum input voltage (REF)
-0.3 to +3.0
V
VOMAX
Maximum output voltage
-0.3 to +7.5
V
lOMAX
Maximum output current
10
mA
TA
Operating ambient temperature range
-20 to +70
"C
TSTG
Storage temperature range
-65 to +125
"C
NOTE:
Outputs other than CLKO, OSCO, R, G, B, and Vl5S are short-circuit protected.
DC ELECTRICAL CHARACTERISTICS Voo = 5V ± 10%; VSS = OV; TA = -20 to +70"C, unless otherwise specified.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
4.5
5.0
Max
Supply
Voo
Supply voltage (Pin 40)
laD
Supply current (Pin 40)
5.5
V
350
mA
V
Inputs F6 1
Slave modes (Figure 1)
VI(P_P)
Input voltage (peak-to-peak value)
1.0
7.0
±Vcc
Input peaks relative to 50% duty factor
0.2
3.5
V
III
Input leakage current at VI
20
p.A
CI
Input capacitance
12
pF
=0
to 10V; TA = 25"C
Stand-alone mode (Figure 2)
C1
Series capacitance of crystal
28
Co
Parallel capacitance of crystal
7.1
RR
Resonance resistance of crystal
G
Gain of circuit
pF
pF
60
n
TBD
VIV
V
BUFEN, RE, 00
VIL
Input voltage Low
0
0.8
VIH
Input voltage High
2.0
6.5
V
II
Input current at VI
-10
+10
fJA
CI
Input capacitance
7
pF
2.7
V
=0
to Voo + 0.3V; T A = 25"C
REF (Figure 3)
VREF
Input voltage
RREF
Resistance (Pin 21 to Pin 20) with REF supply and R, G, B
outputs OFF
January 14, 1987
0
13-70
1 to 2
125
n
Signetics Linear Products
Product Specification
SAA5350
Single-Chip Color CRT Controller (625-line System)
DC ELECTRICAL CHARACTERISTICS (Continued)
VDD = 5V ± 10%; Vss = OV; TA = -20 to + 70'C, unless otherwise
specified.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
Outputs
SAND
VOH
Output voltage high level at 10 = 0 to -301lA
4.2
Val
Output voltagA intermediate level at 10 = -30 to + 301lA
t.3
VOL
Output voltage low level at 10 = 0.2mA
CL
Load capacitance
0
VDD
2.0
V
2.7
V
0.2
V
30
pF
F1/6, CLKO, DDAIFS
VOH
Output voltage High at 10H = -2001lA
VOL
Output voltage Low at 10L = 3.2mA
CL
Load capacitance
2.4
VDD
V
0
0.4
V
50
pF
LDS, AS
VOH
Output voltage High at 10H = -200flA
VOL
Output voltage Low at 10L = 3.2mA
CL
Load capacitance
2.4
VDD
V
0
0.4
V
200
pF
DTACK, BR (open·drain outputs)
VOL
Output voltage Low at 10L = 3.2mA
CL
Load capacitance
COFF
Capacitance (OFF state)
0
0.4
V
t50
pF
7
pF
V
R, G, B2
VOH
Output voltage High at 10H = -1 001lA; VREF = 2.7V 3
VOL
Output voltage Low at 10L = 2mA
0.4
2.4
V
ROBL
Output resistance during line blanking
150
no
COFF
Output capacitance (OFF state)
12
pF
10FF
Output leakage current (OFF state) at VI = 0 to VDD + 0.3V;
TA = 25'C
-10
+10
IlA
VOH
Output voltage High AT 10H = -2501lA
2.4
VDD
V
VOL
Output voltage Low at 10L = 2mA
0
0.4
V
VOL
Output voltage Low at 10L = 1mA
0
0.2
V
10FF
Output leakage current (OFF state) at VI = 0 to VDD+ 0.3V;
TA = 25'C
-10
+10
IlA
2.0
6.0
V
VDS
Input/Outputs
VCS/OSCO
VIH
Input voltage High
VIL
Input voltage Low
II
Input current (output OFF) at VI = 0 to VDD + 0.3V; T A = 25'C
CI
Input capacitance
January 14, 1987
13-71
0
0.8
V
-10
+10
IlA
10
pF
•
Product Specification
Signetics linear Products
Single-Chip Color CRT Controller (625-line System)
SAA5350
DC ELECTRICAL CHARACTERISTICS (Continued) Vee=5V ±10%; Vss= OV; TA=-20 to + 70°C, unless otherwise
specified.
LIMITS
PARAMETER
SYMBOL
UNIT
Min
Typ
Max
'fCS
VIH
Input voltage High
3.5
10.0
V
VIL
Input voltage Low
0
1.5
V
-10
+10
pA
10
pF
II
Input current at VI = 0 to Vee + 0.3V; TA = 25°C
CI
Input capacitance
VOH
Output voltage High at IOH = -200 to 100pA
VOL
Output voltage Low at IOL = 3.2mA
CL
Load capacitance
2.4
6.0
V
0
0.4
V
50
pF
V
A1/DO to A16/D15, UDS, R/W
VIL
Input voltage Low
0
0.8
VIH
Input voltage High
2.0
6.0
V
II
Input current at VI = 0 to Vee + 0.3V; TA = 25°C
-10
+10
IlA
10
pF
2.4
Vee
V
0
0.4
V
200
pF
CI
Input capacitance
VOH
Output voltage High at IOH = -200pA
VOL
Output voltage Low at IOL = 3.2mA
CL
Load capacitance
January 14, 1987
13-72
Product Specification
Signetics Linear Products
Single-Chip Color CRT Controller (625-Line System)
SAA5350
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
Timing F6 (Figure 1)
tR, tF
Rise and fall times
10
80
ns
fF6
Frequency
5.9
6.1
MHz
CLKO, F1/6, R, G, B, VOS, FS/OOA, 004 , 5 (see Figure 4)
tCLKH
CLKO High time
30
ns
tCLKL
CLKO Low time
20
ns
tCLKR
!cLKF
CLKO rise and fall times
10
ns
tVCH
CLKO High to R, G, B, VDS change
10
tvoc
R, G, B, VDS valid to CLKO rise
10
ns
!cov
CLKO High to R, G, B, VDS valid
60
ns
tFOD
CLKO High to R, G, B, VDS floating after OD fall
30
ns
tvs
Skew between outputs R, G, B, VDS
20
ns
tVR, tVF
R, G, B, VDS rise and fall times
30
ns
tAOD
CLKO High to R, G, B, VDS active after OD rise
tCOD
CLKO High to FS/DDA change
tDOC
FS/DDA valid to CLKO rise
tF1H
F1 High time 6
500
ns
tF1L
F1 Low time6
500
ns
tF6H
F6 High time
83
ns
tF6L
F6 Low time
83
tODS
OD to CLKO rise setup
45
ns
tODH
OD to CLKO High hold
0
ns
ns
0
ns
55
ns
ns
5
ns
Memory access limlng 7, B, 9 (see Figure 5)
UOS, LOS, AS
tcvc
Cycle time
tSM
UDS High to bus-active for address output
75
ns
tASU
Address valid setup to AS fall
20
ns
tAsH
Address valid hold from AS Low
20
ns
tAFS
Address float to UDS fall
0
ns
tATD
AS Low to UDS fall delay
50
ns
tHDS
UDS, LDS High time
220
ns
tLDS
UDS, LDS Low time
200
ns
tHAS
AS High time
125
ns
tLAS
AS Low time
320
ns
tAUH
AS Low to UDS High
305
ns
tDSU
Data valid setup to UDS rise
30
ns
tDSH
Data valid hold from UDS High
0
ns
tUAS
UDS High as AS rise delay
0
tAFA
AS Low to data valid
January 14, 1987
500
ns
ns
270
13-73
ns
•
Signetics Linear Products
Product Specification
Single-Chip Color CRT Controller (625-Line System)
SAA5350
AC ELECTRICAL CHARACTERISTICS (Continued)
LIMITS
SYMBOL
PARAMETER
UNIT
Min
Typ
Max
Link-through buffers7, 8 (see Figure 6)
tSEA
BUFEN Low to output valid
100
ns
tLTD
Link-through delay time
85
ns
tlFR
Input data float prior to direction change
tOFR
Output float after direction change
60
ns
tSEO
Output float after BUFEN High
60
ns
0
ns
Microprocessor READ from EUROM (Figure 7)
tRUO
R/W High setup to UDS fall
tUOA
UDS Low to returned-data access time
0
210
ns
tREA
RE LOW to returned data access time
210
ns
tOTL
Data valid to DTACK Low delay
20
tOLU
DTACK Low to UDS rise
0
tOTR
DDS
0
tOSA
UDS High to address hold
0
ns
tOSH
UDS High to data hold
10
ns
tSRE
UDS High to RE rise
10
ns
tUOR
UDS High to R/W fall
0
toso
UDS Low to DTACK Low
190
tAUL
Address valid to UDS fall
0
ns
High to DTACK rise
ns
ns
ns
50
ns
ns
260
ns
Microprocessor WRITE to EUROM (Figure 8)
twCY
Write cycle time lO
500
ns
twuo
R/W Low setup to UDS fall
0
ns
tRES
RE Low to UDS fall
30
ns
tASS
Address valid to UDS fall
30
ns
tLUS
UDS Low time
100
ns
toss
Data valid to UDS rise
80
tOTA
UDS Low to DTACK Low
0
tOLU
DTACK Low to UDS rise
0
tOTA
UDS High to DTACK rise
0
tOSH
UDS High to data hold
0
ns
tOSA
UDS High to address hold
a
ns
tSRE
UDS High to RE rise
10
ns
tuow
UDS High to R/W rise
a
ns
ns
60
ns
ns
50
ns
FI/6 to memory access cycle (Figure 9)
tUF6
UDS High to F6 (component of F1/6) rise
20
ns
tF6U
F6 (component of F1/6) High to UDS rise
40
ns
January 14, 1987
13-74
Product Specification
Signetics Linear Products
SAA5350
Single-Chip Color CRT Controller (625-line System)
AC ELECTRICAL CHARACTERISTICS (Continued)
I
SYMBOL
I
PARAMETER
I
Synchronization and blanking TCS, SAND, FS/DDA
I
See Figure 10 for timing relationships and Figure 11 for vertical
sync and blanking waveforms.
I
LIMITS
Min
I
I
Typ
I
I
Max
I
I
UNIT
I
NOTES:
I. Pin 30 must be biased externally as it is internally AC-coupled.
2. 16-level analog voltage outputs.
3. Output voltage guaranteed when programmed for top level.
4. CLKO, R, G, B, FI/6, VDS: CL = 2SpF; j'g/DDA: CL = SOpF.
S. CLKO, FI/6, VDS, j'g/DDA: reference levels = 0.8 to 2.0V; R, G, B: reference levels = 0.8 to 2.0V with VREF = 2.7V.
6. These times may momentarily be reduced to a nominal 83n5 in slave-sync mode at the moment of resynchronization.
7. CL = 150pF.
B. Reference levels = O.B to 2.0V.
9. F6 input at 6MHz.
10. Microprocessor write cycle times of less than 500ns are permitted but often result in wait states being generated; the precise timing of DTACK will
then depend on the internal synchronization time.
14----11f.,.-----I
WF20300S
Figure 1. F6 Input Waveform
SAA535Q
c,
30
F6
20 pF
1M
TL.._...------IT
R,
-c~
CD
20 pi'
NOTE:
1. Catalog number of crystal: 4322 143 04101.
a. Osclllator Circuit for SAA5350
Stand·Alone Sync Mode
b. Equivalent Circuit of Crystal at
Resonance (see Characteristics for
Values)
Figure 2
January 14, 19B7
13·75
•
Signetics Unear Products
Product Specification
Single-Chip Color CRT Controller (625-Line System)
SAA5350
, . - - - - - - - - - - - R R.. - - - - - - - - - - " ' " \
R. G, OR e ANALOG
OUTPUT
Figure 3. Circuit Arrangement Giving One-of-Slxteen Reference Voltage Levels for the R. G or B Analog Outputs
Wf20231S
Figure 4. Video Timing
January 14, 1987
13-76
Product Specification
Signetics Linear Products
SAA5350
Single-Chip Color CRT Controller (625-line System)
00·1)15
Al·AI6
V
/
ADDRESS
OUTPUT
-~-r
'\
DATA INPUT
I-IoSH~
I-IosutH09
_I""u_
Iul.
~"SH"'"
I--'"s-
r\
!j
-
'.ro
'AF'
'HAS
-'UAS
tAUH
~-----------------------tus--------------------------~
~------------------------------------~YC--------------------------------~~
Figure 5. Memory Access Timing
Figure 6. Timing of Link-Through Buffers
•
January 14, 19B7
13-77
Signetics Unear Products
Product Specification
Single-Chip Color CRT Controller (625-Line System)
SAA5350
ADDRESS VAUD
tAU\.
~----------t~------------~
Iii!
-~.
Figure 7. Timing of Microprocessor Read From EUROM
~D'-wma~
A,e!D,. """'"
__ 'I------------------f'
Figure 8. Timing of Microprocessor Write to EUROM
January 14. 1987
13-78
""fL'""fJ.LI.l.I.
Signetics Linear Products
Product Specification
Single-Chip Color CRT Controller (625-Line System)
SAA5350
~v
F1/6
Figure 9. Timing of F1/6 to Memory Access Cycle
TCS~
1
(LINE SYNC COMPONENT)
r--
SAND-n
(SANDCASTLE OUTPUT
SAND
(SANDCASTLE OUTPUT
WITHOUT PHASE LOCK)
..._ _ _ _ _ _ _ •__ - - - '
I
r--+---!
INCLUDING PHASE LOCK)
-I-
I
l
FS/DDA
OJ,lS 1.5ps
4.75pS
a.spa
16.5IJS
33.5",s
56.5ps
5V
2V
OV
2V
ov
2V
I
(DDASHOWN)
2V
OV
OV
64.s
NOTE:
1. All timings are nominal and assume fF6 '" 6MHz.
Figure 10. Timing of Synchronization and Blanking Outputs
f - 4 - - - - - - - - - - - - - - F I E L D BLANKING (25 LINES + LINE BLANKING)I---------------t~
5 EQUALIZING 5 BROAD
PULSES
PULSES
5 EQUALIZING
PULSES
(2'. LINE: 1..(2'" LINES)
END OF 4TH FIELD (ODD)
I
I
(2'" LINES)
I
START OF 1ST FIELD (EVEN)
I
•
NOTE:
1. Separation of broad pulses = 4.75Jls; equalizing pulse widths = 2.25p.5,
Figure 11. Vertical Synchronization and Blanking Waveforms
January 14, 1987
13-79
Product Specification
Signetics Unear Products
Single-Chip Color CRT Controller (625-Line System)
SAA5350
R
G
B
SYNC
8051
Figure 12. Basic Videotex Decoder Configuration
BASIC VIDEOTEX DECODER
CONFIGURATION
required to define explicitly every character in
a row.
A basic, practical decoder configuration is
shown in Figure 12. Reference should also be
made to the Block Diagram.
The addresser is used for row buffer filling
and for fetching screen colors, and during the
display time it is also used for addressing
ORCS characters.
Character and attribute data is fetched from
the external memory, processed by the row
buffer fill logic according to the stack coding
scheme (in stack mode) and then fed into one
half of the dual display row buffer. The data
fetch process takes place during one lineflyback period (per row) and, since time is
required to complete the fill, the other half of
the dual row buffer Is used for display. The
row buffers exchange functions on alternate
rows - each holds the 40 columns of 32 bits
January 14, 1987
Timing
The timing chain operates from an external
6MHz clock or an on-chip fixed-frequency
crystal oscillator. The basic video format is 40
characters per row, 24/25 rows per page,
and 10 video liries per row. EUROM will also
operate with 20/21 rows per page and 12
video lines per row. The two extra lines per
row are added symmetrically and contain
13-80
background color only for ROM-based alphanumeric characters. ORCS characters, block
and smooth mosaics, and line drawing characters occupy all 12 lines.
The display is generated to the normal 625line/50Hz scanning standard (interlaced or
non-interlaced). In addition to composite sync
(Pin 32) for conventional timebases, a clock
output at lMHz or 6MHz (Pin 29) is available
for driving other videotex devices, and a
12MHz clock (Pin 27) is available for hardcopy dot synchronization. A defined-displayarea timing signal (Pin 33) simplifies the
application of external peripherals such as a
light pen; this signal is nominally coincident
with the character dot information.
Signetics Linear Products
Product Specification
Single-Chip Color CRT Controller (625-Line System)
Character Generation
EUROM supports eight character tables,
each of (nominally) 126 characters. Four
tables are in on-chip ROM and contain fixed
characters, and four are stored in an external
RAM. The contents of the fixed character
SAA5350
tables (Tables 0 to 3) are shown in Figures 13
and 14.
Aa OIlPgp
lEa!!lAQaq
Ee"2BRbr
UUaaCSCS
caa4DTdt
Eeo5EUeu
iiij6FV:fv
~.
0
0
0
0
1
0
0
0
0
0
1
1
1
1
0
0
I
32 Bits per character position
To reduce the amount of memory required,
attributes in APDC are coded using a Stack
architecture. Such a system exploits the natural redundancy of normal text by allocating
memory dynamically. It allows the external
memory to be reduced to 2kbytes per screen.
This has beneficial side effects; for example,
it reduces the memory bandwidth for a given
display, reducing the memory speed required
or increasing the time available for microprocessor operations.
pointer
character-code. 7 bit
::>
attribute and character
character memory
group memory
Example of Dynamic Allocation of Memory Using Coding Stack
Stack coding used in APDC
B7
B6
B5
B4
B3
B2
B1
BO
COMMENTS
P
0
0
F4
F3
F2
F1
FO
P
0
84
83
B2
B1
BO
H4
0
1
1
1
1
1
1
H3
L
0
0
0
1
1
1
H2
T2
0
1
1
0
0
1
H1
T1
G
0
1
0
1
0
HO
TO
D
U
I
C
W
H
Foreground color (PIBGR)
Transparent = 000000
Background color (PIBGR)
Transparent = 00000
Flash
Character table and lock bit
Size. double height and width
Underline (Lining)
Invert
Conceal
Window/Box
Marked area
(not a display attribute)
Protected area
(not a display attribute)
P
P
P
P
P
P
P
P
0
1
1
1
1
1
1
1
P
P
The fourth character in the row has its painter
bit set, and so the first (or, generally, the next)
attribute byte is fetched from memory. This
byte also has its pointer bit set, and so the
next attribute byte is also fetched, and so on.
The fourth attribute byte has a clear pointer
bit indicating that it is the last in the group.
The next character byte is now fetched. The
pointer being clear, this character is displayed
with the same attributes as those set for the
previous one.
13-98
The stack system records only the position in
a row where attribute-changes occur, with no
restriction upon how many attribute-changes
apply to anyone character. The restriction to
40 attribute-changes in a row has been carefully studied, and not found in practice to be
an editorial limitation.
The actual coding of attributes, a form of
Huffman coding, is shown below.
NOTE:
Previously published as "Technical Information
137," ELCOMA, October 1984.
Signetics
Section 14
SMPS for TV/Monitor
Linear Products
INDEX
TDA2582
TEA1039
Control Circuit for Power Supplies.......................................... 14-3
Control Circuit for Switched-Mode Power Supply ....................... 14-12
II
March, 1987
TDA2582
Signetics
Control Circuit For Power
Supplies
Product Specification
Linear Products
DESCRIPTION
The TDA2582 is a monolithic integrated
circuit for controlling power supplies
which are provided with the drive for the
horizontal deflection stage.
FEATURES
• Voltage-controlled horizontal
oscillator
" Phase detector
CD Duty factor control for the
negative-going transient of the
output signal
o Duty factor increases from zero
to its normal operation value
o Adjustable maximum duty factor
o Overvoltage and overcurrent
protection with automatic restart
after switch-off
o Counting circuit for permanent
switch-off when n-times
overcurrent or overvoltage is
sensed
• Protection for open-reference
voltage
• Protection for too-low supply
voltage
• Protection against loop faults
• Positive tracking of duty factor
and feedback voltage when the
feedback voltage is smaller than
the reference voltage minus 1.5V
• Normal and "smooth" remote
ON/OFF possibility
PIN CONFIGURATION
N Package
PHASEDET
OUT
15 ~EACTANCE
FBPULSE
PQSIN
REF
FRECIN
RESTARTCT
CAPfRCIN
SLDWSTART
& TRANSFER
OVERCURRENT
14
~~~~L~CE
13
~~~~~G
12
iM~ST ISMOOTH
PROT. IN
OVERVOLTAGE
PROT. IN
FEEDBACK
9 POS SUPPLY
VOlliN - , ,_ _ _...s--
TOP VIEW
APPLICATIONS
• Video monitors
• Power supplies
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
-25°C to +80°C
TDA2582N
16·Pin Plastic DIP (SOT·38)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
V9 -
16
Supply voltage at Pin 9
Vll
-16
Voltage at Pin 11
RATING
UNIT
14
V
o to 14
V
111M
Output current (peak value)
40
rnA
PTOT
Total power dissipation
280
mW
TSTG
Storage temperature
-65 to +150
°C
TA
Operating ambient temperature
-25 to +80
°C
II
February 12, 1987
14-3
853·1177 87584
Signetics Linear Products
Product Specification
TDA2582
Control Circuit For Power Supplies
BLOCK DIAGRAM
J1J
33k
*:1444-2.7nF
--"""""-------1
15
8
13
ERROR
AMPLlF1ER
OSCILLATOR
~~
~
78.
2k
3.2k
2k
I
~
KV~ Gf1
~ r
10
~g
LW
hv.-
TDA2582
t
PHASE
DETECTOR
PULSE WIDTH
MODUt.ATOR
ACTIVE FOR
+
~
~
2
4.2k
+
FLYBACK
..
~
~
.fUl.
FROMTDA2 571
r
t
~
3k
,.~
SLOW START
•
l
OUTPUT STAGE
3k
~
~
,~~.
INTERNAL SUPPl.Y
CIRCUIT
+ 2.1V
+
..
n
i
1l.7V
FORTRfF'ON
•
February 12, 1987
':'
"":"
OfIENoClRCUIT
REFERENCE DJODe
I--
G~
18
4
1k
-
MmATYP.
.,;.
12k
~"
10 DRIVE
TRANSISTOR BASE
!~,
7.7k
7
±
!~ 1"
11
1k
OVERVOLTAGE
PROTECTION
FORTRI~~
5
CUTOUT
CIRCUIT
DUTY FACTOR
ADJUSl'MENT
5k
~
+
MAXlMUM
12
I--
V1O-t.5V
~
J
-YI:
LDOPFAULT
PROTECTION
. . oF
CI-1.....
41k
33k
14
SETVO
~+Vo
"::"
REDUCE LOOP GAIN
I-
>uv FOR TRIP-ON
LOW SUPPlYVOLTAQE
PROTECTION
<9.4VFOR TRiP-ON
14-4
F"
12V
Signetics Linear Products
Product Specification
TDA2582
Control Circuit For Power Supplies
DC ELECTRICAL CHARACTERISTICS Vcc = 12V; V10. 16 = 6.1V; TA = 25°C, measured in Figure 3.
LIMITS
SYMBOL
UNIT
PARAMETER
Min
Typ
Max
V9 _ 16
Supply voltage range
10
12
14
V9 _ 16
Protection voltage too-low supply voltage
8.6
9.4
9.9
Ig
Supply current at I) = 50%
14
Ig
Supply current during protection
14
Ig
Minimum required supply current1
P
Power consumption
V
V
rnA
rnA
17
rnA
mW
170
Required input signals
VW-16
Reference vOltage 2
1ZS-161
Feedback input impedance
V1O - 16
High reference voltage protection: threshold voltage
V3- 16(P.P)
13M
±13
Horizontal reference signal (square-wave or differentiated;
negative transient is reference)
voltage-driven (peak-to-peak value)
current-driven (peak value)
switching-level current
V2- 16
Flyback pulse or differential deflection current
12M
Flyback pulse current (peak value)
-V6-16
+V6- 16
Overcurrent protection: 3 threshold voltage
V7-16
Overvoltage protection: (VREF = V10-16) threshold voltage
V4- 16
Remote-control voltage; switch-off4
V4-16
Remote-control voltage; switch-on
V5- 16
'Smooth' remote control; switch-off5
V5-16
'Smooth' remote control; switch-on
3
V
14
Remote-control switch-off current
1
rnA
5.6
6.1
6.6
200
7.9
8.4
5
-1
VREF-130
8.9
V
12
1.5
100
V
rnA
p.A
5
V
1.5
rnA
640
680
695
735
mV
mV
VREF-60
VREF-O
mV
1
600
640
V
kn
5.6
V
4.5
V
V
4.5
Delivered output signals
V11 _16(P.P)
Horizontal drive pulse (loaded with a resistor of 560n to + 12V
peak-to-peak value
111M
Output current; peak value
VCESAT
VCESAT
Saturation voltage of output transistor
at 111 = 20mA
at 111 = 40mA
I)
Duty factor of output pulse 6
14
Charge current for capacitor on Pin 4
15
Charge current for capacitor on Pin 5
110
Supply current for reference
February 12, 1987
11.6
V
200
40
rnA
400
525
mV
mV
98 ±0.8
0
110
120
0.6
14-5
1
%
p.A
p.A
1.45
rnA
•
Signetics Linear Products
Product Specification
Control Circuit For Power Supplies
TDA2582
DC ELECTRICAL CHARACTERISTICS (Continued) vce = 12V; V10-16 = 6.1V; TA = 25'C, measured in Figure 3.
LIMITS
PARAMETER
SYMBOL
UNIT
Min
Typ
Max
0.0003
0.0004
'C- 1
-104
-2
%
3
%
Oscillator
Temperature coefficient
Relative frequency deviation for V10 -16 changing from 5.6 to
6.6V
Oscillator frequency spread (with fixed ex1ernal components)
Frequency control sensitivity at Pin 15
fNOM = 15.625kHz
5
kHzlV
Phase control loop
loop gain of APC-system (automatic phase control)7
= 15,625kHz)
.:lf
Catching range (fNOM
t
Phase relation between negative transient of sync pulse and
middle of flyback
.:lt
Tolerance of phase relation
5
1300
kHz/!'S
2100
1
Hz
I1S
iOA
I1S
NOTES:
1. This value refers to the minimum required supply current that will start aI/ devices under the following conditions: Vg -16 = 10V; V'O -16 = 6.2V;
li=50%.
2. Voltage obtained via an external reference diode. Specified voltages do not refer to the nominal voltages of reference diodes.
3. This spread is inclusive temperature rise of the Ie due to warming up. For other ambient temperatures the values must be corrected by using a
temperature coefficient of typical- 1.85mV
4. See application information Pin 4.
5. See application information Pin 5.
t
6. The duty factor is speCified as follows: 6 - ~ X 100% (see Figure 1). After switch-on, the duty factor rises gradually from 0% to the steady value.
rc.
The relationship between VS_ 16 and the du"/"y factor is given in Figure 6 and the relationship between V12-16 and the duty factor is shown in
Figure 8.
7. For component values, see Block Diagram.
NOTE:
o-~ X
T
100%.
Figure 1
February 12, 1987
14-6
Product Specification
Signetics Linear Products
TDA2582
Control Circuit For Power Supplies
Vcc (+12V)
~z
9
-r
2
5
\1 ,1
-
+
::: 1O,F
3.9k
1k
10k
22k
:~ 150pF
f
~
~
'oADJ.
22k
+~1'F33 +i
;~'F +~O"'F
100nF
L..-
f--
22
'F
f--5.6k
022/Jf
470
~+
VERT. SYNC
7
1
,.
4
12
6
13
10
8
5
•
15
9
3
14
HOR.
sYNC
TDA2576
11
Vee
12
7
,----:~·1OOnF
f
270k
100nF
~~
~;J
~~
1%
t5k
PHASE
ADJUST ;.
~
"3k
+
:
Pl
7.5k
2%
~
18k
~
'CI
BY206
10} 3p.s).
The toroidal transformer in Figure 4a is for
obtaining a pulse representing the midflyback
from the deflection current. The connection of
the picture phase information is shown in
Figure 4b.
3 Reference Frequency Input - The input
circuit can be driven direolly by the squarewave output voltage from Pin 8 of the
TDA2571.
The negative-going transient switches the current source connected to Pin 1 from positive to
negative.
The input circuit is made such that a differentiated signal of the square-wave from the
TDA2571 is also accepted (this enables power
line isolation). The Input circuit switching level
is about 3V and the input impedance is about
8kn.
4 Restart Count Capacitor/Remote-Control Input -
Counting
An external capacitor (C4 = 471J.F) is connected between Pins 4 and 16. This capacitor
controls the characteristics of the protection
circuits as follows.
If the proteolion circuits are required to operate, e.g., overcurrent at Pin 6, the duty faolor
will be set to zero, thus turning off the power
supply.
After a short interval (determined by the time
constant on Pin 5), the power supply will be
restarted via the slow-start circuit.
If the fault condition has cleared, then normal
operation will be resumed. If the fault condition is persistent, the duty factor of the pulses
is again reduced to zero and the proteolion
cycle is repeated.
February 12, 1987
r------,
'I
--V-
~~2
i l t !L______ I
The current values are chosen such that the
correct phase relation is obtained when the
output signal of the TDA2571 is applied to
Pin 3.
With a resistor of 2 X 33kn and a capacitor of
2.7nF, the control steepness is O.55V/p.s (Figure 3).
"
A
TDA25a
~
~
a.
~
b_
Figure 4
The number of times this action is repeated
(n) for a persisting fault condition is now
determined by: n = C4/C5.
7 Over voltage Protection Input - When the
voltage applied to this pin exceeds the threshold level, the protection circuit will operate.
Remote Control Input
The tripping level is about the same as the
reference voltage on Pin 10.
For this application, the capacitor on Pin 4
has to be replaced by a resistor with a value
between 4.7 and 18kn. When the externallyapplied voltage V4.16 > 5.6V, the circuit
switches off; switching on occurs when
V4-16 < 4.5V and the normal starting-up procedure is followed. Pin 4 is internally conneoled to an emitter-follower, with an emitter
voltage of 1.5V.
5 Siow-Start and Transfer Characteristics
for Low Feedback Voltage -
stow-Start
An external shunt capacitor (C5 = 4.71J.F) and
resistor (R5 = 270kn) are connected between Pins 5 and 16. The network controls
the rate at which the duty factor increases
from zero to its steady-state value after
switch-on. II provides protection against
surges in the power transistor.
Transfer Charactetfstlc for Low
Feedback Voltages
The duty factor transfer charaoleristic for low
feedback voltages can be influenced by R5.
The transfer for three different resistor values
is given in Figure 6.
'Smooth' Remote ON/OFF
The ON/OFF information should be applied
to Pin 5 via a high-ohmic resistor; a high OFFlevel gives a slow rising voltage at Pin 5,
which results in a slowly decreasing duty
faolor.
6 Overcurrent Protection Input - A voltage proportional to the current in the power
switching device is applied to the integrated
circuit between Pins 6 and 16. The circuit trips
on both positive and negative polarity. When
the tripping level is reached, the output pulse
is immediately blocked and the starting circuit
is aolivated again.
14-10
8 Feedback Voltage Input - The control
loop input is applied to Pin 8. This pin is
internally connected to one input of a differ,
ential amplifier, functioning as an amplitude
comparator, the other input of which is conneoled to the reference source on Pin 10.
Under normal operating conditions, the voltage on Pin 8 will be about equal to the
reference voltage on Pin 10. For further
information refer to Figures 6 and 7.
9 12V Positive Supply - The maximum
voltage that may be applied is 14V. Where
this is derived from an unstabilized supply rail,
a regulator diode (12V) should be conneoled
between Pins 9 and 16 to ensure that the
maximum voltage does not exceed 14V.
When the voltage on this pin falls below a
minimum of 8.6V (typically 9.4V), the proteclion circuit will switch off the power supply.
10 Reference Input - An external reference diode must be connected between this
pin and Pin 16.
The reference voltage must be between 5.6
and 6.6V. The IC delivers about 1rnA .into the
external regulator diode. When the external
load on the regulator diode approaches this
current, replenishment of the current can be
obtained by conneoling a suitable resistor
between Pins 9 and 10. A higher referencevoltage value up to 7.5V is allowed when use is
made of a duty factor limiting resistor < 27kn
between Pins 12 and 16.
11 Output - An external resistor determines
the output current fed into the base of the
driver transistor. The output circuit uses an
NPN transistor with 3 series-conneoled clamping diodes to the internal 12V supply rail. This
provides a low-impedance in the "ON" state,
that is, with the drive transistor turned off.
Signetics Linear Products
Product Specification
TDA2582
Control Circuit For Power Supplies
12 Maximum Duty-Factor Adjustment!
Smoothing
Maximum Duty-Factor Adjustment
Pin 12 is connected to the output voltage of
the amplitude comparator (V 10 _ 8). This voltage is internally connected to one input of a
differential amplifier, the other input of which
is connected to the sawtooth voltage of the
horizontal oscillator. A high voltage on Pin 12
results in a low duty factor. This enables the
maximum duty factor to be adjusted by limiting the voltage by connecting Pin 12 to the
emitter of an NPN transistor used as a
voltage source.
Figure 8 plots the maximum duty factor as a
function of the voltage applied to Pin 12. If
some spread is acceptable, the maximum
duty factor can also be limited by connecting
a resistor from Pin 12 to Pin 16. A resistor of
12k>! limits the maximum duty factor to about
50%. This application also reduces the total
IC gain.
Smoothing
Any double pulsing of the IC due to circuit
layout can be suppressed by connecting a
capacitor of about 470pF between Pins 12
and 16.
13 Oscillator Timing Network - The timing
network comprises a capacitor between Pins
13 and 16, and a resistor between Pin 13 and
the reference voltage on Pin 10.
The charging current for the capacitor (C13)
is derived from the voltage reference diode
connected to Pin 10 and discharged via an
internal resistor of about 330>!.
14 Reactance-Stage Reference Voltage This pin is connected to an emitter-follower
which determines the nominal reference voltage for the reactance stage (lAV for reference voltage V10- 16 = 6.W). Free-running
frequency is obtained when Pins 14 and 15
are short-circuited.
15 Reactance-Stage Input - The output
voltage of the phase detector (Pin 1) is
connected to Pin 15 via a resistor. The
voltage applied to Pin 15 shifts the upper
level of the voltage sensor of the oscillator,
thus changing the oscillator frequency and
phase. The time-constant network is connected between Pins 14 and 15. Control sensitivity is typically 5kHzlV.
16 Negative Supply (Ground)
1,5
100
typ
Ab
(%1
6
I'l(,l
V12=2V
~ ,!>~o"'~
0,5
o
2.5V
,>o"'<}..
~.,., rf10"'~
50
0
a
so
0
6
b
(%1
-50
typ
o
50
a
SO V8 _ 10 1mVI 100
Figure 7. Duty Factor of Output Pulses as a Function of
Error Amplifier Input (Va-l0); V11).16 6.1V
6
typ
o
2
4
V12 - 16 (VI
6
Figure 8. Maximum Duty Factor limitation as a Function
of the Voltage Applied to Pin 12; Vl0-16 6.1V
=
February 12, 1987
va-16 IV)
Figure 6, Duty Factor of Output Pulses as a Function of
Feedback Input Voltage (V a-16) With R5 as a Parameter
and V12-16 as a Limiting Value; V10-16 = 6.1V
(%1
o
4
100
b (%1
Figure 5. Duty Factor Change as a Function of Initial
Duty Factor; at 1mV Error Amplifier Input Change;
tJ.VB-l0(P.P) = 1mV
50
3V
=
14-11
•
TEA1039
Signe1ics
Control Circuit for SwitchedMode Power Supply
Product Specification
Linear Products
DESCRIPTION
The TEA1039 is a bipolar integrated
circuit intended for the control of a
switched-mode power supply. Together
with an external error amplifier and a
voltage regulator (e.g., a regulator diode)
it forms a complete control system. The
circuit is capable of directly driving the
SMPS power transistor in small SMPS
systems.
FEATURES
• Wide frequency range
• Adjustable Input sensitivity
• Adjustable minimum frequency or
maximum duty factor limit
• Adjustable overcurrent protection
limit
• Supply voltage out-of-range
protection
• Slow-start facility
APPLICATIONS
• Home appliances
• Frequency regulation
• Flyback converters
• Forward converters
DESCRIPTION
November 14, 1986
TOP VIEW
TEMPERATURE RANGE
ORDER CODE
-25°C to +125°C
TEA1039U
14-12
U Package
PIN NO.
ORDERING INFORMATION
9-Pin Plastic SIP
PIN CONFIGURATION
1
CM
2
3
4
5
6
7
LIM
FB
RX
B
9
D~~';;nO~
SYMBOL
ex
OVOfCUrrent protecIIon Input
LImII oet1Ing Input
Feedback Input
External resistor connactIon
External capacitor connection
M
V••
Mode Input
Common
Q
Output
Va;
Poailive supply connection
853-0980 86554
Signetics linear Products
Product Specification
TEA1039
Control Circuit for Switched-Mode Power Supply
BLOCK DIAGRAM
Vee OUT OF RANGE
CM~f-----I
M~f----~--~--r-L-~
LIM
o=t-.....----t-l
FB
3
a
1.3V
-O.2SIRX
CX
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
Vee
Supply voltage range, voltage source
-0.3 to +20
V
lee
Supply current range, current source
-30 to +30
rnA
VI
Input voltage range, all inputs
-0.3 to +6
V
II
Input current range, all inputs
-5 to +5
rnA
Va-7
Output voltage range
-0.3 to +20
V
la
la
Output current range
output transistor ON
output transistor OFF
o to 1
-tOO to +50
A
rnA
TSTG
Storage temperature range
-65 to +150
·C
TA
Operating ambient temperature range
(see Figure 1)
FD
Power dissipation (see Figure 1)
November 14, 1986
UNIT
-25 to +125
·C
max. 2
W
14-13
IwrrH~~
HEATSINK
i\ATSINK
""'1\
\ \
o
\
-25
25
50
75
TA(·C)
100
125
Figure 1. Power Derating Curve
II
Signetlcs Linear Products
Product Specification
TEA1039
Control Circuit for Switched-Mode Power Supply
DC ELECTRICAL CHARACTERISTICS Vcc = 14, TA = 25°C, unless otherwise specilied.
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
14
20
V
7.5
9
11
12
rnA
rnA
Supply Vcc (Pin 9)
Vee
Supply voltage, operating
Icc
Icc
Supply current
atVee=11V
at Vee = 20V
dlecllee
dT
Vcc
dVeel dT
11
variation with temperature
-0.3
Supply voltage, internally limited
at ICC = 30mA
variation with temperature
23.5
%rC
28.5
V
mV/"C
18
Low supply threshold voltage
variation with temperature
9
10
-5
11
dVeel dT
V
mV/"C
Veemax
dVeel dT
High supply threshold voltage
variation with temperature
21
23
10
24.6
V
mV/"C
0.3
V
VCCmin
Feedback Input FB (Pin 3)
Va
7
Input voltage for duty factor = 0;
M input open
-IFB
Internal relerence current
Rg
Internal resistor Rg
0
0.5 IRX
rnA
130
kn
Limit setting Input LIM (Pin 2)
V27
Threshold voltage
-ILiM
Internal reference current
1
V
0.25 IRX
rnA
Overcurrent protection Input CM (Pin 1)
V, 7
dV, 7/dT
Threshold voltage
variation with temperature
tpHL
Propagation delay, CM input to output
300
370
0.2
420
500
mV
mVloC
ns
Oscillator connections RX and CX (Pins 4 and 5)
V47
dV4 71 dT
Voltage at RX connection
at -14 = 0.15 to 1mA
variation with temperature
6.2
7.2
2.1
8.1
V
mVloC
VLS
Lower saw100th level
VFT
Threshold voltage for output H to L transition in F
mode
VFM
Threshold voltage for maximum frequency in F mode
2.2
V
VHS
Higher saw100th level
5.9
V
0.25 IRX
rnA
-lex
Internal capacitor charging current, CX connection
fose
Oscillator frequency (output pulse repetition
Irequency)
dill
dl/I
-dT
dill
dl/I
dT
November 14, 1986
Minimum Irequency in F mode,
initial deviation
1.3
V
2
V
105
1
-10
variation with temperature
10
-15
variation with temperature
15
-0.16
14-14
%
%rc
0.034
Maximum Irequency in F mode,
initial deviation
Hz
%
%rC
Product Specification
Signetics Linear Products
Control Circuit for Switched-Mode Power Supply
DC ELECTRICAL CHARACTERISTICS
SYMBOL
At/t
At/t
variation with temperature
AT
UNIT
%
%I"C
10
%
%rc
0.034
Minimum output LOW time in D mode
at C5 = 3.6nF
At/t
15
-10
variation with temperature
--
MAX
0.2
Pulse repetition frequency in D mode,
initial deviation
AT
TYP
-15
variation with temperature
-
toLmin
MIN
Output LOW time in F mode,
initial deviation
AT
Allf
AI/f
(Continued) vee = 14, TA = 25°C, unless otherwise specified.
PARAMETER
-
TEA1039
1
Ils
0.2
%fOC
Output Q (Pin 8)
Va 7
AVa 7/AT
Output voltage LOW at la = 100mA
variation with temperature
Va 7
AVa 7/AT
Output voltage LOW at la = 1A
variation with temperature
FUNCTIONAL DESCRIPTION
The TEAl 039 produces pulses to drive the
transistor in a switched-mode power supply.
These pulses may be varied either in frequency (frequency regulation mode) or in width
(duty factor regulation mode).
The usual arrangement is such that the transistor in the SMPS is ON when the output of
the TEA1039 is HIGH, I.e., when the opencollector output transistor is OFF. The duty
factor of the SMPS is the time that the output
of the TEA1039 is HIGH divided by the pulse
repetition time.
Supply Vee (Pin 9)
The circuit is usually supplied from the SMPS
that it regulates. It may be supplied either
from its primary DC voltage or from its output
voltage. In the latter case an auxiliary starting
supply is necessary.
The circuit has an internal Vee out-of-range
protection. In the frequency regulation mode
the oscillator is stopped; in the duty factor
regulation mode the duty factor is made zero.
When the supply voltage returns within its
range, the circuit is started with the slow-start
procedure.
When the circuit is supplied from the SMPS
itself, the out-of-range protection also provides an effective protection against any
interruption in the feedback loop.
Mode Input M (Pin 6)
The circuit works in the frequency regulation
mode when the mode input M is connected to
ground (VEE, Pin 7). In this mode the circuit
produces output pulses of a constant width
but with a variable pulse repetition time.
The circuit works in the duty factor regulation
mode when the mode input M is left open. In
November 14, 1986
this mode the circuit produces output pulses
with a variable width but with a constant pulse
repetition time.
0.8
1.5
1.2
V
mVI"C
1.7
-1.4
2.1
V
mV/oC
Oscillator Resistor and
Capacitor Connections RX and
CX (Pins 4 and 5)
is HIGH until the voltage on the capacitor
exceeds the voltage on the feedback input
FB; it becomes HIGH again after discharge of
the capacitor (see Figures 5 and 6). An
internal maximum limit is set to the duty factor
of the SMPS by the discharging time of the
capacitor.
The output pulse repetition frequency is set
by an oscillator whose frequency is determined by an external capacitor C5 connected
between the CX connection (Pin 5) and
ground (VEE, Pin 7), and an external resistor
R4 connected between the RX connection
(Pin 4) and ground. The capaCitor C5 is
charged by an internal current source, whose
current level is determined by the resistor R4.
In the frequency regulation mode these two
external components determine the minimum
frequency; in the duty factor regulation mode
they determine the working frequency (see
Figure 2). The output pulse repetition frequency varies less than 1% with the supply
voltage over the supply voltage range.
The feedback input compares the input current with an internal current source whose
current level is set by the external resistor R4.
In the frequency regulation mode, the higher
the voltage on the FB input, the longer the
external capacitor C5 is charged, and the
lower the frequency will be. In the duty factor
regulation mode external capacitor C5 is
charged and discharged at a constant rate,
the voltage on the FB input now determines
the moment that the output will become
LOW. The higher the voltage on the FB input,
the longer the output remains HIGH, and the
higher the duty factor of the SMPS.
In the frequency regulation mode the output
is LOW from the start of the cycle until the
voltage on the capacitor reaches 2V. The
capacitor is further charged until its voltage
reaches the voltage on either the feedback
input FB or the limit setting input LIM, provided it has exceeded 2.2V. As soon as the
capacitor voltage reaches 5.9V the capacitor
is discharged rapidly to 1.3V and a new cycle
is initiated (see Figures 3 and 4).
For voltages on the FB and LIM inputs lower
than 2.2V, the capacitor is charged until this
voltage is reached; this sets an internal maximum frequency limit.
In the duty factor regulation mode the capacitor is charged from 1.3V to 5.9V and discharged again at a constant rate. The output
14-15
Feedback Input FB (Pin 3)
Limit Setting Input LIM (Pin 2)
In the frequency regulation mode this input
sets the minimum frequency, in the duty
factor regulation mode it sets the maximum
duty factor of the SMPS. The limit is set by an
external resistor R2 connected from the LIM
input to ground (Pin 7) and by an internal
current source, whose current level is determined by external resistor R4.
A slow-start procedure is obtained by connecting a capacitor between the LIM input
and ground. In the frequency regulation mode
the frequency slowly decreases from fMAX to
the working frequency. In the duty factor
regulation mode the duty factor slowly increases from zero to the working duty factor.
II
Signetics Linear Products
Product Specification
Control Circuit for Switched-Mode Power Supply
Overcurrent Protection Input
eM (Pin 1)
Output Q (Pin 8)
The output is an open-collector NPN transistor, only capable of sinking current. It requires
an external resistor to drive an NPN transistor
in the SMPS (see Agures 7 and 8).
A voltage on the eM input exceeding O.37V
causes an immediate termination of the output pulse. In the duty factor regulation mode
the circuit starts again with the slow-start
procedure.
100
80
60
40
:....
i
~
u,
~
3
4
,}~
~ ~ ......
~
10
8
8
1
~
i'...""",( 1I
20
~ ......
~ "'~
6 8 10
20
R4(kll)
40
80 80100
01'077215
Figure 2. Minimum Pulse Repetition Frequency In the Frequency Regulation Mode,
and Working Pulse Repetition Frequency In the Duty Factor Regulation Mode,
88 a Functfon of External Resistor R4 Connected Between RX and Ground with
External capacitor C5 Connected Between CX and Ground as a Parameter
November 14, 1986
14-16
TEA1039
The output is protected by two diodes, one to
ground and one to the supply.
At high output currents the dissipation in the
output transistor may necessitate a heatsink.
See the power derating curve (Figure 1).
Product Specification
Signetics Linear Products
TEA1039
Control Circuit for Switched-Mode Power Supply
- - - vFS
60
- - 5.9V
40
/V
20
1
'0
I
I I
I
I/~
./.V
C5=2.7nF
I
0±f-----~-''"
~
.~ ~ ~b:
b
~/
/b
82DpF
"'Pf
2
3
8 10
R4(kll)
40 50
20
NOTES,
a. The voltages on inputs FB or LIM are between 2.2V and 5.9V. The circuit is in its normal regulation mode.
b. The voltage on input FB or input LIM is lower than 2.2V. The circuit works at its maximum frequency.
c. The voltages on inputs FB and LIM are higher than 5.9V. The circuit works at its minimum frequency.
Figure 3. Timing Diagram for the Frequency Regulation Mode Showing the
Voltage on External Capacitor C5 Connected between CX and Ground and
the Output Voltage as a Function of Time for
Three Combinations of Input Signals
Figure 4. Minimum Output Pulse
Repetition Time tMIN (Curves a) and
Minimum Output LOW Time tOLmln
(Curves b) in the Frequency Regulation
Mode as a Function of External
Resistor R4 Connected Between
RX and Ground with External
Capacitor C5 Connected Between
CX and Ground as a Parameter
- - - - vFa
1.6
..
V
V
1.2
V
V
"-
~ 0.8
V
-~
V
0.4
I
0
NOTES,
a. The voltages on inputs FB or LIM are below 5.9V. The circuit is in its normal regulation range.
b. The voltages on inputs FB and LIM are higher than 5,9V. The circuit produces its minimum output LOW time, giving
the maximum duty factor of the SMPS.
Figure 5. Timing Diagram for the Duty Factor Regulation Mode Showing the
Voltage on External Capacitor C5 Connected Between CX and Ground and the
Output Voltage as a Function of Time for Two Combinations of Input Signals
0
2
4
6
8
CS (nF)
OP07730S
Figure 6. Minimum Output LOW Time
tOLmin in the Duty Factor Regulation
Mode as a Function of External
Capacitor C5 Connected Between CX
and Ground. In This Mode the
Minimum Output LOW Time is
Independent of R4 for Values
of R4 Between 4k!1 and 80k!1
•
November 14, 1986
14-17
Signetlcs Linear Products
Product Specification
Control Circuit for Switched-Mode Power Supply
TEA1039
NOTE:
An Optocoupler CNX62 Is Used for Voltage Separation.
Figure 7. Typical Application of the TEA1039 in a Variable-Frequency Flyback Converter Switched-Mode Power Supply
November 14, 1986
14-18
Signetics Linear Products
Product Specification
Control Circuit for Switched-Mode Power Supply
TEA1039
NOTE:
An Optocoupler CNX62 is Used for Voltage Separation.
Figure 8. Typical Application of the TEA21039 In a Fixed-Frequency Variable Duty Factor Forward Converter
Switched-Mode Power Supply
November 14, 1986
14-19
Signetics
Section 15
Packaging Information
Linear Products
INDEX
Substrate Design Guidelines for Surface Mounted Devices................................
Test and Repair ......................................................................................
Fluxing and Cleaning................................................................................
Thermal Considerations for Surface-Mounted Devices......................................
Package Outlines for Prefixes ADC, AM, CA, DAC, LF, LM, MC,
NE, SA, SE, SG, pA and ULN ...................................................................
Package Outlines for Prefixes HEF, OM, MEA, PCD, PCF, PNA,
SM, SAB, SAF, TBA, TCA, TDA, TDD and TEA ...........................................
15-3
15-14
15-17
15-22
15-35
15-52
II
Signetics
Substrate Design Guidelines for
Surface-Mounted Devices
Linear Products
INTRODUCTION
SMD technology embodies a totally new automated circuit assembly process using a
new generation of electronic components:
surface-mounted devices (SMDs). Smaller
than conventional components, SMDs are
placed onto the surface of the substrate, not
through it like leaded components. And from
this, the fundamental difference between
SMD assembly and conventional throughhole component assembly arises; SMD component positioning is relative, not absolute.
When a through-hole (leaded) component is
inserted into a PCB, either the leads go
through the holes, or they don't. An SMD,
however, is placed onto the substrate surface, its position only relative to the solderlands, and placement accuracy is therefore
influenced by variations in the substrate track
pattern, component size, and placement machine accuracy.
Other factors influence the layout of SMD
substrates. For example, will the board be a
mixed-print (a combination of through-hole
components and SMDs) or an all-SMD design? Will SMDs be on one side of the
substrate or both? And there are process
considerations, such as: what type of machine will place the components and how will
they be soldered?
Using our expertise in the world of SMD
technology, this section draws upon applied
research in the area of substrate design and
manufacture, and presents the basic guidelines to assist the designer in making the
transition from conventional through-hole
PCB assembly to SMD substrate manufacture.
Designing With SMD
SMD technology is penetrating rapidly into all
areas of modern electronic equipment manufacture - in professional, industrial, and consumer applications. Boards are made with
conventional print-and-etch PCBs, multilayer
boards with thick film ceramic substrates, and
with a host of new materials specially developed for SMD assembly.
However, before substrate layout can be
attempted, footprints for all components must
be defined. Such a footprint will include the
combination of patterns for the copper solderlands, the solder resist, and, possibly, the
solder paste. So the design of a substrate
breaks down into two distinct areas: the SMD
footprint definition, and the layout and track
routing for SMDs on the substrate.
February 1987
Each of these areas is treated individually;
first, the general aspects of SMD technology,
including substrate configurations, placement
machines, and soldering techniques, are discussed.
4
I
~, r:=:} ,c:::1,
I
Substrate Configurations
SMD substrate assembly configurations are
classified as:
Type I - Total surface mount (all-SMD);
substrates with no through-hole components
at all. SMDs of all types (SM integrated
circuits, discrete semiconductors, and passive devices) can be mounted either on one
side, or both sides, of the substrate. See
Figure 1a.
a. Type 1- Total Surface-Mount
(all-SMD) Substrates
Type IIA - Double-sided mixed-print; substrates with both through-hole components
and SMDs of all types on the top, and smaller
SMDs (transistors and passives) on the bottom. See Figure 1b.
Type liB - Underside attachment mixedprint; the top of the substrate is dedicated
exclusively to through-hole components, with
smaller SMDs (transistor and passives) on
the bottom. See Figure 1c.
Although the all-SMD substrate will ultimately
be the cheapest and smallest variation as
there are no through-hole components, it's
the mixed-print substrate that many manufacturers will be looking to in the immediate
future, for this technique enjoys most of the
advantages of SMD assembly and overcomes the problem of non-availability of
some components in surface-mounted form.
The underside attachment variation of the
mixed-print (type liB - which can be thought
of as a conventional through-hole assembly
with SMDs on the solder side) has the added
advantages of only requiring a single-sided,
print-and-etch PCB and of using the established wave soldering technique. The all-SMD
and mixed-print assembly with SMDs on both
sides require reflow or combination wave!
reflow soldering, and, in most cases, a double-sided or multilayer substrate.
The relatively small size of most SMD assemblies compared with equivalent through-hole
designs means that circuits can often be
repeated several times on a single substrate.
This multiple-circuit substrate technique
(shown in Figure 2) further increases production efficiency.
15-3
b. Type IIA - Mixed-Print
(Double-Sided) Substrate
DF07090S
c. Type liB - Mixed-Print (Underside
Attachment) Substrate
Figure 1
•r:P.=.Y.=!l?=.CU
0I. 1 -0
.-0 1 -0
~ .. i .. i
[?=.~.=i=[?_=i=O
ou
1·0
1·0
ill
i n1·0
i
[!::;=~=~=~..
"""oos
Figure 2. Multiple-Circuit Substrate
Mixed Prints
The possibility of using a partitioned design
should be investigated when considering the
mixed-print substrate option. For this, part of
the circuit would be an all-SMD substrate, and
the remainder a conventional through-hole
•
Signetics Linear Products
Substrate Design Guidelines for Surface-Mounted Devices
PCB or mixed-print substrate. This allows the
circuit to be broken down into, for example,
high and low power sections, or high and low
frequency sections.
Automated SMD Placement
Machines
The selection of automated SMO placement
machines for manufacturing requirements is
an issue reaching far beyond the scope of
this section. However, as a guide, the four
main placement techniques are outlined.
They are:
In-Line Placement - a system with a series
of dedicated pick-and-place units, each placing a single SMO in a preset position on the
substrate. Generally used for small circuits
with few components. See Figure 3a.
a. In-line Placement
b. Sequential Placement
Sequential Placement - a single pick-andplace unit sequentially places SMOs onto the
substrate. The substrate is positioned below
the pick-and-place unit using a computercontrolled X-Y moving table (a "software
programmable" machine). See Figure 3b.
Simultaneous Placement - places all
SMOs in a single operation. A placement
module (or station), with a number of pickand-place units, takes an array of SMOs from
the packaging medium and simultaneously
places them on the substrate. The pick and
place units are guided to their substrate
location by a program plate (a "hardware
programmable" machine), or by softwarecontrolled X-V movement of substrate and/or
pick-and-place units. See Figure 3c.
Sequential/Simultaneous Placement - a
complete array of SMOs is transferred in a
single operation, but the pick-and-place units
within each placement module can place all
devices simultaneously, or individually (sequentially). Posijioning of the SMOs is software-controlled by moving the substrate on
an X-Y moving table, by X-Y movement of the
pick-and-place units, or by a combination of
both. See Figure 3d.
All four techniques, although differing in detail, use the same two basic steps: picking the
SMO from the packaging medium (tape, magazine, or hopper) and placing it on the substrate. In all cases, the exact location of each
SMO must be programmed into the automated placement machine.
Soldering Techniques
The SMO-populated substrate is soldered by
conventional wave soldering, reflow soldering, or a combination of both wave and reflow
soldering. These techniques are covered at
length in another publication entitled SMD
Soldering Techniques, but, briefly, they can
be described as follows:
Wave Soldering - the conventional method
of soldering through-hole component assemFebruary 1987
c. Simultaneous Placement
d_ Sequential/Simultaneous Placement
Figure 3
blies where the substrate passes over a wave
(or more often, two waves) of molten solder.
This technique is favored for mixed-print assemblies with through-hole components on
the top of the substrate, and SMOs on the
bottom.
Reflow Soldering - a technique originally
developed for thick-film hybrid circuits using a
solder paste or cream (a suspension of fine
solder parlicles in a sticky resin-flux base)
applied to the substrate which, after component placement, is heated and causes the
solder to melt and coalesce. This method is
predominantly used for Type I (all-SMO) assemblies.
Combination Wave/Reflow Soldering - a
sequential process using both the foregoing
techniques to overcome the problems of
soldering a double-sided mixed-print substrate with SMOs and through-hole components on the top, and SMOs only on the
bottom. (Type liB).
Footprint Definition
An SMO footprint, as shown in Figure 4,
consists of:
• A pattern for the (copper) solderlands
• A pattern for the solder resist
15-4
• If applicable, a pattern for the solder
cream.
The design for the footprint can be represented as a set of nominal coordinates. and
dimensions. In practice, the actual coordinates of each pattern will be distributed
around these nominal values due to positioning and proceSSing tolerances. Therefore, the
coordinates are stochastic; the actual values
form a probability distribution, with a mean
value (the nominal value) and a standard
deviation.
The coordinates of the SMO are also stochastic. This is due to the tolerances of the
actual component dimensions and the positional errors of the automated placement
machine.
The relative positions of solderland, solder
resist pattern, and SMO, are not arbitrary. A
number of requirements may be formulated
concerning clearances and overlaps. These
include:
• Limiting factors in the production of the
patterns (for example, the spacing
between solderlands or tracks has a
minimum value)
Signetics Linear Products
Substrate Design Guidelines for Surface-Mounted Devices
• Maximizes the number of tracks
between adjacent solderlands.
The final SMD footprint design also depends
on the soldering process to be used. The
requirements for a wave-soldered substrate
differ from those for a reflow-soldered substrate, so each is discussed individually.
Footprints for Wave Soldering
Figure 4. Component Lead, Solder
Land, Solder Resist, and Solder
Cream 11 Footprint"
• Requirements concerning the soldering
process (for example, the solderlands
must be free of solder resist)
• Requirements concerning the quality of
the solder joint (for example, the
solderland must protrude from the SMD
metallization to allow an appropriate
solder meniscus)
Mathematical elaboration of these require·
ments and substitution of values for all toler·
ances and other parameters lead to a set of
inequalities that have to be solved simulta·
neously. To do this manually using worst·
case design is not considered realistic. A
better approach is to use a statistical analy·
sis; although this requires a complex comput·
er program, it can be done.
Such an approach may deliver more than one
solution, and, if this is so, then the optimal
solution must be determined. Optimization is
achieved by setting the following objectivefind the solution that:
• Minimizes the area occupied by the
footprint
c:=:::=C>
To determine the footprint of an SMD for a
wave-soldered substrate, consider four main
interactive factors:
• The component dimensions plus
tolerances - determined by the
component manufacturer
• The substrate metallization - positional
tolerance of the solderland with respect
to a reference point on the substrate
o The solder resist - positional tolerance
of the solder resist pattern with respect
to the same reference point
o The placement tolerance - the ability of
an automated placement machine to
accurately position the SMD on the
substrate.
The coordinates of patterns and SMDs have
to meet a number of requirements. Some of
these have a general validity (the minimum
overlap of SMD metallization and solderland)
and available space for solder meniscus.
Others are specifically required to allow successful wave soldering. One has to take into
account factors like the "shadow effect"
(missing of joints due to high component
bodies), the risk of solder bridging, and the
available space for a dot of adhesive.
The "Shadow Effect"
In wave soldering, the way in which the
substrate addresses the wave is important.
Unlike wave soldering of conventional printed
boards where there are no component bodies
to restrict the wave's freedom to traverse
across the whole surface, wave soldering of
SMD substrates is inhibited by the presence
of SMDs on the solder-side of the board. The
solder is forced around and over the SMDs as
shown in Figure 5a, and the surface tension
EXTENDED
of the molten solder prevents its reaching the
far end of the component, resulting in a dryjoint downstream of the solder flow. This is
known as the "shadow effect."
The shadow effect becomes critical with high
component bodies. However, wetting of the
solderlands during wave soldering can be
improved by enlarging each land as shown in
Figure 5b. The extended substrate metallization makes contact with the solder and allows
it to flow back and around the component
metallization to form the joint.
The use of the dual-wave soldering technique
also partially alleviates this problem because
the first, turbulent wave has sufficient upward
pressure to force solder onto the component
metallization, and the second, smooth wave
"washes" the substrate to form good fillets of
solder. Similarly, oil on the surface of the
solder wave lowers the surface tension,
(which lessens the shadow effect), but this
technique introduces problems of contaminants in the solder when the oil decomposes.
Footprint Orientation
The orientation of SO (small outline) and VSO
(very small outline) ICs is critical on wavesoldered substrates for the prevention of
solder bridge formation. Optimum solder penetration is achieved when the central axis of
the IC is parallel to the flow of solder as
shown in Figure 6a. The SO package may
also be transversely oriented, as shown in
Figure 6b, but this is totally unacceptable for
the VSO package.
Solder Thieves
Even with parallel mounted SO and VSO
packages, solder bridges have a tendency to
form on the leads downstream of the solder
flow. The use of solder thieves (small squares
of substrate metallization), shown in Figure 7
for a 40-pin VSO, further reduces the likelihood of solder-bridge formation.
....
~
SUBSTRATE
~~~~W
~.;... ~
SUBSTRATE
;:Z~7Z~
DIRECT:
~
a. Surface Tension Can Prevent the Molten Solder
From Reaching the Downstream End of the SMD,
Known as the "Shadow Effect"
b. Extending the Solder Lands to Overcome the
Shadow Effect
Figure 5
February 1987
SOLDER FLOW
15-5
Signetics Linear Products
Substrate Design Guidelines for Surface-Mounted. Devices
For bonding small outline (SO) ICs to the
substrate, two dots of adhesive are sufficient
for SO·8, ·14, and ·16 packages, but the SOL·
20, ·24, ·28, and VSO·40 packages need
three dots. The through·tracks (or dummy
tracks) must be positioned beneath the IC
accordingly to support the adhesive dots.
~~;=~~~;=~~4Cm=~
Iii;
FLOW
OIRECTION
FLOW
DIRECTION
Sr
jM:TALLIZATION
. ~ #".
~ESweo~>!?f+Y\ LAND
11
\
C
b. Transverse Orientation for
SO Packages Only
a. Parallel Orientation for SO
and VSO Packages
Figure 6
adjacent pins and solderlands, thus increas·
ing the chance of solder bridges forming.
-=---+
SussTR;e
Dummy Tracks for Adhesive
Application
~
DIRECTION '-----'
{r:
210
~ SOLD~~~ANDS
SOLDER THIEF
--J't-
DF0718QS
Figure 7. Example of Solder Thieves
for VSO-40 Footprints (Dims In mm)
sOle
Figure 8. Misaligned Placement of SO
Package Increases the Possibility of
Solder Bridging
Placement Inaccuracy
Another major cause of solder bridges on SO
ICs and plastic leaded chip carriers (PLCCs)
is a slight misalignment as shown in Figure 8.
The close spacing of the leads on these
devices means that any inaccuracy in place·
ment drastically reduces the space between
February 1987
For wave soldering, an adhesive to affix
components to the substrate is required. This
is necessary to hold the SMDs in place
between the placement operation and the
soldering process (this technique is covered
at length in another publication entitled Adhe·
sive Application and Curing).
The amount of adhesive applied is critical for
two reasons: first, the adhesive dot must be
high enough to reach the SMD, and, second,
there mustn't be too much adhesive which
could foul the solderland and prevent the
formation of a solder jOint. The three parame·
ters governing the height of the adhesive dot
are shown in Figure 9. Although this diagram
illustrates that the minimum requirement is
C > A + B, in practice, C > 2(A + B) is more
realistic for the formation of a good strong
bond.
Taking these parameters in turn, the sub·
strate metallization height (A) can range from
about 35!lm for a normal print·and·etch PCB
to 135!lm for a plated through·hole board.
And the component metallization height (B)
(on 1206·size passive devices, for example)
may differ by several tens of microns. There·
fore, A + B can vary considerably, but it is
desirable to keep the dot height (C) constant
for anyone substrate.
The solution to this apparent problem is to
route a track under the device as shown in
Figure 10. This will eliminate the substrate
metallization height (A) from the adhesive
dot·height criteria. Quite often, the high com·
ponent density of SMD substrates necessitates the routing of tracks between solder·
lands, and, where it does not, a short dummy
track should be introduced.
15-6
>A+
B
SUBSTRATE
NOTES:
A "" Substrate metallization height
8 ... SMD metallization height
C = Height of adhesive dot
Figure 9. Adhesive Dot Height Criteria
Footprints for Reflow Soldering
To determine the footprint of an SMD for a
reflow·soldered substrate, there are now five
interactive factors to consider: the four that
affect the wave solder footprints (although
the solder resist may be omitted), plus an
additional factor relating to the solder cream
application (the positional tolerance of the
screen'printed solder cream with respect to
the solderlands).
Solder Cream Application
In reflow soldering, the solder cream (or
paste) is applied by pressure syringe dispens·
ing or by screen printing. For industrial purposes, screen printing is the favored te<;:h·
nique because it is much faster than dispens·
ing.
Screen Printing
A stainless steel mesh coated with emulsion
(except for the solderland pattern where
cream is required) is placed over the sub·
strate. A squeegee passes across the screen
and forces solder cream through the uncoated areas of the mesh and onto the solderland. As a result, dots of solder cream of a
given height and density (in mg/mm2) are
produced.
There is an optimum amount of solder cream
for each joint. For example, the solder cream
requirements for the C1206 SM capacitor are
around 1.5mg per end; the SO IC requires
between 0.5 and 0.75mg per lead.
The solder cream density, combined with the
required amount of solder, makes a demand
upon the area of the solderland (in mm 2). The
footprint dimensions for the solder cream
pattern are typically identical to those for the
solderlands.
Signetics Linear Products
Substrate Design Guidelines for Surface-Mounted Devices
DUMMY·TRACK [
OR
I I
TROUGH-~~
1
C>B
Figure 10. Through-Track or Dummy
Track to Modify Dot Height Criteria
/------
DO
Floating
One phenomenon sometimes observed on
reflow·soldered substrates is that known as
"floating" (or "swimming"). This occurs
when the solder paste reflows, and the force
exerted by the surface tension of the now
molten solder "pulls" the SMD to the center
of the solderland.
When the solder reflows at both ends simultaneously, the swimming phenomenon results
in the SMD self·centering on the footprint as
the forces of surface tension fight for equilibri·
um. Although this effect can remove minor
positional errors, it's not a dependable fea·
ture and cannot be relied upon. Components
must always be positioned as accurately as
possible.
Footprint Dimensions
The following diagrams (Fig. 11 to 19) show
footprint dimensions for SO ICs, the VSO-40
package, PLCC packages, and the range of
surface-mounted transistors, diodes, resistors, and capacitors. All dimensions given are
based on the criteria discussed in these
guidelines.
--lorDD-1l
I I
A
B
DM~
-i-..{.INCHES
INCHES
PACKAGE
OUTLINE
50·8, 14, 16
SOL-1B, 20, 24, 28
B
A
C
PACKAGE
OUTLINE
D
.155 .275 .060 .024 .050
.310 .450 .070 .024 .050
VSO-40
VSO-56
so
so
SMALL
LARGE
A
B
C
D
4.0
7.B
7.0
1.5
1.B
.6
.6
11.4
PACKAGE
OUTLINE
1.27
1.27
SOL-B
B
C
D
13.2
2.1
.6
C
D
A
9.0
C
D
E
.536
.108
.676
.108
.02
.02
.030
.030
VSO-40
VSO·56
A
B
C
D
E
B.O
11.5
13.4
16.9
2.7
2.7
.5
.5
.762
.75
Figure 12. Footprints for V50 ICs
METRIC (mm)
PACKAGE
OUTLINE
B
.32
.46
METRIC (mm)
METRIC (mm)
PACKAGE
OUTLINE
A
1.27
INCHES
PACKAGE
OUTLINE
A
B
SOL·B
.36
.52B
.OB4 .024 .050
Figure 11. Footprints for 50 ICs
Please note - these footprints are based on
our experience with both experimental and
actual production substrates and are reproduced for guidance only. Research is constantly going on to cover all SMDs currently
available and those planned for in the future,
and data will be published when in it becomes
available.
PACKAGE
OUTLINE
PLCC-20
PLCC-2B
PLCC-44
PLCC·52
PLCC-6B
PLCC·B4
PLCC-32
A
C
INCHES
D
E
G
.260 .440.090 .024 .050 .260 .440
.360 .540.090 .024 .050 .360 .540
.560 .740.090 .024 ,050 .560 .740
,660 .B40 .090 ,024 .050 .660 .840
.8601.040.090 .024 .050 .860 1.040
1.0601.240.090 ,024 .050 1.0BO 1.240
.360 .540,090 .024 .050 .460 .640
Figure 13. Footprints for PLCCs
•
February 1967
15-7
Signetics Linear Products
i
i
Substrate Design Guidelines for Surface-Mounted Devices
r=ll
~ D+r 0-+-01
o==tl
o~ 0]
~:~
r- --1
~C·+-:-·l·-C~
A
~B
G$-
E
F
DF07280S
-t
~C~
B
I
A
SOT-23
I
A
B
Reflow
1 1.2
0.8
2.6
3.4
SOT·23
Reflow
Wave
I
Wave
F
SOD-80
0.048 0.104 0.028 0.044 0.104
0.032 0.136 0.052 0.052 0.048 0.152
-
Reflow
Wave
METRIC (mm)
C
D
0.7
1.3
E
1.1
1.3
E
F
SOD-BO
2.6
1.2
3.8
Reflow
Wave
Figure 14. Footprints for SOT-23
Transistors
~~~~~~EI
SOT-143
I
A
INCHES
D
E
F
2.6
METRIC (mm)
C
D
E
F
0.7
1.2 0.9
1.1
G
H
G
0,92.0
H
METRIC (mm)
B
C
1
2.4
2.5
5.2
5.0
~~~~~~EI
SOT·89
A
1.4
2.0
SOT·89
B
"""""
INCHES
C
D
E
F
INCHES
B
A
SIZE
C1812
C2220
0.08 X 0.05
0.128 X 0.064
0.128 X 0.1
0.18 x 0.08
0.18 x 0.128
0.228 x 0.2
CODE
SIZE
C0805
R/C1206
C1210
C1808
C1612
C2220
2.0 x 1.25
3.2 x 1.6
3.2 X 2.5
4.5 X 2.0
4.5 X 3.2
5.7 X 5.0
C
0.032 0.136 0.052
0.072 0.184 0.056
0.072 0.184 0.056
0.112 0.248 0.068
0.112 0.248 0.068
0.16
0.296 0.068
METRIC (mm)
A
B
0.8
1.8
I.B
2.8
2.8
4.0
3.4
4.6
4.6
6.2
6.2
7.4
A
B
I 2.0
4.6
METRIC (mm)
C
D
E
2.6
1.2
0.8
F
G
0.7
3.B
Figure 16. Footprints for ReflowSoldered SOT-89 Transistors
lEi
O~
OJ
:~_e-:J
·1·
OF"'OOS
D
0.056
0.068
0.104
0.084
0.132
0.204
C
D
1.3
1.4
1.4
1.7
1.7
1.7
1.4
1.7
2.6
2.1
3.3
5.1
Figure 18. Footprints for ReflowSoldered Surface-Mounted Resistors
and Ceramic Multilayer Capacitors
15-8
G
I 0.08 0.1840.104 O.04B 0.032 0.02B 0.152
~~~~~~EI
D
1.4
1.25
1.1
Figure 17. Footprints for ReflowSoldered SOT-143 TrBnslstors
February 1987
A
COBOS
R/C1206
0.104 0.0280.0460.0360.044 0.036 0.116 0.044
A
0.056
0.08
1
CODE
ClaDa
C
0.056
0.05
DF07270S
C1210
B
B
0.208
0.2
D
D DI be
G
DF07200S
I
0.096
0.10
C
-L
i
~H--1
PACKAGE I
OUTLINE
I
B
~c "I- :-+-c~
0_,0+1
-t-I 1
0-011
E
I
INCHES
A
Figure 15. Footprints for SOO-80
Diodes
~B.+-:-+.B~
SOT·143
~:~
OF07250S
INCHES
C
D
INCHES
SIZE
B C
A
D
E
I
C0805
10.08 X 1.050.0480.1440.0460.0480.016
R/C1206 0.12B X .064O.0B 0.192 0.056 0.056 0.020
CODE
COBOS
R/C1206
I
1
SIZE
2.0 X 1.25
3.2 x.6
METRIC (mm)
A
B C
D
E
1.2
2.0
1.2
1.4
0.4
0.5
3.6
4.8
1.2
1.4
Figure 19. Footprints for WaveSoldered Surface-Mounted Resistors
and Ceramic Multilayer Capacitors
Signetics Linear Products
Substrate Design Guidelines for Surface-Mounted Devices
Layout Considerations
Component orientation plays an important
role in obtaining consistent solder-joint quality. The substrate layout shown in Figure 20
will result in significantly betler solder joints
than a substrate with SMD resistors and
capacitors positioned parallel to the solder
flow.
bd. ~ bdbd
Component Pitch
The minimum component pitch is governed
by the maximum width of the component and
the minimum distance between adjacent
components. When defining the maximum
component width, the rotational accuracy of
the placement machine must also be considered. Figure 21 shows how the effective width
of the SMD is increased when the component
is rotated with respect to the footprint by
angle q,0. (For clarity, the rotation is exaggerated in the illustration.)
SOLDER
FLOW
U
The minimum permissible distance between
adjacent SMDs is a figure based upon the
gap required to avoid solder-bridging during
the wave soldering process. Figure 22 shows
how this distance and the maximum component width are combined to derive the basic
expression for calculating the minimum pitch
(FMIN)·
As a guide, the recommended minimum
pitches for various combinations of two sizes
of SMDs, the R/C1206 and COB05 (R or C
designating resistor or capacitor respectively;
the number referring to the component size),
are given in Table 1. These figures are
statistically derived under certain assumed
boundary conditions as follows:
• Positioning error (f>.p)± 0.3mm; (± 0.012")
• Pattern accuracy (f>.q)± 0.3mm;
(± 0.012")
Ld
bd
bd bd
~
SUBSTRATE
DIRECTION ~
Figure 20. Recommended Component Orientation for Wave-Soldered Substrates
• Rotational accuracy (q,)± 3°
• Component metallization/solderland
overlap (MMIN) 0.1 mm (0.004") (Note
this figure is only valid for wave
soldering)
• The figure for the minimum permissible
gap between adjacent components
(GMIN) is taken to be 0.5mm (0.020").
As these calculations are not based on worstcase conditions, but on a statistical analysis
of all boundary conditions, there is a certain
flexibility in the given data.
For example, it is possible to position RI
C1206 SMDs on a 2.5mm pitch, but the
probability of component placements occurring with GMIN smaller than 0.5mm will increase; hence, the likelihood of solder-bridging also increases. Each application must be
assessed on individual merit with regard to
acceptable levels of rework, and so on.
February 19B7
NOTES:
tP = Component rotation with respect to footprint
L sin ¢ = Effective increase in width
W sin ¢ = Effective increase in length
Figure 21. The Influence of Rotation of the SMD With Respect to the Footprint
Solderland/Via Hole
Relationship
With reflow-soldered multilayer and doublesided, plated through-hole substrates, there
must be sufficient separation between the via
holes and the solderlands to prevent a solder
15-9
well from forming. If too close to a solder
joint, the via hole may suck the molten solder
away from the component by capillary action;
this results in insufficient wetting of the joint.
•
Signetics Linear Products
Substrate Design Guidelines for Surface-Mounted Devices
of a leaded component. Minimum distances
between the clinched lead ends and the
SMOs or substrate conductors are 1mm
(0.04") and 0.5 (0.02") respectively.
feU
--------+--1-8';.,';.,'''''_
L:
p,± ,-p-+--+'--+-++
1
Wmax
t
Gmio
NOTES:
WMAX "" Maximum width of component
GM1N '" Minimum permissible gap
FMIN = Minimum pitch
P1 = Nominal position of component 1 (tolerance .1.p)
P2 = Nominal position of component 2 (tolerance Ap)
FMIN = WMAX + 2Ap + G M1N
Table 1. Recommended Pitch For R/C1206 and C080S SMDs
Component
Component B
'A
~---~r----~
R/C1206
COSOS
li;1
Solderland/Component Lead
Relationship
Of special consideration for mixed·print sub·
strate layout is the location of leaded compo·
nents with respect to the SMO footprints and
February 1987
Uniform placement uses a modular grid sys·
tem with devices placed on a uniform center·
to·center spacing. (For example, 2.5 (0.1") or
5mm (0.2") as shown in Figure 24b.) This
placement has the distinct advantage of es·
tablishing a standard and enables the use of
other automated placement machines for fu·
ture production requirements without having
to redesign boards.
Substrate Population
Figure 22. Criteria for Determining the Minimum Pitch of SMOs
Combination
Placement Machine Restrictions
There are two ways of looking at the distribu·
tion of SMOs on the substrate: uniform SMO
placement and non·uniform SMO placement.
With nonuniform placement, center·to·center
dimensions of SMOs are not exact multiples
of a predetermined dimension as shown in
Figure 24a, so the location of each is difficult
to program into the machine.
R/C120S
COBOS
3.0(0.12")
2.B(0.112")
2.B (0.112")
2.S(0.0104")
R/C120S
COBOS
5.B (0.232")
5.3(0.212")
5.3 (0.212")
4.B(0.192")
R/C120S
COBOS
4.1 (0.IS4")
3.S(0.144")
3.7 (0.14B")
3.0(0.12")
the minimum distance between a protruding
clinched lead and a conductor or SMO. Figure
23 shows typical configurations for R/C120S
SMOs mounted on the underside of a sub·
strate with respect to the clinched leads
15-10
Population density of SMOs over the total
area of the substrate must also be carefully
considered, as placement machine limitations
can create a "lane" or "zone" that restricts
the total number of components which can be
placed within that area on the substrate.
For example, on a hardware·programmable
simultaneous placement machine (see Figure
3c), each pick·and·place unit within the place·
ment module can only place a component on
the substrate in a restricted lane (owing to
Figure 23. Location of R/C1206
SMDs on the Underside of a Mixed·
Print Substrate with Respect to the
Clinched Leads of Through-Hole
Components (Dimensions In mm)
Signetics Linear Products
Substrate Design Guidelines for Surface-Mounted Devices
Test Points
Siting of test points for in·circuit testing of
SMD substrates presents problems owing to
the fewer via holes, higher component densities, and components on both sides of SMD
substrates. On conventional double-sided
PCBs, the via holes and plated-through component lead-holes mean that most test-points
are accessible from one side of the board.
However, on SMD substrates, extra provision
for test-points may have to be made on both
sides of the substrate.
2.5mm
H
f:=l
~d
rr. hl
rh
+1
C:l
[:=J
II- fll
II
C:J
DF07380S
a. Non-Uniform Component Placement
2.Smm
H
FPi
IB
b!d In- n In- n bld
ILL j.....lJ ILL j.....lJ
FFl
bbl
Irr n
ILL !-lJ
In- n
ILL !-J..I
Df07390S
b. Uniform Component Placement
Figure 24
adjacent pick-and-place units), typically 10 to
12mm (004" to 0048") wide, as shown in
Figure 25.
SUBSTRATE
DIRECTION
S
c==::::>
$
$
10.0mm
......
••
til
TYPICAL
•
~
I
1$1-
S
DF07400S
Figure 25. Substrate "Lanes"
From Use of a Simultaneous
Placement Machine
Placement of the 10 components in the lane
on the right of the substrate shown will
require a machine with 10 placement modules (or ten passes beneath a single placement module), an inefficient process considering that there are no more than three SMDs
in any other lane.
February 1987
Figure 26a shows the recommended approach for positioning test-points in tracks
close to components, and Figure 26b shows
an acceptable (though not recommended)
alternative where the solderland is extended
to accommodate the test pin. This latter
method avoids sacrificing too much board
space, thus maintaining a high-density layout,
but can introduce the problem of components
moving ("floating") when reflow-soldered.
The approach shown in Figure 26c is totally
unacceptable since the pressure applied by
the test pin can make an open-circuit
soldered joint appear to be good, and, more
importantly, the test pin can damage the
metallization on the component, particularly
with small SMDs.
a. RECOMMENDED Test Point
Location Close to an SMD
b. Acceptable Test Point Location
CAD Systems for SMD
Substrate Layout
At present, about half of all PCBs are laid out
using computer-aided design (CAD) techniques, and this proportion is expected to rise
to over 90% by 1988. Of the many current
CAD systems available for designing PCB
layouts for conventional through-hole components and ICs in DIL packages, few are SMDcompatible, and systems dedicated exclusively to SMD substrate layout are still comparatively rare. There are two main reasons
for this: some CAD suppliers are waiting for
SMD technology to fully mature before updating their systems to cater to SMD-Ioaded
substrates, and others are holding back until
standard package outlines are fully defined.
However, updating CAD systems used for
through-hole printed boards is not simply a
case of substituting SMD footprints for can·
ventional component footprints, since SMD·
populated substrates impose far tougher restraints on PCB layout and require a total
rethink of the layout programs. For example,
systems must deal with higher component
densities, finer track widths, devices on both
sides of the substrate (possibly occupying
corresponding positions on opposite sides),
and even SMDs under conventional DILs on
the same side of the substrate.
The amount of reworking that a program
requires depends on whether it's an interactive (manual) system, or one with fully automatic routing and placement capabilities. For
15-11
c. UNACCEPTABLE Test Point
Location
Figure 26
interactive systems, where the user positions
the components and routes the tracks manually on-screen, program modifications will be
minimal. Automatic systems, however, must
contend with the stricter design rules for SMD
substrate layout. For example, many autorouting programs assume that every solderland is a plated through-hole and, therefore,
can be used as a via hole. This is not
applicable for SMD-populated substrates.
CAD programs base the substrate layout on a
regular grid. This method, analogous to drawing the layout on graph paper, must have the
grid lines on a pitch that is no larger than the
smallest component or feature (track width,
pitch, and so on). For conventional DIL
boards, this is typically 0.635mm (0.025"), but
with the much smaller SMDs, a grid spacing
of 0.0254mm (0.001") is required. Consequently, for the same area of substrate, a
CAD system based on this finer grid requires
•
Signetics Linear Products
Substrate Design Guidelines for Surface-Mounted Devices
a resolution more than 600 times greater than
that required for conventional-layout CAD
systems.
To handle this, extra memory capacity can be
added, or the allowable substrate area can be
limited. In fact, the small size of SMDs, and
the high-density layouts possible, generally
result in a smaller substrate. However, highdensity layout gives rise to additional complications not directly related to the SMD substrate design guidelines. Most CAD systems,
for instance, cannot always completely route
all interconnects, and some traces have to be
routed manually. This can be particularly
difficult with the fewer via holes and smaller
component spacing of SMD boards.
Ideally, the CAD program should have a
"tear-up and start again" algorithm that allows it to restart autorouting if a previous
February 1987
attempt reaches a position where no further
traces can be routed before an acceptable
percentage of interconnects (and this percentage must first be determined) have been
made. This minimizes the manual reworking
required.
CAE/CAD/CAM Interaction
Computer-aided production of printed boards
has evolved from what was initially only a
computer-aided manufacturing process
(CAM - digitizing a manually-generated layout and using a photoplotter to produce the
artwork) to fully-interactive computer-aided
engineering, design, and manufacture using a
common database. Figure 27 illustrates how
this multi-dimensional interaction is particularly well-suited to SMD-populated substrate
manufacture in its highly-automated environment of pick-and-place assembly machines
and test equipment.
15-12
Using a fully-integrated system, linked by
local area network to a central database, will
make it possible to use the initial computeraided engineering (CAE - schematic design,
logic verification, and fault simulation) in the
generation of the final test patterns at the end
of the development process. These test patterns can then be used with the automatic
test equipment (ATE) for functional testing of
the finished substrates.
Such a system is particularly useful for testing
SMD-populated substrates, as their high component density and fewer via-holes make incircuit testing ("bed of nails" approach) difficult. Consequently, manufacturers are turning
to functional testing as an alternative. These
aspects are covered in another publication
entitled Functional Testing and Repair.
Signetics Unear Products
Substrate Design Guidelines for Surface-Mounted Devices
CAD
SOFTWARE
J
CAD
't:'I
,t1
,Q
.
CAE"':"-::::' "
SOFTWARE
i" """ DEVELOPMENT
CAM
""'"~
COMPONENT
PLACEMENT
~
R-------4;,1
MANUFACTURE
CAE
SonwARE~~'~~--~~'~~--=L-J~~==~~~~~'r===~~~\J=~~~~~~t-~~~~
LOCAL AREA NETWORK
HARDWARE
Figure 27. The Software-Hardware Interaction for the Computer-Aided Engineering, Design,
and Manufacture of SMD Substrates
II
February 1987
15-13
Signetics
Test and Repair
Linear Products
AN INTRODUCTION
The key questions that must be asked of any
electronic circuit are "does it work, and will it
continue to do so over a specified period of
time?" Until zero-defect soldering is
achieved, and all components are guaranteed
serviceable by the vendors, manufacturers
can only answer these questions by carrying
out some form of test on the finished product.
The types of tests, and the depth to which
they are carried out, are determined by the
complexity of the circuit and the customer's
requirements. The amount of rework to be
performed on the circuit will depend on the
results of these tests and the degree of
reliability demanded. The criteria are true of
all electronic assemblies, and the test engineer must formulate test schedules accordingly.
Substrates loaded with surface mounted devices (SMDs), however, pose additional problems to the test engineer. The devices are
much smaller, and substrate population density is greater, leading to difficulty in accessing all circuit nodes and test points. Also SMD
substrate layout designs often have fewer via
and component lead holes, so test points
may not all be on one side of the substrate
and double-sided test fixtures become necessary.
To achieve the high throughput rates made
possible by using highly automated SMD
placement machines and volume soldering
techniques, automatic testing becomes a necessity. Visual inspection of the finished substrate by trained inspectors can normally
detect about 90% of defects. With the correct
combination of automatic test equipment, the
remainder can be eliminated. In this publication, we hope to provide the manufacturer
with information to enable him to evaluate
and select the best combination of test equipment and the most effective test methods for
his product.
BARE·BOARD TESTING
Although SMD substrates will undoubtedly be
smaller than conventional through-hole substrates and have less space between conductors, the principles of bare-board testing
remain the same. Many of the testers already
in use can, with little or no modification, be
used for SMD substrates. As this is already a
well-established and well-documented practice, it will not be discussed further in this
publication, but it is recommended that bareFebruary 1987
board testing always be used as the first step
in assuring board integrity.
POST·ASSEMBLY TESTING
Testing densely populated substrates is no
easy task, as the components may occupy
both sides of the board and cover many of
the circuit nodes (see Figure 1 for the three
main types of SMD-populated substrates).
Unlike conventional substrates, on which all
test points are usually accessible from the
bottom, SMD assemblies must be designed
from the start with the siting of test points in
mind. Probing SMD substrates is particularly
difficult owing to the very close spacing of
components and conductors.
Mixed print or all-SMD assemblies with components on both sides further aggravate the
testing problems, as not all test points are
present on the same side of the board.
Although two-sided test fixtures are feasible,
they are expensive and require considerable
time to build.
The application of a test probe to the top of
an SMD termination could damage it, and
probe pressure on a poor or open solder joint
can force contact and thus allow a defective
joint to be assessed as good. Figure 2a
illustrates the recommended siting of test
points close to SMD terminations, and Figure
2b shows an alternative, though not recommended, option. Here, problems could arise
from reflow soldering (solder migrating from
the joint) unless the test point area is separated from the solder land area with a stripe of
solder resist. Excessive mechanical pressure
caused by too many probes concentrated in a
small area may also result in substrate damage.
It is good practice for substrates to have test
points on a regular grid so that conventional,
rather than custom, testers may be used. If
the substrate has tall components or heatsinks, the test points must be located far
enough away to allow the probes to make
good contact. All test points should be solder
coated to provide good electrical contact. Via
holes may also be used as test points, but the
holes must be filled with solder to prevent the
probe from sticking.
AUTOMATIC TEST EQUIPMENT
(ATE)
As manufacturers strive to increase production, the question becomes not whether to
15-14
d
I
k~,~
I
a. Type I - Total Surface Mount
(AII-SMD) Substrates
b. Type IIA - Mixed Print
(Double-Sided) Substrate
c. Type liB - Mixed Print
(Underside Attachment) Substrate
Figure 1
use automatic test engineering (ATE), but
which ATE system to use and how much to
spend on it. Because of the rapid fall in price
of computers, memories, and peripherals,
today's low-cost ATE equals the performance
of the high-cost equipment of just two or
three years ago. For factory automation, manufacturers must consider many factors, such
as production volume, product complexity,
and availability of skilled personnel.
One question is whether the ATE system can
be used not only for production testing but
also for service and repair to reduce the high
cost of keeping a substrate inventory in the
field. Another is whether assembly and process-induced faults represent a significant
percentage of production defects, rather than
out-of-tolerance components. These questions need to be answered before deciding on
the type of ATE system required.
Signetics Linear Products
Test and Repair
of an in-circuit tester alone, improves the
throughput rate.
IN·CIRCUIT
IN·CIRCUIT TESTER
100
:
50
TESTER
%
~~g~~ ANA~LV2~~RO$Bi~~:R=~i,::
TESTER
60
098
FUNCTIONAL
TIME
~ 65%
'".
9 MONTHS
PROG~A=NG
40
nME 4 DAVS
35%
a_ Recommended Location
of Test Points Close to SMOs
30
PROGRAMMING
TIME 6 HOURS
20
10
Figure 3_ Bar Chart Showing a
Comparison of Percent Fault Detection
and Programming Time for
Various ATE Systems
design can, however, often eliminate the
need for double-sided test probe fixtures.
b_ Acceptable, Though
Not Recommended, Location of
Test Points Close to SMOs
In-circuit testers power the assembly and
check for open or short-circuits, circuit parameters, and can pinpoint defective components. They can provide around 90%. fauH
coverage, but are more expensive than shortcircuit testers and programming can take
more than six weeks.
In-circuit analyzers are relatively simple to
program and can detect manufacturing-induced faults in one third of the time required
by an in-circuit tester. Fault coverage is
between 50% and 90%. Because they do not
power the assembly, they cannot detect digital logic faults, unlike an in-circuit tester or
functional tester.
DFOl-430S
c_ Unacceptable Location
of Test Points Close to SMOs
Figure 2
Several systems are currently available to the
manufacturer, including short-circuit testers,
in-circuit testers, in-circuit analyzers, and
functional testers. Figure 3 shows a bar-chart
giving a comparison of percent fault detection
and programming time for various ATE systems.
A loaded-board, short-circuit tester takes
from two to six hours to program and its
effective fault coverage is between 35% and
65%. It has the advantage of being operationally fast and comparatively inexpensive. On
the negative side, however, it is limited to the
detection of short-circuits and may require a
double-sided, bed-of-nails test fixture (see
Figure 4), which for SMD substrates may be
expensive and take time to produce. Careful
February 1987
Functional testers, on the other hand, check
the assembly's performance and simply
make a go or no-go decision. Either the
assembly performs its required function or it
does not. They are much more expensive, but
their fault coverage is between 80% and
98%. Their major disadvantages, apart from
cost, are that they cannot locate defective
components, and programming for a highcapacity system can take as long as nine
months_
Combining a short-circuit tester with a functional tester produces even more dramatic
results. If most defects are manufacturingproduced shorts, the use of a short-circuit
tester to relieve the functional tester of this
task can increase throughput five-fold while
maintaining a fault coverage of up to 98%.
If manufacturing faults and analog component defects are responsible for the majority
of failures, a relatively low-cost, in-circuit
analyzer can be used in tandem with an incircuit tester or functional tester to reduce
testing costs and improve throughput. The incircuit analyzer is three times faster than an
in-circuit tester in detecting manufacturinginduced faults, offers test and diagnostics
usually within 10 seconds each, and is relatively simple to program. But because it is
unpowered, an in-circuit analyzer cannot test
digital logic faults; either an in-circuit tester or
functional tester following the in-circuit analyzer must be used to locate this type of
defect.
POLLUTED POWER SUPPLIES
Today's electronic components and the
equipment used to test them are susceptible
to electrical noise. Erroneous measurements
on pass-or-fail tests could lower test throughput or, even more seriously, allow defective
products to pass inspection. Semiconductor
chips under test can also be damaged or
destroyed as high-energy pulses or line-voltage surges stress the fine-line geometrics
separating individual cells.
Noise pulses can be either in the normal (lineto-line) mode or common (line-to-ground)
mode. Common-mode electrical noise poses
a special threat to modern electronic circuitry
since the safety ground line to which common-mode noise is referenced is often used
as the system's logic reference point. Since
parasitic capacitance exists between safety
ground and the reference point, at high frequencies these pOints are essentially tied
together, allowing noise to directly enter the
system's logic.
ATE Systems
An analysis of defects on a finished substrate
will determine which combination of ATE will
best meet the test requirements with regard
to fault coverage and throughput rate.
If most defects are short-circuits, a loadedboard short-circuit tester, in tandem with an
in-circuit tester, will pre-screen the substrate
for short-circuits twice as fast as the in-circuit
tester. This allows more time for the in-circuit
tester to handle the more complex test requirements_ This combination of ATE, instead
15-15
MANUAL REPAIR
The repair of SMD-populated substrates will
entail either the resoldering of individual joints
and the removal of shorts or the replacement
of defective components.
The reworking of defective joints will invariably involve the use of a manual soldering
iron. Bits are commercially available in a
variety of shapes, including special hollow
bits used for desoldering and for the removal
of solder bridges. The criteria for the inspec-
•
Signetics Linear Products
Test and Repair
Figure 4. Double-Sided, Bed-of-Nails Test Fixture
Using air pressure, the center pin of the collet
then pushes the PLCC into contact with the
substrate where it is maintained with the
correct amount of force. Heat is then applied
through the walls of the collet to rellow the
solder paste. The center pin maintains pressure on the PLCC until the solder has solidified, then the center pin is raised and the
replacement is complete.
VACUUM
PIPETTE
I
HEAD
Mor
SUBSTRATE
Figure 5. Heated Collet for the Removal and Replacement of Multi-Leaded SMDs
(a PLCC is Shown Here)
tion of reworked soldered joints are the same
as those for machine soldering.
Special care must be taken when reworking
or replacing electrostatic sensitive devices.
Soldering irons should be well grounded via a
safety resistor of minimum 100k.l1. The
ground connection to the soldering iron
should be welded rather than clamped. This
is because oxidation occurs beneath the
clamp, thus isolating the ground connection.
Voltage spikes caused by the switching of the
iron can be avoided by using either continuously-powered irons, or irons that switch only
at zero voltage on the AC sine curve.
To remove defective leadless SMDs, a variety
of soldering iron bits are available that will
apply the correct amount of heat to both ends
of the component simultaneously and allow it
to be removed from the substrate. If the
substrate has been wave soldered, an adhesive will have been used, and the bond can
February 1987
be broken by twisting the bit. Any adhesive
residue must then be removed. The same
tool is then used to place and solder the new
component, using either solder cream or
resin-cored solder.
When a multi-leaded component, such as a
plastic leaded chip carrier (PLCC), has to be
removed, a heated collet can be used (see
Figure 5). The collet is positioned over the
PLCC, heat is applied to the leads and solder
lands automatically until the solder rellows.
The collet, complete with the PLCC, is then
raised by vacuum. Solder cream is then reapplied to the solder lands by hand. No
adhesive is required in this operation.
The collet is positioned over the replacement
PLCC, which is held in place by the slight
spring pressure of the PLCC leads against the
walls of the collet. The collet, complete with
PLCC, is then raised pneumatically and positioned over the solder lands.
15-16
Another method, well-suited to densely populated SMD substrates, uses a stream of
heated air, directed onto the SMD terminations. Once the solder has been rellowed, the
component can be removed with the aid of
tweezers. While the hot air is being directed
onto the component, cooler air is played onto
the bottom of the substrate to protect it from
heat damage. During removal, the component should be twisted sideways slightly in
order to break the surface tension of the
solder and any adhesive bond between the
component and the substrate. This prevents
damage to the substrate when the component is lifted.
.
To fit a new component, the solder lands are
first retinned and lIuxed, the new component
accurately placed, and the solder rellowed
with hot air. Substituting superheated argon,
nitrogen, or a mixture of nitrogen and hydrogen for the hot air stream removes any risk of
contaminating or oxidizing the solder.
Focused infrared light has also been used
successfully to rellow the solder on densely
populated substrates.
In general, the equipment and procedures
used for the replacement of PLCCs can be
used for lead less ceramic chip carriers
(LCCCs) and small-outline packages (SO
ICs). SO ICs are somewhat easier to replace,
as the leads are more accessible and only on
two sides of the component.
Signetics
Fluxing and Cleaning
Linear Products
INTRODUCTION
The adoption of mass soldering techniques
by the electronics industry was prompted not
only by economics, and a requirement for
high throughput levels, but also by the need
for a consistent standard of quality and reliability in the finished product unattainable by
using manual methods. With surface-mounted device (SMD) assembly, this need is even
greater.
The quality of the end-product depends on
the measures taken during the design and
manufacturing stages. The foundations of a
high-quality electronic circuit are laid with
good design, and with correct choice of
components and substrate configuration. It is,
however, at the manufacturing stage where
the greatest number of variables, both with
respect to materials and techniques, have to
be optimized to produce high-quality soldering, a prerequisite for reliability.
Of the two most commonly-used soldering
techniques, wave and reflow, wave soldering
is by far the most widely used and understood. Many factors influence the outcome of
the soldering operation, some relating to the
soldering process itself, and others to the
condition of components and substrate to
which they are to be attached. These must be
collectively assessed to ensure high-quality
soldering.
One of the most important, most neglected,
and least understood of these processes is
the choice and application of flux. This section outlines the fluxing options available, and
discusses the various cleaning techniques
that may be required, for SMD substrate
assembly.
FLUXES
Populating a substrate involves the soldering
of a variety of terminations simultaneously. In
one operation, a mixture of tinned copper,
tin/lead-or gold-plated nickel-iron, palladiumsilver, tin/lead-plated nickel-barrier, and even
materials like Kovar, each possessing varying
degrees of solderability, must be attached to
a common substrate using a single solder
alloy.
It is for this reason that the choice of the flux
is so important. The correct flux will remove
surface oxides, prevent reoxidization, help to
transfer heat from source to joint area, and
leave non-corrosive, or easily removable corrosive residues on the substrate. It will also
February 1987
improve wettability of the solder joint surfaces.
The wettability of a metal surface is its ability
to promote the formation of an alloy at its
interface with the solder to ensure a strong,
low-resistance joint.
However, the use of flux does not eliminate
the need for adequate surface preparation.
This is very important in the soldering of SMD
substrates, where any temptation to use a
highly-active flux in order to promote rapid
wetting of ill-prepared surfaces should be
avoided because it can cause serious problems later when the corrosive flux residues
have to be removed. Consequently, optimum
solderability is an essential factor for SMD
substrate assembly.
Flux is applied before the wave soldering
process, and during the reflow soldering process (where flux and solder are combined in a
solder cream). By coating both bare metal
and solder, flux retards atmospheric oxidization which would otherwise be intensified at
soldering temperature. In the areas where the
oxide film has been removed, a direct metalto-metal contact is established with one lowenergy interface. It is from this point of
contact that the solder will flow.
Types of Flux
There are two main characteristics of flux.
The first is efficacy-its ability to promote
wetting of surfaces by solder within a specified time. Closely related to this is the activity
of the flux, that is, its ability to chemically
clean the surfaces.
ed in varying quantities to increase it. These
take the form of either organic acids, or
organic salts that are chemically active at
soldering temperatures. It is therefore convenient to classify the colophony-based fluxes
by their activator content.
Non-Activated Rosin (R) Flux
These fluxes are formed from pure colophony
in a suitable solvent, usually isopropanol or
ethyl alcohol. Efficacy is low and cleaning
action is weak. Their uses in electronic soldering are limited to easily-wettable materials
with a high level of solderability. They are
used mainly on circuits where no risk of
corrosion can be tolerated, even after prolonged use (implanted cardiac pacemakers,
for example). Their flux residues are noncorrosive and can remain on the substrate,
where they will provide good insulation.
Rosin, Mildly-Activated (RMA)
Flux
These fluxes are also composed of colophony in a solvent, but with the addition of
activators, either in the form of di-basic organic acids (such as succinc acid), or organic
salts (such as dimethyl ammonium chloride or
diethylammonium chloride). It is customary to
express
the amount of added activator as mass percent of the chlorine ion on the colophony
content, as the activator-to-colophony ratio
determines the activity, and, hence, the corrosivity. In the case of RMA activated with
organic salts, this is only some tenths of one
percent.
Organic Soluble Fluxes
When organic acids are used, a higher percentage of activator must be added to produce the same efficacy as organic salts, so
frequently both salts and acids are added.
The cleaning action of RMA fluxes is stronger
than that of the R type, although the corrosivity of the residues is usually acceptable.
These residues may be left on the substrate
as they form a useful insulating layer on the
metal surfaces. This layer can, however,
impede the penetration of test probes at a
later stage.
Most of the fluxes soluble in organic liquids
are based on colophony or rosin (a natural
product obtained from pine sap that has been
distilled to remove the turpentine content).
Solid colophony is difficult to apply to a
substrate during machine soldering, so it is
dissolved in a thinning agent, usually an
alcohol. It has a very low efficacy, and hence
limited cleaning power, so activators are add-
The RA fluxes are similar to the RMA fluxes,
but contain a higher proportion of activators.
They are used mainly when component or
substrate solderability is poor and corrosionrisk requirements are less stringent. However,
as good solderability is considered essential
for SMD assembly, highly-activated rosin fluxes should not be necessary. The removal of
The second is the corrosivity of the flux, or
rather the corrosivity of its residues remaining
on the substrate after soldering. This is again
linked to the activity; the more active the flux,
the more corrosive are its residues.
Although there are many different fluxes
available, and many more being developed,
they fall into two basic categories; those with
residues soluble in organic liquids, and those
with residues soluble in water.
15-17
Rosin, Activated (RA) Flux
•
Signetics Linear Products
Fluxing and Cleaning
flux residues is optional and usually dependent upon the working environment of the
finished product and the customer's requirements.
Water-Soluble Fluxes
The water-soluble fluxes are generally used
to provide high fluxing activity. Their residues
are more corrosive and more conductive than
the rosin-based fluxes, and, consequently,
must always be removed from the finished
substrate. Although termed water soluble, this
does not necessarily imply that they contain
water; they may also contain alcohols or
glycols. It is the flux residues that are water
soluble. The usual composition of a watersoluble flux is shown below.
1. A chemically-active component for cleaning the surfaces.
2. A wetting agent to promote the spreading
of flux constituents.
3. A solvent to provide even distribution.
4. Substances such as glycols or watersoluble polymers to keep the activator in
close contact with the metal surfaces.
Although these substances can be dissolved
in water, other solvents are generally used, as
water has a tendency to spatter during soldering. Solvents with higher boiling pOints,
such as ethylene glycol or polyethylene glycol
are preferred.
Water-Soluble Fluxes With
Inorganic Salts
These are based on inorganic salts such as
zinc chloride, or ammonium chloride, or inorganic acids such as hydrochloric. Those with
zinc or ammonium chloride must be followed
by very stringent cleaning procedures as any
halide salts remaining on the substrate will
cause severe corrosion. These fluxes are
generally used for non-electrical soldering.
Although the hydrazine halides are among
the best active fluxing agents known, they are
highly suspect from a health point of view and
are therefore no longer used by flux manufacturers.
Water-Soluble Fluxes With
Organic Salts
These fluxes are based on organic hydrohalides such as dimethylammonium chloride,
cyclo hexalamine hydrochloride, and aniline
hydrochloride, and also on the hydrohalides
of organic acids. Fluxes with organic halides
usually contain vehicles such as glycerol or
polyethylene glycol, and non-ionic surfaceactive agents such as nonylphenol polyoxyethylene. Some of the vehicles, such as the
polyethylene glycols, can degrade the insulation resistance of epoxy substrate material
and, by rendering the substrate hydrophilic,
make it susceptible to electrical leakage in
high-humidity environments.
February 1987
Water-Soluble Fluxes With
OrganiC Acids
Based on acids such as lactic, melonic, or
citric, these fluxes are used when the presence of any halide is prohibited. However,
their fluxing action is weak, and high acid
concentrations have to be used. On the other
hand, they have the advantage that the flux
residues can be left on the substrate for some
time before washing without the risk of severe
corrosion.
Solder Creams
For reflow soldering, both the solder and the
flux are applied to the substrate before soldering and can be in the form of solder
creams (or pastes), preforms, electro-deposit,
or a layer of solder applied to the conductors
by dipping. For SMD reflow soldering, solder
cream is generally used.
Solder cream is a suspension of solder particles in flux to which special compounds have
been added to improve the rheological properties. The shape of the particles is important
and normally spherical particles are used,
although non-spherical particles are now being added, particularly in very fine-line soldering.
In principle, the same fluxes are used in
solder creams as for wave soldering. However, due to the relatively large surface area of
the solder particles (which can oxidize), more
effective fluxing is required and, in general,
solder creams contain a higher percentage of
activators than the liquid fluxes. The drying of
the solder paste during preheating (after component placement) is an important stage as it
reduces any tendency for components to
become displaced during soldering.
Flux Selection
Choosing an appropriate flux is of prime
importance to the soldering system for the
production of high-quality, reliable joints.
When solderability is good, a mildly-activated
flux will be adequate, but when solderability is
poorer, a more effective, more active flux will
be required. The choice of flux, moreover, will
be influenced by the cleaning facilities available, and if, in fact, cleaning is even feasible.
choice will be between an RA or an RMA
rosin-based flux.
Application of Flux
Three basic factors determine the method of
applying flux: the soldering process (wave or
reflow), the type of substrate being processed
(all-SMD or mixed print), and the type of flux.
For wave soldering, the flux must be applied
in liquid form before soldering. While it is
possible to apply the flux at a separate fluxing
station, with the high throughput rates demanded to maximize the benefits of SMD
technology, today's wave-soldering machines
incorporate an integral fluxing station prior to
the preheat stage. This enables the preheat
stage to be used to dry the flux as well as
preheat the substrate to minimize thermal
shock.
The most commonly-used methods of applying flux for wave soldering are by foam, wave,
or spray.
Foam Fluxing
Foam flux is generated by forcing low-pressure clean air through an aerator immersed in
liquid flux (see Figure 1). The fine bubbles
produced by the aerator are guided to the
surface by a chimney-shaped nozzle. The
substrates are passed across the top of the
nozzle so that the solder side comes in
contact with the foam and an even layer of
flux is applied. As the bubbles burst, flux
penetrates any plated-through holes in the
substrate.
Wave Fluxing
A double-sided wave can also be used to
apply flux, where the washing action of the
wave deposits a layer of flux on the solder
side of the substrate (see Figure 2). Waveheight control is essential and a soft, wipe-off
brush should be incorporated on the exit side
of the fluxing station to remove excess flux
from the substrate.
With water-soluble fluxes, aqueous cleaning
of the substrate after soldering is mandatory.
If thorough cleaning is not carried out, severe
problems may arise in the field, due to corrosion or short circuits caused by too low a
surface resistance of the conductive residues.
For rosin-based fluxes, the need for cleaning
will depend on the activity of the flux. Mildlyactivated rosin residues can, in most cases,
remain on the substrate where they will afford
protection and insulation. In practice, for the
great majority of electronic Circuits, the
15-18
AERATOR
COMPRESSED AIR
Figure 1. Schematic Diagram
of Foam Fluxer
Signetics Linear Products
Fluxing and Cleaning
PREHEATING
Preheating the substrate before soldering
serves several purposes. It dries the flux to
evaporate most of the solvent, thus increasing the viscosity. If the viscosity is too low, the
flux may be prematurely expelled from the
substrate by the molten solder. This can
result in poor wetting of the surfaces, and
solder spatter.
IMPELLER
Figure 2. Schematic Diagram
of Wave Fluxer
Spray Fluxing
Several methods of spray fluxing exist; the
most common involves a mesh drum rotating
in liquid flux. Air is blown into the drum which,
when passing through the fine mesh, directs
a spray of flux onto the underside of the
substrate (see Figure 3). Four parameters
affect the amount of flux deposited: conveyor
speed, drum rotation, air pressure, and flux
density. The thickness of the flux layer can be
controlled using these parameters, and can
vary between 1 and 10j1m.
The advantages and disadvantages of these
three flux application techniques are outlined
in Table 1.
Flux Density
One of the main control factors for fluxes
used in machine soldering is the flux density.
This provides an indication of the solids
content of the flux, and is dependent on the
nature of the solvents used. Automatic con·
trol systems, which monitor flux density and
inject more solvent as required, are commer·
cially available, and it is relatively simple to
incorporate them into the fluxing system.
Drying the flux also accelerates the chemical
action of the flux on the surfaces, and so
speeds up the soldering process. During the
preheating stage, substrate and components
are heated to between 80 0 G and 9D O G (solvent-based fluxes) or to between 1000 G and
11 DOG (water-based systems). This reduces
the thermal shock when the substrate makes
contact with the molten solder, and minimizes
any likelihood of the substrate warping.
The most common methods of preheating
are: convection heating with forced air, radiation heating using coils, infrared quartz lamps
or heated panels, or a combination of both
convection and radiation. The use of forced
air has the added advantage of being more
effective for the removal of evaporated solvent. Optimum preheat temperature and duration will depend on the nature and design of
the substrate and the composition of the flux.
Figure 4 shows a typical method of preheat
temperature control. The desired temperature
is set on the control panel, and the microprocessor regulates preheater No. 1 to provide
approximately 60% of the required heat. The
IR detector scans the substrate immediately
following No. 1 heater and reads the surface
temperature. By taking into account the surface temperature, conveyor speed, and the
thermal characteristics of the substrate, the
microprocessor then calculates the amount
of additional heat required to be provided by
heater No. 2 in order to attain the preset
temperature. In this way, each substrate will
have the same surface temperature on reaching the solder bath.
POSTSOLDERING CLEANING
ROTATING DRUM
Figure 3. Schematic Diagram
of Spray Fluxer
February 1987
Now thal worldwide efforts in both commercial and industrial electronics are converting
old designs from conventional assembly to
surface mounting, or a combination of both, it
can also be expected that high-volume cleaning systems will convert from in-line aqueous
cleaners to in-line solvent cleaners or in-line
saponification systems (a technique that uses
an alkaline material in water to react with the
rosin so that it becomes water soluble).
These systems may, however, become subject to environmental objections, and new
governmental restrictions on the use of halogenated hydrocarbons.
15-19
The major reason for this is that the watersoluble flux residues, containing a higher
concentration of activators, or showing hygroscopic behavior, are much more difficult to
remove from SMD-populated substrates than
rosin-based flux residues. This is primarily
because the higher surface tension of water,
compared to solvenls, makes it difficult for
the cleaning agents to penetrate beneath
SMDs, especially the larger ones, with their
greatly reduced off-contact distance (the distance between component and substrate).
Postsoldering cleaning removes any contamination, such as surface deposits, inclusions,
occlusions, or absorbed matter which may
degrade to an unacceptable level the chemical, physical, or electrical properties of the
assembly. The types of contaminant on substrates that can produce either electrical or
mechanical failure over short or prolonged
periods are shown in Table 2.
All these contaminants, regardless of their
origin, fall into one of two groups: polar and
non-polar.
Polar Contaminants
Polar contaminants are compounds that dissociate into free ions which are very good
conductors in water, quite capable of causing
circuit failures. They are also very reactive
with metals and produce corrosive reactions.
It is essential that polar contaminants be
removed from the substrates.
Non-Polar Contaminants
Non-polar contaminants are compounds that
do not dissociate into free ions or carry an
electrical current and are generally good
insulators. Rosin is a typical example of a
non-polar contaminant. In most cases, nonpolar contamination does not contribute to
corrosion or electrical failure and may be left
on the substrate. It may, however, impede
functional testing by probes and prevent good
conformal coat adhesion.
Solvents
The solvents currently used for the postsoldering cleaning of substrates are normally
organic based and are covered by three
classifications: hydrophobic, hydrophillic, and
azeotropes of hydrophobic/hydrophillic
blends.
Azeotropic solvents are mixtures of two or
more different solvents which behave like a
single liquid insomuch that the vapor produced by evaporation has the same composition as the liquid, which has a constant boiling
point between the boiling points of the two
solvents that form the azeotrope. The basic
ingredients of the azeotropic solvents are
combined with alcohols and stabilizers.
These stabilizers, such as nitromethane, are
included to prevent corrosive reaction be-
•
Signetlcs Linear Products
Fluxing and Cleaning
Table 1. Advantages and Disadvantages of Flux Application Methods
Advantages
Disadvantages
Foam
Fluxing
• Compatible with continuous
soldering process
• Foam crest height not
critical
• Suitable for mixed-print
substrates
• Not all fluxes have good foaming
capabilities
• Losses throught evaporation may
be appreciable
• Prolonged preheating because of
high boiling point of solvents
Wave
Fluxing
• Can be used with any
liquid flux
• Wave crest height is critical to
ensure good contact with bottom
of substrate without
contaminating the top
Method
• Compatible with continuous
soldering process
• Suitable for denselypopulated mixed print
Spray
fluxing
• Can be used with most
liquid fluxes
• Short preheat time if
appropriate alcohol
solvents are used
• Layer thickness is
controllable
tween the metallization of the substrate and
the basic solvents.
Hydrophobic solvents do not mix with water
at concentrations exceeding 0.2%, and consequently have little effect on ionic contamination. They can be used to remove nonpolar contaminants such as rosin, oils, and
greases.
Hydrophillic solvents do mix with water and
can dissolve both polar and non-polar contamination, but at different rates. To overcome these differences, azeotropes of the
various solvents are formulated to maximize
the dissolving action for all types of contamination.
Solvent Cleaning
Two types of solvent cleaning systems are in
use today: batch and conveyorized systems,
either of which can be used for high-volume
production. In both systems, the contaminated substrates are immersed in the boiling
solvents, and ultrasonic baths or brushes may
also be used to further improve the cleaning
capabilities.
The washing of rosin-based fluxes offers
advantages and disadvantages. Washed substrates can usually be inserted into racks
easier, as there will be no residues on their
edges; test probes can make better contact
without a rosin layer on the test pOints, and
the removal of the residues makes it easier to
visually examine the soldered joints. On the
other hand, washing equipment is expensive,
and so are the solvents, and some solvents
present a health or environmental hazard if
not correctly dealt with.
February 1987
• High flux losses due to nonrecoverable spray
• System requires frequent
cleaning
Aqueous Cleaning
For high-VOlume production, special machines have been developed in which the
substrates are conveyor-fed through the various stages of spraying, washing, rinsing, and
drying. The final rinse water is blown from the
substrates to prevent any deposits from the
water being left on the substrate.
Where water-soluble fluxes have been used
in the soldering process, substrate cleaning is
mandatory. For the rosin-based fluxes, it is
optional, and is often at the discretion of the
customer.
Conformal Coatings
A conformal, or protective coating on the
substrate, applied at the end of processing,
prevents or minimizes the effects of humidity
and protects the substrate from contamination by airborne dust particles. Substrates
that are to be provided with a conformal
coating (dependent on the environmental
conditions to which the substrate will be
subjected) must first be washed.
Environmental and Ecological
Aspects of Fluxes and Solvents
Fumes and vapors produced during soldering
processes, or during cleaning, will not, under
normal circumstances, present a health hazard, if relevant health and safety regulations
are observed.
Fumes originating from colo phony can cause
respiratory problems, so an efficient fumeextraction system is essential. The extraction
system must cover the fluxing, preheating,
and soldering stations, remain operational for
at least one hour after machine shutdown,
15-20
and conform to local regulations. Today, the
problem of noxious fumes is unlikely to concern the cleaning station, as all commercial
systems are equipped to condense the vapors back into the system. In the future,
however, it can be expected that a much
lower degree of escape of noxious fumes
from any system will be allowed, and all
systems may have to be reviewed.
Certain fluxes, particularly some water-soluble ones, contain highly aggressive substances, and must not be allowed to come
into contact with the skin or eyes. Any contamination should immediately be removed
with plenty of clean, fresh water. Deionized
water should also be readily available as an
eye-wash. Should contamination occur, a
qualified medical practitioner should be consulted. Protective clothing should be worn
during cleaning or maintenance of the fluxing
station.
Conclusion
SMD technology imposes tougher restraints
on fluxing and cleaning of substrate assemblies. Traditionally, rosin-based fluxes have
been used in electronic soldering where residues were considered "safe" and could be
left on the board. However, increased SMD
packing density, fine-line tracks, and more
rigid specifications have resulted in changes
to this basic philosophy.
There is now a demand for surfaces free from
reSidues; test probes are more efficient when
they do not have to penetrate rosin flux
residues, and conformal coating and board
inspection benefit from the absence of such
residues.
Cleaning also poses problems for SMD substrates. The close proximity of component
and substrate means ihat solvents cannot
effectively clean beneath devices. Components must also be compatible with the cleaning process. They must, for example, be
resistant to the solvents used and to the
temperatures of the cleaning process. They
must also be sealed to prevent cleaning fluids
from entering the devices and degrading
performance.
So, eliminating the need for cleaning is better
than poor or incomplete cleaning. And in a
well-balanced system, mildly-activated rosinbased fluxes, leaving only non-corrosive residues, can be successfully used for SMD
substrate soldering without subsequent
cleaning.
Much research into fluxes and solder creams
is presently being done - for example, the
production of synthetic resin, with qualities
superior to colophony at a lower cost. Another area of research is that of solder creams
with non-melting additives, such as lead or
ceramic spheres, that increase the distance
Signetics Linear Products
Fluxing and Cleaning
CONVEYOR
DRIVE
MOTOR
PRE·HEATER
2
SOLDER BATH
TEMPERATURE SET
CONTROL PANEL
Figure 4. Schematic Diagram of a Typical Controlled Preheat System
Table 2. Substrate Contaminants
Contaminant
Organic compounds
Inorganic insoluble compounds
Organo·metallic compounds
Inorganic soluble compounds
Particle matter
Origin
Fluxes, solder mask
Photo·resists, substrate processing
Fluxes, substrate processing
Fluxes
Dust, fingerprints
between component and substrate, thus
making it easier for cleaning fluids to pene·
trate beneath the component. It also in·
creases the joint's ability to withstand thermal
cycling.
Rosin·free and halide· free fluxes are also
being developed with similar activities to con·
ventional rosin·based fluxes. These new
types will combine the "safety" of rosin
fluxes with easier removal in conventional
solvents. Using non· polar materials, ionizable
or corrosive residues are eliminated, and the
need for cleaning immediately after soldering
is avoided.
•
February 19B7
15-21
Signetics
Thermal Considerations for
Surface-Mounted Devices
Linear Products
INTRODUCTION
Thermal characteristics of integrated circuit
(IC) packages have always been a major
consideration to both producers and users of
electronics products. This is because an increase in junction temperature (TJ) can have
an adverse effect on the long-term operating
life of an IC. As will be shown in this section,
the advantages realized by miniaturization
can often have trade-offs in terms of increased junction temperatures. Some of the
VARIABLES affecting TJ are controlled by
the PRODUCER of the IC, while others are
controlled by the USER and the ENVIRONMENT In which the device Is used.
With the increased use of Surface-Mount
Device (SMD) technology, management of
thermal characteristics remains a valid concern, not only because the SMD packages
are much smaller, but also because the
thermal energy is concentrated more densely
on the printed wiring board (PW8). For these
reasons, the designer and manufacturer of
surface-mount assemblies (SMAs) must be
more aware of all the variables affecting TJ.
POWER DISSIPATION
Power dissipation (PD), varies from one device to another and can be obtained by
multiplying Vcc Max by typical Icc· Since Icc
decreases with an increase in temperature,
maximum Icc values are not used.
THERMAL RESISTANCE
The ability of the package to conduct this
heat from the chip to the environment is
expressed in terms of thermal resistance. The
term normally used is Theta JA (OJA)' OJA is
often separated into two components: thermal resistance from the junction to case, and
the thermal resistance from the case to
ambient. OJA represents the total resistance
to heat flow from the chip to ambient and is
expressed as follows:
OJC
+ OCA = OJA
JUNCTION TEMPERATURE (TJ)
Junction temperature (TJ) is the temperature
of a powered IC measured by Signetics at the
.w.wJ.
rmm
so LEADFRAME
DIP LEADFRAME
DIP LEADFRAME
b. PLCC-68 Leadframe Compared
to a 64-Pln DIP Leadframe
a. SO-14 Leadframe Compared
to a 14-Pln DIP Leadframe
Figure 1
February 1987
15-22
Signetics Linear Products
Thermal Considerations for Surface-Mounted Devices
substrate diode. When the chip is powered,
the heat generated causes the T J to rise
above the ambient temperature (TA)' T J is
calculated by multiplying the power dissipation of the device by the thermal resistance of
the package and adding the ambient temperature to the result.
TJ=(Po
x
8JA)+TA
FACTORS AFFECTING 8JA
There are several factors which affect the
thermal resistance of any IC package. Effective thermal management demands a sound
understanding of all these variables. Package
variables include the leadframe design and
materials, the plastic used to encapsulate the
device, and, to a lesser extent, other variables such as the die size and die attach
methods. Other factors that have a significant
impact on the 8JA include the substrate upon
which the IC is mounted, the density of the
layout, the air-gap between the package and
the substrate, the number and length of
traces on the board, the use of thermallyconductive epoxies, and external cooling
methods.
PACKAGE CONSIDERATIONS
Studies with dual in-line plastic (DIP) packages over the years have shown the value of
proper leadframe design in achieving minimum thermal resistance. SMD leadframes
are smaller than their DIP counterparts (see
Figures 1a and 1b). Because the same die is
used in each of the packages, the die-pad, or
flag, must be at least as large in the SO as in
the DIP.
While the size and shape of the leads have a
measurable effect on 8JA, the design factors
that have the most significant effect are the
die-pad size and the tie-bar size. With design
constraints caused by both miniaturization
and the need to assemble packages in an
automated environment, the internal design
of an SMD is much different than in a DIP.
However, the design is one that strikes a
balance between the need to miniaturize, the
need to automate the assembly of the package, and the need to obtain optimum thermal
characteristics.
lEAD FRAME MATERIAL is one of the more
important factors in thermal management.
For years, the DIP leadframes were constructed out of Alloy-42. These leadframes
met the producers' and users' specifications
in quality and reliability. However, three to five
years ago the lead frame material of DIPs was
changed from Alloy-42 to Copper (ClF) in
order to provide reduced 8JA and extend the
reliable temperature-operating range. While
this change has already taken place for the
DIP, it is still taking place for the SO package.
February 1987
Signetics began making 14-pin SO packages
with ClF in April 1984 and completed conversion to ClF for all SO packages by 1985. As
is shown in Figures 10 through 14, the
change to ClF is producing dramatic results
in the 8JA of SO packages. All PlCCs are
assembled with copper leadframes.
The MOLDING COMPOUND is another factor
in thermal management. The compound used
by Signetics and Philips is the same high
purity epoxy used in DIP packages (at present, HC-10, Type II). This reduces corrosion
caused by impurities and moisture.
OTHER FACTORS often considered are the
die-size, die-attach methods, and wire bonding. Tests have shown that die size has a
minor effect on 8JA (see Figures 10 through
14).
While there is a difference between the
thermal resistance of the silver-filled adhesive
used for die attach and a gold silicon eutectic
die attach, the thickness of this layer (1 - 2
mils) is so small it makes the difference
insignificant.
Gold-wire bonding in the range of 1.0 to 1.3
mils does not provide a significant thermal
path in any package.
In summary, the SMD leadframe is much
smaller than in a DIP and, out of necessity, is
designed differently; however, the SMD package offers an adequate 8JA for all moderate
power devices. Further, the change to ClF
will reduce the 8JA even more, lowering the TJ
and providing an even greater margin of
reliability.
SIGNETICS' THERMAL
RESISTANCE
MEASUREMENTS - SMD
PACKAGES
The graphs illustrated in this application note
show the thermal resistance of Signetics'
SMD devices. These graphs give the relationship between 8JA Gunction-to-ambient) or 8JC
Gunction-to-case) and the device die size.
Data is also provided showing the difference
between still air (natural convection cooling)
and air flow (forced cooling) ambients. All 8JA
tests were run with the SMD device soldered
to test boards. It is important to recognize
that the test board is an essential part of the
test environment and that boards of different
sizes, trace layouts, or compositions may give
different results from this data. Each SMD
user should compare his system to the
Signetics test system and determine if the
data is appropriate or needs adjustment for
his application.
15-23
Test Method
Signetics uses what is commonly called the
TSP (temperature-sensitive parameter) method. This method meets Mil-STD 883C, Method 1012.1. The basic idea of this method is to
use the forward voltage drop of a calibrated
diode to measure the change in junction
temperature due to a known power dissipation. The thermal resistance can be calculated using the following equation:
Ll.TJ TJ- TA
8JA=-=-Po
Po
Test Procedure
TSP Calibration
The TSP diode is·calibrated using a constanttemperature oil bath and constant-current
power supply. The calibration temperatures
used are typically 25°C and 75°C and are
measured to an accuracy of ± 0.1 °c. The
calibration current must be kept low to avoid
significant junction heating; data given here
used constant currents of either 1.0mA or
3.0mA. The temperature coefficient (K-Factor) is calculated using the following equation:
Temperature Coefficient (OC/mV)
Higher Test Temperature (0C)
lower Test Temperature (0C)
Forward Voltage at IF and T2
Forward Voltage at IF and T1
Constant Forward Measurement Current
(See Figure 2)
Where: K
T2
T1
VF2
VF1
IF
=
=
=
=
=
=
VF(VOLTS)
Figure 2. Forward Voltage - Junction
Temperature Characteristics of a
Semiconductor Junction Operating at
a Constant Current. The K Factor Is
the Reciprocal of the Slope
Thermal Resistance
Measurement
The thermal resistance is measured by applying a sequence of constant current and
constant voltage pulses to the device under
test. The constant current pulse (same current at which the TSP was calibrated) is used
to measure the forward voltage of the TSP.
The constant voltage pulse is used to heat
the part. The measurement pulse is very short
•
Signetics Linear Products
Thermal Considerations for Surface-Mounted Devices
(less than 1% of cycle) compared to the
heating pulse (greater than 99% of cycle) to
minimize junction cooling during measurement. This cycle starts at ambient temperature and continues until steady-state conditions are reached. The thermal resistance
can then be calculated using the following
equation;
.Cl.TJ K{VFA - VFS)
eJA = = -'--'-'-'--'-=
Po
VH X IH
Where; VFA
= Forward Voltage of TSP at Ambient Temperature (mY)
VFS
= Forward
Voltage of TSP at
Steady-State Temperature
(mY)
VH
= Heating Voltage (V)
IH
=
Heating Current (A)
Figure 3_ Board Trace Configuration for Thermal Resistance Test Boards
Test Ambient
eJA Tests
All eJA test data collected in this application
note was obtained with the SMD devices
soldered to either Philips SO Thermal Resistance Test Boards or Signetics PLCC Thermal Resistance Test Boards with the following parameters;
Board size
-
SO Small
1.12" X 0.75" X 0.059"
- SO Large;
1.58" X 0.75" X 0.059"
-PLCC;
2.24" X 2.24" X 0.062"
Board Material- Glass epoxy, FR-4 type
with 10z. sq.ft. copper solder coated
Board Trace Configuration - See Figure 3.
SO devices are set at 8 - 9mil stand-off and
SO boards use one connection pin per device
lead. PLCC boards generally use 2 - 4 connection pins regardless of device lead count.
Figure 5 shows a cross-section of an SO part
soldered to test board, and Figure 4 shows
typical board/device assemblies ready for eJA
Test.
The still-air tests were run in a box having a
volume of 1 cubic foot of air at room temperature. The air-flow tests were run in a 4" X 4"
cross-section by 26" long wind tunnel with air
at room temperature. All devices were
soldered on test boards and held in a horizontal test position. The test boards were held in
a Textool ZIF socket with 0.16" stand-off.
Figure 6 shows the air-flow test setup.
eJC Tests
The eJC test is run by holding the test device
against an "infinite" heat sink (water-cooled
block approximately 4" X 7" X 0.75") to give
February 1987
Figure 4_ Device/Board Assemblies
a eCA (case-to-ambient) approaching zero.
The copper heat sink is held at a constant
temperature ("'20'C) and monitored with a
thermocouple (O.040" diameter sheath,
grounded junction type K) mounted flush with
heat-sink surface and centered below die in
the test device. Figure 7 shows the eJC test
mounting for a PLCC device.
SO devices are mounted with the bottom of
the package held against the heat sink. This
is achieved by bending the device leads
straight out from the package body. Two
small wires are soldered to the appropriate
leads for tester connection. Thermal grease
is used between the test device and heat sink
to assure good thermal coupling.
PLCC devices are mounted with the top of
the package held against the heat sink. A
15-24
n
TESfDEVICE
PART SfAND-OFF
TEsrBOARD
PLASTIC PIN
SUPPORT
CONNECTION
PINS
Figure 5_ Cross-Section of Test Device
Soldered to Test Board
small spacer is used between the hold-down
mechanism and PLCC bottom pedestal.
Small hook-up wires and thermal grease are
used as with the SO setup. Figure 7 shows
the PLCC mounting.
Signetics Linear Products
Thermal Considerations for Surface-Mounted Devices
PLCC DEVICES
SO DEVICES
lo®l·l0 (.004) 1
any side.
7.60 (.299)
7.40 (.291)
10.65 (.419)
10.26 (.404)
1-.IE®I·25 (.010) ® I
U,.27 (.050)
r·
esc
-o-r-----r-------------
lB.l0 (.713)
17.70 (.697)
75 (.030) X45.
.50 (.020)
,
§
L
-----l
.10 (.004) 1
2.65 (.104)
2.35 (.093)
t
-,
.4B (.019)
.35 (.014)
_+..1T I E lo®1
.25 (.010) @
I
~~'-------"
I
.32 (.013)
.23 (.009)
853-0006 B1217
4-PIN HERMETIC TO-72 HEADER (E PACKAGE)
February 1987
S. Pin numbers start with pin # 1 and continue
counterclockwise to pin #28 when viewed from top.
6. Signetics ordering code for a product packaged in a
plastic small outline (SO) package is the suffix Dafter
the product number.
15-40
1.07 (.042)
.10 (.004)
.B6 (.034)
Signetics Linear Products
For Prefixes ADC, AM, CA, DAC, LF, LM,
MC, NE, SA, SE, SG, pA, ULN
Package Outlines
a-PIN CERDIP (FE PACKAGE)
NOTES:
1. Controlling dimension: inches. Millimeters are shown in
parentheses.
2. Dimensions and tolerancing per ANSI Y14.SM - 1982.
3. "T", "0", and "E" are reference datums on the body
and include allowance for glass overrun and meniscus on
the seal line, and lid to base mismatch.
4. These dimensions measured with the leads constrained
to be perpendicular to plane T.
5. Pin numbers start with pin # 1 and continue
counterclockwise to pin #8 when viewed from the top.
.055 (1.40)
.030 (.76)
1----+--.100 (2.54) ese
853·0580 81594
14-PIN CERDIP (F PACKAGE)
1
NOTES:
1. Controlling dimension: inches. Millimeters are shown in
parentheses .
2. Dimensions and tolerancing per ANSI Y14.5M - 1982.
3. "T", "0", and "E" are reference datums on the body
and include allowance for glass overrun and meniscus on
the seal line, and lid to base mismatch.
4. These dimensions measured with the leads constrained
to be perpendicular to plane T.
5. Pin numbers start with pin # 1 and continue
counterclockwise to pin #14 when viewed from the top.
.110 (2.79)
•050 (1.27)
.320 (8.13)
.290 (7.37)
(NOTE 4)
~
.:
sse
.300 (7.62)
(NOTE 4)
.395 10.03
.300 7.62)
J L ' 0 2 3 (.58)..,.j$fTI Elo®I.010 (.254)
.015 (.38)
•
853·0581 81594
February 1987
15-41
Signetics Linear Products
For Prefixes ADC, AM, CA, DAC, LF, LM,
MC, NE, SA, SE, SG, pA, ULN
Package Outlines
16·PIN CERDIP (F PACKAGE)
NOTES:
1. Controlling dimension: inches. Millimeters are shown in
parentheses.
2. Dimensions and tolsrancing per ANSI Y14.SM - 1982.
3. "T" I "0", and "E" are reference datums on the body
and include allowance for glass overrun and meniscus on
the seal line, and lid to base mismatch.
4. These dimensions measured with the leads constrained
to be perpendicular to plane T.
5. Pin numbers start with pin #1 and continue
counterclockwise to pin #16 when viewed from the top.
"
~ '300(7'62) BSC:J
~
-l
~
JL'023 {.588»----I$I r IElo®I.Q10 (.254)
.015 (.3
(NOTE 4)
.395 (10.03)
f-
.300 (7.62)
853-0582 81594
18·PIN CERDIP (F PACKAGE)
-j
I
NOTES:
[.098 (2.49)
1. Controlling dimension: inches. Millimeters are shown in
parentheses.
2. Dimensions and tolerancing per ANSI Y14.5M - 1982.
3. "r', "0", and "E" are reference datums on the body
and include allowance for glass overrun and meniscus on
the seal line, and lid to base mismatch.
4. These dimensions measured with the leads constrained
to be perpendicular to plane T.
5. Pin numbers start with pin # 1 and continue
counterclockwise to pin #18 when viewed from the top.
.012 (.30)
~::""::"::"'''-''-''-''~~'''YI
.306 (7.77)
JL'023
(.58)--@l
.015 (,38)
r IElo@j.010 (.254)
853-0583 81594
February 1987
15-42
Signetlcs Linear Products
For Prefixes ADC, AM, CA, DAC, LF, LM,
MC, NE, SA, SE, SG, pA, ULN
20-PIN CERDIP (F PACKAGE)
1--.Q78 (1.98)
I
.012 (.30)
1
r
.078 (1.9B)
.012 (.30)
·--·i-'D...='-".::w='-"".::w"-"~:::"""=~:::"""~~7.77)
Package Outlines
NOTES:
1. Controlling dimension: inches. Millimeters are shown in
parentheses.
2. Dimensions and tolsrancing per ANSI Y14.SM - 1982.
S. "T". "0". and "E" are reference datums on the body
and include allowance for glass overrun and meniscus on
the seal line, and lid to base mismatch.
4. These dimensions measured with the leads constrained
to be perpendicular to plane T.
5. Pin numbers start with pin #1 and continue
counterclockwise to pin #20 when viewed from the top.
J L . 0 2 3 (·5B)--l$ITIElo@i.Ol0 (.254)
.015 (.38)
853-0584 81594
22-PIN CERDIP (F PACKAGE)
NOTES:
1. Controlling dimension: inches. Millimeters are shown in
parentheses.
2. Dimensions and tolsrancing per ANSI Y14.5M - 1982.
3. "T", "D", and "E" are reference datums on the body
and include allowance for glass overrun and meniscus on
the seal line, and lid to base mismatch.
4. These dimensions measured with the leads constrained
to be perpendicular to plane T.
5. Pin numbers start with pin #1 and continue
counterclockwise to pin #22 when viewed from the top.
JL
•
.023 (·5B)-I$lTIElo®I.D10 (.254)
.015 (.3B)
853-0585 81594
February 19B7
15-43
Signetics Linear Products
For Prefixes ADC, AM, CA, DAC, LF, LM,
MC, NE, SA, SE, SG, pA, ULN
Package Outlines
24-PIN CERDIP (F PACKAGE)
.09B (2.49)
NOTES:
1. Controlling dimension: Inches. Millimeters are shown In
parentheses.
.040 (1.02)
2. Dimensions and toleranclng per ANSI Y14.SM - 1982.
"r', "0", and "E" are reference datums on the body
and Include allowance for glass overrun and meniscus on
3,
the seal line, and lid to base mismatch.
4. These dimensions measured with the leads constrained
to be perpendicular to plane T.
.
5. Pin numbers start with pin #1 and continue
.59B 15.19)
counterclockwise to pin #24 when viewed from the top.
.514 r.06)
D~.~:::~J:_'_L~:.~'0:0~(2.i?~" ~8Bi '5sr;"'i32?84"'i:)Di'1i""""'iJ'ViI·
Ifii'i.
1240 (31.50)
l_:~::;~~:---r
ill-
I~
~
.620 (15.75)
.175 (4.45)
.145 (3.88)
.590 (14.99)
(NOTE 4)
.225 (5.72) MAX.
~4.19
~
~3.18
.
JL::::--I!l'" ~m. "'" .,
.eoc\'~5.24)~
(NOTE 4)
~
10
.600 (15.25)
B53'()5BB 84221
28-PIN CERDIP (F PACKAGE)
NOTES:
1. Controlling dimension: inches. Millimeters are shown in
parentheses.
2. Dimensions and tolerancing per ANSI Y14.5M -
1982.
3. "T", "0", and "E" are reference datums on the body
and Include allowance for glass overrun and meniscus on
the seal line, and lid to base mismatch.
4. These dimensions measured with the leads constrained
to be perpendicular to plane T.
5. Pin numbers start with pin #1 and continue
counterclockwise to pin #28 when viewed from the top.
6. Denote. window location 'or EPROM Produc1s.
J L.'00(2.54)BSC
1.486(37.72)
1.440(38.88)
R II R Y t1R
J-:::::--IoI*IO., ~_
H
II
81
853'()589 64000
February 1987
15·44
Signetics Linear Products
For Prefixes ADC, AM, CA, DAC, IF, lM,
MC, NE, SA, SE, SG, pA, UlN
Package Outlines
20-PIN PGA (G PACKAGE)
"~·X~~~:::~~lh45(~~;~El:::~~
lbl r·
.022 (.56)
.055 (1.40)
PIN ",
~
NOTES:
1. Package dimensions conform to Mil-M-38510. outline NO.
2, 20 leads, square ceramic leadless chip carrier.
2. Controlling dimension: inches, millimeters are shown in
parenthesis.
3. Dimension and tolerancing per ANSI Y14.5M - 1982.
4. This dimension represents the minimum spacing between
the corner contact pads. Theso corner pads may have a
.020 inch by 45 degree maximum chamfer to accomplish
the .015 minimum spacing.
5. Pin numbers start with pin #1 and continue
counterclockwise to pin #20 when viewed from the top.
6. Signetics order code for product packaged in a CCCL is
the suffix "G" after the product number.
e -
P
OO6 (.15) TY .
.360 (9.14)
~5
t=
["'6)
(.'6) TYp:j _J
.015
.003 (.OB)
.360 (9.14)
.345 (8.76)
Jl
J
- - TYP.----tIII-·028(.71)
.022 (.56)
~
.063 (1.60)
.085 (2.16) TVP.
.065 (1.65)
.015 (.38) MIN.
(4 CORNERS)
853·0063 82276
8-PIN HERMETIC TO-5 HEADER (H PACKAGE)
1-L~O'A.Jl
8.00 (.315l
-r-~O'610'OI
:~
051\",0' (
1428 (562)
'i2"7Oi5OOi
nOD n0
~INSULATOR
038(015)
~DIA
::~~ ::i~~: CIA.
0.41 (.016)
8 LEACS
II
February 19B7
15-45
Signetics Linear Products
For Prefixes ADC, AM, CA, DAC, LF, LM,
MC, NE, SA, SE, SG, pA, ULN
10-PIN HERMETIC TO-S/100 HEADER SHORT CAN (H PACKAGE)
10-PIN HERMETIC TO-S/100 HEADER TALL CAN (H PACKAGE)
February 1987
15-46
Package Outlines
Signetics Unear Products
For Prefixes ADC, AM, CA, DAC, LF, LM,
MC, NE, SA, SE, SG, pA, ULN
Package Outlines
16-PIN HERMETIC SDIP (I PACKAGE)
I~[~~]~l~
I
0.51
.1
20.70 C,8151
19.93 (.785)
I
1.65 (.065)
12.95 (.510\
_I
~: ::~~:
;:!~
',::1,
,.D20.:.L
' '~~r1rl~~~~,:]J~$l~~=IT~1-. (Note
T
~
T
13.1.005\ MIN.
_....L_ _ ~
0.31 (.0121
0.20 (.0081
I
8.74 (.344)
7.111.280)
"""'''''
8-PIN PLASTIC PDIP (N PACKAGE)
NOTES:
1. Controlling dimension: inches. Metric are shown in
parentheses.
2. Package dimensions conform to JEDEC specification
MS·Q01·AB for standard dual in-line (DIP) package .SOO
inch row spacing (PLASTIC) 8 leads (issue B. 7/85)
3. Dimensions and toleranc;ng per ANSI Y14. 5M·1992.
4. "T", "0" and liE" are reference datums on the molded
body and do not Include mold flash or protrusions. Mold
flash or protrusions shall not exceed .010 inch (.25mm)
on any side.
5. These dimensions measured with the leads constrained
to be perpendicular to plane T.
6. Pin numbers start with pin #1 and continue
counterclockwise to pin #8 when viewed from the top.
.255 (6.48)
.245 t22)
~I
•IOO(2.54)(BSO)
---l
.376 (.955)
.385 (.930)
.064 (1.63)
CORNER
t-
lEAD
OPT,ON
.045 (1.14)
(4 PLACES)
.322 (8.18) _
.300 (7.62)
(NOTE 5)
.125 (3.18)
~
PLANE
~
.035 1(.89)
.120 (3.05)
.022 (.56)
.017 (A3)
#lTlEIO®!
.010 (.25)
if
.020 ( , 5 : 1 ; )
.138 (3.51)
i!lI I
.015 (.38)
.010 (.25)
653'()404 81230
BSC
.300 (7.62)
(NOTE 5)
.395 (10.03)
.300 ( 7.62)
P000312S
•
February 1987
15-47
Signetics Linear Products
For Prefixes ADC, AM, CA, DAC, LF, LM,
MC, NE, SA, SE, SG, pA, ULN
Package Outlines
14·PIN PLASTIC DIP (N PACKAGE)
NOTES:
1. Controlling dimension: inches. Metric are shown in
parentheses.
2. Package dimensions conform to JEDEC specification
MS-001-AC for standard dual in-line (DIP) package .SOO
inch row spacing (PLASTIC) 14 leads (issue B. 7/85)
3. Dimensions and tolerancing per ANSI Y14. SM-1982.
4. "T". "0" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .010 inch (.2Smm)
on any side.
5. These dimensions measured with the leads constrained
to be perpendicular to plane T.
6. Pin numbers start with pin # 1 and continue
counterclockwise to pin # 14 when viewed from the top.
PLANE
~
1'8~9)
ff
.035
.020 1.51)
.13813.51)
#IT/EIO@I.Ol0 (.25)
.0151·38 )
@I
ssc
.300 17.62)
INOTE 5)
.395 110.03)
.300 ( 7.62)
.120 13.05)
.0101.25 )
853-0405 81231
16·PIN PLASTIC DIP (N PACKAGE)
OS
.004 .10
NOTES:
1. Controlling dimension: inches. Metric are shown in
parentheses.
2. Package dimensions conform to JEDEC specification
MS-001-AA for standard dual In-Jine (DIP) package .300
inch row spacing (PLASTIC) 16 leads (issue B. 7185)
3. Dimensions and tolerancing per ANSI Y14. SM-1982.
4. 'T', "0" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .010 inch (.2Smm)
on any side.
5. These dimensions measured with the leads constrained
to be perpendicular to plane T.
6. Pin numbers start with pin #1 and continue
counterclockwise to pin # 16 when viewed from the top.
CORNER
lEAD
.322 18.18)
OPTION
.300 17.62)
INOTE 5)
14 PLACES)
J
.12513.18)
~
~
PLANE
.035 (.89)
.138 13.51)
.120 13.05)
--i+ITIE@ 010 (.25)
ij I
.0151.38 )
.0101.25 )
853'()406 81232
February 1987
ii
.0201:1")
15-48
ssc
.300 (7.82)
INOTE 5)
.395 110.03)
:3oOT'7.62i
~\\
Signetics Linear Products
For Prefixes ADC, AM, CA, DAC, LF, LM,
MC, NE, SA, SE, SG, JJA, ULN
Package Outlines
18-PIN PLASTIC DIP (N PACKAGE)
o
.004
,10)
NOTES:
1. Controlling dimension: inches, Metric are shown in
parentheses.
2. Package dimensions conform to JEDEC specification
MS-001-AD for standard dual in-line (DIP) package .300
inch row spacing (PLASTIC) 18 leads (issue 8. 7/85)
3. Dimensions and tolsrancing per ANSI Y14. 5M-19B2.
4. "r', "0" and "e" are reference datums on the molded
body and do not include mold nash or protrusions. Mold
flash or protrusions shall not exceed .010 Inch (.2Smm)
on any side.
5. These dimensions measured with the leads constrained
to be perpendicular to plane T.
6. Pin numbers start with pin #1 and continue
counterclockwise to pin # 18 when viewed from the top.
r-
.322 (8.16) _
.300 (7.62)
(NOTE 5)
!.-JI==·-=-·==-.lkl
.125 (3.18)
~
PlANE
~
.1.
JL
ii
:~: :::j6~:~II
.138 (3.51)
.120 (3.05)
.022 (.56) -l+lTIE!O@)I .010 (.25)
.017 (.43)
(f"
@I
ssc
.015 (.38)
.300 (7.62)
(NOTE 5)
.395 (10.03)
,0\0 (.25)
.300 ( 7.82)
853·0407 61233
'""""'"
20-PIN PLASTIC DIP (N PACKAGE)
DS.OO4
.10
NOTES:
1. Controlling dimension: inches. Metric arB shown in
parentheses.
2. Package dimensions conform to JEDEC specification
M5-0D1·AE for standard dual In-line (DIP) package .300
Inch row spacing (PLASTIC) 20 I.ads (lssu. S. 7/65)
3. Dimensions and tolerancing per ANSI Y14. 5M·1982.
~~~~~~~~
4. "T", "0" and "E" are reference datums on the molded
.255 (6.48)
body and do not Include mold flash or protrusions. Mold
flash or protrusions shall not exceed .010 inch (.25mm)
on any side.
5. These dimensions measured with the leads constrained
to be perpendicular to plane T.
6. Pin numbers start with pin #1 and continue
counterclockwise to pin #20 when viewed from the top.
PIN#1
E-ii:D~--t----- 1.057
(26.65)
~
.322 (6.16)
~
.300 (7.62)
.Q45 (1.14)
(NOTE 5)
sse
.300 (7.62)
(NOTE 5)
.Ji/TiE!O®!..010
(.25)
~
*1
.300 ( 7.62)
653.()406 61234
February 1987
15-49
•
Signetics linear Products
For Prefixes ADC, AM, CA, DAC, IF, lM,
MC, NE, SA, SE, SG, pA, UlN
Package Outlines
22-PIN PLASTIC DIP (N PACKAGE)
o S ,004
(0.10)
I
.L_ _
NOTES:
1. Controlling dimension: inches. Metric are shown in
parentheses.
2. Package dimensions conform to JEDEC specification
MS-010-AA for standard dual in-line (DIP) package .400
Inch row spacing (PLASTIC) 22 leads (issue A. 7/85)
3. Dimensions and tolerancing per ANSI Y14. 5M-1982.
4. "T", "0" and liE" afS reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .010 inch (.25mm)
on any side.
5. These dimensions measured with the leads constrained
to be perpendicular to plane T.
.355 (9.02)
--+T:'fT:"FFfTT"i""f""FifT"'F'FfTT"iTTId!~(B.76)
U - . ' 0 0 (2.54) BSe
1,110 (28.19)
-D·
.064 (1.63)
1.095 (27.81)
.045 (1.14)
6. Pin numbers start with pin # 1 and continue
counterclockwise to pin #22 when viewed from the top.
:J
r-
.190 (4.B3)
~
.165 (4.19)
.145 (3-j1:-6B_)_ _-t.r_-'-c.,.r--.
PLANE
~
I!
1
.035 (.B9)
.020
.138 (3.51)
(.=-t')
.120 (3.05)
-I+ITIEIDOO.010
(.251
.422 (10.72)
.400 (10.Hi) (NOTE 5)
.015 (.38)
<8i1
_
sse
.400 (10.16)
(NOTE 5)
.495 (12.57)
j\\
--l
.400 (10.18)
.010 (.25)
853·0409 81235
24-PIN PLASTIC DIP (N PACKAGE)
NOTES:
1. ContrOlling dimension: Inches. Metric are shown in
parentheses.
2. Package dimensions conform to JEDEC specification
MS-011-M for standard dual in-line (DIP) package ,600
inch row spacing (PLASTIC) 24 leads (issue B. 7/85)
3. Dimensions and tolerancing per ANSI Y14. 5M-1982.
4. "T", "0" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .010 inch (.25mm)
on any side .
5. These dimensions measured with the leads constrained
to be perpendicular to plane T.
6. Pin numbers start with pin # 1 and continue
counterclockwise to pin #24 when viewed from the top.
s .004 .10
I
:J
.555 (14.10)
.545 (13.84)
~~~~
~plliIN~]---~W
H - . ' 0 0 (2.54) BSC
E![}--+----- ~:: ~:~::~
.064 (1.63)
.155 (3.94)
.045 (1.14)
.145 (3.68)
PLANE
~
'045(1'~4)
I,
.138 (3.51)
.020 (.51)
.120 (3.05)
-t+IT! EiD@ .010 (.25) # I
\~
.600 (15.24) Bse--l
(NOTE 5)
.015 (.36)
.695 (17.65)
~
.600 (15.24)
853-0412 81238
February 1987
I--
15·50
I
Signetics Linear Products
For Prefixes ADC, AM, CA, DAC, LF, LM,
MC, NE, SA, SE, SG, pA, ULN
Package Outlines
28-PIN PLASTIC DIP (N PACKAGE)
NOTES:
1. Controlling dimension: inches. Metric are shown in
parentheses.
[
2. Package dimensions conform to JEDEC specification
MS-01'-AB for standard dual in-line (DIP) package .600
inch row spacing (PLASTIC) 28 leads (issue B. 7/85)
3. Dimensions and tolerancing per ANSI Y14. 5M-1982.
~..~
4. "T", "0" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .010 inch (.25mm)
on any side.
5. These dimensions measured with the leads constrained
to be perpendicular to plane T.
6. Pin numbers start with pin #1 and continue
counterclockwise to pin #28 when viewed from the top.
~
.. =+WVV~~vvi' ~...)
rnr_+___·'_OO_(2._::::::
.D84 (1.83)
.045 (1.'4)
::J
.155 (3.94)
.145(3.68)
t=J
~ Ii
PLANE
.,,. (3.51)
.120 (3.05)
::
~:~
1+IrfED@.010 f.25)
#1
.020
~
(.':t:)
.... ('5.24)
8.0---11
.Q15 (.38)
(NOTE 5)
.695 (17.65)
i1o"'ii5i
.600 (U.24)
853·04'3 84099
•
February 1987
15-51
Signetics
Package Outlines
For Prefixes HEF, OM, MEA,
PCO, PCF, PNA, SAA, SAB, SAF,
TBA, TCA, TOA, TOO, TEA
Linear Products
INTRODUCTION
Soldering
immediately after soldering to keep the temperature within the permissible limit.
1. By hand
3. Repairing soldered joints
The same precautions and limits apply as in
(1) above.
Apply the soldering iron below the seating
plane (or not more than 2mm above it). If its
temperature is below 300'C it must not be in
contact for more than 10 seconds; if between
300'C and 400'C, for not more than 5 seconds.
2. By dip or wave
The maximum permissible teniperature of the
solder is 260'C; this temperature must not be
in contact with the joint for more than 5
seconds. The total contact time of successive
solder waves must not exceed 5 seconds.
The device may be mounted up to the seating
plane, but the temperature of the plastic body
must not exceed the specified storage maximum. If the printed-circuit board has been
pre-heated, forced cooling may be necessary
February 1987
SMALL OUTLINE (SO)
PACKAGES
The Reflow Solder Technique
The preferred technique for mounting miniature components on hybrid thick or thin-film
circuits is reflow soldering. Solder is applied
to the required areas on the substrate by
dipping in a solder bath or, more usually, by
screen printing a solder paste. Components
are put in place and the solder is reflowed by
heating.
Solder pastes consist of very finely powdered
solder and flux suspended in an organic liquid
binder. They are available in various forms
depending on the specification of the solder
15-52
and the type of binder used. For hybrid circuit
use, a tin-lead solder with 2 to 4 % silver is
recommended. The working temperature of
this paste is about 220 to 230'C when a mild
flux is used.
For printing the paste onto the substrate a
stainless steel screen with a mesh of 80 to
10511m is used for which the emulsion thickness should be about 50l1m. To ensure that
sufficient solder paste is applied to the substrate, the screen aperture should be slightly
larger than the corresponding contact area.
The contact pins are positioned on the substrate, the slight adhesive force of the solder
paste being sufficient to keep them in place.
The substrate is heated to the solder working
temperature preferably by means of a controlled hot plate. The soldering process
should be kept as short as possible: 10 to 15
seconds is sufficient to ensure good solder
joints and evaporation of the binder fluid.
After soldering, the substrate must be
cleaned of any remaining flux.
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCO, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TOA, TOO, TEA
Package Outlines
a-PIN PLASTIC SO (SOT-97A)
,
_
6x
-.
,
1,15
'~'
I
I
I
II max
II
~O,32
:1
~
~
'i_[1gj_i'
,
I~I--=--I~I
. . . - - - 9,5
8,3
max
----+-
112max tll
+1 1+
top view
a-PIN CERDIP (SOT-151A)
!-
10,lI.max
_I
-t
5,08
_'0,0_
7,6
top view
POOt47OS
•
February 1987
15-53
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCD, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TDA, TOO, TEA
Package Outlines
a-PIN METAL CERDIP (SOT-153B)
PQOl030S
9-PIN PLASTIC SIP (SOT-110B)
~21
I~"
I
'~s",,~~~E
~ -~ \.Y
,
'
~~~~~~~~~~nr1-.,
,
m,"
,
".76(2)
t
t:;-
\ "p ....
T~"'-=--"',=·====p=====~i
1.-'._ _ _ _
February 1987
22mQx _.
..I
15-54
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCO, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TOA, TOO, TEA
Package Outlines
9-PIN PLASTIC POWER SIP (SOT-131A, B)
~
0[,0_:
.
1_
_1
I
2 •0 I..
9-PIN PLASTIC SIP (SOT-142)
1-'- - - - - 2 1 - - - - - 1_ , _
=~",b~='==i=='=='=='===k==i1---.~~x t
I
Ii'"'
I
,
12
,
-
',!
'
I
,ax i
,
~
. . . I..
~~~
I
I
;~I
I
I _ i _ ,_ _ ,_______:_"
m~x-I11,20
6,35
,
_ '-O,l.
.. 1,65"
top vIew
, _ -_ _ _ 22mox
.-
II
February 1987
15-55
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCO, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TOA, TOO, TEA
Package Outlines
9-PIN PLASTIC POWER SIP-BENT-TO-DIP (SOT-157B)
' - - - - 2 4 , 4 " , , 0 ) < -_ _ _ ,
,------19,8 - - - - - ,
-=~"t'"'-I
bas.
-315
-j
12,4
T
~
lTT
"
T
I
""
.'
,
.;"Y
, -'--i-;':-- -i_I_~
.
ImiJ.
i..
·1'·'
,
1
.1,1, 0,4
I
t.. ~._:_
1
,
.I, I_
4.3- ..;
..I
PQOl07OS
12-PIN PLASTIC DIP WITH METAL COOLING FIN (SOT-150)
22mQ(-~1
4,7
"'''
I
_____ 17,, _ _ _ 1
16,9
top
February 1987
VI~W
15-56
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCO, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TOA, TOO, TEA
Package Outlines
13-PIN PLASTIC POWER SIP-BENT-TO-DIP (SOT-141B)
?'.'~o.oo"".j
005 •
.
,
~J':5::~;
I.
)
Z
"
,
17.5
10,0
,
...
14-PIN PLASTIC DIP (SOT-27K, M,
•
Ii,
1...3
8.2Smc:.: -
-I
-=-=....--.==r-1=--=---=---='
..
...
;?x
I=';,.-!
... 1
--!0.51
I
_ ':-0.32
~.
~
....
n
1-----t9.smax ,_.
3,OS
~
II
I
"
max
U
[ill]
'0
8,3
top
v;~w
•
February 1987
15-57
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCO, PCF, PNA,
SM, SAB, SAF, TBA, TCA, TOA, TOO, TEA
Package Outlines
14-PIN CERDIP (SOT-73A, B, C)
- - - - - 19,94mex - - - - - _
-8,25
--I
1±:::r:;C::::::;=;:=:;=;::::::;~=:;=-=-::::;:-=-=-::::;=~:::j
~~~
. .
meX~1
side view
'
K
:
:
,0,32
1,1 0,23
~
I,:'
1,1
,l_l?8_f ,
_ _ _ 10,0 _ __
7,6
14-PIN METAL CERDIP (SOT-S3B)
1------
19,25 max
.. ig:~g
"
Ij
~~;;- [lliJ_1
top view
February 1987
15-58
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCO, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TOA, TOO, TEA
Package Outlines
16-PIN PLASTIC DIP (SOT-38)
1 - 8.25max - - ;
,
I
--I
c
o
a.i
~.
4.7
m,,,
~I
:li
'0.51 ;
lm.rn_1
.0.76 l21
:-
[@
..,i
9.S
B.3
top
View
16-PIN PLASTIC DIP (SOT-38A)
22max-----_
!i
i~
'-,3.9
3.4
top view
•
February 1987
15-59
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCO, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TOA, TOO, TEA
Package Outlines
16·PIN PLASTIC DIP (SOT·3aD, DE)
~-----19.5mQx
------,
I
I
_
r 0,32
:( max
1,1
!-I71ll-!
:_10
_ _,
8,3
lead t indication /t'ither index or sign)
16·PIN PLASTIC DIP (SOT-3aZ)
, - - - - - - 19,5mall;----_"
~:
~I
g'i
r:;~x
.;;.
~,I
'0.51 I
~mjn ,
"to,76 m
I
I
... I 0,32
:( max
:
!-171ll-1,
1 -
February 1987
15·60
1,1
10
8•3 -
Slgnetics Linear Products
For Prefixes HEF, OM, MEA, PCD, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TDA, TDD, TEA
Package Outlines
16-PIN PLASTIC DIP WITH INTERNAL HEAT SPREADER (SOT-38WE-2)
_ - - - - 2 2 m Q I t - -_ __
I
I
,
I
. :_ _ [ill1 _ _~i
1_-9$-_
'.3
16-PIN PLASTIC QIP (SOT-58)
------22mcx - - - - - - ,
I
i_~_
---~_-- ....I
•
February 1987
15-61
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCD, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TDA, TDD, TEA
Package Outlines
16-PIN CERDIP (SOT-74A, B, C)
- - - - - - 19,94max - - - - - -
--I
tb=-=::n=n:~::::;::-:::r~:::;=;~n::=f=j::j
~~~
-s.25,max_/
:
~
;
Iji
~
:~
'fi,:..O,32
II
0,23
l,f
, ),1
.
l-l?El_J ,
_ _ _ 10,0 _ __
7,6
top view
16-PIN METAL CERDIP (SOT-84B)
.
'-----19,2SmOIr.----_
IIT
top vIew
February 1987
15-62
.
Side view
/
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCD, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TDA, TDD, TEA
Package Outlines
18-PIN METAL CERDIP (SOT-8S8)
23,4mcx - - - - - _
side view
I
-
.l....O.30
II 0,20
II
I
",;!rr!o-,_~_l
top view
18-PIN PLASTIC DIP (SOT-102A)
, - - - - - - - 23,5 max - - - - - - _
top view
(4 )
•
February 1987
15-63
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCD, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TDA, TOO, TEA
Package Outlines
18-PIN PLASTIC DIP (SOT-102C)
22mOl!
----_
-8,2S·"''':l
~
1
ij
_
0,32
sicte"iew
:
max
,
,
1_ _ 8.25 _ _ I
7,50
top yie-w
18-PIN PLASTIC DIP (SOT-102CS)
22mQx
----_
side view
I
I
- J- ~~~
"I
;-~--;'I
:~--
-top view
February 1987
15-64
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCD, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TDA, TOO, TEA
Package Outlines
18-PIN PLASTIC DIP (SOT-102G)
- - - - - - 25,4ma, - - - - - - _ 1
side view
I
I
I
II
:;
:1
or_[1;ID_i'
_9.5_
8,3
top view
18-PIN CERDIP (SOT-133A, 8)
23,6ma)(
------_1 ___
t
5.08
ma,
lo,38 I
,
- r min ,
. .:..1 076'"
'
1 '-1 . .
- a.2sma
side view
;
l:
~'
1
032
:1 0:23
f
II
:J
~
u
1--
i ---i
1 ,
7,62
,_ _ _ 10,0 _ __
7,6
II
February 1987
15-65
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCO, PCF, PNA,
SM, SAB, SAF, TBA, TCA, TOA, TOO, TEA
Package Outlines
20-PIN PLASTIC DIP (SOT-146)
21mox - - - - - - - . ,
side view
top view
20-PIN CERDIP (SOT-152B, C)
ro-------11
~
25,4max--------
~--------------------~---t
5,08
max
. ! ~?~ j
t
3,4
2,9
I
0,51
1,27_
max
February 1987
~3076121
t'
: o,~: -1~_$_~IO-,2-54~®""'I'"
15-66
side view
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCD, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TDA, TOO, TEA
Package Outlines
20·PIN METAL CERDIP (SOT·1548)
.
c
o
0.
- - 2S,8mQx
1_
I
-------
II
7.57 max _.--,
'
I
side view
L-.'
+
_
3,9
3,4
!-O,30
0.20
LI
,•
.-:-~--,
7C'i mollC
top view
20·PIN PLASTIC DIP (SOT·116)
-,= ___
'~:::'
,I.
t: _=_1i
I
I_ _
side view'
rw:;&l_r"
"
11,11
•
February 1987
15-67
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCO, PCF, PNA,
SM, SAB, SAF, TBA, TCA, TOA, TOO, TEA
Package Outlines
22-PIN METAL CERDIP (SOT-11S8)
. - - - - - - - - - 28,omax - - - - - - - _
side view
top view
r·_·_·-
1~·i2lF~·~~·
P001310S
22-PIN CERDIP (SOT-134A)
. - - - - - - - - - - 2 7 . 9 4 m a x - - - - - -_ _
side view
top view
FOO'' ' '
February 1987
15-68
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCD, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TDA, TDD, TEA
Package Outlines
24-PIN METAL CERDIP (SOT-86A)
,_~~~~~-
3I.00ma1~~~~-~
__
12.S0mr::.~_
. [ill)
-
24-PIN CERDIP (SOT-94)
,.-~~~~~~- "m~-~~~~
__-.
,_ _ _
1S.9mQx~
__
..
February 19B7
15-69
Signetics Uneer Products
For Prefixes HEF, OM, MEA, PCD, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TDA, TOO, TEA
Package Outlines
24-PIN PLASTIC DIP WITH INTERNAL HEAT SPREADER (SOT-101A, B)
~--------------i2_.--------------
__,
.----t5.lm.1 - - - . .
f;=='4.1maX-
I
',1
....
side view
,~-----+------~
,
I~
to
0.32
trial
' - - - (imJ----..J
,______ ----_I
~~~~
(4)
""""50S
28-PIN METAL CERDIP (SOT-87A)
top view
February 1987
15-70
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCD, PCF, PNA,
SM, SAB, SAF, TBA, TCA, TDA, TOO, TEA
Package Outlines
.
'
·
.
·
A
28-PIN METAL CERDIP (SOT-87B)
_ _ O,lO
I
0.20
I
(~~--_I
[" " " "r "" , " 'I
r, LJ
18
17
16
15
11
12
13
1t.
top
~i.w
28-PIN PLASTIC DIP (SOT-117)
- - - - - - - - 35m•• - - - - -_ __
sid. vi.w
, - - - ~J:~~ - - -
(4 )
II
February 1987
15-71
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCO, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TOA, TOO, TEA
Package Outlines
28·PIN PLASTIC DIP (SOT·117D)
_ -_ _
1_ _ _ _
~---..I
:~:~i
____ I
28·PIN CERDIP (SOT·135A)
38,lmo.x - -_ _ _ _ _ _ _---,
,~--
February 1987
15·72
lliJg - - - ----,
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCO, PCF, PNA,
SM, SAB, SAF, TBA, TCA, TOA, TOO, TEA
Package Outlines
40-PIN METAL CERDIP (SOT-aa)
r - - - - - - - - - - - - - - "_>Omo_-----------_,
40-PIN METAL CERDIP (SOT-aaB)
JJ~I'k -~
~-g:lg
i
j
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______
t
-
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.
.
.
0.51 038.
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n
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u
un"
t
-
111
-
-
I_--~--_I
~
1 - - - - - - - - - - - I-
13
14
15
16
17
18
19
20
II
February 1987
15-73
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCD, PCF, PNA,
SM, SAB, SAF, TBA, TCA, TDA, TDD, TEA
Package Outlines
40-PIN PLASTIC DIP (SOT-129)
, _ _ 'S,8mo.
-~,
.~'--------r--"
1~\ __
~;"
:
'
fImI
11,15
lS.g0
(4)
40-PIN CERDIP (SOT-145)
,_ _ _ _ _ _ _ _ 52,Sme ll
1~1
fl ~
...
- - - - - - - -
·~T,·
2,'j
......
,
Lf-.
.
_I~~.I-
February 1987
I~
L-._.--lL-L_ _- ' ""
0,32
II 0,23
~
!~~--~ ~-_1 I
--_._- ---
15·74
!:
~~:~~ ----~I
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCD, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TOA, TOO, TEA
Package Outlines
8-PIN PLASTIC SO (0 PACKAGE) (50-8, SOT-96A)
NOTES:
o® .10 (.004)
1. Package dimensions conform to JEOEC specification
MS-012-M for standard small outline (SO) package, B
leads, 3.75mm (.150") body width (issue A, June 1985),
2. Controlling dimensions are in mm. Inch dimensions in
parentheses.
3. Dimensions and tolerancing per ANSI Y14.SM-1982.
4. "T" I "0" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .15mm (.006") on
any side.
5. Pin numbers start with pin #1 and continue
counterclockwise to pin #8 when viewed from top.
6. Signetics ordering code for a product packaged In a
plastic small outline (SO) package is the suffix 0 after
the product number.
I
4.00 (.157)
3.80 (.150)
.236:t .006
m
I
- + - - - + 1 . 2 7 (.050)
esc
r
I
[iJ
1¢l.10 (.004)
~
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,.1 Tie lo@1
8'
..L~~
(.061< .008)
l . 4 9 (.019)
.35 (.014)
.50 (.020) ><45'
.25 (.010)
.25 (.010) IQI
I
I
.25 (.010)
(.007< .003)
.19 (.OOn
TeQ;]i7
853-0174 88070
P000273S
8-PIN PLASTIC SO (VSO-8, SOT-176)
_".0
_
1
1
7,6max-1
mm
1 - 9 I J max
~
105'
0:35t~
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- 0:49:
0,36:
2.35 2,7
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top view
-1-'-,
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max
I
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February 1987
15-75
•
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCO, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TOA, TOO, TEA
Package Outlines
14-PIN PLASTIC SO (0 PACKAGE) (SO-14, SOT-108A)
NOTES:
1. Package dimensions conform to JEDEC specification
MS-OI2·AB for S1anda'" small oullin. (SO) packag., 14
loads, 3.75mm (.ISO") body width 0_. A. Jun. 1985).
2. Controlling dimensions are In mm. Inch dimensions in
O@ .10 (.004)
parentheses.
3. Dimensions and tolerancing per ANSI Y14.SM-1982.
4 "T" "0" and "E" are reference datums on the molded
. bo~ and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .1Smrn (.006") on
any side,
S. Pin numbers start with pin # 1 and continue
counterclockwise to pin #14 when viewed from top.
6. Signetics ordering code for a product packaged In a
plastic small DutOne (SO) package Is the suffix Dafter
the product number.
(.238 • .ooe)
~
r
1-JE:~
(.DB1 • .ooe)
m
_.50_(.0_20_) x45"
.25 (.010)
~
I
101.10 (.004) 1
.48 (.019)
.35 (.014)
-ffl T 1E lo@1 .25 (.010) @ 1
.25 (.010)
.19 (.007)
8"
(.D25 • .ooe)
.635 :t.15
853-0175 88068
16-PIN PLASTIC SO (0 PACKAGE) (SO-16, SOT-109A)
~O@I.l0
(.004)
~
NOTES:
1. Package dimensions conform to JEDEC specifICation
MS-012-AC for standard small outline (SO) package, 16
leads, 3.75mm (.150") body width (issue A. June 1985).
2. Controlling dimensions are in mm. Inch dimensions in
parentheses.
3. Oimensions and tolerancing per ANSI Y14.5M-1982.
4. "T', "0" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .15mm (.006") on
any side.
5. Pin numbers start with pin #1 and continue
counterclockwise to pin #1 e when viewed from top.
6. Signetics ordering code for a product packaged in a
plastic small ouUine (SO) package Is the suffix 0 after
the product number.
1----'-1
(.236 • .ooe)
---r.Jr
lfIE@I.25 (.010) @ I
•SO (.D20) x45"
r . 2 5 (.010)
.10 (.004)
L~
.35 (.014)
L-~~~8'
-ffITIElo@I.25
(§Offi
I
.25 (.010)
.19 (.007)
(.oo7 • .D03)
.180 • .07
853-0005 88069
February 1987
15-76
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCO, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TOA, TOO, TEA
Package Outlines
16-PIN PLASTIC SOL (0 PACKAGE) (SOL-16, SOT-162A)
r O ® I . , 0 (.004)
~
NOTES:
1. Package dimensions conform to JEDEC specification
M5-013·AA for standard small outline (SO) package, 16
leads. 7.50mm (.300") body width
~
~ssue
A, June 1985).
2. Controlling dimensions are in mm. Inch dimensions in
parentheses.
3. Dimensions and tolerancing per ANSI Y14.SM-1982.
4
"r'
"0" and "E" are reference datums on the molded
. body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .15mm (.006") on
any side.
10.65 (.419)
10.26 (.404)
5. Pin numbers start with pin #1 and continue
counterclockwise to pin #16 when viewed from top.
6. Signetics ordering code for a product packaged in a
plastic small outline (SO) package is the suffix Dafter
the product number.
j-tle®I.25 (.010) ® I
l
~~----~------ ;~~t;~::
f
r
~X45'
.50 (.020)
~
2.65 (.104)
2.35 (.093)
I
.32 (.013)
.23 (.009)
.49 (.019) -1.IT 1 eI0®1.25 (.010)@1
.35 (.014)
.30 (.012)
.10 (.004)
853-0171 81218
20-PIN PLASTIC SOL (0 PACKAGE) (SOL-20, SOT-163A)
1+10®I.l0 (.004) I
I
NOTES:
7.50 (.299)
7.40 (.291)
10.28 (.404)
1
!+!E®! .25 (.010) ®
m
I
U,.27
-0-
(.050)
1
1. Package dimensions confonn to JEDEC specification
MS-013·AC for standard small outline (SO) package, 20
leads, 7.50mm (.300") body width Qssue A, June 1985}.
2. Controlling dimensions are in mm. Inch dimensions in
parentheses.
3. Dimensions and tolerancing per ANSI Y14.5M- 1982.
4. "r', "0" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .15mm (.006") on
any side.
5. Pin numbers start with pin #1 and continue
counterclockwise to pin #20 when viewed from top.
6. Signetics ordering code for a product packaged In a
plastic small outline (SO) package is the suffix 0 after
the product number.
esc
13.00 (.512)
12.50 (.496)
.75 (.030) X45'
.50 (.020)
I
2.65 (.104)
2.35 (.093)
.32 (.013)
.23 (.009)
.,.ITI eio@I.25(.010)@ 1
853-0172 82949
February 1987
15-77
~
.10 (.004)
1.07 (.042)
.86 (.034)
•
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCD, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TDA, TDD, TEA
Package Outlines
24-PIN PLASTIC SOL (D PACKAGE) (SOL-24, SOT-137A)
NOTES,
1. Package dimensions conform to JEDEC specification
MS-013-AD for standard small outline (SO) package, 24
leads, 7,50mm {.300' 'J body width (issue A, June 1985).
2. Controlling dimensions are in mm. Inch dimensions in
parentheses.
3. Dimensions and tolsrancing per ANSI Y14.5M-1982.
4. lOT", "D" and "En are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .1Smm (.006") on
any side.
5. Pin numbers start with pin # 1 and continue
11
I
10.65 (.419)
7.60 (.299)
counterclockwise to pin #24 when viewed from top.
6. Signetics ordering code for a product packaged in a
plastic small outline (SO) package is the suffix 0 atter
the product number.
10.26 (.404)
7.40 (.291)
Ehj
!tIE ®1.25 (.010) ® I
lr
15.60 (.614)
15.20 (.598)
.75 (.030) X45°
.50 (.020)
~
I
!?I
.10 (.004)
I
---l
I
L:::
2.65 (.104)
2.35 (.093)
\
~:~::: -1+1 TIE 10 ®I .25 (.010) @
.32 (.013)
.23 (.009)
I
.30 (.012)
.10 (.004)
1.07 (.042)
.86 (.034)
853·0173 82949
28-PIN PLASTIC SOL (D PACKAGE) (SOL-28, SOT-136A)
NOTES,
lijiID®I.lo (.004) I
1. Package dimensions conform to JEDEC specification
MS·013·AE for standard small outline (SO) package, 28
leads, 7.50mm (.300") body width (issue A. June 1985).
2. Controlling dimensions are in mm. Inch dimensions in
parentheses.
3. Dimensions and tOlerancing per ANSI Y14.5M·1982.
4. "T", "D" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .15mm (.006") on
any side.
5. Pin numbers start with pin # 1 and continue
counterclockwise to pin #28 when viewed from top.
6. Signetics ordering code for a product packaged in a
plastic small outline (SO) package is the suffix Dafter
the product number.
Ul.27 (.050)
r·
esc
-O-~----r-------------
18.10 (.713)
17.70 (.697)
75 (.030) X45 0
.50 (.020)
t
lCl·l0 (.004)
I
-I
1
2.65 (.104)
2.35 (.093)
!
L
.49 (.019) #1 TIE ID ®I .25 (.010)
.35 (.014)
IB I
.32 (.013)
.23 (.009)
853-0006 81217
February 1987
~~'------' ;>"1-=~
I
15-78
.30 (.012)
.10 (.004)
1.07 (.042)
.86 (.034)
Signetics Linear Products
For Prefixes HEF, OM, MEA, PCD, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TDA, TDD, TEA
Package Outlines
40-PIN PLASTIC SO (VSO-40, SOT-158A)
-I
1 - - 9,Oma,
•
24
--I
mex 1--7,omox--r
n?~:LJ ~
T
;-I""t
__ 1,71_
t
1,5
O.~ 5
min
,
0,221
0,15,
- - - 12,3 max ______ 1
top view
- - - 16,0
mQX _ _ _
I
40-PIN PLASTIC SO (OPPOSITE BENT LEADS) (VSO-40, SOT-158B)
1
-~i~l-
ls,5ma'_1
L.,.~.
.
'.
1 05
0:35 -
t
.
• •
..;:=--'
I I" 2,35 2,7
1,1
042
~46 ;cx
max max
-t-t
-::J -1"'101
"', rwl
0:32'
I'Y
- ~:~I---12,3max,---
~
~
..... .
'0
~-I
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:!
mov)(
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(
I
IWUIill~'
1_ _-
16,0 max - - _
I
February 19B7
15-79
Signetics
Section 16
Sales Offices
Linear Products
INDEX
Sales Office Listing..................................................................................
16-3
III
Signetics Unear Products
Sales Offices
SIGNETICS
HEADQUARTERS
811 East Arques Avenue
P.O. Box 3409
Sunnyvale,
California 94088-3409
Phone: (408) 991-2000
ALABAMA
Huntsville
Phone: (205) 830-4001
ARIZONA
Phoenix
Phone: (602) 265-4444
CALIFORNIA
Canoga Park
Phone: (818) 340-1431
Irvine
Phone: (714) 833-8980
(213) 588-3281
Los Angeles
Phone: (213) 670-1101
San Diego
Phone: (619) 560-0242
Sunnyvale
Phone: (408) 991-3737
COLORADO
Aurora
Phone: (303) 751-5011
FLORIDA
Clearwater
Phone: (813) 796-7086
Ft. Lauderdale
Phone: (305) 486-6300
GEORGIA
Atlanta
Phone: (404) 953-0067
ILLINOIS
Itasca
Phone: (312) 250-0050
INDIANA
Kokomo
Phone: (317) 453-6462
KANSAS
Overland Park
Phone: (913) 469-4005
MASSACHUSETTS
Littleton
Phone: (617) 486-8411
MICHIGAN
Farmington Hills
Phone: (313) 476-1610
MINNESOTA
Edina
Phone: (612) 835-7455
February 1987
NEW JERSEY
Parsippany
Phone: (201) 334-4405
NEW YORK
Hauppauge
Phone: (516) 348-7877
Wappingers Falls
Phone: (914) 297-4074
NORTH CAROLINA
Cary
Phone: (919) 481-0400
OHIO
Worthington
Phone: (614) 888-7143
OREGON
Portland
Phone: (503) 297-5592
PENNSYLVANIA
Plymouth Meeting
Phone: (215) 825-4404
TENNESSEE
Greeneville
Phone: (615) 639-0251
TEXAS
Austin
Phone: (512) 339-9944
Richardson
Phone: (214) 644-3500
CANADA
SIGNETICS CANADA, LTD.
Etoblcoke, Ontario
Phone; (416) 626-6676
Nepean, Ontario
Signetics, Canada, Ltd.
Phone: (613) 726·9576
REPRESENTATIVES
ARIZONA
Scottsdale
Thorn Luke Sales, Inc.
Phone: (602) 941-1901
CALIFORNIA
Santa Clara
Magna Sales
Phone: (408) 727-8753
CONNECTICUT
Brookfield
M & M Associates
Phone: (203) 775-6888
FLORIDA
Clearwater
Sigma Technical Associates
Phone: (813) 791-0271
Ft. Lauderdale
Sigma Technical Associates
Phone: (305) 731-5995
ILLINOIS
Hoffman Estates
Micro-Tex, Inc.
Phone: (312) 382-3001
INDIANA
Indianapolis
Mohrlield Marketing Inc.
Phone: (317) 546-6969
IOWA
Cedar Rapids
J.R. Sales
Phone: (319) 393-2232
MARYLAND
Glen Burnie
Third Wave Solutions, Inc.
Phone: (301) 787-0220
MASSACHUSETTS
Needham Heights
Com-Sales, Inc.
Phone: (617) 444-8071
Kanan Associates
Phone: (617) 449-7400
MICHIGAN
Bloomfield Hills
Enco Marketing
Phone: (313) 642-0203
MINNESOTA
Eden Prairie
High Technology Sales
Phone: (612) 944-7274
MISSOURI
Bridgeton
Centech. Inc.
Phone: (314) 291·4230
Raytown
Centech, Inc.
Phone: (816) 358-8100
NEW JERSEY
East Hanover
Emtec Sales, Inc.
Phone: (201) 428-0600
NEW MEXICO
Albuquerque
F.P. Sales
Phone: (505) 345-5553
NEW YORK
Ithaca
Bob Dean, Inc.
Phone: (607) 257-1111
OHIO
Cleveland
Covert & Newman
Phone: (216) 663-3331
Dayton
Covert & Newman
Phone: (513) 439-5788
Worthington
Covert & Newman
Phone: (614) 888-2442
16-3
OKLAHOMA
Tulsa
Jerry Robinson and
Associates
Phone: (918) 665-3562
OREGON
Hillsboro
Western Technical Sales
Phone: (503) 640-4621
PENNSYLVANIA
Pittsburgh
Covert &. Newman
Phone: (412) 531-2002
Willow Grove
Delta Technical Sales Inc.
Phone: (215) 657-7250
UTAH
Salt Lake City
Electrodyne
Phone: (801) 486-3801
WASHINGTON
Bellevue
Western Technical Sales
Phone: (206) 641-3900
Spokane
Western Technical Sales
Phone: (509) 922-7600
WISCONSIN
Waukesha
Micro-Tex, Inc.
Phone: (414) 542-5352
CANADA
Burnaby, British Columbia
Tech·Trek, Ltd.
Phone: (604) 439-1367
Mississauga, Ontario
Tech-Trek, Ltd.
Phone: (416) 238·0366
Nepean, Ontario
Tech-Trek, Ltd.
Phone: (613) 726-9562
Richmond, British Columbia
Tech-Trek, Ltd.
Phone: (604) 271-3149
Ville St. Laurent, Quebec
Tech-Trek, Ltd.
Phone: (514) 337-7540
II
Signetics Linear Products
Sales Offices
DISTRIBUTORS
Contact one of our
local distributors:
Anthem Electronics
Arrow Electronics
Avnet Electronics
Hamiltonl Avnet Electronics
Lionex Corporation
Schweber Electronics
Summit Distributors
Quality Components
Wyle LEMG
Zentronics, Ltd.
FOR SIGNETICS
PRODUCTS
WORLDWIDE:
ARGENTINA
Philips Argentina S.A.
Buenos Aires
Phone: 54-1·541-7141
AUSTRALIA
Philips Electronic
Components and Materials,
Ltd.
Artarmon, N.S.w.
Phone: 61-2-439-3322
AUSTRIA
Osterrlchlsche Philips
Bauelemente
Wien
Phone: 43-222-62-91-11
BELGIUM
N.V. Philips & MBLE
Bruxelles
Phone: 32-2-5-23-00-00
BRAZIL
Philips Do Brasil, Ltda.
Sao Paulo
Phone: 55-11-211-2600
CHILE
Philips Chilena S.A.
Santiago
Phone: 56-02-077-3816
COLOMBIA
Iprelenso, Ltda.
Bogota
Phone: 57-1-2497624
DENMARK
Mlnlwatt AlS
Copenhagen S
Phone: 45-1-54·11·33
FINLAND
Oy Philips Ab
Helsinki
Phone: 358·0·172-71
FRANCE
R.T.C. La RadlotechnlqueCompelec
Paris
Phone: 33·1·43·38·80·00
GERMANY
Valvo
Hamburg
Phone: 49·40·3·296·1
GREECE
Philips Hellenlque S.A.
Athens
Phone: 30-1-9-21-5111
HONG KONG
Philips Hong Kong, Ltd.
Kwai Chung
Phone: 852-0-245-121
INDIA
Peico Electronics & Elect.
Ltd.
Bombay
Phone: 91-22.493·8721
INDONESIA
P.T. Phllips-Ralln Electronics
Jakarta Selatan
Phone: 62-21-512-572
IRELAND
Philips Electrical Ltd.
Dublin
Phone: 353-1-69-33-55
ISRAEL
Rapac Electronics, Ltd.
Tel Aviv
Phone: 972-3-477115
ITALY
Philips S.p.A.
Milano
Phone: 39-2-67-52-1
JAPAN
Nikon Philips Corp.
Tokyo
Phone: 81·3·448·5617
Signetics Japan Ltd.
Phone: 81·3·230·1521/2
KOREA
Philips Industries, Ltd.
Seoul
Phone: 82-2·794-5011/2/3
14/5
MEXICO
Electronica S.A. de C.V.
Toluca
Phone: (721) 613·00
NETHERLANDS
Philips Nederland B.V.
Eindhoven
Phone: 31-40·793·333
NEW ZEALAND
Philips New Zealand Ltd.
Auckland
Phone: 64-9-605914
NORWAY
Norsk AlS Philips
Oslo
Phone: 47·2·68·02·00
PERU
Cadesa
Lima
Phone: 51-14-319253
PHILIPPINES
Philips Industrial Dev., Inc.
Makati
Phone: 63-2-868951-9
SWEDEN
Philips Komponenter A.B.
Stockholm
Phone: 46·8·782·10·00
SWITZERLAND
Philips A.G.
Zurich
Phone: 41-1·488·2211
TAIWAN
Philips Taiwan, Ltd.
Taipei
Phone: 886-2·712·0500
THAILAND
Philips Electrical Co.
of Thailand Ltd.
Bangkok
Phone: 66-2·233·6330-9
TURKEY
Turk Philips
Tlcaret A.S.
Istanbul
Phone: 90-11-43-59-10
UNITED KINGDOM
Mullard, Ltd.
London
Phone: 44-1-580-6633
UNITED STATES
Signetlcs International Corp.
Sunnyvale, California
Phone: (408) 991-2000
PORTUGAL
Philips Portuguesa SARL
Lisbon
Phone: 351-1-65-71-85
URUGUAY
Luzilectron, S.A.
Montevideo
Phone: 598-91-56·41/42
143/44
SINGAPORE
Philips Project Dev. Pte., Ltd.
Singapore
Phone: 65-350-2000
VENEZUELA
Magnetica, S.A.
Caracas
Phone: 58-2-241-7509
SOUTH AFRICA
E.D.A.C. (PTY), Ltd.
Joubert Park
Phone: 27-11-402-4600
Effective 4-14-87
February 1987
SPAIN
Mlniwatt S.A.
Barcelona
Phone: 34·3·301·63·12
16-4
Signetics
a subsidiary of U.S. Philips Corporation
Signelics Corporation
811 E. Arques Avenue
PO. Box 3409
Sunnyvale, California 94088-3409
Telephone 408 1991-2000
©
98-2000-060
Copyright 1987 Signetics Corporation
Printed in USA6132/ RRD / 40MFP0487
880 pages
Source Exif Data:
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