1987_Single Chip_8_Bit_Microcomputers_Vol_2 1987 Single Chip 8 Bit Microcomputers Vol 2
User Manual: 1987_Single-Chip_8_Bit_Microcomputers_Vol_2
Open the PDF directly: View PDF 
.
Page Count: 82
| Download | |
| Open PDF In Browser | View PDF |
,
MITSUBISHI 'l1IolC01C?J
SEMICONDUCTORS UC!Jl!J U
SINGLE-CHIP B-BIT
MICROCOMPUTERS Vol.2
o
~
y
o
A
•
MITSUBISHI
1'& ELECTRIC
All values shown in this catalogue are subject to change for product improvement.
The information, diagrams and all other data included herein
are believed to be correct and refiable. However, no responsibility is assumed by Mitsubishi Electric Corporation for their use, nor
for any infringements of patents or other rights belonging to third
parties which may result from their use.
I
I
I
MITSUBISHI MICROCOMPUTERS
DEVELOPMENT SUPPORT SYSTEMS
Development Support Systems
Debugging machine
EValuation boards
Host machme
Mam unit
Type
with EPROM
Option board
M5M80C49A-XXXP
M5M80C49H-XXXP
I
PCA8403
I
-
M5M80C39AP
e----8-bit
CMOS
M5M80C39HP
-
M5MC49A-XXXFP
-
M5MC49H-XXXFP
-
M5L8048-XXXP
Series
MELP.S
8-48
I
PC4000
M5L8049-XXXP
M5L8049-XXXP-6
PCA8400
[
-
1-4
I
-
M5M8050H-XXXP
Series
MELPS
8-41
PCA8403
-
M5L8039P-6
8-bit
NMOS
I
-
M5L8035LP
M5L8039P-11
PCA8403
t
PCA8403
M5M8040HP
-
M5L8049H1-XXXP
-
M5L8039HLP-14
-
M5L8041A-XXXP
-
-
-
M5L8041AH-XXXP
-
-
-
M5L8042-XXXP
-
-
-
• MITSUBISHI
;""ELECTRIC
t
MITSUBISHI MICROCOMPUTERS
PACKAGE OUTLINES
TYPE 24P2W
24-PIN MOLDED PLASTIC FLAT
Dimension
In
mm
ffy
o
o
N
d
.,.+1
.;
J1.0.4~0.1
1. 27±0. 2
-
d
+1
N
-
00
dd
+1
'"
d
TYPE 24P4
.... '"
0.S±0.2
d
+1
ex>
'"
~____~11~.9_3±_0_._3____~~ d
24-PIN MOLDED PLASTIC DIP
Dimension In mm
311:+:n
~~~~~I
~]
15 24±0 3
--gj
5 5MAX
o
5MIN
o 27+ 0
2 8MIN
07
-0 05
o 5±0. 1
2 54±0 25
1-6
12:+:~: ~
15 2-17
•
MITSUBISHI
~ELECTRIC
MITSUBISHI MICROCOMPUTERS
PACKAGE OUTLINES
TYPE 52P4B
52-PIN MOLDED PLASTIC DIP (LEAD PITCH 1.778mm)
Dimension in mm
15.24±O.3
1
1. 778±O.25
1-8
I..
• MITSUBISHI
.;.. ELECTRIC
I
15.2~17
..
I
MITSUBISHI MICROCOMPUTERS
LETTER SYMBOLS FOR THE DYNAMIC PARAMETERS
b) those that are characteristics of the memory.
The letter symbols so far proposed for memory circuits
are listed in sub-clauses 3.1 and 3.2 below.
All subscripts A should be in lower-case.
3.1. Timing Requirements
The letter symbols for the timing requirements of semiconductor memories are as follows:
Term
Cycle time
Time interval between two signal events
Fall time
Hold time
Precharging time
Rise time
Recovery time
Refresh time interval
Setup time
Transition time
Pulse duration (width)
Subscript
c
d
Note
3 If the same termInal, or signal. can be used for two functIons (for example
Data mput/output, ReadIWntel the waveform should be labelled with the
dual function, If appropriate, but the symbols for the dynamic parameters
rec
rf
su
w
Subscript
a
dis,
en
p
rec
T
v
4. SUBSCRIPTS BAND D
(For Signal Name or Terminal Name)
The letter symbols for the signal name or the name of
the terminal are as given below.
All subscripts Band D should be in upper~case.
Address
Clock
Column address
Column address strobe
Data input
Data input/output
Chip enable
scnpt should not end with H, K, V. X, or Z (See clause 5)
pc
Recovery tIme for use as a characteristIc IS limited to sense recovery time
Signal or terminal
ample CAS, should not be used
It should be noted. when further letter symbols are chosen, that the sub-
The letter symbols for the dynamic characteristics of
semiconductor memories are as follows:
Access time
Disable time
Enable time
Propagation time
Recovery time
Transition time
Valid time
' Subscript
A
C
CA
CAS
D
DO
E
should Include only that part of the subSCript relevant to the parameter
5. SUBSCRIPTS C AND E
(For Transition of Signal)
The following symbols are used to represent the level or
state of a signal:
Transition of signal
Subscript
High logic level
Low logic level
Valid steady-state level (either low or high)
Unknown, changing, or 'don't care' level
High-impedance state of three-state output
H
L
V
X
Z
The direction of transition is expressed by two letters,
the direction being from the state represented by the
fi rst letter to that represented by the second letter, with
the letters being as given above.
When no misunderstanding can occur, the first letter
may be omitted to give an abbreviated symbol for subscripts C and E as indicated below.
All subscripts C and E should be in upper-case.
Subscript
Examples
Transition from high level to
low level
Transition from low level to
high level
Transition from unknown or
changing state to valid state
Transition from valid state to
unknown or changing state
.Transition from high-impedance
state to valid state
Note
Full Abbreviated
HL
L
!
LH
H
XV
V
VX
X
ZV
V
'Smce subSCripts 'C and E may be abbreviated, and since subSCripts Band 0
may contam an Indetermmate number of letters, It IS necessary to put the
restriction on the subSCripts 8 and 0 that they should not end with H. L.
V. X, or Z, so as to avoid possible confUSion
1-10
ER
G
PR
0
R
RA
RAS
RF
RI/J1
S
W
Note 1 In the letter symbols for time Intervals, bars over the subSCripts, for ex-
h
3.2. Characteristics
Characteristic
Erasure
Output enable
Program
Data output
Read
Row address
Row address strobe
Refresh
Read/Write
Chip select
Write (write enable)
•
MITSUBISHI
. . . . ELECTRIC
MITSUBISHI MICROCOMPUTERS
SYMBOLOGY
FOR DIGITAL INTEGRATED CIRCUITS
New symbol
Forrner symbol
Pa rameter -def I n Itlon
C,
Input capacitance
Co
Output capacitance
Clio
Input/output terminal capacitance
C , (¢)
Input capacitance of clock Input
f
Frequency
f (¢)
Clock frequency
I
Current-the current Into an Integrated ClrrtJlt terminal
Iss
Supply current from Vss
ISS(AV)
Average supply current from Vss
ICC
Supply current from Vee
ICC(AV)
Avarage supply current from Vee
ICC(Po)
Power-down supply current from Vee
100
Supply current from VOO
IDD(AV)
Average supply current from Voo
IGG
Supply current from VGG
IS
defined as a positive value and the current out of a terminal
IGG(AV)
Average supply current from VGG
I,
Input current
I'H
High-level Input current-the value of the Input current when VOH IS applied to the Input considered
I,L
Low-level Input current-the value of the Input current when VOL IS applied to the Input considered
10H
High-level output current-the value of the output current when VOH IS applied to the output considered
IS
defined as a negative value
IDL
Low-level output current-the value of the output current when VOL IS applied to the output conSidered
loz
Off-state (high-Impedance state) output current-the current Into an output having a three-state capability with Input condition so applied that
10ZH
Off-state (high-Impedance state) output current, with high-level voltage applied to the output
10ZL
Off-state (high-Impedance state) output current, with low-level voltage applied to the output
los
Short-circuit output current
It will establish according to the product specification, the off (high-Impedance) state at the output
Iss
Supply current from Vss
Pd
Power dlsslpatlOn
NEW
Number of erase/wrl te cycles
NAA
Number of read access unrefreshed
R,
Input reSistance
RL
External load resistance
ROFF
Off-state output resistance
RON
On-state output reSistance
Access time-the time Interval between the application of a specified Input pulse durtng a read cycle and the availability of valid data signal at an output
ta
ta (AD)
Addressaccesstlme-the time Interval between the application of an address Input pulse and the availability of valid data signals at an output
ta (E)
ta (CE)
Chip enable access time
ta(G)
ta (OE)
ta (A)
Co lumn address strobe access tl me
ta(CAS)
Output enable access time
Data access time after program
ta(PA)
Row address strobe access time
ta (AAS)
ta(cs)
Chip select access time
te
Cycle time
teA
te (AD)
Read cycle time-the time Interval between the start of a read cylce and the start of the next cycle
teAF
te(AEF)
Refresh cycle time-the time Interval between successive signals that are Intended to restore the level In a dynamic memory cell to Its original level
tePG
te(PG)
Page-mode cycle time
tCAMW
te(AMA)
Read-modify-wnte cycle time-the time Interval between the start of a cycle
ta (5)
In
which the memory IS read and new data IS entered, and the start of
the nex t cyc Ie
tew
1-12
te(WA)
Wrtte cycle time-the time Interval between the start of a wnte cycle and the start of the next cycle
•
MITSUBISHI
~ELECTRIC
MITSUBISHI MICROCOMPUTERS
SYMBOLOGY
Parameter~deflnltlon
New symbol
Former symbol
ISU(D)
Isu (DA)
Data-In setup time
Isu (D-E)
ISU(DA-CE)
Chip enable setup time before data-In
ISU(D-W)
ISU(DA-WR'
Write setup time before data-In
Isu (E)
Isu (CE)
Chip enable setup time
Isu (E-P)
Isu (CE-P)
Precharge setup time before chip enable
Isu (G-E)
Isu (OE-CE)
Chip enable setup time before output enable
Isu (P-E)
Isu (P'CE)
Chip enable setup time before precharge
Isu (RD)
Read setup time
Power-down setup time
ISU(PD)
Isu (R)
Isu (R-CAS) Isu (RA-CAS)
Column address strobe setup time before read
Isu (RA-CAS)
Column address strobe setup time before row address
Isu (S)
Isu (CS)
Chip select setup tlrne
Isu(S-W)
Isu (CS-WR)
Write setup time before chip select
Isu(w)
ISU(WR)
Write setup time
ITHL
High-level to low-level translt,on time }
lTLH
Low-Ievel- to high-level tranSition time
the time mterval between specified reference pOints on the edge of tf,e output pulse when the output IS
gOing to the low (hlghllevel and when a speCified Input signal IS applied through a speCified network and
the output IS loaded by another speCified network
Data valid time after address
IV(A)
Idv (AD)
IV(E)
Idv (CE)
Data valid time after chip enable
IV(E)PR
IV(CE)PR
Data valid time after chip enable In program mode
IV(G)
Iv (OE)
Data valid time after output enable
Data valid tl me after program
IV(PA)
Iv (S)
IV(CS)
Data valid time after chip select
Pulse width (pulse duration) the time Interval between specified reference pOints on the leading and training edges of the waveforms
Iw
IW(E)
IW(CE)
Chip enable pulse width
IW(EH)
IW(CEH)
Chip enable high pulse width
IW(EL)
IW(EL)
Chip enable low pulse width
Program pulse width
IW(PR)
IW(A)
IW(RD)
Read pulse width
IW(S)
tW(CS)
Chip select pulse width
Iw(W)
IW(WR)
Iw( ¢)
Wr!le pulse width
Clock pulse width
Ta
Ambient temperature
Topr
Operating temperature
Tstg
Storage temperature
VSS
VBB supply voltage
VCC
Vee supply voltage
VOD
VOO supply voltage
I,
VGG
VGG supply voltage
V,
Input voltage
VIH
High-level Input voltage-the value of the permitted high-state voltage at the Input
VIL
Low-level Input voltage-the value of the permitted low-state voltage at the Input
Vo
Output voltage
VOH
High-level output voltage-the value of the guaranteed high-state voltage range at the output
VOL
Low-level output voltage-the value of the guaranteed low-state voltage range at the output
VSS
Vss supply voltage
1-14
•
MITSUBISHI
..... ELECTRIC
,
MITSUBISHI SINGSE-CHIP 8-BIT MICROCOMPUTERS
.QUALITY ASSURANCE AND RELIABILITY TESTING
STAGE
DESIGN/
PRODUCTION
ENGINEERING
SALES
MARKET
1
QUALITY
ASSURANCE
MANUFACTURING
PRODUCTION
CONTROL
MARKET SURVEY)
1,---. " ' - - -___
zUJ
L.{
::;
Q.
STRATEGIC PRODUCT PLAN)
~
g
UJ
a;
(
)
DESIGN" DESicrN Roe-VIEW
E2
z
(!)
Cii
UJ
o
QUALIFICATION (1)
,
(
-f--
)
DECISION OF PRE-PRODUCTION
z
o
f=
u
(
::J
,0
PRE-PRODUCTION
QUALIFICATION (2)
UJO
a::
a::
Q.Q.
(
)
DECISION OF MASS PRODUCTION
~~~U(;TION
z
o
/"
f=
u
::J
o
oa::
Q.
c5
g:
+
)! r
MATERIAL
~~~~MING
I \.
KWAFFR FAB
UJ
~
gj~ KASSEMBLY
i3
,
U
a::
UJU
gj
«
8~
lJFINAL
'\
g:::i I\!NSPECTI0'V
,~
II' QUALITY
::!:O
I,ASSURANCE TEST
::;
~
? 'I?
Ir INVENTORY
SHIPPING
~
Q.
1"\
Iii::J RETUR~ED PRODUCT
U
FAILURE ANALYSiS/COrRECTIVE ACTION
::J
-
CIl
o~
j
Flg.1
1-16
~
~
<3
FAILURE ANALYSIS REPORT GENERATION
~
:5
j
I
-
:>
~
1~8~
o
z
«
Iz
UJ
UJ
b
a::
g:
0
\.. CONTROL
+(
0
0
;""". -C----LO-R-D-ER--L......
~
~
u
o
_--!'::--1------+------+--..J
>
UJ
.i ~
(INVENTORY)
::i
o
I-
~
g
,
UJ
U
~ ~ !z ~
!z ~ ~ j
~ ~ 8
0
~
QUALITY DATA/FAILURE ANALYSIS/QUALITY
IMPROVEMENT
>
a::
~
~
FLOW OF PRODUCT
----- FLOW OF INFORMATION
FLOW CHART OF QUALITY ASSURANCE SYSTEM
• MITSUBISHI
;"ELECTRIC
UJ
CIl
u
MITSUBISHI SINGSE-CHIP 8-BIT MICROCOMPUTERS
.QUALITY ASSURANCE AND RELIABILITY TESTING
:3
RELIABILITY TEST RESULTS
The reliability test results for Mitsubishi Single-chip 8-bit
Microcomputers are shown in Table 2, Table 3 and Table 4.
Table 2 shows the result of endurance tests of steady-state
operation life and high temperature storage life test for representative types of Single-chip 8-bit Microcomputers,
MELPS 740, MELPS 8-48, MELPS 8-41, and Peripheral
LSls. From Table 2, the combined failure rate of Mitsubishi
Table 2
Single-chip 8-bit Microcomputers is calculated 0.16%
/1000hours at 125"C ambient temperature operation.
Table 3 shows the result of environment test of temperature
cycling, high temperature/high humidity and pressure cooker test for the same type of products as of endurance tests.
Table 4 shows the results of mechanical tests for representative products of various package types.
ENDURANCE TEST RESULTS
Test
High Temperature
Operation Life
High Temperature
Storage Life
Low Temperature
Storage Life
Series
Type Number
Test Condition
Ta('C)
1084
36
132
48
480
48
120
48
48
36
36
84
1,816,000
36,000
180, 000
96, 000
732, 000
48,000
186,000
48,000
72,000
36,000
72,000
132,000
7
7
38
140
38, 000
280, 000
125
5.5
5.5
5.5
66
72
170
66, 000
72, 000
170, 000
M5L8041A-XXXP
M5L8042-XXX P
125
5.5
5.5
44
88
44, 000
88, 000
Peripheral
M5L8243P
M5M82C43P
125
5.5
5.5
44
66
44, 000
66, 000
MELPS 740
M50740-XXXSP
M50744-XXXSP
M50747-XXXSP
M50753-XXXFP
M50754-XXXSP
M50931-XXXFP
M50943-XXXFP
M50734SP
150
-
448
120
360
32
60
32
22
48
448, 000
120, 000
720, 000
32, 000
60,000
32, 000
22, 000
48, 000
M50747ES
M50747E-XXXSP
250
175
-
44
66
44, 000
66, 000
MELPS 8-48
M5L8049-XXXP
M5L8050H-XXX P
M5M80C49-XXXP
150
-
66
66
88
66, 000
66,000
88, 000
MELPS 8-41
M5L8041A-XXXP
M5L8042-XXXP
150
-
44
88
44, 000
88, 000
Peripheral
M5L8243P
M5M82C43P
150
-
44
66
44,000
66, 000
MELPS 740
M50740-XXXSP
M50744-XXXSP
M50747-XXXSP
-55
5.5
5.5
5.5
48
36
36
22
36
48
24
22
44, 000
36, 000
36, 000
22, 000
36, 000
48, 000
24, 000
44, 000
MELPS 740
M50740-XXXSP
M50743-XXXSP
M50744-XXXSP
M50745-XXXFP
M50747-XXXSP
M50753-XXXFP
M50754-XXXSP
M50757-XXXSP
M50931-XXXFP
M50943-XXXFP
M50950-XXXSP
M50734SP
125
M50747ES
M50747E-XXXSP
125
MELPS 8-48
M5L8049-XXXP
M5L8050H-XXX P
M5M80C49-XXXP
MELPS 8-41
7
6
7
6
7
6
6
6
6
6
6
6
M50753-XXXSP
M50757-XXXSP
M50950-XXXSP
M50734SP
1-18
Number of Device Hours Number of
(Hours)
Samples
Failures
Vcc(volt)
5.5
5.5
5.5
-
M50747E-XXXSP
-55
MELPS 8-48
M5L8049-XXXP
M5M80C49-XXXP
MELPS 8-41
M5L8042-XXXP
• MITSUBISHI
;"ELECTRIC
I
44
44, 000
-55
5.5
-
22
22
22, 000
22, 000
-55
-
22
22, 000
4
a
a
a
2
0
0
0
0
0
a
a
a
1
a
a
a
a
a
a
a
a
a
0
0
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
MITSUBISHI SINGSE-CHIP 8-BIT MICROCOMPUTERS
QUALITY ASSURANCE AND RELIABILITY TESTING
Test
Temperature Cycling
Series
MELPS 740
Test Condition
Number of
Number of Failures
Samples lOCycles IOOCycies 500Cycles
M50740-XXXSP
M50743-XXXSP
M50744-XXXSP
M50745-XXXFP
M50747-XXXSP
M50747-XXXFP
M50753-XXXFP
M50754-XXXSP
M50754-XXXFP
M50931-XXXFP
M50734SP
-65'C, 30mm
150'C, 30min
M50747ES
M50747E-XXXSP
-65'C, 30min
150'C, 30min
38
38
0
0
a
0
0
0
MELPS 8-48
M5L8049-XXXP
M5L8050H-XXX P
M5MBOC49-XXX P
M5MC49-XXXFP
-65'C, 30min
150'C, 30min
88
76
220
50
0
0
0
0
0
0
0
0
0
0
0
0
MELPS 8-41
M5LB041A-XXXP
M5L8042-XXXP
-65'C, 30min
150'C, 30mm
82
50
0
0
a
0
0
0
M5L8243P
M5M82C43P
-65'C, 30min
150'C, 30min
38
38
0
0
0
0
0
0
-"
Peripheral
1-20
Type Number
• MITSUBISHI
..... ELECTRIC
220
313
120
38
400
38
38
88
96
38
72
0
0
0
0
0
0
a
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
a
0
0
0
a
a
MITSUBISHI SINGSE-CHIP 8-BIT MICROCOMPUTERS
QUALITY ASSURANCE AND RELIABILITY TESTING
Flg.7
Enlarged
micrograph
of corroded
Aluminum
bonding pad
(4)
Aluminum Electromigration
Figure 11 shows an open circuit of aluminum metallization in high current density region caused by accelerated operation life test. This failure is due to aluminum
electromigration. Voids and hillock have been formed
in aluminum metallization by high current density operation.
Flg.11
Voids and
hillocks
formation
by Aluminum
electromlgratlon
Flg.S
CI
distribution
on corroded
Aluminum
bonding pad
5
(3)
Destructive Failure by Electrical Overstress
Surge voltage marginal tests have been performed to
reproduce the electrical overstress failure in field uses.
Figure 9 and Figure 10 are an example of failure
observed by surge voltage test. The trace of destruction is verified as the aluminum bridge by X ray micro
analysis.
Flg.9
Micrograph of surge
voltage destruction
Fig.10
Aluminum trace
of destructive spot
1-22
SUMMARY
The Mitsubishi quality assurance system and examples of
reliability control have been discussed. Customer's interest
and requirement for high reliable IC & LSI are increasing
significantly. To satisfy customer's expectancy. Mitsubishi
as an IC vendor, would like to make perpetual efforts in the
following areas.
(,) Emphasis on built-in reliability at design stage and reliability evaluation to investigate latent failure modes
and acceleration factors.
(2) Execution of periodical endurance, environment and
mechanical test to verify reliability target and realize
higher reliability.
(3) Focus on development of advanced failure analysis
techniques. Detail failure analysis, intensive corrective
action, and quick response to customer's analysis request.
(4) Collection of customer's quality data in qualification, incoming inspection, production and field use to improve
PPM, fraction defective and FIT, failure rate.
Mitsubishi would highly appreciate if the customer would
provide quality and reliability data of incoming inspection or
field failure rate essential to verify and improve the qualityl
reliability of IC & LSI.
•
MITSUBISHI
"'ELECTRIC
MITSUBISHI MICROCOMPUTERS
SERIES MELPS 8-48 MICROCOMPUTERS
FUNCTION OF SERIES MELPS 8-48 MICROCOMPUTERS
M5L8048-XXXP Block Diagram
DATA BUS
I/O PORT 1
I/O PORT 2
OS(
FREQ
(5V) VOD
(sv) Vee
tov) Vss
~
ROREGISTERo
UJ
R1REGISTER
1
~ R2 REGISTE R 2
~ R3REGISTER3 -
A4REGISTER'
~
R5REGISTER~~
R6 REGISTE R.
R7REGISTER 1
RAM 64 BYTES
--------------------To
T)
iNT RESET PROG
EA
X 1
X? ALE PSEIII
55 AD WR
M5L8049-XXXP Block Diagram
DATA BUS
I/O PORT 1
I/O PORT 2
T,
(5\<) Voo
l.Svl Vee
POWER
SUPPLY
FOR RAM
lOY) Vss
:s~ ~~=~g:;~~=:
A2 REGISTER'
~ ~; =~g:;~~=: ~
A5REGISTER~~J
A6 REGISTER.
A7REGISTEA1
RAM 128 BYTES
To
2-4
T1
i'N,.
RESET PROG EA
X1
X 2 ALE
PSnJ
-----------------
ss
• NJITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
SERIES MELPS 8-48 MICROCOMPUTERS
FUNCTION OF SERIES MELPS 8·48 MICROCOMPUTERS
BASIC FUNCTION BLOCKS
Program Memory (ROM)
The M5L8048-XXXP contain 1024 bytes of ROM. The
M5L8049-XXXP contains 2048 bytes of ROM. The program
for the users application is stored in this ROM. Addresses 0,
3, 7 of the ROM are reserved for special functions. Table 1
shows the meaning and function of these three special
addresses.
Table 1 Reserved, defined addresses and their
meanings and functions
Address
Meaning and function
0
The first instruction executed after a system reset
3
The first Instruction executed after an external Interrupt IS
accepted.
7
The f,rst Instruction executed after a timer Interrupt IS accepted.
The ROM can be used to store constants and other 8-bit
fixed data in .addition to the program_ Instructions such as
MOVP A, @A and MOVP3 A, @A can be used to access
the constants and data. The data could be in the form of
tables, and can be easily looked up.
A good practice to simplify programming is to reserve
general-purpose register bank 0 for use of the main program
and register bank 1 for interrupt programs_ For example if
register bank 0 (addressed 0-7) is reserved for processing
data by the main program, when an interrupt is accepted
the first instruction would be to switch the working registers from bank 0 to bank 1. This would save the data of
the main program (addresses 0-7)_ The interrupt program
can then freely use register bank1 (addresses 24-31) without destroying or altering data of the main program_ When
the interrupt processing is complete and control is returned
to the main program by the RETR instruction, register
bank 0 (in this example) is automatically restored as the
working register bank at the same time the main program
counter is restored_
Addresses 0-31 have special functions, but when not
all of the registers are required, the ones not needed can be
used for general storage_ This includes both banks of general-purpose registers and the stack_
63
USER RAM
32X 8
32
31
Data Memory (RAM)
A7
I
The M5L8048-XXXP and M5L8748S contain 64 bytes of
RAM. The M5L8049-XXXP contains 128 bytes of RAM.
The RAM i~ used for data storaQe and manipulation and is
divided into sections for more efficient processing. Addresses 0-7 and 24-31 form two banks of general purpose
'registers that can be directly addressed. Addresses 0-7
compose bank 0 and are numbered RO-R7. Addresses
24-31 compose bank 1 and are also numbered RO-R7.
Only one bank is active at a time. The instructions SEL
I
I
I
I
24
23
/
\
8
7
Addresses 8-23 compose an 8-level program counter
stack. The details for using the stack will be found in the
"Program Counter and Stack," section. Please refer to that
section for details_
The remaining section, addresses 32 and above, must
be accessed indirectly using the general-purpose registers
RO or R 1. Of course all addresses can be indirectly addressed using the general-purpose registers RO and R1.
}
GENERAL'PURPOSE REGISTERS
REGISTER BANK 1
}
GENERAL'PURPOSE REGISTERS
REGISTER BANK 0
Al
AO
25
8,LEVE L ST AC K
16X 8
A7
I
I
I
Al
AO
RBO and SEL RB1 are used to select the working bank.
Fig_ 1 shows the division of the RAM and its mapping.
2-6
,
Fig.4 Data memory (RAM)
PROGRAM COUNTER (PC) AND'STACK {SKI
The Series MELPS8-48 program counter is composed of a
12~bit binary counter as shown in Fig, 5, The low-order 10
bits can address 1024 bytes of memory. When the highorder 2 bits are zero, the Internal, on chip memory is
accessed. The high-order 2 bits can have the values 1-3,
which allows the user to add up to three banks of 1024
bytes, The program counter can address up to 4096 bytes
of memory.
• MITSUBISHI
. . . . ELECTRIC
MITSUBISHI MICROCOMPUTERS
SERIES MELPS 8 .. 48 MICROCOMPUTERS
FUNCTION OF SERIES MELPS 8-48 MICROCOMPUTERS
I/O PORTS
The Series MELPS8-48 has three 8-bit ports, which are called data bus, port 1 and port 2.
Port 1 and Port 2
Ports 1 and 2 and both 8-bit ports with identical properties. The output data of these ports are retained and do not
change until another output is loaded into them. When
used as inputs the input data is not retained so the input
signals must be maintained until an input instruction is
executed and completed.
Ports 1 and 2 so-called quasi-bidirectional ports have
a special circuit configuration to accomplish this. The
special circuit is shown in Fig. 8. All terminals of ports
1 and 2 can be used for input or output.
CPU
INTERNAL-+----l
BUS
CONDITIONAL JUMPS USING TERMINALS To,
T! and INT
RESET
Conditional jump instructions are used to alter program depending on internal and external conditions (states). Details
of the jump instructions for the Series MELPS8-48 can be
found in the section on machine instructions.
WRITE
PULSE
Fig. 8 I/O ports 1 and 2 circuit
Internal on chip pull-up resistors are provided for all
the ports. Through the use of pull-Up resistors, TTL standard high-level or low-level signals can be supplied. Therefore
each termi nal can be used for both input and output. To
shorten switching time from low-level to high-level, when 1s
are output, a device of about 5kn or lower is inserted for
a short time (about 500ns when using a 6MHz crystal oscillator) ..
A port used for input must output all 1s before it reads
the data from the input terminal. After resetting, a port is
set to an input port and remains in this state, therefore it
is not necessary to output all ls if it is to be used for input.
In short a port being used for output must output 1s before
it can be used for input.
The individual terminals of quasi-bidirectional ports
can be used for input or output. Therefore some terminals
can be in the input mode while the remaining terminals
of a port are in the output mode. This capability of ports
1 and 2 is convenient for inputting or outputting l-bit or
data with few bits. The logical instructions ANL and ORL
can easily be used to manipulate the input or output of
these ports.
2-8
Data Bus (Port 0)
The data bus is an S-bit bid irectional port, wh ich is used
with I/O strobed signals. When the data bus is used for
output the output data is latched, but if it is used for input
the data is not latched. Unlike ports 1 and 2, which can
have individual terminals in the input or output mode, all
terminals of the data bus are in the input or output mode.
When the data bus is used as a static port the OUTL instruction can be used to output data and the INS instruction to input data. Strobe pulse RD is generated while the
INS instruction is being executed or WR while OUTL is
being executed_
The data bus read/write using MOVX instructions, but
then the data bus is a bidirectional port. To write into the
data bus a WR signal is generated and the data is valid when
WR goes high. When reading from the data bus, an RD signal is generated. The input levels must be maintained until
RD goes high. When the data bus is not reading/writing, it
is in the high-impedance state.
The input signal status of To, T. and INT can be checked by the conditional jump. instructions. These input
terminals, through conditional jump instructions such as
JTO and JNTO, can be used to control a program. Programs and processing time can be reduced by being able
to test data in input terminal rather than reading the data
into a register and then testing it in the register.
Terminal To, T. and I NT have other functions and uses
that are not related to conditional jump instructions. The
details of these other functi'ons and uses can be found in
the section on terminal functions.
•
MITSUBISHI
. . . . ELECTRIC
MITSUBISHI MICROCOMPUTERS
SERIES MELPS 8-48 MICROCOMPUTERS
FUNCTION OF SERIES MELPS 8·48 MICROCOMPUTERS
The STRT T instruction is used to change the counter
to a timer. The internal clock signal becomes the input to
the timer. The internal clock is 1/32 of 400kHz (when
using 6MHz crystal) or 12.5kHz. The timer is therefore
counted up every 80tls. Fig. 9 shows the ti mer/event
counter.
The counter can be initialized by executing an MOV T,
A instruction. The timer can be used to measure 80tls20ms in multiples of 80tls. When it is necessary to measure
over 20ms (maximum count 256x80tls) of delay time the
number of overflows,one every 20ms, can be counted by
the program. To measure times of less than 80tls; external
clock pulses can be input through Tl while the counter is
in the event counter mode. Every third (or more) ALE sig·
nal can be used instead of an external clock.
SERIES MELPS8-48 CYCLE TIMING
The output of the state counter is 1/3 the input frequency
from the oscillator. When a 6MHz crystal is used for input,
the output would be 2MHz (500ns). A ClK signal is generated every 500ns (one state cycle) which is used for the
demarcation of each machine state. The instruction ENTO
ClK will output the ClKsignal through terminal To. The in-.
put of the cycle counter is ClK (state cycle) and the output
is an ALE signal which is generated every 5 state cycles.
Fig. 11 Shows the relationship between clock and generated cycles. •
One machine cycle contains 5 states with a ClK signal
for demarcation of each state. The Series MElPS8-48 instructions are executed in one machine cycle or two
machine cycles. An instruction cycle can be one or two
machine cycles as shown in Fig. 12.
Fig.10 Clocking cycle generation
INTERRUPT
REQUEST
Fig. 9 Timer/event counter
elK
.~
IOUTPUT TO Tol
ALE
500nsiWHEN USING A 6MHz CRYSTAL)
52
53
54
55
51
52
53
54
r- I I
r- rt- r -
P5EN
RD
WR
PROG
Flg.11 Clock and generated cycle signals
INSTRUCTION EXECUTION
5 Ops
2 MACH I NE CYCLES
1*-+-+-----'------1
Fig.12 Instruction execution timing
2-10
•
MITSUBISHI
..... ELECTRIC
55
f-.-rt~t-nt-njJ"l~f-I"1jJ"lt-n
MITSUBISHI MICROCOMPUTERS
SERIES MELPS 8-48 MICROCOMPUTERS
FI,INCTION OF SERIES MELPS 8·48 MICROCOMPUTERS
A type D flip-flop with preset and reset terminals, as shown
in Fig. 11, is used to generate the signal for SS. When the
preset terminal goes to low-level, SS goes to high-level,
which puts the CPU in RUN mode. When the preset terminal is grounded it goes to high-level. Then SS goes to lowlevel. When SS goes to low-level, the CPU stops. Then when
the push-button switch is pushed, a pulse is sent to the
clock terminal of the type D flip-flop which turns SS to
high-level. When SS goes to high-level the CPU fetches the
WHEN SS IS LOW, THE CPU RECOGNIZES THAT
IT IS TO STOP
t
WHEN THE NEXT INSTRUCTION IS FETCHED,
THE CPU SETS SWITCHES SO ITWI LL STOP AFTER
THE EXECUTION OF THE INSTRUCTION IS COM·
PLETEO
1
next instruction and begins to execute it, but then an ALE
signal is sent to the reset terminal of the type D flip-flop
which turns SS to low-level. The CPU again stops as soon
as execution of the current instruction is completed. When
the push-button switch is again pushed, the cycle is repeated and the CPU is in single-step operation as shown in Fig.
12. While the CPU is stopped in single-step operation, the
data bus and the lo~-order 4 bits of port 2 are used to output the memory address of the next instruction to be fetched. This interferes with input and output, but essential
input/output can be latched by using the rising edge of
ALE as clock.
WHEN ALE IS HIGH, THE MEMORY ADDRESS OF
THE NEXT INSTRUCTION TO BE FETCHEO IS OUT,
PUT THROUGH THE DATA BUS (8 BITS) AND THE
LOW,ORDER 4 BITS OF PORT 2
~
WHEN SS IS RETURNED TO HIGH LEVEL THE
CPU RECOGNIZES THAT IT IS IN THE RUN MODE
THEN THE ALE SIGNAL GOES TO LOW,LEVEL
WHICH INDICATES THE CPU IS IN THE RUN MODE
AND THAT IT IS EXECUTING INSTRUCTIONS'
~
IF THE CPU IS IN THE SINGLE,STEP MODE (PRE,
SET TERMINAL GROUNDEO), AS SOON AS ALE
GOES TO LOW,LEVEL, SS GOES TO LOW,LEVEL
(STOP) IF THE CPU IS THE RUN,MODE (PRE,
SET TERMINAL NOT GROUNDED), SS WI LL RE,
Central Processing Unit (CPU)
Central Processing Unit (CPU) is composed of an 8-bit parallel arithmetic unit, accumulator, flag flip-flop and instruction decoder_ The 8-bit parallel arithmetic unit has circuitry to perform the four basic arithmetic operations
(plus, minus, multiply and divide) as well as Iog'ica I operations such as AND and OR_ The flag flip-flop is used to
indicate status such as carry and zero_ The accumu lator
contains one of the operations and the result is usually
retained in the accumu lator_
2-12
MAIN AT HIGH,LEVEL
Fig_ 15 CPU operation in single-step mode
• MITSUBISHI
..... ELECTRIC
MITSUBISHI MICROCOMPUTERS
SERIES MELPS 8-48 MICROCOMPUTERS
FUNCTION OF SERIES MELPS 8-48 MICROCOMPUTERS
S
Instruction cod€'
Typ
ANL A, :ttn
ANL A, Rr
ANL A, (PRr
ORL A, ::n
ORL A. Rr
ORL A. (aRr
XRL A. ::tn
u
J
~
XRL At Rr
XRL A, (eRr
INC A
DEO A
OlR A
OPl A
DA A
SWAP A
Rl A
RlO A
RR A
RRC A
u
!
~
INC Rr
INC ({:IRr
07 D s D s D 4
0
1
0
1
03 0 2'0,0 0
0
0
1
1
"1"e"s" .. "3"2"'"0
0
0
0
1
1
1
0
0
0
1
1
0
1
0
0
r 2 r, r 0
0
0
o '0
1
1
"7"e"," .. "3"2"'"0
r2 r1
g>
2-14
DEC Rr
Hexadecimal
0
AO
Description
e
0
z
58
+
r
I
I
50
+
r
I
I
2
2
(A)-(A)Vn
I
I
(A)-(A)V(Rr)
r=0-7
The logical sum of the contents of regIster A
and the contents of regIster Rr IS stored In
regIster A
I
I
(A)-(A)V (M(Rr»
r=O-l
The logIcal sum of the contents of regIster A
and the contents of memory locatIon, of
the current page, whose address IS In reglster Rr, IS stored In regIster A
2
2
(A)
43
n
48
+
r
0
1
0
1
0
0
0
o
0 '0
40
+
r
1
1
0
1
0
0
1
D3
1
Function
>
U
2
0
"7"e"s" ..
Effected
carry
ill
u
2
1
'0
>OJ
53
n
0
"3"2","0
n
-
The logical product of the contents of register A and data n. IS stored In register A
(A)-(A)An
The logical product of the contents of reglster A and the contents of register Rr• IS
stored In register A
(A)- (A) A (Rr)
r=0-7
The logical product of the contents of
(A)~(A)A(M(RrJ)
register A and the contents of memory locatlon, of the current page, whose address IS
In register R r • IS stored In register A
r=O-l
~
The I09'cal sum of the contents ot register
A and data n,
IS
stored
In
register A
The exclUSive 0 R of the contents of register
A and data n, IS stored In regIster A
(A)ltn
0
1
1'2','0
D8
+
r
I
I
(A) ~ (A)1t (Rr)
r=1-7
The exclUSIve 0 R of the contents of regIster
A and the contents of register R r IS stored
In register A
1 1 0
1
0
0
oro
DO
+
r
I
I
(A)-(A)V(M(Rr»
r=0-1
The exclUSIve OR of the contents of regIster
A and the contents of memory locatIon, u;
the current page, whose address IS In regIster
Ar • IS stored In regIster A
0
0
0
1
0
1
1
1
1 7
I
I
(A)~(A)+I
I ncrements the contents of regIster A by 1
The result IS stored In register A. and the carries are unchanged
0
0
0
0
0
1
1
1
07
I
I
(A)-(A)-I
Decrements the contents of register A by 1
The result IS stored to regIster A. and the carries are unchanged
0
0
1
0
0
1
1
1
27
I
I
(A)~O
37
I
I
(A)~(A)
57
I
I
(A) --- (A) 10 Hexadecimal
47
I
I
(A.-A,)~ (Ao-A,)
E7
I
I
F7
I
I
77
I
I
87
I
I
18
+
r
I
I
10
+
r
I
I
08
+
r
I
I
1
1
o
0
1
1
0
I
1
1
0
1 0
1
0
1
1
1
0
1
o
0
0
1
1
1
1
1
1
0
0
1
1
1
•
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
0
0
0
0
0
1
1 '2 r 1 , 0
o
0
0
1
0
1
o
1
~
1
'0
~
0:;
ill
Mnemonic
1
1
0
0
1 ' 2 ' , '0
Clears the contents of register A, resets to
0
Forms l's complement of register A. and
stores It to regIster A
0
(A n +l)-(A n)
~Ao)-(A,)
0
(A n)---(A n + 1)
(A,)- (Ao)
(Rr)~(Rr)+1
r=O- 7
(M(Rr »-(M (Ar »)-+ I
r=O-l
(Rr)~(Rr)-1
r=O- 7
• MITSUBISHI
"'ELECTRIC
The contents of regIster A IS converted to bl nary
coded decImal notIon, and It IS stored In register
A If the contents of register Aare more than 99
the carry flags are set to 1 otherwise they are
reset to 0
Exchanges the contents of bIts 0-3 of reglster A With the contents of bIts 4-7 of reglSterA
ShIfts the contents of regIster A left one blt
A., the MSB IS shifted to the carry flag and
the carry flag IS shifted to Ao the LSB
Shifts the contents of register A right one
bit Ao the LSB IS rotated to A., the MSB
n=0-6
(Ao)-(A,.,)
(A,)-(O)
(O)~(Ao) n=0-6
I
Shifts the contents of register A left one bit '
A., the MSB IS rotated to Ao the LSB
n=0-6
(An+I)-(A n)
(Ao)-(O)
(O)-(A,) n=0-6
0
0
ShIfts the contents of register A fight one
bit Ao the LSB IS sh If ted to the tarry flag
and the carry flag IS shifted to A., the MSB
Increments the contents of register Rr by
I The result IS stored In regIster Ar and the
cames are unchanged
Increments the contents of the memory
locatIon. of the current page, whose address
IS to regIster Rr by 1 Register Ar uses btt
0-5
Decrements the contents of regIster Rr by
1 The resu(t is stored In register Rr and the
carnes are unchang~d
MITSUBISHI MICROCOMPUTERS
,
SERIES MELPS 8-48 MICROCOMPUTERS
FUNCTION OF SERIES MELPS 8-48 MICROCOMPUTERS
S
offeeted
Instruction code
~
Mnemonic
Ty
CALL m
07 06 05 0
4
m10"'9me 1
0 3 0 2 0,0 0
0
1
0
0
Hexa·
>
CD
decimal
C
((SP» - (PC) (PSW,-PSW,)
(SP) ~ (SP) + 1
+
m71T1e msm4
Function
~
1 4
Cm a-m 1o)
X2
m3 m 2 m 1 m O
m
carry
~
2
2
(PCO-l0)-m
~
RET
1
o
0
0
0
0
1
1
IS
transferred to pea"'"
2
IS
decremented by 1 The program
counter IS restored to the saved settmg In
the stack indicated by the stack pOinter
(PC) ~ ((SP»
The PSW
IS
not changed and Interrupt dls-
abled IS mamtalneJ
RETR
IN A, Pp
1 0
o
0
0
0
1
0
o
1
0
o
1
1
P'Po
The SP
93
(SP)~(SP)-l
2
1
2
1
2
2
2
2
2
1
2
(A)~(BUS)
Enters the contents of data bus (port 0)
to register A
1
2
(BUS)~(A)
Output latches the contents of register A
data to data bus (port 0)
08
+
OUTL Pp, A
o
0
1
1
1
o
P'Po
1
0
0
1
1
o
P, Po
"7"'"5"4 "3"2"'"0
ORL Po, lin
1
0
0
0
1
o P1PO
"7"&"5"4 "3"2"'"0
98
+
n
0
88
+
n
0
(Pp)
Loads the contents of Pp to register A
p~1-2
(Pp)
0
ANL Pp, :ltn
(PC) (PSW'-PSW')~( (SP»
(A)~
38
+
IS decremented by 1 The program
counter and the 4 high-order bits of the
PSW are restored with the saved data In the
stack mdlcated by the stack pointer The
Interrupt becomes enabled after the execution IS completed
1
0
~(A)
Output latches the contents of register A to
Pp
P~1-2
Logical ANDs the contents of Pp and data
n Outputs the result to Pp
(Pp)~(Po)lIn
P~1-2
(Pp)~(Pp)V
n
Logical ORs the contents of Pp and data
n Outputs the result to Pp
p~1-2
INS A, BUS
0
0
0
0
1
o
0
0
08
OUTL BUS, A
o
0
0
0
0
0
1 0
02
ANL BUS, lin
1
o
0
1
1
o
0
98
n
2
2
(BUS)
(BUS) lin
Logical ANDs the contents of data bus
(port 0) and data n Outputs the result to
data bus (port 0)
88
n
2
2
(BUS)~(8US)Vn
Logical 0 Rs the contents of data bus (port
0) and data n Outputs the result to data
bus (port 0)
1
2
0
"7"&"5"4 "3"2"'"0
'5
ORL BUS, lin
::>
1 000
1
0
0
0
"7"&"5"4 "3"2"'"0
a.
£
MOVO A, Po
o
0
0
0
1
1 P, Po
~
Inputs the contents of Pp
to the low-order 4 bits
of register A and Inputs
to the high-order 4 bits
of register A
OC
+
P1PO
(A.-A,)~(Pp.-pp,)
a
(A4-A7)-O p=4.-7
MOVO Pp, A
0
0
1
1
1
1 p, Po
3C
+
1
2
1
2
P,Po
ANLD PO, A
1
o
0
1
1
1 P1PO
(PP.-pp,)~(
A.-A,)
Outputs the low-order 4
bits of register A to Pp
p~4-7
9C
+
P,Po
(PP.-pp,)~( PP.-pp,)
II(A.-A,)
p=4-7
ORLO Pp, A
1
0
0
0
1
1 P, Po
8C
+
P,Po
2-16
the stack pOinter (SP} The SP IS mGre-
mented by 1 and m
(SP)~(SP)-l
1
~
"
%
g
Calls subroutme from address m The program counter and the 4 high-order bits of
the PSIN are stored In the address indicated
The SP
83
.0
0
0
PC 10 and the MBF IS transferred to PC Il
e
~
)Descnptlon
e
Z
by
(PC,,)~MBF
~
;;
AC
(PP.-pp,)-( PP.-pp,)v (A.-A,)
1
2
p=4-7
• MITSUBISHI
. . . . ELECTRIC
Logical ANDs the 4 loworder bits of register A
and the contents of Pp
Ppcontams the result
Logical ORs the 4 loworder bits of register A
and the contents of Pp
Pp contains the result
Pp's
used
multlfor
plymg 8243
ports are P4
-P,
Correspondenceto P2.
PI IS shown
below
P4
P5
P6
P7
P,PZ=OO
p,Pz=Ol
p,Pz =10
p,Pz=11
MITSUBISHI MICROCOMPUTERS
SERIES MELPS 8-48 MI.CROCOMPUTERS
FUNCTION OF SERIES MELPS 8-48 MICROCOMPUTERS
Details of execution
Item
RESET input low level
TF(Timer Flag) - 0
TIRF(Timer INT Request FF) - 0
TCNTF(Timer INT Enable FF) - 0
INTE(External INT Enable FF) - 0
IFF(INT Enable FF) - 1
JTF execution
TF(Timer Flag) -
Timer/event counter
overflow
TF(Tlmer Flag)-l
When TIRF(Tlmer INT Request FF) -
EN TCNTI execution
TCNTF(Timer INT Enable FF) -
1
DIS TCNTI execution
EN I execution
TCNTF(Timer INT Enable FF) -
0
INTF(External INT Enable FF) -
1
DIS I execution
INTF(Ex,ernal INT Enable FF) -
0
RETR execution
IEF(INT Enable FF)-l
Symbol
,
0
1
TCNTF(Timer INT Enable FF) = 1
Symbol
Meanmg
Meanmg
A
8-blt register (accumlator)
PO
Program counter
AO-A3
The low-order 4 bits of the register A
POO-P07
The low-order 8 bits of the program counter
A4- A7
The high-order 4 bits of the register A
POB-PO,O
The high-order 3 bits of the program counter
Ao-.An,An+,
b
The bits of the register A
PSW
Program status word
b7 bSbS
BS
The bits 5---7 of the flfst byte machine code
Rr
,
Register deSignator
Register bank select
BUS
Corresponds to the pan 0 (bus I/O port)
,a
The value of bit 0 of the machine code
'2"'0
The value of bits 0---2 of the machine code
AO
Auxiliary carry flag
82 8 180
The value of bits O~2 of the stack pOinter
0
Carry flag
SP
Stack pOinter
DBB
Data bus buffer
ST4-ST7
Bits 4---7 o~ the status register
STS
System status
Timer / event counter
The Wiltue of the bits 5-7 of the first byte machine code
Register number
Fa
Flag 0
F,
Flag 1
INTF
Interrupt flag
T
To
T,
IBF
Input buffer full flag
TONTF
Timer / event counter overflow Interrupt flag
The value of the ll-blt address
TF
Timer flag
#
Symbol to Indicate the ImmedIate data
(M (A))
The second byte (low-order 8 bits) machine code of the
l1-blt address
The bits 5~ 7 of the first byte (high-order 3 blts)machme
code of at he l1-blt address
'
The content of the memory locatIon addressed by the register A
@
Symbol to rndlcate the cuntent of the memory locatIon
(M(Rr))
The content of rhe memory locatIon addressed by the regIster Ar
m
m7rn6 mSrn 4m3m2mlmO
ml0 mg ma
(Mx(Rr))
Test prn 0
Test pin 1
address by the register
MBF
The content of the external memory location addressEd
by the register Rr
Memory bank flag
.......,.
n
The value of the Immediate data
(
n 7n 6n Sn 4n 3n 2n In a
The Immediate data of the second byte mach me code
1\
LogIcal A~D
OBF
Output buffer full flag
V
Inclusive OR
¥
ExclUSIve OR
P
Pp
Port number
-
NegatIOn
Port deSIgnator
0
Content of flag IS set or reset after execution
P'PO
The bits of the machine code corresponding to the port number
2-18
Shows directIon of data flow
~
,
• MITSUBISHI
;"ELECTRIC
Exchanges the contents of data
)
Contents of register, memory location or flag
MITSUBISHI MICROCOMPUTERS
M5L8048-XXXPIM5L8035LP
SINGLE-CHIP 8-BIT MICROCOMPUTER
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5L8048-XXXP and M5L8035LP are 8-bit parallel
microcomputer fabricated on a single chip using highspeed N-channel silicon-gate ED-MOS technology_
TEST PIN 0 To .... 1
Vee (5V)
CLOCK INPUT 1 x,-+ 2
M5l8048-XXXP
M5l8035lP
Built-in ROM (1 K bytes)
External ROM
CLOCK INPUT 2 X, _
3
RESET INPUT RESET -
4
5
SINGLE-STEP INPUT SS _
FEATURES
•
•
Single 5V power supply
Instruction cycle _ ...• _ .....
•
Basic machine instructions:
1-byte instructions: 68
2-byte instructions: 28
•
•
REQ0~~~~~~0:;: INT . .. _ 2.5tls (min)
7
RD -
8
READ
STO:r,R~NGA~:~
..... '" ... 96
PSEN -
9
'WRITE WR -
10
LATC~~~m~
Direct addressing . . . . . . . . . . . . . . up to 4096 bytes
Internal ROM • . . . . . . . . . . . . . ___ . __ 1024 bytes
(for M5L8048-XXXP only)
•
Internal RAM . . . . . . . . . . . . . . . . . . . . . 64 bytes
•
Built-in timer/event counter . . . . . . . . . . . . .. 8 bits
•
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . 27 lines
ALE -
110 PORT 1
11
27 .....
P1 0
Voo (5V)
25 _ PROG ~/gERNAL
26
DATA BUS
P2 3
P2,
22 .... P2 ,
24 ....
23 ....
- . ' - -_ _ _ _--"2-1 .......
• Easily expandable Memory and I/O
• Subroutine nesting . . . . . . . . . . . . . . . . . . . 8 levels
• External and timer/event counter interrupt. 1 level each
•
•
•
6
EXTERNAL ACCESS EA -
Outline
Low power standby mode
External RAM ....... _ .......•.. _ .. 256 bytes
Interchangeable with i 8048 and i 8035L in pin configuration and electrical characteristics
f,
CONTRO,L
OUTPUT
1/0 PORT 2
P2 0
40P4
FUNCTION
APPLICATION
The M5L8048-XXXP and M5L8035LP are integrated 8-bit
•
CPU, with memory (ROM, RAM) and timer/event counter
Control processor or CPU for a wide variety of applications
BLOCK DIAGRAM
DATA BUS
interrupt all contained on a single chip.
110 PORT 2
1/0 PORT 1
osc
FHEQ
ROREGISTER 0
Rl REGISTER 1
R2REGISTER 2 0
R3REGISTER 3 ""
R.REGISTER 4 ;;::
~ RS REGISTER <; co
o R6REGISTER6
R7REGISTER'
8
~
STACK
i:2
ROREGISTER 0
w R1REGISTERl
R2REGISTER2
~ R3REGISTER 3 R4REGISTER4 ~
6
R6REGISTER6
R5REGISTER 5;ii,
R7REGISTER7
RAM 64 BYTES
--------------------To
2-20
T]
iNT RESET
PROG EA
X1
X 2 ALE PSEN
55 AD WR
• MITSUBISHI
. . . . ELECTRIC
,__
MITSUBISHI MICROCOMPUTERS
MSL8048- XXXP/MSL803SLP
SINGLE-CHIP a-BIT MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Vee
Supply voltage
VOO
'Supply voltage
V,
Input voltage
Vo
Output voltage
Conditions
Unit
Limits
With respect to Vss
-0.5-7
V
-0.5-7
V
-0.5-7
V
-0.5-7
V
1.5
W
Pd
Power diSSipation
Topr
Operating free-air temperature range
-20-75
'C
Tstg
Storage temperature range
-65-150
"C
Ta=25\:
.RECOMMENDED OPERATING CONDITIONS
(Ta = -20-75"C, unless otherwISe noted)
Limits
Symbol
Parameter
Min
Nom
Max
Unit
Vee
Supply voltage
4.5
5
5.5
V
Voo
Supply voltage
4.5
5
5.5
V
Vss
Supply voltage
V,Hl
High-level Input voltage, except X1, X2 and RESET
0
V
2
V,H2
High-level Input voltage, except X1, X2 and RESET
V,L
Low-level Input voltage
V
Vee
- - r---
-----
--.-~
3.8
Vee
V
-0.5
0.8
V
-
ELECTRICAL CHARACTERISTICS
(Ta=-20-75'C,
Vcc=VoD=5V± 10%, VSS=OV,
unless otherWISe noted)
Limits
Parameter
Symbol
VOL1
Low-level output voltage, BUS, FfD, WR,
VOL2
Test conditions
PS""EN, ALE
Min
Typ
Max
Unit
IOL=2mA
0.45
V
Low-level output voltage, except the above and PROG
IOL=1.6mA
0.45-
V
V OL3
Low-level output voltage, PROG
IOL=1mA
0.45
V
VOH1
High-level output voltage, BUS, RD, WR,
V OH2
High-level output voltage, except the above
IOH
I nput leak current, T1, I NT
VSS";V,N";Vee
~
-10
I,
J5SEl\I,
IOH= ~ 100 "A
ALE
V
2.4
= -50,uA
V
2.4
10
1Q
"A
loz
Output leak current, BUS, TO high-Impedance state
VSS + 0.45"; V,N"; Vee
ILl1
Inpu't current dUring low-level Input, port
V'L=0.8V
~0.2
ILl2
Input current dUring low-level Input, RESET,
V'L=0.8V
-0.05
IDD
Supply current from VDO
10
20
mA
loo+lcc
Supply current from VD D and Vee
65
135
mA
TIMING REQUIREMENTS
Symbol
ss-
(Ta=~20-75"C. Vee=VDD=5V±10%, Vss=OV. unlessotherw,senoted)
Alternative
symbol
Parameter
Limits
Min
to
Cycle time
tCY
2.5
th (PSEN-O)
Data hold time after PSEN
I DR
t h (R-O)
Data hold time after RD
IDR
tsu (PSEN-O)
Data setup time after
tsu (R-O)
tsu (A-D)
Typ
Unit
Max
15.0
itS
0
200
ns
0
200
ns
t RD
500
ns
Data setup time after RD
tRD
500
ns
Data setup time after address
tAD
950
ns
Isu (PROG'O)
Data setup time after PROG
tpR
810
ns
th (PROG'O)
Data hold time before PROG
IpF
150
ns
Note 1
2-22
I
PSt"N
0
The Input voltage level of the Input voltage IS VIL -0 45V and VIH=2 4V
•
MITSUBISHI
;'ELECTRIC
10
"A
mA
mA
MITSUBISHI MICROCOMPUTERS
MSL8049-XXXP, P-6
MSL8039P-ll, P-6
SINGLE·CHIP a·BIT MICROCOMPUTER
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5L8049-XXXP, P-6 and M5L8039P-ll, P-6 are 8bit parallel microcomputers fabricated on a single chip
using high-speed N-channel silicon gate ED-MOS technology.
~pe
Speed
II MHz Type
6 MHz Type
I nternal ROM Type
TEST PIN 0 To .... I
CLOCK INPUT 1
External ROM Type
M5L8049·XXXP
M5L8039P·II
M5L8049·XXXP·6
M5L8039p·6
X, -
CLOCK INPUT 2 X, -
3
RESET INPUT RESET -
4
SINGLE-STEP INPUT
Ss -+
REQ~~~~~~~~i
INT EXTERNAL ACCESS EA -
FEATURES
READ RD
•
Single 5V power supply
•
Instruction cycle
11MHz
STO:ER~~A~~~
~
Vee (5V)
2
I/O PORT 2
5
6
7
8
~
PSEN
9
WRITE WR~ 10
8M Hz
ADDRES~~~~~~
6MHz
ALE
~
I/O PORT 1
11
Do ..... 12
2.5"s(min)
•
Basic machine instructions
l-byte instructions: 68
27
96
DATA BUS
2-byte instructions: 28
VDD (5V)
25 _
PROG ~;g-ERNAL
24 .... P2 3
•
Direct addressing .. .
. up to 4096 bytes
•
•
Internal RAM . . . . . . . . .
Built-in timer/event counter
...... 128 bytes
. 8 bits
•
•
•
27 lines
I/O Ports . . . . . . . . . . . . .
Easily expandable Memory and I/O:
Subroutine nesting . . . . . . . . . _ ... _ . . . .. 8 levels
•
External and timer/event counter interrupt. 1 level each
•
External RAM ....................... 256 bytes
•
M5L8049-XXXP/M5L8039P-ll, P-6 are interchangeable
with i 8049/i 8039, i 8039-6 in pin configuration and electrical characteristics.
BL09K DIAGRAM
P1 0
++
26
DATA BUS
110 PORT 1
23 ++ P2 2
22 .... P2,
l
CONTROL
OUTPUT
I/O PORT 2
......'-_ _ _ _ _r2-1 ++ P2 0
Outline
40P4
APPLICATION
• Control processor or CPU for a wide variety of applications
I/O PORT 2
T,
~ ~~~~g:~~~= ~
6 R2AEGISTER2
~ :!~~g',~~~~: ~
R5REGISTEUR~
REGISTER.
R7REGISTER1
R6
RAM 128 BYTES
--------------------TO
2-24
TI INT RESET PROG EA
x1
X 2 ALE PSEN
SS
•
MITSUBISHI
...... ELECTRIC
MITSUBISHI MICROCOMPUTERS
MSL8049·XXXP,P·6
MSL8039P.ll,P·6
SINGLE-CHIP 8-BIT MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Unit
Limits
Conditions
-0.5-7
Supply voltage
Vee
V
-~-~
VDD
Supply voltage
V,
Input voltage
Va
Output voltage
Pd
Power diSSipation
Ta~25"C
Topr
Operating free-a If temperature range
MSLB049-XXXP-6
MSLB039P-6
MSLB049-XXXP
MSLB039-11
With respect to Vss
]
V
-0.5
V
7
-0.5-7
V
1 :5
W
-20-75
·C
1
Storage temperature range
Tstg
-0.5-7
0-70
·C
- 65-150
RECOMMENDED OPERATING CONDITIONS
(Ta =-20-75"C,unlessotherwlSenoted)
Limits
Parameter
Symbol
Nom
Max
Unit
Vee
Supply voltage
4.5
5
5.5
V
VDD
Supply voltage
4.5
5
5.5
V
Vss
Supply voltage
VIHl
High-level Input voltage, except for Xl, Xl,
-
f--
Min
V
0
RESTI
2
V
Vee
t----- r - - VIH2
High-level Input voltage, Xl. X 2• RESET
V,L
Low-level Input voltage
ELECTRICAL CHARACTERISTICS
3.8
Vee
V
-0.5
0.8
V
(Ta=-20-75"C,
Vee~VaD~5V ±
1 0%,
VSS~OV,
unless otherwISe noted)
Limits
Symbol
Parameter
Test conditions
Min
Unit
Max
TVp
V OL1
Low-level output voltage, BUS, RD, WR, PSEN, ALE
IOL~2rnA
0.45
V
V OL2
LOW-level output voltage, except for the above and PROG
laL~
0.45
V
VOL3
Low-level output voltage PROG
IOL~lrnA
0.45
V
V OH1
High-level output voltage, BUS, RD, WR, PSEN, ALE
I<>< ><
>< ><
_ ~
-t
",,!~
n ................
:I
R6 REGISTER 6
RAM(l28 SYTESl
CD CD
!"I :.::.
STACK
T,
INT
FLAG 0
FLAG 1
TIMER FLAG
CARRY
ACC
nn
.....
(It
:l I: I:!
:I UlUI:I
- 1:1: n
~ GD GD ~
o 00 n
g nn
:I
"I
~
I:
0
W W ~
CD CD C
:.::. ~
",,=
MITSUBISHI MICROCOMPUTERS
MSM80C49A-XXXP/MSM80C39AP
MSM80C49H-XXXP/MSM80C39H P
SINGLE·CHIP a·BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Symbol
Conditions
Limits
Unit
V ss -0.3-7
V
Input voltage
Vss-O. 3-Vee+0. 3
V
Vo
Output voltage
Vss-O. 3-Vee+0. 3
V
Pd
Power dissipation
1.5
W
t
'c
Parameter
Vee
Supply voltage
V,
Ta=25'C
Topr
Operating free-air temperature range
-20-75
Tstg
Storage temperature range
65-150
RECOMMENDED OPERATING CONDITIONS
(Ta=-20~75'C, unless otherwise noted)
limits
Symbol
Parameter
M5M80C49A-XXXP
M5M80C49H-XXXP
M5M80C39AP
M5M80C39HP
Min
Nom
Max
Min
Nom
Max
4,5
5
5.5
4.5
5
5.5
Unit
Vee
Supply voltage
Vss
Supply voltage
V 1H1
High-level Input voltage, except EA, RESET, X" X,
0. 7Vee
Vee
2
Vee
V
V 1H2
High-level input voltage, EA, RESET, X" X,
D. 8Vee
Vee
3.8
Vee
V
V 1U
Low-level Input voltage, except EA, RESET, X" X,
Vss
0. 3Vee
Vss
O.'S
V
V 1L2
Low-level input voltage, EA, RESET, X" X,
Vss
0. 2Vee
Vss
0.6
V
ELECTRICAL CHARACTERISTICS
V
0
0
V
(Ta=-20-75'C, Vcc =5V±10%, Vss=ov, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
M5M80C49A-XXXP
M5M80C49H-XXXP
M5M80C39AP
Min
Typ
Unit
M5M80C39HP
Max
Min
Typ
Max
VOL
Low-level output voltage
IOl-2mA
V OH1
High-level output voltage, except Pl o-Pl" P2o-P2,
IOH-
0. 75Vcc
2.4
V
V OH2
High-level output voltage, P1o-Pl" P2o-P2,
400"A
(Note 1)
2.4
V
I,
Input current, T" INT, SS, EA, STBY
VSS~VIN~VCC
O. 75Vcc
-1
1
-1
1
"A
102
Output current, BUS, To, high Impedance state
VSSS:VIN::S;;:VCC
-1
1
-1
1
I"
Input current dUring low level, Port
V1L-VSS
-40
-100
-200
-500
"A
/lA
1'2
leel
Input current during low level, RESET, SS
V1L-VSS
-40
-100
-40
-100
/lA
Supply current
atllMHz
5
10
5
10
rnA
2.5
5
2.5
5
rnA
1
10
1
10
/lA
ICC2
Supply current dUring HALT
at 11 MHz(Note 2)
ICG3
Supply current during STAND BY
(Note3)
VCC(STB)
Stand by power supply voltage
Note
2-36
0.45
2
IOH--5/lA (M5M80C49A-XXXP, M5M80C39AP)
IOH=-40/lA (M5M80C49H-XXXP, M5MSOC49HP)
BUS, To, T" EA, INT=Vcc or Vss
SS, RESET, STBY=V ce
BUS, To, T" EA, INT=Vcc or Vss
RESET, STBY=Vss
SS=Vcc
• MITSUBISHI
';"ELECTRIC
0.45
2.
V
V
MITSUBISHI MICROCOMPUTERS
MSM80C49A-XXXP/MSM80C39AP
MSM80C49H-XXXP/MSM80C39HP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING DIAGRAM
Write to External Data Memory
Read from Exteral Data Memory
td(AlE-R)
td(ALE_W)
ALE
WR
BUS
Instruction Fetch from External Program
Memory
Port 2 (Expanded port)
td( PROG-ALE)
ALE
ALE
1-_~-+-~_t...
d--l(PSEN-ALE)
1~_____________ P2o-P23-~~--~~----"~~-x~~~JDURING
,,...-----'f
PSEN - - - -__11---"<1.
td(A-ALE)
BUS
I,
OUTPUT _ F l_ _...:;:..-_...rl--";::';~~
-I-~;ij---tJ(;
---~~AD~D:R~ES~SJ>--+--4~~:l~----- P;~;,~~3 INPUT
PROG
------------~~'lt~W~(P~R~O~G~u---I}-----
Port 1, Port 2
ALE
2-38
,J""---
......,--..",,.......--"OJ.....,~;;...,.rI--..u--..J-.....
•
MITSUBISHI
"'-ELECTRIC
N
..,.I
C>
HALT instruclJon cycle
t--
[S1-8~S3---8-';-
85 181 82
1
. --;,
83
84
85181
82
83
84
85181
82
83
84
85181
82
83
84
wi
To
1\
ALE
r\
II
P8EN~---
,.
J'II:I
r""_
J'II-I
r\
'---1,---'-----1
~
1\
\
I
!---------.. . '__J~'__J~'__J~L_J
Q~Q~Q~Q--
DB
!,
INT
F=lg.2
1:1:
UIUI
1:1:
f
\
!! aD aD
Z
00
HALT instruction timming chart (Interrupt disable)
('H/I
-Ie:
:UI:III
c:iiii
r
~
181
82
83
84
85181 82
>r
HALT instruction cycle
- - ---
---~,
83
84 85181
~
executing Instructloni
82
83
84
85181
Calling Interrupt sUNice routme-----=1
82
83
84
85181
82
83
84
11'1
n
nn
~~
=
3>
" =
><><><-1
:I
..................
::; >< ><
~
() "'a "'a !!!!
1\
ALE
P8EN
-1'---1
r\
II
---" -- -
~
DB
,fC+
~
1\
r\
'-----1
\
5: 1:1:
),
\
I
1--0-8-e----B-8---0-I
- 1:1: ()
~ aDaD~
S nn ~
o 0 0 ()
"
HALT instruction timming chert (Interrupt enable)
W W "
U) U) e:
~ =3>;;1
!:
Fig.3
=
:I UlUI!
:I
INT
(I)
"'a "'a ~
MITSUBISHI MICROCOMPUTERS
MSM80C49A.XXXP/MSM80C39AP
MSM80C49H·XXXP/MSM80C39HP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESETn+_
l,uF
M5M80C49A-XXXP
M5M80C49H-XXXP
roB-=!
Internal reset
STBY
Control circuit example for standby mode
x,
x,
PORT 1
Open
STBY PORT 2
' - RESET OUTPUT
~ EA
DBf--
r-
~T,
Tof-Vo.
I
Fig.7
2-42
I~@
----------~,~--------------~\~---------
Internal standby
Flg.6
®r:'---
Conditions of measurement Icc (at standby mode)
• MITSUBISHI
. . . . ELECTRIC
N
I
1:
BLOCK DIAGRAM
r---
I/O PORT P2
1/0 PORT P1
DATA BUS
---------------------,
I
I
I
,.
"'I:
r"'_
~~
::Uall
ni
~,
T,
I
j
I
~
I
I
I
iIi)
.
-"
><
><
><
."
I
I
R2 REGISTER 2
0
R3 REGISTER 3
'"
'"
R4 REGISTER 4
I
L.-..aoot,"","",",n&;;~C)1
~~ .. ---.
DECODER
Iffi0
0
(5VlVcct--:
U
RS REGISTER S
R6 REGISTER 6
z
ID
(I)
I
I
R7 REGISTER 7
LU
0
(OVlVssr
STACK
I
RO REGISTER 0
To
'"
~'
g
5" [52
i= z
15 ~
Z
o
u
(!)
ID
"--
INT
FLAG 0
FLAG 1
TIMER FLAG
CARRY
ACC
ACC BIT TEST
I~
I
R1 REGISTER 1
R2 REGISTER 2
R3 REGISTER 3
R4 REGISTER 4
RS REGISTER S
R6 REGISTER 6
~
'"
z
'"
ID
R7 REGISTER 7
,I
.
I
--.J
I
RAM(128 BYTESl
- - - - - - - - - - - - - ---- - - - - - - - - - - - STBY To
CII
T,
INT RESETPROG EA X,
xi
ALE PSEN
SS
RD
WR
.'Z."
n
lID
I
all
-t
n
i:
0
(I)
-
I:
n
::u
0
n
0
i:
"-tC
::u
'"
==
C")
U)
•
I:
"'a-
.... =
== CII
== C
all
(I)
.. Z
C") I:
U>~
0
Z n
•
><
><
><
."
"'a
0
I:
"
C
-t
'"
::u
(I)
MITSUBISHI MICROCOMPUTERS
MSMC49-XXXFP/MSMC49H-XXXFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Limits
Unit
Vss-0.3-7
V
Input voltage
Vss-O. 3-Vee+0. 3
V
Vo
Output voltage
Vss-O. 3-Vee+0. 3
V
Pd
Power disSipation
0.3
W
Topr
Operating free-air temperature range
-20-75
°C
Tstg
Storage temperature farge
-65-150
°C
ConditIOns
Parameter
Symbol
Vee
Supply voltage
V,
Ta=25"C
RECOMMENDED OPERATING CONDITIONS
(Ta=-20-75°C, unless otherwise noted)
limits
Symbol
MSMC49A-XXXFP
Parameter
Vee
Supply voltage
Vss
Supply voltage
V'H1
High-level Input voltage. except EA. RESET,
V 1H2
High-level Input voltage, EA. RESET, X" X,
V 1L1
Low-level Input voltage, except EA. RESET, X,. X,
V 1L2
Low-level Input voltage, EA, RESET, X" X,
Nom
Max
Min
Nom
Max
4.5
5
S.5
4.5
5
5.5
V
2
Vee
V
0
ELECTRICAL CHARACTERISTICS
x,. X,
Unit
MSMC49H-XXXFP
Min
V
0
0. 7Vee
Vee
O. aVec
Vee
0. 3Vce
3.8
Vee
V
Vss
Vss
0.8
V
Vss
0. 2Vee
Vss
0.6
V
(Ta=-20-75"C, Vcc =5V±10%, Vss=ov, unless otherWise noted) .
limits
Symbol
Parameter
Test conditions
M5MC49A-XXXFP
Min
Low-level output voltage
Typ
IOL=2mA
Unit
M5MC49H-XXXFP
Max
Min
Typ
Max
0.45
0.45
V
VOL
V OH1
High-level output voltage, except P1o-P17, P2o-P27 IOH=-400"A
O. 75Vcc
2.4
V OH2
High-level output voltage, Pl o-P17, P2o-P27
(Note 1)
2.4
I,
Input current, T,. INT, SS, EA, STBY
VSS~VIN~VCC
O. 75Vcc
-1
loz
Output current, BUS, To, high Impedance state
VSS~VIN~VCC
-1
111
Input current durmg low level, Port
VIL=VSS
-40
-100
-200
1'2
Input current during low level, RESET, S8
VIL=VSS
-40
-100
-40
-100
/-lA
Icc1
Supply current
at 11 MHz
5
10
5
10
mA
Ice2
Supply current dUring HALT
at 11 MHz(Note 2)
2.5
5
2.5
5
mA
Icc3
Supply current dUring STAN D BY
(Note3)
1
10
1
10
/-lA
VCC(STB)
Stand by power supply voltage
Note
2
3
2
IOH=-5jiA (M5MC49A-XXXFP)
IOH=-40jiA (M5MC49H-XXXFP)
BUS. To, T EA, INT=Vec or Vss
"
SS, RESET, STBY=Vec
BUS. To, T EA, INT=Vcc or Vss
"
RESET, STBY=Vss
SS=Vec
2-46
• MITSUBISHI
"'-ELECTRIC
1
-1
1
-1
2
V
V
1
/-lA
1
/-lA
-500
/-lA
V
MITSUBISHI MICROCOMPUTERS
MSMC49·XXXFP/MSMC49H·XXXFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING DIAGRAM
Write to External Data Memory
Read from Exteral Data Memory
td(ALE-R)
td(ALE-W)
ALE
ALE
WR
BUS
--~~~~--~~>----
BUS
Instruction Fetch from External Program Memory
Port 2 (Expanded port)
Ie
ALE
ALE
td(PSEN-ALE)
I """;-----o-i----.~
IJ--------------
PSEN
I~--~
BUS
~~A~O~OR!E~SS!)--+--~C~!J~-----------
P2o-P23 ___~~____~__~~}-~__~~__~J-
DURING
OUTPUT __J'~____~___'~~~~~~~J~__~~~'-----__
P2o-P23 __~r-__~~____,,______~~~~__~~~U-_____
DURING
INPUT
tSUZ(A-O)
PROG
-------------------------t.Ir-~lw~(~PR~O~G~U~-~---------
Port 1, Port 2
ALE
NEW DATA
2-48
• MITSUBISHI
"'ELECTRIC
N
I
(JT
o
I EO
[£1-· 82
83
84
I
HALT Instruction cycle
·-----~l
85181 82
83
84
85181
82
83
84
85181
82
83
84
85181
82
$3
84
__
I
To
ALE
~
P8EN..J
,.
11'131:
~CiI
-Ie:
r"'_
~
r\
1\
"----1
/}
,----
\
L-...J
j--------_Q~Q~- - -Q~ Q-_
DB
INT
r--\
II
{""""""\
"-J~"-J~"-J~'--'
----------------jJ,
Fig.2
:I
(II
:I
r
\
tit
HALT instruction timming chart (Interrupt disable)
Z
C)
:::a~
niii
=
r
[S1
82
83
~5J~;----;-
HALT instructIon cycle
-
II
::
83
r
84 85 181
r
.
=
11'1
executmg instructIOn,
82
83
84
85 181
Calling interrupt survice routine------1
82
83
84
85181
82
83
84
__
I
n
'V
110
Ill:!
-I
To
n
31:
ALE
II
{""""""\
P8EN..J
~
--
- _ . -,,-----
r--\
1\
"----1
L-.J
~
r\
\
I
'eJ~e3-B-----8-B---0---
INT
- - - - - - - - - - - - - - j iJ, - - - - - HALT instruction timming chert (Interrupt enable)
><
><
><
"'31:
-a=t
......... tIt
:Ii
(llUi
31:
n
~n
U):::a
0
n
0
!:
e:
-I
'"
::u
Fig.3
U)
:1=
'V
\_--------------~I
••
tit
-0
:::a
DB
(")
(")31:
:cO
• n
><'V
><~
.,,'"
-a=
MITSUBISHI MICROCOMPUTERS
MSMC49-XXXFP/MSMC49H-XXXFP
SINGLE-CHIP a-BIT CMOS MICROCOMPUTER
M5MC49A-XXXFP
M5MC49H-XXXFP
STBY
f--o~
8
__
ro
I nternal reset
~~
STBY
Control circuit example for standby mode
_-1
,------
5V
Vee
~
l-
58
X,
X,
INT
PORTl
~
~
Open
STBY PORT 2
RESET OUTPUT
DB r--
EA
Tor--
~T,
Vss
1_.____
~
Fig.7
2-52
I}~
----------~~--------------..,\~---------
Internal standby
Fig.6
@~'---
Conditions of measurement Icc (at standby mode)
• MITSUBISHI
"'-ELECTRIC
MITSUBISHI MICROCOMPUTERS
MSL8049Hl.XXXP/MSL8039HLP·14
SINGLE-CHIP 8-BIT MICROCOMPUTER
PIN DESCRIPTION
Pm
Name
Input or output
FunctIOn
Vss
Ground
Normally connected to ground (OV)
Vee
Main power supply
Connected to 5V power supply
Voo
Power supply
CDConnected to 5V power supply
®Used for memory hold when Vee
To
Test pm 0
Input
Output
IS
cut.
Q)ControJ signal from an external source for conditional Jumping In a program Jumping is dependent on
external conditions (JTO/JNTO)
(2)Used for outputting the Internal clock signal (ENTO ClK)
X" X2
Crystal ,"puts
Input
External crystal oscillator or RC circuit mput for generating Internal clock signals
An external clock signal can be Input through Xl or X2
-RESET
Reset
Input
Control used to initialiZe the CPU
SS
Single step
Input
Control signal used
mode
-INT
Interrupt
Input
Q)Control signal from an external source for condltronal Jumping In a program. Jumping IS dependent on
external conditions (JNI)
(2)Used for external Interrupt to CPU
EA
External access
Input
CDNormally maintained at OV
(£JWhen the level 15 raised to 5V, external memory will be accessed even when the address 15 less than
400 16 (2048) The M5l8039HlP-14 IS raised to5V
RD
Read control
Output
Read control signal used when the CPU requests data from external data memory or external device to
be transferred to the data bus
(MOVX A, @R r , and INS A, BUS)
-PSEN
Program store enable
Output
Strobe signal to fetch external program memory
WR
Write control
Output
Write control signal used when the CPU sends data through the data bus to external data memory or external deVice.
(MOVX @R r, A and OUTl BUS, A)
ALE
Address latch enable
Output
A signal used for latching the address on the data bus. An ALE signal occurs once during each cycle
~
In
conjunction With ALE to stop the CPU through each instruction,
In
the single-step
Q)Provldes true bidirectional bus transfer of instructIons and data between the CPU and external memory SynchroniZing IS done With signals RO/WR The output data IS latched.
Do-D7
Data bus
Input/output
(2)When using external program memory, the output of the low-order 8 bits of the program counter are
synchronized with ALE After that, the transfer of the Instruction code or data from the external program
memory IS synchronized With PSEN
@The output of addresses for data uSing the external data memory IS synchronIzed with ALE After that,
the transfer of data With the external data memory IS synchronized With Ro/WR
(MOVX A, @R r , and MOVX @Rr,A)
Input/output
P2 0 -P27
Port 2
Output
Input/output
PROG
Program
Pl o-P1 7
Port 1
T,
Test pin 1
2-54
Output
(Dauasl-bldlrectlonal port When used as an input port, FF 16 must first be output to thiS port After reset,
when not used as an output port, nothing needs to be output
(£JP2o....... P23 output high-order 4 bits of the program counter when uSing external program memory
@P2o-P2, serve as a 4-blt 1/0 expander bus for the M5l8243P
Strobe signal for M5l8243P 110 expander
Input/output
QuasI-bidirectional port When used as an Input port, FF 16 must first be output to thiS port After reset,
when not used as an output port, nothing needs to be output
Input
(DControl signal from an external source for conditional Jumping In a program. Jumping IS dependent on
external conditions (JT1/JNT1)
(2)Whe" enabled, event signals are transferred to the timer/event counter (STRT CNT)
•
MITSUBISHI
..... ELECTRIC
MITSUBISHI MICROCOMPUTERS
MSL8049Hl.XXXP/MSL8039HLP·14
SINGLE-CHIP 8-BIT MICROCOMPUTER
TIMING REQUIREMENTS
(Ta = 0-70'C, Vee = Vee = 5V±10%,
Parameter
Symbol
v•• = ov,
unless otherwise noled)
L.'mlts
Relallonshlp 10
Alternative
cycle lime (Ic)
symbol
Min
I
71.4
1000
ns
Typ
Max
Unil
I
Clock cycle
l/lxTAL
Ie
Cycle lime
15t
Icy
1. 07
15
I-'S
Ih (PSEN-O)
Dala hold lime after PSEN
1.5t- 30
IDA
0
80
ns
Ih (A-D)
Data hold lime after RD
1.5t- 30
IDA
0
80
ns
tsu
Data setup time after PSEN
4.5t-170
tAD2
160
ns
Dala setup time after RD
6t-170
tRD1
260
ns
10. 5t - 220
tAD1
530
ns
7.5t- 220
tAD2
340
ns
8.5t-120
t pA
530
ns
1.5t
tpF
110
ns
(PSEN-O)
Isu (A-D)
Data setup time after address
tSU1 (A-D)
(external data memory read cycle)
Data setup time after address
tSU2 (A-D)
(external program memory read cycle)
tsu (PROG-O) Data setup time after PROG
Data hold time after PROG
th (PROG-O)
Note 1
2
a
The inpul voltage level is V,L = O. 45V and V,H = 2.4V
IXTAL is the oscillator frequency entered at Ihe crystal Input terminals (X" X,)
SWITCHIN~
CHARACTERISTICS
Symbol
(Ta = 0-70'C, Vee = Veo = 5V±10%, Vss = OV, unless olherwise noted)
Parameter
Relallonshlp to
Alternative
cycle time (tcl
symbol
Min
Limits
Typ
Max
Unit
ALE pulse Width
3.5t-170
ILL
80
ns
Id (A-ALE)
Address to ALE signal delay time
2t - 110
tAL
30
ns
tv (ALE-A)
tw (PSEN)
Address valid time after ALE
t-40
ILA
30
ns
PSEN pulse Width
6t- 200
tC02
225
ns
tW(A)
RD pulse Width
7.5t - 200
tec1
ns
tw(w)
WR pulse Width
7.5t - 200
tCC1
Id (Q-W)
Data to WR signal delay tllne
6.5t - 200
tow
330
330
260
tv (W-Q)
Data valid time after WR
t-50
two
20
ns
td (A-W)
Address to WR signal delay time
5t-150
lAW
ns
td (AZ-A)
Address disable to RD signal delay lime
2t-40
td ('AZ-W)
Address disable to WR signal delay time
2t-40
t A FC1
tAFC1
200
100
100
ns
td
td
(AZ.PSEN)
Address disable to PSEN signal delay time
0.5t- 40
(ALE-R)
ALE to RD signal delay time
Id (ALE-W)
td
tw
(ALE)
ns
ns
ns
5
ns
3t-75
tAFC2
t LAFC1
140
ns
ALE to WR signal delay time
3t-75
tLAFC1
140
ns
ALE to PSEN signal delay time
1.5t-75
tLAFC2
40
ns
Id (A-ALE)
RD to ALE signal delay time
t-65
tCA1
10
ns
Id (W-ALE)
WR to ALE signal delay time
t-65
tOA1
10
ns
td (PROG-ALE)
td (PSEN-ALE)
td (pC-PRoa)
tv (PROG-PC)
td (Q-PROG)
tv (PROG-Q)
PROG to ALE signal delay time
t-65
tOA1
10
ns
PSEN to ALE signal delay time
4t-70
tCA2
210
ns
Port control to PROG signal delay time
1.5t- 80
tcp
25
ns
Port control valid time after PROG
4t- 260
t pc
25
ns
Data to PROG signal delay time
6t- 290
lop
130
ns
Data vaUd lime after PROG
1.5t-90
Ipo
15
ns
tw
PROG low-level pulse Width
10. 5t - 250
Ipp
500
ns
tP;L
80
ns
5
(ALE-PSEN)
(PROGL)
AI-200
Id (O-ALE)
Dala to ALE signal delay time
tv
Data valid time after ALE
0.5t- 30
I LP
Id (ALE-Q)
Delay time after ALE
4.5t+ 100
Ipv
tW(TO)
To pulse spacing
3t
(ALE-Q)
Nole 3
4
2-56
tOPRR
Condilions of measuremenl conlrol oulput C L = 80pF dala bus oulput, port oulpul CL = 150pF
Reference levels for Input/oulput voltages are low-level = O. 8V high-level = 2V
• MITSUBISHI
. . . . ELECTRIC
ns
420
210
ns
ns
MITSUBISHI MICROCOMPUTERS
MSL8049HI-XXXP/MSL8039HLP-14
SINGLE-CHIP 8-BIT MICROCOMPUTER
TYPICAL CHARACTERISTICS
DATA BUS HIGH-LEVEL
OUTPUT VOLTAGE VS. HIGH-LEVEL
OUTPUT CURRENT
:;
3.8
I
~
w
C!l
~
..J
~
I::::l
0I::::l
o
3,4
w
~ ...............
-
3.2
--
..J
~
~
0.3
~
o
>
W
3.0
..J
0.2
0.1
~
:i:.
C!l
:c
-0.2
-0.4
-0.6
-0.8
HIGH-LEVEL OUTPUT CURRENT
1/
-1.0
"'-. i'...
::;:
T8 = 25·C
'"~
w
C!l
«'
I..J
0
>
I::::l
0-
~
..J
W
>
W
..J
:::0
..J
:;
::;:
~
..J
0
>
'" l\
I::::l
-0. 15
-0.2
-0.25
-0.3
LOW-LEVEL INPUT CURRENT
1\
~
..J
:::0
..J
o
o
-0. 35
Vce=5V
'0
1.6
.E
()
1.2
~
0-
0::::l
en
cw
1.0
N
a:«
::;:
~
1.4
w
0.8
."
Z
w
-0.08
()
-0. 1
1,(mA)
1.4
,
1.2
~
0-
0::::l
............
I'--:--....
en,
cw
I ............
1. 0
I'-.......
...............
N
r-.
a:
«
::;:
0.8
:--....
II:
o
Z
0.6
25
o
25
50
AMBIENT TEMPERATURE
2-58
-0.06
Vee = 5V
Voo = 5V
II:
II:
::::l
II:
o
-0.04
NORMARIZED SUPPLY CURRENT (Joo)
VS. AMBIENT TEMPERATURE
Voo=5V
Z
-0. 02
LOW-LEVEL INPUT CURRENT
1,(mA)
NORMARIZED SUPPLY CURRENT (Jed
VS. AMBIENT TEMPERATURE
II:
II:
::::l
\\
>
W
1.6
I-
Vee = 5V
Ta = 25"C
"\,
..J
W
o
IOL(mA)
RESET LOW-LEVEL INPUT
VOLTAGE VS. LOW-LEVEL
INPUT CURRENT
0-
\
-0. 1
4
w
C!l
10
8
LOW-LEVEL OUTPUT CURRENT
IOH(mA)
Vee=5V
/
6
5
5
V
o
o
P 1 • P2 LOW-LEVEL INPUT
VOLTAGE VS. LOW-LEVEL
INPUT CURRENT
:;
V
I::::l
::::l
V
Ta=25"C
0.4
..J
W
..J
~
W
Vee=5V
~
Ta=25"C
..........
0.5
S
Vee=5V
3.6
~
DATA BUS LOW-LEVEL
OUTPUT VOLTAGE VS. LOW-LEVEL
OUTPUT CURRENT
75
100
0.6
-25
Ta("C)
25
50
AMBIENT TEMPERATURE
• MITSUBISHI
;"ELECTRIC
---
75
Ta("C)
100
MITSUBISHI MICROCOMPUTERS
SERIES .MELPS 8-41 SLAVE MICROCOMPUTERS
FUNCTIONS OF SERIES MELPS 8·41 SLAVE MICROCOMPUTERS
BASIC FUNCTION BLOCKS
Program Memory (ROM)
The M5L8041 A-XXXP contains a 1024-byte ROM while the
M5L8042-XXXP has a built-in 2048-byte ROM. The program
for the user application IS stored in this ROM. Addresses 0,
3 and 7 of the ROM are reserved for special functions.
Table 1 shows the meaning and functions of these special
addresses.
Table 1 Reserved, defined addresses
and their meanings and functions
Meamng and functton
Address
0
3
7
The first instruction executed after a system reset
The first instruction executed after an external Interrupt IS
accepted
The first instruction executed after a timer mterrupt,
based on the timer/event counter, IS accepted.
Data Memory (RAM)
A good practice to simplify programming is to reserve
general-purpose register bank 0 for use of the main program and register bank 1 for interrupt programs. For example, if register bank 0 (addresses O~?) is reserved for processing data by the main program, when an interrupt is
accepted, the first instruction would be to switch the working registers from bank 0 to bank 1. This saves the data of
the main program (addresses O~?). The interrupt program
can then freely use register bank 1 (addresses 24 ~ 31 )
without destroying or altering data of the main program.
When the interrupt processing is complete and control is
returned to the main program by the RETR instruction, register bank 0 (in this example) is automatically restored as
the working register bank at the same time the main program counter is restored.
Addresses 8 ~ 23 comprise an 8-level program counter
stack. More information on using the stack is found in the
section on the program counter and stack and so reference
should be made here for further details.
The general-purpose registers and program counter stack
sections may be used in exactly the same way as the other
RAM sections.
The M5L8041 A-XXXP has a built-in 54-byte (128 bytes for
M5L8042-XXXP) RAM. The RAM is used for data storage
and manipulation and it is divided into sections for more
efficient processing. Addresses 0 ~ 7 and 24 ~ 31 form two
banks of general-purpose registers that can be directly
addressed. Addresses O~ 7 compose bank 0 and are numbered Ro~R7' Addresses 24~31 compose bank 1 and are
also numbered Ro~ R7. Only one bank is active at a time.
The instructions SEL RBO and SEL RB1 are used to select
the working bank. Fig. 1 shows the division of the RAM and
its mapping. The remaining sections, addresses 32 and
above, must be accessed indirectly using the generalpurpose registers Ro or R,. Of course, all addresses can be
indirectly accessed using the general-purpose registers Ro
and R,.
(Note 3)
User RAM
32XB
32
(Note4)
31
R7
I
I
I
I
I
25
R,
24
Ro
1
1
General-purpose
reglsters/Register bank 1
23
B-Ievel stack
16x8
R7
I
I
I
General-purpose
) registers/Register bank 0
R,
RO
Flg.l
Data memory (RAM)
Note 3 : The corresponding address IS 127 for the M5L8042-XXXP
4 : The corresponding capacity is 96 X 8 for the M5L8042-XXXP
3-4
• MITSUBISHI
"-ELECTRIC
MITSUBISHI MICROCOMPUTERS
SERIES MELPS 8-41 SLAVE MICROCOMPUTERS
FUNCTIONS OF SERIES MELPS 8-41 SLAVE MICROCOMPUTERS
Program Status Word (PSW)
I/O PortS·
The PSW (program status word) is stored in 8 bits in the
register storage. The configuration is shown in Fig. 4. The
high-order 4 bits of the PSW are stored in the stack, along
with the PC, when an interrupt is accepted or a subroutine
call executed. When control is returned to the main program by RETR, both the PC and the high-order 4 bits of PSW
are restored. When control is returned by RET, only the PC
is restored, so care must be taken to ensure that the contents of the PSW are not unintentionally changed.
The order and meaning of the 8 PSW bits are given below.
BitO-Bit2 : Stack painter (So, Sl, S2)
Bit 3
: Not used
Bit 4
: Working register bank indicator
0= BankO
1 = Bank 1
Bit5
Flag 0 (value is set by user and can be
tested with JFO conditional jump instruction.)
: Auxiliary carry bit (AC). It is set/reset by the
Bit6
ADD and ADDC instructions and used by the
DAA decimal compensation instruction.
: Carry bit (CY). This indicates an overflow afBit 7
ter an arithmetic or logic operation.
The S~ries MELPS 8:41 has two 8-bit ports, called port 1
and port 2.
(1) Port 1 and port 2
Ports 1 and 2 are both 8-bit ports with identical properties. The output data of these ports are retained and
do not change until another output is loaded into them.
When used as inputs, the input data is not retained so
the input signals must be maintained until an input instruction is executed and completed.
Ports. 1 and 2 are so-called quasi-bidirectional ports
which have a speCial circuit configuration to accomplish this purpose. All the pins of the ports can be used
for input or for output.
sv
CPU internar-+--I
bus
PORT 1
IPORT 2
PINS
Reset-+---i
Write pulse--f---_----'
High-order 4 bits are stored along with PC In stack.
Flg.5
I I I I
Cy
Cy
AC
Fo
BS
:
:
:
:
AC
Fo
BS
11
Flg.4
3-6
I I I I
Sz
Sl
So
Carry
Auxiliary carry ~ carry from low-order 4 bits of ALU)
Flag 0
Working register bank indicator
Sz }
S 1 Stack pointer
So
Program status word
1/0 port 1 and 2 circuit
The speCial circuit is shown in Fig. 5. Internal on-chip
pull-up resistors are provided for all the ports for pullup to 5V. The current required for setting the TTL signal high can be supplied through these pull-up resistors. In addition, the level can be pulled low by the
standard TTL output. This means that any pin can be
used for both input and output.
To shorten the switching time from a low level to high
level, when 1's are output, a device with a relatively low
impedance is turned on for a short time (approx. 500ns
when a 6MHz crystal oscillator is used).
To use a particular port pin as an input, a logic "1"
must first be written to that pin. After resetting, a port is
set to an input port and remains in this state.
Therefore, it is not necessary to output all 1's if it is to
be used for input. In short, a port being used for output
must output 1's before it can be used for input.
•
MITSUBISHI
~ELECTRIC
MITSUBISHI MICROCOMPUTERS
SERIES MELPS 8-41 SLAVE MICROCOMPUTERS
FUNCTIONS OF SERIES MELPS 8-41 SLAVE MICROCOMPUTEIJS
Fl (flag 1)
When the data or command is input into the input datal
command bus buffer by the master CPU, the Fl flag is set
to the condition of the Ao input.
The Fl flag is also set by the flag setting instructions (CPL
Fl , CLR Fl ).
• Output Data Bus Buffer Register
The accumulator (A) contents are transferred to the DBB
(0) output data bus buffer register by the OUT DBB, A instruction. Since the OBF flag is set at this time, the master
CPU can judge whether the data has been transferred to
the register by confirming the state of the OBF flag.
• Input Data/Command Bus Buffer(DBB(l)) Register
When the write request (W =0) is g~nerated from the master CPU, the data on the data bus is transferred to the DBB
(1) input data/command bus buffer register. Since the IBF
flag is set at this time, it is possible to judge whether the
data or command has been transferred inside the Senes
M ELPS 8-41 by confirming the state of this flag.
The unconditional jump instructions for enabling a jump to
be made to Jh~ address where the ordinary interrupt processing program is stored are contained in address 3 of the
program memory.
The interrupt level is one so that the next interrupt cannot
be accepted until the current interrupt processing has been
completed. The RETR instruction terminates the interrupt
processing. That is to say, the next interrupt cannot be
accepted until the RETR instruction is executed. T~e next
interrupt can be accepted at the start of the second cycle
of the RETR instruction (2-cycle instruction). Timer/event
counter overflow which causes an interrupt request will also
not be accepted .
Priority is given to the external interrupt when both an external interrupt and timer interrupt have been generated at
the same time.
Conditional Jumps Using Pins To, T1
and Flags IBF, OBF
The conditional jump instructions are used to alter programs, depending on the internal and external conditions
(states) of the CPU. Details of the jump instructions can be
found in the section on machine instructions.
The input signal status of pins To and Tlo and the states of
the IBF and OBF flags can be checked by the conditional
jump instructions. These input pins, through conditional
jump instructions such as JTO and JNTO, can be used to
control a program. This means that programs and processing time can be reduced by being able to test data in the
input pin rather than reading the data into a accumulator
and then testing it.
Pin Tl has other functions and uses which are not related to
conditional jump instructions. Details of these other functions and uses can be found on the section dealing with pin
functions.
Interrupt
(j)TIMER INTERRUPT ENABLE FF (TCNTF)
®TIMER INTERRUPT REQUEST FF (TIRF)
@EXTERNAL INTERRUPT LATCH
®EXTERNAL INTERRUPT ENABLE FF (INTF)
@INTERRUPT ENABLE FF (IEF)
@INTERRUPT ACKNOWLEDGE FF
CZlEXTERNAL INTERRUPT PENDING FF (EIPF)
Fig.8
Interrupt control section configuration
The CPU recoJlnizes ~n external interrupt by a low-level
signal at the Sand W pins. When such an interrupt is
accepted, the external interrupt pending flip-flop and IBF
flag are set.
Interrupt requests are sampled between the SYNC signa"
outputs of every machine cycle. When a request is recognized, then as soon as the instruction being executed is
terminated, a subroutine call is made to address 3 of the
program memory. As with ordinary subroutine calls, the
program counter and program status word (PSW) are saved
in the program counter stack.
3-8
•
MITSUBISHI
. . . . ELECTRIC
MITSUBISHI MICROCOMPUTERS
SERIES MELPS 8-41 SLAVE MICROCOMPUTERS
FUNCTIONS OF SERIES MELPS 8-41 SLAVE MICROCOMPUTERS
2 5.us (when uSln9 a6MHz crystal)
Instruciton cycle
1
X tal
asc
55
TIMER
OVERFLOW
51
52
Instruction
decode,
Instruction program
fetch
counter
renewal
53
1
54
1
55
51
1
Instruction execution
TIMER
FLAG (TF)
s a
Fig.12
Reset
Incremented
EDGE
Flg.9
Instruction execution timing
DETECTOR
Timer/event counter configuration
Cycle Timing
+
The output of the state counter is
the input frequency
from the oscillator, and a ClK signal is produced which determines the times of each machine state (see Fig. 10) .
During the cycle count the ClK signal is prescaled by
and a machine cycle containing 5 states is produced. The
Series MElPS 8-41 instructions are executed in one or two
machine cycles. Fig. 12 shows the internal operation with an
instruction formed from one machine cycle.
+
The RESET pin is for resetting the CPU. A Schmitt trigger
circuit along with a pull-up resistor are connected to it on
the chip. A sufficiently long pulse can be obtained for resetting by attaching 1I" F capacitor ~shown in Fig. 13. An
external reset pulse applied at RESET must remain at the
low level for at least 10ms after the power has been turned
on and after it has reached its normal level.
The reset function causes the following initialization within
the CPU.
(1) The program counter is reset to O.
(2) The stack pointer is reset to O.
(3) The register bank 0 is selected.
(4) Ports 1 and 2 are reset to the input mode.
(5) External and timer interrupts are reset to disable state.
(6) Timer is stopped.
(7) Timer flag is cleared.
(8) Flags Fa and Fl are cleared.
SERIES MELPS
8-41
Fig.10
5V
Clock generator circuit
I--- 10- 500ns(when using a6MHz crystal)
51
Internal
clock
5YNC
52
53
54
55
51
52
53
54
+1.u F
55
7fr 10V
f--n- ~ ~ f-.n- --fL I--n. f--n- f.--n -IL -IL
.-- h
.--
~
-
Fig.13
PROG
Fig.ll
3-10
Clock and generated cycle signals
• MITSUBISHI
. . . . ELECTRIC
Example of reset circuit
MITSUBISHI MICROCOMPUTERS
SERIES MELPS 8-41 SLAVE MICROCOMPUTERS
FUNCTIONS OF SERIES MELPS 8-41 SLAVE MICROCOMPUTERS
Interrupt Request to Master CPU
P2,
ORQ
DRQn
M5L.82 57P
SERIES MELPS 8-41
P2,
Ports P2 4 and P2 5 of Series MELPS 8-41 can be used not
only as ordinary input/output ports but also as the outputs of
the ISF (input buffer full) flag and OSF (output buffer full)
flag. Immediately after resetting, both ports function as input ports.
OM A
DACK
DACKn
SERIES MELPS 8-41
OSF
Flg.16
OMA control
P2 4
When the EN DMA instruction is executed, P2s becomes
the ORO (OMA request) output. Subsequently, when P2s is
set to "1", ORO becomes "1" and DMA-based data transfer
is requested.
-- --- DRO is cleared when the OACK • R, DACK • W or EN DMA
instruction is executed.
<10 ('nte_rn_a_'_ _ _--j
EN DMA
P26!DRQ
--..----{""'"'
OSF
Interrupt request
} to master CPU
P2 5
ISF
Fig.18
Interrupt request to master CPU
When the EN FLAGS instruction is executed, P2 4 functions
as the OSF pin and P2 5 as the ISF pin. "1" must be output
to both pins so that the OSF and ISF flag states are output
to each pin, respectively. These states are not output while
"0" is output to the pins. The OSF flag output indicates that
data~s been output to the output data bus buffer register;
the ISF flag output indicates that the input data/command
bus buffer register is in the data accept enable mode.
RESET
OUTL
ANL
ORL
Fig.17
Internal configuration of OMA control
When the EN DMA instruction is executed, P2 7 becomes
the OACK (DMA acknowledge) input. The OACK input is
used as the chip select input for DMA transfer. There is,
therefore, no connection with the state of S (chip select)
during OMA transfer.
Fig.19
3-12
• MITSUBISHI
"-ELECTRIC
Internal configuration of IBF/OBF
MITSUBISHI MICROCOMPUTERS
SERIES MELPS 8·41 SLAVE MICROCOMPUTERS
FUNCTIONS OF SERIES MELPS 8-41 SLAVE MICROCOMPUTERS
MACHINE INSTRUCTIONS
S
Instruction code
"'
" "0">-
"'
;;:,
Mn~monfc
D7 D
Type
MOV A, *I n
6
DSD4
D3 D 2D,Do
0 0 1 0
n7 n6 n5 n4
0
1
0
1
0
0
n
1
0
n
3
1
2 "1
1
n
1
()
2
2
(A)-n
1
1
(A)-(PSW)
1
1
(A)-(Rr)
r=0-7
1
1
(A)-(M(Rr))
r=0-1
1
1
(PSW)-(A)
(C) - (A7), (A C) -
1
1
(STS)-(A)
(ST4 - ST7) -
1
1
(Rr)-(A)
r= 0-7
2
2
(R,)-n
,=0-7
1
1
(M(R'))-(A)
,=0-1
2
2
(M(Rr))-n
r=0-1
1
2
(A)-(M(A))
1
2
(A) -
+
r
1
1
(A)-(Rr)
r=0-7
0
r
1
1
(A)-(M(Rr))
r=0-1
1
1
(Ao - A3) - (M (Rro ,=0-1
2
2
(A)-(A)+ n
1
1
(A) - (A) + (Rr)
,=0-7
1
1
(A) - (A) + (M (Rr) )
,=0-1
2
2
(A)-(A)+ n +(C)
3
2
n
O
1
7
C
MOV A, PSW
1
1
1
1 r
1
2
r
1
r
8
F
0
+r
MOV A, Rr
1
1
1
1
0
0
0
r
0
F
0
+
MOV A, @Rr
r
1
1
0
1
1
0
1
1
7
D
MOV PSW, A
1
0
1
0
0
0
0
0
9
0
MOV STS, A
1
1
0
0
1 r
2
r
1
r
8
A
0
+
MOV Rr, A
r
, ,
MOV Rr, *In
1
0
n 7 n6 n5 n4
1 r 2 r 1 r 0
n3 n 2n,nO
Function
III
Hexadecimal
8
B
,
+
(AB)
(A4 -
A7)
n
1
1
0
0
0
0
0
r
A
0
MOV @Rr, A
1
MOV @Rr, *In
n
7
,
0 1 1
n6 n5 n4
0
0
r
0
"3
n 2 n ,n
O
0
0
0
1
0
0
B
0
n
,
1
--
0
+
r
+r
3
A
MOVP A, @A
1
1
1
0
1
0
0
1
3
E
MOVP3 A, @A
0
0
1
0
,
r
2
r
1
r
8
2
0
XCH A, Rr
0
0
1
0
0
0
0
r
2
0
+
XCH A, @Rr
0
1
0
1
0
0
r
0
3
0
0
+r
XCHD A, @Rr
0
0
ADD A, *In
0
0
n7 n6 n5 n4
1
0
1
0
0
0
1
1
0 3 0 2 0,0 0
1 r
2
r
1
r
0
0
3
n
1
(M (page 3, A))
8
6
+r
ADD A, Rr
0
-g
~
~
1
0
0
ADDC A, *In
3-14
1
0
0
0
0
r
0
6
0
+r
ADD A, @Rr
n
0
7
n
0
6
n
5
1
n
4
0
"3
, ,
0 1
n 2 n ,n
O
3
n
• MITSUBISHI
;"ELECTRIC
R(3))
MITSUBISHI MICROCOMPUTERS
S~RIES
MELPS 8-41 SLAVE :MICROCOMPUTERS
FUNCTIONS OF SERIES MELPS 8-41 SLAVE MICROCOMPUTERS
IS
.,
Instruction cOde
~
Mnemonic
D7 D • D s D 4
Type
0
1
1
1
D3 D 2D, D O
1 r
2
r
1
ra
1
1
1
0
0
0
r
0
1
1
(A) - (A)
r=0-7
1
1
(A) - (A)
r=O-1
2
2
(A)-(A) An
1
1
(A) - (A) 1'1 (Rr)
r=0-7
1
1
(A) - (A) A (M (Rr) )
r= 0-1
2
2
(A)-(A)V n
1
1
(A) - (A) V (Rr)
r=0-7
1
1
(A) - (A) V (M (Rr) )
r=O-1
2
2
(A)-(A)¥n
1
1
(A) - (A)¥ (Rr)
r=I-7
+r
1
1
(A) - (A)¥ (M (Rr) )
r=O-1
1 7
1
1
(A)-(A)
07
1
1
(A)-(A)-1
2
7
1
1
(A)-O
3
7
1
1
(A)-O>:)
5
7
1
1
(A) -
(A) DeCimal Conversion
4
7
1
1
(A, -
A, ) -
E
7
1
1
(An+l ) - (An)
(Ao)-(A7) n=0-6
F
7
1
1
(An+1) - (An)
(Ao)-(C)
(C)-(A7) n=0-6
7
8
+r
7 0
+r
ADDC A. @Rr
0
ANLA.#n
1
0
1
"7"6"5"4
0
1
0
1
1
0
0
1
2
r
1
r
0
n
5 8
+r
ANL A. Rr
0
1
0
1
0
0
0
r.
5
0
+r
ANL A. @Rr
0
ORL A. # n
1
0
0
"7"6"5"4
0
1
0
0
0
1
0
1
2
r
1
r
0
n
8
4
+r
ORL A. Rr
0
1
0
0
0
0
0
r.
4
0
+r
ORL A. @Rr
1
,
XRL A. # n
1
0
1
0
0
1
1
"7"6"5"4
"3"2"1"0
1
1 r
1
0
1
2
r
1
ra
1
0
1
0
0
0
r.
n
D
D
XRL A. @Rr
0
0
0
1
0
1
1
0
0
0
0
1
1
1
0
0
1
1
1
0
1
0
1
1
1
CPL A
'0
1
DA A
0
1
"
0
0
1
0
0
0
1
1
1
1
1
1
SWAP A
1
1
1
0
0
1
1
+1
1
CLR A
0
0
1
DEC A
0/0
8
+r
1
INC A
0
3
D
XRL A, Rr
1
+ (M (Rr) ) + (C)
3
4
"3"2"1"0
1 r
+ (Rr) + (C)
5 3
"3"2"1"0
1 r
Function
(.)
Hexadecimal
AD DC A. Rr
0
'"
"
~
III
1
RL A
(Ao -
A3 )
"
1
FlLC A
3-16
1
1
1
0
1
1
1
• ' MITSUBISHI
..... ELECTRIC
MITSUBISHI MICROCOMPUTERS
SERIES MELPS 8-41 SLAVE MICROCOMPUTERS
FUNCTIONS OF SERIES MELPS 8-41 SLAVE MICROCOMPUTERS
I,S
Instruction code
D?D6 D S D
Type
0
"
~
1
1
4
1
D3 D 2D,Da
0
1
1
1
Hexadecimal
7
0
1
1
0
0
1
1
1
""'
6
>.
()
1
1
1
1
7
RRC A
Function
"0
OJ
7
RR A
E
£
~
~
~
Mnemonic
"
0
0
1
1 f2r,rO
+
INC Rr
r
~
E
£
iij
0
*
c;,
0
1
0
0
0
r 0
1
1
0
0
1
DEC Rr
J8b m
'2','0
+
r
0
1
0
b?b.b s l
0
m7 m Sm Sm 4
rnSm2m,mO
1
0
b
0
1
1
1
(M(Rr)) ~ (M(Rr))+ 1
r=0-1
1
1
(Rr) ~ (Rr)- 1
r=0-7
2
2
When (Ab)= 1 , (pCa-PC?) ~ m
When (Ab)= 0 , (PC) ~ (PC)+ 2
b?b6bs= 0 -
m7 m e m Sm 4
J08F m
m7 m Sm S m 4
ma m 2m,mO
1
JTF m
m7 m Sm Sm 4
0 1 1 0
rnSm2rn,rnO
JMP m
m1Q m 9 m S O
m7 m Sm Sm 4
rnam2m,rnO
0
0
0
0
0
0
m3 m 2m,mO
D
0
8
0
1
1
7
0
JNI8F m
1
n= 0-6
1
m
1
(Ao)
1
2
1
+
~
1
8
C
(An+,)
(A?)~(C)
1
0
+
r
1
Q)
c::
0
INC @Rr
~
(An+,)
(Ao) n=O-6
(Rr) ~ (Rr)+ 1
r= 0-7
8
1
~
(An)
(C)
0
~
(An)
(A?)
1
0
0
0
6
~
2
2
When (18F)= 0, (PCo-PC?)
m
2
2
When (OBF)= 1 , (PCa-PC?)
2
2
When (TF)= 1 , (PCa-PC?) ~ m
When (TF)= 0 , (PC) ~ (PC)+ 2
2
2
(pCB- PC,a) ~ mB-m,a
(PCa- PC?) ~ ma- m?
1
2
2
2
2
2
When (C)= 1 , (PCa-PC?) ~ m
When (C)= 0 , (PC) ~ (PC)+ 2
2
2
When (C)= 0, (PCa-PC?) ~ m
When (C)= 1 , (PC) ~ (PC)+ 2
2
2
When (A)= 0, (PCo-PC?) ~ m
When (A)4= 0 , (PC) ~ (PC)+ 2
2
2
When (A)4= 0, (PCa-PC?) ~ m
When (A)= 0 , (PC) ~ (PC)+ 2
2
2
When (Ta)= 1 , (PCa-PC?) ~ m
When (Ta)= 0, (PC) ~ (PC)+ 2
6
m
6
1
m
4
0
+
rns ..... ,o
~
m
1
0
1
1
0
0
1
1
JMPP @A
1
"-
E
DJNZ Rr, m
1
1
0
rn7rnSrnSrn4
1
'2','0
+
r
m
1
1
1
1
JC m
m7 m S m Srn 4
JNC m
m7 m Sm Sm 4
JZ m
m7 m Sm Sm 4
JNZ m
m7 m Sm Sm 4
JTO m
m7 rn e m Srn 4
JNTO m
m7 m Sm Sm 4
JT1 m
m7 rn S m Srn 4
1
1
1
0
0
0
3-18
8
E
rn3m2rn,rnO
~
1
1
0
0
0
1
1
0
0
1
1
0
0
0
1
1
0
1
0 1 1 0
mSm2m,mO
F
0
E
0
1
1
6
m
ma m 2m,mO
0
1
1
0
1
1
0
1
1
0
m
9
1
1
0
3
0
1
1
0
6
m
2
ma m 2m,mO
mSrn2m,mO
6
m
m3 m 2rn,mO
0
6
C
rnarn2m,mO
0
6
m
m3 m 2m,mO
0
(PC a- PC?)
3
8
6
2
m
12
6
5
m
2
• MITSUBISHI
"ELECTRIC
2
~
(M(A))
(Rr) ~ (Rr)- 1 r= 0-7
When (Rr)4= 0, (PCa-PC?) ~ m
When (Rr)= 0 , (PC) ~ (PC)+ 2
When (To)= 0, (PCa-PC?) ~ m
When (T 0)= 1 , (PC) ~ (PC)+ 2
When (T,)= 1 , (PCo-PC?) ~ m
When (T,)= 0, (PC) ~ (PC)+ 2
m
MITSUBISHI MICROCOMPUTERS
SERIES MELPS 8-41 SLAVE MICROCOMPUTERS
FUNCTIONS OF SERIESMELPS 8-41 SLAVE MICROCOMPUTERS
IS
Instruction code
Mnemonic
Type
6
1
0
D5D•
0
0
D3 D 2D, D a
0
1
1
0
JNT1 m
rn 7 m e,m S m,4
JFO m
rn7rnernSrn4
rnarn2m,mO
0
JF1 m
m7 m e m Sm 4
0 1 1 0
rn 3 rn 2 rn,m O
1
a.
...,~
0
1
0
1
1
1
0
1
1
1
0
1
1
0
0
0
1
1
1
1
0
Function
0
1
0
0
4
0
1
1
0
1
lD
()
2
2
When (T,)= O. (PC a-PC7) ~ m
When (T,)= 1 . (PC) - (PC)
2
2
2
When (Fa)= 1 . (PCa-PC7) ~ m
When (Fa)= 0 . (PC) ~ (PC)
2
2
2
When (F,)= 1 . (PC a-PC7) ~ m
When (F,)= O. (PC) ~ (PC)
2
6
m
6
B
m
7
6
m
+
+
+
1
9
7
1
1
(C)~O
A
7
1
1
(C)~(C)
8
5
1
1
(Fa)~O
1
CPL C
C
Hexadecimal
ma m 2m,mO
CLR C
"2
"'" "'">."
>.
D7 D
0
-
1
CLR Fa
0
()
'"
;:
El
--
0
1
0
1
0
0
1
1
CPL Fa
0
1
1
0
0
1
0
0
1
1
0
0
1
0
1
0
0
CALL m
m7 m e m S m 4
~e
0
1
0
0
rn3rn2rn,rnO
0
1
0
1
1
(Fa) ~ (Fo)
A
5
1
1
(F,)~O
B
5
1
1
(F,J ~
1
4
2
2
((SP)) ~ (PC)(PSW.-PSW 7)
(SP) ~ (SP)
1
(PC O-PC ,0 ) ~ m
1
CPL F,
m'Orng rn a 1
5
1
CLR F,
1
9
+
rns-rn,o
m
+
(SP)
1
RET
.g
(1=,)
~
(SP) -
1
8
3
1
2
(PC)~((SP))
9
3
1
2
(SP) ~ (SP) - 1
(PC)(PSW 4 -PSW7) ~ ((SP))
1
2
(A)-(Pp)
p=1-2
1
2
P=1-2
2
2
(Pp) ~ (Pp)A n
p=1-2
,2
2
(Pp) ~ (Pp)V n
p=1-2
1
1
(A)~(DBB)
1
1
(DBB)~(A)
rJ)
0
1
0
1
0
1
0
1
RETR
0
0
0
0
1 0
P
1
Po
8
0
+
IN A. Pp
P
0
0
1
1
1
0 P 1 Po
3
~
B-
6
Sa.
E
ANL Pp.#n
1
n
0
1
ORL pp. #n
0
1
7 "6"5"4
n7
0
"6
0
0
n5 n4
1 0
P
1
Po
9
"3 n 2",n O
1 0
P
1
Po
"3
n 2 n ,n
0
0
(Pp)~(A)
8
+
p
OUTL P p • A
8
+
n
8
P
8
+
p
O
n
0
0
1
0
1
0
2
2
IN A. DBB
0
OUT DBB. A
3-20
0
0
0
0
0
1
0
0
2
• MITSUBISHI
;"ELECTRIC
MITSUBISHI MICROCOMPUTERS
SERIES MELPS 8-41 SLAVE MICROCOMPUTERS
FUNCTIONS OF SERIES MELPS 8-41 SLAVE MICROCOMPUTERS
S
Instruction code
~
Mnemonic
0 70
Type
0
6
0
0
5
0
0.
0
0 30
2
0,0 0
1 1 P, Po
Hexadecimal
0
MOVD A, Pp
~
0
0
1
1
1 1 P, Po
ID
*'
()
1
2
1
2
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
+
P,Po
3 C
+
MOVD Pp, A
0
()
~
",.,
P,Po
Function
"0
(Ao':"'A3) (A.~A7) -
(PpO~Pp3)
0 p=4~7
(PpO~Pp3)
-
(Ao~A3)
-
(Ppo~Pp3)J\(Ao~A3)
-
(Ppo~Pp3)V(Ao~A3)
P=4~7
iii
u
.,a.c
1
0
0
1
1 1 P, Po
9
ANlO Pp, A
><
w
~
1
0
0
0
1 1 P, Po
+
8 C
+
ORlD Pp, A
P,Po
0
0
0
0
0
1
0
1
0
0
0
1
0
1
0
1
1
1
0
0
0
1
0
1
C
1
1
0
1
0
1
0
1
D
1
1
1
0
0
1
0
1
E
1
1
1
0
1
0
1
F
5
EN FLAGS
MOV A, T
MOV T, A
~
STRT T
(BS) - 1
5
EN DMA
1
(BS)-O
5
SEl RB1
0
(INTF) -
5
SEl RBO
p=4~7
(INTF)-1
1 5
DIS I
p=4~7
(PpO~Pp3)
5
EN I
0
(PpO~Pp3)
C
P,Po
0
1
0
0
0
0
1
0
4
2
0
1
1
0
0
0
1
0
6
2
0
1
0
1
0
1
0
1
5 5
0
1
0
0
0
1
0
1
4
5
0
1
1
0
0
1
0
1
6
5
0
0
1
0
0
1
0
1
2 5
0
0
1
1
0
1
0
1
3 5
0
0
0
0
0
0
0
0
0
(P2.) (P2 5 ) -
(OBF)
(IBF)
(A)-(T)
(T)- (A)
0
()
.&c
STRT CNT
"0
~
"
E
,::
STOP TCNT
EN TCNTI
DIS TCNTI
"
~
NOP
~
Note 1
2
3-22
0
(TCNTF) -
1
(TCNTF) -
0
Executing an instruction may produce a carry (overflow or underflow) The carry may be lost or it may be transferred to C or AC The (0)
mark Indicates a carry which affects C or AC The detail affection of carnes for instructions ADD, AD DC and DA is as follows
(C) - 1 At overflow of accumulator
( C) - a At no overflow of accumulator
(A C)- 1 At ovelilow of bit 3 of accumulator
(A C)- 0 At no overflow
The contents of ST,-ST7 are read when host computer reads status of MELPS 8-41.
• MITSUBISHI
...... ELECTRIC
MITSUBISHI MICROCOMPUTERS
SERIES MELPS8-41 SLAVE MICROCOMPUTERS
FUNCTIONS OF SERIES MELPS 8·41 SLAVE MICROCOMPUTERS
Item
Details of execution
TF (Timer Flag) - 0
TIRF (Timer INT Request FF) - 0
TCNTF (Timer INT Enable FF) - 0
RESET input low level
INTF (ExternallNT Enable FF)-O
IEF (INT Enable FF)-1
IBF-O
EIPF (External Interrupt Pending FF) - 0
JTF execution
TF (Timer Flag) - 0
Timer/event Counter
TF (Timer Flag) - 1
TCNTE (Timer INT Enable FF) = 1 When TIRF (Timer INT Request FF) -1
-",,-e rll ow
EN TNCTI execution
TCNTF (Timer INT Enable FF) - 1
DIS TNCTI execution
TCNTF (Timer INT Enable FF) - 0
EN I execution
INTF (ExternallNT Enable FF)-1
DIS I execution
INTF (ExternallNT Enable FF) - 0
RETR execution
IEF (INT Enable FF)-1
Symbol
Symbol
Contents
Contents
A
8-blt register (accumulator)
PC
Program counter
Ao-A3
Low-order 4 bits of register A
PC O-PC 7
Low-order 8 bits of program counter
A 4 -A 7
High-order 4 bits of register A
PC B -PC1Q
High-order 3 bits of program counter
Ao-A n , A n +,
81ts of register A
PSW
Program status word
b
Value of bits 5-7 of first byte machine code
Rr
Register designator
b7 b6 b5
Bits 5-7 of first byte machme code
r
RegIster number
BS
RegIster bank select
ro
Value of bit
AC
AuxilIary carry flag
r2'l'O
Value of bits 0-2 of machine code
C
Carry Ilag
828 1 8 0
Value of bits 0-2 of stack pOinter
DBB
Data bus buffer
SP
Stack pomter
aof machine code
Fo
FlagO
ST4 ST 7
Bits 4-7 of status register
F,
Flag 1
STS
System status
INTF
External Interrupt enable flip-flop
T
Timer/event counter
IBF
Input buffer full flag
To
Test pm
m
Destmatlon address
T,
Test pin 1
Timer/event counter Interrupt flip-flop
a
Second byte (low-order 8 bits) machine code
TCNTF
corresponding to destmatlon address
TF
Timer flag
m10mgma
Bits 5-7 of first byte (high-order 3 bits) machine code
:f:j:
Symbol to mdlcatp Immediate data
(M(A»)
Content of memory location addressed by register A
@
Symbol to Indicate content of memory location
(M(Rr»)
Content of memory location addressed by register Rr
(Mx(Rr))
Content of external memory location addressed by
m7mSmSm4m3m2m1 mo
addressed by register
n
Value of Immediate data
--
n7n6n5n4n3n2n1 no
Immediate data of second byte machine code
/I
Logical AND
OBF
Output buffer full flag
V
Logical OR
p
Port number
Exclusive OR
Pp
Port deSignator
'V-
P,Po
Bits of machine code corresponding to port number
0
Content of flag is set or reset after execution
register Rr
3-24
(
Shows direction of data flow
Exchanges contents of data
)
• MITSUBISHI
. . . . ELECTRIC
Contents of register, memory location or nag
Negation
MITSUBISHI MICROCOMPUTERS
MSL8041A-XXXP
SLAVE MICROCOMPUTER
FUNCTION
The M5L8041 A-XXXP is designed as an ordinary 8-bit CPU
peripheral LSI chip and it contains a small stand-alone microcomputer. Although this microcomputer functions independently, when it is used as a peripheral controller, it is
called the slave microcomputer in contrast to the master
computer. These two devices can transfer the data alterna-
tively through the buffer register between them. The
M5L8041 A-XXXP contains the buffer register 10 use Ihis LSI
as a slave microcomputer and it can be accessed in Ihe
same way as other standard peripheral devices. Since the
M5L8041 A-XXXP is a complete microcomputer, it is easy to
develop a user-oriented mask-programmed peripheral LSI
only by changing the control software.
PIN DESCRIPTION
Pin
Name
Ground
Vee
Main power supply
-
Voo
Power supply
-
To
Test pm 0
Input
X,. X 2
Crystal mputs
Input
RESET
Reset
Input
SS
Single step
Input
CS
Chip select input
Input
EA
External access
Input
-
Function
Input or output
Vss
R
Read enable Signal
Input
Ao
Address Input
Input
~
W
Wnte enable Signal
Input
SYNC
Sync Signal output
Output
DQo-DQ7
Data bus
Input/output
P2 o-P2 7
Port 2
Input/output
PROG
Program
Connected to a OV supply (ground)
Connected to a 5V supply
Connected to a 5V supply
Used' as a memory hold when Vee is cut off
Provides external control of conditional program Jumps (JTO/JNTO instructions).
An internal clock Circuit IS provided so that by connectmg an RC Circuit or crystal to these input pms the
clock frequency can be determmed. Pins X 1 and X2 can also be used to mput an external clock signal
CPU initialization mput.
Used to halt the execution of a command by the CPU When used
In
combination with the SYNC signal,
the command executron of the CPU can be halted every instruction to enable Single step operation
Chip select mput data bus control
Normally maintained at OV
Serves as the read Signal when the master CPU IS accepting data on the data bus from the M5L8041A-
XXXP.
An address mput used to mdlcate whether the Signal on the data bus is data or a command
Serves as the write Signal when the master CPU IS outputtmg data from the bus to the M5L8041A-
XXXP
Output 1 time for each machine cycle.
Three-state, bidirectional data bus, Data bus IS used to mterface the M5L8041A-XXXP to a master system data bus.
Qualsi-bidlrectlonal port When used as an Input port, FF16 must first be output to thiS port.
After resetting, however, when not used afterwards as an output port, this IS not necessary.
P2 0 -P2 3 are used when the M5L8243P 1/0 port expander IS used
Pl o-P1 7
Port 1
T,
Test pm 1
3-26
Output
Input/output
Input
Serves as the strobe Signal when the M5L8243P 110 expander IS used
Qualsi-bldlrectlonal port When used as an Input port, FF,6 must first be output to this port.
After resettmg, however, when not used afterwards as an output port, thiS is not necessary
Provides external control of conditional program Jumps (JTl IJNTl Instructions).
Can serve as the input pm for the event counter (STRT CNT instructions)
•
MITSUBISHI
...... ELECTRIC
MITSUBISHI MICROCOMPUTERS
MSL8041A-XXXP
SLAVE MICROCOMPUTER
TIMING REQUIREMENTS
DBB Read
Symbol
(Ta
=
-20-75t:, Vee
Parameter
= 5V±10%,
unless otherwise noted)
Alternative
Test conditions
symbol
Limits
Min
Typ
Max
Unit
Cycle time
Icy
IW(R)
Read pulse with '
IRR
tsu
Chip-select setup time betor read
tAR
0
ns
Chip-select hold time after read
tRA
0
ns
te
(¢»
(CS-A)
th (R-CS)
2,5
te (;1
= 2,511S
15
250
f.LS
ns
DBB Write
Symbol
Parameter
tw(w)
Write pulse width
tsu (cs-w)
-
tsu
Alternative
Test conditions
symbol
limits
Min
Typ
Max
Unit
tww
250
ns
tAw
0
ns
es. Ao, hold time after wlrte
tWA
0
ns
Data setup time before write
tow
150
ns
Data hold time after write
two
0
ns
es, ~.
setup time before write
(AO-W)
th (w-cs)
th (W-AO)
tsu
(DQ-W)
th (W-OQ)
-
Port 2
Alternative
Symbol
Parameter
Test conditions
symbol
Limits
Min
Typ
Max
Umt
PROG pulse width
tpp
1200
ns
Port control setup time before PROG
tcp
CL = BOpF
110
ns
th (PR-PC)
Port control hold time after PROG
t pc
CL - 20pF
100
ns
tsu
(Q-PR)
Output data setup time before PROG
top
CL - BOpF
250
ns
tsu
(O-PR)
Input data hold timer before PROG
t pR
CL
Input data hold time after PROG
tpF
CL
= BOpF
= 20pF
0
tw
(PR)
tsu
(PC-PR)
th (PR-O)
810
ns
150
ns
DMA
Symbol
Parameter
Alternative
Test conditIons
symbol
limits
Min
Typ
Max
Unit
tsu (DACK-R)
Data acknowledge tIme before read
t ACC
0
th (R-OACK)
Data hold time after read
t CAc
0
ns
tsu (OACK-W)
Data setup time before write
t ACC
0
ns
th (W-DACK)
Data hold tIme after write
tCAC
0
ns
SWITCHING CHARACTERISTICS
ns
(Ta = -20-75'C, Vee = 5V±10%, unless otherwise noted)
DBB Read
SYmbol
Alternative
Test condItIons
symbol
limits
Min
Typ
Max
Unit
Data enable time after CS
tAD
CL = 150 pF
225
ns
(AO-DO)
Data enable time after address
tAO
CL -150 pF
225
ns
(R-DO)
Data enable time after read
tRO
CL -150 pF
225
ns
(R-DO)
Data dIsable time after read
tOF
100
ns
t pzx (CS-DO)
t pzx
t pzx
t pxz
Parameter
DMA
Symbol
Parameter
Data enable tIme after DACK
tl;'HL (R-DRO)
ORO disable time after read
t pHL (W-DRO)
ORO disable time after write
tpzx
(DACK-OQ)
Note 2
3-28
Alternative
Test conditions
symbol
Limits
Min
Typ
Max
Unit
tACO
150 pF Load
225
ns
tCRO
150 pF Load
200
ns
t CRO
150 pF Load
200
ns
Output voltage discriminating levels, low and high, are 0, BV and 2, OV r'lspeclively
• MITSUBISHI
"'ELECTRIC
MITSUBISHI MICROCOMPUTERS
MSL8041A-XXXP
SLAVE .MICROCOMPUTER
TYPICAL CHARACTERISTICS
">
3. 8
X0
>
w
...-'«
0
4
...
2
...:::J
0..
:::J
0
-'
W
>
W
Vee = 5V
Ta = 25"C
Vee = 5V
Ta = 25'C
6
(!)
>
" --~
.........
I'--
w
o
~o
o3
>
...
...
0..
::J
o
2
-'
w
1/
~
±
~
(!)
-0 4
o
o8
06
HIGH-LEVEL OUTPUT CURRENT
1 0
-'
2
IOH(mA)
~
~
...::J
0..
~
(!)
~
r\.
3
2
a
-'
\
~
-'
- 0 05
- 0 1
Z
-'
w
~
-'
\
- 0 15
~
o
-'
- 0 2
LOW-LEVEL INPUT CURRENT
o
- 0 25
l,(mA)
...
Z
w
16
Vee
V DD
z
1 4
>-'
w
()
...........
1 0
oW
"- ~
N
a:«
8
>-'
::J
(fl
1 2
1 0
= 5V
= 5V
"-
W
N
a:«
o8
:;:
a:
""
............
~ ......
0
0 6
2&
25
50
AMBIENT TEMPERATURE
3-30
Vee
V DD
0
I'---
a:
z
1,(mA)
1 4
0..
0..
:;:
o
0 1
::J
12
0..
0..
~
0 08
a:
a:
::J
()
0 06
VS. AMBIENT TEMPERATURE
1 6
.E
a:
a:
0 04
\
NORMARIZED SUPPLY CURRENT (1 00 )
"...
= 5V
= 5V
02
\
LOW-LEVEL INPUT CURRENT
NORMARIZED SUPPLY CURRENT (led
VS. AMBIENT TEMPERATURE
']
\
0..
1
0
\
...::J>
-'
w
>
w
Vee = 5V
Ta = 25'C
"1\
w
"\
w
(!)
IOL(mA)
RESET LOW-LEVEL INPUT
VOLTAGE VS. LOW-LEVEL
INPUT CURRENT
Vee = 5V
Ta = 25'C
i'..
10
LOW-LEVEL OUTPUT CURRENT
p,. P2 LOW-LEVEL INPUT
VOLTAGE VS. LOW-LEVEL
INPUT CURRENT
............
V
o
-'
-02
/
/
::J
........
0
8
/
4
(!)
-'
I
DATA BUS LOW-LEVEL
OUTPUT VOLTAGE VS. LOW-LEVEL
OUTPUT CURRENT
o~
DATA BUS HIGH-LEVEL
OUTPUT VOLTAGE VS. HIGH-LEVEL
OUTPUT CURRENT
75
100
z
-25
TaCC)
25
50
AMBIENT TEMPERATURE
• MITSUBISHI
...... ELECTRIC .
75
TaCC)
100
MITSUBISHI MICROCOMPUTERS
MSL8041AH-XXXP
SLAVE MICROCOMPUTER
DESCRIPTION
The M5L8041 AH-XXXP is a general-purpose, programmable
interface device deisgned for use with a variety of 8-bit
microcomputer systems. This device is fabricated using Nchannel sillicon-gate ED-MaS technology.
FEATURES
Mask ROM .................................... · 1024-word by 8-bit
Static RAM ......................................... 54-word by 8-bit
•
Instruction cycle"""""""'''''''''''''''':'''''''''''''', 1. 25,us
(Oscillator frequency 12MHz)
18 programmable I/O pins
Asynchronous data register for interface to master processor
•
•
•
TEST PIN 0
To- 1
CLOCK 1
X,- 2
CLOCK 2
X, -
3
RESET RESET -
4
Vee (5V)
TEST PIN 1
INPUT/
OUTPUT
PORT 2
SINGLE STEP
•
•
•
•
PIN CONFIGURATION (TOP VIEW)
CHIP SELECT
CS -
6
Acc~;:f~~~E 1) E~ READ
7
R- B
ADDRESS
INPUTI
OUTPUT
PORT 1
WRITE
W- 10
SYNCHRONIZED SYNC _ 11
SIGNAL
DOo '" 12
8-bit CPU, ROM, RAM, I/O, timer, clock and low power,
stand-by mode
27 .... P1 0
26
25 -
DATA BUS
Single 5V supply
Alternative to custom LSI
Voo (5V) EXTERNAL
PROG
1/0
CONTROL
INPUT/
OUTPUT
PORT 2
APPLICATION
Alternative to custom LSI for peripheral interface
Outline 40P4
Note 1
Connect to Vss in the operating condition.
BLOCK DIAGRAM
DATA BUS
INPUT/OUTPUT PORTl
INPUT/OUTPUT PORT2
RESET
SINGLE STEP
ROM
N
U TI N REGISTER
INSTRUCTION
DECODER
TEST PINO
TEST PIN 1
R
READ
WRITE
Ao
CLOCK
CHIP SELECT
ADDRESS
' - - - - - { 7 EA
EXTERNAL ACCESS
---~
(NOTE I)
PROG
~
3-32
To
T,
EXTERNAL 1/0 CONTROL
SYNCHRONIZED
SIGNAL
•
MITSUBISHI
.;.. ELECTRIC
MITSUBISHI MICROCOMPUTERS
MSL8041AH-XXXP
SLAVE MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vee
Supply voltage
Voo
Supply voltage
V,
Inpul voltage
Vo
Output voltage
Pd
Power dissipation
Topr
Operating temperature range
TstQ
Storage temperature range
Conditions
With respect to Vss
Ta = 25'C
Ratings
Unit
-0.5-7
V
-0.5-7
V
-0.5-7
V
-0.5-7
V
1500
0-70
mW
°C
-65-150
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Limits
Parameter
Nom
Max
Vee
Supply voltage
4.5
5
5.5
Voo
Supply voltage
4.5
5
5.5
Vss
Supply voltage
V ,H
High-level Input voltage
V'L
Low-level input voltage
f(.)
Operating frequency
Unit
V
V
V
0
2.0
V
0.8
1
ELECTRICAL CHARACTERISTICS
Symbol
Min
12
V
MHz
(T a =O-70'C. Vcc=5V±10%. unless otherwise noted)
Parameter
Test conditions
Limits
Min
Typ
Max
Unit
V'L
V 1H1
-0.5
0.8
V
High-level input voltage (all except X,. X2, RESET)
2.0
Vee
V
V 1H2
High-level input voltage (X" X2, RESET)
3.8
Vee
V
V OL1
Low-level output voltage (000- 007)
10l = 2mA
0.45
V
V OL2
Low-level output voltage (Pl o-PI 7, P2 0-P27, SYNC)
10l = 1.6mA
0.45
V
V OL3
Low-level output voltage (PROG)
10l=lmA
0.45
V
V OH1
High-level output voltage (000-007)
10H = -400"A
2.4
V OH2
High-level output voltage (all other outputs)
10H = -50"A
2.4
I,
Input leakage current (To, T" R, W, CS, A", EA)
Vss ~ Vt ~ Vee
IOZL
High-impedance state output leakage current (000-007)
Vss
1'L1
Low-level input load current (Pl o-Ph, P2 0-P27)
V,l = O. BV
-0.5
IIL2
Low-level input load current (RESET, SS)
V,l = O. BV
-0.2
100
Supply current from Voo
lee
3-34
Low-level input voltage
+ 10
+ O. 45 ,;; Vo ,;; Vee
Total supply current
• MITSUBISHI
. . . . ELECTRIC
V
V
-10
10
-10
10
!LA
!LA
mA
mA
10
mA
145
mA
MITSUBISHI MICROCOMPUTERS
MSL8041AH-XXXP
SLAVE MICROCOMPUTER
TIMING DIAGRAMS
Read
)
K
Ih (R-CS)
Isu (CS-R)
Isu(~R}
j~
IW(R}
"'
IpZX(R-OQI
/J
IpZX(Ao-OQ) Ipzx
(CS-DQ~
IpXZ(R-OQI
~
VALID DATA
Write
CS,
Ao
Iw(w)
w
Port 2
SYNC
I
\'-----~/
\_---_/
_----J
Isu (Q PRJ
EXPANDER
PORT OUTP UT
)
P20 -P23 DATA
PORT CONTROL
J{
EXPANDER
PORT INPU T
)
P20 -P23 DATA
Isu(PC-PR)
PROG
DMA
PORT CONTROL
,
,
J:!:-!o
th(PR-PC)
ISU(oACK-R}
I w ( R)
I
llh(R-OACK)
,
Isu (oACK- wi
.I
th(w-OACKI
_I
w
Iw(W)
X
.1
Ipzx( oACK-oQ)
Isu(o-w)
ORO
3-36
DATA
IW(PR)
,
,
Ih(PR-O)
\ ~ll-INPUT
If
\_-
K
OUTPUT
DATA
Isu(O-p~
th(PR Q)
I-:'
I
Ih(W-o)
u~~
U
I PHL( W-oRQ)
• MITSUBISH. I
" " ELECTRIC
MITSUBISHI MICROCOMPUTERS
MSL8041AH-XXXP
SLAVE MICROCOMPUTER
APPLICATION EXAMPLES
(1) Interface with M5L8085AP
PERIPHERAL
DEVICES
(2) Interface with Series MELPS 8-48 Microcomputer and M5L8243P .
d
R
R
W
W
Port
CS
Ao
Port
OQo- DQ7
8
PROG
PROG
P2 o-P2,
4
P2o-P2,
P4~
1
P5~
p.
DQo- DQ7
M5L8243 P
M5L8041AH
P,
-xxxp
SERIES
MELPS8-48
Microcomputer
P2,-P2,
~
Kn
PERIPHERAL
DEVICES
4
Plo-PI,
8
To
T,
/
3-38
• MITSUBISHI
;"ELECTRIC
MITSUBISHI MICROCOMPUTERS
MSL8042·XXXP
SLAVE MICROCOMPUTER
FUNCTION
The M5L8042-XXXP is designed as an ordinary 8-bit CPU
peripheral LSI chip and it contains a small stand-alone microcomputer. Although this microcomputer functions independently, when it is used as a peripheral controller, it is
called the slave microcomputer in contrast to the master
computer. These two devices can transfer the data alternatively through the buffer register between them. The
M5L8042-XXXP contains the buffer register to use this LSI
as a slave microcomputer and it can be accessed in the
same way as other standard peripheral devices. Since the
M5L8042-XXXP is a complete microcomputer, it is easy to
develop a user-oriented mask-programmed peripheral LSI
only by changing the control software.
PIN DESCRIPTION
Pm
Name
Input or output
Vss
Ground
-
Vee
MaIO power supply
-
Function
Connected to a OV supply (ground)
Connected to a 5V supply
Connected to a 5V supply
Voo
Power supply
To
Test pm 0
Input
X" X2
Crystal mputs
Input
RESET
Reset
Input
SS
Smgle step
Input
CS
Chip select Input
Input
EA
External access
Input
R
Read enable signal
Input
Ao
Address Input
Input
An address mput used to indicate whether the Signal on the data bus IS data or a command
W
Write enable Signal
Input
Serves as the wnte Signal when the master CPU IS outputting data from the bus to the M5L8042-XXXP.
SYNC
Sync Signal output
Output
-
-
DO c-D0 7 Data bus
Used as a memory hold when Vee
Inputloutput
IS
cut off
Provides external control of conditional program Jumps (JTO/JNTO instructions)
An mternal clock cirCUit IS provided so that by connecting an RC CircUit or crystal to these mput plns, the
clock frequency can be determined. Xl and X2 can also be used to mput an external clock signal
CPU inlttallzatlon mput.
Used to halt the execution of a command by the CPU When used In combination with the SYNC signal,
the command execution of the CPU can be halted every instruction to enable single step operation
Chip select Input for data bus control.
Normally maintained at OV
Serves as the read signal when the master CPU IS accepting data on the data bus from the M5L8042-
XXXP
Output 1 time for each machine cycle.
Three-state, bidirectional data bus. Data bus IS used to Interface the M5L8042-XXX P to a master system data bus
Quasl-bld(rectlonal port When used as an Input port, FF16 must first be output to thiS port.
P20 -P2 7
Port 2
Input/output
After resetting, however, when not used afterwards as an output port, thiS
IS
not necessary.
P2o- P2, are used when the M5L8243P 1/0 expander IS used
PROG
Program
Pl o-Ph
Port 1
T,
Test pm ,
3-40
Output
Input/oOtput
Input
Serves as the strobe Signal when the M5L8243P 1/0 expander IS used
QuaSI-bidirectional port. When used as an Input port, FF16 must first be output to thiS port
After resetting, however, when not used afterwards as an output port, thiS is not necessary
Provides external control of conditional program Jumps (JT1/JNTl Instructions)
Can serve as the Input pin for the event counter (STRT CNT instruction)
• MITSUBISHI
..... ELECTRIC
MITSUBISHI MICROCOMPUTERS
MSL8042-XXXP
SLAVE MICROCOMPUTER
TIMING REQUIREMENTS
(Ta = 0-70C;, Vcc = 5V±10%, unless otherwise noted)
DBB Read
Symbol
Parameter
Alternative
Cycle time
tCY
tWIRl
Read pulse width
tRR
tsu
Chip select setup time before read
Chip select hold time after read
tc
(¢)
(CS-R)
th (R-CS)
Test conditions
symbol
Limits
Min
Typ
1. 25
tc«)=l.25l's
Max
15
Unit
I1S
160
ns
tAR
0
ns
tRA
0
ns
DBB Write
Symbol
Parameter
Write pulse width
tW(w)
tsu (cs-w)
tsu
Alternative
Test conditions
symbol
Limits
Min
Typ
Max
Unit
tww
160
ns
tAW
a
ns
CS, Ao, hold time after write
tWA
0
ns
Data setup time before write
tow
130
ns
Data hold time after write
two
0
ns
CS, AQ. setup time before write
(AO-W)
th (w-cs)
-
th (W-AO)
tsu
(OQ-W)
th (W-OQ)
Port 2
Symbol
Parameter
Alternative
Test conditions
symbol
Limits
Min
Typ
Max
Unit
PROG pulse width
tpp
Port control setup time before PROG
tcp
CL - BOpF
th (PR-PC)
Port control hold time after PROG
t pc
CL - 20pF
60
ns
tsu
(Q-PR)
Output data setup time before PROG
top
CL = BOpF
200
ns
tsu
(O-PR)
Input data hold time before PROG
tpR
CL = BOpF
Input data hold time after PROG
t PF
CL = 20pF
tw
(PR)
tsu
(PC-PR)
th (PR-O)
700
ns
80
ns
0
650
ns
150
ns
DMA
Symbol
Parameter
Limits
Alternative
Test conditions
symbol
Min
Typ
Max
Unit
DACK setup time before read
tAce
0
ns
DACK hold time after read
t CAC
0
ns
tsu (DACK-W)
OACK setup time before write
tACC
0
ns
th (W-DACK)
DACK'hold time after write
t CAC
0
ns
tsu
th
(DACK-R)
(R-DACK)
Notel:
Input voltage level V'L = O. 45V, V,H = 2. 4V
SWITCHING CHARACTERISTICS
(Ta =0-70'C, Vcc = 5V±10%, unless otherwise noted)
DBB Read
Symbol
Alternative
Parameter
~-
Min
Typ
Max
Unit
tAD
CL = 100pF
130
ns
tAD
CL = 100pF
130
ns
Data enable time after read
tRo
C L = 100 pF
130
ns
Data disable time after read
tOF
85
ns
tpzx (CS-DO)
Data enable time after CS
t pzx (AD-DO)
Data enable time after address
tpzx (R-DO)
tpxz
(R-DO)
Lrmlts
Test conditions
symbol
DMA
Symbol
Limits
Alternative
Parameter
Test conditions
symbol
Min
Typ
Max
Unit
Data enable time after DACK
tACD
130
ns
t pHL (R-ORO)
ORO disable time after read
tCRO
90
ns
t pHL
ORO disable time after write
tCRO
90
ns
tpzx
(OACK-OQ)
Note 2
3-42
(W-DRO)
CL -150 pF
Output voltage discriminating levels, low and high, are O. 8V and 2. OV respectively
• MITSUBISHI
"'-ELECTRIC
MITSUBISHI MICROCOMPUTERS
MSL8042·XXXP
SLAVE MICROCOMPUTER
TYPICAL CHARACTERISTICB
DATA BUS HIGH-LEVEL
OUTPUT VOLTAGE VS. HIGH-LEVEL
OUTPUT CURRENT
3 8
Vee = 5V
Ta = 25'C
w
3 6
""
(!)
~
~
3 4
~
::>
0..
~
::>
3 2
w
0
.............
r--
>
a
4
a
3
a
2
a
1/
-
~
::>
0
...J
W
G;
::o
:i:.
(!)
a
o6
4
a8
HIGH-LEVEL OUTPUT CURRENT
1 0
...J
IOH(mA)
vee = 5V
Ta= 25'C
""-
"'"
w
~
...J
0
>
~
1\-
::>
0..
:!:
\
1
\
...J
W
>
W
...J
::0
...J
a
a
05
a
1
a
15
a
LOW-LEVEL INPUT CURRENT
2
a
o 02
25
..!?
~
Z
w
a::
a::
Vee = 5V
Voo = 5V
>-
::>
1 2
1
a
cw
N
cc«
:<
a8
a::
0
z
"
~
1 4
Z
::>
" '"
a
08
a
1
l,(mA)
Vee = 5V
Voo = 5V
0
1 2
>-
...J
0..
0..
::>
r---........
(Jl
1 0
c
W
N
...............
cc a
«
"
~
r---........
8
i'-.... ....
:<
a::
a
0
6
25
25
50
AMBIENT TEMPERATURE
3-44
06
w
...J
0..
0..
(Jl
a
a::
a::
::>
()
\
VS. AMBIENT TEMPERATURE
1 6
.E
1 4
04
NORMARIZED SUPPLY CURRENT (loo)
VS. AMBIENT TEMPERATURE
1 6
a
LOW-LEVEL INPUT CURRENT
1,(mA)
NORMARIZED SUPPLY CURRENT {led
'0
Vee = 5V
Ta = 25'C
"l'\,
:>
l\.
IOL(mA)
RESET LOW-LEVEL INPUT
VOLTAGE VS. LOW-LEVEL
INPUT CURRENT
~
~
.
10
LOW-LEVEL OUTPUT CURRENT
(!)
i'...
'\
V
2
Pl. Pz LOW-LEVEL INPUT
VOLTAGE VS. LOW-LEVEL
INPUT CURRENT
........
/
/
::>
0..
...J
a2
/
~
...J
a
Vee=5V
Ta = 25'C
~
...J
......
3.0
2 8
5
(!)
...J
W
I
:;- a
1
o
>
W
DATA BUS LOW-LEVEL
OUTPUT VOLTAGE VS. LOW-LEVEL
OUTPUT CURRENT
75
100
z
TaCC)
- 25
25
50
AMBIENT TEMPERATURE
• MITSUBISHI
. . . . ELECTRIC
75
TaCC)
100
MITSUBISHI MICROCOMPUTERS
MSL8~3P
INPUT /OUTPUT EXPANDER
PIN DESCRIPTION
Name
Symbol
Input or output
Function
CS
Chip select
In
Chip select Input. A high on CS causes PROG input to be regarded high inside the M5L8243P, then this
inhibits any change of output or internal status.
PROG
Program
In
A hlgh-te-Iow tranSition on PROG signifies that address (PORT 4-7) and control are available on PORT 2,
and a low-te-high transition signifies that the designated data is available on the dlslgnated port through
PORT 2. The designation Is shown In Table 1.
P2o-P2s
Input/output port 2
In/out
The 4-blt bidirectional port contains the address and control bits shown In Table 1 on a hlgh-te-Iow transition of PROG. During a low-te-hlgh transition It contains the Input (output) data on this port.
P4 0 -P4 s
P50 -P5s
InpuVoutput port 4
InpuVoutput port 5
InpuVoutput port 6
InpuVoutput port 7
In/out
P6o-P6 s
P70 -P73
The 4-blt bidirectional I/O port. May be programmed to be Input, low-Impedance latched output or a
three-state. This port Is automatically set output mode when it Is written. ANLed or ORLed then contlnues its mode until next read operation. After reset on a read operation. this port is in high-impedance
and input mode.
OPERATION
The M5L8243P is an input/output expander designed specifically for the Series MELPS 8-41 and Series MELPS 8-48.
The Series MELPS 8-41 and Series MELPS 8-48 already
have instructions and PROG pin to communicate with the
M5L8243P.
An example of the M5L8243P and the Series MELPS 8-41 or
Series MELPS 8-48 is shown in Fig. 1. The following description of the M5L8243P basic operation is made according to Fig. 1.
Upon initial application of power supply to the device, and
then about 500",s after, resident bias circuits become stable
and each device is ready to operate. And each port of the
M5L8243P is set input mode (high-impedance) by means of
a resident power-on initialization circuit.
When the microcomputer begins to execute a transfer instruction
MOVO
A , Pi
i = 4, 5, 6, 7
w~ich means the value on the port Pi is transferred to the
accumulator, then the signals are sent out on the pins
PROG and P2o-P2 3 as shown in Timing Diagram.
On the high-to-Iow transition of the pin PROG, the
M5L8243P latches the instructions (ex. 0000) into itself from
pins P2 o- P2 3 and transfers them to the instruction register
(CD in Timing Diagram). During the low-level of PROG, the
M5L8243P continuously outputs the contents of the specified input (output) port (in this case port p.) to pins P2oP23 (® in Timing Diagram). The microcomputer, at an
appropriate time, latches the level of pins P2 o- P2 3 and resumes high-level of PROG.
The next example is the case in which the microcomputer
executes
4-4
MOVO
Pi,A
i=4,5,6,7
the transfer (output) instruction.
In this case, as in the previous case, on the high-to-Iow
transition of the pin PROG, the M5L8243P latches the instructions (ex. 0110) into itself from pins P2 o-P2 3 and transfers them to the instruction register (CD in Timing Diagram).
After this, the microcomputer sends out high to the pin
PROG, transferring the data to pin P2o- P23 which is an
output data to inpuVoutput port. Then the. M5L8243P transfers the data of pins P2o- P2 3 to the port latch of the designated input/output port (in this case Pe). In a few seconds
after a low-te-high transition on the PROG, the deSignated
port (Pe ) becomes in an output mode and the data of the
port latch are transferred to the port pins (@ in Timing
Diagram).
When instructions
ANlO
ORlO
PI,A
PI,A
i = 4,5,6,7
are executed, the microcomputer generally operates as
same function as MOVD Pi, A.
It only differs in that the data of port latch after ® in the
Timing Diagram is ANDed or ORed with the data of port
latch before ® and the data of pins P2 0 -P2 3.
When instructions
MOVO
Pi, A
ANlO
Pi, A
Pi ,A
i = 4, 5, 6, 7
ORlO
are executed toward the port in an output mode, the outputs are generated on the port as soon as low-to-high transition on the PROG occurs.
When the mode of the output port is going to be changed
during the execution and the instruction
MOVO
A , Pi
i = 4, 5, 6, 7
is executed, it is preferable to execute one dummy instruction. Because it takes a little time to turn the deSignated
port into a high-impedance state after high-to-Iow transition
on the PROG, the result may be that the first instruction is
not read correctly.
• MITSUBISHI
;"'ELECTRIC
MITSUBISHI MICROCOMPUTERS
MSL8243P
INPUT/OUTPUT EXPANDER
TIMING REQUIREMENTS
Symbol
(Ta = -20-7S'C. Vee = 5V±10%. unless otherwise noted)
Alternative
Parameter
Test conditions
symbol
Limits
Min
Typ
Max
Unit
tSU(INST-PR)
Instruction code setup time before PROG
tA
80pF Load
100
ns
th(PR-INST)
Instruction code hold time after PROG
te
20pF Load
60
ns
tSU(OQ-PR)
Data setup time before PROG
te
80pF Load
200
ns
th(PR_OQ)
Data hold time after PROG
to
20pF Load
20
ns
tW(PR)
PROG pulse width
tK
700
ns
tSU(CS-PR)
Chip-select setup time before PROG
tes
50
ns
th(PR-CS)
Chip-select hold time after PROG
tes
50
ns
tSU(PORT-PR)
Port setup time before PROG
tiP
100
ns
the PR-PORT)
Port hold time after PROG
tiP
100
ns
SWITCHING CHARACTERISTICS
Symbol
Parameter
(Ta =-20-75'C. Vcc=SV±10%. unless otherwise noted)
Alternative
Test conditions
symbol
Limits
Min
Typ
Max
Unit
ta(PR)
Data access time after PROG
tAce
80pF Load
0
650
ns
tdv(PR)
Data valid time after PROG
tH
20pF Load
0
150
ns
Output valid time after PROG
t po
100pF Load
700
ns
Input/output switching time
-
800
ns
tpHL(PR)
tpLH(PR)
tpZX(PR)
tpXZ(PR)
4-6
• MITSUBISHI
"'ELECTRIC
MITSUBISHI MICROCOMPUTERS
MSL8243P
INPUT /OUTPUT EXPANDER
Example
To use 20mA sinking capability at port 7, find the effects on
the sinking capabilities of the other I/O lines.
Assume the M5L8243P is driving loads as shown below.
3 lines: -20mA (VOL = 1.OV max, port 7 only)
4 lines: -4mA (VOL = 0.45V max)
9 lines: -1.6mA (VOL = 0.45V max)
Is this within the allowable limit?
~ IOL = (20mA X 3)
(4mA X 4)
(1.6mA X 9) =
90.4mA
+
Flg.2
4-8
From the curve we see that with respect to IOL = 4mA, IOL
is 93mA (Point B) and that the above load of 90.4mA is within the limit of 93mA.
Note: The sinking current of ports 4 - 7 must not exceed
30mA regardless of the value of VOL'
+
Expansion Interface example
• MlTSUBISHI
. . . . ELECTRIC
MITSUBISHI MICROCOMPUTERS
MSM82C43P/FP
INPUT/OUTPUT EXPANDER
PIN DESCRIPTION
Symbol
Name
Functioh
Input or output
CS
Chip select
In
PROG
Program
In
P2o-P23
Input/output port 2
P4 o-P4 3
P5o-P5 3
P60 -P6 3
P7o -P73
Input/output port 4
Chip select input. A high on CS causes PROG input to be regarded high inside the M5M82C43P. This
then inhibits any change of output or Internal status
A hlgh-to-Iow tranSition on PROG Signifies that address (ports 4-7) and control are available on port 2.
and a low-la-high transition Signifies that the designated data is available on the designated port through
port 2 The designation IS shown
Input/output port 5
Input/output port 6
Input/output port 7
In/out
Table 1.
tion 01 PROG. During a low-la-high transition, It contains the mput (output) data on this port
4-blt bidirectional I/O ports. May be programmed to be input. low-Impetlance latched or 3-state These
In/out
ports are automatically set to the output mode when written, ANLed or ORLed and this mode continues
until the next read operation After reset on a read operation, this port IS placed
In
the high ImP7dance
and Input mode
OPERATION
The M5M82C43P is an input/output expander designed
specifically for the Series MElPS8-41 and Series MELPS848. The Series MELPS8-41 and Series MELPS8-48 already
have instructions and PROG pin to communicate with the
M5M82C43P.
An example of the M5M82C43P and the M5M80C49-XXXP is
shown in Fig. 1. The following description of the
M5M82C43P basic operation is made according to Fig. 1.
Upon initial application of the power supply to the device,
each port of the M5M82C43P is set to the input mode (highimpedance) by means of the resident power-on initialization circuit.
When the microcomputer begins to execute a transfer instruction
MOVO
A, Pi
i = 4, 5, 6, 7
which means the value on the port Pi is transferred to the
accumulator, then the signals are sent out on the pins
PROG and P2 o-P2 3 , as shown in the timing diagram.
On the high-to-Iow transition of pin PROG, the M5M82C43P
latches the instructions (e.g. 0000) into itself from pins P2 oP2 3 and transfers them to the instruction register (CD in the
timing diagram). During the lOW-level of PROG, the
M5M82C43P continuously outputs the contents of the specified input (output) port (in this case, port P4) to pins P2 oP23 ((2) in the timing diagram). The microcomputer, at the
appropriate time, latches the level of pins P2 o- P2 3 and resumes the high level of PROG.
The next example is the case in which the microcomputer
executes
4-10
In
This 4-bldlrectional port contains the address and control bits shown in Table 1 on a high-la-low transi-
MOVO
Pi, A
i = 4, 5, 6, 7
the transfer (output) instruction.
In this case, as in the previous case, on the high-to-Iow
transition of pin PROG, the M5M82C43P latches the instructions (e.g.0110) into itself from pins P2o- P2 3 and transfers
them to the instruction register (CD in the timing diagram).
After this the microcomputer sends out high to pin PROG,
transferring the data to pins P2 0 - P2 3 which is an output
data to the input/output port. Then the M5M82C43P transfers the data of pins P2 o-P2 3 to the port latch of the designated input/output port (in this case P6). In a few seconds
after a low-to-high transition on the PROG, the designated
port (P6) is set to the output mode and the data of the port
latch is transferred to the port pins (@ in the timing
diagram).
When instructions
ANlO
Pi,A
1= 4, 5, 6, 7
Pi, A
ORlO
are executed, the microcomputer generally operates as the
same function as MOVD Pi, A.
It only differs in that the data of the port latch after@ in the
timing diagram is ANDed or ORed with the data of the port
latch before @ and the data of pins P2 o-P2 3
When instructions
MOVO
Pi, A
Pi,A
ANlO
Pi, A
i = 4,5,6,7
ORlO
are executed toward the port in an output mode, the outputs are generated on the port as soon as low-to-high transition on the PROG occurs.
When the mode of the output port is going to be changed
during the execution and the instruction
MOVO
A, Pi
i = 4, 5, 6, 7
is executed, it is preferable to execute one dummy instruction. Because it takes a little time to turn the deSignated
port into a high-Impedance state after the high-to-Iow transition on the PROG, the result may be that the first instruction is not read correctly
• MITSUBISHI
. . . . ELECTRIC
MITSUBISHI MICROCOMPUTERS
MSM82C43P/FP
INPUT /OUTPUT EXPANDER
TIMING REQUIREMENTS
Symbol
(T a = -20-75'C, Vee
Parameter
= 5V±10%,
Vss
= OV,
unless othelWise noted)
Alternative
Test conditlOns
symbol
tSUCINST-PR)
Instruction code setup time befor PROG
tA
the PR-INST)
Instruction code hold time after PROG
ts
tSU(OQ-PR)
Data setup time before PROG
tc
th(PR-OQ)
Data hold time after PROG
to
= 80pF
= 20pF
Cl = 80pF
Cl = 20pF
Limits
Min
Typ
Max
Unit
Cl
100
ns
Cl
60
ns
200
ns
20
ns
tW(PR)
PROG pulse with
tK
700
ns
tSU(CS-PR)
Chip select setup time before PROG
tcs
50
ns
thCPR-CS)
Chip select hold time after PROG
tCB
50
ns
tSU(PORT-PR)
Port setup time before PRDG
"tiP
100
ns
th(PA-POAT)
Port hold time after PROG
tiP
100
ns
SWITCHING CHARACTERISTICS
Symbol
Parameter
ta(PR)
Data access time after'PROG
tdV(PR)
Data valid time after PROG
tpHL(PR)
(T a = -40-85'C, Vee
= 5V±10%,
Alternative
tH
Output valid time after PROG
t po
Input/output switching time
-
= ov,
unless othelWise noted)
Test conditions
symbol
tAce
Vss
= 80pF
Cl = 20pF
Cl
Cl
= 100pF
Limits
Min
a
a
Typ
Max
Unit
650
ns
150
ns
700
ns
800
ns
tpLH(PR)
tpZX(PR)
tpXZ(PA)
4-12
•
MITSUBISHI
..... ELECTRIC
MITSUBISHI MICROCOMPUTERS
MSM82C43P/FP
INPUT/OUTPUT EXPANDER
Example:
To use the 20mA sinking capability at port 7, find the effects
on the sinking capabilities of the other 1/0 lines. Assume
the M5M82C43P is driving loads as shown below:
3 lines: 20mA (VOL = 1.0V max, port 7 only)
4 lines: 4mA (VOL = 0.45V max)
9 lines: 1.6mA (VOL = 0.45V max)
Is this within the allowable limit?
lloL = (20mA X 3)
(4mA X 4)
(1.6mA X 9)
90.4mA
+
From the curve it is seen that with respect to IOL = 4mA, IOL
is 93mA (point B) and that the above load of 90.4mA is within the limit of 93mA.
Note: The sinking current of port 4 - 7 must not exceed
30mA regardless of the value of VOL'
+
M5MBOC49-XXXP
PROGr-----------~-------------+------------~------------~
Fig.2
4-14
Expansion interface example
• MITSUBISHI
"'ELECTRIC
MITSUBISHI MICROCOMPUTERS
SERIES MELPS8·48 MASK ROM
ORDERING METHOD
SERIES MELPS 8-48 MASK-PROGRAMMABLE ROM CONFIRMATION MATERIAL
SINGLE-CHIP 8-BIT MICROCOMPUTERS M5L8048-XXXP, M5L8049-XXXP, P-6, M5L8049H1-XXXP and M5M8050H-XXXP
MITSUBISHI ELECTRIC
Signature
Customer
Company name
Prepared
Company address
Tel
Company contact
Date
The single-chip microcomputer type number to order and
the type of EPROMs to be supplied should be specified by
~er
2
3
4
checking / in the boxes. Three sets of EPROMs should be
supplied.
02732
02764
OM5L8048-XXXP
OA (000" - 3FF,,)
OA (000,. - 3FF,,)
08748
08748H
DM5L8049-XXXP
OM5L8049-XXXP-6
OA (000,. - 7FF,.)
OA (000,. - 7FF,.)
08749
08749H
OM5L8049H1-XXXP
OA (000,. - 7FF,.)
OA (000,. - 7FF,.)
08749
08749H
OM5M8050H-XXXP
OA (000,. - FFF,.)
OA (000,. - FFF,.)
microcomputer type number
Note
Approved
-
The high-level data of both data outputs and address Inputs of the supplied EPROM will be programmed as '1', and
low-level as '0'.
Cleary indicate the type number of EPROMs and address designation letter symbols A and 8 on the supplied
EPROMs
The data Of the addresses in parentheses on the EPROM are programmed onto the ROM
The data from each PROM in the set is compared and if 2 of the 3 are equal. the equal value will be programmed
into the ROM. When the 3 values are different programming is halted and the customer is notified of the error. The
error report will show the address and data
CUSTOMER'S IDENTIFICATION MARK
If you require a special identification mark, please specify In the following format.
I,
1
Mitsubishi IC type number
Note 5 : A mark field should start with the box at the extreme right
6 : The identification mard should be no more than 12 characters consisting of alphanumeric
characters (except J.I and 0) or dashes
COMMENTS
5-4
•
MITSUBISHI
..... ELECTRIC
MITSUBISHI MICROCOMPUTERS
SERIES MELPS 8-41 MASK ROM
ORDERING METHOD
MASK ROM ORDERING METHOD
EPROM SPECIRICATIONS
Described below is the ordering method applicable when
programs submitted by the customer are written into the
mask ROMs.
An automatic mask ROM design program is prepared
for writing programs into mask ROMs, and (1) the drafting
data for mask ROM generation, (2) the reference list for
mask ROM preparation error checks and (3) an automatic
test protram for the large-scale tester designed to test the
mask ROMs are all automatically generated.
When the object program is stored in the Series MELPS
8-41 single-chip microcomputer mask ROM, the order for
the object program medium is received as an EPROM
form. Consequently, the EPROM or EPROMs which have
stored the object 'program equivalent to one single-chip
microcomputer chip should be submitted accompanied by
the prescribed confirmation sheets for 3 sets of EPROMs
respectively.
1, Usable EPROMs include Mitsubishi's M5L2732K and
M5L2764K or Intel's 2732, 8741, 8741 A, 8742 or their
equivalent. The M5L2732K and the M5L2764K are the
standard EPROMs.
2. "High" is treated as 1 for the EPROM data and
address.
3. All the data from the head address to the final address
are treated as the EPROM's effective data.
CHECKPOINTS
1. Cleary indicate the type number of EPROM.
SERIES MELPS 8-41 MASK ROM DEVELOPMENT CAD SYSTEM
FROM CUSTOMER
MITSUBISHI ELECTRIC
LARGE
TESTER
WATER
TEST
• FINAL
TEST
1--------1. QA TEST
•
5-6
•
MITSUBISHI
"-ELECTRIC
MITSUBISHI DATA BOOK
SINGLE-CHIP 8-BIT MICROCOMPUTERS Vol.2
April, First Edition 1987
Editioned by
Committee of editing of Mitsubishi Semiconductor Data Book
Published by
Mitsubishi Electric Corp., Semiconductor Division
This book, or parts thereof, may not be reproduced in any form without permission of
Mitsubishi Electric Corporation.
MITSUBISHI SEMICONDUCTORS
SINGLE-CHIP 8-BIT MICROCOMPUTERS Vol.2
J.. MITSUBISHI ELECTRIC CORPORATION
HEAD OfFICE : MITS UBISHI OENK I BLDG
H-09925-A KI-8704 Printed In JBpan ( ROO )
© 1987 MITSUBISHI ELECTRIC CORPORATION
MARUNOUCHI. TOKYO 100. TELEX J24532 CABLE MELCO TOKYO
Revised publication. elfectlve Apr. 1987.
Superseding publication H- 09380-A 0/ Nov. 1985.
Specifications subject to change without notice.
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2014:07:09 16:33:48-08:00 Modify Date : 2014:07:09 16:38:57-07:00 Metadata Date : 2014:07:09 16:38:57-07:00 Producer : Adobe Acrobat 9.55 Paper Capture Plug-in Format : application/pdf Document ID : uuid:2bb33ab6-9b2b-8a41-a791-98fafd215732 Instance ID : uuid:26941f71-0a7d-9241-9ba3-5c75c8706766 Page Layout : SinglePage Page Mode : UseNone Page Count : 82EXIF Metadata provided by EXIF.tools