1987_TI_Interface_Circuits_Data_Book 1987 TI Interface Circuits Data Book
User Manual: 1987_TI_Interface_Circuits_Data_Book
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SLYD002
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Interface
i
Circuits
Data Book
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1987
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TEXAS
INSTRUMENTS
Interface Circuits
Data Book
•
TEXAS
INSTRUMENTS
IMPORTANT NOTICE
Texas Instruments (Tn reserves the right to make changes in the
devices or the device specifica~ions identified in this publication
without notice. TI advises its customers to obtain the latest version
of device specifications to verify, before placing orders, that the
information being relied upon by the customer is current.
TI warrants performance of its semiconductor products to current
specifications in accordance with TI's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
such testing necessary to support this warranty. Unless mandated
by government requirements, specific testing of all parameters of each
device is not necessarily performed.
In the absence of written agreement to the contrary. TI assumes no
liability for TI applications assistance, customer's product design, or
infringement of patents or copyrights of third parties'by or arising from
warrant
use of semiconductor devices described herein. Nor does
or represent that 'any license, either express or implied, is granted
under any patent right, copyright, or other intellectual property right
of TI covering or relating to any combination, machine, or process in
which such semiconductor devices might be or are used.
n
Specifications contained in this data book supersede all data for these
products published by TI in the United States before September 1986.
ISBN 0-89512-199-9
Copyright © 1987. Texas Instruments Incorporated
INTRODUCTION
Texas Instruments offers a broad line of Interface and Speech Products serving analog signal
conditioning/processing and interface applications that may require higher currents and/or higher voltages than
can be achieved with conventional digital devices.
TI's Interface circuits represent technologies from classic bipolar through BIDFET, Advanced Low-Power Schottky
(ALS), IMPACr",LinCMOS"', and ~DVANCED LinCMOS" processes. The ALS and IMPACT'" oxide-isolated
technologies provide the Interface family with improved speed-power characteristics. LinCMOS'· and ADVANCED
LinCMOS" technologies feature a step-function improvement in impedance, speed, power dissipation, and
threshold stability.
TI's Interface products include such devices as data transmission circuits that tie computers and their associated
peripherals together according to a set of industry (EIA) standards that prescribe line length, data rates, and
propagation delays, among other tlj)ngs. With the recent growth of the flat panel display market, TI's highvoltage display drivers are providing cost-effective and reliable solutions to the AC-plasma, vacuum-fluorescent,
and electroluminescent display markets. Analog-to-digital and digital-to-analog converters are offered as peripheral
support chips in microprocessor-based systems and DSP (digital signal processing) related analog interfaces.
TI's line of high-current motorlprinthead and MOSFET drivers combine logic control and high current-drive
capability on one IC.
During the last decade, TI has produced a wide range of speech-generating devices based on the technique
of pitch-excited linear predictive coding (LPC). This technique extracts data from original recorded speech to
define the control parameters for a mathematical model of the vocal tract. The speech generated from this model
retains all the inflection and voice characteristics of the original spoken phrase while minimizing digitized data
storage requirements; and it does not exhibit the robotic quality often associated with synthesis-by-rule systems.
This data book provides information on the following types of products:
•
•
•
•
•
•
•
•
•
•
•
•
Analog Switches
High-Current Actuators and Peripheral Drivers
Switched-Capacitor General Purpose Filters .
AID and DIA Converters
High-Voltage Display Drivers
IBM 360/370 I/O Line Drivers
IEEE-488 (GPIB) Octal Bus Transceivers
RS-422-A Line Drivers
RS-422-A, RS-423-A, and RS-485 Line Receivers
LPC10 and LPC12 Voice Synthesis Functions on a Chip
One-Chip Speech System
Auxiliary Speech Memories
These products cover the dynamic dev'elopment of linear circuits from the classical operational amplifier to the
high-performance AID and DIA converters and speech-generating devices. New surface-mount packages (8
to 84 leads) include both ceramic and plastic chip carriers, and the small-outline (D) plastic packages that optimize
board density with minimum impact on power-dissipation capability.
The Selection Guide includes a functional description of each product, and to assist the design engineer, the
Guide is organized into sections containing information on key parameters and packaging. Ordering information
and mechanical data are in Appendix B.
IMPACT·, LinCMOS·, and ADVANCED LinCMOS· are trademarks of Texas Instruments Incorporated.
v
During the last decade, TI has produced one of the largest IC socket families. Tl's sockets include every type
and size socket in common use today and are available in a wide choice of contact materials and designs. Details
on Tl's sockets are presented in Appendix B.
While this volume offers design and specification data only for Interface and Speech components, complete
technical data for any TI semiconductor product is available from your nearest TI Field Sales Office, local
authorized TI distributor, or. by writing directly to:
'
Texas Instruments Incorporated
LITERATURE RESPONSE CENTER
P. O. Box 809066
DALLAS, TEXAS 75380-9066
We sincerely feel that you will discover the new 1987 Interface Circuits Data Book to be a significant addition
to your collection of technical literature.
vi
General Information
Alphanumeric Index
Selection Guide
Cross-Reference Guide
Data Sheets
Data Sheets
Cross-Reference Guide
Data Sheets
Cross-Reference Guide
Data Sheets
Data Sheets
Data Sheets
1-1
C)
CD
:::s
CD
!.
.s-3O'
ao·
:::s
1-2
ALPHANUMERIC INDEX
PAGE NO.
DEVICE
AOC0803C ...........................
AOC08031 ...........................
AOC0804C ...........................
AOC08041 ............................
AOC0805C ...........................
AOC08051 ............................
AOC0808 ............................
AOC0808M ...........................
AOC0809 ............................
AOC0831A ...........................
AOC08318 ...........................
ADC0832A ...........................
ADC08328 ...........................
ADC0834A ...........................
ADC0834B ...........................
ADC0838A ...........................
ADC0838B ...........................
AM26LS31C ..........................
AM26LS31M ..........................
AM26LS32AC .........................
AM26LS32AM ........................
AM26LS33AC .........................
AM26LS33AM ........................
AM26S10C ...........................
AM26S10M ..........................
AM26S11C ...........................
AM26S11M ..........................
OS3680 .............................
L293 ................................
L2930 ..............................
L298 ................................
MC3446 .............................
MC3450 .............................
MC3452 .............................
MC3453 .............................
MC3486 .............................
MC3487 .............................
N8T26 ..............................
PBL3717A ............................
SN55107A ...........................
SN55107B ...........................
SN55108A ...........................
SN55108B ...........................
SN55109A ...........................
SN55110A ...........................
SN55113 ............................
SN55114 ............................
SN55115 ............................
SN55116 ............................
SN55117 ............................
SN55118 ............................
SN55119
SN55121
SN55122
SN55138
SN55150
SN55152
SN55154
SN55157
SN55158
SN55182
SN55183
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2-9
2-9
2-15
2-15
2-9
2-9
2-21
2-29
2-21
2-37
2-37
2-37
2-37
2-45
2-45
2-45
2-45
4-5
4-5
4-13
4-13
4-13
4-13
4-23
4-23
4-23
4-23
5-5
5-9
5-13
5-17
4-31
4-35
4-35
4-43
4-47
4-53
4-57
5-19
4-73
4-73
4-73
4-73
4-89
4-89
4-101
4-113
4-121
4-131
4-131
4-131
4-131
4-143
4-147
4-181
4-205
4-223
4-237
4-255
4-261
4-377
4-385
PAGE NO.
DEVICe
SN55188 ............................
SN55189 ............................
SN55189A ...........................
SN5520 .............................
SN5522 .............................
SN55234 ............................
SN5524 .............................
SN55325 ............................
SN55326 ............................
SN55327 ............................
SN55426B ...........................
SN55427B ...........................
SNf;5450B ...........................
SN55451B ...........................
SN56452B
SN55453B
SN55454B
~~~1
............................ .
SN55462 ............................
SN55463 ............................
SN55464 ............................
SN55471 ............................
SN55472 ............................
SN55473 ............................
SN55474 ............................
SN55500E ...........................
SN55501E ...........................
5N55551 ............................
SN55552 ............................
SN55553 ............................
SN55554 ............................
SN55ALS 192 .........................
SN65176B ...........................
SN65500E ...........................
SN65501E ...........................
SN65508 ............................
SN65509 ............................
SN655128 ...........................
SN655138 ...........................
SN65518 ............................
SN65551 ............................
SN65552 ............................
SN65553
SN65554
SN65555
SN65556
SN65557
SN65558
SN65559
SN65560
SN65563
SN65564
SN65567
SN65568
SN75061
SN75064
SN75065 ............................
SN75066 ............................
SN75067 ............................
SN75068 ............................
SN75069 ............................
SN75107A ...........................
TEXAS
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INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
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4-391
4-397
4-397
6-3
6-15
6-35
6-25
6-45
6-55
6-55
3-3
3-3
5-81
5-81
5-81
5-81
5-il1
5-93
5-93
5-93
5-93
5-109
5-109
5-109
5-109
3-17
3-29
3-79
3-79
3-95
3-95
4-481
4-351
3-23
3-35
3-41
3-47
3-53
3-59
3-71
3-87
3-87
3-101
3-101
3-109
3-109
3-117
3-117
3-125
3-125
3-133
3-133
3-141
3-141
4-63
5-23
6-23
5-23
5-23
5-29
5-29
4-73
C
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(II
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iii
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Q)
C
Q)
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1-3
ALPHANUMERIC INDEX
DEVICE
SN75107B ......................•.....
SN75108A ........................... .
SN75108B ........................... .
SN75109A ....... : ................... .
SN75110A ........................... .
SN75111 ............................ .
SN75112 ............................ .
SN75113 ......................... .
SN75114 ............................ .
SN75115 ............................ .
SN75116 ............................ .
SN75117 ............................ .
SN75118 ............................ .
SN75119 ............................ .
SN75121 ............................ .
SN75122 •............................
SN75123 ............................ .
SN75124 ............................ .
SN75125 ............................ .
SN75127 ............................ .
SN75128 ............................ .
SN75129 ............................ .
SN75136 ............................ .
SN75138 ........................... .
SN75140 ............................ .
SN75141 ............................ .
SN75146 ............................ .
SN75150 ............................ .
SN751506 ........................... ,
SN751508 ........................... .
SN75151 ............................ .
SN751516 ........................... .
SN751518 ........................... .
SN75152 ..................... .
SN75153 ............................ .
SN75154 ............................ .
SN75155 ............................ .
SN75157 ............................ .
SN75158 ............................ .
SN75159 ............................ .
SN75160B ........................... .
SN75161B ........................... .
SN75162B ........................... .
SN75163B ........................... .
SN75164B ........................... .
SN75172 ............................ .
SN75173 ............................ .
SN75174 ............................ .
SN75175 ............................ .
SN75176B ........................... .
SN75177B ........................... .
SN75178B ........................... .
SN75179B ........................... .
SN75182 ............................ .
SN75183 ............................ .
SN75188 ............................ .
SN75189 ............................ .
SN75189A ........................... .
SN75207 ............................ .
SN75207B ........................... .
SN75208 ............................ .
SN75208B ........................... .
1-4
PAGE NO.
4-73
4-73
4-73
4-89
4-89
4-97
4-89
4-101
4-113
4-121
4-131
4-131
4-131
4-131
4-143
4-147
4-153
4-157
4-163
4-163
4-169
4-169
4-175
4-181
4-191
4-191
4-199
4-205
3-153
3-161
4-211
3-153
3-161
4-223
4-211
4-2S7
4-245
4-255
4-261
4-269
4-281
4-289
4-289
4-301
4-309
4-319
4-327
4-335
4-343
4-351
4-361
4-361
4-371
4-377
4-385
4-391
4-397
4-397
4-405'
4-405
4-405
4-405
DEVICE
SN75372 ............................ .
SN75374 ............................ .
SN75407 ............................ .
SN75408 ............................ .
SN75435 ............................ .
SN75436 ............................ .
SN75437A ........................... .
SN75438
................... .
SN75440 ........................ .
SN754410 ........................ .
SN754411 ........................ .
SN75446 ............................ .
SN75447 ............................ .
SN75448 ............................ .
SN75449
SN75451B
SN75452B
SN75453B
SN75454B
SN75461
SN75462
SN75463
SN75465
SN75466
SN75467
SN75468
SN75469
SN75471
SN75472
SN75473 ............................ .
SN75476 ......................... .
SN75477 ............................ .
SN75478 ............................ .
SN75479 ....................... .
SN75491 ............................ .
SN75491A ....................... .
SN75492 ............................ .
SN75492A ........................... .
SN75494 ............................ .
SN75500E ........................... .
SN75501E ........................... .
SN75508 ............................ .
SN75509 ............................ .
........................... .
........................... .
~7elH
~7el~
SN75514
SN75518
SN75551
SN75552
SN75553
SN75554
SN75555
SN75556
SN75657
SN75558
SN75559
SN75560
'SN75563
SN75564
SN75567
SN75568
SN75581
............................ .
............................ .
............................ .
............................ .
........................ .
...................... .
..................... .
............................ .
............................ .
............................ .
............................ .
............................ .
............................ .
............................ .
............................ .
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TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
PAGE NO.
5-33
5-43
5-53
5-53
5-57
5-63
5-63
5-63
5-69
5-153
5-159
5-75
5-75
5-75
5-75
5-81
5-81
5-81
5-81
5-93
5-93
5-93
5-101
5-101
5-101
5-101
5-101
5-109
5-109
5-109
5-117
5-117
5-117
5-117
3-7
3-7
3-7
3-7
3-15
3-23
3-35
3-41
3-47
3-53
3-59
3-65
3-71
3-87
3-87
3-101
3-101
3-109
3-109
3-117
3-117
3-125'
3-125
3-133
3-133
3-141
3-141
3-149
ALPHANUMERIC INDEX
DEVICE
SN75603
SN75604
SN75605
SN75608 ............................
SN75609 ............................
SN75ALS126 .........................
SN75ALS130 .................... .
SN75ALS160
........ .
SN75ALS161 .........................
SN75ALS162 .........................
SN75ALS163 ................. .
SN75ALS164 .........................
SN75ALS165 ....................... .
SN75ALS192 .........................
SN75ALS193 .........................
SN75ALS194 .........................
SN75ALS 195 .........................
TL0808 ..............................
TL0809...
. ............... " ....
TL182C ..............................
TL1821 ...................... .
TL182M ..
. ............ .
TL185C ....................... .
TL1851 ....................... .
TL185M .............................
TL188C ..............................
TL1881 ..............................
TL188M ........................ .
TL191C ..............................
TU911 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TL191M .............................
TL376C ..............................
TL48108 .............................
TL4810BI ............................
TL500C ..............................
TL501C ..............................
TL502C ..............................
TL503C ..............................
TL505C ..............................
TL507C ..............................
TL5071 ..............................
TL5812 ..............................
TL581~ .............................
TL601C ..............................
TL6011 ..............................
TL601M .............................
TL604C ..............................
TL6041 ..............................
TL604M .............................
TL607C ..............................
TL6071 ..............................
TL607M ....... _.....................
TL610C ..............................
TL6101 ..... .. . ..
. ...............
TL610M .............................
TLC04 ............. ' .................
TLC0820AC ..........................
TLC0820AI ...........................
TLC0820AM ..........................
TLC0820BC ..........................
TLC0820BI ...........................
TLC0820BM ..........................
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PAGE NO.
5-123
5-123
5-123
5-133
5-143
4-413
4-419
4-425
4-435
4-443
4-453
4-461
4-471
4-481
4-489
4-501
4-511
2-57
2-57
2-65
2-65
2-65
2-65
2-65
2-65
2-65
2-65
2-65
2-65
2-65
2-65
5-165
3-171
3-171
2-71
2-71
2-71
2-71
2-85
2-91
2-91
3-177
3-177
2-97
2-97
2-97
2-97
2-97
2-97
2-97
2-97
2-97
2-97
2-97
2-97
2-103
2-113
2-113
2-113
2-113
2-113
2-113
DEVICE
TLC1O ............................... .
TLC1205AI ........................... .
TLC1205BI ........................... .
TLC1225AI ........................... .
TLC1225BI ........................... .
TLC14 ............................... .
TLC15401 ............................ .
TLC1540M ........................... .
TLC15411 ............................ .
TLC1541M ........................... .
TLC20 ............................... .
TLC320401 ........................... .
TLC32040M .......................... .
TLC40161 ............................ .
TLC4016M ........................... .
TLC40661 ............................ .
TLC4066M ........................... .
TLC532AI ............................ .
TLC532AM ........................... .
TLC533AI ............................ .
TLC533AM ........................... .
TLC5401 ............................. .
TLC540M ............................ .
TLC541I ............................. .
TLC541M ............................ .
TLC5431 ............................. .
TLC543M ............................ .
TLC5441 ............................. .
TLC544M ............................ .
TLC5451 ............................. .
TLC545M ............................ .
TLC5461 ............................. .
TLC546M ............................ .
TLC548C ............................ .
TLC5481 ............................. .
TLC548M ............................ .
TLC549C ............................ .
TLC5491 ............... c ............. .
TLC549M ............... , ............ .
TLC7135 ............................. .
TLC7136C ........................... .
TLC7524C ........................... .
TLC75241 ............................ .
TLC7528C ........................... .
TLC75281 ............................ .
TLC7533 ............................. .
TSP50C40A .......................... .
TSP50C50 ........................... .
TSP5110A ........................... .
TSP5220C ........................... .
TSP60C20 ........................... .
TSP6100 ............................. .
uA9636AC ....................... .
uA9637AC ........................... .
uA9637AM ........................... .
uA9638C ............................'.
uA9639C ............................ ,
UCN4810A , , .. , .............. , ...... ,.
UDN2841 ... , .... , .... , ... , .......... .
UDN2845 ....... , , ........ , .......... .
ULN2001A ........ , .. , , . , ... , ... , , , , .,
ULN2002A , ... , ... , ........ , .. , . , ... , .
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
PAGE NO.
2-123
2·181
2-181
2-181
2-181
2-103
2-197
2-197
2-197
2-197
2-123
2-271
2-271
2-205
2-205
2-213
2-213
2-139
2-139
2-139
2-139
2-149
2-149
2-149
2-149
2-157
2-157
2-157
2-157
2-165
2-165
2-165
2-165
2-173
2-173
2-173
2-173
2-173
2-173
2-221
2-233
2-243
2-243
2-251
2'251
2-263
7-3
7-7
7-11
7-15
7-19
7-23
4-523
4-529
4-529
4-535
4-539
3-183
5-169
5-169
5-173
5-173
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1-5
ALPHANUMERIC INDEX
DEVICE
UlN2003A ...........................
UlN2004A ...........................
UlN2005A ...........................
UlN2064 ............................
UlN2065 ............................
UlN2066 ............................
UlN2067 ............................
UlN2068 ............................
UlN2069 ............................
UlN2074 ............................
UlN2075 ............................
1-6
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PAGE NO.
5-173
5-173
5-173
5-181
5-181
5-181
5-181
5-187
5-187
5-193
5-193
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SELECTION GUIDE
DATA ACQUISITION CIRCUITS
c
o
cu
Single-Slope and Dual-Slope AID Converters
',;::
RESOLUTION
CONVERSION
FUNCTION
SPEED (ms)
TYPE
4112 Bits
Dual-Slope Analog
TL500
8-10 Bits
Processors
TL501
PACKAGE
...E
PAGE
2-71
J
'2:71
N
t---
4 1/2 Digits
80
TL502
with Seven-Segment
Digital Processors
50
2-71
TL503
with BCD Outputs
10-Bits
2-71
Q)
Outputs
4 1/2 Digits
.e
.5
e
Digital Processors
Dual-Slope Analog
cQ)
e,:,
~
TL505
Pulse-Width
7-Bits
Modulator for
1
TL507
Single-Slope
P
2-91
Converter
4 1/2 Digits
Dual-Slope ADC
34
3112 Digits
N
Dual-Slope ADC
333
2-221
TlC7135
with BCD Output
t--2-233
TLC7136
with LCD Drivers
DIA Converters (5 to 15 Volts)
RESOLUTION
8 Bits
8 Bits
10 Bits
FUNCTION
TYPE
Single Multiplying DAC
TLC7524
Dual Multiplying DAC
TLC7528
Single Multiplying DAC
TLC7533
SETTLING TIME
100 ns
150 ns
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
PACKAGE
PAGE
D,N
2-243
N
2-251
I 2-263
1-7
SELECTION GUIDE
DATA ACQUISITION CIRCUITS
~
:sCD
i
~
3
ao·
Successive-Approximation AID Converters
ADDRESS
CONVERSION
AND
SPEEDt
DATA I/O
I"sl
FORMAT
100
:s
PARALLEL
1
15
30
10
84
SERIAL
13
25
22
25
13
25
22
25
31
31
52
UNADJUSTED
POWER
RESOLUTION
ERROR
TYPE
DISSIPATION
BITS
IMAXI
(TYPI
DEDICATED DIGITAlf
±LSB
0.5
ADC0803
1§
ADC0804
1.0
0
ADC0805
10mW
0.75
ADC0808
0.75
ADCOS08M
1.25
8
ADCOS09
8
0.75
TlOS08
0.5mW
1.25
Tl0809
1.0
TLC0820A
1
35mW
TLC0820B
0.5
TLC532A
5
6
6mW
TLC533A
1.0
TLC1205A
TLC1205B
0.5
1§
12 Plus Sign
25mW
0
1.0
TLC1225A
0.5
TLC1225B
1.0
ADC0831A
1§
0.5
ADC0831B
1.0
ADC0832A
2§
0.5
ADC0832B
10mW
1.0
ADC0834A
4§
0.5
ADC-Q834B
1.0
ADC0838A
B
ADC0838B
TLC540
11
0
TLC541
8
TLC543
5
TLC544
0.5
TLC545
19
6mW
TLC546
TLC548
1
TLC549
TLC1540
11
10
1.0
TLC1541
SIGNAL INPUTS.
ANALOG
21
ANALOG
#
TLC32040
14
200mW
PACKAGE
PAGE
N
7i5
FN,N
FK,JD
2-21
2-29
2-21
2-9
FN,N
'2-9
2-57
'2-57
FN,N
FK,J
FN,N
2-113
2-139
'2-i39
2-181
N,J
~
~
2-181
2-37
P
N
r-t37
'2-37
'2:37
2-45
'2-45
2-45
FN,N
D,N
FN,N
D,P
FN,N
N
~
I 2-149
I 2-149
I 2-157
2-157
I 2-165
2-165
2-173
I 2-173
2-197
I 2-197
2-271
t Includes access time.
t Analog/digital inputs can be used either as digital logic inputs or inputs for analog to digital conversion. For example: The TLC532/3A
can have 11 analog inputs, 5 analog inputs and 6 digital inputs, or any combination in between.
§ Differential Input .
• The TLC32040 has two differential inputs for the 14 bit AID and a serial port input for the 14 bit D/A.
ttThe AID conversion accuracy for this device is measured in terms of signal-ta-quantization distortion and also in LSB over certain converter
ranges. Please refer to the data sheet.
1-8
TEXAS ~
INSTRUMENTS
POST OFFICE eox 856012 • DAllAS. TeXAS 75265
SELECTION GUIDE
DATA ACOUISITION CIRCUITS
c:
o
Analog Switches and Multiplexers
FUNCTION
TYPICAL
VOLTAGE
POWER
IMPEDANCE
RANGE
SUPPLIES
(OHMI
(VI
(VI
150
DUAL SPST
100
TWIN DUAL SPST
150
SPOT
±10
±15
100
DUAL SPOT
SPST WITH ENABLE
100
SPST WITH LOGIC INPUTS
QUAD BILATERAL
80
ANALOG SWITCH
30
-17 to +25
±25
2 to 12
12
PACKAGE
TL1B5
PAGE
2-65
N
2-65
E
o
.E
TL191
2-65
TL601
2-97
'ii
Q)
c:
Q)
2-97
c:J
TL18B
TL604
TL607
P
TLC4016
TLC4066
2-65
2-97
2-97
TL6l0
50
.
-..
ca
TYPE
TL1B2
100
TWIN SPOT
~
N,D,J
2-205
2-213
Switched-Capacitor Filter ICs
POWER
FILTER
ORDER
SUPPLIES
DUAL FILTER, GENERAL PURPOSE
2
±4 to ±5
LOW PASS, BUTTERWORTH
4
±2.5 to ±6
FUNCTION
TYPE
PACKAGE
PAGE
FN,N
~
D,P
~
(VI
TLC10
TLC20
TLC04
TLC14
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-123
2-103
1-9
SELECTION GUIDE
DISPLAY DRIVERS
Q
CD
:::I
CD
Electroluminescent Display Drivers
i
DESCRIPT
DRVRS
INPUT
PER PKG
COMPP.TIBILITY
POWER
SUPPLY'
5'
...0-
...o·3
PRODUCT FEATURES
TYPE
PKG
•
225-V open-drain OM OS outputs
SN55551
FD
3-79
•
Serial-in, parallel-out architecture
SN65551
•
50-rnA current sink output capability
SN75551
!'N,N
3-87
FD
3-79
FN,N
3-87
PAGE
• Extremeiy low steady state power
AI
SN55552
consumption
•
:::I
(SNXX552) drivers
32
VCCl
(logic)
ROW
DRIVER
Left side (SNXX551) and right side
CMOS
=
•
10.8 V •
Monolithic BIDFET integrated circuits
Very low steady-state power
consumption
to 15 V
34
enh~nce
circuit layout
300-mA output capability
SN65558
High-voltage open-collector N-P-N outputs
SN75558
•
225-V totem-pole BIDFET output structures
•
70-mA output capability
•
Very low steady-state power consumption
SN65564
Selectable Open-Source or Open-Drain output
SN75564
•
60-V totem-pole BIDFET output structures
•
Serial-in, parallel-out architecture
COLUMN
DRIVERS
32
90-V output voltage swing capability
•
1 5-mA output source and sink current
CMOS
capability
High-speed serially-shifted data input
•
T ctem-pole outputs
•
Latches on all driver outputs
•
Energy recovery system compatible
• 80-V totem-pole BIDFET output structures
•
Serial-in, parallel-out architec~ure
•• Top (SNXX559) and bottom (SNXX560)
3-117
FN
I--3-133
SN75563
•
•
3-117
I---
SN66563
• 3-State capabilities
10.8 V •
to 15 V
SN65557
SN75557
•
drivers enhance circuit layout
=
SN75552
•
15":mA sink or source output capability
•• Top
(SNXX553) and bottom (SNXX554)
VCC1
(logic)
SN65552
SN55553
SN65553
SN75553
SN55554
SN65554
I--3-133
FD
3-95
FN,N
3-101
FD
3-95
3-101
SN75554
I---
SN65555
3-109
SN75555
FN,N
I---
SN65556
3-109
SN75556
SN65559
SN75659
FN,N
3-125
FN,N
3-125
15-mA sink or source output capability
drivers enhance circuit layout
•
VCCl
(logic)
= 4.5
V
to 5.5 V
Energy recovery sys~em compatible
• 4.5-V to 5.5-V VCCl operation at 5 MHz
•
Two Parallel high-speed l6-bit shift registers
• 60-V totem-pole BIDFET output sUuctures
1 5-mA sink or source output capability
•• Top (SNXX567) and bottom (SNXX568)
drivers enhance circuit layout
1-10
TEXAS ...,
INSTRUMENTS
POST OFFICE BOX 665012 • OAU.AS. TEXAS 75265
SN65560
SN75560
SN65567
3-141
SN75567
FN
SN65568
SN75568
3-141
SELECTION GUIDE
DISPLAY DRIVERS
c
o
LED Display Drivers
DESCRIPT
SEGMENT
DRIVERS
DIGIT
DRIVERS
"';:;
DRVRS
INPUT
POWER
PER PKG
COMPATIBILITY
SUPPLY
10 V
4
•
20 V
MOS
6
10 V
50-rnA source/sink capability
TYPE
PKG
PAGE
SN75491
3-7
SN75491A
SN75492
SN75492A
•
250-mA sink capability
Variable from
•
250-mA sink capability
3.2 V to 8.8 V
•
Display blanking provisions
•
•
•
Serial·in, parallel-Qut architecture
60-V totem-pole outputs
SN65512B
25-mA current source output capability
SN75512B
•
On-board latches
Ail features same as SN65512B except
SN65513B
•
Shift register reset replaces latches
SN75513B
20 V
.
.
co
PRODUCT FEATURES
N
3-7
-
SN75494
3-15
E
o
c
iii
II)
c
II)
c:;J
Vacuum Fluorescent Display Drivers
DESCRIPT
DRVRS
INPUT
POWER
PER PKG
COMPATIBILITY
SUPPLY
VCCI lIogic)
~5Vto15V
VCC2 Idisplay)
TTL
=OVt060V
PRODUCT FEATURES
PKG
PAGE
DW,N
3-53
I
V CC 1 (logic)
= 5 V to 15 V,
12
TYPE
VCC2, (display)
DW,N
3-59
DW,N
3-65
FN,N
3-71
=OVto60V
V CC 1 (logic)
= 5 V to 15 V,
ANODE,
CMOS
GRID
DRIVERS
DR DDT
All features same as SN655128 except
SN75514
•
125-V totem-pole output
All features same as SN655128 except
SN65518
•
32 bits for large format displays
SN75518
VCCI (logic)
•
Serial-in. parallel-out architecture·
=5Vto15V
•
60-V totem-pole outputs
VCC2 (display)
•
40-mA current source output capability
=OVt060V
•
Second source to Sprague UCN-4810A
to 60 V
SEGMENT
MATRIX
VCC2, VCC3,
(display) = 0 V
32
CMOS. TTL
FORMATS
• VCCI (logic)
i = 5 V to 15 V.
VCC2. (display)
=OVt060V
10
CMOS. TTL
10
VCCI (logic)
CMOS
~5Vto15V
VCC2 (display)
=OVto60V
20
•
Serial~in,
•
60-V totem-pole outputs
•
40~mA
•
Improved direct replacement for
UCN4810A
N
3-183
DW.N
3-171
FN.N
3-177
parallel-out architecture
current source output capability
TL4810B
TL4810BI
UCN4810A and TL4810A
•
•
•
70-V output voltage swing capability
Drives up to 20 lines
TL5812
Direct replacement for Spragup.
TL58121
UCN5812A
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
1-11
SELECTION GUIDE
DISPLAY DRIVERS
.~
DC Plasma Display Drivers
:I
...
CI)
DESCRIPT
!!.
:;
.....
...o
3
III
DRVAS
INPUT
POWER
PER PKG
COMPATIBILlTV
SUPPLY
ROW
PRODUCT FEATURES
•
•
VCC liogic)
DRIVERS
•
=4Vt06V
TVPE
PKG
220-mA parallel output sink current
Left side (SN751506) and right side
(SN751516) drivers enhance circuit
SN751506
3-153
SN751516
layout
o
32
:I
CMOS
•
VCC liogic)
= 4.5 V to
5.5 V
COLUMN
DRIVERS
I---
- 120-V open collector P-N-P parallel
• outputs
!:t.
FT
Two parallel high-speed 16-bit
shift registers
•
•
PAGE
lBO-V open drain parallel. output
Latches on all driver outputs
Top (SN75150B) and bottom
(SN75151B) drivers enhance circuit
SN75150B
SN751518
3-161
layout
ANODE
DRIVERS
VCC+ = 4.5 V
to 5.5 V
•
7
TTL
•
VCC- =
-10.B V to
Serial· in, parallel-out architecture
100-V output capability
•
Alternative driver for VF
•
Independent addressing of each gate
SN75581
J,N
3·149
TVPE
PKG
PAGE
-13.2 V
AC Plasma Display Drivers
DESCRIPT
DRVRS
PER PKG
INPUT
COMPATIBILITY
POWER
PRODUCT FEATURES
SUPPLY
for serial and parallel applications
VCCl (logic)
= 10Vto
4
14~
VCC2 (display)
=40Vt090~
32 (B-bits
with 1
AXIS
DRIVERS
to 13.2 V
CMOS
V CC2 (display)
= 0 V to 100
32
32 x 1
•
= 10.8 V
selectors)
•
•
•
•
30-mA integral clamp diodes on outputs
Switches 70 V in 1.2 ~s
3-input AND function (SN55426B)
~
High-speed serial-in, parallel-out
Fast output transitions
«
150 ns)
•
X-axis driver ISNXX500)
•
V-axis driver (SNXX501)
SN55501E
•
Military temperature packages available
(SN55500, SN55501)
'-12
•
3-3
SN65501E
SN75501E
FD,JD
3-17
FN,N
3-23
FD
JD
FN,N
SN65508
High-speed serial-in, parallel-out
=VCCl to 90 V •
X-axis driver (SNCC508)
V-axis driver (SNXX508)
plus 2
VCCl liogic)
•
=8 Vto 11.4 V
select
V CC2 (display)
bits)
SN65500E
SN75500E
to 9.35 V
32 (8 bits
SN55500E
• 25·mA output current capability
VCCl liogic)
= 7.65 V
VCC2 (display)
J
SN55427B
NAND function (SN55427B)
architecture IMHz)
VCCl (logic)
of 4
•
SN55426B
High input impedance 1 MO typically
FN
SN75509
=VCCl to 90 V
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TeXAS 75265
3-35
3-41
SN75508
SN65509
3-29
I--3-47
SELECTION GUIDE
LINE DRIVERS AND RECEIVERS
I:
o
Line Drivers
APPLICATION
.~
OUTPUT
DRIVERS
DEVICE
PER PACKAGE
TYPE
SN55158
2
EIA STANDARD RS-422-A
DIFFERENTIAL
4
EIA STANDARD RS-485
DIFFERENTIAL
4
EIA STANDARD RS-423-A
SINGLE-ENDED
2
EIA STANDARD RS-232-C
SINGLE-ENDED
2
4
2
IBM 360/370
GENERAL PURPOSE
GENERAL PURPOSE
SINGLE-ENDED
SINGLE-ENDED
DIFFERENTIAL
4
2
2
PKG
SN75158
JG
D,JG,P
PAGE
NI,.IMBER
4-261
SN75159
D,J,N
4-269
uA9638
D,JG,P
4-535
AM26LS31
D,FK,J,N
4-5
MC3487
D,J,N
4-53
SN75151
DW,J,N
SN75153
J,N
SN75172
J,N
4-319
SN75174
4-335
4-211
SN55ALS192
J,N
J,FK
SN75ALS192
D,J,N
SN75ALS194
D,J,N
4-501
SN75172
J,N
4-319
SN75174
J,N
4-335
uA9636A
SN55150
D,JG,P
JG,FK
4-523
D,JG,P
D,JG,P
SN55188
J,FK
SN75188
D,J
SN75123
D,J,N
4-153
SN75ALS126
D,J,N
4-413
SN75ALS130
D,J,N
4-419
SN55121
FK,J
D,J,N
D,J,N
SN55109A
FK,J
SN75109A
D,J,N
SN55110A
FK,J
SN75110A
D,J,N
4-391
4-143
4-43
4-89
SN75111
D,J,N
4-97
D,J,N
4-89
SN55113
FK,J
SN75113
D,J,N
SN55114
FK,J
D,J,N
SN55183
FK,J
SN75183
D,J,N
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265
I:
CD
C!J
4-523
SN75112
SN75114
CD
4-205
SN75150
MC3453
iii
4-481
uA9636A
SN75121
.E
.s
.
.2
4-101
4-113
4-385
1-13
SELECTION GUIDE
LINE DRIVERS AND RECEIVERS
C)
G)
line Receivers
:::s
G)
i-
APPLICATION
OUTPUT
RECEIVERS
DEVICE
PER PACKAGE
TYPE
S"
0...
2
3
...
III
c)"
EIA STANDARD RS-422-A
DIFFERENTIAL
4
:::s
4
EIA STANDARD RS-485
DIFFERENTIAL
4
2
EIA STANDARD RS-423-A
SINGLE-ENDED
4.
2
EIA STANDARD RS-232-C
SINGLE-ENDED
4
3
IBM 360/370
SINGLE-ENDED
7
8
GENERAL PURPOSE
1-14
SINGLE-ENDED
2
PKG
PAGE
NUMBER
SN75146
D,JG,P
SN55157
JG
SN75157
D,JG,P
uA9637A
D,JG,P
4-529
uA9639
D,JG,P
4-539
AM26LS32A
D,FK,J,N
4-13
MC3486
D,J,N
4-47.
SN75173
D,J,N
4-327
SN75175
D,J,N
4-343
SN75ALS193
J
4-489
SN75ALS195
J
4-511
SN75173
D,J,N
4-327
SN75175
D,J,N
4-343
SN75146
D,JG,P
4-199
SN75157
D,JG,P
4-255
uA9637A
D,JG,P
4-529
uA9639
D,JG,P
4-539
AM26LS32A
D,FK,J,N
4-13
MC3486
D,J,N
4-47
SN75173
D,J,N
4-327
SN75175
D,J,N
4-343
SN75ALS193
SN75ALS195
J
J
4-489
4-511
SN55152
J,FK
SN75152
D,J,N
SN55154
J,FK
SN75154
D,J,N
SN55189
J,FK
4-199
4-255
4-223
4-237
SN75189
D,J,N
SN55189A
J,FK
SN75189A
D,J,N
SN75124
D,J,N
4-157
D,J,N
4-163
DW,J,N
4-169
SN75125
SN75127
SN75128
SN75129
SN55122
FK,J
SN75122
D,J,N
SN75140
D,JG,P
SN75141
D,JG,P
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-397
4-147
4-191
SELECTION GUIDE
LINE DRIVERS AND RECEIVERS
I:
o
line Receivers (Continued)
'';::
APPLICATION
OUTPUT
RECEIVERS
DEVICE
PER PACKAGE
TYPE
SN55107A
2
GENERAL PURPOSE
DIFFERENTIAL
4
D,J,N
SN55107B
FK,J
SN75107B
D,J,N
SN5510BA
FK,J
SN7510BA
D,J,N
SN5510BB
FK,J
SN7510BB
D,J,N
SN55115
FK,J
ca
iii
4-73
Q)
I:
Q)
"
4-121
D,J,N
SN551B2
FK,J
SN751B2
D,J,N
SN75207
D,J,N
SN75207B
D,J,N
SN7520B
D,J,N
SN7520BB
AM26LS33A
D,J,N
D,FK,J,N
4-13
MC3450
D,J,N
4-35
MC3452
D,J,N
4-35
655012 • DALLAS, TEXAS 75265
.
.2
.
E
I:
SN75115
TEXAS ."
eqx
PAGE
NUMBER
FK,J
SN75107A
INSTRUMENTS
POST OFFICE
PKG
4-377
4-405
1-15
SELECTION GUIDE
LINE DRIVERS AND RECEIVERS
~
Line Transceivers
:::J
CD
!i
APPLICATION
EIA STANDARD RS-232-C
BUS 1/0
TRANSCEIVERS
PER PACKAGE
SINGLE-ENDED
1
DIFFERENTIAL
1
SN75155
SN65176B
SN75176B
SN75177B
4
SN75178B
SN75179B
MC3446
S-
O'
...
3
I»
EIA STANDARD RS-422-A
AND
EIA STANDARD RS-485
P+
o·:::J
EIA STANDARD 488 GPIB
SINGLE-ENDED
8
DEVICE
TYPE
DIFFERENTIAL
1
4
SINGLE-ENDED
8
1
DW,J,N
DW,J,N
DW,J,N
DW,J,N
4-281
4-425
4-289
4-435
SN751628
SN75ALS162
DW,N
DW,N
DW,N
4-289
4-443
4-309
DW,N
DW,J,N
DW,J,N
D,J,N
4-461
4-471
D,J,N
D,J,N
4-23
4-57
D,J,N
FK,J
D,J,N
4-175
DW,J,N
4-301
DW,J,N
FK,J
D,J,N
4-453
SN75061
AM26S10C
AM26S11C
N8T26
SN75136
SN75163B
SN75ALS163
SN75117
SN55118
SN75118
SN55119
SN75119
TEXAS.
1-16
INSTRUMENlS
POST
OFF!C~
4-361
SN75160B
SN75ALS160
SN751618
SN75ALS161
SN55116
SN75116
SN55117
DIFFERENTIAL
4-351
4-371
4-31
SN55138
SN75138
GENERAL PURPOSE
D,JG,P
D,JG,P
D,JG,P
D,JG,P
D,JG,P
PAGE
NUMBER
4-245
D,JG,P
D,J,N
SN75164B
SN75ALS164
SN75ALS165
IEEE 802.3 1BASE5
PKG.
BOX 655012 • DALLAS, TEXAS 752:65
FK,JG
D,JG,P
J,FK
D,J,N
FK,JG
D,JG,P
4-63
4-23
4-181
4-131
SELECTION GUIDE
PERIPHERAL DRIVERS/ACTUATORS
r:::
o
General Purpose Drivers and Actuators
"';;
OFFSWITCHING
OUTPUT DRIVERS OUTPUT
STATE
INPUT
VOLTAGE
CURRENT
PER
CLAMP
VOLTAGE
CAPABILITY
MAX (VI
(mAl
PACKAGE DIOOES
MAX (VI
20
30
300
2
NO
TTL
NO
TTL
20
30
300
2
300
NO
TTL
20
30
2
20
30
300
NO
TTL
2
20
30
300
NO
TTL
2
2
20
30
300
TTL
NO
2
20
30
300
NO
TTL
2
20
30
300
NO
TTL
2
20
30
300
NO
TTL
2
24
24
500
YES
TTL
4
24
24
500
YES
TTL
30
35
300
NO
TTL
2
2
30
35
300
NO
TTL
2
30
35
300
NO
TTL
2
35
300
NO
TTL
30
2
30
35
300
NO
TTL
30
35
300
NO
TTL
2
35
300
30
2
NO
TTL
70
TTL,CMOS
4
35
YES
500
35
70
600
YES
TTL,CMOS
4
70
CMOS,MOS,TTL
4
600
35
YES
70
TTL,CMOS
4
1000
35
YES
35
50
1250
YES
TTL
4
35
50
1250
YES
4
MOS
35
50
1250
YES
TTL,5 V MOS
4
35
50
1500
TTL,5 V MOS
4
NO
4
35
50
1500
NO
TTL,5 V MOS
4
35
50
1250
YES
TTL
35
50
1250
YES
MOS
4
35
YES
TTL,CMOS
4
1250
50
4
TTL,CMOS
35
50
1250
NO
2
55
70
YES
TTL,CMOS
350
55
70
350
2
YES
TTL,CMOS
55
70
350
2
YES
TTL,CMOS
TTL,CMOS
2
55
70
350
YES
2
50
70
500
YES
TTL,CMOS
50
70
2
500
YES
TTL,CMOS
4
50
70
500
YES
TTL,CMOS
7
50
50
350
YES
TTL,CMOS,PMOS
7
50
50
350
YES
25 V PMOS
7
50
50
YES
TTL,CMOS
350
7
50
50
350
YES
15 V MOS
7
50
50
350
YES
TTL
FUNCTION
AND
AND
NAND
OR
NOR
AND
NAND
OR
NOR
MOS DRIVER
MOS DRIVER
AND
NAND
OR
NOR
AND
NAND
OR
INVERT W ENAB
INVERT W ENAB
BUFFER W ENAB
INVERT W ENAB
INVERT
INVERT
INVERT
INVERT
INVERT
INVERT
INVERT
INVERT
INVERT
AND
NAND
OR
NOR
NAND
OR
INVERT W ENAB
INVERT
INVERT
INVERT
INVERT
INVERT
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
DELAY
TIME
TYP
(nsl
20
18
25
18
26
18
25
18
26
35
35
28
38
28
35
28
38
28
1050
750
1450
1050
500
500
500
500
500
500
500
500
500
300
300
300
300
500
500
1050
250
250
250
250
250
ca
TYPE
SN55450B
SN55451B
SN55452B
SN55453B
SN55454B
SN75451B
SN75452B
SN75453B
SN75454B
SN75372
SN75374
SN55461
SN55462
SN55463
SN55464
SN75461
SN75462
SN75463
SN75437A
SN75435
SN75440
SN75438
SN75064
SN75066
SN75068
UDN2841
UDN2845
ULN2064
ULN2066
ULN2068
ULN2074
SN75446
SN75447
SN75448
SN75449
SN75407
SN75408
SN75436
ULN2001A
ULN2002A
ULN2003A
ULN2004A
ULN2005A
PKG
PAGE
FK,J 5-81
r-FK,JG 5-81
FK,JG ~
FK,JG ~
FK,JG ~
D,P ~
D,P ~
D,P
D,P ~
D,P 5-33
D,N 1 5-33
FK,JG 5-93
FK,JG ~
r-FK,JG 5-93
FK,JG 1 5-93
D,P ~
D,P '5:93
D,P
NE
5-63
r-NE
5-57
NE 1 5-69
NE 1 5-63
NE ~
NE ~
NE
NE 1 5-169
NE : 5-169
NE
5-181
NE 1 5-181
NE : 5-187
NE
5-193
D,P
5-75
D,P ~
D,P ~
D,P ~
D,P
D,P
NE 1 5-63
D,N 1 5-173
D,N 1 5-173
D,N 1 5-173
D,N : 5-173
D,N 5-173
r--s:-s;-
E
...
....or:::
ca...
Q)
r:::
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"
'5:93
'5-29
'5-53
'5:53
1-17
SELECTION GUIDE
PERIPHERAL. DRIVERS/ACTUATORS
~
General Purpose Drivers and Actuators (Continued)
.
i
SWITCHING
!!!.
VOLTAGE
S'
o
MAXIVI
-
50
3
50
50
50
t»
!:to
o
50
50
:2
OFFSTATE
VOLTAGE
MAXIVI
.80
80
80
8Q
80
OUTPUT DRIVERS
CURRENT
PER
ImAI
OUTPUT
CLAMP
PACKAGE DIODES
1500
4
4
1500
1500
1500
4
4
INPUT
CAPABILITY
FUNCTION
YES
YES
YES
TTL
MOS
TTL,5 V MOS
INVERT
INVERT
INVERT
YES
YES
YES
TTL
MOS
TTL,5 V MOS
INVERT
INVERT
INVERT
DELAY
TIME
TYP
TYPE
SN75065
SN75067
NE
NE
500
500
500
SN75069
ULN2065
ULN2067
NE
NE
500
500
28
ULN2069
ULN2075
SN55471
1500
1500
4
4
1500
4
300
300
2
2
NO
NO
NO
TTL,5 V MOS
TTL
TTL
INVERT
AND
NAND
55
55
70
70
70
300
300
300
2
2
NO
NO
OR
NOR
38
28
35
SN55472
SN55473
SN55474
55
55
55
55
70
70
70
70
300
300
300
300
2
2
AND
NAND
28
38
SN75471
SN75472
2
2
2
NO
NO
NO
YES
YES
TTL
TTL
TTL
OR
AND
NAND
28
200
55
55
70
70
300
2
YES
60
60
60
60
100
100
100
300
100
2
4
350
360
7
7
YES
YES
YES
YES
350
350
350
7
7
YES
YES
7
YES
50
55
55
55
60
60
60
80
80
70
70
100
100.
TTL
TTL
TTL,CMOS
TTL,CMOS
TTL,CMOS
TTL,CMOS
OR
200
200
NOR
200
TTL,CMOS,MOS TELECOM RY DRV 1000
INVERT
250
TTL
TTL,CMOS,PMOS INVERT
250
25 V PMOS
TTL,CMOS
15 V MOS
INVERT
INVERT
INVERT
PKG
Insl
500
500
250
250
250
NE
NE
SN75479
DS3680
SN75465
SN75466
SN75467
SN75468
SN75469
5-23
5 -23
1 5 - 29
1 5 - 181
1
: 5-181
5-187
1 5- 193
NE
FK,JG 5 109
1 FK,JG 1 5- 109
FK,JG 5-109
FK,JG : 6-109
D,P 1 5- 109
D,P
SN75473. D,P
SN75476 D,P
SN75477 D,P
SN75478
PAGE
D,P
D,P
1
5-109
5- 109
: 5-117
5-117
1 5- 117
1 5- 117
D,J,N 5-5
D,N : 5-101
D,N 1 5- 101
D,N
5-101
D,N
D,N
: 5-101
5-101
Motor Drivers and Power Actuators
SWITCHING
VOLTAGE
MAXIVI
18
36
36
36
36
40
VOLTAGE
MAXIVI
18
36
36 '
36
36
40
OUTPUT
CURRENT
DRIVERS OUTPUT
. CLAMP
PER
ImAI
PACKAGE DIODES
500
600
1000
1000
1000
3
4
4
'4
4
1
INPUT
FUNCTION
CAPABILITY
DELAY
TIME
TYP
TTL,MOS,CMOS
HALF-H DRIVER
TTL
TTL
HALF-H DRIVER
HALF-H DRIVER
600
600
YES
NO
TTL,CMOS
TTL,CMOS
TTL,CMOS
HALF-H DRIVER
600
600
40
1
YES
YES
46
46
60
40
46
46
60
2000
1000
2000
2500
1
1
2
2
YES
YES
NO
YES
60
60
2500
2
YES
TYPE
PKG
PAGE
Insl
NO
YES
NO
2000
2000
40
40
1-18
OFFSTATE
TTL,CMOS
TTL,CMOS
TTL
TTL
TTL,CMOS
TTL,CMOS
HALF-H DRIVER
HALF-H DRIVER
HALF-H DRIVER
TL376C
..If
TEXAS
INSTRUMENlS
POST OFFICE BOX 656012 • DAlL.AS, TEXAS 75266
~
5-13
5-9
~
5-159
SN754411 NE
SN75603 KC,KH,K
SN75604 KC,KH,K
SN75605 KC,KH,KI 5-123
PBL3717
NE
5-i9
L298
KV
SN75608 KV
"6-i23
~
HALF-H DRIVER
STEPPER DRIVER
FULL-H DRIVER
ACTUATOR
ACTUATOR
NE
L293D
NE
L293
NE
SN754410 NE
5-i7
800
800
ti33
SN75609
KV
5-i43
SELECTION GUIDE
MEMORY INTERFACE CIRCUITS
c
o
Core-Memory Drivers
MAX OUTPUT
tpo
CURRENT
TYP
600 mA
",0:;
DEVICE
PKG
OUTPUTS
45 ns
VCCI = 5 V
VCC2 = 4.5 V to 24 V
DUAL SOURCE, DUAL SINK
SN55325
FK,J
6-45
40 ns
VCC =5 V
QUADRUPLE SINK
SN55326
J
6-55
35 ns
VCCI = 5 V
VCC2 = 4.5 V to 24 V
QUADRUPLE SOURCE
SN55327
J
6-55
TYPE
('0
PAGE
POWER SUPPLIES
E
...
NUMBER
.2
.E
"!CD
c
CD
o
tpD - Propagation Delay Time
Core-Memory Sense Amplifiers
THRESHOLD
tpo
SENSITIVITY
TYP
±15 mV
UNITS PER PACKAGE
DEVICE
TYPE
PKG
PAGE
NUMBER
35 ns
1
RESISTOR
SN5520
J
6-3
30 ns
1
OPEN COLL OR RESISTOR
SN5522
J
6-15
2
RESISTOR
SN5524
J
6-25
2
RESISTOR
SN55234
J
6-35
25 ns
±7 mV
TYPE OF OUTPUT
2B ns
2
TOTEM POLE
SN55236
SN75236
WC
See
Note 1
tpD - Propagation Delay Time
NOTE 1: For additional information, contact your nearest TI field sales office.
MOS-Memory Sense Amplifiers
THRESHOLD
tpo
SENSITIVITY
TYP
UNITS PER PACKAGE
TYPE OF OUTPUT
17 ns
2
TOTEM POLE
19 ns
2
OPEN COLLECTOR
25 ns
2
2
TOTEM POLE
OPEN COLLECTOR
±25 mV
±10mV
25 ns
DEVICE
TYPE
PKG
PAGE
NUMBER
SN55107A
FK,J
SN75107A
D,J,N
4-73
4-73
SN5510BA
FK,J
4-73
SN7510BA
D,J,N
4-73
SN75207
D,J,N
SN75208
D,J,N
4-405
4-405
tpD - Propagation> Delay Time
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
1-19
SELECTION GUIDE
SPEECH SYNTHESIS CIRCUITS
PROCESS
PMOS
DESCRIPTION
LPC-l0 VOICE SYNTHESIZER, 4-BIT CONTROL BUS
PACKAGE
LPC-l0 VOICE SYNTHESIZER, 8-BIT CONTROL BUS
N
128K-BIT ROM FOR TSP5110A AND TSP5220C
MICROPROCESSOR, SYNTHESIZER, 64K-BIT ROM
CMOS
256K-BIT ROM FOR TSP50C4X, TSP50C50 FAMILIES
LPC- 12 HIGH-QUALITY VOICE SYNTHESIZER WITH 6-POLE
LOW-PASS FILTER
1-20
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012. DALLAS, TEXAS 75265
N
J,N
DEVICE TYPE
PAGE
TSP51 lOA
7-11
TSP5220C
7-15
TSP6100
7-23
TSP50C40A
7-3
TSP60C20
7-19
TSP50C50
7-7
Alphanumeric Index
Selection Guide
Data Acquisition Circuits
Cross-Reference Guide
Data Sheets
Data Sheets
Cross-Reference Guide
Data Sheets
Cross-Reference Guide
Data Sheets
Data Sheets
Data Sheets
2-1
•
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2-2
DATA ACQUISITION CIRCUITS
CROSS·REFERENCE GUIDE
CROSS·REFERENCE GUIDE
(manufacturers arranged alphabetically)
Replacements were based on similarity of electrical and mechanical characteristics as shown in currently published
data. Interchangeability in particular applications is not guaranteed. Before using a device as a substitute, the
user should compare the specifications of the substitute device with the specifications of the original.
Texas Instruments makes no warranty as to the information furnished and buyer assumes all risk in the use
thereof. No liability is assumed for damages resulting from the use of the information contained in this list.
ANALOG
DEVICES
AD570JN
AD7512DIJN
AD7512DIJQ
AD7512DIKN
AD7512DIKQ
AD7512DISD
AD7512DITD
AD7533
AD7524JN
AD7524AD
AD7528LN
AD7528CQ
AD7820
BURR-BROWN
AD7533
AD7820
ADC82AG
ADC82AM
DATEL
ADC-830C
ADC-EK12DC
TI
DIRECT
REPLACEMENT
TI
FUNCTIONAL
REPLACEMENT
ADC0803CN
TL 182CN
TL 1821N
TL18'2CN
TL1821N
TL182MJ
TL182MJ
TLC7533
TLC7524CN
TLC75241N
TLC7528CN
TLC75281N
TLC0820
TI
DIRECT
REPLACEMENT
TLC7533
TLC0820
TI
FUNCTIONAL
REPLACEMENT
TLC0820BIN
TLC0820AIN
TI
DIRECT
REPLACEMENT
ADC0803CN
TI
FUNCTIONAL
REPLACEMENT
TLC7135CN or
TLC7136CN or
TL5001 113CN
TLC7135CN or
TLC7136CN or
TL500/1/3CN
ADC-EK12DR
TI
FUNCTIONAL
REPLACEMENT
TL5071N
FUJITSU
MB4053P
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012. DALLAS, 'fEXAS 75265
PAGE
NO.
2-9
2-65
2-65
2-65
2-65
2-65
2-65
2-263
2-243
2-243
2-251
2-251
2-113
c:
0
'+,
';
'S
C'
(J
«
ca
ca
~
C
PAGE
NO.
2-263
2-113
2-113
2-113
PAGE
NO.
2-9
2-221
2-233
2-71
2-221
2-233
2-71
PAGE
NO.
2-91
2-3
DATA ACQUISITION CIRCUITS
CROSS·REFERENCE GUIDE
INTERSIL
..
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ADC0803LCD
ADC0803LCN
ADC0804LCD
ADC0804LCN
DGM182AK
DGM182BJ
DGM185AK
DGM1858J
DGM188AK
DGM188BJ
DGM191AK
DGM191BJ
ICL7106CPL
ICL7126CPL
ICL7135CPI
ICL7136CPL
TI
DIRECT
REPLACEMENT
ADC08031N
ADC0803CN
ADC08041N
ADC0804CN
TL182MN
TL182CNIIN
TL185MN
TL185CNIIN
TL188MN
TL188CN/IN
TL191MN
TL191CNIIN
TI
FUNCTIONAL
REPLACEMENT
TL604MP
TL604CP/IP
TL604MP
TL604CP/IP
TL610MP
TL610CP/IP
TL610MP
TL610CP/IP
TLC7136CN
TLC7136CN
TLC7135CN
TLC7136CN
PAGE
NO.
2-9
2-9
2-15
2-15
2-97
2-97
2-97
2-97
2-97
2-97
2-97
2-97
2-233
2-233
2-221
2-233
CO)
r::
:+
en
HARRIS
HF10
LINEAR
TECHNOLOGY
LTC1060ACN
LTC1060CN
MAXIM
MF10BN
MF10CN
ICL7135
TI
DIRECT
REPLACEMENT
TLC10
2-123
TI
DIRECT
REPLACEMENT
TLC10N
TLC20N
PAGE
NO.
2-123
2-123
TI
DIRECT
REPLACEMENT
TLC10N
TLC20N
TLC7135
PAGE
NO.
2-123
2-123
2-221
TI
FUNCTIONAL
REPLACEMENT
TLCOB20ACN
TLC0820BCN
TLCOB20ACN
TLC0820BCN
MICRO
NETWORKS
MN5100/5101
MN5120/5130/5140
TI
FUNCTIONAL
REPLACEMENT
TLC7135CN
TL500/1l3CN
ADC08061N series
ADC0804CN or
ADC0805CN series
ADC0808NI
ADC809N
MICRO
POWER SYSTEMS
MP7138AN
MP7574AD/BD
MP7574JN/KN
MP75811JN/KNI
AD/BD
2-4
PAGE
NO.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76265
PAGE
NO.
2-113
2-113
2-113
2-113
PAGE
NO.
2-221
2·71
2-9
2-15
2-9
2-21
2·21
DATA ACOUISITION CIRCUITS
CROSS·REFERENCE GUIDE
MOTOROLA
TI
DIRECT
REPLACEMENT
MC1405L
MC14433P
MC14442L
MC14442P
MC14443P
MC14444P
MC14447P
MC145040FN
MC145040L
MC145040P
MC54HC4016J
MC74HC4016J
MC74HC4016N
MC54HC4066J
MC74HC4066J
MC74HC4066N
TLC533AMJ
TLC533AIN
NATIONAL
DIRECT
REPLACEMENT
TLC541MFN
TLC541MJ
TLC541MN
TLC4016MJ
TLC40161N
TLC40161N
TLC4066MJ
TLC40661N
TLC40661N
TI
ADC0803LCD
ADC0803LCN
ADC0804LCD
ADC0604LCN
ADC0805LCN
ADC0808CCJ
ADCOBOBCCN
ADC0809CCN
ADC0811BCJ
ADC0811BCN
ADC0811BCV
ADC0811BJ
ADCOBllCCJ
ADCOBllCCN
ADCOBllCCV
ADCOBllCJ
ADCOB20BCD
ADCOB20BCN
ADC0820BD
ADC0820CCD
ADC0820CCN
ADC0820CD
ADC0829BCN
ADC0829CCN
ADC0830BCN
ADC0830CCN
ADC0831BCJ
ADCOB31BCN
ADCOB31CCJ
ADC0831CCN
ADC0832BCJ
ADC0832BCN
ADC08031N
ADC08031N
ADC08041N
ADC0804CN
ADC08051N
ADC0808N
TL0808N
ADCOB08N
TLOB08N
ADC0809N
TL0809N
TLC5411N
TLC541IN
TLC5411FN
TLC541MJ
TLC541IN
TLC541IN
TLC5411FN
TLC541MJ
TLC0820BIN
TLC0820BCN
TLC0820BMJ
TLC0820AIN
TLC0820ACN
TLC0820AMJ
TLC533AIN
TLC533AIN
ADC0831BIP
ADC0831BCP
ADC0831AIP
ADC0831ACP
ADC0832BIP
ADC0832BCP
TI
FUNCTIONAL
REPLACEMENT
TL500CN
TL501CN
TL505CN
TLC7135CN or
TL500/1/3CN
TLC532AMJ
TLC532AIN
TL5071N
TLC5461N
TL5071P
TLC540MFN
TLC540MJ
TLC540MN
TI
FUNCTIONAL
REPLACEMENT
TLC5401N
TLC540lN
TLC540lFN
TLC540MJ
TLC540lN
TLC540lN
TLC540lFN
TLC540MJ
TLC532AIN
TLC532AIN
TLC5461N
TLC5461N
TLC5491N
TLC5491N
TLC5491N
TLC5491N
TLC5441N
TLC5441N
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
PAGE
NO.
2-71
2-71
2-85
2-221
2-71
2-139
2-139
2-91
2-165
2-91
2-149
2-149
2-149
2-205
2-205
2-205
2-213
2-213
2-213
c:
0
'';::
'iii
'S
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U
4(
ca
1ii
C
PAGE
NO.
2-9
2-9
2-15
2-15
2-9
2-21
2-57
2-21
2-57
2-21
2-57
2-149
2-149
2-149
2-149
2-149
2-149
2-149
2-149
2-113
2-113
2-113
2-113
2-113
2-113
2-139
2-139
2-165
2-165
2-173
2-173
2-173
2-173
2-157
2-157
2-5
DATA ACQUISITION CIRCUITS
CROSS,REFERENCE GUIDE
(continued)
NATIONAL
:::;'
ADC0832CCJ
ADCOB32CCN
ADCOB34BCJ
ADC0834BCN
ADC0834CCJ
ADC0834CCN
ADC0838BCJ
ADC0838BCN
ADCOB38CCJ
ADC0838CCN
ADC1001CCJ
ADC1005BCJ
ADC1005CCJ
ADC1205
ADC1225
C
ADC3511CCN
..
C
I»
I»
l>
(')
.Q
C
iii'
;::j.'
e)"
;:,
(')
(')
;::j.'
en
TI
DIRECT
REPLACEMENT
ADC0832AIP
ADC0832ACP
ADCOB34BIN
ADC0834BCN
ADC0834AIN
ADC0834ACN
ADC083BBIN
ADC0838BCN
ADC0838AIN
ADC0838ACN
TLC1205
TLC1225
TLC7135CN or
TL500/1/3CN
TLC7135CN or
TL500/1/3CN
TLC7136CN or
TL500/1/2CN
TLC 7136CN or
TL500/1/2CN
ADC3711CCN
ADD3701CCN
TLC10CN
TLC20CN
TLC4016MJ
TLC4066MJ
TLC40161N
TLC40661N
TLC04
TLC14
TI
FUNCTIONAL
REPLACEMENT
TLC7524CN
TLC75241N
TLC752B
TLC7533
PRECISION
MONOLITHICS
PM7524HP
PM7524FQ
PM7528
PM7533
RCA
CD4016AD
CD4016AE
CD4066AD
CD4066AE
CA3162E
2-6
\
TLC15411N
TLC15411N
TLC15411N
ADD3501CCN
MF10BN
MF10CN
MM54HC4016J
MM54HC4066J
MM74HC4016N/J
MM74HC4066N/J
MF4-50
MF4·100
TI
FUNCTIONAL
REPLACEMENT
TLC5441N
TLC5441N
TI
DIRECT
REPLACEMENT
TLC4016MJ
TLC40161N
TLC4066MJ
TLC40661N
TI
FUNCTIONAL
REPLACEMENT
TL50 1CN/TL503CN
.
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 ,. DALLAS, TEXAS 7fi26S
PAGE
NO.
2·157
2-157
2-45
2-45
2-45
2-45
2-45
2-45
2-45
2-45
2-197
2-197
2-197
2-181
2·181
2-221
2-71
2-221
2·71
2-233
2-71
2-233
2-71
2·123
2-123
2-205
2·213
2-205
2-213
2-103
2-103
PAGE
NO.
2·243
2-243
2-251
2-263
PAGE
NO.
2·205
2·205
2·213
2·213
2·71
DATA ACQUISITION CIRCUITS
CROSS"REFERENCE GUIDE
SIGNETICS
ADCOB03/4/5-1 LCN
ADCOB04-1CN
NE5034F
NE5036FE/N/D
TI
DIRECT
REPLACEMENT
ADCOB03/4/51N
ADC0804CN
TLC532AIN
TLC549CN/CD
TLC549CN/CD
NE5037F/N/D
SILICONIX
TI
DIRECT
REPLACEMENT
DG182AP
DG182BP
DG185AP
DG185BP
DG188AP
DG188BP
DG191AP
DG191BP
TL182MN
TL182CNIIN
TL185MN
TL185CN/IN
TL188MN
TL188CNIIN
TL191MN
TL191CNIIN
LD110CJ
LLD111ACJ
LD120CJ
LD121ACJ
Si520DJ
Si7135CJ
TELEDYNE
TSC7106CPL
TSC7126
TSC7126ACPL
TSC7135CPI
TSC8700
TSC8701
TSCB703
TSC8704
TSC14433CN
TI
FUNCTIONAL
REPLACEMENT
TI
FUNCTIONAL
REPLACEMENT
TL610MP
TL610CPIIP
TL604MP
TL604CPIIP
TL604MP
TL604CPIIP
TL604MP
TL604CPIIP
TL503CN or
TLC71350N
TL501CN or
TLC7135CN
TL500CN or
TLC7135CN
TL503CN or
TLC7135CN
ADC0808N
ADC0809N
TLC7135CN
TI
DIRECT
REPLACEMENT
TI
FUNCTIONAL
REPLACEMENT
TLC7136CN
TLC7136CN
TLC7136CN
TLC7135CN
ADC0808N
TLC15411N
ADC080BN
TLC15411N
TLC7135CN
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
PAGE
NO.
2-9
2-15
2-139
2-173
2-173
PAGE
NO.
e
2-97
2-97
2-97
2-97
2-97
2-97
2-97
2-97
2-71
2-221
2-71
2-221
2-71
2-221
2-71
2-221
2-21
2-21
2-221
"';::;
0
"US
"S
CI"
U
«
....asas
Q
PAGE
NO.
2-233
2-233
2-233
2-221
2-21
2-197
2-21
2-197
2-221
2-7
•
2-8
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • .DAlLAS, ,TEXAS 75265
ADC0803, ADC0805
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH DIFFERENTIAL INPUTS
02754, NOVEMBER 1983-REVISEO SEPTEMBER 1986
• 8-Bit Resolution
• Ratiometric Conversion
• 100 Conversion Time
• 135 ns Access Time
• Guaranteed Monotonicity
Reference Ladder Impedance
• High
8 kD Typical
• No Zero Adjust Requirement
• On-Chip Clock Generator
• Single 5-Volt Power Supply
Operates wit!1 Microprocessor or as
• Stand-Alone
N DUAL-IN-LINE PACKAGE
(TOP VIEWI
CS
fl.S
•
R5
WR
ClK IN
INTR
IN+
INANlG GND
REF/2
DGTl GND
VCC (OR REF)
ClK OUT
DBO (lSB)
DBl
DB2
DB3
DATA
DB4
OUTPUTS
DB5
DB6
DB7 (MSB)
II
~
.
"5
u
U
c
o
';:I
"iii
"5
C"
u
n
CLK 1191
OUT
iii'
;:;.'
:::s
CLKIN
~'
c
::+
en
DGTL 1101
GND
VCC
REF/2
10
CLK
C1
~~t:'
141
CLK
(')
---1-
S
CLKAP-R
.c
c
0'
"START"
FLIP·FLOP
GEN
CLK B
OSC
-
CLe
-+~-+
1201
LADDER
AND
DECOOER
191
-
LE
1
ANLG (81
GNO
DAC
SAR
LATCH
8·BIT
SHIFT
REGISTER
===
===
-+===
1 -----
--
.H
.4 to .
CLKA
C1
"---
~I
LE
EN
!!!!. DBO (LSBI
~DB1
3·STATE
OUTPUT
LATCH
~DB2
~DB3
~DB4
~DB5
.!.!!! DB6
.!!!! DB7 (MSBI
2-10
R
10
~
(71
~
Rf+
.. .~
IN-
"INTERRUPT"
..- R
VCC
(61
IN+ ~
0
TEXAS ~
INSTRUMENTS
POST OFFtCE BOX 655012 • DALLAS, TEXAS 75265
S
T -
V
INTR
ADC0803, ADC0805
8·BIT ANALOG·TO·DlGITAL CONVERTERS
WITH DIFFERENTIAL INPUTS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
. . . . . . . . . . . . . . . . . .. 6.5 V
Input voltage range es, RD, WR
. . . . . . . . . .. - 0.3 V to 18 V
Other inputs .
-0.3 V to Vee +0.3 V
Output voltage range. . . . . . . . . . . . . . . . . . . .
-0.3 V to Vee +0.3 V
Operating free-air temperature range: ADe080_1. . . . . . . . . . . . . . .
-40°C to 85°C
ADe080_e. . . . . . . . . . . . . .
. .. ooe to 70°C
Storage temperature range ....... . . . . . . . . . . . . . . . . . .
- 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260°C
....1/1
"S
...
(,)
U
c:
o
NOTE 1: All voltage values are with respect to digital ground (DGTL GNDI with DGTL GND and ANLG GND connected together unless
".t:'
otherwise noted.
"iii
"S
recommended operating conditions
C"
Supply voltage. VCC
Analog input voltage (see Note 2)
MIN
NOM
4.5
5
-0.05
0.25
Voltage at REF/2 (see Note 31, VREF/2
High-level input voltage at CS, RD, or WR, VIH
2.5
Low-level input voltage at CS, RD, or WR, VILClock input frequency (see Note 5). fclock
Duty cycle for fclock above 640 kHz (see Note 51
1
1460
100
NOTES:
ADC080_1
ADC080_C
V
0
Pulse duration, WR input low, tw(WR)
I
I
V
0.8
640
275
V
V
V
100
40%
UNIT
15
-0.05
Pulse duration, clock input (high or low) for fclock below 640 kHz, tw(CLK)
Operating free-air temperature, T A
6.3
VCC+ 0 .05
2
Analog ground voltage (see Note 41
MAX
(,)
«
....It!It!
C
V
kHz
60%
ns
781
ns
-40
85
0
70
°C
2. When the differential input voltage (VI + - VI_I IS less than or equal to 0 V, the output code is 0000 0000.
3. The internal reference voltage is equal to the voltage applied to REF/2 or approximately equal to one~half of the Vee when
REF/2 is left open. The voltage at REF/2 should be one-half the full-scale differential input voltage between the analog inputs.
Thus, the differential input voltage range when REF/2 is open and Vee = 5 V is 0 V to 5 V. VREF/2 for an input voltage
range from 0.5 V to 3.5 V (full-scale differential voltage of 3 VI is 1.5 V.
4. These values are with respect to DGTL GND.
5. Total unadjusted error is guaranteed only at an fclock of 640 kHz with a duty cycle of 40% to 60% (pulse duration 625 ns
to 937 ns). For frequencies above this limit or pulse duration below 625 ns, error may increase. The duty cycle limits should
be observed for an fclock greater than 640 kHz. Below 640 kHz, this duty cycle limit can be exceeded provided tw(CLK)
remains within limits.
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-11
ADCOB03, ADC0805
8·BIT ANALOG·TO·DIGITAL CONVERTERS
WITH DIFFERENTIAL INPUTS
electrical characteristics over recommended operating free·air temperature range. Vee
fclock = 640 kHz. VREF/2 = 2.5 V (unless otherwise notedl
PARAMETER
VOH
C
I»
At
VOL
l>
TEST CONOITIONS
High-level
All outputs
output voltage
DB and
Vee - 4.75 V,
lNm
=
Vee
4.75 V,
Low-level
Data outputs
VCC - 4.75 V,
output
INTR output
VCC
voltage
CLK OUT
= 4.75
IOH -
=
IOH
MIN
-360 ~A
2.4
-10pA
4.5
IOL
VCC - 4.75 V,
IOL
=
=
VT+
0.4
360 ~A
0.4
Clock negative-going
VT_
o·::::I
VT + - VT _ Clock input hysteresis
:=;"
n
~'
c
i:
threshold voltage
IIH
High-level input current
IlL
Low-level input current
IOZ
Off-state output current
Short-current
IOHS
output current
Short-circuit
IOLS
output current
3.1
3.5
V
1.5
1.8
2.1
V
0.6
1.3
2
1
-1
-3
Vo - 0
V
~A
~A
~A
Vo
=
5 V
Output high
Vo
=
0,
TA
=
25·C
-4.5
-6
mA
Output low
Vo
=
5 V,
TA
=
25·C
9
16
mA
TA
=
25·C,
3
VREF/2 - open,
CS = 5 V
reference current
Input resistance to
RREF/2
V
2.7
0.005
-0.005
Supply current plus
ICC
UNIT
0.4
1 mA
threshold voltage
iii'
MAX
V
IOL - 1.6 mA
V,
Clock positive-going
.Bc
Typt
5 V.
See Note 6
reference ladder
1.1
2.5
1.8
8
mA
kll
Ci
Input capacitance (control)
5
7.5
pF
Co
Output capacitance (OBI
5
7.5
pF
NOTE 6: Resistance is calculated from the current drawn from a 5-volt supply applied to pins 8 and 9.
operating characteristics over recommended operating free-air temperature. Vee
VREF/2 - 2.5 V. fclock - 640 kHz (unless otherwise noted I
PARAMETER
TEST CONDITIONS
= 4.5
Supply-voltage-variation error
VCC
Total adjusted error
With full-scale adjust,
Total unadjusted error
ADC0803
ADC0805
VREF/2
=
V to 5.5 V,
2.5 V,
ten
Output enable time @ 25·C
VREF/2 open,
See Notes 7 and 8
TA - 25"·C,
tdis
Output disable time·@ 25 ·C,
TA - 25·C, CL
td(lNTRI
Delay time to reset INTR @ 25·C
TA
DC common-mode error
tconv
Conversion cycle time @ 25·C
CR
Free-running conversion rate
t All typical
NOTES: 7.
8.
g.
2-12
=
=
MIN
See Note 7
=
LSB
±1/4
±1/2
See Notes 7 and 8
±1
=
100 pF
10 pF, RL - 10 kll
to WR,
UNIT
±1/2
CL
25·C,
MAX
±1/8
See Notes 7 and 8
fclock - 100 kHz to 1.46 MHz,
TA
Typt
±1/16
See Notes 7 and 8
25·C
iiii'fR connected
= 5 V.
See Note 9
CSatOV
66
LSB
LSB
±1/16
±1/8
LSB
135
200
ns
125
200
ns
300
450
73
8770
ns
clock
cycles
conv/s
values are at T A = 25 ·C.
These parameters are guaranteed over the recommended analog input voltage range.
All errors are measured with reference to an ideal straight line through the end-points of the analog-to-digital transfer characteristic.
Although internal conversion is completed in 64 clock periods, a CS or WR low-to-high transition is followed by 1 to 8 clock
periods before conversion starts. After conversion is completed, part of another clock period is required before a high-ta-Iow
transition of iiii'fR completes the cycle.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
ADC0803, ADC0805
8·BIT ANALOG·TO·DlGITAL CONVERTERS
WITH DIFFERENTIAL INPUTS
PARAMETER MEASUREMENT INFORMATION
_ __~__J/
\~_________
1414----a CLOCK PERIODS (MINI,----~~1
I
~~O~%
!
___________
tcI(lNTRI~
1
1
1
50'l1
~
~~O%
'S(,)
...
o
____-I-I_____________________________
I
c
o
'iii
1
':;l
I
I
1
________~I~
-----------------
= 4.75
All outputs
V, IOH
-10 p.A
Clock positive-going
n
VT+
threshold voltage
.Q
c
Clock negative-going
Iii'
::+
VTVT+ -VT-
Clock input hysteresis.
::s
IIH
High-level input current
O·
threshold voltage
(')
IlL
low-level input current
~.
10Z
Off-state output current
10HS
Short-circuit output current
I Output high
10LS.
Short-circuit output current
I
ICC
Supply current plus reference current
RREF/2
Ci
Input resistance to reference ladder
Input capacitance (control)
Co
Output capacitance (DB)
c
::+
III
MIN
TYpt
MAX
2.4
V
4.5
0.4
0.4
2.7
3.1
3.5
V
1.5
1.8
2.1
V
0.6
1.3
2
V
0.005
1
-1
I'A
-0.005
-3
3
Vo - 0,
TA - 25°C
-4.5
-6
Vo - 5 V,
REF/2 open,
TA - 25°C
es at 5 V,
9
16
TA = 25°e
See Note 6
V
0.4
Vo = 0
Vo - 5 V
Output low
UNIT
I'A
mA
mA
2.5
mA
5
7.5
kG
pF
5
7.5
pF
1.9
1
I'A
1.3
NOTE 6: The resistance is calculated from the current drawn from a 5-V supply applied to pins 8 and 9.
operating characteristics over recommended operating free·air temperature. Vee = 5 V,
VREF/2 - 2.5 V, fclock = 640 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Supply-voltage-variation error
Vce
(See Notes 2 and 7)
= 4.5
Total unadjusted error
VREF/2
(See Notes 7 and 8)
=
MIN
V to 5.5 V
(See Note 8)
ten
Output enable time
CL - 100 pF
tdis
Output disable time
Delay time to resel'iNTR
CL - 10 pF,
Conversion cycle time (See Note 9)
fclock
teenv
CR
I
Conve~sion
=
RL - 10 kG
100 kHz to 1.46 MHz
time
Free-running conversion rate
INTR connected to
CS at 0
MAX
UNIT
± 118
LSB
±1
LSB
±1/16
±1/8
LSB
135
200
ns
125
200
ns
300
450
2.5 V
DC common-mode error
td(lNTR)
TypT
±1/16
WR,
65%
72%
103
114
8827
V
ns
clock
cycles
p.S
conv/s
t All typical values are at T A = 25°C.
NOTES: 2. The internal reference voltage is equal to the voltage applied to REF/2, or approximately equal to one-half of the Vee when
REF/2 is left open. The voltage at REF/2 should be one-half the full-scale differential input voltage between the analog inputs.
Thus, the differential input voltage when REF/2 is open and VCC = 5 V is to 5 V. VREF/2 for an input voltage range from
0.5 V to 3.5 V (full-scale differential voltage of 3 V) is 1.5 V.
.
7. These parameters are guaranteed over the recommended analog input voltage range.
S. All errors are measured with reference to an ideal straight line through the end~points of the analog-to-digital transfer characteristic.
9. Although internal conversion is completed in 64 clock periods, a CS or WR low-to-high transition is followed by 1 to 8 clock
periods before conversion starts. After conversion is completed, part of another clock period is required before a high-to-Iow
transition of fIiJirI completes the cycle.
a
2-18
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75265
ADC08041, ADC0804C
8·BIT ANALOG·TO·DIGITAL CONVERTER
WITH DIFFERENTIAL INPUTS
timing diagrams
\\._____
_........,._......J!
1414----8 CLOCK PERIODS (MINII----+l~1
I
(II
i
~~50_%~-----------J~0%
I
~
~
u
(3
14-
·S
'd(lNTRlif
I
iNTii
..
I
...
.•••••••
I
I
I
50%
·S
C
o
50%
.~
I
ton-+l
'iii
~~~UTS -----------------cc :::::::
C'
u
..
( "6012 •
~"'L'A'. t&~A.
1628.
ADCOBoa, ADCOa09
CMOS ANALOG·TO·DlGITAL CONVERTERS
WITH a·CHANNEL MULTIPLEXERS
, 02642. JUNE 1981-REVISED FE8RUARY 1986
•
•
Resolution of B Bits
•
1001's Conversion Time
•
•
•
•
•
•
•
•
•
N
Total Unadjusted Error ... ± 0.75 LSB Max
for ADC0808 and ± 1.25 LSB Max for
ADCOB09
DUAL-iN-LINE PACKAGE
CTOPViEWI
INPUTS
{
!
II
201}INPUTS
:7
I/)
,t=
Ratiometric Conversion
.
C3
~
AeB} ADDRESS
START
EOe
2-5
OE
elK
Vee
REF+
GND
Guaranteed Monotonicity
No Missing Codes
Easy Interface with Microprocessors
Latched 3-State Outputs
Latched Address Inputs
u
6
9
ALE
2-1 (MSB)
2-2
2- 3
2- 4
2- S llSB)
REF-
.,oc
'0
'S
C"
~
2-7 ......_ _J-' 2- 6
Single 5·Volt Supply
Low Power Consumption
...caca
FN PACKAGE
Q
CTOPVIEWI
Designed to be Interchangeable with
National Semiconductor ADCOBOB.
ADCOB09
4
3
2 1 28 21 26
25
description
24
23
The ADCOB08 and ADC0809 are monolithic
22
CMOS devi,ces with an 8-channel multiplexer. an
21
8-bit analog-to-digital (AID) converter. and
10
20
microprocessor-compatible control logiC. The
11
19
8-channel multiplexer can be controlled by a
12 13 14 15 16 11 18
microprocessor through a 3-bit address decoder
+0,.....<0 I mV
with address load to select anyone of eight
u.. 2 I I u. (I) I
~(!)NN~:::!N
single-ended analog switches connected directly
ex>
to the comparator. The 8-bit AID converter uses
I
N
the successive-approximation conversion
technique featuring a high-impedance threshold detector. a switched-capacitor array. a sample-and-hold.
and a successive-approximation register (SAR). Detailed information on interfacing to most popular
microprocessors is readily available from the factory.
The comparison and converting methods used eliminate the possibility of missing codes. nonmonotonicity.
and the need for zero or full-scale adjustment. Also featured are latched 3-state outputs from the SAR
and latched inputs to the multiplexer address decoder. The single 5-volt supply and low power requirements
make the ADCOB08 and ADCOB09 especially useful for a wide variety of applications. Ratiometric
conversion is made possible by access to the reference voltage input terminals.
The ADC0808 and ADC0809 are characterized for operation from -40°C to 85°C.
PRODUCTION DATA documanllcontai. informati••
currant II of publi.ati.n d.ta. Pradum •••form to
_Ifillli.ns psr Ih. ta.... 01 T.... Instrumanta
ltaadard warr...,. Prodlction ,racessing dOli not
.......rily ind.... tasting of all parameters.
Copyright © 1983. TexBs Instruments Incorporated
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-21
ADCOBOB. ADCOB09
CMOS ANALOG·TO·DIGITAL CONVERTERS
WITH B·CHANNEL MULTIPLEXERS
functional block diagram (positive logic)
•
SAMPLE-AND-HDLD
BINARY-WEIGHTED
CAPACITORS
(12)
REF+ ~'-----I
REF- -'.:11.:;;6)'--_ _ _-1
C
...
I»
I»
l>
n
0(261
c
iii·
~
o
1 (271
.Q
SWITCH
MATRIX
,....---,1171 2-8 (LSBI
(141 2- 7
(151 241
2(28)
ANALOG
INPUTS
::::I
(")
3 111
4 (2)
OUTPUT
LATCHES
ANALOG
MULTIPLEXER
EN
L.......,r--....J
7 (51
CLOCK -,-11",0.:..1
_-+__--'
OUTPUT ENA8LE (OE)-'1"'91'---_f-_ _ _ _ _ _ _ _ _ _ _ _ _---J
•
1251'--...L....-"
ADDRESS C (23)
ADDRESS LOAD (221
ENABLE (ALE)
ADDRESS
DECODER
MULTIPLEXER FUNCTION TABLE
INPUTS
ADDRESS
SELECTED
ADDRESS
ANALOG
A
STROBE
CHANNEL
t
t
t
t
t
t
t
t
0
1
2
3
4
5
6
7
C
L -
B
L
L
L
L
H
L
H
L
L
H
H
H
H
L
L
L
H
H
H
L
H
H
H
H=
high level. L = low level
l = low·to-high transition
2-22
END OF
CONVERSION IEOCI
START CONVERSION ISTART)..:1"'61'-_+-_ _ _ _--'
~~~=::: (241
(211 :z-1 (MSBI
~_ _ _ _ _ _ _~_ _(~71
6 141
::+
en
DIGITAL
OUTPUTS
(191 2- 3
(201 2 _ 2
5 131
~r
c
(81 2-5
(181 2-4
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DAUAS. TEXAS 75265
ADC0808, ADC0809
CMOS ANALOG·TO·DIGITAL CONVERTERS
WITH 8·CHANNEL MULTIPLEXERS
operating sequence
CLOCK
!!!
START
CONVERSION
'5
...U
ADDRESS LOAD
ENABLE
:
\,
(3
,50%
1
c
tw(ALCI
.;
o
~ADDRESSSTABLE
ADDRESS
5O~50%1
:::A.lJo,
I
tsu+-r-;- th
ANALOG INPUT
"J..
MULTIPLEX OUTPUT
/lNTERNALI
\
I
I'
1
1
INPUT STABLE
OUTPUT
ENABLE
LATCH OUTPUTS
ANALOG VALuE:
~I_____________~;'~____J
I
END OF
CONVERSION
x~
-I
ANALOG VALUE
>
n
ADC0808
Typt
MAX
Rl
=
10 k!l
90
80
105
250
80
250
105
250
250
ns
ns
100
116
90
100
116
~s
14.5
0
14.5
~s
Delay time,
tdlEOel end of conversion
c
;::;.'
See Notes 8 and 9
0
output
en
tTypical values for all except supply voltage sensitivity are at Vee = 5 V, and all are at TA = 25°C.
NOTES:
4. Supply voltage sensitivity relates to the ability of an analog-ta-digital converter to maintain accuracy as the supply voltage
varies. The supply and V ref + are varied together and the change in accuracy is measured with respect to full-scale.
5. Linearity efror is the maximum deviation from a straight line through the end points of the AID transfer characteristic.
6. Zero error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input I(oltage.
7. Total unadjusted error is the maximum sum of linea~ty error, zero error, and full-scale error.
8. Refer to the operating sequence diagram.
9. For clock frequencies other than 640 kHz, td(EOC) maximum is 8 clock periods plus 2 "'s.
2·26
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
ADC0808. ADC0809
CMOS ANALOG·TO·DIGITAL CONVERTERS
WITH 8·CHANNEL MULTIPLEXERS
PRINCIPLES OF OPERATION
The ADC0808 and ADC0809 each consists of an analog signal multiplexer, an 8-bit successiveapproximation converter, and related control and output circuitry.
multiplexer
..
tn
The analog multiplexer selects 1 of 8 single-ended input channels as determined by the address decoder.
Address load control loads the address code into the decoder on a low-to-high transition. The output latch
is reset by the positive-going edge of the start pulse. Sampling also starts with the positive-going edge
of the start pulse and lasts for 32 clock periods. The conversion process may be interrupted by a new
start pulse before the end of 64 clock periods. The previous data will be lost if a new start of conversion
occurs before the 64th clock pulse. Continuous conversion may be accomplished by connecting the Endof-Conversion output to the start input. If used in this mode an external pulse should be applied after power
up to assure start up.
·3
E
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converter
The CMOS threshold detector in the successive-approximation conversion system determines each bit
by examining the charge on a series of binary-weighted capacitors (Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing switch Sc and all ST switches, and by
simultaneously charging all the capacitors to the input voltage.
;
Q
In the next phase of the conversion process, all ST and Sc switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference voltage.
In the switching sequence, all eight capacitors are examined separately until all 8 bits are identified, and
then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold
detector looks at the first capacitor (weight = 128). Node 128 of this capacitor is switched to the reference
voltage, and the equivalent nodes of all the other capacitors on the ladder are switched to REF -. If the
voltage at the summing node is greater than the trip-point of the threshold detector (approximately onehalf the VCC voltage), a bit is placed in the output register, and the 128-weight capacitor is switched
to REF -. If the voltage at the summing node is less than the trip point of the threshold detector, this
128-weight capacitor remains connected to REF + through the remainder of the capacitor-sampling (bitcounting) process. The process is repeated for the 64-weight capacitor, the 32-weight capacitor, and so
forth down the line, until all bits are counted.
With each step of the capacitor-sampling process, the initial charge is redistributed among the capacitors.
The conversion process is successive approximation, but relies on charge redistribution rather than a
successive-approximation register (and reference DAC) to count and weigh the bits from MSB to LSB.
.oo:~t~;'t~~J:t!;tt!~J:~~.tt!~tt!;,r~~
REF-
REF-
~i
REF-
REF-
REF-
REF-
REF-
iii i i
REF-
j
OUTPUT
LATCHES
REF-
i i
FIGURE 1. SIMPLIFIED MODEL OF THE SUCCESSIVE·APPROXIMATION SYSTEM
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-27
II
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2·28
ADC0808M
CMOS ANALOG·TO·DlGITAL CONVERTER
WITH 8·CHANNEL MULTIPLEXER
NOVEMBER 1986
•
•
•
•
•
•
•
•
•
•
•
•
Total Unadjusted Error ... ± 0.75 LSB Max
JD
•
DUAL-IN-LiNE PACKAGE
(TOPVIEWI
Resolution of 8 Bits
100 p.s Conversion Time
"rur{
Ratiometric Conversion
Guaranteed Monotonicity
No Missing Codes
r}INPUTS
START
EDe
2- 5
DEN
elK
Vee
REF+
GND
2- 7
Easy Interface with Microprocessors
Latched 3-State Outputs
Latched Address Inputs
Single 5-Volt Supply
Low Power Consumption
Designed to be Interchangeable with
National Semiconductor ADC0808CJ
"~~
~}ADDRESS
...
Co)
C3
ALE
2-1 (MSB)
2-2
2- 3
2- 4
2- 8 (lS8)
REF2- 6
c
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"5
C"
.:l
ca
;
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FK PACKAGE
(TOPVIEWI
description
The ADC0808M is a monolithic CMOS device
with an 8-channel multiplexer, an 8-bit analogto-digital (AID) converter, and microprocessorcompatible control logic. The 8-channel
mUltiplexer can be controlled by a microprocessor through a 3-bit address decoder with
address load to select anyone of eight singleended analog switches connected directly to the
comparator. The 8-bit AID converter uses the
successive-approximation conversion technique
featuring a high-impedance threshold detector,
a switched capacitor array, a sample-and-hold,
and a successive-approximation register (SAR).
Detailed information on interfacing to most
popular microprocessors is readily available from
the factory.
4321282726
5
25
6
24
7
23
8
22
9
10
21
20
11
19
12 13 14 15 16 17 18
+01'<0 I iii"
I
N
The comparison and converting methods used
eliminate the possibility of missing codes,
nonmonotonicity, and the need for zero or full-scale adjustment. Also featured are latched 3-state outputs
from the SAR and latched inputs to the multiplexer address decoder. The single 5-volt supply and low
power requirements make the ADC0808M especially useful for a wide variety of applications. Ratiometric
conversion is made possible by access to the reference voltage input terminals.
The ADC0808M is characterized for operation over the full military temperature range of - 55
PRODUCTION DATA documonls .ontain inlo",.'ion
.urrant •• of publi••,lo. d.te. Produ.,••onform 10
spo.ifi••,io.. por Iho terms of T.... Instrument.
::=~~8r:::le =:~:: :.o=£:.~ not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DAlLAS, TeXAS 75265
ac to 125 ac.
Copyrig,",t @ 1986, Texas Instruments Incorporated
2-29
ADC0808M
CMOS ANALOG·TO·~IGITAL CONVERTER
WITH 8·CHANNEL MULTIPLEXER
functional block diagram (positive logic)
•
SAMPLE-AND-HOLD
BINARY-WEIGHTED
CAPACITORS
REF+ ."11,,,21:--_""-_-1
REF- .:.,:11"'81'--_ _ _-1
SWITCH
MATRIX
THRESHOLD
DETECTOR
0(281
(171 2-8 (LSBI
(141
1 (271
2(281
ANALOG
INPUTS
OUTPUT
LATCHES
ANALOG
MULTIPLEXER
3 111
4 (21
7
(81 2-5
(181 2-4
(201 2 -2
1211 r1 (MBBI
5 (31
TIMING
EN
6 (41
AND
CONTROL
I---------ir--...:.:..:.. CONVERSION
171 END DF
CLOCK .:.,:(1"'01'--_+-_--1
START CONVERSION (STARTI ...:(.:;61'--_-t-_ _ _ _---'
--ll-----------------'
OUTPUT ENABLE IOEI_(:,:.9,-1
(25Ir-.........-.,
ADDRESS A (241
ADDRESS B (231 ADDRESS
DECODER
ADDRESSC
ADDRESS LOAD (221
ENABLE (ALEI
MULTIPLEXER FUNCTION TABLE
INPUTS
ADDRESS
ADDRESS
B
L
L
A
L
H
STROBE
CHANNEL
f
f
0
L
H
H
L
L
H
H
L
t
t
t
H
H
H
H
H
SELECTED
ANALOG
C
L
L
L
DIGITAL
OUTPUTS
(191 2 - 3
7 151
H
L
H
L
H
t
t
t
,
2
3
4
5
6
7
= high level, L = low level
t = low-to-high transition
2·30
r
1161 2-e
TEXAS . "
INSlRUMENlS
POST OFFICE $Ox 866012 • DAL.LAS, TEXAS 762S&
IEOCI
ADCOBOBM
CMOS ANALOG·TO·DIGITAL CONVERTER
WITH B·CHANNEL MULTIPLEXER
operating sequence
•..
CLOCK
START
CONVERSION
(I)
150%
"S
!---I- tw(S)
ADDRESS LOAD
ENABLE
E
twlAL,C)
~ ADDRESS STABLE
ADDRESS
Y"I"Vl
:::JII...l....J 50% 1I
50%
tsu~tJ,
ANALOG INPUT
](
,.
MULTIPLEX OUTPUT
(INTERNAL)
(j
50%
pi
, I
:
i
ANALOG VALUE
I
INPUT STABLE
::
:;
1
)<[
----+J
c
ANALOG VALuE:
x~
______________
OUTPUT
ENABLE
- - - - - - - - - - - - - - - - - -.....
LATCH OUTPUTS
tconv------'---I·I
{J
50"101
-t I"" ten
CD
CD
Q
,I--tel(EOC)
! ---1\'-5O%
___~,...----~i5O%
"
I
I'
..
c(
)C
~I""'''''''''''''''''''''''''''''''~;'~'''''~
c:T
U
pi
I
END OF
CONVERSION
o
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"S
+l
\50%
"'t
!--teli.
------------~H""I.izSSTT.A~TnE~~;r~;-------------~to~:~t--------J~
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 15265
2-31
ADC0808M
CMOS ANALOG·TO·DIGITAL CONVERTER
WITH 8·CHANNEL MULTIPLEXER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................. 6.5 V
Input voltage range: control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to 15 V
all other inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to Vee + 0.3 V
Operating free·air temperature range .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 °e to 125 °e
Storage temperature range ......................................... - 65 °e to 1 50 0 e
ease temperature for 60 seconds: FK package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260 0 e
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JD package ...... : .... 300 0 e
II
NOTE 1: All voltage values are with respect to network ground terminal.
recommended operating conditions
Supply voltage, VCC
Positive reference voltage, Vref+ (see Note 2)
MIN
NOM
MAX
4.5
5
6
vCC
0
5
Negative reference voltage, VrefDifferential reference voltage, Vref+ - VrefHigh-level input voltage, VIH
1.5
200
Address load control pulse duration, twIALC)
Address setup tima, tsu
Address hold time, th
200
50
50
10
-55
Clock frequency, f clock
Operating free-air temperature, TA
NOTE 2: Care must be taken that this rating is observed even during power-up.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
V
V
V
V
V
VCC-1.5
Low-level input voltage, VIL
Start pulse duration, tw(S)
2-32
VCC+O.l
-0.1
UNIT
640
1280
125
V
ns
ns
ns
ns
kHz
·C
ADC0808M
CMOS ANALOG·TO·DIGITAL CONVERTER
WITH 8·CHANNEL MULTIPLEXER
electrical characteristics over recommended operating free-air temperature range.
5.5 V (unless otherwise noted)
Vee -
4.5
V to
total device
PARAMETER
VOH
VOL
10Z
TEST CONDITIONS
= -360 ~A
= 1.6 mA
= 1.2 mA
Vo = VCC
High-level output voltage
Low-level output voltage
I
10
10
10
Data outputs
I End of conversion
Off-state Ihigh-impedance-state)
output current
Control input current at maximum input voltage
Vo - 0
VI = 15 V
IlL
Low-level control input current
VI
ICC
Ci
Supply current
Input capacitance, control inputs
Iclock - 640 kHz
TA = 25°C
Co
Output capacitance. data outputs
TA
II
MIN
Typt
0.3
10
10
25°C
Resistance Irom pin 12 to pin 16
UNIT
V
=0
=
MAX
VCC-O.4
0.45
0.45
V
3
-3
~
1
-1
~
3
mA
pF
pF
1000
•
~
kll
analog multiplexer
PARAMETER
Ion
loll
Channel on-state current (see Note 3)
Channel off-state current
TEST CONDITIONS
VI - Vcc.
VI = O.
Vcc = 5 V.
TA = 25·C
VCC = 5 V
I clock = 640 kHz
I clock = 640 kHz
VI = 5 V
VI - 0
VI = 5 V
VI = 0
MIN
Typt
MAX
2
-2
10
-10
z,oo
-200
1
-1
UNIT
~
nA
~A
t Typical values are at VCC = 5 V and T A = 25°C.
NOTE 3: Channel on-state current is primarily due to the bias current into or out 01 the threshold detector. and it varies directly with clock
Irequency.
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-33
ADcoaoaM
CMOS ANALOG-TO-DIGITAL CONVERTER
WITH a-CHANNEL MULTIPLEXER
•
operating characteristics. TA - 25°e. Vee" VREF+ .. 5 V. VREF- = 0 V. fclock
(unless otherwise noted)
TEST CONDITIONS
PARAMETER
kSVS
MIN
VCC = Vref+ = 4.5 V to 5.5 V,
See Note 4
TA = -55°C to 125°C,
Supply voltage sensitivity
Typt
640 kHz
MAX
UNIT
±0.05
%/V
Linearity error (see Note 5)
±0.25
LSB
Zero error (see Note 6)
±0.25
TA
Total unadjusted error (see Note 7)
=
=
±0.25
25°C
tpZL
Output enable time to low level
TA
-55°C to 125°C
See Figure 1
tpZH
Output enable time to high level
See Figure 1
tdis
Output disable time
See Figure 1
teonv
tdlEOCI
Conversion time
See Note 8 and 9 and Figure 1
See Notes 8 and 10 and Figure 1
Delay time, end of conversion output
LSB
±0.5
±0.75
90
0
LSB
90
150
250
ns
360
ns
200
100
405
116
~s
14.5
~s
ns
t Typical values for all except supply voltage sensitivity are at VCC = 5 V. and all are at TA = 25°C.
NOTES: 4. Supply voltage sensitivity relates to the ability of an analog-to-digital converter to maintain accuracy as the supply voltage
varies. The supply and Vref+ are varied together and the change in accuracy is measured with respect to full-scale.
5. Linearity error is the maximum deviation from a straight line through the end points of the AID transfer characteristic.
6. Zero error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
7. Total unadjusted error is the maximum sum of linearity error, zero error, and full-scale error.
8. Refer to the operating sequence diagram.
9. For clock frequencies other than 640 kHz. tconv is 57 clock cycles minimum and 74 clock cycles maximum.
10. For clock frequencies other than 640 kHz, td(EOC) maximum is 8 clock cycles plus 2 ps.
PARAMETER MEASUREMENT INFORMATION
Vec
TEST
POINT
5 kll
OUTPUT--~----------~--~~----.
100 pF
11.7 kll
FIGURE 1. TEST CIRCUIT
2-34
TEXAS
..If
INSTRUMENTS
POST OFFiCe sox 655012 • DALLAS. TEXAS 75266
ADC0808M
CMOS ANALOG-TO-DiGITAL CONVERTER
WITH 8-CHANNEL MULTIPLEXER
PRINCIPLES OF OPERATION
The ADC0808M consists of an analog signal multiplexer, an 8-bit successive-approximation converter,
and related control and output circuitry.
multiplexer
...
!II
The analog multiplexer selects 1 of 8 single-ended input channels as determined by the address decoder.
Address load control loads the address code into the decoder on a low-to-high transition. The output latch
is reset by the positive-going edge of the start pulse. Sampling also starts with the positive-going edge
of the start pulse and lasts for 32 clock periods. The conversion process may be interrupted by a new
start pulse before the end of 64 clock periods. The previous data will be lost if a new start of conversion
occurs before the 64th clock pulse. Continuous conversion may be accomplished by connecting the Endof-Conversion output to the start input. If used in this mode an external pulse should be applied after power
up to assure start up.
.
U
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u
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~
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converter
The CMOS threshold detector in the successive-approximation conversion system determines each bit
by examining the charge on a series of binary-weighted capacitors (Figure 2). In the first phase of the
conversion process, the analog input is sampled by closing switch Sc and all ST switches, and by
simultaneously charging all the capacitors to the input voltage.
...asas
Q
In the next p~ase of the conversion process, all ST and Sc switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference voltage.
In the switching sequence, all eight capacitors are examined separately until all 8 bits are identified, and
then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold
detector looks at the first capacitor (weight = 128). Node 128 of this capacitor is switched to the reference
voltage, and the equivalent nodes of all the other capacitors on the ladder are switched to REF -. If the
voltage at the summing node is greater than the trip-point of the threshold detector (approximately onehalf the VCC voltage), a bit is placed in the output register, and the 128-weight capacitor is switched
to REF -. If the voltage at the summing node is less than the trip point of the threshold detector, this
128-weight capacitor remains connected to REF + through the remainder of the capacitor-sampling (bitcounting) process. The process is repeated for the 64-weight capacitor, the 32-weight capacitor, and so
forth down the line, until all bits are counted.
With each step of the capacitor-sampling process, the initial charge is redistributed among the capacitors.
The conversion procesf is successive approximation, but relies on charge redistribution rather than a
successive-approximation register (and reference DAC) to count and weigh the bits from MSB to LSB.
Sc
~·:~t~;t~;t~;'t~;'t~~t~~t~;'t~;'~
REF-
REF-
~i
REF-
f f
REF-
REF-
j
REF-
REF-
REF-
LATCHES
REF-
11 i i i
FIGURE 2. SIMPLIFIED MODEL OF THE SUCCESSIVE-APPROXIMATION SYSTEM
TEXAS ~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-35
..
C
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c:
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;::;.'
0'
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en
2-36
ADC0831A, ADC0832A, ADC0831B, ADC0832B
AID PERIPHERALS WITH SERIAL CONTROL
02795, AUGUST 19S5-REVISED JUNE 1986
ADC0831 ••. P DUAl-IN-LiNE PACKAGE
•
8-Bit Resolution
•
Easy Interface to Microprocessors or
Stand-Alone Operation
•
Operates Ratiometrically or with 5-V
Reference
•
(TOPVIEWI
C S [ ] 8 VCC
2
7
ClK
IN+
INGNO
Single Channel or Multiplexed Twin
Channels with Single-Ended or Differential
Input Options
•
Input Range 0 to 5 V with Single 5-V
Supply
•
Inputs and Outputs are Compatible with
TTL and MOS
•
Conversion Time of 32 f.IS at
ClK - 250 kHz
•
Designed to be Interchangeable with
National Semiconductor ADC0831 and
ADC0832
DEVICE
3
4
6
5
DO
~
REF
..
"S
(,)
ADC0832 ..• P DUAl-IN-LiNE PACKAGE
[]B
(j
(TOPVIEWI
CS
CHO
CHl
2
3
GNO
4
7
6
5
C
o
VCC/REF
:E
ClK
DO
01
II)
"S
g-
ee
j!
ca
Q
TOTAL UNADJUSTED ERROR
A-SUFFIX
I
ADC0831
± 1 LSB
ADC0832
±1 LS8
I
B-SUFFIX
± Y, LSB
± Yo LSB
description
These devices are 8-bit successive-approximation analog-to-digital converters. The ADC0831A and
ADC0831 B have single input channels; the ADC0832A and ADC0832B have multiplexed twin input
channels. The serial output is configured to interface with standard shift registers or microprocessors.
Detailed information on interfacing to most popular microprocessors is readily available from the factory.
The ADC0832 multiplexer is software configured for single-ended or differential inputs. The differential
analog voltage input allows for common-mode rejection or offset of the analog zero input voltage value.
In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span
to the full 8 bits of resolution.
The operation of the ADC0831 and ADC0832 devices is very similar to the more complex ADC0834 and
ADC0838 devices. Ratiometric conversion can be attained by setting the REF input equal to the maximum
analog input signal value, which gives the highest possible conversion resolution. Typically, REF is set
equal to VCC (done internally on the ADC0832). For more detail on the operation of the ADC0831 and
ADC0832 devices, refer to the ADC0834/ADC0838 data sheet.
The ADC0831 AI, ADC0831 BI, ADC0832AI, and ADC0832BI are characterized for operation from -40°C
to 85°C. The ADC083 1 AC, ADC0831 BC, ADC0832AC, and ADC0832BC are characterized for operation
from ooC to 70 D C.
PROOUCTIOI DATA do.um_ .....in information
current as 01 public.tion data. ProdUeII conform
to speciIjcation. psr the term. 01 T.... lnstru_
IIIndani warranty. Production procsasing does not
necessarily iBel.ile tasting of III panmatars.
Copyright © 1985, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-37
ADC0831A, ADC0832A, ADC0831B, ADC0832B
AID PERIPHERALS ,WITH SERIAL CONTROL
functional block diagram
C~----.-------~----------------------r-~~~~~
cs
>----------i>CLK
r ---Di-i~-t--+-------I
: IADC0832I
L_C:N~Y~_J
CH1/IN-
EN
Cs
EN
REF
2-38
LADDER
AND
DECODER
EN
BITS 0.-7
CS
R
BITS 0-7
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TeXAS 75265
EOC
DO
ADC0831A, ADC0832A,ADC0831B, ADC0832B
AID PERIPHERALS WITH SERIAL CONTROL
sequence of operation
•
ADC0831
3
4
6
8
10
9
ClK
...
It)
l'
es
• I I,
I•
t su . . . . .
~
tconv-----~~
::,
MUX
I
SETTLlNG-.j
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o
I
IfM-----MSB-F.RST D A T A - - - - - - N N '
101-1
I
'';:;
o~:~::~~__-LI~M~SB-LI~-L~-L~-L~-L~-L~-L__~:O:~lS~B____~1~__~H~'-Z~_
5
4
3
'iii
'S
C"
0
u
n
.Q
E.
III
;:;
NOTE 1: All voltaQe values, except differential voltages, are with respect to the network ground terminal.
o·
:::J
recommended operating conditions
(")
::;.
n
c
a
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
fclock
Clock frequency
MIN
NOM
MAX
4.6
5
6.3
V
V
2
10
40
Clock duty cycle (see Note 21
UNIT
0.8
V
400
kHz
60
%
twH(CSI
Pulse duration, CS high
220
ns
tsu
th
Setup time, CS low or AOC0832 data valid before clockt
Hold time, AOC0832 data valid after clockt
350
90
ns
TA
Operating free-air temperature
I AI and BI suffixes
I AC and BC suffixes
ns
-40
85
0
70
°C
NOTE 2: The clock duty cycle range ensures proper operation at all clock frequencies. If a clock frequency is used outside the recommended
duty cycle range, the minimum pulse duration (high or low I is 1 ~s.
electrical characteristics over recommended range of operating free-air temperature.
Vee - 5 V. fclock - 250 kHz (unless otherwise noted)
digital section
PARAMETER
VOH
TEST CONDITIONSt
VCC
VCC - 4.75 V,
Low-level output
VOL
IIH
IlL
10H
~
High-level output
voltage
voltage
High-level input
current
Low-level input
current
High-level output
(source) current
Low-level
outp~t
10L
(sinkl current
10Z
state output
High-impedancecurrent (DO)
~
VCC
4.75 V,
4.75 V,
AI, BI SUFFIX
MIN
10H ~ -360 ~A
10H 10L
~
-10~
1.6 mA
TYP*
AC, BC SUFFIX
MAX
2.4
2.8
4.5
4.6
0.4
0.34
VIH ~ 5 V
VIL ~ 0
TYP*
MAX
UNIT
V
V
0.005
1
0.005
1
~A
-0.005
-1
-0.005
-1
~
VOH ~ 0,
TA
~
25°C
-6.5
-14
-6.5
-14
mA
VOL ~ VCC,
TA
~
25°C
8
16
8
16
mA
Vo
~
5 V,
TA
~
25°C
0.01
3
0.01
3
Vo
~
0,
TA
~
25°C
-0.Q1
-3
-0.01
-3
~A
Ci
Input capacitance
5
5
pF
Co
Output capacitance
5
5
pF
t All parameters are measu~ed under open-loop conditions with zero common-mode input voltage.
*All typical values are at VCC ~ 5 V. TA ~ 25°C.
2-40
MIN
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 865012 • DALLAS, TEXAS 75265
ADC0831A, ADC0832A, ADC0831B, ADC0832B
A/D PERIPHERALS WITH SERIAL CONTROL
electrical characteristics over recommended range of operating free-air temperature. Vee = 5 V.
fclock = 250 kHz (unless otherwise noted)
analog and converter section
PARAMETER
TEST CONDITIONS t
Common-mode input voltage range
VICR
MIN
-0.05
See Note 3
TYP'
MAX
UNIT
Ilistdbyl
current
isee Note 41
"iREFI
On-channel
CJ
VI - 5 V at on-channel,
VI ~ a at oil-channel
Oil-channel
On--channel
1
-1
-1
VI - 0 at on-channel,
VI - 5 V at oil-channel
Off-channel
~A
1
Input resistance to reference ladder
1.3
'3
...
VCC tO .05
Standby input
...
II)
V
to
2.4
5.9
k!l
C3
c
o
'';::;
'iii
'3
C'
total device
CJ
TEST CONDITIONSt
ICC
MIN
MAX
2.5
Supply current
3
5.2
UNIT
ct
...
('CI
mA
('CI
Q
t All parameters are measured under open-loop conditions with zero common-mode input voltage.
t All typical values are at VCC = 5 V, TA ~ 25°C.
NOTES:
3. II channel IN - is more positive than channel IN +, the digital output code will be 0000 0000. Connected to each analog input
are two on-chip diodes that will conduct forward current for analog input voltages one diode drop above Vee- Care must
be taken during testing at low VCC levels i4.5 VI because high-level analog input voltage i5 VI can, especially at high
temperatures, cause this input diode to conduct and cause errors for analog inputs that are near full-scale. As long as the
analog voltage does not exceed the supply vpltage by more than 50 mV, the output code will be correct. To achieve an absolute
o V to 5 V input voltage range requires a minimum Vce of 4.95 volts for all variations of temperature and load.
4. Standby input currents are currents going into or out of the on or off channels when the AID converter is not performing
conversion and the clock is in a high or low steady-state condition.
operating characteristics Vee = REF = 5 V. fclock = 250 kHz. tr
(unless otherwise noted)
VCC
Total unadjusted error
Vrel ~ 5 V,
TA ~ MIN to MAX
isee Note 51
Common-mode error
tpd
output data alter ClK!
isee Note 61
DO after
MIN
4.75 V to 5.25 V
Differential mode
data
LSB-lirst
Cl
~
Cl
~
10 pF,
Rl
~
10 k!l
Cl Rl
~
MAX
±1/16
±1/4
MIN
UNIT
TYP
MAX
±1/16
±1/4
lSB
±1
lSB
lSB
±1/16
±1/4
± 1/16
± 1/4
650
1500
650
1500
250
600
250
600
125
250
125
250
ns
100 pF
data
CSt
AI. AC SUFFIX
TYP
± 1/2
MSB-lirst
Output disable time,
tdis
~
Supply-voltage variation error
Propagation delay time,
BI. BC SUFFIX
TEST CONDITIONst
PARAMETER
tf
ns
100 pF,
2 k!l
Conversion time (multiplexer
tconv addressing time not included)
500
500
8
8
clock
periods
t All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX,
use the appropriate value specified under recommended operating conditions.
NOTES: 5. Total unadjusted error includes offset, fuJI-scale, linearity, and multiplexer errors.
6. The most significant-bit-first data is output directly from the comparator and therefore requires additional delay to allow for
comparator response time. Least-significant-bit-first data applies only to ADC0832.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-41
ADC0831A, ADC0832A, ADC08318, ADC08328
AID PERIPHERALS WITH SERIAL CONTROL
PARAMETER MEASUREMENT INFORMATION
eLK
-+I
c
....
II)
»
0.4V
n
I
.c
c
I
I
I
~
It------f--
eLK
I+-tsu
I
I
DATA IN
I
tpd
==E
GND
_--Vee
--'"\ I
I
\
----GNO
OATAOUT
(DO)
____ oJ
I~
2 V
vee
50%
:
.
I I
I~th
iii'
0'
~D
:
-tI
cs-=x-:---~-t-:------vee
II)
:+'
I
I4- t su
r ---vo H
50%
VOL
FIGURE 2. DATA OUTPUT TIMING
(011
:::J
o
::;'
FIGURE 1. ADC0832 DATA INPUT TIMING
n
c
i
Vee
:+'
III
FROM
OUTPUT
UNDER
TEST
TEST
POINT
1 !
J ~;-ee
S1
_
l
~--~
IW
Note A)
S2
'i
LOAD CIRCUIT
-1
CS
-tj
~tr
50%~
1=:90::::%~--
_ _...... !2'!L - - - -
Vee
CS
GND
SARS OUTPUT .J!..c~".!!...
90%~
__ _ _
90%
VOH
GND
DO AND
SARS OUTPUT
VOLTAGE WAVEFORMS
S1 closed
I
~
S2 open
10%
FIGURE 3. OUTPUT DISABLE TIME TEST CIRCUIT AND VOLTAGE WAVEFORMS
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
-vee
- - - - GND
VOLTAGE WAVEFORMS
NOTE A: CLincludes probe and jig capacitance.
2-42
Vee
10%
~tdiS
It--tt-tdis
Sl open
50%1
~
- - - - - GND
I
DO AND
~tr
I
ADC0831A, ADC0832A, ADC0831B, ADC0832B
AID PERIPHERALS WITH SERIAL CONTROL
TYPICAL CHARACTERISTICS
UNADJUSTED OFFSET ERROR
vs
REFERENCE VOLTAGE
16
V
I
I I I
1(+) -
I~r
V
<>
I
1(-) =
•
LINEARITY ERROR
vs
REFERENCE VOLTAGE
1.5
...
I
'-
I/)
Vee = 5 V
fclock = 250 kHz
1.25 I-TA= 25°e
14
"3
...
(,)
(3
12
III
~
III
III
....I
I
2
....
.l:i
:::
0
10
C
1.0
o
I
".;::
e
8
w0.75
6
'E.
.S
1\
4
l"t--
o
0.01
tT
(,)
0.5
«
0.25
C
...coco
....I
'\.
2
"iii
"3
0.1
o '----o
10
2
4
3
Vref-Reference Voltage-V
Vref- Reference Voltage- V
FIGURE 4
FIGURE 5
LINEARITY ERROR
vs
FREE-AIR TEMPERATURE
0.5
LINEARITY ERROR
vs
CLOCK FREQUENCY
1
3
1
Vref = 5 V
fclock - 250 kHz
0.45
III
III
....I
I
0.4
~
.l:i
>1; 0.35
c::
.
.1::
'""'"'"
/
/
2
I
0
l::
w 1.5
~
~
0.3
-25
/
III
....I
:::;
0.25
-50
Vref = 5 V
VCC - 5 V
2.5
III
~
0
25
.
'i
J
c::
'" "
50
5
:::;
0.5 f--= -40 oe
1'-
75
""
-
100
~
85°V 25°C
o
o
TA-Free-Air Temperature- °C
FIGURE 6
100
200
300
400
500
600
f clock - Clock Frequency - kHz
FIGURE 7
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-43
ADC0831A. ADC0832A. ADC0831B. ADC0832B
AID PERIPHERALS WITH SERIAL CONTROL
TYPICAL CHARACTERISTICS
•
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
1.5
C
...
vs
CLOCK FREQUENCY
fclock - 250 kHz
CS
III
III
SUPPLY CURRENT
1.5
r-----,---.---.....--...,----,
1.0
r-i---t==::t:===:f:==i
high
or:(
l>
(')
J:I
C
..
0'
=
C.
Q.
Q.
Q.
n
:;'
I/)
c
;:;
~
:::I
::I
'1
I
(')
.----
~
u
0.5 1----1-----1---+---+-----1
1l
(II
0.5 '--_-'--_-'-_--'-_ _L - _ - ' - _ - - '
-50 -25
0
25
50
75
100
TA - free-Air Temperature - DC
OL-_~
o
_ _- L_ _
fiGURE 8
fiGURE 9
OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
25r--~--r-~--~-~-~
or:(
20
E
.:..c
~ 15~-~~~~-4-=~~~4--~
:::I
u
:;
~ 10 ~-+---+---4--+--4--~
o
I
5}
5
F::T.=:-t-7~:::::i:::=t--l
IOL (VOL = 0.4 VI
OL-_L-_~_-L_~_~_~
-50 -25
0
25
50
75
TA-free-Air Temperature- DC
fiGURE 10
2-44
~
_ _~_~
100
200
400
300
fclock-Clock frequency-kHz
T~.
INSTRUMENTS
POST OFFICE. BOX 656012· DALLAS, TeXAS 75265
100
500
ADC0834A, ADC0838A, ADC0834B, ADC0838B
AID PERIPHERALS WITH SERIAL CONTROL
02795. AUGUST 1985- REVISED OCTOBER 1986
ADC0834 ••• N DUAL-IN-liNE PACKAGE
•
8-Bit Resolution
•
Easy Interfece to Microprocessors or
Stand-Alone Operation
•
Operates Ratiometrically or with 5-V
Reference
•
4- or 8-Channel Multiplexer Options with
Address Logic
•
•
•
(TOPVIEWI
VCC
01
CHl
CH2
CH3
OGTL GNO
Shunt Regulator Allows Operetion with
High-Voltage Supplies
Remote Operation with Serial Data Link
•
Inputs and Outputs are Compatible with
TTL and MOS
•
Conversion Time of 32 ,.s at
fclock = 250 kHz
•
Designed to be Interchangeable with
National Semiconductor ADC0834 and
ADC0838
...
!II
'5
...u
c::;
C
ADC0838 ... N DUAL-IN-liNE PACKAGE
(TOP VIEW)
Input Range 0 to 5 V with Single 5-V
Supply
•
~
CLK
SARS
DO
REF
_ _8
...r- ANLG GNO
CHO
CHl
CH2
CH3
CH4
CH5
CH6
CH7
COM
OGTL GNO
o
'~
'U;
VCC
'5
V+
C'
~
CS
01
...asas
CLK
SARS
DO
Sf
REF
ANLG GND
C
ADC0838 ... FN CHIP CARRIER PACKAGE
DEVICE
ADC0834
ADC083B
(TOP VIEW)
TOTAL UNAOJUSTED ERROR
A SUFFIX
B SUFFIX
± 1 LSB
± 1/2 LSB
±1 LSB
± 1/2 LSB
N
_
0
J:J:J:
I
U
u+
UUU»
3
2
1 2019
18
description
17
These devices are 8-bit successiveapproximation analog-to-digital converters each
with an input-configurable multichannel
multiplexer and serial input/output. The serial
input/output is configured to interface with
standard shift registers or microprocessors.
Detailed information on interfacing to most
popular microprocessors is readily available from
the factory.
16
7
15
8
14
9 10111213
The ADC0834 (4-channel) and ADC0838
(8-channel) multiplexer is software configured
for single-ended or differential inputs as well as
pseudo-differential input assignments. The
differential analog voltage input allows for
common-mode rejection or offset of the analog
zero input voltage value. In addition, the voltage
reference input can .be adjusted to allow
encoding any smaller analog voltage span to the
full 8 bits of resolution.
The ADC0834AI, ADC0834BI, ADC0838AI, and ADC0838BI are characterized for operation from - 40 DC
to 85 DC. The ADC0834AC, ADC0834BC, ADC0838AC, and ADC0838BC are characterized for operation
from ODC to 70 DC.
PRODUCTION DATA dacullllllllB contain inia....ti••
carrent •• of publi••ti•• d.ta. Pr.dlcts ••nf.rm
to .,atjcati.1II per tho WIll. of T.... lnstra_
staridIIrd warranty. Producti.n pl'1lC8lling d... not
n......rily in.la~. t..ting .1 .11 poro..lllrs.
Copyright © 1985. Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75285
2-45
'~n3Jl:l "<>!IISlnb·v • ..a
N
./:..
0>
II ..
I:
:::I
()
:::I
"'CII=
mCQ
::aW
0
"'CII>
:
.
!;g:.:-
0'
ClK
CS,
r
~
,
-5!:
STAAT
FLIP-FLOP
1\1
~ClK
cs
SARS
D,
(SuNotaA)
()
'/If:'
Co
.
iii'
5·IUT SHIFT REGISTER
CC
SELECT 0 SELECT 1 ODD/EVEN SGL/W
1\1
3
r ::-DC:;';- -,
-{
J
ONLY
~
~
o
~Z
~~~
~;~c~1T1
J
CHO---------i
,
CH'------;
CH2------;
"~
-
::ef:
_CQ
~}>
me;,
::an
-=
:':-CQ
!>ClK
.... w
ADC0838<=@
CH3------;
2:.:-
ANALOGMUX
-Ie;,
::an
Q=
.... CQ
cs
CHe
CH7
W
COM
CQ
IZI
cs
~Z~
:ll
:.:-e;,
.... n
cn=
n.j::loo
e;,!I'
~1T1
~~~
~
-.j::Ioo
tn:':-
~~
SE I
L ___
:.:-:.:-
-e;,
e;,n
cs
Cii
COMPARATOR
REF - - - - - - - - - - - - 1
EN
LADDER
AND
DECODER
VCCJPfTO'NTERNAL
CIRCUITS
7V
.".
"='
V+
7V
.
.".
NOTE A: For the AOC08;,4, 01 is input directly to the 0 input of SElECT 1, SELECT 0 is forced to • high.
cs
ClK
....'T
ClK
EDC
DO
ADC0834A, ADC0838A, ADC0834B, ADC0838B·
AID PERIPHERALS WITH SERIAL CONTROL
functional description
The AOC0834 and AOC0838 use a sample data comparator structure that converts differential analog
inputs by a successive-approximation routine. Operation of both devices is similar with the exception of
a select enable (SE) input, analog common input, and multiplexer addressing. The input voltage to be
converted is applied to a channel terminal and is compared t.o ground (single-ended), to an adjacent input
(differential), or to a common terminal (pseudo-differential) that can be an arbitrary vol1age. The input
terminals are assigned a positive ( + ) or negative ( -) polarity. If the signal inputs applied to the assigned
positive terminal is less than the signal on the negative terminal, the converter output is all zeros.
•
Channel selection and input configuration are under software control using a serial data link from the
controlling processor. A serial communication format allows more functions to be included in a converter
package with no increase in size. In addition, it eliminates the transmission of low-level analog signals
by locating the converter at the analog sensor and communicating serially with the controlling processor.
This process returns noise-free digital data to the processor.
'.;:l
A particular input configuration is assigned during the multiplexer addressing sequence. The multiplexer
address is shifted into the converter through the data input (01) line. The multiplexer address selects the
analog inputs to be enabled and determines whether the input is single-ended or differential. When the
input is differential, the polarity of the channel input is assigned. Oifferential inputs are assigned to adjacent
channel pairs. For example, channel 0 and channel 1 may be selected as a differential pair. These channels
cannot act differentially with any other channel. In addition to selecting the differential mode, the polarity
may also be selected. Either channel of the channel pair may be designated as the negative or positive input.
...
'S
II)
.
CJ
(3
C
o
'iii
'S
C"
CJ
---J.-,,--J'----:,-...L---II
7
ADC0834A, ADC0838A, ADC0834B, ADC0838B
AID PERIPHERALS WITH SERIAL CONTROL
sequence of operation
ADC0838
1
CLK
3
4
5
6
7
8
nnn
---1f--JUUUHUU4
I
--JIoI
l'
I
I
,
I
I
I
I
I
I
I
I
I
MUX
~ tsu
14
15
16
17
18
19
20
21
22
23
24
25
26
27
I
START'
SEL SELl I
SIGN BIT 1 BIT 0 I
II)
I
I
DIF EVEN 1
"iii
"S
C"
I_~rf~_
I
0'
I
I
I
I
l
co
;
,
C
I
I
I
I
U
c(
I
,
I
HI-Z
'I
SARSlL.._ _ _ _ _ _ _--'
C
o
I I
I
~
(3
~
:
BITIr-~S~G~LrO~D~DT_~I_r~O~I~'~~~7r_~7r_7r_7r_7r_~'7r_7r_7r_7r_7r_7r_7r_7r_7r_7r_7r_7fi7r_7r_7r_7fi7r_7r_7r_7.n7.n7.n7.n77.
DI~
II
..
"S
1~1------~--------------------------~r-
I
I
I I
I
I
13
I
: ~RESS~:
----,
12
14+----.tconv----~
I
I I
11
n
kf-l-tsu
II
CS
2
fl fl fl fl
I
II
I
HI-Z
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
.......)1
-----~~------------------------------------I I
SE HElD LDW OR CONNECTED TO a;
I
I
,
I
:-RJ:
SE '-_________~:_+:-------.~---------------------------------------------------------'rI I
II
MUX SETTLING..J
-1i
OO.!H.!!I;:o-Z'--____.:.T.:.:IM;;;E=-__
I
I4--MSB-FIRSTDATA -~~i4----LSB-FIRSTDATA-
I
,
I
'176
- - - - - - - - -1 t - - - - - - - - ~
I
:
L~BI
I
0
2
4
I
6
USEDTOCONTROL LsBFIRSTOATA -
-
-
-
-
-
-
-
-
-
-
-
-
--
'---________________________~r_
1$
,I
SE
HI-Z
IMSBI
I ,
MUX
,
'
!4--MSB-FIRST DATA _ _ LSB-HElD---l~_----LSB-FIRST D A T A _
SETTLlNG~
I
*',
I
'
TIME
,
I
I
--41::~I'---:--'-~--:-LSB----'--c:-'-----::-"--:-'--:--,---:O--,--:-L-:1
D O - - - - - - - L - ' - -MS-L..
IBI
I
--,I
MS:-,--BI
6
3
4
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 6!i5012 • DALLAS. TExAS 15265
2-49
ADC0834A, ADC0838A, ADC0834B, ADC0838B
AID PERIPHERALS WITH SERIAL CONTROL
ADCOS3S MUX ADDRESS CONTROL LOGIC TASLE
•
MUX ADDRESS
SGL/DIF
ODD/EVEN
SELECTED CHANNEL NUMBER
0
L
1
l
l
H
H
l
0
l
l
C
l.
r+
I»
I»
l
l
l
l
l
H
H
l>
l
H
l
l
..c
c
l
H
l
H
l
H
H
l
l
H
H
H
H
l
l
H
l
l
l
H
H
l
H
l
H
l
H
H
c
H
H
l
l
H
H
l
H
UI
H
H
H
H
l
H
H
H
n
(ii'
::+
S'
~
n
~'
::+'
H
=
high level, l
=
0
SELECT
+
-
2
1
1
-
2
3
+
-
3
4
5
+
-
COM
6
7
+
-
-
+
+
-
+
+
-
-
+
+
-
+
-
+
-
+
-
+
+
low level, - or +
+
= polarity
-
of selected input
absolute maximum ratings over recommended operating free-air temperature range (unless otherwise
noted)
Supply voltage, Vce (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6.5 V
Input voltage range: Logic.......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 15 V
Analog .... " .............................. -0.3 V to Vee+0.3 V
Input current: V + input ................................................... 1 5 mA
Any other input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 5 mA
Total input current for package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Operating free-air temperature range: AI and BI suffixes .................... - 40 °e to 85°e
AC and Be suffixes. . . . . . . . . . . . . . . . . . . . .. ooC to 70 0 e
Storage temperature range ......................................... - 65°C to 150 0 e
Case temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260 0 e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ............. 260°C
NOTES: 1. All voltage values, except differential voltages, are with respect to the network ground terminal.
2. Internal zener diodes are connected from the Vee input to ground and from the V + input to ground. The breakdown voltage
of each zener diode is approximately 7 volts. One zener diode can be used as a shunt regulator and connects to Vee through
a regular diode. When the voltage regulator powers the converter, this zener and regular diode combination ensures that the
Vee input (6.4 Vl is less than the zener breakdown voltage. A series resistor is recommended to limit current into the V + input.
2-50
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
ADC0834A. ADC0838A. ADC08348. ADC08388
AID PERIPHERALS WITH SERIAL CONTROL
recommended operating conditions
VCC
Supply voltage
VIH
High~level
input voltage
MIN
NOM
MAX
4.5
5
6.3
2
UNIT
V
V
Vil
low-level input voltage
0.8
V
fclock
Clock frequency
10
400
kHz
Clock duty cycle Isee Note 31
40
60
IwHICSI
Pulse duration, CS high
220
%
ns
Isu
Setup time, CS low, SE low, or data valid before clock!
350
ns
Ih
Hold time, data valid after clocki
TA
Operating free-air temperature
-40
85
0
70
°c
NOTE 3: The clock duty cycle range ensures proper operation at all clock frequencies. If a clock frequency is used outside the recommended
duty cycle range, the minimum pulse duration (high or low) is 1 IA.S.
~!..~~UFFIX
MIN TYP* MAX
TEST CONDITIONSt
PARAMETER
=
Vcc
4.75 V,
Vec = 4.75 V,
=
lOH = -360 ~A
IOH - -10 ~A
~
c
o
'';:::
'iii
'5
CT
u
...
=
2.8
4.5
4.6
VCC
High-level input current
VIH = 5 V
III
Low-level input current
Vil
10H
High-level output (source) current
VOH
TA
= 25°C
-6.5
10l
Low-level output (sink) current
VOL - VCC.
Vo = 5 V,
TA ~ 25°C
8
High-impedance-state output
current IDO or SARS)
Vo
=0
= 0,
= 0,
10l
TA
TA
1.6 rnA
= 25°C
= 25°C
0.005
1
-0.005
-1
-14
-6.5
16
MAX
8
UNIT
V
0.34
0.4
Low-level output voltage
IIH
5.25 V,
AC, BCSUF~~
MIN TYP*
2.4
VOL
IOZ
u
Q
digital section
High-level output voltage
III
C3
1
MSB-first data
CL
.
~
1
CSt
CL
~
CL
~
650 1500
650 1500
250
600
250
600
125
250
500
125
250
500
100 pF
LSB
I:
o
'iii
'S
ns
LSB-flrst data
10 pF, RL ~ 10 kO
100 pF, RL ~ 2 kO
Conversion time (multiplexer
teonv
MIN
± 1/16 ±1/4
MIN to MAX
I
output data after CLK!l
AI. AC SUFFIX
MAX
15 rnA at V + pin.
~
25 °e (unless
'';::
Output disable time,
tdis
4.75 V to 5.25 V
5 V,
TYP
Vref ~ 5 V, VCC open
diode operation (see Note 2)
(see Note 71
BI. BC SUFFIX
MIN
Differential mode
Change in zero-error from
tpd
~
TA
Common-mode error
Propagation delay time,
~
VCC
20 ns, TA
tf
8
addressing time not included)
8
C'
to>
c:(
ns
...caca
clock
periods
C
t All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX,
use the appropriate value specified under recommended operating conditions.
NOTES: 2. Internal zener diodes are connected from the Vee input to ground and from the V + input to ground. The breakdown voltage
of each zener diode is approximately 7 volts. One zener diode can be used as a shunt regulator and connects to Vee through
a regular diode. When the voltage regulator powers the converter. this zener and regular diode combination ensures that the
Vee input (6.4 V) is less than the zener breakdown voltage. A series resistor is recommended to limit current into the V + input.
6. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
7. The most significant bit (MSB) data is output directly from the comparator and therefore requires additional delay to allow for
comparator response time.
PARAMETER MEASUREMENT INFORMATION
CLK
~
I
~
14- tsu
I
I
GND
14- tsu
-,\":-:-----f-:-----I
cs 0.4V\ I
I
I
I
I4-M--th
I
vce
I
GND
I
_---Vce
DATA IN
(DII
FIGURE 1. DATA INPUT TIMING
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-53
ADC0834A, ADC0838A, ADC0834B, ADC0838B
AID PERIPHERALS WITH SERIAL CONTROL
PARAMETER MEASUREMENT INFORMATION
•
I
GND
~tpd
tpd----.j
~- - - - -
DATA
OUT (DO)
-
----
"}f\511'1o
___ o
J.
If-
-I"".z::vcc
II .,-..511'10
'--GND
~ t..,
14--
SE-----------~V:---:::
FIGURE 2. DATA OUTPUT TIMING
TEST
POINT
FROM
OUTPUT
UNDER
TEST
1
r
CL
~ ~
(See Note A)
LOAD CIRCUIT
"1
-tf
~tr
---1-----10%
---s:=
_
GND
VOH
~1dis
GND
,
DO.AND
SARS OUTPUT
S1 closed
S2 open
I
_1~_ _
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTE A: CL includes probe and jig capacitance.
FIGURE 3. OUTPUT DISABLE TIME TEST CIRCUIT AND VOLTAGE WAVEFORMS
.2-54
VCC
11l.!. _ _ _ _ GND
~1dis
DO AND S1 open
90%
SARSOUTPUT _S!.c~ _ _ _
~tr
_~I
90%
CS
50%1
5O%~1I:"::9:::0%::--- Vee
·TEXAS . "
INSTRUMENTS
post OFFice BOX 656012 • DALLAS. TEXAS 75265
-Vcc
GND
ADC0834A, ADC0838A, ADC08348, ADC08388
AID PERIPHERALS WITH SERIAL CONTROL
TYPICAL CHARACTERISTICS
UNADJUSTED OFFSET ERROR
vs
REFERENCE VOLTAGE
16
LINEARITY ERROR
vs
REFERENCE VOLTAGE
1.5
r-- VII+) = VII:':") = 0 V
14
12
i
c
o
'';:
e
'iii
w0.75
8
's0'
~
6
'e=
:::;
I\,
4
"- I'\.
2
(,)
..
ca
ca
Q
0.25
0.1
1.0
Vref-Reference Voltage-V
0.01
«
0.5
r-
o
o
10
o
2
3
4
Vref-Reference Voltage-V
FIGURE 4
LINEARITY ERROR
vs
CLOCK FREOUENCY
vs
FREE·AIR TEMPERATURE
0.5
3
L
_I.
V re f- 5V
fclock = 250 kHz
0.45
IX!
en
..I
0.4
51
..I
'ij
., 0.35
e
:::;
0.3
-25
~5V
VrefVCC=5V
/
/
2
/
I
"~
~
0.25
-50
2.5
"- I"\.
w
o
15
Ji
""
25
5
FIGURE 5
LINEARITY ERROR
I
~
U
.!.
0
e
's
IX!
I
;:
!!
I
!j' 1.0
IX!
en
..I 10
e
w
r.
VCC=5V
fclock = 250 kHz
1.25 -TA=25°C
1.5
'E
I
!lle
:::;
r-...... .......
50
85°
0.5 i-==- -40·C
.......
75
100
o
o
100
200
300
V :?
400
500
600
fclock - Clock Frequency - kHz
TA-Free·Air Temperature-·C
FIGURE 6
FIGURE 7
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXA.S 76265
2-55
ADC0834A, ADC0838A, ADC083411, ADC0838B
AIQ PERIPHEPA~S WITH SERIAL CONTROL
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
SUPPLY CURRENT
YS
YS
FREE-AIR TEMPERATURE
1.5
~ock
"'-
I»
l>
n
.Q
C
ii'
g:
~
n
:::;;'
n
C
;;"
J
I
'i'
...
1I
.
CLOCK FREQUENCY
1.5
= 250 kH!CS=HIGH
«
I;:
~e .. S
E
.S"
~
c
~
........... ~ "eels"
"
';. 1.0
is.
~
CI.
"I
I
.......... v.ee"'4S
-..:..~
fI)
tJ
S;
VCC=5V
TA = 25°C
I
1: 1.0
-...... r--..
--
~
"
~
tJ
:?:
CI.
CI.
r-
"I
~
fI)
0.5
tJ
~
fII,
r-0.5
~50
-25
o
50
75
0
100
0
300
400
100
200
fclock - Clock Frequency - kHz
TA - Free·Air Temperature _·C
FIGURE 8
FIGURE 9
OUTPUT CURRENT
VS
FREE-AIR TEMPERATURE
25
VCC=5V
101 (\I.
f- -/0
ft (II.
~") r-..
-"::1-- Oft '" 0 II)
~
r--- ::---I-
f-..:::.'OH (VO H = 2.4 VI
-'!'pl (VOL! 0.4 VI
-
ro
-50
-25
75
o
25
50
T A - Free-Air Temperature - ·C
FIGURE 10
2-56
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
100
500
nOBOB. nOB09
LOW-POWER CMOS ANALOG-TO-DIGITAL CONVERTERS
WITH B-CHANNEL MULTIPLEXERS
- REVISED
•
Total Unadjusted Error ... ± 0.75 LSB Max
for TL0808 and ± 1.25 LSB Max for
TL0809 Over Temperature Ranga
•
Ideal for Battery Operated, Portable
Instrumentation Applications
•
Resolution of 8 Bits
•
100
•
Ratlometric Conversion
•
Guaranteed Monotoniclty
,",S
".'OT.'UlA"A 1986
N DUAL-IN-LiNE PACKAGE
(TOP VIEW)
~}INPUTS
~}ADDRESS
Conversion Time
(I)
.t:
:s
()
...
ALE
c:;
2-1 (MSBI
2-2
•
No Missing Codes
•
Easy Interface with Microprocessors
•
Latched 3-State Outputs
•
Latched Address Inputs
•
Single 5-Volt Supply
•
Extremely Low Power
Consumption ... 0.3 mW Typ
•
Improved Direct Replacements for
ADC0808, ADC0809
C
o
2- 3
2- 4
elK
Vee
REF +
GND
E(I)
2 -8 (lSBI
REF-
·S
C"
2-7 ......_ _ j - ' 2- 6
()
n
.Q
c
iii'
;::;.'
NOTE 1: All voltage values are with respect to network ground terminal.
recommended operating conditions
0'
:::J
I
f clock - 10kHz to 640 kHz
fclock - 640 kHz to 1280 kHz
Clock frequency, fclock (see supply voltage recommendation above)
n
::;'
Supply voltage, VCC
n
c
I
Positive reference voltage, V ref + (see Notes 2. 3, and 4)
Negative reference voltage, Vref- (see Notes 2, 3, and 4)
Differential reference voltage, Vref+ - Vref- (see Note 4)
High-level input lIoltage, control inputs, VIH
i:
MIN
2.75
4
10
2.75
UNIT
1280
kHz
VCC+ O.1
-0.1
V
V
V
V
0.3 Vee
200
Start pulse duration, tw(S)
Address load control pulse duration, tw(ALC)
Address setup time, tsu
200
50
Address hold time, th
Operating free-air temperature, T A (see Note 4)
2·60
VCC
0
3
MAX
5.5
5.5
0.7 Vce
Low-level input voltage, control inputs, VIL
NOTES:
NOM
50
40
85
V
V
ns
ns
ns
ns
·C
2. The accuracy of the conversion will depend on the stability of the reference voltages applied.
3. Analog voltages greater than or equal to Vref+ convert to all highs, and all voltages less than Vref- convert to all lows.
4. For proper operation of the TL0808 and TL0809 at free-air temperatures below O·C, VCC and (Vref+ - Vref-) should not
be less than 3 volts.
TEXAS •
INSTRUMENTS
FiOST OFi=ICE: 'BOX 66£)012 • t)ALLAS, TItXA$ 75266,
TLoaoa, TLOa09
LOW·POWER CMOS ANALOG·TO·DIGITAL CONVERTERS
WITH a·CHANNEL MULTIPLEXERS
electrical characteristics over recommended operating free-air temperature range, Vee - 3 V to 5.25 V
(unless otherwise noted)
total device
PARAMETER
TEST CONDITIONS
VOH High·level output voltage
VOL
Low-level output voltage
10
I Data outputs
I End of conversion
-360 p.A
MAX
0.4
1
-1
Control input current at maximum input voltage
IlL
Low-level control input current
VI - 0
ICC
Supply cUrlent
ei
Input capacitance, control inputs
TA - 25°C
Co
Output capacitance, data outputs
TA
1
-1
=
UNIT
p.A
C3
640 kHz
100
500
~A
0:3
3
mA
10
15
pF
10
15
pF
1000
o
+=
'iii
itA
fclock - 640 kHz
1
c
~A
fclock
Resistance from pin 12 to pin 16
..
V
VCC - 3 V,
25°C
(I)
'S(.)
Vee - 5 V,
=
...
V
10-1.2mA
II
output current
TYpt
0.4
Vo - VCC
Vo = 0
VI - 15 V
10Z
MIN
VCC-O.4
1.6 mA
10
Off-state (high-impedance-state)
=
=
'S
C'
(,)
c(
...ca
kll
t3
analog multiplexer
PARAMETER
Ion
loff
TEST CONDITIONS
Channel on-state cUrlent (see Note 5)
Channel off-state current
VI
=
3 V,
VI - 0,
fclock
=
MIN
Typt
f clock - 640 kHz
= 3 V,
= 25°e
=
MAX
2
-2
640 kHz
VCC
VI
3 V
10
200
TA
VI - 0
VI - 3 V
10
200
1
Vec
=
3 V
VI - 0
-1
UNIT
~A
nA
~A
tTypical values are at Vee = 3 V and TA = 25°e.
NOTE" 5: Channel on~state current is primarily due to the bias current into or out of the threshold detector, and it varies directly with clock
frequency.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2-61
TLOBOB, nOB09
LOW·POWER CMOS ANALOG·TO·DIGITAL CONVERTERS
WITH B·CHANNEL MULTIPLEXERS
operating characteristics. TA _25°e. Vee - 3 V. VREF+ - 3 V. VREF- - 0 V. fclock .. 640 kHz
(unless otherwise noted)
PARAMETER
c
kSVS
!I»
sensitivity
nOBOB
MIN
VCC = Vref+ = 3 V to 5.25 V.
TA= -40°C to 85°C. See Note 6
(see Note 7)
Zero error (see Note 8)
.sc
iii'
;;,
o
::::s
o
Total unadjusted
error (See Note 9)
TA = 25°C
Output enable time
CL - 50 pF.
CL - .10 pF.
See Note 10
ten
tdis
Output disable time
teonv
Conversion time
TYpt
nOB09
MAX
MIN
±0.05
Linearity error
l>
RL - 10 kll
90
MAX
UNIT
±0.05
%/V
±0.5
±1
LS8
±0.5
±0.5
±0.25
±0.5
±0.5
80
105
100
±O.75
250
250
116
90
80
105
110
14.5
0
TA - -40°C to 85°C
RL - 10 kll
Typt
LSB
±1
± 1.25
250
250
LSB
ns
ns
116
~s
14.5
~
Delay time.
ifc
::r
II)
Supply voltage
TEST CONOITIONS
td(EOC) end of conversion
output
See Notes 10 and 11
0
tTypical values for all except supply voltage sensitivity are at Vcc = 3 V. and all are at T A = 25°C.
NOTES:
6. Supply voltage sensitivity relates to the ability of an analog-to-digital converter to maintain accuracy as the supply voltage
varies. The supply and V ref + are varied together and the change in accuracy is measured with respect to full-scale.
7. Linearity error is the maximum deviation from a straight line through the end points of the AID transfer characteristic.
8. Zero error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
9. Total unadjusted error is the maximum sum of linearity error, zero error, and full-scale error.
10. Refer to the operating sequence diagram.
11 . For clock frequencies other than 640 kHz. td(EOC) maxi!llum is 8 clock periods plus 2
2-62
TEXAS . "
INSTRUMENTS
POST o~FiCE dox 8550,. • OALLA~. TEXAs 16265
~s.
nOBOB, nOB09
LOW·POWER CMOS ANALOG·TO·DIGITAL CONVERTERS
WITH B·CHANNEL MULTIPLEXERS
PRINCIPLES OF OPERATION
The TL0808 and TL0809 each consists of an analog signal multiplexer, an 8·bit successive-approximation
converter, and related control and output circuitry.
multiplexer
...
II)
The analog multiplexer selects 1 of 8 single-ended input channels as determined by the address decoder.
Address load control loads the address code into the decoder on a low-to-high transition. The output latch
is reset by the positive-going edge of the start pulse. Sampling also starts with the positive-going edge
of the start pulse and lasts for 32 clock periods. The conversion process may be interrupted by a new
start pulse before the end of 64 clock periods. The previous data will be lost if a new start of conversion
occurs before the 64th clock pulse. Continuous conversion may be accomplished by connecting the Endof-Conversion output to the start input. If used in this mode an external pulse should be applied after power
up to assure start up.
..
C3
"S
Co)
c
o
",0::
"iii
"S
CO
Co)
converter
The CMOS threshold detector in the successive·approximation conversion system determines each bit
by examining the charge on a series of binary-weighted capacitors (Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing switch Sc and all ST switches, and by
simultaneously charging all the capacitors to the input voltage.
n
.c
c
iii"
;::;'"
0"
:::I
(")
:;"
n
c
;::;'"
III
2-64
TL182, TL185, TL188, TL191
BI·MOS SWITCHES
D2234. JUNE 1976-REVISED SEPTEMBER 1986
•
Functionally Interchangeable with Siliconix
DG182. DG185. DG188. DG191 with Same
Terminal Assignments
•
Monolithic Construction
•
Adjustable Reference Voltage
•
JFET Inputs
•
Uniform On-State Resistance for Minimum
Signal Distortion
•
± 10-V Analog
•
TTL. MOS. and CMOS Logic Control
Compatibility
The TL 182. TL 185. TL 188. and TL 191 are
monolithic high-speed analog switches using BIMOS technology. They comprise JFET-input
buffers. level translators. and output JFET
switches. The TL 182 switches are SPST; the
TL 185 switches are SPOT. The TL 188 is a pair
of complementary SPST switches as is each half
of the TL 191 .
CJ
o
Ne
Ne
Ne
Ne
'S
1A
2A
~
'+l
'iii
C'
VEE
Vref
....asas
Q
(TOP VIEW)
101
Ne
151
1A
102
152
281
201
VEE
Vref
VLL
Vee
Ne
2A
252
202
TL188
N DUAL·IN·LlNE PACKAGE
(TOP VIEW)
The output switches are junction field-effect
transistors featuring low on-state resistance and
high off-state resistance. The monolithic
structure ensures uniform matching.
Ne
Ne
Ne
Ne
01
51
A
02
52
Vee
VLL
BI-MOS technology is a major breakthrough in
linear integrated circuit processing. BI-MOS can
have ion-implanted JFETs. p-channel MOS-FETs.
plus the usual bipolar components all on the
same chip. BI-MOS allows circuit designs that
previously have been available only as expensive
hybrids to be monolithic.
Devices with an "M" suffix are characterized for
operation from - 55°C t0125 °C. those with an
"I" suffix are characterized for operation from
- 25°C to 85 °C. and those with a "C" suffix
are characterized for operation from 0 °C to
70°C.
C
25
20
TL185
N DUAL·IN·LlNE PACKAGE
The threshold of the input buffer is determined
by the voltage applied to the reference input
(V ref} . The input threshold is related to
the reference input by the equation
Vth = Vref + 1.4 V. Thus. for TTL compatibility. the Vref input is connected to ground. The
JFET input makes the device compatible with
bipolar. MOD. and CMOS logic families.
Threshold compatibility may. again. be
determined by Vth = Vref + 1.4 V.
Ne
VEE
Vref
TL191
N DUAL·IN·LlNe PACKAGE
(TOP VIEW)
Ne
181
1A
1D2
152
252
202
VEE
Vref
VLL
Vee
Ne
2A
251
101
201
Ne-No internal connection
Copyright @ 1984, Texas Instruments Incorporated
PRODUCTION DATA do.uments .ontain
information currant 8S of publication data.
ProductiDn proceSSing does not necass.rir,
.
(3
15
10
Vee
VLL
A high level at a control input of the TL 182 turns
the associated switch off. A high level at a
control input of the TL 185 turns the associated
switch on. For the TL 188. a high level at the
control input turns the associated switches S 1
on and S2 off.
:IDd~=:onl~::ut:=ifi:::~~:sar!~~:::~
....III
'S
TL182
N DUAL·IN·LlNE PACKAGE
(TOP VIEW)
description
includB testing of all paramaters.
Voltage Range
TEXAS . '
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-65
TL1B2. TL185
BI·MOS SWITCHES
TL 182 TWIN SPST SWITCH
symbol
schematic (each channel)
VLL
VCC
0
1A
1S
S
2A
2S
(5)
\1l
--1:..
(2)
---t...
(13)
10
(10)
(14)
20
FUNCTION TABLE
(EACH HALF)
VEE
INPUT
SWITCH
A
L
S
ON (CLOSED)
H
OFF (OPEN)
Vref
TL 185 TWIN DPST SWITCH
schematic (each channel)
VLL
symbol
VCC
lA
01
lSl
152
115)
(16)
(4)
-'-
-"'"-
(1)
(3)
101
102
(10)
Sl
2A
A-+~~--4-------+-------r-----~
02
2S1
252
(5)
(9)
-'"....,/-
(6)
(8)
201
202
52
FUNCTION TABLE
(EACH HALF)
VEE
2·66
Vref
TEXAS . "
INSTRUMENTS
POST OFFice BOX 665012 • DALLAS. TEXAS 75266
INPUT
SWITCHES
A
L
SWl ANDSW2
OFF (OPEN)
H
ON (CLOSED)
TL188, TL191
BI·MOS SWITCHES
TL 188 DUAL COMPLEMENTARY SPST SWITCH
schematic
symbol
VLL
.....
vcc
III
·3
Dl
A
(41
51
S2 (111
51
(,)
(51
.../-
---t.
(31
Dl
(121
(3
C
o
D2
.~
A--+r--*-~-------+-------r----~"I
D2
·iii
S2
-
I»
r+
I»
»
n
.c
c
in'
0'
;:;:
~
+-t,
OOR01
02
s OR S1
S2
See the preceding two pages for operation of the switches.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
n
~'
c
a
2-68
Positive supply to negative supply voltage, VCC - VEE ............................. 36 V
Positive supply voltage to either drain, VCC - Vo ................................. 33 V
Orain to negative supply voltage, Vo - VEE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 33 V
Orain to source voltage, Vo - Vs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 22 V
Logic supply to negative supply voltage, VLL - VEE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 36 V
Logic supply to logic input voltage, VLL - VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 33 V
Logic supply to reference voltage, VLL - Vref .................................... 33 V
Logic input to reference voltage, VI - Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 33 V
Reference to negative supply voltage, Vref - VEE ................................. 27 V
Reference to logic input voltage, Vref - VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2 V
Current (any terminal) ................................. ;................... 30 mA
Operating free-air temperature range: TL182M, TL 185M, TL 188M, TL 191 M .. .. - 55°C to 125°C
TL1821, TL1851, TL1881, TL1911 ......... -25°C to 85°C
TL182C, TL185C, TL188C, TL191C ......... ooC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1;6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260°C
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 666012 • DAllAS. TEXAS 76266
electrical characteristics. Vee
15V. VEE
-15V. VLL =5V. Vref
PARAMETER
VIH
TA
input voltage
High-Jevel control
IIH
input current
Low-level control
III
input current
Off-state drain current
IOloff)
2i
en
....
f;1
Z
"'f;i
~~
~;;C~
~~ 3:
c:~
Z.
/! ITl
~
~
>
en
VI
~
5 V
VI
~
0
VO-l0V,
VIH
~
~ ~.
~
'"
~
0>
'"
Off-state source current
VIH
On·5tate channel
~.
Vs -
2 V,
2 V,
VO~-10V,
'o(on) + 'S(on) leakage current
VIH
~
2 V,
-10 V,
Drain-ta-source
VD~-10V,
on-state resistance
VIH
~
MIN TO MAX
~
MIN to MAX
Vref+~
V re f+ 2
V re f+ O.8
10
20
TA - MAX
20
20
20
-250
-250
-250
5
5
100
100
5
5
0.8 V
TA
~
MAX
10 V,
TA
=
25°C
Vil
~
0.8 V
TA - MAX
Vs
~
-10 V,
TA = 25°C
Vil
~
0.8 V
1 mA,
100
100
TA - MAX
TA - MIN to 25°C
TA
Tl188
0.8 V Tl185,
~
MAX
TA = MIN to 25°C
Tl191
TA
~
MAX
100
100
-10
-10
200
-200
-200
75
100
100
100
150
150
125
150
150
250
300
300
1.5
ICC
Supply current from
Vee
1.5
1.5
lEE
Supply current from VEE
-5
-5
-5
ILL
Supply current from V LL
4.5
4.5
4.5
'ref
Reference current
-2
-2
-2
ICC
Supply current from
Vee
1.5
1.5
1.5
lEE
Supply current from VEE
-5
-5
-5
ILL
Supply current from VLL
4.5
4.5
4.5
Iref
Reference current
-2
-2
-2
Both control inputs at 5 V
switching characteristics. Vee - 10 V. VEE -
Turn-on time
Turn-off time
-------
RL
~
300O,
--- ' - - - - - - - - - -
CL
~
30 pF,
~
25"C
TA = 25°C
-20 V. VLL - 5 V. Vref -0 V. TA = 25°e
TEST CONDITIONS
PARAMETER
ton
toft
TA
Both control inputs at 0 V
Figure 1
------
Tl1_M
Tl1_1
TL1_C
TYP
TYP
175
350
TYP
175
175
350
350
UNIT
V
V re f+ 2
V re f+ O.8
~
~
MAX
10
~
~
MIN
V re f+ O.8
Vs
IS
TLl_C
MAX
TA - 25"C
Vil
Vil
2 V,
MIN
TA - 25"C
Tl182,
rOSlon)
~
Tl1_1
MAX
TA = MIN to MAX
VO~-10V,
ISlott)
MIN
TA
input voltage
Low-level control
Vil
TL1_M
TEST CONDITIONS
High-Ieve! control
OV
V
.A
.A
nA
nA
nA
{l
mA
mA
-I
r-
=
N
-I
r-
m-
UNIT
-=
• CTI
n.
0-1
3:-
-
en ren=
E?'
=i-l
nr:z:
mea
en-
N
en
(0
Data Acquisition Circuits
TL182, TL185, TL188, TL191
BI·MOS SWITCHES
PARAMETER MEASUREMENT INFORMATION
Vee = 15 V
VLL = 5 V
OUTPUT
D
VEE --15 V
CL includes probe and jig capacitanca
Vs • 3 V fo, ton and -3 V for toft
RL
VO=VS --::...-RL + 'DSlon)
TEST CIRCUIT
3'C:
tf <10ns
x=t.<10;s..-----3V
'\
I
INPUT A
1\
I
,I
I
'-----$r-'.
ton-j4---+!
7
OV
I
- --;;,;-V-;;+--r-vot----- OUTPUT
~tOff
----~---~
0.1 Va
3V
OV
va
------------------~V
NOTE: A. The solid waveform applies for TL i 85 and SWl of TL185 and TL 191; the dashed waveform applies for TL 182 and SW2 of
TL185 and TL191.
B. Vo is the steady-state output with the switch on. Feed through via the gate capacitance may result in spikes (not shown I at
the leading and trailing edges of the output waveform.
FIGURE 1. VOLTAGE WAVEFORMS
2-70
TEXAS
-II
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
TL500C THRU TL503C
ANALOG-TO-DIGITAL-CONVERTER BUILDING BLOCKS
02477. DECEMBER 1979-REVISEO DECEMBER 1986
TL500CITL501 C
ANALOG PROCESSORS
•
True Differential Inputs
•
Automatic Zero
•
Automatic Polarity
-3
•
High Input Impedance • . . 109 Ohms
Typically
(j
...en
TL501C CAPABILITIES
TL500C CAPABILITIES
•
•
•
Resolution . . . 14 Bits (with TL502C)
Linearity Error •.. 0.001%
4 1/2-Digit Readout Accuracy with External
Precision Reference
•
•
•
•
•
•
•
Resolution ... 10-13 Bits (with TL502C)
Linearity Error ... 0.01 %
3 1/2-Digit Readout Accuracy
C
o
-iii
'3
-+l
cr
()
c(
J9as
TL502C CAPABILITIES
TL502C/TL503C
DIGITAL PROCESSORS
•
•
~
Fast Display Scan Rates
•
Compatible with Popular Seven-Segment
Common-Anode Displays
Internal Oscillator May Be Driven or
Free-Running
•
High-Slnk-Current Segment Driver for Large
Displays
Interdigit Blanking
Q
TL503C CAPABILITIES
Over-Range Blanking
4 1/2-Digit Display Circuitry
High-Sink-Current Digit Driver for Large
Displays
•
•
Multiplexed BCD Outputs
High-Sink-Current BCD Outputs
Caution. These devices have limited built-in gate protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
description
The TL500C and TL501 C analog processors and TL502C and TL503C digital processors provide the basic
functions for a dual-slope-integrating analog-to-digital converter.
The TL500C and TL501 C contain the necessary analog switches and decoding circuits, reference voltage
generator, buffer, integrator, and comparator. These devices may be controlled by the TL502C, TL503C,
by discrete logic, or by a software routine in a microprocessor.
The TL502C and TL503C each includes oscillator, counter. control logic. and digit enable circuits. The
TL502C provides multiplexed outputs for seven-segment displays, while the TL503C has multiplexed BCD
outputs.
When used in complementary fashion, these devices form a system that features automatic zero-offset
compensation, true differential inputs, high input impedance, and capability for 4 1/2-digit accuracy.
Applications include the conversion of analog data from high-impedance sensors of pressure, temperature,
light, moisture, and position. Analog-to-digital-Iogic conversion provides display and control signals for
weight scales, industrial controllers, thermometers, light-level indicators, and many other applications.
PRODUCTION DATA documonts contain informllion
currant I I of publication date. Products conform to
opoolficllion. por tho tarms of Ta..s I.strumanla
:'~=~~i~·ir::1~1i ~:=:~ti:; :.r::;::~::'1 nat
Copyright © 1979. Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-71
TL500C THRU TL503C
ANALOG· TO·DIGITAL·CONVERTER BUILDING BLOCKS
principles of operation
The basic principle of dual-slope-integrating converters is relatively simple. A capacitor, CX, is charged
through the integrator from VCT for a fixed period of time at a rate determined by the value of the unknown
voltage input. Then the capacitor is discharged at a fixed rate (determined by the reference voltage) back
to VCT where the discharge time is measured precisely. The relationship of the charge and discharge values
are shown below (see Figure 1).
Vcx
VIt1
VCT - - RX Cx
Vref t2
VCT = Vcx - - - RX Cx
Combining equations 1 and 2 results in:
Charge
(1 )
Discharge
(2)
(3)
where:
VCT
VCX
VI
t1
t2
= Comparator (offset) threshold voltage
= Voltage change across Cxduring t1 and during t2 (equal in magnitude)
= Average value of input voltage during t1
= Time period over which unknown voltage is integrated
= Unknown time period over which a known reference voltage is integrated.
Equation (3) illustrates the major advantages of a dual-slop converter:
a. Accuracy is not dependent on absolute values of t1 and t2, but is dependent on their ratios. Longterm clock frequency variations will not affect the accuracy.
b. Offset values, VCT, are not important.
The BCD counter in the digital processor (see Figure 2) and the control logic divide each measurement
cycle into three phases. The BCD counter changes at a rate equal to one-half the oscillator frequency.
auto-zero phase
The cycle begins at the end of the integrate-reference phase when the digital processor applies low levels
to inputs A and B of the analog processor. If the trigger input is at a high level, a free-running condition
exists and continuous conversions are made. However, if the trigger input is low, the digital processor
stops the counter at 20,000, entering a hold mode. In this mode, the processor samples the trigger input
every 4000 oscillator pulses until a high level is detected. When this occurs, the counter is started again
and is carried to completion at 30,000. The reference voltage is stored on reference capacitor Cref,
comparator offset voltage is stored on integration capacitor CX, and the sum of the buffer and integrator
offset voltages is stored on zero capacitor CZ. During the auto-zero phase, the comparator output is
characterized by an oscillation (limit cycle) of indeterminate waveform and frequency that is filtered and
d-c shifted by the level shifter.
integrate-input phase
The auto-zero phase is completed at a BCD count of 30,000, and high levels are applied to both control
inputs to initiate the integrate-input phase. The integrator charges CXfor a fixed time of 10,000 BCD counts
at a rate determined by the input voltage. Note that during this phase, the analog inputs see only the high
impedance of the noninverting operational amplifier input. Therefore, the integrator responds only to the
difference between the analog input terminals, thus providing true differential inputs.
2-72
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TL500C THRU TL503C
ANALOG· TO·DIGITAL·CONVERTER BUILDING BLOCKS
integrate-reference phase
At a BCD count of 39,999 + 1 = 40,000 or 0, the integrate-input phase is terminated and the integratereference phase is begun by sampling the comparator output. If the comparator output is low corresponding
to a negative average analog input voltage, the digital processor applies a low and a high to inputs A and
B, respectively, to apply the reference voltage stored on Cref to the buffer. If the comparator output is
high corresponding to a positive input, inputs A and B are made high and low, respectively, and the negative
of the stored reference voltage is applied to the buffer. In either case, the processor automatically selects
the proper logic state to cause the integrator to ramp back toward zero at a rate proportional to the reference
voltage. The time required to return to zero is measured by the counter in the digital processor. The phase
is terminated when the integrator output crosses zero and the counter contents are transferred to the
register, or when the BCD counter reaches 20,000 and the over-range indication is activated. When
activated, the over-range indication blanks all but the most significant digit and sign.
til
!!
'5
...
(,)
c:5
c
o
~
Seventeen parallel bits (4-1/2 digits) of information are strobed into the buffer register at the end of the
integration phase. Information for each digit is multiplexed out to the BCD outputs (TL503C) or the sevensegment drivers (TL502C) at a rate equal to the oscillator frequency divided by 400.
BCD COUNTER VALUES
20.000
,
30.000
a
I '
'AUTOZEROllillTEGRATEI
I
I INPUT
:
I
:
I
I
HOLD
I i :
I
I
I ,
I
I
I
I
:
I
I
I
I
V(pinl)
ANALOG PROCESSOR
TL500 OR TL501
BUFFER
OUTPUT
Tl502 OR TL503
(See
Note AJ
.. =
r - - - - -- - - - - - -"Y" ~~+-,
Cx
RX
:z:,o-l
2 ....
:z:,oc:n
DIGITAL PROCESSOR
~
INTEGRATOR
OUTPUT
------,I
,
OSCILLATOR
INPUT
,
...------,
i
I
':
w_",.n
I
I
J
~
•
QCI
I
<;> TRIGGER
INPUT
i
(See Note B)
I
C)n
~-I
.=
Q=
5!c
S-I
-I ....
:z:,oc:n
. w
.... CI
gn
LEVEL
SHIFTER
Cz
~
~
"'~Z
ANALOG SWITCH
LOGIC CONTROL
C
i=
~
---
ANALOG
GROUND
C)
I
I
U
L
I
fi '
iii
I
I
I
I
~
~
CII
I
I
I
~C::~
;~
~
m
C,.f
~;C~
~~~
=:
=
CCI
§~
~!TI
2
<
m
CONTROL
LOGIC
I __ _
L
_J
---DIGITAL
COMMON
__ __
DIGIT-ENABLE
________ .JII
-LAND DRIVERS
I
COMMON
OUTPUTS
(01 THRU 05)
NOTES: A, Pin 18 of the TL502 provides an output of fosc loscillator frequency)
B. The trigger input assumes a high level if not externally connected.
+
20,000.
FIGURE 2. BLOCK DIAGRAM OF BASIC ANALOG-TO-DIGITAL CONVERTER USINGTL500C or TL501C and TL502C or TL503C
MODE
Auto Zero
ANALOG
INPUT
COMPARATOR
X
Oscillation
Hold t .
Integrate
Positive
H
Input
Negative
L
Integrate
Reference
X
CONTROLS
ANALOG SWITCHES
AAND B
CLOSED
L
L
S3, S4, 57, S9, S10
H
H
51,52
L'
L
H
53, 56, 57
H'
H
L
53,55,58
H '" High, L '" low, X '" Irrelevant
t If tbe trigger input is low at the beginning of the auto-zero cycle, the system will enter the hold mode. A high level (or open circuit) will signal the digital process~r
to continue or resume normal operation.
t This is the state of the comparator output as determined by the polarity of the analog input during the integrate input phase.
CCI
....
Q
n
~
TL500C, TL501 C
ANALOG PROCESSORS
J DUAL·IN·L1NE PACKAGE
description of analog processors
(TOP VIEW)
The TL500C and TL501 C analog processors are
ANALOG INPUT 1
designed to automatically compensate for
ANALOG INPUT 2
internal zero offsets, integrate a differential
REF OUTPUT
VCC+
voltage at the analog inputs, integrate a voltage
BUFFER OUTPUT
REF INPUT
at the reference input in the opposite direction,
INTEGRA TOR INPUT
ANALOG GND
and provide an indication of zero·voltage
INTEGRATOR OUTPUT
Cref+
crossing. The external control mechanism may
VCCCrefbe a microcomputer and software routing,
DIGITAL COMMON
CONTROL B INPUT
discrete logic, or a TL502C or TL503C controller.
CONTROL A INPUT -...;._--.:..- COMPARATOR OUTPUT
The TL500C and TL501 C are designed primarily
for simple, cost·effective, dual-slope analog-todigital converters. Both devices feature true
differential analog inputs, high input impedance,
and an internal reference-voltage source. The TL500C provides 4-1/2-digit readout accuracy when used
with a precision external reference voltage. The TL501 C provides 100-ppm linearity error and 3-1 /2-digit
accuracy capability. These devices are manufactured using TI's advanced technology to produce JFET,
MOSFET, and bipolar devices on the same .chip. The TL500C and TL501 C are intended for operation over
the temperature range of ODC to 70 DC.
•
....en
.
"S
C,)
C3
c
o
~
'iii
'S
C'
C,)
«
....caca
C
schematics of Inputs and outputs
CONTROL A AND CONTROL B INPUTS
COMPARATOR OUTPUT
OUTPUT
INPUT
DIGITAL
COMMON
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Positive supply voltage, VCC + (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. + 18 V
Negative supply voltage, VCC _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -18 V
Input voltage, V, ......................................................... ± VCC
Comparator output voltage range (see Note 2) .............................. 0 V to VCC+
Comparator output sink current (see Note 2) .................................... 20 mA
Buffer, reference, or integrator output source current (see Note 2) .................... 10 mA
Total dissipation at (or below) 25 DC free-air temperature (see Note 3) . . . . . . . . . . . . . .. 1025 mW
Operating free-air temperature range ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0 DC to 70 DC
Storage temperature range ......................................... - 65 DC to 150 DC
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds. . . . . . . . . . . . . . . . . . . . .. 300 DC
NOTES: 1. Voltage values, except differential voltages, are with respect to the analog ground common pin tied together.
2. Buffer, integrator, and comparator outputs are not short~circuit protected.
3. For operation above 25·C free·air temperature, refer to Dissipation Derating Curves, Appendix A. TL500C and TL501 C chips
are glass mounted.
TEXAS
-If
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-75
TL500C. TL501C
ANALOG PROCESSORS
recommended operating conditions
Positive supply voltage, Vcc +
C
MIN
NOM
MAX
7
12
-12
15
Negative supply voltage, VCC
-9
Reference input voltage, V refill
0.1
Analog input voltage, VI
I»
....
I»
Differential analog input voltage, VID
I Control inputs
I Control inputs
»
.Q
Peak positive integrator output voltage, VOM +
C
Peak negative integrator output voltage, VOM-
:=.'
Full scale input voltege
Autozero and reference capacitors. Cz and eref
0.2
:::s
Integrator capacitor, Cx
0.2
Low-level input voltage, VIL
(')
iii'
0'
n
5
V
±5
V
10
V
V
V
V
+9
-5
V
2 Vref
15
100
"F
"F
kG
See
Integrator time constant, RXCX
::+
(/)
V
V
0.8
Integrator resistor, RX
~r
c
-15
2
High-level input voltage, VIH
UNIT
Note 4
0
Free-air operating temperature, T A
70
12.5
3
Maximum conversion rate with TL502 or TL503
system electrical characteristics at Vcc± (unless otherwise noted) (see Figure 3)
± 12 V, Vref - 1,000 ± 0.03 mV, TA - 25°C
TEST CONDITIONS
PARAMETER
°C
cony/sec
TYP
MAX
TYP
MAX
50
300
10
0.005
0.05
0.001
30
0.005
Zero error
Linearity error relative to full scale
VI = -2 V to 2 V
Full scale temperature coefficient
TA = ooC to 70°C
Temperature coefficient of zero error
TA = O°C to 70°C
TL500C
TL501C
MIN
Rollover error t
Equivalent peak-to-peak input noise voltage
6
4
200
20
109
MIN
6
1
500
30
20
109
UNIT
/LV
%FS
ppm/oC
"V/oC
100
"V
/LV
G
Analog input resistance
Pin 1 or 2
Common-mode rejection ratio
VIC = - 1 V to + 1 V
86
90
dB
Current into analog· input
VI = ±5 V
50
50
pA
90
90
dB
Supply voltage rejection ratio
tRoliover error is the voltage difference between the conversion results of the full-scale positive 2 volts and the full-scale negative 2 volts.
NOTE 4. The minimum integrator time constant may be found by use of the following formula:
VID (full scale) tl
Minimum RXCX =IVOM-I-Vlfpin 2)
where
VID = voltaga at pin with respect to pin 2
VI(pin 2) = voltage at'pin 2 with respect to analog ground
tl = input integration time seconds
2-76
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75266
TL500C, TL501C
ANALOG PROCESSORS
electrical characteristics at Vcc± -
± 12 V. Vref - 1 V. TA = 25°C (see Figure 3)
integrator and buffer operational amplifiers
PARAMETER
TEST CONDITIONS
MIN
TYP
VIO
Input offset voltage
15
liB
Input bias current
VOM+
Positive output voltage swing
50
11
VOM-
Negative output voltage swing
AVO
Bl
CMRR
Voltage amplification
SR
Output slew rate
9
-5
Unity-gain bandwidth
MAX
mV
pA
V
-7
V
110
dB
MHz
3
Common mode rejection
VIC -
100
- 1 V to + 1 V
UNIT
dB
5
V/"s
comparator
TEST CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
VIO
Input offset voltage
15
mV
liB
Input bias current
50
pA
AVO
VOL
Voltage amplification
100
dB
Low-level output vOltage
IOH
High-level output current
200
400
mV
5
20
nA
MIN
TYP
MAX
UNIT
1.12
1.22
1.32
V
1.tsmA
'OL
VOH - 3 V
!!
.
U
'3
u
c
o
';;
'3
C'
u
n
J:I
C
iii"
;:;."
0"
:::I
(')
~"
n
C
;:;."
5V
(12)
(16)
2
kn
VCC_
COMPARATOR (10)
OUTPUT
MPU
LOGIC
CONTROLLER
ISee Note C)
(9)
CONTROL A
(8)
CONTROL 8
BUFFER
OUTPUT
(15)
INTEGRATOR
INPUT
(14)
D
RX=27kn
INTEGRATOR
OUTPUT (13)
t1 = 100 InS
fTom
VIDlfuU ...Ie)t1
RXCX = VOM-VUPIN 2)
Cx = 1 "F
I..e Note D)
en
NOTES: C. T<>sts are started approximately 5 seconds after power-on.
D. Capacitors used are TRW's X363UW polypropylene or equivalent for CX, Cref, and CZ; however for Cref and Cz film-dielectric
capacitors may be substituted.
FIGURE 3. TEST CIRCUIT CONFIGURATION
external-component selection guide
The autozero capacitor Cz and reference capacitor Cref should be within the recommended range of
operating conditions and should have low-leakage characteristics. Most film-dielectric capacitors and some
tantalum capacitors provide acceptable results. Ceramic and aluminum capacitors are riot recommended
because of their relatively high-leakage characteristics.
The integrator capacitor Cx should also be within the recommended range and must have good voltage
linearity and low dielectric absorption. A polypropylene-dielectric capacitor similar to TRW's X363UW is
recommended for 4-1/2-digit accuracy. For 3-1/2-digit applications, polyester, polycarbonate, and other
film dielectrics are usually suitable. Ceramic and electrolytic capacitors are not recommended.
Stray coupling from the comparator output to any analog pin (in order of importance 17, 18, 14, 7, 6,
13, 1, 2, 15) must be minimized to avoid oscillations. In addition, all power supply pins should be bypassed
at· the package, for example, by a O.Ol-,.F ceramic capacitor.
Analog and digital common are internally isolated and may be at different potentials. Digital common can
be within 4 volts of positive or negative supply with the logic decode still functioning properly.
The time constant RXCX should be kept as near the minimum value as possible and is given by the formula:
. .
VID (full scale) t1
MInimum RXCX = IVOM- I - V I(pin
. 2)
where:
VID(full scale) = Voltage on pin 1 with respect to pin 2
t1 = Input integration time in seconds
Vl(pin 2) = Voltage on pin 2 with resepct to analog ground
2-78
TEXAS ...,
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75285
TL502C. TL503C
DIGITAL PROCESSORS
TL502 ... N DUAL·IN·L1NE PACKAGE
ITOPVIEWI
description of digital processors
The TlS02C and TlS03C are control logic
devices designed to complement the TlSOOC
and TlS01 C analog processors. They feature
interdigit blanking, over-range blanking, an
internal oscillator, and a fast display scan rate.
The internal-oscillator input is a Schmitt trigger
circuit that can be driven by an external clock
pulse or provide its own time base with the
addition of a capacitor. The typical oscillator
frequency is 120 kHz with a 470-picofarad
capacitor connected between the oscillator input
and ground.
CONTROL B OUTPUT
01 (LSBI
DIGIT
02
{
ENABLE
03
04
OUTPUTS
D5IMSBI*
VCC
CONTROL A OUTPUT
20,000t
OSCILLATOR INPUT
TRIGGER
COMPARATOR INPUT
~}7-SEGMENT
7-SEGMENT{A
DRIVER
B
OUTPUTS
C
ED
DIGITAL COMMON '-L-=---";.;J-'
DRIVER
OUTPUTS
TL503 ... N DUAL-IN-LINE PACKAGE
ITOP VIEWI
The TlS02C provides seven-segment-display
output drivers capable of sinking 100
milliamperes and compatible with popular
common-anode displays. The TlS03C has four
BCD output drivers capable of 100-milliampere
sink currents. The code (see next page and
Figure 4) for each digit is multiplexed to the
output drivers in phase with a pulse on the
appropriate digit-enable line at a digit rate equal
to fosc. divided by 200. Each digit-enable output
is capable of sinking 20-milliamperes.
CONTROL B OUTPUT
VCC
01 ILSBI
CONTROL A OUTPUT
DIGIT
02
OSCILLATOR INPUT
{
ENABLE
03
TRIGGER
04
COMPARATOR INPUT
OUTPUTS
D5IMSBI*
03
02
00
DIGITAL COMMON l..I2._--'!J~01
t Pin 18 of TL502 provides an output of fosc loscillator frequenciesl
320,000.
*05, the most significant bit, is also the sign bit.
The comparator input of each device, in addition
to monitoring the output of the zero-crossing
detector in the analog processor, may be used
in the display test mode to check for wiring and
display faults. A high logic level (2 to 6.S volts)
at the trigger input with the comparator input at
or below 6.S volts starts the integrate-input
phase. Voltage levels equal to or greater than 7.9
volts on both the trigger and comparator inputs
clear the system and set the BCD counter to
20,000. When normal operation resumes, the
conversion cycle is restarted at the auto zero
phase.
These devices are manufactured using 12 l and
bipolar techniques. The TlS02C and TlS03C are
intended for operation from O°C to 70°C.
TABLE OF SPECIAL FUNCTIONS
Vee - 5V :1:10%
TRIGGER
INPUT
COMPARATOR
INPUT
VlpSO.8 V
Vls6.5
2 VsVISS.5 V
VlsS.5
Vls6.5 V
VI2:7.9
VI2:7.9 V
VI, VIL
I
I
Comparator and "trigger inputs
cr
u
MIN
NOM
MAX
4.5
5
5.5
2
Comparator and trigger inputs
Operating free-air temperature
0
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
0.8
70
UNIT
V
V
V
·C
ca
-;
Q
2-81
s~!nOJ!O Uo!~!s!nbo" e~ea
'"
00
'"
CI-t
-,...
electrical characteristics at 25°C free-air temperature
PARAMETER
VIK
Input clamp voltage
Positive-going input
VT+
VTVT+ - VT-
threshold voltage
Negative-going input
threshold voltage
Hysteresis
QU'!
::::j=
TERMINAL
All inputs
TL502C
TEST CONDITIONS
Vec - 4.5 V,
II
MIN
=
-12mA
TYP
-0.8
)ioN
TL503C
MAX
-1.5
MIN
TYP
MAX
-0.8
-1.5
UNIT
,...5"
V
:r:I ,...
Oscillator
VCC
=
5 V
1.5
1.5
V
Oscillator
VCC
=
5 V
0.9
0.9
V
Oscillator
VCC
=
5 V
0.4
0.6
0.8
0.4
0.6
0.8
positive-going input
Oscillator
VCC
=
5 V
-40
-94
-170
-40
-94
-170
~A
Oscillator
VCC
=
5 V
40
117
170
40
117
170
~
4.15
4.4
4.15
4.4
VCC
= 4.5
4.25
4.4
4.25
4.4
4.25
4.4
threshold voltage
Input current at
~
IT-
negative-going input
threshold voltage
0
::1_
r:iz
i'lrJ)
Digit enable
VOH
High-level output voltage
X""'l
c~
~
I"(TI
Digit enable
Pin 18 (TL502C only)
VOL
Low-level output voltage
z4r~.
~ (jj
~
>
en
II
Input current
IIH
High-level input current
IlL
Low-level input voltage
~
~
~
V,
=0
IOH
Control A and B
~;:o~
;~
Pin 18 (TL502C only)
Control A and B
VCC
= 4.5
V
High-level output current
(Output transistor off)
Low-level output current
IOL
ICC
(Output transistor on)
Supply current
10 mA
2 mA
100 mA
IOL
IOL
BCD drivers
IOL - 100 mA
Oscillator
Comparator, Trigger
Oscillator
Oscillator
Comparator, Trigger
VCC
=
5.5 V,
VI
=
5.5 V
VCC
=
5.5 V,
VI
=
2.4 V
VCC
=
5.5 V,
VI
= 0.4
Segment drivers
Va
BCD drivers
Va
Va
=
Va
Pin 18 (TL502C only)
Control A and 8
Va
VCC
= 4.5 V
= 4.5
Digit enable
VCC
VCC
VCC - 5.5 V
V,
Va
0.15
0.4
0.088
0.4
0.17
0.3
65
100
-0.6
-1
0.5
-0.1 -0.17
-1
-2.5
-4
V
-0.5
-0.9
V
-0.25
-0.4
V,
0.2
0.5
0.088
0.4
0.3
65
100
~A
mA
-0.6
1
-1
0.5
-0.1 -0.17
-1.6
-1
-2.5
-4
-0.25
-0.4
-1.6
mA
mA
mA
0.25
V
0.25
V
3.55 V
V
0.17
1
V'
= 0.5
= 0.5
= 0.5
= 5.5
= 5.5
Digit enable
IOH
=
=
=
Segment drivers
Comparator, Trigger
V
IOL - 20 mA
IOL
18
23
73
mA
110
73
110
n=
mW
enn
en
Q
:r:I
en
Input current at
IT+
"'a-t
QU'!
mA
TL502C. TL503C
DIGITAL PROCESSORS
special functions t operating characteristics at 25°C free-air temperature
PARAMETER
TEST CONDITIONS
Input current into
VI
Vcc = 5.5 V.
Vee = 5.5 V.
comparator or trigger inputs
= 8.55
MIN
V
VI = 6.25 V
TYP
MAX
1.2
1.8
0.5
tThe comparator and trigger inputs may be used in the normal mode or to perform special functions. See the Table of Special Functions.
•
...en
·S
...U
U
TYPICAL APPLICATION DATA
c
o
'';::
1-
01-------~
--f~~--~--~-----.----------------------------------------:--- 16.7 /-IS (se. Not. E)
316.71'.::=t
I
'iii
·S
a-
U
I
' > - _ . - - - 0 COMP
OUT
()
.Q
C
(ij'
;::;.'
0'
Cz
::l
.
o
(2)1
:::;'
B
S3A
ANALOG~
()
c
INPUT
;:;:
A
I
I
(3).
(II
1(7)
~
I
I
______________________ ~---~-J
(5)
GND
(9)
GND
NOTE: Analog and digital GND are internally connected together.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 18 V
Input voltage, pins 2, 4, 6, and 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2) . . . . . . .. 875 mW
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260°C
NOTES:
1. Voltage values are with respect to the two ground terminals connected together.
2. For operation above 25°C free-air temperature, derate linearly to 560 mW at 70°C at the rate of 7.0 mw/oe.
recommended operating conditions
Supply voltage. Vee
NOM
MAX
7
9
15
4
3
0
0.5
3.6
VCC+l
0.2
1.S
See "component selection"
0.5
2
16.6
500
0
70
Analog input voltage, VI
Reference input voltage, Vref(l)
High-level input voltage at A or B, VIH
low-level input voltage at A or B, Vll
Integrator ca'pacitor, eX
Integrator resistor, RX
Integration time, t1
Operating free-air temperature, T A
2-86
MIN
TEXAS . "
INSTRUMENlS
POST OFJ=ICE BOX 6~5012
II
DALLAS, TEXAS 75265
UNIT
V
V
V
V
V
MO
ms
°c
TL505C
ANALOG·TO·DIGITAL CONVERTER
electrical characteristics. Vee
(unless otherwise noted)
9 V. Vref(l) - 1 V. TA - 25 oe. connected as shown in Figure 1
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage at pin 8
IOH ~ 0
IOH
High-level output current at pin 8
VOH - 7.5 V
VOL
Low-level output voltage at pin 8
IOL - 1.6 mA
Maximum peak output voltage
YOM
Vrel(O)
swing at integrator output
Reference output voltage
Temperature coefficient of
aVref
reference output voltage
MIN
TYP
7.5
8.5
V
100
~A
200
RX ;;, 500 kll
1.15
TA ~ O°C to 70°C
High-level input current into A or B
VI - 9 V
IlL
Low-level input current into A or B
II
Current into analog input
VI - 1 V
to 4 V,
VI
liB
Total integrator input bias current
ICC
Supply current
o
400
1.22
1.35
A input at 0 V
~A
10
200
~A
±10
±200
pA
4.5
'5
~
(j
V
10
±10
No load
:!
mV
ppm/DC
±100
1
•
UNIT
V
VCC-2 VCC-l
Irel ~ -100 ~A
IIH
MAX
PARAMETER
TEST CONDITIONS
VI - 0
Linearity error
VI - 0 to 4 V
Ratiometric reading
Temperature coefficient of
VI - Vrel(l) ~ 1 V
Vrel(l) constant and ~ 1 V,
ratiometric reading
TA = OOC to 70°C
MIN
0.998
8
0-
u
c:(
mA
TYP
MAX
0.1
0.4
mV
0.02
0.1
%FS
1.000
1.002
±10
o
'iii
'5
pA
f!
as
C
system electrical characteristics. Vee" 9 V. Vref(l) - 1 V. TA - 25°e. connected as shown in
Figure 1 (unless otherwise noted)
Zero error
C
'';::
UNIT
ppm/DC
DEFINITION OF TERMS
Zero Error
The intercept (b) of the anolog-to-digital converter system transfer function y = mx + b. where y is the
digital output. x is the analog input. and m is the slope of the transfer function. which is approximated
by the ratiometric reading.
Linearity Error
The maximum magnitude of the deviation from a straight line between the end points of the transfer function.
Ratiometric Reading
The ratio of negative integration time (t2) to positive time (t1).
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-87
TL50.5C
ANALOG·TO·DIGITAL CONVERTER
PRINCIPLES OF OPERATION
A block diagram of an MPU system utilizing the TL505C is shown in Figure 1. The TL505C operates in
a modified positive-integration three-step dual-slope conversion mode. The AID converter waveforms during
the conversion process are illustrated in Figure 2.
VCC
RX
Cx
1 Mn
0.01 "F
(12'---- (111-----
(10)
I
I
I
I
I
I
I
S2C
Cz
:
MPU
CONTROLLER
A 1(7)
rLOGK~~~~~I~I~O-kn-1-U
LOGIC DECODE
A
I ~.. F(14):' S3A
ANALOG ~
INPUT (2):
AND
B '(6)10
SWITCH DRIVERS
(31'
kn
B
i
.
L______________________ ~---~-J
~(5)
~(9)
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF TL505C INTERFACE WITH A MICROPROCESSOR SYSTEM
FUNCTION TABLE
I
A------II
CONTROLS
I
I
I
B------~I------~I
I
I
A
I
I
-V2
I
COMPARATOR
OUTPUT
L
L
H
H
I
L
H
.rm.1IJl1I
I
_\1W!1I!\\IJmI'II\1I _ _ _ _ _~_ _
,1II111R11IMIIIMIlI
I
i
--to---+l·I~"---t'
.1.
t2-..I.>----to-.
V, =V2 - V3= VI +VO(ofs)
FIGURE 2. CONVERSION PROCESS TIMING DIAGRAMS
2-88
51.52
53
51,54
I
Vl- rVo(ofs)
IT
SWITCHES CLOSED
I
I
I
INTEGRATOR
OUTPUT
.........
. TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
ANALOG
B
TL505C
ANALOG-TO-DIGITAL CONVERTER
PRINCIPLES OF OPERATION
The first step of the conversion cycle is the auto-zero period to during which the integrator offset is stored
in the auto-zero capacitor and the offset of the comparator is stored in the integrator capacitor. To
accomplish this, the MPU takes the A and B inputs both low. This is decoded by the switch drivers, which
close 51 and 52. The output of the comparator is connected to the input of the integrator through the
low-pass filter consisting of RZ and CZ. The closed loop of A 1 and A2 will seek a null condition where
the offsets of the integrator and comparator are stored in Cz and CX, respectively. This null condition
is characterized by a high-frequency oscillation at the output of the comparator. The purpose of 52B is
to shorten the amount of time required to reach the null condition.
•
en
_t::
~
u
...
U
c
At the conclusion of to, the MPU takes the A and B inputs both high closing 53 and opening all other
switches. The input signal VI is applied to the non inverting input of A 1 through CZ. VI is then positively
integrated by A 1. 5ince the offset of A 1 is stored in CZ, the change in voltage across Cx will be due to
only the input voltage. It should be noted that since the input is integrated in a positive integration during
t1, the output of A 1 will be the sum of the input voltage, the integral of the input voltage, and the comparator
offset, as shown in Figure 2. The change in voltage across capacitor Cx (VCX) during t1 is given by
';;
-5
(1 )
....asas
where R1
=
RX
o
'';::
C"
~
Q
+ RS3B and
R53B is the resistance of switch 53B.
At the end of t1, the MPU takes the A input low and the B input high closing 51 and 54 and opening
all other switches. In this state, the reference is integrated by A 1 in a negative sense until the integrator
output reaches the comparator threshold. At this point, the comparator output goes high. This change
in state is sensed by the MPU, which terminates t2 by again taking the A and B inputs both low. During
t2, the change in voltage across Cx is given by
AVCX(2)
where R2
=
RX
+
RS4
+
=
Vreft2
R2 CX
(2)
Rref and
Rref is the equivalent resistance of the reference divider.
Since AVCX1 = -AVCX2, equations (1) and (2) can be combined to give
VI
= Vref
R1 • t2
R2 • t1
(3)
This equation is a variation on the ideal dual-slope equation, which is
(4)
Ideally then, the ratio of R1/R2 would be exactly equal to one. In a typical TL505C system where
RX = 1 MO, the scaling error introduced by the difference in R1 and R2 is so small that it can be neglected
and equation (3) reduces to (4).
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-89
TL505C
ANALOG· TO· DIGITAL CONVERTER
TYPICAL APPLICATION DATA
•
RX
C
AI
;
SIGNAL OUT
CaMP
»
K(X)
SEE NOTE 3
n
.c
c
iii'
;:;
o·:::I
A
TMS1000
SERIES
10
kO
10kO
LOGIC
SEGMENT
DRIVE
R8
CONTROL
B
...Q
R9
LINES
n
c
;:;
DIGIT
DRIVE
-11-11-'
'=UI-I
TIL312 LED
.,..
UI
DISPLAYS
NOTE 3: Connect to either 9 V or 0 V depending on which device in the TMS1000 series is used and how it is programmed.
FIGURE 3. TL505C IN CONJUNCTION WITH A TMS1000 SERIES MICROPROCESSOR
FOR A 3·DIGITAL PANEL METER APPLICATION
5V
12V
5601N914
1 kll
FROM
AUDIO
SYSTEM
0.5
8ll
"F
ANALOG
INPUT
IN
B
470pF
TL505
GND
RX2
"::"
D2
D1
TIS91
2.2kO
9
A
B
A
REF
VCC
CaMP/LAMP
TEST
CaMP
OUT
2.2 kll
1N91
VCC
OSC
INPUT
e
d
TL502
J
b
a
CZ1
RX1/CX1
6.8 "F
0.22
CZ2
GND
CX2
•
"F
SEGMENT
TIL807
FIGURE 4. AUDIO PEAK POWER METER
2-90
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
9,D1.D2
TL5071, TL507C
ANALOG-TO-DIGITAL CONVERTER
02503, OCTOBER 1979- REVISEO SEPTEMBER 1986
DB
P DUAL-IN·LlNE PACKAGE
(TOPVIEWI
•
low Cost
•
7-Slt Resolution
•
Guaranteed Monotonicity
•
Ratiometric Conversion
•
Conversion Speed ... Approximately 1 ms
•
Single-Supply Operation ... Either
Unregulated a-v to 18-V (VCC2 Input), or
Regulated 3.5-V to 6-V (VCC1 Input)
•
12 l Technology
•
Power Consumption at 5 V ... 25 mW Typ
•
Regulated 5.5-V Output (:s 1 rnA)
ENABLE
ClK
GND
OUTPUT
2
3
4
7
6
5
RESET
VCC2
VCC1
ANALOG INPUT
FUNCTION TABLE
ANALOG
INPUT CONDITION
ENABLE
OUTPUT
X
It
H
l
H
l
VI
< 200 mV
H
H
H
V ramp > VI > 200 mV
VI> Vramp
description
tlow level on enable also inhibits the reset function.
The TL507 is a low-cost single-slope analogH = high level, l = low level, X = irrelevant
to-digital converter designed to convert analog
A high level on the reset pin clears the counter to zero, which sets
input voltages between 0.25 VCC1 and 0.75
the internal ramp to 0.75 Vee. Internal pull down resistors keep
VCC1 into a pulse-width-modulated output
the reset and enable pins low when not connected.
code. It contains a 7-bit synchronous counter,
a binary weighted resistor ladder network, an operational amplifier, two comparators, a buffer amplifier,
an internal regulator, and necessary logic circuitry. Integrated-injection logic (l2L) technology makes it
possible to offer this complex circuit at low cost in a small dual-in-line a-pin package.
In continuous operation, it is possible to obtain conversion speeds up to 1000 per second. The Tl507
requires external signals for clock, reset, and enable. Versatility and simplicity of operation, coupled with
low cost, make this converter especially useful for a wide variety of applications.
The TL507C is characterized for operation from 0 °C to 70°C, and the TL5071 is characterized for operation
from -40°C to a5~C.
functional block diagram (positive logic)
COMPARATOR 2
200mV
ANALOG~15~1________________________________~,
INPUT
CTR
R
MSBO
+
RESET IBI
III
ENABLE
R
0
0
0
0
0
LSBO
R
2
4R
COMPARATOR 1
BR
R
32R
B4R
~
REGULATOR
171
0.25 VCCI
IBI
VCC2
VCCI
131
L----'--'-GND
~ indicates an n-p-n open-collector output.
PRODUCTION DATA d•••m.... c.ntllal_fermatl._
current I. of p.bllcati•• dl". Praduall ....mar.. 10
_ificatlo.. par the lanns of Tillis I_atrvmonll
lb...... WIImInt,. P,.ducllo. prac...I•• d... not
nc"",,,", Incl••• inti_a of .11 pln..-1.
Copyright
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TEXAS 75265
@
1979, Texas Instruments Incorporated
2-91
TL5071, TL507C
ANALOG·TO·DlGITAL CONVERTER
schematics of inputs and outputs
II
EQUIVALENT OF ENABLE
EQUIVALENT OF CLOCK
ANO RESET INPUTS
INPUT
EQUIVALENT OF ANALOG
INPUT
VCC1--------~--
;--(-,.~
J----l
C
75kn
I»
.....
I»
l>
C')
INPUT
.Q
C
iii"
0"
;::;."
:::J
(')
::;"
OUTPUT
2
;::;."
. . , . - - -...----VCC1
en
OUTPUT
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC1 (see Note 1) ............................................ 6.5 V
Supply voltage, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20 V
Input voltage at analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6.5 V
Input voltage at enable, clock, and reset inputs .................................. ±20 V
On-state output voltage ...................................................... 6 V
Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20 V
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2) . . . . . . .. 725 mW
Operating free-air temperature range: TL5071 ............................ - 40°C to 85 °C
TL507C ............................. -OOCto 70°C
Storage temperature range ......................................... - 65°C to 1 50°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260°C
NOTES:
2-92
1. Voltage values are with respect to network ground terminal unless otherwise noted.
2. For operation above 25°C free-air temperature, refer to Dissipation Derating Curves, Appendix A.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TL5071, TL507C
ANALOG-TO-DIGITAL CONVERTER
recommended operating conditions
MIN
NOM
MAX
Supply voltage, VCCI
3.5
5
6
V
Supply voltage, VCC2
8
15
18
V
Input voltage at analog input
0
5.5
V
±18
V
Input voltage at chip enable, clock, and reset inputs
V
2
High·level input voltage, VIH, reset and enable
UNIT
Low-level input voltage, VIL, reset and enable
0.8
V
On-state output voltage
5.5
V
Off-state output voltage
0
Clock frequency, fclock
125
18
V
150
kHz
II
...
II)
.
'3
u
(j
C
o
'iii
''::
electrical characteristics over recommended operating free-air temperature range,
VCC1 = VCC2 = 5 V (unless otherwise noted)
'3
C"
u
regulator section
PARAMETER
TEST CONDITIONS
VCCI
Supply voltage (output)
VCC2
ICCI
Supply current
VCCI
ICC2
Supply current
VCC2
=
=
=
=
10 to 18 V,
ICCI
Oto -1 mA
5 V,
VCC2 open
15 V,
VCCI open
MIN
TYP*
MAX
5
5.5
6
V
5
7
8
10
mA
TYP*
MAX
UNIT
(')
FUNCTION TABLE
FUNCTION TABLE
.Q
C
LOGIC INPUTS
ii'
a:o
t.
~
n
ANALOG SWITCH
B
X
S1
OFF (OPEN}
S2
ON (CLOSED}
X
L
OFF (OPEN}
ON (CLOSED}
H
H
ON (CLOSED}
OFF (OPEN}
A
ANALOG SWITCH
LOGIC INPUT
H
S1
ON (CLOSED}
S2
OFF (OPEN)
L
OFF (OPEN}
ON (CLOSED)
A
~.
c
TL607
::;'
TL610
&
(II
S~(6)S
Xl
FUNCTION TABLE
INPUTS
A ENABLE
X
L
FUNCTION TABLE
INPUTS
ANALOG SWITCH
S1
S2
B
C
X
X
S
OFF (OPEN)
OFF (OPEN}
OFF (OPEN}
L
L
H
OFF (OPEN}
ON (CLOSED}
X
L
X
OFF (OPEN)
H
H
ON (CLOSED}
OFF (OPEN}
X
X
L
OFF (OPEN)
H
H
H
ON (CLOSED}
tThese symbols are in accordance with ANSI/IEEE Std 91-1984.
TL607 logic diagram (positive logic)
-f---..,
Hr"""'~__
ENABLE.:.;;(3;.:.)-.....
2-98
ANALOG SWITCH
A
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • OALLA.~. TeXAS 75265
TL601, TL604, TL607, TL610
P-MOS ANALOG SWITCHES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee + (see Note 1) ............................................ 30 V
Supply voltage, Vee _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 30 V
Vee + to Vee _ supply voltage differential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 35 V
Control input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vee +
Switch off-state voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 30 V
Switch on-state current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10 mA
Operating free-air temperature range: TL601 M, TL604M, TL607M, TL610M . . .. - 55°C to 125°C
TL6011, TL6041, TL6071, TL6101 ......... -25°C to 85°C
TL601e, TL604e, TL607e, TL610e ......... ooe to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature (1,6 mm) 1/16 inch from case for 60 seconds: JG package ....... , .... 300°C
Lead temperature (1,6 mm) 1/16 inch from case for 10 seconds: P package. . . . . . . . . . . .. 260°C
NOTE 1: All voltage values are with respect to network ground terminal.
•
....en
..
"~
CJ
c
o
+=l
"iii
"S
aU
c(
....caca
recommended operating conditions
Vee + (see Figure 1)
Supply voltage, Vee _ (see Figure 1)
Vee + to Vee _ supply voltage differential
Supply voltage,
(see Figure 11
High·level control input voltage, YIH
Low-level control input voltage, VIL
Voltage at any analog switch (51 terminal
TL601M. TL604M
Tl601l, TL6041
Tl601C, TL604C
Tl607M, TL610M
Tl6071, TL61 01
TL607C, TL610C
MIN
NOM
MAX
MIN
NOM
MAX
MIN
NOM
5
10
25
5
10
25
5
10
25
-5
-20
-25
-5
-20
-25
-5
-20
-25
15
30
15
30
15
30
2
5.5
2
5.5
2
5.5
All inputs
0.8
VCC- +8
Switch on-state current
Operating free-air temperature, T A
VCC+
0.8
VCC- +8
10
-55
TEXAS
125
VCC+
-II
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
85
MAX
V
V
V
V
0.8
VCC- +8
10
-25
Q
UNIT
0
VCC+
V
10
mA
70
De
2-99
TL601, TL604, TL607, TL610
P·MOS ANALOG SWITCHES
•
c
!
PARAMETER MEASUREMENT INFORMATION
+10V
2.4V
OR~~OUTPUT
~~
PULSE
GENERATOR
(See Not,AI
__ J
-=
I»
.c
c
(ii'
a:
o
CL=35pF
(Sea Note BI
'="
1kO
»
n
T
RL=
1 kO
-'"
_--5V
50%
50%
~
I ------' I
OV
ton~
toff-lf---tf
OUTPUT
/90%
~O~O
INPUT
Vo = (10 VI - - -
TEST CIRCUIT
1kO+ron
NOTES: A. The pulse generator has the following characteristics:
Z~ut = 50 II, tr S 15 ns, tf S 15 ns, tw = 500 ns.
B. CL includes probe and jig cap~itance.
VOLTAGE WAVEFORMS
FIGURE 2
.::1
(')
:;'
n
TYPICAL CHARACTERISTICS
c
;::;.'
Ul
SWITCH ON·STATE RES(STANCE
1000
700
c::
I
8c
400
.j.
200
~
li,l
100
0
70
a:
c
ii
~
c
~
40
20
10
-15
,.
SWITCH ON·STATE RESISTANCE
YS
YS
FREE·AIR TEMPERATURE
SWITCH ANALOG VOLTAGE
1000
\\ I
I
I
IO(sw) .. -10 rnA
~~
c::
L.--IO(sw) = -1 rnA
7
L
700
f-+v~(SW)! _121v
400
I---Jl\sWi" _11 V
I
§
.
~
~ b....
200
T:I V
VI
Ip(sw) = -100 p.A
I
..
!i
en
70
C
9c
40
~
., -,. l.
-I---
I--- tr"
~
VCC+= 10V
VCC_=-2OV
TA =2fC
20
-10
o
-5
5
Vl(sw)-Switch Analog Voltage-V
I
I
=_SV_ ~ ~
a: 100
I-V~.~ 10-
-
~ iii....
\=_10
'sW I
°i
10
I
LVI(sw) .. 10 V
Vl(sw) =OV
VCC+" 10V
VCC_=-20V
IO(sw)= 1 rnA
FIGURE 4
TEXAS''''
INSTRUMENTS
I
--
10
-75 -50 -25
0
25 50 75 100 125
TA-Free·Air Ternperature-OC
FIGURE 3
2·100
I---
~~
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TL601, TL604, TL601, TL610
P·MOS ANALOG SWITCHES
electrical characteristics over recommended operating free·air temperature range. Vee +
Vee- ... -20 V. analog switch test current ... 1 rnA (unless otherwise noted)
Tl6 __ M
MIN TYP*
IIH
High~level
III
Low-level input current
VI - 0.4 V
loff
Switch off-state current
Vllswl - -10 V,
See Note 2
input current
VI
~
5.5 V
UNIT
MAX
MIN TYP*
0.5
10
-50 -250
MAX
10
0.5
-50 -250
-400
TA - 25°C
TA ~ MAXT
10 V.
TL6 __ C
TL6 __ 1
TEST CONOITIONSt
PARAMETER
...
-500
-50 -100
-10
-20
p.A
/LA
pA
nA
...
'5
II)
~
U
c
Tl601
ron
Vllswl
~
IOlswl
~
10V,
Tl604
-1 mA
Tl607
Tl610
Switch on-state resistance
Tl604
75
200
40
80
40
100
220
400
220
600
120
25
300
120
20
400
Tl610
Switch off-state resistance
Con Switch on-state input capacitance Vllswl - 0 V, f - 1 MHz
Coif Switch off-state input capacitance Vllswl - 0 V, f ~ 1 MHz
16
logic inputlsl
10
5
10
5
10
5
10
3
5
3
5
5
10
5
10
-1.2
-2.5
-1.2
-2.5
-2.5
-5
-2.5
-5
-0.05
-0.5
-0.05
-0.5
1.2
2.5
1.2
2.5
TYP
MAX
400
500
100
150
TL604
at 5.5 V,
Enable
All switch
terminals
input high
Enable
Input low
TL607
Tl610
Tl601
logic inputls)
Tl604
at 5.5 V,
Enable
All switch
terminals
input high
Enable
open
input low
8
5
Tl607
Tl610
o
+:
'iii
'5
c:r
u
n
The designer-selected Vee + for chosen Vee _ supply values limit the maximum input voltage that can
be applied to. either switch terminal; that is. the input voltage should be between Vee _ + 8 V and Vee +
to keep the on-state resistance within specified limits.
.
.c
c
RECOMMENDED COMBINATIONS
OF SUPPLY VOLTAGES
iii"
::+
o·::::J
30
(")
:;.
n
c
;-
25
>I
8. 20
ill
~
a.>1:1.
'1"+
(.)
(.)
15
10
>
O~--~--~
-30
-25
__
-20
~~
-15
__
~
__
-10
~
-5
VCC_-Supply Voltage-V
FIGURE 1
2-102
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
__- J
0
TLC04, TLC14
BUTTERWORTH FOURTH·ORDER LOW·PASS
SWITCHED·CAPACITOR FILTERS
PRODUCT
PREVIEW
02970. NOVEMBER. 1986
Low Clock-to-Cutoff-Frequency Ratio Error
TLC04 ... ± 0.8%
TLC14 ... ±1%
•
Filter Cutoff Frequency Dependent Only on
External-Clock Frequency Stability
•
•
ClKIN
ClKR
Minimum Filter Response Deviation Due to
External Component Variations Over Time
and Temperature
2
7
FILTER IN
VCC+
lS
3
6
AGND
VCC _
4
5
FilTER OUT
...
II)
'3
~
C3
Cutoff Frequency Range from 0.1 Hz to
20 kHz
c
o
'';:::
•
5-V to 12-V Operation
•
Self Clocking or TTL-Compatible and CMOSCompatible Clock Inputs
•
DB
D OR N PACKAGE
(TOP VIEWI
•
'in
'3
C"
u
«
ca
';
Designed to be Interchangeable with
National MF4-50 and MF4-100
C
description
The TLC04 and TLC14 are monolithic Butterworth low-pass switched-capacitor filters. Each is designed
as a low-cost, easy-to-use device and to provide accurate fourth-order low-pass filter functions in circuit
design configurations.
Each filter features cutoff frequency stability that is dependent only on the external-clock frequency. stability.
The cutoff frequency is clock tunable and has a clock-to-cutoff frequency ratio of 50: 1 with less than
± 0.8% error for the TLC04 and a clock-to-cutoff frequency ratio of 100: 1 with less than ± 1 % error for
the TLC 14. The input clock features self-clocking or TTL- or CMOS-compatible options in conjunction with
the level shift (LS) pin.
The TLC04 and TLC14 are characterized for operation from OOC to 70°C.
functional block diagram
171
Vcc+-LS (31
~
w
:>w
IX:
a..
FILTER'IN _18_1_ _ _ _ _ _ _ _--t
tO
(61
AGND----------~
141
Vcc---
::>
.....- - - - - - - '
C
oIX:
a..
PRODUCT PREVIEW .....m.nls .ontain inlarmltion
on prad.cts in tho fo,mlli.a 0' ....ign ~ha•• of
da.alopmant. Charaeta,lstl. datI ana otha,
=:~~~:=:.rrg~ dt-:i:a=::I~rT:.:~~:~:;=
prod.cts wltho.t notica.
Copyright © 1986. Texas Instruments Incorporated
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-103
TLC04,TLC14
BUTTERWORTH FOURTH·ORDER LOW·PASS
SWiTCHED·CAPACITOR FILTERS
PRODUCT
PREVIEW
pin description
PIN
NAME
NO.
1/0
DESCRIPTION
AGND
6
I
Analog Ground - The noninverting input to the operational amplifiers of the Butterworth fourth·order low-
;
ClKIN
1
I
:J>
()
ClKR
pass filter.
c
Clock In - The clock input terminal for CMOS-compatible clock or self·clocking options. For either option,
the level Shift (lS) terminal is at VCC _. For s,>If-clocking, a resistor is connected between the ClKIN and
CLKR terminal pins and a capacitor is connected from the elKIN terminal pin to ground.
2
I
Clock R - The clock input for a TTL-compatible clock. For a TTL clock, the level shift pin is connected
to mid-supply and the ClKIN pin may be left open, but it is recommended that it be connected to either
,Q
c
iii'
:=;.'
0'
FilTER IN
8
I
FilTER OUT
5
3
0
lS
:::s
I
VCC+ or VCC-.
Filter Input
Butterworth fourth-order low-pass Filter Output
level Shift - This terminal accommodates the various input clocking options. For CMOS-compatible clocks
or self-clocking, the level-shift terminal is at VCC _ and for TTL-compatible clocks, the level·shift terminal
(')
is at mid-supply.
~r
c
a
VCC+
7
I
Positive supply voltage terminal
VCC-
4
I
Negative supply voltage terminal
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee ± (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 7 V
Operating free-air temperature range ......................................
to 70°C
Storage temperature range ......................................... -65°C to 1.50 o e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260°C
ooe
NOTE 1; All voltage values are with respect to the AGND terminal.
recommended operating conditions
TlC04
::0
o
C
MIN
MAX
2.5
6
-6
2.5
-2.5
6
-6
VCC+
VCC-
Negative supply voltage
-2.5
VIH
High-level input voltage
2
Vil
low-level input voltage
fco
TA
."
MAX
Positive supply voltage
fclock
TLC14
MIN
2
0.8
UNIT
V
V
V
0.8
V
5
lxl0 6
10
lxl0 6
Hz
Cutoff frequency (see Note 3)
0.1
20xl0 3
0.1
10xl03
Operating free-air temperature
0
70
0
70
Hz
DC
. Clock frequency (see Note 2)
NOTES; 2. Above 250 kHz, the input clock duty cycle should be at 50% to allow the operational amplifiers the maximum time to settle
while processing analog samples.
3. The cutoff frequency is defined as the frequency where the response is 3.01 dB less' than the dc gain of the filter.
c:
n
-I
."
::0
-~
~
2-104
TEXAS ..,
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
TLC04, TLC14
BUTTERWORTH FOURTH-ORDER LOW-PASS
SWITCHED-CAPACITOR FILTERS
PRODUCT
PREVIEW
electrical characteristics over recommended operating free-air temperature range, Vee +
Vee - ... - 2.5 V, fclock :S 250 kHz (unless otherwise noted)
- 2.5 V,
•
filter section
PARAMETER
VOO
Output voltage offset
VOM
Peak output voltages
lOS
Short-circuit output current
ICC
Supply current
TEST CONDITIONS
MIN
TLC04
Typt
MAX
MIN
-150
~
RL = 5 kll
VOMSource
2
2.3
-1
-1.5
See Note 4
28
fclock = 250 kHz
1.5
MAX
-300
2
-1
-0.5
TA = 25°C,
Sink
TLC14
TYpt
2.3
..
u
(3
V
-1.5
c:
o
mA
28
1.5
III
·S
mV
-0.5
2.25
...
UNIT
2.25
~
mA
·iii
NOTE 4: lOS (source current) is measured by forcing the output to its maximum positive voltage and then shorting the output to the negative
supply (VCC _) terminal. lOS (sink current) is measured by forcing the output to its maximum negative voltage and then shorting
the output to the positive supply (VCC +) terminal.
operating characteristics over recommended operating free-air temperature range, Vee +
Vee- .. -2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Clock-to-cutoff-frequency ratio
(fclockifco)
Temperature coefficient of
clock-to-cutoff frequency ratio
fclock "'. 250 kHz,
TA = 25°C
fclock '" 250 kHz
fco = 5 kHz,
f = 6 kHz
TLC04
Typt
MAX
MIN
49.27
50.07
50.87
99
100
101
-25
0
25
-25
0
25
MIN
TLC14
Typt
MAX
Dynamic range (see Note 6)
Stop-band frequency
attentuation at 2 f co
DC voltage amplification
Peak-to-peak clock
feedthrough voltage
UNIT
ppm/DC
-1.7 -1.46 -1.22
f = 3 kHz
-7.92 -7.42 -6.92
f = 2.25 kHz
-1.77 -1.51 -1.25
dB
TA = 25°C
80
24
f clock :s 250 kHz
fclock '" 250 kHz,
!9
CIS
c
dB
f = 4.5 kHz
fclk = 250 kHz,
TA = 25°C
V,
CO
u
w
a:
c..
I-
(,)
;:)
C
oa:
c..
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-105
TLC04, TLC 14
BUTTERWORTH FOURTH·ORDER LOW·PASS
SWITCHED·CAPACITOR FILTERS
•
PRODUCT
PREVIEW
electrical characteristics over recommended operating free-air temperature range,
= - 5 V, fclock :S 250 kHz, (unless otherwise noted)
Vee -
vee + -
5 V,
filter section
PARAMETER
C
...
III
III
TEST CONDITIONS
MIN
VOO Output voltage offset
»
YOM Peak output voltages
.Q
lOS
Short~circuit
lee
Supply current
(')
c
iii"
::+
output current
I VOM+
VOMSource
Rl = 5 kD
~
4
-4
TlC04
Typt ,MAX
-200
4.5
-4.1
MIN
4
-4
-1.5
TA = 25°e.
See Note 4
50
2.5
fclock = 250 kHz
TLC14
Typt MAX
-400
4.5
-4.1
-1.5
50
2.5
3.5
3.5
UNIT
mV
V
mA
mA
cr
NOTE 4: lOS (source currentl is measured by forcing the output to its maximum positive voltage and then shorting the output to the negative
n
supply (Vee _) terminal. lOS (sink current) is measured by forcing the output to its maximum negative voltage and then shorting
the output to the positive supply (Vee +) terminal.
::::I
=:;'
2
clocking section
::+
PARAMETER
In
TEST CONDITIONS*
Vee = 10 V
VT+ Positive-going input threshold voltage
VT- Negative-going input threshold voltage elKIN
Vhys Hysteresis (VT + - VT _ )
low-level output voltage
Input leakage current
Output current
Output current
Vee = 5 V
Vee=10V
Vee = 5 V
VOH High-level output voltage
VOL
Vee = 5 V
Vee - 10 V
elKR
Typt
6.1
3.1
1.3
0.6
7
3.5
2.3
4
3.8
1.9
7.6
1.2
2
3.8
3
1.5
MAX
8.9
4.4
9
4.5
UNIT
V
V
V
Vee=10V
10 = -10 ~A
Vee = 5 V
Vee- 1OV
10 = 10~
Vee = 5 V
Vce = 10V level Shift pin at mid-supply.
Vee - 5 V TA = 25°e
Vee = 10 V
elKR shorted to VeeVee = 5 V
-3
0.75
-6
-1.5
mA
Vee - 10 V
elKR shorted to Vee +
Vee = 5 V
2.5
0.65
5
1.3
mA
t All typical values are at T A = 25 De.
*Vee = Vee+ - Vee-·
"tJ
::xl
o
C
c:
(")
-f
"tJ
~
m
S
m
:e
2-106
,MIN
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
V
1
0.5
2
2
V
~A
TLC04. TLC14
PRODUCT
PREVIEW
BUTTERWORTH FOURTH·ORDER LOW·PASS
SWITCHED·CAPACITOR FILTERS
operating characteristics over recommended operating free-air temperature range.
VCC - - - 5 V (unless otherwise noted)
PARAMETER
Clock·to-cutoff-frequency ratio
(fclock/fco)
Temperature coefficient of
clock-ta-cutoff frequency ratio
TEST CONDITIONS
fclock
s
250 kHz.
Frequency response above and below
= 5 kHz.
fclk = 250 kHz.
TA = 25°C
cutoff frequency (see Note 5)
fco - 2.5 kHz.
fclk
TA
Stop-band frequency
attentuation at 2 feo
=
25°C
TA
= 250 kHz,
= 25°C
= 25°C
f
=
f
= 4.5
6 kHz
fclock S 250 kHz.
Peak-to-peak clock
feedthrough voltage
TA
=
49.58 49.98
50.38
0
15
-7.84 -7.57
-7.3
MIN
99
-15
TLC14
Typt
MAX
100
0
UNIT
...
101
15
(I)
ppm/DC
CJ
c:
o
-1.56 -1.44 -1.32
f
=
3 kHz
-7.67 -7.42 -7.17
f
=
2.25 kHz
-1.64 -1.51 -1.38
"+=
"iii
d8
80
RS S 2 k!l
.
"S
C3
d8
kHz
fclock S 250 kHz
DC voltage amplification
TLC04
Typt
MAX
-15
f clock S 250 kHz
fco
Dynamic range (see Note 7)
TA
MIN
Vcc+ - 5 V.
d8
dB
24
25
24
25
-0.15
0
0.15 -0.15
0
25
25·C
25
0.15
"S
C"
78
CJ
<
...asas
dB
Q
mV
t All typical values are at T A = 25 ·C.
NOTES: 5. The frequency responses at f are referenced to a dc gain of 0 dB.
7. The dynamic range is referenced to 2.82 V rms (4 V peak) where the wideband noise over a 20-kHz bandwidth is typically
282 ",V rms for the TLC04 and 355 ",V rms for the TLC14.
~
w
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a:
c..
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oa:
c..
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-107
TLC04, TLC14
BUTTERWORTH FOURTH·ORDER LOW·PASS
SWITCHED·CAPACITOR FILTERS
PRODUCT
PREVIEW
TYPICAL APPLICATION DATA
5V-------------------------,
bl -
TLC04/TLC14
r - - - - - -VCC+
...C
ill-
III
III
CMOS
l>
CLKIN
n
LEVEL
-
-
--,
(31hS
I
I
V
+_5_
I
I
I
I
I
I
I
-t__...;(...;11;.:.I.::.CL:::.K.::.:IN.:...;
- 5 V
.Q
I
(21 CLKR
=:..:.._ _ _ _----J
-=~I
r:
iii'
;::;.'
I
::::I
I
I
0'
(")
:::;'
(sil FILTER
n
r:
I
IN
(6)1 AGND
;::;.'
FILTER (5)
I
L ______
1/1
OUT
~CC-
________
I
...J
(41
-5V---.--------------------~
FIGURE 1. CMOS·CLOCK·DRIVEN, DUAL·SUPPLY OPERATION
5V-----.~
________________- ,
(71
---
VCC+
TLC04/TLC14
- - - - - --"""1
I
I
~~~----------.---~
I
I
I
I
TTLill-5V
CLKR
- - - - - - ' - ; . . . . . , . - - - - - - - - - - - - - - -......
OV
I
I
I
."
:ll
(sil
FILTER IN
FILTER 1(51
o
(61I A GND
I
C
C
L
n
-I
LOW·PASS FILTER
VCC-
FIGURE 2. TTL·CLOCK·DRIVEN, DUAL·SUPPLY OPERATION
m
~
m
~
2·108
I
--- - -- J41 -- -- --- J
-5V
."
:ll
OUT
TEXAS . . ,
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TLC04. TLC14
BUTTERWORTH FOURTH-ORDER LOW-PASS
SWITCHED-CAPACITOR FILTERS
PRODUCT
PREVIEW
TYPICAL APPLICATION DATA
5v------------------------~
r----
1(71
TLC04ITLC14
--~----VCC+
LEVEL
(311 LS
---.,1
I
SHIFT
I
I
I
I
I
I
I
I
I
(811 FILTER IN
FILTER
INPUT
FILTER I (51
(61IAGND
':"' I
OUT
I
L ______vcc-_ _ _ _ _ _ _ _ .J
--------------------J
...
U)
..
-3
u
C3
c
o
';:
'iii
'3
eu
c(
~
Q
(41
_5V ____
1
fclock - -=RC=-x:-In-;~1''7(y:-;-C-C---V:-;-T--')~(r:'V;-T'+)~~
~ VCC - VT+
VT-
'J
For VCC - 10 V.
fclock -
1
'i:69Rc
FIGURE 3. SELF-CLOCKING THROUGH SCHMITT TRIGGER OSCILLATOR. DUAL-SUPPLY OPERATION
~
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a:
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....
o
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C
oa:
a..
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS, TEXAS 75265
2-109
TLC04, TLC14
BUTTERWORTH FOURTH·ORDER LOW·PASS
SWITCHED·CAPACITOR FILTERS
PRODUCT
PREVIEW
TYPICAL APPLICATION DATA
+10V--------~--------------------~
r - - - ---
o
S
(3)
(7)
VCC+ -
I lS
TlC04/TlC14
-~E~ ~---,
SHIFT
I»
- + 10 V
~
»
n
CMOS
ClKIN
.c
c
(SEE NOTE A)
i·
I1lIClKIN
--+-----~~~~~~r~o---~
I
I
oV
I
TTQf[.---5V
a:o
(2)
IClKR
ClKR
:::I
OV
n
10 kll
~.
(B) I FilTER IN
FilTER IN ~5 VOC --+-------I----!:~.:::.:.:::.!..:::....--------------~
(SEE NOTE B)
(6) I AGND
c
;::;:
til
FilTER
OUT
IL ______VCC-_ _ _ _ _ _ _ _ ..J
10 kll
(4)
(SEE NOTE C)
NOTES: A. The external clock used must be of CMOS level because the clock is input to a CMOS Schmitt trigger.
B. The Filter input signal should be dc-biased to mid-supply or ac-coupled to the terminal.
C. The AGND terminal must be biased to mid-supply.
FIGURE 4. EXTERNAL-CLOCK-DRIVEN SINGLE-SUPPLY OPERATION
2-110
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265
(5)
TLC04, TLC 14
BUTTERWORTH FOURTH·ORDER LOW·PASS
SWITCHED·CAPACITOR FILTERS
PRODUCT
PREVIEW
TYPICAL APPLICATION DATA
•
+10V------------~------------------------..,
r- - -- - ---
(7)
VCC+ -
-
-
-
-
-
-
-
.,
~
.
"5
(3)
lS
(1)
ClKIN
(2)
ClKR
(8)
FilTER IN
Co)
u
c
o
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cr
Co)
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D.
TEXAS . "
INSTRUMENTS
j:'OST c;)FFICE BOX 655012 • DALLAS. T~XAS 75265
2-111
TLC04, TLC14
PRODUCT
PREVIEW
BUTTERWORTH FOURTH·ORDER LOW·PASS
SWITCHED·CAPACITOR FILTERS
TYPICAL APPLICATION DATA
•
5V--~----------------------------~
r - - - - ----vcc+---------,
(7)
I
131
I
LS
I
I
-+----1____.....:.;.11:...1.;-C;;,:L::.,;KI::.:,N__-I
CLOCK __
INPUT
121
I
I
CLKR
I
I
I
I
181
161
10kn~-+--.
I
FILTER
OUT 1151
FILTER IN
l
I AGND
L _________
~~
~1#
________
~
-5V--~~~~----------------------~
FIGURE 6. DC OFFSET ADJUSTMENT
-a
::IJ
oC
c:
n
~
-a
::IJ
m
S
m
~
2-112
TEXAS . "
INSlRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
~
PRODUCT
PREVIEW
TLC0820A. TLC0820B
ADVANCED LinCMOS™ HIGH·SPEED 8·BIT ANALOG·TO·DlGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIQUES
02873, SEPTEMBER 1986- REVISED OCTOBER 1986
•
Advanced LinCMOS" Silicon-Gate
Technology
•
8-Bit Resolution
•
Differential Reference Inputs
•
Parallel Microprocessor Interface
•
Conversion Time
Write-Read Mode, , . 0.9 ,.s and 1.1 ,.s
Read Mode ..• 2.5 ,.s Max
•
No External Clock or Oscillator Components
Required
•
On-Chip Track-and-Hold
•
Low Power Consumption ... 50 mW Typ
•
Single 5-V Supply
•
TLC0820B is Direct Replacement for
National Semiconductor ADC0820BIBC and
Analog Devices AD7820LICIU;
TLC0820A is Direct Replacement for
National Semiconductor ADC0820CICC and
Analog Devices AD7820KIBIT
TLC0820AM. TLC08208M ... J OR N PACKAGE
TLC0820AI. TLC082081 ..• N PACKAGE
TLC0820AC. TLC08208C ... N PACKAGE
(TOP VIEW)
ANlGIN
(lSB) DO
D1
D2
D3
WR/RDY
MODE
RD
Vee
Ne
OFlW
D7 (MSB)
D6
D5
D4
es
REF+
REF-
GND
....
II)
·S
.
u
(3
C
o
•.;::l
·iii
·S
CI"
U
TLC0820AM. TLC0820BM ... FK PACKAGE
TLC0820AI. TlC0820BI ... FN PACKAGE
TLC0820AC. TLC0820BC ... FN PACKAGE
c:(
(TOP VIEW)
Q
ca
-;
a;~
~C!)
-...J
~
0
2
U
UU
OO<{>2
3
D2
D3
WR/RDY
MODE
RD
2 1 20 19
18
17
16
15
4
5
6
7
8
14
9 10 11 12 13
NC- No internal connection
description
The TLC0820A and TlC0820B are Advanced LinCMOS'" 8-bit analog-to-digital converters each consisting
of two 4-bit "flash" converters. a 4-bit digital-to-analog converter. a summing (error) amplifier. control
logic. and a result latch circuit. The modified "flash" technique allows low-power integrated circuitry to
complete an 8-bit conversion in 1.4 microseconds. The on-chip track-and-hold circuit has a 100-nanosecond
sample window and allows the TLC0820A and TLC0820B to convert continuous analog signals having
slew rates of up to 100 millivolts per microsecond without external sampling components. TTL-compatible
three-state output drivers and two modes of operation allow interfacing to a variety of microprocessors.
Detailed information on interfacing to most popular microprocessors is readily available from the factory.
The TLC0820AM and TLC0820BM are available in both the N plastic and the J ceramic packages and
are characterized for operation over the full military temperature range of - 55°C to 125°C. The TLC0820AI
and TlC0820BI are characterized for operation from - 40°C to 85 DC. The TLC0820AC and TlC0820BC
are characterized for operation from O°C to 70°C.
Advanced LinCMOS is a trademark of Texas Instruments.
development. Characteristic data anil othar
products without noli...
5>
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a:
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(.)
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oa:
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Copyright © 1986, Texas Instruments Incorporated
PRODUCT PREVIEW do.umonts .ontain information
on products in tho formati.. or design pha.. of
~::~~:~=:.rr::t d:'Si.!Ca=:I~rT3i!::~~:~:~::'
~
w
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-113
TLC0820A. TLC0820B
ADVANCED LinCMOS"" HIGH·SPEED 8·BIT ANALOG·TO·DIGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIQUES
PRODUCT
PREVIEW
functional block diagram
REF +
REF-
4-BIT FLASH
ANALOG-TODIGITAL
CONVERTER
(4 MSBs)
(12)
(11)
..»
C
4
4
r-J-!!!. OFLW
~ DO (LSB)
rill D1
4
I»
I»
n
~
.c
c
.-
4-BIT
DIGITALTO-ANALOG
CONVERTER
t--
iii"
OUTPUT
LATCH
AND
3-STATE
BUFFERS
::::I
n
:::;'
n
c
;::;.'
' - - -1
ANLG IN
11}
+1
t
'--
4-BIT FLASH
ANALOG-TODIGITAL
CONVERTER
14 LSBs}
WR/RDY
CI
RD
(7)
16}
n
TIMING
AND
CONTROL
113}
IS}
'"C
::D
o
C
c:
(')
-I
'"C
::D
m
S
m
:e
2-114
~ D4
-112L 07 (MSB)
4
III
MODE
02
~ D3
-1ill. 05
-1!!.L D6
::+
0'
~
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75266
~
DIGITAL
OUTPUTS
PRODUCT
PREVIEW
TLC0820A, TLC0820B
ADVANCED LinCMOS™ HIGH·SPEED 8·BIT ANALOG·TO·DIGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIOUES
PIN
NAME
ANLG IN
cs
1
13
Analog input
This input must be low in order for RD or WR to be recognized by the ADC.
DO
2
Three-state data output, bit 1 ILSBI
D1
3
Three-state data output, bit 2
D2
4
Three-state data output, bit 3
D3
5
Three-state data output, bit 4
D4
14
Three-state data output, bit 5
D5
15
Three-state data output, bit 6
D6
16
Three-state data output, bit 7
Three-state data output, bit 8 IMSBI
D7
17
GND
10
INT
9
•
DESCRIPTION
NUMBER
!!
"5
.
C3
u
c
o
·iii
-.;::=
"5
Ground
tdlintl' is complete and the data result is in the output latch. tdlintl is typically 800 ns starting after the rising
edge of the WR input Isee operating characteristics and Figure 3). If RD goes low prior to the end of tdlint),
INT goes low at the end of tdRIL and the conversion results are available sooner (see Figure 2). INT is reset by the
rising edge of either RD or
MODE
7
C"
u
In the WRITE-READ mode, the interrupt output, INT, going low indicates that the internal count:down delay time,
CS.
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TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-115
TLC0820A, TLC0820B
ADVANCED LinCMOSTM HIGH·SPEED 8·BIT ANALOG·TO·DIGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIQUES
•
c
!DI
»
n
.Q
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
Input voltage range, all inputs (see Note 1)
Output voltage range, all outputs (see Note 1)
Operating free-air temperature range
Storage temperature range
Case temperature for 60 seconds: FK package
::+"
Case temperature for 10 seconds: FN package
Lead temperature 1,6 mm (1/16 inch) from case
for 60 seconds: J package
Lead temperature 1,6 mm (1/16 inch) from case
for 10 seconds: N package
o·
~
n
~.
c
::+"
TLC0820AM
TLC0820AI
TLC0820AC
TLC08208M
10
-0.2 to
TLC0820BI
10
-0.2 to
TLC0820BC
10
-0.2 to
VCC+ O.2
~0.2 to
VCC+ 0 .2
-0.2 to
VCC+ 0 .2
-0.2 to
VCC+0.2
-55 to 125
VCC+ 0 .2
-40 to 85
VCC+ 0 .2
to 70
65 to 150
C
iii'
PRODUCT
PREVIEW
65 to 150
260
260
V
V
V
o
65 to 150
UNIT
260
·C
·C
·C
·C
300
·C
260
260
·C
260
NOTE 1: All voltages are with respect to network ground terminal, pin 10:
en
recommended operating conditions
TLC0820AM
TLC0820BM
MIN NOM MAX
Supply voltage, VCC
4.5
Analog input voltage
-0.1
Positive reference voltage, VREF +
VREFGND
Negative reference voltage, VREFHigh-level input VCC = 4.75 V CS, WR/RDY, RD
to 5.25 V
MODE
voltage, VIH
Low-level input VCC = 4.75 V CS, WR/RDY, RD
to 5.25 V
MODE
tdWR (see Figures 2 and 3)
Write-pulse duration in write-read mode, tww
(see Figures 2, 3, and 4)
Operating free-air temperature. T A
8
VCC+ O.1
TLC0820BI
MIN NOM MAX
4.5
5
8
-0.1
Vee
VREFVREF+ GND
VCC+O.l
-0.1
NOM
5
UNIT
MAX
8
VCC+O.l
Vee
VREF+
2
3.5
0.8
1.5
1.5
0.6
0.6
MIN
4.5
VREFVREF+ GND
3.5
0.8
TLCOB20AC
TLC0820BC
Vee
2
2
3.5
voltage, VIL
Delay time from WR to RD in write-read mode,
5
TLC0820AI
V
V
V
V
V
0.8
1.5
0.6
V
~s
0.6
50
0.6
50
0.6
50
~s
-55
125
-40
85
0
70
·C
""C
:rI
o
C
c:
(")
-I
""C
:rI
m
S
m
:e
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
PRODUCT
PREVIEW
TLC0820A, TLC0820B
ADVANCED LinCMOSTM HIGH·SPEED 8·BIT ANALOG·TO·DIGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIQUES
electrical characteristics over recommended operating free-air temperature range,
(unless otherwise noted)
PARAMETER
VOH High-level output voltage
VOL
Low-level output voltage
TEST CONDITIONS
VCC
or OFLW
VCC - 4.75 V,
Any D, OFLW,
iNT,
or WR/RDY
CS or
IIH
High~level
input current
= 4.75
Any D, INT,
=
VCC
V,
5.25 V,
IOH
= - 36O I'A
IOH IOL
=
-10p.A
MIN
10Z
II
Low-level input current
CS, WR/RDY,
VIL
=
0.4
=0
Off-state (high-impedance
Any 0 or
Vo - 5 V
WR/RDY
Va - 0
Short-circuit output current
iNT,
or WRiRDY
Rref
Reference resistance
ICC
Supply current
Ci
Input capacitance
Co
Output capacitance
V
.t::
..
U
::I
CS at 5 V,
V(
CS at
5 V,
VI
=
5 V,
TA
Va
0.1
3
50
200
-0.005
-1
I'A
0.1
-0.1
3
-3
p.A
=5V
=0
=
25·C
1
3
-3
7
I'A
c
o
E
en
"3
8'
or(
I'A
as
;
Q
14
mA
Any D or OFLW
INT
en
1.6 mA
5 V
state) output current
Analog input current
UNIT
Co)
VIH
RD, or MODE
V
V
0.005
WR/RDY
MAX
4.5
RD
Any D, OFLW,
lOS
Typt
5
2.4
MODE
IlL
Vee -
Va
= 0,
TA
=
25·C
CS, WR/RDY, and RD at 0 V
Any digital
-6
-12
-4.5
-9
1.25
2.3
6
kll
7.5
15
mA
5
Analog (pin 1)
pF
45
Any digital
5
pF
t All typical values are at T A = 25 ·C.
~
W
:;:
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a:
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(.)
:::>
c
oa:
D..
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2-117
TLC0820A, TLC0820B
ADVANCED LinCMOSTM HIGH·SPEED 8·BIT ANALOG·TO·DIGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIQUES
PRODUCT
PREVIEW
operating characteristics, Vee - 5 V, VREF+ - 5 V, VREF- - 0, tr - tf - 20 ns, TA - 25°e
(unless otherwise noted)
PARAMETER
Supply voltage
kSVS
VCC
sensitivity
=
MIN
5 V ± 5%
TYP
MAX
±1/16
±1/4
Total unadjusted error T MODE pin at 0 V
tconvR
Read mode
conversion time
Internal count~
MODE pin at 0 V, See Figure ·1
taR
Access time from Ro~
MODE pin at 0 V, See Figure 1
taRl
Access time from
taR2
Access time from RO~
taiNT
Access time from
tdis
Disable time from ROt
Delay time from
tdRDY
tdRIH
~Rll
~WIH
~(NC)
CS~
to RDY~
Delay time from
ROt to INn
Delay time from
RD~
to INn
Delay time from
WRt to INn
Delay to next
conversion
Cl
=
down delay time
RD~
50 pF,
MODE pin at 5 V,
Cl
=
15 pF
tdWR < td(int)'
See Figure 2
Cl
=
100 pF
MODE pin at 5 V,
Cl
=
tdWR > td(int)
See Figure 3
Cl
=
±1/16
±1/4
lSB
1/2
lSB
1.6
2.5
1.6
2.5
/,S
800
1300
800
1300
ns
tconvR
+20
190
tconvR
+50
280
tconvR tconvR
+20
+50
190
280
210
320
15 pF
70
120
70
120
100 pF
90
150
90
150
Cl = 50 pF,
See Figures 1, 2, and 3
MODE pin at 5 V,
tdWR < td(intl'
See Figure 2
MODE pin at 5 V,
Cl = 50 pF,
See Figure 4
ns
ns
20
50
20
50
ns
95
70
95
ns
50
100
50
100
ns
125
225
125
225
ns
200
290
200
290
ns
175
270
175
270
ns
500
ns
500
0.1
Slew rate tracking
ns
70
See Figures 1, 2, 3, and 4
tTotal unadjusted error includes offset, full-scale, and linearity errors.
'"0
:D
o
C
c:
o
-t
'"0
:D
m
S
m
=E
TEXAS ."
INSTRUMENTS
post
MAX
320
Rl - 1 kll,
Cl - 10 pF,
See Figures 1, 2, 3, and 5
MODE pin at 0 V,
Cl = 50 pF,
See Figure 1
UNIT
TYP
210
Tiii'f. MODE pin at 5 V, See Figure 4
2-118
MIN
1
MODE pin at 5 V"
Sea Figures 3 and 4
~(int)
TLC08208
TLC0820A
TEST CONDITIONS
OFi=!ICS; BOX 666012 • DALLAS. TEXAS 75265
0.1
VI".
PRODUCT
PREVIEW
TLC0820A, TLC0820B
ADVANCED LinCMOSTM HIGH·SPEED 8·BIT ANALOG·TO·DIGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIQUES
PARAMETER MEASUREMENT INFORMATION
B~~__________-J/
",.... ---\--
f
' - -_ _----..J
j.-td(NCI---I
1
WR/ROY
WITH
---t
~XTERNAL PULL-UP
r,:
I
~
1
.
-II....--~I
------r-------{
I }--------
j.--taR----I
-.j "j.-tdiS
FIGURE 1. READ MODE WAVEFORMS (MODE PIN LOW)
____ _
tww~ .__---_.._-..-~
,l
B:)
WR/ROY
~~_~L
""___
tdWR
~
tdRIL-.I....
INT
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td(int)l
CSLOW----------------
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WR/ROY
0..
1--=-J'
INT _ _ _
j4-td (intl
I-
-=ll
00-07 ---..:.....)
CJ
\.-taiNT
(
~:[.~
)-
FIGURE 4. WRITE-READ MODE WAVEFORMS
(STAND-ALONE OPERATION. MODE PIN HIGH. AND RD LOW)
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
:::>
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0..
2-119
TLC0820A. TLC0820B
ADVANCED linCMOSTM HIGH·SPEED 8·BIT ANALOG·TO·DIGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIQUES
PRODUCT
PREVIEW
PARAMETER MEASUREMENT INFORMATION
II
..
C
III
III
Vcc
CL - 10 pF
TLC0820
INPUT
~t'J4-
1m
RO
DATA
OUTPUT
On
CS
VCC--~~~
)!.
--+I
CL
~
~
1 kG
VOH
DATA
c
OUTPUTS
iir
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O·
':"
n
::;"
VCC
110 %
GNO
GNO
tdl. I+-
I
~O%
""'--
GNO----------~:
t,-20ns
:::s
CL - 10 pF
~
c
::r
en
TLC0820
"""
1 kG
INPUT
-+tt'!4VCC~-..l...1
I
90%
I
nu
RO
DATA
OUTPUT
On
CS
GNO
50%
110%
I
-+ttdi.14I
DATA
: ..""..-OUTPUTS VOL - - - - ¥ 1 0 %
VCC
GNO
CL
t,-20n.
On-DO .•. 07
TEST CIRCUIT
VOLTAGE WAVEFORMS
FIGURE 5. TEST CIRCUIT AND VOLTAGE WAVEFORMS
."
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2-120
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 15265
PRODUCT
PREVIEW
TLC0820A, TLC0820B
ADVANCED LinCMOSTM HIGH·SPEED 8·BIT ANALOG·TO·DIGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIQUES
PRINCIPLES OF OPERATION
The TLC0820A and TLC0820B each employ a combination of "sampled-data" comparator techniques and
"flash" techniques common to many high-speed converters. Two 4-bit "flash" analog-to-digital conversions
are used to give a full 8-bit output.
The recommended analog input voltage range for conversion is -0.1 V to VCC +0.1 V. Analog input signals
that are less than VREF _ + Y, LSB or greater than VREF + - Y2 LSB convert to 00000000 or 11111111
respectively. The reference inputs are fully differential with common-mode limits defined by the supply rails.
The reference input values define the full-scale range of the analog input. This allows the gain of the ADC to
be varied for ratio metric conversion by changing the VREF + and VREF _ voltages.
The device operates in two modes, read (only) and write-read, which are selected by the MODE pin (pin 7).
The converter is set to the read (only) mode when pin 7 is low. In the read mode, the WR/RDY pin is used
as an output and is referred to as the "ready" pin. In this mode, a low on the "ready" pin while CS is low
indicates that the device is busy. Conversion starts on the falling edge of RD and is completed no more than
2.5 microseconds later when INT falls and the "ready" pin returns to a high-impedance state. Data outputs
also change from high-impedance to active states at this time. After the data is read, RD is taken high, INT
returns high, and the data outputs return to their high-impedance states.
The converter is set to the write-read mode when pin 7 is high and WR/RDY is referred to as the "write" pin.
Taking CS and the "write" pin low selects the converter and initiates measurement of the input signal.
Approximately 600 nanoseconds after the "write" pin returns high, the conversion is completed. Conversion
starts on the riSing edge of WR/RDY in the write-read mode.
•
!!
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The high-order 4-bit "flash" ADC measures the input by means of 16 comparators operating simultaneously.
A high precision 4-bit DAC then generates a discrete analog voltage from the result of that conversion. After
a time delay, a second bank of comparators does a low-order conversion on the analog difference between
the input level and the high-order DAC output. The results from each of these conversions enter an 8-bit latch
and are output to the three-state buffers on the falling edge of RD.
~
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TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-121
TLC0820A. TLC0820B
ADVANCED LinCMOS"" HIGH-SPEED 8"BIT ANALOG-TO.-DIGITAL
CONVERTERS USING MODIFIED "FLASH" TECHNIQUES
PRODUCT
PREVIEW
TYPICAL APPLICATION DATA
~es
(13)
Wi!
c
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(2)
01
(31
p.P
02
(4)
BUS
03
(5)
04
(14)
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00
-'2
;,
(")
::;"
05
(15)
c
06
(16)
a
07
(17)
(18)
(6)
~
(2)
(3)
(4)
(5)
(14)
(15)
(16)
(17)
(18)
c:
(')
01
(7)
MOOE f - - 5 V
REF+
(12)
03
REF-
(11)
fo.
06
07
(10)
OFLW
GNO
es
~
"*
(20)
Vee - 5 V
(1)
WR/ROY ANLG
IN
RO
(7)
00
01
t
MOOE - 5 V
REF+
(12)
02
03
05
REF-
(11)
06
":"
07
OFLW
::D
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=:
2-122
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
"':"
(10) :;:: ;::;:0.1Il
GNO
----.
":'
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u
04
FIGURE 6. CONFIGURATION FOR 9-BIT RESOLUTION
-I
5V
fO
02
I~~
(13)
C
00
08
'"\.
o
RO
05
OFL
::D
ANLGIN
04
n
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(20)
Vee f--5V
(1)
WR/ROY ANLG
IN
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II)
es
(6)
F
•
TLC10, TLC20
UNIVERSAL DUAL SWITCHED-CAPACITOR FILTER
ADVANCE
INFORMATION
D2952, AUGUST 1986-REVISED SEPTEMBER 1986
•
N DUAL-IN-LiNE PACKAGE
Maximum Clock to Center-Frequency Ratio
Error
TLC10, .. ±O.S%
TLC20, .. ±1,5%
(TOP VIEW)
1LP
1BP
1NAH
11N1APIN
SW
2LP
2BP
2NAH
21N2APIN
AGNO
Critical-Frequency Times Q Factor Range Up
to 200 kHz
VCC+
VOO+
LS
1CLK
VCCVOOCF/CL
2CLK
•
Critical-Frequency Operation Up to 30 kHz
FN CHIP CARRIER PACKAGE
•
Designed to be Interchangeable with:
National MF10
Maxim MF10
Linear Technology LTC 1 OSO
•
•
•
Filter Cutoff Frequency Stability Dependent
Only on External-Clock Frequency Stability
Minimum Filter Response Deviation Due to
.External Component Variations over Time
and Temperature
II
...
II)
-S
...CJ
(3
c:
o
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-iii
-S
C"
CJ
(TOP VIEW)
-<
...asas
J:
C
c
--'-----------+-+-----~-~f--NOTCHOUT
rlH------"B..;..P71-1~+- BAND-PASS OUT
I
I
lPI
H'-~+-+-
I
IR3
SW
VDD+
lOW-PASS OUT
R2
I
I
I
I
..J
L
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o
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«
2-127
TLC10,TLC20
UNIVERSAL DUAL SWITCHED·CAPACITOR FILTER
ADVANCE
INFORMATION
TYPICAL APPLICATION DATA
!clock
-- --,
% TLC10 TLC20
r--
..c
I
II)
.c
c
I
-4--
(ii'
I
~
I
I
>-...._________-+-+-_ _ _NAH
;;;.;;;.;...:-_+_NONINVERTING
I
...
II
::+"
o·
::I
~'
NONOVERLAPPING
I CLOCK GENERATOR ~
IN....
I AGND ,-........
r---:--
I_
c
I ,-_'-
Ul
VDD+~
....- t - BAND-PASS OUT (BP1)
.-+-+-----=~I
""'ji>
APIN
VI--i......:..:.:....::;+--+------i-
::+"
BAND-PASS 'OUT (BP2)
Ir~
IL I ___
---- _
I
'- 'J1>
lPI
'--- +
-
-
H""';-I-+-t- lOW-PASS OUT
I
R3
R2
I
_ _ _ _ _ _ _ .JI
fa = fclock/l00 or !clock/50
0= R3/R2
HOlP = - 1
HOlP (peak) = a x HOlP (for high as)
HOBPl = -R3/R2
HOBP2 = 1 (noninverting)
Circuit dynamics:
HOBPl =
a
FIGURE 2. MODE 18 FOR NON INVERTING BAND-PASS AND LOW-PASS OUTPUTS
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nm
-
:2
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2-128
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
ADVANCE
INFORMATION
TLC10,TLC20
UNIVERSAL DUAL SWITCHED·CAPACITOR FILTER
TYPICAL APPLICATION DATA
fclock
I
VI
R1
IAGND
~I
APIN
'h TLC 1 0 TlC20
I~
IClK
IIN_
NONOVERlAPPING
I CLOCK GENERATOR
...
r'"
...+ /
~
'5
I
I
BPi
I
I
7t>
-
"""t'i>
+
I
-
-
VDD+~
I----
+
:I~
= Inotch x yR2/R4
= Iclock/100 or
L-
r--n>
c
o
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BAND·PASS OUT
'5
C'
Co)
I
..
2
NAHI
~I
10
•
-------- -- --,
r--
----
_ _ _ _ _ .JI
+ 1
Iclock/50
y'R2/R4+1
R2/R3
HOlP (as I approaches 01 =
HOBP (at f
= 101
=
-
-R2/R1
R2/R4 + 1
R3/R1
HON 1 (as I approaches 01
=
-R2/R1
R2/R4 + 1
z
o
HON2 (as I approaches 0.5 Iclockl = - R2/R1
j:::
Circuit dynamics:
HOBP
=
IAGND
n
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0'
:::l
(")
I
,
""I:"'
...+/
NAHI
I
BPi
I
I
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APIN'
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III
2
~I
I
~--"--
VDD-...j.!!!-
'-+
'-
-
'-:-
r-
-
r-n>
"7't>
=
BAND-PASS OUT
I
'-:-
I--- +
+
'---
:L1-"_________
10
NOTCH OUT
-
lPI
I
I
I
I
---
-.J
....
R3
R2
.,
lOW-PASS OUT
I
I
I
..L
...,..,.
R4
I
I
I
..J
Ifclock/100 or fclock/50) ~
Q = ~x R3/R2
HOHP las f approaches 0.5 Iclock) = - R2/R1
HOlP las f approaches 0) = - R4/R 1
HOBP lat f = 101 = - R3/R1
Circuit dynamics:
R2/R4 = HOHP/HOlP: HOBP = t'HOHP x HOlP x Q
HOlP Ipeak) = Q x HOlP Ifor high Qs)
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HOHP Ipeak)
=
Q x HOHP Ifor high Qs)
tin this mode. the feedback loop is closed around the input summing amplifier; the finite GBW product of this operational amplifier will
cause a slight Q enhancement. If this is a problem. connect a low-value capacitor 110 pF to 100 pF) across R4 to provide some phase lead.
2
(")
m
FIGURE 4. MODE 3 FOR HIGH-PASS. BAND-PASS. AND LOW-PASS OUTPUTS
-2
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2
2-130
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
ADVANCE
INFORMATION
TLC1 0, TLC20
UNIVERSAL DUAL SWITCHED·CAPACITOR FILTER
,.
TYPICAL APPLICATION DATA
fclock
R1
iI
------.....,
TLC10. TLC20
r--
L-:.=:.:..._ _ _ _ _-/
I
NONOVERLAPPING
CLOCK GENERATOR <1>2
!II
I
.~
..
::s
CJ
(j
BPi ...- + - 4 - - - - - - - - B A N O - P A S S OUT
r-++-----=::-:-I
It>
Jt>
....---1+
I
0'
EXTERNAL
OPERATIONAL
AMPLIFIER
NOTCH OUT
I
R3
~
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I
I
C
o
CJ
C
+
-
r---
1 __, -
;::;:
Ul
...-+- BAND-PASS OUT
~-+-----~
I
~.
All-PASS OUT
I
I
APIN
I
~
I
-"'" >4..-_________-++___~NA:.;;H:.:.I!.__...r. . . . .
CLOCK GENERATOR
I
iir
;::;:
n
-- -,
y, TlC10 TlC20
r--
r-n>
~
I
'--
r---- +
-
-
VDD+~
-
'-
I
LPI
LOW-PASS OUT
+
'"--
:I~
L ___________ _
I
I
R3
R2
I
I
..J
fa = fclock/100 or fclock/50
fz = fo t
= fo/BW = R3/R2
o
Oz = R3/R1
HOAP (at 0 sis 0.5 Iclock)
(lor AP output R1 = R21
= - R2/R1 =
-1
+ 1) = -2
(R2/R1 + 1) = - 2 (R3/R2)
HOlP (as I approaches.Q) = -(R2/R1
HOBP (at I
l>
= fa) = - R3/R2
Circuit dynamics:
C
HOBP = HOlP X 0 = (HOAP + 1) 0
~
tDue to the sampled-data nature of the filter, a slight mismatch of fz and fo occurs causing a O.4-dB peaking around fa of the all-pass
filter amplitude response (which theoretically should be a straight line). If this is unacceptable, Mode 5 is recommended.
Z
om
-
FIGURE 6. MODE 4 FOR ALL-PASS. BAND-PASS. AND LOW·PASS OUTPUTS
Z
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2-132
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
TLC10,TLC20
UNIVERSAL DUAL SWITCHED·CAPACITOR FILTER
ADVANCE
INFORMATION
TYPICAL APPLICATION DATA
Ir--
fclock
VI
..-
% TLC10 TLC20
II CLOCK GENERATORI~
1/>2
ICLK
....
APIN
COMPLEX ZERO OUT
c
I
I
BPi
I
I
'- ~
+.
I
----
,-_'-
VDD+~
:l~
-+
+
J1>
----
BAND·PASS OUT
cr
Co)
I
LPI
LOW-PASS OUT
+
-
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'.;::
R3
10
Q
I
I
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TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·133
TLC10.TLC20
UNIVERSAL DUAL SWITCHED·CAPACITOR FILTER
ADVANCE
INFORMATION
TYPICAL APPLICATION DATA
II
c
!!
DI
fclock
I
VI
CK-- -
I
R1
..Q
c
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-
-I,
...
NAH
I
...
,
r-++-____BP....;'--4-+_ LOW-PASS OUT
I
(INVERTED)
I
APlN'
~r
c
::t.
r=+-t-----f-
*1
I '- J.-
III
,
1~>-.....---------t-+---""';;~---4- HIGH·PASS OUT
I
n
-
IAGND
*,
n
~O:E-RLA-PP-IN-GI-~.p-1
'CLOCK GENERATOR .p2
IN-
l>
-
Yo TLC10 TLC20
-+
....---1+
VDD-~
R2
I r-'IL I ____________ -1,
fc = R2/R3 (fclock/100 or fclock/50)
HOlP =
~R3/R1
HOHP = -R2/R1
FIGURE 8. MODE 6 FOR SINGLE·POLE HIGH·PASS AND LOW·PASS OUTPUT
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2-134
. TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TLC10,TLC20
UNIVERSAL DUAL SWITCHED·CAPACITOR FILTER
ADVANCE
INFORMATION
TYPICAL APPLICATION DATA
fclock
I
•
% TLC 1 0 TLC20
CK- -
-
I .:,=w-:~-
-
I
-
---,
I
ICLOCK GENERATOR <1>2
IN-
IAGND
~I
I
...
I:,)
NAHI
.
I
I
BPi
I
I
APIN 1
I
I_~
VDD-~
LOW-PASS OUT
(NON INVERTED)
Ei>
'-+
,--
'-
---
r-n>
~
'---
:L 1-'____
-
I
+
-
.
c
o
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cr
(,)
;
TLC10.TLC2D
UNIVERSAL DUAL SWITCHED·CAPACITOR FILTER
•
HOBP~------------~'
...rn
0.707 HOBP ~--------..,~-+--\.
;;:
'S
t!>
...
u
U
I:
fL
fo
o
'';:;
fH
'iii
'S
C'
u
f (LOG SCALE)
FIGURE 11. BAND·PASS OUTPUT
«
HOp
:>
HOLP
>
; 0.707 HOLP
;;:
-
...
CO
CO
C
~
t!>
f'
fp
~ fo J1 - 2~2
HOp ~ HOlP x
fp
fe
--===
2..J
1 _ 1
o
40 2
f (LOG SCALE)
FIGURE 12. LOW·PASS OUTPUT
:>
>
;
;;:
S!
HOp~-----~~
HOHP~--------~~
Z
o
-
0.707 HOHP ~----..,.r
HOp
~ HOHP x _--,1_ _
fp
2..J
o
1 _
1
40 2
le:(
~
a:
o
LlZ
f (LOG SCALE)
FIGURE 13. HIGH·PASS OUTPUT
W
(,)
Z
e:(
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TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-137
•
2-138
TLC532AM, TLC532AI, TLC533AM, TLC533AI
LinCMOSTM 8-BIT ANALOG-TO-DiGITAL PERIPHERALS
WITH 5 ANALOG AND 6 DUAL-PURPOSE INPUTS
0281
•
LinCMOSTM Technology
•
8-Bit Resolution
Total Unadjusted Error ... ±0.5 LSB Max
•
Ratiometric Conversion
•
Access Plus Conversion Time:
TLC532A ... 15 p's Max
TLC533A . . . 30 p's Max
REFGNO
3-State. Bidirectional I/O Data Bus
•
5 Analog and 6 Dual-Purpose Inputs
•
On-Chip 12-Channel Analog Multiplexer
•
Three On-Chip 16-Bit Data Registers
•
Software Compatible with Larger TL530 and
TL531 (21-lnput Versions)
•
On-Chip Sample-and-Hold Circuit
•
Single 5-V Supply Operation
REF+ (Al)
VCC
2- 1 (MSB)
2- 2
2- 3
2- 4
2- 5
I/O
DATA
BUS
•
...
AO}
A2
ANALOG
A3
INPUTS
A4
A5
~ =~
!II
.
·3
Co)
C3
~ ~ ~;~;
2 - 8 (lSB)
READ/WRITE IR/W)
CLOCK (ClK)
REGISTER SELECT (RS)
CHIP SELECT (CS)
'-l.:"':""'_J-'
c
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A 12/03
DIGITAL
A 13/04
INPUTS
A 14/05
A 15/06
RESET (R'j
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IF SC BIT IS LOGIC ONE (HIGH)~--;-,---+---~
I
I
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I I
C3
I
START CONVERSION CYCLE
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re---twL(resetl-------llj
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DATA
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~
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~ ten
~
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,
:
I
lS
LS
LS
lS
:
B~E
B~E
B~E
8~E
L
I
i
~
.., ~ten I
I4-ten I
-+I If-ten
I
:
L
I
I
... .., 14-
-.! ,.ten
I
LS
MS
BYTe
BYTE
This is a l6-bit input instruction from the microprocessor being sent to the control data register.
This is the 2-byte 116-bit) content of the digital data register being sent to the microprocessor.
This is the LS byte (S-bit) content of the analog conversion data register being sent to the microprocessor.
This is the LS byte IS-bitl content of the digital data register being sent to the microprocessor.
These are MS byte IB-bit), LS byte IB-bitl. and LS byte IB-bit) content of the analog conversion data register or digital data
register being sent to the microprocessor.
F. This is the 2-byte (16-bit) content of the analog conversion data register being sent to the microprocessor.
I
-+t t.tsu~US)l._tsu(bUS)
MS
B!,!E
HI·ZSTATE
NOTES: A.
B.
C.
D.
E.
tn
I
I
I
lS
BYTE
TLC532AM, TLC532AI, TLC533AM, TLC533AI
LinCMOS™ 8·BIT ANALOG·TO·DIGITAL PERIPHERALS
WITH 5 ANALOG AND 6 DUAL·PURPOSE INPUTS
read or write cycle time sequence
trlClK)..j
3
ClK
\4- ...j j.-tf(ClK)
CLOCK #1
(Seo Noto A)
CONTROL
INPUTS
RiW
RS
I
I!-___----'
)
----J
.... (A)~
'+-1
I
START
CONVERSION
,--.,.....--4-_1-_-;.,1
IXXXXXXXXXXX)9{
.... (CS)-I
I
I
END I
CO. NVERSION .....
)
II
--J ~thlC)
j4-
__~_~__-J~~-------~-----
I
--I i--tenI
~
.
U
c
o
'iii
'5
'';:;
C"
Co)
..
«XXXXXXXOO>OC
I
'J~I
28
~n-
I
ii
CLOCK #10
Q
I
DATA BUS
DATA OUT
("READ")
HI·Z
MS
BYTE
HI·Z
I
HI·2
lS!
BYT See Nota B
I
I
I
~~"'is
tsu(bus)-+! j4r"j
DATA BUS
DATA IN
("WRITE")
HI-Z
MS
BYTE
I
I
I
"'I~tdis
~
14- tsu (bus)
'I
I
HI·Z
...J
th(bUS)~~
lS
BYTE
I
HI·Z
I
I
'--
--I j4""thibUS)
1
I
Ie
I
tacq
.1
NOTES: A. The reset pulse fFi low) is required only during power-up.
B. The most-significant byte output of Data Out occurs when elK is high. When elK is low, Data Out is in the high-impedance
(off) state. When elK goes high again, the least-significant byte is placed on the data bus. At this point, the least-significant
byte will remain on the bus for as long as elK is kept high.
TEXAS •
INSTRUMENTS
P051 o••'c. lOX 8nola • DALI.AS, t.~A. 1d20&
2-143
TLC532AM, TLC532AI, TLC533AM, TLC533AI
LinCNiOSTM 8·BIT ANALOG·TO·DIGITAL PERIPHERALS
WITH 5 ANALOG AND 6 DUAL·PURPOSE INPUTS
DATA BUS
LINES 2- 1
2-2
2- 3
2- 4
2- 5
2- 6
2- 7
X
X
X
X
X
X
IfM~BII
I
I
I
I
I
f~SCBII IfM~BII
MOST-SIGNIFICANT BYTE
t
c
.!
I
2- 1
2- 8
1
2- 2
2- 3
2- 4
2- 5
X
X
X
A3
I
I..
2- 6
2- 7
Al
I A2
I
I
2- 8
If~~11
LEAST-SIGNIFICANT BYTE
:1
lS-BIT WRITE
III
Unused Bits (X) - The MS byte bits 2 - 1 through 2 -7 and LS byte bits 2 - 1 through 2 -4 of the control register are not used internally.
l>
C')
Start Conversion (SC)- When the
bit in the MS byte is set to a logical 1 (high levell, analog-ta-digital conversion of the specified analog channel
will begin immediately after the completion of the control register write.
Analog Multliplex Address IAO-A31- These four address bits are decoded by the analog multiplexer and used to select the appropriate analog channel as
shown below:
.Q
c
se
iii"
Hexadecimal Address (A3
= MSB)
1
Channel Select
AO
REF+ (Al)
2-5
A2-A5
c
6-9 (not used)
A-F
A10-A15
UI
FIGURE 1. CONTROL REGISTER TWO-BYTE WRITE WORD FORMAT AND CONTENT
::+
0'
o
::s
n
~'
::+
DATA BUS
2- 1
LINES
I(~~~II
2- 7
2-2
2- 8
O~
0
1 4 - - - - - - MOST-SIGNIFICANT BYTE
14------~-S-BIT
REAO - - - - - -
2- 1
2-2
2-3
2- 4
2- 5
2- 6
2- 7
I(:~B)I
RS
R5
R4
R3
R2
Rl
j~
I
I
I
I
2- 8
I (L:OBII
LEAST-SIGNIFICANT BYTE
16-BIT READ
AID Status (EOC)- The AID status end·of·conversion IEOe) bit. is set whenever an analog-to-digjtal conversion is successfully completed by the AID converter.
The status bit is cleared by a 16-bit write from the microprocessor to the control register. The remainder of the bits in the MS byte of the analog conversion
data register are always reset to logical 0 to ~implifv microprocessor interrogation of the AID converter status.
AID Result (RO-R71- The LS byte of the analog conversion data register contains the result of the analog-ta-digital conversion. Result bit R7 is the MSB and
the converter follows the standard convention of assigning a code of all ones (11111111) to a full-scate analog voltage. There are no special overflow
or underflow indications.
FIGURE 2. ANALOG CONVERSION DATA REGISTER ONE-BYTE AND
TWO-BYTE READ WORD FORMAT AND CONTENT
DATA BUS
1,::,1 ':: 1';' 1';'1 ';' 1';'1 ';' 1~: 1
LINES 2- 1
A15
1D6
(MSS)
1 4 - - - - - - MOST-SIGNIFICANT BYTE
J+--------S-BIT
----~
~
LEAST-SIGNIFICANT
BYTE-----~
REAO-------1~
14-------------------1S-BIT
READ------------------~
Shared Digital Port (A10/D1-A15/D61- The voltage present on these pins is interpreted as a digital signal and the corresponding states are read from these
bits. A digital value will be given for each pin even if some or all of these pins are being used as analog inputs.
Analog Multiplexer Address (AO-A3)- The address of the selected analog channel presently addressed is given by these bits.
Unused Bits (X)- lS byte bits ?-3 through 2- 8 of the digital data register are not used.
FIGURE 3. DIGITAL DATA REGISTER ONE-BYTE AND TWO-BYTE READ WORD FORMAT AND CONTENT
2-144
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TLC532AM. TLC532AI. TLC533AM. TLC533AI
LinCMOSTM 8·BIT ANALOG·TO·DIGITAL PERIPHERALS
WITH 5 ANALOG AND 6 DUAL·PURPOSE INPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 6.5 V
Input voltage range: Positive reference voltage. . . . . . . . . . . . . . . . . . . . .. VREF _ to VCC + 0.3 V
Negative reference voltage. . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to VREF +
All other inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to VCC + 0.3 V
Input current, II (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 10 mA
Total input current, (all inputs) ............................................. ± 20 mA
Operating free-air temperature range: TLC532AM, TLC533AM .............. - 55°C to 125°C
TLC532AI, TLC533AI ................. -40°C to 85°C
Storage temperature range ......................................... -65°C to 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package. . . . . . . . . . . .. 260°C
Case temperature for 10 seconds: FN package ................................... 260°C
Supply voltage, V cc
Positive reference VOltage, VREF + (see Note 2)
Negative reference voltage, VREF _ (see Note 21
Low·level input voltage, VIL
VREF-
I Clock input
other digital inputs
NOM
TLC533A
MAX
MIN
NOM
MAX
4.75
5
5.5
4.75
5
5.5
2.5
vee+ O. 1
2.5
2.5
-0.1
vee
0
-0.1
vee
0
Vee+ O•1
2.5
1
Vee
Vee+ O. 2
1
Vee
Vee+ O.2
Vee- O.B
2
Vee- O•B
0.8
0.1
2
2.048
0.1
1.048
0.8
V
1.06
MHz
75
100
ns
145
ns
Data bus input setup time, tsu{bus)
140
185
ns
Control (R/W, RS, and CSI hold time, th(CI
10
20
ns
Data bus input hold time, th(busl
15
20
ns
305
575
3
3
Pulse duration of clock high, twH(CLKI
230
440
Pulse duration of clock low, twL(CLKI
200
410
Pulse duration, reset low. twL(reset)
C
V
V
V
V
100
Pulse duration of control during read, twlC)
....CIJCIJ
UNIT
Address (R/W and RSI setup time, tsu(AI
CS setup time, tsu(CSI
'iii
V
2
I Any digital input
Clock frequency, fCLK
C
o
'~
u
TLC532A
I All
u
High-level output voltage
IOH = -1.6 mA
VOL
low-level output voltage
IOL = 1.6 mA
IIH
IlL
()
.c
c
High-level
Any digital or Clock input
input current
Any control input
Low-level
Any digital or Clock input
input current
Any control input
Off-state (high impedance-state)
IOZ
iii'
;:;
Analog input current (see Note 3)
II
and all other analog channels
()
Ci
;:;
ICC+IREF+
ICC
C/I
MAX
vcc.
UNIT
V
0.4
10
VIH = 5.5 V
1
-10
VIL = 0
-1
10
10
V
p.A
~A
~A
;500
nA
±400
nA
I Digital pins 3 thru 10
4
30
I Any other input pin
2
15
Supply current plus reference current
VCC = VREF+ = 5.5 V.
Outputs open
1.5
3
mA
Supply current
VCC = 5.5 V
1.4
2
mA
Input capacitance
~r
Typt
2.4
VI - 0 to VCC
VI = 0 to VCC.
Clock input at 0 V
Leakage current between selected channel
:::J
MIN
VO=VCC
Vo - 0
output current
0'
c
TEST CONDITIONS
VOH
-
pF
NOTE 3: Analog input current is an average of the current flowing into a selected analog channel input during one full conversion cycle.
operating characteristics over recommended operating free-air temperature range, VREF +
VREF - at ground, fCLK .. 2 MHz (unless otherwise noted)
TEST CONDITIONS
MIN
TYpt
MAX
UNIT
See Note 4
±0.5
LSB
Zero error
See Note 5
±0.5
LSB
Fullpscale error
See Note 5
±0.5
LSB
Total unadjusted error
See Note 6
±0.5
LSB
Absolute accuracy error
See Note 7
±1
teonv
30
tacq
Channel acquisiti~n time prior to starting conversion
10
ten
Data output enable time (see Note 8)
CL - 50 pF. RL = 3 kO.
Idis
Data output disable time
CL - 50 pF. RL - 3 kO
tf(bus)
Vcc.
PARAMETER
Unearity error
Conversion time (including
channel acquisition time)
tr(bus)
-
Data bus output High-impedance to high-level
rise time
Low to high-level
Data bus output High-impedance to low-level
fall time
High to low-level
CL = 50 pF. RL.= 3 kO
CL = 50 pF. RL = 3 kO
LSB
Clock
Cycles
Clock
Cycles
250
10
ns
ns
150
300
150
300
ns
ns
tTypical values are at VCC = 5 V. TA = 25°C.
NOTES: 4. Linearity error is the deviation from the best straight line through the AID transfer characteristics.
5. Zero error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the convertad output for full-scale input voltage.
6. Total unadjusted error is the sum of linearity, zero, and full-scale errors.
7. Absolute accuracy error is the maximum difference between af' analog value and the nominal midstep value within any ·step.
This includes all errors including inherent quantization error, which is the ± 0.5 LSB uncertainty caused by the AID converters
finite resolution.
8. II chip-select setup time. tsuICS). is less than 0.14 microseconds. the effective data output enable time. ten. may extend
such that tsu(CS) + ten is equal to a maximum of 0.475 microseconds.
2-146
TEXAS . "
INSTRUMENTS
POST OFFIr.F ROX R!55012 • OAL LAS. TFXAS 7!;1.65
TLC533AM, TLC533AI
LinCMOSTM 8-BIT ANALOG-TO-DIGITAL PERIPHERALS
WITH 5 ANALOG AND 6 DUAL-PURPOSE INPUTS
electrical characteristics over recommended ranges Vee, VREF + , and operating free-air temperature,
VREF - at ground, feLK = 1.048 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
=
VOH
High-level output voltage
IOH
VOL
Low-level output voltage
IOL - 1.6 mA
IIH
IlL
IOZ
II
High-level
Any digital or Clock input
input current
Any control input
Low-level
Any digital or Clock input
input current
Any control input
=
VIL
=0
1
-10
-1
10
VO-VCC
Va
Analog input current Isee Note 3)
VI - 0 to VCC
Leakage current between selected channel
VI = 0 to VCC,
Clock input at 0 V
=0
Any other input pin
ICC+IREF+
Supply current plus reference current
VCC = VREF+
Outputs open
ICC
Supply current
VCC
=
5.5 V,
5.5 V
V
II
...
II)
.
"S
~A
u
(3
~
C
~A
o
±500
nA
±400
nA
"iii
"S
-10
Digital pins 3 thru 10
UNIT
V
5.5 V
=
MAX
10
output current
Input capacitance
Typt
0.4
Off-state Ihigh impedance-state)
and all other analog channels
Ci
VIH
MIN
2.4
-1.6 mA
"+:=
CO
u
4
30
2
15
1.3
3
mA
1.2
2
mA
«
pF
...caca
Q
NOTE 3: Analog input current is an average of the current flowing into a selected analog channel input during one full conversion cycle.
operating characteristics over recommended ranges Vee, VREF +, and operating free-air temperature,
VREF - at ground, fclock = 1.048 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
See Note 4
±0.5
LSB
Zero error
See Note 5
±0.5
LSB
Full-scale error
See Note 5
±0.5
LSB
Total unadjusted error
See Note 6
±0.5
LSB
Absolute accuracy error
See Note 7
±1
Conversion time (including
tconv
Channel acquisition time prior to starting conversion
ten
Data output enable time Isee Note 8)
CL - 50 pF, RL - 3 k!l,
tdis
Data output disable time
CL - 50 pF. RL
tflbus)
Data bus output
High-impedance to high-level
rise time
Low to high·level
Data bus output
High-impedance to low-level
fall time
High to low-level
Cycles
Clock
10
=
3 k!l
CL
=
50 pF, RL
=
3 k!l
CL
=
50 pF, RL
=
3 k!l
LSB
Clock
30
channel acquisition time)
tacq
trlbus)
Typt
Linearity error
Cycles
335
10
ns
ns
150
300
150
300
ns
ns
tTypical values are at VCC = 5 V, TA = 25°C.
NOTES: 4. linearity error is the deviation from the best straight line through the AID transfer characteristics.
5. Zero error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
6. Total unadjusted error is the sum of linearity, zero, and full-scale errors.
7, Absolute accuracy error is the maximum difference between an analog value and the nominal mid step value within any step.
This includes all errors including inherent quantization error, which is the ± O. 5 LSB uncertainty caused by the AID converters
finite resolution.
S. If chip-select setup time, tsu(CS), is less than 0.14 microseconds, the effective data output enable time, ten, may extend
such that tsu(CS) + ten is equal to a maximum of 0.475 microseconds.
TEXAS •
INSTRUMENlS
2-147
•
...C
I»
I»
l>
n
.c
c
(ii'
;:;'
0'
:::s
(")
::0'
n
c
;:;'
en
2-148
TLC540M. TLC5401. TLC541 M. TLC5411
LinCMOSTM 8·BIT ANALOG·TO·DlGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
02799. OCTOBER 1983- REVISED DECEMBER 1985
•
LinCMOS'" Technology
•
S-Sit Resolution AID Converter
N DUAL-IN-LiNE PACKAGE
(TOP VIEWI
•
Microprocessor Peripheral or Stand-Alone
Operation
•
On-Chip 12-Channel Analog Multiplexer
•
Built-In Self-Test Mode
•
Software-Controllable Sample and Hold
•
Total Unadjusted Error ... ± 0.5 LSB Max
•
•
TLC541 is Direct Replacement for Motorola
MC145040 and National Semiconductor
ADC0811. TLC540 is Capable of Higher
Speed
INPUT AD
INPUT Al
INPUT A2
INPUT A3
INPUT A4
INPUT A5
INPUT A6
INPUT A7
INPUT A8
GND
II...
VCC
SYSTEM CLOCK
I/O CLOCK
ADDRESS INPUT
DATA OUT
CS
REF+
REFINPUT Al0
INPUT A9
II)
·S
...u
C3
c
o
'';::;
·iii
FN CHIP CARRIER PACKAGE
'S
(TOP VIEWI
u
C'
1048 kHz
20
20
'CLKIIIO) s 525 kHz
100
100
> 525 kHz
40
'CLK(SYSI
(see Note 4)
110
'CLKIIIO)
Operating
free~air
temperature, T A
ns
'CLK(SYS) s 1048 kHz
40
TLC540M. TLC541 M
-55
125
-55
125
TLC5401, TLC5411
-40
85
-40
85
ns
ns
·C
NOTES: 2. Analog input voltages greater than that applied to REF + convert as all "l"s (11111111), while input voltages less than that applied to REFconvert as all "O"s (OOOOOOOO), For proper operation, REF + voltage must be at least 1 volt higher than REF - voltage. Also, the total unadjusted
error may increase as this differential reference voltage falls below 4.75 volts.
3. To minimize errors caused by noise at the chip select input, the internal circuitry waits for three System Clock cycles (or less) after a chip select
falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock~in an address until the minimum
chip select setup time has elapsed.
4. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity of normal
room temperature, the devices function with input clock transition time as slow as 2 microseconds for r,emote data acquisition applications where
the sensor and the AID converter are placed several feet away from the controlling microprocessor.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-151
TLC540M, TLC5401, TLC541 M, TLC5411
LinCMOSTM 8·BIT ANALOG·TO·DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
electrical characteristics over recommended operating temperature range.
VCC - VREF + - 4.75 V to 5.5 V (unless otherwise noted). fCLKU/O)
TLC540 or fCLKU/O) .. 1.1 MHz for TLC541
..
C
DI
DI
l>
n
..c
c
fir
:+
0'
VOH
VOL
IOZ
~'
c
f:
Off-state (high-impedance statel
output current
IIH
High-level input current
IlL
lee
Low-level input current
TEST CONDITIONS
Vec = 4.75 V,
IOH- 360 ~A
IOL = 1.6 mA
Vo - Vee,
Vo - 0,
es at Vee
~atVee
Vee - 4.75 V,
VI = Vee
VI = 0
es at 0 V
Operating supply current
Selected channel leakege current
:::s
n
PARAMETER
High-level output voltage (pin 161
Low-level output voltage
lee + IREF Supply and reference current
I Analog inputs
Input capacitance
ei
Selected channel at Vee,
Unselected channel at 0 V
Selected channel at 0 V,
Unselected channel at Vee
es at 0 V
VREF+ = Vee,
MIN
Typt
t All typical values are at T A = 25 ·e.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75285
MAX
2.4
UNIT
V
0.4
V
10
-10
p.A
0.005
-0.005
2.5
-2.5
JlA
1.2
2.5
mA
0.4
1
-0.4
-1
1.3
3
55
15
i
w
a:
c..
toCJ
:::::>
C
oa:
c..
LinCMOS is a trademark of Texas Instruments Incorporated
PRODUCT PREVIEW documenta contain information
on products in the formative or design p'hase of
developmant. Characteristic data aoil othar
=:~:.ati.::sr~~ dt-:i::a=::I~rTli:ac:~:::~:.:
products without notice.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
Copyright © 1986. Texas Instruments Incorporated
2-157
TLC543M, TLC5431, TLC544M, TLC5441
8·BIT ANALOG·TO·DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 5 INPUTS
PRODUCT
PREVIEW
functional block diagram
•..
REF+
c
CII
CII
ANALOG {
INPUTS
CONVERTER
(SWITCHED-CAPACITORS)
6-CHANNEL
ANALOG
MULTIPLEXER
l>
(')
REF-
.c
c
DATA
OUTPUT
iii"
::;.
o·
~
(')
~r
-+_____
ADDRESS __________
INPUT
c
~.
END-OFI-----r--.---.f-CONVERSION
OUTPUT
~
I/O
CLOCK----------~~----------~~----------~*---t_~t_------~::~_,
CS--------+------------------J
operating sequence
~I.--------------------ta+c--------------------~~
I
I/O I
CLOCK ~
-,-..
:
12131415161718
I
II
It--- ACCESS --.! I+-- SAMPLE -
I
CYCLE B
CYCLE B
I
.......,..,=.dJ"""::--I1
DON'T :CARE
I.
I'
.....---tconv------.t
(S.. N~te A)
CS~.~.------------------------------~,
MSB
ADDRESS
LSB
o
c
c:
n
-I
~
m
S
m
I
CYCLE C
;:;
LSB
~_ _ _-.;D;.;O;.;N.;..'T.;..;;C;.;A;;.;R;;.E_ __
~
HI-Z STATE
__
END OF
CONVERSION
CYCLE C
.~~~---------------------------~r--
~~_ _ _ _ _.;;;D.;;;O.;.;N.;.;'T.;.;C;;;;A.;;;R.;.;E;....~,.
DATA--1
OUT
"a
I
It--- ACCESS ""'" It--- SAMPLE ---.j
If----twH(CS)--"MSB
INPUT--I~-
;:g
!
PREVIOUS
.7
,-----+ A7
MSB CONVERSION DATA A
LSB
_CONVERSION DATA B ___
MSB
LSB MSB
MSB
I
NOTES: A. The conversion cycle, which requires 36 internal system clock periods, is initiated on the 8th falling edge of the I/O Clock
after CS goes low for the channel whose address exists in memory at that time. If CS is kept low during conversion. the I/O
clock must remain low for at least 36 system clock cycles to allow conversion to be completed.
B. The most significant bit (MSB) will automatically be placed on the DATA OUT bus after CS is brought low. The remaining
seven bits (A6-AO) Will be clocked out on the first seven· I/O Clock falling edges.
C. To minimize errors caused by noise at the CS Input. the internal circuitry waits for three internal system clock cycles (1.4 ""
at 2 MHz) after a chip select transition before responding to control input signals. Therefore. no attempt should be made to
clock-in address data until the minimum ch·ip-select setup time has elapsed.
:e
2-158
TEXAS
~
INSTRUMENTS
PO" O~PIC~ .Q~ d"~U • DA••A8, t~x"'. 1UI5
PRODUCT
PREVIEW
TLC543M, TLC5431, TLC544M, TLC5441
8·BIT ANALOG·TO·DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 5 INPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
Input voltage range (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to VCC + 0.3 V
Output voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to VCC + 0.3 V
Peak input current range (any input) ......................................... ± 10 mA
Peak total input current (all inputs) ........................ . . . . . . . . . . . . . . . . .. ± 30 mA
Operating free-air temperature range: TLC5431, TLC5441 . . . . . . . . . . . . . . . . . . .. -40°C to 85°C
TLC543M, TLC544M ................. -55°C to 125°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package ........ 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............ 300°C
Supply voltage, VCC
3
2.5
Positive reference voltage, VREF + Isee Note 2)
Negative reference voltage, VREF _ (see Note 2)
VREF _ Isee Note 2)
Analog input voltage Isee Note 2)
MAX
6
5
4.75 to 5.5 V)
NOM
MAX
6
3
5
2.5
0.1
VCC
0
VCC+0.1
2.5
1
VCC
VCC+0.2
-0.1
VCC+ O.1
2.5
1
VCC
VCC+0.2
VCC
0
VCC
0.8
2.048
System clock frequency, fCLKWOI Ifor VCC ~ 4.75 to 5.5 V)
0
4
V
V
V
V
0.8
V
1.1
MHz
2.1
MHz
200
404
ns
Input/Output clock low, twLII/Oi
200
404
ns
< 1.1 MHz
Duration of CS input high state during conversion, twHICS)
Setup time, address bits at data input
before I/O CLOCKt, tsulAI
Hold time, address bits after I/O CLOCKt, thlA)
Setup time,
CS low
before clocking in first address bits,
Operating free-air temperature, TA
I
TLC543M, TLC544M
I TLC5431, TLC5441
ns
17
17
~s
200
400
ns
0
0
ns
1.4
1.4
tsulCS) Isee Note 4)
100
100
40
> 1.1 MHz
C
V
Input/Output clock high, twHII/O)
LfCLKlIIO)
I fCLKII/O)
....1010
UNIT
V
2
2
0
4.75 to 5.5 V)
MIN
VCC
0
Low-level control input voltage, VIL Ifor VCC - 4.75 to 5.5 V)
I/O clock transition time Isee Note 3)
c
o
'';::
w
a::
Q.
tO
::l
C
o
a::
Q.
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-159
PRODUCT
PREVIEW
TLC543M, TLC5431, TLC544M, TLC5441
8·81T ANALOG·TO·DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 5 INPUTS
•
...mmC
»
n
electrical characteristics over recommended operating temperature range,
VCC - VREF + - 4.75 V to 5.5 V (unless otherwise noted), fCLK(l/O) - 2.048 MHz for TLC543
or fCLK(l/O) - 1.1 MHz for TLC544
PARAMETER
VOH
VOL
.Q
IOZ
iii"
IIH
IlL
lec
c
'Ei:
o
:::J
(")
=i.
Ilkg
n
TEST CONDITIONS
High-level output voltage.
Vee
Data out. EOe
Low-level output voltage
I Data out
I EOe
en
V.
=
Off-state (high-impedance statel
Vo
High-level input current
Vo = O.
VI = Vee + 0.3 V
Low-level input current
VI
Operating supply current
Selected channel leakage current
IREF
Reference current
ei
Input capacitance
II Analog inputs
.
Control ,nputs
t All typical values are at Vee
IOH
-360,.A-
=
IOL
=
CS at
Vee.
UNIT
V
0.4
0.4
Vee
10
CS at Vee
-10
2.5
V
~A
0.005
-0.005
~2.5
,.A,.A-
CS"atOV
1.2
2
mA
Selected channel at Vee.
Unselected channel at 0 V
0.4
1
-0.4
-1
0.1
7
5
1
55
15
=
0
Selected channel at 0 V.
Unselected channel at Vee
VREF+
=
See Figure 1
CSatOV
Vee.
= 5 V. T A = 25°C.
vec
SELECTED
ANALOG
INPUT
OTHER
ANALOG
INPUTS
FIGURE 1. SELECTED CHANNEL LEAKAGE CURRENT
::0
o
C
C
(")
-I
."
::0
m
S
m
=e
2-160
MAX
2.4
1.6 mA
PARAMETER MEASUREMENT INFORMATION
."
Typt
IOL - 3.2 mA
Vee - 4.75 V •
Vee = 4.75 V.
output current
C
:+
= 4.75
MIN
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
,.A-
mA
pF
-a -a
operating characteristics over recommended operating free-air temperature range. VCC
fCLKU/OI = 2.048 MHz for TLC543 or 1.1 MHz for TLC544
PARAMETER
VREF +
TLC543
MIN
TYP
=
TLC544
MAX
MIN
==
mCl
4.75 to 5.5 V.
TYP
U&
Data bus and EOC rise time
tf(bus)
Data bus and EOC fall time
tPHL(EOC)
Propagation delay, 8th 1/0 clock! to EOC
Delay time, EOC to DATA OUT (MSB)
td(EOC)
See Figure 2
(see Note 9)
-1
ns
300
300
ns
300
300
ns
400
400
ns
-1
ps
NOTES: 5. Linearity error is the maximum deviation from the best straight line through the AID transfer characteristics.
6. Zero error is the difference between the output of an ideal and an actual AID converter for zero input voltage; full-scale error is that same difference for fullscale input voltage.
7. Total unadjusted error comprises linearity, zero, and full-scale errors.
8. Both the input address and the output codes are expressed in positive logic. The A5 analog input signal is internally generated and is used for test purposes.
9. The EOC signal is output after 40 internal clock cycles, while the data is available after 36 internal clock cycles. Thus, the delay time, EOC to DATA OUT,
is a negative value equal to four internal system clock cycles less internal propagation delays.
~C)CI-I
eta .....
-n
-I-Ig,
=:J:ool::o
cnz W
m:J:05:
=
......
-Cl-I
:J:oC) .....
.....·n
n-lg,
Cl901::0
ZCI~
-1-'
=~-I
CI-I .....
..... :J:on
..... g,
:J:o-aol::o
Zmol::o
CI=5:
g,=a~
-= . . .
Zm n
C:J:ool::o
-1 ..... 01::0
cncn
_
-a=g,
r:"
Ol
PRODUCT PREVIEW
Data Acquisition Circuits
II
PRODUCT
PREVIEW
TLC543M, TLC5431, TLC544M, TLC5441
8-BIT ANALOG·TO·DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 5 INPUTS
PARAMETER MEASUREMENT INFORMATION
.)1.4: kll
III
OUTPUT
UNOER TEST
c
....
fl
OUTPUT
UNDER TEST
CL
IS •• Not. Al
TEST POINT
CL
1'ISEE NOTE Al
II)
II)
UNOER T E S T T -
T .
CL
l I S•• Not. Al
3 kO
":"
J>
O~ 'r..:~_
TEST POINT
":"
IS •• Not. BI
n
.a
c
;;'
LOAD CIRCUIT FOR
td.
and tf
IS •• Not. BI
LOAD CIRCUIT FOR
tpZH AND tpHZ
t,.
LOAD CIRCUIT FOR
tpZL AND tpLZ
::+
0'
1
~\
::::I
50 %
I '---------..I.t--
n
:;;'
I
n
VCC
- - - - -
0 V
I
INTERNAL
SYSTEM
CLOCK
c
i:
~tpLZ
If---tPZL-----.I
OUTPUT
WAVEFORM 1
IS •• Not. CI
I I
\L 50%
liS•• Not. BI
I
y,::-:
""...._ _-III-;&,
1
...--tPZH----+I
-
Vce
-- 0 V
I4--t!-tPHZ
WA~~~~~~2 _ _ _ _ _ _ _ _ _Jf50%
IS•• Not•.CI
10~
~%---VOOVH
. -
VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES
C~~CK \.=.:.::.=.::..
0.8 V
I
J4- t d---.JIr--_ _ _ __
X-
DATA
OUTPUT _ _ _ _ _- J
-
-
-
2.4V
-
-
-
-
-
0.8 V
VOLTAGE WAVEFORM FOR DELAY TIME
."
/
I/O
CLOCK - - - - - "
::D
o
8TH
CLOCK
EOC
\0.8V
I
r-
o
c::
(')
VOLTAGE WAVEFORM FOR
RISE AND FALL TIMES
~I tPHLIEOCI
~
- - - - - - - -..... 1
EOC
-I
T
..J
2 .4V
:'--tdIEOCI---"
DATA OUT
I
-------C.
2.4V
(
O.4V
I
~VALlDMS8~
."
VOLTAGE WAVEFORMS FOR EOC TIMING
::D
m
~
m
NOTES:
~
A. CL = 50 pF' for TLC543 and 100 pF for TLC544.
B. ten = tpZH or tpZL. tdis = tpHZ or tpLZ'
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
FIGURE 2. OPERATING CHARACTERISTICS
2-162
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76265
PRODUCT
PREVIEW
TLC543M, TLC5431, TLC544M, TLC5441
8·BIT ANALOG·TO·DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 5 INPUTS
PRINCIPLES OF OPERATION
introduction
TLC543 and TLC544 are each complete data acquisition systems on a single chip. They include the functions
of analog multiplexer, sample and hold, 8·bit A/D converter, data and control registers, and control logic.
Flexible serial communication is achieved with a microprocessor or microcomputer using a TTL·compatible
three-state Data Out and four control lines: Chip Select (CS), I/O Clock, Address Input, and End of
Conversion (EOC) output.
.
To maximize access speed, the device simultaneously writes the previous conversion result, reads a new
multiplexer address, and acquires the analog signal. This is followed by the AID conversion, whose end
is signalled by EOC output going high. These Total Access and Conversion Cycles are completed in a
minimum of 22 p's for the TLC543 and 25 p's for the TLC544. Conversion can take place, in any order,
on the five analog inputs or the built-in self-test system.
The system clock,which drives the control logic and the switched-capacitor successive approximation
AID converter, is internal to the device and typically runs at a frequency of 4 MHz. This internal system
clock runs independently and there are no required phase or frequency relationships with other signals .
..
II)
.
"S
u
(3
C
o
"~
"iii
·S
C"
u
..
w
a::
0.
....
CJ
::>
c
o
a::
0.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-163
TLC543M, TLC5431, TLC544M, TLC5441
8·BIT ANALOG-TO·DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 5 INPUTS
PRODUCT
PREVIEW
CS input
To minimize bus contention caused by noise enabling the three-state Data Out, when the CS input is brought
low the device waits for two rising edges and a falling edge of the internal system clock before recognizing
the CS transition. Hence, the setup time tsu(CS) should be observed when using the CS input. This applies
also to a CS high-to-Iow transition, except for disabling of DATA OUT, which goes into a high-impedance
state immediately within the tdis specification (see Figure 3). If this interruption of CS in the low state
is less than 1.5 internal system clock cycles, and hence not recognized, DATA OUT will be immediately
enabled with the return of CS to the low state. DATA OUT becomes enabled after a CS high-to-Iow transition
in time ten (equivalent to tsu(CS) for this device, see Figure 3).
C
I»
;-
»
n
.c
c
::+
CS can be brought high during a conversion without affecting the ongoing conversion but must remain
high until the end of conversion. Otherwise, a CS falling edge will cause a reset condition that will abort
the conversion in progress. When a new access cycle is started, the previous conversion result will be output.
~'
A new conversion may be restarted by toggling CS high-to-Iow at least tsu(CS) before the eighth falling
edge of the 110 clock. The ongoing access cycle will be aborted. Again, when a new access cycle is started,
the previous conversion result will be output.
iii"
S'
::::s
n
n
c
;'
end of conversion output IEOC)
EOC goes Iowa propagation delay time tPHL(EOC) after the 8th falling edge of the 110 clock, and goes
high when conversion is complete. At this time the MSB is available at Data Out; however, if CS is high
it will be necessary to bring CS low and wait for the CS recognition time before Data Out is available,
since Data Out is in a high-impedance state when CS is high. Delay time td(EOC) of EOC to Data Out
is a negative value of 4 internal system clock cycles less internal propagation delay, because the EOC
signal is output after 40 internal system clock cycles whereas conversion is complete with data available
after 36 cycles.
""C
::a
o
c
c:
n-I
""C
::a
m
S
m
~
2-164
TEXAS ..,
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
ADVANCE
INFORMATION
TLC545M. TLC5451. TLC546M. TLC5461
LinCMOSTM 8-BIT ANALOG-TO-DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 19 INPUTS
02850, DECEMBER 1985
N DUAL·IN·L1NE PACKAGE
(TOP VIEWI
•
LinCMOS'· Technology
•
8-Bit Resolution AID Converter
•
Microprocessor Peripheral or Stand-Alone
Operation
•
On-Chip 20-Channel Analog Multiplexer
•
Built-In Self-Test Mode
•
Software-Controllable Sample and Hold
•
Total Unadjusted Error, ..
•
± 0,5
LSB Max
Timing and Control Signals Compatible with
8-Bit TLC540 and 10-Bit TLC1540 AID
Converter Families
TYPICAL PERFORMANCE
TL545
TL546
Channel Acquisition Time
1.5 ~s
9 ~s
76 x 10 3
6mW
2.7 ~s
17 ~s
40 x 103
6mW
Conversion Time
Sampling Rate
Power Dissipation
INPUT
INPUT
INPUT
INPUT
INPUT
AO
A1
A2
A3
A4
INPUT A6
INPUT A7
INPUT A8
INPUT AS
INPUT A10
INPUT A11
INPUT A12
GND
VCC
SYSTEM CLOCK
1/0 CLOCK
ADDRESS INPUT
DATA OUT
CS
REF+
REFINPUT A18
INPUT A17
INPUT A16
INPUT A15
INPUT A14
INPUT A13
..
II)
':;
...
U
C3
C
0
:-2
II)
':;
C'
U
..
------1
,...-_........_ - - ,
A~~:U~S _ _ _ _-+__~
CONTROL LOGIC
AND 1/0
COUNTERS
I-----J
2
1/0
CLOCK
~------_t--------------------~
S;:~:
______t--__________- -____- - - -__
l>
c
~z
n
m
Z
."
o::XI
s:
l>
:::I
o
z
2-166
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DAlLAS. TeXAS 75265
~~-------~
ADVANCE
INFORMATION
TLC545M. TLC5451. TLC546M. TLC5461
LinCMOSTM 8-BIT ANALOG-TO-DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 19 INPUTS
operating sequence
\1
I 2 I 3 I 4 I 5 16 I
7
\S
110
CLOCK--/
OON'T
~
I
1
I2 I
3
\ 4
\ 5
\ 6
I 7 Is
.:<11
'con. ~ f +--ACCESS--'; :'-SAMPLE"":
I JSeeNotaSee
Note A)!~I I
CYCLE C
I I
CYCLE C
,
~~
L-ff-,.- - - - - - - - - - - - - '
w H ( C S I I~- - - - - - - - - - - - - '
~,~
~
.
U
-S
(See Note CI
MSB
LSB
MSB
OON'T CARE
LSB
u
OON'T
CARE
c
o
HI·Z STATE
DATA ---I
OUT.
-iii
B7
_CONVERSION DATA B _ _
MSB
LSB MSB
A7
+-- PREVIOUS CONVERSION DATA A _
MSB
(See Note BI
-.;::;
LSB MSB
-S
C"
NOTES: A. The conversion cycle. which requires 36 system clock periods. is initiated with the 8th 1/0 clockl after CSl for the channel
whose address exists in memory at that time.
B. The most significant bit (MSBI will automatically be placed on the DATA OUT bus after Cs is brought low. The remaining
seven bits (A6-AO) will be clocked out on the first seven I/O clock falling edges.
~
III
III
~
Q
C. To minimize errors caused by noise at the Cs input, the internal circuitry waits for three system clock cycles (or less) after
a chip select transition before responding to control input signals. Therefore. no attempt should be made to clock-in address
data until the minimum chip-select setup time has elapsed.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) ............................................. 6.5 V
Input voltage range (any input) ................................. -0.3 V to VCC +0.3 V
Output voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to VCC +0.3 V
Peak input current range (any input) ......................................... ± 10 mA
Peak total input current (all inputs) .......................................... ± 30 mA
Operating free-air temperature range: TLC5451, TLC5461 . . . . . . . . . . . . . . . . . . .. -40°C to 85°C
TLC545M, TLC546M . . . . . . . . . . . . . . . .. - 55°C to 125°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . .. 260°C
Case temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
z
NOTE 1: All voltage values are with respect to network ground terminal.
o
~
::?!
a:
ou.
Z
w
(J
Z
~
c
20
100
40
20
100
40
fCLK(I/O) :s 525 kHz
fCLK(I/O) > 525 kHz
TLC545M, TLC546M
TLC5451, TLC5461
55
-40
125
85
55
-40
V
V
V
V
V
V
fCLK(SYS) :s 1048 kHz
1048 kHz
UNIT
VCC
190
404
404
200
200
fcLK(SYS)
free-air temperature, T A
VCC+O.1
Vce- 2.5
VCC Vec+0.2
feLK(I!OI
110
System clock low, twL(SYS)
Input/Output clock high, twH(I/O)
Input/Output clock low, twL(I/O)
I/O
5.5
Vce
0
0
System clock frequency, fCLK(SYS)
System clock high, twH(SYS)
(see Note 4)
1
0
5
MIN
4.75
0.8
address bit, tsu(CSI (see Note 3)
System
4.75
2.5
-0.1
MAX
2
Setup time, address bits at data input before I/O CLKt, tsu(A)
Address hold time, th
Clock transition time
TLC545
NOM
125
85
ns
System
clock
cycles
System
clock
cycles
MHz
MHz
ns
ns
ns
ns
ns
ns
°C
NOTES: 2. Analog input voltages greater than that applied to REF + convert as aU"1"s (11111111), while input voltages less than that
applied to REF - convert as aU "O"s (000000001. For proper operation, REF + voltage must be at least 1 volt higher than
REF - voltage. Also, total unadjusted errors may increase as this differential reference voltage falls below 4.75 volts.
»
c
~
:2
3. To minimize errors caused by noise at the Chip Select input, the internal circuitry waits for three system clock cycles (or less)
after a chip select falling edge or rising edge is detected before responding to control input Signals. Therefore, no attempt
should be made to clock-in address data until the minimum chip select setup time has elapsed.
4. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In
the vicinity of normal room temperature, the devices function with input clock transition time as slow as 2 microseconds
for remote data acquisition applications where the sensor and the AID converter are placed several feet away from the controlling
microprocessor.
nm
:2
'"II
o::J:J
3:
l>
::!
o
:2
2-168
..If
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76265
TLC545M. TLC5451. TLC546M. TLC5461
LinCMOSTM 8-BIT ANALOG-TO-DiGITAL PERIPHERALS
WITH SERIAL CONTROL AND 19 INPUTS
ADVANCE
INFORMATION
electrical characteristics over recommended operating temperature range.
VCC ... VREF + ,., 4.75 V to 5.5 V (unless otherwise noted). fCLK(l/O) - 2.048 MHz for TLC545
or fCLK(l/O) ,., 1.1 MHz for TLC546
PARAMETER
TEST CONDITIONS
= 4.75
VOH
High-level output voltage (pin 241
Vee
VOL
Low-level output voltage
Vee - 4.75 V,
10Z
IIH
Off-state (high-impedance statel
Vo
output current
Vo
High-level input current
V,
= Vee,
= 0,
= Vee
III
low-level input current
VI
VI - 0
lee
Operating supply current
es at 0 V
MIN
10H = - 360 p.A
10l - 3.2 rnA
Typt
10
es at Vec
-10
es at Vee
Input capacitance
=
-0.005
-2.5
~A
1.2
2.5
rnA
0.4
1
-0.4
-1
1.3
3
Analog inputs
7
55
I
Control inputs
5
15
Vee,
~
2.5
I
VREF+
C3
III
"S
c
o
"~
"iii
"S
C'
~A
Selected channel at 0 V,
Unselected channel at Vee
ei
~A
...
V
0.005
Selected channel at Vee,
lee + IREF Supply and reference current
~A
•
UNIT
V
0.4
Unselected channel at 0 V
Selected channel leakage current
MAX
2.4
es at 0 V
(,)
c
--+I tPLZ
~ tPHZ
fl50%
10%
- - - - -
r.I
\:90%" - - - -
0V
VOH
.._ _ _ _ OV
VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES
c
<
l>
2
1/0
CLOCK
2
."
o:::D
s:l>
OUTPUT
- - - - 0.4 V
I4- t d--+l
m
-
\-----o.aV
X---------I
(')
1,.-_ _ _ _ _-
DATA
OUTPUT
-------'
2 •4V
----------o.BV
VOLTAGE WAVEFORM FOR DELAY TIME
NOTES:
:::!
o
VOLTAGE WAVEFORM FOR
RISE AND FALL TIMES
A. CL = 50 pF for TLC545 and 100 pF for TLC546
B. ten =. tpZH or tpZL. tdis = tpHZ or tpLZ
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
2
2-170
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
ADVANCE
INFORMATION
TLC545M, TLC5451, TLC546M, TLC5461
LinCMOSTM 8-BIT ANALOG-TO-DiGITAL PERIPHERALS
WITH SERIAL CONTROL AND 19 INPUTS
principles of operation
The TLC545 and TLC546 are both complete data acquisition systems on single chips. Each includes such
functions as system clock, sample-and-hold, 8-bit A/D converter, data and control registers, and control
logic. For flexibility and access speed, there are four control inputs; Chip Select (CS), Address Input, I/O
clock, and System clock. These control inputs and a TTL-compatible 3-state output facilitate serial
communications with a microprocessor or microcomputer. The TLC545 and TLC546 can complete
conversions in a maximum of 9 and 17 microseconds respectively, while complete input-conversion-output
cycles can be repeated at a miximum of 13 and 25 microseconds, respectively.
The System and I/O clocks are normally used independently and do not require any special speed or phase
relationships between them. This independence simplifies the hardware and software control tasks for
the device. Once a clock signal within the specification range is applied to the System clock input, the
control hardware and software need only be concerned with addressing the desired analog channel, reading
the previous conversion result, and starting the conversion by using the I/O clock. The System clock will
drive the" conversion crunching" circuitry so that the control hardware and software need not be concerned
with this task.
When CS is high, the Data Output pin is in a high-impedance condition, and the Address Input and I/O
Clock pins are disabled. This feature allows each of these pins, with the exception of the CS, to share
a control logic point with their counterpart pins on additional A/D devices when additional TLC545ITLC546
devices are used. Thus, the above feature serves to minimize the required control logic pins when using
multiple A/D devices.
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The control sequence has been designed to minimize the time and effort required to initiate conversion
and obtain the conversion result. A normal control sequence is:
1. CS is brought low. To minimize errors caused by noise at the CS input, the internal circuitry waits
for two rising edges and then a falling edge of the System clock after a CS transition before the
transition is recognized. The MSB of the previous conversion result will automatically appear on
the Data Out pin.
2. A new positive-logic multiplexer address is shifted in on the first five rising edges of the I/O clock.
The MSB of the address is shifted in first. The negative edges of these five I/O clocks shift out
the 2nd, 3rd, 4th, 5th, and 6th most significant bits of the previous conversion result. The onchip sample-and hold begins sampling the newly addressed analog input after the 5th falling edge.
The sampling operation basically involves the charging of internal capacitors to 'the level of the
analog input voltage.
3. Two clock cycles are then applied to the I/O pin and the 7th and 8th conversion bits are shifted
out on the negative edges of these clock cycles.
4. The final 8th clock cycle is applied to the I/O clock pin. The falling edge of this clock cycle completes
the analog sampling process and initiates the hold function. Conversion is then performed during
the next 36 system clock cycles. After this final I/O clock cycle, CS must go high or the I/O clock
must remain' low for at least 36 system clock cycles to allow for the conversion function.
CS can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple
conversion, special care must be exercised to prevent noise glitches on the I/O Clock line. If glitches occur
on the I/O Clock line, the I/O sequence between the microprocessor/controller and the device will lose
synchronization. Also, if CS is taken high, it must remain high until the end of conversion. Otherwise,
a valid falling edge of CS will cause a reset condition, which will abort the conversion in progress.
A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps
1 through 4 before the 36 system clock cycles occur. Such action will yield the conversion result of the
previous conversion and not the ongoing conversion.
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TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-171
TLC545M, TLC5451, TLC546M, TLC5461
LinCMOSTM 8·BIT ANALOG·TO·DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 19 INPUTS
ADVANCE
INFORMATION
It is possible to connect the system and 1/0 clocks together in special situations in which controlling circuitry
points must be minimized. In this case, the following special points must be considered in addition to the
requirements of the normal control sequence previously described.
i. When CS is recognized by the device to be at a low level, the common clock signal is used
as an 1/0 clock. When the CS is recognized by the device to be at a high level, the common
clock signal is used to drive the "conversion crunching" circuitry.
2. The device will recognize a CS transition only when the CS input changes and subsequently
the system clO(::k pin receives two positive edges and then a negative edge. For this reason,
after a CS negative edge, the first two clock cycles will not shift in the address because a
low CS must be recognized before the 1/0 clock can shift in an analog channel address. Also,
upon shifting in the address, CS must be raised after the 6th 1/0 clock, which has been
recognized by the device, so that a CS low level will be recognized upon the lowering of the
8th 1/0 clock signal recognized by the device. Otherwise, additional common clock cycles will
be recognized as 1/0 clocks and will shih in an erroneous address.
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For certain applications, such as strobing applications, it is necessary to start conversion at a specific point
in time. This device will accommodate these applications. Although the on-chip sample-and-hold begins
sampling upon the negative edge of the 5th 1/0 clock cycle, the hold function is not initiated until the negative
edge of the 8th 1/0 clock cycle. Thus, the control circuitry can leave the 1/0 clock signal in its high state
during the 8th 1/0 clock cycle, until the moment, at which the analog signal must be converted. The
TLC545/546 will continue sampling the analog input until the 8th falling edge of the 1/0 clock. The control
circuitry or software must then immediately lower the 1/0 clock signal to initiate the hold function at the
desired point in time and to start conversion.
Detailed information on interfacing to most popular microprocesors is readily available from the factory.
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2-172
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
TLC548, TLC549
LinCMOS'" 8·BIT ANALOG·TO·DIGITAL
PERIPHERAL WITH SERIAL CONTROL
02816,
•
LinCMOSTM Technology
•
Microprocessor Peripheral or Stand·Alone
Operation
(TOP VIEW)
•
8·Bit Resolution A/D Converter
•
Differential Reference Input Voltages
•
Conversion Time , , . 17 p's Max
•
Total Access and Conversion Cycles Per Second
TLC548 ... up to 45,500
TLC549 , .. up to 40,000
REF+rJ]B VCC
ANALOG IN 2
7
1/0 CLOCK
REF- 3
6 DATA OUT
GND 4
5
CS
•
On·Chip Software-Controllable Sample-and-Hold
± 0.5
1983-REVISEO JULY 1986
TLC548M, TLC549M ... 0 DR P PACKAGE
TLC5481. TLC5491 ... 0 OR P PACKAGE
TLC548C. TLC549C .•• 0 PACKAGE
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Total Unadjusted Error ...
•
4-MHz Typical Internal System Clock
•
Wide Supply Range ... 3 V to 6 V
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The TLC548 and TLC549 are each complete data acquisition systems on a single chip. Each contains an internal
system clock, sample-and-hold, 8-bit A/D converter, data register, and control logic circuitry. For flexibility and
access speed, there are two control inputs: I/O Clock and Chip Select (CS). These control inputs and a TTLcompatible three-state output facilitate serial communications with a microprocessor or minicomputer. A
conversion can be completed in 17 microseconds or less, while complete input-conversion-output cycles can·
be repeated in 22 microseconds for the TLC548 and in 25 microseconds for the TLC549 .
The internal system clock and I/O clock are used independently and do not require any special speed or phase
relationships between them. This independence simplifies the hardware and software control tasks for the device .
Due to this independence and the internal generation of the system clock, the control hardware and software
need only be concerned with reading the previous conversion result and starting the conversion by using the
I/O clock. In this manner, the internal system clock drives the "conversion crunching" circuitry so that the control
hardware and software need not be concerned with this task.
When CS is high, the data output pin is in a high-impedance condition and the I/O clock pin is disabled. This
CS control function allows the I/O Clock pin to share the same control logic point with its counterpart pin when
additional TLC548 and TLC549 devices are used. This also serves to minimize the required control logic pins
when using multiple TLC548 and TLC549 devices.
The control sequence has been designed to minimize the time and effort required to initiate conversion and
obtain the conversion result. A normal control .sequence is:
1. CS is brought low. To minimize errors caused by noise at the CS input, the internal circuitry waits for
two rising edges and then a falling edge of the internal system clock after a CS~ before the transition
is recognized. However, upon a CS rising edge, DATA OUT will go to a high-impedance state within
the tdis specification even though the rest of the IC's circuitry will not recognize the transition until
the tsu(CS) specification has elapsed. This technique is used to protect the device against noise when
used in a noisy environment. The most significant bit (MSB) of the previous conversion result will initially
appear on the DATA OUT pin when CS goes low.
2. The falling edges of the first four I/O clock cycles shift out the 2nd, 3rd, 4th, and 5th most significant
bits of the previous conversion result. The on-chip sample-and-hold begins sampling the analog input
after the 4th high-to-Iow transition of the I/O Clock. The sampling operation basically involves the charging
of internal capacitors to the level of the analog input voltage.
3. Three more I/O clock cycles are then applied to the I/O pin and the 6th, 7th, and 8th conversion bits
are shifted out on the falling edges of these clock cycles.
4. The final, (the 8th), clock cycle is applied to the I/O clock pin. The on-chip sample-and-hold begins the
hold function upon the high-to-Iow transition of this clock cY,cle. The hold function will continue for
the next four internal system clock cycles, after which the holding function terminates and the conversion
is performed during the next 32 system clock cycles, giving a total of 36 cycles. After the 8th I/O clock
cycle, CS must go high or the I/O clock must remain low for at least 36 internal system clock cycles
to allow for the completion of the hold and conversion functions. CS can be kept low during periods
of multiple conversion. When keeping CS low during periods of multiple conversion, special care must
be exercised to prevent noise glitches on the I/O Clock line. If glitches occur on the.I/O Clock line, the
I/O sequence between the microprocessor/controller and the device will lose synchronization. If CS
is taken high, it must remain high until the end of conversion. Otherwise, a valid high-to-Iow transition
of CS will cause a reset condition, which will abort the conversion in progress.
A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1
through 4 before the 36 internal system clock cycles occur. Such action will yield the conversion result of the
previous conversion and not the ongoing conversion.
2-178
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
TLC548, TLC549
LinCMOSTM 8-BIT ANALOG-TO-DIGITAL
PERIPHERAL WITH SERIAL CONTROL
PRINCIPLES OF OPERATION
For certain applications, such as strobing applications, it is necessary to start conversion at a specific point
in time. This device will accommodate these applications. Although the on-chip sample-and-hold begins sampling
upon the high-to-Iow transition of the 4th I/O clock cycle, the hold function does not begin until the high-to-Iow
transition of the 8th I/O clock cycle, which should occur at the moment when the analog signal must be converted.
The TLC548 and TLC549 will continue sampling the analog input until the high-to-Iow transition of the 8th
I/O clock pulse. The control circuitry or software will then immediately lower the I/O clock signal and start the
holding function to hold the analog signal at the desired point in time and start conversion.
Detailed information on interfacing to the most popular microprocessor is readily available from Texas Instruments.
II
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Copyright @ 1987, Texas Instruments Incorporated
PRODUCT PREVIEW documonts contsin information
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ADVANCED LinCMOS" is a trademark of Texas Instruments Incorporated
on products in the farmative or design ~ha8' of
development. Characteristic data Bnil othar
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TLC1225
ANLG VCC+
VOD
CLK IN
WR
CS
RD
OGTL GND
REAOY OUT
INT
..
'5
J OR N DUAL-IN-LINE PACKAGE
(TOP VIEWI
ANLG VCCININ+
ANLG GNO
REF
•..
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2-181
PRODUCT
PREVIEW
TLC1205A, TLC1205B, TLC1225A, TLC1225B
SELF·CALIBRATING 12·BIT·PLUS·SIGN UNIPOLAR OR BIPOLAR
ANALOG· TO· DIGITAL CONVERTERS
functional block diagram
•
r - - - MiCRopRocessoR - - - -,
8-BIT
CALIBRATION
DAC
I
ANLG Vccr---
IN+
r
13-BIT
CAPACITOR DAC
AND SIH
T
L
INREF
~
~
-I-
13-BIT
CAPACITOR DAC
AND SIH
13
I
13
8
I
8
8-BIT SWITCH
CONTROL
r+-
8-BIT SAR
I
I
REGISTER 2
8
ALU
ADDRESS
COUNTER
1
13
5 V - 10 V TRANSLATOR
ADDRESS
COUNTER
2
6
13 BIT SAR
INPUT DATA LATCHES
13-BIT CALIBRATION
CONTROL LOGIC
~
13
13-BIT DATA LATCH
41
TLC1205: 41 - 8
TlC1225: 41 - 13
CS
L- _ _ _ _
WR
1_1_ -
I
I
I
I
I
I
I
I
I
I
I
CONTROL
ROM
I
I
I
I
I
I
PROGRAM
COUNTER
INT
I
I
I
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VOS
I
I
I
6
MUX
8-BIT
DATA
PATH
I
CLOCKS
41
I
I
8-WORD
RAM
13-BIT SWITCH CONTROL
1/0 BUS
I
REGISTER 1
8-BIT
IH
CALIBRATION
DAC
I
I
I
--
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RD
READY OUT
STATUS
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ITlC1205 ONLY)
In Mode 1, these converters are replacements for National Semiconductor ADC1205 and ADC1225
integrated circuits. The Mode 1 conversion time for guaranteed accuracy is 51 clock cycles. In the Mode 2
operation, these devices are no longer true replacements. However, the Mode 2 conversion time for
guaranteed accuracy is only 26 clock cycles.
The TLC1205AM, TLC1205BM, TLC1225AM, and TLC1225BM are characterized for operation over the
full military temperature range of - 55°C to 125°C. The TLC1205AI, TLC1205BI, TLC1225AI, and
TLC1225BI are characterized for operation from -40°C to 85°C.
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2-182
TEXAS ."
INSfRUMENlS
POST OFFICE BOX 86501 ~ • DAL.LAS. TeXAS 75265
PRODUCT
PREVIEW
TLC1205A, TLC1205B, TLC1225A, TLC1225B
SELF·CALIBRATING 12·BIT·PLUS·SIGN UNIPOLAR OR BIPOLAR
ANALOG·TO·DlGITAL CONVERTERS
operation description
calibration of comparator offset
The following actions are performed to calibrate the comparator offset:
1. The IN + and IN - inputs are internally shorted together in order that the comparator input is zero.
A course comparator offset calibration is performed by storing the offset voltages of the
interconnecting comparator stages on the coupling capacitors, which connect the interconnecting
stages. Refer to Figure 1. The storage of offset voltages is accomplished by closing all switches
and then opening switches A and A', then switches Band B', and then C and C'. This process
continues until all interconnecting stages of the comparator are calibrated. After this action, some
of the comparator offset still remains uncalibrated.
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NOTE 1: Bipolar input range is defined as: VI + = - 5.05 V to + 5.05 V, VI_ = - 5.05 V to + 5.05 V, and IVI + - VI-I'" 5:05 V.
The unipolar input voltage range is defined as: VI+ = -0.05 V to 5.05 V, VI_ = -0.05 V to 5.05 V,
and I VI + - VI_ I '" 5.05 V.
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TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-185
TLCn05A, TLC1205B, TLC1225A, TLC1225B
SELF·CALIBRATING 12·BIT·PLUS·SIGN UNIPOLAR OR BIPOLAR
ANALOG· TO·DlGITAL CONVERTERS
PRODUCT
PREVIEW
, operating characteristics over recommended operating free·air temperature range.
ANLG Vee+ '" DGTL Vee = Vref '" 5 V. ANLG Vee- = -5 V (for bipolar input rangel.
ANLG Vee - '" ANLG GND (for unipolar input rangel. fclock '"" 2.6 MHz (unless otherwise noted)(see
Note 11
PARAMETER
.
TEST CONDITIONS
C
Unipolar input range
I»
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L.inearity error
Bipolar input range
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Adjusted positive and negative
iii"
full-scale error (see Note 2)
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Adjusted positive and negative
~
full-scale error (see Note 3)
(")
Temperature coefficient of gain
~.
Temperature coefficient of offset point
c
Zero error
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k
. Supply voltage
SVS sensitivity
Positive and negative
full-scale error
TLC1205B, TLC1225B
±0.5
TLC1205A, TLC1225A
±2
TLC1205B, TLC1225B
±1.5
Conversion tim
tdis
LSB
LSB
Unipolar input range
±1
LSB
Bipolar input range
±1
LSB
15
ppm/DC
1.5
ppm/DC
ANLG VCC+
ANLG VCC-
=
=
=
±0.75
5 V ± 5%,
-5 V ± 5%,
5 V ± 5%
±0.75
LSB
±0.25
Mode 1
51
Mode 2
26
-felk
210
ns
Access time (delay from falling edge of
ta
UNIT
±0.5
DGTL VCC
Linearity error
te
MAX
±1
Zero error
.Q
MIN
TLC1205A. TLC1225A
CL
=
100 pF
Disable time, output (delay from rising
RL
10 kit
CL
edge of RD to high-impedance state
RL
=
=
2 kll,
CL
C"S.RD to data output)
=
=
10 pF
260
100 pF
290
1
ns
td(READY)
lID or WR
to READY OUT delay
400
ns
tdUNTI
RD or WR to reset of INT delay
400
ns
NOTES:
1. Bipolar input range is defined as: VI + = - 5.05
The unipolar input voltage range is defined. as:
and IVI+ - VI_I :5 5.05 V.
2. See section - Positive and Negative Full-Scale
3. See section - Positive and Negative Full-Scale
V to + 5.05 V, VI_ = - 5.05 V to + 5.05 V, and I VI + - VI_ I :5 5.05 V.
VI+ = -0.05 V to 5.05 V, VI_ = -0.05 V to 5.05 V,
Adjustment, Unipolar Inputs.
Adjustment, Bipolar Inputs .
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2-186
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
PRODUCT
PREVIEW
TLC1205A, TLC1205B, TLC1225A, TLC1225B
SELF·CALIBRATING 12·BIT·PLUS·SIGN UNIPOLAR OR BIPOLAR
ANALOG· TO·DlGITAL CONVERTERS
CALIBRATE
CONVERSION
~A':~~:9
elK IN
o
1
~
26
twICS.WRI
28
35
51
0
1
26
Htw,CS.WR,
1---J~------------~L--J
I
I
"I
I
I
READY OUT
CAPACITOR
r1...fL..fl.n.fl.n .....fl..fl1l. n ..
r
WR
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ANO ONE
INPUT
SAMPliNG
CAPACITOR
T-tj
:
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•
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tdIREADY)
I
if 2nd byte of
LTLC1205 is read
r
!'-----------i-"
I
II
I I
I
~ I4- t dIREADY)
I'-
-.t I't-tdIREADY)
I
~
I
tdIREAOY)~
,
I
~ .tdIREADYI
I I
I I
tdIREADYI-+I ~ :
IItd(lNTI-.....I
i~
II _ _ _ ___
I
I:
I
1--1(--:=
I
"-- CS stays low to address
I
I
RD ------------------------------------;,
L----I
:
I/O BUS
2nd byte of TLC 1205
,i
i
L~-- ..
L
Read 2nd byte of TLC1205
----------------------------rdKi~C-:
I
I
ta~
I4-Idi•
...I
!;nd byte of TLC1205
FIGURE 3. MODE 1 TIMING DIAGRAM
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TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2·187
PRODUCT
PREVIEW
TLC1205A. TLC1205B. TLC1225A. TLC1225B
SELF·CALIBRATING 12·BIT·PLUS·SIGN UNIPOLAR OR BIPOLAR
ANALOG·TO·DIGITAL CONVERTERS
~ T ..I .
•..
CONVERSION
-I
C
~tw(CS.Wii)
----;LJ
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,
READY OUT
:+'
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-+t
I
I
,
:;:,
-..
I
I
~'
I
I
~ If- td(READY)
I
~
~ td(READY)
I
td(READY)
I
-tI
14-
if 2nd byte of
TlC1205 is read
r* . .
I
I
I
I
It- td(READY)
I
I
I
(')
r,
HtW(CS'WR)
It- td(REA~Y)
--~I""
0'
1
~~-----~L--J~------
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..flJ1.n.fl.....n.f"1..fl.fl.n •.
ClKIN
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SAMPLING
SAMPLING
I
I
~
td(READY)~
It- td(READY)
I
~
:td(lNTI~
C
,
:+'
14- t(READY)
It- I
I
:
i-I-:-:~C~S-s-ta-YS-I-OW-
I
,
III
I
to address 2nd byte
of TlC1205
-
--..I
I
I
,
I
I
I
0
----~,-----~,~-----------~~r~L-l.-----J~
lsu~
I
----0(
I
I/O BUS
t.u~·
If-'--*-, th
I
I
\tl _ _ _~~~'j.-_ _ _ _ _ _ _ _ _~I_..( I
J"I- th
:
~
ta-H
r - -
'-_
~tdiS~Z
2nd byte of
TLC1205
COMMAND TO CALIBRATE
7 CAPACITORS & OFFSET
(REQUIRES 105 CLOCK CYCLES)
FIGURE 4. MODE 2 TIMING DIAGRAM
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2-188
Read 2nd byte
of TLC1205
.
TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
PRODUCT
PREVIEW
TLC1205A, TLC1205B, TLC1225A, TLC1225B
SELF·CALIBRATING 12·BIT·PLUS·SIGN UNIPOLAR OR BIPOLAR
.
ANALOG·TO·DIGITAL CONVERTERS
PARAMETER MEASUREMENT INFORMATIQN
•
DGTL
VCC
RD
GND
R D - i ¥ F V C C DATA
':" 1
OUTPUT
CL
':" RL
DGTL
-?f
...
---..JI=:::-50%
90%
UI
..
C3
·S
10%
u
~
tdiS
VOH----"'!!I 90 %
DATA OUTPUT
GND----
c
o
Vcc
-..:=
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,---t"--.. RL
-RD
':" J
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u
DATA
OUTPUT
CL
w
Mode 1
a:
a..
The conversion sequence is initiated when CS and WR are both low.
I-
Mode 2
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C
o
The writing of the conversion command word to the six least significant bits of the data bus, when either
CS or WR goes high, initiates the conversion sequence.
oa:
a..
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-189
TLC1205A,TLC1205B, TLC1225A, TLC1225B
SELF·CALIBRATING 12·BIT·PLUS·SIGN UNIPOLAR OR BIPOLAR
ANALOG·TO·DIGITAL CONVERTERS
PRODUCT
.PREVIEW
analog sampling sequence
Mode 1
Sampling of the input signal occurs during clock cycles 29 thru 35 of the conversion sequence.
c
Mode 2
;
Sampling of the input signal occurs during clock cycles 4 thru 10 of the conversion sequence.
l>
(')
.Q
completed
C
iii·
AID conversion
When INT goes low. conversion is complete and the AID result can be read. A new conversion can begin
immediately.
:=;:
o·::s
Mode 1
(')
The AID conversion is complete at the end of clock cycle 51 of the conversion sequence.
~r
c
;-
Mode. 2
The AID conversion is complete at the end of .clock cycle 26 of the conversion sequence.
aborting a conversion in process and beginning a new conversion
Mode 1 and Mode 2
If a conversion is initiated while a conversion sequence is in process. the ongoing conversion will be aborted
and a new conversion sequence will begin.
Mode 1
If the new conversion is started before the Analog Sampling begins (see Analog Sampling Sequence section
and the Mode 1 Timing Diagram). the particular internal capacitor that was being calibrated during the
aborted conversion sequence will be calibrated during the new conversion sequence. Otherwise. the next
internal capacitor will be calibrated during the new conversion sequence.
reading the conversion result
TLC1205
"'tIl
::D
oC
c:
(')
Upon activating the required control signals to read the conversion result or status information. the
appropriate pins are brought out of a high-impedance state and drive the, data bus with the proper
information. These pins are 012/07/0 through D8/DOIINT/DI0.
If STATUS. CS. and RD are all low. status information can be read. The format of the conversion result
and status information and the respective pins for output are presented in Table 1.
-t
"'tIl
::D
m
S
m
~
2-190
TEXAS
..If
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS. TEXAS 75265
PRODUCT
PREVIEW
TLC1205A. TLC1205B. TLC1225A. TLC1225B
SELF·CALIBRATING 12·BIT·PLUS·SIGN UNIPOLAR OR BIPOLAR
ANALOG· TO·DIGITAL CONVERTERS
TABLE 1
•
1/0 BUS
BYTES
MSB
LSB
STATUS
STATUS
CS
RO
0121
071
0
0121
061
SARS
0121
051
01
0121
041
01
0111
031
01
0101
021
BYSTI
091
011
EOCI
081
001
INTI
012
06
015
012
05
014
012
04
013
011
03
012
010
02
011
09
01
010
DB
DO
SARS
L
L
L
BYST
EOC
INT
H
H
L
L
H
012
07
L
L
L
L
L
.f!
'5
~
U
c:
o
'iii
'5
The status information is described in Table 2.
'~
TABLE 2
0"
STATUS
BIT DESCRIPTION
BIT
L
()
TO CLEAR BIT
w
f
tU
:::J
o
o
a:
Q.
. TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2-191
TLC1205A, TLC1205~ TLC1225A, TLC1225B
SELF·CALIBRATING 12·BIT·PLUS·SIGN UNIPOLAR OR BIPOLAR
ANALOG·TO·DlGITAL CONVERTERS
PRODUCT
PREVIEW
general
II
reset INT
When reading the conversion data, the falling edge of the first low-going combination of CS and RD will
reset INT. The falling edge of the low-going combination of CS and WR will also reset INT.
...C
ready out
n
l>
For high-speed microprocessors, READY OUT allows the TLC1205 and the TLC1225 to insert a wait state
in the microprocessor's read cycle.
iii'
c
status write (TLC1205)
0'
A status write resets the internal logic and status bits and aborts any conversion in process. A status write
occurs when CS, WR, and STATUS are taken low.
III
III
.Q
;::;"
:::l
(")
:::;'
n
reference voltage (V ref)
c
This voltage defines the range for I VI + - VI_I. When I VI + - VI_I equals Vref, the highest conversion
data value results. When I VI + - VI_ I equals 0, the conversion data "alue is zero. Thus, for a given
input, the conversion data changes ratiometrically with changes in V ref.
;::;"
en
Vos
This pin is a digital input and is used to select Mode 1 or Mode 2 operation. A logic low selects Mode 1;
a logic high selects Mode 2.
In Mode 1, the ICs are true replacements for National Semiconductor's ADC1205 and ADC1225. The
ADC 1205 and ADC 1225 use the vas pin to adjust zero error. Since the zero error adjustment voltage
is below the TLC1205's and TLC1225's maximum acceptable level for a logic low signal, the TLC1205
and TLC12251Cs are true replacements. Even in Mode 1, the TLC1205's and TLC1225's converted data
can be read earlier than the ADC1205's and ADC1225's.
calibration and conversion considerations
Mode 1
Calibration of the seven internal capacitors is an integral part of the AID conversion. One of the seven
internal capacitors is calibrated during the first part of the conversion sequence. For example, one of the
capacitors is calibrated during the first conversion. The next capacitor is calibrated during the second
conversion. After seven conversions, the pattern for calibrating the internal capacitors repeats. A conversion
sequence requires 51 clock cycles.
""C
:::0
o
C
c:
(')
-i
""C
:::0
m
~
m
:E
2-192
A conversion is initiated by the low-going combination of CS and WR. The conversion sequence is
illustrated in the Mode 1 timing diagram.
Mode 2
Calibration of the internal capacitor and AID conversion are two separate actions. Each action is
independently initiated. Mode 2 conversion is much faster than Mode 1, since Mode 2 conversion is not
accompanied by the calibration of internal capacitors. In Mode 2, a calibration command that calibrates
all seven internal capacitors is normally issued first. A conversion command then initiates the AID conversion
without calibrating the internal capacitors. Subsequent conversions can be performed by issuing additional
conversion commands. The calibration and conversion commands are totally independent from one another
and can be initiated in any order. Calibration and conversion commands require 105 and 26 clock cycles,
respectively.
TEXAS
.-1.!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
PRODUCT
PREVIEW
TLC1205A, TLC1205B, TLC1225A, TLC1225B
SELF-CALIBRATING 12-BIT-PLUS-SIGN UNIPOLAR OR BIPOLAR
ANALOG-TO-DiGITAL CONVERTERS
The calibrate and conversion commands are initiated by writing control words on the six least significant
bits of the data bus. These control words are written into the IC when either CS or WR goes high. The
initiation of these commands is illustrated in the Mode 2 Timing Diagram. The bit patterns for the commands
are shown in Table 3.
TABLE 3. MODE 2 CONVERSION COMMANDS
COMMAND
CS
Conversion
Calibrate t
+ WR
t
t
015
H
014
L
L
X
I/O BUS
013 012
Required number
011
X
X
X
010
L
L
L
L
L
of clock cycles
26
105
•
tCalibration is lost when clock is stopped.
analog inputs
differential inputs provide common mode rejection
The differential inputs reduce common-mode noise. Common-mode noise is noise common to both IN +
and IN - inputs, such as 60-Hz noise. There is no time interval between the sampling of the IN + and INso these inputs are truly differential. Thus, no conversion errors result from a time interval between the
sampling of the IN + and IN - inputs.
input bypass capacitors
Input bypass capacitors may be used for noise filtering. However, the charge on these bypass capacitors
will be depleted during the input sampling sequence when the internal sampling capacitors are charged.
Note that the charging of the bypass capacitors through the differential source resistances must keep pace
with the charge depletion of the bypass capacitors during the input sampling sequence. Note that higher
source resistances reduce the amount of charging current for the bypass capacitors. Also, note that fast,
successive conversion will have the greatest charge depletion effect on the bypass capacitors. Therefore,
the above phenomenon becomes more significant as source resistances and the conversion rate (i.e., higher
clock frequency and conversion initiation rate) increase.
In addition, if the above phenomenon prevents the bypass capacitors from fully charging between
conversions, voltage drops across the source resistances will result due to the ongoing bypass capacitor
charging currents. The voltage drops will cause a conversion error. Also, the voltage drops increase with
higher IVI + - VI_ I values, higher source resistances, and lower charge on the bypass capacitors
(i.e., faster conversion rate).
For low-source-resistance applications (Rsource < 100 m, a 0.001-JLF bypass capacitor at the inputs will
prevent pickup due to the series lead inductance of a long wire. A 100-ohm resistor can be placed between
the capacitor and the output of an operational amplifier to isolate the capacitor from the operational amplifier.
input leads
The input leads should be kept as short as possible, since the coupling of noise and digital clock signals
to the inputs can cause errors.
power supply considerations
Noise spikes on the VCC lines can cause conversion error. Low-inductance tantalum capacitors (> 1 JLF)
with short leads should be used to bypass ANLG VCC and DGTL Vcc. A separate regulator for the TLC1205
or TLC1225 and other analog circuitry will greatly reduce digital noise on the supply line.
~
w
:>w
a:
0..
IU
:::J
Q
o
a:
0..
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-193
•
TLC1205A. TLC1205B. TLC1225A. TLC1225B
SELF·CALIBRATING 12·BIT·PLUS·SIGN UNIPOLAR OR BIPOLAR
ANALOG· TO·DIGITAL CONVERTERS
PRODUCT
PREVIEW
positive and negative full·scale adjustment
unipolar inputs
Apply a differential input voltage that is 0.5 LSB below the desired amilog full-scale voltage (VFS) and
adjust the magnitude of the REF input so that the output code is just changing from 0 1111 1111 111 0
to 0 1111 1111 1111. If this transition is desired for a different input voltage, the reference voltage can
be adjusted accordingly.
bipolar Inputs
First, follow the procedure for the Unipolar case.
Second, apply a differential input voltage so that the digital output code is just changing from
1 000000000001 to 1 000000000000. Call this actual differential voltage Vx. The ideal differential
voltage for this transition is:
-VFS
+~
8192
(1 )
The difference between the actual and ideal differential voltages is:
Delta
= Vx
- (- VFS
+
~fI2)
(2)
Then apply a differential input voltage of:
Vx -
Delta
(3)
2
and adjust Vref so the digital output code is just changing from 1 000000000001 to 1 000000000000.
This procedure produces positive and negative full-scale transitions with symmetrical minimum error.
2-194
TEXAS
..If
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76266
PRODUCT
PREVIEW
TLC1205A, TLC1205B, TLC1225A, TLC1225B
SELF-CALIBRATING 12-BIT-PLUS-SIGN UNIPOLAR OR BIPOLAR
ANALOG-TO-DIGITAL CONVERTERS
TYPICAL APPLICATIONS
(4095) 0 1111 1111 1111
(4094) 0111111111110
w
7::://
(2) 0 0000 0000 0010
(1) 0 0000 0000 0001
(0) 0 0000 0000 0000
o
'-'
o
I::l
::l
""
"
""
~TIVE
OSITIVE
FULL-SCALE
TRANSITION
(/)
+-'
-:;
...
(.l
U
I:
o
-~
e: - Vref
o
~
1111111111111 (-1)
1111111111110 (-2)
.... "
+Vref
'iii
':;
C'
(.l
w
W
r-----<~DGTLGND
POWER GND ...._ _ _ _ _ _- '
A. The analog input must have some current return path to ANALOG GND.
B. Bypass capacitor leads must be as short as possible.
FIGURE 7. ANALOG CONSIDERATIONS
a:::
a..
IU
::l
C
oa:::
a..
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-195
TLC1205A, TLC1205B, TLC1225A, TLC1225B
SELF·CALIBRATING 12·BIT·PLUS·SIGN UNIPOLAR OR BIPOLAR
ANALOG· TO·DIGITAL CONVERTERS
PRODUCT
PREVIEW
4 k!l
VXDR
t:S=E=-E~NO:::T=E-=B-+--tIN(+)
ANLG VCC+
500!l
ZERO
ADJ
IN(-) SEE NOTE A
DGTL Vce
500 !l
TLC1205
TLS1225
t-......- . - -.. +
~
0.11'F
¥
10 I'F
t - - - -....- -..
+
0.1 I'F,..,...":, 10 "F rt"'":'_
3.9 k!l
..L..J.:"
1 k!l
t--~FS
ADJ
8.2 kll
"'tJ
:::D
o
NOTE:
C
c:
o
A. VI_ = 0.15 x ANLG Vee+.
B. 15% of ANALOG Vee s VXDR s B5% of ANALOG Vee·
FIGURE 9. OPERATING WITH RATIOMETRIC TRANSDUCERS
-I
"'tJ
:::D
m
S
.m
~
2-196
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TLC1540M, TLC15401, TLC1541M, TLC15411
LinCMOSTM 10-BIT ANALOG-TO-DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
02859, DECEMBER 1985-REViSED OCTOBER 1986
•
•
•
•
•
•
•
•
LinCMOS'" Technology
N DUAL-iN-LINE PACKAGE
(TOP VIEW)
1 O-Bit Resolution AID Converter
INPUT AD
INPUT A1
INPUT A2
INPUT A3
INPUT A4
INPUT A5
INPUT A6
INPUT A7
INPUT AS
GND
Microprocessor Peripheral or Stand-Alone
Operation
On-Chip 12-Channel Analog Multiplexer
Built-In Self-Test Mode
Software-Controllable Sample and Hold
Total Unadjusted Error . , .
TLC1540: ± 0.5 LSB Max
TLC1541: ±1.0 LSB Max
VCC
SYSTEM CLOCK
I/O CLOCK
ADDRESS INPUT
DATA OUT
CS
REF+
REFINPUT A1D
INPUT A9
....!II
..
U
'S
u
c
o
~
'iii
'S
Pinout and Control Signals Compatible with
TLC540 and TLC549 Families of 8-Bit AID
Converters
cr
FN CHIP CARRIER PACKAGE
(TOP VIEW)
u
c(
....COCO
TYPICAL PERFORMANCE
Channel Acquisition Sample Time
Conversion Time
Samples per Second
Power Dissipation
5.5
C
~s
21 ~s
32 x 103
6mW
3
description
2 1 20 19
18 I/O CLOCK
17
ADDRESS INPUT
The TLC1540 and TLC1541 are LinCMOSm AID
16
DATA OUT
6
peripherals built around an 10-bit switched15 CS
7
capacitor successive-approximation AID
14 REF+
8
converter. They are designed for serial interface
9 1011 12 13
to a microprocessor or peripheral via a threestate output with up to four control inputs
[including independent System Clock, I/O Clock,
Chip Select (CS)' and Address InputJ. A
2.1-megahertz system clock for the TLC 1540
and TLC 1541, with a design that includes
simultaneous readlwrite operation, allows highspeed data transfers and sample rates of up to
32,258 samples per second. In addition to the
high-speed converter and versatile control logic, there is an on-chip 12-channel analog multiplexer that
can be used to sample anyone of 11 inputs or an internal "self-test" voltage, and a sample-and-hold that
can operate automatically or under microprocessor control. Detailed information on interfacing to most
popular microprocessors is readily available from the factory.
INPUT
INPUT
INPUT
INPUT
INPUT
A3
A4
A5
A6
A7
4
5
The converters incorporated in the TLC 1540 and TLC1541 feature differential high-impedance reference
inputs that facilitate ratiometric conversion, scaling, and analog circuitry isolation from logic and supply
noises. A totally switched-capacitor design allows guaranteed low-error conversion (±0.5 LSB for the
TLC 1540, ± 1 LSB for the TLC1541) in 21 microseconds over the full operating temperature range.
The TLC1540 and the TLC1541 are available in both the Nand FN plastic packages, The M-suffix versions
are characterized for operation from - 55°C to 125°C. The I-suffix versions are characterized for operation
from - 40°C to 85 °C,
LinCMOS is a trademark of Texas Instruments Incorporated
This document contains information on products in
more thaD Dna phase of development. The status of
each daviee is indicated on the'paga(s) specifying its
electrical characteristics.
.Jf
INSTRUMENTS
TEXAS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1985, Texas Instrliments Incorporated
2-197
TLC1540M, TLC15401, TLC1541 M, TLC15411
LinCMOS1M 10·BIT ANALOG·TO·DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
functional block diagram
REF+
---
(-
11II1-
ANALOG
INPUTS
-
N
1I-
1L..-;
t
+
SAMPLE
AND
HOLD
100BIT
ANALOG·TO·DIGITAL
CONVERTER
(SWITCHED·CAPACITORS)
-
12-CHANNEL
ANALOG
MULTIPLEXER
I-
REF-
10
I
OUTPUT
DATA
REGISTER
INPUT
ADDRESS
REGISTER
10·To-l DATA ,~
DATA
SELECTOR AND
OUTPUT
DRIVER
10
4
Y
4
SELF.TEST·I
REFERENCE
I INPUT I
LMULTIPLEXER I
ADORESS
INPUT
2
CONTROL LOGIC
AND I/O
COUNTERS
±
I/O
CLOCK
Ci
SYST EM
CLOCK
operating sequence
II.
I/O
CLOCK--{
I
DON'T~
'==--=~"I~'=:::;"~o~n.:-----+t
-
I
MSS
I4--: AC CESS----':
~~ I
~',
~~
L.f_r"'ISoe=No=,.,.,C"'I-----------.J
'wHICSI
LSD
I2 I3 I4 I5 I6 I
1
CYCLEC
I
7
I 8 I 9 I I.
l+-- SAMPLE ~
I
CVCLEC
I
MSS
ADDRESS----7~'---------O::;O::;N:.·T:....:::CA:::R.:.:E:...-_.,J.---{ ",=~,=-
I
~
LSB
DON'T CARE
~~
INPUT
HI·ZSTATE
+--MSS
A9
PREVIOUSCONYERSION DATA-------+
LSS MSa
ISaeNoteBI
NOTES:
f!..
The conversion cycle, which requires 44 System Clock periods. is initiated on the 10th falling edge of the I/O Clock. after
CS. goes low-for the channel whose address exists in memory at that time. (f CS is kept low during conversion, the I/O Clock
must remain low for at least 44 System Clock cycles to allow conversion to be completed.
B. The most significant bit IMSB) will automatically be placed on the DATA OUT bus after CS is brought low. The remaining
nine bits IAB-AO) will be clocked out on the first nine I/O Clock falling edges.
C. To minimize errors caused by noise at the CS input, the internal circuitry waits for three System Clock cycles lor less) after
a chip-select falling edge is detected before responding to control input signals. Therefore. no attempt should be made to
clock-in address data until the minimum chip-select setup time has elapsed.
2·198
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76266
I
TLC1540M, TLC15401, TLC1541M, TLC15411
LinCMOSTM 10·BIT ANALOG·TO·DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) ............................................. 6.5 V
Input voltage range (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to VCC + 0.3 V
Output voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to VCC + 0.3 V
Peak input current range (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 10 mA
Peak total input current (all inputs) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 30 mA
Operating free-air temperature range: TLC15401, TLC15411 . . . . . . . . . . . . . . . . .. -40°C to 85°C
TLC1540M, TLC1541M ... '" ......... -55°C to 125°C
Storage temperature range ......................................... - 65°C to 150°C
Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: N package. . . . . . . . .. 260°C
•
!!
'S
...
o
(,)
c
o
'';:;
'iii
NOTE 1: All voltage values are with respect to digital ground with REF - and GND wired together (unless otherwise natedl.
'S
recommended operating conditions
C'
(,)
TLC1540, TLC1541
Supply voltage, VCC
MIN
NOM
MAX
4.75
5
5.5
UNIT
Positive reference voltage, VREF + Isee Note 21
2.5
Negative reference voltage, VREF _ (see Note 2)
0.1
VCC
0
VCC+O.1
2.5
1
VCC
VCC+O.2
V
VREF _ (see Note 21
0
High-level control input voltage, V,H
VCC
0.8
Low-level control input voltage, V,L
Q
V
V
V
2
V
ns
400
Setup time, address bits before I/O CLK1, tsu(AI
Hold time. address bits after I/O CLK1, th(AI
...
V
V
Differential reference voltage, VREF +
Analog input voltage (see Note 21
s
>
ns
30
1048 kHz
20
1048 kHz
100
525 kHz
Operating free-air
fCLK(I/OI
525 kHz
TLC1540M, TLC1541 M
temperature, TA
TLC1540l, TLC15411
40
55
125
-40
85
ns
ns
·C
NOTES: 2. Analog input voltages greater than that applied to REF + convert as all "1"s (111111111, while input voltages less than that
applied to REF - convert as all "O"s (000000001. For proper operation, REF + voltage must be at least 1 volt higher than
REF - voltage. Also, the total unadjusted error may increase as this differential reference voltage falls below 4.75 volts.
3. To minimize errors caused by noise at the chip select input, the internal circuitry waits for three System Clock cycles lor lessl
after a chip select falling edge is detected before responding to control input signals. Therefore, no attempt should be made
to clock-in an address until the minimum chip select setup time has elapsed.
4. This is the time required for the clock input signal to fall from V,H min to V,L max or to rise from V,L max to V,H min. In
the vicinity of normal room temperature, the devices function with input clock transition time as slow as 2 microseconds
for remote data acquisition applications where the sensor and the AID converter are placed several feet away from the controlling
microprocessor.
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-199
TLC1540M, TLC15401, TLC1541M, TLC1541J
LinCMOSTM 10·81T ANALOG·TO·DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
PRODUCT
PREVIEW
electrical characteristics over recommended operating temperature range, VCC .. VREF +
III
4.75 V to 5.5 V (unless otherwise noted), fCLK(IIO) .. 1.1 MHz, fCLK(SYS) .. 2.1 MHz
PARAMETER
TEST CONDITIONS
....
102
»
IIH
High-level input current
IlL
Low-level input current
= 4.75
Vee = 4.75
Va = Vee,
Va = 0,
VI = Vee
VI = 0
lee
Operating supply current
CS
C
DI
DI
(')
.c
c
VOH
High-level output voltage (pin 16)
VOL
Low-level output voltage
Vee
Off-state (high-impedance state)
output current
iii'
V,
10H
V,
10L
;::;"
es at Vee
10
es at Vee
-10
:::J
n::::;'
Unselected channel at Vee
c
;::;"
til
lee + 'REF Supply and reference current
I Analog inputs
Input capacitance
I eontrol inputs
VREF+
=
~A
0.005
2.5
~A
-2.5
~A
1.2
2.5
mA
0.4
1
-0.4
-1
~A
f
es at 0 V
Vee,
V
-0.005
at 0 V
Selected channel at 0 V
UNIT
V
0.4
Unselected channel at 0 V
Selected channel leakage current
MAX
2.4
Selected channel at Vee,
0'
(')
Typt
MIN
= 360 ~A
= 3.2 mA
ei
1.3
3
7
55
5
15
mA
pF
operating characteristics over recommended operating free-air temperature range,
VCC .. VREF+ .. 4,75 V to 5.5 V, fCLKII/O) .. 1.1 MHz, fCLK(SYS) .. 2.1 MHz
PARAMETER
teonv
TLC1540
MIN
MAX
UNIT
linearity error
See Note 5
±0.5
LSB
Zero error
See Notes 2 and 6
±0.5
LSB
Full-scale error
See Notes 2 and 6
±0.5
LSB
Total unadjusted error
See Note 7
±0.5
LSB
Self-test output code
Input A 11 address
Conversion time
See Operating Sequence
21
~s
See Operating Sequence
31
~s
See Operating Sequence
6
Total access and
conversion time
Channel acquisition time
tacq
TEST CONDITIONS
(sample cycle)
=
1011 (See Note 8)
0111110100
(500)
1000001100
(524)
1/0
clock
cycles
Time output data
tv
remains valid after
10
ns
1/0 clock<
"'0
::D
oC
C
o
-f
"'0
::D
:::mm
=:
td
Delay time, liO clock.
to data output valid
ten
Output enable time
tdis
Output disable time
tr(bus) Data bus rise time
tf(bus) Oata bus fall time
400
I
See Parameter
Measurement
Information
ns
150
ns
150
ns
300
ns
300
ns
t All typical values are at Vee = 5 V, TA = 25°e.
NOTES: 2. Analog input voltages greater than that applied to REF + convert to all "1 "s (11111111), while input voltages less than that
applied to REF - convert to all"O"s (00000000), For proper operation, REF + voltage must be at least 1 volt higher than
REF - voltage. Also, the total unadjusted error may increase as this differential reference voltage falls below 4.75 volts.
5. Linearity error is the maximum deviation from the best straight line through the AID transfer characteristics.
6. Zero error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
7. Total unadjusted error comprises'linearity, zero, and full-scale errors.
8. Both the input address and the output codes are expressed in positive logic. The A 11 analog input signal is internally generated
and is used for test purposes.
PRODUCT PREVIEW documents contein informetion
on products in the formative or dBsign @hase of
development. Characteristic data and other
2-200 specifications are duign goals. Taxas Instruments
reserves the right to change or discontinue thasa
products without notica.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
ADVANCE
INFORMATION
TLC1540M. TLC15401. TLC1541M. TLC15411
LinCMOSlM 10·81T ANALOG·TO·DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
electrical characteristics over recommended operating temperature range. VCC - VREF +
4.75 V to 5.5 V (unless otherwise noted). fCLKII/O) - 1.1 MHz. fCLK(SYS) - 2.1 MHz
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage (pin 16)
Vee - 4.75 V.
IOH - 360 p.A
VOL
Low-level output voltage
Vee - 4.75 V.
10L - 3.2 mA
Off-state (high-impedance state)
Vo
IO.z
IIH
Typt
MIN
10
Vo
0.005
0.005
2.5
p.A
1.2
2.5
mA
IlL
Low-level input current
ICC
Operating supply current
es at 0 V
Selected channel at Vee.
0.4
Unselected channel at 0 V
Selected channel leakage current
I
I
-0.4
=
'iii
'3
cr
~2
~
(SEE NOTE BI
'-s~
W~~:;~~M2
OO~ . 'f,':~M'"
UNDERTEST+
2AV
---------·O.8V
VOLTAGE WAVEFORM FOR DELAY TIME
VOLTAGE WAVEFORM FOR
RISE AND FALL TIMES
NOTES: A. CL = 50 pF
2
2-202
B. ten = tpZH or tPZL. tdis = tPHZ or tpLZ.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
ADVANCE
INFORMATION
TLC1540M, TLC15401, TLC1541M, TLC15411
LinCMOSTM 10·BIT ANALOG·TO·DIGITAL PERIPHERALS
WITH SERIAL CONTROL AND 11 INPUTS
principles of operation
The TLC 1 540 and TLC 1 541 are bath camplete data acquisitian systems an single chips. Each includes
such functians as sample-and-hald, 10-bit A/D canverter, data and cantral registers, and cantral lagic.
Far flexibility and access speed, there are faur cantral inputs; Chip Select ICS), Address Input,
I/O Clack, and System Clack. These cantral inputs and a TTL-campatible three-state autput are intended
far serial cammunicatians with a micrapracessar ar micracamputer. The TLC 1540 and TLC 1541 can
camplete canversians in a maximum af 21 micrasecands, while camplete input-canversian-autput cycles
can be repeated at a maximum af 31 micrasecands.
The System and I/O Clacks are narmally used independently and do. nat require any special speed ar phase
relatianships between them. This independence simplifies the hardware and saftware cantral tasks far
the device. Once a clack signal within the specificatian range is applied to. the System Clack input, the
cantral hardware and saftware need anly be cancerned with addressing the desired ana lag channel, reading
the previaus canversian result, and starting the canversian by using the I/O Clack. The System Clack will
drive the "canversian crunching" circuitry so. that the cantral hardware and saftware need nat be cancerned
with this task.
When CS is high, the Data Output pin is in a three-state canditian and the Address Input and I/O Clack
pins are disabled. This feature allaws each af these pins, with the exceptian af the CS pin, to. share a
cantral lagic paint with their caunterpart pins an additianal A/D devices when additianal TLC 1 540/1 541
devices are used. In this way, the abave feature serves to. minimize the required cantral lagic pins when
using mUltiple A/D devices.
•..
!II
'5
...
u
(3
C
o
-.=
'iii
'5
C'
u
c
~2
om
;2
'TI
o::IJ
3:
~
S
2
2-204
TEXAS ..,
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TLC4016M, TLC40161
SILICON-GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
JANUARY 1986
•
TLC4016M ... J OR N PACKAGE
TLC40161 ... D OR N PACKAGE
High Degree of Linearity
•
High On-Off Output Voltage Ratio
•
Low Crosstalk Between Switches
•
Low On-State Impedance of 50 Ohms Typ
at VCC = 9 V
•
Individual Switch Controls
•
Extremely Low Input Current
ITOPVIEWI
1A
18
28
2A
2C
3C
GND
VCC
1C
4C
4A
48
38
3A
..
en
-5
...
u
C3
c
0
description
The TLC4016 is a silicon-gate CMOS quadruple
analog switch integrated circuit designed to
handle both analog and digital signals. Each
switch permits signals with amplitudes up to
12 volts peak to be transmitted in either
direction.
logic symbol t
lC
151
2C
2A 141
3C
3A
4C
4A
-;;
1131
lA 111
Each switch section has its own enable input
control. A high-level voltage applied to this
control terminal turns on the associated switch
section.
Applications include signal gating, chopping,
modulation or demodulation (modem), and signal
multiplexing for analog-to-digital and digital-toanalog conversion systems.
~
'"'
161
181
XI
1
()
1
121
n
n
131
n
n
191
1121
'"'
1111 ()
1101
'5
C"
U
lB
«
..
as
2B
as
C
3B
4B
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 61 7-12.
The TLC4016M is characterized for operation
from - 55°C to 125°C, and the TLC40161 is
characterized from -40°C to 85°C.
logic diagram (positive logic)
A
8
C
PRODUCTIOI DATA dooumonts oolllai. i.fermatlo.
ourront os of publi..tio. dolo. Produots conform to
specifications por tho Iorms of To..s lostrumanto
1: . ~::::~i:r &!:o::;:::~:'.~ .ot
=:::1;01:
Copyright @ 1986, Texas Instruments Incorporated
TEXAS ",
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-205
TLC4016M, TLC40161
SILlCON,GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range (see Note 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.5 V to 15 V
Control-input diode current (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
1/0 port diode current (VI < 0 or VI/O > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 mA
On-state switch current (VI/O = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±25 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
D package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 950 mW
J package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .. 875 mW
Operating free-air temperature, T A: TLC4016M .......................... - 55°C to 125°C
TLC40161 ............................ -40°C to 85°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D and N packages ....... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............. 300°C
C
I»
;
l>
()
.Q
C
iii'
::+"
0'
::::J
o
~r
c
NOTES:
::;o'
en
1. All voltages are with respect to ground unless otherwise specified.
2. For operation above 25 0 C free-air temperature, see Dissipation De~ating Table.
DISSIPATION DERATING TABLE
Maximum Power Dissipation
B50C
125°C
Package
25°C
950mW
1025 mW
875 mW
D
J
N
494mW
533 mW
455 mW
205 mW
175mW
Derating
Factor
7.6 mw/oe
8.2 mw/oe
7.0 mw/oe
recommended operating conditions
Supply voltage. Vee
I/O port voltage. VI/O
High-level input voltage. VIH
Low-level input voltage. VIL
Input rise time, tr
Vee = 9 V
Vce = 12 V
MAX
5
12
V
Vee
V
6.3
8.4
0
0
Vee - 2 V
Vee = 4.5 V
Vee - 9 V
Vce- 12V
=
=
NOM
2t
0
1.5
3.15
Vee - 2 V
Vee - 4.5V
Vee
Vee
MIN
0
0
Operati.ng free-air temperature, T A
Vec
0.3
0.9
1.8
2.4
V
V
1000
2 V
4.5 V
Vee = 9 V
Input fall time. tf
Vce
Vee
Vce
UNIT
Vee = 2 V
Vee = 4.5 V
Vee - 9 V
TLe4016M
TLe40161
-55
-40
500
400
1000
no
500
400
125
ns
85
°e
tWith supply voltages at or near 2 volts, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital
signals be transmitted at these low supply voltages.
2-206
.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TLC4016M. TLC40161
SILICON-GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted).
PARAMETER
= 1 rnA,
VA = 0 to Vee,
4.5 V
100
220
100
200
9V
50
120
50
105
See Figure 1
On-state switch
resistance
= 1 rnA,
VA = 0 or Vee,
IS
See Figure 1
VA = OtaVee,
See Figure 1
On-state switch
resistance matching
VI
II
Control input current
ISan
lee
ei
0 or Vee
=
Vs = ±Vee,
See Figure 2
On-state switch
VA = 0 or Vee,
See Figure 3
-
leakage current
VI
Supply current
Input capacitance
capacitance
10
=0
=0
A or B
e
A·ta B
VI
=0
MIN
or Vee,
MIN
12 V
30
100
30
85
2V
120
240
120
215
4.5 V
50
120
50
100
9V
35
80
35
75
12 V
20
70
20
60
4.5 V
10
20
10
20
9V
5
15
5
15
12 V
5
15
5
15
2V
±1
±1
±0.1
±O.l
to
UNIT
5.5 V
±10
±600
±10
±600
9V
12 V
±15
±800
±15
±800
±20 ±1000
±20 ± 1000
5.5 V
±10
±150
±10
± 150
9V
±15
±200
±15
±200
12 V
±20
±300
±20
±300
5.5 V
2
40
2
20
9V
8
160
8
80
12 V
16
320
16
160
2 V to
15
12 V
5
2 V to
12 V
5
15
10
5
5
10
•
II)
,t=
!l
.=
u
U
c
o
';l
!l
'iii
'S
cr
u
pA
6V
25°e
Off-state switch
leakage current
Feedthraugh
ef
=
VI - 0 or Vee,
TA
ISaff
TLC40161
TVpt
MAX
VCC
IS
rSon
TLC4016M
TVpt
MAX
TEST CONDITIONS
nA
II(
...
CO
CO
Q
nA
pA
pF
pF
t All typical values are at T A "" 25°e.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75265
2-207
TLC4016M, TLC40161
SILICON-GATE
BILATERAL ANALOG SWITCH
. . CMOS QUADRUPLE
.
$witching charact~ri$tic$ over recommended operating free-air temperature range, CL - 50 pF lunle$$
otherwi$8 noted)
TEU CONDITION$
PARAMETER
tpd
Propagation delay time,
AtoBorBtoA
VCC
2V
4.5 V
9V
See Figure 4
TLC4016M
MIN TYpt
MAX
25
75
12 V
2V
ton
RL = 1 kG,
See Figures 5 and 6
Switch turn-on time
RL = 1 kG,
See Figures 5 and 6
toff
Switch turn-off time
fco
Switch cutoff frequency
(channel loss = 3 dB)
VOCF(PP)
4.5V
9V
12 V
2V
4.5 V
9V
attenuation between any two
See Figure 7
4.5 V
See Figure 8
4.5 V
15
14
13
150
8
30
18
6
5
45
15
10
12 V
4.5 V
9V
Control feedthrough voltage
to a~y switch, peak to peak
Frequency at which crosstalk
5
4
3
32
8
100
TLC40161
MIN Typt
MAX
25
62
5
13
4
12
11
3
125
32
15
252
54
48
45
120
1
PARAMETER MEASUREMENT INFORMATION
VCC
C XI
TE$T
SWITCH
I
B
FIGURE 1. ON·STATE RESISTANCE TEST CIRCUIT
VCC
VI - 0
C XI
TEU
B
SWITCH
V$ - VA - VB
CONDITION I: VA - O. VB - VCC
CONDITION 2: VA - VCC. VB - 0
FIGURE 2. OFF·STATE SWITCH LEAKAGE CURRENT TEST CIRCUIT
2·208
TEXAS
8
100
180
t All typical values are at T A = 25°C.
A I
6
5
45
15
10
,e,
INSTRUMENTS
POST OFFICE Bf;)X 656012 • DALLAS, TeXAS 75266
25
15
13
210
45
40
38
180
1
ns
ns
ns
MHz
120
switches equals 50 dB
VI - VCC
8
UNIT
mV
MHz
TLC4016M, TLC40161
SILlCON·GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
PARAMETER MEASUREMENT INFORMATION
•
VCC
C
VI - VIH
Xl
A 1
B
TEST
SWITCH
~
...U=
.".
U
..,o
c
FIGURE 3. ON·STATE SWITCH LEAKAGE CURRENT TEST CIRCUIT
';;
'S
tr
VCC
VI
~
C Xl
VI - VIH
TEST
SWITCH
J"B;;.:O;;,,:R...:..;A..-VO
'-----_.....
A OR B 1
~50PF
...
lIS
lIS
Q
TEST CIRCUIT
A~~B
__________
J~rO-%----------~~~"_-__-_-__-_-_::
I
I
I
I
~ tpd
B~~A
tpd--lI4+-~.1
I
I
______________
J~~'
I
I
~~~"
VOLTAGE WAVEFORMS
FIGURE 4. PROPAGATION DELAY TIME. SIGNAL INPUT TO SIGNAL OUTPUT
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2·209
TLC4016M, TLC40161
SILlCON·GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
PARAMETER MEASUREMENT INFORMATION
•
VCC
C
V,
...
I»
I»
C Xl
A
Ic
1 kll
TEST
SWl'rCH
11 OF 41
-=
':'
B
Vo
J
50PF
TEST CIRCUIT
fij'
;:;:
0'
;.,..o%---------------"'"'\\,~
:::I
n
~r
c
_ _-.J
;::;:
I
14
en
---n
I
~
ton - tpZL
\~.
tott - tpLZ
14
Vo
\
....._ _ _ _ _ _ _ _ _ _ _ _ _ _ _
OV
!/"
~}10~
TEXAS .."
POST OFFICE BOX 655012 • DAllAS. TEXAS 75265
'V"
_ _ --VOL
VOLTAGE WAVEFORMS
INSTRUMENTS
-V"
~I
FIGURE 5. SWITCHING TIME (tPZL. tPLZ). CONTROL TO SIGNAL OUTPUT
2-210
-
TLC4016M, TLC40161
SILlCON·GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
PARAMETER MEASUREMENT INFORMATION
VCC
C Xl
TEST'
SWITCH
(1 OF 4)
A
..
rn
I-'B-._-.....50pF
·S
VO
e
lkO
C3
c
o
+=
'iii
·S
TEST CIRCUIT
- - -.......
VCC
VI _ _ _
--J{~ ___"
V
I
!
as
Q
---i
I
I
~~C.l,O%
c(
toff-tpHZ~
= tPZH
I
VO _ _ _ _ _ _
C'
CJ
------VCC
r\.o%_____ o
I
I4--+t- ton
-
VOH
_____
~
9 0%- --VOH
OV
,
'-=OV
VOLTAGE WAVEFORMS
FIGURE 6, SWITCHING TIME (tPZH. tPHZI. CONTROL TO SIGNAL OUTPUT
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2·211
TLC4016M, TLC40161
SILlCON·GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
PARAMETER MEASUREMENT INFORMATION
VCC
X1
TEST
SWITCH
11 OF 41
1-.....----4.-VO
150 pF -=600 Il
TEST CIRCUIT
·c------r
Vo-------t __________ ~~ _______ ~ocr
VOLTAGE WAVEFORMS
FIGURE 7. CONTROL FEEDTHROUGH VOLTAGE
VCC
X1
VI
X2
600 Il
2
TEST
SWITCH
11 OF 4)
TEST
SWITCH
11 OF 4)
V01
':'
2
V02
J
6000
50PF
':'
':'
NOTE: ADJUST I lor ax -
V02
':'
- 50 dB.
V01
FIGURE 8. CROSSTALK 8ETWEEN ANY TWO SWITCHES, TEST CIRCUIT
2-212
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 8&6012 • D"LL"S. TEX"S 76285
TLC4066M, TLC40661
SILlCON·GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
02922, JANUARY 1986
•
High Degree of Linearity
•
High On·Off Output Voltage Ratio
TLC4066M ... J OR N PACKAGE
TLC40661 ... D OR N PACKAGE
(TOP VIEW)
•
Low Crosstalk Between Switches
•
Low On·State Impedance ... Typically
30 Ohms at VCC - 12 V
•
Individual Switch Controls
•
Extremely Low Input Current
•
Functionally Interchangeable with National
Semiconductor MM54/74HC4066, Motorola
MC54/74HC4066, and RCA CD4066A
lA
18
28
2A
2C
3C
GND
lC
4C
4A
48
38
3A
en
'5
..
u
C3
c
,8
logic symbol t
lC
lA
2C
2A
3C
3A
4C
4A
description
The TLC4066 is a silicon-gate CMOS quadruple
analog switch integrated circuit designed to
handle both analog and digital signals. Each
switch permits signals with amplitudes up to
12 volts peak to be transmitted in either
direction.
Each switch section has its own enable input
control. A high-level voltage applied to this
control terminal turns on the associated switch
section.
•..
VCC
'in
(13)
(1)
(5)
(4)
()
Xl
1
1
n
(6)
(81
(121
(111
Il
n
n
n
'5
(2)
(3)
n
(9)
()
(101
C'
U
18
..
VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... ± 20 mA
I/O port diode current (VI < 0 or Vila> VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
On-state switch current (Vila = 0 to Vcc) ................................... , ± 25 mA
Continuous current through VCC or GND pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
D package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 950 mW
J package. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 875 mW
Operating free-air temperature, T A: TLC4066M ..... . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
TLC40661 ............................ - 40°C to 85 °C
Storage temperature range ......................................... - 65°C to 1 50°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D and N packages. . . . .
260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............. 300°C
III
C
I»
I»
l>
n
.c
c
U;"
::+"
0"
:::I
(")
~"
c
NOTES:
::+"
1. All voltages are with respect to ground unless otherwise specified.
2. For operation above 25 °C free~air temperature, see Dissipation Derating Table.
en
DISSIPATION DERATING TABLE
Maximum Power Dissipation
Package
25°C
85°C
125°C
Derating
Factor
7.6 mw/oe
0
J
1025 mW
533 mW
205 mW
8.2 mw/oe
N
875 mW
455 mW
175 mW
7.0 mW/De
950 mW
494 mW
recommended operating conditions
Supply voltage, Vee
110 port voltage, VI/O
Vee
High-level input voltage, VIH
=
Vee
=
=
Low-level input voltage, VIL
Vee
=
=
Vee
Vee
Vee
Vee
Input fall time, tf
Operating free-air temperature, T A
Vee
=
=
=
=
=
12
V
0
Vee
v
Vee
Vee
9 V
6.3
Vee
12V
8.4
0
Vee
0.3
4.5 V
0
0.9
9 V
0
1.8
0
2.4
Vee - 12V
Input rise time, tr
MAX
5
1.5
Vee - 2 V
Vee
NOM
2t
3.15
2 V
Vee - 4.5 V
Vee
MIN
UNIT
V
V
1000
2 V
4.5 V
500
9 V
400
2 V
1000
500
4.5 V
ns
ns
400
Vee - 9 V
TLe4066M
-55
125
TLe40661
-40
85
De
tWith supply voltages at or near 2 volts, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital
signals be transmitted at these low supply voltages.
2-214
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TLC4066M, TLC40661
SILlCON·GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
electrical characteristics over recommended operating' free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
IS
VA
See Figure 1
On-state switch
rSon
= 1 rnA,
= OtoVee,
resistance
IS
= 1 rnA,
VA = 0 or Vee,
See Figure 1
resistance matching
VA = 0 to Vee,
See Figure 1
Control input current
VI
On-state switch
VCC
MIN
TlC4066M
Typt
MAX
TlC40661
Typt
MAX
MIN
4.5 V
100
220
100
200
9V
12 V
50
30
110
105
90
50
30
2V
120
240
120
215
4.5 V
50
120
50
100
9V
35
BO
35
75
12 V
20
70
20
60
4.5 V
10
20
10
20
9V
5
5
15
12 V
5
15
15
5
15
UNIT
85
!l
•
!l
2V
II
= 0 or Vee
or
±1
±1
~A
6V
15011
ISon
lee
ei
ef
5.5 V
Off·state switch
Vs
leakage current
See Figure 2
On-state switch
VA = 0 or Vee,
See Figure 3
leakage current
Feedthrough
capacitance
9V
12 V
= 0 or Vee,
10 = 0
VI
Supply current
Input capacitance
= ±Vee,
A or B
e
A to B
VI
=0
±10
±600
±15 ±BOO
±20 ±1000
±10
±600
±15 ±800
±20 ± 1000
5.5 V
±10
±150
±10
±150
9V
±15
±200
±15
±200
12 V
±20
±300
±20
±300
5.5 V
2
40
2
20
9V
B
160
80
12 V
16
320
B
16
2 V to
15
12 V
5
2 V to
12 V
5
5
5
nA
~A
160
15
10
nA
10
pF
pF
t All typical values are at T A = 25°e.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-215
•
TLC4066M, TLC40661
SILlCON·GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
switching characteristics over recommended operating free-air temperature range, CL - 50 pF (unless
otherwise noted)
.
PARAMETER
tpd
ton
toff
TEST CONDITIONS
Propagation delay time.
See Figure 4
AtoBorBtoA
RL = 1 kll. '
See Figures 5 and 6
Switch turn-on time
RL ='1 kll.
Switch turn-off time
See Figures 5 and 6
Switch cutoff frequency
fco
VOCFIPP)
Ichannel loss = 3 dB)
Control feedthrough voltage
to any switch, peak to peak
Frequency at which crosstalk
attenuation between any two
VCC
MIN
TLC4066M
TYpt MAX
2V
4.5 V
9V
12 V
2V
25
5
4
3
32
4.5 V
8
9V
12 V
6
5
45
15
10
2V
4.5 V
9V
12 V
8
100
120
4.5 V
9V
See Figure 7
4.5 V
See Figure 8
4.5 V
75
15
TLC40661
MIN Typt MAX
15
30
13
5
12
13
150
30
18
25
15
15
252
54
48
5
45
15
10
13
210
45
40
46
8
100
38
180
1
PARAMETER MEASUREMENT INFORMATION
VCC
C X1
TEST
SWITCH
1 B
4--ls
FIGURE 1_ ON-STATE RESISTANCE TEST CIRCUIT
VCC
VI - 0
C X1
TEST
SWITCH
B
Vs - VA - VB
CONDITION 1: VA - O. VB - VCC
CONDmON 2: VA - VCC. VB - 0
FIGURE 2. OFF-STATE SWITCH LEAKAGE CURRENT TEST CIRCUIT
2-216
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655.012 • DALLAS. TEXAS 75265
180
1
ns
ns
ns
MHz
120
t All typical values are at TA = 25 ·C.
A 1
10
11
125
6
switches equals 50 dB
VI - VCC
4
3
32
8
UNIT
mV
MHz
TLC4066M, TLC40661
SILlCON·GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH
PARAMETER MEASUREMENT INFORMATION
•..
VCC
C
VI - VIH
Xl
TEST
SWITCH
A 1
1 B
II)
"5
~
-=
VA
U
FIGURE 3. ON·STATE SWITCH LEAKAGE CURRENT TEST CIRCUIT
VI - VIH
VI
VCC
C'
TEST
SWITCH
n
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c
TEST CIRCUIT
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;::;:
o·
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(')
VI __________
~.
c
~10~%~~~9~0~%-----------~9~0%~~~~~.:~----~-----------:,
M-.I- tf
I4-*" t,
;::;:
C------f
fn
Vo---------t ___________ ~
n
_____
VOLTAGE WAVEFORMS
FIGURE 7. CONTROL FEEDTHROUGH VOLTAGE
VCC
X1
TEST
SWITCH
11 OF 4)
X2
TEST
SWITCH
11 OF 41
VI
6000
2
2
V02
6000
1 5 0 PF
'::'
NOTE: ADJUST f fo, aX -
V02
'::'
- 50 dB.
V01
FIGURE 8. CROSSTALK BETWEEN ANY TWO SWITCHES. TEST CIRCUIT
2-220
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
~1'"'
PRODUCT
PREVIEW
TLC7135
Advanced LinCMOSTM 4 1/2-OIGIT PRECISION
ANALOG-TO-DIGITAL CONVERTER
02851. DECEMBER 1986
N
•
ADVANCED LinCMOS'" Technology
•
Zero Reading for O-V Input
•
Precision Null Detection with True Polarity
at Zero
•
1-pA Typical Input Current
•
DUAL-IN-LiNE PACKAGE
ITOP VIEW)
•
True Differential Input
•
Multiplexed Binary-Coded-Decimal Output
•
Low Rollover Error: ± 1 Count Maximum
•
Control Signals Allow Interfacing with
UARTs or Microprocessors
•
Autoranging Capability with Over- and
Under-Range Signals
•
TTL-Compatible Outputs
•
VCCREF
ANlG COMMON
INT OUT
AUTO ZERO
BUFF OUT
CrefCref+
ININ+
VCC+
(MSD) D5
(lSB) B1
B2
UNDER-RANGE
OVER-RANGE
...
In
-5
RUN/HOLD
DGTl GND
POLARITY
ClK
BUSY
D1 (lSD)
D2
D3
D4
B8 (MSB)
B4
~
C3
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-iii
-5
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ADVANCED LinCMOS· is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW documents contain inf.rmation
on products i. the formative or design pha.. of
development. Characteristic data
an~
othar
:=i:.It::1
rrg~ d:i::a=:I~rT:i::~~:::~::'~
products without notice.
TEXAS ..,.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright @ 19~6, Texas Instruments Incorporated
2-221
TLC7135
Advanced LinCMOSTM 4 1/2·DI6IT PRECISION
ANALOG· TO· DIGITAL CONVERTER
PRODUCT
PREVIEW
functional block diagram
•
POLARITY 1231
FROM ANALOG
SECTION
POLARITY
FUp·FLOP
1201 D1 ILSSI}
1191 D2
DIGIT
ZERO
CROSS
DETECT
11S) D3
DRIVE
1171 D4
OUTPUT
1121 D61MSBI
CLK ..
12=21'--_ _ _ _~
RUN/iRH:6.:;;12;,;;5:...1- - - - - - 1 CONTROL
OVER.RANGE 1271
12::
8:..
1 - _....._ _-1
UNDER.RANOE.::
LOGIC
COUNTERS
MULTIPLEXER
-i
~~12~8~1_ _....._ _
8USy.::12:.:.1:..)_ _....._ _-1
DGTL
OND~12;:.:4~1- - - - - - i
1131 81 }
1141 B2
1161
B4
BINARY CODED
DECIMAL OUTPUT
(18) B8
ANALOG SECTION
(8)
r--REFI21
."
------,
I
I A/Z
~ I ~O--4
I
I
~T
C
I
I
(")
I
I
I
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-I
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m
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TO
IN+~o-----......+---.....---+-_~
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TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2-223
TLC7135
Advanced LinCMOS™ 4 1/2·DIGIT PRECISION
ANALOG· TO·DIGITAL CONVERTER
PRODUCT
PREVIEW
operating characteristics.VCC+ - 5 V. VCC- ... -5 V. Vref - 1 V. fclock - 120 kHz.
TA - 25°C (unless otherwise noted)
•
"'FS
PARAMETER
Full-scale temperature coefficient
(see Note 4)
TEST CONDITIONS
VID
=
2 V.
- 2 V :S VID :S 2 V
- 2 V :S VID :S 2 V
± Full-scale symmetry error (see Note 6)
(rollover error)
VID
=
±2 V
Display reading with O-V input
VID
Display reading in ratiometric operation
VID = Vref. TA = 25°C
OOC :S TA :S 70·C
O.
TVP
OOC :S TA :S 70°C
MAX
UNIT
5
ppm/DC
0.5
0.01
1
count
LSB
0.5
1
OOC :S TA :S 70°C
Linearity error
Differential linearity error (see Note 5)
=
MIN
I
-.0000
±.OOOO
+.9998
+ .. 9995
+.9999 +1.0000
+.9999 +1.0005
+.0000
count
Digital
Reading
Digital
Reading
NOTES: 4. This parameter is measured with an external reference having a temperature coefficient of less than 0.01 ppm/DC.
5. The magnitude of the difference between the worst case step of adjacent counts and ·the ideal step.
6. Rollover error is the difference between the absolute values of the conversion for 2 V and - 2 V .
."
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2-2?4
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
PRODUCT
PREVIEW
TLC7135
Advanced LinCMOS™ 4 1/2-DlGIT PRECISION
ANALOG-TO-DIGITAL CONVERTER
timing diagrams
. , , - END OF CONVERSION
BUSYtlL-r,~,___________________________________
•
...
II)
B1-BB
04
05
02
03
01
05
-S
...u
U
05
-.J1~4--~~~2c20rr1------------------Z20Ocol:~~---J~
I
I
L
COUNTS
04
COUNTS
---'r
_~~I_~
I...._ _ _ _
200 1'1
~
r-----,
COUNTS
I
03
200
COUNTS
-iii
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C"
~
...caca
Q
-i4!4t----...1
_ _--,
02 ___________________~r
200
c
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".;::l
~
_________
~141---~~
~_~
COUNTS
I
01 _ _ _ _ _ _ _ _~-'1
200
-i4~t---...1
COUNTS
t Delay between BUSY going low and the first STROBE pulse is dependent upon the analog input.
FIGURE 1
DIGIT SCAN ,..,
1""\
,..,
05
FOR OVER-RANGE I L--.-....I L..--...I L . - -
~04
~03
~02
~01
14
1000
.1
.
COUNTS
FIGURE 2
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:;:)
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TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-225
PRODUCT
PREVIEW
TLC7135
Advanced LinCMOS"" 4 1/2·DIGIT PRECISION
ANALOG·TO·DIGITAL CONVERTER
timing diagrams (continued)
INTEGRATOR
OUTPUT
11~:~-1 I :~~~: I OE-I::::~ATE
COUNTS
COUNTS
COUNTS MAX_
~ FULL MEASUREMENT CYCLE
40.002 COUNTS
~I
BUSY
OVER-RANGE _ _
WHEN APPLICABLE
UNDER-RANGE
WHEN APPl.lCABLE
~
~:lQQI:lQCQllalQCIL_ _ _ _ _ _ _ _ _-J
FIGURE 3
STJm1E
IIIII
.JlD4
It
--1l.;;.;D3~_ _ _~N
"'U
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tFirst D5
of AUTO ZERO and DE-INTEGRATE is one count longer.
FIGURE 4
-I
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~
2-226
TEXAS ~
INSTRUMENlS
POST OFFICE BOX 655012 .• DALLAS. TEXAS 76286
PRODUCT
PREVIEW
TLC7135·
Advanced LinCMOSTM 4 1/2·OIGIT PRECISION
ANALOG· TO·DIGITAL CONVERTER
PRINCIPLES OF OPERATION
A measurement cycle for the TLC7135 consists of the following four phases.
1.
2.
3.
4.
Auto-Zero Phase. The internal IN + and IN - inputs are disconnected from the pins and internally
connected to ANLG COMMON. The reference capacitor is charged to the reference voltage. The
system is configured in a closed loop and the auto·zero capacitor is charged to compensate for offset
voltages in the buffer amplifier, integrator, and comparator. The auto-zero accuracy is limited only
by the system noise, and the overall offset, as referred to the input, is less than 10 p,V.
Signal Integrate Phase. The auto-zero loop is opened and the internal IN + and IN - inputs are
connected to the external pins. The differential voltage between these inputs is integrated for a fixed
period of time. If the input signal has no return with respect to the converter power supply, INcan be tied to ANLG COMMON to establish the correct common-mode voltage. Upon completion
of this phase, the polarity of the input signal is recorded.
De-integrate Phase. The reference is used to perform the de-integrate task. The internal IN - is
internally connected to ANLG COMMON and IN + is connected across the previously charged reference
capacitor. The recorded polarity of the input Signal is used to ensure that the capacitor will be connected
with the correct polarity so that the integrator output polarity will return to zero. The time, which
is required for the output to return to zero, is proportional to the amplitude of the input signal. The
return time is displayed as a digital reading and is determined by the equation 10,000 x (VIDlVref).
The maximum or full-scale conversion occurs when VID is two times Vref.
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C
Zero Integrator Phase. The internal IN - is connected to ANLG COMMON. The system is configured
in a closed loop to cause the integrator output to return to zero. Typically this phase requires 100
to 200 clock pulses. However, after an over-range conversion, 6200 pulses are required.
description of analog circuits
input signal range
The common mode range of the input amplifier extends from 1 V above the negative supply to 1 V below
the positive supply. Within this range, the common mode rejection ratio (CMRR) is typically 86 dB. Both
differential and common mode voltages cause the integrator output to swing. Therefore, care must be
exercised to assure the integrator output does not saturate.
analog common
Analog common (ANLG COMMON) is connected to the internal IN - during the auto-zero, de-integrate,
and zero integrator phases. If IN - is connected to a voltage which is different than analog common during
the signal integrate phase, the resulting common mode voltage will be rejected by the amplifier. However,
in most applications, IN LO will be set at a known fixed voltage (power supply common for instance).
In this application, analog common should be tied to the same point, thus removing the common mode
voltage from the converter. Removing the common mode voltage in this manner will slightly increase
conversion accuracy.
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reference
The reference voltage is positive with respect to analog common. The accuracy of the conversion result
is dependent upon the quality of the reference. Therefore, to obtain a high accuracy conversion, a high
quality reference should be used.
tO
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TEXAS
..tf
INSTRUMENlS
POST OFFICE BOX 655012 • DAllAS. TEXAS 75265
2-227
TLC7135
Advanced LinCMOSTM 4 1/2·DIGIT PRECISION
ANALOG· TO·DIGITAL CONVERTER
•
description of digital circuits
RUN/HOLD input
When the RUN/HOLD input is high or open, the device will continuously perform measurement cycles every
40,002 ·clock pulses. If this input is taken low, the IC will continue to perform the ongoing measurement
cycle and then hold the conversion reading for as long as the pin is held low. If the pin is held low after
completion of a measurement cycle, a short positive pulse (greater than 300 ns) will initiate a new
measurement cycle. If this positive pulse occurs before the completion of a measurement cycle, it will
not be recognized. The first STROBE pulse, which occurs 101 counts after the end of a measurement
cycle, is an indication of the completion of a measurement cycle. Thus, the positive pulse could be used
to trigger the start of a new measurment after the first STROBE pulse.
c
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PRODUCT
PREVIEW
STROBE input
:::2
Negative going pulses from this input are used to transfer the BCD conversion data to external latches,
UARTS, or microprocesors. At the end of the measurement cycle, the digit·drive (05) input goes high and
remains high for 201 counts. The most ·significant digit (MSD) BCD bits are placed on the BCD pins. After
the first 101 counts, halfway through the duration of output 01-05 going high, the STROBE pin goes low
for 1/2 clock pulse width. The placement of the STROBE pulse at the midpoint of the 05 high pulse allows
the information to be latched into an external device on either a low-level or an edge. Such placement
of the STROBE pulse also ensures that the BCD bits for the second MSD will not yet be competing for
the BCD lines and latching of the correct bits is assured. The above process is repeated for the second
MSD and the 04. output. Similarly, the process is repeated through the least significant digit (LSD).
Subsequently, inputs 05 through 01 and the BCD lines will continue scanning without the inclusion of
STROBE pulses. This subsequent continuous scanning causes the conversion results to be continuously
displayed. Such subsequent scanning does not occur when an over-range condition occurs.
n
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BUSY output
. The BUSY output goes high at the beginning of the signal integrate phase and remains high until the first
clock pulse after zero·crossing or at the end of the measurement cycle if an over-range condition occurs.
It is possible to use the BUSY pin to serially transmit the conversion result. Serial transmission can be
accomplished by ANDing the BUSY and CLOCK signals and transmitting the ANDed output. The transmitted
output consists of 10,001 clock pulses, which occur during the signal integrate phase, and the number
of clock pulses, which occur during the de-integrate phase. The conversion result can be obtained by
subtracting 10,001 from the total number of clock pulses.
OVER-RANGE output
When an over-range condition occurs, this pin goes high after the BUSY signal goes low at the end of
the measurement cycle. As previously noted, the BUSY signal remains high until the end of the measurement
cycle when an over-range condition occurs. The OVER-RANGE output goes high at end of BUSY and goes
low at the beginning of the de-integrate phase in the next measurement cycle.
-0
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UNDER-RANGE output
-I
-0
:a
m
At the end of the BUSY signal, this pin goes high if the conversion result is less than or equal to 9% (count
of 1800) of the full-scale range. The UNDER-RANGE output is brought low at the beginning of the signal
integrate phase of the next measurement cycle.
S
m
~
2-228
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TeXAS 75265
TLC7135
Advanced LinCMOSTM 4 1/2·DIGIT PRECISION
ANALOG·TO·DIGITAL CONVERTER
PRODUCT
PREVIEW
PRINCIPLES OF OPERATION
POLARITY output
The POLARITY output is high for a positive input signal and is updated at the beginning of each de-integrate
phase. The polarity output is valid for all inputs including ± 0 and over-range signals.
digit-drive (05, 04, 02 and 011 outputs
Each digit-drive output (01 through 05) sequentially goes high for 200 clock pulses. This sequential process
is continuous unless an over-range occurs. When an over-range occurs, all of the digit drive outputs are
blanked from the end of the strobe sequence until the beginning of the de-integrate phase (when the
sequential digit drive activation begins again). The blanking activity, during an over-range condition, may
be used to cause the display to flash and indicate the over-range condition.
•
BCD outputs
The BCD bits (B8, B4, B2 and B 1) for a given digit are sequentially activated on these outputs.
Simultaneously, the appropriate Digit-drive line for the given digit is activated.
system aspects
integrating resistor
The value of the integrating resistor (RINTI is determined by the full scale input voltage and the output
current of the integrating amplifier. The integrating amplifier can supply 20 pA of current with negligible
non-linearity. The equation for determining the value of this resistor is as follows:
R
_
INT -
FULL-SCALE VOLTAGE
liNT
Integrating amplifier current, liNT, from 5 to 40 p.A will yield good results. However, the nominal and
recommended current is 20 p.A.
integrating capacitor
The product of the integrating resistor and capacitor should be selected to give the maximum voltage swing
without causing the integrating amplifier output to saturate and get too close to the power supply voltages.
If the amplifier output is within 0.3 V of either supply, saturation will occur. With ± 5-V supplies and ANLG
COMMON connected to ground, the designer should design for a ± 3.5-V to ±4-V integrating amplifier
swing. A nominal capacitor value is 0.47 p.F. The equation for determining the value of the integrating
capacitor (CINTI is as follows:
CINT
=
10,000 x CLOCK PERIOD x liNT
INTEGRATOR OUTPUT VOLTAGE SWING
~
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where: liNT is nominally 20 pA.
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Q.
Capacitors with large tolerances and high dielectric absorption can induce conversion inaccuracies. A
capacitor, which is too small could cause the integrating amplifier to saturate. High dielectric absorption
causes the effective capacitor value to be different during the signal integrate and de-integrate phases.
Polypropylene capacitors have very low dielectric absorption. Polystyrene and Polycarbonate capacitors
have higher dielectric absorption, but also work well.
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TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
2-229
TLC7135
Advanced LinCMOSTM 4 1/2-DIGIT PRECISION
ANALOG-TO-DIGITAL CONVERTER
PRODUCT
PREVIEW
PRINCIPLES OF OPERATION
•
auto-zero and reference capacitor
Large capacitors will tend to reduce noise in the system. Dielectric absorption is unimportant except during
power-up or overload recovery. Typical values are 1 I'F.
reference voltage
For high-accuracy absolute measurements, a high quality reference should be used.
rollover resistor and diode
The TLC7135 has a small rollover error, however it can be corrected. The correction is to connect the
cathode of any silicon diode to the INT OUT pin and the anode to a resistor. The other end of the resistor
is connected to ANLG COMMON or ground. For the recommended operating conditions the resistor value
is 100 kO. This value may be changed to correct any rollover error which has not been corrected. In many
non-critical applications, the resistor and diode are not needed.
maximum clock frequency
For most dual-slope AID converters, the maximum conversion rate is limited by the frequency response
of the comparator. In this circuit, the comparator follows the integrator ramp with a 3 jtS delay. Therefore,
with a 160 kHz clock frequency (61's period), half of the first reference integrate clock period is lost in
delay. Hence, the meter reading will change from 0 to 1 with a 50 I'V input, 1 to 2 with a 150 I'V input,
'2 to. 3 with a 250 I'V input, etc. This transition at midpoint is desirable; however, if the clock frequency
is increased appreciably above 160 kHz, the instrument will flash" 1" on noise peaks even when the input
is shorted. The above transition points assume a 2-V input range is equivalent to 20,000 clock cycles.
If the input signal is always of one polarity, comparator delay need not be a limitation. Clock rates of 1 MHz
are possible since non-linearity and noise do not increase substantially with frequency. For a fixed clock
frequency, the extra count or counts caused by comparator delay will be a constant and can be subtracted
out digitally.
For signals with both polarities, the clock frequency can be extended above 160 kHz without error by
using a low value resistor in series with the integrating capacitor. This resistor causes the integrator to
jump slightly towards the zero-crossing level at the beginning of the de-integrate phase and thus,
compensates for the comparator delay. This series resistor should be 10 to 50 ohms. This approach allows
clock frequencies up to 480 kHz.
minimum clock frequency
The minimum clock frequency limitations result from capacitor leakage from the auto-zero and reference
capacitors. Measurement cycles as high as 10 seconds are not influenced by leakage error.
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rejection of 50 Hz or 60 Hz pickup
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To maximize the rejection of 50 Hz or 60 Hz pickup, the clock frequency should be chosen so that an
integral multiple of 50 Hz or 60 Hz periods occur during the signal integrate phase. To achieve rejection
of these signals, some clock frequencies which could be used are as follows:
50 Hz: 250, 166.66, 125, 100 kHz, etc.
60 Hz: 300, 200, 150, 120, 100, 40, 33.33 kHz, etc.
<
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2-230
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75265
PRODUCT
PREVIEW
TLC7135
Advanced LinCMOSlM 4 1/2·DIGIT PRECISION
ANALOG· TO·DIGITAL CONVERTER
PRINCIPLES OF OPERATION
zero·crossing flip· flop
This flip-flop interrogates the comparator's zero-crossing status. The interrogation is performed after the
previous clock cycle and the positive half of the ongoing clock cycle have occurred so that any comparator
transients which result from the clock pulses do not affect the detection of a zero-crossing. This procedure
delays the zero-crossing detection by one clock cycle. To eliminate the inaccuracy, which is caused by
this delay, the counter is disabled for one clock cycle at the beginning of the de-integrate phase. Therefore,
when the zero-crossing is detected one clock cycle later than the zero-crossing actually occurs, the correct
number of counts is displayed.
•
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noise
The peak-to-peak noise around zero is approximately 15 p.V (peak-to-peak value not exceeded 95% of
the time). Near full scale, this value increases to approximately 30 p.V. Much of the noise originates in
the auto-zero loop, and is proportional to the ratio of the input signal to the reference.
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analog and digital grounds
~
For high-accuracy applications, ground loops must be avoided. Return currents from digital circuits must
not be sent to the analog ground line.
Q
power supplies
The TLC7135 is designed to work with ± 5-V power supplies. However, 5-V operation is possible if the
input signal does not vary more than ± 1.5 V from mid-supply.
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TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-231
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2-232
PRODUCT
PREVIEW
TLC7l36C
Advanced LinCMOSTM 3 l/2·DIGIT PRECISION
ANALOG·TO·DIGITAL CONVERTER AND LCD DRIVER
02849. OCTOBER 1986
•
•
•
•
•
•
•
•
•
•
•
N DUAL-IN-lINE PACKAGE
(TOPVIEWI
ADVANCED LinCMOS" Technology
Zero Reading for O-V Input on All Scales
VCC+
Precision Null Datection with True Polarity
at Zaro
UNITS
True Differential Input and Reference
Direct LCD Display Drive with No External
Components
Low Noise - 15 ,.Vp-p Without Hysteresis
or Overrange Hangover
2C
TENS
On-Chip Clock Oscillator and Reference
Convenient 9-V Battery Operation with Low
Power DiSSipation. Less than 1 mW
Direct Replacement for Intersil and Maxim
ICL7136
100'5
Pin Compatible with IntersillCL7106;
ICL7126 and Teledyne TSC7106. TSC7136
1C
1B
1A
1F
1G
1E
f
r
1-pA Typical Input Current
2B
2A
2F
2E
f
3B
3F
3E
(1000'5) 4AB
POL (MINUS)
OSC1
OSC2
OSC3
TEST
REF HI
REF LO
Cref+
CrefCOMMON
IN HI
IN LO
AUTO ZERO
BUFF
INT
VCC2G (TENS)
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Caution. These devices have limited built-in gate protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
description
The TLC7136C is a high-performance. very low-power 3 1/2-digit analog-to-digital converter (ADC). The
TLC7136C contains seven-segment decoders. display drivers. a clock, and a reference. This device is
designed to interface with liquid crystal displays and incorporates a backplane drive. The device can easily
be powered with a 9-volt battery because the supply current is less than 100 microamperes.
The TLC7136C provides high accuracy and versatility and such features as auto-zeroing to less than 10
microvolts, zero drift of less than 1 "V/oC, maximum input bias current of 10 picoamperes, and rollover
error of less than 1 count.
The differential input and on-chip reference are particularly useful when measuring load cells, strain gauges,
and other bridge-type transducers. Single-supply operation provides economy in that a high-performance
panel meter can be built with only seven passive components and a display. The TLC7136C is an improved
version of the Intersil ICL7126 in that overrange hangover and hysteresis effects are eliminated.
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The TLC7136C is characterized for operation from O°C to 70°C.
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ADVANCED
LinCMOS~
PRODUCT PREVIEW do.u.nll coatBi. Inlor.llion
on preduell I. tho formati.. or dlSi•• ,h••• of
dl.elop ....t. Ch....t.'i.li. data ad otb.,
="'rv::t~:sriO; ~i::I='~ T::.:.!:l:'::7:::
prodoell without natlca.
a..
is a trademark of Texas Instruments Incorporated.
Copyright @ 1986, Texas Instruments Incorporated
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
2-233
PRODUCT
PREVIEW
TLC7136C
Advanced LinCMOSTM 3 .1/2-DIGIT PRECISION
ANALOG-TO·DIGITAL CONVERTER AND LCD DRIVER
functional block diagram (with external components)
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BP
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1
1
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r~~~~~~~::::::~::~~::::::+=~~~____~__~I~(1)
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6.2 V
VCC+
I
'-__......___-4-__+--4>-_-+_______4-_~+-"N.....,I.:::(3"-7·)TEST
I
I
1(26)
VCC_ _....
_->----='
_ _ ...1
(40)
OSC1
(381
OSC3
(39)
RT
OSC2
Cre,
Cref+
Cref-
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_ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ANALOG
_ _ _SECTION
_ _ _ _ JI
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COMMON
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INT
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VCC-
NOTE: Letters beside switches indicate state of conversion during switch closure.
2-234
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
PRODUCT
PREVIEW
TLC7136C
Advanced LinCMOSTM 3 1/2·D1G1T PRECISION
ANALOG·TO·DIGITAL CONVERTER AND LCD DRIVER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (Vcc + with respect to Vcc -), Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Voltage range for any input except clock (see Note 1) . . . . . . . . . . . . . . . . . . . . . . VCC _ to VCC +
Clock input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Vtest to VCC +
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OoC to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds ...................... 260°C
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NOTE 1: Input voltages may exceed the supply voltages provided the input current is limited to ± 100 itA.
C
recommended operating conditions
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MIN
VCC
Supply voltage
Vref
Reference input voltage
VI
Input voltage at IN HI or IN
Cref
Cz
Cx
Reference capacitor
Auto~zero
Rs
Integrator resistor
TA
Operating free-air temperature
NOM
MAX
I FS (full scale) VID = 200 mY, See Note 2
I FS VID - 2 V
Full-scale input voltage
V
capacitor
Integrator capacitor
..
V
!,F
0.033
0.47
!,F
0.15
!,F
kll
0.047
180
1.8
I'll
I'll
V
VCC+ -0.5
1
I FS = 2 V
«
V
Vcc- +1
0.1
IFS - 200 mV
0"
CJ
mV
2 Vref
La
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UNIT
9
100
1
C
Mil
0
°c
70
electrical characteristics, Vee - 9 V, fclock .. 16 kHz, TA .. 25°e (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Common-mode rejection ratio
Noise voltage
(peak-to-peak value not exceeded 95% of time)
Input leakage current
Scale factor temperature coefficient
MIN
= 0,
VIC = ±1 V,
FS = 200 mV
VID
VID
= 0,
FS
=
200 mV
VIO
VID
=0
= 199
TA
=
0 to 70°C,
mV,
See Note 3
Analog common voltage (with respect to VCC +)
Temperature coefficient of analog common voltage
(with respect to V CC +)
250 kll between COMMON and VCC +
-2.6
TYP
MAX
50
!'V/v
15
!'V
1
10
pA
1
5
ppm/DC
-3
-3.2
V
ppm/DC
150
250 kll between COMMON and VCC +
UNIT
Peak-to-peak segment drive voltage (see Note 4)
4
5
6
Peak-to-peak backplane drive voltage (see Note 4)
4
5
6
V
50
100
!,A
Supply current (see Note 5)
Power dissipation capacitance
VID = 0
See Note 6
NOTES: 2. VIO is the voltage at IN HI with respect to IN
40
V
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La.
3. This is measured using a fixed external reference voltage with O-ppm/oC temperature coefficient.
4. Backplane drive is in phase with segment drive for a turned-off segment. 180 0 out of phase for a turned-on segment. Backplane
frequency is 20 times the conversion rate. The average dc component is less than 50 mY.
5. This does not include current through the common terminal. During the auto-zero phase. current is 10 to 20 p.,A higher. Use
of a 48-kHz oscillator increases current by typically 8 pA.
6. This can be used to determine the no-load dynamic power dissipation. Po
=
CpdoVCC2of+ICCoVCC'
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TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-235
PRODUCT
PREVIEW
TLC7136C
Advanced LinCMOS"'" 3 1/2·DIGIT PRECISION
ANALOG·TO·DIGITAL CONVERTER AND LCD DRIVER
operating characteristics over recommended operating free-air temperature range,
•
PARAMETER
Zero-input digital reading
TEST CONDITIONS
MIN
-0.000
VID = O. FS = 200 mV
VID - V r.( = 100 mV
Ratiometric digital reading
Rollover error (see Note 71
Linearity error
999
VID- = VID+ = 200 mV or 2 V
FS = 200 mV or 2 V
VIO - O.
TA = O·C to 70·C
Zero-reading temperature coefficient
Vee -
TYP
MAX
±O.OOO
+0.000
1000
999'1000
±0.2
9
V
UNIT
±O.2
±1
±1
Count
Count
0.2
1
",V/·C
NOTE 7: Rollover error is the difference between the magnitudes of the conversion results for equal positive and negative inputs near full scale.
PARAMETER MEASUREMENT INFORMATION
Vcc=9V
II
240kn
(261
(1)
vCC+
(361
1Dkn
VCCPOL
REFHI
lA
1B
(351
(321
ANALOG
INPUT
VOLTAGE
(301
1C
REF LO
10
COMMON
1E
1F
IN LO
1G
0.1 p.F
(311
(401
2A
INHI
2B
2C
OSC1
20
560kn(391
OSC2
2E
50 pF (381
2F
OSC3
2G
."
Cref+
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2-236
3A
3B
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Craf_
3C
AUTO ZERO
3D
3E
180kn (281
BUFF
3F
3G
INT
(201
4AB
(41
(31
(21
(81
(61
(71
(121
(111
(101
(91
(141
24
(131
(251
(231
(161
(241
(151
(181
(171
(221
(191
BP
FIGURE 1. TEST CIRCUIT (CLOCK FREQUENCY -
TEXAS
16 kHz. 1 READING PER SECOND)
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76265
PRODUCT
PREVIEW
TLC7136C
Advanced LinCMOS"" 3 1/2·DlGIT PRECISION
ANALOG·TO·DlGITAL CONVERTER AND LCD DRIVER
PARAMETER MEASUREMENT INFORMATION
Vcc=9V
...---------.....-.111
...en
240 k!1
(1)
VCC+
(36)
10k!1
REFHI
(26)
ANALOG
INPUT
VOLTAGE
1C
REF LO
(30)
COMMON
IN LO
1E
1F
1G
0.1 "F
1 MO
(31)
+
(40)
2A
INHI
OSC1
2B
2C
20
180 kO(39)
OSC2
OSC3
2E
2F
2G
Cref+
3A
3D
Cref_
3C
3D
3E
180kU(28)
BUFF
Co)
C3
1A
10
(32)
...
Vcc_
POL
1B
(35)
"S
(4)
(3)
(2)
(8)
(6)
(7)
(12)
(11)
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TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-237
TLC7136C
Advanced LinCMOS'" 3 112-DIGIT PRECISION
ANALOG-TO-DIGITAL CONVERTER AND LCD DRIVER
PRODUCT
PREVIEW
PRINCIPLES OF OPERATION
A measurement cycle, for the TLC7136C, consists of four phases. The four phases are as follows:
1. Auto-Zero Phase. The intemallN HI and IN LO inputs are disconnected from the pins and are internally
connected to analog COMMON. The reference capacitor is charged to the reference voltage. The system
is configured in a closed loop and the auto-zero capacitor is charged to compensate for offset voltages
in the buffer amplifier, integrator, and comparator. The auto-zero accuracy is limited only by the system
noise, and the overall offset, as referred to the input, is less than 10 microvolts.
2. Signal Integrate Phase. The auto-zero loop is opened and the intemal IN HI and IN LO inputs are
connected to the external pins. The differential voltage between these inputs is integrated for a fixed
period of time. If the input signal has no return with respact to the converter power supply, IN LO
can be tied to analog COMMON to establish the correct common-mode voltage. Upon completion of
this phase, the polarity of the input signal is recorded.
3. Deintegrate (reference-integrate) Phase. The reference is used to perform the deintegrating task, which
is performed in the following manner. The IN LO is internally connected to analog COMMON and IN
HI is connected across the previously charged reference capacitor. The recorded polarity of the input
signal is used to ensure that the capacitor will be connected with the correct polarity so that the
integrator output will return to zero. The time that is required for the output to return to zero is
Proportional to the amplitude of the input signal. The return time is displayed as a digital reading and
is determined by the equation 1000 VID/Vref.
4. Zero Integrator Phase. The internal IN LO is connected to analog COMMON. The system is configured
in a closed loop to cause the integrator output to return to zero. Typically this phase requires 11 to
140 clock pulses. However, after an overrange conversion, 740 pulses are required.
description of analog circuits
input signal range
The common-mode range of the input amplifier extends from 1 volt above the negative supply to 0.5 volt
below the positive supply. Within this range, the common mode rejection ratio (CMRR) is typically 86 dB.
The common-mode signal also causes the integrator output to swing and there is a possibility that the
integrator output could saturate. This saturation, which causes an incorrect conversion, is most likely with
the combination of a large positive common mode voltage and a large negative differential voltage. The
negative differential voltage causes the integrator output to go positive when most of the integrator's
positive output swing capability has been used up by the large positive common mode voltage. In such
situations, the integrator swing can be reduced to less than. the recommended 2-volt swing with a minimal
reduction in accuracy. The linear range of the integrator output is within 0.3 volts of either supply.
differential reference
"'0
The reference voltage must lie within the device power supply range. The major source of common-mode
error is caused by the loss or gain of charge from the reference capacitor due to stray capacitances. With
large common-mode voltages, the reference capacitor will gain charge or voltage while de integrating a
positive signal and, conversely, lose charge or voltage while deintegrating a negative signal. This gain or
loss of reference capacitor voltage will cause a rollover error. The selection of a reference capacitor that
is large in comparison to the stray capacitance will reduce the rollover error to less than 0.5 counts (see
Component Value Selection).
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analog common
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2-238
For battery operation or when the inputs are floating with respect to the TLC7136C power supply, the
analog COMMON pin is used to set the common mode voltage. The COMMON pin is preset by internal
circuits to a voltage that is approximately 3 volts less than the TLC7136C positive supply. This preset
voltage will give a 6-volt end-of-battery life.
TEXAS ..,
INSTRUMENTS
. POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
PRODUCT
PREVIEW
TLC7136C
Advanced LinCMOS™ 3 1/2·DIGIT PRECISION
ANALOG·TO·DIGITAL CONVERTER AND LCD DRIVER
PRINCIPLES OF OPERATION
When the power supply voltage is greater than 7 volts. the TLC7136C zener will be in a regulating mode
and the preset voltage at the COMMON pin will have reference-like qualities. The preset voltage will then
have a low 0.001 %-per-volt voltage coefficient. a low output impedance of approximately 35 ohms. and
a temperature coefficient of less than 80 ppml DC. Therefore. the preset voltage could be used for an onchip reference. however. there are some limitations. For 2 DC to 8 DC temperature changes. a scale factor
of one count or more can result. Also. if the power supply voltage drops below 7 volts. the voltage coefficient
will be poor since the zener will no longer be in a regulating mode.
Analog COMMON is connected to the internal IN La during the auto-zero. deintegrate. and zero integrator
phases. If IN La is connected to a voltage that is different from analog common during the signal-integrate
phase. the resulting common-mode voltage will be rejected by the amplifier. However. in certain applications.
IN La is set at a fixed known voltage. for example the power supply common voltage. For these applications.
the COMMON pin should be tied to IN La to eliminate the common-mode rejection error. The same
consideration applies to the reference vol.tage. Referring the reference voltage to analog COMMON eliminates
another common-mode error source. Referring the reference voltage to an analog common is accomplished
by connecting COMMON to either REF La or REF HI.
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test
The TEST pin performs two functions. First. it is connected to the internally generated digital supply (negative
side) through a 500-ohm resistor. This connection allows the TEST pin to be used as the negative supply
for external segment drivers. such as decimal points or any LCD segment that requires up to 1-milliampere
load current. Second. the pin performs a test function. When the TEST pin is pulled up to VCC +. all
segments will turn on and the display will read - 1888. In this test mode. a constant DC voltage is applied
to the segments. rather than a square wave. and the segments may be damaged if the test is prolonged.
description of digital circuits
An internal digital ground is generated with a 6-volt zener diode and a large P-channel source follower.
This generated supply can handle the large capacitive currents that result when the backplane (8P) voltage
is switched. Dividing the clock frequency by 800 gives the BP frequency. For 3 readings per second. the
I;3P signal is a 5-volt. 60-Hz squarewave. The segments that are driven at the same frequency and amplitude
are in phase with BP when off. and out of phase with BP when on. Except in the test mode. a negligible
amount of DC voltage is placed across the segments. For negative-polarity inputs. the polarity indication
will become active. Also. if the placement of IN La and IN HI is switched. the polarity indication can be
switched accordingly.
system timing
The TLC7136C clock circuit is shown in Figure 3. The three possible clock setups are pin 40 connected
to an external oscillator. a crystal between pins 39 and 40. or an RC oscillator with connections to pins
38. 39. and 40.
The frequency of the clock oscillator is first divided by four and then the resulting clock signal is used
to clock the decade counters. The divide-by-four clock signal is then further divided to form the four convertcycle phases. which are as follows:
1. 1.000 counts for signal integration.
2. 0 to 2.000 counts for reference deintegration.
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TEXAS ."
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TeXAS 75265
2-239
TLC7136C
Advanced LinCMOSTM 3 1/2·DlGIT PRECISION
ANALOG·TO·DlGITAL CONVERTER AND LCD DRIVER
PRODUCT
PREVIEW
PRINCIPLES OF OPERATION
3.
11 to 140 counts for zero integration (with an overranged conversion of greater than 2,060 counts,
the zero integrator phase will require 740 counts, and auto-zero will require 260 counts).
4. 910 to 2900 counts for auto-zero (for signals less than full-scale, auto-zero gets the unused portion
of reference deintegration and zero integration).
C
I»
....
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The total measurement cycle requires 4,000 counts or 16,000 clock pulses. A 48-kilohertz oscillator would
be required for three readings per second.
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,·(40)
I
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IL __ . ."''....._.:....._ _ _ _ _ _ _ _ _ _ _ _ _ _-'
IL ____ +,..,.,-L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...J
~L
______________ _
NOTE: This figure shows all three external control circuits connected; however, only one external circuit (crystal, RC network or external
oscillator) is connected for proper operation.
FIGURE 3. CLOCK CIRCUITS
component value selection
integrating. resistor
The buffer amplifier and integrator class A output stages require approximately 6 microamperes of quiescent
current and can source - 1 microampere of current without inducing any significant nonlinearity. The
integrating resistor should be sufficiently large that the buffer amplifier and integrator will remain in this
linear region. However, the resistor must also be small enough that PC board leakage remains insignificant.
Values of 180 kilohms and 1.8 megohms are recommended for the respective 200-millivolt and 2-volt
full-scale voltages.
integrating capacitor
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The integrating capacitor should be chosen to give the maximum voltage swing, yet not allow the combined
tolerances of the integrating resistor and capacitor to cause the integrator to saturate. The linear range
of the integrator extends to within 0.3 volt of VCC _ or VCC +. A + 2-volt full-scale integrator swing works
fine when analog common is used asthe reference. Capacitor values of 0.047 microfarad and 0.15 microfarad are recommended for 3 (48-kilohertz oscillator) and 1 (16-kilohertz oscillator) readings per second
respectively. As the oscillator frequency is increased, the capacitor value must be decreased to maintain
the same output swing. Polypropylene capacitors are recommended because of their reasonable cost and
low dielectric absorption, which produces low roll-over errors.
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m
=:
2-240
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
PRODUCT
PREVIEW
TLC7136C
Advanced LinCMOSTM 3 1/2·DIGIT PRECISION
ANALOG·TO·DIGITAL CONVERTER AND LCD DRIVER
PRINCIPLES OF OPERATION
INTEGRATOR
OUTPUT
----1'
AUTO·
ZERO
'"
""
.........
SIGNALINTEGRATE
1000 COUNTS
""
•
rn
.1::
" "- - - - ~----
DE-INTEGRATE
(REFERENCE-INTEGRATEI
2000 COUNTS (MAX)
::::1
~
C3
ZERO
INTEGRATOR
c
o
.~
:!i::::1
cr
U
4000 COUNTS
116,000 OSCILLATOR CYCLES)
cr:
;
FIGURE 4. TIMING DIAGRAM
auto-zero capacitor
Q
The size of this capacitor has an effect upon the noise of the system. For 200-millivolt full-scale applications,
in which noise must be kept to a minimum, a 0.47-microfarad capacitor is recommended. The zero-integrator
phase allows the use of a large auto-zero capacitor without the accompanying hysteresis or overrange
hangover problems that can occur with the ICL7126 or ICL7106.
reference capacitor
A 0.1-microfarad capaoitor is fine for most applications. However, with large common-mode signals, if
the REF LO pin is not connected to analog COMMON and the full-scale voltage is 200 millivolts, a larger
capacitor is required to prevent rollove'r error. A 1-microfarad capacitor will hold this rollover error to
0.5 counts.
.
oscillator components
A 50-pF capacitor is recommended for all frequency ranges. The resistor can be selected from the equation:
f = 0.45/RC
where: R = 180 kilohms for 48-kilohertz oscillator (3 readings per second) and 560 kilohms for 16-kilohertz
oscillator (1 reading per second).
reference voltage
An input voltage of 2 Vref is required to obtain a full-scale reading of 2,000 counts. Therefore, for a fullscale of 200 millivolts and 2 volts, Vref should be 100 millivolts and 1 volt respectively. In many situations,
the designer might like to have a full-scale voltage other than 200 millivolts or 2 volts. In situations where
the designer desires a full-scale voltage of X volts, the designer can select a Vref of X/2 volts. The value
of the integrating resistor can be determined by the following equation:
X volts (desired full-scale)
200 mV
Value of Integrating Resistor for X volts full-scale
180 kG (integrating resistor for 200 mV full-scale)
~
'POST OFFICE BOX 655012 , bAllAS, texAs 76265
a:
Q.
l-
Sometimes a designer will want a digital reading of zero when VI does not equal zero. This desire can
be met by connecting VI between IN HI and COMMON and the zero-reading V.I between COMMON and
IN LO.
TEXAS
:>w
e,)
If X volts is greater than 200 millivolts, it is better to work with an X/2 volts reference, since dividing
the X volts down to 200 millivolts will cause the input signal to be more susceptible to noise.
INstRUMENTS
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2-241
C
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VI
2-242
ADVANCE
INFORMATION
TLC7524
Advanced LinCMOS™ 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTER
03008, SEPTEMBER 1986
•
•
D OR N PACKAGE
Advanced LinCMOS" Silicon-Gate
Technology
Easily Interfaced to Microprocessors
•
On-Chip Data Latches
•
Guaranteed Monotonicity
•
Segmented High-Order Bits Ensure LowGlitch Output
•
•
•
(TOP VIEW)
Designed to be Interchangeable with Analog
Devices AD7524. PMI PM-7524. and Micro
Power Systems MP7524
OUT1
OUT2
GND
DB7
DB6
DB5
OB4
DB3
RFB
REF
VOD
WR
CS
DBO
DB1
DB2
...
In
-5
~
C3
c
o
'iii
'';::;
'5
c::r
(,)
(')
I S-1
2R
2R
2R
2R
(16)
.c
c
II
S-2
11
:1
1
i:d'.
I
1
0
I
:::I
-es
(')
.
::;'
Wli
(')
C
{:Y
1
I
I
I
I
I
:1
"
:
DATA LATCHES
1(4)
DB7
(MSB)
1(5)
DB6
(1)
(
+ + +
til
R
I
(12)
(13)
Il s-s
1(6)
t
(2)
I
I
(3)
OUT1
OUT2
GND
1(11)
DBO
(LSB)
DB5
'~--------~v~--------~
DATA INPUTS
operating sequence
14
~~
tsu(CS)
I
I
'\
I
I
~I
th(CS)
I
M-----tw(WR)---.I
I
I
'\
»
c
~
I,
I"-tsU(D)--+i
If-tj-- th(D)
1
DBO-DB7
--...;..----~~(====J)I------
2
(")
m
2
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3:
~
S
2
TEXAS
2-244
~
INSTRUMENTS
pilat
II~Flcl! 1iO~
8liiiQi i • IIAli.As, tExAs t&~8i
ADVANCE
INFORMATION
TLC7524
Advanced LinCMOSTM 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 16.5 V
Digital input voltage, VI ....................................... -0.3 V to VDD+0.3 V
Reference voltage, Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 V
Peak digital input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10 p.A
Operating free-air temperature range: TLC75241 .......................... -25°C to 85°C
TLC7524C ............................ OOC to 70°C
Storage temperature range ......................................... - 65°C to 1 50°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 260°C
II
II)
,~
~
~
U
c
o
recommended operating conditions
voo MIN
Supply voltage, VOO
Voo -
V
NOM
MAX
MIN
5
5.25
14.5
4.75
Reference voltage, V ref
5
±10
High-level input voltage, VIH
15 V
NOM MAX
15
15.5
±10
2.4
II)
V
1.5
40
40
V
ns
0
0
ns
Data bus input setup time, tsulOI
25
10
25
10
ns
Data bus input hold time, thlOI
Pulse duration, WR low, tw(WRI
40
40
CS hold time, th(CSI
InC75241
Operating free-air temperature, TAl TLC7524C
..
V
0.8
CS setup time, tsu(CSI
'3
cr
u
----4!>--DUTPUT
CS----I
WFi----t
GNO
FIGURE 2. UNIPOLAR OPERATION (2-QUADRANT MULTIPLICATION)
Vref
VOO
20 kll
2
RA - 2 kll
(See Note 3)
o
20 kll
">....-DUTPUT
OBO-OB7
~
~
a:
oLL
cs---t
WR----I
-w
:2
(.)
FIGURE 3. BIPOLAR OPERATION (4-QUADRANT OPERATION)
NOTES:' 3. RA and RB used only if gain adjustment is required.
4. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
2
«
>
o
«
2-247
TLC7524
Advanced LinCMOSTM 8·BIT MULTIPLYING
OIGIT AL· TO·ANALOG CONVERTER
AOVANCE
INFORMATION
principles of operation (continued)
TABLE 2. BIPOLAR (OFFSET BINARY) CODE
TABLE 1. UNIPOLAR BINARY COOE
DIGITAL INPUT
DIGITAL INPUT
(SEE NOTE 51
MSB
C
...
(SEE NOTE 6)
ANALOG OUTPUT
MSB
LSB
ANALOG OUTPUT
LSB
DI
11111111
- Vref (255/256)
11111111
Vref (127/128)
DI
10000001
- V ref (129/256)
10000001
Vref (1/128)
10000000
-Vref (128/256)
(')
01111111
- Vref (127/256)
01111111
00000001
-Vref (1/256)
0
00000001
- Vref (127/128)
00000000
-Vref
»
.Q
C
(ij.
00000000
=
10000000
-Vref/2
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NOTES:
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c
5. LSB
=
1/256 (Vref).
6. LSB = 1/128 (Vref).
microprocessor interfaces
~
(I)
00-07
I-________________...;,D'-A_T_A__
BU_S______--.
Z-80A
WRJ---.r........
>---------------~WR
ADDRESS BUS
AO-A15
FIGURE 4. TLC7524-Z-80A INTERFACE
)I
C
~
:2
(')
00-07
I-_________________D...;A...;T...;A...;B...;U...;S:....-____--.
6800
m
-~
1/>2
o
::XJ
VMA
I------r--"
~----~--------~WR
1--'--+---1
3:
l>
:::t
AO-A15
ADDRESS BUS
o
:2
2-248
FIGURE 5. TLC7524-6800 INTERFACE
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
0
-Vref (1/128)
TLC7524
Advanced LinCMOSTM 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTER
ADVANCE
INFORMATION
microprocessor Interfaces (continued)
A8-A15
ADDRESS BUS
r-------------~-;
DECODEI---+----.
LOGIC
8051
8-BIT t--::~-I
LATCH
ALE
r--+--+--+_...J
...---------tWR
WRr--+--+---------~
ADO-AD7
r-_________A_D_D.;.;RE;;,.;S;.;;,S/;.;;,D;.,.AT_A_B,;.;U;.;;,S_ _ _ _ _ _ _ _ _-r
FIGURE 6. TLC7524-8051 INTERFACE
•
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cr
Co)
..
ct
ca
ca
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III
2-250
ADVANCE
INFORMATION
TLC7528
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTER
02979. JANUARY 1987
•
ADVANCED LinCMOS'" Silicon·Gate
Technology
•
Easily Interfaced to Microprocessors
N DUAL-IN-LiNE PACKAGE
•
On·Chlp Data Latches
•
Guaranteed Monotonlclty
•
Designed to be Interchangeable with Analog
Devices ADC7528 and PMI PM·7528
•
•..
ITOPVIEW}
Fast Control Signaling for Digital Signal
Processor Applications Including Interface
with TMS320
AGND
OUTA
RFBA
REFA
DGND
DACA/DACB
(MSB) DB7
DB6
DB5
DB4
OUTB
RFBB
REFB
VDD
WR
CS
DBO (LSB)
DBl
DB2
DB3
U)
·S
~
CJ
c
o
.;;
';::
·S
KEY PERFORMANCE SPECIFICATIONS
Resolution
Linearity Error
Power Oissipation at VOO = 5 V
Settling Time at VDD = 5 V
Propagation Delay at VDD = 5 V
C"
U
..
8 bits
c:(
1/2 LS8
5mW
100 ns
80 ns
ca
ca
C
description
The TLC7528 is a dual 8-bit digital-to-analog converter designed with separate on-chip data latches and
featuring excellent DAC-to-DAC matching. Data is transferred to either of the two DAC data latches via
a common 8-bit input port. Control input DACA/DACB determines which DAC is to be loaded. The "load"
cycle of the TLC7528 is similar to the "write" cycle of a random-access memory, allowing easy interface
to most popular microprocessor busses and output ports. Segmenting the high-order bits minimizes glitches
during changes in the most significant bits, where glitch impulse is typically the strongest.
The TLC7528 operates from a 5-volt to 15-volt power supply and dissipates less than 15 mW (typical).
Excellent 2- or 4-quadrant multiplying makes the TLC7528 a sound choice for many microprocessorcontrolled gain-setting and signal-control applications.
The TLC75281 is characterized for operation from - 25 to 85°C. The TLC7528C is characterized for
operation from O°C to 70°C.
z
o
i=
c
c
«
2-255
ADVANCE
INFORMATION
TLC7528
Advanced LinCMOSlM DUAL 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTER
•!
»
2R
2R
2R
2R
2R
S8 .
R
~"""'-RF8A
~-+--~-+--~~-fJ~~~----r-~----OUTA
~--~~--~~'f---~4---"-------AGND
n
.Q
c
i!:
=::t.
g
FIGURE 1. SIMPLIFIED FUNCTIONAL CIRCUIT FOR DACA
n
RFBA
~.
c
;:
R
VREFA-'lM.----....------.....----......---OUTA
_1256
FIGURE 2. TLC7528 EQUIVALENT CIRCUIT. DACA LATCH LOADED WITH 11111111.
MODE SELECTION TABLE
i5AeA1
DACB
L
H
X
X
cs
WR
DACA
DACB
L
L
H
L
L
X
X
H
WRITE
HOLD
HOLD
HOLD
HOLD
WRITE
HOLD
HOLD
L = low level, H = high level, X = don't care
»
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2
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3:
»
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-
o
2
TEXAS ...,
2-256
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
ADVANCE
INFORMATION
TLC7528
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTER
TYPICAL APPLICATION DATA
The TLC7528 is capable of performing 2·quadrant or full 4-quadrant multiplication. Circuit configurations
for 2-quadrant and 4-quadrant multiplication are shown in Figures 3 and 4. Input coding for unipolar and
bipolar operation are summarized in Tables 1 and 2, respectively.
•
...
In
vilA)
±10 v
..
':;
U
U
r:::
o
'iii
VDD~---(14)
DBO
. .
: I :
7
'.;:l
INPUT
BUFFER
':;
cr
u
DB7
C
o
«
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-259
TLC7528
Advanced LinCMOSTM DUAL 8·BIT MULTIPLVING
DIGITAL·TO·ANALOG CONVERTER
ADVANCE
INFORMATION
TYPICAL APPLICATION DATA
•
A8-A16
1----....
C
III
S
~
n
.c
CPU
Z80-A
E.
;:o
WRI---l_'"
:::I
(')
::rc
-r-_____.....
DO-D71-_ _ _ _ _ _ _ _
D_A_TA_BU_S_ _ _
it
NOTE:
A = decoded add-ess for TLC7528 DACA.
A + 1 = decoded address for TLC7528 DACB.
FIGURE 7. TLC7528 TO Z80-A INTERFACE
programmable window detector
The programmable window comparator shown in Figure 8 will determine if voltage applied to the DAC
feedback resistors are within the limits programmed into the TLC7528 data latches. Input signal range
depends on the reference and polarity, that is, the test input range is 0 to -Vref. The DACA and DACB
data latches are programmed with the upper and lower test limits. A signal within the programmed limits
will drive the outDut high.
VCC
VDD
TEST
INPUT-...- - - - - - - - .
o TO -Vref
r---==::-:+:;:;:"--~
»c
~
2:
1kO
-n
DATA r - - " ' -.......
INPUTS
'---..-T"7''-I
IiI
n
AGNDe--t-............
TLC7628
m
+Vref
PASS/FAiL
OUTPUT
_+......:.;ll.;::.81:.rRE;;:.F.;::.B-i
RFBB
(191
FIGURE 8. DIGITALLY PROGRAMMABLE WINDOW COMPARATOR (UPPER- AND LOWERcLiMIT TESTER)
2-260
TEXAS
..If
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
ADVANCE
INFORMATION
TLC7528
Advanced LinCMOSTM DUAL 8·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTER
TYPICAL APPLICATION DATA
digitally controlled signal attenuator
Figure 9 shows the TLC7528 configured as a two-channel programmable attenuator. Applications include
stereo audio and telephone signal level control. Table 3 shows input codes vs attenuation for a 0 to 15.5 dB
range.
Attentuation db
VDD
= -
=
20 1091O 0/256. 0
•
.~
.
C3
::l
CJ
digital input code
(17lr---;::====::;;;:;;:;:1!(@3LI____....,
c
o
RFBA (21
OUTA
OUTPUT
.~
·iii
·S
CJ'
~
0:<'1-+---.....
..
•
TLC752B
DB7
CI
1151
WR
(161
as
as
Q
61' - - - - - - DACA/DACBF
(lBI
REFB
VOB
AGND (11
DGND (51
FIGURE 9. DIGITALLY CONTROLLED DUAL TELEPHONE ATTENUATOR
TABLE 3. ATTENUATION vs DACA. DACB CODE
ATTN(dB)
DAC INPUT CODE
0
0.5
1.0
1.5
11110010
11100100
11010111
2.0
11001011
2.5
3.0
3.5
4.0
11000000
10110101
10101011
4.5
11111111
10100010
10011000
CODE IN
DECIMAL
ATTN(dBI
8.0
255
242
8.5
9.0
228
215
9.5
203
192
181
171
10.0
10.5
11.0
11.5
162
12.0
5.0
5.5
6.0
6.5
10010000
152
144
12.5
13.0
10001000
10000000
01111001
136
128
121
13.5
14.0
7.0
7.5
01110010
01101100
114
108
14.5
15.0
15.5
DAC INPUT CODE
CODE IN
DECIMAL
01100110
01100000
01011011
102
96
91
01010110
01010001
86
81
01001100
01001000
01000100
76
72
01000000
00111101
00111001
68
64
61
00110110
00110011
00110000
57
54
51
48
00101110
00101011
46
43
z
i=
C2
C
OUTB (20)
<
l>
lOW PASS
OUT
RFBB 1191
2
REFB 1181
(")
181
m
~DACB
CIRCUIT EQUATIONS:
DACA2 AND DACB2
2:
."
o
~
~
o-
C1 - C2. R1 - R2, R4 - R5
Q_
R3.
R4
NOTES: A. Op-amps Al, A2, A3, and A4 are TL2B7.
B. C3 compensates for the op-amp gain-bandwidth limitations.
2
C. DAC equivalent resistance equals
RF
RfbIDACB1)
RF
Ao - - RS
256 x IDAC ladder resistance)
DAC digital code
FIGURE 10. DIGITALLY C.ONTROLLED STATE-VARIABLE FILTER
2-262
TEXAS ."
INSTRUMENTS
POST GFFICE BOX 655012 • DAlLAS, TEXAS 75265
PRODUCT
PREVIEW
TLC75331. TLC7533C
Advanced LinCMOS™ 1O·BIT MULTIPLYING
DIGlTAL·TO·ANALOG CONVERTERS
02166. OCTOBER 1986
•
ADVANCED LinCMOS" Silicon-Gate
Technology
N DUAL-IN-LiNE PACKAGE
(TOP VIEW)
•
Guaranteed Monotonicity
•
Fast Settling Time
OUT1
OUT2
RFB
REF
GND
VDD
•
CMOS/TTL Compatible
•
Four-Quadrant Multiplication
•
Designed to be Interchangeable with Analog
Devices AD7533, AD7520, and PMI
PM-7533
(MSB) BIT
BIT
BIT
BIT
BIT
1
2
3
4
5
BIT
BIT
BIT
BIT
BIT
...
III
10 (LSB)
9
8
7
6
'3
...
(,)
(3
C
o
'';:;
'iii
'3
KEY PERFORMANCE
SPECIFICATIONS
Resolution
10 Bits
Linearity Error
1/2 LSB
Power Dissipation
30 mW
Settling Time
150 ns
C'
(,)
c:r:
...caca
Q
description
The TLC7533 is an ADVANCED LinCMOS" 10-bit digital-to-analog converter featuring two- and fourquadrant multiplication.
The TLC7533 is pin and functionally equivalent to the AD7520 and AD7533. Texas Instruments advanced
thin-film-on-monolithic-CMOS fabrication process provides 10-bit linearity without laser trimming.
The TLC7533 features TTL or CMOS compatibility with low input leakage currents from 5-V to 15-V power
supplies. Output scaling is provided by an internal feedback resistor and an external operational amplifier.
Both positive and negative reference voltages can be utilized.
The TLC75331 is characterized for operation from - 25°C to 85 DC. The TLC7533C is characterized for
operation from OOC to 70°C.
~
w
:>w
a::
c..
~
(J
;:)
C
o
a::
c..
ADVANCED LinCMOS is a trademark of Texas Instruments Incorporated
PRODUCT PREVIEW documents contain informetion
on products in the formative or design ,hase of
development. Characteristic data anil othar
spacifications ara design goals. Taxas Instruments
ra.arval the right to change or discontinue thasa
products without notica.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright @) 1986, Texas Instruments Incorporated
2-263
TLC75331, TLC7533C
Advanced LinCMOSlM 1o·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTERS
PRODUCT
PREVIEW
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VDD (see Note 1) .................................... -0.3 V to 16.5 V
Digital input voltage, VI ......................................... -0.3 to VDD+0.3 V
Reference voltage, Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±25 V
Operating free-air temperature range: TLC75331 .......................... - 25°C to 85 °C
TLC7533C ............................ OOC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 260°C
c
!I»
»
n
NOTE 1: All voltage values are with respect to the network ground terminal.
5.
!II
recommended operating conditions
.Q
;::;."
S·
MIN
:::I
Supply voltage, VDD
(')
Reference voltage, Vref
High-level input voltage, VIH
~r
c
;::;..
!II
NOM
5
MAX
16.5
±10
0.8
.
I TLC75331
Operating free-air temperature, TAl TLC7533C
-25
0
v
V
2.4
Low-level input voltage, VIL
UNIT
85
70
V
V
°C
electrical characteristics over recommended operating temperature range, Voo ... 15 V,
Vref ... ± 10 V, OUT1 and OUT2 at 0 V (unless otherwise noted)
'I
PARAMETER
Input leakage current, digital input
Input resistance (pin 15) (see Note 2)
Ilkg
Output leakage current
II
ksvs
TEST CONDITIONS
loun
IOUT2
Supply voltage sensitivity
100
Ci
(aAv/aVDD) (see Note 3)
Supply current
Input capacitance, digitai· input
Co
Output capacitance
o
C
."
Output current settling time
m
Feedthrough error
-<
m
~
20
±200
OUT2
OUTl
OUT2
kO
nA
Digital inputs at VIH
±200
VDD - 14 V to 16.5 V,
Digital inputs at VIH
0.008
%/%
2
mA
pF
10
100
Digital inputs at VIH
35
35
100
Digital inputs at VIL
pF
operating characteristics over recommended operating free-air temperature range, VOO .. 15 V,
Vref - 10 V, OUT1 and OUT2 at 0 V (unless otherwise noted)
PARAMETER
Relative accuracy
Gain error
::D
5
Digital inputs at VIL
UNIT
pA
NOTES: 2. Temperature coefficient is approximately -300 ppm/DC.
3. AV is the ratio of the DAC's external operational amplifier output voltage to the REF input voltage when using the internal
feedback resistor .
c:
o
-I
MAX
±1
VI - VIL
OUTl
."
::D
MIN
VI = 0 or VDD
TEST CONDITIONS
See Note 4
Digital inputs at VIH, See Notes 4 and 5
To ±0.05% FSR,
RL - 100 II,
Digital inputs changing from VIH to VIL, or VIL to ViH
Digital inputs at VIL.
V,e! = ±10 V sine wave at 100 kHz
MIN
MAX
±0.05
± 1.5
150
±0.1
UNIT
%FSR
%FS
ns
%FSR
NOTES: 4. Practical Full Scale Range (FSR) = V ref - 1 LSB.
5. Gain error is measured using the internal feedback resistor. Full-Scale (FS) = -Vref (1023/1024). Maximum gain change
from T A = 25°C to minimum or maximum temperature is 0.1 % FSR.
2-264
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 7526!l
PRODUCT
PREVIEW
TLC7533L TLC7533C
Advanced LinCMOSTM 1O·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTERS
PRINCIPLES OF OPERATION
The TLC7533 is a 10-bit multiplying DIA converter consisting of an inverted R-2R ladder and analog
switches. Binary-weighted currents are switched between the
and OUT2 bus lines by NMOS current
switches. The on-state resistances of these switches are binarily scaled so that the voltage drop across
and OUT2 bus lines should be maintained at the same potential so
every switch is the same. The
that the current in each ladder leg remains constant and is independent of the switch state. Most applications
require only the addition of an external operational amplifier and a voltage reference.
oun
oun
The equivalent circuit for all digital inputs low is shown in Figure 1 . With all of the digital inputs low, the
entire reference current, Iref, is switched to OUT2 as shown in Figure 2. The current source Iref/1024
represents the constant current flowing through the termination resistor of the R-2R ladder; while the current
source Ilkg represents leakage currents to the substrate. The output capacitances, Col 1) and Co (2), are
due to the capacitance of the NMOS current switches and vary with the switch state. With all digital inputs
low, all of the current switches and the entire resistor ladder are switched to the OUT2 bus line. The
capacitance appearing at OUT2 is a maximum of 100 pF; at
there is a maximum of 35 pF. With
all digital inputs high, all of the current switches are switched to OUT1, and 100 pF maximum appears
at
A maximum of 35 pF appears at OUT2 as shown in Figure 3.
oun
oun.
....
II)
·S
.
u
C3
c:
o
.+:
·iii
·S
C"
u
w
FIGURE 2. DAC EQUIVALENT CIRCUIT ALL DIGITAL INPUTS LOW
FIGURE 3. DAC EQUIVALENT CIRCUIT ALL DIGITAL INPUTS HIGH
a:
D..
....
(.)
:::>
c
oa:
D..
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-265
PRODUCT
PREVIEW
TLC7533L TLC7533C
Advanced LinCMOSTM 10-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
TYPICAL APPLICATION DATA
The TLC7533 is capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations
for 2-quadrant or 4-quadrant multiplication are shown in Figures'4 and 5. Input coding for unipolar and
bipolar operation are summarized in Tables 1 and 2, respectively.
VI
15 V
RA = 2 k!l
(see Note 6)
RB (see Note 6)
VDD
REF
BIT1
DIGITAL
INPUT
(D)
Vo
TLC7533
GND
FIGURE 4. UNIPOLAR OPERATION (2-QUADRANT MULTIPLICATION)
15 V
VI
RA - 2 k!l
(see Note 6)
VDD
DIGITAL
INPUT
20 kO
20 k!l
Vo
REF
BIT1
(D)
=
FIGURE 5. BIPOLAR OPERATION (4-QUADRANT OPERATION)
NOTES:
."
:JJ
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C
6. RA and RB are used only if. gain adjustment is required .
7. C1 (10-33 pF) may be required for phase compensation when using high·speed op·amps.
DAC DIGITAL INPUT
LSBt
MSB
c
o
-I
."
TABLE 2. BIPOLAR (OFFSET BINARY) CODE
TABLE 1. UNIPOLAR BINARY CODE
DAC DIGITAL INPUT
ANALOG OUTPUT
1111111111
1000000001
-VI (1023/1024)
-VI (513/1024)
1000000000
-VI (512/1024)
=
ANALOG OUTPUT
MSB
LSB*
1111111111
- Vref/2
+VI (511/512)
1000000001
+VI (1/512)
1000000000
0
0111111111
-VI (511/1024)
0111111111
-VI (1/512)
m
0000000001
-VI (1/1024)
0000000001
-VI (511/512)
0000000000
-VI (0/1024) = 0
0000000000
- VI (512/512)
m
~
t 1 LSB = 12 - 10) VI
t 1 LSB = 12 - 9) V)
:JJ
:::;
2-266
TEXAS
"!1
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
=
-VI
PRODUCT
PREVIEW
TLC7533L TLC7533C
Advanced LinCMOSTM 10·BIT MULTIPL VING
DIGITAL·TO·ANALOG CONVERTERS
TYPICAL APPLICATION OAT A
The TLC7533 may be used in voltage output operation as shown in Figure 6. In this configuration, the
input voltage is applied to the OUT 1 terminal and the output voltage is taken from the REF terminal. The
output voltage varies with the digital input code according to the equation shown. The output should be
buffered to prevent loading errors due to the high output resistance of this circuit (typically 10 kilohms).
The input voltage should not exceed 1.5 volts to ensure nonlinearity errors less than 1 LSB.
..
til
.
'5
(,)
U
15 V
c:
o
'';::
'iii
~-_VI
DIGITAL.-~--I BITl
'5
s 1.5V
C-
INPUT
(,)
..
o
c::(
(D)
CU
CU
FIGURE 6. VOLTAGE OUTPUT OPERATION
By connecting the DAC in the feedback of an op-amp as shown in Figure 7, the circuit behaves as a
programmable gain amplifier with the transfer function:
Va = -VI
where D
CO;4)
Digital Input Code (expressed as a decimal number)
DIGITAL
INPUT
Vo
(D)
GAIN TABLE
0
VONI
1023
-1.00097
-2
512
-4
256
-8
128
2
-512
1
-1024
0
open loop
FIGURE 7. PROGRAMMABLE GAIN AMPLIFIER
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-267
PRODUCT
PREVIEW
TLC75331. TLC7533C
Advanced LinCMOS'" 1O·BIT MULTIPLYING
DIGITAL·TO·ANALOG CONVERTERS
TYPICAL APPLICATION DATA
The programmable function generator shown in Figure 8 produces both square and triangular wave output
at a frequency determined by the digital input code. The digital input of the digitally programmable limit
detector shown in Figure 9 determines the trip point of the PASS/FAIL output. For a digital input of
0000000000, the threshold is 0 V, for 11111 11111, the threshold is - Vref.
o
~
CII
-.:Fl.f"--
('j
SQUARE WAVE·--.----4~......,.....w._<
»
.c
c
fir
15
4.7 k!l
v
~.
o·
::I
(")
:rc
=+
en
VDD
DIGITAL
INPUT
REF
--A./--
BIT1
>-.....--*_ TRIANGLE
TLC7533
WAVE
(D)
10~4 (8 R~ C
x)
t -
GND
Rx
....
~
10 k!l
FIGURE 8. PROGRAMMABLE FUNCTION GENERATOR
15V
v.et
DIGITALr-~---t BIT1
INPUT'
TLC7533
PASS/FAIL OUTPUT
(D)
GND
THRESHOLD -
....
"'U
::rJ
FIGURE 9. PROGRAMMABLE LIMIT DETECTOR
o
C
c:
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::rJ
m
S
m
~
2-268
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
-v.et(-E-)
1024
PRODUCT
PREVIEW
TLC7533L TLC7533C
Advanced LinCMOSTM 10·81T MULTIPLYING
DIGITAL·TO·ANALOG CONVERTERS
TYPICAL APPLICATION DATA
15 V
•
Vref
R1
...en
·S
Vo
...
u
(3
REF
DIGITAL
INPUT
10)
BITl
R2
C
TlC7533
o
+
GND
V o _ V ref
where:
'::'
'4:l
'iii
[~R2
~ ( R1 R1+R2)]
R1 +R2)_ 1024
·S
c::r
u
O:s 0 :s 1023
II(
FIGURE 10. MODIFIED SCALE· FACTOR AND OFFSET
15 V
!ca
Q
Vref
10 kll
10 kll
ANALOG
"""':"<--1 BITl
MAGNITUDE
BITS
•
:
L-,,L...-!BITl 0
Vo
TlC7533
5 kll
GND
SIGN B I T - - - - - . - - - - - - - - - - - - - - - '
FIGURE 11. 10·BIT AND SIGN MULTIPLYING DAC
~
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TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·269
•
2-270
TLC32040M, TLC320401
PRODUCT
PREVIEW
ANALOG INTERFACE CIRCUIT
FEBRUARY 19B7
•
•
14-Blt Dynamic Range ADC and DAC
•
10-Blt ADC and DAC Linearity Over Any
10-Blt Range
•
Variable ADC and DAC Sampling Rate Up to
19.200 Samples per Second
•
Switched-Capacitor Antialiasing Input Filter
and Output-Reconstruction Filter
•
•
•
J OR N PACKAGE
ITOP VIEW)
ADVANCED LlnCMOS" Silicon Gate Process
Technology
Serial Port for Direct Interface to
TMS32011. TMS32020. and TMS32025
Digital Processors
Synchronous or Asynchronous ADC and
DAC Conversion Rates with Programmable
Incremental ADC and DAC Conversion
Timing Adjustments
NU
RESET
EOOR
FSR
DR
MSTR ClK
VOO
REF
DGTl GNO
SHIFT ClK
EODX
DX
WORD/BYTE
FSX
•..
NU
NU
IN+
INAUX IN+
AUX INOUT+
OUT-
fI)
'S
e
C3
c
o
'iii
Vcc+
VccANlG GND
ANlG GND
NU
NU
~
'Sgo
u
c(
!
NU - Nonusable; no external connection
should be made to these pins
Q
Serial Port Interface to SN54299 or
SN74299 Serial-to-Parallel Shift Registers
for Parallel Interface to TMS32010 or Other
Digital Processors
description
The TLC32040 is a complete analog-to-digital and digital-to-analog input/output system on a single
monolithic CMOS chip. This device integrates a bandpass switched-capacitor antialiasing input filter. a
14-bit resolution A/D converter. four microprocessor-compatible serial port modes. a 14-bit resolution D/A
converter. and a low-pass switched-capacitor output-reconstruction filter. The device offers numerous
combinations of Master Clock input frequencies and conversion/sampling rates. which can be changed
via digital processor control.
Typical applications for this IC include modems (7.2-, 8-, 9.6-, 14.4-, and 19.2-kHz sampling rate), analog
interface for digital signal processors, speech recognition/storage systems, industrial process control,
biomedical instrumentation, acoustical signal processing, spectral analysis, data acquisition, and
instrumentation recorders. Four serial modes, which allow direct interface to the TMS32011, TMS32020,
and TMS32025 digital signal processors, are provided. Also, when the transmit and receive sections of
the Analog Interface Circuit (AIC) are operating synchronously, it will interface to two SN54299 or SN74299
serial-to-parallel shift registers. These serial-to-parallel shift registers can then interface in parallel to the
TMS32010, other digital signal processors, or external FIFO circuitry. Output data pulses are emitted to
inform the processor that data transmission is complete, or to allow the DSP to differentiate between two
transmitted bytes. A flexible control scheme is provided so that the functions of the IC can be selected
and adjusted coincidentally with signal processing via software control.
The antialiasing input filter comprises seventh-order and fourth-order CC-type (Chebyshev/elliptic
transitional) low-pass and high-pass filters, respectively, and a fourth-order equalizer. The input filter is
implemented in switched-capacitor technology and is preceded by a continuous time filter to eliminate
any possibility of aliasing caused by sampled data filtering. When no filtering is desired, the entire composite
filter can be switched out of the.signal path. A selectable, auxiliary, differential analog input is provided
for applications where more than one analog input is required.
ADVANCED
LinCMOS~
=at~:a~':t ~t.=~rT:'::'::'==
prod.eII without Rod...
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is a trademark of Texas Instruments Incorporated
PRODUCT PREVIEW do......11 conul. i.larmadon
D. praducll i. til•. latmlliva or daiB. (ilia...f
...II.p .. I.t. Chlra.toriatl. dltl a.~ .thor
~
w
Copyright @ 1987, Texas Instruments Incorporated
TEXAS ."
INSIRUMENTS
POST OFFICE BOX 865012 • DALLAS. TeXAS 75265
2-271
TLC32040M, TLC320401
ANALOG INTERFACE CIRCUIT
PRODUCT
PREVIEW
description (continued)
The A/D and D/A converters each have 14 bits of resolution with 10 bits of integral linearity guaranteed
over any 1O-bit range. The A/D and D/A architectures guarantee no missing codes and monotonic operation.
An internal voltage reference is provided to ease the design task and to provide complete control over
the performance of the IC. The internal voltage is brought out to a pin and is available to the designer.
Separate analog and digital voltage supplies and grounds are provided to minimize noise and ensure a wide
dynamic range. Also, the analog circuit path contains only differential circuitry to keep noise to an absolute
minimum. The only exception is the DAC sample-and-hold, which utilizes pseudo-differential circuitry.
II
The output-reconstruction filter is a seventh-order CC-type (Chebyshev/elliptic transitional low-pass filter
with a fourth-order equalizer) and is implemented in switched-capacitor technology. This filter is followed
by a continuous-time filter to eliminate images of the digitally encoded signal.
The TLC32040M is characterized for operation over the full military temperature range of - 55°C to 125°C,
and the TLC320401 is characterized for operation from - 40°C to 85 °C.
functional block diagram
FILTER
INAUX IN+
r-
AUX IN__
R~EI~S~TI~ _ _ _ _
I
J
I L.-.-~----'
L:_
FILTER
OUT + +-1------1
OUT - +-1------1
TRANSMIT SECTION
"'0
vcc+ vcc- ANLG DTGL VDD
GND GND (DIGI
:xl
o
C
cC')
-I
"'0
:xl
m
::;;
m
:E
2-272
TEXAS ~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MSTR CLK
SHIFT CLK
WOROIBYTE
ox
PRODUCT
PREVIEW
TLC32040M, TLC320401
ANALOG INTERFACE CIRCUIT
PRINCIPLES OF OPERATioN
analog input
Two sets of analog inputs, IN +, IN -, and AUX IN +, AUX IN -, are provided. Each input set can be operated
in either differential or single-ended modes, since sufficient common-mode range and rejection are provided.
Normally, the IN + and IN - inputs are used; however, the auxiliary inputs, AUX IN + and AUX IN -, can
be used if a second input is required. The gain for the IN +, IN -, and auxiliary AUX IN + and AUX INinputs can be programmed to either 1, 2, or 4 (see the Gain Control Table). Either input circuit can be
selected via software control. It is important to note that a wide dynamic range is assured by the differential
internal analog architecture and by the separate analog and digital voltage supplies and grounds.
•
...
!II
..
'S
u
U
C
Q
+l
AID bandpass filter. AID bandpass filter clocking. and AID conversion rate timing
'iii
The AID bandpass filter can be selected or bypassed via software control. The frequency response of this
filter is presented in the following pages. This response results when the switched-capacitor filter clock
frequency is 288 kHz. Several possible options can be used to attain a 288-kHz switched-capacitor filter
clock. When the filter clock frequency is not 288 kHz, the filter transfer function is frequency-scaled by
the ratio of the actual clock frequency to 288 kHz. The low-frequency roll-off of the high-pass section
is 300 kHz. However, the high-pass section low-frequency roll-off can be changed to 200 kHz with a metal
mask option.
'S
c::r
u
w
a:
Il.
tO
::)
o
o
a:
Il.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-273
TLC32040M, TLC320401
PRODUCT
PREVIEW
ANALOG INTERFACE CIRCUIT
PRINCIPLES OF OPERATION (continued)
asynchronous versus synchronous operation
If the transmit section of the AIC (low-pass filter and DAC) and receive section (bandpass filter and ADC)
are operated asynchronously, the low-pass and band-pass, filter clocks are independently generated from
the Master Clock signal. Also, the DIA and AID conversion rates are independently determined. If the
transmit and receive sections are operated synchronously, the low-pass filter clock drives both low-pass
and band-pass filters. In synchronous operation, the AID conversion timing is derived from, and is equal
to, the DIA conversion rate timing. (See description of the WORDIBYTE pin in the Pin Functional Description
Section.)
D/A converter performance specifications
Fundamental performance specifications for the D/A converter circuitry are presented in the DIA converter
operating characteristics section of the data sheet. The 01A converter has a sample-and-hold that is realized
with a switched-capacitor ladder.
system frequency response correction
Sin xIx correction circuitry is performed in digital signal processor software. The system frequency response
can be corrected via DSP software to ± 0.1 dB accurac;y to a band-edge of 3000 Hz for all sampling rates.
This correction is accomplished with a first-order digital correction filter, which requires only seven TMS320
instruction cycles. With a 200-ns instruction cycle, seven instructions represent an overhead factor of
only 1.1 % and 1.3% for sampling rates of 8 and 9.6 kHz, respectively (see the sin xIx Correction Section
for more details).
serial port
The serial port has four possible modes that are described in detail in the pin description section. These
modes are briefly described below.
1. The transmit and receive sections of the AIC are operated asynchronously, and the AIC serial
port interfaces directly with the TMS32011.
2. The transmit and receive sections of the AIC are operated asynchronously, and the AIC serial
port interfaces directly with the TMS32020 and the TMS32025.
3. The transmit and receive sections of the AIC are operated synchronously, and the AIC serial port
interfaces directly with the TMS32011.
4. The transmit and receive sections of the AIC are operate!;! synchronously, and the AIC serial port
interfaces directly with the TMS32020, TMS32025, or two SN54299 or SN74299 serial-toparallel shift registers, which can then interface in parallel to the TMS3201 0, to any other digital
signal processor, or to external FIFO circuitry.
."
::0
o
testing
C
c:
,An addendum accompanying this data sheet fully describes the test capabilities of the IC, provided by
the design.
o
-t
."
internal voltage reference
::0
m
~
m
:e
2-274
The internal reference eliminates the need for an external voltage reference, and thus provides overall circuit
cost reduction. Additionally, the internal reference makes the performance of the IC less susceptible to
noise. Thus, the internal reference eases the design task and provides complete control over the performance
of the IC. The internal reference is brought out to a pin and is available to the designer. To keep the amount
of noise on the reference signal to a minimum, an external capacitor may be connected between REF and
ANLG GND.
TEXAS''''
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TLC32040M. TLC320401
ANALOG INTERFACE CIRCUIT
PRODUCT
PREVIEW
PRINCIPLES OF OPERATION (continued)
reset
A reset function is provided to initiate serial communications between the AIC and DSP and to allow fast,
cost-effective testing during manufacturing. The reset function will initialize all AIC registers, including
the control register. The reset pin has an internal pull-up resistor. After a negative-going pulse on the RESET
pin, the AIC will be initialized. This initialization allows normal serial port communications activity to occur
between AIC and DSP (see AIC DX Data Word Format section).
•
...
II)
..
"5
u
(3
loopback
C
This feature allows the user to test the circuit remotely. In loop back, the OUT + and OUT - pins are internally
connected to the IN + and IN - pins. Thus, the DAC bits (d15 to d2), which are transmitted to the DX
pin, can be compared with the ADC bits (d15 to d2), which are received from the DR pin. An ideal comparison
would be that the bits on the DR pin equal the bits on the DX pin. However, in practice there will be some
difference in these bits due to the ADC and DAC output offsets.
The loopback feature is implemented with digital signal processor control by transmitting the appropriate
serial port bit to the control register (see AIC Data Word Format section):
PIN
NAME
NO.
ANlG GND
17,18
AUX IN+
24
o
"';::=
"iii
"5
C"
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a:
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C
oa:
~
.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-275
TLC32040M, TLC320401
ANALOG INTERFACE CIRCUIT
PRODUCT
PREVIEW
PIN
•
NAME
rnox
NO •
11
DESCRIPTION
I/O
0
(See the WORD/BYTE pin description and the Serial Port Timing Diagram.) During the word-mode
timing, this signal is a low-going pulse that occurs immediately after the 16 bits of D/A converter and control
or register information have been transmitted from the TMS320 serial port to the AIC. This signal can be used
C
to interrupt a microprocessor upon the completion of serial communications. Also, this signal can be used
....
I»
I»
to strobe and enable external serial-to-parallel shift registers, latches, or an external FIFO RAM, and to facilitate
parallel, data-bus communications between the AIC and the serial-to-parallel shift registers. During the bytemode timing, this signal goes low after the first byte has been transmitted from the TMS320 serial port to
~
.Q
the AIC and is kept low until the second byte has been transmitted. The TMS32011 can use this low-going
C
iii'
;::;.'
0'
signal to differentiate between the two bytes as to which is first and which is second.
-mi
4
0
=
the AIC via the DR pin of the AIC. The most significant DR bit will be present on the DR pin before -mi goes
(')
~'
c
In the serial transmission modes, which are described in the WORD/BYTE pin description, the FSR pin is held
low during bit transmission. When the ~ pin goes low, the TMS320 serial port will begin receiving bits from
low. (See Serial Port Timing and Internal Timing Configuration Diagrams.)
FSX
14
0
When this pin goes. low, the TMS320 serial port will begin transmitting bits to the AIC via the
DX pin AIC. In all serial transmission modes, which are described in the WORD/BYTE pin description, the FSX
pin is held low during bit transmission (see Serial Port Timing and Internal Timing Configuration Diagrams).
IN+
IN-
26
I
I
Noninverting input to analog input amplifier stage
Inverting input to analog input amplifier stage
I
The Master Clock signal is used to derive all the key logic .signals of the AIC, such as the Shift Clock, the
switched-capacitor filter clocks, and the A/D and D/A timing signals. The Internal Timing Configuration diagram
;::;:
til
MSTR ClK
25
6
shows how these key Signals are derived. The frequencies of these key signals are synchronous submultiples
of the Master Clock frequency to eliminate unwanted aliasing when the sampled analog signals are transferred
OUT+
22
0
between the switched-capacitor filters and the A/D and D/A converters (see the Internal Timing Configurationl.
Noninverting output of analog output power amplifier. Can drive transformer hybrids or high-impedance loads
OUT-
21
B
0
directly in either a differential or a single-ended configuration.
Inverting output of analog output power amplifier; functionally identical with and complementary to OUT + .
2
I
REF
REm
The internal voltage reference is brought out to this pin.
A reset function is provided to initialize the TA, TA', TB, RA, RA', RB, and control registers. This
reset function initiates serial communications between the AIC and DSP. The reset funetion will initialize all
AIC registers including the control register. After a negative-going pulse on the iirrE'f
pin, the AIC registers will be initialized to provide an B-kHz data conversion rate for a 5.1 B4-MHz master clock
input Signal. The conversion rate adjust registers, TA' and RA', will be reset to 1. The CONTROL register bits
will be reset as follows (see AIC DX Data Word Format section).
d7
=
1, d6
=
1, d5
=
1, d4
= 0,
d3
= 0,
d2
=
1
This initialization allows normal serial-port communication to occur between Ale and DSP. This pin has an
""0
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-I
internal pull-up resistor and is set to a high logic level unless it is pulled to ground.
SHIFT ClK
VDD
VCC+
VCC-
10
7
20
19
0
The Shift Clock signal is obtained by dividing the Master Clock signal frequency by four. This signal is used
to clock the serial data transfers of the AIC, described in the WORD/BYTE pin description
below (see the Serial Port Timing and Internal Timing Configuration diagram).
Digital supply voltage, 5 V ± 5%
Positive analog supply voltage, 5 V ± 5%
Negative analog supply voltage - 5 V ± 5%
""0
:J:I
-~
m
~
2-276
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 76266
PRODUCT
PREVIEW
TLC32040M. TLC320401
ANALOG INTERFACE CIRCUIT
PIN
NAME
NO.
WORD/BYTE 13
DESCRIPTION
I/O
I
This pin, in conjunction with a bit in the CONTROL register, is used to establish one of four serial
modes. These four serial modes are described below. This pin has an internal pull-up resistor and is set to
a logic high unless it is pulled to ground.,
..
fI)
Ale transmit and receive sections are operated asynchronously.
The following description applies when the Ale is configured to have asynchronous transmit and receive sections.
"S
~
If the appropriate data bit in the Control register is a 0. (see the AIC OX Data Word Format), the transmit and
receive sections will be asynchronous.
L
Serial port will directly interface with the serial port of the TMS32o.11 and communicates in two
t3
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o
B-bit bytes. The operation sequence is as follows (see Serial Port Timing diagrams).
~
1. The ffi or FSR pin is brought low.
2. One 8-bit byte is transmitted or one a-bit byte is received.
3. The
"iii
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rnox or EOOR pin is brought low.
4. The FSX or
FSR pin
0"
CJ
emits a positive frame-sync pulse that is
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Q.
2-277
PRODUCT
PREVIEW
TLC32040M, TLC320401
ANALOG INTERFACE CIRCUIT
INTERNAL TIMING CQNFIGURATION
MASTER CLOCK. - - - - - ,
DIVIDE BY 4
5.184 MHz (111
_ _ _ _ _ _ _ _ _ _ _ _ .J
10.368 MHz (21
SHIFT CLOCK
1.296 MHz (11
2.592 MHz (21
------,
OPTIONAL EXTERNAL CIRCUITRY
FOR FULL DUPlEX MODEMS
-'53.6kHz- - - - - ,
DIVIDE CLOCK (11
BY 135
COMMERCIAL
. EXTERNAL
FRONT-END
F~.!i.'i~~~DX
DIVIDER CIRCUITRY
I
I
I
I
IL __________
FILTERSt
:.JI
TX COUNTER B
TB-40; 7.2 kHz
TB-36; 8.0 kHz
TB-30; 9.6 kHz
TB - 20; 14.4 kHz
TB-15; 19.2 kHz
DIVIDER CIRCUITRY
L ____ _
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lOWPASS
SWITCHED
CAP FilTER
ClK - 288 kHz
SQUARE WAVE
RX COUNTER B
RB-40; 7.2 kHz
RB-36; 8.0 kHz
AB-30; 9.6 kHz
RB-20; 14.4 kHz
RB-15; 19.2 kHz
D/A
CONVERSION
FREQUENCY
BANDPASS
SWITCHED
CAP FilTER
CLK - 288 kHz
SQUARE WAVE
AID
CONVERSION
FREQUENCY
____ J
NOTE; Frequency 1, 20.736 MHz, is used to show how 153.6 kHz (for a commercially available modem split-band filter clockl, popular
speech and modem sampling signal frequencies, and an internal 288-kHz switched-capacitor filter clock can be derived synchronously
and as submultiples ofthe crystal oscillator frequency. Since these derived frequencies are synchronous submultiples of the crystal
frequency, aliasing does not occur as the sampled analog signal passes between the analog converter and switched-capacitor filter
stages. Frequency 2, 41.472 MHz, is used to show that the AIC can work with high-frequency signals, which are used by high-
speed digital signal processors.
tSplit-band filtering can alternatively be performed after the analog input function via software in the TMS320.
*These control bits are described in the AIC OX Data Word Format section.
m
-~
<
2-278
TEXAS . "
INSTRUMENTS
POST OFFice BOX 666012 • DALLAS, TEXAS 75265
PRODUCT
PREVIEW
TLC32040M, TLC320401
ANALOG INTERFACE CIRCUIT
explanation of internal timing configuration
All of the internal timing of the AIC is derived from the high-frequency clock signal that drives the Master
Clock input pin. The Shift Clock signal, which strobes the serial port data between the Ale and DSP, is
derived by dividing the Master Clock input signal frequency by four.
TX Counter A and TX Counter B, which are driven by the Master Clock signal, determine the D/A conversion
period timing. Similarly, RX Counter A and RX Counter B determine the A/D conversion period timing. In
order for the switched-capacitor low-pass and band-pass filters to meet their transfer function specifications,
the frequency of the clock inputs of the switched-capacitor filter must be 288 kHz. If the frequencies of
the clock inputs are not 288 kHz, the filter transfer function frequencies are scaled by the ratios of the
clock frequencies to 288 kHz. Thus, to obtain the specified filter responses, the combination of Master
Clock frequency and TX Counter A and RX Counter A values must yield 288-kHz switched-capacitor clock
signals. These 288-kHz clock signals can then be divided by the TX Counter Band RX Counter B to establish
the D/A and A/D conversion period timings.
- TX Counter A and TX Counter B are reloaded every D/A conversion period, while RX Counter A and RX
Counter B are reloaded every A/D conversion period. The TX Counter Band RX Counter B are loaded with
the values in the TB and RB Registers respectively. Via software control, the TX Counter A can be loaded
with either the T A Register, the T A Register less the TA' Register, or the TA Register plus the TA' Register.
By selecting the TA Register less the T A' Register option, the upcoming conversion period timing will occur
earlier by an amount of time that equals TA' times the signal period of the Master Clock. By selecting
the TA Register plus the TA' Register option, the upcoming conversion period timing will occur later by
an amount of time that equals TA' times the Signal period of the Master Clock. Thus, the D/A conversion
timing can be advanced or retarded. An identical ability to alter the A/D conversion timing is provided.
In this case, however, the RX Counter A can be programmed via software control with the RA Register,
the RA Register less the RA' Register, or the RA Register plus the RA' Register.
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The above feature is particularly useful for modem applications. This feature allows controlled changes
in the A/D and D/A conversion timing. This feature can be used to enhance signal-to-noise performance,
to perform frequency-tracking functions, and to generate nonstandard modem frequencies.
If the transmit and receive sections are configured to be synchronous (see WORD/BYTE pin description),
then both the low-pass and bandpass switched-capacitor filter clocks are derived from TX Counter A. Also,
both the D/A and A/D conversion timing are derived from the TX Counter A and TX Counter B. When the
transmit and receive sections are configured to be synchronous, the RX Counter A, RX Counter B, RA
Register, RA' Register, and RB Registers are not used.
~
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TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DAL.LAS. TEXAS 75265
2-279
PRODUCT
PREVIEW
TLC32040M, TLC320401
ANALOG INTERFACE CIRCUIT
AIC DR or OX word bit pattern
II
AID or DIA MSB
1 st bit sent
1st bit sent of 2nd byte
c
!
AID or DI A LSB
~
~
D6
D5
D4
D3
D2
D1
DO
AIC OX data word format section
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+- d15 (MSBI through d2 go to the D/A
;;'
:::J
COMMENTS
d151d141d131d121d111d10ld91dSld71dSld51d41d21d11dO
primary OX serial communication protocol
.... / 0
0
converter register
The TX and RX Counter A's are loaded with the TA and RA register
values. The TX and RX Counter B's are loaded with TB and RB
register values.
+- d15 (MSSI through d2 go to the D/A
(')
.... / 0
1
converter register
~'
The TX and RX Counter A's are loaded with the TA+TA' and
RA + RA' register values. The TX and RX Counter B's are loaded
with the TB and RB register values. NOTE: d1
c
~O,
dO = 1 will cause
the next 01 A and AID conversion periods to be changed by the
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en
addition of TA' and RA' Master Clock cycles, in which TA' and
RA' can be positive or negative or zero. Please refer to the
+- d15 (MSBI through d2 gO to the D/A
....
Conversion Period Adjustment Error Detection Table .
/
1
0
converter register
The TX and RX Counter A's are loaded with the TA- TA' and
RA - RA' register values. The TX and RX Counter B's are loaded
with the TB and RB register values. NOTE: d1 = 1, dO =0 will cause
the next DI A and AID conversion periods to be changed by the
subtraction of TA' and RA' Master Clock cycles, in which T A' and
RA' can be positive or negative or zero. Please refer to the
Conversion Period Adjustment Error Detection Table .
+- d 15 (MSBI through d2 go to the DI A
converter register
.... 1 1
1
The TX and RX Counter A's are loaded with the TA and RA register
values. The TX and RX Counter B's are loaded with the TB and
RB register values. After a delay of four Shift Clock cycles, a
secondary transmission will immediately follow to program the Ale
to operate in the desired configuration.
NOTE: Setting the two least significant bits to 1 in the normal transmission of DAC information (Primary Communications) to the AIC
will initiate Secondary Communications upon completion of the Primary Communications.
."
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Upon completion of the Primary Communication, FSX will remain high for four SHIFT CLOCK cycles and will then go low and initiate
the Secondary Communication. The timing specifications for the Primary and Secondary Communications are identical. In this manner,
the Secondary Communication, if initiated, is interleaved between successive Primary Communications. This interleaving prevents
the Secondary Communication from interfering with the Primary Communications and DAC timing, thus preventing the Ale from
skipping a DAC output.
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~
2-280
TEXAS·~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
PRODUCT
PREVIEW
TLC32040M, TLC320401
ANALOG INTERFACE CIRCUIT
secondary OX serial communication protocol
x x 1- to TA register -Ix x I+- to RA register -+ I
x I+' to TA' register -Ix I- to RA' register -I
x I+'- to TB register -Ix I- to RB register -I
x x x x x x x x d7 d6 d5 d4 d3 d2
I+-
0
0
d 13 and d6 are MSBs
0
1
d14 and d7 are 2's complement sign bits
1 0
1
-+I
CONTROL
REGISTER
•
d14 and d7 are MSBs
1
...en
d2 = 0/1 deletes/inserts the bandpass filter
·S
d3 = 0/1 disables/enables the loopback function
...
()
d4 = 0/1 disables/enables the AUX IN + and AUX IN - pins
d5' = 011 asynchronous/synchronous transmit and receive sections
(3
d6 = 0/1 gain control bits (see Gain Control Section)
C
o
d7 = 0/1 gain control bits (see Gain Control Section)
:een
reset function
·S
A reset function is provided to initiate serial communications between the AIC and DSP. The reset function
will initialize all AIC registers, including the control register. After a negative-going pulse on the RESET
pin, the AIC registers will be initialized to provide an 8-kHz AID and D/A conversion rate for a 5.184 MHz
master clock input signal. The AIC, excepting the CONTROL register, will be initialized as follows (see
AIC DX Data Word Format section):
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TEXAS ."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-281
PRODUCT
PREVIEW
TLC32040M, TLC320401
ANALOG INTERFACE CIRCUIT
AIC responses to improper conditions
•
The Ale has provisions for responding to improper conditions. These improper conditions and the response
of the Ale to these conditions are presented in Table 1 below:
AIC register constraints
c
The following constraints are placed on the contents of the Ale registers:
a
1.
2.
3.
4.
5.
6.
7.
I»
»
(')
.Q
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iii'
::+'
0'
::l
(')
TA register must be > 1.
TA' register can be either positive, negative, or zero.
RA register must be > 1 .
RA' register can be either positive, negative, or zero.
(TA register ± TA' register) must be > 1. .
(RA register ± RA' register) must be > 1.
TB register must be > 1.
TABLE 1. AIC RESPONSES TO IMPROPER CONDITIONS
:;'
(')
c:
;::;:
(/I
IMPROPER CONDITION
TA register
+ TA'
register
TA register - TA' register
=0
=
AIC RESPONSE
or 1
Reprogram TX Counter A with TA register value
0 or 1
TA register
+ TA' register < 0
MOD 64 arithmetic is used to ensure that a positive value is loaded into the TX Counter A,
RA register
+ RA' register
Reprogram RX Counter A with RA register value
Le., TA register
= 0 or 1
+ TA'register + 40 HEX is loaded into TX Counter A
RA register - RA I register = 0 or 1
RA register
+ RA' register
= 0 or 1
MOD 64 arithmetic is used to ensure that a positive value is loaded into RX Counter A, i.e.,
RA register + RA' register
AIC is shut down
TA register - 0 or 1
+ 40 HEX is loaded into RX Counter A
RA register = 0 or 1
TB register = 0 or 1
Reprogram TB register with 24 HEX
RB register = 0 or 1
Reprogram RB register with 24 HEX
Ale and DSP cannot communicate
Hold last DAC output
improper operation due to conversion times being too close together
-0
:::D
If the difference between two successive D/A conversion frame syncs is less that 1/19.2 kHz, the Ale
operates improperly. In this situation, the second D/A conversion frame sync occurs too quickly and there
is not enough time for the ongoing conversion to be completed. This situation can occur if the A and B
registers are improperly programmed or if the A + A' register or A - A' register result is too small. When
incrementally adjusting the conversion period via the A + A' register options, the designer should be very
careful not to violate this requirement (see diagram below).
o
~~~~E~~
FSX
I
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~
14-0NGOING
C
C
-I
t2 - t1
2:
I
CONVERSION~
1/19.2 kHz
-0
:::D
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:::m
~
2-282
. TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
PRODUCT
PREVIEW
TLC32040M, TLC320401
ANALOG INTERFACE CIRCUIT
asynchronous operation - more than one receive frame sync occurring between two transmit frame
syncs
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol is followed. The command to use the incremental conversion period adjust option is sent to the
AIC during a FSX frame sync. The ongoing conversion period is then adjusted. However, either Receive
Conversion Period A or B may be adjusted. For both transmit and receive conversion periods, the incremental
conversion period adjustment is performed near the end of the conversion period. Therefore, if there is
sufficient time between t1 and t2, the receive conversion period adjustment will be performed during Receive
Conversion Period A. Otherwise, the adjustment will be performed during Receive Conversion Period B.
The adjustment command only adjusts one transmit conversion period and one receive conversion period.
To adjust another pair of transmit and receive conversion periods, another command must be issued during
a.subsequent FSX frame (see figure below).
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en
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+=
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M"-------TRANSMIT CONVERSION PERIOD------i~"1
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~RECEIVE CONV. _ _ _ RECEIVE CONV.-tf
PERIOD A
PERIOD B
asynchronous operation - more than one transmit frame sync occurring between two receive frame
syncs
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol is followed. For both transmit and receive conversion periods, the incremental conversion period
adjustment is performed near the end of the conversion period. The command to use the incremental
conversion period adjust options is sent to the AIC during a FSX frame sync. The ongoing transmit conversion
period is then adjusted. However, three possibilities exist for the receive conversion period adjustment
in the diagram as shown in the figure below. If the adjustment command is issued during Transmit
Conversion Period A, Receive Conversion Period A will be adjusted if there is sufficient time between t1
and t2. Or, if there is not sufficient time between t1 and t2, Receive Conversion Period B will be adjusted.
Or, the receive portion of an adjustment command may be ignored if the adjustment command is sent
during a receive conversion period, which is already being or will be adjusted due to a prior adjustment
command. For example, if adjustment commands are issued during Transmit Conversion Periods A, B,
and C, the first two commands may cause Receive Conversion Periods A and B to be adjusted, while the
third receive adjustment command is ignored. The third adjustment command is ignored since it was issued
during Receive Conversion Period B, which already will be adjusted via the Transmit Conversion Period B
adjustment command.
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I
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I
....
I
14-TRANSMIT CONV ......... TRANSMIT CONV. • TRANSMIT CONV.-.r
PERIOD A
PERIOD B
PERIOD C
12
FSIiU
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~RECEIVE CONVERSION PERIOD A
U
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I
RECEIVE CONVERSION PERIOD B-----.!~I
TEXAS . "
INstRUMENTS
POST OFFIce BOX 655012 • DALLAS. TEXAS 75265
::l
C
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a:::
~
2-283
PRODUCT
PREVIEW
TLC32D4DM, TLC32D401
ANALOG INTERFACE CIRCUIT
asynchronous operation - more than one set of primary and secondary DX serial communication
occurring between two receive frame sync (see Ale DX Data Word Format section)
The TA, TA', TB, and control register information that is transmitted in the secondary communications
is always accepted and is applied during the ongoing transmit conversion period. If there is sufficient time
between t1 and t2, the TA, RA', and RB register information, which is sent during Transmit Conversion
Period A, will be applied to Receive Conversion Period A. Otherwise, this information will be applied during
, Receive Conversion Period B. If RA, RA', and RB register information has already been received and is
being applied during an ongoing conversion period, any subsequent RA, RA', or RB information that is
received during this receive conversion period will be disregarded (see diagram below).
..
C
III
III
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PRIMARY
iii'
tl
SECONDARY
;:;
r----,
PRIMARY
SECONDARY
PRIMARY
,.---""
----.,
SECONDARY
0'
:::s
(')
TRANSMIT
TRANSMIT
TRANSMIT
M----CONVERSION---_.M----CONVERSION----Mt----CONVERSION----M
PERIOD A
PERIOD 8
PERIOD C
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+- RECEIVE CONVERSION_-I....._ _ _ _ _ _ RECEIVE CONVERSION PERIOD 8------...1
PERIOD A
.....
'absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC + (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 15 V
Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to 15 V
Output voltage, Vo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. -0.3 V to 15 V
Input voltage, VI .................................................. - 0.3 V to 15 V
Digital ground voltage .............................................. - 0.3 V to 15 V
Operating free-air temperature range: TLC32040M ....................... - 55°C to 125°C
TLC320401 ......................... -40°C to 85°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............ 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ............ 260°C
NOTE 1:· Voltage values for maximum ratings are with respect to
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2-284
TEXAS •
INsrRUMENTS
POST OFFICE BOX 655012 • DALLAS; TEXAS 75265
PRODUCT
PREVIEW
TLC32040M. TLC320401
ANALOG INTERFACE CIRCUIT
recommended operating conditions
PARAMETER
MIN
NOM
MAX
UNIT
Vcc + (see Note 2)
4.75
5
5.25
Supply voltage, V CC _ (see Note 2)
-4.75
-5
-5.25
V
V
5
5.25
V
Supply voltage,
Digital supply voltage, VDD (see Note 2)
4.75
Digital ground voltage with respect to ANLG GND, DGTL GND
0
High-level input voltage, VIH
Low-level input voltage, VIL (see Note 3)
Load resistance at OUT + and/or OUT -, RL
VOO+O.3
V
-0.3
0.8
V
300
100
0.075
Analog input amplif,er common mode input voltage (see Note 5)
AID or D/A conversion rate
Operating free-air temperature, T A
NOTES:
..
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Load capacitance at OUT + and/or OUT -, CL
MSTR CLK frequency (see Note 4)
...en
V
2
5
10.368
pF
± 1.5
V
19.2
kHz
I TLC32040M
-55
125
TLC320401
-40
85
I:
o
MHz
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Gain relative to gain at 1 kHz
TEST CONDITIONS
Input signal reference is 0 dB
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C
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f = 100 Hz
f-150Hz
300 Hz s f s 3.4 kHz
f =4 kHz
f l!: 4.5 kHz
MIN
MAX
UNIT
-0.5
-45
-33
0.6
-15
-50
dB
::;
o·:::J
bandpass filter transfer function with 200-Hz high-pass roll-off (see curvesl, SCF clock
frequency - 288 kHz, input (IN + - IN -I is a ± 3-V sinewave (see Note 91
(')
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c
PARAMETER
it
Gain relative to gain at 1 kHz
TEST CONDITIONS
Input signal reference is 0 dB
f = 100 Hz
f-150Hz
300 Hz s f s 3.4 kHz
f = 4 kHz
f l!: 4.5 kHz
MIN
MAX
UNIT
-37
-12
-0.5
0.6
-15
-50
dB
MAX
UNIT
0.5
-5
-30
-50
dB
MAX
UNIT
low-pass filter transfer function, SCF clock frequency - 288 kHz (see Note 91
PARAMETER
Gain relative to gain at 1 kHz
TEST CONDITIONS
Output signal reference is 0 dB
f s 3.4 kHz
f = 3.5 kHz
f=4kHz
f l!: 4.4 kHz
MIN
-0.5
serial port
VOH
VOL
II
CI
Co
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PARAMETER
High·level output voltage
Low-level output voltage
Input current
Input capacitance
Output capacitance
TEST CONDITIONS
MIN
IOH = -3oopA
IOL = 2 mA
2.4
Typt
0.4
±10
15
15
V
V
pA
pF
pF
t All typical values are at TA = 25 ·e.
NOTE 9: The above filter specifications are guaranteed for a switched'capacitor filter clock range of 288 kHz. For switched-capacitor filter
clocks at frequencies oth9r than 288 kHz, the filter response is shifted by the ratio of switched-capacitor filter clock frequency
to 288 kHz.
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....
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S
~
2-288
TEXAS ~
INSlRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75266
PRODUCT
PREVIEW
TLC32040M. TLC320401
ANALOG INTERFACE CIRCUIT
operating characteristics over recommended operating free-air temperature range. Vcc+
Vcc- = -5 V. VOO = 5 V
5 V.
II
AID converter (2's complement output. 14-bit resolution)
PARAMETER
Integral linearity, f
~
TEST CONDITIONS
4.5 kHz to 19.2 kHz
ISee Note 10)
MIN
Typt
UNIT
Sixteenth full scale
±Yz
bit 1
bit 2 thru bit 11
Eighth lull scale
bit 2
bit 3 thru bit 1 2
Quarter full scale
±%
±%
bit 4 thru bit 13
Hall lull scale
±%
bit 4
bit 5 thru bit 14
Full scale
±%
bit 5
1
Conversion rate
Signal-ta-quantization distortion ratio (for input signals> - 15 dBm
m at the ADC input
1/1
"~
::::I
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bit 3
20
60
in the 300 Hz to 3400 Hz band)
Equivalent input noise (relative to 600
MAX
bit 1 thru bit 10
...
U
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kHz
"';::::
dB
Inputs grounded
p..V rms
75
"iii
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C"
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«
DIA converter (2's complement input. 14-bit resolution)
PARAMETER
Integral linearity, f
~
TEST CONDITIONS
4.5 kHz to 19.2 kHz
ISee Note 10)
MIN
Typt
MAX
bit 1 thru bit 10
Sixteenth full scale
±%
bit 1
bit 2 thru bit 11
Eighth full scale
±%
bit 2
bit 3 thru bit 12
Quarter full scale
±%
bit 3
bit 4 thru bit 13
Hall lull scale
±Y2
bit 4
bit 5 thru bit 14
Full scale
±%
bit 5
10
Settling time
Conversion time
1
...caca
UNIT
C
~s
20
kHz
noise (measurement includes low-pass and bandpass switched-capacitor filters)
PARAMETER
Transmit noises
TEST CONDITIONS
I single-ended
I differential
Receive noise (see Note 11)
OX input
~
TYP
00000000000000, constant input code
Inputs grounded, gain
=
1
MAX
125
250
150
UNIT
p,V rms
p,V rms
timing requirements
serial port -
Ale input signals
MIN
PARAMETER
MAX
UNIT
ns
tclMCLKI
Master clock cycle time
95
trIMCLK)
Master clock rise time
10
ns
tIIMCLK)
Master clock fall time
10
ns
42%
Master clock duty cycle
tsulDX)
DX setup time belore SCLKt
thlDX)
DX hold time after SCLKt
~
58%
20
ns
t clSCLKI/2
ns
W
>
w
t All typical values are at T A ~ 25°C.
NOTES: 10. Integral linearity for the AID and D/A converters is guaranteed over the conversion frequency range of 4.5 kHz to 19.2 kHz.
Over this range the slew rates of the AID and D/A converters' sample-and-hold circuits are adequate to guarantee the above
integral linearity specifications.
11 . This noise is referred to the input with a buffer gain of one. If the buffer gain is two or four, the noise figure will be correspondingly
reduced. The noise is computed by statistically evaluating the digital output of the AID converter.
a:
c..
....
(,,)
;:)
C
oa:
c..
TEXAS
-Ij}
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-289
PRODUCT
PREVIEW
TLC32040M, TLC320401
ANALOG INTERFACE .CIRCUIT
II
..
C
I»
I»
»
operating characteristics over recommended operating free-air temperature range.
VCC- - - 5 V. VDD = 5 V (cont~nuedl
serial port - AIC output signals
PARAMETER
Shift clock (SCLK) cycle time
tc(SCLK)
tfISCLK)
trISCLK)
td(CH-FLI
tdICH-FH)
iir
ci"
td(CH-DR)
tdw(CH-EL)
tdw(CH-EH)
o
tflEODXI
tf(EODR)
;::;:'
::::s
~.
c
;::;:'
UI
MIN
MAX
38
Shift clock (SCLK) fall time
Shift clock (SCLK) rise time
Shift clock (SCLK) duty cycle
n
.Q
C
Vcc+ - 5 V.
50
50
55
ns
ns
Delay from SCLKt to FSR/FSX.
Delay from SCLKt to FSR/FSK)t
90
90
DR valid after SCLKt
90
90
90
15
ns
ns
ns
45
Delay from SCLKt to EODX/EODR. in word mode
Delay from SCLKt to EODX/EODRt in word mode
EODX fall time
tdbICH-EL)
EODR fall time
Delay from SCLKt to EODX/EODR. in byte mode
tdbICH-EHI
Delay from SCLKt to EODX/EODRt in byte mode
15
100
100
analog input signal required for full-scale AID conversion
CONTROL REGISTER BITS
d7
d6
INPUT CONFIGURATIONS
Differential configuration
Analog input = IN+ - IN= AUX+ - AUX-
1
0
1
0
Single-ended configuration
1
0
Analog input = IN + - ANLG GND
= AUX + - ANLG GND
ANALOG INPUT
±6 V
RESULT
full-scale
0
1
1
+3 V
±1.5 V
±3 V
full-scale
full-scale
half-scale
±3 V
±1.5 V
full-scale
full-scale
0
1
0
0
1
R
IN +
-"""""-1
~
R
IN - -1IN~t-I
TO MUX
'"tJ
o
C
c:
(")
-I
Rfb
Rfb - R for d6 d6 Rfb - 2R for d6
Rtb - 4R for d6
1. d7 O. d7 - 1. d7
- O. d7
1
0
- 0
- 1
FIGURE 1. IN + AND IN - GAIN CONTROL CIRCUITRY
'"tJ
::0
m
S
m
:e
2-290
AID CONVERSION
1
·0
Rfb
::0
UNIT
ns
TEXAS
.Jf
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75286
%
ns
ns
ns
ns
ns
ns
PRODUCT
PREVIEW
TLC32040M, TLC320401
ANALOG INTERFACE CIRCUIT
R
AUX IN+-"M............
•
~
R
AUX IN - -'VV............
..._!TOMUX
II)
+'
'S(J
...
C3
Rib
Rib - Rlord6 d6 Rib - 2Rlord6
Rib - 4R lor d6
1. d7 O. d7 '" 1. d7
= O. d7
r::::
1
0
o
'';:'
- 0
- 1
'iii
'S
C"
FIGURE 2. AUXILIARY INPUT CIRCUITRY
(J
w
a::
D..
....
o
::l
C
o
a::
D..
TEXAS . "
INSTRUMENTS
POST OFfiCE BOX 655012 • DALLAS, TEXAS 75265
2-291
TLC32040M, TLC320401·
ANALOG INTERFACE CIRCUIT
PRODUCT
PREVIEW
correction filter
EI
To compensate for the sin xIx roll-off of the Ale: the first-order correction filter. which is shown below.
is recommended.
t---------.....- ...
U(i+11
The difference equation for this correction filter is:
Yi+1 = p2(1-p1) (Ui+1)+p1 y1
where the constant p1 determines the pole locations.
The resulting squared magnitude transfer function is:
IH(f)12 =
p22 (1 ~p1)2
1 - 2p1 cos(2 11" f/fs) + p1 2
"'0
::zJ
o
C
c:
(")
-I
"'0
::zJ
m
S
~
2-292
.
TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
Y(i+ 11
PRODUCT
PREVIEW
TLC32040M, TLC320401
ANALOG INTERFACE CIRCUIT
correction results
Table 3 below shows the optimum p values and the corresponding correction results for 8000 Hz and
9600 Hz sampling rates.
TABLE 3
II...
II)
f (Hz)
300
600
900
1200
1500
1800
2100
2400
2700
3000
ERROR (dB)
ERROR (dB)
fs - 8000 Hz
fs - 9600 Hz
p1 - -0.14813
p2 - 0.9888
-0.099
-0.089
-0.054
-0.002
0.041
0.079
0.100
0.091
-0.043
-0.102
p1 - -0.1307
p2 - 0.9951
-0.043
-0.043
0
0
0
0.043
0.043
0.043
0
-0.043
..
"5
u
C3
c
o
:-2
II)
"5
8"
w
a:
c..
tO
~
C
oa:
c..
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-293
PRODUCT
PREVIEW
TLC32040M, TLC320401
ANALOG INTERFACE CIRCUIT
byte-mode timing
II
c
;
~lf"tflSClKI
~lf"trISCLKI
2V
SHIFT ClK
I 0.8V
tclICH-Fll-+j ~
,
I I
I I
I'
I
0.8 V
I
~ k-tclICH-FHI
l>
:
n
~
lr!dICH-DRI
iii"
a:o
OX
(')
~;:x-on
08
~
~
EODR, EODX
c
::+
o
0908
07
1
~
06~
--I,.-v-
word-mode timing
r------ttclSClKI
2V
SHIFT ClK
I
0.8 VI
_ _~
--.'if-tdICH-Fll II
0. 8V
\1
DR
015
t
I:
,
:
i,
tdICH-FH ......
~
• .., "'"",....;.
_ _ __
I
I
11
I~ !t-tdICH-DRI
2V
:
~ 013 (012G}}:X"i>D...D_1_ _D;;..0'-+i_-+____
I
i
tsulDXI~ k--
DX----~~
~'I
---t je-thIOX)
tdwICH-El~ k- .-.j if-tclw(CH-EH)
' ; 2v
"
'LJ'
O.BV
FIGURE 3, SERIAL PORT TIMING
~
o
c
c:
(')
-I
"'0
::J:J
m
<
-
~
2-294
I
tdbICH-EH~ It-t",~0",.8:",:V_ _ _ _ _ _ _ _ _--If'~' _ _ _ _ _
;1
-S S
FX,FR
00
I
DON'T CARE
_ _ _ _ __' _I.-_t...,hl,OJ_X_I_ _ _----t--.r--tdbICH-Ell
~.
:
01
I
,
tsulDXI..... If-
.
:::s
I'
------flI.".-v-
1 .,.._
0.8vt"-_ _-if_J-
:
DR-'--0-1-5--"'~""'0"'1-:4~0~1ttill
~
c
tdICH-FH.-.! ~
".....,...-_ _ _ _ _---.."
~,me ~_~,---_f12V
.Q
1
~ if-tclICH-Fll
TEXAs
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
PRODUCT
PREVIEW
TLC32040M, TLC320401
ANALOG INTERFACE CIRCUIT
TMS32010
m
SN74LS299
..... S1
i5EiiI
QH'
•
OR
112
y
AO/PAO f - A
08-016
I,
\,
A1/PA1 f-B
A-H
G2
,
G1
.
U
r--Cl=
SN74LS299
~
:1
":;
TLC32040
SR'-
I - S1
SN74LS138
"7
li1
[7
Yi I V7 I -
A2/PA2 ' - C
< f--
SO
Vi I--
QH'
U
c
o
"."iii
":;
SHIFT CLK
>-
SO
/
00-015
00-07
'\
00-015
\
'\
WE
c:r
u
c(
A-H
SR
ca
OX
7
1ii
c
~
0.-/
rL'
CLK OUT
MSTR CLK
mox
iN'i'
FIGURE 4. TLC32010-TLC32040 INTERFACE CIRCUIT
in instruction timing
ClKOUT _ _--'
I
so. (IT
00-015
I
I ~I--------------------------L-_ _~I"'.
J
I
I
______________~c:~~~I>----------------------(
VALID
)
out instruction timing
~
w
CLKOUT _ _.....J
:>w
a:
Q.
SN74LS138 Y1
....
SN74lS299 ClK
~D15 ----------------«~V~A~l~JD~~)~--------------------
FIGURE 5. TMS32010-TMS32040 INTERFACE TIMING
(J
::l
C
oa:
0..
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS, TEXAS 75265
2-295
TLC32040M. TLC320401
PRODUCT
PREVIEW
ANALOG INTERFACE CIRCUIT
AIC TRANSMIT CHANNEL FILTER
•
0.3
10
Magnitude
0
-10
c
0.25
'\
-20
!I»
III
"tI
..
.Ec
..
:iE
I
:J>
n
"tI
C
CD
J:I
(ii'
::+
0'
-30
See Note
Kf' /
/ r\J. 1 \X
\
1\
-50
-60
L
-70
::::I
\
iI""\.
--'
~'
-80
V
C
-90
::+
en
I
0.1
>
to
a;
0.05
...
Q
::I
0.05
e
..,~
0.1
a:
0
--
r-r-See Note A
I--+-See Note C
(')
E
0.15
1\
Group Delay
-40
.
0.2
CI
.
OJ
0.15
0.2
o
2
3
5
4
Frequency-kHz
NOTES: A;
B.
C.
D.
Maximum relative delay ( 0 Hz to 600 Hz) = 125 ~s.
Maximum relative delay (600 Hz to 3000 Hz) = ± 50 ~.
Absolute delay (600 Hz to 3000 Hz) = 700 ~s.
VCC+ = 5 V, VCC- = -5 V, SCF clock f = 288 kHz, input
=
±3-V sinewave, TA
=
25°C.
FIGURE 6
AIC RECEIVE CHANNEL FILTER (300 Hz)
10
0.35
Magnitu~e
See Note A
0
0.3
\
-20
I
-30
.ec
..'"
:iE
-40
~
-50
-60
"'C
:J:I
-70
o
\l /\ v.. V
LSee Note B
c:
-90
0
(")
-I
"'C
:J:I
m
<
\
0.05
0
0.05
.
I
>
a;
Q
...
::I
e
CI
..
>
~
OJ
a:
0.1
\
See Note C-
2
0.1
\
\
\y
1\
-80
C
0.15
Group Delay
\ /
E
0.2
\
III
"tI
.
0.25
-10
0.15
3
4
5
Frequency-kHz
NOTES: A. Maximum relative delay (200 Hz to 600 Hz) = 3350 ~s.
B. Maximum relative delay (600 Hz to 3000 Hz) = ± 50 ~s.
c. Absolute delay (600 Hz to 3000 Hz) = 1230 ~s.
D. VCC+ = -5 V, VCC- '" -5 V, SCF clock f = 288 kHz, input
iii
=
±3-V sinewave, TA
FIGURE 7
~
2-296
TEXAS ",
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
=
25°C.
PRODUCT
PREVIEW
TLC32040M. TLC320401
ANALOG INTERFACE CIRCUIT
AIR RECEIVE CHANNEL FILTER (200 Hz)
0.3
10
Magnitude
0
0.25
rS~e N~te A
-10
0.2
1\
-20
"a
..
I
"a
~a>
II
:E
0.15
\
aI
-30
-40
-,
- -:; J
c-
rrou p Dela
-50
-60 -70
0.05
\
\
\
See Note B
0.1
\
'rJ
0
0.05
See Note C
-90
2
I
>-
~
Q
Q.
e"
..,..
c:l
~
II:
0.15
-80
o
E
>
"\ 0.1
1 1
In
3
4
5
0.2
II
..
tn
.
"S
u
U
c
o
"~
"iii
"S
C"
U
c(
5I'G
Q
Frequency- kHz
NOTES: A.
B.
C.
D.
Maximum relative delay (200 Hz to 600 Hz) = 3350 ~s.
Maximum relative delay (600 Hz to 3000 Hz) = ± 50 ~s.
Absolute delay (600 Hz to 3000. Hz) = 1080 ~s.
VCC+ = -5 V, VCC- = -5 V, SCF clock f = 288 kHz, input = ±3-V sinewave, TA = 25°C.
FIGURE 8
~
w
:>w
a:
a..
~
CJ
:::)
C
oa:
a..
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 15265
2-297
C
....
I»
I»
»
n
.c
c
iii'
;:;'
0'
:::l
(")
:;i'
n
c
;:;'
til
2-298
Alphanumeric Index
Selection Guide
Cross-Reference Guide
Data Sheets
Display Drivers
Data Sheets
Cross-Reference Guide
Data Sheets
Cross-Reference Guide
Data Sheets
Data Sheets
Data Sheets
3-1
C
Iii"
iii
"C
<
..cr
C
.
CD
(/)
3-2
SN554268. SN554278
AC PLASMA DISPLAY DRIVERS
D2520. MARCH 1979-REVISED OCTOBER 19B6
•
90-V Output Swing
•
CMOS-Compatible Inputs
•
Quad Drivers with Independent Addressing
of Each Gate for Serial or Parallel
Applications
•
High Data Input Impedance . . . 1 MO Typ
•
30-mA Clamp Diodes on Output
SN55426B ... J
DUAL-IN-L1NE PACKAGE
(TOP VIEW)
1A
2A
3A
4A
VCC1
GND
VCC2
4Y
3Y
M
S
NC
2Y
1Y
description
The SN55426B and SN55427B are monolithic
integrated-circuit plasma display drivers. The
logic of the two drivers is complementary to
permit controlled writing or erasing at a specified
point on the display. The '426B non inverting
pulser is normally near ground potential and is
pulsed near VCC2; the' 427B inverting pulser is
normally near VCC2 potential and is pulsed near
ground potential. The devices are designed to
accept CMOS logic input signals and drive one
display line per output.
SN55427B ... J
DUAL-IN-L1NE PACKAGE
(TOP VIEW)
1A
2A
S
NC
2Y
1Y
..
UI
Q)
>
'ii:
3A
4A
VCC1
GND
VCC2
4Y
3Y
M
•
Q
>
IV
Q.
I/)
o
NC - No internal connection
There are four gates per package with individual
data inputs. Additionally, each device has a
strobe and a multiplex input controlling all four
gates. The devices require two powe~ supplies:
the logic section power supply VCC1, and the
high-voltage bias supply VCC2. VCC2 controls
the magnitude of the output swing.
FUNCTION TABLE
OUTPUTS
INPUTS
Each output is designed to sustain
20-milliampere switching transients on the
output. Each output is also protected by source
and sink clamp diodes with 30-milliampere
current capability. Each device is designed to be
operated at 50 kilohertz but may be operated as
high as 85 kilohertz.
A
M
S
'426B '427B
L
X
H
L
X
X
L
X
X
L
H
X
L
L
H
H
H
H
H
L
H
~
high level. L
X
=
irrelevant
~
low level.
The multiplex and strobe inputs (inputs M and
S, respectively) act on all four gates
simultaneously and aid in plasma panel design.
The
SN55426B and
SN55427B
are
characterized for operation over the full military
temperature range of - 55°C to 125°C.
PRODUCTION DATA documents contain information
currant as of publication date. Products conform to
specifications par the terms of Texas Instruments
:~~~::~~i~8i~:I~~i ~!:ti:~ti:; :1~O::~:~:':r~~S
not
TEXAS
"-11
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
Copyright © 1984, Texas Instruments Incorporated
3-3
SN554268. SN554278
AC PLASMA DISPLAy'DRIVERS
logic symbols t
'426B
'427B
CMOS/PLASMA
DISP
CMOS/PLASMA
DISP
M (3)
M (3)
S (4)
S (4)
lA
2A
3A
4A
(1)
1A (1)
(2)
(14)
(131
2A (2)
3A (14)
4A (131
(7) 1V
(6) 2V
(B) 3V
(9) 4Y
tThese symbols are in accordance with ANSIIIEEE Std 91-1984
and lEe Publication 617-12.
logic diagrams (positive logic)
'4278
'4268
M (31
S (41
M
S
(4)
lA
(1)
2A
(2)
1V
1A (1)
(31
2V
2A (2)
3V
3A (14)
3A (14)
4V
4A (13)
4V
4A (13)
POSITIVE LOGIC: V • A·M·S
POSITIVE LOGIC: V •
schematics of inputs and outputs
EQUIVALENT OF EACH A, M. OR S INPUT
TYPICAL OF ALL OUTPUTS
VCC2
,::~~::
3-4
~-+--....-4-- OUTPUT
TEXAS . "
INSlRUMENlS
POST OFFICE BOX 665012 • DALLAS. TeXAS 76285
A-ir.S
SN55426B, SN55427B
AC PLASMA DISPLAY DRIVERS
;
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCCl (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 V
Supply voltage, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 95 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 5 V
Continuous output current, 10 ............................................... 20 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2). . . . . . .. 800 mW
Operating free-air temperature range ................................ "
- 55°C to 125°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds ...................... 300°C
NOTES:
1. All voltage values are with respect to network ground terminal.
2. For operation above 25·C free-air temperature. refer to Dissipation Derating Curves in Appendix A. In the J package, SN55426B
and SN55427B chips are alloy mounted.
recommended operating conditions
Supply voltage for logic section, VCCl
Supply voltage for output section, VCC2
High-level input voltage, VIH
Low-level input voltage, VIL
Strobe frequency
Duration of strobe pulse
Operating free-air temperature, T A
PARAMETER
VOL
Low-level output voltage
VOK
Output clamp voltage
ICCl
ICC2
Supply current, output section
High-level input current
14
90
50
3
85
85
V
V
V
kHz
kHz
125
"s
·C
= 12 V
VCCl = 12 V,
VCC2 = 90 V,
r
10
10
10
= -1 mA
= -15mA
= 1 mA
10 - 15 mA
10
Typt
MIN
ICCl (av) Average supply current, logic section
ICC2(av) Average supply current, output section
tw = 5"s,
No load
-30mA
12
50
10
1.1
0.1
10
All inputs at 12 V
All outputs high
All outputs low
f
MAX
UNIT
V
4
V
8
VCC2+ 0.8 VCC2+2
-0.9
-2
VIH
No load
v
5
VCC2- 4 VCC2- 1
VCC2-8 VCC2-1.8
2
3.5
= 30mA
10 -
UNIT
- 55 °C to 125 °C (unless otherwise
TEST CONDITIONS
VIH = 7 V.
VIL = 3 V
VIH = 7 V,
VIL = 3 V
Output high,
Output low,
IA
M, S
Supply current, logic section
IIH
MAX
12
70
1.5
-55
electrical charecteristics. VCC1 - 12 V. VCC2 - 70 V. T A noted)
High-level output voltage
NOM
10
40
7
0
0
Data input frequency
VOH
MIN
•
= 50 kHz,
V
60
200
p.A
15
1.9
0.6
mA
mA
mA
mA
1.3
t All typical values are at 25 ·C.
switching characteristics. VCC1 - 12 V. VCC2 - 70 V. TA - 25°C
tpLH
tpHL
PARAMETER
Propagation delay time, low-to-high-Ievel output
Propagation delay time, high-to-Iow-Ievel output
T
T
I
TEST CONDITIONS
CL = 20 pF,
RL = 100 kll,
See Figure 1
TEXAs
-If
INSTRUMENTS
POST OFFice BOX 655012 • DALLAS, TEXAS 76265
I MIN
TVP
MAX
I
0.7
1.2
I
0.3
0.8
I UNIT I
I
I
p.S
p.S
I
I
3-5
S1554268, SI554278
AC PLASMA DISPLAY DRIVERS
PARAMETER MEASUREMENT INFORMATION
VCC1
VCC2
~<10ns
<10ns--+t-ll
1 I
}-+-....--~.... OUTPUT
INPUT
CL -20pF
(See Note BI
:
1
7;".9Q%=----""""g""II%""."""K
r---I
-10V
!'\
--..,;J111%
I
I
111%
OV
te-'PLH~
.....PHL~
I
I
~g-II%-----+-~- 1- - - -- VOH
I
'426B OUTPUT
"'----VOL
CL-20pF
(see Note B)
'4278 OUTPUT
9Q%~1 VOH
+-...J/i1- -
\
111%
I~~_ _ _ _
.....~-.....~OUTPUT
~+
1
"'-'PHL~
1
It-'PLH--"
11 SN55427B
VOLTAGE WAVEFORMS
TEST CIRCUITS
NOTES: A. The pulse generator has the following characteristics: Zo = 50 D, PRR :s 50 kHz, tw = 5 !'fl.
B. CL includes probe and jig capacitance.
FIGURE 1. SWITCHING TIMES
3-6
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
-
-VOL
SN75491. SN75491A. SN75492. SN75492A
MOS·TO·LED DRIVERS
02355. OCTOBER 1972-REVISEO SEPTEMBER 1986
QUAD SEGMENT DRIVER AND HEX DIGIT DRIVER FOR INTERFACING
BETWEEN MOS AND L1GHT·EMITTING·DIODE (LED) DISPLAYS
•
50·mA Source or Sink Capability
('491, '491A)
•
250·mA Sink Capability ('492, '492A)
•
Rated for 10·V Operation ('491, '492)
•
Rated for 20·V Operation ('491A, '492A)
•
Low Input Current for MOS Compatabillty
•
Low Standby Power
•
High·Gain Darlington Circuits
SN75491.SN75491A
N DUAL-IN-L1NE PACKAGE
(TOPVIEWI
lA
lE
lC
GND
2C
2E
2A
4A
4E
4C
'.
Vss
3C
3E
3A
~
CD
>
·C
Q
SN75492.SN75492A
N DUAL-IN-L1NE PACKAGE
description
The SN75491 and SN75491 A are quadruple
segment drivers. The SN75492 and SN75492A
are hex digit drivers. The SN75491 and
SN75492 are characterized for operation to
10 volts. The SN75491A and SN75492A are
characterized for operation to 20 volts.
~
"S.
II)
(TOP VIEWI
The SN75491, SN75491 A, SN75492, and
SN75492A are monolithic integrated circuits
designed to be used together with MOS
integrated circuits and common-cathode LED's
in serially addressed multi-digit displays. This
time-multiplexed system, which uses a segmentaddress-and-digit-scan method of LED drive,
minimizes the number of drivers required.
lA
6Y
6A
lY
2Y
2A
GND
3A
3Y
C
Vss
SA
5Y
4A
4Y
logic symbols t
SN75491.SN75491A
MOS/LED A
".
lA (11
~
The SN75491, SN75491A, SN75492, and
SN75492A are characterized for operation from
ooe to 70 oe.
2A (7)
3A (81
logic diagram (each driver)
SN75491.SN75491A
4A
1141
4E
SN75492.SN75492A
INPUT A - - c > t = :
lA (141
MOS/LED
~
2A (31
SN75492.SN75492A
INPUT A
~
3A (51
4A (81
5A (101
6A (121
OUTPUT Y
t These symbols are in accordance with ANSI/IEEE
Std 91-1984 and lEe Publication 617-12.
PRODUCTION DATA do.amants .ontaln information
currant 8S af publication data. Products conform to
specifications per the terms of Texas Instruments
::.~=~~·r::I~'1i ~:~:~ti:f :'lo=~1t::.s not
Copyright © 1986, Texas Instruments Incorporated
TEXAS ",
INSTRUMENTS
POST OFFICE BOX 865012 • DALL.AS, UXAS 15266
3-7
SN75491, SN75491A, SN75492, SN75492A
MOS-TO-LED DRIVERS
schematics
SN75491, SN75491A (each driver)
c
SN75492, SN75492A (each driver)
y
~_ _ _....... (1,
(1,7,8,14)
A - .....~IN\___-1......-I
o
2, 6, 7, 9,13)
(14,3,5,8,10,12)
A
VSS(;.;1..;.1)_....._ _......._ _~........_ _ _'-(4..;.) GND
-i.r____~~...____e-(~4) GND
VSS~(1..;.14)~.-__
iii'
'C
iii
<
o
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
~
<'!'
CD
~
III
SN75491
Input voltage range (see Notes 1 and 2)
Collector (output) voltage. Vc
Collector (output)-ta-input voltage
Emitter-to-ground voltage (VI '" 5 V)
10
20
5
5
10
20
Emitter-ta-input voltage
Voltage at VSS terminal with respect to any other device terminal
.1 Each collector (output)
Collector loutput) current, IC 1
All collectors (outputs)
Continuous total dissipation at (or below) 25°C
SN75492
SN75492A
UNIT
Storage temperature range
20
50
250
250
200
600
600
875
875
70
o to
V
V
10
50
o to
V
V
200
875
free-air temperature (see Note 3)
Operating free-air t,emperature range
o to
70
70
V
mA
875
o to
mW
DC
70
DC
-65 to 150 -65 to 150 -65 to 150 -65 to 150
Lead temperature 1,6 mm 11/16 inch)
260
from case for 10 seconds
NOTES:
SN75491A
-5VtoVSS -5 V to VSS - 5 V to VSS - 5 V to VSS
10
10
20
20
10
20
10
20
260
260
DC
260
1. All voltage values are with respect to network ground terminal.
2. The input is the only device terminal that may be negative with respect to ground.
3. For operation at 25°C free-air temperature, refer to Dissipation Derating Curves in Appendix A. For these devices in the N
package, use the 7-mW/oC curve.
'491, '491A electrical characteristics, VSS
10 V for SN75491, VSS - 20 V for SN75491A,
T A = OOC to 70 DC (unless otherwise noted)
PARAMETER
VCElon)
TEST CONDITIONS
On-State collector-emitter voltage
Input - 8.5 V through 1 kO,
IC = 50 mA, TA = 25 DC
VE - 5 V,
Input - 8.5 V through 1 kO,
VE - 5 V,
= 50 mA
Vc = VSS,
VE
II
Vc - VSS,
VE - 0,
VE - 0,
MIN Typt
MAX
0.9
1.2
V
1.5
IC
ICloft)
Off-state collector current
II
Input current at maximum input voltage
VI - VSS,
IC = 20 mA
IE
Emitter reverse current
VI
ISS
Current into VSS terminal
= 0,
VE
= 0,
=
40 pA
100
VI - 0.7 V
1 '491
1 '491A
5 V,
t All typical values are at T A = 25 DC.
3-8
=
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
IC
=
0
UNIT
100
2.2
4.7
3.3
6.5
pA
mA
100
pA
1
mA
SN75491. SN75491A. SN75492. SN75492A
MOS-TO-LED DRIVERS
'492, '492A electrical characteristics, VSS - 10 V for SN75492, VSS - 20 V for SN75492A,
TA = OOC to 70°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Input
VOL
IOH
Low-level output voltage
6.5 V through 1 klJ.
10L - 250 mAo
TA = 25°C
Input = 6.5 V through 1 kO,
10l - 250 mA,
VOH
High-level output current
=
=
VSS,
VOH - VSS,
II
Input current at maximum input voltage
ISS
Current into VSS terminal
VI
=
VSS,
VI
= 40
MIN Typt
MAX
0.9
1.2
=
200
p.A
20 mA
V
1.5
200
VI - 0.5 V
10l
UNIT
1'492
I '492A
2.2
3.3
4.7
6.5
1
~A
mA
mA
t All typical values are at TA = 25°C.
•
.
en
~
·C
C
SN75491, SN75491A switching characteristics, VSS - 7,5 V. TA - 25°C
PARAMETER
TEST CONDITIONS
tpLH Propagation delay time, low-to-high-Ievel output (collectorl
tpHl Propagation delay time, high-to-Iow-Ievel output (collector)
VIH = 4.5 V,
RL = 200 0,
VE
Cl
= 0,
= 1 5 pF
MIN
>
ca
TYP MAX
1-___10"'0;;-_---if-_--1
20
Q.
en
o
SN75492, SN75492A switching characteristics, VSS = 7.5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
=
tplH Propagation delay time, low-to-high-Ievel output
VIH
tpHl Propagation delay time, high-to-Iow-Ievel output
Cl = 15 pF
7.5 V,
Rl
=
MIN
TYP
MAX
300
30
390,
PARAMETER MEASUREMENT INFORMATION
SN75491, SN75491A
7.5V
P--4~I---
OUTPUT
INPUT
....,;1,;,0%
...._ _ _ _ 0 V
r---VOH
I
SN75492, SN75492A
OUTPUT
7.5V
I
I
I
I
:
tPHl--j....i
~~.....- - - OUTPUT
=
VOLTAGE WAVEFORMS
TEST CIRCUITS
NOTES: A. The pulse generator has the following characteristics: Zout = 50 0, PRR
B. Cl includes probe and jig capacitance.
s
100 kHz, tw = 1 ~s.
FIGURE 1. PROPAGATION DELAY TIMES
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
3-9
SN75491, SN75491A, SN75492, SN75492A
MOS·TO·LED DRIVERS
TYPICAL CHARACTERISITCS
SN75491,SN75491A
COLLECTOR CURRENT
vs
INPUT CURRENT
INPUT CURRENT
vs
INPUT VOLTAGE
5
Vss = 10 V ('491, '492)
Vss =20 V ('491A, '492A)
10 =20 mA
VE - 0 ('491, '491AI
TA 25°C
4
0
0'
"2I»
<
C
:::!.
.
<
CD
=
1
.!.c
E
....
I I
3
I
~ 1-'491, '492
u
a.
c
2
1
V
UI
/
o ./
o
2
-1/
50
/
V
«
V
...EcI
6
=
..
~ 30
u
/
S.
.!!
/
20
;3
I
!i
V
4
VSS = 10 V
VC=2.5V
_ VE=O
40
TA 25°C
8
10 12
14 16
10
o
18 20
o
/
40
FIGURE 3
FIGURE 2
SN75491,SN75491A
COLLECTOR CURRENT
vs
INPUT VOLTAGE
SN75491, SN75491A
ON·STATE COLLECTOR·EMITTER VOLTAGE
vs
COLLECTOR CURRENT
l'
50
VSS = 10V
f-VC = 2.5 V
1.0
t
~
40 I- VE =0
TA = 25°C
0.8
.~E
1
,...
-;; ..- ~ ,
~
~
/"
'Y
o
:3.,
0.4
i9
0.2 -VSS = 10V
i
8
l20
10
i
o
..I
o
0.5
1.0
1.5
2.0
2.5
iii
~
0.6
\
\- TA = 70°C
\.
TA = 25°C
\.. TA =O°C
I
VE=O
- Input = 3.5 V thru 1 kG
i J L 1 L
0
o 5 10 15 20 25 30
35
40 45 50
Ic-Collector Current-mA
VI-Input Voltage-V
FIGURE 5
FIGURE 4
3-10
....
1\ 1\
~ 30
~u
200
II-Input Current-pA
VI-Input Voltage-V
-
160
120
80
/
TEXAS ."
INSTRUMENTS
pos; OFFICE BOX 8&5012 • OAUAS, TEXAS 76285
SN75491. SN75491A. SN75492. SN75492A
MaS-TO-LED DRIVERS
TYPICAL CHARACTERISTICS
SN75492,SN75492A
OUTPUT CURRENT
SN75492, SN75492A
OUTPUT CURRENT
vs
vs
INPUT CURRENT
INPUT VOLTAGE
250
200
E
I
'150
j
:;
u
i
/
/
«
J
I
r- Va = 2.5 V
200 r- TA = 25°C
E
.Lc:
~
...
e-
100
II)
>
-;:
C
U
:J
:J
/
/
o
50
100
150
o
200
250
300
Q.
III
I
50
.J
(II
I
2
o
>
1
0
I
50
II
..
III
150
:;
/
100
:J
o
I
2
VISS =1 10
I
«
~
250
I
VSS = 10 V
Va =2.5 V
TA = 25°C
is
l/
o
0.5
11-1 nput Current-IlA
1.0
1.5
2.0
2.5
VI-Input Voltage-V
FIGURE 6
FIGURE 7
SN75492, SN75492A
LOW·LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1.0
>I
2J, 0.8
19
0
>
...
:J
c.
0.6
~~
-\
,/
;
.
Qi
>
\
1\
0
..J
...- ~ r:== I-- ~
~ K I-~
-
-
i--
1'- TA = 70 0 e
"-
TA = 25°e
TA = O°C
0.4
;i:
0
..J
I
..J
0.2
0
VSS = 10 V
Input = 6.5 V thru 1 kU
>
o
o
I
I
I
50
I
100
I
150
200
250
la-Output Current-rnA
FIGURE 8
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-11
SN75491, SN75491A, SN75492, SN75492A
MOS;TO-LED DRIVERS
TYPICAL APPLICATION DATA
Figure 9 is an example of time multiplexing the individual digits in a display to minimize circuitry. Up to
twelve digits, each of which use a seven-segment display with decimal point, may be displayed using only
two SN75491 and two SN75492 drivers.
+v
RL
Vss --~--~''-r--------------r----------t-----,
C
l
A
2of8
DRIVERS
SHOWN
,
I
,SN75491
, QUAO SEGMENT
DRIVER
, 12 PACKAGESI
,
I
L __ _____
THIS POINT
$:!D
Ii c Ii E F G
DP -- -- -- r-.-+-r-r-f-ll-+-+-----,.
~
IS CONNECTED
ro~
SEGMENTS OF
ALL DIGITS.
E_J
E
-- -- -- -
-,
I TIL360
,~~
I MLEoDNODLISP'TLAHICy
,
, 12 PACKAGESI
____ ...J
, SN75492
, HEX DIGIT
,
I
IL _____
~
_________________ J I
FIGURE 9. INTERFACING BETWEEN MOS CALCULATOR CIRCUIT
AND LED MULTI-DIGIT DISPLAY
3-12
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS. TEXAS 75266
~:~:~;AGESI
SN75491. SN75491A. SN75492. SN75492A
MOS·TO·LED DRIVERS
TYPICAL APPLICATION DATA
SN75491, SN75491A,
SN75492, OR SN75492A
...,
r------I
I
I
I
I
:
I
I
r-- ~
IL _____ IL ___ JI
-I
___ _
I
INPUTI
I
""'--___--l
I
I
IL
r-------- -,
I
INPUTI
~I~..-!
SN75491, SN75491A
SN75492, OR SN75492A
I ___ .JI
.L
FIGURE 10. QUAD OR HEX RELAY DRIVER
+V1
,
... I
~--INPUT
FROM-+...,..,........-i
MOS
I
I
I
I
I
I
I
IL ___ _
J
I
IL ___
OUTPUT
TO
TTL
FIGURE 12. MOS·TO·TTL LEVEL SHIFTER
-,
..r-----~
,-------,
I
I
I
I
I
I
IL ____
I
'491, '491 A
I
I
I
-,
+V2
LOAD
I
I
I
I
IL _______ ..JI
LOAD
I
INPUT...:1'-'w_--i
II)
C
+V1
SN75941
INPUT
,--------
>
ca
Q.
_
+V1
I
>
·C
Q
FIGURE 13. QUAD HIGH-CURRENT N-P-N
TRANSISTOR DRIVER
r----.
SN75491, SN75491A
SN76492, OR SN75492A
LOAD
I
INPUT-+...,..,........--i
I
+V2
r-------·
I
I
~
FIGURE 11. QUAD OR HEX LAMP DRIVER
SN75491, SN75491 A
•
CD
'492, '492A
'492, '492A
V2
SN75942
r-------,
....JI ____ JI
INPUT I
'492, '492A
I
I
NOTE A: This circuit may be used as a digit driver for commonmode LED displays.
FIGURE 14. QUAD OR HEX HIGH-CURRENT
P-N-P TRANSISTOR DRIVER
I
I
I
IL _ _ _ _ _ _ .JI
FIGURE 15. BASE/EMITTER SELECT N-P-N
TRANSISTOR DRIVER
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
3-13
S175491, SN75491A, SN75492, SN75.492A
MOS·TO·LED DRIVERS .
TYPICAL APPLICATION DATA
+v
LOAD
LAMP OR RELAY
r-----SN75491 OR SN75491A
INPUT,--1'f-1....",...-1
......_-:-I:.:;:INPUT 2
I
I
_ _ _ _ _ ...1I
I
I
IL
_____ _
SN75491, SN75491A,
SN75492 OR SN75492A
r------- 1
nR~E
I
I
INPUT
I
I
I
I
'491, '491A
I
I
I
I
I
I
r---1
L___
_ __ .J
'492, '492A
FIGURE 16, STROBED "NOR" DRIVER
5V~~----------------~----~~----~-------,
r-----1/4 SN75491 OR SN76491A
2.7kn
2.7kn
I
........- r -..... OUTPUT
RL =60n
NONII:~~~TING--+----1-/4-S-N7-64-9-1O-R-S-N-75-49-1-A-+------+--1/-4-SN-7-54-91-0-R-S-N7-54-9-1A--...,
r------
----·---1
IN~::~~NG --t-+I"""".....-i
r-----
1 kn
IN
1/4 SN75491 OR SN75491A
I
I
5kn
IL _____ _
~V~._--~----------------~
FIGURE 17, SN75491/SN75491A USED AS AN INTERFACE CIRCUIT BETWEEN THE
BALANCED 30·MHz OUTPUT OF AN RF AMPLIFIER AND A COAXIAL CABLE
3-14
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75265
SN75494
HEX MOS-TO-LED DIGIT DRIVERS
01932. MARCH 1983-REVISEO JANUARY 1987
•
Low Input Current for MOS Compatibility
•
Low Voltage Operation
•
N
DUAL-IN-LINE PACKAGE
CTOPVlEW)
Vss
Low Standby Power
•
Display Blanking Capability
•
250-mA Sink Capability
•
Low-Voltage Saturating Outputs
•
High-Gain Circuits
Vee
1A
1Y
2Y
2A
3Y
3A
6A
6Y
5Y
5A
4Y
4A
Voo
E
description
The SN75494 is designed to be used as an interface between MOS integrated circuits and LEOs in serially
addressed multidigit displays. This device is similar in operation to the SN75492, but has several advantages
over the earlier circuit. The SN75494 can be operated at lower supply voltages therefore, reducing power
consumption. The enable (E) input is used as a blanking input.
logic symbol t
schematic
'r---
1 OF 6 DRIVERS
lA (2)
1V
2A (5)
2V
3A C7l
4A (10)
3V
5A (12)
6A (15)
5V
4k
A
o-.-II--.---..--l
I
I
I
4V
6V
VSS
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
-_--+
y
I
I
L
logic diagram (positive logic)
VaD
NOTES: A. The VSS terminal must be connected to the most
positive voltage that is applied to the device.
B. Resistor values shown are nominal and in ohms.
PRODUCT/D. DATA documents contein informetio.
.urrant as of publication date. Prod••ts .onfarm to
spaciflcations par tho terms of T.... Instrum••te
:'':~~~,~~
==:i:r IIlo::~~A:~ not
Copyright © 1983. Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 666012 • OALLAS. TEXAS 76266
3-15
SN75494
HEX MOS-TO-LED DIGIT DRIVERS
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, VCC (see Note 1) .............................................. 10 V
Supply voltage, VSS (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10 V
Input voltage ............................................................. VSS
Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10 V
Continuous output current (each driver) ....................................... 250 rnA
Continuous VOO current .......... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 600 rnA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 3) . . . . . . .. 800 mW
Operating free-air temperature range ...................................... ooC to 70°C
Storage temperature range ......................................... - 65°C to 1 50°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 260°C
C
iii"
recommended operating conditions
"C
iii
MIN
MAX
-<
Supply voltage, Vee
3.2
8.8
C
...
Supply voltage, VSS
6.5
8.8
V
:e"
Operating free-air temperature, T A
0
70
°e
CI
;
electrical characteristics,
Input
0
TEST CONOITIONS
.1 A input
current
J
i:" input
Off-state output
IO(off)
current (from
V to VOO)
VO(on)
A at 8.8 V,
Eat 8.8 V
Vee = 3.2 V,
A at 8.8 V,
i:" at 8.8 V
Vee - 3.2 V,
A to 8.8 V thru 100 kll,
MIN
i:" to
i:"
8.8 V thru 100 kll
at 0 V,
Vat 10 V
i:" to
A at 8.8 V,
6.5 V thru 1 kll,
Vat 10 V
On-state
Vee = 3.2 V,
output voltage
i:" to
VSS - 6.5 V, A to 6.5 V thru 1 kll,
8.8 V thru 100 kll,
All other A inputs at 0 V
Current into
One A input at 8.8 V,
Vee terminal
All other A inputs at 0 V
E to 6.5 V thru 1 kll,
One A input at 8.8 V,
Eat 0 V,
All other A inputs at 0 V
ISS
t All typical
NOTES: 1.
2.
3.
3-16
eurrent into VSS
terminal
Vee = 3.2 V,
i:" at
Typt
MAX
2
0 V,
All A inputs at 0 V
UNIT
1.8
3
2.5
1.6
2.5
1
200
1
100
0.25
0.4
10
500
60
500
11
20
mA
10
500
p.A
mA
/LA
IOL = 250 mA
One A input to 8.8 V thru 100 kll, Eat 0 V,
Ice
V
Vee = B.B V, VSS = B_B V, TA = ooe to 70 e (unless otherwise noted)
PARAMETER
II
UNIT
V
p.A
values are at T A =; 25°e.
Voltage values are with respect to the most negative device terminal, VOO, unless otherwise noted.
No other terminal on the device may be more positivB than VSS.
For operation above 25°C free-air temperature, derate linearly from 800 mW at 63°C to 736 mW at 70 0 e at the rate of
9.2 mW/oe.
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
ADVANCE
INFORMATION
SN55500E
AC PLASMA DISPLAY DRIVER
1986
02471 DECEMBER 1984-REVISEo
•
•
•
•
•
•
•
•
•
Controls 32 Electrodes
JD PACKAGE
(TOP VIEWI
100-V Totem-Pole Outputs
SO
DATA
ClK
101
102
103
104
105
106
107
108
201
202
203
204
205
206
207
208
GND
Low Stand-by Power Consumption
All Outputs Contain Sink and Source Clamp
Diodes
15 rnA Steady-State Output Current
Rugged DMOS Outputs
CMOS Inputs
Dependable Texas Instruments Quality and
Reliability
Direct Replacement for SN55500D
description
The SN55500E is a monolithic BIDFETt
integrated circuit designed to perform the line
select operation of a matrix-addressable display.
The device inputs are diode-clamped CMOS
inputs.
The outputs of the driver are normally low and
can be selectively switched high when the strobe
input is low. Selection of the outputs is achieved
through the data, SO, and S1 inputs. The 8-bit
data stored internally in the serial register is
inverted and sent to one of four output sections
by the 2-line to 4-line decoder. All other outputs
remain low. Internal circuits provide a highcurrent pulse to the level-shifting circuit during
positive output transitions. When the output
transition is complete, the low steady-state
current reduces the circuits stand-by power
consumption. All outputs contain clamp diodes
to the VCC2 and GND supply inputs.
The SN55500E is characterized for operation
over the full military temperature range of
-55°C to 125°C.
VCC1
S1
STRB
401
402
403
404
405
406
407
408
301
302
303
304
305
306
307
308
VCC2
•
~
II)
>
'C
Q
>
ca
Q.
/I)
is
FD PACKAGE
(TOP VIEW)
«
~
III
ou~~ou tLl=uo
~ZuOUlZ>UlUlZ~
6 5 4 3 2 1 44 43 42 41 40
39
38
37
9
201
10
11
12
13
14
15
16
17
36
35
34
33
32
31
30
29
1819202122232425262728
z
o
i=
_------~~~
CMOS/PLASMA DISP
r
SELECT
II
(41 101
c
Z3
'0
Z4
<
Z5
Cij"
iii
...C
<"
CD
Z6
Z7
UI
Z8
108
2-LlNE TO
4-LlNE
DECODER
201
Sl
(111 108
1121 201
I>
101
208
DATA
301
8.12
1.13
(191 208
1291 301
I>
I>
1.14
I>
I>
1221 308
(371 401
8.14
I>
1301 408
8.13
Rl
R2
R3
R4
8-BIT
SHIFT
R5
REGISTER R6
ClK
308
401
R7
R8
408
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the JD package.
FUNCTION TABLE
INPUTS
FUNCTION
LOAD
»
c
~
2
(")
m
-
STROBE
OUTPUTS
SELECT
S1 SO
SHIFT REGISTER
DATA
ClK
R1
R2
R3 ... R8
H
X
X
H
l
R1n
R2n ... R7 n
L
t
t
X
X
X
X
X
H
H
H
X
R1n
R1n
R2n
X
H
X
X
H
H
L
L
H
L
H
L
L
R1n
R1n
R1n
R2n
R2n
R2n
X
H
H
H
L
R1n
R2n
R2n
R3 n
R3 n
R3n
R3 n
R3n
STRB
L
L
101 ... 108 201 ... 208 301 ... 308 401 ... 408
l ... L
L ... L
L ... L
L ... L
.. · R7n
... R8 n
... R8 n
... R8 n
.. · R8 n
... R8 n
L ... L
L ... L
L ... L
L ... L
Rl ... R8
L ... L
L ... L
L ... L
Rl ... R8
L ... L
L ... L
L ... L
L
L
L
L
Rl
typical operating sequence
2
."
o
:s:
~
o
ClK
ANY QUTPUT IN
8 SELECTED BY
SO AND Sl
RVALID
RVAL'O
--L-.....I~----------~i~!-L_.....I~
2
3-18
TEXAS . "
INSTRUMENTS
POST ol=i!ICS BOX 656012 • DALLAS. tEXAS 16266
L
L
L
L
R8
L ... L
H = .high level. L = low level. X = irrelevant. t = low-to-high transition.
Rl ... R8 = levels currently at internal outputs of shift registers one through eight, respectively.
Rl n ... R8 n = levels at outputs Rl through R8 respectively, before the most recent t transition' of the clock.
::D
...
...
...
...
...
__
L ...
L ...
L ...
L ...
L
L
L
L
L ... L
Rl ... R8
ADVANCE
INFORMATION
SN55500E
AC PLASMA DISPLAY DRIVER
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
VCC1--------~----~_e---
•
INPUT - -....JV\,.,..........
I!!
CD
>
";:
C
GND--e-----------. .~~
>-
ca
Q.
en
Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8 V
Supply voltage, V CC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCCl +0.3 V
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2) . . . . . .. 1825 mW
Operating free-air temperature range ......... . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 1 50°C
Case temperature for 60 seconds: FD package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JD package ........... 300°C
NOTES:
1. Voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, see Dissipation Derating Table.
DISSIPATION DERATING TABLE
PACKAGE
POWER
DERATING
ABOVE
RATING
TA
25°C
67°C
FD
1825 mW
FACTOR
14.6 mW/oC
JD
1825 mW
22 mW/oC
z
o
-l!e:(
~
a:
o
LL
Z
W
(.)
Z
e:(
>
C
e:(
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-19
ADVANCE
INFORMATION
SN55500E
AC PLASMA DISPLAY DRIVER
recommended operating conditions
MIN
10.8
Supply voltage, VCCl
Supply voltage, VCC2
High·level input voltage, VIH, as a percentage of VCCl
Low-level input voltage, VIL, as a percentage of VCCl
High-level output clamp current
Low-level output clamp current
Clock frequency, f clock (see Figure 2)
Duration of high or low clock pulse, tw
Data inputs before clockt
Setup time, tau
Select inputs before strobe~
Data inputs after clockt (see Note 31
Strobe input high after clockt
Hold time, th
Select inputs after strobet
Operating free-air temperature, TA
Operating case temperature, T C
NOM
12
0
76%
MAX
13.2
100
25%
20
-20
0
62
20
50
50
60
60
-56
8
UNIT
V
V
mA
mA
MHz
ns
ns
ns
125
·C
·C
NOTE 3: For operation above 26·C junction temperature, refer to Figure 2.
electrical characteristics over recommended operating temperature range (unless otherwise noted)
~
C
<
~
2
VIK
PARAMETER
Input clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
VOK
Output clamp voltage
IIH
IlL
ICCl
ICC2
High-level input current
Low-level input current
Supply current
Supply current
TEST CONDITIONS
II = -12mA
VCCl = 12 V,
10H = -1 mA
VCCl = 13.2 V,
10H = -10mA
VCC2 = 100 V
10H = -15 mA
10L=lmA
VCCl
13.2 V,
10L
10mA
VCC2 = 100 V
10L = 15mA
10 = 20mA
VCC2 = 0
10--20mA
13.2 V,
VI
VIH min
VCCl
VI = VIL max
VCCl = 13.2 V,
=
=
VCCl = 13.2 V,
VCC2
MIN
94
92
90
=
TYpt
-1
97.5
94.6
93.5
0.85
2
2.75
1
-1.2
=
0.06
1
VCC2 = 100 V
= 100 V
MAX
-1.5
UNIT
V
V
2
4
5
2.6
-2.5
1
-1
1
5
V
V
P~A
mA
mA
tAli typical values are at Vcc = 12 V, TA = 25·C.
switching characteristics. VCC1 - 12 V. VCC2 - 100 V. TA - 25°C
(")
m
tDHL
tDLH
2
tTHL
trLH
."
o:;g
PARAMETER
Delay time, high-to-Iow-Ievel output from strobe input
Delay time, low-to-high-Ievel output from strobe input
Transition time, high-to-Iow-Ievel output
Transition time. low-to-high-Ievel output
TEST CONDITIONS
CL = 30 pF,
See Figure 1
3:
~
-t
o2
3-20
TEXAS'"
INSIRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MIN
MAX
250
450
200
300
UNIT
ns
ns
ns
ns
ADVANCE
INFORMATION
SN55500E
AC PLASMA DISPLAY DRIVER
PARAMETER MEASUREMENT INFORMATION
OUTPUT
TEST
UNDER - - - - r - - - - - - P O I N T
TEST
J
Cl (8ee Note A)
lOAD TEST CIRCUIT
ClK
\-------~,.
'+--
!+-
. 1--------- ------ ----- Vil
~I
lw
I
i--------- --------~~~%
tau
.
: VALID
.
~
~
·C
Q
--+I+-- III ---.:
DATA --I-RR-E-LE-V-A-NT----)<
•
>
ca
X"'--I-RR-E-lEV-A-NT--- VIH
j.-th~
' - - - - - - - - - Vil
Q.
II)
is
STRB
SELECT
OUT
VOLTAGE WAVEFORMS
NOTE A. Cl includes probe and jig capacitance.
FIGURE 1. SWITCHING CHARACTERISTICS
z
i=
'':
C
>
ca
c..
I/)
is
GND -...._ _~ VCC2
FN PACKAGE
(TOP VIEWI
U m
aU:J~ou
U~~Ud
~ZuoU)z>U)U)z~
w
NOO,....COIO
OOOOzz UOOOO
NNNNC)
UM M M M
a:
>
0..
NC _. No internal connection
I-
CJ
::>
o
oa:
0..
PRODUCT PREVIEW documanls conlain informalion
on products in the formative or design ~has. of
development. Characteristic data Bnil ather
~=;!i::t:=:1ri~:t dt-:.sir8=::I~r TdTs::~~:~:~:=
products wilhoul nollca.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Copyright © 1985, Texas Instruments Incorporated
3-23
PRODUCT
PREVIEW
SN65500E, SN75500E
AC PLASMA DISPLAY DRIVERS
logic symbol t
functional block diagram (positive logic)
CMOS/PLASMA OISP
STRB-------
130) 4Q8
208
301
ClK
Z5
t>
t>
201
DATA
119) 208
(29) 301
8.13
1.14
108'
2-LlNE TO
4-u'NE
DECODER
. S1
(11)10B
112) 201
Z6
101
R1
R2
R3
R4
8-BIT
SHIFT R5
REGISTER R6
308
401
408
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the N package.
FUNCTION TABLE
INPUTS
FUNCTION
."
::a
OUTPUTS
SELECT
Sl SO
DATA
elK
lOAD
H
L
X
X
X
X
X
X
STROBE
X
X
X
X
X
t
t
X
H
H
L
L
L
H
H
H
H
H
L
H
STRB
H
H
H
L
L
L
L
SHIFT REGISTER
R2
R3 ... R8 1Q1 ... 1Q8 2Q1 ... 2Q8 3Q1 ... 3Q8 4Q1 ... 408
R1
L _._ L
L __ . L
L __ . L
R2n __ . R7 n
L ._. L
L
R1n
L _._ L
L . __ L
L .. _ L
L ... L
H
R2n ... R7 n
R1n
L _._ L
L ___ L
L . __ L
R3 n ___ R8 n
L . __ L
R1n
R2n
L ___ L
L ___ L
L _.. L
R1 ... R8
R2n
R3 n .-. R8 n
R1n
L ___ L
L __ . L
R1 __ . R8
R3 n ... R8 n
L ... L
R1n
R2n
L _._ L
R1 ___ RB
L _.. L
L _.. L
R3 n ._- R8 n
R1n
R2n
R3 n ___ R8 n
R1 . __ R8
L .. _L
L ._. L
L ._. L
R1n
R2n
H = high level. L = low level. X = irrelevant. t = low-to-high transition_
R1 ___ RB = levels currently at internal outputs of shift registers one through eight. respectively_
R1 n . __ R8 n = levels at shift-register outputs R1 through R8. respectively. before the most recent t transition of the clock_
o
C
c:
n
-I
."
::a
~
~
3-24
TEXAS . "
INSTRUMENTS
POST OFFICE
sox 8&6012
• DALLAS, TEXAS 7628&
SN65500E, SN75500E
PRODUCT
PREVIEW
AC PLASMA DISPLAY DRIVERS
typical operating sequence
ClK
ANY OUTPUT IN
B SELECTED BY
SO AND S1
RVALID
RVA!.ID
.......--.L..--
--.L--.L..-----------~HI-
schematics of inputs and outputs
~
CD
EQUIVALENT OF EACH INPUT
TYPICAL OF All OUTPUTS
>
";:
Q
VCC1--------~--~~_e~
>
ca
Q.
III
Q
INPUT ......._.lW.............
GND ............----------~~--
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 V
Supply voltage, VCC2 ...................................................... 100 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. VCC1 +0.3 V
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
FN package ....................................................... 1775 mW
N package ........................................................ 1275 mW
Operating free-air temperature range: SN65500E. . . . . . . . . . . . . . . . . . . . . . . . .. - 40°C to 85 °C
SN75500E ............................ OOC to 70°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ............ 260°C
Case temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
NOTES: 1. Voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, see Dissipation Derating Table.
DISSIPATION DERATING T/'BlE
PACKAGE
FN
N
POWER
DERATING
RATING
FACTOR
ABOVE
TA
1775
1275
14.2
10.2
25°C
25°C
~
w
:>w
a::
D.
I-
o
:::>
c
oa::
D.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-25
SN65500E, SN75500E
PRODUCT
PREVIEW
AC PLASMA DISPLAY DRIVERS
recommended operating conditions
SN75500E
SN65500E
NOM
MAX
MIN
NOM
MAX
Supply voltage, VCCl
10.8
12
13.2
10.8
12
Supply voltage, VCC2
High-level input voltage, VIH. as a percentage of VCCl
Low-level input voltage, VIL, as a percentage of Vee1
High-level output clamp current
low-level output clamp current
0
75%
100
0
75%
13.2
100
V
V
25%
20
-20
mA
25%
20
-20
Clock frequency, fclock (see Figure 21
Duration of high or low clock pulse, tw
C
iii"
Setup time, tsu
~
Hold time, th
'C
.
C
0
62
Data inputs before clockt
Select inputs before strobe!
Data inputs after clockt (see Note 31
Strobe input high after clockt
Select inputs after strobet
Operating free-air temperature, T A
~"
UNIT
MIN
8
20
0
62
20
50
50
50
50
50
50
50
-40
50
0
85
8
mA
MHz
ns
ns
ns
70
·C
NOTE 3: For operation above 25·C junction temperature, refer to Figure 2.
ill
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VIK
TEST CONDITIONS
Input clamp voltage
VCCl - 12 V,
VOH High-level output voltage
VOL
low-level output voltage
VCCl = 13.2 V,
VCC2 = 100 V
VCCl = 13.2 V,
VCC2 = 100 V
VOK Output clamp voltage
IIH
III
High-level input current
Low-level input current
ICCl Supply current
ICC2 Supply current
."
::I:J
o
MIN
12 mA
1110H - -1 mA
10H = -10 mA
15 mA
10H -
-1
94
92
97.5
94.5
90
93.5
0.85
10l - 1 mA
10l = 10 mA
2
2.75
10l - 15 mA
10-20mA
20mA
10 -
VCC2 = 0
VCCl = 13.2 V.
VCCl - 13.2 V,
VCCl - 13.2 V.
VCC2 - 100 V
SN65500E
Typt
MAX
1
1.2
VI = VIH min
VI - Vil max
VCC2 - 100 V
SN75500E
Typt
MAX
MIN
-1.5
95
93
91
2
4
5
2.5
2.5
1
-1
-1
97.5
94.5
93.5
0.85
2
2.75
1
1.2
-1.5
UNIT
V
V
2
4
5
2.5
2.5
V
V
1
-1
~A
mA
mA
0.05
1
0.05
1
1
5
1
3
~A
tAli typical values are at VCCl = 12 V, TA = 25·C .
switching characteristics. VCC1 = 12 V. VCC2 -
C
c:
(")
-I
."
::I:J
PARAMETER
tDHl
tDlH
tTHl
tTlH
100 V. TA - 25°C
TEST CONDITIONS
Delay time, high-to-Iow-Ievel output from strobe input
Delay time. low-to-high-Ievel output from strobe input
Cl =' 30 pF.
Transition time. high-to-Iow-Ievel output
See Figure 1
Transition time. low-to-high-Ievel output
MAX
UNIT
250
450
200
ns
300
m
S
m
:e
3-26
MIN
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
ns
ns
ns
SN65500E, SN75500E
PRODUCT
PREVIEW
AC PLASMA DISPLAY DRIVERS
PARAMETER MEASUREMENT INFORMATION
OUTPUT
TEST
UNDER - - - - r . . - - - - - P O I N T
TEST
T
CL (see Note AI
'='
LOAD TEST CIRCUIT
CLK
\---------f1----------- -------------~~~%
------ ----I.
~
1
VIL
tw
i+-
X
tsu
~I
--+I+-
:
DATA --IR-RE-LE-V-A-N-T-......
--+:
th
VALID
I--th
C.
II)
I,----VIH
Q
x=
~ th +I
14-- tsu +1
----------""'\X
.
.
:
-.j tDlH I+-
~
lTLH-to/
~
-
-
~
~--90%
VIL
VIH
VIL
tDHL
9%0%:t.
VALID
10
~______
OUT
>
ca
~------- VIL
1\..._ _ _ _----J I _
SELECT
II)
Q
'\
STRB
..!:
·c
xr--I-RR-E-LEV-A-NT--- VIH
--l
•
-.j
VOH
10% VOL
i4-lTHL
VOLTAGE WAVEFORMS
NOTE A. CL includes probe and jig capacitance.
FIGURE 1. SWITCHING CHARACTERISTICS
;:
w
:>w
a:
a.
I-
o
o
o
::l
a:
a.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 7"5265
3-27
SN65500E, SN75500E
PRODUCT
PREVIEW
AC PLASMA DISPLAY DRIVERS
TYPICAL CHARACTERISTICS
MAXIMUM CLOCK FREQUENCY
vs
VIRTUAL JUNCTION TEMPERATURE
9
•
N
::E:
:i
I
>u
..c
&
C
~
'0
'"u
ir
ii'
<
8
7
--......
I---
VCC1 - 12 V
VIH - 12 V
VIL - 0
(See Note 4)
- --.......
.......
6
fj
C
E
::I
E
5
:i
4
..
::I.
---
"iii
<
...
CD
U>
3
25
65
45
85
105
125
TJ-Junction Temperature-·C
NOTE 4: This curve assumes a symmetrical clock pulse ..
FIGURE 2
THERMAL. INFORMATION
junction temperature formula
TJ = TA
+
TJ = TC
+ PORliJC
PORliJA
where
."
::0
o
T J = virtual junction temperature
T A = free-air temperature
Po = average device power dissipation
R9 = thermal resistance (junction-to-air, R9JA, or junction-to-case, R9JC)
C
c:
C)
-I
."
PACKAGE TYPE
FN 44-pin plastic
RIIJA
70 ·C/w
RSJC
22 ·C/W
N 40-pin plastic
97 ·C/W
27 ·C/w
::0
S
m
:e
3-28
TEXAS
~
INSTRUMENTS
POST OFFICE SOX 855012 • DAllAS, TEXAS 75265
SN55501E
AC PLASMA DISPLAY DRIVER
02472. APRIL 1986
•
JD PACKAGE
ITOPVIEWI
Controls 32 Electrodes
•
100-V Totem-Pole Outputs
•
Low Stand-by Power Consumption
•
All Outputs Contain Sink and Source Clamp
Diodes
•
15 mA Steady-Stata Output Current
•
Rugged DMOS Outputs
•
CMOS Inputs
•
Direct Replacement for SN55501C.
SN55501D
VCCl
SUSTAIN
STROBE
Ql
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Ql0
Qll
Q12
Q13
Q14
Q15
Q16
description
The SN55501 E is a monolithic BIDFETt
integrated circuit designed to provide the serialto-parallel conversion and level translation of
data in a matrix-addressable display. This device
has diode-clamped CMOS inputs.
The Q outputs of these drivers are normally high
and can be switched either selectively or
together. Any output whose associated register
bit (in the internal 32-bit serial register) contains
a low will switch low when the strobe input is
switched low if the sustain input is high. All other
outputs remain high. When the sustain input is
switched low. all outputs switch low
independently of the data or strobe inputs. This
feature can be used to generate a portion of the
sustain pulse required in the operation of an AC
plasma display. The internal level-shift circuits
provide additional drive during the times that the
outputs switch high to facilitate fast rise times
while maintaining low standby power
consumption. All outputs contain clamp diodes
to the VCC2 and GND supply inputs.
The SN55501 E is characterized for operation
over the full military temperature range of
-55°C to 125°C.
t BIDFET -Bipolar. double-diffused. N-channel and P-channel
MOS transistors on same chip - patented process.
DATA IN
SERIAL OUT
Q32
Q31
Q30
Q29
Q28
Q27
Q26
Q25
Q24
Q23
Q22
Q21
Q20
Q19
Q18
Q17
VCC2
GND
•
..
III
CD
>
·C
Q
>
ca
Q.
III
is
FD PACKAGE
ITOPVIEWI
I:J
zO
w~
- ...J
mOcnzd
'"
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Ql0
Qll
Q12
6 5 4 3 2 1 4443424140
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
34
15
31
16
30
17
29
1819202122 2324 2526 27 28
MV"''''OU "' .... 000>0
ooooi5 z
tlOOOCJ
>
NC-No internal connection
PROOUCTIOI DATA d.c.lli.....ntain i.farllllio.
currant •• of publication d.... Pre..... conlorm to
_li.lli••• por th. torlll 0' TUII I.otru......
:=~il;"r:~~l.i =:~I:: l.l,,:::.:lt::" not
Copyright @ 1986, Texas Instruments Incorporated
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-29
SN55501E
AC PLASMA DISPLAY DRIVER
logic symbol t
functional block diagram (positive log.ic)
SUSTAIN
STROBE
CLOCK
•
DATA IN (39)
0'
02
(4) 01
IS) 02
2
2
[> 3
[> 3
2
2
[> 3
[> 3
(19) 016
(22) 017
...;e'
2
2
[> 3
[> 3
(36) 031
(37) 032
(38) SERIAL OUT
en
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
C
iii'
'C
iii
<
C
..
0'
DATA IN
CLOCK (1)
·
02
03
03
32-81T
STATIC
SHIFT
REGISTER
··
030
030
03'
CD
IEC Publication 617-12.
Pin numbers shown are for the JD package.
03'
032
032
' - - - - - j > - - SERIAL OUT
FUNCTION TABLE
OUTPUTS
INPUTS
FUNCTION
LOAD
STROBE
SUSTAIN
SERIAL
Rl
R2
R3 ... R32
DATA
01
02
03 .... 032
H
H
R1n
R2 n ···R31 n
R32 n
H
H
H. ... H
H
H
L
R1n
R2 n ···R31 n
R32 n
H
H
H. ... H
H
H
R1n
R2n
R3n ···R32n
R32 n
H
H
H .... H
H
L
H
R1n
R2n
R3 n···R32n
R32 n
R1
R2
R3 .... R32
X
X
L
R1n
R2n
R3 n···R32n
R32 n
L
L
L .... L
DATA
CLOCK
STROBE
SUSTAIN
H
t
H
L
i
X
X
X
X
SHIFT REGISTER
H = high level, L = low level, X = irrelevant, i = low-to-high-Ievel transition.
R1 ... R32 ::::: levels currently at internal outputs of shift registers one through thirty-two, respectively.
R1 n ... R32n ::::: levels at Shift-register outputs R1 through R32 respectively, before the most recent t transition at the Clock input.
3-30
TEXAS~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN55501E
AC PLASMA DISPLAY DRIVER
typical operating sequence
SUSTAIN
I~
STROBEU
ANY Q OUTPUT
ILf1J1J
UI
L .'RRELE---,VANT
-.-
CLOCK
r:
---'E]-VA-L-'O'--"",
B
IeCD
>
";::
schematics of inputs and outputs
Q
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL Q OUTPUTS
Vcc1--------~-----.-.~
•
TYPICAL SERIAL OUTPUT
------~~----~...~I--VCC2
>
co
is.
!II
C
OUTPUT
INPUT - -...JV<>IIt-_.....
- - - - - -__-4~~----~-GND
GND~---------.--~-4~
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage. VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 V
Supply voltage. VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC1 +0.3 V
Continuous total dissipation at (or below) 25°C free-air (see Note 2) . . . . . . . . . . . . . . .. 1825 mW
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
Storage temperature range ......................................... - 65°C to 150°C
Case temperature for 60 seconds: FD package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
Lead temperature 1.6 mm (1/16 inch) from case for 60 seconds: JD package ........... 300°C
NOTES:
1. All voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, see Dissipation Derating Table.
DISSIPATION DERATING TABLE
PACKAGE
FD
JD
POWER
DERATING
ABOVE
RATING
FACTOR
14.6 mw/oe
TA
25°C
67°C
1825 mW
1825 mW
22 mw/oe
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-31
SN55501E
AC PLASMA DISPLAY DRIVER
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VCC1
10.8
1~
13.2
V
Supply voltage, VCC2
0
100
V
High-level input voltage, VIH
0.75 Vee1
Low-level input voltage, VIL
0.25 VCe1
-20
Peak high-level Q output current, 10H
Peak low-level Q output current, IOL
High-level Q output clamp current, 10KH
Low-level Q output clamp current, IOKL
0
Clock frequency, fclock. at or below, 25°C junction temperature (see Note 3)
C
...
<'
...
fI)
mA
8
MHz
ns
Strobe high after clockt
150
ns
Strobe high after sustaint
250
Hold time, th
Data hold time after clockt
- 55
Operating free-air temperature, T A
'c
125
Operating case temperature, T C
CD
mA
ns
Data inputs before clockt
C
20
-20
20
50
Setup time, tsu
Qj
<
mA
62
Duration of high or low clock pulse, tw
iii'
't:I
mA
20
NOTE 3: See Figure 3 for maximum clock frequency when devices are operated in cascade or for operation above T J
25°e.
electrical characteristics over recommended operating temperature range
PARAMETER
VIK
High-level
VOH
TEST CONDITIONS
Input clamp voltage
Q outputs
output voltage
Serial out
Low-level
VOL
output voltage
Output clamp
VOK
Q outputs
voltage
~
12 V,
VCC1
~
13.2 V,
VCC2
~
100 V
VCC1
~
10.8 V,
VCC1
~
13.2 V,
VCC2
~
100 V
~
10.8 V,
Seria'i out
VCC1
Q output
VCC2 ~ 0
High-level
VCC1
input current
VCC2
Low-level
input current
VCC1 - 13.2 V,
100 V
VCC2
ICC1
Supply current from V CC 1
ICC2
Supply current from VCC2
IIH
IlL
tTypical values are at VCC1
3-32
VCC1
~
13.2 V,
~
100 V
MIN
Typt
MAX
UNIT
-1
-1.5
V
12 mA
IIOH - -1 mA
IIOH - -10 mA
94
97.5
II
~
92
94.5
IIOH
~
-15 mA
90
93.5
10H
~
-100~A
9
10
IIOL - 1 mA
IIOL ~ 10 mA
IIOL - 15 mA
100 ~A
IIOK - 20 mA
IIOK - -20 mA
VIH - VIHmin,
IOL
~
V
0.85
2
2
4
2.75
5
0.1
1
1
-1.2
2.5
VIL - VILmax,
2.5
V
V
1
~A
-1
~A
~
12 V, TA
~
VCC1
~
13.2 V,
VCC2
~
100 V
VCC2
~
100 V
I Outputs low
I Outputs high
25'C.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
0.05
1
0.1
1
1
5
mA
mA
SN55501E
AC PLASMA DISPLAY DRIVER
switching characteristics. VCC1 -
12 V. VCC2 -
PARAMETER
Delay time.
tDHL
tDLH
100 V. TA - 25°C
TEST CONDITIONS
MIN
TYP
MAX
Strobe to Q outputs
CL = 30 pF
250
high-to-Iow-
Sustain to Q outputs
CL=30pF
250
level outputs
Clock to serial data output
CL = 20 pF
147
Delay time.
low-to-high-
Strobe to Q outputs
CL - 30 pF
CL = 30 pF
450
Sustain to Q outputs
level outputs
Clock to serial data output
CL = 20 pF
147
450
UNIT
ns
ns
tTHL
Transition time, high-to-Iow-Ievel Q output
CL = 30 pF
200
ns
tTLH
Transition time. low-to-high-Ievel Q output
CL = 30 pF
300
ns
PARAMETER MEASUREMENT INFORMATION
OUTPUT
UNDER
TEST
--1"--+'
CL
•
TEST
POINT
(See Note A)
LOAD TEST CIRCUIT
DATA
x
IRRELEVANT
tau
~
-/f
VIH
X
.,
VALID
th
IRRELEVANT
VIL
1 50%
CLOCK
_~
VIH
VIL
tDHL~
VOH
WAVEFORM 1 (See Note B)
SERIAL
OUT
,50%
I
VOL
I
~tDLH-----t
I
WAVEFORM 2 (S.. Note C)
VOH
/50%
VOL
It--th--.l
VIH
~50%
STROBE
/50%
I
I
I
;/'50%
SUSTAIN
tDLH1-----+I
On
an WAVEFORM 2 (5.. Note E)
NOTES: A.
B.
C.
D.
E.
it
90%
10%
tDHL~
I
WAVEFORM 1 (See Note D) 90%
10%·
-.I
VIL
I
I
I
I.--th--+l
VIH
tDLH~
90%
10%
M-tTHL
lTHL
I
90%
10%
~ M-tTLH
VIL
VOH
VOL
VOH
VOL
CL includes probe and jig capacitance.
Serial out waveform for internal conditions such that a low is registered in R32.
Serial out waveform for internal conditions such that a high is registered in R32.
an output with a low stored in associated register Rn.
an o~tput with a high stored in associated register Rn.
VOLTAGE WAVEFORMS
FIGURE 1. SWITCHING CHARACTERISTICS
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DAttAS. TEXAS 75265
3-33
SN55501E
AC PLASMA DISPLAY DRIVER
RECOMMENDED OPERATING CONDITIONS
MAXIMUM CLOCK FREQUENCY
vs
JUNCTION TEMPERATURE
10
:t
9
>
u
c
8
I
!
0
;'
"0
iii
'<
0
:::iI,
.
<
G
(I)
~
lAo
...u
ts
E
~
.~
II
:t
...Iu
,7
6
5
10
VCC1 - 12 V
VIH - VCC1
VIL - 0
(SYMMETRICAL CLOCK PULSE)
N
::t
INPUT VOLTAGE LOGIC LEVEL LIMITS
vs
VCC1 SUPPLY VOLTAGE
-r--- t:::sr--.I
-
1
EOOEVities
4
3
>
I
--
II
'"
~
0
>
5Q.
..5
7
6
5
4
-
3
2
2
....-
_V ~\~~\l\
8
rGL.EOE~_r-
r.--~
CASCAO
----
9
-
VILmax
s
..'!
o
25
50
75
o
10
125
100
11
12
T J-Junction Temperature- °C
FIGURE 3
FIGURE 2
THERMAL CHARACTERISTICS
junction temperature formula
TJ = TA
+
PORO
where
TJ = virtual junction temperature
T A = free-air temperature
Po = average device power dissipation
RO = thermal resistance (junction-to-air. ROJA. or junction-to-case. ROJC)
PACKAGE
FD
JD
3-34
13
VCC1 - Supply Voltage -
RaJA
68°C/W
45°C/W
RaJC
. 20 0 C/W
12°C/W
TEXAS . "
INSTRUMENTS
POST OFFICE SOX 655012 • DALLAS, TeXAS 76265
V
14
SN65501E. SN75501E
AC PLASMA DISPLAY DRIVERS
02472, MARCH 1983-REVISED DECEMBER 1985
•
N PACKAGE
(TOP VIEW)
Controls 32 Electrodes
•
100-V Totem-Pole Outputs
•
Low Stand-by Power Consumption
•
A" Outputs Contain Sink and Source Clamp
Diodes
•
15 mA Steady-State Output Current
•
Rugged DMOS Outputs
•
CMOS Inputs
•
Direct Replacement for SN75501C
CLOCK
SUSTAIN
STROBE
01
02
03
04
05
06
07
08
09
010
all
012
013
014
015
016
GND
description
The SN65501 E and SN75501 E are monolithic
BIDFETt integrated circuits designed to provide
the serial-to-parallel conversion and level
translation of data in a matrix-addressable
display. The device inputs are diode-clamped
CMOS inputs.
The Q outputs of these drivers are normally high
and can be switched either selectively or
together. Any output whose associated register
bit (in the internal 32-bit serial register) contains
a low will switch low when the strobe input is
switched low if the sustain input is high. All other
outputs remain high. When the sustain input is
switched low, all outputs switch low
independently of the data or strobe inputs. This
feature can be used to generate a portion of the
sustain pulse required in the operation of an AC
plasma display. The internal level-shift circuits
provide additional drive during the times that the
outputs switch high to facilitate fast rise times
while maintaining low standby power
consumption. All outputs contain clamp diodes
to the VCC2 and GND supply inputs.
The SN65501 E is characterized for operation
over the temperature range of -40°C to 85°C.
The SN75501 E is characterized for operation
over the temperature range of OOC to 70°C.
VCCl
DATA IN
SERIAL OUT
032
031
030
029
028
027
026
025
024
023
022
021
020
019
018
017
•
...!IICD
>
,·C
Q
>
ca
Q.
!II
is
VCC2
FN PACKAGE
ITOP VIEW)
6
02
03
04
05
06
07
08
09
010
all
012
5 4
3
2
1 44 43 42 41 40
7
8
9
39
10
36
38
37
11
35
12
34
13
33
14
34
15
31
16
30
17
29
031
030
029
028
027
026
025
024
023
022
021
1819202122232425262728
t BIDFET -Bipolar, double-diffused. N-channel and P-channel
MOS transistors on same chip - patented process.
NC - No internal connection
Copyright @·1983, Texas Instruments Incorporated
PRODUCTION DATA documents contain information'
currant .s of publication date. Products conform to
specifications par the terms of Texas Instruments
:'~=i;a{:::.r~ ~!:\::i:; :I~o:=~:t:~~
not
TEXAS •
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
3-35
SN65501E, SN75501E
AC PLASMA DISPLAY DRIVERS
logic symbol t
functional block diagram (positive logic)
CMOSI
PlASMADISP
SUSTAIN
STROBE
CLOCK
DATA IN
CLOCK (1)
DATA IN (391
··
C
;"
ii
-<
"
...<"
..
••
•
2
2
[> 3
[> 3
2
2
[> 3
[> 3
2
2
C
(41 al
(51 Q2
·••
(191 a16
(221 a17
3~·BIT
STATIC
SHIFT
REGISTER
•••
(361
·•
031
(371 032
(381 6ERIAL OUT
[> 3
[> 3
ft)
UI
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEG Publication 617-12.
Pin numbers shown are for the N package.
I--~----D-- SERIAL OUT
FUNCTION TABLE
INPUTS
FUNCTION
LOAD
STROBE
SUSTAIN
DATA
CLOCK
STROBE
SUSTAIN
H
L
t
t
X
X
H
H
H
H
L
X
H
H
H
H
L
X
X
X
SHIFT REGISTER
Rl
R2
R3 ... R32
H
R2 n .. ·R31 n
R1n
L
R2 n .. ·R31 n
R1n
R3 n .. ·R32 n
R1n
R2n
R3 n .. ·R32 n
R1n
R2n
R3 n .. ·R32 n
R1n
R2n
OUTPUTS
SERIAL
DATA
R32 n
R32 n
R32 n
R32 n
R32 n
01
Q2
03 .••. 032
H
H
H
Rl
L
H
H
H
R2
L
H .... H
H .... H
H .... H
R3 .... R32
L .... L
H = high level. L = low level. X = Irrelevent. t = low-to-high-Ievel transition.
R1...R32 = levels currently at internal outputs of shift registers one through thirty-two. respectively.
Rl n... R32n = levels at shift-register output. Rl through R32 respectively. before the most recent t transition st the Clock input.
3-36
TEXAS
-If
INSTRUMENTS
POST OFFlc;e BOX 855012 • DALLAS, TEXAS ·75285
SN65501E. SN75501E
AC PLASMA DISPLAY DRIVERS
typical operating sequence
SUSTAIN
STROBE
U
(~
U~I
IRRELE~VANTIlJUlJ
CLOCK
B I
ANY Q OUTPUT
r'
EJ
schematics of inputs and outputs
'EQUIVALENT OF EACH INPUT
VCC1--------~----_.
TYPICAL OF ALL Q OUTPUTS
•
TYPICAL SERIAL OUTPUT
__~
INPUT ---i_ANIo-
ca
':I:'
CL
'::" (See Note AI
Q.
II)
is
LOAD TEST CIRCUIT
DATA
X
IRRELEVANT
---------'
VALID
X"---I-RR-E-L-E-V-A-N-T--- VIH
""--":"1..-------'..1
VIL
tsu-t~t--.....
f 4 - - - t h - - - - . ,..
~
CLOCK
~~---------------~""_ _ _.Jf50%
------..,
1:---'
_tw
.It
_I
tDHL_1
-------------~---~
I
}50%
WAVEFORM 1 (See Note BI
SERIAL
OUT
WAVEFORM 2 (See Note CI
~tDLH--.t
VOH
VOL
/50%
-
'1.1
,
-
On WAVEFORM 1 (See Note 01
On WAVEFORM
VIL
I
I
VIH
50 %
- I
tDLH-jf---+I
I
tDHL~
"N: -:- ----
~~~
2~(s:-e-e-:N-:-o-te-=EI~-":~!ii.!-
-
VIH
F 50 %
I.--th--+l""------'- 1
" - - - - - -7
tDHL~
VIL
VOH
VOL
~th---.l
SUSTAIN
VIH
I.
STROBE
-
-
-
I
~-
1ifo%
~~~
'l\;-----
•
f
PARAMETER MEASUREMENT INFORMATION
IL.
-
~~~
-:A'SO%
-~10%
~I
tDLH~
-
-
-=Z~O%
~~~
VIL
.~:~
VOH
VDL
NOTES: A. CL includes probe and jig capacitance.
B. Serial out waveform for internal conditions such that a low is registered in R32.
C. Serial out waveform for internal conditions such that a high is registered in R32.
D. an output with a low stored in associated register Rn.
E. Q n output with a high stored in associated register Rn.
VOLTAGE WAVEFORMS
FIGURE 1. SWITCHING CHA~ACTERISTICS
TEXAS ."
3-39
INSTRUMENTS
""sT OFFICE 80M 866012 •
bA~"".,
UXA8
1b~••
SN65501E, SN75501E
AC PLASMA DISPLAY DRIVERS
TYPICAL CHARACTERISTICS
INPUT VOLTAGE LOGIC LEVEL LIMITS
vs
VCC1 SUPPLY VOLTAGE
MAXIMUM CLOCK FREQUENCY
vs
JUNCTION TEMPERATURE
10
N
:I:
:IE
9
I
>
u
..
8
c
::J
go
C
0'
...£
6
0
5
u
(j
'C
iii
E
E
::J
'<
oj(
C
'"
:::S,
:IE
...
en
u
<
...I
CD
7
4
----
---
10
VCC1 = 12 V
VIH - VCCl
VIL - 0
..--
9
~\,,~\(\
8
(SYMME~RICAL CLOCK PULSEI
--sr
>
..
6
~
C4SC40EO~
~
5
G
"VC~EO~
__
I
Ol
>
:;
OElI/CES~
C-
.5
7
4
3
3
2
2
-
....
VILm ax
0
:;p
o
25
o
50
75
10
125
100
11
12
TJ-Junction Temperature- °C
FIGURE 3.
FIGURE 2
THERMAL CHARACTERISTICS
junction temperature formula
TJ = TA + PORO
where
TJ = virtual junction temperature
T A = free-air temperature
Po = average device power dissipation
RO = thermal resistance (junction-to-air, ROJA, or junction-to-case, ROJC)
PACKAGE
FN
N
3-40
13
VCC1-Supply Voltage- V
RaJA
RaJC
70 0 C/W
100·C/w
22°C/W
27°C/W
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
14
ADVANCE
INFORMATION
SN6550B, SN7550B
AC PLASMA DISPLAY DRIVERS
02924, DECEMBER 19B5-REVISED OCTOBER 19B6
FN PACKAGE
•
Controls 32 Electrodes
•
Very Low Steady-State Power Consumption
•
Rugged DMOS Outputs
•
CMOS-Compatible Inputs
•
Dependable Texas Instruments Quality and
Reliability
(TOP VIEW)
6
description
The SN65508 and SN75508 are monolithic
BIDFETt integrated circuits designed to provide
the serial-to-parallel conversion and level
translation of data in a matrix-addressable
display, All inputs are CMOS compatible and all
outputs are totem-pole DMOS structures,
If the strobe input is at a high logic level, all
outputs are high, When the strobe input goes
low, any output whose associated register bit
contains a low will go low, All outputs whose
associated register bit contains a high will remain
high. When the reset input is low, all register bits
are low. In this condition, ali outputs will go low
when the strobe input goes low. The serial data
output from the shift register may be used to
cascade additional devices. This output is not
affected by the Strobe input,
The SN65508 is characterized for operation from
-40°C to 85°C. The SN75508 is characterized
for operation from OOC to 70°C,
Qll
5 4
3 2
•
1 4443424 140
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
34
15
31
16
30
17
.>
en
G)
';:
Q
>
IV
Q.
en
29
is
1819202122232425262728
NC-No internal connection
logic symbol t
CMOS/
PLASMA DISPLAY
STROBE (42)
V2
RESET
CLK--'-'''--J;>
z
o
(61 01
(7) 02
··
·•
2
2
[>
[>
~
(21)016
:2:
(25)017
IX
oLL.
•
2
2
[>
[>
(39)031
(40) 032
Z
w
(3) SERIAL OUT
tThis symbol is in accordance with ANSI/IEEE Std 91-1094 and
lEe Publication 617-12.
.
(J
Z
~
c
tBIDFET -Bipolar, double-diffused, N-channel and P-channel MOS
transistors on same chip - patented process
ADVANCE INFORMATION documents contain
=::!=r.:~or~~~t"c::~~r'~
~ata and othar spacifications Ira subjlct to change
without notice.
DATA IN"'"- - - 0 1
32-BIT
STATIC
SHIFT
REGISTER
Q32
to---SERIAL OUT
typical operating sequence
R E S E T U _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ :::
STROBE
l>
CLOCK
<
l>
2
n
DATA
-
U
~
32
C
l>
m
2
-
-VIH
VIH
_ _ _ _ _ _ VIL
r-----------------------------------~-------VOH
OUTPUTS
U
DATA
'-----VOL
."
0
::0
s:
l>
:::!
0
2
TEXAS
3-42
-II
INSTRUMENTS
~O'T
OFFICI lOX 1111012 • OALLAS, TEXAS 1S281
SN65508, SN75508
AC PLASMA DISPLAY DRIVERS
ADVANCE
INFORMATION
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL Q OUTPUTS
--------~----_e_.~VCCl
vcc1--------~----~-e----
INPUT
TYPICAL OF SERIAL OUTPUT
-_.JVIIIt-_...
•
t-----....-OUTPUT
~
CD
>
";:
Q
>-
--------~~--------GND
GND~__----------~"'----
.!!
"~
Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC1 (see Note 1) ........................................... " 15 V
Supply voltage, VCC2 ..................................................... " 95 V
Input voltage, VI ........................................... -0.3 V to VCC + 0.3 V
High-level output voltage, VOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 95 V
High-level output current, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 3 rnA
Continuous total power dissipation at (or below)
25°C free-air temperature (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1700 mW
Operating free-air temperature range: SN6550B . . . . . . . . . . . . . . . . . . . . . . . . .. - 40°C to B5°C
SN7550B ............................ O°C to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Case temperature for 10 seconds ............................................. 260°C
NOTES: 1. Voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, derate linearly to 1088 mW at 70°C at the rate of 13.6 mW/oC.
z
o
~
ns
I
High-level output voltage
Low-level output voltage
TEST CONDITIONS
o outputs
VCCl
=
7.65 V,
Q outputs
VCCl - 7.65 V,
VCCl - 7 ..65 V,
Serial output
VCCl
Serial output
VOK
Output clamp voltage
VCC2
IIH
High-level input current
VI
IlL
Low-level input current
lOS
Short-circuit output current
ICCl
Supply current from VCCl
ICC2
Supply current from V CC2
=
=
MIN
MAX
-3 mA
83
87
10H - -50 ~A
10L - 10 mA
6.8
7.65
1.4
2.4
0
0.8
10H
=
10L = 50 pA
.110 - 100 mA, tw :5 1 ~s
0110 _ -100 rnA, tw :S 1 P.s
7.65 V,
=
= 9.35 V
VI = 0.4 V
Vo = 0
°C
9.35 V •
UNIT
V
V
2.5
-2.7
V
1
pA
-1
pA
-20
mA
500
pA
Output high
500
pA
Output low
8.5
mA
switching characteristics. VCC1 .. 7.65 V. TA
c
<
:t>
:2
PARAMETER
TEST CONDITIONS
Pulse duration, reset low
tdl
Delay time, V CC2 to Q outputs (10%
td2
10%1
Delay time, VCC2 to Q outputs (90%-90%1
RL - 100 kO,
RL - 100 kG,
CL - 100 pF
CL - 100 pF
(')
:t>
m
-
:2
"T1
o
:::0
s:
:t>
-I
6
:2
3-44
MIN
MAX
125
twRSTL
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
UNIT
ns
800
ns
800
ns
SN65508, SN75508
AC PLASMA DISPLAY DRIVERS
ADVANCE
INFORMATION
PARAMETER MEASUREMENT INFORMATION
141.---twCLK--~~
1
".'"
1
~"".
.,,),1.,.
\:: ---::
0_%_ _ _ _ _
..
1.---twCLK--~~
1
t4-- tsu-"~I..--th---+!
•
,
..J~O%
DATA IN _ _ _ _ _
1
6V
~
VALID
...O_%_ _ _ _ _ _ _
oV
•
~
~
·c
Q
>
ca
FIGURE 1. INPUT TIMING VOLTAGE WAVEFORMS
...... )~,~------------------::
a.III
is
I
VCC2
I
I
1.---10
..
I'S--~~
I
,
I
10%
----------~I--
~OO~%~--------90V
(4-td2-+1
I
,
- --,------
-OV
,
I..-:::::-:::------ VOH
I4-td1--.r1l90%
I
ANY OUTPUT
_____________....II110~ ________
FIGURE 2. VOLTAGE WAVEFORMS FOR OUTPUT DELAY TIMES
Z
VOL
o
i=
<
:E
a:
oLl-
Z
w
<
(.)
Z
~
<
o
TEXAS . "
INSTRUMENTS .
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
3-45
•
3-46
SN65509, SN75509
AC PLASMA DISPLAY DRIVERS
02923, OECEMBER 1985-REVISEO OCTOBER 1986
FN PACKAGE
•
Controls 32 Electrodes
•
Very Low Steady-State Power Consumption
•
Rugged DMOS Outputs
•
CMOS-Compatible Inputs
•
Dependable Texas Instruments Quality and
Reliability
(TOP VIEW)
~
~«
dUUU:JU tl':::cuul3
zzzuz>ozz""
6
description
The SN65509 and SN75509 are monolithic
BIDFETt integrated circuits designed to perform
the line~select operation of a matrix~addressable
display. All inputs are CMOS compatible and all
outputs are totem-pole DMOS structures,
The 8-bit data stored internally in the serial
register is transferred to one of four output
sections selected by the last two bits entered
into the 10-bh shift register. All 24 unselected
outputs will remain at the high level while the
state of the eight selected outputs will be set by
the corresponding data in the shift register.
VCC2 can be used as an output strobe as shown
in typical operating sequence.
5 4 3 2 1 4443424140
7
39
8
9
10
11
12
13
14
15
16
17
38
•
37
36
35
..
403
en
34
33
34
31
30
29
1819202122 232425262728
LOc'ol'-OOOU
G)
401
308
307
306
305
>
"a;:
C
>-
IV
is.
en
o
Nr-NMo::t
OOOOzz UOOOO
NNNNC)
~C")M('f')("I')
NC - No internal connection
The SN65509 is characterized for operation from -40°C to 85°C. The SN75509 is characterized for
operation from OOC to 70°C.
FUNCTION TABLE
INPUT BITS
OUTPUTS
FIRST
LAST
ENTERED
08
4
4
4
07
ENTEREO
06
05
04
08
03
02
01
S1
SO
BYTE 4
BYTE 3
BYTE 2
BYTE 1
408-401
308-301
208-201
108-101
01
~
L
L
All H
All H
All H
08-01
~
L
H
All H
All H
08-01
All H
08-01
~
H
L
All H
08-01
All H
All H
08
~
H
H
All H
All H
All H
01
08
01
08
01
t BIDFET - Bipolar, double~diffused, N-channel and P-channel MOS transistors on same chip - patented process
Copyright © 1985, Texas lnstrumen.ts Incorporated
PRODUCTION DATA documents ,ontain information
current as of publication data. Products conform to
TEXAS . .
INSTRUMENTS
specifications per the terms of Taxas Instruments
:~~~~:~~i~8i~:1~1i ~!=:~ti:r :,~o::;:::::.::.~s
not
~OST
OFFICE; sOX 65$012 • DALLAS, texAS 76265
3-47
SN65509. SN75509
AC PLASMA DISPLAY DRIVERS
logic symbol t
CMOS/PL.~ lQl
8.11
C>~ 108
1.12
201
11
G14
·· ··
C>~
·· ··
C>~
·· C>~
··
C>~
·· C>~
·
[OlJ
Zl
iii'
[02J
Z2
jjj'
[03J
Z3
8.12
C>~ 2Q8
[04J
Z4
1.13
3Ql
[05J
Z5
[06J
Z6
[07J
Z7
[08J
Z8
C
'0
<
..<'
..
C
CD
en
8.13
3Q8
1.14
4Ql
8.14
4Q8
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
functional block diagram
101
•
•
108
2Ql
•
O.
';:
Q
>-
C\'I
UNSElECTED
OUTPUTS
Q.
II)
is
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF All OUTPUTS
VCC1--------e-----e-._-
------~------.-~I--VCC2
OUTPUT
INPUT --e-...,..'Ir-_"
------~~~----~._GND
GND~~----------~~-
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
3-49
•
SN65509, SN75509
AC PLASMA DISPLAY DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 V
Supply voltage, VCC2 ..................... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 95 V
Input voltage, VI ........................................... -0.3 V to VCC + 0.3 V
High-level output voltage, VOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 95 V
High-level output current, IOH ........................... :. . . . . . . . . . . . . . . . . .. .:.. 3 mA
Low-level output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 25 mA
Continuous total power dissipation at (or below)
25°C free-air temperature (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1700 mW
Operating free-air temperature range: SN65509 .......................... -40°C to 85°C
SN75509 ............................ ooC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Case temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
NOTES:
1. Voltage values are with respect to network ground terminal.
2. For operation above 25°C free·air temperature, derate linearly to 1088 mW at 70°C at the rate of 13.6mW/oC.
recommended operating conditions
MIN
MAX
UNIT
Supply voltage, VCCl
8
11.4
V
Supply voltage, VCC2
Veel
8.5
SO
V
VCCl - 11.4 V
VCCl -8V
High·level input voltage, VIH
VCCl - 11.4 V
Low·level input voltage, VIL
VCCl
~8V
6
0
VeCl
2.S
0
2
Output current, 10 Itw :5 1 ~sl
Clock frequency; fclock
Setup time, data before clock!, tsu
Hold
tim~,
data after clock!, th
Pulse duration, clock' high or low, twCLK
I
I
Operating free-air temperature, T A
Veel
V
V
80
mA
3.1
MHz
100
ns
100
ns
SN6550S
161
-40'
SN7550S
0
ns
85
70
°C
electrical characteristics over recommended operating free-air temperature range, VCC1 == 11.4 V,
VCC2 = 90 V (unless otherwise noted)
PARAMETER
~
TEST CONDITIONS
8 V,
IOH ~ -3 mA
Low·level output voltag,
VCCl
VCCl
~
8 V,
VOK
Output clamp voltage
VCC2
~
IIH
High-level input current
0110 110 VI - 11.4V
IlL
Low-level input current
VI - 0.4 V
lOS
Short-circuit output current
Vo
ICCl
Supply current from
VOH
High·level output voltage
VOL
ICC2
3-50
~
IOL ~ 20 mA
100 mA, tw :5 ,. ~s
-100 mA, tw::; 1
0
Vee 1
Supply current from VCC2
All outputs high
Eight outputs low
TEXAS •
INSTRUMENTS
PoST OFPICI lOX 861012 • DII••AS, tEXAS 752 . .
p.S
MIN
MAX
83
1.4
87
V
2.4
2,5
V
-2.7
UNIT
V
1
-1'
~A
-20
mA
500
~A
~A
500
~A
5
mA
SN65509, SN75509
AC PLASMA DISPLAY DRIVERS
switching characteristics. VCC1
PARAMETER
TEST CONDITIONS
tdl Delay time. VCC2 to Q outputs (10% td2 Delay time. VCC2 to Q outputs (90% -
10%1
RL = 100 kll.
90%1
RL
=
100 kll.
MAX
UNIT
100 pF
800
ns
CL = 100 pF
800
ns
CL
=
MIN
PARAMETER MEASUREMENT INFORMATION
1'114f----t wCLK--.........1
r-----------~
CLOCK
I
I
~'-O_%__________-Jl:~
-fo%
__
7V
•
~
CD
0 V
>
'0:
Q
1'114--- t wCLK--.......
1lI
>
ca
en
t
I4--tsu-....'"14t--th~
I
-'JEo%
DATA IN _ _ _ _ _ _
I
Q.
7V
}E,-o~%_______ o
VALID
is
V
FIGURE 1. INPUT TIMING VOLTAGE WAVEFORMS
r-------------SOV
/.SO%
VCC2
___________________10_%~i- 1_ - -- -- - - -:
i4-ld2....-t
I
ANY OUTPUT
I+--
-0 V
1!.1'"S-O%--------'VOH
td1
--+i:
----------------------1 - - - --- -10%
-VOL
FIGURE 2. VOLTAGE WAVEFORMS FOR OUTPUT DELAY
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-51
•
3-52
SN655128, SN755128
VACUUM FLUORESCENT DISPLAY DRIVERS
02654, DECEMBER 1985
•
Each Device Drives 12 Lines
•
60-V Output Voltage Swing Capability
•
25-mA Output Source Current Capebility
•
High-Speed Serially-Shifted Data Input
•
TTL-Compatible Inputs
•
Latches on All Driver Outputs
DW,N
DUAL·IN·LlNE PACKAGE
ITOP VIEW)
010
011
012
09
as
STROBE
SERIAL OUT
07
DATA IN
as
LATCH ENABLE
01
05
04
02
03
description
The SN65512B and SN75512B are monolithic
BIOFETt integrated circuits designed to drive a
dot matrix or segmented vacuum fluorescent
display,
All device inputs are diode-clamped p-n-p inputs
and will assume a high logic level when opencircuited, The nominal input threshold is 1,5
volts. Outputs are totem-pole structures formed
by an n-p-n emitter follower and double-diffused
MaS (OMOS) transistors.
•
VCC2
GND
VCC1
CLOCK
logic symbol:!:
LATCH ENABLE IB)
STROBE 13
The device consists of a 12-bit shift register. 12
latches. and 12 output AND gates. Serial data
is entered into the shift register on the low-tohigh transition of the Clock. When high. the
Latch Enable input transfers the shift register
contents to the outputs of the 12 latches. The
active-low strobe input enables all Q outputs.
Serial data output from the shift register may be
used to cascade shift registers. This output is not
affected by the Latch Enable or Strobe inputs.
TTLNAC
FLUOR DISP
C2
(9)
20 t>
20 t>
(12) Q4
20 t>
3
20 t>
3
20 t>
3
20 t>
20 t>
07
3
(1B)
as
3
(19)
09
3
(20)
010
3
20 t>
3
20 t>
The SN65512B is characterized for operation
from -40°C to 85°C. The SN75512B is
characterized for operation from OOC to 70°C.
01
(10)
02
3
3 111) Q3
20 t>
(13)
(14)
as
06
(17)
(1)
(2)
(4)
011
012
SERIAL OUT
t This svmbol is in accordance with ANSI/IEEE Std 91·1984
and IEC Publication 617·12.
t BIOFET - Bipolar, double·diffused. N·channel and P·channel MOS transistor. on same chip - patented process.
PRDDucnDI DATA dacU..I.llnIIIll.fal1llltla.
.omlt II at ",,"lillian Uta. Pnd.cto .1.fIr.. to
.p••IIIcItI... por til. 11l1li of T.... 111I1U..11II
=~I:"''' =:':1 :;::no..:::.::.' III
Copyright @ 1985. Texas Instruments Incorporated
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 866012 • DALLAS. TEXAS 76285
3-53
SN655128, SN755128
VACUUM FLUORESCENT DISPLAY DRIVERS
functional block diagram (positive logic)
LATCH
ENABLE
STROBE
II
;----""'R1
CLOCK
R2
12
LATCHES
12-BIT
STATIC
SHIFT
REGISTER
DATA
IN
R11
R12
> - - - - - - - - SERIAL OUT
FUNCTION TABLE
CONTROL INPUTS
FUNCTION
LATCH
CLOCK ENABLE STROBE
lOAD
LATCH
STROBE
H
r
Nor
X
X
X
X
SHIFT REGISTER
x
x
Load and shift t
X
L
H
X
X
X
X
X
H
L
No change
As
As
As
As
determined
determined
determined
determined
= high level, L = low level, X = irrelevant,
OUTPUTS
LATCHES
LC1 THRU LC12
SERIAL
Determined by Latch Enablet
Determined by Latch Enablet
R12
R12
Determined by Strobe
Determined by Strobe
above Stored data
above New data
above Determined by Latch Enablat
above Determined by Latch Enablet
R12
R12
R12
R12
Determined by Strobe
Determined by Strobe
All L
LC 1 thru LC 12, respectively
R1 THRU R12
Q1 THRU Q12
r = low-to-high-Ievel transition.
t R12 takes on the state of R11 , R11 takes on the state of R10, . . . R2 takes on the state of R1 , and R1 takes on the state of the data input.
*New data enter the latches while Latch Enable is high. These data are stored while Latch Enable is low.
3-54
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN655128, SN755128
VACUUM FLUORESCENT DISPLAY DRIVERS
typical operating sequence
CLOCK
DATA
IN
IRRELEVANT
VALID
SR
__________- L___________v_A_L_ID___________
coNTENTS ___________I_N_v_AL_ID
LATCH
ENABLE
______________________
______________
•
I!!
CD
,NEW DATA VALID
PREVIOUSLY STORED DATA
LATCH
CONTENTS
STROBE
~rl~
>
'i:
Q
--------------------------------...,
~-~
Q OUTPUTS
>
ca
Q.
II)
VALID
is
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
VCC1--------~--------
OUT
--------~------VCC2FOR
Q OUTPUTS
VCC1 fOR
SERIAL OUTPUT
.....---OUTPUT
__ --.J
INPUT - -......--f
j]
:
TEXAS
-If
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
GND
3-55
SN65512B, SN75512B
VACUUM FLUORESCENT DISPLAY DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
c(ii'
Supply voltage, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 V
Supply voltage, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 70 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. VCC1
Continuous total power, dissipation at (or below) 25°C free-air temperature (see Note 2)
.
OW package ..................................................... ;. 1125 mW
N package ............... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1150 mW
Operating free-air temperature range: SN65512B.. . . . . . . . . . . . . . . . . . . . . . . .. - 40°C to 85 °C
SN75512B ............................ OOCto70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 260°C
NOTES: 1. Voltage values are with respect to network ground terminal.
"'C
2. For operation above 25°C free-air temperature, derate the OW package at the rate of 9.0 mWI DC and the N package at the
rate of 9.2 mW/oC.
iii
-<
C
:::!,
recommended operating conditions
<
CD
til
MIN
5
Supply voltage, VCCI
Supply voltage, VCC2
High-level input voltage, VIH
SN65512B
MAX
15
0
2
Low-level input voltage, VIL
High-level output current, IOH
Low-level output current, IOL
Clock frequency, f clock
Pulse duration, clock high or low, tw
Setup time, data before clockt, tsu
(see Figure 1)
VCCI
Vcel
VCCI
VCCI
VeCl
= 10V
= 15 V, TA =
= 5 V, TA =
- 15 V, TA = 5 V, TA =
VCCI - 15 V,
VCCI - 5 V,
VeCl = 15 V,
VCCI = 5 V,
Hold time, data after clockt, th
(see Figure 1)
25°C
25°C
25°C
25°C
TA - 25°C
TA - 25°C
TA = 25°C
TA = 25°C
Operating free-air temperature, T A
60
SN75512B
MIN
5
0
2
MAX
15
60
0.8
-25
0.8
-25
5
4
1
5
4
1
0
0
100
500
85
V
V
V
V
mA
mA
MHz
ns
500
100
100
250
50
250
-40
0
0
100
UNIT
ns
250
50
250
0
ns
70
°c
electrical characteristics over recommended operating free-air temperature range, VCC2 - 60 V (unleSs
otherwise noted)
VIK
PARAMETER
Input clamp voltage
High-level output
57.5
58
9
9.5
2.6
Q outputs
IOH = -25 mA
Serial output
voltage
High-level input current
Low-level input current
Serial output
IIH
IlL
ICCI
Supply current fr,om V CC 1
ICC2
Supply current from ,VCC2
IOH = -200 pA, VCCI - 10 V
IOL = 5 mA,
VCCI = 10V
IOL = 200 ~A,
VCCI - 10V
VI - 5 V
VCel - 15 V,
VI = 0.8 V
VCCI = 15 V,
'VI = 5 V
VCCI = 15 V
VI - 0.8 V
All outputs high
VCCI = 15 V
Strobe at 2 V
VOL
t Ali typical values are at veel
3-56
MIN
voltage
Low-level output
VOH
Q outputs
TVpt
TEST CONDITIONS
11= -12 mA
10 V, TA = 25°C.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 866012 • DALLAS, TEXAS 76266
0.05
0.01
-25
MAX
-1.5
UNIT
V
V
5
0.2
1
-150
V
~A
~A
80
2
10
500
~A
6
100
0.8
3
mA
pA
mA
SN655128, SN755128
VACUUM FLUORESCENT DISPLAY DRIVERS
switching characteristics. VCC1
10 V. VCC2 '" 60 V. TA
PARAMETER
TEST CONDITIONS
tDHL
Delay time, high-to-Iow-Ievel output
tDLH
Delay time, low-to-high-Ievel output
tTHL
Transition time, high-to-Iow-Ievel output
tTLH
Transition time, low-to-high-Ievel output
MIN
CL = 30 pF,
See Figure 2
MAX
UNIT
300
300
500
500
ns
ns
ns
ns
PARAMETER MEASUREMENT INFORMATION
~--------tw------~~~I
I
,.-------""'-f--- -
f
>
"a::
II)
VIH
I
CLOCK
Q
>
as
Q.
tn
is
~-------tw------__~
t+--tsu--~~-th---+l
I
I
I
I
N\/\/\l!
DATA IN
\I\!\/\I\
- -
\ V V \ N \ I VIH
VALID
/\/\/\/\/
"-""'~-~-~-VIL
-
FIGURE 1. INPUT TIMING VOLTAGE WAVEFORMS
I4-----+j-'" 30 ns
I+----+t-'" 30 ns
I
I
I
I
I
I
I
I
I
I
I
I :
I
I
I
STROBE
I
I
I
~
I
90%
1.5 V
_ _ _ _ _ _1;.;:0;':'%";Jf:._1 _ _ _ _ _ _ _ _ 0 V
I
I4-tDHL-+t
I4-tDLH-+!
I
I
I
OUTPUTS
~1~~-------3V
I
I
Q
I
I
I
I
I'
I
I
,,_-------"'\ll-90%
- ---VOH
I
I
I
I
I
i+---+I-tTLH
I
I
I
I
I
I
I
VOL
\4---W- t THL
FIGURE 2, SWITCHING-TIME VOLTAGE WAVEFORMS
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
3-57
3-58
SN65513B,SN75513B
VACUUM FLUORESCENT DISPLAY DRIVERS
02721. MARCH 1983-REVISED SEPTEMBER 1986
OW OR N PACKAc;iE
ITOPVIEW)
•
Each Device Drives 12 Lines
•
60-V Output Voltage Swing Capability
•
25-mA Output Source Current Capability
•
High-Speed Serially-Shifted Data Input
•
TTL-Compatible Input
•
Reset Input
all
012
STROBE
SERIAL OUT
DATA IN
VCCl
CLOCK
RESET
01
02
description
The SN65513B and SN75513B are monolithic
BIDFETt integrated circuits designed to drive a
dot matrix or segmented vacuum fluorescent
display.
010
09
08
07
VCC2
GND
06
05
04
03
•
~
~
·C
Q
All device inputs are diode-clamped p-n-p inputs
and will assume a high logic level when left open.
The nominal input threshold is 1 .5 volts. Outputs
are totem-pole structures formed by n-p-n
emitter follower and double-diffused MOS
(DMOS) transistors.
>ca
Q.
.!
C
The device consists of a 12-bit shift register and 12 output AND gates. Data is entered into the shift register
outputs. The
on the low-to-high transition of the Clock input. The active-low strobe inpLit enables all
Reset input sets the shIft register contents to all lows. The serial data output from the shift register may
be used to cascade additional devices. This output is not affected by the strobe input.
a
The SN65513B is characterized for operation from -40°C to 85°C and the SN75513B is characterized
for operation from OOC to 70°C.
logic symbol*
TTUVAC
FLUOR DIS.
STROBE
RESET
CLOCK
191
DATA IN
I>
I>
I>
I>
I>
I>
I>
I>
I>
I>
I>
1101
2
2
1111
1121
1131
1141
2
2
2
2
2
2
1171
(IBI
1191
1201
(11
121
(41
01
02
03
04
05
06
07
08
09
010
011
012
SERIAL OUT
t BIDFET -Bipolar. double·diffused. N·channel and P-channel MOS transistors on same chip-patented process.
t This symbol is in accordance with ANSIIIEEE Std 91-1984 and lEe Publication 617-12.
Copyright @ 1983. Texas Instruments Incorporated
PRODUCTION DATA d••• ment. • ..tain
~~J:::i::nt.~~~:t":i;:'trD~b~iC::~t~ ::
of TaXI. Instruments standi'S· warranty.
Production procasslng doas nDt n.c....rUy
include teating of all p.ramater•.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
3-59
SN65513B, SN75513B
VACUUM FLUORESCENT DISPLAY DRIVERS
logic diagram (positive logic)
STROBE
RESET
CLOCK
DATA IN
SHIFT
REGISTER
------+--+----1 10
01
Rl
....---IR
"'+---bCl
10
02
R
Cl
••• •••
•
••
Rll
R
Cl
I'D
012
R
L-_ _ _~Cl
SERIAL OUT
FUNCTION TABLE
INPUTS
FUNCTION
LOAD
STROBE
RESET
RESET
CLOCK
OUTPUTS
STROBE
SHIFT REGISTERS
Rl THRU R12
SERIAL
01 THRU 012
H
t
X
Load and Shift t
R12t
Determined by strobe
H
H
L
Not
Not
H
R12
R12
H
X
No Change
No Change
All L
All L
R1 thru R12, respectively
All L
L
L
H = high level. L = lo,!" level, X = irrelevant, t = low-to-high transition.
t R12 and the serial output take on the state of R11, R11 takes on the state of RIO , , , R2 takes on the state of Rl , and
R1 t~kes on the state of the data input,
3-60
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS; TeXAS 75285
SN655138, SN755138
VACUUM FLUORESCENT DISPLAY DRIVERS
typical operating sequence
CLOCK
DATA IN
SR CONTENTS
IRRELEVANT
VALID
INVALID
•
CLEARED
VALID
u
RESET
r!
CD
>
'C
STROBE
C
Q OUTPUTS
>
as
"S.
U)
VALID
is
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
VCCl ---------1~--------
VCC2 FOR
Q OUTPUTS
VCCl FOR
SERIAL OUTPUT
f--------
OUTPUT
--~Sl
INPUT - -...---1
~GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 V
Supply voltage, VeC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 70 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Vee1
eontinuous total dissipation at (or below) 25°e free-air temperature (see Note 2). . . . . .. 1150 mW
Operating free-air temperature range: SNG5513B.. . . . . . . . . . . . . . . . . . . . . . . .. - 40 °e to 85°e
SN75513B ............................ ooe to 70 0 e
Storage temperature range ......................................... - 65 °e to 150 0 e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260 0 e
NOTES: 1. Voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, derate linearly to 598 mW at 85°C at the rate of 9.2 mW/oC.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75285
3-61
SN65513B, SN75513B
VACUUM FLUORESCENT DISPLAY DRIVERS
recommended operating conditions, T A -
- 40°C to 85 °C (unless otherwise noted)
MIN
MAX
Supply voltage. VCCl
5
15
V
Supply voltage. VCC2
0
60
'v
High-level input voltage. VIH
2
0.8
V
25
mA
mA
V
Low-level input voltage. VIL
High-level output current. IOH
Low-level output current. IOL
•
VCCl = 10 V
VCCl - 15 V.
VCCl = 5 V.
Clock frequency. fclock
5
TA - 25°C
0
4
TA = 25°C
1
Pulse duration, clock high, tw
VCCl - 15 V.
VCCl - 5 V.
TA - 25°C
0
100
TA = 25°C
500
Setup time. data before clockt (see FiQure 11. tsu
VCCl - 15 V.
VCCl - 5 V.
TA - 25°C
100
TA - 25°C
250
VCCl = 15 V.
VCCl = 5 V.
SN65513B
TA = 25°C
50
TA = 25°C
250
Hold time. data after clockt (see Figure 11. th
Operating free-air temperature, T A
SN75513B
PARAMETER
Input clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
IIH
High-level input current
IlL
Low-:-Ievel input current
ICCl
ICC2
TEST CONDITIONS
11- -12 mA
IOH - -25 mA
ns
ns
-40
85
0
70
Q outputs
Serial output
Q.outputs
Serial output
Supply current from VCCl
Supply current from VCC2
MIN
57,5
200 ~A
IOH IOL - 5 mA
9
MHz
ns
Typt
°C
10 V,
electrical characteristics over recommended operating free-air temperature range, VCC1
VCC2 - 60 V (unless otherwise noted)
VIK
UNIT
MAX
UNIT
-1.5
V
58
9,5
V
2,6
5
0.05
0.2
V
IOL - 200 ~A
VCCl = 15 V.
VI = 15 V
0.Q1
1
~A
VCCl - 15 V.
VCCl - 15 V.
VI - 0 V
All inputs at 5 V
-25
-150
~A
0,08
0.5
VCCl = 15 V.
VCCl = 15 V.
All inputs at 0,8 V
2
0.01
6
0.1
VCCl - 15 V.
Strobe at 2 V
0.8
3
All outputs high
mA
mA
t All typical values are at VCCl = 10 V. TA = 25°C.
switching characteristics, VCC1 ... 10 V, VCC2
PARAMETER
3-62
60 V, TA
TEST CONDITIONS
tDHL
Delay time. high-to-Iow-Ievel output
tOLH
Delay time. low-to-high-Ievel output
tTHL
Transition time, high-to-Iow-Ievel output
tTLH
Transition time, low-to-high-Ievel output
MAX
UNIT
300
ns
CL = 30 pF.
300
ns
See Figure 2
500
ns
500
ns
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MIN
SN655138, SN755138
VACUUM FLUORESCENT DISPLAY DRIVERS
PARAMETER MEASUREMENT INFORMATION
•
FIGURE 1. INPUT TIMING VOLTAGE WAVEFORMS
_
_
-,
STROBE
30
I'
I I
3V
--'I.J
~
L1"90%
~"
.. _ _ _ _ _....;';.;;O.;.;:%~$t:;-I _ _ _ _ _ _ _ 0 V
".5 V
~tDLH~
Q OUTPUTS
14-,,30 ns
~
ns
"
}
1
I
~tDHL~
:Ii
90%~ VOH
-+I 14- tTLH
I ,
VOL
.-.I I4--tTHL
FIGURE 2. SWITCHING-TIME VOLTAGE WAVEFORMS
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-63
C
iii'
'CI
Di
<
...C
<'
CD
;
3-64
SN75514
VACUUM FLUORESCENT DISPLAY DRIVER
ADVANCE
INFORMATION
APRIL 19B3-REVISED SEPTEMBER 19B6
OW OR N PACKAGE
(TOP VIEW)
•
Each Device Drives 12 Lines
•
125-V Output Voltage Swing Capability
•
25-mA Output Source Current Capability
•
High-Speed Serially Shifted Data Input
•
CMOS-Compatible Inputs
•
Latches on All Driver Outputs
011
012
STROBE
SERIAL OUT
DATA IN
VCCl
CLOCK
01
02
03
010
09
08
07
VCC3
VCC2
GND
06
05
04
~
(I)
>
description
";:
Q
The SN75514 is a monolithic BIOFETt integrated circuit designed to drive a dot matrix or segmented vacuum
fluorescent display. All device inputs are diode-clamped CMOS compatible inputs. The outputs are totempole structures formed with double-diffused MaS (OMOS) transistors.
The device consists of a 12-bit shift register, a 12-bit storage register, and 12 output AND gates. Serial
data is entered into the shift register on the low-to-high transition of the clock input. On the high-to-Iow
transition of the strobe input, data is transferred from the shift registers to the latches. When Strobe goes
high, all Q outputs are enabled. Serial data output from the shift register may be used to cascade additional
devices. Serial Out is not affected by the Strobe input.
>
ca
Q.
III
is
Supply voltage VCC2 and VCC3 are used to provide 25-milliampere output source current capability at
acceptable static device power dissipation. In this mode of operation VCC3 should be equal to
VCC2 + 10 volts. It is possible to operate this device with VCC3 = VCC2. However, the current capability
will be reduced.
The SN75514 is characterized for operation from OOC to 70°C.
logic symbol:!:
logic diagram (positive logic)
STROBE-----i
>--....------.
STORAGE
REGISTER
STROBE
z
o
OATAIN
CLOCK_,....-.p.
CLOCK
DATA IN
181
20
20
20
20
20
20
20
20
20
20
20
20
I>
I>
I>
I>
I>
I>
I>
I>
I>
I>
3
3
3
Q2
1101
Q3
1111
Q4
1121
1131
3
3
3
1171
1181
1191
1201
i=
01
191
recommended operating conditions
CU
MIN
Supply voltage, V CC 1
5
Supply voltage, V CC2
0
Supply voltage, VCC3
VCC2
High-level input voltage, VIH (see Figure 11
VCC1 -5V
VCC1 = 15 V
Low-level input voltage, VIL (see Figure 11
VCC1 -5V
VCC1 - 15 V
NOM
MAX
15
130
VCC2+ 1O
4
11.25
3.75
25
Low-level output current, IOL
Clock frequency, fclock Isee Figure 21
0
UNIT
V
V
V
V
mA
2.5
mA
7.5
MHz
Data setup time before clockt, tsu (see Figure 31
150
ns
Data hold time after clockt, th Isee Figure 31
150
ns
I VCC
- 5 V
IVCC-15V
Operating free~air temperature, TA
1200
ns
500
0
Q.
I/)
Q
V
1
High-level output current, IOH (T A - 25°CI
Delay time, strobe low to clock high, tdISL-CHI
.
70
°c
2:
o
~
~
:E
t%:
oLL
2:
w
~
(.)
2:
~
>
C
~
TEXAS . "
INSTRUMENlS
POST OFFICE B,?X 655012 • DALLAS, TeXAS 75265
3-67
SN75514
VACUUM FLUORESCENT DISPLAY DRIVER
ADVANCE
INFORMATION
electrical characteristics over recommended operating free-air temperature range. VCC1 -10 V (unless
otherwise noted)
IIH
IlL
PARAMETER
Input clamp voltage
High-Ieyel output
voltage
Low-level output
voltage
High-level input current
Low-level input current
ICCl
Supplv Current from V CC 1
ICC2
Supply Current from V CC2
VIK
VOH
VOL
C
ii'
i:i"
'C
TEST CONDITIONS
a outputs
Serial
a outputs
Serial
;;;
ICC3
VCC2
10H =
10L =
10L =
VCCl
VCCl
VCCl
VCCl
VCCl
VCC2
VCC3
<
...C
<"
CD
MIN
TVpt
125
9
126
9.3
1.6
11= -1 mA
- 130 V,
-200 ~A
2.5 mA
200 ~
- 10 V,
- 10V,
- 15V
= 5V
= 15 V,
= 130V,
= 140 V
VCCl = 15 V,
VCC2 = 130 V,
VCC3 = 140 V
Supply Current from ICC~
10 = -25 mA
0.Q1
VI = 10 V
VI = OV
MAX
-1.5
UNIT
V
V
5
1
1
-5
5
5
All outputs high
-5
All outputs low
0.1
V
~
~
mA
mA
All outputs high
5
mA
Strobe at 0 V
0.1
t All typical values are at TA = 25 ·C.
switching characteristics. VCC1 - 15 V. VCC2 - 130 V. TA - 25°C
tDHL
tDLH
trHL
tTLH
PARAMETER
Delay time, high-to-lo\N-level output
Delay time, low-to-high-Ievel output
Transition time, high-to-Iow-Ievel output
Transition time, low~to~high~level output
TEST CONDITIONS
CL = 30 pF,
See Figure 4
»
~
2
n
m
2
"TI
is:
»
:::!
o
2
3-68
TEXAS ..Jg.
INSlRUMENlS
PO$T OFFICE BOX 6&5012 • DALLAS. TEXAS 75285
MIN
MAX
0.8
0.8
1
3
UNIT
~
~s
~
~
ADVANCE
INFORMATION
SN75514
VACUUM FLUORESCENT DISPLAY DRIVER
RECOMMENDED OPERATING CONDITIONS
INPUT THRESHOLD
12
vs
SUPPL Y VOLTAGE VCC1
SUPPLY VOLTAGE
I
T
10
....
8
~~
.
8
T
4
>
'>
:'t!
./
-l'o/
/~
~
a.
c
"'\. v
2
V
o
3
5
7
9
0
/
r
/
!l 5
~
I&.
V
~E
4
1/
3
~
.§ 2
/V
i
11
I
0
7
~ 8
o>(i\
~
I
TA=O Cto70 C
~
~
0
8
7
TA = O·Cto 70·C
>I
MAXIMUM INPUT DATA RATE
vs
13
15
o
4
8
V
•
/
V
/
8
10
12
14
16
Supply Voltdge VCC1-V
Supply Voltage VCC1-V
FIGURE 1
FIGURE 2
2
o
i=
<
~
a:::
ou.
-w
2
(.)
2
~
<
C
TEXAS
41
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TeXAS 75285
3-69
SN75514
VACUUM FLUORESCENT DISPLAY DRIVER
ADVANCE
INFORMATION
PARAMETER MEASUREMENT INFORMATION
Ie
tw~
1
Ir-----""I:
I
CLOCK
I
1
I
1+--- tw ~-_.I
je--tsu~th--+l
C
iii'
'C
iii
I
:
Dm ••
1
:
<>(XX)
VAUD
...C
FIGURE 3. INPUT TIMING VOLTAGE WAVEFORMS
CD
-l- - - - - '
N
<'
iil
STROBE
,........oQO ns
k-+l--oQO ns
I
I
I
I
f--------I 50%
:-------;~Q1'---------- OV
I
j4---tf-. t OHL
~
tI
tOLH
1
!\":,,,
1 1
~tTHL
VOH
Yl----nvDC
1- ~I
t
~ TLH
FIGURE 4. SWITCHING·TIME VOLTAGE WAVEFORMS
»
c
~
:2
(')
m
:2
."
o
::KJ
3:
»
::!
o
:2
3-70
V"
-1{:I-1P""::9~0%::------- VCC1
---__..1
a OUTPUTS
VIH
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • OAll-AS, TEXAS 75265
SN65518, SN75518
VACUUM FLUORESCENT DISPLAY DRIVERS
02720, MARCH 1983-REVISEO OCTOBER 1986
•
Each Device Drives 32 Lines
•
60-V Output Voltage Swing Capability
•
25-mA Output Source Current Capability
•
High-Speed Serially Shifted Data Input
•
Latches on All Driver Outputs
N DUAL-IN-LiNE PACKAGE
(TOP VIEW)
VCC2
SERIAL OUT
032
031
030
029
028
027
026
025
024
023
022
021
020
019
018
017
description
The SN65518 and SN75518 are monolithic
BIDFETt integrated circuits designed to drive a
dot matrix or segmented vacuum fluorescent
display.
The devices each consist of a 32-bit shift
register, 32 latches, and 32 output AND gates.
Serial data is entered into the shift register on
the low-to-high transition of the clock input.
While the Latch Enable input is high, parallel data
is transferred to the output buffers through a
32-bit latch. Data present in the latch during the
high-to-Iow transition of Latch Enable is latched.
When the Strobe input is low, all Q outputs are
enabled. When the Strobe input is high, all Q
outputs are low.
GND
::C~~:~~i~ai~:I~"'i =::~i:r :.~o:::::~:s nDt
•
LATCH ENABLE
"""L_ _..r-
CLOCK
FN PACKAGE
ITOP VIEW)
I-
::::>
o
The SN65518 is characterized for operation from
-40 oe to 85°e and the SN75518is
characterized for operation from ooe to 70 oe.
PRODUCTION DATA documenls conlain information
current as of publicatioJl data. Products conform to
specifications per the terms of Taxas Instruments
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015
016
STROBE
Serial data output from the shift register may be
used to cascade additional devices. This output
is not affected by the Latch Enable or Strobe
inputs.
tBIDFET -Bipolar, double-diffused, N-channel and P-channel MOS
transistors on same chip-patented process.
VCCl
DATA IN
6
5 432
1 4443424140
7
39
8
38
9
37
10
36
11
12
35
34
13
14
33
32
15
31
16
30
17
29
1819202122232425262728
011
012
013
NC
NC - No internal connection
Copyright © 1983, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-71
SN65518, SN75518
VACUUM FLUORESCENT DISPLAY DRIVERS
logic symbol t
CMOS/VAC
FLUOROISP
CLOCK (211
OATA IN (39)
I>
I>
3
3
20
20
I>
I>
3
3
20
20
I>
I>
3
3
20
20
••
•
(38) 01
(37) Q2
•
·•
·•• ·•• ·
c
(ii'
't:I
iii
-<
...C
~'
123) 016
(18) 017
iil
(4)031
(3)032
(2) SERIAL
OUT
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the N package.
logic diagram (positive logic)
STROBE--~:>----------------,
LATCH - - - - - - - - - - - ,
ENABLE
SHIFT
REGISTER
OATAIN
CLOCK"""--i>-
3-72
TEXAS ."
INsTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75266
SN65518, SN75518
VACUUM FLUORESCENT DISPLAY DRIVERS
FUNCTION TABLE
CONTROL INPUTS
FUNCTION
LOAD
LATCH
STROBE
LATCHES
Rl THRU R32
LCl THRU LC32
OUTPUTS
SERIAL
01 THRU 032
ENABLE
STROBE
t
X
X
X
X
X
X
As determined above Stored data
R32
Determined by Strobe
As determined above New data
R32
Determined by Strobe
H
As determined above Determined by Latch Enable
R32
AIIL
L
As determined above Determined by Latch Enable §
R32
LCl thru LC32, respectively
Not
LATCH
SHIFT REGISTER
CLOCK
X
X
X
X
L
H·
X
X
Load and shift*
Determined by latch Enable§
R32
Determined by Strobe
No change
Determined by Latch Enable §
R32
Determined by Strobe
H = high level, L = low level, X = irrelevant, t = low-to-high-Ievel transition.
• R32 and the serial output take on the state of R3l. R31 takes on the state of R30, ... R2 takes on the state of R1, and R t takes on
the state of the data input.
§New datB enter the latches while Latch Enable is high. These data are stored while latch Ena~le is low.
•
I!!
CD
>
";:
Q
typical operating sequence
CLOCK
DATA IN
SRCONTENTS
>-
«I
unununUnL ••• JlJUUlJ1J
Q.
/I)
Q
~
VALID
IRRELEVANT
INVALID
VALID
LATCH ENABLE ______________________________~r-lL
______________________
LATCH
PREVIOUSLY STORED DATA
NEW DATA VALID
CONTENTS ____________________________________
L-________________________
__
STROBE
o OUTPUTS
________________________________________L-_V_A_L_ID__L-______________
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-73
SN65518, SN75518
VACUUM FLUORESCENT DISPLAY DRIVERS
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT
VCC1--------~----_._t~--
TYPICAL OF ALL Q OUTPUTS
- - - - - - - - _ t - - - - - VCC2
INPUT--......,.,.,........
C
iii'
___ .--J
"C
m
-<
GNO--__----------e-e----
C
:::s,
~
Ul
...- - - - - OUTPUT
TYPICAL OF SERIAL OUTPUT
------'--_.----_t~'""""
VCC1
f-----~--OUTPUT
11
----------e-e---- GNO
--------e-e--------GNO
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage. VCCl (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 V
Supply voltage. VCC2 ........................... .,. . . . . . . . . . . . . . . . . . . . . . . . . .. 70 V
Input voltage. VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. VCCl
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1650 mW
FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 700 mW
Operating free-air temperature range: SN65518............ . . . . . . . . . . . . . .. - 40°C to 85 °c
SN75518 ............................. OoC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Case temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds: N package ............ 260o'C
NOTES:
3-74
1. Voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, derate the N package linearly at the rate of 13.2 mW/oC and the FN package
linearly at the rate of 13.6 mW/oC.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, T~XAS 76265
SN65518, SN15518
VACUUM FLUORESCENT DISPLAY DRIVERS
recommended operating conditions. T A
25 DC (unless otherwise noted)
MIN
MAX
Supply voltage, VCCl
4.5
15
V
Supply voltage, VCC2
0
60
V
VCCl - 4.5 V
VCel = 15 V
VCCl = 4.5 V
High-level input voltage, VIH (see Figure 11
Low-level input voltage, VIL (see Figure 11
VCCl
=
3.5
V
12
1
.
15 V
High-level output current, IOH
6
Low-level output current, IOL
VCCl
VCCl
Clock frequency, fclock (see Figure 21
VCCl
Pulse duration, clock high, tw(CKHI
= 10Vto
= 4.5 V
= 10Vto
Pulse duration, clock low, tw(CKLI
VCCl
= 4.5
Setup time, data before clockt, tsu
Hold time, data after clock!, th
2
mA
5
0
100
1
15V
V
VCCl = 4.5 V
SN65518
Operating free-air temperature, T A
mA
0
VCCl - 10Vto 15V
VCCl - 4.5 V
VCCl -10Vto15V
SN75518
V
-25
15V
VCCl - 4.5 V
VCCl -10Vto15V
UNIT
II
MHz
ns
500
100
ns
500
75
ns
150
75
150
ns
-40
85
0
70
·C
electrical characteristics over recommended ranges of operating free-air temperature and VCC1 (unless
otherwise noted). VCC2 = 60 V
.
PARAMETER
VIK
VOH
Input clamp voltage
High-level output voltage
VOL
Low-level output voltage
IIH
High-level input current
IlL
Low-level input current
ICCl
Supply current
ICC2
Supply current
Q outputs
Serial output
Q outputs
Serial output
I SN65518
SN65518,
SN75518
t All typical values are at T A
=
TEST CONDITIONS
11- -12 mA
IOH - -25 mA
VCCl = 5 V,
IOH = -20 ~A
IOL = 1 mA
IOL - 20 ~A
VI = 15 V
VCCl = 15 V,
VI - 0 V
VCCl - 15 V,
VCCl - 4.5 V
VCCl = 15 V
Outputs high,
TA = -40·C
Outputs high,
TA - O°Cto MAX
Outputs low
MIN
Typt
MAX
1.5
57.5
4.5
58
4.9
5
5
0.06
0.8
UNIT
V
V
V
0.1
1
~A
0.1
1
~
1.8
4
2
5
7
12
10
0.01
0.5
mA
mA
25 ·C.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-75
SN65518, SN75518
VACUUM FLUORESCENT DISPLAY DRIVERS
switc"lng characteristics, VCC2 - 60 V, CL - 50 pF, TA - 25°C (unless otherwise noted)
,PARAMETER
td
Delay time, Clock to data output
tDHL
Delay time, high-to-Iow-Ievel
a output
VCCI = 4.5 V
VCCI = 15 V
from latch enable
from strobe
from latch enable
from strobe
from latch enable
II
Delay time, low-to-high-Ievel
tDLH
from strobe
from latch enable
from strobe
a output
a output
Transition time, low-to-high-Ievel
tTLH
a output
MIN
VCCI = 15 V
VCCI = 4.5 V
VCCI = 15 V
MAX
See Figure 6
See Figure 5
600
150
1.5
1
0.5
0.5
1.5
See Figure 6
See Figure 5
See Figure 6
1
0.25
0.25
See Figure 5
See Figure 6
See Figure 5
VCCI = 4.5 V
VCCI - 4.5 V
VCCI = 16 V
VCCI = 4.5 V
VCCI = '16 V
Transition time, high-to-Iow-Ievel
tTHL
TEST CONDITIONS
CL=15pF,
See Figure 4
3
See Figure 6
1.5
2.5
0.75
See Figure 6
UNIT
ns
pS
pS
pS
pS
RECOMMENDED OPERATING CONDITIONS
INPUT VOLTAGE LOGIC-LEVEL LIMITS
vs
SUPPLY VOLTAGE VCC1
12
I
I
T A - Full Range
10
>
..I
8
~
5co.
6
I
4
~O/
/V
./
2
o
,. /'"
3
5
. , -J'\.o
~
7
9
I
N
:z:
:E
5
~
c
/
4
:;,
'/
V
......f
/
3
"0
(j
E
:;,
2
/
.!.
:E
11
13
15
o
4
Supply Voltage VCC1- V
V
V
6
8
10
12
Supply Voltage VCC1-V
FIGURE 1
3-76
I
T A - Full Range
....
~
.5
6
I
.:>~
1!'"
'>
V'
/'
-
MAXIMUM INPUT DATA RATE
vs
SUPPLY VOLTAGE VCC1
FIGURE 2
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TeXAS 75285
14
16
SN65518, SN75518
VACUUM FLUORESCENT DISPLAY DRIVERS
PARAMETER MEASUREMENT INFORMATION
/4--twICKHI~
I
lr-----~
I
CLOCK
60%
I
I
:
:
!.---twICKLI-----...!
VIL
*Zm:::
j4--t,u---.-- t h--+!
I
OA,."
I
<>
as
Q.
II)
is
SN55552 ... FP PACKAGE
(TOP VIEW)
NMq-l.!'ltOI""-OOOla ..... N
........................................ NNN
00000000000
6
5
4 3 2
14443424140
011 7
010 ~8
09 ~9
08 10
07 ~11
06 ~ 12
05J13
39
38
37
36
35(
34
33
J
~~14
023
024
025
026
027
028
029
~ O~
03~15
02 ~16
01 J17
1819 20
21.~
31 031
30 032
29[ NC
23~ 25262728
NC-No internal connection
t BIDFET - Bipolar, double-diffused, N-channel and P-channel MDS transistors on same chip -
specifications per the tarms, at Texas Instruments
=~~:=i~a{~:1~1i ~=::i:r
:.r;..e:::A::.s not
patented process.
Copyright © 1986, Texas Instruments Incorporated
PRODUCTIOI DATA documents contain information
current as of publication data. Products conform to
TEXAS •
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
3-79
SN55551. SN55552
ELECTROLUMINESCENT ROW DRIVER
logic symbols t
SN55551
SN55552
CMOSIEL OISP
SUBSTRATE (25)
COMMON
STROBE (271
CMOS/El DISP
SUBSTRATE
[0 SOURCE SUPPLY)
COMMON
~ 10 SOURCE SUPPLY]
STROBE ~ V3
(23)
ENABLE
G2
-
SRG 32
CLOCK
(28)
"l
DATA IN '-'----- 10
(30) 01
2.3
~ >C11-
t>
2.3
C
iii"
2.3
'C
iii"
2.3
<
...C<"
CD
...
til
2.3
2.3
2.3
(311 02
t>
t>
~
~
t>
t>
~
~
:"
(441 015
(11 016
:"
2.3
2.3
r
~~ 01
~~ 02
t>
t>
~~ 017
~~ 018
t>
t>
o~ 031
"
"
"
(16) 0;'
(171 032
t>
t>
:
2.3
2.3
(1BI SERIAL OUT
t These symbols are in accordance with ANS)/[EEE Std 91-1984 and [EC Publication 617-12. The symbol
open-drain output,
Q
Q~ 032
~ SERIAL OUT
here indicates an n-channel
logic diagram (positive logic)
SUBSTRATE ______________________________________________--,
COMMON
STROBE--------------------~
ENABLE-------------------,
DATA
f--I----
Q1
IN ---------I
CLOCK----.---~>
f--I---- Q2
1---+-Q31
Q32
~-----------
3-80
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SERIAL OUT
SN55551. SN55552
ELECTROLUMINESCENT ROW DRIVER
FUNCTION TABLE
CONTROL INPUTS
FUNCTION
CLOCK ENABLE
•
ENABLE
X
X
X
X
L
H
STROBE
X
X
LOAD
No .•
OUTPUTS
SHIFT REGISTERS
R1 THRU R32
STROBE
01 THRU 032
SERIAL
X
Load and Shift t
R32
X
H
No Change
R32
Determined by Enable and Strobe
Determined by Enable and Strobe
As determined above
R32
All 0 outputs off
H
As determined above
R32
Determined by RI through R32
L
As determined above
R32
All 0 outputs on
H = high level, l = low level, X = irrelevant. ! = high-ta-Iow transition.
tRegister R32 takes on the state of R31. R31 takes on the state of R30, ... R2 takes on the state of RI, and RI takes on the state of
the data input.
•
~
CD
typical operating sequence
>
u
CLOCK
U_____________ _
VIH
----- --- ----- -.
-JnL___"'n ----------
DATA IN _ _ _ _~n----
SN55551 ENABLE _ _ _ _ _
SN55552 ENABLE
STROBE
";::
Q
________~Il~__~!l------lL-__
I
..J
COMPOSITE ROW
I
... J [
DRIVE APPLIED TO
SUBSTRATE COMMON
>-
«I
SUBSTRATE COMMON
Q.
II)
VIH
Q
SUBSTRATE COMMON
VIH
SUBSTRATE COMMON
VIH
SUBSTRATE COMMON
IfIH
SUBSTRATE COMMON
+HV
OV
lIEu
II'~
.,':::: II ~ ~u_::~':~u-'H;:
- - - - - - - -HV
.,'~~=r"QA\L_~_~~::
SN55551
02 OUTPUT
II
-+HV
OUTPUT FLOATS
"I•....::;::..:..:~....:...:=:.:.::.......I
OUTPUT FLOATS
III
~
U___________
OUTPUT
-HV
~
~U:::TvOltage ..!:,,~=~~~~====~tI!.., ~ _________
SN55552
::
II
II
__ uu_ ~
OUTPUT FLOATS
- - +HV
FLOATS
HV
NOTE: During operation Clock, Data In, Enable, and Strobe are referenced to the Composite Row Drive signal received at the Substrate
Common pin of the device.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-81
SN55551, SN55552
ELECTROLUMINESCENT ROW DRIVER
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL Q OUTPUTS
VCC
__ ---.J
'N'o_. . .
II
TYPICAL OF SERIAL OUTPUT
.-----1- OUTPUT
VCC-----.---.-.--
INPUT _ ......
....--+- OUTPUT
c
fij"
"C
iii
SUBSTRATE COMMON
-<
.
..
....---~HH...
_ _ _........_ ......-4_SUBSTRATE
COMMON
______............___...... SUBSTRATE
COMMON
C
<"
CD
absolute maximum ratings oVl:lr operating temperature range (unless otherwise noted)
(I)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 18 V
Q off-state output voltage, VO(offl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 225 V
Input voltage ........................................................ VCC+0.3 V
Substrate common terminal current (see Note 2) .................................. 1.5 A
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 3) . . . . . .. 1825 mW
Minimum operating free-air temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C
Operating case temperature . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 125°C
Storage temperature range .......................................... - 65°C to 150°C
Case temperature for 60 seconds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
NOTES:
1. Voltage values are with respect to substrate common terminal.
2. Duty cycle is limited by package dissipation.
3. For operation above 25 °C
free~air
temperature, derate linearly at the rate of 14.6 mW/oC.
recommended operating conditions
MIN
NOM
MAX
10.8
12
15
V
0
200
V
HighMlevel input voltage
O.75VCC
VCC+O.3
V
VIL
Low-level input voltage
0.3
O.25VCC
V
1010n)
On-state
Vee
Supply voltage
VOloff)
VIH
Off-state Q output voltage
Vee - 10.8 V,
Q
output current
VDD = 80 V,
Duty cycle :s 1 %
Te
3-82
50
= 25°e
rnA
Vee - 15V,
Te
UNIT
80
= 25°e
fclock
tw
Clock frequency, TA - 25°e
Clock pulse duration, high or low, TA - 25°e
80
ns
tsu
th
Setup time, data valid before clock!, TA - 25°e
20
ns
Hold time, data valid after clock!. T A - 25°e
110
ns
TA
Operating free-air temperature
-55
°e
Te
Operating case temperature
6.25
125
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
MHz
°e
SN55551, SN55552
ELECTROLUMINESCENT ROW DRIVER
electrical characteristics over recommended operating temperature range.
common at 0 V
PARAMETER
TEST CONDITIONS
I Serial outputs
I Q outputs
10 - -100 ~A
10 = 50 rnA
VOH
High-level output voltage
VOL
Low-level output voltage
IIH
High-level input current
VI - 12 V
I Serial output
IlL
Low-level input current
VI = 0
Off-state Q output current
Va = 200 V
ICC
Supply current
Vee -
12
V. Te -
25
0
12 V. substrate
MAX
10
UNIT
V
50
1.5
5
-5
50
500
V
~A
~A
~A
~A
e
TEST CONDITIONS
PARAMETER
MIN
10=100~A
1010ffi
switching characteristics.
Vee
tdLH
Delay time, clocU to serial!
CL = 45 pF to common,
tdHL
Delay time, clock! to serialt
See Figure 1
MIN
MAX
UNIT
200
200
ns
500
ns
II
ns
VDD - 100 V, RL - 2 k!l,
tdHL
Delay time, enable to
Q
output!
CL = 45 pF to common,
See Figure 1
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
3-83
SN55551. SN55552
ELECTROLUMINESCENT ROW DRIVER
PARAMETER MEASUREMENT INFORMATION
+
VDD. ::0.V2kO
•
Q OUTPUTS
SERIAL OUT ---1..---TEST POINT
TEST POINT
TCL.45PF
r C L .. 45PF
...SERIAL OUTPUT LOAD CIRCUIT
Q OUTPUT LOAD CIRCUIT
Iflt----tw---~.I
CLOCK
I
50%1
50%f
~
M r ' - - - - tw
---
. " . - - - ' VIH
50%T
'\... _ _ _ _ _~~----J_
'1
-t
t h - -......
VIL
\.- tau---+!
I
----------_I_--------~I_------VIH
DATA IN
50%1
..
I VALID
I
I. '--- - - - - -
VIL
j414--- tclHL,----...1
"X
I
WAVEFORM 1 Ca•• Not. AI
I
%-
90
---VOH
I.
VOL
I
VOH
...
~--tclLH--........1
SERIAL OUT
--------...;..--...;.------------+;.. - - - -WAVEFORM 2
ENABLE
C•••
Not. BI
:/'0%
50%~
VOL
VIH
-------------------1+-~tclCOn)------.I
-- - - ---- -
VIL
{-;----VOH
_,0%
Q OUTPUTS
Ca.. Nota C)
----VOL
VOLTAGE WAVEFORMS
NOTES: A. Waveform 1 is for internal conditions such that a low is clocked into R32.
B. Waveform 2 is for internal conditions such that a high is clocked into A32,
C. To measure !dConl' a high is stored In the associated register.
FIGURE 1. SWITCHING CHARACTERISTICS
3-84
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 866012'. DALLAS. TeXAS 75285
SN55551, SN55552
ELECTROLUMINESCENT ROW DRIVER
RECOMMENDED OPERATING CONDITIONS
MAXIMUM ON-STATE Q OUTPUT CURRENT
vs
SUPPLY VOLTAGE
1I
80
Duty Cycle s 1%
TA - 25°C
1:
~..
75
t
o
70
a
65
~
60
i•
/
I
~
I
V
55
/
50
10
V
/
/
/
•
/
11
15
14
13
12
vee-Supply Voltage-V
FIGURE 2
TYPICAL CHARACTERISTICS
OUTPUT CHARACTERISTICS SHOWING
SAFE OPERATION AREA (SOA)
110
1I
100
1
1
a
ic5
I
SO~
4
~ vJe -'12 VI'·
/
80
V
70
Vee - 10.8 V
40
~
=
\
SO~~
,f
50
(.)
i
0
I
30
20
10
120
1I
.....
/V/
V;
60
9
vs
JUNCTION TEMPERATURE
Duty Cycle s 1 %
Te - 25°C
Vee- 15V \
90
!
OUTPUT SATURATION CURRENT
100
r---..
80
r-.....
...................
Vee - 15 V
r----::.: . . . . .
.............
60
---- r---
...............
----
Vee - 10.8 V
r-I'-
40
9
20
o
ow
o
40
~
~
1001W1401~
-75 -50 -25
0
25
50
75
100 125
TJ-Junctlon Temparature- °e
Yo-Output Voltage-V
FIGURE 3
FIGURE 4
TEXAS
,If
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75285
3-85
II
C
iii'
iii'
"0
-<
..c<'
CD
Cil
3-86
SN65551, SN65552, SN75551, SN75552
ELECTROLUMINESCENT ROW DRIVER
MARCH 1983-REVISED SEPTEMBER 1986
N
DUAL·IN-LiNE-PACKAGES
•
Each Device Drives 32 Electrodes
•
High-Voltage Open-Drain DMOS Outputs
•
50-mA Output Current Capability
•
CMOS-Compatible Inputs
•
Very low Steady-State Power Consumption
(TOP VIEW)
SN65551. SN75551
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
032
description
The SN65551, SN65552, SN75551, and
SN75552 are monolithic BIDFETt integrated
circuits designed to drive the row electrodes of
an electroluminescent display. All inputs are
CMOS-compatible and all outputs are highvoltage open-drain DMOS transistors. The
SN75552 output sequence has been reversed
from the SN75551 for ease in printed circuit
board layout.
The devices consist of a 32-bit shift register, 32
AND gates, and 32 output OR gates. Typically,
a composite row drive signal is externally
generated by a high-voltage switching circuit and
applied to the Substrate Common terminal. Serial
data is entered into the shift register on the highto-low transition of the clock input. A high Enable
input allows those outputs with a high in their
associated register to be turned on causing the
corresponding row to be connected to the
composite row drive signal. When the Strobe
input is low, all output transistors are turned on.
The Serial Data output from the shift register
may be used to cascade additional devices. This
output is not affected by the Enable or Strobe
inputs.
SERIAL OUT
ENABLE
CLOCK
015
014
013
012
011
010
09
08
07
06
05
04
03
02
01
•
.
!II
CD
>
.~
Q
>CO
Q.
!II
is
NC
DATA IN
STROBE
VCC
SUBSTRATE
COMMON
SN65552. SN75552
017
016
015
014
013
012
011
010
09
08
07
06
05
04
03
02
01
The SN65551 and SN65552 are characterized
for operation from -40°C to 85°C. The
SN75551 and SN75552 are characterized for
operation from O°C to 70°C.
SERIAL OUT
ENABLE
CLOCK
018
019
020
021
022
023
024
025
026
027
028
029
030
031
032
NC
DATA IN
STROBE
VCC
SUBSTRATE
COMMON
NC - No internal connection
t BIDFET
- Bipolar. double-diffused, N-channel and P-channel MOS transistors on same chip - patented process.
PRODUCTION DATA ....um••ts contain infermatiDn
currant as of publication date. Preducts conform to
opacifi.atio.. por lb. tarms of T.... Instrum.nts
:==ir,.I:I~'l.; =~:i:l' :I:":=~~:~ not
Copyright © 1983, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
3-87
SN65551, SN6555t SN75551, SN75552
ELECTROLUMINESCENT ROW DRIVER
SN65552. SN75552 ... FN PACKAGE
(TOP VIEW)
SN65551. SN75551 ... FN PACKAGE
(TOP VIEW)
('.IN
________ _
.-OCDOO,",COLnV('l')N.-
NM..;tLnco,",como_C"II
_ _ _ _ _ _ ......... NNN
ddddddddddd
dddddddd.ddd
6 5 4 3 2
39
8
38
37
9
II
10
7
39
8
38
9
37
08
10
36
11
35
12
34
36
35
12
34
07
06
13
33
05
13
33
14
34
04
15
31
03
14
15
34
31
031
16
30
02
16
30
032
17
29
1819202122232425262728
01
17
29
1819202122232425262728
'0
'<
C
011
11
C
iii'
iii'
6 5 4 3 2 1 4443424140
1 44 43 42 41 40
7
:::!,
<
CD
;;
NC-No internal connection
logic symbols t
SN65551.SN75551
SN65552.SN75552
CMOS/EL DISP
SUBSTRATE 121)
COMMON
STROBE (23)
CMOS/EL DISP
(~ SOURCE SUPPLV)
2.3
2.3
2.3
2.3
2.3
2.3
(~ SOURCE SUPPL VI
t>
t>
Q
(26) 01
t>
t>
Q
Q
140)
t>
t>
~
16) 031
(17) 032
Q
(27) 02
0~5
.
11) 016
,
11S) SERIAL OUT
,
2.3
2.3
t>
t>
Q
Q
(27) 031
126) 032
118) SERIAL OUT
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12. The·symbolQ here indicates an n-channel
open~drain output.
Pin numbers shown are for N package.
3-88
TEXAS . .
INSTRUME~TS
POST OFFICE BOX 866012 • DALL-AS, TEXAS 715266
SN65551, SN6555t SN75551, SN75552
ELECTROLUMINESCENT ROW DRIVER
logic diagram (positive logic)
SUBSTRATE ________________________________________- - ,
COMMON
----------01
STROBE - .
ENABLE - - - - - - - - - - - - - - - ,
•
DATA IN -------f
CLOCK -----<~-<:p.
~
~
';:
Q
>
ca
is.
til
i5
FUNCTION TABLE
CONTROL INPUTS
FUNCTION
LOAO
ENABLE
STROBE
OUTPUTS
SHIFT REGISTERS
R1 THRU R32
Q1 THRU Q32
CLOCK
ENABLE
STROBE
j
X
X
X
X
Load and Shift t
R32
No Change
R32
Determined by Enable and Strobe
L
H
As determined above
R32
All Q outputs off
H
H
As determined above
R32
Determined by Rl through R32
X
L
As determined above
R32
All Q outputs on
No. j
X
X
X
SERIAL
Determined by Enable and Strobe
H = high level, L ::::: Low level, X = irrelevant; ! = high-ta-Iow transition.
tRegister R32 takes on the state of R31, R31 takes on the state of R30, ... R2 takes on the state of R1, and R1 takes on the state of
the data input.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
a-89
SN65551. SN65552. SN75551. SN75552
ELECTROLUMINESCENT ROW DRIVER
typical operating sequence
U
CLOCK
U_____________ _
VIH
DATAIN _ _ _ _~n----
----- ---- ---- -.
JnL-.__ n ---------.In. .___.Jn - ------
SN75551 ENABLE _ _ _ _ _ _
-J
SN75552 ENABLE _ _ _ _ _ _ _ _ _
C
fii'
STROBE
iii'
COMPOSITE ROW
DRIVE APPLIED TO
SUBSTRATE COMMON
"CS
-<
C
1. .___
SUBSTRATE COMMON
VIH
SUBSTRATE COMMON
VIH
SUBSTRATE COMMON
VIH
SUBSTRATE COMMON
.J
SUBSTRATE COMMON
II--+
... J
L
HV
DV
:::!.
<
til
- - - - - - - -HV
CD
n~s~
:.:.rr ~
SN75552
01 OUTPUT
SN75551
02 OUTPUT
n
n
SN75552
02 OUTPUT
~___ ~~:~ ___.~ _____~
I
I[+HV
l
U_________ :I_____
-+HV
OUTPUT FLOATS
14
14
-I
OUTPUT FLOATS
OUTPUT FLOATS
_I
-HV
I[+HV
uI44:-U-:_~_T_~_L~_A_~_S~_ _ _ _ _ _ -HV
OUTPUT FLOATS
- -
HV = high voltage
__ -
____ -HV
NOTE: During operation Clock, Data In, Enable, and Strobe are referenaed to the Composite Row Drive signal received at the Substrate
Common pin of the device.
3-90
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
SN65551, SN6555t SN75551, SN75552
ELECTROLUMINESCENT ROW DRIVER
schematic of inputs and outputs
TYPICAL OF SERIAL OUTPUT
TYPICAL OF ALL Q OUTPUTS
EQUIVALENT OF EACH INPUT
....---+- OUTPUT
Vec -----
III
is.
en
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
C
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 18 V
Q off-state output voltage, VO(off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 225 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. VCC + 0.3 V
Substrate common terminal current (see Note 2) .................................. 1.5 A
Continuous total dissipation at (or below) 25°C free-air temperature
(see Note 3): FN package ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1700 mW
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1250 mW
Operating free-air temperature range: SN65551, SN65552 .................. -40°C to 85°C
SN75551, SN75552 . '" ., ............... ooC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 260°C
NOTES:
1. Voltage values are with respect to substrate common terminal.
2. Duty cycle is limited by package dissipation.
3. For operation above 25°C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the N package, use
the 10.0·mW/oe curve lor these devices.
recommended operating conditions
vee
Supply voltage
VIH
High·level input voltage (see Figure 1)
VIL
Low-level input voltage (see Figure 1)
VO(otf)
Off-state Q output voltage
Vee
Vee
Vee
Vee
1 %,
10 (on)
On-state output current, duty cycle
(see Figures 2, 3, and 4)
10K
Output clamp current
Iclock
Clock frequency
tw
Pulse duration, clock high or low
tsu
Setup time, data belore clock (see Figure 3)
th
Hold time, data alter clock (see Figure 3)
TA
Operating free-air temperature
::$;
I
I
Vee
Vee
=
=
=
=
=
=
10.8 V
15 V
MIN
NOM
MAX
10.8
12
15
8.1
11.1
11.25
15.3
10.8 V
-0.3
2.7
15V
-0.3
3.75
0
200
10.8
v,
15V,
TA - 25°e
TA
=
50
25°e
80
0
TEXAS •
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TeXAS 75265
V
V
V
V
mA
-45
mA
4
MHz
125
ISN65551, SN65552
I SN75551, SN75552
UNIT
ns
50
ns
100
ns
-40
85
0
70
°e
3-91
SN65551, SN65552, SN75551, SN75552
ELECTROLUMINESCENT ROW DRIVER
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
= 200 V
10 = -100 pA
10L = 50 mA. See
10L = 100p.A
Off-state Q output current
MIN
MAX
Va
1010ff)
VOH
'High-level output voltage
VOL
Low-level output voltage
IIH
Highwlevel input current
VI@Vee
IlL
low-level input current
VI - 0
ICC
Supply current from Vee
.LSerial outputs
L Q outputs
I Serial output
UNIT
10
pA
VCC-1.5
V
Figure 3
30
V
1
1
-1
pA
pA
250
pA
MAX
UNIT
200
ns
200
ns
500
ns
switching characteristics. VCC - 12 V. TA == 25°C
PARAMETER
TEST CONDITIONS
MIN
Propagation delay time. high-to-Iow
tpHL
level serial output from clock
eL
Propagation delay time. low-to-high
tPLH
=
20 pF to ground. See Figure 7
level serial output from clock
Turn-on delay time. Q outputs
tdlon)
10L - 50 mA. Strobe at Vee.
RL = 1.4 kll to 100 V. See Figure 7
from enable
RECOMMENDED OPERATING CONDITIONS
MAXIMUM ON-STATE Q OUTPUT CURRENT
INPUT VOLTAGE LOGIC-LEVEL LIMITS
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
12
TA = Full Range
10
>I
i
j
...
"c
j'
>
8
J--- ~
J---
MinimumVIH
80
«
E
...c
75
3;
70
I
Duty Cycle';;; 1 %
TA = 25°C
!
"
0
0
4
~
60
E
E
55
65
l!
c
0
Maximum VIL
"
2
o
10
'x
~
11
12
13
14
15
50
10
vee-Supply Voltage-V
/
/
.IV
11
12
13
14
vee-Supply Voltage-V
FIGURE 1
FIGURE 2
TEXAS •
INSTRUMENTS
POST OFFICI; BOX 665012 • DALLAS, TEXAS 75265
/
/
a
Q,
3-92
/
56
/
15
SN65551. SN65552. SN75551. SN75552
ELECTROLUMINESCENT ROW DRIVER
TYPICAL CHARACTERISTICS
ON-STATE Q OUTPUT CURRENT
vs
OUTPUT VOLTAGE
OUTPUT SATURAnON CURRENT
vs
FREE-AIR TEMPERATUREt
110
110
-
NC
CO
Q.
en
Q
SN55554 ... FD PACKAGE
(TOP VIEW)
.....
..... ('W)t"\I
Nomoo,....cotn
N - - _ ...............
_ _ .....
_
00000000000
The SN55553 and SN55554 are characterized
for operation over the full military temperature
range of - 55°C to 125°C.
6
5 4 3 2 1 44 43 42 41 40
7
H
8
9
10
11
12
13
38
37
36
35
34
33
14
32
15
31
16
30
17
29
1819202122 232425262728
illO
09
08
07
06
05
04
03
02
01
NC
I-UUU~C"'ujZ~
::JZZZUZU Ual -
al
iX
I::J
OU>«««
-'
zl- z
U
w~w
o-'
«
:c
U
W
~
en
-'
1=
::J
o
NC-No internal connection
tBIDFET - Bipolar, double-diffused, N-channel and P-channel MOS transistors on same chip - patented process.
PRODUCTION DATA docum.ntl •••tain informltio.
.ur""t •• of pu.licltio. d.ta. Products conl.nn to
.p.cificationl plr the tarlll 01 T.... In.trum.nts
m.d.... wlrrlnty. Production pr.....ing d... not
.......ril' i.cludo tastin••1 III plr.mllars.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
Copyright
© 1986, Texas Instruments Incorporated
3-95
SN55553. SN55554
ELECTROLUMINESCENT COLUMN DRIVERS
logic symbols t
SN55553
SN55554
CMOS/EL OISP
CMOS/EL OISP
OUTPUT ENABLE 1211) EN3
OUTPUT ENABLE (28) EN3
LATCH ENABLE (26) C2
LATCH ENABLE (26) C2
CLOCK(22)
t--'----,..---:-[>-3-i('i<1l 015
t----i~~---::3-i (1) 016
1--=--.-:::-7---::3:-1(;6) 031
1-----t-::7--::3-i1(17) 032
'-""'-"'---''-1(18) SERIAL OUT
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OUTPUTENABLE-------------------------,
LATCH ENABLE-------------------,
Rl
CLOCK
01
32·BIT
STATIC
SHIFT
REGISTER
DATA IN
R2
32
LATCHES
02
R31
031
R32
032
>----- SERIAL DATA OUT
3-96
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN55553, SN55554
ELECTROLUMINESCENT COLUMN DRIVERS
FUNCTION TABLE
CONTROL INPUTS
FUNCTION
LOAD
ENABLE
LC1 THRU LC32
SERIAL
Load and shift t
Determined by
R32
Determined by
No change
R32
Output Enable
As determined above
Latch Enable'
Stored data
R32
Determined by
As determined above
New data
R32
Output Enable
L
As determined above
Determined by
R32
All L
H
As determined above
Latch Enable'
R32
LCl thru LC32, respectively
ENABLE
t
X
X
H
X
X
X
X
X
X
X
X
X
X
OUTPUT
LATCHES
R1 THRU R32
OUTPUT
ENABLE
No!
LATCH
SHIFT REGISTER
LATCH
CLOCK
L
OUTPUTS
01 THRU 032
H = high level, L = low level, X = irrelevant, t = low-to-high-Ievel transition.
tR32 and the serial output take on the state of R31, R3l takes on the state of R30, ... R2 takes on the state of Rl, and R1 takes
on the state of the data input.
.
!II
CD
>
"C
Q
'New data enter the latches while Latch Enable is high. These data are stored while Latch Enable is low.
tvpical operating sequence
unununUnL•••
CLOCK - - ,
DATA IN
SR CONTENTS
LATCH ENABLE
•
nmuuu
VALID
IRRELEVANT
INVALID
VALID
______________________
LATCH CONTENTS
>
ca
C.
!II
Q
~Il~
______
~-------
NEW DATA VALID
PREVIOUSLY STORED DATA
OUTPUT ENABLE
_- L_ _ _ _ _ _ _ __ _
Q OUTPUTS ____________________________L -_
VALID
schematic of inputs and outputs
EQUIVALENT Of EACH INPUT
TYPICAL Of ALL Q OUTPUTS
VCC1------~e-----..._.---
--------e---~_.--VCC2
INPUT
-e-"IV,-e-.
GND--__- - - - - - - -...---4~·
TYPICAL Of SERIAL OUTPUT
- - - - - - - -...- - - - - - - VCCI
OUTPUT
- -.....>----4...............-
GND
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
....- - - -.....-
...-------4-
------~
dUTPUT
GND
3-97
SN55553, SN55554
ELECTROLUMINESCENT COLUMN DRIVERS
absolute maximum ratings over operating temperature range (unless otherwise noted)
Supply voltage, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 18 V
Supply voltage, VCC2 ...................................................... 70 V
Input voltage .................. ' ................................... VCC1 + 0.3 V
Ground current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 700 rnA
Continuous total dissipation at (or below) 25 DC free-air temperature (see Note 2) . . . . . .. 1825 mW
Minimum operating free-air temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 DC
Operating case temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 125 DC
Storage temperature range ......................................... - 65 DC to 150 DC
Case temperature for 60 seconds ................. '. . . . . . . . . . . . . . . . . . . . . . . . . . .. 260 DC
c
NOTES:
iir
1. Voltage values are with respect to network ground terminal.
2. For operation above 25°C free·air temperature. derate linearly at the rate of 14.6 mW/oC.
)
'C
iii
-<
recommended operating conditions
C
MIN
NOM
MAX
UNIT
10.B
12
13.2
V
60
V
::::!.
VCCl
Supply voltage
CD
VCC2
Supply voltage
VIH
VIL
High·level input voltage
Low-level input voltage
10H
High-level output current
~15
mA
IOL
Low-level output current
15
mA
<
til
0
0.75VCC
VCC+0.3
~0.3
0.25VCC.
V
10K
Peak output clamp diode current
±20
mA
fclock
Clock frequency, TA = 25°C
6.25
MHz
tw(CLK)
tw(LE)
Clock pulse duration, high or low, TA = 25°C
Latch enable pulse duration, T A
~
BO
25°C
ns
BO
Setup time, data valid before clock;, T A = 25°C
tsu
th
Hold time, data valid after clock;, TA = 25°C
TA
Operating free-air temperature
TC
Operating case temperature
20
ns
110
ns
~55
125
electrical characteristics over recommended operating temperature range, VCC1 .. 12 V,
VCC2 = 60 V
TEST CONDITIONS
PARAMETER
VOH
3-98
High·level output voltage
~15
Q outputs
10 =
Serial output
10
Q outputs
10 = 15 mA
10 = lOOI'A
~
~100
VOL
Low-level output voltage
IIH
High-level input current
VI = 12 V
IlL
Low-level input current
VI = 0
ICCl
Supply current, VCCl
ICC2
Supply current, VCC2
Serial output
mA
I'A
MIN
MAX
55
V
10
10
1.5
5
~5
7
Outputs high
Outputs low
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
UNIT
20
2
V
I'A
I'A
mA
mA
SN55553, SN55554
ELECTROLUMINESCENT COLUMN DRIVERS
switching characteristics. VCC1 = 12 V. VCC2 - 60 V. TC .. 25°C
PARAMETER
Delay time, clockt to serialt
tdLH
TEST CONDITIONS
Delay time, clockt to serial.
Delay time, LE to Q outputt
Delay time, LE to Q outpud
tdHL
tdLH
tdHL
MIN
CL = 45 pF to ground,
See Figures 1 and 2
CL - 45 pF to ground,
See Figures 1 and 3
MAX
200
UNIT
ns
200
1000
ns
ns
500
ns
PARAMETER MEASUREMENT INFORMATION
OUTPUT
---1"'---
TEST POINT
~Cl- 45pF
FIGURE 1. OUTPUT LOAD CIRCUIT
1f~---tWIClK)---~~1
ClOCK~
50%1
1f~---tWICLK)----I~"14.---th---1
jt-tsu~
I
DATA IN --------50-%...,*\._ _ _...;.I_v_A_lI_D_ _ _ _
I
j 4 - - - tdHl
.Jlr-------::~
---.l_1
:JL,-: - - - - - - VOH
SERIAL OUT WAVEFORM 1
",90%
(see Nota A)
'-----VOl
I t - - - - t d L H - -...
~
.£1
SERIAL OUT WAVEFORM 2
Isee Note B)
VOH
10%
----------------------
-
- - - - - VOL
FIGURE 2. VOLTAGE WAVEFORMS FOR SERIAL OUTPUT
, -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ VIH
-JI ____________________
OUTPUT ENABLE _ _ _ _ _
LATCH ENABLE
~
.1"
_ _ _ _ _ _ _ _ _ _ _ _ _ _J.
14
..
-
-- -
OUTPUT Isee Note C)
l
----------------7-----,
I
1
Q
OUTPUT Isee Note DJ _ _ _ _--oJ/
I
-VIH
VIL
twlLE)
I+--tdlH---i
Q
VIL
VOH
10%
----VOL
~O%---VOH
~tdHL---.!
VOL
FIGURE 3. VOLTAGE WAVEFORMS FOR Q OUTPUTS
NOTES: A. Waveform 1 is for internal conditions such that a low is clocked into R32.
B. Waveform 2 is for internal conditions such that a high is clocked into R32.
C, To measure 'dLH, initially a low is stored in the latch and a high is stored in the shift register.
D. To measure tdHL, initially a high is stored in the latch and a low is stored in the shift register.
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75266
3-99
o
iii'
'CI
iii
-<
o
:I,
..
<
CD
UI
3-100
SN65553, SN65554, SN75553, SN75554
ELECTROLUMINESCENT COLUMN DRIVERS
02744. MARCH 1983-REVISEO SEPTEMBER 1986
•
Each Device Drives 32 Electrodes
•
60-V Output Voltage Swing Capability
•
15-mA Output Source and Sink Current
Capability
•
High-Speed Serially-Shifted Data Input
•
Totem-Pole Outputs
•
Latches on All Driver Outputs
N
DUAL-IN-LiNE PLASTIC PACKAGE
(TOPVIEWI
SN65553,SN75553
017
016
015
014
013
012
011
010
09
08
07
06
05
04
03
Q2
01
SERIAL OUT
CLOCK
GND
description
The SN65553, SN65554, SN75553. and
SN75554 are monolithic BIDFETt integrated
circuits designed to drive the column electrodes
of an electroluminescent display. The SN65554
and SN75554 output sequence has been
reversed from the SN65553 and SN75553 for
ease in printed circuit board layout.
The devices consist of a 32-bit shift register, 32
latches. and 32 output AND gates. Serial data
is entered into the shift register on the low-tohigh transition of the clock input. When high, the
Latch Enable input transfers the shift register
contents to the outputs of the 32 latches. When
Output Enable is high, all Q outputs are enabled.
Serial data output from the shift register may be
used to cascade shift registers. This output is not
affected by the Latch Enable or Output Enable
018
019
020
021
022
023
024
025
026
027
•
..
fI)
Q)
.~
028
029
030
03.1
032
OUTPUT ENABLE
DATA IN
LATCH ENABLE
Q
>
ftI
'a
fI)
is
VCCl
VCC2
FN PLASTIC CHIP CARRIER PACKAGE
(TOPVIEWI
SN65553.SN75553
- _ _ _ _ _ _ NNN
NMVInCOr--.C:Oo)O_N
00000000000
inputs~
6 5 4 3 2 1 4443424140
The SN65553 and SN65554 are characterized
for operation from -40°C to 85°C. The
SN75553 and SN75554 are characterized for
operation from ooe to 70°C.
on
7
8
01
37
10
36
11
35
12
34
13
33
14
32
15
31
30
16
29
17
1819202122232425262728
024
025
026
0~7
028
Q29
030
031
032
NC
NC-No internal connection
tBIDFET - Bipolar, double-diffused. N-channel and P-channel MOS transistors on same chip - patented process.
PRODUCTIOI DATA doc.montscDnlal. information
.arrent I. of p••,icatl•• data. P..ducts confDrm tD
.poeificationl psr the IIrm. of TII8I Instramonts
=~I~·1=7i =:':l' r.:=~n:.::" not
Copyright @ 1986, Texas Instruments Incorporated
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
3-101
SN65553, SN65554, SN75553, SN75554
ELECTROLUIUIINESCENT COLUMN DRIVERS
N
DUAL-IN-LiNE PLASTIC PACKAGE
FN PLASTIC CHIP CARRIER PACKAGE
(TOPVIEWI
NN SN65554.SN75554
________ _
_00)00 ['0 CO Lf) q-MN..-
ITOPVIEWI
, SN655!14. SN75554
016
017
018
019
020
021
022
023
024
025
S2
tn
"C
i'
015
014
0,13
012
011
010
09
08
07
06
05
04
03
02
01
OUTPUT ENABLE
DATA IN
LATCH ENABLE
VCC1
VCC2
026
027
028
029
030
031
032
SERIAL OUT
CLOCK
GND
'<
C
:I.
<
...
(II
tn
00000000000
6
027
543 2
1 4443424140
7
39
8
9
38
37
10
36
11
35
12
34
13
14
33
32
15
31
16
30
I-UUU~ON~WWW
Z
oO Z Z Z U
OCl
d
I-
o.
o
NC-No internal connection.
logic symbols t
SN65553. SN75553
SN65554. SN75554
CMOS/EL DISP
CMOS/EL DISP
OUTPUT ENABLE (251 EN3
OUTPUT ENABLE (25) EN3
LATCH ENABLE (23) C2
LATCH ENABLE (23) C2
CLOCK (19)
1-'-:"--''--~--:3-1'1i6) 031
1----1r-=~---::3-1(17l 032
'-""''-''''--'!..fIiI1B1S) SERIAL OUT
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for N packages.
3-102
TEXAS . "
INSTRUMENTS
POST OFfiCE BOX 655012 • DALLAS. TEXAS 75265
SN65553. SN65554. SN75553. SN75554
ELECTROLUMINESCENT COLUMN DRIVERS
logic diagram (positive logic)
OUTPUTENABLE----------------------------,
LATCH ENABLE - - - - - - - - - - - - - - - .
SHIFT
REGISTER
DATA IN
-------t
.....--11>
CLOCK -
•
...CD
!II
>
"i:
C
>
«I
Q.
!II
is
FUNCTION TABLE
CONTROL INPUTS
FUNCTION
LOAD
LATCH
OUTPUT
ENABLE
CLOCK
LATCH
OUTPUT
OUTPUTS
SHIFT REGISTER
LATCHES
R1 THRU R32
LC1 THRU LC32
SERIAL
R32
Determined "by
No change
Determined by
Latch Enable t
R32
Output Enable
As determined above
Stored data
R32
Determined by
As determined above
New data
Output Enable
All L
LC1 thru LC32, respectively
ENABLE
ENABLE
t
Not
X
X
X
X
X
X
L
H
X
X
X
X
X
X
L
As determined above
Determined by
R32
R32
H
As determined above
Latch Enable t
R32
Load and shift t
01 THRU 032
H = high level, L = low level, X = iirelevant, t = low-to-high-Ievel transition.
tR32 and the seriai output take on the state of R31, R31 takes on the state of R30 .... R2 takes on the state of R1, and R1 takes
on the state of the data input.
+New data enter the latches while latch Enable is high. These data are stored while Latch Enable is low.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS. TeXAS 75265
3-103
SN65553, SN65554, SN75553, SN75554
ELECTROLUMINESCENT COLUMN DRIVERS
typical operating sequence
CLOCK
Inn
u u unUnL ••• JlJlJ1J1JlJ
DATA IN
SRCONTENTS
VALID
IRRELEVANT
INVALID
VALID
LATCH ENABLE ______________________________~r_l~
c
______________________
~.
LATCH
CONTENTS ________P_R_EV_I_O_US_L_Y_S_T_O_RE_D_D_A_T_A________~_______
N_EW
__D_A_TA
__
V_A_Ll_D_______
iii
<
C
OUTPUT
ENABLE
::l.
ei
til
a OUTPUTS
------------------------------~
VALID
------------------------------~~--~~-----------
schematic of inputs and outputs
EaUIVALENT OF EACH INPUT
VCC1-------e~--~~~--
INPUT--.......,..,.............
GND--__
3-104
---~~
TYPICAL OF ALL
Q
OUTPUTS
-------e~-e~~
OUTPUT
____
TYPICAL OF SERIAL OUTPUT
VCC2
---e---e-e-e~~GND
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
VCC1
. . . . . - -...-
---_.....__e--....-
OUTPUT
GND
SN65553. SN65554. SN75553. SN75554
ELECTROLUMINESCENT COLUMN DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 18 V
Supply voltage, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 V
Input voltage ...................................................... VCC1 + 0.3 V
Ground current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 700 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2)
FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1700 mW
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250 mW
Operating free-air temperature range: SN65553, SN65554 ... . . . . . . . . . . . . . .. -40°C to 85°C
SN75553, SN75554 ..................... O°C to 70°C
Storage temperature range ................................. :....... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package. . . . . . . . . . . .. 260°C
Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
NOTES:
1. Voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the N package, use
the 1O.O-mWI °C curve tor these devices.
•
Supply voltage, VCC2
VCCI
High-level input voitage. VIH (see Figure 11
VCCI
VCCI
Low·level input voltage, VIL (see Figure 11
VCCI
=
=
=
=
10.8 V
15 V
MIN
NOM
10.8
12
MAX
UNIT
15
V
0
60
V
8.1
11. 1
11.25
15.3
10.8 V
-0.3
2.7
15 V
-0.3
3.75
V
V
High-level output current, IOH
-15
mA
Low-level output current, IOL
15
mA
Output clamp current, 10K
Clock frequency, f ciock
0
20
mA
6.25
MHz
Pulse duration, clock high or low, tw(CLKI (see Figure 21
80
ns
Pulse duration, latch enable, tw(LEI (see Figure 41
80
ns
Data setup time before clock i, tsu (see Figure 2)
20
ns
Data hold time after clock 1, th (see Figure 21
80
I SN65553, SN65554
I SN75553, SN75554
ns
-40
85
0
70
°C
electrical characteristics over recommended r.anges of VCC1 and operating free-air temperature,
VCC2 = 60 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
VOL
Low~level
IIH
High·level input current
= -15 mA
10 = -100 pA
10L = 15 mA
10L = 100 pA
VI = VCCI
Low~level
VI - 0
'1iL
>
as
III
Supply voltage, VCCI
output voltage
Q
Q.
recommended operating conditions
Operating free-air temperature, T A
~
CD
>
'':::
Q outputs
10
Serial output
Q outputs
Serial output
input current
ICCl
Supply current from VeCl
ICC2
I SN6S5S3, SN65554
Supply current from VCC21 SN75553. SN75554
TEXAS
MIN
MAX
57
V
VCC1- loS
8
1
1
pA
5
mA
10
~
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
V
pA
-1
12
INSTRUMENTS
UNIT
mA
3-105
Q
SN65553, SN65554, SN75553, SN75554
ELECTROLUMINESCENT COLUMN DRIVERS
switching characteristics. VCC1 - 12 V. VCC2 - 60 V. TA - 25 D C
TEST CONDITIONS
PARAMETER
MIN
Propagation delay time, high-to-Iow-Ievel
tpHL
tpLH
tDHL
tDLH
c
Serial output from Clock
CL = 20 pF to ground,
Propagation delay time, low-to-high-Ievel
See Figure 3
Serial output from Clock
Delay time, high-to-Iow-Ievel
CL = 20 pF to ground,
Q output from Latch Enable
See Figure 4
Delay time, low-to-high-Ievel
CL = 20 pF to ground,
Q output from Latch Enable
See Figure 4
(ii'
't:II
.f
..
RECOMMENDED OPERATION CONDITIONS
c
~'
INPUT VOLTAGE LOGIC-LEVEL LIMITS
til
SUPPLY VOLTAGE VCC1
YS
12
TA =
~,,~
10
>I
.,
!!'"
8
.I
F~II Range
~~
...- ,.---
l.-----
~ 6
...
::I
Q.
c
"'i
">
4
2
o
10
11
MaximumVIL
12
13
14
vce-Supply Voltage-V
FIGURE 1
3-106
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76266
15
MAX
UNIT
140
ns
140
ns
500
ns
1
ps
SN65553, SN65554, SN75553, SN75554
ELECTROLUMINESCENT COLUMN DRIVERS
PARAMETER MEASUREMENT INFORMATION
/4---tw (CLKI---.j
I
I
1
-1----- V,H
I
CLOCK
50%
I
50%
I
I
I
I
I
I
j...--tW(CLKI--.!
/4--tsu---+l+- th----.j
I
O.....
I
oo:::
FIGURE 2. INPUT TIMING VOLTAGE WAVEFORMS
•
..
(I)
II)
>
";:
Q
....J/:r5o-%----.'\------~::
CLOCK _ _ _
>ca
C.
(I)
C
I
I
I
r--------: fO%
SERIAL OUTPUT
----tP-LH--+l-+..J
~- - - - - - - - -
-
VOH
VOL
.., --j { . - - -- -- -- - ,~
SERIAL OUTPUT
.....- - - - - - - - - - - - - VOL
FIGURE 3. VOLTAGE WAVEFORMS FOR PROPAGATION DELAY
CLOCK TO SERIAL OUTPUT
LATCH ENABLE _ _ _ _..J{50%
tW(LE)~5~
-
-
-
-
~::
I
~tDLH
r----------
a OUTPUT
-+:...Jl{~ ________ _
VOH
___
VOL
I
I
a OUTPUT
i 1\0%---------
VOH
~tDHL
FIGURE 4. VOLTAGE WAVEFORMS FOR DELAY TIMES.
LATCH ENABLE TO Q OUTPUTS
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
3-107
•
C
iii"
'C
iii'
<
C
:::t.
~
iil
3-108
SN65555. SN65556. SN75555. SN75556
ELECTROLUMINESCENT COLUMN DRIVER
SN85555,SN75555
• Each Device Drives 32 Electrodes
N OUAL-IN-L1NE PACKAGE
• 90-V Output Voltage Swing Capability
Using Ramped Supply
(TOPVIEWI
017
016
015
014
013
012
011
010
09
08
07
06
05
Q4
03
02
01
SERIAL OUT
CLOCK
GNO
• 15-mA Output Source and Sink Current
Capability
• High-Spaed Sarially-Shifted Data Input
• Totem-Pole Outputs
• Latches on All Drlvar Outputs
description
The SN65555, SN65556, and SN75556 are
monolithic BIDFETt integrated circuits designed
to drive the column electrodes of an electroluminescent display. The SN65556 and
SN75556 output sequence has been reversed
from the SN65555 and SN75555 for ease in
printed circuit board layout.
The devices consist of a 32-bit shift register, 32
latches, and 32 output AND gates. Serial data
is entered into the shift register on the low-tohigh transition of the clock input. When high, the
Latch Enable input transfers the shift register
contents to the outputs of the 32 latches. When
Output Enable is high, all outputs are enabled.
Data must be loaded into the latches and Output
Enable must be high before supply voltage VCC2
is ramped up.
The SN65555 and SN65556 are characterized
for operation from -40°C to 85°C. The
SN75555 and SN75556 are characterized for
operation from O°C to 70 o e.
•
en
~
CD
.~
~
028
029
030
031
032
OUTPUT ENABLE
QATAIN
LATCH ENABLE
Q
>
ca
a.en
is
VCC1
VCC2
SN85566,SN75556
FN PLASTIC CHIP CARRIER PACKAGE
a
Serial data output from the shift register may be
used to cascade shift registers. This output is not
affected by the Latch Enable or Output Enable
inputs.
018
019
020
021
022
023
024
025
026
027
(TOPVIEWI
NM¢Il)(Q"COCDO_N
- . - - _ _ _ _ NNN
00000000000
6 5 4 3 2 1 4443424140
all
010
09
08
Q7
7
8
9
10
11
12
13
14
15
16
01
17
39
38
36
35
34
33
32
31
1819202122232425262728
NC - No internal connection
talDFET :- Bipolar, double-diffused, N-channel and P-channel MOS transistors on same chip - patented process.
PRODUCTION DATA d..u""",11 .ontaln 1.lonnltio.
.umat II 01 publieotion dill. Products .onlorm to
opICifieotio•• pa, tha tar... 01 TUH Instruments
:,'::=~·I:I~li ~:=::':: :.f':":~:~ not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265
Copyright @ 1985, Texas Instruments Incorporated
3-109
SN6555L
SN6555~
SN7555L SN75556
ELECTROLUMINESCENT COLUMN DRIVER
SN66656.SN75556
SN65556.SN75556
N DUAL·IN·LlNE PACKAGE
FN PLASTIC CHIP CARRIER PACKAGE
(TOPVIEWI
NN _ _ _ _ _ _ _ _ _
(TOPVIEWI
016
017
018
019
020
021
022
023
024
025
C
if
'C
026
027
028
029
030
031
032
SERIAL OUT
CLOCK
GND
jij
-<
C
::::!.
<
iil
CD
_omco,.....COI.t)q-('I)N_
015
014
013
012
011
010
09
08
07
06
05
04
03
02
01
OUTPUT ENABLE
DATA IN
LATCH ENABLE
00000000000
6 5 4 3 2
022
023
024
025
026
029
1 4443424140
7
8
39
38
9
37
10
36
11
35
12
34
13
14
33
32
15
31
16
30
17
29
08
07
06
05
04
03
02
01
NC
1819202122232425262728
VCCl
VCC2
NC - No internal connection
logic symbols t
SN65556.SN75556
SN65555.SN75555
117) 01
116)02
1171 01
116)02
C>
2D C>
20
20 C>
20 C>
3
3
··
·
11) 017
140)018
C>
20 C>
i27l 031
126) 032
20 C>
20 C>
20
118) SERIAL OUT
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publicatio'n 617-12,
Pin numbers shown are for N packages.
3·110
TEXAS ...,
INSlRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3
3
··
140) 015
III 016
116) 031
117) 032
118) SERIAL OUT
SN65555, SN65556, SN75555, SN75556
ELECTROLUMINESCENT COLUMN DRIVER
logic diagram (positive logic)
VCC2--------------------------------------------------~
OUTPUT __________________________________- ,
ENABLE
OUTPUT
BUFFERS
LATCH
ENABLE
DATA IN
•
-------I
t-+----01
CLOCK - -.....----1~
.
II)
CD
>
.~
Q
...-+----02
••
~
Q.
28 STAGES
103 THRU 030)
NOT SHOWN
•
II)
is
...-+----031
...------032
>------------------------SERIAL OUT
FUNCTION TABLE
CONTROL INPUTS
FUNCTION
LOAD
LATCH
OUTPUT
ENABLE
LATCH
OUTPUT
CLOCK
ENABLE
ENABLE
!
X
X
X
X
X
X
No!
X
X
X
X
l
H
X
X
SHIFT REGISTER
R1 THRU R32
OUTPUTS
LATCHES
LC1 THRU LC32
SERIAL
01 THRU 032
Load and shift t
Determined by Latch Enable.t
R32
Determined by Output Enable
No change
Determined by Latch Enable:t:
R32
Determined by Output Enable
As determined above Stored data
R32
Determined by Output Enable
As determined above New data
R32
Determined by Output Enable
l
As determined above Determined by latch Enable;
R32
Alil
H
As determined above Determined by Latch Enable:!:
R32
lC 1 thru lC32, respectively
H = high level, L = low level, X = irrelevant, t = low-to-high-Ievel transition.
tR32 and the serial output take on the state of R31, R31 takes on the state of R30, ... R2 takes on the state of R1, and R1 takes on
the state of the data input.
;f:New data enter the latches while Latch Enable is high. These data are stored while Latch Enable is low.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TEXAS 75266
3-111
SN65555, SN65556, SN75555, SN75556
ELECTROLUMINESCENT COLUMN DRIVER
typical operating sequence
unununUnL ••• J1J1JU11lJ
CLOCK - - ,
DATA IN
II
SR CONTENTS
C
iii'
LATCH ENABLE
iii'
<
LATCH
CONTENTS
'C
..<'
..
C
VALID
IRREL~VANT
INVALID
VALID
______________________
~r1~
________________
I
PREVIOUSLY STORED DATA
NEW DATA VALID
OUTPUT
ENABLE
CD
fI)
VCC2
----------------------~/
\~------
___V_A_L_I~
OOUTPUTS ____________________________________~I'
___
"~_____________
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL 0 OUTPUTS
VCC1---~~--._~--
INPUT
_t-'''''''-'-'
GND~~----._~~
3-112
VCC2
OUTPUT
--e--~~~~~-GND
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TYPICAL OF SERIAL OUTPUT
----+---- VCC1
.....- -. . .-
OUTPUT
---e-~~-~--GND
SN6555t SN6555L SN7555t SN75556
ELECTROLUMINESCENT COLUMN DRIVER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 18 V
Supply voltage, VCC2 (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 90 V
Input voltage ..................................................... Vee1 + 0.3 V
Ground current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 700 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 3):
N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1250 mW
FN package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1700 mW
Operating free-air temperature range: SN65555, SN65556 .................. -40°C to 85°C
SN75555, SN75556 .................... , O°C to 70 0 e
Storage temperature range ......................................... - 65 °e to 150°C
Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260 0 e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package. . . . . . . . . . . .. 260°C
NOTES:
•
1. Voltage values are with respect to network ground terminal.
2. These devices have been designed to be used in applications in which the high·voltage supply, VCC2, is switched to ground
before changing the state of the outputs.
3. For operation above 25°C free·airtemperatur., derate the N package at the rate of 10 mW/oC and the FN package at the
rate of 13.6 mW/oC.
recommended operating conditions
VCCl
Supply voltage
VCC2
Supply voltage
V,H
High-level input voltage (see Figure 1)
V,L
Low-level input voltage (se. Figure 1)
VCCl VCCl -
10.8 V
15 V
VCCl - 10.8 V
VCC1
~
15 V
MIN
NOM
MAX
10.8
12
15
V
0
80
V
8.1
11.1
11.25
15.3
-0.3 t
2.7
-0.3 t
3.75
UNIT
V
V
IOH
High-level output current
-15
rnA
IOL
Low-level output current
15
rnA
10K
Output clamp· current
20
rnA
fclock
Clock frequency
6.25
MHz
a
tw(CLK)
Pulse duration, clock high or low (see Figure 2)
80
ns
tw(LE)
Pillse duration, latch enable (see Figure 4)
80
ns
tsu
Setup time
th
Hold time
dv/dt
Rate of rise for VCC2 (see Figur. 4)
TA
Operating free-air temperature
Data before clock t (see Figure 2)
Output enable before VCC; (see Figure 4)
Data after clock; (see Figu!. 2)
Output enable after Vcct Isee Figure 4)
20
ns
500
80
ns
100
80
SN65555, SN65556
40
85
SN75555.SN75556
0
70
V/~s
°c
tThe algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic
voltage levels.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TeXAS 75265
3-113
SN65555, SN65556, SN75555, SN75556
ELECTROLUMINESCENT COLUMN DRIVER
electrical characteristics over recommended operating free-air temperature range, VCC1 - 12 V,
VCC2 - 80 V
TEST CONDITIONS
PARAMETER
VOH
•
o
ii'
iii
"C
High-level output voltage
VOL
Low-level output voltage
IIH
High-level input current
Q outputs
lo=-15mA
Serial output
10 -
MIN
MAX
77
V
10.5
-100 pA
UNIT
Q outputs
10L = 15 mA
Serial output
10L - 100 ~A
1
VI - 12 V
1
8
V
pA
IlL
Low-level input
-1
~A
ICCl
Supply current from V CC 1
2
mA
ICC2
Supply current from V CC2
5
mA
cu~rent
VI = 0
switching characteristics, VCC1 - 12 V, TA '" 25°C
o
tpHL
::::!.
;;
tpLH
Ul
TEST CONDITIONS
PARAMETER
<
td
MIN
Propagation delay time, high-to-Iow-Ievel
Serial output from Clock
CL = 20 pF to ground, VCC2 = 0,
Propagation delay time, low-to-high-Ievel
See Figure 3
Serial output from Clock
dv/dt = 80
Delay time, VCC2 to Q outputs
V/~s,
See Figure 4
RECOMMENDED OPERATION CONDITIONS
INPUT VOLTAGE LOGIC-LEVEL LIMITS
vs
SUPPLY VOLTAGE VCC1
12
>I
II
!
TA = L
Full RangeI
.
10
1
It' ,,\~
tlt~
~
~
8
---
l
0
>...
6
"c
Co
j'
->
4
-
Maximum VIL
-
2
o
10
11
12
13
14
vee-Supply Voltage-V
FIGURE 1
3-114
TEXAS . "
INSTRUMENTS
. POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
15
MAX
UNIT
140
ns
140
ns
100
ns
SN6555t SN6555~ SN7555t SN75556
ELECTROLUMINESCENT COLUMN DRIVER
PARAMETER MEASUREMENT INFORMATION
If--'w(CLK)--+j
..1 ___
I
I
VIH
I
CLOCK
1-----'I
VIL
lII----'w(CLK)--+t
jf--'su--+k-'h-+l
I
:
OATAIN~
VALID
VIH
"f:IXI)VIL
FIGURE 2. INPUT TIMING VOLTAGE WAVEFORMS
•
f
CD
>
"i:
C
\ ----::~
-'to%
CLOCK _ _ _
--..j
\f'r--------
I
SERIAL OUTPUT
\
-----+1-'
~
SERIAL OUTPUT
I+- tpLH
>-
CIS
Q.
en
is
I
VOH
50%
- - - - - - /4-tpHL
----"'~o%-
- - - - --
VOL
VOH
~,--------VOL
FIGURE 3. VOLTAGE. WAVEFORMS FOR PROPAGATION DELAY
CLOCK TO SERIAL OUTPUT
):;---:::
1.\50%
To'
OUTPUT _ _ _......
ENABLE
vCC2
'It ~
I
I
t"'-hI/1~
_ _ _ _ _...l(/10m
th - - - - BOV
10%\
I
tct~ t.-,.-_....,.
QOUTPUT
V
-&-
VALID \ - . - - - - -
_
OV
V
OH
VOL
FIGURE 4. VOLTAGE WAVEFORMS FOR DELAY TIMES. LATCH ENABLE TO Q OUTPUTS
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
3-115
II
c
(ii'
'C
i»
<
..;;:C
CD
Cil
3-116
SN65557. SN65558. SN75557. SN75558
ELECTROLUMINESCENT ROW DRIVERS
02999. DECEMBER 1985
SN65557, SN75557 ... FN PACKAGE
•
Each Device Drives 32 Electrodes
•
High-Voltage Open-Collector N-P-N Outputs
Using Ramped Supply
NN .......... - - ..................... U
•
300-mA Output Current Capability
6
•
CMOS-Compatible Inputs
•
Very Low Steady-State Power Consumption
ITOPVIEWI
...... OOl(X)r--(l)I!)q-('f')N
ooooooooooz
5 4 3 2
1 4443 42 41 40
37
NC
Qll
Ql0
10
36
Q9
11
35
Q8
12
34
39
38
description
These devices are monolithic BIDFETt integrated
circuits designed to drive the row electrodes of
an electroluminescent display. All inputs are
CMOS-compatible and all outputs are highvoltage open-collector n-p-n transistors. The
SN65558 and SN75558 output sequences have
been reversed from the SN65557 and SN75557
for ease in printed circuit board layout.
Q31
13
33
14
34
15
31
16
30
17
29
1819202122232425262728
II..
en
CD
>
'C
C
>
as
Q.
en
C
The devices consist of a 32-bit shift register, 32
AND gates, and 32 output OR gates. Typically,
a composite row drive signal is externally
generated by a high-voltage switching circuit and
applied to the Substrate Common terminal. Serial
data is entered into the shift register on the highto-low transition of the clock input. A high Enable
input allows those outputs with a high in their
associated register to be turned on causing the
corresponding row to be connected to the
composite row drive signal. When the Strobe
input is low, all output transistors are turned on.
The Serial output from the shift register may be
used to cascade additional devices. This output
is not affected by the Enable or Strobe inputs.
SN65558. SN75558 ... FN PACKAGE
ITOPVIEWI
NMvLOClI-
OATA IN ~1D
C
E1L- G2
SRG 32
[>
2.3
···
[>
2.3
[>
···
···
[>
2.3
Q~'01
:..Jlli,02
Q ~ 011
_Q ~ 012
0 ~ 015
2.3
[>
2.3
[>
.Q p>---l!l 016
2.3
[>
.Q~ 021
2.3
··· ··•
[>
.Qp-!!!! 022
2.3
[>
o~ 031
2.3
[>
r
DATA IN ~1D
Q
~ 032
~ SERIAL OUT
2.3
2.3
[>
2.3
[>
2.3
[>
·· ···
··· ···
··· ···
··· ··
[>
2.3
[>
2.3
I>
I>
2.3
[>
2.3
[>
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
functional block diagram (positive logic)
su~~~~~~
______________________________________..,
STROBE------------------~
ENABLE--------,
DATA IN - - - - i
CLOCK
-"'-<:1>
Q31
032
' - - - - - - - - - - - - - - - - - - - S E R I A L OUT
3-118
tEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
po....!.!.!!. 02
[>
2.3
2.3
Q~ 01
.
0 ~ 011
Q ~ 012
0
~ 017
.Q ~ 018
.Q~ 021
Q~ 022
Q~ 031
~ 032
~
~ SERIAL OUT
SN65557, SN65558. SN75557, SN75558
ELECTROLUMINESCENT ROW DRIVERS
FUNCTION TABLE
CONTROL INPUTS
LOAD
ENABLE
STROBE
OUTPUTS
SHIFT REGISTERS
FUNCTION
R1 THRU R32
SERIAL
01 THRU 032
CLOCK
ENABLE
STROBE
j
X
X
Load and Shift t
No j
X
L
X
No Change
R32
Determined by Enable and Strobe
X
H
As determined above
R32
All Q outputs off
X
H
H
As determined above
R32
Determined by Rl through R32
X
X
L
As determined above
R32
All Q outputs on
R32
Determined by Enable and Strobe
H = high level, L = low level, X == irrelevant, ~ = hjgh~to~low transition.
t Register R32 takes on the state of R31, R31 takes on the state of R30, ... R2 takes on the state of R1. and R1 takes
on the state of the data input.
•
...
en
~
.;:
schematics of inputs and outputs
C
>-
EOUIVALENT OF EACH INPUT
TYPICAL OF ALL 0 OUTPUTS
vCC------~~--__~._--
. - - -....- - OUTPUT
INPUT-....JV\,..,...........
TYPICAL OF SERIAL OUTPUT
------~.-----VCC
«I
C.
en
i5
OUTPUT
TEXAS ...,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-119
SN65557, SN65558, SN75557, SN75558
ELECTROLUMINESCENT ROW DRIVERS
tvpical operating sequence
CLOCK
U
----..
U
".-----...
-
-
-
-
-
-
-
-
-
-
-
-
- - VIH
SUBSTRATE COMMON
-
- -
.In - - - - - - - - - - - - -- -
DATA IN _ _ _
SN65!;57, SN76557
ENABLE
SN6555B, SN75558
ENABLE
-----.1
...,
...,- -
SN65558, SN75558
01 OUTPUT
SN65557,SN75557
02 OUTPUT
VIH
SUBSTRATE COMMDN
v _____________ ~:V
V______ ~--- ::v
V_______ ::v
~::V
SN65558, SN75558
02 OUTPUT
HV = High voltage
3-120
~~BSTRATE COMMON
OV
RAMPED COMPOSITE ROW - - - - - " "
DRIVE APPLIED TO
SUBSTRATE COMMON
SN65557, SN75557
01 OUTPUT
VIH
SUBSTRATE COMMON
-
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 8&5012 • DALLAS, TEXAS 75285
SN65557. SN65558. SN75557. SN75558
ELECTROLUMINESCENT ROW DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vce (see Note 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 18 V
Off-state output voltage, VO(offl (see Note 21 .................................... 110 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vec+0.3 V
Substrate common terminal current (see Note 3) ................................ 750 mA
Continuous total dissipation at (or belowl 25 DC free-air temperature (see Note 41: . . . . .. 1700 mW
Operating free-air temperature range: SN65557, SN65558 .................. - 40°C to 85 °C
SN75557, SN75558 ..................... ooe to 70°C
Storage temperature range ......................................... -65 DC to 150°C
Case temperature for 10 seconds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
NOTES:
1. Voltage values are with respect to substrate common terminal.
2. Data must be clocked into the shift register and Q outputs enabled prior to ramping substrate common to - HV (see typical
operating sequence).
3. Duty cycle is limited by package dissipation.
>
~
7i
II)
recommended operating conditions
Supply voltage, Vee
Vee _. 10.8 V
High-level input voltage, VIH Isee Figure 1)
Vee
Vee
Low-level input voltage, VIL (see Figure 1)
=
=
15V
10.8 V
Vee - 15 V
Oll'state Q output voltage, VO(oll)
Q
MIN
NOM
MAX
10.8
12
15
8.1
11.1
11.25
15.3
-0.3
2.7
-0.3
3.75
-0.3
output current, 10(on). duty cycle :s: 1%,Vee- 15 V
Rate of rise for substrate common, dV/dt (see Figure 4)
Clock frequency, fclock
0
Pulse duration, clock high or low, tw
Setup time, tsu
Enable before substrate common! (see Figure 4J
I
I
10(011) Off-state Q output current
High·level output voltage
100
V/~s
4
MHz
ns
ns
-40
85
SN75557, SN75558
a
70
CONDITIONS
SN65557
MIN
I Q outputs
I Serial output
10 -
-100 ~A
= 12 V (unless
SN75558
MAX
MIN
UNIT
MAX
10
20
10.5
10.5
10
IOL ~ 100 "A
1
1
VI = 12 V
1
1
Low-level output voltage
IIH
High-level input current
IlL
Low-level input current
VI -
ICC
Supply current from
a
Vee
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
~A
V
20
10L - 300 rnA
VOL
.
Vee
°e
SN75557
SN65558
Vo = 100 V
Serial outputs
ns
SN65557,SN65558
TEST
PARAMETER
V
V
500
electrical characteristics over recommended operating free-air temperature range,
otherwise noted)
V
rnA
100
Operating free-air temperature, T A
V
100
50
Hold time, th, data after clock! (see Figure 3)
C
UNIT
300
125
Data before clock! Isee Figure 3)
VOH
f!
CD
>
'i:
Q
4. For operation above 25°C free-air temperature, derate linearly to 1088 mW at the rate of 13.6 mW/oC.
On-state
II
V
~A
-1
-1
pA
250
250
~A
3-121
SN65557, SN65558, SN75557, SN75558
ELECTROLUMINESCENT ROW DRIVERS
switching characteristics. VCC .. 12 V. TA - 25°C
PARAMETER
tpHL
tpLH
level serial output from clock
CL = 20 pF to substrate common
Propagation delay time. low-to-high-
II
C
MIN
(see Figure 4)
level serial output from clock
Turn~on
td(onl
TEST CONDITIONS
Propagation delay time. high-to-Iow-
delay
from enable
tim~.
Q outputs
dVldt = 100 Vips. Strobe at VCC.
RL = 2 klHo 60 V (see Figure 4)
RECOMMENDED OPERATING CONDITIONS
iii"
"C
Dr
<
INPUT VOLTAGE LOGIC-LEVEL LIMITS
vs
SUPPLY VOLT AGE
...Cc:CD
...
12
TA -
-----
~oe to 76 e
0
!II
10
~
>
.....
8
>
6
I
.ll!0
~NIMUMVIH
5a.
c
I
>"
4
-
2
MAXIMUM Vil
o
10
11
12
13
14
Vee-Supply Voltage-V
FIGURE 1
3-122
TEXAS •
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75265
15
MAX
UNIT
200
ns
200
ns
500
ns
SN65557. SN65558. SN75557. SN75558
ELECTROLUMINESCENT ROW DRIVERS
PARAMETER MEASUREMENT INFORMATION
CLOCK
II '--_ _ _J..
~tw
•
.,
,..-tsu _ _ _ th~
I
DATA IN
~
IVIH
~
VALID
VIL
FIGURE 2. INPUT TIMING VOLTAGE WAVEFORMS
,.----{,F-'--""\~~%-
-
- - - VIH
CLOCK
I
If
1 f - -.....
~It-tPLH
vlL
~
tPHL 141
-.J",.0-%-----1
50.sL- --
DATA OUT _ _ _ _
VOH
'"LVOL
FIGURE 3. VOLTAGE WAVEFORMS FOR PROPAGATION DELAY TIMES, CLOCK TO DATA OUT
, . - - - - - - - - - - VIH
ENABLE
1'0%
---------~-,- -
-
-
-
-
-
-
-
-
-
VIL
I
~tsu_+l+__td~
SUBSTRATE
COMMON
. ·'--1-----"
'I.._...:.._ _ _ _ _ -60 V
I
I
---------------;:90:::%~X_
Q OUTPUT
.- - - - - 0V
\
'-----VOL
FIGURE 4. VOLTAGE WAVEFORMS FOR TURN ON DELAY TIME.
SUBSTRATE COMMON TO Q OUTPUT
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
3-123
SN65557, SN65558, SN75557, SN75558
ELECTROLUMINESCENT ROW DRIVERS
TYPICAL CHARACTERISTICS
ON-STATE Q OUTPUT CURRENT
vs
ON-STATE Q OUTPUT VOLTAGE
300
028
029
030
031
032
NC
DATA IN
LATCH ENA8LE
07
06
05
04
03
02
01
SERIAL OUT
CLOCK
GND
"i:
Q
>
as
Q.
III
is
VCCl
VCC2
SN65559, SN75559 .•. FN PACKAGE
(TOPVIEWI
__
_ _ _ _ _ _ NNN
C'\I
(W) q. ID co ,.... ex).0) 0
... N
ddddddddddd
6
011
The SN65559 and SN65560 are characterized
for operation from -40°C to 85°C. The
SN75559 and SN75560 are characterized for
operation from OOC to 70°C.
5 4 3 2 1 4443424140
7
39
8
38
37
10
36
11
12
35
34
13
33
14
32
15
31
16
30
z
o
i=
NC - No internal connection
C
<
l>
ENABLE
CLOCK .;...(1_9,-)--1:>
CLOCK ,,-(1_9,-)- [ >
(17) Ql
DATA IN (24)
2
n
2
"T1
o
m
20
2D
20
~
~
C>
C>
C>
20 C>
::IJ
o2
(26) Ql
DATA IN (24)
(16) Q2
C>
3-126
(40) Q15
(1)
Q16
C>
20 C>
(16) Q31
20
(27) Q31
(26)
Q32
(18)
SERIAL OUT
20
20
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for N packages.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
"
C>
C>
il) Q17
(40)
Q18
··
(27) Q2
·
(17) Q32
(lB)
SERIAL OUT
SN65559, SN65560, SN75559, SN75560
ELECTROLUMINESCENT DISPLAY COLUMN DRIVERS
ADVANCE
INFORMATION
FUNCTION TABLE
CONTROL INPUTS
FUNCTION
CLOCK
;
LOAD
LATCH
H
~
high level; L
LATCH
ENABLEt
No;
X
X
X
X
L
H
~
SHIFT REGISTERS
LATCHES
Rl THRU R32
LCl THRU LC32
Load and Shift
No change
~
irrelevant; ;
~
SERIAL
Determined by Latch Enable
Stored data
New data
As determined above
low level; X
OUTPUTS
R32 t
01 THRU 032
LC 1 thru LC32 respectively
R32
R32
R32
LC 1 thru LC32 respectively
low-to-high-Ievel transition
t New data enters the latches while Latch Enable is high. These data are stored while Latch Enable is low.
t R32 and the serial output take on the state of R3l, A3l takes on the state of A30 ... R2 takes on the state of Rl and Rl takes
•
...
II)
on the state of the data input.
Q)
>
logic diagram (positive logic)
';:
C
VCC2
LATCH
ENABLE
OUTPUT BUFFERS
SHIFT
REGISTER
Cl
20
T
L10
R2
L
20
10
R3l
01
I>
LC2
r--
02
•
••
.-- C2
20
10
R32
I
I>
LC3l
T
Cl
r--
•
••
•
••
Cl
L
LCl
~ C2
Cl
•
••
I>
~ C2
Rl
CLOCK
i:'S
LATCHES
10
DATA IN
>ca
is.
II)
-
r--
031
I LC32
z
o
i=
I>
C2
20
28 STAGES
(03 THR U 030)
NOTSHOWN
c
I
CD
15""
~
8
la'
>
;
6
'j
4
...c
Maximum Vil
'>
-
2
»
C
<
»
2:
n
»
m
0
10
11
12
13
14
VCC1-Supply Voltage-V
FIGURE 1
-
2:
"TI
0
::xJ
s:
»
:::!
0
2:
3-130
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
MAX
UNIT
140
ns
140
ns
100
ns
V/~s,
CL = 100 pF,
Q
MIN
15
ADVANCE
INFORMATION
SN65559. SN65560. SN75559. SN75560
ELECTROLUMINESCENT DISPLAY COLUMN DRIVERS
PARAMETER MEASUREMENT INFORMATION
!.--tw(CLKI~
.1 ___
I
I
VIH
I
CLOCK
I
1'-------'1
I 4 - - tw (CLKI--+l
If-tsu~th-+l
I
DATA IN
:
~
"Kf.XI.)
VALID
VIH
II
~
G)
VIL
>
';:
Q
FIGURE 2. INPUT TIMING VOLTAGE WAVEFORMS
>
ca
-+I
I
I
SERIAL OUTPUT
I
UI
i5
~tPLH
fl
I
r-------VOH
50%
-----+I...J-+I
Q.
\ ----::~
...JfO%
CLOCK _ _ _
-------VOL
i+-tPHL
~O:-
SERIAL OUTPUT - - - -......
-
-
-
-
-
-
VOH
\...- - - - - - - - VOL
FIGURE 3. VOLTAGE WAVEFORMS FOR PROPAGATION DELAY CLOCK TO SERIAL OUTPUT
t. - 0.8 ps~
VCC2 _ _ _ _
.........,~r:::"!o~%--"'\\
I
td~
Q
OUTPUT
2:
o
j4-
-
-
-
-
-
i=
c
c
«
tBIDFET-Bipolar, double-diffused, N-channel and P-channel MOS transistors on the same chip - Patented Process
Copyright @ 1986. Texas Instruments Incorporated
ADVANCE INFORMATION d.o....nll oontain
~n,::z.!i~::':;'~=Jr:::..":~~:ec::~
~... and oilier .paoifloation. ara a.bjact to ohanga
without notice.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
3-133
SN65563, SN65564, SN75563, SN75564
ELECTROLUMINESCENT ROW DRIVERS
ADVANCE
INFORMATION
LOAD FUNCTION TABLE
CONTROL INPUTS
POSITIVE
CLOCK
ENABLE
WRITE
FUNCTION
X
X
l
Nol
LOAD
X
X
OUTPUTS
SHIFT REGISTER
R1 THRU R34
SERIAL
Load and Shift T
R34
Determined by Enable and Positive Write
No Change
R34
Determined by Enable and Positive Write
01 THRU 034
t Register R34 takes on the state of R33. R33 takes on the state of R32 •... R2 takes on the state of R1. R1 takes on the state of the
data input.
OUTPUT CONTROL FUNCTION TABLE
c
;.
POSITIVE
WRITE
SHIFT REGISTER
CONTENTS Rn FOR
R1 THRU R34
(Determined Above)
CONTROL INPUTS
FUNCTION
'"C
ii
<
C
:::!.
<
CD
Ul
=
H
high. L
=
SERIAL
01 THRU 034
R34
R34
High-Impedance
H
H
L
R34
R34
CLOCK
ENABLE
X
X
X
X
L
H
X
X
H
H
L
X
X
OUTPUT
CONTROL
=
low. X
irrelevant. l
=
OUTPUTS
H
L
High-Impedance
high-to·low transition
logic symbols*
SN65564.SN75564
SN65563.SN75563
VCC2
VCC2
CMOS/EL OISP
1271
] [0
1281
CLOCK
VCC2
1221
Vss
1231
Vss
ENABLE
POSITIVE
WRITE
VCC2
DRAIN SUPI'LV)
1211
-""
] [0 DRAIN SUPPLY]
{221
] [0 SOURCE SUPPLY]
1201
POSITIVE {251
ENABLE
EN3[OUTPUT ENABLE]
EN2 [OUTPUT SELECT]
1251
CMOS/EL DISP
{281
VSS
{231
Vss
] [0 SOURCE SUPPL V]
1201
{271
WRITE
SRG34
C1/-
CLOCK
{211
EN3 [OUTPUT ENABLE]
EN2[OUTPUT SELECT]
....
SRG34
C1/-
r
DATA IN
»
c
1D
2.3U
I>
2.3
··
I>
m
Z
-
··
."
o~
2.3U
2.30
b
2.30
h
2.30
···
I>
I>
3:
h
···
I>
tl
2.30
2.30
I>
~
o
~
o
1261
h
2.30
h
2.30
2.30
2.30
1291
01
DATA IN
{261
I>
1301 Q2
···
1441
111
1171
I>
017
··
033
(181
034
{191 SERIAL
OUT
z
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
··
I>
016
*These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
3-134
I>
1D
··
I>
I>
2.30
2.30
2.30
2.30
h=l
1181
:::::-1
(17)
::::-J
(11
:::::-1
2.30
{441
2.30
2.30
2.30
b
h=l
2.30
2.3U
2.30
2.30
1301
{291
01
02
018
019
033
034
{191 SERIAL
OUT
ADVANCE
INFORMATION
SN65563, SN65564, SN75563, SN75564
ELECTROLUMINESCENT ROW DRIVERS
logic diagram Ipositive logic)
VCC2--------------------------------------------------,
PO~~:~~
_________________
~------------_,
.-I-+--oL..I
01
ENABLE
OATA IN
•
------------1
CLOCK
..
en
CD
02
>
"t;
Q
>
IV
"Q.
en
Q
•• ••
• •
••
•
•• ••
• •
•
31 STAGES
(03 THRU 0331
NOT SHOWN
VSS~
--1
1--______________
>------------------ SERIAL OUT
2:
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
VCC1------~.-----.-e----
o
TYPICAL OF ALL Q OUTPUTS
1---~~-----.--~~VCC2
i=
SERIAL OUTPUT
«
--------e----------VCCI
::E
a:
ou.
INPUT
-._JW_'_"
2:
........+-OUTPUT
__- - - - - OUTPUT
--~~
VSS~~-------1~__e_---
I-~~~~------~--VSS
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
----J7
......lJ
-----------
w
CJ
2:
VSS
«
c>
«
3-135
SN65563, SN65564, SN75563, SN75564
ADVANCE
INFORMATION
ELECTROLUMINESCENT ROW DRIVERS
typical operating sequence
CLOCK
DATA IN
----,U1"--------,U __________
---11- ----- --- - - - - -- ---
VIH
-VSS
----VIH
~--------------------VSS
•
-----VIH
ENABLE
'------VSS
POSITIVE WRITE CYCLE
PO~~:~~.-J _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
C
iii'
'a
5
VCC2
c
/
\
/
\
-:;s
- - - - ---::S::MGND
:::t,
...en~
VSS--------------------------SYSTEMGND
.J/~
FIRST _ _ _ _ _
OUTPUT
.
I
SECOND
OUTPUT _ _ _ _-----J
NEGATIVE WRITE CYCLE
POSITIVE--,--- WRITE
-
-- -
---------------VIH
•
VSS
VCC2
VSS
»
c
~
FIRST
OUTPUT
:2
(")
SECOND
OUTPUT
m
-
:2
"TI
o
Vselect*
\
\
/
/
\
/
_ _ .:.... _ _ _ -HVt
SYSTEM GND
----------------~
\
/
tHY = high voltage
*Vselect is a voltage level typically equal to VCC2 of the column driver.
::0
3l:
»
::!
o
:2
3-136
SYSTEM GND
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TeXAS 75285
SYSTEM GND
_ _ _ _ _ _ -HVt
ADVANCE
INFORMATION
SN65563, SN6556' SN7556t SN75564
ELECTROLUMINESCENT ROW DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 V
Supply voltage, VCC2 ...................................................... 230 V
Supply voltage, VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 230 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to VCC1 + 0.3 V
Continuous total power dissipation at (or below) 25°C free-air temperature
(see Note 2) ........................................................ 1700 mW
Operating free-air temperature range: SN65563, SN65564 . . . . . . . . . . . . . . . . .. - 40°C to 85°C
SN75563, SN75564 . . . .. . . . . . . . . . . . . . . .. O°C to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 260°C
NOTES:
1. Voltage values are with respect to
Vss.
2. For operation above 25 DC free·air temperature. derate to 1088 mW at 70 DC at the rate of 13.6 mW/DC.
•
recommended operating conditions (see Note 1. Figure 1. and Figure 2)
MIN
Supply voltage. VCC2
0
MAX
13.2
225
Supply voltage. VSS
0
225
V
10.8
Supply voltage. VCCl
NOM
12
UNIT
V
V
High-level input voltage. VIH
0.75VCCl
VCCl +0.3
V
Low-level input voltage. VIL t
-0.3
0.25VCCl
-70
mA
High-level output current. IOH
Low-level output current. IOL
Output clamp current. 10K
V
70
mA
±70
4
MHz
mA
Clock frequency. f clock
Pulse duration. Clock high or low. twCLK
125
ns
Setup time. data high or low befora clock •• tsu 1
100
ns
Setup time. Clock low before VCC21 or VSS •• tsu2
300
ns
Setup time. Enable high before VCC21 or VSS!. tsu3
300
ns
Setup time. Positive Write high or low before VCC21 or VSS •• tsu4
Hold time. data high or low after clock!. thl
300
100
ns
ns
Hold time. Clock high after VCC2! or VSSI. th2
500
Hold time. Enable high after VCC2! or VSSI. th3
300
·ns
ns
Hold time. Positive Write after VCC2! or VSSI. th4
300
•Slew rate. VCC2 or VSS with one active output driving a 4.7-nF load
to VSS or VCC2. dvldt
5
Rest time, period between successive ram pings of VCC2 or VSS
Operating
free~air
temperature, T A
z
o
ns
45
I
SN65563. SN65564
-40
85
I
SN75563. SN75564
0
70
VII's
i=
:lE
a:
«
P.s
DC
tThe algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
oLL
Z
W
(,)
Z
~
Q
«
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-137
ADVANCE
INFORMATION
SN65563, SN6556' SN7556t SN75564
ELECTROLUMINESCENT ROW DRIVERS
electrical characteristics over recommended operating ranges of VCC1 and free-air temperature.
VCC2 .. 225 V. VSS .. 0 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Vo = 225 V
MAX
20
10(0111
Off-state Q output current
Q outputs
VOH
High-level
output voltage
Serial Out
10 = -70 rnA
100 pA,
10 -
Low-level
Q outputs
10 = 70 rnA
output voltage
Serial Out
10=100~A
1
High-level input current
VIH -' VCCI
1
IlL
Low-level input current
VIL - 0
c
ICCI
Supply current from VCCI
"g
ICC2
Supply current from VCC2
•
0'
VOL
IIH
iii
-<
...C
<'
CD
...
(II
Vo - 0
-20
VCCI
=
12 V
VCC2- 3O
10.5
All Q outputs low
pA
V
30
One Q output high
UNIT
V
~A
-1
pA
500
~A
5
200
rnA
MAX
UNIT
400
ns
400
ns
6
~s
6
~s
6
~s
6
~
pA
switching characteristics operating range of VCC1. TA == 25°C
PARAMETER
tpLH
TEST CONDITIONS
Propagation delay time, low-to-high
level serial output from clock
Propagation delay time, high-to-Iow
tpHL
tPLH
tpHL
tpLH
tpHL
CL = 50 pF to VSS,
See Figures 3 and 5
level serial output from clock
Propagation delay time, low-to-high
dv/dt =
level Q output from VCC2
Propagation delay time, high-to-Iow
One output on with
lever Q output from V CC2
Propagation delay time, low-to-high
level Q output from V 55
Propagation delay time, high-to-Iow
level Q output from V 55
45'V/~s,
CL = 4.7 nF to VSS,
See Figures 4 and 5
dv/dt - 45 V/~s,
One output on with
CL = 4.7 nF to VCC2,
See Figures 4 and 6
PARAMETER MEASUREMENT INFORMATION
»c
<
»
:2
(")
-m-n
:2
o::rJ
FIGURE 1. INPUT TIMING VOLTAGE WAVEFORMS
3:
»
::::!
o
:2
3-138
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
MIN
ADVANCE
INFORMATION
SN65563, SN65564, SN75563, SN75564
ELECTROLUMINESCENT ROW DRIVERS
PARAMETER MEASUREMENT INFORMATION
~VIH
CLOCK~
I
ENABLE
!+--th2~
I
90%"
I
I
I
I
I
I
I
I
I
I
I
I
X~g~
WRITE
I
I
I
~g~)(
I
1
I
----VIH
VIL
VIH
1(,.
,::X
\%
i
II
ill
~
VIL
1
1---- - - - - - -
Q)
>
";:
Q
-+HV
>
IV
SYSTEM GND
I
I
I
vsst
- - -
~th4
I4- t su4-+1
VCC2t
~o%
r+-+t- th3
j4- t su3-+j
POSITIVE
VIL
I
I4--- t su2 --+I
Q.
(/)
Q
SYSTEM GND
------------HV
tTiming waveforms are with respect to VCC2 or VSS, as appropriate.
FIGURE 2. CONTROL INPUT TIMING VOLTAGE WAVEFORMS
,.--.....,jr---, - - - - --- VIH
\0%
CLOCK
1'----
I
i4- t pHL-+i
\0....- - - -
I+-tpLH~
I..------(;f
--Jfo%
DATA OUT _ _ _ _
VIL
~V""
VOL
FIGURE 3. VOLTAGE WAVEFORMS FOR PROPAGATION DELAY TIMES. CLOCK TO DATA OUT
z
o
~
«
~
a:
o
LL
-w
Z
CJ
z
«
>
c
«
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-139
SN65563. SN6556' SN7556~ SN75564
ELECTROLUMINESCENT ROW DRIVERS
ADVANCE
INFORMATIOI
PARAMETER MEASUREMENT INFORMATION
,..-_ _ _ _ _ _ _ _--.,
VCC2 _ _ _
II ' ' ' ' '
..J~
-
-
-
-
~.
J'.
-
~-
------,
- -
- - +HV
hS_",'
I++t-- tPHL
~ tPLH
- -
----- _.MY
.
SYSTEM GND
c
;'
iii'
'tJ
<
---_
SJ
VSS
~'
, . - - - - - - - SYSTEM GND
'i'~%--------~-~- ----
_n_",
Ul
I++I-tPHL
I4-+t-tPLH
____~ I
QOUTPUT
I
SYSTEM GND
J:':--_____
~%
HV
FIGURE 4. VOLTAGE WAVEFORMS FOR PROPAGATION DELAY TIMES. VCC2 (VSSI TO Q OUTPUT
OUTPUT
UNDER
TEST
TEST
POINT
·,,-r"
»
c
FIGURE 5. LOAD CIRCUIT
~
VCC2~
:2
om
I
-
CLt
OUTPUT
_
TEST
UNDER - - - - - . - - - - - - POINT
TEST
:2
."
o
::xJ
s:
~
o
-----I..------
FIGURE 6. LOAD CIRCUIT
t CL includes probe and jig capacitance.
:2
3-140
TEXAS •
INSTRUMENTS .
POST OFFICE BOX 656012 • DALLAS. TEXAS 76265
ADVANCE
INFORMATION
SN65567, SN65568, SN75567, SN75568
ELECTROLUMINESCENT DISPLAY COLUMN DRIVERS
02983. DECEMBER 1986
•
Controls 32 Electrodes
•
60-V (Ramped VCC2) Totem-Pole Outputs
SN65567, SN75567 ... FN PACKAGE
•
Low CMOS Stand-By Power Consumption
•
Energy Recovery System Compatible
•
15-mA Source and Sink Compatibility
•
High-Speed Serially-Shifted Data Input
ITOPVIEWI
______
_ NNN
N('t).q-It)CO
...... _
COO')O
.... N
00000000000
6 5 4 3 2 1 4443424140
011
7
39
38
37
36
35
34
33
8
9
10
description
11
12
The SN65567, SN65568, SN75567, and
SN75568 are monolithic BIDFETt integrated
circuits designed to provide the serial-to-parallel
conversion and level translation of data in a
matrix-addressable electroluminescent display.
The device inputs are diode-clamped CMOS
inputs. The SN65568 and SN75568 output
sequences are reversed from the SN65567 and
SN75567 for ease in printed circuit board layout.
These column drivers consist of two 16-bit static
shift registers, 32 latches, and 32 high-voltage
outputs. Typically, a 32-bit data string is split
into two 16-bit data strings externally and then
entered in parallel into the shift registers on the
low-to-high transition of the clock signal. The
register associated with Data Input 1 loads the
odd bits while the shift register associated
with Data Input 2 loads the even bits of the
32 latches. This method of entering data
effectively doubles the clock frequency of a
32-bit shift register. A logic high signal on the
latch enable input transfers the data from the
shift register to the latches while the VCC2 bus
is low. Once stable in the latch circuits, the
VCC2 rail is ramped up to allow the data to
appear at the high-voltage outputs. By limiting
VCC2 to a maximum of 50 volts, these devices
may be safely operated in a non-ramped VCC2
mode. Drivers may be cascaded via the serial
data outputs of the static shift registers. These
outputs are not affected by the latch enable
input.
01
13
14
15
16
17
•
r!
CD
>
";::
32
31
30
Q
>
ca
29
1819202122232425262728
Q.
(I)
is
SN65568. SN75568 .•. FN PACKAGE
ITOP VIEWI
NN
_ _ _ _ _ _ _ ........
.... 0 0) co '" co It) q- ('t)'N .-
00000000000
6 5 4 3 2 1 4443424140
7
8
025
026
027
028
029
030
031
032
39
38
37
36
35
34
33
10
11
12
13
14
15
16
17
Z
o
i=
I>
I>
I>
420
217
219
"a
iii
...o
17 420
229 18 420
SRG16
.,401C43/-1
II)
DATA IN2
l1!L-
SRG16
~0IC41/-1
rJ.!!!- 01
DATA IN1
02
~
1151
.EZ!-
03
~
r---l!!...
22
29 420
24
30 420
0
0
0
0
0
0
016
017
0
0
0
~ 018
~ 019
f-!llL 029
~ 030
~
~
430
031
032
r--E2!- OUT1
SERIAL
1
l32
~ 03
.
r-!lli- 04
14 420
15 420
l29 16 420
231 17 420
I>
I>
I>
I>
r..lill... 014
0
0
~ 015
~ 016
~ 017
0
0
0
22
24
29 420
30 420
31 420
32 420
I>
I>
I>
I>
214
~ Q29
~ 030
~ 031
t-1l?L 032
216 31
1
SERIAL
~ OUT1
l30 32
232
1
SERIAL
~ aurz
0
0
SERIAL
~ aUT2
1
.
.
~ 01
~ 02
215
217
0
0
0
0
0
l30 32
420
SRG16
DATA IN2 2!!L
216
218 31
I>
2 420 I>
3 420 I>
4 420 I>
1
.,40IC431 + JJI ,.
I>
I>
I>
I>
31 420
32 420
,.
21
23
0
0
0
r
430
~
410
~ 04
I>
I>
I>
I>
231 19 420
...<"CD
~ 1>240
0
0
0
16 420
0
0
0
-<
-=*
CMOSIEL DISP
(PWR Q 1-032]
LATCH ENABLE ~ C42
C42
!> 240
SRG1S
DATA IN1
veC2
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
FUNCTION TABLE
CONTROL INPUTS
FUNCTION
»
<
»
:2
c
(')
m
:2
."
o
s:
CLOCK
LOAD
LATCH
H
=
high level; L
;
LATCH
ENABLE
No;
X
X
X
X
L
H
=
low level; X
SHIFT REGISTERS
LATCHES
R1 THRU R32
LC1 THRU LC32
Load and Shift t
No change
As determined above
=
irrelevant; ;
OUTPUTS
SERIAL
S01
S02
R31
R32
R31
R32
Stored data
R31
R32
New data
R31
R32
Determined by Latch Enable t
= low-to-high-Ievel
PARALLEL
01 THRU 032
LC 1 thru LC32 respectively
LC 1 thru LC32 respectively
transition
t Each even-numbered shift register stage takes on the state of the next-lower even-numbered stage and likewise each odd-numbered
shift register stage takes on the state of the next-lower odd-numbered state; i.e .. R32 takes on the state of R30. R30 takes on the state
of R28 •... R4 takes on the state of R2. R2 takes on the state of Data In 2. R31 takes on the state of R29. R29 takes on the state
of R27 •... R3 takes on the state of Rl. and Rl takes on the state of Data In 1.
tNew data enters the latches while latch Enable is high. These data are stored while Latch Enable is low .
:xJ
»
o
""""
:2
3-142
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN65567, SN65568, SN75567, SN75568
ELECTROLUMINESCENT DISPLAY COLUMN DRIVERS
ADVANCE
INFORMATION
logic diagram (positive logic)
vCC2----------------------------------------------------~
LATCH
ENABLE
SHIFT
REGISTER 1
CLOCK
OATAINl
LATCHES
OUTPUT
BUFFERS
C2
>--+--110
20
01
•
(I)
C2
~
20
02
CD
__ C
>
Q
>
IV
C2
20
03
Q.
(I)
is
C2
20
••
•
OATAIN2
••
•
SHIFT
REGISTER 2
•
••
•••
•
••
04
•
••
•
••
10
R2
C2
LC29
029
'---+-120
i=
C2
~~---------+_t20
LC30
030
LC31
031
....--------+--420
C2
032
SERIAL OUT2
TEXAS ."
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
~
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LC32
SERIAL oun
INSTRUMENTS
«
a:
C2
~.-----+_----------~20
z
o
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«
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«
3-143
SN65567, SN65568, SN75567, SN75568
ELECTROLUMINESCENT DISPLAY COLUMN DRIVERS
ADVANCE
INFORMATION
typical operating sequence
n nunUnl ••• J1JlJUlfU
. uu
CLOCK - - - ,
DATA IN
II
SR CONTENTS
VALID
IRRELEVANT
INVALID
VALID
LATCHENABLE ______________________________~r_lL
C
iii"
ii'
______________________
'C
LATCH
CONTENTS
________________________________
PREVIOUSLY STORED DATA
<
...C
~
______________________
__
NEW DATA VALID
VCC2 ________________________________~1
:c"
CD
iil
__
''''''''-----
QOUTPUTS __________________________________~I'~ VA_L_I_D__
"~____________
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL Q OUTPUTS
- - - - - -. . .-
..........-
TYPICAL OF SERIAL OUTPUTS
VCC2
OUTPUT
INPUT ___IVIII......41---41
~---4H~ OUTPUT
»
c
~
GND~~-------e~~~--
---e-~~4-~-GND
:2
(")
m
-
:2
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s:
»
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:2
3-144
TEXAS ..,
INSlRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
----.~~~-4-GND
ADVANCE
INFORMATION
SN65567, SN65568, SN75567, SN75568
ELECTROLUMINESCENT DISPLAY COLUMN DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8 V
Supply voltage, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 70 V
Input voltage, VI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. VCC1 +0.3 V
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2) . . . . . .. 1700 mW
Operating free-air temperature range: SN65567, SN65568 .................. -40°C to 85°C
SN75567, SN75568 ..................... OOCt070oC
Storage temperature range ......................................... - 65°C to 150 DC
Case temperature for 10 seconds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
NOTES:
1. Voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, derate linearly at the rate of 13.6 mW/oC.
~
·C
MIN
NOM
MAX
Supply voltage, VCC1
4.5
5
5.5
v
Supply voltage, VCC2
0
60
V
3.4
4.2
4.8
5.8
V
High-level input voltage, VIH
low-level input voltage, Vil
VCC1 - 4.5 V
VCC1 - 5.5 V
VCC1 = 4.5 V
-0.3
1.1
= 5.5 V
-0.3
1.3
VCC1
a output current, IOH
low-level a output current, IOl
a output clamp current, 10K
-15
High-level
5
mA
MHz
100
ns
100
ns
Setup time, data before clock t, tsu
50
ns
Hold time, data after clock' t, th
50
ns
Operating free-air temperature, T A
-40
0
60
Vips
85
70
°C
z
NOTE 3: VCC2 must be ramped only when data within the latches is stable.
electrical characteristics over recommended operating free-air temperature range, VCC1 .. 5 V
PARAMETER
High-level output voltage
VOL
low-level output voltage
TEST CONDITIONS
a outputs
IOH = -15 mA
MIN
MAX
57
Serial output
VCC2 = 60 V,
IOH = 100 pA
a outputs
IOl = 15 mA
8
Serial output
IOl = 100 pA
1
IIH
High-level input c,urrent
III
Low-level input current
VIH = VCC1
Vil = 0
ICC1
Supply current from VCC1
VI = VCC1
ICC2
Supply current from VCC2
VCC2 = 60 V
Q.
II)
is
V
Pulse duration, latch enable high, twllE)
SN65567, SN65568
SN75567, SN75568
>
(II
mA
20
Rate of rise of VCC2, dvldt (see Figure 3)
Q
mA
15
0
UNIT
Clock frequency, fclock
Pulse duration, clock high, tw(ClK)
VOH
•
~
recommended operating conditions
3.8
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
::?!
V
oLL
1
pA
pA
pA
0.5
0.5
~
V
-1
500
I Outputs low
I Outputs high
UNIT
o
mA
a::
Z
w
«
(.)
z
«
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c
«
3-145
SN65567, SN65568, SN75567, SN75568
ELECTROLUMINESCENT DISPLAY COLUMN DRIVERS
ADVANCE
INFORMATION
switching characteristics, VCC1 = 5 V, VCC2 = 0, TA = 25°C
PARAMETER
tpHL
tpLH
II
Propagation delay time, high-to-Iow leirel
Propagation delay time, low-to-high level
FROM
TO
INPUT
OUTPUT
TEST CONDITIONS
Serial
Clock
Out
Serial
Clock
Out
Delay time, VCC2 to Q output
Q
VCC2
MAX
ns
CL = 20 pF,
See Figure 2
140
ns
100
ns
= 60 V/JLs,
= 100 pF,
CL
See Figure 3
PARAMETER MEASUREMENT INFORMATION
CLOCK
I '--_ _ _- J I
I f - - twICLK)-----+t
If-tsu-+k-th--+t
.1
DATA IN
:
~
VALID
'KfYY)
V,,,,
VIL
FIGURE 1. INPUT TIMING VOLTAGE WAVEFORMS
~fO%
CLOCK _ _ _
»c
<
»
:2
-+I
I
SERIAL OUTPUT
m
-
:2
'T1
o
SERIAL OUTPUT
\ ----::~
~tPLH
1 r------- VOH
1.
1/ 50 %
-----+I..J- - - - - - - - V O L
I
1
~
(')
\4-tPHL
----"""""\~o:-
- - - - --
VOH
~---------VOL
FIGURE 2. VOLTAGE WAVEFORMS FOR PROPAGATION DELAY CLOCK TO SERIAL OUTPUT
::J:J
s:
»-I
o-
:2
3-146
TEXAS
UNIT
140
dv/dt
td
MIN
CL = 20 pF,
See Figure 2
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
·SN65567, SN65568, SN75567, SN75568
ELECTROLUMINESCENT DISPLAY COLUMN DRIVERS
ADVANCE
INFORMATION
PARAMETER MEASUREMENT INFORMATION
I, - 0.8!'. -+j
14-
VCC2 ____....l,r::~O~%----,\ - - - - - - :OVV
I
Id""*l
Q OUTPUT
k-,__-""\
U%VALIO '\ - - - ---::~
II..
III
FIGURE 3. VOLTAGE WAVEFORMS FOR DELAY TIMES. LATCH ENABLE TO Q OUTPUTS
II)
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Q.
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TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
3-147
II
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(1)
en
3-148
SN75581
GAS DISCHARGE DISPLAY DRIVER
02725. MARCH 1983
J ANON
•
Each Device Drives 7 Lines
•
150-V Output Voltage Swing Capability
•
TTL Compatible Inputs
•
Latches on All Driver Outputs
•
High-Speed Serially Shifted Data Input
•
Output Enable/Disable Function
•
Serial Data Output for Cascade Operation
•
DUAL-IN-LiNE PACKAGES
(TOP VIEW)
VCC+
01
NC
02
03
04
05
OUTPUT ENABLE
Shift Register Has Synchronous Clear
Function
CLOCK
LATCH ENABLE
DATA IN
VCC-
•
06
07
GND '-i.:'----';i-' SERIAL OUT
~
NC - No internal connection
(I)
>
·C
description
The SN75581 is a monolithic BIDFETt integrated circuit designed to drive a dot matrix or segmented display.
The output characteristics of this driver make it compatible to several display types including VF and DC
plasma displays.
Q
>
ca
Q.
UI
All device inputs are diode-clamped p-n-p inputs and, when left open, assume a high-logic level. The nominal
input threshold is 1.5 volts. Outputs are open-source DMOS transistors for excellent high-voltage
characteristics and reliability.
i5
The device consists of a 7-bit shift register, seven latches, and seven output AND gates. Serial data is
entered into the shift register on the low-to-high transition of the Clock input. When the Latch Enable input
is high, data is transferred from the shift registers to the latch outputs. When Latch Enable makes a highto-low transition with the Clock input high, the shift register is cleared. Taking the Output Enable input
high enables all Q outputs simultaneously. The Serial Output is not affected by the Output Enable input.
The SN75581 is characterized for operation from OOC to 70°C.
logic symbol:!:
OUTPUT (31
ENABLE (61
LATCH
ENABLE
logic diagram (positive logic)
OUTPUT E N A B L E - j l > - - - - - - - - - - - - - - .
TTL/GAS DISCH
DISPLAY
LATCH ENABLE-j>-.----------,
CLOCK--,~_--,
SRG7
2R
DATA I N - - - - t - + - - - l
Cl
3D
3D
3D
3D
3D
3D
3D
1>4 ~
1>4
4
1>4
1>4
1>4
1>4~
(161
(151
(141
(131
(12}
III}
(101
191
Ql
Q2
Q3
Q4
Q5
Q6
Q7
SERIAL
OUT
t BIDFET -Bipolar. double·diffused. N-channel and P·channel MOS transistors on same chip-patented process.
*This symbol is in accordance with ANSI/IEEE Std 91·1984 and lEe Publication 617-12.
PRODUCTION DATA d.cume.'. co.,.in
inl.,mlll.. cu,ra.' e. .1 publl.etl.n dele.
P,oducts co.Io,m ta .....ili.aIi••• , . Ih.
of Taxil Instruments Itandard
Ie,...
wlrranty.
Productl.. proc...ing d... not .......'lIy
include tasting af all parameters.
Copyright @ 1983. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 666012 • DAUAS. TeXAS 75265
3-149
SN15581
GAS DISCHARGE DISPLAY DRIVER
typical operating sequence
UUUlJUUU
CLOCK
DATA------------,-------~-----------------
IN
SHIFT
REGISTER
II
CONTENTS
IRRELEVANT
VALID
IRRELEVANT
------------.&..--------------'---------NEW DATA
LATCH _ _ _ _ _ _ _ _ _ _ _
ENABLE
CLEARED
n
1.._ _ _ __
~
.&. _____________
C
iii·
CONTENTS,
LATCH _______________________
PREVIOUSLY STORED DATA
"C
iii
<
OUTPUT
ENABLE
C
~
::::!.
<
~
Q
...
NEW DATA
---,
.&. ____
OUTPUTS _____....__
.&. __
PREVIOUS DATA
.:.VA:::LilliID~____
N_EW
__D_A_TA
__
VA_L_ID_
(I)
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL Q OUTPUTS
VCC+ - - -...- - -
----41.....- - VCC+
-----1.....- -
VCC+
OUTPUT
INPUT
VCC------~----
TYPICAL SERIAL OUTPUT
- . .- - 4.....- - OUTPUT
- - - - -.....- - GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC + (see Note 1) ............................................. 7 V
Supply voltage, VCC _ .................................................... -15 V
Differential supply voltage, V CC + - VCC - .................................... 18.7 V
Output current (one output) ............................................... -5.5 mA
Applied output voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. V CC + - 145 V
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
N package ........................................................ 1150 mW
J package ................................ '. . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
Operating free-air temperature range ...................................... ooC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............ 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ............ 260°C
NOTES:
1. Voltage values are with respect to network ground terminal.
2. For operation above 25·C free-air temperature, derate the J package linearly to 656 mW at 70·C at the rate of B.2 mW/·C
and the N package to 736 mW at 70·C at the rate of 9.2 mW/·C.
3-150
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN75581
GAS DISCHARGE DISPLAY DRIVER
recommended operating conditions
MIN
4.5
Supply voltage, Vcc +
-10.8
Supply voltage, VCCHigh-level input voltage, VIH
NOM
MAX
5
5.5
-12 -13.2
UNIT
V
V
V
2
Low-level input voltage, VIL
0.8
2
V
MHz
Clock frequency, fclock
Pulse duration, clock high, twICKH)
140
ns
Pulse duration, clock low, twiCKL)
320
ns
Pulse duration, latch enable high, twILEH)
250
ns
Pulse duration, output enable low, twIOEL)
3
Data before clock!
Clock high before latch enable!
Setup time, tsu
Data after clock!
Hold time, th
Operating
free~air
Clock high after latch enable.
p's
70
ns
75
70
ns
500
temperature, T A
0
70
•
DC
electrical characteristics over recommended operating free-air temperature range.
Vcc+ = 4.5 V to 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
=
-500 p.A
VOH
High-level output voltage, serial output
10H
VOL
Low-level output voltage, serial output
1010n)
On-state output current, Q outputs
1010fl)
Off-state output current, Q outputs
IIH
High-level input current
VCC+ = 5.5 V, 10L = 1.6 mA
VOH - VCC+ - 10V
VCC+ - 5.5 V, Va - -140 V
VI - 5.5 V
IlL
Low-level input current
VI
ICC+
ICC-
Supply current from VCC +
Supply current from V CC _
switching characteristics. CL
= 0.4 V
VCC+ - 5.5 V,
VCC+ = 5.5 V,
=
20 pF. TA
=
VCC- VCC-
=
Typt
2.4
4.7
0.15
-2
MAX
UNIT
V
0.4
-5.5
V
mA
5
5
p.A
p.A
50
p.A
-13.2 V
12
30
mA
-13.2 V
-11
-28
mA
Typt
MAX
UNIT
2.2
3
0.75
2
200
350
180
350
25 °C
TEST CONDITIONS
PARAMETER
MIN
MIN
Propagation delay time, high-to-Iow-Ievel
tpHL
tPLH
Q output from latch enable or
=
output enable
RL
Propagation delay time, low-to-high-Ievel
See Figure 4
25 kll,
Q output from latch enable or
p's
output enable
tpHL
tpLH
Propagation delay time, high-to-Iow-Ievel
serial data from clock
Propagation delay time,
low~to-high-Ievel
RL = 3 kll,
See Figure 5
serial data from clock
t All typical values are at V CC +
ns
5 V, VCC-
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-151
SN75581
GAS DISCHARGE DISPLAY DRIVER
PARAMETER MEASUREMENT INFORMATION
"
CLOCK
•
I+--twICKLI---t~...I·..----twICKHI---~
~
I
--""""""\\~_""---Jl
l4-'su ___th--.l
I
I
-"><
c
!
DATA IN _ _ _ _ _ _
0'
'C
j.
tou
2i'
-<
I
I
~".___~"!"""
1
~I.
iil
OV
i
I
j4--ftpxx *
I
:
sv
'L1~%-1
__ ;-------1-----------i
i
--+I
i i ! XI ! S"-~~---::
OUTPUT ENABLE
~
SERIAL OUT
I
tPHl~
I
Q
I
I
I
I
-----,
_ _ _ _ _ _ __
t~------------
LATCH ENABLE _ _ _ _ _ _ _ _ _ _ _
<
CD
5V
.wILEIlI---toI
~.....~IoI--th
..:.:---Ji
C
::!,
L::
\0%
I
~tPlH
\l I
OUTPUTS
I
I
!+-tpxx*
ov
I
-+I
I+- tpxx*....j
I
I
~
~
~~::
-VOH
-----VOL
'tpxx is tpHl or tPlH Iwhichever is appropriate)
FIGURE 3. VOLTAGE WAVEFORMS
Q OUTPUTS
--"---41-25kn
Vcc+
TEST POINT
TCl =
~3kn
20pF"
SERIAL OUTPUT
'='
~ TEST POINT
-130 V
I Cl
= 20pF"
'Includes probe and jig capacitance
FIGURE 4. Q OUTPUT LOAD CONDITIONS
"Includes probe and jig capacitance
FIGURE 5. SERIAL OUTPUT LOAD CONDITIONS
3-152
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 866012 • DALLAS. TEXAS 76285
ADVANCE
INFORMATION
SN751506, SN751516
DC PLASMA DISPLAY DRIVERS
03005. DECEMBER 19B6
SN751506 ... FT PACKAGE
ITOP VIEW)
•
Each Device Drives 32 Lines
•
1S0-V Open Drain Parallel Outputs
•
220-mA Parallel Output Sink Current
Capability
•
CMOS-Compatible Inputs
•
Strobe Input Provided
•
Serial Data Output for Cascade Operation
•
Inputs Have Built-in Electrostatic Discharge
Protection
description
The SN751506 and the SN751516 are
monolithic integrated circuits deSigned to drive
the scan lines of a dc plasma panel display. The
SN751516 pin sequence is reversed from the
SN751506 for ease in printed circuit board
layout.
Each device consists of a 32-bit shift register and
32 OR gates. Serial data is entered into the shift
register on the high-to-Iow transition of the clock
input. When the strobe input is low, all Q outputs
are in the off-state. Outputs are open-drain JFET
transistors with a breakdown voltage in
excess of 180 volts. The outputs have a
220-milliampere sink current capability in the on
state. Only one Q output should be allowed to
be in the on state at a time.
032
031
030
029
02B
027
026
025
024
023
022
021
020
019
018
017
NC
GND
NC
NC
CLOCK
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015
016
NC
GND
NC
STROBE
NC
VCC
NC
SERIAL OUT
VCC
NC
DATA IN
•
...enCD
>
';:;
Q
>
ca
is.
en
0
SN751516 ... FT PACKAGE
ITOP VIEW)
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015
016
NC
GND
NC
STR.OBE
NC
Serial data output from the shift register may be
used to cascade shift registers. This output is not
affected by the strobe input. All inputs are
CMOS compatible with ESD protection built in.
The SN751506 and SN751516 are
characterized for operation from OOC to 70°C.
VCC
NC
DATA IN
032
031
030
029
028
027
026
025
024
023
022
021
020
019
018
017
NC
GND
NC
NC
CLOCK
Z
0
j::
C
~
t>~
C
iii'
~
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•
••
C
:!!.
<
~
••
•
••
•
•
••
••
•
EN
(241
OATAIN
(11
(21
••
•
1331 016
(161
017
t>~
t>~
•
••
(21 031
(11 032
...
(II
(181
016
(331
017
t>~
t>~
(481
•
••
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
logic diagram (positive logic)
STROBE
r----..,Rl
F-+---r........) - - - - - - - 0 1
R2
32-BIT
STATIC
SHIFT
REGISTER
OATAIN
»
o
L-_ _ _~
m
2
-
o
2
3-154
28 OUTPUTS
(03 THRU 0301
NOT SHOWN
>------032
o
3:
»
::!
•
•
•
" ) - - - - - - - 031
~
2
"o:xl
>------02
•
•
•
~>_------ SERIAL
OUT
FUNCTION TABLE
FUNCTION
LOAD
STROBE
CONTROL INPUTS
CLOCK
•
No.
X
X
I
STROBE
X
X
L
H
SHIFT REGISTERS
Rl THRU R32
Load and shift t
SERIAL
No change
As determined above
R32
R32
OUTPUTS
01 THRU 032
Determined by STROBE
R32
All high impedance
R32
Rl thru R32
H = high level, L = low level, X = irrelevant, ! = high to low transition.
t R32 takes on the state of R31, R31 takes on the state of R30, ... R2 takes on the state of R1,
and R1 takes on the state of the data input.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DAl.LAS, TEXAS 76266
02
t>~
t>~
1241 SERIAL OUT
CLK
01
••
•
(47)
031
032
(251 SERIAL OUT
SN751506, SN751516
ADVANCE
INFORMATION
DC PLASMA DISPLAY DRIVERS
typical operating sequence
CLOCK~ • • •
DATAINt
-rJrlJlL1l.Jl________________________________
VALID
IRRELEVANT
---.,------------------------r-------------------------
•
SHIFTCONTENTS
REGISTER ____~_________________________L_____________________________ _
INVALID
VALID
STROBE
en
~
CD
OUTPUTS
VALID
OFF STATE
>
OFF STATE
'a::;
Q
t Only 1 bit in 32 should be low in the input data.
>
ca
Q.
schematics of inputs and outputs
en
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL Q OUTPUTS
VCC----------._----~._
is
TYPICAL OF SERIAL OUTPUT
- - - -.....~-----------VCC
__-4~VIr....~~OUTPUT
INPUT -JVVIr.....JVI/'r-.....
----~....----~-----GND
GND----~----------....~
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) ...................................... -0.4 V to 7 V
On-state Q output voltage, Va . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.4 V to 125 V
Off-state Q output voltage, Va ............ , ......................... -0.4 V to 180 V
Input voltage ............................................... - 0.4 V to VCC + 0.4 V
Serial output voltage .......................................... -0.4 V to VCC+O.4 V
Q output on-state time duration (see Note 2) " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 P.s
Q output duty cycle (see Note 2) ............................ .' ................. 1/200
Continuous total power dissipation at (or below) 25°C free-air
temperature (see Note 3) ............................................. 1025 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O°C to 70°C
Storage temperature range ......................................... -55°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 260°C
NOTES:
1. Voltage values are with respect to GND.
2. Only one Q output should be on at a time.
3. For operation above 25°C free-air temperature, derate linearly to 656 mW at 70°C at the rate of 8.2 mW/oC.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
z
i=
o
«
:!:
a:
o
u.
Z
w
(.)
z
«
>
o
«
3-155
SN751506, SN751516
ADVANCE
INFORMATION
DC PLASMA DISPLAY DRIVERS
recommended operating conditions
MIN
4
Supply yoltage, VCC
NOM
5
Peak on-state Q output voltage, VO(onl
High·level input voltage, V,H
3.2
VCC - 4 V
VCC = 6 V
0.8
1.2
Low-level input voltage, V,L
220
200
Clock frequency, f clock
ofij'
"Q
iii
<
o
Pulse duration, clock high or low, twCLK
Pulse duration, data, two
Pulse duration, strobe, twSTRS
Setup time, data before clockl, tsu
Hold time, data after clockl, th
Operating free-air temperature, T A
UNIT
V
V
V
4.S
VCC = 4 V
VCC - 6 V
Output current, 10 (TA = 25 ·CI
•
MAX
6
110
V
mA
kHz
1.5 t
5
ps
ps
2
1
1.2
po
po
ps
·C
0
70
:I,
~
t The minimum clock period is
;;
51's.
electrical characteristics. Vee - 5 V. TA - 25°e (unless otherwise noted)
VOH
PARAMETER
High-level output voltage
VOL
Low-level output voltage
1010ffi
IOL
Off-state output current
Low·level output current-
IIH
IlL
Ci
High-level input current
ICC
Supply current
TEST CONDITIONS
Serial out
Q outputs
MIN
4.5
10H = -0.1 mA
10L - 180 mA
IOL = 0.1 mA
Serial out
Q outputs
Q outputs
VOH = 110V
VOL = 16V
low-level input current
Input capacitance
TVP
MAX
6
10
0.5
1
220
V
itA
mA
VI = VCC
V, = 0
1
-1
15
All Q outputs off
1
40
One Q output on
UNIT
V
20
itA
itA
pF
mA
switching characteristics, Vee - 5 V. TA .. 25°e
»
c
~
2
(")
~
-
ted
PARAMETER
Propagation delay time, clock to serial output
tDHL
Delay time, high·to·low-Ievel Q output from strobe or clock inputs
tDLH
trHL
Delay time, low-to-high-Ievel Q output from strobe or clock inputs
Transition time, high-to-Iow-Ievel Q output
trLH
Transition time, low-to-high-Ievel Q output
TEST CONDITIONS
CL =15 pF
CL
=
RL = 470 II,
See Figures 2 and 3
* Typical values are for clock inputs. Typical times from strobe inputs will be less.
2
o"'::a"
s:
»
::!
o
2
3-156
150 pi:,
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
MIN
TVP
0.2
MAX
0.5
UNIT
ps
0.2*
0.6
I's
0.35*
0.1
1
0.3
po
pS
0.35
1
ps
SN751506, SN751516
ADVANCE
INFORMATION
CLOCK
DC PLASMA DISPLAY DRIVERS
~50%
f+ - - - - - --
\50%
50%
.1
I.--tWCLKH
It--twCLKL
t---lsuO ---+!.---thO ~
..,..
*".
~
4V
-1 V
--.I
*".
::
.1
two
•
f
CD
>
·c
FIGURE 1. INPUT TIMING VOLTAGE WAVEFORMS
CLOCK
INPUT
l'
--.J
LAST
PULSE
~5~-
-
-
-- ------------ -::
------------~I--~ ~---------------------------------VOH
SERIAL OUT ____________....;.I_ _
r
J~50%
Q
>CO
15.
II)
Q
~
I+-tWSTRB-+j
STROBE ------------.....;..:------------50-%"'~
",.5-0%----------- 4 V
tpd
14-- tOHL ~
tOLH -14-+1
14
.1 tOHL
------------~I--~~X--------~I~~-----wl~~------VOH
Q OUTPUT
I
90%
I
10%
j'!1
","-_~1.;.O%;;....;i\ 1
. -. . --
-------....;.I---~
f+-tOLH--.I
90%
II
tTLH·
14
1;;90%
1 0;;.;10;.:%:....____
1;-
VOL
....,....tTHL
FIGURE 2. SWITCHING CHARACTERISTICS
z
o
«~
~
a:
oLL
Z
W
(.)
z
«
>
c
«
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-157
SN75150l SI751516
ADVANCE
INFORMATION
DC PLASMA DISPLAY DRIVERS
PARAMETER MEASUREMENT INFORMATION
5V
NOTES: A. Input pulses are supplied by generators having the following characteristics: tw
tf '" 30 ns, Zo = 50 Il.
B. CL includes probe and jig capacitance.
TEST CIRCUIT
FIGURE 3
2
o"
:II
~
~
6
2
3-158
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Voo - 100V
=
1.25 ~s, PRR '" 200 kHz, tr '" 30 ns,
SN75150l SN751516
ADVANCE
INFORMATION
DC PLASMA DISPLAY DRIVERS
TYPICAL CHARACTERISTICS
LOW-LEVEL Q OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
LOW-LEVEL OUTPUT CURRENT Q OUTPUTS
vs
FREE-AIR TEMPERATURE
500
10
Vee = 5 V
IOL - 180 mA
>
I
II)
.ll!'"0
~
8
-I--
>
~
S-
6
!--
"
0
Gi
~
-'
Vee = 5 V
Vo - 16 V
~
I 400
-
-
E
~
c:"
300
"
Q.
~
r-- r--
o
Gi 200
4
!
~
~
.3
o
i'... 100
~ 2
o
>
9
o
o
o
10
20
30
40
50
60
70
80
o
10
20
60
70
80
0.5
26
Vee - -5 V
One Q
Output low
24
..f
.
Vee - 5 V
eL-15pF
0.4
z
E
o
j::
.!.
>
~ 0.3
22
"
CJ
~
Q.
20
r-- r--
I/)
I
CJ
S;
50
PROPAGATION DELAy TIME,
CLOCK TO SERIAL OUTPUT
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
g.
40
FIGURE 5
FIGURE 4
~
30
T A -Free-Air Temperature- °e
TA-Free-Air Temperature- °e
~
•
-- -
18
--- -
~
-
.~
& 0.2
~
a:
~
oLL
C1.
~
0.1
Z
o
o
. Q.
.
W
16
o
10
20
30
40
50
60
70
80
o
10
20
30
40
50
60
TA-Free-Air Temperature- °e
TA-Free-Air Temperature- °e
FIGURE 7
FIGURE 6
70
80
Z
~
o
.
<'
..
C
CD
III
a;
a;
c
a; 0.3
c
a; 0.3 ~
-
~
0.2
B
J:;
J:;
'"
J: 0.2
B
~
'"
.3
J: 0.1
I
...J
:z:
e
f.--
~
>
"
...J
.3
Vec - 5 V
CL = 150 pF
RL = 470 n
I
>
C
0.5
"-
t-
iii'
DELAY TIME,
LOW-TO-HIGH-LEVEL Q OUTPUT
vs
FREE-AIR TEMPERATURE
o
I 0.1
:z:
...J
e
o
10
20
30
40
50
60
T A - Free-Air Temperature -
70
o
80
o
°e
10
20
TRANSITION TIME,
HIGH-TO-LOW-LEVEL Q OUTPUT
vs
FREE-AIR TEMPERATURE
»
c
<
»
2
(")
m
2
."
o
::tI
3:
»
:::!
o
2
j.: 0.4
60
70
80
VCC = 5 V
CL = 150 pF
RL = 470 n
"
E
j.: 0.8
c
..,o
c
..
.2
·iii
.!::
~ 0.3
a;
~ 0.6
"
~
c
C
~
>
...J
~ 0.2
--
.3
B
:f 0.1
J:;
I
-
...J
--
-§,
i"
.3
20
30
40
50
60
T A - Free-Air Temperature -
70
......-
V
.......--
I
t"
10
0.2
~
:z:
...J
0
o
-
0.4
J:
:z:
t"
50
TRANSITION TIME,
LOW-TO-HIGH-LEVEL Q OUTPUT
vs
FREE-AIR TEMPERATURE
.. 1.0
"I
Vcc = 5 V
CL .. 150 pF
RL = 470 n
"E
40
FIGURE 9
FIGURE 8
.. 0.5
"I
30
TA-Free-Air Temperature- °c
80
0
o
°e
10
20
30
40
50
60
T A - Free-Air Temperature - °C
FIGURE 10
FIGURE 11
. TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • pALLAS, TEXAS 75265
70
80
SN751508, SN751518
ADVANCE
INFORMATION
DC PLASMA DISPLAY DRIVERS
02984. JANUARY 1987
SN75150S' ... FT PACKAGE
•
Each Device Drives 32 Lines
•
-120-V P-N-P Open-Collector Parallel
Outputs
•
High-Speed Serially Shifted Data Inputs
•
CMOS-Compatible Inputs
•
Strobe and Sustain Inputs Provided
•
Serial Data Output for Cascade Operation
(TOP VIEWI
Q1
Q2
Q3
Q4
05
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
015
Q16
GND
SUSTAIN
NC
LATCH ENABLE
NC
Q32
Q31
Q30
Q29
Q28
Q27
Q26
Q25
Q24
Q23
Q22
Q21
Q20
Q19
018
Q17
GND
NC
STROBE
NC
CLOCK
description
The SN751508 and SN751518 are monolithic
integrated circuits designed to drive the data
lines of a dc plasma panel display. The
SN751518 pin sequence is reversed from the
SN751508 for ease in printed circuit board
layout.
Each device consists of two 16-bit shift
registers, 32 latches, 32 OR gates, and 32
P-N-P open-collector output AND gates.
Typically, a 32-bit data string is split into two
16-bit data strings externally and then entered
in parallel into the shift registers on the high-tolow transition of the clock signal. A logic high
signal on the Latch Enable input transfers the
data from the shift registers to the inputs of 32
OR gates through the latches. Data present in
the latch during the high-to-Iow transition of
Latch Enable is stored. When the Strobe input
is high, the latch is masked and a high will be
placed on the data input of the output AND
gates. When the Strobe input is low, and the
Sustain input is high, data from the latches is
reflected at the outputs. A logic low signal on
the Sustain input will force all outputs to their
off state. Drivers may be cascaded via the serial
data outputs of the static shift registers. These
outputs are not affected by the Latch Enable,
Strobe, or Sustain inputs.
VCC
SERIAL OUT2
SERIAL OUT1
•
....CD
II)
>
'':::
C
>
ca
C.
II)
is
VCC
DATA IN2
DATA IN1
SN751518 ..• FT PACKAGE
(TOP VIEWI
Q1
Q2
Q3
04
Q5
06
Q7
Q8
Q9
Q10
Q11
Q12
013
014
015
Q16
GND
SUSTAIN
NC
LATCH ENABLE
NC
The SN751508 and the SN751518 are
characterized from ooe to 70°C.
VCC
DATAIN2
DATAIN1
Q32
Q31
Q30
Q29
Q28
Q27
Q26
Q25
Q24
Q23
Q22
Q21
Q20
019
Q18
017
GND
NC
STROBE
NC
CLOCK
Z
0
i=
«
::?!
a:
0
LL
Z
W
(.)
VCC
SERIAL OUT2
SERIAL OUT1
Z
«
>
C
«
NC-No internal connection.
ADVANCE INFORMATION d•• uments ••ntai.
=.::~;
. .::. .r:::..":'!'~~::,~~:Pst'l!
iIIta and oth., spacilications are subject t. cha.go
without natice.
TEXAS
~
INSTRUMENTS
POST OFFiCe BOX
~55012
• DALLAS, TEXAS 75265
Copyright © 1987, Texas Instruments Incorporated
3-161
SN751508, SN751518
ADVANCE
INFORMATION
DC PLASMA DISPLAY DRIVERS
logic symbols t
SN751508
SUSTAIN
ill.L
CMOS/El DlSP
EN44
STROBEill!- V43
LATCH ENABLE!WCLOCK
C42
J!!lJ::. I> zoo
SRG'S
,4D(C41J-1
J
r
DATA IN1 ~41D
l1
Z3
···
c
(ii'
3420
442D
iii'
<
C
t>
t>
t>
t>
l15
l17
··
~
1420
2420
15420
164Z0
22.
23'
17420
18420
t>
t>
t>
t>
~,01
43.44
02
43.44
43.440 ~ 03
43.44
~ 04
f---1ill'
···
43.44~ ~ 015
43.44l' ~ 0'6
017
43.44~
018
43.440
···
SRG18
:::2,
'-,40(C45/-1
ti
DATA INZ~~ 45D
iil
r
' 22
24
···
···
~ 02.
29420 t> 43.44{
30420 J> 43.44
31420 C> 43,44
!--------ill 030
t>
f---l!l 032
32420
l16
l18 31
43,44
1
~ 031
SERIAL
~ Dun
,
230
232
f---1.!!!
f---1.!!!
~ OUT2
SERIAL
32
SN751518
,.!.!!L-
CMOS/EL DISP
EN44
STROBE,!.W.- V43
.~
C42
LATCH ENABLE
CLOCK.~ 1>240
SUSTAIN
SRG16J
1:,40(C41J-1
DATA IN1.~ 4,D
»c
23
···
··
~
2
om
-
1 420
t>
2420
t>
43.44
43.44
3420 [> 43,44
I>
43.44
4420
l1.
l17
15420
16420
22.
231
17420
22
24
29420
30420
31 420
18420
t>
t>
t>
t>
··
SRG16
,40(C45/-1
2
DATA INZ!~ 45D
."
o:xl
s:
···
···
»
:::!
o
2
l1
r
32 420
l16
l18 3'
43.44~
43.44~
43.44~
43.440
···
~I02
~ 03
~,Q4
~ 01.
~,
~,017
a'.
~ 0'8
43.44
~ 02.
43.440 j---l!!!! 030
1>'43.44
~ 031
t> 43.440 --.!!!l 032
1
t>
t>
,
230
232
J----!!!,A'
32
SERIAL
--.!W Dun
SERIAL
-.illl OUT2
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
3-162
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN751508. SN751518
ADVANCE
INFORMATION
DC PLASMA DISPLAY DRIVERS
logic diagram (positive logic)
SUSTAIN
STROBE
LATCH
ENABLE
II
CLOCK
Q1
DATAIN1
II)
~
Q)
.~
~
Q
02
>
ca
Q.
II)
is
Q3
Q4
•
••
• ••••
• ••••
• ••••
•
•
•
•••
DATAIN2
029
2
Q30
o
~
Q31
~
a::
oLL
Q32
2
1...-_ _ _ _ _ _ _ _ _ _ _ _ _ _--1
1-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1
">---- SERIAL oun
">---
SERIAL OUT2
w
CJ
2
~
C
«
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
3-163
SN751508, SN751518
ADVANCE
INFORMATION
DC PLASMA DISPLAY DRIVERS
FUNCTION
LOAD
•
CLOCK
SUSTAIN
=
H
high level, L
LATCHES
LC1 THRU LC32
Determined by
Latch Enable
Stored data
New data
Determined by
X
X
X
X
X
X
No change
X
X
X
L
H
X
X
X
X
X
L
H
X
H
H
X
X
X
L
~
STROBE
SHIFT REGISTERS
R1 THRU R32
Load and shift t
No
LATCH
ENABLE
CONTROL INPUTS
LATCH
STROBE SUSTAIN
ENABLE
~
X
=
low level, X
=
irrelevant,
~
*
As determined above
*
Latch Enable *
As determined above
Latch Enable
Determined by
As determined above
=
OUTPUTS
SERIAL
S01 S02
R31
R32
R31
R32
R31
R32
R31
R32
Q1 THRU Q32
Determined by
Sustain and Strobe
Determined by
Sustain and Strobe
LC 1 thru LC32
All on (high I
All off
high-to-Iow transition
t Each even-numbered shift register stage takes on the state of the next-lower even-numbered stage, and likewise each odd-numbered
shift register stage takes on the state of the next-lower odd-numbered stage; i.e:, R32 takes on the state of R30, R30 takes on the state
of R28, ... R4 takes on the state of R2, R2 takes on the state of Data In2, R31 takes on the state of R29, R29 takes on the state of
R27, ... R3 takes on the state of Rl, and Rl takes on the state on Data In1.
New data enters the latches while Latch Enable is high. This data is stored while Latch Enable is low.
*
typical operating sequence
CLOCK
DATA IN
~ •••
1Jl'--___________
VALID
IRRELEVANT
~--~------~--------------
SHIFT - - - - - - - - - , - - - - - - - - - - - - REGISTER
INVALID
VALID
CONTENTS---------~-------------
n
LATCH ENABLE
--------~~---------LATCH CONTENTS PREVIOUSLY STORED DATA
I
NEW DATA VALID
STROBE
l>
SUSTAIN
C
~
2
QOUTPUTS
OFF-STATE
I I
VALID
om
2
-n
o
::u
s:
l>
-I
(5
2
3-164
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TeXAS 75265
OFF STATE
SN751508. SN751518
ADVANCE
INFORMATION
DC PLASMA DISPLAY DRIVERS
schematics of inputs and outputs
EQUIVALENT OF EA.CH INPUT
vcc--------~~--~~~
INPUT -'V".,.. . .J\I\,.,......
TYPICAL OF ALL Q OUTPUTS
-r
TYPICAL OF SERIAL OUTPUT
----~~~--------VCC
VCC2
--LOUTPUT
II
"'--4>JV""'''_~ OUTPUT
----__~----~-----GND
GND----~--------~~~
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.4 to 7 V
On-state Q output voltage, VO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -120 V to VCC +0.4 V
Input voltage ............................................... -0.4 V to VCC+O.4 V
Serial output voltage .......................................... -0.4 V to VCC+O.4 V
Continuous total power dissipation at (or below) 25°C free-air temperature
(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
Operating free-air temperature range ...................................... ooc to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 260°C
NOTES: 1. Voltages values are with respect to GND.
2. For operation above 25°C free-air temperature, derate linearly to 656 mW at 70°C at the rate of 8.2 mW/oC.
:2
o
t=
UNIT
4.5
4.6
-1.2
rnA
17
25
3
15
/LA
/LA
pA
rnA
pF
t All typical values are at T A = 25°C.
switching characteristics Vee - 5 V, TA - 25°e (unless otherwise noted)
tDd
PARAMETER
Propagation delay time, Clock to Serial Out
TEST CONDITIONS
CL=15pF
Or Strobe
tDLH
Delay time, low-to·high-Ievel Q output from Sustain
tDHL
Delay time, high-to-Iow-Ievel Q output from Sustain or Strobe
tTLH
tTHL
Transition time, low-to-high-Ievel Q output
Transition tinie,- high-to-Iow-Ievel Q output
CL=15pF,
RL = 91 kll,
See Figures 1 and 2
tTypical values for delay times are measured from the Sustain input.
3-166
-
TEXAS . "
INSTRUMENTs
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
MIN
TVP
100
MAX
150
UNIT
ns
0.3 t
1
I'S
1t
2.5
2
11
5
18
J'S
I's
I's
SN751508, SN751518
ADVANCE
INFORMATION
DC PLASMA DISPLAY DRIVERS
PARAMETER MEASUREMENT INFORMATION
~------------------4V
CLOCK
,
'--_J_ - - - ________
I"------.J
-1 V
.,1 tw--l
t+-tsU-+th-+j
I---tw
on.,.
J
•
! ~"""'------";"''''~'l..0_%
_____________________ : :
14- twf---+l
,!-+\-t
pd
SERIAL OUT
------------+i. .)(~-------....,..."'~~o-%---------------------VOH
_________---:,...J.
.
.
j4- tsu""",
---------________
j4-tsu~
j4-tw-*l
I
n~%-
LATCH ENABLE
____________.J.
-----------------------VOL
'1...
I
.
1 V
I
r-tsu-t>!
j4-
I*-tw~
I
tw-+j
I
--------------~I--~I
I . I
STROBE
I
I
I
I
I
~tsu1
________________-J.
I
/~---4V
50%
1 _ _ _ _ _ _ _ _.J.
r-
I
.l\....li \
I -./
-.IIn~I-Y:
tTLH-t>f
j.-
_
-1 V
Y""\i"------4V
~
I
I tOLH.j 14- I tOHL ~ It- I
tOLH..j I-~tOHL ~
Q OUTPUTS ___________________
_
: . tw--r-tw-4
1:
SUSTAIN
4V
I I.
tTLH~ ~
I
1V
K1\ n,:---:
I I
I
tTHL"
I
!'-tOLH
I, -+I
-tt
It-
tTLH
If-tTHL
14-
NOTE: Input tr and tf are less than or equal to 10 ns.
FIGURE 1. INPUT TIMING AND SWITCHING TIME VOLTAGE WAVEFORMS
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS. tEXAS 15265
z
i=
o
]
';:
Q
U
II)
I
u
E
VCC - 5.5 V
5 -All Q outputs low
o
o
No load
I
10
20
-elf
I
30
40
50
60
70
10
80
1r
F
20
FIGURE 3
.3
~ 0.3
:s
o
~
.
- -
g
80
:r
I-
.:
- 0.5
'ii
>.!!! 0.1
c!
f---l---+---+---+---f--+---+----j
....I
:r
51
o
o
10
20
30
40
50
60
70
80
oLL
2:
C
I
2
o
i=
~
o
i=
:r
....
70
"" 1.5 I-~---+---t---+---ll--t---+----i
.S!'
E
51
60
Vee - 5 V
Cl - 15 pF
Rl - 91 kll
~
~
~~
50
2r--.---r--'---.--'r-~---r--'
I
""
~
40
DELAY TIME. SUSTAIN INPUT TO Q OUTPUT.
HIGH TO LOW
vs
FREE-AIR TEMPERATURE
~
0.5
I
.S!'
g
30
FIGURE 4
DELAY TIME. SUSTAIN INPUT TO Q OUTPUT.
LOW TO HIGH
vs
FREE-AIR TEMPERATURE
Vee - 5 V
-Cl-15pF
:r 0.4 _Rl - 91 kll
i:5
TA-Free-Air Temperature-·C
TA -Free-Air Temperature-·e
~
>
ca
13.
II)
Vee - 5 V
O~~
o
__
10
~
___ L_ _
20
30
~_ _~~_ __L~
40
50
60
TA -Free-Air Temperature-·e
TA -Free-Air Temperature- ·e
FIGURE 5
FIGURE 6
70
80
w
o
2:
c
-----------,
m
LATCH
ENABLE
LATCH ENABLE
BLANKING (13)
SHIFT
LATCHES
OATAIN
CLOCK_--"
(12)
20t>
3
20t>
3
C
20t>
3
't:S
20 t>
3
20t>
3
fii'
ii'
<
20 t>
3
C
20 t>
3
<
20 t>
3
20 t>
3
:::!.
..
CD
In
(II)
(10)
(9)
(8)
(3)
(2)
(1)
(18)
(17)
(16)
Ql
02
Q3
Q4
os
06
Q7
as
Q9
Ql0
SERIAL DATA OUT
t This symbol is in accordance with ANSI/IEEE Std 9 I -1984 and
IEC Publication 617-12.
Pin numbers shown are for the N package.
FUNCTION TABLE
CONTROL INPUTS
FUNCTION
LOAD
LATCH
BLANK
H
= high
CLOCK
LATCH BLANKENABLE
ING
SHIFT REGISTERS
Rl THRU Rl0*
LATCHES
LCI THRU LC10
OUTPUTS
SERIAL
01 THRU 010
X
Load and shift
Determined by Latch Enable §
RIO
Determined by Blanking
X
X
X
Determined by Blanking
Determined by Blanking
X
X
No change
Determined by Latch Enable §
As determined above Stored data
As determined above New data
RIO
L
H
X
X
H
As determined above
Determined by Latch Enable §
RIO
All L
X
X
L
As determined above
Determined by Latch Enable §
RIO
LC I thru LC I 0 respectively
t
X
Not
X
level, L
= low level,
X
= irrelevant,
*
RIO
RIO
Determined by Blanking
t = low-to-high-Ievel transition.
*Register RIO takes on the state of R9, R9 takes on the state of R8 ... R2 takes on the state of Rl, and Rl takes on the state of the data input.
§ New data enter the latches while Latch Enable is high. These data are stored while Latch Enable is low.
3-172
TEXAS
,e,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TL4810BI, TL4810B
VACUUM FLUORESCENT DISPLAY DRIVERS
typical operating sequence
CLOCK
DATA IN
VALID
LATCH
CONTENTS
VALID
INVALID
SR CONTENTS
LATCH
ENABLE
IRRELEVANT
____________________
~r1~
PREVIOUSLY STORED DATA
______________
NEW DATA VALID
•
BLANKING
Q OUTPUTS
VALID
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
VDD--~------------~~
TYPICAL OF ALL OUTPUTS
VBB (Q OUTPUTS I
-------~--- VDD (SERIAL OUTPUTI
INPUT--........- . - - -..
100
OUTPUT
--~1l
~VSS
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
3-173
TL4810BI; TL4810B
VACUUM FLUORESCENT DISPLAY DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
•
Logie supply voltage, VDD (see Note 1) ......................................... 18 V
Driver supply voltage, VBB . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. 70 V
Output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. 70 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to VDD + 0.3 V
Continuous total dissipation at 25°C free air-temperature (see Note 2):
DW package ........................................................ 11 50 mW
N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 875 mW
Operating free-air temperature range: TL481 OBI .......................... - 40°C to 85 °C
TL4810B ............................. OOC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 260°C
C
iii·
"0
ii"
-<
NOTES: 1. Voltage values are with respect to VSS.
2. For operation above 25
free-air temperature, refer to the Dissipation Derating Table.
ac
C
DISSIPATION DERATING TABLE
::::!.
<
CD
;;
POWER
DERATING
ABOVE
RATING
FACTOR
OW
1150
9.2 mWloC
TA
25 DC
N
875
7.0 mWloC
25°C
PACKAGE
recommended operating conditions
TL4810BI
PARAMETER
MIN
NOM
TL4810B
MAX
MIN
NOM
MAX
Supply voltage, VOO
4.75
15.75
4.75
15.75
Supply voltage, VBB
5
60
5
60
Supply voltage, VSS
High-level input voltage, VIH
0
I for VOO
I for VDD
Low-level input voltage, VIL
= 5 V
- 15 V
V
V
V
3.5
5.3
3.5
13.5
15.3
13.5
5.3
15.3
V
0.8 -0.3 T
0.8
V
25
mA
DC
-0.3 T
Continuous high-level output current, IOH
Operating free-air temperature, T A
0
UNIT
-25
-40
85
0
70
t The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for logic
voltages only.
3-174
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75266
TL4810BI, TL481 DB
VACUUM FLUORESCENT DISPLAY DRIVERS
electrical characteristics over recommended operating free-air temperature range. Voo
VBB = 60 V. VSS = 0 (unless otherwise noted)
PARAMETER
High-level
VOH
output
voltage
low-level
VOL
output
voltage
Q
outputs
10H =
VDD = 5 V,
-25 rnA
Serial output
Q outputs
=
High-level input current
IBB
Supply current from VBB
57.5
58
4.5
14.7
4
4.5
14
14.7
MAX
0.5
1
0.05
0.1
VDD-15V,
10l = 100~
Blanking input at VDD,
0.02
0.1
0.02
0.1
Va
TA
= MIN to
= 60 V,
= 85 DC
= 0,
= MAX
2.5
70°C
3.7
...CD
3.7
CI)
2
-1
-15
-1
-15
~A
>
30
50
30
50
~A
0.5
1
0.5
2.7
4
2.7
1
4
Q.
rnA
VI - VDD
to MAX
>
';:
C
Blanking input at VDD,
= 0 DC
V
rnA
Blanking input at VDD,
All outputs high, T A
2.5
UNIT
V
1
All outputs high, TA -
Supply current from VDD
TYP*
58
0.1
All outputs low
IDD
MIN
0.5
Vo
IH
4
14
TL4810B
MAX
0.05
TA
10(off) Off-state output current
57.5
~A
10H = -100~
Blanking input at VDD
1 ~A,
TYP*
10L - 100 ~
Low-level Q output current TA
(pull-down current)
-100
MIN
VDD - 5 V,
10H
Serial output
10H -
VDD - 15V,
Va - 60 V,
10L
TL481 OBI
TEST CONOITIONSt
= 5 V to 15 V.
- 40 DC
CO
CI)
C
5
All inputs at 0 V,
VDD - 5 V
10
50
10
50
One Q output high
VDD - 15V
10
100
10
100
All inputs at 0 V,
VDD - 5 V
10
50
10
50
All outputs low
VDO - 15 V
10
100
10
100
~A
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
= 25 DC, except for 10.
*All typical values are at TA
timing requirements over recommended operating free-air temperature range
VDO = 5 V
MIN
MAX
PARAMETER
VOD - 15V
MIN
MAX
UNIT
tw(CKH)
Pulse duration, clock high
250
50
ns
tw(LEH)
Pulse duration, latch enable high
tsu(DI
Setup time, data before clock;
250
125
50
25
ns
ns
th(Dt
Hold time, data after clock;
125
25
ns
tCKH-LEH
Delay time, clock; to latch enable high
125
25
ns
switching characteristics. VBB
=
60 V. T A
PARAMETER
MIN
Propagation delay time, latch enable to output
TYP
MAX
VDD = 5 V
VDD = 15V
TEXAS .."
INSTRUMENTS ,
POST OFFICE BOX 655012 • DAllAS. TEXAS 75266
0.5
3-175
TL481DBI, TL481 DB
VACUUM FLUORESCENT DISPLAY DRIVERS
PARAMETER MEASUREMENT INFORMATION
-----1
CLOCK
VIL
I
tsu(DI
~-r--r_
DATA
I
I
~O%
C
iii"
.1
.j.
14
I
-----------VIH
LAST
CLOCK 50%
VIL
I PULSE
INPUT
j4-tCKH.LEH-..r
tw(LEHI
.!
th(DI
ENABLE-----....;.;~I
VALID 5 0 % X X X X VIL
\50% -
-
VIH
VIL
I4-tpd---+l
VIH
OUTPUT __________________9_0J%~r-V-A-Ll-D~~
FIGURE 1. INPUT TIMING
"C
50%1
LATCH
FIGURE 2. OUTPUT SWITCHING TIMES
iii
-<
..
C
THERMAL INFORMATION
:C!"
CD
N PACKAGE DUTY CYCLE
OW PACKAGE DUTY CYCLE
iil
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
100
\
90
"#.
.!!
u
>-
SO
S
,.E
70
\ 1\\
\
U
Q
E
.
';c
::i!:
100
N= 1 to 6
90
r\\ .I
"#.
N-S 1
.,
~ N-9~
U
>-
>-
5
E
VBS - 60 V
VOO - 15 V
IOH - -25 mA
50 IOL - 1 p,A
N - Number of outputs high
All other outputs low
40
~
~
~
H
70
Q
:::I
60
~
SO
U
N-JO
~
N -1 to 4
N-5
N-7,
.6><
.
60
::i!:
50
__- L__L_~_ _- L__~__L _ _ J
35
45 55
65
75 S5
95 100
40L-~
~
T A - Free-Air Temperature -
~
100
25
·C
T A - Free-Air Temperature -
FIGURE 3
3-176
FIGURE 4
.
TEXAS'"
INSTRUMENTS
POST OFFice BOX 655012 • DALLAS, TeXAS 75265
·C
TL58121, TL5812
VACUUM FLUORESCENT DISPLAY DRIVERS
D2914, OCTOBER 1985-REVISED AUGUST·1986
N
DUAL-IN-L1NE PACKAGE
(TOP VIEWI
•
Drives Up to 20 Lines
•
70-V Output Voltage Swing Capability
•
40-mA Output Source Current Capability
•
High-Speed Serially-Shifted Data Input
•
CMOS-Compatible Inputs
•
Direct Replacement for Sprague UCN5812A
VBB
SERIAL DATA OUT
020
019
018
017
016
015
014
013
012
011
description
The TL58121 and TL5812 are monolithic
BIDFETt integrated circuits designed to drive a
dot matrix or segmented vacuum fluorescent
display (VFO), Each device features a serial data
output to cascade additional devices for large
display arrays.
The TL58121 is characterized for operation from
-40°C to 85°C. The TL5812 is characterized
for operation from OOC to 70°C.
01
02
03
04
05
06
07
08
09
010
BLANKING
II.
(I)
CD
>
".:::
Q
LATCH ENABLE (STROBE)
Q.
(I)
FN PACKAGE
(TOP VIEWI
4
018
017
016
015
014
013
012
3 2
>
CO
CLOCK
VSS
A 20-bit data word is serially loaded into the shift
register on the low-to-high transition of the clock
input. Parallel data is transferred to the output
buffers through a 20-bit O-type latch while the
Latch Enable input is high and is latched when
the Latch Enable input is low. When the blanking
input is high, all outputs are low.
The outputs are totem-pole structures formed by
n-p-n emitter-follower and double-diffused MaS
(OM OS) transistors with output voltage ratings
of 70 volts and a source-current capability of 40
milliamperes. All inputs are CMOS compatible.
VDD
DATA IN
0
1 2827 26
25
6
24
8
22
9
10
21
23
20
11
19
02
03
04
05
06
07
08
12131415 161718
.- (!)
~
(I)~
ZUlU
wO
0')
al~d
d>o
ad
~
....J
::1:
....J
al
U
cr
I-
~
w
....J
al
«
Z
w
:r
U
I-
«....J
t BIDFET -
Bipolar, double-diffused. N-channel and P-channel MOS transistors on the same chip - patented process.
Copyright © 1985, Texas Instruments Incorporated
PRODUCTION DATA documents contain information
current 8S of publication data. Products conform to
specifications par the tarms of Taxas Instruments
:~~::~~i~8ir::1~1e ~:~~:i:; :,iO::::::~::'~S not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
3-177
TL58121, TL5812
VACUUM FLUORESCENT DISPLAY DRIVERS
logic symbol t
CMOSIVAC
FLUOR OISP
BLANKING 1131
LATCH 1161
ENABLE
11
EN3
C2
CLOCK _1_1_51_--t:>
OATAIN~I~2~71~-{~==~~~~~
C
iii'
'0
20 C>
3
<
20 C>
3
20 C>
3
20 C>
3
iii
1261
1251
1171
1121
Q1
Q2
Q10
Q11
C
::2,
<
Cil
CD
141
131
121
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
BLANKING------Q
LATCH E N A B L E - - - - - - - - - ,
SHIFT
REGISTER
LATCHES
OATAIN---f
CLOCK--'--I>
3-178
TEXAS
..II
INSTRUMENTS
POST OFFICE BOX &56012 • DALLAS. tEXAS 76285
Q19
Q20
SERIAL
OUT
TL58121. TL5812
VACUUM FLUORESCENT DISPLAY DRIVERS
FUNCTION TABLE
CONTROL INPUTS
FUNCTION
CLOCK
ENABLE
ING
X
X
X
X
X
X
Nol
X
X
X
X
LATCH
BLANK
::=
BLANK·
1
LOAD
H
LATCH
high level, L
::=
L
H
X
X
OUTPUTS
SHIFT REGISTER
LATCHES
Rl THRU R20
LCl THRU LC20
SERIAL
Load and shifti
Determined by
R20
Ql THRU 020
Determined by
No change
Latch Enable §
R20
Blanking
As determined above
Stored data
R20
Determined by
As determined above
New data
R20
Blanking
H
As determined above
Determined by
R20
All L
L
As determined above
Latch Enable §
R20
LC 1 thru LC20, respectively
low level, X = irrelevant, i
= low-to-high-Ieve!
II
transition.
...CLl
I/)
:t:R20 takes on the state of R19 , R19 takes on the state of R18, ... R2 takes on the state of Rl, and Rl takes on the state of the data input.
§New data enter the latches while Latch Enable is high. These data are stored while Latch Enable is low.
>
';:
typical operating sequence
C
>
co
CLOCK
C.
I/)
DATA IN
SR
CONTENTS
I
INVALID
____________________________
LATCH
ENABLE
LATCH
CONTENTS
C
IRRELEVANT
VALID
PREVIOUSLY STORED DATA
VALID
~rl~
____
NEW DATA VALID
BLANKING
Q OUTPUTS
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
VCC1---------.----~._~---
TYPICAL OF ALL Q OUTPUTS
- - - -.....- - - VCC2
"""--4......
OUTPUT
INPUT - -..........
GND--._------~--~._._---
TYPICAL OF SERIAL OUTPUT
- - - -.....- - - GND
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
t-----...-OUTPUT
- - - - - - - -__-4~-------GND
3-179
TL58121, ,TL5812
VACUUM FLUORESCENT DISPLAY
DRIVER~
absolute maximum ratings over free-air operating temperature range (unless otherwise noted)
Supply voltage, Voo (see Note 1) , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 V
Supply voltage, VSS ....................... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 70 V
Output voltage, VO ........................ ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 70 V
Input voltage, VI ............................................. -0.3 V to VOO+0.3 V
Output current, 10 ...................................................... - 40 rnA
Continuous total power dissipation at (or below) 25°C free-air temperature (see Note 2):
N package ....... ' ........................._.. '. . . . . . . . . . . . . . . . . . . . . . .. 1150 mW
FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1400 mW
Operating free-air temperature range:
TL58121. ...................................................... -40°C to 85°C
TL5812 .......................................................... OOC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 260°C
c
0"
"1:'
iii
"<
NOTES
...:cr
C
CD
ii1
1. All voltage values are with respect to VSS.
2. For operation above 25°C free-air temperature, derate the N package linearly to 598 mW at 85°C or to 736 mW at 70°C
at the rate of 9,2 mW/oC, Oerate the FN package to 728 mW at 85°C or to 896 mW at 70°C at the rate of 11-2 mW/oC .
recommended operating conditions
Supply voltage, Voo
MIN
4,5
Supply voltage. VBB
0
NOM
Supply voltage, VSS
VOO-1.5
-0.3
V
60
V
Low-level input voltage, V,L
V
VOO+O.3
0,8
High-level output current, 10H
40
1 TL58121
r TL5812
UNIT
15
0
High-level input voltage. VIH
Operating free-air temperature, T A
MAX
-40
85
0
70
V
V
mA
°C
t The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for logic
voltage levels,
electrical characteristics over operating free-air temperature range, VDD - 5 V to 15 V, VSS - 60 V
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
Q outputs
VOH
High-level output voltage
Serial outputs
Q outputs
VOL
"H
',L
10L
Low-level output voltage
Low-level input current
Low-level output current (pull down current)
Off-state output current
'BB
Supply current from VBB
100
Supply current from VOO
10H -
VOO - 15 V,
10H - -20 ~A
Blanking at VOO
= 1 mA,
VOO - 5 V,
VOO
= 15 V,
V, = VOO
V, - 0
Va - 60 V,
Va = 0,
Outputs high
VOO
58.2
4.9
14,5
14.9
0.7
MAX
'OL - 20,.A-
0.03
0.3
Blanking at VOO
Blanking at VOO
~
INSTR,UMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 76265
2,5
UNIT
V
1.5
0,3
=5 V
= 15 V
TEXAS
Typt
0.06
Outputs low
VOO
MIN
57.5
4.6
'OL - 20·,.A-
t All typical characteristics are at T A = 25°C.
3-180
20,.A-
VOO - 5 V,
10L
Serial outputs
High-level input current
'0(011)
= -25 mA
10H
0,3
1
-0.3
-1
3.2
V
~A
~A
mA
<-1
3,5
-15
0,02
0.5
1-5
3
1.7
4
8
~A
mA
mA
TL58121. TL5812
VACUUM FLUORESCENT DISPLAY DRIVERS
timing requirerrlents over operating free-air temperature range
PARAMETER
Pulse duration, clock high
twLEH
Pulse duration, latch enable high
tsuo
thO
tCKH-LEH
MIN
voo
twCKH
100
=
500
100
5V
VOO - 15 V
VOO - 5 V
VOO
=
VOO VOO
Oelay time, clockt to latch enable high
Vaa -
60
=
ns
75
15 V
150
5V
ns
75
TA == 25°C
PARAMETER
tpd
ns
150
VOO - 15 V
V.
ns
75
15 V
MIN
Propagation delay time,
Voo = 5 V
latch enable to output
VOO-15V
UNIT
ns
150
VOO - 5 V
Hold time, data after clockt
MAX
500
5V
VOO - 15 V
VOO
Setup time, data before clockt
switching characteristics.
=
TYP
.2.2
0.8
MAX
•
I!!
II)
>
';:
C
>
CO
C.
CI)
is
PARAMETER MEASUREMENT INFORMATION
CLOCK
I
~tsuD-+l_~thD-"d
I
I
I
---_ I
DATA _ _ _ _)(50%
VIH
}(""5_0_%_ _ _ _ VIL
FIGURE 1. INPUT TIMING
CLOCK
I
I4tCKH-LEH+!
jf-twLEH
-+t
I
LATCH
~
I
I
ENABLE _ _ _ _ _ _..1 : 50%
"'5_°°_10_ _ _ __
I4---t d ---+II
p
OUTPUT
FIGURE 2. OUTPUT SWITCHING TIMES
TEXAS
~
INSIRUMENTS
POST OFFICE BOX 655012 • DAUAS. TEXAS 76285
3-181
TL58121, TL5812
VACUUM FLUORESCENT DISPLAY DRIVERS
THERMAL INFORMATION
DUTY CYCLE
vs
FREE-AIR TEMPERATURE
100r--'~~~u-~~r-",-'~~~~
90~~~~~~~~~~~~~--~
SO~~~~~~~~~~~~~~
11I
.!!
C
iii'
'C
Di
<
C
:::!.
..
<
CD
!II
70~~~~~~~~~~~~~~
~ 60r-~~~~~~~~~~~~~
~ 50r-~---+---P~~~~~~
Q
E
.§..
~
40r-~---+--~--+-~~~~
30
conducting IOH -
- 25 m~
20 All other outputs low. IOL - 1 mA
10 VSB - 60 V
VOO - 15 V
__-L__
__
__
OL-~
W
~
~~~-L
~
~
~
ro
~
~
T A - Free-Air Temperature- °C
FIGURE 3
3-182
L-~
~
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
100
UCN4810A
VACUUM FLUORESCENT DISPLAY DRIVER
02676. OCTOBER 1982-·REVISEO NOVEMBER 1986
•
N
Each Device Drives 10 Linlls
DUAL-IN-L1NE PACKAGE
•
60-V Output Voltage Rating
•
40-mA Output Source Current
•
High-Speed Serially-Shifted Data Input
•
CMOS-Compatible Inputs
•
Latches on All Driver Outputs
•
Designed to be Interchangeable with
Sprague UCN4810A
(TOP VIEW)
08
07
06
CLOCK
VSS
VDD
LATCH ENABLE ISTROBE)
05
04
description
09
010
SERIAL DATA OUT
VBB
DATA IN
BLANKING
01
02
03
•
~
The UCN481 OA is a monolithic BIOFET t integrated circuit designed to drive a dot matrix or segmented
vacuum fluorescent display (VFO). This device features a serial data output to cascade additional devices
for large display arrays_
A 10-bit data word is serially loaded into the shift register on the positive-going transitions of the clock.
Parallel data is transferred to the output buffers through a 10-bit Ootype latch while the latch enable input
is high and will be latched when the latch enable is low. When the blanking input is high, all outputs are low.
~
';:
Q
>
ca
Q.
en
C
Outputs are totem-pole structures formed by n-p-n emitter-follower and double-diffused MaS (OMOS)
transistors with output voltage ratings of 60 volts, and 40 milliamperes source-current capability. All
inputs are compatible with CMOS and TTL levels, but each requires the addition of a pull-Up resistor to
VOO when driven by TTL logic.
The UCN4810A is characterized for operation from O°C to 70 o C.
logic symbol:!:
logic diagram (positive logic)
BLANKING
CMOS/
LATCH------------,
ENABLE
SHIFT
LATCHES
REGISTER
LATCH ENABLE (7)
BLANKING (13)
DATA IN
CLOCK
(12)
2D t>
3
2Dt>
3
2Dt>
3
2D t>
3
2Dt>
3
2D t> 3
2D[>
3
2D t> 3
2D t>
3
(11)
(10)
(9)
(8)
(3)
(2)
(1)
(18)
(17)
(16)
01
Q2
Q3
04
05
Q6
07
QB
09
010
SERIAL DATA OUT
t BIDFET - Bipolar Double-Diffused. N-Channel and P-Channel MOS transistors on same chip - patented process.
tThis symbol is in accordance with ANSI/lEEE Std 91-1984 and IEC Publication 617-12.
PRODUCTION DATA .....uma.ts ""ntai. inform.tion
currant as of publicatio. data. Praducts conform to
specifications par the terms of TaXB. Instrumants
=~~i~ai:ru"'i ~~i:~i:r lIr:.e;::~~~s not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Copyright © 1982, Texas Instruments Incorporated
3-183
UCN4810A
VACUUM FLUORESCENT DISPLAY DRIVER
FUNCTION TABLE
CONTROL INPUTS
FUNCTION
t
LOAD
LATCH
BLANK
BLANK-
OUTPUTS
SHIFT REGISTERS
LATCHES
R1 THRU R10
LC1 THRU LC10 t
SERIAL
Q1 THRU Q10
ENABLE
ING
X
X
X
X
X
X
Load and shift*
Determined by Latch Enable t
R10*
Determined by Blanking
No change
As determined above
Determined by Latch Enable t
R10
R10
Determined by Blanking
As determined above
R10
Determined by Blanking
H
As determined above
New data
Determined by Latch Enable t
R10
All L
L
As determined above
Determined by Latch Enable t
R10
LC1 thru LC12 respectively
<
No T
LATCH
C
iii'
CLOCK
X
X
X
X
L
H
X
X
Stored data
Determined bV Blanking
H = high level~ L = low level, X = irrelevant, t = low-to-high-Ievel transition.
t New data enter the latches while Latch Enable is high. These data are stored while Latch Enable is low.
* Rl0 takes on the state of R9, 1:19 takes on the state of RS ... R2 takes on the state of R1. and R1 takes on the state of the data input.
'tJ
~
typical operating sequence
...C
<'
CD
CLOCK
...
!II
DATA IN
VALID
SR CONTENTS
INVALID
IRRELEVANT
VALID
n
LATCH
ENABLE - - - - - - - - - - - - - - - - . . . .
"'-----------
LATCH------------------r--------------CONTENTS _____________________________
________________________
__
PREVIOUSLY STORED DATA
NEW DATA VALID
~
BLANKING
Q OUTPUTS
VALID
------------------------------~----~-----------
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
VDD----~----------------_.~~--
INPUT - - - -....- -......--~----...
VBB
~---------- OUTPUT
100
kll
VSS-------~--~-----._~~---
3-184
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TeXAS 76266
VSS
UCN4810A
VACUUM FLUORESCENT DISPLAY DRIVER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Logic supply voltage, VDD (see Note 1) ......................................... 18 V
Driver supply voltage, Vaa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 60 V
Output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 60 V
Input voltage ............................................... -0.3 V to VOD+0.3 V
Continuous output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 40 mA
Continuou~ total dissipation at 25 DC free-air temperature (see Note 2) . . . . . . . . . . . . . .. 1150 mW
Operating free-air temperature range ...................................... ODC to 70 DC
Storage temperature range ......................................... - 65 DC to 1 50 DC
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ....................... 260 DC
NOTES:
.
1. Voltage values are with respect to VSS.
(I)
2. For operation above 25°C free-air temperature, derate linearly to 736 mW at 70 0 e at the rate of 9.2 mW/oC.
CI)
>
0;:
recommended operating conditions
C
MIN
Supply voltage, VOO
4.75
Supply voltage, VBB
5
Supply voltage, VSS
NOM
MAX
UNIT
15.75
v
v
60
0
=
=
Lfor VOO
High-level input voltage, VIH
I for VOO
5
v
15 V
low-level input voltage, Vil
Operating free-air temperature, T A
V
3.5
5.3
13.5
15.3
--0.3 t
O.B
V
-25
mA
70
°e
Continuous high-level output current. IOH
0
>CO
C.
(I)
Q
v
t The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics, VOO
otherwise noted)
4.75 V to 15.75 V, VBB .. 60 V, VSS .. 0, TA .. 25°C (unless
PARAMETER
.10l
Blanking input at VOO
Va
= 60 V,
Blanking input at VOO
Va
=
High-level output voltage
10H
Val
Low-level output voltage
Low-level output current
10l
1010ff)
IIH
Ipull-down current)
Off-state output current
High-level input current
r;
Input resistance
ro
Output resistance
IBB
100
Supply current from VBB
Supply current from VOO
MIN
TEST CONDITIONS
= -25 mA
= 1 pA,
VOH
60 V,
TA
= 0 V,
= 70 0 e
VOO - 5 V,
VOO
=
15V,
=
=
mA
15
pA
0.1
=
0.3
VI
15 V
20
6
VOO
15 V
All outputs high
13
1.3
All outputs low
All inputs at 0 V,
VOO
One output high
VOO
All inputs at 0 V,
VOO
All outputs low
VOO
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
=
=
=
=
5 V
15 V
mA
kll
50
5 V
V
0.B5
VI - 5 V
VOO - 5 V
VOO
0.4
UNIT
V
1
VSS
All other terminals open,
MAX
57.5
kll
mA
1
3
5 V
0.1
15 V
0.2
mA
3-185
UCN4810A
VACUUM FLUORESCENT DISPLAY DRIVER
tirrting requirements for Vee - 5 V and Vee" 15 V, TA - ooe to 70 0 e
VDD .. 5 V
MIN MAX
PARAMETER
1000
500
250
250
1000
Pulse duration, clock high, tw(CKH)
Pulse duration, latch enable high, tw(LEH) .
Setup time, data before clock t, tsu(D)
Hold time, data after clock t, th(D)
Delay time, clock t to latch enable high, tcKH-LEH
=
switching characteristics, Vee
UNIT
250
300
150
150
400
ns
ns
ns
ns
ns
5 V or 15 V, TA .. 25°e
MIN
PARAMETER
tpd
VDD .. 15 V
MIN MAX
Propagation delay time, latch enable to output
TYP
MAX
UNIT
ps
1
PARAMETER MEASUREMENT INFORMATION
CLOCK
INPUT
CLOCK
~I
tsu(D)
:..
\1\1\1\1'\
I
LATCH
ENABLE
:
MAN
VALID
14
~tCKH-LEH -...
th(D)
/\/\/\N,.----'Wvv\f:',-,r-X"""'ll~
DATA
I
I
I-I
I
OUTPUT
FIGURE 1, INPUT TIMING
DUTY CYCLE
vs
FREE-AIR TEMPERATURE
SO
70
'#.
60
~>-
50
~
40
I
.........
........
'
......... ~-6
........
........ ....... :---.... ....... .......... ....... 7
......
....... ........ ........
..........
S
........ 9-
i"
10-
t)
Q
N .. Number·of outputs conducting
simultaneously
lo-25mA
20
VSB" 60 V
10 VOO" 15 V
30
o
-
25 30 35 40 45 50 55 60 65 70 75
T A -Free-Air Temperature- °C
3-186
VALID
FIGURE 2. OUTPUT SWITCHING TIMES
THERMAL INFORMATION
90
tw(LEH)
I
I
I+-tpd~
VIH
VIL
100
,
~I
TEXAS .".
INSTRUMENTS .
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
'L
Alphanumeric Index
Selection Guide
Cross-Reference Guide
Data Sheets
Data Sheets
~__L_in_e__D_r_iv_e_r_s__a_n_d_R_e_c_e_i_v_e_r_s______~
Cross-Reference Guide
Data Sheets
Cross-Reference Guide
Data Sheets
Data Sheets
Data Sheets
.-5'
..c<'
..
CD
CD
en
::xl
CD
n
CD
..<'
CD
en
4-2
LINE DRIVERS AND RECEIVERS
CROSS·REFERENCE GUIDE
CROSS· REFERENCE GUIDE
(manufacturers arranged alphabetically)
Replacements were based on similarity of electrical and mechanical characteristics as shown in currently published
data. Interchangeability in particular applications is not guaranteed. Before using a device as a substitute, the
user should compare the specifications of the substitute device with the specifications of the original.
Texas Instruments makes no warranty as to the information furnished and buyer assumes all risk in the use
thereof. No liability is assumed for damages resulting from the use of the information contained in this list.
AMD
AM26LS31C
AM26LS32C
AM26LS33C
AM26S10C
AM26S10M
AM26S11C
AM26S11M
FAIRCHILD
I'A1488C
I'A1489AC
I'A1489C
I'A26lS31C
I'A26LS32C
!
"i)
CJ
Q)
-..
a::
t il
Q)
>
";:
0
Q)
s::
:::i
4-73
4-73
4-163
4-163
4-169
4-169
4-191
4-89
4·319
4-327
4-335
4-343
4-351
4·361
4·361
4-3
"
LINE DRIVERS AND RECEIVERS
CROSS·REFERENCE GUIDE
NATIONAL
....
S·
CD
C
::::!.
<
CD
Cil
::a
CD
n
CD
<.
...CD
III
4-4·
0514BB
051489
051489A
0526L531
D526L532
0526L532M
0526L533C
0526L533M
0526510C
052651 OM
D526511C
D526511M
053486
053487
D555107
0555108
0555109
0555110
0555113
D555114
0555115
0566121
0555122
0575107
0575108
0575109
0575110
0575113
0575114
0575115
0575121
0575122
0575123
05751240575125
0575127
0575128
0575129
0575150
0$75154
0575207
0575207
0575208
0575208
0575108
057820A
0578220
057830
058820
058820A
058830
SUGGESTEO
TI REPLACEMENT
SN75188
5N75189
5N75189A
AM26L531C
AM26L532AC
AM26L532AM
AM26L533AC
AM26L533AM
AM26510C
AM26A10M
AM26S11C
AM26511M
MC3486
MC3487
5N551078
5N55108
5N55109A
5N55110A
5N56113
5N55114
5N55115
5N55121
5N66122
5N751078
5N751088
5N75109A
5N75110A
5N75113
5N75114
5N75115
5N75121
5N75122
5N75123
5N75124
5N75125
5N75127
5N75128
5N751~9
5N75160
SN75154
5N75207B
5N75207
5N75208
5N75208B
5N75108B
5N55182
5N55182
5N55183
5N75182
5N75182
5N75183
PAGE
NO.
4·391
4-397
4-397
4-5
4-13
4-13
4-13
4-13
4-23
4-23
4-23
4-23
4-47
4-53
4-73
4-73
4-89
4-89
4-101
4-113
4-121
4-143
4-147
4-73
4-73
4-89
4·89
4-101
4-113
4-121
4-143
4-147
4-153
4-157
4-163
4-163
4-169
4-169
4-205
4-237
4-405
4-405
4-405
4-405
4-73
4-377
4-377
4-385
4-377
4-377
4-385
SIGNETICS
SUGGESTED
TI REPLACEMENT
PAGE
NO.
8T125
8T126
8T127
8T128
8T129
8T13
8T14
8T23
8T24
8T26
OM7820
DM7830
OM8820
OM8830
MC1488
MC1489
MC1489A
SN75126
5N75AL5126
5N75127
5N751284-169
5N75129
5N75121
5N75122
5N75123
5N75124
N8T26
5N55182
5N55183
5N75182
5N75183
5N75188
5N75189
5N75189A
4-163
4-163
4-163
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-169
4-143
4-147
4-153
4-157
4-57
4-377
4-385
4-377
4-385
4-391
4-397
4-397
AM26LS31M. AM26LS31C
QUADRUPLE DIFFERENTIAL LINE DRIVERS
02433. JANUARY 1979-REVISEO OCTOBER 1986
•
Meets EIA Standard RS-422-A
•
Operates from a Single 5-V Supply
•
TTL Compatible
lA
•
Complementary Outputs
1Y
•
High Output Impedance in Power-Off
Conditions
lZ
4Y
ENABLE G
4Z
2Z
ENABLE
•
Complementary Output Enable Inputs
2Y
3Z
2A
3Y
GND
3A
AM26LS31M ... J PACKAGE
AM26LS31C ... D. J. OR N PACKAGE
(TOP VIEW)
description
The AM26LS31 M and AM26LS31 Care
quadruple complementary-output line drivers
designed to meet the requirements of EIA
Standard RS-422-A and Federal Standard 1020.
The three-state outputs have high-current
capability for driving balanced lines such as
twisted-pair or parallel-wire transmission lines,
and they provide a high-impedance state in the
power-off condition. The enable function is
common to all four drivers and offers the choice
of an active-high or active-low enable input.
Low-power Schottky circuitry reduces power
consumption without sacrificing speed.
The AM26LS31 M is characterized for operation
over the full military temperature range of
-55°C to 125°C. The AM26LS31C is
characterized for operation from O°C to 70°C.
G
AM26LS31M ... FK PACKAGE
(TOP VIEW)
>-
•
U
«UU«
~Z>
"Ci)
G
U
-...
CI)
a:
! II
9 10111213
CI)
>
"t:
C
CI)
NC - No internal connection
logic symbol t
G (4)
VCC
4A
FUNCTION TABLE (EACH DRIVER)
INPUT
EN
G
ENABLES
c
::::i
OUTPUTS
A
G
~
V
H
H
X
H
L
L
H
X
L
H
H
X
L
H
L
L
X
L
L
H
X
L
H
Z
Z
Z
IV
H = high level
L = low level
X = irrelevant
Z = high impedance (off)
lZ
2Y
2A
2Z
3Y
3A
3Z
4A
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for 0, J. and N packages.
PRODUCTION DATA documonts contlin information
.urrent as of publiCltio. data. Products ..nlorm to
specifications par the terms of TaXI. Instruments
=-=~';·i:,~l~ ~:~::I:r :.~o.:::~::.s
nat
Copyright @ 1979. Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-5
AM26LS31M, AM26LS31C
QUADRUPLE DIFFERENTIAL LINE DRIVERS
logic diagram (positive logic)
r-
S"
CD
Pin numbers shown are for D, J, and N packages.
S'
schematic (each driver)
:Iii!"
...
INPUT A
G)
!II
~
G)
nG)
:C!"
G)
Cil
911
911
OUTPUT Y
4-6
OUTPUT Z
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
AM26LS31M, AM26LS31C
QUADRUPLE DIFFERENTIAL LINE DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
AM26LS31M
AM26LS31C
UNIT
Supply voltage, Vee (see Note 1!
7
7
Input voltage
7
7
V
5.5
5.5
V
Output off-state voltage
o package
V
950
Continuous total dissipation at (or below) 25°C free-air temperature
FK package
1375
(see Note 2!
J package
1375
mW
1025
N package
1150
Operating free-air temperature range
-55 to 125
o to 70
°e
Storage temperature range
-65 to 150
-65 to 150
°e
Case temperature for 60 seconds: FK package
260
Lead temperature 1,6 mm (1116 inch! from case for 60 seconds: J package
300
Lead temperature 1,6 mm (1116 inch! from case for 10 seconds:
NOTES:
°e
o or N package
300
°e
260
°e
1. All voltage values, except differential output voltage VOD, are with respect to network ground terminal.
2. For operation above 25°C freeMair temperature. refer to the Dissipation Derating Curves in Appendix A. In the J package,
AM26LS31 M chips are alloy mounted and AM26LS31 e chips are glass mounted. In the N package, use the 9.2-mW/oe curve
for these devices.
•
..
III
CD
>
"iii
.recommended operating conditions
(J
AM26LS31M
Supply voltage, Vee
AM26LS31C
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.5
High-level input voltage, VIH
Low-level input voltage, VIL
V
V
2
2
UNIT
V
0.8
0.8
High-level output current, IOH
-20
-20
mA
Low-level output current, IOL
20
20
mA
70
°e
Operating free-air temperature, T A
55
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
125
0
CD
-.
a:
I II
CD
>
";::
o
CD
c:::
:::;
4-7
AM26LS31 M, AM26LS31 C
QUADRUPLE DIFFERENTIAL LINE DRIVERS
electrical charcteristics over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONst
PARAMETER
Input clamp voltage
VCC - MIN,
VOH High-level output voltage
VOL Low-level output voltage
VCC - MIN,
VIK
11--18mA
20.mA
10H -
VCC - MIN,
MIN
TVP;
MAX
-1.5
10Z
Off-state (high-impedance-state) output current
II
Input current at maximum input voltage
VCC = MAX,
VI = 7 V
V
V
2.5
0.5
10L - 20 mA
I Vo
I Vo
VCC = MAX
UNIT
-20
- 0.5 V
= 2.5 V
20
0.1
V
p.A
mA
IIH
High-level input current
VCC - MAX,
VI - 2.7 V
20
~A
IlL
Low-level input current
VCC - MAX,
VI - 0.4 V
0.36
mA
lOS
Short-circuit output current§
VCC = MAX
-150
mA
ICC
Supply current (both drivers)
VCC - MAX,
80
rnA
-30
All outputs disabled
32
t For conditions shown as MIN or MAX. use the appropriate value: specified under recommended operating conditions.
All typical values are at VCC = 5 V and T A = 25°C.
*
§ Not
r5'
..<'
more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
switching characteristics. Vee'" 5 V. TA = 25°e
PARAMETER
CD
tpLH
CD
-
tpHL
CD
tpZH
Output enable time to high level
CL = 30 pF, RL = 75O,
CD
tpZL
Output enable time to low level
CL - 30 pF, RL - 180O,
tpHZ
Output disable time from high level
tpLZ
Output disable time from low level
;
~
n
<'CD
;
4-8
TVP
MAX
14
20
ns
14
20
ns
1
6
ns
See Figure 1
25
40
ns
See Figure 1
37
45
ns
21
30
ns
23
35
ns
TEST CONDITIONS
o
Propagation delay time,
low-to-high-Ievel output
Propagation delay time,
CL = 30 pF, See Figure 1,
51 and 52 open
high-to-Iow-Ievel output
Output-to-output skew
CL = 10pF, See Figure 1, 51 and 52 closed
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALl.AS, TeXAS 75265
MIN
UNIT
AM26LS31 M; AM26LS31 C
QUADRUPLE DIFFERENTIAL LINE DRIVERS
PARAMETER MEASUREMENT INFORMATION
INPUTA~.3V
(See Note BI
1.3~----::
:'-tPLH~
1
OUTPUTY
k
I/.I
I
tpHL
III tpHL
:.
1.-1-
14
Skew...-i
I
/.-
.1
Skew
-VOH
~
I.-=tPLH~
VOL
~~5
' ' -________
-Jyl_vVOOLH
V
•
OUTPUT Z
PROPAGATION DELAY TIMES AND SKEW
ENABLEG"~r-------~· 3V
1.5 ~'!\...
ENABLEG--J
(See Note CI
1.5 V
-+~------OV
tPlZ"
~I
I
--.. . I.--_____--..:-r----..
!t--tPZL---.I
4 .5V
WAVEFORM 1
(See Note DI
I
Sl CLOSED
15 V
S2 O P E N '
I
(f--tPZH~
Sl OPEN
WAVEFORM 2
(See Note DI
_ _ _ S2 CLOSED
I
( S l CLOSED
I S2 CLOSED
I
¥ __ 10
I
~*-----VOH
:{f-
_____ = 0 V
"1.5 V
Sl CLOSED
S2 CLOSED
~~~_"-
'au>s
-..
CD
"'1.5 V
I
-.---VOL
tPHz-I4~-~",~ 0.5 V LO.5 V
I
f
CD
ENABLE AND DISABLE TIMES
a:
! II
CD
>
';:
C
CD
c
::J
VOLTAGE WAVEFORMS
TEST
POINT
J
VCC
1800
FROM OUTPUT_---<_............>--
I
Vee - 4.5 V
I
I
I
3
TA -
TA -
l--25°e .....
-55 oe -
2
I
o
>
Load - 470 Il
to Ground
See Note 3
r-
S'
CD
TA
C
o
:::!,
~
til
-
-1 25oe I
1 f- Vee - 5 V
Load - 470 Il
f- to Ground
See ote 3 I
o
o
2
3
i
o
2
;:g
FIGURE 3
FIGURE 2
CD
3
V,-Enable G Input Voltage-V
VI-Enable G Input Voltage-V
n
CD
<'
OUTPUT VOLTAGE
CD
vs
vs
en
ENABLE G INPUT VOLTAGE
ENABLE G INPUT VOLTAGE
..
6
Vee - 5.5 V
Vee - 5 V
5
OUTPUT VOLTAGE
Vee - 4.5 V
II
!!'"
5
4
II
i'"
>
3
5
TA - 125°e
0
I
0
2
I
4
I
TA - 25 0 e
3
~
~
0
I
0
5
I
0
>
Vee - 5 V
Load - 1 kll to Vee
See Note 4
>
>
I
6
Load - 470 Il to Vee
TA - 25°e
See Note 4
I
TA -
2
o
o
3
2
.......
. . . . t'-,
>
>
........
-55 oe"
o
o
2
3
V,-Enab'e G Input Voltage-V
V,-Enable G input Voltage-V
FIGURE 5
FIGURE 4
t Data for temperature below 0 De and above 70 De are applicable to AM26LS31 M circuits only.
NOTES: 3. The A input is connected to Vee during the testing of the Y outputs and to ground during testing of the Z outputs.
4. The A input is connected to ground during the testing of the Y outputs and to Vee during the testing of the Z outputs.
4-10
TEXAS ..,
INSTRUMENlS
POST OFFICE BOX" 655012 • DALLAS. TEXAS 75265
AM26LS31M, AM26LS31C
QUADRUPLE DIFFERENTIAL LINE DRIVERS
TYPICAL CHARACTERISTICS t
HIGH-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR 'TEMPERATURE
.
I
I
&
4
i
>
r----- '-IOH -
-
3
=
~
0
.
'ii
>
-'
i>
..
20mA
~
f-"
-
!
r-.,
.. SV
3
V
4.S V
r--:r- ......... \
::I
10H - -40mA
J
-'S
>
>
CD
-r--r-- VO~
--r--r--~CJ~
---r-!:.C ..:-t:Fr-.....\
4
5
2
•
'ii
>
2
.!l
.i:.
.i:.
.'Z'
::z:
I
::z:
:r'"I
>
>
...
II)
::z:
0
o
0
_ VCC - 5 V
See. Note 13
-75 -50 -25
0
25
50
75
o
o
100 125
CI)
-TA - 25"C
Sie Nite 31
>
'i
C,)
-20
-40
-60
-...
CI)
-100
-80
a:
10H-High·Level Output Current-mA
TA -Free-Air Temperature - "C
I I)
CI)
FIGURE 6
''::
0.5
>
I
&
>
I
.ll!'"
0.4
'--
0
>
.ll!
·0
>
1.0
I
0.9
TA - 25"C
See Note 4
0.8
~
~
0
0.5
.
'ii
>
II
-'
0.4
0.2
~
0
~
0
-'
I
-'
0
0.1
>
o
-'
I
-'
0
VCC - 5 V
10L - 40 mA
See ,Note
>
i
-75 -50 -25
25
50
75
100 125
::::i
~
~
......-:: ~C-5.5V_
VCC - 4.5 V
h- ~
0.3
~
0.2
?'
~
0.1
o
0
CI)
c
/
0.7
S 0.6
S 0.3
0
Gi
>
-'
C
LOW-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
II
>
FIGURE 7
o
20
40
60
80
100
120
10L -Low-Level Output Current-mA
TA-Free·Air Temperature-"C
FIGURE 8
FIGURE 9
tOata for temperature below Qoe and above 7Qoe are applicable to AM26LS31M circuits only.
NOTES: 3. The A input is connected to Vee during the testing of the Y outputs and to ground during testing of the Z outputs.
4. The A input is connected to ground during the testing of the Y outputs and to Vee during the testing of the Z outputs.
TEXAS.~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-11
AM26LS31 M, AM26LS31 C
QUADRUPLE DIFFERENTIAL LINE DRIVERS
TYPICAL CHARACTERISTICSt
Y OUTPUT VOLTAGE
vs
DATA INPUT VOLTAGE
Y OUTPUT VOLTAGE
vs
DATA INPUT VOLTAGE
5
No
5
L~ad
f-TA _25°C
_Vee 1.5 V
No Load
Vec - 5.5 V
I
i>
.....,.
S
0
I
•
Vce • 4.5 V
CI>
CI>
!0
3
I
3
s...
S 2
2
0
I
0
0
,
>
>
:::s
CD
C
~.
o
o
.
CD
!II
~.
J 11
o
o
3
2
2
VI-Data Input Voltage-V
FIGURE 11
FIGURE 10
(')
:i;;
J
VI-Data Input Voltage-V
i
tOata for temperature below OOC and above 70°C are applicable to AM26LS31M circuits only.
4-12
TA. -55°C_
TA·25°C,
>
I
!::
I. 1251c-
>
Vee. 5 V
•
TA
4
4
>
TEXAS ."
INSTRUMENTs
POST OFFICE BOX 655012 • DALLAS,
TEX~S
75265
3
AM26LS32AM. AM26LS33AM. AM26LS32AC. AM26LS33AC
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
02434. OCTOBER 1980- REVISED SEPTEMBER 1986
AM26LS32AM. AM26LS33AM .•. J PACKAGE
AM26LS32AC. AM26LS33AC ... D. J. OR N PACKAGE
(TOP VIEW)
•
AM26LS32A Meets EIA Standards
RS-422-A and RS-423-A
•
AM26LS32A has ± 7-V Common-Mode
Range with ± 200-mV Sensitivity
•
AM26LS33A has ± 15-V Common-Mode
Range with ± 500 mV Sensitivity
•
Input Hysteresis ... 50 mV Typical
•
Operates from a Single 5-V Supply
•
Low-Power Schottky Circuitry
•
3-State Outputs
•
Complementary Output Enable Inputs
•
Input Impedance . . . 12 kO Min
1B
1A
1Y
G
2Y
2A
2B
GND
VCC
4B
4A
4Y
G
3Y
3A
3B
AM26LS32AM. AM26LS33AM ... FK PACKAGE
(TOP VIEW)
II
U
'
'G)
(,)
(I)
a::
14
I II
~
9 1011 1213
(I)
>
';:
C
(I)
NC - No internal connection
c:
:::i
Compared to the AM26LS32C and the AM26LS33C, the AM26LS32A and AM26LS33A incorporate an
additional stage of amplification to improve sensitivity. The input impedance has been increased resulting
in less loading of the bus line. The additional stage has increased propagation delay; however, this will
not affect interchangeability in most applications.
The AM26LS32AM and the AM26LS33AM are characterized for operation over the full military temperature
range of - 55°C to 125°C. The AM26LS32AC and AM26LS33AC are characterized for operation from
ooe to 70°C.
FUNCTION TABLE (EACH RECEIVER)
DIFFERENTIAL
ENABLES
INPUT
vlD '" vTH
VTL '" VID s VTH
VID s VTL
X
H = high level. L
=
OUTPUT
G
G
H
X
X
L
H
H
H
X
?
X
L
?
H
X
L
X
L
L
L
H
Z
low level. X
=
irrelevant
Z = high impedance (off). ? = indeterminate
Copyright © 1980. Texas Instruments Incorporated
PRODUCTION DATA documanl. conlain information
currant as of publication data. Products conform to
.pacifications par the terms of TeXIS Instruments
:~~~~~~i~air::I~~i ~:~:~i:r :ltD:=:::9t::'~S not
TEXAS ."
4-13
INSTRUMENTS
post OFFICE BOX 868012 • DAL.AS. tEXAS
'5266
AM26LS32AM. AM26LS33AM. AM26LS32AC. AM26LS33AC
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
logic symbol t
lA
logic diagram (positive logic)
(31
1Y
(31 1.y
2Y
(51 2y
18
2A
(51
2B
3A
(111
3B
4A
3Y
(131 4Y
(111 3y
4B
c:
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
(131 4y
:s
CD
...C
...<'enCD
schematics of inputs and outputs
;a
CD
CD
EQUIVALENT OF EACH .
EQUIVALENT OF EACH ENABLE INPUT
DIFFERENTIAL INPUT
VCC------~---1~
VCC----------~-----
8.3 k!l
NOM
(')
...<'
CD
en
20 k!l
NOM
INPUT _ _""1~::::..t--
4-14
ENABLE - . -......---1
TEXAS . "
INSTRUMENTS
POST ,OFFICE BOX 655012 • DALLAS, TEXAS 75265
TYPICAL OF ALL OUTPUTS
AM26LS32AM, AM26LS33AM, AM26LS32AC, AM26LS33AC
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
AM26LS32AM
AM26LS32AC
AM26LS33AM
AM26LS33AC
7
Supply voltage, Vee Isee Note 1)
7
UNIT
V
Input voltage, any differential input
±25
±25
V
Differential input voltage Isee Note 2)
±25
±25
V
o package
950
Continuous total dissipation at (or below)
FK package
1375
25 DC free-air temperaure Isee Note 3)
J package
1375
1025
Operating free-air temperature range
-55 to 125
o to 70
DC
Storage temperature range
-65 to 150
-65 to 150
DC
260
DC
300
DC
N package
lead temperature 1,6 mm 11/16 inch)
o or N
from case for 10 seconds
Case temperature for 60 seconds
lead temperature 1,6 mm 11/16 inch)
from case for 60 seconds
mW
1150
package
FK package
260
J package
300
DC
II
...
Ul
NOTES:
1. All voltage values. except differential voltages, are with respect to the network ground terminal.
2. Differential voltage values are at the non inverting (A) input terminals with respect to the inverting (8) input terminals.
3. For operation above 25°C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the J package,
AM26LS32AM and AM26lS33AM chips are alloy mounted and AM26LS32AC and AM26lS33Ae chips are glass mounted.
In the N package, use the 9.2 mW/oe curve.
AM26LS32AM
AM26LS32AC
AM26LS33AM
AM26LS33AC
MIN
4,5
High-level input voltage, VIH
NOM
MAX
MIN
NOM
5
5.5
4.75
2
5
2
low-level input voltage, Vll
I
AM26lS32AM, Arv'l26LS32Ae
AM26LS33AM, AM26LS33Ae
low-level output current, IOL
-55
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
>
'l:
UNIT
MAX
5.25
V
0.8
V
±7
±7
±15
V
8
125
0
-440
"A
8
mA
DC
70
C
Q)
V
0.8
±15
-440
High-level output current, IOH
Operating free-air temperature, T A
-...
Q)
Q)
Supply voltage, Vee
I
CJ
a:
Ul
recommended operating conditions
Common-mode input voltage, VIC
Q)
>
'iii
c:::
::i
4-15
AM26LS32AM, AM26LS33AM, AM26LS32AC, AM26LS33AC
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
Vee. Vie. and operating free-air temperature
electrical characteristics over recommended ranges of
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
Differential input
VTH
Va ~ VOHmin,
high-threshold voltage
Differential input
VTL
Hysteresis, VT + - VT- §
Enable input clamp voltage
VOH
High-level output voltage
..
VOL
II
r5'
CD
VCC - MIN,
VID - 1 V,
VI@
~
0.8 V,
VCC - MIN,
Low-level output voltage
-0.5 t
Line input current
2.5
0.4
lOt: - 8 mA
0.45
20
Vo - 2.4 V
0.4 V
-20
VI
-15 V,
Other input at -15 V to 10 V
-1.7
~
V
V
2.7
10L - 4 mA
~
V
mV
1.5
Vo
UNIT
V
1.2
V
~A
mA
IIIENI
Enable input current
VI
5.5 V
100
~A
IIH
High-level enable current
20
#A
-0.36
mA
-85
mA
70
rnA
~
CD
lOS
Short-circuit output current'
VCC ~ MAX
III
ICC
Supply current
VCC - MAX,
CD
-0.2t
AM26LS33A
Other input at -10 V to 15 V
c2'
III
AM26LS32A
15 V,
VIC -
CD
0.5
VI -
Low-level enable current
CD
1 V,
VID -
VCC ~MAX
Input resistance
(')
AM26LS33A
10H ~ -440 #A '32AC, '33AC
output current
IlL
:D
0.2
'32AM, '33AM
VI(GI ~ 0.8 V
r;
-..<'
MAX
50
C
~
Typt
18 mA
11-
VI - 2.7 V
VI ~ 0.4 V
~
10L ~ 8 mA
VCC - MIN,
Off-state (high-impedance-statel
10Z
0.45 V,
~A
low-threshold voltage
VIK
Vhys
~
Va
10H ~ -440
MIN
AM26LS32A
15Vt015V, One input to AC ground
12
-15
All outputs disabled
kO
15
52
t All typical values are at VCC ~ 5 V, TA ~ 25°C, and VIC ~ O.
The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for threshold
levels only.
§ Hysteresis is the difference between the positive-going input threshold voltage, VT +, and the negative-going input threshold voltage,
VT _. See Figures 10 and 11 .
, Not more than one output should be shorted at a time.
*
switching characteristics.
Vee
= 5
V.
TA
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-high-Ievel output
tpHL
Propagation delay time, high-to-Iow-Ievel output
tpZH
Output enable time to high level
tpZL
Output enable time to low level
tpHZ
Output disable time from high level
tpLZ
Output disable time from low level
~
15 pF,
See Figure 1
CL ~ 15 pF,
See Figure 1
CL
CL
~
5 pF,
See Figure 1
~
TEXAS
INSTRUMENTS
4-16
~QST
OFFlte BOX 'sodl ~ • gALLAS, tEXAS ,USS
MIN
TYP
MAX
20
35
UNIT
ns
22
35
ns
17
22
ns
20
25
ns
21
30
ns
30
40
ns
AM26LS32AM. AM26LS33AM. AM26LS32AC. AM26LS33AC
QUADRUPLE DIFFERENTIAL LINE RECEIV.ERS
PARAMETER MEASUREMENT INFORMATION
TEST
POINT
OV\I- -
-
--+2.SV
INPUTJOV
I
FROM OUTPUT _ _. -..... -.............
UNDER TEST
.....- - - - - 2 . S V
)/, .. ,..tv"'
tpLH --....~t---...I
See Note B
OUTPUT
CL
See Note A
-----'
14"
tPHL
51 and 82 closed
VOL
VOLTAGE WAVEFORMS FOR tPLH. tPHL
II
TEST CIRCUIT
I+- sS ns
ENABLE
I!!
CD
ENABLE
G
G
>
""";';;';';~-OV
-";'';''-;';;;'''-0 V
.11-::9==0:::"%-- l V
'Q)
Co)
1r:'90:::%::-- l V
CD
a::
ENABLE
-
G
OUTPUT
S1 open
S2
closed
_
_
_. I
+---x ~
1.lV
I
~
G
I
:-VOH
~~1.4V
tPHZ~S1
tPLZ
OUTPUT
closed
S2 closed
52 open
~
S2 closed
~=1.4
-=*-
-~-VOL
O.SV
'i:
V
C
CD
c:
:::;
VOLTAGE WAVEFORMS FOR tpLZ. tpZL
VOLTAGE WAVEFORMS FOR tPHZ. tpZH
~OTE5:
--I!!
ENABLE
- - -OV
O.S VI
A. CL includes probe and jig capacitance.
B. All diodes are 1Nl064 or equivalent.
C. Enable G is tested with ~ high; G is tested with Glow.
FIGURE 1
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-17
AM26LS32AM,AM26LS33AM, AM26LS32AC, AM26LS33AC
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
5
.IO,2I V
TA - 25°e -
II
r-
:i"
CD
..<"
3
~~
'''\ ~
"\ ~ V
a;
....>
l!
2
~
Vee -
I
:r
0
>
i>'"
4
15
3
$
0
Vee - 5.25 V
I
I
I
Vee - 5 V
a;
....,>
I~ ~
4.75 V
I~ ~
.s.»
:r
I
:r
0
>
~~
o
-10
CD
-20
-30
2
l!
~~
o
C
..
I
~
>
$
0
>
4
Q'
15
5
V~O
>
.,I
'"
~
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
-40
Vee - 5 V
VIO - 0.2 V
10H - -440 pA
o
-50
o
.\
I
I
10
20
30
Cil
50
60
70
80
FIGURE 3
FIGURE 2
::0
40
TA-Fraa-Air Tamparatura- °e
IOH-High-Laval Output eurrant-mA
CD
(')
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
CD
..
<"CD
III
0.6
.,I
i'"
>
s
$
0
a;
....,>
0.5
0.4
~
0.2
...I
0
0.1
oS
>
.,V
0.3
/
/
0.5
,/'
Vee - 5 V
TA - 25°C
>
/
V
>
./
.,I
.;J'"
0.4
Q
>
S
$
0.3
0
V
1
3
0.2
~
Q
...I
...
0
0.1
Vee - 5 V
VIO - -0.2 V
IOL-8mA
>
o
o
0
5
10
15
20
25
30
o
I
I
10
20
FIGURE 4
4-18
30
40
50
60
TA-Fraa-Air Tamparatura- °e
IOL -Low-Laval Output eurrant-mA
FIGURE 5
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
70
80
AM26LS32AM, AM26LS33AM, AM26LS32AC, AM26LS33AC
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
ENABLE G VOLTAGE
ENABLE G VOLTAGE
5
5
VID = 0.2 V
-TA=25°e
Load = 8 kn
4 - t o ground
>I
vbe= 5.J V
Vee = 5 V
VID = 0.2 V
Load = 8 kn to ground
4
r
TA=70oe
>
Vee= 5 V
TA=25°e
I
~
>...
"'"
Vee= 4.5 V
3
"'0
!!!
"'0
TA = oOe_
3
>
5
:J
.s-:J
.s-
2
0
I
0
"
0
I
0
>
a
2
>
~
Q)
>
"Qi
0
0
0
1.5
0.5
2.5
2
0
3
0.5
Enable G Voltage-V
FIGURE 6
1.5
2
Enable G Voltage - V
2.5
3
(.)
Q)
a:
-.
III
...
Q)
FIGURE 7
>
".:;
OUTPUT VOLTAGE
vs
ENABLE G VOLTAGE
6
6
Vee=5.5V
Vee = 5 V
5
Vee= 4.5 V
>I
VID=I- o.2 )
TA=25°e
Load = 1 kn to Vee
Vee~ 5V
>
I
"'"
!!!
>... 3
>
...
3
0
I
0
2
"'0
?=25~e-~
"'0
a
.s-":J
:J
2
>
c:
::::i
I
I
4
!!!
Q)
VID = -0.2 V
Load = 1 kn to Vee
5
8, 4
9o
o
OUTPUT VOLTAGE
vs
ENABLE G VOLTAGE
....TA I=0° e
iA = 70ol e-t
>
o
o
0.5
1.5
2
2.5
3
o
o
0.5
Enable G Voltage-V
1.5
2
2.5
3
Enable G Voltage - V
FIGURE 8
FIGURE 9
TEXAS .",
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-19
AM26LS32AM, AM26LS33AM, AM2LS32AC, AM26LS33AC
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
TYPICAL CHARACTERISTICS
5
>
4
"0
3
>
...
•
::>
AM26LS33A
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
OUTPUT VOLT AGE
vs
DIFFERENTIAL INPUT VOLTAGE
5
Vee; 5 V
10;0
TA;25°e
I
J
AM26LS32A
-
t--V~_
!.
Vle- YIC=
7V
I
t"ov
I
VT+ ~T+
VT
VIC;
7V
VT_ VT+
,.,.
S'
4 f - - f-ttl~ ; I- -VIC;
-15V
OV
!::
3
..'"...
f--
0
>...
::>
...::>
0-
0-
8
>
I
2
0
I
0
I
g
TA; 25°C
10;0
Vce; 5V
I
-\'IC; '--15 V
VT-
Vr-
VT-
VT+
VT+
VT+
2
>
CD
C
:!,
~
o
-200-150-100 -50
~
CD
n
CD
<'
CD
til
0
50
o
100 150 200
-200-150-100· -'50
VID - Differential Input Voltage - mV
50
FIGURE 11
FIGURE 10
INPUT CURRENT
vs
INPUT VOLTAGE
-25-20-15-10 - 5 0
5
10 15 20 25
VI - Input Voltage - V
FIGURE 12
4-20
0
100 150
VID - Differential Input Voltage - mV
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TeXAS 75265
200
AM26LS32AM, AM26LS33AM, AM26LS32AC, AM26LS33AC
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
TYPICAL APPLICATION
Yo AM26LS32AC
Yo AM26LS31C
DATA
RT*
IN
DATA
OUT
Yo AM26LS33AC
Yo AM26LS32AC
DATA
DATA
OUT
OUT
*RT equals the characteristic impedance of the line.
FIGURE 13. CIRCUIT WITH MULTIPLE RECEIVERS
a
en
~
G)
>
'i
(,)
G)
a::
en
~
G)
>
'i:
o
G)
c:
:::;
TEXAS . "
INSTRUMENTS
POsf bt=jrlCE BOX 655012 • DALI..A9, T&XAS 75266
4-21
III
r3'
CD
..<'
..
-..<'
C
CD
VI
:J:J
CD
(')
CD
CD
VI
4-22
AM26S10M, AM26S1 ~C, AM26S11 M, AM26S11 C
QUADRUPLE BUS TRANSCEIVERS
02298, JANUARY 1977 -REVISED SEPTEMBER 1986
AM26S10M. AM26S11M • , . J PACKAGE
AM26S10C. AM26S11C .• , D. J, OR N PACKAGE
•
Schottky Circuitry for High Speed. Typical
Propagation Delay Time ... 12 ns
•
Drivers Feature Open-Collector Outputs for
Party-Line (Data Bus) Operation
(TOP VIEW)
•
Driver Outputs Can Sink 100 mA at 0.8 V
Maximum
•
P-N-P Inputs for Minimal Input Loading
•
Designed to be Interchangeable with
Advanced Micro Devices AM26S10 and
AM26S11
Vee
GNO
1B
1R
10
20
2R
2B
GNO
4B
4R
40
5
30
3R
3B
a
AM26S10M, AM26S11M .•. FK PACKAGE
description
(TOP VIEW)
The AM26S 10 and AM26S 11 are quadruple bus
transceivers utilizing Schottky-diode-clamped
transistors for high speed. The drivers feature
open-collector outputs capable of sinking
100 mA at 0,8 V maximum, The driver and
strobe inputs use p-n-p transistors to reduce the
input loading,
o
U
mZU Um
_t!lZ> ....
3
4
5
6
2 1 20 19
~
CD
18
>
'iii
u
17
16
-.
CD
15
The driver of the AM26S10 is inverting; the
driver of the AM26S11 is noninverting. Each
device has two ground connections for improved
ground current-handling capability. For proper
operation, the ground pins should be tied
together,
a::
14
8
CI)
CD
>
'i:
C
CD
NC - No internal connection
c
::::i
The AM26S 10M and AM26S 11 M are characterized for operation over the full military temperature range
of - 55°e to 125°e. The AM26S10e and AM26S11e are characterized for operation over the temperature
range of ooe to 70 oe.
AM26S10
AM26S11
FUNCTION TABLE
FUNCTION TABLE
(TRANSMITTING)
(TRANSMITTING)
OUTPUTS
INPUTS
OUTPUTS
INPUTS
R
D
B
H
S
L.
H
H
L
L
L
L
L
H
S
D
B
R
L
H
L
L
L
H
AM26S 10 AND AM26S 11
FUNCTION TABLE
(RECEIVING)
INPUTS
OUTPUT
S
B
D
R
H
H
H
X
X
H
L
H = hIgh level, L = low level,
PRODUCTION DATA documanlS contain information
currant .s of public.tion data. Praducts conform to
specificatioRs per the terms of TIXIS Instramltnts
=~~~i~a:l~le ~=::i:r :'~D:=::::9t::'s~S nat
L
X=
orrelevant
Copyright © 1980, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
4-23
AM26S10M, AM26S10C, AM26S11 M, AM26S11 C
QUADRUPLE BUS TRANSCEIVERS
logic symbols t
AM26S10
AM26S11
S
III
po-.........:.:(7C!.1 28
po-_.....:.(7;.;.1 28
po-..........!!(9~1 38
po-_.....,!;(9~1 38
(151 48
(151 48
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
logic diagrams (positive logic)
r-
AM26S10
S'
AM26S11
CD
C
::I,
...~
en
+-4L__~
-
10~(4~1--______
CD
20~(5~1--------+-~__J
...
2R~(6~1-------i----~
(21 18
(21 18
(71 28
{71 28
(91 38
{91 38
{151 48
(151 48
1R (31
::u
CD
()
<'
CD
en
30(111
3R(101
40 (131
4R (141
Pin numbers shown are for 0, J, and N packages.
4-24
TEXAS
~
INSfRUMENTS
POST OFFICE
aox 655012
10
bAbL.At:i 1 tt)tAS 75266
AM26S10M. AM26S10C. AM26S11M. AM26S11C
QUADRUPLE BUS TRANSCEIVERS
schematic (each transceiver)
B-----~====~======~==~~~~~----~--~----~
__
1100
NOM
2 kO
NOM
VCC
v
AM26S11I
rt
I .
I
!
I!
,--+~~IL .. -.i
R
I
_..J ___ -1
I
AM26S10
I
I
I
I
~--~------~------r---+---~----~--~~----~~--~--~~-4----GND
---------
--------1
COMMON
CIRCUITRY
TO THREE
"'---OTHER
DRIVERS
:
I
TO ONE
OTHER
RECEIVER
en
(\)
I
I
L _____ -,
f-~--~>--"
II
.
TO TWO
}--~-- OTHER
RECEIVERS
I
I
I
I
>
"iii
(.)
(\)
-..
a:
en
(\)
>
".::
C
(\)
c
::::i
I ___________________________________ :
L
~
TEXAS ."
INSTRUMENTS
POST OFFICE QcOX 655012 • DALLAS, TEXAS 75265
4-25
AM2'6S10M, AM26S1 DC, AM26S11 M, AM26S11 C
QUADRUPLE BUS TRANSCEIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) ...................................... -0.5 V to 7 V
Driver or strobe input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0,5 V to 5.5 V
Bus voltage, driver output off: AM26S10M, AMS26S11M .................. -0.5 V to 5.5 V
AM26S10C, AM26S11C ................... -0.5 V to 5.25 V
Driver or strobe input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 30 mA to 5 mA
Driver output current .. ! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 200 mA
Receiver output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 30 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
D package .......................................................... 950 mW
FK package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1375 mW
J package (AM26S10M) ............................................... 1375 mW
J package (AM26S10C) .............................................. 1025 mW
N package .......................•................................ 1150 mW
Operating free-air temperature range: AM26S 10M, AM26S11 M ............. - 55°C to 125°C
AM26S10C, AM26S11C .................. ooC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............. 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package ......... 260°C
•
r-
5'
C'D
.o
..
;C'
NOTES:
C'D
til
-.
1. All voltage values are with respect to network ground terminals connected together.
2. For operation above 25°C free-air temperature, see Dissipation Derating Curves in Appendix A. In the J package, AM26S10M
and AM26S11M chips are alloy mounted and AM26S10C and AM26S11C chips are glass mounted. For these devices in
the N package, use the 9.2-mWloC curve.
::Jl
C'D
recommended operating conditions
(')
C'D
.
;C'
AM26S10M
AM26S11M
C'D
til
Supply voltage, VCC
High-level input voltage, VIH
Low-level input voltage, VIL
MIN
NOM
4.5
5
Dar S
B
MIN
4.75
NOM
5
UNIT
MAX
5.25
2
2.25
2.4
0.8
0.8
B
1.6
-1
1.75
I Driver
100
100
I Receiver
20
125
-55
.
TEXAS ..,
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
-1
20
0
V
V
Dar S
Operating free-air temperature, T A
4-26
AM26S11C
MAX
5.5
2
Receiver high~level output current, IOH
Low-level output current, tOl
AM26S10C
70
V
rnA
rnA
°C
AM26S10M. AM26S10C. AM26S11M. AM26S11C
QUADRUPLE BUS TRANSCEIVERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
AM26S10C
AM26S10M
TEST CONDITIONSt
PARAMETER
MIN
VIK
Input clamp
o or
voltage
S
High-level
VOH
output voltage
R
R
Low-level
VOL
t--
output voltage B
Off-state
10(off)
output current
High-level
IIH
input current
Input current
at maximum
II
input voltage
Low-level
IlL
input current
B
D
rs
o or
S
TYP*
Vee = MIN, VIH = 2 V,
VIL = VIL max,
2.5
IOH = -1 mA
VIH = 2 V,
MIN
TYP*
MAX
-1.2
3.4
2.7
0.5
IOL - 40 mA
0.33
0.5
0.33
0.5
IOL - 70 mA
100 mA
IOL
0.42
0.7
0.42
0.7
0.8
0.51
0.8
0.51
I Vee
- MAX, Va - 0.8 V
50
50
,I Vee
I Vee
- MAX, Va - 4.5 V
200
100
- 0,
100
100
30
30
20
20
100
100
-0.54
-0.54
-0.36
-0.36
VIL = 0.8 V
Va - 4.5 V
Vee = MAX, VI = 2.7 V
V
V
3.4
0.5
IOL - 20 mA
Vee = MIN,
VIH = VIHMIN,
VIL = 0.8 V
MAX
-1.2
Vee = MIN, 11= -18 mA
UNIT
AM26S11C
AM26S11M
V
~A
~A
lOS
~A
>
"ii)
C.)
0
S
Vee = MAX, VI = 0.4 V
CD
mA
R
-20
Vee = MAX
-55
-18
-60
-...
a:
1/1
CD
>
mA
"~
current§
lee
...
1/1
CD
Vee = MAX,VI = 5.5 V
Short-circuit
output
a
I
Supply AM26S10
Vee - MAX, Strobe at 0 V,
I
current AM26S 11
All driver outputs low
No load,
45
70
45
70
80
80
C
mA
t For conditions shown as MIN or MAX, use the appropriate value shown under recommended operating conditions.
:I All typical values are at T A = 25 De and Vee = 5 V.
§ Not more than one output should be shorted to ground at a time, and duration of the short circuit should not exceed one second.
switching characteristics.
Vee
= 5
V. TA
PARAMETER
=
25°e
FROM TO
tpLH Propagation delay time, low-to-high-Ievel output
tpHL Propagation delay time, high-to-Iow-Ievel output
tpLH Propagation delay time, low-to-high-Ievel output
tpHL Propagation delay time, high-to-Iow-Ievel output
tpLH Propagation delay time, low-to-high-Ievel output
tpHL Propagation delay time, high-to-Iow-Ievel output
tTLH Transition time. low-to-high-Ievel output
tTHL Transition time, high-to-Iow-Ievel output
0
5
AM26S10
TEST
CONDITIONS
MIN
B
B
See Figure 1
B
CD
I:
::i
R
B
AM26S11
TYP
MAX
10
10
MIN
TYP
MAX
15
12
19
12
19
14
15
18
15
20
13
18
14
20
10
15
10
15
10
15
15
4
10
4
10
10
2
4
2
4
TEXAS ."
INSfRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
UNIT
ns
ns
ns
ns
4-27
AM26S10M, AM26S1 ~C, AM26S11 M, AM26S11 C
QUADRUPLE BUS TRANSCEIVERS
PARAMETER MEASUREMENT INFORMATION
VCC
,'-----'----------------,
,..-------.;..I-....J
500
INI. . - - - -...
AM26S11 .
........+-,. . . -
-[>0- -1
I
I
2800
I
RECEIVER
iL __________________________ J.
III
50 pF
r-
ISee Note 8)
5'
1
15 pF
ISe8 Note 8)
ISee Note C)
J
CD
.<'
..
o
o
S
R
8
TEST CIRCUIT
CD
*_mn______
!II
~
CD
n
AM26S11
~":::]
CD
<'
CD
,
,
____
n
I """""A""M':"'26""'S-10,...-J,
U;
0 V
f
~:U~8E!
i
--r,----~I------J,1
-
,
-+I 14I
~-1
tpLH
Ot08
-.t
...j .... BtPtHo LR
:-
~~~~~~R---
14- tpHL
I
Ot08
==== -. :.:
\-1
--t 1+
I
.
...-t 14I
tPLH
StaB
\. __'" "-.{.
....
14- tpLH
I
....aJ j4- tpHL
B to R
--'l
....\ ' -_ _ _
'I
I
V
OV
tpHL
StaB
F~==:~
~ 14- tpLH
B to R I B to R
\~___...LE ::'
VOLTAGE WAVEFORMS
NOTES: A. The pulse generators have the following characteristics: Zout
B. Includes probe and jig capacitance.
C. All diodes are 1 N916 or equivalent.
= 50 0, tr = 10
FIGURE 1
4-28
: : ,
TEXAS ..,
INSTRUMENlS
POST OFFICE BOX 655012 .• DALLAS, TEXAS 75265
± 5 ns.
AM26S1DM, AM26S10C, AM26S11M, AM26S11C
QUADRUPLE BUS TRANSCEIVERS
TYPICAL APPLICATION
STROBE
DRIVER
INPUTS
RECEIVER
OUTPUTS
1111
DDDD
5 V
AM26S101
AM26S11
B
100 II
100 II
B
1 I
1
STROBE
STROBE
DRIVER
B
B
INPUTS
RECEIVER
OUTPUTS
,.J Hll
~
~
R-
RR_
B
B
B
B
1IiI
R-
~
I---
1 I
1
SR
AM26S101
AM26S11
RR
RECEIVER
OUTPUTS
DDDD
SR
AM26S101
AM26S11
DRIVER
INPUTS
B
B
1
1
1
B
B
5 V
RI-Rr-RI--100 II
100 II
100 II
100 II
100 II
100 II
II
.
1/1
CII
>
.a;
to)
100-11 TRANSMISSION LINE
FIGURE 2. PARTY-LINE SYSTEM
CII
a:
--.
1/1
CII
>
.;:
C
CII
c:
:::i
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-29
r-
:r
CD
...c
<"
CD
Ul
::ltI
CD
()
CD
~"
Ul
4-30
MC3446
QUADRUPLE BUS TRANSCEIVER
02290. JANUARY 1977-REVISED SEPTEMBER 1986
•
(TOP VIEW)
1R
1B
10
•
Driver Outputs Stay Off During Power Up
and Power Down
•
Drivers Feature Open-Collector Outputs for
Party-Line Operation
•
Designed -for Interchangeability with
Motorola MC3446
•
D. J, OR N DUAL-IN-LiNE PACKAGE
Driver Inputs Compatible with TTL and MOS
Circuitry
Vee
4R
4B
1,2,3S
20
2B
40
4S
3D
2R
3B
GNO"""",_~.... 3R
Meet IEEE Standard 488-1975
logic diagram (positive logic)
description
•
'B~~~~------------~
vcc~~~----------~,
These circuits are quadruple single-ended line
transceivers designed for bidirectional flow of
data and instructions. The bus terminal
characteristic complies with paragraph 3.5.3 of
IEEE Standard 488 (see Figure 3). Each driver
output is tied to the junction of an internal
voltage divider that sets the no-load outpuf
voltage and provides bus termination. The driver
outputs are guaranteed to be "off" during power
up and power down if either input is high. The
receivers feature 950 millivolts typical hysteresis
for noise immunity.
1,2,3S
.
--'='-----t-l._,1
'0
II)
Q)
>
2B--'='--~~-----------r,
'Qj
U
-..
Q)
a:
20 --='-----+~./
I I)
Q)
38....:..:.:"-"1"++----+,
>
'C
C
The MC3446 is characterized for operation from
ODC to 70 DC.
Q)
30 --=-:.""------t_"
c:
::i
FUNCTION TABLE
4B~~~~----------~'
ITRANSMITTINGI
0
H
L
L
L
os
OUTPUT
INPUTS
S
40
B
R
H
H
L
L
Rl
~
....:..:.=------£.-"
2.4 kO NOM. R2
~
5 kO NOM
logic symbol t
FUNCTION TABLE
IRECEIVING)
INPUTS
S
B
H
H
H
L
1,2,3S
OUTPUT
0
X
X
R
10
H
lR
L
20
2R
3D
(10) 38
3R
45
(14) 48
tThis symbol is in accordance wilh ANSI/IEEE SId 91-1984 and
lEe Publicalion 617-12.
Copyright @ 1986, Texas Instruments Incorporated
PRODUCTION DATA documanl. conlain informalion
currant I. af publication data. Products conform to
spacifications par the terms of TIXI. Instruments
:~~:=~~;;8{::I~'li ~~a:i:ti:r lI~D::;::~:~ nat
.
TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-31
MC3446
QUADRUPLE BUS TRANSCEIVER
schematics of inputs and outputs
EQUIVALENT OF EACH
DRIVER AND
STROBE INPUT
EQUIVALENT OF
DRIVER OUTPUTS/RECEIVER INPUTS
RECEIVER OUTPUTS
_ _ _ _ _ _. -__~-VCC
440Sl.
NOM
20kSl.
NOM
BUS
VCC--.....- -
-- - - - --1-----....-- - VCC
2.4kSl.
NOM
13.6kSl.
NOM
D
OR
S
OUTPUT
2.2kSl.
NOM
r-
5'
CD
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
C
::!,
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage ................................ : ............................' 5.5 V
Driver output current ........................................... : . . . . . . . .. 150 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
D package ......................................................... 950 mW
J package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package ........................................................ 1050 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............ 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D and N package ....... 260°C
...<
CD
(II
:l:I
CD
n
CD
<'
CD
...
(II
NOTES: 1. Voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the J package, use
the 8.2 mW/oC curve, in the 0 package, use the 7.6 mW/oC curve, and in the N package, use the 9.2-mW/oC curve.
recommended operating conditions
Supply voltage, Vee
Low-level input voltage, VIL
o or S
o or S
High-level output current, IOH
Receiver
Low-level output current, IOL
Driver
Receiver
High-level input voltage, VIH
Operating free-air temperature, TA
4-32
MIN
NOM
4.75
2
5
TEXAS . "
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
5.25
V
V
0.8
-0.4
V
mA
48
mA
8
0
INSTRUMENTS
MAX UNIT
70.
°c
MC3446
QUADRUPLE BUS TRANSCEIVER
electrical characteristics over recommended ranges of Vee and operating free-air temperature (unless
otherwise noted)
PARAMETER
VIK
D or S
Positive-going input
VT+
VT-
High-level output voltage
Val
Low-level output voltage
IO(bus)
Bus current
VOK
II
-12 mA
0.6
0.85
1.1
400
950
VIH - 2.4 V,
VIH - 2 V,
2.5
2.4
3.3
R
B
Vil
R
Vil - 0.8 V,
10l - 8 mA
VIH - 2.4 V,
Va - 5.5 V
=
B
VIH
B
VIH
10 -
o or S
o or S
VI
0.8 V,
=
=
2.4 V,
=
10l
= 48
Low-level input current
0.7
1
lOS
Short-circuit output current
ICCH
Supply current, all outputs high
VIH - 2 V
No load
ICCl
Supply current, all outputs low
No load
5
0.2
TA - 25°C
V
-3.2
-1.5
Vil - 0.4 V,
V
mA
-1.3
VIH - 2.4 V
VCC - 5 V,
3.7
0.4
2.5
=5V
= 0.4 V
V
mV
0.4
mA
5.5 V
High-level input current
R
IOH - 0
10H - - 4OO l"A
Va
2.4 V, Va
-12 mA
IIH
=
V
B
B
III
tAli typical values are at VCC = 5 V, TA
V
B
D or S
input voltage
UNIT
2
Output clamp voltage
Input current at maximum
MAX
-1.5
1.8
Negative-going input
VOH
=
1.5
threshold voltage
Input hysteresis, (VT + - VT-)
II
B
threshold voltage
Vhys
MIN Typt
TEST CONDITIONS
Input clamp voltage
4
V
mA
20
0.38
~
mA
14
mA
10
19
mA
32
39
mA
•
~
CI)
"~
CI)
(,)
CI)
-..
~
! II
CI)
>
";:
25°C.
C
switching characteristics. Vee"" 5 V. TA ... 25°e
PARAMETER
FROM
TO
0
B
CI)
c
TEST CONDITIONS
Propagation delay time,
tplH
tpHl
low-to-high·level output
Propagation delay time.
Propagation delay time,
tPHl
tplH
tpHl
Propagation delay time,
::::;
ns
See Figure 1
50
S
ns
B
50
high-to-Iow·level output
Propagation delay time,
low-to-high-Ievel output
UNIT
50
high.to-Iow-Ievel output
low-to· high· level output
MAX
40
Propagation delay time,
tplH
MIN
50
B
R
ns
See Figure 2
40
high-to-Iow-Ievel output
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75266
4-33
MC3446
QUADRUPLE BUS TRANSCEIVER
PARAMETER MEASUREMENT INFORMATION
RECEIVER OUTPUT
OPEN
~O%
+5V
INPUT
STROBE or DRIVER
INPUT MONITOR
.
100 n
-:O:--3V
I
I
I
I
I
OV
I
14-
£:::c
tPLH'"
l
50pF
(See Note B)
14- tPHL
~
-I---VOH
:
I
OUTPUT
I
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
FIGURE 1
INPUT (BUS)
MONITOR
.S'
+5V
CD
400n
OUTPUT
(RECEIVER)
...C
<'
...enCD
-
,~"'
:l
tPLH
50n
(')
j+-tPHL
~
OUTPUT
CD
<'CD
...
L
1.5V
..
en
OV
--.l I+- ~
~ ,,~--•
15 pF
(Se. Note B)
CD
I
I
I
(See Note C)
::0
\~~~"
I
VOH
VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
FIGURE 2
NOTES:
A. The input pulse is supplied by a generator having the following characteristics: tw ::::: 100 ns, PRR ::$ 1 MHz, tr
If '" 10 ns, Zout ~ 50 O.
B. This value includes probe and jig capacitance.
C. All diodes are 1 N916 or 1 N3064.
TYPICAL CHARACTERISTICS
RECEIVER TRANSFER CHARACTEAISTICS
DRIVER OUTPUT CHARACTERISTCSt
ob-d-~~~~~~
o
Vo-Driver Output Voltilge-V
1
=
25°C.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
__L -
1.5
2
2.5
3
V,-Input Voltage-V
FIGURE 4
FIGURE 3
tConditions for typical curve are VCC ~ 5 V, TA
4-34
0.5
3.5
4
:s:
10 ns,
MC3450, MC3452
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
03006. FEBRUARY 1986- REVISED OCTOBER 1986
•
Four Independent Receivers with Common
Enable Input
•
High Input Sensitivity ... 25 mV Max
D, J, OR N PACKAGE
(TOP VIEW)
16
Vcc+
46
lA
•
High Input Impedance
•
MC3450 has Three-State Outputs
•
MC3452 has Open-Collector Outputs
•
Glitch-Free Power-Up/Power-Down
Operation
1Y
EN
2Y
2A
26
GND
description
4A
4Y
Vcc·3Y
3A
36
FUNCTION TABLE
The MC3450 and MC3452 are quadruple
differential line receivers designed for use in
balanced and unbalanced digital data
transmission. The MC3450 and MC3452 are the
same except that the MC3450 has three-state
ouputs whereas the MC3452 has open-collector
outputs, which permit the wire-AND function
with similar output devices. Three-state and
open-collector outputs permit connection
directly to a bus-organized system.
H
Z
DIFFERENTIAL INPUTS
ENABLE
OUTPUT
A-B
EN
y
VID >: 25 mV
L
H
- 25 mV < VIO < 25 mV
VID s 25 mV
L
?
L
L
X
H
Z
=
~
high level, L = low level, ? = indeterminate,
impedance (off)
II
...
II)
CD
>
"iii
u
-...
CD
a:
I I)
The MC3450 and MC3452 are designed for
optimum performance when used with either the
MC3453 quadruple differential line driver or
SN75109A, SN75110A, and SN75112 dual
differential drivers.
CD
>
".::
Q
CD
c
::i
The MC3450 and MC3452 are characterized for
operation from OOC to 70°C.
logic symbols t
MC3450
MC3452
EN
lA
(3)
18
1Y
lA
(3)
18
2A
(5)
28
2A
15)
2Y
1Y
2Y
28
3A
(11 )
38
3Y
3A
(11)
38
4A
(13)
48
4Y
4A
(13)
3Y
4Y
48
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
PRODUCTION DATA documents conllin information
currant .s af publication date. Praducts conform to
spacifications par the tarms of TUls Instruments
==~~i~·{nr:l:ri =:~:f
:.r:::::::.::s not
Copyright @ 1986. Texas Instruments Incorporated
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-35
MC3.450, MC3452
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
logic diagram (positive logic)
!N
1A
121
>-__1;..3.;..1 1Y
111
1B ~~---~-OL'
2A
2B
161
151 2Y
171
1101
3A ~~---~--r~~_~11~11~3Y
191
3B
4A
r""
S"
..
4B
1141
1131 4Y
1151
CD
C
~"
schematics of inpu~s and outputs
~
EQUIVALENT OF
A OR B INPUT
:::a
CD
~
Vcc+-~~-
Vcc+--~e----
TYPICAL OF MC3452
OUTPUT
-----~vcc
3kO
1 kO
NOM
~"
TYPICAL OF MC3450
OUTPUT
EQUIVALENT OF
ENABLE INPUT
1400
NOM
Ul
INPUT
INPUT
OUTPUT
OUTPUT
2000
NOM
Vcc---......-
v c c - - t - - _....-4t-GND--e_------
-4-_. . .-..
-GND
TEXAS.
4-36
INSTRUMENTS
~ST
OFFICE BOX 6fUS012 • DALLAS. TEXAS 76266
L.--"'-GND
MC3450, MC3452
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC + (see Note 1) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Supply voltage, VCC _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 7 V
Differential input voltage (see Note 2) .......................................... ± 6 V
Common-mode input voltage (see Note 3) ....................................... ± 5 V
5.5 V
Enable input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 4):
D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950 mW
J package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package ................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1150 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OoC to 70°C
Storage temperature range ......................................... - 65°C to 1 50°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: Dar N package ......... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . .. 300°C
NOTES:
1.
2.
3.
4.
All voltage values, except differential input voltage. are with respect to network ground terminal.
Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input.
Common-mode input voltage is the average of the voltages at the A and B inputs.
For operation above 25°C free-air temperature, derate the D package to 608 mW at 70°C at the rate of 7.6 mWfoC, the
J package to 656 mW at 70°C at the rate of 8.2 mWfoC, ~nd the N package to 736 mW at 70°C at the rate of 9.2 mWfoC.
In the J package, MC3450 and MC3452 chips are glass mounted.
.
(I)
CI)
>
"Q)
(,)
CI)
recommended operating conditions
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
--..
-5 -5.25
V
">:;
V
C
a:
Supply voltage, VCC+
-4.75
Supply voltage, Vec
2
High-level enable input voltage, VIH
Low-level enable input voltage, VIL
Low-level output current, IOL
0.8
V
-16
mA
5
5
V
Common-mode input voltage, VIC (see Note 5)
-3
3
V
Input voltage range, any differential input to ground
- 5t
3
0
70
Differential input voltage, VID (see Note 5)
Operating free-air temperature, T A
( I)
CI)
>
CI)
c:
::::i
V
°e
t The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for commonmode input voltage.
NOTE 5: The recommended combinations of input voltages fall within the shaded area of Figure 1.
RECOMMENDED COMBINATIONS OF INPUT VOLTAGES
FIGURE 1
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-37
MC3450. MC3452
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
electrical characteristics over recommended operating free-air temperature range,
(unless otherwise noted)
PARAMETER
A inputs
High-level
IIH
B inputs
input current
Low-level
IlL
input current
r-
...~.C
lOS
iii
ICCH+
CD
CD
ICCH-
c!,
1/1
= 0.4 V
VCC± - ±4.75 V, VID - 25 mY,
EI'ii at 0.8 V,
10H = -400 ",A,
-1.6
-1.6
VIL
= - 3 V to 3
VCC±
=
2.4
=
±4.75 V, VOH
Va - 2.4 V
Va - 0.4 V
Short-circuit
VID - 25 mY,
EN at 0.8 V
=
5.25 V
0.5
tpHL
A and B
Y
tpZH
EN
tpZL
EN
tPHZ
EN
Y
Y
Y
Y
Y
Y
EN
EN
tpHL
EN
=
0.5
V
CL
-18
-70
=
=
60
mA
-30
-30
mA
TA
MIN
MC3450
Typt
MAX
50 pF,. See Figure 2
17
25
50 pF, See Figure 2
17
25
CL - 15 pF, See Figure 2
CL
=
50 pF, See Figure 2
CL
=
CL
= 15 pF, See Figure 4
= 15 pF, See Figure 4
CL
mA
60
CL - 15 pF, See Figure 2
CL
p,A
25°C .
TEST CONDITIONS
t All typical values are at VCC + = 5 V, VCC-
4-38
mA
",A
40
Va - 0,
Vee ± .. ± 5 V,
TO
(OUTPUT)
Y
p,A
250
40
V CC _, outputs high
A and B
p,A
mA
V
VCC +, outputs high
Supply current from
FROM
(INPUT)
p,A
-3 V to 3 V
output current
switching characteristics,
UNIT
V
VCC± - ±4.75 V, VIO - -25 mY,
EI'ii at 2 V,
10L = 16 mA,
VIC
tpLZ
-10
EN
VIC
tpLH
1
-10
t All typical values are at VCC+ = 5 V, VCC- = -5 V, TA
:t: Not more one output should be shorted at a time.
tpLH
75
40
-10
High-impedance-state
PARAMETER
30
40
2 V
=
Supply current from
::JJ
75
75
VJD - 2 V
output current:f:
(')
...CD
30
30
VIO
Low-level output
10Z
-2 V
75
B inputs
voltage
CD
30
MC3452
Typt
MAX
A inputs
current
VOL
-2 V
MIN
1
-10
High-level output
S·
=
=
MC3450
Typt
MAX
EN
voltage
10H
VID
VIO
MIN
±5.25 V
VIH - 2,4 V
VIH - 5.25 V
High-level output
VOH
TEST' CONDITIONS
-
Vee ±
15 pF, See Figure 3
-5 V, TA = 25°C.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TEXAS 76265
MIN
MC3452
Typt
MAX
19
25
19
25
21
UNIT
ns
ns
ns
27
18
ns
29
25
ns
25
ns
MC3450, MC3452
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
OUTPUT
5V
390
GENERATOR
(SEE NOTE Al
{l
50 !l
5V
~
FOR
MC3452
.....- -......... 100 mV
CL
(SEE NOTE BI
•
FOR
MC3450
(SEE NOTE CI
TEST CIRCUIT
...
II)
II)
INPUT
>
100 mV
'i)
I
I
CJ
0 V
II)
-...
I
a:
tpHL~
I I)
I
,----"'"'\:-1- - - -
VOH
II)
>
I
'a::
OUTPUT
C
VOL
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR
tf :s: 6 ns.
a. CL includes probe and jig capacitance.
C. All diodes are 1 N916 or equivalent.
VOLTAGE WAVEFORMS
II)
:s: 1 MHz, duty cycle:::; 50%, tr :s: 6 ns,
c:
::i
FIGURE 2. PROPAGATION DELAY TIMES
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75285
4-39
MC3450. MC3452
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
tpZH
tpZL
tpHZ
tpLZ
A
B
100 mV
GNO
GNO
100 mV
m
GNO
100 mV
Sl
Open
Closed
losed
Closed
S2
Closed
Open
Cosed
Closed
(SEE NOTE CI
1 kO
GENERATOR
(SEE NOTE Al
500
TEST CIRCUIT
---'"
I"'"
5'
ENABLE
CD
.
<'
.
c
- - - - - - - 3V
\.5V
I "------ 0 V
tPZH-J.....!
CD
I
"-~ ~
til
~
OUTPUT_ _ _ _ _
CD
n
VOH
__ 0 V
CD
..
~'
.~
til
~3V
ENAB~ _ _ _ _ _ _ _ oV
,~
I
tpLZ~
~~1.5V
OUTPU~~~~ ~~_
VOL
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR
tf S 6 ns.
B. CL includes probe and jig capaCitance.
C. All diodes are 1N916 or equivalent.
s
1 MHz, duty cycle
FIGURE 3. MC3450ENABLE AND DISABLE TIMES
4-40
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
= 50%, tr
S 6 ns,
MC3450, MC3452
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
5V
390 !l
>-....- ...- -
GENERATOR
(SEE NOTE AI
OUTPUT
50 !l
TEST CIRCUIT
ENABLE~'5V
-~.~V-----3V
I
I
I
tpLH~
I
I
~
"i
()
ov
I
I
~
I
tpHL~
-..
CD
a:
I
:-I----vOH
I
OUTPUT
I I)
I
CD
1.5 V
>
";:
C
CD
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR '" 1 MHz. duty cycle
tf '" 6 ns.
B. CL includes probe and jig capacitance.
c
= 50%. tr
'" 6 ns,
::::i
FIGURE 4. MC3452 PROPAGATION DELAY TIMES FROM ENABLE
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
4-41
r
S'
CD
...C
...
<'
CD
Ul
:u
CD
(')
CD
<'
...
CD
Ul
4-42
MC3453
QUADRUPLE LINE DRIVER WITH COMMON ENABLE
03000. FEBRUARY 1986
•
Similar to a Dual Version of SN75110A Line
Drivar
•
Improvad Stability Over Supply Voltage and
Temperature Ranges
•
Constant-Currant Outputs
•
High Output Impedance
D. J, OR N
DUAL-IN-L1NE PACKAGE
(TOP VIEWI
1A
VCC+
1Y
4A
1Z
4Y
2Z
4Z
2Y
3Z
ENABLE
3Y
•
High Common-Mode Output Voltaga Ranga
1-3Vt010VI
•
Glitch-Frae Powar-UpIPowar-Down
Operation
•
TTL Input Compatibility
•
Common Enable Circuit
LOGIC
ENABLE
Designad to be Interchangeable with
Motorola MC3453
INPUT
INPUT
Z
Y
H
H
ON
OFF
•
3A
2A
VCC-
GND
FUNCTION TABLE
description
The MC3453 features four line drivers with a
common enable input. When the enable input is
high, a constant output current is switched
between each pair of output terminals in
response to the logic level at that channel's
input. When the enable is low, all channel
outputs are nonconductive (transistors biased to
cutoff). This minimizes loading in party-line
systems where a large number of drivers share
the same line.
L
L
H
OFF
ON
H
L
OFF
OFF
L
L
OFF
OFF
low logic level
H = high logic level
logic symbol t
lY
The driver outputs have a common-mode voltage
range of - 3 volts to 10 volts, allowing commonmode voltages on the line without affecting
driver performance.
All inputs are diode clamped and are designed
to satisfy TTL-system requirements. The inputs
are tested at 2 volts for high-logic-level input
conditions and 0.8 volt for low-logie-level input
conditions. These tests guarantee 400 millivolts
of noise margin when interfaced with Series
54174 TTL.
=
III
OUTPUT
CURRENT
lA
2A
lZ
2Y
2Z
3Y
3A
3Z
4Y
4A
4Z
tThis symbol is in accordance with ANSIIIEEE Std 91-1984 and
lEe Publication 617-12.
The MC3453 is characterized for operation from
OOC to 70°C.
PRODUCTION DATA doeum.... co.it.in information
cumot I I of publicotion data. Products conform to
spacifications per the terms of raxls Instruments
=:~~atnr:I~tz; ~=::i:r :.r=:::..~~ not
Copyright @ 1986. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75265
4-43
MC3453
QUADRUPLE LINE DRIVER WITH COMMON ENABLE
logic diagram (positive logic)
ENABLE
1Y
1A"";"";---f--I
1Z
2Y
2A----f--I
2Z
3Y
3Z
4Y
4Z
!::
::I
CD
schematics of inputs and outputs
C
:::!,
~
...
-
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
VCC+------~----
, - - - - - - OUTPUT
(II
:a
CD
n
CD
<'
CD
iil
INPUT
_1--..
-1
' - - - - - - OUTPUT
Vcc--i------~-----
-
...- - t l - - - - - - VCC-
GNO ....- - -
4-44
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, -reXAS 75266
MC3453
QUADRUPLE LINE DRIVER WITH COMMON ENABLE
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee + (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Supply voltage, Vee _ ..................................................... - 7 V
Input voltage (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Output voltage range (any output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 5 V to 12 V
Continuous total disSipation at (or below) 25°C free-air temperature (see Note 2):
D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950 mW
J package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025 mW
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ODC to 70 DC
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N package .......... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . .. 300 0
e
NOTES:
1. All voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, derate the D package to 60B mW at 70°C at the rate of 7.6 mW/oC, derate
the J package to 656 mW at 70°C at the rate of B.2 mW/oC, and the N package to 736 mW at 70°C at the rate of 9.2
mW/oC. In the J package the MC3453 is glass mounted.
II
CI)
"-
CD
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VCC+
4.75
5
5.25
V
Supply voltage, VCC-
-4.75
-5 -5.25
V
High-level input voltage, VIH
2
5.5
V
low-level input voltage, VIL
0
O.B
V
V
Common-mode output voltage range
I
VOCR+
0
10
I VOCR-
0
-3
V
0
70
°c
Operating free-air temperature, TA
>
"iii
t.)
CD
a:
CI)
"-
CD
>
.;:
C
CD
r::
:J
NOTE 3: All unused outputs must be grounded.
electrical characteristics over recommended operating free-air temperature range. Vee +
Vee- - -5.25 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VIK
Input clamp voltage
11- -12mA
10(on)
On-state output current
VCC+ = 5.25 V,
VCC+ - 4.75 V,
VCC-
VCC- -
4.75
IO(offl
Off-state output current
VCC+ - 4.75 V,
VCC- -
-4.75 V
IIH
High-level input current
VI
VI
IlL
Low-level input current
VI
ICC+
ICC-
Supply current from V CC _
v
6.5
MAX
UNIT
-0.9
-1.5
V
11
15
11
100
= 5.25 V
= 0.4 V
Enable at 2 V
Enable at 0.4 V
Enable at 2 V
A inputs at 0.4 V
t All typical values are at VCC + = 5 V, VCC-
- 5.25 V
TYpt
2.4 V
A inputs at 0.4 V
Supply current from V CC +
=
-5 V, and TA
Enable at 0.4 V
=
5.25V.
33
mA
~A
40
~A
1
mA
-1.6
mA
50
33
50
-68
-31
-90
-40
mA
rnA
25"C.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
4-45
MC3453
QUADRUPLE LINE DRIVER WITH COMMON ENABLE
switching characteristics. VCC+
=
5 V. VCC- -
PARAMETER
tpLH Propagation delay time, low-to-high-Ievel output
tPHL Propagation delay time, high-to-Iow-Ievel output
tpLH Propagation delay time, low-to-high-Ievel output
tPHL Propagation delay time, high-to-Iow-Ievel output
n.
-5 V.RL'" 50
FROM
TO
TEST
(lNPUn
(OUTPUT)
CONDITIONS
A
Yor Z
A
Enable
Enable
Yor Z
YorZ
CL - 40 pF. TA - 25°C
MIN
TYP
MAX
9
7
15
ns
15
ns
14
25
ns
15
25
ns
See Figure 1
YorZ
UNIT
PARAMETER MEASUREMENT INFORMATION
AINPUT-------------~
, - - - - - - - . - - - - -....- - - OUTPUT Y
p----------ilI----.----
ENABLE - - - - - - - - - - - -__..,
OUTPUT Z
TEST CIRCUIT
A INPUT
-----I:~50%
... rc-.,S--_J
~tw'-+I
I
1
I
I
1
ENABLE
1 ,...--I
I
1
I
'--------'--:- - -- -
I
---14-+1
~tPHL
_-----'T'"I---
I
I
0 V
if-+I-tPHL
I
I
I
I
3V
50%
I
I
I
I
I
tpLH
~-----tw2~
I
I
"'-----oV
I
OUTPUT Y
off
50%
on
,...~lf.....- - - - - - - - - - - - - - off
OUTPUT Z
_1I _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
I
I
tPHL--W-+I
on
i.-.j....tPLH
VOLTAGE WAVEFORMS
NOTES: A. The pulse generators have the following characteristics: Zo = 50 fI, tr = tf = 10 ± 5 ns, tw1 = 200 ns, PRR :s 1 MHz,
tw2 = 1 ~s, PRR :s 500 kHz.
B. CL includes probe "and jig capacitance.
FIGURE 1. PROPAGATION DELAY TIMES
4-46
TEXAS .. "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
_
MC3486
QUADRUPLE LINE RECEIVER WITH 3·STATE OUTPUT
02434, JUNE 1980-REVISED SEPTEMBER 1986
•
Meets EIA Standards RS·422·A and
RS423·A and Federal Standards 1020 and
1030
•
Three·State. TTL-Compatible Outputs
•
Fast Transition Times
•
Operates from Single 5-Volt Supply
•
Designed to be Interchangeable with
Motorola MC3486
D, J OR N PACKAGE
(TOP VIEWI
Vee
1B
1A
4B
1Y
4A
4Y
1,2EN
2Y
3,4EN
2A
3Y
2B
3A
GND
3B
description
The MC3486 is a monolithic quadruple
differential line receiver designed to meet the
specifications of EIA Standards RS-422-A and
RS-423-A and Federal Standards 1020 and
1030, The MC3486 offers four independent
differential-input line receivers that have TTLcompatible outputs, The outputs utilize threestate circuitry to provide a high-impedance state
at any output when the appropriate output
enable is at a low logic level.
The MC3486 is designed for optimum
performance when used with the MC3487
quadruple differential line driver, It is 'supplied in
a 16-pin package and operates from a single
5-volt supply,
•
FUNCTION TABLE (EACH RECEIVERI
DIFFERENTIAL INPUTS
A-8
ENABLE
OUTPUT
Y
H
VID > 0.2 V
H
-0.2 V < VID < 0.2 V
VIO < -0.2 V
H
?
H
L
L
Irrelevant
H = high level, L = low level, Z
(off), ? = indeterminate
...
II)
CI)
>
Z
'Qj
U
= high-impedance
CI)
--...
a:
I I)
logic diagram (positive logic)
CI)
>
'0::;
1,2EN
C
The MC3486 is characterized for operation from
lA
r::
::::i
OOC to 70 c C,
lB
logic symbol t
CI)
2A
2B
(31
lY
(61
(5)
(71
2Y
1,2EN
lA
(31 lY
3.4EN
lB
2A
(51 2Y
3A..!..!~....J""'"
28
(11)
3Y
(13)
4Y
3 B - -..... ~
3.4EN
4A
3A
4 B - -......,~
(111 3Y
38
4A
(131 4Y
48
tThis symbol is in accordance with ANSIIIEEE Std 91-1984 and
lEG Publication 617-12,
PRODUCTION DATA documonls contoin information
currant as of publication date. Products conform to
specifications par the terms of Texas Instrumants
::~=~~i~at::I~tz~ ~!:~~~i:; :1~D::::::~::.s not
Copyright @ 1980. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-47
MC3486
_
QUADRUPLE LINE RECEIVER WITH 3-STATE OUTPUT
schematics of inputs and outputs
EQUIVALENT OF OUTPUT ENABLE
EQUIVALENT OF EACH INPUT
EXCEPT OUTPUT ENABLE
TYPICAL OF ALL OUTPUTS
VCC------~----~--
B5 G VCC
NOM
VCC-----------.~----
8.3 kG
NOM
16.8 kG
NOM
INPUT-JVIfV--l-_~_
OUTPUT ~-...--t
ENABLE
OUTPUT
c:
:::s
CD
C
::::!.
...<
CD
en
:a
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
CD
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8 V
Input voltage, A or B inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±15 V
Differential input voltage (see Note 2) ......................................... ± 25 V
Enable input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8 V
Low-level output current ................................................... 50 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 3):
D package ........ , 950 mW
J package ........ 1025 mW
N package . . . .. . .. 1150 mW
Operating free-air temperature range ...................................... OoC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package ......... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............. 300°C
n
CD
c:!,
...
CD
en
NOTES: 1. All voltage values, except .differential-input voltage, are with respect to network ground terminal.
2. Differential-input voltage is measured at the noninverting input with respect to the corresponding inverting input.
3. For operation above 25°C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the J package, MC3486
chips are glass mounted. In the N package, use the 9.2-mW/oC curve for these devices. In the 0 package, use 7.6 mW/oC curve.
recommended operating conditions
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
Common-mode input voltage, VIC
±7
V
Differential input voltage, VID
±6
V
Supply voltage, VCC
,
High-level enable input voltage, VIH
2
Low-level enable input voltage, VIL
Operating free-air temperature, T A
4·48
0
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855012 • CALLAS. TEXAS 71528&
V
0.8
V
70
°c
MC3486
QUADRUPLE LINE RECEIVER WITH 3-STATE OUTPUT
electrical characteristics over recommended ranges of common-mode input voltage, supply voltage,
and operating free-air temperature (unless otherwise noted)
VTH
VTL
VIK
PARAMETER
Differential-input high-threshold voltage
Differential-input low-threshold voltage
Enable-input clamp voltage
VOH
High-level output voltage
VOL
TEST CONDITIONS
Va - 2.7 V,
Va
10
= 0.5
MIN
= -0.4 rnA
= 8 rnA
MAX
0.2
-0.2T
V,
10
11- -10 rnA
VID* - 0.4 V, 10 - -0.4 rnA,
See Note 4 and Figure 1
-1.5
2.7
VIL - 0.8 V,
10Z
High-impedance-state output current
liB
Differential-input bias current
IIH
High-Ievel'enable input current
IlL
lOS
ICC
Low-level enable input current
VI = 2.7 V
VI - 0.5 V
Short-circuit output current
VID
Supply current
VIL
VIL
= 0.8
V,
=
=
VID
VID
0.5
=
-3 V, Vo
3 V,
VCC = 0 V or 5.25 V,
Other inputs at 0 V
40
-40
-3.25
-1.5
2.7 V
Va = 0.5 V
VI - -10V
VI VI
VI
=
=
-3 V
"1.5
3.25
100
3 V
10 V
VI - 5.25 V
=3
=0
Vo
V,
= 0,
See Note 5
V
V
V
V
VID* = -0.4 V,IO = 8 rnA,
See Note 4 and Figure 1
Low-level output voltage
UNIT
-15
V
p.A
•
rnA
p.A
20
-100
-100
p.A
rnA
85
rnA
~
CD
>
'i
(,)
CD
t The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet for threshold
voltages only.
NOTES: 4. Refer to EIA Standards RS-422-A and R5-423-A for exact conditions.
Q
tpLH
tpZH
tpZL
tpHZ
tpLZ
CD
TEST CONDITIONS
Propagation delay time, high-to-Iow-Ievel output
Propagation delay time, low-to-high-Ievel output
Output enable time to high level
Output enable time to low level
Output disable time from high level
Output disable time from low level
CL
CL
= 15 pF, See Figure 2
= 15 pF, See Figure 3
TEXAS
~
CD
switching characteristics, Vee" 5 V, TA .. 25°e
tpHL
-,~
5. Only one output at a time should be shorted.
PARAMETER
a:
.Jf
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
MIN
TYP
MAX
28
27
35
13
20
26
30
30
35
27
35
30
UNIT
ns
ns
c::
::::i
ns
ns
ns
ns
4-49
MC3486
QUADRUPLE LINE RECEIVER WITH 3·STATE OUTPUT
PARAMETER MEASUREMENT INFORMATION
I
IOH
+(-)
FIGURE 1. VOH. VOL
INPUT
GENERATOR
'see Note AI
r-
5'
51 ()
1.5 V
I
CD
I
--.l tPHLj4-
...o<'
_--~-J -
CD
til
I
1.5V
=
OV
-VOH
OUTPUT
CD
(')
2V----------------~
CD
<'
CD
TEST CIRCUIT
...
en
VOLTAGE WAVEFORMS
FIGURE 2. PROPAGATION DELAY TIMES
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR :s 1 MHz, duty cycle = 50%, tr :s 6 ns,
tf :s 6 ns.
8. CL includes probe and stray capacitance.
4·50
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 752,65
MC3486
QUADRUPLE LINE RECEIVER WITH 3-STATE OUTPUT
PARAMETER MEASUREMENT INFORMATION
-----...,I
SWl
-1.5 V
OUTPUT
I
1.5 V--O
SW2
2 kll
I
D-5V
I
I
(see Note C)
I
I
I
'*
I
I
L ________ J
GENERATOR
(see Note .A)
51 II
CL - 15 pF
II
.
(see Note B)
(/)
TEST CIRCUIT
Q)
>
-(j)
()
Q)
tpZL
tpZH
INPUT
~
I
3V
SWl TO 1.5 V
- -1.5 V SW2 OPEN
SW3 CLOSED
+--OV
tpZH
.
-1-0 V
tpZL
~
-
L1.5
---.I
14--
OUTPUT
--..I
L
---OV
INPUT
kL
OUTPUT
SWl TO 1.5 V
SW2 CLOSED
SW3 CLOSED
II
Q)
c:
::i
1.5 V
SW3 CLOSED
-OV
I
tPLZ~
'-)
I
Q
3V~~~1TO
-1.5V
INPUT
1.5 V
SW2 CLOSED
--OV
f
__
~
0.5 V_ _
SW3 OPEN
>
';:
tpLZ
I
tPHZ~
Q)
-1.5 V
SW2 CLOSED
VOL
3V
1.5 V
I
( /)
~--4.5V
VOH
-1.5 V
tPHZ
--.
V
~_~ ~- SWl TO
---+t l+I
OUTPUT
IN:U:~
a::
VOH
~
~--1.3V
OUTPUT ~0.5 V
~
VOL
-1.3V
VOLTAGE WAVEFORMS
FIGURE 3. ENABLE AND DISABLE TIMES
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR '" 1 MHz, duty cycle = 50%, tr '" 6 ns,
tt .s 6 ns.
.
B. CL includes probe and stray capacitance.
C. All diodes are 1 N916 or equivalent.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-51
•
I"'"
S'
CD
C
::2,
<
CD
Cil
~
CD
n
CD
<'
CD
Cil
4·52
MC3487
QUADRUPLE DIFFERENTIAL LINE DRIVER
WITH 3-STATE OUTPUTS
D2578, MAY 1980-REVISED SEPTEMBER 1986
•
Meets EIA Standard RS-422-A and Federal
Standard 1020
•
Three-State, TTL-Compatible Outputs
•
Fast Transition Times
•
High-Impedance Inputs
•
Single S-Volt Supply
•
Power-Up and Power-Down Protection
•
Designed to be Interchangeable with
Motorola MC3487
0, J, DR N DUAL-IN-liNE PACKAGE
ITOP VIEW)
vee
lA
lY
lZ
1,2EN
2Z
2Y
2A
GNO
4A
4Y
4Z
3,4EN
3Z
3Y
3A
a
description
The MC3487 offers four independent differential line drivers designed to meet the specifications of EIA
Standard RS-422-A and Federal Standard 1020, Each driver has a TTL-compatible input buffered to reduce
current and minimize loading,
...
en
The driver outputs utilize 3-state circuitry to provide high-impedance states at any pair of differential outputs
when the appropriate output enable is at a low logic level. Internal circuitry is provided to ensure a highimpedance state at the differential outputs during power-up and power-down transition times, provided
the output enable is low. The outputs are capable of source or sink currehts of 48 milliamperes,
G)
>
-iii
(,)
G)
The MC3487 is designed for optimum performance when used with the MC3486 quadruple line receiver.
It is supplied in a 16-pin dual-in-line package and operates from a single 5-volt supply,
-...
The MC3487 is characterized for operation from OOC to 70°C,
-~
Ct:
en
G)
>
C
logic symbol t
G)
logic diagram (positive logic)
c
::::l
(2) lV
..... 10-4_1:.:3::...)
(6)
lZ
2V
(5) 2Z
1101 3y
(11) 3Z
(14) 4Y
0-......:.1.:,:13::.) 4Z
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEG Publication 617-12.
PRODUCTION DATA due.mants .ontai. information
.urra.t as of publi••tio. data, Products .onform to
.pacificllion. par th. tarms of T.... Instrum.nts
:.=~~~a{'::I~ =~:~i:; :'l"=~~ not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 865012 • DALLAS, tEXAS 75266
Copyright @ 1980, Texas Instruments Incorporated
4-53
MC3487
QUADRUPLE DIFFERENTIAL LINE DRIVER
WITH 3-STATE OUTPUTS
FUNCTION TABLE (EACH DRIVER,
INPUT
OUTPUT
OUTPUTS
Z
ENABLE
Y
H
H
H
L
L
H
L
H
X
L
High-Impedance
High-Impedance
=
H
TTL high level
L = TTL low level
X
= irrelevant
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
VCC------~------
III
TYPICAL OF ALL OUTPUTS
---------.--------~-VCC
r-
5'
CD
...o
<'
CD
-
gf! NOM
iil
p------t-----.---OUTPUT
::u
CD
n
CD
<'
...
CD
III
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. 8 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .. 5.5 V
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
o package .......................................................... 950 mW
J package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package ........... , .... " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 50 mW
Operating free-air temperature range .............. , . . . . . . . . . . . . . . . . . . . . . .. ooC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J packag'e ............. 300°C
Lead temperature 1,6 mm (1/16 inch) from case for. 10 seconds: 0 and N packages ....... 260°C
NOTES:
1. All voltage values, except differential output voltage, VOD, are with respect to the network ground terminal.
2. For operation above 25°C free-air temperature, refer to the Dissipation Derating Cl:'rves in Appendix A. In the J package,
MC3487 chips are glass mounted. In the N package. use the 9.2-mW/oC curve for these devices,
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
4.75
5
5.25
2
High-level input voltage. VIH
Low-level input voltage. VIL
Operating free-air temperature, T A
4-54
0
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
V
V
0,8
V
70
°C
MC3487
QUDRUPLE DIFFERENTIAL LINE DRIVER
WITH 3-STATE OUTPUTS
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VIK
Input clamp voltage
11= -18 mA
VOH
High-level output voltage
VIL - 0.8 V,
VIH - 2 V,
10H -
VOL
Low-level output voltage
Differential output voltage
VIH - 2 V,
See Figure 1
10L - 48 mA
IVODI
VIL - 0.8 V,
RL - 100!l,
RL = 100 !l,
See Figure 1
Change in magnitude of
alVODI
VOC
differential output voltage t
Common-mode output voltage:l:
Change in magnitude of
20 mA
MAX
-1.5
2.5
V
V
±0.4
V
2
V
RL = 100!l,
See Figure 1
3
V
RL = 100!l,
See Figure 1
±0.4
V
common-mode output voltage t
10
Output current with power off
VCC = 0
High-impedance-state
Output enables
Vo - 2.7V
100
output current
at 0.8 V
Vo - 0.5 V
-100
II
Input current at maximum
input voltage
V
0.5
aivoci
10Z
UNIT
100
Vo = 6 V
-100
Vo = -0.25 V
~A
~A
VI = 5.5 V
100
~A
II
...
Ul
II)
IIH
High-level input current
VI - 2.7 V
50
~A
IlL
Low-level input current
VI - 0.5 V
-400
~A
lOS
Short-circuit output current§
VI = 2 V
Outputs disabled
-140
mA
ICC
Supply current (all drivers)
Outputs enabled,
-40
105
No load
85
mA
>
-i
uII)
a:
-...
Ul
II)
talVODland alvocl are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high
level to a low level.
~In EIA Standard RS-422-A, Voc, which is the average of the two output voltages with respect to ground, is called output offset voltage, VOS.
§Only one output at a time should be shorted and duration of the short-circuit should not exceed one second.
switching characteristics over recommended range of operating free-air temperature. Vee = 5 V
PARAMETER
TEST CONDITION
tpLH
Propagation delay time, low-to-high-Ievel output
tpHL
Propagation delay time, high-to-Iow-Ievel output
CL=15pF,
MIN
See Figure 2
Skew
Differential-output transition time
lTD
tpZH
Output enable time to high level
tpZL
Output enable time to low level
tPHZ
tpLZ
Output disable time from high level
CL = 15 pF,
CL = 50 pF,
See Figure 3
See Figure 4
Output disable time from low level
MAX
20
>
-i::
o
II)
c:
:::i
UNIT
ns
20
ns
6
ns
20
ns
30
ns
30
25
ns
ns
30
ns
PARAMETER MEASUREMENT INFORMATION
FIGURE 1. DIFFERENTIAL AND COMMON-MODE OUTPUT VOLTAGES
TEXAS .."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-55
MC3487
QUADRUPLE DIFFERENTIAL LINE DRIVER
WITH 3·STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
INPUT--A,.s V
SV
200n
f--+--~SW'
GENERATOR
ISeeNotoAI
V OUTPUT
I
I.'PLH ...J
~'PHL '
I
.. ,..---ll---.:t- - - -
VOH
I
,
,
3V'L _ _ _ _ _ _ ....J,
'.5v~l·
I Skew-i-1
I
I Skew-j-l
!--'PHL
IoO-tPLH-+!
I
-=-
ISoo Not. CI
I
f·sv
I
: CL ='s pF
: IS.. Not. BI
'.svll..-_-_-_-_-_-_,_-::
I
--I
VOL
VOH
Z OUTPUT
\,.sv
"s1
-
II
-
-VOL
VOLTAGE WAVEFORM
TEST CIRCUIT
FIGURE 2. PROPAGATION DELAY TIMES
r-
S·
INPUT
;--\---3V
---1
CD
...C<.
GENERATOR
ISo. Not. AI
son
OUTPUT
L-~~
__~____-L
........J
~ _____ ...
3V~-r
CD
Cil
:::0
CL = 'S pF
IS•• Not. BI
!~!
OUTPUT
-1
10%
,0%
~
VOLTAGE WAVEFORMS
TEST CIRCUIT
CD
'---0 V
tTO--: : - --: :-- tTD
FIGURE 3. DIFFERENTIAL-OUTPUT TRANSITION TIMES
(')
CD
<.
CD
r------,
III
I
...
I
I
I
~hLl
Oor3V
GENERATOR
ISo. Noto AI
J
sv
~_~~-M~~OS~W'
__~ .
I
I
'kn
L_____ J
50
200n
(See Not8 C)
n
ISW2
TEST CIRCUIT
OUTPUT
ENABLE
INPUT
t
,I...- - - 0 V
PHZ .... ~
V
~.5
V ~~ closed
,
SW2closed
OUTPUT
t
OUTPUT
3V
-::\,'.S V'-
~...
PLZ-., I
..,.5
V
.. ,.S V
~I SWI closed
----1~ SW2 closed
OUTPUT
;;;;-3V
ENABLE
OVJ.'·~Y
INPUT
tpZL
--r'JL,.5 V ~, closed
OUTPUT
: ~2open
I
VOL
tPZH~ ~
VOH
, ~'open
OUTPUT
,.~ y
closed
=-I I--
----.I
VOL
SW2
VOLTAGE WAVEFORMS
FIGURE 4. DRIVER ENABLE AND DISABLE TIMES
NOTES: A. The input pulse is supplied by a generator having the following characteristics: tr " 5 ns, tf " 5 ns, PRR " 1 MHz, duty
cycle = 50%, Zo = 50 D,
B. Cl includes probe and stray capacitance.
C. All diodes are 1 N916 or 1 N3064,
4-56
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
N8T26
QUADRUPLE BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
02462, MAY 1978-REVISEO
•
P-N-P Inputs for Minimal Input Loading
1200 p.A Maximum)
•
High-Speed Schottky Circuitry
•
3-State Outputs for Driver and Receiver
RE
Vee
1R
DE
•
Party-Line IData-Sus) Operation
18
1D
2R
28
2D
4R
48
4D
3R
38
•
Single S-V Supply
•
Designed to be Interchangeable with
Signetics N8T26. also Called 8T26
1986
0, J, OR N PACKAGE
(TOP VIEW)
GND '-C:.....----'~ 3D
description
The N8T26 is a quadruple transceiver utilizing
Schottky-diode-clamped transistors, Both the
driver and receiver have three-state outputs,
With p-n-p inputs. the input loading is reduced
to a maximum input current of 200 microamperes. This device is capable of high
switching rates into high-capacitance loads and
are suitable for driving long bus lines.
II)
>
(6) 2B
'Q)
(10) 3B
a::
(,)
II)
--.
I II
II)
(13) 48
FUNCTION TABLE (DRIVER)
>
.;:
OUTPUT
DE
0
B
H
L
H
H
H
L
L
X
Z
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
RE ....:..:.'---------
-iii
switching characteristics, Vee = 5 V, TA - 25°e
PARAMETER
FROM
tpLH Propagation delay time, low-to-high-Ievel output
tpHL Propagation delay time, high-to-Iow-Ievel output
B
TO
D
B
tpLZ Output disable time from low level
tpZL Output enable time to low level
RE
R
tpLZ Output disable time from low level
tpZL Output enable time to low level
DE
(,)
TEST CONDITIONS
R
tpLH Propagation delay time, low-to-high-Ievel output
tpHL Propagation delay time, high-to-Iow-Ievel output
a
B
CL = 30 pF,
See Figure 1
MIN
TVP
MAX
8
18
7
10
CL - 300 pF,
14
20
See Figure 2
12
20
CL = 30 pF,
9
17
See Figure 3
15
30
CL = 300 pF,
20
43
See Figure 4
20
38
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
ns
CD
a:
I II
"-
CD
>
';:
ns
C
CD
ns
ns
c:
:::i
4-59
N8T2S
QUADRUPLE BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
2.6V
VCC
TEST
POINT
CIRCUIT
UNDER
TEST
(see Note B)
B
DE
RE
92n
R
D (all)
OPEN
CL = 30 pF
(_NoteC)
GND
•
TEST CIRCUIT
-tot ,.. "Sns
INPUT
r-
i1
~
:;'
~ ~_..:..n~ _ _ 2.6V
90 %
9o%,,--i
1.SV
1.SV1\10%
I4----*tPHL
CD
c
\l"
CD
1/1
--""'
.V-
VOH
-\:\1_._S_V_ _ _ _ _ _ _ _
l._S.JVl
- - - VOL
VOLTAGE WAVEFORMS
OUTPUT
<'""'
OV
tpLH------..
FIGURE 1. PROPAGATION DELAY TIMES FROM BUS TO RECEIVER OUTPUT
::J:J
CD
(')
2.6 V
CD
2.6 V
VCC
<'
CD
TEST
POINT
""'
1/1
CIRCUIT
UNDER
TEST
(See Note B)
DE
RE
D
-=
~
R(all)
OPEN
TEST CIRCUIT
~';Sns
:
INPUT
(see Note D)
B
~
I
10%
i+-<5ns
9 0 % 4 [ 1 - - - -2.6V
1.5 V
10%
0 V
I
I
~tPHL
\.s
tPLH~
, y - - : VOH
I
OUTPUT
-=
~
90%
1.S V
CL = 300 pF
(see Note C)
260n
V
1.57
.... _ _ _ _ _ _ _ _ _J
-
VOL
VOL TAGE WAVEFORMS
FIGURE 2. PROPAGATION DELAY TIMES FROM DRIVER INPUT TO BUS
NOTES:
4-60
A.
B.
C.
D.
The pulse generator in Figures 1 and 2 has the following characteristics: PRR '" 1 0 MHz, duty cycle
All inputs and outputs not shown are open.
CL includes probe and jig capacitance.
All diodes are 1 N9 16 or 1 N3064.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
= SO%, Zout = 50 O.
NUT26
QUADRUPLE BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
2.6V
5V
Vcc
TEST
POINT
RE
0(.111
2.4 kfl
CIRCUIT
UNDER
TEST
(se. Not. B)
DE
240n
R
5kn
(Probe)
GND
CL
= 30 pF
(see Not. D)
(see Not. C)
TEST CIRCUIT
II
..
_<:5n.
: -,'=""..__=~
2.6V
INPUT
UI
)
_
CD
tPL;;Z=-_ _....;;:"'"\
>
-Qi
i /'
OUTPUT
(.l
____""'Y,O%
CD
a::
-.
.
UI
VOLTAGE WAVEFORMS
CD
>
-;:
FIGURE 3. RECEIVER ENABLE AND DISABLE TIMES
Vee
2.6V
o
5V
CD
o (all)
iiE
DE
c:
TEST
POINT
2.4kn
CIRCUIT
UNDER
TEST
(se.Not. B)
70n
:::i
B
R (alii
OPEN
GND
Skn
(Probe)
CL = 300 pF
(se. Not. C)
(see Note D)
TEST CIRCUIT
....... "Sn •
.j,-,=-_.....,.=i=I-L - - - - - 2.6 V
90%
I
)
INPUT
I
I
_ _ _ _~...;..."'~
tPZL
OUTPUT
\.SV
I 110%
)~~--~ tPLZ
10%Y
VOLTAGE WAVEFORMS
FIGURE 4. DRIVER ENABLE AND DISABLE TIMES
NOTES:
A.
B.
C.
D.
The pulse generator in Figures 3 and 4 has the following characteristics: PRR .:5 5 MHz, duty cycle = 50%, Zout "'"' 50 O.
All inputs and outputs not shown are open.
CL includes probe and jig capacitance.
All diodes are lN9l6 or lN3064.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-61
•
4-62
ADVANCE
INFORMATION
SN75061
DRIVER/RECEIVER PAIR WITH SQUELCH
02959. JANUARY 1987
•
IEEE 802.3 1 BASE5 Driver and Receiver
•
On-Chip Receiver Squelch with Adjustable
Threshold
•
OW. J. OR N PACKAGE
(TOP VIEW)
Adjustable Squelch Delay
•
Direct TTL-Level Squelch Output
•
Squelch Circuit Allows for External Noise
Filtering
Vee
DRDLAJ
DRO+
DROSODLAJ
RXI+
RXrSOTHAJ
GND
'DATEN
DRr
DLEN
RXO
SOO
SODU
SORXO
•
Two Driver-Enable Options
•
On-Chip Start-of-Idle Detection and Disable
•
Driver Guarantees 2.0 Volts Minimum into a 50-Ohm Differential Load to Allow for Use with
Doubly-Terminated Lines and Multipoint Architectures
•
On-Chip Driver Slew-Rate Control for Very Closely Matched Output Rise and Fall Times
II
'II)
PIN
NAME
NUMBER
DATEN
15
DESCRIPTION
~
Q)
>
Driver Data Enable. When low. places driver outputs in an active state. When high, the driver outputs
"Qi
are in a high-impedance state if OLEN is also high.
DLEN
13
(,)
Q)
-a:
Driver Delay Enable. When this signal is low and DATEN is high. the driver outputs are active for a
period of time set by DRDLAJ after a positive-going transition on DRI. If there is no active data on DRI,
I I)
~
the outputs are in a high-impedance state.
DRDLAJ
1
Q)
>
";:
Driver Delay Adjust is a connection for the external R-C combination that determines the duration of
the driver output 'active state after a positive transition on DRI when OLEN is low and DATEN is high.
DRI
14
Driver Data Input
Q)
r:::
::i
DRO+
2
Noninverting Driver Output
DRO-
3
Inverting Driver Output
GND
8
Ground. Common for all voltages
RXI+
5
Noninverting Receiver Input
RXI-
6
Inverting Receiver Input
RXO
12
SODLAJ
4
C
Main Receiver Output
Squelch Delay Adjust is a connection for an external R-C combination that determines the duration
of the receiver unsquelch after a negative-going transition on SQDLI.
SODU
10
2:
o
Squelch Delay Input is the input to the one-shot that controls the duration of the receiver unsquelch
period. The main receiver output remains unsquelched as long as
saou
is held high. Timing of the
«i=
unsquelch period begins on the high-to· low transition of SODU.
sao
SORXO
11
9
Squelch Output is high while the receiver is squelched.
:1E
Squelch Receiver Output is high only when the differential receiver input exceeds the threshold set
a:
by SOTHAJ.
SOTHAJ
7
oLL
Squelch Receiver Threshold Adjust. The voltage at this input determines the threshold. of the squelch
receiver in a ratio of - 2. SOTHAJ to threshold. If left open. the squelch receiver threshold defaults
to -600 mV.
Vee
16
2:
Supply voltage input
w
CJ
2:
«
«
c>
Copyright @) 1987. Texas Instruments Incorporated
ADVANCE 'NFORMATION documents contain
~~::::~:rD:;h~~= o,r3:~~~!~~~~:::~~rst1!
ilata and ather spacifications ara subject to change
without notice.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
4-63
SN75061
DRIVER/RECEIVER PAIR WITH SQUELCH
ADVANCE
INFORMATION,
FUNCTION TABLES
RECEIVER§
DRIVER
INPUTS
III
r-'
:i"
INPUTS
OUTPUTS
DRIVER
DATA
DELAY
IN
ENABLE
ENABLE
OUTPUT +
OUTPUT-
L
L
H
L
X
X
L
H
H
L
X
H
H
Z
Z
H
H
L
Ht
Lt
L
H
L
L*
H*
CONDITION
IN+
No active signal'
Active signal'
IN-
OUTPUTS
RECEIVER
SQUELCH
OUT
THRESHOLD
X
X
H
H
L
H
L
L
H
L
H
L
t This condition is valid during the time period set by Driver Delay Adjust following a rising transition on Driver In, Following
this, if no subsequent positive transition occurs on Driver- In, the outputs will go to the high impedance state.
t This condition is valid if it occurs within the enable time set by Driver Delay Adjust after a rising transition on Driver In. Otherwise.
the outputs will be in the high-impedance state.
§ Pins
9 and 10 are tied together.
t
, An active signal is one that has an amplitude greater than the threshold level set by Squelch Threshold Adjust.
logic diagram (positive logic)
CD
SLEW CONTROL
...c
~.
-
DRIVER DATA.:.(1;.,;4;,:.}_ _ _. -_ _ _ _ _ _ _ _ _ _ _..
INPUT, DRI
U;
::u
>-__.....;.(3..;.}
CD
~
:c.
D~VERDATA~11~5;,:.}____+_----------------~~
ENABLE,
...
CD
r - - -.....--'
l5A"I'E'N
INVERTING
DRIVER OUTPUT,
DRO-
DRIVER DELAY (13)
ENABLE, 6LEiiI
III
DRIVER DELAY
ADJUST,DRDLAJ
-:r
....
CT
l>
c
<
l>
NONINVERTING
RECEIVER .:;15::.:}_............_ ...~-+-{,
INPUT, RXI+
INVERTING .;.(6"'}_-+-....
...q/
RECEIVER -
_+-_...
2
om
>-------------------,""" 112} MAIN RECEIVER
OUTPUT, RXO
INPUT, RXI-
-
~l-----t-t-1I~~---II1~1~} SQUELCH
OUTPUT,
2
."
o
::D
~
~
SQUELCH RECEIVER 17}
THRESHOLD -=+-J>M....
ADJUST, SQTHAJ
o
19}
SQUELCH
RECEIVER
OUTPUT,
SQRXO
(10)
SQUELCH
DELAY
INPUT,
SaDL!
SQUELCH
DELAY
ADJUST,
SODLAJ
2
4-64
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
sao
ADVANCE
INFORMATION
SN75061
DRIVER/RECEIVER PAIR WITH SQUELCH
description
The SN75061 is a single-channel driver/receiver pair designed for use in IEEE 802.3, 1BASE5 applications
as well as other general data ,communications circuits. The SN75061 offers the system designer both a
driver and a receiver that are easily configured for use with a variety of controllers and data
encoder/decoders.
The receiver features a full analog squelch circuit with an adjustable threshold and a programmable squelch
delay. Internal nodes of the squelch circuitry are brought out to external connections to allow for the insertion
of noise filtering circuitry of the designer's choice.
As with the receiver, the driver offers the user a variety of implementation options. Driver enabling may
be controlled directly by an external logic input, or by use of an on-chip one-shot that is retriggered as
long as data is being sent to the driver. The driver will then automatically go to the high-impedance state
when end-of-packet occurs. The driver features internal slew-rate control for optimal matching of rise and
fall times allowing for reduction of driver-induced jitter.
receiver
The SN75061 receiver implements full amilog squelch functions by integrating both a separate, parallel
squelch receiver with an externally programmable threshold, and a programmable one-shot. The output
of the squelch receiver and the input to the high-level dc-triggered one-shot are brought out to external
connections. These pins can be shorted for direct implementation, or used for the insertion of noise-filtering
circuitry of the implementer's design. The receiver one-shot can be effectively bypassed by applying a
high logic level to Squelch Delay In. The squelch threshold may be set externally by applying an external
voltage set to a level that is - 2 times the desired threshold voltage. If Squelch Threshold Adjust is left
open, the squelch receiver will default to its internal preset value of - 600 millivolts. The receiver also
outputs a high logic "squelch" signal when there is no active data present at the receiver inputs. When
no data is present on the transmission line, the receiver output assumes a high level. The "unsquelch"
duration is set externally with an R-C combination at Squelch Delay Adjust.
driver
The driver offers the user a variety of implementation options. Driver enabling may be controlled directly
by an active-low external logic input on Data Enable, or by use of another on-chip one-shot that retriggers
with positive-going transitions on the driver input line. If no positive transition occurs within the pulse
duration set by an external R-C combination, the one-shot times out and the driver is automatically put
into a high-impedance state. When operating in the delay-enable mode, the 2-bit-time high-level start-ofidle pulse prescribed by IEEE 802.3 1BASE5 causes the one-shot to time out and automatically place the
driver outputs in the high-impedance state. This delay time is also adjustable for use in other applications.
The driver implements an output slew-rate control that is internally set for nominally 40 mV/ns. (This is
roughly a 1OO-ns peak-to-peak differential transition time.) The driver outputs are capable of driving a 50-ohm
differential load with a guaranteed minimum output level of 2 volts. Short-circuit output current is guaranteed
to be greater than 100 milliamperes.
...
en
4)
>
"i
u
-...
4)
a:
en
4)
>
"~
C
4)
c:
:.:;
z
o
~
<
:E
a:
ou..
-Zw
o
z
~
<
c
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS. TeXAS 75265
4-65
SN75061
DRIVER/RECEIVER PAIR WITH SQUELCH
ADVANCE
INFORMATION
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (any logic input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Receiver differential input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 V
Receiver input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . .. ± 1 5 V
Driver output voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. - 0.5 V to 15 V
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 1):
DW or J package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package ........................................................ 1150 mW
Operating free-air temperature range ...................................... ooC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............. 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package ....... 260°C
NOTE 1: For operation above 25°C free-air temperature. derate the DW and J packages to 656 mW at 70°C at the rate of 8.2 mW/oC,
and the N package to 736 mW at 70°C at the,'ate of 9.2 mW/oC.
.
r-
recommended operating conditions
S'
CD
Supply voltage, VCC
C
Driver high-level input voltage, VIH
...<
Driver low-level input voltage, VIL
(II
Driver low-level output current, tOl
::J:I
Receiver common-mode input voltage, VIC (see Note 2)
n
External timing resistance, Rext
CD
<'
External timing capacitance. Cext
...
Operating free-air temperature, T A
:::!,
CD
NOM
5
CD
MAX
5.25
UNIT
V
v
2
0.8
Driver high-level output current, IOH
CD
(II
MIN
4.75
V
-150
mA
150
mA
-2.5
5
V
5
260
kll
No restriction
0
70
°c
NOTE 2: The algebraic convention, in which the less positive (more negative) limit is designated as minimum. is used in this data sheet
for common-mode input voltage VIC and threshold levels VTH and VTL.
»c
<
»2
("')
m
2
."
o:0
s:»
::!
o2
4-66
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
ADVANCE
INFORMATION
SN75061
DRIVER/RECEIVER PAIR WITH SQUELCH
electrical characteristics over recommended operating free-air and supply voltage range (unless
otherwise notedl
driver
VIK
PARAMETER
Input clamp voltage
TEST CONDITIONS
11= -18 mA
VOD
Differential-output voltage
RL = 50!l
RL = 115!l
MIN
Typt
2
2.4
Change in differential-output voltage
aVOD
for a change in logic input state
High-level input current
VI = 2.4 V
lOS
low-level input current
Short-circuit output current
VI = 0.5 V
Va = 0 V or 6 V. VI = 0.8 V or 2.5 V
10Z
High-Impedance output current
VCC = 5.25 V
IIH
IlL
I
I
±100
MAX
-1.5
3.3
3.65
VOC = 0
V
50
mV
20
-35
pA
±300
VOC-l0V
UNIT
V
pA
mA
100
-100
pA
MAX
-1.5
UNIT
V
receiver
VIK
PARAMETER
Input clamp voltage. squelch delay
VTH Differential-input high-threshold voltage
VTL
Differential-input low-threshold
voltage (see Note 2)
TEST CONDITIONS
11= -18 mA
Va = 2.7 V.
10 = -0.4 mAo
VIC = 5 V
Va = 0.5 V.
10 = 16 mAo
VIC = 5 V
MIN
50
5
RXO
VCC = 4.75 V.
SODLAJ at 0.8 V
SORXO
RXO
VOL
Low-level output voltage
sao
SORXO
IIH
High-level input current
IlL
Low-level input current
SODU
RXO
lOS
'I
Short-circuit output current
mV
50
sao
10H = -400 pA.
10H = -20 ~A.
VIDIRXn = -0.7 V. SODLAJ open
10L - 8 rnA
VCC = 4.75 V.
10L = 16 rnA
SODLAJ at 2 V
10L = 8 mA
VCC = 4.75 V.
IOL=8mA
10L = 16 rnA
VID(RXn = 50 mV
VI = 2.4 V
VCC = 4.75 V.
2.7
2.7
3.5
2.7
4.65
VCC = 5.25 V.
Va = 0
SORXO
VCC - 5 V.
Vo - 0
0.35
-15
-15
-0.8
-1
-570
10
-600
Input resistance
Squelch preset threshold voltage
Ratio of Squelch Threshold Adjust input
voltage to actual squelch threshold voltage
SOTHAJ at 200 mV to 4 V
mV
V
Supply current
Vcc = 5.25 V.
No loads
Driver outputs disabled.
G)
>
"~
a:
fG)
>
";:
C
V
CD
C
~
-1.9
0.5
0.45
0.5
V
20
-35
pA
-85
-100
-1.2
-630
~A
mA
kll
mV
-2.1
driver and receiver
ICC
...
U)
0.45
0.5
VI - 0.5 V
sao
mV
a
G)
-50
Vhvs Hysteresis (VTH - VTL)
VIC Common-mode input voltage
VOH High-level output voltage
TYpt
70
t All typical values are at VCC = 5 V. T A = 25 cc.
NOTE 2: The algebraic convention, in which the less-positive (more negative) limit is designated as minimum, is used in this data sheet
for common-mode input voltage VIC and threshold levels VTH and VTL.
z
i=
o
Q
OLEN at 3 V - - - - ,
C
~
INPUT
OV
~
:iii!:
.......-e---..-DRO +
OUTPUT
n
m
t:>-",--.L-DRO-
-:iii!:
OUTPUT- -
-
f, - -- -~o
I
I
I
t,-+I
j4-
I)A'j'El\i at 0.5 V
."
o
SR-~
-
V
--2V
-+I It- tf
tr or tf
TEST CIRCUIT
VOLTAGE WAVEFORMS
FIGURE 1. DRIVER SLEW RATE MEASUREMENTS
:XJ
s:
l>
--3V
~Cext - 100pF
NOTE A: The input pulse is supplied by a generator having the following characteristics: PRR s 1 MHz, Duty Cycle s 50%, tr s6 ns,
tfs 6 ns, Zout = 50 O.
::!
o
:iii!:
4-68
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEX;4S 75265
ADVANCE
INFORMATION
SN75061
DRIVER/RECEIVER PAIR WITH SQUELCH
PARAMETER MEASUREMENT INFORMATION
5V
Rext - 62 kO
OROLAJ
~
1.5 V
1.5V
--3V
INPUT
OLEN at 3 V - - -....
I
RL 1000
I
too +~ 14-
~-~----~--~ORO+
0 V
too --.j It+-_VO+
OUTPUT
~
OUTPUT
50%
VO_
'-~----*---..L.ORO-
DATEN at 0.5 V
TEST CIRCUIT
VOLTAGE· WAVEFORMS
FIGURE 2. DRIVER DIFFERENTIAL DELAY TIMES
...
UI
Q)
5V
>
'0)
Rext - 62 kO
(,)
Q)
OROLAJ
OLEN at 3 V - - - . . . ,
~
1.5 V
1.5 V
INPUT
+
I
ORIatOVor3V
tpzHH
OUTPUT
3V
---OV
tPHZ~
.
0.5 V
-*-VOH
~
-f
2.3 V
--a:...
UI
Q)
>
";:
C
Q)
c
::::i
VOLTAGE WAVEFORMS
TEST CIRCUIT
FIGURE 3. DRIVER ENABLE AND DISABLE TIMES
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR :s 1 MHz, Duty Cycle :s 50%, tr :s 6 ns,
tf :s 6 ns, Zout ~ 50 0. .
B. CL includes probe and jig capacitance.
C. The input pulse is supplied by a generator having the following characteristics: PRR :s 500 kHz, Duty Cycle :s 50%,
tr:s 6 ns, tf :s 6 ns, Zout ~ 50 0.
2:
o
~
~
a:
oLL
-w
Z
(.)
z
c
"Gi
tt--twlenl-+i 0.5 V
CJ
!"""'-VOH
~
OUTPUT
.
2.3 V
-...
Q)
a:
,.
I II
OV
Q)
>
";:
VOLTAGE WAVEFORMS
C
FIGURE 6. ENABLE DURATION TIME WITH DELAY ENABLE LOW
Q)
c:
::J
5V
Rext - 51 k!l
JNPU~1.5V 1.5V~3V
SOOLAJ
~Cext - 50 pF
•
~---OV
~
RXI+
1.5 V _-,-,R.:.:X;..I--..:..:.:.;c::........-OUTPUT
OUTPUT
I4-ten lRXI
~
1.3V
-
OPEN----I
SOTHAJ
SORXO
VOH
1.3V
-
-VOL
z
o
;:::
«
~
SOOLI
VOLTAGE WAVEFORMS
TEST CIRCUIT
FIGURE 7. RECEIVER ENABLE (UNSQUELCH) TIMES
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR :os; 500 MHz, Duty Cycle s 50%,
tr s 6 ns, tf :s; 6 n5, Zout = 50 n.
B. CL includes probe and jig capacitance.
C. The input pulse is supplied by a generator having the following characteristics: PRR .:5 200 kHz, Duty Cycle .:5 50%, tr .:56 ns,
tp; 6 ns, Zout = 50 !l.
.
a:
ou.
Z
w
(,)
z
c
--="'-....-OUTPUT
1.5 V_---'R.;;.X.;;.I--a
OUTPUT
1.3 V
1.3 V
VOL
OPEN SOTHAJ
•
3V
TEST CIRCUIT
VOLTAGE WAVEFORMS
FIGURE 8. RECEIVER PROPAGATION DELAY TIMES
r:::
::s
5V
CD
.
cr
.
Rext - 51 kn
C
1.5V
1.5V
~
3V
INPUT
CD
~--OV
en
~
It-
t unsq -.(
CD
~
1.5 V--':'::':':"-d
CD
OPEN SOTHAJ
..cr
en
RXO
OUTPUT
~
1.3V
VOH
1.3V
- - -VOL
,--_.;;;.SO"",O~'OUTPUT
TEST CIRCUIT
VOLTAGE WAVEFORMS
FIGURE 9. UNsaUELCH DURATION TIME
»
»<
2
c
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR '" 1 MHz, Duty Cycle", 50%, tr '" 6 ns,
tf '" 6 ns, Zout = 50 n.
B. CL includes probe and jig .capacitance.
C. The input pulse is supplied by a generator having the following characteristics: PRR '" 1 00 kHz, Duty Cycle", 50%,
tr '" 6 ns, tf '" 6 ns, Zout = 50 n.
(")
m
2
."
o
::a
s:
~
(5
2
4-72
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN55107A. SN55107B. SN55108A. SN55108B
SN75107A. SN75107B. SN75108A. SN75108B
DUAL LINE RECEIVERS
02304. JANUARY 1977-REVISED OCTOBER 19B6
•
High Speed
•
Standard Supply Voltage
SN55107A.SN55107B.SN55108A
SN55108B ... J PACKAGE
SN75107A.SN75107B.SN75108A
SN75108B ... D. J. OR N PACKAGE
•
Dual Channels
•
High Common-Mode Rejection Ratio
•
High Input Impedance
•
High Input Sensitivity
•
Differential Input Common-Mode Range of
±3 V
ITOP VIEWI
1A
1B
NC
1Y
1G
5
GND
VCC+
VCC2A
2B
NC
2Y
2G
•
Strobe Inputs for Receiver Selection
•
Gate Inputs for Logic Versatility
•
TTL Drive Capability
•
High DC Noise Margin
•
'107A and '1078 Have Totem-Pole Outputs
~~~~~
•
'108A and '108B Have Open-Collector
Outputs
3
•
SN55107A,SN55107B,SN55108A,
SN55108B ... FK PACKAGE
ITOPVIEWI
..
+ I
UU
NC
NC
1Y
NC
lG
"B" Versions Have Diode-Protected Input
for Power-Off Condition
description
2
en
Q)
>
1 2019
4
18
5
17
6
16
"4)
U
Q)
a:
--.
en
15
Q)
14
8
>
";:
9 10111213
These circuits are TTL-compatible high-speed
line receivers. Each is a monolithic dual circuit
featuring two independent channels. They are
designed for general use as well as such specific
applications as data comparators and balanced,
unbalanced, and party-line transmission
systems. These devices are unilaterally
interchangeable with and are replacements for
the SN55107, SN55108, SN75107, and
SN75108, but offer diode-clamped strobe inputs
to simplify circuit design.
o
(l)QUC!:l>
Q)
ZZNN
c
::;
C!:l
NC-No internal connection
The essential difference between the" A" and" B" versions can be seen in the schematics. Input-protection
diodes are in series with the collectors of the differential-input transistors of the "8" versions. These diodes
are useful in certain "party-line" systems that may have mUltiple Vee + power supplies and may be operated
with some of the Vee + supplies turned off. In such a system, if a supply is turned off and allowed to
go to ground, the equivalent input circuit connected to that supply would be as follows:
INPUT~~
......~~--.t!J-ot---1~:;J.
INPUT --tW"---iI~I--"-"--'
1II"'ILw..J~
"A" VERSION
"B" VERSION
This would be a problem in specific systems that might possibly have the transmission lines biased to
some potential greater than 1.4 volts.
The SN55107A, SN55107B, SN55108A, and SN551088 are characterized for operation over the full
military temperature range of - 55°e to 125°e. The SN751 07A, SN75107B, SN75108A, and SN751088
are characterized for operation from ooe to 70 oe.
Copyright © 1981, Texas Instruments Incorporated
PRODUCTION DATA documents COOlain information
current as of publication date. Products conform
to spe£ificatio.. per the larms of T.... Instruments
standard warranty. ProductiGn processing dOli not
necessarily incluila testing of all paramaters.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-73
SN55107A, SN551078, SN55108A, SN551088
SN75107A, SN751078, SN75108A, SN751088
DUAL LINE RECEIVERS
logic symbols t
SN5510S
SN75108
SN55107
SN75107
s
1A
18
1G
2A
28
2G
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12_
Pin numbers shown are for 0, J, and N packages_
logic diagram (positive logic)
....
5"
..c<"
CD
CD
;
ji
CD
<"
CD
(')
.
o
FUNCTION TABLE
DIFFERENTIAL
INPUTS
A-8
STROBES
G
S
VIO;': 25 mV
- 25 mV < VIO < 25 mV
VIO
s -25 mV
OUTPUT
y
X
X
X
H
L
L
H
X
H
H
Indeterminate
H
H
X
L
L
H
X
H
H = high level, L = low level, X = irrelevant
4-74
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75265
H
L
SN55107A. SN551078. SN55108A. SN551088
SN75107A. SN751078. SN75108A, SN751088
DUAL LINE RECEIVERS
schematic (each receiver)
(141
vCC+~'--'----'---~---'--------~------~~--~
1 kG
1 kG
400 !l
4 k!l
1.6 k!l
I
-"
(1, 121
lA
INPUTS
lB (2.111
3 k!l
3 k!l
.
(II
(131
VCC-~t---~~----+---+-----~--t-----------~
+-_--11--'-=(6::.1
STROBE
S
G)
,~
G)
U
TO OTHER RECEIVER
t R = 1 kll for '107A and '107B, 750 II for '10SA and '10SB.
NOTES: 1. Resistor values shown are nominal.
2. Components shown with dashed lines in the output circuitry are applicable to the '107A and '107B only. Diodes in series
with the collectors of the differential input transistors are short-circuited on '107A and '108A.
-.
G)
a:
( II
G)
>
";:
Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC + Isee Note 3) .,', ..................... , ............... ,.,. 7 V
Supply voltage, VCC _ ......... , ....... , ...... , .. , .. ,.,.................... - 7 V
Differential input voltage Isee Note 4) ........................................•. ± 6 V
Common-mode input voltage Isee Note 5) ........ ,.............................. ± 5 V
Strobe input voltage. , .................. , .... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Continuous total dissipation at lor below) 25°C free-air temperature Isee Note 6):
D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 950 mW
FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1375 mW
J package ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package ............... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11 50 mW
Operating free-air temperature range: Series 55 . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
Series 75 .............................. ooC to 70°C
Storage temperature range ......................................... -65°C to 150°C
Case temperature for 60 seconds: FK package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
Lead temperature 1,6 mm 11/16 inch) from case for 60 seconds: J package ............. 300°C
Lead temperature 1,6 mm 11/16 inch) from case for 10 seconds: D or N package ......... 260°C
NOTES: 3.
4.
5.
6.
G)
c
:.:J
All voltage values, except differential voltages, are with respect to network ground terminal.
Differential voltage values are at the noninverting (A) terminal with respect to the inverting (B) terminal.
Common-mode input voltage is the average of the voltages at the A and B inputs.
For operation above 25°C free-air temperature, derate linearly at the following rates: 7.6 mW/oC for the 0 package, 11.0
mW/oC for the FK package, 8.2 mW/oC for the J package, and 9.2 mW/oC for the N package.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-75
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
recommended operating conditions (see Note 7)
Supply voltage. VCC +
Supply voltage, VCC-
SN75107A.SN75107B
SN5510BA.SN5510BB
SN7510BA.SN7510BB
MIN
MIN
NOM
MAX
5
-5
5.25
V
-5.25
V
NOM
MAX
UNIT
4.5
5
5.5
4.75
-4.5
-5
-5.5
-4.75
0.025
5
0.025
5
V
-5 t
-0.025
-5 t
-0.025
V
Common-mode input voltage, VIC (see Notes 8 and 9)
-3 t
-3 t
Input voltage, any differential input to ground (see Note 8)
-5 t
3
3
3
3
V
V
High-level input voltage between differential inputs,
VIOH (see Note B)
Low-level input voltage between differential inputs,
VIOL (see Note 8)
-
SN55107A.SN55107B
-5 t
V
High-level input voltage at strobe inputs, VIHIS)
2
5.5
2
5.5
Low-level input voltage at strobe inputs. VIL(S)
0
O.B
0
0.8
V
-16
rnA
-16
Low-level output current, IOL
-55
70
125
0
°c
in which the less positive (more negative I limit is designated as minimum, is used in this data sheet for input
Operating free-air temperature, T A
r-
:i"
CD
c...
t The algebraic convention,
voltage levels only.
NOTES: 7. When using only one channel of the line receiver, the strobe G of the unused channel should be grounded and at least one
ci!"
...
CD
of the differential inputs of the unused receiver should be terminated at some voltage between - 3 V and 3 V.
B. The recommended combinations of input voltages fall within the shaded area of the figure shown .
9. The common-mode voltag,e may be as low as -4 V provided that the more positive of the two inputs is not more negative
than -3 V.
til
RECOMMENDED COMBINATIONS
OF INPUT VOLTAGES
::D
CD
(')
CD
~.
U1
o
"0
~
-1
C1 -2
9
«
-3
1-
4
-5
-5 -4 -3-2 -1 0
2 3
Input B to Ground Voltage-V
4-76
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75266
SN55107A. SN55107B. SN5510BA. SN5510BB
SN75107A. SN75107B. SN7510BA. SN7510BB
DUAL LINE RECEIVERS
electrical characteristics over recommended free-air temperature range (unless otherwise noted)
PARAMETER
High-level
IIH
III
IIH
TEST CONDITIONSt
A
r-s
input current
low-level
~
B
input current
VCC±
VCC±
IIH
VCC±
=
MAX,
VCC±
~
MAX,
current into S
VCC± - MAX,
into lG or 2G
current into S
High-level
VOH
Val
MAX
High-level input
Low-level input
III
~
MAX
HighMlevel input current VCC+ ~ MAX,
into lG or 2G
VCC± - MAX,
Low-level input current
III
~
VCC±
VIH(SI
=
30
75
30
30
75
30
~
-5 V
-5 V
VID
=
5V
2.4 V
~
MAX,
Vll(S)
:=
~
MIN,
Vll(S)
= O.B
low-level
output voltage
VCC± ~ MIN,
10l ~ 16 rnA,
=
0.4 V
V, VIOH ~ 25 mY,
-3 V to 3 V
VIH(SI = 2 V,
VIOL
VIC ~ -3Vt03V
MIN,
VCC±
=
MAX
Supply current from
ICCH + VCC +, outputs high
VCC±
=
MAX,
TA
=
25°C
Supply current form
ICCH - V CC _, outputs high
VCC±
=
MAX,
TA
=
25°C
=
75
75
UNIT
pA
-10
-10
-10
-10
40
40
1
1
I'A
rnA
-1.6
-1.6
rnA
BO
BO
2
2
I'A
rnA
-3.2
-3.2
rnA
2.4
I'A
V
-25 mY,
0.4
0.4
VOH ~ MAX VCC+
250
a
Ul
r-
V
ep
p.A
>
'cp
rnA
a:
(,)
ep
Short-circuit
output current §
5 V
=
VIHISI - MAX VCC±
=
lOS
~
VIO
VID
VlllSI = 0.4 V
VCC±
10H ~ -400 p.A, VIC
output current
VIO
VIH(SI - MAX VCC+
VCC±
10H
'10BA, '1088
MIN TYP' MAX
VIH(SI = 2.4 V
output voltage
High-level
'107A, '1078
MIN TYP' MAX
-18
-70
-Ul
r-
30
18
30
rnA
-B.4 -15
-B.4
15
rnA
lB
ep
>
';:
C
ep
c:
::i
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
'All typical values are at VCC+ = 5 V, VCC- = -5 V, TA = 25°C.
§ Not more than one output should be shorted at a time.
-
switching characteristics. VCC+ = ±5 V. TA = 25°C. see Figure 1
PARAMETER
tPlH(O)
tpHl(OI
tplH(SI
tpHllSI
TEST CONDITIONS
=
Propagation delay time, low-to-high-Ievel
Rl = 390 g, Cl
output, from differential inputs A and B
Propagation delay time, high-to-Iow-Ievel
Rl - 390O, Cl - 15 pF
output, from differential inputs A and B
Rl
Rl
=
=
=
50 pF
TYP MAX
17
25
25
390O, Cl
390O, Cl
=
=
50 pF
15 pF
17
390O. Cl
~
50 pF
10
15
B
15
Propagation delay time, low-to-high-Ievel
Rl
output, from strobe input G or S
Rl - 390O, Cl - 15 pF
Propagation delay time, high·-!o-Iow-Ievel
Rl
output. from strobe input G or 5
Rl - 390O, Cl - 15 pF
=
'107A, '1078
MIN
390O, Cl
TEXAS
=
50 pF
~
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TlXAS 7526.
'10BA, '1088
MIN
TYP MAX
19
25
19
25
13
20
13
20
UNIT
ns
n.
ns
ns
4-77
SN55107A, SN55107B, SN5510BA, SN5510BB
SN75107A, SN75107B, SN7510BA, SN7510BB
DUAL LINE RECEIVERS
PARAMETER MEASUREMENT INFORMATION
OIFFERENTI~LL_
INPUT
.
VCC-
r----- 1 ------.,
lAI
.
·-.:.:.:.:I-f.....
I
I
OUTPUT
'107A, '107B
I
I
IV
'=' (See Note 0)
390 n
......
OUTPUT
.----4~"""~-'108A, '108B
~,~e-~e-~
CL~5PF
.5·
CD
STROBE
INPUT
(See Nnte B)
C
:::!.
...<
-
J,(see Note C)
CD
(I)
:CDa
n
TEST CIRCUIT
CD
<.
...
CD
INPUT
A
(I)
~oomv
100mV
I
I
I
I
I
I
~
____J
-----OV
14-----tp2---~
jf--tpl--./
I
I
STROBE
INPUT
G or S
I
I
II
II
-.t
I
tPLH(D)-+/
If-
3V
1.5V
1.5V
'--_ _ _ _ _JJ.
i4- t PHL(O)
I
I
____
0 V
I
O"~M ~""'~ ;,..5-V----~-1.-5'"\(~~:
VOLTAGE WAVEFORMS
FIGURE 1. PROPAGATION DELAY TIMES
NOTES: A. The pulse generators have the folio'wing characteristics: Zout = 50 n, tr = 10 ±S ns, tf = 10 ±S ns, tpdl = 500 ns,
PRR s I MHz, tpd2 = I~s, PRR s 500 kHz.
B. Strobe input pulse is applied to Strobe I G when inputs 11',-1 B are being tested, to Strobe S when inputs 1 A-I B or 2A-2B
are being tested, and to Strobe 2G when inputs 2A-2B are being tested.
C. CL includes probe and jig capacitance.
D. Ali diodes are IN916.
4-78
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
SN551D7A, SN551D7B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
TYPICAL CHARACTERISTICS t
HIGH-LEVEL INPUT CURRENT INTO 1A or 2A
vs
FREE-AIR TEMPERATURE
100
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
6
, 1'10a~
r --(~oaA
I
"
5
>
I
.&
4 f--
>
3
~
~
~
·iPur
-
\
~
~
Nl)"v~rting
Inve,{;ng
Inputs _
_
ao
CJ
60
t---
~
Q.
.5
'107A, '1078
Gi
.,>
2
,
40
..............
-'
l;
J:'"
Vcc:!: - :!:5V
RL-4001l
TA - 25°C
I
o
I
I
0
10
20
30
-- -r-
20
l'
I
-40 -30 -20 -10
J
:!:5V
E
!
:;
\
r\
I
vcc:!: -
'iii
CJ
-75 -50 -25
VID-Differentiallnput Voltage-mV
0
25
50
75
100 125
Q)
a:::
--.
( I)
TA-Free-Air Temperature- °C
Q)
FIGURE 3
SUPPLY CURRENT, OUTPUTS HIGH
vs
FREE-AIR TEMPERATURE
'107A, '1078
PROPAGATION DELAY TIME
(DIFFERENTIAL INPUTS)
vs
FREE-AIR TEMPERATURE
30
I
I
vcc:!: -
FIGURE 2
I
o
Q)
c:
:::i
!
VCC:!:-:!:5V
35 f-RL - 390 Il
CL - 50 pF
30
E
i= 25
ICC+
.
>
Gi
1
Q
"
.'"
rei
-
I
';:
0
"i
Q.
!:!
20
-
r-- tPLH(D}
15
........
~
~
i--=
tPHL(D}
10
IL
5
5
o
-75 -50 -25
0
25
50
75
100 125
o
-75-50 -25
TA-Free-Air Temperature- °C
FIGURE 4
tValues below
ooe
and above 70
0
e apply
0
25
50
75
100 125
T A - Free-Air Temperature - °C
FIGURE 5
to SN55 Series only.
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
4-79
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN7510BA, SN75108B
DUAL LINE RECEIVERS
TYPICAL CHARACTERISTICSt
'108A, '108B
'108A, '108B
PROPAGATION DELAY TIME, LOW-TO-HIGH LEVEL
(DIFFERENTIAL INPUTS)
vs
FREE-AIR TEMPERATURE
120
VCC±-±5V
c
CL-15pf
I 100
PROPAGATION DELAY TIME, HIGH-TO-LOW LEVEL
(DIFFERENTIAL INPUTS)
vs
FREE-AIR TEMPERATURE
40
.
..E
j::
>
to
'ii
80
RL - 3900 {)
0
-
I--- L--
c
i
r
I
r
60
CI
to
Q.
r-
:i"
CD
...c
£I
40
r-
Q
:E
-'
20
S-
~.
R
-
I
0
25
.
I
E
../'"
,.....,
CL - 15 pf
30
RL - 390 {) '-
25
~
20
£I
75
/
15
CD
(')
Q 10
:r::
S-
5
o
-75-50 -25
100 125
c
I
30
~
25
~
RL-390{)
CL - 50 pf
.
c
..E
I
Q.
£
20
VCC±=±5V
RL=390{)
CL - 15 pf
30
25
>
'ii 20
0
-----
15
tPLH(S)
....
10
o
J r
t7HL(S!
5
r--
-75 -50 -25
tValues below
ooe
c
..
.g
t~(S)
15
CI
Q.
£
10
...t-
tPHL(S)
5
-----
....- . /
/'
/
o
0
25
50
75
TA - free-Air Temperature fiGURE 8
4-80
35
to
0
to
CI
CD
100 125
j::
c
-.,
75
40
>
0
50
PROPAGATION DELAY TIME (STROBE INPUTS)
vs
FREE-AIR TEMPERATURE
Vd±_1±5~
..
.
25
'108A, '108B
'107A, '107B
35
0
TA-free-Air Temperature- °C
fiGURE 7
PROPAGATION DELAY TIME (STROBE INPUTS)
vs
FREE-AIR TEMPERATURE
40
UI
1
:::;
CD
cr
...CD
lJ
RL - 1950 {)
RL = 3900 {)
TA-free-Air Temperature- °c
fiGURE 6
:XJ
\
CI
to
Q.
50
I
>
..
c
.,8
.
.!!
0
----
RL - 390 {)
I
~
I
c 35 f- VCC± - ±5 V
j::
V
50
I
O
-75 -50 -25
...
UI
~
--
V
I
..
100 125
-75 -50 -25
°c
0
25
50
75
100 125
TA - free-Air Temperature- °C
FIGURE 9
and, above 70 0 e apply to SN55 Series only.
TEXAS . "
INSTRUMENTS
POST OFFICE bOX 85&012 • DALLAS, TaXAS 712ee
SN55107A, SN551078, SN55108A, SN551088
SN75107A, SN751078, SN75108A, SN751088
DUAL LINE RECEIVERS
TYPICAL APPLICATION DATA
basic balanced-line transmission system
The' 107 A, '1 07B, '1 OSA, and' 1OSB dual line circuits are designed specifically for use in high-speed data
transmission systems that utilize balanced, terminated transmission lines such as twisted-pair lines. The
system operates in the balanced mode, so noise induced on one line is also induced on the other. The
noise appears common-mode at the receiver input terminals where it is rejected. The ground connection
between the line driver and receiver is not part of the signal circuit so that system performance is not
affected by circulating ground currents.
The unique driver-output circuit allows terminated transmission lines to be driven at normal line impedances.
High-speed system operation is ensured since line reflections are virtually eliminated when terminated lines
are used. Crosstalk is minimized by low signal amplitudes and low line impedances.
The typical data delay in a system is approximately (30 + 1.3 L) nanoseconds, where L is the distance
in feet separating the driver and receiver. This delay includes one gate delay in both the driver and receiver.
Data is impressed on the balanced-line system by unbalancing the line voltages with the driver output
current. The driven line is sel.ected by appropriate driver-input logic levels. The voltage difference is
approximately:
II
...
I/)
II)
>
VDIFF .. 1/2IO(on) • RT·
'iii
High series line resistance will cause degradation of the signal. The receivers, however, will detect signals
as low as 25 mV (or less). For normal line resistances, data may be recovered from lines of several thousand
feet in length.
-...
Line-termination resistors (RT) are required only at the extreme ends of the line. For short lines, termination
resistors at the receiver only may prove adequate. The signal amplitude will then be approximately:
'0::
to)
II)
a:
I /)
II)
>
C
II)
VDIFF .. 10(on) • RT·
RT
r:::
:.:::i
RT
RT
A
_..r--....
DATA INPUT
TRANSMISSION LINE HAVING
CHARACTERISTIC IMPEDANCE Zo
RT = lO/2
B-"'1-_"
INHIBIT
C--r--...
D -......._ ,
DRIVER
SN55109A.SN55110A.
SN75109A.SN75110A.
SN75112
y
~~--------L--------~
STROBES
RECEIVER
·107A. ·107B. ·108A. '108B
FIGURE 10
data-bus o.r party-line system
The strobe feature of the receivers and the inhibit feature of the drivers allow these dual line circuits to
be used in data-bus or party-line systems. In these applications, several drivers and receivers may share
a common transmission line. An enabled driver transmits data to all enabled receivers on the line while
other drivers and receivers are disabled. Data is thus time-multiplexed on the transmission line. The device
specifications allow widely varying thermal and electrical environments at the various driver and receiver
locations. The data-bus system offers maximum performance at minimum cost.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DAL.LAS. TeXAS 75265
4-S1
SN55107A. SN551078. SN5510BA. SN5510B8
SN75107A. SN751078. SN7510BA. SN7510B8
DUAL LINE RECEIVERS
TYPICAL APPLICATION DATA
RECEIVER 4
RECEIVER 2
RECEIVER 1
DRIVERS
SN55109A. SN55110A.
SN75109A. SN76110A.
SN76112
v
v
STROBES
RT
STROBES
STROBES
LOCATION 2
DRIVER 1
A
DATA INPUT B
A
C
c
o
DRIVER 3
DRIVER 4
LOCATION 3
LOCATION 4
Ii
INHIBIT 0
LOCATION 1
RECEIVERS:
·107A. ·107B.
·108A. '108B
FIGURE 11
unbalanced or single-line systems
These dual line circuits may also be used in unbalanced or single-line systems. Although these systems
do not offer the same performance as balanced systems for long lines, they are adequate for very short
lines where environmental noise is not severe.
The receiver threshold level is established by applying a dc reference voltage to one receiver input terminal.
The signal from the transmission line is applied to the remaining input. The reference voltage should be
optimized so that signal swing is symmetrical about it for maximum noise margin. The reference voltage
should be in the range of - 3 volts to 3 volts. It can be provided by a voitage supply or by a voltage divider
from an available supply voltage.
A single-ended output from a driver may be used in single-line systems. Coaxial or shielded line is preferred
for minimum noise and crosstalk problems. For large signal swings. the high output current (typically 27 mAl
of the SN75112 is recommended. Drivers may be paralleled for higher current. When using only one channel
of the line drivers. the other channel should be inhibited and/or have its outputs grounded.
SN55109A.SN55110A
SN75109A,SN75110A
SN75112
INPUT
A
'107A, '107B
OUTPUT
INPUT~
B-<--~
Vref--«../"
INHIBIT C
STROBES
D-<--~
FIGURE 12
4-82
~OUTPUT
TEXAS . "
INSTRUMENTS
POST OFFice BOX 655012 • DALLAS, TEXAS 75266
SN55101A, SN551018, SN55108A, SN551088
SN15101A, SN151018, SN15108A, SN151088
DUAL LINE RECEIVERS
TYPICAL APPLICATION DATA·
'108A, '1088 dot-AND output connections
The '1 08A, '1088 line receivers feature an opencollector-output circuit that can be connected in
the dot-AND logic configuration with other
similar open-collector outputs. This allows a level
of logic to be implemented without additional
logic delay.
b--If++-OUTPUT
SN5401/SN7401 0' equivalent
II
.
FIGURE 13
II)
increasing common-mode input voltage range of receiver
CI)
The common-mode voltage range or CMVR is defined as the range of voltage applied simultaneously to
both input terminals that if exceeded does not allow normal operation of the receiver.
>
'G:j
CJ
CI)
a:
The recommended operating CMVR is ± 3 volts, making it useful in all but the noisiest environments. In
extremely noisy environments, common-mode voltage can easily reach ± 10 V to ± 15 V if some precautions
are not taken to reduce ground and power supply noise, as well as crosstalk problems. When the receiver
must operate in such conditions, input attenuators should be used to decrease the system common-mode
noise to a tolerable level at the receiver inputs. Differential noise is also reduced by the same ratio.
--.
These attenuators have been intentionally omitted from the receiver input terminals so the designer may
select resistors that will be compatible with his particular application or environment. Furthermore, the
use of attenuators adversely affects the input sensitivity, the propagation delay time, the power dissipation,
and in some cases (depending on the selected resistor values) the input impedance, therefore reducing
the versatility of the receiver.
CI)
The ability of the receiver to operate with
approximately ± 1 5 volts common-mode voltage
at the inputs has been checked using the circuit
shown in Figure 14. The resistors R1 and R2
provide a voltage divider network. Dividers with
three different values presenting a 5-to-1
attenuation were used so as to operate the
differential inputs at approximately ± 3 volts
common-mode voltage. Careful matching of the
two attenuators is needed so as to balance the
overdrive at the input stage. The resistors used
are shown in Table A.
=
2 kIt R2
= 0.5
DEVICE
PARAMETERS
-
tPLH
'107A, '107B
tpHL
R1 = 6 kG, R2 = 1.5 kG
Attenuato, 3:
Rl
=
12 kG, R2
=
'108A, '108B
3 kG
tpHL
Table B shows some of the typical switching
results obtained under such conditions.
TEXAS . "
INSTRUMENTS
POST OFfICE BOX 655012 • DALLAS. TEXAS 75265
INPUT
ATTENUATOR
TYPICAL
(ns)
1
20
2
32
3
42
1
22
2
31
3
33
1
36
2
47
3
57
1
29
2
38
3
41
c::
:::i
SHOWN IN FIGURE 14
kG
R1
>
C
RECEIVER WITH ATTENUATOR TEST CIRCUIT
tpLH
Attenuata, 2:
CI)
'0:::
TABLE B. TYPICAL PROPAGATION DELAYS FOR
TABLE A
Attenuata, 1:
I I)
4-83
SN55107A. SN551078. SN55108A. SN551088
SN75107A. SN75107~ SN75108A. SN751088
DUAL LINE RECEIVERS
TYPICAL APPLICATION DATA
~V
---"Or
+16V}
+14 V
5V
ONE
ATTENUATOR
ON EACH
INPUT
R1
R2
- 16 V -----./
+15 V
OR
-15 V
...,..,Io--....--J
R1
+5V
R2
FIGURE 14. COMMON-MODE CIRCUIT FOR TESTING INPUT ATTENUATORS.
WITH RESULTS SHOWN IN TABLE B
Two methods of terminating a transmission line to reduce reflections are:
~:d:~
R1
R3 - R1 + R2 - ZO/2
METHOD 2
R1
~1-:3_3_-'V'""R_2
....R_2...J
ill
R1 + R2 > > Zo
R3 - ZO/2
FIGURE 15
The first method uses the resistors as the attenuation network and line termination. The second method
uses two additional resistors for the line terminations.
4-84
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS, TEXAS 75265
8N55107A, 8N551078, 8N55108A, 8N551088
8N75107A, 8N751078, 8N75108A, SN751088
DUAL LINE RECEIVERS
TYPICAL APPLICATION DATA
For party-line operation. method 2 should be used as follows:
II
FIGURE 16
II)
To minimize the loading. the values of R1 and R2 should be fairly large. Examples of possible values are
shown in Table A.
~
G)
>
"i
(J
G)
furnace control using the SN75108A
The furnace control circuit in Figure 17 is an example of the possible use of the SN551 07 A Series in areas
other than what would normally be considered electronic systems. Basically the operation of this control
is as follows. When the room temperature is below the desired level. the resistance of the room temperature
sensor is high and channel 1 noninverting input is below (less positive than) the reference level set on
the input differential amplifier. This situation causes a low output. operating the "heat on" relay and turning
on the heat. The channel 2 noninverting input is below the reference level when the bonnet temperature
of the furnace reaches the desired level. This causes a low output. thus operating the blower relay. Normally
the furnace is shut down when the room temperature reaches the desired level and the channel 1 output
goes high. turning the heat off. The blower remains on as long as the bonnet temperature is high. even
after the "heat on" relay is off. There is also a safety switch in the bonnet that shuts the furnace down
if the temperature there exceeds desired limitations. The types of temperature-sensing devices and biasresistor values used are determined by the particular operating conditions encountered.
IX
'"'U)
~
G)
>
".:
Q
G)
c:
:::I
5V
BONNET
ROOM
BONNET UPPER
TEMP
SENSOR
TO "HEAT ON"
RELAY
RETURN
TO BLOWER
RELAY
RETURN
FIGURE 17. FURNACE CONTROL USING SN75108A
TEXAS . "
INSTRUMENTS
I'OST O~Flce BOX 865012 " DALLAS, tExAS 7&261
4-85
SN55107A, SN551078, SN55108A, SN551088
SN75107A, SN751078, SN75108A, SN751088
DUAL LINE RECEIVERS
TYPICAL APPLICATION OATA
repeaters for long lines
In some cases, the driven line may be so long that the noise level on the line reaches the common-mode
limits or the attenuation becomes too large and results in poor reception. In such a case, a simple application
of a receiver and a driver as repeaters [shown in Figure 18(a)) restores the signal level and allows an adequate
signal level at the receiving end. If multichannel operation is desired, then proper gating for each channel
must be sent through the repeater station using another repeater set as in Figure 18(b).
REPEATERS
D~;A
DRIVER
q=l
RECEIVER
H
DRIVER
4=J
P
•
RECEIVER
r
DATA
OUT
P
8. SINGLE-CHANNEL LINE
DATA
OUT
DATA
IN
r5'
CD
CLOCK
IN
.
.
C
P
p
<'
CD
-
-j
~::=;-'A~==~\________.:........-....
b. MULTICHANNEL LINE WITH STROBE
en
FIGURE 18. RECEIVER-DRIVER REPEATERS
:xl
CD
C'l
CD
.
receiver as dual differential comparator
<'
CD
en
There are many applications for differential comparators, such as voltage comparison, threshold detection,
controlled Schmitt triggering, and pulse width control .
As a differential comparator, a '1 07A or '108A may be connected so as to compare the noninverting input
terminal with the inverting input as shown in Figure 19. Thus the output will be· high or low resulting from
the A input being greater or less than the reference. The strobe inputs allow additional control over the
circuit so that either output or both may be inhibited.
STROBE 1
OUTPUT 1
REFERENCE 1
STROBE 1.2
OUTPUT 2
REFERENCE 2
FIGURE 19. SN55107A SERIES RECEIVER AS A DUAL DIFFERENTIAL COMPARATOR
4-86
"TEXAS ..,.
INsrRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN55107A. SN55107B. SN55108A. SN55108B
SN75107A. SN75107B. SN75108A. SN75108B
DUAL LINE RECEIVERS
TYPICAL APPLICATION DATA
window detector
The window detector circuit in Figure 20 has a large number of applications in test equipment and in
determining upper limits, lower limits, or both at the same time - such as detecting whether a voltage
or signal has exceeded its limits or "window". Illumination of the upper-limit (lower-limit) indicator shows
that the input voltage is above (below) the selected upper (lower) limit. A mode selector is provided for
selecting the desired test. For window detecting, the "upper and lower limits" test position is used.
5V
+5 V -5 V
, kO
UPPER
JC>-:---t--'vv......-::I:-F".'lIMIT
INDICATOR
SET
UPPER
LIMIT
INPUT
FROM
TEST
POINT
'::'
LOWER
JC>-'--i---"M,....-::I-F"" LIMIT
INDICATOR
SET
~~~iR
•
II)
~
CD
>
"Q)
kO
_ ' /
L -,o4.=3++-___-e. . 4......."'7/1okO
......
2
4.7 kO
4.7 kO
CJ
CD
--...
a:
I I)
CD
MODE
SELECTOR
>
";::
MODE SELECTOR LEGEND
o
CD
POSITION
CONDITION
OFF
2
TEST FOR UPPER LIMIT
3
TEST FOR LOWER LIMIT
4
TEST FOR UPPER AND LOWER LIMITS
c:
:.J
FIGURE 20. WINDOW DETECTOR USING SN75108A
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-87
SN55107A, SN55107B, SN55108A, SN551088
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
TYPICAL APPLICATION DATA
temperature controller with zero-voltage switching
The circuit in Figure 21 switches an electric resistive heater on or off by providing negative-going pulses
to the gate of a triac during the time interval when the line voltage is passing through zero. The pulse
generator is the 2N5447 and four diodes. This portion of the circuit provides negative-going pulses during
the short time (approximately 100 /Ls) when the line voltage is near zero. These pulses are fed to the inverting
input of one channel of the '1 08A. If the room .temperature is below the desired level, the resistance of
the thermistor is high and the noninverting input of channel 2 is above the reference level determined by
the thermostat setting. This. provides a high-level output from channel 2. This output is ANO'ed with the
positive-going pulses from the output of channel 1, which are reinverted in the 2N5449.
r
r-
5'
C1)
...c
...<'
+
5·V
ZENER
120 V TO
220 v
60 Hz
C1)
-III
::J:I
C1)
n
C1)
<'
...
C1)
III
HEATER
LOAD
FIGURE 21. ZERO-VOLTAGE SWITCHING TEMPERATURE CONTROLLER
4-88
TEXAS •
INSTRUMENTS
POST OFFICE BOX 65801 • • DAL... S. TeXAS 7&265
SN55109A, SN55110A,
SN75109A, SN75110A, SN75112
DUAL LINE DRIVERS
D2106, DECEMBER 1975-REVISED SEPTEMBER 1986
•
Improved Stability over Supply Voltage and
Temperature Ranges
•
Constant-Current Outputs
•
High Speed
•
Standard Supply Voltages
•
High Output Impedance
•
High Common-Mode Output Voltage Range
(-3 V to 10 VI
•
TTL Input Compatibility
•
Inhibitor Available for Driver Selection
SN55109A, SN55110A, . . . J PACKAGE
SN75109A, SN75110A, SN75112 .
D, J, OR N PACKAGE
(TOP VIEWI
lA
lB
lC
2C
2A
2B
GND
VCC+
IV
lZ
VCCD
2Z
2V
SN55109A, SN55110A ... FK PACKAGE
II
(TOP VIEWI
-55°C to 125°C
OOC to 70°C
OUTPUT
J or FK PACKAGE
J or N PACKAGE
FUNCTION
SN55109A
SN75109A
SN55110A
SN75110A
SN75112
+
U
co
~~Z>~
6-rnA Current
II)
Switch
3
12-mA Current
lC
NC
2C
NC
2A
Switch
27-mA Current
Switch
description
logic symbol t
lC
(31
~
1 20 19
Q)
4
18
5
6
16
7
15
>
'(j)
17
CJ
Q)
a:
-I I)
14
8
9
The SN55109A, SN55110A, SN75109A,
SN75110A, and SN75112 have improved
output current regulation with supply voltage
and temperature variations. In addition, the
higher current of the SN75112 (27 rnA) allows
data to be transmitted over longer lines. These
drivers offer optimum performance when used
with the SN55107A, SN55108A, SN75107A,
and SN75108A line receivers.
2
~
Q)
1011 1213
>
'0:
C
Q)
c::
::;
NC - No internal connection
logic diagram (positive logic)
&
lA (11
lB (21
lC (3)
2C
D (101
(1)
lA
(2)
lB
2A (51
2B
(6)
(131
IV
lZ
2C (4)
2V
2A (5)
2Z
2B (6)
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
lED Publication 617-12.
Pin numbers shown are for 0, J, and N packages.
PRODUCTION DATA documents contain information
currant as of publication datB. Products conform to
specifications per the terms of Taxas Instruments
:~~~~:~~i~ar::1~78 ~=~:i:f :'~O:::::::t::'s-:S not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1986, Texas Instruments Incorporated
4-89
SN55109A, SN55110A
SN75109A, SN75110A, SN75112
DUAL LINE DRIVERS
description (continued)
These drivers feature independent channels with common voltage supply and ground terminals. The
significant difference between the three drivers is in the output current specification. The driver circuits
feature a constant output current that is switched to either of two output terminals by the appropriate
logic levels at the input terminals. The output current can be switched off (inhibited) by low logic levels
on the enable inputs. The output current is nominally 6 milliamperes for the' 109A, 12 milliamperes for
the' 1 lOA, and 27 milliamperes for the SN75112.
The enable!inhibit feature is provided so the circuits can be used in party-line or data-bus applications.
A strobe or inhibitor (enable 0), common to both drivers, is included for increased driver-logic versatility.
The output current in the inhibited mode, 10(off), is specified so that minimum line loading is induced when
the driver is used in a party-line system with other drivers. The output impedance of the driver in the inhibited
mode is very high-the output impedance of a transistor biased to cutoff.
•
r-
:i"
CD
...c
CD
...<"
en
-
The driver outputs have a common-mode voltage range of - 3 volts to 10 volts, allowing common-mode
voltage on the line without affecting driver performance.
All inputs are diode clamped and are designed to satisfy TTL-system requirements. The inputs are tested
at 2.0 volts for high-logic-level input conditions and 0.8 volt for low-logic-level input conditions. These
test guarantee 400 millivolts of noise margin when interfaced with Series 54/74 TTL.
The SN551 09A and SN5511 OA are characterized for operation over the full military temperature range
of - 55 DC to 125 DC. The SN75109A, SN75110A, and SN75112 are characterized for operation from
oDe to 70 De.
FUNCTION TABLE lEACH DRIVER)
:::D
~
ENABLE
LOGIC
INPUTS
CD
...<"
en
CD
B
C
D
y
Z
x
L
X
OFF
OFF
X
L
OFF
OFF
L
X
X
X
H
ON
OFF
X
L
ON
OFF
H
H
H
H
H
OFF
ON
X
H
OUTPUTSt
INPUTS
A
= high level,
H
H
L
=
low level, X
=
irrelevant
t When using only one channel of the line drivers, the
other channel should be inhibited and/or have its
outputs grounded.
4-90
TEXAS .",
INSTRUMENTS
POST OFFice BOX 855012 • DALLAS. TEXAS
762~5
SN55109A, SN55110A
SN75109A, SN75110A, SN75112
DUAL LINE DRIVERS
schematic leach driver)
vcc+...!1c.::14::!)........._~_ _~
ENABLE C ..:.13::":'..,;;4;...)-41,...J(
ENABLE D .,!.11;..:O:.:..)_-I-..
•
..
INPUT A .;,11;,:..';0;5),......-1
INPUT B ~2~,.!!.64~
(II
GNDlI7~)~f.~====~r--1
G)
>
'Q)
U
G)
I
COMMON TO BoTH DRiVERS I
I
I
I
VCC_:.:..11~1;...).-~_ _ _ _~
a::
--.
( II
G)
>
.;:
C
G)
c:
:::i
W...
'V...
VCC+bUS
VCC_bUS
L _ _ _ _ _ _ _ _ _ _ .J
~--:.......".-..:..--..:.....;..,
TO OTHER DRIVER
Pin numbers shown are for D, J, and N packages.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
4-91
SN55109A. SN55110A
SN75109A. SN75110A. SN75112
DUAL LINE DRIVERS
absolute maximum ratings over operating free-air temperature range ·(unless otherwise noted)
VCC+
SN55109A
SN75109A
SN55110A
SN75110A
SN75112
UNIT
7
-7
7
-7
7
-7
V
5.5
5.5
5.5
V
-5 to 12
-5 to 12
-.5 to 12
V
Supply voltage (see Note 1)
VCC- Supply voltage
Input voltage
VI
Output voltage range
D package
950
Continuous total dissipation at (or below) FK package
1375
25 DC free-air temperature (see Note 2)
1375
J package
N package
55 to 125
Operating free-air temperature range
•
r-
:i'
-65 to 150
Storage temperature range
Case temperature for 60 seconds: FK package
260
Lead temperature 1,6 mm (1116 inch) from case for 60 seconds: J package
300
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
NOTES:
CD
...c
<'
CD
iil
~
CD
n
CD
<'
CD
...en
4-92
V
1025
1025
1150
1150
o to
mW
o to 70
DC
-65 to 150
-65 to 150
DC
300
260
300
260
260
260
70
DC
IIDN package
package
DC
DC
1. Voltage values are with respect to network ground terminal.
2. For operation above 25 DC free-air temperature, refer to Dissipation Derating Table. In the J package, SN551 09A and SN5511 OA
chips are alloy mounted, and SN75109A and SN75110A chips are glass mounted.
DISSIPATION DERATING TABLE
PACKAGE
0
FK
J (Alloy-mounted chip)
J (Glass-mounted chip)
N
POWER
DERATING
RATING
FACTOR
7.6 mW/oC
ABOVE
950 mW
1375 mW
11.0 mW/oC
TA
25°C
25 DC
1375 mW
11.0 mW/oC
25°C
1025 mW
8.2 mW/oC
25°C
1150mW
9.2 mW/oC
25°C
. TEXAS .",
INSTRUMENTS
POST OFFICE BOX 655012 .. DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN75109A.
SN65109A.
SN75110A
SN56110A
Supply Voltage
Supply voltage
Vcc-
NOM
MAX
MIN
NOM
MAX
4.75
5
5.25
-4.75
-5
-5.25
2:
ooe
4.5
5
5.5
TA <
ooe
4.75
5
5.5
TA
OOC
-4.5
-5
-5.5
TA < O°C
-4.75
-5
-5.5
TA
Vee +
2:
0
10
0
10
V
0
-3
0
-3
V
High-level input voltage, V,H
2
0.8
V
70
'c
0.8
-55
125
"'hlZ
NOTE 3: When using only one channel of the line drivers, the other channel should be inhibited andlor have its outputs grounded.
~rn
~-l
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
~;;C~
,;C~
;~
1'("1"1
~~4r
~
'"
~
'"'"
'"'"
SN75109A
MIN
Input clamp voltage
10(on}
On-state output current
1010ffi
Off-state output current
IIH
VCC±
VCC±
Input current at maximum
II
VCC±
input voltage
High·level input current
VCC± - MIN.
A, B. or C inputs
o input
e. or C inDuts
low·level input current
VCC±
A,
o input
A,
IlL
= MIN.
= MAX.
= MIN.
e,
VCC±
or C inputs
o input
=
MAX.
= MAX.
VCC±
= MAX.
VCC±
= MAX.
ICC+(on)
Supply current from VCC+ with driver enabled
ICC-Ion}
Supply current from Vce _ with driver enabled
ICC + loft}
Supply current from Vee + with driver inhibited
VCC±
ICC-loft}
Supply current from Vee _ with driver inhibited
A,
I,
=
-12 rnA
=
=
Vo
Vo
10 V
-3 V
3.5
VI
VI
VI
=
=
=
6
MAX.
e, and 0 inputs at 0.4 V
TYP*
MAX
-1.5
-0.9
7
12
6
0.4 V
C and 0 inputs at 2 V
=
-0.9
2.4 V
A and B Inputs at 0.4 V,
e,
MAX
5.5 V
SN75112
SN75110A
TYP*
Vo - 10 V
0
SN55110A.
SN55109A.
TEST CONDITIONS t
PARAMETER
VIK
V
2
!il
~Z
V
Negative common-mode output voltage
Operating free-air temperature, TA
....
'"
v
Positive common-mode output voltage
Low-level input voltage, V,L
13
UNIT
SN75112
MIN
MIN
6.5
UNIT
TYP*
MAX
-1.5
-0.9
-1.5
15
27
36
12
MIN
18
27
100
100
100
1
1
1
2
2
2
40
40
40
80
80
80
-3
-3
-3
-6
-6
-6
18
30
23
35
25
40
-18
-30
-34
-50
-65
-100
18
21
30
-10
-17
-32
V
mA
p.A
mA
p.A
"".....en
Z
-
=
CD
mA
rnA
:1=0
"""
e ""z
zen
C ..... en
:I=oen1"'"-=
I"'"_CD
mA
_=:1=0
Z:l=o"
rn"
U!I
a""z
=
iii! en
_ .....
tFor conditions shown as MIN or MAX, use appropriate value specified under recommended operating conditions.
lAIi typical values are at VCC+ = 5 V, VCC- = -5 V, TA = 25°C.
.
/
"Qj
U
CI)
a::
-4
-3
1/1
-5
-6
Vcc_-Negative Supply Voltage-V
FIGURE 3
FIGURE 2
-7
--...
1/1
CI)
>
";:
o
CI)
I:
::J
SN75112
35
«
30
1-c:
e
25
E
:;
Vcc+ =4.5 V
Va = -3V
TA=25°C
I
II
u
~
:::l
E:::l
0
20
e
15
'7
10
!3
'1
c:
"2
0
(5
-3
----
I
I
-4
-5
h
/
5
o
/1--
/
V
-6
-7
Vcc_-Negative Supply Voltage-V
FIGURE 4
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-95
SN55109A, SN55110A
SN75109A, SN75110A, SN75112
DUAL LINE DRIVERS
TYPICAL APPLICATION DATA
special pulse-control circuit
Figure 5 shows a circuit that may be used as a pulse generator output or in many other testing applications.
INPUT
•
OUTPUTS
A
y
Z
HIGH
OFF
ON
LOW
ON
OFF
+5V
INPUT--+-~
+2.5V-"'+-~
3"
..
CD
C
~"
1/2'109A,
L
U;
f
GROUND
or~~~:i12
"""I- -
-=
(')
CD
.
TO OTHER
LOGIC AND
STROBE
INPUTS
~"
(II
INPUT PULSE
\
I
2 \3
\
,
04_+-_ _ _ _+-_-I-...J
CC
V---1
-
-5V
OUTPUT
n
...J L
SWITCH
POSITION
I
j
Z
r-
1
ZERO VOLTS
2
3
Vv
4
O"~""""~ Jl... 1J
5
FIGURE 5. PULSE CONTROL CIRCUIT
4-96
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TexAS 75265
6
n-
...J L
ZERO
VOLTS
SN75111
QUADRUPLE LINE DRIVER WITH COMMON ENABLE
03000, FEBRUARY 1986
•
Similar to a Dual Version of SN75109A Line
Driver
•
Improved Stability Over Supplv Voltage and
Temperature Ranges
D. J, OR N
DUAL-IN-L1NE PACKAGE
(TOP VIEW)
•
Constant-Current Outputs
•
High Output Impedance
•
High Common-Mode Output Voltage Range
(-3 V to 10 VI
•
Glitch-Free Power-Up/Power-Down
Operation
•
TTL Input Compatibility
•
Common Enabla Circuit
lA
lY
lZ
2Z
2Y
ENABLE
2A
GND
VCC+
4A
4Y
4Z
3Z
3Y
3A
VCC-
FUNCTION TABLE
description
The SN75111 features four line drivers with a
common enable input. When the enable input is
high, a constant output current is switched
between each pair of output terminals in
response to the logic level at that channel's
input. When the enable is low, all channel
outputs are nonconductive (transistors biased to
cutoffl. This minimizes loading in party-line
systems where a large number of drivers share
the same line.
ENABLE
INPUT
INPUT
Z
V
H
H
ON
OFF
L
H
OFF
ON
H
L
OFF
OFF
L
L
OFF
OFF
' CURRENT
...en
Q)
>
"as
(,)
CI)
a:
--...
= low logic level
H = high logic level
l
en
CI)
>
";:
logic symbol t
C
Q)
r::
::;
The driver outputs have a common-mode voltage
range of - 3 volts to 10 volts, allowing commonmode voltages on the line without affecting
driver performance.
All inputs are diode clamped and are designed
to satisfy TTL-system requirements. The inputs
are tested at 2 volts for high-logic-level input
conditions and 0.8 volt for low-logic-level input
conditions. These tests guarantee 400 millivolts
of noise margin when interfaced with Series
54/74 TTL.
OUTPUT
LOGIC
1V
1Z
2V
2Z
3V
3Z
4V
4Z
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
The SN75111 is characterized for operation from
ooe to 70 oe.
PRODUCTION DATA documlnls cont.in information
curranl u of publication datI. Products conform tu
spacifications per the terms af Taxa. Instruments
=-=:~~i;.i~:,~l~ ~=:~:; :lla::~:::£::'B
not
Copyright @ 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-97
.SN75111
QUADRUPLE LINE DRIVER WITH COMMON ENABLE
logic diagram (positive logic)
ENABLE
1Y
1A---+--I
2A---+--I
1Z
2Y
2Z
3Y
3Z
4A....:.:.;~---I
r-
:i'
CD
4Y
4Z
schematics of inputs and outputs
C
..
~'
;
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
.--------- OUTPUT
VCC+---------.-----
::IJ
CD
(')
CD
<'
CD
;
INPUT ~...-....-I
L...._ _ _ _ _
vcc--4------~~-----
OUTPUT
- -....-.----------VCCGNO ....- -
4-98
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN75111
QUADRUPLE LINE DRIVER WITH COMMON ENABLE
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee + (see Note 1) ............................................. 7 V
Supply voltage, Vee - ..................................................... - 7 V
Input voltage (any input) .................................................... 5.5 V
Output voltage range (any output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. - 5 V to 12 V
eontinuous total dissipation at (or below) 25 De free-air temperature (see Note 2):
D package ......................................................... 950 mW
J package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package ........................................................ 1150 mW
Operating free-air temperature range ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 De to 70 De
Storage temperature range ......................................... - 65 De to 1 50 De
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N package .......... 260 De
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............. 300 De
NOTES: 1. All voltage values are with respect to network ground terminal.
2. For operation above 25·e free-air temperature, derate the D package to 608 mWat 70·e at the rate of 7.6 mW/·e, derate
the J package to 656 mW at 70·e at the rate of 8.2 mW/·e, and the N package to 736 mW at 70·e at the rate of 9.2
mW/·e. In the J package the SN75111 is glass mounted.
II)
>
"CD
recommended operating conditions
u
MIN
NOM
Supply voltage, Vee +
4.75
5
Supply voltage, Vee-
MAX
UNIT
v
-4.75
5.25
-5 -5.25
2
5.5
V
0
0.8
V
IVOeR+
0
IVOeR-
0
10
-3
V
0
70
·e
High-level input voltage, VIH
Low-level input voltage, VIL
Common-mode output voltage range
...CD
Operating free-air temperature, T A
V
V
!
...
I I)
~
";::
C
CD
C
::::;
NOTE 3: All unused outputs must be grounded.
electrical characteristics over recommended operating free-air temperature range, VCC+ - 5.25 V,
VCC- - -5.25 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Input clamp voltage
11= -12 mA
10(onl
On-state output current
Vee + - 5.25 V,
Vee+ - 4.75 V.
10(offl
Off-state output Current
IIH
High-level input current
VIK
Vec+ - 4.75 V,
VI - 2.4 V
Vee- -
MIN
5.25 V
Vec- - - 4.75 V
Vee- = -4.75 V
3.5
Typt
MAX
UNIT
-0.9
-1.5
V
5.5
7
5.5
VI = 5.25 V
IlL
Low-level input current
VI - 0.4 V
Ice+
Supply current from Vee +
A inputs at 0.4 V
lee-
SupplV current from Vee-
A inputs at 0.4 V
t All typical values are at Vee + = 5 V, V ce _
Enable at 2 V
mA
100
~A
40
1
~
mA
-1.6
mA
28
40
Enable at 0.4 V
Enable at 2 V
27
-43
40
-55
Enable at 0.4 V
-25
-35
mA
mA
-5 V. and TA = 25·e.
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-99
5N75111
QUADRUPLE LINE DRIVER WITH COMMON ENABLE
S)Nitching characteristics. VCC+ - 5 V. VCC- -
-5 V. RL = 50 O. CL - 40 pF. TA
FROM
(INPUT)
TO
TEST
(OUTPUT)
CONOITIONS
tpLH Propagation delay time, low-to-high-Ievel output
tpHL Propagation delay time, high-to-Iow-Ievel output
A
Y or Z
A
Yor Z
tpLH Propagation delay time, low-to-high-Ievel,output
Enable
Y or Z
tPHL Propagation delav time, high-to-Iow-Ievel output
Enable
Y or Z
PARAMETER
MIN
=
25°C
TYP
MAX
9
7
15
ns
15
ns
14
15
25
ns
25
ns
See Figure 1
UNIT
PARAMETER MEASUREMENT INFORMATION
,...-----_._-----.----- OUTPUT Y
AINPUT--------------~
~-------...-:----._--- OUTPUT Z
ENABLE --------------~
!:
:s
CD
C
~.
~
TEST CIRCUIT
:xJ
CD
n
CD
A INPUT
Cr
CD
C;;
~50%
---I:!+-'w1-+1~S---J
I
I
I
ENABLE
I
'-_____...J.._: _____
I
I
I
I
I
~'PHL
k-*-tPHL
I
I
_-----~I-
I
I
---
off
50%
I
I
on
r--fff:.------------OUTPUT Z
OV
I
tpLH~
I
50%
50%
I
I
I
OUTPUT Y
, - - - 3V
I
I
I
I
I
I
-----OV
I
I
off
I
I
I
I
I
I
'PHL-*-+I
I
-1 ___ - - - - - - - - - - - - - - on
i.-.!-tPLH
VOLTAGE WAVEFORMS
NOTES: A. The pulse generators have the following characteristics:
tw2 = 1 p.o, PRR s 500 kHz.
B. CL includes probe and jig capaCitance.
Zo =
50 D, tr
= tf =
10 ± 5 ns, tw1
FIGURE 1. PROPAGATION DELAY TIMES
4-100
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
= 200 ns, PRR s
1 MHz,
SN55113, SN75113
DUAL DIFFERENTIAL LINE DRIVERS
01315. SEPTEMBER 1973-REVISEO SEPTEMBER 1986
•
Choice of Open-Collector, Open-Emitter, or
3-State Outputs
•
High-Impedance Output State for Party-Line
Applications
•
Single-Ended or Differential AND/NAND
Outputs
•
Single 5-V Supply
•
Dual Channel Operation
•
Compatible with TTL
SN55113 ... J PACKAGE
SN75113 ... D. J. OR N PACKAGE
•
Short-Circuit Protection
•
High-Current Outputs
•
Common and Individual Output Controls
•
Clamp Diodes at Inputs and Outputs
•
Easily Adaptable to SN55114 and SN75114
Applications
•
Designed for Use with SN55115 and
SN75115
(TOP VIEWI
lZP
lZS
1YS
1YP
1A
18
1C
GND
VCC
2ZP
2ZS
2YS
2YP
2A
2C
CC
SN55113 ... FK PACKAGE
(TOP VIEW)
3
1YS
1YP
NC
lA
18
5
17
6
16
1
15
14
8
CD
2ZS
2YS
NC
2YP
2A
>
'q)
U
CD
a:
-.
!II
"CD
9 1011 1213
The SN55113 and SN75113 dual differential line
drivers with three-state outputs are designed to
provide all the features of the SN55114 and
SN75114 line drivers with the added feature of
driver output controls. Individual controls are
provided for each output pair, as well as a
common control for both output pairs. If any
output is low, the associated output is in a highimpedance state and the output can neither drive
nor load the bus. This permits many devices to
be connected together on the same transmission
line for party-line applications.
The output stages are similar to TTL totem-pole
outputs, but with the sink outputs, YS and ZS,
and the corresponding active pull-up terminals,
YP and ZP, available on adjacent package pins.
The SN55113 is characterized for operation over
the full military temperature range of - 55 °e to
125°e. The SN75113 is characterized for
operation over the temperature range of ooe to
70 oe.
=~~i;ai~:I-::le t:~:~:f :.~D=~::.I.not
~
1 2019
18
description
PRODUCTION DATA d......nts ...tai. Inl.,.,lIi••
.urronl II of p....II.III.n dill. Prod.cts ..of.... to
.....lfi.III... par th. ta.....1 T.... lnotr....nll
2
4
TEXAS
,~
UOUUU
C
~ZZUN
(!)
CD
c
NC - No internal connection
:::i
FUNCTION TABLE
INPUTS
OUTPUTS
OUTPUT
CONTROL
C
CC
X
L
X
H
H
H
L
H
H
H
DATA
A Bt
X
X
X
X
L
X
X
L
H
H
AND
NAND
y
Z
Z
Z
H
H
L
Z
Z
l
L
H
H = high level. L = low level. X = irrelevant.
Z = high impedance (offl
ts input and 4th line of function table a,e applicable only
to driver number 1.
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76265
Copyright @ 1973, Texas Instruments Incorporated
4-101
SN55113, SN15113
DUAL DIFFERENTIAL LINE DRIVERS
logic diagram (positive logic)
logic symbolt
1C (7)
EN 1
cc
2C
1VP
1A
1VS
1ZP
1ZS
18
2VP
2VS
2ZP
2ZS
r-
S·
CD
C
::!.
Ci
;;;
tThis symbol is in accordance with ANSIIIEEE Std 91·1984 and
IEC Publication 617·12.
Pin numbers shown are for D, J, and N packages.
schematic
::D
INPUT 18
(61
CD
n
CD
INPUT lA
(51
r-~----~----~------~~----~--~~~'(~16"'I'Vee
:C2"
...
CD
tn
AND (41
PULL·UP
lYP
(1)
AND
SINK (31
OUTPUT
1YS
(21
OUTPUT (71
eONTROL~------t-+
Ie
W·.·
VCC bus
:t:These components common to both drivers.
Resistor values shown are nominal and in ohms.
4-102
TEXAS ."
INSTRUMENTS
POST OfFICE BOX 666012 • DALLAS. TEXAS 75285
NAND
PULL·UP
lZP
NAND
SINK
OUTPUT
lZS
SN55113, SN75113
DUAL DIFFERENTIAL LINE DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Off-state voltage applied to open-collector outputs ................................. 12 V
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
o package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 950 mW
FK or J package ..................................................... 1000 mW
N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11 50 mW
Operating free-air temperature range: SN55113. . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
SN75113 ............................. O°C to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds: 0 or N package ......... 260°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............. 300°C
NOTES: 1. All voltage values are with respect to network ground terminal.
2. For operation above 25·C free-air temperature. see Dissipation Derating Curves in Appendix A. In the J and FK packages. SN55113
chips are alloy mounted; SN75113 chips are glass mounted. In the N package. use the 9.2-mW/·C curve for these devices.
•
..
en
CD
recommended operating conditions
SN55113
MIN
Supply voltage. VCC
SN75113
MAX
MIN
NOM
MAX
5
5.5
4.75
5
5.25
V
0.8
-40
0.8
-40
V
mA
40
40
mA
70
·C
2
Low-level input voltage. VIL
High-level output current. IOH
Low-level output current, IOL
Operating free·air temperature, T A
UNIT
NOM
4.5
High-level input voltage. VIH
>
";
-55
2
125
0
V
U
CD
-..
a:
en
CD
>
"~
o
CD
c
::i
TEXAS •
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75265
4-103
SN55113, SN75113
DUAL DIFFERENTIAL LINE DRIVERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
V,K
Input clamp voltage
VOH
High-level output voltage
VOL
low-level output voltage
VOK
Output clamp voltage
" =
V,H = 2 V,
Vee = MIN,
V,l = o.s
Vee
•
I 10H
I
V
= MIN,
V,L = O.S
Vee
V,
5'
CD
C
~'
(II
"H
...
CD
:xl
CD
CO)
',L
CD
<'
...
Vee
(high-impedance-state)
Output controls
output current
al O.S
input voltage
A, S, C
input current
ec
Low-level
A,B,e
input current
ee
lOS
output current §
(II
Supply current
lee
TA
V
V, =
MAX,
5.5
V,
Vee =
MAX,
V, = 0.4
= MAX,
All inputs at 0 V
.Iboth drivers)
=
MAX,
Vee
TA
-1.5
3.4
40mA
2
3.0
2
3.0
'OH-
Vo - 010
Vo
I
0.4
0.23
0.4
V
-1.5
-1.1
-1.5
V
1
10
200
1
10
pA
20
Vee
=0
= 0.4 V
= 2.4 V
= Vee
V
±10
±10
-150
-20
±SO
±20
±80
±20
so
20
1
1
2
2
40
40
so
80
-1.6
-1.6
-3.2
-3.2
pA
rnA
2.4 V
V
= 0,
TA
= 25°e
I Vee
No load,
V
V
0.23
TA = 70°C
Vo
Vo
Vo
Vo
UNIT
-1.1
TA = 125°C
= MAX
Vee =
Short-circuit
MAX
-0.9
2.4
TA = 25°C
V
= MAX,
Vee =
TYP*
3.4
ee
High-level
CD
-1.5
A, S, e
at maximum
"
-0.9
MIN
2.4
TA - 25°e
VOH = 12 V
Off-state
Input current
MAX
-10 rnA
'0=-40rnA
TA - 25°e,
r-
SN75113
Typt
'Ol = 40 rnA
= MAX,
VOH = 5.25
IOZ
-
V,H = 2 V,
Vee = MAX
output current
MIN
-12 rnA
Vce - MIN,
Off-state open-collector
'Oloffi
SN55113
TEST CONDITIONS t
PARAMETER
= 25°e
-40
= MAX
Vee -
7
V
-90
-120
-40
-90
-120
47
65
47
65
65
85
65
S5
pA
rnA
rnA
rnA
tAli parameters with the exception of off-state open-collector output current are measured with the active pull-up connected to the sink output.
iAIi typical values are at TA = 25 Q C and Vce = 5 V, with the exception of ICC at 7 V.
§Only one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
switching characteristics, Vee == 5 V, eL == 30 pF, TA .. 25°e
PARAMETER
TEST CONDITIONS
SN55113
MIN
SN75113
UNIT
TYP
MAX
TYP
MAX
13
20
13
30
ns
12
20
12
30
ns
See Figure 2
7
15
7
20
ns
See Figure 3
14
30
14
40
ns
MIN
IplH
Propagation delay time, low-to-high-Ievel output
IpHL
Propagation delay time, high-to-Iow-Ievel output
IPZH
Output enable time to high level
RL
tpZL
Output enable time to low level
Rl -
tpHZ
Output disable time from high level
Al
180 0, See Figure 2
10
20
10
30
ns
IplZ
Output disable time from low level
Al - 250 0, See Figure 3
17
35
17
35
ns
4-104
See Figure 1
=
=
n,
250 n,
180
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN55113, SN75113
DUAL DIFFERENTIAL LINE DRIVERS
PARAMETER MEASUREMENT INFORMATION
1kn
~t-_. . ._AND
INPUT
PULSE
GENERATOR
(SaeNote Al
I
50n
NAND
I
...I - -....-OUTPUT
L _ _ _ _ _ _ -J
' " CL=30pF
-4:'
(Soo Note BI
TEST CIRCUIT
~<5 ns
--.j
~
j(L
1t-------3V
vl
9 0%'51i
1
1
INPUT
1.::%
:
10%
I
1
:"
NAND
OUTPUT
,
tpHL
\5V
!
i"~--v.-l~~:-:~tP~L~H~_
OV
VOH
: /1.5V
\-.
tPLH-l4I4--+l~
•
.
II)
CD
10%
----+1_ o J
1
OUT~~~
1+-<5 ns
-
-
"'1+---:-~~I-tPHL
..Jf,.·5-V-----~ ~
___
>
"i
U·
CD
-.
a::
I I)
CD
-
-
VOL
---:::
>
";:
Q
CD
c
::::i
WAVEFORMS
FIGURE 1. tPLH and tPHL
NOTES: A. The pulse generator has the following characteristics: Zout
B. CL includes probe and jig capacitance.
= 50 D. PRR s
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 76265
500 kHz. tw
= 100 ns.
4-105.
SN55113, SN75113
DUAL DIFFERENTIAi LINE DRIVERS
PARAMETER MEASUREMENT INFORMATION'
INPUT
PULSe
GENERATOR
ISoeNoteAI
AND
~~--~---------OUWUT
NAND
~r---~---------'OUWUT
CL· 30 pF
~ lSee Note BI
'kG
SV
TEST CIRCUIT
14-
It-
"0:
I
I
I
I
C
I4-_tP_L_Z_...t~K 5V
:::i
I
I
CD
c
\"--'5_v__
OUTPUT
-
- ""l- VOL
WAVEFORMS
FIGURE 3. tpZL and tPLZ
NOTES: A. The pulse gener~tor has the following characteristics: Zout
= 50 II, PRR s
500 kHz, tw
= 100 ns.
B. CL includes probe and jig capacitance.
TEXAS
-If
INSTRUMENTS
POST OFFICE BOX 856012 • DALLAS, TEXAS 75265
4-107
SN55113, SN75113
DUAL DIFFERENTIAL LINE DRIVERS
TYPICAL CHARACTERISTICSt
OUTPUT VO LTAG E
vs
DATA INPUT VOLTAGE
OUTPUT VOLTAGE
vs
DATA INPUT VOLTAGE
6
6
No load
TA=25"C
5
VCC=5V
No load
5
TA = 125·C
~
VCC=5.5V
&4
!
VCC=5V
VCC= 4.5 V
.. 3
~"
\
'~"A.= 25·C
TA=-55 C
9o 2
>
t::
::::J
CD
..<.
.
C
o
o
CD
2
3
4
o
o
2
~
FIGURE 4
CD
n
!2.
.
(II
6
4
FIGURE 5
OUTPUT VOLTAGE
vs
OUTPUT CONTROL VOLTAGE
<
CD
3
VI-Data Input Voltage-V
VI-Data Input Voltage-V
(II
OUTPUT VOLTAGE
vs
OUTPUT CONTROL VOLTAGE
6
=
Load 500 n to ground
TA = 25·C
VC~=5V
I
I
Load - 500 n to ground
5
5
VCC=5.~
I
•
TA=125(;
/
V_ -
VCC=5V
VCC = 4.5 V_ ' - - \
T~~= 25·C
TA=-55 C
DISABLED
o
o
DISABLED
HIGH
I
2
4
3
I
HIGH
1
o
o
2
3
4
VI-Input Voltage (Output Controll-V
VI-Input Voltage (Output Controll-V
FIGURE 6
FIGURE 7
tOata for temperatures below O·C and above 70·C and for supply voltages below 4.75 V and above 5.25 V are applicable to SN55113
circuits only. These parameters were measured with the active pull-up connected to the sink output.
4-108
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN55113, SN75113
DUAL DIFFERENTIAL LINE DRIVERS
TYPICAL CHARACTERISTICSt
OUTPUT VOLTAGE
6
vs
OUTPUT CONTROL VOLTAGE
OUTPUT CONTROL VOLTAGE
6
Load = 500 n to VCC
TA = 25°C
VCC=5.5V
VCC=5V
5
OUTPUT VOLTAGE
vs
5
VCC = 4.5 V
>I
.'"
>I
..
4
'"
:I
:I
~...
::J
~...
3
::J
&
::J
90
Load = 500 n to VCC
VCC=5V
4
/ T A = 25°C
I(
3
II
&
::J
90
2
>
OlfABLfO JOW
o
2
3
o
4
TA = -55°C
TA = 125°C
I
I
OIS+LEd
LOJ.j
I
~
o
2
>
L
o
VI-Input Voltage (Output Controll-V
...CD
II)
>
"iii
(,)
2
3
VI-Input Voltage (Output Controll-V
FIGURE 8
-...
CD
a::
4
I I)
CD
FIGURE 9
>
";:
C
OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
vs
vs
OUTPUT CURRENT
FREE-AIR TEMPERATURE
4.0
5
VCC= 4.5V
3.6
3.2
=r
2.8
;!l.
~ 2.4
~
; 2.0
a.
~ 1.6
-- ----
VOH(lOH = -10 mA~
~
CD
c
::::i
4
~ r-
1..
~r-
'" 3
:I
Q
C-VOH(lOH = -40 mAl
>...
::J
&
::J
0
I
I
01.2
2
TA = 25°C
-----
---r--.
VCC = 5.5 V
l-t--.
JV~C=5V
--':fZ.....
--.....r(
r
r-..'
t---.'
VCC=4.5V
,
:x:
>
0
>
0.8
0.4 -
r-VOL(lOL
o
I
-75 -50 -25
40mA)
I
I
0
25
50
75
100
125
o
o
~
-20
-40
-60
-80
-100 -120
IOH-Output Current-mA
T A -Free-Air Temperature-° C
FIGURE 10
FIGURE 11
tOata for temperatures below O°C and above 70°C and for supply voltages below 4.75 V and above 5.25 V are applicable to SN55113
circuits only. These parameters were measured with the active pull-up connected to the sink output.
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 6550t 2 • DALLAS. TEXAS 75265
4-109
SN55113, SN75113
DUAL DIFFERENTIAL LINE DRIVERS
TYPICAL CHARACTERISTICS t
SUPPLY CURRENT
(BOTH DRIVERS)
vs
SUPPLY VOLTAGE
LOW·LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
0.6
80
TA=J5°C
0.5
l'..
!
~~
"
&
9"
VCC=4.5~
0.4
0.3
0.2
-'
r-
5'
~
CD
C
::I.
0.1
o
<
iil
.CD
/
V
N~load I
70 f-TA=25°C
/-
~
«
E
I
b?'
VCC=5.5V
/
V
~
~~~ ~
1: 50
o~
f;>~'
2!
;;
(,)
>a.
,1-"
40
'f"
30
(,)
!:: 20
10
~
~
60
60
o
1~
100
IOL-Output Current-rnA
~
./
o
IJ"
/
/
2
4
5
6
3
VCC-Supply Voltage-V
CD
<'
CD
100
56
«
E
.!.c:
VCC=5V
54 I nputs grounded
No load
52
">-
(,)
80
50
-....
46
I
:::l
'f
(,)
!::
,,/
~
c:
2!
-............
Q.
a.
VCC=5V
RL =00
CL =30pF
Inputs: 3-volt square wave
TA = 25°C
~
~ 48
45
8
SUPPLY CURRENT
(BOTH DRIVERS)
vs
FREQUENCY
SUPPLY CURRENT
(BOTH DRIVERS)
vs
FREE·AIR TEMPERATURE
iil
7
FIGURE 13
FIGURE 12
CD
n
~
o
,a.
Q.
"""
42
40
'f"
~
'-
"""
40
20
38
36
-75 -50 -25
0
25
50
75
100
125
0.1
TA-Free·Air Temperature-oC
I II
I
o
0.4
4
10
f-Frequency-MHz
40
100
FIGURE 15'
FIGURE 14
tOata for temperature below ooe and above 70 eC and for supply voltages below 4.75 V and above 5.25 V are applicable to SN55113
circuits only. These parameters were measured with the active pull-up connected'to the sink output.
0
4·110
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN55113, SN75113
DUAL DIFFERENTIAL LINE DRIVERS
TYPICAL CHARACTERISTICS t
PROPAGATION DELAY TIMES
FROM DATA INPUTS
vs
FREE-AIR TEMPERATURE
!
=
20
.:
l!
16
...
18
~
14
~
12
.::
30
VCC=5V
CL = 30 pF
See Figure 1
",
tpLH
'ii
Q
- -,........
f---"
tpHL
M
E
~
OUTPUT ENABLE AND DISABLE TIMES
vs
FREE-AIR TEMPERATURE
10
VCC=5V
See Figures 2 and 3
f
25
:;
E
------
~
..,/
20
-~
1
is 15
tP~z
:;;
I! 10
6
4
...
a
2
o
tPZH
III
=
o
-75 -50 -25
o
25
50
75
100 125
I---
tpZ~
....
11
8
V
-
f---"
./'"
--- II.
til
Q)
>
"Gi
5
o
to)
Q)
T A-Free-Air Temperature-°c
0
25
50
75
100 125
t il
Q)
TA-Free-Air Temperature-oC
>
";:
FIGURE 17
FIGURE 16
--..
a:
-75 -50 -25
C
tOata for temperature below DOC and above 7D °cc and for supply voltages below 4.75 V and above 5.25 V are applicable to SN55113
circuits only. These parameters were measured with the active pull-up connected to the sink output.
Q)
::::i
TYPICAL APPLICATION DATA
=a
=D--
TWISTED
PAIR
SN75113 DRIVER
SN75115 RECEIVER
tRT=ZO. A capacitor may be connected in series with RT to reduce power dissipation.
FIGURE 18. BASIC PARTY-LINE OR DATA-BUS DIFFERENTIAL DATA TRANSMISSION
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
c:
4-111
4-112
SN55114, SN75114
DUAL DIFFERENTIAL LINE DRIVERS
01315, SEPTEMBER 1973-REVISEO SEPTEMBER 1986
•
Choice of Open-Collector. Open-Emitter. or
Totem-Pole Outputs
•
Single-Ended or Differential AND/NAND
Outputs
•
Single 5-V Supply
•
Dual Channel Operation
•
TTL-Compatible
•
Short-Circuit Protection
•
High-Current Outputs
•
Triple Inputs
•
Clamp Diodes at Inputs and Outputs
•
Designed for Use with SN55115 and
SN75115 Differential Line Receivers
•
SN55114 .•. J PACKAGE
SN75114 . , . 0, J, OR N PACKAGE
(TOP VIEWI
1ZP
1ZS
1YS
1YP
1A
1B
1C
GND
VCC
2ZP
2ZS
2YS
2YP
2C
2B
2A
SN55114 ... FK PACKAGE
(TOP VIEW)
3
Designed to be Interchangeable with
Fairchild 9614 Line Driver
18
17
5
7
16
15
8
14
6
description
The SN55114 and SN75114 dual differential line
drivers are designed to provide differential output
signals with the high-current capability for
driving balanced lines, such as twisted pair, at
normal line impedances without high power
dissipation, The output stages are similar to TTL
totem-pole outputs, but with the sink outputs,
YS and ZS, and the corresponding active pullup terminals, YP and ZP, available on adjacent
package pins. Since the output stages provide
TTL-compatible output levels, these devices may
also be used as TTL expanders or phase splitters.
The SN55114 is characterized for operation over
the full military temperature range of - 55 De to
125 D e. The SN75114 is characterized for
operation from oDe to 70 De,
lB
lC
CD
>
'Q)
CJ
-.
~
en
9 10111213
CD
~~~~~
>
';:
(!l
C
NC- No internal connection
CD
C
~
FUNCTION TABLE
INPUTS
A
H
OUTPUTS
B
C
Y
H
H
H
L
L
H
ALL OTHER INPUT COMBINATIONS
H
=
high level, L
=
Z
low level
logic diagram (positive logic)
1YP
1A
(51
en
2ZS
2YS
NC
2YP
2C
1YS
logic symbol t
lA
II
.
2 1 20 19
&t>
(61
(71
(91
2A
(101
2B
(111
2C
(41
(31
18-:'=:"""---1
lYP
lYS
::=I:,r::I~'l.; =~::i; :''i'':''':::Nt:'~ not
1ZS
lZP
lZS
2YP
2YP
2YS
2YS
2ZP
2ZP
2ZS
tThis symbol is in accordance with ANS'IIlEEE Std 91-1984 and
IEC Publication 617·12.
PRODUCTION DATA d...mlHlls ""ntain information
current as af pu.licatioR date. Products conform to
specifications per the terms of Texas Instruments
1ZP
1C
2ZS
Pin numbers shown are for D, J, and N packages.
Copyright © , 985, Texas InStruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
4-113
SN55114, SN15114
DUAL DIFFERENTIAL LINE DRIVERS
schematic (each driver)
TO
OTHER
DRIVER
r-"--.
1161
Vcc
AND
PULL.~',::4,,-,1:::2!61
_+-__-'
' -_ _4---4':..:',..,1:.:::51 ~:ND PULL·UP
1_~=i_~~-Z_~'~2'~'~4INAND
AND 13,131
+-
SINK OUTPUT
SINK OUTPUT
vs
181
zs
GND
Pin numbers shown are for. D, J, and N packages
tThese components are common to both drivers.
Resistor values shown are nominal and in ohms.
!:
~
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
CD
SN55114
C
..
:::!.
<
CD
!e.
:J:I
CD
~.
..
Supply voltage, Vec (see Note 1)
Input voltage
SN75114
7
5.5
12
Off·state voltage applied to open-collector outputs
D package
Continuous total dissipation at (or below)
FK package
25 0 C free-air temperature (see Note 2)
J package
7
5.5
12
UNIT
V
V
V
950
1375
1375
N package
CD
<
Operating free-air temperature range
-55to125
en
Storage temperature range
Case temperature for 60 seconds: FK package
-65 to 150
1025
1150
o to 70
-65 to 160
·C
·C
'c
260
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package
Lead temperature 1,6 mm (1116 inch) from case for 10 seconds: D or N package
mW
·C
·C
300
260
NOTES: 1. Voltage values are with respect to network ground terminal.
2. For operation above 25·C free·air temperature, refer to Dissipation Derating Curves in Appendix A. In the FK and J packages,
SN65114 chips are alloy mounted. In the J package, SN75114 chips are glass mounted,
recommended operating conditions
SN65114
MIN NOM
Supply voltage, VCCI
High·level input voltage, VIH
Low·level input voltage, VIL
4.5
5.6
2
MIN NOM MAX
4.75
-40
40
-56
TEXAS ."
INSTRUMENlS
POST OFFice BOX 656012 • DALLAS, TeXAS 75285
5
125
0
UNIT
5.25
V
0.6
-40
40
V
V
rnA
rnA
·C
2
0.6
High-level output current, 10H
Low:level output current, 10L
Operating free·air temperature, T A
4-114
5
SN75114
MAX
70
SN55114, SN75114
DUAL DIFFERENTIAL LINE DRIVERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
VOK
Output clamp voltage
Off-state
open~collector
10(off} output current
Input current at
"
maximum input voltage
"H
',L
High-level input current
Low-level input current
Short-circuit
lOS
lee
output current §
Vee - MIN,
Vee - MIN,
"
= 0.8 V,
V,L
Vee - MIN,
MIN TYP*
-0.9
12 rnA
-
V,H - 2 V,
L'oH- -10 rnA
I'OH - -40 rnA
=
=
-1.5
2.4
3.4
2
3.0
2
3.0
- 25°e
=
0.2
0.4
6.1
-1.1
6.5
MAX. Va
= 0,
TA
Supply current
All inputs at 0 V, No load,
(both drivers)
TA
=
25°e
V
6.1
6.5
-1. 1 -1.5
V
1
100
=
I Vee
25°e
•
~A
200
40
-1. 1 -1.6
=
V
0.45
- 70 0 e
Vee = MAX, V, = 2.4 V
Vee - MAX, V, - 0.4 V
Vee
UNIT
V
200
- 125°e
- 25°e
1
MAX, V,
MAX
-1.5
0.2
- 1.5
1
100
25°e
- 25°e
5.5 V
Vee
MIN TYP*
-0.9
3.4
V,H - 2 V,
V, 10L = 40 rnA
Vee - 5 V, 10 - 40 rnA,
TA
Vee = MAX, 10 = -40 rnA, TA
TA
VOH = 12 V
TA
Vee = MAX
TA
VOH = 5.25 V
TA
MAX
2.4
= 0.8
V,L
SN75114·
SN55114
TEST CONDITIONSt
PARAMETER
-40
- MAX
I Vee - 7 V
-90 - 120
1
-1.1
-40
rnA
40
~A
-1.6
rnA
-90 -120
37
50
37
50
47
65
47
70
...
!II
II)
>
·iii
rnA
to)
II)
-a:
rnA
~
t All parameters with the exception of off-state open-collector output current are measured with the active pl.lllup connected to the sink
output. For conditions shown 85 MIN or MAX. use the appropriate value specified under recommended operating conditions.
All typical values are at TA = 25°e and Vee = 5 V, with the exception of lee at 7 V.
§ Only one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
*
switching characteristics, Vee"" 5 V, TA
tPLH
tpHL
=
TEST CONDITIONS
Propagation delay time, low·to-high-Ievel output
eL - 30 pF,
See Figure 1
Propagation delay time, high-to-Iow-Ievel output
C
II)
c
25°e
PARAMETER
~
.;:
::::i
SN55114
MIN
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TEXAS 76265
SN75114
UNIT
TYP
15
MAX
TYP
MAX
20
15
30
ns
11
20
11
30
ns
MIN
4-115
SN55114, SN75114
DUAL DIFFERENTIAL LINE DRIVERS
PARAMETER MEASUREMENT INFORMATION
14-<5 ns
~
INPUT
~
~
VCC=5V
2kn
V
rl~90%~_ _-9O%~~1-=-: - -
I
1.5 V
1.5V
~
INPUT 10%
~
tw
~"""'_..&..l..---,.-AND OUTPUT
•
'='
OUTPUT
I'
I
z
I
OUTPUT
:
10%
OV
tpLH
y,"'.5-v--~I-I-.5""'X---VOH
I
_ _ _ _ .J
--3V
I
t4:!1
14j4-....,~"I-tpLH
I
V
Z
NAND OUTPUT
~<5 ns
i
X
I'
I
tpLH-IoII4~""'y-1>I1 VOH
1.57
5V
tpHL-IoI141--","~~1
TEST CIRCUIT
"'--VOL
------
-
-
VOL
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zout = 500 O. PRR
B. CL includes probe and jig capacitance.
s 500 kHz. tw '" 100 ns.
FIGURE 1. PROPAGATION DELAY TIMES
TYPICAL CHARACTERISTICS t
OUTPUT VOLTAGE
6
OUTPUT VOLTAGE
vs
vs
DATA INPUT VOLTAGE
DATA INPUT VOLTAGE
6
No load
TA=25"C
5
VCC=5V
No load
5
TA = 125°(:
VCC=5.5V
VCC=5V
VCC=4.5V
.
o
o
2
3
VI-Data Input Voltage-V
\ ~A=25°C
TA = _55°C
4
o
o
2
3
4
VI-Data Input Voltage-V
FIGURE 2
FIGURE 3
t Data for temperatures below OOC and above 70°C and for supply voltages below 4.75 V and above 5.25 V are applicable to SN55114
circuits only. These parameters were measured with the active pullup connected to the sink output.
4·116
~
TEXAS
INSTRUMENTS
POST OfFICE BOX -655012 • DAtLAS. TEXAS 76265
SN55114. SN75114
DUAL DIFFERENTIAL LINE DRIVERS
TYPICAL CHARACTERISTICS t
HIGH-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
0_4
5
TA = 25°C
------- --
TA = 25°C
J .A ~
VCC= 5_5 V
4
r-- /
>I
f3
..&
r--..
~
~
r--
VCC= 5_5 V
> 0_3
t
;g
K
1--..."
~
e-,.
f- r--.."
,. 2
9:I:
VCC =4_5V
.)'
I
VCC=5 V
0_2
9
"\
...J
~
~0_1
o
>
/
o
II
o
.0
-20
-60
--40
-80
-100
-120
o
/
~
V
Vcc= 4_5 V
./
•
V
f!
Q)
.~
Q)
10
20
30
40
50
60
70
CJ
80
Q)
a:
.
IOL -Output Current-rnA
IOH-Output Current-rnA
FIGURE 4
--I/)
Q)
>
FIGURE 5
.~
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
PROPAGATION DELAY TIMES
vs
FREE-AIR TEMPERATURE
4_0
40
VCC=4.5V
3_6
3_2
VOHUOH = -10 rnA!.--
==j 2_8
l!I,
~ 2_4
~
i
9
f.-
Q
--
..
...!.
r-
c
f--- f----l--- f-f--- r--VOHUOH = -40 rnA)
Q)
c:
:::::i
VCC=5V
See Figure 1
30
E
j::
~
Gi 20
Q
2_0
./
~
c
0
1_6
~
'"
a.
..
~ 1_2
!! 10
t PHL
I
CL
0_8
.-/
-
0_4 r--- -VOL(lOL = 40 rnA)
o
o
I
-75 -50 -25
0
25
50
75
100
125
-75 -50 -25
0
25
50
75
100 125
TA-Free-Air Ternperature-oC
TA-Free-Air Ternperature-oC
FIGURE 7
FIGURE 6
t Data for temperatures below OOC and above 70°C are applicable to SN55114 circuits only. These parameters were measured with the
active pullup connected to the sink output.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 76285
4-117
SN55114, SN75114
DUAL DIFFERENTIAL LINE DRIVERS
TYPICAL CHARACTERISTICS t
SUPPLY CURRENT
(BOTH DRIVERS)
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
(BOTH DRIVERS)
vs
SUPPLY VOLTAGE
80
42
No load
70 TA = 25°C
VCC=5V
I nputs grounded
40 Outputs open
1 60
'iii
u
-.
CI)
a::
I I)
CI)
>
';:
C
CI)
c
:J
TEXAS . . . \
INSTRUMENlS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
4-119
•
4-120
SN55115, SN75115
DUAL DIFFERENTIAL LINE RECEIVERS
01315, SEPTEMBER 1973-REViSEO OCTOBER 1986
•
Choice of Open-Collector or Active Pull-Up
(Totem-Pole I Outputs
•
Single 5-V Supply
•
Differential Line Operation
SN55115 ... J DUAL-iN-LINE PACKAGE
SN75115 ... D. J. OR N PACKAGE
(TOP VIEW)
•
Dual-Channel Operation
•
TTL Compatible
lYS
lYP
lSTRB
lRTC
lB
lRT
lA
GND
VCC
2YS
2YP
2STRB
2RTC
2B
2RT
2A
•
± 15 V Common-Mode Input Voltage Range
•
Optional-Use Built-In 130-0 Line-Terminating
Resistor
•
Individual Frequency Response Controls
•
Individual Channel Strobes
•
Designed for Use with SN55113. SN75113.
SN55114. and SN75114 Drivers
a..
Designed to be Interchangeable with
Fairchild 9615 Line Receivers
3
•
•
SN551 15 ... FK PACKAGE
(TOP VIEW)
(J)
U(J)
>->-U U>-
lSTRB
lRTC
NC
lB
lRT
description
The SN55115 and SN75115 dual differential line
receivers are designed to sense small differential
signals in the presence of large common-mode
noise, These devices give TTL-compatible output
signals as a function of the differential input
voltage. The open-collector output configuration
permits the wire-ANDing of similar TTL
outputs (such as SN5401/SN7401) or other
SN55115/SN75115 line receivers. This permits
a level of logic to be implemented without extra
delay. The output stages are similar to TTL
totem-pole outputs. but with sink outputs. 1YS
and 2YS. and the corresponding active pull-up
terminals. 1 YP and 2YP. available on adjacent
package pins. The frequency response and noise
immunity may be provided by a single external
capacitor. A strobe input is provided for each
channel. With the strobe in the low level. the
receiver is disabled and the outputs are forced
to a high level.
.
~~z>'"
2
II)
1 2019
4
18
5
17
6
16
7
15
14
8
II)
2YP
2STRB
NC
2RTC
2B
>
'G)
(,)
II)
a::
--..
I I)
II)
9 10111213
>
.;:
«QU«
I_ZZNa::
(!)
C
'"
II)
c:
NC - No internal connection
::::i
FUNCTION TABLE
STROBE
DIFF
OUTPUT
INPUT
(VP AND VS TIED TOGETHER)
L
X
H
H
L
H
H
H
L
H = VI 2: VIH min or VID more positive than VTH max
L = VI :5 VIL max or VID more negative than VTL max
X = irrelevant
The SN55115 is characterized for operation over
the full military range of - 55°C to 125°C. The
SN75115 is characterized for operation from
ooe to 70°C.
PRODUCTION DATA documents .ontain information
CURant as of publication data. Products canfarm to
specifications per the terms of Tuas Instruments
:'::=~~i;8:;:1~1i ~::i:r :.~o::;:::£::-.~
not
TEXAS
..If
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXA~ 75265
Copyright © 1973, Texas Instruments Incorporated
4-121
SN55115, SN75115
DUAL DIFFERENTIAL LINE RECEIVERS
logic symbol t
logic diagram Ipositive logic)
&1>
lB 151
lYP
lA
1YS
2YP
2YS
•.
I"""
5"
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
schematic leach receiver)
RESPONSE·
CD
TIME
...o::-
RT
(6,10)
CD
STROBE
13.131
CONTROL
14,121
1k
Cl
::a
CD
()
1.6 k
1.64 k
CD
<"
...
CD
20
(II
L-_-1f--__--1-2-.14-1 ~LL-UP
5>
3'
-+____+-_--+______--,
IN';iT ~,-,.1",,11_ _
____-~11~.1-5~1
::p\n
vs
130
1.Sk
L-___~-4-----4----~. .-~la~I,GND
COMMON TO
r-------,I
I
BOTH RECEIVERS
I
I
I
I
I
I
I
I
I
I
I
Resistor values are nominal and in ohms.
I
IL _______ JI
Pin numbers shown are for D. J. and N packages.
4-122
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 15285
SN55115, SN75115
DUAL DIFFERENTIAL LINE RECEIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SN55115
Supply voltage. Vee (see Note 1)
Input voltage at A. B. and RT inputs
SN75115
7
±25
±25
V
5.5
5.5
V
14
V
Input voltage at strobe input
Off~state voltage applied to open-collector outputs
14
o package
V
950
Continuous total dissipation at (or below)
FK package
1375
25°C free-air temperature (see Note 2)
J package
1375
1025
Operating free-air temperature range
-55 to 125
o to 70
Storage temperature range
-65 to 150
-65 to 150
N package
mW
1150
Case temperature for 60 seconds: FK package
260
Lead temperature 1.6 mm (1/16 inch) from case for 60 seconds: J package
300
Lead temperature 1.6 mm (1116 inch) from case for 10 seconds: 0 or N package
NOTES:
UNIT
7
260
°c
°c
°C
°C
°c
1. All voltage values, except differential input voltage, are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the FK and J packages,
SN551 15 chips are alloy mounted and SN751 1 5 chips are glass mounted. For these devices in the N package. use the 7.0-mW/oC
curve. For the 0 package, use the 8.2 mW/oC curve.
•
...CD
rJ)
>
'(j)
recommended operating conditions
(.)
CD
SN55115
SN75115
MIN
NOM
MAX
MIN
NOM
MAX
Supply voltage. Vee
4.5
5
5.5
4.75
5
5.25
High-level (strobe) input voltage. VIH
2.4
V
a:
--...
r J)
CD
>
V
'':::
Low-level (strobel input voltage. VIL
0.4
0.4
V
C
High-level output current. IOH
-5
-5
mA
LowRlevel output current. IOL
15
15
mA
70
°C
Operating free-air temperature, T A
-55
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 752'65
2.4
UNIT
125
0
CD
r::
::i
4-123
SN55115, SN75115
DUAL DIFFERENTIAL LINE RECEIVERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
Differential input
VTH§
VTl§
high·threshold voltage
low-threshold voltage
VOH
.-5"
input voltage range
High-level output voltage
= 0.4 V,
IOl
=
15 mA,
VIC
=
0
Vo
=
2.4 V,
10H
=
-5 mA,
VIC
=
0
VIO
=
±1 V
Low-level output voltage
-
III
Low-level input current
ISH
ISl
IIATCI
High-level strobe current
VIO
VCC
=
=
=
MAX,
VCC
=
MIN,
=
+15
to
to
-15
-19
-15
-19
2.4
0.5 V,
Low-level strobe current
VIO
1010ffi
CD
=
-0.5 V,
VCC = MAX,
VIO = 0.5 V,
V strobe = 0.4 V
Response-time-control
VCC = MAX,
current
VAC
VIO = 0.5 V,
=0
Off-state open-collector
VIO = -4.5 V
output current
VCC = MIN,
Line-terminating
RT
lOS
ICC
VCC
resistance
=
output current N
VIO
Supply current
VCC - MAX,
(both receivers)
VIC
25°C
TA = 25°C
-1.15
-1.2
5
-2.4
-3.4
-1.15
-1.2
200
VIO' - 0.5 V,
=0
TA
= 25°C
mA
,.A
mA
mA
100
,.A
200
77
130
167
74
130
179
-15
-40
-80
-14
-40
-100
mA
32
50
32
50
mA
TA = 25°C
25°C
-2.4
-3.4
TA = MAX
=
V
0.7
10
TA = MAX
TA
-0.7
2
TA = 25°C
Vo = 0,
0.45
5
=
5.25 V.
V
-0.9
-0.5
-0.7
100
VOH
= MAX,
= -0.5 V
VCC
=
V
3.4
0.22
-0.7
TA - 25°C
5V
Short-circuit
TA
0.4
VOH - 12 V,
VIO = -4.75 V
III
MAX
2.4
-0.9
-0.5
TA = 25°C
=
+24
2.4
TA = MIN
TA
mV
2.4
3.4
0.22
TA = 25°C
UNIT
mV
-500'
to
2.4
MAX
500
+24
rTA = MAX
4.5 V
TYP*
to
2.2
VI = 0.4 V,
MIN
+15
TA = MIN
-0.5 V, ITA = 250C
Other input at 5.5 V,
VCC - MIN,
CD
...
VIO
VCC = MIN,
Vstrobe
n
:c"
MIN,
SN75115
MAX
-500'
TA - MAX
III
:CDa
=
TYP*
500
10l = 15mA
CD
...c
:c"
CD
...
VCC
10H = -5 mA
VOL
MIN
Vo
Differential input
Common-mode
VICR
SN55115
TEST CONOITIONS t
PARAMETER
0
t Unless otherwise noted V strobe = 2.4 V. All parameters with the exception of off-stBte open-collector output current are measured with the active pull-up
connected to the sink output.
i All typical values are at
Vce
= 5 V, TA = 25°C, and VIC = O.
r~spect to the A input terminal.
, The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for threshold voltages only.
§ Differential voltages are at the B input terminal with
U Only one output should be shorted to ground at a time, and duration of the short-drcuit should not exceed one second.
switching characteristics. Vee = 5 V. eL ... 30 pF. TA PARAMETER
Propagation delay time,
tpLH
low-to-high-Ievel output
Propagation delay time,
tpHL
4-124
high-to-Iow-Ievel output
25°e
SN55115
TEST CONDITIONS
MIN
SN75115
TYP
MAX
RL =' 3.9 klJ. See Figure 1
18
RL = 390 11, See Figure 1
20
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX
~55012
• DALLAS, TEXAS 75265
MIN
UNIT
TYP
MAX
50
18
75
ns
50
20
75
ns
SN55115, SN75115
DUAL DIFFERENTIAL LINE RECEIVERS
PARAMETER MEASUREMENT INFORMATION
OPEN
5V
~
'" 5 ns-.!
OIFFERENTIAl
INPUT
i!Io
.L
1~
RESPONSE
TIME CONTROL
OPEN
.
OUTPUT
I
10%
V
3V
I
If-tpHl
~
j4-tPlH
I
~
I
1.5V
1.5V
VOH
I
-----VOl
TEST CIRCUIT
NOTES:
- - - - +3
90%:X
10 V I
-
I
~
1--'" 5 ns
~
90%
V
WAVEFORMS
A. The pulse generator has the following characteristics: Zout = 50 Il, PRR " 500 kHz, tw = 100 ns, duty cycle = 50%.
B. CL includes probe and jig capacitance.
FIGURE 1, PROPAGATION DELAY TIMES
TYPICAL CHARACTERISTICS
II
...
II)
Q)
>
INPUT CURRENT
vs
INPUT VOLTAGE
'i
(,)
Q)
6
4
';:
C
Q)
c:
V
:.:::i
/
-4
-6
/
V
/
V
-25-20-15-10-5
0
5
10 15 20 25
VI-Input Voltage-V
FIGURE 2
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-125
SN55115,
SN~5115
DUAL DIFFERENTIAL LINE RECEIVERS
.TYPICAL CHARACTERISTICSt
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
4_0
3_4
3_2
>
.
I
i
~
S
...
S
•
I
I
VOH (VIO -
1
T
I
-0.5 V, IOH -
.I.
I
-5 mA,!--
1.6
~
No Load
TA - 25°C
5
_~~t--
VCC - 5.5 V
>
..
I
~
i'"
>
2.0
1.2
S·
6
VCC - 4_5 V
2.4
o
I
r-
2.8
OUTPUT VOLTAGE
vs
COMMON-MOOE INPUT VOLTAGE
S
VCC - 5
4
I
3
~
0
I
~
2
>
0.4 I - - VOL,(VIO - 0.5 V, IOL - 15 mAI_
CD
o
:::!.
-75 -50 -25
<
CD
0
I
I
I
25
50
75
I
~
j"VIO - 1 V
I
I
I
o
100 125
-25-20-15-10-5
TA-Free-Air Temperature- °C
Ul
I
I I .t
VIO - -1 V
0
0.8
C
vi
VCC - 4.5 V
FIGURE 3
CD
0
5
10 15 20 25
Vlc-Common-Mode Input Voltage-V-
FIGURE 4
(')
CD
HIGH-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
<'
...en
CD
0.4
5
VIO - -0.5 V
TA - 25°C
~
~
~
~V"..;;;;;
1'£Cf..::. 4.StI/.
""
"
i
S
o
-20
-30
VIO - 0.5 V
TA - 25°C
~
0.3
VCC-4.~v
~
0.2
]
~
. V
-1
0.1
V
V
VCC - 5.5 V
V
o
>
~
-10
>
I
&
!
1/.'
~v
..........
o
o
LOW-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
-40
-50
o
o
IOH-High-Level Output Current-rnA
5
10
15
20
25
30
IOL -Low-Level Output Current-rnA
FIGURE 5
FIGURE 6
t Data for temperatures below OOC and above 70°C and for supply voltages below 4.75 V and above 6.25 V are applicable to SN56115
circuits only. These parameters were measured with the active pull-up connected to the sink output.
4-126
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS. TEXAS 75266
SN55115, SN75115
DUAL DIFFERENTIAL LINE RECEIVERS
TYPICAL CHARACTERISTICS t
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
6
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
6
Vee· 5 V
Load - 2 kG to Vee
I
I
4
...
0
I
Ol
3
4
~
I I
15
5
5
"
TA • 125°e
l!!
>
Vee - 4.5 V
>
>
Ol
Vee - 5 V
5
5
"
Vee. 5.5 V
,
0
>
~ .15 oe
5 3
TA -
-55°e
0
2
2
I
>
en
o
o
-0.2
o
-0.1
0.1
-0.2
0.2
-0.1
5
I
>
5
;
0
I
0
>
I
"
Ol
4
C
>
5
:::::i
0
I
0
!vee - 4.50:
j
I
3
2
T~
>
o
o
4
= 0.5 V
'", V TA"I = 125°e
V
" TAI- -55°e
I I
;
~\
3
CI)
c:
I--
15
2
>
VI,
l!!
2
o
o
en
CI)
5
>
\
vee· 5
a:
Vee - 5 V
No Load
~
3
-.
CI)
0.2
6
!\.
0
0.1
OUTPUT VOLTAGE
vs
STROBE INPUT VOLTAGE
, N
1\
4
u
o
';::
No Load
VIO - 0.5 V
TA - 25°e
I
1
Vee - 5.5 V
'0)
FIGURE 8
OUTPUT VOLTAGE
vs
STROBE INPUT VOLTAGE
>
>
VID-Oifferentiallnput Voltage-V
FIGURE 7
6
CI)
Load - 2 kG to Vee
TA - 25°e
Vlo-Oifferentiallnput Voltage-V
Ol
.
0
0
>
"
~
•
;
/..---1..-0
I
= k5 0 e
2
3
4
Vstrobe-Strobe Input Voltage-V
Vstrobe-Strobe Input Voltege-V
FIGURE 10
FIGURE 9
t Data for temperatures below ooe and above 70°C and for supply voltages below 4.75 V and above 5.25 V are applicable to SN55115
circuits only. These parameters were measured with the active pull up connected to the sink output.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-127
SN55115. SN75115
DUAL DIFFERENTIAL LINE RECEIVERS
TYPICAL CHARACTERISTICS t
SUPPLY CURRENT
(BOTH RECEIVERS)
vs
SUPPLY VOLTAGE
60
SUPPLY CURRENT
(BOTH RECEIVERS)
vs
FREE-AIR TEMPERATURE
40
No Load
TA - 25 DC
35
50
~
I
!
•
B INPUT AT VCC
40
AINPUTAT~
::I
(.)
~
30
g;
::I
'f
/.
20
(.)
C
J;
::s
//
10
CD
....2"C
...
en
o .......
o
CD
1/
=t>--SN75115 RECEIVER
"ii)
CJ
t A capacitor may be connected in series with Zo to reduce power dissipation.
FIGURE 15. BASIC PARTY-LINE OR DATA-BUS DIFFERENTIAL DATA TRANSMISSION
II)
-...
a::
en
II)
>
";:
C
II)
c
::i
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-129
r-
S'
..
CD
C
~'
Cil
:a
~
CD
l-en
4-130
SN55116 THRU SN55119
SN75116 THRU SN75119
DIFFERENTIAL LINE TRANSCEIVERS
02143. MAY 1976-REVISEO SEPTEMBER 1986
features common to all types
additional features of the SN55116/SN75116
•
Single 5-V Supply
•
Independent Driver and Receiver
•
3-State Driver Output Circuitry
•
•
TTL-Compatible Driver Inputs
Choice of Open-Collector or Totem-Pole
Outputs on Both Driver and Receiver
•
TTL-Compatible Receiver Output
•
Dual Data Inputs on Driver
•
Optional line-Termination Resistor in
Receiver
•
Differential Line Operation
•
Receiver Output Strobe ('116, '117) or
Enable ('118, '119)
•
Designed for Party-Line (Data-Bus)
Applications
•
Choice of Ceramic or Plastic Packages
•
± 15-V Receiver Common-Mode Capability
•
Receiver Frequency Response Control
additional features of the SN55117/SN75117
•
Driver Output Internally Connected to
Receiver Input
•
...CD
The SN55118/SN75118 is an SN55116/SN75116 with 3-State Receiver Output Circuitry
The SN55119/SN75119 is an SN55117/SN75117 with 3-State Receiver Output Circuitry
II)
>
"ij)
description
u
These integrated circuits are designed for use in interfacing between TTL-type digital systems and differential
data transmission lines. They are especially useful for party-line (data-bus) applications. Each of these circuit
types combine in one package a three-state differential line driver and a differential-input line receiver,
both of which operate from a single 5-volt power supply. The driver inputs and receiver outputs are TTL
compatible. The driver employed is similar to the SN55113/SN75113 three-state line driver, and the receiver
is similar to the SN55115/SN75115 line receiver.
The '116 and '118 circuits offer all the features of the SN55113/SN75113 driver and the
SN55115/SN75115 receiver combined. The driver performs the 'dual input AND and NAND functions when
enabled, or presents a high impedance to the load when in the disabled state. The driver output stages
are similar to TTL totem-pole outputs, but have the current-sink portion separated from the current-sourcing
portion and both are brought out to adjacent package pins. This feature allows the user the option of using
the driver in the open-collector output configuration, or, by connecting the adjacent source and sink pins
together, of using the driver in the normal totem-pole output configuration.
-...
CD
a::
I I)
CD
>
";:
C
CD
::i
The receiver portion of the '116 and '118 features a differential-input circuit having a common-mode voltage
range of ± 15 volts. An internal 130-ohm resistor is also provided, which may optionally be used for
terminating the transmission line. A frequency response control pin allows the user to reduce the speed
of the receiver or to improve differential noise immunity. The receiver of the '116 also has an output strobe
and a split totem-pole output. The receiver of the '118 has an output-enable for the three-state split totempole output. The receiver section of either circuit is independent of the driver section except for the Vee
and ground pins.
The '117 and '119 circuits provide the basic driver and receiver functions of the '116 and '118, but use
a package that is only half as large. The '117 and' 119 are intended primarily for party-line or bus-organized
systems as the driver outputs are internally connected to the receiver inputs. The driver has a single data
input and a single enable input, and the' 117 receiver has an output strobe while the' 119 receiver has
a three-state-output enable. These devices do not, however, provide output connection options, line
termination resistors, or receiver frequency-response controls.
The SN55116, SN55117, SN55118, and SN55119 are characterized for operation over the full military
temperature range of -55 De to 125 De; the SN75116. SN75117. SN75118, and SN75119 are
characterized for operation from ODe to 70 De.
PRODUCTION DATA d... manll c.ntain info,..ali••
cu,rant u at publicatl•• data. PredDeII c••form to
_iflclli••• per Iha terms at Taul Inll,u ..anll
:.=~~.r'::I':.'1i =:~ti::
:.r::::::.::-
not
Copyright @ 1980, Texas Instruments Incorporated
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
c
4-131
SN55116 THRUSN55119, 5N75116 THRU SI75119
DIFFERENTIAL LINE TRANSCEIVERS
SN55116 . .. J PACKAGE
SN75116 ... D. J.OR N PACKAGE
SN55118 . .. J PACKAGE
SN75118 ... D. J. OR N PACKAGE
(TOP V(EWI
DZP
DZS
DYS
DYP
RA
1 V,6
2
3
4
RT
5
6
RB
GND
8
(TOPVIEWI
b! VCC
DZP
DZS
DB
DA
DE
RYP
RYS
RS
RTC
15
14
13
12
11
10
9
RT
RB
GND
SN55116
FK PACKAGE
U
NNU Um
U
(J) 0..
(J) 0..
ooz>o
002>0
3
N N U
3
2 1 20 19
18
17
16
15
14
6
8
DYS
DYP
NC
RA
RT
DA
DE
NC
RYP
RYS
oco
2 1 20 19
4
18
5
17
6
16
15
14
7
8
DA
DE
NC
RYP
RYS
9 1011 1213
9 1011 1213
mouu
CDouucn
w
a:ZZl-a::
a::ZZI-CC
Cl
a:
SN65117 ... JG PACKAGE
SN75117 ... D. JG. OR P PACKAGE
SN55119 . .. JG PACKAGE
SN75119 ... D. JG. OR P PACKAGE
(TOP VIEWI
(TOP VIEWI
Cl
a:
01
0108
B
2
A
3
GND
4
VCC
.DE
RY
5 RS
B
A
7
6
2
3
8
7
6
4
6
SN55117
FK PACKAGE
SN55119
FK PACKAGE
(TOP VIEWI
(TOP VIEWI
U
zoz>z
3
3212019
"\,!..!, 12
2 1 20 19
NC
B
NC
A
NC
NC
17[ DE
161 NC
15 RY
14 NC
18
4
5
6
VCC
DE
RY
RE
u _ u uu
zoz>z
u _ u uu
NC
B
NC
A
NC
0
GND
U
18
17
16
15
14
13
9 1011 1213
uoucnu
~~~~~
9
ZZZa:Z
Cl
Cl
NC-No internal connection.
4-132
6
SN55118
FK PACKAGE
(TOP VIEWI
(TOPVIEWI
DYS
DYP
NC
RA
RT
VCC
DB
DA
DE
RYP
RYS
RE
RTC
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75285
NC
DE
NC
RY
NC
SN55116 THRU SN55119. SN75116 THRU SN75119
DIFFERENTIAL LINE TRANSCEIVERS
'116, '118
'117, '119
FUNCTION TA8LE
FUNCTION TABLE
OF ORIVER
OF DRIVER
INPUTS
INPUTS
OUTPUTS
DE
DA
08
DY
L
X
X
H
H
L
X
X
L
H
H
H
OUTPUTS
B
A
DZ
01
DE
Z
Z
H
H
H
L
L
L
H
L
X
H
L
H
L
Z
Z
H
L
H
'116, '118
'117, '119
FUNCTION TA8LE OF RECEIVER
FUNCTION TABLE OF RECEIVER
RSIRE
INPUTS
OUTPUT RY
DIFF
RSIRE
'117
H
L
H
H
H
L
H
H
L
L
X
X
L
H
Z
'116
'118
A
Z
H
L
L
X
H
H
L
H
H
H
L
OUTPUT RY
'119
B
INPUT
II
.
II)
CD
>
·iii
H = high level (VI'" VIH min or VID more positive than VTH max)
L = low level (VI s VIL max or VIO more negative than VTL max)
X = irrelevant
Z = high impedance (off!
(,)
CD
a:
--.
I I)
CD
>
.;:
schematics of inputs and outputs
Q
EQUIVALENT OF
EACH DRIVER INPUT
AND EACH RE AND RS INPUT
4kll
VCC~--NOM
INPUT
EQUIVALENT OF
EACH RECEIVER INPUT
(EXCLUOING ENABLES
AND STROBES)
CD
TYPICAL OF ALL OUTPUTS
c
:.::;
----~~------._---VCC
Vcc----------~1 pF NOM
INPUT~...........M
7kll
NOM
..........-
8kll
NOM
R
PULLUP
'----------....,--<'-- OUTPUTt
~___
--- Y
",""",
SINK
Driver output R - 9 !l NOM
Receiver 'output R - 20!l NOM
tOn 117 and '119, common outputs replace
the separate pullup and sink outputs.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 665012 .. DALLAS, TEXAS 75265
4-133
SN55116 THRU SN55119, SN75116 THRU SN75119
DIFFERENTIAL LINE TRANSCEIVERS
logic diagrams (positive logic)
logic symbols t
'116 AND '116 DRIVER
'116
DE (13)
&1>
DE (13)
(4) DVP
(3) DVS
EN
DA (14)
DB (15)
DZP
DA(1
:..:...;.4:....). . , - -.....L--'
DZS
DB (15)
&1>
I>
'116 RECEIVER
RT
RS
RTC
'118
&1>
r-
:i'
DE (13)
CD
EN
'118 RECEIVER
DA (14)
C
DB (15)
:::'!.
~
Ul
-
I>
~
CD
n
CD
..:c:CD
til
RS(~5~)
'117 DRIVER AND RECEIVER
__________________,
'117
DE (7)
I>
EN
(3) A
(2) B
01
L-_ _ _ _ _+-.-__!:.:.::: : } BUS
'119 DRIVER AND RECEIVER
'119
DE (7)
01 (1)
I>
EN
1-_ _---:(:.::,:3)
A
~)-_.:.;;(6~) RV
(2) B
~
(3) A}
_____+-+-__~(2)8
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown for '116 and '118 are for J and N packages; those shown for '117 and '119 are for JG and P packages.
4-134
TEXAS ..,
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
BUS
SN55116 THRU SN55119, SN75116 THRU SN75119
DIFFERENTIAL LINE TRANSCEIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
'116,
'117,
'118
'119
7
7
IDA, DB, DE, 01, RE, RS
5.5
5.5
IRA, RB, RT
±25
Supply voltage, VCC
Input voltage, V,
IA
V
V
o to
and B
6
V
12
Off-state voltage applied to open-collector outputs
SN75116
SN55116
UNIT
THRU
THRU
SN55119
SN75119
o package
950
FK package
•
1375
Continuous total dissipation at (or below)
J package
1375
1025
,25 ac free-air temperature (see Note 2)
JG package
1050
825
N package
1150
P package
1000
-55 to 125
-65 to 150
Operating free-air temperature range
Storage temperature range
Case temperature for 60 seconds: FK package
mW
~
o to 70
65 to 150
260
Lead temperature 1,6 mm (1/16 inch) from case
300
for 60 seconds: J and JG packages
~
°c
°c
°c
300
°c
260
°c
"Qi
f.)
CD
-a:
~
Lead temperature 1,6 mm (1/16 inch) from case
for 1 0 seconds: 0, N, or P package
NOTES:
UNIT
CD
>
";:
1. All voltage values are with respect to network ground terminal.
2. For operation above 25
free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the FK and J packages,
SN55116 through SN55119 chips are alloy mounted and SN75116 through SN75119 chips are glass mounted. In the JG
package, SN55117 and SN55119 are alloy mounted and SN75117 and SN75119 chips are glass mounted. In the N package,
use the 9.2 mW/oC curve for these devices. In the P package, use the 8-mW/oC curve for these devices.
ac
0
CD
::i
recommended operating conditions
SN55'
PARAMETER
Supply voltage, VCC
High-level input voltage, V,H
All inputs except
Low-level input voltage, V,L
differential inputs
High-level output current, IOH
Low-level output current, IOl
Receiver input voltage,
V,
Operating free-air temperature, T A
SN75'
MIN
TYP
MAX
MIN
TYP
MAX
4.5
5
5.5
4.75
5
5.25
2
Drivers
2
0.8
0.8
V
mA
Receivers
-5
Drivers
40
40
Receivers
15
15
±15
±15
'117, '119
0
-55
TEXAS ..,
INSTRUMENTS
POST OFFICE SOX 655012 • DALLAS, TEXAS 75265
V
V
-40
-5
'116, '118
UNIT
-40
6
0
6
125
0
70
C
mA
V
°c
4-135
SN55116 THRU SN55119, SN75116 THRU SN75119
DIFFERENTIAL LINE TRANSCEIVERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
driver section
VIK
Input clamp voltage
High-level output voltage VIL = 0.8 V,
VIH = 2 V
Vee = MAX,
10Z
.
-1.5.
2.4
3.4
2
3
1.8
I SN55'
I SN75'
Off-state
TA = 25'e
(high-impedance-state)
Vee - MAX, Vo = 0
output current
DE at 0.8 V,
Vo = 0.4V to Vee
TA = MAX
Vo = 0 to Vee
3
1.8
TA = MAX
-1.5
2
-40 rnA
1
MAX
-0.9
3.4
2
TA = 25'e
TYP*
2.4
2
VIL = 0.8 V, 10L = 40 mA
Vo = 12 V
MIN
UNIT
V
V
0.4
0.4
V
-1.5
-1.5
V
10
200
.A
20
±10
I SN55'
I SN55'
I SN75'
-300
.A
±150
±20
Input current
II
at maximum
Vee = MAX, VI = 5.5 V
1
1
mA
Vee = MAX, VI = 2.4 V
40
40
~
Vee = MAX, VI = 0.4 V
-1.6
-1.6
mA
-120
mA
60
mA
input voltage Driver or
CD
<'
CD
-0.9
Vee = MAX, Vo = 0 to Vee, DE at 0.8 V,
::rJ
CD
MAX
Vee = MIN, VIH = 2 V,
Vee = MAX, 10 = -40 mA, DE at 0.8 V
'117, '119
TYP*
10H = -10 mA
10H -
Off-state open-collector
CD
n
ISN55')
Output clan:'p voltage
C
iil
= -55°C to 125°C
VOK
5'
-
TA = o'e to 70'e ISN75') 10H = -40 rnA
TA
Low-level output voltage
r-
..<'
10H = -lOrnA
TA = 25'e ISN55')
VOL
'O(oft) output current
CD
MIN
Vee = MIN, 11= -12mA
Vee = MIN,
VOH
'116, '118
TEST CONDITIONS t
PARAMETER
High-level
IIH
enable
input current input
Low-level
IlL
C/l
input current
Short-circuit
lOS
output current §
-40
Vee = MAX, Vo = 0, TA = 25'e
Supply current (driver
ICC
and receiver combined)
-120
42
Vee = MAX, TA = 25'e
-40
60
42
t All parameters with the exception of off-state open-collector output current are measured with the active pull-up connected to the sink output. For conditions
:j:
shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at Vee = 5 V and TA = 25°C.
§ Not more than one output should be shorted 'at a time, and duration of the short circuit should not. exceed one second.
switching characteristics. Vee" 5 V. eL == 30 pF. TA .. 25°e
driver section
PARAMETER
TEST CONDITIONS
tpLH Propagation delay time, low-to-high-Ievel output
See Figure 13
tpHL Propagation delay time, high-to-Iow-Ievel output
MIN
TYP
MAX
14
30
12
30
UNIT
ns
tpZH Output enable time to high level
RL= 18011,
See Figure 14
8
20
ns
tpZL Output enable time to low level
RL - 250 n,
See Figure 15
17
40
ns
tpHZ Output disable time from high level
RL- 18011,
See Figure 14
16
30
ns
tpLZ Output disable time from low level
RL - 250 II,
See Figure 15
20
35
ns
4-136
TEXAS . "
INSTRUMENTS
POST OFFiCe BOX 655012 • DALLAS, TeXAS 75265
SN55116 THRU SN55119, SN75116 THRU SN75119
DIFFERENTIAL LINE TRANSCEIVERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
receiver section
PARAMETER
TEST CONOmoNst
'116. '118
MIN TYP*
MAX
'117. '119
MIN TYP* MAX
0.5
0.5
1
1
Vee - MIN.
high-threshold yoltage§
Vo ~ 0.4 V.
See Note 3
Differential input
low-threshold voltage §
See Note 3
Differential input
VTH
VTL
Vo
~
2.4 V.
~
IOL
15 mAo
See Note 4
~
Vee; - MIN.
-5 mAo See Note 4
Vee - 5 V.
See Note 5
V,
VOH
Input voltage range#
High-level output voltage
Vee
~
5 V. V,O ~ -1 V or 1 V, See Note 3
V,O - -0.5 V,
Vee - MIN,
IOH ~ -SmA. See Note 4
See Note 3
Vee - 5 V.
V,O -
-1 V.
See Note 5
VOL
'Hree)
Low-level output voltage
Receiver input current
Input current at
IOL
=
15 mAo
See Note 3
Vee ~ MAX.
See Note 3
Vee ~ MIN.
See Note 4
V,O
Vee - 5 V.
See Note 5
V, ~ OV,
0.4 V,
V,
V, - 2.4 V.
0.5 V,
V,O -
V,O - 1 V,
"
Strobe
maximum input
voltage
Enable
Vee - MIN,
Vstrobe = 4.5 V
V,
Vee - MAX,
"H
High-level
input current
Vee
',L
Low-level
input current
'iRe)
'01011)
10Z
RT
lOS
lee
Enable
Strobe
Enable
Response·time·control
current (Pin 9)
Off-state open-collector
output current
Off-state
(high-impedance state)
output current
Line-terminating resistance
Short-circuit
output current II
Supply current (driver
and receiver combined)
~
MAX,
V,
~
-0.5'
-0.5'
-1'
-1'
15
to
-15
6
to
0
2.4
2.4
2.4
2.4
V
V
0.5 V.
0.4
0.4
0.4
0.4
V
Other input at 0 V
Other input at 2.4 V
Other input at 0.4 V
-0.5
0.4
0.1
-0.9
0.7
0.3
-0.5
-0.4
0.1
-1
0.8
0.4
mA
'116. '117
5
5
pA-
5.5 V
'118, '119
1
1
mA
~
2.4 V
'118, '1,9
40
40
pA
'116, '117
-2.4
-2.4
'118, '119
1.6
1.6
Vee - 5 V
Vee - MAX, Va - 0,
V,O ~ -0.5 V, See Note 4
V,O - 0.5 V,
TA
~
25°e
-1.2
SN55'
SN75'
'118, '119
SN55118
SN55119
SN75118
SN75119
TA
~
25°e
TA
=
25°C
mA
mA
1
TA - 25°C
II
V
~
Vee - MAX, 'V,O - 0.5 V.
Vstrobe = 0.4 V, See Note 4
0.4 V
Vee - MAX,
V,
V,O - 0.5 V,
Vee - MAX,
RC at 0 V,
See Note 4
TA ~ 25°C
Vee - MAX,
Va ~ 12 V,
TA ~ MAX
V,O ~ -1 V
25°C
TA
Vee ~ MAX.
VO~ OtoVee,
TA ~ MAX
RE at 0.4 V
Vee - MAX,
See Note 4
V
Vee - 5 V.
See Note 5
IOH
UNIT
10
200
20
±10
±150
pA
±10
±150
pA
±20
±20
77
167
-15
-80
42
60
0
-15
42
-80
mA
60
mA
t Unless otherwise noted Vstrobe = 2.4 V. All parameters with the exception of off-state open-collector output current are measured with the active pull-up
connected to the sink output. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:t: All typical values are at Vec = 5 V, TA = 25°C, and VIC = O.
§ Differential voltages are at the B input terminal with respect tp the A input terminal. Neither receiver input of the '117 or '119 should be taken negative
with respect to GND.
, The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for threshold voltages only.
#Input voltage range is the voltage range that, if exceeded at either input, will cause the receiver to cease functioning properly.
~ Not more than one output should be shorted at-a time.
NOTES:
3. Measurement of these characteristics on the '117 and '119 requires the driver to be disabled with the driver enable at 0.8 V.
4. This applies with the less positive receiver input grounded.
5. For' 116 and' 118. this applies with the more positive receiver input at 15 V or the more negative receiver input at - 15 V. For' 117 and' 119.
this applies with the more positive receiver input at 6 V.
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-137
SN55116 THRU SN55119, SN75116 THRU SN75119
DIFFERENTIAL LINE TRANSCEIVERS
switching characteristics. VCC - 5 V. CL - 30 pF, TA - 25°C
receiver section
tpLH
tpHL
tPZH
tPZL
tpHZ
tpLZ
PARAMETER
Propallation delay time, low-to-high-Ievel output
Propagation delay time, high-to-Iow-Ievel output
Output enable time to high level
Output enable time to low level
Output disable time from high level
TEST CONDITIONS
RL = 480 II, See
RL = 250 II, See
RL = 480 II, See
RL = 250 II, See
'118
and
'119
only
Output disable time from low level
MIN
RL= 400 II, See Figure 16
TYP
MAX
20
75
75
ns
ns
20
ns
ns
ns
ns
17
Figure 14
Figure 15
Figure 14
9
16
12
17
Figure 1 5
35
30
35
UNIT
TYPICAL CHARACTERISTICS
DRIVER OUTPUT VOLTAGE
vs
DRiVER iNPUT VOLTAGE
r-
:i"
CD
6
>I
::x.r
~
CD
(')
CD
..
S
Vee= S_S V
&4
Vee=SV
~
Vee = 4_S V
:C"
"
S-
(II
0
I
0
CD
Vee=SV
No load
S
-.
(II
6
No load
TA= 2Soe
..
..
c
:c"
CD
DRIVER OUTPUT VOLTAGE
vs
DRIVE;R INPUT VOLTAGE
"
>
~
&4
:I
.s-"
~
3
9"0
2
3
.
2
>
4-
TA=-SSoe
I
r- -TA=2Soe
-
TA=12)e -
o
o
2
3
4
o
o
2
VI-Data Input Voltage-V
VI-Date Input Voltage-V
FIGURE 1
4-138
FIGURE 2
TEXAS ..,
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
I
3
4
SN55116 THRU SN55119, SN75116 THRU SN75119
DIFFERENTIAL LINE TRANSCEIVERS
TYPICAL CHARACTERISTICS
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
DRIVER LOW-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
0.6
I
TA = 25·C
TA = 25·C
~ 5~----~----~----~----~--~
t
~ 0.5
VCc=[/
j
~ 4~-=--~-
~
13~-=~+--
AV
V
0.4
i
~
]
0.3
"ii
:;
~ 2~----+------~----~--~~----~
-'
X
.9
~
~ 0.1
I
~
0.2
I
-'
[7
/
V
/
~
~
VCC = 5.5 V
•
f?
Q)
>
'Q)
U
-20
-60
-40
-100
-80
Q)
o
o
20
40
I
~
14
j:: 12
-
tpHL
~
...-
L-- I---
tpLH
~
c
8
&
6
~
...e
.
j::
:a
m
Q)
c
:J
25
I
I--- V
.~
20 f - -
V . . . '"
-I.?
tpZL
tpHZ
...
..
c
:a
..a-"
c 10
w
4
d
2
o
~
E
Q
~I
I
VCC=5V
See Note 6
is 15
"a
~ 10
.9
Q)
DRIVER OUTPUT ENABLE AND DISABLE TIMES
vs
FREE-AIR TEMPERATUREt
30
VCC=5V
CL = 30 pF
See figure 13
...
,~
FIGURE 4
DRIVER PROPAGATION DELAY TIMES
vs
FREE-AIR TEMPERATUREt
l: 16
120
IOL -Low-Level Output Current-mA
FIGURE 3
18
100
(I)
IOH-High-Level Output Current-mA
20
80
60
a:
........
-75 -50 -25
0
25
50
75
100
125
tPZH
5
~75
-50 -25
T A-free-Air Temperature-·C
0
25
50
75
100
125
TA-Free-Air Temperature-·C
FIGURE 5
FIGURE 6
t Data for temperatures below O·C and above 70°C are applicable to SN55116 through SN55119 devices only.
NOTE 6: For tpZH and tpHZ: RL = 180 D, see Figure 14. For tpZL and tpLZ: RL = 250 D, see Figure 15.
TEXAS ""
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-139
SN55116 THRU SN55119, SN75116 THRU SN75119
DIFFERENTIAL LINE TRANSCEIVERS
TYPICAL CHARACTERISTICS
RECEIVER OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
6
RECEIVER OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLrAGE t
6
Vcc = 5.5 V
VCC=5V
Load = 2 kG to Vcc
Load = 2 kG to VCC
TA=25·C
VCC=5V
5
5
VCC=4.5V
>I
..
1J, 4
~Ti=125.C
.!::
..=
=
.
0
>
3
a.
0
I
0
2
>
r
I
•
-TA=25 C
TA=-55·C~
S'
01
...C
~'
o
-0.1
o
0.1
VID-Differentiallnput Voltage-V
-0.2
iil
~
o
0.2
o
0.1
-0.1
VID-Differentiallnput Voltage-V
-0.2
FIGURi: 7
01
n
:C'
01
FIGURE 8
RECEIVER PROPAGATION DELAY TIMES
vs
FREE-AIR TEMPERATUREt
...01
III
30
25
I
.1.
VCC=5V
RL =400 G
See Figure 16
.--
V
-
tP~
.....-
i--
/'
RECEIVER OUTPUT ENABLE AND DISABLE TIMES
vs
FREE-AIR TEMPERATUREt
30
/
..
c:
I
..
.....-V
III
tpHL
~
00
~
Q
.....c:
100
20
:is
5
0
25
E
j::
1~
I--
I---
15
:is
c:
w
10
0=
5
;
S-
~~~
VCC=5V
See Note 7
;
...
o
---
tv /
""""'--1
tpZL
~
o
-75 -50 -25
0
25
50
FIGURE 10
FIGURE 9
4-140
75
TA-Free-Air Temperature-·C
t Data for temperatures below O°C and above 70°C are applicable to SN55116 through SN55119 devices only"
=
"I"
tpZH
TA:-Free-Air Temperature-·C
NOTE 7: For tpZH and tpHZ: RL
0.2
480 II. see Figure 14. For tpZL and tpLZ: RL
=
250 II. see Figure 15.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
100 125
SN55116 THRU SN55119, SN75116 THRU SN75119
DIFFERENTIAL LINE TRANSCEIVERS
TYPICAL CHARACTERISTICS
SUPPLY CURRENT (DRIVER & RECEIVER)
vs
FREE-AIR TEMPERATUREt
SUPPLY CURRENT (DRIVER AND RECEIVER)
vs
SUPPLY VOLTAGE
80
70
I
50
No load
TA = 25°e
45
I
~
::!
50
Col
>
C.
Co
"I
en
40
30
Col
!d 20
10
o
o
E 35
I
E
V
!;
)
Iv
~ 30
25
">
Col
/
is.
Co
"
en
I
Col
!d
20
III
Q)
>
'Q)
10
V
3
...
15
52
- --
«
/
E
:--r--
40
L
ct 60
4
5
6
7
8
(,)
Q)
Vee=5V
o
T
I
-75 -50 -25
vee-Supply Voltage-V
0
25
50
75
TA-Free-Air Temperature-Oe
FIGURE 11
a::
FIGURE 12
100 125
...
I II
Q)
>
';::
C
Q)
t Data for temperatures below GOG and above 7GoG are applicable to SN55116 through SN55119 devices only.
c
:::i
TEXAS ~
INSTRUMENTS.
POST OFFICE BOX 8&5012 • DALLAS, nXAS 75265
4-141
SN55116 THRU SN55119, SN75116THRU SN75119
DIFFERENTIAL LINE TRANSCEIVERS
PARAMETER MEASUREMENT INFORMATION
---1"---
FROM OUTPUT
TEST
UNDER TEST
POINT
1----l.-
FROM OUTPUT
UNDER TEST - -...
CL =30 pF
CL =30pF
(Se. Not. B)
. . (See Note B)
LOAD CIRCUIT
TEST
- - POINT
RL
+'
"=
LOAD CIRCUIT
1f-..5 ns
14-.. 5 ns
I
~=----OV
~;;';"'--VOH
OUTPUT
r-
5'
AND
OUTPUT
CD
...o
VOLTAGE WAVEFORMS
<'
CD
VOLTAGE WAVEFORMS
FIGURE 13. tPLH and tPHL (DRIVERS ONLVI
Ul
l :I
CD
n
FROM OUTPUT
UNDER TEST
CD
<'
CD
Ul
5V
iRL = 250 11
•.
TEST
POINT
CL = 30 pF
(See Note B)
--1:'--"'-+'
FIGURE 14. tPZH and tPHZ
...
FROM OUTPUT_..._"_"-4H"'--1~""IJUNDER TEST
LOAD CIRCUIT
LOAD CIRCUIT
-+l
*-.. 5 ns
50%
I
Jr.:~-_""'"::::="I~I_I- 90%
I
-
- - VH
(s. . Not. EI
i-,;.;l~O.;;%_ _ _ VL
-+I
VOH
OUTPUT
OUTPUT
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
FIGURE 15. tpZL and tPLZ
NOTES: A.
B.
C.
D.
E.
4-142
1.5 V
FIGURE 16. tpLH and tPHL (RECEIVERS ONLVI
Input pulses are supplied by generators having the following characteristics Zout = 50!l, PRR '" 500 kHz. tw = 100 ns.
CL includes probe and jig capacitance.
All diodes are 1N3064 or equivalent.
When testing the' 116 and. ' 118 receiver sections. the response-time control and the termination resistor pins are left open.
For·116and'IIB.VH = 3V.VL = -3V.theA input is atOV.
For '117 and '119, VH = 3 V, VL = 0 V, the A input is at 1.5 V.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS," TEXA.S 75265
SN55121, SN75121
DUAL LINE DRIVERS
01334. SEPTEMBER 1973-REVISEO SEPTEMBER 1986
•
SN55121 ... J PACKAGE
SN75121 ... D. J. OR N PACKAGE
Designed for Digital Data Transmission over
50-0 to 500-0 Coaxial Cable. Strip Line. or
Twisted Pair
•
High-Speed. . . tpd - 20 ns Max at
CL - 15 pF
(TDPVIEW)
1A
1B
1C
10
IE
IF
1Y
GNO
•
TTL Compatible with Single 5-V Supply
•
2.4-V Output at IOH -
•
Uncommitted Emitter-Follower Output
Structure for Party-Line Operation
•
Short-Circuit Protection
•
AND-OR Logic Configuration
•
Designed for Use with Triple Line Receivers
SN55122. SN75122
•
Designed to be Interchangeable with
Signetics N8T13
- 75 mA
VCC
2F
2E
20
2C
2B
2A
2Y
•
SN55121 ... FK PACKAGE
(TOP VIEW)
U
m'"
3
1C
10
NC
IE
1F
description
The SN55121 and SN75121 dual line drivers are
designed for digital data transmission over lines
having impedances from 50 to 500 O. They are
also compatible with standard TTL logic and
supply voltage levels.
The low-impedance emitter-follower outputs of
the SN.55121 and SN75121 will drive
terminated lines such as coaxial cable or twisted
pairs. Having the outputs uncommitted allows
wired-OR logic to be performed in party-line
applications. Output short-circuit protection is
provided by an internal clamping network that
turns on when the output voltage drops below
approximately 1.5 volts. All of the inputs are in
conventional TTL configuration and the gating
can be used during power-up arid power-down
sequences to ensure that no noise is introduced
to the line.
.
2 1 2019
I/)
18
17
16
4
5
6
7
2E
20
NC
2C
2B
Q)
>
"Gi
(,)
Q)
a:
9 1011 12 13
--
~~~~~
"i:
14
8
~
Q)
>
C
Cl
Q)
NC - No internal connection
I:
:.:i
FUNCTION TABLE
INPUTS
A
B
H
X
D
H
C
H
H
X
X
X
OUTPUT
E
X
H
All other input combinations
F
X
H
Y
H
H
L
H = high level
L = low level
X = irrelevant
The SN55121 is characterized for operation over
the full military temperature range of - 55 DC to
125 D
The SN75121 is characterized for
operation from ODC to 70 De.
e.
PRODUCTION DATA documents contein information
current as of publication data. Products conform to
spBcifications per the terms of Tlxas Instruments
:::~:~~i~l{nr:I~1~ ~:~:;ti:; :.~o::;:::::~~~
not
Copyright @ 1984, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-143
SN55121, SN75121
DUAL LINE DRIVERS
logic symbol t
logic diagram (positive logic)
&
lA (1)
",1[>
lA~:-.,...-_
lB
lC
lB (2)
lC (3)
~
(4)
10
(5)
1E
m lV
lD~""''''''--
lE
&
IF
(6)
IF
(10)
2A
2B 111)
2C (12)
2A",*~
(9) 2V
20 (13)
2E (14)
III
r-
:i"
CD
...c
___....
2B
2C
2D..u...........- -
2V
2E
2F 115)
2F
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12_
Pin numbers shown are for J I;Ind N packages.
schematic (each driver)
vcc----~----~----_.----~----------~--~~--~~----_.__,
TO OTHER
4kO
4kO
3600
150
LINE DRIVER
.
.<'
<'
CD
fI)
::0
A ____J
CD
(')
CD
B----+-...
CD
C
----+--1-•
o ----jf--++.
fI)
-----f--.....--- v
E----+-~r+------------_+
F----+-~r+------------_4~
GND----~~~~--------------~~~~~~~~~~~~----~
TO OTHER
LINE DRIVER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SN55121
SN75121
UNIT
Supply voltage, V CC Isee Note 1)
6
6
V
Input voltage
6
6
V
Output voltage
6
6
V
D package
Continuous total dissipation at (or below)
25·C free air temperature Isee Note 2)
950
FK or J package
J package
1375
N package
-55 to 125
Operating free-air temperature range
Storage temperature range
65 to 150
Case temperature for 60 seconds FK package
260
Lead temperature 1,6 mm 11/16 inch) from case for 60 seconds: J package
300
Lead temperature 1,6 mm 11/16 inch) from case for 10 seconds:
mW
1025
1150
D or N package
o to 70
·C
65 to 150
·C
·C
300
·C
260
·C
NOTES: 1. All voltage values are with respect to both ground terminals connected together.
2. For operation above 25·C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the J package, SN55121
chips are alloy mounted and SN75121 chips are glass mounted. In the N package, use the 9.2 mW/·C curve for these devices.
4-144
TEXAS •
INSTRUMENTS
POST OF~I~& BOX 6&501 a • DALLAS, TEXAS 1&aO'
SN55121, SN75121
DUAL LINE DRIVERS
recommended operating conditions
SN55121
Supply voltage, V CC
SN75121
MIN
NOM
MAX
MIN
4.75
5
5.25
4.75
High-level input voltage, VIH
NOM MAX
5
5.25
2
2
Low-level input voltage, VIL
Operating free-air temperature, T A
-55
125
V
V
0.8
-75
High-level output current, 10H
UNIT
0.8
-75
V
mA
70
°C
0
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
=
=
=
=
VIK
Input clamp voltage
VIBR)I
VOH
Input breakdown voltage
VCC
High-level output voltage
VIH - 2 V,
10H -
VCC - 5 V,
VIH - 4.5 V,
VCC
II
5 V,
II
5 V,
10H
High-level output current
10L
Low-level output current
VIL - 0.8 V,
1010ffi
IIH
Off~state
VCC - 3 V,
High-level input current
VI
IlL
Low-level input current
VI
lOS
Short-circuit output current
VCC - 5 V,
ICCH
Supply current, outputs high
ICCL
Supply current, outputs low
VCC = 5.25 V,
VCC - 5.25 V,
TA
output current
=
= 4.5
= 0.4
5.5
10 mA
-75 mA,
VOH - 2 V,
VOL - 0.4 V,
Vo - 3 V
V
-100
See Note 3
-250
mA
-800
~A
500
~A
40
~A
-1.6
mA
-30
mA
V
-0.1
V
TA - 25°C
All inputs at 2 V,
UNIT
V
V
2.4
See Note 3
See Note 3
25°C,
MAX
-1.5
MIN
-12 mA
Outputs open
28
mA
All inputs at 0.8 V, Outputs open
60
mA
II
~
CD
>
'Qi
(.)
CD
-...'"
a:
CD
>
.;:
tNot more than one output should be shorted at a time.
NOTE 3. The output voltage and current limits are guaranteed for any appropriate combination of high and low inputs specified by the
function table for the desired output.
C
CD
switching characteristics. Vee = 5 V. TA = 25°e
tpLH
TEST CONDITIONS
PARAMETER
Propagation delay time, low-to-high-Ievel output
tpHL
Propagation delay time, high-to-Iow-Ievel output
tpLH
Propagation delay time, low-to-high-Ievel output
tpHL
Propagation delay time, high-to-Iow-Ievel output
TYP
MAX
RL = 37 II, CL
See Figure 1
=
15 pF,
MIN
11
20
8
20
RL = 37 II, CL
See Figure 1
=
1000 pF,
22
50
20
50
UNIT
ns
ns
PARAMETER MEASUREMENT INFORMATION
_
t--... 5 ns
--...I
... 5 ns
'ic::::::::----:::::::-'lI::'--t90%
,
3V
- - -
1.5V, :
I
10%
,
}-I.......-----.-OUTPUT
tpLH-i'-----<.."',
,
I
CL
(See Not. B)
OV
I
,
1_5~VOH
-----'
VOLTAGE WAVEFORMS
TEST CIRCUIT
3V
tPHL~
f.5V
OUTPUT
VOL
FIGURE 1_ SWITCHING TIMES
NOTES: A. The pulse generators have the following characteristics: Zout
B. Cl includes probe and jig capacitance.
= 50 II, tw = 200 ns, duty cycle s
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS; TeXAS 75265
C
:::;
50%.
4-145
SN55121, SN75121
DUAL LINE DRIVERS
TYPICAL CHARACTERISTICS
OUTPUT CURRENT vs OUTPUT VOLTAGE
-300
VCC=5V
VIH =2V
TA=25·C
-250
l-200
'\
~
!
8 -150
I\.
1\
~
•
0-100
I
E
\
-50
r-
5'
o
G)
...c
~'
...en
o
\
0.5
1
1.5
2
2.5
3
3.5
4 4.5
5
Vo-Output Voltage-V
FIGURE 2
::a
TYPICAL APPLICATION DATA
G)
(')
G)
i -'13 SN55122-
:c'
-i
I
...
G)
I
en
I
I
L!!~~~g!..J
I
I
L_l~ J!~[!~.:d
FIGURE 3. SINGLE-ENDED PARTY LINE CIRCUITS
4-146
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN55122. SN75122
TRIPLE LlNE·RECEIVERS
01334, SEPTEMBER 1973-REVISEO SEPTEMBER 19B6
•
•
•
Designed for Digital Data Transmission Over
Coaxial Cable. Strip line. or Twisted Pair
(TOP VIEW)
Designed for Operation with 50·0 to 500·0
Transmission lines
1A
18
2R
2S
2A
28
2Y
TTL Compatible
•
Single 5-V Supply
•
Built-In Input Threshold Hysteresis
•
High Speed . . . Typical Propagation
Delay Time - 20 ns
•
Independent Channel Strobes
•
Input Gating Increases Application Flexibility
•
Fanout to 10 Series 54/74 Standard Loads
•
Can be Used with Dual Line-Drivers
SN55121 and SN75121
•
SN55122 •.• J PACKAGE
SN75122 .•. D, J, OR N PACKAGE
VCC
1S
1R
1Y
3A
3S
3R
3Y
GND
SN55122 ..• FK PACKAGE
II
.
(TOP VIEW)
U
m~
3
Interchangeable with Signetics NBT14
description
The SN55122 and SN75122 are triple linereceivers that are designed for digital data
transmission over lines having impedances from
50 to 500 ohms. They are also compatible with
standard TTL logic and supply voltage levels.
2
11)
1 2019
2R
2S
4
18
5
17
1R
1Y
NC
6
16
NC
2A
28
8
14
3A
3S
7
Q)
.~
Q)
(.)
Q)
a:
"""-
..
11)
9 1011 1213
Q)
>
>OU>a::
.~
o
NZZ('t)(I')
t:l
Q)
c:
NC-No internal connection
:::i
The SN55122 and SN75122 have receiver inputs with built-in hysteresis to provide increased noise margin
for single-ended systems. The high impedance of this input presents a minimum load to the driver and
allows termination of the transmission line in its characteristic impedance to minimize line reflection. An
open line will affect the receiver input as would a low-level voltage. The receiver can withstand a level
of - 0.15 volt with power on or off. The other inputs are in TTL configuration. The S input must be high
to enable the receiver input. Two of the line receivers have A and B inputs that. if both are high, will hold
the output low. The third receiver has only an A input that, if high, will hold the output low.
The SN55122 is characterized for operation over the full military temperature range of - 55°C to 125°C.
The SN75122 is characterized for operation from O°C to 70°C.
PRODUCTION DATA documents contain information
current IS of publication date. Pradaets conform to
specificatioRs par the terms of TaXI. Instruments
==i:;ai~:I:.r~ =::i~n :.o::::::~~s
not
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 665012 • DALLAS. TeXAS 75265
4-147
SN55122, SN75122
TRIPLE LlNE·RECEIVERS
logic symbol t
logic diagram
1R
1S~~-z~--~L--'
1A~~------~r-~
1A
1B~~--------L-~
1B
2R
2R.....;.~-dJlT
2S
2A
2S~~-%~--~L-~
2B
2A~~------~r-~
n---:'_71.....;. 2Y
2B.....;.~--------L_....~
3R
•
3R
3S
3S~--~~----L-~
3A
r::::
~
3A ----------~
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for D. J. and N packages.
CD
C
FUNCTION TABLE
:::!.
<
CD
...
en
INPUTS
A
H
fn
X
L
CD
~.
til
L
X
X
B*
H
X
X
X
L
L
OUTPUT
R
S
Y
X
L
X
H
H
X
L
L
H
H
H
H
X
L
H
X
X
L
t B input and last two lines of the
function table are applicable to
receivers 1 and 2 only.
H = high level
L = low level
X = irrelevant
4-148
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 6550.12 • DALLAS, TeXAS 75265
'91
n---3Y
SN55122, SN75122
TRIPLE LlNE·RECEIVERS
schematic diagram (each receiver)
4 kO
TO OTHER
RECEIVERS
800n
5BD
R (14.3.101
~11..:3.:..
• ..;7'..;9.;..1 y
II
...CD
I/)
>
'G)
U
CD
-
GND~(8~1~-'-'__-4~-+
a:
...
A (1.5.121
TO OTHER
RECEIVERS
I /)
CD
(2.61
§8-----
W'"
>
.~
C
Vee bus
§a input is provided on receivers 1 and 2 only.
Resistor values shown are nominal.
CD
c
:.:J
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. 6 V
Input voltage: R input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6 V
A, B, or S input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6 V
Output current .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 1 00 rnA
Continuous total power dissipation at (or below) 25 DC case temperature (see Note 2):
D package ......................................................... 950 mW
J or FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. 1375 mW
N package ........................................................ 11 50 mW
Operating free-air temperature range: SN55122. . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125 DC
SN75122 ............................. ODC to 70 DC
Storage temperature range ......................................... - 65°C to 150 DC
Case temperature for 60 seconds: FK package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260 DC
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............ 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package ........ 260 DC
NOTES:
1. Voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, refer to the Dissipation Derating Curves in Appendix A. In the FK and J package,
SN55122 chips are alloy mounted and in the J package, SN75122 chips are glass mounted. For derating the N package,
use the 9.2-mW/oe curve and for the 0 package, use the 7.6-mW/oe curve.
TEXAS ."
INSTRUMENTS
poaT OFFICE lOX 85&012 • DALLAS. tEXAS 15265
4-149
SN55122. SN75122
TRIPLE LlNE·RECEIVERS
recommended operating conditions
Supply voltage, Vee
High-level input voltage; VIH
Low-level input voltage, VIL
I A,
I A.
MIN
NOM
4.75
5
B. R, or S
O.B
•
r-
:r
CD
TEST CONDITIONS
I
VIK
Input clamp voltage
I
VUB!!1
Input breakdown voltage.
I
VOH
R
A.B. or S
A.B, or S
16
mA
°e
0
70
°e
...o
n
~.
~
MIN Typt
0.3
Vee = 5 V.
11=-12mA
Vee = 5 V,
II = 10 mA
5.5
VIH = 2 V,
VIL = 0.6 V. IOH = -500 pA
2.6
VIH = 2 V.
VOL
Low-level output voltage
IIH
High-level input current
IlL
Low-level input current
CD
CD
4.75 V to 5.25 V
MAX
0.6
UNIT
V
-1.5
V
V
VIIS) = 2 V.
V
2.6
IOH = -500 pA
<'CD
~
l:J
~
TA = 25°e
VIIB) = O.
VIIR) = 1.45 V Isee Note 3).
V
pA
125
Vee = 5 V,
VilA) = 0,
High-level output voltage
-500
-55
electrical characteristics over recommended operating free-air temperature. Vee
(unless otherwise noted)
PARAMETER
V
V
B, R, or S
.
I SN55122
OperatIng free-air temperature, TAJ SN75122
Hysteresis
5.25
2
High-level output current, IOH
Low-level output current. IOL
VhYS~
MAX UNIT
I
I
I
A,B, or S
R
A.B, or S
0.4
VIL = 0.6 V. IOL = 16 mA
VII B) = 0,
VilA) = O.
VIIR) = 1.45 V (see Note 4).
VIIS) = 2 V.
0.4
IOL = 16 mA
VI = 4.5 V
40
170
VI = 3.8 V
V
pA
VI = 0.4 V,
VIR = 0.8 V
-0.1
-1.6
mA
TA = 25°e
-50
-100
mA
72
rnA
100
mA
IOS§
Short-circuit output current
Vee = 5 V,
leeH
High-level supply current
leeL
Low-level supply current
Vee = 5.25 V, All inputs at 0.8 V. Outputs open
Vee = 5.25 V, All inputs at 2 V. Outputs open
t All typical values are at Vet = 5 V and T A = 25°e.
~ Hysteresis is the difference between the positive-going input threshold voltage, VT +. and the negative-going input threshold voltage.
VT _. See Figure 4.
§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
NOTES: 3. The receiver input was high immediately before being reduced to 1.45 V.
4. The receiver input was low immediately before being increased to 1.45 V.
switching characteristics. Vee - 5 V. TA - 25°e
TYP
MAX
tpLH Propagation delay time. low-to-high-Ievel output from R input
See Figure 1
20
30
tpHL Propagation delay time, high-to-Iow-Ievel output from R input
See Figure 1
20
30
PARAMETER
4-150
TEST CONDITIONS
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
·MIN
SN55122, SN75122
TRIPLE LlNE·RECEIVERS
PARAMETER MEASUREMENT INFORMATION
~
2.6 V
VCC
s 5
ns
I'f- S
-+I
I
PULSE
GENERATOR
(see Note AI
5 ns
licn=
__~=:-'\l'-·+
-- -- 2.6 V
90%
90%
I
I
1N3064
14--"'~+-1 tPLH
I
»f...-<........-OUTPUT
5 kO
OU_T_PU_T_ _
I
10%
I
I
tPHL-IoI14f---i~~1
OV
~~r.-5-v-------~\L~~V:H
~VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics: Zout
B. CL includes probe and jig capacitance.
FIGURE 1.
~
50 O. tw = 200 ns. duty cycle = 50%.
II
...
III
SWITCHING TIMES
II)
>
"Gi
(,)
II)
TYPICAL CHARACTERISTICS
a:
--I!!
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
II)
>
.t:;
o
4.0
>
I
CD
CO
."
!::
VCC - 5 V
3.5 -No load
TA - 25°C
3.0
II)
c
::::i
2.5
0
>
;
So
::I
2.0
0
1.5
0
1.0
VT-
VT+
I
>
0.5
o
o
0.4
0.8 1
1.4
1.8 2
V'-'nput Voltage-V
FIGURE 2
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4·151
SN55122. SN75122
TRIPLE LINE-RECEIVERS
TYPICAL APPLICATION DATA
r -1i3SNSS;22- - i
I
I
•
rS-
I
I
L~~~~l~~J
75-0 COAXIAL CABLE
CD
.
C
~-
ill
~
n
CD
'Qi
H = high level
L = low level
X = irrelevant
U
-...
Q)
I%:
I II
logic symbol t
The low-impedance emitter-follower outputs of
the SN75123 will drive terminated lines such as
coaxial cable or twisted pair; Having the outputs
uncommitted allows wired-OR logic to be
performed in party-line applications. Output
short-circuit protection is provided by an internal
clamping network that turns on when the output
voltage drops below approximately 1.5 volts. All
the inputs are in conventional TTL configuration
and the gating can be used during power-up and
power-down sequences to ensure that no noise
is introduced to the line.
Q)
>
'~
C
lA (1)
Q)
lB (2)
lC (3)
c:
::i
(7)1Y
10 (4)
&
lE (5)
(61
IF
2A (10)
2B (11)
(12)
2C
20
2E
The SN75123 is characterized for operation from
ooe to 70 oe.
2F
(9) 2Y
(13)
(14)
(151
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
logic diagram. each driver (positive logic)
A _ - - ' r - -.....
B
C
0--,,--_,,
Y
E
F
PRODUCTION DATA do.umanto contain information
currant as of publication date. Products conform to
specifications paf the terms of Texas Instruments
::=::i~a{::I~le ~=:~ti:r :.r::~:::~ru:s
nat
Copyright © 1986, Texas Instruments Incorporated
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS, TEXAS 75265
4-153
SN75123
DUAL LINE DRIVER
schematic (each driverl
e-____e-____~~______~__,
VCC~(~16~1~~____- .______~____~.-____________
TO OTHER
LINE DRIVER
4 kll
4 kll
360 II
16 II
A (1.101
B (2.111
C 13.121
D 14.131
17.91 y
E (5.141
•
F (6.151
GNDI~8~1~~~~~--------------~~~'-~-4~~~~~-4~----~
TO OTHER
LINE DRIVER
r-
:r
CD
...c
<"
CD
...en
Resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise notedl
Supply voltage, Vec (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
o package ......................................................... 950 mW
J package ......................................................... 1025 mW
N package ........................................................ 1150 mW
Operating free-air temperature range ...................................... O°C to 70°C
Storage temperature range .......................................... - 65°C to 150°C
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds: 0 or N package. . . . . . . .. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............. 300°C
-.
:lI
CD
(')
CD
...<"
CD
fI)
NOTES: 1. All voltage values. except differential input voltage. are with respect to network ground terminal.
2. For operation above 25°C free-air temperature. derate the D package to 608 mW at 7DoC at the rate of 7.6 mW/oC. the
J package to 656 mW at 70°C at the rate of 8.2 mW/oC. and the N package to 736 mW at 70·C at the rate of 9.2 mW/·C.
In the J package. SN75123 chips are gla•• mounted.
recommended operating conditions
MIN
4.75
Supply voltage. VCC
High-level input voltage. VIH
5
MAX
5.25
2
0.8
Low-level input voltage. VIL
High-level output current, IOH
Operating free-air tempeature, T A
4-154
NOM
0
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
100
70
UNIT
V
V
V
mA
°c
SN75123
DUAL LINE DRIVER
electrical characteristics. Vee - 4.75 V to 5.25 V. TA - ooe to 70 0 e (unless otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
Input clamp voltage
V(BRH Input breakdown voltage
VOH
High-level output voltage
10H
High-level output current
VOL
Low-level output voltage
VCC - 5 V,
II -
VCC - 5 V,
II - 10 mA
VCC - 5 V,
VIH - 2 V,
10H
= - 59.3
= 5 V,
= 25°C,
TA
Vo
High-level input current
IlL
Low-level input current
lOS
Short-circuit output current t
VCC
ICCH
Supply current, outputs high
Supply current, outputs low
VCC
=
=
5.25 V,
V
2.9
ITA - ooC to 70°C
V,
=
VOH
V
V
2 V,
-100
-250
mA
0.15
40
p.A
- 240 p.A, See Note 3
=3
V
-0.1
5 V,
UNIT
3.11
ITA - 25°C
See Note 3
10L -
IIH
ICCL
= 4.5
VIL - O.B V,
VCC = 0,
VI - 4.5 V
VI - 0.4 V
10(offl 011·51a1e output current
VIH
MAX
-1.5
5.5
mA, See Note 3,
VCC
MIN
-12mA
40
p.A
-1.6
mA
-30
mA
2B
mA
60
mA
TA = 25°C
All inputs at 2 V,
Outputs open
VCC - 5.25 V,
Outputs open
V
All inputs at O.B V,
II
.
en
tNot more than one output should be shorted at a time.
NOTE 3: The output voltage and current limits are guaranteed for any appropriate combination of high and low inputs specified by the
function table for the desired output.
-.
switching characteristics. Vee - 5 V. TA - 25°e
PARAMETER
en
TEST CONDITIONS
RL = 500,
Cl = 15 pF,
See Figure 1
tpLH Propagation delay time, low-to-high-Ievel output
tpHL Propagation delay time. high-to-Iow-Ievel output
tpLH Propagation delay time, low-to-high-Ievel output
RL - 500,
tpHL Propagation delay time, high-to-Iow-Ievel output
CD
>
"iii
u
CD
a:
MIN
CL - 100 pF,
See Figure 1
TYP
MAX
12
12
20
20
20
35
15
25
UNIT
CD
>
";:
ns
o
CD
ns
c:
::::i
PARAMETER MEASUREMENT INFORMATION
3 V
~ Je-S5 ns
.i-='=""""~=~-I- - -
VCC
r---- L -,
INPUT
I
PULSE
GENERATOR r--T"_ _
tpLH
':' L - - - -
J- J
RL 50 0
I
..
!
I
I
3 V
1~1.;.0%;...._ _ 0 V
I
>-I-.....--~-OUTPUT
(see Note AI
-
I
I
CL
(See Note BI
':'
I
OUTPUT_ _ _. . J
TEST CIRCUIT
1.5 V
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zout
B. CL includes probe and jig capacitance.
=
500; tw
=
200 ns, duty cycle
=
50%.
FIGURE 1. SN75123 SWITCHING TIMES
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-155
SN75123
DUAL LINE DRIVER
TYPICAL CHARACTERISTICS
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
-300
Vee a 5 V
All inputs at 2 V
TA - 25°e
-250
0(
E
I
C
-200
'\
~::J
•
CJ
S
~
0
I
r-
'\.
-150
'\
-100
\
.9
5'
CD
-50
C
:::!,
o
o
<
CD
...
!II
\
2
4
3
5
VO-Output Voltage-V
l;
CD
FIGURE 2
n
CD
<'
CD
...
TYPICAL APPLICATION DATA
!II
r------,
A-,-&---r-.....
r-------,
B-,.--I
C ....r;;:;:::~.../
95 II COAXIAL CABLE
o
I
-+--t....-/
I
L ___ _'12~N:..5".!..3 .J
I
E--'--I"-'"
F
9511
9511
I
I A--#""_
I B--1._-'
L. ____ ~ ~N~~4.J
FIGURE 3. UNBALANCED LINE COMMUNICATION USING '123 AND '124
. 4-156
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
Y
5N75124
TRIPLE LINE RECEIVER
D1322, SEPTEMBER 1973-REVISED SEPTEMBER 1986
•
Meets IBM System 360 Input/Output
Interface Specifications
D, J, OR N PACKAGE
(TOP VIEW)
•
Operates from Single 5-V Supply
•
TTL Compatible
1A
16
2R
2S
2A
26
2Y
•
Built-In Input Threshold Hysteresis
•
High Speed , .. Typical Propagation Delay
Time - 20 ns
•
Independent Channel Strobes
•
Input Gating Increases Application Flexibility
•
Designed for Use with Dual Line Driver
SN75123
•
Designed to be Interchangeable with
Signetics N8T24
GND
Vee
IS
lR
lY
3A
3S
3R
3Y
logic symbol t
II
lR
IS
lA
description
lB
~
2R
>
'Q)
The SN75124 triple line receiver is specifically
designed to meet the input/output interface
specifications for IBM System 360. It is also
compatible with standard TTL logic and supply
voltage levels.
2S
2A
2B
The SN75124 has receiver inputs with built-in
hysteresis to provide increased noise margin for
single-ended systems. An open line will affect
the receiver input as would a low-level input
voltage and the receiver input can withstand a
level of -0.15 volt with power on or off. The
other inputs are in TTL configuration. The S input
must be high to enable the receiver input. Two
of the line receivers have A and B inputs that,
if both are high, will hold the output low. The
third receiver has only an A input that, if high,
will hold the output low.
3S
The SN7 5124 is characterized for operation from
ooe to 70 oe.
CD
U
CD
a:
-I I)
~
3R
CD
>
';:
3A
C
tThis symbol is in accordimc. with ANSI/IEEE Sid
lEe Publication 617-12.
91-1984
CD
and
logic diagram (positive logic)
lR
15 "':";":':""---Lo-../
lA -'-'------1r~
1 B ..:=::.....----L_./
2R
FUNCTION TABLE
INPUTS
OUTPUT
A
H
B*
R
S
V
H
X
X
X
X
X
X
L
H
H
L
L
X
X
L
L
L
L
H
H
H
H
X
X
L
H
X
X
L
2A
..:.:.'-----Ir,
2B ..:.:.'------IL...../
3R
3S ...:..;-'-----IL..-"
+8 input and last two lines of the
function table are applicable to
receivers 1 and 2 only.
3A
...:..;-'----i
Copyright © 1981. Texas Instruments Incorporated
PRODUCTION DATA documant. contain information
current as of publication date. Products conform to
specification.s per the terms of Texas Instruments
:~~-::!:~~i~8i~:I~~e ~:~::i:r lI,O:::~:~:-'~S not
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
c:
::i
4-157
SN75124
TRIPLE LINE RECEIVER
schematic (each receiver)
vcc _(1_6_1__--~--__- -__----_.--~----------~----------_.--~------------_,
4kll
TO OTHER
RECEIVERS
R (14.3. 101
80011
5811
(13.7.91 Y
•
S (15.4.111
....
\ :r
CD
o
(81
:::!.
<
til
GND - - - _ .....- -....- - .
(1.5.121
12.61 t
8 ------
A
CD
TO OTHER
RECEIVERS
~
CD
(')
CD
.2'
...
CD
til
w ...
Vee bus
t 8 input is provided on receivers 1 and 2 only.
Resistor value~ shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage: R input with VCC applied. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
R input with VCC not applied. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6 V
A, B, or S input ............................................... 5.5 V
Output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Output current ........................................................ ± 100 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
D package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 950 mW
J package ........................................................ 1025 mW
N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1150 mW
Operating free-air temperature range ...................................... ooC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............ 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package ........ 260°C
NOTES:
4-158
1. Voltage values are with respect to network ground terminal.
2. For operation above 25°e free·air temperature. refer to the Dissipation Derating Curves in Appendix A. In the J package.
SN75124 chips are glass mounted. For these devices in the N package. use the g.2-mW/oC curve .
. TEXAS'"
INSTRUMENTS
POST OFFice BOX 866012 • OALlA$. TeXAS 76265
SN15124
TRIPLE LINE RECEIVER
recommended operating conditions
Supply voltage, Vee
A, B, or S
High-level input voltage, VIH
MIN
NOM
4.75
5
R
O.B
R
0.7
output current, IOL
Operating free-air temperature, T A
electrical characteristics.
0
Vee
Vhys
PARAMETER
Hysteresis (VT + - VT _ )
R
VIK
Input clamp voltage
A,B, or S
Vee - 5 V,
Vee - 5 V,
A,B, or S
Vee
V(BR)!
o De to
4.75 V to 5.25 V. TA
voltage
=
5 V,
MIN Typt
0.2
0.4
TA - 25°e
12 mA
II II
=
BOO ~A,
VOH
VIH - VIH min, VIL - VIL max, IOH See Note 3
VOL
Low-level output voltage
VIH - VIH min, VIL - VIL max, 10L - 16 mA,
See Note 3
II
maximum input voltage
IIH
High-level input current
IlL
Low-level input current
lOS
Short-circuit output current*
lee
Supply current
mA
70
°e
MAX
VI - 6 V,
2.6
V
R
VI - 3.11 V
A,B, or S
VI - 0.4 V
Vee = 5V,
Vee - 5.25 V
5
40
170
TA
=
25°e
II
...
II)
CD
>
'iii
0.4
Vee - 0
VI - 4.5 V
V
V
5
A,B, or S
UNIT
V
5.5
VI - 7 V
R
~A
16
1.5
10 mA
High·level output voltage
Input current at
V
-800
70 De (unless otherwise noted)
TEST CONDITIONS
Input breakdown
V
V
1.7
High·level output current, 10H
low~level
5.25
2
A, B, or S
Low·level input voltage, VIL
MAX UNIT
CJ
V
CD
--...
a::
I I)
mA
CD
>
~A
-0.1
-1.6
mA
-50
-100
mA
72
mA
';:
c
CD
c
:::i
tTypical value is at Vee = 5 V, TA = 25°e.
t Not more than one output should be shorted at a time. and duration of the short-circuit should not exceed one second.
NOTE 3: The output voltage and current limits are guaranteed for any appropriate combination of high and low inputs specified by the
function table for the desired output.
switching characteristics.
Vee
= 5
V.
TA
PARAMETER
TEST CONDITIONS
tpLH Propagation delay time, low-to-high-Ievel output from R input
tpHL Propagation delay time, high-to-Iow-Ievel output from R input
See Figure 1
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
MIN
TYP
MAX
20
30
20
30
4-159
SN75124
TRIPLE LINE RECEIVER
PARAMETER MEASUREMENT INFORMATION
VCC
i+-'" 5ns
=,.,...__
2.6 V
:,.1
90%
84.50
~
14-'"
..,..,~I_+
90%
5ns
_____ 2.6 V
I
I
I
....
I
~tPLH
)OI.....--4~....-OUTPUT
I
CL _
5 kO
I
30pF
L '--
---1--.....J
(see Note 81
....
I ' 10%
I
I
1N3064
I
I
....
LVOL
NOTES: A. The pulse generator has the following characteristics: Zout
B. CL includes probe and jig capacitance.
~
50 0, PRR
s 5 MHz, duty cycle
FIGURE 1. SN75124 SWITCHING TIMES
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
RECEIVER INPUT VOLTAGE
4.0
VCC - 5 V
3.5 rNa load
TA - 25°C
3.0
III
g)
2.5
'5
2.0
~
;
o
VT-
VT+
1.5
I
~ . 1.0
0.5
o
o
0.20.40.60.8 1 1.21.41.61.8 2
VI-Input Voltage-V
FIGURE 2
4-160
'1~:~VOH
VOLTAGE WAVEFORMS
!
0 V
OUT_P_U_T_ _" " f . 5 V
TEST CIRCUIT
>I
I
I
tPHL~
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
= 50%.
SN75124
TRIPLE LINE RECEIVER
TYPICAL APPLICATION DATA
r-----.,
A --.....1--1-....
B-"""T""-I
C
r--------,
95-0 COAXIAL CABLE
o
E--w--r-,
I
F-+---L_o/
I
L ____ Y,_S~5~3.J
950
950
I
II
A -___
I
B---t,._,
y
L ____ .:: ':N~1:'4.J
-=FIGURE 3_ UNBALANCED LINE COMMUNICATION USING SN75123 AND SN75124
•
~
Q)
>
"iii
u
-.
Q)
a::
I II
Q)
>
";:
C
Q)
c
:::i
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-161
r-
:i"
CD
...c<"
CD
...
(I)
~
CD
(")
CD
<"
...
CD
(I)
4-162
SN75125. SN75127
SEVEN-CHANNEL LINE RECEIVERS
02239. JANUARY 1977-REVISEO SEPTEMBER 1986
•
Meets IBM 360/370 110 Specification
•
Input Resistance ..• 7 kO to 20 kO
•
Output Compatible with TTL
•
Schottky-Clamped Transistors
•
Operates from Single S-V Supply
•
High Speed ..• Low Propagation Delay
•
Ratio Specification for Propagation Delay
Time, Low-to-Hlgh/High-to-Low
•
Seven Channels in One 16-Pin Package
•
Standard VCC and Ground Positioning on
SN7S127
SN75125 ... D. J. OR N PACKAGE
(TOPVIEWI
lA
2A
3A
4A
5A
6A
7A
lY
Vee
3Y
4Y
5Y
6Y
7Y
2Y
GND
SN75127 ... 0, J. OR N PACKAGE
•
(TOP VIEW)
Vee
lA
2A
3A
4A
5A
6A
7A
description
The SN75125 and SN75127 are monolithic
seven-channel line receivers designed to satisfy
the requirements of the IBM System 360/370
input/output interface specifications. Special
low-power design and Schottky-clamped
transistors allow for low supply-current
requirements while maintaining fast switching
speeds and high-current TTL outputs.
lY
2Y
3Y
4Y
5Y
6Y
7Y
GND
...CD
U)
>
"i)
(,)
CD
-...
a:
U)
CD
>
"C
Q
The SN75125 and SN75127 are characterized
for operation from oDe to 70 De.
CD
c
::i
logic symbols t
SN75127
SN75125
lA
2A
3A
4A
5A
6A
7A
11)
(2)
t>
(3)
(4)
(5)
(6)
(7}
lY
2Y
3Y
4Y
5Y
6Y
7Y
rl)
lA
(2)
2A
(3)
3A
(4)
4A
(5)
5A
(6)
6A
(7)
7A
t>
lY
2Y
3Y
4Y
5Y
BY
7Y
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publicaiton 617-12.
PRODUCTION DATA d.culIOIIIs .antain infa...atia.
.. rrant ..., p.blloatla. data. Produ... ca.larm ta
_ifioatia., par tha term, a' TI. .I lnatrumlnta
=:~~·i:I~'li =:~; :.:o;::.:~":." .at
Copyright @ 1986: Texas Instruments Incorporated
TEXAS ."
INSTRUMENTS
POST OFFICE 80X 855012 • DALLAS. TEXAS 76265
4-163
SN7 5,125, .SN7 5127
SEVEN·CHANNEL LINE RECEIVERS
schematic (each receiver)
COMMON CIRCUITRY
V C c - - - f - - f ' - - - - - - - . - - - -......---~r_~_;_150 II
I
NOM
__- __-,___:.. CHANNELS
TO OTHER
I
I
I
I
I
A---4"""",,,__-I
INPUT
•
I
I
I
!::
::J
CD
C
:!.
<
iil
CD
::XI
12 kIl
NOM
I
I
I
GNO~.~-~~--~~-----+--~~--I~~~~~-~4__+
L-________________________~I~--------------+_~--_IoTOOTHER
L-______________________________________4-______________~~+_--.CHANNE~
CD
C')
L
CD
.
<'
CD
OU;PUT:
__ __
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
II)
Supply voltage. VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage range: SN75125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.15 V to 7 V
SN75127 .......................................... -2 V to 7 V
Continuous total dissipation at (or below) 25 DC free·air temperature (see Note'2):
o package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 950 r'nW
J package ..' ............................ '............................ '1025 mW
N package .............................................. : . . . . . . . . . .. 1150 mW
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 DC to 70 DC
Storage temperature range ......................................... - 65 DC to 150 DC
Lead temperature 1.6 mm (1/16 inch) from case for 60 seconds: J package ............ 300 DC
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds: 0 or N package ........ 260 DC
NOTES: 1. All voltage values are with respect to network ground terminal.
2. For operation above 25°C free·air tam perature. refer to the Dissipation Derating Curves in Appendix A. In the J package.
SN75125 and SN75127 chips are glass mounted. For these devices in the N package. use the 9.2-mW/oC curve.
4·164
TEXAS ,-If
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN75125, SN75127
SEVEN-CHANNEL LINE RECEIVERS
recommended operating conditions
MIN
NOM
MAX
Supply voltage, Vee
4.5
5
5.5
High-level input voltage, V,H
1.7
V
V
Low-level input voltage, V,L
0.7
High-level output current, 10H
-0.4
Low-level output current, 10L
16
0
Operating free-air temperature, T A
UNIT
70
V
V
mA
De
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
TEST CONOITIONS
VOH
PARAMETER
High-level output voltage
Vee - 4.5 V,
V,L - 0.7 V,
VOL
Low-level output voltage
Vee - 4.5 V,
V,H - 1.7 V,
"H
I,L
High-level input current
Vee = 5.5 V,
V, = 3.11 V
Low-level input current
Vee = 5.5 V,
V, = 0.15V
lOS
Short-circuit output curren(t
ri
Input resistance
Vee = 5.5 V,
Vo = 0
Vee - 4.5 V, 0 V, or open,
lee
"V, = 0.15 V to 4.15 V
Vee - 5.5 V,
'OH All inputs at 0.7 V
Supply current
0.4 mA
10H 10L - 16 mA
MIN
Typt
2.4
3.1
MAX
UNIT
V
0.4
0.5
V
0.3
0.42
mA
30
~A
-18
-60
mA
7
20
kO
15
25
mA
28
47
mA
-0.4 mA,
Vee = 5.5 V,
10L = 16 mA,
All inputs at 4 V
II)
~
(I)
>
-i
()
(I)
--a:
I I)
~
(I)
>
-;:
t All typical values are at Vee = 5 V, T A = 25 De.
~ Not more than one output should be shorted at a time.
Q
(I)
r:
switching characteristics. Vee" 5 V. TA - 25°e
PARAMETER
TEST CONDITIONS
tpLH Propagation delay time, low-to-high-Ievel output
tpHL Propagation delay time, high-to-Iow-Ievel output
tpLH
Ratio of propagation delay times
RL
tpHL
tTLH Transition time, low-to-high-Ievel output
tTHL Transition time, high-to-Iow-Ievel output
= 4000,
eL = 50 pF,
See Figure 1
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MIN
TYP
MAX
7
14
25
ns
10
18
30
ns
0.5
0.8
1.3
1
7
12
ns
1
3
12
ns
UNIT
::::i
4-165
SN75125. SN75127
SEVEN·CHANNEL LINE RECEIVERS
PARAMETER MEASUREMENT INFORMATION
VCC
TEST CIRCUIT
I
-+j
INPUT
!.
I t.--10ns
If
100 ns ---~.II
10ns~
.: O.a::
_ _ .....;1;.;;0..;;;'*'~_,
I
I
I
.
~:;~
-
-
-
-
10,*,
3V
ov
:'.
~:1f-2-v-----VOH
.
~
o.8v
-lI _____
-1 \.-
t-rHL
t-rLH
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zout = 50 0. PRR s 5 MHz.
B. CL includes probe and jig capacitance.
C. All diodes are 1N3064 or equivalent.
FIGURE 1
4·166
-
I
!'\;0.8V
-..l
-
I
1.7 V
I
OUTPUT
1'4--
'l!!o'-------9-0-'*'1[';ri -
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS, TEXAS 75265
VOL
SN75125. SN75127
SEVEN·CHANNEL LINE RECEIVERS
TYPICAL CHARACTERISTICS
VOLTAGE TRANSFER CHARACTERISTICS
5
r
VOLTAGE TRANSFER CHARACTERISTICS
5
TA • 70°C
Vee· 5 V
.111
4
Vee· 5.5 V
4
Vee. 4.5 V
>
>
I
I
=3
=3
CD
CD
II
is
TA • 25°e-
-
:s 2
CI.
:s
TA·ooe-
....
>...
...
0
II
is
....
>
:s
CI. 2
:s
I
0
>
I
>
.1,
Vee· 5 V
No Load
I
0
o
I
I.
o
2
2
CD
/
>
I
f
/V
I
c
is
/
~
>
.;:
c
CD
c
:::i
0.4
o
0.3
]
/
/
o
CD
Vee .15 V
_VI·
5 V
0.5
TA • 25°C
>
15
/
:s 0.2
(.)
/
I II
LOW-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
E
0
-.
VI-Input Voltage-V
/
..
0.1
()
a::
0.6
ee I. ~ V
r- No Load
TA • 25°C
5CI.
'ii)
FIGURE 3
J
.5
CD
>
o
INPUT CURRENT
vs
INPUT VOLTAGE
III: 0.3
III
j
FIGURE 2
0.4
.
No Load
TA·25oe
VI-Input Voltage-V
I
•
0
I
0
/
~
0.2
.3
~
o
>
0.1
o
2
4
3
5
/
o
",...,
5
~
~
10
~
15
20
10 - Output Current - mA
VI-Input Voltage-V
FIGURE 5
FIGURE 4
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-167
SN75125. SN75127
SEVEN·CHANNEL LINE RECEIVERS
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
-ii)
u
-..
CD
a:
I II
CD
>
logic symbols t
-0:::
C
SN75129
SN75128
CD
C
::;
1S
28
2S
lA
lY
lA
2A
2Y
2A
2Y
3A
3Y
4Y
3A
4A
4A
lY
5A
5Y
5A
5Y
6A
7A
6Y
6A
6Y
7Y
SA
SY
7A
SA
7Y
SY
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Pu'blication 617-12.
PRODUCTION DATA d......nts •••tai.l.lonnati••
cu.nnt I. of pubU••tl•• dlta. Pr.ducta ...for .. to
spacifi.ati••• por tho IorIIs .1 T._ I.st......ts
::=~;ai~:I:ri =::~; lI~o:=::1::~ not
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-169
SN75128, SN75129
EIGHT·CHANNEL LINE RECEIVERS
logic diagrams (positive logic)
SN75128
SN75129
•
r-
~.
C
:::!.
<
CD
Ul
:D
CD
~
schematic (each driver)
<.
CD
Ul
IN~T~~r--·-_-·-_--·~_N.~_--.-_--.-_-.-_--.-_--.-_-.-_--.-_+-,~.~~~~~
12 kll
NOM
iv
i
!
I
I
I
I
I
i
j
I
TO THREE
OTHER
CHANNELS
4-170
\'"----V~---....I/
TO SevEN
OTHER CHANNELS
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76285
SN75128. SN75129
EIGHT-CHANNEL LINE RECEIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
A input voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.15 V to 7 V
Strobe input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Continuous total dissipation at (or below) 25 DC free-air temperature (see Note 2):
OW package ........................................................ 1125 mW
J package .......................................................... 1025 mW
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11 50 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 DC to 70 DC
Storage temperature range ......................................... - 65 DC to 150 DC
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: OW or N package. . . . . .. 260 DC
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............ 300 DC
NOTES: 1. All voltage values are with respect to network ground terminal.
2. For operation above 25·C free-air temperature, refer to the Dissipation Derating Curves in Appendix A. In the J package,
SN75128 amd SN75129 chips are glass mounted. For these devices in the N package, use the 9.2-mW/De curve.
recommended operating conditions
/I)
MIN
4.5
Supply voltage, Vec
High·level input voltage, VIH
A
1.7
S
2
I\IOM
5
0.7
S
0.7
High-level output current, 10H
Low~level output current, IOl
Operating free-air temperature, T A
as
>
"a)
MAX UNIT
5.5
V
(,)
V
A
low-level input voltage, Vil
a
0
V
-0.4
rnA
16
rnA
De
70
-.
CD
a::
/ I)
CD
>
"0:::
C
CD
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
VOH
PARAMETER
High-level output voltage
Val
low-level· output voltage
VIK
Input clamp voltage
S
Vce - 4.5 V,
II
IIH
High-level i~put current
A
Vec - 5.5 V,
VI - 3.11 V
S
Vec
III
Low-level input current
A
S
Vec - 5.5 V,
lOS
ri
Short-circuit output current
lee
*
Input resistance
Supply current
MIN TYpt
TEST CONDITIONS
Vee
Vec
Vee
Vec
= 4.5
= 4.5
=
=
=
V,
V,
5.5 V,
5.6
v,
VIi.. = 0.7 V,
VIH - 1.7 V.
=
SN75129
Vee - 5.5 V,
SN75128
Vee
SN75129
Vec
=
=
2.4
MAX
3.1
0.4
-18 mA
0.3
V
0.5
V
-1.5
V
0.42
mA
20
p.A
30
p.A
-0.4
-60
mA
20
kD
VI
= 0.4
=0
V
-18
aVI - 0.15Vt04.15V
All A inputs at 0.7 V
7
19
:::::i
UNIT
VI - 0.15 V
Vec - 4.5 V, 0 V, or open;
Strobe at 2.4 V,
Vee - 5.5 V,
= -0.4 rnA
= 16 rnA
VI - 2.7 V
5.5 V, Va
SN75128
IOH
10l
mA
31
Strobe at 0.4 V,
All A inputs at 0.7 V
19
31
5.5 V,
Strobe at 2.4 V,
All A inputs at 4 V
32
"53
5.5 V,
Strobe at 0.4 V,
All A inputs at 4 V
32
53
mA
t All typical values are at Vee = 5 V, TA = 25 De.
t Not more than one output should be shorted at a time.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 15286
c
4-171
SN75128, SN75129
EIGHT-CHANNEL LINE RECEIVERS
switching characteristics.
",
vee,.; 5 V.
PARAMETER
FROM
tPLH Propagation delay time, low-to-high-Ievel output
tpHL Propagation delay ti~e, high-to-Iow-Ievel output
tpLH Propagation delay time, low-to-high-Ievel output
tPHL Propagation delay time, high-to-Iow-Ievel output
tpLH
Ratio of propagation delay times
tPHL
Transition
time, low-to-high-Ievel output
tTLH
ITHL Transition time, high-to-Iow-Ievel output
:i"
OUTPUT
CD
o
l:i
CD
MIN
7
10
A
S
A
RL = 40011,
CL = 50 pF,
See Figure 1
TYP MAX
14
25
18
30
26
22
40
35
0.5
0.8
1.3
1
1
7
3
12
12
SN75129
MIN TYP MAX
7
10
14
18
25
20
16
30
35
30
0.5
0.8
1.3
1
1
7
12
12
3
UNIT
ns
ns
ns
ns
ns
ns
INPUT
ISee Notes V ren
A, D, and EI
VCC
:!:----OV
40011
:::I.
~
SN75128
TEST CONDITIONS
PARAMETER MEASUREMENT INFORMATION
III...
Ci'l
25°e
TA -
FROMOUTPUT_~__~~~-4~"~"~I+-,
2 V
2V
UNDER TEST
OUTPUT
n
CD
I
I
I
.
:c::-
i
CD
0.8V
4--tTHL
til
I
-;---VOL
tTLH ..........
VOLTAGE WAVEFORMS
Input pulses are supplied by a generator having the following characteristics: Zo = 50 11, PRR s 5 MHz.
Includes probe and jig capacitance.
All diodes are 1N3064 or equivalent.
The strobe inputs of SN75129 are in-phase with the output.
V re fl = 0.7 V and V re f2 = 1.7 V for testing data IAI inputs, V re fl = V re f2 = 1.3 V for strobe inputs.
FIGURE 1
4-172
0.8 V
.
" LOAD CIRCUIT
NOTES: A.
B.
C.
D.
E.
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
VOH
I
I
I
I
I
SN75128, SN75129
EIGHT-CHANNEL LINE RECEIVERS
TYPICAL CHARACTERISTICS
VOLTAGE TRANSFER CHARACTERISTICS
FROM A INPUTS
VOLT AGE TRANSFER CHARACTERISTICS
5
I
5
I
I
VCC - 5.5 V
TA - 70 oC-
VCC - 5 V
4
4
>
>
.....
......
I
I
.t:
3
0
ii
!:i
!:ia.
I I
2
3
>
TA - 25°C -
>
;
0
VCC - 4.5 V
=
0
a
2
I
I
0
0
TA - O°C_ -00
>
>
.l
I
VCC = 5 V
No Load
o
en
No Load
~
CD
TA - 25°C
o
o
2
I
I
I
o
2
VI-Input Voltage-V
to)
CD
a:
--
VI-Input Voltage-V
FIGURE 2
>
-iii
en
FIGURE 3
~
CD
0.4
V~C ~ 5~
c(
E
0.3 t-
/
TA - 25°C
~
:s
!:ia.
/
>
..
V
I
;= 0.3
0
iii
>
....
...~I
...
0
/
0.1
V
/
/
~
/
0.1
>
/
o
0.2
0
/
o
~
0
/
c
1.
c::
::i
>
/
0.2
CD
~
VCC V
0.5 I- VI - 5 V
TA - 25°C
E 0.4
/V
I
E
U
0.6
/
r- No Load
>
';:
o
LOW-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
INPUT CURRENT
vs
INPUT VOLTAGE
o
2
4
3
5
o
VI-Input Voltage-V
5
10
15
20
IO-Output Current-rnA
FIGURE 5
FIGURE 4
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
4-173
III
r-
:r
CD
o
..;:;-
CD
Ul
:x:I
CD
(')
CD
..<'
CD
en
4-174
SN75136
QUADRUPLE BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
02291 JANUARY 1977-REVISEO SEPTEMBER 1986
•
D. J. OR N PACKAGE
P-N-P Inputs for Minimal Input Loading
(200 p.A Maximum)
•
High-Speed Schottky Circuitry
•
3-State Outputs for Driver and Receiver
•
Party-Line (Data-Bus) Operation
•
Single S-V Supply
•
Driver has 4O-mA Current Sink Capability
•
Designed to be Functionally Interchangeable
with Signetics NBT26. also Called 8T26
ITOPVIEWI
RE
Vee
1R
18
DE
4R
10
48
2R
28
2D
GNO y:;~--,~
40
3R
38
3D
logic symbol t
•
description
The SN75136 is a quadruple transceiver utilizing
Schottky-diode-clamped transistors. Both the
driver and receiver have three-state outputs.
With p-n-p inputs. the input loading is
reduced to a maximum input current of
200 microamperes.
131 18
...enCD
.~
161 28
The SN75136 is characterized for operation from
ooe to 70 oe.
CD
U
CD
-...
1101 38
a::
en
1131 48
CD
FUNCTION TABLE IDRIVERI
INPUT
>
.~
OUTPUT
D
DE
B
L
H
H
H
H
L
X
L
Z
tThis symbol is in accordance with ANSI/IEEE SId 91-1984 and
lEe Publication 617-12.
C
logic diagram (positive logic)
~
FUNCTION TABLE IRECEIVERI
INPUT
OUTPUT
B
RE
R
L
L
H
H
L
L
X
H
Z
H = high level
L = low level
X :;:::: irrelevant
Z = high impedance
121
131
151
16)
3B
prDellSing
includo tasting of all pa ..mota...
4R
4B
Copyright © 1986, Texas Instruments Incorporated
PRODUCTION DATA d.cumants •• nlain
0'Production
Texas Instruments standard warrantr.'
dOl. not necessHri y
2R
2B
3R
3D
13)
information Cllrrent 8. of pllblication data.
Products confurm tel specifications par the tarms
lR
18
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-175
CD
C
SN75136
QUADRUPLE BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
VCC------~--------
VCC
5kllNOM
INPUT
OUTPUT
•
Drivers:
Receivers:
r-
:r
GI
.
..
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
D package ......................................................... 950 mW
J package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11 50 mW
Operating free-air temperature range ............................. , . . . . . . .. ooC to 70°C
Storage temperature range .......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............. 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package. . . . . . . .. 260°C
C
:c"
GI
UI
::a
GI
n
GI
.
:c"
GI
UI
NOTES:
1. Voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the N package, use
the 9.2-mW/oe curve for these devices. In the J package, SN75136 chips are glass mounted. and use the 8.25 mW/oe curve.
recommended operating conditions
Supply voltage. Vee
High-level input voltage. VIH
Low-level input voltage, Vil
High-level output current, IOH
Low-level output current, 10 L
B. D. DE. RE
B, D. DE. RE
NOM
MAX
UNIT
5
5.25
V
2
V
0.85
-10
Driver, B
Receiver, R
-2
Driver, 8
40
Receiver, R
16
Operating free-air temperature, T A
4-176
MIN
4.75
0
TEXAS •
INSTRUMENTS
POST OFFICE BOX 65~12 • DALI.,AS, TeXAS 75265
70
V
mA
rnA
°e
SN75136
QUADRUPLE BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature and supply voltage range
(unless otherwise noted)
PARAMETER
V,K
B,D,DE,RE
10Z
"H
I,L
-1
B
V,L
R
V,L - 0.B5 V,
10H -
B
V,H - 2 V,
R
V,H
'OL - 40 mA
V,L = 0.85 V, 10L
Off-state (high-impedance
B,R
OE at 0.B5 V,
RE at 2 V,
state) output current
R
RE at 2 V,
Vo
D,DE,RE
V,
Low-level output voltage
High-level
i~put
current
Low·level· input current
lOS
Short-circuit output current:!:
ICC
Supply current
switching characteristics.
MAX
"=
-5 rnA
V,H = 2 V,
VOH High-level output voltage
VOL
MIN Typt
TEST CONOITIONS
Input clamp voltage
=
=
=
2 V,
= 0.85
=
V, 10H
=
-10 mA
-2 mA
Vo
3.1
2.6
3.1
0.5
0.5
100
5.25 V,
V
~A
-100
0.5 V
5.25 V
=
V
V
= 16 mA
= 2.6 V
25
B,D,DE,RE V,
0.4 V
B
VCC = 5.25 V
R
VCC
2.6
UNIT
-200
-50
-150
-30
-75
No load
87
~A
~A
a
mA
mA
Vee
PARAMETER
FROM
TO
TEST CONDITIONS
tpLH Propagation delay time, low-to-high-Ievef output
tpHL Propagation delay time. high-to-Iow-Ievel output
B
R
CL
=
30 pF, See Figure 1
tpLH Propagation delay time, low-to-high-Ievel output
tpHL Propagation delay time, high-to-Iow-Ievel output
D
B
CL
=
300 pF,See Figure 2
fiE
R
CL
=
30 pF, See Figure 3
DE
B
CL
=
300 pF, See Figure 4
tpLZ
Output disable time from low level
tpZL
Output enable time to low level
tpLZ Output disable time from low level
tpZL Output enable time to low level
MIN
TYP
MAX
8
18
7
14
11
20
16
24
16
24
15
30
9
24
31
38
UNIT
ns
~
CD
>
'G)
(,)
ns
-
ns
C
CD
ns
a:
~
CD
>
'i:
CD
tAli typical values are at TA = 25°C and VCC = 5 V.
+Only one output s,hould be shorted to ground at a time, and duration of the short circuit should not exceed one second.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
c:
:::::i
4-177
SN7.5136
QUADRUPLE BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
2.6 V
VCC
TEST
POINT
CIRCUIT
UNDER
TEST
(see Note BI
92 Il
(_NoteOJ
R
o (all)
CL
1.3 kll
OPEN
~
30 pF
(see NoteCI
GND
TEST CIRCUIT
III
--tt ,.. <6 n.
,
!
t:
:
~tPHL
::::I
..
.
CD
C
OUTPUT
~-
__ 2.6 V
~..:=-n~
90%~
1.5V I
INPUTJ'90%
I 1.5V
10%
10%
OV
tPLH~
. V-
----\l.
~
VOH
...
1._5_V_ _ _ _ _ _ _ _ _
15-JV;r
-VOL
VOLTAGE WAVEFORMS
UI
FIGURE 1. PROPAGATION DELAY TIMES FROM BUS TO RECEIVER OUTPUT
3:i
~
-Gi
: /
Co)
G)
____"'1,0%
IX:
IG)!!
VOLTAGE WAVEFORMS
>
-;:
Q
FIGURE 3. RECEIVER ENABLE AND DISABLE TIMES
Vee
2.6V
5V
G)
D (all)
ire
DE
c::
::;
TEST
POINT
CIRCUIT
UNDER
TEST
(see Note B)
B
R (alii
OPEN
(_NoteD)
GND
TEST CIRCUIT
INPUT
:~1..;;0%;.;.._ __
:
_ _ _....;I.~tI
OUTPUT
tpZL
\.5V
10%Y
~ tpLZ
VOLTAGE WAVEFORMS
FIGURE 4. DRIVER ENABLE AND DISABLE TIMES
NOTES:
A. The pulse generator in Figures 3 and 4 has the fallowing characteristics: PRR
B. All inputs and outputs not shown are open.
C. CL includes probe and jig capacitance.
D. All diodes are lN916 or lN3064.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
s
5 MHz, duty cycle = 50%, Zout '" 50 O.
4-179
•
rs·
·CD
.
C
~.
C;;
:a
CD
n
CD
~.
C;;
4·180
SN55138, SN75138
QUADRUPLE BUS TRANSCEIVERS
01663. SEPTEMBER 1973-REVISEO SEPTEMBER 1986
•
•
•
•
•
•
•
•
SN55138 ... J PACKAGE
SN75138 ... D. J. OR N PACKAGE
(TOP VIEW)
Single 5-V Supply
High-Input-Impedance. High-Threshold
Receivers
Vee
GNO
Common Driver Strobe
4B
4R
40
S
3D
3R
3B
1B
1R
10
20
2R
2B
TTL-Compatible Driver and Strobe Inputs
with Clamp Diodes
High-Speed Operation
100-mA Open-Collector Driver Outputs
GNO
Four Independent Channels
SN55138 ... FK PACKAGE
(TOP VIEW)
TTL-Compatible Receiver Output
•
o
U
m Z U Um
description
~(!)Z>
'G)
u
CD
a:
f!
CD
>
'0:::
9 1011 1213
mouma:
NZZMM
(!)
C
NC - No internal connection
CD
c:
FUNCTION TA8LE
(TRANSMITTING)
INPUTS
H
OUTPUTS
FUNCTION TA8LE
(RECEIVING)
INPUTS
OUTPUT
S
0
B
R
S B 0
R
L
H
L
H
L
L
H
L
H H X
H L X
L
H
=
high level. L
=
low level. X
::i
= irrelevant
logic symbol t
The SN55138 is characterized for operation over
the full military temperature range of - 55 DC to
125 DC; the SN75138 is characterized for
operation from O°C to 70 oC.
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for D. J. and N packages.
PRODUCTION DATA d........ts ••ntai. i.formllio.
• urrellt as of publicatio. dille. Products co.form to
.p••ificlllo.1 par lb. tarm. of T.xas Instruments
:':=~~i~·[.':I':.'1oi =:~:I' :'l:=~
..
t
Copyright @ 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-181
SN55138, SN75138
QUADRUPLE BUS TRANSCEIVERS
logic diagram (positive logic)
s
(12)
(2) 18
10 (4)
1R (3)
In 28
(5)
20~--------~~-L
__~
2R IS)
•
(9) 38
(11)
3D
------------+----tL......-.J
(10)
3R~~--------~----~
r5'
(15) 48
(13)
40~~-----------L
__~
(14)
4R~~--------------~C
CD
...
~'
Pin numbers showns are for D. J, and N packages.
til
schematics of inputs and outputs
C
~
n
CD
~'
EQUIVALENT OF EACH
STROBE AND DRIVER INPUT
VCC - - - - . . - - -
til
INPUT
EQUIVALENT OF
EACH RECEIVER INPUT
TYPICAL OF ALL
DRIVER OUTPUTS
vocz~~
,~"'
---q-
1~
TYPICAL OF ALL
RECEIVER OUTPUTS
---__.:::
C
CD
V
c
::::l
~A
mA
·C
4-183
SN55138, SN75138
QUADRUPLE BUS TRANSCEIVERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
VIK
Input clamp
voltage
High-level
VOH
output voltage
Driver or strobe
Receiver
•
r-
:r
CD
c...
VIL(S) = 0.8 V,
IOL = 100 mA
output voltage
Vee - MIN,
VIH(R) - VIH min,
VIH(S) = 2 V,
IOL = 16 mA
Driver or strobe
Vee = MAX,
VI = Vee
Driver or strobe
Vee = MAX,
VI = 2.4 V
Vee = 5 V,
VIIR) = 4.5 V,
High-level
IIH
input current
Low-level
IlL
input current
Input current
with power off
Short-circuit
lOS
output current §
CD
...
VIH(S) - 2 V,
VIL(R) = VIL max, IOH = -4OOI'A
LOW-level
C')
<'
CD
Vee - MIN,
Receiver
MIN TYP'
-1.5
2.4
3.5
MAX
-1.5
2.4
3.5
UNIT
V
V
0.45
0.45
0.4
0.4
1
1
40
40
V
rnA
voltage
...
CD
II = -12 mA
SN75138
MAX
Input current at
UI
:xl
Vee = MIN,
VIH(D) = 2 V,
maximum input
II
<'
CD
-
MIN TYP*
Vee MIN,
Driver
VOL
SN55138
TEST CONDITIONSt
PARAMETER
lee
Supply current
UI
Receiver
Driver or strobe
Receiver
VI - 0.4 V
Vee = MAX,
VIIR) = 0.45 V,
VI = 4.5 V
Receiver
Vee = MAX,
All driver
Vee = MAX,
outputs low
VI(S) = 0.8 V
1.1
-20
25
1.6
1
1.5
-55
VI(D) = 2 V,
Vee - MAX,
300
-50
VI(S) = 2 V
Vee = 0,
All driver
1
Vee - MAX,
Receiver
outputs high
25
VIIS) = 2 V
1.1
-18
300
I'A
1.6
rnA
-50
I'A
1.5
rnA
-55
mA
50
65
50
65
42
55
42
55
mA
VI(R) - 3.5 V,
VI(S) = 2 V,
Receiver outputs open
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. Parenthetical letters
0, R, and S used with VI refer -to the driver input, receiver input, and strobe input, respectively.
tAli typical values are at Vee = 5 V, TA = 25°e.
§Not more than one output should be shorted at a time.
switching characteristics. Vee = 5 V. TA
PARAMETERt
tpLH
tpHL
tpLH
tpHL
tpLH
tPHL
FROM
(INPUT)
25°e
TO
(OUTPUT)
Driver
Driver
Strobe
Driver
Receiver
=
Receiver
TEST CONDITIONS
eL
=
50 pF,
RL
50 II,
See Figure 1
eL - 15 pF,
See Figure 2
RL - 400 II,
ttPLH " propagation delay time, low-to-high-Ievel output
tpHL ;. propagation delay time, high-to-Iow-Ievel output
4-184
=
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
MIN
TYP
MAX
15
24
14
24
18
28
22
32
7
15
8
15
UNIT
ns
ns
ns
SN55138, SN15138
QUADRUPLE BUS TRANSCEIVERS
PARAMETER MEASUREMENT INFORMATION
TEST
POINT
Vcc
FROM OUTPUT
UNDER TEST
~
~ POINT
T-=
DRIVER
INPUT
(S•• Not. 01
STROBE
INPUT
Rl
TEST
Cl
(Sea Note BI
-X' --
,-,\X,...---3V
. 1.5 V
\ 1.5 V
, I '-_ _ _ _ _-' ,\
-...I I
~ --OV
,..
VCC
.1
tplH
I
:-\ .
~:~~VER
r----
4V
i''\.2_.5_V_ _ _ _--'t2.5 V _ _ 0 V
1- tPlH
....
' ..1-----....
1-----....1- tpH l
14'
..
DRIVER
OUTPUT
___...Jf...
~:=
1
RECEIVER_ _ _ _..1
OUTPUT
"
v,.5
•
fI)
"-
V
CD
>
"ii)
U
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
CD
IX:
~
FIGURE 2. PROPAGATION DELAY TIMES
FROM RECEIVER INPUT
FIGURE 1. PROPAGATION DELAY TIMES
FROM DATA AND STROBE INPUTS
NOTES: A. Input pulses are supplied by generators having the following characteristics: tw
=:
100 ns, PRR
::s: 1 MHz, tr ::s: 10 ns, tf
"-
CD
:S 10 ns,
Zout ~50 o.
B. CL includes probe and jig capacitance.
C. All diodes are 1N916 or 1N3064.
"~
C
CD
D. When testing driver input (solid line) strobe must be low; when testing strobe input (dashed line) driver input must be high.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
c:
::::i
4-185
S155138, S175138
QUADRUPLE BUS TRANSCEIVERS
TYPICAL CHARACTERISTICS t
STROBE·TO·OI=lIVER OUTPUT
DRIVER TRANSFER CHARACTERISTICS
DRIVER TRANSFER CHARACTERISTICS
8
VCC- 6V
vIlSI-a.BV
•
•
Lj' Bon •• Vee
TA -
3
ale
Tl.~·c
TA·126°C
2
~
0
't
;
J•
CD
~
CD
n
<'
CD
...
VJ'BV
VIIDI'2V
o
FIGURE 4
~'D
400n
R
10 kG
L
All
.~
~
'\ ~~:;
VUDI-2V
2
TA''''C
Load .. 50 n to Vee
1
'0
1
vcc-.1v
VCC- 6.BV
o
o
o
VI(SI-Stroba Input Voltage-V
~
I
f vJ .•.•IV
I
VCC- 6V .
VCC- 4.6V
!
2
~
,
I
g
o
All
""'~~=:
l
VItRI-Receiver Input Voltage-V
FIGURE 8
HIGH· LEVEL OUTPUT VOlTAGE
"
~
o
..
HIGH·lEVEl OUTPUT VOLTAGE
R
'0 kG
1
FIGURE 7
OUTPUT CURRENT (RECEIVER)
~u
400n
•
VIIRI-Reoaiur Input Voitaga-V
FIGURE 6
.V
TA-moe
>I
j
T 26j,C"\ -\ \T-j'"
'j"j'"
RECEIVER TRANSFER CHARACTERISTICS
.V
vcc- sv
VCC- 4.6V
>
FIGURE 5
RECEIVER TRANSFER CHARACTERISTICS
8
VCC-S V
'?
LoMI- &00 to Vee
o
VUDI-Or'vt, Input VoIbgI-V
Vcc- S•6V
t
TiC
1
STROBE·TO·DRIVER OUTPUT
TRANSFER CHARACTERISTICS
C
.112tr~
TAI._.~c
FIGURE 3
CD
UI
TA
VUDI-Dri¥t' Input Volu.g.--V
...:c.!'
I
VCC- 4•6V
00
r5'
CD
rL
VIIS)-O.av
TA-2&°C
Loed -600 to Vee
Vee- 6V
~e
1
•
Vcc- 6.5V
TRANSFER CHARACTERISTICS
LOW·LEVEL OUTPUT VOLTAGE
"
OUTPUT CURRENT (RECEIVER)
OUTPUT CURRENT (RECEIVER)
1.2
1·
>
i
o
1
~TA'2&'C
3
]
"
...... ".'\.
I~
TA'-56'",-
t
o
o
,
"
,5.,
I~
~
•
w m
~
~
~
~
IOH(RI-Htgh·Level Output Cul1'8nt-mA
FIGURE 9
toata for temperatures beiDw
4-186
VICR)-O.8V
TA·
...C
VCC"'6V
VIIR)-O.8V
1
:--"TA-'2&'C
~
o
o
"'\.r\.
'\.r\. VCC-6V
r\. .'\.1
Vcc-4.6V ,'\.1\
1
'\.'1\. \l
10 15 20 26 30 35 40
IOHIRI-High·Level Output Current-mA
TA"!ss°C
t
1.0
J
0.8
]
0••
I
VCC" 6.6V
.'~~
II:
:i 0.2
o
ooe and above 70'e is applicable tD SN56138 circuits only.
~,
INSTRUMENTS'
POST DFFICE BOX 65&012 ' DALLAS, TEXAS 75266
,/
~/
{D.4
~
Tl'26,J
~
~
r
VCC-4.6V
VUR,-3.6V
0102030405080
IOLIRI-low·Level Output Currnet-mA
FIGURE 11
FIGURE 10
TEXAS
't
SN55138. SI75138
QUADRUPLE BUS TRANSCEIVERS
TYPICAL CHARACTERISTICSt
LOW-lEVEL OUTPUT VOLTAGE
RECEIVER INPUT CURRENT
"
RECEIVER INPUT VOLTAGE
1.2
't
1".
VICS'- 0.8
. I/r~-
ju
1••
u
Vcc- 4.5V
VlfD)"'2V
1Q
VI
"
~
~
TA--56 C
! •.•
~~
$
~
•o
11.2
.L
I
Q
100
TA" -6S"C
1.•
150
.,
26"'C
200
250
d
~
TA .. 25"C, -61i"C
••
IOLIDI-Low-LIIVtI Output Current-mA
1.4
/
I 1.2
1.•
/
.. . ..':'f> >1> ..
0.6
0.4
30D
VICSI-2V
TA-26°C
! ...
t•
E 0.2
0.2
50
VUS,-2V
"
RECEIVER INPUT VOLTAGE
•
1.
! ...
I ...
11
A
~
.3
TIA"'~
I
.
Vee-sv
1.'
d
1i 0 .•
RECEIVER INPUT CURRENT
"
OUTPUT CURRENT (DRIVER OUTPUT)
')
TA -126"C
~
-:8t-~ ~-
0.4
>
0.2
••
II
VI(RI-RllCliller Input VoI..ge-V
FIGURE 12
FIGURE 14
FIGURE 13
f!
Q)
SUPPLY CURRENT
"
SUPPLY VOLTAGE
(ALL DRIVER OUTPUTS LOW)
••
SUPPLY CURRENT
PROPAGATION DELAY TIMES
SUPPLYVQLTAGE
FREE-AIR TEMPERATURE
8O,---:-----,-"T""---.--,
VIISI- a.BV
7. Ori.., '0IIII... 1itDjV
32
VI(DI-2V
\ TA-aoe
28
.#
~0
.a
••
~
A 0 125°C
-80 -40 -20 0
DRIVER PROPAGATION DELAY TIMES
LOAD CAPACITANCE
, ,
",~,,(s-D\
tpLHI~DI -
;:
IPLHID-D)
t
;!i
tPHLI~-D)
g
TTl
FIGURE 18
tOata for temperatures below
i--";';;.~\D.o\
..- ..- I,.
;..~r.ol
J•
1
-
6.1 5.2 6.3 6.4 5.5
VCC-Supplv Voltage-V
.11
....- ..I..-
L.I.v
n.
•o
80 100 120 140
RECEIVER PROPAGATION DELAY TIMES
"
!I ~ ..- I- ~_
26
tpHLIS·D)
I I I
FIGURE 17
"
•
eo
Q)
TA-FI1HI-Air Temperature-°c
FIGURE 16
Driwr load: CL" 50 pF, RL" 50 n, See Figure 1
RlCtiVer load: CL "15pF, RL 400 n. 8ft Figure 2
20 40
>
0t:
C
RL" 60
S.. Figure 1
TA-26°C
20 40 80 80 100 120 140 160 180 200
CL -Lnd C.pacltlnce-pf
FIGURE 19
.
,.
,
f
"
LOAD CAPACITANCE
VCC-SV
RL .. 400
TA - 25°C
n. S.. Figura 2
J ,•
! .
j
if
~
12
6 ~
~ r-
....-:: ~ ~"\",,,\
l •
••
ro
~
30
..
80
00
M
80
CL -Load C8pac:itance-pF
FIGURE 20
ooe and above 70°C is applicable to SN55138 circuits only.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX·655012 • DALLAS. TEXAS 75265
c
:::::i
I ""tLI"i"\
VCC-SuppIVVoItage-V
PROPAGATION DELAY TIMES
5
~~~
•
•
Vcc-SupplvVoIUgl-V
4.5 4 .• 4.7 4.• 4.9
~\lID~tPHL(D-Dl
.-
I
tflHL(R·RI
•
a:
1
",~,,\s-I1\
2
~ ~~+--r~--~+--r-+~
VI I
~
TA"25°C
Fi~re
en
•
f 3Of-+~~~~~4-~--4-~
SUPPL Y VOLTAGE
.
•
i:f-+-f-+---'
FIGURE 15
30
Co)
Q)
:--".""'\ii -.
Vcc" SV
Driver load: CL - 60 pF. RL -50 n,See
Q)
./
, /T~O-55°C
,.
>
0Qi
4-187
SN55138. SN75138
QUADRUPLE BUS TRANSCEIVERS
TYPICAL APPLICATION DATA
5V
5V
P
loon
r--j
@I>--'-,---+@
I
I
50 ft Belden #8795
100·n Telephone Cable
L2/4 SN5513!J
- \_ _ _ OV
- - - - - - --OV
@=]:-A-F::
r5'
CD
...C
<'
...CDtil
TYPICAL VOLTAGE WAVEFORMS
FIGURE 21. POINT-TO-POINT COMMUNICATION OVER 50 FEET OF TWISTED PAIR AT 5 MHz
-:::D
5V
5V
CD
C')
CD
<'
CD
...
til
100 n
100 n
>-;-....-®
®
@
or equivalent
-==;:--4V
2V
OV
2V
OV
TYPICAL VOLTAGE WAVEFORMS
FIGURE 22. PARTY-LINE COMMUNICATION ON 500 FEET OF TWISTED PAIR AT 1 MHz
4-188
TEXAS •
INSTRUMENTS
POST OFFICE BOX'655012 • DALLAS, TEXAS 75265
SN55138, SN75138
QUADRUPLE BUS TRANSCEIVERS
TYPICAL APPLICATION DATA
5V
1000 ft RG-53
or
I
~uival8nt
©I
'>-...:...,-.-@
l2'~5513~
@~
==t___
-=--""'-----t -
t
-::@I =t=i =~::
@
==:: •
- - - - - - - - - - - - - - - - - - ov
-5V
4V
-==:: @t-
~
I -
~-3V
\- I
TYPICAL VOLTAGE WAVEFORMS
FIGURE 23. POINT-TO-POINT COMMUNICATION OVER 1000 FEET OF COAX AT 1 MHz
...
III
CD
>
'a;
CJ
CD
a:
-...
...
III
CD
>
';:
o
CD
c
:::::i
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
4-189
!::
i
c:::!!,
<
til
CD
~
n
CD
<'
CD
til
4-190
SN75140, SN75141
DUAL LINE RECEIVERS
02155, JANUARY 1977-REVISEO OCTOBER 1986
•
•
•
•
•
•
•
•
Single 5-V Supply
0, JG. DR P PACKAGE
ITOPVIEW)
± 100 mV Sensitivity
For Application As:
Single-Ended Line Receiver
Gated Oscillator
Level Comparator
10UT[]8
eOMSTRB 2
7
1 LINE
3
6
GND 4
5
Adjustable Reference Voltage
Vee
20UT
eOMREF
2L1NE
logic symbol t
.r----.,
TTL Outputs
COMSTRB !.:12~)_ _
TTL-Compatible Strobe
Designed for Party-Line
(Data-Bus) Applications
II
Common Reference Pin
•
Common Strobe
•
'141 Has Diode-Protected
Input Stage for Power-Off
Condition
~
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
description
(,)
CP
a::
(2)
Each of these devices consists of a dual
single-ended line receiver with TTL-compatible
strobes and outputs, The reference voltage
(switching threshold) is applied externally and
can be adjusted from 1.5 volts to 3.5 volts,
making it possible to optimize noise immunity for
a given system design. Due to their low input
current (less than 100 microamperes), they are
ideally suited for party-line (bus-organized)
systems.
The '140 has a common reference voltage pin
and a common strobe, The '141 is the same as
the '140 except that the input stage is diode
protected.
COMSTRB
lUNE ~1_3)_ _-1~
(1)
~
) 1 > - - lOUT
CP
>
(6)
COMREF ~-....
.a.'
"C
C
»_1_7;..) 20UT
2L1NE
~
"i)
logic diagram (positive logic I
.!15:)_--.,........ - -___
CP
c:
:::l
FUNCTION TABLE
lEACH RECEIVER)
LINE INPUT
s
STROBE
OUTPUT
Vref - 100 mV
L
H
+ 100 mV
X
X
H
L
L
'" Vref
H = high level. L =low level. X = irrelevant
The SN75140 and SN75141 are characterized
for operation from ooe to 70 oe.
PRODUCTION DATA dD.um••tl .Dntal.lnformatiD.
CUrratlt as of publicotiD. date. P'Ddum COnlD'" t.
Ipoeillc"'D.1 pa' tho ta.... Df T.... 1.II,um••tl
:'~::=i;.:::I~'li ~=:~~n :.~O:::~:~
not
Copyright © 1986, Texas Instruments Incorporated
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
4-191
SN75140, SN75141
DUAL LINE RECEIVERS
schematic (each receiver)
r-~~~------~-----'-----'----~----~~~------~~----VCC
4000
LINE
INPUT {L}
COM REF
TO OTHER
LINE RECEIVER
4000
_--w. . . -+----..l
t-----OUTPUT
•
TO OTHER
LINE RECEIVER
~------~~-~~~---~---4--~~----~~~r-~-----GND
4. TO OTHER LINE RECEIVER
LEGEND:
1111111111'140 device only
Resistor values shown are nominal and in ohms.
r-
S·
~_~______ CDMMON
STROBE
CD
...C
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
~.
~
=
CD
~
::.:-
...
UNIT
Supply voltage, Vec {see Note 1}
Reference input voltage, Vref
Line input voltage with respect to ground
V
5.5
V
-2 to 5.5
line input voltage with respect to Vref
Strobe input voltage
CD
(I)
7
I 0 package
I JG package
Continuous total dissipation at {or below}
25°e free-air temperature {see Note 2}
±5
V
V
5.5
V
725
825
mW
1000
1 P package
o to 70
Operating free-air temperature range
Storage temperature range
-65 to 150
°e
°C
300
°C
260
°C
Lead temperature 1,6 mm {1/16 inch} from case for 60 seconds: JG package
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: o or P package
NOTES: 1, Unless otherwise specified, voltage values are with respect to network terminal.
2. For operation above 25 °e free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the JG package, these
chips are glass mounted. For SN75140 and SN75141 devices in the P package, use the 8.0-mW/oe curve.
recommended operating conditions
MIN
NOM
MAX
Supply voltage, VCC
4.5
5
5.5
Reference input voltage, Vref
1.5
3.5
V
Vref+ O. 1
V
High-level line input voltage, VIHIL}
UNIT
V
Low·level line input voltage, VIL(L}
0
VCC- 1
Vre f- O. 1
High-level strobe input voltage, VIHIS}
2
5.5
V
Low-level strobe input voltage, VIL(S}
0
0.8
V
TEXAS . "
4-192
INSIRUMENlS
~ST
OFFICE SOX 655012 • DALLAS, TEXAS 75265
V
SN75140. SN75141
DUAL LINE RECEIVERS
electrical characteristics over recommended operating free-air temperature range. Vee - 5 V ± 10%.
Vref - 1.5 V to 3.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK(SI
Strobe input clamp voltage
VOH
High-level output voltage
VOL
10H = -400 p.A
VIH(LI = Vrel
10L = 16 mA
Low-level output voltage
Strobe input current
11151
12 mA
11151 VIL(LI - Vr_1 - 100 mY, VIL(SI - 0.8 V,
2.4
High-level
V
0.4
1
2
80
VilLI = 0 V, Vrel = 3.5 V
Com reI
100
70
200
-3.2
~A
-10
~
>
Short-circuit output current i
VCC = 5.5 V
ICCH
Supply current, output high
VIIS) = 0 V, VIIL) = Vref - 100mV
ICCL
Supply current, output low
VIIS) = 0 V, VIIL) = Vr_f
+ 100 mV
=
mA
CJ
CD
-.
I I)
CD
-66
mA
18
30
mA
20
35
mA
TYP
MAX
22
35
22
30
12
22
8
15
-18
'a)
a:
~A
-20
lOS
II
CD
-10
VIIL) = 1.5 V, Vref = 0 V
Com ref
5 V, T A
35
VIIL) = 0 V, Vref = 1.5 V
Reference
=
100
VIIS) = 0.4 V
line input
input current
35
1.6
Strobe
Com strb
Low-level
mA
40
VilLI = 3.5 V, Vr~1 = 1.5 V
Reference
IlL
V
0.4
VIISI = 2.4 V
Line input
input current
UNIT
V
100 mY, VIL(SI = 0.8 V,
Com strb
IIH
MAX
1.5
VIISI = 5.5 V
Com strb
Strobe
t All typical values are at V CC
Typt
VIL(LI - Vrel - 100 mY, VIH(SI - 2 V,
10L = 16 mA
Strobe
at maximum
input voltage
+
MIN
25 ·C.
>
';:
C
CD
c:
:::::i
t Only one output should be shorted at a time.
switching characteristics. Vee - 5 V. Vref
PARAMETER
tpLH(L)
2.5 V. TA - 25°e
TEST CONDITIONS
Propagation delay time, low-tohigh-level output from line input
tpLH(S)
tpHL(S)
UNIT
ns
Propagation delay time, high-totPHL(L)
MIN
low-level output from line input
CL = 15 pF, RL = 400 ll, See Figure 1
Propagation delay time, low-tohigh-level output from strobe input
ns
Propagation delay time, high-tolow-level output from strobe input
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
4-193
SN75140. SN75141
DUAL LINE RECEIVERS
PARAMETER MEASUREMENT INFORMATION
:5 10ns
2.5 V
Vcc
---l1f-
~
$-1- - - -
LINE
INPUT 2.5 V
---1r.-r-.... __
LINE
INPUT
STROBE
INPUT
•
ISee NOTE B)
1+-:510nS
~10%90%10%
OUTPUT
- - -2.7V
__
2._5_V_ _ _ _ _ _ _ _ __
2.3 V
-
II
I'
II
II
I
I
1:- ----.,
:510 ns--.t W--
,
L - ~ - ---1
STROBE
INPUT
CL - 15pF
ISee Note C)
---.j
H-tPLHILI
10%
r-
10%
jt-tPHLIS)I
I
~
---...
1.5 V
OUTPUT
TEST CIRCUIT
J.....-.
f"
:510 ns
~'9.0%E--
1.5V
tPHLIL)~)
I
...
1.5V
3.5V
0 V
jf-tPLHIS)
I
VOH
VOLTAGE WAVEFORMS
3'
CD
NOTES:
...
<'CD...
C
A. Input pulses are supplied by generators having the following characteristics: PRR ::s; 1 MHz, duty cycle ::s; 50%, Zout
B. Unused strobes are to be grounded.
C, CL includes probe and jig capacitance .
D. All diodes are 1N3064.
-
FIGURE 1
CIl
::KI
CD
n
CD
TYPICAL CHARACTERISTICS
<'CD...
OUTPUT VOLTAGE
vs
LINE INPUT VOLTAGE
CIl
4
"T
'1
'1
Vee - 5 V
>
3
>
2
.,I
i'"
SQ.
S
V,ef -
"'
2.5 V-
VI(SI - 0
TA - 25°e
-
0
I
0
>
\.
o
o
2
3
4
Vl(lI- Line Input Voltage- V
FIGURE 2
4-194
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 65'5012 • DALLAS, TEXAS 75265
5
= 50 O.
SN75140. SN75141
DUAL LINE RECEIVERS
TYPICAL APPLICATION DATA
line receiver
---..,
5V
STROBE
r--DATA _-,-_.r--,.
INPUT
~-7I---t----""'--1I:--r,i-.J"_
I
STROBE
I
RT
I
I
OUTPUT
I
I
I
I
I
I
I
I
I
I % SN75361A I
I
I
I
% SN75140/% SN75141
•
high fan-out from standard TTL gate
STROBE
ANY
SERIES 54174
LOGIC
N=1
r-t----t----r,-.l____- ....
~
CD
>
----:-+-1'. . .
'iii
N =2 ....
CJ
CD
-..
a:
I I)
CD
>
';:
SN75140/SN75141
Q
CD
c
::i
t Although most Series 54/74 circuits have a guaranteed 2.4-V output at 400
~A. they are typically capable of maintaining a 2.4-V
output level under a load of 7.5 rnA.
dual bus transceiver
+5V
vee
r
= 5 V
RT (50 to 100 II depending
-",--'..--:-..._..;D~A..;.T;.;.A.;..;.BU..;.S.;....-tlI
.J... -
DATA IN
I
DATA IN
STROBE -1:-a..:::-%"S-N-7'545~ _
vee
I
...J
= 5 V
r-1. ----..,
DATA OUT
+5V
I
I
I
I
DATA OUT
STROBE
on rone impedance'
,~.__~-,~
II
I
I
L __
I
I I
':'_~.1
% SN75140/% SN75141
Vraf = 1.5 V
to 3.5 V
....
Using this arrangement, as many as 100 transceivers can be connected to a single data bus. The adjustable reference voltage
feature allows the noise margin to be optimized for a given system. The complete dual bus transceiver (SN75453B driver and
SN75140 receiver) can be assembled in approximately the same space required by a single 16-pin package and only one power
supply is required (+ 5 VI. Data In and Data Out terminals are TTL compatible.
TEXAS "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-195
SN75140. SN75141
DUAL LINE RECEIVERS .
TYPICAL APPLICATION DATA
schmitt trigger
vee
R1
= 5V
STROBE
r
SIGNAL
INPUT
----,
)O-.;.I...._TTL
I
I
I
OUTPUT
L- __ lr -_-1
_
-
,...
<
CD
...
tn
::a
CD
(')
CD
<'
...
CD
tn
3.5
3.5
CD
C
:I,
EXAMPLES OF TRANSFER CHARACTERISTICS
4
4
S'
Yo SN751401
Yo SN75141
:>
R1
RT
RF
TA
3
I
iD
2.5
>
2
!'"0
-
6.2 kll
3.9 kll
16 kll
25°C
>
I
~
~
GO
2.5
>
2
!'"0
R1
RT
RF
TA
3
-
5.9 kll
3.9 kll
5 kll
25°C
~
c.
~
1.5
0
I
0
1.5
0
I
0
>
>
0.5
o
0.5
o
o
0.5
1.5
2
2.5
3
o
0.5
1.5
2
2.5
VI-Input Voltage-V
VI-Input Voltage-V
Slowly changing input levels from data lines, optical detectors, and other types of transducers may be converted to standard TTL
signals with this Schmitt trigger circuit. R1, RF, and RT may be adjusted for the desired hysteresis and trigger levels.
4-196
TEXAS
..If
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
3
SN75140, SN75141
DUAL LINE RECEIVERS
TYPICAL APPLICATION DATA
gated oscillator
Vcc
STROBE
STROBE
OUTPUT~
}C>+-+-.-OUTPUT
~twl.-
Vref
R
-:;rc
...
II)
OSCILLATOR FREQUENCY
vs
RC TIME CONSTANT
II)
>
"Q)
(,)
II)
-...
40
a::
I I)
20
N
:t
:!!
10
c:
7
!
u.
4
I
>u
II)
~ .........
......... 1-1--
III
::I
C'
~
>
";:
C
;Vref - 1.5V
II)
-
'- Vref - 2.5 V
s::
::;
RF-15kll
..!.
0.6
tw - -
2
f.
VCC - 5 V
TA - 25°C
1
0.1
0.2
0.4 0.7 1
2
4
7 10
RC Time Constant-I's
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-197
r5'
(I)
...c
<'
...
(I)
-!II
lJ
(I)
(')
(I)
<'
...
(I)
!II
4-198
SN75146
DUAL DIFFERENTIAL LINE RECEIVER
02609. FEBRUARY 1986
•
Meets EIA Standards RS-422-A and
RS-423-A
•
Meets EIA Standards RS-232 and
CCITT Y.2S with External Comp~nents
•
Meets Federal Standards 1020 and 1030
•
Built-in S-MHz Low-Pass Filter
•
Operates from Single S-Y Power Supply
•
Wide Common-Mode Yoltage Range
•
High Input Impedance
D. JG. DR P PACKAGE
(TOPVIEWI
VCC[j8
10UT
2
7
20UT
3
6
GND
4
5
logic symbol t
11N +
11N -
•
TTL-Compatible Outputs
•
S-Pin Dual-In-Line Package
•
Pinout Compatible with the I'A9637 and
I'A9639
11N+
11N21N+
21N-
21N+
21N -
(8)
]
(7)
.ere>
(2)
'\)
(6)
(3)
(5)
10UT
20UT
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEG Publication 617-12.
description
II.
fI)
Q)
The SN75146 is a dual differential line receiver
designed to meet EIA standards RS-422-A and
RS-423-A. The receiver is designed to have a
constant impedance with input voltages of
± 3 volts to ± 25 volts allowing it to meet the
requirements of EIA standard RS-232-C and
eelTT recommendation Y. 2S with the addition
of an external bias resistor. This receiver is
designed for low-speed operation below
355 kilohertz, and has a built-in 5-megahertz
low-pass filter to attenuate high-frequency
noise. The inputs are compatible with either a
single-ended or a differential line system and the
outputs are TTL compatible. This device
operates from a single 5-volt power supply and
is supplied in both the S-pin dual-in-line and small
outline packages.
>
"iii
logic diagram
u
Q)
lIN+~8)
.er
-.
a::
(2) lOUT
l1N- 17)
f I)
Q)
>
2IN+~6)
.r:r
(3) 20UT
"C
Q
Q)
21N- (5)
c:
:::::i
The SN75146 is characterized for operation from
70°C.
ooe to
PRODUCTION DATA doculla.t. comi. i.formllion
curranl II of ,.bllclllon UII. ProdUell co.form to
l,.clficlllo.1 per tho terml of Taxu 1.llromanll
:'~:~~I~air::I':.'li =~~i:r :.\"=:::,:~~ not
Copyright © 1986, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-199
SN75146
DUAL DIFFERENTIAL LINE RECEIVER
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
Vcc--------~~~~---
-----~---Vcc
Rl
50 Il NOM
740!l NOM
7.4 Rl
OUTPUT
7.4 k!l NOM
INPUT - -........M r -....
740 Il NOM
II
r-
5"
CD
...C
<"
CD
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V CC (see Note 1) ...................................... - O. 5 V to 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 V
. Differential input voltage (see Note 2) ......................................... ± 25 V
Output voltage (see Note 1) ...................................... , .. -0.5 V to 5.5 V
Low-level output current ................................................... 50 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 3):
D package. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 725 mW
JG package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 825 mW
P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1000 mW
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O°C to 70°C
Storage temperature range ......................................... - 65°C to 1 50°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package ........... 300°C
Lead temperature 1,6 mm (1/16 inch). from case for 10 seconds: D and P package ....... 260°C
C;;
::D
CD
()
CD
...<"
CD
(I)
NOTES:
1. All voltage values, except differential input voltage, are with respect to the network ground terminal.
2. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input.
3. For operation above 25°e free-air temperature. derate the JG package to 528 mW at 70 0 e at the rate of 6.6 mW/De, the
o package to 464 mW at 70 De at the rate of 5.8 mW/De. and the P package to 640 mW at 70 De at the rate of 8 mW/De.
The SN75146 chips are glass mounted in the JG package.
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage. Vee
Common-mode input voltage, VIC
4.75
5
5.25
±7
V
Operating free-air temperature, T A
0
25
70
4-200
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
V
°e
SN75146
DUAL DIFFERENTIAL LINE RECEIVER
electrical characteristics over recommended ranges of supply voltage. common-mode input voltage.
and operating free-air temperature (unless otherwise noted I
PARAMETER
TEST CONDITIONS
VT
Threshold voltage (VT + and VT _ )
Vhys
Hysteresis (VT + - VT _ )
VIB
Input bias voltage
11- 0
VOH
High-level output voltage
VIO - 0.2 V,
VOL
Low-level output voltage
VIO
r;
Input resistance
See Note 5,
II
Input current
lOS
Short-circuit output current §
Vo
ICC
Supply current
VID -
Typt
MIN
See Note 4
MAX
-0.2~
0.2
-0.4~
0.4
UNIT
V
70
10 -
-0.2 V,
=
10
0,
=
I VI =
0.5
V
7.8
9.5
kO
1.1
3.25
6
10V
-40
V
V
0.35
10 V
= 0.2
V
3.5
20 mA
IVI VID
-0.5 V,
2.5
-1 mA
VI - 3 V to 25 V or
VI = -3Vto -25V
0 to 5.5 V,
See Note 6
=
2.4
2
=
VCC
mV
mA
1.6
3.25
-75
-100
mA
35
50
mA
No load
II...
t All typical values are at VCC = 5 V, TA = 25°C.
t The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for
en
CD
threshold levels only.
.
§ Only one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTES: 4. The expanded threshold parameter is tested with a 500-0 resistor in series with each input.
5. ri is defined by AVI/Ali.
6. The input not under test is grounded.
switching characteristics.
Vee
= 5
V.
>
'0;
(,)
CD
a::
~
TA
CD
PARAMETER
TEST CONDITION
tpLH
Propagation delay time, low-to-high-Ievel output
tPHL
Propagation delay time, high-to-Iow-Ievel output
CL = 30 pF,
See Figure 1
MIN
TYP
MAX
>
';::
100
150
300
C
100
150
300
CD
C
:::::;
PARAMETER MEASUREMENT INFORMATION
OUTPUT
r------""""
+0.5 V- -
392fl
INPUT
(M~:~: B)~ 5~
-0.5
51 fl
V~
5~\1
-~---
'--
~tPLH
r---
~t"HL
l.. '..
Ir-----------~
(see Note A)
3.92kfl
OUTPUT
______-J.
OH
~-----VOL
VOL TAGE WAVEFORM
TEST CIRCUIT
NOTES:
V
A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: tr
duty cycle = 50%.
:$
5 ns, tf
:$
5 ns, PRR
:$
300 kHz,
FIGURE 1. TRANSITION TIMES
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
4-201
SN75146
DUAL DIFFERENTIAL LINE RECEIVER
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
4
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
4
VC~=4.~!?V
VCC=5.25V
TA = 25°C
r-TA = 25°C
I
I
VIC=O
I
I
I
I
!
~IC=~
:
C
:::I,
o
~
-
-100
r;
-50
:
:
I
:
I
n
'i
I
I
o
100
50
-50
-100
o
50
100
VID-Differential Input Voltege-mV
FIGURE 2
CD
VIC-O
;
I
o
=±7 V
VIC=±7V:
VID-Qifferentiallnput Voltage-mV
::a
VIC
!
I
I
I
I
I
VIC=±7 V:
CD
I
I
I
I
I
S'
I
I VIC=O
:VIC=±7V
!
r-
I
I
•
•I
I
FIGURE 3
CD
:cr
CD
TYPICAL APPLICATION DATA
iii
+12 V
+5V
>---IL
R
1/2 uA9636
-12 V
IS•• Note Al
V
NOTE A: In order to meet the input-impedance and open-circuit-input voltage requirements of RS·232-C and CCITT V.28 and guarantee
open-circuit-input failsafe operation, R and V are selected to satisfy the following equations:
R
V = -1.1 - 3.3 ri
volts
3k1lS~S7kll
R
+ 'i
FIGURE 4. RS-232-C SYSTEM APPLICATIONS
4-202
TEXAS
~
INSTRUMENTS
POST OFFiCe; BOX 855012 • DALLAS. TEXAS 76286
SN75146
DUAL DIFFERENTIAL LINE RECEIVER
TYPICAL APPLICATION DATA
+5V
TWISTED PAIR
+5V
+5V
II
~
Q)
>
FIGURE 5. RS-422-A SYSTEM APPLICATIONS
"a)
U
-..
Q)
a::
( I)
Q)
>
".:::
Q
G)
c
:::i
TEXAS.
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 76285
4-203
II
r-
:r
CD
...o
<'
CD
u;
::J:I
CD
n
CD
.::-
...
CD
III
4-204
SN55150. SN75150
DUAL LINE DRIVERS
0951 JANUARY 1971-REVISEO SEPTEMBER 1986
•
Satisfies Requirements of EIA Standard
RS·232·C
•
Withstands Sustained Output Short· Circuit
to any Low·lmpedance Voltage Between
-25 V and 25 V
SN56150 ... JG PACKAGE
SN75150 ... D. JG. OR P PACKAGE
(TOPVIEWI
•
2 p's Max Transition Time Through the + 3
V to - 3 V Transition Region Under Full
2500·pF Load
•
Inputs Compatible with Most TTL Families
•
Common Strobe Input
S u 8 VCC+
2
7
lY
lA
2A
3
6
2Y
GND
4
5
VCC-
SN55150 .•. FK PACKAGE
+
U
•
Inverting Output
•
Slew Rate can be Controlled with an
External Capacitor at the Output
•
Standard Supply Voltages ...
(TOP VIEWI
U
U
UU
2002>2
3
NC
lA
NC
± 12 V
description
2
'8
5
17
6
16
7
'5
14
8
The SN55150 and SN75150 are monolithic dual
line drivers designed to satisfy the requirements
of the standard interface between data terminal
equipment and data communication equipment
as defined by EIA Standard RS·232·C. A rate of
20,000 bits per second can be transmitted with
a full 2500·pF load. Other applications are in
data·transmission systems using relatively short
single lines, in level translators, and for driving
MOS devices. The logic input is compatible with
most TTL families. Operation is from + 12·volt
and - 12·volt power supplies.
The SN55150 is characterized for operation over
the full military temperature range of - 55°C to
125°C. The SN75150 is characterized for
operation from OOC to 70°C.
II...
1 20'9
4
1/1
2Y
CI)
>
NC
'0)
CJ
9 '0'1 '2'3
UOU
222
t!l
-...
CI)
a::
IU
u
U
>
2
1/1
CI)
>
NC - No internal connection
';:
C
logic symbol t
CI)
r:::
:.:::i
t This symbol is in accordance with ANSI/IEEE Std 9' -1984 and
lEG Publication 617-12.
Pin numbers shown are for D, JG, and P packages.
logic diagram (positive logic)
STROBE (II
1 A ..:;(2=:1_+-I._J
2 A ..:;(3=:1_ _- I . _ J
PRODUCTION DATA documonts contain information
current 8S of publication data. Products conform to
spacifications par the terms of Texas Instruments
:'~~~:~~i;8t::I~lJe ~:~::i:r lr~D:::~~::-'~ not
Copyright © 1982, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4·205
SN55150, SN75150
DUAL LINE DRIVERS
schematic leach line driver)
vcc+ __-.__
~.-
*-+
____________-.____
~~
15 kll
11 kll
____-.____________
~
10 kll
INPUT ___
A
STROBE __-.-111.......~~.....1-1.....+--1
S
7 kll
TO OTHER
LINE DRIVER
II
r-
OUTPUT
15 kll
5'
y
CD
...o
...<'
CD
(I)
~
CD
4.5 kll
GND---.----~~--_t
TO OTHER
LINE DRIVER
n
CD
<'
...
CD
(I)
TO OTHER
LINE DRIVER
VCC_--~------------------------~~--------~----~~_J
4-206
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN55150. SN75150
DUAL LINE DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SN55150
Supply voltage Vee + Isee Note 1)
Supply voltage VeeInput voltage
Applied output voltage
SN75150
15
V
-15
-15
V
15
15
V
±25
±25
V
o package
Continuous total dissipation at (or below) 25°C
UNIT
15
725
FK package
1375
JG package
1050
825
Operating free-air temperature range
-55 to 125
o to 70
°e
Storage temperature range
-65 to 150
-65 to 150
°e
free-air temperature (see Note 2)
P package
1000
Case temperature for 60 seconds: FK package
260
Lead temperature 1,6 mm 11/16 inch) from case for 60 seconds: JG package
300
°e
°e
Lead temperature 1,6 mm 11/16 inch) from case for 10 seconds: 0 or P package
NOTES:
mW
260
°e
1. Voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the JG package, SN55150
chips are alloy mounted and SN75150 chips are glass mounted. In the P package use the 8.0-mW/oC curve for these devices.
.
CI)
CI)
>
"a;
recommended operating conditions
(J
CI)
SN75150
SN55150
a:
--.
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
Supply voltage, Vee +
10.B
12
13.2
10.8
12
13.2
V
Supply voltage, Vee-
-10.B
-12
-13.2
- 10.8
-12
- 13.2
V
5.5
2
5.5
V
";::
O.B
0
0.8
V
C
±15
V
High-level input voltage, VIH
2
Low-level input voltage, VIL
0
Applied output voltage, Vo
Operating free-air temperature, T A
±15
-55
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
125
0
70
°e
CI)
CI)
>
CI)
c:
:::i
4-207
SN55150, SN75150
DUAL LINE DRIVERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
.
PARAMETER
TEST CONDITIONS
VCC- - -13.2 V,
RL = 3 kll to 7 kll
10.8 V,
VCC- -
VCC+ - 10.8 V,
VOH
High-level output voltage
VOL
Low-level output voltage Isee Note 3)
IIH
High-level input current
= 0.8
VIL
VCC+ -
V,
10.8 V,
=
2 V,
VCC+ - 13.2 V,
VCC- = -13.2 V,
VIH
RL
=
IlL
Low-level input current
=
VCCVI
lOS
ICCH+
CD
.
ICCH-
CD
ICCL+
:c:!'
Ul
l
en
TA
high-level output
Supply current from V CC + '
low-level output
=
TA
=
UNIT
V
-5
Data input
1
10
Strobe input
2
20
Data input
-1
-1.6
Strobe input
-2
-3.2
2
-3
8
-8
13.2 V,
Vo - 25 V
VQ = -25 V
-13.2 V
Vo
V
~A
= 0, VI = 3
= 0, VI = 0
V
10
15
30
-10
-15
-30
10
22
-1
-10
8
17
-9
-20
VCC- = -13.2 V,
RL = 3 kll,
rnA
rnA
25°C
VCC+ = 13.2 V,
VI = 3 V,
low-level output
-8
MAX
rnA
V
VCC+ = 13.2 V,
VI = 0,
Supply current from VCC _,
ICCL-
~
';:
C
Q)
c
:::::i
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
4-209
SN55150. SN75150
DUAL LINE DRIVERS
TVPI.CAL CHARACTERISTICS
OUTPUT CURRENT
vs
APPLIED OUTPUT VOLTAGE
20
Vcc+ - 12V
VI _ 2.4V
15 Vcc- - -12 V
TA - 25°C
<
10
I
5
E
1
°
i
•
r
"
.....- .....- .J-
- - ::::::. ...-- ",
.....
",
-5
o
I
..9- 10
I--- I--"RL-7kll
'RL - 3 kll
1I
-15
yl -.0.4 IV
°
-20
-25-20-15-10-5
5 10 15 20 25
VO-Applied Output Voltage-V
FIGURE 2
TYPICAL APPLICATION DATA
r-----,
'0:1.,...---..,
CHANNEL 1 I
DATA INPUT I
STROBE
CHANNEL 2
DATA INPUT
'"
I
I
I
1
I
I
I-
l
I
~If+-.,
~~~O_..J
ALL DIODES ARE-·
1N752A
,..
MIL·STD·1BBC _ _ _ _ _
INTERFACES
CHANNEL 2 STROBE
r--
--,
I
II
CHANNEL 1 STROBE
FIGURE 3. DUAL-CHANNEL SI!\IGLE-ENDED
INTERFACE CIRCUIT MEETING MIL-STD-188C.
PARAGRAPH 7;2.
4·210
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 7&266
SN75151, SN75153
QUAD DIFFERENTIAL LINE DRIVERS WITH 3·STATE OUTPUTS
02453. DECEMBER 1978-REVISED OCTOBER 1986
•
Meets EIA Standard RS·422-A
•
High-Impedance Output State for Party-Line
Operation
•
High Output Impedance in Power-Off
Condition
•
Low Input Current to Minimize Loading
•
Single 5-V Supply
•
40-mA Sink- and Source-Current Capability
•
High-Speed Schottky Circuitry
•
Low Power Requirements
SN75161
OW. J, OR N PACKAGE
(TOP VIEWI
1A
1Y
1Z
1C
CC
2C
2Z
2Y
2A
VCC
4A
4Y
4Z
4C
S
3C
3Z
3Y
3A
GND
•
SN75153
description
J OR N DUAL-IN-L1NE PACKAGE
These line drivers are designed to provide
differential signals with high current capability
on balanced lines. These circuits provide strobe
and enable inputs to control all four drivers, and
the SN75151 provides an additional enable input
for each driver. The output circuits have active
pull-up and pull-down and are capable of sinking
or sourcing 40 milliamperes.
(TOPVIEWI
...
II)
1A
1Y
1Z
CC
2Z
2Y
2A
The SN75151 and SN75153 meet all
requirements of EIA Standard RS-422-A and
Federal Standard 1020. They are characterized
for operation from ooe to 70 oe.
VCC
4A
4Y
4Z
CD
>
.G)
(,)
CD
a::
--...
S
I I)
3Z
3Y
3A
GND
CD
.>.:::
C
CD
c
::l
FUNCTION TABLES
SN75151
SN75153
ENABLE
STROBE
DATA
CC
C
S
A
L
X
X
X
X
L
H
X
L
H
CC
S
A
L
X
X
H
L
X
L
H
H
X
L
L
H
H
H
H
L
X
Z
Z
X
L
H
H
H
X
L
L
H
H
H
H
L
::a::i:r :.r::;:~A:~~ not
DATA
Z
Z
H
PRODUCTIO.'OATA docu",onts conlain infor",ation
currant II of publication data. Products conform to
specificatioRs per the terms of Texas Instruments
STROBE
Z
H
OUTPUTS
ENABLE
y
H
=:~~ii,a{::~~i
INPUTS
OUTPUTS
INPUTS
ENABLE
Y
Z
Z
Z
Copyright IS) 1978. Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-211
SN75151. SN75153
QUAD DIFFERENTIAL LINE DRIVERS WITH 3·STATE OUTPUTS
logic symbols t
SN75151
SN75153
lC (41
lA (11
2C (61
2A (91
3C (141
•
3A (111
3A
4C (161
4A (191
4A
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagrams (positive logic)
r-
:r
CD
o
S
<
CC
iil
lC
:::I.
CD
~
CD
SN75153
SN751S1
lA
(lSI
,S
(5)
cc
(4)
(2)
(1)
(3)
(121
(4)
.-l
lY
lZ
lA
(11
(')
CD
<'
CD
.
2C
en
2A·
3C
3A
4C
4A
4·212
I
(6)
(8)
(91
(71
2Y
2Z
2A
(71
(141
(121
(11)
(131
3A
(91
(161
(lSI
(19)
(17)
.
4Y
4Z
-
(31
1
(5)
(61
J...
3Y
3Z
I
1
4A
(15)
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS, TEXAS 75265
I
-
1
.L
1 1
-
(2)
1
(10)
(11)
(141
(13)
1Y
lZ
2Y
2Z
3Y
3Z
4Y
4Z
SN75151, SN75153
QUAD DIFFERENTIAL LINE DRIVERS WITH 3·STATE OUTPUTS
schematic
STROBE S
COMMON TO ONE
TO THREE
INPUT A
OTHER DRIVERS
OTHER CHANNEL
VCC~~__~____~____~____4-+-__~__~__~r_-~'
____- 4 r -__~____~
91l
OUTPUT Z
OUTPUT Y
II
ENABLE C
(SN75151
ONLYI -
-
-
~-
-!t
.,.:--
"iii
i
CJ
50
500
t
Voe
{-
FIGURE 1. DIFFERENTIAL AND COMMON-MODE OUTPUT VOLTAGES
TEXAS
..
en
VOD2
I
CD
a::
-.
n
,r,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
CD
>
";:
o
CD
c:
::i
4-215
SN75151, SN75153
QUAD DIFFERENTIAL LINE DRIVERS WITH 3·STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
1 kO
5 V
----.,.....I\Nr,
.......+---f-~t--+- Y OUTPUT
1-.......---:----1L...Jp---:-- Z OUTPUT
Y
Y
RL - 1000
Z
Z
r-
:S"
...c
CD
TERMINATION B
TERMINATION A
<"CD
...
TEST CIRCUITS
(II
"i
CD
I"
~ 1 14--,,;
II,
1 I 90%
(')
CD
<"
CD
...
INPUT
(II
25ns~
~ 11 14--,,;
5 ns
I
90%
1
5 ns
I
;:r I" - - -
10%1
...-
......-tPLH
OV
~tPHL
.,....90-%---1,-~0%
Y OUTPUT
3 V
1
1.5 V
1- -
I
I
1
10%
I
I
VOH
1.5 V
1 -+I I4-tTHL
1",
..--+!.If-tPLH
90%:
90%
VOH
1.5 V
Z OUTPUT
10%
10%
I
I4-tTHL
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zout = 50 \}, PRR ,,; 10 MHz.
B. C'L includes probe and jig capacitance.
FIGURE 2, tPLH, tPHL. tTLH. tTHL. AND OVERSHOOT FACTOR
4-216
. TEXAS'"
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TERMINATION C
SN75151, SN75153
QUAD DIFFERENTIAL LINE DRIVERS WITH 3·STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
,-----,
r-.-~--~I~
I
'*
I
I
I
I
I
I
I
I
I
IL
___ JI
I
CL-30pF
(See Note B)
~I-o---""-OUTPUT
I
I
CL-30pF
I
Note B)
I
L ____________'l:' (See
____
I
~
~
1 kll
5V
...
TEST CIRCUIT
III
~
s 5n.-.I
.jr.:::::::-_~="Iiltt-I 90%
90%
1.5V
I
...--100 n.-----.t
~tpZH
I
I
I
1/
OUTPUT
I
/1.5 V
_ _ _- J .
>
'4j
- --
3 V
CJ
-...
Q)
I
1.5V
I
Q)
I
a:
10%
I II
0 V
Q)
>
~
';:
~.... VOH
I
0.5 V
tPHZ.../.--.l
Voff
o
Q)
~
0 V
r::
:.:J
VOLTAGE WAVEFORMS
FIGURE 3. tpZH AND tPHZ
NOTES: A. The pulse generators have the following characteristics: Zout = 50 11, PRR s 500 kHz.
B. CL includes probe and jig capacitance.
TEXAS . "
INSlRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-217
SN75151, SN75153
QUAD DIFFERENTIAL LINE DRIVERS .WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
SV
6V
RL-11111
1 kll
~1~--"'--OUTi>UT
.....-"-..A~-----.--_....J
I
I
CL-30pF
I
I
I
-:I:' (.ee Nole B) I
lL-------------=-----~
TEST CIRCU(T
-+l
~";5n•
..r:=-~90~%~:-
r - - - -
1.5V
II
1.5V
1----100ns~
10%
OV
I
I
I4-IPZL....
I
I
I
____"'\ I
I
I
If-IpLZ-.j
,\SV
I
OUTPUT
-3 V
•
!~5
V
l_OlV
-
.,.-VOL
VOLTAGE WAVEFORMS
FIGURE 4. tPZL AND tPLZ
NOTES: A. The pulse generators have the following characteristics: Zout = 50 II, PRR ,,; 500 kHz .
. B. CL includes probe and jig capacitance.
4-218
TEXAS "
INSTRUMENTS
POST OFFICI! BOX 655012 • DALLA$. TEXAS 76266
SN75151, SN75153
QUAD DIFFERENTIAL LINE DRIVERS WITH 3·STATE OUTPUTS
TYPICAL CHARACTERISTICS
Y OUTPUT VOLTAGE
vs
DATA INPUT VOLTAGE
5
>
..
No Lo~d
TA - 25°e
Vee - 5.5 V
4
Vee - 5 V
I
Vee - 4.5 V
01
.l::
0
3
>
;
~
0
I
0
2
.
>
II)
~
"«;
o
(J
CD
a::
0 2 3
--.
I I)
VI-Data Input Voltage-V
CD
>
";:
FIGURE 5
Y OR Z OUTPUT VOLTAGE
vs
ENABLE INPUT VOLTAGE
4
6
Load -470!l
to Ground
See Note 3
-TA - 25°e
-
Q
Y OR Z OUTPUT VOLTAGE
vs
ENABLE INPUT VOLTAGE
Vee - 5 V
5
Vee - 5 V
Vee - 4.5 V
>
1
I
Vee - 4.5 V
II
01
!;
Load - 470!l to Vee
TA - 25°e
See Note 4
Vee - 5.5 V
Vee - 5.5 V
CD
c:
:.::;
4
3
~
0
I
0
2
>
o
o
o
3
2
o
2
3
VI-Enable Input Voltage-V
VI-Enable Input Voltage-V
FIGURE 6
FIGURE 7
NOTES: 3. The A input is connected to Vee during the testing of the Y outputs and to ground during testing of the Z outputs.
4. The A input is connected to ground during the testing of the Y outputs and to Vee during the testing of the Z outputs.
TEXAS ."
INSfRUMENlS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75286
4-219
SN75151, SN75153
QUAD DIFFERENTIAL LINE DRIVERS WITH 3·STATE OUTPUTS
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
HIGH·LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
..,
>
VCC - 5 V
See Note 3
>,
.
f>
5
'"
~
."
0
> 4
a.
~
0
1..
....;;
I"'"
r,
CD
0
s·
IOH -
3
IOH -
a.
!i
0
_40mA
::::!.
...
-
TA '.
2~OC
>
!J
.;;
2
'"
%
I
X
0
>
o
<
2
r-- ~ee I.. 5l'7" See Note 3
.~
r-- _liCe
.........
.. ~
J,~
......... \
- lice .. 45
-t--:-. -...II
j'"""-...\
Gi
>
CD
3
;
-20mA
x
C
----
-
4
6
o
10
20
30
40
50
60
70
o
80
o
-20
T A - Free-Air Temperature- °c
(II
:xJ
-40
-100
FIGURE 9
FIGURE 8,
CD
-80
-60
IOH-High-Level Output Current-mA
C')
CD
;r
CD
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
...
(II
LOW-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
0.6 .----,,--.,--,---,--..,--..,--.,---,
.,
0.5
>
0.4
>
i'"
VCC - 5'V
IOL - 40 mA
See Note 4
-+--+--+--1--___1--1
0
Ii
....
...~,
I--___I~___I-_+-_+-_+_-+--+-__f
0.3 I--___If-___I-_+-_+-_+_-+--+-__f
>
0.2 f--+--+--+--+----1f-_+--+----i
0
...0
>
>
..I
'"
~
~
1.0
f---+--+--+---If---+--f--I---l
O~~-~_~~_-L_~~~~
o
10
20
30
40
50
60
70
80
0.8
~;
0.7
~
0
0.5
0.4
~
0.3
...
0.2
....
0
::-
J
0.6
1
.3,
0.1
TA - '25°C
0.9 See Note 4
~(jC
.
A.~~~
~ ~CC"
~
//
~~
~.
-r
"
0.1
o
o
20
40
60
80
100
120
IOL -Low-Level Output Current-mA
TA-Free-Air Temperature
FIGURE 10
FIGURE 11
NOTES: 3. T~e A input is connected to Vee during the testing of the Y outputs and to ground during testing of the Z outputs.
4,. The A input is connected to ground during the testing of the Y outputs and to Vee during the testing ,of the Z inputs,
4-220
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
SN75151, SN75153
QUAD DIFFERENTIAL LINE DRIVERS WITH 3·STATE OUTPUTS
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
80
70
E 60
!!! 50
$
:::I
«
A
I
c
ii
Q.
70
A Inputs Grounde0V
..
>
80
#
,/
2
"Qj
3
4
5
6
7
vee-Supply Voltage-V
FIGURE 13
FIGURE 12
NOTES:
fl V
V
./
/'
3. The A input is connected to Vee during the testing of the Y outputs and to ground during testing of the Z outputs.
4. The A input is connected to ground during the testing of the Y outputs and to Vee during the testing of the Z inputs.
8
(.)
Q)
a:
-~
Q)
>
"a:::
Q
Q)
c
:::i
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4·221
r-
5"
CD
...C
...enCD
<"
--
:tJ
CD
(")
CD
<"
...enCD
4-222
SN55152, SN75152
DUAL LINE RECEIVERS
01114, AUGUST 1972-REVISEO SEPTEMBER 19B6
SN55152 ... J PACKAGE
SN75152 ... 0, J, OR N PACKAGE
•
Meets Specifications of EIA RS-232-C or
MIL-STD-188Ct
•
Dual Differential Receiver with Independent
Strobes
(TOP VIEW)
•
Common-Mode Input Voltage
Range ... ±25 V
•
Differential Input Capability with One Input
Grounded . , , ± 25 V
•
HYST CONTt
lOUT
lSTRB
lHYST ADJ
l1N-
•
Input Hysteresis (Double Thresholds)
Remain Approximately Fixed for Power
Supply and/or Temperature Variations
VCC-
SN55152 ... FK PACKAGE
+ 12 V
Standard Supply Voltages ...
and -12 V
2RT
21N+
lRT
l(N+
GND
Continuously Adjustable Hysteresis with
External Resistors
•
VCC+
20UT
2STRB
2HYST ADJ
2(N-
(TOP VIEW)
II...
II)
CI)
>
'G)
description
The SN55152 and SN75152 are dual differential
line receivers designed to meet the requirements
of EIA Standard RS-232-C or MIL-STD-188
interfaces, A single control, HYST CONT. sets
the input hysteresis for the required operation.
An added feature is the capability of adjusting
the hysteresis to any voltage between ±0.3 volt
typical and ± 5 volts typical by means of the
hysteresis adjust terminals. 1HYST ADJ and
2HYST ADJ. making the SN55152 and
SN75152 useful for a wide variety of line
receiver and Schmitt trigger applications. The
large common-mode input voltage range and
differential input voltage (± 25 volts) give the
circuit added versatility. The SN55152 and
SN75152 are designed for operation from
standard ± 12-volt supplies with ± 10%
variation. Each receiver has an output strobe that
is TTL compatible.
3
1 HYST ADJ
NC
l1N-
2
1 20 19
(.)
CI)
4
18
5
6
17
2STRB
2HYST ADJ
16
NC
-...
15
21N2RT
';:
14
a:
I I)
CI)
>
C
9 10111213
CI)
+ 0
U
1+
Z
Z
UZ
Z
;:: (!)
c
:::i
~N
NC ~ No internal connection
The SN55152 is characterized for operation over
the full military temperature range of - 55 DC to
125°C. The SN75152 is characterized for
operation from 0 DC to 70 °C.
t To meet the specifications of EIA Standard RS-232-C, connect the hysteresis control pin, HYST CONT, to VCC _. Also, connect termination
resistor pin 1 RT to inverting input 11N -, and termination resistor pin 2RT to inverting input 21N -. To meet the specifications of
MIL-STO-188, leave HYST CO NT, 1RT. and 2RT open.
PRODUCTION DATA do•• monls .ontain information
currant 8. of publication data. Products conform to
specifications per the terms of Taxas Instruments
:~~::~~i~8t::I~~i ~~:~~i:r :'~O::::::A::s~S
not
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-223
SN55152, SN15152
DUAL LINE RECEIVERS
Definition of logic levels:
FUNCTION TABLE
(EACH RECEIVER)
UNE INPUT
STROBE
OUTPUT
H
H
H
L
H
L
H
L
X
•
For the strobe: H (high) is any voltage between
VIH min and Vee.
L (low) is any voltage between
ground and VIL max.
For the line input: H (high) is any differential input
voltage (VIO):(: more positive
than Vr _, once the level of
Vr + has been reached.
L (low) is any differential input
voltage (VIO):(: more negative
than Vr +, onc.e the level of
Vr - has been reached.
X (irrelevant) is any input voltage
permitted by maximum ratings.
t Differential input voltages IVT and ViOl are at the non inverting
input terminal IN + with respect to the inverting input terminal
IN-.
logic symbol t
logic diagram (positive logic)
1STRB
1HYST ADJ
l1N+
13)
(4)
m
(6)
1RT
l1NHYST CONT
21N+
2RT
21N2HYSTADJ
2STRB
IS)
(1)
(10)
1111
(121
(131
(141
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe PUb.lication 617-12.
Pin numbers shown are for D. J, and N packages.
4-224
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 76265
SN55152, SN75152
DUAL LINE RECEIVERS
schematic (each receiver)
;--,,-; ---,
STROBE
(3. 14J
10 kG
I
OUTPUT
(2,lS}
10 kU
vcc+
I
3 kO
I
,
,
I
10 kU
I,
10 kO
I
I
I
,
L _____ ..J
1--<~______----<~8_kO..---t-__,-15,-,'_2-,--1 ::~~~~~~
, kO
r-----~-------J-:::::: II
.
1--- --- ---181
I
I
-l
GND
Q)
I
I
I
I
22 kO
:
511
n
2 kO
L-______________
511
n
I
I
C
I
1.1 kO
~--------------~--r_~'--~_t~----~--4-~~19J
I
~ L ______V~~._J
(4,13,
TO OTHER
HYSTERESIS RECEIVER
ADJUST
Portions of circuit within dashed lines are common to both receivers.
Resistor values shown are nominal.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
(.)
Q)
a:
--.
I
3.3 kn
(1) HYSTERESIS I
....----+--'-------+-~~-+..;.. CONTROL I
n
>
"Qj
I
,I
511
1/1
4-225
1/1
Q)
>
";:
Q)
r:
:::i
•
SN55152, SN75152
DUAL LINE RECEIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SN55152
Supply voltage, VCC + (see Note 11
Supply voltage, VCC (see Note 11
Voltage at any line input with respect to other line input, ground, or RT
15
-15
±25
±25
RT terminal voltage (see Note 11
o package
Continuous total dissipation at (or belowr
25·C free-air temperature (see Note 21
free~air
1375
1375
1025
1150
-55 to 125
o to 70
-65 to 150
temperature range
I
60 seconds I
Lead temperature 1,6 mm (1116 inchl from case for
Lead temperature 1,6 mm (1116 inchl from case for 10 seconds
±25
950
FK package
Storage temperature range
Case temperature for 60 seconds
±25
J package
N package
Operating
SN75152
15
-15
FK package
J package
I0
or N package
-65 to 150
260
300
UNIT
V
V
V
V
mW
·C
·C
·c
300
260
·C
·C
NOTES: 1. These voltage values are with respect to network ground terminal.
2. For operation above 25·C free-air temperature, refer to Dissipation Derating Curves in Appendix A. hi the J package, SN55152
chips are alloy mounted and SN75152 chips are glass mounted. In the N package, use the 9.2-mWI·C curve for these devices.
recommended operating conditions
SN75152
SN55152
NOM MAX
MIN NOM MAX·
13.2
12
13.2
10.8
12
-12 -13.2 -10.8
-12 -13.2
-10.8
2
2
0.8
0.8
-55
125
70
0
MIN
10.8
Supply voltage, VCC +
Supply voltage, VCCHigh-level input voltage at strobe, VIHfS\
Low-level input voltage at strobe, VIL(SI
Operating free-air temperature, T A
4-226
.
TEXAS"
INSTRUMENTS
POST OFFICE BOX 665012 • OALLAS, TeXAS 75265
UNIT
V
V
V
V
·C
electrical characteristics over operating free-air temperature range, Vcc +
otherwise noted)
TEST
PARAMETER
1
See
VT-
Negative-going threshold voltage
VT+
Positive-going threshold voltage
VT-
Negative-going threshold voltage
VOH
High-level output voltage
1 and 2
1 and 2
;~~
~~~
c:1'1~
l'1'1
~z ..
~ ~,..
1;;
...
5
MIN
TYP* MAX
(SEE NOTE 3)
Low-level output voltage
VOL
1 and 2
Input current into strobe at
II
MIL-STO-188 Conditions
Figure 8
2
3
maximum strobe voltage
= VT + max,
= -500 pA
= VT _ min,
10H = -500 ~A
VIO = VT _ min,
10L = 6.4 rnA
.
_ ..
1
1
----
2.2
-3
-2.2
3
-1.5
3
4.1
6
3
4.1
6
0
0.15
0.4
V
V
V,
2 V,
V
1
rnA
=
2.4 V
30
-0.5
80
-1.5
rnA
TA
Supply
current
from
V CC
_- -----
2 V,
1.5
V
0.1
4
Supply current from V CC +
-0.3 -0.03
5.5 V
rl
--
-0.5
V
=
IVlol = 3 Vto 25 V,
Rr connected to inverting line input,
-
'55152
UNIT
VUstrobe)
4
--
-0.1
=
Input resistance
ICC+
-0.3
VUstrobe)
VUstrobel
--'kc -
-0.5
= 0.8
VUstrobe) = 0.4 V
IVlol - 0 V to 25 V, RT open,
5
'75152
VUstrobe)
3
6
0.5
=
3
Open-circuit input voltage
0.5
0.3
VUstrobe)
Low-level strobe current
Short-circuit output current
0.3
0.03
VIO
High-level strobe current
VUopenl
lOS
0.1
'55152
10H
VIO
IlL
EIA RS-232-C
'75152
EIA RS-232-C Conditions
IIH
MIL-STO-188
-12V ± 10% (unless
TEST CONOITIONS t
FIGURE
Positive-going threshold voltage
VT+
~
~-
f:iz
12V ±10%,VCC-
=
TA - 25°C
pA
6
9
3
5
7
+1
-1.9
±2
-4
rnA
10
-7
16
rnA
-13
rnA
kll
25°C
=3V
VIO = -3 V,
"io =_ -3 V,_
VIO
VI/strobel
-
=
2.4 V
_ _II'LIstrobel =_2.4Y _ _
-
V
t Differential input voltages (VT and Viol are at the noninverting line input terminal with respect to tha inverting line input terminal.
*Typical values are at VCC+ = 12 V, VCC- = -12 V, TA = 25°C.
NOTE 3: The algebraic convention, in which the less positive (more negativellimit is designated as minimum, is used in this data sheet for threshold levels only, e.g.,
when -0.1 V is the maximum, the minimum limit is a more negative voltage.
switching characteristics, VCC+ = 12 V, VCC-
-12 V, TA
CI
Cfn
~2
25°C
_ U'I
r-U'I
2-
PARAMETER
tpLH
tpHL
Propagation delay time, low-to-high-Ievel output
Propagation delay time, high-to-Iow-Ievel output
TEST
FIGURE
7
mU'l
TEST CONomONS
MIN
TVP
CL = 15pF
MAX
40
60
UNIT
N
::a °
mfn
ns
"2
!!!""'"
'G)
I--:: -----1
r
(,)
G)
-...
a::
I I)
I
I
HYST
CONT
G)
>
';:
I
C
I
I
I
INV
L ____
'I = II VIO
llil
G)
OPEN
c
::i
HYST
I
.B.£2:!.--~--I~~
OPEN
OPEN
=
FIGURE 4
VCC+
r
I
Vcc-
J------------,
NON
I INV -
HYST
CONT
I
TO OTHER
RECEIVER
I
OPEN
I ~
I
I
II
OPEN
FIGURE 5
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DAl.LAS. TEXAS 76266
4-229
SN55152,· SN75152
DUAL LINE RECEIVERS
PARAMETER MEASUREMENT INFORMATION
J--- :E~ ______L,
Vcc+
r
Vcc-
HYST
CONT
'NONIINV
IINV
.L
---
TO OTHER
RECEIVER
,
I
,
I
I
HYST
ADJ
S
GND.
--------I-~
OPEN
FIGURE 6
rS'
CD
VCC+
.
C
OPEN
VCC-
r -L----------L,
HYST
I
~'
U;
~
CD
n
I
CONT
I
INPUT --+---4~""""..t
I
CD
..
~'
D-~I!-""- OUTPUT
OPEN--:4~--r-J T
fI)
ADJ
GND!
CL = 15 pF
(See Note B)
TEST CIRCUIT
:
Jo
14-
s 10 ns-+l
INPUT
10%
tpLH
OUTPUT
~
-+I
I I
~9:::0:'!:%~-~9~0~%..
~1-
I
I
I
OV
:
0 V
'1.5V
5V
I
:
~
s 10 ns
- ---
10%
-5 V
~
'4
tPHL
1.5V\C-- VOH
_ _ _",.
~VOL
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR s 1 MHz, duty cycle = 50%, Zout
B. CL includes probe and jig capacitance.
FIGURE 7. PROPAGATION DELAY TIMES
4-230
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 6550.12 • DALLAS, TeXAS 75265
~
50 n.
SN55152, SN75152
DUAL LINE RECEIVERS
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
5
>
I
4
VCC+ = 12 V
VCC- = -12 V
TA = 25°C
EIA RS-232-C CONOITION
(See Figure 21
J
CII
.::
....
"
::==
~
=3
CD
.-
0
>
:::I
VT-
Q.
:::I
0
I
0
>
VT~
VTI
MIL-STD-188
CONDITION
(See Figure 11
2
1
VT+
.t---
a
...
",
Ql
• l---
IV! f-I-
>
"a;
.- ...
(J
0 ~,
-25
Ql
-4
-3
-2
o
-1
2
3
4
25
a:
",
Ql
VID-DIFFERENTIAL INPUT VOLTAGE-V
>
";:
C
FIGURE 8
Ql
THRESHOLD VOLTAGE VARIATION
vs
POSITIVE SUPPLY VOLTAGE
>
20
I
15
·c
10
J
5
E
.!
~
o
>
'0
'0
.t:.
!!
~
I
~
C
:::::i
VCC- = -12 V
TA = 25°C
JIA
RS-~32-C 'CONDlTION
(See Figure 21
1\
o
-V
-5
-~ -
V
-="
MIL-STD-188 CONDITION
(See Figure 11
-10
-15
-20
10.5
11
11.5
12
12.5
13
13.5
VCC+ -Positive Supply Voltage-V
FIGURE 9
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-231
SN55152, SN75152
DUAL LINE RECEIVERS
TYPICAL CHARACTERISTICS
THRESHOLD VOLTAGE VARIATION
vs
NEGATIVE POWER SUPPLY
>
E
I
..
c
.2
.!
(II
>
(II
1:1)
20
VCC+ = 12 V
15 TA = 25°C,
EIA RS-232-C_
10
CONDITION
(See Figure 21/
5
(II
-a>
0
V ~
V
~ -5
.::
,...
S·
CD
...C~.
2! -10
.::
~
b"
L-r-\
MIL-S.fo-188
CONDITION
(See Figure 11
/
I-
~
/
-15
/
-20
-10.5 -11 -11.5 -12 -12.5 -13 -13.5
VCC - - Negative Supply Voltage - V
--iil
:::a
FIGURE 10
CD
(')
THRESHOLD VOLTAGE
vs
HYSTERESIS ADJUST RESISTANCE
CD
<'
CD
...
til
±6
>
VCC+ = 12 V
VCC- = -12 V
RT open
TA = 25°C
\
±5
\
I
GI
:i!'
~
±4
1\
\
r--....
'-....
o
o
0.5
...............
1.5
r--
2
2.5
3
Radjt -HYSTERESIS ADJUST RESISTANCE-kG
t Radj is connected between Hysteresis Adjust terminal and Vee _.
FIGURE 11
4-232
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN55152. SN75152
DUAL LINE RECEIVERS
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
80
..
c
I
II
E
70
tP~L
60
j::
..
>- 50
III
Q
c
.g
III
tPI.H
40
III
...
30
DI
III
Q,
S!
IL
I/)
20 VCC+ = 12 V
VCC- = -12 V
10 CL=15pF
See Figure 7 I
o
o
10
20
30
CD
>
'i)
(,)
-...
CD
40
50
60
TA - Free-Air Temperature -
70
°c
FIGURE 12
80
a:
I /)
CD
>.
'0::
C
TYPICAL APPLICATIONS
CD
C
::;
Some typical applications of the SN55152 and SN75152 are as follows:
•
•
•
•
MIL-STD-188 Interface Receiver
EIA RS-232-C Interface Receiver
Single-Ended Line Receiver
. Differential Line Receiver
•
•
High-Noise-Immunity Line Receiver
•
•
•
•
•
High-Voltage-Logic-to-TTL Translator
Schmitt Trigger
MOS-to-TTL Converter
Pulse Generator
Threshold Detector
Pulse Shaper
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
4-233
SN55152. SN15152
DUAL LINE RECEIVERS
TYPICAL APPLICATIONS
:'L_:-~
VCC+ HYST
NON. CONT
I INV
____~r,
I
TO OTHER
RECEIVER
VCC.
INPUT
OPEN
I
I
I
I
_-'V\""'"
I
TTL-COMPATIBLE
OUTPUT
I
AOJ
S
GNO!
OP:-~~:~-l-"
FIGURE 13. MIL-STD-188 SINGLE-ENDED LINE RECEIVER
C
:::I
+12V
CD
:::!,
<
til
CD
~cc+
::D
I NON.
IINV
CD
(')
-12V
,.J___________,
C
HYST
CONT
VCC-I
I
TO OTHER
RECEIVER
INPUT
I
CD
<'CD
TTL-COMPATIBLE
OUTPUT
I
til
GN~
S
STR:~-r
OPEN
NORMAL OPERATION
+12 V
OPEN
r. --1 kSl
VCC+
'NON.
IINV
-12 V
______
HYST
CONT
J_,
VCCTO OTHER
RECEIVER
I
I
I
INPUT
I
I TTL-COMPATIBLE
I
S
200 Sl
OPEN
OUTPUT
GN~
STR~:-r
FAIL-SAFE OPERATION
FIGURE 14. EIA RS-232-C SINGLE-ENDED RECEIVER
4-234
.
TEXAS'"
INSTRUMENTS
POST OFFICE BOX 865012 • DALLAS, TEXAS 75265
SN55152, SN75152
DUAL LINE RECEIVERS
TYPICAL APPLICATIONS
12 V
HYSTERESIS
CONTROL
125 G
3.9 G
A ........----L.....---......
-vzsN75i52RG63B/U ....-iI-~_-.........-f",J
CABLE
TO OTHER
RECEIVER
-j
I
I
I
.....
B~----L-r-
I
6.B kG
...._ _.J
TTL-COMPATIBLE
OUTPUT
::-~-I_N_~J
en
~
CD
-12 V
>
'i
FIGURE 15. SINGLE-ENDED TRANSMITTER WITH DRIVER "OR" CAPABILITY
AND RECEIVER WITH ADJUSTABLE NOISE IMMUNITY
u
CD
a:
en
12 V
5V
~
CD
>
1 kG
'a:::;
560 G
C
CD
c
::::i
JTTL·COMPATIBLE
---'--r
I OUTPUT
Frequency to 0.5 MHz
Common-Mode Voltage ... -12 V to
+ 10 V
t The 1N4444 diodes are required only for negative common-mode protection at the driver outputs.
FIGURE 16. BALANCED LINE OPERATION WITH HIGH COMMON-MODE-VOLTAGE CAPABILITY
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 76266
4-235
r-
S'
CD
...
...
C
~'
til
.......
:xl
CD
(")
CD
:a'
...
CD
til
4-236
SN55154, SN75154
QUADRUPLE LINE RECEIVERS
0899, NOVEMBER 1970-REVISED SEPTEMBER 1986
SN55154 .. ,J PACKAGE
SN75154 ... D, J, OR N PACKAGE
•
Satisfies Requirements of EIA Standard
RS-232-C
•
Input Resistance , , . 3 kO to 7 kO over Full
RS-232-C Voltage Range
•
Input Threshold Adjustable to Meet
"Fail-Safe" Requirements Without Using
External Components
(TOP VIEW)
3T
2T
VCC2
VCC1
4T
1Y
2Y
3Y
4Y
1T
1A
2A
3A
4A
GND
•
Built-In Hysteresis for Increased Noise
Immunity
•
Inverting Output Compatible with TTL
•
Output with Active Pull-Up for Symmetrical
Switching Speeds
SN55154 ... FK PACKAGE
(TOP VIEW)
•
Standard Supply Voltages. , , 5 V or 12 V
UU
f-f-UUU
Rlt
II
.
N~
NMZ»
description
3
The SN55154 and SN75154 are monolithic
Low-Power Schottky line receivers designed to
satisfy the requirements of the standard
interface between data terminal equipment and
data communication equipment as defined by
EIA standard RS-232-C, Other applications are
for relatively short, single-line, point-to-point
data transmission and for level translators,
Operation is normally from a single five-volt
supply; however, a built-in option allows
operation from a 12-volt supply without the use
of additional components. The output is
compatible with most TTL circuits when either
supply voltage is used,
1T
1A
NC
2A
3A
2
fI)
1 2019
4
18
5
17
6
16
7
15
8
14
CD
>
'iii
u
1Y
-.
CD
Ill:
f I)
9 1011 1213
...
<{
Cl U +-
CD
>
>-
'i:
ZZ'f"'"q-
(:J
a:
C
CD
I:
NC No internal connection
t For function of R 1, see schematic
:::::i
In normal operation, the threshold-control terminals are connected to the VeC1 terminal, even if power
is being supplied via the alternate VeC2 terminal. This provides a wide hysteresis loop, which is the
difference between the positive-going and negative-going threshold voltages, See typical characteristics,
In this mode of operation, if the input voltage goes to zero, the output voltage will remain at the low or
high level as determined by the previous input.
For fail-safe operation, the threshold-control terminals are open. This reduces the hysteresis loop by causing
the negative-going threshold voltage to be above zero. The positive-going threshold voltage remains above
zero as it is unaffected by the disposition of the threshold terminals. In the fail-safe mode, if the input
voltage goes to zero or an open-circuit condition, the output will go to the high level regardless of the
previous input condition,
The SN55154 is characterized for operation over the full military temperature range of - 55°C to 125°C.
The SN75154 is characterized for operation from ooC to 70°C.
PRODUCTION DATA documenls contain informBtion
current BS 01 publication dote, Praducts conform to
specifications par the terms of TaXIS Instruments
:=~~i~lt::I~Ji ~:~::i:r lI~o:=~~::~
not
Copyright @ 1985, Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 656012 • DALL.AS. TEXAS 75266
4-237
SN55154, SN75154
QUADRUPLE LINE RECEIVERS
logic symbol t
logic diagram
1A~1V
1T~ V
2A~2V
2T~
V.·
3A~3V
3T~ V·
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
4A~4V
4T~ V·
Pin numbers shown are for D, J, and N packages.
r-
5'
schematic
COMMON TO 4 RECEIVERS
CD
..::C
r------,
I
I
VCC2
(See Not. 11
CD
-
3.2 kl1
I
iil
:lJ
CD
n
CD
VCC1
til
GND
.
I
IL_______ .JI
R1 ________~1~5Mkl1~
<'
CD
I
I
I
I
-----:..1--....
1 OF 4 RECEIVERS
THRESHOLD
CONTROL
r---- ----------l
I
I
I
1.6
1.6
I
5 kl1
i
kl1
kl1
20011
..."
I
I
I
INPUT
I
I
OUTPUT
I
I
14.2 kn
I
2.7 kl1
IL
:
I
__________________
I
~
Component values shown are nominal.
,}, .. . Substrate
NOT~ 1: When VCC1 is used, VCC2 may be left open or shorted to VCC1. When VCC2 is used, VCC1 must be left open or connected
to the threshold control pins.
4-238
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
SN55154. SN75154
QUADRUPLE LINE RECEIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SN55154
Normal supply voltage, VCC1 Isee Note 2)
Alternate supply voltage, VCC2
Input voltage
SN75154
UNIT
7
7
V
14
14
V
±25
±25
V
D package
950
Continuous total dissipation at (or below)
FK package
1375
25°C free-air temperature (see Note 3)
J package
1375
mW
1025
N package
1150
Operating free-air temperature range
-55 to 125
o to 70
DC
Storage temperature range
-65 to 150
-65 to 150
DC
Case temperature for 60 seconds: FK package
260
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package
300
DC
Lead temperature 1,6 mm 11/16 inch) from case for 10 seconds: D or N package
300
DC
260
DC
recommended operating conditions
SN55154
Normal supply voltage, VCC1
Alternate supply voltage, VCC2
SN75154
(/)
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
10.8
12
12
UNIT
13.2
10.8
13.2
V
3
15
3
15
V
Low-level input voltage, VIL Isee Note 4)
15
3
15
3
V
High-level output current, IOH
-400
-400
p.A
Low-level output current, IOL
16
16
mA
DC
-55
125
0
70
CD
>
'03
V
High-level input voltage, VIH Isee Note 4)
Operating free-air temperature, T A
II
...
t,)
CD
a:
--...
( /)
CD
>
';::
C
NOTES:
2. Voltage values are with respect to network ground terminal.
3. For operation above 25°C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the J package, SN55154
chips are alloy mounted and SN75154 chips are glass mounted. In the N package, use the 9.2·mWI °C curve for these devices.
4. The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet
for logic and threshold levels only, e.g., when 0 V is the maximum, the minimum limit is a more negative voltage.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS, TEXAS 75265
CD
c::
:::;
4-239
SN55154, SN75154
QUADRUPLE LINE RECEIVERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
TEST
PARAMETER
VT+
VT-
Positive-going
Normal operation
threshold voltage
Negative-going
Fail-safe operation
Normal operation
threshold voltage
Fail-safe operation
High-level output voltage
1
10H = -400 ~A
VOL
Low-level output voltage
1
10L - 16 mA
aVI - -25 V to
lOS
~
CD
2
Short-circuit output current t
ICC1
Supply current from VCC1
ICC2
Supply current from VCC2
0.8
0.8
2.2
3
2.2
3
1.1
3
0
0.8
0.8
1.4
3
3.3
6
0
0.8
2.2
2.4
3.5
0.29
14V
5
aVI = -14Vto -3V
3
3
aVI- -3Vto3V
3
6
aVI = 3 V to 14 V
3
5
5
V
V
V
0.4
7
7
8
7
7
aVI = 14 V to 25 V
3
5
3
11- 0
0
0.2
2
4
VCC1 = 5.5 V, VI = -5 V
-10
-20
-40
5
V
VCC1 ~ 5.5 V, TA = 25°C
20
35
VCC2 - 13.2 V,TA - 25°C
23
40
TYP
MAX
V
kll
V
mA
mA
tNot more than one output should be shorted at a time .
tAli typical values are at VCC1 = 5 V, TA = 25°C.
switching characteristics. VeC1
n
1
Fail-safe operation
Input resistance
CD
til
Normal operation
VOH
Vl(open) Open-circuit input voltage
...C
CD
...<'
1
Hysteresis (VT + - VT _I
r-
3'
1
Vhys
ri
MIN TYP* MAX
UNIT
(SEE NOTE 41
TEST CONDITIONS
FIGURE
-= 5 V. TA
CD
<'
CD
...
til
TEST
PARAMETER
tpLH
Propagation delay time, low-to-high-Ievel output
tpHL
Propagation delay time, high-to-Iow-Ievel output
tTLH
Transition time, low-to-high-Ievel output
tTHL
Transition time, high-to-Iow-Ievel output
MIN
TEST CONDITIONS
FIGURE
6
CL = 50 pF,
RL=39011
UNIT
11
ns
8
7
ns
2.2
ns
ns
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE vs INPUT VOLTAGE
:1-VCC1 =5V
TA=25·C
4
..
>I
3
~
0
>
;
:/--
NORMAL , ....
OPERATI1ON-
FAILSAFE."
OPERATIOj
:/--
2
~
See Note 5
VT_
VT_
VT+
rs--
0
I
0
>
0
-25
-3
-2
-1
0
1
2
3
4
~~
25
VI-Input Voltage-V
NOTE 5: For normal operation, the threshold controls are connectd ',to VCe1. For fail-safe operation, the threshold controls are open.
4-240
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN55154, SN75154
QUADRUPLE LINE RECEIVERS
PARAMETER MEASUREMENT INFORMATION
doc test circuits t
TEST TABLE
MEASURE
A
T
Y
VCCl
(PIN 15)
Open-circuit input
VOH
Open
Open
IOH
4.5 V
Open
(fail safe)
VOH
Open
Open
IOH
10.8 V
VT+ min,
VT _ min (fail safe)
VOH
O.B V
Open
IOH
Open
5.5 V
VOH
0.8 V
Open
IOH
Open
13.2 V
VOH
Note A
Pin 15
IOH
5.5 V and T
Open
VOH
Note A
-3 V
Pin 15
IOH
T
13.2 V
Pin 15
IOH
5.5 V and T
Open
3V
Pin 15
IOH
T
13.2 V
TEST
VT + min (normal!
VCC2
(PIN 16)
Open
VIL max,
VT _ min (normal!
VOH
VOH
VIH min, VT + max,
VT _ max (fail safel
VOL
3V
Open
IOL
4.5 V
Open
VOL
3V
Open
IOL
Open
10.8 V
VIH min, VT + max
(normal!
VOL
3V
Pin 15
IOL
4.5 V and T
Open
VOL
VOL
3V
Pin 15
IOL
T
10.8 V
Note B
Pin 15
IOL
5.5 V and T
Open
VOL
Note B
Pin 15
IOL
T
13.2 V
VT _ max (normal!
~
OPEN
01D.8V
OPEN
I
()
-.
a:
9
-t,., {
L..----r----J
~I
~
li l ~
IA
CD
"a;
en
CD
>
013.2V
OPEN 0
4.5 V
-
en
>
CD
NOTES: A. Momentarily apply -5 V, then 0.8 V.
B. Momentarily apply 5 V, then ground.
5.5VO
II.
-VCC1- VCC2 -
.a
GND
~OH
yl
"~
C
CD
c
:::i
IOL
~-=-
I
V~L~ VOH
FIGURE 1. VIH. VIL. VT+. VT-. VOH. VOL
t Arrows indicate actual direction of current flow. Current into a terminal is a positive value.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265
4-241
SN55154. SN75154
QUADRUPLE LINE RECEIVERS
PARAMETER MEASUREMENT INFORMATION
d-c test circuits t (continued)
TEST TABLE
T
Open
Open
Open
Pin 15
~_--'-01--
II
OPEN
VCCl
VCC2
IPiN 15)
IPIN 18)
5V
Open
Open
Open
Open
Open
GND
. Open
T and 5 V
GND
GND
Open
Open
Pin 15
Pin 15
Pin 15
Open
Open
12 V
T
T
T
12 V
GND
GND
Open
FIGURE 2. 'I
Co
:::s
CD
5.5 V
C
~~--1C>--13.2
V
TEst TABLE
:I.
<
CD
...
f
-
VCCl
VCC2
IPiN 15)
IPIN 18)
Pin 15
Open
5.5 V
5.5 V
Open
Pin 15
T
Open
Open
13.2 V
13.2 V
T
OPEN
_____ .1,
In
VeCl
VeC2
Rl
Open
I
~~--y=+- OPEN
~
~.
;;;
FIGURE 3. Vl(open)
":'::/"---1;,=~:v
r5V
-5V
IA
T
~_·1
__ l_ J ---,
Veel
VCC2
L.. _ _ _ _
GND
~
Each output is tasted separately.
FIGURE 5. ICC
t Arrows indicate actual direction of current flow. Current into a terminal is a positive value.
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 865012 • DALLAS. TEXAS 15285
yl
I
_ _ _ _ ..J
All four line receivers are tested simultaneously.
FIGURE 4. lOS
4-242
Rl
11
OPEN
SN55154, SN75154
QUADRUPLE LINE RECEIVERS
PARAMETER MEASUREMENT INFORMATION
INPUT
OUTPUT
5V
OPEN
rI
PULSE
GENERATOR
(See Note Al
L J-,I
- -VCC1- -VCC2 -
T
A
OPEN
rr
RL~390n
R1
(See Nota C)
~_____y~. .~~-.~~+-,
IL.. _ _ _ _ ..,.
GND_ _ _ _ _ ..JI
CLz50pF
'*
~
(Sao Noto B)
':'
TEST CIRCUIT
'--*-
~ 10 ±2 ns
I
I
10 ±2 ns
I
bf~~~0%~-----"""9""0%~, - : INPUT
10%}/
--....;.;;~.y-
-
-
-
-
-
-
-
5V
•
~
~
"CD
II
=av\i10%
I
I
I
~ tpHL ~
\l!~V
12V
iI
tTHL---I
1.5V I
1_0.8 V
I
0.8 V
I
I
----I
I-
(J
G)
-...
a:
U)
14-
G)
I
u
2V
OV
-5 V
0
--.j tpLH
I
OUTPUT
-
>
";:
VOH
C
-I------VOL
c:
::i
:
G)
I
I
f4-lTLH
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zout = 5011. tw = 200 ns. duty cycle
B. CL includes probe and jig capacitance.
C. All diodes are 1N3064.
s 20%.
FIGURE 6. SWITCHING TIMES
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
4-243
c::
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CD
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CD
4-244
8N15155
ADVANCE
INFORMATION
LINE DRIVER AND RECEIVER
02951, JULY 1986
•
Meets EIA Standard RS-232-C
•
10-mA Current Limited Output
•
Wide Range of Supply
Voltage ... VCC - 4.5 V to 15 V
•
Low Power ... 130 mW
..
Built-In 5-Volt Regulator
•
Response Control Provides:
Input Threshold Shifting
Input Noise Filtering
DB
D, JG, OR P PACKAGE
(TOP VIEW)
Vcc-
DA
RY
GND
2
3
4
7
6
5
vcc+
DY
RTC
RA
logic symbol t
I>
DA (2)
•
Power-Off Output Resistance ... 300 !l Typ
•
Driver Input TTL Compatible
RA (5)
description
The SN75155 is a monolithic line driver and
receiver that is designed to satisfy the
requirements of the standard interface between
data
terminal
equipment
and
data
communication equipment as defined by EIA
standard RS-232-C. A Response Control input
is provided for the receiver. A resistor or a
resistor and a bias voltage can be connected
between the response control input and ground
to provide noise filtering. The driver used is
similar to the SN75188. The receiver used is
similar to the SN75189A.
II
...
I>
.II
RTC
II)
CD
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12
>
"iii
(.)
-...
CD
a:
logic diagram
I I)
Vcc-
....;(....;1)"-_ _ _ _-,
VCC+
....:.;;=----...--.
CD
>
";:
C
CD
DA
c
....;;;;'----+--i
::::i
The SN75155 is characterized for operation from
ooe to 70°C.
RA
Z
RTe
0
i=
«
:E
a:
0
u.
~
w
(J
z
«
>
c
«
ADVANCE INfORMATION do.uments .ontei.
~':!;=::':;h=
Jrz:.~~~'6:::=':'
~ete and other opacificatio.. a....bject to ohange
without Rotica.
Copyright @) 1986, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-245
ADVANCE
INFORMATION
SN75155
LINE DRIVER AND RECEIVER
schematic
DA~I~21~
__________________________________________,
vcc+~18~1~--
•
__~____~______________________________~____~__~~__,
RA~15~'-+____-1_3~.5~k_n~~~~
GND~14~1-4____~~____~+-~
__~~~~~~__~~~
RTC~16~1______________~
r-
:i'
CD
...c
<"CD...
--
*-____~__________~__*-__~~____~~
VCC_~I~l'____________~~________
1/1
:lJ
CD
All resistor values shown are nominal.
(')
CD
...<"
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC + (see Note 1) .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 V
Supply voltage, VCC _ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ~ 15 V
Input voltage range:
Driver.......................................... - 1 5 V to 15 V
Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 30 V to 30 V
Output voltage range (Driver) .......................................... - 15 V to 15 V
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
D package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 725 mW
JG package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 825 mW
P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1000 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds, JG package. . . . . . . . . . .. 300°C
Case temperature for 60 seconds, FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds, D or P package . . . . . . . .. 260°C
CD
1/1
l>
C
<
l>
2:
n
m
2:
NOTES:
."
o
1. All voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, refer to Dissipation Derating Table. In the JG package, SN75155 chips are
glass mounted.
DISSIPATION DERATING TABLE
:l:J
s:
l>
-4
o
2:
4-246
PACKAGE
TA - 25°C
POWER RATING
DERATING FACTOR
ABOVE TA
TA - 70°C
POWER RATING
0
725 mW
5.8 mW/oC
25°C
464 mW
JG
825 mW
6.6 mW/oC
25°C
528 mW
P
1000 mW
8.0 mW/oC
25°C
640 mW
TEXAS
-1.!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
ADVANCE
INFORMATION
SN75155
LINE DRIVER AND RECEIVER
recommended operating conditions
PARAMETERS
MIN
NOM
MAX
Supply voltage, Vcc +
4.5
12
15
V
Supply voltage, VCC-
-4.5
-12
-15
V
±15
V
25
V
V
Input voltage, driver, VIIO)
Input voltage, receiver, VIIR)
-25
High-level input voltage, driver, VIH
2
Low-level input voltage, driver, VIL
O.B
Response control current
0
Operating free-air temperature, T A
V
24
rnA
rnA
70
°c
±5.5
Output current, receiver, IO(R)
UNIT
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
total device
PARAMETERS
ICtH+
ICCL+
High-level supply current
Low-level supply current
Supply current
V,
V,
VCC+ - 12 V,
VCC+ = 5 V,
VCC+
=9
V,
ICCH-
High-level supply current
VCC+
Low-level supply current
=
9 V,
VCC+ - 5 V,
VCC+ = 9 V,
VCC+
=
12 V,
VCC+ - 5 V,
VCC+ = 9 V,
VCC+
t All typical values are at T A
=5
=9
VCC+ - 12 V,
VCC+ = 5 V,
ICC+
ICCL-
Typt
MAX
6.3
B.1
9.1
11.9
10.4
14
V,
2.5
3.4
VIIR) = 0.6 V,
Output open
3.7
5.1
4.1
5.6
4.8
6.4
6.7
-2.4
9.1
-5 V,
VI(OI
VIIO) - 2 V,
-3.1
-9 V,
VIIR)
=
-3.9
-4.9
-4.8
-6.1
TEST CONDITIONS
VCC+
VCC+
=
12 V,
VCCVCC-
=
=
VCC- VCCVCC-
=
=
VCC- VCCVCCVCCVCC-
=
=
VCC- VCCVCC-
VIIO)
-9 V,
VI(R)
Output open
-12 V,
-5 V,
-9 V,
-12 V,
= 0,
= 0,
VCC- -
=
=
MIN
= 2 V,
= 2.3 V,
-5 V,
VIIO)
VIIR)
= 0.8
= 2.3
=0
V,
2.3 V,
-12 V,
Output open
-5 V,
VI(O) - 0.8 V,
-9 V,
VIIR) = 0.6 V,
Output open
-12 V,
UNIT
rnA
rnA
-0.4
.
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rnA
rnA
CD
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-0~2 -0.35
-0.25
•
rnA
-0.27 -0.45
= 25°C.
z
o
~
~
a::
oLL
Z
w
CJ
Z
~
C
t All typical values are at T A ~ 25 DC.
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CD
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en
PARAMETER MEASUREMENT INFORMATION
CD
>
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iloH t
i
RESPONSE
CONTROL
OPEN
UNLESS
OTHERWISE
SPECIFIED
T it- 1,'
-i
1
C
C
"
RC
vc
+VC
lolt
VOH
VOL
11
":"
c
::::i
":"
t Arrows indicate actual direction of current flow. Current into a terminal is a positive value.
FIGURI;: 1. RECEIVER SECTION TEST CIRCUIT (VT +, VT -. VOH. VoLi
z
o
~
~
a::
oLL
Z
W
CJ
Z
~
C
c(
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-249
ADVANCE
INFORMATION
SN75155
LINE DRIVER AND RECEIVER
PARAMETER MEASUREMENT INFORMATION
INPUT
RL-3kO
J
L,.6
---'1 .
INPUT
~H~-"'~-OUTPUT
~~5~---3V
V
(SEE NOTE BI
CL - 60pF
(SEE NOTE AI
~
tpHL-.i
I
OV
-.I
I
-",=",=-VOH
--:9:"!O~%~1
OUTPUT
II
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. CL includes probe and jig capacitance.
B. The input waveform is supplied by a generator with the following characteristics: Zout .. 500, tw = 1 "s, tr S 10 ns, tf S 10
r-
ns~
FIGURE 2, DRIVER SECTION SWITCHING TEST CIRCUIT AND VOLTAGE WAVEFORMS
S'
CD
C
OUTPUT
::l,
:;
;
RESPONSE
CONTROL
INPUT
L2
--- V
- - " • (SEE NOTE BI
INPUT
:xl
6V
I
CD
t~L~
n
--4V
\.- 2 V
1\,,_____
~14~_.~
CD
...<'enCD
VOH
OUTPUT
TEST CIRCUIT
~
0 V
I
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The input waveform is supplied by a generator with the following characteristics: Zout .. 500, tw = 1 1'8, tr S 10 ns, tf S 10 ns.
C
FIGURE 3. RECEIVER SECTION SWITCHING TEST CIRCUIT AND VOLTAGE WAVEFORMS
~
2
n
m
-2
""o
s:
~
~
(5
2
4-250
TEXAS . "
INSTRUMENTS
POST OFFice BOX 8S501 2 • DAL.LAS, TEXAS 75265
ADVANCE
INFORMATION
8N75155
LINE DRIVER AND RECEIVER
TYPICAL CHARACTERISTICS
(DRIVER)
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
VOLTAGE TRANSFER CHARACTERISTICS
20.-or~--~-.-.--~-r-'r-~~
10
TA - 25°C
RL - 3 kll-
Vcc± - ±12 V
8
6
>
I
I=
g
f..- VtC±1 -
ti
16
9
~
4
I
VCC± - ±5 V
2
i
o
8~--l----1f....-..:,t...---+----<~-l4~--l-.::..~t.I----+-I--I--I
(J
~
-2
o
I
o
6 -4
>
12~t-+-~~~~~kf~~
II
0~~-4~+'-~~~~~~L-+--4
-4
-8
III
~
Q)
- - 12 f--Ir--l--J.~q,.....~+--1f-+---+----l
-6
- 16
-8
1.2
1.4
1.6
1.8
VI-Input Voltage-V
'Qj
I----.I~:::=j../--I-
(,)
Q)
a:
- 20 LL-....L-L__.L..-...L----L__-'--...L----L__-'--....J
-20
-12
-4 0 4
8 12 16 20
-10
1
>
2
~
YO-Output Voltage-V
FIGURE 4
Q)
>
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FIGURE 5
C
Q)
SHORT-CIRCUIT OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
15
~
10
=FALL
:0
(J
5
I
o
U
-5
-I--.
400
...........
VCC+ - 12 V
Vce- - -12 V
Vo - 0
VCC+- 12V
Vce - -1 2V
TA - 25°e
..
f..-R:S~
:2
o
~ 100
I
i:c
.~
t:
~
1000
I.
IOS(lI - H
I
I
I
c
SLEW RATE
vs
LOAD CAPACITANCE
.!!
III
~
i=
4
I
•
r-
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CD
~
.!::
RC I.
O~EN- r--
RC- 2Okll
Vc - -5 V
VCC+ - 12 V
VCC- - -12 V
TA - 25°C
3
~
!:i
!:i 2
...
VT+
VT+
VT+
o
I
o
>
VT-
VT-
VT-
C
~'
.
o
CD
-5
-4
-3
-1
-2
(II
0
2
3
4
5
VI-Input Voltage-V
:ltI
CD
FIGURE 8
n
CD
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CD
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
til
RC - 10 kll
V - 12 V
5
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~
i
.~
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m
~
!:i
o
Z
~
c
z
-
..
I
Rc l •
O~EN
RC - 20 kllJ.
I - - - V C - - 12
Y
VCC+ _ 12 V
VCC- _ -12V
TA - 25°C
~
VT+
VT+
2
VT+
I
VT-
VT-
VT-
"T1
o
:D
i:
l>
:::!
o
z
4-252
o
-5
-4
-3
-2
-1
0
VI-Input Voltage-V
FIGURE 9
TEXAS •
INSTRUMENTS
. POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2
3
4
5
ADVANCE
INFORMATION
5N75155
LINE DRIVER AND RECEIVER
TYPICAL CHARACTERISTICS
(RECEIVER)
INPUT CURRENT
vs
INPUT VOLTAGE
INPUT THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
10
3
VCC+- 12V
VCC- - -12 V
2.5
>
.
I
'"
~
-
2
>
~ 1.5
-
c(
VT+
-I---
E
4
C
!
:;
2
I
r-- r---
u
0
I"
-4
ic
VT-
0.5
./
/'
/'
-2
-6
o
VCC- - -12 V
6
.c
III
~
;
...
.s
TA - 25°C
8 VCC+ - 12 V
V
/'
./
...
/'
In
CI)
>
"Gi
u
CI)
V
-8
o
10
20
30
40
50
60
T A -Free-Air Temperature- °C
-10
-25-20-15-10 -5
70
0
5
10 15 20 25
VI-Input Voltage-V
FIGURE 11
FIGURE 10
--r:x:...
In
CI)
>
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CI)
c:
::::i
NOISE REJECTION
9
\ \
\
8
~ 7
go6
.
\
5
-5i
4
I-
3
o
~
;
\ 1\
~
-5
~
,JVCC+ - 12 V
'IvCC_ - -12 V
TA & 25°C
"
t-"
\
\
IX'
1\
~2
Cc
Cc
Cc
Cc
-
Cc -
1000 pF
500 pF
300 pF
100 pF
10 pF
LV'
IV--
"-
I'
z
o
i=
«
:IE
a::
"- ......
.......
oLL
~
o
10
100
1000
tw-Pulse Duration-ns
FIGURE 12
10000
W
(.)
Z
~
«
c
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-253
r:j"
CD
...c
<'
CD
...
til
~
CD
(')
CD
<'
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CD
til
4-254
SN55157, SN75157
DUAL DIFFERENTIAL LINE RECEIVER
02300. SEPTEMBER 1980-REVISEO SEPTEMBER 1986
•
Meets EIA Standards RS-422-A and
RS-423-A
•
Meets Federal Standards 1020 and 1030
•
Operates from Single 5-V Power Supply
SN55157 ... JG PACKAGE
SN75157 ... D. JG. OR P PACKAGE
ITOPVIEW)
•
Wide Common-Mode Voltage Range
•
High Input Impedance
•
TTL-Compatible Outputs
•
High-Speed Schottky Circuitry
•
8-Pin Dual-In-Line Package
•
Similar to uA9637AC except for Corner
VCC and Ground Pin Positions
1 I N + [ ] B Vee
10UT 2
7 11N20UT 3
6 21N+
GND 4
5 21N-
logic symbol t
(2) 10UT
11N21N+
(3) 20UT
21N-
description
The SN7515 7 is a dual differential line receiver
designed to meet EIA standards RS-422·A and
RS-423-A and Federal Standards 1020 and
1030. It utilizes Schottky circuitry and has TTLcompatible outputs. The inputs are compatible
with either a single-ended or a differential-line
system. The device operates from a single 5-volt
power supply and is supplied in an a-pin dual-inline package and small outline package.
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEG Publication 617-12.
•
..
en
Q)
>
logic diagram
The SN55157 is characterized over the full
military temperature range of - 55°C to 125°C.
The SN75157 is characterized for operation from
DoC to 70°C.
'iii
lIN~~ll
•
.I:I
(2)
to)
Q)
a::
--.
lOUT
en
l1N- (7)
Q)
>
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2IN+~6)
.I:I
C
(3) 20UT
Q)
21N- (5)
s::::
:::i
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
VCC
------------~-----VCC
50n NOM
INPUT--~---Y~-e~~----~
OUTPUT
CURRENT
SOURCE
Copyright © 1980, Texas Instruments Incorporated
PRODUCTION DATA documents contein information
currant IS of publication date. Products conform to
specifications par the terms of TaxBs Instruments
:~~~:~~i~8:::,~1i ~!:ti~~ti:r :,~o::::::t:~~S
not
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-255
8N55157, 8N75157
DUAL DIFFERENTIAL LINE RECEIVER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) ...................................... -0.5 V to 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. ± 15 V
Differential input voltage (see Note 2) ......................................... ± 15 V
Output voltage (see Note 1) ......................................... -0.5 V to 5.5 V
Low-level output current ................................................... 50 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 3):
SN55157 JG package ............................................... 1050 mW
SN75157 D package ................................................. 725 mW
JG package ................................................ 825 mW
P package ................................................ 1000 mW
Operating free-air temperature range: SN55157 .......................... -55°C to 125°C
SN75157 ............................. O°Cto 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds JG package ............ 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds D or P package ......... 260°C
•
r-
S'
CD
...C
~'
;
fn
NOTES: 1. All voltage values, except differential input voltage, are with respect to the network ground terminal.
2. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input.
3. For operation above 25°C free-air temperature, derate the SN55157 JG package to 672 mWat 70°C at the rate of 8.4 mW/oC,
the SN75157 JG package to 528 mW at 70°C at the rate of 6.6 mW/oC, the 0 package to 464 mW at 70°C at the rate
of 5.8 mW/oC, and the P package to 640 mW at 70°C at the rate of 8.0 mW/oC. In the JG package, SN55157 chips are
alloy mounted and SN75157 chips are glass mounted.
.
recommended operating conditions
CD
Suppiy voltage, VCC
...
Common·mode input voltage, VIC
<'
CD
(II
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
±7
I
I
Operating free·alr temperature, TA
SN55157
-55
25
125
SN75157
0
25
70
V
°c
electrical characteristics over recommended ranges of supply voltage, common-mode input voltage,
and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Threshold voltage (VT + and VT _)
Vhys
Hysteresis (VT +
VOH
High·level output voltage
VID = 0.2 V,
10=-lmA
VOL
Low-level output voltage
VID = -0.2 V,
10=20mA
- VT _ )
Input current
0.2
-0.4
See Note 5
MAX
Sae Nota 4
-0.2
VT
II
MIN TYpt
0.4
70
2.5
VCC = 0 to 5.5 V, LVI = 10 V
See Note 6
I VI
lOS
Short-circuit output current*
Vo = 0,
VID = 0.2 V
ICC
Supply current
VID = -0.5 V,
No load
-40
V
mV
3.5
V
0.35
0.5
1.1
3.25
-1.6 -3.25
= -10 V
UNIT
V
mA
-75 -100 . mA
35
50
mA
tAli typical values are at VCC = 5 V, TA = 25°C.
*Only one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTES: 4. The algebraic convention, where the less-positive (more-negative) limit is designated as minimum, is used in this data sheet
for threshold levels only.
5. The expanded threshold parameter is tested with a 500-1) resistor in series with each input.
6. The input not under test is grounded.
4-256
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN55157, SN75157
DUAL DIFFERENTIAL LINE RECEIVER
switching characteristics. VCC - 5 V. TA .. 25°C
PARAMETER
TEST CONOITION
tpLH
Propagation delay time, low-to-high-Ievel output
tpHL
Propagation delay time, high-to-Iow-Ievel output
CL
=
15 pF,
MIN
TYP
MAX
15
25
13
25
See Figure 1
PARAMETER MEASUREMENT INFORMATION
VCC'"
VCC'"
OUTPUT
51
I:O~~U;--50%
50%
392n
INPUT
(see Note B)
-0.5 V
n
CL = 15 pF
I... Note AI
I
:
~ tPLH
3.92 kn
OUTP_U_T_ _
:
---
14---! tpHL
...'L_____
~l"
...
(II
Q)
>
'Q)
U
VOLTAGE WAVEFORMS
TEST CIRCUIT
Q)
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: tr :S 5 ns, tf :S 5 ns, PRR :S 5 MHz,
duty cycle = 50%.
-...
a::
( II
Q)
>
FIGURE 1. TRANSITION TIMES
.~
C
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
4
vs
vs
DIFFERENTIAL INPUT VOLTAGE
DIFFERENTIAL INPUT VOLTAGE
vc6
4
4.~5
=
V
-TA = 25°C
>I
3
..
I
I
I
I
"0
:>
2
0
1
0
I
I
-50
I
I
I
I
I
I
I
2
VIC = ±7 V
VIC = ±7 V:
:
r
I
>
:
I
VIC= 0
I
I
0
I
0
VIC=O
I I
I
VIC=O
I
I
I
o
-100
;
S:>
I
I
VIC = ±7 V I
I
~
I
I
I
I
>
:VIC=±7V
3
.,
'"
:l
I
I
I
I
S:>
:
>I
I
VIC=O
VCC = 5.25 V
TA = 25°C
I
I
I
I
.,
'"
:l
>
Q)
c:
:::;
OUTPUT VOLTAGE
o
o
50
100
-50
-100
o
50
100
VID-Differentiallnput Voltage-mV
VID-Differentiallnput Voltage-mV
FIGURE 3
FIGURE 2
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
4-257
SN75157
DUAL DIFFERENTIAL LINE RECEIVER
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
5_0
=j
i.
3_0
o"
2_5
!i
2_0
-;;
t..
"
>
0_5
!
'\.,.
-10
/'
0_3
-'
0_2
/
/'
00_1
o
o
-20 -30 -40 -50 -60 -70 -80
5
10
15
FIGURE 4
FIGURE 5
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
100
No1load I
90 - Inputs open
80 f- TA = 25°C
.
I 70
c:
60
~
"
i
'1"
]I
/
50
/V
40
/
30
/
20
,/
10
o
.."..-
V
023
456
VCC-Supply Voltage-V
FIGURE 6
4-258
20
25
30
35
IOL -Low-Level Output Current-mA
IOH-High-Level Output Current-mA
(,,)
V
Y
>
I\..
-
oE
"-
I
o
=j
"'" i'.. "-
f1.5
VC~= 5~
_
VID = 0_2 V
TA = 25°C -
-z, 4_0
3_5
0_6
VC~=5~
4_5
~
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 666012
it
DAUAS. TEXAS 75266
7
8
40
SN75157
DUAL DIFFERENTIAL LINE RECEIVER
TYPICAL APPLICATION DATA
+5V
TWISTED PAIR
+5V
+5V
•
~
FIGURE 7. RS-422-A SYSTEM APPLICATIONS
~
"Qi
(,)
CD
ex::
~
CD
>
".:::
C
CD
c
::::i
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75285
4-259
•
,
4-260
SN55158, SN75158
DUAL DIFFERENTIAL LINE DRIVERS
02292. JANUARY 1977-REVISED SEPTEMBER 1986
•
•
•
•
•
•
•
SN55158 ... JG PACKAGE
SN75158 ... D. JG. OR P PACKAGE
(TOP VIEW I
Meets EIA Standard RS-422-A
Single 5-V Supply
lZ[]8 Vee
Balanced-Line Operation
TTL-Compatible
High Output Impedance in Power-Off
Condition
IV
lA
2
3
7
6
2Z
GND
4
5
2A
2V
High-Current Active-Pullup Outputs
Short-Circuit Protection
•
Dual Channels
•
Input Clamp Diodes
description
The SN55158 and SN75158 are dual complementary-output line drivers designed to satisfy the
requirements set by the EIA Standard RS-422-A interface specifications. The outputs provide
complementary signals with high-current capability for driving balanced lines. such as twisted pair. at normal
line impedance without high power dissipation. The output stages are TTL totem-pole outputs providing
a high-impedance state in the power-off condition.
II...
II)
Q)
>
'i)
U
-...
Q)
The SN55158 is characterized for operation over the full military temperature range of - 55°C to 125 °e.
The SN75158 is characterized for operation from O°C to 70 o e.
a:
I I)
Q)
logic symbol t
>
logic diagram (positive logic)
t>
''::
o
~lY
(2) 1Y
1A
1A (3)
'-VJo--.!!!.
Q)
r:
1Z
:::i
1Z
2A
(5)
(61
~2Y
2V
2A~2Z
2Z
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
PRUDDCTIO. DATA ............ontolol."""'III••
ou,nmt •• 01 p.bOcatlo. d.... P'.d......nf.,m to
I)IIICifl••Ii••• per tho .......1 T.... Inotrum.1II
=:~I~·:.':I~l.; =:~i:; 1Ir=::1t:~~ nat
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-261
SN55158. SN75158
DUAL DIFFERENTIAL LINE DRIVERS
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
VCC-------e------~___
---"'--VCC
4 k!l
NOM
INPUT
9!l NOM
OUTPUT
GND-~~----~~
II
---+---GND
r-
S"
..<"
.
CD
C
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
'
Supply voltage, VCC ................................. ' ................ , ...... 7 V
Input voltage ........ , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
D package ......................................................... 725 mW
JG package (alloy mount), SN55158 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1050 mW
JG package (glass mount), SN75158 .............. , ........... ,.......... 825 mW
P package ..................................... ' . . . . . . . . . . . . . . . . . .. 1000 mW
Operating free-air temperature range: SN55158. . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
SN75158 ............................. ooC to 70°C
Storage temperature range ......................................... - 65°C to 1 50°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package ........... 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package. . . . . . . .. 260°C
CD
en
:J:I
CD
(')
CD
~"
til
NOTES: 1. All voltage values except differential output voltage Voo are with respect to network ground terminal. VOO is at the Y output
with respect to the Z output.
2. For operation above 25°C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the JG package, SN55158
chips are alloy mounted and SN75158 chips are glass mounted, In the P package, use the 8.0-mW/oC curve for these devices.
recommended operating conditions
SN55158
Supply voltage, Vee
NOM
MAX
MIN
NOM
MAX
4,5
5
5,5
4,75
5
5.25
High-level input voltage, VIH
2
Low-level input voltage, VIL
High-level output current, IOH
Low-level output current, IOL
Operating free-air'temperature, TA
4-262
SN75158
MIN
2
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
V
V
0.8
0.8
V
-40
-40
mA
40
mA
70
°C
40
-55
UNIT
125
0
SN55158, SN75158
DUAL DIFFERENTIAL LINE DRIVERS
electrical characteristics over operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
Input clamp voltage
VOH
High-level output voltage
II
Vee - MIN.
Vil - 0.8 V.
10H
Vee - MIN.
Vil - 0.8 V.
VIH ~ 2 V.
10l ~ 40 rnA
10 ~ 0
IV ODll
IV OD21
Differential output voltage
Vee ~ MAX.
Differential output voltage
Vee ~ MIN
differential output voltage §
Common-mode output voltage 1
Voe
10
II
common-mode output voltage §
Output current with power off
Input current at maximum
input voltage
IIH
High-level input current
Vee
~
-40 rnA
-0.9
-1.5
3.0
MAX
-0.9
-1.5
3.0
2
UNIT
V
V
0.4
V
3.5 2VOD2
V
V
3.0
±0.02
±0.4
±0.02
±0.4
1.9
3
1.8
3
1.4
3
1.5
3
±0.01
±0.4
±0.01
±0.4
See Figure 1
~
TYP*
0.2
0.4
3.5 2VOD2
3.0
Rl ~ 1000.
IVo - 6 V
Vee ~ 0 Iva ~ -0.25 V
Iva ~ -0.25t06V
MIN
2.4
0.2
MIN or MAX
0.1
100
0.1
100
-0.1
-100
-0.1
-100
±100
V
V
V
..
II)
~A
Q)
±100
Vee ~ MAX.
VI
5.5 V
1
1
rnA
Vee ~ MAX.
VI ~ 2.4 V
40
40
~A
-1
-1.6
rnA
-90
-150
rnA
37
50
rnA
>
'a;
U
Q)
Low-level input current
Vee ~ MAX.
lOS
Short-circuit output current f1
Vee - MAX
Supply current (both driversl
MAX
2
Vee - MAX
Vee - MIN
III
ICC
~
SN75158
TYP*
2
Vee ~ MIN
Change in magnitude of
.:I.lVoel
MIN
-12 rnA
VIH ~ 2 V.
Low-level output voltage
.:I. JVOD 1
~
Vee ~ MIN.
VOL
Change in magnitude of
SN55158
TEST CONDITIONSt
VI
~
0.4 V
-40
Vee - MAX.
Inputs grounded.
No load.
TA
~
25°C
-1
-1.6
-90
-150
37
50
-40
a:
-.
II)
.
Q)
>
.~
C
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at Vee ~ 5 V and T A ~ 25°C except for Voe. for which Vee is as stated under test conditions.
§.:I.I VOD 1 and .:1.1 Voe 1 are the changes in magnitudes of VOD and Voe. respectively. that occur when the input is changed from a high
*
Q)
level to a low level.
, In EIA Standard RS-422-A. Voe. which is the average of the two output voltages with respect to ground. is called output offset voltage. VOS.
#Only one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
switching characteristics. Vee = 5 V. TA = 25°e
TEST
PARAMETER
CONDITIONS
SN55158
MIN
SN75158
MAX
tplH
See Figure 2.
16
25
16
25
ns
tpHl
Propagation delay time. high-to-Iow-Ievel output
Termination A
10
20
10
20
ns
tplH
Prop~gation
See Figure 2.
13
20
13
20
ns
tpHl
Propagation delay time, high-to-Iow-Ievel output
Termination B
9
15
9
15
ns
tTlH
Transition time, low-to-high-Ievel output
See Figure 2.
4
20
4
20
ns
lTHl
Transition time, high-to-Iow-Ievel output
Termination A
4
20
4
20
ns
10
%
Overshoot factor
See Figure 2.
Termination C
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
MAX
10
MIN
UNIT
TYP
Propagation delay time. low-to-high-Ievel output
delay time. low-to-high-Ievel output
TYP
r:::::
:::::i
4-263
SN55158, SN75158
DUAL DIFFERENTIAL LINE DRIVERS
PARAMETER MEASUREMENT INFORMATION
FIGURE 1. DIFFERENTIAL AND COMMON-MODE OUTPUT VOLTAGES
INPUT
V OUTPUT
Z OUTPUT
T
v--------,
CL - 15 pF-L
v
100 !l
z
CL-30pF
(see Note BI
(see Note BI
z
CL - 15PFl
(see Note B1'T'
":"
TERMINATION A
":"
TERMINATION B
TERMINA nON C
TEST CIRCUIT
OVERSHOOT
"~;""'--OV
,oo.~~~
0%
10%
10%
I
I
tTLH-+I
I
I
tf-ITHL
t_
r-
OVERSHOOT
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zout = 50!l, tw = 25 ns, PRR '" 10 MHz.
B. CL includes probe and jig capacitance.
FIGURE 2. SWITCHING TIMES
4-264
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN55158, SN75158
DUAL DIFFERENTIAL LINE DRIVERS
TYPICAL CHARACTERISTICS t
OUTPUT VOLTAGE
vs
DATA INPUT VOLTAGE
OUTPUT VOLTAGE
vs
DATA INPUT VOLTAGE
6
6
ve6 - 51V
No loed
No load
TA = 25°C
5
5
>
...~
!!
Vee - 5.5
4
'0
Vee - 5 V
!i
Vee - 4.5 V
> 3
S
TA - 125°C
. /
V
0
\ T j - j5 e
2
<]'
o
>
TA - -55°C
fI)
"-
CD
>
o
o
2
.1
o
4
3
'i
u
o
2
VI-Data Input Voltage-V
>
I
...
CD
!!
'0
...>
3
::J
S
0
----
2
I
LOW-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
0.4
--
I
.I
I
/1
~Ff..- 5V
> 0.3
-.......1'--'
~
...
OJ
>
!i 0.2
5::J
0
.....I
0
"
>
0.1
/
-40
-60
-80
V
/v
V
l/
V
.%
Vee - 4.5 V
f7
l\
-20
,I.e
Vee - 5.5 VA
I
?-- t--.'
Vee - 4.5 V
~
o
c
::J
-'.
J
J:
.0
o
CD
TA - 25°C
Vee - 5.5 V
t--.
t--.
';:
Q
TA - 25°C
t---
~
f
CD
>
FIGURE 4
HIGH-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
4
4
VI-Data Input Voltage-V
FIGURE 3
5
3
o
-100 -120
o
10
20
30
40
50
60
70
80
IOL -Output eurrent-mA
IOH-Output eurrent-mA
FIGURE 5
FIGURE 6
tData for temperatures below Doe and above 70 0 e are applicable to SN55158 circuits only.
TEXAS
-II
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75285
4-265
SN55158. SN75158
DUA~ DIFFERE~TIAL
LINE DRIVERS
TYPICAL CHARAC'T~RISTICSt
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
4.0
3.0
•...
2.5
I
!
~
0
30
Ve~- 5 ~ .I I _20'"
I. ~l .-.::::
~l
~
"o~l\O~ - -..--::.--
3.5
>
PROPAGATION DELAY TIMES
vs
FREE-AIR TEMPERATURE
l!!
-
0
>
CD
.<'o
!
2.0
f
1.5
6
1
20
-
h-h-
tpLH
15
...-
V
tPHL_ h- I--
10
..--
1s
Q.5
VOLIIOL - 40 IIlAI
o
-75 -50 -25
CD
25
j::
1.0
!i"
.. SIV
Sa. Figure 2
Termination A
I
I
r-
Ve~
;
0
25
50
o
100 125
75
-75 -50 -25
T A -Free-Air Temperature- De
ii
CD
25
50
100 125
75
TA - Free-Air Temparature- De
FIGURE 7
()
0
FIGURE 8
CD
~'
SUPPLY CURRENT
(BOTH DRIVERS)
vs
SUPPLY VOLTAGE
;
SUPPLY CURRENT
(BOTH DRIVERS)
vs
FREE-AIR TEMPERATURE
80
42
No load I
TA .. 25 De
70
40
<
60
~
50
i
Q.
40
30
I
u
.!:}
I
C 38
~
,~~
/'
Q.
::J
1/1
,1-"
ved - 5 1V
Input grounded
Outputs open
-......
~
::J
u·
",~cP- ~
O~
>Q.
,1-"
lI
,~~
36
"'-
34
""'"
U
20
.!:}
I
V
10
o
o
32
./
2
3
456
7
8
30
-75 -50 -25
0
25
50
75
T A - Free-Air Temperature- DC
vee-Supply Volt!lge-V
FIGU~E
FIGURE 9.
toats for temperatures below O'C and above 70'C are applicable to SN55158 circuits only.
4-266
~
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS. TEXAS 76266
10
'"
100 125
SN55158, SN75158
DUAL DIFFERENTIAL LINE DRIVERS
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
(BOTH DRIVERS)
vs
FREQUENCY
100
~
Vee - 5 V
RL - 00
eL - 30 pF
Inputs: 3-volt square wave
TA - 25°e
80
I
t:
a
60
§'
40
..
~
,...,11
III
V
CII
I
u
Jr
20
o
0.1
0.4
4
10
40
100
f - Frequency- MHz
FIGURE 11
TEXAS •
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TeXAS 76265
4-267
4-268
SN75159
DUAL DIFFERENTIAL LINE DRIVER
WITH 3-STATE OUTPUTS
02325. JANUARY 1917-REVISEO SEPTEMBER 1986
•
Meets EIA Standard RS-422-A
D. J. OR N PACKAGE
(TOP VIEW)
•
Single 5-V Supply
•
Balanced Line Operation
•
TTL-Compatible
•
High-Impedance Output State for Party-Line
Applications
•
High-Current Active-Pull-Up Outputs
NC
lZ
lY
lA
18
lEN
GND
•
Short-Circuit Protection
NC-No internal connection
•
Dual Channels
•
Clamp Diodes at Inputs
VCC
2Z
2Y
28
2A
2EN
NC
description
The SN75159 dual differential line driver with three-state outputs is designed to provide all the features
of the SN75158 line driver with the added feature of driver output controls. There is an individual control
for each driver. When the output control is low. the associated outputs are in a high-impedance state and
the outputs can neither drive nor load the bus. This permits many devices to be connected together on
the same transmission line for party-line applications.
The SN75159 is characterized for operation from
coe to
logic symbol t
II
.
III
Q)
>
'Q)
Co)
Q)
a:
--.
70 oe.
I II
Q)
logic diagram (positive logic)
>
';:
(61
lEN
(41
lA
(51
lB
(91
2EN
(10)
2A
(11)
2B
C
&t>
EN
lEN
Q
(31
lY
lA
lZ
lB
Q)
(3)
(21
c::
::i
1Y
lZ
2EN
2A
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEG Publication 617-12.
2B
(12)
(13)
2Y
2Z
Copyright @ 1986, Texas Instruments Incorporated
PRODUCTION DATA documants contain information
current as of publication date. Products conform to
specifications par the tarms af Taxas Instruments
==i~.i~:I~'li ~r::l:~ti:r :.;o::::::~:~~ .ot
TEXAS ..,
INSTRUMENTS
~ost
OFFIC!
~OX
866012 •
~ALLAS,
nXAS 16265
4-269
SN75159
DUAL DIFFERENTIAL LINE DRIVER
WITH 3"STATE OUTPUTS
schematic (each driver)
INPUT B
(14)
VCe-'~-'---'--~-'
(5. 11)
INPUT A
(4. 10) .---.....--+---<....--1H-----.~--~....----.___,
4 kO
90
90
(3.12)
(2.13)
OUTPUT
OUTPUT
y
Z
I"'"
5"
CD
c
~"
.
<
CD
en
~
n
CD
<"
CD
.
en
V
4 kO
OUTPUT
CONTROL
(6.9)
GND~(7~)____~______~--._~
w...
Vee bus
Resistor values shown are nominal.
4-270
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS; TeXAS 75265
SN75159
DUAL DIFFERENTIAL LINE DRIVER
WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Off-state voltage applied to open-collector outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 V
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950 mW
J package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 50 mW
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 1 50°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............ 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package ........ 260°C
NOTES:
1. All voltage values except differential output voltage VOD are with respect to the network ground terminal. VOD is at the Y
output with respect to the Z output.
2. For operation above 25°C free-air temperature, derate the D package to 608 mW at 70 0 e at the rate of 7.6 mW/oC, the
J package to 656 mW at 70 °C at the rate of B.2 mw/oe, and the N package to 736 mW at 70°C at the rate of 9.2 mw/oe.
In the J package, SN75159 chips are glass mounted.
II...
1/1
Q)
recommended operating conditions
Supply voltage, Vee
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
Low-level input voltage, VIL
High·level output voltage, IOH
Low-level output current, IOl
a
Operating free-air temperature, T A
(.)
Q)
V
a::
O.B
V
1/1
-40
mA
40
mA
>
0;:
70
°e
C
2
High·level input voltage, VIH
>
0Qj
--...
Q)
Q)
c:::
::i
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-271
SN75159
DUAL DIFFERENTIAL LINE DRIVER
WITH 3·STATE OUTPUTS
electrical characteristics over operating free·air temperature range (unless otherwise noted)
PARAMETER
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
VOK
Vo
TEST CONDITIONS
II
AIVoel
S·
CD
.<'
.
10
Vee - 4.75 V.
VIL - 0.8 V.
=
VIL - 0.8 V.
10l
Output clamp voltage
Output voltage
Vee - 4.75 V to 5.25 V.
Vee
5.25 V.
en
10
*
Output current with power off
Vee
=
Vee
=
10 - 0
state) output current
~
0.4
V
-1.5
V
0
6
V
V
2
3.5 2VOD2
3.0
±0.4
1.8
3
Vee - 4.75 V
1.5
3
Vee = 4.75 V
to 5.25 V
±0.01
±0.4
0.1
-0.1
100
Vee
RL
Vo
Vo
=0
=
100!l.
=
=
=
Vee = 5.25 V.
Output controls
at 0.8 V
TA
=
See Figure 1
6 V
-0.25 V
Vo - 0 to Vee
±10
Vo - 0
Vo - 0.4 V
±20
V
V
V
~A
20
~A
±20
20
Vo - 2.4 V
Vo - Vee
Input current at
-100
V
±100
-0.25 V to 6 V
70 D e
V
V
3.0
±0.02
5.25 V
UNIT
0.25
=0
CD
(')
MAX
-1.5
-1.1
40 mA
-40 mA
TA - 25 D e.
Off-state (high impedance-
2.4
4.75 V
Vo
10Z
Typt
-0.9
Vee - 4.75 V
Common-mode output voltage §
common·mode output voltage
=
=
10 -
MIN
-40 mA
VIH = 2 v.
Vee - 5.25 V.
C
CD
=
10H
2 V.
Vee - 4.75 V.
Change in magnitude of
r-
11- -12mA
VIH
I V OD11 Differential output voltage
I V OD21 Differential output voltage
Change in magnitude of
AIVODI
differential output voltage*
Voe
Vee - 4.75 V,
<'
CD
II
Vee
=
5.25 V.
VI
=
5.5 V
1
IIH
High-level input current
Vee
=
5.25 V.
VI
=
2.4 V
40
~A
en
Ill:
Low-level input current
Vee - 5.25 V.
VI - 0.4 V
-1
-1.6
mA
lOS
Short-circuit output current'
Vee - 5.25 V
5.25 V.
-90
-150
mA
(nputs grounded.
47
65
mA
CD
.
ICC
maximum input voltage
Supply current (both drivers)
vq:: =
-40
No (oad.
TA = 25 D e
mA
t All typical values are at Vee = 6 V and TA = 25 D e except for Voe. for which Vee is as stated under test conditions.
* <1.1 VOO I and AIVoe I are the changes in magnitudes of VOD and Voe. respectively. that occur when the input is changed from a high
level to a low level.
§ In EIA Standard RS-422-A. Voe. which is the average olthe two output voltages with respect to ground. is called output offset voltage. VOS.
, Only one output should be shorted at a time. and duration of the short-circuit should not exceed one second.
TEXAS .."
4-272
INSTRUMENTS
POST
o~~lce
BOx 855012 • DALLAS. tEXAS 7526&
SN75159
DUAL DIFFERENTIAL LINE DRIVER
WITH 3-STATE OUTPUTS
switching characteristics over operating free-air temperature range.
PARAMETER
Vee -
5
V (unless otherwise noted)
TEST CONDITIONS
tpLH Propagation delay time, low-to-high-Ievel output CL = 30 pF, RL
tpHL Propagation delay time, high-to-Iow-Ievel output Termination A
=
MIN
Typt
MAX
16
25
ns
11
20
ns
13
20
ns
9
4
4
7
14
10
17
15
ns
20
ns
20
ns
20
ns
40
ns
30
ns
35
10
ns
100 n, See Figure 2,
tpLH Propagation delay time, low-to-high-Ievel output
CL = 15pF, See Figure 2. Termination B
tpHL Propagation delay time. high~to-low~level output
CL = 30 pF, RL = 100 n, See Figure 2,
tTLH Transition time. low-to-high-Ievel output
Termination A
tTHL Transition time. high-to-Iow-Ievel output
pF,
RL
= 180 n,
pF,
RL
=
RL
=
CL
= 30 pF,
= 30 pF,
RL
=
tpZH Output enable time to high level
CL
tpZL Output enable time to low level
tpHZ Output disable time from high level
CL
CL
tPLZ Output disable time from low level
Overshoot factor
t All typical values are at T A
=
= 30
= 30
See Figure 3
250 n, See Figure 4
1BOn, See Figure 3
RL = 250 n, See Figure 4
100 n, See Figure 2, Termination C
UNIT
%
II
25 ·C.
~
CD
SYMBOL EQUIVALENTS
DATA SHEET PARAMETER
RS-422-A
Vo
V oa , Vob
iVOD11
VO
Vt
I V OD21
.6.I VODI
VOC
.6.I V ocl
lOS
10
I IVtl -
>
';
U
CD
a:
! II
~
IVtl I
IVosl
I Vos - Vos I
Iisal, Ilsbl
Ilxal, Ilxbl
CD
>
-;:
Q
CD
c:
:.::;
PARAMETER MEASUREMENT INFORMATION
FIGURE 1. DIFFERENTIAL AND COMMON·MODE OUTPUT VOLTAGES
TEXAS "
INSTRllMENTS
POST OFFICE BOX 65sb12 • DALLAS, TEXAS 75265
4-273
SN75159
DUAL DIFFERENTIAL LINE DRIVER
WITH 3·STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
r---,
1 kD
5V----~~--~
I
I
I
""--:---V OUTPUT
I
PULSE
GENERATOR
(See Note Al
II
I-........--;--L.-P....:...--z OUTPUT
V--------l.., CL _
V
Z
CL 30 pF
(sea
Nota BI
l
.
RL - 1000
Z
CL- 15pF
(See Note BI
l
15 pF
~.
_ _ _ _ _..J RL -
1000
Z
~
TERMINATION C
TERMINATION B
TERMINATION A
V
""'"
~ (See Note BI
TEST CIRCUITS
\f---25n.~
~ I ~S5 ns
II
1
INPUT
10%
I
90%
1.5 V
90%
90%
•1
I
I
~LH
!t---*-tPHL
90%
Z
OUTPUT
10%
OVERSHOOT
0 V
'''%;=~\
1:0% !I...!!!!- - - - VOH
I I 1.5V
I
10%
3V
1
I
11 . 5V 1
jt-S5 ns
-1-1- - - - - -
1.5 V
t PLH; '
OU;PUT
-till
10%
VOL
I
1
I
IWt-ITHL
I
)
14~~:~~_
.
10%
I
"""";';';;"--";';':~I-I
- -
-
VOH
VOL
VOLTAGE WAVEFORMS
s
10 MHz.
FIGURE 2. tPLH. tPHL. tTLH. tTHL. AND OVERSHOOT FACTOR
4·274
.
,--
OVERSHOOT
IHI-ttLH
NOTES: A. The pulse generator has the following characteristics: Zout = 50 D. PRR
B. CL includes probe and jig capacitance.
O%t=~
TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN75159
DUAL DIFFERENTIAL LINE DRIVER
WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
INPUT
PULSE
GENERATORI--4I.....--~.....- - ' - I
(See Note Al
T-=
CL 30 PF
(See
Note BI
,'O--.....
--,OUTPUT
I
'----1I~CL-_---J
1-=
I
1 kl1
30PF
(See
Note BI
L __________
I
I
I
I
I
...
~
III
~
-i
5V
()
TEST CIRCUIT
Q)
a:
.....
INPUT
...
III
~
S5ns-.!
~~__=,.,jl.-I-90%
90%
I
1.5V
1.5V
I
Q)
>
-;:
Q
-3V
~100 ns~ 1\..:,;10%::.:::..._ _
OUTPUT
~tPZH
I
:
I
:/
I
f
_ _ _....J
1 .5V
:
tPHZ
Q)
c
:::;
OV
-*-VOH
~T
I 0.5 V
--k--+t
Voff
~
0 V
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zout = 50 11, PRR
B. CL includes probe and jig capacitance.
s
500 kHz.
FIGURE 3, tpZH AND tPHZ
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-275
SN75159
DUAL DIFFERENTIAL LINE DRIVER
WITH 3;STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
INPUT
PULSE
GENERATOR
{See Note Al
5V
T
-=
CL 30 PF
{See
Note Bl
RL - 250 II
'O--.....--OUTPUT
5V
I
1 kll
I....--_-..._~I
I
I
T-=
!L ___________ JI
30PF
(see
Note Bl
I
....5'
CD
...
<'CD
...
TEST CIRCUIT
C
(II
:xl
CD
INPUT
C")
CD
<'
CD
;1
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zout
C. CL includes probe and jig capacitance.
=
50 II. PRR s 500 kHz.
FIGURE 4. tPZL AND tPLZ
4-276
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN75159
DUAL DIFFERENTIAL LINE DRIVER
WITH 3·STATE OUTPUTS
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
DATA INPUT VOLTAGE
OUTPUT VOLTAGE
vs
DATA INPUT VOLTAGE
6
6
No load
TA - 25°C
Vcc - 5 V
No load
5
5
>
..
Q
4
0
>
'I:
3
=
~
I
f
\
2
f\ \...VCC" -
"
4
~
3
o
I
o
>
2
,"\
\ ~TA
~
5 V
~VCc'- 4.75 V
0
>
r T A - 70°C
I
"
~
0
>
jVCC - 5.25 V
I
~TA
--
- 25°C
I
.>
_'OOc
I II
G)
o
o
o
2
3
~
____
~~
o
4
2
VI~Data
VI-Data Input Voltage-V
I
Vcc - 5 V
>
.
I
Q
~
=
~
0
0
--a:..
4
I II
Input Voltage-V
>
";:
C
G)
c:
::::i
TA - 25°C
VOH IIOH -
-20 mAI,.-
VOH IIOH -
-40 mAl
>
3.0
4
~--4----+----~--~---+--~
I
f3~':::"-..b-"':::~II-="-.b----~---+----I
=
~
2.5
2.0
o
1.5
I
I
>
3
HIGH-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
0
>
(,)
G)
____~
G)
OUTPUT VOLTAGE
vs
FREE·AIR TEMPERATURE
3.5
"iii
~
FIGURE 6
FIGURE 5
4.0
__- L____
:t
o
1.0
>
0.5
o
VOL (lOL - 40 mAl
o
25
50
o
75
L-__
o
~
__- i____L-__
-20
-40
-60
-L~-i
__- - J
-80 -100 -120
IOH-Output CUrrent-mA
T A -Free-Air Temperature- °C
FIGURE 7
FIGURE 8
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TEXAS 16265
4·277
SN15159
DUAL DIFFERENTIAL LINE DRIVER
WITH 3·STATE OUTPUTS
'
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
(BOTH DRIVERS)
LOW-LEVEL OUTPUT VOLTAGE
0.6
vs
vs
OUTPUT CURRENT
SUPPLY VOLTAGE
80
I
No1load
TA - 25 D e
~
0.5
>
Vee - 4.75~
I
&
~
~
S
S
0.3
...I
0.2
...
o
r
0.4
# V
o
S·
>
CD
0.1
C
:::!.
<
CD
;
'0
--:a
V
o
/
/
70
~
A
is.
-
... 44
Jl
I
42
9
40
u
8
Vee = 5 V
RL = 00
eL - 30 pF
Inputs: 3-volt square wave
80
'ii
Q
g'
Q.
~
.
"
--
tPLH
Q.
OUTPUT ENABLE AND DISABLE TIMES
vs
FREE-AIR TEMPERATURE
30
Vee - 5 V
See Figures 3 and 4
..E
I 25
II)
j::
.
is
...."
"
~
."
tpHL
20
tp
15
w
6
II...
-
tpHZ
:is 10
8
,=--- ~
tpZL
tPZH
U)
CD
4
2
0
>
"iii
Vee - 5 V
eL = 30 pF
RL - 100 {l
o
25
o
(J
75
50
CD
o
25
50
75
....
...CD
a:
U)
T A -Free-Air Temperature- °e
TA-Free-Air Temperature- °e
FIGURE 14
FIGURE 13
>
.;:
C
CD
C
~
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-279
II
r-
::r
CD
..c<'
..
-..<'
CD
til
::0
CD
(')
CD
CD
til
4-280
SN75160B
OCTAL GENERAL·PURPOSE
INTERFACE BUS TRANSCEIVER
02525, OCTOBER 1985
MEETS IEEE STANDARD 488-1978 (GPIBI
•
8-Channel Bidirectional Transceiver
•
Power-Up/Power-Down Protection (GlitchFree)
•
•
ow. J. OR N DUAL-IN-LiNE PACKAGE
(TOP VIEWI
High-Speed, Low-Power Schottky Circuitry
Low-Power Dissipation . . . 72 mW Max per
Channel
GPI8
1/0
•
Fast Propagation Times . . . 22 ns Max
•
High-Impedance P-N-P Inputs
•
Receiver Hysteresis ... 650 mV Typ
•
Open-Collector Driver Output Option
•
No Loading of Bus When Device is Powered
Down (VCC = 0)
PORTS
TE
Vee
81
82
83
02
03
84
04
85
05
01
86
06
87
88
07
08
GNO
PE
II
.
FUNCTION TABLES
EACH DRIVER
description
0
H
L
H
X
TE
H
H
X
L
EACH RECEIVER
OUTPUT
INPUTS
The SN75160B 8-channel general-purpose
interface bus transceiver is a monolithic, highspeed, low-power Schottky device designed for
two-way data communications over singleended transmission lines. It is designed to meet
the requirements of IEEE Standard 488-1978.
The transceiver features driver outputs that can
be operated in either the passive-pull up or threestate mode. If Talk Enable (TE) is high, these
ports have the characteristics of passive-pullup
outputs when Pullup Enable (PE) is low, and of
three-state outputs when PE is high. Taking TE
low places these ports in the high-impedance
state. The driver outputs are designed to handle
loads up to 48 milliamperes of sink current.
TERMINAL
110 PORTS
PE
H
X
L
X
H = high level, L
B
H
L
zt
zt
= low level, X
B
L
H
X
INPUTS
OUTPUT
TE
L
L
H
0
L
H
Z
PE
X
X
X
II)
CI)
>
'iii
C.l
CI)
a::
--.
I I)
= irrelevant, Z = Hi9h~impedance
CI)
>
';:
state.
t This is the high~impedance state of a normal 3-state output
modified by the internal resistors to Vee and ground.
C
iii
Output glitches during power-up and powerdown are eliminated by an internal circuit that
disables both the bus and receiver outputs. The
outputs do not load the bus when Vee = 0
volts. When combined with the SN75161 B or
SN75162B management bus transceivers, the
pair provides the complete 16-wire interface for
the IEEE 488 bus.
The SN75160B is characterized for operation
from ooe to 70 oe.
PRODUCTION DATA documonts .ontain information
curroat I. 01 pu~IiCllion data. Producla .onform to
specifications par the tarmi af Texl. Instruments
:::==i~.i:I~7i
::::i:,R 1I~-=:lt::'s nat
Copyright © 1985. Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
c:::
::;
4-281
SN75160B
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
logic diagram (positive logic)
logi~ symbol t
Bl
02 (18)
82
B3
03 (17)
B4
•
r-
:r
CD
...c
B5
B6
04 (16)
B7
TERMINAL
B8
GPI8
I/O
PORTS
05 (15)
t This symbol is in accordance with ANSI/lEEE Std 91-1984 and
IEC Publica lion 617-12.
\l Designates 3-state outputs.
D6 (14)
~ Designates passive-pullup outputs.
<'
CD
...
Ul
::xJ
CD
(')
08 (12)
CD
<'
CD
...
Ul
schematics of inputs and outputs
EQUIVALENT OF ALL CONTROL INPUTS
EQUIVALENT OF ALL INPUT/OUTPUT PORTS
VCC--------~--------
9kn
10kn
NOM
NOM
INPUT
GNO--~----_4~----~-
Driver output Req'" 30
n
Receiver output Req'" 110
NOM
n
NOM
Circuit Inside dashed lines is on the driver outPuts only.
·4-282
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN75160B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Low-level driver output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
OW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ........ 1125 mW
J package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1375 mW
N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1150 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 60 seconds: J package. . . . . . . . .. 300°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: OW or N package. . .. 260°C
ooe
NOTES:
1. All voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, derate the DW package at the rate of 9.0 mW/oC, the N package at the rate
of 9.2 mW/oC. and the J package at the rate of 11.0 mW/oC. In the J package. SN75160B chips are alloy mounted.
recommended operating conditions
II
..
!II
Supply voltage. V CC
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
0.8
Low-level input voltage. VIL
High-level output current, IOH
Low-level output current, IOL
V
2
High-level input voltage. VIH
Bus ports with pull ups active
-5.2
Terminal ports
-800
48
Bus ports
16
Terminal ports
Operating free-air temperature. T A
0
70
V
mA
~A
mA
'c
a>
>
"iii
(J
a>
a:
--..
! II
a>
>
";:
C
a>
c:
:J
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-283
SN75160B
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
electrical characteristics over recommended ranges of supply voltage and operating free·air temperature
(unless otherwise noted)
PARAMETER
~ystere$is
Vhys
(VT+ - VT-)
High-level
VOH
output voltage
Low-level
output voltage
,VOL
Input current at
II
•
TEST CONDITIONS
Input clamp voltage
VIK
maximum input voltage
MIN
11= -18 mA
-0.8
Bus
Terminal
- 800 ~A,
-5.2 mA,
TE at 0.8 V
PEandTEat2V
Bus
10H 10H -
Terminal
10L = 16 mA,
TE at 0.8 V
Bus
10L = 48 mA,
TE at 2 V
Terminal
IIH
IlL
High-level input current
Terminal
Low-level input current
Terminal
VI/O(bus)
Voltage at bus port
TYpt
0.4
0.65
2.7
2.5
3.5
Current into bus port
0.5
0.5
VI = 5.5 V
0.2
100
~
VI = 2.7 V
VI - 0.5 V
0.1
-10
20
-100
~A
3.0
3.7
1l(bus) = 0
1l(bus) - -12 mA
Driver disabled
2.5
-1.5
ICC
Supply current
No load
Ci/o(bus)
Bus-port capacitance
VCC = 5 V to 0 V,
f = 1 MHz
V
mA
2.5
-40
-15
-35
-75
-25
-50
-125
Receivers low and enabled
70
90
Drivers low and enabled
85
110
VI/O = 0 to 2 V,
~A
2.5
0
0.7
Vl(bus) - 0 V to 2.5 V
Terminal
Bus
V
-3.2
+2.5
-3.2
Vl(bus) = 2.5 V to 3.7 V
Power on Driver disabled
Vl(bus) = 5 V to 5.5 V
output current
V
0.3
Power off Vee -0,
lOS
V
0.35
Vl(bus) = 3.7 V to 5 V
Short-circuit
UNIT
V
3.3
Vl(bus) = -1.5 V to 0.4 V -1.3.
0
Vl(busl - 0.4 V to 2.5 V
II/O(busl
MAX
-1.5
~A
mA
mA
pF
30
tAli typical values are atVeC = 5V,TA = 25°C.
switching characteristics. Vee - 5 V. eL - 15 pF. TA - 25°e (unless otherwise noted)
PARAMETER
tpLH
tpHL
tPLH
low-to-high-Ievel output
Propagation delay time,
low-to-high-Ievel output
Output enable time to high level
tPHZ
Output disable time from high level
tPZL
tpLZ
Output
Output
Output
Output
Output
Output
Output
Output
tPHZ
tpZL
tpLZ
ten
tdis
4-284
TEST CONDITIONS
:Terminal
Bus
CL = 30 pF,
See Figure 1
Bus
Terminal
eL = 30 pF,
See Figure 2
high-to-Iow-Ievel output
tpZH
tpZH
TO
high-to-Iow-Ievel output
Propagation delay time,
Propagation delay time,
tPHL
FROM
Propagation delay time,
enable time to low level
disable time from low level
enable time to high level
disable time from high level
enable time to low level
disable time from low level
pull-up enable time
pull-up disable time
TE
Bus
See Figure 3
TE
Terminal
See Figure 4
PE
Bus
See Figure 5
TEXAS ,..,
INSTRUMENTS
POST OFFICE BOX 8~60'2 • DALLAS, TEXAS 752E1is
MIN
TYP MAX
14
20
14
20
10
20
15
22
25
35
UNIT
ns
ns
13
22
22
35
22
32
20
30
12
20
23
32
19
30
15
22
13
20
ns
ns
ns
SN151608
OCTAL GENERAL"PURPOSE INTERFACE 8US TRANSCEIVER
PARAMETER MEASUREMENT INFORMATION
200n
D'NPUT
X
f.5V
-
5:
----'1~_,
-
tpLH""""
j'I"2-.2-V------------.\: - -
BOUTPUT
"ij)
(,)
Q)
a:
-~
Q)
>
";::
C
Q)
c:
:::;
VOLTAGE WAVEFORMS
TEST CIRCUIT
FIGURE 2. BUS-TO-TERMINAL PROPAGATION DELAY TIMES
~~V
'i~~----3V
82
tpZH-----t
480n
B OUTPUT(
S1to3V I
14-
tpHZ"""'"
S20PEN ,
tpZL
0V
I ,..------------~..
0.8 V
14
3~V
BOUTPUT
S1 to GND
1.0V
S2CLOSED
VOLTAGE WAVEFORMS
TEST CIRCUIT
FIGURE 3. TE-TO-BUS ENABl.E AND DISABLE TIMES
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR :s; 1 MHz, 50% duty cycle, tr s;6 ns,
tf sns, Zout = 50 O.
B. CL includes probe and jig capacitance.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-285
SN75160B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
PARAMETER MEASUREMENT INFORMATION
~_
52
TE
'NPUT~\':'5_V
tpZH~
DDUTPUTI
51to3V
S2DPEN
....Ji·":.___
______
I
I
r.:
tpHZ--t
I
1.5V
tpZL ~
I
:
3V
-0 V
,...
-96%- -
-VDH
OV
tpLZ-..j
4V
o OUTPUT
81 toGND
52 CLOSED
TEST CIRCUIT
II
' -_ _ _ _ _ _....I!_O.:!~ _ -VOL
VOLTAGE WAVEFORMS
FIGURE 4. TE·TO·TERMINAL ENABLE AND DISABLE TIMES
r-
5"
..
.
CD
C
~"
:>-...7'-....- -....-OUTPUT
fIl
::u
CD
()
CD
~"
Cil
TEST CIRCUIT
VOLTAGE WAVEFORMS
FIGURE 5. PE-TO-BUS PULLUP ENABLE AND DISABLE TIMES
NOTES:
A. The input pulse is supplied by a generator having the following characteristics: PRR s; 1 MHz, 50% duty cycle, tr s6 ns,
tl :s ns. Zout
=
50 II.
B. CL includes probe and jig capacitance.
4-286
TEXAS ..,
INSTRUMENTS
POST OFFiCe BOX 866012 • DALLAS. TeXAS 75286
SN75160B
OCTAL GENERAL"PURPOSE INTERFACE BUS TRANSCEIVER
TYPICAL CHARACTERISTICS
TERMINAL HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
4_0
>I
..'"'"
-5
>
~
:J
1
3.5
.........
3.0
2.5
>
.J
'"
J:'"
1:.
I
>
'"'"
l!I
"0
>...
'\
2.0
S:J
1.0
0
;;
0.5
-5
0.4
"
-10 -15 -20
0.3
>
.J
'"
~
0.2
/
0
.J
I
\.
o
I
tC=5 V
0.5 -TA=25°C
V
:J
'\
1.5
o
>I
'\.
"\.
J:
0
0.6
.1.
Vec = 5 V
TA=25°C-
S:J
0
;;
TERMINAL LOW-LEVEL OUTPUT VOLTAGE
vs
.J
0
>
't\.
V
~
•
...
I/)
0.1
o
-25 -30 -35 -40
/
/
/
/
II)
>
"Qi
o
IOH-High-Level Output Current-mA
20
10
30
40
50
60
IOL -Low-Level Output Current-mA
II)
>
";:
C
TERMINAL OUTPUT VOLTAGE
II)
vs
c
BUS INPUT VOLTAGE
::i
4.0
Vce = 5 V
No load
TA = 25°C
3.5
>I
3.0
l!I
"0
'"'"
2.5
>...
2.0
::J
S:J
0
I
0
>
VT1.5
VT+
1.0
0.5
o
o
--...
I /)
FIGURE 7
FIGURE 6
(,)
II)
a:
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VI-Input Voltage-V
FIGURE 8
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
4-287
SN75160B
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
TYPICAL CHARACTERISTICS
BUS HIGH-LEVEL OUTPUT VOLTAGE
BUS LOW-LEVEL OUTPUT VOLTAGE
vs
vs
BUS HIGH-LEVEL OUTPUT CURRENT
BUS LOW-LEVEL OUTPUT CURRENT
4
0..6
VCC'=5V
TA = 25'C
~
3
I""
2
t
VCC=5V
TA=25'C
....
0..4
0
a;
0..3
~
0..2
'"
0
0..1
..
.!l
~
1-I
~~
CD
>
0.
<
CD
-
/
V
SOl
'\.
:f
:::I.
./
0..5
"0
>
rC
>I
V
/'"
V
./
./
V
/
0.
0.
-10.
-20.
-30.
-40.
-50.
-GO
0.
IOH-High-Level Output Current-mA
C;;
:J:J
10.
~
40
50. 60.
70. 80. 90. 10.0.
FIGURE 10.
FIGURE 9
CD
20. 30
IOL -Low-Level Output Current-mA
BUS CURRENT
~.
BUS OUTPUT VOLTAGE
vs
vs
C;;
TERMINAL INPUT VOLTAGE
BUS VOLTAGE
VCC= 5V
No load
TA = 25'C
2
3r-~---+--+---~-+--~--+-~
!
c
...
~
u
-1
.
ID
I
-;;
!
~
__~__~__~~__~__~~
1.0. 1_1 1.2 1.3 1.4 1.5 1.6 1.7
THE UNSHADED
~t-t--t-t-~ AREA CONFORMS TO
PARAGRAPH 3.5.3 OF
~H-T-+"*, IEEE STANDARD 488-1978
0.L-~
0..9
FIGURE 12
FIGURE 11
4-288
2
3
4
VI/O(bus)-Bus Voltage-V
VI-Input Voltage-V
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
5
6
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
02618, OCTOBER 1980-REVISEO OCTOBER 19B5
MEETS IEEE STANDARD 488-1978 (GPIB)
•
8-Cham;el Bidirectional Transceiver
•
Power-Up/Power-Down Protection
(Glitch-Freel
•
Designed to Implement Control Bus
Interface
•
SN75161B Designed for Single Controller
•
SN75162B Designed for Multi-Controllers
•
High-Speed, Low-Power Schottky Circuitry
•
Low-Power Dissipation ... 72 mW Max Per
Channel
•
Fast Propagation Times . . . 22 ns Max
•
High-Impedance P-N-P Inputs
•
Receiver Hysteresis ... 650 mV Typ
•
Bus-Terminating Resistors Provided on
Driver Outputs
•
SN75161B ... OW. J. OR N DUAL-IN-L1NE PACKAGE
(TOP VIEW)
GPIB
I/O
PORTS
GPIB
I/O
PORTS
description
The SN75161 Band SN75162B eight-channel
general-purpose interface bus transceivers are
monolithic, high-speed, low-power Schottky
devices designed to meet the requirements of
IEEE Standard 488-1978. Each transceiver is
designed to provide the bus-management and
data-transfer signals between operating units of
a single- or multiple-controller instrumentation
system. When combined with the SN75160B
octal bus transceiver, the SN7 5161 B or
SN75162B provides the complete 16-wire
interface for the IEEE 488 bus.
The SN75161 Band SN75162B each features
eight driver-receiver pairs connected in a frontto-back configuration to form input/output (I/O)
ports at both the bus and terminal sides. A power
up/down disable circuit is included on all bus and
receiver outputs. This pr9vides glitch-free
operation during VCC power-up and powerdown. The direction of data through these driverreceiver pairs is determined by the DC, TE, and
SC (on SN75162B) enable signals. The SC input
on the SN75162B allows the REN and IFC
transceivers to be controlled independently.
=~I~·i~:I~'l.; =~1:~ti:r :'l°;'~:~~::· not
VCC
REN
)FC
NDAC
NRFD
DAV
EOI
ATN
SRO
DC
TERMINAL
I/O PORTS
SN75162B ... OW DUAL-IN-L1NE PACKAGE
(TOP VIEW)
No Loading of Bus When Device is Powered
Down (VCC = 01
PRODUCTION DATA doc...anlleantain Inform.tion
••rrant .1 of publi••tion dot._ Pred.cts .onform to
.ps.iIl.llio•• par tho to.... of T•••• In.trum.nll
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRO
GND
SC
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRO
NC
GND
VCC
NC
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRO
NC
DC
~
CD
>
'ii)
U
CD
TERMINAL
I/O PORTS
GPIB
I/O
PORTS
VCC
NC
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRO
DC
TERMINAL
I/O PORTS
Copyright © 1980. Texas Instruments Incorporated
INSTRUMENTS
POST OFFiCe BOX 655012 • DALLAS, TEXAS 75266
CD
>
-;:
C
CD
C
NC-No internal connection.
TEXAS •
en
::;
SN75162B ... N DUAL-IN-L1NE PACKAGE
(TOP VIEW)
SC
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRO
GND
-.
a:
4-289
SN75161Q. SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
The driver outputs (GPIB 110 ports) feature active bus-terminating resistor circuits designed to provide a
high impedance to the bus when supply voltage Vee is O. The drivers are designed to handle loads up
to 48 milliamperes of sink current. Each receiver features p-n-p transistor inputs for high input impedance
and a guaranteed hysteresis of 400 millivolts for increased noise immunity. All receivers have 3-state outputs
to present a high impedance to the terminal when disabled.
The SN75161 Band SN75162B are characterized for operation from
ooe
CHANNEL IDENTIFICATION TABLE
NAME
DC
r-
:i"
TE
Talk Enable
SC
System Control (SN7S162B onlyl
.c<"
CLASS
Control
ATN
Attention
SRO
Service Request
Bus
REN
Remote Enable
Management
IFC
Interface Clear
EOI
End or Identify
DAV
CD
IDENTITY
Direction Control
Data Valid
NDAC
Not Data Accepted-
NRFD
Not Ready for Data
Data
Transfer
CD
;
ii
CD
~
~"
iil
4-290
TEXAS •
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
to 70 oe.
SN75161B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SN75161B logic symbol t
DC(l1)
SN75161B logic diagram (positive logic)
EN1/G4
TE~(1~)----~EN~2~/G~5~,
EN3
TV'
I>
.rr
.rr
1
I>
1
(14)
EOI
(7) EDI
TV'
.rr
.rr
1
I>
TV'
I>
2V'
SRQ (12)
2"
.rr
I>
2"~
SRQ
•
.
CI)
REN (19)
~
1
(91
II)
.rr
1
I>
(8) ATN
~
.rr
I>
(13)
ATN
3V'
(2)
REN
>
-i
CJ
CI)
-.
IX
.rr
IFC (181
(31 IFC
I I)
CI)
tThis symbol is in accordance with IEEE Std 91-1984 and lEe
publication 617-12:
Qdesignates 3-state output, edesignates passive-pullup outputs.
(15)
DAV
(61
>
-;:
Q
DAV
CI)
:S
NDAC
NRFD
(171
(41 NDAC
1161
(51 NRFD
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 856012 • DALLAS. TEXAS 75265
4-291
SN75162B
OCTAL GENERAL,PURPOSE INTERFACE BUS TRANSCEIVER
SN75162B logic symbol t
oc
SN75162B logic diagram (positive logic)
[13) (12) r-E-Nl~/G-4----'
TE [2) (2)
sc [1) (1)
EN2/G5
EN3
t-~..,
TE
sc
ATN
[9)
(9) ATN
REN
[17)
EOI (15)
[8]
(8)
[15)
SRQ (13)
[10]
(10)
[22]
REN (20)
[3]
(3)
[21]
IFC (19)
[41
(4)
[18]
DAV (16)
[7]
[20]
(18)
[5]
[19]
[61
(6)
EOI
SRQ
IFC
I"'"
:r
CD
DAV
..<'c
..
CD
en
ii
CD
n
CD
..
<'
CD
REN
NDAC
tThis symbol is in accordance with IEEE Std 91-1984 and lEe
publication 617-12.
Qdesignates 3-state output, ~designates passive-pull up outputs.
en
NDAC
(17)
NRFD
[ I Denotes pin numbers for DW package.
( ) Denotes pin numbers for N package.
4-292
TEXAS.
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TEXAS 76266
IFC
(7) DAV
(5) NDAC
NRFD
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SN75161B
RECEIVE/TRANSMIT FUNCTION TABLE
CONTROLS
DC
TE
ATNt
BUS-MANAGEMENT CHANNELS
ATNt
SRQ
REN
IFC
EOI
DATA-TRANSFER CHANNELS
DAV
H
H
H
H
L
L
H
L
H
R
NDAC
NRFD
(Controlled by TEl
(Controlled by DCI
T
R
R
-2-
T
R
R
R
R
L
L
L
T
R
T
T
--,=-
R
T
T
H
L
X
R
T
R
X
T
R
T
R
T
T
H
R
T
T
L
R
T
R
R
•
SN75162B
RECEIVE/TRANSMIT FUNCTION TABLE
...enCD
>
-Qj
(,)
CD
-...
a:
en
CD
>
-;;:
Q
H = high level, L = low level, R = receive, T = transmit, X = irrelevant
Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the
bus side to the terminal side. Data transfer is noninverting in both directions.
t ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC
and TE inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only.
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
CD
t:
:i
4-293
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS· TRANSCEIVERS
schematics of inputs and outputs
TYPICAL OF SRQ;NDAC, and NRFD
GPIB 1/0 PORT
EQUIVALENT OF ALL
CONTROL INPUTS
-.------Tr~------~~r-----~----~--vcc
1.7 kO
NOM
vcc------.------gkn
10 kO
NOM
NOM
INPUT
GND-4____
~
____
~
·~--~~~---4~4_
4
__~_________ GND
INPUT/OUTPUT
PORT
L-________________-r__________________________~____e_ir_c_u_it_in_s_id_e_d_a_s_h_ed__li_ne_s_i_s_o_n~t-h-e~d-ri-ve-r-o-u-t-pu-t-s-o-n-IY_.--J
TYPICAL OF ALL 1/0 PORTS
EXCEPT SRQ, NDAC, and NRFD GPIB 1/0 PORTS
r-
:i"
CD
C
:!-
...<
CD
en
~
CD
n
CD
<-
...
----~~~--4_r+~--~+-~--~--------GNO
CD
en
INPUT/OUTPUT
PORT
Driver output Req ~ 30 O·NOM
Receiver output Req ~ 110 0 NOM
Circuit inside dashed lines is on the driver outputs only.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage. . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Low-level driver output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
OW package (20 pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1125 mW
OW package (24 pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1350 mW
J package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1375 mW
N package (20 pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150 mW
N package (22 pin) ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1700 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooC to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .' . . . . . . . .. - 65°C to l' 50 °C
Lead temperature 1,6 mm (1/16) inch from the case for 60 seconds: J package .......... 300°C
Lead temperature 1,6 mm (1/16) inch from the case for 10 seconds: OW or N package .... 260°C
NOTES:
1. All voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, derate the 20'pin OW package at the rate of 9.0 mw/oe, the 24·pin OW
package at the rate of 10.8 mW/oC, the 20-pin N package at the rate of 9.2 mW/oC, the 22-pin N package at the rate of
13.6 mw/oe, and the J package at the rate of 11.0 mw/oe. In the J package, SN75161 B chips are alloy mounted.
4-294
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
recommended operating conditions
Supply voltage, Vee
High-level input voltage, VIH
MIN
NOM
MAX
4,75
5
5.25
2
0.8
Bus ports with 3-5tate outputs
Terminal ports
Bus ports
Low-level output current, tOl
mA
-800
~A
16
Terminal ports
70
0
V
-5.2
48
Operating free-air temperature, T A
V
V
Low-level input voltage, VIL
High-level output current, IOH
UNIT
mA
°e
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
TEST eONDITIONS
MIN
Typt
MAX
UNIT
-0.8
-1.5
V
VIK
Input clamp voltage
Vhys
Hysteresis (VT + - VT_)
Bus
High-level
Terminal
output voltage
Bus
10H ~ -800 ~A
10H ~ - 5.2 mA
Low-level
Terminal
10L
~
16 mA
0.3
0.5
output voltage
Bus
10L
~
48 mA
0.35
0.5
Terminal
VI
VOHt
VOL
Input current at
II
maximum input voltage
High-level
IIH
IlL
VI/Olbus)
II
input current
and
control
input current
inputs
at bus port
-18 mA
Power off
lOS
lee
ei/o(bus)
Short-circuit
Terminal
output current
Bus
Supply current
2.5
3.3
V
V
V
II
...
II)
Q)
>
-Qj
(.J
Q)
~A
~
2.7 V
0.1
20
~A
--...
a::
I I)
VI
VI
~
0.5 V
Driver disabled
Vee
~
0,
No load,
-10 -100
Illbus) ~ 0
Illbus) ~ -12 mA
VI/O
~
2.5
3.0
Q)
V
s::::
::::i
+2.5
Vllbus)
~
3.7Vt05V
0
Vllbus) - 5 V to 5.5 V
Vllbus) ~ 0 V to 2.5 V
0.7
-3.2
mA
2.5
2.5
-40
-15
-35
-25
-50 -125
TE, De, and se low
1 MHz
C
-3.2
0
2.5Vt03.7V
~
~A
Q)
>
-;::
1.3
~
0 to 2 V, f
3.7
-1.5
Vllbus)
Vee - 5 V to 0 V,
Bus-port capacitance
3.5
100
Driver disabled
Power on
2.7
0.2
Vllbus) Vllbus) - 0.4 V to 2.5 V
Current into bus port
0.65
5.5 V
1.5 V to 0.4 V
II/Olbus)
0.4
~
Terminal
Low-level
Voltage
~
-75
110
30
~A
mA
mA
pF
t All typical values are at Vee ~ 5 V, T A ~ 25°e.
+VOH applies for three-state outputs only.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-295
SN751618, SN751628
OCTAL GENERAL·PURPOSE INTERFACE 8US TRANSCEIVERS
switching characteristics, Vee - 5 V, CL
PARAMETER
=
15 pF, TA .. 25°C (unless otherwise noted)
FROM
TO
Terminal
Bus
TEST
MIN
CONDITIONS
TYP
MAX
14
20
14
20
29
35
10
20
15
22
UNIT
Propagation delay time,
tpLH
tpHL
low-to-high-Ievel output
Propagation delay time,
tpLH
Bus
Bus
30 pF,
CL
Terminal
~
30 pF,
Output disable time from high level
tpZL
Output enable time to low level
:i'
tpLZ
Output disable time from low level
CD
tpZH
Output enable time to high level
...c
tpHZ
Output disable time from high level
tpZL
Output enable time to low level
...
tpLZ
Output disable time from low level
BUS
TE, DC,
45
See Figure 3
REN, IFC,
SC
ns
60
(ATTN, EOI,
or
ns
ns
See Figure 2
high-to-Iow-Ievel output
Output enable time to high level
-
~
Propagation delay time,
low-to-high-Ievel output
tpHZ
<'
CD
30 pF,
See Figure 1
NRFDI
tpZH
r-
CL
(SRQ, NDAC
Terminal
low-to-high-Ievel output
Propagation delay time,
tpHL
~
See Figure 1
high-to-Iow-Ievel output
Propagation delay time,
tpLH
CL
60
and DAVI
ns
55
55
TE, DC,
50
See Figure 4
Terminal
or
45
SC
ns
55
(II
::xJ
CD
n
PARAMETER MEASUREMENT INFORMATION
CD
<'
CD
4,3V
5V
...
(II
240n
200n
FROM ITERMINALI
OUTPUT UNDER
---e~-----~-4'--TESTPOINT
TEST
FROM IBUS)
OUTPUT UNDER--4~---"-"'-TEST POINT
TEST
T
CL
= 30 pF
1
480 n
ISee Note A)
":"
LOAD CIRCUIT
,_----"""- - - -- 3 V
1,5V
1,5V
IS•• Not. BI
I
BUS
INPUT
OV
tPLH-/4+I
!,------""-I- 2.2 V
.L..5V
---It .
tPHL~
BUS
OUTPUT
3k.l1
':"
LOAD CIRCUIT
INPUT
CL ~ 30 pF
IS•• Note A)
-VOH
I
TERMINAL
OUTPUT
IS•• Note B)
\1:~ - -30v
V
•
tPHL~
,_-----"':T --1.5V
VOH
1.5V
VOL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
FIGURE 2. BUS·TO·TERMINAL
PROPAGATION DELAY TIMES
FIGURE 1. TERMINAL· TO·BUS
PROPAGATION DELAY TIMES
NOTES:
4·296
A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ,;; 1 MHz, 50% duty cycle, tr ,;;6 ns,
tf ,;;6 ns, Zout ~ 50 n.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS '75265
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
PARAMETER MEASUREMENT INFORMATION
S1
S1
Q--5V
lOon
FROM (BUS)
OUTPUT UNDER_.--+---t~TEST POINT
TEST
I.,..
FROM (TERMINAL)
~
OUTPUT
UNDER TEST
LOAD CIRCUIT
CONTROL
INPUT __ J
'i' .
I
I+-
tpHZ.-I
:
I
I--
-90%- - -
I
I
BUS
I
~II .. 3.5 V
OUTPUT
·1.0 V
S1 C L O S E D " \ _ _ _ _ _- J 0.5
V - VOL
--
\!
~
r--
I I
I
1.5V
I
S1 OPEN_ _--.J
OV
tPLZ---I...j
TERMINAL
OUTPUT
3V
~1.5V
i\I '- ___
(S••____
Note B) ._JI!\
1\.. _____ OV
1.5V
tPZH-.!
VOH
2V
tpZL --+----I
3 kn
--,'tr------ --"\ r-----
--, r-------_,. r----
BUS
OUTPUT
S10PEN
CL = 15 pF
(See Note A)
LOAD CIRCUIT
3V
CONTROL
~1.5V
V 1.5V
INPUT __ J
(S•• Note B) JI'11>;"
'- _______
____ OV
tPZH-I
240n
__-"'--4'- TEST POINT
r
480 n
CL· 15 pF
(See Note A)
Q--4.3V
tPZL-!
TERMINAL
OUTPUT
S1 CLOSED
t-
tpHZ....
1I
C--- - ---
VOH
90%
I
tPLZ-IOj
a
~
~
-i
OV
CJ
-.
G)
1
a:
1.0V
I II
G)
VOLTAGE WAVEFORMS
>
-;:
C
VOLTAGE WAVEFORMS
FIGURE .4; TERMINAL ENABLE
AND DISABLE TIMES
FIGURE 3. BUS ENABLE AND
DISABLE TIMES
G)
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR S 1 MHz. 50% duty cycle, tr S 6 ns,
tf s6 ns, Zout = 500.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
c
::i
4-297
•
SN75161B, SN75162B
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVERS
TYPICAL CHARACTERISTICS
TIORMINAL HIGH·LEVEL OUTPUT VOLTAGE.
vs
HIGH·LEVEL OUTPUT CURRENT
4.0
l'
..i
3.0
;
2.5
o
2.0
:5
1.5
:If
1.0
~
;
i
TA=25°C
l'
'"'I\.
!.
'\
0.5
0.4
;- /
B.
0
0.3
V
=
/
0.2
~
"J
"
0
"J
I
"J
0 0.1
V
>
'\~
-10 -15 -20 -25 -30 -35 -40
IOH-High·Level Output Curr~nt-mA
-5
40
10
20
30
50
IOL -LoIII/·Level Output Current-mA
FIGURE 6
FIGURE 5
TERMINAL OUTPUT VOLTAGE
vs
BUS INPUT VOLTAGE
4.0
VCc=5V
No load
TA = 25°C
3.5
>I
3.0
&
l!I 2.5
.
~
:r
2.0
VT_
~
1.5
>
1.0
0
I
0
VT+
0.5
o
o
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VI-Input Voltage-V
FIGURE 7
4·298
/
/
V
Ii
I\.
o
VCc=5V
TA = 25°C
;
'\
::r
~ 0.5
o
0;6
~CC=15V
,
3.5
TERMINAL LOW·LEVEL OUTPUT VOLTAGE
vs
LOW·LEVEL OUTPUT CURRENT
TEXAS •
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 76286
60
SN75161B, SN75162B
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVERS
TYPICAL CHARACTERISTICS
BUS HIGH·LEVEL OUTPUT VOLTAGE
vs
HIGH·LEVEL OUTPUT CURRENT
BUS·LOW LEVEL OUTPUT VOLTAGE
vs
LOW·LEVEL OUTPUT CURRENT
4
>I
..
CD
l!
-0
..."
0.6
Vce = S V
TA= 2SoC
~
3
>
"'-
"
0
~
2
.t
..J
.1::.
CD
%
..So"
-0
>
~
"'\
,...
Gi
>I
"
0
..
,.
..J
'" ~
~
J:
~
o
o
0.4
V
0.3
0.2
0
..J
I
..J
0
>
/'
II
...
./'
II)
CD
>
"(jj
oL--L~
o
-...
CD
a:
I I)
CD
FIGURE 9
>
";:
C
BUS CURRENT
vs
BUS VOLTAGE
CD
I:
::::i
-:r
Vec = S V
No ioad
TA= 2SoC
(.)
__L--L~__~-L~__~~
10 20 30 40 SO 60 70 80 90 100
IOL - Low·Level Output Current-rnA
BUS OUTPUT VOLTAGE
vs
TERMINAL INPUT VOLTAGE
..
./'
V
FIGURE 8
>I
V
V
0.1
-10
-20
-40
- 30
-so -60
IOH-High·Level Output Current-rnA
4
/V
o.S
Gi
"\
I
VCC=SV
TA = 2Soc
2
3
CD
l!
-0
..a-"
>
I
2
"I
0
0
>
~H-+++ AREA CONFORMS TO
o
0.9
-6 ~f----f---.J'--+-42" PARAGRAPH 3.S.3 OF
'-IEEE STANDARD 488·1918
1.0
1.1 1.2 1.3 1.4 1.5
VI-Input Voltage-V
1.6
1.7
-1
FIGURE 10
234
0
VI/O(busl-Bus Voltage-V
5
6
FIGURE 11
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4·299
•
4·300
SN75163B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
D2611, OCTOBER 1985
ow. J.
•
8-Channel Bidirectional Transceivers
•
Power-Up/Power-Down Protection
(Glitch-Free)
•
High-Speed Low-Power Schottky Circuitry
•
Low Power Dissipation , . . 66 mW Max per
Channel
•
High-Impedance P-N-P Inputs
•
Receiver Hysteresis ... 650 mV Typ
•
Open-Collector Driver Output Option
•
No Loading of Bus When Device is Powered
Down (VCC - 0)
OR N DUAl-IN-LiNE PACKAGE
(TOP VIEW)
BUS
I/O PORTS
Vee
TE
B1
B2
B3
B4
B5
B6
B7
01
02
03
04
05
06
07
08
PE
BB
GNO
II
FUNCTION TABLES
description
EACH RECEIVER
EACH DRIVER
The SN75163B octal general-purpose interface
bus transceiver is a monolithic, high-speed,
low-power Schottky device. It is designed for
two-way data communications over single-ended
transmission lines. The transceiver features
driver outputs that can be operated in either the
open-collector or three-state modes. If Talk
Enable (TEl is high, these outputs have the
characteristics of open-collector outputs when
Pullup Enable (PEl is low and of three-state
outputs when PE is high. Taking TE low places
the outputs in the high-impedance state. The
driver outputs are designed to handle loads of
up to 48 milliamperes of sink current. Each
receiver features p-n-p transistor inputs for high
input impedance and 400 millivolts of
guaranteed hysteresis for increased noise
immunity.
TERMINAL
1/0 PORTS
INPUTS
H
OUTPUT
INPUTS
OUTPUT
0
TE
PE
B
B
TE
PE
D
H
H
H
H
l
L
L
H
X
X
X
l
H
H
l
L
H
H
X
L
Z
X
l
H
L
L
X
l
X
Z
en
"-
CD
>
'Q)
H
Z
Co)
en
= high level. l = low level, X = irrelevant, Z = high-impedance
state.
nDt
CD
r::
:::i
Copyright
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
CD
>
Q
The SN75163B is characterized fpr operation
from ooe to 70 oe.
:::=:~i~ai~:,~7~ ~=::i:r :.~O=:£::~
"-
';:
Output glitches during power-up and powerdown are eliminated by an internal circuit that
disables both the bus and receiver outputs. The
outputs do not load the bus when Vee = 0
volts.
PRODUCTION DATA doct/mlnls ..nlain in'ormation
currant I. of publication date. Products conform to
spacifications par the tarms of Taxal Instruments
CD
a:
© 1983, Texas Instruments Incorporated
4-301
SN75163B
. OCTAL GENERAL"PURPOSE INTERFACE BUS TRANSCEIVER
logic symbol t
logic diagram (positive logic)
TE
01 --'--'-"4 ::>-----,
02 (18)
Bl
82
03 (17)
B3
B4
B5
04 (16)
B6
B7
:i"
c
..<"
..
TERMINAL
88
r-
CD
05 (15)
BUS
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
V Designates 3-5t8te outputs.
Q Designates open-collector outputs.
06 (14)
CD
en
(13)
::J:3
07
CD
-'--'--+--'--1 ::>-----,
n
CD
.
<"
CD
08 (12)
en
schematics of inputs and outputs
EQUIVALENT OF ALL CONTROL INPUTS
EQUIVALENT OF ALL INPUT/OUTPUT PORTS
---.---~---------.----~t--Vcc
10kn NOM
VCC-----~~--------
9knNOM·
INPUT
GNO--__--~--~__- ----~-~--~--i--~--~------GNO
INPUT/OUTPUT
PORT
Driver output Req
= 30 n
NOM
Receiver output Req '" 110
4-302
n
NOM
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN75163B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Low-level driver ou~put current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 mA
Continuous total dissipation at lor below) 25°C free-air temperature (see Note 2):
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1125 mW
J package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1375 mW
N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11 50 mW
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ooC to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
Lead temperature 1,6 mm (1/16) inch from the case for 60 seconds: J package .......... 300°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: N package. . . . . . . . .. 260°C
NOTES:
1. All voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, derate the OW package at the rate of 9.0 mW/oC, the N package at the rate
of 9.2 mw/oe, and the J package at the rate of 11.0 mw/oe. In the J package, SN751638 chips are alloy mounted.
MIN
NOM
MAX
UNIT
II
.
4.75
5
5.25
V
'Q)
V
-.
recommended operating conditions
en
Supply voltage, Vee
High-level input voltage, V,H
2
Low-level input voltage, V,L
High-level output current, IOH
Low-level output current. IOL
Bus ports with pullups active
Terminal ports
v
-10
mA
-800
~A
48
Bus ports
16
Terminal ports
Operating free-air temperature range, T A
0.8
0
70
mA
°e
Q)
>
CJ
Q)
IX:
en
Q)
>
';::
C
Q)
c::
:::i
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS. TEXAS 75265
4-303
SN75163B
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
electrical characteristics over recommended ranges of supply voltage and operating free·air temperature
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
Input clamp voltage
Vhys
Hysteresis IVT + - VT-)*
High level
output voltage
Terminal
Bus
10H IOH -
Low-level
Terminal
10L
output voltage
Bus
10L
Bus
Vo - 5.5 V,
D and TE at 2 V
VOH
VOL
II
•
:i"
10Z
II
CD
Off-state output current
. maximum input voltage
IIH
IlL
lOS
ICC
input current
Low-level
MAX
-1.5
TE at 0.8 V
PE and TE at 2 V
~
16 mA,
TE at 0.8 V
0.3
0.5
~
48 mA,
PE and TE at 2 V
0.4
0.5
3.5
3.3
PE at 0.8 V,
PE at 2 V,
IVo ~ 2.7 V
TE at 0.8 V
IVa - 0.4 V
V
V
100
~
20
-20
~A
VI
~
5.5 V
0.2
100
~A
Terminal
VI
~
2.7 V
0.1
20
~A
Terminal
VI
~
0.5 V
~A
-10
-100
Short-circuit
Terminal
-15
-35
-75
output current
Bus
-25
-50
-125
input current
V
V
-800 ~A,
-10 mA,
2.7
2.5
UNIT
Terminal
Supply current
IReceivers low and enabled
No load
Cil
ii
CD
Typt
-0.8
0.4 0.65
Bus
13-state mode)
High-level
CD
...c<'
lopen-collector mode)
Input current at
MIN
-18 mA
Bus
High-level output current
10H
,...
~
VIK
VCC ~ 5 V or 0 V, VI/O
f ~ 1 MHz
Ci/olbus) Bus-port capacitance
80
I Drivers low and enabled
~
100
0 to 2 V,
mA
mA
pF
30
(')
CD
<'CD...
en
t All typical values are at VCC ~ 5, T A ~ 25 ·C.
*Hysteresis is the difference between the positive-going input threshold voltage, VT +, and the negative-going input threshold voltage, VT _.
switching characteristics. VCC - 5 V. CL = 15 pF. TA - 25 D C (unless otherwise noted)
tpLH
tpHL
tpLH
tpHL
PARAMETER
Propagation delay time,
low-to-high-Ievel 9utput
Propagation delay time,
Terminal
TO
Bus
TEST CONDITIONS
CL
~
30 pF,
See Figure 1
high-to-Iow-Ievel output
Propagation delay time.
low-to-high-Ievel output
Propagation delay time.
Bus
Terminal
CL
~
30 pF,
See Figure 2
high-to-Iow-Ievel output
tpZH
Output enable time to high level
tpHZ
Output disable time from high level
tpZL
tpLZ
Output enable time to low level
tpZH
tpHZ
tpZL
Output enable time to low level
tpLZ
Output disable time from low level
ten
Output pull-up enable time
tdis
Output pull-up disable time
4-304
FROM
MIN
TYP
MAX
14
20
14
20
10
20
15
22
25
35
ns
ns
13
22
22
35
Output disable time from low level
22
32
Output enable time to high level
Output disable time from high level
20
12
30
20
23
32
19
30
15
22
13
20
TE
Bus
See Figure 3
TE
Terminal
See Figure 4
PE
Terminal
See Figure 5
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
ns
ns
ns
SN75163B
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
PARAMETER MEASUREMENT INFORMATION
DINPUT
f.sv
xs~---3V
--./L _.
'",----ov
tpHl ~
tPLH-.--...
I"'-'--""'""\~II- -V OH
!
• OUTPUT
2.2 V
•
1.0V
VOH
3V
II
VOLTAGE WAVEFORMS
TEST CIRCUIT
FIGURE 1. TERMINAL·TO·BUS PROPAGATION DELAY TIMES
II)
~
.,NPUT
240 n
-f.sv
\:---3V
----": ..
I .
tplH~
tpHl~
I
I
rIjr-----""\1.~.:
L
-V OH
l .SV
o OUTPUT
3.n
OV
G)
>
'Q)
(,)
G)
a:
~
G)
>
'C
VOL
C
Q)
c
::::i
VOLTAGE WAVEFORMS
TEST CIRCUIT
FIGURE 2. BUS·TO·TERMINAL PROPAGATION DELAY TIMES
S2
~5V
tpZH--.,.....
to3V
.ouTPuTI
SI
480n
S20PEN
I
I
tpHZ--..J
'----~OV
I ,..-------~;.
2V
O.BV
3.SV
VOLTAGE WAVEFORMS
TEST CIRCUIT
FIGURE 3. TE·TO·BUS ENABLE AND DISABLE TIMES
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR :5 1 MHz, 50% duty cycle, tr :56 ns,
If :5 ns, Zout ~ 50 11.
B. CL includes probe and jig capacitance.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
4·305
SN75163B
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
PARAMETER MEASUREMENT INFORMATION
.Jt~___
~_
82
TE
INPUT~,":'5_V
______
tPZH"""
o OUTPUT
3 kn
r.:
I
tpHZ~
81 to3V
I
I
820PEN
I
I
tpZL"""
tpLZ~
1.5V
r--90%- -
3V
-0 V
-VOH
:
OV
4V
o OUTPUT
81 to GNO
52 CLOSED
TEST CIRCUIT
VOL TAGE WAVEFORMS
FIGURE 4. TE-TO-TERMINAL ENABLE AND DISABLE TIMES
r
:i"
r-------"\;- - - - -
CD
...c;r
CD
...
3V
1.5V
>~...,;..:'--....--__1I-OUTPUT
~i5--J ~=--__ o V
1/1
:i;
CD
n
CD
;r
.
CD
1/1
VOL TAGE WAVEFORMS
TEST CIRCUIT
FIGURE 5. PE-TO-BUS PULLUP ENABLE AND DISABLE TIMES
NOTES:
A. The input pulse is supplied by a generator having the following characteristics: PRR s 1 MHz, 50% duty cycle, tr ::5 6 ns,
tf "ns, Zout
=
50 II.
B. CL includes probe and jig capacitance.
4-306
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN75163B
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
TYPICAL CHARACTERISTICS
TERMINAL HIGH-LEVEL OUTPUT VOLTAGE
4.0
>I
3.5
...........
&
l! 3.0
"'6
>...
2.5
0
2.0
..J
1.5
J:
I
:z:
1.0
>
0.5
:0
e-:0
..
a;
,.
.i:
en
0
o
vs
HIGH·LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
,
" '\
-5
0.6
.1.
I
VCC=5V
TA = 25°C -
>I
&
co
tC=5 IV
0.5 f---T A = 25°C
...
"'6
>...
0.4
0
0.3
V
:0
'\
o
TERMINAL LOW·LEVEL OUTPUT VOLTAGE
vs
e"
a;
,.
..
..J
""
-10 -15 -20
3:0
0.2
/
..J
I
..J
0
>
'~
/
II
.
II)
Q)
0.1
>
'Q)
o
-25 -30 -35 -40
/
/
/
/
~
(,)
Q)
o
IOH-High-Level Output Current-mA
10
20
30
40
50
IOL -Low-Level Output Current-mA
60
IZ:
~
Q)
FIGURE 7
FIGURE 6
TERMINAL OUTPUT VOLTAGE
vs
C
Q)
c
::::i
BUS INPUT VOLTAGE
4.0
VCC=5V
No load
TA = 25°C
3.5
>I
>
';:
3.0
& 2.5
l!
"'6
>
...
e-":0
90
>
2.0
VT1.5
VT+
1.0
0.5
o
o
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VI-Input Voltage-V
FIGURE 8
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
4-307
SN751638
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
TYPICAL CHARACTERISTICS
BUS LOW·LEVEL QUT~UT VOLTAGE
vs
BUS LOW·LEVEL OUTPUT CURRENT
BUS HfGH·LEVEL OUTPUT VOLTAGE
vs
BUS HIGH·LEVEL OUTPUT CURRENT
4
ii
3
~
r-
:i"
CD
2
>
cr
...
II)
::rJ
~
0
0
-10
0.5
."
0.4
0
0.3
./
Ci
-20
-30
./
8-
"
..
Ii
>
..J
~"\
0
S'
VCC=5V
TA = 25°C
..
>
r-....
~:E:
CD
>I
!'
.1 '" "
o
0.6
'VCC I=5V
TA=25°C
/'
;i 0.2
0
I
..J
'"
-40
>
-60
o
IOH-High·Level Output Current-mA
FIGURE 9
CD
10
20 30
...
II)
3r-~---+--~--~--+-~r--+--~
2r--+---r--+---H--+---r--+-~
OL--L__~__L-~__~__L-~~
1.0
1.1
1.2
1.3
1.4
1.5 1.6
VI-Input Voltage-V
FIGURE 11
4-308
50 60
FIGURE 10
VCC=5V
No load
TA = 25°C
0.9
40
70 80 90 100
IOL -Low·Level Output Current-mA
BUS OUTPUT VOLTAGE
vs
TERMINAL INPUT VOLTAGE
~.
./
0.1
o
-50
./
/
..J
0
vV'
V
/'
. TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 665012 • DAllAS. TEXAS 75265
1.7
SN75164B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
02908. OCTOBER 1985
•
a-Channel Bidirectional Transceiver
•
Power-Up/Power-Down Protection
(Glitch-Free)
OW SMALL OUTLINE PACKAGE
(TOP VIEWI
•
•
SC
TE
ATN+EOI (OR Function) Output to Simplify
Board Layout
REN
IFC
NDAC
GPIB
Designed to Implement Control Bus
Interface for Multi-Controllers
Low-Power Dissipation _ .. 72 mW Max Per
Channel
•
Fast Propagation Times . . . 22 ns Max
•
High-Impedance P-N-P Inputs
•
Receiver Hysteresis ... 650 niV Typ
•
Bus-Terminating Resistors Provided on
Driver Outputs
IFC
NDAC
NRFD
DAV
I/O
PORTS
•
VCC
ATN+EOI
REN
NRFD
DAV
EOI
EOI
ATN
SRO
NC
TERMINAL
1/0 PORTS
ATN
SRO
NC
DC
GND
II
.
N DUAL-IN-LINE PACKAGE
(TOP VIEWI
til
•
SC
TE
No Loading of Bus When Device is Powered
Down (VCC - 0)
REN
IFC
GPIB
The SN75164B features eight driver-receiver
pairs connected in a front-to-back configuration
to form input/output (1/0) ports at both the bus
and terminal sides. All outputs are disabled (at
a high-impedance state) during Vee power-up
and power-down transitions for glitch-free
operation. The direction of data flow through
these driver-receiver pairs is determined by the
De, TE, and se enable signals. The SN75164B
is identical to the SN75162B with the addition
of an OR gate to help simplify board layouts in
several popular applications. The A TN and EOI
signals are ORed to pin 21, which is a standard
totem-pole output.
PRODUCTION DATA d••u....ts .....1. i.for..otl••
.urr••t I. of pilblicoti•• dot.. Produell ••nfonn t•
• pacifi.otl••• p.r tho t.rms of T.... I.str.....ts
:=:~~i~·ir::I:ri =:~i:r ~r:;::::.::~ Rot
U
CD
SRO
SRO
DC
t il
TERMINAL
CD
1/0 PORTS
DAV
EOI
ATN
GND
-.
a::
NDAC
NRFD
NRFD
DAV
EOI
ATN
PORTS
The SN75164B eight-channel general-purpose
interface bus transceiver is a monolithic, highspeed, low-power Schottky device designed to
meet the requirements of IEEE Standard
488-1978. Each transceiver is designed to
provide the bus-management and data-transfer
signals between operating units of a multiplecontroller instrumentation system. When
combined with the SN75160B octal bus
transceiver, the SN75164B provides the
complete 16-wire interface for the IEEE 488 bus.
CD
'G>)
IFC
NDAC
1/0
description
VCC
ATN+EOI
REN
>
';:
C
CD
C
::i
NC-No internal connection.
CHANNEL IDENTIFICATION TABLE
NAME
DC
TE
SC
ATN
SRQ
REN
IFC
EOI
ATN+EOI
DAV
NDAC
NRFD
IDENTITY
CLASS
Direction Control
Talk Enable
System Control
Attention
Service Request
Remote Enable
Interface Clear
Control
Bus
Management
End or Identify
A TN logical OR EOI
Data Valid
Not Data Accepted
Not Ready for Data
Logic
Data
Transfer
Copyright @ 1985, Texas Instruments Incorporated
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-309
SN75164B
OCTAL GENERAL"PURPOSE INTERFACE BUS TRANSCEIVER
The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a
high impedance to the bus when supply voltage Vee is O. The drivers are designed to handle loads up
to 48 milliamperes of sink current. Each receiver features p-n-p transistor inputs for high input impedance
and a guaranteed hysteresis of 400 millivolts for increased noise immunity. All receivers have 3-state outputs
to present a high impedance to the terminal when disabled.
The SN75164B is manufactured in a 22-pin dual-in-line and 24-pin Small Outline package. The SN75164B
is characterized for operation from ooe to 70 oe.
logic symbol t
logic diagram (positive logic)
DC [13](12) "E--N-1/~G-4---"
TE [2](2)
sc [1](1)
•
EN2/G5
r-
S"
CD
...C<"
CD
til
~
CD
n
CD
<"
...
CD
(II
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEG Publication 617·12.
•
[ 1 Denotes pin numbers for OW package.
( ) Denotes pin numbers "for N package.
4-310
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655Q12 • DALLAS, TEXAS 75265
SN75164B
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
RECEIVE/TRANSMIT FUNCTION TABLE
H = high level, L ::= low level, R ::= receive, T = transmit, X = irrelevant
Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the
bus side to the terminal side. Data transfer is non inverting in both directions.
t ATN is a normal transceiver channel that functions additionally 85 an internal direction control or talk enable for EOI whenever the DC
and TE inputs are in the same state. When DC and TE are in oPPosite states, the ATN channel functions as an independent transceiver only.
ATN+ EOI FUNCTION TABLE
INPUTS
OOTPUT
EOI
ATN+EOI
H
X
X
H
L
H
H
L
ATN
L
II
~
Q)
>
'G)
U
Q)
a:::
I I)
~
Q)
>
'~
C
Q)
c
:::::i
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-311
SN75164B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
schematics of inputs and outputs
TYPICAL OF SRQ, NDAC, and NRFD
GPIB 1/0 PORT
EQUIVALENT OF ALL
CONTROL INPUTS
~----rr~-_---~~~---.---.--vcc
vcc---._--gkn
10 kU
NOM
1.7 kll
NOM
NOM
INPUT
GND-4_ _
~_~~
-+-----4----GND
.~L..
____ J
4
INPUT/OUTPUT
~
Circuit inside dashed lines is on GPIB 110 ports only.
rSa»
I - -TYPICAL
-- - - - + - - ATN+EOIOUTPUT
-----t
OF ALL 1/0 PORTS
EXCEPT SRQ, NDAC, and NRFD GPIB I/O PORTS
--
-;:
~
C
~
::::i
+2.5
-3.2
3.7 V to 5 V
5 V to 5.5 V
0.7
2.5
Terminal
-15
-75
Bus
-25
-10
-125
Vee - 0,
No load,
=0
40
Vl(bus) - 0 V to 2.5 V
to 2 V, f
=
1 MHz
~
V
mA
~A
mA
-100
TE, De, and se low
Vee - 5 V to 0 V,
c
-3.2
0
2.5
VI/O
CD
>
-a;
-1.3
2.5 V to 3.7 V
ATN+EOI
lee
V
40
0
Power off
III
CD
Driver disabled
Power on
.
CD
Terminal'
High-level input current
•
a:
0.5
Vl(bus)
lOS
-1.5
Input current at
ATN, EOI
II/Olbus)
UNIT
10L = 4 mA
VI - 5.5 V
ATN, EOI
VI/Olbus)
=
=
-800~
Terminal
Terminal.
IlL
MAX
0.4
8us
Terminal,
IIH
MIN Typt
TEST CONDITIONS
a
120
30
mA
pF
tAli typical values are at Vee = 5 V, TA = 25°e.
tVOH applies for three-state outputs only.
§ Except ATN and EOI terminal pins.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-313
SN75164B
OCTAL GENERAL·PURPOSEINTERFACE BUS TRANSCEIVER
switching characteristics. Vee - 5 V. eL - 15 pF. TA - 25°e (unless otherwise noted)
PARAMETER
FROM
TO
Terminal
Bus
TEST
CONDITIONS
Propagation delay time,
tPLH
tpHL
low-to-high-Ievel output
Propagation delay time,
high-to-Iow-Ievel output
Propagation delay time,
tpLH
low-to-high-Ievel output
Bus
Terminal
(SRa,IIIDAC
IIIRFD)
CL = 30 pF,
See Figure 1
CL = 30 pi',
See Figure 1
Propagation delay time
tPLH
low-to-high-Ievel output
Propagation delay time,
tpHL
tpLH
r-
S·
C
::2.
<
CD
...
(II
~
Propagation delay time,
low-to-high-Ievel output
high-to-Iow-Ievel output
tpZH
Output enable time to high level
tpHZ
Output disable time from high level
tpZL
tpLZ
Output enable time to low level
Output disable time from low level
tpZH
Output enable time to high level
n
tPHZ
Output disable time from high level
~.
tpZL
tpLZ
Output enable time to low level
CD
CD
Terminal
CL = 30 pF,
See Figure 2
high-to-Iow-Ievel output
Propagation delay time,
tpHL
CD
Bus
Output disable time from low level
TYP
MAX
14
20
14
20
29
35
10
20
15
22
UNIT
ns
ns
ns
Terminal ATN
or
Terminal EOI
ATN+EOI
See Figure 3
14
ns
ATN+EOI
See Figure 3
14
ns
Terminal ATN
or
Terminal EOI
TE, DC,
or
BUS
(ATTN, EOI,
REN,IFC,
SC
60
See Figure 4
and DAV)
60
ns
55
TE, DC,
or
45
55
Terminal
See Figure 5
SC
50
45
55
(II
4-314
MIN
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 856012 • DALLAS, TeXAS 76286
ns
SN75164B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
PARAMETER MEASUREMENT INFORMATION
5V
4.3 V
24011
20011
FROM (TERMINALI
OUTPUT UNDER
TEST
FROM (BUSI
OUTPUT UNDER-.....~----4~....>--TEST POINT
TEST
J
CL = 30 pF
(See Note AI
l'
48011
....
LOAO CIRCUIT
BUS
INPUT
1.5 V
1.5 V
3kl1
(Se. Not. AI
!,------_-,--
.L..5V
---Ir .
(See Note BI
"---0 V
-VOH
2.2V
\-1~5: - 0V
v
-3
•
tPLH--j4+I
tPHL~
Ir_-----_:t---VOH
tPHL-l4-+I
BUS
OUTPUT
CL = 30 pF
LOAD CIRCUIT
,._-----""'-----3V
TERMINAL
INPUT
....------<.........~TEST POINT
TERMINAL
OUTPUT
1.5 V
II
...
III
Q)
1.5 V
>
'Q)
VOH
VOLTAGE WAVEFORMS
(,)
Q)
-...
VOLTAGE WAVEFORMS
FIGURE 1. TERMINAL-TO-BUS
PROPAGATION DELAY TIMES
a:
FIGURE 2. BUS-TO-TERMINAL
PROPAGATION DELAY TIMES
I II
Q)
>
TEST
POINT
';:
C
VCC
Q)
c::
:::i
2kl1
FROM
ATN+EOI
VOLTAGE WAVEFORMS
(S.. Note CI
LOAD CIRCUIT
FIGURE 3. ATN
NOTES:
+ EOI PROPAGATION DELAY TIMES
A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ~ 1 MHz, 50% duty cycle, tr ::s 6 ns,
tf ,;6 ns, Zout = 50 n.
C. All diodes are 1 N916 or 1 N3064.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TeXAS 75265
4-315
SN75164B
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
PARAMETER MEASUREMENT INFORMATION
SI
SI
~5V
200n
240n
FROM (BUSI
OUTPUT UNDER ~f--"'-~~ TEST POINT
TEST
FROM (TERMINALI
OUTPUT
--1.----.-------<..--TEST POINT
UNDER TEST
CL· 15 pF
480 n
J(SOONoteAI,::,
CL = 15 pF
(S.eNoteAIJ
LOAD CIRCUIT
•
r-
S'
CD
Ij'
tPZH-I
BUS
I
OUTPUT
I
S10PEN
C
::s,
<
CD
~
I
I+I
I
2V
tPZL--+-----I
BUS
OUTPUT
SI CLOSED
::XJ
--, r--------" r-----
3V
CONTROL
V 15 V
~
INPUT __ J jI\
(See_____
Note BI J,Ij\
1.5_____
V
I \... ___
1'OV
3V
"'1.5 V
J
'f..... -
tPHZ.-I
___
OV
t+- - - - -
I
3kn
LOAD CIRCUIT
--"" r-------, r----
CONTROL
~1.5 V
INPUT __ J
(SOO Note BI
..... _______
0--4.3 V
VOH
90%
I
OV
tPLZ-I..t
I
~II .. 3.5 V
\!1.0 V
'\
0.5 V
' - - - - - - - - ' - - - VOL
tpZH-I
TERMINAL
I
OUTPUT
I
r--
tPHZ-.(
I
------
I 1.5V
SI OPEN_ _....J
tpZL --I
t+TERMINAL
OUTPUT
SI CLOSED
VOLTAGE WAVEFORMS
,...
I
I
I
VOH
90%
tPLZ--i
OV
I
1.0 V
VOLTAGE WAVEFORMS
CD
(')
FIGURE 4. BUS ENABLE AND
DISABLE TIMES
CD
<'CD
C;;
FIGURE 5. TERMINAL ENABLE
AND DISABLE TIMES
NOTES: A, CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following chara'cteristics: PRR
tf s6 ns. Zout = 50 I),
4·316
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
s
1 MHz. 50% duty cycle. tr S 6 ns.
SN75164B
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
TYPICAL CHARACTERISTICS
TERMINAL HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
4_0
>I
.,
'"
l!
"6
>...
"
S-
1_5
.,,.
:r'"I
>
"6
"\
>...
0.4
"
-;;
.,,.
0_3
~
0_2
"
S-
"'\
0
~
0_5
·0
oJ
I
oJ
0
>
"
~
-5
/
oJ
~
o
VCC = 5 V
-TA=25°C
0_5
l!
,,~
1_0
o
J J
8.
:I:
0
>I
~
2_5
oJ
J::.
"""
3_0
2_0
0_6
II
VCC = 5 V
TA=25°C-
3_5
"
-;;
0
TERMINAL LOW-LEVEL OUTPUT VOLTAGE
vs
II
...
V
II)
II)
>
'Q)
o
IOH-High-Level Output Current-rnA
10
20
FIGURE 7
TERMINAL OUTPUT VOLTAGE
(,)
II)
50
60
-...
a:
I I)
II)
>
';:
C
c
::::i
4_0
VCC= 5V
No load
TA = 25°C
3_5
8.
40
II)
vs
BUS INPUT VOLTAGE
l!
30
IOL -Low-Level Output Current-rnA
FIGURE 6
>I
/
0_1
o
-10 -15 -20 -25 -30 -35 -40
V
V
/
/
V
3_0
2_5
"6
>...
2_0
"
1_5
>
1_0
"
S-
0
I
0
Vr-
VT+
0.5
o
o
0_2 0.4 0_6 0.8 1.0 1.2 1.4 1.6 1_8 2_0
VI-Input Voltage-V
FIGURE 8
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
4-317
SN75164B
OCTAL GENERAL"PURPOSE INTERFACE BUS TRANSCEIVER
TYPICAL CHARACTERISTICS
BUS HIGH·LEVEL OUTPUT VOLTAGE
vs
HIGH· LEVEL OUTPUT CURRENT
LOW·LEVEL OUTPUT CURRENT
4
...
;"
.1
r-
5"
CD
2
Vee = 5 V
TA = 25°e
~ r'\.
o
..
o
-10
>...
0.4
"
0.3
0
"ii
-20
..
-'
~"'\
-30
~ 0.2
0
-'
I
-'
0
~
-40
>
V
V
./'
-60
/'
V
o
IOH-High-Level Output Current-rnA
UI
ii
CD
/
0.1
o
-50
10
20
30
UI
50 60
70
80
90 100
FIGURE 10
BUS OUTPUT VOLTAGE
<"CD...
40
IOL -Low· Level Output Current-rnA
FIGURE 9
C"l
CD
/
./
>
>
<"
/"
0.5
e-"
o
...
.'"
VCC = 5 V
TA = 25°C
:l
'\
CD
>I
"0
:If::t
C
0.6
I
~
o
BUS LOW·LEVEL OUTPUT VOLTAGE
vs
BUS CURRENT
vs
vs
TERMINAL INPUT VOLTAGE
BUS VOLTAGE
4
VCC = 5 V
No load
TA = 25°e
>I
2
«
E
.Lc:
3
8.
:l
!!!
:;
"0
>...
e-"
u
2
9"0
,
>
THE UNSHADED
~H---I4--N AREA CONFORMS TO
~I--I---'_+...p.; PARAGRAPH 3.5.3 OF
IEEE STANDARD 488·1978
OL-__L-~__~__- i__- L__- L__~---'
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
-1
FIGURE 11
4-318
o
2
3
4
VI/O(bus)-Bus Voltage-V
VI-Input Voltage-V
FIGURE 12
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5
6
SN75172
QUADRUPLE DIFFERENTIAL LINE DRIVER
D2596, DCTDBER 1980-REVISED SEPTEMBER 1986
•
Meets EIA Standards RS-422-A and RS-485
•
Meets CCITT Recommendations V, 11 and
X.27
J OR N DUAL-IN-liNE PACKAGE
(TOP VIEW)
•
Designed for Multipoint Transmission on
long Bus lines in Noisy Environments
•
3-State Outputs
•
Common-Mode Output Voltage Range of
-7Vt012V
•
Active-High and Active-low Enables
•
Thermal Shutdown Protection
•
Positive- and Negative-Current limiting
•
Operates from Single 5-V Supply
•
low Power Requirements
•
Functionally Interchangeable with
AM26lS31
Vee
lA
lY
lZ
ENABLE G
2Z
2Y
2A
GND
4A
4Y
4Z
ENABLE G
3Z
3Y
3A
•
...
VI
Q)
>
'(jj
CJ
description
Q)
The SN75172 is a monolithic quadruple differential line driver with three-state Dutputs_ It is designed to
meet the requirements of EIA Standards RS-422-A and RS-485 and CCITT Recommendations V, 11 and
X.27, The device is Dptimized for balanced multipoint bus transmission at rates Df up tD 4 megabaud,
Each driver features wide pDsitive and negative cDmmDn-mDde Dutput vDltage ranges making it suitable
for party-line applicatiDns in nDisy environments,
The SN75172 provides pDsitive- and negative-current limiting and thermal shutdDwn for protectiDn from
line fault cDnditiDns Dn the transmissiDn bus line. Shutdown Dccurs at a junctiDn temperature Df
approximately 150 cC. This device offers Dptimum perfDrmance when used with the SN75173 Dr SN75175
quadruple differential line receivers,
The SN75172 is characterized fDr DperatiDn from OCC tD 70 cC,
logic symbol t
FUNCTION TABLE (EACH DRIVER)
INPUT ENABLES
OUTPUTS
A
G
G
Y
G
H
H
X
H
L
G
L
H
X
L
H
H
X
L
H
L
L
X
L
L
H
X
L
H
Z
Z
1Y
1Z
2A
3A
Z
H = high level, L = low level
X = irrelevant, Z = high impedance (off)
2Y
2Z
3Y
3Z
4A
4Y
4Z
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~:~~i~ai~:I~~e ~!~~~~ti~; :1~O::~:~:t::S~S not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1980, Texas Instruments Incorporated
4-319
a:
--...
VI
Q)
>
';:
o
Q)
c:
~
SN75172
QUADRUPLE DIFFERENTIAL LINE DRIVER
logic diagram (positive logic)
G
(41
G
(121
(2)
lA ...;.;(1.;..1---'---1
(31
(61
2A
(7)
(5)
(101
3A -:..;;(9.;..1_ _ _-1
(111
(14)
4A ....:,.(1;,.;;5.;..1_ _ _-I
(13)
1Y
lZ
2Y
2Z
3Y
3Z
4Y
4Z
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
VCC
---------4t----
-
-
-
---
- - - - -....- - - VCC
--.--~
INPUT - -............--1
,---OUTPUT
--- ----I
Data inputs: Req' - 3 kG NOM
Enable !nputs: Req - 8 kG NOM
4-320
-
-
-
- -.....- -...- - - GND
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
SN15112
QUADRUPLE DIFFERENTIAL LINE DRIVER
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Continuous total dissipation at (or below)
25 DC free-air temperature (see Note 2): J package ........................... 1375 mW
N package . . . . . . . . . . . . . . . . . . . . . . . . . .. 11 50 mW
Operating free-air temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O°C to 70 DC
Storage temperature range ......................................... - 65 DC to 1 50 DC
Lead temperature 1,6 mm (1116 inch) from case for 60 seconds: J package ............ 300 DC
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ..... , ...... 260 DC
NOTES:
1. All voltage values are with respect to the network ground terminal.
2. For operation above 25°C free-air temperature, derate the J package to 880 mW at 70°C at the rate of 11.0 mW/oC and
the N package to 736 mW at 70 0 e at the rate of 9.2 mW/oC. In the J package, SN75172 chips are alloy mounted.
recommended operating conditions
Supply voltage, VCC
High-level input voltage, VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
2
Low-level input voltage, VIL
High-level output current, IOH
Low-level output current, IOL
0
Operating free-air temperature. T A
f!
>
'i)
CD
V
0.8
Common-mode output voltage, VOC
II
V
-7 to 12
V
-60
mA
60
mA
70
°c
U
-...
CD
a:
I I)
CD
>
';::
C
•
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 76265
CD
c
::::i
4-321
SN75172
QUADRUPLE DIFFERENTIAL LINE DRIVER
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
Input clamp voltage
11= -18 mA
Output voltage
10 - 0
IV ODll
Differential output voltage
10 - 0
IV OD21
VOD3
41 VODI
•
VOC
41 V ocl
r-
5·
CD
C
:::!.
<
ii1
::a
~
-
TEST CONDITIONS
VIK
Vo
Differential output voltage
Differential output voltage
~
ii1
See Figure 1
See Figure 1
V
0
6
V
1.5
6
V
5
V
5
V
±0.2
V
+3
-1
V
±0.2
V
±100
~A
±100
~A
~A
2
V
1.5
2.5
1.5
differential output voltage t
RL = 54
°
or 100 0, See Figure 1
Change in magnitude of
common-mode output voltage:t:
10
Output current with power off
10Z
High-impedance-state output current
VCC = 0,
Vo = -7Vto12V
VO--7VtoI2V
IIH
High-level input current
VI
IlL
Low-level input current
VI - 0.5 V
20
-360
Vo -
-180
lOS
Short-circuit output current
ICC
Supply current lall driversl
=
2.7 V
-7 V
180
Vo = VCC
Vo - 12 V
No load
UNIT
~ VOD1'
See Note 3
Common~mode output voltage §
MAX
-1.5
Change in magnitude of
CD
!.
RL = 1000,
RL-540,
Typt
MIN
~A
mA
500
I Outputs enabled
38
I Outputs disabled
18
60
40
mA
t All typical values are at VCC = 5 V and T A = 25 ·C.
t 41VODI and 41Voci are the changes in magnitude of VOD an"oc, 'respectively, that occur when the input i,s changed from a high
level to a low level.
§ In EIA Standard RS-422-A, Voc, which is the average of the two output voltages with respect to ground, is called output offset voltage, VOS.
NOTE 3: See EIA Standard RS-485 Figure 3-5, Test Termination Measurement 2.
SYMBOL EQUIVALENTS
DATA SHEET PARAMETER
Vo
I V ODll
IV OD21
RS-485
RS-422-A
Vas' Vob
Va
V t IRL = 100
Vas. Vob
VA
m
IV OD31
41 V ODI
Voe
41 Vocl
lOS
10
4-322
I IVtl-IVtl I
IVosl
I Vas - Vas I
lisal. lisbl
lixal. Ilxbl
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
m
V t IRL = 54
Vt ITest Termination
Measurement 2)
I IVtl-IVtl I
IVosl
I Vas - Vas I
lis· lib
SN75172
QUADRUPLE DIFFERENTIAL LINE DRIVER
switching characteristics. Vee - 5 V. T A - 25°e
PARAMETER
too
Differential-output delay time
tTO
Differential-output transition time
tpZH
Output enable time to high level
tpZL
Output enable time to low level
tpHZ
Output disable time from high level
tPLZ
Output disable time from low level
MIN
TEST CONDITIONS
RL
=
5411.
TV,"
MAX
45
65
ns
80
120
ns
See Figure 2
UNIT
RL - 11011.
RL - 11011.
See Figure 3
80
120
ns
See Figure 4
45
ns
RL - 11011.
RL - 11011.
See Figure 3
See Figure 4
78
80
115
111
30
ns
ns
PARAMETER MEASUREMENT INFORMATION
II
i
~ V~I~D_2 ~
_____
____
~
CD
:L JlVOC
>
'Q)
CJ
FIGURE 1. DIFFERENTIAL AND COMMON-MODE OUTPUT VOLTAGES
CD
a:
~;5:
INPUT
~ ••~.
(SoaN_AI
'00
'~
C
I
It-tt- 'DO
--w-.t
I
50n
CD
>
~OV
:
GENERATOR
~
3V
CD
c
I
T- ..2.5V
~
OUTPUT
3V
50%
'TO ~
90%
I
.
:
10%
It-
I
I
__
:::i
50%
"'-2.5 V
Ie- tTO
VOLTAGE WAVEFORMS
TEST CIRCUIT
FIGURE 2. DRIVER DIFFERENTIAL-OUTPUT DELAY AND TRANSITION TIMES
NOTES:
A. The input pulse is supplied by a generator having the following characteristics: tr :s; 5 ns, tf ::s; 5 ns, PRR
cycle = 50%. Zo = 50 11.
B. CL includes probe and stray capacitance.
TEXAS
..If
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
s
1 MHz, duty
4-323
8N75172
QUADRUPLE DIFFERENTIAL LINE DRIVER
PARAMETER MEASUREMENT INFORMATION
INPUT
S1
o V or 3 v - I - - - - 1
~n~'""""i:>--...- .. OUTPUT
----...
GENERATOR
(SeE NOTE Al
~~5-:-
:...Jl"-'
I+-+I-tPZH:
I
I
I
---- J
2.3 V
I
I
RL-110!l
50P~
r-0 . 5 V
-Jl-VOH
: I l'~
OUTPUT
50 !l
3V
~OV
--+I
CL (SEE NOTE BI
I
I
V
off
~
0 V
I4-tPHZ
3V
-:: (SEE NOTE CI
TEST CIRCUIT
VOLTAGE WAVEFORMS
FIGURE 3. tpZH AND tPHZ
r-
s·
...c
5V
11)
~.
-
S1
o V or 3 V'--t----I
OUTPUT
til
1
::0
11)
n
11)
~:~--
INPUJf.5V
GENERATOR
(SEE NOTE Al
~.
5O!l
L - - -
CL-50pF
-·J(SEE NOTE BI
I
3V
-:: (SEE NOTE CI
til
3V
I
I
~tPZL I
I
I
0V
I4----+t- tpLZ
OUTPU-T---~.3V
~ 0~5
"--_..:I
f-
V
VOL
.".
TEST CIRCUIT
VOLTAGE WAVEFORMS
FIGURE 4. tpZL AND tpLZ
NOTES: A. The input pulse is supplied by a generator having the following characteristics: tf :5 5 ns, tf :5 5 ns, PRR
cycle = 50%, Zout ~ 50!l.
B. CL include probe and jig capacitance.
C. To test the active· low enable G, ground G and apply an inverted waveform to G.
4-324
.
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
s
1 MHz, duty
SN75172
QUADRUPLE DIFFERENTIAL LINE DRIVER
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
5
--
> 4.5
I
.
[!l,
4
~
3.5
~
3
"
5
I
VCC = 5 V
TA - 25°C
-....
>
............
Qj
2
'"
\
~
4
~
3.5
i
3
~
2.5
....~
2
....
~
1.5
.:.
1
I
_ VCC - 5 V
TA = 25°C
:f 1.5
:ko 1
o
> 0.5
0.5
o
o
o
o
-20 -40 -60
-80 - 100 - 120
High-Level Output Current-rnA
I
I
- ---
CD
'"o
~
3
20
40
60
80
100
IOL -Low-Level Output Current-rnA
>
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
o
2.5
cr:
1/1
"(I)
>
"~
C
(I)
c
::i
Ou~put 'Disab'ed
40 TA = 25°C
30
c(
..........
. . . i'---
2
.~
! 1.5
~
Q
~
10
tJ
" Vce - 0 V
Ire. J
cc I. 5 V
o
- -30 ~
\
$10.5
20
" 0
=
e- - 10
o"
I -20
t'--..
1\
I
Q
t
E
'\
iii
00
-
50
1.
- 5 V
I-TA = 25°C
...........
=
~
i'-
120
FIGURE 6
I
vcc
........
(I)
>
"Qi
()
(I)
DIFFERENTIAL OUTPUT VOLT AGE
vs
OUTPUT CURRENT
~ 3.5
1/1
"-
f--
/
FIGURE 5
4
I
a;
J:.
>
4.5
I
~
02.5
~
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
-40
\
10 20 30 40 50 60 70 80 90 100
IO-Output Current-rnA
-50
-25-20-15-10-5 0
5 10 15 20 25
YO-Output Voltage-V
FIGURE 8
FIGURE 7
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-325
8N75172
QUADRUPLE DIFFERENTIAL LINE DRIVER
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
100
SUPPLY CURRENT
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
II
30
I
90 r-No Load
,I
Outputs Enabled
80 r- TA = 25 0 e
c:(
E 70
I
(,)
>
is.
Co
::I
~
I
(,)
r5'
J}
CD
..
..
o
o
<'CD
-
~
~
2
>
is.
Co
::I
,... GROUNDED
---
~
20
10
C
)
30
:;
(,) 15
~NPUTS
OPEN\
40
~ 10
(,)
J}
/
5
/
3
4
5
6
7
o
o
8
L!
Vee-Supply Voltage-V
1/1
FIGURE 9
l:J
/
~
f'
INPUTS
50
/
~I: 20
j
1:
~ 60
:;
1
1
No Load.
25 r- Inputs Open
Output Disabled
c:(
E
TA = 25°e
V
/
/
/
V
V
/
/
2
3
4
5
6
vee-Supply Voltage-V
7
8
FIGURE 10
CD
n
CD
<'CD
..
TYPICAL APPLICA nON
1/1
1/4 SN75173
1/4 SN75174
1/4 SN75173
1/4SN75175
1/4 SN75172
1/4 SN75173
1/4 SN75173
1/4SN75174
NOTE A: The line length should be terminated at both ends in its characteristic impedance. Stub lengths off the main line should be kept
as short as possible.
FIGURE 11
4-326
TEXAS •
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
5N75173
QUADRUPLE DIFFERENTIAL LINE RECEIVER
02600, OCTOBER 1980-SEPTEMBER 1986
•
Meets EIA Standards RS-422-A. RS-423-A.
and RS-485
•
Meets CCITT Recommendations V.1 O.
V.11. X.26. and X.27
D, J. OR N
DUAL-IN-LiNE PACKAGE
(TOP VIEWI
•
Designed for Multipoint Bus Transmission on
Long Bus Lines in Noisy Environments
•
3-State Outputs
•
Common-Mode Input Voltage
Range . . . - 12 to 12 V
•
Input Sensitivity ... ± 200 mV
•
Input Hysteresis ... 50 mV Typ
•
High Input Impedance . . . 12 kO Min
•
Operates from Single 5-Volt Supply
•
Low Power Requirements
•
Plug-In Replacement for AM26LS32
Vee
18
1A
48
4A
4Y
1Y
G
G
2Y
2A
28
3Y
3A
38
GND
logic symbol
II...
G
G
1/1
CI)
(31
lA
>
'G)
lY
18
description
CJ
2A
The SN75173 is a monolithic quadruple
differential line receiver with three-state outputs.
It is designed to meet the requirements of EIA
Standards RS-422-A, RS-423-A, and RS-485
and several CCITT recommendations. The
device is optimized for balanced multipoint bus
transmission at rates up to 10 megabits per
second. Each of the two pairs of receivers has
a common active-high enable. The device
features high input impedance. input hysteresis
for increased noise immunity. and input
sensitivity of ± 200 millivolts over a commonmode input voltage range of -12 to 12 volts.
The SN75173 is designed for optimum
performance when used with the SN75172 or
SN75174 quadruple differential line drivers.
(51
28
-...
CI)
a::
2Y
1/1
3A
(111
38
CI)
3Y
>
';:
4A
(131
48
C
4Y
CI)
c:
:.::i
logic diagram (positive logic)
>--+-,,(3;.;,1 1 Y
The SN75173 is characterized for operation from
OOC to 70°C.
(111 3y
4A':"(1.:...4;,;,1--1..... ,
(131 4y
48 (151
PRODUCTION DATA do.umlnts .ontaln information
.u..ant II of publi••tion datI. Productl .onform 10
spacifications per Ihl tarms of TI..I Inatrumlnts
standard warranty. Production p:roeelsing dOl. nat
n.callarily include tasting of all paramatan.
Copyright @ 1980. Texas Instruments Incorporated
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-327
SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVER
FUNCTION TABLE (EACH RECEIVER)
DIFFERENTIAL
A-B
VID ;" 0.2 V
-0.2 V < VID < 0.2 V
VID '" -0.2 V
II
OUTPUT
G
G
Y
H
X
H
X
L
H
X
H
?
X
L
?
H
X
L
X
L
H
Z
L
X
H
L
X
?
Z
ENABLES
L
= high level
= low level
= irrelevant
= indeterminate
= high-impedance (off)
schematics of inputs and outputs
r-
5'
..:c:CD
C
.-
EQUIVALENT OF A OR B INPUT
::J:J
CD
(')
G INPUT
VCC-------.----.--VCC----------~----B.3 kll
CD
Cil
EQUIVALENT OF G OR
NOM
16.B kll
NOM
INPUT ___-~.::.:.:.:._I_INPUT-..........--t
CD
~'
Cil
4-328
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
TYPICAL OF ALL OUTPUTS
SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage, A or B inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 V
Differential input voltage (see Note 2) ......................................... ± 25 V
Enable input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Low-level output current ................................................... 50 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 3):
D Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 950 mW
J Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1150 mW
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OOC to 70 0 e
Storage temperature range ......................................... - 65 °e to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............ 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package ........ 260 0 e
NOTES:
1. All voltage values, except differential input voltage, are with respect to network ground terminal.
2. Differential-input voltage is measured at the non inverting input with respect to the corresponding inverting input.
3. For operation above 25 De free-air temperature, derate the D package to 608 mW at 70 De at the rate of 7.6 mW/De, the
J package to 656 mW at 70 De at the rate of 8.2 mW/De, and the N package to 736 mW at 70 De at the rate of 9.2 mW/De.
In the J package, SN75173 chips are glass mounted.
recommended operating conditions
a
...
en
CD
>
"Gi
u
Supply voltage, Vee
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
Common-mode input voltage, V'C
±12
V
Differential input voltage, VID
±12
V
V
High·level input voltage, VIH
2
Low-level input voltage, VIL
O.B
High-level output current, IOH
low-level output current, IOL
Operating free-air temperature, T A
0
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
V
-400
pA
16
mA
De
70
-...
~
en
CD
"~
o
CD
c::
::::i
4-329
SN75173
QUADRUPLE DIFFERENTIAL LINE
RECEIVE~
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unles! otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VTH
Differential-input high-threshold voltage
Vo = 2.7 V,
10 = -0.4 mA
VTL
Differential-input low-thresho!d voltage
Vo = 0.5 V,
10 = 16 mA
Vhys
Hysteresis §
VIK
VOH
Enable-input clamp voltage
High-level output voltage
VID - 200 mV,
VOL
Low-level output voltage
VID = -200 mV,
10Z
High-impedance-state output current
II
Line input current
IIH
High-level enable-input current
Vo - 0.4 V to 2.4 V
Other input at 0 V,
VI = 12 V
See Note 4
7V
I VIVIH = 2.7 V
IlL
ri
low-level enable-input current
Input resistance
lOS
ICC
Short-circuit output current'
Supply current
TYpt
MAX
0.2
-0.2;
50
11= -18mA
-1.5
-400~
10H -
2.7
0.45
IIOL = 8 mA
IIOL = 16 mA
0.5
±20
1
-0.8
20
-100
I
VIL - 0.4 V
12
UNIT
V
V
mV
V
V
V
~
mA
~A
~A
kll
-15
-85
Outputs disabled
70
mA
mA
t All typical values are at VCC = 5 V, TA = 25·C.
0* The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for threshold
voltage levels only.
§ Hysteresis is the difference between the positive-going input threshold voltege, VT +, and the negative-going input threshold voltege,
VT _. See Figure 4.
, Not more than one output shQuld be shorted at a time and the duration of the short-circuit should not exceed one second.
NOTE 4: Refer to EIA Standard RS-422-A and RS-423-A for exact conditions.
switching characteristics, Vee - 5 V, TA - 25°e
tPZH
tpZL
PARAMETER
Propagation delay time, low-to-high-Ievel output
Propagation delay time, hillh-to-Iow-Ievel output
Output enable time to high level
Output enable time to low level
tpHZ
tpLZ
Output disable time from high level
Output disable time from low level
tPLH
tpHL
4-330
0
TEST CONDITIONS
VID = -1.5 V to 1.5 V, CL = 15 pF,
See Figure 1
See Figure 2
CL=15pF,
See Figure 3
CL-15pF,
5 pF,
See Figure 2
CL
CL = 5 pF,
See Figure 3
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 855012' • DALLAS. TE~f.S 76285
MIN
TVP
MAX
20
22
35
35
17
20
21
30
22
25
30
40
UNIT
ns
ns
ns
ns
ns
ns
SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVER
PARAMETER MEASUREMENT INFORMATION
IN~l.SV
I
i
OUTPUT
I
~
tPLH..j
-l.S V
-.I ,... tPHL
~VO"
OUTPUT
1.3 V
1.3 V
.
VOL
"::"
TEST CIRCUIT
VOLTAGE WAVEFORMS
a.
FIGURE 1. tPLH. tPHL
vcc
SJ2kll
I/)
:Ft+lr-
INPUT
1.3 V
I
tpZH
I
>
"G)
--OV
-.
1.3 V
..I 14tpHZ
Q)
3V
f.)
Q)
a:
O.SV
~~VOH
1,,3 V
:-l -S1 closed
OUTPUT
Sl open
---=OV
=1.4V
I /)
Q)
>
"l:
C
Q)
C
::i
"::"
TEST CIRCUIT
VOLTAGE WAVEFORMS
FIGURE 2. tPHZ. tpZH
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR "
tr :s 6 ns, tf :S 6 ns, Zout = SO D.
B. CL includes probe and jig capacitance.
C. All diodes are lN916 or equivalent.
D. To test the active-low enable
.
TA - 25°C
I
>
4
.
I
ell
i..
'"
3
Vie -12 V
I
VT-VT+
VIC I0
v~--t IVT+
vi
ell
12 V
>
:;Q.
:;
VT-- I--
I
...J:...
>
J:
0
3
R~
0
f--
j
Q.
:;
~
'0
I--
I
VT+
4
S
D
2
2
.~
0
1,,\ ~
1,,\~ VVCC'1
I~ ~
Vce - 5 V
I
~~
>
o
-75
-25 0
25 50 75 100 125
o
o
Vlo-Olfferentiallnput Voltage-mV
-10
-20
-30
-40
10H-High-Level Output Current-rnA
FIGURE 4
4-332
I
I
Vee = 5.25 V
~~
~~
J:
0
-125.
= 4.75 V
FIGURE 5
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
-50
5N75173
QUADRUPLE DIFFERENTIAL LINE RECEIVER
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.6
5.0
>
I
4.5
I
II>
CI
4.0
II>
CI
Q
3.5
"0
S
3.0
0
iii
>
II>
2.5
0
iii
....
2.0
....II>
CI
1.5
I
1.0
.l!!
>
~
.i:
:E
l:
0
>
./
0.5
/
:!
>
0.4
SCo
S
0.3
>
~
0.2
/
Q
....
....I
0
>
Vee - 5 V
VIO - 0.2 V
IOH = - 44O I'A
0.5
o
V
Vee - 5 V
TA - 25°C
>
o
I
I
I
10
20
30
40
50
60
70
/'
/
,/
/V
II
III
~
0.1
CD
>
'iii
o
o
80
C.)
5
10
15
20
25
30
IOL -Low-Level Output Current-rnA
T A - Free-Air Ternperature- °e
CD
a:
I II
~
FIGURE 6
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
5
VIO - 0.2 V
Load - 8 kO to ground
TA - 25°C
>
I
0.4
>
.l!!Q
....
0.2
'"
"0
:!
SCo
S
0
II
I
/'
Vee - 5 V
3
I
Vee = 4.75 V_
2
I
0
....Q
....
CD
c:
:J
>
~
I
0
C
Vee - 5.25 V-
I
0.3
0
iii
>
II>
4
.
>
SCo
S
>
';::
OUTPUT VOLTAGE
vs
ENABLE G VOLTAGE
0.5
II>
CI
CD
FIGURE 7
>
0.1
Vee - 5 V
VIO - -0.2 V
IOL - 8 rnA
I
I
>
0
o
10
20
30
o
40
50
60
70
80
o
0.5
1.5
2
2.5
3
VI-Enable G Voltage-V
TA-Free-Air Ternperature- °e
FIGURE 8
FIGURE 9
TEXAS . "
INSTRUMENTS
POST
OF~ICE
BOX 655012 • DALLAS, TEXAS 75265
4-333
SN15173
QUADRUPLE D,IFFERENTIAL LINE RECEIVER
TYPICAL CHARACTERISTICS
INPUT CURRENT
vs
INPUT VOLTAGE
OUTPUT VOLTAGE
vs
ENABLE G VOLTAGE
6
I
Vee -
.L
5.25 V
5
>
..
Vee - 4.75 V
I
C>
4
1.0
VIO ~ -0.2 V
Load - 1 kO to Vee
TA - 25°e
" Vee I-
E
II
I
I
0.25
~
::s
0
E
3
U
;
~ - 0.25 f--+-t-7'i'~-t-:~~*~'i-"n~+"'rl
I
-0.5 h""'f---I---,.4+1'<-
0
0
0.5
c(
5 V
110
>
;
0.
;
0.75
2
=
>
I"'"
5'
CD
.c<'
.
o
o
CD
0.5
1.5
fn
- 1 .0 .........-"---'-"'-'.........-'"-Uo-lU.l-'--L"--'-'-.........L.>..->L..>->I
-8 -6 -4 -2 0
2
4
6
8 10 12
3
VI-Input Voltage-V
FIGURE 11
FIGURE 10
CD
<'
CD
III
2.5
VI-Enable G Voltage-V
III
.
2
TYPICAL APPLICATION
1/4 SN75172
1/4 SN75175
UP TO 32
1/4 SN75173
1/4 SN75174
DRIVER/RECEIVER PAIRS
1/4 SN75172
1/4 SN75173
1/4 SN75173
1/4 SN75174
NOTE 4: The line should be terminated at both ends in its characteristic impedance. Stub lengths off the main line should be kept as short
as possible.
4-334
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN75174
QUADRUPLE DIFFERENTIAL LINE DRIVER
02601, DCTDBER 1980-REVISED OCTDBER 1986
•
•
Meets EIA Standards RS-422-A and RS-485
and CCITT Recommendations V, 11 and
X.27
J OR N DUAL-IN-LiNE PACKAGE
(TOP VIEW)
Designed for Multipoint Transmission on
long Bus lines in Noisy Environments
•
3-State Outputs
•
Common-Mode Output Voltage Range of
-7 V to 12 V
•
Active-High Enable
•
Thermal Shutdown Protection
•
Positive- and Negative-Current limiting
•
Operates from Single 5-V Supply
•
low Power Requirements
Vee
1A
1Y
1Z
1,2EN
2Z
2Y
2A
GND
4A
4Y
4Z
3,4EN
3Z
3Y
3A
FUNCTION TABLE (EACH DRIVER)
•
ENABLE
H
H
H
L
L
H
L
H
X
L
Z
Z
Functionally Interchangeable with MC3487
description
--
OUTPUTS
INPUT
Y
Z
...
I II
Q)
>
'Qi
H ~ TTL high level,
L ~ TTL low level,
X = irrelevant,
Z ~ High impedance (off)
(.l
The SN75174 is a monolithic quadruple
differential line driver with three-state outputs.
It is designed to meet the requirements of EIA
Standards RS-422-A and RS-485 and eelTT
Recommendations V.11 and X.27. The device
is optimized for balanced multipoint bus transmission at rates up to 4 megabaud. Each driver features wide
positive and negative common-mode output voltage ranges making it suitable for party-line applications
in noisy environments.
Q)
--...
a:
Ul
Q)
>
';::
Cl
Q)
The SN75174 provides positive- and negative-current limiting and thermal shutdown for protection from
line fault cDnditions on the transmissiDn bus line. ShutdDwn occurs at a junction temperature Df
approximately 150 oe, This device Dffers Dptimum perfDrmance when used with the SN75173 Dr SN75175
quadruple differential line receivers.
The SN75174 is characterized fDr DperatiDn from ooe tD 70 oe.
logic symbol t
logic diagram, each driver (positive logic)
,:=r:
1,2EN
1Y
1A
1Z
2Y
2A
2Z
3,4EN
3Y
3A
3Z
4A
tThis symbol is in accordance with ANSI/IEEE Std 91 1984 and
lEe Publication 617-12.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~::~~i~at::I~;r~ ~!~:i~~ti:fn :llo::~:~:t:rOs~s
not
Copyright © , 986, Texas Instruments Incorporated
TEXAS
-I!}
INSTRUMENTS
POST OFF!CE·BOX 655012 • DALLAS, TEXAS 75265
r::::
:::i
4-335
SN75174
QUADRUPLE DIFFERENTIAL LINE DRIVER
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
VCC----------------e--------
- - -....------VCC,
Req
INPUT ---...-.......---/
...------- OUTPUT
r-
5'
(I)
~--~~----GND
Data Inputs: Req = 3 kll NOM
Enable Inputs: Req = 8 kll NOM
...c
<'
...
(I)
(/)
::0
absolute
(I)
(')
(I)
m~ximum
ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Continuous total dissipation at (or below) 25 DC free-air temperature (see Note 2):
J package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1375 mW
N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1625 mW
Operating free-air temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 DC to 70 DC
Storage temperature range ......................................... - 65 DC to 150 DC
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package. . . . . . . . . . .. 300 DC
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ............ 260 DC
<'
...
(I)
(/)
NOTES:
1. All voltage values are with respect to the network terminal.
2. For operation above 25°e free·air temperature, derate the J package to BBO mW at 70 0 e at the rate of 11.0 mw/oe and
'
the N package to 1040 mW at 70 0 e at the rate of 13.0 mw/oe.
recommended operating conditions
Supply voltage, Vee
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
2
High-level input voltage, VIH
Low-Level input voltage, VIL
Common-mode output voltage,
Voe
High-level output curent, IOH
Low-level output current, IOL
Operating free-air temperature, T A
4-336
V
O.B
-7to12
0
TEXAS
..If
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75266
V
V
60
mA
60
mA
70
°e
SN75174
QUADRUPLE DIFFERENTIAL LINE DRIVER
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
Vo
Output voltage
I V ODll
Differential output voltage
I V OD21
Differential output voltage
VOD3
TEST CONOITIONS
MIN
TYpt
11= -18 rnA
VIL - 0.8 V,
VIH - 2 V,
10H = -33 rnA
VIL - 0.8 V,
VIH - 2 V,
10L = 33 rnA
Differential output voltage
VOC
1.1
V
10 - 0
0
6
V
10 - 0
1.5
6
V
RL = 100ll,
See Figure 1
RL = 54 Il,
See Note 3
See Figure 1
y, VODl
V
2
1.5
1.5
2.5
RL = 541lor 100ll,
See Figure 1
5
V
5
V
±0.2
V
+3
-1
V
±0.2
V
±100
I'A
CJ
±100
~
a:
common mode output voltage:;
10
Output current with power off
10Z
High-impedance-state output current
VCC - 0,
VO--7Vto12V
Vo -
- 7 V to 12 V
IIH
High-level input current
VI = 2.7V
20
~
IlL
Low-level input current
VI - 0.5 V
-360
~
Vo = -7 V
-250
lOS
Short-circuit output current
ICC
Supply current (all drivers)
II
.
en
Q)
Change in magnitude of
alvocl
.v
V
differential output voltage*
Common mode output voltage
UNIT
3.7
Change in magnitude of
alvODI
MAX
-1.5
180
Vo - VCC
Vo - 12 V
Q)
--.
en
Q)
>
"l:
rnA
C
500
I Outputs ~nabled
I Oututs disabled
No load
>
"iii
38
18
60
40
Q)
c
::::;
rnA
t All typical values are at VCC = 5 V and T A = 25°C.
*aIVODI and alvocl are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high
level to a low leve,".
NOTE 3: See EIA Standard RS-485 Figure 3.5, Test Termination Measurement 2.
switchjng characteristics. Vee" 5 V. TA = 25°e
TYP
MAX
45
65
ns
80
120
ns
See Figure 3
80
120
ns
RL - 110 Il,
See Figure 4
55
ns
Outut disable time from high level
RL - 110 Il,
See Figure 3
75
80
115
Output disable time from low level
RL - 110 Il,
See Figure 4
18
30
ns
PARAMETER
too
Differential-output delay time
tTD
Differential-output transition" time
tpZH
TEST CONOITIONS
RL = 54 Il,
See Figure 2
Output enable time to high level
RL = 110 Il,
tpZL
Output enable time to low level
tpHZ
tpLZ
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MIN
UNIT
ns
4-337
SN75174
.
.
QUADRUPLE DIFFERENtiAL LINE DRIVER
SYMBOl EQUIVALENTS
OATA SHEET PARAMETER
RS-422-A
RS-4B5
Vo
Voa. Vob
Vo
Vt (RL = 100 Il)
Voa. Vob
VO
Vt (RL = 540)
Vt (Test Termination
I V ODll
I V OD21
I vODa I
Measurement 2)
~IVODI
Voe
IIVtl -
lVosl
IVosl
~IVoel
lOS
10
I Vos - Vos I
Iisal. Ilsbl
I Vos - iTos I
Ilxal. Ilxbl
lia. lib
IVtl1
IIVtl -
IVtl1
11- - - - - - PARAMETER MEASUREMENT INFORMATION
!::
::s
CD
C
::!.
~
U;
:xl
FIGURE 1. DIFFERENTIAL AND COMMON-MODE OUTPUT VOLTAGES
~
CD
c:CD
---av
~
...en
INPUT
1.5V
I
OUTPUT
-*+I
too
GENERATOR
(See Note A)
" -_ _ _r--,'av
I
CL-50pF
(See Note Bl
1.5V
I
ov
If--M-- too
+ --2.5V
OUTPUT
-2.5V
~tTO
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteritics: tr S 5 ns. tf "
duty cycle = 50%. Zo = 50 Il.
B. CL includes probe and stray capacitance.
FIGURE 2_ DIFFERENTIAL-OUTPUT DELAY AND TRANSITION TIMES
4-338
TEXAS ."
INSTRUMENTS
POST OFFiCe BOX 665012 • DALlAS, TEXAS 75265
5 ns. PRR s 1 MHz.
SN75174
QUADRUPLE DIFFERENTIAL LINE DRIVER
PARAMETER MEASUREMENT INFORMATION
3VorOV
"""<>--+-.--OUTPUT
"~::
~tpZH
I
O.SV
-~-VOH
I
f~
I I
GENERATOR
(See Note AI
OUTPUT
I
2.3 V
=
_..'------o..l
Voff = 0 V
tpHZ --,.----.,
TEST CIRCUIT
VOLTAGE WAVEFORMS
FIGURE 3. tPZH AND tpHZ
5V
RL-ll00
~)--+""'-OUTPUT
o V to 3 V-+---I
GENERATOR
(See Note AI
I
50 0
L ___ -.l
\~s~
INP~1'5V
tpZL
CL = 50PFI
(See Note BI
=
14
.,
(
1~5V
\.3V
.
=
II)
Q)
>
'iii
(,)
Q)
a:
~tPLZ
I
OUTPUT
--::
II
...
f O;~
--.
I I)
Q)
>
f- VOL
';::
C
Q)
t::
VOLTAGE WAVEFORMS
TEST CIRCUIT
:::i
FIGURE 4. tPZL AND tpLZ
NOTES: A. The input pulse is supplied by a generator having the following characteritics: PRR oS 1 MHz, duty cycle
tf oS 5 ns, Zo = 50 O.
B. CL includes probe and stray capacitance.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
= 50%, tr
oS 5 ns,
4-339
SN75174
QUADRUPLE DIFFERENTIAL LINE DRIVER
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
vs
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
5
>
I
!
5
I
VCC ~ 5 V
TA = 25°C
4.5
4
r-- r--
3.5
>
.,I
'"
~
0
-.........
>
;
..............
~
"""-\
I
VCC ~ 5 V
TA - 25°C
4.5
4
I
3.5
/
3
0
iii
2.5
>
....
..
2
....0
....I
~
1.5
II
o
-20
-40
-60-80
----
/
0
>
-100 -120
o
20
High-Level Output Current - rnA
40
OUTPUT CURRENT
.t:
>
;
2.5
I
.........
0
iii
~
!
TA - 25°C
..........
.............
2
,
"""- ,
>
20
~
10
0.5
"
eo"
I
-10
-
-30
;
\
o
'i
U
"\
1.5
o
10 20 30 40
.II . I. J
_ Output disabled
TA - 25°C
o
,VCC - OV
~jO'"
r.:~·VCC
= 5 V
-20
II
50 60 70 80 90 100
-50
-25-20 -15 -10 -5
IO-Output Current-rnA
0
5
10 15
VO-Output VOltage-V
FIGURE 7
4-340
120
-40
\
o
100
30
I
~I
0
0
40
=
.............
0
~
50
I 5V_
I.
VCC
1
3
....
'"
80
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
vs
3.5
60
FIGURE 6
DIFFERENTIAL OUTPUT VOLTAGE
>
...---- J
IOL -Low-Level Output Current-rnA
FIGURE 5
4
II
FIGURE 8
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
20 25
SN75174
QUADRUPLE DIFFERENTIAL LINE DRIVER
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
100
ct
E
I
c
....
I:
1
~
Q.
Q.
INPUTS OPEN '"lIl,I
50
:s
(I)
I
30
J;
C
,..
U
o
--
15
/
Q.
:s
(I)
I
~
~
10
u
/
5
/
o
7
8
V
/
I'
/
II...
I
/
J;
23456
)I
No Load.
25 _ Input Opan
Output Disablad
TA - 25°e
20
"6.
"f ~INPUTS
GROUNDED
10
I~-l
~:s
~
/
20
o
E
I
//
60
40
u
ct
I
70
:s
U
30
1
.1
90 _ No Load
Outputs Enablad
80 - TA - 25°e
o
III
CD
>
'G)
/
Vee-Supply Voltaga-V
y
CD
2
3
4
5
6
7
8
a::
-.
III
...
vee-Supply Voitage-V
CD
>
FIGURE 10
FIGURE 9
';:
C
CD
c::
::::i
TYPICAL APPLICATION
1/4 SN75173
1/4 SN75175
UP TO 32
DRiVER/RECEIVER PAIRS
• • •
1/4 SN75172
1/4 SN75173
1/4 SN75173
1/4 SN75174
NOTE: The line length should be terminated at both ends in its characteristic impedance. Stub lengths off the main line should be kept
as short as possible.
FIGURE 11
TEXAS ...,
INSTRUMENlS
POST OFFICE BOX 66&012 • ()ALLAS, iEXAS 16265
4-341
II
r-
:5"
CD
...c<"
...
CD
-en
:xl
CD
n
CD
<"
...
CD
en
4-342
SN75175
QUADRUPLE DIFFERENTIAL LINE RECEIVER
02602, OCTOBER 19BO-REVISEO SEPTEMBER 1986
•
Meets EIA Standards RS-422-A. RS-423-A.
and RS-485
•
Meets CCITT Recommendations V.10.
V.1" X.26, and X.27
D. J, OR N
DUAL-IN-L1NE PACKAGE
(TOP VIEW)
•
•
•
Designed for Multipoint Bus Transmission on
Long Bus Lines in Noisy Environments
1Y
1,2EN
2Y
3-State Outputs
2A
Common-Mode Input Voltage Range
-12Vto12V
•
Input Sensitivity ... ± 200 mV
•
Input Hysteresis ... 50 mV Typ
26
Vee
46
4A
4Y
3,4EN
3Y
3A
GND '--<;'--_~ 36
logic symbol t
•
High Input Impedance ... 12 kO Min
•
Operates from Single 5-Volt Supply
•
Low Power Requirements
•
16
1A
1.2EN
lA
...
III
131 lY
lB
Plug-in Replacement for MC3486
Q)
2A
>
'Q)
uQ)
151 2Y
2B
description
The SN75175 is a monolithic quadruple
differential line receiver with three-state outputs.
It is designed to meet the requirements of EIA
Standards RS-422-A, RS-423-A. and RS-485
and several eelTT recommendations. The
device is optimized for balanced multipoint bus
transmission at rates up to 10 megabits per
second. Each of the two pairs of receivers has
a common active-high enable.
--...
~
3.4EN
I II
3A
Q)
>
1111 3Y
'':::
3B
4A
C
1131 4Y
4B
Q)
c::
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
~
logic diagram (positive logic)
The receivers feature high input impedance.
input hysteresis for increased noise immunity,
and input sensitivity of ± 200 millivolts over a
common-mode input voltage range of
±12volts. The SN75175 is designed for
optimum performance when used with the
SN75172 or SN75174 quadruple differential line
drivers.
The SN75175 is characterized for operation from
to 70 De.
ODe
FUNCTION TABLE (EACH RECEIVER)
DIFFERENTIAL INPUTS
A-B
VIO'" 0.2 V
-0.2 V < VIO
VIO '" -0.2 V
X
H
X
< 0.2 V
ENABLE
H
H
H
L
OUTPUT
Y
H
?
L
Z
= high level, L = low level, ? = indeterminate,
= irrelevant, Z = high impedance (off)
:~~~::~~i~ar::iu~~ ~~~~~ti:f :,iO::~:~:t:~~ not
(11)3Y
3B
4A
4B
Copyright © '980, Texas Instruments Incorporated
PRODUCTION DATA documonts contain information
current,.s of publication date. Products conform to
specifications per the terms of Texas Instruments
3A
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-343
5N75175
QUADRUPLE DIFFERENTIAL LINE RECEIVER
schematics of inputs and outputs
EQUIVALENT OF EACH A OR B INPUT
vCC----~~---.--
EQUIVALENT OF EACH ENABLE INPUT
TYPICAL OF ALL OUTPUTS
---------4~--Vcc
VCC---------1~--
B.3k!l
NOM
16.8k!l
NOM
INPUT _ _""1,;;:~~
INPUT-_ _--i
OUTPUT
...
S'
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) .............................................. ' 7 V
Input voltage, A or B inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 25 V
Differential input voltage (see Note 2) ......................................... ± 25 V
Enable input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Low-level output current ................................................... 50 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 3):
D package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 950 mW
J package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1150 mW
Operating free-air temperature range ....................................... O°C to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1.6 mm (1/16 inch) from case for 60 seconds: J package ............ -300°C
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds: D or N package ........ -260°C
..<'
.
CD
C
CD
en
:::a
CD
n
CD
..<'
CD
en
NOTES: 1. All voltage values, except differential input voltage, are with respect to network ground terminal.
2. Differential-input voltage is measured at the noninverting input with respect to the corresponding inverting input.
3. For operation above 25°C free-air temperature. derate the 0 package to 608 mW at 70°C at the rate of 7.6 mW/oC. the
J package to 656 mW at 70°C at the rate of 8.2 mW/oC, and the N package to 736 mW at 70°C at the rate of 9.2 mW/oC.
In the J package. SN75175 chips are glass mounted.
4-344
TEXAS . .
INSTRUMENTS
~OST O~"CE
BOX 655012 • DAllAS, tEXAS 16265
SN75175
QUADRUPLE DIFFERENTIAL LINE RECEIVER
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
Common-mode input voltage, VIC
±12
V
Differential input voltage, VIO
±12
V
0.8
V
High·level enable input voltage, VIH
2
V
Low·level enable input voltage, VIL
High-level output current, IOH
Low-level output current, IOl
0
Operating free-air temperature, T A
400
~A
16
mA
70
°C
electrical characteristics over recommended ranges of common-mode input voltage, supply voltage,
and operating free-air temperature (unless otherwise noted)
PARAMETER
VTH
VTL
voltage
Differential-input low-threshold
voltage
Vhys
Hysteresis §
VIK
Enable-input clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
High-impedance-state
10Z
output current
Va
= 2.7
V,
10
=
-0.4 mA
Vo
= 0.5
V,
10
=
16 mA
II - -18 mA
VID - 200 mV,
VID
=
Va
= 0.4
- 400 ~A, See Figure 1
=
0.45
0.5
16 mA
VIH - 2.7 V
IlL
Low-level enable-input current
VIL - 0.4 V
r;
Input resistance
•
.
II)
CP
>
"iii
V
(J
CP
V
--.
>
a:
V
I I)
CP
I VI - 12 V
7V
-
1
I VI
See Note 4
V
mV
2.7
JIOL - 8 mA
IIOL
UNIT
V
±20
Other input at 0 V,
High-level enable-input current
Short-circuit output current1
-0.2+
V to 2.4 V
IIH
Supply current
0.2
-1.5
10H -
-200 mV, See Figure 1
Line input current
ICC
MAX
50
II
lOS
MIN TVpt
TEST CONDITIONS
Differential·input high· threshold
0.8
~A
";::
C
mA
20
~A
-100
~A
CP
s::::
::i
kG
12
-15
Outputs disabled
-85
mA
70
mA
tAli typical values are at VCC = 5 V, TA = 25°C.
t The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for threshold
voltage levels only.
§ Hysteresis is the difference between the positive-going input threshold voltage, VT +, and the negative-going input threshold voltage,
VT _. See Figure 4.
, Not more than one output should be shorted at a time and the duration of the short-circuit should not exceed one second.
NOTE 4: Refer to EIA standards'RS-422·A, RS·423·A, and RS-485 for exact conditions.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-high-Ievel output
tpHL
Propagation delay time, high-to-Iow-level output
tpZH
Output enable time to high level
tpZL
Output enable time to low level
tpHZ
Output disable time from high level
tpLZ
Output disable time from low level
CL -. 15 pF,
See Figure 2
CL = 15 pF,
See Figure 3
CL = 15 pF,
See Figure 3
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MIN
TVP
MAX
22
35
UNIT
ns
25
35
ns
13
30
ns
19
30
ns
26
35
ns
25
35
ns
4-345
SN75175
QUADRUPLE DIFFERENTIAL LINE RECEIVER
PARAMETER MEASUREMENT INFORMATION
FIGURE 1. VOH, VOL
GENERATOR
(see Not. A)
INPUT
1.5V
I
C
I
I
I
::::J
CD
..<'
-!
OV
I4-t!-tPHL
C
tpLH..J.-.-.\
1.5 V
I
2V------~--------~
_ - -__-1- - - VOH
I
OUTPUT
::J:J
CD
()
TEST CIRCUIT
CD
..
<'
CD
en
VOLTAGE WAVEFORMS
FIGURE 2. PROPAGATION DELAY TIMES
NOTES: A. The input pulse is supplied by a generator having tne following characteristics: PRR
tf s 6 ns, Zout = 50 0.
B. CL includes probe and stray capacitance.
4-346
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 855012 ' DALLAS, TEXAS 15285
s
1 MHz, duty cycle = 50%, tr S 6 ns,
.
SN75175
QUADRUPLE DIFFERENTIAL LINE RECEIVER
PARAMETER MEASUREMENT INFORMATION
1.5V
-1.5V--o
2kn
(_NoteC)
GENERATOR
(_NoteA)
51
n
II
.
TEST CIRCUIT
II)
3V
INPU~
tpZH
INPU~
3V
.. "----A := := ~
e . 5 V SWI to 1.5 V
V SW2 open
"--E.
---tll4-tPZH
I
OUTPUT
CD
tpZL
>
"Gi
C.5V
(,)
"--....h==~V
•
I
~
SW3 CLOSED
SWltol.5V
SW2 open
If- tpZL SW3 closed
--4.SV
VOH
- -1.5 V
---OV
OUTPUT
~
--1.5V
CD
a:
~
CD
>
";::
C
VOL
CD
c:
tPHZ
INPUT
~.5V
I
~tPHZ
P3V~'5V
3V
tpLZ
SWlto-I.SV
SW2 closed
- - - 0 V·SW3 open
OUTPUT
-$:LL
-f.
.
3;lto_I.5V
SW2 closed
- - -0 V SW3 closed
I
I
0.5 V
I
IN UT
:::i
!f-M-tpLZ
__ O.S V
~
---1.4V
VOH
OUTPUT
_--1.4V
VOL
VOLTAGE WAVEFORMS
FIGURE 3. ENABLE AND DISABLE TIMES
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR
t r '" 6 ns, Zout = 50 0.
B. CL includes probe and stray capacitance.
C. All diodes are 1N916 or equivalent.
TEXAS •
INSTRUMENTS
POST OFFiCe BOX 655012 • DALLAS. TeXAS 75265
s ·1 MHz, duty cycle
= SO%, tf
s 6 ns,
4-347
SN75175
QUADRUPLE DIFFERENTIAL LINE RECEIVER
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
5
5
VCC=5V
TA = 25°C
10 =0
VIO = 0.2 V
TA = 25°C -
~
4
>I
.....
VIC=
-12V
I
l!l
"0 3
VT--
>
I
~IC= I-~V I
VT-
L
..
VI~=
!'
"0
I--
12 V
1
>
VT-
~
:::I
S2
90
:---.
~
3
:::I
Q.
~~
1,,\ ~
"\ ~ /VCC-5.25V
I
I
VVCC=5V
:::I
I
VT+- '-- VT+ I-- F-- VT + I--
~
4
0
..'"
a;
2
....I
l:.
.!!'
::t
I
::t
0
>
I"'"
5'
VCC = 4.75 V
>
CD
...c
o
o
;:CD
...
-125-100 -75-50-25 0
-
25
50 75 100 125
~ i::\.
o
-5 -10 -15 -20-25-30-35-40-45-50
VID-Oifferentiallnput Voltage-mV
(II
::xl
10H-High-Level Output Current-mA
FIGURE 5
FIGURE 4
CD
~~
~~
~~
n
;:-CDCD
...
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
(II
5
LOW·LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0_6
V:O = 01.2 V
TA - 25°C
~
>I
2:. 4
~
~
:::I
Q.
3
0.4
a:::I
~
:::I
0 0.3
a;
a;
"'"
:i:'"
>
...
:::I
0
....I
..
0_5
'"
l!l
"0
l!l
VCC=5V
TA = 25°C
.'"
2
....I
l:.
~ 0.2
0
....I
I
I
::t
>
o
o
10
20
30
/
/
~
0.1
o
40
50
60
70
80
o
5
10
15
20
25
10l -low-level Output Current-mA
T A -Free-Air Temperature-·C
FIGURE 7
FIGURE 6
4-348
V
....I
I-VCC= 5 V
r- VID = 0.2 V
10H = -440p.A
0
/
//
/
V
/
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
30
SN75175
QUADRUPLE DIFFERENTIAL LINE RECEIVER
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
FREE-AIR TEMPERATURE
ENABLE VOLTAGE
0.5
=t
5
0.4
CD
~
4
I
>I
~
...
CD
!
Vee=5V
:3 3
0.3
-J
ee =5.k5V-
.JI
Vee = 4.75 V-
~
:>
o
1j
VID = 0.2 V
Load = 8 kU to ground
TA = 25°C
~
So
:>
0.2
0
I
0
....~
I
~ 0.1
o
2
>
r- Vee = 5 V
...
II)
VID = -0.2 V
rlOL = 8 mA
o
I
I
10
20
G)
>
'iii
0
30
40
50
60
70
80
0
0,5
2
1.5
VI-Enable Voltage-V
TA-Free·Air Temperature-oe
2.5
(,)
G)
-...
3
0:
I I)
G)
FIGURE 9
FIGURE 8
>
';::
SUPPLY CURRENT
(ALL RECEIVERS)
C
vs
ENABLE VOLTAGE
vs
::::i
OUTPUT VOLTAGE
6
I
.1
V
...
5
"
& 4
:3
~
~
100
No load
90 I- I nputs open
TA =25°
80
I
Vee=5V
I
~:> 60
3
~
...
2
:>
'fu
E
o
/, V
u 50
>
Ii.
W
40
~ OUTPUTS ENABLED
30
11
20
10
o
0.5
1.5
2
2.5
VI-Enable Voltage-V
3
o
/
V/
hV
~
So
:>
9
c
SUPPLY VOLTAGE
VID ~ -0.2
Load = 1 kU to Vee
TA=25°e
Vee= 5.25 V
G)
o
./
£
2
3
4
5
6
7
8
vee-Supply Voltage-V
FIGURE 10
FIGURE 11
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75285
4-349
SN75175
QUADRUPLE DIFFERENTIAL LINE RECEIVER
TYPICAL CHARACTERISTICS
INPUT CURRENT
vs
INPUT VOLTAGE
0.75
«
-0.5
E
...cI
~
:;
...
"a.c
I
<.J
r-
:j'
0
-0.25
-0.5
-0.75
\1)
...c
<'
-6 -4 -2
...
0
2
4
6
8
10
12
\1)
--
VI-Input Voltage-V
(II
:l:I
FIGURE 12
\1)
n
\1)
<'
...
TYPICAL APPLICATION
\1)
(II
1/4 SN75172
1/4 SN75174
UPTO 32
DRIVER/RECEIVER PAIRS
1/4 SN75173
•
1/4 SN75172
•
1/4 SN75173
1/4 SN75175
•
1/4 SN75173
1/4 SN75174
FIGURE 13
NOTE: The line should be terminated at both ends in its characteristic impedance. Stub lengths off the main line should be kept as short
as possible.
4-350
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 76266
ADVANCE
INFORMATION
SN65176B, SN75176B
DIFFERENTiAL BUS TRANSCEIVERS
02619, JULY 1985-REVISEO OCTOBER 1986
•
Bidirectional Transceiver
•
Meets EIA Standards RS-422-A and RS-485
and CCITT Recommendations V, 11 and
X,27
•
Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
D. JG. OR P PACKAGE
•
3-State Driver and Receiver Outputs
•
Individual Driver and Receiver Enables
•
Wide Positive and Negative Input/Output
Bus Voltage Ranges
(TOP VIEW)
~D8
Vee
RE 2
7 B
DE
D
3
4
6
5
A
GND
FUNCTION TABLE (DRIVER)
•
Driver Output Capability, . . ± 60 rnA Max
•
Thermal Shutdown Protection
•
Driver Positive and Negative Current
Limiting
INPUT
ENABLE
D
DE
A
OUTPUTS
H
H
H
L
L
H
L
H
X
L
Z
Z
B
•
FUNCTION TABLE (RECEIVERI
•
Receiver Input Impedance . . . 12 kg Min
•
Receiver Input Sensitivity. . . ± 200 mV
DIFFERENTIAL INPUTS
ENABLE
OUTPUT
A-B
RE
R
VIO;> 0.2 V
L
H
L
?
L
L
H
(,)
G)
Z
Ill:
-0.2 V
< Vio < 0.2
V
VIO';; -0.2 V
•
Receiver Input Hysteresis ... 50 mV Typ
•
Operates from Single 5-Volt Supply
•
Low Power Requirements
X
H
X
=
=
...
II)
G)
>
"a;
--...
high level, l = low level, ? = indeterminate,
irrelevant, Z = high impedance (off!
I I)
G)
>
";:
logic symbol t
description
C
G)
c:::
::J
The SN65176B and SN75176B differential bus
transceivers are monolithic integrated circuits
designed for bidirecti'onal data communication
on multipoint bus transmission lines. They are
designed for balanced transmission lines and
meet EIA Standard RS-422-A and RS-485 and
eelTT Recommendations V.11 and X.27.
The SN65176B and SN75176B combine a threestate differential line driver and a differential
input line receiver both of which operate from
a single 5-volt power supply. The driver and
receiver have active-high and active-low
enables, respectively, that can be externally
connected together to function as a direction
control. The driver differential outputs and the
receiver differential inputs are connected
internally to form differential input/output (110)
bus ports that are designed to offer minimum
loading to the bus whenever the driver is disabled
or Vee = 0 volts. These ports feature wide
positive and negative common-mode voltage
ranges making the device suitable for party-line
applications,
(61 A
(71 B
:2
o
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
logic diagram (positive logic)
DE
i=
«
:a:a::
ou.
-='---.,
:2
w
D
o
:2
RE ....:::..--...,
«
(61
>
Q
R
«
ADVANCE INFORMATION d••umlnts contlin
~-:::3!:~nO:h::J~~~f~p::a:r.·C~:~~'stT!
ilata and other spacifications are subject to change
without notica.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1985, Texas Instruments Incorporated
4-351
ADVANCE
INFORMATION
SN65176B. SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
The driver is designed to handle loads up to 60 milliamperes of sink or source current. The driver features
positive- and negative-current limiting and thermal shutdown for protection from line fault conditions.
Thermal shutdown is designed to occur at a junction temperature of approximately 150°C. The receiver
features a minimum input impedance of 12. kO, an input sensitivity of ± 200 millivolts, and a typical input
hysteresis of 50 millivolts.
The SN65176B and SN75176B can be used in transmission line applications employing the SN75172 and
SN75174 quadruple differential line drivers and SN75173 and SN75175 quadruple differential line receivers.
The SN65176B is characterized for operation from -40°C to 85°C and the SN75176B is characterized
for operation from O°C to 70°C.
schematics of inputs and outputs
•
r-
S"
EQUIVALENT OF EACH INPUT
v c c - - -.... - - - - -
TYPICAL OF A AND B 110 PORTS
- -....- -...- -.... - - VCC
TYPICAL OF RECEIVER OUTPUT
B6n
VCC
NOM
INPUT
CD
...C
...
OUTPUT
~"
fI)
--+-+-+-_-+--- GND
::D
CD
(")
CD
:c"
CD
Driver Input: Req = 3 kO NOM
Enable Inputs: Req" B kn NOM
...
fI)
»
c
~
2
(")
m
-
2
."
o
::0
3:
»
::!
o
2
3-352
TEXAS ."
INSlRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
ADVANCE
INFORMATION
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise notedl
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Voltage at any bus terminal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 10 V to 15 V
Enable input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
D package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 725 mW
JG package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 825 mW
P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1100 mW
Operating free-air temperature range: SN65176B.... . . . . . . . . . . . . . . . . . . . . .. - 40°C to 85 °e
SN75176B ........ , ................... OOC to 70°C
Storage temperature range ......................................... - 65°C to 1 50°C
Lead temperature 1,6 mm (1/16 inch) from the case for 60 seconds: JG package ........ 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package ........ , 260°C
NOTES:
1. All voltage values. except differential input/output bus voltage, are with respect to network ground terminal.
2. For operation above 25·e free-air temperature, refer to Dissipation Derating Table. In the JG package, the chips are glass
mounted.
4
en
DISSIPATION DERATING TABLE
a-
li)
PACKAGE
TA - 25·C
POWER RATING
D
725 mW
DERATING FACTOR
ABOVE TA - 25·C
5.8 mw/·e
TA - 70·e
POWER RATING
TA - B5·C
POWER RATING
464mW
377 mW
JG
825 mW
6.6 mw/·e
528 mW
429 mW
P
1100mW
B.B mw/·e
702 mW
570 mW
>
'G)
(J
II)
IX
ea-n
li)
>
'r:
recommended operating conditions
Supply voltage, Vee
Voltage at any bus terminal (separately or common mode),
MIN
TYP
MAX
UNIT
4.75
5
5.25
V
12
-7
V
V, or VIC
High-level input voltage, VIH
D, DE, and RE
Low·level input v.oltage, VIL
D, DE, and RE
0.8
Driver
High-level output current, IOH
Receiver
Driver
LowMlevel output current, IOL
Operating free·air temperature, TA
I
SN65176B
SN75176B
c
:::i
V
±12
V
-60
mA
-400
pA
60
-40
B
B5
0
70
Receiver
I
II)
V
2
Differential input voltage, VID (see Note 3)
C
mA
·e
NOTE 3: Differential-input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
z
o
~
::!:
a:
ou.
-w
Z
(.)
z
c
TYP*
Voo,
2
See Note 4
1.5
V
2.5
1.5
See Figure 1
RL = 54 II or 100 II,
Change in magnitude of
5
V
5
V
±0.2
V
+3
-1
V
±0.2
V
1
-0.8
mA
r-
AIVoe
com·mon~mode output voltage §
CD
10
Output current
IIH
High-level input current
VI - 2.4 V
IlL
Low-level input current
VI = 0.4 V
20
-400
Vo -
-250
3'
...<'
C
CD
Cil
::1:1
CD
lOS
Short-circuit output current
n
CD
<'
lee
...
CD
Supply current (total package)
Output disabled,
See Note 5
IVo = 12 V
IVo = -7 V
-7 V
-150
Vo - 0
250
Vo = Vee
Vo - 12 V
No load
~A
~A
mA
250
I Outputs enabled
42
55
10utputs disabled
26
35
mA
(I)
t The power-off measurement in EIA Standard RS-422-A applies to disabled outputs only and is not applied to combined inputs and outputs.
= 5 V and T A = 25°e.
§AIVODI and AIVoel are the changes in magnitude of VOD and Voe respectively, that occur when the input is changed from a high
level to a low level.
NOTES: 4. See EIA Standard RS-485 Figure 3.5, Test Termination Measurement 2.
5. This applies for both power on and off; refer to EIA Standard RS-485 for exact conditions. The RS-422-A limit does not apply
for a combined driver and receiver terminal.
*All typical values are at Vee
»
c
»<
2
m
:2
C')
"T1
driver switching characteristics. VCC .. 5 V. TA .. 25°C
PARAMETER
too
Differential-output delay time
tTD
tpZH
Differential-output transition time
TEST CONDITIONS
MIN
TYP
15
MAX
22
UNIT
ns
RL = 5411,
See Figure 3
20
30
ns
Output enable time to high level
RL - 110 II,
See Figure 4
85
120
ns
tpZL
Output enable time to low level
RL - 110 II,
See Figure 5
40
60
ns
tpHZ
Output disable time from high level
RL - 110 II,
See Figure 4
150
250
ns
tpLZ
Output disable time from low level
RL - 110 II,
See Figure 5
20
30
ns
o
::xJ
s:
»
-I
(5
:2
4-354
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
ADVANCE
INFORMATION
SN65176B. SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SYMBOL EQUIVALENTS
DATA SHEET PARAMETER
RS-422-A
Va
Voa ' Vob
Va
V t (RL - 100
!VOO1!
!VOO2!
RS-485
V oa , Vob
Va
V t (RL - 54
m
m
Vt (Test Termination
Measurement 2)
!VOO3!
!!Vt ! -
A!VOO!
!Vt !!
!!Vt -
!Vt !!
VOC
IVos!
!Vos!
A!VOC!
! Vas - Vas!
! Vas - Vas!
lOS
!Isa!, !Isb!
10
!Ixa!, !Ixb!
lia, lib
RECEIVER SECTION
receiver electrical characteristics over recommended ranges of common-mode input voltage. supply
voltage, and operating free-air temperature (unless otherwise noted I
PARAMETER
TEST CONDITIONS
VTH
Differential-input high-threshold voltage
Va
VTL
Differential-input low-threshold voltage
Va
VhyS
Hysteresis §
VIK
Enable-input clamp voltage
VOH
= 2.7 v,
= 0.5 V,
10
10
=
=
MIN
TYpt
-0.4 mA
MAX
0.2
-0.2*
8 mA
High-level output voltage
VOL
Low-level output voltage
II
VIO
18 mA
= - 200
IOH
=
-400
~A,
See Figure 2
VIO -
-200 mV,
2.7
10Z
High-impedance-state output current
Line input current
0.45
IIH
High-level enable-input current
VIH - 2.7 V
IlL
Low-level enable-input current
VIL - 0.4 V
ri
Input resistance
lOS
Short-circuit output current
ICC
Supply current (total packagel
Va - 0.4 V to 2.4 V
±20
Other input - 0 V,
VI -
See Note 6
VI
12 V
=
1
-7 V
-0.8
G)
V
-
V
>
";:
~
G)
G)
c
:::::i
~A
mA
~A
-85
mA
~A
kll
-15
I Outputs enabled
I Outputs disabled
V
20
-100
12
No load
CJ
a:
C
IOL - 8 mA,
See Figure 2
II
V
mV
1.5
mV,
42
55
26
35
z
o
mA
;::
t All typical values are at VCC = 5 V, TA = 25°C.
:t The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for commonmode input voltage and threshold voltage levels only.
Vr +, and the negative-going input threshold voltage,
VT _. See Figure 4.
NOTE 6: This applies for both power on and power off. Refer to EIA Standard RS-485 for exact conditions.
§ Hysteresis is the difference between the positive-going input threshold voltage,
PARAMETER
TEST CONDITIONS
Propagation delay time, low-to-high-Ievel output
tpHL
Propagation delay time. high-to-Iow-Ievel output
tpZH
tpZL
Output enable time to high level
Output enable time to low level
tpHZ
Output disable time from high level
tpLZ
Output disable time from low level
VIO - 0 V to 3 V,
See Figure 6
CL = 15 pF,
CL
=
15 pF,
CL
=
15 pF,
";
UNIT
V
50
II
See Figure 7
See Figure 7
TEXAS . "
INSTRUMENTS
POST OFFiCe BOX 655012 • DALLAS, TEXAS 76265
MIN
TYP
MAX
21
35
UNIT
ns
(,)
23
35
ns
Z
10
20
ns
12
20
ns
20
35
ns
17
25
ns
~
c
"Qi
U
CD
GENERATOR
a:
-..
II)
50n
(Soo Note AI
...
CD
>
";::
TEST CIRCUIT
~
I
INPUT
C
INPUT~--~==::V
-----3V
----1.5V
I
I
tpZH
~
I
~VOH
---3V
~
INPUT
1 .5 V
I1--~4'5V
O.V
OUTPUT
INPUT
S3 closocl
~
2:
1.5V
-F'---
Sltol.5V
S2 closed
I
I
tPHZ~
I
tPZL~
-+I l4--
~~:.- _
OUTPUT
Slto-l.5V
0 V S2 closed
530pon
I
OV
CD
c
::::i
o
VOL
3V 51 to -1.5 V
S2 closed
" - - O V S3 closed
----11 .._-
ou.
OV
I
O"~"' ~!
~ '0"
-i--~ ___ ~1.3V
tPLZ~
I
-2:w
~
OUTPUT
---~1'3V
0.5 V
CJ
2:
VOL
VOLTAGE WAVEFORMS
FIGURE 7. RECEIVER OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR '" 1 MHz, 50% duty cycle, tr '" 6 ns,
tf '" 6 ns, Zout = 50 II.
B. CL includes probe and jig capacitance.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
i=
;
,
~
.........
0
Gi
...c
<'
CD
iil
.VCCI =5V
-'TA = 25°C
4
I
I
I
3
2.5
>
..
2
~
1.5
....
....0
I
,..
I
.....0
:z::
~ 0.5
o
o
3.5
I
]
2
1:.
'" 1.5
:f
r-
l!0'"
..
r-- r-..
...............
>
4.5
>
-20
-40
-60
-80
0.5
o
-100 -120
o
20
IOH-High-Level Output Current-mA
- f...--
40
FIGURE 8
FIGURE 9
<'
CD
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
vs
DRIVER OUTPUT CURRENT
en
4
(')
CD
...
::r
3.5
.5-
3
t
~
»c
~
:2
nm
:2
."
o
......
2.5
o
=
25°C
.........
........
.........
. . . 1"-
:>
ii
v~C=~v -
TA
2
......
~
.~
2! 1.5
:iiC
1\
I
1\
g 0.5
\
>
00
10 20 30 40 50 60 70 80 90 100
10 - Output Current-mA
::tI
3l:
FIGURE 10
~
o
:2
. 4-358
60
80
100
IOL -Low-Level Output Current-mA
:D
CD
II
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
120
ADVANCE
INFORMATION
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
TYPICAL CHARACTERISTICS
RECEIVER HIGH-LEVEL OUTPUT VOLTAGE
RECEIVER HIGH-LEVEL OUTPUT
vs
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT CURRENT
5
5
>I
&
:l
"0
4
5-
3
>
;
~
"
0
Ii
..
>
.oJ
Vcc - 5 V
VIO - 200 mV
IOH - -440/LA
VID = 0.2 V
TA=25°C -
2
.c
:f'"
I
J:
0
>
o
-
~~
1'\ ~
~ ~ VVCC=5_2~V
~VV~CJ5VI- r--~
VCC = 4.75 V
~~
~~
o
II...
en
CD
~~
>
"Qj
o
-10
-20
-30
-40
-50
IOH-High-Level Output Current-mA
(J
-40 -20 0
20 40 60 80 100 120
TA-Free-Air Temperature- °c
CD
a:
-..
...
en
CD
=f
&
:l
"0
RECEIVER LOW-LEVEL OUTPUT VOLTAGE
RECEIVER LOW-LEVEL OUTPUT VOLTAGE
vs
vs
RECEIVER LOW-LEVEL OUTPUT CURRENT
0.6
VCC=5V
TA = 25°C
0.5
."
0.4
0
Ii
0.3
>
5-
"
t
.oJ
t
0.2
0
.oJ
I
.oJ
0 0.1
V
/
V
~/
V
>
FIGURE 12
FIGURE 11
V
/
V
".::
o
CD
c:
::::i
FREE-AIR TEMPERATURE
0.6
VCC - 5 V
VIO - -200 mV
I 0.5 IOL = 8 mA
>
II
'"
~
~ 0.4
;
CL
;
00.3
~II
z
o
--
~
«
~
-'
~ 0.2
a:
oLL
.9
I
>
60.1
o
Z
>
o
5
10
15
20
25
30
IOL-Low Level Output Current-mA
o
-40 -20
0
20
40 60 80 100 120
TA -Free-Air Temperature- °c
FIGURE 13
FIGURE 14
W
(,)
z
«
>
c
«
TEXAS
~
INSTRUMENTS
POST OFFICE BOX- 655012 • DALLAS, TEXAS 75265
4-359
ADVANCE
INFORMATION
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
TYPICAL CHARACTERISTICS
RECEIVER OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
RECEIVER OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
5
VIO = 0.2 V
Load = 8 kn to ground
TA = 25°e
4
j
Vee=5V
6
-J
5
1
ee = 5. 25 V-
>I
e-
'"
J!'"
Vee =4.75 V -
3
Vee = 4.75 V
4
,!
I
V\D = -0.2 V
Load = 1 kn to Vee
TA = 25°C
""vee l= 5 V
I----
15
>
11
1
I
Vee = 5.25 V
=
3
&
2
cr
~
2
0
>
s·CDr
C
o
::::!.
;i
o
iil
0.5
1.5
2
2.5
o
o
3
0.5
VI-Enable Voltage-V
:::I:J
1.5
2
VI-Enable Voltage-V
FIGURE 15
CD
2.5
3
FIGURE 16
(')
CD
ci:'
CD
TYPICAL APPLICATION
iil
SN651768.
SN751768
SN651'768.
SN751768
l>
o
~
:2
UPTO 32
(')
...
m
TRANSCEIVERS
-
:2
."
FIGURE 17. TYPICAL APPLICATION CIRCUIT
::D
NOTE 7: The line should be terminated at both ends in its characteristic impedance. Stub lengths off the main line should be kept as short
as possible.
o
3:
l>
::!
o
:2
4-360
TEXAS . "
INSTRUMENTS
POST OfFICE BOX 655012 • DALLAS, TeXAS 75265
SN75177B, SN75178B
ADVANCE
INFORMATION
DIFFERENTIAL BUS REPEATERS
D2606. JULY 1985
•
•
Meets EIA Standards RS-422-A and RS-485
and CCITT Recommendations V. 11 and
X.27
SN75177B ... D. JG. OR P
DUAL-IN-LiNE PACKAGE
(TOP VIEW)
VCC[]8 A
Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
•
3-State Outputs
•
Bus Voltage Range ... - 7 V to 12 V
•
Positive and Negative Current Limiting
•
Driver Output Capability . . . 60 mA Max
•
Driver Thermal Shutdown Protection
•
Receiver Input Impedance . . . 12 kO Min
•
Receiver Input Sensitivity . . . ± 200 mV
•
Receiver Input Hysteresis ... 50 mV Typ
•
Operates from Single 5-Volt Supply
•
Low Power Requirements
T
EN
GND
2
3
7
6
4
5
B
Z
Y
SN7517BB •.• D, JG. OR P
DUAL·IN-LiNE PACKAGE
(TOP VIEW)
VCC[]8 A
T
EN
GND
2
3
7
6
4
5
B
Z
Y
...
SN75177B FUNCTION TABLE
description
The SN75177B and SN75178B differential bus
repeaters are monolithic integrated devices each
designed for one-way data communication on
multipoint bus transmission lipes. These devices
are designed for balanced transmission bus line
applications and meet EIA Standards RS-422-A
and RS-485 .and CCITT Recommendations V.11
and X.27. Each device is designed to improve
the performance of the data communication over
long bus lines. The SN75177B and SN75178B
are identical except for the complementary
enable inputs, which allow the devices to be
used in pairs for bidirectional communication.
(II
CI)
DIFFERENTIAL INPUTS
ENABLE
OUTPUTS
A-B
EN
T
Y
Z
'G)
VID '" 0.2 V
-0.2 V < VID < 0.2 V
H
H
H
L
H
?
?
?
VID '" 0.2 V
H
L
L
H
X
L
Z
Z
Z
-
>
Co)
CI)
a:
...
( II
CI)
>
';:
SN75178B FUNCTION TABLE
H
X
C
DIFFERENTIAL INPUTS
ENABLE
A-B
EN
T
Y
Z
VID '" 0.2 V
-0.2 V < VID < 0.2 V
L
H
H
L
L
?
?
?
OUTPUTS
CI)
VID '" 0.2 V
L
L
L
H
X
H
Z
Z
Z
c
:::i
= high level. L = low level. ? = indeterminate.
= irrelevant, Z = impedance (off)
The SN75177B and SN75178B feature positive- and negative-current limiting three-state outputs for the
receiver and driver. The receiver features high input impedance, input hysteresis for increased noise
immunity, and input sensitivity of ± 200 millivolts over a common-mode input voltage range of -7 volts
to 12 volts. The driver features thermal shutdown for protection from line fault conditions. Thermal
shutdown is designed to occur at a junction temperature of approximately 150
The driver is designed
to drive current loads up to 60 milliamperes maximum.
ac.
The SN75177B and SN75178B are designed for optimum performance when used on transmission buses
employing the SN75172 and SN75174 differential line drivers, SN75173 and SN75175 differential line
receivers, or SN75176B bus transceivers.
z
o
i=
-='----....-----.......,
A
Y
z
B
I
T' 21
RECEIVER
SN751781i
DRIVER
SN751788
EN -""'----....--------,
C>
"i/
"i/
151 Y
A
Y
161 Z
z
B
rS'
RECEIVER
ORIVER
T 121
CD
tThese symbols are in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12 .
...C<'
...
en
CD
. schematics of inputs and outputs
:xl
EQUIVALENT OF DRIVER OR ENABLE INPUT
(')
VCC--------~~---
CD
TYPICAL OF ALL DRIVER OUTPUTS
VCC
CD
<'
CD
...en
INPUT -1~+---i
OUTPUT
l>
C
~
2
om
2
."
o
Dri_ input: Req • 3 kll NOM'
Enable input: RIC( = 8 kll NOM
......- - _ - - - GND
TYPICAL OF ALL RECEIVER OUTPUTS
EQUIVALENT OF EACH RECEIVER INPUT
-------+---
Vee
960ll
INPUT
NOM
---------t
__.....l.._
16.8 kll
NOM
OUTPUT
960ll
NOM
:JJ
s:l>
:::i
o
2
4-362
Vee
TEXAS
.If
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75286
ADVANCE
INFORMATION
SN75177B, SN75178B
DIFFERENTIAL BUS REPEATERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) ................................................ 7 V
Voltage at any bus terminal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 10 V to 15 V
Differential input voltage (see Note 2) ......................................... ± 25 V
Enable input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 3):
D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725 mW
JG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 mW
P package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1000 mW
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooC to 70°C
NOTES:
1. All voltage values, except differential input voltage, are with respect to network ground terminal.
2. Differential input voltage is measured at the non inverting input with respect to the corresponding inverting input.
3. For operation above 25°e free-air temperature, derate the D package to 464 mW at 70 0 e at the rate of 5.8 mW/oe, the
JG package to 528 mW at 70 0 e at the rate of 6.6 mw/oe and the P package to 640 mW at 70 0 e at the rate of 8.0 mW/oe.
in the JG package, SN75177B and SN75178B chips are glass mounted.
recommended operating conditions
MiN
Supply voltage, Vee
4.75
High-level input voltage, VIH
EN or EN
Low-level input voltage, VIL
EN or EN
Differential input voltage, VID
High·level output current, IOH
Low-level output current, IOL
Driver
Receiver
UNIT
5
5.25
V
0.8
V
12
V
±12
-60
V
rnA
-400
pA
8
0
.
II)
Q)
>
"i»
u
V
60
Driver
Receiver
Operating free-air temperature, T A
MAX
2
-7
Common-mode input voltage, VIC
NOM
70
-..
Q)
a:
I I)
Q)
>
".:
mA
C
°e
c
::;
Q)
t The algebraic convention, where the less-positive (more-negative) limit is designated minimum, is used in this data sheet for commonmode input voltage and threshold voltage.
2
o
i=
:E
a:
IVool
VOC
i IVtl -IVtl I
IVosl
IVasl
I Vas
I Vas - Vas I
t>iVocl
lOS
]isal, lisbl
10
lixal, Ilxb!
- Vas
I
lia, lib
RECEIVER SECTION
receiver electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VTH
Differential-input high-threshold voltage
Va
Vn
Differential-input low-threshold voltage
Va
Vhys
Hysteresis §
VIK
Enable-input clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
10Z
~
2.7 V,
10
~
0.5 V,
10
MIN
Typt
-0.4 mA
~
~
MAX
0.2
-0.2+
8 mA
-18 mA
VIO - 200 mV,
10H
-
10L
~
-400
~A,
See Figure 2
VIO ~ - 200 mV,
2.7
8 mA,
0.45
See Figure 2
High-impedance-state output current
Va
~
20
0.4 V to 2.4 V
Other input at 0 v,IVI
-400
~
12 V
1
Q)
mA
20
~A
IlL
Low-level enable-input current
VIL - 0.4 V
-100
~A
ri
Input resistance
lOS
Short-circuit output current
-85
mA
12
kG
-15
Supply current (total package)
No load
r:::
:.:::i
~A
VIH ~ 2.7 V
-0.8
>
V
High-level enable-input current
IVI ~ -7 V
I /)
Q)
';:
C
IIH
ICC
--...
V
line input current
I Outputs
(.)
Q)
V
II
See Note 5
enabled
57
70
JOutputs disS,bled
26
35
2:
-o
mA
~
<3:
t All typical values are at VCC ~ 5 V, T A ~ 25 DC.
t The algebraic convention, where the less-positive (more-negative) limit is designated minimum, is used in this data sheet for common
mode input voltage and threshold voltage levels only.
§ Hysteresis _is the difference between the positive-going input threshold VOltage, VT +, and the negative-going input threshold voltage,
VT ~. See Figure 12.
NOTE 5: Refer to EIA Standard RS-422-A for exact conditions.
receiver switching characteristics, VCC = 5 V, TA
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-high-Ievel output
VIO
tpHL
Propagation delay time, high-to-Iow-Ievel output
CL
tpZH
Output enable time to high level
tpZL
Output enable time to low level
tpHZ
Output disable time from high level
tpLZ
Output disable time from low level
CL
CL
~
~
~
~
-1.5Vto1.5V,
15 pF,
See Figure 6
15 pF,
See Figure 7
15 pF,
See Figure 7
TEXAS . "
INSTRUMENTS
MIN
>
'iii
a:
mV
-1.5
I/)
Q)
V
V
50
II -
UNIT
II...
TYP
MAX
19
35
UNIT
ns
30
40
ns
10
20
ns
12
20
ns
25
35
ns
17
25
ns
:lE
a::
o
LL
2:
w
U
2:
<3:
>
C
<3:
4-365
SN75177a SN75178B
DIFFERENTIAL BUS REPEATERS
ADVANCE
INFORMATION
PARAMETER MEASUREMENT INFORMATION
VOC
-=1FIGURE 2. RECEIVER VOH AND VOL
FIGURE 1. DRIVER VOD AND VOC
~
--3V
II
INPUT
GENERATOR
(See Note AI
c:
::::J
1.5V
1.5V
I
I
I
I
I
50 n
I
T-
I
CD
..<'
..
OUTPUT
':'
C
OV
I
~too
I
too---i++l
~-2.5
~tTD
CD
TEST CIRCUIT
(fI
'i;
V
VOLTAGE WAVEFORMS
FIGURE 3. DRIVER DIFFERENTIAL-OUTPUT DELAY AND TRANSITION TIMES
CD
v---
(')
OUTPUT
CD
<'
.
CD
(SN75178AI ~
INP~1.5V
o Vor 3V -----I
(fI
I
I
(SN75177A)
GENERATOR
(See Note AI
50
n
SN75178B
Enable is
active low
Y
I
OUTPUT
':'
0 V
O.~V
R
-LVOH
r
2.3V
_"";"_J
3V
1.5V~
~tPZH
»
c
<
»
;'2
~2.5V
50%
1
tpHZ~
T
Vall '" 0 V
':'
VOLTAGE WAVEFORMS
TEST CIRCUIT
FIGURE 4. DRIVER ENABLE AND DISABLE TIMES (tPZH, tPHZ)
NOTES:
(")
m
A. The input pulse is supplied by a generator having the following characteristics: PRR :5 1 MHz, 50% duty cycle, tr :s; 6 ns,
tf ::;6 ns, Zout = 50 n.
B. CL includes probe and jig capacitance.
-
; '2
."
o
:XJ
S
»
-I
o;'2
4-366
TEXAS •
INSTRUMENTS
ADVANCE
INFORMATION
SN75177B, SN75178B
DIFFERENTIAL BUS REPEATERS
PARAMETER MEASUREMENT INFORMATION
5V
X
I _____
(SN75178A)~
,..----3V
1 .5V
INPUT-Al.5V
(SN75177A)
3VorOV----i
CL=50pF
(See Note B)
GENERATOR
(See Note A)
50
n
I
oJ I
tPZL~
I
I
-=
SN75178B
I
~tPLZ
_£~.5V
I
OUTPUT
Enable is
active low
0 V
,
t £ ' 5V
:
\2.3 V
,-VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
III
FIGURE 5. DRIVER ENABLE AND DISABLE TIMES (tPZL. tPLZ)
--3V
GENERATOR
(See Note A)
>-___...._OUTPUT
50n
~
INPUT
1.5 V ·
I
1.5V
~'"f
,
1.3 V
~
Q)
1.5 V
I
I
OUTPUT
I
>
'Q)
OV
~---"'---t
~~'
I
U
Q)
VO,
1.3 V
A. The input pulse is supplied by a generator having the following characteristics: PRR
tf :;;6 ns, Zout = 50 O.
B. CL includes probe and jig capacitance.
~
I II
't:
C
VOLTAGE WAVEFORMS
Q)
c
FIGURE 6. RECEIVER PROPAGATION DELAY TIMES
NOTES:
--..
>
Q)
VOL
TEST CIRCUIT
a:
::i
1 MHz, 50% duty cycle, tr :56 ns,
z
o
i=
--...- ...---....- . -....-""III'r--
4.S
f
1.5
I
1
:I:
4.5
1'"
4
c5
2.5
]
!
1.5
I
il
o
-20
-40
-60
-80
-100 -120
IOH-High Level Output Current-rnA
o
20
40
60
80
I .....
3
V~C-~V l-
2.5
j
I.S
l"-
100
i',
is
1
~
0.5
120
1\
\
00
10 20 30 40 50 60 70 80 90100
IOL - Low Level Output Current-rnA
FIGURE 8
TA = 25°C
t-.....
t--...
i
I
/
~ 0.5 f--I--
o
3.5
il
I-- e=
I
-'
~ O.5
f
>
I
~
2
0
VCC=5V
TA = 2S"C
~ 3.5
..............
3
2.S
t
r::::::::
3.S
o
l'
VCc'"'SV
TA = 2S"C
10 - Output Current-rnA
FIGURE 9
FIGURE 10
II...
III
RECEIVER OUTPUT VOLTAGE
RECEIVER HIGH·lEVELQUTPUT VOLTAGE
RECEIVER HIGH·LEVEL OUTPUT VOLTAGE
"
HIGH·LEVEL OUTPUT CURRENT
"
FREE·AIR TEMPERATURE
DIFFERENTIAL INPUT VOLTAGE
I
5 VCc= 5V
10=0
VID '" 0.2 V
TA = 2!fC
I
I
I
t-....
f-' ~
1'\ ~
1'\ ~ VVCC-S.25V
~ V~~5VI- I~
Vcc = 4.75 V
1
o~=±=t~~~=t~
-125
-75
-25
0
0
FIGURE 11
0.4
o
0.3
~
!]
~
~
o
3f-~-4--+-~-4--+-~-4
!
VCC"'5V
./
V
1
~
CD
1
c:
VCC"'5V
VID=0.2V
:::::i
10H = --440JAA
oL-~
o
10
__L-~~__~~~~~
~
~
~
~
00
N
M
T A-Free·Air Temperature-oC
"
0.5
V
r-~~--"---r---'--"---r--
VCC=5 V
VIO" -0.2 V
IOl = 8 rnA
or
~ 0.4
/'
~
i
~
0.3
1--+--1-+-11--
p='f=t-+--1,--!-4-+--I
30.2 f--+--I-+----jr---I---+--+---I
0.2
!~
O. 1
!]
0.1
f-+--I-+-+--+--+--t-----I
0
15
20
25
CD
>
";:
FIGURE 13
/V
10
I I)
C
FIGURE 12
TA=ZS"C
-"...
a::
i
FREE·AIR TEMPERATURE
f
!3
4~+-+-4--I--I--+-+~
RECEIVER LOW·LEVEL OUTPUT VOLTAGE
•
>
CD
!
LOW-LEVEL OUTPUT CURRENT
0.5
CD
"Qj
RECEIVER LOW-LEVEL OUTPUT VOLTAGE
o.
~
I'\:~ I
~I
~
or
-10
-20
-30
--40
-50
IOH-High.Level Output Current-rnA
25 50 75 100 126
VID - Differential Input Voltage-mV
l'
I I I
I I 1
"
30
00
IOL-Low Level Output Current-mA
10
~ ~
40
~
00
~
T A-Free-Air Ternperature_°c
FIGURE 14
FIGURE 15
M
2:
o
~
:e
a:
ou..
2:
w
o
2:
c
~
2
(')
m
2
o"::D
s:
~
o
2
4-370
. TEXAS'"
INSTRUMENTS
ADVANCE
INFORMATION
SN75179B
DIFFERENTIAL DRIVER AND RECEIVER PAIR
02845, OCTOBER 1985
•
D, JG. OR P DUAL· IN· LINE PACKAGE
Meets EIA Standards RS-422-A and RS-485
and CCITT Recommendations V. 11 and
X.27
(TOP VIEW)
VCC[JjB A
•
Bus Voltage Range ... - 7 V to 12 V
•
Positive and Negative Current Limiting
•
Driver Output Capability . . . 60 mA Max
•
Driver Thermal Shutdown Protection
•
Receiver Input Impedance . . . 12 kO Min
•
Receiver Input Sensitivity ... ± 200 mV
•
Receiver Input Hysteresis ... 50 mV Typ
•
Operates from Single 5-V Supply
•
Low Power Requirements
o
R
2
3
GND
4
7
6
5
B
Z
Y
FUNCTION TABLE (DRIVER)
INPUT
OUTPUTS
D
Y
H
H
L
L
L
H
Z
III
FUNCTION TABLE (RECEIVER)
description
The SN75179B driver and bus receiver circuit is
a monolithic integrated device designed for
balanced transmission line applications and
meets EIA Standards RS-422-A and RS-485 and
CCITT Recommendations V.11 and X.27. It is
designed to improve the performance of fullduplex data communications over long bus lines.
The SN75179B driver outputs provide limiting
for both positive and negative currents. The
receiver features high input impedance, input
hysteresis for increased noise immunity, and
input sensitivity of ± 200 millivolts over a
common-mode input voltage range of - 12 volts
to 12 volts. The driver provides thermal
shutdown for protection from line fault
conditions. Thermal shutdown is designed to
occur at a junction temperature of approximately
150°C. The device is designed to drive current
loads of up to 60 milliamperes maximum.
H
=
DIFFERENTIAL INPUTS
OUTPUT
A-B
R
VID '" 0.2 V
-0.2 V< VID< 0,2 V
H
VID ,;; -0.2 V
L
fI)
"-
II)
>
?
'CD
(J
II)
a:
high level. L = low level, ? = indeterminate
-f I)
logic symbol t
"-
II)
>
';:
C
II)
s::
:i
C>
D (3)
tThis symbol is in accordance with ANSI/IEEE Std 91·1984 and
lEe Publication 617·12.
2:
o
t=
logic diagram
B)A
R
The SN75179B is characterized for operation
from OOC to 70°C.
IT
~
«
(2)
(7)
B
:iE
a:
6)Z
~
oLL
(31
D
(5)
-w
y
2:
CJ
2:
«
>
Q
CD
( I)
V
2
II
a:
ou.
Z
w
(J
TEST CONDITIONS
See Figure 3
MIN
TYP
MAX
15
22
20
30
z
c
'CD
VOLTAGE WAVEFORMS
CD
-...
a:
Ul
CD
>
FIGURE 3. DRIVER DIFFERENTIAL-OUTPUT DELAY AND TRANSITION TIMES
';;:
C
~
--3V
GENERATOR
(S.. Note AI
INPUT
>------it__OUTPUT
50n
1.5 V
tpLH
T
1.5.V
I
I
I
... -'" t
-14-+1
CD
I:
:,:j
I 1.5 V
OV
,............- PHL
~-.-=.~VOH
OUTPU~1.3V
L
VOL
TEST CIRCUIT
z
o
t=
VOLTAGE WAVEFORMS
«
FIGURE 4. RECEIVER PROPAGATION DELAY TIMES
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR :s 1 MHz, 50% duty cycle, tr 56 ns,
1f ,;6 ns, ZOU1 = 50 II.
B. CL includes probe and jig capacitance.
:lE
a:
oLL
Z
W
(,)
Z
~
c
«
~
TEXAS
INSTRUMENTS
4-375
ADVANCE
INFORMATION
SN751798
DIFFERENTIAL DRIVER AND RECEIVER PAIR
TYPICAL CHARACTERISTICS
DRIVER HIGH·LEVEL OUTPUT VOLTAGE
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
DRIVER LOW·LEVEL OUTPUT VOLTAGE
vs
vs
HIGH·LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
OUTPUT CURRENT
S
~
E
"0
4
>
3. 5
~
3
o
3
--
4. 5
Vee'" 5 V
TA=2S"C
>I 4.5
r--
I
ff
a 2.5
b...
2. 5
I
J
&
~
1
1.5
I
~ 0,5
0
o
-20
40
60 -80 -100 -120
IOH-High Level Output Current-rnA
I----
--
~
O. 5
o
~
I'--.
& 2.5
"i!
j
v~e' ~v r-
TA=2S"C
"
.a
~
2
3.S
~
I
"0
> 3.S
..............
~ 1. 5
J:
>I
t
~
~
Vee = 5 V
TA = 2S"C
!
-
:!
I'--.
'\
1.5
o
I
~
~
00
00
100
IOL - Low Leyel Output CurTellt-rnA
00
1~
1\
0.5
\
102030405060 708090100
10 - Output Current-mA
FIGURE 7
FIGURE 6
FIGURE 5
r-
:5'
RECEIVER OUTPUT VOLTAGE
vs
vs
vs
...c
DIFFERENTIAL INPUT VOLTAGE
HIGH·LEVEL OUTPUT CURRENT
FREE-AIR TEMPERATURE
CD
Vec'5V
cE"
I
RECEIVER HIGH·LEVEl OUTPUT VOLTAGE
'TA = 2SoC
10= 0
VID = 0.2 V
TA = 2S"C
CD
ii1
.....
:u
CD
-
C- C-
VIC""
VIC=
OV
VIC=
-12V
VT_
VT
VTI_
I
I
- r- -VT+
n
~VT+
VT+
.......
-
12V
I
I"""~
'\~
~
1,\ ~ , / Vee-I 5.25r V} _. -
CD
<"
CD
...
I~
Vee = 4.75 V
1
111
o
-125
-75
-25
a
o
o
25 50 75 100 125
VID - Differential Input Voltage-mV
I
I
I
I
(')
m
-
:2
."
o
:::a
s:
~
Vee- 5V
'\~
VCC = 5 V
VID""0.2V
IOH'" -4401lA
I'\:
'\:
T A.-Fret·Air Temperature-"'C
FIGURE 10
RECEIVER LOW·LEVEL OUTPUT VOLTAGE
RECEIVER LOW·LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.6
>I
VCC'" 5 V
TA=25"'C
J
i
0
0.4
/
0.3
]
!:.
0
./
O.S
0.2
/
V
~
;
/
~
/'
'OL'8mA
~~__~~~~~
i;
0.3 FI-=f==T-t-+-I-=+==r-~
]
0.2
~-t-t--t-t--t-r-+-I
0.1
~-t-t--+-t--t-~~-I
!
V
~
>
0.1
o
0.4
o
>
o
FREE-AIR TEMPERATURE
0.5 r-~-r-"'-r--r-'r--r--.
Vee"" 5 V
VID = -0.2 V
10
15
~
~
IOL -Low Level Output Current-mA
~
°0~-'1~0-'2~0-'~~~4~0-'5~0-'6~0-'7~0~80·
T A-Free·Air Temperature-"'C
FIGURE 11
FIGURE 12
o
:2
4-376
°0~~1~0~2~0~~~~4~0~SO~~OO~~70~~.0
FIGURE 9
O
~
:2
~
-10
-20
-30
-40
··-50
IOH-High-Level Output Current-mA
FIGURE 8
:t=-
RECEIVER HIGH·LEVEL OUTPUT VOLTAGE
TEXAS . "
INSTRUMENTS
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
01292, OCTOBEA 1972-AEVISEO SEPTEMBER 1986
SN551B2, , ,J PACKAGE
SN751B2 , , , D, J OR N PACKAGE
•
Single 5-V Supply
•
Differential Line Operation
•
Dual Channels
11N-
•
TTL Compatibility
RT
11N+
•
± 15
•
± 15 V Differential Input Voltage Range
•
Individual Channel Strobes
(TOP VIEWI
V Common-Mode Input Voltage Range
•
Built-In Optional Line-Termination Resistor
•
Individual Frequency Response Controls
•
Designed for Use with Dual Differential
Drivers SN55183 and SN75183
VCC
21N2RT
21N+
1STRB
1RTC
2STRB
lOUT
2RTC
GND
20UT
SN551B2 ' , ' FK PACKAGE
(TOP VIEWI
+
U
II.
I
.l:~uu~
Z>N
•
Designed to be Interchangeable with
National Semiconductor DS7820A and
DS8820A
3
1 2019
11N+
4
18
NC
5
6
7
8
17
16
15
14
1STRB
description
2
NC
en
CJ)
>
'iii
tJ
The SN55182 and SN75182 dual differential line
1RTC
receivers are designed to sense small differential
9 10111213
signals in the presence of large common-mode
f-OUf-U
noise, The'se devices give TTL-compatible output
:::JZZ:::JfOt!)
oa:
signals as a function of the polarity of the
NN
differential input voltage, The frequency
NC-No internal connection.
response of each channel may be easily
controlled by a single external capacitor to
provide immunity to differential noise spikes, The output goes to a high level when the inputs are opencircuited. A strobe input is provided which, when in the low level, disables the receiver and forces the
output to a high level.
-.
CJ)
a:
en
CJ)
>
~i:
C
CJ)
:::i
The receiver is of monolithic single-chip construction, and both halves of the dual circuits use common
power supply and ground terminals,
The SN55182 is characterized for operation over the full military temperature range of - 55 D C to 125 D C.
The SN75182 is characterized for operation from 0 DC to 70 DC.
logic symbol t
l1N+
l1N-
(31
logic diagram (positive logic)
&
l1N+
l1N-
lRT
lSTRB
lAT
lRTC
lRTC
lSTRB
(31
(11
lOUT
121
151
(41
21N+
21N2RT
2STAB
2ATC
21N+
21N2AT
tThis symbol is in acco,dance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for 0, J and N packages.
PRODUCTION DATA documents ••lIIIIi. i.fa,matio.
currant as of publication data. Products conform
~·~~:.:.t::d':'cti'":n~~=i~~:::
necessarily inclaile tasting of all parameters.
2RTC
2STRB
, TEXAS'"
INSTRUMENTS
(111
(131
c
20UT
(121
(91
(101
4-377
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
schematic (each receiver)
RESPONSE TIME
CONTROL
FUNCTION TABLE
______-4~--~--_;-(5-.-9)._------~----_.~(~14~)
.Vee
167
H
k
H
5k
320
....- - - -....- - OUTPUT
(6. B)
(3.11)
170
L
4.15
NONINVERTING
INPUT
II
STROBE
5k
DIFF
OUTPUT
INPUT
X
H
L
H
H
L
H = VI '" VIH min or VIO more
positive than VTH max
L = VI s VIL max or VIO more
negative than VTL max
x' = irrelevant
750
RT
(2.12)
'67' k
1k
....---------r----r-------~--....------~(7~)GROUND
167
INVERTING (1.13)
INPUT
~"'5k~~-----'
(4.10)
STROBE
Resistor values shown are nominal and in ohms.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SN551B2
SN751B2
UNIT
Supply voltage. VCCI (see Note 1)
Common-mode input voltage
8
8
V
±20
±20
V
Differential input voltage (see Note 2)
±20
±20
V
8
8
50
50
Strobe input voltage
Output sink current
o package
Continuous
~otal
dissipation at (or below)
25°C free-air temperature (see Note 3)
950
FK package
1375
J package
1375
N package
V
mA
.
Operating free-air temperature range
Storage temperature range
Lead temperature 1.6 mm (1/16 inchl from case for 60 seconds: J package
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds: 0 or N package
Case temperature for 60 seconds: FK package
1025
mW
1150
-55to 125
o to 70
·C
-65 to 150
-65 to 150
·C
300
300
·C
260
·C
260
·C
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground terminal.
2. Differential voltage values are at the non.inverting terminal with respect to the inverting terminal.
3. For operation above 25·C free-air temperature. refer to Dissipation Derating Curves in Appendix A. In the J package. SN551 B2
chips are alloy mounted and SN75182 chips are glass mounted. For these devices in the N package. use the 9.2-mW'·C curve.
For the 0 package use the 7.6-mW'·C curve,
4-378
TEXAs •
INSTRUMENTS
SN55182. SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
recommended operating conditions
SN55182
MIN
NOM
4.5
Supply voltage, VCC
SN75182
MAX
5
5.5
MIN
4.5
MAX
5
5.5
V
±15
V
±15
Common-mode input voltage, VIC
High-level strobe input voltage, VIH(strobe)
2.1
5.5
2.1
5.5
V
0
0.9
0
0.9
16
V
p.A
mA
70
°C
low-level strobe input voltage, Vll(strobe)
High-level output current, 10H
400
400
16
low-level output current, 10l
-55
Operating free-air temperature, T A
UNIT
NOM
125
0
electrical characteristics over recommended ranges of VCC. VIC. and operating free-air temperature
(unless otherwise noted)
PARAMETER
TEST CONDITIONSt
VTH
Differential input high-threshold voltage
VTL
Differential input low-threshold voltage
VOH
Val
VIC -
15Vt015V
1
VIC -
3 V to 3 V
-15Vt015V
-0.5
VID - 1 V,
Vstrobe -.2.1 V,
VIC -
Vstrobe - 0.4 V,
~A
-1
2.5
4.2
5.5
2.5
4.2
5.5
0.25
0.4
3
4.2
0
-0.5
VIC
Noninverting input
II...
II)
V
Q)
>
'Qi
CJ
-...
Q)
a:
V
~
';:
mA
C
Q)
-3 -4.2
15V
5
VIC - 0
-15 V
ISH
High-level strobe current
Vstrobe - 5.5 V
ISl
Low-level strobe current
Vstrobe - 0
ri
Input resistance
RT
line terminating resistnce
TA - 25°C
lOS
Short-circuit output current
VCC = 5.5 V,
VIC = 15 V,
Vo = 0
VID = -1 V
4.2
6
ICC
Supply current (average per receiver)
VIC - 0,
VIC = -15 V,
VID -
6.8
10.2
9.4
14
-1
3.6
-0.5 V
VID = -1 V
r::::
:.:::i
7
1
1.4
7 -9.8
VIC -
I Inverting input
J. Noninverting input
V
I I)
Vstrobe = 2.1 V,
VIC = JJ
VIC - -15 V
Input current
UNIT
V
10l = 16mA
VIC - 15 V
Inverting input
II
10H = -400 ~A
Va - 0.4 V,
10l = 16 mA,
10H = -400
VID = -1 V,
Low-level output voltage
MAX
0.5
VIC -
10H = -400 p.A
1 V,
VID -
High-level output voltage
. MIN TYP*
-3Vt03V
Va - 2.5 V,
5
-1.4
mA
~A
mA
kll
1.8
5
2.5
120
170
250
-2.8
-4.5
-6.7
kll
11
mA
mA
tUnless otherwise noted, Vstrobe .. 2.1 V or open.
*AII typical values are at VCC = 5 V, VIC = 0, and TA = 25°C.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-379
SN55182. SN15182
DUAL DIFFERENTIAL LINE RECEIVERS
Vee -
switching characteristics.
5
V.
TA
PARAMETER
TEST CONDITIONS
MIN
Propagation delay time, low-to-high-Ievel output
tpLH(DI
from differential input
Propagation delay time, high-to-Iow-Ievel output
tPHL(DI
RL = 400O,
from differential input
40
ns
31
45
ns
9
30
ns
15
25
ns
See Figure 1
from strobe input
Propagation delay time, high-to-Iow-Ievel output
tpHL(SI
MAX
18
UNIT
CL = 15 pF,
Propagation delay time, low-to-high-Ievel output
tPLH(SI
TYP
from strobe input
PARAMETER MEASUREMENT INFORMATION
II
INPUT
OUTPUT
4000
PULSE
GENERATOR NO.l.----....- - d
(Soo Note AI
r-
S"
eD
...C
:c"
CD
See Noto C
CL = 15pF
(Se. Note BI
PULSE
GENERATOR NO. 21---~~--"'"
(So. Noto AI
iil
::0
INPUT
CD
n
TEST CIRCUIT
CD
:c"
CD
.Jt
:--tw---1
iil
OV'''--_--dtt~,---Itov
ov
INPUT _ _ _ _
I
I
--.I> 100 ns I.--
1
STROBE
J1.3V
--l> 100 nsr----
I
I
!
OUTPUT
1.3V~
I
;-.f-tPLH(D)
i
..il1.3V
"-----/'
OV~ ~:.:v
--l >100 ns :.1.3V~
,..---"\'
1.3V'
-----'I-~I
1.--1
I
I
I
tPHL(DI-4----.f
J...- tw--'I
I
I
---' >100 ns
l{l
l1.3V
f<
I
:
I
:
\1.3V
I
: .
tPHL(S)+--t
--- -
-
-
:.:V
I
I
:
VOH
: ./1.3V
Iii. - ----- VOL
---t+tPLH(S)
VOLTAGE WAVEFORMS
NOTES: A. The pulse generators have the following characteristics: Zo = 500, tr :S 10 ns, tf S 10 ns, tw = 0.5 ±0.1 ~s, PRR S 1 MHz.
B. CL includes probe and jig capacitance.
C. All diodes are 1N3064 or equivalent.
FIGURE 1. PROPAGATION DELAY TIMES
4-380
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN55182. SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
TYPICAL CHARACTERISTICS t
DIFFERENTIAL INPUT THRESHOLD VOLTAGE
DIFFERENTIAL INPUT THRESHOLD VOLTAGE
vs
vs
SUPPLY VOLTAGE
COMMON·MODE VOLTAGE
0.3
0.5
>I
V,C= 0
TA = 25 c C
.,en
e
o
0.2
>
0.3
o
0.2
"C
0.1
o
----
]c: -01
.
-5
~
Va = 2.5 V
--':":::'~a = -400 f.1A
Va
0
Co
c:
"iii
.;::;
I---------
-0.1
r--
c: -0.2
~
~
~
is -0.2
-
Va =
4OOf.1A
O.~ V I
-~O=16
-
--..:.::~
...
CI)
~ -0.3
is
I
Q)
I
C -0.4
c
->
-> -0.3
4.5
0.1 f-= Va = 2.5 V, 'a -
...:;
.s::;
,j J
0.4 V, la - 16 mA -
Vce = 5 V
TA = 25°C
0.4
5.5
5
VCC-Supply Voltage-V
6
-0.5
-20
>
'Q)
.-
CJ
-10
10
o
Vlc-Common·Mode Input Voltage- V
Q)
20
a:
--...
CI)
Q)
FIGURE 3.
FIGURE 2.
DIFFERENTIAL INPUT THRESHOLD VOLTAGE
>
.;:
C
Q)
vs
c:
FREE·AIR TEMPERATURE
:::i
>
E
I
&
e
o
50 f---J--+---i"'--':'
>
"C
o
-5
~
......
.s::;
-50f---+---+---+---~--+---~~--~
::I
Co
c:
~
-100
f---+----+-""'~.
C
~
~ -1501---J--fis
I
C
->
__~__- L__- L__~__L -__L-~
-75 -50 -25
o 25 50 75 100 125
-200L-~
TA-Free·Air Temperature-OC
FIGURE 4.
tData for temperatures below DoC and above 70 0
e are applicable to SN55182 circuits
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
only.
4-381
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
TYPICAL CHARACTERISTICS t
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
5
VCC=5V
'"
'"
:!
...
"0
II
1
VCC=5V
VIC=O
_ sV lOH=-400J.lA,.::::;;
,
VIO- O-
-
4
>I
VOLTAGE TRANSFRER CHARACTERISTICS
5
4
>I
.,
co
'"
3
~
....
>
::I
0
I
0
CI.
2
::I
0
I
0
>
r-
CD
VID = -0.5 V, IOL = 16 mA-
2 r---
o
-75 -50 -25
0
25
50
75 100 125
TA-Free-Air Temperature-'C
...
~
-0.5
~
I
I '/"
I ITA = _55°C
1I I
:; '/
I II
11I /J
=1125 C
r--
o
<'
CD
4 eac~
lN3064
,
10 ~\.
>
5'
o...
3
::I
CI.
rf
r-t
r?t::--
UNOEATEST
>
::I
~ ~ .....
I
fROM OUTPUT
0
-
TA = 25°C
I
0_1
0.3
-0.1
-0.3
VID-Oifferentiallnput Voltage-V
0.5
UI
ii
CD
FIGURE 6
FIGURE 5
n
CD
<'
INPUT CURRENT
vs
INPUT VOLTAGE
CD
til
TERMINATING RESISTANCE
vs
FREE-AIR TEMPERATURE
10
8
6
«
E
I
200
VCC=5V
VID = 0 to ±20 V
TA = 25°C
",V
4
'C
2
:;
0
~
u
ic
-2
~\'u-t
".?'
'"
/
.....V
'"
~
I
180
/
'"
c
.~
8~
'E
170
l;
160
~
-8 ~~~I
-10
-20
.j.,
V
0:
~~'~
~«,.~
-6
190
tl
c
~,,~V--t\~~V
1\)-<'
;..:-T -4
1
10
-10
o
VI-Input Voltage-V
20
4-382
o·e
and above
150
-75 -50 -25
0
25
50
75
T A -Free-Ai~ Temperature-° C
FIGURE 8
70De
1/
.....- /"
FIGURE 7
toata for temperatures below
/
are applicable to SN55182 circuits·only.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 866012 • DALLAS, TEXAS 76265
100 125
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
TYPICAL CHARACTERISTICS t
SUPPLY CURRENT
POWER DISSIPATION
(AVERAGE PEA RECEIVER)
(AVERAGE PER RECEIVER)
COMMON·MODE INPUT VOLTAGE
COMMON·MODE INPUT VOLTAGE
12
300
Vee" 5V
l"- I"'f---
~
b 200
v:--' 'Iv
'-~
I----
'i
IO.~ ' -
-
V
.........
100
T~~
TAl
0
-20
20
1//
\~A-25°C
I
'-
Max rated Po at TA '" 12SO C
\~
J
-10
10
VIC-Common-Mode Input Voltage-V
/
~
o
-20
VID"'-1V
\
~
r--..,
........
Vcc- 5V
1
No load
TA = 25°C
125°C
I
/'
I
',=
L'
/
10
-10
Vlc-Common.Mode Input Voltage-V
FIGURE 9
II
20
FIGURE 10
I/)
~
Q)
>
NOISE PULSE DURATION
'G)
RESPONSE TIME·CONTROL CAPACITANCE
!
1000
Vee - 5 V
U
700
'cI
TA 25°C
See Note 4
a:
400
.,;
200
Q)
~
!~ l00~;i~!I~~i!II~~~1I
==.r----c=0V
I
-2.SV
I /)
~
Q)
>
'0::::
I
C
j+---1- t w
70
..E
--
2.5V~~-~~-C1 ____ _
f-+-t-ttttttt-H-bI'I-tttt---t+ttH-tti
Q)
r:::
::i
40
~
I
}
IO,LO-L-Ll'O=IUlOO-:-L40.LO.LLI.ll,1LOO::-O...L.~ooo'::u~,O,OOO
Response Time Control Capacitance-pF
FIGURE 11
INPUT PULSE FOR FIGURE 11
PROPAGATION DELAY TIMES FROM
DIFFERENTIAL INPUT
,
PROPAGATION DELAY TIMES FROM STROBE INPUT
FREE·AIR TEMPERATURE
Vee "'5 V
See Figure 1
J4
tPHL(D)
....-
V
FREE·AIR TEMPERATURE
-
20
Vee 5V
18 See Figure 1
--
16
r-....
-
....-
-
14
12
10
I.
......-
tPLH(D)
18
--r--I
75
50 -25
0
25
50
75
•
100 125
./
~HLI~I
n
V
/
tPLH(S)
V
......-
T A-Free·Air Temperature-Oe
-75 --50 -25
0
25
50 15 100 125
TA-free·Air Temperature-°e
FIGURE 12
FIGURE 13
toata for temperatures below Doe and above 7Doe are applicable to SN55182 circuits only.
NOTE 4: Figure 11 shows the maximum duration of the illustrated pulse that can be applied differentially without the output changing
from the low to high level.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-383
SN55182, 5175182
DUAL DIFFERENTIAL LINE RECEIVERS
TYPICAL APPLICATION DATA
Vee = 5 V
J
'12'182
r----- -l
INV
INPU-T
I
I
II
I
I
O.002I'F
{See Note AI
I
TWISTED
STROBE-+----~
PAIR
II
r-
S'
I
IL __ GND ___ JI
~
....
NOTES: A. When the inputs are open-circuited, the output will be high. A capacitor may be used lor dc isolation 01 the line-terminating
resistor. At the frequency of operation, the impedance of the capacitor should be relatively small.
CD
I = 5 MHz
C = 0.002 ~F
Example: let
C
::::!,
<
Ul
CD
Zc =
1
2rlC
::rJ
Zc
~
160
-
2". {5 x 106 1 (0.002 x 10- 6 )
B. Use of a capacitor to control response time is optional.
CD
n
CD
FIGURE 14_ TRANSMISSION OF DIGITAL DATA OVER TWISTED-PAIR LINE
~'
Ul
4-384
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN55183, 5N75183
DUAL DIFFERENTIAL LINE DRIVERS
01292, OCTOBER 1972-REVISEO SEPTEMBER 1986
•
•
•
•
•
•
•
•
•
•
•
SN55183 ... J PACKAGE
SN75183 ... 0, J OR N PACKAGE
Single 5-V Supply
Differential Line Operation
(TOP VIEW)
Dual Channels
1A
TTL Compatibility
18
VCC
20
1C
2C
Short-Circuit Protection of Outputs
10
28
Output Clamp Diodes to Terminate Line
Transients
1Y
2A
1Z
2Y
GNO
2Z
High-Current Outputs
Quad Inputs
SN55183 ... FK PACKAGE
(TOP VIEW)
Single-Ended or Differential AND/NAND
Outputs
U
IXl«UUO
~~z>'"
Designed for Use with Dual Differential
Drivers SN55182 and SN75182
..
3 2 1 2019
Designed to be Interchangeable with
National Semiconductor DS7830 and
DS8830
description
18
2C
5
17
NC
6
16
28
7
15
NC
8
14
2A
III
~
';
(J
-.
CD
a:
I II
9
The SN55.183 and SN75183 dual differential line
drivers are designed to provide differential output
signals with high-current capability for driving
balanced lines, such as twisted-pair, at normal
line impedances without high power
dissipation. These devices may be used as TTL
expander/phase splitters, as the output stages
are similar to TTL totem-pole outputs.
CD
NOUN>-
>
~2ZNN
';:
(!l
C
CD
NC - No internal connection.
C
::;
The driver is of monolithic single-chip construction, and both halves of the dual circuits use common power
supply and ground terminals.
The SN55183 is characterized for operation over the full military temperature range of - 55°C to 125°C,
The SN75183 is characterized for operation from ooe to 70°C.
logic symbol t
1A
1B
1C
10
2A
2B
2C
20
(1)
logic diagram (positive logic)
&[>
(2)
(5)
1Y
(3)
(4)
1Z
1A
(1)
1B
(2)
1C
(3)
10
(4)
2A
(10)
(10)
(11)
2Y
1121
(13)
2Z
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for 0, J, and N packages.
2B
(11)
2C
(12)
20
(131
2Y
2Z
positive logic:
v = ABCD
Z
PRODUCTION DATA documents contain information
currant as of publication date. Products conform
to specifications per the terms of Texas Instruments
standard warra~. Production processing dOBS not
necessarily includa tasting of all parametars.
=
ABeD
Copyright @ 1986, Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-385
SN55183. SN75183
DUAL DIFFERENTIAL LINE DRIVERS
schematic (each driver)
(14)
vee
v
2k
9
(6,8)
A
(1,10)
B
(2,11)
e
(3,12)
z
r-
:r
CD
C
""'<"
CD
""'
-(/I
4k
3k
3.2 k
:tJ
CD
9
(')
CD
o
<"
(4,13)
(5,9)
CD
v
""'
(/I
'--_+-_.....__....-4_ _(;...;..7)
L-_ _
Resistor values shown are nominal and in ohms.
4-386
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
GND
SN55183, SN75183
DUAL DIFFERENTIAL LINE DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SN55183
Supply voltage, Vee (see Note 11
Input voltage
Duration of output short-circuit (see Note 21
SN75183
UNIT
7
7
V
5.5
5.5
V
1
1
s
D package
950
Continuous total dissipation at (or below)
FK package
25°C free-air temperature (see Note 31
J package
1375
1375
1025
Operating free-air temperature range
-55 to 125
o to 70
°e
Storage temperature range
-65 to 150
-65 to 150
°e
260
300
300
°e
°e
260
°e
N package
mW
1150
Case temperature for 60 seconds: FK package
Lead temperature 1,6 mm (1/16 inchl from case for 60 seconds: J package
Lead temperature 1,6 mm (1/16 inchl from case for 10 seconds: D or N package
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground terminal.
2. Not more than one output should be shorted to ground at a time.
3. For operation above 25°C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the J package, SN55183
chips are alloy mounted and SN75183 chips are glass mounted. For these devices in the N package, use the 9.2-mW/oC curve.
For the D package, use the 7.6-mW/oe curve.
II
..
II)
Q)
>
"Qi
recommended operating conditions
U
Q)
SN55183
Supply voltage, Vee
High-level input voltage, VIH
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
2
Low-level input voltage, VIL
Low-level output current, IOL
Operating free-air temperature, T A
-55
electrical characteristics over recommended ranges of
(unless otherwise noted)
PARAMETER
High-level output voltage
Y
VOH
Low-level output voltage
High-level output voltage
OUTPUT
=
2 V,
Z
VOL
Low-Ievael output voltage
IIH
II
Input current at maximum input voltage
OUTPUT
V,
=
mA
40
40
mA
70
°e
125
0
MIN Typt
1.8
10L - 40 mA
10H - -0.8 mA
10H
-40
-40 rnA
IOL - 32 rnA
= 0.8
0.8
-40
2.4
10H -
VIL
0.8
V
V
-0.8 mA
VIH - 2 V,
-40 mA
0.22
1.8
10L - 40 mA
0.22
Low-level input current
Vee
ICC
Supply current (average per driver)
Vee - 5 V,
No load
=
5 V,
I I)
Q)
>
";:
o
Q)
c:
::::i
TA = 125°C
All inputs at 5 V,
UNIT
V
V
3.3
VIH - 2 V,
Short-circuit output current t:
0.4
2.4
0.2
IlL
--..
V
3.3
10L - 32 mA
lOS
MAX
0.2
VIH - 2 V,
VIH = 2.4 V
VIH = 5.5 V
VIL - 0.4 V
High-ievel input current
=
VIL - 0.8 V,
VIL - 0.8 V,
VIL - 0.8 V,
(NANDI
IOH
2
a:
and operating free-air temperature
TEST CONDITIONS
VIH
(ANDI
VOL
Vee
UNIT
MIN
High-level output current, 10H
VOH
SN75183
0.4
V
120
~A
2
4.8
rnA
mA
-40 -100 -120
mA
10
18
rnA
t All typical values are at Vee = 5 V, TA = 25°C.
iNot more than one output should be shorted to ground at a time and duration of the short-circuit should not exceed one second.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-387
SN55183, SN75183
DUAL DIFFERENTIAL LINE DRIVERS
switching characteristics, Vee - 5 V, TA - 25°e
TEST CONDITIONS
PARAMETER
Propagation delay time,
tpLH
tpHL
tpLH
tpHL
low-to-high-Ievel Y output
AND
,..
Propagation delay time,
gates
high-to-Iow-Ievel Y output
MIN
CL = 15 pF,
See Figure 1(a)
Propagation delay time,
low-to-high-Ievel Z output
NAND
Propagation delay time,
gates
high-to-Iow-Ievel Z output
UNIT
TYP
MAX
8
12
ns
12
18
ns
6
12
ns
6
8
ns
9
16
ns
8
16
ns
Propagation delay time,
tpLH
low-to-high-Ievel
Youtput
with respect
to Z output
differential output
Propagation delay time
•
tpHL
high-to-Iow-Ievel
ZL = 100 0 in s.eries
with 5000 pF,
See Figure 1(b)
differential output
I"'"
PARAMETER MEASUREMENT INFORMATION
:i"
CD
VCC=±5V
INPUT
...c
INPUT J . l , 5 V
~.
:
;
:
I
-.!tPLH
:JJ
I
CD
I
~.
I
~
Y
I
OUTPUT
Z
-.r.---.J
I
L ___ -
-=
OUTPUT
-::!:,CL
-=
= 15 pF
Z
(Sao Nota B)
14::
'
2.5V
ov
I
---.j tpH L I+-
~
I
1,5V
I
1.5V
I
I
VOL
I
---I tPLH~
V
'
OH
I
1.5V
1.5V
~
,
--.I
OUTPUT
\1~~-- -
TEST CIRCUIT
----VOH
I
I
tPHLj.=:
- - - - - VOL
VOLTAGE WAVEFORMS
(a)-OUTPUTS Y AND Z
INPUT
VCC=5V
Y
INPUT
OUTPUT
I
-.jtPLH
I
I
I
I
I
I
I
'------.J.--.J
Z
\..1.~~---- 3V
.11.5 V
Jj
j\
OV
~
-.jtPHL!4DIFFERENTIAL ~.,
- - - - +VYS
OUTPUT
OV
OV
VOLTAGE
-VYS
OUTPUT
TEST CIRCUIT
VOLTAGE WAVEFORMS
(b)-DIFFERENTIAL OUTPUT
NOTES: A. The pulse generators have the following characteristics: Zo = 50 0, t,
B. CL includes probe and jig capacitance.
C. Waveforms are monitored on an oscilloscope with Rin
!'l'"
0
..,>
0
1.8
1.6
'"
!'l
0
1.4
~
::::::t'-
--::::
.r:;
I-
I
1.0
I-
>
I
>
...
NAND GATE
AND GATE--=
1.2
/
I
0
I
, I
0
I,
J:
>
0.6
I
25
50
75
100
.......
,/
/l /
/1 I
VIL max
0
,, ~ ~ I/TIA=2~oC
I
I
1 o
C
I
~ ~TA=-55
/ I
'"
~
50n LOAD
I
,
2
'"
S-
0.8
0.4
-75 -50 -25
VCC = 5 V
H...: ~
,
I
CI>
.r:;
,
i'..
3 "- I
>I
<::::: t::-
,
,~onLloADI
VIHmin
2_0
>I
,I
200 n LOAD
~
o
125
I
•
\
II)
"-
TA = 125°C
CD
>
I
'Qi
()
o
CD
-20 -40 -60 -80 -100 -120 -140-160
TA-Free-Air Temperature-OC
a:
IOH-Output Current-mA
I I)
"-
FIGURE 2
CD
FIGURE 3
>
';:
C
DIFFERENTIAL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
vs
vs
DIFFERENTIAL OUTPUT CURRENT
OUTPUT CURRENT
4
CI>
'"
!'l
0
3
>
...
'"
S0'"
OJ
c:::
::i
3
VCC=5V
VCC=5V
>I
CD
s:::........ :--....
I
'o
TA=125C
.:::::8: ~
-......:
2
>I
CI>
co
!'l
~ t".....
:--....
c
~
~
TA=-55°C-
i3
I
~
\
>
>
25
>
...
1\
>
~
\ \
50
75
100
o
125
.--o
f.-"
......... V
20
40
60
V
~::'25°C
I I
r-
80 100 120 140 160 180 200
FIGURE 5
FIGURE 4
coe
/'
IOL -Output Current-mA
IOD-Differential Output Current-mA
tOata for temperatures below
/
I/
TA = _55°C
'"
0
I
..J
0
........
,,/
...,-
TA = 25°C (
'"
S-
t- r--- 11. r\
N
o
o
0
TA = 25°C
'';:
".
2
,,/
and above 70°C are applicable to SN5S183 circuits only.
TEXAS
..II
INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS, TeXAS 75265
4-389
SN55183, SN75183
DUAL DIFFERENTIAL LINE DRIVERS
TYPICAL CHARACTERISTICS t
TOTAL POWER DISSIPATION
(BOTH DRIVERS)
vs
FREQUENCY
PROPAGATION DELAY TIME OF
DIFFERENTIAL OUTPUT
vs
FREE-AIR TEMPERATURE
20
240
.~
I
VCC=5V
See Figure 1(b)
220
~ 200
~
.
c
I
15
E
>
co
Qj
0
---
tPLH
10
c
0
.~
tpHL
'"
11
...e
r-
:i'
5
-~
'CD
...c
...<'
-75 -50
::1:1
<'
...
'1
~
--
~
---
;...- '--'
o"=
140
"
120
~
-
~
I
_
V
....
~
100
80
o
~
180
160
60
CD
til
CD
I
c
o
j::
VCC=5V
No load
Input: 3-volt square wave
TA =25°C
40
0.1
-25 0
25
50
75 100 125
TA-Free-Air Temperature-oC
0.4
4
FIGURE 6
tOata for temperatures bela\/\(
ooe
10
40
100
f-Frequency-MHz
FIGURE 7
and above 70°C are applicable to SN55183 circuits only.
TYPICAL APPLICATION DATA
CD
til
Vee = 5 V
%SN55182
r----INV
I
I
INPUT
I
J -l
.
II
I
0.002 ",F
(See Note A)
I
TWISTED
PAIR
I
I
GND
I
L--'l----J
-=-
NOTES: A. When the inputs are open-circuited, the output will be high. A capacitor may be used for de isolation of the line-terminating
resistor. At the frequency of operation, the impedance of the capacitor should be relatively small.
Example: let
,
=
e
=
5 MHz
0.002 ~F
Ze =_1_
21rle
2" 15 x 106 ) 10.002 x 10 - 6)
Ze = 16 (J
B. Use of a capacitor to control response time is optional.
FIGURE 8. TRANSMISSION OF DIGITAL DATA OVER TWISTED-PAIR LINE
4-390
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN55188, SN75188
QUADRUPLE LINE DRIVERS
01323. SEPTEMBER 1983-REVISEO SEPTEMBER 1986
•
Meets Specifications of EIA RS-232-C
•
Designed to be Interchangeable with
Motorola MC1488
•
Current-Limited Output: 10 mA Typ
•
Power-Off Output Impedance: 300
•
Slew Rate Control by Load Capacitor
SN55188 ... J PACKAGE
SN75188 ... D OR J PACKAGE
(TOP VIEW)
VCC-
Min
(J
•
Flexible Supply Voltage Range
•
Input Compatible with Most TTL Circuits
GND
SN55188 ... FK
CHIP CARRIER PACKAGE
description
The SN55188 and SN75188 are monolithic
quadruple line drivers designed to interface data
terminal equipment with data communications
equipment in conformance with EIA Standard
RS-232-C using a diode in series with each
supply-voltage terminal as shown under typical
applications.
(TOP VIEW)
I
«
3
The SN55188 is characterized for operation over
the full military temperature range of - 55°C to
125°C. The SN75188 is characterized for
operation from OOC to 70°C.
2A
lA
28
II
.
+
u
u
uu U III
>Z>
"iii
(l
-.
CD
15
NC
14
38
9 10111213
a:
en
CD
>
".::
;..OU;..«
C
""ZZ"''''
l?
logic symbol t
2A
VCC+
48
4A
4Y
38
3A
3Y
1A
1Y
2A
28
2Y
(2)
[>
(4)
(5)
&[>
NC - No internal connection
IV
CD
c:
:.:::i
logic diagram (positive logic)
2V
(9)
~
3A
(10)
38
(12)
4A
(13)
48
'A~'V
2A
28
tThis symbol is in accordance wilh ANSI/IEEE Std 91-1984 and
lEG Publication 617-12.
3A
(4)
(5)
(9)
(10)
38
FUNCTION TABLE
(DR)VERS 2 THRU 4)
H
L
X
A
B
Y
H
H
L
X
L
H
X
L
H
= high level.
= low level.
= irrelevant
PRODUCTION DATA do.umo.'••0.111. i.lormOllo.
.urro.' al 01 publi.olion dall. Producls .onform 10
spacific.tians par the terms of TaXI. Instrumants
::-=~~I~.{::I~'li ~!:~:~ti:r l!~D::;:~~:~ not
4A
48
(12)
(13)
~2V
~3V
~4V
Positive logic
y = Ii. (driver 1)
Y = AS or Ii. + B (drivers 2 thru 4)
Pin numbers shown are for D, J, and N packages.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-391
SN55188, SN75188
QUADRUPLE LINE DRIVERS
schematic (each driver)
TO OTHER
DRIVERS
VCC+----. .----~------------~~----_1~------_,
B.2k
INPUT(S){A
B----J4--t-____~._~--_.----~30~O~-OUTPUT
•
GND
TO
I"""
3.7 k
S'
70
CD
VCC_--~~--____----~----------~~------~----~
C
All resistor values shown
:::!,
are nominal and in ohms.
<
CD
Cil
~
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SN55188
CD
SN75188
UNIT
n
Supply voltage VCC + at (or below) 25°C free-air temperature (see Notes 1 and 2)
15
15
V
~'
Supply voltage VCC _ at (or belowl 25°C free-air temperature (see Notes 1 and 2)
15
15
V
CD'
....
til
Input voltage range
-15 to 7
-15 to 7
V
Output voltage range
-15 to 15
-15 to 15
V
o package
950
Continuous total dissipation at (or below)
FK package
1375
25°C free-air temperature {see Note 2}
J package
1375
mW
1025
N package
1150
Operating free-air temperature range
-55 to 125
Oto 70
Storage temperature range
-65 to 150
-65to 150
Case temperature for 60 seconds
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds
I FK package
I J package
260
300
300
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: o or N package
. NOTES:
260
°C
DC
°C
DC
1. All voltage values are with respect to the network ground terminal.
2. For operation above 25°C free-air temperature, refer to the Maximum Supply Voltage Curve, Figure 6, and the Dissipation
Derating Curves in Appendix A. In the J package, SN55188 chips are alloy mounted and SN75188 chips are glass mounted.
recommended operating conditions
SN55188
MIN
NOM
SN75188
MAX
MIN
NOM
MAX
UNIT
Supply voltage, VCC +
7.5
9
15
7.5
9
15
V
Supply voltage, VCC-
7.5
9
-15
-7.5
-9
-15
V
High-level input voltage, VIH
1.9
Low-level input voltage, VIL
0.8
Operating free-air temperature, T A
4-392
1.9
-55
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
125
0
V
0.8
V
70
°C
SN55188. SN75188
QUADRUPLE LINE DRIVERS
electrical characteristics over operating free-air temperature range, Vee +
(unless otherwise noted)
PARAMETER
9 V, vee-
SN55188
MIN Typt MAX
TEST CONDITIONS
ISee Note 31
VOH
VOL
High·level output voltage
RL - 3kll
low-level output voltage
RL
=
6
7
6
7
9
10.5
9
10.5
-
3 kll
IIH
High-level input current
VI - 5 V
IlL
Low-level input current
VI - 0
Short-circuit output
laSIHI
current at high leverl:
Short-circuit output
laSILI
ro
current at low level t
Output resistance.
power off
Supply current
ICC+
from VCC+
VI
= 0.8
VI
=
V
=
-7
-6
-7
-6
-10.5
-9
-10.5
-9
10
I'A
-1
-1.6
-1
-1.6
mA
-6
-9
-12
mA
6
9
12
mA
V
13.2 V,
VCC+
VCC-
-13.2 V
10
V,
Va
=0
-4.6
1.9 V,
Va
=0
4.6
-9-13.5
VCC- - 0,
VCC+ - 9 V,
No load
All inputs at 1.9 V
15
Supply current
ICC-
from ICC-
VCC- = -12 V,
No load
300
Total power dissipation
20
15
All inputs at 0.8 V
4.5
6
4.5
6
19
25
19
25
All inputs at 0.8 V
5.5
7
5.5
All inputs at 1.9 V
34
All inputs at 0.8 V
All inputs at 1.9 V
-17
-23
7
-18
-23
-15 V,
All inputs at 1.9 V
VCCNo load, TA = 25°C All inputs at 0.8 V
-34
-34
-2.5
-2.5
333
333
576
576
=
-9 V,
VCC+ = 12 V,
No load
VCC-
=
-12 V,
! II
Q)
>
C
';:
Q)
c:
::::;
-0.015
-0.5
VCC-
-..
-17
All inputs at 0.8 V
VCC+ = 9 V,
No load
mA
u
Q)
a:
12
-13
-0.5
-18
II
34
12
-13
Q)
>
'iii
20
All inputs at 1.9 V
-
Po
13.5
300
All inputs at 1.9 V
VCC+ - 15 V,
No load, TA = 25°C All inputs at 0.8 V
VCC- = -9 V,
No load
II
..
!II
9
VCC+ - 0,
Va = -2Vt02V
VCC+ - 12 V,
No load
UNIT
ISee Note 31
VCC+ - 13.2 V,
-13.2 V
VCCVCC+ - 9 V,
VCC- = -9 V
VIH ~ 1.9 V,
SN75188
MIN Typt MAX
VCC+ - 9 V,
-9 V
VCC-
-
VIL - 0.8 V,
-9 V
-0.015
mA
mW
t All typical values are at TA = 25°C.
:t Not more than one output should be shorted at a time.
NOTE 3: The algebraic convention in which the less positive (more negative) limit is designated as minimum, is used in this data sheet
for logic voltage levels only. e.g., if -6 V is a maximum, the typical value is a more negative voltage.
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-393
SN55188, SN75188
QUADRUPLE LINE DRIVERS
switching characteristics. VCC+ - 9 V. VCC- PARAMETER
-9 V. TA - 25°C
TEST CONDITIONS
MIN
tpLH
Propagation delay time, low-to-high-Ievel output
tpHL
tTLH
Propagation delay time, high-to-Iow-Ievel output
Transition time, low-to-high-Ievel output t
Transition time, high-to-Iow-Ievel output t
RL=3kll,
See Figure 1
Transition time, low-to-high-Ievel output*
RL = 3 kll to 7 kll, CL = 2500 pF,
See Figure 1
trHL
tTLH
tTHL
Transition time, high-to-Iow-Ievel output*
CL = 15 pF,
TVP
MAX
UNIT
220
350
175
ns
100
75
ns
ns
100
55
45
2.6
3.0
t Measured between 10% and 90% points of output waveform.
* Measured between + 3 V and - 3 V points on the output waveform lElA RS-232-C conditions)
PARAMETER MEASUREMENT INFORMATION
•
INPUT
c:
PULSE
GENERATOR
(So. NotoA)
:::I
..
CD
~------__--~---OUTPUT
1
C
~'
Cil
::a
CD
n
CD
CL
(SHNatoB)
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES; A. The pulse generator has the following characteristics: tw = 0.5
B. CL includes probe and jig capacitance.
..<'
p.S,
PRR
s 1 MHz, Zo = 50 11.
FIGURE 1. PROPAGATION AND TRANSITION TIMES
CD
en
4-394
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 855012 .' DAUAS, TEXAS 76286
ns
~s
p'S
SN55188, SN75188
QUADRUPLE LINE DRIVERS
TYPICAL CHARACTERISTICS t
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
VOLTAGE TRANSFER CHARACTERISTICS
20
12
Vcc+ = 12 V, VCC- = -12 V
9
:r
t
>
'"
0
I
0
I
12
.
.''""
0
-3
8
~
4
I.J
0
&
-4
9'"
> -6
-12
E
I
c
3 VCC+= 6 V, VCC- = -6 V
9
-8
-12
-9
RL =3kn
TA = 25°C
o
-16
0.2 0.4 0.6 0.8
1
VCC+=9V
VCC-= -9V
TA = 25°C
'c(
6 VCC+ = 9 V, VCC-= -9 V
.&
15
I
16
1.2 1.4 1.6 1.8
V
..... t ....I
/
- -.. -f.
...
/
/
~y
j
V
J
'..,.~
arnl
LOAD LINE-
•
.>
II)
8
/- -:-:"0\'\\V\"I 0. I
-20
-16 -12
2
~.9VI~
/
VOLlvl =
CD
'iii
Co)
-8
VI-Input Voltage-V
-4
o
4
12
8
16
YO-Output Voltage-V
FIGURE 2
-.
CD
a:
I I)
CD
>
FIGURE 3
'~
12
1
9
c
l!!
6
.
VCC+=9V
9V
VCC
RL=oo
TA = 25°C
-
'OSllI IV, = 1.9 VI
OJ
.i'"
..
.
0
~
<;i
~
.c
'1
til
9
CD
c
:.:i
1000
I
I.J
Q
SLEW RATE
vs
LOAD CAPACITANCE
SHORT·CIRCUIT OUTPUT CURRENT
vs
FREE·AIR TEMPERATURE
..
~
3
100
:r
~
0
a:
VCC+=9V
-3 I-VCC_= -9V
VO=O
~
iii
10
-6
loS(HI (VI = 0.8 VI
-9
-12
-100-75 -50 -25
0
25
50 75 100 125 150
1
10
100
1000
10,000
CL -Load Capacitance-pF
TA-Free·Air Temperature-·C
FIGURE 4
FIGURE 5
tOata for tempeatures below Qoe and above 7Qoe are applicable to SN55188 circuit only.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-395
SN55188, SN75188
QUADRUPLE LINE DRIVERS
THERMAL INFORMATIONt
MAXIMUM SUPPLY VOLTAGE
vs
FREE-AIR TEMPERATURE
16
-,....
14
>I
12
l!
10
......
8
3.
~
~
1"+I
----
6
U
u
~
r-
4
S·
2
C
o
CD
:2.
RL ~ 3 k~ (fro~ eac~ out~ut to proun11
-75 -50 -25
li
0
25
50
75
100 125
T A-Free-Air Temperature-°c
til
FIGURE 6
~
CD
tData for temperatures below ooC and above 70°C are applicable to SN55188 circuit only.
C')
CD
~.
...
TYPICAL APPLICATION DATA
U)
Diodes placed in series with the VCC+ and VCC- leads will protect the SN55188/SN75188 in the fault condition in which the
device outputs are shorted to ± 15 V and the power supplies are
at low voltage and provide low-impedance paths to ground,
Vcc+= 12V
VCC- = -12V
:I ....
0"
.."'c'"
.. 0
=> ....
H
__ D' -----!1-::-.. .--
OUTPUT TO HNIL
-O.7VT010V
1/4SN56188
OR SN75188
FIGURE 8. POWER SUPPLV PROTECTION TO MEET
POWER-OFF FAULT CONDITIONS OF
EIA STANDARD RS-232-C
-12V
FIGURE 7. LOGIC TRANSLATOR APPLICATIONS
4-396
TEXAS . .
INSTRUMENTS
~ST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN55189. SN55189A. SN75189. SN75189A
QUADRUPLE LINE RECEIVERS
D1619, SEPTEMBER 1973-REVISED SEPTEMBER 1986
SN55189. SN55189A ... J PACKAGE
SN75189. SN75189A ... D. J. OR N PACKAGE
•
Input Resistance ... 3 kO to 7 kO
•
Input Signal Range . . . ± 30 V
•
Operates from Single 5-V Supply
•
Built-in Input Hysteresis (Double Thresholds)
•
Response Control Provides:
Input Threshold Shifting
Input Noise Filtering
•
Satisfies Requirements of EIA RS-232-C
•
Fully Interchangeable with Motorola
MC1489. MC1489A
(TOP VIEW)
lA
lCONT
1Y
2A
2CONT
2Y
GND
VCC
4A
4CONT
4Y
3A
3CONT
3Y
SN55189. SN55189A .. . FK PACKAGE
(TOP VIEW)
I-
description
Z
0
U
These devices are monolithic Low-power
Schottky quadruple line receivers designed to
satisfy the requirements of the standard
interface between data terminal equipment and
data communication equipment as defined by
EIA Standard RS-232-C. A separate response
control terminal is provided for each receiver. A
resistor or a resistor and bias voltage source can
be connected between this terminal and ground
to shift the input threshold levels. An external
capacitor can be connected between this
terminal and ground to provide input noise
filtering.
The SN55189 and SN55189A are characterized
for operation over the full military temperature
range of -55°C to 125°C. The SN75189 and
SN75189A are characterized for operation from
OOC to 70°C.
~
2
1Y
NC
2A
NC
2CONT
U
Z
II
...
U
U~
>'d"
1 2019
4
II)
5
18
17
6
16
15
8
14
4CONT
NC
4Y
NC
3A
Q)
·W>
(,)
Q)
a::
--...
I I)
9 10 11 1213
Q)
>
.;:
>-OU>-I-
NZZMZ
(!)
0
C
U
M
NC~No
Q)
I:
internal connection
::i
logic diagram (each receiver)
A~Y
RESPONSE~
logic symbol t
CONTROL
1A (1)
2 CONT
3A
3 CONT
3Y
4Y
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for 0, J, and N packages.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~~:~~i~ai~:1~1~ ~!::i~~ti:: :1~O::::~:t::s~S not
Copyright
TEXAS
-I!}
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS, TEXAS 75265
©
1980, Texas Instruments Incorporated
4-397
SN5518~
SN55189A,
SN7518~
SN75189A
QUADRUPLE LINE RECEIVERS
schematic (each receiver)
r---e-------~~--VCC
5 kO
\ 9 kO
2 kO
OUTPUT Y
RESPONSE ________~--~R~lv_~--_4~~~
CONTROL
4 kO
INPUT A
III
--~"""'''''''''''--i
GND
roo
5'
CD
C
..
<'
CD
U;
Resistor values show'n are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
::a
CD
SN55189
SN55189A
(')
CD
Supply voltage,
CD
Input voltage
...<'en
Vce
(see Note 11
10
±30
±30
V
V
20
mA
D package
Continuous total dissipation at (or below)
25°C free-air temperature (see Note 2)
950
FK or J package
J package
1375
1025
-55 to 125
o to 70
Storage temperature range
-65 to 150
·-65 to 150
260
Case temperature for 60 seconds: FK package
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds:
J package
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds:
D or N package
4-398
mW
1150
N package
Operating temperature range
NOTES:
UNIT
10
20
Output current
SN75189
SN75189A
300
300
260
°e
°e
°e
°e
°e
1. All voltage values are with respect to network ground terminals.
2. For operation above 25 °C' free-air temperature, refer to the Dissipation Derating Curves in Appendix A. In the J package,
SN551 89 and SN55189A chips are alloy mounted and SN75189 and SN75189A chips are glass mounted. In the N package,
use the 9.2-mW/oe curve for these devices.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN55189, SN55189A, SN75189, SN75189A
QUADRUPLE LINE RECEIVERS
electrical characteristics over operating free-air temperature range.
noted)
TEST
PARAMETER
TEST CONDITIONSt
FIGURE
Positive-going
VT+
threshold voltage
TA -
1
-55°C to 125°C
VT-
threshold voltage
High-level
VOH
output voltage
Low-level
VOL
output voltage
2
input current
Low-level
IlL
2
input current
Short-circuit
lOS
ICC
1
1
High-level
IIH
1
TA
'189A
VI
= O°C
TA -
= 0.75
V,
Input open,
VI
=
VI
=
3 V,
MAX
1
1.3
1.5
Supply current
2
1.9
2.25
MAX
1
1.3
1.5
1.75
1.25
0.75
=
0.35
-55°C to 125°C
2.25
1.0
1.25
1.25
=
=
-0.5 mA
2.6
4
5
2.6
4
5
10H
-0.5 mA
2.6
4
5
2.6
4
5
10L
=
10 mA
0.2
0.45
0.2
0.45
10H
25 V
8.3
0.43
3.6
8.3
0.43
-3.6
3V
V
2.25
V
1.6
3.6
-8.3
0.43
5 V,
1.9
0.65
-3.6
-8.3
0.43
-3
VI
1.6
2.65
1.0
to 70°C
3
output current
TVP*
1.9
1.30
0.75
UNIT
MIN
1.55
VI - 3 V
VI - -25 V
VI -
SN751B9
SN751B9A
TVP*
1.75
TA - 25°C
'189,
SN551B9
SN551B9A
0.6
-55°C to 125°C
TA -
Negative-going
V ± 1 %. (unless otherwise
0.9
TA - 25°C
TA - ooC to 70°C
'189A
= 5
MIN
TA = 25°C
TA - ooc to 70°C
'189
Vee
-3
20
Outputs open
26
20
V
V
mA
mA
Vee
= 5
V.
TEST
Propagation delay time, low-to-high-Ievel output
tpHL
Propagation delay time, high-to-Iow-Ievel Qutut
tTLH
Transition time, low-to-high-Ievel output
tTHL
Transition time, high-to-Iow-Ievel output
(.)
Q)
a:
--.
I I)
Q)
>
';:
s::::
::::i
TEST CONDITIONS
FIGURE
tpLH
'0)
Q)
TA
PARAMETER
.>
C
t All characteristics are measured with the response control terminal open.
tAli typical values are at VCC = 5 V, TA = 25°C.
switching characteristics.
II)
Q)
mA
mA
26
a.
CL
4
CL
CL
CL
TEXAS
=
=
=
=
15 pF, RL
15 pF, RL
15 pF, RL
15 pF, RL
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
=
=
=
=
MIN
TVP
MAX
85
3.9 kO
25
3900
25
50
3.9 kO
120
175
3900
10
20
UNIT
ns
ns
4-399
SN5518~
SN55189A,
SN7518~
SN55179A
QUADRUPLE LINE RECEIVERS
PARAMETER MEASUREMENT INFORMATIONt .
VCC
y,y.+-{
RESPONSE
CONTROL
'~-O-PEN--l-'~"
UNLESS
OTHERWISE ICC
SPECIFIED
•
n+
r
V
IRC
±C \
i
r-VC
":"
'IIOL
~ ~
+VC
':"
FIGURE 1. VT+. VT-. VOH. VOL
r-
3'
CD
C
::::!,
<
...
VI
CD
~
OPEN
~
'!e.
:a
CD
RESPONSE
CONTROL
OPEN
n
CD
<'
CD
...
ICC is tested for all four
receivers simultaneously
en
FIGURE 2. IIH. IlL. ICC
VCC
FIGURE 3. lOS
t Arrows indicate actual direction of current flow. Current into a terminal is' a positive value.
4-400
V10H
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TeXAS 75265
SN55189, SN55189A, SN75189, SN75189A
QUADRUPLE LINE RECEIVERS
PARAMETER MEASUREMENT INFORMATIONt
VCC
RESPONSE
CONTROL
OPEN
(See Note C)
T-=
Cl - 15pF
(See Note B)
-=
TEST CIRCUIT
s 10 ns~ If-
~
If-s 10 ns
I I
I I
Lt;"9~0~%~-------9~0~%':"'"\'Ii·~: INPUT
-
-- -
--- 4 V
50%~10%
10%jf50%
I~~-----------OV
I
-'tPHl-.l
I
I
I
trHl ~
~ VOH
1.5 V
10%
90%
I
I - - -~-- VOL
10%
I
If-
If- trlH~
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zout
~
50 II, tw = 500 ns.
B. CL includes probe and jig capacitances.
C. All diodes are 1 N3064 or equivalent.
FIGURE 4. SWITCHING TIMES
II)
(I)
If-tPlH--..I
I
OUTPUT -----~9::0~%~~
1.5 V
II
...
>
"iii
u
(I)
-...
a:
I I)
(I)
>
"~
C
(I)
c
::i
t Arrows indicate actual direction of current flow. Current into a terminal is a positive value.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-401
SN55189, SN55189A, SN75189, SN75189A
QUADRUPLE LINE RECEIVERS
TYPICAL CHARACTERISTICSt
SN55189. SN75189
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
6
RC- 5kll
Vc - 5 V
VT-
r5"
VT-
VT+
'---
o
CD
RC - 13 kll
Vc - 5V
-1
...
'--
RC- 11kll
Vc - -5 V
00
VT+
VT+ VT-
~
-2
-3
I
RC -
VT+
-
'--'-
o
C
~"
VT-
VCC - 5 V
TA - 25°C
See Figure 1
2
t-3
5
4
VI-Input Voltage-V
-
FIGURE 5
iil
SN55189A.SN75189A
:D
OUTPUT VOLTAGE
. vs
INPUT VOLTAGE
CD
n
CD
<"
6
~
til
I
RC - 5 kll
Vc - 5V
VT-
RC -
VT+
o
-3
-2
-1
RC- 11kll
Vc - -5 V
00
VT-
o
VT+
2
VCC - 5V
TA - 25°C
See Figure 1
VT_
VT+
3
4
VI-Input Voltage-V
FIGURE 6
tOata for free-air temperatures below
4-402
o·e and above 70·e are applicable to SN55189 and SN55189A circuits only.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75265
5
SN55189, SN55189A, SN75189, SN75189A
QUADRUPLE LINE RECEIVERS
TYPICAL CHARACTERISTICS t
INPUT THRESHOLD VOLTAGE
vs
SUPPLY VOLTAGE
2.4
2.2
>
2.0
•
1.8
I
CD
i>
:!i!
~
OJ
!
.t:
.........
"'~ .........
1.4
1.2
SCI. 1.0
0.8
"""-
r-......
"76'9",
"~
.,-
~ ~'"
'1
"1
>
1.6
I
1.4
I
.........
I"--- ~
r--:
1
"~89 JT I
=of 1.2
>
:!i!
"7~t:- :----
0.6
"189A VT+
1.8
b-:'6'9)
1.6
l-
.5
2;0
"189 VT+
a
1.0
1(:.
0.8
i
0.6
.5
0.4
"189A VT-
0.2
o
0.4
-75-50-25 0
25 50 75 100 125150
2345678
TA-Free-Air Temperature-oe
FIGURE 7
tOata for free-air temperatures below
ooe
9
10
Vee-Supply Voltage-V
FIGURE 8
and above 70 0 e are applicable to SN55189 and SN55189A circuits only.
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 655012 • DAl.LAS, TEXAS 75265
4-403
SN5518L SN55189A. SN75189. SN75189A
QUADRUPLE LINE RECEIVERS
TYPICAL CHARACTERISTICS
NOISE REJECTION
NOISE REJECTION
5
1\
1
~
.~E
•..
fl~lI- 3??~
4 \
1\ 1\ 1\ I~g - ~ob ~F
\
>
I
~
C~ I~ 'i~o pF
Cc - 12
I'-...
O
5'
CD
c
10
<'
CD
40
100
400 1000
o
4000 10000
40
10
FIGURE 9
iil
400 1.000 '4000.10000
tw-Pulse Width-ns
tw-Pulse Width-ns
-
100
FIGURE 10
:D
INPUT CURRENT
vs
INPUT VOLTAGE
CD
(')
CD
.
<'
CD
10
en
VCC = 5 V
8 Control open
6
"iii
CJ
Q)
a::
""-
...
1/1
Q)
H ;:;;; high level, L = low level, X = irrelevant
The SN75207, SN75207B, SN75208, and
SN75208B are pin-for-pin replacements for the
SN75107A, SN75107B, SN75108A, and
SN751 08B, respectively, The improved input sensitivity makes them more suitable for MOS memory sense
amplifiers and can result in faster memory cycles, Improved sensitivity also makes them more useful in
line receiver applications by allowing use of longer transmission line lengths, The '207 and '207B each
features a TTL-compatible active-pull-up output, The '208 and '208B each features an open-collector output
that permits wired-AND logic connections with similar output configurations,
>
";:
C
CD
The essential difference between the unsuffixed and "B" versions can be seen in the schematics, Inputprotection diodes are in series with the collectors of the differential-input transistors of the "8" versions,
These diodes are useful in certain "party-line" systems that may have mUltiple Vee + power supplies
and may be operated with some of the Vee + supplies turned off, In such a system, if a supply is turned
off and allowed to go to ground, the equivalent input circuit connected to that supply would be as follows:
t:J
...
INPUT-~
........
INPUT---i~""'-iI4~·Ht!JH""''''''-'*
~-.~~
UNSUFFIXED VERSION
"8" VERSION
This would be a problem in specific systems that might possibly have the transmission lines biased to
some potential greater than 1 ,4 volts,
These devices are characterized for operation from 0 °e to 70 0 e and are available in ceramic dual-in-line
(J) package, plastic small outline (D) package, or plastic dual-in-line (N) package,
PRODUCTION DATA documents contain information
current 8S of publication date. Products conform to
specifications per the tarms of Texas Instruments
::::~~i~ai~:1~1i ~!:~~~i:: :I~O::;:::::'::'~S not
TEXAS . "
INSTRUMENTS
POST OFFiCe BOX 655012 • DALLAS. TEXAS 75265
c:
:::::i
4-405
SN75207, SN75207B, SN75208, SN76208B
DUAL SENSE AMPLIFIERS FOR MOS MEMORIES
OR DUAL HIGH·SENSITIVITY LINE RECEIVERS
logic symbolst
logic diagram (positive logic)
SN75207
S (61
S
lA
lB
lB
lG = - - - ' - -
lG":";;"O------'
2A
2B
2G..:.:!.----,
2G
2A
SN75208
•
S
lB
r
lG
S·
2A
CD
...C
~.
ii1
~
CD
n
2B
lA
2B
2G (81
t These symbols are in accordance with ANSIIIEEE Std 91-1984
and IEC Publication 617-12.
schematic (each receiver)
CD
Vcc l'_4...:.1_ _'_4o---...--_-_~---_'_4o-----_._-___.
~.
1 kn
ii1
1 kn
400 n
4kn
- - - - --,
120n~
1.6kn
.------+
....
I
---I
r- ..... -.r
L_8~~.3__
4.8 kn
(1. 121
lA
INPUTS
)
(71
lB (2. 111
GND
(5. 81 STROBE
L:::==:t=:::::;--i-'3 kn
G
3 kn
(_'3...:.1+-_~o__--~-~--~-_r-----~
VCC-
t---*-_+--,-(6-,-1
STROBE
S
TO OTHER RECEIVER
t R = 1 kn for '207 and '207B, 750 n for '208 and '208B.
NOTES: A. Resistor values shown are nominal.
B. Components shown with dashed lines in the output circuitry are applicable to the '207 and '207B only. Diodes in series with
the collectors of the differential input transistors are short-circuited on '207 and '208.
4-406
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN75207, SN752078, SN75208, SN752088
DUAL SENSE AMPLIFIERS FOR MOS MEMORIES
OR DUAL HIGH·SENSITIVITY LINE RECEIVERS
design characteristics
The '207, '2078, '208, and '2088 line receivers/sense amplifiers are TTL-compatible dual circuits intended
for use in high-speed data-transmission systems or MOS memory systems. They are designed to detect
low-level differential signals in the presence of common-mode noise and variations of temperature and
supplies. Dc specifications reflect worst-case conditions of temperature, supply voltages, and input voltages.
The input common-mode voltage range is ± 3 volts. This is adequate for application in most systems. In
systems with requirements for greater common-mode voltage range, input attenuators may be used to
decrease the noise to an acceptable level at the receiver-input terminals.
The circuits feature individual strobe inputs for each channel and a strobe input common to both channels
for logic versatility. The strobe inputs are tested to guarantee 400 millivolts of dc noise margin when
interfaced with Series 54/74 TTL.
The circuits feature high input impedance and low input currents, which induce very little loading on the
transmission line. This makes these devices especially useful in party-line systems. The excellent input
sensitivity (3 millivolts typical) is particularly important when data is to be detected at the end of a long
transmission line and the amplitude of the data has deteriorated due to cable losses. The circuits are designed
to detect input signals of 10 millivolts (or greater) amplitude and convert the polarity of the signal into
appropriate TTL-compatible output logic levels.
CI)
CJ
Supply voltage, Vee + (see Note 1) ............................................. 7 V
Supply voltage, VCC _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 7 V
Differential input voltage (see Note 2) .......................................... ± 6 V
Common-mode input voltage (see Note 3) .................................... . .. ± 5 V
Strobe input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Continuous total dissipation at (or below) 25 DC free-air temperature: (see Note 4)
D package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 950 mW
J package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11 50 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 DC to 70 DC
Storage temperature range ......................................... - 65 DC to 150 DC
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds:
J package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 300 DC
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds:
D or N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260 DC
1.
2.
3.
4.
...
III
>
"i
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
NOTES:
•
-...
CI)
a:
I II
CI)
>
";:
C
All voltage values, except differential voltages, are with respect to ground terminal.
Differential input voltage values are at the noninverting (A) terminal with respect to the inverting (8) terminal.
Common· mode input voltage is the average of the voltages at the A and B inputs. .
For operation above 25°C free·air temperature, derate linearly to 608 mW at 70 0 attha rate of 7.6 mW/oC for the D package,
e
656 mW at 70 0 e atthe rate of 8.2 mw/oe for the J package. and 736 mW at 70 0 e at the rate of 9.2 mw/oe for the N package.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
CI)
c
::;
4-407
SN75207. SN752078. SN75208. SN752088
DUAL SENSE AMPLIFIERS FOR MOS MEMORIES
OR DUAL HIGH·SENSITIVITY LINE RECEIVERS
recommended operating conditions (see Note 5)
MIN
Supply voltage, Vcc +
4.75
Supply voltage, VCCHigh-level differential input voltage
-4.75
VIDH (see Note 6)
Low-level differential input voltage, VIOL
Common-mode input voltage, VIC (see Notes 6 and 7)
Input voltage, any differential input to ground Isee Note 6)
UNIT
V
V
5
V
-5 t
-0.01
V
-3
-5 t
3
3
5.5
0.8
-16
70
V
2
Low-level input voltage at strobe inputs, VILIS)
0
Low-level output current, IOL
•
MAX
5.25
5
-5 -5.25
0.01
High-level input voltage at strobe inputs, VIH(S)
Operating free-air temperature. T A
NOM
0
V
V
V
rnA
°c
t The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for logiC
voltage levels only.
NOTES: 5. When using only one channel of the line receiver, the strobe G of the unused channel should be grounded and at least one
r-
S'
...r
..
CD
of the differential inputs of the unused receiver should be terminated at some voltage between ,-3 V and 3 V.
6. The recommended combinations of input voltages fall within the shaded area of the figure shown.
7. The common-mode voltage may be as low as - 4 V provided that the more positive of the two inputs is not more negative
than -3 V.
C
RECOMMENDED COMBINATIONS
OF INPUT VOLTAGES
CD
en
~
CD
(')
>
.,I
g>
CD
15
CD
."
C
..
c::en
>
"e
CI
6
.~
I
:;
c.
.5
023
Input-B-to-Ground Voltage-V
4-408
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN75207, SN752078, SN75208, SN752088
DUAL SENSE AMPLIFIERS FOR MOS MEMORIES
OR DUAL HIGH-SENSITIVITY LINE RECEIVERS
electrical characteristics over recommended free-air temperature range (unless otherwise noted)
PARAMETER
High-level
IIH
IlL
~
B
input current
Low-level
VCC±
~ VCC±
B
input current
into lG or 2G
± 5_25 V
VID
± 5_25 V
VCC±
=
=
±5_25 V, VIH(SI
±5.25 V, VIH(SI
= 2.4 V
= ± 5.25 V
VCC±
=
±5.25 V, VIL(SI
= 0.4 V
VCC±
input current
=
VID
VIO
=
High-level
IIH
'207, '207B
MIN Typt MAX
TEST CONDITIONS
VIO
=5V
= -5 V
= -5 V
=5V
30
30
'208, '208B
MIN TYpt MAX
UNIT
75
30
75
75
30
-10
75
-10
-10
-10
40
40
p.A
1
1
mA
-1.6
-1.6
mA
80
80
p.A
2
2
mA
-3.2
-3.2
mA
p.A
p.A
Low-level
IlL
input current
into lG or 2G
High-level input
IIH
current into S
= ±5.25 V, VIH(S) = 2.4 V
VCC± - ±5.25 V, VIH(SI - ± 5.25 V
VCC±
Low-level input
IlL
current into S
High-level
VOH
output voltage
Low-level
VOL
output voltage
VCC±
High-level
IOH
output current
output current t
Supply current from
ICCH + VCC +, outputs high
VCC -, outputs high
= 0.4 V
= 0.8 V, VIOH = 10 mV,
- 3 V to 3 V
= 2 V, VIOL = -10mV,
- 3 V to 3 V
±4.75 V, VOH
VCC±
=
±5.25 V
VCC±
=
±5.25 V, TA
= 25°C
VCC±
=
±5.25 V, TA
= 25°C
II
..
II)
2.4
V
0.4
0.4
V
250
p.A
CD
>
-iii
(,)
-..
CD
= 5.25 V
=
a::
I I)
-18
-70
18
CD
mA
30
18
30
mA
-8.4 -15
-8.4
15
mA
>
-;::
C
CD
Supply current from
ICCH-
±5.25 V, VIL(SI
VCC±
Short-circuit
lOS
=
VCC± = ±4.75 V, VIL(SI
VIC =
IOH = -400 p.A,
VCC± = ±4.75 V, VIH(SI
IOL = 16 mA,
VIC =
t All typical values are at VCC + = 5 V, VCC _ = - 5 V, TA
t Not more than one output should be shorted at a time.
c::
:::::i
= 25°C.
switching characteristics. VCC+ - 5 V. VCC- '" -5 V. TA '" 25°C
PARAMETER
tpLH(O)
tpHL(OI
tPLH(S)
tpHLISI
TEST CONDITIONS
'207, '2078
MIN
MAX
'208, '208B
MIN
. MAX
UNIT
Propagation dalay time, low-to-high-Ievel
output, from differential inputs A and B
35
35
ns
20
20
ns
17
17
ns
17
17
ns
Propagation delay time, high-to-Iow-Ievel
output, from differential inputs A and B
Propagation delay time, low-to-high-Ievel
RL
= 470 Il,
CL = 15 pF,
See Figure 1
output, from strobe input G or 5
Propagation delay time, high-to-Iow-Ievel
output, from strobe input G or S
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-409
SN75207, SN752078, SN75208, SN752088
DUAL SENSE AMPLIFIERS FOR MOS MEMORIES
OR DUAL HIGH·SENSITIVITY LINE RECEIVERS
PARAMETER MEASUREMENT INFORMATION
VCC-
DIFFERENTIAL
INPUT
r- - - - - _1_ - - - --.,
1A I
OUTPUT
I
~~----~~I-i"
11y
7
•..
470
(S88 Not8 01
n
"'--"',""","""--4H~OUTPUT
!::
:::I
CD
CL]
15 pF
7(S" Note CI
STROBE
INPUT
(S.. Note BI
C
~'
U;
~
n
CD
<'
CD
TEST CIRCUIT
..
f/-------------------------40mV
rn
INPUT
B
10 mV
10mV
oV ----II
I---of
j..-t 1----J
W
STROBE
INPUT
G or S
M----tw2---~
I
I
3v--------+I------+I---------1/
I
I
I
---t
3V
1.5 V
------.".~I - - tPHl(SI -.t
IfIf-
tPHl(DI-..
VOH----_
OUTPUT
Y
1-(_ _
,.,1.5
0 V
1.5X --VOH
V
Y"\....VOL
VOLTAGE WAVEFORMS
NOTES: A. The pulse generators have the following characteristics: Zout = 50 n, tr S 5 ns, tf S 5 ns, tw1 = 500 ns with PRR S 1 MHz,
tw2 = 1 ~s with PRR s 500 kHz.
B. Strobe input pulse is applied to Strobe 1 G when inputs 1A-1 B are being tested, to Strobe S when inputs 1 A-1 B or 2A-2B
are being tested, and to Strobe 2G when inputs 2A-2B are being tested.
C. CL includes probe and jig capacitance.
D. All diodes are 1N916.
4·410
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN75207, SN752078, SN75208,SN752088
DUAL SENSE AMPLIFIERS FOR MOS MEMORIES
OR DUAL HIGH,SENSITIVITY LINE RECEIVERS
TYPICAL APPLICATION DATA
STROBES
r---- ----,
1000
INPUT
FROM
or
MOS MEMORY
OUTPUT
TO
TTL
I
TO
OUMMY
LINE
SN75452B
1000
V r.,
ADJUSTMENT
I
1/2 '207, '207B
I
or
I
IL ________
1/2 '208, '2088
..JI
a
'~------~V~------JI
'--v---J '----v---'
DRIVE
I
I
r-----~~~I--i'~~~,
SN75361A
TTL
I
I
SENSE
MEMORY
FIGURE 2. MOS MEMORY SENSE AMPLIFIER
~
CD
RECEIVER 1
'j
v
v
STROBES
tRANSMISSION LINE HAVING
CHARACTERISTIC IMPEDANCE 20
STROBES
>
RECEIVER 4
RECEIVER 2
STROBES
RT
U
CD
a:
~
CD
>
';:
Q
LOCATION 2
DRIVER 1
DRIVER 3
A
DRIVER 4
A
DATA INPUT B
B
C
CD
c:
:::::i
C
INHIBIT D
D
LOCATION 1
LOCATION 3
LOCATION 4
Receivers are '207, '2078, or 208', or '2088; drivers are SN55109A, SN75109A, SN55110A, SN75110A, or SN75112.
FIGURE 3. DATA-BUS OR PARTY-LINE SYSTEM
PRECAUTIONS:
When only one receiver in a package is being
used, at least one of the differential inputs of the
unused receiver should be terminated at some
voltage between - 3 volts and 3 volts,
preferably at ground. Failure to do so will cause
improper operation of the unit being used
because of common bias circuitry for the current
sources of the two receivers. Strobe G of the
unused channel should be grounded.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
4-411
•
4-412
ADVANCE
INFORMATION
SN75ALS126
QUADRUPLE LINE DRIVER
02299, FEBRUARY 1986-REVISEO OCTOBER 1986
•
SN75ALS126 ... D, J, OR N PACKAGE
Meets IBM 360/370 I/O Interface
Specification GA22-6974-3 (Also see
SN75ALS130)
(TOP VIEWI
lY
1i=
lA
1,2G
2A
2F
2Y
GND
Vee
4Y
4F
4A
3AG
3A
3F
3Y
•
Minimum Output Voltage of 3.11 V at
10H = -60 mA
•
Fault Flag Circuit Output Signals Driver
Output Fault
•
Fault-Detection Current Limit Circuit
Minimizes Power Dissipation During a Fault
Condition
•
Advanced Low-Power Schottky Circuitry
•
Dual Common Enable
INPUTS
•
Individual Fault Flags
G
A
Y
F
L
X
L
H
H
H
H
H
H
H
S
L
•
FUNCTION TABLE
Designed to be an Improved Replacement
for the MC3481
H = high level, L
X = irrelevant, S
ground
description
a.
OUTPUTS
=
=
I/)
CI)
>
"iii
low level,
shorted to
(.)
CI)
The SN75ALS 126 quadruple line driver is
designed to meet the IBM360/370 I/O
specifications GA22-6974-3, The output voltage
is 3,11 volts minimum (at 10H = - 59,3 milliamperes) over the recommended ranges of supply voltage
(4.5 volts to 5.5 volts) and temperature (OOe to 70°C), Driver outputs use a fault-detection current-limit
circuit to allow high drive current but still minimize power dissipation when the output is shorted to ground,
The SN75ALS126 is compatible with standard TTL logic and supply voltages,
a:
-.
I/)
.
CI)
>
".:
Q
CI)
r::
::i
The SN75ALS126 employs the IMPACT'" process to achieve fast switching speeds and low power
dissipation. Fault-flag circuitry is designed to sense and signal a line short on any Y line, Upon detecting
an output fault condition, the fault-flag circuit forces the driver output into a low state and signals a fault
condition by causing the fault-flag output to go low,
The SN75ALS 126 will drive a 50-ohm load as required in the IBM GA22-6974-3 specification or a 90-ohm
load as used in many I/O systems. Optimum performance can be achieved when the device is used with
either the SN75125, SN75127, SN75128. or SN75129 line receivers.
The SN75ALS126 is characterized for operation from OOC to 70°C.
z
o
j::
o
lA (31
lEN2
(21
IF
lA
1.2G
Gl
20
(11
3EN4
(61
&1>
(31
(41
(11
F
1V
lY
(61
2A
2F
(51
(71
21'
2Y
G3
2A (51
•
4~
(71
(101
3A (111
(91
(141
2Y
(101
3F
3A (111
3AG (121
3Y
(91
(151
3Y
4F
(141
4A (131
31'
41'
4Y
4A (131
(151
t This symbol is in accordance with ANSIIIEEE Std 91-1984 and
4Y
lEe Publication 617-12.
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
V C C - - - -. .~
Req
TYPICAL OF ALL Y OUTPUTS
-11..----....-
TYPICAL OF F OUTPUTS
....- -....- - v C C
VCC
20 kll
NOM
r - - i - Y OUTPUT
l>
C
<
l>
:2
0
F
OUTPUT
INPUT
....~.-....--GND
GND
m
-
A Inputs: Req - 20 kll NOM
G Inputs: Req - 10 kll NOM
e--.......-GND
:2
."
0
::D
s::
l>
::!
0
:2
4-414
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855012 • DAl.lAS. TEXAS 75266
ADVANCE
INFORMATION
SN75ALS126
QUADRUPLE LINE DRIVER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc ........................................................ , 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 1):
o package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950 mW
J package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 50 mW
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: 0, N package . . . . . . . . .. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............ 300°C
NOTE 1: For operation above 25°C free-sir temperature, derate the D package to 608 mW at Jooe at the rate of 7.6 mW/oC, the J package
to 656 rnW at 70°C at the rate of 8.2 rnw/oe, and the N package to 736 rnW at 70°C at the rate of 9.2 mw/oe.
recommended operating conditions
Supply voltage, Vee
MIN
NOM
MAX
UNIT
4.5
5
5.95
V
2
High-level input voltage, VIH
0.8
Low-level input voltage, VIL
High-level output current, IOH
0
Operating free-air temperature, T A
a
~
V
II)
V
"iii
-59.3
rnA
70
°e
>
(J
II)
a::
-t il
"-
II)
>
".:
C
II)
c:
::i
2:
o
i=
«
:2E
a:
ou.
-w
Z
(.)
2:
~
«
C
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-415
SN75ALS126
QUADRUPLE LINE DRIVER
ADVANCE
INFORMATION
electrical characteristics over recommended ranges of_supply voltage and operating free-air temperature
VIK
PARAMETER
Input clamp voltage
TEST CONDITIONS
A,G
Y
VOH
High-level output voltage
Y
F
Y
VOL
•
Low-level output voltage
y
10(offl
II
Input current
IIH
High-level input current
IlL
Low-level input current
lOS
Short-circuit output
Supply current, all
leeH
leeL
outputs high
Supply current,
Y outputs low
10H - -59.3 mA
VIH = 2 V
Vee - 5.25 V, 10H - -41 mA
VIH = 2 V
Vee = 4.5 V, 10H = -400 ~A
VIH = 2 V
Vee - 5.5 V, 10L - -240p.A,
VIL = 0.8 V
Vee - 5.95 V, 10L - -1 mA,
Vee - 4.5 V,
Y
Y
Vee - 0,
A
""""G
A
Vee
=
4.5 V,
10L
=
8 mA,
VIL - 0,
VIL = 0,
VIH
=
=
4.5 V,
VIH
=
2.7 V
Vee
=
5.95 V, VIL
=
0.4 V
--4F
Vee
=
5.5 V,
=
0
-4F
Vee
=
5.95 V, Vb
G
Va
MAX
-1.5
UNIT
V
3.11
3.9
V
2.5
0.15
0.15
Y at 0 V
0.5
100
Va - 3.11 V
=
Va
200
100
400
3.11 V
5.5 V
Vee
G
2......
MIN
-18 mA
VIL = 0.8 V
Vee = 4.5 V,
Vee - 4.5 V,
F
Off-state output current
=
II
=0
-15
20
80
250
-1000
-5
-100
-15
-5
-110
Vee = 5.5 V, No load
Vee - 5.95 V, No load
Vee = 5.5 V, No load
Vee - 5.95 V, No load
V
p.A
p.A
p.A
p.A
mA
25
27
mA
45
47
mA
switching characteristics over recommended operating free-air temperature range
»c
~
2
(")
-m
tpLH
tpHL
tpLH
tpHL
tpLH
2
tpHL
o
tpLH
:!:
tpHL
."
::D
~
PARAMETER
Propagation delay time,
low-to-high-Ievel output
Propagation delay time,
high-to-Iow-Ievel output
FROM
TO
Vee
A
Y
Ratio of propagation
delay times
Propagation delay time,
low-to-high-Ievel output
Propagation delay time,
high-to-Iow-Ievel output
Propagation delay time,
low-to-high-Ievel output
Propagation delay time,
high-to-Iow-Ievel output
TEST CONDITIONS
RL
=
= 4.5
V to 5.5 V,
eL = 50 pF,
50 D,
VH(refl = 3.11 V,
See Figures 1 and 2
0.3
Vee - 5.25 V to 5.95 V,
A
A
Y
F
RL
=
90D,
eL
=
50 pF,
VH(refl = 3.9 V
See Figures 1 and 2
RL = 2 kD,
Vee = 5 V,
eL = 15 pF,
See Figures 1 and 2
o
2
4-416
MIN
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76266
MAX
UNIT
30
ns
28
ns
3
34
ns
34
ns
45
ns
75
ns
SN15ALS126
QUADRUPLE LINE DRIVER
ADVANCE
INFORMATION
PARAMETER MEASUREMENT INFORMATION
4V
A INPUT _ _ _ _JI 10%
tw ---/_"';"' _ _...J
!...
NORMAL
OPERATION
~ tpLH
-+j
:I \l
tpLH - .
I
1
1
VHlrefl :
Y OUTPUT _ _ _ _......loJ.
1 _ 0.5 V
I
I
I
I
I-
tpHL
-I ~ tpLH
U
F OUTPUT - - - - - - - - . . . , I
1.3 V
I
r-------
VOH
til
DRIVER
1._3
V _
-
II
...
]
g~~~~ION
~
'Q)
U
-VOL
NOTE A: The input pulse is supplied by a generator having the following characteristics: PRR
tf S 6 ns, Zout = 50 0.
=
-...
Q)
a::
1 MHz, duty cycle
=
50%, tr S 6 ns,
t il
Q)
>
';':
FIGURE 1. INPUT AND OUTPUT VOLTAGE WAVEFORMS
Q
Q)
c
::::;
5V
Y OUTPUT --~~-~~-----,
2 kO
F OUTPUT
- . - -.......-
. .-I~.--.
2
o
t=
NOTE A: CL includes probe and stray capacitance.
FIGURE 2. SWITCHING CHARACTERISTICS LOAD CIRCUITS
«
~
a:
oLL
2
w
(.)
2
«
>
c
«
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-417
4-418
ADVANCE
INFORMATION
SN75ALS130
QUADRUPLE LINE DRIVER
02299, FEBRUARY 1986
•
D. J. OR N PACKAGE
Meets IBM 360/370 I/O Interface
Specification GA22-6974-3 (Also see
SN75ALS126)
•
Minimum Output Voltage of 3.11 V at
10H - -60 mA
•
Fault-Flag Circuit Output Signals Driver
Output Fault
•
Fault-Detection Current Limit Circuit
Minimizes Power Dissipation During a Fault
Condition
•
Advanced Low-Power Schottky Circuitry
•
Common Enable and Common Fault Flag
•
Designed to be an Improved Replacement
for the MC3485
(TOP VIEWI
4V
4W
4A
F
3A
3W
3V
FUNCTION TABLE
INPUTS
Gt
A
L
X
H
H
description
The SN75ALS 130 quadruple line driver is
designed to meet the IBM 360/370 I/O
specifications GA22-6974-3. The output voltage
is 3.11 volts minimum (at 10H = - 59.3
milliamperes) over the recommended ranges of
supply voltage (4.5 volts to 5.5 volts) and
temperature (OOC to 70°C). Driver outputs use
a fault-detection current limit circuit to allow high
drive current but still minimize power dissipation
when the output is shorted to ground. The
SN75ALS130 is compatible with standard TTL
logic and supply voltages.
Vee
lV
lW
lA
G
2A
2W
2V
GND
H
X
X
L
H
H
Y
L
L
OUTPUTS
j:t
W
H
H
H
H
H
H
L
S
L
H
II
~
CD
>
'G)
= high level. L = low level,
= irrelevant, S = shorted to
(,)
CD
a::
ground
t G and j: are common to the four
drivers. If any of the four Y
outputs is shorted, the Fault·
Flag will respond.
~
CD
>
';:
C
CD
c:
::::;
The SN75ALS130 employs the IMPACT'" process to achieve fast switching' speeds and low power
dissipation. Fault-flag circuitry is designed to sense and signal a line short on any Y line. Upon detecting
an output fault condition. the fault-flag circuit forces the driver output into the off (low) state and signals
a fault condition by causing the fault-flag output to go low.
The SN75ALS130 will drive a 50-ohm load as required in the IBM GA22-6974-3 specification or a 90-ohm
load as used in many 1/0 systems. Optimum performance can be achieved when the device is used with
either the SN75125, SN75127, SN75128, or SN75129 line receivers.
The SN75ALS130 is characterized for operation from OOC to 70°C.
z
i=
«
:E
o
a:
oLL
Z
w
(.)
Z
~
c
«
IMPACT is a trademark of Texas Instruments Incorporated
ADVANCE INFORMATION doc••o.tI ..ltaln
==:;=a~r::..~:"c::=r.:
~Ita .nd ather .poeilicoli... oro .ub/lel ta ....go
without .atice.
Copyright @ '986, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75265
4-419
SN75ALS130
QUADRUPLE LINE DRIVER
ADVANCE
INFORMATION
logic symbol t
logic diagram (positive logic)
G 14)
G 14)
1A 13)
112)
/""_,..:..:11,:::6)
F
vee
-........+1:..:,:1)1Y
~--~~~-~
L-_Do--f--,,12::.:) 1W
1A 13)
2A 15)
-........+1~7)2V
2A 15)
~_+-'1,:::6) 2W
3A 111)
!:
::s
3A 111)
CD
-........+-'1.::!9) 3V
L-----4+-_---l
C
~-~11;.::;O)3W
::::!.
.
<
CD
4A 113)
(II
:a
4A 113)
115) 4V
CD
C')
CD
.cr
CD
(II
~_--,-,11...;.;4) 4W
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12 .
l>
C
<
l>
2
o
m
-2
."
o
::rJ
~
~
o
2
4-420
TEXAS . " .
INSTRUMENTS
POST OFFICE BOX
65~012
• DALLAS. TeXAS 75285
SN75ALS130
QUADRUPLE LINE DRIVER
ADVANCE
INFORMATION
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL Y OUTPUTS
-~~---.....--VCC
V C C · - - - - -.....- Req
20 kll NOM
...---t-- Y OUTPUT
INPUT-.................
GND-.....--~~~---
- - _........-
...-GND
A Inputs: Req - 20 kll NOM
G Inputs: Req - 10 kIl NOM
II
...
III
TYPICAL OF AU W OUTPUTS
TYPICAL OF F OUTPUT
-
....- - - - - - - VCC
~
"iii
to)
CD
a::
...CD
I II
FOUTPUT
>
"ii:
C
CD
C
W OUTPUT
::;
- - -.........~~GND
...........--GND
z
i=
o
'a;
(.)
CD
a:
PARAMETER MEASUREMENT INFORMATION
~
CD
>
't:
4.0 V
C
A INPUT
CD
c:
10%
::::i
NORMAL
OPERATION
Y OUTPUT
z
o
i=
c
-i
OUTPUT
L
H
L
X
L
X
0
L
H
X
H
X
Z
u
G)
-..
a::
I I)
G)
>
low level, X
=
-i:
irrelevant,
Q
Z = high-impedance state.
G)
t This is the high-impedance state of a normal 3-stete
output modified by the internal resistors to Vee and
ground.
c
:::i
z
o
~
<
::!.
An active turn-off feature has been incorporated
into the bus-terminating resistors so that the
device exhibits a high impedance to the bus
when Vee = 0, When combined with the
SN75ALS161 or SN75ALS162 management
bus transceiver, the pair provides the complete
16-wire interface for the IEEE 488 bus.
a:
oLL
Z
W
The SN75ALS160 is manufactured in a 20-pin
package and is characterized for operation from
ooe to 70 oe.
o
Z
<
>
Q
<
Copyright @ 1986, Texas Instruments Incorporated
ADVANCE INFORMATION documents contain
~o:;:r::rO:;h= .sr::=~::=~':P.tT!
~oto Ind other opacifications oro ..bjact ta chlngo
without notice.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
4-425
SN75ALS160
OCTAL GENERAL"PURPOSE INTERFACE BUS TRANSCEIVER
ADVANCE
INFORMATION
logic diagram (positive logic)
logic symbol t
02 1181
B3
•
t=:~7B4
B5
03 (171
B6
B7-
04 (161
TERMINAL
B8
!::
=
CD
...C
CD
...<"
GPIB
05 1151
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
'il Designates 3-state outputs.
~ Designates passive-pul!up outputs.
110
PORTS
06 (141
1(1~~31~-h-6==;1
07":';
!!!.
:a
CD
n
08 1121
CD
<"
CD
...
(4
schematics of inputs and outputs
EQUIVALENT OF ALL CONTROL INPUTS
VCC--------~--------
»
c
~
2
EQUIVALENT OF ALL INPUTfOUTPUT PORTS
9krl
NOM
Raq
10kn
NOM
INPUT
(')
m
2
."
o
GNO - -......- - - -....__- -_ _
::0
3:
»
-I
6
Driver output Req = 30 II NOM
Receiver output Req = 110 II NOM
Circuit inside dashed lines is on the driver outputs only.
2
4-426
TEXAS •
INSTRUMENTS
POST OFFICE BOX 866012 • OAL!-AS. TEXAS 75286
SN75ALS160
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
ADVANCE
INFORMATION
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage. VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Low-level driver output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 mA
Continuous total dissipation at (or below) 25 DC free-air temperature (see Note 2):
OW package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1125 mW
J package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1375 mW
N package ........................................................ 11 50 mW
Operating free-air temperature range ...................................... ODC to 70 DC
Storage temperature range ......................................... - 65 DC to 1 50 DC
Lead temperature 1.6 mm (1/16 inch) from the case for 60 seconds: J package .......... 300 DC
Lead temperature 1.6 mm (1/16 inch) from the case for 10 seconds: OW or N package .... 260 DC
NOTES: 1. All voltage values are with respect to network ground terminal.
2. For operation above 25·C free-air temperature. derate the OW package to 720 mW at 70·C at the rate of 9.0 mW/ ·C. derate
the J package to 880 mW at 70·C at the rate of 11.0 mW/·C. and derate the N package to 736 mW at 70·C at the rate
of 9.2
•
•
mw/·e.
...
II)
recommended operating conditions
II)
MIN
Supply voltage. Vee
4.75
High-level input voltage. VIH
low-level input voltage. Vil
High-level output current. IOH
low-level output current. IOl
NOM
5
MAX
5.25
2
Operating free· air temperature. TA
V
0.8
-5.2
-800
Bus ports with pullups active
Terminal ports
Bus ports
Terminal ports
0
UNIT
V
V
mA
>
'i
i
-...
a:
I I)
II)
~A
>
48
16
mA
';:
C
70
·e
II)
c:
::;
z
i=
o
C
'G)
CJ
Q)
a:
--
25°C.
I /)
~
Q)
>
-;::
C
Q)
c:
:.J
;2
o
i=
«
~
a:::
o
LL
;2
W
(.)
;2
«
c>
«
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-429
SN75ALS160
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
ADVANCE
INFORMATION
PARAMETER MEASUREMENT INFORMATION
20011
DINPUT f.5V
X.5:---
3V
~.- - - 0 V
- - - " ..
IPL~
tpH.L~
BDU~UT 1'~2'-2V--------~--~,\:---VOH
~VOH
48011
VOLTAGE WAVEFORMS
TEST CIRCUIT
FIGURE 1. TERMINAL·TO-BUS PROPAGATION DELAY TIMES
r-
5-
CD
BINPUT f.5V
\.:---3V
---'l"
C
:::!.
<
,.
tpLH~
~
OV
tpHL~
: r--------~_1- - -VOH
se.
DOU~UT
::D
1.5V
CD
n
CD
~.
;
VOLTAGE WAVEFORMS
TEST CIRCUIT
FIGURE 2. BUS-TO-TERMINAL PROPAGATION DELAY TIMES
~SV
l>
c
~
'PZH---t
:2
480n
nm
51 toGND
:2
0V
0,8 V
3.5 V
1.0V
S2CLOSED
o::D
s::
VOLTAGE WAVEFORMS
TEST CIRCUIT
l>
:2
14tpHZ--.I
I, r------------t-T
BOU~UT
."
:::!
BOUTPUTI
SI to3V I
S20PEN ,
-
o
\.5~_---3V
S2
FIGURE 3. TE-TO-BUS ENABLE AND DISABLE TIMES
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR '" 1 MHz, 50% duty cycle, t, '" 6 ns,
tf ",6 ns, Zout = 50 Il.
B. CL includes probe and jig capacitance.
4-430
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
ADVANCE
INFORMATION
SN75ALS160
OCTAL GENERAL"PURPOSE INTERFACE BUS TRANSCEIVER
PARAMETER MEASUREMENT INFORMATION
-Jt-:.___
\._
1\\..5_v_____
TE INPUT
tPZH--+j
DOUTPUTI
Slto3V
S20PEN
tpZL
I
I
~
tpHZ~
I
,....
-gO%---VOH
1.5V
I
I
I
OV
--t
tpLZ-.t
4V
o OUTPUT
S1 to GND
3V
-0 V
LOV
82 CLOSED
TEST CIRCUIT
a
VOLTAGE WAVEFORMS
FIGURE 4. TE-TO·TERMINAL ENABLE AND DISABLE TIMES
...
III
Q)
PE INPUT
>-....:..:::-....- -....
I,
--..Ii
-OUTPUT
t
on
\~ -
1.5V
--
i\5V
>
"a;
3V
()
Q)
OV
a:
--...
----i '-"'i.~ 14-_-----~~""""'\iL90%--VOH
I II
:
Q)
>
";:
C
VOL'" O.BV
Q)
c:
:::J
TEST CIRCUIT
VOLTAGE WAVEFORMS
FIGURE 5. PE-TO-BUS PUlLUP ENABLE AND DISABLE TIMES
NOTES: A. The input pulse is supplied by a generator having the following characteristics: Pi=1R ,; 1 MHz, 50% duty cycle, tr ,; 6 ns,
tf ,; 6 ns, Zout ~ 50 n.
B. CL includes probe and jig capacitance.
2:
o
-
J0-
e:(
~
a:
o
LL
Z
W
U
Z
e:(
>
C
e:(
TEXAS . "
INSTRUMENTS
PQSTOFFICE BOX 655012. DALl.AS, TEXAS 75265
4-431
SN75ALS160
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
ADVANCE
INFORMATION
TYPICAL CHARACTERISTICS
TERMINAL HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW·LEVEL OUTPUT CURRENT
4.0
>
3.5
...go
3.0
I
"0
>
;
•
.9::J
o
;;
I
........
I
>
8,
"0
>
...
e
'\
2.0
::J
"'"
1.5
1.0
0.5
o
-5
J
.I.
VCC = 5 V
0.5 I---TA = 25°C
~
'\
2.5
o
>I
~
:J:
o
0.6
I
VCC = 5 V
TA=25°C-
>
"
~
J:'"
...
TERMINAL LOW-LEVEL OUTPUT VOLTAGE
vs
-10 -15 -20
0
;;
0.4
0.3
..."
~
...I
0.2
0
0.1
>
/
0
...
~
""" l\.
>
o
-25 -30 -35 -40
/
o
IOH-High-Level Output Current-mA
V
/
10
vs
BUS INPUT VOLTAGE
4.0
VCC = 5 V
No load
TA = 25°C
3.5
C
<
l>
2
nm
-
2
-n
0
::D
s:
l>
8,
~
3.0
2.5
"0
>...
::J
.9::J
0
I
0
>
2.0
VT-
VT+
1.5
1.0
0.5
o
o
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VI-Input Voltage-V
FIGURE 8
::::!
0
2
4·432
30
FIGURE 7
TERMINAL OUTPUT VOLTAGE
l>
20
40
V
50
IOL -Low·Level Output Current-mA
FIGURE 6
>I
,/
V
/'
TEXAS •
INSTRUMENTS
POSi OFFice BOX 655012 • DALLAS. TEXAS 75265
60
ADVANCE
INFORMATION
SN75ALS160
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
TYPICAL CHARACTERISTICS
BUS HIGH·LEVEL OUTPUT VOLTAGE
vs
BUS HIGH-LEVEL OUTPUT CURRENT
BUS LOW-LEVEL OUTPUT CURRENT
4
8.
~
~
3
>...
a-"
0"
a;
,.
..
0.6
VCCI~ 5 V
>I
0
BUS LOW·LEVEL OUTPUT VOLTAGE
vs
2
TA = 25°C
I~
'"
i'"
I
:J:
0
>
-10
..
!
0.5
>...
0.4
./
-20
"
0
a;
..,.
V
"-
-30
,,/
0.3
..J
~
~
0
..J
~
-40
,/
V
II
...
III
0.1
(I)
>
-iii
O~~
-50
./
/
I
0
/
0.2
..J
>
,,/
./
a-"
~
i:.
o
VCC =5V
TA = 25°C
0
..J
o
>I
o
-60
IOH-High-Level Output Current-rnA
20
30
40
50 60
70 80
90 100
IOL -Low-Level Output Current-rnA
I II
(I)
>
';:
o
BUSCURRENT
BUS OUTPUT VOLTAGE
(I)
vs
vs
TERMINAL INPUT VOLTAGE
BUS VOLTAGE
c:
:.:J
4
VCC = 5 V
No load
TA = 25°C
..'"
2
3
z
o
~
0
>...
a-"
--...
I%:
FIGURE 10
FIGURE 9
>I
to)
(I)
__~-L~__J-~__~-L__~~
10
~
2
«
:;
"
0
I
0
a:
,
>
o
u.
THE UNSHADED
-5 """I--I--l'-+-N AREA CONFORMS TO
o~~
0.9
__
1.0
~
__
1.1
~
__
1.2
~
__+-__
1.3
'.4
~~
1.5
__~
1.6
-6 ~H-t-+~ PARAGRAPH 3.5.3 OF
IEEE STANDARD 488-1978
1.7
-1
o
2
3
4
VI!O(bus)-Bus Voltage-V
VI-Input Voltage-V
FIGURE 12
FIGURE 11
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5
Z
6
w
(.)
z
«
c>
«
4-433
r-
S'
CD
...C
<'
CD
...
(II
~
CD
('j
CD
<'
...
CD
(II
4-434
SN75ALS161
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
ADVANCE
INFORMATION
02618, JUNE 1986
MEETS IEEE STANDARD 488-1978 (GPIB)
•
8-Channel Bidirectional Transceiver
•
Designed to Implement Control Bus
Interface
OW, J, OR N PACKAGE
(TOP VIEW)
TE
REN
•
Designed for Single Controller
•
High-Speed Advanced Low-Power Schottky
Circuitry
•
•
IFC
Low Power Dissipation ... 46 mW Max per
Channel
High-Impedance P-N-P Inputs
•
Receiver Hysteresis ... 650 mV Typ
•
Bus-Terminating Resistors Provided on
Driver Outputs
•
NRFD
I/O
PORTS
Fast Propagation Times . . . 20 ns Max
•
•
NDAC
GPIB
VCC
REN
IFC
NDAC
NRFD
TERMINAL
DAV
I/O PORTS
EOI
EOI
ATN
ATN
SRO
GND
DC
SRO
II
CHANNEL IDENTIFICATION TABLE
IDENTITY
NAME
No Loading of Bus When Device is Powered
Down (VCC - 0)
Power-Up/Power-Down Protection
(Glitch-Free)
description
DC
Direction Control
TE
Talk Enable
~
Attention
SRQ
Service Request
Bus
REN
Remote Enable
Management
IFC
Interface Clear
EOI
End or Identify
Data Valid
NDAC
Not Data Accepted
NRFD
Not Ready for Data
1/1
Q)
Control
ATN
DAV
The SN75ALS 161 eight-channel generalpurpose interface bus transceiver is a monolithic,
high-speed, Advanced Low-Power Schottky
process device designed to provide the busmanagement and data-transfer signals between
operating units of a single controller
instrumentation system. When combined with
the SN75ALS 160 octal bus transceiver, the
SN75ALS161 provides the complete 16-wire
interface for the IEEE 488 bus.
CLASS
>
-Qj
(J
Q)
ex:
1/1
~
Q)
>
-;:
Data
C
Transfer
Q)
c:
:::i
2
o
-t-
The SN75ALS161 features eight driver-receiver
pairs connected in a front-to-back configuration
to form input/output (I/O) ports at both the bus
and terminal sides. The direction of data through
these driver-receiver pairs is determined by the
DC and TE enable signals.
«
2
a:
o
The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a
high impedance to the bus when Vee = O. The drivers are designed to handle loads up to 48 milliamperes
of sink current. Each receiver features p-n-p transistor inputs for high input impedance and a guaranteed
hysteresis of 400 millivolts minimum for increased noise immunity. All receivers have 3-state outputs to
present a high impedance to the terminal when disabled,
The SN75ALS 161 is manufactured in a 20-pin package and is characterized for operation from 0 °e to 70 °e.
ADVANCE INFORMATION documents contain
information on new products in the samplin~ or
preproduction phase of development. Charactenstic
data and other specifications are subject to change
without notice.
LL
2
w
(.)
2
«
>
c
«
Copyright © 1986, Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
4-435
SN75ALS161
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
logic symbol t
DC (11 )
TEll)
AOVANCE
INFORMATION
logic diagram (positive logic)
EN1/G4
EN2/G5
EN3
ATNI13
1\7
E01(14 )
1
.rr
I>
3\7
ATN
1
.rr
SRol12
I>
1 ~
REN (19 )
I>
1\7
1
.rr
IFC l1S1
I>
1\7
.rr
II
r-
:i"
.rr
DAV(15 )
I>
2\7
NDAC(17 )
I>
2"
.rr
CD
.
<.
c
NRFDI16
CD
(')
CD
(141
SRa (121
191
REN (191
(21
~
IFC (181
.rr
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
'V Designates 3-state outputs.
<'
e
CD
.
C7I EOI
SRa
REN
2"~
I>
(II
~
181 ATN
.rr
1
CD
EOI
(13)
DAV
(31 IFC
(151
(61
(171
(41 NDAC
(161
(51 NRFD
DAV
Designates passive-pullup outputs.
(II
NDAC
NRFD
»
»2<
c
RECEIVE/TRANSMIT FUNCTION TABLE
nm
CONTROLS
DC
TE
BUS-MANAGEMENT CHANNELS
ATNt
:2
H
H
H
H
H
L
L
L
H
L
s:
H
L
L
L
H
X
X
o::g
o2
SRa
REN
DATA-TRANSFER CHANNELS
IFC
EOI
DAV
NDAC
NRFD
(Controlled by TEl
,..L
T
R
R
(Controlled by DCI
."
~
ATNt
L
R
T
R
R
T
R
T
T
r-!L
T
R
T
T
R
T
R
R
R
R
T
T
T
R
T
T
T
T
R
R
R
H = high level, L = low level, R = receive, T = transmit, X = irrelevant
Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the
terminal side. Data transfer is noninverting in both directions.
t ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC
and TE inputs are in the same ~tate. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only.
4-436
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN75ALS161
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
ADVANCE
INFORMATION
schematics of inputs and outputs
EQUIVALENT OF ALL
CONTROL INPUTS
TYPICAL OF SRQ;NOAC, and NRFD
GPIB 1/0 PORT
-.---;r~-r----~'~I---,--~>--vec
vce ---1>-----
1.7 kU
NOM
9kl}
NOM
I
I
10 kl!
NOM
I
I
I
INPUT
GND
...._
-+_--<~_
a.
PORT
Circuit inside dashed lines is on the driver outputs only.
III
TYPICAL OF ALL 1/0 PORTS
EXCEPT SRQ, NDAC, and NRFD GPIB 1/0 PORTS
G)
>
'Q)
(.)
G)
a::
""-
.
III
G)
>
''::;
a
G)
c:
::J
INPUT IOUTPUT
PORT
Driver output Req ~ 30!l NOM
Receiver output Req ~ 110!l NOM
Circuit inside dashed lines is on the driver outputs only.
Z
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Low-level driver output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
OW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1125 mW
J package ........................................................ 1375 mW
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11 50 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OOC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 60 seconds: J package .......... 300°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: OW or N package . . .. 260°C
NOTES:
1. All voltage values are with respect to network ground terminal.
2. For operation above 25·e free-air temperature, derate the DW package to 720 mW at 70·e at the rate of 9.0 mW/·e, derate
the J package to 880 mW at 70·e at the rate of 11.0 mW/·e, and derate the N package to 736 mW at 70·e at the rate
of 9.2 mW/·e.
o
i=
<
:?:
a:
oLl-
-w
Z
(J
Z
C
-a;
25
CJ
CII
t All typical values are at T A = 25°C.
rx:
--.
en
CII
PARAMETER MEASUREMENT INFORMATION
>
-io:
SV
FROM IBUS)
OUTPUT UNDER:-~rp----"-"'-TEST POINT
TEST
ISee Note A!
Ilsee
CL = 30 pF
Note A)
'::'
LOAD CIRCUIT
-
--3 V
I.SV
I.S V
ISee Not. B)
BUS
INPUT
~---OV
_-----'-1-2.2 V
.L,.SV
-..I: .
z
o
ISe. Note B)
-VOH
.
tPHL*-+!
I_-----_+---VOH
TERMINAL
OUTPUT
I.SV
VOLTAGE WAVEFORMS
W
(.)
z
FIGURE 2. BUS-TO-TERMINAL
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ~ 1 MHz, 50% duty cycle, tr :s6 ns,
tf ,,;6 ns, Zout = 50 n.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
oLL
Z
1.SV
VOLTAGE WAVEFORMS
FIGURE 1. TERMINAL-TO-BUS
PROPAGATION DELAY TIMES
i=
:2!
a:
«
\-1 :S~ - - 30Vv
tPLH~
tPHL~
BUS
OUTPUT
3kn
LOAD CIRCUIT
_-----_,.- INPUT
c:
::J
FROM !TERMINAL!
OUTPUT UNOER
---1~---~-~-TESTPOINT
TEST
480 n
CL = 30 pF
CII
240n
200n
l'
C
4.3V
«
>
c
«
4-439
•
SN75ALS161
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
ADVANCE
INFORMATION
PARAMETER MEASUREMENT INFORMATION
SI
SI
Q--5V
200n
FROM (BUS)
OUTPUT UNDER_,....-. . .TEST
J
CL = 15 pF
(See Not. A)
480
-4~-"-"'- TEST POINT
OUTPUT
UNDER TEST
J
n
LOAD CIRCUIT
CONTR~L•
INPUT
!:
:::I
CD
-..I
I
14-
BUS
OUTPUT
SI CLOSED
~
'V';5: - --
tPHZ...-I
I
11
2V
I
CONTROL.
INPUT __ J
I
t--
-90%- - -
I
VOH
tPLZ~
'\:
1.0 V
tPZL--!
C I I "'3.5 V
0.5 V
___ VOL
r--
I
I
S10PEN
0V
l .5V
~1.5V
i\I ' - ___
(S••_____
Nota B) J Ij\
1'- _____
tPZH-!
TERMINAL
I
OUTPUT
I
TERMINAL
OUTPUT
SI CLOSED
1.5V
I-"
tpHZ-..j
I
r--
------
I
I
tPLZ-!
I
OV
... 4V
1.0V
VOLTAGE WAVEFORMS
»c
<
»
2
om
2
."
o
::rJ
s:
»
::!
o
2
4-440
VOH
90%
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics:. PRR ,; 1 MHz, 50% duty cycle, t f
tf ,;6 ns, Zout = 50 II.
UI
3V
OV
FIGURE 4. TERMINAL ENABLE
AND DISABLE TIMES
FIGURE 3. BUS ENABLE AND
DISABLE TIMES
<-CD
3kfl
--,V,--------, r-----
3V
VOLTAGE WAVEFORMS
CD
CL = 15pF
(Sea Nota A)
LOAD CIRCUIT
(Sea Not. B) J ~.
_______
' - ____ OV
tPZL~
(')
.
}.\.
__ JI
'-
tpZH
BUS
OUTPUT
SI OPEN
C
~~
!!.
""'..j"""'5-V------
240n
FROM (TERMINAL)
. . .-TEST POINT
Q--4.3V
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
,; 6
ns,
SN75ALS161
OCTAL GENERAL"PURPOSE INTERFACE BUS TRANSCEIVER
ADVANCE
INFORMATION
TYPICAL CHARACTERISTICS
:r..
TERMINAL HIGH·LEVEL OUTPUT VOLTAGE
vs
HIGH·LEVEL OUTPUT CURRENT
4.0
CC =15V
3.5
TA = 25°C
J
.........
f.
3.0
0
"ii
2.0
..J
1.5
>
.""
2.5
>
...
i:.
:f 1.0
I
~
0.5
o
o
-5
:r&
."
~
'\
VCC=5V
TA = 25°C
0.5
-
0.4
CI.
=
..
0.3
~
0.2
0
"ii
_"\
>
..J
""
0
..J
I
..J
0 0.1
'\..
%
0.6
.ll!
'\
CI.
..
'"
TERMINAL LOW·LEVEL OUTPUT VOLTAGE
vs
LOW·LEVEL OUTPUT CURRENT
/
/
V
/"
V
V
/
'/
•
...
II)
CI)
>
'"
>
"a;
U
-10 -15 -20 -25 -30 -35 -40
10
20
30
40
50
IOL -Low·Level Output Current-mA
IOH-High·Level Output Current-mA
FIGURE 5
FIGURE 6
60
CI)
a:
--...
I I)
CI)
>
"C
TERMINAL OUTPUT VOLTAGE
vs
BUS INPUT VOLTAGE
C
CD
c:
::;
4.0
VCC=5V
No load
TA = 25°C
3.5
>I
.....
3.0
z
:I 2.5
~
=
S-
2.0
0
I
0
"
1.5
>
1.0
o
VT-
VT+
i=
c
I
'""
-10
-20
-40
- 30
-50 -60
IOH-High·Level Output Current-mA
::»
FIGURE 8
/V
0.5
/"
0.4
'"
0.3
....~
....I
~
0.2
0
1
....
'"
VCC=5V
TA - 25°C
VV
V
V
V
./
V
0.1
o
o
10 20 30 40 50 60 70 80 90 100
IOL - Low-Leval Output Current-mA
FIGURE 9
CD
n
BUS OUTPUT VO LTAG E
!.
<
CD
.
BUS CURRENT
vs
BUS VOLTAGE
vs
TERMINAL INPUT VOLTAGE
til
VCC=5V
No load
TA = 25°C
2
>I
l>
C
<
l>
2
0
m
2
."
0
-
8.
!0
>
;
~
0
I
0
>
:D
3:
~
THE UNSHADED
~H-f-+-+" AREA CONFORMS TO
~~~-+--j.,>" PARAGRAPH 3.5.3 OF
OL-~
0.9
__- L__
1.0
~~L--L
~ IEEE
__~__L-~
1.1 1.2 1.3 1.4 1.5
VI-Input Voltage-V
1.6
1.7
-1
FIGURE 10
2
3
4
VI/O(bus)-Bus Voltage-V
FIGURE 11
S
2
4-442
STANDARD 488-1978
0
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 856012 • DALLAS. TEXAS 75286
5
6
ADVANCE
INFORMATION
SN75ALS162
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
02618. JUNE 1986
MEETS IEEE STANDARD 488-1978 (GPIB)
•
a-Channel Bidirectional Transceiver
•
Designed to Implement Control Bus
Interface
DW PACKAGE
(TOPVIEWI
•
Designed for Multicontrollers
•
High-Speed Advanced Low-Power Schottky
Circuitry
•
Low Power Dissipation ..• 46 mW Max per
Channel
•
Fast Propagation Times ... 20 ns Max
•
High-Impedance P-N-P Inputs
•
Receiver Hysteresis ... 650 mV Typ
•
Bus-Terminating Resistors Provided on
Driver Outputs
GPIB
110
PORTS
SC
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRO
NC
GND
VCC
NC
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRO
NC
DC
TERMINAL
I/O PORTS
•
.
II)
•
No Loading of Bus When Device is Powered
Down (VCC - 0)
•
Power-Up/Power-Down Protection
(Glitch-Free)
N DUAL-!N-UNE PACKAGE
ITOPVIEWI
U
description
The SN75ALS162 eight-channel generalpurpose interface bus transceiver is a monolithic,
high-speed, Advanced Low-Power Schottky
process device designed to provide the busmanagement and data-transfer signals between
operating units of a multiple-controller
instrumentation system. When combined with
the SN75ALS160 octal bus transceiver, the
SN75ALS 162 provides the complete 16-wire
interface for the IEEE 488 bus.
CD
'G>)
GPIB
I/O
PORTS
SC
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRO
GND
VCC
NC
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRO
DC
CD
..
£E
II)
CD
>
'C
TERMINAL
I/O PORTS
Q
CD
C
::::i
NC-No internal connection.
2
o
The SN75ALS 162 features eight driver-receiver
pairs connected in a front-to-back configuration
to form input/output (I/O) ports at both the bus and terminal sides. The direction of data through these
driver-receiver pairs is determined by the De, TE, and se enable signals. The se input allows the REN
and IFe transceivers to be controlled independently.
i=
:t
a:
The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a
high impedance to the bus when Vee = O. The drivers are designed to handle loads up to 48 milliamperes
of sink current. Each receiver features p-n-p transistor inputs for high input impedance and a guaranteed
hysteresis of 400 millivolts minimum for increased noise immunity. All receivers have 3-state outputs to
present a high impedance to the terminal when disabled.
-2w
The SN75ALS 162 is manufactured in a 22-pin dual-in-line N package and in 24-pin OW package, and is
characterized for operation from ooe to 70 o e.
«
ou.
CJ
2
~
C
«
ADVANCE IIIFORMATIOI d......1ItI
~••toin
=:.:;.=,n:
..~..:~:::~.tf.
other
ore •••
cha...
iIItiI.n~
~
wlt.....t aatico.
joct 10
Copyright @ 1986, Texas Instruments Incorporated
TEXAS , . ,
INSTRUMENTS
POST OFFICE BOX 856012 • DALLAS. TEXAS 75285
4-443
SN75ALS16.2
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
ADVANCE
INFORMATION
CHANNEL IDENTIFICATION TABLE
IDENTITY
NAME
DC
TE
Talk Enable
SC
System Control
ATN
SRQ
Attention
Service Request
REN
Remote Enable
IFC
Interface Clear
Control
EOI
End or Identify
DAV
Data Valid
NDAC
NRFD
CLASS
Direction Control
Bus
Management
Data
Not Data Accepted
Not Ready for Data
logic svmbol t
Transfer
logic diagram (positive logic)
DC [13] (12) EN1/G4
EN2/G5
TE [2J (2)
SC [1J (1)
EN3
s·i"""
CD
...o
~-.,
TE
cr
CD
...
SC
ATN
III
~
[9J
(9) ATN
CD
(')
CD
~.
iil
REN
[17J
EOI (15)
[8J
(8)
[15J
SRa (13)
[10J
(10)
[22J
REN (20)
[3J
(3)
[21J
IFC (19)
[4J
(4)
[18J
(16)
(7J
(201
(181
(51
(19]
[61
(61
EOI
SRa
IFC
DAV
»
c
~
b::::::JE:J~r-r~ NRFD
2
n
m
2
-
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
V Designates 3-state outputs.
~ Designates passive-pullup outputs.
"T1
o::D
s:
~
o
2
REN
NDAC
DAV
NDAC
NRFD
(17)
( I Denotes pin numbers for OW package.
( I Denotes pin numbers for N package.
4-444
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
IFC
(7) DAV
/51 NDAC
NRFD
ADVANCE
INFORMATION
SN75ALS162
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
RECEIVE/TRANSMIT FUNCTION TABLE
H = high level. L = low level, R = receive, T = transmit, X = irrelevant
Direction of data· transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the
terminal side. Data transfer is noninverting in both directions.
t A TN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EO) whenever the DC
and TE inputs are in the same state. When DC and TE are in oPPosite states. the ATN channel functions as an independent transceiver onlv.
II
,.
..
en
Q)
schematics of inputs and outputs
>
"a;
EQUIVALENT OF ALL
CONTROL INPUTS
TYPICAL OF SRQ. NDAC. and NRFD
GPIB I/O PORT
-'---~t--~~--~---t--Vcc
Vee - - -....- - - -
'kn
1.7 kO
10 kU
NOM
NOM
NOM
Co)
Q)
a:
--.
en
Q)
>
";:
Q
Q)
INPUT
c::
:::i
GND-4_ _
~
__
~_
·~--4i-~---~-4--~-----GNO
INPUT/OUTPUT
PORT
Circuit inside dashed lines is on the driver outputs only.
TYPICAL OF ALL I/O PORTS
EXCEPT SRQ. NDAC. and NRFD GPIB I/O PORTS
:2
o
i=
<
~
a:
oLL
-w
:2
----~--~--~4r~~--~~----~---------GND
INPUT/OUTPUT
PORT
Driver output Req = 30 P NOM
Receiver output Req = "0 {) NOM
Circuit inside dashed lines is on the driver outputs only.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
(,)
:2
<
>
C
<
4·445
SN75ALS162
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
ADVANCE
INFORMATION
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vec (see Note 1) ............•.................................. 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
low-level driver output current .............................................. 100 mA
Continuous total dissipation at (or below) 25 DC free-air temperature (see Note 2):
DW package ....................................................... 1350 mW
N package .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1700 mW
Operating free-air temperature range ...................................... ODC to 70 DC
Storage temperature range .......................................... -65 DC to 150 DC
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: DW or N package. . . . .. 260 DC
NOTES:
1. All voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, derate the DW package to 864 mW at 70°C at the rate of 10.8 mW/oC, and
derate the N package to 1088 mW at 70°C at the rate of 13.6 mw/oe.
II
recommended operating conditions
r-
Supply voltage. Vee
5'
High-level input voltage. VIH
CD
Low-level input voltage. VIL
..
C
~.
;;;.
f
High-level output current, IOH
Low-level output current, IOL
NOM
5
MAX UNIT
5.25
V
0.8
V
V
2
-5.2
Bus ports with 3-state outputs
-800
Terminal ports
48
Bus ports
16
Terminal ports
0
Operating free-air temperature, T A
(')
CD
<'
...en
CD
»
c
~
:2
n
m
-
:2
."
o
:x.
s:
»
:::!
o
:2
4·446
MIN
4.75
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
70
mA
~A
mA
°e
ADVANCE
INFORMATION
SN75ALS162
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
,
PARAMETER
TEST CONDITIONS
Input clamp voltage
Vhys
Hysteresis (VT + - VT-I
High-level
VOHt
VOL
output voltage
LowRlevel
output voltage
Input current at
II
IIH
IlL
VI/O(busl
maximum input voltage
Bus
= -800/iA
= -5.2 rnA
= 16 rnA
Terminal
10H
Bus
Terminal
10H
10L
Bus
10L - 48 rnA
Terminal
VI
=
VI
=
VI
= 0,5
High-level
Terminal
input current
and
Low-level
control
input current
inputs
Voltage at bus port
Power on
Short-circuit
Terminal
output current
Bus
Supply current
ei/o(busl
Bus-port capacitance
5 V, TA
=
3,3
V
fiA
2,7 V
0,1
20
fiA
-10 -100
!iA
V
Il(busl
Il(busl
=0
= -12
VI(busl
2,5
= 0.4
= 2,5
= O.
Vl(busl
=5V
=0V
=0
V to 2,5 V
to 5.5 V
=
1 MHz
3.7
-1.5
V
V
>
'Q)
+2,5
-3.2
2,5
0
0,7
rnA
-15
-35
-25
-50 -125
55
30
-75
75
U
fiA
-...
rnA
'':
rnA
Q)
pF
:::i
Q)
a:
2,5
-40
to 2.5 V
...
Q)
-3.2
0
•
II)
-1.3
V to 3.7 V
TE, De, and se low
to 2 V, i
3,0
rnA
- 1.5 V to 0.4 V
Vee - 5 V to 0 V,
VI/a
2.5
V
100
No load,
lee
3.5
0.2
Driver disabled
Vee
2.7
5.5 V
VI/bus I
Power off
0,65
0,5
Vl(busl - 3.7 V to 5 V
=
V
0.4
0.35
Driver disabled
Current into bus port
t All typical values are at Vee
UNIT
-1.5
0.5
Vl(busl
lOS
MAX
-0.8
0,3
Vl(busl -
II/O(busl
MIN Typt
11= -18 rnA
VIK
I I)
Q)
>
C
c
25°e.
*VOH applies for three-state outputs only.
2:
o
i=
«
:E
a::
oLL
2:
w
(.)
2:
~
C
«
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
4-447
SN75ALS162
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
ADVANCE
INFORMATION
switching characteristics over recommended range of operating free-air temperature (unless otherwise
noted), Vee .. 5 V
PARAMETER
FROM
TO
Terminal
Bus
TEST
CONDITIONS
MIN TYpt
MAX
10
20
12
20
5
10
7
14
Propagation delay time,
tpLH
low-to-high-Ievel output
Propagation delay time,
tpHL
high-to-Iow-Ievel output
Propagation delay time,
tpLH
low-to-high-Ievel output
tPHL
r-
:i"
..c;;r
CD
CL = 30 pF,
Terminal
Bus
Propagation delay time,
•
CL = 30 pF,
See Figure 1
.Output enable time to high level
tpHZ
Output disable time from high level
tpZL
Output enable time to low level
tpLZ
Output disable time from low level
tpZH
.output enable time to high level
tpHZ
tpZL
Output disable time from high level
tpLZ
Output disable time from low level
TE, DC,
or
SC
BUS
(ATTN, EOI,
CL= 15pF,
30
20
REN,IFC,
See Figure 3
45
and DAV)
ns
20
20
TE, DC,
Terminal
or
Output enable time to low level
ns
ns
See Figure 2
high-to-Iow-Ievel output
tpZH
UNIT
SC
CL=15pF,
25
See Figure 4
30
ns
25
t All typical values are at T A = 25 ·C.
CD
Ul
PARAMETER MEASUREMENT INFORMATION
:::0
CD
n
CD
;;.r
..
5V
4.3V
CD
(R
240n
200n
FROM (BUS)
OUTPUT UNDER-4~----4~"'I--TEST POINT
TEST
'l'
l>
c
~
z
(')
Z
."
o::tI
INPUT
BUS
OUTPUT
::!
CL =30pF
(See Note A)
3kn
LOAD CIRCUIT
, _ - - - - - " ' - - - --3 V
1.5V
1.5V
(See Note B)
I
OV
tPHL-ff-+I
!I"'2-.2-V------I-- -VOH
BUS
INPUT
1,.5
---I: .
V
'S.. Note B)
tPLH~
\-1:~ - 0V
-3
•
v
tPHL~
I_-----_:t---VOH
TERMINAL
OUTPUT
1.5V
VOLTAGE WAVEFORMS
3:
l>
o
z
'='
LOAD CIRCUIT
m
-
'l'
480 n
CL = 30 pF
(See Note A)
FROM 'TERMINAL)
OUTPUT UNDER
- .....- - - -...~.-TEST POINT
TEST
1.5V
VOLTAGE WAVEFORMS
FIGURE 1. TERMINAL-TO-BUS
PROPAGATION DELAY TIMES
FIGURE 2. BUS-TO-TERMINAL
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the follo\,\(ing characteristics: PRR s 1 MHz, 50% duty cycle, tr s6 ns,
tf S 6 ns, Zout = 50 II.
4-448
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
ADVANCE
INFORMATION
SN75ALS162
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
PARAMETER MEASUREMENT INFORMATION
51
o--5V
200n
FROM (BUS)
OUTPUT UNOER ........ - -.....-~~ TEST POINT
TEST
CL = 15 pF
480n
(See Note A)
FROM (TERMINAL)
OUTPUT
-4t--"---4~ TEST POINT
UNOER TEST
J
J
LOAD CIRCUIT
- - , r-------"\.
CONTROL
INPUT
'l(tl.5V
__ J
'I'\.. _______ J
(See Note B)
tPZH--I
BUS
OUTPUT
I
I
14I
I
I
2 V
tpZL --+---+I
51 OPEN
,\1
CL = 15 pF
3kn
(See Note A)
LOAD CIRCUIT
r - - - - 3V
1.5V
':'
\ . . - - - - OV
V
tpHZ-.I
t+-
- - - ,
90%
-
I
VOH
tPLZ--l...t
~II
tPZH-!,.TERMINAL
I I
OUTPUT'
1.5V
51 OPEN_ _---1
I
0V
BUS
OUTPUT
'1.0V·
51 C L O S E D .
0.5 V
'---------' - - -
--, ,------ --"' r-----
CONTROL
¥1.5V
INPUT __ J ,...
(See_____
Note B) J
I '- ___
tPZL--!,.....
"3.5 V
VOL
TERMINAL
OUTPUT
51 CLOSED
~1.5V
3V
JI'1'- _____ OV
tpHZ-.j
I
,...
------
,
VOH
90%
tPLZ--!
III
II)
>
-iii
,
OV
.. 4V
I
II
..
u
II)
-..
IX:
1.0V
I II
II)
VOLTAGE WAVEFORMS
>
-;:
C
VOLTAGE WAVEFORMS
FIGURE 3. BUS ENABLE AND
DISABLE TIMES
FIGURE 4. TERMINAL ENABLE
AND DISABLE TIMES
II)
c
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR s 1 MHz, 50% duty cycle, tr s6 ns,
tf s6 ns, Zout = 50 O.
::i
Z
o
i=
/
/
/
./
0.1
'\.
-5
-10 -15 -20 -25 -30 -35 -40
10
20
30
40
50
IOL -Low·Level Output Current-mA
IOH-High·Level Output Current-mA
III
:0
FIGURE 5
FIGURE 6
CD
n
CD
TERMINAL OUTPUT VOLTAGE
vs
BUS INPUT VOLTAGE
Cr
CD
;;;
4.0
VCC=5V
No load
TA = 25°C
3.5
l>
C
<
l>
2
o
m
2
."
o
:xJ
s:
l>
>I
3.0
&
:J 2.5
...
2.0
::I
1.5
>
1.0
~
::I
c-
0
I
0
!
VT-
VT+
0.5
o
o
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VI-Input Voltage-V
FIGURE 7
::!
o
2
4·450
/
V
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
60
ADVANCE
INFORMATION
SN75ALS162
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
TYPICAL CHARACTERISTICS
BUS HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
BUS-LOW LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
4
>I
..'"
i>
3
"
2
.a-"
0
'ii
>
0.6
VCC=5V
TA = 25°C
~
>I
8.
..a
"
~
0
'ii
'\
..
J:
:f'"
.
i0
"" ~
0
>
o
o
0.4
0.3
VV-
>
..J
0.2
..J
I
"\
I
:t
/'
0_5
~
~ i'\.
..J
VCC=5V
TA = 25°C
..J
~
V
V
•
/'
.
/
III
G)
0.1
o
o
-10
-20
-40
- 30
-50 -60
IOH-High-Level Output Current-mA
V
Y
V
>
·i
(,)
G)
10 20 30 40 50 60 70 80 90 100
IOL - Low-Level Output Current-mA
VCC=5V
No load
TA = 25°C
G)
c
::::i
2
«
>I
.
E
0
c
f!
-1
I
t
..&
~
2:
o
;;
-2
:;
t=
(.)
II)
9"
....I
"
~
J:I
~
.;:
Q
FIGURE 9
FIGURE 8
-..
__
L-~
1.1 1.2 1.3 1.4 1.5
VI-Input Voltage-V
1.6
1.7
-1
FIGURE 10
o
2
3
4
VI/O(bus)-Bus Voltage-V
FIGURE 11
5
-o
2:
IEEE STANDARD 488-1978
__- L__~~__~
6
w
2:
c
'iii
u
Z
CD
a:
= high level, L = low level, X. = irrelevant, Z = High-impedance
state.
--.
en
CD
>
'r::
C
CD
t:
::::i
z
o
i=
'Qj
(J
II)
-..
a:
t il
II)
>
'':::
mA
C
DC
c
:::;
II)
2:
o
i=
"i)
U
~
...en
~
"~
C
CD
TEST CIRCUIT
c:
:.:J
VOLTAGE WAVEFORMS
FIGURE 2. BUS·TO·TERMINAL PROPAGATION DELAY TIMES
~SV
'is~_---3V
52
-------+..,;.
tpZH-.j...-
BOUTPUTI
S1 to3V ,
4800
S20PEN
I
tpZL
, ..
:
tPHZ--.I
0V
0.8 V
3SV
BOUTPUT
S1 toGND
CJ
Z
FIGURE 3. TE·TO·BUS ENABLE AND DISABLE TIMES
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75265
s
o
-Zw
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR
tf s 6 ns, Zo~t = 50 11.
B. CL includes probe and jig capacitance.
~
:E
a:
11.
1.0V
S2CLOSED
1:EST CIRCUIT
z
o
1 MHz, 50% duty cycle, tr S 6 ns,
~
Q
c(
4·457
SN75ALS183
OCTAL GENERAL,PU"POSE INTERFACE 8US TRANSCEIVER
ADVANCE
INFORMATION
PARAMETER MEASUREMENT INFORMATION
~_
3V
• TE INPUT1'''''.5_V_ _ _ _ _- J t . 5 :_ _ _ -ov
'PZH~
o OUTPUT I
SI'o3V
S20PEN
'PZL
I
I
~
I
1.6 V
--.of
o OUTPUT
51 to GNO
S2CLOSED
TEST CIRCUIT
'PHZ--t
i
I
I
'PLZ"",",
OV
4V
_ _ _ _ _ _ _1._o..!'!-
_ "';"VOL
VOLTAGE WAVEFORMS
.FIGURE 4. TE·TO-TERMINAL ENABLE AND DISABLE TIMES
r-
:r
CD
c~.
~
iil
>-+-;.::..-.....-~,....-'OUTPUT
if
n
CD
~.
iil
VOLTAGE WAVEFORMS
TEST CIRCUIT
FIGURE 5. PE-TO-BUS PULLUP ENABLE AND DISABLE TIMES
l>
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR :SO 1 MHz, 50% duty cycle, tr :SO 6 ns,
tf :SO 6 ns, Zout = 50 II.
B. CL includes probe and jig capacitance.
C
~
2
om
:2
."
o::rJ
s:
l>
::::!
o
2
4-458
TEXAS ..,
INSTRUMENTS
POST OFFICE aox 8560'2 • DALLAS. TEXAS 75285
ADVANCE
INFORMATION
SN75ALS163
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
TYPICAL CHARACTERISTICS
TERMINAL HIGH·LEVEL OUTPUT VOLTAGE
vs
HIGH·LEVEL OUTPUT CURRENT
LOW·LEVEL OUTPUT CURRENT
4.0
>I
t
.
!
'a
>
3.0
2.0
....
1.5
II
i:
VCc s 5V
TA = 25°C-
~
..5-"
"""~
"
1.0
0.5
o
-5
0.4
"
0.3
....t
....~
....I
r\.
0.2
V
V
/
/
V
V
./
•
..
II)
CD
0.1
0
~
o
>
0
'ii
~
.2'
:z:
I
:z:
t
'a
V
J
.I.
VCC =5V
0.5 -TA-25°C
::r
~
2.5
"
0
'ii
»
......
0.6
I
I
3.5
TERMINAL LOW·LEVEL OUTPUT VOLTAGE
vs
>
~
o
-10 -15 -20 -25 -30 -35 -40
>
·i
u
o
IOH-High·Level Output Current-mA
10
20
30
40
50
IOL -Low· Level Output Current-mA
FIGURE 6
FIGURE 7
TERMINAL OUTPUT VOLTAGE
60
-.
CD
a:
I I)
CD
>
·C
C
CD
c
vs
:::::i
BUS INPUT VOLTAGE
4.0
VCC=5V
No load
TA = 25°C
3.5
>I
3.0
!
2.5
8.
2:
I
~ 2.0
:;
~
1.5
>
1.0
0
I
0
o
I
I
VT-
i=
VT+
«
~
a:
oLL
0.5
o
o
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VI-Input Voltage-V
FIGURE 8
2:
w
(.)
2:
~
C
«
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
4-459
SN75ALS163
OCTAL GENERAL"PURPOSE INTERFACE BUS TRANSCEIVER
ADVANCE
INFORMATION
TYPICAL CHARACTERISTICS
BUS LOW-LEVEL OUTPUT VOLTAGE
vs
BUS LOW-LEVEL OUTPUT CURRENT
BUS HIGH-LEVEL OUTPUT VOLTAGE
vs
BUS HIGH-LEVEL OUTPUT CURRENT
4
0.6
VCC I=5V
TA =2SOC
r----..,
Vcc=SV
TA= 2SoC
~
0.5
.a-"
0_4
0
'ii
0.3
t
/'
'15
""
>
\..
c:
::::J
"\
"
~
CD
.:c"
C
CD
~
:rJ
CD
o
o
-10
-20
-30
..
V
/)"
1 V
0.2
...I
I
"~
-40
...I
~
-50
0.1
o
-60
o
IOH-High-Level Output Current-mA
10
20 30 40 50 60
FIGURE 10
BUS OUTPUT VOLTAGE
vs
TERMINAL INPUT VOLTAGE
:c"
CD
iil
VCC= SV
No load
TA = 2SoC
3r-~---r--~--Hr-+--~--+-~
l>
C
2r--+---r--+---K--+--~--r--;
om
:2
s:
»
-I
O~~~-L__~~__- L__~~~
0.9
1.0
1.1
1.2
1.3
1.4
'_5 1_6
VI-Input Voltage-V
FIGURE 11
(5
:2
4-460
70 80 90 100
IOL -Low-Level Output Current-mA
FIGURE 9
CD
"o:JJ
/
/'
(')
~
:2
V
V
/
TEXAS ",
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75266
1.7
ADVANCE
INFORMATION
SN75ALS164
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
02908. JUNE 1986
•
a-Channel Bidirectional Transceiver
•
Designed to Implement Control Bus
Interface
OW PACKAGE
(TOP VIEWI
•
Designed for Multicontrollers
•
High-Speed Advanced Low-Power Schottky
Circuitry
•
Low Power Dissipation . . . 46 mW Max per
Channel
•
Fast Propagation Times . . . 20 ns Max
•
High-Impedance P-N-P Inputs
•
Receiver Hysteresis . . . 650 mV Typ
•
Bus-Terminating Resistors Provided on
Driver Outputs
•
•
SC
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRO
NC
GND
GPIB
I/O
PORTS
N DUAL-IN-LiNE PACKAGE
(TOP VIEWI
GPIB
I/O
PORTS
Power-Up/Power-Down Protection
(Glitch-Free)
description
The SN75ALS 164 eight-channel generalpurpose interface bus transceiver is a monolithic,
high-speed, Advanced Low-Power Schottky
device designed to meet the requirements of
IEEE Standard 488-1978. Each transceiver is
designed to provide the bus-management and
data-transfer signals between operating units of
a multiple-controller instrumentation system.
When combined with the SN75ALS160 octal
bus transceiver, the SN75ALS 164 provides the
complete 16-wire interface for the IEEE 488 bus.
The SN75ALS164 features eight driver-receiver
pairs connected in a front-to-back configuration
to form input/output (I/O) ports at both the bus
and terminal sides. All outputs are disabled (at
a high-impedance state) during Vee power-up
and power-down transitions for glitch-free
operation. The direction of data flow through
these driver-receiver pairs is determined by the
DC, TE, and SC enable signals. The
SN75ALS164 is identical to the SN75ALS162
with the addition of an OR gate to help simplify
board layouts in several popular applications.
The ATN and EOI signals are ORed to pin 21,
which is a standard totem-pole output.
VCC
ATN+EOI
REN
IFC
NDAC
NRFD
TERMINAL
DAV
I/O PORTS
EOI
ATN
SRO
DC
CI)
'Q>)
(,)
CI)
-...
a:
en
CI)
>
'0::
C
CI)
c::
:::::i
NC-No internal connection.
CHANNEL IDENTIFICATION TABLE
NAME
DC
TE
SC
ATN
SRO
REN
IFC
EOI
ATN+EOI
DAV
NDAC
NRFD
IDENTITY
CLASS
Direction Control
Talk Enable
System Control
Attention
Control
Service Request
Remote Enable
Interface Clear
Bus
End or Identify
ATN logical OR EOI
Data Valid
Not Data Accepted
Not Ready for Data
2:
o
~
Management
:?!
a:
ou..
Logic
Data
-w
2:
Transfer
CJ
2:
c
-....___..:.(4.:.:.' IFC
m
[~
m
-
DAV~(1~6~1_ _+-_ _.....~ ~~e--_-.!.(7~IDAV
;2
."
o
[20]
[5]
NDAC~(l~B~I_ _+-_ _.....~ ~~.-_ _~(5~INDAC
:0
3:
~
[~
o;2
[ ] Denotes pin numbers for DW package.
( I Denotes pin numbers for N package.
4-462
~
+-__.....-1 ;>-.....___..:;(60'-' NRFD
NRFD ~(1,,-7~1_ _
::!
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
ADVANCE
INFORMATION
SN75ALS164
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
RECEIVE/TRANSMIT FUNCTION TABLE
H = high level, L = low level, R = receive. T = transmit, X = irrelevant
Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the
terminal side. Data transfer is non inverting in both directions.
..
t ATN is a normal transceiver channel that functions additionally as an internal direction control or talk"enable for EOI whenever the DC
and TE inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only.
II
~
CD
ATN+ EOI FUNCTION TABLE
INPUTS
ATN
EOI
ATN+EOI
H
X
X
H
L
H
H
L
L
>
u
-Qi
OUTPUT
CD
a::
.....
Ul
~
CD
>
-0:::
C
CD
c:
::;
2:
-o
le::(
:!
a::
ou.
2:
w
Co)
2:
e::(
>
C
e::(
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-463
SN75ALS164
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
ADVANCE
INFORMATION
schematics of inputs and outputs
TYPICAL OF SRO, NDAC, and NRFD
GPIB 1/0 PORT
EOUIVALENT OF ALL
CONTROL INPUTS
~----~r~----_-~'r-----~----~vcc
vee -----...-----9kn
1.7 kU
10 ki!
NOM
NOM
NOM
INPUT
GriD ......__-<'-__......_
~---~r+~--~~----~-------GNO
PORT
•
Circuit inside dashed lines is on GPIB I/O ports only.
I--------t---------i
TYPICAL OF ALL 1/0 PORTS
EXCEPT SRO, NDAC, and NR FD GPIB 1/0 PORTS
r-
5'
CI)
ATN+EOIOUTPUT
c....
~'
C;;
~
n
OUTPUT
CI)
~'
C;;
PORT
Driver output Req = 30 Il NOM
Receiver output Req = 110 Il NOM
Circuit inside dashed lines is on GPIB I/O ports only.
l>
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage .................... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Low-level driver output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 mA
Continuous total dissipation at (or below) 25 DC free-air temperature (see Note 2):
OW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1350 mW
N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1700 mW
Operating free-air temperature rarige ..................................... '. 0 DC to 70 DC
Storage temperature range ......................................... - 65 DC to 1 50 DC
Lead temperature 1,6 mm (1/16) inch from the case for 10 seconds: OW or N pac;kage .... 260 DC
C
~
2
om
2
."
o
:a
-------*-----4~GND
NOTES:
s:
1. All voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, derate the OW package to 864 mW at 70°C at the rate of 10.8 mW/oC,
and derate the N package tD 1088 mW at 70°C at the rate of 13.6 mW/oC.
l>
::!
o
2
4-464
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 856012 • DALLAS. TeXAS 76265
SN75ALS164
OCTAL GENERAL"PURPOSE INTERFACE BUS TRANSCEIVER
ADVANCE
INFORMATION
recommended operating conditions
Supply voltage, Vee
High-level input voltage, VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
0.8
-5.2
V
2
V
Low-level input voltage, VIL
Bus ports with 3-state outputs
High-level output current, IOH
Low-level output current, IOl
Terminal ports
-800
ATN+EOI
-400
Bus ports
48
Terminal ports
16
ATN+EOI
rnA
~A
rnA
4
Operating free-air temperature, T A
0
70
°e
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
VIK
Input clamp voltage
Vhys
Hysteresis (VT + - VT_)
VOHt
High-level output voltage
II
Low-level output voltage
Bus
Terminal
10H 10H - -400 ~A
10L ~ 16 rnA
Bus
10L - 48 rnA
ATN+EOI
Input current at
Terminal§
10L ~ 4 mA
VI ~ 5.5 V
maximum input voltage
ATN, EOI
VI - 5.5 V
High-level input current
control
ATN, EOI
Low-level input current
control
ATN, EOI
VI/O(bus)
800 ~A
- 5.2 rnA
IOH -
Terminal,
IlL
-18 rnA
Terminal
Terminal
IIH
~
8us
ATN+EOI
VOL
MIN Typt
-0.8
TEST CONDITIONS
II
Voltage at bus port
VI
~
Current into bus port
Power off
2.7
3.5
2.5
3.3
0.3
0.35
0.5
0.2
0.4
100
0.1
20
Q)
"a;
(,J
Q)
a:
--..
( I)
V
Q)
>
";::
~A
C
Q)
c:
~A
::i
40
~
0.5 V
-10 -100
VI
~
0.5 V
-500
Il(bus) - 0
12 mA
Il(bus) Vl(bus) ~ - 1.5 V to 0.4 V
2.5
1.5
+2.5
-3.2
2.5Vto3.7V
VI (bus)
~
3.7 V to 5 V
0
VI(bus) - 5 V to 5.5 V
0.7
Bus
-25
-10
-50 -125
lee
Supply current
No load,
eilo(bus)
Bus~port
Vee - 5 V to 0 V,
VI/O ~ 0 to 2 V, f
ATN+EOI
TE, De, and se low
~
1 MHz
mA
~A
-75
mA
-100
55
30
75
j::
0.5
VI - 2.7 V
Driver disabled
V
V
200
2.7 V
Driver disabled
Power on
0.65
UNIT
2.7
Vl(bus) - 0.4 V to 2.5 V
11/0(bus)
0.4
MAX
-1.5
mA
pF
a:
o
u.
2:
w
(J
2:
C
o
~
2
n
m
2
-n
o
:D
s:
l>
:::!
o
2
4-466
CL = 30 pF,
See Figure 1
MIN
TEXAS . "
INSTRUMENTS
POST OFFice BOX 8580'2 • DALLAS. TeXAS 75285
30
20
45
ns
20
CL=15pF,
See Figure 5
20
25
30
25
ns
SN75ALS164
OCTAL GENERAL"PURPOSE INTERFACE BUS TRANSCEIVER
ADVANCE
INFORMATION
PARAMETER MEASUREMENT INFORMATION
5V
4.3V
240n
200n
FROM IBUS)
OUTPUT UNDER--4I..----.-+-TEST POINT
TEST
CL = 30 pF
1'lseeNoteA)
FROM ITERMINAL)
OUTPUT UNDER
TEST
......- - -.......-....-TEST POINT
J
480 n
....
LOAO CIRCUIT
-
--3V
1.5V
1.5V
BUS
INPUT
~---O'V
!r-----""""-I- - VOH
2.2V
1,.5 V
----I: .
tPHL~
BUS
OUTPUT
3kn
....
LOAD CIRCUIT
_-----_- INPUT
CL = 30 pF
ISoo Nota AI
\-
:5~ -
I .
ISe. Nato B)
-3V
0V
tPHL~
tPLH--14+I
I_-----~:T---VOH
TERMINAL
OUTPUT
1.5V
II
.
II)
CP
1.5V
>
"ii)
tJ
VOLTAGE WAVEFORMS
FIGURE 1. TERMINAL·TO-BUS
PROPAGATION DELAY TIMES
TEST
POINT
CP
VOLTAGE WAVEFORMS
ex:
--.
>
FIGURE 2. BUS-TO-TERMINAL
PROPAGATION DELAY TIMES
I I)
CP
";:
C
VCC
CP
c:
:::i
2kn
FROM
ATN+EOI
VOLTAGE WAVEFORMS
ISo. Note C)
z
o
~
:;
LOAD CIRCUIT
a:::
FIGURE 3. ATN+EOI PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR
tl ,,;6 ns, Zout ~ 500.
C. All diodes are 1 N91 6 or 1 N3064.
:$
oLL
1 MHz, 50% duty cycle, tr ::s; 6 ns,
Z
w
(.)
z
c
-4.3V
NOTES: A. CL includes probe and jig capacitance .
B. The input pulse is supplied by a generator having the following characteristics: PRR :5 1 MHz. 50% duty cycle, tr :56 ns,
tf :56 ns, Zout = 5011.
»o
<
»2
o
-m
2
o""
::XJ
S
»
:::!
o
2
4-468
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN75ALS164
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
ADVANCE
INFORMATION
TYPICAL CHARACTERISTICS
TERMINAL HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
TERMINAL LOWcLEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
4_0
>I
3.S
t
3.0
>
;
2.S
"
2.0
0
....
0
Ii
..
II
...I
J:.
i'"
I
0.6
.........
vdc= SIV
TA=2SoC-
r'\.
8.
.."
>
0
"\
1.0
"
...I
~
i
I
...I
0
>
'r\.
-S
0.2
0
...I
r\.
o
0.3
t
O.S
o
0.4
S-
0
Ii
:t
>
I
tC=5 V
O.S -TA=25'C
l!
0
"r-...
'\
1.S
>I
V
:/
/
II
Ie
CD
0.1
o
-10 -15 -20 -25 -30 -35 -40
/
/
L
/
/
IOH-High-Level Output Current-mA
>
o
20
10
30
40
50
IOl -low-level Output Current-mA
FIGURE 6
60
'CD
u
CD
a:
Ie
CD
FIGURE 7
>
';:
C
TERMINAL OUTPUT VOLTAGE
vs
BUS INPUT VOLTAGE
CD
c:
:J
4_0
VCC=5V
No load
TA=2S'C
3.S
::r
8.
~
i;
3.0
2.0
VT-
"
0
>
z
o
2.S
VT+
1.S
i=
«
:E
a::
ou.
1.0
0.5
o
o
0.2 0.4 0.6 0.8 1.0 1.2 1_4 1.6 1.8 2.0
VI-Input Voltage-V
FIGURE 8
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 8650t 2 • DALLAS, TeXAS 76286
Z
w
o
z
~
c
«
4-469
ADVANCE
INFORMATION
SN75ALS164
,
OCTAL GENERAL"PURPOSE INTERFACE BUS TRANSCEIVER
TYPICAL CHARACTERISTICS
BUS HIGH·LEVEL OUTPUT VOLTAGE
BUS LOW·LEVEL OUTPUT VOLTAGE
vs
vs
HIGH·LEVEL OUTPUT CURRENT
LOW·LEVEL OUTPUT CURRENT
4
0,6
~
3
2
CD
o
o
-10
-20
TA = 2SOC
..
!
O.S
>
.."
0.4
0
'ii
0.3
5-
"
.
-30
-40
/'
V
/'
>
oJ
~
0
oJ
0,2
oJ
0
>
/'
V
V
0.1
o
-SO
-60
o
10
20 30
40
SO 60
70 80
90 100
10L -Low· Level Output Current-rnA
FIGURE 9
CD
/'
V
/
I
10H-High·Level Output Current-rnA
~
/'
'0
'"'""~
5"
...
cr
CD
...en
>I
~ i\.
rC
Vcc= SV
vccl=SV
TA = 2SOC
FIGURE 10
n
CD
BUS OUTPUT VO LTAGE
vs
TERMINAL INPUT VOLTAGE
<"CD
...
en
BUSCURRENT
vs
BUS VOLTAGE
Vcc= SV
No load
TA = 2SOC
l>
C
<
l>
>I
.!.c
.."
U
~
'0
>
2r--+--~--+---H--+--~--+-~
"
5-
"I
0
m
>
-
:j
0.9
__
1.0
~
__- L_ _- L_ _
1.1
1,2
1.3
~_ _u-~
1.4
1,S
__~
1,6
1.7
-1
FIGURE 11
2
FIGURE 12
0
2
4·470
0
3
4
VI/O(bus)-Bus Voltage-V
VI-Input Voltage-V
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
S
6
ADVANCE
INFORMATION
SN75ALS165
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
D3011. JUNE 1986
MEETS IEEE STANDARD 488-1978 (GPIBI
•
8-Channel Bidirectional Transceiver
•
High-Speed Advanced Low-Power Schottky
Circuitry
•
Low Power Dissipation ... 46 mW Max per
Channel
•
Fast Propagation Times ... 20 ns Max
•
High-Impedance P-N-P Inputs
•
Receiver Hysteresis ... 650 mV Typ
•
No Loading of Bus When Device is Powered
Down (VCC a 01
•
Power-Up/Power-Down Protection (GlitchFreel
•
DW. J. OR N PACKAGE
(TOP VIEW)
BUS
1/0 PORTS
TE
Vee
B1
B2
01
02
B3
B4
03
04
B5
B6
B7
05
06
TERMINAL
1/0 PORTS
07
08
PE
B8
GNO
FUNCTION TABLES
EACH DRIVER
Driver and Receiver Can Be Disabled
Simultaneously
INPUTS
D TE PE
H
H
H
description
The SN75ALS 165 eight-channel generalpurpose interface bus transceiver is a monolithic,
high-speed, Advanced Low-Power Schottky
device
designed
for
two-way
data
communications over single-ended transmission
lines. It is designed to meet the requirements of
IEEE Standard 488~ 1978. The transceiver
features driver outputs that can be operated in
either the passive-pullup or three-state mode. If
Talk Enable (TEl is high, these ports have the
characteristics of passive-pullup outputs when
Pullup Enable (PEl is low and of three-state
outputs when PE is high. Taking TE low places
these ports in the high-impedance state. Taking
TE and PE low places both the drivers and
receivers in the high-impedance state. The driver
outputs are designed to handle loads up to 48
milliamperes of sink current.
OUTPUT
B
...
I/)
EACH RECEIVER
INPUTS
B TE PE
H
L
L
H
L
H
X
L
H
L
H
H
X
L
X
H
X
X
L
X
zt
zt
x'
X
L
Q)
>
OUTPUT
'ii)
D
L
H
(,)
Q)
-...
a:
I /)
Z
Z
Q)
>
'':::
C
H = high level. L = low level. X = irrelevant.
Z = high-impedance state,
tThis is the high-impedance state of a normal 3-state
output modified by the internal resistors to Vce and
ground.
Q)
c::
::J
z
o
i=
«
~
a:::
oLL
An active turn-off feature has been incorporated
into the bus-terminating resistors so that the
device exhibits a high impedance to the bus
when Vee = O. When combined with the
SN75ALS161 or SN75ALS162 management
bus transceiver, the pair provides the complete
16-wire interface for the IEEE 488 bus.
Z
w
(.,)
z
>
c
«
The SN75ALS 165 is manufactured in a 20-pin
package and is characterized for operation from
ooe to 70 oe.
«
Copyright © 1986, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-471
SN75ALS165
OCTAL GENERAL"PURPOSE INTERFACE BUS TRANSCEIVER
logic symbol t
ADVANCE
INFORMATION
logic diagram (positive logic)
PE (11)
TE
01
02
-
(1)
'"v
~~
(19)
"'-
'f
'f
B3
84
r-
S"
.
CD
...::...en
C
03
B6
04
l"f
(16)
"flo(
(15)
rl..
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
V Designates 3-5tate outputs.
-
05
06
....
(14)
CD
...
07
DB
6
.....,
1
(5)
A
1
(6)
'I
...
....., 1
(7)
(12)
........, 1
IB)
2
."
o
1
(9)
'f
J.,
EQUIVALENT OF ALL INPUT/OUTPUT PORTS
vcc-------.------9kn
NOM
INPUT
l:J
3:
~
o
2
4-472
83
84
85
86
GNO--~--_4----_4-
Driver output Req = 30 11 NOM
Receiver output Req = 110 0.. NOM
Circuit inside dashed lines is on the driver outputs only.
-If
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
87
rl..
schematics of inputs and outputs
EQUIVALENT OF ALL CONTROL INPUTS
(4)
L('
1
<
»2
om
B2
(13)
en
l>
c
(3)
'f
CD
()
<"
CD
~1
'f
CD
:tI
~1
.....,
B8
B1
(17)
B7
~ Designates passive-pullup outputs.
(2)
'I
B5
II
~l
.....,
(1B)
8B
SN75ALS165
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
ADVANCE
INFORMATION
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Low-level driver output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 mA
Continuous total dissipation at (or below) 25 DC free-air temperature (see Note 2):
OW package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1125 mW
J package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1375 mW
N package ........................................................ 1150 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 DC to 70 DC
Storage temperature range ......................................... - 65 DC to 150 DC
Lead temperature 1,6 mm (1/16 inch) from the case for 60 seconds: J package. . . . . . . . .. 300 DC
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: OW or N package . . .. 260 DC
NOTES: 1. All voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, derate the OW package to 720 mW at 70 0 e at the rate of 9.0 mw/oe, derate
the J package to 880 mW at 70°C at the rate of 11.0 mw/oe, and derate the N package to 736 mW at 70°C at the rate
of 9.2 mw/oe.
4
f
~
recommended operating conditions
MIN
4.75
Supply voltage, Vee
Low-level output current, IOL
MAX
UNIT
5
5.25
V
(,)
V
V
mA
-.
2
High-level input voltage, VIH
Low-level input voltage, VIL
High·level output current, IOH
NOM
0.8
-5.2
-800
Bus ports with pullups active
Terminal ports
Bus ports
Terminal ports
0
Operating free-air temperature, TA
~A
'G)
CD
a:
I I)
CD
>
';::
48
16
mA
Q
70
°e
c
::J
CD
z
o
t=
C
C
~
Z
(')
m
-Z
.."
o
:D
s:
l>
::!
o
z
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 866012 - DAllAS. TEXAS 76285
35
-50
42
52
30
V
V
3.7
1.5
-3.2
+2.5
-3.2
2.6
2.5
40
-75
-125
56
70
V
mA
~A
mA
mA
pF
ADVANCE
INFORMATION
SN75ALS165
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
switching characteristics over recommended range of operating free-air temperature (unless otherwise
noted), Vee - 5 V
PARAMETER
tpLH
tpHL
tPLH
tpHL
tpZH
tpHZ
tpZL
Propagation delay time,
low-to-high-Ievel output
Propagation delay time,
high-to-Iow-Ievel output
Propagation delay time,
low-to-high-Ievel output
Propagation delay time,
high-to-Iow-Ievel output
Output enable time to high level
Output disable time from high level
tpLZ
tpZH
Output enable time to low level
Output disable time from low level
Output enable time to high level
tpHZ
tpZL
tpLZ
Output disable time from high level
Output enable time to low level
Output disable time from low level
ten'
Output pull-up enable time
Output pull-up disable time
tdis
FROM
Terminal
Bus
TO
TEST CONDITIONS
CL = 30 pF,
See Figure 1
Bus
CL = 30 pF,
See Figure 2
Terminal
TE
Bus
CL=15pF,
See Figure 3
TE
Terminal
CL=15pF,
See Figure 4
PE
CL,= 15pF,
See Figure 5
Terminal
MIN
Typt MAX
UNIT
10
20
12
20
5
10
7
14
11
3
20
10
35
20
ns
ns
8
20
20
20
20
3
4
10
12
ns
ns
ns
18
5
5
8
9
II
t!
>
CD
'ii)
U
CD
a::
~
CD
t All typical values are at T A = 25 ·C.
>
'C
Q
CD
c
::::i
z
i=
o
~
a:
ou.
"~
Z
w
Z
Q
·ai
()
G)
> .......;.::.-.....---<.--OUTPUT
--...
~
en
G)
>
.iI:
Q
G)
r:::
::::i
VOLTAGE WAVEFORMS
TEST CIRCUIT
FIGURE 5. PE·TO·BUS PULLUP ENABLE AND DISABLE TIMES
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ,; 1 MHz, 50% duty cycle, tr ,; 6 ns,
tf ,;6 ns, Zout = 500.
B. CL includes probe and jig capacitance.
z
o
i=
c
...
~:::I
o
II
r-
s·
CD
..........
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
1:I:
1.0
o
:c"
CD
o
-S
i>
0.4
&
:::I
0_3
0
"ii
..
>
I\.
-10 -lS -20
....
~
0.2
....0
.1\.
....I
"',
/
c;J
/
/
L
>
o
-2S -30 -3S -40
o
10
FIGURE 6
20
TERMINAL OUTPUT VOLTAGE
vs
BUS INPUT VOLTAGE
:c"
CD
4.0
3.S
:t>
c
<
:t>
>I
..
&
:::I
m
>
:2
I
2.0
:::I
0
-
3.0
1lI 2.S
:2
(')
VCC=S V
No load
TA = 2SoC
&
~
l_S
i
VT_
VT+
J
0
1.0
O.S
."
o
:x:J
3:
:t>
o
o
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VI-Input Voltage-V
FIGURE 8
:::!
o
:2
4-478
30
FIGURE 7
CD
V
40
so
IOL -Low-Level Output Current-mA
n
...en
/
/
0.1
0
IOH-High-Level Output Current-mA
"i
CD
/
:0
~ o_s
...c
tC=SIV
O.S r---- TA = 2SoC
.
'\
_S!'
:>I
&
'\
2.0
1.S
Vdc=SIV
TA=2S0C-
'\
"ii
:;
0.6
,
2.5
....
1:.
TERMINAL LOW-LEVEL OUTPUT VOLTAGE
vs
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DAl.L.AS, TeXAS 76266
60
ADVANCE
INFORMATION
SN75ALS165
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
TYPICAL CHARACTERISTICS
BUS HIGH·LEVEL OUTPUT VOLTAGE
vs
BUS HIGH·LEVEL OUTPUT CURRENT
BUS LOW-LEVEL OUTPUT VOLTAGE
vs
BUS LOW-LEVEL OUTPUT CURRENT
4
>I
&
:J
0
3
>
...
=
0=
So
..
2
Oi
0.6
" I""
VCC'= S V
TA = 2SoC
Vee=SV
TA = 2SoC
>I
.'"
:J
0
>
...
=
=
~
."
J:
I
J:
0
0.4
So
r\.
..J
'\
0
Oi
...
0.3
;i:
0.2
'\.
0
..J
I
..J
>
>
o
-'0
-20
VV
..J
0
o
//
O.S
-30
"""
-40
-60
/
•
./
V
...rn
CI)
0.'
>
'iii
o
-SO
VV
/
CJ
o
CI)
10
IOH-High-Level Output Current-mA
20 30
40
SO 60
a:
--
70 80 90 100
~
IOL -Low-Level Output Current-mA
CI)
>
''::
FIGURE '0
FIGURE 9
C
BUS OUTPUT VOLTAGE
CI)
c
::::i
vs
TERMINAL INPUT VOLTAGE
Vce = S V
No load
TA = 2SoC
::r
3~~---+--~--~--+---~-+--~
2
t
o
o
>
...
i=
oLL
Z
OL-~
0.9
__-L__~__L-~__- L__L--..I
1.0
,.,
'.2
'.3
'.4
'.S
VI-Input Voltage-V
FIGURE 11
'.6
'.7
W
(.)
2
C
"Gi
H - high level. L - low level,
Z ~ high impedance (off),
x = irrelevant
CJ
CD
~
High-impedance inputs maintain input currents low. less than 1 microampere for a high level and less than
100 microamperes for a low level. Complementary control inputs, G and G, allow these devices to be enabled
at either a high input level or low input level. The SN75ALS 192 is capable of data rates in excess of 20
megabits per second and is designed to operate with the SN75ALS193 quadruple line receiver.
The SN75ALS192 is characterized for operation from OOC to 70°C.
logic symbol t
logic diagram (positive logic)
~1
G
(4)
EN
G
lA (11
"J
"J
(21
(31
(61
2A
3A
4A
(71
(91
(15)
(51
(101
(111
(141
(131
lY
lZ
2Y
2Z
3Y
3Z
4Y
4Z
tThis symbol is in accordance with ANSI/IEEE Std 91·1984 and
lEe Publication 617·12.
PRODUCTION DATA documBnts contain
information currant as of publicltion dlte.
:;od~:.:onl~;;I1::::ifi::~~~~s·r:.~:::~
Praductlon processing dolS not nlcl.sarir,
includB lasting of an parameters.
-
a:
Copyright @) 1985, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-481
CD
>
";::
C
CD
r::
:::::i
SN75ALS192
QUADRUPLE DIFFERENTIAL LINE DRIVERS
schematics of inputs and outputs
EQUIVALENT OF EACH
EQUIVALENT OF EACH
DATA (AI INPUT
ENABLE INPUT
TYPICAL OF EACH OUTPUT
---<-------......--VCC
INPUT---<_.....-t
I NPUT---<_......,
OUTPUT
r-
:::r
CD
o
:::!.
absolute maximum ratings over operating free-air temperature ranga (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage, VI . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Output off-state voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
D package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 950 mW
J package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1000 mW
N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 875 mW
Operating free-air temperature range ...................................... ooC to 70°C
lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............ 300°C
lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package ... '" .. 260°C
~
iil
iCD
(')
CD
~.
iil
NOTES: 1. All voltage values except differential output voltage VOD are with respect to netw~rk ground terminal.
2. For operation above 25°C free-air temperature, refer to the Dissipation Derating Table. In the J package, SN75ALS192 chips
are glass mounted.
DISSIPATION DERATING TABLE
PACKAGE
D
J (Glass mount)
N
4-482
TA - 25°C
POWER RATING
DERATING
FACTOR
ABOVE
950 mW
7.6 mw/oe
1000 mW
S.2 mw/oe
TA
25°C
2Soe
875 mW
7.0 mw/oe
25°C
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
TA - 70°
POWER RATING
60SmW
656 mW
560 mW
SN75ALS192
QUADRUPLE DIFFERENTIAL LINE DRIVERS
recommended operating conditions
Supply voltage, Vee
High-level input voltage, VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
2
V
Low-level input voltage, VIL
High-level output current, 10H
0.8
-20
mA
20
mA
70
°e
Low-level output current, IOL
Operating fre.a-air temperature. T A
0
V
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
Input clamp voltage
Vee
VOH High-level output voltage
VOL Low-level output voltage
Vee
VIK
Vee
=
=
=
4.75 V, II = -18 mA
4.75 V, 10H = -20 mA
=
=
=
5.25 V
MAX
UNIT
-1.5
V
0.5
V
2.5
V
4.75 V, 10L - 20 mA
I Vo = 0.5 V
10Z
Off-state (high-impedance state) output current
Vee
II
Input current at maximum input voltage
Vee
IIH
High-I.evel input current
Vee
IlL
Low-level input current
Vee - 5.25 V, VI - 0.4 V
lOS
Short-circuit output current+
Vee
lee
Supply current lall drivers)
Vee - 5.25 V, All outputs disabled
=
MIN Typt
I Vo
5.25 V, VI
5.25 V, VI
-20
_ 2.5 V
=
=
20
7 V
2.7 V
-30
5.25 V
~A
mA
20
~A
0.2
mA
-150
mA
45
mA
26
•
...
II)
0.1
G)
>
'iii
u
G)
-...
a:
I I)
tAli typical values are at Vee = 5 V, TA = 25°e.
:t:Not more than one output should be shorted at a time, anq duration of the short-circuit should not exceed one second.
G)
>
'':
switching characteristics. Vee - 5 V. TA
o
-= 25°e (see Figure 1)
G)
PARAMETER
TEST CONDTIONS
MIN
TYP
MAX
UNIT
tPLH Propagation delay time, low-to-high-Ievel output
6
13
tpHL Propagation delay time. high-to-Iow-Ievel output
9
14
ns
3
6
ns
ns
Output-ta-output skew
tpZH Output enable time to high level
tpZL Output enable time to low level
tpHZ Output disable time from high level
tpLZ Output disable time from low level
eL
=
30 pF,
SI and S2 open
ns
RL - 75 Il
11
15
RL - 1801l
16
20
ns
8
15
ns
18
20
ns
eL
=
10 pF,
S 1 and S2 closed
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75285
c
::::;
4-483
SN75ALS192
QUADRUPLE DIFFERENTIAL LINE DRIVERS
PARAMETER MEASUREMENT INFORMATION
INPUTA
ENABLE
.1,.3V
\1:;;--3V
~
(See Note Al
I
~tPLHII
OV
~
1"-- VOH
I
OUTPUT V :
I
I Skew+! I'tPHLj4------+f
OUTPUT Z
:.
I
---..r --------"" 'L"'
G
(See Note B)
I
VOL
yVOH
WAVEFORM 2
Slopen,
(See Note C)
52 closed
I
I Skew~
tPLz*"--+I
(See Note C)
~.---------J,--VOL
-~
4.5 V
I Slelosed.
1.5V
I S20pen
I
~tPZH----"
WAVEFORM 1
3V
1.5 V
~'--------OV
I
---+----""'\'1- -
1.5 V
!.-tPLH--.J
\,.5 V
J"\1.5 V
ENABLEG---JI
I.--tpZL--+I
¥I __ £
I SI and
I
T
S2 closed
tpHZ~
~1.5V
.---VOL
0.5 V
\~~--- VOH
C
T': ~ ""
I
I
I
0
v~fand
"" 1.5 V
52 closed
•
PROPAGATION DELAY TIMES AND SKEW
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
TEST
POINT
SI
CL
75 !l
(See Note 0)
J
Vec
T
'80!l
S2
TEST CIRCUIT
NOTES: A. When measuring propagation delay times and skew, switches 51 and S2 are open.
B. Each enable is tested separately.
C. Waveform 1 is for an output with'internal conditions such that the output is low except when disabled by the enable inputs.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the enable inputs.
D. CL includes probe and jig capacitance.
E. All input pulses are supplied by generators having the following characteristics: PAR s 1 MHz, Zout :::= 50 n, tr S 15 ns, and
tf s 6 ns.
FIGURE 1. SWITCHING TIMES
4-484
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN75ALS192
QUADRUPLE DIFFERENTIAL LINE DRIVERS
TYPICAL CHARACTERISTICS
y OUTPUT VOLTAGE
Y OUTPUT VOLTAGE
vs
vs
DATA INPUT VOLTAGE
DATA INPUT VOLTAGE
5.0
5.0
No Load
4.5 -Outputs Enabled
TA-25·e
4.0
::r
Vee=5V
4.5 Outputs Enabled
No Load
4.0
I
Vee = 5.5 V -
::r
Vee=5VI
Vee- 4.5 V -
3.5
r
&
~ 3.0
~
-TA=25·e
2.5
2.0
~
2.0
1.5
01,5
a
:::0
>
o·e-
I
~ 3.0
'+,
9o
TA
&
~
:::0
I
3.5
'.., 2.5
e-
TA = 70·e
>
1.0
1.0
0.5
0.5
o
o
o
0.5
1.0
1.5
2.0
3.5
3.0
...
II)
Q)
>
'iii
o
0.5
1.5
1.0
2.0
2.5
3.0
VI-Data Input Voltage":V
VI-Data Input Voltage-V
CJ
Q)
--...
a:
I I)
FIGURE 2
FIGURE 3
Q)
>
';::
vs
vs
ENABLE G INPUT VOLTAGE
ENABLE G INPUT VOLTAGE
Vee = 5.5 V
I
3.5
3~5
vee-~v
3.0
>I
..
E
Vee=4.5V
I
&
:I 2.5
~
~+'
'; 2.0
:::0
S
1.0
TA = 70·e-
I
2.5
TA = 25·e-
I
2.0
TA = o·e-
o
0.5
1.0
1.5
2.0
2.5
'-.".,1"..........
Vee=5V
VI =2V
RL = 470 n to Ground
See Note 3
0.5
3.0
o
o
0.5
1.0
1.5
2.0
2.5
3.0
VI-Enable G Input Voltage-V
VI-Enable G Input Voltage-V
FIGURE 5
FIGURE 4
NOTE 3: The A input is connected to
-........
0 1.5
I
0
> 1.0
VI =2V
RL = 470 n to Ground
See Note 3
TA = 25°e
0.5
o
3.0
So
:::0
9 1.5
~
Q)
c
::J
4.0
4.0
>
C
Y OUTPUT VOLTAGE
Y OUTPUT VOLTAGE
Vee
during the testing of the Y outputs and to ground during the testing of the Z outputs.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-485
SN75ALS192
QUADRUPLE DIFFERENTIAL LINE DRIVERS
TYPICAL CHARACTERISTICS
Z OUTPUT VOLTAGE
vs
ENABLE G INPUT VOLTAGE
Z OUTPUT VOLTAGE
vs
ENABLE G INPUT VOLTAGE
6
RL = ~70 n
See Note 3
TA = 2S·C
Vcc= S.S V
VCC= SV
S
VCC = 4.S V
>I
.,
'"
:I
4
;
3
~
6
t~ VCC
-
I
0
r-
S
>I
.,
'"
:I
~...
:::J
TA = 70·C'-.
4 I--TA = O·C
'-...
TA = 2S·C'-...
3
l'-
e
~
0
Vce = S V
RL = 470 n to VCC
See Note 4
:::J
90
2
>
2
>
5'
..<'
.
CD
C
o
CD
o
VI-Enable G Input Voltage-V
en
::D
1.0
1.S
O.S
2.0
2.S
VI-Enable G Input Voltage-V
FIGURE 6
FIGURE 7
HIGH·LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
S.O ,--.....,---,--,-----,--,--,--,---,
VCC=SV
> 4.S IOH = -20 mA+--~-t--f---f--l
I
See Note 3
HIGH-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.0
CD
n
CD
.
<'
CD
en
S.O
=f
See Note 3
4.S r-TA = 2SOC
& 4.0~~~~r--f---f---f---f---f---t
t
~...
3.S ~+=t=+=t==+==t==tl
3.0 f---f--f--f---f---f---f--I--t
~ 3.S
o-.;"
2.S f---t--+--j---t--t--t--+--1
o-.;
~
s.
.s
2.0 f - - - t - + - - I - - l - - + - - t - - t - - - t
:::J
~ 3.0
2.S
5 1.0 f----If---f--+--+-+--j--+---l
5 1.0
O.S f - - - t - + - - t - - l r - - + - - t - - t - - t
0L-~_-L
o
10
20
__~~L--L_~__L-~
30
40
SO
60
70
80
O.S
o
o
TA-Free-Air Temperature-·C
4-486
I
I
I
I
Vce= 4.S V r---
.'"
'\l"\ "\
1"\"\ '\
-100
-80
-20
-60
-40
IOH-High-Level Output Current-mA
FIGURE 9
FIGURE 8
NOTES:
I
.=Vec=S"._ : - -
";><'\ '\
I
>
VCC=S.SV,_ - ,
t\." ~ : \
3 2.0
l:.
~ 1.S
>
I\.
I\. r\.
r-- r\."
I\.
I'\.
...
l:.
~ 1.S f---f--f--f--f--f--f--f---I
I
--
4.0
3. The A input is connected to Vee during the testing of the V outputs and to ground dUTing the testing of the Z outputs.
4. The A input is connected to ground during the testing of the Y outputs and to Vee during the testing of the Z outputs.
TEXAS . .
INSTRUMENTS
pdST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SN75ALS192
QUADRUPLE DIFFERENTIAL LINE DRIVERS
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
:r
~
~
~
i
vs
vs
FREE-AIR TEMPERATURE
OUTPUT CURRENT
0_5 r---"T---.---,--------,,-----,----,----,-------,
VCC = 5 V
IOL = 20 mA----j----1----1----1----1-----j
See Note 4
0_4~-r_-r_-~-~-~-~-~~
0_3~-~-~-~-~-~-~-~~
::s
>
I
1_0
See Note 4
0_9 -TA=25°C
i
0_8
~
0_7
e.
0_6
...
o
3 0_2~-~-~-~-~-~-~-~~
~
/
II ~ V
.5
0.4
.3
0.3
~
>
~
-;;
~ 0_1~-~-~-~-~-~-~-~~
I
10
20
30
40
50
60
70
0_1
/
o
o
O~~L-~-~--L-~-~-~~
o
~
~~
;i:
5 0 -2
80
TA-Free-Air Temperature-oC
>
'i
10 20 30 40 50 60 70 80 90 100
IOL -Low-Level Output Current-mA
>
::s
'fu
!d
>
vs
SUPPLY VOLTAGE
C
Gro~nded
:;
INPUTS GROUNDED
10
o
A Inlputs 6pen ~r
Outputs Disabled
No Load
TA = 25°C
35
20
a:
'':
SUPPLY CURRENT
40
30
-...
II)
vs
40
(,)
II)
I I)
Outputs Enabled
70 No Load
TA = 25°C
-a
CL
II)
SUPPLY VOLTAGE
:;
II
...
FIGURE 11
80
u
~
VCC=5_5V-
II)
SUPPLY CURRENT
f
;..---
~~
FIGURE 10
.!.c
I
Vcc = 5 V7 'r--tlf
::s
~ 0_5
18
2A
-..
CD
a:
28
3A
description
The SN75ALS193 is a monolithic quadruple line
receiver with three-state outputs designed using
Advanced Low-Power Schottky technology.
This
technology
provides
combined
improvements in bar design. toolif'1g production.
and wafer fabrication. This. in turn. provides
significantly less power requirements and
permits much higher data throughput than other
designs. The device meets the specifications of
EIA Standards RS-422-A and RS-423-A. It
features three-state outputs that permit direct
connection to a bus-organized system with a
Fail-Safe design that ensures the outputs will
always be high if the inputs are open.
UI
(11) 3Y
CD
3B
4A
>
';:
(131 4Y
C
48
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
logic diagram (positive logic)
The device is optimized for balanced multipoint
bus transmission at rates up to 10 megabits per
second. The input features high input
impedance. input hysteresis for increased noise
immunity. and an input sensitivity of
± 200 millivolts over a common-mode input
voltage range of - 7 to 7 volts. It also features
active-high and active-low enable functions that
are common to the four channels. The
SN75ALS 193 is designed for optimum
performance when used with the SN75ALS 192
quadruple differential line driver.
z
i=
«
::e:
a:
0
(31 1y
(51 2y
0
LL
Z
(111 3y
W
(.)
Z
(131 4y
«
>
c
«
The SN75ALS193 is characterized for operation
from ooe to 70 oe.
Copyright © 1984, Texas Instruments Incorporated
ADVANCE INFORMATION documents .ontaln
~-=:::=rO::h=Or~~:;:~p:a:·C=::~~':;!
dots and other specifications are subjaot to change
without notl.e.
CD
C
::;
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-489
'SN75ALS193
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3·STATE OUTPUTS
ADVANCE
INFORMATION
FUNCTION TABLE lEACH RECEIVER)
DIFFERENTIAL
A-B
VID ;;,; 0.2 V
-0.2 V
H
L
X
7
Z
< VIO < 0.2 V
VID s -0.2 V
X
ENABLES
G
G
X
H
X
L
X
H
X
L
X
H
L
X
L
H
OUTPUT
y
H
H
?
7
L
L
Z
= high level
= low level
= irrelevant
= indeterminate
= high·impedance (off)
schematics of inputs and outputs
r-
:r
II)
c
:::!.
EQUIVALENT OF EACH A OR B INPUT
VCC------~~--.---
EQUIVALENT OF G OR G INPUTS
VCC-------e--~~
3 kll
NOM
<
iii
-
TYPICAL OF ALL OUTPUTS
VCC
50 Il
NOM
II)
::D
II)
~
:c!'
18 kll
NOM
INPUT
OUTPUT
II)
INPUT
iii
300 kll
NOM
VeclA)
or
GND IB)
l>
c
GND-L--.--e~----
- - - - - -..... -....-
~2
GND
CO)
m
2
."
o
:xl
s:
l>
:::!
o
2
4·490
TEXAS •
INSTRUMENTS
POST OFFICE BOX 855012 • DAUAS, TEXAS 76266
GND
ADVANCE
INFORMATION
SN75ALS193
QUADRUPLE DIFFERENTIAL LINE RECEIVER.
WITH 3·STATE OUTPUTS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage, A or B inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 15 V
Differential input voltage (see Note 2) ......................................... ± 15 V
Enable input voltage ................. ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Low-level output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 3) ....... 1025 mW
Operating free-air temperature range ...................................... OoC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds ...................... 300°C
NOTES:
1. All voltage values, except differential input voltage, are with respect to network ground terminal.
2. Differential-input voltage is measured at the noninverting input with respect to the corresponding inverting input.
3. For operation above 25°C free-air temperature, derate to 656 mW at 70°C at the rate of 8.2 mW/oC. In the J package,
SN75ALS193 chips are glass mounted.
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
±7
V
±12
V
Common-mode input voltage, VIC
Differential input voltage, VIO
II
...
II)
CD
>
'Q)
U
CD
High-level output current, IOH
-400
~A
Low·level output current, IOL
16
mA
-...
70
°c
'0:::
2
High-level input voltage, VIH
Low-level input voltage, VIL
V
0.8
0
Operating free-air temperature, T A
V
a:::
I I)
CD
>
o
CD
C
:::;
z
o
i=
«
~
a::
oLa.
~.
W
CJ
Z
~
«
c
..If
TEXAS
INSTRUMENTS
poST OFFICE BOX 865012 • DAUAS. TEXAS 75265
4-491
SN75ALS193
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
ADVANCE
INFORMATION
electrical characteristics over recommended range of common-mode input voltage. supply voltage.
and operating free-air temperature (unless otherwise noted)
TEST CONDITIONS
PARAMETER
•
!::
::s
CD
.:c.
!!.
C
CD
::D
CD
()
CD
.
ci!"
VT+
Positive-going threshold voltage
VT-
Negative-going threshold voltage
Vhys
Hysteresis §
VIK
Enable-input clamp voltage
11- -18 mA
VOH
High-level output voltage
VIO = 200 mV,
VOL
low-level output voltage
VID = -200 mV
10Z
High-impedance-state output current
TYpt
MAX
UNIT
200
mV
-200;
mV
120
Line input current
IIH
High-level enable-input current
III
Low-level enable-input current
IOH = -400 pA
Short-circuit output current
Supply current
3.6
. VCC = 5.25 V
0.5
20
20
Vo - 0.4 V
0.7
VI - 15 V
VI - -15 V
-1.0
1.2
-1.7
20
VIH = 2.7 V
100
VIH - 5.25 V
-100
Vil = 0.4 V
VIO -'3 V,
Va - 0,
See Note 5
Outputs disabled
V
V
0.45
10l - 16 mA
Vo = 2.4 V
Input resistance
lOS
2.7
IOl - 8 mA
See Note 4
ICC
mV
-1.5
Other input at 0 V,
II
V
~A
mA
~A
~A
12
18
-15
-78
-130
mA
22
35
mA
kll
t All typical values are at VCC = 5 V, T A = 25 ·C .
t: The algebraic cOlJvention, in which the less positive limit is designated minimum, is used in this data sheet for threshold voltage levels only.
§ Hysteresis is the difference between the positive-going input threshold voltage, VT +, and the negative-going input threshold voltage,
VT-·
NOTES: 4. Refer to EIA Standard RS-422-A and RS-423-A for exact conditions.
5. Not more than one output should be shorted at a time and the duration of the short-circuit should not exceed one second.
CD
C/l
MIN
switching characteristics.
Vee -
5
V.
TA - 25 0 e
tPlH
PARAMETER
Propagation delay time, low-to-high-Ievel output
tpHl
Propagation delay time, high-to-Iow-Ievel output
tpZH
Output enable time to high level
tpZl
Output enable time to low level
tpHZ
Output disable time from high level
tplZ
Output disable time from low level
4-492
TEST CONDITIONS
VIO - -2.5 V to 2.5 V, Cl = 15 pF,
See Figure 2
C;:l = 15 pF,
Cl = 15 pF,
See Figure 3
See Figure 3
TEXAS'.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
MIN
TYP
MAX
15
22
ns
15
22
ns
13
25
11
25
13
15
25
22
UNIT
ns
ns
SN75ALS193
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3·STATE OUTPUTS
ADVANCE
INFORMATION
PARAMETER MEASUREMENT INFORMATION
I
IOH
+H
2V----'
FIGURE 1. VOH, VOL
INPUT~~V---2.5V
::J~ v
>-+-.-OUTPUT
tPLH..j
ItI
~ -2.5 V
-.I
III
~
I
OUTPUT
1.3V
•
...
If-tPHL
11----voH
I
~
"Qj
1.3V
U
CD
VOL
a:
-...
...CD
=
III
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES:
A. The input pulse is supplied by a generator having the following characteristics: PRR
50 lI,t r S 6 ns, tf S 6 ns.
s
1 MHz, duty cycle
s
50%, Zout
=
>
";:
C
CD
B. Cl includes probe and jig capacitance.
c
FIGURE 2. tPLH, tPHL
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
::::i
4·493
SN75ALS193
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3·STATE OUTPUTS
ADVANCE
INFORMATION
PARAMETER ,MEASUREMENT INFORMATION
-+t
G
I
I
II I
II
I I
SO%
EN~BLE 1.3 V
I
See Note C
I
10%
10%
G
10%
I I
I:I
1.3V
SO%
1.3V
OV
~l;.;;O.;,;%:....._OV
3V
--S""0.".,%--3V
I,
l __ --OV
:l----OV
1 Sl closed
I S2 closed
.
h-=-~VOH
.!~0.5V
tPHZ-4---+i
~1.4 V
I,
OUTPUT
S2 open
~
VOLTAGE WAVEFORMS FOR tpHZ. tpZH
TEST
POINT
C
:::!,
<
CD
;
::rJ
CD
n
...<'
FROM OUTPUT - . _.......-+-11---.
UNDER TEST
CD
(II
CL
See Note A
r
LOAD CIRCUIT
NOTES: A. CL includes probe and jig capacitance.
B. A" diodes are 1N3064 or equivalent.
C. Enable G is tested with G high; G is tested with Glow.
FIGURE 3. tpHZ. tpZH. tpLZ. tpZL
4-494
tpLZ
V
~I.
~I
~ 1.4 V
I
- i.
VOLTAGE WAVEFORMS FOR tPLZ. tpZL
CD
CD
1.3
VOL
---£.0.5 V
Sl closed
S2 closed
S'
5 ns
ENABLE
I
I.
OUTPUT
I
1
II
I
I4-s
I
I+-s 5 ns
I
-1- - - - 3 V
SO% I
1.3 VI
I
I,
ENABLE
-+I
~s 5ns
I
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DAllAS, TEXAS 75265
ADVANCE
INFORMATION
SN75ALS193
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3·STATE OUTPUTS
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
5
4
>,
4
VIO = 200 mV
Vie = 0
RL - 8 kll to GNO
TA - 25°e
TA
TA
TA
3 TA
Vee - 5.5 V
>,
Vee - 5 V
cu
.
Vee - 4.5 V
CI
~ 3
o
-
125°e
70 0 e
,25°eooe
>-1--
TA - -55°e
CI
~
>
=
>
..
2
>
1
"
So
o",
o
0.
=
o, 2
~
Vee - 5 V
VIO - 200 mV
Vie - 0
RL = 8 kll to GNO
>,
0.5
1.5
2
Enable Voltage-V
2.5
o
o
3
I
0.5
FIGURE 4
5
Vee - 5.5 V
Vee - 5 V
Vee - 4.5 V
>,
I
VIO - -200 mV
Vie - 0
RL - 1 kll to Vee
TA - 25°e
3
--a:...
en
CD
>
C
CD
c:
:.J
~4
>
~
S
o
6.
=3
.. 3
~ '*"
l/
=
o, 2
o
>
I 2
o
>
o
o
3
-,I
-55°e
VTA - ooe
~ VTA - 25°el/ VTA - 70 0 e
>,
1!!
2.5
t)
';:
I,
14- TA -
5
~4
1.5
2
Enable Voltage-V
>
'G)
6
-'-
l!!
0.5
2.5
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
"0
o
o
en
CD
CD
FIGURE 5
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
6
1.5
2
Enable Voltage-V
I
II
...
l/
l/
-(A -
r
5oe
-
Vee - 5 V
VIO - - 200 mV
Vie - 0
RL - 1 kll to Vee
0.5
FIGURr:; 6
1.5
2
Enable Voltage-V
2.5
3
FIGURE 7
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-495
SN75ALS193
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
ADVANCE
INFORMATION
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
4
5
4
>
Vce - 5 V
V'C - -12 V to 12 V
10 - 0
TA - 25°C
>
I
&
:13
-,..
:r
CD
-
=
02
~
~2
I
o
>
]
VT-
VT+
.J:.
J:'" 1
I
J:
o
>
..c
~.
...
=
3
~
IOH - -400 p.A
~
I
&
1!
-
10H - 0
o
-200
til
:CD:a
-100
100
o
Vlo-Oifferentiallnput Voltage-mV
200
VCC - 5 V
VIO - 200 mV
V'C - 0
I
I
I
o
o 10 20 30 40 50 60 70
TA-Free-Air Temperature- °e
FIGURE 8
80
FIGURE 9
n
CD
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
~.
til
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
5
5
......
,,
,""
""- "
"
V,O - 200 mV
VIC - 0
TA - 25°C
" , t
.1
k":
1
~
J
f- VCC - 5.5 V
f-VCC - 5 V
f- Vce - 4.5 V
~
~~
~ '\
'\ '\
.'\
'\ ,,\l'\.
'\l'\.
FIGURE 10
TA
V- TA
~ ~ ~ TA
~~
r\."\: :-..
- ooC
- 25°C- 70o~_
,,~~
\ .~
"
-20
-40
-60
-80
-100
10H-High-Level Output Current-mA
-60
-80
-100
-20
-40
10H-High-Level Output Current-mA
4-496
,
Vee - 5 V
V,O - 200 mV
V'C - 0
FIGURE 11
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TeXAS 75265
SN75ALS193
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3·STATE OUTPUTS
ADVANCE
INFORMATION
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
0.4
VCC - 5 V
VIO - -200 mV
VIC - 0
>
.,I
SO.3
'0
>
;
...
~
10 - 8 mA
•
0.2
~
!l
-
~
o
I' 0.1
....
o
>
o
o
I
10 = 0
...
10
20
30
40
50
60
!II
Q)
>
·iii
u
Q)
70
--a:...
80
! II
T A - Free-Air Temperature- °C
Q)
>
FIGURE 12
.~
Q
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.8
>
.,I
~CC l4.5 IV_
0.7 r--VCC - 5 V _ _
VCC - 5.5 V_
:1:'0.6
:: 0.5
::s
~
o
1 0 .2
....
o
>
/'
0.1
o
o
~
TA - 250C-:::J
TA - ooC .......
&
!! 0.6
!
'0
>
;
h~
5
00.4
'ii
>
!l 0.3
fA .170 0/ ,
~ 0.7
~~
-a
0.5
~~
~
~
~
r
0.3
o
I'
0.2
6 0.1
VIO - -200 mV
VIC - 0
TA - 25°C
>
80
..II
'fj
~~
So
::s
00.4
'ii
10
20
30
40
50
60
70
10L -Low-Level Output Current-mA
,I
0.8
I J
N JI
Q)
r:
:::i
~
00
V
~
~
VCC = 5 V
VIO - -200 mVVIC = 0
10 20
30 40
50
60
70
10L -Low-Level Output Current-mA
80
FIGURE 14
FIGURE 13
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-497
SN75ALS193
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3-STATEOUTPUTS .
ADVANCE
INFORMATION
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
50
c(
~
III
r-
S'
~
~ 15
10
,
CD
~
C
V
::3,
~
U;
2
.,/
3
:lJ
5 Vi
VCC - 4.5 V
j
L
'f 10
(J
};
VID - -200 mV
Outputs Enabled
5
4
5
6
7
o
10 - 0
o
8
VCC-Supply Voltage-V
10
20 30
40 50 60 70
TA-Free-Air Temparature- °C
FIGURE 15
CD
!
(J
~ENABLED
(J
20
~ 15
DISABLED')
§' 20
-
.!.
/
UI
~CC
1
h
25
J.VCC -I 5.5I.V
25
35
~::I 30
(J
30
VID - - 200 mY
45 VIC - 0
10 - 0
40 TA - 25°C
80
FIGURE 16
n
CD
<'
SUPPLY CURRENT
vs
FREQUENCY
SUPPLY CURRENT
vs
DIFFERENTIAL INPUT VOLTAGE
CD
U;
30
40
I 1
35
Vcc - 5.5 V
I
I
Vcc - 5 V
25
III'
Vcc .:,"S'V
VI - ± 1.5 V Square Wave
CL - 15 pF
Four Channels Driven
TA - 25°C
Vcc - 4.5 V
5
o
5
o
100
-100
VID-Differentiallnput Voltage-mV
200
o
10 k
100 k
1M
10 M
f- Frequency- Mz
FIGURE 17
4-498
V
~
10 - 0
Outputs Enabled
VIC - 0
TA - 25°C
-200
II
FIGURE 18
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
100 M
ADVANCE
INFORMATION
SN75ALS193
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3·STATE OUTPUTS
TYPICAL CHARACTERISTICS
INPUT RESISTANCE
vs
FREE-AIR TEMPERATURE
INPUT CURRENT
vs
INPUT VOLTAGE
30
3
25
2
-
.~
TA - 25°e
"iii
o
o
10
20 30
40
50
60
70
TA-Frae-Air Temperature- °e
(J
(I)
-3
-20 -15 -10 -5
0
5
10
15
VI-Input Voltage to GNO-V
80
FIGURE 19
30
.
.
E
j::
'"
..
t pILZ ,,tpHZ ....
, tPZH
15
c
:;:
.~ 10
~
i!
~
III
.-~
~
tPHZ
J
I---
~
rr
tPzi. ---l
~
1---1tPHL.....J
tPZH
>
";:
C
CI)
s:::::
:::i
20
tPLH,
c
I 20
I I)
PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE
I
Vee - 5 V
eL-15pF
c
I
.
[\
18
eL - 15 pF
TA = 25°e
16
E
j:: 14
>
~
~
12
c
10
-...
a:
(I)
FIGURE 20
SWITCHING CHARACTERISTICS
vs
FREE-AIR TEMPERATURE
25
20
tP~L_
tpLH-
Q
II
'!.
...
£I
...
.",
"'0
~
5
8
6
4
2
o
o
10
20
30 40
50
60
70
TA-Free-Air Temperature- °e
80
o
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
Vee-Supply Voltage-V
FIGURE 22
FIGURE 21
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-499
4-500
SN75ALS194
QUADRUPLE DIFFERENTIAL LINE DRIVER
WITH 3-STATE OUTPUTS
02917, OCTOBER 1985-REVISEO OCTOBER 19B6
D, J, N PACKAGE
•
Meets EIA Standard RS-422-A
•
High-Speed ALS Design
•
3-State TTL-Compatible
•
Single 5-V Supply Operation
•
High Output Impedance in Power-Off
Condition
•
Two Pairs of Drivers Independently Enabled
•
Designed as a Replacement for the MC3487
with Improvements: ICC 50% Lower.
Switching Speed 30% Faster
(TOP VIEWI
lA
Vee
1Y
4A
4Y
4Z
3,4EN
3Z
3Y
3A
lZ
1,2EN
2Z
2Y
2A
GNI)
FUNCTION TABLE (EACH DRIVER I
OUTPUT
INPUT
description
OUTPUTS
ENABLE
Y
Z
H
H
L
H
This quadruple complementary-output line driver
H
H
L
L
is designed for data transmission over twistedHigh-Impedance
High-Impedance
X
L
pair or parallel-wire transmission lines, It meets
the requirements of EIA Standard RS-422-A and
H ~ TTL high level, L ~ TTL low level, X ~ irrelevant
is compatible with 3-state TTL circuits.
Advanced Low-Power Schottky technology provides high speed without the usual power penalty. Standby
supply current is typically only 26 milliamperes. while typical propagation delay time is less than
10 nanoseconds and enable/disable times are typically less than 16 nanoseconds.
II
II)
~
CD
>
"iii
(J
CD
-a:
I I)
~
High-impedance inputs keep input currents low. less lhan 1 microampere for a high level and less than
100 microamperes for a low level. The driver circuits can be enabled in pairs by separate active-high enable
inputs. The SN75ALS194 is capable of data rates in excess of 10 megabits per second and is designed
to operate with the SN75ALS195 quadruple line receiver.
The SN75ALS194 is characterized for operation from
logic symbol t
ooe
to 70 o e.
CD
>
";:
C
logic diagram (positive logic)
(21 lV
(31
lZ
(61
2Y
(51
2Z
(101 3Y
(111 3Z
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
(141 4Y
(131
D--";';";';"'4Z
PRODUCTION DATA documents contein in'ormation
current as of publi.ation data. Products con'orm to
specifications per the tarms of Taxas Instruments
:'::~:~~i~8{nr:I~'~ ~:\:~:: :I~O:::~:S~S not
Copyright @ 1985, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TEXAS 75265
CD
s:::
:::i
4-501
SN75ALS194
QUADRUPLE DIFFERENTIAL LINE DRIVER
WITH 3-STATE OUTPUTS
schematics of inputs and outputs
EQUIVALENT OF EACH
EQUIVALENT,OF EACH
DATA (A) INPUT
ENABLE INPUT
EQUIVALENT OF EACH
OUTPUT
~~------.--VCC
I NPUT---
'Q)
VI = 2.7 V
50
~A
(J
II)
VI - 0.5 V
-200
~A
-140
mA
45
mA
-40
All outputs disabled
26
a:
--.
I I)
II)
t All typical values are at Vec = 5 V, TA = 25 ·e.
t aivool and alVoe I are the changes in magnitude of VOO and Voe, respectively, that occur when the input is changed from a high
>
';:
C
level to a low level.
CD
I::
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
::i
switching characteristics. Vee = 5 V. TA = 25°e
PARAMETER
TEST CONDTIONS
tPLH Propagation delay time, low-to-high-Ievel output
tpHL Propagation delay time, high-to-Iow-Ievel output
Output-to-output skew
tTO
Differential-output transition time
tpZH Output enable time to high level
tpZL Output enable time to low level
CL = 15 pF,
See Figure 1
CL - 15 pF,
See Figure 2
See Figure 3
CL = 50 pF,
tpHZ Output disable time from high level
tpLZ Output disable time from low level
MIN
TYP
MAX
6
9
13
UNIT
ns
14
ns
3.5
6
ns
8
14
ns
9
12
ns
12
20
ns
9
14
ns
12
15
ns
SYMBOL EQUIVALENTS
DATA SHEET PARAMETER
RS-422-A
Vo
Voa, Vob
I V OD11
VO
I V OD21
V t IRL = 100!l)
aivool
I IVtl -
Voc
-=l.
IVtl I
VOC
IVosl
alvocl
I Vos - Vos I
FIGURE 1. DRIVER VOD AND VOC
lOS
lisa I, Ilsb I
10
Ilxal, Ilxbl
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-503
SN75ALS194
QUADRUPLE DIFFERENTIAL LINE DRIVER
WITH 3·STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
~-------3V
INPUT.A1.5V
5V
GENERATOR
(Sea Nota AI
YOUTPUT
k L =15PF
I
:(Sea Nota BI
I
II
I
I
I
Skaw4-t
!oe-tPHL
Z OUTPUT
III
tPHL
--VOH
I,
(SaaNotaCI "::"
.
I. .1
I
r-
Y,.5V
•
3V'L _ _ _ _ _ _ ...1•
1\
~--~-------ov
I.tPLH~
200n
t--+---il.. S1
1.5V
--I
1.5V~
I
'----VOL
Skaw-t-t
.... tPLH--i
,~VOH
\1.5 V
1.57
~--------~
TEST CI RCUIT
-
-
.
-'VOL
VOLTAGE WAVEFORM
FIGURE 2. PROPAGATION DELAY TIMES
INPUT
r-\---3V
~OV
-..I
GENERATOR
(Saa Note AI
tTO....., ~ --: :-- tTO
OUTPUT
50n
L-__~__~____- L
3V-...... ·---'
CL = 15 pF
(Sea Nota BI
:.. _ _ _ _ _ oJ
!~!
OUTPUT ~
to%
10%
'll.
VOLTAGE WAVEFORMS
TEST CIRCUIT
FIGURE 3. DIFFERENTIAL·OUTPUT TRANSITION TIMES
NOTES: A. The input pulse is supplied by a generator having the following characteristics: tr S 5 ns, tf S 5 ns, PRR S 1 MHz, duty
cycle = 50%, Zo = 50 II.
B. CL includes probe and stray capacitance.
C. All diodes are 1 N916 or 1 N3064.
4-504
TEXAS'"
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 76265
SN75ALS194
QUADRUPLE DIFFERENTIAL LINE DRIVER
WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
J
5V
OUTPUT
~_~~-M~~OS~l
Oor3V
1 kn
GENERATOR
(See Note A)
200n
(See Note C)
50n
TEST CIRCUIT
OUTPUT
ENABLE
INPUT
':":\:
1.5 V ,
3V
I\'"- - -
tpHZ .... I!:
OUTPUT
~.5 V
Sl CLOSED
I
S2 CLOSED:
OUTPUT tPLZ .... ~
Sl CLOSED
S2 CLOSED
~I
0V
V
OH
~':
"'1.5 V
"1.5 V
--.-/J~ VOL
II
OUTPUT
~3V
ENABLE
1.5V
INPUT OV
I
tpZL =t! !.OUTPUT
Sl CLOSED
:
1.5 V
S2 OPEN
I
VOL
OUTPUT tPZy;:;-H""",::-- VOH
Sl OPEN
1.5 V
S2 CLOSED
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: tr :S 5 ns, tf ::s 5 ns, PRR :s 1 MHz, duty
cycle
= 50%, Zo =
50 0.
B. Cl includes probe and stray capacitance.
C. All diodes are IN916 or lN3064.
FIGURE 4. DRIVER ENABLE AND DISABLE TIMES
TEXAS .",
INSTRUMENTS
POST OFFICE BOX 655012 • OA:"LAS, TeXAS 75265
4-505
SN75ALS194
QUADRUPLE DIFFERENTIAL LINE DRIVER
WITH 3·STATE OUTPUTS
TYPICAL CHARACTERISTICS
y OUTPUT VOLTAGE
y OUTPUT VOLTAGE
vs
DATA INPUT VOLTAGE
vs
DATA INPUT VOLTAGE
5.0
No Load
4.5 I-0utputs Enabled
TA 25'C
4.0
=
=j
i~
II
VCC=5.5VVCC=5Vf
I
f--VCC=4.5V-
3.5
3.0
5.0
VCC=5V
4.5 Outputs Enabled
No Load
4.0
... 2.5
:.
=j
1
I
TA=O'CI
3 .0
I-TA = 25'C
'.. 2.5
2.0
9i
o
1.5
01.5
2.0
>
1.0
1.0
0.5
0.5
o
I
3.5
~
>
TA = 70'C
o
0.5
1.0
1.5
2.0
3.5
o
3.0
o
0.5
1.0
1.5
2.0
2.5
3.0
VI-Data Input Voltage-V
VI-Data Input Voltage-V
FIGURE 6"
FIGURE 6
y OUTPUT VOLTAGE
vs
ENABLE G INPUT VOLTAGE
y OUTPUT VOLTAGE
vs
ENABLE G INPUT VOLTAGE
4.0
4.0
VCC=15 .5V
3.5
3.5
I"'CC=5 V
=j
I
3.0
> 3.0
VCC=4.5V
8.
~
':i
!
TA=25°C-
I
2.0
VI =2V
RL = 470 n to Ground
See Note 3
TA=25'C
0.5
o
0.5
1.0
1.5
2.0
2.5
3.0
o
>
VCC= 5V
VI =2V
RL = 470 n to Ground
See Note 3
0.5
o
o
0.5
1.0
1.5
2.0
2.5
VI-Enable G Input Voltage-V
FIGURE 7
4-506
"--- ....
1.0
VI-Enable G Input Voltage-V
NOTE 3: The A input is connected to
"-"
TA=O'C- '-.,
9 1.5
1.0
o
I
2.5
>
2.0
9t 1.5
o
>
TA = 70'C~
I
f
'0
:I 2.5
FIGURE 8
Vee
during the testing of the Y outputs and to ground during the testing of the Z outputs.
.
TEXAS . "
INSTRUMENTS
POST OFFICE
sox 855012
• DALLAS, tEXAS 75265
3.0
SN75ALS194
QUADRUPLE DIFFERENTIAL LINE DRIVER
WITH 3·STATE OUTPUTS
TYPICAL CHARACTERISTICS
Z OUTPUT VOLTAGE
vs
ENABLE G INPUT VOLTAGE
6
RL =
n
See Note 3
TA = 25°e
Vec=5V
Vce = 4.5 V
>I
..'"
6
~70 t~ Vee
Vec ':' 5.5 V
5
Z OUTPUT VOLTAGE
vs
ENABLE G INPUT VOLTAGE
-
5
>I
4
~
Vce=5V
RL = 470 n to Vee
See Note 4
TA = 70·e-
.....
4 TA - 25°e
.."
3
~
0
>
~
3
;
8-
TA -
90"
2
>
2
>
oL--L__~~==±=~==~
o
0.5
1.0
1.5
2.0
2.5
o
3.0
o
VI-Enable G Input Voltage-V
1.0
1.5
2.0
0.5
2.5
VI-Enable G Input Voltege-V
FIGURE 9
t
3.5
&
~=t=::j:::=t=::f:::::::jt==t===11
3.01---f----1---+---+--~--~--+_--1
HIGH·LEVEL OUTPUT VOLTAGE
vs
OUTPUT CU RRENT
5.0
l'
..&
oa;"
.3
2.01---1--1--,---+--+--+--+--1
..J
f
1.51---1--1--,---+--+--+--+--1
I
:I: 1.0 1----11---+---+---+--~--~--+_--I
~
0.5
1----11---+---+---+--~--~--+_--I
OL-~
o
__
10
~
20
__
~~~-L
30
40
__
50
~
__
60
L-~
70
80
See Note 3
4.5 r-TA = 25°C
--"-"-
14.0
~
2.5 1----'1-----1---+---+--~--~--+_--1
.J:.
3.5
3.0
r\.
2.5
t 2.0
t
1.5
5 1.0
~"\ I\.
Vee = 5.5 V,_ -
I
,~r'\
1'\.' ~
I
I
I
I
.--Vee=5V_ Vce = 4.5 V -
'\l'\['\
> 0.5
o
~
'\ .'\ .'\
I
o
TA-Free·Air Temperature-Oe
'\['\' I\..
-80
-100
-20
-40
-60
IOH-High·Level Output Current-mA
FIGURE 11
NOTES:
3.0
FIGURE 10
HIGH·LEVEL OUTPUT VOLTAGE
vs
FREE·AIR TEMPERATURE
5.0.---.--.---.---.---.---.--,---'
Vee=5V
> 4.5 IOH = -20 mA+_--+---I----1f--+---;
I
See Note 3
4.0
oa;"
a
8-
"
Q
I
0
~
I'-..
I'-- ......
ooe~
I'--
FIGURE 12
3. The A input is connected to Vee during the testing of the Y outputs and to ground during the testing of the Z outputs,
4, The A input is connected to ground during the testing of the Y outputs and to Vee during the te~ting of the Z outputs,
'TEXAS ..,
INSTRUMENTS
. POST OFFICE BOX 856012 • DALlAS, TeXAS 75265
4·507
SN75ALS194
QUADRUPLE DIFFERENTIAL LINE DRIVER
WITH 3·STATE OUTPUTS
TYPICAL CHARACTERISTICS
LOW·LEVEL OUTPUT VOLTAGE
vs
FREE·AIR TEMPERATURE
=j
1
0.5 r---r--'-r--~--r--.--'--r--'
Vee=5V
IOL = 20 mA-t--+--t---j--t----l
See Note 4
0 .4
~
i
:;
•
LOW·LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
t--1--+--+-~-~--+---+-~
0.3 t--1---+---+--~--~--+--+-~
1.0
=j
..
!
~
0.7
,.
0.6
~ 0.5
.5 0.2 t--1---+--+-~-~-+--+-~
.5
0.4
..9
0.3
~
..9
~
~
0.1
t--1--+--+-~-~-+--+-~
~
>
10
20
30
4.0 50
60
70
T A-Free·Air .Temperature-°e
...
40
...
I
c
I!!
(J
>-
i,.
INPUTS OPEN
~
~ 20
~~
10
----
2
3
4
P""
5
30
en
~
20
/
15
I
(J
~
7.
J
10
8
o
/
1/
V
/
o
V
vee-Supply Voltage-V
2
3
4
5
6
7
vee-Supply Voltage-V
FIGURE 15
FIGURE 16
NOTE 4: The A input is connected to ground during the testing of the Y outputs and to
4-508
/'
/
V
25
5
6
Gro~nded
!:i
INPUTS GROUNDED
o
A Inlputs tipen ~r
Outputs Disabled
No Load
TA = 25°e
35
50
o
10 20 30 40 50 60 70 80 90 100
IOL -Low-Level Output eurrent-mA
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
~
30
~5.5V-
SuppLY CURRENT
vs
SUPPLY VOLTAGE
(J
'f"(J
~
;;...-
FIGURE 14
60
>- 40
ii
~~
.se ~
FIGURE 13
Outputs Enabled
70 No Load
TA = 25°e
,.~
1/
o
o
80
80
«
E
.!.c
0.1
I
/
~ ~V
I
5 0 .2
~I
II
Vee = 5 V., r---olJ
OJ
o~~-~~~-~-~-~-~~
o
Vee = 4.5
t 0.8
o
a;
1 J
See Note 4
0.9 -TA = 25°e
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75285
Vee
during the testing of the Z outputs.
8
SN75ALS194
QUADRUPLE DIFFERENTIAL LINE DRIVER
WITH 3·STATE OUTPUTS
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREQUENCY
60
50
'Q)
100 k
1M
10 M
f-Frequency-Hz
FIGURE 17
100M
(J
(I)
-..
a::
I I)
(I)
>
''::
Q
(I)
c:
::::i
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
4-509
r-
5'
CD
...Cci:'
...CD
-til
:II
CD
(')
CD
<'
CD
...
til
4-510
ADVANCE
INFORMATION
SN75ALS195
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3·STATE OUTPUTS
02928; JUNE 1985-REVISED DCT08ER 1986
•
Meets EIA Standards RS·422·A and
RS·423·A
•
Meets CCITT Recommendations V.10,
V.11, X.26, and X.27
J PACKAGE.
(TOPVIEWI
•
- 7 V to 7 V Common·Mode Range with
200·mV Sensitivity
•
3·State TTL·Compatible Outputs
•
High Input Impedance . . . 12 kO Min
•
Input Hysteresis ... 120 mV Typ
•
Single 5·V Supply Operation
•
Low Supply Current
Requirement ... 35 mA Max
•
Improved Speed and Power Consumption
Compared to MC3486
18
Vee
1A
48
1Y
4A
1.2EN
2Y
4Y
2A
3Y
28
3A
GND
38
3,4EN
logic symbol t
•
(31 lV
...
II)
Q)
(51 2V
description
>
u
Q)
'Q)
The SN75ALS195 is a monolithic quadruple line
receiver with three-state outputs designed using
Advanced Low-Power Schottky technology.
This
technology
provides
combined
improvements in bar design, tooling production,
and wafer fabrication, providing significantly less
power consumption and permitting much higher
data throughput than other designs. The device
meets the specifications of EIA Standards
RS-422-A and RS-423-A.
The SN75ALS195 features three-state outputs
that permit direct connection to a bus-organized
system with a fail-safe design that ensures the
outputs will always be high if the inputs are
open. The device is optimized for balanced
multipoint bus transmission at rates up to
10 megabits per second. The input features high
input impedance, input hysteresis for increased
noise immunity, and an input sensitivity of
± 200 millivolts over a common-mode input
voltage range of ± 7 volts. It also features an
active-high enable function for each of two
receiver pairs. The SN75ALS195 is designed for
optimum performance when used with the
SN75ALS 194 quadruple differential line driver.
a::
--...
I I)
(111 3V
Q)
>
';::
(131 4v
C
Q)
c:
logic diagram
The SN75ALS195 is characterized for operation
from
to 70°C.
ooe
1.2EN
1 A --'-'''---', ......
2
o
(31
lV
(51
2V
i=
«
lB---..."",
2A --'-'''---', .....
~
a:
oLL
2B--"""
2
3,4EN
3A...:.:=--" ......
w
(111
U
2
3V
«
3B---....' .......
4A
1131
>
c
4V
«
4 B - -......1/'
ADVANCE INFORMATION documents contoin
information on new ~roducts in the samplinp or
preproduction phase of development. Characteristic
data and other specifications are subject to change
without notice.
~
tThis symbol is in accordance with ANSIIlEEE Std 91-1 984 and
IEC Publication 617-12.
Copyright © 1986, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-511
SN75ALS195
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3·STATE OUTPUTS
ADVANCE
INFORMATION
FUNCTION TABLE (EACH RECEIVER)
ENABLES
DIFFERENTIAL
G
H
A-B
VID ;;: 0.2 V
-0.2 V < VIO < 0.2 V
VIO
s -0.2
V
X
III
roo
H
L
X
?
Z
=
OUTPUT
G
Y
X
X
L
H
H
?
7
H
X
L
X
L
L
L
H
Z
X
L
H
X
high level
= low level
= irrelevant
= indeterminate
= high·impedance (off)
schematics of inputs and outputs
S'
EQUIVALENT OF EACH A or B INPUT
EQUIVALENT OF EACH ENABLE INPUT
TYPICAL OF ALL OUTPUTS
CD
VCC------4.---~--
C
:!,
3 k(J
<
VCC - - -.....- - - i...
-----.--VCC
50 (J
3 k(J
CD
5 k(J
U;
~
CD
(')
CD
.::-
...en
CD
18 kll
INPUT ~........,.,..,.~.-.-t
OUTPUT
INPUT
300 k(J
VCC(A)
»
c
<
»
or
GND (B)
50 Il
2
(')
m
2
-n
o
::D
3:
»
::!
o
2
4-512
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
ADVANCE
INFORMATION
SN75ALS195
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage, A or B inputs, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 15 V
Differential input voltage (see Note 2) ......................................... ± 15 V
Enable input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Low-level 'output current ............... ,................................... 50 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 3) . . . . . .. 1025 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O°C to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............ 300°C
NOTES:
1. All voltage values, except differential input voltage, are with respect to network ground terminal.
2.
Differential~input
voltage is measured at the noninverting input with respect to the corresponding inverting input.
3. For operating above 25°C free-air temperature, derate the J package to to 656 mW at 70°C at the rate of 8.2 mW/oC. In
the J package, SN75ALS195 chips are glass mounted.
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
±7
V
±12
V
Common-mode input voltage, VIC
Differential input voltage, VID
2
High-level input voltage, VIH
High-level output current, IOH
-400
p.A
16
rnA
70
°c
0
III
>
°i
CJ
CD
-...
a:
V
Low-level output current, IOL
Operating free-air temperature, T A
...CD
V
0.8
Low-level input voltage, VIL
•
I I)
CD
>
0;:
C
CD
s::::
::::i
z
i=
o
«
~
a:
ou..
-Zw
o
z
~
Q
«
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-513
SN75ALS195
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3·STATE OUTPUTS
ADVANCE
INFORMATION
electrical characteristics over recommended ranges of common-mode input voltage. supply voltage.
and operating free-air temperature (unless otherwise noted)
PARAMETER
•
VT+
Positive-going threshold voltage
VT-
Negative-going threshold voltage
Vhys
VIK
Hysteresis §
CD
VOH
VOL
Low-level output voltage
VID = -200 mV
10Z
High-impedance state output current
IlL
...C
MAX
UNIT
200
mV
mV
VID - 200 mY.
Une input current
400!,A
10H -
I
I
2.7
3.6
0.45
10L - 8 mA
0.5
10L = 16 mA
VIL - 0.8 V.
Vo = 2.7 V
VID -
VIL - 0.8 V.
Vo = 0.5 V
VID - 3 V.
Other input at 0 V.
VI
See Note 4
15 V
VI VIH - 2.7 V
High-level enable-input current
-3 V.
<'
Short-circuit output current
VID - 3 V.
See Note 5
JLA
15 V
III
ICC
Supply current
Outputs disabled
Vo - O.
V
-20
0.7
1.2
1.0
1.7
20
100
mA
JLA
-100
JLA
-78
-130
mA
22
35
mA
VIL = 0.4 V
lOS
V
V
20
VIH - 5.25 V
Low-level enable-input current
mV
-1.5
Input resistance
...
Typt
120
11= -18 mA
IIH
MIN
-200~
Enable-input clamp voltage
High-level output voltage
II
r
S'
TEST CONDITIONS
12
18
-15
kll
CD
(')
t All typical values are at VCC = 5 V. T A = 25°C:
:t. The algebraic convention. in which the less positive limit is designated minimum. is used in this data sheet for threshold voltage levels only.
CD
§ Hysteresis is the difference between the positive-going input threshold voltage, VT +, and the negative-going input threshold voltage,
...
VT-·
NOTES: 4. Refer to EIA Standard RS-422-A and RS-423-A for exact conditions .
5. Not more than on~ output should be shorted at a time and the duration of the short-circuit should not exceed one second.
CD
:D
<'
CD
III
switching characteristics, Vee
= 5 V,
TA
»
c
.~
tpLH
Propagation delay time. low-to-high-Ievel output
tpHL
Propagation delay time. high-to-Iow-Ievel output
tpZH
Output enable time to high level
tpZL
Output enable time to low level
tpHZ
tpLZ
Output disable time from high level
Output disable time from low level
= 25°e
TEST CONDITIONS
PARAMETER
VID - 0 V to 3 V.
See Figure 2
CL - 15 pF.
CL=15pF.
See Figure 3
CL = 15 pF.
See Figure 3
(')
m
:2
."
o
::D
3:.
»
=!
o
:2
4-514
TEXAS •
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75285,
MIN
TYP
MAX
15
22
ns
15
22
ns
13
25
11
25
13
25
15
22
UNIT
ns
ns
ADVANCE
INFORMATION
SN75ALS195
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3·STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
I
IOH
+ (-I
2v----'
FIGURE 1. VOH. VOL
GENERATOR
(see Note Al
50 II
a..
1.5 V
I
I
III
0 V
G)
-.ltPHLjt-
>
'j
_--_~--VOH
U
I
1.5 V
OUTPUT
2V-------~
VOL
TEST CIRCUIT
G)
a::
~
G)
>
'0:::
VOLTAGE WAVEFORMS
C
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR :s 1 MHz. duty cycle :s 50%. Zout =
50 D,t r :s 6 ns, tf :S 6 ns.
B. CL includes probe and jig capacitance.
G)
C
::i
FIGURE 2. PROPAGATION DELAY TIMES
z
o
t=
~
:E
a:
ou.
Z
w
o
z
~
>
C
~
TEXAS •
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TeXAS 76266
4-515
SN75ALS195
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3·STATE OUTPUTS
ADVANCE
INFORMATION
SWl
+2.5V
OUTPUT
SW2
-2.5V--o
2 k!l
0-5 V
(see Note CI
CL - 15pF
~ (see Note BI
GENERATOR
(see Note .AI
•
51!l
TEST CIRCUIT
'LJE
tpZH
.
INPUT
3V
SWl to 2.5 V
-1.5 V SW2 open
I -
+ __ 0 V
tPZH~
.
IN:U:~
SW3 closed
~
-
OUTPUT
tPHZ........r
OUTPUT
.
14--
--
f
SWl to 2.5 V •
SW2 closed
0 V
L
1.5 V
3V~3V
15 V
SWl
INPUT
I
I
tPLZ-+!
I
I
VOH
to -2.5 V
SW2 closed
.
I
SW3 closed
_
J4-
I
0 V
-
SW3 closed
--1.4V
OUTPUT~
VOL
---1.4V
VOLTAGE WAVEFORMS
2
"o:J:J
---.I
tpLZ
'f='LL
0.5 V__
SW2 closed
SW3 open
VOL
3V
1.5 V
I
I
nm
-
~
V
~
~--4.5V
VOH
-1.5 V
tPHZ
»
c
<
»
2
1-
tpZL ~
---OV
INPUT
L,.5V
~-=~SWl to -2.5V
0
f4I
OUTPUT
tpZL
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR
50 !l.t r s 6 ns. tf S .6 ns.
B. CL includes probe and jig capacitance.
3:
~
C. All diodes are 1N3064 or equivalent.
FIGURE 3. ENABLE AND DISABLE TIMES
o
2
4-516
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76266
s 1 MHz. duty cycle s 50%. Zout =
SN15ALS195
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3·STATE OUTPUTS
ADVANCE
INFORMATION
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
5
>
4
4
VIO VIC RL TA -
200 mV
0
8 kO to GND
25°C
VCC - 5.5 V
>
1
&
VCC - 5 V
1
&
VCC - 4.5 V
TA
TA
TA
3 TA
-
125°C
70°C
,25°CooC
-
.....
TA -
-55°C
~
1!! 3
~
~2
::I
i
g
; 2
o
1
1
o
>
~
0.5
1.5
2
2.5
o
o
3
VCC - 5V
VID - 200 mV
VIC - 0
RL - 8 kO to GNO
1
FIGURE 4
5
I
VCC - 4.5 V
-...
en
CD
>
·C
Q
CD
c:
::;
~ TA - -55°C
V-TA - ooC
~ , T A - 25°C,TA-70oC
V
V
J
IV V
12
2.5
3
,.....TA - r5OC-
V
It"
~
2
(,)
a:
5
>
1
&4
~
1.5
CD
>
'i
6
_~
>3
0.5
en
CD
3
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
VIO - -200 mV
VIC - 0
RL - 1 kO to VCC
TA - 25°C
Vec - 5 V
I
2.5
FIGURE 5
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
VCC - 5.5 V
I
2
Enable Voitage-V
Enable Vohage-V
6
1.5
0.5
II
...
VCC - 5V
VIO - - 200 mV
VIC - 0
RL - 1 k!l to VCC
o
o
0.5
Enable Voltage- V
1.5
2
Enable Voitaga-V
FIGURE 6
FIGURE 7
2.5
3
z
o
~
:E
a:
oLL
-Zw
to)
Z
~
Q
10H - 0
VCC - 5 V
VIC - - 12 V to 12 V
>
10 - 0
TA - 25°C
l!!'" 3
I
'"
I
~
o
;
'"
~'" 3
•
~
::J
>
02
:IQ.
~
~2
VT-
I
~
J:.
:f'" 1
VT+
o
>
r-
:r
CD
c
I
::t:
VCC - 5 V
VIO - 200 mV
VIC - 0
o
>
..<..
o
-200
CD
-400 p.A
'""IOH -
--::a
en
o
-100
o
o
200
100
I
10
VIO-Oifferentiallnput Voltage-mV
I
I
20 30
40
50
60
70
TA-Free-Air Temperature- °C
FIGURE 8
FIGURE 9
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
CD
80
n
CD
.<'
CD
en
5
5
VCC - 5 V
VIO - 200 mV
VIC - 0
VID - 200 mV
>
I
~4
»
c
<
»
:2
n
m
:2
'T1
o
CD
-5
>
~3
:I
o
a;
a;2
...I
J:.
:f
'"
~1
o
>
:ll
s:
»
:::!
o
.....
'"
'"'"
>
VIC - 0
TA - 25°C
°
.........
.........
.........
"- V
"~ ~'\
"~
'\
1
1
I I J
i-- VCC - 505 V
'"" VCC - 5 V
I-VCC - 4.5 V
~
~
"0
>
:13
;
o
~
~
a;
a;2
J:.
:f'"
'\
.'\ ."''\ l"'- ~
~~
~~
V
TA - ooC
TA - 25°CTA - 70o~_
~~ ::....
~1
\,~
~
0"
l'\
-20
-40
-60
-80
-100
10H-High-Level Output Current-mA
-100
-20
-40
-60
-80
10H-High-Level Output Current-mA
FIGURE 11
FIGURE 10
:2
4-518
V~
...I
'\
'\
1
I
"'4
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
ADVANCE
INFORMATION
SN75ALS195
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
0.4
VCC - 5 V
vlD - -200 mV
VIC - 0
>
.,I
SO.3
~
~
]
10 - SmA
•
00.2
I
i'~ 0.1
.
10 - 0
~
en
G)
6
>
-;
>
u
o
-..
G)
o
10
20 30 40
50 60 70
TA-F.ee-Ai. Tempe.atu.e-·C
a:
SO
en
G)
>
-.:::
FIGURE 12
C
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
vs
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
O.S
.I.
I
.I.
VCC - 4.5 V_
0.7 -VCC - 5V--...,
I
VCC - 5.5 V_
:i'0.6
>
.,
~.. 0.5
t
~
00.4
~~
j
~ 0.3
I
I
O.S
)
=f
t:l / /
1': 1y'
o
o
!
~
5 0 .5
~~
~
00.4
10 20
30 40
50 60
70
10L -Low-Level Output Cu ••ent-mA
1
~
0.3
~I
0.2
o-'
VID - -200 mV
VIC - 0
TA - 25°C
>
1/
TA - 250C-::::J.
TA - ooC .........
8.
~
/'
o-'
> 0.1
2,
fA _170 0
0.7
B 0.6
~~
i'~ 0.2
G)
c:
::i
0.1
~
80
~
~
wI
~
~
~
a:
ou..
VCC = 5 V
VIO - -200 mV
VIC = 0
10 20
30 40 50
60 70
10L -Low-Level Output Cu••ent-mA
FIGURE 14
FIGURE 13
z
o
~
80
Z
w
(.)
z
';:
SWITCHING CHARACTERISTICS
vs
FREE-AIR TEMPERATURE
30
..
c
I 20
tpHZ ....
E
:c'"
.
tP'LZ,,-
..•
j::
20
I
tpLH
Vee - 5 V
eL-15pF
25
, tPZH
15
'!"
c
~ '"'5"
.~ 10
~
II)
tPHZ
J
-
PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE
tt.= ~
~ ~ I---~
I--tPHL.J
rr
tpzi......I
tpZH
c
I
16
tP~L_
j::
14
tPLH-
•E
t\
>
II
eL-15pf
18 I-TA - 25°e
c
10
'"
8
";:
C
Q)
c
::::l
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
- - -. .~---- VCC+
VCC+------~.---------~--
CURRENT
SOURCE
INPUT
OUTPUT
---~""'--VCC-
VCC-------~~-----------
PRODUCTIOJ DATA d_ _ •••tail! i.formation
='
:.:'J:~~':·:I~~:r,:,!= .~nf·~x!:
1.ltroml.tl
wlrrlnty. 'r.do.tl••
Itlnd.r~
. prllCllliIIl ..... not _'ily incl.... _.1 of In
..romoton.
Copyright @ 1980, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 866012 • DALLAS, TEXAS 76265
4-523
uA9636AC
DUAL LINE DRIVERS WITH ADJUSTABLE SLEW RATE
absolute maximum ratings over operating free-air temperature ranga (unless otherwise noted)
Positive supply voltage range, Vee + (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . .. Vee _ to 15 V
Negative supply voltage range, Vee _ . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. 0.5 V to -15 V
Output voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 1 5 V
Output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 1 50 mA
Continuous total dissipation at (or below) 25°e free-air temperature (see Note 2):
o package ......................................................... 725 mW
JG package ......................................................... 825 mW
P package ................... : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1000 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OOC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 'mm (1/16 inch) from case for 60 seconds: JG package ........... 300 0 e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: 0 and P packages. . . . . .. 260°C
NOTES: 1. All voltage values are with respect to the network ground terminal.
2. For operation above 25·C free-air temperature, refer to Dissipation Derating Cur.ves in Appendix A. In the JG package, uA9636AC
chips are glass mounted. In the P package, use the 8.0 mW/·C curve for these devices.
recommended operating conditions
MIN
10.8
-10.8
Positive supply voltage, Vr.r, +
Negative supply voltage, VCCHigh-level input voltage, VIH
Low-level input voltage, VII
NOM MAX
12 13.2
-12 -13.2
2
0.8
Wave-shaping resistor, RWS
Operating free-air temperature, T A
10
0
1000
70
UNIT
V
V
V
V
kll
·C
electrical characteristics over recommended range of free-air temperature, supply voltage, and waveshaping resistance (unless otherwise noted)
PARAMETER
VIK
Input clamp voltage
TEST CONDITIONS
11- -15 mA
RL VOH
VOL
High-level output voltage
Low-level output voltage
VI
VI
= 0.8 V
IIH
High-level input current
VI - 2.4 V
VI = 5.5 V
IlL
Low·level input current
VI
10
Output current (power offl
lOS
Short-circuit output current~
ro
Output resistance
ICC+
Positive supply current
ICC-
Negative supply current
= 0.4 V
VCC± = 0,
VI = 2 V
V =0
RL = 450 II
VCC = ±12V,
RWS = 100 kll,
VCC RWS
RL = 3 kll to ground
RL - 450 II to ground
±12 V,
= 100 kll,
Vo
=
5
00
RL = 00
RL = 3 kll to ground
RL - 450 II to ground
=2V
MIN Typt MAX
(See Note 3)
-1.1 -1.5
5
4
-6
-6
-6
±6 V
15
-15
VI
= 0,
Output open
VI - 0,
Output open
5.6
5.6
5.4
-5.7
6
6
6
-5
-5.6
-5.4
-5
-4
-20
10
100
-80
±100
25
150
-40 -150
25
50
UNIT
V
V
V
p.A
""'p.A
mA
II
13
18
mA
-13
-18
mA
tAli typical values are at VCC ±12 V, TA = 25·C.
~Not more than one output should. be shorted to ground at a time.
NOTE 3: The algebraic convention, in which the less-positive (more-negative) limit is designated as minirl)um, is used in this data sheet
for logic voltage levels, e.g., when - 5 V is the maximum, the .minirr:tum. is a more-negative voltage.
4-524
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76265
uA9636AC
DUAL LINE DRIVERS WITH ADJUSTABLE SLEW RATE
switching characteristics, VCC± - 12 V, TA - 25°C, see Figure 1
PARAMETER
TEST CONDITioNS
tTLH
Transition time, low-to-high-Ievel output
tTHL
TYP
MAX
1.1
1.4
RL = 450 II,
RWS - 100 kll
11
14
CL=30pF
RWS - 500 kll
40
55
70
110
140
1.1
1.4
11
14
RL = 450 II,
RWS - 100 kll
BO
O.B
B
CL = 30 pF
RWS = 500 kll
40
55
70
Rws-lmll
BO
110
140
RWS- 1MII
RWS - 10 kll
Transition time, high-to-Iow-Ievel output
MIN
O.B
B
RWS = 10 kll
UNIT
I's
I'S
a
PARAMETER MEASUREMENT INFORMATION
--3V
~
INPUT
---t
INPUT-. .
x)--..- .....~- OUTPUT
50 II
~
(See Note B)
Q)
>
"i
(.)
OV
CL-30pF
RWS
(See Note AI
O%
OUTPUT
I
~
VCC-
-...
Q)
a:
- - - VOH
en
I
I
tTHL
90%
--til
10%
I+-
_1- __ - - VOL
10%
-+I
Q)
>
~ tTLH
";::
I
C
VOLTAGE WAVEFORMS
c
::::i
I
I
Q)
TEST CIRCUIT
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: tr :s; 10 ns, tf :s; 10 ns, Zout = 50 II,
PRR :s; 1 kHz, duty cycle = 50%.
FIGURE 1. TRANSITION TIMES
TEXAS ...,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-525
uA9636AC
DUAL LINE DRIVERS WITH ADJUSTABLE SLEW RATE
TYPICAL CHARACTERISTICS
INPUT CURRENT
vs
INPUT VOLTAGE
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
12
250
V6C±' - '±d V
RWS - 100 kO
RL - 4500
10
>
8
CD
til
6
I
!
4
~
I
2
~
o
0
150
:I.
TA - 25°C
6-2
-
.!.
100
~
5(1
,U
o
c
1
TA - 70°C
4
~
200
::I
:;
TA - ooC
..,.
-150
-6
-200
.<'c
.
-8
-
~
TA - 70°C
~ -50
I·
:-100
> -4
:f
CD
VCC±I - 1±12V
RWS - 100 kD TA - ooCr-----.
I
TA - 25°C-
o
!-- TA - ooC
I
I
!--TA = 25°C
-250
0.4
1.2
1.6
0.8
VI-Input Voltage-V
en
-2 -1
2
n
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
(POWER ON)
CD
<'
CD
u;
30
..
100
- '±d V
RWS - 100 kO
TA - 25°C
80
60
'i
I
10
\..
VI- 2 V
I
40
I!!
20
u
0
~
!i
o
&-20
~ -20
o·
~
1/
=0
TA = 25°C
VI
I
J
r
::I
r
9-30
VI
1- 40
=0
J
9
J
-60
-80
-50
-10-8-6-4-20246810
VO-Output Voltage-V
I
-100
-10-8 -6 -4 2
0 2 4
6
VO-Output Voltage-V
FIGURE 4
4-526
I
vdc± 1= 01
~
~ -10
-40
2345678
VI-Input Voltage-V
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
(POWER OFF)
V~C±I
20
0
FIGURE 3
FIGURE 2
::rI
CD
50
i"--.
VTA - 70°C
CD
40
r----
FIGURE 5
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
8
10
uA9636AC
DUAL LINE DRIVERS WITH ADJUSTABLE SLEW RATE
TYPICAL CHARACTERISTICS
TRANSITION TIMES
vs
WAVESHAPING RESISTANCE
1000
700
::I. 400
..
..
TA
I
= OOC
/
200
E
~
i= 100
c
70
.51
.!::
40
..
c
f!
20
~
I
....
X
..i
10
7
4
t"
2
~
....
If
V
V
_ 70°
a
/
...
I/)
V
1
0.01
Q)
V
>
"iii
tJ
0.04 0.1
0.4
4
10
Q)
a:
""-
...
RWS - Waveshaping Resistance - MO
I/)
Q)
FIGURE 6
>
.;:
C
TYPICAL APPLICATION DATA
Q)
12 V
TWISTED PAIR
OR
5V
c:
:.:::i
FLAT CABLE
RWS
-12 V
FIGURE 7. RS-423-A SYSTEM APPLICATION
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-527
•
r-
:r
CD
...c
...CD
:c!'
III
:CD:a
(')
CD
..<'
CD
III
4-528
uA9637AM. uA9637AC
DUAL DIFFERENTIAL LINE RECEIVER
02609, SEPTEMBER 1980-REVISEO NOVEMBER 1986
•
Meets EIA Standards RS-422-A and
RS-423-A
•
Meets Federal Standards 1020 and 1030
•
Operates from Single 5-V Power Supply
uA9637M , . , JG PACKAGE
uA9637C , , . D, JG, OR PPACKAGE
ITOPVIEWI
•
Wide Common-Mode Voltage Range
•
High Input Impedance
•
TTL-Compatible Outputs
•
High-Speed Schottky Circuitry
•
8-Pin Dual-In-Line and "Small Outline"
Packages
•
•
VCC[j8
10UT
2
7
20UT
3
6
GND
4
5
11N+
1IN21N+
21N-
logic symbol t
11N+
llN-
Similar to SN75157 except for Corner VCC
and Ground Pin Positions
Designed to Be Interchangeable with
Fairchild ,.A9637A
21N+
21N-
(8)
(7)
]
.at>
(2)
lOUT
(6)
(3)
(5)
20UT
tThis symbol is in accordance with ANSI/lEEE Std 91-1984 and
lEe Publication 617-12_
description
logic diagram
The uA9637 AC is a dual differential line receiver
designed to meet EIA standards RS-422-A and
RS-423-A and Federal Standards 1020 and
1030, It utilizes Schottky circuitry and has TTLcompatible outputs. The inputs are compatible
with either a single-ended or a differential-line
system. This device operates from a single 5-volt
power supply and is supplied in an a-pin dual-inline package and small outline package.
II
f!
>
"G)
CD
U
CD
a:
1IN+~81
.a
f!
CD
>
";:
121 lOUT
llN- 171
C
2IN+~61
.r:t.
CD
c
131 lOUT
::::i
21N- 151
The uA9637 AM is characterized over the full
military temperature range of - 55°C to 125°C.
The uA9637 AC is characterized for operation
from OOC to 70°C.
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
----------.----VCC
VCC
son NOM
INPUT--~--~~~~----i
OUTPUT
CURRENT
SOURCE
PROOUCTIOI DATA d••• ments •• ntlln
~':':=~.t.:~1P:'fi':.r~m:~~=
., T.... Instruml.ts .tI.d.~ warranty,
Producti.n pr••essing dDII not n...... rlly
laotuda tlItinl of .11 poramators.
Copyright @ 1980, Texas Instruments Incorporated
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4-529
uA9637AM, uA9637AC
DUAL DIFFERENTIAL LINE RECEIVER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
II
r-
Supply voltage, VCC (see Note 1) ...................................... - 0.5 V to 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 1 5 V
Differential input voltage (see Note 2) ......................................... ± 15 V
Output voltage (see Note 1) .................................. ; ...... -0.5 V to 5.5 V
Low-level output current ................................................... 50 rnA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 3):
D package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. 725 mW
JG package: uA9637 AM ............................................ , 1050 mW
uA9637 AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 825 mW
P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1000 mW
Operating free-air temperature range: uA9637 AM . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
uA9637AC ............................ ooC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package ........... 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package ...... '"
260°C
NOTES:
:i"
CD
.
..c::..
CD
1. All voltage values, except differential input voltage, are with respect to the network ground terminal.
2. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input.
3. For operation above 25°C free-air temperature, derate linearly at the following rates: 5.8 mWI °C for the 0 package, 8.4 mW/oC
for uA9637AM in the JG package, 6.6 mW/oC for uA9637AC in the JG package. and 8.0 mW/oC for the P package.
recommended operating conditions
til
uA9637AM
ii
CD
Supply voltage. VCC
CD
Common-mode input voltage. VIC
n
..
<'
CD
til
MIN
NOM
4.5
5
uA9637AC
MAX
5.5
MIN
4.75
NOM
MAX
5
5.25
±7
-55
Operating free,-air temperature, T A
125
0
UNIT
V
±7
V
70
°c
electrical characteristics over recommended ranges of supply voltage. common-mode input voltage.
and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VT
Threshold voltage (VT + and VT _)
Vhys
Hysteresis (VT +
-
See Note 5
MIN Typt
MAX
See Note 4
-0.2
0.2
-0.4
VT - )
0.4
70
VOH
19 - eve output vo tage
VOL
Low-level output voltage
II
Input current
lOS
Short-circuit output current+
Va = O.
ICC
Supply Current
VIO = -0.5 V.
VIO - 0.2 V.
0.2 v.
VIO -
1 mA
10 10 - 20 mA
2.5
VCC = 0 to 5.5 V. I VI = 10 V
See Note 6
VIO = 0.2 V
No load
tAli typical values are at VCC = 5 V. TA = 25°C.
-40
v
3.5
0.35
0.5
1.1
3.25
-75 -100
35
V
mV
-1.6 - 3.25
IVI=-10V
UNIT
50
V
mA
mA
mA
:l:Only one output should be shorted at a time, and duration of the short~circuit should not exceed one secQnd.
NOTES: 4. The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet
for threshold levels only.
5. The expanded threshold parameter is tested with a 500~O resistor in series with each input.
6. The input not under test is grounded.
4-530
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
uA9637AM, uA9637AC
DUAL DIFFERENTIAL LINE RECEIVER
switching characteristics. Vce - 5 V. TA - 25°e
I
PARAMETER
Propagation delay time, low-to-high-Ievel output
Propagation delay time, high-to-Iow-Ievel output
I
I
I MIN
TEST CONDITION
CL
=
30 pF,
TYP MAX1 UNIT l
I
I
See Figure 1
15
13
25\ ns
251 ns
l
I
PARAMETER MEASUREMENT INFORMATION
VCC+
OUTPUT
VCC+
392n
I.... Nota AI
+0.5 V- -
,.-----"""'\
I.!N:~i 81 ~ 5~
-0.5V~....-.I
5~\11L.____
-
~ tpHL
tpLH
.-Jl.. ,. v\"'_____II
3.92 kn
OUT_PU_T_ _
VOLTAGE WAVEFORM
TEST CIRCUIT
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: tr S 5 n5, tf
duty cycle = 50%.
:s 5 ns, PRR :s 5 MHz,
FIGURE 1. TRANSITION TIMES
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
OUTPUT VOLTAGE
4
vs
vs
DIFFERENTIAL INPUT VOLTAGE
DIFFERENTIAL INPUT VOLTAGE
4
vch
= 4JS V
-TA = 25°C
>I
3
VIC=O
!!l,
:I
.
e-"
I
I VIC=O
i
I
VIC=±7V
0
>
VCC = 5.25 V
TA = 25°C
I
I
I
I
VIC = ±7 V:
I
I
"
0
I
0
VIC= ±7 V
>
I
:
VIC=O !
"
o
-100
-50
o
VIC = ±7 V
I
2
VIC=O
i
I
~
I
I!
I
50
100
o
-50
-100
o
50
100
VID-Differentiallnput Voltage-mV
VID-Differential Input Voltage-mV
FIGURE 3
FIGURE 2
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TeXAS 75285
4-531
uA9637AM, uA9637AC
DUAL DIFFERENTIAL LINE RECEIVER
TYPICAL CHARACTERISTICS
HIGH·LEVEL OUTPuT VOLTAGE
vs
HIGH·LEVEL OUTPUT CURRENT
LOW·LEVEL OUTPUT CURRENT
S.O
>
~
LOW-LEVEL OUTPUT VOLTAGE
vs
0.6
VCC = S V
VIO= 0.2 VTA = 2S"C
4.S
4.0
f
0.5 f- VID = -0.2 V
TA = 2S"C
>
0.4
i
0.3
l!
~ 3.S
i
3.0
o"
2.S
""'" ~
"
iii
.5
.i:
f
2.0
1.S
I
~ 1.0
'"
o
-10
.,.,/"
"" r'\.
.5
!
0.2
./
V
iii
O.S
o
o
VC~=5~
:r
/
I
...J
~ 0.1
"I'\.
."
o
o
-20 -30 -40 -SO -60 -70 -80
S
10
1S
FIGURE 4
FIGURE 5
SUPPLY CU RRENT
vs
SUPPLY VOLTAGE
100
No1load I
90 - Inputs open
80 _ TA=25"C
'
";:
Q
G)
c
::i
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 6155012 • DALLAS, TeXAS 7528fi
4-533
•
r-
5'
CD
C
::::!,
<
CD
...en
--
:lJ
CD
(')
CD
<'
...
CD
en
4-534
uA9638C
DUAL HIGH-SPEED DIFFERENTIAL LINE DRIVER
0261
•
Meets EIA Standard RS-422-A
•
Operates From a Single S-V Supply
•
TTL-and CMOS-Input Compatibility
•
Output Short-Circuit Protection
•
Schottky Circuitry
•
Designed to be Interchangeable with
Fairchild 9638
OCTOBER 19BO-REVISED SEPTEMBER 19B6
DB
D. JG. OR P DUAL-IN-L1NE PACKAGE
(TOP VIEWI
Vee
1A
2A
GND
2
3
7
6
5
4
1Y
1Z
2Y
2Z
logic symbol t
description
t>
The uA9638C is a dual high-speed differential
line driver designed to meet EIA Standard
RS-422-A. The inputs are TTL- and CMOScompatible and have input clamp diodes.
Schottky-diode-clamped transistors are used to
minimize propagation delay time. This device
operates from a single 5-volt power supply and
is supplied in an 8-pin dual-in-line package.
(8) 1Y
lA (2)
lZ
2Y
2A (3)
II
...
2Z
II)
logic diagram
CP
>
-iii
811Y
~
The uA9638C is characterized for operation
from OOC to 70°C.
(J
CP
lA (21
a::
-..
...CP
(71 lZ
II)
>
-;:
(612Y
~
C
2A (31
CP
(51 2Z
c:
:.:J
tThis symbol is in accordance with ANSI/IEEE SId 91-1984 and
lEe Publication 617-12.
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
--------~----~~---Vcc
vcc----------------.-----~-
4k.flNOM
INPUT--~~~--~----r___4
9.6.fl
~------_1~~~---OUTPUT
.....- - - G N D
PRODUCTION DATA d•• umanl. contain
information current as of publication date.
Praducts canfarm to specifications per the terms
of T8xa. Instruments standard warranty.
Productioo processing dOBS not Recessarily
include I.sting ., an parameters.
Copyright
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
© 1980, Texas Instruments Incorporated
4-535
uA9638C
DUAL HIGH·SPEED DIFFERENTIAL LINE DRIVER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Vcc (see Note 1) .................................. -0.5 V to 7 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
o package ......................................................... 725 mW
JG package ........................................................ 825 mW
P package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1000 mW
Operating free-air temperature range ...................................... O°C to 70°C
Storage .temperature range ......................................... ' - 65°C to 1 50°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package ........... 300°C
Lead temperature 1,6 mm (1/16 inch) fror:n 10 seconds: 0 and P package .............. 260°C
•
NOTES: 1. Voltage values except differential output voltages are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, refer to Dissipation Derating Curves in Appendix A. In the JG package, uA963Be
chips are glass mounted. In the P package, use the 8.0-mW/oC curve for these devices.
recommended operating conditions
Supply voltage, Vee
High-level input voltage, VIH
MIN
NOM
MAX
UNIT
4.75
2
5
5.25
V
V
Low-level input voltage, VIL
High-level output current, 10H
Low-level output current, 10L
Operating free-air temperature, TA
0
O.B
V
-'-50
mA
50
mA
70
°e
electrical characteristics over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input clamp voltage
Vee = 4.75 V, 11= -18 mA
VOH
High-level output voltage
Vee - 4.75 V, VIH - 2 V,
VIL = O.B V
Low-level output voltage
Vee - 4.75 V, VIH - 2 V,
10L = 40 mA
VOL
1 VODI 1 Differential output voltage
1 VOD2 1 Differenti al output voltage
Change in magnitude of+
.11 VOD 1 differential output voltage
Common-mode output voltage §
Voe
.11 Voe 1
MIN Typt
-1
IIOH- -10 mA
IIOH = -40 mA
VIL - O,B V,
2,5
3,5
0.5
Vee = 5.25 V, 10 = 0
2VOD2
2
Vee = 4.75 V to 5,25 V, RL = 10011, See Figure 1
- 6 V
I Vo = -0,25 V
0,25 V to 6 V
I VO-
II
Input current
IIH
High-level input current
Vee = 5.25 V, VI - 5.5 V
Vee - 5,25 V, VI - 2,7 V
IlL
Low-level input current
Vee - 5.25 V, VI - 0,5 V
lOS
Short-circuit output"current'
Vee = 5.25 V, Vo = 0
ICC
Supply current (all drivers)
Vee - 5.25 V, No load,
v
V
±0.4
V
3
V
±0,4
V
100
0.1
_0,1 -100
pA
common-mode output voltage
Vee = 0,
V
V
Change in magnitude of f:
Output current with power off
UNIT
V
2
LVo
10
MAX
-1.2
± 100
50
26
-50
All inputs at 0 V
45
p.A
p.A
200
p.A
-150
mA
65
mA
t All typical values are at Vee = 5 V ~nd T A = 25°C.
~.11 VOD 1 and.11 Voe 1 are the changes in magnitude of VOD and Voe, respectively, that occur when the input is changed from a
high
level to a low level.
§In EIA Standard RS·422-A, Voe, which is the average of the two output voltages with respect to ground, is called output offset voltage, VOS.
,Only one output at a time should be shorted and duration' of the short-circuit should not exceed one second.
4-536
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TeXAS 75265
uA9638C
DUAL HIGH·SPEED DIFFERENTIAL LINE DRIVER
switching characteristics. Vee - 5 V. TA '" 25°e
PARAMETER
too
ItrD
TEST CONDITION
Differential-output delay time
CL
Differential-output transition time
~
15 pF,
MIN
RL
~
TYP
MAX
10
15
ns
10
15
ns
1000
See Figure 2
Skew
1
UNIT
ns
PARAMETER MEASUREMENT INFORMATION
t
INPUT
50n
a
VOD2
I
50n
ell
FIGURE 1. DIFFERENTIAL AND COMMON·MODE OUTPUT VOLTAGES
~
>
'Q)
-3V
(.)
-..
GI
INPUT
a:
I
YOUTPUT
ell
'--:-----0 v
GI
tDD....I.--.I
>
I
DIFFERENTIAL I
RL
GENERATOR
(See Noto AI
~
lOOn
OUTPUT
10%
'0:;
I
C
GI
C
:::::i
ZOUTPUT
15
CL =
pF
(Sae Noto BI
50%\1
'50%
, . - - - - - - . . , . - - - -VOH
YOUTPUT
_ _ _ _ _ _ _J~
i[
VOL
=-t .. Skew
ZOUTPUT
TEST CIRCUITS
Skew-./
,50%
IA-
50%'-=:::
VOLTAGE WAVEFORMS
NOTES: A. The input pulse generator has the following characteristics: ZOUT
B. CL includes probe and jig capacitance.
~
50 0, PRR :s 500 kHz, tw
~
100 ns, tr
~
:s 5 ns.
FIGURE 2. SWITCHING TIMES
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
4·537
•
4-538
uA9639C
DUAL DIFFERENTIAL LINE RECEIVER
03009. OCTOBER 19B6
•
•
•
•
•
•
•
•
•
Meets EIA Standards RS-422-A and
RS-423-A
D. JG. OR P PACKAGE
(TOP VIEW)
Meets Federal Standards 1020 and 1030
VCC[]8
lOUT 2
7
20UT 3
6
GND 4
5
Operates from Single 5-V Power Supply
Wide Common-Mode Voltage Range
High Input Impedance
l1N+
l1N21N+
21N-
logic symbol t
TTL-Compatible Outputs
High-Speed Schottky Circuitry
liN +
S-Pin Dual-In-Llne and "Small Outline"
Packages
11N21N+
Designed to be Interchangeable with
Fairchild I'A9639AC
21N-
(8)
]
17)
.D'I>
(2)
16)
(31
(5)
lOUT
20UT
tThis symbol is in accordance with ANSIIIEEE Std 91-1984 and
lEe Publication 617-12.
description
The uA9639C is a dual differential line receiver
designed to meet EIA standards RS-422-A and
RS-423-A and Federal Standards 1020 and
1030. It utilizes Schottky circuitry and has TTLcompatible outputs. The inputs are compatible
with either a single-ended or a differential-line
system. This device operates from a single 5-volt
power supply and is supplied in an B-pin dual-inline package and "small outline" package.
a
logic diagram
The uA9639C is characterized for operation
from ODC to 70°C.
lIN+~81
.D'
(21 lOUT
lIN- 171
2IN+~6)
.D'
(3) 20UT
21N- (5)
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
VCC
----------~.-----Vcc
son NOM
8kn
INPUT--~--~~~-4~__~
OUTPUT
CURRENT
SOURCE
PRODUCTION DATA d......... contel. inlor.diG.
currlat H 01 p.blicdiD. dati. Producll conform II
.....flcatl ••• per dol II.... 01 TIll. IlIIIrulllllll
oIt....rd wlrredy. Prodlcti.. ' ......i.. dta nat
n_"1v i.cl.... IIItInl 01 all PI ..........
Copyright Cl' 1986. Texas Instrument. Incorporated
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 856012 • DALLAS. TEXAS 75285
4-539
uA9639C
DUAL DIFFERENTIAL LINE RECEIVER
absolute maximum ratings over operating free-air temperature range (unless otherwise notedl
•
Supply voltage, VCC (see Note 1) ............................ . . . . . . . . .. - 0.5 V to 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 15 V
Differentialinput voltage (see Note 2) ................. -. . . . . . . . . . . . . . . . . . . . . . •. ± 15 V
Output voltage (see Note 1) .......................... , . . . . . . . . . . . . .. -0.5 V to 5.5 V
Low-level output current ..................•................................ 50 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 3):
o package ................ " . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 725 mW
JG package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 825 mW
P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1000 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O°C to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package ... , •. ,:.-,;,~. -, 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: 0 and P package ....... 260°C
NOTES:
1. All voltage values, except differential input voltage, are with respect to the network ground terminal.
2. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input.
3. For operation above 25°C free-air temperature, derate the D package to 464 mW at 70°C at the rate of 5.8 mW/oC, the
JG package to 528 mW at 70°C attha rate of 6.6 mW/oC, and the P package to 640 mW at 70°C at the rate of 8.0 mW/oC,
recommended operating conditions
MIN
4.75
Supply voltage, VCC
Common-mode input voltage, VIC
Operating free-air temperature, T A
NOM
MAX
UNIT
5
5.25
±7
70
V
V
0
°c
electrical characteristics over recommended ranges of supply voltage. common-mode input voltage.
and operating free-air temperature (unless othewise noted I
PARAMETER
MIN TYpT
TEST CONDITIONS
VT
Threshold voltage (VT + and VT-I
Vhys
VOH
VOL
Hysteresis (VT + - VT _)
High-level output voltage
Low-level output voltage
II
Input current
lOS
ICC
.Short-circuit output current*
Supply current
See Note 5
VID - 0.2 V,
0.2 V,
VID -
10 -
VCC - 0 to 5.5 V,
See Note 6
Vo
= 0,
VID -
0.5 V,
I
-1 mA
2.5
-40
UNIT
V
mV
0.5
3.25
-1.6 -3.25
-10 V
VID = 0.2 V
No load
70
3.5
0.35
1.1
'0 - 20 mA
VI - 10 V
I V, =
MAX
See Note 4
-0.2
0.2
-0.4
0.4
-75 -100
' 35
50
V
V
mA
mA
mA
tAli typical values are at VCC = 5 V, TA = 25°C_
tOnly one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTES: 4. The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet
for threshold levels only.
5. The expanded threshold parameter is tested with a 500-0 resistor in series with each input.
6. The input not under test is grounded.
switching characteristics.
I
I tPLH
I tpHL
4-540
Vee -
5
V.
TA -
PARAMETER
Propagation delay time, low-to-high-Ievel output
Propagation delay time, high-to-Iow-Ievel output
ODe to
70 De
TEST CONDITION
CL = 30 pF,
See Figure 1
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
MIN
MAX
85
85
UNIT
ns
ns
uA9639C
DUAL DIFFERENTIAL LINE RECEIVER
PARAMETER MEASUREMENT INFORMATION
VCC+
Vcc+
OUTPUT
+0.5 V- 39211
INPUT
I N P 0 T 50%
(sea Note B)
-0.5 V
5111
(see Note AI
r--------,
50%\
!
I
: '------
14---! tpHL
.-...I tpLH
.-J/" ,..\. ____
3.92k11
OUTP_U_T_ _
VOL TAGE WAVEFORM
TEST CIRCUIT
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: tr :S 5 ns, tf :S 5 ns, PRR
duty cycle = 50%.
II
..
II)
:s
5 MHz,
Q)
>
"G)
FIGURE 1. TRANSITION TIMES
U
Q)
.
£Z:
""II)
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
4
vs
vs
DIFFERENTIAL INPUT VOLTAGE
4
VC~= 4.~5 V
VIC= 0
~'"
>I
i
3
>
...
~IC=~
-50
:
:
I
I
I
I
o
I
>
I
VIC - ±7 V
VIC=±7 V:
90
VIC= ±7 V
o
I
I
I
2
~'"
-100
I
I VIC=O
"
2
>
:::::i
VCC= 5.25 V
TA = 25°C
'"
l!
"0
VIC=±7V
0
I
0
Q)
c
I
I
3
l!
"0
>...
>
Q
DIFFERENTIAL INPUT VOLTAGE
'-TA = 25°C
:r..."
Q)
";::
OUTPUT VOLTAGE
VIC=O
I
:
50
100
o
-50
-100
o
50
100
VID-Differentiallnput Voltage-mV
VID-Differential Input Voltage-mV
FIGURE 3
FIGURE 2
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-541
uA9639C
DUAL DIFFERENTIAL LINE RECEIVER
TYPICAL CHARACTERISTICS
LOW·LEVEL OUTPUT VOLTAGE
vs
LOW·LEVEL OUTPUT CURRENT
HIGH·LEVEL OUTPUT VOLTAGE
vs
HIGH·LEVEl OUTPUT CURRENT
5.0
.>
4.5
~
4.0
l!
•
2.5
a;
>
j 2.0
:r
CD
...c
<'
CD
i 1.5
6I 1.0
>
;;;
:i
CD
n
.."
>
o
-10
..-/
0.4
S-
/'"
"
.,..J>
0 0.3
a;
'" "
0
I
00.1
..J
>
I'\.
'"
0
-80
5
0
10
15
FIGURE 4
FIGURE 5
CD
...<'
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
CD
III
100
'.
,
No load
90 I- I nputs open
80 I- TA = 25°C
.
E 70
I
I:
~ 60
"
/
u 50
>
15.
a. 40
~
/'
/
30
/
20
10
o
--
/
,/
023
4
5
6
VCC-Supply Voltage-V
FIGURE 6
4-542
20
25
30
35
IOL -Low· Level Output Current-mA
IOH-High.Level Output Current-mA
'1"
/""
..J
-20 -30 -40 -50 -60 -70
«
/
/
./
/
~ 0.2
'"
0.5
o
.,
15
.c
r-
0.5 I- VID = -~.2 V
TA = 25 C
co
l!
""
3.0
VcIC=5~
>I
....,
~ 3.5
~
o"
0.6
Vcc = 5 V
VID = 0.2 VTA = 25°C
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DAL.LAS, TEXAS 76285
7
8
40
uA9639C
DUAL DIFFERENTIAL LINE RECEIVER
TYPICAL APPLICATION DATA
+5 V
TWISTED PAIR
+5V
+5V
•
~
Q)
FIGURE 7. RS-422-A SYSTEM APPLICATIONS
>
'iii
t)
-...
Q)
a:
I I)
Q)
>
'0:::
C
Q)
r:
::J
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4-543
4-544
Alphanumeric Index
Selection Guide
Cross-Reference Guide
Data Sheets
Data Sheets
Cross-Reference Guide
Data Sheets
Peripheral Driversl Actuators
•
'------Cross-Reference Guide
Data Sheets
Data Sheets
Data Sheets
5-1
5-2
PERIPHERAL DRIVERS/ACTUATORS
CROSS-REFERENCE GUIDE
CROSS·REFERENCE GUIDE
(manfacturers arranged alphabetically)
Replacements were based on similarity of electrical and mechanical characteristics as shown in currently published
data. Interchangeability in particular applications is not guaranteed. Before using a device as a substitute, the
user should compare the specifications of the substitute device with the specifications of the original.
Texas Instruments makes no warranty as to the information furnished and the buyer assumes all risk in the
use thereof. No liability is assumed for damages resulting from the use of the information contained in this list.
FAIRCHILD
I'A75451
I'A75452
~75453
~75454
I'A75461
I'A75462
SUGGESTED
TI REPLACEMENT
SN75451B
SN75452B
SN75453B
SN75454B
SN75461
SN75462
MC1412
MC1413
ULN2002A
ULN2003A
I'A3680
OS36805-173
~9665
ULN2001A
ULN2002A
ULN2003A
ULN2004A
I'A9666
I'A9667
~9668
MOTOROLA
MC1411
MC1412
MC1413
MC1413T
MC1416
SUGGESTED
TI REPLACEMENT
ULN2001A
ULN2002A
ULN2003A
SN75468
ULN2004A
PAGE
NO.
5-81
5-81
5-81
5-81
5-93
5-93
5-173
5-173
5-173
5-173
5-173
5-173
PAGE
NO.
5-173
5-173
5-173
5-101
5-173
MC1471
MC1473
MC1474
SN75476
SN75478
SN75479
5-117
5-117
5-117
SN75451B
SN75452B
SN75453B
SN75454B
SN75451B
SN75452B
SN75453B
SN75454B
5-81
5-81
5-81
5-81
UON2841
UON2845
UON2841
UDN2845
5-169
5-169
ULN2001
ULN2002
ULN2003
ULN2004
ULN2001A
ULN2002A
ULN2003A
ULN2004A
5-173
5-173
5-173
5-173
ULN2064
ULN2065
ULN2066
ULN2067
ULN2068
ULN2069
ULN2064
ULN2065
ULN2066
ULN2067
ULN2068
ULN2069
5-181
5-181
5-181
5-181
5-187
5-187
ULN2074
ULN2075
ULN2074
ULN2075
5-193
5-193
NATIONAL
DS3611
DS3612
DS361J
SUGGESTED
TI REPLACEMENT
SN75471
SN75472
SN75473
PAGE
NO.
5-109
5-109
5-109
DS3658
SN75437A
5-63
OS3668
SN75435
5-57
OS3669
SN75440
5-69
OS3680
OS3680
5-5
OS75361
OS75365
SN75372
SN75374
5-33
5-43
OS75451
OS75452
OS75453
OS75454
SN75451B
SN75452B
SN75453B
SN75454B
5-81
5-81
5-81
5-81
OS75461
OS75462
OS75463
SN75461
SN75462
SN75463
5.-93
5-93
5-93
LM3611
LM3612
LM3613
SN75471
SN75472
SN75473
5-109
5-109
5-109
LM75453
SN75453B
5-81
RIFA
PB0352301
PB0352302
PB0352303
PB0352304
SUGGESTED
TI REPLACEMENT
ULN2001A
ULN2004A
ULN2003A
ULN2002A
PAGE
NO.
5-173
5-173
5-173
5-173
PB0352311
PB0352312
PB0352313
PB0352314
SN75466
SN75469
SN75468
SN75467
5-101
5-101
5-101
5-101
UC3717
PBL3717A
5-19
. TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
•
..
...
II)
0
CO
...;:,
-..
CJ
-;:
0
...
iii
CD
~
Q.
-;:
CD
Il.
5-3
PERIPHERAL DRIVERS/ACTUATORS
CROSS·REFERENCE GUIDE
SUGGESTED
TI REPLACEMENT
PAGE
NO.
L293
L293
L293D
L293D
L298
L293
SN754411 *
L293D
SN754410*
L298
5-9
5-159
5-13
5-153
5-19
L201
L202
L203
L204
ULN2001A
ULN2002A
ULN2003A
ULN2004A
ULN2001
ULN2002
ULN2003
ULN2004
SGS·ATES
5-53
5-63
5-169
5-169
5-173
5-173
5-173
5-173
UDN-2949
UDN-2950
UDN-3611
UDN-3612
UDN-3613
SN75605*
SN75605*
SN75471
SN75472
SN75473
5-123
5-123
5-109
5-109
5-109
ULN2001A
ULN2002A
ULN2003A
ULN2004A
5-173
5-173
5-173
5-173
UDN-5711
UDN-5713
UDN-5714
UDN-5722
SN75476
SN75478
SN75479
SN75477
5-117
5·117
5-117
5-117
ULN2064
ULN2065
ULN2066
ULN2067
ULN2068
ULN2069
ULN2064
ULN2065
ULN2066
ULN2067
ULN2068
ULN2069
5-181
5-181
5-181
5-181
5-187
5-187
ULN·2001
ULN·2002
ULN-2003
ULN-2004
ULN-2005
ULN2001A
ULN2002A
ULN2003A
ULN2004A
ULN2005A
5·173
5-173
5-173
5-173
5-173
ULN2074
ULN2075
ULN2074
ULN2075
5-193
5-193
PBL3717A
PBL3717A
5-19
ULN-2021
ULN-2022
ULN-2023
ULN·2024
ULN·2025
SN75266
SN75267
SN75268
SN75269
SN75265
5-101
5-101
5-101
5·101
5-101
ULN·2064
ULN·2065
ULN·2066
ULN-2067
ULN-2068
ULN-2069
ULN2064
ULN2065
ULN2066
ULN2067
ULN2068
ULN2069
5·181
5·181
5-181
5·181
5-187
5-187
ULN-2074
ULN-2075
ULN2074
ULN2075
5-193
5-193
~
SG2001
SG2002
SG2003
SG2004
ULN2001A
ULN2002A
ULN2003A
ULN2004A
5-173
5-173
5-173
5-173
::::!,
SG2022
SG2023
SG2024
SN75467
SN75468
SN75469
5·101
5·101
5-101
...en
»
SG75451
SG75452
SG75453
SG75454
SN75451B
SN75452B
SN75453B
SN75454B
5-81
5-81
5-81
5-81
0
SG75461
SG75462
SG75463
SN75461
SN75462
SN75463
5-93
5-93
5·93
en
SG75473
SN75473
5-109
<
-...
~
(')
C
......
I»
SUGGESTED
TI REPLACEMENT
PAGE
NO.
UNITRODE
SUGGESTED
TI REPLACEMENT
PAGE
NO .
L293
L293
5-9
L293
SN754411*
5·159
L293D
L293D
5-13
L293D
SN754410'
5-153
L298
L298
5-17
PBL3717A
PBL3717A
5-19
* Consult product data sheet for possible slight product differences.
5-4
PAGE
NO.
SN75407*
SN75437A
UDN2841
UDN2845
SILICON
GENERAL
C
SUGGESTED
TI REPLACEMENT
UDM-5732
UDN-2541
UDN·2841
UDN-2845
"'tI
...
is'
::T
...!!!.
~
SPRAGUE
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
DS3680
QUAD TELEPHONE RELAY DRIVER
D2758, MARCH 1986
•
D, J OR N PACKAGE
(TOP VIEW)
Designed for - 52-V Battery Operation
•
50-mA Output Current Capability
•
Input Compatible with TTL and CMOS
AMPL #1 {'N+
AMPL # 2 { IN -
•
High Common-Mode Input Voltage Range
•
Very Low Input Current
•
Fail-Safe Disconnect Feature
IN IN +
BAT GND
OUTPUT AMPL # 1
OUTPUT AMPL # 2
OUTPUT AMPL # 3
AMPL #3 {'N+
OUTPUT AMPL #4
INBAT NEG
AMPL #4 IN- -.. _ _..r- IN+ AMPL #4
•
Built-In Output Clamp Diode
•
Direct Replacement for National DS3680
and Fairchild pA3680
description
The DS3680 telephone relay driver is a monolithic integrated circuit designed to interface - 48-volt relay
systems to TTL or other systems in telephone applications, It is capable of sourcing up to 50 milliamperes
from standard - 52-volt battery power. To reduce the effects of noise and IR drop between logic ground
and battery ground. these drivers are designed to operate with a common-mode input range of ± 20 volts
referenced to battery ground, The common-mode input voltages for the four drivers can be different. so
a wide range of input elements can be accommodated, The high-impedance inputs are compatible with
positive TTL and CMOS levels or negative logic levels. A clamp network is included in the driver outputs
to limit high-voltage transients generated by the relay coil during switching, The complementary inputs
ensure that the driver output will be "off" as a fail-safe condition when either output is open.
symbol leach driver)
IN+
15 k!l
:::I
BAT GNO
r-~--~--~-'-
NONINVERT*NG
INPUTIN+
+
.
OUTPUT
INVERTING
INPUT IN-
(I)
...u
schematic diagram leach driver)
BATTERY GROUND
...
Sas
The DS3680 is characterized for operation from - 25°C to 85 °C.
"0::
IN-
Q
"!CD
BATTERY NEGATIVE
~
c..
"0::
L -_ _......,......,___
OUTPUT
:.
~__~__~____~__________~~~BA~TNEG
PRODUCTION DATA d......nts contai. info,...tion
currant as of publi.ation data. P,od.cts co.lo,m to
_ilicllion. pa' tho tarm. of Tax•• lnatrumants
::'::~i~·i~:,~li =:~i:; 1Ir;::~~::.s nDt
Copyright @ 1986, Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
5-5
DS3680
QUAD TELEPHONE RELAY DRIVER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range at BAT NEG, VB- ................................ -70 V to 0.5 V
Input voltage with respect to BAT GND. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . .. - 70 V to 20 V
Input voltage with respect to BAT NEG ................................. -0.5 V to 70 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 V
Output current: resistive load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 100 mA
inductive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 50 mA
Inductive output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 H
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 3):
D package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 900 mW
J package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1650 mW
Operating free-air temperature range .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 25°C to 85 °C
Storage temperature range ......................................... - 65°C to 1 50°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............. 300°C
N package ............ 260°C
NOTES:
1. AU voltages are with respect to the BAT GND terminal, unless otherwise specified.
2. Differential input voltages are at the noninverting input terminal IN + with respect to the inverting input terminal IN -.
3. For operation above 25°C free-air temperature, derate linearly at the rate of 7.2 mW/oC for the 0 package, 8.2 mW/oC for
the J package, and 13.2 mW/oC for the N package.
recommended operating conditions
."
...CD
-6"
Supply voltage, VBInput voltage, either input
::s-
...
!!!..
...C
CD
..
<"
CD
1/1
MIN
MAX
-10
-60
V
20
V
V
-20
High·level differential input voltage, VIDH
Low-level differential input voltage, VIDL
Operating free-air temperature, T A
2
20
-20 l
0.8
V
-25
85
°C
tThe algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for input voltage
levels.
-52 V
electrical characteristics over recommended operating free-air temperature range, VB(unless otherwise noted)
i>
n
r+
C
PARAMETER
..
£I)
r+
o
IIH
TEST CONDITIONS
High-level input current (into IN +)
1/1
IlL
Low-level input current (into IN +)
VO(on) On-state output voltage
10 (off) Off-state output current
IR
Clamp diode reverse current
=2V
VID = 7 V
VID = 0.4 V
VID = -7 V
10 = 50 mA,
Va
=
Va
=0
VB-
VID - 2 V
I VID - 0.8 V
I Inputs open
10 - 50 mA
Output clamp voltage
IB(on)
On-state battery current
10 = -50 mA,
All drivers on
IB(off)
Off-state battery current
All drivers off
=
MIN
VID
VOK
tAli typical values are at TA
5-6
UNIT
VB-
=0
25°C.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
Typt
MAX
40
100
375
1000
0.01
5
UNIT
~A
~A
-1
-100
-1.6
-2.1
2
100
-2
-100
2
100
0.9
1.2
-0.9
-1.2
-2
-4.4
mA
1
100
~A
V
~A
~A
V
DS3680
QUAD TELEPHONE RELAY DRIVER
switching characteristics VBTurn-on time
toff
Turn-off time
MIN
TEST CONDITIONS
PARAMETER
ton
VID = 3-V pulse,
L = 1 H,
TYP
RL = 1 k!l,
See Figure 1
MAX
10
10
PARAMETER MEASUREMENT INFORMATION
BAT GND
VI---~
-52 V
-52 V
FIGURE 1, GENERALIZED TEST CIRCUIT, EACH DRIVER
f
....cas
BATGND
:::J
INPUT---I
U
>---1~-OUTPUT
«
...
CD
-
RL=1kfl
I I)
BAT NEG
>
L=1H
';:
C
ca...
-52 V
CD
TEST CIRCUIT
.c
INPUT ~_ _ _ _ _ _ _ _ _ _ _ _ _
,
- - - - - ' - +3V
,I ~
~ '"-~-t-offi 1
I
I
.;----ton
OUTPUT
-25
vy
-25
v\L
c.
';:
:.
0V
VO(on)
, "--"'-52V
VOLTAGE WAVEFORMS
FIGURE 2. SWITCHING CHARACTERISTICS, EACH DRIVER
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5-7
DS3680
QUAD TELEPHONE RELAY DRIVER
TYPICAL APPLICATION DATA
52VBATTERY
+111-
~r----~ ~----~~----------~
(1)
(2)
(9) OS3680
BAT NEG
(4)
(3)
(5)
(6)
(8)
I
I
L ___ .J
(7)
K1
r-
K2
b:-
---C
IN+ }
IN- AMPL#1
IN+ }
AMPL#2
IN-
---L
---L
IN+ }
AMPL#3
ININ+ }
IN- AMPL#4
K36-:-
CONTROL
SIGNAL
SOURCE
K4r-
-:.
-6"
.
o.
..
::T
CD
---C
OUT #4
K1 THRU K4
50-V RELAY COILS - 50 rnA MAX
BATGNO
(14)
!!.
~"
FIGURE 3. RELAY DRIVER
en
i>
~
C
.111
..
g
en
5-8
TEXAS •
INSTRUMENTS
POST OFFICE BOX 856012 • DALLAS, TeXAS 75285
L293
QUADRUPLE HALF-H DRIVER
ADVANCE
INFORMATION
02942. SEPTEMBER 1986
•
'-A Output Current Capability per Channel
•
Wide Supply Voltage Range:
4.5 V to 36 V
•
Separate Input-Logic Supply
•
Thermal Shutdown
•
Internal ESD Protection
•
High-Noise-Immunity Inputs
•
NE DUAL·IN·LlNE PACKAGE
nop VIEW)
1.2EN
1A
1Y
VCC1
4A
4Y
HEATSINK AND {
} HEATSINK AND
GROUND
2Y
GROUND
3Y
2A
VCC2
Designed to be Interchangeable with
SGS L293
0...0.;;""---''"'""
Y
L
X
L
Z
H
:2
H
L
H = high·level
L = low·level
x = irrelevant
Z = high·impedance (off)'
w
c.J
:2
~
C
«
•
...
II)
All inputs are TTL-compatible. Each output is a complete totem-pole drive circuit with a Darlington transistor
sink and a psuedo-Darlington source. Channels are enabled in pairs with channels 1 and 2 enabled by 1,2EN
and channels 3 and 4 enabled by 3,4EN. When an enable input is high, the associated channels are enabled
and their outputs are active and in phase with their inputs. When the enable input is low, those channels
are disabled and their outputs are off and in a high-impedance state. With the proper data inputs, each
pair of drivers form a full-H (or bridge) reversible drive suitable for solenoid or motor applications.
External high-speed output clamp diodes should be used for inductive transient suppression. A VCCl
terminal, separate from VCC2, is provided for the logic inputs to minimize device power dissipation.
Sca
....U:::J
~
~
CD
>
'C
c
'!CD
The L293 is designed for operation from O°C to 70°C.
.c
c.
logic diagram
logic symbol t
a:
3,4EN
OUTPUT
EN
H
H
A
The L293 is a quadruple high-current half-H
driver designed to provide bidirectional drive
currents of up to one ampere at voltages from
4.5 volts to 36 volts. It is designed to drive
inductive loads such as relays, solenoids, dc and
stepping motors, as well as other highcurrent/high-voltage loads in positive-supply
applications.
~
3A
(EACH CHANNEL)
description
i=
«
oLL
FUNCTION TABLE
INPUTS
:2
o
'C
C>
Q
:.
(3) lY
EN
EN
C>
C>
Q
(11)
Q
3Y
Q
(14) 4Y
EN
EN
C>
(6) 2Y
t This svmbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
Copyright @ 1986. Texas Instruments Incorporated
ADVANCE INFORMATION documants cD.tai.
~~~=!~rD:;h= J':!~~~'::'°C:::::=':~
~ata ond othar specifications are •• bjact to change
without notice.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
5-9
L293
QUADRUPLE HALF·H DRIVER
»
c
ADVANCE
INFORMATION
schematics of inputs and outputs
~
2
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
---e----~._------VCC2
VCC,------~~---
(")
m
:2
'TI
o
::a
s:
. - - - - - - - OUTPUT
INPUT
~
o-
GND--~--~~--------
2
---4~--~~------GND
•
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
2'
Logic supply voltage, VCC1 (see Note 1) ......................................... 36 V
Output supply voltage, VCC2 .........................•....................... 36 V
Input voltage .............................................................. 7 V
Output voltage range .. , ........................................ -3 V to VCC2+3 V
Peak output current (nonrepetitive, t s 5 ms) .................................... ± 2 A
Continuous output current . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. ± 1 A
Continuous total dissipation at (or below) 25°C free-air temperature
(see Notes 2 and 3) ................................................. 2075 mW
Continuous total dissipation at (or below) 25°C case temperature (see Note 3) ........ 7375 mW
Continuous total dissipation at 80°C case temperature (see Note 3). . . . . . . . . . . . . . . .. 4130 mW
Operating case or virtual junction temperature range ...................... - 40°C to 150°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 260°C
til
NOTES: 1. All voltage values are with respect to the network ground terminal.
2. For operation above 25°C free-air temperature, derete linearly at the rate of 16.6 mW/oC.
3. For operation above 25°C case temperature. derate linearly at the rate of 59 mW/oC. Due to variations in individual device
-:
:::!.
~
CD
;
-
57
:C.
!
_
~,
a
o
electrical characteristics and thermal resistance, the built·in thermal overload protection may be activated at power levels
slightly above or below the rated dissipation.
recommended operating conditions
MIN
4.5
Logic supply voltage, VCC1
Output supply voltage, VCC2
VCCl
2.3
IVCC1 :s7V
High-level input voltage, VIH VCCl
l!:7V
Low-level input voltage, VIL
I
Output current, 10
Operating free-air temperature, T A
MAX
7
36
2.3
-0.3
VCC'
7
1.5
±1
0
70
UNIT
V
V
V
V
A
°c
tThe algebraic convention, in which the least positive (most negative) designated minimum, is used in this data sheet for logic voltage levels.
5-10
,
TEXAS""
INSTRUMENTS
POST OFFICE BOX 65&012 • DALLAS. TEXAS 75265
ADVANCE
INFORMATION
L293
QUADRUPLE HALF-H DRIVER
electrical characteristics. VCC1 - 5 V. VCC2 - 24 V. TA - 25 0 C
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
IIH
High-level input current
',L
Low-level input current
ICCl
Logic supply current
ICC2
TEST CONDITIONS
-1 A
IOH =
10L - 1 A
A
7N-
V,
=7
~
V,
=0
10
=0
EN
Output supply current
10
=0
2
MIN
TYP
MAX
V
VCC2 -1.8 VCC2 - 1.4
1.2
0.2
V
0.2
-3
-2
UNIT
1.8
100
V
±10
-10
-100
All outputs at high level
22
All outputs at low level
60
All outputs at high impedance
24
All outputs at high level
All outputs at low level
24
All outputs at high impedance
TEST CONDITIONS
tpLH
Propagation delay time, low-to-high-Ievel output from A input
tpHL
Propagation delay time, high-to-Iow-Ievel output from A input
tTLH
Transition time, low-to-high-Ievel output
tTHL
Transition time, high-to-Iow-Ievel output
MIN
TYP
pA
oLL
rnA
UNIT
ns
ns
400
300
300
ns
ns
5 V
PULSE
GENERATOR
(See Note AI
24V
VCCl VCC2
INPUT
A
2
C
.~
I - - - - - t w - -.........
I
c
I
I
1
1
I
1
.c
i4---*- tPHL
TEST CIRCUIT
(.)
:l
~9~0%~--3V
Y
3V
-2w
...oen
PARAMETER MEASUREMENT INFORMATION
INPUT
a:
~
MAX
800
CL = 30 pF,
See Figure 1
VCC2
(3)
~
2
EN
~
(1)
EN
:D
I>
(7)
~
::!
"
(6)
"
(11)
"
(14)
I>
o
<1>1
(10)
2
EN
CONTROL B
0
EN
(9)
I>
(15)
MOTOR
GND
ALL DIODES: 1N4935
14.5.12.13)
':'
':'
FIGURE 2. TWO·PHASE MOTOR DRIVER
5-12
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
L293D
QUADRUPLE HALF·H DRIVER
ADVANCE
INFORMATION
02942. SEPTEMBER 1986
•
•
•
600-mA Output Current Capability per
Channel
NE DUAL·IN-liNE PACKAGE
Output Clamp Diodes for Inductive Transient
Suppression
1,2EN
Wide Supply Voltage Range:
4.5 V to 36 V
4A
1Y
4Y
J
Separate Input-Logic Supply
•
Thermal Shutdown
•
Internal ESD Protection
•
High-Noise-Immunity Inputs
•
Designed to be Interchangeable with
SGS L293D
VCC2
~
VCCl
lA
~
} HEATSINK AND
HEATSINK AND
GROUND)
2Y
2A
•
z
o
(TOP VIEWI
a:
GROUND
3Y
3A
--":'----';.1-'
ou.
Z
w
3,4EN
(,)
FUNCTION TABLE
z
(EACH CHANNELl
INPUTS
description
The L293D is a quadruple high-current half-H
driver designed to provide bidirectional drive
currents of up to 600 milliamperes at voltages
from 4.5 volts to 36 volts. It is designed to drive
inductive loads such as relays, solenoids, dc and
stepping motors, as well as other highcurrent/high-voltage loads in positive-supply
applications.
o
·C
c
A VCC1 terminal, separate from VCC2, is provided for the logic inputs to minimize device power dissipation.
"!CD
The L293D is designed for operation from OOC to 70°C.
logic symbol t
logic diagram
lA (21
C>
EN
EN
C>
C>
EN
EN
4A (151
.c
c.
·C
C>
'\J
'\J
'\J
'\J
d?
(3l ly
(61 2y
(111 3y
(141 4y
tThis symbol is in accordance with ANSI/lEEE Std 91-1984 and
IEC Publication 617-12.
Copyright @ 1986, Texas Instruments Incorporated
ADVANCE INFORMATION documants contain
~~:'~3~~~::h=.s'3!",c;.:::.:.~::;:~:::r.:~
iIati and other specifications are subjaollO ....nga
withaut notice.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
5-13
L293D
QUADRUPLE HALF-H DRIVER
»
o
ADVANCE
INFORMATION
schematics of inputs and outputs
~
2
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
---1~----~-.-----VCC2
VCC1-----.....,,....---
(")
-m
CURRENT
SOURCE
2
."
o
:xJ
~
.............--OUTPUT
INPUT
!:i
o2
GND--~--~~---------~.---~---~--GND
absolute maximum ratings over operating free-air
temperatur~
range (unless otherwise noted)
Logic supply voltage, VCC1 (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 36 V
Output supply voltage, VCC2 ............. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 36 V
Input voltage .............................................................. 7 V
Output voltage range ........................................... - 3 V to VCC2 + 3 V
Peak output current (nonrepetitive, t s 100 "s) ................................. ± 1.2 A
Continuous output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 600 rnA
Continuous total dissipation at (or below) 25°C free-air temperature
(see Notes 2 and 3) ................................................. 2075 mW
Continuous total dissipation at (or below) 25°C case temperature (see Note 3) ........ 7375 mW
Continuous total dissipation at 80°C case temperature (see Note 3). . . . . . . . . . . . . . . .. 4130 mW
Operating case or virtual junction temperature range ...................... - 40°C to 1 50°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 260°C
NOTES: 1. All voltage values are with respect to the network ground terminal.
2. For operation above 25°C free-air temperature, derate linearly at the rate of 16.6 mW/oC.
3. For operation above 25 DC case temperature, derate linearly at the rate of 59 mW/DC. Due to variati9ns in individual device
electrical characteristics and thermal resistance, the built-in thermal overload protection may be activated at power levels
slightly above or below the rated dissipation.
recommended operating conditions
MIN
4.5
Logie supply voltage, VCC1
Output supply voltage, V CC2
VCCl
2.3
!VCCl s7V
High-level input voltage, VIH ! VCCl
;,,7V
2.3
-0.3 t
Low-level input voltage, VIL
Output current, 10
Operating free-air temperature, T A
0
MAX
7
36
VCCl
7
1.5
±600'
70
UNIT
V
V
V
V
mA
°C
t The algebraic convention, in which the least positive (most negative) limit is designated minimum. is u.sed in this data sheet for logic
voltage levels.
5-14
TEXAS . "
INSTRUMENTS
POsrOFFICE BOX 655012 • DALLAS. TEXAS 75265
ADVANCE
INFORMATION
L293D
QUADRUPLE HALF-H DRIVER
electrical characteristics. VCC1
5 V. VCC2 = 24 V. TA = 25°C
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = -0.6 A
Val
Low-level output voltage
10l - 0.6 A
VOKH
High-level output clamp voltage
10K - 0.6 A
VOKL
Low-level output clamp voltage
10K -
IIH
High-level input current
III
ICCI
ICC2
Low-level input current
~
A
~
Logic supply current
TYP
UNIT
V
I.B
V
V
VCC2+ 1.3
1.3
VI =7V
VI = 0
10 = 0
MAX
VCC2-1.8 VCC2-1.4
1.2
-0.6 A
10 = 0
Output supply current
2:
MIN
V
0.2
100
0.2
±10
-3
-10
-2
-100
All outputs at high level
22
All outputs at low level
60
All outputs at high impedance
24
All outputs at high level
24
All outputs at low level
6
All outputs at high impedance
4
switching characteristics. VCC1 - 5 V. VCC2
TEST CONDITIONS
tplH
Propagation delay time. low-to-high-Ievel output from A input
tpHl
Propagation delay time, high-to-Iow-Ievel output from A input
tTLH
Transition time, low-to-high-Ievel output
tTHl
Transition time, high-to-Iow-Ievel output
MIN
TYP
i=
«
:?!
a:
p.A
oLL
p.A
2:
mA
(.)
w
2:
mA
24 V. TA
PARAMETER
o
MAX
UNIT
800
ns
Cl = 30 pF,
400
ns
See Figure 1
300
ns
300
ns
«
>
c
«
•-.
!II
o
ca
PARAMETER MEASUREMENT INFORMATION
5 V
INPUT
u
.;:
1.5 V
I
I
OUTPUT
10%
~tw
l(seo
CL-30pF
Note B)
EN
-
3V
90%
PULSE
GENERATOR
(Soe Note A)
3V
::::s
I
I
I
~tpHL
-::'
..
-1-----0
~I
'ii
CD
.c
I
I
I
c.
.;:
d?
~tPLH
I
TEST CIRCUIT
c
I
I
I
90% VOH
I
OUTPUT
HtTHL
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: tr S IOns, tf S IOns, tw = 10 ~s, PRR = 5 kHz, lout = 50 O.
B. CL includes probe and jig capacitance.
FIGURE 1. SWITCHING TIMES
.
TEXAS"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
5-15
L293D
QUADRUPLE HALF·H DRIVER
»c
»2<
TYPICAL APPLICATION DATA
5V
(')
2
'\I
(2)
CONTROL A
~(3:.:.)_ _ _ _ _ _..,
EN
."
(1)
o:rJ
s:
I>
EN
(7)
»
-I
'\I
(6)
'\I
(11)
I>
6
(10)
2
•
24V
10 kll
m
-
ADVANCE
INFORMATION
~1
~2
EN
(9)
EN
CONTROL B
I>
'\I (14)
(15)
GND
14.5.12.13)
FIGURE 2. TWO·PHASE MOTOR DRIVER
5-16
TEXAS •
INSTRUMENTS
POST OFFICE BOX 6550.12 • DALLAS, TEXAS 75265
0
MOTOR
PRODUCT
PREVIEW
L298
DUAL FULL·H DRIVER
02942. OCTOBER 1986
2 A Per Channel Output Capability
•
Wide Range of Output Supply
Voltage ... 5 V to 46 V
•
Saparate Input-Logic Supply Voltage
•
Thermal Shutdown
•
Internal Electrostatic Discharge Protection
•
High Noise Immunity
•
~
w
KV PACKAGE
(TOP VIEW)
•
-$8
Direct Replacement for SGS L298
description
The L298 is a dual high-current full-H driver
designed to provide bidirectional drive currents
of up to two amperes at voltages from 5 volts
to 46 volts. It is designed to drive inductive loads
such as relays, solenoids, dc motors, stepping
motors, and other high-current or high-voltage
loads in positive-supply applications. All inputs
are TTL compatible. Each output (VI is a
complete totem-pole drive with a Darlington
transistor sink and a psuedo-Darlington source.
Each full-H driver is enabled separately. Outputs
1Vl and 1V2 are enabled by 1 EN and outputs
2Vl and 2V2 are enabled by 2EN. When an EN
input is high, the associated channels are active.
When an EN input is low, the associated
channels are off (Le., in the high-impedance
state).
Each half of the device forms a full-H reversible
driver suitable for solenoid or motor applications.
The current in each fulI-H driver can be
monitored by connecting a resistor between the
sense output terminal 1E and ground and another
resistor between sense output terminal 2E and
ground.
15
14
13
12
11
10
9
8
-$-
7
6
5
4
3
2
2E
2Y2
2Yl
2A2
2EN
2Al
VCCl
GND
lA2
lEN
lAl
VCC2
lY2
lYl
lE
:>w
a:
c.
I-
o
:::l
C
oa:
c.
The tab is electrically connected to pin 8.
logic symbol t
•
t This symbol is in accordance with ANSI/IEEE Sid 91-1984 and
IEC Publication 617-12.
External high-speed output-clamp diodes should
be used for inductive transient suppression. To
minimize device power dissipation, a VCCl
supply voltage, separate from VCC2, is provided
for the logic inputs.
PRODUCT PREVIEW documents contain information
on produeta in the formative Dr design ~h••e of
dava.apmaot. Characteristic data anil othar
=:U::Sri~:t d:i::B=::I~rT::~::r:~:::
produeta withDI! notice.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
5-17
L298
DUAL FULL·H DRIVER
."
PRODUCT
PREVIEW
logic diagram (positive logic)
:D
o
lYl
lY2
(2)
VCC2
(4)
(31
2Yl
2Y2
(13)
(14)
C
c:
o-I
."
:D
m
<
iii
:e
lA1.;.;(5,,-1_>-f-d-""
(12) 2A2
1A2~(7~)--~r-------------r-------------~
1EN~(6~)--~~----------__t-__________~
(10) 2A1
(1)
(11) 2EN
1(151
2E
lE
absolute maximum ratings over operating temperature (unless otherwise noted)
Logic supply voltage, VCC1, (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Output supply voltage, VCC2 ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 50 V
Input voltage .............................................................. 7 V
Emitter output (1 E and 2E) voltage .......................'................. -1 to 2.3 V
Peak output current (nonrepetitive, tw oS 0.1 ms), . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 3 A
(repetitive, tw oS 10 ms, duty cycle oS 80%) . . . . . . . . . . . . . . . . . . .. ±2.5 A
Continuous output current ..... ~ ............................... ; . . . . . . . . . . . .. ± 2 A
Continuous total power dissipation at 75°C case temperature (see Note 2) ............... 25 W
Operating case or virtual junction temperature range ...................... - 40°C to 150°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds. . . . . . . . . . . . . . . . . .. 260°C
•
-:
::2.
'0
:r
...
...C
~.
...
en
CD
!!.
~c
S
Ul
NOTES: 1. All voltage values are with respect to the network ground terminal.
2. The absolute maximum power dissipation ratings are design goals. For further information contact the factory .
recommended operating conditions
MIN
MAX
4.5
7
46
UNIT
VCC1
Logic supply voltage
VCC2
VIH
Output supply voltage
High-level input voltage
2.3
VCe1
V
VIL
Low-level input voltage
. -0.3 t
1.5
V
10
Output current
TA
Operating free-air temperature
VIH
+ 2.5
0
V
V
±2
A
70
°c
tThe algebraic convention, in which the least positive (most negative designated minimum), is used in this data sheet for logic voltage levels.
5-18
TEXAS ."
INSTRUMENTS
POST OFFice BOX 655012 • DALLAS. TeXAS 75265
PRODUCT
PREVIEW
PBL3717A
STEPPER MOTOR DRIVER
02985. FEBRUARY 19B7
•
Three Operating Modes ... Full Step, Half
Step, and Quarter Step
•
Both Digital and Analog Control of Output
Current
NE PACKAGE
3:
w
ITOPVIEWI
Y2
E
RC
l-Ampere Bidirectional Output Current
Capability
VCC2
GNO
GNO'
•
Chop-Mode Current Regulation
VCC1
•
Wide Output Supply Voltage
Range . . . 10 V to 46 V
GNO
GNO
REF
COMP
•
Separate Input-Logic Supply
•
Thermal Shutdown Protection
•
Output Clamp Diodes for Inductive Transient
Protection
•
:>w
Y1
VCC2
11
a:
Q.
....
CJ
OIR '-C::.-....:~ 10
::;)
o
o
FUNCTION TABLE
LOGIC INPUTS
•
Internal ESD Protection
•
Direct Replacement for SGS PBL3717A
DIR
H
~
H
10
L
L
L
H
~
H
L
X
H
H
~
H
description
11
a:
Q.
OUTPUTS
Y1
Y2
Source
Sink
Sink
Source
Source
Sink
Sink
Source
Source
Sink
Sink
Source
LEVEL
High Current
Medium Current
•
Low Current
Off
The PBL3717 A is a high-current, high-voltage
full-H reversible driver designed to control and
drive one phase of a bipolar stepper motor. It is
designed to provide bidirectional drive currents
of up to one ampere at voltages from 10 volts to 46 volts in positive-supply applications. Two PBL3717 A
devices, with a few external components, form a complete two-phase bipolar stepper motor driver. All
inputs are TTL-compatible. Each output (Y) forms a complete totem-pole drive with a Darlington transistor
sink and a psuedo-Darlington source. Logic input pin DIR selects the direction of current flow in a load
connected between outputs Y1 and Y2. A high level at the DIR input causes the load current to flow from
output Yl (source) to output Y2 (sink). A low level at the DIR input causes the load current to flow from
output Y2 (source) to output Y1 (sink). When logic. inputs 10 and 11 are both high, the Y1 and Y2 outputs
are disabled and in the high-impedance state.
The current in the full-H driver load can be monitored by connecting a resistor between the sense output
terminal E and ground. Voltage feedback from terminal E to the COMP input pin provides output current
regulation via chop-mode operation of the sink output transistors. Three levels of output current can be
selected by programming two logic inputs, 10 and 11, as shown in the function table. These inputs are
internally decoded to enable one of three comparators to set the output current level to low, medium,
or high. The precise level of output current is set by the comparator selected, the comparator reference
voltage applied to the REF pin, the value of the sense resistor, and the sense output voltage fed back to
the COMP input. When chop-mode current regulation is used, an internal monostable circuit, programmed
by an external RC network at ~he RC pin, sets the current decay time.
The device contains built-in high-speed output clamp diodes for inductive transient protection. A separate
supply voltage (VCC1) is provided for the logi<; input circuits to minimize device power dissipation. Supply
voltage VCC2 is used for the output circuits. Both VCC2 supply pins should be connected together as
close to the package as possible.
The PBL3717 A is characterized for operation from OOC to 70°C.
PRODUCT PREVIEW do.umen...ontain information
OR products in the farmative or design ,hase of
development. Characteristic data anil other
spacificatiolll are design goals. Tuas Instruments
raserves the right to change Dr discontinue these
p..d.... witho.t noli•••
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 76265
Copyright © 1987, Texas Instruments Incorporated
5-19
PBL3717A
STEPPER MOTOR DRIVER
."
:0
PRODUCT
PREVIEW
logic diagram (position logic)
gc:
10-,=(9;..1_ _ _
-+-~.-~~---.,
VCC2
(141
VCC2
(31
11~(7~1______~;-~;-~~--,
o-I
REF
(151 Y1
(111
COMP(~10~1+---'-~~__~__+-~
+-__________+-__~(1__1 Y2
DIR~18~1~~1-------~---4--+-~
•
o
GND--~~~------------------~--~------------------~
(4.5.12.131
(181
E
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
::I.
Output supply voltage. VCC2 (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 50 V
Logic supply voltage. VCC1 ................................................... 7 V
Logic input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6 V
Comparator input voltage .................................................... VCC1
Reference voltage. Vref. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 V
Continuous output current ................................................. ± 1.2 A
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 3) . . . . . .. 2075 mW
Continuous total dissipation at (or below) 25 DC case tem'perature (see Note 3) ........ 7375 mW
Operating case or virtual junction temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OOC to 150 DC
Storage temperature range ......................................... - 65 DC to 150°C
Lead temperature 1.6 mm (1/16 inch) from the case for 10 seconds ................... 260°C
<
CD
~
..
~
Ii
o
Cil
NOTES: 1. All voltage values are with respect to the GND terminal.
2. Both VCC2 pins must be connected together as close to the package as possible for optimum testing and operation of the device,
3. For operation above 25°C free-air temperature. derate linearly at the rate of 16.6 mW/oC. For operation above 25°C case
temperature, derate linearly at the rate of 59 mW/DC. To avoid exceeding the design maximum virtual junction temperature.
these ratings should not be exceeded. Due to variations in individual device electrical characteristics and thermal resistance,
the built-in thermal overload protection may be activated at power levels slightly above or below the rated dissipation,
5-20
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
PBL3717A
STEPER MOTOR DRIVER
PRODUCT
PREVIEW
UNIT
:=w
V
V
V
V
a:
a..
recommended operating conditions
MIN
10
4.75
2
Output supply voltage, VCC2
logic supply voltage, VCC1
High-level input voltage, VIH
low·level input voltage, Vll
Output current, 10
MAX
46
5.25
VCC1
O.S
0
Operating free-air temperature, T A
±1
70
A
'c
:>w
I(.)
:::::>
c
oa:
Q.
•....
..
!II
o
CO
::l
U
c
.
c(
~
Q)
>
";:
iii
Q)
.c
Q.
";:
~
TEXAS •
INSTRUMENlS
POST OFFICE BOX 656012 • DALLAS, TeXAS 75265
5-21
•
..
..
..c
<'
..
"'C
CD
'6'
::T
CD
~
CD
(I)
i>
(')
....
C
I»
....
o
..
(I)
5-22
SN7506' SN75065, SN75066, SN75067
QUADRUPLE HIGH-CURRENT DARLINGTON SWITCHES
02620, FEBRUARY 19B1-REVISED SEPTEMBER 1986
•
•
•
•
•
•
•
•
Output Collector Current ... 1,5 A Max
NE
DUAL-IN-L1NE PACKAGE
2-W Dissipation Rating
(TOP VIEWI
High Output Voltage Capability
Outputs Diode-Clamped for Inductive Loads
Common-Emitter Circuit for Current Sink
SN75064 and SN75065 Have TTLCompatible Inputs
SN75066 and SN75067 Have CMOS- and
PMOS-Compatible Inputs
Functionally Interchangeable with ULN 2064
thru ULN2067. Respectively
CLAMP
1C
1B
E, SUBSTRATE, {
AND HEATSINK
2B
2C
CLAMP
4C
NC
4B
} E, SUBSTRATE,
AND HEATSINK
3B
NC
3C
NC - No internal connection
schematic (each Darlington pair)
description
....."'II--CLAMP
The SN75064. SN75065. SN75066. and
SN75067 are monolithic high-voltage. highcurrent Darlington transistor switches. Each
comprises four n-p-n Darlington pairs. All units
feature high-voltage outputs with commoncathode clamp diodes for switching inductive
loads. Outputs and inputs may each be paralleled
for higher current capability. Applications include
relay drivers. hammer drivers. lamp drivers.
display drivers (LED and gas discharge). line
drivers. and logic buffers. These CDmmonemitter circuits are designed to operate as
current sinks to the load.
The SN75064 and SN75065 are intended for
use with TTL and 5-volt MOS logic. The
SN75066 and SN75067 are intended for use
with PMOS and higher voltage CMOS logic.
.,r--<"'~~-OUTPUT
C
•
INPUT 8_"""...--1
7.2 k[J NOM
.
3 k[J NOM
en
...oco
E
...::s
CJ
--fe
';:
c
..
iii
G)
The SN75064 thru SN75067 are characterized
for operation from OOC to 70°C.
~
Q.
';:
G)
a.
logic symbol t
(11 CLAMP
(81 CLAMP
18 (31
(21 1c
28 (61
E=~~(712C
38 (111
48 (141
(91 3C
(161 4C
tThis symbol is in accordance with ANSI/IEEE Std 91- 1984 and
IEC Publication 61 7 -12.
PRODUCTIOI DATA docoma.1s co.tai. infarmatio.
currant as of publication date. Products conform to
specifications per the terms of Texas Instruments
:.~~:~~;at::1~1i ~~:~::I:; :1~D::~:::::t:is~S not
Copyright © 1981, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • 'DALLAS, TEXAS 75265
5-23
SN75064, SN7506L SN7506L SN75067
QUADRUPLE HIGH-CURRENT DARLINGTON SWITCHES
absolute maximum ratings at 25°e free-air temperature for each switch (unless otherwise noted)
SN75064
SN75065
SN75066
SN75067
UNIT
Collector-emitter voltage
50
80
50
80
V
Input voltage (see Note 1)
15
15
30
30
V
Peak collector current (see Figures 12, 13, and 14)
1.5
1.5
1.5
1.5
A
Input current
25
25
25
25
rnA
mW
Total power dissipation at (or below) 25°C
free-air temperature (see Note 2)
Operating free-air temperature range
Storage temperature range
Lead temperature 1,6 mm (1/16 inch)
from the case for 10 seconds
2075
2075
2075
2075
o to 70
o to 70
o to 70
o to
70
°C
-55 to 150
-55 to 150
-55 to 150
-55 to 150
°C
260
260
260
260
°C
NOTES: 1. All voltage values (unless otherwise noted) are with respect to the emitter/substrate terminal E.
2. For operation above 25°C free-air temperature, derate to 1328 mW at 70°C at the rate of 16.6 mW/oC.
electrical characteristics at 25°e free-air temperature (unless otherwise noted)
TEST
PARAMETER
•
..
..
..
"tI
FIGURE
Collector sustaining
VCEX(sus) voltage
Collector output
ICEX
CD
cutoff current
1
2
-6-
:T
CD
On-state
Ilion)
!!.
input current
On-state
Vllon)
4
input voltage
Ul
....
..
i>
n
c
II)
VI = 0.4 V,
IC = 100 mA
SN75064
SN75065
SN75066
SN75067
MIN MAX
MIN MAX
MIN MAX
MIN MAX
35
50
VCE = 50 V
100
VCE - 50 V, TA - 70°C
500
35
Collector-emitter
VCE(sat)
saturation voltage
5
500
100
100
VCE - 80 V, TA - 70°C
VI - 2.4 V
500
500
VI - 3.75 V
2
4.3
2
4.3
4.5
9.6
4.5
9.6
0.9
VI - 5V
VCE - 2 V,
IC - 1 A
VCE - 2 V,
See Note 3
IC - 1.5 A,
reverse current
6
2
6.5
6.5
2.5
10
10
II = 6251'A, IC = 500 mA
1.13
1.13
1.13
1.13
II - 935 p.A, Ic - 750 mA
11= 1.25 mA,lc = 1 A
1.25
1.25
1.25
1.25
1.4
1.4
1.4
1.4
II - 2 mA,
VR - 50 V,
IC - 1.25 A,
1.6
1.7
Clamp-diode
forward voltage
7
IF - 1.5 A,
100
100
50
50
100
100
1.75
1.75
1.75
1.75
2
2
2
2
See Note 3
NOTE 3: These parameters must be measured on one output at a time using pulse techniques, tw = 10 ms, duty cycle
switching characteristics at 25°e free-air temperature, Vee
PARAMETER
Propagation delay time, high-to-Iow-Ievel output
s
5 V
TEST CONDITIONS
Propagation delay time, low-to-high-Ievel output
5-24
=
V
50
TA = 70°C
IF - 1 A
mA
1.7
50
TA - 70°C
I'A
V
1.6
VR - 80 V
VR = 80 V,
VF
1.8
5.2
2
VR - 50 V
Clamp-diode
0.9
5.2 2.75
2.5
See Note 3
IR
1.8
2.75
II = 2.25 mA,lc = 1.5 A,
(I)
V
VCE = 80 V
See Note 3
o
50
UNIT
100
VI - 12 V
C
~-
3
TEST CONDITIONS
See Figure 8
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
MIN
TYP
MAX
1.5
I'A
V
10%.
SN7506' SN75065. SN75066. SN75067
QUADRUPLE HIGH·CURRENT DARLINGTON SWITCHES
PARAMETER MEASUREMENT INFORMATION
OPEN
OPEN
VCE
ICEX
+--
OPEN
FIGURE 1. VCEX(sus)
FIGURE 2. ICEX
OPEN
OPEN
;lC~""'-OPEN
FIGURE 3. Ilion)
FIGURE 4. Vllon)
•
OPEN
OPEN
FIGURE 6. IR
FIGURE 5. VCE(sat)
FIGURE 7. VF
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
5-25
•
SN75064, SN75065, SN75066, SN75067
QUADRUPLE HIGH·CURRENT DARLINGTON SWITCHES
PARAMETER MEASUREMENT INFORMATION
~
-"""VIH
.--_t--35V
CLAMP
INPUT
68 n,2W
-t-4--
;>c)-....
PULSE
GENERATOR
(.88 Not. AI
:
tpHL ---Ii
OUTPUT
CL = 15 pF
(... Notoa)
(... Note C)
50%
50%
:
.--
OV
......
..- tpLH
Ir
VOH
~
OUTPUT
I 50%
50%
---VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 50 kHz, duty cycle
B. CL includes all probe and stray capacitance.
.
C. VIH = 2.5 V for SN75064 and SN75065. VIH = 10 V for SN75066 and SN75067.
= 10%, Zo = 50 II.
.
FIGURE 8, SWITCHING TIMES
ELECTRICAL CHARACTERISTICS
SN75064, SN75065
SN75068, SN75067
INPUT CURRENT
TA':z\tC
No .....
See Figure 3
V
., 10
/
1.6
TA"~5°C
VeE" VCE(lIt)
TA·2S·C
Nolood
See Figure 3
V
~/
j
!.
"
BASE CURRENT
INPUT VOLTAGE
14
12
TYPICAL COLLECTOR CURRENT
INPUT CURRENT
'"
INPUT VOLTAGE
¥
/~'v""~
V .........v
*
1.
::...
o0
V
1--
10
VI-Input Vottagll-V
I
'I'
1"0
~~
~~
~
v1
~75064.lN750
CHARACTERIZED ONLY
8ARE
j
V
UP TO THIS POINT
0 ••
/
1/
12
0.5
1.5
2••
la-8_ Current-mA
VI-Input Voltage-V
FIGURE 9
,/
Duty Cycle· 90%
FIGURE 10
FIGURE 11
THERMAL INFORMATION
MAXIMuM COLLECTOR CURRENT
MAXIMUM COLLECTOR CURRENT
DUTY CYCLE
DuTY CYCLE
2.0
TA-26"C
N'" Number of Outputs
1i 1.5
Ii
\
1..0
Il
"-J
r--- . . . ,.J./....
.~
~o .
•
0
o
"'.'f!::.i"":f-..
--
10 20 30 40 50 60 70 80 90 100
Duty Cycle-%
FIGURE 12
5-26
~
I~
I"
r-....
E
1,.
-
Conducting Simu!tllneou_iy
DUTY CYCLE
2.0
2.0
TA-50'C.
N .. Number of Outpuu
Conducting SimuttiMOusly
1E
~ 1.S
l\ \
j
8
\
1.0
!
~ 0.5
o
o
i'\. "i"- l"
MAXIMUM COLLECTOR CURRENT
"
"
-
TA' 70"C
N = Number of OutpUU
Conducting Shnultlneously
-;- !-
1\'
~~ r::::
"'N~ ~
f:;:
~~ r-
'.
Duty Cycle-%
FIGURE 13
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TEXAS 76266
'"
."'r--. ,~"'.l'
"\
~~
~
r- r-
10 20 30 40 50 60 70 80 90 100
k\
- !-!-
--
"'j" r- -::
o
o
lQ 20 30 40 50 60 70 80 90 100
Duty Cycle-'J6
FIGURE 14
SN75064, SN75065, SN75066, SI75067
QUADRUPLE HIGH·CURRENT DARLINGTON SWITCHES
TYPICAL APPLICATION DATA
Vee
I
j
~
TMS11100
,.......J
---,
~
1
18
2
15
3
14 f-
4 SN75066 13
6
12
1j
~
~
8
llf-
7
10
8
9
FIGURE 15. RELAY DRIVER INTERFACE
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DAUAS, TEXAS 75265
•
5·27
5-28
SN75068, SN75069
QUADRUPLE HIGH-CURRENT DARLINGTON SWITCHES
02621. DECEMBER 1979- REVISED FEBRUARY 1987
•
Output Collector Current ... 1.5 A Max
•
2-W Dissipation Rating
•
High Output-Voltage Capability
•
Preamp for High Current Gain
•
Outputs Diode-Clamped for Inductive Loads
•
Common-Emitter Circuit for Current Sink
•
Inputs Compatible with TTL and 5-Volt
CMOS
•
NE
DUAL·IN-UNE PACKAGE
(TOP VIEW)
CLAMP
4C
lC
4B
1B
E. SUBSTRATE.
AND HEATSINK
2B
VCC
E. SUBSTRATE.
AND HEATSINK
3B
t
!
1
5
NC
3C
2C '-l.:"---_~ CLAMP
Functionally Interchangeable with ULN2068
and ULN2069
NC - No· internal connection
schematic leach switch)
description
The SN75068 and SN75069 are monolithic
integrated circuits each consisting of four highvoltage. high-current n-p-n cascaded transistor
switches. Each switch includes a first stage
compatible with both TTL and 5-volt CMOS
signal levels. The second and third stages form
uncommitted-collector outputs with commoncathode clamp diodes for switching inductive
loads.
The SN75068 and SN75069 can sink up to
1.5 amperes per switch. Applications include
logic buffers. MaS drivers. memory drivers. line
drivers. relay drivers. hammer drivers. lamp
drivers. and display drivers (LED and gas
discharge) .
VCC
900
INPUT
n
2.5 kO
CLAMP
r---""t---
B
C
l!!
....oas
....::::sCJ
~
l!!
Q)
>
'0:::
Resistor values shown are nominal.
,
logic diagram
(11
CLAMP
The SN75068 and SN75069 are characterized
for operation from OOC to 70°C.
Q
(9)
ca...
CLAMP
lB
logic symbol t
II
OUTPUT
(31
(2)
lC
Q)
~
Q.
'0:::
CLAMP
(6)
(81
2B
:.
2C
CLAMP
(3)
1C
18
(6)
(8)
28
(11 )
38
48
2C
(10)
3B
(11)
(10)
~"';""I-~
3C
3C
(15)
(16)
4C
(15)
tThis symbol is in accordance with ANSIIIEEE Std 91·1984 and
IEC Publication 617-12.
4B - - - t - - f
(13)
E
PRODUCTlOII DATA ilocuments cantaln information
.un..t .. of publication dalo. Products conform to
opocilicationo por the terms of Te••• Inotruments
:':~:~~i~a{::I~'li ~~~~~:r :.~a:==::~~~ not
E
E
E
Copyright © 1981, Texas Instruments Incorporated
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
5-29
SN75068. SN75069
QUADRUPLE HIGH-CURRENT DARUNGTON SWITCHES
absolute maximum ratings at 25°e free-air temperature for each switch (unless otherwise noted)
SN75068
SN75069
UNIT
Collector-emitter voltage
50
80
Supply voltage, VCC (see Note 1)
10
10
V
Input voltage
15
15
V
1.5
1.5
2075
Peak collector current (see Figures 10, 11, and 12)
Total power dissipation at (or below) 25°C free-air temperature (see Note 2)
Storage temperature range
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds
A
o to 70
mW
DC
-55 to 150
- 55 to 150
DC
260
260
DC
o to
Operating free-air temperature range
NOTES:
2075
V
70
1. All voltage values (unless otherwise noted) are with respect to the emitter/substrate terminal E.
2. For operation above 25 DC free-air temperature, derate total power to 1328 mW at 70 DC at the rate of 16.6 mW/DC.
electrical characteristics at 25°e free-air temperature, Vee = 5 V (unless otherwise noted)
PARAMETER
VCEX(sus)
•
'CEX
'lion)
V'(on)
Collector sustaining voltage
Collector output cutoff current
On-state input current
On-state input voltage
Collector-emitter
VCE(sat)
saturation voltage
TEST
FIGURE
1
TEST CONDITIONS
V, = 0.4 V,
IC = 100 mA
VCE - 50 V
VCE = 50 V,
2
SN75068
MIN
MAX
35
SN75069
MIN
3
TA = 70 DC
5
Y
500
100
TA = 70 DC
V, = 3.75 V
4
250
250
1000
1000
IC - 1.5 A,
2.4
2.4
V, = 2.4 V,
IC = 500 mA
1.13
1.13
V, = 2.4 V,
Ic = 750 mA
1.25
1.25
V, - 2.4 V,
IC - 1 A
IC - 1.25 V
1.4
1.4
See Note 3
V, = 2.4 V,
'R
Clamp-diode reverse current
VR = 50 V,
6
IC = 1.5 A,
VF
Clamp-diode forward voltage
Supply current
ICC
(only one switch conducting)
7
'F - 1 A
. 'F - 1.5 A,
8
V, = 2.4 V,
1.7
TA = 70 DC
100
50
TA = 70 DC
1.75
1.75
See Note 3
2
2
IC = 500 mA
6
6
s
switching characteristics at 25°e free-air temperature, Vee = 5 V
PARAMETER
TEST CONDITIONS
tPHL Propagation delay time, high-to-Iow-Ievel output
5-30
See Figure 9
TEXAS •
INSTRUMENTS
POST OFFICE BOX"S55012 • DALLAS, TEXAS 75265
~A
100
NOTE 3: These parameters must be measured on one outp~t at a time using pulse techniques, tw = 10 ms, duty cycle
tpLH Propagation delay time, low-to-high-Ievel output
V
50
VR = 80 V
VR = 80 V,
~A
V
1.6
See Note 3
VR = 50 V
p.A
500
VCE - 2 V,
See Note 3
V, - 2.4 V,
UNIT
100
VCE = 80 V
VCE - 80 V,
V, = 2.4 V
MAX
50
MIN
TYP
MAX
1.5
V
mA
10%.
5N75068, 5N75069
QUADRUPLE HIGH·CURRENT DARLINGTON SWITCHES
PARAMETER MEASUREMENT INFORMATION
Vee
OPEN
Vee
• OPEN
VeE
'eEX
~
OPEN
FIGURE 2. ICEX
FIGURE 1. VCEX(sus)
Vee
Vee
OPEN
OPEN
•
JIO~~-OPEN
FIGURE 3. Ilion)
Vee
FIGURE 4. Vllon)
OPEN
OPEN
FIGURE 6. IR
FIGURE 5. VCE(sat)
lee
FIGURE 7. VF
OPEN
FIGURE 8. ICC
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TeXAS 75265
5-31
SN75068. SN75069
QUADRUPLE HIGH·CURRENT DARLINGTON SWITCHES
PARAMETER MEASUREMENT INFORMATION
,......-~.--35V
L\-~~2.4V
._
CLAMP
L
INPU~1.2V
68 n.2W
:
......
ov
~ tpLH
....
Ir
~
CL = 15 pF
(see Note AI
:
tpHL ~
~~--~~~-OUTPUT
GENERATOR
(_NoteSI
I 50%
OUTPUT
VOH
50%
---VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR
B. CL includes all probe and stray capacitance.
= 50 kHz. duty cycle = 10%. Zo = 50 II.
FIGURE 9. SWllCHING TIMES
THERMAL INFORMATION
•
MAXIMUM COLLECTOR CURRENT
MAXIMUM COLLECTOR CURRENT
"
DUTY CYCLE
DUTY CYCLE
2.0
2.0
HI
TA = 25"C
N .. Number of Outputs
.
~
1\
CD
-
r--..
is'
CD
.<
I'\.
o
o
- - r-
o
10 20 30 40 50 60 70 80 90 100
o
Duty Cycle-'*'
Conducting Simultaneously
I\,
-
"'N~ "-
14
I
N '"' Number of Outputs
')~ r::::
r--:~
Iv"
C
CD
1\1\ ........"' .......
-...J.
ff~p.- ::::
e.
:::!,
l\ \
. . . . . . . . r,....l\l·~:--- .....
:::T
TA"'70"C
Conducting Simultaneously
~
1'\
"
DUTY CYCLE
2.0
TA = SOoC
N .. Number of OutPuts
Conducting Simultaneously
MAXIMUM COLLECTOR CURRENT
'r--..
,1\
.'\.
I'- N
i4
N~
""- I-o
10 20 30 40 50 60 70 80 90 100
~;-...
"i' I- .....
l- I-- ::
01020304050 60 7080 90100
Duty Cycle-%
DutyCycle-%
II)
..
i>
FIGURE 10
FIGURE 12
FIGURE 11
(')
..
TYPICAL APPLICATION DATA
C
I»
V+
VCC - 5 V
o
Cil
1
16
'-- 2
--.J
TMS1000
II
3
~
4
5
I- ~
15 l- I--14 t-
::~:~:: 13
12
6
11
7
8
10
-~
9
FIGURE 13. RELAY DRIVER INTERfACE
5-32
TEXAS . "
INSTRUMENTS
POST OFFICE BOX· 656012 • DALLAS. TEXAS 75286
- r-
....... ..,..
....., Iv.
f-::
-
SN75372
DUAL MOSFET DRIVER
03004. JULY 1986
•
D OR P PACKAGE
Dual Circuits Capable of Driving HighCapacitance Loads at High Speeds
•
Output Supply Voltage Range Up to 24 V
•
Low Standby Power Dissipation
ITOPVIEWI
l A D B VCCl
E 2
7
lY
3
6 2Y
GND 4
5 VCC2
2A
description
The SN75372 is a dual NAND gate interface
circuit designed to drive power MOSFETs from
TTL inputs. It provides high current and voltage
levels necessary to drive large capacitive loads
at high speeds. The device operates from a
VCCl of 5 volts, and a VCC2 of up to 24 volts.
The SN75372 is characterized for operation from
logic symbol t
1A
(11
(71 1Y
2A
131
(61 2Y
O°C to 70 o C.
tThis symbol is in accordance with ANSIIIEEE Std 91-1984 and
lEe Publication 617-12.
•
logic diagram (positive logic)
E 121
lA ...:1.;.;11~I-L_~
2A ...!13::1_ _1
~
schematic (each driver)
VCCI
VCC2
TO OTHER {
DRIVER
INPUT A ------+~.t_4>---4
OUTPUT Y
ENABLE E -~-......--I--loIf..J
t--~------~------'~----~-GND
1 -____•
PRODUCTION DATA documant. contain information
.urrant a. of publication dlla. Products conform to
specifications par the terms of TaXIs Instruments
==i~ai~:I~~i ~::\::i~n :'~-::::A:~~I nDt
}
TOOTHER
DRIVER
Copyright @ 1986, Texas Instruments Incorporated
TEXAS ...,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
5-33
8N75372
DUAL M08FET DRIVER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range of VCC1 (see Note 1) .............................. -0.5 V to 7 V
Supply voltage range of VCC2 .................................... ; . .. -0.5 V to 25 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Peak output current (tw < 10 ms, duty cycle < 50%): Sink ....................... 500 mA
Source. . . . . . . . . . . . . .. . . . . .. 500 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
o package ......................................................... 725 mW
P package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1200 mW
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 260°C
NOTES: 1. Voltage values are with respect to network ground terminal. '
2. For operation above 25°C free-air temperature, see the Dissipation Derating Table.
DISSIPATION DERATING TABLE
PACKAGE
o
•
P
POWER
RATING
725mW
1200mW
DERATING
ABOVE
FACTOR
5.8 mW/oe
9.6 mW/oe
TA
25°e
25°e
recommended operating conditions
..
"l
is·
=CD
ill
Supply voltage, VeC1
Supply \toltage, Vee2
High-level input voltage. V,H
Low-level input voltage, V,L
MIN
4.75
NOM
5
4.75
2
20
High-level output current, IOH
c::::!.
<
Low-level output current, IOL
Operating free-air temperature, TA
0
CD
~a
c
&II
~
5-34
TEXAS . "
INSTRUMENTS
POST OFFICE .BOX 655012 • DALLAS, TEXAS 75265
MAX
5.25
24
UNIT
V
0.8
V
V
V
-10
40
mA
mA
70
°C
SN75372
DUAL MOSFET DRIVER
electrical characteristics over recommended ranges of VCC1. VCC2. and operating free-air temperature
(unless otherwise noted)
PARAMETER
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
VF
II
Low-level output voltage
Output clamp diode
forward voltage
Input current at maximum
input voltage
IIH
IAnyA
High-level input current
Any E
IlL
I Any A
Low-level input current
Any E
ICC1(H)
VI
= 0,
VI
=
IF
=
MIN
TVpt
VCC2-1.3 VCC2- 0.8
VCC2 2.5 VCC2 1.8
0.16
both outputs high
Supply current from VCC2,
both outputs high
ICC1(L)
Supply current from VCC1,
both outputs low
ICC2(L)
Supply current from VCC2,
both outputs low
Supply current from VCC2,
standby condition
tAli typical values are at VCC1
=
5 V, VCC2
V
V
0.3
1.5
20 mA
1
5.5 V
40
= 0.4 V
VCC1 = 5.25 V,
All inputs at 0 V,
VCC2 = 24 V,
No load
VCC1 = 5.25 V,
All inputs at 5 V,
VCC2 = 24 V,
No load
VCC1 - 0,
All inputs at 5 V,
VCC2
No load
=
UNIT
0.5
VI = 2.4 V
VI
MAX
-1.5
V
0.25
Supply current from VCC1,
ICC2(H)
ICC2(S)
TEST CONDITIONS
11- -12mA
VIL - 0.8 V,
IOH - -50 ~A
10 mA
VIL - 0.8 V,
IOH VIH = 2 V,
IOL = 10 mA
VCC2 - 15 V to 24 V, VIH - 2 V,
IOL = 40 mA
20 V, and TA
=
V
mA
~
-1
80
-1.6
-2
-3.2
2
4
mA
0.5
mA
16
24
mA
7
13
mA
0.5
mA
mA
...
CD
>
';:
MIN
= 390 pF,
RO = 1011,
CL
tTLH Transition time, low-to-high-Ievel output
tTHL Transition time, high-to-Iow-Ievel output
tpLH Propagation delay time, low-to-high-Ievel output
tpHL Propagation delay time, high-to-Iow-Ievel output
::l
t)
~
en
25°C.
TEST CONDITIONS
PARAMETER
f
.s
III
24 V,
switching characteristics. VCC1 ~ 5 V. VCC2 - 20 V. TA - 25°C
tDLH Delay time, low-to-high-Ievel output
tDHL Delay time, high-to-Iow-Ievel output
•
See Figure 1
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
MAX
20
35
ns
10
20
ns
20
30
ns
.c
30
ns
';:
65
50
ns
10
20
40
10
30
UNIT
Q
TVP
ns
'!CD
c.
:.
5-35
SN75372
DUAL MOSFET DRIVER
,PARAMETER MEASUREMENT INFORMATION
$10nS~
5 V
INPUT
I VCC1
I
3 V
I
(
1
I
I
-t -----
1
INPUT
VCC2 I
I
PULSE
GENERATOR
(See Note A)
,..1 __ 1,
~$10n.
i':9:'!:o"::%----::9~0%~t:-
1
20 V
1 I
1 4 - - - 0 , 5 , . . - - -...1
10%
10%
OV
I
I
If-tPLH-+!
J:>-+.JV\,.,....,....-OUTPUT
r-"---L~
2,4V
l
~t'fLH
I
I
VOH
1
1
1
OUTPUT
TEST CIRCUIT
1
tOLH-l+-+!
VCC2-3 V
VOLTAGE WAVEFORMS
•
NOTES: A. The pulse generator has the following characteristics: PRR = 1 MHz, Zout ~ 50 !l .
B. CL includes probe and jig capacitance.
FIGURE 1. SWITCHING TIMES. EACH DRIVER
"0
...
-S"
CD
TYPICAL CHARACTERISTICS
::r
CD
...
HIGH-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
!!.
5?
<"CD
l>
0.5~-~---.---.---.---,
VCC2
,
-... i'"
Ul
VCC1 - 5 V
>
II
VCC2- 0 . 5
VCC2 - 20 V
D)
...
III
>
;
VI - 0.8 V
I;;;;;;
()
...0c
LOW-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VCC2- 1.O
IIIIIII IIIIIII
~Ii!:
TA -
~
0
1II
...1:.
:E'"
V
VCC2- 1.5
-...;::
VCC2-2.0
2~'~IC
TA - 70°C
~:--
TA - OOC
I
J:
0 VCC2-2.5
1111111
0.4
!i
0.3
o
'ij
t
0.2
1____--I---7'~-I____--I____---I____-_l
j
!.. 0.1
~--j---j---j---j---l
-t
oJ
o
>
>
VCC2- 3. O
-0.01
VCC1 - 5 V
VCC2 - 20 V
VI - 2 V
,
>
8.
o L - _ - L_ _ _
o
20
40
~
-0.1
-1
-10
-100
IOH-High-Leve' Output Current-mA
~
FIGURE 3
TEXAS
_ _ _ __ L_ _
60
80
IOL -Low-Level Output Current-mA
FIGURE 2
5-36
__
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
~
100
SN75372
DUAL MOSFET DRIVER
TYPICAL CHARACTERISTICS
POWER DISSIPATION (BOTH DRIVERS)
vs
FREQUENCY
VOLTAGE TRANSFER CHARACTERISTICS
1200
24
20
'\
>
I
II>
til
16
S
VCC1 - 5 V
vCC2 - 20 V
No load
TA - 25°C
1000
3:
E 800
I
c
.,.
"0
>
5Q.
5
I
8
Q.
In
I
i5
4
200
o
0.5
1.5
VI-Input Voltage-V
2
o I- -
2.5
10
-
-
- -
20
200
.; :!!
.5
~
I
2 :f
'
I ~
J: ~
~.3
~ ~..... b:= .....;..- ~
120
~
40bo pF r--
-
II>
Cl - 2000 pF
In
...o
II)
....CO
....U
~
-...
ct
I I)
CD
>
';:
c
...
ia
CD
.c
c.
Cl - 4000 pF
~
~
';:
:.
::I
60
Cl - 200 pF-,,\
I
Cl -
.L
390 pf
6 a;
.~ a;
....
til,
100
Q. 0
80
...
Cl - 1000 pF
~
0 ....
0: 0
I ';'
J:.!!'
a-J:
Cl - 2000 pF , Cl
60
Cl - 200 pF ___
.... .s::
f-----
::I 140
.. Q.
VCC1 - 5 V
VCC2 - 20 V
RO - 100
See Figure 1
-
"..
PROPAGATION DELAY TIME,
HIGH-TO-LOW-LEVEL OUTPUT
vs
FREE-AIR TEMPERATURE.
160
a 140
6Q)
.., ~
., ....
til,
~ -g,
Do
Cl
~
2i ~
I
FIGURE 5
PROPAGATION DELAY TIME,
LOW-TO-HIGH-LEVEL OUTPUT
vs
FREE-AIR TEMPERATURE
180
1/
/
V
FIGURE 4
I-
I
ct
0
o
I
Cl - 4000 pF
I 400
>
I
V\V" 1\1
Cl - 2000 pF
'iii
0
I
JI
600
I
I
I
C,l ,-,~OO p F \ I
Cl - 1000 pF I\. /
.0
12
I
VCC1 - 5 V
VCC2 - 20 V
INPUT: 3 V Square wave
50% duty cycle)
TA - 25°C
o
20
30 40
50 60 70
TA -Free-Air Temperature- °C
80
o
10
FIGURE 6
.
~ 10~0
I !
pF
Cl - 390 pF- I---
Cl-50pF
20 30 40
50 60 70
TA-Free-Air Temperature- °C
80
FIGURE 7
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5-37
, SN75372
DUAL MOSFET DRIVER
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME.
HIGH-TO-LOW-LEVEL OUTPUT
vs
VCC2 SUPPLY VOLTAGE
PROPAGATION DELAY TIME.
LOW-TO-HIGH-LEVEL OUTPUT
vs
VCC2 SUPPLY VOLTAGE
200
200
VCC1 - 5 V
RO - 10 I}
TA - 25°C
See Figure 1
180
oj
.5
i
1ft
I- ..
>
-IQ
So
160
140
'$
0 120
~ ~ 100
80
40
...
CD
...
~
...C
CD
...<"
o
.....
C
III
100
~~
80
.t"6
I ';'
60
:z:.2'
!-:z:
40
.... .e
CL - 390 pF
011
I
20
10
15
VCC2-Supply Voltage-V
VCC1 - 5 V
VCC2 - 20 V
TA - 25°C
See Figure 1
j::
.!.
160
0
> So 140
..!!! ..
til
Q 0
.. "
a
......
"'.
120
>----- RO - 24~
"it
.. .e
e~•
D.
o
25
I ~
:z:
~
.... 0
!- ....
V V
IV V
60
40
20
o
-
CL - 50 pF
o
V
/
/'
. / RO
,~ ~
V
j::
>
l/
.!.
So
~ ;
Q
~
10
160
RO -
·iii!. 100
VRo-
0
~ ~
80
.t"b
I ';'
60
j:f
40
.... .e
/
2000
3000
4000
o
>
./
./
V
VRo -
101}
/1/
J~ L.- l---"Ro - b
V- V
o
1000
2000
3000
CL -Load Capacitance-pF
FIGURE 11
FIGURE 10
NOTE: For RD = 0, operation with CL
'"
V
24,:/
/
",
V
/'
/
0 120
8"'1
I}
/'
140
20
1000
25
20
10
15
5
VCC2-Supply Voltage-V
VCC1 - 5 V
VCC2 - 20 V
TA - 25°C
See Figure 1
180
CL -Load Capacitanca-pF
5-38
-
CL-~_
200
I~ 1/
[7
o
..,.CL - 200 pF 1: : ;
PROPAGATION DELAY TIME.
HIGH-TO-LOW-LEVEL OUTPUT
vs
LOAD CAPACITANCE
V
V
V
V "/
80
1
'CL - 1000 pF
FIGURE 9
-
I
";:: ~ 100
CL = 2000 pF_
20
CL~50pF
200
~ ~
1
/'
/
V
PROPAGATION DELAY TIME •
LOW-TO-HIGH-LEVEL OUTPUT
vs
LOAD CAPACITANCE
180
1
CL-400/
/
FIGURE 8
til
l>
"1
k.
6'ii
.., ~
......
5
-S"
:::r
()
200 pF
~
CD
-..
t!l
V
20
'"0
> So 140
J! :;
0 120
CL - 1000 pF
~
160
I- ..
[7
VcL
o
.t f
CL - 2000 pF
60
:z:~
~.9
./
7
......
VCC1 ~ 5 V
RO - 10 I}
TA - 25°C
See Figure 1
180
.- ../
17/
",.
2:z:
~ ~
/'
7
sa;
&:§.
CL - 4000 pF /
2000 pF violates absolute maxim"um current rating.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
4000
SN75372
DUAL MOSFET DRIVER
APPLICATIONS INFORMATION
driving power MOSFETs
The drive requirements of power MOSFETs are much lower than comparable bipolar power transistors.
The input impedance of a FET consists of a reverse biased PN junction that can be described as a large
capacitance in parallel with a very high resistance. For this reason, the commonly used open-collector driver
with a pull-up resistor is not satisfactory for high-speed applications. In Figure 12(a). an IRF151 power
MOSFET switching an inductive load is driven by an open-collector transistor driver with a 4700 pull-up
resistor. The input capacitance (Ciss) specification for an IRF151 is 4000 pF maximum. The resulting long
turn-on time due to the combination of Ciss and the pull-up resistor is shown in Figure 12(b).
4SV
~
5V
141
'*9
lSI
171
>
..
~'"
>
.
:;;
I
ell
4
3
2
....I
~1
I
:z: 0
~
/
0
/
/'
;'
\
0.5
1.5
2
Time-I'.
Ibl
2.5
3
•
...
en
...ca
...u:::s
o
~
...en
. la)
Q)
FIGURE 12. POWER MOSFET DRIVE USING SN75447
>
'i:
o
a;
...
Q)
~
C.
'i:
Q)
a.
TEXAS . .
INSTRUMENTS .
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5-39
5N75372
DUAL M05FET DRIVER
APPLICATIONS INFORMATION
A faster, more efficient drive circuit uses an active pull-up as well as an active pull-down output
configuration, referred to as a totem-pole output. The SN75372 driver provides the high speed, totempole drive desired in an application of this type, see Figure 13(a). The resulting faster switching speeds
are shown in Figure 13(b).
48 V
5V~__---------e---e~---,
171 ,...~(;.;4.;..1.....1..;.(8~1
~----<--"'-I
(31
(51
'h SN75372
~
~q
(11
>
I
.---.---.----.---r---.r--.
4
I 31-r--+--+-+-r--1f--I
~
CI
....I
2H--+--+-+--+--i1--i
~
1J--+-~-4--H-~r-~
I
o L-....L_..L--1_.J.j,_........I
:r:
~
°
1.5
0.5
2
2.5
3
Time-I's
(bl
(al
FIGURE 13. POWER MOSFET DRIVE USING SN75372
Power MOSFET drivers must be capable of supplying high peak currents to achieve fast switching speeds
as shown by the equation
Ipk
VC
where C is the capacitive load, and tr is the desired rise time. V is the voltage that the capacitance is
charged to. In the circuit shown in Figure 13(a), V is found by the equation
V = VOH - VOL
Peak current required to maintain a rise time of 100 ns in the circuit of Figure 13(a) is
(3-0)4( 109)
IpK =
100(109 )
120 mA
Circuit capacitance can be ignored because it is very small compared to the input capacitance of the IRF151.
With a VCC of 5 V, and assuming worst-case conditions, the gate drive voltage is 3 V.
For applications in which the full voltage of VCC2 must be supplied to the MOSFET gate, the SN75374
QUAD MOSFET driver should be used.
5-40
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
SN75372
DUAL MOSFET DRIVER
THERMAL INFORMATION
power dissipation precautions
Significant power may be dissipated in the SN75372 driver when charging and discharging high-capacitance
loads over a wide voltage range at high frequencies. Figure 5 shows the power dissipated in a typical
SN75372 as a function of load capacitance and frequency. Average power dissipated by this driver is
derived from the equation
PT(AV)
=
POC(AV) + PC(AV) + PS(AV)
where POC(AV) is the steady-state power dissipation with the output high or low, PC(AV) is the power
level during charging or discharging of the load capacitance, and PS(AV) is the power dissipation during
switching between the low and high levels. None of these include energy transferred to the load and all
are averaged over a full cycle.
The power components per driver channel are
POC(AV)
PC(AV) "" C
PHtH+PLtL
T
V~
I
I
I
f
I
I
I4--tH~
I
PS(AV)
~---'T - 'If----~tI
FIGURE 14. OUTPUT VOLTAGE WAVEFORM
where the times are as defined in Figure 14.
PL, PH, PLH, and PHL are the respective instantaneous levels of power dissipation, C is the load capacitance.
Vc is the voltage across the load capacitance during the charge cycle shown by the equation
Vc = VOH - VOL
•
.
en
...oca
::;,
-~..
en
Q)
>
''::;
PS(AV) may be ignored for power calculations at low frequencies.
o
..
"i
.!c.
''::;
:.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
5-41
SN15312
DUAL MOSFET DRIVER
THERMAL INFORMATION
In the following power calculation, both channels are operating under identical conditions:
VOH = 19.2 volts and VOL = 0.15 volts with VCC1 = 5 volts, VCC2 = 20 volts, Vc = 19.05 volts,
C = 1000 picofarads, and the duty cycle = 60%. At 0.5 MHz, PS(AV) is negligible and can be ignored.
When the output voltage is high, ICC2 is negligible and can be ignored.
On a per-channel basis using data sheet values
22
rnA)
rnA)]
(1
rnA)
rnA)]
POC(AV) = [ (5 V) ( - + (20 V) (0
-2
(0.6) + [(5
V) 6
-2
- + (20 V) (7
-2
(0.4)
POC(AV = 47 mW per channel
Power during the charging time of the load capacitance is
PC(AV)
=
(1000 pF) (19.05 V)2 (0.5 MHz)
=
182 mW per channel
Total power for each driver is
PT(AV) = 47 mW + 182 mW = 229 mW
and total package power is
PT(AV) = (229) (2) = 458 mW.
5-42
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 6S!1012 • DAL.LAS. TEXAS 75266
8N75374
QUADRUPLE M08FET DRIVER
03004, SEPTEMBER 19B6
•
Quadruple Circuits Capable of Driving HlghCapacitance Loads at High Speeds
•
Output Supply Voltage Range from 5 V to
24V
•
Low Standby Power Dissipation
•
V CC3 Supply Maximizes Output Source
Voltage
D OR N PACKAGE
(TOP VIEW)
VCC1
4Y
4A
2E2
2El
3A
3Y
VCC2
1Y
1A
1E1
1E2
2A
2Y
GND
description
The SN75374 is a quadruple NAND interface
circuit designed to drive power MOSFETs from
TTL inputs. It provides the high current and
voltage necessary to drive large capacitive loads
at high speeds.
The outputs can be switched very close to the
VCC2 supply rail when VCC3 is about 3 volts
higher than VCC2. The VCC3 pin can also be tied
directly to VCC2 when the source voltage
requirements are lower.
The SN75374 is characterized for operation from
OOC to 70°C.
VCC3
schematic (each driver)
Veel
VCC3
Vccz
TO OTHER{
DRIVERS
INPUT
•
A.----...-t~
ENA6LE E l - -......---1H4-+
~
ENABLE EZ-r----l:::::-1H4.J
o
logic symbol t
i:;,
2E1 112)
2E2 (13)
2A
(,)
lEl _("",4:...)_ _ _- ,
EN2
13)
1Y
16)
".:
lE2
15)
C
2El
112)
iii
2E2
113)
..
lA
(3)
lY
2A
16)
2Y
3A
111)
4A
114)
CD
.c
Q.
2Y
3A (11)
".:
3Y
4A (14)
4Y
tThis symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
PRODUCTIDN DATA doc...lftll •• ntain info,mation
c.rrant as of pabllcatlon dall. Prodacll •••10,.. to
opoclficllions po, tho tar..s Tnaa Inll" ..anta
i:; 1110::"':::'::' not
:'=:~ri~·i~l~li
=:I::
:.
0'
3Y
4Y
Copyright @ 1986, Texas Instruments Incorporated
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76266
5-43
SN75374
QUADRUPLE MDSFET DRIVER
absolute maximum
ra~ings
over operating free-air temperature range (unless otherwise noted I
Supply voltage range of
Supply voltage range of
Supply voltage range of
Input voltage. . . • . . . .
Peak output current (t w
VCC1, (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V
VCC2 ....................................... , -0.5 V to 25 V
VCC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 30 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
< 10 ms, duty cycle < 50%): Sink ....................... 500 mA
Source . . . . . . . . . . . . . . . . . . . .. 509 mA
. Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2):
o package ......................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package ........................................................ 1650 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OOC til 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 260°C
NOTES: 1. Voltage values are with respect to network ground terminal.
2. For operation above 25 DC, see the Power Dissipation Derating Table.
POWER DISSIPATION DERATING TABLE
PACKAGE
D
N
'l
...
RATING
POWER
DERATING
FACTOR
1025 mW
1650 mW
8.2 mW/oC
13.2 mW/oC
ABOVE
TA
25°C
25°C
recommended operating conditions
MIN
NOM
MAX
UNIT
:r
G)
Supply voltage, VCCl
4.75
5
5.25
V
!.
Supply voltage, VCC2
4.75
20
24
V
Supply voltage, VCC3
VCC2
0
24
28
V
4
10
V
~.
c:::!.
<
Voltage difference between supply voltages: VCC3 - VCC2
High-level input voltage, VIH
CD
Low-level input voltage, VIL
iil
High-level output current, IOH
~
.....
2
Low-level output current, IOL
Operating free-air temperature, T A
0
C
I»
o
fI)
5-44
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265
V
0.8
-10
V
mA
40
mA
70
°C
SN75374
QUADRUPLE MOSFET DRIVER
electrical characteristics over recommended ranges of VCC1. VCC2. VCC3. and operating free-air
temperature (unless otherwise noted)
VIK
TEST CONDITIONS
PARAMETER
Input clamp voltage
VCC3 = VCC2+3 V,
VOH
VOL
High·level
VCC3 = VCC2 + 3 V,
VCC3 - VCC2,
Low-level
VCC3 = VCC2,
VIH - 2 V,
IOL - 10 mA
VCC2 = 15 V to 28 V, VIH - 2 V,
IOL = 40 mA
output voltage
IIH
input current
Low-level
IlL
input current
0.3
0.5
1.5
1
~ VI = 2.4 V
Any E
~
Any E
VCC1, all outputs high
VCC2, all outputs high
Supply current from
ICC3IH)
80
-1
-1.6
-2
-3.2
4
8
-2.2
0.25
2.2
3.5
31
47
VI = 0.4 V
VCC1 = 5.25 V,
VCC2 = 24 V,
All inputs at 0 V,
VCC3 = 28 V,
No load
VCC3, all outputs high
Supply current from
ICC1IL)
VCC1, all outputs low
Supply current from
ICC2IL)
ICC3IL)
ICC2IH)
VCC2, all outputs low
Supply current from
VCC3, all outputs low
Supply current from
VCC2, all outputs high
Supply current from
ICC3IH)
VCC3, all outputs high
Supply current from
ICC2IS) V CC2, standby
condition
VCCl = 5.25 V,
VCC3 = 28 V,
No load
2
16
V
mA
~A
mA
mA
•
..
!II
...oas
...u
mA
-
«
~
27
G)
VCC1 = 5.25 V,
>
0.25
VCC2 = 24 V,
All inputs at 0 V,
VCC3 = 24 V,
No load
'':::
mA
C
.
ca
0.5
G)
.s:.
c.
0.25
VCC2 = 24 V,
All inputs at 0 V,
VCC3 = 24 V,
No load
VCC3, standby
condition
V
~
VCC2 = 24 V,
All inputs at 5 V,
VCCl = 0,
Supply current from
ICC3IS)
V
40
Supply current from
ICC2IH)
V
0.25
Supply current from
ICC1IH)
UNIT
VI = 5.5 V
maximum input voltage
High-level
MAX
-1.5
0.15
IF = 20 mA
VI = 0,
forward voltage
Input current at
II
TVPt
VIL = 0.8 V, IOH = -100 ~A VCC2- 0.3 VCC2- 0.1
VIL = 0.8 V, IOH = -10 mA VCC2- 1.3 VCC2- 0.9
VIL - 0.8 V, IOH - -50~
VCC2- 1 VCC2- 0.7
VIL = 0.8 V, IOH = -10 mA VCC2- 2.5 VCC2-1.8
output voltage
Output clamp diode
VF
MIN
11= -12 mA
'':::
mA
0.5
d!.
tAli typical values are at VCCl = 5 V, VCC2 = 20 V, VCC3 = 24 V, and TA = 25°C except for VOH for which VCC2 and VCC3 are
as stated under test conditions.
switching characteristics. VCC1 = 5 V. VCC2 - 20 V. VCC3 - 24 V. TA - 25°C
PARAMETER
TEST CONDITIONS
tDLH Delay time, low-to-high-Ievel output
tDHL Delay time, high-to-Iow-Ievel output
tTLH Transition time, low-to-high-Ievel output
tTHL Transition time, high-to-Iow-Ievel output
tpLH Propagation delay time, low-to-high-Ievel output
tpHL Propagation delay time,
high~to-Iow-Ievel
MIN
TVP
MAX
20
30
ns
10
20
ns
20
30
ns
20
30
10
40
60
ns
ns
10
30
50
ns
= 200 pF,
RD = 2411,
CL
See Figure 1
output
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
UNIT
5-45
SN75374
QUADRUPLE MOSFET DRIVER
PARAMETER MEASUREMENT INFORMATION
24V
5VJ 20V
INPUT
rvtcl ·d~21I
I
I
PULSE
GENERATOR
ISee Note Al
VCC3
e::t::~
,
__~~~~~---OUTPUT
2.4V
TEST CIRCUIT
SI0n.~
I
INPUT
I
I
I
10%
~Sl0ns
r.9:":0~%"""'---:::9~0%~r
-t -----
3 V
I
I
I I
" ' - - - 0 . 5 ~s-----~~I
10%
OV
I
If--tPLH~
I
-:
:::!.
"C
:::T
CD
~ITLH
I
VCC2-2 V
I
I
I
I
OUTPUT
i
.c
~.
fiJ
....
i>
n
I
tOLH-l4-+!
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator hlis the following charQcteristics: PRR
B. CL includes probe and jig capacitance.
=
1 MHz. Zout * 50 D.
FIGURE 1. SWITCHING TIMES. EACH DRIVER
c
I»
o
fiJ
5-46
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN75374
QUADRUPLE MOSFET DRIVER
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VCC2~~Dm~-nnm~-nnmr-rnTmm
1
~
~
o
VCC2 - 0.5I-+-H+IlIIl....Hi">t1'IIH!-+-I
~llllll UW
~I I
go
.r;.>
%
~ VCC2-2.5
VCC2- 1 .O
VCC2 - 20 V
VCC3 _ 24 V-tt+II-+++1-tt+11-+++1-tt+11
O IIS_V.L...1..I.J.LI"'-..J......I..I.I.LWl-....I....I...1.1.LWI
VCC2 - 3.0 L.......JVL...
' u·....W';...
-0.01
-0.1
-1
-10
-100
i;
111111 IIIII
TA _ 70°C
~,
TA~
1 VCC2- 2 .O
:f'"
~ VCC2- 2 .5
o
>
VCC2-3.0
-0.1
-1
-10
-100
-0.01
IOH-High-Level Output Current-mA
FIGURE 3
FIGURE 2
LOW-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VOLTAGE TRANSFER CHARACTERISTICS
0.5.-----.-----.-----.-----,----.
VCC1 - 5 V
VCC2 - 20 V
>
I
VCC3 - 24 V
~ 0.4
•
24
20
V, - 2 V
.lll
m
1111111
TA - 25°C
.I
VCC2-1.5
'OH-High-Leve' Output Current-mA
>
I
~
'[ 0.3 f------f------f-----7"I7L'----,f------l
=
o
....
~
=
o=
"ii
1 VCC2 - 2.0 f-VI-C~C'+'1~=lI-::5+'V.+..H-tt+lI-+-++++I!1j-I-+H-I!IlI
~.,
VCC2 - VCC3 V, - O.S V
VCC2- 0 .5 ;;;;;;
Q.
V CC2 - 1 .5 t-r-H+tt!tt-Httt!tlI-+-t+tttHI--t-HtHlfi
~.,
!]
VCC1 - 5 V
.,
.I
~
U
I
I
T~"::' ooc
VCC2 - 1.0
VCC2
>
~
16
'"
~..
12
'"
Q.
0.2
=
I__----,.....,..~--I__----I__----II__----I
o
I
o
>
~
.s
~ 0.1~----1------1__----1__----1__----I
S
4
o
>
0'-------'--__---'____--'____--'____--'
o
20
40
100
60
80
IOL -Low·Level Output Current-mA
o
o
VCC1 - 5 V
VCC2 - 20 V
VCC3 - 24 V
TA - 25°C
No load
0.5
FIGURE 4
1.5
V'-'nput Voltage-V
2
2.5
FIGURE 5
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5-47
SN75374
QUADRUPLE MOSFET DRIVER
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME,
HIGH-TO-LOW-LEVEL OUTPUT
vs
T A-FREE-AIR TEMPERATURE
PROPAGATION DELAY TIME,
LOW-TO-HIGH-LEVEL OUTPUT
vs
FREE-AIR TEMPERATURE
250
.~
';.
..
;!
250
I
CL - 4000 pF~
225 VCC1 -5V
VCC2 - 20 V
200 VCC3 - 24 V
!:i 175 RO -240
CI.
See Figure 1
8150
CL - 2000 pF
f
~"i5
I
.'" ~ 125
C~
&. . .
[ '6.100
ct~
I ~ 75
J:
225
.~
200 VCC1 - 5 V
I- ..
VCC2 - 20 V
175
VCC3 - 24 V
Q 0 150 RO - 240
c ~
See Figure 1
~ 125
! §.
. '"
I
..
.g ....
"',
- 11000!F
[
~ 100
~I
';'
75
J:.!!'
j!;-J:
50
0 ....
c~-doo)
~
~.9 50
CL - 4000 pF
f
"
.... .e
25
CL - 2000 pF
CL = 1000 pF
CL - 200 pF
25
CL - 50 pF
o
o
10
'l
:s.
CL-50pFI
o
20 30
40 50 60
70
TA-Free-Air Temperature- °C
o
80
10
20 30 40 50 60
70
TA - Free-Air Temperature- °C
FIGURE 7
FIGURE 6
'C
::r
80
CD
i.
PROPAGATION DELAY TIME,
LOW-TO-HIGH-LEVEL OUTPUT
vs
VCC2 SUPPLY VOLTAGE
c
:s.
Ci
;;;
»
...
250
VCC1 - 5 V
VCC3 - VCC2+4 V
RO - 240
TA - 25°C
See Figure /
225
(')
C
I»
...o.
.0
.; ~ 200
.§ I
';. !:i 175
V
..1&
t!: d
150
II
c~
.g......~
125
"',
[ '6. 100
ez
IL'
I ~
V
J:~
&.9
50
25
I---
CL - 50pF- k
o
o
5
250
V
VCC1 - 5 V
VCC3 - VCC2+4 V - CL RO-240
.; ~ 200
.§ I
TA - 25°C
I- ..
~
175 See Figure 1 /
225
CL - 4000pF
----+---
/
~Gi
.'" ~ 125
......
"',
[
~ 100
CL - 200 pF
Q:I ';'
0
.... .e
75
J:.!!'
j!;-J:
50
~
----
CL - 50 pF-,- '""\
pF-
~
-
CL - 1000 pF
I
CL - 200 pF-
r-:
25
i'
5
20
10
15
VCC2-Supply Voltage-V
FIGURE 9
FIGURE 8
5-48
dooo
CL - 2000 pF
/'
0 ....
CL - 1000 pF
I
I
10
15
20
VCC2-Supply Vohage-V
-
! §.
t!: d 150
...... v-c;: - 2000 pF
---
75
V
./
PROPAGATION DELAY TIME,
HIGH-TO-LOW-LEVEL OUTPUT
vs
VCC2 SUPPLY VOLTAGE
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75286
25
SN75374
QUADRUPLE MOSFET DRIVER
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME,
LOW-TO-HIGH-LEVEL OUTPUT
PROPAGATION DELAY TIME,
HIGH-TO-LOW-LEVEL OUTPUT
vs
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
250
VCCl - 5 V
225 VCC2 - 20 V
VCC3 - 24 V
TA - 25°C
See Figure 1
I
/V
[7
I
RO - 2411-
/
/
1\/ V'
[7
/ ~
V
17. . . [4._
25
o
h
e. 175
Q
0 150
125
Q'
I
RO RO -
I ';'
75
.... .1:
:I:.2' 50
!-:I:
25
1000
2000
3000
CL -Load Capacitance-pF
r....
/'
t------ ty
"\
V ~V
~ k:'
24111011-
~
~V
o
o
4000
/V
I
RO - 0
~ ~ 100
o ....
d: 0
~
o
~
.. "
ali
.... ....i:
/'
/
~/
1011 ...........
RO = 0P".,
RO -
V
/
250
VCCl - 5 V
225 VCC2 - 20 V
VCC3 - 24 V
ai ~ 200
TA - 25°C
.5 I
I- ~
See Figure 1
/
---
V
V
~
1000
2000
3000
CL -Load Cepacitance-pF
4000
II
FIGURE 11
FIGURE 10
POWER DISSIPATION (ALL DRIVERS)
vs
FREQUENCY
VCCl - 5 V
VCC2 = 20 V
VCC3 - 24 V
2000 INPUT: 3-Volt Square wave
(50% duty cyclel
3: 1800
E
TA - 25°C
I 1600
I
c:
1400
o!
I
.91200
II)
isI
I-
11.
i~
I
D9f
AO~r<
600 I - -
C\..':'v
400
#
ii7'!)a.Q(c
~
,
#
D9f
~ ~~rt~\..I
200
o
I
D09~
",0
...0
1000
800
I
I
I
10
20
40
70100
200
400
1000
f-Frequency-kHz
FIGURE 12
NOTE: For RD
= 0,
operation with CL
>
2000 pF violates absolute maximum current rating.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
5-49
SI75374
QUADRUPLE MOSFET DRIVER
APPLICATIONS INFORMATION
driving power MOSFETs
The drive requirements of power MOSFETs are much lower than comparable bipolar power transistors.
The input impedance of a FET consists of a reverse biased PN junction that can be described as a large
capacitance in parallel with a very high resistance. For this reason, the commonly used open-collector driver
with a pull-up resistor is not satisfactory for high-speed applications. In Figure 13(a), an ,IRF151 power
MOSFET switching an inductive load is driven by an open-collector transistor driver with a 470 0 pull-up
resistor. The input capacitance (Ciss) specification for an IRF151 is 4000 pF maximum. The resulting long
turn-on time due to the product of input capacitance and the pull-up resistor is shown in Figure 13(b).
48V
5V-e--------~._~._--~~------
m
•
141
IBI
TLC655
.
>
f
3
~
./
2
I
6
1
I
0
>
~
% SN75447
121
4
!
'RFSi
131
I
>
151
IBI
-:
~
__~
V
0
V
/
0.5
1.5 2
Tlmo-,.,.
2.5
3
Ibl
::::!.
"C
:r
CD
lal
i.
FIGURE 13. POWER MOSFET DRIVE USING SN7S447
o
::::!.
~
til
..
i>
n
A faster, more efficient drive circuit uses an active pull-up as well as an active pull-down output
configuration, referred to as a totem-pole output. The SN75374 driver provides the high-speed totempole drive desired in an application of this type, see Figure 14(a). The resulting faster switching speeds
are shown in Figure 14(b).
c
!!t
o
til
48V
7}
5V
m
141
IBI
131
151
% SN75374
IRFPst
.I
....I
>
.l!'"
0
4
>
3
<.:l
2
'0
1
!
>
'"
~
0 "---'----'----'---......- -....
0
1.5
0.5
Tlme-pos
Ibl
lal
FIGURE 14. POWER MOSFET DRIVE USING SN7S374
5-50
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS. TeXAS 7526F;;
2
2.5
3
SN75374
QUADRUPLE MOSFET DRIVER
APPLICATIONS INFORMATION
Power MOSFET drivers must be capable of supplying high peak currents to achieve fast switching speeds
as shown by the equation
VC
Ipk
tr
where C is the capacitive load, and tr is the desired rise time. V is the voltage that the capacitance is
charged to. In the circuit shown in Figure 14(a), V is found by the equation
V
= VOH
- VOL
Peak current required to maintain a rise time of 100 ns in the circuit of Figure 14(a) is
(3-0)4( 10 9 )
120 mA
100(10 9 )
Circuit capacitance can be ignored because it is very small compared to the input capacitance of the IRF 1 51 .
With a VCC of 5 V, and assuming worst-case conditions, the gate drive voltage is 3 V.
For applications in which the full voltage of VCC2 must be supplied to the MOSFET gate, VCC3 should
be at least 3 volts higher than VCC2.
•
THERMAL INFORMATION
power dissipation precautions
Significant power maybe dissipated in the SN75374 driver when charging and discharging high-capacitance
loads over a wide voltage range at high frequencies. Figure 12 shows the power dissipated in a typical
SN75374 as a function of frequency and load capacitance. Average power dissipated by this driver is
derived from the equation
PT(AV) = POC(AV)
+ PC(AV) + PS(AV)
where POC(AV) is the steady-state power dissipation with the output high or low, PC(AV) is the power
level during charging or discharging of the load capacitance, and PS(AV) is the power dissipation during
switching between the low and high levels. None of these include energy transferred to the load and all
are averaged over a full cycle.
The power components per driver channel are
POC(AV)
PC(AV) '" C V 2 C f
I
PLHtLH + PHLtHL
PS(AV) = ---=T:-----
MlI4~--T
__
-
tL~
llf---~.t
FIGURE 15. OUTPUT VOLTAGE WAVEFORM
where the times are as defined in Figure 15.
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
5-51
SN75374
QUADRUPLE MOSFET DRIVER
THERMAL INFORMATION
PL, PH, PLH, and PHL are the respective instantaneous levels of power dissipation, C is the load capacitance.
Vc is the voltage across the load capacitance during the charge cycle shown by the equation
Vc = VOH - VOL
PS(AV) may be ignored for power calculations at low frequencies ..
PS(AV) may be ignored for power calculations at low frequencies.
In the following power calculation, all four channels are operating under identical conditions: f = 0.2 MHz,
VOH-= 19.9 volts and VOL = 0.15 volts with VCC1 = 5 volts, VCC2 = 20 volts, VCC3 = 24 volts,
Vc = 19.75 volts, C = 1000 picofarads, and the duty cycle = 60%. At 0.2 MHz for CL < 2000 pF,
PS(AV) is negligible and can be ignored. When the output voltage is low, ICC2 is negligible and can be
ignored.
On a per-channel basis using data sheet values
POC(AV) =[(5V)e;A)+ (20 V) (-2.!mA) + (24 V) (2. 24mA)}0. 6) +
•
[(5V)(3\mA) +
(20V)~0:A)+ (24V)(16:A)}0.4)
POC(AV = 58.2 mW per channel
Power during the charging time of the load capacitance is
PC(AV) = (1000 pF) (19.75 V)2 (0.2 MHz) = 78 mW per channel
Total power for each driver is
PT(AV) = 58.2 mW + 78 mW
=
136.2 mW
The total package power is
PT(AV)
5-52
=
(136.2) (4)
=
544.8 mW
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
SN75407, SN75408
DUAL HIGH-CURRENT PERIPHERAL DRIVERS
02829. SEPTEMBER 1986
o
•
Characterized for Use to 500 mA
•
No Output Latch-Up at 50 V
•
Very Low Quiescent Power
Typical
•
Very Low Input Current
•
Output Clamp Diodes for Transient
Suppression
•
TTL- or MOS-CompatibleDiode-Clamped
Inputs
•
Standard 5-V Supply Voltage
•
New Plastic DIP (PI with Copper Lead
Frame Provides Cooler Operation and
Improved Reliability
,
DR P PACKAGE
SUS
(TOP VIEW}
. . 100 mW
. 1
IJA.
lA
lY
GND
Typical
2
3
4
7
6
5
VCC
2A
2Y
CLAMP
FUNCTION TASLES
SN75407
(EACH NAND DRIVER)
INPUTS
description
The SN75407 and SN75408 dual peripheral
drivers are designed for use in systems that
require high current, high Voltage, and fast
switching outputs. These devices have diodeclamped inputs as well as high-current, highvoltage output clamp diodes for switching
inductive loads. Special circuits enable these
devices to feature very low quiescent power and
minimal input current requirements. Applications
include logic buffers, hammer drivers, dc motor
drivers, and dc relay/solenoid drivers.
The SN75407 and SN75408 are characterized
for operation from 0 DC to 70 DC.
OUTPUT
A
S
H
H
L
L
X
H
X
L
H
Y
SN7540S
(EACH OR DRIVER)
INPUTS
•
OUTPUT
A
S
Y
H
X
H
X
L
H
H
L
L
functional block diagrams (positive logic)
SN75407
(3) 1Y
1A
-='-----'--
S
(6)
logic symbols
SN75407
2A---.._ _
(5)
2Y
CLAMP
(4) GNO
s
2A
SN7540S
SN7540S
(3) 1Y
1A
-"-'---~-~....
S
(6)
2Y
(5)
(4)
PRODUCTION DATA documants conlOln Information
carrant of publication data. Products conform to
.paciflcation. par the IOrm. of T.... Instruments
I'
:'~'!!:~~i~8t::1~7i ~:~:~ti:r :'~D::::~::.s nat
CLAMP
GNO
Copyright © 1986, Texas Instruments Incorporated
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5-53
SN75407, SN75408
DUAL HIGH·CURRENT PERIPHERAL DRIVERS
schematics of inputs and outputs
TVPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
CLAMP
V C C - - - -. .-
OUTPUT
INPUT
GND
absolute maximum ratings over operating free·air temperature (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 V
Output current (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 550 mA
Output clamp diode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 550 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 3):
D package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 725 mW
P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .. 1200 mW
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooC to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . 260°C
h
..
..
..<'c
"tI
CD
-6'
:::r
•
•
•
.
•
•
•
.
•
.
•
•
.
.
•
•
•
.
•
.
.
•
.
•
.
•
.
•
..
CD
!!.
NOTES:
1. All voltage values are with respect to the network ground terminal.
2. Both halves of this dual circuit may conduct rated current simultaneously; however, power dissipation averaged over a short
time interval must fall within the continuous dissipation ratings .
3. For operation above 25°C free-air temperature, derate the D package to 464 mW at 70 0 at the rate of 5.8 mW/oC and
the P package to 768 mW at 70 0 e at the rate of 9.6 mw/oe.
e
..
CD
III
i>
recommended operating conditions
....
s::
....
o
(')
..
Q)
III
PARAMETERS
Supply voltage, Vce
NOM
MAX
5
5.25
2
Hjgh-Ievel input voltage, VIH
Low-level input voltage, VIL
Operating free-air temperature, T A
5-54
MIN
4.75
0
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
UNIT
V
V
0.8
V
70
°C
SN75407. SN75408
DUAL HIGH·CURRENT PERIPHERAL DRIVERS
electrical characteristics over recommended operating free·air temperature range (unless otherwise
noted)
PARAMETER
VIK
IOH
TEST CONDITIONS
Input clamp voltage
High-level output current
Vee - 4.75 V
VIH - 2 V,
VIL = O.B V,
VOH = 70 V
Vee = 4.75 V,
VOL
MIN
11= -12mA
Low-level output voltage
VIH = 2 V,
VIL = O.B V
V (BRIO Output breakdown voltage
VR(KI Output clamp diode reverse voltage
Vee - 4.75 V,
0.3
IOL - 200 mA
0.22
0.45
IOL = 300 mA
0.45
0.65
IOL = 500 mA
O.B
1
IOH - 100 p.A
IR = 100 p.A
70
100
Vee - 4.75 V,
70
100
IF = 500 mA
0.6
1.2
High-level input current
Vee - 5.25 V,
VI - 5.25 V
IlL
Low-level input current
Vee = 5.25 V,
VI = O.B V
leCL
Supply current,
SN75407
SN7540B
Supply current,
SN75407
outputs low
SN7540B
p.A
100
IIH
outputs high
V
1
Vee = 4.75 V,
leeH
UNIT
-1.5
0.10
Output clamp diode forward voltage
Strobe S
MAX
-0.9
IOL - 100 mA
VF(KI
A input
Typt
Vee = 5.25 V
Vee = 5.25 V
V
V
V
2
V
p.A
0.01
10
-0.5
-10
1
20
p.A
VI = 0
20
30
VI = 5 V
20
30
VI = 5 V
20
30
VI = 0
20
30
Typt
MAX
0.5
1
p.s
0.4
O.B
p's
0.1
0.2
p.s
0.1
0.2
p's
mA
mA
switching characteristics, Vee" 5 V, TA .. 25°e
PARAMETER
tpLH
TEST CONDITIONS
Propagation delay time, low·to-high-Ievel output
tPHL
Propagation delay time, high-to-Iow-Ievel output
tTLH
Transition time, low-to-high-Ievel output
tTHL
Transition time, high-to-Iow-Ievel output
VOH
MIN
CL = 15 pF,
RL = 100!l,
See Figures 1 and 3
RL = 100 !l,
See Figures 2 and 3
Vs = 50!l,
High-level output voltage after switching
Vs -10
UNIT
mV
II
..
III
...oca
...:::;,
CJ
..
~
III
CD
>
·C
t All typical values are at Vee = 5 V, T A = 25 ·e.
Q
PARAMETER MEASUREMENT INFORMATION
INPUT
2.4 V
I
Co
I
50 V
I
L
I
I
SIA
CD
RL - 100!l
J
AIS
·C
Q.
SN75407
PULSE
GENERATOR
(See Note AI
'!CD
.c
I
!L
CIRCUIT
UNDER
TEST
___ _
I
I
SN75408
I
-=-
I
OPEN
0.4 V
NOTES
A. The pulse generator has the following characteristics; tw = 5 p.s, PRR = 100 kHz, Zout = 50 11.
B. CL includes probe and jig capacitance.
FIGURE 1. TEST CIRCUIT FOR SWITCHING TIMES
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
5-55
SN75407. SN75408
DUAL HIGH·CURRENT PERIPHERAL DRIVERS
PARAMETER MEASUREMENT INFORMATION (continued)
Vs - 50 V
INPUT
2.4 V
I
2mH
SN75407
1000
PULSE
GENERATOR
(See Note AI
A
CIRCUIT
UNDER
TEST
S
J
OUTPUT
CL - 15 pF
(See Note BI
SN75408
I
0.4V
•
NOTES
A. The pulse generator has the following characteristics; tw = 40 I'S, PRR = 12.5 kHz, Zout = 500.
B. CL includes probe and jig capacitance.
FIGURE 2. TEST CIRCUIT FOR HIGH·LEVEL OUTPUT VOLTAGE AFTER SWITCHING
r..I- s5 ns
I4*-s10 ns
I
:
:
I
I
;,-1~9~0%~--- 3 V
I
\
I
10% _ _ _ _.....;.;;.;,;..I!.'+
10%
I _____ 0 V
II\.,;,,;;.;;..
~
~I
tw
~I s10n.
\4-M-s5n.
(I (
II
\"( ....
:
90%
90%
II
SN75407 INPUT
I
10%
-I
I
I
I
(
14
1
10%
OV
~ tPLH
tpHL
I
I
I
I
I
I
10%
10%
1
~.::.::::.....----.;.;;.;.-,::....t-
FIGURE 3. VOLTAGE WAVEFORMS
TEXAS
- -
~1TLH
J4-*-tTHL
5-56
3V
I
90%
OUTPUT
----
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
VOL
SN75435
QUADRUPLE PERIPHERAL DRIVER
WITH OUTPUT FAULT PROTECTION
D2848. FEBRUARY 1985
•
Saturating Outputs With low On Resistance
•
Very low Standby Power ... 53 mW Max
NE DUAl-IN·lINE PACKAGE
(TOP VIEW)
•
1Y
1,2 CLAMP
2Y
High-Impedance MOS- or TTL-Compatible
Inputs
•
Standard 5-V Supply Voltage
•
No Output Glitch During Power-Up or
Power-Down
•
Output Clamp Diodes for Transient
Suppression
•
2-W Power Package.
•
600-mA Output Current
•
35-V Switching Voltage
1A
2A
G
1
HEATSINK [
AND GND
HEATSINK
AND GND
3Y
3,4 CLAMP
4Y
60 0 C/W ROJA
VCC
3A
4A
FUNCTION TABLE
(EACH NAND DRIVER)
INPUTS
description
The SN75435 quadruple peripheral driver is
designed for use in systems requiring high
current, high voltage, and high load power. It
features four inverting open-collector drivers
with a common enable input that, when taken
low, disables all four outputs. Each driver is
protected against load shorts with its own
latching over-current shutdown circuitry, which
will turn the output off when a load short is
detected. A short on one load will not affect
operation of the other three drivers. The latch for
the shutdown will hold the output off until the
input or enable pin is taken low and then high
again. A delay circuit is incorporated in the overcurrent shutdown to allow load capacitance of
up to 5 nF at 35 volts.
OUTPUT
Y
A
G
l
X
H
X
H
l
H
H
l
•
H = high level, L = low level
X = irrelevant
..
logic symbol t
I/)
....o
ca
....::::l
(J
«
--..
I /)
CI)
>
";:
p-_-+-",,(3,,-) 2Y
C
~__________~~~~-(~2) 1.2ClAMP
..
p-_ _-,,(6:.:.) 3Y
(ij
r-----------~~~~(~8) 4Y
.s:::
c.
L-__________-1~~~-(~7~) 13.4 CLAMP
Q..
CI)
Applications include relay drivers, lamp drivers,
solenoid drivers, motor drivers, LED drivers, line
drivers, logic buffers, hammer drivers, and
memory drivers.
The SN75435 is characterized for operation from
70°C.
ooe to
specifications per the terms' of Texas Instruments
~~~~~:~~i~ai~:1~1~ ~!:ti~~ti:r ~~O::~:~:t:~~S not
CI)
tThis symbol is in accordance with ANSI/IEEE Std 91 1984 and
IEC Publication 617-12.
PRODUCTION DATA documents contain information
current as of publication datB. Products conform to
";:
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1985, Texas Instruments Incorporated
5-57
SN76436
QUADRUPLE PERIPHERAL DRIVER
WITH OUTPUT FAULT PROTECTION
logic diagram (positive logic)
schematic of inputs
YOUTPUT
EQUIVALENT OF EACH INPUT
r------
VCC----+-
~-~-_.-CLAMP
G
INPUT
~_~~_"
__
~
_ _ GND
TO THREE
OTHER DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range of VCC (see Note 1) ............................ '. . . . . . . . . . . .. 7 V
Input voltage ............... ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Output supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 70 V
Output diode clamp current ............. '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 A
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2) ....... 2075 mW
Operating free-air temperature range ...................................... ODC to 70°C
Storage temperature range ......................................... - 65 DC to 150 DC
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260 DC
•
1
:I.
NOTES: 1. All voltage values are with respect to network ground terminal.
'CI
2. For operation above 25°C free-air temperature, derate linearly at the rate of 16.6 mW/OC.
:r
CD
e.
recommended operating conditions
C
MIN
4.75
2
Supply voltage. Vee
:I.
<
CD
Ig
High-level input voltage. VIH
Low-level input voltage. VIL
Output voltage
NOM MAX
5 5.25
0.8
35
Output current
600
35
Load capacitance (See Figure 31
c
UNIT
V
V
V
V
rnA
nF
electrical characteristics over recommended operating free-air temperature range
til
VIK
PARAMETER
Input clamp voltage
IOH
High-level output current
Low-level output voltage
VR
VF
Output clamp diode reverse voltage
leeH
leel
Output clamp diode forward voltage
High-level input current
Low-level input current
Over-current shutdown current
Su pply current. outputs high
tAli typical values are at Vee
=
I
IOl - 300 rnA
VIH
Vee - 4.75 V.
IF = 600 rnA
I
IOl = 600 rnA
IR - 100 ~A
Vee
= 5.25 V.
Vee - 5.25 V.
Vee = 4.75 V to 5.25 V
Vee
Supply current. outputs 19w
= 4.75
=2 V
II = -12 rnA
VIH = 2 V.
VOH = 70 V
V.
Vee
VOL
IIH
III
5-58
TEST CONDITIONS
Vee = 4.75 V.
Vee = 4.75 V.
VIL = 0.8 V.
= 5.25 V.
Vee - 5 ..25V.
MIN Typt
-0.9
100
70
VI = 5.25 V
vI - 0.8 V
650
VI = 0
VI - 5 V
5V.TA = 25°e.
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76285
MAX
-1.5
UNIT
V
~A
0.25
0.5
0.55
100
1
1.2
0.01
0.5
1.6
10
-10
~
10
rnA
rnA
rnA
V
850
6
55
V
75
V
~A
SN75435
QUADRUPLE PERIPHERAL DRIVER
WITH OUTPUT FAULT PROTECTION
switching characteristics. VCC - 5 ,V. TA - 25°C
PARAMETER
tpLH
TEST CONOITIONS
MIN
Propogation delay time. low-to-high-Ievel output
tpHL
Propagation delay time. high-to-Iow-Ievel output
ITLH
tTHL
Transition time. low-to-high-Ievel output
VOH
High-level output voltage after switching
CL = 30 pF. RL
See Figure 1
= 60 0.
Transition time. high-to-Iow-Ievel output
TYP MAX
750
UNIT
ns
750
ns
200
ns
200
See Figure 2
ns
mV
VS-l0
PARAMETER MEASUREMENT INFORMATION
'~~T ~~--r-----,
~
G/A
I
..........-=:.,
I
30V
~"""""",""""'-OUTPUT
CIRCUIT
,,--5,...--+1
~ 11+-.. 5n.
INPUT
03V
..'On..... 1
II
I
I
I
I.----...'PHL
OUTPUT
I
I
':1.--.,..
OV
I
UlIIDER
TEST
90%~ 50%
~
'PLH+I
,!,'"' ~VOH
r~~':.::O%~__:.:u~~£l
I I
~ \f-'THL
I I
""OPEN
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics: PRR = 100 kHz. Zout = 50 0.
B. CL includes probe and jig capacitance.
__ voL
-.j ~'TLH
•
FIGURE 1.. SWITCHING CHARACTERISTICS
TEXAS •
INSTRUMENTS
POST OFFICE BOX 865012 • DALLAS. TEXAS 75266
5-59
SN75435
QUADRUPLE PERIPHERAL DRIVER
WITH OUTPUT FAULT PROTECTION
PARAMETER MEASUREMENT INFORMATION
INPUT
5V
~
~ I 1--<5 ns
I 911%
2mH
~~
M
rr-
I
~
111%
INPUT
90%
1.5V
1.5V
CL = 15pF
' - _ _ _ _ _ _ _....J,_ -
ISo. Note Bl
VOLTAGE WAVEFORMS
TEST CIRCUIT
=
12.5 kHz, Zout
=
50 Il.
FIGURE 2. LATCH-UP TEST
RECOMMENDED OPERATING CONDITIONS
MAXIMUM OUTPUT SUPPLY VOLTAGE
vs
LOAD CAPACITANCE
::::!.
"C
:::r
100
CD
-..ccr
0;
..
CD
TA - OOCto,70°C
>
I
40
8.
:I
"0
> 20
U)
)j;
>'li
...
n
0 10
III
"
&
2'
S
-
'"
~
E
E
"
"
'j(
4
:;:
2
0
iil
.
1
1
I
2
4
10
20
40
C L - Load Capacitance - n F
FIGURE 3
5-60
OV
OUTPUT
NOTES: A. The pulse generator has the following characteristics: PRR
B. CL include probe and jig capacitance.
-:
3V
I
111%
I
.
< 10 ns~ I , . -
. TExAs'"
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
100
-VOL
SN75435
QUADRUPLE PERIPHERAL DRIVER
WITH OUTPUT FAULT PROTECTION
TYPICAL APPLICATION OAT A
0.01
~
+5V
~F
i
1
lkn
\r
SN74lS194t lvcc
ClR
..J'o,
~
CWI CCW+
,...
SI
L
STEPC OMMAND
SRG4
+Vs
R
+r
"1"
4~'- T"~
Ml [SHIFT]
.,
M2 [lOAD]
ClK
EN
1~/C3
r
SR SER 1.30
A
B
~
°A
2,30
CLAMP
°B
2,30
VA
~
=:*l
VB
1
YC
C
~
~~
°c
2,30
2,30
t*l
aD
YO
1
~ND
-4:-
uND
r,.::,::- ,I
I
I
I
I
I
I
I
I
"'"'-< I
I
:0
L __
I
I
I
I
..J
..
III
~
+}CC
(2/3] SN7427
o
..
«I
~
&
:l
~
u
1..-1
.~
c
~ND
iii
4-WINDING STEPPER MOTOR CONTROL CIRCUIT
~
.CD
.s:
c.
.~
:.
STEP COMMAND
CW/CCW+
------------------~
YA
YB
OUTPUTS
YC
YO
LJ
LJ
LJ
LJ
LJ
L
TIMING DIAGRAM FOR MOTOR CONTROL CIRCUIT
tThe SN74LS194 is a universal shift register with both shift-right and shift-left capability. In this application SO (pin 9) is wired high
and only the shift-right and parallel-load modes are utilized. The logic symbol shown above has been simplified to show only the
utilized modes.
tThis signal is CW/CCW or CW/CCW depending on motor winding.
TEXAS
"!1
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TEXAS 75265
5-61
"tI
...
'6"
CD
:::r
...
CD
!!!.
...c•r
CD
Cil
i>
...
...
o...
(')
C
III
en
5-62
SN75436. SN75437A. SN75438
QUADRUPLE PERIPHERAL DRIVERS
02806, DECEMBER 1986
•
NE DUAL-IN-LiNE PACKAGE
Saturating Outputs with Low On-State
Resistance
ITOP VIEWI
•
High-Impedance Inputs Compatible with
CMOS, MOS, and TTL Levels
•
Very Low Standby Power, , ,21 mW
Maximum
•
High-Voltage Outputs .. , 70 V Min
•
No Output Glitch During Power Up or Power
Down
•
No Latch-Up Within Recommended
Operating Conditions
•
Output Clamp Diodes for Transient
Suppression
•
2-Watt Power Package
1A
2A
G
1Y
1,2 D
2Y
HEATSINK,{
AND GND
}HEATSINK,
AND GND
Vee
3Y
3,4 D
4Y
3A
4A
FUNCTION TABLE
leach NAND driverl
OUTPUT
INPUTS
A
G
H
H
X
L
The SN75436, SN75437A, and SN75438
quadruple peripheral drivers are designed for use
in systems requiring high current, high voltage,
and high load power. Each device features four
inverting open-collector outputs with a common
enable input that, when taken low, disables all
four outputs, The envelope of I-V characteristics
exceeds the specifications sufficiently to avoid
high-current latch up. Applications include
driving relays, lamps, solenoids, motors, LED's,
transmission lines, hammers, and other highpower-demand devices,
logic symbol t
H
H
L
X
description
y
L
H = high level,
L = low level,
X = irrelevant
equivalent schematic of each input
logic diagram (positive logic, each driver)
. - - - - - y OUTPUT
.---.t-.. . .
- D OUTPUT
ENABLE
G
r--~--~--'----GND
TO THREE
OTHER DRIVERS
tThiS symbol is in accordance with ANSI/IEEE SId 91-1984 and
lEG Publication 617-12.
SELECTION GUIDE
FEATURE
Maximum recommended output current
Maximum VOL at maximum IOl
Maximum recommended output supply
voltage in an inductive switching circuit, Vs
SN75436
SN75437A
0.5
0.5
0.5
0.5
1
A
1
V
50
35
35
V
:~aC~~:~~i~.i~:I~"'e ~!:\~~ti:r :1~o::~::::9t:~~
not
UNIT
COPYright © 1986, Texas Instruments Incorporated
PRODUCTION DATA documents contain information
current as of publication "date. Products conform to
specifications per the terms of Texas Instruments
SN75438
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5-63
SN75436, SN75437A, SN75438
QUADRUPLE PERIPHERAL DRIVERS
absolute maximum ratings (unless otherwise noted)
Supply voltage, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage ............................................................. 30 V
Output current: SN75436, SN75437 A (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0.75 A
SN75438 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.25 A
Output clamp diode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.25 A
Output voltage (off-state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 70 V
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2) ....... 2075 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooC to 70°C
Storage temperature range .......................... ,'.............. - 65°C to 150°C
Lead temperature 1,6 mm (1/16-inch) from case for 10 seconds ...................... 260°C
NOTES:
1. All four sections of these circuits may conduct rated current simultaneously; however, power dissipation average over a short
time interval must fall within the continuous dissipation ratings.
2. For operation above 25°e free-air temperature, derate linearly to 1328 mW at 70 0 e at the rate of 16.6 mw/oe.
recommended operating conditions
PARAMETER
SN75436
NOM MAX
5.25
5
0.5
MIN
4.75
Supply voltage, Vee
Output current, IOL
Output supply voltage in inductive switching
circuit (see Figure 2), Vs
MIN
4.75
SN75437A
NOM MAX
5.25
5
0.5
50
High-level input voltage, VIH
Low-level input voltage, VIL
2
Operating free-air temperature, TA
a
MIN
4.75
SN75438
NOM MAX
5
5.25
1
35
2
0.8
0.8
70
a
70
35
2
0.8
70
a
UNIT
V
A
V
V
V
°e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VIK
Input clamp
IOH
High-level output current
TEST CONDITIONS
Vee = 4.75 V,
Vee - 4.75 V,
VIL
= 0.8 V,
Vee
VIH
= 4.75 V,
=2 V
= 4.75 V,
VOL
Low-level output voltage
VR(K)
Output clamp diode
reverse voltage
Vee
Output clamp diode
IF
forward voltage
High-level input current
Low-level input current
Supply current,
IF - 1 A
VF(K)
IIH
IlL
leeH
leeL
outputs high
Supply current,
outputs low
II
=
-12 mA
SN75436
SN75437A
MIN TVpt
MAX
-0.9 -1.5
= 750 mA
=1A
= 100~
70
-0.9
100
1
100
0.14
0.25
0.28
0.5
0.14
0.28
0.25
0.5
0.42
0.60
0.75
1
100
= 500 mA
1
VI
VI
Vee
= 5.25 V,
= 5.25 V,
= 5.25 V,
VI
= 5.25 V
= 0.8 V
= OV
Vee
= 5.25 V,
VI
=5V
Vee
Vee
70
1.6
100
V
~A
V
V
1
1.6
1.2
V
0.1
-0.25
10
-10
0.1
-0.25
2
10
-10
~A
1
4
1
4
mA
45
65
45
65
mA
t All typical values are at Vee = 5 V, TA = 25°e.
5-64
UNIT
1
IOL
101
IR
TVPt
MAX
-1.5
VIH - 2 V,
VOH = 70 V
IOL = 250 mA
IOL - 500 mA
SN75438
MIN
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
~A
SN75436, SN75437A, SN75438
QUADRUPLE PERIPHERAL DRIVERS
switching characteristics, VCC
=
5 V, TA -
tPHL
PARAMETER
Propagation delay time, low-to-high-Ievel output
Propagation delay time, high-to-Iow-Ievel output
tTLH
Transition time. low-to-high-Ievel output
tTHL
Transition time, high-to-Iow-Ievel output
tpLH
TEST CONDITIONS
CL = 30 pF,
See Figure 1
VOH
=
RL
RL
Vs
SN75438
RL
=
60
MIN
°
TYP
MAX
UNIT
1950
5000
ns
150
500
ns
40
=
10 =500 mA,
See Figure 2
10 =1 A,
1000,
= 70O,
= 35 V,
= 35O,
ns
ns
36
10 500 mA,
See Figure 2
Vs - 35 V,
SN75437A
after switching
RL
Vs - 50 V,
SN75436
High-level output voltage,
25 0 C
See Figure 2
VS-10
mV
VS-10
mV
VS-10
mV
PARAMETER MEASUREMENT INFORMATION
.'""1" F----- i ":, -."
, -_ _ _- ,
PULSE
GENERATOR
(See Note Al
I
A/G
CIRCUIT
G/A
UNDER
~----1 TEST
I
II
I
I
____ .J
~-'-
-
I
, 1 4 - - 5 "..-----1..
-.t I
14-:$5 ns
INPUT
II 90%
10%I,1.5V
OUTPUT
OV
:
I
~tPHL
CL - 30pF
I
90%
(See Note BI
I
OUTPUT
I
50%
10%
I I
~
"'OPEN
t-tTLH
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics: PRR
B. CL includes probe and jig capacitance.
=
100 kHz, Zout
=
50 O.
FIGURE 1, SWITCHING CHARACTERISTICS
Vs
INPUT
2 mH
.4
40p.s------~~~
....,. .....:$5 ns
III
PULSE
A
GENERATOR Ht------I
(See Note Al
G
2.4V
OUTPUT
INPUT
10%
•• 90%
• 1.5 V
OUTPUT
'
I,.+----3
-"114-:$10 n.
90%
1.5 V
V
I
10%
0 V
~~---------~~-:::
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics: PRR = 12',5 kHz, Zout = 50 0.
B. CL includes probe and jig capacitance.
FIGURE 2, LATCH-UP TEST
TEXAS .".
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
5-65
SN75436, SN75437A, SN75438
QUADRUPLE PERIPHERAL DRIVERS
PARAMETER MEASUREMENT INFORMATION
MAXIMUM COLLECTOR CURRENT
vs
DUTY CYCLE
1.4
<
1.3
SN 5438
I
1:
~
u
!"
1.1
E
;,
E
0.9
"I
0.8
\
=
0
I
'j(
J;
r\
Simulianerl~
9
I
~4-~
L--
r-...
'\
'\.
~~
"
I--
z}S ~
I
J
I
K~
'\
SN75436. SN75437A
0.7
0.6
\
TA - 25°C
N - Number
of Outputs
Conducting
u
::E
N - 1
"-
1\ 1\
1.2
9_ I--
...........
...........
10 20 30 40 50 60 70 80 90 100
"I
Duty Cycle-%
:::!,
"CS
::T
FIGURE 3
.
.<'
CD
MAXIMUM COLLECTOR CURRENT
vs
DUTY CYCLE
9!.
C
CD
1.4
CJ
)0
....c
I»
....
0
C')
.
<
1.3
1:
~
;,
1.2
I
U
SNJ543~
1.1
1\ \ \
0.9
~
\ \
;S
U)
U
~
E
;,
0.8 SN75436
.="
0.7
::E
I
J;
i
......
N - 1
I"
""-
"''"
SN, 543 A
0.6
i'-.
~~
4-
1 '
,~
4- ~
"'."
t'--
.........
~ t-....
. . . 1'-...
TA - 70°C
0.5 N - Number of Outputs
Conducting Simultaneously
0.4
o 10 20 30 40 50 60 70 80 90 100
Duty Cycle-%
FIGURE 4
TEXAS ...,
5-66
INSTRUMENTS
POST
OFFIC~
BOX 855012 • DALLAS. TEXAS 75265
SN75436, SN75437A, SN75438
QUADRUPLE PERIPHERAL DRIVERS
TYPICAL APPLICATION DATA
001
F
. I,il
r'
1
1 kn
SN74194I Vcc
....
"
~
Sl
cW!Ccw
ClK
I
R
~~r
..... Ml [SHIFT)
L
STEP CO MMAND
M2 [lOAD)
1__ /C3
SR SER:-t
A
1, 3D
2, 3D
B
2, 3D
c
G
r
OA
Ivcc
EN
t>
A
2, 3D
, aB
A
ac
A
aD
A
r--
V
~
CLAMP
D
Sl SER 2,3D
(OI;EN)
+Vs
+5V
SRG4
CUi
1 I
I
hv
2
V
3
1D
hv
1
.,!,.GND
I
I
I
I
41
'---=--
D
.,!,.GND
----I
I
1
0:
I
I
____ I
•
...
!II
+5V
2ca
(2/3) SN74271vcc
&
....::su
~
~
.A
~
CD
>
'C
.....
Q
lGND
'!CD
.c
FIGURE 5. 4-WINDING STEPPER MOTOR CONTROL CIRCUIT
Q.
'C
:.
STEP COMMAND
CW/CCW
V1
OUTPUTS
{
V2
V3
V4
LJ
LJ
u
LJ
LJ
L
FIGURE 6. TIMING DIAGRAM
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 865012 • DALLAS. TeXAS 75265
5-67
..
.
..<'
..
"'0
CD
-6'
::r
CD
e!-
O
CD
en
l>
n
....
c
....o
..
II)
III
5-68
SN75440
QUADRUPLE PERIPHERAL DRIVER
D2872, JANUARY 1985-REVISED SEPTEMBER 1986
•
Saturating Outputs with Low On-State
Resistance
•
High-Impedance Inputs Compatible with
CMOS, MOS, and TTL Levels
•
Very Low Standby Power
Maximum
•
High-Voltage Outputs, .. 70 V Min
•
No Output Glitch During Power Up or Power
Down
•
No Latch-Up Within Recommended
Operating Conditions
•
NE DUAL-IN-LiNE PACKAGE
ITOP VIEWI
lY
l,2CLAMP
2Y
HEATSINK{
AND
GND
3Y
3,4CLAMP
4Y
21 mW
FUNCTION TABLE
INPUTS
A
G
Output Clamp Diodes for Transient
Suppression
•
2-Watt Power Packages
•
Direct Replacement for National
Semiconductor DS3669
lA
2A
G
lEATS'NK
AND
GND
VCC
3A
4A
OUTPUT
Y
L
H
L
H
X
X
H
H
H
L
= high-level
L = low-level
X
= irrelevant
description
...
(II
The SN75440 quadruple peripheral driver is
designed for use in systems requiring high
current, high voltage, and high load power, Each
device features four noninverting open-collector
outputs with a common enable input that, when
taken low, disables all four outputs, The
envelope of I-V characteristics exceeds the
specifications sufficiently to avoid high-current
latch up, Applications include driving relays,
lamps, solenoids, motors, LEDs, transmission
lines, hammers, and other high-power-demand
devices,
....oCO
:;:,
1)
-
2
absolute maximum ratings (unless otherwise noted)
!C
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage ......................... : ................ :.................. 30 V
Output current (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0.75 A
Output clamp diode current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .. 1 A
Output voltage (off-state) .................................................... 70 V
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2) ....... 2075 mW
Operating virtual junction temperature ......................................... 150°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1.6 mm (1/16 inch).from case for 10 seconds ...................... 260°C
o
til
NOTES:
5-70
1. All four sections of these circuits may conduct rated current simultaneously; however, power dissipation averaged over a
short time interval must fall within the continuous dissipation ratings.
2. For operation above 25°C free-air temperature, derate IinearJv at the rate of 16.6 mWI DC.
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
SN15440
QUADRUPLE PERIPHERAL DRIVER
recommended operating conditions
PARAMETER
Supply Voltage, Vee
MIN
NOM
MAX
4.75
5
5.25
V
600
mA
Output current, 10L
Output supply voltage in Figure 2 (Inductive switching circuit, Vs
High-level input voltage, V,H
free~air
35
V
0.8
V
70
"e
2
V
Low-level input voltage, V,L
Operating
temperature, TA
UNIT
0
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
V,K
Input clamp voltage
10H
High-level output current
Vee = 4.75 V,
Vee - 4.75 V
" - -12 mA
V,H - 2 V,
V,L = 0.8 V,
VOH = 70 V
Vee - 4.75 V,
VOL
Low-level output voltage
Vee - 4.75 V,
Output clamp diode forward voltage
'F - 800 mA
I'H
',L
leeH
High-lev~1
input current
Vee - 5.25 V,
V, - 5.25 V
low-level input current
Vee - 5.25 V,
Supply current, outputs high
Vee - 5.25 V,
leeL
Supply CUl'rent, outputs' low
Vee - 5.25 V,
V,H - 2 V,
5 V, TA
switching characteristics.
=
Vee -
'R -
100~A
UNIT
V
~A
V
70
100
V
1
1.6
V
0.1
10
~A
V, - 0.4 V
-0.25
-10
~A
V,H - 2 V
1
4
mA
50
65
mA
aV
•
25"e.
5
V.
TA
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-high-Ievel output
RL
=
6011,
tpHL
Propagation delay time, high-to-Iow-Ievel output
eL
=
30 pF,
tTLH
Transition time. low-to-high-Ievel output
tTHL
Transition time, high-to-Iow-Ievel output
VOH
100
0.7
Output clamp diode reverse voltage
=
1
0.4
VF(D)
tAli typical values are at Vee
MAX
-1.5
l'OL = 300 mA
VR(D)
V,L =
-0.9
.l'OL = 600 mA
V,H = 2 V,
V,L = 0.8 V
Typt
MIN
High-level output voltage, after switching
TYP
MAX
A Input
MIN
1.4
5
G Input
1.5
5
A Input
0.1
0.5
G Input
2.5
5
See Figure 1
Vs - 35 V,
10 = 500 mA,
RL = 70 11,
See Figure 2
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Vs -10
UNIT
~s
~s
200
ns
50
ns
mV
5-71
SN75440
QUADRUPLE PERIPHERAL DRIVER
PARAMETER MEASUREMENT INFORMATION
LrL-----l
A=OV
INPUT G=2.4V VCC
I
A/G I
JOV
RL=60Q
I
CIRCUIT
UNDER
TEST
G/AI
OUTPUT
I
I"·. . .,
I
CL=JOpF
I
I
I
L~
I
...J
____
"::"
OPEN
TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics: PRR " 100 kHz, Zout = 50 0.
B. CL includes probe and jig capacitance.
:55n.~
INPUT A
2.7V.
1.5 V
E /lS3
5
r-
~
1."-------"'"
I '
,2.7V
1.5 V
:
JI~0.7V
o.7v-LI"
-J~~~~:V
INPUTG - - - - - ltPHLJ
OUTPUT
~:510n.
"'1\
JC
50%
10%
lr
L
50%
10%
trHL
~
trLH
VOLTAGE WAVEFORMS
FIGURE 1. SWITCHING CHARACTERISTICS
5-72
TEXAS . "
'INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5N75440
QUADRUPLE PERIPHERAL DRIVER
PARAMETER MEASUREMENT INFORMATION
Vs = 35 V
5V
INPUT
2mH
700
A
..,,_-4t-4-......-e--OUTPUT
2.4V
G
NOTES: A. The pulse generator has the following characteristics: PRR
B. CL includes probe and jig capacitance.
':;5nS---+j
A INPUT
s
12.5 kHz, Zout = 5011.
f40PS~l
,':;10n.
O%
-*1190%
~
10%1....
. ______-'.
1.5V
•
1.5 V
.2~
____
3V
0
V
VOH
OUTPUT
VOL
VOLTAGE WAVEFORMS
FIGURE 2. LATCH-UP TEST
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5-73
..
..
..c<'
..
~
'6'
::r
(I)
~
(I)
(/I
i>
g
...o..s::
I»
(/I
5-74
SN75446 THRU SN75449
DUAL PERIPHERAL DRIVERS
02481. DECEMBER 1978-REVISEO FEBRUARY 1987
•
•
•
•
Very Low Input Current
•
•
S2u B
VCC
7 2A
Characterized for Use to 350 mA
No Output Latch-Up at 50 V IAfter
Conducting 300 mAl
•
•
•
SN75446. SN75447. SN75448. SN76449 ..• D OR P PACKAGE
(TOP VIEW)
Very Low Power Requirements
1A
1Y
3
6
2Y
GND
4
5
CLAMP
High-Voltage Outputs 170 V Mini
FUNCTION TABLES
Output Clamp Diodes for Transient
Suppression 1350 mA, 70 VI
SN75446
(EACH AND DRIVER)
TTL- or MOS-Compatible Diode-Clamped
Inputs
INPUTS
A
S
H
H
Standard Supply Voltage
Suitable for Hammer-Driver Applications
OUTPUT
Y
H
L
X
L
X
L
L
description
SN75447
Series 75446 dual peripheral drivers are
designed for use in systems that require high
current, high voltage, and fast switching times.
The SN75446, SN75447, SN75448, and
SN75449 provide AND, NAND, OR, and NOR
drivers, respectively. These devices have diodeclamped inputs as well as high-current, highvoltage inductive-clamp diodes on the outputs.
(EACH NAND DRIVER)
Series 75446 drivers are characterized for
operation from OOC to 70°C.
(EACH OR DRIVER)
INPUTS
•
OUTPUT
y
A
S
H
H
L
L
X
H
X
L
H
SN76448
INPUTS
schematics of inputs and outputs
EQUIVALENT
OF EACH INPUT
TYPICAL
OF ALL OUTPUTS
OUTPUT
A
S
y
H
X
X
H
H
H
L
L
L
SN75449
- (EACH NOR DRIVER)
CLAMP
VCC--_-
INPUTS
OUTPUT
GND
OUTPUT
A
S
y
H
X
L
X
H
L
L
L
H
H = high level
L = low level
X = irrelevant
PRODUCTION DATA doc.monts _oln info,m.thuI
...,nat .. of poblicatlo. dato. Prodaota conform to
_Ificati.... PO' the terlhl ., Tn.. Ilmomints
=~~r,·i~~~7i ~ r..::'..:':t::" ••t
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 66&012 • DALLAS. TEXAS 75266
Copyright @ 1980, Texas Instruments Incorporated
5-75
SN75446 THRU SN75449
DUAL PERIPHERAL DRIVERS
logic diagrams (positive logic)
logic symbols t
SN75446
SN75446
1A (21
&t>
~
(31 1Y
(3) 1Y
(61
(51
(41
2Y
CLAMP
GNO
positivo logic: Y = AS or A+~
SN75447
SN75447
(31
1Y
(61
S
2A
2Y
(51 CLAMP
(41 GND
""0
CD
:;,.
positive logic: V =
~
..
..<
SN75446
::r
CD
1A (2)
",1t>
I!.
~
AS or A + S
SN75448
(31 1Y
(31 1Y
C
:;,.
(61,2Y
CD
-..
(51 CLAMP
(II
~
n
....
(41 GND
c
positive logic: Y = A
I»
0
SN75449
SN75449
(II
+ S or A ~
(31 1Y
(6) 2Y
(51 CLAMP
t These symbols are in accordance with ANSI/IEEE Std 91-1984
and lEe Publication 617-12.
(4)
positive logic: Y = A+S or
5-76
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
AS
GND
SN75446 THRU SN75449
DUAL PERIPHERAL DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Output current (see Note 2) ................................................ 400 mA
Output clamp diode current ................................................ 400 mA
Continuous total dissipation at (or below)
25°C free-air temperature (see Note 3): 0 package ............................ 725 mW
P package . . . . . . . . . . . . . . . . . . . . . . . . . .. 1200 mW
Storage temperature range ......................................... - 65°C to 1500C
Lead temperature 1,6 mm (1 '1 6 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 2600C
NOTES:
1. Voltage values are with respect to network ground terminal.
2. Both halves of this dual circuit may conduct rated current simultaneously; however, power dissipation averaged over a short
time interval must fall within the continuous dissipation ratings.
3. For operation above 25°C free-air temperature, derate the D package at the rate of 5.8 mW/oC and the P package at the
rate of 9.6 mW/oe.
recommended operating conditions
Supply voltage, Vee
High-level input voltage, V,H
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
2
Operating free-air temperature, T A
II
V
Low·level input voltage, V,L
0
0.8
V
70
°e
Ie
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
V,K
IOH
TEST CONDITIONS
"=
Input clamp voltage
High-level output current
V,L
Vee
VOL
-12mA
= 4.75 V,
Vc,:e
Low-level output voltage
V,H
V,L
= 0.8
V,
V,H - 2 V,
VOH
= 4.75
= 2 V,
= 0.8 V
V,
= 4.75
= 4.75
V,
MIN
=
70 V
IOL - 100 mA
'OL
IOL
IOL
=
=
=
0.75
Vee
=
5.25 V,
V,
=
Vee
=
5.25 V,
V,
= O.B
V,
=5V
=0
=5V
=0
=0
=5V
=0
leeH
Supply current, outputs high
SN75446
SN75447
SN75448
Vee = 5.25 V
SN75449
Supply current, outputs low
SN75447
SN75448
SN75449
tAli typical values are at Vee
=
5 V, TA
=
=
5.25 V
~A
IeCD
>
";:
V
Q
'!CD
100
V
100p.A
70
100
V
.c
'F - 350 mA
0.6
1.2
V
";:
'R
V,
V,
V,
Vee
CO
a
~
70
IOH - 100 p.A
V,
SN75446
leeL
0.3
0.55
Vee
Strobe S
100
350 mA
Vee - 4.75 V,
A input
1
0.10
0.45
Output clamp diode forward voltage
low-level input current
V
0,65
VF(K)
High·level input current
-1.5
0.45
VR(K)
"H
-0.9
0.22
Output clamp diode reverse voltage
I,L
UNIT
200 mA
Output breakdown voltage
V,
MAX
300 mA
V(8R)O
Vee
Typt
...o
V,
=
5.25 V
V,
V, - 5 V
V
1.6
0.01
10
-0.5
-10
-1
-20
11
18
11
18
18
25
18
25
11
18
11
18
18
25
18
25
p.A
Q.
:.
~A
mA
mA
25°e.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALl.AS, TEXAS 75~65
5-77
SN75446 THRU SN75449
DUAL, PERIPHERAL DRIVERS
switching characteristics,
tPLH
tpHL
vee" 5 V,
25°e
TEST CONOITIONS
Propagation delay time, high-to-Iow-Ievel output
tTHL
Transition time, low-to-high-Ievel output
Transition time, high-to-Iow-Ievel output
VOH
High-level output voltage after switching
tTLH
TA -
PARAMETER
Propagation dela,y time, low-to-high-Ievel output
CL
Vs
=
=
MIN
15 pF, RL = 100 0,
See Figure 1
TYP
300
MAX
750
UNIT
200
500
100
100
ns
ns
ns
50
50
55 V, 10 =300 rnA,
See Figure 2
vS-oms
PARAMETER MEASUREMENT INFORMATION
INPUT
VI~
2.4V
I
i
SN75446
I SN75447
r
I
I
I
•
SIA
I
I
.
.
c
.~
."
SN75448
RL=1oon
I
AIS
PULSE
GENERATOR
(See Note Al
____ l30V
I
IL
I
SN7j449 I
I
~--~p--t~~~--OUTPUT
CIRCUIT
UNDER
TEST
__ _
CD
-S'
:::r
oAV
OPEN
TEST CIRCUIT
CD
!!.
r-___- - 3 V
:!,
2.7 V
SN75446 INPUT
SN75448
UI
~
C
0.1 V
0.1 V
SN75447
SN75449
g..
UI
I
I
14
0.7 V
oV
I
I
~I tpHL
tPLH
OUTPUT----::9~0%~~:%
-J.--.--.r
iL
l
50%
10%
I I
90%VOH
I
I
",,+--VOL
I I
~tTHL
~tTLH
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: PRR = 100 kHz. Zout
B. CL includes probe and jig capacitance.
=
50 O.
FIGURE 1 .. SWITCHING CHARACTERISTICS
5-78
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 666012 • OAUAS, TEXAS 75265
ns
V
SN75446 THRU SN75449
DUAL PERIPHERAL DRIVERS
PARAMETER MEASUREMENT INFORMATION
VS=55V
INPUT
2.4 V
5V
rl
..L,
2mH
SN75446
I
SN75447
PULSE
GENERATOR t-....-_+-A'-t
(See Note AI
I
180n
-I:
CIRCUIT
UNDER
TEST
~OUTPUT
c( L=
15pF
See Note BI
SN75448 I
?
GND
•
0.4 V
TEST CIRCUIT
J..-+ .. 5 ns
SN75446
INPUT
SN75448
O%
1.-.1- .. 10 ns
I I
I I
Z~90:=:%-_3V
~
I
I
1.5 V
J
1~_:1:0:%===:-:;j;;;;::===1::0::%:~1 ______ 0V
-J1~I ~·90% "5ns
SN75447
INPUT
SN75449
OUTPUT
10%
1.5 V
I
--.I~11f--"10ns
40""
90%~1
:-------3V
1.5 V
1.5 V
I
10%
~';';"'--OV
\;VO'
~-------------------------'
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: PRR
B. CL includes probe and jig capacitance.
=
12.5 kHz, Zout
=
VOL
50 !l.
FIGURE 2. LATCH-UP TEST
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5-79
5-80
SN554508 THRU SN554548
SN754518 THRU SN754548
DUAL PERIPHERAL DRIVERS
02217, DECEMBER 1976-REVISED SEPTEMBER 19B6
SN55450B , . , J PACKAGE
(TOP VIEW)
PERIPHERAL DRIVERS FOR
HIGH-CURRENT SWITCHING
AT VERY HIGH SPEEDS
G
1A
•
Characterized for Use to 300 mA
•
High-Voltage Outputs
•
No Output latch-Up at 20 V (After
Conducting 300 mAl
•
High-Speed Switching
•
Circuit Flexibility for Varied Applications
•
TTL-Compatible Diode-Clamped Inputs
•
Standard Supply Voltages
•
New Plastic DIP (P) with Copper Lead
Frame Provides Cooler Operation and
Improved Reliability
•
VCC
2A
2Y
2B
2C
2E
SUB
1Y
1B
1C
1E
GND
SN55450B , . , FK PACKAGE
(TOP VIEW)
U
«
U U«
-(9Z>",
3
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
2 1 2019
1Y
4
18
NC
1B
NC
1C
5
17
6
16
8
14
15
2Y
NC
2B
NC
2C
9 1011 1213
woumw
(9
SUMMARY OF SERIES 55450B/75451 B
IJl
SN55451B
AND
FK,JG
SN55451 B, SN55452B,
SN55453B, SN55454B ... JG PACKAGE
SN75451B, SN75452B,
SN75453B, SN75454B ... D OR P PACKAGE
SN55452B
NAND
FK,JG
(TOP VIEW)
SN55453B
SN55454B
OR
FK,JG
NOR
FK,JG
SN75451B
AND
D,P
SN75452B
NAND
D,P
SN75453B
OR
D,P
SN75454B
NOR
D,P
PACKAGES
COMPLETE CIRCUIT
ANDt
SN55450B
...o
...u:::s
CQ
LOGIC OF
DEVICE
II
..
II)
..... Z Z : J N
FK,J
.'
Series 55450B175451 B dual peripheral drivers
are a family of versatile devices designed for use
in systems that employ TTL logic. This family is
functionally interchangeable with and replaces
the 75450 family and the 75450A family
devices manufactured previously. The speed of
the 55450B/75451 B family is equal to that of
the 75450 family. and the parts have been
designed to ensure freedom from latch-up.
Diode-clamped inputs simplify circuit design.
I I)
Q)
Q
"!
Q)
SN55451 B, SN55452B,
SN55453B, SN55454B, ... FK PACKAGE
(TOP VIEW)
description
--..
>
".:
1 A [ ] B VCC
1B 2
7 2B
1Y 3
6
2A
GND 4
5
2Y
tWith output transistor base connected externally to output of gate.
«
.c:
Q.
"0::
Q)
Il.
U
U
«
U
3
2
1 20 19
UU
Z_Z>Z
4
NC
5
17
6
16
8
NC
2B
NC
14
9 1011 1213
UQU>-U
ZZZ"'Z
(9
NC-No internal connection
PRODUCTION DATA documents contain information
currant as of publication data. Products conform to
specifications per the terms of Texas Instruments
=~~~~:~~i~8i~:I~~e ~:~:~ti:r ~~o::~:~9t::S~
not
Copyright
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
© 1981, Texas Instruments Incorporated
5-81
SN554508 THRU SN554548
SN754518 THRU SN754548
DUAL PERIPHERAL DRIVERS
description (cont'd)
Typical applications include high-speed logic buffers, power drivers, relay drivers, lamp drivers. MOS drivers,
line drivers, and memory drivers.
The SN55450B is a unique general-purpose device, featuring two standard Series 54 TTL gates and two
uncommitted, high-current, high-voltage n-p-n transistors. The device offers the system designer the
flexibility of tailoring the circuit to the application.
The SN55451 B/SN75451 B, SN55452B/SN75452B, SN55453B/SN75453B, and SN55454B/SN75454B
are dual peripheral AND, NAND, OR, and NOR drivers, respectively, (assuming positive logic). with the
output of the logic gates internally connected to the bases of the n-p-n output transistors.
Series 55450B drivers are characterized for operation over the full military range of - 55 DC to 125 DC.
Series 75451B drivers are characterized for operation from ODC to 70 DC.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SN55450B
II-:
..
..
c
..
SN55451B
SN75451B
SN55452B
SN75452B
SN55453B
SN75453B
SN55454B
SN75454B
UNIT
7
7
7
Input voltage
5.5
5.5
5.5
V
Interemitter voltage (see Note 2)
5.5
5.5
5.5
V
VCC·to-substrate voltage
35
V
35
V
Supply voltage. VCC (see Note 1)
Collectorwto~substrate
voltage
V
-6'
::r
(\)
Collector-base voltage
35
V
Collector-emitter voltage (see Note 3)
30
V
!!.
Off-state output voltage
Emitter-base voltage
:::!.
<
(\)
..
30
400
mA
500
mA
400
400
Peak collector or output current
(t w '" 10 ms, duty cycle", 50%. (see Note 4)
500
500
D package
a
c:
....
o
V
30
Continuous collector or output current (see Note 4)
UI
l>
5
Continuous total dissipation at (or below)
25°C free-air temperature (see Note 5)
725
FK package
1375
J package
1375
JG package
1375
mW
1050
1200
P package
I»
V
o to
Operating free-air temperature range
-55 to 125
-55 to 125
Storage temperature range
-65to 150
- 65 to 150
FK package
260
260
°C
J or JG package
300
300
°C
UI
Case temperature for 60 seconds
Lead temperature 1,6 mm
(1/16 inchl from case for 60 seconds
Lead temperature 1,6 mm
(1/16 inch) from case for 10 seconds
NOTES:
5-82
D or P package
1.
2.
3.
4.
70
-65 to 150
260
°c
°c
°C
Voltage values are with respect to the network ground terminal unless otherwise specified.
This is the voltage between two emitters of a multiple~emjtter transistor.
This value applies when the base~emitter resistance (RSEI is equal to or less than 500 O.
Both halves of these dual circuits may conduct rated current simultaneously; however, power dissipation averaged over a
short time interval must fall within the continuous dissipation rating.
5. For operation above 25°C free-air temperature, refer to the Dissipation Derating Table .
. TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
SN55450B THRU SN55454B
SN75451B THRU SN75454B
DUAL PERIPHERAL DRIVERS
DISSIPATION DERATING TABLE
PACKAGE
POWER
DERATING
RATING
FACTOR
ABOVE
TA
5.8 mW/oe
25°e
1375 mW
11.0 mW/oe
25°e
1375 mW
25°e
1050mW
11.0mW/oe
8.4 mW/oe
1200mW
9.6 mW/oe
25°e
D
725mW
FK
J
JG
P
25°e
recommended operating conditions (see Note 6)
SERIES 55450B
MIN NOM MAX
Supply voltage. Vee
4.5
High-level input voltage. VIH
2.2
Low-level input voltage. VIL
5
5.5
SERIES 75451B
MIN NOM MAX
4.75
-55
5.25
2
0.8
Operating free-air temperature. T A
5
125
0
UNIT
V
V
0.8
V
70
°e
NOTE 6: For the SN554508 only. the substrate (pin 8) must always be at the most negative device voltage for proper operation.
II
..
~
o
..
CIS
:J
U
~
~
II)
>
·C
Q
!
II)
~
c.
·C
:.
TEXAS . "
INSTRUMENTS
POST OFFice BOX 665012 • DALLAS. TeXAS 75285
5-83
SN554508
DUAL PERIPHERAL POSITIVE·AND DRIVER
logic symbol t
schematic
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
logic diagram (positive logic)
G
151 1C
4kll
1A .;;;(2;.;.1_--1-"'"
1.6kSl
13011
(61 1E
II
181 SUB
2A-+-+4
1101 2C
2A----i
__
(131
2E
......._--"(9"-1 2E
positive logic:
y =
JiG
or
L-"~---~~-~--~------GND
A +G (gate onlyl
or =-=
A + G (gate and
ResiStor values shown are nominal.
e = AG
transistorl
Pin numbers shown are for the J package.
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
TTL gates
PARAMETER
VIK
Input clamp voltage
VOH
High-level output voltage
~
= MIN,
Vee
Vee = MIN,
10l
= -400 p.A
= MIN,
= 16mA
Vee
= MAX,
10H
Vee
low-level output voltage
VOL
II
TEST CONDITIONS*
Input current at maximum
input A
input voltage
input G
input A
IIH
High-level Input current
input G
Vee
input A
IlL
Low~level
lOS
Short-circuit output current'
Vee
Ic.CH
leCl
Supply current, outputs high
Vee
Supply current, outputs low
Vcc
input current
input G
Vee
= MAX,
= MAX,
= MAX,
= MAX,
= MAX,
II
= -12 mA
= 0.8 V,
VIL
VIH
VI
VI
VI
Vo
VI
VI
MIN
2.4
= MIN,
SN55450B
TYP§
MAX
-1.2
-1.5
0.5
2
= 2.4 V
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
mA
40
80
"A
-1.6
-3.2
-18
mA
-35
-55
mA
2.8
4
mA
7
11
mA
:I: For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
§AJI typical values are atVeC = 5V,TA = 25°C . .
.1Not more than one output shoul~ be shorted at a time.
5-84
V
1
= 5.5 V
= 0.4 V
=0
=0
= .5V·
V
V
3.3
0.25
UNIT
SN55450B
DUAL PERIPHERAL POSITIVE·AND DRIVER
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
output transistors
SN55450B
PARAMETER
TEST CONDITIONSt
Collector-base
V(BR)CBO
breakdown voltage
Collector-emitter
V(BR)CER
breakdown voltage
Emitter-base
V(BR)EBO
V
IC = 100 ",A, RBE = 5000
30
V
5
V
VCE(s.t)
IC = 100 rnA
25
Static forward current
See Note 7
IC = 300 rnA
30
transfer ratio
VCE = 3 V, TA = MIN,
IC = 100 rnA
10
See Note 7
IC = 300 rnA
15
IB = 10 rnA, IC = 100 rnA, See Note 7
0.85
1.2
IB = 30 rnA, IC = 300 rnA, See Note 7
1
1.4
Collector-emitter
IB = 10 rnA, IC = 100 rnA, See Note 7
0.25
0.5
saturation voltage
IB = 30 rnA, IC = 300 rnA, See Note 7
0.45
0.8
Base-emitter voltage
UNIT
MAX
35
VCE = 3 V, TA = 25°C
VBE
TYP*
IC = 100 ",A, IE = 0
IE = 100 ",A, IC = 0
breakdown voltage
hFE
MIN
V
V
II...
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at VCC = 5 V, TA = 25°C.
NOTE 7: These parameters must be measured using pulse techniques. tw = 300 p,s, duty cycle :s 2%.
!II
...oco
switching characteristics. Vee = 5 V. T A = 25°e
...:;,
TTL gates
PARAMETER
tpLH
tPHL
TEST CONDITIONS
MIN
Propagation delay time,
low·to·high·level output
CL = 15 pF,
Propagation delay time,
TYP
MAX
UNIT
12
ns
8
ns
See Figure 1
RL = 4000,
'!
PARAMETER
td
Rise time
ts
Storage time
tf
F.II time
>
";:
Q
output transistors
tr
...
II)
high·to·low·level output
Delay time
U
~
!II
TEST CONDITIONS§
IC = 200 rnA,
IB(1) = 20 rnA,
VBE(off) = -1 V,
CL=15pF,
MIN
IB(2) = -40 rnA,
RL = 500,
See Figure 2
TYP
MAX
UNIT
8
ns
12
ns
7
ns
6
ns
II)
.c
Q.
";:
:.
§ Voltage and current values shown are nominal; exact values vary slightly with transistor parameters.
gate and transistors combined
TEST CONDITIONS
PARAMETER
tpLH Propagation delay time, low·to·high·level output
tpHL Propagation delay time, high·to·low·level output
tTLH Transition time,
tTHL Transition time,
VOH
High~level
low~to-high-Ievel
output
high~to-Iow-Ievel
output
output voltage after switching
MIN
TYP
MAX
20
30
UNIT
ns
IC = 200 rnA,
CL = 15 pF,
20
30
ns
RL = 500,
See Figure 3
7
9
12
ns
Vs - 20 V,
RBE = 5000,
IC = 300 rnA,
See Figure 4
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75266
VS-6.5
15
ns
mV
5-85
SN554518, SN754518
DUAL PERIPHERAL POSITIVE·AND DRIVERS
logic symbol t
lA
lB
2A
2B
logic diagram (positive logic)
(1)
&1>
~
(2)
(3) lY
(6)
(5) 2Y
(7)
tThis symbol is in accordance with ANSI/IEEE STO 91-1984 and
IEC Publication 617-12.
FUNCTION TABLE
(EACH DRIVER)
"tI
:::!,
"C
::r
CD
B
L
L
L (on state)
L
H
L (on state)
schematic (each driver)
Y
H
L
L Ion state)
H
H
H I off state)
r-----~~--~~-------VCC
4kf!
positive logic:_ _
Y ~ AB or A+B
II
CD
A
y
A
B
L-~---~--~~~~-GND
Pin numbers shown are for D, JG, and P packages.
Resistor values shown are nominal.
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
.
i.
PARAMETER
c...
<'CD...
en
VIK
Input clamp voltage
10H
High-level output current
i>
TEST CONDITIONS*
VCC - MIN,
II -'-12mA
VCC - MIN,
VIH - MIN,
...
...o...
VOL
SN55451B
MAX
SN75451B
MIN TYP§ MAX
UNIT
-1.2
-1.5
-1.2
V
300
VOH ~ 30 V
VCC - MIN,
(')
MIN TYP§
VIL - 0.8 V,
10L ~ 100 mA
Low-level output voltage
VCC - MIN,
C
I»
100
0,25
0.5
0.25
0.4
0.5
0.8
0.5
0.7
~A
V
VIL - 0.8 V,
10L ~ 300 mA
en
-1.5
II
Input'current at maximum input voltage
VCC ~ MAX,
VI ~ 5.5 V
1
1
IIH
High-level input current
VCC - MAX,
VI - 2.4 V
40
40
~A
IlL
Low-level input current
VCC - MAX,
VI - 0.4 V
-1.6
mA
ICCH Supply current, outputs high
ICCL Supply current, outputs low
VCC - MAX,
VI - 5 V
VCC - MAX,
VI - 0
-1
-1.6
-1
mA
7
11
7
11
mA
52
65
52
65
mA
TYP
MAX
UNIT
18
25
ns
:t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditons.
§ All typical values are at VCC ~ 5 V, T A ~ 25°C.
switching characteristics. Vee = 5 V. TA = 25°e
PARAMETER
TEST CONDITIONS
tpLH Propagation delay time, low-to-high-Ievel output
tPHL Propagation delay time, high-to-Iow-Ievel output
tTLH Transition time, low-to-high-Ievel output
tTHL Transition time, high-to-Iow-Ievel output
VOH High-level output voltage after switching
5-86
MIN
10
= 200 mA,
CL
= 15 pF,
18
25
ns
RL
~
See Figure 3
5
8
ns
7
12
ns
500,
Vs - 20 V,
10
= 300 mA,
See Figure 4
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 ,. DALLAS, TEXAS 75265
VS-6.5
mV
SN554528, SN754528
DUAL PERIPHERAL POSITIVE-NAND DRIVERS
logic svmbol t
1A
1B
2A
2B
logic diagram (positive logic)
(11
&C>
(21
(61
(71
.,-t--
2Y
tThis symbol is in accordance with ANSI/IEEE STO 91 1984 and
IEC Publication 617-12.
FUNCTION TABLE
(EACH DRIVER I
A
schematic (each driver)
Y
B
H (off state I
L
L
L
H
H (off state I
H
L
H loff state)
H
H
L (on state)
vee
4kf!
1.6 kf!
1.6 kf!
130 f!
A
positive logic:
Y~ABorA+B
B
Pin numbers shown are for D, JG, and P packages.
PARAMETER
VIK
10H
TEST CONDITIONS
Input clamp voltage
High-level output current
*
VCC ~ MIN,
11~-12mA
VCC ~ MIN,
Vil ~ 0.8 V.
SN55452B
TYP§ MAX
MIN
-1.2
VCC - MIN,
10l
VOL Low-level output voltage
~
10l
~
-1.2
...
V
CD
>
~A
100
'0:::
Q
VIH - MIN.
0.25
0.5
0.25
0.4
0.5
0.8
0.5
0.7
'!CD
V
VIH ~ MIN.
300 mA
II
Input current at maximum input voltage
VCC
~
MAX,
VI
~
5.5 V
1
1
mA
IIH
High-level input current
VCC
~
MAX,
VI
~
2.4 V
40
40
~A
IlL
Low-level input current
VCC - MAX,
VI - 0.4 V
-1.1
-1.6
- 1.1
-1.6
mA
ICCH Supply current, outputs high
ICCL Supply current, outputs low
VCC - MAX,
VI - 0
11
14
11
14
mA
VCC ~ MAX,
VI
~
56
71
56
71
mA
TYP
MAX
UNIT
26
35
5 V
.c
c..
'0:::
CD
c..
:I: For conditions shown as MiN or MAX, use the appropriate value specified under recommended operating conditions.
§ All typical values are at VCC ~ 5 V, T A ~ 25 DC.
switching characteristics. Vee = 5 V. TA - 25°e
PARAMETER
TEST CONDITIONS
tpLH Propagation delay time, low-to-high-Ievel output
tpHl Propagation delay time, high-to-Iow-Ievel output
tTlH Transition time. low-to-high-Ievel output
tTHL Transition time, high-to-Iow-Ievel output
VOH High-level. output voltage afte-r switching
ns
~
200 mA,
CL ~ 15 pF,
24
35
ns
RL
=
500,
See Figure 3
5
8
ns
7
12
10
~
See Figure 4
TEXAS
~
INSTRUMENTS
PO~T
MIN
10
Vs ~ 20 V,
...oas
...u:::s
~
III
UNIT
-1.5
300
100 mA
VCC ~ MIN.
SN75452B
TYP§ MAX
MIN
-1.5
VOH ~ 30 V
•
~
Resistor values shown are nominal.
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
OFFICE BOX 655012 • DALLAS, TEXAS 75265
300 mA,
VS-6.5
ns
mV
5-87
SN554538, SN754538
DUAL PERIPHERAL POSITIVE·OR DRIVERS
logic symbol t
1A
1B
2A
2B
logic diagram (positive logic)
(11
«1C>
~
(21
1A.!.I1:J.I...z-......
(31 1Y
)0----1
1B (21
(61
(51 2y
171
2A (61
tThis symbol is in accordance with ANSI/IEEE STD 91-1984 and
lEe Publication 617-12.
2B-I7_I"'1I._'
FUNCTION TABLE
(EACH DRIVER I
A
B
L
L
Y
L (on state I
L
H
H (off statel
H
L
H (off state I
H
H
H (off statel
schematic (each driver)
A
positive logic:
y ~ A+B or
-:...
B
iiii'
Pin numbers shown are for D. JG. and P packages.
Resistor values shown are nominal.
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
'6'
:::r
...
...c
CD
!!.
PARAMETER
<'
CD
TEST CONDITIONS*
VIK
Input clamp voltage
lOH
High-level output Current
Vee ~ MIN.
Vee - MIN.
Ul
»2
VOL
c
...o
I»
Ul
VOH
~
30 V
~
MIN.
VIL
MIN TYP§
-1.2
-1.5
-1.2
-12 mA
~
SN75453B
MAX
VIH - MIN.
lice
lOL.~
Low-level output voltage
~
II
SN55453B
MIN TYP§
300
0.8 V.
100 mA
MAX
-1.5
100
0.25
0.5
0.25
0.4
0.5
0.8
0.5
0.7
UNIT
V
~A
V
Vee - MIN.
lOL ~ 300 mA
VIL - 0.8 V.
Vee - MAX.
~ MAX.
VI - 5.5 V
1
1
40
40
~A
1.6
mA
II
Input current at maximum input voltage
IIH
High-level input current
Vee
IlL
Low-level input current
Vee - MAX.
VI - 2.4 V
VI - 0.4 V
leeH Supply' current. outputs high
leeL Supply current, outputs low
Vee - MAX.
VI - 5 V
Vee - MAX.
VI - 0
1
1.6
1
mA
8
11
8
11
mA
54
68
54
68
mA
TYP
MAX
UNIT
18
25
ns
16
25
ns
5
8
ns
7
12
ns
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§AII typical values are at Vce ~ 5 V. TA ~ 25°C.
switching characteristics. Vee = 5 V. TA
=
25°e
/
PARAMETER
TEST CONDITIONS
tpLH Propagation delay time. low-to-high-Ievel output
tpHL Propagation delay time. high-to-Iow-Ievel output
tTLH Transition time, low-to-high-Ievel output
tTHL Transition time. high-to-Iow-Ievel output
VOH High-level output voltage after switching
5-88
10
~
200 mA.
RL
~
50 Il.
Vs -
20 V.
See Figure 4
MIN
eL = 15 pF.
See Figure 3
10
~
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75266
300 mA.
VS-6.5
mV
SN554548, SN754548
DUAL PERIPHERAL POSITIVE·NOR DRIVERS
logic symbol t
lA
18
2A
28
logic diagram (positive logic)
(1)
",1[>
lA (1)
(2)
18_(2_)-...._,
(6)
(7)
2A (s)
tThis symbol is in accordance with ANSI/IEEE STD 91-1984 and
lEe Publication 617-12.
28_(7_)......_ ,
FUNCTION TA8LE
(EACH DRIVER)
schematic (each driver)
A
8
L
L
Y
VCC
H loff state)
L
H
L (on state)
H
l
L Ion state)
H
H
L Ion state)
positive logic:
Y ~
A+ii or Aii'
1 kn
Pin numbers shown are for D, JG, and P packages.
Resistor values shown are nominal.
•
.
!II
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
TEST CONDITIONS*
PARAMETER
VIK
10H
Input clamp voltage
High-level output current
Vee - MIN,
II -
Vee - MIN,
VIL - 0.8 V,
SN554548
MIN TYP§ MAX
-1.2
-12 mA
Vee - MIN,
IOl
~
VIH - MIN,
0.25
100 mA
Vee - MIN,
-1.5
-1.2
300
VOH ~ 30 V
VOL Low-level output voltage
SN75454B
TYP§ MAX
MIN
-1.5
100
0.5
0.25
UNIT
«
V
~
VIH - MIN,
0.5
0.8
0.5
-~
~A
.~
c
0.4
V
10l ~ 300 mA
...oca
...:::su
.
16
CD
0.7
..c:
Q.
II
Input current at maximum input voltage
Vee - MAX,
VI - 5.5 V
1
1
mA
.~
IIH
High-level input current
Vee - MAX,
VI - 2.4 V
40
40
~A
III
Low-level input current
Vee - MAX,
VI - 0.4 V
-1
-1.6
-1
-1.6
mA
d?
leeH Supply current, outputs high
leel Supply current, outputs low
Vee - MAX,
VI - 0
VI ~ 5 V
13
17
13
17
mA
61
79
61
79
mA
TYP
MAX
UNIT
27
35
ns
el ~ 15 pF,
24
35
ns
See Figure 3
5
8
ns
7
12
Vee ~ MAX,
:t: For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§AII typical values are at Vee ~ 5 V, TA ~ 25°e.
switching characteristics.
Vee -
5 V. TA - 25°C
PARAMETER
TEST CONDITIONS
tplH Propagation delay time, low-to-high-Ievel output
tpHl Propagation delay time, high-to-Iow-Ievel output
tTlH Transition time, low-to-high-Jevel output
tTHL Transition time, high-to-Iow-Ievel output
VOH High-level output voltage after switching
10
= 200 mA,
RL'~
50O,
Vs - 20 V,
10
= 300 mA,
See Figure 4
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
MIN
VS-6.5
ns
mV
5-89
SN554508
DUAL PERIPHERAL DRIVER
PARAMETER· MEASUREMENT INFORMATION
~<10na
,
I
OUTPUT
5V
I
INPUT 1.5 V
I
,
PULSE
GENERATOR~~---L__~
(See Note Al
10%
10%
jf---0.5
tPLli~
I
(See Note C)
90%3V
1~
V
I
-I-------°V
,.0---.1.'
I'"--tt-tPHL
-I-----VOH
I
OUTPUT
I
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: PRR
B. CL includes probe and jig capacitance.
C. All diodes are 1N3064.
:s
1 MHz, Zout .. 60 O.
FIGURE 1. PROPAGATION DELAV TIMES. EACH GATE (SN66460B ON LVI
•
INPUT -1 V
1kn
~0.3~
i1I
10 V
RL
R
INPUT 1.5 V
50n
..,--_ _-OUTPUT
190%
I
. 90":\- -
I
tt-< 6 ns
-to!
-.t tr If-
...I tot.-+t tt If-
O--UT-PU--T---=10%=\l
:....:::90%:.::..______
.
:i
-1er
TEST CIRCUIT
rn
S
ill
5-90
:s
1%, Zout .. 50 O.
FIGURE 2. SWITCHING TIMES. EACH TRANSISTOR (SN66460B ONLVI
TEXAS
°
V
.:::~~J!.l<~'"'10:::,...-_--_-::~
VOLTAGE WAVEFORMS
NOTES: A. The puise generator has the following characteristics: duty cycle
B. CL includes probe and jig capacitance.
.
1.-<5 no
I
.... tcltf-
c~.
----3V
1.5 V
' .. 10%
___.:.:10%:.:::11_
-.I
I
~
INSTRUMENTS
POST OFfICE BOX 66&012 • DALLAS, TEXAS 16285
81554508 THRU 81554548
81754518 THRU 8N754548
DUAL PERIPHERAL DRIVER8
PARAMETER MEASUREMENT INFORMATION
I
INPUT 2.4V
:,.1"'90::",.---- 3 V
INPUT 90%
:
55450B 1.5 V
I 1.5 V
'451B
I
10% I I
'453B
1 "-":..::o.----,rf----'=.I'--I- - - - - - - 0 V
10V
155J50B I
1~~--+---r
"iI:
Q
'!
Q)
.c
Q.
"iI:
:.
....
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: PRR ,.; 12.5 kHz, Zout = 50 II.
B. When testing SN55450B, connect output Y to transistor base with a 500-11 resistor from there to ground, and ground the
substrate terminal.
C. CL includes probe and jig capacitance.
FIGURE 4. LATCH-UP TEST OF COMPLETE DRIVERS
TEXAS . "
INSTRUMENTS
POST OFFICE SOX 85.5012 • DALLAS. TeXAS 75266
5-91
81554508 THRU 81554548
81154518 THRU 81154548
DUAL PERIPHERAL DRIVER8
TYPICAL CHARACTERISTICS
SN55450B
SN55450B
TTL GATE
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VC~=5JV
VIL=0.8VTA = 25°C
See Figure 2 -
~
~
r\\
-:
:I.
..
<
CD
Ul
"
~
\
-
~C--
40
30
20
10
w
LL
.c
o
10
400
70 100
200
20
40
Ic-Collector Current-rnA
FIGURE 6
TRANSISTOR
COLLECTOR-EMITTER SATURATION VOLTAGE
vs
COLLECTOR CURRENT
TRANSISTOR
BASE-EMITTER VOLTAGE
vs
COLLECTOR CU.RRENT
C
..
:-r--
!-
f-
SN55450B
!!.
....o
I°
TA=70 C
FIGURE 5
...=-CD
I»
LL
\.
:I.
S
C
70
c
-5 -10 -15 -20 -25 -30 -35 -40
IOH-High Level Output Current-rnA
'C
~
80
~
I
\
•
~
TA=2~ __
\.
o
o
TRANSISTOR
STATIC FORWARD CURRENT TRANSFER RATIO
vs
COLLECTOR CURRENT
100
o
VCE '" 3 V
~
a: 90 See Nite 7
1.2
IC
-=10
~ 1.0 18
8. 0.9 See Note 7
~
>
0.8
'i
0.6
--.-c
S 0.7
~ 0.5
~
~
II I
1.1
II I
--
TA=O°c
UJ....
~
~
t~
A
V
TA = 70°C
~
'E
0.3
~
0_2
V
0.2
0.1
i
. . . . . I-"'"f:::=::
--= f--::;; ~r = 25°C
0.1
400
~
TA =O°C
(\1111
iii 0
20
40
70 100
200
Ic-Collector Current-rnA
10
20
70'-00
200
40
Ic-Collector Current-rnA
FIGURE 8
FIGURE 7
NOTE 7: These parameters must be measured using pulse techniques. tw = 300
5-92
VI
TA=7~'f
w
.,
~
't
10
/
cl1l
,..°
TA=25C
0.4
o
IC
-=10
18
See Note 7
0.5
S
.~ 0.4
I
~ 0.3
>
0.6
{lB.
duty cycle :;;2%.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
400
SN55461 THRU SN55464
SN75461 THRU SN75463
DUAL PERIPHERAL DRIVERS
02218. DECEMBER 1976-REVISED SEPTEMBER 1986
PERIPHERAL DRIVERS FOR HIGH-VOLTAGE.
HIGH-CURRENT DRIVER APPLICATIONS
•
Characterized for Use to 300 rnA
•
High-Voltage Outputs
•
No Output Latch-Up at 30 V (After
Conducting 300 mAl
•
Medium-Speed Switching
•
Circuit Flexibility for Varied Applications and
Choice of Logic Function
•
TTL-Compatible Diode-Clamped Inputs
•
Standard Supply Voltages
SN55461. SN55462.
SN55463. SN55464 ... JG PACKAGE
SN75461. SN75462.
SN75463 ... 0 DR P PACKAGE
(TOP VIEW)
1 A U 8 VCC
1B
2
7
2B
lY 3
6
2A
GND
4
S
2Y
SN55461. SN55462.
SN55463. SN55464 •... FK PACKAGE
(TOP VIEW)
u
u..: u uu
z~z>z
Q4
gs
g
pa
. ' New Plastic DIP (PI with Copper Lead
Frame for Cooler Operation and Improved
Reliability
•
3
2 1 2019
18
17
16
1S
NC
lB
NC Q6
lY 7
NC
Packaga Options Include Plastic "Small
Outline" Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
14
NC
2B
NC
2A
NC
9 10111213
uou>-u
ZZZNZ
(!)
SUMMARY OF SERIES 55461/75461
DEVICE
LOGIC
...o~
...
NC ~ No internal connection
CO
PACKAGES
SN55461
AND
FK.JG
SN55462
NAND
FK,JG
SN55463
OR
FK,JG
SN55464
NOR
FK.JG
SN75461
AND
D,P
SN75462
NAND
D,P
SN75463
OR
D.P
~
(,)
~
II)
...
CD
>
";:
o
iii
...
CD
~
description
C.
';:
These dual peripheral drivers are functionally interchangeable with SN55451 B through SN55454B and
SN75451 B through SN75453B peripheral drivers, but are designed for use in systems that require higher
breakdown voltages than those devices can provide at the expense of slightly slower switching speeds.
Typical applications include logic buffers, power drivers, relay drivers, lamp drivers, MOS drivers, line drivers,
and memory drivers.
:.
The SN55461/SN75461, SN55462/SN75462, SN55463/SN75463, and SN55464 are dual peripheral
AND, NAND, OR, and NOR drivers, respectively, (assuming positive logic), with the output of the gates
internally connected to the bases of the n-p-n output transistors.
Series 55461 drivers are characterized for operation over the full military temperature range of - 55°C
to 125°C; Series 75461 drivers are characterized for operation from OOC to 70°C.
PRODUCTION DATA do••mlllltJ contain information
currant as of publication data. Products conform to
sp.cificltioRs per the tarms af Taxas Instruments
::::!:~~i;ai~:I~.t
=::i:: :ua:::;~:;,.as not
Copyright
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
© 1981, Texas Instruments Incorporated
5-93
SN55461 THRU SN55464
SN75461 THRU SN75463
DUAL PERIPHERAL DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SN55461
SN75461
SN55462
SN75462
SN55463
Supply voltage, Vee Isee Note 1)
Input voltage
7
7
V
5.5
5.5
V
Interemitter voltage (see Note 2)
5.5
5.5
V
Off-state output voltage
35
35
400
400
mA
500
mA
Continuous collector or output current (see Note 3)
Peak collector or output current
500
(t w '" 10 ms, duty cycle", 50%, see Note 3)
D package
Continuous total dissipation at (or below)
FK package
1375
25°C free-air temperature (see Note 4)
JG package
1050
mW
-55to 125
Storage temperature range
-65 to 150
Lead temperature 1.6 mm
(1/16 inch) from c.s. for 60 seconds
Lead temperature 1.6 mm
-:
NOTES:
...
...c<.
...CD
CD
!!!.
70
°e
°e
FKpackage
260
°e
JG package
300
°e
260
°e
1. Voltage values are with respect to network ground terminal unless otherwise specified.
2. This is the voltage between two emitters of a multiple-emitter transistor.
3. Both halves of these dual circuits may conduct r.ated current simu~aneously; however, power dissipation averaged over a
short time interval must fall within the continuous dissipation rating .
4. For operation above 25°C free-air temperature, refer to the Dissipation Derating Table.
DISSIPATION DERATING TABLE
PACKAGE
UI
i>
POWER
DERATING
ABOVE
RATING
FACTOR
5.8 mW/oe
TA
25°e
D
725 mW
(')
FK
1375 mW
11 mW/oe
25°e
C
JG
1050 mW
25°e
F'
1200 mW
8.4 mW/oe
9.6 mW/oe
...
......o
II)
UI
o to
-65 to 150
D or P package
(1/16 inch) from case for 10 seconds
:r
1200
Operating free-air temperature range
Case temperature for 60 seconds
V
725
P package
:::!.
'tI
UNIT
SN75463
SN55464
25°e
recommended operating conditions
.Supply voltage, Vee
High-level input voltage, V,H
SN55461
SN75461
THRU SN55464
THRU SN75463
MIN
NOM
MAX
MIN
NOM
MAX
4.5
2.2
5
5.5
4.75
5
5.25
Low-level input voltage, VIL
Operating free-air temperature, T A
5-94
2
0.8
-55
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TeXAS 75285
125
0
UNIT
V
V
0.8
V
70
°e
SN55461. SN75461
DUAL PERIPHERAL POSITIVE-AND DRIVERS
logic symbol t
1A
18
2A
2B
logic diagram (positive logic)
(11
&1>
~
(21
(31 1Y
(61
(51 2Y
f7I
tThis symbol is in accordance with ANSI/IEEE STO 91-19B4 and
IEC Publication 617-12.
FUNCTION TABLE
(EACH DRIVER I
A
B
L
L
Lion state I
L
H
L (on state)
H
L
Lion statel
H
H
H loff state I
schematic (each driver)
r-----~~--~~-------Vcc
Y
4kU
1.6kU
130[1
v
A
positive logic:_ _
Y ~ AB or A+B
B
..
L-~------~----~~~~-GND
Pin numbers shown are for D, JG, and P packages.
Resistor values shown are nominal.
!II
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
VIK
Input clamp voltage
10H
High·level output current
TEST CDNDITIONSt
VCC ~ MIN.
II
VCC - MIN.
VIH - MIN.
Low~level
10L
output voltage
MAX
-1.2
-1.5
~
MIN TYP*
-1.2
300
VIL - O.B V.
100 mA
MAX
-1.5
100
0.25
0.5
0.25
0.4
0.5
O.B
0.5
0.7
UNIT
V
~A
V
VIL - O.B V.
VCC - MIN.
SN75461
MIN TYP*
-12 mA
VOH ~ 35 V
VCC - MIN.
VOL
~
SN55461
10L ~ 300 rnA
.
a;
.
-.:;
Q
CD
Input current at maximum input voltage
VCC - MAX.
VI - 5.5 V
1
1
mA
IIH
High·levef input current
VCC - MAX.
40
40
~A
IlL
Low-level input current
VCC - MAX.
VI - 2.4 V
VI - 0.4 V
ICCH Supply current, outputs high
ICCL Supply current, outputs low
VCC - MAX.
VCC - MAX.
~
(,)
..c
II
1
1.6
1
1.6
rnA
B
56
11
B
11
rnA
76
56
76
rnA
TYP
MAX
UNIT
30
55
ns
15 pF.
25
40
ns
See Figure 1
8
20
ns
10
20
VI - 5 V
VI - 0
....oca
....
Co
-.:;
d?,
tFor conditions shown "as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at VCC ~ 5 V. TA ~ 25°C.
switching characteristics, Vee - 5 V, TA = 25°e
PARAMETER
TEST CONDITIONS
tpLH Propagation delay time, low-to-high-Ievel output
tpHL Propagation delay time, high-to-Iow-Ievel output
tTLH Transition time, low-to-high-Ievel output
tTHL Transition" time, high-to-Iow-Ievel output
VOH High-level output voltage after switching
10 ~ 200 rnA.
RL
~
500.
Vs ~ 30 V.
See Figure 2
CL
~
10
TEXAS •
Il'tSTRUMENTS
POST OFFICE BOX 656012 • DAllAS. TEXAS 75265
~
MIN
300 rnA.
VS-l0
ns
rnV
5-95
SN55462, SN75462
DUAL PERIPHERAL POSITIVE·NAND DRIVERS
logic diagram (positive logic)
logic symbol t
lA
lB
2A
2B
(1)
&1>
(2)
(6)
(7)
. r - r - - 2Y
tThis symbol is in accordance with ANSI/IEEE STO 91-1984 and
IEC Publication 617-12.
FUNCTION TABLE
schematic (each driver)
(EACH DRIVER)
•
Y
B
A
L
L
H (off state)
L
H
H (off state)
H
L
H (off state)
H
H
L (on state)
A
positive logic:
y
Pin
number~
= Ali
or
B
A+B
shown are for 0, JG. and P packages.
Resistor values shown are nominal.
electrical characteristics over recommended operating free· air temperature range (unless otherwise
noted)
PARAMETER
VIK
Input clamp voltage
10H
High-level output current
VOL
TEST CONDITIONSt
VCC - MIN,
II -
Vec - MIN,
Vil - 0.8 V,
VOH
= 35
SN55462
MIN
-1.2
-12 mA
SN75462
MAX
-1.5
V
Vce - MIN,
VIH - MIN,
= 100 mA
Vee = MIN,
10L = 300 rnA
VIH - MIN,
MIN TYP*
-1.2
300
10L
Low-level output voltage
TYP*
MAX
UNIT
-1.5
V
100
pA
0_25
0_5
0.25
0.4
0.5
0.8
0.5
0.7
V
II
Input current at maximum input voltage
Vce - MAX,
VI - 5.5 V
1
1
IIH
High-level input current
VCC - MAX,
40
40
pA
IlL
Low-level input current
Vce - MAX,
VI - 2.4 V
VI - 0.4 V
ICCH Supply current, outputs high
leel Supply current, outputs low
Vee - MAX,
VI - 0
Vee
= MAX,
VI
=
5 V
rnA
-1.1
'13
-1.6
-1.1
-1.6
17
13
17
rnA
rnA
61
76
61
76
rnA
TYP
MAX
UNIT
45
65
ns
30
13
50
ns
25
ns
10
20
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*AII typical values are at Vee = 5 V, TA = 25°e.
'
switching characteristics. Vee
=
5 V. TA - 25°e
PARAMETER
TEST CONDITIONS
tpLH Propagation delay time, low-to-high-Ievel output
tpHL Propagation delay time, high-to-Iow-Ievel output
tTLH Transition time, low-to-high-Ievel output
= 200 rnA,
RL = 50 Il,
10
MIN
eL = 1.5 pF,
See Figure 1
tTHL Transition time, high-to-Iow-Ievel output
VOH High-level output voltage after switching
5-96
Vs - 30 V,
See Figure 2
10
= 300 rnA,
TEXAS •
, INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
VS-l0
ns
mV
SN55463. SN75463
DUAL PERIPHERAL POSITIVE-OR DRIVERS
logic symbol t
lA
lB
2A
2B
logic diagram Ipositive logic)
11)
",1[>
Q
12)
13) 1Y
(6)
(51 2Y
(7)
tThis symbol is in accordance with ANSI/IEEE STO 91-1984 and
lEe Publication 617-12.
FUNCTION TABLE
schematic leach driver)
(EACH DRIVER)
A
B
L
L
H
L
Y
L (on state)
H (off state I
H
L
H (off statel
H
H
H (off state I
A
positive logic:
y ~ A
+ B or
B
)iii
Resistor values shown are nominal.
Pin numbers shown are for D, JG, and P packages.
electrical characteristics over recommended operating free-air temperature range lunless otherwise
noted)
•
...f!o
...'"
:::J
PARAMETER
VIK
IOH
TEST CONDITIONSt
Input clamp voltage
~
Vee
Vee - MIN,
High-level o!Jtput current
-12 rnA
MIN TYP*
-1.2
VIH - MIN,
10L
Low-level output voltage
~
VIL - 0.8 V,
100 rnA
Vee - MIN,
10L ~ 300 rnA
Input current at maximum input voltage
Vee
IIH
High-level input current
Low-level input current
Vee - MAX,
Vee ~ MAX,
VI - 2.4 V
IlL
Vee - MAX,
VI - 5 V
Vee - MAX,
VI - 0
leeH Supply current, outputs high
leeL Supply current, outputs low
~
MAX,
VI
VI
~
~
MAX
-1.5
MIN TYP*
-1.2
TVP
-1.5
100
0.25
0.5
0.25
0.4
0.5
0.8
0.5
0.7
UNIT
V
5.5 V
1
40
0.4 V
U
..
~
II)
~
FA
·C
Q
V
VIL - 0.8 V,
II
SN75463
300
VOH ~ 35 V
Vee - MIN,
VOL
~
II
MIN,
SN55463
'!
Q)
1
rnA
-1
-1.6
-1
40
-1.6
FA
rnA
8
11
8
11
rnA
58
76
58
76
rnA
TVP
MAX
UNIT
30
55
ns
..c
c.
·C
l.
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
~AII typical values are at Vee ~ 5 V, TA ~ 25°e.
switching characteristics.
Vee" 5 v.
TA ..
25°e
PARAMETER
TEST CONDITIONS
tpLH Propagation delay time, low-to-high-Ievel output
tPHL Propagation delay time, high-to-Iow-Ievel output
tTLH Transition time, low-to-high-Ievel output
tTHL Transition time. high-to-Iow-Ievel output
VOH High-level output voltage after switching
~
MIN
10
~
200 rnA,
eL
15 pF,
25
40
ns
RL
~
50 II,
See Figure 1
8
25
25
ns
10
Vs - 30 V,
10
~
See Figure 2
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
300 rnA,
VS-l0
ns
rnV
5-97
SN55464
DUAL PERIPHERAL POSITIVE·NOR DRIVER
logic symbol t
1A
1B
2A
2B
logic diagram (positive logic)
(1)
",11>
(21
(61
(71
tThis symbol is in accordance with ANSI/IEEE STD 91·1984 and
lEe Publication 617·12.
FUNCTION TABLE
(EACH DRIVERI
B
L
L
H
Lion statel
H
L
Lion statel
H
H
Lion state I
L
schematic (each driver)
V
A
H loff state I
positive logic:
y =
A+1i or Aii'
Pin numbers shown are for the JG package.
Resistor values shown are nominal.
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
VIK
Input clamp voltage
IOH
High·level output current
VOL
Low·level output voltage
SN55464
TEST CONDITIONS t
PARAMETER
Vee = MIN.
11=-12mA
Vee = MIN.
VIL - 0.8 V.
VOH = 35 V
Vee = MIN.
VIH
10L
=
=
MIN TYP*
-1.2
MIN.
100 mA
Vee = MIN.
VIH - MIN.
= 300 mA
Vee = MAX.
II
Input current at maximum input voltage
High·level input current
VI
III
Low-level Input current
leeH Supply current. outputs high
leel Supply current. outputs low
=
UNIT
-1.5
V
300
I'A
0.25
0.5
0.5
0.8
-1
V
IOL
IIH
MAX
5.5 V
1
rnA
Vee - MAX.
Vee = MAX.
VI = 2.4 V
40
-1.6
Vee = MAX.
VI = 0
14
19
I'A
mA
mA
Vee = MAX.
VI = 5 V
67
85
mA
TVP
MAX
UNIT
40
65
ns
VI
= 0.4
V
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
*All typical values are at Vee = 5 V. TA = 25°e.
switching characteristics. Vee - 5 V. TA - 25°e
PARAMETER
TEST CONDITIONS
tpLH Propagation delay time. low·to·high·level output
tpHL Propagation delay time. high·to·low·level output
tTlH Transition time, low-to-high-Ievel output
tTHl Transition time, high-to-Iow-level output
VOH High·level output voltage after switching
5-98
MIN
10 = 200 mAo
el=15pF.
30
50
ns
Rl = 500.
See Figure 1
8
20
ns
10
20
Vs - 30 V.
See Figure 2
10
= 300 mAo
TEXAS . "
.INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
VS-l0
ns
mV
SN55461 THRU SN55464
SN75461 THRU SN75463
DUAL PERIPHERAL DRIVERS
PARAMETER MEASUREMENT INFORMATION
,~"10ns
-+t
I
:,.,9"'0==%,-----3 V
I
I
INPUT 2.4 V
I
10V
~
10% I I
- 1 - - - - - - - OV
'462
PULSE
GENERATOR
(See Note AI
1.5 V
OUTPUT
L~---l---f1ITRCunr-~;t,
-+I
JI !.-"10 ns
:.--------11-----.....:'-1-1 - - - - - - -3 V
INPUT
'462
'464
: I
90%
1.SV
:
I
10%
OV
I
'463
'464
GND
~
0.4 V
If-tpLH~
:SUB
I
I
I
I
90%
~
50%
OUTPUT
10%
~'I_--------~I-
tTLH~
TEST CIRCUIT
I
I
-1- - VOL
~
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: PRR
B. CL includes probe and jig capacitance.
:s
1 MHZ, Zout = 50 O.
~
,~"10 ns
-+t
I
VS=30V
:'''90=%,------ 3 V
I
I
I
10% I 1
~~~
PULSE
GENERATOR
(See Not. AI
Ljl---J__-fLcmilsrnrr-~;f,
~
I
1\..:.10:;..;%=--_ _ _ 0 V
GND
:SUB
I
~
TEST CIRCUIT
NOTES:
- - - - - - ·0 V
I '-- .. 5 ns
-+I I !.-"10 ns
I :,'__-------j,f.------,:'-I-I - - - - - - -3 V
190%
90%
II
I I
INPUT
'462
'464
:::l
U
~
en
...
1.SV
-.....:.;::..:::...---l:~....:..::.:::.J'-I-
OUTPUT
•
...oas
FIGURE 1. SWITCHING TIMES
CD
>
'C
c
'!CD
.c
Q.
'C
:.
"""~~/-----~~:::
VOLTAGE WAVEFORMS
A. The pulse generator has the following characteristics: PRR
B. CL includes probe and jig capacitance.
:s 12.5
kHz, Zout ~ 50
o.
FIGURE 2. LATCH-UP TEST
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
5-99
."
...
:::T
...e!..
...c
<'
...en
(I)
-6'
(I)
(I)
i>
...c:::
...o...
(')
I»
en
5-100
SN75465 THRU SN75469
DARLINGTON TRANSISTOR ARRAYS
02625. DECEMBER 1976-REVISEO SEPTEMBER 1986
HIGH-VOLTAGE HIGH-CURRENT DARLINGTON TRANSISTOR ARRAYS
•
500 mA Rated Collector Current
(Single Output)
D OR N PACKAGE
ITOPVIEW)
•
High-Voltage Outputs ... 100 V
•
Output Clamp Diodes
•
Inputs Compatible with Various Types of
Logic
•
Relay Driver Applications
•
Higher-Voltage Versions of ULN2005A.
ULN2001A.ULN2002A. ULN2003A.and
ULN2004A. Respectively. for Commercial
Temperature Range
18
28
38
48
58
68
78
E
1C
2C
3C
4C
5C
6C
7C
COM
description
The SN75465. SN75466. SN75467. SN75468. and SN75469 are monolithic high-voltage. high-current
Darlington transistor arrays. Each consists of seven n-p-n Darlington pairs that feature high-voltage outputs
with common-cathode clamp diodes for switching inductive loads. The collector-current rating of each
Darlington pair is 500 milliamperes. The Darlington pairs may be paralleled for higher. current capability.
Applications include relay drivers. hammer drivers. lamp drivers. display drivers (LED and gas discharge).
line drivers. and logic buffers.
The SN75465 has a 1050-ohm series base resistor and is especially designed for use with TTL where
higher current is required and loading of the driving source is not a concern. The SN75466 is a generalpurpose array and may be used with TTL. P-MOS. CMOS. and other MOS technologies. The SN75467
is specifically designed for use with 14- to 25-volt P-MOS devices and each input has a zener diode and
resistor in series to limit the input current to a safe limit. The SN75468 has a 2700-ohm series base resistor
for each Darlington pair for operation directly with TTL or 5-volt CMOS. The SN75469 has a 10.5-kilohm
series base resistor to aUow its operation directly from CMOS or P-MOS that use supply voltages of 6
to 15 volts. The required input current is below that of the SN75468 and the required voltage is less than
that required by the SN75467.
logic symbol t
COM
18
28
38
48
58
68
7B
11)
(2)
(3)
(4)
15)
(6)
(7)
4C
~
(I)
.
CD
>
';:
c
J:
(16)
lC
';:
(15)
2C
(14)
3C
Q.
:.
5C
6C
;k>-~____t-~ll~3~) 4C
7C
7B
=~;a{nr:I~1Ji ~:\:~:; :;=::A:'~I not
:::J
U
3C
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
PRODUCTION DATA doc...e........i. i.f.rmlti••
c.rrent .. of publicllion de... Prad.ct8 ...form t.
spacifications plr the terms at TaXI. Instruments
...
COM
lC
2C
~
...oca
'!!CD
logic diagram
(9)
II
(12)
5C
(11)
6C
~>-....._______I;.;I;;;O)~ 7C
Copyright © 1986. Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
5-101
SN75465 THRU SN75469
DARLINGTON TRANSISTOR ARRAYS
schematics .(each Darlington pair)
INPUT B
SN75467
SN75466
COM
RB
INPUT B
SN75465: RB - 1.05 kll
SN75468: RB - 2.7 kll
SN75469: RB - 10.5 kll
II
'--~-E
SN75465.SN75468.SN75469
All resistor values shown are nominal.
absolute maximum ratings at 25°C free-air temperature (unless otherwise noted)
Collector-emitter voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 V
Input voltage (see Note 1): SN75465 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 V
SN75467, SN75468, SN75469 .......................... 30V
Peak collector current (see Figures 14 and 1 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 500 mA
Output clamp diode current ................................................ 500 mA
Total emitter-terminal current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 2.5 A
Continuous dissipation (total package) at (or below) 25°C free-air temperature (see Note 2):
o package .....................•................................... 950 mW
N package ......................................................... 1650 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OOC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 260°C
NOTES:
5-102
1. All voltage va,lues are with respect to the emitter/substrate terminal, E, unless otherwise noted.
2. For operation above 25 DC free-air temperature. derate the 0 package linearly at the rate of 7.6 mW/DC and derate the N package
linearly at the rate of 13.2 mW/DC.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALlAS, TeXAS 75265
SN75465, SN75466, SN75467
DARLINGTON TRANSISTOR ARRAYS
electrical characteristics at 25°C free-air temperature (unless otherwise noted)
PARAMETER
TEST
Collector cutoff current
1
Il(0ff)
Off-state input current
3
VCE - 100 V, IC - 500
II
Input current
VI - 3 V
Vl(onl
On-state input voltage
4
5
IR
Clamp diode reverse current
Clamp diode forward
VF
Ci
voltage
TYP
MAX
50
VCE - 100 V, II - 0,
100
TA - 70°C
~A,
50
TA - 70°C
mA
2.4
V
IC - 350 mA
Ic - 100 mA
0.9
II = 350~,
IC = 200 mA
1.0
1.3
II - 500 ~A,
IC - 350 mA
1.2
1.6
7
VR - 100 V
VR - 100 V,
TA - 70°C
8
IF = 350 mA
Input capacitance
VI = OV,
1.1
50
100
f = 1 MHz
~A
2.4
II - 250 ~A,
6
UNIT
~A
65
1.5
VCE - 2 V,
Collector-emitter
saturation voltage
MIN
VCE = 100 V, II = 0
ICEX
VCE(sat)
SN75465
TEST CONDITIONS
FIGURE
V
~A
1.7
2
V
15
25
pF
electrical characteristics at 25°C free-air temperature (unless otherwise noted)
PARAMETER
ICEX
11(0ff)
II
Collector cutoff current
hFE
1
TEST CONDITIONS
4
VI - 17 V
VCE = 2 V,
5
VCE - 2 V, IC - 300 mA
250 pA, Ic
100 mA
II
II - 350 pA, IC - 200 mA
II - 500 pA, IC - 350 mA
7
VF
Clamp diode forward voltage
8
Ci
Input capacitance
IC = 350 mA
50
65
~
50
65
...
III
pA
0.82
1.25
mA
1000
13
0.9
1.1
0.9
1.1
1.0
1.2-
1.3
1.0
1.3
1.6
1.2
1.6
VR-l00V
50
1.7
f - 1 MHz
50
100
VR - 100 V, TA - 70°C
IF - 350 mA
VI - 0 V,
UNIT
500
IVI - 6 V
6
Clamp diode reverse current
MAX
50
Input current
IR
TYP
100
VCE - 50 V, IC - 500 pA,
TA = 70°C
6
MIN
50
3
Collector-emitter
VCE(sat)· saturation voltage
SN75467
MAX
100
Off-state input current
transfer ratio
TYP
VCE = 100V,ili = 0
TA = 70°C
On-state input voltage
SN75466
MIN
VCE = 100 V, 11=0
2
Static forward current
Vl(on)
TEST
FIGURE
15
2
25
100
V
V
...oca
...
:i
::::J
fCD
>
"0::::
C
~
ca...
.::::
1.7
2
V
15
25
pF
CD
c.
"0::::
d?
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5-103
SN75468, SN75469
DARLINGTON TRANSISTOR ARRAYS
electrical characteristics at 25 DC free-air temperature (unless otherwise noted)
PARAMETER
ICEX
Collector cutoff current
TEST
FIGURE
1
2
IHoff)
Off-state input current
3
II
Input current
4
SN75468
TEST CONDITIONS
MIN
TYP
SN75469
MAX
VCE - 100V, II - 0
50
VCE - 100V,jll- 0
100
MIN
TYP
100
TA = 70·C
50
TA = 70·C
3.85 V
VI
65
0.93
50
65
VCE = 2 V
0.35
0.5
1.0
1.45
2.4
IC - 250 mA
2.7
7
'l
:::3.
"C
::r
Clamp diode reverse current
7
VF
Clamp diode forward voltage
a
Ci
Input capacitance
8
II = 350 pA, IC = 200 mA
<
CD
1.0
1.2
1.3
1.0
1.3
1.6
1.2
1.6
VR = 100 V, TA = 70·C
IF - 350 rnA
PARAMETER
c:::3.
1.1
f = 1 MHz
0.9
1.1
50
50
100
100
1.7
2
1.7
2
15
25
15
25
V
pA
V
pF
switching characteristics at 25 DC free-air temperature
CD
i
0.9
VR = 100 V
VI = 0 V,
V
3
II - 500 pA, IC - 350 mA
IR
6
Ic - 275 mA
IC - 350 mA
II = 250 pA, IC = 100 mA
6
mA
5
IC - 200 mA
IC - 300 mA
Collector-emitter
VCE(sat) saturation voltage
pA
1.35
VI - 5 V
5
pA
500
IVI - 1 V
VCE - 50 V, Ic - 500 pA,
Ic = 125 mA
On-state input voltage
UNIT
50
VI - 12 V
Vllon)
MAX
TEST CONDITIONS
MIN
TYP
MAX
tPLH
Propagation delav: time, low-to-high-Ievel output
Vs = 50 V,
RL = 163
(I,
0.25
1
~
tPHL
Propagation delay time, high-to-Iow-Ievel output
CL=15pF,
See Figure 9
0.25
1
ps
VOH
High-level output voltag .. after switching
Vs - 50 V,
10
~
300 mA,
See Figure 10
~
.);
~
C
II)
8'
~
5-104
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
VS-20
UNIT
mV
SN75465 THRU SN75469
DARLINGTON TRANSISTOR ARRAYS
PARAMETER MEASUREMENT INFORMATION
OPEN
OPEN
VCE
ICEX
ICEX
+--
+--
OPEN
FIGURE 1. ICEX
FIGURE 2. ICEX
OPEN
OPEN
IHon)
---+
VI---t
~~"""-OPEN
•
~
FIGURE 4.11
FIGURE 3. IHoff)
o
;
....U:::J
OPEN
OPEN
IC
hFE =
II
~
!II
...
G)
·c>
Q
'!
G)
.c
c.
NOTE: II is fixed for measuring VCE{sat), variable for measuring hFE.
FIGURE 5. VUon)
FIGURE 6. hFE. VCE(sat)
·c
:.
OPEN
FIGURE 8. VF
FIGURE 7.IR
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
5-105
SN75465 THRU SN75469
DARLINGTON TRANSISTOR ARRAYS
PARAMETER MEASUREMENT INFORMATION
OPEN
INPUT
Vs - 60 V
'466 only
2.7 kII
RL - 1630
-~-1
--'748
6'-
'467
'468
'469
)C~+-'-
__
~--O~T
I T (5CL..- Note
15 pF
BI
__ ...J
":'
":"
TEST CIRCUIT
---...
,.....$
i ~90%
INPUT
~
14-$
--.j
5 na
I 60%
10%; I
I
50%
I
---"';';;.;,;;jI1
~
10 n.
90%~I-i----------~N ••eCI
0.5,..
10%
I ~:.:::..------
0 V
..
_'PHL~
'---'PLH-tt
I r----VOH
--------""'\ I
6Oy_____
OUTPUT
",0%
VOL
VOLTAGE WAVEFORMS
-:.
NOTES: A. The pulse generator has the following characteristics: PRR' = 1 MHz, Zout - 50 II.
B. CL includes probe and jig capacitance.
C. For testing the '465, '466, and '468, VIH = 3 V; for the '467, VIH = 13 V; for the '469, VIH = 8 V.
FIGURE 9. PROPAGATION DELAY TIMES
-6"
::r
Vs
CD
i.
OPEN
INPUT
2mH
'466 only
2.7 kII
1N3084
--~-""'I
2000
I
'465
'487
'488
'469
TEST CIRCUIT
-..I 14-$ 6 ns
I
I
I
INPUT
:
_ _ _1,;.;0;,;;%;,,_
i
I
If
OUTPUT
I
90%
1.6V
~
I
\4--$
10 ns
I
V
9 0 % i l : - - - - - - - - - - IJ!NoteCI
1.5V I
10%
V
:
°
I
40 •• -------MN
\"'-------...,.JI"'--------- ~::
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: PRR = 12.5 kHz, Zout = 50 II.
B. CL includes probe and jig capacitance.
C. For testing the '465, '466, and '468, VIH = 3 V; for the '467, VIH = 13 V; for the '469, VIH = 8 V.
FIGURE 10, LATCH-UP TEST
5-106
TEXAS,'"
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TEXAS 75265
SN75465 THRU SN75469
DARLINGTON TRANSISTOR ARRAYS
TYPICAL CHARACTERISTICS
COLLECTOR·EMITTER
COLLECTOR·EMITTER
SATURATION VOLTAGE
SATURATION VOLTAGE
,2.
i
>
6
r-TAI,
"
COLLECTOR CURRENT
(ONE DARLINGTON)
(lWO DARLINGTONS PARALLELED)
.~
~
j
~
"
'r
26"~
f
,,'260~A
l.0
h I:V
1.5
1,'350~A
II' 6oo~A--
~
j
i
100 200 300 400 600 600 700 800
!
ft
"
INPUT CURRENT
V
V I>:::
/....1::/
1.6
.:;;;;; P'
1.0
'f"
00
5OO~A
,"
500
/
"" 360~A .....
~ 0.5
o
II'~'"
.~
E
~
0.6
0
f-T~' 2s"C
.~
.t!IJ8
1.0
!
>~
2.5
> 2.0
2.0
Iil
COLLECTOR CURRENT
COLLECTOR CURRENT
~~
4110
<
400
!
350
E
I
300
I;3
200
!,}
150
I
250
RL"0}'
TA' 26"C
/'
/
/
VS" 10V
I
/
/
VS=8 V
I
I
100
100 200 300 400 500 600 700 800
Ie-Collector Currln1-mA
ICltot)-Tot.1 Collector Current-mA
FIGURE 11
FIGURE 12
50
75
100 125 150 175 200
II-Input Current-f'A
FIGURE 13
..
-------THERMAL INFORMATION
D PACKAGE
MAXIMUM COLLECTOR CURRENT
N PACKAGE
MAXIMUM COLLECTOR CURRENT
vs
vs
DUTY CYCLE
DUTY CYCLE
..
III
...o
III
::l
1:)
~
1I
CD
J 400F==f==~~~J-~~-h~~~--+-~
j
r-+--+-p.,;~-"-
'C
OL-~~_~-L-J_~~~L-~~
o
10 20 30 40 50 60 70 80 90 100
Duty Cycle - %
Duty Cycle-%
FIGURE 14
FIGURE 15
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
5-107
SN75465 THRU SN75469
DARLINGTON TRANSISTOR ARRAYS
TYPICAL APPLICATION DATA
Vss
SN75467
Vee
+V
SN75465
SN75466,SN75468
+V
OUTPUT
P-MOS TO LOAD
VDD
SN75469
TTL TO LOAD
VCC
+V
BUFFER FOR
HIGHER CURRENT LOADS
5-108
SN75465
SN75468
USE OF PULL-UP RESISTORS
TO INCREASE DRIVE CURRENT
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
+V
SN55471 THRU SN55474
SN75471 THRU SN75473
DUAL PERIPHERAL DRIVERS
02130, DECEMBER 1976-REVISED SEPTEMBER 1986
PERIPHERAL DRIVERS FOR HIGH-VOLTAGE,
HIGH-CURRENT DRIVER APPLICATIONS
•
Characterized for Use to 300 rnA
•
High-Voltage Outputs
•
No Output Latch-Up at 55 V (After
Conducting 300 rnA)
•
Medium-Speed Switching
•
Circuit Flexibility for Varied Applications and
Choice of Logic Function
•
TTL-Compatible Diode-Clamped Inputs
•
Standard Supply Voltages
•
New Plastic DIP (P) with Copper Lead
Frame Provides Cooler Operation and
Improved Reliability
SN55471, SN55472,
SN55473, SN55474 , •• JG PACKAGE
SN75471, SN75472,
SN75473 •.. D OR P PACKAGE
(TOP VIEWI
l A D 8 VCC
1B 2
7
2B
lY 3
6
2A
GND 4
5
2Y
SN554:71, SN55472,
SN55473, SN55474 ... FK PACKAGE
(TOPVIEWI
U
U«UUU
•
Z~Z>Z
3 2 1 20 19
NC
Package Options Include Plastic "Small
Outline" Packages. Ceramic Chip Carriers.
and Standard Plastic and Ceramic 300-mil
DIPs
18
NC
17
2B
NC
7
16
15
8
14
NC
lB
4
5
NC
6
lY
NC
2A
9 1011 12 13
....
UOU>U
ZZZNZ
~
'C
Q
'!CD
.c
c.
'C
description
Series 55471/7 5471 dual peripheral drivers are functionally interchangeable with Series 554518/75451 8
and Series 55461/75461 peripheral drivers, but are designed for use in systems that require higher
breakdown voltages than either of those series can provide at the expense of slightly slower switching
speeds than Series 554518/754518 (limits are the same as Series 55461/75461), Typical applications
include logic buffers, power drivers, relay drivers, lamp drivers. MOS drivers, line drivers, and memory
drivers,
:.
The SN55471/SN75471, SN55472/SN75472, SN55473/SN75473. and SN55474 are dual peripheral
AND, NAND, OR. and NOR drivers, respectively, (assuming positive logic) with the output of the logic
gates internally connected to the bases of the n-p-n output transistors,
Series 55471 drivers are characterized for operation over the full military temperature range of - 55°C
to 125°C. Series 75471 drivers are characterized for operation from OOC to 70°C.
PRODUCTION DATA do.umonls .ontain iofa,mation
current as of publication data. Preducts conform to
spacificltions par the tarms of TUBS Instruments
:~~==i~8{::I~'l~ ~!:~::i:r :.~a::~:::9t::s
not
Copyright © 1986, Texas Instruments Incorporated
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
5-109
SN55471 THRU SN55474
SN75471 THRU SI75473
DUAL PERIPHERAL DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SN55471
SN75471
SN55472
SN75472
SN55473
SN75473
UNIT
SN55474
Supply voltage, VCC (see Note 1)
Input voltage
Interemitter volt~ge (see Note 2)
Off-state output voltage
Continuous collector or output current (see Note 3)
Peak collector or output current (tw s 10 ms, duty cycle s 50%, see Note 3)
o package
Continuous total dissipation at (or below)
FK package
JG package
25°C free-air temperature (see Note 4)
P package
Operating free-air temperature range
Storage temperature range
FK package
Case temperature for 60 seconds
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds
JG package
o or P package
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
NOTES:
.-:
-S.
7
7
5.5
5.5
V
V
5.5
5.5
V
70
70
V
400
400
mA
500
mA
500
725
1375
mW
1050
1200
-55 to 125
o to 70
-65 to 150
-65 to 150
260
°C
°C
°C
300
°C
°C
260
1. Voltage values are with respect to the network ground terminal unless otherwise spedfied.
2. This is the voltage between two emitters of a multiple-emitter transistor.
3. Both halves of these dual circuits may conduct rated current simultaneously; however, power dissipation averaged over a
short time interval must fall within the continuous dissipation rating .
4. For operation above 25°C free-air temperature. refer to the Dissipation Derating Table.
:r
CD
DISSIPATION DERATING TABLE
i.
c::::!.
PACKAGE
<
CD
U;
l>
POWER
DERATING
RATING
ABOVE
TA
25°C
0
725mW
FACTOR
5.8 mW/oC
FK
1375 mW
1050 mW
11.0 mW/oC
8.4 mW/oC
25°C
JG
P
1200mW
9.6 mW/oC
25°C
25°C
2.
;
a-
recommended operating conditions
U;
SN55471
SN55472
SN75472
SN75471
SN55473
SN75473
UNIT
SN56474
MIN
NOM
MAX
MIN
NOM
MAX
Supply voltage, VCC
4.5
5
5.5
4.75
5
5.25
High-level input voltage, VIH
2.2
Low-level input voltage, VIL
0.8
Operating free-air temperature, T A
5-110
2
55
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
125
0
V
V
0.8
V
70
°c
SN55471, SN75471
DUAL PERIPHERAL POSITIVE·AND DRIVERS
logic symbol t
lA
18
2A
2B
logic diagram (positive logicl
(1)
&t>
(1)
(3) lY
~
(2)
1A
(2)
1B-........
___
(6)
(5) 2Y
(7)
(6)
2A-...I"--"""
(7J
2B-......
__
tThis symbol is in accordance with ANSI/IEEE STD 91-1984 and
IEC Publication 617-12.
FUNCTION TABLE
(EACH DRIVER)
A
B
schematic (each driverl
r------.-----.------Vcc
Y
L
L
L (on state)
L
H
L (on state)
H
L
L (on statel
H
H
H (off state I
4kn
positive logic:_ _
y ~ AS or A+B
Y
A
B
II...
~~---~---~~~~-GND
Resistor values shown are nominal.
Pin numbers shown are for the JG, D, and P packages.
II)
...oca
...;:,
electrical characteristics over recommended operating free-air temperature range (unless otherwise
notedl
.
PARAMETER
VIK
10H
TEST CONDITIONS*
Input clamp voltage
High~level
output current
VCC = MIN,
II = -12 mA
VCC = MIN,
VIH = MIN,
VOH
~
-1.2
VIL - 0.8 V,
10L = 100 mA
Low·level output voltage
VCC = MIN,
Input current at maximum input voltage
I'H
IlL
High-level input current
VCC - MAX,
Low-level input current
ICCH Supply current, outputs high
ICCL Supply current, outputs low
-1.5
-1.2
-1.5
100
0.25
0.5
0.25
0.4
0.5
0.8
0.5
0.7
(,)
IG)!!
>
.;:
V
pA
c
V, - 5.5 V
1
1
mA
40
pA
VCC - MAX,
VI - 2.4 V
VI ~ 0.4 V
40
VCC = MAX,
VI = 5 V
VCC - MAX,
VI - 0
VCC - MAX,
«
UNIT
V
VIL = 0.8 V,
10L = 300 mA
'I
SN75471
MIN TYP§ MAX
300
70 V
VCC - MIN,
VOL
SN55471
MIN TYP§ MAX
-1
-1.6
-1
-1.6
mA
8
11
8
11
mA
56
76
56
76
mA
TYP
MAX
UNIT
30
55
ns
CL =·15 pF,
25
40
ns
See Figure 1
8
20
ns
10
20
iii
...G)
.c
Co
.;:
:.
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§ All typical values are at V CC = 5 V, T A ~ 25°C.
switching characteristics. Vee = 5 V. TA = 25°e
PARAMETER
TEST CONDITIONS
tpLH Propagation delay time, low-to-high-Ievel output
tPHL Propagation delay time, high-to-Iow-Ievel output
tTLH Transition time, low-to-high-Ievel output
tTHL Transition time, high-to-Iow-Ievel output
VOH High-level output voltage after switching
10
~
200 mA,
RL ~ 50!l,
Vs - 55 V,
10 ~ 300 mA,
See Figure 2
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MIN
VS~18
ns
mV
5-111
SN55472, SN75472
DUAL PERIPHERAL POSITIVE·NAND DRIVERS
logic symbol t
lA
lB
2A
2B
logic diagram (positive logic)
(11
lot>
(21
(61
m
tThis syn',bOI is in accordance with ANSI/IEEE STO 91-1984 and
IEC Publication 617-12.
FUNCTION TABLE
schematic (each driver)
(EACH DRIVERI
l
l
Y
H (off statel
.l
H
H
H (off statel
l
H (off statel
H
H
l (on statel
A
B
positive logic:
Y
B
= AS or A+B
Resistor values shown are nominal.
Pin numbers shown are for the JG, 0, and P packages.
'1..
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
.
is·
::T
CD
i.
c
::::!.
<
CD
PARAMETER
VIK
Input clamp voltage
10H
High-level output current
TEST CONDITIONS*
2c
.
III
S'
U)
VOL
II -
= MIN,
= 70 V
VIL
= 0.8
VIH
=
VCC
VOH
VCC - MIN,
Cil
j;
VCC - MIN,
10l
Low-level output voltage
=
SN75472
MIN TYP§ MAX
UNIT
-1.2
-1.2
V
-12 rnA
= 300
MIN,
-1.5
100
300
0.25
0.5
0.25
0.4
0.5
0.8
0.5
0.7
~A
V
VIH - MIN,
rnA
=
-1.5
V,
100 rnA
VCC - MIN,
10l
SN55472
MIN TYP§ MAX
II
Input current at maximum input voltage
VCC - MAX,
VI
5.5 V
1
1
rnA
IIH
High-level input current
VCC - MAX,
VI - 2.4 V
40
40
IlL
Low·level input current
VCC - MAX,
VI - 0.4 V
1.6
~
rnA
ICCH Supply current, outputs high
ICCl Supply current, outputs low
VCC = MAX,
VI
=0
13
17
13
17
rnA
VCC - MAX,
VI - 5 V
61
76
61
76
rnA
TYP
MAX
UNIT
45
65
ns
Cl=15pF,
30
50
ns
See Figure 1
13
25
ns
10
20
ns
1.1
1.6
1.1
:t: For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§ All typical values are at VCC = 5 V, T A = 25 ·C.
switching characteristics, Vee" 5 V, TA .. 25°e
PARAMETER
TEST CONDITIONS
tPLH Propagation delay time, low-to-high-Ievel output
tpHL Propagation delay time, high-to-Iow-Ievel output
tTLH Transition time, low-to·high·level output
10
~
200 rnA,'
Rl = 500,
MIN
tTHl Transition time, high·to-Iow-Ievel output
VOH High-level output voltage after switching
5-112
Vs - 55 V,
See Figure 2
10 = 300 rnA,
TEXAS •
INSTRUMENTS
POST OFFICE BOX 865012 • DALLAS, TEXAS 76265
VS-IS
mV
SN55473. SN75473
DUAL PERIPHERAL POSITIVE-OR DRIVERS
logic symbol t
lA
lB
2A
2B
logic diagram (positive logic)
(1)
;;,:11>
~
(2)
(3) IV
(6)
(5) 2V
(7)
tThis symbol is in accordance with ANSI/IEEE STD 91-1984 and
lEe Publication 617-12.
FUNCTION TABLE
(EACH DRIVER)
A
B
schematic (each driver)
V
L
L
L (on state)
L
H
H (off state)
H
L
. H (off state)
H
H
H (off state)
A
positive logic:
V
=
A+B or
B
AS
Pin numbers shown are for the JG, D, and P packages.
Resistor values shown are nominal.
PARAMETER
VIK
10H
TEST CONDITIONS*
Input clamp voltage
High-level output current
VCC = MIN,
II = -12 mA
VCC - MIN,
VIH - MIN,
-1.2
VOH = 70 V
Vce - MIN,
VOL
SN55473
MIN TYP§ MAX
VIL - 0.8 V,
IOL = 100 mA
Low-level output voltage
Vec = MIN,
-1.5
SN75473
TVP
MIN TVP§
-1.2 -1.5
300
100
0.25
0.5
0.25
0.4
0.5
0.8
0.5
0.7
UNIT
10L = 300 mA
p.A
o
1;
...
~
U
-.
c(
,~
C
'!CD
.c
Q.
'':::
CD
II
Input current at maximum input voltage
Vec = MAX,
VI = 5.5 V
1
1
mA
IIH
IlL
High-level input current
Low-level input current
VCC - MAX,
VI - 2.4 V
-1
-1
mA
ICCH Supply current, outputs high
ICCL Supply current, outputs low
VCC - MAX,
VI -:- 0.4 V
VI = 5 V
40
-1.6
p.A
Vce - MAX,
40
-1.6
8
11
8
11
rnA
VCC - MAX,
VI -
5B
76
58
76
rnA
TVP
MAX
UNIT
30
55
a
..
! II
CD
V
V
VIL = 0.8 V,
•
!II
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
Q..
:t: For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§ All typical values are at VCC = 5 V, T A = 25 DC.
switching characteristics, Vee'" 5 V, TA - 25°e
PARAMETER
TEST CONDITIONS
tpLH Propagation delay time, low-to-high-Ievel output
tpHL Propagation delay time, high-to-Iow-Ievel output
tTLH Transition time, low-to-high-Ievel output
tTHL Transition time, high-to-Iow-Ievel output
VOH High-level output voltage after switching
MIN
ns
10
~
200 rnA,
CL=15pF,
25
40
ns
RL
~
50 0,
See Figure 1
8
10
25
25
ns
ns
Vs - 55 V,
See Figure 2
10 - 300 rnA,
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
VS-IS
mV
5-113
•
SN55474
DUAL PERIPHERAL POSITIVE·NOR DRIVER
logic symbol f
lA
lB
2A
2B
logic diagram (positive logic)
.. It>
(11
lA (11
(21
lB~(2~I""'II..._~
(61
(71
2A (61
tThis symbol is in accordance with ANSI/IEEE STO 9 I -1984 and
IEC Publication 617-12.
2B (71
FUNCTION TABLE
(EACH DRIVERI
A
schematic (each driver)
y
8
L
L
H loff state)
L
H
Lion statel
H
L
Lion statel
H
H
L Ion state)
positive logic:
y =
A+BorAB·
Pin numbers shown are for the JG package.
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
SN55474
TEST CONDITIONSt
PARAMETER
VIK
10H
VOL
Input clamp voltage
VCC = MIN,
II = -12 mA
High-level output current
VCC = MIN,
VOH = 70V
VIL = 0.8 V,
VCC = MIN,
10L = 100 mA
VIH = MIN,
VCC = MIN,
10L = 300 mA
VIH = 2 V,
Low-level output voltage
MIN
UNIT
TYP§
MAX
-1.2
-1.5
V
300
/LA
0.25
0.5
0.5
0.8
V
II
Input current at maximum input voltage
VCC = MAX,
VI - 5.5 V
1
IIH
High-level input current
VCC = MAX,
VI = 2.4 V
40
/LA
IlL
Low-level input current
VCC = MAX,
VI = 0.4 V
-1.6
mA
ICCH
Supply current, outputs high
VCC = MAX,
VI = 0
14
19
mA
ICCL
Supply current, outputs low
VCC = MAX.
VI = 5 V
67
85
mA
-I
mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§AII typical values are at VCC = 5 V, TA = 25.oC.
switching characteristics, Vee" 5 V. TA - 25°e
PARAMETER
TEST CONDITIONS
tPLH Propagation delay time, low-to-high-Ievel output
tpHL Propagation delay time, high-to-Iow-Ievel output
tTLH Transition time, low-to-high-Ievel output
tTHL Transition time, high-to-Iow-Ievel output
VOH High-level output voltage after switching
5-114
10 = 200 mA,
RL = 50
n,
Vs - 55 V,
See Figure 2
CL=15pF,
See Figure I
10 = 300 mA,
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS. TEXAS 75265
MIN
TYP MAX UNIT
40
65
ns
30
50
ns
8
20
ns
10
20
VS-IS
ns
mV
SN55471 THRU SN55474
5N75471 THRU SN75473
DUAL PERIPHERAL DRIVERS
PARAMETER MEASUREMENT INFORMATION
14-<10 n.
1
90=%:-----3 V
:,.1
INPUT 2.4 V
1.5V
10 V
1
1
1-=::.::...--II-..:..::.::.x..I-------
~
I.___
'472
PULSE
GENERATOR
(See Noto Al
I-
1.5V
OUTPUT
~~~;;~~:;"
INPUT
'472
: ' - - 0 . 5 ".
1 "<5 ns
1 I
1 90%
-+I
90%
OV
~I
I !.-< 10 n.
1-1-1-------3V
: 1
1.5 V
:
1 10%
1
OV
If-tPLH-+j
I 55r 4 I
0.4V
1
1
90%
1
....
50%
10%
10%
I
~'I_-----""I--I-
OUTPUT
tTLH~
-
VOL
!.-
•
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics: PRR
B. CL includes probe and jig capacitance. .
s
1 MHz, Zout
~
50 II.
FIGURE 1. SWITCHING TIMES
14-<10 no
-+i
1
1
VS=55V
9==0%=----3 V
I
:,.1
I
I
INPUT 2.4 V
10% I 1
5V
-1-------
~
PULSE
GENERATOR
(See Note Al
1.5V
OV
~I
II-.1---~_I~;;;~;__:::7J
OUTPUT
-+I I !.-< 10 ns
r.:-=::-----,/~__::_~.:.:'-I-I- - - - - - -3 V
90%
: 1
1.5V I
-=1;:,;0%:::"""_ _ _ 0 V
....
~
....
TEST CIRCUIT
_____J~:::
VOLTAGE WAVEFORMS
NOTES: A. The pulse g~nerator has the following characteristics: PRR s 12.5 kHz, Zout = 50 II.
B. CL includes probe and jig capacitance.
FIGURE 2. LATCH-UP TEST
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76266
5-115
•
5-116
SN75476 THRU SN75479
DUAL PERIPHERAL DRIVERS
02284, DECEMBER 1976-REVISED SEPTEMBER 1986
o OR P PACKAGE
•
Characterized for Use to 300 mA
•
No Output Latch-Up at 55 V (After
Conducting 300 mAl
•
High-Voltage Outputs (100 V Typical)
•
Output Clamp Diodes for Transient
Suppression (300 rnA. 70 VI
•
TTL- or MOS-Compatible Diode-Clamped
Inputs
•
P-N-P Inputs Reduce Input Current
•
Standard Supply Voltage
•
Suitable for Hammer-Driver Applications
•
New Plastic DIP (PI with Copper Lead
Frame Provides Cooler Operation and
Improved Reliability
ITOPVIEWI
S [ ] S VCC
lA
lY
2
3
7
6
2A
2Y
GND
4
5
CLAMP
FUNCTION TABLES
SN75476
lEACH AND DRIVERI
INPUTS
OUTPUT
A
S
Y
H
H
H
L
X
L
X
L
L
SN75477
lEACH NAND DRIVERI
description
Series 75476 dual peripheral drivers are
designed for use in systems that require high
current. high voltage. and fast switching times.
The SN75476, SN75477, SN75478. and
SN75479 provide AND. NAND, OR. and NOR
drivers. respectively. These devices have diodeclamped inputs as well as high-current. highvoltage clamp diodes on the outputs for
inductive transient protection.
The SN75476, SN75477, SN75478. and
SN75479 drivers are characterized for operation
from O°C to 70 o C.
INPUTS
OUTPUT
,y
A
S
H
H
L
L
X
H
X
L
H
f
o
'Iii
...=
SN7547S
U
lEACH OR DRIVERI
INPUTS
~
f
CD
>
'i:
OUTPUT
A
S
H
X
Y
H
X
H
H
L
L
L
Q
'!CD
SN75479
.c
Q.
lEACH NOR DRIVERI
EQUIVALENT
OF EACH INPUT
TYPICAL
OF ALL OUTPUTS
CLAMP
VCC--t-OUTPUT
'i:
INPUTS
:.
OUTPUT
A
S
Y
H
X
L
X
H
L
L
L
H
H = high level
L = low level
X = irrelevant
GND
PRODUCTION DATA documo.ts cont.in
information current as of publicatian data.
:;od;:~:on":::u~:::ifi::~~~~rr!~~:::~
Production processing dOBS not nacassari7y
include testing of all parameters.
Copyright © 1984. Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
5-117
SN75476 THRU SN75479
DUAL PERIPHERAL DRIVERS
logic symbols t
logic diagrams (positive logic)
(3)
SN75478
1A (21
&1>
~
1Y
1A
(31 1y
S
(6)
2A
(5)
(4)
positive logic: Y = AS or
2.Y
CLAMP
GND
A+S
SN75477
(3)
1Y
1A
S
(6)
2A
(5)
2Y
CLAMP
(4) GND
"'tI
positive logic: Y
CD
=
A! or i
+S
:::!,
't:J
:::r
SN75478
...
et
...C
:C'
...
en
CD
1A
(21
",11>
(3) 1Y
~
131 1y
1A
S
(6)
-
2Y
CD
IS)
l>
(')
....
....
0
CLAMP
(4) GND
C
I»
positive logic: V = A + S or
...
en
AS
SN75479
(3) 1Y
S
(6) 2Y
2A
IS) CLAMP
(4)
GND
positive logic: V =
TThese symbols are in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
5-118
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
A"'+'S or AS
SN75476 THRU SN75479
DUAL PERIPHERAL DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Continuous output current (see Note 2) ....................................... 400 mA
Peak output current: tw ,;; 10 ms, duty cycle ,;; 50% . . . . . . . . . . . . . . . . . . . . . . . . . . .. 500 mA
tw ,;; 30 ns, duty cycle,;; 0.002% ............................. 3 A
Output clamp diode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 400 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 3):
D package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 725 mW
P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1200 mW
Storage temperature range ......................................... - 65°C to 150°C'
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 260°C
NOTES:
1. Voltage values are with respect to network ground terminal.
2. Both halves of this dual circuit may conduct rated current simultaneously; however, power dissipation averaged over a short
time interval must fall within the continuous dissipation ratings.
3. For operation above 25°C free-air temperature, derate the D package at the rate of 5.8 mW/oC and the P package at the
rate of 9.6 mW/oC.
recommended operating conditions
Supply voltage, Vr.r.
0.8
V
II
70
°c
o
MIN
NOM
MAX
4.5
5
5.5
Low-level input voltage, VIL
Operating free-air temperature, T A
V
V
2
High-level input voltage, VIH
UNIT
0
....
~
IV
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
:::s
(,)
MIN TYPt
-0.95
MAX
UNIT
~
II)
-1.5
V
"-
1
100
pA
"0::;
VCC = 4.5 V, IIOL = 100 mA
0.16
0.3
VOL
Low-level output voltage
VIH = 2 V,
0.22
0.5
0.6
Output breakdown voltage
IIOL = 300 mA
VIL = 0.8 V
Vee = 4.5 V, IOH = 100pA
0.33
V(BRIO
VRIKI
Output clamp diode reverse voltage
VCC = 4.5 V,
VF(KI
IIH
Output clamp diode forward voltage
VCC = 4.5 V,
IR = 100pA
IF = 300 mA
High-level input current
VCC = 5.5 V,
VI = 5.5 V
IlL
Low-level input current
VCC = 5.5 V,
VI = 0.8 V
TEST CONDITIONS
PARAMETER
VIK
IOH
11= -12 mA
Input clamp voltage
High-level output current
A input
Strobe S
VCC - 4.5 V,
VIH - 2 V,
VIL = 0.8 V,
VOH = 70 V
ICCL
Supply current, outputs high
Supply current, outputs low
100'
V
70
0.8
100
1.15
0,01
V
1.6
V
10
~A
-80 -110
-160 -220
10
17
VI = 0
VI = 5 V
10
10
17
SN75479
VI = 0
10
17
SN75476
VI = 0
VI =5V
54
75
54
75
VI = 0
54
75
VI - 5 V
54
75
SN75477
SN75478
SN75477
SN75478
VCC = 5.5 V
VCC = 5.5 V
SN75479
V
70
VI - 5 V
SN75476
ICCH
IIOL = 175 mA
17
CD
>
c
iii
"CD
.c
c.
"0::;
:.
pA
mA
mA
t All typical values are at V CC = 5 V, T A = 25°C.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5-119
SN75476 THRU SN75479
DUAL PERIPHERAL DRIVERS
switching characteristics.
vee" 5 V. TA
..
25°e
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-high-Ievel output
tPHL
Propagation delay time, high-to-Iow-Ievel output
tTLH
Transition time, low-to-high-Ievel output
trHL
Transition time,
VOH
High-level output voltage after switching
high~to-Iow-Ievel
MIN
CL = 15 pF, RL = 100 II,
See Figure 1
MAX
200
350
ns
200
350
ns
50
125
ns
90
125
output
Vs - 55 V, 10
~300
mA,
VS-18
See Figure 2
PARAMETER MEASUREMENT INFORMATION
~~--
2_4 V
INPUT
I
I
I
SN75476 I
SN75477 I
:I
AIS
PULSE
GENERATOR
(See Note A)
SIA
I
SN75478
SN75479
..~
I
I
IL
CIRCUIT
UNDER
TEST
30V
,,----.--ir-__
-1~OUTPUT
_ _' _
OPEN
,0.4 V
;S"
TEST CIRCUIT
i"
i.
1.../--.. 5ns
..c
..
2~7vlII
~"
.....- - 3 V
SN75476 INPUT 1.5V
SN75478
~
SN75477
SN75479
C
S
..o
~
__ =03=V=-===~;=====~~
--to! I,jf re::=
..5 ns 0.5 ,..
II 2.7 V
I
I
~
I
j4
OUTPUT---~~"\J
90%
0.7 V
OV
I
tpHL
tpLH
~
5~
-
r\1
15O%0%/L'1
90% VOH
I
"",----------I-~- VOL
I I
~trHL
I I
~tTLH
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: PRR = 1 MHz, Zout = 50 II.
B. CL includes probe and jig capacitance.
FIGURE 1. SWITCHING CHARACTERISTICS
5-120
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
' UNIT
TYP
ns
mV
SN75476 THRU SN75479
DUAL PERIPHERAL DRIVERS
PARAMETER MEASUREMENT INFORMATION
Vs =55V
INPUT
5V
2.4V
r-1
.-l-,
2mH
SN75476
I
SN75477
PULSE
GENERATOR
(See Note AI
A
~
I
180n
CL = 15 pF
(See Note BI
SN75478
SN75479
I
0.4 V
I
GND
-
-
TEST CIRCUIT
1.-4- "10 ns
1---+1--- .. 5 ns
SN75476
SN75478 INPUT
SN75477
INPUT
SN75479
~:
1.5V
~
Y,!;~90~%_3V
I
II
en
....
SIV
...
::::I
15V
. -:_. . _
. .~10~:~.~~~ ~
-J ~ I ~~:1:0%="=5:n.=~4ioo-;~;.=~
~
,.... OUTPUT
to
CIRCUIT
UNDER
TEST
90%
"10":- 0 V
90%~-i-:--·---- -3V
1.5 V
1.5 V
I
10% _ _ OV
' -_
10%
to)
-..
«
en
~
';::
c
e
Q)
..c
Q.
';::
d?
OUTPUT
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: PRR
= 12.5 kHz, Zout = 50 n.
8. CI, includos probo and jig capacitanco.
FIGURE 2. LATCH-UP TEST
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
5-121
5-122
SN75603, SN75804, SN75605
HIGH·CURRENT HALF·H DRIVERS
02832. MARCH 1984-REVISEO OCTOBER 1986
I(C. KH. AND KV PACKAGES
•
Three-State Outputs
•
Continuous Output Current of
•
Outputs Can Switch 40 V
•
Transient Suppression
•
Thermal Shutdown
•
Inputs Compatible with TTL and 5-V CMOS
•
VCC Range: 8 V to 40 V
±2
(TOP VIEW)
A
lD ~~1
EN
VCC
GROUND TERMINAL IS IN
ELECTRICAL CONTACT WITH
MOUNTING BASE
FUNCTION TABLE
deBcription
INPUTS
EN
DIR
L
L
L
H
H
L
H
H
The SN75603, SN75604, and SN75605 are
high-current half-H drivers designed for highcurrent switching of bidirectional loads at
voltages from 8 V to 40 V. The devices are ideal
for the switching of bidirectional dc and stepping
motors.
SN76603
OUTPUT
SN76604
Z
Z
SN76606
L
Z
Z
Z
L
H
H
L
H
Z
The SN75603 and SN75604 are designed to be used together in pairs, which eliminates the need for
additional control logic. The SN75605 is a functional replacement for Sprague UDN2949. By controlling
the enable and direction inputs, these devices may be placed in the high-impedance output state.
logic symbols
SN76604
SN76603
EN=O
t> - N
V
E N t>
fiN
V
OUT
DIR
SN76606
EN
EN
t>f l -
V
OUT
•
OUT
DIR
DIR
logic diagrams (positive logic)
SN75603
VCC
EN---.,
DIR
SN76606
SN75604
> .........>---OUT
PRODUCTIOI DATA . _...... 10l11li1. laformllill
.......1 u of ,ullcatlal ~. Pnotlocts ..ot.... II
.,..111••11.1. pI. til. 11_ If T_ I _ a _
lii..... WI.ra.IY. P"'~ctl•• ,ra_I•• diU not
_ I I , I....da IeItIDg of III ..r a _
VCC
EN
EN---.,
DIR
.x>-.-.....--OUT
..If
INSTRUMENTS
TEXAS
POST OFFICE BOX 866012 • OALLAS. TEXAS 76286
DIR -~I---...-4
Copyright @ 1984.
T~xas
>-.......--OUT
Instruments Incorporated
5-123
SN75603, SN75604, SN75605
HIGH·CURRENT HALF·H DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 40 V
Output voltage, VO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 42 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 40 V
Output current, 10 ....................................................... ±2.5 A
Continuous total power dissipation at (or below) 110°C case temperature (see Note 1) ....... 10 W
Continuous total power dissipation at (or below) 25°C free-air temperature (see Note 2) .... " 2 W
Operating case or virtual junction temperature range ...................... - 40°C to 150°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 260°C
NOTES:
1. For operation above 110 De case temperature, derate linearly at the rate of 250 mW/De.
2. For operation above 25°C free-air temperature, derate linearly at the rate of 16 mW/oC.
recommended operating conditions
MIN
•
Vee
Supply voltage
8
VIH
High-level input voltage
2
VIL
Te
Low-level input voltage
TJ
.
-6'
CD
VOH
::r
ii
.
<'
.
o
Vee -
PARAMETER
VIK
Input clamp voltage
High-level output voltage
VOL
low-level output voltage
VOKH
High-level output clamp voltage
CD
en
i>
n
....c
....
o
II)
Ul
VOKL
MAX
40
Low-level output clamp voltage
8
V to
UNIT
V
V
0.8
Case temperature
Junction temperature
electrical characteristics.
;f
NOM
-40
125
V
DC
-40
150
DC
TYP
MAX
UNIT
-0.9
-1.5
V
40 V, TA .. 25 0 e
TEST CONDITIONS
11= 12'mA
Vce- 1.5 Vee- 0.9
Vee- 2 Vee- 1.2
10H = -1 A
10H -
MIN
-2 A
V
10L = 1 A
0.9
1.5
10L - 2 A
10 = 1 A
1.1
2
Vee+ 1.2 Vce+ 1.5
Vee+ 1.4 Vee+ 2
10 = 2 A
10 = -1 A
10 = -2 A
-1.2
-1.5
-1.4
2
0.1
V
V
V
High-impedance·state
Vo = 40 V
output current
Vo = 0
-0.1
100
-100
~A
IIH
High-level input current
VI = 5.5 V
0.Q1
10
~A
IlL
Low-level input current
VI - 0
Output at high impedance
8
20
~A
16
30
10Z
ICC
5-124
Supply current
Output at high level
35
50
Output at low level
30
40
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
mA
SN75603, SN75604, SN75605
HIGH·CURRENT HALF·H DRIVERS
switching characteristics, T A .. 25 DC
PARAMETER
TEST CONDITIONS
High-impedance-state output voltage after
VOZH
switching. with high-level voltage applied
High-impedance-state output voltage after
VOZL
switching with low-level voltage applied
Vee = 40 V,
IOl ~ 2 A,
l = 2 mH,
R = 190,
el =15 pF,
See Figure 1
Vee = 40 V,
L = 2 mH,
IOH = -2 A,
R = 190,
el = 15 pF,
See Figure 2
MIN
TYP
MAX
UNIT
mV
Vee- 1O
10
mV
tpZH
Enable time to the high level
Vee = 25 V,
1.3
~s
tpHZ
Disable time from the high level
Vee = 250,
1.B
~s
tTZH
Enable transition time to the high level
el = 15 pF,
70
ns
tTHZ
tpZl
Disable transition time from the high level
See Figure 3
500
ns
Enable time to the low level
Vee = 25 V,
1
~s
tPLZ
Disable time from the low level
Rl = 250,
2.5
~s
tTZl
Enable transition time to the low level
el = 15 pF,
100
ns
tTlZ
Disable transition time from the low level
See Figure 4
100
ns
II.
II)
....oas
~..
II)
G)
>
·C
Q
~G)
.c
C·C
:.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
5-125
8N75603, 8N75604, 8N75605
HIGH·CURRENT HALF·H DRIVER8
PARAMETER MEASUREMENT INFORMATION
INPUT
I
PULSE
GENERATOR
(See Note AI
)~ L
Vcc
- 2 mH
.
EN
R - 1 911
CIRCUIT
UNDER
TEST
OUTPUT
OUT
CL - 15 pF
See Note BI
DIR
. _ DIR
(See Note CI
GND
1
•
VCC - 40 V
)
T'
TEST CIRCUIT
14--- 10 ".--~
3V
l...
INPUT
SN75605
'6'
::r
G)
...
...c
...<'
!!t
14~f---10 ".--~
INPUT
SN75603 .
SN75604
G)
III
i>
n
....c
III
....o
OV
;;;
OUTPUT
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: PRR = 50 kHz, Zout
B. CL includes probe and jig capacitance.
C. DIR is low for SN75603 and SN75605, and high for SN75604.
FIGURE 1. LATCH·UP TEST
5-126
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
=
50 11, tr
s 5 ns, tf S 5 ns.
5N75603, 5N75604, 5N75605
HIGH-CURRENT HALF-H DRIVER5
PARAMETER MEASUREMENT INFORMATION
INPUT
VCC - 40 V
I
VCC
PULSE
GENERATOR
(See Note AI
:;::1' (See
CL - 15 pF
Note BI
EN
CIRCUIT
UNDER
TEST
DIR
_
(See Note CI
OUT
~h
OUTPUT
- 2 mH
)
DIR
R - 190
GND
.1
-
':'
'::'
TEST CIRCUIT
~
101'5
I
I
INPUT
1.5V
OV
...oas~
...
~
(,)
OUTPUT
Q)
C:::L
>
-t:;
VOLTAGE WAVEFORMS
NOTES:
..
~
en
/
A. The pulse generator has the following characteristics: PRR ~ 50 kHz, Zout
B. CL includes probe and jig capacitance.
C. DIR is low for SN75603 and SN75605, and high for SN75604.
FIGURE 2. LATCH-UP TEST
=
Q
50 0, Ir 5 5 ns, If 5 5 ns.
"!
Q)
.c
Q.
-t:;
:.
TEXAS ~
5-127
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS
7526~
SN75603, SN75604, SN75605
HIGH·CURRENT HALF·H DRIVERS
PARAMETER MEASUREMENT INFORMATION
INPUT'
VCC - 25 V
I
VCC
PULSE
GENERATOR
(See Note A)
:;;~CL - 15 pF
EN
(See Note B)
CIRCUIT
UNDER
TEST
OUTPUT
OUT
. _ DIR
DIR
(See Note C)
RL - 2511
GND
~
TEST CIRCUIT
~..........--10ps ...............~
-3V
"l
:::!.
INPUT
I
"0
:::r
tPZH*-+!
CD
!.
I
OUTPUT
~
...
en
n
90%
I
I
I I
50%
10%
trZH-+!
);
en
)f
'90%
c:::!.
...c
ao
...
OV
tot
tpHZ "-
'I
~
VOH - 100%
50%
I
10%
VOZL
I I
j.-
~
~tTHZ
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: PRR = 50 kHz, Zout 50 II, tr :s 5 ns, tf :s 5 ns.
B. CL includes probe and jig capacitance.
C. DIR is high for SN76603 and SN75605, and low for SN75604.
FIGURE 3. SWITCHING TIMES. ENABLE TIME TO HIGH·LEVEL AND DISABLE TIME FROM HIGH·LEVEL
5-128
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS, TEXAS 75265
SN75603, SN75604, SN75605
HIGH·CURRENT HALF·H DRIVERS
PARAMETER MEASUREMENT INFORMATION
INPUT
VCC - 25 V
I
VCC
PULSE
GENERATOR
ISee Note AI
EN
R - 2 511
CIRCUIT
UNDER
TEST
OUTPUT
OUT
r
DIR
DIR
(See Note C I -
L - 15 pF
ee Note BI
GND
1
S~N:S~~3
TEST CIRCUIT
..c-:s.--
3V
3 V
..- • ~
SN75604J! .. - •
I
I
tPlL~
OV
I
I
tTlL
-.t
I
I
•
I
I
I
V
90% OlH
I
I
OUTPUT
I
- - - - " ' , - - -0 V
~tPLZ
~tPLZ
I
90%
INPUT
SN75605
I
I
~
I
-.I
-I--VOL
I
!f-tTLl
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: PRR = 50 kHz. lout '" 50 O. tr S 5 ns. tf S 5 ns.
B. CL includes probe and jig capacitance. •
C. DIR is low for SN75603 and SN75605. and high for SN75604.
FIGURE 4. SWITCHING TIMES. ENABLE TIME TO LOW LEVEL. AND D,lSABl.E TIME FROM LOW LEVEL
TEXAS ."
INSTRUMEl'llS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
5·129
8N15603, 8N15604, 8N15605
HIGH·CURRENT HALF·HDRIVER8
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT CURRENT
vs
OUTPUT VOLTAGE
LOW·LEVEL OUTPUT CURRENT
vs
OUTPUT VOLTAGE
2.0
c(
I
~
~::I
0
I
Vee - 8 V
TA - 25°e
1.5
CJ
i!i
0
1.0
~
~
..9
...I
~
0.5
o
II
I
I
~
~
o
0.5
J
-0.5
/V
::I
CJ
!i
;
0
/
.
l
I
Vee - 8 V
TA - 25°e
c(
-1.0
...i:..
'i
>
r
J
-1.5
I
:t
~
-2.0
2
1.5
6.5
6
/
7
7.5
8
VOH-High-Level Output Voltage-V
VOL -Low-Level Output Voltege-Y
FIGURE 5
FIGURE 6
TYPICAL APPLICATIONS INFORMATION
SN75603 and SN75604 in speed·controlled, reversible dc motor drive
The SN75603 and SN75604 are recommended for continuous current applications of up to 2 amperes.
The application shown in Figure 7 illustrates. a reversible dc motor drive circuit with adjustable speed control.
The DIR inputs for these drivers are complementary and therefore may be tied together and driven from
the same logic control for bidirectional motor drive. The enables (EN) are tied together and driven by a
pulse-width-modulated generator providing "on" duty cycles of 10% to 90% for speed control. A separate
enable control is provided through a SN7409 logic gate.
5-130
TEXAS
~
INSTRUMENTS
POST OFFice· BOX 655012 • DALLAS. TeXAS 75265
SN75603, SN75604, SN75605
HIGH·CURRENT HALF·H DRIVERS
TYPICAL APPLICATIONS INFORMATION
5V
r-----------------~~--_.~----~~--~~._----~~----_.--------~-----12V
6200
2.7 kO
r
+
1 kO
10l'F
TLC555
L
141
RESET
(71
10 kO
+
TL431
181
2.7 kO
VDD
10
l'F
DISC
IN914
H
161
THRES
OUT
131
1.2 kO
1 kO
121
+---A
TRIG
IN914
DIR
DIR
GND
JO.11'F
SN75603
GND
SN75604
5V
.....oca
(141
111
SN7409
ENABLE---.
en
VCC
131
...u:::s
(21
GND
..
..
~
en
171
-=
LOGIC INPUT
DIRECTION
CONTROL
G)
FIGURE 7. SN75603 AND SN75604 IN A BIDIRECTIONAL MOTOR
CONTROL APPLICATION WITH SPEED CONTROL
FUNCTIONAL TABLE FOR MOTOR CONTROL CIRCUIT
MOTOR
DIRECTION
MOTOR
SPEED
DEFINITION OF TERMS USED IN FUNCTION TABLE
EN ..... :Enable
EN
DC
SPC
L
X
N
OFF
OFF
H
X
L
A
SLOW
H
L
W
A
FAST
B ...... Direction of current-left to right
H
H
N
SLOW
H ...... High logic level
H
H
W
B
B
FAST
L ....... Low logic level
DC ..... Direction control
>
.;:
Q
iii
G)
~
Q.
';:
:.
SPC ... . Speed control
A ...... Direction of current-right to left
N ...
.. Speed control set for narrow pulse width
W ...... Speed control set for wide pulse width
X ...... Irrelevant
. TEXAS'"
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265
5-131
SN75603. SN75604. SN75605
HIGH·CURRENT HALF·H DRIVERS
TYPICAL APPLICATIONS INFORMATION
power solenoid drive
The SN75603, SN75604, and SN75605, with up to 70 watts of output drive capability, are ideal for driving
high-power solenoids. In applications that require high drive currents, these devices may be used as individual
drivers or combined for bidirectional drive applications. A typical application would be a power solenoid
operating a fluid-flow-control valve.
Figure 8 shows the SN75603 and the inverting SN75604 in a basic drive configuration for a reversing
power solenoid.
EN
Vee
POWER
SOLENOID
DIR
.
'1
-6"
FIGURE 8. REVERSIBLE POWER SOLENOID DRIVE
:::T
CD
i.
.c<"
..
CD
en
l>
~
c
a
o
.
en
5-132
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
ADVANCE
INFORMATION
SN75608
DUAL FLUX-REGULATING ACTUATOR
02955. DECEMBER 1986
•
2.5-A Current Capability per Channel
•
For Split-Supply Applications
•
Wide Differential Supply Voltage
Range ... 30 V to 60 V
•
•
:2
KV SINGLE-IN-LINE PACKAGE
o
ITOP VIEW)
~15
High-Impedance Clamped Inputs Compatible
with TTL or CMOS Devices
Output Clamp Diodes for Inductive Transient
Suppression
)
14
)
13
)
12
)
11
)
10
)
0
Thermal Shutdown
•
Internal ESD Protection
6
•
Short-Circuit Protection on Sink Outputs
4
•
Input Hysteresis Improves Noise Immunity
3
•
No Output Glitch During Power-Up or
Power-Down
•
15-Pin SIP Power Package
5
~
1
a:
ou.
VEE
:2
TC
7
2
«
~
2CAP
9
8
•
i=
2S0URCE
VCC
2SINK
2A
VEE
)
)
w
1CAP
VEE
GND
1A
1SINK
VCC
1S0URCE
(.)
:2
~
«
C
The tab is electrically connected to the VEE pins .
description
The SN75608 is a high-current dual flux-regulating actuator designed for switching double-ended loads
with currents up to 2.5 amperes at differential supply voltages from 30 volts to 60 volts. It is designed
to drive and control the electromagnetic flux in printheads, solenoids, relays, and other loads whose
inductance value varies during operation.
•
The SN75608 performs the function of flux regulation under control of standard TTL or CMOS input signals
for two independent channels. Flux is proportional to the integral of the inductive-load volt;lge. It is a function
of t!1e total amount of current in the load and is the magnetic field maintained in the load. With flux regulation,
the load current will vary to compensate for core saturation, temperature changes, and other variations
of load inductance during operation while maintaining controlled, relatively constant flux in the load.
Each channel has separate sink and source driver outputs for driving each end of the inductive load. Internal
feedback, consisting of an integrator and voltage comparator, provides flux regulation via chop-mode
operation of the source output. The integrator circuit provides current to the capacitor terminal (CAP)
proportional to the differential voltage between the sink and source outputs for each channel. The integrator
requires an external capacitor connected between the CAP and VEE terminals. The voltage at the CAP
terminal, referenced to VEE, is proportional to the integral of the source to sink (load) voltage.
The feedback path is completed by a differential voltage comparator that controls the state of the source
output. The inverting comparator input is connected to the CAP terminal, and the non inverting input is
connected to an analog voltage, Vref(TC), which is referenced to VEE. Vref(TC) is proportional to the
Threshold Control (TC) voltage, which is referenced to ground. The comparator hysteresis controls the
charge and discharge voltage excursions at the CAP terminal and thus controls the on and off time of
the source output chopper.
ADVANCE INFORMATION documants contain
~:;=~~:;h= Jr3:....-:.:::.~~~::~~':Pst~~
~ata and othar spacificatioils Ire subjact to chango
withDut notice.
Copyright © 1986, Texas Instruments Incorporated
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5-133
8N75608
DUAL FLUX-REGULATING ACTUATOR
»
c
<
»
2
ADVANCE
INFORMATION
description (continued)
(")
m
2
"T1
o
The SN7560S features built-in thermal protection and a sink output over-current sensor to prevent damage
to the device. The outputs are disabled under low-VCC or low-VEE supply-voltage conditions to prevent
transient output turn-on during power-up or power-down. The TC input'is a combined threshold and logic
input that disables the outputs when the TC input voltage is less than O.S V. This permits an external
RC time delay at the TC input during logic system power-up to allow logic at input A to stabilize without
causing undesired output turn-on. When a fault condition is detected by anyone of these five protection
features, the RS latch for each channel is set. The fault condition must be removed and the A input taken
high before the RS latch will reset, reactivating the channel.
The SN7560S is characterized for operation from -20°C to S5°C.
::a
s:
~
o2
•
DRIVER FUNCTION TABLE (EACH CHANNEL)
INPUTS
OUTPUTS
A
TC
CAP
SOURCE
SINK
X
:s0.8 V
X
OFF
OFF
H
;;.:2 V
X
OFF
OFF
L
",2 V
VT-
OFF
ON
OPERATING MODE
Disabled
COMMENTS
TC acts as a digital input referenced to GND
TC acts an an analog input referenced to GND
Active
(See Note 1)
INTEGRATOR FUNCTION TABLE (EACH CHANNEL)
VOLTAGE
INPUTS.
A
C
:::!.
;;
Ci'l
CAP
DIFFERENTIAL VOLTAGE
CAP TERMINAL
VOLTAGE
VO(SOURCE) - VO(SINK)
(See schematic)
X
TC
:;;0.8 V
X
X
01 Sinking
H
",2 V
X
X
01 Sinking
L
",2 V
X
",300 mV
L
;;.:2 V
>VT-
:s-300 mV
INTEGRATOR MODE OF OPERATION
02 Sourcing
03 Sinking
Reset
Charge
Discharge
H = high level; L = low level; X = irrelevant
NOTE 1: The TC input has an operating range from 0 Vto 6 V. but its effect on the CAP terminal is linear from approximately
2 V to 6 V. The best linearity is achieved within the recommended operating linear range.
i>
..
2
c
C»
o
Ci'l
5-134
Reset (Disabled)
TEXAS
~
INSTRUMENTS
POST OFFICE
~ox
655012 • DALLAS, TEXAS 75265
ADVANCE
INFORMATION
SN75608
DUAL FLUX·REGULATING ACTUATOR
2
logic diagram leach channel. positive logic)
r----+~~.:':;~
r----------------------------------~--_._vcc
o
~
<2:
~
IN:UT---I-------------f
a:
oLL
CHIP
DISABLE
2
PROTECTION
LATCH
w
CJ
COMPARATOR
2
<2:
SOURCE
OUTPUT
SINK
OUTPUT
IN~~T--i---I-....-IL..:=.:.::.:..::.:...j_I----...:..::='----'
t------------t-CAP
c>
<2:
•
~
o
1ii
COMMON TO BOTH
L _ _ ~~L!... ___ ...J
GND--~~----------------~
r------....-------------VEE
TO OTHER
CHANNEL
....U:::J
~
fI)
...
G)
>
c
'C
'!
G)
..c
Q.
'C
:.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
5-135
SN7560B
ADVANCE
INFORMATION
DUAL FLUX·REGULATING ACTUATOR
»
c
<
»
:2
schematics of inputs and outputs
EQUIVALENT OF EACH A OR TC INPUT
EQUIVALENT OF EACH SOURCE OUTPUT
VCC
VCC
('")
m
:2
"T1
o
:1l
S
»
~
o
:2
A OR TC INPUT
_ _ _ _ _ _ _~~__
";:
C
V
v
V
~
G)
A
A
DC
.c
c.
";:
t The algebraic convention, in which the least positive (most negative) designated minimum, is used in this data sheet for logic voltage levels.
NOTE 1: The TC input has a operating range from 0 V to 6 V, but its effect on the CAP terminal is linear from approximately 2 V to 6 V.
:.
The best linearity is achieved within the recommended operating linear range.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
5-137
9'
w
SJOJBnJOV/SJ9A!JO IBJ94d!J9d
NOI.l'1II\IMO:lNI 3:lN'11\0'1
~
00
electrical characteristics over recommended ranges of Vee. VEE. and virtual junction operating temperature (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
Input clamp voltage at A or TC
VIK
Source output
On-state output voltage
VO(on)
Sink output
V(CAPI
CAP terminal output voltage
VOK(SRCI
Source output clamp voltage
VOK(SNKI
~
Sil
~Z
~~
~c:~
~~
~
~
~
'"
10 = -2.5 A
10 = 1 A
10 = -2.5A
10 = 1 A
10 - 2.5 A
I Source output
I Sink output
IIH
High-level input current at A
IlL
II
Low-level input current at A
Input current at TC
Current at CAP terminal
Reset mode
MAX
UNIT
-0.9
-1.5
V
VCC-1.9
VCC-3.7
VCC-2.5
VEE + 1.8
VEE+ 1.2
VEE+3
VEE+2
VEE +0.4
VEE +0.2
See Note 6
See Note 6
V
r-
VEE-1.6
VEE -1.5
VEE-2.2
VCC+1.4
VCC+2.1
VCC+2.2
-0.4
VCC+3.3
-2
1
~
2
V
;r:.
C1
rnA
VI = 0
-10
)LA
VI - 0 to 6 V
±10
)LA
VI(TCI = 5 V, V(CAPI = VEE +2 V,
RL = 1 kll from Source to Sink
VI(TC) = 2 V, V(CAPI = Vee + 5 V,
10(SRCI = - lOrnA. 10(SNKI = lOrnA
1
4
n
-I
C
pA
V(CAPI - VEE + 1 V to VEE +6 V
m
C1
V
10
Charge mode
><
=
C
VEE-1.1
0.3
Reset mode
Discharge mode
Typt
VCC-2.8
Vo = VEE
Vo = VCC
VI - 5.5 V
I(CAP)
See Note 6
10 = 2.5 A
Off-state output current
~Z
~~4'
-1 A
10(off)
~I"l
'"
10 -
I(CAPI = 1 rnA,
10 = -1 A
Sink output clamp voltage
~;:O=1
MIN
II = -12 rnA
ClM
C2
;r:. .....
r- U1
.."m
r-CI
C=
;r:.
-I
o
=
rnA
-115
)LA
5
Positive-going threshold voltage
VT+
VI(TC)
at CAP terminal (charge model
RL = 1 kll from
Negative-going threshold voltage
VT-
~
Source to Sink,
at CAP terminal (discharge model
Vhys
Normalized hysteresis at CAP
VT+
Terminal (lVT+ - VT-)NT+l
0.95 VinCI
VI(TCI = 2 V to 6 V
See Notes 7, 8, and 9
Charge mode
gmt
See Notes 7 and 8
Transconductance of integrator
Discharge mode
RL = 1 kll from Source to Sink,
V(CAP) = VeE to VT+ - 0.1 V
10(SRC) = -10 rnA, 10(SINK) = 10 rnA.
VCAP = VT+ + 0.1 V to VT- + 0.1 V
0.05
3
pS
3
t All typical values are at VCC = 20 V, VEE = -20 V, TJ = 25°C.
tTransconductance (gm) of the integrator is: I(CAP)/[V(SRC) - V(SNK)l. The ratio of VT + NI(TC) is factory adjusted to compensate for variances in gm' This causes
the integration time to be more constant from unit to unit.
NOTES: 6. These parameters must be measured on one output at a time using pulse techniques, tw = 1 ms, duty cycle < 10%.
7. Threshold values are those voltage levels at the CAP terminal at which the source output changes state. A level more positive than VT + causes the source
output to go to the off state, and a level more negative than VT _ causes the source output to go to the on state. Both VT + and VT _ are variable values
that are dependent on the voltage level at the TC input.
8. VT + and VT _ are measured differentially with CAP terminal voltage referenced to the Vee terminal.
9. Both VT + and VT _ must be measured at the same junction temperature using the same TC voltage.
2
.."
o
3:CI
=;r:.
;r:.<
-I;r:.
-2
On
2m
ADVANCE
INFORMATION
SN7560B
DUAL FLUX·REGULATING ACTUATOR
electrical characteristics over recommended ranges c)f Vee. VEE. and virtual junction operating
temperature (unless otherwise noted) (continued)
PARAMETER
lEE
Supply
Supply
Supply
Supply
ICC
Supply current from V CC All source and
ICC
lEE
IC~
current
current
current
current
from
from
from
from
TEST CONDITIONS
V CC
Disabled
VEE
VCC All source and
VEE sink outputs off
sink outputs on
lEE
Supply current from VeE
ICC
Supply current from V CC All source outputs
off and all
Supply current from VeE sink outputs on
lEE
= O.
VI/TCI = 0
VilA) = 5 V.
VIITCI = 6 V
VilA) = 0,
VIITC) = 5 V,
V/CAPI = VEE +
VilA) = 0,
VIITC) = 3 V,
V(CAP) = VEE +
MIN
VilA)
VCC = 25 V,
VEE = -25 V,
No load
2 V
5 V
Typt
MAX
UNIT
8
-13
14
-23
10
-16
18
-28
rnA
rnA
rnA
rnA
16
28
rnA
-25
-45
rnA
10
18
rnA
-20
-35
rnA
TEST CONDITIONS
tfv
ton
Sink output turn-on time from A input
toff
tfv
trY
MIN
TYP
700
MAX
UNIT
n.
900
n.
200
150
ns
ns
600
n.
Sink output turn off time from A input
900
Sink output voltage fall time (turnirg on)
Sink output voltage rise time (turning off)
100
150
ns
ns
ns
Source output voltage fall time (turning off)
~
a:
ou.
-Zw
(.)
c
switching characteristics. T A - 25°e
PARAMETER
i=
z
t All typical values are at VCC = 20 V, VEE = -20 V, TJ = 25°C.
ton
toff
trY
z
o
VCC = 20 V,
CL = 30 pF,
VeE = -20 V,
See Figure 1
TEXAS ."
INSTRUMENTS
POST OFFiCe BOX 655012 • DALLAS, TeXAS 75265
n
I
...c
I
SINK
OUTPUT
...o
I»
10%
I
I
50%
I
I
10%
~~::""---';';;':~I~-I-- Von
Ul
~trv
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: PRR " 5 kHz, tw
B. CL includes probe and jig capacitance.
=
10
/LS,
ZO
FIGURE 1. SWITCHING TIMES FROM A INPUTS
5-140
TEXAS ~.
INSTRUMENTS
, POST OFFICE BOX 655012 • DALLAS, TE~AS 75265
=
500.
ADVANCE
INFORMATION
SN75608
DUAL FLUX·REGULATING ACTUATOR
TYPICAL APPLICATION DATA
2:
A typical application of the SN75608 Dual Flux-Regulating Actuator driving inductive loads is shown in Figure 2.
Figure 3 illustrates representative waveforms that occur with the circuit connected as shown in Figure 2. The
waveforms illustrate adjustment of output current in the load to compensate for a change in the load inductance
while maintaining a constant CAP voltage waveform and thus constant electromagnetic flux in the load.
For optimum operation. both VCC pins must be connected together. close to the package. as well as all three
VEE pins. A low-impedance bypass capacitor. 10 microfarads or larger. should be connected between VCC
and VEE. also close to the package. The value of the integration capacitor connected between the CAP terminal
and VEE is dependent on the load characteristics and the performance desired. The analog voltage on the TC
terminal may be varied between 2 volts' and 6 volts for fine adjustment of integrator timing characteristics.
o
i=
C
c
.~
FIGURE 2. TYPICAL DOT-MATRIX PRINTHEAO-ORIVER APPLICATION
"!CD
.c
Co
.~
:.
TEXAS
~
INSTRUMENTS
post O~FtCE BOX 655012
• DALLAS, tEXAS 15265
5-141
SN75608
ADVANCE
INFORMATION
DUAL FLUX·REGULATING ACTUATOR
»
~
:2
TYPICAL APPLICATION DATA
c
(")
INPUT VOLTAGE
LOAD INDUCTANCE
.....,
rlf'-l
,........ 5 V
L--.J - L---...J ___ 0 V
f------
-----of,;;
m
:2
"::Do
s:
»
-I
o
-11. -
. :::n-:
.:---------- ~:: : ~~~~C~I(TC}
CAP VOLTAGE
:2
VEE
----.
• ---VCC -2 V
SOURCE OUTPUT
'1:!,
GND
VOLTAGE
"C
:::r
...
CD
!!.
- - - VEE -1.5 V
...C<'
-------
- - - VCC +.1.5V
CD
~
»
S
c
SINK OUTPUT
GND
VOLTAGE
CII
S
til
L.._.....I ___ VEE +1.5V
FIGURE 3. REPRESENTATIVE WAVEFORMS
5-142
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
ADVANCE
INFORMATION
SN75609
DUAL FLUX-REGULATING ACTUATOR
02973, DECEMBER 1986
•
2.5-A Current Capability per Channel
•
For Positive Supply Applications
•
Wide Supply Voltage Range ... 30 V to
60V
•
High-Impedance Clamped Inputs Compatible
with TTL or CMOS Devices
o
(TOP VIEW)
15
14
•
Output Clamp Diodes for Inductive Transient
Suppression
•
Thermal Shutdown
•
Internal ESD Protection
•
Short-Circuit Protection on Sink Outputs
•
Input Hysteresis Improves Noise Immunity
•
No Output Glitch During Power-Up or
Power-Down
•
z
KV SINGLE-IN-LiNE PACKAGE
13
12
11
10
9
8
7
6
5
4
0
3
2
~
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)
)
)
)
)
)
)
)
)
)
)
)
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8N75609
ADVANCE
INFORMATION
DUAL FLUX-REGULATING ACTUATOR
l>
description (continued)
C
~
:2
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-
:2
."
o
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•
The SN75609 features built-in thermal protection and a sink output over-current sensor' to prevent damage
to the device_ The outputs are disabled under low-VCC supply-voltage conditions to prevent transient output
turn-on during power-up or power-down. The TC input is a combined threshold and logic input that disables
the outputs when the TC input voltage is less than 0.8 V. This permits an external RC time delay at the
TC input during logic system power-up to allow logic at input A to stabilize without causing undesired
output turn-on. When a fault condition is detected by anyone of these four protection features, the RS
latch for each channel is set. The fault condition must be removed and the A input taken high before the
RS latch will reset, reactivating the channel .
The SN75609 is characterized for operation from - 20°C to 85 °C.
DRIVER FUNCTION TABLE (EACH CHANNEL}
INPUTS
OUTPUTS
A
TC
CAP
SOURCE
SINK
X
sO.8 V
X
OFF
OFF
H
:.:2 V
X
OFF
OFF
L
:.:2 V
VT-
OFF
ON
OPERATING MODE
Disabled
COMMENTS
TC acts as a digital input referenced to GND
TC acts as an analog input referenced to GND
Active
(See Note 1)
INTEGRATOR FUNCTION TABLE (EACH CHANNEL)
VOLTAGE
INPUTS
"'tI
...
-6.
::r
CD
...
!!.
CD
C
:::3.
<
CD
iil
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A
TC
CAP
DIFFERENTIAL VOLTAGE
CAP TERMINAL
VOLTAGE
VO(SOURCE) - VO(SINK)
(See schematic)
X
sO.8 V
X
X
01 Sinking
H
:.:2 V
X
X
01 Sinking
L
:.:2 V
X
:.:300 mV
L
:.:2 V
=
02 Sourcing
s -300 mV
>VT-
=
INTEGRATOR MODE OF OPERATION
03 Sinking
=
Reset (Disabled)
Reset
Charge
Discharge
H
high level; L
low level; X
irrelevant
NOTE 1: The TC input has an operating range from 0 to 6 volts, but its effect on the CAP terminal is linear from approximately
2 V to 6 V. Best linearity is achieved within the recommended operating linear range.
2c
...o
m
iil
TEXAS
5-144
~
INSTRUMENTS
I'OST
O~~ICE
BOX 655012 • DALLAS. TEXAS 75265
ADVANCE
INFORMATION
SN75609
DUAL FLUX·REGULATING ACTUATOR
2:
logic diagram leach channel. positive logic)
0
i=
VCC
«
A
INPUT
~
TO OTHER
r-
-w
2:
LATCH
COMPARATOR
0
2:
SOURCE
OUTPUT
I~~--J~
SINK
OUTPUT
I
I
INPUT
Vref(TC)
I
I
CAP
COMMON TO BOTH
L __
~H~E'::.
__ - I
GND--~~-------------------------------'-----~------~--------------------~ GND
TO
OTHER
CHANNEL
a:
0
LL
PROTECTION
I
I
I
I
I....--..J........,
I
1----/
TC
CHANNEL
CHIP
DISABLE
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C
«
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.
III
...
...u
0
CIS
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Q.
TEXAS
..tJ,J
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5-145
5N75609
ADVANCE
INFORMATION
DUAL FLUX·REGULATING ACTUATOR
»
c
schematics of inputs and outputs
~
2
EQUIVALENT OF EACH A OR TC INPUT
EQUIVALENT DF EACH SOURCE OUTPUT
VCC--~-_-
VCC
(')
m
-2
."
o
::0
s:
»
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o
2
•
A OR Tt
INPUT
_...-_-1
__-J~__~~-.______ SOURCE
OUTPUT
GND-.....- -....-
- - - - -...-
EQUIVALENT OF EACH CAP TERMINAL
(INTEGRATOR OUTPUTI
....- - - GND _
EQUIVALENT OF EACH SINK OUTPUT
--------4~VCC
CURRENT
SOURCE
SINK
OUTPUT
---~~~-~~---GND
CAP
5-146
TEXAS
~
INSTRUMENTS
POST OFFice BOX 665012 • DALLAS, TeXAS 75265
ADVANCE
INFORMATION
5N75609
DUAL FLUX-REGULATING ACTUATOR
z
absolute maximum ratings over operating temperature range (unless otherwise noted)
Supply voltage range, VCC (see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to 60 V
Input voltage range, VI, A and TC inputs (see Note 4) ...................... - 1.6 V to 60 V
CAP terminal range, V(CAP) . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. -0.3 V to VCC
Source output voltage range, VO(SRC) (see Note 4) . . . . . . . . . . . . . . . . . . .. -3 V to VCC +0.3 V
Sink output voltage range, VO(SNK) (see Note 4) ...................... -0.3 V to VCC+4 V
Input current, II, A and TC inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 1 5 mA
Peak output current, source and sink outputs (nonrepetitive, tw :$ 100 /Ls), 10M .......... ± 3 A
Continuous dissipation at (or below) 90°C case temperature (see Note 5) ................ 20 W
Continuous dissipation at (or below) 25°C free-air temperature (see Note 5) ........... 3.575 W
Operating case or virtual junction temperature range ...................... - 20°C to 150°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds. . . . . . . . . . . . . . . . . .. 260°C
NOTES: 2. All voltage values, except differential Voltages, are with respect to the network ground terminal.
3. Both VCC pins must be connected together as close to the package as possible for optimum testing and operation of the
device. GND pins are handled in a like manner.
4. The maximum current limitation at this terminal generally occurs at a voltage of lower magnitude than the voltage limit. Neither
the maximum current nor the maximum voltage for this terminal should be exceeded.
5. For operation above 25°C free-air temperature, derate linearly at the rate of 28.6 mW/DC. For operation above sooe case
temperature, derate linearly at the rate of 333 mW/oC. To avoid exceeding the design maximum virtual junction temperature,
these ratings should not be exceeded. Due to variations in individual device electrical characteristics and thermal resistance,
the built-in thermal overload protection may be activated at power levels slightly above or below the rated dissipation.
o
i=
«
~
a:
oLL
-Zw
(.)
z
«
>
c
«
•
..
...
recommended operating conditions
II)
Supply VOltage, VCC
High-level input voltage at A, VIH
low-level input voltage at A. Vll
linear-range TC input voltage (see Note 1)
MIN
30
2
0.3 T
MAX
0.8
V
3
6
V
±1
A
±2.5
125
A
Continuous output current, 10
Peak output current at 40% duty cycle, 10
-20
Operating virtual junction temperature, T J
60
7
o
UNIT
V
as
::l
V
t)
~
~
Q)
>
·C
·C
Q
tThe algebraic convention, in which the least positive (most negative) designated minimum, is used in this data sheet for logic voltage levels.
NOTE 1: The TC input has an operating range from 0 to 6 volts, but its effect on the CAP terminal is linear from approximately 2 V to
6 V. Best linearity is achieved within the recommended operating linear range.
'!
Q)
.s::.
Q.
·C
:.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5-147
SJo~emO" ISJ9A!JOleJ94d!J9d
'f
~
OJ
NOll"II\IHO:lNI 3:JN"1\0"
electrical characteristics over recommended ranges of Vee and virtual junction operating temperature (unless otherwise notedl
TEST CONDITIONS
PARAMETER
VIK
Input clamp voltage at A or TC
II -
Source output
VO(on)
On-state output voltage
VlCAP)
CAP terminal output voltage
VOK(SRC)
Source output clamp voltage
Sink output
VOK(SNK)
-12mA
10 = -1 A
10 = -2.5 A
10 - 1 A
10 = -2.5A
10 = 1 A
10 = 2.5 A
I Source output
I Sink output
Typt
MAX
UNIT
-0.9
-1.5
V
VCC-2.8 VCC-l.9
1.2
Reset mode
See Note 6
See Note 6
1.8
2
3
0.2
-1.1
0.4
-1.6
-1.5
-2.2
VCC+ 1.4 VCC + 2.1
-
VCC+2.2 VCC+3.3
-0.4
-2
Vo - 0 V
V
V
mA
Off-state output current
:Q
Vo = VCC
VI = 5.5 V
'ii
IlL
II
Low-level input current at A
VI - 0
-10
~A
Input current at TC
VI = 0 to 6 V
±10
~A
~~
!~r
I(CAP)
Current at CAP terminal
~~
~@4r
'"
V(CAP) ,; 1 V to 6 V
Charge mode
VI(TC) = 5 V, V(CAP) = 2 V,
RL = 1 kll from Source to Sink
Discharge mode
rt"'1
~z
Reset mode
10(SRC) = -10 mA, 10(SNK) = 10 mA
RL = 1 kll from
Vhys
VT+
terminal UVT + - VT - )iVT + J
gm;
Transconductance of integrator
mA
-115
~A
5
0.95 VI(TC)
See Notes 7, 8, and 9
Discharge mode
----------
:zJ
VI(TC) = 3 V to 6 V
Charge mode
---
....l=oCI
See Notes 7 and 8
Source to Sink,
at CAP terminal (discharge mode)
Normalized hysteresis at CAP
4
~A
....C
VI(TC)
at CAP terminal (charge mode)
Negative-going threshold voltage
VT-
~
'"
VI(TC) - 2 V, V(CAP) - 5 V,
Positive-going threshold voltage
VT+
N
~
1
5:2
C)
l=o
High-level input current at A
1
m
n
IIH
10
;i,
C
10(011)
~z
.."en
r-CI
CCI:I
C)
V
2i
0.3
l=o .....
r- c:n
><
VCC-3.7 VCC-2.5
See Note 6
10 = 2.5 A
I(CAPI - 1 mA,
10 = -1 A
Sink output clamp voltage
MIN
CI en
C2
"-----._--
RL - 1 kll from Source to Sink,
V(CAPl = 0 V to VT + - 0.1 V
10(SRC) = - 10 mA, 10(SINK) = 10 mA,
-"-CAP = VT±.. + 0.1 V to_VT_ + 0.1 V
0.05
3
~S
3.
t All typical values are at VCC = 40 V, TA = 25°C.
;Transconductance (gm) of the integrator is: i(CAP)/[V(SRC) - V(SNK)J. The ratio 01 VT +iVl(TC) is lactory adjusted to compensate lor variances in gm. This causes
the integration time to be more constant from unit to unit.
NOTES: 6. These parameters must be measured on one output at a time using pulse techniques, tw = 1 ms, duty cycle <10%.
7. Threshold values are those voltage levels at the CAP terminal at which the source output changes state. A level more positive than Vr + causes the source
output to go to the off state, and a level more negative than Vr _ causes the source output to go to the on state. Both VT + and Vr _ are variable values
that are dependent on the voltage level at the Te input.
8. Vr + and Vr _ are measured differentially with CAP terminal voltage referenced to the GND terminal.
9. Both Vr + and Vr _ must be measured at the same junction temperature using the same Te voltage.
:2
.."
CI
:zJl=o
3:CI
l=o<
.... l=o
-2
Cln
2m
ADVANCE
INFORMATION
SN75609
DUAL FLUX·REGULATING ACTUATOR
electrical characteristics over recommended ranges of
temperature (unless otherwise noted) (continued)
PARAMETER
Supply current
M.IN
= O.
VIITC) = 0
VI(A) = 5 V.
VI(TC) = 5 V
VI(A) = O.
VI(TC) = 5 V.
V(CAP) = 2 V
VI(A)
All source and
sink outputs off
All source and
sink outputs on
VCC = 50 V.
No load
All source outputs
VI(A) - O.
off and all
VI(TC)
TYpt
MAX
19
34
26
37
26
46
26
46
o
UNIT
i=
C
switching characteristics. T A = 25 °e
Ion
Source output turn-on time from A input
PARAMETER
TEST CONDITIONS
TYP
700
Ioff
trv
Source output turn-off time from A input
900
ns
Source output voltage rise time (turning on)
200
ns
tfv
Source output voltage fall time Iturning off!
150
ns
ton
Sink output turn-on time from A input
toff
VCC
= 40 V.
CL
= 30
pF.
See Figure 1
MIN
MAX
UNIT
ns
600
ns
Sink output turn off time from A input
900
ns
tlv
Sink output voltage fall time (turning ani
100
ns
trv
Sink output voltage rise time (turning offl
150
ns
PARAMETER MEASUREMENT INFORMATION
C
~
40 V
40V
:2
INPUT
o
5V
m
RL - 30 Il
VCC
TC
:2
A
o
CAP
SINK
.--...-_1-------- SINK OUTPUT
1
CL-30pF
(See Note B)
"T1
:2J
SOURCE ~~----~~----SOURCEOUTPUT
2V
3:
l>
::::1
TEST CIRCUIT
o
:2
ir:-90':":%~-- 3 V
90%
A INPUT
I
I
10%
I
I
14
"'tI
10%
I
-(-----OV
tw ----.!~
I
...
.g'
=-CD...
!!!.
CD
I
~toff
ton --t4--+I
I .,.".,.,.,._ _ _~~-I--- Von
90%
I
I
SOURCE
OUTPUT
I
I
I
I
:50%
I
I
10~
I
I
I
I
I
I
I
I
ton~
~toff
I
I
SINK
OUTPUT
I
II
Voff
I
I
I
I
10%
I
10%
I
~;';:':'::""---;';:':~'-I-- Von
~trv
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: PRR :5 5 kHz, tw = 10
B. CL includes probe and jig capacitance.
~s,
Zo = 50 Il.
FIGURE 1. SWITCHING TIMES FROM A INPUTS
5-150
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
ADVANCE
INFORMATION
SN75609
DUAL FLUX-REGULATING ACTUATOR
z
TYPICAL APPLICATION DATA
A typical application of the SN75609 Dual Flux-Regulating Actuator driving inductive loads is shown in Figure 2.
Figure 3 illustrates representative waveforms that occur with the circuit connected as shown in Figure 2. The
waveforms illustrate adjustment of output current in the load to compensate for a change in the load inductance
while maintaining a constant CAP voltage waveform and thus constant electromagnetic flux in the load.
For optimum operation, both VCC pins must be connected together, close to the package, as well as all three
GND pins. A low-impedance bypass capacitor, 10 microfarads or larger, should be connected between VCC
and GND, also close to the package. The value of the integration capacitor connected between the CAP terminal
and GND is dependent on the load characteristics and the performance desired. The analog voltage on the TC
terminal may be varied between 3 volts and 6 volts for fine adjustment of integrator timing characteristics.
5V
o
-
I-
c
2A
c
';:
c
'ii
...Q)
..c:
Q.
:.
A separate supply voltage (VCC 1 ) is provided for the logic input circuits to minimize device power dissipation.
Supply voltage (VCC2) is used for the output circuits.
The SN754410 is designed for operation from - 40 °C to 85°C.
ADVANCE INFORMATION d.cumonls contain
~~~~:::!~.:~h=
.r:::~p=':°C:::::~~~st~~
_ and othor spacifications are subject to chango
without notice.
.
Copyright
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
';:
© 1986, Texas Instruments "Incorporated
5-153
SN754410
QUADRUPLE HALF·H DRIVER
):>
o
<
ADVANCE
INFORMATION
logic symbol t
logic diagram
1A(21
C>
):>
(31 1y
2
o
m
:2
."
o
::xJ
S
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
):>
lEe Publication 61 7 -12.
-I
o
:2
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
VCC1------~~---
."
...
:T
CD
...
2!.
...c
<"...
CD
CD
-6'
..........--OUTPUT
INPUT
en
i>
(")
r+
c:
GND--~--~~---------~~--~~--""--GNO
Ol
r+
o...
en
5-154
TEXAS.
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
ADVANCE
INFORMATION
SN754410
QUADRUPLE HALF,H DRIVER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
2:
o
Logic supply voltage range, VCC1 (see Note 1) ........................... -0.5 V to 36 V
Output supply voltage range, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 36 V
Input voltage ............................................................. 36 V
Output voltage range, Vo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 3 V to VCC2 + 3 V
Peak output current (nonrepetitive, tw s 5 ms), IPK ............................... ± 2 A
Continuous output current, 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 1.1 A
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2) . . . . . .. 2075 mW
Continuous total dissipation at (or below) 25°C case temperature (see Note 2) ........ 7375 mW
Operating case or virtual junction temperature range ...................... - 40°C to 150°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260°C
NOTES:
1. All voltage values are with respect to the network ground terminal.
2. For operation above 25°C free-air temperature, derate linearly at the rate of 16.6 mw/oe. For operation above 25°C case
temperature, derate linearly at the rate of 59 mw/oe. To avoid exceeding the design maximum virtual junction temperature,
these ratings should not be exceeded. Due to variations in individual device electrical characteristics and thermal resistance,
the built-in thermal overload protection may be activated at power levels slightly above or below the rated dissipation.
i=
«
:E
a:
oLL
2:
w
U
2:
~
«
o
recommended operating conditions
Logic supply voltage. VCC1
Output supply voltage. VCC2
High-level input voltage. VIH
Low~revel
input voltage, Vil
MIN
MAX
4.5
4.5
2
5.5
36
V
5.5
V
Operating free-air temperature, T A
..
V
-0.3 t
0.8
V
-40
-40
±1
125
85
·C
·C
Output current. 10
Operating virtual junction temperature, T J
UNIT
(I)
o
-.
+'
CO
::::I
A
o
~
(I)
tThe algebraic convention, in which the least positive (most negative designated minimum), is used in this data sheet for logic voltage levels.
CI)
>
'0::
C
..
a;
CI)
.s::.
Q,
"0::
CD
0..
TEXAS ."
INSTRUMENTS
POST OFFice BOX 655012 • DALLAS. TeXAS 75265
5-155
SN754410
ADVANCE
INFORMATION
QUADRUPLE HALF·H DRIVER
l>
C
~
:2
(')
electrical characteristics over recommended ranges of VCC1. VCC2. and operating virtual junction
temperature (unless otherwise noted)
PARAMETER
V,K
VOH
TEST CONDITIONS
Input clamp voltage
-12 mA
10H = -0.5 A
10H - -1 A
High-level output voltage
m
-
:2
10H
l>
::::!
o
:2
=
-1 A,
TJ
=
Low-level output voltage
VOKL
10Z
"H
I,L
ICCl
ICC2
MAX
UNIT
-0.9
-1.5
V
25°C
High-level output clamp voltage
=
1 A,
TJ
=
25°C
1.2
10K - 1 A
Low-level output clamp voltage
10K
=
=
-0.5 A
-1 A
Off-state (high impedance-statel
Vo - VCC2
output current
Vo
High-level input current
V,
low-level input current
V,
Logic supply current
10
Output supply current
10
=0
= 5.5
=0
=0
=0
."
1.4
V
1.8
VCC2 + 1.4 VCC2+ 2
VCC2+ 1.9 VCC2+2.5
-1.1
-2
- 1.3
-2.5
10K - 0.5 A
10K
V
2
10L - 1 A
10L
VOKH
Typt
VCC2- 1.5 VCC2-1.1
VCC2- 2
VCC2- l .8 VCC2- l .4
1
10L - 0.5 A
VOL
"TI
o
::xJ
s:
MIN
"=
500
-500
V
V
~A
10
~A
-10
~
All outputs at high level
38
All outputs at low level
70
All outputs at high impedance
25
All outputs at high level
33
All outputs at low level
20
All outputs at high impedance
V
mA
mA
5
CD
::::!.
"0
tAli typical values are at VCCl
=
5 V, VCC2
=
24 V, TA
=
25°C.
~
CD
switching characteristics. VCC1 = 5 V. VCC2 == 24 V. TA ... 25°C
i
c::::!.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tDLH
Delay time, low-to-high-Ievel output from A input
800
ns
tDHL
Delay time, high-to-Iow-Ievel output from A input
400
ns
tTLH
Transition time, low-to-hlgh-Ievel output
300
ns
>
~
tTHL
Transition time, high-to-Iow-Ievel output
300
ns
tpZH
Enable time to the high level
700
ns
tpZL
Enable time to the low level
...
tpHZ
Disable time from the high level
tpLZ
Disable time from the low level
<
CD
iil
C
III
o
iil
5-156
CL = 30 pF,
CL
=
30 pF,
See Figure 1
See Figure 2
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
400
ns
900
ns
600
ns
ADVANCE
INFORMATION
SN754410
QUADRUPLE HALF·H DRIVER
PARAMETER MEASUREMENT INFORMATION
5 V
INPUT
2
o
i=
<
~tr
24 V
~~_3V
I
I
90%
VCC1 VCC2
PULSE
GENERATOR
ISee Note A)
A
INPUT
CIRCUIT
UNDER
TEST
3V
"-...;..---~-
..
I..--tw
CL-30pF
Iiseo Note B)
EN
~
oLL
-+ll+-tDHL
I
I
I
":"
I
o
I
I
I
OUTPUT
TEST CIRCUIT
-2w
I4-tDLH
GND
":"
a:
0 V
I
OUTPUT
V
~
I
+ - -- - -
2
.....- -1" - -
~;.;.;..-.....;..;..;.;.
~tTHL
<
>
C
VOL
~trlH
<
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: tr oS IOns, tf oS IOns, tw ~ 1 0 ~s, PRR
B. CL includes probe and jig capacitance.
=
5 kHz, Zout ~ 50 O.
FIGURE 1. SWITCHING TIMES FROM DATA INPUTS
12 V
5 V 24 V
INPUT
PULSE
GENERATOR
ISee Note A)
•
Rl- 220
INPUT
CIRCUIT
UNDER
TEST
V
OUTPUT
I
TEST CIRCUIT
OV
~I
~tPlZ
~tPZl
I
I
I
I
":"
10%
I
I+---tw
Tlsee Note BI
To 3 V for tpZH and tpHZ
To 0 V for tpZl and tplZ
I
I
Cl-30pF
A
OUTPUT
~12
I
V
I
I.-.!-tPZH
I
OUTPUT
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: tr oS IOns, tf oS IOns, tw
B. CL includes probe and jig capacitance.
~
10
~s,
PRR
~
5 kHz, Zout
~
50 O.
FIGURE 2. SWITCHING TIMES FROM ENABLE INPUTS
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 7626S
5-157
5N754410
ADVANCE
INFORMATION
QUADRUPLE HALF-H DRIVER
»
c
TYPICAL APPLICATION DATA
~
5V
24V
:2
(")
10 kll
m
-
:2
(2)
CONTROL A
Q~(3~)____________~
EN
."
(1)
o
I>
::a
EN
s:
»
(7)
Q (6)
::!
I>
o
(10)
:2
•
-:...
-6:::r
EN
(9)
EN
CONTROL B
I>
(15)
GND
(4.5.12.13)
~
i.
FIGURE 3. TWO-PHASE MOTOR DRIVER
...o
...<'
en
~
»....
(')
C
I»
....o
;
5-158
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 866012 • DAI.LAS, TeXAS 76286
,,1
I
ADVANCE
INFORMATION
SN754411
QUADRUPLE HALF-H DRIVER
02942, NOVEMBER 1986
•
1-A Output Current Capability per Channel
•
Applications Include Half-H and Full-H
Solenoid Drivers and Motor Drivers
•
Designed for Positive-Supply Applications
•
Wide Supply Voltage Range:
4,5 V to 36 V
•
TTL- and CMOS-Compatible High-Impedance
Diode-Clamped Inputs
•
Separate Input-Logic Supply
•
Thermal Shutdown
•
Internal ESD Protection
:2
NE DUAL-IN-L1NE PACKAGE
-lo-
(TOP VIEW)
1,2EN
1A
1Y
VCC1
4A
4Y
HEATSINK AND {
GROUND
2Y
2A
e:(
~
} HEATSINK AND
GROUND
3Y
3A
r::c
oLL
:2
VCC2 """<.:._--"'..... 3,4EN
(.)
(EACH CHANNEL)
:2
INPUTS
•
Input Hysteresis Improves Noise Immunity
A
EN
OUTPUT
y
•
Three-State Outputs
H
H
H
L
H
L
X
L
Z
~
high-level
•
Minimized Power Dissipation
•
Sink/Source Interlock Circuitry Prevents
Simultaneous Conduction
H
•
No Output "Glitch" During Power-Up or
Power-Down
Z
•
Improved Functional Replacement for the
SGS L293
w
FUNCTION TABLE
e:(
>
C
e:(
L ~ low-level
X = irrelevant
~
high-impedance (offl
....
~
o
IU
::::I
(,)
description
~
en
.
.
The SN754411 is a quadruple high-current half-H driver designed to provide bidirectional drive currents
of up to one ampere at voltages from 4.5 volts to 36 volts, It is designed to drive inductive loads such
as relays, solenoids, dc and stepping motors, as well as other high-current/high-voltage loads in positivesupply applications,
All inputs are compatible with TTL and low-level CMOS logic. Each output (V) is a complete totem-pole
driver with a Darlington transistor sink and a psuedo-Darlington source. Channels are enabled in pairs with
channels 1 and 2 enabled by 1,2EN and channels 3 and 4 enabled by 3,4EN. When an enable input is
high, the associated channels are enabled and their outputs become active and in phase with their inputs.
When the enable input is low, those channels are disabled and their outputs are off and in a high-impedance
state. With the proper data inputs, each pair of drivers form a full-H (or bridge) reversible drive suitable
for solenoid or motor applications,
Q)
>
-;:
C
CO
Q)
.c
c.
-;:
d?
External high-speed output clamp diodes should be used for inductive-transient suppression, A separate
supply voltage (VCC1) is provided for the logic input circuits to minimize device power dissipation, Supply
voltage (VCC2) is used for the output circuits.
The SN754411 is designed for operation from -40°C to 85°C.
Copyright © 1986, Texas Instruments Incorporated
ADVANCE INFORMATION documents contain
~~~~~3~~~rD:;h~: Jr3:v~~~~~~~~~~:~~:~~rst1!
lIata and other spacifications are subject to change
without notice.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5-159
SN754411
ADVANCE
INFORMATION
QUADRUPLE HALF-H DRIVER
»
c
logic symbol t
~
2
1A (2)
C>
EN
EN
(')
m
2
-
C>
C>
EN
EN
CS
"»s:
logic diagram
4A (15)
C>
(3)1Y
Q
Q
Q
Q
IS)2Y
(11) 3Y
(14) 4Y
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
::!
o
2
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
-
......- -......---VCC2
VCC1----.~--
.
"tI
(I) .
-6-::r
ell
i
.
c
...----OUTPUT
INPUT
~.
;
»..
GND--~--~---------
(')
..
C
III
---e-----e-------GND
o
;
5-160
TEXAS .~
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TeXAS 75266
ADVANCE
INFORMATION
SN754411
QUADRUPLE HALF-H DRIVER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
2
Logic supply voltage range, VCC1 (see Note 1) ........................... -0.5 V to 36 V
Output supply voltage range, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 36 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V
Output voltage range, Vo . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. - 3 V to VCC2 + 3 V
Peak output current (nonrepetitive, tw s 5 ms), IpK ............................... ± 2 A
Continuous output current, 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 1 .1 A
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2) ....... 2075 mW
Continuous total dissipation at (or below) 25°C case temperature (see Note 2) ........ 7375 mW
Operating case or virtual junction temperature range ...................... - 40 °C to 150°C
Storage temperature range ......................................... - 65°C to 1 50°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 260°C
NOTES:
1. All voltage values are with respect to the network ground terminal.
2. For operation above 25°C free-air temperature, derate linearly at the rate of 16.6 mWI DC. For operation above 25 DC case
temperature, derate linearly at the rate of 59 mW/oC. To avoid exceeding the design maximum virtual junction temperature,
these ratings should not be exceeded. Due to variations in individual device electrical characteristics and thermal resistance,
the built-in thermal overload protection may be activated at power levels slightly above or below the rated dissipation.
MIN
MAX
4.5
5.5
V
Output supply voltage, VCC2
4.5
36
V
2
5.5
V
-0.3 t
0.8
v
±1
A
Operating virtual junction temperature, T J
-40
125
°C
Operating free-air temperature, T A
-40
85
°C
High·level input voltage, VIH
Low-level input voltage, VIL
Output current, 10
i=
'C
Q
"!
CI)
.c
Q.
'C
:.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
5-161
SN754411
QUADRUPLE HALF·H DRIVER
»
C
<
»z
o
m
-Z
o""
::IJ
3:
»
~
oz
ADVANCE
. INFORMATION
electrical c:haracteristics over recommended ranges of VCC1, VCC2, and operating virtual junction
.temperature (unless otherwise noted)
PARAMETER
VIK
Input clamp voltage
TEST CONDITIONS
IOH = -0.5 A
VOH
High-level output voltage
,
11= -12 mA
IOH - -1 A
IOH--1A,
Low-level output voltage
Off-state (high impedance-statel
10L - 1 A
10L - 1 A,
.
VCC2- 1.8 VCC2-1.4
1
1.4
2
1.2
TJ - 25°C
V
1.8
~A
VI - 0
10
~
IlL
low-level input current
Output supply current
V
VCC2-2
TJ - 25°C
~A
High-level input current
ICC2
V
10
IIH
Logic supply current
UNIT
VI - 5.5 V
Vo - VCC2
Vo - 0
ICCl
MAX
-1.5
-0.9
500
_500
output current
10Z
Typt
VCC2-1.5 VCC2- 1.1
10L - 0.5 A
VOL
MIN
10 = 0
10 = 0
All outputs at high level
38
All outputs at low level
70
All outputs at high impedance
25
All outputs at high level
33
All outputs at low level
20
5
All outputs at high impedance
mA
mA
tAli typical values are at VCCl = 5 V, VCC2 = 24 V, TA = 25°C.
switching characteristics, VCC1 .. 5 V, VCC2 .. 24 V, TA - 25°C
PARAMETER
TEST CONDITIONS
tDLH
Delay time, low-to-high-Ievel output from A input
tDHL
Delay time, high-to-Iow-Ievel output from A input
CL = 30 pF,
See Figure 1
MIN
TYP
MAX
UNIT
800
ns
400
ns
300
ns
tTLH
Transition time, low-to-high-Ievel output
tTHL
Transition time, high-to-Iow-Ievel output
300
ns
tPZH
Enable time to the high level
700
ns
tpZL
Enable time to the low level
400
ns
tpHZ
tpLZ
Disable time from the high level
900
ns
600
ns
5·162
CL = 30 pF,
See Figure 2
Disable time from the low level
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
ADVANCE
INFORMATION
SN754411
QUADRUPLE HALF-H DRIVER
z
o
PARAMETER MEASUREMENT INFORMATION
(NPUT
5V
i=
24V
VCC1 VCC2
PULSE
GENERATOR
(Saa Nota AI
«
...ir9~O:-::%~-3V
~
a:
A
CIRCUIT
UNDER
TEST
3V
y
I
INPUT
OUTPUT
I\,..;.;;.;.;...-....;.;~r--+-
-OV
-Zw
I
~tw--""'~
CL-30pF
EN
-- -
ou..
I(S&& Not& BI
..-I 14- tDLH
.I I.
~ (4-tDHL
GND
....
I
(.)
z
I
«
I
TEST C(RCUIT
I
OUTPUT
>
c
I
«
~tTHL
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: tr " 10 ns, tf " 10 ns, tw = 10 !'s, PRR = 5 kHz, Zout = 50 D.
B. CL includes probe and jig capacitance.
•
FIGURE 1. SWITCHING TIMES FROM DATA INPUTS
INPUT
5 V
24 V
f
...o
...::s
12 V
CO
I+-*-tf
PULSE
GENERATOR
(Saa Not& AI
CJ
VCC1 VCC2
EN
~
II)
INPUT
CIRCUIT
UNDER
TEST
Y I-"'~_OUTPUT
.....'_°%___ 0 V
1
I
CL-30pF
A
I + - - - t w ---·~I
(S&& Note BI
To 3 V for tpZH and tPHZ
ToO V for tPZL and tpLZ
~tPZL
--I
....
~tPLZ
II
=12 V
I
OUTPUT
CD
>
-;:
-;
CD
.c
Q.
-;:
1
TEST CIRCUIT
.
o
.
:.
I
I..!-tPZH
1
OUTPUT
r---~
I
=12 V
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: tr " 10 ns, tf " 10 ns, tw = 10,.s, PRR = 5 kHz, Zout = 50 0.
B. CL includes probe and jig capacitance.
.
FIGURE 2. SWITCHING TIMES FROM ENABLE INPUTS
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
5-163
SN754411
QUADRUPLE HALF·H DRIVER
:t>
o
<
:t>
ADVANCE
INFORMATION
TYPICAL APPLICATION DATA
5 V
24 V
:2
(')
m
(2)
CONTROL A
:2
o
"
(1)
::0
EN
s::t>
(7)
:::!
o
"
EN
CONTROL B
CD
"
EN
(9)
."
(6)
I>
(10)
:2
•
" 1-'(...:3)-+_-._ _ _ _ _ _ _---.
EN
1
(11)
0
I>
(15)
GND
"
(14)
MOTOR
All DIODES: 1 N4935
~
-6'
(4.5.12.13)
':::J'
CD
-=
!!.
FIGURE 3. TWO·PHASE MOTOR DRIVER
~
..c
..
c2'
CD
1/1
i>
(')
....
C
....o
I»
~
1/1
5-164
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
-:'
I
TL376C
THREE-CHANNEL STEPPER-MOTOR DRIVER
D2570. DECEMBER 1979
Three Independent Inverting Stepper-Motor
Driver Circuits
NE DUAL-IN-L1NE PACKAGE
•
High Output Source Current ... 500 rnA
Typ
•
High Output Sink Current ... 500 rnA Typ
•
Inputs Are Compatible with Bipolar and
MOS
•
Wide Supply Voltage Range ... 4 V
to 18 V
10UT
1lN
GND
GND
GND
21N
20UT
•
Threshold Voltage Range is Approximately
One-Half VCC
•
Active Pull-Down on Each Input
21N
•
Low Standby Power Dissipation
31N
•
14-Pin NE Power Package
•
(TOP VIEWl
Vee
31N
GND
GND
GND
30UT
Vee
logic symbol t
liN
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
description
The TL376C is a monolithic bipolar three-channel stepper-motor driver. The input signal is inverted through
the device and drives a totem-pole output section. Each output can source or sink up to 500 milliamperes.
The wide supply-voltage range coupled with a threshold voltage level of approximately one-half VCC allows
this device to interface with MOS as well as bipolar outputs. An active-pull-down circuit is included on
each input. In typical operai:ion, a microprocessor supplies a three-phase signal to the device, which then
drives a two-winding stepper-motor.
The TL376C is characterized for operation from OOC to 70°C.
r------,
(,)
..
~
CD
IN
>
~~~I--~.-~71+----------.-----------.--.-----------~--~---vcC
I
I
I
I
I
I
I
I
I
I
I
I
a;
CD
.c
Q.
I
.~
r~
I
115 kll
I
I
.~
C
I
I
TO TWO
OTHER AMPLIFIERS
~
...oca
...::s
«
schematic leach driver)
COMMON
•
d?
I
e-~I~----~--r_--~-J
115 kll
OUT
I
I
18011
I
I
Resistor values shown are nominal.
PRODUCTION DATA do.uments ....tain information
current as of publication date. Products conform to
specifications paf the terms of Texas Instruments
:'::=~~i~at::1~1i ~=::i~n :.r:::::~::.s nat
Co·pyright © 1979, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
5-165
TL376C
THREE·CHANNEL STEPPER·MOTOR DRIVER
absolute maximum ratings over operating free·air temperature (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 22 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Vee
Output voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.9 V to Vee + 1 V
Output current, each amplifier ...... . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . .. 550 mA
Total power dissipation at (or below) 25°e free-air temperature (see Note 2) .......... 2075 mW
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 °e to 150 0 e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260 0 e
NOTES:
1. Voltage values are with respect to the network ground terminal.
2. For operation above 25°C free-air temperature, derate linearly at the rate of 16.6 mW/oC.
recommended operating conditions
MIN
NOM
VCC+ O. B
2
High-level input voltage, VIH
""C
4
Operating free-air temperature, TA
0
PARAMETER
VOL
CD
VOH
High-level output voltage
II
Input current
ICC
Supply current
..
<'
..
c
CD
11
.
V
lB
V
70
°c
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
-6'
!.
V
2
Supply voltage range, VCC
CD
:::r
UNIT
VCC
VCC_ o 2
Low-level input voltage, VIL
..
MAX
low-level output voltage
TEST CONDITIONS
IOL = 500 rnA.
500 rnA,
IOH VI - VCC
VI = 1.B V
Inputs open,
VI - VIL max
Typt
VCC
MAX
1.5
UNIT
V
100
~A
2
rnA
1.5
V
~A
5
Outputs open, VCC - lB V
tTypical values are measured at VCC = 15 V, T A = 25°C.
In
l>
n
r+
C
I»
..
r+
o
In
5-166
MIN
VI - VIH min
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
0.7
·
TL376C
THREE·CHANNEL STEPPER·MOTOR DRIVER
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
INPUT CURRENT
vs
INPUT VOLTAGE
20
VCC ., 18 V
TA _ 250C -1-+---+-+--+-1--1
18
16
161-+--+-~~-4-+-~--l-+-~
>
.'"
1 14~~~1-+--+-+--+-~~~~
I 14
I
E12~±=~~~-Lf=~=F=+~~
~
8
:! 12
'0
:: 10
10~~-41-~-+-+--+-~~~~
"
Sa. 8
;- 8
o
c
16
~ 6
>
4
4
2
2
0
VCC - 18 V
10 - 0
TA - 25°C
18
0
2
4
6 8 10 12 14 16
VI-Input Voltage-V
o
o
18 20
2
4
6
8 10 12 14 16 18
VI-Input Voltage-V
.
...
II)
FIGURE 2
FIGURE 1
o
ca
~
LOW·LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
1.0
>
I
~0.8
-a
..
>
~ 0.6
o
a;
ii
.....
""E'
r t- TA - ooCI
1/
j:-P
...- ::....-"\
U
";::
c
'-
"!
TA
=
50°C
G)
.c
Q.
";::
:.
0.4
!
VCC - 18 V
VI - 18 V
~0.2
~
I
o
o
100
200
300
400
500
10L -Low-Level Output Current-rnA
FIGURE 3
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
5-167
TL376C
THREE·CHANNEL STEPPER·MOTOR DRIVER
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
18.0
1.0
Vee c 18 V
VI - 0
>
I
t
Outputs Open
0.9 Inputs Open
c(
17.8
TA = 25·e
0.8
...- ,/'
T 0.7
~
,/"
E
~ 17.6
;
o
! 0.6
!:i
(J
>-
~ 17.4
/
0.5
/
Q.
r.
I-TA -25·e
/
'"
:f
~
~
~
~17.2
~
L I- TA - o·e
17.0
o
g. 0.4
TA = 50·e
(I)
I 0.3
/
g
/
11" r--
o
>
/
- 0.2
0.1
'"""
-100
-200
-300
-400
-500
IOH-High-Level Output eurrent-mA
o
o
/
2
FIGURE 4
/
/
4
6
8 10 12 14 16 18 20
Vee-Supply Voltage-V
FIGURE 5
...c~.
C;;
i>
n
....
c
I»
....o
C;;
5-168
V
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DAlLAS, TEXAS 75265
I
UDN2841, UDN2845
QUADRUPLE HIGH-CURRENT DARLINGTON DRIVERS
D2507, DECEMBER 1980-REVISED AUGUST 1986
•
For Use with Negative Supplies
•
Current Sink ... UDN2841
•
NE DUAL-iN-LiNE PACKAGE
(TOP ViEW)
4C
lC
liN
Sink or Source Combination ... UDN2845
•
Output Current Capability ... 1.5 A
•
High Output-Voltage Capability ... 50 V
•
Preamplifier for High Current Gain
•
Inputs Compatible with TTL and 5-V CMOS
•
Reliable Monolithic Construction
•
Designed to be Interchangeable with
Sprague UDN2841 and UDN2845
4E
41N
VCC
}lE' 3E, and
HEATSINK
31N
3C
2C
1 E, 3E, and{
HEATSINK
GND
2(N
2E
description
These quadruple Darlington switches are monolithic bipolar devices especially designed for high-current,
high-voltage peripheral driver applications. The devices are designed to offer solutions to interface problems
involving electronic-discharge printers, bipolar and unipolar dc motor drivers, telephone relays, LEDs, PIN
diodes, and other high-current loads operating from negative power supplies.
The UDN2841 is intended for current-sink applications with the load connected to ground and the device
switching the negative supply. The UDN2845 is a sink and source combination for use in bipolar switching
applications where both ends of the load are floating. The UDN2841 and UDN2845 each feature inputs
that are compatible with standard TTL and 5-volt CMOS signals. The p-n-p input transistor serves as a
level translator and the first n-p-n transistor stage is designed to provide sufficient current gain to drive
the output Darlington-connected pair.
Driver channels 2 and 4 have uncommitted collectors and emitters while 1 and 3 have emitters internally
connected to the substrate. For proper operation, the substrate must be connected to the most-negative
supply voltage,
1/1
..