1987_Toshiba_Microprocessors_Volume_1_8bit_MPU_and_MCUs 1987 Toshiba Microprocessors Volume 1 8bit MPU And MCUs
User Manual: 1987_Toshiba_Microprocessors_Volume_1_8bit_MPU_and_MCUs
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TABLE OF CONTENTS
VOL. I
TLCS-Z80 Family (CMOS Z80)
TM PZB4COOAP/AP-B/AP-B
TMPZB4COOAF/AF-B.. .. .. . . ... ... .. .... .... .. ... .. ... .. .. ... . . .. ............. . ... ... .. . .. ..
3
TMPZB4CO1 F ... .. . .. .. .. .. .. ... ............... . .. .. ... .. .. .. ... .. .. ..... . .... .. .... . . . .. ... 73
TMPZB4C1 OAP/TMPZB4C1 OAP-B
TMPZB4C1 OAF/TMPZB4C1 OAF-B ........................................................... 103
TMPZB4C20P, TMPZB4C20AP/AP-B
TMPZB4C20F, TMPZB4C20AF/AF-6 ......................................................... 173
TMPZB4C30P, TMPZB4C30AP/AP-B
TMPZB4C30F, TMPZB4C30AF/AF-B ......................................................... 201
TM PZB4C40,41 ,42 P/TM PZB4C40,41 ,42AP/AP-B
TMPZB4C43F, TMPZB4C43AF/AF-6 ......................................................... 227
TMPZB4C60P ............................................................................... 273
PLCC Package Options for TLCS-ZBO Family.............................. " ... " ............. 811
TLCS-85 Family LSI
TMPBOB5AP/TMPBOB5AP-2." .. " .. " .. " ........ " .. " .......................................... 295
TMPBOB5HP/TMPBOB5AHP-2 .... " ....... " ...... "" ........ "" .. " ..................... "" ... " .. 327
TMPB155P/TMPB155P-2
TMPB15B/TMPB15BP-2 ..... " ...................... "" ...... " .... " ..... " .. " ...... " .. " ...... ". 338
TMPB355P" ............... " ....... " ... ". " . " " . "" .. " ........... " ................... " .... " .. " .. 355
TM PB2C51 AP-2/TM PB2C51 AF-2
TMPB2C51 AP-B/TMPB2C51 AF-8 ................................... " " ....................... 365
TMPB251 AP........... " .... "." .... " ...... "" ... " ... " .. " .. "" .. """ ......... "" .. "" .. "" .. " ... " .. " 381
TMP82C53P-2/F-2 ................................................. "" ....................... 397
TMPB253P-5."" .. "" .. " ....... " ... " .. "" .. "" ... "" .. "."." ..... " ..... "" .. "" .. " .. " ........ " .. " ... 411
TMP82C54P/TMPB2C54P-2 ....... " ... " .......... " ... "."" ................................. " 805
TMPB2C55AP-5/AF-5/AP-2/AF-2/AP-1 O/AF-1 0." ... """""".""""""""."""."""""""""".""" ... """.427
TMP8255AP-5................................... " .. "" .. " ........... " ........... ""."""."" .. ". 447
TMPB2C59AP-2/AF-2 .""."" ....... " .... " ... " .............. " ... " ............................. 463
TMPB259AP ...................................... " ... " ... "." " .. "" ... "" .. " " ... " " .. " ....... " .. 487
TM P82C37 AP-5/ AF-5 .......... " ....... " ........... " ... " ... " ........... " ... " " ...... " ... " " .. " 497
TMPB237AP"" .. """.".".""" .. "" .. "" .. " ... """ .... " .......... " ... " ............................. 527
TMPB2C79P-2/F-2 ... " ... ""."" .. " ... "" .. """ .... " ............................................ 555
TMPB279P-5 .................................... ". " .. " ... " .. " ....... " .... " ... "" .. " " ......... 575
8 Bit Microcontroller TLCS-48 Family
TM P8048AJTM P8035A
TMP8049AJTMP8039A. .......................... (DIP and PLCC) ........................... 597
TMP80C48AP/-6, TMP80C35AP/-6
TMP80C48AF/-6 ............................................................................ 631
TMP80C49AP/-6, TMP80C39AP/-6
TM P80C49AF/-6 ............................................................................ 655
TMP80C50AP/-6, TMP80C40AP/-6
TMP80C50AF/-6 ............................................................................ 679
TMP8048PI, TMP8035PI .......................................................... , ....... .. 703
TMP8049PI-6, TMP8039PI-6 ....... , ......... , ................. " ........................... 733
TMP8243P/TMP8243PI ... , ........ , ...... , ........... , ........................... , ......... 763
TMP82C43P ................................................................................ 773
PLCC Package Option for TLCS-48 CMOS Family ........................................... 818
Application Specific Standard Products
TMPZ84C011 AF/TMPZ84C011 AF-6 ........................................ , .. , .......... .. 783
TMPZ84C013AT/TMPZ84C013AT-6......................................................... 787
TMPZ84C015AF/TM PZ84C015AF-6 ........................................................ 795
Volume #1 Errata Sheet .......................................................... .... 821
ii
-
1 -
2 "
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ AP-6/AP-8
TMPZ84COOAF/AF-6
TECHNICAL DATA
TMPZ84~00AP,
1.
TMPZ84COOAP-6, TMPZ84COOAP-8, TMPZ84COOAF, TMPZ84COOAF-6
TLCS-Z80 CPU: 8-BIT MICROPROCESSOR
GENERAL DESCRIPTION AND FEATURES
THE TMP Z84 COOA (from here on re ferred to as Z80 or CPU) is CMOS ver sion of
Z80 CPU which provides low power operation and high performance.
Built into the CMOS Z80 microprocessor are all bus control, memory
control, and timing signals in addition to eight general purpose 16-,bit
registers and an arithmetic-and-logic unit.
The CMOS Z80 is fabricated
using Toshiba's CMOS Silicon Gate Technology.
1.1
o
o
o
o
o
o
o
o
o
o
o
o
o
o
FEATURES
Software Compatible with the Zilog Z80 CPU
DC to 4MHz Operation (TMPZ84COOAP/AF)
DC to 6MHz Operation (TMPZ84COOAP-6/AF-6)
DC to 8MHz Operation (TMPZ84COOAP-8)
Single SV Power Supply : SV + 10%
Powerful Set of 158 InstructIons
Duplicate Sets of Both General-purpose and Flag Registers
Two Interrupt Inputs
- Non-maskable Interrupt (MMi)
- 3 Modes of Maskable Interrupt (INT)
o 8080 Compatible (Non-Z80 Peripheral Device) (Mode 0)
o Restart (Mode 1)
o Z80 Family Peripheral with Daisy Chain (Model 2)
Low Power Consumption
9mA Typ. @4MHz@5V (TMPZ84COOAP/AF)
lSmA Typ. @6MHz@SV (TMPZ84COOAP-6/AF-6)
20mA Typ. @8MHz@5V (TMP Z84 COOAP -8)
Less than 10uA @SV (Stand-by)
Extended Operating Temperature
-40'C to 8S'C
Two Indexed Registers
10 Addressing Modes
On-chip Dynamic Memory Refresh Counter
40 pin DIP package, 44 pin Mini Flat package.
Z80 is a trademark of Zilog Inc.
-
3
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ AP-6/ AP-8
TMPZ84COOAF/AF-6
TECHNICAL DATA
2.
2.1
PIN CONNECTIONS AND PIN FUNCTIONS
PIN CONNECTIONS (TOP VIEW)
All
Ala
AlZ
A9
Al3
Al4
A8
Al5
A6
A5
A7
eLK
D4
A4
D3
A3
D5
A2
D6
Al
AO
VSS
RFSH
MI
Vee
D2
D7
DO
Dl
RESET
BUSREQ,
INT
NMI
HALT
~
IORQ,
Fig. 2.1
DIP Pin Connections
INT
DI
DO
RFSH
vaS(O"D)
D7
D2
AD
*ICV
Al
VOC(5V)
D6
.
(Note)
A2
D5
A3
D3
D.
A5
OLK
Connect Pin 39 and Pin 17 externally.
ICV must be used at open condition or connected with VCC.
*
Fig. 2.2
MFP Pin Connections
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4 -
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ AP-6/ Ap·8
TMPZ84COOAF/ AF-6
TECHNICAL DATA
2.2
PIN NAMES AND PIN DESCRIPTION
(1)
AO-A15. Address BUB (output, active High, 3-state)
AO-Al5 form a 16-bit addun bUB. The Addreas Bus provides the address
for memory data bus exchanges (up to 64K byteB) and for I/O device
exchanges.
(2)
BUSACK. Bus Acknowledge (output, active Low)
BUB Acknowledge indicates to the requesting device that the CPU addreas
bus, data bus, and control signals MREQ, IORQ. RD, and WR have entered
their high impedance statea. The external circuitry can now control these
lines.
(3)
BUSREQ. Bus Request (input, active Low)
Bus Request has a higher priority than NMI and is always recognized at the
end of the current machine cycle.
BUSREQ forces the CPU address bus.
data, and control aignals MREQ, IORQ, RD, and WR to go to a high-impedance
state 10 that other devices can control these lines. BUSREQ is normally
wire-ORed and requires an external pullup for these applications.
Extended BUSREQ periods due to extensive DMA operations can prevent the
CPU from properly refreshing dynamic RAMs.
(4)
DO-D7. nata Bus (input/output, active High, 3-.tate)
DO-D7 conatitute an 8-bit bidirectional data bus, u.ed for data exchange
with memory and I/O.
(5)
HALT. Halt State (output, active Low)
HALT indicates that the CPU has executed a Hal instruction and is awaiting
either a non-maskable or a maskable interrupt (with the mask enabled)
before operation can resume.
While halted, the CPU executes NOPs to
maintain memory refresh.
(6)
iNT. Interrupt Request (input, active Low)
Interrupt Request is generated by Ilo devices. The CPU honors a request
at the end of the current instruction if the internal software-controlled
interrupt enable flip-flop (IFF) is enabled.
INT is normally wire-ORed
and require. an external pull-up for these applications.
(7)
IORQ. Input/Output Request (output, active Low, 3-state)
IORQ indicates that the lower half of the address bus holds a valid I/O
addrea s for an I/O read or wri te operat ion.
IORQ is a1 so generated
concurrently with Ml during an interrupt acknowledge cycle to indicate
that an interrupt response vector can be placed on the data bus.
(s)
Mi. Machine Cycle One (output, active Low)
MI, together with MREQ. indicatea that the current machine cycle it the
opcode fetch cycle of an instruction execution.
Note that during
execution of 2-byte op-codes alway. begin with CIH, DDH, lDH or FDR. Ml
,,.., OCCUri with IORQ to indicate an interrupt ackt!owled&e cycle.
{9}
MREQ. Memory Request (output, active Low, 3-.tate)
MREQ indicatee that the addu .. bu. holdl a valid addu .. for a lIIIemor1
read or memory write operation.
-
5 -
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/AP-6/AP-8
TMPZ84COOAF/AF-6
TECHNICAL DATA
(10) HMI. Non-Maskable Interrupt (input, active Low)
NMl has higher priority than INT.
NMI is always recognized at the end of
the current instruction, independent of the status of the interrupt enable
flip-flop, and automatically forces the CPU to restart at location 0066H.
(11) RD. Memory Read (output, active Low, 3-state)
RD indicates that the CPU wants to read data from memory or an I/O device.
The addressed I/O device or memory should use
onto the CPU data bus.
this
signal
to
gate
data
(12) RESET.
Reset (input, active Low)
RESET initializes the CPU as follows:
it resets the interrupt enable
flip-flop, clears the PC and Registers I and R, and sets the interrupt
status to Mode o.
During reset time, the address and data bus go to a
high-impedance state, and all control output signals go to the inactive
state. Note that RESET must be active for a minimum of three full clock
cycles before the reset operation is complete.
(13) RFSH. Refresh (output, active Low)
RFSH together with MREQ, indicates tha t the lower seven
system's address bus can be used as a refresh address to
dynamic memories.
bits of the
the system's
(14) WAIT.
Wait (input, active Low)
WAIT indicates to the CPU that the addressed memory or I/O devices are not
ready for a data transfer.
The CPU continues to enter a Wait state as
long as this signal is active. Extended WAIT periods can prevent the CPU
from refreshing dynamic memory properly.
(15) WR.
Memory Write (output, active Low, 3-state)
WR indicates that the CPU data bus holds valid data to be stored at
addressed memory or I/O location.
the
(16) CLK. clock (input)
Single phase system clock input. When CLK is a DC state (either a high or
low level), CPU stops its operation and maintains resisters and control
signals.
(17) VCC.
Power Supply
+SV
(18) VSS. Power Supply
Ground refernece (OV).
-
6 -
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ AP-6/ AP.8
TMPZ84COOAF/AF-6
TECHNICAL DATA
3.
3.1
FUNCTIONAL DESCRIPTION
BLOCK DIAGRAM
INSTRUCTION
DECODER
IN ST
IJ'--~==-"'"
ALU
REG.
VCC-
VssCLOCK-
CPU
TIMING
CONTROL
SYSTEME
AND CPU
CONTROL
OUTPUTS
CPU
CONTROL
INPUTS
Fig. 3.1
3.2
CPU
TIMING
BIT
BLOCK DIAGRAM
CPU REGISTERS
The internal registers contain 208 bits of read/write memory that are
accessible to the programmer.
These registers include two sets of six
general-purpose registers which may be used individually as either 8-bit
r-egisters or as l6-bit register pairs.
In addition, there arfe two sets
of accumulator and flag registers.
A group of "Exchange" instructions
makes either set of main or alternate registers accessbile to the
programmer.
The alternate set allows operation in foregound-background
mode or it may be reserved for very fast interrupt response.
-
7 -
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ AP-6/ AP-8
TMPZ84COOAF/ AF-6
TECHNICAL DATA
The Z80
~lso
contains a Stack Pointer, Program Counter, two index
registers, a Refresh regis ter (counter), and an Interrup t register.
Figure 3 shows the registers within the Z80 CPU.
Table 1 provides further information on these resisters.
MAIN RED 1Sl'ER SEI'
ALTERNA1E REDlSTER SEl'
AlXUMUlATCR
F
FUlO REDIsrER
A' ACaJMUlATCR
F' FlAG REDISTER
B GENERAL RJRR:SE
C
GUIERAL l'tlRl alE
B' GENERAL RJRRl3E
c'
D Ol!l/J!RAL PlRPOSE
E GENERAL RJRRlSE
rJ GlllffiAL RIRRlSE
E' GENERAL PURRlSE
H GENERAL PlRPOSE
L
H' GENmAL PI.RRJSE
L' GENERAL RlRRlSE
A
G~L
PlRREE
GENERAL PI.lRFalE
}
GENERAl,
PURPOSE
REGISTERS
_ B B I T S _ __
INrERRUPT FLIP. FLOPS srATlE
-------16BITS-------
l
~
IX INDEX RED IsrER
IY INJEI: REllISl'ER
SPECIAL
PURPOSE
REGISTERS
Sf' STACK JOINTER
}C
I
1 = INTERRUPTS
ElWllED
INTERRUPT MODE FLIP. FLOP
ffiOORAM OJUNTER
I INTERRJPJ' VEI::'Im
0= INTERRUPTS
DISABliD
R MEMORY REffiESH
-BBITS-
o
o
1
1
FIGURE 3. CPU REGISTERS
-
8 -
0
1
0
1
IN'I'ERR!JPI' MOIF.O
NaJ' USF.D
INTERRllPl' Mornl
INT~WJPI Morn2
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ AP-6/ AP-8
TMPZ84COOAF/ AF·6
TECHNICAL DATA
Remarks
Size (Bits)
Register
A, A'
Accumulator
8
Stores an operand or the results of
an operation.
F, F'
Flags
8
See Instruction Set.
B, B I
General Purpose
8
Can be used separately or as a l6-bit
register with C.
C, C'
General Purpose
8
See B, above.
D, D'
General Purpose
8
Can be used separately or as a l6-bit
register with E.
E, E'
General Purpose
8
See D, above.
H, H'
General Purpose
8
Can be used separately or as a l6-bit
register with L.
L, L'
General Purpose
8
See H, above.
Note: The (B ,C) , (D,E) , and (H ,L) sets
are combined as follows:
B - High byte
C - Low byte
E - Low byte
D - High byte
H - High byte
L - Low byte
I
Interrupt
Register
8
Stores upper eight bits of memory address for vectored interrupt processing.
R
Refresh Register
8
Provides user transparent dynamic
memory refresh. Automatically incremented and placed on the address bus
during each instruction fetch cycle.,
IX
Index Register
16
Used for indexed addressing.
IY
Index Register
16
Same as IX, above.
SP
Stack Pointer
16
Stores addresses or data temporarily.
See Push or Pop in instruction set.
PC
Program Coun ter
16
Holds address of next instruction.
IFFI-IFF2
Interrupt Enable
Flip-Flops
Set or reset to indicate interrupt
status (see Figure 3) .
IMFa-IMFb
Interrupt Mode
Flip-Flops
Reflect Interrupt mode (see Figure 3).
TABLE 1. ZSO CPU REGI STE RS
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9 -
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAPIAP.61AP.8
TMPZ84COOAF/AF·6
TECHNICAL DATA
(1)
Special Purpose Registers
Program Counter (PC)
The program counter is 16-bit counter and holds the 16-bit address of
the current instruction being fetched from memory.
The PC is automatically
incremented after its contents have been transferred to the address lines.
When a program jump occurs the new valve is automatically placed in the PC,
overriding the incrementer.
Stack Pointer (SP)
The stack pointer holds the 16-bit address of the current top of a stack
located anywhere in external system RAM memory.
organized as a last-in first-out (LIFO) file.
The external stack memory is
Data can be pushed onto the
stack from specific CPU registers or popped off of the stack into specific
CPU registers through the execution of PUSH and POP instructions.
popped from the stack is always the last data pushed onto it.
The data
The stack
allows simple implementation of ml;ltiple level interrupts, unlimited subroutine
nesting and simplification of many types of data manipulation.
Two Index Registers (IX & IY)
The two independent index registers hold a l6-bit base address that is
used in indexed addressing modes.
In this mode, an index register is used
as a base to point to a region in memory from which data is to be stored or
retrieved.
An additional byte is included in indexed instructions to specify
a displacement from this base.
This displacement is specified as a two's
-
10-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ AP-6/ AP-8
TMPZ84COOAF/AF-6
TECHNICAL DATA
complement signed integer.
This mode of addressing greatly simplifies many
types of programs, especially where tables of data are used.
Interrupt Page Address Register (I)
The Z80CPU can be operated in a mode where an indirect call to any
memory location can be achieved in response to an interrupt.
The I Register
is used for this purpose to store the high order 8-bits of the indirect address
while the interrupting device provides the lower 8-bits of the address.
This feature allows interrup routines to be dynamically located anywhere in
memory with absolute minimal access time to the routine.
Memory Refresh Register (R)
The Z80CPU contains a memory refresh counter to enable dynamic memories
to be used with the same ease as static memories.
Seven bits of this 8-bit
register are automatically incremented after each instruction fetch.
The
eighth bit will remain as programmed as the result of an LD R, A instruction.
The data in the refresh counter is sent out on the lower portion of the
address bus along with a refresh control signal while the CPU is decoding
and executing the fetched instruction.
This mode of refresh is totally
transparent to the programmer and does not slow down the CPU operation.
The programmer can load the R register f.or testing purposes, but this register
is normally not used by the programmer.
During refresh, the contents of the
I register are placed on the upper 8 bits of the address bus.
-
11 -
TOSHIBA
(2)
INTEGRATED CIRCUIT
TMPZ84COOAP/ AP-6/ AP-8
TMPZ84COOAF/ AF·6
TECHNICAL DATA
Accumulator and Flag Registers
The CPU includes two independent 8-bit accumulators and associated 8-bit
flag registers.
The accumulator holds the results of 8-bit arithmetic or
logical operations while the flag register indicates specific conditions for
8 or l6-bit operations, such as indicating whether or not the result of an
operation is equal to zero.
The programmer selects the accumulator and flag
pair that he wishes to work with a single exchange instruction so that he may
easily work with either pair.
(3)
General Purpose Registers
There are two matched sets of general purpose registers, each set
containing six 8-bit registers that may be used individually as 8-bit registerE
or as 16-bit register pairs by the programmer.
One set is called BC, DE and
HL while the complementary set is called BC', DE' and HL'.
~he
At anyone time
programmer can select either set of registers to work with through a
single exchange command for the entire set.
response is required, one set
0:
In systems where fast interrupt
general purpose registers and an accumulator-
flag register may be reserved for handling this very fast routine.
Only a
simple exchange commands need be exe"cuted to go between the routines.
This
greatly reduces interrupt service time by eliminating the requirement for
saving and retrieving register contents in the external stack during interrupt
or subrou~ine processing.
These general purpose registers are used for a wide
• range of applications by the programmer.
They also simplify programming,
especially in ROM based systems where little external read/write memory is
available.
-12-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ Ap·6/ Ap·8
TMPZ84COOAF/ AF·6
TECHNICAL DATA
ARITHMETIC & lOGIC UNIT (AlU)
The 8-bit arithmetic and logical instructions of the CPU are executed
in the ALU.
Internally the ALU communicates with the registers and the
external data bus on the internal data bus.
The type of functions performed by the ALU include:
Add
Left or right shifts or rotates (arithmetic
and logical)
Subtract
Increment
Logical AND
Decrement
Logical OR
Set bit
Logical Exclusive OR
Reset bit
Compare
Test bit
INSTRUCTION REGISTER AND CPU CONTROL
As each instruction is fetched from memory, it is placed in the
instruction register and decoded.
The control section performs this
function and then generates and supplies all of the control signals
necessary to read or write data from or to the registers, controls the ALU
and provides all required external control signals.
-
13-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/AP-6/ AP-&
TMPZ84COOAF/AF-6
TECHNICAL DATA
FLAGS
Each of the two
zao
CPU Flag registers contains six bits of information
which are set or reset by various CPU instructions.
Four of these bits are
testable; that is, they are used as conditions for jump, call or return instructions.
1)
The four testable flag bits are:
Carry Flag (C) - This flag is the carry from the highest order bit
of the accumulator.
For example, the carry flag will be set during
an add instruction where a carry from the highest bit of the accumulator is generated.
This flag is also set if a borrow is generated
during a subtraction instruction.
The shift and rotate instructions
also affect this bit.
2)
Zero Flag (Z) - This flag is set if the result of the operation loaded a zero into the accumulator.
3)
Otherwise it is rese"t.
Sign Flag (S) - This flag is intended to be used with signed numbers
and it is set if the result of the operation was negative.
Since
bit 7 (KSB) represents the sign of the number (A negative number has
a 1 in 'bit 7), this flag stores the state of bit 7 in the accumulator.
4)
Parity/Overflow Flag (P/V) - This dual purpose flag indicates the
parity of the result in the accumulator when logical
~perations
are
performed (such as AND A, B) and it represents overflow when signed
two's complement arithmetic operations are perfomed.
-14 -
The
zao
overflow
TOSHIBA
INTEGRATED CIRCUIT
TMPZ84COOAP/ AP-6/ AP-8
TMPZ84COOAF/ AF-6
TECHNICAL DATA
flag indicates that the two's complement number in the accumulator
is in error since it has exceeded the maximum possible (+127) or is
less than the minimum possible (-128) number that can be represented
two's complement notation.
There are also two non-testable bits in the flag register.
Both of these are
used for BCD arithmetic.
I}
Half carry (H) = This is the BCD carry or borrow result from the
least significant four bits of operation.
imal
When using the DAA (Dec-
Adjust Instruction) this flag is used to correct the result of
a previous packed decimal add or subtract.
2}
Add/Subtract Flag (N) - Since the agorithim for correcting BCD operations is different
for addition or subtraction, this flag is used
to specify what type of instruction was executed last so that the
DAA operation will be correct for either addition or subtraction.
The Flag register can be accessed by the programmer and its format is as follows:
D7 D6 D5 D4 D3 D2 Dl DO
I S I z I X I H I X IP/V IN I C I
X means flag is indeterminate.
-
15-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAPIAP-61AP-8
TMPZ84COOAF/AF-&
TECHNICAL DATA
The Table 2 lists how each flag is affected by various CPU instructions.
, , ·indicates
· 'X'
· 'R'
· '5'
that the instruction does not change the flag.
means that the flag goes to an indeterminate state.
means that it is reset.
means that it is set.
'0' indicates that it is set or reset according to the previous discussion.
Note)
Any instruction not appearing in the table 2 does not affect any
of the flags.
Table 2 includes a few special cases that must be described for clarity.
Notice that the block search instruction sets the Z flag if the last compare
operation indicated a match between the source and the accumulator data.
Also, the parity flag is set if the byte counter (register pair BC) is not
equal to zero.
This same use of the parity flag is made with the block move
instructions.
Another special case is during block input or output instruc-
tions, here the Z flag is used to indicate the state of register B which is
used as a byte counter.
Notice that when the I/O block transfer is complete,
the zero flag will be reset to a zero (i.e. B=O) while in the case of a block
move command the parity flag is reset when the operation is complete.
A
final case is when the refresh or I register is loaded into the accumulator,
the interrupt enable flip flop is loaded into the parity flag so that the
complete state of the CPU can be saved at any time.
-
16-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ AP-6/ Ap·8
TMPZ84COOAF/ AF·6
TECHNICAL DATA
p7 D6 D5p4p3 D2
t!/
H
DI DO
Instruction
S Z
V NC
Comments
ADD A,s;ADC A,s
o
0
x
0
x
V R
0
8-bit add or add with carry
SUB:s; SBC A,s; CP s; NEG
o
0
x
0
x
V S
0
8-bit subtract, subtract with
carry, compare and negate
accumulator
AND s
o
0
x S x
P
OR s; XOR s
o
0
x R x
P
INC s
o
0
x
0
x
V
R -
8-bit increment
DEC s
o
0
x
0
x
V
S -
8-bit decrement
ADD DD, SS
- - x x x
R 0
16-bit add
ADC HL, SS
o
0
x x x
V
R 0
16-bit add with carry
SBC HL, SS
o
0
x x x
V
S
0
16-bit subtract with carry
RLA; RLCA; RRA; RRCA
-
- x
R
0
Rotate accumulator
RL s; RLC s; RR s; RRC s;
o
0
x R x
P
R
0
Rotate and shift locations
RLD; RRD
o
0
x R x
P
R-
Rotate digit left and right
DAA
o 0 x 0 x
P
-
Decimal adjust accumulator
CPL
- - x S x
s -
Complement accumulator
SCF
- - x Rx
R S
Set carry
CCF
- - x x x
R
Complement carry
IN r, (C)
o 0 x R x
P
INI; IND; OUTI; OUTD
x
x x x
x
x S x x x
x
LDI! LDD
x x x R x
o
LDIR; LDDR
x x x R x
R
: : } Logical operations
Rx
SLA s; SRA s; SRL s
r INDR;
INIR
OTIR; OTDR
0
0
0
R-
::}
-17-
:~}
Input register indirect
Block input and output
Z=O if BjO otherwise Z=l
Block transfer instructions
P/V=l if BCtO, otherwise p/V=O
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ AP-6/AP-8
TMPZ84COOAF/AF-6
TECHNICAL DATA
07 06 O.~ 04 O~ 02 D1 Oc
Instruction
S Z
p/
V NC
H
CPI; CPIR; CPO; CPOR
o
0
x
LO A, I', LO A, R
o
0
x R x IFF R -
The content of the interrupt
enable flip-flop (IFF) is
copied into the P/V flag.
BIT b, s
x
0
x S x
The state of bit b of
location s is copied into the
Z flag
TABLE 2.
0
x
Comments
0
x
S -
R -
Block search instructions
Z=l i f A= (HL) , otherwise
Z=O
P/V=l i f BC;!O, otherwise
p/V=O
SUMMARY OF FLAG OPERATION
The following notation is used in this table:
OPERATION
SYMBOL
C
Carry/link flag. C=l if the operation produced a carry from
the MSB of the operand or result.
z
Zero flag.
Z=l if the result of the operation is zero.
s
Sign flag.
S=l if the MSB of the result is one.
p/V
Parity or overflow flag. Parity (P) and overflow (V) share the
same flag. Logical operations affect this flag with the parity
of the result while arithmetic operations affect this flag with
the overflow of the result.
If P/V holds parity. P/V=l if the result of the operation is
even, p/V=O if result is odd. If P/V holds overflow, P/V=l if
the result of the operation produced an overflow.
H
Half-carry flag. H=l if the add or subtract operation produced
a carry into or borrow from bit 4 of the accumulator.
-
18-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
OPERATION
SYMBOL
N
TMPZ84COOAP/ AP-6/ AP-8
TMPZ84COOAF/AF-6
Add/Subtract flag. N=l if the previous operation was a subtract.
Hand N flags are used in conjunction with the decimal adjust
instruction (DAA) to properly correct the result into packed
BCD format following addition or subtraction using operands with
packed BCD format.
The flag is affected according to the result of the operation.
The flag is unchanged by the operation.
R
The flag is reset by the operation.
S
The flag is set by the operation.
o
The flag is affected according to the result of the operation.
x
The flag is a "don't care".
v
p/V flag affected according to the overflow result of the
operation.
p
P/V flag affected according to the parity result of the operation.
r
Anyone of the CPU registers A, B, C, D, E, H, L.
s
Any 8-bit location for all the addressing modes allowed for the
particular instruction.
ss
Any 16-bit location for all the addressing modes allowed for
that instruction.
I
I resister
R
Refresh counter.
n
8-bit value in range <0, 255>
nn
16-bit value in range <0, 65535>
-19 -
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/Ap·6/Ap·8
TMPZ84COOAF/ AF·6
TECHNICAL DATA
INTERRUPT
The CPU accepts two interrupt input signals: NMI and INT.
a non-maskable interrupt and has the highest priority.
The
~~II
is
INT is a lower
priority interrupt since it requires that interrupts be enabled in software
in order to operate.
Either
~!I
or INT can be connected to multiple
peripheral devices in a wired-OR configuration.
The ZSO has a single response mode for interrupt service for the
non-maskable interrupt.
The maskable interrupt, INT, has three programmable
response modes available.
These are:
Mode 0 -- compatible with the S080 microprocessor.
Mode 1 -- Peripheral Interrupt service, for use with non-SDSO/ZSD systems.
Mode 2 -- a vectored interrup"t scheme, usually daisy-chained, for use with
ZSO family and compatible peripheral devices.
Both the INT and
l~I
inputs are sampled by the CPU on the rising edge
of CLK in the last T state of the last Machine (M) cycle of any instruction.
However. if BUSRQ is active at the same time, it will be processed before any
interrupts.
Figure 4 illustrates the ZSD interrupt service sequence.
-
20-
INTEGRATED CIRCU IT
TOSHIBA
TMPZ84COOAP/AP.6/AP.8
TMPZ84COOAF/AF-6
TECHNICAL DATA
NOTE (1)
NO
(2)
INT and NHI are always
acted on at the end of
an instruction.
BUSRQ is acted on at
the end
cycle.
YES
~f
a machine
(3)
While the CPU is in the
DMA MODE, it will not
res~d to~tive inputs
on INT or N}!I.
(4)
These three inputs are
acted on in the following
order of priority.
1) BUSRQ
highest
2) NHI
3) INT
YES
NO
SET NMI F/F
1----_1_-_ _-'
SET INT. F/F
FIGURE 4.
Z80 CPU INTERRUPT SEQUENCE
-
21 -
lowest
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ AP.6/ AP.8
TMPZ84COOAF/AF-6
TECHNICAL DATA
(1)
Non-Maskable Interrupt (NMI)
The non-maskable interrupt cannot be disabled by program control
and therefore will be accepted at all times by the CPU.
NMI is usually
reserved for servicing only the highest priority type interrupts, such
as that for orderly shutdown after power failure has been detected.
After recognition of the NMI signal (providing BUSREQ is not active),
the CPU jumps to restart location 0066H.
Normally, software starting
at this address contains the interrupt service routine.
(2)
Maskable Interrupt (INT)
Regardless of the interrupt mode set by the user, the Z80 CPU
response to a maskable interrupt input follows a common timing cycle.
After the interrupt has been
detect~,d
by the CPU (provided that
interrupts are enabled and BUSREQ is not active) a special interrupt
processing cycle begins.
This is a special fetch (Ml) cycle in which
IORQ becomes active rather than MREQ, as in a normal HI cycle.
addition,
In
this special HI cycle is automatically extended by two WAIT
states, to allow for the time required to acknowledge the interrupt
request and to place the interrupt vector on the bus.
Mode 0 Interrupt Operation
This mode is compatible with the 8080 microprocessor interrupt
service procedures.
The interrupting device places an instruction on
the data bus.
-
22-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ AP-6/ AP-8
TMPZ84COOAf/Af-6
TECHNICAL DATA
This is normally a Restart Instruction, which will initiate an
unconditional jump to the selected one of eight restart locations in
page zero of memory.
Mode I Interrupt Operation
Mode 1 operation is very similar to that for the NMI.
The
principal difference is that the Mode 1 interrupt has a vector address
of 0038H only.
Mode 2 Interrupt Operation
This interrupt mode has been designed to utilize most effectively
the capabilities of the Z80 microprocessor and its associated peripheral
family.
The interrupting peripheral device selects the starting address
of the interrupt service routine.
It does this by placing an 8-bit
address vector on the data bus during the interrupt acknolwedge cycle.
The high-order byte of the interrupt service routine address is supplied
by the I (Interrupt) register.
This flexibility in selecting the
interrupt service routine address allows the peripheral device to use
several different types of service routines.
These routines may be located at any available location in memory.
Since
the interrupting device supplies the low-order byte of the 2-byte vector,
bit 0 (Ao) must be a zero.
Figure 5 illustrates the vector processing sequence.
-
23-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ AP-6/ AP-8
TMPZ84COOAF/ AF-6
TECHNICAL DATA
MEMORY
Z80 CPU
r---1I--"::®~-{
IDW ORIER } VECTOR TABLE
PC
IREG
INrERRLIPT
SERVICE
ROUTINE
NOTES:
1)
Interrupt vector generated by peripheral is read by CPU during
interrupt acknowledge cycle.
2)
Vector combined with I register contents form l6-bit memory address
pointing to vector table.
3)
Two bytes are read sequentially from vector table.
are read into PC.
4)
Processor control is transferred to interrupt service routine and
execution continues.
FIGURE 5.
VECTOR PROCESSING SEQUENCE
-
24-
These 2 bytes
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ AP.6/ AP.8
TMPZ84COOAF/ AF-6
TECHNICAL DATA
(3)
Interrupt Pt ioriLy (Daisy Chaining ,ll1d
N('stl~d
Interrupts).
The interrupt priority of each peripLeral devl(e is determined by its
physical InCdt iun within a d,l1sy-chail! cllnfiguration.
Eacli d,'vi( e in the
chain has an int, rrupt enable input lim' (rEI) an,\ an interrupt enable l)utput
line (r[o), which '_s fed to the next lower priority device.
The first device
in the daisy chain has its lEI Input hardwired to a High level.
1~e
first
device has highest priority, while each succeeding device has a corJesponding
lower pdority.
This arra'lgement permits thfc CPU to select the highest
priority interrupt from sever31 simultaneously interrupting peripherals.
The interruptl,lg device disables its TEO litle to tIl(' next l()wer priori ty
peripheral until ir has been serviced.
After servicing. its lEO line is
raised, allowing lower priority peripherals to dE'mand interrupt sE'rvicing.
The Z80 CPU will nest (queue) any pend1ng interrupts or interrupts
received while a selected peripheral is being serviced.
(4)
Interrupt Enable/DisablE'
Op~ration.
In the Z80-CPU there is an enable flip flop (called IFF) that is set or
reset by the progranuner using the Enable Interrupt (EI) and Disable Interrupt
(DI) instructions.
When the IFF is reset, an interrupt (except NMI) cannot
be accepted by the CPU.
-
25-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/AP-6/AH
TM PZ84 COOAF/AF-6
TECHNICAL DATA
-Actually, there are two enable flip flops, called IFFl and IFF2.
Actually disables interrupts
from being accepted.
Temporary storage location
for IFFl.
A reset to the CPU will force both IFFl and·IFF2 to the reset state so
that interrupts are disabled •• They can then be enabled by an EI instruction
at any time by the programmer.
When an EI instruction is executed, any
pending interrupt request will not be accepted until after the instruction
following EI has been executed.
This single instruction delay is necessary
for cases when the following instruction is a return instruction and interrupts must not be allowed until the return has been completed.
and IFF2 can be enabled by execution of the EI instruction.
Both IFFI
When an
interrupt is accepted by the CPU, both IFFl and 1FF2 are automatically reset,
inhibiting further interrupts until a new E1 instruction is executed.
Note that for all of the previous cases, IFFl and IFF2 are always equal.
The purpose of IFF2 is to save the status of IFFl when a non-maskable
interrupt occurs.
When a non-maskable interrupt is accepted, IFFl is reset
to prevent further interrupts until reenable by the programmer.
Thus, after
a non-maskable interrupt has been accepted maskable interrupts are disabled
but the previous state of IFFl has been saved so that the complete state of
the CPU just prior to the non-maskable interrupt can be restored at any time.
When a Load Register A with Register I (LD A, I) instruction or a Load Register
A with Register R (LD A, R) instruction is executed, the state of IFF2 is
-
26-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84COOAP/ AP-6/ AP-8
TMPZ84COOAF/AF-6
copied into the parity flag where it can be tested or stored.
A second method of restoring the status of IFF! is thru the executjon
of a Return From Non-Maskable Interrupt (RETN) instruction.
Since this
instruction indicates that the non maskable interrupt service routine is
complete, the contents of IFF2 are now copied back into IFF!, so that the
status of IFF! just prior to the acceptance of the non-maskable interrupt
will be restored automatically.
Operation of the two flip-flops is described in Table
-
27-
3.
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/AP-6/AP-8
TMPZ84COOAF/AF·6
TECHNICAL DATA
IFF!
IFF2
Conunents
CPU Reset
0
0
Maskable interrupt
INT disabled
DI instruction
execution
0
0
Maskable interrupt
INT disabled
EI instruction
execution
1
1
Maskable interrupt
INT enabled
Action
LD A,I instruction
execution
lFF2 ..... Parity flag
LD A,R instruction
execution
IFF2 ..... Parity flag
Accept NMI
0
RETN instruction
execution
IFF!
IFF2
Accept INT
0
IFF! ..... IFF2
(Maskable interrupt
INT disabled)
IFF2 ..... IFF! at
completion of an
service routine.
0
RET I
Note)
"_" indicates no change.
TABLE 3.
STATE OF FLIP-FLOPS
.."
-
28-
NMI
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ Ap·6/ AP-8
TMPZ84COOAF/AF·6
TECHNICAL DATA
CPU TIMING
The
zao
CPU executes instructions by proceeding through a
sequence of operations.
spec~fic
These include:
Memory read or write
I/O device read or write
Interrupt acknowledge
All instructions are merely a series of these basic operations.
Each
of these basic operations can take from three to six clock periods to complete
or they can be lengthened to synchronize the CPU to the speed of external
devices.
The basic clock periods are referred to as T states and the basic
operations are referred to as M (for machine) cycles.
Figure 6 illustrates
how a typical instruction will be merely a series of specific M and T cycles.
Notice that this instruction consists of three machine cycles (Ml, M2 and M3).
The first machine cycle of any instruction is a fetch cycle which is four,
five or six T states long (unless lengthened by the wait signal).
The fetch
cycle (Ml) is used to fetch the OP code of the next instruction to be executed.
Subsequent machine cycles move data between the CPU and memory or 110 devices
and they may have anywhere from three to five T cycles (again they may be
lengthened by wait states to synchronize the external devices to' the CPU).
The following paragraphs describe the timing which occurs within any of the
basic machine cycles.
-
29-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/AP-6/AP-8
TMPZ84COOAF/AF-6
TeCHNICAL DATA
TState
II
CLK
MI
(OP Cexle Fetch)
1!2
(Memory Read)
M:3
(Memory Write)
Instruction Cycle
FIGURE 6.
BASIC CPU TIMING EXAMPLE
All CPU timing can be broken down into some very simple timing
diagrams as shown in Figure 7 through 14.
These diagrams show the following
basic operations with and without wait states (wait states are added to
synchronize the CPU to slow memory or I/O devices).
Fig.
7
Instruction OP code fetch (Ml cycle)
Fig.
S
Memory data read or write cycles
Fig.
9
I/O read or write cycles
Fig. 10
Bus Request/Acknowledge Cycle
Fig. 11
Interrupt Request/Acknowledge Cycle
Fig. 12
Non maskable Interrupt Request/Acknowledge Cycle
Fig. 13
Exit from a HALT instruction
Fig. 14
Reset Cycle
-
30-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/AP-6/AP-8
TMPZ84COOAF/ AF-6
TECHNICAL DATA
(1)
Instruction fetch
Figure 7-0 shows the timing during an Ml cycle (OP code fetch).
Notice
that the PC is placed on the address bus at the beginning of the MI cycle.
halt clock time later the MREQ signal goes cctive.
One
At this time the address
to the memory has had time to stabilize so that the falling edge of MREQ can
be used directly as a chip enable clock to dynamic memories.
The RD line
also goes active to indicate that the memory read data should be enabled onto
the CPU data bus.
The CPU samples the data from the memory on the data bus
with the rising edge of the clock of state T3 and this same edge is used by
the CPU to turn off the RD and MREQ signals.
Thus the data has already been
sampled by the CPU before the RD signal becomes inactive.
Clock state T3 and
T4 of a fetch cycle are used to refresh dynamic memories.
(The CPU uses this
time to decode and execute the fetched instruction so that no other operation
could be performed at this time).
During T3 and T4 the lower 7-bits of the
address bus contain a memory refresh address and, the RFSH signal becomes
active to indicate that a refresh read of all dynamic memories should be
accomplished.
Notice that a RD signal is not generated during refresh time
to prevent data from different memory segments from being gated onto the data
bus.
The MREQ signal during refresh time should be used to perform a refresh
read of all memory elements.
The refresh signal cannot be used by itself
since the refresh address is only guaranteed to be stable during MREQ time.
-
31 -
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/AP.6/AP.8
TMPZ84COOAF/AF-6
TECHNICAL DATA
Figure 7-1 illustrates how the fetch cycle is delayed if the memory
activates the WAIT line.
During T2 and every subsequent Tw, the CPU samples
the WAIT line with the falling edge of CLK.
If the WAIT line is active at
this time, another wait state will be entered
durin~
the following cycle.
Using this technique the read cycle can be lengthened to match the access
time of any type of memory device.
Ml eyel
T2
Tl
Tw
T3
TW
T4
- ~ ~ ~ ~ IL- ~
eLK
X
AO-A15
pe
X
REJo'RESt! AlJi'l'
~
X
\
I
I"fN
DBO-DB 7
-,
~
------- lJ...:
------
II
l L : _JL
--------- - - - - -----
foo-
1\
FIGURE 7-1.
INSTRUCTION OP CODE FETCH WITH WAIT STATES
-
32-
INTEGRATED CIRCUIT
TOSHIBA
TMPZ84COOAP/AP.6/AP.8
TMPZ84COOAF/AF-6
TECHNICAL DATA
1 Cye
11
CLK
AD-Alb
12
13
1~
11
ILJ~ IL- ~ ~
......
I
I
PC
R ~:r'f, ,".: I AIlDR
J
\
L- r-
J
\
-1-------- ----- -----1----- T \ : ------- 1----- -
-t\
u
L.. _ _ _ _
r-
'iN
DBD-DB7
\,.;..;.;..
1\
FIGURE 7-0.
1
INSTRUCTION OP CODE FETCH
- 33-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ AP-6/ AP-8
TMPZ84COOAF/ AF·6
TECHNICAL DATA
(2)
Memory read or write
Figure 8-0 illustrates the timing of memory read or write cycles other
than an OP code fetch (Ml cycle).
These cycles are generally three clock
periods long unless wait states are requested by the memory via the WAIT
signal.
cycle.
The MREQ signal and the RD signal are used the same as in the fetch
In the case of a memory write cycle, the MREQ also becomes active
when the address bus is stable so that it can be used directly as a chip
enable for dynamic memories.
The WR line is active when data on the data
bus is stable so that it can be used directly as a R/W pulse to virtually
any type of semiconductor memory.
Furthermore the WR signal goes inactive one halt T state before the address
and data bus contents are changed so that the overlap requirements for
virtually any type of semiconductor memory type will be met.
Memory Wn toe Cyel
101 eoory Read Cye 1
TZ
Tl
T3
Tl
TZ
T3
ClK
AC>-A15
101
A
101 EM OR
ADD
1oIREQ.
1m
WR
IY>.TA BlS
( IlJ-CY7)
WAlT
---
---- TL
-:r-L
FIGURE 8-0.
MEMORY READ OR WRITE CYCLES
-
34-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ AP-6/ AP-8
TMPZ84COOAF/AF-6
TECHNICAL DATA
Figure 8-1 illustrates how a WAIT request signal will lengthen any
memory read or write operation.
This operation is identical to that
previously described for a fetch cycle.
Notice in this figure that a
separate read and a separate write cycle are shown in the same figure
although read and write cycles can never occur simultaneously.
Tl
CLK
--'
AD-A15
TZ
TW
TW
T3
Tl
~ r--"L..... ~ '""L- ~ ~
:MOI"(~
l~
AU
r--
)1"(
\
READ
} CYCLE
DATA BE
IN
ero-O?)
WR
'"-
mTA BUS
(ro-07)
WAlT
WRITE
} CYCLE
DATA OUT
--- ------ rt ------- P-L= -:LL.: -.fL
_. ,- ----
FIGURE 8-1.
-
MEMORY READ OR WRITE CYCLES WITH WAIT STATES
-
35-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/Ap·6/Ap·8
TMPZ84COOAF/ AF·6
TECHNICAL DATA
(3)
Input or output cycles
Figure 9-0 illustrates an I/O read or 110 write operation.
Notice that
during I/O operations a single wait state is automatically inserted.
The
reason for this is that during I/O operations, the time from when the IORQ
signal goes active until the CPU must sample the WAIT line is very short and
without this extra state sufficient time does not exis't for an I/O port to
decode its address and activate the WAIT line if a wait is required,
Also,
without this wait state it is difficult to design MOS I/O devices that can
operate at full CPU speed.
signal is sampled.
During this wait state time the WAIT request
During a read I/O operation, the RD line is used to enable
the addressed port onto the data bus just as in the case of a memory read.
For 1/0 write operations, the WR line is used as a clock to the I/O port,
again with sufficient overlap timing automatically provided so that the
rising edge may be used as a data clock.
Figure 9-1 illustrates how additional wait states may be added with the
WAIT line.
The operation is identical to that previously described.
-
36-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ AP-6/ AP-8
TMPZ84COOAF/ AF-6
TECHNICAL DATA
Tl
CLK
..-J
T2
•
Tl
T3
I\...-- ~ ~ ~ I"L
I
PORT AD RESS
II
AO-A7
TW
\
I
\
Ilo\TA BUS
}
Read
Cycle
IN
- 1-------I-IL- - - - - ------- - - - - - - - - - --\
writ;e
} Cycle
OUT
DATA BUS
}--
*
Automatically
inserted by
Z8D CPU
FIGURE 9-0.
CLK
-
•
TW
T3
~ r--"\- ' L - ~ ~ ~
X
AD-A7
TW
T2
T1
INPUT OR OUTPUT CYCLES
PORT ADDRESS
I
Ilo\TA IDS
RD
WAlT
J.!i,
\
READ
} CYCLE
- --- ------ _LL__ :rc: ------- ---
-
----
DATA filS
OUT
WRITE
} CYCLE
*
Automatically
inserted by
Z8D CPU
FIGURE 9-1.
INPUT OR OUTPUT CYCLES WITH WAIT STATES
-
37-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/AP.6/AP.8
TMPZ84COOAF/ AF-6
TECHNICAL DATA
(4)
Bus request/acknowledge cycle
Figure 10 illustrates the timing for a Bus Request/Acknowledge cycle.
The BUSRQ signal is sampled by the CPU with the rising edge of the last clock
period of any machine cycle.
If the BUSRQ signal is active. the CPU will set
its address. data and tri-state control signals to the high impedance state
with the rising
edg~
of the next clock pulse.
At that time any external
device can control the buses to transfer data between memory and I/O devices.
(This is generally known as Direct Memory Access [DMA] using cycle stealing).
The maxunyn time for the CPU to respond to a bus request is the length
of a machine cycle and the external controller can maintain control of the
bus for as many clock cycles as is desired.
Note. however, that if very long DMA cycles are used, and dynamic memories
are being used, the external controller must also perform the refresh
function.
This situation only occurs if very large blocks of data are
transferred under DMA control.
Also note that during a bus request cycle,
the CPU cannot be interrupted by either a NMI or an INT signal.
-
Any II Cycle---;"_-BueAvaUab1e Stat;:---j
La8~~te
TX
TX
TX
AO-AlS
DO-Il'7
fi:b~~--+-~--~
FIGURE 10.
BUS REQUEST / ACKNO"I EDGE CYCLE
-
38-
T1
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ AP-6/ AP-8
TMPZ84COOAf/ Af·6
TECHNICAL DATA
(5)
Interrupt request/acknowledge cycle
Figure 11-0 illustrates the timing associated with an interrupt cycle.
The interrupt signal (INT) is sampled by the CPU with the rising edge of the
last clock at the end of any instruction.
The signal will not be accepted
if the internal CPU software controlled interrupt enable flip-flop is not
set or if the BUSRQ signal is active.
Ml cycle is generated.
When the signal is accepted a special
During this special Ml cycle the IORQ signal becomes
active (instead of the normal MREQ) to indicate that the interrupting device
can place an a-bit vector on the data bus.
automatically added to this cycle.
Notice that two wait states are
These states are added so that a ripple
priority interrupt scheme can be easily implemented.
The two wait states
allow sufficient time for the ripple signals to stabilize and identify which
I/O device must insert the response vector.
--LaetMCycIe
of Instruction
Ml
LaetT Stat
CLK
TIi'f
T2
TI
*
Tw
TW
*
T3
...... ~ ~ ~ ~ ~ IL- ~
-
r-~:L. L
--- ----- ----- ---__ ------I
AD-A15
----
----
I REFRESH
PC
J
\
\
*
Automaticall
inserted by
zao CPU.
.1'JN'
IY.TA IDS
---- ---- ----
-
f----
~
---- ---- - - - - 'r-JL- ----- - - - - - - - - - - - r'
--Mode 0 shown
FIGURE 11-0.
INTERRUPT REQUEST/ACKNOWLEDGE CYCLE
-
39-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ AP.6/AP.8
TMPZ84COOAF/AF·6
TECHNICAL DATA
Figure 11-1 illustrates how additional wait states can be added to the
interrupt response cycle.
Again the operation is identical to that previously
described.
T}
eLK
AD-A15
---'
T2
TW
loll
•
TW
•
TW
T4,
T3
iL.-JiL-.JI ' - ~ ~ ~ ~
IX
J.
PC
REFRES
!--
ADDR
- h
---- i - - - - ---- __""LL -:JL': - - - - i - - - - - - - - - - - - - r----- ---~
\
*
h
·TJN
'-=
t-'
\
I
r-
Automatically
inserted
by Z80
cpu.
I
Mode 0 shown
FIGURE 11-1.
INTERRUPT REQUEST/ACKNOWLEDGE WITH WAIT STATES
-
40-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ AP-6/ AP-8
TMPZ84COOAF/ AF-6
TECHNICAL DATA
(6)
Non maskable interrupt response
Figure 12 illustrates the request/acknowledge cycle for the non-maskable
interrupt.
A pulse on the NMI input sets an internal NMI latch which is
tested by the CPU at the end of every instruction.
This NMI latch is
sampled at the same time as the interrupt line, but this line has priority
over the normal interrupt and it cannot be disabled under software control.
Its usual function is to provide immediate response to important signals such
as an impending power failure.
The CPU response to a non maskable interrupt
is similar to a normal memory read operation.
The only difference being that
the content of the data bus is ignored while the processor automatically
stores the PC in the external stack and jumps to location 0066H.
The service
routine for the non maskable interrupt must begin at this location if this
interrupt is used.
(7)
Halt acknowledge cycle and exit
Whenever a software halt instruction is executed the CPU begins executing
NOP's until an interrupt is received (either a non-maskable or a maskable
interrupt while the interrupt flip flop is enabled).
The two interrupt lines
are sampled with the rising clock edge during each T4 state as shown in
Figure 13.
If a non-maskable interrupt has been received or a maskable
interrupt has been received and the interrupt enable flip-flop is set, then
the halt state will be exited on the next rising clock edge.
The following
cycle will then be an interrupt acknowledge cycle corresponding to the type
of interrupt that was received.
If both are received at this time,
-
41 -
the~
the
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/AP-6/AP-8
TMPZ84COOAF/ AF-6
TECHNICAL DATA
non maskable one will be acknowledged since it was highest priority.
The
purpose of executing NOP instructions while in the halt state is to keep the
memory refresh signals active.
Each cycle in the halt state is a normal MI
(fetch) cycle except that the data received from the memory is ignored and
a NOP instruction is forced internally to the CPU.
The halt acknowledge
signal is active during this time to indicate that the processor is in the
halt state.
loll
--LaetM
Cycle
lAst TTime
CLK
mrr
-
~~~
r--l
f_-___-
:---L- ~ ~ ~
~
--- --- ---- ---- fr------ -------
I
Ao-A15
T5
T4
T3
T2
Tl
REFRESH
PC
II
I
\
I
\
I
!/
'" 1012 an:! 1013 are stack write operations
FIGURE 12.
NON MASKABLE INTERRUPT RESPONSE
~_Ml
__-+___________ Ml __________
~~
__ Ml
T4
CLK
HALT
-mrF or
HALT INSTRUCTION
IS RECEIVED
DURING THI S
MEMORY CYCLE
FIGURE 13.
EXECUTE NOP
HALT ACKNOWLEDGE CYCLE AND EXIT
-
42-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOA.,/AP-6/AP-8
TMPZ84COOAF/ AF-6
TECHNICAL DATA
(8)
Reset cycle
RESET
~ust
be active for at least three clock cycles for the CPU to
properly accept it.
As long as RESET remains active, the address and data
buses float, and the control outputs are inactive.
Once RESET goes inactive, two internal T cycles are consumed before the CPU
resumes normal processing operation.
RESET clears the PC (program counter),
so the first OPcode fetch will be to location OOOOH'
(See Figure 14.)
elK
AD-A15
FLOAT
DD-D7
MR~IOFQ----~------tT.n7Tn~---ff~--r------4-------+,-----~------
~.
mrnm.
lIAL'f
FIGURE 14.
-
43-
RESET CYCLE
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/AP-6/AP-8
TMPZ84COOAF/AF·6
TECHNICAL DATA
POWER DOWN FUNCTION
When system clock to Z80 CPU is stopped at either a high or low level,
Z80 CPU stops its operation and maintains registers and control signals.
However ICC2 Stand-by Supply Current is guaranteed only when the
supplied system clock is stopped at a low level during T4 state of the
following machine cycle (actually that is HI cycle and executes NOP instruction) next to OPcode fetch cycle of HALT instruction.
The timing diazram
when POWER DOlm FUNCTION is implemented by HALT instruction is shown as
figure 15.
This function can be easily realized
\~hen
T6497 clock generator con-
troller is connected with Z80 CPU.
~
OPcode fe tch
cycle of HALT
lnstruc tl on
(Ml cycle)
Tl
T2
T3
T4
t
r;xecutlon of
NOP
(Ml cycle)
Tl
T2
T3
T4
eLK
r----------.,~r<-----
1'--_----'
~------------------~!;~I-----
FIGURE 15.
TIMING DIAGRAM OF
POl~ER
DOWN FUNCTION
BY HALT INSTRUCTION
RELEASE FROt·l pmJER DOWN STATE
The system clock must be supplied to Z80 CPU to release power down state.
When the system clock is supplied to CLK terminal of Z80 CPU, CPU restarts
operati'on continuously from the state when power down function has been
implemented.
-
44-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAPI AP-61 AP-8
TMPZ84COOAF/AF-6
TECHNICAL DATA
Note the followings when release from
pO\~er
down state.
(1) When external oscillator has been stopped to enter power down state, some
warming-up time may be required to obtain precious and stable system
clock for release from power down state.
(2) When HALT instruction is executed to enter power down state, Z80 CPU will
An interrupt signal (NMI or tNT, or RE'SE'r signal must be
enter HALT state.
generated to ZilO CPU after the system clock is supplied to re1ease- power down
state.
Othen~ise
Z80 CPU is still in HALT state even if the system clock
is supplied.
Figure 16 shows an example to connect with T6497 clock generator/controller.
r-
r
VCC
[
r:;..
--'-
P'
r = s e t 81 gnt.:ll
r
-
45-
}Interrupt Reque st SI gnal
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/Ap·6/Ap·8
TMPZ84COOAF/ AF·6
TECHNICAL DATA
INSTRUCTION SET
The Z80 microprocessor has one of the most powerful and versatile
instruction sets available in any a-bit microprocessor.
It includes such unique operations as a block move for fast, efficient data
transfers within memory or between memory and I/O.
It also allows operations
on any bit in any location in memory.
The Z80 CPU can execute 158 different instruction types including all
78 of the 80aOA CPU.
The instructions are devided into the following categories:
8-bit loads
l6-bit loads
Exchanges, block transfers, and searches
a-bit arithmetic and logic operations
General-purpose arithmetic and CPU control
l6-bit arithmetic operations
Rotates and shifts
Bit set, reset, and test operations
Jumps
Calls, returns, and restarts
Input and output operations
-
46-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAPI AII-61 AII-8
TMPZ84COOAF/AF-6
TECHNICAL DATA
A variety of addressing modes are implemented to permit efficient and
data transfer between various registers, memory locations, and input/output
devices.
These addressing modes are as follows:
Inunediate
Inunediate extended
Modified page zero
Relative
Extended
Indexed
Resister
Resister indirect
Implied
Bit
-
47-
INTEGRATED CIRCUIT
TOSHIBA
TMPza4COOAPI AP-61AP-a
TMPza4COOAfl Af-6
TECHNICAL DATA
B-BIT LOAD GROUP
Instruction
Flas
Code
Hex Operation
No. of No. of M No. of T COlllllents
S Z H~ N C Bytes ICycles States
D7D6DsD,D3D2DjDo
r+ rl
0.1 ... r .... <- r' ....
4
1
1
LDr r
2
7
2
OO+r .... l l 0
r<-n
LDr,n
n
7
2
1
o 1 <- r .... 1 1 0
r"" (HL)
LDr (HL)
19
3
5
DD
LDr, (IX+d)
1 101 1 101
r"" (IX+d)
0 1+r .... 110
d-5
19
3
FD
r"" (IY+d)
LDr, (IY+d)
1 111 1 101
0 1<-r ... l10
d2
7
(HL) .... r
011 1 0 .... r ...
LD(HL),r
- 1
19
(lX+d) .... r
5
DIl
1 101 1 1 0 1
LD(IX+d) ,r
- 3
01110+r ....
d19
3
5
FD
(IY+d) .... r
LD(lY+d) ,r
1 111 1 101
01110+r'"
d3·
10
2
o 0 1 1 0 1 1 0 36 (HL) + n
LD(HL),n
n_
(IX+d) +n
4
5
19
11011101
DD
LD(IX+d),n
o0 1 1 0 1 1 0
d_
n_
4
5
19
(IY+d) +n
1 111 1 101
FD
LD(lY+d) ,n
o 0 1 1 0 1 1 0 36
do
n1
2
7
LDA (BC)
o 0 0 0 1 0 1 0 OA A+ (BC)
2
A .... (DE)
1
7
000 1 101 0
1A
LD A (DE)
4
13
A + (nn)
3
LDA, (nn)
001110.10
3A
nn2
1
7
LD(BC) ,A
o 0 0 0 0 0 1 0 02 (BC) +A
-(DE) +A
Z
000 1 001 0
7
LD(DE),A
12
- 1
4
o 0 1 100 1 0 32 (nn) +A
13
LD(nn),A
- 3
-nn_
A+l
2
2
LDA, I
1 1 101101
ED
9
o 0 RIH R o 101 0 1 1 1 57
2
LDA, R
1 1 101 101
ED
2
9
A""R
00 Rift R o 1 0 1 1 I I I 5F
I+A
1 1 1 0 1 101
2
2
ED
LDI,A
9
--o 1 000 1 1 1 47
LDR, A
1 I 101 101
z
2
ED
~
R""A
o J. 001 111 4F
,
Notes: r,r means any of the registers A, B, C, D, E, II, L
IFF the content of the interrupt enable flip-flop (IFF) is copied into the
Flag Notation: --flag not affected, R-flag reset, S-flagl set.
0- flag is affected according to the result of the operation.
~Inemonic
--- ------- - -- -------- --
r,r
000
001
010
011
100
101
111
Reg.
B
C
D
E
H
L
A
- - - -- ---
.
------
0
-
---------
.
------
---------------
0
---- - - - -- -
.
----- ---
-
48-
P/v flag
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ AP.6/ AP.8
TMPZ84COOAF/ AF-6
TECHNICAL DATA
16-81T LOAD GROUP
Instruction Code
Mnemonic
LD dd,nn
D7D6DsD.D3D2DIDo
o
0 d d 0 0 0 1
S ZHt N C
dd .... nn
n_
nLDIX,nn
LDIY,nn
LD HL, (nn)
LDdd,
(nn)
1 1 0 1 1 101
0 0 1 0 000 1
DO
IX .... nn
21
·
1 1 1 1 1 101
0 1 000 0 1
FD
IY .... nn
21
nn-
0 1 0 101 0
2A
H .... (nn+l)
(nn)
L
ED
ddH-+-(nn+l)
ddL-+-(nn)
DO
IXH-+-(nn+l)
IXL ....(nn)
nn-
-
1 1 1 0 1 1 0 1
1 d d 1 011
o
nnLDIX,
(nn)
3
------
4
------
4
4
14
------
3
5
16
-----
4
6
20
----- -
4
6
20
1 1 011 101
0 101010
o
(nn)
2A
1 1 1 1 110 1
1 0 1 0 1 0
o0
LD(nn),dd
LD(nn),IX
-
o· 0 1 0 o 0 1 0
.
LD SP HL
LD SP, IX
LD SP,IY
14
11 SP
-- ---
4
6
20
22
(nn+l ) .... H
(nn) .... L
------
3
5
16
EO
(nn+l) .... ddH
(nn) .... ddL
------
4
6
20
DD
(nn+l)-+- IXH (nn) .... IXL
-----
4
6
20
-----
4
6
20
----------------
1
2
1
2
10
2
2
10
nn_
1 1 1 0 110 1
0 1 d d 001 1
·
1 1
o0
o
n_
n..----
1 1 101
1 0 001 0
n---
1 1 1 1 1 101
001 0 o 0 1 0
.
dd Pair
00 BC
01 DE
10 HL
-
2A
22
nLD(nn),IY
4
10
IYH-+-(nn+l)
IYL ....(nn)
FO
nn_
LD(nn),HL
3
FD
22
(nn+l) .... lYH (nn).... IYL
n_
n_
1 1 1 1 i.~ Cfg- SP....HL
SP+]X
1 1 0 1 1. 101
DD
1 1 1 1 1 0 0 1
F9
1 1 1 1 1 101
FD
SF-+- IY
1 1 1 1 1 001
F9
-
49-
Corranents
States
-- -- --
nnLDIY,
No. of No. of M No. of T
Bytes Cycles
nn_
o
o
Flags
Operation
Hex
6
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ AP-6/ Ap·8
TMPZ84COOAF/AF·6
TECHNICAL DATA
Instruction Code
Mnemonic
D7 DSDs D,D3D2DIDo
o1
Hex
0 1
PUSHqq
1 1 q q
PUSH IX
1 1 011 1 0 1
1 1 1 o 0 1 0 1
DO
o1
o1
FD
PUSH IY
1 1 III 1
1 1 100 1
ES
ES
POPqq
1 1 q q 0 001
POPIX
1 1 o 1 110 1
1 1 1 000 0 1
DD
1 1 1 1 1 101
1 1 1 o 0 0 0 1
FD
El
POPIY
El
Operation
Flags
No. of No. of M No. of T
Comments
S Z H Ply N C Bytes Cyc1 es States
(SP-2)+qqL (SP-l)+QQH
SP-?SP-2
(SP-2)+IXL (SP-l)+IXH
Sp"Sp··2
(SP-2)+IYL (SP-2)+IYH
SP-+SP-2
QqH+(SP+l) qqL··(SP)
SP+SP+2
IXH+(SP+1) IXL+(SP)
SP-+SP+2
IYH+(SP+l) IYL+(SP)
Sp-"SP+2
--
1
3
11
-----
2
4
15
-----
2
4
IS
-----
1
3
10
-----
2
4
14
-----
2
4
14
---
qq
00
01
10
11
Pair
BC
DE
HL
AF
I
Notes: dd 1s any of the register pairs BC, DE, HL, SP
qq is any of the register pairs AF, BC, DE, HL
(PAIR)H' (PAIR)L refer to high order and low order eight bits of the register pair
respectively. e.g. BCL-C, AFH-A
Flag Notation: - . flag not affected, R - flag reset, S = flag set,
O~flag is affected according to the result of the operation.
-
50-
INTEGRATED CIRCU IT
TOSHIBA
TMPZ84COOAP/ AP-6/ AP-8
TMPZ84COOAF/ AF·6
TECHNICAL DATA
EXCHANGE GROUP AND BLOCK TRArMI:.R AND SEARCH GROUP
Instruction Code
Mnemonic
Hex
EXX
D7DsDsD.D3D2D,Do
1 1 10101 1
o 0 001 000
1 1 0 1 100 1
FJ{(SP) ,HL
1 1 10001 1
E3
EX(SP),IX
1 1 o 1 110 1
1 1 1 000 1 1
1 1 1 1 1 101
11100011
101 0 000 0
DD
E3
FD
E3
ED
AO
1 1 1 o 1 101
1 0 1 1 a 0 0 0
ED
BO
LDD
11101101
10101000
ED
A8
LDDR
1 1 1 0 1 101
101 1 1 000
ED
B8
EX DE, HL
EX AF AF'
EX(SP),IY
LUi
LDIR
CPI
1 1
o
o
ED
Al
1 1 101 1 0 1
1 011000 1
ED
Bl
1 1 101 1 0 1
1 o 1 0 1 0 0 1
ED
A9
1 1
o
1
DE+-+HL
AF ..... AF·
Flags
No. of No. of M No. of T
Comments
S Z H Piv N C Bytes Cycles States
1
4
------ 1
(Exx)
4
1
-- --- 1
4
Register
1
--- -- 1
bank and
auxiliary
19
register
5
------ 1
bank ex23
6
chan~e
------ 2
-
(BC..... BC.)
DE-DE'
HL-HL'
H-(SP+1)
I:-"::.{SP)
1 1 0 1
0 0 0 1
1
1
CPIR
1 U 1 1 U 1
EB
08
D9
Operation
IXH-~P+l)
-
IXL-(SP)
IYH-CSP+l) - - - - JYL..... (SP)
(DE) .. (HL) - - RQ) R DE.. DE+1
HL<-HL+l
BC.. BC-l
(DE) .. (HL) - - R R R DE.. DE+1
HlA-HL+l
BC.. BC-l
Reg~~h
BCeD
(DE) .. (HL) - RDE+-DE-l
HL..HL-l
BC+BC-l
(DE)+(HL) - - R R R DE.. DE-l
HL<-HL-l
BC...BC-l
Repeat
until
BC=O
A-(HL)
fJ~ ~W s HL+HL+l
BC..-BC-l
A-(HL)
v 2 vI0 s -HL+-HL+l
BC..BC-l
Repeat
until
A=(HL) or
-
Rp
2
6
23
2
4
16
*1
2
2
5
4
21
16
If
If
2
4
16
2
2
5
4
21
16
2
4
16
2
5
2
4
21
16
2
4
16
IRC=()
CPD
~-(HL)
2
~L+HL-l
rsC+BC-l
-
51 -
,-1- S -
BerO
BC=O
If RC,O
If BCzO
*2
*3
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/ Ap·6/ AP-8
TMPZ84COOAF/ AF·6
TECHNICAL DATA
Instruction Code
Nmenomic
CPDR
Notes:
. e-2 in the op-code provides an effective
ilddress of pc+e as PC s incremented by 2 prior to the addition of e.
Flag Notation: - - flag not affected, R - flag reset, S - flag set,
o - flag is affected according to the result of the operation.
10
"
-
59-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COOAP/AP-6/AP-8
TMPZ84COOAF/AF-6
TECHNICAL DATA
CAll AND RETURN GROUP
Instruction Code
Mnemonic
CALLnn
CALLcc,nn
D7D6 D5D• D3D2DIDo
Hex
1 1001101
n_
n1 1 c c 1 0 0
CD
n--n_
RET
1 100 1 001
RETcc
1 1
RET!
C9
c cOO 0
1 l' 1 0 1
001
1 0 1
000
1 0 1
101
101
1 0 1
RETN*
o1
1 1
o1
aSTp
ll+t+lll
ED
4D
ED
45
Operation
(SP-l)+PCH
(SP-2) .... PCL
PC+-nn
If condiCion cc is
false contlnue,
otherwise
same is
CALLnn
PCL+(SP)
PCIf"" (S P+l )
If condition cc is
false continue,
otherwise
same as
RET
Return from
interrunt
Return from
non maskable interrupt
I (SP-l)+PCH
(SP-2)+PCL
PCH+O
PCL+P
Fla s
No. of No. of M No. of T
S Z HIN N C Bytes Cycles States Collllllents
- - ----
3
5
17
--- ---
3
3
10
If cc is
3
5
17
false
If cc is
true
1
3
10
1
1
5
I
3
11
2
4
14
2
4
14
1
j
11
------ - - -- -
------ - - -- -
------
cc is
false
If cc is
true
Condice
tion
1000 NZ non-zero
001 Z zero
010 NC non
carry
011 C carry
100 PO paritI odd
101 P parity even
110 P sign
positive
111 M sign
negative
If,
t
000
001
010
011
100
101
110
III
*
RETN loads IFF2 + IFFI
Flag Notation:
flag not affected, R - flag reset, S • flag set,
o - flag is affected according to the result of the operation.
-
60-
p
OOH
08H
10H
18H
20H
28H
30H
38H
INTEGRATED CIRCUIT
TOSHIBA
TMPZ84COOAP/AP-6/ AP-8
TMPZ84COOAF/ AF-6
TECHNICAL DATA
INPUT AND OUTPUT GROUP
Instruction Code
Mnemonic
IN A, (n)
INr, (C)
F1~lr~.- No. of No. of M No. of T
1 1 0 1 101 1
n_
DB
A.... (n)
1 1 1
1 1
1
000
r
1
ED
r .... (C)
R P
If r-110
only the
flags will
be affected
-(lit)..-(C)
XY. XX rs X
B<-B-l
° °
rrcrrru
.L
1
1 0 1 000 1 0
ED
A2
1 1 101 101
1 0 1 1 0
1
ED
B2
------
°° °
Bytes Cycles
States
2
3
11
2
3
12
Comments
n to Ao"'A7
IAcc to A."'A1S
C to Ao"'A7
B to As"'AI5
2
4
16
C to Ao"'A7
B to-Aa"'~5
5
21
C to Ao"'A7
B to Aa"'AI5
1:!~l!1:!"J.
INIR
1 101 0
1 1
1 1 101 101
o 1 r 001
D3
(HL) .... (C)
B<-B-l
HL<-HL+l
Repeat
until B-O
-(HL)+(C)
B....B-l
HL....HL-l
(HL) .... (C)
B....B-l
HL....HL-l \
Repeat
until B-O
(n) ....A
ED
(C) ....r
OUTI
1 1 101 101
101 0 001 1
ED
A3
OTIR
1 1 101 101
ED
° °
IND
1 1 1 U 1 1 U 1
1 0 1
1 0 1 0
°
°
INDR
1 1 1 0 1 1
1
1 011 1 0 1 0
OUT(n),A
OUT(C),r
°
1
° °
° °
1 1
0 1 1
ED
AA
ED
BA
B3
OUTD
1 1 101 101
1
1
1 0 1 1
ED
AB
OTDR
1 1 101 101
10111011
ED
BB
Notes:
r
S Z H PAr N C
Hex
°
r-INI
Operation
D7D6 DSD.D3 D2D1Do
WI
---
/--~~~~----~--~
~"<----J
I§ 1""1-__
A L U
/IFFl
FLUG(F')
B REGISTER
CONTROL CIRCUIT FOR CONTROL IlUS
~
~
~
~
~
~
lOrut
!iAi:T
WAIT
M}{El.<
RD
W}{
Fig. 3.1
Block Diagram
-77-
+
t
IlUSREl.< i'i"liSACi{
Ml
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COIF
TECHNICAL DATA
3.2
System configuration
The TMPZ84C01F has a built-in system clock generator for CMOS Z80 in
addition to the standard functions of the TMPZ84COOP CMOS Z80 MPU.
The explanation is provided here with emphasis placed on the halt
function relative to the clock generator, which is an additional
function. The internal register group, reset and interrupt function are
ident ical to those of the TMP84COOP.
For detai Is please refer to the
data sheet for the TMPZ84COOP.
In this section, the following principal compoments and functions will be
described.
(1) Generation of clock
(2) Operation mode
(3) Warming-up time at time of restart
3.2.1
Generating the system clock
The TMPZ84C01F has a built-in oscillation circuit and required clock can
be easily generated by connecting an oscillator to the external terminals
(XTALl, XTAL2).
Clock in the same frequency as input oscillation
frequency is generated.
Examples of oscillator connection are shown in Fig. 3.2.
C IN
22pF
Fig. 3.2
3.2.2
33 pF
Examples of Oscillator Connection and Constant
Operation modes
There are 4 kinds of operations modes available for the TMPZ48COIF in
connection with generation of clock; RUN Mode, IDLEl/2 Modes and STOP
Mode.
One of these modes is selected by the mode select inputs (MSl,
MS2) •
The operation mode is effective when the halt instruction is executed and
when
the halt
instruction is not
executed,
clock
is
supp~ied
continuously. Restart of MPU from the stopped state under IDLEl/2 Mode
or STOP Mode is effected by inputting either RESET signal or interrupt
signal (INT or NMI).
-
78-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C01F
TECHNICAL DATA
Operations of these modes in the halt state are shown in Table 3.1.
Table 3.1
IOperation Model MSI
I RUN Mode
I 1
I
I
I IDLEI Mode
Clock Generating Operation Modes
MS2
I
I
I
I
I
I IDLE2 Mode
I
STOP Mode
0
0
Description at HALT State
MPV continues the operation and supplies
clock to the outside continuousl .
The internal oscillator's operation only
is continued and clock (CLK) output as
well as internal operation are stopped at
"0" level of T4 state in the halt instruc-I
tion operation code fetch cycle.
I
The internal oscillator's operation and
I
clock (CLK) output are continued but the I
internal operation are stopped at "0"
I
level of T4 state in the halt instruction I
operation code fetch cycle.
I
All operations of the internal oscillator, I
clock (CLK) output, and internal operationl
are stopped at "0" level of T4 state in
I
the halt instruction operation code fetch I
cycle.
I
3.2.3
Warming-up time at time of restart (STOP Mode)
When MPU is released from thE' halt state by accpeting an interrupt
request,
MPU,
then,
wi 11
execute
an
interrupt
service
routine.
Therefore, when an interruption request
is accepted,
MPV
starts
generation of internal system clock and clock output after a warming-up
time by the internal counter (2**14+2.5) TcC (TeC: Clock Cycle) to obtain
a stabilized oscillation for MPU operation.
Further, in case of the restart by RESET signal, the internal counter
does not operate for a quick operation at time of power ON.
3.3
Status change flowchart and basic timing
In this section, the status change and basic timing when the TMPz84C01F
is operating are explained.
3.3.1
Status change flowchart
-
79-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
MODE CI.!ANOE
>-=-__
TMPZ84COIF
~.,
?
111
Ml
MJ\!EDI ALI:;LY
'i
E~
l..FTEh t.CCEPTl NG="'-'-'''------------~~=L_.,
Ill"'!' ?
TW'
NO
'i ES
IS M 31
;-'TATE?
YES
>~'-----------_,
NO
NO
rllLT
1 '.~TI..T' : Ie \
YES
>--,r====----"
HALT
Fig. 3.3
-
~TAHT
(a) Status Change Flowchart
80-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C01F
TECHNICAL DATA
HALT START
RUN MODE
CLOCK OUTPUT STOP
INTERNAL
INTERNAL OPERATION
OPERATION STOP
STOP
INTERNAL OSCILLATIOM
STOP
(CLOCK OUTPUT STOP)
INTERNAL OPERATION
STOP
YES (STOP MODE)
NO (I DLEV2 MODE)
INTERNAL SYSTEM CLOCK RESTART
CLOCK OUTPUT RESTART ONLY STOP,IDLEI
END
Fig. 3.3
(b) Status Change Flowchart
-
81 -
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
3.3.2
TMPZ84C01F
Basic tlmlng
The bas lC timing is explained here wi th emphas i" placed on the ha 1 t
function relative to the clock generator. Except ~ signal output, the
following items are idnetical to those for the TMPZ84COOP. Refer to the
data sheet for the TMPZ84COOP.
o Operation code fetch cycle
o Memory read/write operation
o Input/output operation
o Bus request/acknowledge operation
o Maskable interrupt request accepting operation
o Non-maskable interrupt request accepting operation
o Reset operation
Note that the TMPz84COIF does not have the refresh terminal (RFSM) but
refresh address is output on the address bus in the operation code fetch
cycle (Mi) as in the TMPZ84COOP since the on-chip refresh control circuit
is available.
(1)
(a)
Operation when HALT instruction is execution
When MPU fetches a halt instruction in the operation code fetch cycle,
HALT signal goes active (low level) in synchronous with falling edge of
T4 state for the peripheral LSI and MPU stops the operation. The system
clock generating operation after this differs depending upon the
operation mode (RUN Mode, IDLEI/2 Mode or STOP Mode).
If the internal
system clock is running, MPU continues to execute NOP instruction even in
the halt state.
RUN Mode (MSl=l, MS2=1)
Shown in Fig. 3.4 is the basic
executed in RUM Mode.
timing when the halt
instruction
is
In RUN Mode, system clock (¢) in MPU and clock output (CLK) to the
outside of MPU are not stopped even after the halt instruction is
executed. Therefore,until th" halt stae is released by the interrupt
signal (MNI OR INT) or RE' .,1 signal, MPU continues to execute NOP
instruction.
HALT OP CODE
FETCH CYCLE
Fig. 3.4
+_
NOP bXbCUTION
I
NOP EXECUTION
--------~--------~
--'---'----
Timing of RUN Mode (at Halt Command Execution)
-
82-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COl F
TECHNICAL DATA
(b)
IDLEl Mode (MSl=O, MS2=O)
Shown in Fig. 3.5 is the basic timing when the halt instruction is
executed in IDLEl Mode.
In IDLEl Mode, system clock (6) in MPU and clock output (CLK) to the
outside. of MPU are stopped and MPU stops its operation after the halt
instruction is exeduted.
However, the internal oscillator continues to operate.
T4
~~----------------~0~'------
CLK
It
1'\
¢(INTERNAL
SYSTEM CLOCK)
_ _J
MPU OPERATION STOP
_____________________________~
HALT ----~~r
~
M1
--{fl-------
:fr-----
-.---------------------------------------------------
HALT COMMAND OPERATION
-I
cODE FETCH CYCLE
Fig. 3.5
(c)
IDLEl Mode Timing (at Halt Instruction Execution)
IDLE2 Mode (MSl=O, MS2=1)
Shown in Fig. 3.6 is the basic timing when the halt instruction is
executed in IDLE2 Mode.
In IDLE2 Mode, system clock (p) in MPU is stopped and MPU stops its
operation after the halt instruction is executed.
However, the interneel oscillator and clock output (CLK) to the outside
of MPU continues to operate.
T4
eLK
¢(INTERNAL
SYSTEM CLocK)
HALT
~
MPU OPERA TION STOP
~--------------------~f~S------
__
~-----------~Jlr--------
" I"
M1
HALT INSTRUCTI ON OPERAT ION
CODE FETCH CYCLE
Fig. 3.6
I
'
IDLE2 Mode Timing (at Halt Instruction Execution)
-- 83--
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C01F
TECHNICAL DATA
(d)
STOP Mode (MSl=l, MS2=0)
Shown in Fig. 3.7 is the basic timing when the halt instruction is
executed in STOP Mode.
In STOP Mode, internal operation and internal oscillator are stopped
after the halt instruction is executed. Therefore, system clock (0) in
MPU and clock output (eLK) to the outside of MPU are stopped.
Tl
T2
T3
T4
CLK
¢( INTERNAL
SYSTEM CLOCK)
CLK OUTPUT STOP
~~MPU
OPE1'lATION
STOP
~-HALT INSTRUCTION OPERATION
CODE FETCH CYCLE
Fig. 3.7
(2)
STOP Mode Timing (at Halt Instruction Execution)
Release from halt state
The ha I t state of MPU is re leased when "0" is input to RESET signa I and
MPU is reset or an interrupt request is accepted.
An interrupt request
signal is sampled at the leading edge of the last clock cycle (T4 state)
of NOP instruction. In case of the maskable interrupt, interrupt will be
accepted by an active INT signal ("0" level)'
In case of the
non-maskable interrupt, if the internal NMI F/F which is set at the
leading edge of NMl signal is set to "1", the interrupt is accepted.
However, in case of the maskable interrupt, the interrupt enable
flip-flop must have been set to "1".
The accepted interrupt process is
started from next cycle.
Further, when the internal system clock is stopped (IDLEl/2 Mode, STOP
Mode), it is necessary first to restart the internal system clock.
The
internal system clock is restarted when RESET or interrupt signal (NHI or
TIIT) is input.
(a)
RUM Mode (MSl, MS2=1)
The halt release operation by acceptance of interrupt request in RUN
Mode is shown in Fig. 3.8.
In RUN Mode the internal system clock is not stopped and therefore, if
the interruption signal is recognized at the rise of T4 state of the
continued NOP instruction, MPU will executes the interrupt process from
next cycle.
-
84-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84C01F
The halt release operation by resetting MPU in RUN Mode is shown in
Fig. 3.9. After reset, MPU will execute an instruction starting from
address OOOOH. However, in order to reset MPU it is necessary to keep
RESET signal at "0" for at least 3 clocks. In addtion, if RESET signal
becomes "1", after the dummy cycle for at least 2T states, MPU executes
an instruction from address OOOOH.
HALT INSTRUCTION
EXECUT ION
I
INTERRUPT PROCESS
NOP INSTRUCTION EXECUTION
_ _ _ _ _11.-=,1_ _
-I
T2
T3
Tl
T4
CLK
¢(INTERNAL
SYSTEM CLOCK)
-
Fig. 3.8
.J--MPU INTERNAL
LATCH t'OR NMJ
Halt Release Operation Timing by
Interrupt Request Signal in RUN Mode
EXECUTE IN STRUC TlON
HALT INSTRUCTION
EXECUTION
• \
f~DDRESS OOOOH
Tl
CLK
¢(INTERNAL
SYSTEM CLOCK)
------------~~~------------~:.~'-----------,
----'-'C:J
RESET----,L,f-,
Fig. 3.9
(b)
IDLEI Mode
Halt Release Operation Timing by
Reset in RUN Mode
(MSl=O, MS2=0), IDLE2 Mode (MSl=O, MS2=1)
- 85-
T2
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COl F
TECHNICAL DATA
The halt release operation by interrupt signal in IDLE1 Mode is shown
in Fig. 3.10 (a) and in IDLE 2 Mode in Fig. 3.10 (b).
When receiving NMI or fNT signal, MPU starts the internal system clock
operation.
In IDLE1 Mode, MPU starts clock output to the outside at
the same time.
The operation stop of MPU in IDLE1/2 Mode is taken
place at "0" level during T4 state in the halt instruction operation
code fetch cycle.
Therefore, after restarted by the interruption
signal, MPU executes one NOP instruction and samples an interrupt
signal at the rise of T4 state during the eKecutlon of this NOP
instruction, and eKecutes the interrupt process from nect cycle.
r--r
Nap INSTRVCT ION E.XECU TION
T4
CLK
'" (INTERNAL
SYSTEM CLOCK)
II
T~
T2
Jl'--_-r~-_--'
T41
TI
Jl'----;I--_--f.J
~~---;------~,--------~
'\"~:
')
---------I.',.,-----~ _____
J
L
--l--JI
II
--------~~------~t
MPU
INTERNAL
LATCH FOR NMI
l
INTERRUPT SAMPLING TIMING
Fig. 3.10 (a)
IDLEl Mode
Nap INSTRUCTION eXECUTION
14
CLK~
(> (I NTERNAL
n
SYSTEM CLOCK) --1
_ _ _ _ _--'
~
~ ~,r-----;-------~
.,f--------';\--,L-j
\
NMI
~i
':_
_
I
L
I
- - -
-
- - -
- - - - - I ; ~----
l'
-,-- -
J--
MI'U
LATCHINTEHNAL
FoR NMI
:,r-- - - -
I
INTERHUPT SAMPLING TIMING
Fig. 3.10 (b)
Fig. 3.10
IDLE2 Mode
Halt Release Operation Timing by
Interrupt Request Signal in IDLEl/2 Mode
-
86-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COIF
TECHNICAL DATA
If no interrupt signal
is accepted during the execution of the first
NOP instruction after the internal system clock is restarted, MPU is
not released from the halt state and is placed in IDLE1/2 Mode again at
"0" level during T4 state of the NOP instruction, stopping the internal
system clock.
If INT signal is not at "0" level at the rise of T4
state, no interrupt request is accepted.
The halt release operation by resetting MPU in IDLEl Mode is shown in
Fig. 3.11 (a) and that in IDLE2 Mode in Fig. 3.11 (b).
When RESET signal at "0" level is input into MPU, the internal system
clock is restarted and MPU will execute an instruction stored in
address OOOOH.
At time of RESET signal input, it is necessary to take the same care as
that in resetting MPU in RUN Mode.
I
"EXECUTE INSTRUCTION
ADDRESS OOOOH
Tl
eLK
'" (INTERNAL
SYSTEM CLOCK)
HALT
T2
FROM
T3
SL.,~JULfULJL
JL
~
~r-~--------~
Fig. 3.11 (a)
IDLEl Mode
EXECUTE INSTRUCTION FROM
ADDRESS OOOOH
Tl
CLK
'" (INTERNAL
SYSTEM CLOCK)
T2
T3
IVu-u-u-LJLfl.JLJLJL
~~
-----f'II--\I-------~r/~---_.,
r-\
~--~I
RESET
-----I·iJ___--4CJn----Fig. 3.11 (b)
Fig. 3.11
IDLE2 Mode
Halt Release Operation Timing by
Reset in IDLE1/2 Mode
-
87-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COIF
TECHNICAL DATA
(c)
STOP Mode (MSI=I, MS2=0)
The halt release operation by interrupt signal in STOP mode is shown in
Fig. 3.12.
When MPU received an interrupt signal, the internal oscillator is
restarted.
In order to obtain stabillized oscillation, the internal
system clock and clock output to the outside are started after a
warming-up time of (2**14+2.5) Tce (TcC: Clock Cycle) by the internal
counter passed.
MPU executes one NOP instruction after the internal system clock is
restarted and at the same time, sampling an interrupt signal at the
rise of T4 state during the execution of this NOP instruction. If the
interrupt signal is accepted, MPU executes the interrupt process
operation from next cycle.
At time of interrupt signal input, it is necessary to take the same
care as that in the interrupt signal input in IDLEI/2 Mode. The hal t
release operation by MPU resetting in STOP Mode is shown in Fig. 3.13.
When RES'E'f signal at "0" level is input into MPU, the internal
oscillator is restarted. However, since it performs a quick operation
at time of power ON, the internal counter does not operate. Therefore,
the operation may not be carried out properly due to unstable clock
immediately after the internal oscillator is restarted. To restart the
clock by RESET signal in STOP Mode, it is necessary to hold RESET
signal at "0" level for sufficient time.
When RESET signal becomes
"1", after the dummy cycle for at least 2T states, MPU starts to
execute an execution from address OOOOH.
NOP COMMAND EXECUTION
I-
Tl
T4
CLK
rp (INTERNAL
SYSTEM CLOCK)
HALT
I
T2
T3
Tl
T4
~J--_ _-~
~f----hl-----'
~f--+--------~
I
J
I
I
I
, ___ MPU INTERNAL
LATCH FOR NMI
---1r--------- __ ,. . __ J
:,
INT
INTEHRUPT SAMPLING TIMING
Fig. 3.12
Halt Release Operation Timing by
Interrupt Request Signal in STOP Mode
- 88-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84COl F
EXECUTE I~STRUCTION FROM
ADDRESS OOOOH
CLK
¢
(INTERNAL
SYSTEM CLOCK)
II
I
f1 \
Fig. 3.13
3.4
3.5
fJ
CJ
.!
Halt Release Operation Timing by
Reset in STOP Mode
Instruction set
Instruction set of the TMPZ84C01F are the same as those for
TMPz84COOP. For details refer to the data sheet for the TMPZ84COOP.
the
Method of use
A connecting example of the TMPZ84C01F with the TLCS-Z80 family
peripheral LSI's is shown in Fig. 3.4.
For the explanation and
precautions for connection, refer to Section 3.5 Method of use of the
data sheet for the TMPZ8400P.
-
89-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84COl F
t
~
!
MPU
RE2.ET
HALT
eLK
AO -Al5
IORQ
MREll,
MI
~ll
RD
DO-D7
ViR
BUSREll,
BUSACK
~~v
INT
CTC
RESET
S10
RESET
a
~'J
'"to
DO-D?
<
V)
r-- :;;
=>
::l
CSl
AIr-
'"
"'c----
,-
RD
C/D
'---
1NT
'--
''-':::>"
'"
'"<
Ml
csa
~
:r:
iOR'l
B/A
AOe
:0
>l
CLK
>l
"
L-.-
:::>
::
-CE
~
DMA
~
~
f
CLK
lOR"
MREll,
-Ml
AO--Al5
A
RD
DO-D7
Wh
BUSREQ
nl
"
0
"
'"
"1
'--
'v
V
Fig. 3.14
I---
INT
CE
HAl
<
0
0
>l
~
~
to
>-<
Example Connection with Z80 family peripheral LSI
-
90-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84COIF
4. Electrical Characteristics
4.1 Absolute Maximum Ratings
I
Symbol
vcc
I
Item
S ... pply Voltage
1
Rating
-0.5 to +7
I
I Unit
V
-40 to BS
I
1----------1-----------------------------------1--------------------1-----VIN
I Input Voltage
I -0.5 to Vee + 0.5 I
V
1----------1-----------------------------------1--------------------1-----I
PD
I Power Dissipation (TA=8S·C)
I
250
I mW
1----------1-----------------------------------1--------------------1-----TSOLDER I Soldering Temperature (10 sec)
I
260
I·c
1----------1-----------------------------------1--------------------1-----TSTG
I Storage Temperature
-55 to 125
I·c
1----------1-----------------------------------1--------------------1-----1
1
1
I
4.2
1
TOPR
I
Operating Temperature
I
·C
DC Electrical Characteristics
DC Characteristics (1)
TA = -40·C to BO·C, VCC
SYMBOL
VOLC
VOHC
VIL
VIH
VIHR
VILR
VOL
VOHI
VOH2
ILl
ITEM
Low Level Clock
Output Volta~e
High Level Clock
Output Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
(RESET)
Input Low Voltage
(RESET)
Output Low Voltage
(Except Clock)
Output High Voltage
(1) (Except Clock)
Output High Voltage
(II)(Except Clock)
Input Leak Current
SV ± 10%, VSS = OV
TEST CONDITION I
MIN.
10L = 2.DmA
I
I
IVCC-0.6
IOH =-2.0mA
ITYP.I
I - I
I
I
I - I
I
I
I
I -0.5
2.2 I I
IVCC-0.6 I I
I
I -0.5
I
IOL
2.DmA
I
IOH
-1. 6mA
I
IOH
-2S0uA
VSS~
VIN~
0.8
VCC
VCC
IUNITI
I V I
I
I V
I
I V I
I V I
I V I
0.45
I
MAX.
0.4
I
I
0.4
I
2.4
I
I VCC-O.B
I
I
-
I
ICCl
) State Output
Current in Floatin
Supply Current
(@ RUN Mode)
(Note)
ICC2
Supply Current
(@ STOP Mode)
ICC)
Supply Current
(@ IDLEI Mode)
0.4~
±10
I
±10
I
0.2V,VILC=VIL
=0.2V
-
91 -
1
1
I
V I
I
V I
I
V I
I
V I
I
I
I UA I
I
I
TliAI
I
I
I
rnA I
I
I
I
UA I
I
I
I
rnA I
I
I
I
1LO
I
I
I
VCC
1
15
20
0.5
10
1.0
2.0
I
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
SYMBOL
ICC4
(Note)
4.3
TEST CONDITION I
VCC=5V,CLK=4MHzI
VIHC=VIH=VCC- I
0.2V,VILC=VIL I
=0.2V
I
MIN. ITYP.I
I
MAX. IUNITI
I
I
6.0 I mA I
I
I
I
I
I
I 3.01
I
I
I
I
At T4 "LOW" state of the halt instruction fetch cycle.
AC Electrical Charactreistics
TA
I NO.
I 1
I 2
I 3
I 4
I 5
I 6
I
I 7
I
I 8
I
I 9
I
I
I 10
I
I
I 11
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ITEM
Supply Current
(@ IDLE2 Mode)
TMPZ84COIF
-40·C to 85·C, VCC = 5V ± 10%, VSS
SYMBOL
TcC
TwCh
TwC1
TfC
TrC
TdCr(A)
TdA(MREQf)
TdCf(MREQf)
TdCf(MREQr)
ITEM
Clock freg uenci:
High clock Eu1se width
Low clock Eu1se width
Clock falling time
Clock rising time
Effective address output
delai: from clock rise
Address output definite
time Erior to MREg
~y from clock fall to
MREg="L"
~y from clock rise to
MREg="H"
TwMREQh
MREQ high level pulse
width
TWMREQI
MREQ low level pulse
width
~y from clock fall to
MREg="H"
.£!;lay from clock fall to
RD="L"
.£!;lay from clock rise to
RD="H"
Data set-up time for
clock rise
Data hold time for
iii rise
12
TdCf(MREQr)
13
TdCf(RDf)
14
TdCr(RDr)
15
TsD(Cr)
ov
(*): TEST CONDITION
(*)
MIN. TYP. IMAX. I UNIT
250
ns
DC
110
DC
ns
110
DC
ns
30
ns
30
ns
ns
110
-
CL=
2201
100pF
35
17
TsWAIT(Cf)
WAIT
signal set-up time
for clock fall
70
18
1*
I 19
ThWAIT(Cf)
WAIT
10
TdCr(M1r)
ns
85
ns
ns
-
ThD(RDr)
TdCr(M1f)
85
110
16
I
I 20
I
ns
65
0
I
I
I
I 85
I
I 95
I
I 85
I
- I
-
ns
ns
ns
ns
ns
I
I
I
ns
I
hold time after
clock fall
.£!;lay from clock rise to
M1="L"
.£!;lay from clock rise to
Ml-"H"
-
92-
-
-
I
I
I
I
ns
1100
ns
!
ns
I
1100
I
ns
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
I NO.
\ 21
SYMBOL
TdGf(RDr)
\
\ 22
TdCr(RDf)
I
\
23
TsD(Cf)
I
\
\
\
24
I 25
I
I 26
\
\
\
27
I 28
TdA( IORQf}
TdCr(IORQf)
TdCf( IORQr}
TdD(WRf)
TdCf(WRf)
I
I
I 29
\ 30
\
\
\
31
I 32
TwWR
TdCf(WRr)
TdD(WRf)
TdCr(WRf)
\
\ 33
TdWRr(D)
\
\ 34
\
\
\
\
\
35
36
I
I 37
\ *
\ 38
TdCf(HALT)
40
41
TdCr(BUSACKf)
TdCf(BUSACKr)
TdCr(Dz)
TdCr(CTz)
\
\
\
\
\
\
\ -10\
\ CL=
\
\
\
I
I
I
I
I
I
\
I
I
\
\
TdCr(Az)
TdCr(A)
-
93-
UNITI
ns I
I
ns I
\
-
-
\
\
P.OOpF \
I
\
\
\
\
\
\
\
\
I
BUSREQ hold time after
\
clock rise
I
Time from clock rise to \
BUSACK="L"
I
Time from clock fall to I
BUSACK="H"
\
Delay from clock rise to \
data bus float state
\
Delay from clock rise to I
control output float
\
state
\
(MRE
lOR
RD WR)
\
Delay from clock rise to \
address bus float state \
Address holding time from\
MREQ I IORg I RD or WR
\
\
\
\ 42
\
\ 43
I
IMIN.ITVP.IMAX.
- \ - I 85
I
I
I
I - I - I 85
I
I
\
I 501 - I
\
I
I
I
\
I
I 1801 - I
I
\
I
I - I - I 75
I
\
I
- I 85
\
\
I
I
I
\ I 80\
I
I
I
I
- \ 80
\
I
I
I
I
\
I
I 2201 - I I
I
I 80
ThBUSREQ(Cr)
I
\
WR 2ulse width
Delay from clock fall to
WR="H"
Dat~definite time prior
to WR fall
Delay from clock rise to
WR="L"
Output data~olding
after WR="H"
Delay from clock fall to
HALT="L" or "H"
I (* )
I
I
I
I
I
I
I
NMI 2u1se width
Set-up time for clock
rise
I
\
ITEM
Delay from clock fall to
RD="H"
Delay from clock rise to
RD="L"
Data set-up time for
clock fall (at time of
M2! M3, M4! M5 c~cle)
Address definite time
rior to lOR fall
Delay from clock rise to
IORg="L"
Delay from clock fall to
IORg="H"
Dat~definit time prior
to WR fall
Delay from clock fall to
WR="L"
TwNMI
TsBUSREQ(Cr)
\
\ 39
TMPZ84C01F
\
I
\
-
I
I
60\
-
I
-
\
I
I
I
I
I
I
I
I
I
\
I
\
\
\
\
\
\
\
\
\
\
\
-
\
\
ns I
I
I
ns I
I
ns I
I
I ns I
\
I
I ns \
\
I
I ns I
I
\
I
I
I ns I
I ns I
\
- I
\
\
ns \
\
65
I
-
I
I
\
ns
\
\
I
ns \
\
\
\
\
I
\300
\
I
\
\
ns \
I
I
\
\
I
- I ns I
I
I ns I
\
\
I
I
I
\
I
I
101
I
I ns I
\
I
I
I
1100 I ns \
I
I
I
I
I
- 1100 I ns \
I
\
I
\
\
- I - I 90 \ ns \
801
501
- I
\
-
I
\
-
I
\
I
\
\
\
\
- I \
80\
\
-
80
\
\
I
ns \
\
I
\
\
\
\
I 90 \ ns \
\
\
\
\ ns \
I
\
\
\
-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPl84C01F
ITEM
I (*). IMIN .1 TYP.IMAX.1 UNIT I
1
1
1
I
I
RESET set-up time for
I
I 601 - I - I ns I
__+-______+--'c;...:1.:;o..::.ck;;.:....;r;...:i;.;;:s..:;e_ _ _ _ _ _ 1
I
I
I
I
I
I
I
I
I
I
RESET hold time from
I
I 101
I ns I
clock rise
I
I
I
I
I
I
--~----------~==~~~--------I
INT set-up time for clock I
rise
I
--~----------~~~------------I
I
I
I
I
80 I
I
I
1
I
- I ns I
I
I
1
I
1
INT hold time after c10ckl
I 101
ns
rise
I CL= I
I
~~~~~~~~-~MT~.~o-u-tP-u-t~(I~IL~I~I)~d-e7fl~·n~i-t--e I
1-5~6~5~1--~r--r-n-stime prior to IORQ fall 1100pFI
I
~~~~~~~~-~D~e~1=a-y~f~r~o~m~c1~o~c~k~fa~1~1~t--o I
1---;I---~1~8~5-r-n-slOR ""L"
I
I
I
I
~;;--+-:-;-;:-;'"=;::::-""'-;--;D~e:.:;l""a-y....:f:=-r-o-m--cc1-:-o-c7k-r-:-is-e--:"t--o I
I
1
I 85
ns
IORQ="R"
I
I
I
I
--;:c;--+-:-;-:==-=----r-:D:-"e~l"'"ay---;f=-r-o-m-c-=l'--o-c"'-k-;:"fa-=1C-:1---:I - I - 1150
ns
to- 1
data
output
I
I
I
I
_ _+-_ _ _ _ _-+-==-=.::.==---_ _ _ _ _ 1
I
1(2** I
Clock (CLK) restart time I
by INT (STOP mode)
I
I
--;-------+-----------1
Clock (CLK) restart time I
by NMI (STOP mode)
I
_ _+-_ _ _ _ _+-_ _ _ _ _ _ _ _ _ _ 1
I
I
I
I
I
I
I
- 114+ I
12.5)1
IxTccl
1(2**1
114+ I
12.5)1
IxTccl
I
I
1
Clock (CLK) restart time I
by INT (IDLEI/2 mode)
I
I
I
I 2.51
ITcC I
__~----------+_----------------II
II
Clock (CLK) restart time I
by NMI (IDLEI/2 mode)
I
I
I
I
I
54
TRSTlI
TRST2I
55
Note 1.
Note 2.
4.4
4.5
I
I
1
I ns
I
I
1
1
I ns
I
I
I
I
- I 2.51
ITcC I
I
ns
I
'-1-
- I ns
I
I
Test conditions
VIR = 2.4V, VIL = 0.4V, VIRC = vec - 0.6V, VILC = 0.6V
VOR = 2.2V, VOL = 0.8V
Items with an asterisk (*) are non-compatible with NMOS Z80.
Capacitance
The capacity of TMPZ84C01F is alike with that of the TMPZ84COOP.
details refer to the relative part of the TMPPZ84COOP.
For
Timing diagram
Figs. 4.1 to 4.10 show the basic timings of respective operations.
Numbers shown in the figures correspond with those in the AC Electrical
Characteristics Table in 4.3.
-
94-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C01F
TECHNICAL DATA
AO-A15
DO-D7
Fig. 4.1
Operation Code Fetch Cycle
T3
AOAl~
I
[Rii
OPERATION
MAD
DOD?
WRITE
OPERATION
[ViR
DOD?
---t=~~
Fig. 4.2
Memory Read/Write Cycle
-
95-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COIF
TECHNICAL DATA
AO-A7
IOR~
'@
WAIT
RD
@
INPUT
OPERATION
\
OUTPUT
OPERATION
DOD7
WR
'I
1
DOD7
(Note)
DATA OUTPUT
f
wait state (TW*) is inserted automatically by MPU.
Fig. 4.3 Input/Output Cycle
Note 1 TL is the final state of the preceding instruction.
Note 2 2 wait state (TW*) is inserted automatically by MPU.
Fig. 4.4
Interrupt Request/Acknowledge Cycle
-
96-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COl F
TECHNICAL DATA
FINAL M CYCLE
TL
Ml
T3
11
T4
T5
-- - -- ------ ----=
NMI
~--~--------~
AO-A15
(Note)
REFRESH ADDRESS
NMI is asynchronous input but in order to assure the positive response in the following cycle, NMI trailing edge signal must be
generated keeping abreast of the leading edge of the preceding TL
state.
Fig. 4.5 Non-maskable Interrupt Request Cycle
¢
DO-Lo
Note
Note 2
~=*=
TL is the final state of any machine cycle.
Tx is optional clock used by requested peripheral LSI.
Fig. 4.6
Bus
Request/Acknowledge Cycle
-
97-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84COIF
HALT COMMAND'S
141
T4
I
141
I
Tl
T2
T3
T4
loll
Tl
T2 .
"":~
~-.---------------
mIT
(Note)
INT signal is also used for releasing from the halt state.
Fig. 4.7
Halt Asknowlege Cycle
Ml
AD-A15
00-07
Ml
MREq.RD.WR
IORQ.BU8ACK
HALT
______________~I
I
-----------,""~----~(~(----------------~~--------
17777/1
Fig. 4.8
-
\'-_ __
Reset Cycle
98-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COl F
TECHNICAL DATA
T4
Tl
T2
T3
CLK
~---
-U
!~:
j
Fig. 4.9
Clock Restart Timing (STOP Mode)
Tl
T2
eLK
(IDLE 1 MODE)
CLK
(IDLE2 MODE)
INT
--T
NMf
Fig. 4.10
'tJ
~)
.1
I
I
([?)
J
I
Clock Restart Timing (IDLE1!2 Mode)
-
99-
T3
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
5.
TMPZ84C01F
Outline Drawing
Unit in mm
rIItt
O.8PITCH
n-----------------.-
'1
o
..,tI
10
....
14.0±O.1
( 17.6±O.3)
1.~5
MARK
J
,//1
(0.6 )
~-1
J
M
-<
:>I
(l.2±O.2 )
to
r:
'"
1
..
.-.
to
....
c:i
15.2±O.3
-100-
..;
....,
(
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
6.
TMPZ84C01F
Precautions
(1)
To reset MPU, it is necessary to hold RESET signal input at "0" level for
at least 3 clocks.
In particular, to release the HALT state by RESET signal in STOP Mode,
hold ~ signal at "0" level for sufficient time in order to stabilize
output from the internal oscillator.
(2)
In releasing MPU from the HALT state by interrupt signal in IDLEl/2 Mode
and STOP Mode, MPU wi 11 not be re leased from the HALT state and the
internal system clock will stop again unless an interrupt signal is
accepted during the execution of NOP instruction even when the internal
system clock is restarted by the interrupt signal input.
In particular,
care must be taken when INT is used.
Other precautions are identical to those for the TMPZ84COOP except those
for RFSH termial. Refer to the data sheet for the TMPZ84COOP.
-101-
INTEGRATED CIRCUIT
TOSHIBA
TECHNICAL DATA
TMPZ84C01F
-102-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl0AFnMPZ84Cl0AF-6
TMPZ84ClOAP, *TMPZ84ClOAP-6, TMPZ84ClOAF, *TMPZ84ClOAF-6
CMOS Z80 DMA:
1.
Direct Memory Access Controller
General Description and Features
The TMPz84ClOA (hereinafter referred to as DMA) is CMOS version of Z80 DMA
(Direct Memory Access Controller) which provides low power consuming but
powerful and versatile operations.
This DMA is designed to improve system performance by allowing the system
memory and peripheral LSI's to directly transfer data between them.
Memory-to-memory and I/O-to-I/O (I/O devices as peripheral LSI or I/O
devices such as printer, etc.) data transfer capability is also provided.
The DMA is fabricated using Toshiba's CMOS Silicon Gate Technology.
The principal functions and features of the DMA are as follows.
(1) Compatible with the Zilog Z80 DMA.
(2) DC to 4MHz operation (TMPZ84ClOAP/TMPZ84ClOAF)
DC to 6MHz operation (TMPZ84ClOAP-6/TMPZ84ClOAF-6)
(3) Single SV power supply: SV+lO%
(4) Data transfer rate 2M bytes/sec. (at 4MHz), 3M bytes/sec. (at 6MHz)
(5) Data transfer in max. 64K byte block length.
(6) Address generation with incrementing, decrementing, or fixed address
by source and destination.
(7) Built-in daisy chain structure interrupt circuit.
(8) Low power consumption
SmA Typ. (SV,4MHz)
6mA Typ. (SV,6MHz)
lOuA MAX.
(SV, stand-by)
(9) Extended operating temperature
-40'C to 8S'C
(10) Transfer, search, or transfer/search operations can be specified.
(11) Byte, burst or continuous modes can be specified.
(12) Bit maskable byte searching function.
(13) Avai lab Ie m standard 40-pin dual-in-line package and 44-pin mini
flat package.
Further, in the following text and explanations for charts and tables,
hexadecimal numbers are directly used without giving an identification to
explanation of address, etc. to the extent not to cause confusions.
* Under development.
(Note)
Z80(R) is a registered trademark of Zilog Inc., U.S.A.
-103-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C1 OAP/TMPZ84Cl OAP-a
TMPZ84C1 OAF/TMPZ84C lOAF-a
TECHNICAL DATA
2.
Pin Connections and Pin Functions
The pin connections and I/O
TMPZS4C10A are shown below.
2.1
pin
names
and
brief
functions
of
the
Pin connections
The pin connections of the TMPZSOC10A are as shown in Fig. 2.1.
1
2
3
A5
A4
A3
A2
A1
•
AO
.0
A5
39
.\7
38
HI
lIf
3'7 nrf/~Ji;
36 IW
30 DO
6
Cl~
iffi
fIT,
10
~
12
13
14
BAt
~15
26
27
1>6
1>7
26
M1
~ifAT'l'
16
25 HIJY
A15
A14
17
18
2,
A6
A13
A12
19
20
23
22
21
"0
lUI
""'"
.1CV
'"
""'
"
'"
'"
D.
'1
!rol
Il!1rnJIi:;
=
>R
DO
Dl
33 D2
32 1)3
31
30 vSS(OV)
2. D5
•
~
"
.
3.
I!L
.,
DO
°S"····"·"O
.~olo!«««1
>'
>'
DMA
Fig. 3.6
(1)
(2)
1
1
1
1
1 3] 1
1
1
1
1
>1
1 5] 1
1<_ _ 1
1
1
I/O
1J
2J
3]
I/O
4J
5J
Trnasfer between
memory and I/O
Transfer between
memories
Trnasfer between
I/O and I/O
Memory search
I/O search
Transfer paths of DMA
Transfer between memory and I/O
This is the most ordinary method of data transfer and data transfer with
the high speed serial interfaces (Z805IO, etc.) is possible.
Transfer between memories
This method of transfer is used for relocation of the memory content and
high speed transfer of voluminous data between memories.
In addition,
this method is used to support memory mapped I/O.
It is possible to
program to make ROY conditions active for this type of data transfer.
The same function as that of LDIR command (block transfer command) of the
Z80 MPU is provided.
Number of clocks required by MPU for transfer of
data of single byte is 21 clocks in case of the LDIR command while it can
be processed in 4 clocks when DMA is used (in case of 2 cycle variable
timing). Further, when DMA is used, approx. 420 clocks are required for
initialization but in transfering data of 25 bytes or above, DMA becomes
advantageous.
-110-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
(3)
TMPl84Cl OAP/TMPl84Cl OAp·6
TMPl84Cl OAF/TMPl84Cl OAF·6
Transfer between I/O and I/O
This method of transfer can be used in such applications as
of real time data requiring temporary storage of input
instance, in transfering data from a diskette to a line
program only starts the DMA operation and data is tranferred
I/O.
However, if I/O error occurred, its recovery becomes
Further, when there is a byte equality, it is possible to
various operations by the search function.
acquisition
data.
For
printer, a
from I/O to
necessary.
branch into
(4)
Memory search
This memory search is used to search a large quantity of data at high
speed. The same function as that of CPIR command (sarch command) of the
Z80 MPU is provided.
Number of clocks required by MPU for single byte
memory search is 21 clocks when the CPTR command is used while the search
is possible in 2 clocks (in case of 2 cycle variable timing) when DMA is
used.
Further, approx. 376 clocks are required for initialization when
DMA is used and therefore, DMA is advantageous for memory search of more
than 19 bytes.
In addition, the search of special bytes in the end of
block and character check block is also possible.
(5)
I/O Search
This is used for search of special bytes in the end of block and
character check block.
For instance, this is used for search of a file
mark showning a file delimiter on a magnetic tape.
3.2.8.2 Operating classes
There are 3 kinds of basic operation classes for DMA.
2 out of these 3
kinds are further divided into 2 classes.
In addition, the ports
referred to here denote the data source and destination.
(1)
Data transfer between 2 ports
Transfer
Data transfer path in the flow of readout cycle followed by write
cycle. This is executed without external logic circuit between DMA and
MPU.
21 Simultaneous transfer
Data transfer path for simultaneous read and write of data tranferred
between ports by generating required control signal through use of an
external logic circuit.
2 times of efficiency of the transfer only
class is obtained.
11
(2)
11
(3)
11
Search of special bit pattern in byte at one port
Search
This is a method to search special bit pattern by comaparing data read
from the source port with a matched byte.
The matched byte is masked
by another byte and can be compared with a special bit pattern (a
certain bit in bytes).
Data transfer between 2 ports and search
Transfer/search
Data transfer is performed in the same transfer method as that of the
only transfer class and at the same time, the same search as that for
the search only class is performed.
-111-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl DAP/TMPZ84Cl DAN
TMPZ84Cl DAF/TMPZ84C 1DAF·6
TECHNICAL DATA
21
Simultaneous transfer/search
Data transfer is performed in the same transfer method as that of the
simultaneous transfer class and at the same time, the same search as
that for the search only class is performed.
In this case, an external logic circuit is required.
3.2.8.3 Operation modes
In the transfer methods for various operation classes, DMA can select the
following modes:
o Byte mode
o Burst mode
o Continuous mode
The single byte transfer/search is shown in Fig. 3.7 (commonly applicable
to all modes).
CASE OF TRANSFER
o CONTINUITY
o
BUS RELEAS E
o INTERRUPT
Fig. 3.7
Single Byte Transfer/Search
The data transfer is started at the point of time when DMA is enabled.
In the first single byte operation in any mode, ROY signal is first
checked to determine if it is active.
-112-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl0AP/TMPZ84Cl0AP-6
TMPZ84Cl OAF/TMPZ84Cl OAF-6
TECHNICAL DATA
Then, the bus request is made and single byte transfer/search is
performed when DMA becomes the bus master.
The same operation is
continued until the end of block judgement is made. If it is not the end
of block, however, a different operation is carried out after judgement
of RDY signal.
The operations in respective modes are as shown in Fig.
3.8, 3.9 and 3.10.
(1)
Byte mode
In the data transfer operation of DMA, the system bus control right is
released whenever 1 byte is transferred at a time and the system bus
control right is returned to MPU for at least one machine cycle period.
If RDY signal of DMA is active when one machine cycle passes after the
system bus control right is returned to MPU, the bus request is made
again to MPU and next one byte data transfer is performed. Further, when
RDY signal is non-active, the system bus control right is retained by
MPU.
This operation is shown in Fig. 3.8.
NO
EXECUTE OVER CPUl
MACHINE CYCLE
NO
o INTERRUPT
o BUS RELEASE
o AUTOMATIC RESTART
Fig. 3.8
Byte Mode
-113-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
(2)
TMPZ84Cl OAP/TMPZ84Cl OAp·6
TMPZ84C10AF/TMPZ84Cl0AF-6
Burst mode
In the burst mode, after one byte data is transferred, RDY signal is
checked to determine if it is active whithout abandoning the system bus
contral right.
If RDY signal is active, data transfer is continued until
RDY signal becomes non-active and after the data transfer is completed,
DMA stops to operate. Since MPU is ready to operate during the period in
which I/O device does not transfer data (when RDY signal is non-active),
data transfer rate and bus using efficiency are effective.
This operation is shown in Fig. 3.9.
Fig. 3.9
Burst Mode
-114-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl OAF/TMPZ84Cl OAF-6
TECHNICAL DATA
(3)
Continuous mode
When the data transfer is commenced, DMA retains the system bus control
right until the transfer of last byte of a data block is completed or the
stop condition of RDY signal becomes non-active during the operation, DMA
is simply put in the idle state and still retains the system bus control
right while waiting that RDY signal becomes active again. What must be
taken care of Is that if number of data bytes is smaller than that set in
the byte counter, DMA cannot end the block transfer forever and the
system is impeded to operate properly.
This operation is shown in Fig. 3.10.
DMA ENABLE DATA
START
THANS¥'j~R
NO
YES
NO
o INTERRUPT
o BUS RELEASE
o AUTOMATIC RESTART
Fig. 3.10
Continuous Mode
-115-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl DAP/TMPZ84Cl DAP-6
TMPZ84Cl DAF/TMPZ84Cl DAF-6
TECHNICAL DATA
3.2.8.4 Transfer speed
Shown in Table 3.1 are the comparison of max. transfer rates in 5
transfer classes of DMA operation and that of max. transfer rates in
block transfer command of MPU.
The max. speed transfer rate is
accomplished in the simultaneous transfer operation of DMA and at least
one external logic circuit is required. DMA transfers shown in the table
are based on the assumption that interruption is not involved in the
burst or continuous mode, and that the read and write cycle is 2 cycles.
Table 3.1
Transfer and Search Max. Speed (Burst and continuous modes)
Operation
Simultaneous transfer
of DMA
DMA search only
Simultaneous transfer/
search
DMA transfer
DMA transfer/search
Block transfer command
of MPU
Z-80
(4.0 MHz)
Z-80
(6.0 MHz)
2M byte/S
3M byte/S
1M byte/S
1.5M byte/S
0.200M byte/S
0.300M byte/S
Shown in Table 3.2 is the comparison of the Z80 throughput reduction rate
(per transfer K baud) in the byte mode of data transfer by DMA with the
throughput reduction rate in the byte transfer using the interrupt
service routine by six commands (actual minimum) by MPU.
The DMA
transfer in this data is based on the assumption that read and write
cyc Ie timing is longer than 2 cyc les (min.). Therefore, MPU throughput
reduction rate in the 2 cycle simultaneous tranfer is further reduced.
Table 3.2
Z-80 MPU throughput reduction per DMA transfer K baud
(byte mode)
Z-80
(4.0 MHz)
Operation
DMA transfer
DMA transfer/search
MPU transfer by interrupt
Z-80
(6.0 MHz)
0.041%
0.027%
0.2l3%
0.142%
3.2.8.5 Operating conditions
Programmable conditions to get DMA perform certain operations and these
operations are shown in Table 3.3 (a) and (b).
The conditions referred
to here are those conditions for the internal registers of DMA, signals
from peripheral LSI I S and commands to DMA on the data bus.
For details
refer to Table 3.3 (a) and (b).
-116-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAp·6
TMPZ84Cl0AF/TMPZ84Cl0AF·6
TECHNICAL DATA
Table 3.3
(a) Operating Conditions
Conditions
Operations that can be caused
under conditions at left hand
a. Bus release
b. MPU interruption
c. Automatic restart
End of block
Table 3.3
(b) Operating Conditions
Conditions
Coincidence of byte
Pulse control byte coincided
with low order byte of byte
counter
ROY signal ~s active
ROY signal is non-active
RETI command (interruption
return command from MPU)
Operations that can be caused
under conditions at left hand
a. Bus release
b. MPU interruption
c. Continuation
a. Pulse generation
Bus request
MPU interruption
Bus release
Breaking (in case of
continuous mode)
a. Bus request
a.
b.
a.
b.
3.2.8.6 Automatic restart
In DMA data transfer, it is possible to automatically clear the byte
counter, load the content of the start address register on the address
counter again and restart the data transfer at the end of block.
The automatic restart function can reduce a burden of software on MPU in
the CRT refresh or repeating operation.
In addition, it is possible to
write a different start address into the buffer register during the data
transfer (when ROY signal is non-active and the bus is released during
the data transfer in the byte mode or burst mode).
At this time, it
becomes possible to commence the automatic restart of data transfer from
a new start address.
3.2.8.7 Variable cycle
DMA is capable of changing readout and
programming. This function is effective in
and reducing a burden on a software, and an
omitted. Refer to 3.3.2 (2) (i) where this
write cycle lengths through
increasing data transfer rate
external logic circuit may be
function is described.
3.2.8.8 Pulse generation
DMA generates pulse signal on the INT line for every 256 bytes
transfer. This is described in detail in 3.3.2 (2) (k).
3.2.9
Interrupt
DMA is able
conditions:
to make
an
interrupt
request
-117-
to MPU
under
the
for data
following
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl0AF/TMPZ84Cl0AF-6
TECHNICAL DATA
o
After DMA's RDY signal becomes active and before DMA makes a bus
request (BUSREQ .. "0").
When the content of the byte counter coincides with that of the block
length register and the end of block is detected.
When the content of the coincided byte masked by the mask byte
coincides with data in the transfer or search period when the byte
coincidence is formed.
o
o
To make an interrupt request to MPU, it is necessary for DMA to release
the bus.
If DMA is the bus master, signal on the INT line generates
periodic pulses to the peripheral LSI's, which are not sensed by MPU.
Therefore, at the end of block or after stop by byte coincidence, DMA
releases the bus before interrupting MPU.
If interrupt at the end of block and automatic restart at the end of
block are set for DMA by programming, an interrupt is taken place at each
end of block (at this point of time, it is acknowledged for the
continuous operation).
If the automatic restart is programmed in this
case, the status flag at the end of block is not set.
In this case, the
interrupt vector cannot determine a factor for that interrupt.
the Z80 system, interrupt is controlled through the daisy chain
sys tern.
For the interrupt daisy chain, refer to 3.2.7 Interrupt/
Priority Circuit.
In addition, for the interrupt timing, refer to 3.3.2
On
(2)
3.3
(j).
Status change flowchart and basic timing
The status change flowchart and the basic data transfer tlm1ng by DMA are
shown here. The status change flowchart is shown in 3.3.1 and the basic
timing in 3.3.2.
3.3.1
Status change flowchart
,-------,
o CON'!lNUITY
o BUB I'.ELl'~BE
o IN'1'mRRUf'T
to Fig. 311(0)
Fig. 3.11 (a)
Status Change Flowchart
Fig. 3.1l(b)
-118-
Status Change Flowchart
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
BYTE MODE
l3UHST MODE
TMPZ84Cl OAP/TMPZ84Cl OAP-&
TMPZ84Cl0AF/TMPZ84Cl0AF-&
caNT 1 NUOUS MODE
BUSRF}t = 0
(Note)
The details for single byte transfer/search is shown in Fig. 3.ll(b)
Status Change Flowchart.
Fig. 3.11 (c)
Status Change Flowchart
-119-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl OAF/TMPZ84C 1OAF-6
TECHNICAL DATA
3.3.2 Basic timing
When DMA receives a command from MPU or reads the readout register, MPU
has the system bus control right, BUSACK = "1", and MPU is called the bus
master. When DMA operation is data transfer by DMA proper, BUSACK = "0",
and DMA gets the system bus control right and becomes the bus master.
(1) When the bus master is MPU:
(a) Write timing into the write register
To write data into the write register, it is necessary for 3 signals of
CE, IORQ and WR to become "0" simultaneously at the rising edge of
clock.
At this leading edge, DMA latches these 3 signa Is.
After
latched, CE, IORQ and WR signals may change to the invalid level after
certain hold time. Further, DMA writes the status of the data bus (DO
to D7) into necessary write registers at the rising edge of next clock.
CE,IORq,WH
DATA IN DO TO D7 ARE
SIONALS ARE LATCHED
WRITTEN.
Fig. 3.12
(b)
Write Timing into the Write Register of DMA
Readout timing from the readout register
To readout the readout register it is necessary that 3 signals of CE,
IORQ and RD are at "0" and stable for more than 2 clocks.
At the
rising edges of 2 clocks, the status data is on the data bus and kept
as long as CE, IORQ and WR signals are active.
eLK
,.-----
"
\...I-----t-J'- - - - - - - - -
Fig. 3.13
I
Readout Timing from the Readout Register of DMA
-120-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl DAP/TMPZ84Cl DAP-6
TMPZ84Cl DAF/TMPZ84C 1DAF-6
TECHNICAL DATA
(2) When DMA is the bus master:
(a) Transfer
Transfer and transfer/search operations are performed at the same
timing.
Data is latched at the rising edge of RD signal (in case of the
standard timing, the falling edge of T3 state) and held on the data bus
during next wri te cyc Ie.
After RD signa I becomes "1", the data bus
buffer of DMA is enabled.
The standard timing is 3 clock cycles for the memory operation while it
is 4 clock cycles for the I/O operation.
In addition, in the I/O
operation, the t1m1ng is 4 clock cycles including TW* which is
automatically inserted between T2 and T3 state.
When CE/WAIT signal is programmed as "Multiplex" in the write regiser
WR5, DMA samples the status of this signal at the falling edge of T2 in
case of the memory readout and at the falling edge of TW* in case of
the I/O write.
If WAIT signal is at "0" level at this time, DMA
inserts one clock cycle (Tw) and if it is at "1" level, proceeds to
next cycle. Further, when Tw is inserted, WAIT signal is sampled again
during this period and the same processing is performed.
o
Memory to I/O
I/O WRITE CYCLE
MEMORY READ CYCLE
T2
T2
T3
TW*
CLK
-
I
X
I
I
I
MEMORY ADDRESS
I
r£
I/O ADDRESS
READ
\
I
WRITE
r
r
!--
I
I
!--
I
\
\
J
+---IJ-~---- I- - -
Fig. 3.14
-
- -
-
DATA BUS IS DRIVED BY DMA
--- -
-
---:jJj\J---t-
- - - -
- - - -
Transfer Standard Timing of Memory to I/O
-121-
--
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl OAF/TMPZ84Cl OAF·6
TECHNICAL DATA
In the memory readout, DMA put the memory address on the memory bus (AO
to AS) in the period of T 1 rise and bring MREQ and RD signa Is to "0"
level at the falling edge of TI state.
The memory data is read out at
this point of time, put on the data bus (DO to D7), latched by DMA at
the falling edge of T3 immediately before the rise of RD signal, and
when RD signal becomes "1" level, DMA data bus buffer is enabled and
the latched data is output on the data bus.
In the I/O write cyle, DMA put I/O address on the address bus in the Tl
rise operiod, makes IORQ signal and WR signal to "0" level in the T2
rise period, and writes the data on the data bus (data readout from the
memory) into I/O.
o
I/O to memory
In the I/O readout cycle, DMA put I/O address on the address bus in the
TI rise period and makes IORQ signal and RD signal to "0" in the T2
fall period.
I/O data is read out and placed on the data bus at this
time, and is latched by DMA at the trailing edge of T3 immediately
before the rise of RD signal.
When RD signal becomes "1" level, DMA
data bus buffer is enabled and the latched data is output on the data
bus.
I/O READ CYCLE
01
T3
MEMORY WRITE CYCLE
"\
Tl
CLK
I
I
=tX
READ
I/O
I
I
ADDRESS
I
I
MEMORY ADDRESS
{IORQ
RD
I
\
I
(
DATA BUS
IS
DRIVE~~
r-
~
WRITE {MREQ
WR
===---jYI'(
Fig. 3.15
--- ---
--
\.- J
]'C
f---
Transfer Standard Timing of I/O to Memory
-122-
---
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAp·6
TMPZ84Cl OAF/TMPZ84Cl OAF·6
TECHNICAL DATA
In the memory write cycle, DMA places memory address on the address bus
in the Tl fall period, makes MREQ signal to "0" level at the falling
edgE: of Tl and WR signal to "0" level in the T2 rise period, and write
data on the data bus (data readout from I/O) into the memory.
o
Memory to memory
This operation is a combined operation of the memory read cycle and
memory write cycle.
MEMORY READ CYCLE
Tl
1'2
T3
MEMORY WRITE CYCLE
Tl
1'2
1'3
CLK
-+_J}-+--+-~f----(DA1'A
- - - - - [ .....1-
-
-
---
Fig. 3.16
o
BUS. IS DRrVED BY DMA
--- ---j-rhl-t---tI"\.... --- _______ J
Transfer Timing of Memory to Memory
I/O to I/O
This operation is a combined operation of the I/O read cycle and I/O
write cycle.
eLK
DO-.o.,
Fig. 3.17
Transfer Timing of I/O to I/O
-123-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl OAF/TMPZ84Cl OAF·6
TECHNICAL DATA
(b)
Search timing
The search operation is identical to the readout only operation and
data is only read into DMA register for comparison with coincided byte.
The timing of search operation is identical to that of memory to I/O
transfer shown in Fig. 3.14 and that of I/O to memory transfer in Fig.
3.15.
(c)
Simultaneous transfer
The simultaneous transfer operation and the simultaneous transfer/
search operation are performed in the same timing.
When DMA is programmed in the search only mode, the read and write
cycles are generated in one read cycle (source port readout period).
Since only one address is generated on the address bus, the memory or
I/O control signal is generated using an external logic circuit and DMA
operation is performed according to this control signal. In addition,
I/O ports are selected by hardware during the operation. Signals with
(EXT) shown in Fig. 3.18 through Fig. 3.21 are those generated by an
external logic circuit.
o
Memory to I/O (Memory search cycle)
In this data transfer, the memory search mode is programmed and the
memory readout and I/O write are performed in one read cycle by
generating IORQ signal and WR signal in the memory readout cycle using
an external logic cir·cuit. The hardware performs the memory readout by
MREQ signal and RD signal that are output by DMA and the I/O write by
IORQ signal and WD signal that are generated using an external logic
circuit.
READ/WRITE CYCLE
T2
T1
T3
eLK
Ao- A15
READ
[
MR~
RD
DO- D7
WRITE
[""'",,,
DATA BUS IS DRIVED
BY MEMORY
WR(EXT)
-r,-'--
_/
Fig. 3.18
Simultaneous Transfer Timing of Memory to I/O
(Memory research timing)
-124-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl0AF/TMPZ84Cl0AF-6
TECHNICAL DATA
o
I/O to memory (Memory search cycle)
In this data transfer, the memory search mode is programmed and the I/O
read and memory write operations are performed in one readout cycle by
generating IORQ signal and WR signal in the memory readout cycle using
an external logic circuit. The hardwaer performs the I/O readout using
RD signal output by DMA and IORQ signal generated by an external logic
circuit and the memory write using MREQ signal generated by DMA and WR
signal produced by an external logic circuit.
READ/'WRI TE CYCLE
Tl
T2
T3
CLK
AO - A15
IoIRE«
WRITE
RD
READ
Do - D7
IOR,,(EXT)
WR(EXT)
CE/WAIT
Fig. 3.19
--- --
--------
'- ---------
Simultaneous Transfer Timing of I/O to Memory
(Memory research timing)
o
Memory to I/O (I/O search cycle)
In this data transfer, the I/O search mode is programmed and the memory
read and I/O write operations are performed in one readout cycle by
generating MREQ signal and WR signal in the I/O readout cycle using an
external logic circuit. The hardwaer performs the memory readout using
RD signal output by DMA and MREQ signal generated by an external logic
circuit and the I/O write using IORQ signal generated by DMA and WR
signal produced by an external logic circuit.
o
I/O to memory (I/O search cycle)
In this data transfer, the I/O search mode is programmed and the I/O
read and memory write operations are performed in one readout cycle by
generating MREQ signal and WR signal in the I/O readout cycle using an
external logic circuit.
The hardwaer performs the I/O readout using
IORQ and RD signals output by DMA and the memory write using MREQ
signal and WR signal produced by an external logic circuit.
-125-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84C10AF/TMPZ84C10AF-6
TECHNICAL DATA
READ/WRITE CYCLE
C[,K
WRITE
READ
MRE"CEXT)
WR(EXT)
(Note)
Although addresses on AO - A15 are originally I/O addresses, they
are handled as memory addresses.
Fig. 3.20
Simultaneous Transfer Timing of Memory to I/O (I/O search timing)
~EAD/WRITE
I
T1
CYCLE
T3
T2
~I
eLK
WR~
MRE"CEXT)
- --- ffi- - ----__
J
I '---------
(Note)
Although addresses on AO - Al5 are originally I/O addresses, they
are handled as memory addresses.
Fig. 3.21
Simultaneous Transfer Timing of Memory to I/O (I/O search timing)
-126-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl0AF/TMPZ84Cl0AF-6
TECHNICAL DATA
(d)
Bus request timing
When RDY signal becomes active, DMA samples RDY signal at the rising
edge of the clock and if the bus is not full (BUSREQ = "I") DMA makes
BUSREQ signal to "0" level at the rising edge of next clock and request
MPU to hand over the system bus control right.
MPU samples BUSREQ signal at the rising edge of the last state clock of
the machine cycle which MPU is executing at that point of time and if
it is "0", makes BUSACK signal to "0" level at the rising edge of next
clock.
Therefore, maximum value of a time required for MPU to hand over the
bus control right to DMA (BUSACK = "O") after DMA detected that RDY
signal becomes active is the sum of one machine cycle (variable) and
one clock period of MPU.
When detecting that BAI (BUSACK) signal is at "0" level for 2 clock
period, DMA start the DMA action. There is the delay time of max. One
machine cycle + 3 clock period after RDY signal becomes active till the
DMA action is actually started.
MACHINE CYCLE OP MPU
I--J
FINAL STATE
CLK
RDY
BAr(BUSACK)
EXECUTE DMA
Fig. 3.22
(e)
Bus Request Timing
OIIERATION
Bus release timing - byte mode
In the byte mode, DMA makes BUSREQ signa 1 to "1" level at the n.S1ng
edge of the clock immediately before end of each data transfer cycle
(the end of readout cycle in the search operation and the end of write
cycle in the transfer and transfer/searach operation.)
Although BUSREQ signal becomes "1" before the end of DMA cycle by one
clock, MPU resumes the operation one clock after BUSREQ signal becomes
"1" level and therefore, there will be no trouble.
After the bus is released, next bus request is made at the leading edge
of the clock immediately after both BUSREQ signal and BAI signal
becomes "1" level. RDY signal being active is the conditions for this.
DMA CYCLE
'I
CLK~
BUSREQ.
IIA I (
iiUiiiiCK )
Fig, 3.23
BUB Release Timing - Byte Mode
-127-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAp·6
TMPZ84C1 OAF/TMPZ84C 1OAF·6
TECHNICAL DATA
(f)
Bus release at the end of block in the busrst mode or continuous mode
When it is programmed to stop DMA at the end of block in the burst mode
or continuous mode, BUSREQ signal is set to "1" level at the rising
edge of the clock at the end of last data transfer. This last data is
transferred even when RDY signal becomes non-active.
CLK
RDY
MPU IS
BUS MASTER
TRANSFER OF FINAL BYTE
Fig. 3.24
(g)
Bus Request Timing - at End of Block
Bus release when coincidence is detected in the burst mode or
continuous mode
When DMA is set in the burst mode or continuous mode and programmed to
stop its operation at byte coincidence, DMA stops to operated when the
byte coincidence is detected.
Since DMA operation is pipe lined and the advance reading is performed,
a check to determine if the n th data coincides with the coincidenced
byte is carried out at the· same time when the n + 1 st data is
transferred. Therefore, data of N + 1 byte is transferred and BUSREQ
signal is set to "1" level at the leading edge of the clock when this
transfer ended.
CLK
",-
RDY
DATA TRANSFER OF Nth BYTE
Fig. 3.25
(h)
-
- -
-
- - - -
-
-
"----------
DATA TIlANSFER OF n+lth BYTE
COINCEDENCE IS DETECTED IN
Nth BYTE
Bus Release Timing - Byte Mode
Bus release when RDY signal is non-active
If RDY signal becomes non-active in the burst mode, BUSREQ signal is
set to "1" level at the rising edge of next clock after end of the byte
operation that is under execution at the time. For instance, this is
done when the read of the search only or simultaneous transfer/search
operation ended or when the write of the transfer/search operation
ended. Therefore, the action for BUSREQ signal is slightly behind the
action for RDY signal.
-128-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84Cl OAP/TMPZ84Cl OAp·6
TMPZ84Cl0AF/TMPZ84Cl0AF·6
DMA always does not release the bus until the byte action at
is completed.
the time
In contrast with this, in the continuous mode BUSREQ signal is kept at
"0" level even when RDY signal becomes non-active.
In addition, after the byte action at the time ended DMA is put in the
idle state until RDY signal becomes active again.
This figure is shown in Fig. 3.26.
CLK
ACTIVE
RDY
\~----------------------
------------------------------D-M-A--C-Y-C-L-E-----------.~r·::, '~"'"
Fig. 3.26
Bus Release Timing when RDY Signal becomes Non-active
Timing of RDY signal with other signals are shown in Figs. 3.27, 3.28
and 3.29.
In these figures the memory search only operation by the Z80
standard timing by mode is assumed.
In each of the operation modes,
RDY signal is sampled at the rising edge of the last clock of the read
or write cycle to determine its level.
RDY signal can become non-active before completion of the last byte
operation without affecting its operation.
In the byte or burst mode,
BUSREQ signal and BAI signal are set to "1" at the end of byte
operation of RDY signal.
In the byte or burst mode, the bus control
signals (MREQ, IORQ, RD, WR) are also kept at "1" level as long as RDY
signal is non-active.
Further, the address bus and data bus are kept
in 3 state.
The continuous mode differs from other modes in that the address bus
holds an address which is incremented in advance against next byte
during the period when RDY signal is non-active.
This address can be
used immediately after RDY signal becomes active again.
-129-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl OAF/TMPZ84C 1OAF-6
TECHNICAL DATA
RDY
BUSREQ,
BAr
DO-D7
~II---------III----{\,__ _ _ _ _ _ _ _ _ __
~l
/
---If-
....J/
__
----I~J---{\'__
__---I/
----Q---ff---I?------Q- - --- - - --
Fig. 3.27
RDY
r~f-f
Timings of RDY signal with other signals
--it-----t---t---t--,.
--Q---Q-Fig. 3.28
Timings of RDY signal with other signals (Bus mode)
-130-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84C 1OAp·6
TMPZ84Cl0AF/TMPZ84Cl0AF·6
TECHNICAL DATA
RDY
BUSREQ
---f
(------+----11------.1
r
r
~r---------_r-------+------_+----~r--------------------
X
>-
MRF-Q
DO-D7
Fig. 3.29
(i)
---ir--
---fj----
-0-- -0---
Timings of RDY signal with other signals (Continuous mode)
Variable cycle
When programmed, DMA is capable of changing read and write cycle
lengths. Source and destination can be programmed independently by the
write register WRI (designation of Port A) and WR2 (designation of Port
B). This variable cycle function allows the read or write in 2, 3 or 4
clock cycles (more clock cycles if Tw is inserted) and further, can
increase or decrease pulse widths of all signals generated by DMA.
Four signals relative to the data transfer; MREQ, IORQ, RD and WR
signals have the function to end the rising edge timing earlier by 1/2
clock independently.
Differing from the standard timing, in the variable cycle mode IORQ
signal becomes active earlier than MREQ, RD and WR signals by 1/2
clock. Further, CE/wAIT signal can be used in the extension of 3 or 4
clock cycle variable memory cycle and 4 clock cycle variable I/O cycle
only.
In the 3 or 4 clock cycle memory operation, CE/I,AIT signal is
sampled at the T2 falling edge while it is sampled at the T3 falling
edge in the 4 clock cycle I/O oppration.
In the 2 clock cycle
operation it is not sampled.
Use of this vari.able cycle is effective
in increasing data transfer rate and reducing software burden and
further, can eliminate an external logic circuit.
In addition, this
function provides more faster memory read/write speed than normal
speed.
-131-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl0AF/TMPZ84Cl0AF-6
TECHNICAL DATA
T2
Tl
T3
T4
CLK
,------+---1--.'(r'------+---tJ 'r,
' -_ _ _ _-1.1_
~
7--I
,
I
L_-' __
L_
,r ,- -, -,,
MREQ, - - - - - - . ,
'----+,--
RD,WR
"' r
../ '--
I
I
__ ..L_
t
I
'--
1
2CYCLE
3CYCLE
END IN EARLY
2 CYCLE
4CYCLE
END IN EARLY
3 CYCLE
END IN EARLY
4 CYCLE
Variable Cycle
Fig. 30
Tl
L_
-,,
..L_
'I
T2
. I"
T3
'I~
T4
CLK
CE/WAIT
(3 CYCLE AND 4 CYCLE
MEMORY OPERATIONS)
CE/WAIT
(4 CYCLE I/O
OPERATION)
=== =-_-_-_-_-~\~C -=-~l==-~=:::::::: === =~-=
Fig. 31
(j)
,..-----------\
I
--'----'----
------------~
- - - - - - - - - - -WAIT
SamJ~ Ie
----
----
in Variab Ie Timing
Interrupt
The timing for the interrupt acknowledge or return from interrupt is
identical to that of other z80 peripheral LSI's. INT signal is sampled
by MPU at the rising edge of the last clock of all commands.
If the
interrupt enable is not set by the internal MPU software or when BUSREQ
signal is active, this INT signal is not accepted. When INT signal is
accpeted, IORQ signal also becomes active at the same time (normally,
MREQ signal) in the period of its Ml cycle, indicating that the
interrupting LSI can load its 8-bit vector on the data bus.
At the
same time, two wait status are automatically inserted into this cycle.
This is to facilitate execution of the priority interrupt mechanism and
the wait status of 2T gives a stabilizing time to lEI and lEO signals
and thus, it becomes possible to identify which peripheral LIS will
react.
-132-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAp·6
TMPZ84Cl OAF/TMPZ84Cl OAF·6
TECHNICAL DATA
FINAL M CYCLE
IN COMMAND
Ml
FINAL T
STATE
CLK
---l
Tl
T2
TW*
TW*
T3
~~~~~~
-- - - - - - - - ---- ----- ! - - - - ===~-_L - - - - -- - -- ----- 1------ - - - - X
n---------
XREFRESH
PI"'
J
\
/
INPUT
-
-----
--
----
-----
----- t-----
----
Fig. 3.32
----
----
---------
tr\-==
-----
-----
Interrupt Acknowledge
Interrupt on RDY signal (interrupt before the bus request) does not
directly affect BUSREQ signal. The process in this case is carried out
by giving following commands to the write register WR6 in the interrupt
service routine.
o
o
o
(k)
Enable after interrupt return (B7H)
DMA enable (87H)
Execution of RETI command to reset IUS latch during the interrupt
service in the Z80 DMA (ED4DH)
Pulse generation
In the pulse generation, INT signal is set to "0" level (pulses are
generated on the INT line) every 256 bytes after offset value is loaded
to the write registger WR4 by the program.
INT signal is put to "0" level during the DMA cycle in which pulse
control bytes coincide with low order bytes of the byte counter and
kept at "0" level in the full period of trans fer cycle.
Here, the
transfer cycle means the read cycle (the search only or simultaneous
transfer operation) or read/write cycle and lengths of the read and
write cycles can be set independently by variable cycle.
-133-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84Cl QAP/TMPZ84Cl DAP-6
TMPZ84Cl OAF/TMPZ84Cl DAF-6
OLK
INT
(PULSE OUTPUT)
Fig. 3.33 (a)
Pulse Output {Standard timing at the time of transfer}
OLK
INT
(PULSE OUTPUT)
Fig. 3.33 (b)
(1)
lJ
Pulse Output (Standard timing at the time of memory search)
Precautions
Transfer timing
Although the DMA transfer timing is basically identical to the read/
write timing of the Z80 MPU, care is required when variable cycle is
used or in case of simultaneous transfer.
In the case of simultaneous transfer, all addresses which are output by
DMA are interpreted to be memory addresses and I/O are selected by the
hardware using an external logic circuit.
It is normally programmed
that I/O addresses are fixed and memory addresses are updated during
the DMA operation.
At this time, DMA controls memory addresses and
outputs I/O select signal using an external logic circuit.
-134-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl0AF/TMPZ84Cl0AF·6
TECHNICAL DATA
2]
Memory refresh
Since DMA has no refresh signal output function, the refresh of a
dynamic RAM is performed normally using RFSH signal of MPU.
If the
transfer period becomes long in the DMA operation using the burst mode
or continuous mode, another refresh method must be used.
3]
Pulse generation
When the pulse generating function is used for transfer in the byte
mode, pulse output is generated in two times.
This is to avoid BAI
signai from becoming non-active and MPU from being put in HALT state.
Further, when offset value and low order 8 bits of the block length are
equal other, pulse is once generated and after DMA operation is
completed, pulse is generated during the read cycle of the 1st byte
when the DMA operation is performed again without changing the offset
value.
TRANSFER CYCLE OF
TRANSFER CYCLE OF
Nth BYTE
(N+l}th BYTE
CLit
I
BUS~
BAl
""\
I
\
TIi'f/PifLsE
Fig. 3.34
3.4
r--
\
I
r
\
\
I
Pulse Generation Timing (at Byte mode)
Peripheral commands
To operate DMA, specify its operations hy writing into the control
register group through programming.
In addition, the status of DMA can
be known by reading the contents of the status register group.
To give effect to this on a program, write the operation into the write
register by OTIR or OUT command to MPU and read out by INIR or IN
command. In both cases, output of the 110 address decoder to DMA becomes
"0" level. This output is connected to the CE/WAIT pin.
The configurations of the control register group and status register
group are as follows:
(1)
1]
2]
3]
4]
5]
6]
7]
Control
Write
Write
Write
Write
Write
Write
Write
register
register
register
register
register
register
register
register
group
WRO
WR1
WR2
WR3
WR4
WR5
WR6
-135-
TOSHIBA.lNTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl0AF/TMPZ84Cl0AF-6
TECHNICAL DATA
( 2)
Status register group
Readout register RRO
2] Readout register RRI
3] Readout register RR2
41 Readout register RR3
5] Readout register RR4
6] Readout register RR5
71 Readout re.gister RR6
1]
3.4.1
Control register group
The control registers consist of 7 groups of WRO to WR6, each of which
consists of a basic register and related registers.
If the pointer bit
of the basic register is "1", related registers are accessed by turns.
The basic registers WRO to WR6 are identified by the combination of bits
0, 1, 2, 6 and 7. There may be pointer bits for related registers. BBH
(followed by the readout mask) command of WR6 has no pointer bit but data
that follows this command is limited to the readout mask.
(1)
Write register WRO
WRO is idnetified by the condition that Bit 7 of the basic register is
"0" and Bit 1, 0 are other than both "0".
WRO has 4 pointer bits, each of which has related registers,
respectively.
(a)
Basic register bit 0, 1 (Designation of operating class)
Bit 0 and" 1 designate the operating class; transfer, search only, and
transfer/search operaitons.
In addition, simultaneous transfer or
transfer/search is obtained by selecting search and generating a proper
bus control signal for complete transfer through external hardware.
D7
Basic register
I
I
0
D6
I
I
D5
I
I
D4
I
I
D3
I
D2
I
DI
I
I
I
I
0
1
DO
I
I
0
0
0
1
1
0
1
1
Data transfer mode
Don I t use
Transfer
Search
Transfer/search
Data transfer direction
Port B ---) Port A
Port A ---) Port B
v
Related register #0
Port A Start address
(Low order 8 bits)
v
Related register #1
Port A Start address
(high order 8 bits)
-136-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84Cl0AP/TMPZ84Cl0AP-6
TMPZ84Cl OAF/TMPZ84C 1OAF-6
v
Related register 1F2
Block length
(low order 8 bits)
v
Related register 1F3
Block length
(high order 8 bits)
Fig. 3.35
Write Register WRO
(b)
Basic register bit 2 (Designation of data transfer direction)
Data transfer direction is designated when the source port and
destination port at time of the transfer only operaiton by Bit 2.
In
the search only operation, the source port only is designated and in
the simultaenous transfer or transfer/search operation, the destination
port is decided by external wiring.
(c)
Basic register bit 3 - 6 (Pointer bits)
Bit 3 - 6 are the pointer bits which are used to designate four related
registers following respective bits.
(d)
Related register #0, #1 (Port A start address)
These registers are accessed by Bit 3 and 4 of the basic register byte.
When Port A is used as a source or destination, it is necessary to
write the start address.
Low order bytes are written into #0 and high
order bytes in #1.
(e)
Related register #2, #3 (Block length)
These registers are designated by Bit 5 and 6 of the basic register.
Max. 64K bytes can be designated by writing low oreer bytes of block
length into 1F2 and high order bytes into 1F3.
However, as data read is
pipe 1 ine type, number of bytes ac tually searched or trans ferred is
more than that entered here by 1 or 2.
In addition, if "zero" is set
for these registers, the transfer or search of 2**16+1 bytes is carried
out.
(2)
(a)
Write register WRl
WRI is idnetified by the condition that all of Bits 0,
basic register are "0" and Bit 2 is "1".
1 and 7 of the
Basic register bit 3 (Port A designation)
A memory is designated by Port A when "0" is written for Bit 3, while
I/O is designated when "1" is written.
This designation makes the
control signal (MREQ or IORQ) active against the cycle including this
port.
-137-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C.l0AP/TMPZ84Cl0AP-6
TMPZ84Cl0AF/TMPZ84Cl0AF-6
TECHNICAL DATA
D7
Basic register
D6
10 1
1 1
DS
D4
1
1
D3
D2
1
1
1
1
1
1
1
o
0
0
0
1
0
1
1
1
D1
0
1
DO
0
I
1
Designation of Port A
Port A
Memory
Port A
I/O
Port A address update
Decrement
Increment
Address fix
v
0
Related register ifoO
0
Port A variable
timing byte
o
o
1
1"0"1"0"1"0"
1 1 1
1 1 1
WR
RD MREQ
Fig. 3.36
o
1
o
1
IORQ
Cycle length
4 clock
3 clock
2 clock
Don't use
Early end
Write Register WR1
(b)
Basic register Bit 4, 5 (Fixed or variable address designation)
Fixed or variable Port A address is designated by Bit 4 and Bit 5 for
each transfer or search byte.
(c)
Basic register Bit 6 (Pointer bit)
When Bit 6 is set to "1", next re lated regis ter is acces sed.
In
addition, when Bit 6 is set to "0", DMA's variable cycle is not used.
(d)
(3)
Related register #0 (Port A variable timing byte)
By setting values for this register, Port A cycle length
signal timing can be designated.
oBit 0, 1 (Cycle length)
Length of data transfer cycle (memory read/write, I/O
relative to Port A is designated.
Timing can be changed
of 2 - 4 clocks.
oBit 2, 3, 6, 7 (Early end)
The t1m1ng of the control signal IORQ, MREQ, RD and
advanced by 1/2 clock.
and control
read/write)
in a range
WR
can
be
Write register WR2
WR2 is idnetified by the condition that all of Bits 0, 1, 2 and 7 of the
basic register are "0"
-138-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl OAF/TMPZ84Cl OAF-6
TECHNICAL DATA
Ba~ic register bit 3 (Port B designation)
A memory is designated by Port B when "0" is written for Bit 3, while
I/O is designated when "1" is written.
This designation makes the
control signal (MREQ or IORQ) active against the cycle including this
port.
D7 D6 DS D4 D3 D2 Dl DO
Basic register
10 1 1 1 1 10 10 10
(a)
1
1
1
1
1
1
v
Related register #0
1
Designation of Port B
Memory
Port B
Port B
I/O
0
0
0
1
Port B address update
Decrement
Increment
0
1
1
1
0
o
o
1
Address fix
Port B variable
timing byte
o
o
1"0"1"0"1"0"
1 1 1
1 1 1
WR
RD MREQ
Fig. 3.37
I~
1
1
o
1
o
Cycle length
4 clock
3 clock
2 clock
Don't use
1
I
IORQ
Early end
Write Register WR2
(b)
Basic register Bit 4, 5 (Fixed or variable address designation)
Fixed or variable Port B address is designated by Bit 4 and Bit 5 for
each transfer or search byte.
(c)
Basic register Bit 6 (Pointer bit)
When Bit 6 is set to "l", next re lated register is accessed.
In
addition, when Bit 6 is set to "0", DMA's variable cycle is not used.
(d)
Related register #0 (Port B variable timing byte)
By setting values for this register, Port B cycle length
signal timing can be designated.
a Bit 0, 1 (Cycle length)
Length of data transfer cycle (memory read/write, I/O
relative to Port B is designated.
Timing can be changed
of 2 - 4 clocks.
oBit 2, 3, 6, 7 (Early end)
The timing of the control signal IORQ, MREQ, RD and
Rdvanced by 1/2 clock.
-139-
and control
read/write)
in a range
WR
can
be
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
(4)
TMPZ84Cl OAP/TMPZ84Cl OAp·6
TMPZ84C lOAF/TMPZ84Cl0AF·6
Write register WR3
WR3 is identified by the condition that both Bit 0 and Bit 1 of the basic
register are "0" and Bit 7 is "I".
(a)
Basic register Bit 2 (Stop on match)
This bit is used for the search or transfer/search operation.
When
this bit is "I" and trans ferred data matches the match byte, the da ta
transfer is stopped and the bus is released. When this bit is "0" and
transferred data matches the match byte (if DMA is not stopped even
when they matched), the status flag is set on the status byte to allow
interrupt resulting from byte match.
(b)
Basic register Bit 3 (Pointer bit)
When this bit is set at "I", the mask byte follows the basic register.
(c)
Basic register Bit 4 (Pointer bit)
When this bit is set at "I", a match byte follows the basic register.
This bit designates a match byte used for comparison with all data to
be searched.
(d)
Basic register Bit 5 (Interrupt enabled)
When this bit is set at "I", DMA interrupt is enabled.
(e)
Basic register Bit 6 (DMA enable)
When this bit is set at "I", DMA operation is enabled and a bus request
can be made to MPU.
(f)
Related register #0 (Mask byte)
This register is accessed by basic register Bit 3.
It is possible to
write a mask byte required for the search operation.
The mask byte is
capab Ie of masking the match byte (data to be compared) during the
search operation to extract bits to be compared.
When all bits of the mask byte are at "0", the comparison is made and
when they are at "1", the masking is made.
In addi tion, if no masking
is required and all bits are compared, write OOH mask byte.
(g)
Related register #1 (matche byte)
This register is accessed by basic register Bit 4.
The match byte is
used as data to be comapred when the data transfer mode is search or
transfer/search. The match byte is masked by the mask byte of related
register #0.
-140-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C 1OAP/TMPZ84Cl OAP-6
TMPZ84Cl0AF/TMPZ84Cl0AF-6
TECHNICAL DATA
I
I
Bas ic regis ter
D7
1
D6
I
I
D5
I
I
D4
D3
I
I
I
D2
I
I
I
DMA Enab Ie : 1
D1
I
I
0
DO
I
0
I
Stop on match
Interrupt enable : 1
v
Related register #0
(mask byte)
o
Comparison
v
Related register #1
(match byte)
Fig. 3.38
(5)
(a)
(b)
(c)
Write Register WR3
Write register WR4
WR4 is identified by the condition that both Bit 0 and Bit 7 of the basic
register are "I" and Bit
is "0".
Basic register Bit 2 - 4 (Pointer bit)
When these bits are set at "1", the related
accessed after the basic register.
registers 41'0
to 41'2 are
Basic register Bit 5, 6 (Operation mode designation)
Operation mode selected values can be set for Bit 5 and Bit 6.
values to be set, refer to Fig. 3.39.
For
Related register #0, #1 (Port B start address)
These registers are accessed by basic register Bit 2 and Bit 3.
Related register #0 designates low order byte of Port B start address
while related register #1 designated high order byte of Port B.
Further, if low order 8 bits are sufficient for Port B start address,
the loading to related register #1 is not required.
Related register #2 (Interrupt control byte)
Thi.s register control DMA interrupt or pulse generation.
By setting
Bit 3 and Bit 4, related registers #3 and #4 cao be accessed.
o Bit 0 (Interrupt on match)
When Bit 0 is set at "1", DMA generates interrupt if transferred data
matches the match byte in the search or transfer/search operation.
a Bit 1 (Interrupt on end of block)
When Bit 1 is set at "1", DMA generates inter"cupt if a value of the
byte counter becomes "0" in DMA operation.
a Bit 2 (Pulse generation)
When Bit 2 is set at "1", pulse is generated on the INT line whenever
data in number of bytes set on the pulse control byte is transferred.
-141-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84Cl0AP/TMPZ84Cl0AH
TMPZ84Cl OAF/TMPZMCI OAF-e
oBit 3, 4 (Pointer bits)
When Bit 3 is set at "1", pulse control byte is accessed after
interrupt control byte.
When Bit 4 is set at "1", the interrupt vector is accessed.
oBit 5 (Vector value change by status)
When this bit is set at "1", interrupt vector value changes according
to cause for generating interrupt. However, if the automatic restart
or interrupt at the end of block was already set, this mode cannot be
used.
oBit 6 (Interrupt on RDY)
When this bit is set at "1", DMA generates interrupt prior to the bus
request if it detects that RDY signal has become active. Therefore,
the interrupt enable command becomes necessary and when RETI command
is executed after the interrupt enable of WR6 (B7H) is sent out, the
bus request is started.
(e)
Related register #3 (Pulse control byte)
When Bit 3 of the interrupt control byte is set at "1", the pulse
control byte is accessed after the interrupt control byte.
The pulse
control byte gives offset values to pulse that are first generated
(Number of bytes shown by this control byte).
The pulse control byte
compares low order 8 bits of the~te counter and if both coincide each
other, pulses are output on the INT line.
(f)
Related register #4 (Interrupt vector)
When Bit 4 of the interrupt control byte is set at "1", the interrupt
vector is accessed after the interrupt control byte.
The interrupt
vector is loaded on the data bus at time of the interrupt acknowledge
by MPU (IORQ = "0", Ml = "0"). If Bit 5 of the interrupt control byte
is set at "1", Bit 1 and Bit 2 of the interrupt vector change according
to the interrupt factor.
However, when the automatic restart and
interrupt on the end of block has been already programmed, the
interrupt vector sent out at the end of block does not change and
therefore, the mode for vector value change by status cannot be used.
-142-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TM PZ84C lOAF/TM PZ84C 1OAF-6
TECHNICAL DATA
D7
Basic register
D6
I 1 I
I
I
Designation of
data transfer mode
Byte mode
Continuous mode
Burst mode
Don't use
D4
DS
I
I
0
0
1
I
I
D2
D3
Dl
DO
I 0 I 1
I
I
I
I
I
I
0
1
0
1
v
Port B Start address
(Low order 8 bits)
Related register 410
v
Related register 411
Port B Start address
(High order 8 bits)
v
Related register #2
Interrupt control
byte
0
Interrupt on RDY : 1
Vector value change
by status
1 : Interrupt on match
: Interrupt on end
I
of clock
1 : Pulse generation
v
Related register 413
Pulse control byte
v
Related register 414
Interruption vector
0
0
1
1
Fig. 3.39
(6)
0
1
0
1
Interrupt on
Interrupt on
Interrupt on
Interrupt on
end of block
RDY
match
end of block
match and
Write Register WR4
Write register WRS
WRS is identified by the condition that Bit 1 and 7 of the basic register
are "1" and Bit 0, 2 and 6 are "0". WRS has no related register.
oBit 3 (Effective polarity of RDY signal)
When this bit is set at "0", RDY signal becomes "0" and active, and
when it is set at "I", RDY signal becomes "1" and active.
-143-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl0AF/TMPZ84Cl0AF-6
TECHNICAL DATA
oBit 4 (Use of CE/WAIT pin)
When this bit is set at "a", CE function only is available. When it is
set at "1", both CE and WAIT functions become available.
When BUSREQ
signal is at "1", CE function is available, while if BUSREQ signal is
at "0" level, WAIT function is available.
oBit 5 (Automatic register)
When this bit is set at "a" level, DMA operation is stopped at time of
the end of block (Byte counter = "Zero"). When it is at "I" level, the
contents of the address register and byte counter are automatically
loaded on the address counter and byte counter, and. DMA operation is
continued.
Basic register
D7
1
I
I
I
I
D6
0
DS
D4
I
I
D3
I
I
I
I
I
I
0
1
0
1
D2
0
Dl
1
I
I
I
I
DO
0
Effective polarity of RDY signal
Active at "0" level
Active at "111 level
Use of CE/WAIT
Uses only as CE function
Multiplex CE/WAIT
I
0
1
Fig. 3.40
(7)
(a)
Designation of automatic restart
Ends at time of the end of clock
Automatic restart
Write Register WR5
Write register WR6
and 7 of the bas ic
WR6 is idnetified by the condition that Bit 0,
register are at "I" level.
In the case of WR6, the functions (commands)
are divided by the combination of Bits 2 to 6.
Reset (C3H)
This command is used to reset DMA.
By executing this command, DMA
performs the followings;
o Disables the interrupt control circuit and bus request control
circuit.
o Releases the interrupt latch.
o Releases the forced RDY condition.
o Releases the automatic restart condition.
o Releases CE/WAIT function (Bit 4 WR5) and retians CE function only.
o Returns the timings of both Port A and B to the Z80 standard timing.
After turning power to DMA ON, and performing the programming, it is
necessary to execute the reset command once.
In addition, if the DMA
operation is interrupted during its execution, it is necessary to
execute the reset command 6 times successively (this is because there
are 5 related registers that are capable of directing in WR4).
-144-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84C1 OAP-&
TMPZ84Cl0AF/TMPZ84Cl0AF-&
TECHNICAL DATA
Further, DMA is not always reset completely by this reset command.
read sequence is reset only by the read sequence reset command.
(b)
(c)
The
Port A timing reset (C7H)
This command resets Port A variable
timing to the zao standard timing.
timing
byte
and
returns
Port
A
Port B timing reset (CBH)
This command resets Port B variable
timing to the zao standard timing.
timing
byte
and
returns
Port
B
(d)
Load (CFH)
When this command is excuted, the content of the address register is
loaded on the address counter and the byte counter is cleared.
In
addition, the internal forced ROY condition is also released.
Further, an address counter to which the loading can be made
immedaitely is the source port address counter only.
The loading to
the destination port address counter is made when a value of this
counter is initially updated (incremented/decremented) but if "address
if fixed", the loading is not performed.
However, the loading by the
"fixed address destination port programming" technique is possible.
If DMA becomes non-active when the load command is written, another DMA
control byte is written before the load command.
(e)
Continue (D3H)
Although this command clears the byte counter to "zero", both port
address counters do not change.
This command is used in trans ferring
several data blocks to continued positions in the many buffer if it is
desirable to know a break of every block, and continues DMA operation
which has been interrupted by detection of match at the end of block or
search. In order to execute this command, interrupt at the end of each
blocks is needed and new block length shall be entered in WRO with the
continue command.
In transferring data blocks, interrupt becomes necessary whenever
transfer of each data block ended.
In transferring next data block
after the interrupt, this continuity command is used instead of the
load command.
-145-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C1 OAP/TMPZ84Cl OAP-6
TMPZ84Cl OAF/TMPZ84C 1OAF-6
TECHNICAL DATA
D7
Basic register
D6
D4' 'D3
DS
I 1 I
I
I
I
I
I
I
I
I
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
Readout mask
I=Enble
D2
I
I
I
I
I
I
0
0
0
0
0
0
1
1
0
1
1
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
D1
0
I
DO
0
I
I
I
I
I Hexadecimal command name
0 C3
1 C7
0 CB
1 CF
0 D3
1 AF
0 AB
0 A3
1 B7
1 BF
0 8B
1 A7
0 B3
1 87
0 83
0 BB
Reset
Port A timing reset
Port B timing reset
Load
Continue
Interrupt disable
Inte.rrupt enable
Interrupt reset/disable
Post RETI enable
Read status byte
Status byte initialize
Read sequence start
Forced ROY condtion
DMA enable
DMA disable
Contiue readout mask
0
Status byte
Byte counter
(low order 8 bits)
Byte counter
(high order 8 bits)
Port A address counter
(low order 8 bits)
Port A address counter
(high order 8 bits)
Port B address counter
(low order 8 bits)
Port B address counter
(high order 8 bits)
Fig. 3.41
(f)
Write Register WR6
Interrupts disable (AFH)
This cOlmnand is used to simulate the z80 MPU' s interrupt acknowledge
when DMA is operated in a system other than the Z80 MPU.
When DMA
sends the interrupt signal into any MPU other than the Z80 MPU, if the
interrupt disable command is written into the beginning of the service
routine, INT signal returns to "1" level but next interrut signal of
DMA cannot be sent during the service routine is continuously carried
out.
Generation of next interrupt signal becomes possible when the
interrupt enable command is written into the end of the service
routine.
-146-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl OAF/TMPZ84Cl OAF-6
TECHNICAL DATA
(g)
Interrupts enable (ABH)
This is a command used on the Z80 system to enable the interrupt when
the power source is ON.
This command enables the interrupt control
circuit of DMA. When the interrupt disable command is not used, if the
interrupt enab le command is once written, next interrupt is enab led
automat ica lly when RETI command is executed at the fina 1 stage of the
interrupt service routine.
However, if the interrupt disable command
is used, it becomes necessary to write the interrupt enable command at
the final stage of the interrupt service routine.
(h)
Interrupt reset and disable (A3H)
This command is used on such systems as 8080 and 8085 to interface DMA
and MPU which is povided with the interrupt acknowledge function but
has no RETI command.
This command, when executed, performs the
followings:
o Reset of the in-interrupt service routine (IUS) latch
o Reset of the interrupt pending (IP) latch
o Release of the internal forced RDY signal conditions
o Succeeding interrupt disable by DMA (same as the interrupt disable
command)
(i)
Enable after RTEI (B7H)
This command is used only when "interrupt on RDY signal" is programmed
on WR4.
DMA, when detect ing that RDY signal becomes act ive, does not
make the bus request but generates the interrupt signal.
After the
interrupt return, this command enables DMA to make the bus request
again.
This command is always used to make the bus request after the
interrupt to RDY signal on the Z80 MPU system.
This command also can
be used on other MPU's, for instance, 8080.
The interrupt latch (lOR) to RDY signal is set during its interrupt
cycle.
This latch makes RDY signal active and DMA is not allowed to
make the bus request until this latch is reset by post-RETI enable
command.
The execution sequence of the Z80 MPU service routine is as follows and
the bus request is mode after RETI command is executed:
Post RETI Enable
DMA Enable
RETI Command
(j)
(k)
Read status byte (BFH)
This command indicates
access.
that
next
read
command
Status command initialization (80H)
This command indicates the reinitialization
status byte.
-147-
of
is
bit
the
4
status
and
5
of
byte
the
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl0AF/TMPZ84Cl0AF·6
TECHNICAL DATA
The reinitialization of the interrupt pending status (Bit 3) of the
st-atus byte can be effected by the interrupt acknoweledge, interrupt
process,
interrupt
reset
and
disable
command
wr1t1ng.
The
reiqitialization of DMA operation status (Bit 0) can be efected by the
load command.
(1)
Read mask continue (BBH)
This command denotes that next control byte which is to be written into
DMA follows the read mask register. The read mask register is used for
setting a new read sequence of RRO to RR6 and is normally a part of the
initial state setting when the power source for DMA is turned ON.
The read mask can be programmed by setting the related pointer bit of
register to be read out "1" level.
The read sequence start command is
used for initialization.
(m)
Read sequence initiote (A7H)
This command is used to initiate the read sequence pointer command as a
measures to access the first (in low order) read register that is
designated to be readable by the read mask for initialization of DMA by
next MPU read command.
Normally, this command is output to reset the
read sequence immediately after loading of the read mask.
(n)
Forced ROY (B3H)
In the burst mode or continuous mode, this command is used to make the
internal ROY conditions active for the active RDY signal by an external
logic circuit.
This command is used for memory-to-memory transfer or
memory search where ROY signal is not required.
It is not necessary to
consider the effective polarity of ROY signal. Use of this command can
eliminate an external logic circuit.
The forced ROY conditions are released
conditions:
o Reset command
o Load command
o Interrupt reset and disable command
o Ending by end-of-block
o Ending by byte match
o Bus release by DMA
by
the
following
commands/
(0)
DMA enable (87H)
This command is used to enable the bus control circuit of DMA.
The
interrupt circuit is not affected nor the function and latch are reset.
This bus request enable function is identical to that of Bit 6 of WR3.
In the interrupt service routine, DMA enable command is the last
command to DMA before MPU executes RETI command.
(p)
DMA disable (83H)
This command inhibits the bus reqllest by DMA.
This command is used to
stop DMA operation by external events, end-of-block or match by bytes
and when reinitialization of the status byte is required.
-148-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAp·6
TMPZ84Cl OAF/TMPZ84C 1OAF·6
TECHNICAL DATA
3.4.2
Status register group
There are 7 read registers RRO to RR6 avai lab Ie for DMA to know the
operation execution or end status.
The readout of MPU is made according to the method to access DMA as the
peripheral I/O using I/O command. Commands to be written into DMA are as
follows:
1] Read status byte (BFH)
2] Read sequence initiate (A7H)
3] Status byte rinitialize (8BH)
4] Read mask continue (BBH)
The above commands are those which are shown for WR6.
(1)
Read register RRO - Status byte
Bit 0 (DMA operation)
This bi t ind icat es if DMA made the bus reques t "after the last LOAD
command.
"1" indicates that DMA made the bus request while "0"
indicates no bus request made.
(b)
Bit 1 (ROY signal active)
"0" of this bit indicates that ROY signal is active.
signal being non-active.
(c)
Bit 2 (Don't care)
(d)
Bit 3 (Interrupt pending)
This bit indicates the interrupt
indicates the interrupt pending.
pending
(Ip)
"I" indicates ROY
latch
status.
"0"
(e)
Bit 4 (Match detection)
When this bit is "0", it indicates the match after the last status byte
reset or reinitialization command.
(f)
Bit 5 (End-of-block detection)
When this bit is "0", it indicates the end-of-block reached after the
last status byte reset, load, continuity or reinitialization.
(g)
Bit 6, 7 (Don't care)
(2)
Read register RRl, RR2 - Byte counter
The l6-bit counter consisting of two register RR1 and RR2 are cleared to
zero by the load, continuity or reset command.
When DMA starts the
transfer or search, the byte counter is incremented by one at the end of
each read cycle and judges the end-of-block by comparing with the program
content of the block length register (WRO) , when match is detected, DMA
operation is stopped.
If the pulse generation is used at this time, the
content of the WR4 pulse control byte is, after transferred, compared
with low order4 byte (RR1) of the byte counter.
-149-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl DAP/TMPZ84Cl DAN
TMPZ84Cl DAF/TMPZ84Cl DAF-6
TECHNICAL DATA
D7
PRO
D6
D5
* I * I
I
I
I
(*: Don't care) I
I
I
I
0
I
I
D4
D3
I
I
I
D2
I
I
I
D1
* II
I
DO
I
I
I 1
I
I
I
Status byte
: DMA operation is made.
0 : ROY signal active
:
Interrupt pending
0 : Match detection
End-of-block
I
I 0
RR1
Byte counter
(low order 8 bits)
RR2
Byte counter
(high order 8 bits)
RR3
Port A Address counter
(low order 8 bits)
RR4
Port A Address counter
(high order 8 bits)
RRS
Port B Address counter
(low order 8 bits)
RR6
Port B Address counter
(high order 8 bits)
Fig. 3.42
Read Register
(3)
Read register RR3, RR4 - Port A address counter
Write into the 16-bit counter consisting of two read registers RR3 and
Rr4 is made from WRO port A start address register by the load command.
Whenever one byte of DMA operation is carried out according to the
designated content of WRO, this counter is updated (incremented or
decremented) by one.
(4)
Read register RR5, RR6 - Port B address counter
The 16-bit counter consisting of two read registers RR5 and RR6 indicates
Port B address when D~ operation ended. Values in the port B address
register (WR4) are loaded into this counter by the load command and the
coutner is updated by one every time when DMA operation is carried out by
one byte. However, if address fix (Bit 4 and 5 of WR2) is programmed,
the counter does not change.
If Port A or Port B is a fixed address
destination port, in order to properly function the port it is necessary
to program as described for the fixed address destination port.
3.4.3
Address counter and byte counter values when DMA operation ended.
-150-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl0AF/TMPZ84Cl0AF-6
Values of these counters when DMA operation ended are shown in Table 3.4
(a) and Table 3.4 (b).
Tabte 3.4(a)
Values of those counters when DMA operation ended
Address
IValue ofl Number I
Address
I
I
Data I Data I block I of by tel Value I counter valuelcounter value I
format I tansferl length I to be lof by tel of source I of destina- I
I mode Iregisterl trans- Icounterl port
I tion port
I
ferred I
I
I
I
I
I
N+ 1 I
N
N I As -+ (N + 1)1 As + (N)
I Byte I
I
I
I
I
I
I
I
I
N+
ITransferl Burst I
N
N I As -+ (N + 1)1 As -+ (N)
I
I
I
I
I
I
I
I
I
N +
N
N
I
I
I Conti- I
I
I As -+ (N + 1)1 As -+ (N)
I
I nuity I
I
I
I
I
N+
N
N
I
I
I
I As + (N + 1)1
I Byte I
I
I
I
I
I
I
I
N +
N I As + (N + 1)1
I
I
I
I
I
N
I
I Burst I
I
I
I
I
N + 2*1 N + 1*IAs ! (N + 2)*1
I
I Search I
I
I
I
I
I
I
I
I
N+ 1 I
N I As ! (N + 1) 1
I
I
I
I
N
I
I Conti- I
I
I
I
I
N + 2*1 N + 1*IAs ! (N + 2)*1
I
I nuity I
I
I
I
I
I
I
I
I
AS: Start address *: The values when N+1 byte data is transferred and RDY
signal is active using 2-cycle variable timing.
Table 3.4(b)
Data
format
ITransferl
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I Search I
I
I
I
I
I
I
I
I
I
I
AS: Start
Values of those counters when DMA operation ended
Address
Address
Number I
I
I
Data
Byte no. I of by tel Value Icounter valuelcounter valuel
tans fer to be I to be lof by tel of source I of destina- I
mode
detected I trans- I counter I port
I
I tion port
I
I
I ferred I
I
M
Byte
M
As ! (M)
I MI
I
I As -+ (W-l) I
I
I
I
I
I
Burst
M
M
As ! (M) I As -+ (W-1) I
I
I MI
I
I
I
I
I
ContiM
M I MI As ! (M)--r- As -+ (W-l) I
1
nuity
I
I
I
I
Byte
M
M
I
I M1 As ! (M)
I
I
I
I
I
M
I
I As + (M + 1)
I M+ 1 I
Burst
M
I
I
I
I
M* I M - 1*1
As ! (M)*
I
I
I
I
I
I
M I As ! (M + 1)
I M+ 1 I
I
ContiM
I
I
I
I
nuity
M* I M - 1*1
As ! (M)*
I
I
I
I
I
I
address *: The values when match is detected and RDY signal
is
active.
-151-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl0AF/TMPZ84Cl0AF-6
TECHNICAL OAT A
3.4.4
List of command
D7
Basic register
D6
I 0 I
I
I
D4
D5
I
I
D3
I
I
I
D2
I
I
I
I
I
I
0
0
1
1
0
1
DO
Dl
I
0
1
0
1
Data transfer mode
Don't use
Transfer
Search
Transfer/search
Data transfer direction
Port B ---) Port A
Port A ---) Port B
v
Port A Start address
(Low order 8 bits)
Related register #0
v
Port A Start address
(high order 8 bits)
Related register #1
v
Related register #2
Block length
(low order 8 bits)
v
Related register #3
Block length
(high order 8 bits)
Fig. 3.35
Write Register WRO
-152-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl0AF/TMPZ84Cl0AF-6
TECHNICAL DATA
D7
Basic register
D6
10 I
1 1
DS
D4
I
I
1
D3
D2
I
1
1
1
1
0
1
1
1
1
Port A address update
Decrement
Increment
0
1
0
1
DO
I 0 I 0
Designation of Port A
Port A - Memory
Port A - I/O
1
0
0
Dl
1
Address fix
v
Related register #0
1
1
0
1
1
0
Port A variable
timing byte
1
o
o
1
1
o
o
1"0"1"0"1"0"
1 1 1
1 1 1
WR
RD MREQ
Fig. 3.36
I~
1
1
1
1
1
IORQ
Early end
Write Register WRl
-153-
Cycle length
4 clock
3 clock
2 clock
Don't use
TOSHIBA INTEGRATED CIRCUIT
.
TMPZ84Cl OAP/TMPZ84Cl OAp·6
TMPZ84Cl0AF/TMPZ84Cl0AF·6
TECHNICAL DATA
Bas ic re&is ter
D7 D6 D5 D4 D3 D2 D1 DO
1 0 1
I 1 I I 0 I 0 I 0
1
1
1
1
1
1
1
1
o
0
0
1
1
Designation of Port B
Port B - Memory
Port B - I/O
Port B address update
Decrement
Increment
0
1
0
Address fix
v
Related register #0
Port B variable
timing byte
1 0 1 0
1
1
o
o
1
1
1"0"1"0"1"0"
1
1
1
1
1
1
WR
RD MREQ
Fig. 3.37
D7
IORQ
o
1
o
1
Cycle length
4 clock
3 clock
2 clock
Don't use
Early end
Write Register WR2
DS D4 D3 D2 D1 DO
1
1
1
1
1 0 1 0
1
1
1
1
1
1
1
1
1
1
DMA Enable : 1 1
1 : Stop by coincidence
1
Interruption enable
1
Basic register
1
1
D6
1
v
Related register #0
(mask byte)
v
Related register #1
(match byte)
Fig. 3.38
Write Register WR3
-154-
o :
Comparison
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl0AF/TMPZ84Cl0AF-6
TECHNICAL DATA
D7
Basic register
D6
I 1 I
I
I
Designation of
data transfer mode
Byte mode
Continuous mode
Burst mode
Don't use
DS
D4
D3
I
I
I
I
I
I
o
o
0
1
o
D2
I
I
Dl
0
I
I
DO
I 1
I
1
1
v
Port B Start address
(Low order 8 bits)
Related register #0
v
Port B Start address
(High order 8 bits)
Related register #1
v
Related register #2
Interruption control
byte
0
I
I
I
I
I
Interrupt on RDY : 1
Vector value change
by status
1
1 : Interrupt on match
1 : Interrupt on end of
clock
Pulse generation
v
Pulse control byte
Related register #3
v
Related register #4
Interrupt vector
I
I
1
1
0
1
0
1
o
o
Fig. 3.39
Write Register WR4
-155-
Interrupt on
Interrupt on
Interrupt on
Interrupt on
end of block
RDY
match
end of block
match and
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl OAF/TMPZ84Cl OAF-6
TECHNICAL DATA
D7
06
I 1 I
I
I
Basic register
04
05
I
D3
I
I
02
0
I
I
I
I
I
Designation of automatic restart
Ends at time of the end of clock
Automatic restart
0
1
D7
D6
* II * II
D5
I
(*: Don't care) I
I
I
I
o
04
II
I
I
I
03
I
I
I
I
I
I 0:
I
Use of CE/WAIT
Uses only as CE function
MUltiplex CE/WAIT
0
1
PRO
DO
0
I
Effective polarity of RDY signal
Active at "0" level
Active at "I" leve 1
0
1
Fig. 3.40
I
I
I
01
1
I
Write Register WR5
02
DO
01
I * I
I
I
I
I
I
I
Status byte
I
I
I 1:
DMA operation is made.
0: RDY signal active
Interrupt pending
0: Match detection
End-of-block
Byte counter
(low order 8 bits)
RRI
I
RR2
_-'-_"'---.!.._-'----'__
-.1--'--
Byte counter
(high order 8 bits)
RR3
Port A Address counter
(low order 8 bits)
RR4
Port A Address counter
(high order 8 bits)
RR5
Port B Address counter
(low order 8 bits)
RR6
Port B Address counter
(high order 8 bits)
Fig. 3.42
Read Register
-156-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAp·&
TMPZ84Cl OAF/TMPZ84Cl OAF·&
TECHNICAL DATA
Basic register
I
I
D7
1
D6
D5
I
I
D4
I
I
D3
D2
I
I
I
I
D1
DO
I 0 I
I 1 I
I
I
0
1
I
I Hexadecimal command name
Readout mask
l=Enble
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
0
1
0
0
0
1
1
1
1
0
1
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
1
1
0
1
0
1
0
0
C3
C7
CB
CF
D3
AF
AS
A3
B7
BF
8B
A7
B3
87
83
BB
Reset
Port A timing reset
Port B timing reset
Load
Continue
Interrupt disable
Interrupt enable
Interrupt reset/disable
Enable after RETI
Read status byte
Status byte initialize
Read sequence start
Forced RDY condition
DMA enable
DMA disable
Continue readout mask
0
Status byte
Byte counter
(low order 8 bits)
Byte counter
(high order 8 bits)
Port A address counter
(low order 8 bits)
Port A address counter
(high order 8 bits)
Port B address counter
(low order 8 bits)
Port B address counter
(high order 8 bits)
Fig. 3.41
Write Register WR6
-157-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAPnMPZ84Cl OAP-6
.TMPZ84Cl0AFnMPZ84Cl0AF-6
TECHNICAL DATA
3.5
(1)
Method of use
Example of interface
As the method of use of DMA using the ZSO family, a simple example of the
ZSO system interface is shown below.
Fig. 3.43 shows the connection
employing the ZSOMPU, ZSODMA, ZSOPIO, and MEMORY.
II
CLOCK
OBNBRATOR
~
RMET
CIRCUIT
I
I
eLK
nEaPlT
"...
DO-D'7
l-
tt-
M
tz
IT-
llllll-
ff-
r-->'
1lI
Ilii:lXi
roRij
Irn
lIR
Jiii'Sii
YPU
t-
~
AO- A15
zeD
l-
BOSACK
f--
t-
tt-
l-
t-
ll-
I-I--
lll-
III-
"'"'~
lill-
BUSREQ
WAIT
00
m
IIALT
AO - A15
OO-In
~
MEMORY
iffi
WR
RYSH
+.v
I
+5'
oJ
~r-
DECODER
DO-In
BiiY
zeD
~
m
)'r-
eL'
v
AI
PAO- PA'7
DO-D7
zeD
ttt-
PI()
~
RD
PBO- Pll'7
1m
1lI
BRDY
m
BSTB
eLK
I1!1
V'v
1J!O
J
181
or
OTIIER PIlRIPHRRAL LSI
Example of ZSO System Interface
-158-
AftD!
ASTB
I-
tttt-
OF OTHBR DMA.
Fig. 3.43
AD
I--
rrr-
!iif
1&0
1 l
t;=
l-
Ml
RDY
~
r
I-I--
WR
1m!
I-
ll-
'IlIliii
ADDRESS
)
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl0AF/TMPZ84Cl0AF-6
On the Z80 system, signal lines of MPU and peripheral devices are
conneced almost directly. In Fig. 3.43, priority is in the order of DMA
and PIO. This is becuase the connection is made according to the daisy
chanin method which is peculiar to the Z80 system.
In the case of DMA,
especially, in order to operate as a bus controller, BUSACK signal, which
is the output of MPU, is input to BAI of DMA by the bus request daisy
chain. When several units of DMA are used, BAO is connect to BAI of DMA
which has tl>e next higher priority. Hardware can be easily connected as
shown in Fig. 3.43. In addition, memory mapped I/O also can be connected
to DMA.
(2)
Program example
As a program exmaple of DMA operation, an example of transfer from I/O to
memory using PIO is shown •
0020
0021
0030
2000
0100
DPIOB
DPIOB
DMA
DSTN
LENGTH
1000 '
1001'
1003'
1005'
F3
3E 10
ED 47
ED 5E
1007 '
1009'
100B'
100D'
3E
D3
3E
D3
4F
21
07
21
100F'
3E
06
D3
10
C3
06
30
FC
06
OE
21
ED
12
30
104E'
B3
STRT:
PIO
lOll'
1013'
lOIS'
1017'
1019'
10lB'
10lE'
1020'
1021'
FB
C9
. Z80
Z80 DMA DATA TRANSFER
I/O TO MEMORY
(PIO PORT B)
EQU
20H
EQU
+)DPIOB+1
EQU
30H
EQU
2000H
EQU
256
;DATA PIa CHANNEL B
;CONTROL PIO CHANNEL B
;DMA ADDRESS
;DESTINATION
; BLOCK LENGTH
ORG
DI
LD
LD
1M
; INTERRUPT MODE 2
1000H
A,lO
1,A
2
B INITIALIZATION
A,4FH
OUT
(CPIOB) ,A
LD
A,07H
OUT
(CPIOB) ,A
LD
DMA RESET
LD
LD
DMRT:
OUT
DJNZ
A,OC3H
B,06H
(DMA) ,A
DMRT
DMA INITIALIZATION
LD
B,DMAFIN-DMACTA
LD
B,DMA
LD
HL,DMACTA
OTIR
EI
RET
-159-
;MODE 1
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl DAP/TMPZ84Cl DAp·6
TMPZ84Cl DAF/TMPZ84Cl DAF·6
TECHNICAL DATA
;
INTERRUPT ON READY
HALT
1022'
76
lOR:
1023'
76
!OM:
1024'
1027'
1029'
102C'
102E'
1030'
1033'
1035'
CD
3E
32
06
OE
21
ED
C9
1037' IOE:
8B
0030
04
30
105C'
B3
1036'
76
lME:
1037'
1038'
1039'
103A'
103B'
103D'
103F'
1042'
1044'
1046'
1047'
1048'
1049'
104A'
l04B'
E3
D5
C5
F5
DD
FD
CD
FD
DD
F1
C1
D1
E1
FB
ED
SAV:
104D'
E9
RUN:
104E'
104E'
104F'
1050'
1052'
1054'
C3
7D
2000
OOFF
14
DMA COMMAND TABLE
PORT A - MEMORY
PORT B - PIO CHANNEL B
;
DMACTA EQU
$
DEFB
OC3H
:WR6
DEFB
7DH
:WRO
DEFW
DSTN
DEFW
LNGTH-1
DEFB
14H
:WR1
1055'
28
j
j
E5
E5
104D'
E1
E1
4D
INTERRUPT ON MATCH
HALT
INTERRUPT ON END OF BLOCK
CALL
SAY
10
A,8BH
LD
(DMA) ,A
LD
B,DMAFIN-DMACTB
C,DMA
10
LD
HL,DMACTB
OTIR
RET
INTERRUPT ON MATCH, END OF BLOCK
HALT
REGISTER SAVE
EX
(SP) ,HL
PUSH
DE
BC
PUSH
PUSH
AF
PUSH
IX
PUSH
IY
CALL
RUN
POP
IY
POP
IX
POP
AF
POP
BC
POP
DE
POP
HL
EI
RET!
j
JP
DEFB
(HL)
28H
-160-
:WR2
RESET COMMNAD
PORT A TO PORT B(TEMP)
DESTINATION ADDRESS
BLOCK LENGTH
PORT A - "INCREMENT"
ADDRESS
PORT B - "FIXED"
ADDRESS
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl0Af/TMPZ84Cl0Af·6
TECHNICAL DATA
10S6'
10S7'
10S8'
10S9'
AO
9S
20
32
DEFB
DEFB
DEFB
DEFB
OAOH
9SH
DPIOB
32H
10SA'
10SB'
FF
82
DEFB
DEFB
INTV-STRT
82H
10SC'
10SC'
10SD'
lOSE'
10SF'
1060'
CF
01
CF
87
EQU
DEFB
DEFB
DEFB
DEFB
EQU
OCFH
OlH
OCFH
87H
10FF'
1101 '
1103'
110S'
1022'
1023 '
1024'
1036'
DMACTB
DMAFIN
ORC
INTV:
DEFW
DEFW
DEFW
DEFW
END
:WR3
:WR4
ENABLE INTERRUPT
BYTE MODE TRANSFER
PORT B ADDRESS(L)
IOE,STATUS AFFECTS
VECTOR
:INTV INTERRUPT VECTOR
:WRS RDY ACTIVE "LOW" ,CEI
ONLY
$
$
STRT+OFFH
lOR
10M
IOE
lME
-161-
:WR6
:WRO
:WR6
:WR6
LOAD ADDRESS TO PORT A
PORT B TO PORT A
LOAD ADDRESS TO PORT B
ENABLE DMA
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
4.
ELECTRICAL CHARACTERISTICS
4.1
ABSOLUTE MAXIMUM RATINGS
TMPZ84Cl OAP/TMPZ84Cl OAN
TMPZ84Cl OAF/TMPZ84Cl OAF-6
I Symbol I
Item
I
Rating
, Unit I
vcc
i Supply Voltage
,
0.5 to +7
,
V I
I
1----------1-----------------------------------1--------------------1------1
I
VIN
I Input Voltage
I -0.5 to Vcc + 0.5 I
V I
1----------1-----------------------------------1--------------------1------1
I
PD
I Power Dissipation (TA=8S·C)
I
250
I mW I
I----------I-----------------------------------I~-------------------1------1
I TSOLDER I Soldering Temperature (10 sec)
j
260
I °c I
1----------1-----------------------------------1--------------------1------1
I
I
I
I
I
Tstg
I Storage Temperature
I
-65 to 150
I °c I
I
I
I
I
I
I
1----------1-----------------------------------1--------------------1------1
I Topr
I Operating Temperature
I
-40 to 85
I °c I
4.2 DC ELECTRICAL CHARACTERISTICS
TA = -40·C to 8s·C, VCC = SV ! 10%, VSS = OV
SYMBOL
VILC
VOL
PARAMETER
Low Clock Input
Voltage
High Clock Input
Voltage
Low Input Voltage
(Except CLK)
High Input Voltage
(Except CLK)
Output Low Voltage
VOHI
Output High Voltage
VOH2
Output High Voltage
ILl
Input Leak Current
ILO
Output Leak Current
VIHC
VIL
VIH
(1)
(II)
ICCI
Power Supply Current I
ICC2
Standby Supply
Current
Note (1) fCLK=l/TcC(MIN.)
I
I
I
,
I
I
(2)
TEST CONDITION ,
MIN. 'TYP.I MAX. UNIT I
I -0.3 , - '0.6
V I
I
I
I
I
V I
IVCC-0.6 , - IVCC+0.3
I
I
I
I
V I
I -0.5 I - , 0.8
I
I
I
I
I
2.2 I - I vcc
V I
I
I
I
lOL = 2.0mA
V I
I
I 0.4
BUSREQ only
I
I
I
3.2mA
I
I
I
I
lOH = -1. 6mA
I 2.4
I
'V I
I
I
I
I
IOH - -2S0uA
I VCC-0.8 - ,
, V I
I
I
I
I
VSS~ VIN~ VCC ,
I +10 , uA I
I
I
I
VSS + 0.4< VIN ,
+10 , uA I
~VCC
=
I
I
I
I
I
I
VCC-SV,'
,
,
I
5
7 I
I
fCLK=(l) IAP/AFI
VIHC=VIH= I
I
I
I
- P---6+'----i---:('""2~)T---('-:2~) I rnA I
VCC-0.2V I-A
VILC=VIL= II AF-61
6
10 I
I
0.2V
I
I
I
I
VCC=sV
VIHC ,
,
I
=VIH=VCC-0.2V I
10 I uA I
VILC=VIL=0.2V I
I
I
Preliminary
-162-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl OAF/TMPZ84Cl OAF-6
TECHNICAL DATA
AC ELECTRICAL CHARACTERISTICS
4.3
4.3.1
A.C. Characteristics (I)
When operate as peripheral devices (inactive state)
TA = -40·C to 8s·C, VCC = sv ! 10%, VSS = ov
NO.
SYMBOL
2
3
4
5
6
TcC
TwCh
TwCl
TrC
TfC
Th
7
TsC(Cr)
PARAMETER
Clock c;r:cle time
High clock Eulse width
Low clock ulse width
Clock rise time
Clock fall time
Hold time
-- -
IORQ, WR and CE signals
set-up time for clock
I
I
I
I
I
I
I
I
I
I
- I 380 I - 1300
Delay from RD rise to
data outEut
I
I
I
Data input set-up time
I
I
I
I
for clock rise (write
501 - I 30 I and M1 c;r:c Ie)
I
I
I
I
I
I
- I 1601 - 1100
Delay from IORQ fa 11 to
data output
I
I
I
(INTA c;r:cle)
I
I
I
I
I
I
- I 1101 - I 70
Delay from RD rise to
data bus float state
I
I
I
I
I
I
lEI set-up time for lORQ
140 I - 1100 I
fall
I
I
I
(INTA c;r:cle)
I
I
I
De lay from lEI rise to
I 160 I
I 70
lEO rise
I
I
I
Delay from lEI fall to
- I 130 I - I 70
lEO fall
I
I
I
I
I
I
Delay from M1 fall to IEOI - I 1901 - 1100
fall (When interrupt is I
I
I
I
generate~immediately
I
I
I
I
rise
8
TdDO(RDf)
9
TsWM(Cr)
10
TscfCDO)
11
TsRD(DZ)
12
TsIEI(IORQ)
13
TdIEOr (IElr)
14
TdIEOfCIEIf)
15
TdM1 (rEO)
before
16
TsMlfCcr)
17
TsMlr(Cf)
I PreIliminar;r:
I 4 MHz I 6 MHz I
I AP/AF IAP-6/AF-61--1
IMIN.IMAX.IMIN.IMAX.IUNITI
I 2501 DC 1165 I DC I ns I
I llol DC I 65 I DC I ns I
1 llol DC I 65 I DC I ns I
20
ns I
I - I 30
I - I 30 I - I 20 I ns I
01 - I 0 I - I ns I
I
I
I
I
I
I
I
I 1451 - I 60 I - I ns I
I
I
I
I
I
I
M1 c;r:cle.)
1
I
I
I
M1 signal set-up time fori 901
clock rise
I
I
1
I
Ml signal set-up time fori -101
clock fall
1
1
-163-
I
I
I
I
I 70
1
I
1-10
I
I
I
1
1
I
I
I
I
I
I ns I
I
I
I
I
I ns I
I
I
I
I
I ns I
I
I
I
I
I
I
I ns I
I
I
ns I
I
I
ns I
I
ns I
I
I
ns I
I
I
I
I
ns I
I
I
ns I
I
TOSHIBA INTEGRATED CIRCUIT
.
.
NO.
TECHNICAL DATA
SYMBOL
18
TsRD(Cr)
19
TdI(INT)
20
TdBAI r(BAOr)
21
TdBAIf (BAO f)
22
TsRDY(Cr)
TMPZ84Cl OAP/TMPZ84Cl OAp·6
TMPZ84Cl OAF/TMPZ84Cl OAF·6
I PreI
lliminar:r: I
I 4 MHz I 6 MHz I
I AP/AF IAP-6/AF-61--1
PARAMETER
IMIN.!MAX.IMIN.!MAX.IUNITI
I
I
I
I
I
I
RD signal set-up time fori 1151 - I 60 I - I ns I
clock rise (Ml c cle)
I
I
I
I
I
I
- 450 ns I
500
Delay from interruption
generation to INI fall
I
I
I
I
I
(at inactive state)
I
I
I
I
I
I
I
I
I
I
Delay from BAI rise to
- I 1501 - 1100 I ns I
BAO rise
I
I
I
I
I
I
!
I
I
I
- I 1501 - 1100 I ns I
Delay from BAI fall to
BAO fall
I
I
I
I
I
RDY signal set-up time
1001 - I 50 I - I ns I
for clock rise
I
I
I
I
I
4.3.2 A.C. Characteristics (II)
When operate as bus controller (active state)
TA = -40·C to 8S·C, vcc = SV ! 10%, VSS = OV
NO.
SYMBOL
7
TcC
TwCh
TwCI
TrC
TfC
TdA
TdC(AZ)
8
TsA(MREQ)
9
TsA( IRW)
10
TdRW(A)
11
TdRW(Az)
12
TdCf(DO)
2
3
4
5
6
I 4 MHz
I AP/AF
IMIN. IMAX.
Clock cycle time
I 2501 DC
High clock Eulse width
I 1101 DC
Low clock Eulse width
I 1101 DC
Clock rise time
I - I 30
Clock fall time
I - I 30
Delay of address outEut I - 1110
Delay from clock rise to I
1 90
address bus float state I
I
Address set-up time for 1 651
MREQ rise
I
I
(memor:r: cycle)
I
I
Addres~set-up time for
I
I
IORQ, RD, WR fall
I 180 I (I/O cycle)
I
I
Addr~s hold time from
I
I
RD, WR rise
I 901 I
I
Address hold time from
I
I
RD, WR rise
I 951 (at float state)
I
I
Delay from clock fall to I - 1150
data outEut
I
I
PARAMETER
-164-
I PreI
lliminar:r: I
I 6 MHz I
IAP-6/AF-6 1--1
IMIN. IMAX. IUNIT I
I 1651 DC I ns I
I 651 DcTMI
I 651 DC I ns I
I - I 20 1 ns I
I - I 20 1 ns I
I - I 90 I ns I
I - I 80 1 ns I
I
I
I
I
! 351
! ns I
I
I
I
I
I
I
I
I
I
I
I
I
I 110 I - I ns I
I
I
I
I
I
I
I
I
I 351 - I ns I
I
I
I
I
I
I
I
I
I 651 - I ns I
I
I
I
I
I - 1130 I ns I
I
I
I
I
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
NO.
SYMBOL
13
TdCr(DZ)
14
TsDI(Cr)
15
TsDI(Cf)
16
TsDO(WfM)
17
TsDO(WfI)
18
TsWr(DO)
19
20
Th
TdCr(Mf)
21
TdCf{Mf)
22
TdCr(Mr)
23
TdCf{Mr)
24
TwMI
25
26
TwMh
TdCf{If)
27
TdCr(If)
28
TdCr(Ir)
29
TdCf(lr)
30
TdCr(Rf)
31
TdCf{Rf)
32
TdCr(Rr)
33
TdCf(Rr)
TMPZ84C1 OAP/TMPZ84Cl OAP-6
TMPZ84Cl OAF/TMPZ84Cl OAF·6
I PreI
lliminarx I
4 MHz I 6 MHz I
I AP/AF IAP-6/AF-61--1
PARAMETER
IMIN.!MAX.IMIN.!MAX.IUN1TI
Delay from clock rise to I
! 90 ! - ! 70 ! ns I
data bus float state
I
I
I
I
I
I
(write cxc1e)
I
I
I
I
I
I
Data input set-up time upl 35 I
301 - ! ns I
to clock rise (read cycle I
I
I
I
I
in which RD ended at
I
I
I
I
I
clock rise)
I
I
I
I
!
Data input set-up time upl 50 I
401 - I ns I
to clock fall (read cycle
I
I
I
I
in which RD ended at
I
I
I
I
clock fall)
I
I
I
I
Data output set-up time
80 I
25 I
I ns I
up to WR fall
I
I
I
I
(memory cycle)
I
I
I
I
Data output set-up time
100 I
55 I
I ns I
up to WR fal1
I
I
I
I
I
(I/O cycle)
I
I
I
I
I
Data hold time from WR
70 I - I 30 I - I ns I
rise
I
I
I
I
I
Hold time
o ! - I o I - I nb I
Delay from clock rise to
I 70 I ns I
I 851
MREQ fal1
I
I
I
I
I
I
Delay from clock fall to I - I 851 - I 70 I ns I
MRE fall
I
I
I
I
I
I
clock rise to I - I 851 - I 70 I ns I
I
I
I
I
I
I
ns I
clock fall to I
851
I
I
I
I
I
I
1220 I - 1135 I - I ns I
Low MREQ Eulse width
I
I
I
I
I
I
1120 I - I 65 I - I ns I
ulse width
I
I
I
I
I
I
Delay from clock fall to I - I 85 I - I 70 I ns I
IORg fall
I
I
I
I
I
I
Delay from clock rise to I - I 75 I - I 65 I ns I
10RQ fal1
I
I
I
I
I
I
Delay from clock rise to I - I 85 I - I 70 I ns I
lOR rise
I
I
I
I
I
I
Delay from clock fall to I - I 85 I - I 70
ns I
I
10Rg rise
I
I
I
I
I
ns I
Delay from clock rise to I
I 85 I
I 70
RD fal1
I
I
I
I
I
ns I
Delay from clock fa1l to ! - ! 95 ! - ! 80
RD fa1l
I
I
I
I
I
ns I
Delay from clock rise to I
I 85 I
I 70
RD rise
I
I
I
I
I
Delay from clock fal1 to ! - ! 85 ! - ! 70
ns I
RD rise
I
I
I
I
I
-165-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl OAF/TMPZ84C1 OAF-6
TECHNICAL DATA
NO.
SYMBOL
PARAMETER
34
TdCr(Wf)
35
TdCfCwn
36
TdCr(Wrl
37
TdCfCWr)
38
TwWl
Low WR Eulse width
39
TsWA(Cf)
40
TdCr(B)
41
TdCr(Iz)
WAIT signal set-up time
for clock fall
Dela:t: from clock rise up
to BUSREQ signal
Delay from c.!£ck~ise to
IORQ, MREQ, RD, WR signal
float state
Delay from
WR fall
Delay from
WR fall
Delay from
WR rise
Delay from
WR rise
clock rise to
clock fall to
clock rise to
clock fall to
I PreI
Iliminar:t: I
I 4 MHz
I 6 MHz
I
I AP/AF IAP-6/AF-61--1
IMIN.IMAX.IMIN.IMAX.IUNITI
I
I 65 I
I 60 I ns I
I
I
I
I
I
I
I - I 80 I - I 60 I ns I
I
I
I
I
I
I
I
I 80 I
I 70 I ns I
I
I
I
I
I
I
I 80 I - I 70 I ns I
I
I
I
I
I
I
I
1220 I - 1135 I - I ns I
I
I
I
I
I
I
I
I
I
I
I
I
I 70 I
I 60 I
I ns I
I
I
I
I
I
I
I - 1100 I - I 90 I ns I
I
I
I
I
I
I
I - I 80 I - I 70 I ns I
I
I
I
I
I
I
I
I
I
I
I
I
-
A.C Test conditions
VIH = 2.4V, VIL = 0.4V, VIHC = VCC - 0.6V, VILC
VOH = 2.2V, VOL = 0.8V
CL=lOOpF
4.4
0.6V
Capacitance
SYMB OLo--r-::-:---::I..:.:TEM:::=-_-r--c:----:;-:-:::-=-T:::ES::.:T:.......::C.:::.:ON::..::D:..::I..::.T:;.:IO:;:.:N'--_-+I.:.:M::.:IN:.:..:.'---TI..:.:TY.:..:P:-=.-+IMA=;:X:..:.-. I UN IT
CCLOCK
Clock Input
f=lMHz
I
1
1 5 I pF
CaEaci tance
All terminals except
1_ _+1___+-1---::_+-1---=_
CIN
Input
that to be measured
I
I
1 5
I pF
CaEacitance
should be earthed.
1_ _;-1_--11-::-+1---:::-COUT
Output
1
1
I 5
I pF
CaEac i tance
I
I
I
I
-166-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl oAP/TMPZ84Cl oAP-a
TMPZ84Cl oAf/TMPZ84Cl OAf-a
TECHNICAL DATA
4.5
Timing diagram
Numbers shown in the following figures correspond with those in the 4.3
A.C. Electrical Characteristics Table.
(1)
When operate as peripheral devices (inactive state)
®
eLK
@
CE
lOP,",
WR
RD
QJJ®
DO -D7
MI
lEI
lEO
INT
@i
Y
INTERRUPT
CONDITION
BAI
\I
BAO
RDY
J
@
(zj)
i
f
/
ACTIVE
NON-ACTIVE
-167-
~
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
(2)
TMPZ84Cl OAP/TMPZ84Cl OAp·6
TMPZ84Cl0AF/TMPZ84Cl0AF-6
When operate as bus controller (active state)
eLK
r INPUT -+-f-f--++-----/ 1<---+-'1' '---l---++--+_·-V
DO -
D7
i
lOUTPUT
-+-f-f---++----++----+--4+J
RD
-168-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl DAP/TMPZ84Cl OAP-6
TMPZ84Cl DAF/TMPZ84Cl DAF-6
TECHNICAL DATA
5.
External Dimension View
Unit in tmD
5.1
DIP package
><
00(
:>l
0
ui
2:
~
O.S±O lS
:>l
"!
1.4
M
Note 1.
Note 2.
2.S4±02S
O.lS
~
lS.24.± 0 2 S
,,
,
"
"
I,
"
02S+ 01
-DOS
0-15·
This dimension is measured at the center of bending point of leads.
Each lead pitch is 2. 54tmD, and all the leads are located within +0.25
mm from their theoretical positions with respect to No.1 and No.40
leads.
-169-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84Cl OAP/TMPZMC1 OAP-6
TMPZ84Cl0AF/TMPZ84Cl0AF·6
TECHNICAL DATA
5.2
44-Pin mini-flat Package
Unit in mm
035
TnoB(Pl'tCh)
~ ----r
21~
I
14 O±O 1
(17.6±0.3)
.1
-
IBO± 0.25
MARK
....
o
+l
OJ
....
o
J
J/\
(06)
~
UIJUUULUlJlIllIlll
,
~.
(l.2±02)
{'"
"'0
~
15.2±0.3
-170-
,.."'
N
,....
~
....
......
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
6.
TMPZ84Cl OAP/TMPZ84Cl OAP-&
TMPZ84Cl0AF/TMPZ84Cl0AF-&
Precautions
For the basic timings, please refer to the precautions in 3.3.2 (1).
For the commands, care shall be taken to the programming as there are many
registers and setup is considerably complictated.
As the precaution for the programming, the "fixed address destination port
programming" is briefly described.
When Port A is assumed to be the
"fixed address destination port", address can be loaded in the following
steps:
(1)
(2)
(3)
(4)
(5)
(6)
Write Port A address into WRO.
Designate Port A as the source port. (set up temporarily)
Load Port A address on the address counter. (Load command CFH)
Write Port B start address into WR4.
Convert Port A into the destination port.
Load Port B start address on the address counter. (source port address)
-171-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
-172-
TMPZ84Cl OAP/TMPZ84Cl OAP-6
TMPZ84Cl OAF/TMPZ84C1 OAF-6
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84C20P, TMPZ84C20AP/AP-6
TMPZ84C20F, TMPZ84C20AF/AF-6
TMPZ84C20P, TMPZ84C20AP, TMPZ84C20AP-6, TMPZ84C20F, TMPZ84C20AF, TMPZ84C20AF-6
TLCS-z80 PIO: PARALLEL INPUT/OUTPUT CONTROLLER
1.
General Description and Features
The TMPZ84C20 (hereinafter referred to as PIO) is CMOS version of Z80 PIO
and has been designed to provide low power operation.
The PIO is a general purpose parallel input/output port device with two
programmable independent 8-bit ports, which provides a direct interface
between the Z80 microprocessor (hereinafter referred to as MPU) and
peripheral devices.
This PIO provides excellent data transfer processing by the interrupt and
allows the interrupt in Mode 2 of MPU.
The TMPZ84C20 is fabricated using Toshiba's CMOS Silicon Gate Technology.
The principal functions and features of the TMP84C20 are as follows.
(1) Compatible with the functions and pin connections of Zilog Z80 PIO.
(2) Low power consumption
2mA Typ. (@5V @4MHz) •.. TMPZ84C20P/F, TMPZ84C20AP/AF
3mA Typ. (@5V @6MHz) •.• TMPZS4C20AP-6/AF-6
lOuA Max. (@5V, Stand-by)
(3) Operating temperature
-40 C to 85 C
(4) DC to 4MHz operation ..• TMPZ84C20P/AP
DC to 6MHz operation .•• TMPZS4C20AP-6/AF-6
(5) 2 programmable independent 8-bit input/output ports with handshake
func t ion.
(6) 4 operation modes for each port:
Mode 0 (Byte Output Mode)
Mode 1 (Byte Input Mode)
Port A only.
Mode 2 (Byte Input/Output Mode)
Mode 3 (Bit Mode)
(7) Built-in interrupt priority control circuit in daisy chain structure
(S) Port B outputs capable of driving Darlington transistors
(9) All input/output lines are TTL compatible.
(10) Single 5V power supply. Single-phase clock
(11) 40 pin DIP package, 44 pin Mini Flat Package.
(Note)
Z80(R) is a registered trademark of Zilog Inc., U.S.A.
-173-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C20P, TMPZ84C20AP/AP-6
TMPZ84C20F, TMPZ84C20AF/AF-6
TECHNICAL DATA
2.
Pin Connections and Pin Functions
2.1
Pin connections
The pin connections of the TMPZ84C20P are as shown in Fig. 2.1.
.,"
B7
Al
"
A3
V5s(aNll)
Ee
_lev
s.
E5
A<
B4
E3
A3
A2
B2
Al
AO
~
BO
Bffi
DO
lEI
INT
lEO
D1
BP.DY
Vs.s
JJIDY
(a)
"'"'
'"
'"
wi:
ilL
B1
Vee
eLK
(Note) NC must be used at open condition.
*ICV must be used at open
Condition or Connected with Vcc.
(b) MFP Pin Connection
DIP Pin Connection
Fig. 2.1
2.2
"
Pin Connections (Top View)
Pin names and functions
I/O pin names and functions are as shown in Table 2.1.
Table 2.1
Pin Name
DO - D7
Pin Names and Functions
I Number I Input/Output I
lof Pinl
3-state
I
I 8 I
I/O
I
I
I
3-state I
I
I
I
1
I Input
I
I
I
I
I
I
I
Function
8-bit bidirectional data bus.
Data transfer between MPU and PIO
Chip enable.
Used for accessing MPU and PIO.
When MPU selects this PIO, this terminal
becomes L level (Refer to 3.4 Basic timing.)1
I
I
I Normally, this terminal is connected to the I
I
I address decoder output.
I
I
I Control/data select.
I
I
Input
I Indicates if signal on the data bus is con- I
I
I trol signal or data. Selects data at L
I
I
I level and command at H level. Normally,
I
I
I
I connected to address bit Al of MPU.
I
I Port A/port B select.
I
I
1
Input
I Selects Port A at L level and Port B at H
I
B/A
I
I level.
I
I
I Normally, connected to address bit AO of
I
______~I____~________~I_MP~U~.______________________________ I
cin
-174-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
Pin Name 1Number 1Input/Output 1
lof Pin
3-state
1
TMPZ84C20P, TMPZ84C20AP/AP-6
TMPZ84C20F, TMPZ84C20AF/AF-6
Function
1
1
-A~0~-~A~7--rl~~8~+-~~I~/~0~~I~p-o-r-t-A~b-u-s-.-----------------------------1
1
3-state
Input
BSTB
ARDY
Input
1
Output
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
1
Input
Input
IORQ
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
I
RD
I
Input
BO - B7
8
1/0
3-state
CLK
1
Input
1
1
1
1
I
1
1
1
I
I
I
1
1
Data transfer between Port A of PIO and
1
external device.
1
Port A strobe input
1
Handshake signal from the external device. 1
Signal meaning differs depending upon
1
operatiom mode. (Refer to 3.4 Basic
I
timing.)
1
Port B strobe input
1
Handshake signal from the external device. 1
Signal meaning is the same as ASTB but dif- 1
fers if Port A is in Mode 2.
1
(Refer to 3.4 Basic timing.)
1
Regis ter A ready.
1
Port A ready.
1
Handshake signal to the external device.
1
Signal meaning differs depending upon
1
operation mode. (Refer to 3.4 Basic
1
timing.)
1
Machine cycle 1.
1
When both M1 and IORQ are at L level, in1
dicates that MPU is executing the inter1
rupt acknowledge cycle.
(Refer to 3.4
1
Basic timing.) Normally, connected to Ml
1
of MPU.
1
I/O request.
1
Used to access between MPU and PIO. This
1
terminal becomes L level when I/O addresses 1
are on the address in the write cycle and
1
read cycle. Further, when IORQ and Ml are 1
both at L level, it indicates that MPU is
1
executing the interrupt acknoledge cycle.
1
(Refer to 3.4 Basic timing.)
1
Normally, connected to IORQ of MPU.
1
Read signal.
I
Used to access between MPU and PIO.
1
Controls the transfer direction. (Refer to 1
3.4 Basic timing) Normally, connected to
1
RD of MPU.
1
Port B bus.
1
Data transfer between Port B of PIO and
1
external device. Capable of driving -I.SmA 1
(@VoH=l.SV) Dar! ington .trans istors.
1
System clock.
1
Single-phase clock input.
I
In DC state (either at H or L level), PIO isl
in a stand-by state and power consumption
I
becomes extermely less.
1
-175-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
Pin Name 'Number' Input/Output
Function
~~____-+'=o~f~p~in~'r-~3~-~s~t~a~t~e__-r~~
lEI
I
1
I
Input
l'
INT
lEO
,
________~__~__~___________________ ,
Interrupt enable input.
,
Toge ther wi th lEO and INT, forms da isy cha in'
interrupt control signal.
Connected to
lEO of high priority peripheral LSI.
However, to give higher priority than other
peripheral LSI's to this PIO, connect this
terminal to the +SV power.
(Refer to 3.3.2 Interruption.)
Interrupt request.
Interrupt r~est signal for MPU.
Connect to INT of MPU. (0 en drain)
Interrupt enable output.
Together with lEI and INT, forms daisy chain
interrupt control signal.
Connected to
lEI of low priority peripheral LSI.
However, if this PIO has the lowest priority
than any other peripheral LSI's, this lEO
is not used.
(Refer to 3.3.2 Interruption)
PORT Bready
Handshake signal to the external device.
Signal meaning is the same as that of ARDY.
However, it differs when Port A is in Mode
2. (Refer to 3.4 Basic timing.)
"
"
"
"
"
"
"
'1'
"
TMPZ84C20P, TMPZ84C20AP/Ap·6
TMPZ84C20F, TMPZ84C20AF/AF·6
Output
Output
BRDY
1
Output
VCC
1
Power supply
VSS
1
Power supply' OV
, +SV
I
,
-176-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C20P, TMPZ84C20AP/AP-&
TMPZ84C20F, TMPZ84C20AF/AF-6
TECHNICAL DATA
3.
3.1
Functional Description
Block diagram
The block diagram of PIO is shown in Fig. 3.1.
8
INTERNAL
CONTROL
LOGICAL
OPERATION
CIRCUIT
DATA BUS
6
CONTROL
LINE
MPU BUS
I/O
I.OOICAL
OPERATION
CIRCUIT
lEO
I
)
AO-A7
DATA CONTROL
(PORT I/OLIN~It E
A'STB
ARD'f
HANDSHAKE
CONTROL LINE
"~~rr
INTF.HHU!'T
CONTHOL
LOGICAL
OPERATION
CIRCU IT
iNT
r'
JL
8
DO - lY1
~
PORT A
I/O
LOGICAL
OPERATION
CIRCUIT
B
PORT
..J.,
---..;
B
I/O
LOG leAL
OPERATION
CIRCUIT
Ir
)
BO- B7
DI\T A CONTROl •
(1'01<1'
I/~LINI~\NI!:
HANDSHAKE
BRDY
CONTROL LINE
lEI
INTERRUPT
CONTROL LII:E
Fig. 3.1
3.2
Block Diagram
System cinfiguration (Architecture)
The system configuration of PIO consists of four
circuits as below.
(1) MPU Bus Input/Output Logical Operation Circuit
(2) Internal Control Logical Operation Circuit
(3) Interrupt Control Logical Operation Circuit
(4) Port Input/Output Logical Operation Circuit
logical
operation
3.2.1
MPU bus input/output logical operaton circuit
This is a circuit for connecting PIO to MPU. This circuit connects PIO
directly to MPU without using other external circuit.
However, if a
system becomes large, it becomes necessary to provide an address decoder
and a line buffer.
3.2.2
Internal control logical operation circuit
This is a circuit to synchronize the MPU data bus with PIO Port A and
Port B.
-177-
TOSHIBA JNTEGRATED CIRCUIT
TMPZ84C20P, TMPZ84C20AP/AP-6
TMPZ84C20F, TMPZ84C20AF/AF-6
TECHNICAL DATA
3.2.3
Interrupt control logical operation circuit
This is a circuit to perform processing concerning interrupt of MPU such
as decision of priority.
3.2.4 Port input/output logical operation circuit
This i~ a circuit to connect PlO to external devices.
This ciruit
consists of 7 registers and one flip-flop circuit shown below.
Data
write to the registers is performed by MPU according to program. Shown
in parentheses is number of bi ts.
The internal port configurat ion is
shown in Fig. 3.2.
0
0
0
0
0
0
0
Data input register
Data output register
Mode control register
Interrupt vector register
Interrupt control register
Mask control register
Data input/output control register
MODE
CONTROL
REGISTER
(2 BITS)
INTERRUPT
VECTOR
REGISTER
(8 BITS)
----'\
--,I
(8 bits)
(8 bi ts)
(2 bits)
(8 bits)
(2 bits)
(8 bits)
(8 bits)
DATA INPUT
/OUTPUT
CONTROL
REGISTER
(8 BITS)
110UTPUT ENABLE
INTERNAL BUS
w.,
rv'
DATA
OUTPUT
REGISTER
(8 BITS)
-o!
INTERRUPT
CONTROL
REGISTER
(2 BITS)
~
r---v
MASK
CONTROL
REGISTER
(8 BITS)
1NRiT DATA
DATA
INPUT
REGISTER
(8 BITS)
U
HANDSHAKE
CONTROL
CIRCUIT
INTERRUPT
REQ,UEST
Fig. 3.2
(1)
-
if
DATA
CONTROL LINE
READY
STROBE
HANDSHAKE
CONTROL LINE
Internal Port Configuration
Data output register
This register holds data to be transferred from MPU to external devices.
Output data from MPU are transferred through this register.
-178-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
(2)
(3)
(4)
(5)
(6)
(7)
(8)
TMPZ84C20P, TMPZ84C20AP/AP-8
TMPZ84C20F, TMPZ84C20AF/AF·6
Data input register
This register latches data being transferred to MPU from external
devices. All input data to MPU are read into MPU through this register.
Mode control register
This register is used to designate operation modes. Operation modes are
set up through control by MPU.
Interrupt vector register
This register holds vector address of a table that stores atart address
of an interrl,lpt routine. This register is used only when the interrupt
process is performed.
Interrupt control register
This register designates condtions for monitoring the input ports. This
register is used only in Mode 3 of PIO.
Mask control register
This register designates which bits of the input port is enable for the
interrupt request. This register is used only in Mode 3 of PIO.
Data input/output control register
This register designates each of the terminals for output/input use.
This register is used only in Mode 3 of PIO.
Handshake control circuit
This circuit controls data transfer with external devices connected to 8
bit input/output ports.
3.3
Basic operation
3.3.1
Reset
PIO has the following two reset functions:
Power ON reset
PIO has a built-in automatic power ON reset circuit.
Reset by external signal
When RD and IORQ termiansl are set at H level and M1 terminal kept at L
level for 2 system clocks, PIO is reset immediately after the rise of M1
terminal.
(1)
(2)
Reset status
(1) Both ports are set in Mode 1.
(2) Interrupt is disabled.
(3) All bits of the data input/output registers of both ports are reset.
(4) All bits of the mask control registers for both ports are reset and the
completely masked state is resulted.
(5) The port input/output lines of both ports are placed in high impedance
state.
(6) RDY signals for both ports become L level.
The reset status is held until control characters are input.
control characters refer to "3.5 Operating procedures".
3.3.2
For the
Interrupt
PIO is capable of generating interrupt when MPU is operating in Mode 2.
The interrupt request signal (INT) from PIO is accepted when MPU is in
the enabled state (after execution of EI instruction).
When accepted
INT, MPU latches the interrupt vector (8 bit data) from PIO.
-179-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C20P, TMPZ84C20AP/AP-6
TMPZ84C20F, TMPZ84C20AF/AF-6
TECHNICAL DATA
Based on this data, MPU designates the start address of the interrupt
routine and by calling this routine, starts the interrupt processing.
Since the start address of the interrupt routine can be thus designated
by the in terrupt vec tor from PlO, it is poss i ble for user to ca 11 any
addres~ by changing a value of this vector.
The interrupt ends when MPU executes RETI instruction. PIO has the RETI
instruction decoding circuit and is capable of knowing end of the
interrupt by constantly monitoring the data bus.
The interrupt priority of peripheral LSI's is decided by the daisy chain
structure.
When peripheraJ LSI's are connected in series as shown in
Fig. 3.3, peripheral LSI's which are physically closer to MPU will have
higher interrupt priority. Further, in the inside of PIO, Port A has the
higher priority than Port B.
Z80 Peripheral LSI has lEO and lEI terminal.
The lEO terminal of a
higher priority peripheral LSI is connected to the lEI terminal of a
lower priority peripheral LSI by this signal line.
However, the lEI
terminal of a peripperal LSI having the highest priority is connected to
the +5v power supply and the lEO terminal of a peripheral LSI having the
lowest priority is not used.
Generation of interrupt is in accordance
with the following rules:
o
o
o
o
o
When the lEI and lEO terminals are both at H level, no interrupt in
progress.
At this time, the INT terminal is at H level.
In this
state, the interrupt can be requested.
When PIO outputs the interrupt request signal (INT), the lEO terminal
is made to L level by this PIO. When an interrupt request is accepted
by MPU, the INT terminal returns to H level.
When the lEI terminal becomes L level, the lEO terminal also becomes L
level.
When the lEI terminal is at L level, no interrupt request can be made.
I f the lEI terminal becomes L leve 1 wh i Ie interrupt is genera ted, the
interruption process is kept suspended.
The connection in daisy
PIO's without providing
not to exceed the limit
fall of MI signal to the
cycle).
Connecting of
circuit.
(1)
chain
tructure allows connection of up to 4
an e" ernal circuit.
This is maximum quantity
of TEO signal propagation time (time from the
fall of IORQ signal in the interrupt acknowledge
more than 5 PIO's requires a simple external
Before generat ion of interrupt
o Vec
H
MPU INT
Vee
0-1!1
INT
I lEI
UU
IEOI
(1)
INT
I lEI
INT
INT
I
I...!!-I
I...!!-I
IEOI
I lEI
IEOI
I lEI
lEOI
(2)
-180-
0)
(4 )
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C20P, TMPZ84C20AP/Ap·6
TMPZ84C20F, TMPZ84C20AF/AF·6
TECHNICAL DATA
(2)
Interrupt request from peripheral (2) to MPU
____ II_L~____.-___________.------------_r------------~--o Vee
Vee
(3)
HI
0
I H I
I L I
I L I
-1 _ _ _ _ 1-1 _ _ _ _ 1-1 _ _ _ _ 1-1 _ _ _-
Response by MPU to interrupt request
of peripheral (2)
•.•.. Execute the interrupt routine
I_H~____.-___________.------------_r------------~--,o Vee
____ I
Vee
(4)
0
HI
I H I
I L I
I L I
-1 _ _ _--1-1 _ _ _ _ 1-1 _ _ _ _ 1-1 _ _ _-
Interrupt request from peripheral (1) to MPU ••.•• Suspends the interrupt
routine of peripheral (2)
I_L~____.-___________.------------_r------------~--,o Vee
____ I
Vee
(5)
0
HI
I L I
I L I
I L I
-1 _ _ _ _ 1-1 _ _ _ _ 1-1 _ _ _ _ 1-1 _ _ _-
Response by MPU to interrupt request
of peripheral (1)
.••.. Execute the interrupt routine
I_H~____r -___________.------------_r------------~--O Vee
___I
Vee
(6)
0
HI
I L I
I L I
I L I
-1 _ _ _ _ 1-1 _ _ _ _ 1-1 _ _ _--1-1 _ _ _-
The interrupt routine of peripheral (1) ends (execution of RETI command)
Restarts interrupt routine of peripheral (2)
----------_r__----------~-o
I_H~____.-___________.__
___I
Vee
0
HI
I H I
I L I
I L I
-1 _ _ _ _ 1-1 _ _ _ _ 1-1 _ _ _ _ 1-1 _ _ _-
-181-
Vee
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C20P, TMPZ84C20AP/AP-6
TMPZ84C20F, TMPZ84C20AF/AF-6
TECHNICAL DATA
(7)
The interrupt routine of peripheral (2) ends (execution of RETI command)
-=H______.-______________- r______________~--------------~---O Vcc
Vec a
HI
I HI
IHI
1 H I
--1 _ _ _ _ 1-1 _ _ _ _ 1-1 _ _ _ _ 1-1 _ _ __
The interrupt priority of peripheral LSI
Fig. 3.3
(1)
>
>
(2)
(3)
>
(4)
Operation of Daisy Chain
3.3.3
Operation mode
PIO is operated in one of the following 4 operation modes.
are selected by writing mode control characters.
a Mode 0 (Byte output mode)
a Mode 1 (Byte input mode)
a Mode 2 (Byte input/output mode)
a Mode 3 (Bit mode)
These modes
(1)
Mode 0 (Byte output mode)
In Mode 0, PIO sends out data received from MPU to external devices
through the port data output register.
The content of the data output register can be written using an output
command.
In addition, it remains unchanged till next output command even
when data on the data bus changed.
Executing an output command by MPU generates a write signal in PIO in the
write cycle.
Data on the data bus can be latched in the data output
register by this write signal.
(2)
Mode 1 (Byte input mode)
In Mode 1, PIO sends out data received
through the port data input register.
(3)
from
external
device
to
MPU
Mode 2 (Byte input/output mode)
Mode 2 is an operation mode which combined Mode 0 and Mode 1. Mode 2 is
used at Port A only.
In th is mode, all of 4 handshake control 1 ines are used.
The handshake
control line of Port A is used for data output, and that of Port B for
data input. Port A is used for data transfer and Port B is set in Mode 3
(Bit mode) under which the handshake control line is not used.
Interrupt
timing generation is nearly the same in both Mode
and Mode 1.
In case
of the input operation, the handshake control line of Port B is used and
therefore, the interrupt vector written into Port B is transferred.
It
is therefore possible to control interrupt of input and output operation
by different vectors.
°
(4)
Mode 3
Mode 3
as an
normal
(Bit mode)
is an operation mode which each bit of 8-bit port can be handled
input or output.
Since the handshake control line is not used,
read/write can be performed.
-182-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84C20P, TMPZ84C20AP/AP-a
TMPZ84C20F, TMPZ84C20AF/AF·a
In case of write, data sent from MPU to PIO is latched in the data output
register corresponding to bits which are set for output at the same
timing as in Mode O.
Interrupt is generated under the enabled state and when the condition
specified in interrupt control register is satisfied for the bits which
is set as an input. However, if Port A is operating in Mode 2, Port B
cannot generate interrupt in the bit mode.
Further, when the interrupt
is used, the interrupt of a bit which is set for output is inhibited, a
mask control register bit corresponding to that bit is set to 1.
-183-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84C20P, TMPZ84C20AP/AP-6
TMPZ84C20F, TMPZ84C20AF/AF-6
3.4
Status change flowchart and basic timing
3.4.1
Status change flowchart
The status change flowchart of PIO is shown in Fig. 3.4
1I0DI': 0
DATA RECEIVE
FROM MPU
WRITE TO OUTPUT
REGISTER
OUTPUT TO
DEVICE
EXTERNAI~
Fig. 3.4 (a)
Status Change Flowchart of PIO
-184-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C20P, TMPZ84C20AP/A~
TMPZ84C20F, TMPZ84C20AF/AF-6
TECHNICAL DATA
INTERRUPTION CONTROL
CHARACTER
INTERRUPT
VECTOR
WRITE OF
INTERRUPT
VECTOR
2
Fig. 3.4 (b)
Status Change Flowchart of PlO
-185-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C20P, TMPZ84C20AP/A~
TMPZ84C20F, TMPZ84C20AF/AF..
TECHNICAL DATA
3.4.2
Write cycle
Write signal (*WR) is produced in the PIO by IORQ, RD, C/O and CE
signals. At the system clock T2 state, MPU changes the IORQ terminal to
L level and starts the write cycle. At this time, in order to show the
write eycle. Ml terminal needs to be H level. Furhter, signals are sent
from MPU to the B/A terminal and C/O terminal of PIO, respectively, to
designate selection of port, control signal or data.
Thus, the data
output register for the selected port of PIO can latch data at the system
clock T3 state. TW is the waiting state that is automatically added by
MPU.
T2
Tl
Tw
T3
Tl
CLK
c/D,B/A
CE
=x
X
\
/
\
IORQ,
/
RD
MI
DATA BUS
X
"\
*iR
X
INPUT
/
*WR - c/o· CE' IORQ.
Fig. 3.5
Write Cycle Timing
3.4.3 Readout cycle
At the system clock T2 state, MPU sets
the PIO at L level and starts the read
show the read cycle it is necessary to
The PIO output data by CE, IORQ or RD
that is automatically added by MPU
-186-
the RD, CE and IORQ terminals of
cycle. At this time, in order to
set the MI terminal at H level.
signal. TW is the waiting state
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
~
TMPZ84C20P, TMPZ84C20AP/AP-6
TMPZ84C20F, TMPZ84C20AF/AF-6
__________~x~_____
'-----__________-->1
\'--_---.J/
\~-~/
----------------------~~r------------
\~-----'/
Fig. 3.6
3.4.4
Readout Cycle Timing
Mode 0 (Byte output mode)
The output cycle in Mode 0 starts when MPU executes an output command.
When MPU executes the output command, a write signal (*WR) is produced in
the PIa in the write cycle.
Data on the data bus is latched by this
signal in the data output register of the selected port.
The RDY
terminal becomes H level at the first fall of the system clock after the
rise of the write signal (*WR).
This indicates that data from the data
output register is already on the port I/O terminal.
The external device sets the RDY terminal to L level at the fall of the
first system clock after the rise of the STB terminal through which
information of receipt of this data is input to the PIa, and waits next
output command.
If it is the interrupt enabled state at this time, the INT terminal is
set to L level at the rise of the STB terminal and the interrupt request
signal is output to MPU.
The timing chart of Mode 0 is shown in Fig.
3.7.
3.4.5
Mode 1 (Byte input mode)
The input cycle is started when MPU completed the preceding data read.
The external device sets the STB terminal of the PIa to L level and loads
data on the port I/O line.
-187-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C20P, TMPZ84C20AP/AP-6
TMPZ84C20F, TMPZ84C20AF/AF-6
TECHNICAL DATA
The RDY terminal becomes L level at the first fall of the system clock
after the rise of the STB terminal to inhibit the external device to send
out next data.
If it is the interrupt enabled state at this time, the INT terminal is
set to L leve 1 at the rise of the STB terminal and the interrupt is
requested to MPU.
When MPU executes the input command by the interrupt routine, the read
signal (*RD) is produced in the PIO in the read cycle.
This signal
outputs data from the selected port data input register to the data bus,
and MPU receives this data.
The RDY terminal becomes H level at the
first fall of the system clock after the rise of the read signal (*RD)
and next input is waited.
The timing chart of Mode 1 is shown in Fig.
3.8.
TW
T2
T3
CLK
RDY
PORT INPUT/
OUTPUT LINE
DATA FROM MPU
'I
*WR - C/D' QE·IORQ.
Fig. 3.7
Mode 0 Timing
-188-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C20P, TMPZ84C20AP/AP-6
TMPZ84C20F, TMPZ84C20AF/AF-6
TECHNICAL DATA
--if
PORT INPUT/
OUTPUT LINE
--if
*RD
*RD = C/D· CE· RJj.
IOml:
Fig. 3.8
3.4.6
Mode 1 Timing
°
Mode 2 (Byte input/output mode)
Mode 2 is an operation mode combining Mode
and Mode 1.
The timing of output operation is almost identical to that of Mode 0.
However, in Mode 2 data is output only when the ASTB terminal is at L
level while in Mode 0, data is always output to the port input/output
line.
External devices can receive data at the rise of the ASTB signal
using it as a latch signal.
The timing of input operation is identical to that of Mode 1.
The handshake line of Port A is used for output control and the handshake
line of Port B for input control.
Further, the interrupt vector produced by the BSTB signal when Port A is
in input operation and that produced when Port B is used in Mode 3 will
become the same value.
For this reason Port B masks all bits by setting
the mask control words so that the interrupt function is not used.
-189-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84C20P, TMPZ84C20AP/AP-6
TMPZ84C20F, TMPZ84C20AF/AF·6
eLK
ARDY
BRDY
PORT A INPUT
/OUTPUT LINE
- - - - - - - - - \ - - - - - < O U T P U T }---...(
Fig. 3.9
3.4.7
Mode 2 Timing
Mode 3 (Bit mode)
In this mode, the handshake line is not used. Therefore, the normal port
read/write can be performed and read and write of the port is possible
any time.
Write from MPU is latched in the data output regist'er
corresponding to a bit which is set for output at the same timing as that
of Mode O.
Except when Port A is used in Mode 2, the RDY terminal of a
port operating in Mode 3 is fixed at L level and data being transferred
is composed of two data of the data output register and data input
register. That is, data in bits that are set for output and data in bits
set for input are composed into one data.
Interrupt is generated when the interrupt is enabled and bits that are
set for input satisfy conditions specified by the mask control register
and interrupt control register. However, when Port A operates in Mode 2,
Port B is not capable of producing any interrupt in Bit Mode.
Further,
when the interrupt is used, in order to inhibit interrupt of a bit that
is set for output, a mask register bit corresponding to that bit is set
to l.
An interrupt request is generated at the point of time when the logical
condition becomes true.
In addition, when the logical condition becomes
true immediately before the MI terminal becomes L level or the MI
-190-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C20P, TMPZ84C20AP/AP-6
TMPZ84C20F, TMPZ84C20AF/AF-6
TECHNICAL DATA
terminal is at L level, an interrupt is generated at the rise of the Ml
terminal.
CLK
\'-------jfl
\'------'/
\'-----_/
PORT INPUT/
OUTPUT LINE
DATA 1
DATA 2
DATA BUS
lNPUT
INTERRUPT CONDITION
IS SATISFIED
Fig. 3.10
3.4.8
DATA 1 IS PUT ON BUS
Mode 3 Timing
Interrupt acknowledge cycle
At the same time INT signal set to L level, the PIO sets the lEO terminal
at L level to inhibit interrupt request from lower priority order LSI.
When receiving the interrupt request signal (INT) from the PIO, MPU sets
the Ml and IORQ termina ls of the PIO at L leve 1 as the interrupt
acknowledge signal. The IORQ terminal becomes L level later than the Ml
terminal by 2.5 system clocks.
In order to stabilize the daisy chain
connected signal lines, lEI and lEO signals, the ports and peripheral LSI
cannot change interrupt requests during interrupt acknowledge cycle.
The RD terminal is kept at H level to distinguish the interrupt
acknowledge cycle from the command fetch cycle.
If the IORQ terminal
becomes L level when the lEI terminal is at H level, interrupt vector is
output to the data bus from the port requesting the interrupt
At this time, 2 system clocks are automatically inserted by MPU as the
waiting state to keep stability of the daisy chain connect.
-191-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C20P, TMPZ84C20AP/AP-6
TMPZ84C20F, TMPZ84C20AF/AF·6
TECHNICAL DATA
Tl
T2
TW
TW
T3
lEI
Fig. 3.11
3.4.9
Interrupt Acknowledge Cycle Timing
Return from the interrupt cycle
Return from the interrupt is effected when MPU executes RETI command.
This RETI command must be used at the last instruction of the interrupt
routine.
The execution of this RETI command by MPU returns the lEI and
lEO terminals of the PIO to the state before interrupt.
RETI command is a two byte command and its code is EDH and 4DH.
The PIO
decodes the codes of RETI command and des ides a port which makes next
interruption request. In the daisy chain structure, at the point of time
when the command code EDH is decoded, the lEI terminal of a peripheral
LSI making the interrupt is kept at H level and the lEO terminal at L
level.
If the code following EDH is 4DH, an LSI that transmitted the
interrupt immediately before the decoding, that is, only the LSI with lEI
terminal at H level and lEO terminal at L level is returned from the
interrupt.
As a result, the interrupt process of a lower priority
peripheral LSI was suspended.
-192-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C20P, TMPZ84C20AP/AP-6
TMPZ84C20F, TMPZ84C20AF/AF-8
TECHNICAL DATA
T2
Tl
T3
T4
T2
Tl
T3
eLK
iU
\~_--'/
\
/
1m
,'--_----J/
\
/
DATA BUS
--------~~r------------~
0
- - - - - - - - - ,r-------------------------------
lEI
_ _ _ _ _ _ _ _ _ _ .JI
lEO
----------------------~/
Fig. 3.12
3.5
Return Timing from Interrupt Cycle
Operating procedures
To operate the PIO it is necessary to write several control registers
into the PIO for initialization.
On a system with the C/O terminal connected to the Address AO and B/A
terminal connected to Address AI, the write is performed separated for
Port A and B.
C/O (AO)
0
B/A (AU
0
0
1
1
0
1
x
1
x
(1)
CE
0
0
0
0
1
Register Select
PORTA DATA REGISTER.
PORTA CONTROL REGISTERS
PORTB DATA REGISTER.
PORTB CONTROL REGISTERS
Interrupt vector register
07
I
I
06
05
I
I
04
I
I
03
I
I
02
01
I I
0
I
______ > Denotes
--r-
the interrupt vector
words
________________________ > Interrupt vectors given by
user
o
o
o
MPU generates the start address of the interrupt processing routine by
this vector and the content of address shown by the control of I
register of MPU.
01 to 07 are written into the interrupt vector register.
If no interrupt is used, the interrupt vector words are not required.
-193-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C20P, TMPZ84C20AP/Ap·6
TMPZ84C20F, TMPZ84C20AF/AF·6
TECHNICAL DATA
(2)
Mode control register
D7
I
I
D6
D5
I
I
D4
-1-
--1> Denotes the mode control
I
words
1___________________________ > Not used.
(Either 0 or 1 will do)
I-D7=O, D6=0
Mode 0
1____________________________________ >1 D7=0, D6=l
Mode 1
I D7=1, D6=0 Mode 2
f_D7=l, D6=1
Mode 3
Designates operation modes.
D7 and D6 are written into the mode control register.
I
I
I
I
a
a
Data input/output control register
(3)
D7
I
D6
I
I
D5
I
I
D4
I
I
D3
I
I
D2
I
I
D1
DO
_____________________ > 1-0
for au t pu t
1_1
for input
Required only for Mode 3
When Mode 3 is designated by mode control register, write following a
mode control register.
Designates each termnal of the port for output or input.
DO to D7 are written into the data input/output register.
a
a
a
a
(4)
I
Interrupt control register
D7
D6
D5
D4
o
1
1~1
I
I
Den~tes
_ _ _ _>
the interruptvector
reg1ster.
__________________>1-0
Mask word follows.
1_1
Mask word follows.
-0
I
>1
I
I
1
I -0
>1
I
I
>1-0
U
--194--
Generate interrupt when
the input line is at L level.
Generate interrupt when
the input line is at H level.
Generate interrupt at
logical condition "OR".
Generate interrupt at
logical condition "AND".
Disable interrupt request
Enable interrupt request
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C20P, TMPZ84C20AP/AP-6
TMPZ84C20F, TMPZ84C20AF/AF·6
TECHNICAL DATA
a
a
a
Set the interrupt generating conditions.
D4, D5 and D6 are used only in Mode 3.
If D6 is set at 0 (D6=0), interrupt is generated when anyone bit that
is not masked (monitored) by the mask control register become active.
If D6 is set at 1 (D6=1), interrupt is generated when all bits that are
not masked (monitored) by the mask control register become active.
If D4=1, all bits which are pending will be reset in any operation
mode.
D5 and D6 are written into the interruption control register.
a
a
a
(5)
Mask control register
D7
I
D6
\
I
D5
I
D4
\
\
I
D3
\
D2
D1
DO
-0
a
a
Monitored for interrupt
Non monitered for
interrupt
Required only for Mode 3
If D4 is set at 1 (D4=1) by the interrupt control register, the mask
control word is written following the interrupt control register.
If a bit is set at 0, the corresponding input line is monitored.
If a bit is set at 1, the corresponding input line is not monitored.
The PIO checks only the input line which has 0 data and requests
interrupt if the interrupt generation condition is satisfied.
DO to D7 are written into the mask control register.
a
a
a
a
Since four handshake control lines are all used in setting Port A in Mode
2, it is necessary to set Port B in Mode 3 in which the handshake control
line is not used.
In this case, all bits should be masked by the mask
control register (all bits are set at 1).
(Note) I t is possible to set only generation of
register shown below.
D7
D6
I
\
D5
D4
o
o
1
interrupt by
the
control
1
____________> Denotes
a control register
that sets enable/disable
interrupt
_______________________________> Not used (Either 0 or 1 will
do).
\-0
Disable interrupt
- - - - - - - - - - - - - - - - - - - > \lIEnable
-195-
interrupt
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C20P, TMPZ84C20AP/Ap·6
TMPZ84C20F, TMPZ84C20AF/AF-6
TECHNICAL DATA
-4.
ELECTRICAL CHARACTERISTICS
4.1
ABSOLUTE MAXIMUM RATINGS
Symbo~
I
vcc
I
Item
Supply Voltage
I
Ra t ing
-0.5 to +7
I Uni t I
I
V I
---------------------~-----------------------I--------------------1------1
I
VIN
I Input Voltage
I -0.5 to Vee + 0.3 I
V I
\----------\------------------------------------\--------------------1------1
I
PD
\ Power Dissipation
I
250
\ mW I
1----------1-----------------------------------1--------------------1------1
I TSOLDER I So ldering Tempera ture 00 sec)
I
260
I °c I
1----------1-----------------------------------1--------------------1------1
I
Tstg
\ Storage Temperature
I
-65 to 150
I °c I
\----------1-----------------------------------1--------------------1------1
I
Topr
I Operating Temperature
I
-40 to 85
I °c I
4.2
DC ELECTRICAL CHARACTERISTICS
TA = -40 0 C to 85 0 C, VCC = 5V + 10%, VSS = OV
SYMBOL I
PARAMETER
VILC I Low Clock Input
I Voltage
VIRC I High Clock Input
1 Voltage
VlL
1 Low Input Voltage
I (Except CLK)
VIR
1 High Input Voltage
I (Except CLK)
VOL
I Output Low Voltage
I
VOHl I Output High Voltage
I (1)
VOH2 I Output High Voltage
I (II)
ILl
I Input Leakage
Current
I
ILO
I 3-state Output
I Leakage Current in
I Float
ICCI
I
I
I
1
I
I
I
I
I
I Power Supply Currentl
I
I
I
I
ICC2
I
I Standly Supply
Current
I
IOHD*
I
I
I
I
I
I
Darlington Drive
I Current! (2)
Note
I
I
I
I
I
1
I
I
1
I
I
I
I
I
I
I
I
I
I
TEST CONDITION I
MIN. I Typ.1 MAX. IUNITI
0.6 I V
I -0.3 I I
I
I
I
IVCC-0.6 I - IVCC+0.31 V
1
I
I
V
I -0.5 I - I 0.8
1
I
1
2.2 I - Ivcc
V
I
I
I
I
IOL = 2.0mA
V
I
I - I 0.4
I
I
I
lOH = -l.6mA
2.1+
V
I
I - I
I
I
I
IOH = -250uA
V
I vcc-0.81 - I
I
I
I
uA
VIN~ VCC I
VSS~
I - I +10
I
I
I
vss + 0.4~ VOUTI
I
I
uA
S vcc
I
I - I +10
I
I
1
I
I
I
Ip/F I
VCC=5V
I
I
fCLK=(l) IAP/AF I
mA
5
I 2 I
VILC=VIL I
I
I
I
=0.2V
IAP-6 I
I
I
VIHC=CIH I/AF-61
8
rnA
I 3 I
=vcc-0.2vl
I
I
I
VlLC-VIL=0.2
I
I
I
VIHC=VIH
uA
10
I
I 0.51
=VCC-0.2V
I
I
I
VOH=1.5v
I -1.5 I - I -5.0 rnA
REXT = 1.lK
1
I
I
fCLK-l/tcC(MIN. )
(2) Port B only
(1)
-196-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
4.3
TMPZ84C20P, TMPZ84C20AP/AP-a
TMPZ84C20f, TMPZ84C20Af/Af-8
AC ELECTRICAL CHARACTERISTICS
TA = -40 o C to 85 O C,
NO.
SYMBOL
1
2
3
4
5
TeC
TwCh
TwC1
TfC
TrC
6
TsCS(RI)
*7
Th
8
TsRI (C)
9
TdRI (DO)
10
TdRI(DOs)
11
TsDI (C)
12
TdIO(DOI)
13
TsMl(Cr)
14
TsMl (C£)
15
TdM1(IEO)
16
TsIEI(IO)
17
TdIEI (lEO£)
18
TdIEI(IEOr)
19
TcIO(C)
20
TdC(RDYr)
21
TdC(RDYf)
22
TwSTB (C»
vcc = 5V .! 10%, VSS = OV
1 6MHz
1
I 4MHz
I
Ip/AP/AF IAP-6/ AF-61 UNIT I
IMIN.IMAX.IMIN.IMAX.I
I
1 2501 DC 1 1651 DC 1 ns I
ns
651
I 1051
65
ns
105
- I
- I
I ns
- I
- 1
I ns
I
I
I
CE, B/A and c/n Set-up
501
501 - I ns
time for RDI IORQ
I
I
I
Hold time
401 - I ns
401
I
I
I
F9, IORQ set-up time for
70 I - I ns
1151
clock rise
I
I
I
I
I
I
Delay from RD, IORQ fall
- I 3801 - 1300 I ns
to data outEut
I
I
I
I
1
I
Delay from RD, IORQ rise
- I 70 I ns
- I 110
to data float
I
I
I
Data set-up time for
401 - I ns
501
clock rise
I
I
I
I
1
I
Delay from IORQ fall of
- 1120 I ns
- I 160
INTA c~ele to data outEut
I
I
I
I
I
1
M1=L set-up time for
901
701
I ns
clock rise
I
I
I
I
I
I
M1=H set-up time for
01
01 - I ns
clock fall (I'll c~cle)
I
I
I
I
I
I
I
I
Delay from I'll fall to
- I 1901 - 1100 I ns
lEO fall
I 0) I
I
I
I
I
I
I
lEI set-up time for IORQ
1401 - I 1001
I ns
fall
(INTA c~c1e)
I
I
I
I
Delay from lEI fall to
- I 130 I - 1120 I ns
lEO rise
I
I
I
I
Delay from lEI rise to
- I 1601 - 1150 I ns
lEO fall
I
I
I
1
1
1
ns
IORQ=H set-up time for
2001
I 170 I
clock fall
I
I
I
Delay from clock fall to
- I 1901 - 1170 ns
READY rise
I
I
I
Delay from clock fall to
ns
- 1 1401 - 1120
READY fall
I
I
I
1501
I 1201
STROBE Eulse width
(2) I
ns
I - I
PARAMETAER
-197-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C20P, TMPZ84C20AP/A~6
TMPZ84C20F, TMPZ84C20AF/AF-6
TECHNICAL DATA
NO.
23
TsSTB(C)
24
TdIO(PD)
25
TsPD(STB)
26
TdSTB(PD)
27
TdSTB(PDr)
28
TdPD(INT)
29
TdSTB(INT)
Note 1
Note 2
4.4
SYMBOL
6MHz
1 4MHz
Ip/AP/AF 1AP -6/ AF-6;1 UNIT
IMIN.IMAX. MIN. IMAX. 1
1
1
I
Set-up time of STROBE
1501 - 1 ns
2201
rise for clock fall
1
1
1
(in case of making READY
1
1
1
to active by next cycle)
1
1
1
1
1
1
Delay from IORQ rise to
- 1 180
- 1 1601 ns
port data stable
1
1
1
(Mode 0)
1
1
1
Data set-up time for
2301
1901
1 ns 1
STROBE rise
1
1
1
1
(Mode 1)
1
1
1
1
Output data delay time
- 1 2101 - 1 1801 ns
from STROBE fall
1
1
1
1
(Mode 2)
1
1
1
1
1
1
1
1
Delay from STROBE rise
- 1 1801 - 1 1601 ns
to data float
1
1
1
1
(Mode 2)
1
1
1
1
Delay fro~ort data
1 4901 - I 4301 ns
match to INT fall
1
1
1
1
(Mode 3)
1
1
1
1
1
1
1
1
Del~from STROBE rise
1 4401
1 3501 ns
to INT fall
1
1
1
1
(Mode 2)
1
1
1
1
PARAMETAER
-
Item with * mark (No.7) is not compatible with NMOS z80 PIO.
(1) If the daisy chain is at N stage,
2.5 TcC>(N-2)TdIEI(IEOf)+(TdMl(IEO)+TsIEI(IO)+TTL buffer delay
must be satisfied.
(2) In Mode 2, TwSTB>TsPD(STB) must be satified.
(3) AC test condition: Input - VIH=2,4V, VIHC=VCC-0.6V, VIL=0.4V,
VILC=0.6V
Output - VOH=2.2V, VOL=0.8V
CL=100pF
Capacitance
SYMBOL 1
ITEM
I
I
CCLOCK I Clock Input
1
1 Capacitance
CIN
I In]2ut Ca]2acitance 1
COUT
IOut]2ut Cal2acitance 1
TEST CONDITION
f=IMHz
All terminals except that
to be measured should be
earthed.
-198-
IMIN.ITYP.IMAX.luNITI
1 - I 5 I pF 1
1
1
1
1
I
1
I
1 5 I ]2F I
1 - 1
1 10 I ]2F 1
I
-
-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
5.
TMPZ84C20P, TMPZ84C20AP/Ap·6
TMPZ84C20F, TMPZ84C20AF/AF·6
Package Dimension
Unit in mm
5.1 Plastic Package
><
<
::;!
51.:lMAX
0
ori
u
15.24±O25
/'
"
,;
z
~
O.5±O 15
::;!
'"
,.;
Note 1.
Note 2.
1.4
2 54± 025
025+ 01
-005
0-15°
0.15
This dimension is measured at the center of bending point of
leads.
Each lead pitch is 2.54mm, and all the leads are located within
+0.25mm from their theoretical positions with respect to No.1
;nd No.40 leads.
-199-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C20P, TMPZ84C20AP/AP-6
TMPZ84C20F, TMPZ84C20AF/AF-6
TECHNICAL DATA
Unit in mm
5.2 44-pin mini-flat package
035
Tno.B(PitCh)
i----r--i
.
I
.
I__ ~ARKING _~
!
!
I
~
M
t'l
+I
.
+I
o
'"
0
c:i
AREA
,,'
M
..;
,.....
L_-+-_~
140±O.1
(17.6±0..:l)
.1
lBO± 0.25
r--
MARK
....
o
+I
...o
IC)
J
J/\
(l.2± 02)
(0.6 )
~
UUUuu UU U Ullll
~'
,
IC)
....
0
lS.2± O.S
-200-
.....
OJ
....
..;
IC)
reO
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84C30P, TMPZ84C30AP/AP.6
TMPZ84C30F, TMPZ84C30AF/AF-6
TMPZ84C30P, TMPZ84C30AP, TMPZ84C30AP-6, TMPZ84C30F, TMPZ84C30AF, TMPZ84C30AF-6
TLCS-z80 CTC: COUNTER TIMER CIRCUIT
1.
General Description and Features
The TMPZ84C30P (hereinafter referred to as CTC) is CMOS version of Z80
CTC and has been designed to provide low power operation.
The TMPZ84C30P is
fabricated using Toshiba's CMOS Silicon Gate
Technology.
The principal functions and features of the CTCs are as follows.
(1)
Compatible with the Zilog Z80 CTC.
( 2) Low power consumption
3mA Typ. (@5V @4MHz) ••• TMPZ84C30P/F
2.5mA Typ. (@5V @4MHz) ••• TMPZ84C30AP/AF
4mA Typ. (@5V @4MHz) ••• TMPZ84C30AP-6/AF-6
10uA Max. (@5V, Stand-by)
(3)
DC to 4MHz operation ••• TMPZ84C20P/F, TMPZ84C20AP/AF
DC to 6MHz operation '" TMPZ84C20AP-6/AF-6
(4) Signle 5V power supply and single-phase clock. 5V + 10%
(5)
Capable of driving Darlington transistors.
(6) Four independent countor/timer channels each of which is capable of
independently selecting Timer Mode and Counter Mode.
(7) Each channel is provided with a pres caler to divide system clock into
16 or 256.
(8)
Built-in interrupt control logical operation circuit allows priority
processing of interrupt in Daisy-chain structrure and automatic
loading of 8 bit interrupt vector on the system bus.
(9) Four channels occupy 4 successive positions in the Daisy-chain
structure.
Most significant channel is Channel 0 and least
significant channel is Channel 3.
(10)
In both modes, at the zero count, the content of the time constant
register is automatically loaded on the down counter.
(11 )
In either Counter Moder or Timer Mode, the content of the down
counter is readable by the microporcessor (hereinafter referred to as
MPU) •
(12)
Interrupt function available in z80 MPU Mode 2.
(13)
In Timer Mode, the timer operation is selectable at the rise or fall
of the starting trigger. In addition, in Counter Mode the decrement
(-1) of the content of the down counter either at the rise or fall of
external clock is selectable.
(14) Programming to generate interrupt by zero count by the down counter
in each channel is possible.
(15 )
40 pin DIP package, 44 pin Mini Flat package.
(Note)
Z80(R) is a registered trademark of Zilog Inc., U.S.A
-201-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C30P, TMPZ84C30AP/AP-6
TMPZ84C30F, TMPZ84C30AF/AF-6
TECHNICAL DATA
2.
Pin Connections and Pin Functions
2.1
Pin connections (Top View)
The pin connections of the CTC are as shown in Fig. 2.1.
D3
D2
Dl
DO
VCC
D4
D5
D6
D7
vss
CLK,/TRGO
CLY.,/TRGl
CLK/TRG2
CLK,/TRG3
CSl
CSO
RESET
RD
ZC/'TOO
ZC/'TOl
ZC/'T02
IORQ
lEO
INT
lEI
CE
MI
CLK
(a)
DIP Pin Connection
Fig. 2.1
2.2
NC
CSl
CLK,/TF\G3
CLK,/TRG2
NC
*ICV
lEO
IORQ
NO
Zqn02
ZO/TOl
*ICV
ZC/TOO
NO
OLK,/TRGl
OLK,/TRGO
NO
VOO(5V)
NO
RD
GND(OV)
D7
(Note) NC must be used at open condition.
*ICV must be used at open
Condition or Connected with Vee.
(b) MFP Pin Connection
DIP Pin Connections
Pin names and functions
I/O pin names and functions are as shown in Table 2.1.
Table 2.1
Pin Names and Functions
Pin Name I Number I Input/Output I
lof Pinl 3-state
Function
I
I
-=D~O---~D~7--+I~~8~~I~~~I~/~0~--+-~8--~b7i~t~b7id77ir-e-c-t~17·o-n-a~1~d~a~t-a~b-u-s-.---------------1
I
I
I
I
ZC/TOO
I
I
I
I
I
I
ZC/T02
I
I
I
I
I
RD
I
3-state
Input
Output
Data transfer between MPU and PIO
I
Read signal.
I
This signal is used in combination with IORQI
and CEP signals for transfer of data and
I
channel control words between MPU and CTC. I
In both counter and timer modes the output I
is an active high pulse when the downI
counter decrements to zero.
I
-202-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C30P, TMPZ84C30AP/AP-6
TMPZ84C30F, TMPZ84C30AF/AF-6
TECHNICAL DATA
Pin Name
lORQ
I Number I Input/Output I
lof Pinl
3-state
I
I
I
I
I
I
I
I
I
I
I
I
1
1
lEI
MI
I
Output
I
I
I
I
I
I
I
1
I
1
1
1
1
1
I
I
I
I
I
I
Output
1
I
1
1
1
I
I
I
I
1
I
I
I
1
1
1
1
I
I
1
Input
1
1
1
I
Input
I
I
I
1
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
CLK
I
I
I
INT
I
I
I
lEO
I
Input
I
I
I
I
1
Input
1
I
I
Function
I/O request signal.
This signal is used in combine with RD and
CE signals for transfer of data and channel
control words between MPU and CTC.
Interruption enable output.
Controls interruptions by subordinate peripheral LSI's in the' Daisy-chain structure.
This terminal becomes H level only when the
lEI terminal is at H level and MPU is not
providing the interruption service to channels in CTC.
Interruption request.
This terminal becomes L level if a downcounter for any channel in CTC counts zero
when the lEI terminal is at H level and
interruption is authorized by a program.
Interruption enable input.
This terminal indicates presence of interruption by a host peripheral LSI.
Machine cycle 1.
Informs the machine cEe from MPU.
In
combination with the ROD signal, indicates
that MPU fetches commands from the memory,
and in combination with the IORQ signal,
indicates that MPU is in the interruption
acknowledge cycle. This terminal is used,
in combination with the IORQ signal, to sendl
the interruption vector to MPU.
I
Single-phase clock input.
1
Single-phase z80 standard system clock is
I
inputted to this terminal. When this CLK
I
terminal is in the DC state (high or low
I
level), the CTC is placed in the stationary I
________-+I____~I~------__~~s~t~a~t~e~.~~-------------------------------1
I!
Chip enable.
I
CE
I 1 I
Input
Used to write MPU-CTC channel control word, I
I
I
interruption vector, and time constant or
I
to read the content of a downcounter for
I
I
I
I
I
each channel in combination with the IORQ
I
__________+I______Ir-__________+-~a~n~d~RD~7te~rm~1~·n~a~l~s~.~------------_____________ 1
I
I
Reset signal.
I
RESET
I
1 I
Input
When the reset signal is inputted to this
I
I
I
terminal, all channels stop to operate and I
interruption enable bits in all channel
I
I
I
I
I
control registers are reset. This RESET
I
I
I
terminal must be kept at L level for at
I
~~--~~rl--~~I----~------+-~le~a~st~3~s~s~t~e~m~c~1~0~c~k~s~.----_________________ 1
CSO - CSI
Input
Channel selection.
I
Anyone of four channels of the CTC is
1
I
selected by 2-bit code at time of read/
I
____~I______~__________~~w~r~i~t~e~._____________________________________ 1
I
-203-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
Pin Name I Number I Input/Output I
lof Pinl 3-state
I
i
CLK/TRGO I
r
CLK/TRG3 I
Vcc
Vss
I
I
I
I
I
I
I
I
I
I
I
4
I
I
I
Input
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I Power Supply I
I
I
I
I
I Power Supply I
I
I
TMPZ84C30P, TMPZ84C30AP/AP-6
TMPZ84C30F, TMPZ84C30AF/AF-6
Function
External c1ock/timer trigger.
There are 4 CLK/TRG terminals correresponding to 4 channe Is. At the leading or
trailing edge of active signals which are
inputted through these terminals, the content of down counter is decremented (-1) in
Counter Mode, while the timer operation is
started in Timer Mode. Active leading edge
or trailing edge is selectable.
+SV
OV
-204-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
3.
TMPZ84C30P, TMPZ84C30AP/AP-6
TMPZ84C30F, TMPZ84C30AF/AF-6
Functional Description
3.1
Block diagram
The block diagram of CTC is shown in Fig. 3.1.
INTERNAL
CONTROL
LOO ICAL
OPERATION
CIRCUIT
ZC/TOO
eLK/TROO
DATA {
DO-D7
CO~ROL{
CE
MPU BUS
I/O
LOGICAL 1~____
IN_'_rER-,NALr-B_U_S____,
OPERATION
CIRCUIT
CSO
CSI
ZC/TOI
eLK/TRGI
ZC/T02
CLK/TRG2
CLK/TRG3
lEO
lEI
Fig. 3.1
3.2
INT
Block Diagram
System cinfiguration
The system configuration of CTC consists of four logical
circuits as below.
(1) MPU Bus Input/Output Logical Operation Circuit
(2) Channel Control Logic
(3) Interruption Control Logical Operation Circuit
(4) 4 Independent Counter/Timer Channel Logical Circuit
operation
3.2.1
MPU bus input/output logical operaton circuit
This is a circuit for connecting CTC to MPU.
This circuit connects CTC
directly to MPU without using other external circuit.
However, if a
system becomes large, it becomes necessary to provided an address decoder
and a line buffer.
3.2.2
Internal control logical operation circuit
This circuit controls the overall chip operation function like the chip
enable, reset and read/write circuit.
-205-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C30P, TMPZ84C30AP/AP-6
TMPZ84C30F, TMPZ84C30AF/AF-6
TECHNICAL DATA
3.2.3
Interruption control logical operation circuit
This circuit performs processes of MPU relative to interruption such as
decision of priority, etc.
Priority of peripheral LSI's is decided according to their physical
locations in the Daisy-chain connection.
3.2.4
Counter/timer channel logical operation circuit
This counter/timer channel logical operation circuit consists of the
following two registers and two counters.
The figures shown in
parentheses is number of bits. The configuration of this counter/timer
channel logical operation circuit is shown in Fig. 3.2.
o Time constant register (8-bit)
o Channel control register (8-bit)
o Downcounter (8-bit)
o prescaler (8-bit)
CHANNEL CONTROL
TIME CONSTANT
REGISTER(S BITS)
REGISTER(S BITS)
INTERNAL BUS
SYS TEM CLOCK
PRESCALER
DOWN COUNTER
(s BITS)
ZC/TO
(s BITS)
f
CLK/TRG
Fig. 3.2
Counter/Timer Channel Logical Circuit
(1)
Timer constant register
This register retains time constants that are written into the downcounter.
When the eTC is initialized or the downcounter counts zero,
time cons-tants are loaded on the downcounter.
Time constants are set
immediately after MPU writes channel control word into the channel
control register. Time constants that can be set are integers ranging
from 1 to 256.
(2)
Channel control register
This register selects channel modes and conditions by the channel control
word provided from MPU.
(3)
Downcounter
-206-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84C30P, TMPZ84C30AP/AP-6
TMPZ84C30F, TMPZ84C30AF/AF-6
The content of the time constant register is loaded on this downcounter
and its content is decremented (-1) at every edge of external clock in
case of Counter Mode and for every clock output of the prescaler in case
of TUner Mode. The content of the time constant registger is loaded at
time of initialization and when the downcounter counts zero.
The content of the downcounter can be read out anyt ime. In addi t ion, it
is also possible to program so as to generate an interruption request
every time when the down counter counts zero.
(4)
Prescaler
The prescaler is used only in Timer Mode and divides the system clock
into 1/16 or 1/256. Whether the system clock is to be divided into 16 or
256 is programmed by the channel control word.
Further, output of the
prescaler becomes clock input to the downcounter.
3.3
Basic operation
3.3.1
Reset
After power ON, the CTC is in the unstable state. To stabilize the CTC,
apply a signal of L level to the RESET terminal.
Before starting any
channel in Counter Mode or Timer Mode, it is necessary to write the
channel control word and time constant data into the registers for the
channel to be started.
In addition, to make a programming to enable
interruption, it is necessary to write the interruption vector words into
the interruption control circuit. When these data are written into the
CTC, it becomes ready to start.
3.3.2
Interruption
The CTC is capable of producing the interruption while MPU is operating
in Mode 2.
The interruption by the CTC can be programmed for each channel and the
interruption request signal (INT) is output every time when the
downcounter of each channel counts zero.
When MPU accepts the
interruption request from the CTC, the CTC outputs the interruption
vector.
Based on this interruption vector, MPU designates the top
address of the interruption processing routine and MPU starts the
interruption process by calling this interruption processing routine.
Since MPU designates the top address of the interruption processing
routine by the interruption vector received from the CTC, users can call
optional address by changeing this vector value.
The interruption process is ended when MPU executes RETI command. The
CTC is provided with the RETI command decoding circuit and is therefore
able to know end of the interruption process by constantly monitoring the
data bus.
Interruption priority among peripheral LSls is decided by their
connection in the Daisy-chain structure.
Peripheral LSIs are connected
in series and higher priority is given to peripheral LS Is wh ich are
located physically more closer to MPU.
Further, as to the priority of
channel in the CTC, the highest priority is given to channel 0 and
priority beocmes lower in order of Channel 1, 2 and 3.
-207-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C30P, TMPZ84C30AP/Ap·6
TMPZ84C30F, TMPZ84C30AF/AF-6
TECHNICAL DATA
Peripheral LSI's have the signal lines for
the lEO terminal of a host peripheral
terminal of a subordinate peripheral LSI.
peripheral LSI with the highest priority
termin&l and the lEO terminal of a lowest
used.
Interruption under this condition
following rules:
o
o
o
o
o
3.3.3
the lEO and lEI terminals, and
LSI is connected to the lEI
However, the lEI terminal of a
is connected to the +5V power
priority peripheral LSI is not
is generated according to the
When the lEO and lEI terminals are both at H level, no interruption is
generated.
At this time, the INT terminal is at H level.
In this
state, the interruption request can be available.
When the CTC output the interruption request signal (INT), this CTC
resets the lEO terminal to L level. When the interruption is accepted
by MPU, the INT terminal returns to H level.
When the lEI terminal becomes L level, the lEO terminal also becomes L
level.
When the lEI terminal is at L level, no interruption request can be
available.
If the lEI terminal is turned to L level while the interruption is
generating, the interruption process is kept suspended.
Operation Modes
The CTC is operated in
Selection of these modes
word.
o Counter Mode
o Timer Mode
the following alternative operation modes.
is performed by wri t ing the channe 1 control
(1)
Counter mode
In counter mode, number of input edges at the CLK/TRG terminal is counted
and after inputting pulses.
The content of the downcounter is
decremented by -1 synchronizing with the rise of next system clock.
Pulse edge to be counted can be designated either at the leading or
trailing edge by the channel control word.
When the content of the downcounter becomes zero, time constant data that
are written into the time constant register are automatically loaded into
the downcounter.
To load new time cons tant da ta into the downcounter,
new time constant data is written into the time constant register. These
new data will be loaded after the present counting operation is ended.
(2)
Timer mode
In timer mode, a time interval of integral number times of the system
clock cycle is generated.
The time interval is measured on the basis of
the sys tem clock, and sys tem clock is suppl ied to the presca ler.
The
pres caler divides this system clock into 1/16 or 1/156.
Further, output
of the pres caler is used as the clock to decrement (-1) the downcounter.
Time constant data is automatically loaded onto the downcounter every
time when the downcounter counts zero in the same manner as in Counter
Mode.
When the content of the downcounter is reduced to zero, pulse in the
fixed cycle is output from the ZC/TO terminal.
This pulse is given by the following formula:
-208-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
tc
*
P
*
TMPZ84C30P, TMPZ84C30AP/Ap·6
TMPZ84C30F, TMPZ84C30AF/AF·6
TC
tc : System clock cycle
P : Prescaler value (16 or 256)
TC : Time constant data (256 at OOH)
Whether the starting of the timer operation is automatically mode or
perforured at the edge of the CLK/TRG terminal and case of the CLK/TRG
terminal, whether it is performed at the leading edge or trailing edge is
designated by the channel control word.
3.4
Status change flowchart and basic timing
3.4.1
Status change flowchart
The status change flowchart of CTC is shown in Fig. 3.3
-209-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
'>---------------------,
NO
l"VBL
<
JUDOMENl
cO::f!r~L
Of!'
/>-----.-~..,
~HANNEI,
IJOWNC{)!IN'II';I(
..... !)?
TMPZ84C30P, TMPZ84C30AP/ AP-6
TMPZ84C30F, TMPZ84C30AF/AF-6
CONTtWL
WUH U . -_ _- ' -_ _ _- ,
'>--------..,
NU
Fig. 3.4 (a)
Status Change Flowchart of CTC
-210-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
Fig. 3.4 (b)
3.4.2
TMPZ84C30P, TMPZ84C30AP/AP-6
TMPZ84C30F, TMPZ84C30AF/AF-6
Status Change Flowchart of PIa
Write cycle
The write cycle is used for writing channel control word, interruption
vector and time constant.
In the next system clock T2, MPU changes the IORQ terminal of eTC to L
level and starts the write cycle. At time of starting the write cycle, a
2-bit code is added to the eSl and eso terminals of the eTC to designate
a channel.
The eTC internal registers are ready to secure data at the
system clock T3. Tw is in the waiting state which is automatically added
by MPU.
-211-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C30P, TMPZ84C30AP/AP-6
TMPZ84C30F, TMPZ84C30AF/AF-6
TECHNICAL DATA
Tl
T2
T3
TW
Tl
CLK
CSO,CS1.CE
=x
x:=
CHANNEL ADDRESS
IOR"~~
DATA
_____)(~____l_NI_'U_T__~)(~_____
Fig. 3.5
Write Cycle Timing
3.4.3
Readout cycle
The read cycle is used to read out the content of the downcounter.
At the system clock T2, MPU sets the RD and IORQ terminals of the CTC at L
level and starts the read cycle. At time of starting the read cycle, a 2-bit
code is added to the CSI and esa terminals of the eTC to designate a channel.
The content of the down counter at time of the rise of T2 is output to the data
bus at the rise of the system clock Tw.
Tw is the waiting state which is
automatically added by MPU.
Tl
T2
TW
T3
Tl
eLK
CSO,CSl,C~ ~~____C_'I_IA_N_N_I':_I'__A_U_Ui_("_~'_"_'____ ><===
\'----~/
\
/
Fig. 3.5
Read Timing
DATA
-212-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C30P, TMPZ84C30AP/AP-6
TMPZ84C30F, TMPZ84C30AF/AF-6
TECHNICAL DATA
3.4.4
Counter mode
In counter mode, the content of the downcounter is decremented (-1)
synchronizing with the system clock by the edge of pulse added from the
external circuit connected to the CLK/TRG terminal.
Cycle of the pulse
added t.o the CLK/TRG terminal must be larger by two times or more than
the system clock.
In addition, a setup time becomes necessary between
the active edge of the CLK/TRG terminal and the rise of next system
clock.
If a setup time between the active edge of the CLK/TRG terminal
and the rise of next system clock is short.
The downcounter decrements
its content by one (-1) one cycle behind the system clock.
When the content of the downcounter becomes zero, H level pulse will be
output from the ZC/TO terminal.
CLK
CLK/TRO
INTERNAL
COUNTER
ZC/TO
Fig. 3.6
3.4.5
Counter Mode Timing
Timer mode
The timer operation is started by the second rise of system clock at the
edge of pulse added from the external circuit conneced to the CLK/TRG
terminal.
Cycle of the pulse added to the CLK/TRG terminal.
Cycle of
the pulse added to the CLK/TRG terminal must be larger by two times or
more than the system clock.
In addition, a setup time becomes necessary
between the active edge of the CLK/TRG terminal and the rise of next
system clock.
If a setup time between the active edge of the CLK/TRG
terminal and the rise of next system clock is short.
The timer starts
one cycle behind the system clock.
CLK
CLK/TRO
INTERNAL
TIMER
TIMER OPERATION
START
Fig. 3.7
3.4.6
Timer Mode Timing
Interruption acknowledge cycle
After transmitting the interruption reqeust signal (INT), the PIa sets
the lEO terminal at L level to inhibit interruption request by low order
LSI.
-213-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C30P, TMPZ84C30AP/AP-8
TMPZ84C30f, TMPZ84C30Af/Af-6
TECHNICAL DATA
Receiving the interruption request signal (INT) from the eTe, MPU sets
the MI and IORQ terminals of the eTe at L level as the interruption
acknowledge signal. The IORQ terminal becomes L level later than the MI
terminal by 2.5 system clocks.
In order to stabilize the daisy chain
connected signal lines, lEI and lEO signals, each channel cannot change
interruption requests.
The RD terminal is kept at R level to distinguish the command fetch cycle
from the interruption acknowledge cycle.
During this period, the
interruption control logical operation circuit in the eTC decide the most
high order channel requesting the interruption.
If the IORQ terminal
becomes L level when the lEI terminal is at H level, interruption vector
is output to the data bus from the most high order channel requesting the
interruption
At this time, 2 system clocks are automatically inserted by MPU as the
waiting state to keep stability of the daisy chain connection.
Tl
T2
TW
TW
T3
T4
eLK
Ml
\ '--____---JI
\
lORQ,
I
RD
lEI ~ ~ _-_-_____
=]
~~-------
DATA
Fig. 3.8
3.4.7
Interruption Acknowledge Timing
Return from the interruption cycle
Return from the interruption is effected when MPU executes RETI command.
This RETI command must be used at the last stage of the interruption
processing routine. The execution of this RETI command by MPU returns
the lEI and lEO terminals of the eTe to the state before interruption.
RETI command is a two byte command and its code is EDR and 4DR. The eTC
decodes the codes of RETI commllDd and decides a port which makes next
interruption request. In the daisy chain structure, at the point of time
when the command code EDR is decoded, the lEI terminal of a peripheral
LSI making the interruption is kept at H level and the lEO terminal at L
level.
If the code following EDR is 4DR, an LSI that transmitted the
interruption immediately before the decoding, that is, only the LSI with
lEI terminal at R level and lEO terminal at L level is returned from the
interrupt ion.
As a result, the interruption process of a low order
peripheral LSI of which interruption process was suspended.
-214-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C30P, TMPZ84C30AP/Ap·6
TMPZ84C30F, TMPZ84C30AF/AF·6
TECHNICAL DATA
eLK
---J/
\'-_--..J/
t.lI \ ' -_ _
ED
lEI
- - - - - - - --/r------------
_______ J
r
lEO _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Fig. 3.9
Interruption Return Timing
3.5
Operating procedures
In order to operate the CTC in Counter Mode or Timer Mode, a channel
control word and time constant data must be written into the CTC.
To
authorize any interruption by a channel control word, the interruption
vector must be written into the ~TC.
(1)
Channel control word
To write a channel control word into the CTC, designate a channel by
inputting a 2-bit code into the LSI terminal and the LSI terminal. Codes
for respective channels are shown in Table 3.1.
Table 3.1
I
I
I
I
0
I Chan-l
I
I
I Chan-I
2
3
Channel Codes
InEut Terminal I
CSl
I CSO I
0
I 0
I
0
0
I
I
1
I 0
I
1
1
I
I
The channel control word is written into the CTC is 8 bits.
The system
data bus DO to D7 correspond to bit 0 - 7.
The meaning of each bit is outlined in Fig. 3.10.
The function of each
bit is shown in Table 3.2.
D7
InterrUEtion
D6
Counter
timer
DS
Prescaler
Fig. 3.10
D4
Edge
D3
Trigger
D2
Time
constant
D1
Reset
Channel Control Words
In case of the channel control word, DO must always be 1 (DO=1).
-215-
DO
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C30P, TMPZ84C30AP/AP-6
TMPZ84C30F, TMPZ84C30AF/AF-6
TECHNICAL DATA
Table 3.2
Bit
Meanings and Functi6ns of Channel Control Words
o
Meaning and Functon
Channel interruption is inhibited.
Bit
7
(Dn
Bit
6
I(D6)
I
I
A channel is mode in timer
mode.
System clock is input into
the prescaler divided and
output to the downcounter.
I Authorizes channel interruption.
I In either counter mode or timer
I mode, this bit requests the interI ruption to MPU whenever the content
I of the downcounter becomes zero.
I If this bit is set at 1, the interI ruption vector must be written into
lithe CTC before starting the downI counter. Further, if the channel
I control word with this bit set to
I it is written into the CTC. The
I interruption is generated when the
I content of the downcounter becomes
I zero first after a new channel
I control word is written.
I A channel is made in counter mode.
I The content of the downcounter is
I decremented by 1 (-1) at every edge
I of each trigger that is input into
I the CLK/TRG terminal. The prescaler
I is not used in counter mode.
I~B~i-t-+-U~se-d~o-n~l~y--i~n--t~i~m-e-r--m-o~d-e-.-----+I-=U~se-d~o~n~l~y~i~n~t~i~m~e~r~m~o~d-e~.~=T~he--------
I 7
I(D7)
The pres caler is set so as
to divide the system clock
I prescaler is set so as to divide the
I system clock into 1/256.
____-r~i~n~t~0~1~/~16~.~~------~------+I~--~----~--~--~--------~~--
I
I
I
I Bit
I 4
l(d4)
I
I
In timer mode, the timer
I-'In timer mode, the timer operation
operation is started at the
I is started at the leading edge of
trailing edge of the trigger I the trigger pulse (CLK/TRG).
pulse (CLK/TRG).
I In counter mode, the content of the
In counter mode, the content I downcounter is decremented by one
of the downcounter is deI (-1) at the trailing edge of the
cremented by one (-1) at the I external clock pulse.
trailing edge of the external I
1____~~c~10~c~k~~u~l~s7e-(~C~LK~/~T~RG~)~.~----~I~~~~~~~~----~--~--~--_
Bit
3
(D3)
Used only in timer mode.
The timer operation is
started at the leading edge
of the trigger pulse clocks
after a time constant is
loaded onto the downtimer.
Used only in timer mode. The timer
operation is started at the leading
edge of the external trigger pulse
that is input 2 system clocks after
a time constant is loaded onto the
downcounter.
When a time lag between the system
clock and trigger pulse satisfies a
setup time, the prescaler starts to
operate from the second leading
edge of the trigger pulse. If a
time flag between the system clock
and trigger pulse does not satisfy
the setup time. The prescaler
--216--
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C30P, TMPZ84C30AP/AP-6
TMPZ84C30F, TMPZ84C30AF/AF-6
TECHNICAL DATA
I Bit
Meaning and Functon
I____~----------~O----------_r--------------~~~~~---starts to operate at the leading
I Bit
edge of the trigger pulse after 3
I 3
system clocks. If the trigger pulse I
is inputted before leading of a time I
I (D3)
constant, the operation is the same I
I
1____~~~--~~~~~~~~--~--~_T~a~s~~th~a~t~w~h77e~n~B~i~t~3~=~0~.~~~~--~c-I
I
This bit (0) indicates that
This bit (1) indicates that there isl
I
there is no time constant
a time constant written immediately I
written after a channel can
after a channel control word. If a I
I
trol word. However, the chan-I time constant is written while the I
I
nel is in the reset state andl downcounter is operating, a new timel
I
I Bit
this bit cannot be changed tal constant is set in the time constantl
I 2
"0" in the channel control
I register. The counting which is in I
word which is given first
I progress is carried out continuously I
I (D2)
after the channel reset.
! and only after the content of the
I
I
To change other state withoutl downcounter becomes zero, a new timel
I
I
changing a time constant,
I constant is loaded onto the downI
input a channel control word I counter.
I
I
1____~~w~i~t~h~t~h~i~s~b~i~t~c~h~a~n~g~e~d~t~o~O~.~_T1-=~~______~________~__~__________ I
I
The present channel operationl The downcounter operation is stop- I
is continued.
I ped. When this bit is set to 1,
I
I
I
I
I the channel operation is stopped
I
I but all bits in the channel control I
I
I
I register remain unchanged.
I
I When Bit 2=1 and Bit 1=1, the chan- I
I Bit
I nel stops to operate until a new
I
I time constant is written. After a I
I 1
I (Dl)
I new time constant is programmed, thel
I
I preparation for reopening the chanI
I nel is performed and the channel is
I
I reopened according to a value set
I
I for Bit 3. When Bit 2=0 and bit 1=
I
I 1, the channel operation is not
I
I started until a new channel control
1____~______________________________~I_w~o~r~d___
i~s_w~r~i~t~t~e~n~._____________________
(2)
Time constant data
In timer mode or counter mode it is necessary to write time constant data
into the time constant register.
When the channel control word Bit 2 (D2) is 1, time constants are written
into the time constant register immediately after the channel control
word is written. Time constant data are integers in the range from 1 to
256. When 8 bits of this data are all 0, it is regarded as 256.
The bit configuration of time constant data is shown in Fig. 3.11.
D7
D6
D5
D4
D3
D2
Dl
DO
TC7
TC6
TCS
TC4
TC3
TC2
TC1
TCO
Fig. 3.11
Time Constant Data
-217-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C30P, TMPZ84C30AP/AP-6
TMPZ84C30F, TMPZ84C30AF/AF-6
TECHNICAL DATA
(3)
Interruption vector
In the interruption when MPU is in Mode 2, it is necessary for the
channel requesting the interruption to give the interruption vector to
MPU.
The interruption vector is written into the interruption vector
register for Channel 0 with Bit 0 (D» set to O. The write method is the
same as that to write the channel control word into Channel O.
However,
bit 0 (DO) must be always zero.
Bit 7 (D]) to Bit 3 (D3) are values
given by user. Bit 2 (D2) and Bit I (Dl) are values given automatically
by the CTC and a code of a channel with the highest priority among
channels requesting the interruption is used.
The channel codes are
shown in Table 3.3 and the bit configuration of interruption vector in
Fig. 3.12.
Table 3.3 Channel Codes
Bit 1 (D!)
0
1
0
1
Bit 2 (D2)
0
0
I
1
V7
V6
vs
V4
V3
Fi.g 3.12
Channel No. I
I~ High
0
Prior1
II
2
II Low ity
3
Iv
x
x
I
I
o
T _ _ __
Fix to "0".
Chennel codes
Interruption vector given
by user.
Interruption Vector
3.6
(1)
Method of use
Counter mode
A program when the interruption disabled is
explained.
(a) The programming step is shown in fig. 3.13.
Fig. 3.13
set
Counter Programming Step
-218-
using
Channel
0
is
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C30P, TMPZ84C30AP/AP-6
TMPZ84C30F, TMPZ84C30AF/AF-6
TECHNICAL DATA
(b)
The block diagram to change 100 KHz to 10 KHz is shown in Fig. 3.14.
CHANNEL 0
PRESCALER
TIME CUNSTANT
HEOISTER
NOT USED
10
II A TIME CONSTANT IS LOADED EVERY TIME
WHEN THE DOWNCOUNTER COUNTS ZERO.
I
CLK/TRGO(100I(N-2)TdIEI(IEOf)+(TdMl(IEO)+TsIEI+TTL buffer delay must
be satisfied.
(1) :Tcc, (9) :Tdc(INT), (26) :TsCTR(Cs)
Capacitance
TA = 25 0 C
SYMBOL !
ITEM
CCLOCK I Clock Input
I CaEaci tar,ce
CIN
I InEut CaEacitancel
COUT IOutEut CaEacitancel
TEST CONDITION
!MIN.!TYP.!MAX.!UNITI
f=1MHz
pF
5
All terminals except that
to be measured should be
5
I2F
- 10 I2F
earthed.
-223-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C30P, TMPZ84C30AP/Ap·6
TMPZ84C30F, TMPZ84C30AF/AF·6
TECHNICAL DATA
4.5
Timing diagram
Numbers shown in the following figures correspond with those in the 4.3
A.C. Electrical Characteristics Table.
Ci)
-®
CLK
J
~ ~·~rwrL
(g)
.
(VC80,081
I
I
.
~
I
\.
CE
J6lJ
(:7)
-y
L®._
REA D
lORQ
Rii
-~
I
.~
'I.
I
-~
.llJ
I
- f~
Lw_ I
DATA
I
l
_.
~
(~
[
I
I
XL
I
~...J
DATA
" j-
1 )(
L(c!.!
4~--l--
I
Ml
INTERR
ACKNOW LEDGE
t!4JL::;.J,5)
I
~
(tp
'1
Ogl
(j!J)
'1
INT
MODE)
~J
-.J
~
~L.
(TIMER
MODE)
---'f-~
Jt
~
iL
W
I
If
2C/TOO-2
Fig. 4.1
Timing Diagram
-224-
1X
-~
¢:U
eLK/TROO-3
1
-H-@
lEI
(COUNTER
'1'--
(5)-4-1-
DATA
eLK/TROO-3
(6)
~ r-
~
\
lORQ
lEO
!!:?J
(§.)-~
I
,
J
~i
~,
I
IORQ;
I
j y
- j-
I
d---@
'i
WRI TE
I
(Jl)
A
eso,e81
CE
-j
\t
f?)
\.
-= ~
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C30P, TMPZ84C30AP/AP-6
TMPZ84C30F, TMPZ84C30AF/AF-6
TECHNICAL DATA
5.
Package Dimension
Unit in mm
5.1 DIP Package
28
15
]
~
OJ
.,;
1
14
1,5.24 ± 0.2"
3 80 MAX
I
,'1
"
U
z
H
:>l
Col
o 5±0.15
2.54±0 25
II
1.4±015
U --l~
t')
Note 1.
Note 2.
+ 01
025_ 005
0
This dimension is measured at the center of bending point of
leads.
Each lead pitch is 2.54mm, and all the leads are located within
±O.2Smm from their theoretical positions with respect to No.1
and No.28 leads.
Fig. 5.1
Package Dimension
-225-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C30P, TMPZ84C30AP/AP-6
TMPZ84C30F, TMPZ84C30AF/AF-6
TECHNICAL DATA
Unit in
5.2 44-pin mini-flat package
035
llitoS(Plt{,h)
--------------~
-----r
21~
~
I
rl
o
-H
o
.",
rl
140±Ol
(17.6±( ...l)
.1
lBO±025
~.
~
lURK
o
+l
It)
.....
o
J
1/\
(l~±0.2)
(0.6 )
rl
""
UUUU[J1 UUlIllUU
"\
'"c:i
rl
15.2± 0.3
-226-
~
ox
rl
~
"'Nl'-
111m
TOSHIBA INTEGRATED CIRCUIT TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/AP-&
TECHNICAL DATA
TMPZ84C43F/TMPZ84C43AF/AF-&
TMPZ84C40P/41P/42P/43F TMPZ84C40AP/41AP/42AP/43AF TMPZ84C40AP-6/42AP-6/43AF-6
TLCS-Z80 510: SERIAL INPUT/OUTPUT CONTROLLER
1.
General Description and Features
The TMPZ84C40 (510/0) , TMPZ84C41 (510/1) , TMPZ84C42(SlO/2)
(hereina fter
referred to as 510) are CMOS version of Z80 510 and have been designed to
provide low power operation.
SIOs are designed for the adaptation to the various serial data
communications which are needed to the microcomputer system.
SIOs are able to handle the asynchronous signal, the synchronous byte unit
protocol and the synchronous bit unit protocol like HDLC and SDLC.
SIOs are fabricated using Toshiba's CMOS Silicon Gate Technology.
The principal functions and features of the S10s are as follows.
(1)
Compatible with the Zilog Z80 510.
(2)
Compatible with the CCITT-X.2S.
(3)
Compatible with the HDLC/SDLC.
(4) Data transfer rate up to 800K bit/Sec
(5)
2 independent full-duplex channels can be used.
(6)
Built-in CRC generation and checking function.
(7) On chip daisy-chain structure interrupt circuit.
(8) Low power consumption
rnA Typ. (@5V @4MHz)
TMPZ84C40/41/42P, TMPZ84C43F
2.SrnA Typ. (@SV @4MHz)
TMPZ84C40/4l/42AP, TMPZ84C43AF
4 rnA Typ. (@5V @4MHz)
TMPZ84C40/41/42AP-6, TMPZ84C43AF-6
(9)
Single power supply: SV + 10%
(10)
Extended operating temperature: -40 o C to 85°C
(11 ) 40 pin DIP package, 44 pin Mini Flat package.
(Note)
Z80(R) is a registered trademark of Zilog Inc., U.S.A.
-227-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/AP-6
TMPZ84C43F/TMPZ84C43AF/AF·6
TECHNICAL DATA
2.
Pin Connections and Pin Functions
The pin connections, pin functions and functions of SIOs are described in
this chapter.
2.1
Pin connections
The pin connections of the SIOs are as shown in Fig. 2.1.
Dl
D3
DO
D2
D4
D6
lOR"
D5
D?
INT
lEI
lEO
B/A
e/Ii
RXDA
RXCA
illA
TXDA
DTRA
iffilA
CTSA
DCDA
CLK
CE
B/A
e/ll
MI
Rb
Vec
W/RDYA
V/S(OV)
W RDYB
SYNCE
RXDB
RXfXClj
TXDB
DTRB
RTSB
CTSB
ffiCA
lEI
lEO
Dl
D3
D5
D?
INT
lEI
lEO
D4
MI
RD
W/~
DO
D2
D6
lOR"
DE
MI
Dl
D3
D5
VCC
W/RDYA
SYNCA
RXDA
VS~
W/
S\'1ICIi
RXDA
SYNCE
RXDB
RXCB
TXCB
TXDB
RTSB
CTSB
DCDB
RESET
RXCA
TXCA
TXDA
DTRA
!JCi'iB
RESET
R.XCA
'fJfCii
TXDA
DTfiA
RTSA
CTSA
DCDA
CLK
I~ ~ ~ ~
1m
VS~
W/
RXDB
RXCB
=
TXDB
DTRB
RTSB
CTSB
DCDB
RESET
(TMPZ84C42)
(TMPZ84C41 )
(TMPZ84C40)
DO
D2
D4
D6
lOR"
CE
B/A
e/ll
~ ~I&
rl 0 0 N
HAA~AZAAAAH
3332 31 30 2928 272625 24 23
lEI
lEO
CE
34
B/A
c/15
M1
RD
VSS
*
* ICV
ICV
SYNCA
RXDA
W7Rl5'l'B
SYNOB
RXDB
TXOA
RXcB
TXDA
TXCB
I~ ~I~I@ ~III@I~I~ ~I~
(Note 1) NC must be used at
open condition.
(Note 2) *ICV must be used at
open condition or
connected with VCC.
(TMPZ84C43 )
Fig. 2.1
Pin Connections (Top View)
-228-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41,42P/TMPZ84C40,41,42AP/AP-6
TMPZ84C43F/TMPZ84C43AF/AF-6
TECHNICAL DATA
However, it is necessary to choose the terminals in accordance with the
purposes, because they are limited in number. The differences in 510/0,
510/1 and 510/2 are shown in Fig. 2.2(a) SIOs version diagram.
29
5YNCB
S'INC1l
29
28
RxDB
28
RxDB
28
RxCB
27
Rxl'xCB
27
HxCB
27
TXCIi
26
TxDB
26
TxCB
26
TxDB
DTRB
25
TxDB
25
DTRB
25
510/0
510/0
Fig. 2.2(a)
2.2
RxDB
510/0
SIOs Version (40-pin DIP)
How to use TMPZ84C43 as 510/0 or 510/1 510/2.
The Figure 2.2(b) shows six terminals to define TMPZ84C43 as 510/0 or
510/1 or 510/2.
TMPZ84C43
15
S""YNCi3
14
RXDB
13
'Rx'CB
12
TXCB
10 11
I~
Fig. 2.2(b)
III
~
~
E-<
Pinout of TMPZ84C43 "B" Channel
-229-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/AP-&
TMPZ84C43F/TMPZ84C43AF/AF-&
The following table shows five terminals (No.25
40-pin DIP corresponding to these of TMPZ84C43.
Table 2.1
through
29)
of
SIO
in
SIOs Version by TMPZ84C43
Terminal No. I
of SIO in 401
Ein DIP
I
TMPZ84C43
as SIO/2
as SIO/O
as SID/1
I
B
A3
Al
I C
I B I C
I B
I C
I A2
I
I
I
I
I
I
I
I
10
25
I Output I DTRB
10utputi
I DTRB
10utputlTxDB
I 10
I 11
I
I
I
I
I
I
I
I
I
I Input I TxDB
11
10utputi
26
I TxDB
I Output I TxCB
I 12
I 11
I
I
I
I
I
I
I
I
27
IRxTxCBI*
12
I Input I
I Input IRxCB
I Input ITxCB
I 13
INote 11
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
28
I RxDB
I Input I RxDB
I Input IRxCB
13 IInput I
I 14
I 14
I
I
I
I
I
I
I
I
I
I SYNCB I 15
I RxDB
14
I Input I
I SYNCB I 15
29
1**
1**
INote 21
INote 21
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I (Note)
I(Note)
I
I
I SYNCB (terminal
I DTRB (terminal
I number 10) will not I number 15) will notl
I
I be used.
I be used.
I
I The terminal is
I The terminal may
I pulled-up internal-I
I be open.
I
I ly, so it may be
I
I
I o!:'en.
I
AI: Signal Name of SIO/O A2: Signal Name of 510/1 A3: Signal Name of 510/2
Terminal No. of TMPZ84C43
In/out
B:
C:
*Note 1)
**Note 2)
The terminal No.12 (TxCB) and No.13 (RxCB) must be connected
externally when TMPZ84C43 will be used as 510/0.
Bi-directional
-230-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
2.2
TMPZ84C40,41,42P/TMPZ84C40,41,42API Ap·6
TMPZ84C43F/TMPZ84C43AFI AF·6
PIn Names and !unctions
Table 2.2
Pin Names and Functions
1 Pin Name
1Number 1 Input/Output 1
Function
1
1~~__~__rlo~f~p~i~n~I~~3~-~s~t~a~t~e__-+~~~~~~__~__~~__~_________________ I
1 DO - D7
I 8 1
I/O
8-bit bidirectional data bus.
1
1
1
I
3-state
1
1
1
1
Interrupt request signal.
1
lINT
1
1
Output
This is used, in case SlOs request MPU
1
1
l i t h e interrupt. Wired OR connection is
1
1
I
1
possible (becuase of the open drain).
1
1
1 lEI
1
1 lEO
1
1
1
1
1
1
1
1
1
1
1
1
1
I
1
1
1
1
Ml
W/RDYA
W/RDYB
SYNCA
I*SYNCB
1
1
I
1
1
1 RxDA
1 RxDB
1
1
I
1
1
1
1
1
1
1
1
1
1
I
I
1
1
1
1
1
1
1
1
Input
Output
*2
1
Input
1
1
1
TxDA
TxDB
DTRA
I*DTRB
1
1
1
1
1
1
I
Output
Receive clock signal.
In asynchronous mode, pins can choose the
receIve clocks which are 1, 16, 32 and 64
times as large as the data transfer rate
accordin to the ro ram.
Serial transmit data
1
1
1
1
1
1
1
1
1
Interrupt enable input signal.
Interrupt enable output signal.
lEI and lEO are used for the daisy-chain
structure. When lEI terminal is "1" and lEal
terminal is "0" the S10 IS being serviced byl
a MPU in terrupt SerVIce rout ine.
1
I
I
Machine cycle 1.
1
1
1
Input
When the both of Ml and lORQ are "0", the
1
SlO is requesting the interrupt.
1
1
1
Wait/ready signal A, wait/ready signal B.
1
1
1
1
2 1
Output
These can be used as wait signal or ready
1
1
1
signal according to SIOs-programming.
1
S10 becomes active on "0", when pins are
1
1
1
programmed as "WAIT" and are not ready to
1
1
1
receIve the data for MPU.
1
1
1
1
1
SIO become active on "0", when pins are
1
programmed as "READY" and ready to receive
1
1
1
I
the data character for DMA.
1
1
Synchronous signal.
1
1
1
1 *2
1
I/O
In case of the asynchronous receive mode,
1
1
1
These pins become the same input terminals
1
l i a s CTS and DCD.
1
1
1
In case of the external synchronous mode,
1
1
1
pins become the input terminals and in case 1
of the internal synchronous mode, become
1
1
1
l i t h e output terminals.
1
I 2 1
Input
Serial receive data
1
1
I
RxCA
I*RxCB
I
1
1
1
2
Output
Data terminal ready signal.
These pins output the possibility or impossibility of the serial data receive.
-231-
1
1
I
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
I Pin Name I Number I Input/Output I
TMPZ84C40,41 ,42PnMPZ84C40,41,42AP/ AP.6
TMPZ84C43F/TMPZ84C43AF/ AF·6
Function
I
_________~o~f~P~in~I~3~-~s~t~a~te~_+I~----~--------~--~------------------I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
RTSA
RTSB
l
I
I
I
I
I
I
I
I
I
I
I
I
2
I
I
I
I
I
I
I
Output
I
I
I
I
I
I
I
Transmit request signal.
In serial data transmi t, become "0".
Transmi ttable signal.
When terminals are "0", SIOs can receive the
serial data transmit of the modem which has
sent these signals.
I
I Da ta carrier de tect signal.
DCDA
2 I
Input
I When terminals are "0", SIOs can enable the
I
I serial data transmi t.
CLK
I
Input
I Single-phase clock input.
I
I Inputs Z80 standard system clock of singleI
I phase. When CLK termina 1 is DC s ta te ("1"
I
I
I or "0"), SIOs are in stationar sate.
I
I
I 1/0 request signal
1 IORQ
1
Input
I In case both of IORQ and CE are "0", the
I
I
I data or command are transferred between MPU
I
I
I and 510 by the combination of B/A and C/O.
I
I
I Chip enable signal
1
Input
I When input becomes "0", SIOs are enabled.
I CE
I
I
I Channel select signal
1 B/A
I
Input
I Selects the channel (A/B).
I
I
I Command/data select signal
Input
I Selects the command and data.
I C/O
I
I
I
I Read signal.
I RD
I
Input
I In case both of CE and IORQ are "0", if RD
I
I
I is "a" this pin performs the read operation
I
I
I and if'RD is "1", this pin performs the
1__________r-____~I------------+I-w~r~l~·t~e~o~p~e~r~a~t~i~o~n~.----_______________________
I
I
I Reset signal.
I RESET
I
Input
I If RESET is turned into "0", the receiver
I
I
I and transmitter become disabled and the
1__________r-____~I------------+I~se~r~l~·a~l~d~a~t~a~b~e~c~o~m~e--t-h~e__
m~a_r_k__
s_ta~t_e~.__________
CTSA
CTSB
2
I
1
I*RxTxCB
I
I
Output
Vcc
*1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Input
I
I Power
I Bonding terminal of TxCB and RxCB.
I
Supplyl +5V
I-------r----rl--------rl______________________________
I
I
I
I Vss
IPower Supply I OV
I------~--~I--------~I-----------------------------The asterisk (*) mark is difference in accordance with the three versions
(510/0, Sro/l, Sro/2).
-232-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
3.
TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/Ap·6
TMPZ84C43F/TMPZ84C43AF/ AF·6
Functional Description
3.1
Block diagram
INTERNAL
CONTROL
CIRCUIT
READ/WRITE
REGISTER
(CHANNEl, A)
co NTROL BUS
,.-v
--->..,
DATA BUS
<
,----J..,
r
MPU
BUS
I/O
INTERNAL BUS
f--I-- } DATA
CHANNEL A
CLOCK
I---- SYNC
f--- WAIT/READY
r--
f--EXTERNAL
fCONTROL
I-CIRCUIT
(CHANNEL A I - -
~ CHANNEL B
r--'"
I-- } DATA
t--f-- CLOCK
I--- SYNC
I----
INTERRUPT
CONTROL
CIRCUIT
READ/WRITE
REGISTER
(CHANNEL B)
Fig. 3.1
I-CONTROL
I-CIRCUIT
(CHANNEL B) f--
LJ., EXTERNAL
"-----01
r-
WAIT/READY
1
CONTROL LINE
Block Diagram
3.2
System configuration
3.2.1
Architecture
As shown in Fig 3.1, the 510 is composed of MPU bus inter face, the
internal control circuit, the interrupt control circuit and two fullduplex channels which operate independently.
Each channel has the read
regis ter, the wri te register and the external con tro 1 c ircui t wh ich is
conneced to the peripheral LSI or the external device.
Table 3.1 shows the registers in the S10 and their functions.
Each
channel has eight write registers and three read registers. Refer to 3.4
510 programming for details.
(1)
Communication data path
Fig. 3.2 shows the communica t ion path of the transmi t/receive da ta of
each channel.
1] Receiving
The receiver has 8-bit receive shift register and 3-stage 8-bit buffer
register in FIFO configuration.
Therefore, it is possible to get the
sufficient time at the high speed data block transfer. Moreover, the
receiver has the receive error FIFO for the purpose of holding the
parity error, the framing error and the other status information.
The receive data take the different paths according to the oepration
mode and the character length as shown in Fig. 3.2.
-233-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
Table 3.1
TMPZ84C40,41,42P/TMPZ84C40,41 ,42AP/AP-6
TMPZ84C43F/TMPZ84C43AF
/AF-6
,
(a) Write Register
1 Register
1
Function
1
1----------------1-------------------------------------------------1
1 Write register 1 CRC reset. This is used for the setting of the 1
1
O(WRO)
1 register-pointer and command.
1
1----------------1-------------------------------------------------1
1Write register 1 This is used for the setting of the interruptionl
1
1 (WRI )
1 mode.
1
1----------------1-------------------------------------------------1
1 Write register 1 Register for the setting of the vector which is 1
2(WR2)
1 sent out at interruption (Channel B only)
1
1
1----------------1--------------------------------------------------1
1
Write register
1
1
3(WR3)
1
Register having the parameter for the control
of receiver
1
1
1----------------1-------------------------------------------------1
1
Write register
1
Register having the parameter for the control
1
1
1
Write register
1
Register controlling the transmitter
1
S(WRS)
1
1
1
1
1
4(WR4)
1 of receiver and transmitter
1
1----------------1-------------------------------------------------1
1----------------1-------------------------------------------------1
Write register
Register for the setting of the synchronous
1 6(WR6)
1 character and the address field of SDLC
1
1----------------1-------------------------------------------------1
1
1
1
Write register
7(WR7)
1
1
Register for the setting of the synchronous
and the flag of SDLC
1
1
(a) Write Register
1
Register
Function
1
1
1----------------1-------------------------------------------------1
Write register
Indicates the state of transmit/receive and the
1 O(WRO)
1 state of terminals.
1
1----------------1-------------------------------------------------1
1
1
1
Write register
1
1
l(WRl)
1
1
Write register
2(WR2)
1
1
Indicates the error status and terminals number
code.
1
1
1----------------1-------------------------------------------------1
1
1
Indicates the content of the interruption
vector. (Channel B only)
-234-
1
1
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
Fig. 3.2
TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/AP-6
TMPZ84C43F/TMPZ84C43AF/AF-6
Transmit/Receive Data Path (Channel)
o
Aaynchronoua mode
In the asynchronous mode, when the character length ia 7 or 8 bit, the
receive data enter into 3-bit buffer and when it is 5 or 6 bit, data
enter into B-bit receive ahift r~gi.ter jumping 3-bit buffer.
o
Synchronous mode
In the synchronous mode I the data path changes according to the then
receive processing steps.
The receive operaiton begi'Cs at the hunt
phase.
In this mode, the receiver leeks the bit pattern which
coincides with the synchronous charcter which has been programmed
within the receive data.
When SIO is programmed in the mooosynchronous mode, the receiver leeks the bit pattern wh ich coine idea
with the synchronoua character which is set in WR 7. And when SIO is
programmed in the bi-synchronoua mode. the receiver seeks the bit
pattern which coincides with the two successive synchronous characters
which are .et in WR 6 and Wi7.
When the .ynChronization is once uttled. the lubsequent data do no:
pass the sY'Cchronous regilter and so enter into 3-bit buffer.
o
SDLC mode
In SDLC mode, the synchronoul reii.tar alway. monitors the receive data
and the zero. elimination il carried out if necel.ary.
When the synchronous regilter detect. the succellive five "1" within
the receive data and the next bit it "011, thb register eliminat .. the
"011.
Moreover, if the next bit it lilli, thit relister moniton the
.. cond next bit.
-235-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/AP.6
TMPZ84C43F/TMPZ84C43AF/AF-6
If this bit is "0", it must be recognized as the flag and if it is "1",
it must be recognized as the abort sequence (the successive seven "1").
The reformatting data enter into the receive shift register through
3-bit buffer. When the synchronization is once settled, the subsequent
data take the same path regardless of the character length.
2]
Transmitting
The transmi tter has 8-bit transmit data register and 20-bit transmit
shift register.
20-bit transmit shift register reads the data from WR
6, WR 7 and the transmit data register.
o
Asynchronous mode
In the asynchronous mode, the data in 20-bit transmit shift register
are sent to the transmit multiplexer with the start bit and the stop
bit.
o
Synchronous mode
In the synchronous mode, WR 6 and WR 7 hold the synchronous character.
Furthermore, these contents are sent into 20-bit transmit register as
the synchronous character at the time of the data block transmit.
If
the transmitter underrun state occurs during the trasnsmission of the
data block, the contents sent into 20-bit transmit register as the idle
synchronous character.
o
SDLC mode
In SDLC mode,
The flag (WR
beginning and
data, one "0"
(2)
WR 6 holds the station address and WR 7 holds the flag.
7) is sent into 20-bit transmit shift register at the
end of the frame.
With regard to all other field in the
is inserted after the successive five "1".
I/O function
When the transmit/receive of the informations are carried out with MPU,
one of the polling mode, interrupt mode or block transfer mode is chosen
as SIO mode.
o
Polling
In order to operate SIO in the form of polling mode, every interrupt
modes must be inhibited.
In this mode, MPU reads the status bit DO and
D2 within each channel RR 0 and so checks the possibility of transmit/
receive.
o
Interrupt
SIO interrupts are composed of the transmit
interrupt,
receive
interrupt and external/status interrupt.
Enabling and disabling the
interrupt are executed by using the program.
The receive interruption
is further divided into the following three modes.
o Interrupt in the first receive character
o Interrupt in the full receive character
o Interrupt in the special receive condition
The priority order of the interrupt of the channel A is higher than
that of the channel B.
The order in the same channel is the receive-,
transmit- and external/status interrupt.
-236-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84C40,41,42P/TMPZ84C40,41,42AP/AP-6
TMPZ84C43F/TMPZ84C43AF/AF-6
The 510 has as well as the other peripheral LSI the daisy-chain
sturcture interruption priority order control
function and
the
interrupton vector generation function. Furthermore, SIOs have "Status
affect vector" function.
This status affect vector is the function
whic\1 can output the four kinds of vectors according to the
interruption factors.
o
Block transfer
SIOs have the block trans fer mode and so can adapt the mode to MPU
block transfer and DMA controller.
W/RDY line is used for the block transfer.
This line is used as WAIT
I ine for MPU block trans fer and is used as READY 1 ine for DMA block
trans fer.
The ready output of SIOs can transmi t the data to DMA
controller. Further, the wait output of SIOs can not ready to transmit
the data and so request the delay of the output cycle.
3.2.2
Operation
Asynchronous mode
In asynchronous mode, in order to transmit/receive of data, it is
necessary to program the character length, clock rate, interruption mode,
etc. All these parameters are written into the write register, but only
WR 4 should be programmed prior to other registers.
In data transmit, it is not started until transmit enable bit has been
set, but when auto-enable bit is set, SIOs start to transmit immediately
after CTS terminal has become "0", so a programmer can transmit messages
to 510, needless to wait for CTS.
The data format of the asynchronous mode is shown in fig. 3.3.
(1)
MARKING
MARKING
\
START BIT
STOP BIT
PARITY BIT
..DIRECTION OF MESSAGE
Fig. 3.3 Data Format of Asynchronous Mode
11
Transmitting
Serial data are output from TxD terminal, whereby the transmitting
clock rate can be programmed at any of I, 1/16, 1/32 or 1/64 of the
clock rate furnished to transmit clock input (TxC). In addition, these
data are output at leading edge of TxC.
21
Receiving
Receiving operation of asynchronous mode
bit (DO of WR 3) is set. When receiving
for at least 1/2 bit time, 5105 take it a
input data at the middle of bit time.
carried out at the trailing edge of Rxc.
-237-
starts when receiving enable
data input RxD is set at "0"
start bit and sample out the
In addition, the sampling is
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/A,.6
TMPZ84C43F/TMPZ84C43AF/AF-6
TECHNICAL DATA
When a receiver receives the data of the other character length than 8
bit, it converts them into such data as composed with necessary bit,
parity bit, and by making free bit as "1".
(~xample) The case of 6-bit character 11 IpiDsID41D31D21DIIDOI
When external/status interruption is enabled, if it detects break state
during receiving data, it generates interrupt, and then break/abort
status bit (D7 of RR 0) is set, while SIOs wait the release of break
state, monitoring the transmit data. Further, when no-active state of
DCD terminal lasts longer than the time of a specified pulse width,
interrupt is generated and DCD status bit is set at "1".
In the polling mode, MPU must read out the data, detecting significant
bit (DO of RR 0) of receiving character.
This bit is automatically
reset, whenever it reads. out a receiving buffer. In this mode, caution
is requested to prevent double wrl.tlng, by checking the status of
transmit buffer prior to writing into a transmitter.
(2)
Synchronous mode
In the synchronous mode, though there are three kinds of character
synchronization which are monosynchronization, bisynchronization and
external synchronization, the clock of xl ,is used both for transmit/
receive. Receiving data is sampled at the trailing edge of receive clock
input (RxC) , while tranmsitting data varies at the leading edge of
transmit clock input.
The data format of synchronous mode is shown in Fig. 3.4
D_A_T~' :~-IE-L-D------~--C-R-C--1--~--C-R-C-2--~
L-__________L-_____
SYNCHRONOUS
CHARACTER
DATA FIELD
~J~;_IE_L_D
CRC 1
______
~
__C_R_C_l__
CRC 2
~
__C_R_C__2__
~
EXTERNAL SYNCHRONOUS MODE
E
Fig. 3.4
1]
DIRECTION OF MESSAGE
Data Format of Synchronous Mode
Monosynchronous
In this mode, when coincidence wi th synchronous charac ter (8 bit)
programmed in WR 7 is realized, synchronization is generated, thereby
the data transmit becomes possible.
-238-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84C40,41,42P/TMPZ84C40,41,42AP/AP.&
TMPZ84C43F/TMPZ84C43AF/AF-&
21
Bisynchronous
In this mode, when coincidence with two successive synchronous
char~cters programmed in WR 6 and WR 7 is attained, the synchronization
is -generated, thereby data transmit becomes possible.
Further, in
these mono- and bi-synchronous modes, SYNC becomes active during the
receive clock which detects the synchronous character.
31
External synchronous
In this mode, the synchronization is carried out externally. When the
synchronization is attained, it is informed by SYNC terminal.
In
addition, SYNC input should be kept at "0", until the character
synchronization is released. The character configuration begins at RxC
rising after SYNC falling.
After resetting, SID enter into the hunt phase, searching the
synchronous charac ter.
If the synchronizat ion becomes incomplete, it
is possible to enter again into the hunt phase by set the enter-hunt
phase bit (D4 of WR 3) at "1".
o
Transmitting
Data transfer using interruption
If transmit interrupt is enabled, interrupt is carried out when the
transmit buffer becomes empty.
As for the interruption procedure,
the other data are written in the transmitter.
In such case, the
transmit under run state occure if the data is not yet prepared by
some reason.
b. Bi-synchronous transmitting
In the bisynchronous mode, if data run out in a transmitter during
the transmitting, replacing character is to be sent in order to keep
the synchronization. There are two ways for that; one is to insert a
synchronous character, and another is to feed CRC characters wh ich
are till then generated, and then to feed the synchronous character.
The selection of the way is controlled by reset transmit underrun/EOM
command in WR o.
c. End of transmission
Break is carried out by setting D4 of WR 5. At this time, a in both
the transmit buffer and the shift register will go out.
When external/status interruption is enabled, SID generates interrupt
and transmit vector according to the state of the transmitter.
This mode can be used for the block transfer.
a.
o
Receiving
Interrupt on first received character
This mode is usually used for the block transfer.
In addition, in
this mode, SID generates interrupt only for the first character, but
thereafter do not generate interrupt except under the special receive
conditions.
For the purpose of the initialization, it is required to set command
4 of WR 0 (enable at next receive interrupt).
b. Interrupt on all received character
In this mode, interrupt is generated for all characters entering into
receive buffer. When status affect vector is set, special vector is
generated by special receive condition.
a.
-239-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41 ,42pnMPZ84C40,41 ,42AP/AP'6
TMPZ84C43FnMPZ84C43AF/ AF-6
TECHNICAL DATA
c.
(3)
Special recelvlng conditional interrupt
This interrupt can be generated regardless of the selection of the
ab()ve two ways of interrupt.
Although as for the special receive
conditions, there are pari ty error, receive overrun error, framing
error, and end of frame (SDLC), the reset is necessary after read
out, since these error status bits are latched.
These error status bits can be reset by the command 6 of the WRO.
SDLC mode
Though SIO can use both protocols of SDLC and HDLC, since both are very
much similar, here explanation is made only for SDLC mode.
Fig. 3.5 shows the data format of SDLC mode.
In SDLC mode, one data block is called "frame", and these messages are
held between two flags, called open flag and close flag.
Address field
includes the address of secondary station, and 510 receive or disregard
this frame according to the address.
FRAME
DATA FIELD
L-______
~L-
______
~
________
~
Fig. 3.5
o
~§~
________
CRC 1
~
CRC 2 ICLOSE FLAG
______L __ _ _ _ _ _ _ _ _ _ _
~
I
~_
DIRECTION OF MESSAGE
Data Format of SDLC Mode
Transmitting
Data transfer using interrupt
If transmit interrupt is set, whenever transmit buffer becomes empty,
interrupt is generated.
In SDLC mode, data are transferred to SIOs,
by the use of this interrupt.
b. Data transfer using wait/ready
In wait/ready function, WAIT is for lengthening the output cycle of
MPU when SIO transfer buffer is not empty, while READY notifies DMA
that 510 transfer buffer is empty and so ready for receiving data.
If data is written in transfer shift register prior to the
transmitting, SIO enter into the underrun state.
Using this function, it is possible to transmit data to SIOs.
c. Transmitting underrun/EOM
SIO, when there is no data to be transmitted in transfer data buffer,
automatically terminate SDLC frame.
In order to carry out this,
after data run out, SIO at first transmit CRC of 2-byte and then
transmit one or more flags.
After reset t ing, status bi ts of transmi t underrun/EOM are Be t and
prevent CRC character from inserting when transfer data run out.
Using this operation, the frame transmission is started.
At this
time, transmit underrun/ EOM reset command must be set between the
time of transmit of the first data and the end of data.
By doing this, reset state is generated at the end of message, so CRC
characters are automatically transmitted.
a.
-240-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/AP-6
TMPZ84C43F/TMPZ84C43AF/AF-6
TECHNICAL DATA
d.
CRC generation
When CRC calculation is carried out
CRC generator must have been
reset (D6 and D7 of WR 0) piror to the start of tr ansmi t.
Calculation of CRC is started at the time (WR 6) when address field
is written into SIOs.
Further, transmit CRC enable bit (DO of WR 5) must be set prior to
address field writing.
End of transmit
While transmitting, if the transmitter is made to be disabled, though
the data under transmitting at that time are transmitted without· any
change, the transmitter enters into the marking state thereafter.
Even if a transmitter is disabled, characters in the buffer remain,
but when abort command is written in command register, abort sequence
becomes significant and then all data go away.
J
e.
Receiving
In receiving mode, the initial setting of several parameters 15
necessary. Address field is written in WR 6, and flag character in WR
o
7.
When a receiver receives open flag, it compares the content of address
field following the flag with the address set in WR6 and global address
("1111 1111). If address field in frame coincides with either one of
the above two, SlOs start receive.
a.
b.
c.
d.
Interrupt on first received character
This mode is used for the block transfer, which usually uses WAIT/
READY function. In this mode, SIOs generate interruption only to the
first character.
Further, since status flag of this interruption is latched, it 1S
necessary to set command 4 (enable at next receiving character) of WR
o beforehand, in order to initialize again.
When external/status interruption is set, interruption is generated
at every change of DCD. In addition, interruption is generated under
special receive conditions.
Interrupt on all received character
In this mode, 510 generate interrupt to all characters received. In
additioon, when status affect vector has been set, special vector 1S
generated to interruption under special receive conditions.
Special receive condition interrupt
When special receive conditions are used, it is necessary to select
beforehand either of interrupt by first received character or
interrupt by all received characters. Among interrupt under special
receive conditions, status of receive overrun is latched.
Reset of
status bit is carried out by error reset command (command of WR 0).
CRC check
The CRC checker is reset when it receives the leading open flag of
frame, and carries out CRC calculation of the following characters,
continuing to close flag.
In SDLC mode, as transmitting CRC is inverted, special check sequence
is used. Check must be ended with "0001 1101 0000 1111".
Since 510 processes CRC characters as data, MPU must discard them
after reading.
-241-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
e.
TMPZ84C40,41 ,42PflMPZ84C40,41 ,42AP/AP.&
TMPZ84C43FflMPZ84C43AF/AF-6
End of receive
When SIO receives close flag, end of frame bit is set and
this fact indicates that the close flag has been received.
FurLher,
if the status affect vector is set at this time,
interrupt under special receiving conditions is generated and
the vector is transmitted.
At any frame, abort can be
carried out by abort transmit.
Further,
if external/status
interrupt has been set at this time,
interrupt is generated
and break/abort bit in RRO is set.
-242-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/AP-6
TMPZ84C43F/TMPZ84C43AF/AF-6
TECHNICAL DATA
3.3
3.3.1
Status flowchart and basic timing
Status flowchart
C/0-1
(;E. 1Oil1i - 0
Rii-
0
C/!Y- 0
CE.lOR(t-O
RD-1
COMMAND WRITE
(WRO T WR7)
BETT
D 1
D N
PARITY BIT
~nOI'BIT
'1'
NO
NO
Fig. 3.6 (a)
Status Flowchart
-243-
Fig. 3.6 (b)
Status Flowchart
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/AP-6
TMPZ84C43F/TMPZ84C43AFI AF-6
TECHNICAL DATA
TxV
'!'XC
TERMINAl,
OPEN FLAG
CHARACTER (7EH)
INPUT
C/D~l
CE, IORC<
~
0
RD~O
BUFFER EMPTY>----------
?
YES
1 ADDRESS WRITE
2 TRANSMIT DATA
WRITE
TRANSMIT
~ INTERRUPTION
r----------------,
ADDRESS(DO-D7)
TRANSMIT DATA
(DO-D7)
NO
NO
----~
CRC(DO-DlS)
L--------r------~
NO
CLOSE FLAG TRANSFER
( 7 E H )
Fig. 3.6 (c)
Status Change Flowchart
-244-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41,42P/TMPZ84C40,41,42AP/AP-6
TMPZ84C43F/TMPZ84C43AF/AF-6
TECHNICAL DATA
TxD TERMINAL
-----
'!'XC
INPUT
C/D-l
lllf,'!1iilQ;-o
Rl5- 0
SYNCH l(DO-D7)
SYNCH 2(DO - D7)
STATUS
READOUT RHO
c/Ii- a
CE,IORQ,-O
iW-l
---1
CRC(DO-DU,)
SYNCH l(DO - D7)
SYNCH 2(DO-D7)
Fig. 3.6 (d)
Status Change Flowchart
-245-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41,42P/TMPZ84C40,41,42AP/AP-6
TMPZ84C43F/TMPZ84C43AF/AF-6
TECHNICAL DATA
BYNCHRONOU S J-:'S"D"LC-o---.J
Fig. 3.6 (e)
Status Flowchart
-246-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
3.3.2
TMPZ84C40,41,42P/TMPZ84C40,41 ,42AP/AP-6
TMPZ84C43F/TMPZ84C43AF/AF-6
Basic timing
Fig. 3.7 is the timing diagram when data or command are written into SIO
from MPU.
Fig . . 3'.8 is the tlmlng diagram when MPU reads data from SIO.
Fig. ~.9 shows that when MPU accepts an interrupt request of SIO, as the
acknowiedge signal, IORQ terminal is made "0" within a couple of clocks
after M1 terminal is made "0".
In order to hold the state under interruption service at daisy-chain, the
state of interruption request cannot be changed as long as M1 remains
active.
Figure 3.10 is the timing diagram of returning from interruption.
Figure 3.11 shows the state of daisy-chain.
At first, the period during interruption service of 510 is considered.
After Ml becomes active, by interruption request of PIO immediately
before the deconding of "EDH" in the first byte of RETI instruction,
"lEO" of PIO becomes "0".
However, interruption request of PIO is not
acknowledged, because "EDH" is decoded.
There fore, "lEO" of PIO returns
to "l".
By decoding "4DH" at the 2nd byte, "lEO" of 510 returns to "1".
Therefore, "lEI" and "lEO" of peripheral LSI at this time become "1", and
so they enter into the state under no interruption service.
PIO keeps
INT terminal at "0" until this state is realized.
Under this state,
interruption starts from the peripheral LSI of higher interruption
priority order.
Tl
T2
Tl
T3
f\L
CLR
B/A.C/D.CE
DATA
Fig. 3.7
XWRITE DATAX==
Data Write Cycle from MPU to 510
-247-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/AP-6
TMPZ84C43F/TMPZ84C43AF/AF-6
TECHNICAL DATA
T2
Tl
T3
TW
T1
CLR
B/A. C/D.CE
- - - - - - - - - - - : : : : ( READ DATA ) - - - -
DATA
Fig. 3.8
Data Readout Cycle from MPU to SID
CLR
Ml
~~_ _ _ _ _ _ _ _ _ _ _ _ _ _~;--
\,-------;......../
Fig. 3.9
Tl
Interrupt Acknowledge Cycle
T2
T3
T4
Tl
12
T3
T4
Tl
JL
CLK
m:
~
\
RD
DATA
lEI
lEO
4 D
-- - - - - - -- -;r,-------+------_______
__ J
I
______________________- L__
Fig. 3.10
Return Cycle from Interruption
-248-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/AP-6
TMPZ84C43F/TMPZ84C43AF/AF-6
TECHNICAL DATA
[ 1)
Status where SIOs request interruption
lEO
til"
"Ill
"I"
"I"
lEI
1
lEO
lEI
lEO
"1"
"10
INT
"I"
As "EDH" has
acknowledged.
fl111
-1-
"0"
"a"
"0
1
1
SlO
been decoded, the interruption reques t
Therefore, lEO of PIO returns to "l".
111"
INT
--'---I
PlO I
___
Ill"
"I"
of
PIO
is
not
"0"
SIO
As "4DH" has been decoded, lEO of SIOs becomes "1".
"111
1_
[6)
lEO
PlO
PlO
[5)
lEI
Status where PlO has requested interruption immediately before SIOs
decode "ED".
By the request of PlO for interruption lEO of PIO becomes "0".
-1-
[4)
510
lEO
liD"
1
SlOs are under interruption serVlce
1_-[3]
lEI
INT
"I"
PlO
lEI
[ 2)
"III
Ill"
"I"
1_
"1"
INT
~-'--~I
Ul l1
PIO I
___
ifI"
"111
510
Interruption request by PIO is acknowledged, and the lEO of PIO becomes
"0".
"I"
Ill"
1_
PlO
Fig. 3.11
"0"
"0"
SlO
Daisy-chain at RETI nstruction
-249-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40.41.42pnMPZ84C40.41.42AP/AP-&
TMPZ84C43FnMPZ84C43AF/AF·6
.
TECHNICAL DATA
3.4
SIO programming
Here, the meanings of each write register and read register are
specifically explained with regard to each bit. It should be noted that
parameter of write register (WR 4) must have been set prior to other
parameters.
In addition, there are such registers that are used for only single
channel.
WR 0:
Write register 0
Table 3.2
Composition of Write Register 0
I
I
I
I
D3 I D2
D4
D1
DO I
____+-__-r__~----+---~Ir_--+----+----I
D7
D6
CRC
Reset code
DS
Basic command bit
I
I
IRegister pointer bitl
----~I--~----~I--~I----~I--~I----~I----I
DO - D2: Register pointer bit
These bits specify the registers to be written in or read out at the
next byte.
When write or read have ended, the register pointer
specifies WR O.
D3 - DS: Basic command bit
Command 0 (=000): No operation
This command is for setting register pointer without operating SIO.
This is used for reserving the space, in case there is any
possibi1 ity of inva1 idat ing some command among the command chain to
SIO or inserting command at some part of the command chain.
Command 1 (=001): Abort generation
This command is used in order to generate abort sequence (sequence of
successive "1" of more than 7).
This command is used for SDLC only.
Command 2 (=010): External/status interruption reset
Once external interrupt or status interrupt occurs, status bits of
RRO are latched.
This command enables status bits of RRO for
permitting the interrupt again.
Command 3 (=011): Channel reset
This command operates same as reset signal is given at "RESET"
terminal.
The difference between them is that this command resets
single channel only.
Further, command to channel A also reset
interruption priority circuit.
Command 4 (=100): Enabling the interruption at the time of next
character receive
This command is used, when the end of block in data block is detected
and next data block is received and interruption generation is
des ired.
Command 5 (=101): Transmitter interruption hold reset
In transmitter interruption enable mode, when transmit buffer becomes
empty. interruption is generated.
But, if there is no data to be
sent, this command is used in order to suppress the transmitter
interruption generation.
-250-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84C40,41,42P/TMPZ84C40,41,42API AP-6
TMPZ84C43F/TMPZ84C43AFI AF-6
Command 6 (=110): Error reset
Errors committed during block transmit (parity error and overrun
error) are latched at D4 and D5 of RR 1.
This command is used to
clear them.
Command 7 (=111): Return from interruption
This command operates same as it executes RETI instruction on SID
data bus.
There fore, even in MPU other than Z80 MPU (sys terns not
using RETI interruption), daisy-chain in SID can be used.
This
command is for channel A only.
D6 - D7: CRC reset code
These two bits are able to select one of receive CRC checker reset,
tranbsmitter CRC generator reset and transmitter underrun/EOM reset.
Table 3.3
Reset Command Code
Reset command
No operation
Reset the receiving
Reset the transmitter
Reset the transmitter
WR1:
D7
0
0
1
1
D6
0
1
0
1
Write register
Table 3.4
Composition of Write Register
I
I
I
D6
D5 I D4
D3
D2
D1 I DO
I D7
I
I
I
I
I
I
Wait/ready
IStatusITrans-IExter-1
I
I
IRelaffectlmitterlnal
I
I
I Receiving
I
Iceiv- I interruptionlvectorlinter-Istatusl
I
I
IEnablelFunc- ling
I rup- I inter-I
I
I mode
Ition Itrans-I
Ition I rup- I
I
I
Iselec-Imit- I
lenableltion I
I
I
Ition I ting I
lenablel
I
I
I
Iselec-I
I
I
I
I
i
I
Ition I
I
I
I
I
I
I
DO:
External/status interrupt enable
When this bit is set, interrupt can be generated at the time of
synchronous character transmitter start even
in such case as
break/abort has been detected and finished, DCD, CTS or SYNC signals
have changed, or transmitter underrun/EOM latch has been set.
01: Transmit interrupt enable
If this bit is set, transmit interrupt is generaetd wben transmit
buffer becomes empty.
D2: Status affect vector
When this bit is set, D1 - 03 (V!-V3) of WR 2 varies according to
interrupt conditions.
When this bit is not set, interrupt vector is sent with the same
content as in WR 2. This bit can be used for channel B only.
03-04: Receive interrupt mode
This bit can select receivin~ interrupt mode.
-251-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/AP-6
TMPZ84C43F/TMPZ84C43AF/AF·&
D5-D7: Wait/ready function selection (D5-D7)
By these three bits, the selection of function of W/RDY terminal at SIO
is carried out.
Wait/ready function is not used at the same time, since it is selected
according to the program.
The semantics of each of these three bits are:
o When"D5 is set, they mean receive, whereas reset means tranmmit.
o When D6 is set, this means REAOY terminals, and while reset, this means
WAIT terminal.
o When 07 is set, Wait/ready function becomes enable, while reset,
becomes disable.
This means, for example, when 07, 06 and 05 are 110 and transmitter
buffer is full, READY output becomes "1", and when tramsmitter buffer
is empty, REAOY terminal becomes "0".
The above (03-04 and 05-07) is summarized in the table below.
Table 3.5
Receiving
Receivin
Interrupt
receivin
Interrupt
receiving
Interrupt
receiving
(However,
*
Receiving Interruption Mode Codes
03
o
in first character receiving or *special
condition
in character receiving or special
condition
in character receiving or special
condition
except parity error)
1
o
1
1
The special receiving conditions are as follows:
o End of frame (SOLC mode only)
o Receiving overrun error
o Parity error
o Framing error
Table 3.6
Function
Selection of Wait Ready Functions (05 - 07)
H/L Level
At floating
active
Low
High
Low
WAIT
READY
WAIT
I Floating
READY
WAlT
READY
:
:
High
Low
Floating
Low
Low
High
WAIT/REA'
l'erminal
I
I
Condition
I
I
I
I
I
Transmitter buffer is full and
I SIO data port have been
I selected
I
Tranmsitter buffer is empty.
Transmitter buffer is full.
Transmitter buffer is elllI>9T.
Receiving buffer is full.
Receiving buffer is empty and
SIO data port have been
selected.
Receiving buffer is full.
Receiving bugger is empty.
-252-
D7 I 06
05
I
I 0
0 I
I- I -
I
I
I
I
I
I
I
I
I
I
0
0
0
0
1-11
I
I
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41,42P/TMPZ84C40,41,42AP/AP-6
TMPZ84C43F/TMPZB4C43AF/AF·6
TECHNICAL DATA
WR2:
Write register 2
Table 3.7
07
06
Composition of Write Register 2
05
04
03
02
01
00
Vl
VO
Interruption Vector
V7
V6
V5
V4
V3
V2
When the status affect vector bit is set, V3 to Vl
change according to the interruption condition.
This write register is an interruption vector register. When 02 of WR
1 is not set, interruption vector is sent.
When 02 of WR 1 is set,
01-03 (VI-V3) varies according to interruption generate conditions. In
this case, the content of WR 2 remains unchanged.
Further, since WR 2 exists in channel B only, programming of WR 2 of
channel B is necessary even if only channel A of SIO is used.
The following Table (3.8) shows the V3 to Vl of an interrupt vector
when the status affect vector bit is set.
Table 3.8
Channel
B
A
*
Codes according to interruption generate conditions
of each channel
Interruption generate condition
V3
In case transmitter buffer is empty.
0
In case external/status change
0
In case of receiving character is effective. I 0
* In case of s ecial receivin condition
I 0
In case transmitter buffer is empty.
In case external/status chan e
In case of receiving character is effective.
* In case of special receiving condition
I
The special receiving conditions are as follows:
o End of frame (SOLC mode only)
o Receiving overrun error
o Parity error
o Framing error
-253-
V2
0
0
VI
0
I
0
1
0
1
0
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/AP-6
TMPZ84C43F/TMPZ84C43AF/AF-6
TECHNICAL DATA
W3:
Write register 3
Table 3.9
Composition of Write Register 3
I
I
I
I
I
D3 I D2 I Dl I DO I
D4
I DS
I
I
I
I
I
~/
I Syn- I
I
I
I
Receiving IAuto I Efuer t ReIAdIchro- IReI
bit/cha- I enabler hunt Iceiv- Idress Inous Iceiv- I
racter
Isearchlchar- ling
I
I phase ling
I
Imode lacter lenablel
ICRC
I
I
I
I load I
lenablel
I
I
I
I
linhibil
I
I
I
I
I
I
Ition I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
D7
D6
~~
DO:
Receiving enable
When this bit is set, receiving operation starts.
This bit is used for starting receiving operaiton, so it must be set
after all receiving program are complete.
Dl: Synchronous character load inhibition
In synchronous mode, if this bit has been set, synchronous character is
not loaded on transmitter buffer.
D2: Address search mode
When SDLC mode is selected and this bit is set, any message having
programmed address in WR 6 or other address than global address (FFH)
is not received. Therefore, receive interruption does not occur until
the addresses coincide.
D3: Receiving CRC enable
When this bit is set, CRC calculation starts at the time of the start
of transmitter of the last data to the receiving buffer from the
receiving shift register.
D4: Enter hunt phase
When synchronization settling is needed, 510 enter into hunt phase by
setting this bit.
In addition, once synchronization is settled, the
hunt phase is released automatically.
DS: Auto enable
If this bit is set, transmitter is enabled when CTS terminal is "0".
Further, when DCD terminal is "0", receiver is enabled.
D6-D7: Receiving character length
These bits specify the rece1v1ng bit number which composes one
character. The table below shows the bit numbers per one character.
Table 3.10
Codes according to receiving character length
Bit number/Character
5
6
7
D7
0
0
1
D6
0
1
0
1
8
-254-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41,42P/TMPZ84C40,41,42AP/AP-&
TMPZ84C43F/TMPZ84C43AFI AF·&
TECHNICAL DATA
WR 4:
Write register 4
Table 3.11
D7
Composition of Write Register 4
DS
D6
Clock mode
D4
Synchronous
mode
D3
D2
Stop bit
I
I
I
Parity
I
Even/
I
odd IEnablel
I
I
Dl
DO
DO:
Parity selection
When this bit is set, 1 bit transmitter data is added to the bit
numbers wh ich are spec i fied in D6-D7 of WR 3 and then th is added bit
number is received.
Further, if the selected character length is other than 8 bits, the
added parity bit is set at MSB side of data bit and then will be
transferred to receiving data FIFO.
When 8 bits of character length is selected, the parity bit will not be
transferred to receiving data FIFO.
Dl: Parity polarity
When parity is selected by this bit, it must be determined whether
transmittance and check are carried out at even number or odd number.
(even number = 1, odd number = 0)
D2-D3: Stop bit length
Stop bit length at asynchronous mode is selected by these bits.
Both
of D2 and D3 are set at "0" in synchronous mode.
Table 3.12
Codes according to Stop Bit Length
Stop bit
Synchronous mode
1 stop bit/character
1.5 stop bit/character
2 stop bit/character
D3
o
o
D2
o
o
D4-DS: Synchronous mode
Synchronous mode is selected by these bits.
Table 3.12
Codes according to Synchronous Mode
Synchronous mode
8 bits synchronous model
16 bits synchronous
I
I
mode (bisynch mode)
SDLC mode (Flag char- I
acter:7FH)
I
External synchronous
I
mode
I
-255-
D3
0
0
D2
0
1
0
1
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/ AP-6
TMPZ84C43F/TMPZ84C43AF/ AF-6
TECHNICAL DATA
D6-D7: Clock mode
Scale factor between transmitter/receiving clock and data transfer rate
is se lec ted by these bi ts.
Bes ides, xl clock mode must be used in
shyn~ronous mode.
But, in asynchronous mode, the same scale factor is
used at transmitter and receiving area.
Table 3.14
x
x
x
x
WR 5:
Codes according to Clock Mode
Clock Mode
(Data Transfer Rate)
1 data transfer rate
16 data transfer rate
32 data transfer rate
64 data transfer rate
D7
D6
0
0
1
0
1
0
Write register 5
Table 3.15
D7
DTR
Composition of Write Register 5
I
Dl
I D2
I
I
I
I
I
Transmitter ITrans-ITrans-ICRC-161 RTS
/character Imitterlmitterl/SDLC I
Ibreak lenablel
I
I
I
I
I
I
I
D6
D5
D4
DO:
D3
I
I
I
I
I
I Trans-I
Imitterl
I CRC
I
lenablel
DO
Transmitter CRC enable
When transmitter data are loaded from transmitter data buffer into
transmitter shit register, if this bit is set, CRC calculation for
these data is carried out.
In synchronous mode or SDLC mode, if this
bit is not set, CRC calculation and transmission of the transmitter
underrun state are not carried out.
Dl: Transmitter request
When this bit is set, RTS terminal becomes "a".
If not, RTS terminal
becomes "I".
In asynchronous mode, when tranmsitter buffer becomes empty, RTS
terminal becomes "I". In synchronous mode and SDLC mode, RTS terminal
state follows this bit state.
D2: CRC-16/SDLC
When this bit is set, CRC-16 multiple term expression (X**16+X**15+X**
2+1) is selected.
When this bit is reset, CRC-CCITT multiple term
expression (X**16+X**12+X**5+1) is selected.
D3: Transmitter enable
If this bit is set, the transmitter is enabled.
Moreover, even if this bit is reset after data transmitter start, all
of synchronous character and data in progreses of transmit.
D4: Transmitter break
If this bit is set, whatever data are transmitted, transmitter data
line (TxD terminal) is forced to become the space state.
If this bit is reset, TxD becomes the marking state.
D5-D6: Transmitter character length
These bits indicate the transmitter data character length.
-256-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/AP-6
TMPZ84C43F/TMPZ84C43AF/AF·6
TECHNICAL DATA
Table 3.10
Codes according to Transmitter Character Length
Bit number/Character
Max. 5
7 bits
6 bits
8 bits
D6
0
0
1
1
DS
0
1
0
1
As shown in Table 3.16, when bits below than 5 (4 bits, 3 bits etc.)
per 1 character are transmitted, DS and D6 are expressed as "0", but it
is impossible to understand how many bits do data have.
Therefore,
data character should be treated according to the aftermentioned
format. Now, D means the data.
Table 3.17
Trans fer Format in case of max. 5 bits transmitter data
D7
1
1
1
1
0
Transmitter bits/Character
1
2
3
4
5
D6
1
1
1
0
0
DS
1
1
0
0
0
D4
1
0
0
0
0
D3
0
0
0
D
D
Data terminal ready
This bit indicates the state of DTR terminal.
When this bit is set, the state of DTR terminal
reset, it becomes "1".
D7:
WR 6:
D1
0
D
D
D
D
becomes
D
DO
D
D
D
D
D
"0", when
Write register 6
Table 3.18
D7
D6
Composition of Write Register 6
DS
D4
S
7
This
o
o
o
o
D2
0
0
D
D
6
5
y
D2
D3
DO
C
N
4
D1
3
2
o
register is programmed in accordance with the following state:
External syncrhronous mode •..•• Transmitter synchronous character
Mono-syncrhronous mode .•.•.•... Transmitter synchronous character
Bi-syncrhronous mode •.•..••..•. First synchronous character
SDLC mode
.•.•••••••••••••.•... Slave station address
-257-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41,42P/TMPZ84C40,41 ,42APIAP-6
TMPZ84C43F/TMPZ84C43AFI AF-6
TECHNICAL DATA
WR 7:
Write regis ter 7
Table 3.19
D7
D6
Composition of Wri te Register 7
D5
D4
D3
I
I
I
D2
D1
10
(2)
(1)
DO
I,
15
14
(6)
(7)
This
o
o
o
S
Y
13
(5)
12
11
(4)
(3)
C
N
8
(0)
9
register is programmed in accordance with the following state:
Mono-syncrhronous mode •••.•.•.• Receiving synchronous character
Bi-syncrhronous mode ••••.••.•.. Second synchronous character
SDLC mode ••..••••..•••.•••.... Flag character (7EH)
This register is not used in the external synchronous mode.
WR 0:
Readout register 0
Table 3.15
Composition of Readout Register 0
I
D7
D6
\
I
D5
\
\
\
\ Break\Trans-\ CTS
\/abort\mitter\
\
\under \
\
I run/ \
\
\
\ EOM
\
I
D4
D3
D2
\
Dl
\
DO
\
\
I
\ SYNC
\/Hunt
DCD
I
\
\
I
\Re\Trans-\Inter-\ceiv\mitter\rup- ling
\buffer\tion \char\ empty \ pend- I acter \
\
\ ing
\ effec-\
\
\
\ t ive \
\
I
I
I
\-----------,------------\
These registers are used for the external/status interruption mode.
DO:
Dl:
D2:
Receiving character effective
When there is any character of more than 1 byte in the receiving
burrer, this bit is set. When the receiving buffer has become empty,
this bit is reset.
Interruption pending
When the interruption has occurred within SIO regardless of the kinds
of the interruption conditions, this bit is reset. Moreover, this bit
is effective for the channel A only.
Transmitter buffer empty
When the tramsmitter data buffer is empty or SIO is reset, this bit is
set. However, only when CRC character is sent in the synchronous mode
and in SDLC mode, this bit is reset.
-258-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
D3:
D4:
i)
ii)
iii)
iv)
D5:
D6:
D7:
TMPZ84C40,41,42P/TMPZ84C40,41,42AP/AP.&
TMPZ84C43F/TMPZ84C43AF/AF-6
Data carrier detect
This bit indicates the DCD terminal input status. if the external/
status, interruption is generated, the value of this bit is latched.
Sync/hunt
The meaning of this bit differs according to the operation mode.
Asynchronous mode
In this mode, the SYNC terminal status of the SIO is shown. The
external/status interruption is generated by the SYNC terminal status
change.
External synchronous mode
If synchronized through the detection of external synchronization, the
bit must be changed to "0" at the trailing edge of the second RxC from
the trailing edge of RxC which recevied the last bit of that
synchronous character.
That is, to make "SYNC" input to "0" in the
external circuit after detection of the synchronization,
it
is
necessary to wait completely 2 receiving clock cycles.
When "SYNC"
input becomes "0", the sync/hunt bit is set. If the synchronization is
lost or end of message is detected, the enter hunt phase bit is set.
Internal synchronous mode
In Monosynchronous and Bisynchronous modes, this bit is first set at
"1" by the enter hunt phase command (D4 of WR3).
After the SIO
detected the synchronous character, this bit is reset.
SDLC mode
This bit is set when the receiver is disabled or by the enter hunt
phase command.
Thereafter, when the open flag of the frame is
detected, this bit is reset.
CTS (clear to send)
This bit indicates the status opposite to the CTC terminal input
status.
Transmitter under Run/EOM
When SIO is reset (including channel reset), this bit is set. This bit
can be reset only by the reset transmitter under run/EOM latch command
(D7, D6 of WR 0=11).
When the transmitter under run status is caused, the external/status
interruption is also generated.
This bit is also used for controlling transmission in the synchronous
and SDLC modes.
Break abort
In the receiving in asynchronous mode, tihs bit has a meaning of the
break status detection.
Detection of the break status sets this bit,
generating the external/status interruption, while the external/status
interruption reset command resets this bit.
After the break ended, the external/status interruption is again
generated.
In case of the SDLC mode, detection of the abort sequence sets this
bit, generating the external/status interruption.
-259-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/AP-6
TMPZ84C43F/TMPZ84C43AF/ AF·6
TECHNICAL DATA
RR 1:
Read register
Table 3.21
I
I
I
I
End I
of
I
frame I
I
I
I
D7
I
I
I
I
CRC/ I
fram-I
ing I
errorl
I
I
D6
Composition of Readout Register
D5
D4
I
I
I
Re- I
I
ceiv-IParityj
ing I errorl
over-I
I
run I
I
errorl
I
I
I
D3
I
I
I
D2
D1
I·
Fract ion
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I All I
I char-I
I acterl
Itrans-I
Imis- I
I sion I
I
I
DO
DO:
All character transmission
In the asynchronous mode, when all characters are sent out of the
tramsmitter or when there is no transmitted data in the SIO, this bit
is set. Furhter, in the synchronouss mode this bit is always kept set.
Dl - D3: Fraction codes
Since I Field is normally integer times of character length, if not
integer times, these codes show last fragmentary bits. These codes are
significant only for transfer in which end-of-frame bit is set in the
SDLC mode.
Example)
Two cases that [1] number of bits of one character at the end of
I Field is 8 (0) bits and [2] 4 bits are shown in Fig. 3.12.
I
I
I
I
I
[lJ
I fie Id
CRC l
>1
I
[ 2]
CRC l
CR 2
)
I field
I
Fig. 3.12
I Field Fractions
Further, the fragmentary codes for receiving characters in length of 8
bits/character are as follows:
-260-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/AP-6
TMPZ84C43F/TMPZ84C43AF1AF-6
TECHNICAL DATA
Table 3.22 (a)
Bit pattern according to last fragmentary bits in I field
Last fraction bits in I fiedd
1 bl:te before
2 bl:te before
0
3
0
4
0
5
0
6
0
7
0
8
8
8
2
D3
D2
Dl
1
0
0
1
0
1
1
0
0
1
1
0
0
0
0
1
1
0
1
0
1
0
Even when length of I field receiving characters is other than 8 bits,
a similar table can be composed for each character length.
Table 3.22 (b) Bit pattern according to data bits per I character
(In case of no fraction)
bit/character
5-bit/character
6-bit/character
7-bit/character
8-bit/character
D4:
DS:
D6:
D7:
RR
D3
0
0
0
0
D2
0
1
0
DO
1
0
0
Parity error
When the parity selecting bit (Do of WR4) is set, if parity error is
detected in receiving data, this bit is latched.
The latch can be
released by the error reset command (DS, D4, D3 of WR 0=110).
Receive overrun error
Receiving data FIFO is set up to 3 characters. If there is no read by
MPU and more characters are received, these characters are set as the
receiving FIFO.
When these characters are read out by MPU, this receive overrun error
is set. Once set, this bit latches its status. This bit is also reset
if the error reset command (WRO D3 - D5 commands) is written.
CRC/framing error
In the asynchronous mode, if a framing error is detected in received
characters, this bit is set.
Since not latched, this bit is always
updated.
In the synchronous mode and the SDLC mode, this bit shows the sent CRC
check result. This bit is reset when the error reset command (command
6 of WRO D3 - D5) is written.
End of frame
When the end of flag is detected during receiving data and no CRC error
and fragmentary code is normal, this bit is set.
bit is reset by the
error reset command (command 6 of WRO D3 - D5).
Further, this bit is used only in the SDLC mode and is updated when the
first character of next frame is received.
2: Readout register 2
-261-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/AP-6
TMPZ84C43F/TMPZ84C43AF/ AF-6
TECHNICAL DATA
Table 2.23
D7
D6
Composition of Readout Register 2
D5
D4
D3
D2
Dl
DO
Vl
VO
Interruption Vector
V7
V6
V5
V4
V3
V2
When the status affect vector bit is set, V3 to VI
change according to the interruption condition.
When the status affect vector bit (D2 of WRI), is set, V3 to VI change
according to the interruption condition at the time.
Vector that is
read out is decided by the interrupt condition with the highest
priority at the time of readout.
Further, when the status affect vector bit is reset, the content
becomes equal to that of WR2.
3.5
How to use 510
Two examples of systems using the 510 are introduced here.
Shown in Fig. 3.13 is an inter-processor communication system.
In this example, MPU at the left side transmits/receives data to/from
other modules at the right side.
Shown in Fig. 3.13 (a) is also a
communication system as in Fig. 3.13 (b).
As shown in these examples, the 510 is used for data communication with
external devices.
In addition, the most great advantage of the SID is
that it requires less data lines than parallel communication as shown in
this figure.
-262--
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41,42P/TMPZ84C40,41,42AP/AP-6
TMPZ84C43F/TMPZ84C43AF/AF-6
TECHNICAL DATA
Z80
Z80
IIPU
SIO
Fig. 3.13 (a)
Z80
Z80
REXlEIVER
SIO
IIPU
RSXYZ
DRIV
REXlEIVER
Z80
Z80
SIO
IIPU
Inter-processor Communication System
1ST CHANNEL
CH.A lI'::==~
Z80
Z80
UPU
S IO
II'::==~
CH.B (\r
'"
MODEM
(SYNCIIRONOUS/
ASYNCHRONOUS
DATA LINK TO
REMOTE PROCESSOR
2ND CHANNEL
Fig. 3.13 (b)
Inter-processor Communication System
-263-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
4.
ELECTRICAL CHARACTERISTICS
4.1
ABSOLUTE MAXIMUM RATINGS
TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/AP-6
TMPZ84C43 F/TM PZ84C43AFI AF·6
Symbol
Item
Rating
I Unit I
vcc
I Supply Voltage
I
-0.5 to +7.0 I
V I
I
1----------1-----------------------------------1--------------------1------1
I
VIN
I Input Voltage
I -0.5 to Vee + 0.5 I
V I
1----------1-----------------------------------1--------------------1-----I
PD
I Power Dissipation
(TA = 85°C) I
250
I mW
1----------1-----------------------------------1--------------------1-----I TSOLDER I Soldering Temperature (10 sec)
I
260
I °c
1----------1-----------------------------------1--------------------1-----I
TSTG
I Storage Temperature
I
-65 to 150
I °c I
1----------1-----------------------------------1--------------------1------1
I
TOPR
I Operating Temperature
I
-40 to 85
I °c I
4.2
DC ELECTRICAL CHARACTERISTICS
TA = -40°C to 85°C, vcc = 5V + 10%, VSS = OV
SYMBOL I
ITEM
TEST CONDITION I
MIN. ITYP .1 MAX. IUNITI
VILC I Low Clock Input
0.6 I V
I -0.3 I I
I
I
I Voltage
I
IVCC-0.6 I - IVCC+0.31 V
VIHC I High Clock Input
I Voltage
I
I
I
I
VIL
I Input Low Voltage
I -0.5 I - I 0.8 I V
I (Excq~t CLK)
I
I
I
I
2.2 I - Ivcc
VIH
I
I V
I Input High Voltage
I (Except CLK)
I
I
I
I
2.0mA
VOL
IOL
I Output Low Voltage
I
I 0.4 I V
I
I
I
I
-l.6mA
VOHI I Output High Voltage
IOH
2.4 I
I
I V
I (1)
I
I
I
VOH2 I Output High Voltage
IOH - -250uA
vcc-0.81 - I
I V
I (II)
I
I
I
ILl
VIN$ VCC
VSS~
I - I +10 I uA
I Input Leakage
I
I Current
I
I
ILO
VSS + 0.4< VIN
I Output Leakage
I - I +10 I uA
I Current
$ VCC
I
I
I
I
I
I
I
I
I
I
I
IL (SY) I SYNC Pin Leakage
VSS + 0.4< VIN
-40 I - I
10 I uA
I Current
~ VCC
I
I
I
I
I
I
I
VCC-5V
I P/F I
10 I
I 4 I
I
fCLOK=(l) 1-----1--------1----1-------1
I
ICCl I Power Supply Current I VIH=VIHC IAP/AFI
6
I 2.51
I mA
I
I
I
I =VCC-O. 2V I AP-6 I
I
I
I 4 I 10 I
I VIL=VILC I/AF-61
I
I =0.2V
I
I
I
I
I
I Standby Supply
I VCC=5V
I
I
I
I
ICC2 I
Current
10 I uA
I VIH=VIHC
I
I - I
=Vcc-0.2V I
I Except SYNC at
I
I
I
I
I "L" outj:!ut
I VIL=VILC=0.2V I
I
I
I
Note (1) fCLK=l/TeC(MIN.)
-264-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/AP-6
TMPZ84C43F/TMPZ84C43AFI AF·6
TECHNICAL DATA
4.3
AC ELECTRICAL CHARACTERISTICS
TA
NO.
I
2
3
= -40 o C to 8S o c, VCC = SV
SYMBOL
4
5
TcC
TwCh
TfC
TrC
TwCl
6
TsCS(C)
7
TsRD(C)
8
9
TdC(DO)
TsDI(C)
10
TdRD(DOZ)
+ 10%, VSS
=
OV
PARAMETER
Clock cycle time
Clock pulse width (High)
Clock fall time
Clock rise time
Clock pulse width (Low)
Control slgnal to clock!
setup time (CE, c/n, B/A)
IORQ, RD to clock'
setup time
Clock! to data out delay
Data in to clock
setup
(Write or Ml cycle)
RD , to data out float
delay
11
TdIO(DOI)
IORQ I to data out delay
(INTAClZ cycle)
12
TsMl(C)
M1 to clock \
time
13
TsIE1(IO)
14
TdMl(IEO)
15
TdIEI(IEOr)
16
17
TdIEI (lEOf)
TdC(INT)
18
TdIO(W/RWf)
19
TdC(W/RRf)
20
TdC(W/RWZ)
21
Th, Th (CS)
22
23
TwPh
TwPl
TcTxC
24
setup
lEI to IORQ I setup time
(INTAClZ cycle)
Ml I to lEO I delaL
(interrupt before Ml)
lEI I to lEO
delay
(after ED decode)
lEI j to lEO I delay
I 4MHz
I 6MHz
I
I
IPF, AP/AFIAP-6/AF-6IuNITI
IMIN.IMAX.IMIN.IMAX.I
1
1 2501 DC I 1651 DC I ns I
I 105 i DC I 70 I DC I ns 1
I - I 30 I - I 15 I ns I
I - I 30 I - I 15 I ns I
1 1051 DC 1 701 DC 1 ns 1
I
1
I
I
I
I
1 145 I - 1 60 I - 1 ns 1
I
1
I
I
I
1
I 115 I - I 60 I - I ns I
I
I
I
I
I ns I
I - I 220 I - I 150 I ns I
I
I
I
I
I
I
I 50 I - I 30 I - I ns I
I
I
I - I
I
I
I
I
I - I
I
I
I
I
I 90 I
I
I
11 0
I
I
I - I
I
90
I
I
I
120 I
I
I
I
I
-
I
I
I
I
I
160 I
I
-265-
I
1
-
I 2001
I 3301
I
I
ns
I
I
I
I
I
I
ns
I
ns
I
I
I
I
I
I
I
I
I
I
I
I
-
I
I
I
I ns
I
I
I ns
I 160 I - I - I llO I
I
I
I
I
I
I - I 1001 - I 70 I
I - I 2001 - I 15QI
Clockl to INTI delay
I
I
I
I
I
I
I
I
I
I
IORQ I or CE I to W/RDY I I - I 2101
- I 175 I
delay (Wait mode)
I
I
I
I
I
I
I
I
I
I
I - I 1201 - I 1001
Clock'
to W/RDY I delay
(Ready mode)
I
I
I
I
I
I
I
I
I
I
Clock I to W/RDY float
I - I 130 I - I 110 I
delay (Wait mode)
I
I
I
I
I
Any unspecified hold
I
I 0I - I 0I
when setup is specified
I
I
I
I
I
Pulse width (High)
I
I 200 I - I 200 I
TxC cycle time
I
I
I
I
I
- I 120 I
I
I
I
I
I
I
I
I
I - I 190 I - I
I 2001
I 4001
ns
I
I
160 I - I
I
I
I
I
- I 751
I
I
I 140 I
I
I
I
I
ns
ns
ns
ns
ns I
ns
1
I
I
I
I
ns
I ns I
I ns I
I
I
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/A,.&
TMPZ84C43F/TMPZ84C43AF/AF-&
TECHNICAL DATA
NO.
SYMBOL
25
TwTxCl
26
TwTxCh
27
TdTxC(TxD)
PARAMETER
TxC width (Low)
TxC width (High)
TxC I to TxD delay
(xl mode)
28
TdTxC(W/RRf)
TxC I to W/RDY I
(Ready mode)
29
TdTxC(INT)
30
TcRxC
31
TwRxCl
32
TwRxCh
!xC I
to INT I
delay
delay
RxC cycle time
RxC width (Low)
RxC width (High)
33
TsRxD(RxC)
RxD to RxC,
(xl mode)
34
ThRxD(RxC)
RxC I to RxD hold time
(xl mode)
35
TdRxC(W /RRf)
RxC ,- to W/RDY I
(Ready mode)
36
TdRxC(INT)
RxC
37
TdRxC(SYNC)
RxC I to SYNC I
(Output modes)
38
TsSYNC(RxC)
SYNC I to RxC I setup
(External sync modes)
(note)
I
setup time
to INT I
delay
delay
delay
I 4MHz
I 6MHz
I
I
IPF, AP/AF IAP-6/AF-6IUNIT I
IMIN.IMAX.IMIN.IMAX.I
I
I 180 I OQ I 100 I 00 I ns I
I
I
I
I
I
I
I 180 I 00 I 100 I c>o I ns I
I
I
I
I
I
I
I
I
I
I
I
I
- I 2201 ns I
I - I 3001
I
I
I
I
I
I
I
I
I
I
I CLKI
I
51
91
51
91 Peri I
I
I
I
I
lods*1
I
I
I
I
I CLKI
I
51
91
51
91Peril
I
I
I
I
lods*1
I 400 I 00 I 330 I 00 I ns I
I
I
I
I
I
I
I 180 I 00 I 100 I 00 I ns I
I
I
I
I
I
I
I 180 I 00 I 100 I 00 I ns I
I
I
I
I
I
I
I
I
I
I
I
I
01
- I
01
- I ns I
I
I
I
I
I
I
I
I
I
I
I
I
I
I 1401
- I 1001 - I ns I
I
I
I
I
I
I
I
I
I
I
I CLKI
I 101
131
101
13IPeril
I
I
I
I
lods*1
I
I
I
I
I CLKI
1101
131
101
13IPeril
I
I
I
I
lods*1
I
I
I
I
I
I
41
71
41
71 CLKI
I
I
I
I
I
lods*1
I
I
I
I
I
I
- 1-1001
- I ns I
1-1001
I
I
I
I
I
I
AC test condition
VIH=2.4V, VIHC=VCC-0.6V, VIL=0.4V, VILC=0.6V
VOH=2.2V, VOL=0.8V
CL=100pF
*
System Clock
In all modes, the System Clock rate must be at least five times
the maximum data rate.
Restart must be active a minimum of one
complete Clock cycle.
-266-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
4.4
TMPZ84C40,41,42P/TMPZ84C40,41,42AP/AP-&
TMPZ84C43F/TMPZ84C43AF/AF-6
Capacitance
SYMBOL I
ITEM
C CLOCK I Clock Input
I Capacitance
I
CIN
I Input Capacitance I
COUT IOutput Capacitancel
TEST CONDITION
f=1MHz
All terminals except that
to be measured should be
earthed.
-267-
lMIN.ITYP.lMAX.luNITI
I - I - I 7 I pF I
I
I
I
I
I
I - I - I 5 I pF I
I - I - I 10 I pF I
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41 ,42PflMPZ84C40,41 ,42AP/AP-6
TMPZ84C43FflMPZ84C43AF/AF·6
TECHNICAL DATA
4.5
Timing diagram
Numbers shown in the following figures correspond with those in the 4.3
A.C. Electrical Characteristics Table.
r-®.
eLK
J;,:---,
®
-~
~
I'h; r;;v ~QJ
®
-G)-
®
!~
Do-D7
®~
OJ)
'\
@J
d2
'\
~
lEI
~
'\
@
lEO
~
@
(i5)
/
1
Ifi)
"i
®
Fig. 4.1 (a)
@l
1
,...,
~~
Timing Diagram
-268-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41 ,42pnMPZ84C40,41 ,42AP/AP-6
TMPZ84C43FnMPZ84C43AFIAF-6
TECHNICAL DATA
TXD
y
I
@
T\
®
J
/
® J
®
RXD
{!;J
I
I
®
SYNC
®
Fig. 4.1 (b)
"l
'"
Timing Diagram
-269-
®
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
5.
TMPZ84C40,41,42P/TMPZ84C40,41 ,42AP/Ap·6
TMPZ84C43F/TMPZ84C43AF/AF·6
Package Dimension
Unit : mm
x
.;
:::;;
152 4± 025
o
~I'~~~~~~~~
o 5±0.15
1.4
2 54±0 25
0.15
Note 1.
This dimension is measured at the center of bending point of
leads.
Note 2.
Each lead pitch is 2.S4mm, and all the leads are located within
±O.2Smm from their theoretical positions with respect to No.1
and No.40 leads.
-270-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/AP.6
TMPZ84C43F/TMPZ84C43AF/AF·6
TECHNICAL DATA
5.
Outline Drawing
Unit in mm
44-pin mini-flat package
11tt
035
oB (PltCh)
140±Ol
. (l7.6± 0.3 )
.1
-
l.BO ± 0.25
MARK
'o"'
+I
If)
'o"'
J
.//\
(1.2±02)
(0.6 )
~
UUUUUl ~UUUUU
~:
~
If)
'0"'
If>.2±0.5
Fig. 5.1
Outline Drawing
-271-
,...,
~
'"'
......
If'
roi
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
6.
TMPZ84C40,41 ,42P/TMPZ84C40,41 ,42AP/AP-6
TMPZ84C43F/TMPZ84C43AF/AF-6
Precautions
In the programming US ing the SIO, it can be used only for single channe 1
according to registers and bits.
-272-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84C60P
TMPZS4C60P
CMOS ZSO Clock Generator/Controller
1.
General Description and Features
The TMPZS4C60P is a clock generator /controller for the TLCS-ZSO (CMOS)
Family (Microprocessor (MPU) and its peripheral LSI's) fabricated with
Toshiba's CMOS Sil icon Gate Technology. The TMPZS4C60P is provided wi th
two input terminals which are capable of selecting one of the following 3
modes when the TLCS-ZSO MPU execute the HALT instruction.
(1)
RUN Mode
The clock (CLK) output operation of the TMPZS4C60P is continued. The
TLCS-ZSO MPU is in the HALT state at this time and continues to
execute the NOP instruction.
(2) IDLE Mode
The clock (CLK) output by the TMPZS4C60P is stopped.
However, the
internal oscillator only continues to run.
(3) STOP Mode
The operation of the TMPZS4C60P is completely stopped.
In STOP Mode, the operation of the microcomputer system is completely
stopped.
Therefore, it becomes possible to keep the system at low
power consumption.
The TMPZS4C60P is molded in Toshiba's 16 pin standard DIP Package.
The principal functions and features of the TMPZS4C60P are as follows.
(1) Compatible with Toshiba CMOS ZSO (TLCS-ZSO)
(2) Low power consumption
2mA Typ (@SV, 4MHz operation)
SOOuA Typ (@SV 4MHz) (IDLE Mode)
10uA Less (@SV stationary) (STOP Mode)
(3) Single SV power supply (SV¢lO%)
(4) Extended operating temperature (-40'C to SS·C)
(S) The following 3 modes are selectable:
o
RUN Mode
q
IDLE Mode
o
STOP Mode
(Note)
Z80(R) is a registered trademark of Zilog Inc., U.S.A.
-273-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C60P
TECHNICAL DATA
2.
Pin Connections and Pin Functions
The pin connections and I/O
TMPZ84C60P are shown below.
2.1
pin
names
functions
of
the
vee
RsTII
DS
HALT
Ne
Ml
:RESET
RST02
MS2
RSTI2
MSI
eLK
XTAL2(XOUT)
vss
XTALl(XIN)
Fig. 2.1
Pin Connections
Pin names and functions
I/O pin names and functions of the TMPZ84C60P are as shown in Table 2.1.
Table 2.1
Pin Names and Functions
Pin Name INumber Input/Output
of Pin
3-state
1
Function
Input
Restart signal from clock (CLK) stop state
(Level trigger input)
Input
Hall signal (HALT) input
1
Input
Machine cycle 1 (Ml) signal input
1
Output
Restart signal RSTI2 output
1
Input
Restart signal from clock (CLK) stop state
(Ed e tri er in ut)
Single-phase clock output.
When the HALT instruction in STOP Mode is
executed, the TMPZ84C60P stops its operation
and holds clock out ut at "0" level.
Counter output stage selecting input.
Input to set up a warming-up time at time
of restart from the clock stop state in
stop mode.
HALT
Output
CLK
DS
brief
Pin connections
The pin connections of the TMPZ84C60P are as shown in Fig. 2.1.
Ne
2.2
and
1
Input
-274-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C60P
TECHNICAL DATA
Pin Name I Number I Input/Output I
lof Pinl 3-state
I
I
I
I
MSl, MS2 I
I
I
RESET
XTAL 1
( XIN)
XTAL 2
(XOUT)
2
2
NC
VCC
VSS
. 1
I Output
I
Input
I
I
I
I
I
Input
I
I Output
I
I
I
I
I
I
I
I
I
I Power supplyl
I
I
I
I
I Power supplyl
I
I
Function
Reset signal.
Restart signal from clock (CLK) stop state
(Level trigger input)
Mode selection input.
One of 3 modes (RUN, IDLE, STOP) is
selected according to the state of these 2
pins
Crystal oscillator connecting terminal
Use in the open state
+5V
OV
-275-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C60P
TECHNICAL DATA
3.
3.1
Description of Operation
The system configuration, functions and basic operation of the TMPZ84C60P
Clock G~nerator are described here.
Block diagram
The block diagram of the internal cinfiguration is shown in Fig. 3.1.
CLK
XTAL2
CONTROL CI RCUIT
XT/
The use of an LC circuit is not recommended for frequencies higher than
approximately 5 MHz.
- ---1
Xl
-L Cint
T
Lex
X2
I
___ J
C.
TMP8085A
I
" 15 pF
RC Circuit Clock Driver
An RC circuit may be used as the frequency - determining network for the
TMP 8085A if ma1ntaining a precise clock frequency is of no importance.
Variations in the on-chip timing generation can cause a wide variation
in frequency when using RC circuit. The driving frequency generated by
the circuit shown is approximately 3 HHz. I t is not recommended that
frequencies greatly higher or lower than this be attempted.
f
-305-
3 MHz
TOSHIBA INTEGRATED CIRCUIT
TMP8085AP/TMP8085AP-2
TECHNICAL DATA
D.
External clock Driver Circuit
+5V
Duty 1,5 '\, 55%
470 II
+SV
TMP808SA
470 II
POWER ON AND RESET IN
The TMP 80SSA is not guaranteed to work until 10 ms after Vce reaches 4.75 V.
It is suggested that RESET IN be kept low during this period.
Note that the 10 ms period does not lnclude the time it takes for the power
supply to reach its 4.75 V level.
-306-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPB085AP/TMP8085AP-2
INSTRUCT ION SET
Symbols and Abbreviations
DEFINITION
SYHBOLS
ddd,sss
The bit pattern deSignating one of the registers
A,B,C,D,E,H,L (dJd-destination, bSS=source):
REGISTER NAME
ddd or sss
111
000
001
010
A
B
C
all
°E
100
101
110
H
L
H (:1emory)
r,rl,r2
One of the registers A,B,C,D,E,H,L
dS
8-bit data quantity
d16
l6-bit data quantity
addr8
8-bit address of an I/O device
addr
16-bit address quantity
RP
The bit pattern designating one of the register
pairs B,D,H,SP:
RP
00
01
10
11
rp
REGISTER PAIR
(rpH)(rpL)
B
D
H
SP
B-C
D-E
H-L
SP
The second byte of the instruction
The third byte of the instruction
Affected
S
Set
R
Reset
Not affected
-307-
TOSHIBA INTEGRATED CIRCUIT
TMPB085AP/TMP8085AP-!
TECHNICAL DATA
Data Transfer
Mnemonic
Instruction Code
D7 Db Ds D, 03 02 DI 00
1
d
MOV rl, r2
0
HOV M, r
0
1
1
MOV r, M
0
1
d
S
S
(r 1) •
S
S
S
[(H) (L)]
1
1
0
(r)
<<-
d
S
1
0
d
d
d
MYI r, d8
0
0
d
d
MYI M, d8
0
0
1
1
LDA addr
0
0
1
1
Flag
Bytes States C
Z S P AC
Operation
(r2)
1
4
-- - - - --- -- - - -- - - -
(r)
1
7
[(H)(L)]
1
7
(Bd
2
7
2
10
--
-
- -
--
-
- -
<-
d
1
1
0
(r)
0
1
1
0
[(II)(L)]
1
0
1
0
(A)'" [(B3)(B2)]
3
13
1
0
1
0
(A)
[(B)(C)]
1
7
1
7
3
16
--- - ---- - - - - -
3
10
- --- -
3
10
---- -
3
10
--
3
10
---- -
3
16
--- -
-
3
13
---
-
B2
<-
(B2 )
B2
B2
B3
LDAX B
0
0
0
0
<-
LDAX D
0
0
0
1
1
0
1
0
(A) ... [(D)(E)]
LHLD addr
0
0
1
0
1
0
1
0
(L)
+-
[ (B3)(B2)]
(H)
<-
[(B 3 )(B 2 )+1]
B2
B3
LXI H, d16
0
0
1
0
0
0
0
1
B2
(H)
<-
(B3)
(L)
<-
(B2)
(D)
<-
(B 3 )
(E)
<-
(B2)
(B)
<-
(B3)
(C)
<-
(B2 )
B3
LXI D, d16
0
0
0
0
1
0
0
1
B2
B3
LXI B, d16
0
0
0
0
0
0
0
1
B2
-- -
B3
LXI SP, d16
0
0
1
0
1
0
0
1
(SP)II
<-
(B 3 )
(SP)L ... (B 2 )
B2
B3
SHLD addr
0
0
1
0
0
0
1
0 TIB 3 ) (B2)]
B2
<-
(L)
(Il)
[(B 3 )(B2)+1]
-+-
[(B3)(B2)]
(A)
B3
STA addr
0
0
1
0
1
0
1
0
B2
B3
-308-
<-
-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
Mnemonic
TMPB085AP/TMP8085Ap·2
f:::-_.-!!1.~~!:~£~!~~o<.!~
Operation
D7 Db Ds D, D D2 D\ Do
Bytes Stdtes
j
STAX B
0
0
0
0
0
0
1
0
[ (B) (C) J
<-
(A)
<-
(A)
STAX D
0
0
0
1
0
0
1
0
[(D)(E»)
SPHL
1
1
1
1
1
0
0
1
(SP)
XCIIG
\1
1
1
0
1
0
1
1
(H)
+->
(D)
(L)
+-+
(E)
(I.)
<->
[(SP»)
(H)
+-+
[(SP)+l)
(H)(L)
<-
XTHL
IN addr8
1
0
0
0
1
1
1
0
1
1
(A) <-
0
0
1
1
(data)
1
1
0
1
7
1
7
1
~-f
1
OUT addr8
1
1
0
1
- - - - - --- - - - - -
1- -
1-
4
1
16
i_ I
(data)
2
10
-
(A)
2
10
B2
r----
-
1
I
I
i1 1
Flag
C Z S P AC
<-
-
- -
- -
-
-
-- - - - - - -- - - -
B2
Branch
Mnemonic
.niP addr
Instruction Code
D7 Do Ds D, D3 D2 D\ Do
1
1
0
0
Operation
0
0
1
1
(PC)
0
0
1
0
If Z = 0
<-
(B 3)(B2)
Bytes States
Flag
C Z S P AC
-- - -
-
3
10
3
7/10
-- -- -
3
7/10
-
-
-
-
3
7/10
-
-
-
- -
3
7/10
- - - -
B2
B,
JNZ addr
1
1
0
0
(PC)
B2
<-
(B3) (B2),
I
B3
If
Z= 1
(PC) ..- (PC) + 3
JZ addr
JNC addr
1
1
1
1
0
0
0
1
0
1
0
If
Z= 1
B2
(PC)
B3
If Z = 0
0
1
0
1
0
B2
(PC)
B,
If C = 1
1
1
0
1
1
0
1
0
If
<-
(B 3) (B 2 ),
(PC) + 3
C= 1
B2
(PC)
B3
If
<-
(63)(B2),
C= 0
(PC)
-309-
<-
<-
-
(B3)(B2),
(PC) <- (PC) + 3
If C = 0
(PC)
JC addr
<-
(PC) + 3
-
TOSHIBA INTEGRATED CIRCUIT
TMPBOB5AP/TMPBOB5AP-2
TECHNICAL DATA
Mnemonic
JPO addr
Instruction Code
D7 D6 D~ D4 D3 D2 DJ Do
1
1
1
0
0
0
1
0
B3
1
1
1
0
If P=O
(PC)
B2
JPE addr
Operation
1
0
1
0
-.:
B2
1
1
0
3
7/10
- --- -
3
7/10
-
- - - -
3
II 7/10
-
--
-
- - - -
(PC) .. (B 3 )(B 2 ),
If P = 0
0
1
Flag
C Z S P AC
+3
If P = 1
(PC)
1
States
(B3)(B2),
IIfP=l
(PC) .- (PC)
B3
JP addr
-<-
Bytes
1
0
-<-
(PC)
+3
IIfS=O
I
-
-
I
B2
(PC) .. (B 3 )(B 2 ),
B3
If S = 1
(PC)
JM addr
1
1
1
1
1
0
1
0
1
1
0
(PC)
B3
If S = 0
0
1
1
0
1
(PC)
+3
If S = 1
B2
(PC)
CALL addr
-<-
-<-
-<-
I
3
7/10
3
18
3
9/18
-
3
9/18
- --- -
(B 3 )(B2),
(PC)
+3
[(SP)-l)
-<-
(PCR)
B2
[(SP)-2)
-<-
(PCL)
B3
(SP) ... (SP) - 2
- - - -
-
(PC) .. (B3)(B2)
CNZ addr
1
1
0
0
0
1
0
0
B2
B3
If Z = 0,
the actions
specified in the
CALL instruction
are performed.
-- - -
If Z = 1
(PC) ... (PC)
CZ addr
1
1
0
0
1
B2
B3
1
0
0
+3
If Z = 1,
the actions
specified in the
CALL instruction
are performed.
If Z=O,
(PC) .. (PC)
-310-
+3
TOSHIBA INTEGRATED CIRCUIT
TMP8085AP/TMP8085AP-2
TECHNICAL DATA
Mnemonic
CNC addr
Instruction Code
D7 D6 D5 D, D3 D2 DJ Do
1
1
0
1
0
1
0
0
Bytes St:ltes
Operation
If C = 0,
B3
If C = 1
(PC)
1
1
0
1
1
1
0
B3
1
1
0
0
1
0
0
(PC)
+3
I
If C = 0
I
<-
(PC) + 3
If P = 0,
the actions
spec i f ied in the
CALL instruction
are performed.
B2
B3
I
If C = 1,
the actions
specified in the
CALL instruction
are performed.
(PC)
1
<-
I--
0
B2
CPO addr
- - - - -
the actions
specif ied in the
CALL instruction
are performed.
B2
CC addr
9/J 8
3
Fla~
C Z S P AC
[
3
~
I
9/18
- - - - -
I
I
,
;--k"
-
- - - -
I
If P = 1
(PC)
CPE addr
1
1
1
1
0
1
0
0
<-
(PC) + 3
If P = 1 ,
B3
-
-
-
- - -
-
3
9/18
- -
3
9/18
-
the actions
specified in the
CALL instruction
are perf ormed.
E2
If P=O
(PC)
CP addr
~
1
1
1
0
B2
B3
1
0
0
<-
(PC) + 3
If S = 0,
the actions
specified in the
CALL instruction
are performed.
If S = 1
(PC)
<-
-311-
(PC) + 3
TOSHIBA INTEGRATED CIRCUIT
TMPB085AP/TMP8085Ap·2
TECHNICAL DATA
Instruction Code
Mnemonic
CM addr
1
1
1
1
1
Flag
Byte" ~Llte" C Z 5 P AC
Operation
100
9/lB
3
IfS=l.
the actions
specified in the
CALL instruction
are performed.
If5=O
(PC) +- (PC) + 3
I-R-E-T----+1-1--0-0--1-0-0--1-+-(-P-C--L)--+-
1
i
i
I'
I
I
iI
i
I
- - -
-reS?) ]- --t--l--- i --lo--T~ -:::-
(PCH) •
[(5P)+1 J
+
i
I
'
RZ
I1
100
100
0
IfZ=l.
the actions
specified in the
RET instruction
-are performed.
IfZ=O
( PC) +- ( PC)
II
I
I
(5P) +- (5P) + 2
1------+----------+------- - - - - RNZ
1 1 0 0 0 0 0 0
If Z =0.
1
the ac t ions
specified in the
RET instruction
;:::p:;:::~::
:::----~-
I
----r-----6/121- - - -
I
I
I
I
6/12
1
-
l--------
I
+1
I------I----------+----------+--~---+------~
RNC
o
1
0
000
6/12
If C=O.
the actions
specified in the
RET instruction
are performed.
If C = 1
(PC) +- (PC)
-312-
+1
TOSHIBA INTEGRATED CIRCUIT
TMP8085AP/TMP8085AP-2
TECHNICAL DATA
Hnemonic
!
Instruction Code
110
RC
1
100
Bytes S t .J t '-' ~ f-_~F~l-=d~g'---I
Operation
ID7 D6 Ds D4 D3 D2 D1
C Z S P AC
:-
o
6/12
If C=l,
- - - -
-
the actions
I specified in the
I RET instruction
i dre performed.
I
!
I
I
If C
=0
+
(PC) + 1
,
P-=--0 -,---- - ---..---;.\--1-';"1-6-/-1-2---------------j
the actions
i
specified in the
I
RET instruction
are performed.
I
I
(PC)
11-
f-R-po-----+,-1--1-1--0--0--0--0-0-i- f-
1
I,
,
I
I
IfP=l
:
(PC) -<- (PC) + 1
i
~R-P-E----~:-1--1--1-0--1-0--0--0-+-I-f-P-=-1-,----~
the actions
specified in the
RET instruction
are performed.
I
i
I
I
I
6/12 1',1-
I
i
If P=O
(PC)
RP
'11110000
-<-
(PC) + 1
6/12
IfS=O,
the actions
specified in the
RET instruction
are pe r formed.
- - - -
-
- - - -
-
I
I
IfS=l
I, (PC)
RM
1
1
1
1
1
0
0
0
-<-
(PC) + 1
IfS=l,
the actions
specified in the
RET instruction
are performed.
If S
=0
(PC)
~
-313-
(PC) + 1
1
6/12
TOSHIBA INTEGRATED CIRCUIT
TMP8085AP/TMP8085Ap·2
TECHNICAL DATA
Mnemonic
PCHL
Instruction Code
D7 D6 Ds D4 D3 D2 Dl
Do
1
1
11
RST
1
1
1
A
1
0
A
A
0
1
0
1
1
Operation
(PCH)
~
(H)
(PCL)
<-
(L)
[(SP)-1) <- (PCH)
[(SP)-2)
<-
~ytes
States
1
6
1
12
Flag
C Z S P AC
-
-
- - -
- - - - -
(PCL)
(SP)
~
(SP) - 2
(PC)
~
(00000000
OOAAAOOO)
Arithmetic
Mnemonic
Instruction Code
D7 D6 Ds D. D3 D2 Dl Do
Operation
Flag
Bytes States rc--zSpoAC
ADD r
1
0
0
0
0
S
S
S
(A)
<-
(A)+(r)
1
4
000 0 0
ADC r
1
0
0
0
1
S
S
S
(A)
<-
(A) + (r) + (C)
1
4
o
0 0 0 0
ADDM
1
0
0
0
0
1
1
0
(A)
~
(A)+[ (H) (L) )
1
7
0 0 0
ADCM
1
0
0
0
1
1
1
0
(A)<- (A) +[(H XL») +( C)
1
7
o
o
ADI dB
1
1
0
0
0
1
1
0
(A)
2
7
000 0
0
ACI dB
1
1
0
0
1
1
1
0
(A) <- (A)+(B2)+(C)
2
7
() 0 0 0
0
<-
(A) + (B2)
0
000 0
B2
B2
DAD rp
r---suB-
0
0
R
P
1
0
0
1
(H) (L) <- (H) (L)
+ (rH)(rL)
1
10
1
0
0
1
0
S
S
s
(A) <- (A) - (r)
1
4
o - - - -
SBB r
1
0
0
1
1
S
S
S
(A)
(A) - (r) - (C
1
4
SUB M
1
a a
1
0
1
1
0
(A) <- (A) - [ (H)(L) )
1
7
SBB M
1
0
0
1
1
1
1
0
(A)<-(A) - [(H XL»)- (C)
1
7
o0
o0
o0
o a
SUI dB
1
1
0
1
0
1
1
0
(A)
2
7
000 0 0
1
1
1
0
(A)
2
7
000 0
r
+-
+-
(A) - (B2 )
0 0
0
0 0
0 0
a
a
0 0
0
--
B2
SBI dB
1
1
0
1
~
(A) - (B2) - (C
B2
-314--
a
TOSHIBA INTEGRATED CIRCUIT
TMPB085AP/TMP8085Ap·2
TECHNICAL DATA
Mnemonic
DAA
Instruction Code
D7 D. Ds D, D3 D2 DI Do
0
0
1
0
0
1
1
1
Operation
Bytes States
The 8-bit number
in the accumulator
is adjusted to
form two 4-bit BCD
digits by the
following process.
Accumulator
7
4 3
I
I
X
0
y
~)
cd
I
1. If Y ~ 10 or
AC=l,
(A)-+-(A)+6
2. If
X~
10 or
C=l,
(A) 4-7 -+-(A).-7 +6
-315-
1
4
Flag
C Z S P AC
0 000 0
TOSHIBA INTEGRATED CIRCUIT
TMP8085AP/TMP8085AP-2
TECHNICAL DATA
Logical Instruction
Mnemonic
Instruction Code
D7 D6 Ds D, D3 D2 DI Do
Operation
ANA r
1
0
1
0
0
S
S
S
(A)
ANA M
1
0
1
0
0
1
1
0
(A)
ANr d8
1
1
1
0
0
1
1
0
(A)
+-
+-
(A) 1\ (r)
+-
Flag
C Z S P AC
1
4
ROO 0
S
1
7
ROO 0
S
(A) 1\ (62)
2
7
ROO 0
S
(A) '-
Bytes States
Flag
C Z S P AC
-- - -
1
12
-
1
12
- - --
1
10
-- - - -
1
10
o
(SP) - 2
Note: Register
pair rp=SP may not
be specified.
PUSII PSW
1
1
1
1
0
1
o.
1
[(SP)-IJ
+-
[(SP)-2]
<-
(A)
-
C7DGD 5D. D 3D.!DIDo
Is IzlxlAclxlplxlcl
HSB
(SP)
POP rp
1
1
R
P
0
0
0
1
<-
(rH)
<-
(Sp)
POP PSW
1
1
1
1
0
0
0
1
(SP) - 2
(rr,) <- [ (SP) ]
<-
[ (SP)+l]
(SP)+2
(C)
<-
[(SP)]o
(p)
<-
[(SP)
(AC)
<-
lz
[(SP»).
(Z)
<-
(S)
<-
10
[(SP) 17
(A)
+-
[ (SP)+l]
(SP)
[(SP)
+-
-317-
(SP) + 2
0 0 0
0
TOSHIBA INTEGRATED CIRCUIT
TMP8085AP/TMP8085Ap·2
TECHNICAL DATA
Control
Mnemonic
Instruction Code
D7 D6 Ds D, D3 D2 Dl Do
Operation
Bytes
States
c
Flag
Z S P Ae
0
4
--- -- o - - -
-
1
4
- - - -
-
1
4
- - -
-
-
HLT
0
1
1
1
0
1
1
0
Halt
1
5
STe
a a
1
1
0
1
1
1
(C)
+
1
1
4
CMe
0
0
1
1
1
1
1
1
(C)
<-
(e)
1
EI
1
1
1
1
1
0
1
1
Enable interrupts
Note: Interrupts
are not recognized
during the EI instruction.
DI
1
I
1
1
0
0
1
I
Disable interrupts
Note: Interrupts
are not recognized
during the DI instruction.
-
- -
NOP
0
0
0
0
0
0
0
0
No operation is
performed.
1
4
- -
RIM
0
0
1
0
0
0
0
0
(A)
1
4
-
-
- -
1
4
-
-
-
SIM
0
0
1
1
0
0
0
0
+
d7
;
SID
d6
=
17
ds
=
16
d,
=
IS
d3
=
IE
d2
=
H7
dl
=
H6
do
=
MS
IF(AlG
SOD
.
= l'
(Al?
+
,IF(Ah
= 1;
M7
+
(A)2
H6
+
(A)I
HS
+
(A) a
.IF(Aj.
RST7.S
-318-
.
= l'
RESET
- -
TOSHIBA INTEGRATED CIRCUIT
TMPB085APnMP8085AP-2
TECHNICAL DATA
ABSOLUTE HAXIHUM RATINGS
Symbo I
Vrr
VIII
V" It
Pn
T.nl Iio r
Totn
T"nr
Ratings
Item
Un its
Vcc Supply Voltage
-0.5~+7.0
V
-0.5~+7.0
Input Voltage With Respect to Vs~
V
-0.5~+7.0
Output Voltage With Respect to Vc~
V
Power Dissipation
1.5
W
Soldering Temperature (Soldering Time 10 sec.) 260(10sec)
'C
Soldering Temperature
-55~ 150
'C
Operating Temperature
0~70
'C
DC CHARACTERISTICS
TA=O'C to 70'C, Vcc=5V± 5%
SYlIIbo I
VI
V
Vn
Vn,
II'I'
I
II n
V D
V1HI1
VU "
Parameter
Test Conditions
Input low Voltage
Input High Voltage
Output low Voltage
IOl=2mA
Output High Vojtage
IOH=- 400uA
Power Supply Current
O;;;VIN ;;;VCC
Input leakage
Output leakage
0.45 ;;; VOUT;;; VCC
Input low level ( RESET)
Input High level (RESET)
Hysteresis (RESET)
-319-
Hin.
-0.5
2.0
Hax.
O/B
VCC+0.5
2
-0.5
2.4
O. 25
-0.4
170
± 10
± 10
0.8
VCC+0.5
Uni ts
V
V
IIA
RIA
RIA
uA
uA
V
V
V
TOSHIBA INTEGRATED CIRCUIT
TMPB085AP/TMP8085AP-2
TECHNICAL DATA
AC CHARACTERISTICS
TA;O"(; to 70"(;,
Symbol
Vcc=5V±5~,
Vss=OV, Unless Otherwise Noted.
Parameter
ClK Cycle Period
ClK low Time - Standard 150pF loading
- Lightly Loaded(2)
ClK
High
Time
- Standard 150pF loding
tH
- Lightly Loaded(2)
tLtC ClK Rise and Fal I Time
tXKR Xl Rising to ClK Rising
Xl Rising to ClK Fall ing
tXKf
A8-15 Val id to leading Edge of Control(1)
tAl'
tAf.1 AO-7 Val id to Leading of Control
AO-15 Val id to Val id Data In
tAO
Address
Float after leading Edge of READ
tAFR
tf. 'it
tl
THP8085AP THP8085AP-2 Uni ts
Hi n. Hax. Hi n. Hax.
320 2000 200 2000 ns
40
ns
80
100
50
ns
120
70
ns
150
80
ns
30
30
ns
30 120
30 100
ns
30 150
30 110
ns
ns
270
115
240
115
ns
575
350
ns
ns
0
0
( INT)
A8-15 Val id before Trai I ing Edge of AlE[l)
tAL
tAil AO-7 Val id before frail ing Edge of ALE
tARV READY Val id from Address Valid
Address (A8-15l Val id after Control
tl'A
Width of Control low(RD,WR,INTAl
tcc
Edge of ALE
Trail ing Edge of Control to leading Edge
tCL
of ALE
Data Valid to trailing Edge of WRITE
tow
HlDA
to Bus Enable
tHARF
tHARF Bus Float after HlDA
~AI'K HlDA Val id to Trail ing Edge of ClK
t HOII HOLD Itold Time
tHO!> HOLD Setup Time to Trai ling Edge of CLK
tUIH INTR Hold Time
-320-
50
50
120
400
60
230
ns
ns
ns
ns
ns
50
25
ns
115
90
220
420
100
230
210
210
110
0
170
0
150
150
40
0
120
0
ns
ns
ns
ns
ns
ns
ns
TOSHIBA INTEGRATED CIRCUIT
TMP8085APITMP8085AP-2
TECHNICAL DATA
Symbol
Parameter
tiNS
INTR, RST and TRAP Setup
~~
Address Hold Time after
THP808~AP
THP808SAP-2 Un its
Hi n_
Hi n,
--
Ti~e
to f aII i ng
Hax,
Hax
ns
160
150
100
50
ns
130
60
ns
--
Edge of ClK
------- -- -- --- - --
ALE
Trai ling Edge of ALE to leading Edge
tlC
of Control
t I CoK
100
ALE low during ClK High
ALE to Valid Data during Read
~HL - - - - - - - - - Data during \oIr i t e
~IL AU to Valid
-ALE
Width
tI I
ALE to READY Stable
t I RY
200
ns
270
120
ns
flS
80
140
ns
30
110
--
tRAE
50
460
ns
-~
Trailing Edge of READ to Re-Enabl ing of
90
150
ns
Address
~
READ (or INTA)to Val id Data
300
I
"'----
Control Trai I ing Edge to leading Edge of
tRV
150
ns
400
220
ns
0
0
ns
0
0
ns
Next Control
__t RillL
Data Hold Time
~-
READY Hold TIllie
After READ IHTA
IRYS
READY Setup Time to leading Edge of ClK
110
100
ns
~rHl
Data Va lid After Tra iii no Edge of IIRI TE
100
60
os
t W01
LEADING Edge of WRllE to Data Val id
20
Cl=150p
Test conditions,
rHP808~AP
40
tcYc=J20ms
THP8085AP-2 : tcYc=200ms
Notes: 1, A8-15 address specs apply to 101H, SO and Sl except A8-15
are undlfined durlrgT4 - T6 of OF Cycle whereas 101H, SQ, and
51 are stable,
2, LOading equivalent to 50 pF
+
1 TTL input,
3, All timings are measured at output voltage
Vlo08V,
VH=20V>
10 calculate timing specifications at other value of
use 1ab I e 4,
-321-
[cye
ns
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TABLE 4.
TMPB085AP/TMP8085AP-2
BUS TIMING SPECIFICATION AS A TCYC DEPENDENT
tAL
(l/2 ) T - 45
MIN
tLA
(1/2) T - 60
MIN
tLL
(1/2) T - 20
MIN
tLCK
(l/2) T - 60
MIN
tLC
(1/2) T - 30
MIN
tAD
(5/2+N) T - 225
MAX
tRD
(3/2 + N) T - 180
MAX
tRAE
(l/2) T - 10
MIN
tCA
(1/2) T - 40
MIN
tDW
(3/2 +N) T - 60
MIN
two
(l/2) T - 60
MIN
tcc
(3/2 +N) T - 80
MIN
tCL
(l/2) T - 110
MIN
tARY
(3/2) T - 260
MAX
tHACK
(1/2) T - 50
MIN
tHABF
(l / 2) T + 50
MAX
tHABE
(1/2) T + 50
MAX
tAC
(2/2) T - 50
'MIN
tL
(l/2) T - 80
MIN
tH
(1/2) T - 40
MIN
tRY
tLDR
(3/2) T - 80
(4/2) T - 180
MIN
Note:
MAX
N is equal to the total WAIT states.
T
=
tcyC
-322-
TOSHIBA INTEGRATED CIRCUIT
TMPB085AP/TMP8085AP-2
TECHNICAL DATA
Xl INPUT
CLK OUTPUT
tXKR
I~_ _t--=L~---I tCYC
tXKF
FIGURE 4.
CLOCK TIMING WAVEFORM
T3
CLK
~
tLCK
=>
==><
ADDRESS, STATUS
tAO
tLA
tLL
tAL
f--.::..:=.-
tLC
tAC
tRDH
- p- tCL
tLDR
-y
I---- tAFR
tRD
II
Ir
tcc
J.i
FIGURE 5.
READ OPERATION
I
T3
\~_--'/
=><
=><
\'-----'/
\'------/
\'----
><--
ADDRESS, STATUS
tCA
)<
ADDRESS
DATA
tDW
tLDW
tWDL
ALE
-----c=
DATA IN
N.
CLK
-,
tRAE
>
1>-- -
ADDRESS
I
ALE
tCA
---
tWD
.f
\
tCL
tLC
tAC
tcc
1
FIGURE 6.
-K--
OUT
WRITE OPERATION
-323-
I
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8085AP/TMP8085Ap·2
TWAIT
CLK
ALE
RD/ INTA
---+--+------.1 1---+----------------1 i r - - - - - - -
READY
FIGURE 7.
READ OPERATION WITH WAIT CYCLE (TYPICAL)
- SAME READY TIMING APPLIES TO WRITE OPERATION
I
T3
THOLD
I
CLK
INTR
HOLD
~----------~----r--~rl----------------
tH_D_S_-Jt==~~t~H~D~H-+--~~
_ _ _ _ _ _ ____
,-_.j
'----__
_ ______________
HLDA ____________________-rHM~~
tHACK
ADO", 7
~Ir------~
__~
tBABF
_tHARE
ADDRESS
--->t-----------
XADDRESS >- ---(CALL INSi)- - -
---ff------------
,
INTA
BUS FLOATING
"---:ff-----------.f
WR, RD
FIGURE 8.
INTERRUPT AND HOLD TIMING
-324-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8085AP/TMP8085AP-2
OUTLINE DRA\nNG
40 39 !J8 37 36 35 34 33
32 31 30 29 28 27 26 25
~4
23 22 21
Unit in mm
2
3
4
b
7
8
~
10
11 12 J3 J4
10 Ib J7
l~
18 4J
(Note
'"
o
rl
0
-H
-H
o
"'
1)
f "'j'" ~
o 25± 01
254±025
05±01
(Note 2)
14±015
15 0D-17 80
a Z5TYF
Ob±OJ
Note: 1.
2.
This dimension is measured at the center of bending point of leads.
Each lead pitch is 2.54mm, and all the leads are located within
±O.2Smm from their theoritical positions with respect to No.1 and
No.40 leads.
-325-
TOSHIBA INTEGRATED CIRCUIT
TMPB085APnMPB085AP-2
TECHNICAL DATA
-326-
TOSHIBA INTEGRATED CIRCUIT
TMP8085HPITMPB085AHP-2
TECHNICAL DATA
TOSHIBA MaS DIGITAL INTEGRATED CIRCUIT
N-CHANNEL SILICON GATE MOS
8-BIT SINGLE CHIP MICROPROCESSOR
GENERAL DESCRIPTION
The T.-!p8085AHP / AHP -2, from here on referred to as the TMP8085A, is world
standard, complete 8 bit parallel central processing unit (CPU).
Its high
level of-system integration allows a minimum system of there IC's : TMP8085A
(CPU), TMPB155P /TMPB156P (RA.'1/IO) and TMP8355P (ROM/IO). The TMP8085A uses a
multiplexed data hus. The address is plit between the 8 bit address bus and
the 8 bit data bus. The on-chip address latches of TMP8l55P/TMP8156P/TMPB355P
memory products allow a direct interface with TMPB085A.
FEATURES
O.BuSec Instruction Cycle (TMP8085AHP-2 : CLK Cycle Period @200nSec)
Single +5V Power Supply (5V+IO%)
On-Chip Clock Generator (with External Crystal or RC Network)
On-Chip System Controller; Advanced Cycle status information available for
Large System Control
4 Vectored Interrupts (One is Non-Maskable)
Decimal, Binary and Double Precision Arithmetic
Serial In/Serial Out Port
Direct Addressing Capability to 64K Bytes of Memory
Low Power Consumption (Icc max = l35mA)
PIN CONNECTION
(TOP VIEW)
Xl
X2
RESET OU
SO
SI
BLOCK DIAGRAM
INTR
RST5.5,6.5,7.5
TRAP
5
VCC
HOLD
HLDA
CLK(OUT)
RESET IN
READY
10/M
S)
RD
WR
ALE
So
Al5
A )I.
A l3
AI2
All
AIO
Ag
As
,...----'-----,...RESET OU'j
ESET IN
eLK X~D So ALE HOLD
FI GURE 2. Tt1P8085A PINOUT
DIAGRAM
XI WR
DATA/ADDRESS BUS
ADn-i
-327-
ADDRESS BUS
AR-l'i
SI HLDA
'INTA 10/M READY
FIr,URE 2. TMP8085A
PINOUT DIAGRAM
TOSHIBA INTEGRATED CIRCUIT
TMP8085HP/TMP8085AHp·2
TECHNICAL DATA
DRIVING THE Xl and X2 INPUTS
You may drive the clock inputs of the TMP8085A with a crystal, an LC
turned circuit, an RC network or an external clock source.
The driving
frequency must be at least 1 ~ffiz, and must be twice the desired internal cloc~
freq uency.
A.
Quartz Crystal Clock Driver
If a .crystal used, it must have the following characteristics.
Parallel resonance at twice the clock frequency desired.
Cs (shunt capacitance) ~ 7 PF
RS (equivalent shunt resistance)
~
~
<
75 ohms
Xl
G2Z3
f
THP8085AP
1~----~----~X2
L -_ _ _ _ _ __
C2
Note a value
ground.
of
the
external
capacitance
We recommended the following.
Hffiz
< f < 4MHz:
C1 =20pF, C2 =20pF
4MHz
S.
f
S.
C =lOpF, C2 =lOpF
1
8MHz
S.
f
< 10MHz:
8MHz:
C =0
1
'
C =0
2
-328-
Cl and
C2 between Xl,
X2 and
TOSHIBA INTEGRATED CIRCUIT
TMP8085HP/TMP8085AHp·2
TECHNICAL DATA
B
LC Turned Circuit Clock Driver
A parallel-resonant LC circuit may be used as the frequency-determining
network for the TMP8085A, providing that its frequency tolerance of
aproximately 10% is acceptable. The components are chosen from the
formula.
f
=
211
J
L (C
ext
+ C.
:tnt
)
The use of an LC circuit is not recommended for frequencies higher than
approximately 5 MHz.
----,
Xl
TMP8085A
I
..L
Lex
C.
T
I
___ J
X2
Cint
= 15
pF
RC Circuit Clock Driver
An RC circuit may be used as the frequency - determining network for the
TMP8085A if maintaining a precise clock frequency is of no importance.
Variations in the on-chip timing generation can cause a wide variation in
frequency when using RC circuit. The driving frequency generated by the
circuit shown is approximately 3 MHz. It is not recommended that
frequencies greatly higher or lower than this be attempted.
f
-329-
3 MHz
TOSHIBA INTEGRATED CIRCUIT
TMP8085HP/TMP8085AHP-2
TECHNICAL DATA
D.
External Clock Driver Circuit
+SV
Duty l,S '\, 55%
TMP8085A
POliTER ON MI) RESET 1/\
The TMP808SA is not guaranteed to work until 10 ms after vec reaches
4.S0V. It is suggested that RESET IN be kept low during this period.
Note that the 10 ms period does not include the time it takes for the
power supply to reach its 4.S0V level.
-330-
TOSHIBA INTEGRATED CIRCUIT
TMP8085HP/TMP8085AHp·2
TECHNICAL DATA
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VIN
\lout
PD
Tsolder
Tstg
Topr _
eet to VSS
Output Voltage with Respect to VSS
Power Dissi ation
Soldering Temperature
Storage Temperature
Operating Temperature
Ratings
-0.5 to +7.0
-0.5 to +7.0
-0.5 to +7.0
1.5
260 (10 sec
-65 to 150
o to 70
Units
v
v
v
w
C
C
C
DC CHARACTERISTICS
Srmbol
VIL
VIH
VOL
VOH
ICC
IlL
ILO
VILR
VIHR
VHY
Parameter
Input Low Voltage
Input High Voltage
OulJ:~ut Low Voltage
Output High Voltage
Power Supplr Current
Input Leakage
Test Conditions
I
I
I
I IOL-2mA
I IOH=-400uA
I
I o ~ VIN ~ vce
I
Output Leakage
I 0.45 ~ VOUT ~ VCC
I
Input Low Level (RESET) I
Input High Level (RESET) I
Hlsteresis (RESET)
I
-331-
Min. I Max. IUnits
-0.5 I 0/8
I V
2.0 IVCC+0.51 V
I 0.45 I V
2.4 I
I V
I mA
I 135
I +10
I uA
I
I
I +10
I uA
I
I
-0.5 I 0.8 I V
2.4 IVeC+0.51 V
0.25 I
I V
TOSHIBA INTEGRATED CIRCUIT
TMP8085HP/TMP8085AHP-2
TECHNICAL DATA
AC CHARACTERISTICS
TA=OoC to 70 0 C, Vcc=5V~10%, Vss=OV, unless otherwise noted.
I
I
I Symbol I
I tCYC
ItL
I
ItH
I
Itr,tf
ItXKR
I tXKF
I tAC
I
I tACL
I tAD
ItAFR
I
I tAL
I
I tALL
ItARY
I tCA
I tCC
I
I tCL
I
ItDW
I tHABF
I tHABF
ItHACK
I tlIDH
I tlIDS
I
ItINH
ItINS
I
I
ItLA
I tLC
I
I tLCK
I tLDR
ItLDW
ItLL
ItLRY
I tRAE
I
I tRD
ITM:8085AHPITM:8085AHP-2IUnit~
Parameter
I
I CLK C~cle Period
I
I CLK Low Time - Standard 150pF Loading I
- Lightl~ Loaded [ 2]
I
I
ICLK High Time- Standard 150pF Loading I
- Lightl~ Loaded [2]
I
I
I CLK Rise and Fa 11 Time
I
IXI Rising to CLK Rising
I
IXI Rising to CLK Falling
I
IA8-15 Valid to Leading Edge of Control I
[l] I
I
IAO-7 Valid to Leading of Control
I
lAO-IS Valid to Valid Data In
I
IAddress Float after Leading Edge of
I
I READ (INT)
I
IA8-15 Valid before Trailing Edge of
I
IALE[ 1]
I
IAO-7 Valid before Trailing Edge of ALE I
IREADY Valid from Address Valid
I
IAddress (A8-15) Valid after Control
I
I~idth of Control Low (RD,WR,IKTA)
I
lEdge of ALE
I
ITrailing Edge of Control to Leading
I
I Edge of ALE
I
IData Valid to Trailing Edge of WRITE I
IHLDA to Bus Enable
I
IBus Float after HLDA
I
IHLDA Valid to Trailing Edge of CLK
I
I HOLD Hold Time
I
IHOLD Setup Time to Trailing Edge of
I
I CLK
I
IINTR Hold Time
I
IINTR, RST and TRAP Setup Time to
I
I Falling
I
I Edge of CLK
I
IAddress Hold Time after ALE
I
ITrailing Edge of ALE to Leading Edge I
lof Control
I
I ALE Low during CLK High
I
I ALE to Valid Data durin Read
I
ALE to Valid Data during Write
IALE Width
IALE to READY Stable
ITrailing Edge of READ to Re-Enabling
lof Address
1READ (or INTA) to Valid Data
-332-
Mln.IMax. I Mln. I Max.1
320 120001 200 I 20001 ns
40 I
80 I
I
I ns
100 I
50 I
I
I ns
120 I
70 I
ns
I
150 I
ns
80 I
I
30
ns
I
I 301
30 I 1201
30 I 100
ns
30 I 110
ns
30 I 1501
ns
270 I
I 115 I
I
I
I
ns
240 I
I 115 I
ns
I 350
I 5751
0
ns
01
I
I
I
I
I
50 I
ns
115 I
I
I
I
I
50 I
90 I
I
I ns
I 1001 ns
I 2201
60 I
120 I
I
I ns
400 I
I 230 I
I ns
I
I
I
I
50 I
25 I
I
I ns
I
I
I
I
420 I
I 230 I
I ns
I 2101
I 1501 ns
I 1501 ns
I 2101
110 I
40 I
I
I ns
0 I
0 I
I
I ns
170 I
I 120 I
I ns
I
I
I
I
0 I
0 I
I
I ns
160 I
I 150 I
I ns
I
I
I
I
I
I
I
I
100 I
50 I
I ns
I
130 I
60 I
I ns
I
I
I
I
I
100 I
50 I
I ns
I
I 4601
I 270 I ns
200
ns
I 120
80 I
I
I ns
110 I
301 ns
I
150
90 I
I ns
I
I
I
I
3001
1 1501 ns
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
II Symbol II
I tRY
I
ItRDH
I tRYH
I tRYS
I
ItWD
\
ItWDL
TMP8085HP/TMP8085AHP-2
ITMP808SAHPITMP8085AHP-21
Parameter
I Control Trailing Edge of Leading
lEd e of Next Control
Data Hold Time After READ INTA
IREADY Hold Time
I READY Setup Time to Leading Edge of
I CLK
IOata Valid After Trailing Edge of
IWRITE
ILEADING Edge of WRITE to Data Val~d
Test conditions
TMP808SAP
TMP808SAP-2
.
I Min.IMax.1 Min. I Max.I Unas
I 400 I
I 220 I
I ns
I
I
I
I
I
0 I
I ns
I
0 I
I
I
0 I
I
0 I
I ns
11 0
100
ns
I
I
I
I
I
ns
60
100
40
20
ns
CL=lSOpF
tCYC
tCYC
320ns
200ns
Notes: 1. AS-IS address specs apply to 101M, SO and S1 except AS-IS are
undifiend during T4 - T6 of Cycle whereas 101M, SO, and Sl are
stable.
2. Loading equivalent to SOpF + 1 TTL input.
3. All timings are measured at output voltage
VL=0.8V, VH=2.0V
4. To calculate timing specifications at other value
Table 4.
-333-
of tCYC use
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
Table 4.
TMP8085HP/TMP8085AHP-2
Bus Timing Specification as a TCYC Dependent
tAL
( 1/2) T-45
tLA
0/2) T-60
tLL
(1/2) T-20
tLCK
(1/2) T-60
tLC
( 1/2) T-30
tAD
(5/2+N) T-225
tRD
(3/2+N) T-180
tRAE
( 1/2) T-10
tCA
(1/2) T-40
tDW
(3/2+N) T-60
t"ll'D
0/2) T-60
tCC
(3/2+N) T-80
tCL
(1/2) T-ll0
tARY
(3/2) T-260
tRACK
0/2) T-50
tRABF
( 1/2) T+50
tRABE
0/2) T+50
tAC
(2/2) T-50
tL
0/2) T-80
tR
( 1/2) T-40
tRY
( 3/2) T-80
tLDR
(4/2) T-180
I
I MIN
I
I MIN
I
1 MIN
I
I MIN
I
I MIN
I
I MAX
I
I MAX
I
I MIN
I
I MIN
I
I MIN
I
I MIN
I
I MIN
I
I MIN
I
I MAX
I
I MIN
I
I MAX
I
I MAX
I
I MIN
I
I MIN
I
I MIN
I
I MIN
I
I MAX
Note: N is equal to the total WAIT states.
T=tCYC
-334-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8085HP/TMP8085AHP-2
Xl INPUT
CLK OUTPUT
tXKR
1I_ _ _ _t_L_--i t
tXKF
cye
CLOCK TIMING WAVEFORM
CLK
tLCK
t
=>
I
ADDRESS, STATUS
tAD
=>-
tLL
ADDRESS
tLA
tAL
tLC
I
ALE
tCA
r-==-
tAC
tRAE
- -----<=
r>-- -
)< DATA IN
~tRDH
tLDR
fo--tAFR
tRD
II
tCL
.J'-
tcc
Ji
READ OPERATION
CLK
T1
I
T2
I
T3
I
I
\"-_.....Ir------.\~_--'I,-----,\'- __Ir---\'_ __
=><
=><
ADDRESS, STATUS
J
)<
ADDRESS
DATA
tDW
tLDW
OUT
L
\
tLC
tAC
tcc
.~
WRITE OPERATION
-335-
J
tWD
tWDL
ALE
J
tCA
tCL
J
TOSHIBA INTEGRATED CIRCUIT
TMP8085HP/TMP8085AHp·2
TECHNICAL DATA
T2
Tl
TWAIT
T3
Tl
eLK
AS'\.. A15
50S1 1O/i1
---<
ADO'\.. AD7
tRDH
tLDR
ALE
tRD
tCC
RD/INTA
tARY
~--"'-"'-'--+---+-; t
RYH
1~---~r5------------------
READY - - - - - - - " \ 1
READ OPERATION WITH WAIT CYCLE (TYPICAL)
- SAME READY TIMING APPLIES TO WRITE OPERATION
I T4'\..THOLD I
THOLD
I
THOLD
I
Tl
eLK
INTR
_
HOLD
HLDA
___~ ~
_ _________________
t_HD_S-J.t=~~t~H~D~H-+
.... _./
\~._ _ _ _ _ _ _ _ __
HABE
-----::~~~~============t~H~A~C~K~==~-tHABF
AS'\..A1S
ADDRESS
---H---------,'-__
_
IO/i1
,
ADO'\.. 7
XADDRESS }-.--....(CALL lNs'lr-'-- -11-----------'
INTERRUPT AND HOLD TIMING
-336-
TOSHIBA INTEGRATED CIRCUIT
TMP8085HPnMP8085AHP-2
TECHNICAL DATA
.llitLmm
21
40
20
--
z
~
__________~5~1.~3~1~fA~X~·______________~
4-~r----------------------------------i
z
05 ± 0.15
~
d
2.54 ±0.25
1.4 ± 0.15
Note: Each lead pitch is 2.54mm, and all the leads are located within +0.25
mm from their theoretical positions with respect to No.1 and No.40
leads.
-337-
TOSHIBA INTEGRATED CIRCUIT
TMP8155PflMP8155P-2
TMP8156PflMP8156P-2
TECHNICAL DATA
2048 BIT STATIC ms RAt~ WITH I/O PORTS AND TIMER
GENERAL DESCRIPTION
The TMP 8l55P/8l56P are RAM including I/O ports and counter/timer on the chip
for using in the TLCS-85A microcomputer system. The RAM portion is designed
with 2K bit static cells organized as 256 x 8. The 14 bit programmable counter/
timer is the down counter. It provides either a square wave or terminal count
pulse for the cpu system depending or. tiDer mode.
The I/O portion is consists of 2 programmable 8 bit I/O ports and 1 program~
mabIe 6 bit I/O port. The programmable I/O ports can be operated by BASIC
MODE and STROBE NODE.
FEATURES
Single +5V Power Supply
Access Time: 330 ns (TMPS15S-2/TMPS156-2)
Internal Address Latch
2 Programmable S Bit I/O Ports and 1 Programmable 6 Bit I/O Port.
256 Ward x S Bits RAM
Programmable 14 Bit Binary Counter/Timer
Multiplexed Address and Data Bus
Chip Enable Active High (TMP8156P) or Low (TMP81S5P)
40 pin DIP
PIN CONNECTION (TOP VIEW)
PC3
PC"
TIMER IN
RESET
PCS
TIMER OUT
IO/M
CEOR CE
RD
WR
ALE
ADO
AD)
AD2
AD3
AD"
ADS
AD6
AD7
VSS
FIGURE
BLOCK DIAGRAM
VCC
PC 2
PC]
PCO
PB7
PB 6
PBS
PB"
PB3
PB2
PB I
PBO
PA 7
PA6
PAS TIMER
PA"
IN
PA3
PA 2
PAl
PAa
FI GURE 2
TIMER
OUT PCO-S
PB
0-7
TMP8155P/8156P FUNCTIONAL BLOCK DIAGRAM
mp8155P/8156P PINOllT DIAGRArl
-338-
TOSHIBA INTEGRATED CIRCUIT
TMP8155PITMPII55P-2
TMP8156PITMPII56P-2
TECHNICAL DATA
PIN NAMES AND PIN DESCRIPTION
RESET (INPUT)
The Reset signal is a pulse provided by the TMP8085A to initialize the
system. Input high on this line resets the chi~ and initializes the three
I/O ports to input mode. The width of RESET pulse should typically be
two TMP8085A clock cycle times.
ADO~7 (INPUT / OUTFUT, 3-STATE)
These are 3-state Address/Data lines that interface with the CPU lower
8-bit Address/Data Bus. The 8-bit address is latched into the address
latche on the falling edge of the ALE. The address can be applied to the
memory section or the I/O section depending on the polarity of the IO/M
input signal. The 8-bit data is either written into the chip or read
from the chip depending on the status of WR or RD input signal.
CE OR CE (INPUT)
Chip Enable: On the TMP8155P, this pin is CE and is ACTIVE LOW.
On the TMP8156P, this pin is CE and is ACTIVE HIGH.
RD (INPUT)
Input low on this line with the Chip Enable active enables the AD~7
buffers. If IO/M pin is low, the RAM content will be read out to the
AD bus. Otherwise the content of the selected I/O port or command/
status register will be read to the AD bus.
Input low on this line with the Chip Enable active causes the data on the
AD lines to be written to the RAM or I/O ports and command/status register
depending on the polarity of IO/M.
ALE (INPUT)
Address Latch Enable: This control signal latches both the address on the
ADON7 lines and the state of the Chip Enable and rO/M into the chip at the
falling edge of ALE.
IO/Memory Select: This line selects the memory if low and selects the I/O
and command/status register if high.
These 8 pins are general purpose I/O pins.
by programming the Command Register.
-339-
The in/out direction is selected
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8155P/TMP8155P-2
TMP8156P/TMP8156P-2
PBO~7(INPUT/OUTPUTJ3-STATE)
These 8 pins are general purpose I/O pins.
by programming the Command Register.
The in/out direction is selected
These 6 pins can function as either input port, output port, or as control
signal for PA and PB. Programming is done through the Command Registf'r.
When PCa~s are used as control signals, they are defined the following:
PC a
-
A INTR (Port A Interrupt)
PCI - A BF (Port A Buffer Full)
PC2 - A STB (Port A Strobe)
PC) - B INTR (Port B Interrupt)
PC4 - B BF (Port B Buffer Full)
PCs - B STB (Port B Strobe)
TIMER IN (INPUT)
This is the input to the counter-timer.
TIMER OUT (OUTPUT)
This pin is the timer output. This output can be either a square wave or
a pulse depending on the timer mode.
VCC (Power)
+5 volt supply
VSS (Power)
Ground Reference
-340-
TOSHIBA INTEGRATED CIRCUIT
TMP8155P/TMP8155P-2
TMP8156P/TMP8156P-2
TECHNICAL DATA
FUNCTIONAL DESCRIPTION
PROGRAMMING OF THE COMr·1AND REGISTER
The command register consists of eitht latches. Four bits (0-3) define the
mode of the ports, two bits (~-5) enable or disable the interrupt from port
C when it acts as control port, and the last two bits (6-7) are for the timer.
The command register contents can be altered at any time by using the I/O
address XXXXOOO during a WRITE operation. The function of each bit of the
command byte is defined in FUGURE 3.
ADDRESS
I x I x I x I x I x I a Ia I a I
x =
1
AD7 AD6 AD5 AD4 AD3 AD2 AD1 ADO
COMMAND ITH21THIIIEBjIEAlpc 2 PC I PB I PA
1
REGISTER
I
L
o
I
Don't care
Logic "1"
Logic "0"
DEFINE PAO-7 }
DEFINE PBO-7
DEFINES PCO- 5
0
1
INPUT
OUTPUT
HODE
HODE
HODE
HODE
F
ENABLE PORT A
INTERRUPT
}
01
10
1
1
2
3
4
=
ENABLE
ENABLE PORT B - 0 = DISABLE
INTERRUPT
00
= NOP - DO NOT AFFECT COUNTER
OPERATION
01
= STOP -NOP IF TIHER HAS NOT STARTED;
STOP COUNTING IF THE TIMER IS RUNNING
10
L-
TIHER COMMAND
-
= STOP AFTER TC - STOP IHHEDIATELY
AFTE R PRESENT TC IS REACHED (NOP
IF TIHER HAS NOT STARTED)
11
= START - LOAD HODE AND COUNT LENGTH
AND START IHHEDIATELY AFTER
LOAD ING (IF TIMER IS NOT PRESENTLY
RUNN ING). IF TIMER IS RUNNING,START
THE NEW MODE AND COUNT 1.ENGTH
IHHE DIATELY AFTER PRESENT TC
IS REACHED.
FIGURE 3
COMr1AND REGISTER BIT
ASSIGN~lENT
-341-
TOSHIBA INTEGRATED CIRCUIT
TMP8155P/TMP8155P-2
TMP8156P/TMP8156P-2
TECHNICAL DATA
READING THE STATUS REGISTER
The status register consists of seven latches, one for each bit; six (0-5) for
the status of the ports and one (6) for the status of the timer.
The status of the timer and the I/O section can be polled by reading the Status
Register (Address XXXXXOOO). Status word format is shown in FIGURE 4.
Note that you may never write to the status register since the command register
shares the same I/O address and the command register is selected when a write
to that address is issued.
ADDRESS
x__~_x__~__x__~__x__~_x__~~O__~~O__~_O~~
L-__
STATUS
REGISTER
INTERRUPT REQUEST
PORT A BUFFER FULL/EMPTY
(INPUT/OUTPUT)
PORT A INTERRUPT ENABLE
PORT B INTERRUPT REQUEST
PORT B BUFFER FULL/EMPTY
(INPUT/OUTPUT)
PORT B INTERRUPT ENABLE
TIMER INTERRUPT (THIS BIT
IS LATCHED HIGH WHEN
TERMINAL COUNT IS
REACHED, AND IS RESET TO
Lo\~ UPON READING OF THE
CIS REGISTER AND BY HARDWARE
RESET)
FIGURE 4
STATUS REGISTER BIT ASSIGNMENT
-342-
TOSHIBA INTEGRATED CIRCUIT
TMP8155P/TMP8155P-2
TMP8156P/TMP8156P-2
TECHNICAL DATA
INPUT/OUTPUT SECTION
COMMAND/STATUS REGISTER (C/S)
Both register have the common address xxxxxOOO. When the cis registers
are selected during WRITE operation, a command is written into the cis
register. The contents of this register are not accessible through the pins.
When the CIS is selected during a READ operation, the status information of
the I/O ports and the timer becomes available on the ADO_7 lines.
PA Register - This register can be programmed to be either input or output
ports depending on the status of the contents of the CiS Register.
Also depending on the command, this port can operate in either the basic
mode or the strobed mode (See timing diagram). The I/O pins assigned in
relation to this register are PAO-7' The address of this register is
XXXXXOOI.
PB Register
This register functions the same as PA Register. The I/O
pins assigned are PBO-7' The address of this register is XXXXXOlO.
PC Register - This register has the address XXXXXOll and contains only
6-bits. The 6-bits can be programmed to be either input ports, output
ports or as control signals for PA and PB by properly programming the
AD2 and AD3 bits of the CIS register.
When PCO-5 is used as a control port, 3-bits are assigned for Port A and
3 for Port B. The first bit is an interrupt that the TMP8l55P/8156P issues.
The second is an output signal indicating whether the buffer is full
or empty, and the third is an input pin to accept a strobe for the strobed
input mode. See Table 2.
When the port C is programmed to either MODE 3 or MODE 4, the control
signals for PA and PB are initialized as follows:
MODE
~
INPUT MODE
OUTPUT MODE
INTR
SIB
Low
Low
Input Control
Low
High
Input Control
BF
-343-
TOSHIBA INTEGRATED CIRCUIT
TMP8155P/TMP8155P.2
TMP8156P/TMP8156P.2
TECHNICAL DATA
To summarize, the register's assignments are shown TABLE 1.
TABLE 1
I/O PORT ADDRESSING SCHEME
I/O ADDRESS
P HOUTS
NO. OF BITS
SELECT ION
A7 A6 AS A4 A3 AZ Al AO
X X
X
X
X
0
0
0
Internal
Con~and/Status
Register
VO
8
X X
X
X
X
0
0
1
PAO-7
General Purpose
Port A
8
X X
X
X
X
0
I
0
PllO-7
General Purpose I/O Port B
8
X X
X
X
X
0
1
1
PCO-7
General Purpose I/O Port or
6
Control
X
X
X
X
X
1
0
0
Low-Order 8 bits of Timer Count
X
X
X
X
X
I
0
I
High 6 bits/2 bits of Timer Count
TABLE
Pin
PCO
MODE 1
MODE 2
2
TABLE OF PORT CONTROL ASSIGNMENT
MODE 3
MODE 4
Output Port
A INTR (Port A Interrupt)
A INTR (Port A Interrupt)
PCI
Input Port
Input Port
Output Port
A BF (Port A Buffer Full)
A BF (Port A Buffer Full)
PCZ
Input Port
Output Port
A STB(Port A strobe)
A STB (Port A Strobe)
PC3
Input Port
Output Port
Output Port
B INTR (Port B Interrupt)
PC4
Input Port
Output Port
Output Port
B BF (Port B Buffer Full)
PCS
Input Port
Output Port
Output Port
B STB (Port B Strobe)
-344-
TOSHIBA INTEGRATED CIRCUIT
TMP8155P/TMP8155P-2
TMP8156P/TMP8156P-2
TECHNICAL DATA
TIMER SECTION
The timer is a l4-bit down-counter that counts the 'timer input' pulses and
provides either a square wave or pulse when terminal count (TC) is reached.
The timer has the I/O address XXXXXlOO for the low order byte of the register
and the I/O address XXXXXlOl for the high order byte of the register.
To program the timer, the COUNT LEN:;TH REGISTER is loaded first, one byte at a
time, by selecting the timer addresses. Bits 0-13 will specify the length of the
next count and bits 14-15 will specify the timer output mode. The value loaded
into the count length register Cdn have any value from 2H through 3FFFH in
bits 0-13.
IM2 I Ml
I
1 Tl31 T121 T11I TlO
I T9
J,
TIMER t10DE
MSB OF COUNT LENGTH
I
LSB OF COUNT LENGTH
FIGURE
5
TIMER FROMAT
-345-
T8
TOSHIBA INTEGRATED CIRCUIT
TMP8155P/TMP8155P-2
TECHNICAL DATA
TMP8156P/TMP8156P-2
There are four timer modes which are defined by M2 and MI.
M2
MI
o
o
o
-------Put out low during second half of count.
1
-------Continuous square wave; The period of the square-wave
equal s the count length programmed with automatic
reload at terminal count.
I
o
------- Single pulse upon TC being reached.
I
I
-------Continuous pulses.
Note:
In case of an odd-numbered count, the first half-cycle of the
square-wave output,which is high, is one count longer than the
second (low) half-cycle as shown in FIGURE 6.
5
4
3
2
I
5
4
3
2
I
I
5
TIMER IN
M2
MI
0
0
0
I
1
0
I
I
LJ
LJ
I
Load
Ls-
reload
FIGURE 6 ASYMMETRICAL SQUARE-WAVE OUTPUT RESULTING FROM COUNT OF 5
-346-
I
reload
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8155P/TMP8155P-2
TMP8156P/TMP8156P-2
Bits 6-7 (TM2 and TM1) of command register contents are used to start and
stop the counter. There are four commands to choose from;
TM2
TMl
o
o
o
NOP:
1
STOP: NOP if timer has not started; stop counting if the
timer is running.
1
o
STOP AFTER TC: Stop immediately after present TC is reached.
(NOP if timer has not started)
1
1
START: Load mode and count length and start immediately
after loading (if timer is not presently running).
If timer is running, start the new mode and count length
immediately after present TC is reached.
Do not affect counter operation.
Note that while the counter is counting, you may load a new count and mode
into the count length re8isters. Before the new count and mode will be used
by the counter, you must issue a START commapd to the counter. This applies
even though you may only want to change the count and use the previous mode.
The counter in the TMP8l55P/8l56P is not initialized to any particular mode
or count when hardware RESET occurs, but RESET does stop the counting.
Therefore you must issue a START command via the CIS register, because counting cannot begin following RESET.
Please note that the timer circuit on the Th!P8l55P/8l56P chip is designed
to be a square-wave timer, not an event counter. To achieve this, it counts
down by twos twice in completing one cycle. Thus, its registers do not
contain values directly representing the number of TIMER IN pulses received.
You cannot load an initial value of 1 into the count register and cause the
timer to operate, as its terminal count value is 10 (binary). After the
timer has started counting down, the values residing in the count registers
can be used to calculate the actual number of TIMER IN pulses required to
complete the timer cycle if desired. To obtain the remaining count,
perform the following operations in order:
1.
2.
3.
4.
5.
Note:
Stop the count.
Read in the 16-bit value from the count length registers.
Reset the upper two mode bits.
Reset the carry and rotate right one position all 16 bits through
carry.
If carry is set, add 1/2 of the full original count (1/2 full count-l
if full count is odd.)
If you started with an odd count and you read the count length tegister
before the third count pulse occurs, you will not be able to
discern whether one or two counts has occurred. Regardless of this.
the TMP8l55P/8l56P always counts out the right number of pulses in
generating the TIMER our waveforms.
-347-
TOSHIBA INTEGRATED CIRCUIT
TMP8155P/TMP8155P-2
TMP8156P/TMP8156p·2
TECHNICAL DATA
ABSOLUTE MAXIMUM RATINGS
Symbol
Ra t ing
Item
VIN
Vcr; Supply Voltage with Respect to VSS
Input Voltage with Pespect to VSS
Your
Output Voltage with Respect to VSS
VCC
-O.SV to +7.0V
"-
-O.SV to +7.0V
-O.SV to +7.0V
PD
Power Dissipation
1. SW
TSOLDER
Soldering Temperature (Soldering Time 10 sec.)
260°C
TSTC
Storage Temperature
TOPR
Operating Temperature
-55°C to +150°C
O°C to +70°C
D,C. CHARACTERISTICS
Symbol
Parar.leter
Test Conditions
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2rnA
VOH
Output High Voltage
IOH
IIL
Input Leakage
Output Leakage Current
2.0
VIN
=
-400\JA
VCC Supply Current
IIL(CE)
Chip Enable Leakage
8155
S156
-- -
"-
O.S
V
VCC+O.S
V
0.45
V
VIN = VCC to OV.
±l0
lJA
flO
lJA
- - - - - f------
0.45V ~ VOUT ~ VCC
-348-
Units
V
'ICC to OV
~------~~-
Nax.
2.4
._-----
ICC
Typ.
-0.5
t-----"
lLO
Min.
"-"--~
rISO
rnA
+100
-100
lJA
lJA
TOSHIBA INTEGRATED CIRCUIT
TMP8155P/TMP8155P-2
TMP8156P/TMP8156P-2
TECHNICAL DATA
A.C. CHARACTERISTICS
TA~O°C
Symbol
to +70°C,
VcC~+5V±5%
Test
Condition
Parameters
tAL
Address to Latch Setup Time
tLA
tLC
Address Hold Time after Latch
Latch to READ/WRITE Control
Valid Data out Delay trom Kl::AU
Control
Address Stable to Data Out Valid
Latch Enable Width
tRD
tAD
tLL
tRDF
TmS155P/56P TMPS155P-2/56P-2
Min.
50
Max.
SO
100
0
Units
Max.
ns
30
40
ns
ns
170
140
ns
400
330
ns
ns
SO
ns
100
Data Bus Float after READ
Min.
30
70
100
0
teL
tcc
READ/WRITE Control Latch Enable
READ/WRITE Control Width
20
250
10
200
ns
ns
tDW
two
Data In to WRITE Setup Time
Data in Hold Time After WRITE
150
100
ns
0
25
ns
tRV
twp
Recovery Time Between Controls
WRITE to Port Output
300
tpR
tRP
Port Input Setup Time
70
50
Port Input Hold Time
50
10
tSBF
Strobe to Buffer Full
tss
tRBE
tSI
tRDI
tpss
tpHS
200
400
l50pF Load
400
Strobe \.Jid th
200
READ to Buffer Empty
Strobe to INTR On
READ to INTR Off
Port Setup Time to Strobe
50
ns
300
ns
300
300
300
ns
ns
ns
ns
20
100
120
ns
ns
150
400
400
400
Port Hold Time After Strobe
ns
300
ns
ns
tSBE
Strobe to Buffer Empty
400
300
ns
tWBF
WRITE to Buffer Full
400
300
ns
tWI
WRITE to INTR Off
TIMER-IN to TIMER-OUT Low
400
400
300
300
ns
ns
300
tTL
tTH
tRDE
tL
tH
TIMER-IN to TIMER-OUT High
Data Bus Enable from READ Control
TIMER-IN Low Time
TIMER-IN High Time
-349-
10
10
ns
ns
SO
120
40
70
ns
ns
400
TOSHIBA INTEGRATED CIRCUIT
TMP8155P/TMP8155p·2
TMP8156P/TMP8156p·2
TECHNICAL DATA
TIMING WAVEFORMS
A.
READ CYCLE
or CE(8155)
CE(8156)
1O/M
VALID
DATA
------<'-----
ALE
tcc
B.
or
WRITE CYCLE
~~~~~;~~
10/M
VALID DATA
ADO-7
tDW
ALE
FIGURE 7 READ/WRITE TIMING DIAGRAMS
-350-
INTEGRATED CIRCUIT
TOSHIBA
A.
TECHNICAL DATA
BASIC INPUT MODE
RD
PORT
ADO_7
B.
BASIC OUTPUT MODE
WR
ADO_7 - - - - - '
'---~:::=: "--+----
PORT
FIGURE 8 BASIC liD TIMING WAVEFORM
-351-
TMP8155PJTMP8155P.2
TMP8156PJTMP8156P.2
TOSHIBA INTEGRATED CIRCUIT
TMP8155P/TMP8155P-2
TMP8156P/TMP8156P-2
TECHNICAL DATA
A.
STROBED INPUT MODE
\
J
BF
STROBE
-
I
n:-- tSI
\
~
INTR
tSBF
r-- tRBE_
tss -
.Ii
RD
I
\
tpss
INPUT DATA
FROM PORT
B.
~
tRDI
J
tpHS
~
]X
STROBED OUTPUT MODE
BF
\~
J
tSBE
J
tWBF
I-
tSI
~
INTR
tWI
;r
J
\
/
OUTPUT DATA
TO PORT
twp
><
FIGURE
9 STROBED
1/0 TIMING WAVEFORM
-352-
TOSHIBA INTEGRATED CIRCUIT
TMP8155P/TMP8155P-2
TMP8156P/TMP8156P-2
TECHNICAL DATA
LOAD COUNTER FROM CLR ~
I
2
I
1
RELOAD COUNTER FROM
I
tr
I
CLR~
I
TIMER IN
TIMER OUT
(PULSE)
(Note
1),
__ J
\~
TIMER OUT
(SQUARE WAVE)
Note 1:
\
(Note 1)
'-- -------'
I
The timer output is periodic
if in an automatic
reload mode (Ml Mode Bit = 1)
FIGURE
10
TIMER OUTPUT WAVEFORM COUNTDOWN FROM
-353-
5 TO 1
TOSHIBA INTEGRATED CIRCUIT
TMP8155PflMP8155P-2
TMP8156PflMP8156P-2
TECHNICAL DATA
OUTLINE DRAIHNG
1
2
3
4
!:J
b
Uni t in mrn
7
8
~
10
11 ]213 14
l!) Jb 17 18
l~
~
(Note 1)
M
o 25± 0 1
1500-1780
O~±Ol
Note: 1.
2.
This dimension is measured at the center of bending point of leads.
Each lead pitch is 2.54mm, and all the leads are located within
±O.25mm from their theoritical positions with respect to No.1 and
No.40 leads.
-354-
TOSHIBA INTEGRATED CIRCUIT
TMP8355P
TECHNICAL DATA
16,384 BIT ROM WITH I/O PORTS
GENERAL DESCRIPTION
The THPD355P is a ROH and I/O chip to be used in the TLCS-05A microcomputer
system. The ROM portion is organized as 2,048 words by 8 bits.
The I/O portion consists of 2 general purpose I/O ports. Each I/O port has
8 port lines, and each I/O port line is individually programmable as input
or output.
FEATURES
2048 words x 8 bits ROM
Single + 5V Power Supply
Internal Address Latch
2 General Purpose 8-Bit I/O Ports
Access Time: 400 ns (MAX.)
Each I/O Port Line Individually Programmable as Input or Output
Multiplexed Address and Data Bus
40 pin DIP
Compatible with Inptel's 8355
PIN CONNECTIONS (TOP VIEW)
BLOCK DIAGRAM
10m
ALE
CEI
CE 2
CLK
RESET
NC
READY
101M
lOR
RD
!OW
ALE
ADo
ADI
ADz
AD3
A~
ADS
A~
AD]
vss
FIGIIRE
VCC
PB 7
CLK
PB6
PBS READY
PB4
PB)
PB2
PBI
PBo
PA7
PA6
PAS
PA4
PA3
PA2
PAl
PAa
AlO
A9
TOR
RD
lOW
RESET
ADD - 7
______ 8_______ -,
I
"""";'--"---L--L-J--L--L--L.--'--,
Control circuit
Address Latch Decoder 8
I
I
I
I
I
I
I
r--
I
I
I
I
2K
I
I
I
x 8 Bit
1
ROM
I
8
: PA O- 7
I
iI 8
I
I
I
I
I
I
I
I
DDR
I
I
IL _____________________________
8
I
~
AS
TMP8355P PINOUT DIAGRAM
VCC
l..- VSS
I
I
I
FI GURE 2 TMP8355P FUNCTIONAL BLOCK 01 AGRAM
-355-
PBO- 7
TOSHIBA INTEGRATED CIRCUIT
TMP8355P
TECHNICAL DATA
PIN NAMES AND PIN DESCRIPTION
ALE (INPUT)
When Address Latch Enable goes high, ADO--7' IO/TI, A8-l0' CE2, and CEI, enter the
address latches. The signals (ADO-7, loin, A8-10' CE2, CEI) are latched in at
the trailing edge of ALE.
ADO-7 (INPUT/OUTPUT, 3-STATE)
Bi-directional Address/Data bus_ The lower 8-bits of the ROM or I/O address are
applied to the bus lines when ALE is high. During an I/O cycle, Port A or Bare
selected based on the latched value of ADO' If RU or lOR is low when the latched
Chip Enables are active, the output buffers present data on the bus.
AS-10 (INPUT)
These are the high order bits of the ROM address.
operations_
They do not affect I/O
CEll CE2 (INPUT)
CHIP ENABLE INPUTS:ITI is active low and CE 2 is active high.
must be active to permit accessing the ROM.
Both chip enables
IO/M (INPUT)
If the latched lo/R is high when RD is low, the output data comes from an I/O port.
If it is low the output data comes from the ROM_
RD (INPUT)
If the latched Chip Enables are active when 1lil goes low, the ADO_7 output buffers
are enabled and output either the selected ROM location or I/O port.
When both RD and lOR are high, the ADO_7 output buffers are 3-stated.
lOW (INPUT)
row causes the output port pointed
to by the latched value of ADO to be written with the data on AD O_ 7 '
The state of IO/R is ignored.
If the latched Chip Enables are active, a Iowan
ClK (INPUT)
The ClK is used to force the READY into its high
by eEl lOW, CE2 high, and ALE high_
-356-
st~te
after it has been forced low
TOSHIBA INTEGRATED CIRCUIT
TMP8355P
TECHNICAL DATA
READY (OUTPUT, 3-STATE)
READY is a 3-state output controlled by CEl. CE 2 , ALE and CLK.
READY is forced low when the Chip Enables are ac>ive during the time ALE is high,
and remains low until the rising edge of the next CLK.
PAO - PA7 (INPUT/OUTPUT, 3-STATE)
These are general purpose I/O pins. Their input/output direction is determined by
the contents of Data Direction Register (DDR). Port A is selected for write
operations \"hen the Chip Enables are active, and lOW is low and a 0 was previously
latched from ADO'
Read operatiun is selected by either lOR low, active Chip Enables and ADO low,
or 10{H high, RD low, active Chip Enables, and ADO low.
PBo - PB7 (INPUT/OUTPUT, 3-STATE)
This general purpose I/O port is identical to Port A except that it is selected by
1 latched from ADO'
d
RESET (INPUT)
In normal operation,an input high on RESET causes all pins in Ports A and B to
assume input mode (clear DDR register).
lOR (INPUT)
When theChip Enables are active, a low on ~ will output the selected I/O port
onto the AD bus. lOR low performs the same function as the combination of 10/R
high and RI) low. l-lhen lOR is not used in a system, lOR should be tied to VCC "1".
Vee (POWER)
+S volt supply.
VSS (POWER)
Ground Reference
-357-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8355P
FUNCTIONAL DESCRIPTION
ROM SECTION
The TMP8355P contains an 8-bit address latch which allows it to interface
cirectly to TLCS-8SA microcomputer system without additional hardware.
The ROM portion of the chip is addressed by the II-bit address (A8-10, ADO-7)
and CEo
The address, IO/M, CE2 and CEl are latched into the address latches
on falling edge of ALE.
If the Chip Enables (CE 2 and CE l ) are active and
IO/M is low when RD goes low, the contents of the ROM location addressed by
the latched address are put out on the ADO-7 lines.
I/O SECTION
The I/O port portion consits of two B-bit I/O ports and two 8-bit Data
Direction Registers (DDR).
The I/O portion of the chip is addressed by the
latched value of ADO and ADI'
Contents of Port A and Port B can be read and
written, but the contents of DDR's cannot be read.
The contents of the
selected I/O port can be read out when the latched Chip Enable are active and
either RD goes low with 1O/M high, or lOR goes low.
The two 8-bit DDR's (DDRA and DDRB) are used to determine the input/output
status of each pin in the corresponding port.
A '0' specifies an input mode and a 'I' specifies an output mode.
The two 8-bit DDR's are cleared by RESET signal.
The table 1 summarize Port
and DDR designation.
TABLE 1, SELECTION OF PORT AND DDR DESIr,NATION
Selection
ADI
ADO
0
0
Port A
0
1
Port B
1
0
Port A Data Direction Register (DDR A)
1
1
Port B Data Direction Register (DDR B)
-358-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8355P
ABSOLUTE MAXIMUM RATINGS
Symbol
Item
Rating
VCC
VCC Supply Voltage with Respect to VSS
-O.SV to 7.0V
VIN
Input Voltage with Respect to VSS
-O.5v to 7.0v
VOUT
Output Voltage with Respect to VSS
-O.SV to 7.0V
PD
Power Dissipation
TSOLDER
TSTG
TOPR
260°C
-55°C to+150°C,
Storage Temperature
Operating Temperature
D.C. CHARACTERISTICS
TA = O°C to 70°C, Vcc
Symbol
1. 5W
Soldering Temperature (Soldering Time lOsec.)
Parameter
VIL
Input Low Voltage
0°Cto+70°C
5V + 5%
Test Conditions
Min.
-0.5
VIH
Input High Voltage
VOL
VOH
Output Low Voltage
IOL = 2rnA
Output High Voltage
IOH = -400lJA
IlL
Input Leakage Current
VIN
lLO
Output Leakage Current
0.45
ICC
VCC Supply Current
2.0
-359-
c
Typ.
Max.
Units
0.8
V
V
VCC+ 0 . 5
0.45
2.4
V
V
VCC to OV
+ 10
-
lJA
~Vout ~VCC
:!: 10
lJA
180
rnA
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8355P
A.C. CHARACTERISTICS
5V + 5%
Symbol
Test
Conditions
Parameter
Min.
Typ.
Max.
Units
tCYC
Clock Cycle Time
tL
CLK Low l.Jidth
tH
CLK High Hidth
tr,tf
CLK Rise and Fall Time
tAL
Address to Latch Set Up Time
50
ns
tLA
Address Hold Time after Latch
80
ns
t LC
Latch to READ/HRITE Control
100
ns
tRD
Valid Data Out Delay from
320
ns
80
ns
120
ns
--
30
1S0pF
ns
170
ns
400
ns
READ Control
tAD
Address Stable to Data Out Valid
tLL
Latch Enable Width
Load
tRDF
Data Bus Float after READ
tCL
READ/I'JR ITE Control to Latch Enable
tcc
READ/WRITE Control Width
250
ns
tDW
Data In to HRITE Set Up Time
150
ns
tWD
twp
Data In Hold Time after WRITE
10
WRITE to Port Output
tpR
Port Input Set Up Time
50
tRP
t RYH
Port Input Hold Time
50
tARY
ADDRESS (CE) to READY
tRV
Recovery Time between Controls
tRDE
Data Out Delay from READ Controls
tLCK
ALE Lov during CLK High
100
ns
0
20
100
ns
i
ns
400
READY Hold Time
0
-360-
ns
ns
ns
ns
160
ns
160
ns
--
300
ns
10
ns
100
ns
TOSHIBA INTEGRATED CIRCUIT
TIP8355P
TECHNICAL DATA
TIMING WAVEFORMS
AS-10. 10/M
,
-.l
ADDRESS
ADO_7
=>
\
1\
--1
ALE
ADDRESS
K
tAL
-<
tLL ~
ADD ~ESS
tAD
~~--f.2
tRDF .-t--IDATA
~-
-<
ADDRESS
tRDE
~D
tRD
ADO_7
lOW
=>
ADD ~ESS
K
)
DATA
tDW
t ex
ADDRESS
tCL
f---'=-
tcc
FIGURE 3
PROM READ, 1/0 READ, AND WRITE TIMING
H
-
\
II
TL
I- tr
tCYC
FIGURE 4
CLOCK SPECIFICATION FOR TMP8355P
-361-
j---
TOSHIBA INTEGRATED CIRCUIT
TMP8355P
TECHNICAL DATA
eLK
ADO_7. AS-iO
101M
ALE
READY
FIGURE 5
WAIT STATE TIMING (READY::; 0)
A. I NPUT MODE
tPR
PORT INPUT
ADO __ 7
B. OUTPUT MODE
PORT OUTPUT
ADO-7
FIGURE 6
1/0 PORT TIMING
-362-
TOSHIBA INTEGRATED CIRCUIT
TMP8355P
TECHNICAL DATA
PROGRAM TAPE FORMAT
TMP83SSP programs are delivered in the form of punched paper tape or the
87SSA from which to copy. In case of the 87SSA. Toshiba needs two pieces.
(l)
Tape Forma t
f!r )
L•• d.r. 50 "NULL"
I
Comments
(CR)
(Lf)
'hm""'"
or
~r.
Comment (Record mark ":" is not included) )
Option
- - - - - Record Mark
Record Length (2 hexadecimal digits)
Loading Address (4 hexadecimal digits)
Record Type (2 Digits)
"00"
"01"
Normal Record
End of File Record
Data
Check Sum (2 hexadecimal digits)
(CR)
(LF)
:
Dummy characters (RUBOtIT. BLANK) before and after n(CR) (LF)" are
optional.
------ Record Mark (Repeated below)
P&=f
W
]Tr.. ,.r. 50 "NULL" characters or more
(2) Example of Tape List
TOSHIBA MICRO COMPtITER TLCS-84
:10000000066SC7D79CFSOF3F9SlFED5SA8FF16ES70
:1000100088884DDE67D3lFSD8ABA6DF292Fl13F5Cl
:100020004FFlFBSDFFDAA96A99CF7DF94A346B7C09
:100030001973S2F729F12F79AA9COS7CSB8S1EED77
:1003CO005DFDBSE556A67277F6lASlC63lCF9FOE80
:1003DOOOBD2F6F20E8BB1977E3FB5ADlF41FDAA7E2
:1003EOOOBS3D42EOEC32546025B7308CDD52063DID
:1003FOOOB4BE9E9E345B6l38060B20VC372BF60BD6
:OOOOOOOlFF
-363-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8355P
OUTLINE DRAWING
Unit in mm
--+---++1---It]
1
2
3
4
:,
ti
7
8
\) 10 II 1:< 13 14 1b 1b 17 11:< 1" :.iJ
....
'"
(Note 1)
o
+I
'"..,
CD
025TYF
05±Ol
Note: 1.
2.
This dimension is measured at the center of bendinp point of leads.
Each lead pitch is 2.54mm, and all the leads are located within
!O.25mm from their theoritical positions with respect to No.1 and
No.40 leads.
-364-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP82C51 AP-2/TMPB2C51 AF-2
TMPB2C51 AP-B/TMPB2C51 AF-B
PROGRAMMABLE COMMUNICATION INTERFACE
TMP82CSIAP-2/TMP82CSIAF-2
TMP82C51AP-8/TMP82CSIAF-8
GENERAL DESCRIPTION
The TMP82C51A is the industry standard Universal Synchronous/Asynchronous
Receiver/Transmitter (USART) that is fabricated using C-MOS silicon gate
technology.
The 82C51A is mainly used for 8-bit microcomputer extension system, which require serial data communications.
The TMP82CSIAP-2/TMP82C51AP-2 is packaged in the 28 pin standard Dual Inline
Package.
The TMP82C51AF-2/TMP82C51AF-8 is packaged in the 44 pin Flat Package.
FEATURES
Synchronous and Asynchronous Operation
- Synchronous:
5-8 Bit Characters
Internal or External Character Synchronization
Single or Double Character Synchronization (Internal)
Automatic Sync Insertion
- Asynchronous:
5-8 Bit Characters
Clock Rate - 1, 16 or 64 Times Baud Rate
Break Character Generation
1, 1.5 or 2 stop Bits
False Start Bit Detection
Automatic Break Detect and Handling
Baud Rate
TMP82CSIAP-2
DC-I04K Baud
TMP82C51AP-8
DC-240k Baud
Full-Duplex, Double-Buffered, Transmitter and Receiver
Error Detection-Parity, Overrun and Framing
Single +SV Supply : 5V + 10%
-365-
TOSHIBA
INTEGRATED CIRCUIT
TM P82 C51 AP.2/TM P82 C51 AF-2
TECHNICAL DATA
TMP82C51 AP-8/TMP82C51 AF-8
PIN CONNECTIONS (TOP View)
D~
PI
1J:\
1\}
1"";",_c>cr,«:>_~>I')_r";I
1f")1'":Ir':>1"";\","C"YN"'r, C
D.
DTH
Db
RTS
Do
DSli
D'I
RESET
T>:'c
cio
liD
31
22
Dj
3;
21
20
R,D
36
37
36
19
18
VSS (GNO)
D3
D2
lC~
•
D1
eLK
WI{
TxD
CO
TxEMPTY
RD
SYNDET,/BD
CTS
RxRDY
TxRDY
*
BLOCK DIAGRAM
Pin 17 and Pin 39 must be connected to Vec
or mus t be open.
NC: No connection
TxD
DO
Dl
D,
TxRDY
Dc
TxEMPTY
D. Dt
D6
D7
RECEIVE
BUFFER
( F~- S )
RESET--+-------;
CLK
c/ii -+-----;
Ri5 -+----<1
GND
CO}oTROL
CONTROL
LOuIC
WR-t----oq
Os -+----oQ
vee
RECEIVE
-+-----; READ/WRITE
1<;======>1
INTERNAL
DJ.TA BU~
-366-
MODEM
RxD
RxRDY
SYNDET/llD
RxC
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP82C51AP-2/TMP82C51AF-2
TMP82C51 AP-8/TMP82C51AF-8
PIN NAMES AND PIN DESCRIPTIONS
• Interface Signals to CPU (Main System)
DO - D7 (Input/Output)
This 3-state, bidirectional, 8-bit buffer is used to interface the 82C51A to
the system Data Bus. Data is transmitted or received through the buffer upon
execution of Input or Output Instructions of the CPU. Control Words, Command
Words an9 Status Information are also transferred through the Data Bus Buffer.
WR (Input)
A "low" level signal on this input informs the 82C51A that the CPU is Writing
Data or Control Words to the 82C51A.
RD (Input)
A "low" level signal on this input informs the 82C51A that the CPU is Reading
Data or Status Information from the 82C51A.
CS (Input)
A "low" level signal on this input selects the 82C51A. No.-!.eading or writing
operation will occur unless the device is selected. When CS is "high" the
Data Bus is in the floating state and RD and WR have no effect on the chip.
cln
(Input)
This input signal, in conjunction with the WR and RD inputs, informs the
82C51A that the word on the Data Bus is either a Data Character, Control Word
or Status Information. A "high" level signal means Control or Status, a "low"
level signal means Data.
C/i)
0
0
1
x
x
RD
0
1
0
1
x
WR
1
0
1
1
x
CS
0
0
0
0
1
82C51A Receive DATA Buffer --) DATA Bus
82C51A Transmit DATA Buffer <-- DATA Bus
82C51A Status DATA Buffer - - ) DATA Bus
DATA Bus is in floating state.
DATA Bus is in floating state.
CLK (Input)
The CLK input is used to generate internal device timing. No external input
or output is referenced to CLK, but the frequency of CLK must be greater than
30 times the Receiver or Transmitter Data Bit Rates (RxC or TxC) in Synchronous Operatio~and greater than 4.5 times the Receiver Data Bit Rates (RxC or
Transmitter, TxC) in Asynchronous operation.
-367-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP82C51AP-2/TMPB2C51AF-2
TMP82C51 AP-B/TMP82C51 AF-B
RESET (Input)
A "high" level signal on this input forces the 82CS1A into an "Idle" mode.
The device will remain at "Idle" until a new set of Control Words is written
into the 82CS1A to program its functional definition. Minimum RESET pulse
width is 6 tcy •
• MODEM Control Signals
DSR (Input)
The DSR input signal is a general purpose, I-bit inverting input port. Its
condition can be tested by the CPU using a Status Read Operation. The DSR
input is normally used to test MODEM conditions such as Data Set Ready signal.
DTR (Output)
The DTR output signal is a general purpose, I-bit inverting output port. It
can be set "low" by programming the appropriate bit in the Command Instruction
Word. The DTR output signal is normally used for MODEM control such as Data
Terminal Ready or Rate Select signal.
RTS (Output)
The RTS output signal is a general purpose, I-bit inverting output port. It
can be set "low" by programming the appropriate bit in the Command Instruction
Word. The RTS output signal is normally used for MOD&~ control such as Request to Send signal.
CTS (Input)
A "low" level signal on this input enables the 82CSIA to transmit serial data,
if the Tx Enable Bit in the Command~te is set to a "one" (TxEN=l). If
either a Tx Enable off (TxEN=O) or CTS off (CTS=I) condition occurs while the
Tx is in operation, the Tx will transmit all the data in the USART, written
prior to Tx Disable Command before shutting down •
• Transmit Control Signals
TxC (Input)
The transmitter Clock controls the rate at which the character is to be
transmitted. In the Synchronous Transmission Mode, the Baud Rate (Ix) is
equal to the TxC frequency. In Asynchronous Transmission Mode the baud rate
is a fraction of the actual TxC frequency. A portion of the Mode Instruction
selects this factor; it can be 1, 1/16 or 1/64 the TxC.
For Example:
If Baud Rate equals 110 Baud,
(Ix)
TxC
110 Hz
TxC
1. 76 kHz (I6x)
TxC = 7.04 Hz (64x)
-368-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP82 C51 AP-2/TMP82C51 AF-2
TMP82C51 AP-8/TMP82C51 AF-8
The falling edge of TxC shifts the serial data out of the 82C5lA.
TxD (Output)
This line is used to transmit the serial data.
Serial output data on TxD is
changed from parallel data to serial data in accordance with the TxD line will
be held in the marking state ('1' level) immediately on one of the followings.
Master Reset
CTS signal is high (CTS=l)
Tx Disable (TxEN=O)
TxEMPTY signal is high (TxEMPTY=I)
TxRDY (Output)
This output informs the CPU that the transmitter is ready to accept a Data
Character. The TxRDY output pin can be used as an interrupt to the system,
since it is masked by Tx Disable (TxEN=O), or, for polled Operation, the CPU
can check TxRDY using a Sttus Read Operation, TxRDY is automatically reset by
the trailing edge of WR when a Data Character is loaded from the CPU. The
TxRDY pin output status (TxRDY (pin» is different from the TxRDY status bit
status register (TxRDY (status bit» as follows.
TxRDY (status bit) = (Transmit Data Buffer Empty)
TxRDY (pin) = (Transmit Data Buffer Empty) AND (CTS=O) AND (TxEN=l)
TxEMPTY (Output)
The TxEMPTY output will go "high" when the 82C51A has no characters to send.
It resets upon receiving a character from the CPU if the transmitter is
enabled.
In Synchronous Mode, a "high" level signal on this output indicates that a
Character has not been loaded and the SYNC Character or Characters are about
to be or are being transmitted automatically as "fillers". TxEMPTY does not
go "low" when the SYNC characters are being shifted out.
• Receive Control Signals
RxC (Input)
The Receiver Clock controls the rate at which the character i~ to be received.
In Synchronous Mode, the Baud Rate (Ix) is equal to the actual frequency
of RxC.
In Asynchronous Mode, the Baud Rate is a fraction of the actual RxC
frequency. A portion of the Mode Instruction selects this factor; 1, 1/16 or
1/64 the RxC.
For Example:
~Baud
RxC
RxC
RxC
Rate equals 2400 Baud,
2.4 kHz Ox)
38.4 kHz (l6x)
l53.6kHz (64x)
Data is sampled into the 82CSlA on the rising edge of RxC.
-369-
TOSHIBA INTEGRATED CIRCUIT
TMP82C51AP-2/TMP82C51AF-2
TMP82C51 AP-8/TMP82C51 AF-8
TECHNICAL DATA
RxD (Input)
This line is used to receive the serial data. Serial input data on this line
is changed to parallel data in accordance with the format specified by the
Control Words, and then transfered to the Receive Data Buffer.
RxRDY (Output)
This output indicates that the 82C51A contains a Data Character that is ready
to be input to the CPU. RxRDY can be connected to the interrupt structure of
the CPU, or, for Polled Operation, the CPU can check the condition of RxRDY
using a Status Read Operation.
Rx Enable off both masks and holds RxRDY in the Reset Condition.
SYNDET/BD (Input/Output)
This pin is used for SYNDET in Synchronous Mode and may be used as either
input or output, programmable through the Control Word. It is reset to output
mode "low" upon RESET. When used as an Output (Internal Sync Mode), the
SYNDET pin will go "high" to indicate that the 82C51A has located the SYNC
Character in the Receive Mode. If the 82C51A is programmed to use Double Sync
Characters then S'YDET will go "high" in the middle of the last bit of the
second SYNC Character. SYNDET is automatically reset upon a Status Read
Operation. When used as an Input (External Sync Mode), a positive going
signal will cause the 82C51A to start assembling Data Characters on the rising
edge of the next RxC.
In Asynchronous Mode this pin is used for BD.
This output will go "high" whenever the receiver remains "low" through two
consecutive Stop Bit Sequences (including the Start Bits, Data Bits, and
parity bits). Break Detect may also be read as a Status Bit.
It is reset only upon a Master Chip Reset or Rx Data returning to a "one"
state.
Power Supply
VCC (power)
+5 Volt supply
GND (Power)
o Volt supply
-370-
TOSHIBA INTEGRATED CIRCUIT
TMP82C51 Ap·2/TMP82C51 AF·2
TMP82C51 AP-8/TMP82C51 AF·8
TECHNICAL DATA
ABSOLUTE
HAXIMU~l
KATIt-;e;s
Symbol
VCC
Item
Power Supplv Volta"e (with respect to GI\Il)
I
VOLlT
PD
TSOLDEK
TSTe;.
TOPR.
10 ut put Vo 1 t a ge (w i t.h:.:-_r.::...:e~s~p:..:e;..:c;..:t-.::t.::.:o.-:::.G~)I;I:::.).::...:)______--:-I_-:::.lJ.:c.5::.. \::.. ',..:t:.::o:-,:V.::.:C.::.:C~+:::..O.:.;.5::.Power Dissi iltion C1a=70'C)
2S0mW
Soldering Temperature (10 sec)
260 C
Storage Temperature
1-65'C to IS0'C
Operating Temperature
1-40'c to B5'C
I-o.sv
Rating
to 7.0V
Vl~------~~I~n~p~\l~t~V~oltCa~g~e~(~w~i~t~il~-re~s~p~e~c~t~t~o~e;~I'\·~D,)~~~---TI--0~~.5~V~t~0~V~C7C~+0~.S~
D.C CHARACTERS
Topr = -40'C to +B5'C, VCC = +SV + 10%, GND=OV, Unless otherwise noted.
I~boll
IVIL
IVIH
IVOL
iVOHl
IVOH2
I VOFL
I
IIlL
Parameter
Iinput Low Voltage
IInput High Voltage
IOutput Low Voltage
10utput High Voltage
!Output High Voltage
lOut put Leak Current
I
I Input Leak Current
I Test Conditions
I
I
I IOL=2.2rnA
I IOH=-400uA
I IOH=-100uA
10. 45V~VOlJT 82C51A)
J
m-,ffi
1:ww
towC'!
1:DW
DATA BUS
(INPUT DATA)
DON'T CARE
town
DON'T CARE
ATA STABLE
-
f-- I-- toWA
tAW
-,!-
-1,-
toAW
toWA
...., ' -
-~
READ CONTROL OR INPUT PORT CYCLE (82C51A
--> CPU)
..... r-
-I-~
toRR
1:CR
~
DATA BUS
(OUTPUT DATA )
toDF
DATA FLOATING
DATA FLOATING
"':; DATA VALID
...,~
toAR
tRA
tAR
tRA
~'-
-376-
TOSHIBA INTEGRATED CIRCUIT
TMP82C51 AP-2/TMP82C51 AF-2
TMP82C51 AP-8/TMP82C51 AF-8
TECHNICAL DATA
TRANSMITTER CONTROL AND FLAG TIMING (SYNC MODE)
RECEIVER CONTROL AND FLAG TIMING (SYNC MODE)
IYri:'£T
1S':A""S JIlT)
-r-Vr----'-<
------~1
~------
"
I~-~~~~~~~
(StATUS lIT)
I
hD
BYlIe
SY/i::
C~Al
Cl'.Af'Jd
.nn1UlrlKAJ'l
4S':Y .I.OUlS
he
t
PU >lU"" .. ll.
It.T (;YNJ"f:';
J)
lEt
-377-
11 Ke .. ,,:, .,tH
.ThLf.Tt::TATU~
en .lINUbiT)
I!'TATl::; !l17)
TOSHIBA INTEGRATED CIRCUIT
TM P82 C51 AP-2/TM P82 C51 AF-2
TECHNICAL DATA
TRANSMITTER CONTROL AND FLAG
TMP82C51 AP-8/TMP82C51 AF-8
(ASYNC MODE)
TI~ING
'l'J.£ItU'iY
1'slU'¥
(S'r.lnus
In'!)
TxF.DY
(P1»
TxD
£IAM?LE
~GRMAT
:
~
211 CHARAC:!R •
srop
2
Blrs.
)rIou : ix.RD'i( FIt:) - ( TnnSlnlt De.ta !.Jf!u ia .,ltpty ) . (Tx[JOz:l) . ( erE - ~ )
a
'l'ltP.LY(S'IA'I'US SIT) - ( Tun.clt Data 1Iu.!fer
.mpt1 )
RECEIVER CONTROL AND FLAG TIMING (ASYNC MODE)
RECEIVER CONTROL AND FLAG THllNG
(ASYNC MODE)
~ 1'---
OD
(PlN)
I
1'"xFDY
(G'IATlJS BIT)
tATA
I
O~
h
I
;...1,
LOST
II""
\
~
I
RID
RI" DATA 1
J
\
DATA3
1 ~
""I"",
i
"" IlsL~
lIn
'
.
I~
.
"
.,
"
"
DATA
IMTA
DATA
CHAMl
CHAfl.A2
CHA.RAJ
&UMPLI: rO,UlA.']' : ., lilT CHAIlACTlr, WI!H PAAITY
-378-
,
'.
s 1
a.
I
810,. .lTs.
\.
\L1rV-
L;
~
J!
eRr.".
•e
2' 3 " ~
I
Q
f' ffiF
;-
TOSHIBA INTEGRATED CIRCUIT
TMPB2C51 AP-2/TMP82C51 AF-2
TMPB2C51 AP-B/TMP82C51 AF-B
TECHNICAL DATA
OUTLINE DRAWING (Dual Inline Package)
Unit in mm
2f
1524:1025
:,L--____-'
I: :
l'" 'I
11
+01
025_ 005
0-15"
Note: Lead pitch is 2.S4mm and to lerance is +O.2Smm against theoretical
center of each lead that is obtained on-the basis of NO.1 and NO.28
leads.
-379-
INTEGRATED CIRCU IT
TOSHIBA
TMP82C51 AP-2/TMP82C51 AF-2
TECHNICAL DATA
TMP82C51 AP-B/TMPB2C51 AF-B
OUTLINE DRAWING (FLAT PACKAGE)
Uni t in mm
r---i--i
I
I
'
i
MARKING_~
,-- !
AREA
...o
I
+i
o
......
L_-+_~
140±O.1
(1 7.6±O.3)
1~5
"\.1
,
J
.//\
~
<
:..
MARK
1
uu 1J 1IllJU u u U
(l.2±0.2 )
(0.6 )
"'i
,.....
'"
0
-380-
t-
'"
ttl
15.2±0.3
ttl
'"...
~
.L
TOSHIBA INTEGRATED CIRCUIT
TMP8251AP
TECHNICAL DATA
PROGRJl.MflABLE CQfn,lUNICATION INTERFACE
GENERAL DESCRIPTION
The
T~)825lAP
is the industry standard Universal Synchronous/
Asynchronous Receiver/Transmitter (USART) that is fabricated using
N-channel silicon gate MOS technology.
The TNP825lA is mainly used for 8-bit microcomputer extension
systems, which require serial data communications.
FEATURES
Synchronous and Asynchronous Operation
Synchronous:
5-8 Bit Characters
Internal or External Character Synchronization
Single or Double Character Synchronization (Internal)
Automatic Sync Insertion
Asynchronous:
5-8 Bit Characters
Clock Rate - 1,16 or 64 Times Baud Rate
Break Character Generation
I, 1112, or 2 Stop Bits
False Start Bit Detection
Automatic Break Detect and Handling
• Baud Rate DC to 64K Baud (Synchronous)
CC to 19.6K Baud (Asynchronous)
Full-Duplex, Double-Buffered, Transmitter and Receiver
Error Detection-Parity, Overrun and Framing
Single +5V Supply
Compatible with Intel's 825lA/S2657
-381-
TOSHIBA INTEGRATED CIRCUIT
TMP8251AP
TECHNICAL DATA
PIN CONNECTIONS (Top View)
D~
DJ
D:;
00
RxD
GND
:;
D4
b
Db
6
vce
RxC
DB
2J
DTR
HTS
DER
HES>:T
D7
8
TxC
9
CJ,K
Wli
JU
TxO
CT.;
11
Txl!:MPTY
C/O
J2
ltv
J3
CTS
8YNDl!:T/BD
RxRDY
14
TxlWY
BLOCK DIAGRAM
THANSMIT
IlU~'j<'ER
TxD
( P~S )
TxROY
Txl!:Ml'TY
CONTHOL
TXC
lil!:C>:lV>:
BUFj<'ER
( p~S )
RES >:1'
C LK
-+-------1
-+-------1
c/ii -+-----1
Rfi-+------d
iVk-+------d
CS-+------d
RxD
HxRDY
SYND>:T/BD
HEAD/WRIT"-
HxC
CONTHOL
LOLlIC
H1'8
M UD>:M
C'J'S
DTR
vee
OND
INTl!!RNAL
DATA BUS
-3-82-
TOSHIBA INTEGRATED CIRCUIT
TMP8251AP
TECHNICAL DATA
PIN NAMES AND PIN DESCRIPTIONS
Interface Signals to CPU (Main System)
DO
~
D7
(Input/Output)
This 3-state, bidirectional, 8-bit buffer is used to interface the 8251A
to the system Data Bus. Data is transmitted or received through the
buffer upon execution of Input or Output Instroctions of the CPU. Control
Words, Command Words and StJtus Information are also transferred
through the Data Bus Buffer.
W (Input)
A "low" level signal on this input informs the 8251A that the CPU is
Writing Data or Control Words to the 82~IA.
RD (Input)
A "low" level signal on this input informs the 825lA that the CPU is
Reading Data or Status Information from the H251A.
"i:S (Input)
A "low" level signal on this input selects the 825lA. No reading or
writing operation will occur unless the device is selected. When CS
is "high" the Data Bus is in the floating state and RD and WR have no
effect on the chip.
C/O (Input)
This input signal, in conjunction with the WR and Rn- inputs, imforms
the 8251A that the word on the Data Bus is either a Data Character,
Control Word or Status Infromation. A "high" level signal meJns
Control or Status, a "low" level signal means Data.
C/ll
RD
0
0
WR
0
0
1
0
1
1
x
1
x
x
0
x
IT
DATA Bus
0
825IA Receive DATA Buffer
0
8251A Transmit DATA Buffer' DATA Bus
0
8251A Status DATA Buffer
>
DATA Bus
~
DATA Bus
0
8251A Command DATA Buffer
0
DATA Bus is in floating state.
1
-383-
+
TOSHIBA INTEGRATED CIRCUIT
TMP8251AP
TECHNICAL DATA
CLK (Input)
The CLK input is used to generate internal device timing. No external input
or output is referenced to CLK, but the frequency of CLK must be greater than
30 times the, Receiver or Transmitter Data Bit Rates
(RxC or TxC) in
Synchronous Operation, and greater than 4.5 times the Receiver Data Hit RateS
(RxC) in Asynchronous Operation.
RESET (Input)
A "high" level signal on this input forces the 8251A into an "Tdle" mode.
The device wi II remain at "Idle" untill a new set of Control Words is
written into the 825lA to program its functional definition. Minimum
RESET pulse wid th is 6 tcy.
MODEM Control Signals
DSR (Input)
The
Its
The
Set
DSR input slgnal is a general purpose, I-bit inverting input port.
condition can be tested by the CPU using a Status Read Operation.
DSR input is normally used to test MODEM conditions ~uch as Data
Ready signal.
DTR (Output)
The DTR output signal is a general purpose, I-bit inverting output port.
It can be set "low" by programming the appropriate bit in the Command
Instruction Word. The DTR output signal is normally used for MODEM
control such as Data Terminal Ready or Rate Select signal.
RTS (Output)
The RTS output signal is a general purpose, I-bit inverting output port.
It can be set "low" by programming the appropriate bit in the Command
Instruction Word. The RTS output signal b normally used for ~10DHl
control such as Request to Send signal.
CTS (Input)
A "low" level signal on this input enables the 825lA to transmit serial
data, i f the Tx Enable Bit in the Command Byte is set to a "one" (TxEN=I).
either a Tx Enable off (TxEN=O) or CTS of f (CTS=l) condition occurs while
the Tx is in operation, the Tx will transmit all the data in the USART,
written prior to Tx Disable Command before shutting down.
-384-
If
TOSHIBA INTEGRATED CIRCUIT
TMP8251AP
TECHNICAL DATA
Transmit Control Signals
TxC (Input)
The Transmitter Clock controls the rate at which the character is to be
transmitted. In the Synchronous Transmission Mode, the Baud Rate (Ix)
is equal to the TxC frequency. In Asynchronous Transmission Mode the
baud rate is a fraction of the actual TxC frequency. A portion of the
Mode Instruction selects this factor; it can be I, 1/16 or 1/64 the TXC.
For Example:
If Baud Rate equals 110 Baud,
TxC
~
110 Hz (Ix)
TxC
~
1.76 KHz (16x)
TxC
~
7.0 1• KHz (64x)
The falling edge of TxC shifts the serial data out of the 8251A.
TxD (Output)
This line is used to transmit the serial data. Serial output data on
TxD is changed from parallel data to serial data in accordance with the
format specified by the Control Words.
TxD line will be held in the marking state ('I' level) immediately on
one of the followings.
Tx Disable
Master Reset
CTS signal is high
(CTS~I)
(TxEN~O)
TxEMPTY signal is high (TxEMPTY~I)
TxRDY (Output)
This output informs the CPU that the transmitter is ready to accept a Data
Character. The TxRDY output pin can be used as an interrupt to the system,
since it is masked by Tx Disable(TxEN~O), or, for polled Operation, the CPU
can check TxRDY using a Status Read Operation. TxRDY is automatically reset
by the trailing edge of WR when a Data Character is loaded from the CPU.
The TxRDY pin output status (TxRDY (pin» is different from the TxRDY status
bit status (TxRDY (status bit» as follows.
TxRDY (status bit)
TxRDY (pin)
~
(7ransmit Data Buffer Empty)
(Transmit Data Buffer Empty)' (CTS~O)' (TxEN~l)
TxEMPTY (Output)
The TxEMPTY output will go "high" when the 825lA has no characters to send.
It resets upon receiving a character from the CPU if the transmitter is
enabled.
-385-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
In Synchronous Mode, a "high" level signal on this output indicates that
a Character has not been loaded and the SYNC Character or Characters are
about to be or are being transmitted automatically as "fillers". TxEHPTY
does not go "low" when the SYNC characters are being shifted out.
Receive Control Signals
The Receiver Clock controls the rate at which the character is to be
received. In Synchronous Hode, the Baud Rate (Ix) is equal to the actual
frequency of RxC. In Asynchronous Hode, the Baud Rate is a fraction of
the actual RxC frequency. A portion of the Mode Instruction selects this
factor; I, 1/16 or 1/64 the RxC.
For Example:
if Baud Rate equals 2400 Baud,
RxC
=
RxC
RxC
2.4 KHz (Ix)
38.4 KHz (16x)
=
153.6 KHz (64x)
Data is sampled into the 8251A on the rising edge of RxC.
RxD (Input)
This line is used to receive the serial data. Serial input data on this
line is changed to parallel data in accordance with the format specified
by the Control Words, and then transfered to the Recive Data Buffer.
RxRDY (Output)
This output indicates that the 825lA contains a Data Character that is
ready to be input to the CPU. RxRDY can be connected to the interrupt
structure of the CPU, or, for Polled Operation, the CPU can check the
condition of RxRDY using a Status Read Operation.
Rx Enable off both masks and holds RxRDY in the Reset Condition.
-386-
TMP8251AP
TOSHIBA INTEGRATED CIRCUIT
TMP8251AP
TECHNICAL DATA
SYNDET/BD (Input/Output)
This pin is used for SYNDET in Synchronous Mode and may be used as either
input or output, programmable through the Control Word. It is reset to
output mode "low" upon RESET. When used as an Output (Internal Sync Mode),
the SYNDET pin will go "high" to indicate that the 82SlA has located the
SYNC Characte in the Receive Mode. If the 825lA is programmed to use
Double Sync Characters then SYNDET will go "high" in the middle of the
last bit of the second SYNC Character. SYNDET is automatically reset upon
a Status Read Operation. When used as an Input (External Sync Mode), a
positive going signal will cause the 82S1A to start assembling Data
Characters on the rising edge of the next RxC.
In Asynchronous Mode this pin is used for BD.
This output will go "high" whenever the receiver remains "low" through
two consecutive Stop Bit Sequences (including the Start Bits, Data Bits,
and Parity Bits). Break Detect may also be read as a Status Bit.
It is reset only upon a Master Chip Reset or Rx Data returning to a
"one" state.
But, if the hX Data returns to a "one" State during the last bit of the
next character after the Break, Break Detect does not always reset.
Power Supply
VCC (Power)
+5 Volt
supply
GND (Power)
o
Volt supply
-387-
TOSHIBA INTEGRATED CIRCUIT
TMP8251AP
TECHNICAL DATA
ABSOLUTE MAXIMUM RATINGS
SYMBOL
ITEM
RATING
-0.5V to 7.0V
VCC
VIN
Power Supply Voltage (with respect to GND)
Input Voltage (wit h respec t to GND)
VOUT
PD
Output Voltage (with respect to GND)
-0.5V to 7.0V
-0.5V to 7.0V
Power Dissipation (Ta=70·C)
Soldering Temperature (10 sec)
Storage Temperature
lW
260·C
-55·C to l50·C
-
Tsolder
Tstg.
Topr.
O·C to 70·C
Operating Temperature
D.C. CHARACTERISTICS Topr=O°C to 70·C, Vcc=5V ±5%, GND=OV, Unless otherwise noted.
SYMBOL
VIL
VIH
VOL
PARAMETER
Input Low Voltage
TEST CONDITIONS
Input High Voltage
Output Low Voltage
IOL=2.2mA
IOW- 4OO IJA
VOFL
IIL
Output High Voltage
Output Leak Current
Input Leak Current
0.45V5:VOUT5:VCC
ICC
Power Supply Current
All Outputs="High'
VOH
0.45V5:VIN~VCC
MIN.
TYP.
-0.5
-
2.2
-
-
-
MAX.
0.8
UNIT
VCC
0.45
V
V
V
2.4
-
-
-
-
flO
±10
IJA
IJA
-
-
100
rnA
V
A.C. CHARACTERISTICS Topr=O°C to 70°C, VCC=5V±5%, GND=OV, Unless otherwise noted.
BUS READ CYCLE TImNG Note 1)
SYMBOL
tAR
PARAMETER
tRA
CS, C/D Hold Time for RD
tRR
tRD
RD Pulse Width
Data Delay Time for RD
Data Hold Time for RD
tDF
TEST CONDITI ONS
CS, C/D Set-up Time for RD
Note 2)
CL=150pF
Note 3)
MIN.
50
TYP.
MAX.
-
50
250
-
-
10
-
UNIT
ns
ns
ns
250
ns
100
ns
BUS WRITE CYCLE TIMING Note 1)
SYMBOL
tAW
tWA
tww
tDW
tWD
tRV
PARAMETER
CS, C/D Set-up Time for WR
CS, C/D Hold Time for WR
TEST CONDI TI ONS
MIN.
50
50
250
WR Pulse Width
Data Set Up Time for WR
Data Hold Time for WR
Recovery Time Between WRITES
150
50
Note 4)
-388-
6
TYP. MAX.
-
-
-
UNIT
ns
ns
ns
ns
ns
tcyc
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
OTHER
TMP8251AP
TIr~ING
SYMBOL
tcyc
tH
tL
t R , tF
PARMIETER
~IIN .
320
Clock Period
Note 5) , 6)
140
Clock High Level Width
Clcok Low Level Width
90
Clock Rise and Fall Time
TxD Delay Time from Falling Edge of
tDTx
TxC
Ix Baud Rate
DC
Transmitter Input -fTx
l6x Baud Rate
DC
Clock Frequency
64x Baud Rate
DC
Transmitter Input
12
Ix Baud Rate
Clock High Level
tTPH
l6x,64x
Baud
Rate
1
Width
Transmitter In ut
Ix Baud Rate
15
Clock Low Leve
tTPL
3
16x,64x Baud Rate
Width
Ix Baud Rate
DC
Receiver Input
fRx
16x Baud Rate
DC
Clock Frequency
64x Baud Rate
DC
Receiver Input
Ix Baud Rate
12
Clock High Level
tRPH
r------------l6x,64x Baud Rate
1
Width
Receiver Input
Ix Baud Rate
15
tRPL
Clock Low Level
3
Width
l6x,64x Baud Rate
from Center of
TxRDY
Delay
Time
Pin
tTxRDY
Last Bit
Clear Delay Time from Trailing
tTxRDY CLEAR TxRDY
Edge of QR
RxRDY Pin Delay Time from Center of
tRxRDY
Last Bit
from Leading
Clear
Delay
Time
RxRDY
tRxRDY CLEAR
Edge of RD
Internal SYNDET Delay Time from
tIS
Rising Edge of RxC
External SYNDET Set-Up Time fore
16
tES
F_a.!]!:,~ Edge of RxC
---TxHIPTY Delay Time from Center of
20
tTxEMPTY
Last Bit
Edge
Control Delay Time from Rising
8
twc
of WR
( TxEN DTR RTS)
20
tCR
DSR, -cTS Set-up Time for RJ)
1
-389-
TYP.
-
-
-
-
-
-
MAX.
UNIT
1350
ns
tcyc-90 ns
ns
20
ns
1
64
310
615
kHz
-
tcyc
-
tcyc
64
310
615
kHz
-
-
-
-
-
lJS
tcyc
tcye
-
8
tcye Note
-
6
teye Note
-
24
-
6
tcyc Note
-
2 1,
tcyc Note
-
-
tcye Note 7
-
-
teye Note 7
-
-
teyc Note 7
tcye Note 7
-
teyc Note 7
TOSHIBA INTEGRATED CIRCUIT
TMP8251AP
TECHNICAL DATA
Notes:
1)
AC Test Conditions: Output measuring point VOH=2.0V, VOL=O.8V
Input supply level
R~
2)
Assumes that Address is valid before the fall ing edge of
3)
CL means load capacitance.
4)
This recovery time is defined only for Mode Initialization.
Write Data is allowed only when TxRDY=l.
Recovery Time between
Writes for Asynchronous Mode is 8 tcy and for Synchronous Mode
is 16 tcy.
5)
The TxC and RxC frequencies have the following limitations with
respect to CLK:
For Ix Baud Rate, fTx or fRxSl/(30tcy)
For 16x and 64x Baud Rate, fTx or
6)
Minimum Reset Pulse Width is 6 tey.
fRx~1/(4.5tcy)
System Clock must be running
during Reset.
7)
Status up data can have a maximum delay of 28 clock periods from
the event affecting the status.
-390-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8251AP
TIMING WAVEFORMS
SYSTEM CLOCK iNPUT
\'----
C LK
TRANSMITTER CLOCK AND DATA
tTPL
tTPH
TxC(jxMOlJE)
TxC(J6xMODE)
TxD
RECEIVER CLOCK AND DATA
IJATA
/{xD
BIT
L
RxC( lxMODE)
SfaC PERIODS
(1 b x MODE)
I bHxC PERIODS
(16 x MOD£<:)
/{xC(lbxMODE)
------------~II~----------------~\~---------
INTERNAL
SAMPLING PULSE
-391-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8251AP
WRITE DATA CYCLE (CPU'" 8251A)
l
TxRDY
tww
r
tTxRDY CLEAR
f-
tDW
DATA BUS
(INPUT DATA)
tWD
DON'T CARE
DON'T CARE
L 'oTA tlTAlJLl!'
tWA
tAW
rtAW
tWA
READ DATA CYCLE (8251A'" CPU)
\
RxRDY
tRxRDY CLEAH
tRR
RD
tf-I
tltD
DATA BUS
(OUTPUT DA TA)
tDF
DATA
DATA FLOATING
DATA VALID
..,
tHA
tAH
V
C/D
tAR
-392-
tRA
~'LOATIN G
TOSHIBA INTEGRATED CIRCUIT
TMP8251AP
TECHNICAL DATA
WRITE CONTROL OR OUTPUT PORT CYCLE
(CPU -+ 8251A)
-+twe
tv.'\\!
tnw
DATA BUS
(lNPUT DATA)
DON'T CARE
tWD
DON't CARE
ATA STABLJ<;
-
tAW
f-- ~tWA
-c'-
tAW
tWA
0-
READ CONTROL OR INPUT PORT CYCLE
~-
(8251A + CPU)
-AtOR
tRH
~
DATA BUS
(OUTPUT DATA )
tDF
DATA FLOATING
DATA FLOATING
•
DATA VALID
-¥
tAR
tRA
tAR
tHA
-~
-393-
_F-
TOSHIBA INTEGRATED CIRCUIT
TMP8251AP
TECHNICAL DATA
TRANSMITTER CONTROL AND FLAG TIMING
(SYNC MODE)
TlI.k\.JY
($TAtUS flIT)
T)(HDY
( 1'1 N)
TxD
EXAWl"LK
Fut"'U.T
~
BIT
CHARAClEN
WlTH
PAHITY
RECEIVER CONTROL AND FLAG TIMING
~
::iYNC
CHAfiACTEJ1S,
(SYNC MODE)
~
/
I NT ~ftNAL S 'ole
£XTEJ<
I-<
'",...
0
z
H
:s
"l
~
p;
><
I-<
'"'"
0.25TYP
05±O15
Note: 1.
This dimension is measured at the center of bending point of leads.
2.
Each lead pitch is 2.54mm, and all the leads are located within
±O.25mm from their theoritical positions with respect to No.1 and
No.28 leads.
3.
This dimension is to outside of leads.
-396-
TOSHIBA INTEGRATED CIRCUIT
TMP82C53P-2/F-2
TECHNICAL DATA
TOSHIBA MOS TYPE DIGITAL INTEGRATED CIRCUIT
TMP82CS3P-2/TMP82CS3F-2
SILICON MONOLITHIC
CMOS SILICON GATE
PROGRAMMABLE INTERVAL TIMER
GENERAL DESCRIPTION
The TMP82CS3P-2/F-2(hereinafter referred to as TMP82CS3) is a programmable
counter/timer.
It is organized as 3 independent 16 bit counters, each
operates with a ~ount rate of up to SMHz. All modes of operation are software
programmable.
FEATURES
o
o
o
o
o
o
o
Count Binary or BCD
3 Independent 16 Bit Counters
Single +SV Supply
Count rate DC to SMHz
6 programmable Counter Mode
Low Power Consumption 2mA TYP. @SMHz
Extended Operating Temperature -40 0 C to 8S o C
PIN CONNECTIONS
TMP82CS3P-2
TMP82CS3F-2
.....
~~~;~~~~~~~
~
D7
D6
DS
Dl
D;;
D"
Dl
D,:
vee
~
Jill
L:S
C:'K~
Ne
JUT"
otr:'v
CU:l
GA!El
JUTl
ub.TE0
Vss (GND)
PIN NAMES
D7 - DO
CLK N
GATE N
OUT N
C"')N_CG'l-=_c.c.r:~M
NC
GATE~
~.
Data Bus (8 bit)
Counter Clock Input
Counter Gate Input
Counter Output
~
MMMMNNNNNNN
A1
AO
'"
"'''
N
34
35
36
37
38
39
40
41
42
43
44
n
iIR
VCC
• ICV
07
06
05
NC
NC
22
21
20
19
18
17
16
_ N M ....
NC
NC
eLKl
GAUl
DUll
ICV·
15
VSS(GHO)
GATE 0
14
13
12
DUTO
NC
NC
a.nccot-m"':="::
,",U_MNU_CQUU
~
.. = c c a . = c ! 5 z a .
Read Counter
WR
Wri te Counter
AO - Al
VCC
Vss
Chip Select
Counter Select
+5V
Ground (OV)
'"'
*) ICV (Pin17 and Pin39) must be
connected with Vcc or must be OPEN
NC : No Connection
-397-
TOSHIBA INTEGRATED CIRCUIT
TMP8ZC53P-Z/F-Z
TECHNICAL DATA
BLOCK DIAGRAM
CLKO
GATE a
OUTO
DATA
BUS
Bl'FFER
D1 '\, Do
RD
\-i'R
Ao
Al
CS
CLKI
GATEI
oun
CONTROL
WORD
REGISTER
II 2
-398-
CLK2
GATE2
OUT2
TOSHIBA INTEGRATED CIRCUIT
TMP82C53P-2/f-2
TECHNICAL DATA
Read/Write Logic
The Read/Write Logic accepts inputs from the system
generates control signals for overall device operation.
bus
and
in
turn
I
I cs I RD
v.'R I Al I AO
I
1----1----1----1----1----1-------------------------1
1 0 1 1 I 0 I 0 I 0 I Load Counter
I
1----1----1----1----1----1-------------------------1
I 0 I 1 I 0 I 0 I 1 I Load Counter
I
1----1----1----1----1----1-------------------------1
I 0 I 1 I 0 I 1 I 0 I Load Counter "/2
I
1----1----1----1----1----1-------------------------1
I 0 I 1 I 0 I 1 I 1 I Wri te Mode Word
I
/----1----1----1----1----1-------------------------1
I 0 I 0 I 1 I 0 I 0 I Read Counter
I
1----1----1----1----1----1-------------------------1
I 0 I 0 I 1 I 0 I 1 I Read Counter
I
1----1----1----1----1----1-------------------------1
I 0 I 0 I 1 I 1 I 0 I Read Counter #2
I
1----1----1----1----1----1-------------------------1
10/01111111
I
1----1----1----1----1----1 Data Bus is in
I
I 1 I x I x I x I x I High-impedance state
I
1---- 1---- 1---- 1---- 1---- I
I
1011111xlxl
I
",0
"n
",0
"n
Control Word Register
The Control Word Register is selected when AO, Al are 11. It then accepts
information from the data bus buffer and stores it in a register.
The
information stored in this register controls the operational MODE of each
counter, selection of binary or BCD counting and the loading of each count
register.
No reading of the contents of the control Word Register is
available.
Counter #0, Counter #1, Counter #2
These three blocks are identical so only a single counter will be
described. Each counter consists of a signle, 16 bit, preset table , DOv.'N
counter. The counter can operate in either binary or BCD and its input,
gate and output are configured by the selection of MODES (Six MODES: MODE
o to MODE 5) stored in the Control Word Register. Also the control word
handles the loading of the count value so that software overhead can be
minimized for these functions.
The reading of the contents of each counter is available to the programmer
with simple READ operations for event counting applications.
Special
commands and logic are included in the TMP82C53 so that the contents of
each counter can be read "on the fly" without having to inhibit the clock
input.
-400-
TOSHIBA INTEGRATED CIRCUIT
TMP82C53P.2/F-2
TECHNICAL DATA
[MODE Definition)
Mode 0:
lnterrupt on Terminal Count.
The output will be initially low after the mode set operation. After
the count is loaded into the selected count re~ister, the output will
remain 10'" and the counter ,"'ill count.
....'hen terminal count is
reached the output ,"'ill go high and remain high until the selected
count register is reloaded wi th the mode or a new count is loaded.
The counter continues to decrement after terminal count has been
reached.
Rewriting
fo 110wi ng:
(1)
(2)
MODE 1:
a
counter
register
during
counting
results
in
the
Write 1st byte stops the current counting.
Write 2nd byte starts the new count.
Programmable One Shot.
The output will go low on the count following the rising edge of the
gate input.
The output will go high on the terminal count.
If a new count value
is loaded while the output is low it will not affect the duration of
the one-shot pulse until the succeeding trigger.
The current count
can be read at any time without affecting the one-shot pulse.
The one-shot is retriggerable, hence the output will remain low for
the full count after any rising edge of the gate input.
MODE 2:
Rate Generator
Divide by N counter.
The output will be low for one period of the
input clock. The period from one output pulse to the next equals the
number of input counts in the count register.
If the count register
is reloaded between output pulses the present period will not be
affected, but the subsequent period will reflect the new value.
The gate input, when low, will force the output high.
When the gate
input goes high, the count will start from the initial count.
Thus,
the gate input can be used to synchronize the counter.
When this mode is set, the output will remain high until after the
count register is loaded.
The output then can also be synchronized
by software.
MODE 3:
Square Wave Rate Generator
Similar to MODE 2 except that the output will remain high until one
half the count has been completed (for even numbers) and go low for
the other half of the count.
-401-
TOSHIBA INTEGRATED CIRCUIT
TMP82C53P.2/F-2
TECHNICAL DATA
This is accomplished by decrementing the counter by t~o on the
falling edge of each clock pulse. When the counter reaches terminal
count, the state of the output is changed and the counter is reloaded
with the full count and the whole process is repeated.
If the count is odd and the output is high, the first clock pulse
(after the count is loaded) decrements the count by 1.
Subsequent
clock pulses decrement the clock by 2.
After timeout, the output
goes low and the full count is reloaded.
The first clock pulse
(following the reload) decrements the counter by 3. Subsequent clock
pulses decrement the count by 2 until timeout.
Then the whole
process is repeated.
In this way, if the count is odd, the output
will be high for (N + 1)/2 counts and low for (N - 1)/2 counts.
MODE 4:
Software Triggered Strobe
After the mode is set, the output will be high.
When the count is
loaded, the counter will begin counting.
On terminal count, the
outpu t wi 11 go low for one input clock period, then wi 11 go high
again.
If the count register is reloaded between output pulses, counting
will continue from the new value. The count will be inhibited while
the gate input is low.
Reloading the counter register will restart
counting beginning with the new number.
MODE 5:
Hardware Triggered Strobe
The counter will start counting after the r1s1ng edge of the trigger
input and will go low for one clock period when the terminal count is
reached. The counter is retriggerable.
The output will not go low
until the full count after the rising edge of any trigger.
Status
I
1
Modes
0
1
2
3
4
5
I
Low or Going Low
1
1
1
Rising
High
1
Disables counting
1
Enable counting
1(1) Initiates count-I
1
1
1
1
1 (1)
ing
1
Resets output
1
after next clockl
1
Disables count- 1 (I) Reloads counter 1
1 (2) Initiates count-I Enable counting
ing
1
1 (2) Sets output im- 1
ing
1
mediately High 1
I
1
1(1) Disables count- I
I
ing
I
I Initiates counting I Enable counting
1(2) Sets output im- I
1
mediately High 1
1
I
I Disables counting I
I Enable counting
I
I Initiates counting I
1
1 (2)
Figure 1.
Gate Pin Operations
-402-
TOSHIBA INTEGRATED CIRCUIT
TMP82C53P-2/F-2
TECHNICAL DATA
MODE 0:
Interrupt on Terminal Count
MODE 3:
C L [CI.
C LGCr
I
1
~
iJ J.. TE
(r;=:
OUTPUT
2
3
II
I
-rr
1
,
t
t·
2
G J.. Ti
(m::I!C)
, .. ,
.::
,
--,
I
~.+:f=II.
MODE 1:
,.
, .. , .. ,
,
0
r
I t i
i
OC?"fPrY.
(=,)
---+-+'L-Jr-+I-,
Cllm:RF\JIT )
~
~
:<
O:'':"P..j
II I
~-f-l----!I----t
,
~
(=, )
I
(Th'T~_Tl)
, .. ,
,
,
,
O:'IT\.r:
(.
C' U1 I t'T
TF II.
Square Wave Generator
MODE 4:
Programmable One-Shot
Software-Triggered Strobe
C L0 Cr:
~r-------------
Vi'r,
u
OLIE
(r-.lGJ=r.j - - - - - '
:;
;:
1
0
G t.TE
G;.. 'IE
2
~
(~,D}U)
1
[;
O"...l'P.}'T
( t,=' )
MODE 2:
C:.,
n
MODE 5:
Rate Generator
c) cr.
CLO
cr..
L=.Jr----- nn
n
~
ODTP.'T
3
2
1
01'1
~,
:G
U
1 0131 <;
1
0
Hardware-Triggered Strobe
~r--------------
o h TE
L~ (Thl3JEF)
3
2
DUTro!
(n=:;·)
Of. TE
(RESE:')
(31
3
:G
:c
1 C\31 2
1
r---------~
01-. T E
(TRlGJEF,)
OUTFUT
----1L...J
'
(t,= )
Figure 2.
TMP82C53
Timing Diagrams
-403-
1
0
U
OUTroT
(1
3
,
3
2
0
U
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP82C53P.2/F·2
PROGRAMMING the THP82C53
All of the MODEs for each counter are programmed by the systems
software by simple I/O operations.
Each counter of the THP82C53 is individual Iv programmed b1-~7iting a
control word into the Control Word Register. cCS;O, AO=Al=l, WR=O)
D7
D6
I se 1 I seo! RL II
I I I
I
I
I
0
ISelect Counter 0
0
I
ISelect Counter 1
0
1
I
ISelect Counter 2
1
0
I
IIllegal
1
I
I
I
Counter Latchin
eration
Read/Load least significant
bJ::te onlJ::
I
Read/Load most significant I
bJ::te onlJ::
I
Read/Load least significant I
byte first then most
I
significant byte
I
Note.
SC:
BCD:
D3
D2
Dl
DO'
RLO i H2
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
0 II 0
1 II 0
II x
0 II x
II
II
I
I
HI
MO
I
I
I
I
I
I
I
I
0
1
0
1
0
1
BCD
I
I
0
M:
Mode,
D4
D5
I
I
I
I
I
I
I
I
0
0
1
1
0
0
Select Counter, RL: Read/Load,
Binary Coded Decimal.
Figure 3.
MODE
MODE
MODE
MODE
MODE
MODE
Binary Counter
(l6-bits)
BCD Counter
(4 Decades)
0
1
2
3
4
5
Control Word Format
The programmer must write out to the TMP82C53 a MODE Control Word and
the programmed number of count register bytes (l or 2) prior to actually
using the selected counter.
The actual order of the programming is quite flexible.
Writing out
of the MODE Control Word can be in any sequence of counter selection.
The loading of the Count Register with actual count value, however,
must be done in exactly the sequence programmed in the MODE Control Word
(RLO, RLl).
Counter Loading
The count register is not loaded until the count value is written
(one or two bytes, depending on the mode selected by the RL bits),
followed by a rising edge and a falling edge of the clock.
The count register must be loaded with the number of bytes programmed
in the MODE Control Word. The one or two bytes to be loaded in the count
register do not have to follow the associated MODE Control Word. They can
be programmed at any time following the MODE Control Word loading as long
as the correct number of bytes is loaded in order.
All counterY6are down counters4 Loading all zeros will result in the
maximum count (2
for Binary or 10 for. BCD). In MODE 0 and MODE 4, the
new count will not restart until the load has been completed.
-404-
TOSHIBA INTEGRATED CIRCUIT
TMP82C53P-2/f·2
TECHNICAL DATA
Read Operations
ThE' TIIP82C53 contains logic that will allow the programmer to -easily
read the contents of any of the three counters without distrubing the
actual count in progress.
Th('re are two methods that the programmer can use to read the value
of the counters.
ThE' first method involves th~ use of simple I/O read
operations.
By controlling the AO, Al inputs to the TMP82C53, the
programmer can select the counter to be read.
The only requirement with
th(s method is that in order to assure a stable count reading the actual
operation of the selected counter must be inhibited either by controlling
the Gate input or by external logic that inhibits the clock input.
The contents of the counter selected must be read in the sequence
programmed in the MODE Control Word (RLO, RLJ).
When RLO, RLl is 11.
First I/O Read contains the least significant byte (LSB), second I/O Read
contains the most significant byte (MSB) , and the two bytes must be read
before any loading ~R command can be sent to the same counter.
The second method allows the programmer to read the contents of any
counter without effecting or distrubing the counting operation.
When the
programmer wishes to read the contents of a selected counter "On the fly",
he loads the MODE register with a special code which latches the present
count value into a storage register so that its contents contain an
accurate, stable quantity.
The programmer then issues a normal read
command to the selected counter.
The contents of the latched register
must be read in the sequence programmed in the MODE Control v.'ord (RLO,
RLl).
This commands has no effect on the counters mode.
Program Example
Set up sequence
for counter lfO
READ the contents
of counter #0
RELOAD to
counter 410
MVI
OUT
A, OOllOOOOB
CWAD
MVI
OUT
MVI
OUT
A, 53H
CNTO
A, 82H
CNTO
MVI
OUT
IN
MOV
IN
MOV
A, OOOOXXXXB
CWAD
CNTO
L, A
CNTO
H, A
MVI
OUT
MVI
OUT
A, 28H
CNTO
A, 53H
CNTO
-405-
4'0, LSB-MSB, MODE 0, Binary
The address of Control Word
Register
LSB for counter #0
The address of counter 4fO
MSB for counter t'o
The address of counter #0
Latching count
Read LSB of counter liO
Read MSB of counter 410
Load LSB for counter
ito
Load MSB for counter #0
TOSHIBA INTEGRATED CIRCUIT
TMP82C53P-2/F-2
TECHNICAL DATA
ABSOLUTE MAXIMUM RATINGS
I SYMBOL I
ITEM
I
RATING
I
1-------- 1----------------------------------------------1-------------------1
I vcc
I Vee Supply Voltage (with respect to Vss[GND]) I -0.5v to +7.0V
I
1-------- 1----------------------------------------------1-------------------1
I VIN
I Input Voltage (with respect to Vss [GND])
I -0.5v to Vcc+O.Sv 1
1--------1----------------------------------------------1-------------------1
I VOUT I Output Voltage (with respect to Vss [GND])
I -0.5v to Vcc+O.SV I
1-------- 1----------------------------------------------1-------------------1
I PD
I Po",er Dissipation
I
250 my;'
I
1--------1----------------------------------------------1-------------------1
I Tsol I Soldering Temperature (Soldering Time 10 sec) I
260°C
I
1--------1----------------------------------------------1-------------------1
I Tstg I Storage Temperature
I -65°C to +lSOoC
I
1--------1----------------------------------------------1-------------------1
I Topr I Operating Temperature
I -LiOOC to 85 0 C
I
DC CHARACTERISTICS
(Ta = -40 to + 85 0 C, Vee
5V ± 10%, Vss(GND)=O\'
=
I SYMBOL I
PARAMETER
I TEST CONDITION I MIN. I TYP. I PAX. I UNIT I
1--------1----------------------1--------------1-----1-----1------1------1
I VIL
I Input Low Voltage
I
1-0.5 I
: 0.8 I
V I
1-------- 1---------------------- 1-------------- 1----- 1----- 1----·-- 1------ !
I VIH
I Input High Voltage
I
I 2.2 I
I Vee I
V I
I
I
I
I
I
I +0.5 I
I
1--------1----------------------1--------------1-----1-----1------1------1
I VOL
I Output Low Voltage
I IOL=2.2 rnA
I
I
I 0.45 I
V I
1--------1----------------------1--------------1-----1-----1------1------1
I VOHI I Output High Voltage I IOH~400 uA I 2.4 I
I
I
V I
1--------1----------------------1--------------1-----1-----1------1------1
I VOH2 I Outpu t High Vol tage I IOH=-lOO uA I Vee I
I
I
V I
I
I
I
1-0.8 I
I
I
I
1--------1----------------------1--------------1-----1-----1------1------1
I IlL
I Input Leak Current
I OV
"Ie\,
:>1: ..
*ICV
PAl
PM
PAl
. .0
rb1
'h.,
!-1.:3
NC
I!D
~~:c~~~~~~~~
*ICV (pin 17 and Pin 39) must be connected
to VCC (Pin24) or must be open.
NC: No Connection
-427-
TOSHIBA INTEGRATED CIRCUIT
1M P82 C55AP.5/AF-5/AP.2/AF-2/AP-l 0/AF-l 0
TECHNICAL DATA
D7-DO
~lDIHECTIONAL
DATA
HD
WR
CS
HEAD WRITE CONTHOL LouiC
AD
DATA BU$ BUFFER
Al
Rl::!:;ET
OROUP A
GROUP B
CONTROL
CONTROL
INU':,l-L',AL 8-I:l1T bUS
uHOUI' A
uKUUI' b
1/0
1/0
1/0
1/0
PA7-PAO
f'C7-PC4
PC;..i-PCO
PB7-PBO
-428-
TOSHIBA INTEGRATED CIRCUIT
TMP82C55AP.51AF-51AP.21AF-21AP.I OlAF-I 0
TECHNICAL DATA
2.
Pin names and pin functions
Pin Name INumberl Input/Output I
lof Pin I 3-state
I
D7 - DO I
8 I
I/O
I
I
I
I 3-state
I
I
I
I
I
I
PA7-PAO I
8 I
I/o
I
I
I 3-state
I
I
I
I
I
I
I
I
I
I
PB7-PBO I
8
I
I/O
I
I
I 3-state
I
I
I
I
I
I
I
I
I
I
PC7-PCO I
8
I
I/O
I
I
I 3-state
I
I
I
I
CS
RD
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Input
I
I
I
I
I
Input
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
WR
I
Input
AO, Al
2
Input
RESET
I
Input
vee
I
IPower Supply I
I
I
VSS
Function
I
I
3-state bidirectional 8-bit data bus.
I
Used for data transfer 'Jith CPU. Also, usedl
for transfer of control words to PPI and
status information from PPI.
3-state 8 b1t I/O Port A.
Operation mode and input/output configuration are defined by software. Port A contains the output latch buffer and input
latch.
3-state 8-bit I/O Port B.
Opepration mode and input/output configuration are defined by software. Port B contains the output latch buffer and input
latch.
3-state 8-bit I/O Port C.
Operation mode and input/output configura- I
tion are defined by software. Port C can be I
divided into two 4-bit ports by the mode
I
control and also, used as the control signal I
for Port A and Port B. In this case, 3 bits I
of PCO to PC2 are used for Port Band 5 bits I
of PC3 to PC7 for Port A.
I
Chip select input.
I
When this terminal is at "L" level, data
I
transfer PPI and CPU becomes possible. At
I
"H" level, the data bus is placed in the
I
high impedance state and control from the
I
proces sor is ignored.
I
Read signal.
I
When this terminal is at "L" level, data
I
that is input into the port is transferred I
to CPU.
I
Write signal.
I
When this terminal is at "L" level, data
I
or control word is written into PPI from
I
CPU.
I
Used for selecting Port A, B, C and the con-I
trol registers. Normally, this terminal is I
connected to low order 2 bits of the addressl
bus.
I
When this terminals is at "H" level, all
I
internal registers including the control
I
register are cleared. In addition, all
I
ports (Port A, B, C) are placed in the input I
mode (high impedance) of mode O.
I
sv
I
I
I
I
I
I
IPower Supply I GND
-429-
I
TOSHIBA INTEGRATED CIRCUIT
T~P82 C55AP-5/AF-51AP-2/AF·2/AP'l 01AF·l 0
TECHNICAL DATA
3.
Functional Description
The PPI is a progranunable peripheral interface with three 8-bit ports
(Port A, B and C) and two control registers. 24 I/O terminals are divided
into 12-bit group A and group B.
Group A consists of Port A and high
order 4 bits of Port C, while Group B consists of Port B and low order 4
bits of Port C. Each group is independently programmable by control word~
provided from CPU. There are three operation modes available for the PPI.
In mode 0, two 8-bit 1/0 ports and two 4-bit I/O ports can be progranuned
as input or output ports, respectively.
In mode 1, 24 I/O terminals are
divided into Group A and Group B.
8 bits of each group are used as input
or outpt port and of the remaining 4 bits, 3 bits are used as handshaking
and interrupt control signal.
Mode 2 is applicable only to group A and
the terminals are used as a bidirectional 8-bit data bus and 5-bit control
signal.
In case of Port C being used as the output, any bits of Port C
can be set/reset.
There are two control registers; one is used for mode setting and the
other for bit set/reset control.
The control registers can only be
written iuto.
Further, when the reset input (RESET) becomes "I", the
control registers are reset and all I/O tel~inals are placed in input mode
(high impedance status).
Function
Al
AO
0
0
1
0
0
.1
0
1
0
0
1
0
x
x
x
x
CS
0
0
0
0
0
0
0
1
0
0
1
Table 3.1
3.1.
RD
WR
0
0
0
1
1
1
1
1
1
0
0
0
0
x
x
1
0
Port A
Data bus
(Data bus
Port B
(Data bus
Port C
(Port A
Data bus
(Port B
Data bus
(-Port C
Data bus
(Control reglster (---- Data bus
Data bus
3-state
-)
Data bus
__)
3-state
inhibition of combination
Basic Operation of TMP82C55A
Mode Selection
There are three basic modes of operation that can be selected by control
words.
(Group A, Group B)
Mode 0 - Basic I/O
(Group A, Group B)
Mode 1
Strobe input/Strobe output
(Port A only)
Mode 2 - Two-way bus
-
Operation modes for Group A and Group B can be independently defined by
the control word from the CPU. If DB7 is set to "I" in writing a control
word into the PPI, on operation mode is selected, while of DB7 c "O". the
set/reset function for Port C is selected.
-430-
TOSHIBA INTEGRATED CIRCUIT
TMP82 C55Ap·51AF·51 AP-2/AF·2/ Ap·l 01AF·l 0
TECHNICAL DATA
3.1.1 Control word to define operation mode
Fig. 5.1 shows the control words to
TMP82C55A.
define
operation
mode
of
the
Control Word
D7
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Group A Condto1 !Group B Cantrall
D6 I D5
D4
D3 ! D2 ! Dl I DO I
I
-II
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
!
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Input/output selection of
low order 4 bits of Port C
'0' = Output
'I' = Input
Input/output selection of
of Port B
Output
'a'
' I' = Input
Mode selection of Group B
'0' = Mode a
' I' = Mode 1
Input/output selection of
high order 4 bi ts of Port C
'0' = Output
'I' = Input
Input/output selection of
of Port A
Output
'a'
'1' = Input
Mode Selection Group A
'a' = Mode 0
D6
0
0
1
Designation of mode
set flag
x:
Fig. 3.1
D5
0 = Mode 0
Mode 1
1
x = Hade 2
Don't care
Control Word for Mode Selection
3.1.2 Port C bit set/reset control word
Any bit of 8 bits of Port C can be set/reset by Port C bit set/reset
control word. Fig. 3.2 shows the Port C bit set/reset control word.
-431-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPS2 C55AP-5/AF-5/AP-2/ AF-2/ AP-1 0/AF-l 0
Control Word
D7
I
I
I
I
I
D6
DS I D4
_II
Don't care
Bit Set/Reset Flag
"Oil = Active
D3
D2
D1
DO
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
0
0
0
0
1
0
0
1
1
0
0
1
Fig. 3.2
0
0
1
0
1
0
1
Bit set/reset selection
PCO
PCl
PC2
PC3
PC4
PCS
PC6
PC7
Control Word fOT
I-I
I
i
i
i
I
i
i
I
I
I
I
I
I
I
~it
"0"
Reset
"III
Set
Bit selection
Set/Reset
3.2
Operation Modes
3.2.1
Mode 0 (Basic I/O)
This functional configuration is used for simple input or output
operations. No 'handshaking' is required and data is simply ,,'ritten to
Output data to the ports from CPU are
or read from a specified part.
latched out but input data from the ports are not latched.
In Hade 0, 24 I/O terminals are divided into four groups of Port A (8
bits), Port B (8 bits), high order 4 bits of Port C and low order 4 bits
The
of Port C.
Each port can be programmed to be input or output.
configuration of each port are determined according to the contents of
Bit 4 (D4), 3(D3), l(Dl) and O(DO) of the control word for mode
selection.
The I/O configuration of each port in Hade 0 are shown in Table 3.2.
-432-
TOSHIBA INTEGRATED CIRCUIT
TMPS2 C55AP-51AF-51AP-21AF-21AP-l OlAF-I 0
TECHNICAL DATA
Node Setting Control Word
D4 I D3 I D1 I DO
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
I
0
I
0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Table 3.2
0
1
0
1
0
0
0
1
0
1
0
1
Port
A I
Out
Out
Out
Out
Out
Out
Out
Out
In
In
In
In
In
In
In
In
Port C
I (PC7-PC4)
I Out
I Out
I Out
I Out
I In
I In
I In
I In
I Out
I Out
I Out
I Out
I In
I In
In
I
I In
Port B
Out
Out
In
In
Out
Out
In
In
Out
Out
In
In
Out
Out
In
In
I Port C
I (PC3-PCO)
I Out
I In
I Out
In
I
Out
In
Out
In
Out
In
Out
In
Out
In
Out
In
,t
Port definition in Mode 0
3.2.2
Mode 1 (Strobe I/O)
In Mode 1, input/output of port data is performed in conjunction with the
strobe signals or 'handshaking' signals. Port C is used to control Port
A or Port B.
The basic operatings in Mode 1 are as follows:
0
Mode 1 can be set for two groups of Group A and Group B.
Each group consist of 8-bit data port and 4-bit control/data port.
The 8-bit data port can be set as input or output port.
The control/data port is used as control or status of the 8-bit data
port.
0
0
0
(1)
When used as the input port in Mode 1:
o STB (Strobe Input)
At "0", input data is loaded in the internal input latch in the port.
In this case, a control signal from CPU is not concerned and data is
input from the port any time.
This data is not read out on the data
bus unless CPU executes an input instruction.
o
IBF (Input Buffer Full F/F Output)
When data is loaded in the internal input latch from the port, this
output is set to "1". IBF is set ("1") by STB input being reset and is
reset ("0") by the rising edge of RD input.
o
INTR (Interrupt Request Output)
Used for the interrupt process of data loaded in the internal input
latch. When STB input is at "0" if INTE (INTE flag) in the PPI is in
the enabled state ("1"), IBF is set to "l".
INTR is set to "1"
immediately after the rising edge of this STB input and reset to "0" by
the falling edge of RD input.
The INTE flags of Group A and Group B are controlled as follows:
-433-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP82C55AP-5/AF-5/AP-2/AF-2/Ap·l O/AF·l 0
INTEA - Control by bit set/reset of PC4
INTEB - Control by bit set/reset of PC2
(2)
Wh~used
o
as the output port in Mode 1:
OBF (Output Buffer Full F/F Output)
This is a flag which shows that CPU has written data into a specified
port. OBF is set to becomes "0" at the rising edge of WR signal and is
set to "1" at the falling edge of ACK (Acknowledge input) signal.
o
ACK (Acknowledge Input)
ACK signal is sent to the PP 1 as a response from a peripheral device
that received data from the port.
o
INTR (Interrupt Request Output)
When a peripheral device received data from CPU, INTR is set to "1" and
the interrupt is requested to CPU. If ACK signal is received when INTE
flag is in the enable state, OBF is set to "1" and INTR signal becomes
"1" immediately after the rising edge of ACK signal. Further, INTR is
reset at the falling edge of WR signal when data is written into the
PPI by CPU.
The INTE flags of , Group A and Group B are controlled as follows:
INTEA - Control by bit set/reset of PC6
INTEB - Control by bit set/reset of PC2
MOUl!: l( roPT A)
D'7lJ6D~D'D3D2[llDO
1,1 I, I'I~I xIx Ix I
0
j
rc6. pc.,
0 - OUTPUT
1 - JltPtlT
"0
MOllE l(l'uHT fI)
V.,l.I(,D~DtD3D2Dll>O
IHTHH
(a)
Fig. 3.3
(b)
Example of Strobe Input in Mode 1
-434-
TOSHIBA INTEGRATED CIRCUIT
TM P82 C55AP-5/ AF-5/ AP-2/ AF-2/AP-1 0/AF-l 0
TECHNICAL DATA
'~uNTklil
1l..4
'IflIvKl.>
f'e::>
'-' .. UUj Il'T
1- INjl)'r
lONT!~C'L
11£
i)~
,,"OhLo
iJ4 UJ
l.i2
1.11
!
L/(J
l'OHT Ol'Tl'LJl
-------y---------
INTi'U;
Fig. 3.4
Example of Strobe Output
~n
Mode 1
~
I,::t A
J
I
01\1
1/0
J
I, I xl
O~
l>f,
D.:l1..l:.:.o1
0
l
J't::4. tC~
O .. OUTKl1
I .. lIdj~IT
PC,
S'rl:\o
Pc)
1 b~ 10
PC?
(1 ..
(Jun-'UT
I'" 1 h"UT
I
u~T
At~
7hUb (IUH-'UT!
1''-1,,1 1:1(. ,liO!:!
DO
fC'§ INTRA
}'Cto-f'C;
:
1/0
t't!7-HRT It.
kv
Fig. 3.7
Operating example in Mode 1
-436-
IJ
Ir
/
!
/
TOSHIBA INTEGRATED CIRCUIT
TMP82C55AP-51AF-51AP-21AF-21AP-l 01AF-l 0
TECHNICAL DATA
Control Word in Mode 2
D7 D6 DS D4 D3 D2 Dl DO
1 I 1 I X I X I X 11/011/011/01
I
I
I
X = Don't care
I
I
I
I
1 1 _ __
I
1 _ _ _ __
Fig. 3.8
o=
PC2-0
I
Port B
Group B mode
1 =
o=
1 =
o=
1 =
Output
Input
Output
Input
Mode 0
Mode 1
Control Word and Configuration in Mode 2
Control Words
I
D7 D6 D5 D4 D3 D2
1 I 1 I X I X I X I 0
Dl DO
1 11/0 I
I
I
I
I
I
I
I
I
I
PC2-PCO
I
O=Output <--l=Input
I
I
RD
WR
_ _ >1
_ _ >1
PC31
PA7-PAO 1-->
pC71 <-t->
pC61 <_>
PC41
PCSI<->
I
I
INTRA
OBFA
ACKA
STBA
IBFA
3
PC2-PCOI<-t-> I/O
PB7-PBOI<-t-
1_ _ _ _ _ 1
Port A - Mode 2 I/O
Port B - Mode 0 Input
Control Words
I
D7 D6 DS D4 D3 D2 Dl DO
ljllxjxjXjllolxl
.!ill. __>
WR
_ _>
PC31
INTRA
PA7-PAO 1-->
pc71 <-t-> OBFA
PC61--> ACKA
PC41~= STBA
pcSI _ _ > IBFA
PB7-PBOI
PClll'-; OBFB
PC21<
ACKB
PBOI-=> INTRB
_____ 1
Port A - Mode 2 I/O
Port B - Mode 1 Output
Fig. 3.9
Examples in Combination with Mode 2 and Other Mode
-437-
TOSHIBA INTEGRATED CIRCUIT
TMP82C55AP-51AF·51AP-21AF·21Ap·l 01AF·l 0
TECHNICAL DATA
3.2.4 Precautions for use in Mode 1 and 2
When used in Mode 1 and 2, bits which are not used as control or status in
Port C can be used as follow.
If programmed as the input, they are accessed by normal Port C read.
I f programmed as the output, high order bi ts of Port C (PC - PC4) are
accessed using the bit set/reset function. As to low order bits of Port C
(PC3 - PCD), in additions ot access by the bit set/reset function, 3 bi.ts
only can be accessed by normal writing.
3.3.
Reading Port C Status
When Port C is used as the control port, that is, when Port C is used in
Mode 1 or Mode 2, the status information of the control word can be read
out by a normal read operation of Port C.
Data Mode
D7
Mode 1 Input
I/O
D6
D5
D4
D3
D2
D1
DO
I/O
IBFA
INTEA
INTRA
INTEB
IBFB
INTRB
INTEB
OBFB
INTRB
Mode 1 Output
OBFA
INTEA
I/O
I/O
INTRA
Mode 2
OBFA
H,TEI
IBFA
INTE2
INTRA
Table 3.3
By Group B Mode
Status Word Format of Port C
-438-
TOSHIBA INTEGRATED CIRCUIT
TMP82C55AP-51AF-51AP-21AF-21AP-1 01AF-1 0
TECHNICAL DATA
6.
Absolute Maximum Ratings
1 Symbol 1
Item
1
Rating
1 Unit 1
vcc
1 Supply Voltage
,
-0.5 to 7.0
1
V 1
1
1----------1-----------------------------------1--------------------1------1
1
VIN
1 Input Voltage
1 -0.5 to Vcc + 0.5 1
V 1
1----------1-----------------------------------1--------------------1------1
1 PD
1 Power Dissipation
1
250
1 mW I
1----------1-----------------------------------1--------------------1------1
1 TSOLDER I Soldering Temperature 00 sec)
1
260
I·c 1
1----------1-----------------------------------1--------------------1------1
1 TSTG
1 Storage Temperature
1
-65 to 150
I·c 1
1----------1-----------------------------------1--------------------1------1
1 TOPR
1 Operating Temperature
1
-40 to 85
1 ·C 1
7.
DC Electrical Characteristics
TA
1
1
1
1
1
\
\
\
I
1
I
I
I
1
I
1
I
1
1
1
= -40'C
SYMBOL
VIL
to 85·C, VCC
= 5V
ITEM
Input Low Voltage
± 10%, VSS =
o~
TEST CONDITION
MIN. ITYP.
0.3 , 1
2.2
VIH
Input High Voltage
VOL
Output Low Voltage
IOL
VORl
Output High Voltage
lOH = -4001J.A
2.4
VOH2
Output High Voltage
lOR - -1001J.A
VCC-0.8
ILl
Input Leak
0
= 2.5mA
MAX. I UNIT I
V
0.8
VCC
+0.5
0.45
V
V
V
-
< VIN =< VCC
V
±10
~A
±10
I
1
I
-1.0 I
VEXT
1. 5V
(Note!)
1 -5.0
REXT = 1 .l!ill
!DAR \
1
1
I/O cycle Time
1
1
I
I usec
ICCI 1
1 2.01 5.0
VIR> VCC-O.2V
I
1
\ (Note2)1
10
VIL < 0.2V
1
1
1 ICC2 1
cs > VCC-0.2V
1
1
1
1
(Notel) Applied for optional 8 I/O terminals in Port B and Port C.
(Note2 ) Icc2 is not specified for TMP82C55AP-2/AF-2/AP-IO/AF-IO.
~A
8.
Cur~ent
Output Leak Current
(High Impedance
State)
Darlington Drive
Current
OpErating Supply
Current
Stand-by Supply
Current
lLO
0
=
~
VOUT
~
VCC
-
mA
mA
~A
Capa ci tance
TA
= 25'C,
VCC=VSS=OV
SYMBOL 1
ITEM
1
TEST CONDITION
IMIN.ITYP. iMAX.luNIT\
1 - 1 - 1 10 , pF 1
CIN
I Input Capacitance I f - IMHz
1 - I
- , 20 , pF \
COUT 'Output Capacitance 1 (*)
(*): All terminals except that to be measured should be earthed.
-439-
TOSHIBA INTEGRATED CIRCUIT
TMP82C55AP-5/ AF-5/AP-2/AF·2/ AP-1 0/AF-l 0
TECHNICAL DATA
4.4
AC Electrical Charactreistics
TA =-40 o C to 8SoC, VCC = SV±lO%, VSS=OV
SYMBOL
tAR
tRA
tRR
tRD
tDF
tRV
tAW
tWA
tl.'W
tDW
tWD
tWB
tIR
tHR
tAK
tST
tPS
tPH
IAP-5/AF-5IAP-2/AF-21 AP,AF-IO!-I
IMIN.IMAX.IMIN.!MAX.IMIN.!MAX.luNIT I
I
!
!
!
!
!
I
I
Address set-up time for RD fall I 0 I - I 0 I - I 0 I - I ns j
!
!
I
I
I
I
I
I
Address hold time for RD rise I 0 I - I 0 I - I 0 I - I ns I
f
I
I
I
I
I
I
I
I
RD pulse width
I 300 I - I 1601 - I 1501 - I ns I
I
!
!
!
!
I
I
I
Delay from RD fall to decided I - I 2001 - I 140 I - I 1001 ns I
data ouq~ut
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Time from RD rise to data bus I 10 I 1001 0 I 401 0 I 401 TIS I
floating
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Time fromRD or WR rise to next I 8501 - I 2001 - I 1501 - I ns I
RD or WR fall
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Address set-uE time for WR fall I 0 I
I 0 I
I a I
I ns I
I
I
I
I
I
I
I
I
Address holding time for WR
I 20 I - I 201 - I 201 - I ns I
rise
I
I
1
I
I
I
I
I
I
I
I
I
I
I
I
I
WR Eulse width
I 300 I - I 1201 - I 1201 - I ns I
I
I
!
I
I
I
I
I
Bus data set-up time for WR
I 1001
I 1001
I 100 I
I ns I
rise
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Bus data holding time for WR
I 301 - I 301 - I 30 I - I ns I
rise
!
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Delay from WR rise to decided I - I 3501 - I 3501 - I 3501 ns I
data outEut
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Port data set-up time for RD
I 0 I
I ns I
I 0 I
I 0 I
fall
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Port data holding time for RD I 0 I
I ns I
I 0 I
I 0 I
rise
I
I
I
I
I
I
I
I
I
I
!
I
I
I
I
I
ACK Eulse width
I 3001 - I 3001 - I 3001 - I ns I
I
I
I
I
I
I
I
I
STB Eulse width
I 5001 - I 350 I - I 3501 - I ns I
I
I
I
I
I
I
I
I
Port data set-up time for STB I 0 I
I 0 I
I 0 I
I ns I
rise
I
I
I
I
I
I
I
I
!
!
I
I
I
!
1
I
Port data holding time for STB I 1801
I 1501
I ns I
I 1501
rise
I
I
I
I
I
I
I
I
PARAMETER
-440-
TOSHIBA INTEGRATED CIRCUIT
TMP82C55AP-5/ AF·5/AP-2/ AF·2/Ap·l 0/AF·l 0
TECHNICAL DATA
TA=-t,OOC
IAP-5/ AF-51 AP -2/ AF-21 AP,AF-IOI
I
IMIN.IMAX.IMIN.IMAX.IMIN.IMAX.luNITI
I
I
I
I
I
I
I
I
Delay from ACK fa 11 to decided I - I 3001 - I 300 I - I 3001 ns I
data outEut
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Time from ACK rise up to port I 20 I 2501 20 I 2501 201 2501 ns I
(Port A in Mode 2) floating
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Delay from WR rise to OBF fall I - I 650 I - I 3001 - I 3001 ns I
I
I SYMBOL
I
I tAD
I
I
I tKD
I
I
I
I
I
I
I
I
1
PARAMETER
tWOB
I
I
Delay from ACK fall to OBF rise I
I
I
I
I
I
I
I
I
I
I
- I 3501 - I 350 I
I
I
I
I
I
I
I
I
Delay from STB fall to IBF risel - I 300 I - I 3001
1
I
I
1
I
I
I
I
I
I
Delay from RD fall to INTR fall 1 -- I 4001 - 1 4001
I
I
1
I
1
tSIB
tRIB
I
I
1
to 8S o C, VCC=SV±lO%, V5S=OV
tRIT
I
I
I
tSIT
Delay from ACK rise to INTR
rise
1
I
I tAIT
Delay from ACK rise to INTR
rise
I
I
1
I
tWIT
Delay from WR rise to INTR
fall
Note 1.
2.
I
I
I
I
1
I
1
I
I
I
I
1
I
I
- I 3001
I
I 350!
I
I
I
1
I 4501
I
I
I
I
- I 3001
I
I
I
I
1 3501
I
I
1
4501
I
-
-
I
I
I
I
I
I
I 3501 ns I
I
I
I
I
I
I
I 3001 ns I
I
I
I
1
I
I
1 4001 ns 1
I
1
I
I
I
I
I 3001 ns I
1
1
I
I
I
I
I 3501 DS 1
I
I
I
I
I
I
I 4501 DS I
I
I
I
When the power supply is turned ON, reset pulse duration must be
active for at least 500 ns or more.
AC Measuring Point
Input Voltage
VIH=2.4V, VIL=0.45V
Output Voltage VOH=2.2V, VOL=0.8V
CL=l50pF.
-441-
TOSHIBA INTEGRATED CIRCUIT
TMP82 C55AP-5/AF-5/AP-2/AF-2/AP-l 0/AF-l 0
TECHNICAL DATA
4.5
Timing diagram
Mode 0
MODE
0
INPUT OPJ::H'TION
~
~
INPUT
t
I
CSA1.AO
D7 - DO
----J.\
r,H
I
I
-----
---------------------- -(
.
~
J
tDr'
MODE 0
OUTPUT OPERATION
tww
tD\\'
tWD
)[
D7 -DO
t,w
'0,
X.
OUTPUT
J
Fig. 4.1
Mode 1
MODE 1
INPUT OPERATION
tps
INPUT POIIT DATA
IBI"
INTR
-442-
TOSHIBA INTEGRATED CIRCUIT
TMP82 C55AP-51 AF-51AP-2/AF·21Ap·I 01 AF·I 0
TECHNICAL DATA
MUlJt: 1
ueTIVT OPEHAT)OH
I
1
INTI<
,
tww
I
t~IT
'\
oUT rUT
i'ORT l>ATA
tWOB
~
P-
I
I
J
,
J
I
pUU
j
I
I
Fig. 4.2
Mode 2
MODt: .2
U)liIHiXTluN OPERATlUN
WH
r-----,r--------------~~~J----------~~------------
INTk
OuF
I'EH) PH£HAL
BUS
1 fIr'
Fig. 4.3
-443-
TOSHIBA INTEGRATED CIRCUIT
TMP82 C55AP-51AF-51 AP-21AF-21 AP-l 01AF-l 0
TECHNICAL DATA
5.
Package Dimension
Plastic Packge
Unit
40
nnn
21
~
-<
::;::
N
..,;.
20
f"24±025
51.3MAX
0.5 ± 0.15
2.54 ±0.25
l~II
0.25
~~·;5
1.4 ±0.15
Note
1J\
-1-Y
0-15°
Each lead pitch is 2 .54mm, and all the leads are loea ted wi thin
nnn from their theoretical positions with respect to No.1 and
leads.
-444-
:to. 25
No.4
TOSHIBA INTEGRATED CIRCUIT
TMP82C55AP-51A~-51AP-21AF-21AP-l OlAF-I 0
TECHNICAL DATA
EXTERNAL DIMENSION VIEW (Mini Flat Package)
Unit in mm
140±O.1
( 17.6±0.3)
1~5
J
7/\
X
..:
;:;:
MARK
~I
l~
IT1J u uTI ..,.
ill U
"
LD
'0"'
15.2± 0.3
-445-
<-:
•I
I
UUU
LD
(1.2±0.2)
(0.6 )
~l
'"
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
-446-
TMP82 C55AP-5/AF·5/AP-2/AF·2/ AP-l 0/AF·l 0
INTEGRATED CIRCUIT
TOSHIBA
PROGRArU~ABLE
TECHNICAL DATA
TMP8255AP-5
PERIPHERAL INTERFACE (PPI)
GENERAL DESCRIPTION
T~W82SSAP-5 is the high speed programmable peripheral interface LSI,
capable of controlling parallel input/output data.
This LSI is programmable
in several operation moues and is capable of supplying a simple interface
between micro-processors and peripherals equipment.
24 input/output pins are divided into three 8-bit ports and used either
for input or output by programs.
All signal levels are TTL compatible.
Data transfer between the processor and T~82SSAP-S is possible by using
Chip Select Input (CS) and Port Address Ao, AI'
Data write/read operation to/from a specified port is possible by using
Write Input (WR) or Read Input (RD).
FEATURES
• Compatible with INTEL's 825SA-S
o
24 Programmable Input/Output Pins
• Programmable Operation Modes
• Direct Bit Set/Reset Capability
• Single +SV Power Supply
-447-
INTEGRATED CIRCUIT
TOSHIBA
TECHNICAL DATA
TMP8255AP-5
PIN CONNECTION
PIN NAt'lES
TOP VIEW
PAo
'V
PA,
Port
A
PB o
'0
PB,
Port
B
PCo
'0
PC,
Port
C
-
CS
PAJ
p'.;
1-'A1
"Au
Chip Select
-
RD
hLJ
00
CS
J~
A1
Read Signal
Au
-
WR
Write Signal
PC7
TMF8255AP-5
PC6
Ao
- A,
Port Address
RESET
Reset
D4
Do
}->c\i
lJ6
lJ 7
>'Cj
VCc(+OV)
pez
PB'I
PC3
BLOCK DIAGRAt1
D,- Do
Data Bus Buffer
I/O
I/O
I/O
I/O
PA 7 -PAo PC,-PC. PC.-PC o PE,-PB o
-448-
PHd
PSo
18
PB o
PSl
PBZ
j9
PB 4
20
PB3
Bidirectional Data Bus
Read/Write Control Logic
lJ3
P~~.s
pCo
Power Supply
VCC . VSS
RD
WR
CS
Ao
A,
RESET
RES ET
(GNLJ)V IJD
TOSHIBA INTEGRATED CIRCUIT
TMP8255AP-5
TECHNICAL DATA
FUNCTIONAL DESCRIPTION
I/O SIGNALS
TMP8255A-~
uses a 8-bit bidirectional data bus for data transfer to/from
the processor.
Data can be transfered between the data
b~s
and control
registers or between 2 output port groups (Group A and Group B), in the
inside of TMP8255AP-5.
There are 2 control registers.
Group A consists of high-order 4 bits of Port C and Port A.
Group B
consists of low-order 4 bits of Port C and Port B.
Port A
8 data bits are used for input latch/buffer, output latch/buffer,
or bidirectional bus, respectively.
Port B
8 data bits are used for input buffer or output latch/buffer.
Port C
8 data bits are used for input buffer, output latch/buffer, or
two 4-bit control ports in combination with Port A and B.
Operation of each port is controlled by programs.
When two inputs of Port Addresses Ao and A, are used together with Read
Input, Write Input and Chip Select, it is possible to select a specific
port or control register.
Port A selection
A,
0
Ao
0
Port B selection
A,
0
Ao
Port C selection
A,
1
Ao
0
Control register selection
A,
1
Ao
1
(Note: Readout operation from a control register is impossible.)
-449-
TOSHIBA INTEGRATED CIRCUIT
TMP8255AP-5
TECHNICAL DATA
Read (RD)
Data read operation from TMP8255AP-5 to the data bus is
controlled by RD signal (low active).
Write (WR)
Data write operation from the data bus to TMP8255AP-5 is
controlled by WR signal (low active).
Chip Select (CS)
TMP8255AP-5 is selected by CS signal (low active).
When CS="I", the data bus driver is in the high
impedance state.
Reset (RESET)
When RESET=" 1" , all internal registers are cleared and all
ports are in high impedance input mode.
Data Bus
The 8-bit data bus is used for transferring data and
(D,-D o )
program information between the processor and H1P8255AP-5.
PROGRAMMING
To program the operations of TMP8255AP-5, first select the internal control
function to be programmed by the processor.
To do this, execute the write
operation under the programming mode (AI = Ao = RD = "1", CS = WR = "0").
As a result, data bus information is written into one of two control registers.
Input/Output of respective ports and operation mode of each group (Mode 0,
1 and 2 are available) can be selected by one of these control registers.
Another control register is used for controlling set/reset of Port C bits.
One of these two control registers is selected by Bit 7 of the data bus.
When Bit 7 is "1", an operation mode is selected, while the set/reset
function is selected when it is "0".
-450-
TOSHIBA INTEGRATED CIRCUIT
TMP8255AP-5
TECHNICAL DATA
Bit 0 through 6 have different meanings depending upon a
selected control mode.
(a)
1
Control (DB7
~
"1")
Control of
Group B
Control of Group A
DB7
o
~Iode
Operation
DB.
I DB, I DB. I DB,
DB,
I
DB, lOBo
Control of Group A (DB. - DB])
The operation mode is defined by Bit 6 and 5, and the port
fu·nction (input or output) is selected by Bit 4 and 3.
o
Control of Group B (Bit 2, 1 and 0)
The operation mode is defined by Bit 2, and the port function
(input or output) is selected by Bit land O.
The detail of operation modes and port input/output selection are
described in the next item.
Relationship between operation modes and control bit are shown in
the following table.
Operation
Mode
r--
Control Bit
Group A
Group B
6
5
2
0
0
0
0
1
0
1
1
2
1
X
~~
Bit 6 and 5 define Group A
modes and Bit 2 defines
Group B modes.
Note: X mark shows that either 0 or 1 is acceptable.
-451-
TOSHIBA INTEGRATED CIRCUIT
TMP8255AP-5
TECHNICAL DATA
(b)
Bit Set/Reset Control (DB7 = "0")
0
X
X
X
DB7
DB.
DB,
DB.
Bit
DB,
DB31
I/o
Select
J
DB,
DBa
Bi t Sele ct
Bit 3, 2 and 1 select Port C bit to be set/reset.
Port C Bit
Control Bit
--
Se Ie ction
3
2
1
0
0
0
0
1.
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
1---.
Set/Reset
When Bit 0 is "1", selected bit of Port C is set and when it is
"0", selected bit of Port C is reset.
4 are not used.
In this case, Bit 6, 5 and
Therefore, either "0" or "1" is acceptable.
OPERATION MODES
TMP8255AP-5 is designed for various pror,rams which control for
interfacing with various peripherals.
For this purpose, there are 3 basic modes.
-452-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8255Ap·5
Mode 0
24 input/output pins of 3 ports are devided into 4 groups of Port A
(8 bits), Port B (8 bits), Port C (high order 4 bits) and Port C
(low order 4 bits).
Data is latched in the output port, but is not latched in the input
port.
In the data input operation, input data is placed on the data
bus at RD
=
O.
The combination of input/output of these 4 groups is
available in 16 ways.
This combination is selected by the operation
mode register of TMP8255AP-5 using Bit 0, 1, 3 and 4 of the data bus.
Programming under Mode 0
In the case
DB,
=
DB,
=
cs
=
WR
=
"0", Al
=
Ao
=
RD
=
"1", DB7
=
"1" and DB.
"0", the programming is shown in the following table.
Data Bus Bit
Port A
Port C
4
3
1
0
0
0
0
0
Out
Out
0
0
0
1
Out
Out
0
0
1
0
Out
0
0
1
1
Out
0
1
0
0
0
1
0
0
1
1
0
1
1
1
0
1
0
Port B
(PC 7-PC.)
Port C
(PC.-PC o)
.
Out
Out
Out
In
Out
In
Out
Out
In
In
Out
In
Out
Out
1
Out
In
Out
In
0
Out
In
In
Out
1
Out
In
In
In
0
0
In
Out
Out
Out
0
1
In
Out
Out
In
Out
1
0
1
0
In
Out
In
1
0
1
1
In
Out
In
In
1
1
0
0
In
In
Out
Out
1
1
0
1
In
In
Out
In
1
1
1
0
In
In
In
Out
1
1
1
1
In
In
In
In
-453-
TOSHIBA INTEGRATED CIRCUIT
TMP8255Ap·5
TECHNICAL DATA
Mode I
Under Mode I, Port A and high order 5 bits of Port C are correlated to
Group A, and Port B and low order 3 bits of Port B are correlated to Group
B, respectively.
Port C is used for a control signal to control input/output data of Port A
or Port B.
The internal enable/disable flip-flop (INTEl can be controlled by settlng/
resetting Bit 4 and 2 of Port C when Ports A and B are uSed as the input
ports using the bit set/reset function, and by setting/resetting Bit 6 and
2 when they are used as the output ports.
When bit set/reset is "1", the flip-flop is placed in the enable state,
and when bit set/reset is "0", i t is placed in "he disable' state.
Data transfer between the ports and peripherals is controlled b) 3 control
signals for input operation, and is also controlled by J control signals for
output operation.
Functions of individual bits of Port C are specified as
shown in the following table.
--
Related Port ___
I
A
B
Control Functions
Input
Output
PC,
STB
PC,
IBF
PC,
INT~
PC,
pc.
aBF
PC 7
PC,
ACK
I------INTR
- - - ------PC.
--
PC,
--~-----
T-pc,--f--
PC,
pCo -~
--'-------
Out of above stated control functions, those related to input are
as follows.
-454-
TOSHIBA INTEGRATED CIRCUIT
TMP8255Ap·5
TECHNICAL DATA
o
Strobe Input (STB):
When STB
=
"0", data is loaded into the input
latch
o
Input Buffer Full (IBF):
loaded.
Interrupt Request (INTR):
=
This signal shows that data has been already
IBF is set by STB = "0" and is reset at the rising edge of RD.
If INTE flag is in the enable state and TBF
"1", INTR signal becomes" 1" at STB
"1"
INTR signal can be directly connected to INT input of the processor,
and when data is loaded on a port, an interrupt signal is generated.
INTR is reset when RD signal from the processor is received into the
port .
On the other hand, control functions related to output are as follows.
o
Output Buffer Full (OBr):
This is a flag showing that the processor
has loaded data on a specific port (OBF
=
0).
OBF becomes "0" at the
rising edge of WR signal and becomes "1" at the falling edge of ACK
signal from peripherals.
o
Acknowledge (ACK):
When data has been received from a TMP8255AP-5
port, a peripheral responds to TMP825 c AP-5 by transmitting an acknowledge
signal ACK (low active).
o
Interrupt Request (INTR):
This output can be used to interrupt the processor
when a peripheral has accepted data transmitted by the processor.
If INTE flag is in the enable state and
set by ACK
=
"1" and is reset by QR
=
Q!IF
= "1",
INTR sIgnal is
"0".
Mode 2
Under mode 2, Port A is used as a bidirectional bus.
output of Port A are latched under this mode.
-455-
Both input and
TOSHIBA INTEGRATED CIRCUIT
TMP8255AP-5
TECHNICAL DATA
5 bits of Port C are used for control between peripherals and TMP8255AP-5.
Signals used for this control are as follows:
STB, IBF, OBF and INTR:
The functions of these signals are identical
in Mode 1.
ACK:
When this signal becomes active (low), 3-state output buffer of
Port A is enabled to transfer data to peripheral equipment.
During other periods, the output buffer is in high impedance.
For the selection enable/disable of INTE flip-flop, Bit 6 is used for
output operation, and Bit 4 is used for input operation.
Data transfer
between the ports and peripherals is executed by designating pins of
Port C same as in operations under Mode 1.
Under Mode I and 2, Port C status and control bits can be tested when
Port C contents are read out.
All bits of Port C are not used fur
control and status functions, unspecjfied bits can be programmed for
input or output as described below.
In the case Port C has been programmed as output, Pins (PC, - PC.) of
Group A operate Port C by using the bit set/reset function.
Pins (PC; -
PC o ) of Group B controls write operation into Port C or read operation
by using the bit set/reset function.
-456-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8255AP-5
ABSOLUTE MAXIMUM RATING
SYMBOL
Tstg
PARAMETER
Storage
--_. --
Topr
-
Temperature
--~--~--------
Operating
Supply
Voltage
VOUT
Output
Voltage
VIN
Input
Voltage
Pw
Power
Dissipation
-- - - - -_.
-----
D.C CHARACTERISTICS
----
-0.5V to 7.0V
-0.5V to 7.0V
-0.5V to 7.0V
f--
VIL
VIH
Input High Voltage
- - - - 1----------VOL
Output Low
Voltage
VOH
Output High
Voltage
--
1. 0(.1
TEST
--
2.0
( DB)
(PER)
( DB )
10L = 2.5 rnA
r--
(PER)
Input Leak Current
- - ------- .. _ - -
10L = 1.7 rnA
IOH = -400
IOH = -200
VEXT
REXT
1----
OV
OV
~A
2.4
~A
2.4
= 1. 5V,
= 750Q
~
VIN
~.
VOUT
---.-----
Output Leak Current
~
-1.0
r-----
VCC
----
UNIT
V
V
~-
0.45
V
0.45
V
---
V
---
V
I
VCC
~
ClAX.
0.8
VCC
-4.0
rnA
±IO
~A
±IO
~A
120
rnA
MAX.
UNIT
10
pF
20
pF
-- -
Supply Current
CAPACITANCE
SY~lBOL
TYP.
I
(High Impedance State)
ICC
MIN.
- - I--
Darlington Drive
Current
-
CONDITION
-O.S
---
--~--.
--------~---
(Ta = O°c to 70°C, VCC=5V±5%, VSS=OV)
Input Low Voltage
IOFL
DOC to 7DoC
-- _._------ - - - - - - - - - - -
PARAMETER
SYMBOL
IlL
-- ----
~-
Temperature
----------------- ----------
VCC
IDAR
(No te 1
RATING
-65°C to l50°C
(Ta=25°C, VCC=VSS=OV)
PARAMETER
CIN
Input Capacity
CI/O
I/O Capacity
TEST
CONDITION
fc = 1 MHz
-457-
mN.
TYP.
TOSHIBA INTEGRATED CIRCUIT
TMP8255AP.5
TECHNICAL DATA
A.C. CHARACTERISTICS
(Ta=O·C to 70·C, VCC=5V!5%, VSs=OV)
snmOL
tAR
tRA
PARAMETER
RD Pulse Width
tRD
tDF
Data Valid from RD (Note 2)
tAW
tWA
tIM
Address Stable after WR
tDW
tWD
Data Valid after WR
tIR
tHR
MAX.
10
850
ns
200
ns
100
ns
ns
0
ns
20
ns
300
100
ns
ns
30
WR = 1 to Output Delay (Note 2)
Peripheral Data before RD
Peripheral Data after RD
UNIT
ns
ns
0
Data Float after RD
Time between READs and/or WRITEs
Address Stable before WR
WR Pulse Width
Data Valid to WR
tWB
TYP.
0
300
tRR
tRV
MIN.
Address Stable before RD
Address Stable after RD
ns
350
0
ns
ns
0
300
ns
ACK Pulse Width
tST
tps
STB Pulse Width
Peripheral Data before Rising Edge of STB
500
0
ns
ns
tpH
Peripheral Data after Rising Edge of STB
ACK = 0 to Output (Note 2)
180
tAK
tAD
tKD
ns
250
ns
(Note 2)
(Note 2)
650
ns
350
ns
STB = 0 to IBF = 1
(Note 2)
300
ns
RD= 1 to IBF = 0
RD = 0 to INTR = 0
(Note 2)
(Note 2)
300
400
ns
ns
STB
= 1 to INTR = 1
= 1 to INTR = 1
WR = 0 to INTR = 0
(Note 2)
300
ns
ACK
(Note 2)
350
ns
(Note 2)
850
ns
tAOB
ACK = 0 to OBF = 1
tSIT
tAIT
tlHT
20
ACK = 1 to Output Float
WR
tRrT
ns
300
tWOB
tSIB
tRIB
ns
= 1 to OBF = 0
-458-
TOSHIBA INTEGRATED CIRCUIT
TMP8255A,.5
TECHNICAL DATA
TIMING WAVEfORMS
MODE 0
INPUT OPERATION
INPUT
MODE 0
OUTPUT OPERATION
tWVI
1\
c
-
tllW
)(
tAW
-
r-twD_l
-
tWA
----i
)[
)(
OUTPUT
f---
tWB
MODE 1
INPUT OPERATION
INPUT PORT
DATA
IBF
INTR
RD
'"'~'
--?
--------------------------~I~RH
-459-
~tRI:r
------------
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8255AP-5
HODE 1
OUTPUT OPERATION
1;
t
W
INTR
tww
-
f
'1'i
f--
-
OUT!'UT
FORT LATA
-
tWOb-
tAl 'I
f
tWb
l-
I
~
I
ACK
L.\ub
I
r--- 'I,,,,
-
~
HODE 2
BIDIRECTIONAL OfERATION
lr------~~------------------~,,~------------_,I:tj----------------
If
lNTH
tPI!
!'ERIPHle:RAL
BUS
llH
IJstHllJ}
-----------------~II~I-------------------.III--------------~,
- tHH
Note 1.
2.
3.
Available on any B pins of Port B dnd Port C.
Test conditions; CL; 150pF
Period of Reset pulse should be at least
on.
4.
Subsequ~nt
50~s
during or after power
Reset pulse Cdn be 500ns min.
Timing measuring levels are as follows:
-460-
high level
2V
low level
O.BV
TOSHIBA INTEGRATED CIRCUIT
TIP8255AP.5
TECHNICAL DATA
OUTLINE DRAHING
Uni t in mm
"
b
oJ
iC;
111:':: l:S 14
It::
itJ 1'/ 1M 11 .... \1
(Note 1)
025:1. 0 1
1 bOO -1 780
507±015
)
~
;i
~
51
... '"
N
I 1 = CALL ADDRESS INTERVAL 4
I 0 = CALL ADDRESS ll'n.RVAL 8
- - - - - - - - 7 ) I 1 = LEVEL TRIGGER MODE
I 0
EDGE TRIGGER MODE
=
---------------------7) 11 A7 to AS of VECTOR ADDRESS
------------lCW2
AO
07
D6
DS
D4
D3
D2
D1
IAlSIA141A131A121All lAW I Aq
I/T71/T61/1SI/141/T3 I
I
I
I
I
I
I
I
I
I
I
I
DO
Asl
I
)1 A1S-A8 of VECTOR ADDRESS
I or T7-T3 VECTOR ADDRESS
lCW3
AO
D7
D6
DS
D4
D3
s71 s61 ssl s41 S3
I
I
I
1
D2
Dl
s21 S1
I
DO
sol
I
)1 1 ., IR INPUT has a SLAVE.
IR II,PUT does not have a
I o
slave
I
=
-471-
TOSHIBA INTEGRATED CIRCUIT
TMP82C59AP-2/AF·2
TECHNICAL DATA
ICW4
AO
D7
06
DS
D4
D3
o
o
o
o
o
D2
01
DO
I llJ 2 I ID I lIDO I
I
I
I
I
SEAV£ ID
10111213141s16171
_ _+--"7)10111011101110111 ~ CASO
___-+-~> 10 I 0 I 1 I 1 10 101 1 I 1 I ~ CAS 1
_ _ _ _ _-+--7)IOIOIOIOlllllllll f-) CAS2
AO
D7'
D6
DS
o
o
o
D4
D3
02
01
DO
iSFNMIBUFIM/siAEoriuPMI
I
I
I
I
I
I
1
o
)1 1
---~I 0
8086/8088 MODE
808SA MODE
AEOI MODt
NORMAL MODE
I
I I(if; I - "'ON BuFFERED ~lODE
I Iill I - BUFFERED MODE/SLAVE
I iTTlI - BUFFERED MODE/MASTER
1-
)1 I
·------------~I 0
Fig. 3
SPECIAL FULLY NESTED MODE
FULLY "'EST ED MODE
ICW Format
ICW3
This is a co~~and required for cascade connection ~f plural number of
TMP82C59As. When SNGL = 0 in ICWl, the TMP82C59A interpretes a command
written with AO input made at "H" level after lCW2 as lCW3.
[IJ
Master Mode
In the master mode. the TMP82CS9A specifies individually as to wbether
a slave device is added to each interrupt request input.
If the TMP8085A is used as CPU ""'en addition of a slave device is
specified, the master device outputs CALL command code on the data bus
upon receipt of the first lNTA 5i!?naJ and simultaneously outputs the
slave identification code to the cascade line.
The master device becomes high impedance at the second and third INTA
signals, and the slave device selected by the identification code
outputs vector address on the data bus. When the 8086 is used as CPU,
both the master aod slave devices become high impedance at the first
INTA signal.
Simulataneous ly, the master device outputs the slave
identification code to the cascade line. The master device also
-472-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP82C59AP-2/AF-2
INIA
becom~s high impedance at the second
si~nal and the selected slave
device outputs a pointer on the data bus.
When it is specified that no slave device is added, the master device
outputs both CALL command code and vector address as a response to IN1A
signal and simultaneously outputs "L" signal to 3 cascade lines. - This
is the same as the identification code of the slave device connected to
IRa and therefore, in the case of the interrupt request input without
the slave device, added, no slave device can be added to IRO.
Further, to specify the master slave, the SP/E~ terminal must be set at
"H" level or BUF must be set at land M/S at 1 by ICW4.
l2J
Slave Mode
In the slave mode, the TMP82C59A specifies the slave identification
code.
The
slave
device
compares
its
identification
code
with
the
identification code sent from the master device via the cascade line
and if they agree, outputs vector addresses on the data bus upon
receipt of the second and third INTA signals.
Further, to specify the slave mode, the SP/EN terminal must be set at
"L" level or BUF at land M/S at 1 by lCW4.
The format of ICw3 is
shown in Fig. 3.
lCW4
lCW4 is effective only when lC4 = 1 in lCWl.
Although lCW4 is effective for assignment of the special fully nested
mode (SFt\M) , assignment of the buffer mode (BUF) and in the buffer
mode, this command makes the assignment of the master/slave (N/S),
automatic EOI (AEDI) and CPU mode.
When IC4
0 in lCWl, all function
bits of lCW4 are set at "0". The format of ICW4 is shown in Fig. 3.
=
(2)
Dew
There aTe 3 kinds of commands: DeWl, DeW2 and De"'3.
Any time after ICW
is programmed, these command can be programmed to set the nlP82C59A in
various operation modes.
DCi'll
After lCW is set, the TMP82C59A interpretes the operation set command to
be DCWl when AD '" 1. This command is used for setting the content of the
interrupt mask register (IMR). The DCWl format is shown in Fig. 4.
DCW2
The TMP82C59A interpretes the operation set command to be DCW2 when AO =
0, D4
0 and D3 '" O.
This command is used for outputting EDI L2 to LO
are effective only in the case of specific EDI and specific rotation.
The DCW2 format is shown in Fig. 4.
=
OCW3
The TMP82C59A interpretes the operation set command to be DCW3 when AO =
0, D4 .. 0 and D3 '" 1.
This command is used for assigning the special
mask mode, the poll mode and register fOT status information readout,
that is, assigning lRR or ISR. The OCW3 format is shown in Fig. 4.
-473-
TOSHIBA INTEGRATED CIRCUIT
TMP82C~9AP-2/AF-2
TECHNICAL DATA
OCv.'1
AD
I 1
I
D7
D6
D5
1J4
D3
D2
1':71 M61 M51 M41 M31 M21
I
I
I
I
I
I
DO
IJI
~1l1
I
Mol
I
)1
1 = INTERRUPT MASK SET
---'--'----'---'----'--'---'----'--~ I 0
= IKTERRllPI I"JlSK RESEI
OCW2
AO
D7
D6
DS
D4
D3
I 0 I R "I SLIEOllo I 0
I
I
I
I
I
I
I
I
I
I
I
D2
Dl
DO
L21 111 Lal
I
I
+
IR LEVEL TO BE ACTED UPOK
10111213!41s16171
_ _-+-_-;»10111011101110111
- - - - . - ; - - - i » 10 1]1011101110111
_ _ _ _ _-i-_~)IOIII011101110111
I
I I I
l 11
ICiTOTII
1011111
1110111
1110 101
1010101
11 11 11 I
1111101
NON SPECIFIC EOI COMMAND
SPECIFIC EOI COIIJ1AND
ROTATE OK KON-SPECIFIC EOI COM~~D
ROTATE IN AUTOMATIC EOI MODE (SET)
ROTATE IK AUTOMATIC EOI MODE (CLEAR)
ROTATE ON SPECIFIC Eor COMMAND
SET PRIORITY cmlMAND
NO OPERATION
IQlUQI
OCW3
AO
D7
D6
DS
D4
D3
I 0 I 0 I ESM~ll SMM I 0 I 1
I
I
I
I
I
I
D2
1J
I 0 I x
I 1 I 0
I 1 I I
DO
P I RRIRISI
I
I
I
I
II
III o x
0
III 1
1
III 1
II
I
I
I
I
I
I
I
I
I
I
Dl
J 1
NO OPERATION
READ IR REG SET
READ ISR REG SET
l
1
= POLL COMMAND
o = NO POLL COMMA1W
NO OPERATION
RESET SPECIAL MASK MODE
SET SPECIAL MASK MODE
Fig. 4 OCW Format
-474-
1- EOI
I
I
AUTOMATIC
1- ROTATION
I
SPECIFIC
ROTAT I or-;
TOSHIBA INTEGRATED CIRCUIT
TMP82C59Ap·2/AF·2
TECHNICAL DATA
[EXPLANATION OF MODES AND COMMANDS)
(1)
FULLY NESTED MODE
Unless other modes are specified, the TMP82C59A operates in this mode.
Under this mode, priority of the interrupt request inputs is most high' at
IRO and becomes low in order toward IR7.
When INTA signal is input, vector address corresponding to an interrupt
and request having the highest priority at the time is output together
with CALL command code on the data bus and furthermore, corresponding ISR
bits are kept set till EOI command is input to the TMP82C59A before CPU
returns from the service routine or to the final leading edge of INTA
pulse in AEOI mode. As long as these ISR bits are kept set, low priority
interrupt requests are ignored. Priority can be changed by OCW2.
(2)
EOI (END OF INTERRUPT)
EOI command is used to reset ISR bits. It is necessary for CPU to output
EOI command before returning from the service routine.
When AEOl is set in ICW4, ISR bit are automatically reset at the leading
edge of the final lNTA pulse and it is therefore not necessary to output
EOI command.
As ISR bits are set in both the master and slave devices
when cascade connected, it iF- necessary to output EOI command to to both
master device and the slave device corresponding to the master device.
EOI command is available in 2 kinds: non-specific EOI and specific EOI
commands.
When non-specific EOI command is output to the TMP82C59A, ISR bit having
the highest priority among ISR bit is reset.
However, in the special
mask mode it is not possible to reset ISR bit that are masked by IMR by
the non- spec if ic EO! command, and I SR bit having the highest priori ty
among the unmasked ISR bits is reset. On the other hand, it is possible
to specify lSR bit to be reset by the specific EOI command by a program.
EIO command is executed by OCW2.
(3)
AEOI (AUTOMATIC EOI) MODE
In this mode, the non-specific EOl operation is automatcally executed at
the leading edge of the final INTA signal.
Therefore, this mode cannot be used for multiple interruptions.
In
addition, this mode also cannot be used in the slave TMP82C59A.
The
TMP82CS9A can be set in AEOI mode by setting AEOI bit in ICW4 to 1.
(4)
AUTOMATIC ROTATION
This mode is effective in the application to give equal priority to the
interrupt devices.
In this mode, whenever the interrupt service ends, priority of each
interrupt request is updated so that the serviced interrupt request is
set at the lowest priority. Priority of interrupt request input IRn (n=O
to 7) that has been serviced becomes the lowest priority level 7 and
becomes high in order toward IRO and then, IR7 and next IRn+l become the
highest priority level O. (Rotation Priority)
-475-
TOSHIBA INTEGRATED CIRCUIT
TMP82C59AP-2/AF-2
TECHNICAL DATA
For instance, when the interrupt
request IR4 is serviced as shown
in the figure at the right hand,
priority of each interrupt request input is updated.
Before ROTATION (highest prlrlty interrupt request IR4 is being serviced.)
IS7 IS6 ISS IS4 IS3 152 lSI ISO
ISR I 0 I 1 I 0 I 1 I 0 I 0 I 0 I 0 I
This mode specifies R : I, SL : 0
and EOI : 1 by OCW2 at the end of
serVlce. Further, in case of
Pri- I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0
_AEOI mode, when R : 1, 5L : 0
ority I
I
and EOI = 0 are specified by OCW2,
I
I
the internal flip-flop is set and
Lowest priority
Highest priority
the THP82C59A operates in this
mode. If R = 0, SL : 0 and EOI
After ROTATION (Interrupt request IR4
= 0 ar~ ~pecified by OCW2, this 15 being servied.)
mode is cleared.
IS7 IS6 ISS IS4 IS3 IS2 IS 1 ISO
(5)
SPECIFIC ROTATION
In the automatic rotation mode,
ISR I 0 I 1 I 0 I 0 I 0 I 0 I 0 I 0 I
priority of each interrupt request input is updated whenever
interrupt requests are serviced. Pri- 1~2~1~1~1~0~~7~1~6~1~5~~1~4~~1~3~1
Under this mode it is possible
ority
I
I
to change priority by specifying
Highestl
ILowest
an interrupt request input to be
priority
priority
set at the lowest priority by a
program. Priority is determined according to the rotation priority. In
this mode, Rand SL are set at 1 by OCW2 and interrupt request input that
is to be set at lowest priority at L2 to La is specified.
Priority can
be changed simultaneously with EOI command or independently regardless of
EOl command.
(6)
INTERRUPT MASK
Each interrupt request input can be masked individually by the interrupt
mask register (IMR). Content of IMR can be specified by OCWI.
(7)
SPECIAL MASK MODE
Normally when an interrupt service routine is being executed, lower
priority interrupt requests than the interrupt request being serviced are
ignored unless ISR bits are reset by EOI command.
This special mode is
used for an application in which an interrupt request of lower priority
is approved during the service. In this moue IMR also acts as the mask
for ISR.
That is , the TMP82C59A processes an interrupt request by
assuming that ISR bit and IRR bit corresponding to IMR bit set at "1"
have not been set. This mode is set by setting ESSM = 1 and SMM = 1 by
OCW3. Further, when ESSM = 1 and SMM = 0 are assigned by OCW3, this mode
is cleared to the normal mode. The IMR programming is made by OCWl.
-476-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
(8)
TMP82C59AP.2/AF·2
POLL COMMAND
This mode is used in a state where the internal
interrupt
enable
flip-flop of CPU is disabled and no interrupt is authorized.
The service
to the device is mad" by usinp the poll command.
The poll command
specifies P=1 in Oew3.
The mode becomes now the poll mode.
I-'hen the
read operation (RD=O, C~=O) IS made on thf> TMPS2C59A, the fa 11 owi nf'
output is made on the data bus:
D7
D6
I I
D5
D4
D3
D2
Dl
DO
- I Vi 2 IVI 1 I WO
I
I
I
- I I
1010 - W2
Binary code of
among interrupt
inputs.
I
There is an interrupt request to CPU when I = 1.
highest priority
requests to the
interrupt
interrupt
req ues t
request
The T~W82C59A interpretes RD signal as the interrupt acknowledge and when
Dl = 1 is output, sets corresponding ISR bit.
This poll mode is valid
f0r a period from WR (p = 1 in OCW3) to next RD (CS = 0).
Further, an
interrupt request to be serviced is determined at the time when the mode
is made to the poll mode and even when a new or hirh priority interrupt
request
is sent between WR and RD, it is not accepted.
(9)
READII\G SlATUS
CPU is capable of reading the, contents of 3 registers (IRR, ISR, IMR).
When the reading operation is made at AO = 0, the content of IRR or ISR
can be read out.
Selection of IRR and ISR is mClcie by OCW3.
\,'hen RR is
set at 1 and RIS at 0, IRR is assigned and when RR and RIS are set at I,
ISR is assigned.
This assigneQent is kept stored without necessity for performin~ at every
reading operation.
H1R is read when AO
1.
If the poll mode is
specified before the reading operation, the poll command has priority.
(10) EDGE TRIGGERD MODE/LEVEL TRIGGERD MODE
This mode is selected by LTHl of ICW1.
When LTIM is 0, the edge trig~ered mode is selected and interrupt request
is tripgered at the leading edge of the interrupt request signal and kept
continued by holding "H" level.
When LTUl is 1, the level triRf!ered mode
is selected and interrupt request is recognized by "H" level of t'le
interrupt request signal.
For both modes it is necessary to hold the
interrupt request input at "B" level by triggering it till the fast unA
signal is output from CPU.
If the interrupt request input is at "L"
level when INTA signal is output from CPU, the same operations as those
when interrupt requests are generated at IR7 are performed but ISR bits
Bre not set.
-477-
TOSHIBA INTEGRATED CIRCUIT
TMP82C59AP.2/AF-2
TECHNICAL DATA
(11) SPECIAL FULLY NESTED MODE
This mode is used to give priority to the interrupt request input for the
slave devices when they are cascade connected.
This mode is assigned to the master TMP82C59A when SFNM is 1 in lCW4.
With the exception of the following 2 points, this mode is identical- to
the fully nested mode.
[1]
[2]
Even when an interrupt request from a slave device is being serviced,
the master device accepts a higher priority interrupt request from the
same slave device without ignoring it.
(In the fully nested mode, a
higher priority interrupt request from the slave device that is now
being serviced is ignored and interrupt requests from a higher priority
slave device only are accpeted.)
When an interrupt request from a slave device is being serviced, it is
necessary to check by a software as to whether the interrupt request is
only one interrupt request from that slave device.
When the service ended, after the non-specific EOl is output to that
slave device, CPU has to check whether all lSR bits of that slave
device are "0".
If they are all "0", that slave has no interrupt
request being serviced and therefore, the non-specific EOl is output to
the master device to allow acceptance of interrupt request from the
lower priority slave devices.
Otherwise, the non-specific EOl must not be output to the master
device.
(12) BUFFERED MODE
This mode is to output an enable signal to a data bus buffer from the
SP/EN terminal when the data bus buffer is needed for the data bus on a
large system.
Under this mode, "L" level signal is output to the SP/EN
terminal whenever the data bus output of the TMP82C59A is enabled.
The
assingment of this mode is made by lCW4 simultaneously with the
assingment of the master/slave devices.
(13) CASCADE MODE
The TMP82C59A is able to process interrupt requests up to 64 levels by
one master and 8 slave devices.
The cascading is shown in Fig. 5. The master TMP82C59A selects the slave
devices by identi fication codes using 3 cascade lines.
lNT output of
each slave device is connected to the interrupt request inputs of the
master device.
Further, the identification codes corresponding to
respective connections are assigned for the slave devices by lCW3 •
..'hen interrupt request are generated at the interrupt request inputs of
the
slave
devices
and
accepted,
the master
device
outputs
the
identification code to the slave device at the first lNTA signal trailing
edge to output vector address or pointer.
This identification code is
kept maintained to the leading edge of the final lNTA signal.
Normally,
the master device outputs "L" level signal to all cascade line.
EOl
command must be output twice; to the master and second, to the slave
corresponding to the interrupt service.
Further, an address decoder is
required to activate to the CS input of eac~ TMP82C59A.
-478-
TOSHIBA INTEGRATED CIRCUIT
TMP82C59AP-2/AF-2
TECHNICAL DATA
ADDRESS BUS
16
CONTROL BUS
I
I
8
I~~
'J
AD
eAso
TMP82C59AP-2
SF/&.
r
GND
I
AD
es
I
INTU
CASO
CASO
CA81 I -
CASl
CAS.2 ~
CAS.2
TMP82C59AP-2
eASl
SLAVE
BUS
+3
B
3
8
es
r DATA
8
SLAVE,
CAS2
0
SP/EN
7
11111111
1
lI1tll!!
7
6
5 14,
.3
2
1
6
5
4
3
2
1
0
7654-3210
INTERRUPT REqUESTS
Fig. 5
CASCADI!';G
-479-
es
EF/EN-
t
Vee
3
AD
INT
TMP82C59AP-2
~.AST.ER
11.7 }/S M5 M4- M.3 )1.2 MI 1-W
! ln11 11
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
ABSOLUTt MAXIMUM
I
SYMBOL
TM P82 C59Ap·2/ AF·2
RAll~GS
I
ITEM
I
RATING
I
----------------------------------------------------------1--------------1
I
vcc
I VCC Supply Voltage (with respect to VSS (GND) I -0.5 to +7V I
1----------1------------------------------------------------1--------------1
I
VIK
I Input Voltare
l-o.Sto+Vcc+o.SI
1----------1------------------------------------------------1--------------1
I
PD
I Power Dissipation
I
250 mW
I
1----------1------------------------------------------------1--------------1
I
Tsol
I Soldering Tmeperature (Soldering Time 10 sec) I
260°C
I
1----------1------------------------------------------------1--------------1
1 Tstl'
I Storage Temperature
I-65°C to+lS0ocl
1----------1-------------------------------------------------1--------------1
I
Topr
I Operat ing Tempertature
I -40°C to 85°C I
DC CHARACTERISTICS
Ta=-40 to +85 0 C,VCC=5V+IO%,Vss(GND)=OV,
Unless otherwise noted~
I SYMBOL I
PARAMETER
ITEST CONlHTlOClIMII\.ITYP.1 MAX. IUl\lTl
1--------[---------------------------1--------------1----1----1-------1----1
I VIL
I Input Low Voltage
I
1-0.51 - I 0.8 I V I
1--------1---------------------------1--------------1----1----1-------1----1
I VIH
I Input Hi"h Voltage
I
I 2.21 - IVCC+0.51 V 1
1--------1---------------------------1--------------1----1----1-------1----1
I VOL
1 Output LO" Voltage
1 10L = 2.2mA I - I - I 0.45 I V I
1--------1---------------------------1--------------1----1----1-------1----1
I VOHI I Output High Voltage
I 10H" -400uAI 2.41 - I
I V I
1--------1---------------------------1--------------1----1----1-------1----1
I VOH2 I Output High Voltage
1 10H = -100uAlvcc 1 - 1
[V I
I
I
I
1-0.81
I
1
1
1--------1---------------------------1--------------1----1----1-------1----1
I ILl
I Input Leak Current
1 OV<
<:
1524±025
::;;
'"on
II
U
.of-
0 1
11025-005
Note)
Each lead pitch is 2.S4mm, and all the leads are located within +O.2Smm
from their thporetical position with respect to No.1 and No.28 leads.
-485-
TOSHIBA INTEGRATED CIRCUIT
TMP82 C59AP-2/AF-2
TECHNICAL DATA
EXT~R~AL
DIM~NbIO~
Vl~W
44 pins MINI FLATPACKAGc
Unit in mm
lrti
035
08PITCH
n-------------------,-
14,0±O.1
( 17,6±03)
1~5
j
..1/\
><«
;:;.
MARK
(05)
~_L
(12±O2)
tf)
l';
N
1
U1TUUU 1111]1 n IIIII
~~
~
N
~
~
15.2± 0.3
-486-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8259AP
TOSHIBA MOS TYPE DEGITAL
INTEGRATED CIRCUIT
Silicon Monolithic N-Channel Silicon Gate MOS
TMP8259AP
PROGRAMMABLE INTERRUPT CONTROLLER
GENERAL DESCRIPTION
The TMP8259AP is a programmable interrupt controller. It handles up to eight
vectored priority interrupts for the CPU.
It is cascadable for up to 64
vectored priority interrupts without additional circuitry.
FEATURES
o
o
o
o
o
Eight Level Priority Controller.
Expandable to 64 Level.
Interrupt Modes, Interrupt Mask, Vectored Address Programmable.
Single +5V Power Supply.
8085A, 8086 Microcomputer System Compatible.
PIN CONNECTIONS (TOP VIEW)
TMP8259AP
Cs
vcc
WR
AD
ill
TIiTA
D7
D6
D5
D4
D3
D2
Dl
DO
CASO
CASI
VSS(OND)
IR7
IR6
IR5
IR4
IR3
IR2
IRI
IRO
INT
SP/EN
CAS2
-487-
TOSHIBA INTEGRATED CIRCUIT
TIP8258AP
TECHNICAL DATA
PIN NAMES AND PIN DESCRIPTION
1 Pin Name 1 Input/Output 1
Function
1
1----------1--------------1-------------------------------------------------1
1
1
1 Chip Select Input. A low on this pin enables 1
1
cs
1
Input
1 RD and WR communication between the CPU and
l i t h e 8259AP. INTA functions are independent of
CS.
1
1
1
1
1
1
1
1----------1--------------1--------------------------------------------------1
1
1
1 Write Control Input. A low on this pin when CS 1
1
WR
1
1
Input
1
1 is low enables the 8259AP
1 words from CPU.
to accept command
1
1
1----------1--------------1-------------------------------------------------1
I
1 Read Control Input. A low on this pin when CS 1
1
1
RD
1
Input
1 is low enables the 8259AP to release status
1
1
1
1 onto the data bus for the CPU.
1
1----------1--------------1-------------------------------------------------1
1
1
1
1 Bidirectional Data Bus. Command status and
1 DO to D7 1 Input/Output 1 interrupt-vector information is transferred via 1
1
1
1
1 this bus.
1----------1--------------1-------------------------------------------------1
1
1
1 Cascade Lines. The CAS lines form a private
1
1 CASO to 1 Input/Output 1 8259AP bus to control a mUltiple 8259AP
1
1
CAS2
1
1 structure. These pins are outputs for a master 1
1 8259AP and inputs for a slave 8259AP.
1
1
1
lINT
1
1
Output
1 whenever a valid interrupt request is asserted. 1
1
1 I t is used to interrupt the CPU. It is conect- 1
l i e d to CPU I S interrupt pin.
1
1----------1--------------1-------------------------------------------------1
1
1
1 Slave Program/Enable Buffer. This is a dual
1
1
1
1 function pin. When in the buffered mode it can 1
1 SP/EN 1 Input/Output 1 be used as on Output to control buffer trans- 1
1
1
1 ceivers (EN). \\'hen not in the buffered mode it 1
1
1
1
1 is used as an input to des~na te a master
1
1
1
1 8259AP (SP=l) or a slave (SP=O).
1----------1--------------1-------------------------------------------------1
1
1
1 Interrupt Request Output. This pin goes high 1
1
1----------1--------------1-------------------------------------------------1
1
1
1
1
1
IRO to
IR7
1
1
Input
1
1
1 Interrupt Request Inputs. An interrupt request
1 is executed by raising an IR input (low to
1 high), and holding it high until it is acknowledged (Edge Triggered Mode), or just by a high
1 level on a IR input (Level Triggered Mode).
1
1
1
1
1
1
1
1----------1--------------1-------------------------------------------------1
1
1
1
1
1
ffiA
1
1
1
Input
1 Interrupt Acknowledge Input. This pin is used
1 to enable 8259AP interrupt-vector data onto the
1 data bus by a sequence of interrupt acknowledge
1 pulses issued by the CPU.
-488-
1
1
1
1
TOSHIBA INTEGRATED CIRCUIT
TIP8259AP
TECHNICAL DATA
1 Pin Name I Input/Output 1
Function
1
1----------1--------------1-------------------------------------------------1
1
1
1 AD Address Line. This pin acts in conjunction 1
1
1
1 with the CS, WR, and RD pins. It is used by the 1
1
Input
1 8259AP to decipher various command words the CPU 1
1 AD
1
1
1 writes and status the CPU wishes to read. It 1
1
1
1 is typically connected to the CPU AO address
1
1
1
1 line.
1
1----------1--------------1-------------------------------------------------1
1 vcc 1
1 +5V Power Supply
1
1----------1--------------1-------------------------------------------------1
1 VSS 1
1 Ground
1
BLOCK DIAGRAM
D7-DO
Rii
ii'R
AO
Cs
CASO
CASI
CAS2
¢:::;:
DATA
BUS
BUFFER
READ/
WRITE
LOGIC
r-
"
INTERNAL
t
n~
J
In
l-
~
CONTROL LOGIC
IN
SERVICE ;-.. PRIORITY r'-r' RESOLVER "REG
(ISR)
l.}
CASCA!'E
BUFFER/'
COMPARATOR
I
,
~ -1
9
t
INT
IRO
IRl
IR2
IR3
INTERRUPT
RE(20
o S/EST
045
Z.0V~
POINT< 08
-
-492-
TOSHIBA INTEGRATED CIRCUIT
TMP8259AP
TECHNICAL DATA
TIMING WAVEFORMS
WRITE OPERATlON
'I'WLII'H
'I'AHWL
AO
'I'Dv\\'H
DO-D7
READ AND INTA OPERATION
'I'RLRH
AO
TRLDV
TAHDV
DO-D7
INTA SEQUENCE
IR
INT
DO-D?
- 0--
--------_
TeVlAL
CASO-CAS2
'I'CVllV
-493-
INTEGRATED CIRCUIT
TOSHIBA
TECHNICAL DATA
1MP8259AP
OTHER TIMING
:"
ffiA
~\......_--{ "''" ~"'--__ I
ViR
-494-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8259AP
EXTERNAL DIMENSION VIEW
28 pins PRASTIC DIP
Unit in nnn
15
~8
]
U
14
><
..:
::E
N
.;
!l eo MAX
1524±025
I
II
:';i
'"
::E
254±025
+01
11°25-005
H
0-15·
N
to
Note)
Each lead pitch is 2. 54nnn, and all the leads are located within ±O.25mm
from their theoretical position with respect to No.1 and No.28 leads.
-495-
INTEGRATED CIRCUIT
TOSHIBA
TECHNICAL DATA
1MP8259AP
-496-
TOSHIBA INTEGRATED CIRCUIT
TMP82C37 AP.5/AF-5
TECHNICAL DATA
TOSHIBA MOS TYPE DIGITAL INTEGRATED CIRCUIT
TMP82C37AP-5/TMP82C37AF-5
SILICON MONOLITHIC CMOS SILICON GATE
MULTI MODE DMA CONTROLLER
GENERAL DESCRIPTION
The TMP82C37AP-5/AF-5 (hereinafter referred to as TMP82C37A) is a
multimode direct memory access (DMA) controller. The TMP82C37A improves the
system function by directly transferring information between the system memory
Memory-to-Memory data transfer capability is also
and external devices.
provided.
The TMP82C37A is provided with versatile programmable control functions
in order to improve data throughput.
The TMP82C37A is used with an 8-bit address register connected
externally. The TMP82C37A has four bui It-in independent channels and it is
possible to expand channels through cascade connection.
There are three basic data transfer modes which are programmable by the
user.
Each channel is pro~mmable individually and autoinitialization is
possible by End of Process (EOP) signal.
Each channel has the maximum 64K capability for both address and word
count.
EOP signal is capable of terminating data transfer between DMA and
memories. EOP signal is useful for block search or verify or for terminating
erroneous service.
FEATURES
o Four independent DMA channels available
o Three transfer modes available; block, demand, and single transfer modes
o Independent auto initialize function p,rovided to each of all channels
o Memory-to-Memory transfer
o Address increment or decrement
o All DMA request disabled by disabling the master system
o Individual DMA request enable/disable control
o Unrestricted channel expansion by cascade connection
o End of Process (EOP) input for terminating transfer
o Software DMA Request
o Polarity control provided for DREQ signal and DACK signal
o Option for increasing transfer speed up to 2.5M word/sec
o Single +5V power supply
o Low power consumption
5 rnA TYP. ~5MHz
o Extend operating temperature
-40 C to +85 0 C
-497-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP82C37 AP-5/AF-5
PIN CONNECTIONS (TOP VIEW)
TMP82C37AP-S (DIP)
A7
A6
A5
A40
EOP
AS
A2
Al
AO
MEMR
MEMW
note
4
5
READY
HLDA
AllSTB
7
B
6
AEN
9
HR't
10 TMPB2CS7A
CS
VOO( +5V)
DBO
DBI
DB2
DBS
DB40
DAOKO
DACKI
DBb
DB5
D'B7
II
OLK
RESET
DAOK2
DACK3
DRE'tS
DRE't2
DRE't1
DRE'tO
(GND)V SS
22
21
Note) PIN 5 connected +SV or OPEN state
PIN CONNECTIONS (TOP VIEW)
TMP82C37AF-S(MFP)
[oP
A4
c=:::j
C==i
34
3\
OACKl
OB5
PBS
~\ c=:::I 36
~6
: 37
He
~7 =::::) 38
• Icvg 39
17
16
lOR ;===140
lOW c=:::j 41
15
NC~42
HfHR
HEHW
DB)
ICV •
VSS(GHDl
DREQO
14
13
;=:::] 43
'---l 44
12
ORE03
-E
u DDliUDU
NM_~W_~~O-
*)
ICV and NOTE (Pin 1, Pin 17 and Pin 39) must be connected with Vce or must
be OPEN
NC: No Connection
-498-
~
a
en
-
:E
DECREMENTER
EOP
RESET
TIS
t>l
....
0
n
:0;'
t:1
.....
III
JO
'1
CONTROL
.j:Io.
i3
MEMR
CO
CO
-(
....
MEMW"
-(
I
I
~
00
lOR
lOW
I--
CURRENT I CURRENT
ADDRESS I WORD
(16) I COUNT
:
(16)
t
•
I
-
•
ENCODER
HLDA
!IRQ.
DACKO-DACK3
ROTATING
,
PRIORITY
LOGIC
l
~
~
:I:
»
-4
()
»
r-
I--<
(8)
H
MASK
~
•
J
INTERNAL DATA BUS
..
i"
;~
VJ
r'v-
MODE
(4 x 6)
0
~
,
DBO-DB11
r . ....----
DBO-DB?
1
")
I/O
BUFFER"
~-..::::...::::::......
(4)
REQ,UEST
(4)
T
1
rT1
-4
CONTROL
COMMAND
:::::0
n
0
» n:::::0
» c:::
..-1-_...1.-_
READ
BUFFER
rT1
G)
<;
'--------.....--J1I
~
J
11
:z
-4
m
Z
~
«
~
COMMAND
WRITE
BUFFER
DREQ,0-DREQ,3
I
~~~~-tr------v
,
w
.....
>
PRIORITY
~
.)
OUTPUT
BUFFER
READ/WRITE
BUFFER
BASE
WORD
COUNT
(16)
t
~
II
A4-A?
1
READ BUFFER
BASE
:
ADDRESS I
(16)
:
K
J\U-A~
__________~~
I
TIMING
I
IA
()
..
ADSTB
III
...n
t~
I
1,/0
BUFFER
TEMPORARY
ADDRESS REGISTER
(16)
I-
AEN
I
0
~
_
I
rl
I=:!.
TEMPORARY COUNT
REGISTER(16)
~
..
READY
CLK
INCREMENTER
DECREMENTER
•
ISTATUSllr-T...
EM""::::O"(t>'- -
TAK1r__-+__
,FAC
TDCTR
TDCL
~--toH- J--
TDCTR
I
"TAFC
--1--4+-1-+--
-----------!J-----------~ ~----HH ~ ~--__4~1
I
TDCL
~
!DCm
TDCTW
'T.-/ ~ J~~r-__-ir:iJ
IN! E5P _ _ _ _ _ _-"-.JJ-___
<_FO_R_EX_T_E_ND_E_D_WR_I_T_El_ _
TErn
-t--t"-EXT EOP
f
- --
~------TDCL
-I-!-!--
" " " - - - - - - - - - -0--- - - ---
- - - - -
rHHT~_~T~_~_t-_-r~I~i' TAHR
DACK---------~I.r-------r-J~
READ
-I-;A~,;----"·
--
\ \\\\\\\\'\
Timing Diagram 3
10.LLLiiLLLI
Active Cycle
-518-
Iy
-1-1-~---
-------
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP82C37 AP.5/AF-5
CLK
ADSTB
AO-A7
Dl!O-DB7
INT EOP
EXT EOP
Timing Diagram 4
Memory-to-Memory Transfer
CLK
AO-A7
READY
Timing Diagram 5
Compressed Transfer
-519-
TOSHIBA INTEGRATED CIRCUIT
TMP82C31 AP-5/ AF·5
TECHNICAL DATA
CLK
WRITE
(FOR EXTENDED
WRITE)~
TRS
READY
Timing Diagram 6
Ready Timing
r -______________________________
Vce
RESET
---A-~---
~h~r-----------
TRSTD - \
~~
~
'=:~
Timing Diagram 7
,
Reset Timing
Note 1.
TIP. value is that when rated voltage is applied at Ta = 2S 0 C.
Note 2.
Test conditions;
a)
b)
c)
Unless otherwise specified, timing defining
signal voltages are;
Input
High level = 2.4V, Low level = 0.4SV
Output High level = 2. 2V, Low level = 0.8V
Input rising and fall ing times are below 20 ns.
Unless otherwise specified, 1 x TTL gate and
150 pF load are provided to output.
Note 3.
Normal write pulse width is TCY-lOO ns. Extension write pulse width
is 2TCY-IOO ns. Read pulse width is 2TCY-50 ns, and compressed read
pulse width is TCY-SO ns.
Note 4.
TDQ is measured at two different high levels.
TDQl = 2.2V, TDQ2 = 3.3V
Note 5.
It is necessary to keep DREQ active until DACK is received.
Note 6.
Both low active and high active
DACK.
-520-
level
are available
for DREQ and
TOSHIBA INTEGRATED CIRCUIT
TMP82C37 AP-5/ AF·5
TECHNICAL DATA
Note 7.
Output load of the data bus are provided with 1 x TTL gate and 15 pF
as the minimum val ue, and 1 x TTL ga te and 150 pF as the maximum
val ue.
Note 8.
400 ns are required for active read or write pulse recovery time at
time of program condition.
Note 9.
Signal READ and WRITE are lOR and MEMR for the DMA operations from
peripheral devices to the memory.
In the DMA~erations from the
memory to peripheral devices, they are MEMR and lOW.
Note 10. When N state wait is added at time of write to memory in the latter
half of memory-to-memory transfer, this parameter increases by N
(TCY) at a time.
-521-
TOSHIBA INTEGRATED CIRCUIT
TMP82C37 AP-5/AF-5
TECHNICAL DATA
EXTERNAL DIMENSION VIEW (Plastic Package)
Unit in
40
tmn
21
[::::::::::::::::::[1
~
1
15.2"± 0.25
,
"
'.
"'1.
""
t:
0.5±0.15
Note
2.54±0.25
0.25
~g~5
~~
Each pitch is 2.54mm, and all the leads are located within +0.25mm
from their theoretical positions with respect to No. 1 and -No. 40
leads.
-522-
TOSHIBA INTEGRATED CIRCUIT
TMP82C31 AP-5/ AF-5
TECHNICAL DATA
EXTERNAL DIMENSION VIEW (Mini Flat Package)
Unit in mm
~
II : I
OeFITe);
140±Ol
( 17.6±03)
J~5
rl
o
-to
'"
o
rl
,
J
7/\
K
«
;:<
llARK
-~I
1
~.2±
)
'"tO>
ITlTTlll I! I
1
(l.2±O~
(06 )
UUUU
03
-523-
-.;
i
1
~
N
...;
~
TOSHIBA INTEGRATED CIRCUIT
TMPl2G3l AP.5/AF-5
TECHNICAL DATA
Example of Application Circuit
The connecting method of the TMP82C37A and CPU is shown in Fig. 7.
The multimode DMA controller outputs a hold request whenever valid
DMA request is produced from peripheral device.
When CPU answers by the
hold acknowledge signal, the TMP82C37A receives the control right of the
address bus, data bus, and control bus.
In the first transfer, address
(the least significant 8 bits of the address bits and the most significant
8 bits on the data bus) is output.
-The content of the data bus is latched by the 8-bit latch
(TC74HC373P) to make the address bus complete.
After execution of the
first transfer', that latched data is updated only when carry or borrow is
produced on the least significant address byte.
When one TMP82C37A is used, four DMA channels are provided.
ADDRESS BUS
A~A15
1r
)
AS-A15
f----
I
HLDA
CPU
HOLD
AD A3
A4 A7
TMPB2C3'1A
HLDA
fiRQ.
~
0
J
CLOCK
RESET
Ilil~I~lg
1
MEMR
TC74HC373P
LE
AEN
AO-A15
BUSEN I---
OE
V
I
BBlT LATCH
ADSTB
CS
t-
to
I
to
I
~ ~
~ ~
.,'"
'"
I
0
A
4t4
1"""L
MEMW
ICiR
lOW
BOO
DBC-DB?
SYSTEM DATA BUS
I
Fig. 7
Basic System Connection Diagram
-524-
)
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP82C37 AP.5/AF-5
Fig. 8 shows the expansion method for number of DMA channels.
It is
possible to realize net 7 DMA channels by connecting the second TMP82C37A
to one of the DMA channels of the first TMP82C37A.
Thus, any channel
Two DMA chips commonly use the same 8- bi t la tch.
is used for expansion.
.'" .
~
.... - 0
t')
r-
t')
I
CD
"
~o
0:0
~'"
~
00:>
~6OJ
~
..--.......
"'"
0
"Ill
~
Po ....
~
~
r-
....0
....0
...
+'
+'
LV-OV
r-
Jl.OI
0
CD
. . . .r,;
..... j
0
I
I
CD
-<
Laaoaa
::Ii
....
....
....
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....
I-<
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:;! ....
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r:tI ~"'~t')
a:!
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I--'
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~
:0
III
..
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ii
~
Iil
-<
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CD
0
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Fig. 8
f----'
~
A'"'I=Ict!([l
r-iNt'J--
CD
Il.
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VG'lHo
>4 >4>1 >4
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I-< .l!Q!
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I-<
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~
f;l
Expansion of TMP82C37A
-525-
TOSHIBA INTEGRATED CIRCUIT
TM P8Z C37 AP-5/ AF-5
TECHNICAL DATA
-526-
TOSHIBA INTEGRATED CIRCUIT
TMP8237AP
TECHNICAL DATA
TOSHIBA MOS TYPE DIGITAL INTEGRATED CIRCUIT
SILICON MONOLITHIC
TMP8237AP
MULTI MODE DMA CONTROLLER
GENERAL DESCRIPTION
The TMP8237AP (hereinafter referred to as TMP8237A) is a multi-mode
direct memory access (DMA) controller.
The TMP8237A improves the system
function by directly transferring infonnation between the system memory and
external devices. Memory-to-memory data transfer is also possible.
The TMP8237A is provided with versatile programmable control functions in
order to improve data throughput.
The TMP8237A is used with an 8-bit address register connected externally.
The TMP8237A has four built-in independent channels and it is possible to
extend channels through cascade connection.
There are three basic data transfer modes which are programmable by the
user.
Each channel is programmable individually and auto initialization is
possible by End of Process (EOP) signal.
Each channel has the maximum 64K capability for both address and word
count.
EOP signal is capable of tenninating data transfer between DMAs and
memories. EOP signal is useful for block search or verify or for tenninating
erroneous servies.
FEATURES
o Four independent DMA channels available, each of which has the following
registers; mode countrol, current address, base address, current word
count, and base word count registers.
o Four' transfer modes available; block, demand, single word, and cascade
modes.
o Independent auto initialize function provided to each of all channels.
o Kemory-to-memory transfer
o Address increment or decrement
o All DMA request disabled by disabling the master system
o Individual DMA request eanble/disable control
o Unrestricted channel extension by cascade connection
o End of Process (EOP) input tenninal for terminating transfer.
o DMA request by software
o Polarity control provided for DREQ signal and DACK signal
o Option for increasing transfer speed up to 1.5M word/sec.
o Single +5V power supply
-527-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8231AP
Pin Connections
Pin Names
Address Bus
Data Bus
DMA Request
DHA Acknowledge
Chip Select
I/O Read
I/O Write
Nemor), Read
Hemory \irite
Ready
Hold Acknowledge
Address Strobe
Address Enable
Hold Request
clock
Reset
End of Process
+5V, GND
AO evA7
lOR
DBO ev DB7
DREQO '0 DREQ3
DACKO '0 DACK3
CS
lOR
lOW
HEHR
A7
2
JOW
lI.El.lli
MEMW
DOt.8
A6
3
A5
4
5
A4
EOP
REhDY
6
A3
HLDA
?
A2
lJJ8TE
8
9
AD
p,E~
Al
HRI;:
~!E~IW
Vce (+5V)
CS
READY
HLDA
ADSTB
AEN
HRQ
CLK
RESET
EOP
VCC, \'SS
DBO
CLI:
RESET _
DEI
DB2
DACK2
DB3
DACK3
DB4
DREi,3
DACKO
DACKl
DREQ,2
DREQI
DB5
DB6
DB7
DRlll,O
(OND)V SS
Note}
+5V connection or open state
1S
available.
Block Diagram
'Temporary count
Reglstar(16)
EOP_
RESET-
AEN_
Cont rO 1
Current
ADSTB_
I
CUrrent
!
lOR_
I
!
10V(-
DREQO-DREQ3~ ~~~~~;y
HLDA·- Rota t.} ng
HRQ--
~puc
--1J Comrnana
. I (81
H
mask 141
DACKO-DACK3.!.. Frionty
Rog'c
L-____-41 R~quest
(4)
I
~
~
«
0)
I
A4-A7
EQ~l I
~
,....,
i c7ln~)
(16)
lI.ElZW --<
AO-A3
j'.-----,I
Address: Ward
MEMR_
I/O
t--
Re~~~~te
TlIDlng
k
LrTl BUff~6T
Te::::~nter
Address Reg,star
(16)
j~====~~~~--==--j-..>-I---,1
C8'READYCLK_
~
Incren:.eD ter
Decremen'ter
Corr:.mand
Control
)
11
Read/
WrJte
Mode
(4 x 6)
-528-
lstat.usJlTempOrary
~
~)
J
'------...
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8237AP
OPERATIONAL DESCRIPTION
Description of I/O signals
o
vcc
+5V power supply
o
VSS
Ground
o
CLK (Clock, Input)
This input controls the internal operation and data transfer rate of
the TMP8237A.
o
CS (Chip Select, Input)
This input is low active and used to select the TMP8237A as an I/O
device during an I/O read or I/O write by the host CPU. If lOR or lOW
is toggeled following each transfer when a host CPU and the TMP8237A
are transferring data mutually, CS may be kept at LOW.
o
RESET (Reset, Input)
This input is asynchronous input to clear the command, status, request
In addition, this input is used to clear
and temporary registers.
First/Last flip-flops and set the mask register. Following the reset,
the TMP8237A is placed in the idle cycle.
o
READY (Ready, Input)
This input is used to extend the memory read and write pulses from the
TMP8237A in order to adapt to a slow memories or I/O peripheral
devices.
o
HLDA (Hold Acknowledge, Input)
By this signal, the TMP8237A knows
turned over from CPU.
that
the
system bus
control
is
o
DREQ O - DREQ 3 (DMA Request, Input)
DMA request signals are input from peripheral circuits. If priority is
fixed, the highest priority is given to DREQ O and the lowest priority
to DREQ3. Polarity of DREQ is programmable. DREQ becomes high active
by RESET.
o
DBa - DB7 (Data Bus, Input/Output)
The Data Bus lines are bidirectional three-state signals connected to
the system data bus. When CPU is in I/O read state, output is enabled
and contents of the registers (address, status, temporary and word
count) are output to CPU. When CPU is in I/O write sta~e, the data bus
serves as input and it becomes possible to program the control register
of the TMP8237A.
During the DMA cycle, high order 8 bits of address are output on
the data bus and latched by ADSTB signal externally.
During the
memory-to-memory transfer, the data of the source memory location are
loaded into the temporary register of the TMP8237A by the read operation and the contents of the temporary register are output to the
destination memory location by the write operation.
-529-
TOSHIBA INTEGRATED CIRCUIT
TMP8237AP
TECHNICAL DATA
o
o
lOR (1/0 Read, Input/Output)
1/0 read is a bidirectional, low active and 3-state signal.
During the
idle cycle, this signal serves as an input control signal used by CPU
to read the control registers of the TMP8237A.
During the active
cycle, this signal serves as an output control signal used by the
TMP8237A to access data from the peripheral circuit during the DMA read
and transfer.
lOW (I/O Write, Input/Output)
1/0 write is a bidirectional low active, 3-state signal.
During the
idle cycle, this signal serves as an input control signal used by CPU
to load the information to the TMP8237A.
During.the active cycle, this
signal served as an output control signal used by TMP8237A to load the
data to the peripheral.
For write to the TMP8237A by CPU, the leading
edge of the write signal (lOW) is required for every data transfer.
It
is not possible to write more than two data by toggling CS while
holding the lOW pin at low level.
o
EOP (End of Process, Input/Output)
EOP (End of Process) is a signal relative to end of DMA service, and is
a low active, bidirectional and open drain signal.
Wheri the channel
word count reaches zero, the TMP8237A outputs low pulse of EOP to
peripheral deives as the end signal.
In addition, it is also possible to pull EOP to the low level by
peripheral device in order to cause the end of process.
When EOP is received (internally or externally), the channel which
is presently active terminates the service, sets that TC bit of the
status register and resets that request bit.
If that channel is programmed for auto initialization, that
current register 1S updated from the base register.
In all other
cases, mask bit is set and the content of that register rema1ns
unchanged.
During the memory-to-memory transfer, EOP is output when TC of
channell is produced.
EOP is always used for channels with active
DACK and external EOP has no connection when DACK O - DACK 3 are all
inactive.
EOP is an open drain signal and therefore, requires an external
pull-up resistor.
o
AO to A3 (Address, Input/Output)
The low order 4 address lines are the bidirectional 3-state terminals.
In the idle cycle, these terminals serve as the input terminals and
used by CPU for write/read of the control register.
In the active
cycle, they serve as the output terminals and become low order 4 bits
of output address.
o
Au - A7 (Address, Output)
The high order address lines are 3-state output terminals.
terminals are enabled for the period of DMA service only.
o
These
HRQ (Hold Request, Output)
This is the hold request signal to CPU, and is used to request the
system bus control.
HRQ is output by the TMP8237A according to a
software request or unmasked DREQ.
-530-
TOSHIBA INTEGRATED CIRCUIT
TMP8237AP
TECHNICAL DATA
o
DACK Q - DACK 3 (DMA Acknowledge, Output)
The lDMA acknowledge lines indicate that channels are active.
On
ordinary systems, these are used for selecting peripherl devices. Only
one DACK becomes active but it does not become active unless DMA is
controlling the system bus.
Porarily of these lines is programmable.
When reset, they become low active.
o
AEN (Address Enable, Output)
Address Enable is a high active signal and used to enable output of the
external latch which holds high order bytes of address and to disable
the system bus during the DMA cycle.
During the DMA transfer, HLDA and AEN are used to disable all I/O
except programmed I/O. The TMP8237A disables CS input for DMA transfer
to prevent itself from being selected automatically.
o
ADSTB (Address Strobe, Output)
This signal is a strobe output to an external latch circuit and is used
to latch high order 8-bit address from DBa - DB 7 •
o
MEMR (Memory Read, Output)
This is a low active 3-state output used for transferring data from a
memory to a peripheral device or for data accessing from a selected
memory during the memory-to-memory transfer.
o
MEMW (Memory Write, Output)
This is a low active 3-state output used for transferring data from a
peripheral device to a memory or for writing data into a selected
memory during the memory-to-memory transfer.
FUNCTIONAL DESCRIPTION
o
DMA Operation
The TMP8237A has two operations; idle cycle and active cycle.
Each of
these cycles consists of several states.
On the TMP8237A, it is possible to consider 7 states each of which
consists of one clock cycle.
State I (sI) is an idle state.
This is
such a state as there is no valid DMA request pending. 51 is a program
condition state which is programmable by CPU.
State a (SO) is the first DMA service state. This is a state that
the TMP8237A made a hold request to CPU but not yet received the
acknowledge signal from CPU.
When the acknowledge signal is recieved
from CPU, the transfer is started.
Sl, S2, 53 and S4 are the DMA service state.
If much time is
required by the transfer, it is possible to insert the wait state (SW)
before S4 by READY input to the TMP8237A.
In the memory-to-memory transfer, in order to aSsure complete
transfer, read from the memory and write to the memory are required. 8
states are necessary for one transfer.
The first four states (Sl1,
512, 513 and 514) are read from the memory and the latter four state
(521, 522, S23 and S24) are write to the memory.
The temporary data register is used as an intermediate storage
area of memory bytes.
-531-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8237AP
o
Idle cycle
When DMA service is not requested by channels, the TMP8237A enters into
the idle cycle and is placed in SI state.
In order to check if the
channels request DMA service, the TMP8237A samples DREQ for every
clock.
The TMP8237A also samples CS to check if CPU is requesting read or
write of internal registers.
When CS is low and HLDA is also low, the
TMP8237A is placed in the program condition.
At th is time, CPU is able to change or check the content of any
internal register through read or write from that register.
Address lines AD - A3 are input signals and used for selecting a
register being read or wri tten.
lOR and lOW are used for selecting
read or write and decide read/write timing.
The internal flip-flop is used for generating address extension
bits according to number and size of internal registers.
(First/Last
Flip-flop)
This bit is used for deciding high or low order bytes of
16-bit address and word counter register.
The flip-flop is reset by the master clear or reset.
In addition,
this flip-flop also can be reset by an independent software command.
On a special software command, the execution in the TMP8237A program
condition is possible.
These commands are decoded as in the address
setting when both CS and lOW are active.
The data bus is not used for th is command.
This command is
available in two types; clear First/Last flip-flop and master clear.
o
Active cycle
When the TMP8237A is in the idle cycle and the channels are requesting
DMA service, the TMP8237A outputs HREQ to CPU and goes into the active
cyc Ie.
In this cyc le, the DMA service for anyone of 4 modes is
executed.
Single Transfer Mode:
In this mode, the TMP8237A performs a single byte transfer during each
HRQ/HLDA handshake.
When DREQ becomes active, HRQ becomes active.
After CPU responds by driving HLDA active, a single byte transfer will
take place. After the transfer HRQ becomes inactive, its word count is
decreased, and address is increased or decireased.
When word count
becomes zero, a terminal signal is generated and if the channels are
programmed, the auto initialization is made.
To execute the single byte transfer, it is necessary to hold DREQ
until DACK corresponding each DREQ becomes active.
If DREQ is
continuously active, HRQ becomes inactive following each transfer and
then, becomes active again, and the new single byte is executed
following the leading edge of HLDA.
On the 8085 system, one machine cycle can be executed during the
DMA transfer.
Block Transfer Mode:
In this mode the TMP8237A continues the transfer until terminal count
(TC) is generated or End of Process signal (EOP) is externally input.
Here, TC is produced when the word count becomes zero.
What is required for DREQ is to hold it in active state until DACK
becomes active.
Auto initialization (if so programmed) is taken place
at the end of DMA service.
-532-
TOSHIBA INTEGRATED CIRCUIT
TIP8237AP
TECHNICAL DATA
Demand Transfer Mode:
In this mode the TMP8237A continues the transfer when TC is produced or
EOP is input or until DREQ becomes inactive.
Thus, it is possible for
a device, which is requesting the DMA service, to suspend the transfer
by making DREQ inactive.
The service is resumed when DREQ is made
active again.
It is possible to read an intermediate value of address
and word count from the current address and current word count register
of the TMP 8237A while the system bus is returned to CPU during
execution of the DMA service.
The auto initialization is taken place following TC or EOP at the
end of D!1A service.
In order to perform a new DMA service following
the auto initialization, the active edge of DREQ is necessary.
Cascade Mode:
This mode is used when the TMP8237A is cascade connected for a simple
system extension.
HRQ and HLDA of the additional TMP8237A are
connected to DREQ and DACK of the first TMP8237A.
DMA request to the
TMP8237A which is added for the purpose of system extension is
authorized by the priority circuit of the first TMP8237A • .
If the priority is already decided, the D!1A request of additional
device must wait till the DMA acknowledge of first TMP8237A.
The
cascade channel of the first TMP8237A is used only for deciding
priority of the additional TMP8237A and therefore, the channel itself
does not output address nor control signal.
This is to prevent the
added device from colliding with output of the cascade channel. On the
TMP8237A, DACK answers DREQ.
However all other outputs except HRQ are
disabled.
The state of cascade connection is shown in Fig. 2.
In Fig. 2,
two levels of D!1A are formed.
To further extend the TMP8237A, it is
possible to add it to the second level using the remaining channel of
the first TMP8237A.
To further add another TMP8237A, the third level
can be formed by cascade connecting it to the second level.
2nd Level
Microprocessor
1st Level
1
1
1<_ _ 1
DREQ
1_ _>1 HRQ
DACK
1
1 HLDA
1
1 TMP8237A
1
1
DREQ
1 HRQ
DACK
1 HLDA
1
Initial
1
1 TMP8237A
1<_ _ 1
1_ _ >1 HRQ
1
1 HLDA
1
1
1
1<_ _ 1
1
>1 HRQ
1--1
HLDA'
1
Device
1 TMP8237A
1
Additional Device
Fig. 2
Example of Cascade Connection of TMP8237A
-533-
TOSHIBA INTEGRATED CIRCUIT
TMP8237AP
TECHNICAL DATA
o
Transfer format
3 different transfer format are available for 3 active transfer modes.
They are read, write and verify.
In the write transfer, data is
trans ferred from I/O dvice to memory by MEMW and lOR.
In the read
transfer, data is transferred from memory to I/O device by MEMR and
lOW.
The verify transfer is a temporary transfer. The TMP8237A perform
such operations as address generation for read or write transfer,
answer to EOP, etc.
However, memory or 1/0 control line does not
become active.
Memory-to-Memory Transfer:
The TMP8237A has the ability of block movement and 1S capable of
transferring data block from one memory address location to another
location.
When Bit CO of the command register is programmed at Logic
1, Channel 0 and 1 operate as the memory-to-memory transfer channels.
Channel 0 serves as a source address and Channel 1 as a destination
address, and the word count of Channell is used. The memory-to-memory
transfer is executed when software DMA requrest is set for Channel O.
The memory-to-memory transfer must use the block transfer mode.
When Channe l O i s programmed as a fixed source addres s, it is
possible to write single source words into a memory block.
When the TMP8237A is programmed for the memory-to-memory transfer,
Channel 0 and Channel 1 must be masked.
The same value as that is set
for Channel 1 must be set for the word count of Channel O.
During the
memory-to-memory transfer, DACK does not become active.
During
the memory-to-memory
transfer,
the
TMP8237A
answers
external EOP signal.
In the block search, the data comparator uses
this (EOP) input to terminate the DMA ser1ve when match is found.
The
memory-to-memory transfer is shown in Timing Diagram 4.
Auto Initialization:
When Bit 4 of the mode register is set to 1, the channels are set up
for the auto initialization.
During the auto initialization, data are
loaded into the current address and current word count registers from
the base address and base word count registers, respectively, following
EOP.
The base registers are loaded by CPU simultaneously with the
current registers and remain unchanged during the DMA service.
When the channels are under the auto initialization, mask bit is
not set by EOP.
Following the auto initialization, that channel 1S prepared to
execute the service without interposition of CPU.
Priority:
The TMP8237A has two types of priority as an option, which can be
selected by software.
The first type is the fixed priority.
Channel
priority is fixed by channel number.
The lowest priority is 3,
followed by 2, 1, and the highest priority is O.
The second type is the rotating type priority.
In th is type, an
accepted channels is then given with the lowest priority (See the
following diagram.).
On the rotating priority in the single chip DMA system, highest
priori ty of anyone channel comes a fter no more than three higher
priority services have occurred. This rotating priority preclued one
channel to occupy the system all the time.
-534-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
The highest
priority
The lowest
priority
TMP8237AP
1st Service
2nd Service
3rd Service
<--
<-<--
<--
D
1
2
3
Service
\~
1
Service
Req ue s t
\~
Service
2
The priority judging circuit selects a channel wi th the highest
priority requesting the DMA service for every active edge of HLDA
Once the channel starts the service, that operation will not be
suspended even when the service is demanded by another channel with
higher priority.
A channel with higher priority can get the control
right only after a channel with lower priority relinquished HRQ.
Whenever the control is transferred from a channel to another channel,
CPU gets the system bus control right.
This assures the leading edge
of HLDA which ~s used for selecting a channel with the highest
priority.
Shortening of Transfer Time:
In order to accomplish larger throughput allowed by system characteristics, the TMP8237A is capable of shortening the transfer time to 2
clock cycles.
As can be seen from Timing Diagram 3, State S3 is used
to extend readout pulse access time. When State S3 is removed, readout
pulse width becomes equal to write pulse width.
Then, the transfer
will consist of State 52 for changing address and State S4 for
executing read/write.
State 51 is produced when A8 to AIS are updated
(refer to Address Genera~ion).
Shortening of transfer time is shown in
Timing Diagram S.
Address Generation:
To reduce number of pins,
the TMP8237A has high order 8 bits
multiplexed with the data bus.
State Sl is used to output high order
address bits to the external latch. The trailing edge of AD5TB is used
to load address bits from the data line on the external latch circuit.
AEN is used to enable latch outputs from high impedance states.
Low
order address bits are ditectly output by the TMP8237A.
AD to A7 are connected to address buses.
Timing Diagram 3
the relationship among CLK, AEN, ADSTB, DBD to DB7 and AD to A7.
Addresses produced during the block and demand transfers
continuous.
In the transfer of much blocks and demands, the
external address latch is left.
This address data changes only
carry or borrow from A7 to AS is produced in the normal sequence.
save time and speed, on the TMP8237A, Sl state ~s executed only
update of AS to AIS rquiring the latch.
-535-
show
are
same
when
To
for
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TIP823lAP
Description of Registers
Register
Name
No. of Bit
Base address register
Base word count register
Current address register
Current word count register
Temporary address register
Temporary word count register
Status register
Command register
Temporary register
Mode register
Mask register
Request register
Fig. 3
16-bit
16-bit
16-bit
16-bit
16-bit
16- bi t
8-bit
8-bit
8-bit
6-bit
4-bit
4-bit
Quantity
4
4
4
4
1
1
1
1
1
4
1
1
Internal Register
Current Address Register:
Each channel has a 16-bit current address register.
This register
holds addresses that are used during the DMA transfer.
After each
trans fer, th is regis ter is automat ica lly incremented or decremented,
and intermediate address values are stored in the current address
register during the transfer. Write or read of this register is made
by CPU.
An original value is initialized again by the auto
initialization.
The auto initialization is taken place only after EOP.
Current Word Count Register:
Each channel has a 16-bit current word count register.
For this
register, number of words that is one less than that to be tranferred
must be programmed.
The word counter is decremented after each
transfer.
Intermediate values of word count are stored in this
register during the transfer. When the register value becomes zero, TC
is produced.
When this register is in the program condition, load or read is
made by CPU.
Following the end of DMA service, this register is
initialized to original values again by the auto initialization.
The auto initialization is taken place only when EOP is produced.
Be careful that the content of the word count register becomes FFFFH
following internally produced EOP.
Base Address Register, Base Word Count Register:
Each channel has a pair of registers; the base address register and
base word count register. These l6-bit registers store original values
of related current registers.
These registers are used to store
original values
of
current
registers
at
time
of
the
auto
initialization. Write to the base register is made at the same time of
write into 8-bit byte equivalent current registers during the
programming by CPU. Therefore, write into the current registers which
store intermediate values are made over these intermediate values. The
base register cannot be read out by CPU.
-536-
TOSHIBA INTEGRATED CIRCUIT
TMP8237AP
TECHNICAL DATA
Command Register:
This 8-bit register controls the operation of TMP8237A.
This command
re gister is programmed (clear or reset) by CPU when it is in the
program condition.
The charts presented below show the functions of
command bits. For address codes, refer to Fig. 4.
7
5
6
4
2
3
o
<---
:-0
I
1
Bit
Memory-to-memory transfer disable
Memory-to-memory transfer enable
_______ I 0 Channel 0 address hold disable
I 1 Channel 0 address hold enable
I_x
------ 1-0
1_1
1-0
_______________ 1 1
I_x
___________________ 1-1
1_0
1-0
_______________________ 1
1
I_x
Bit 0 = In case of 0
Controller enable
Controller disable
Ordinary timing
Timing shortening
Bit 0 = in case of 0
Fixed type priority
Rotating type priority
Normal write pulse
Extension write pulse
Bit 3 = in case of 1
1-0
--------------1_1
Sense of DREQ is high active.
Sense of DREQ lS low active.
________________________ 1-0
1_1
Sense of DACK is high act ive.
Sense of DACK lS low active.
Mode Register:
All channels have a 6-bit mode register, respectively.
This mode
register is written by CPU when it is in the program condition, and Bit
o and 1 decide which channel's mode register is to be written.
7
6
5
4
3
2
o
<---
Bit
100
101
110
Selection
Selection
Selection
Selection
III
100
101
110
III
lf5.x
of
of
of
of
channel
channel
channel
channel
0
J
2
3
Verify ,transfer
Write transfer (rio --) memory)
Read transfer (Memory --) rio)
Illegal
Bit 6, 7 = in case of 11
-537-
TOSHIBA INTEGRATED CIRCUIT
TMP8237AP
TECHNICAL DATA
- - - - - - - - 1-0
1_1
--------------------- 1-0
1_1
100
_____________________________ 101
110
III
Auto initialize disable
Auto initialize enable
Address increment
Address decrement
Demand mode
Single mode
Block mode
Cascade mode
Request Register:
The TMP8237A is capable of answering DMA service request by software
similar to DREQ.
Each channel has a single bit request register which
cannot be masked.
Further, priority is given by the priority encode
circuit.
Bit of each register is set or cleared by software .and further,
cleared by generation of TC or external EOP. All registers are cleared
by reset.
In order to set or reset bit, a proper form of data word ~s
loaded by software.
Address codes are shown ~n Fig. 4.
DMA service request by
software is accepted only when the channels are in the block mode.
In
the memory-to-memory trans fer, DMA service request by the software
command to Channel 0 only becomes valid.
7
6
5
x
4
3
2
o
<---
Bit
100
Channel 0
Channell
Channel 2
Channel 3
101
110
ill
______ 1-0
1_1
is
is
is
is
selected.
selected.
selected.
selected.
Reset of request bit
Set of request bit
Mask Register:
For each channel, mask bits are allocated to the mask register to
disable DREQ input.
If the auto initialization has not been programmed
for the channels, the channel corresponding to a mask bit is set when
EOP is produced.
Each bit of the 4- bit mask re gister is a Iso set or
cleared by the software command. All bits are also set by reset. This
will disable all DMA requests until the clear mask regi3ter command is
enabled.
Command addressing is shown in Fig. 4.
--538--
TOSHIBA INTEGRATED CIRCUIT
TMP8237AP
TECHNICAL DATA
7
5
6
4
2
3
o
x
<---
Bit
100
101
110
Selection
Selection
Selection
Selection
I.!)
I 0
I- 1
All four
command.
7
5
6
bits
4
of
the mask
o
of
of
of
of
mask
mask
mask
mask
bit
bit
bit
bit
of
of
of
of
channel O.
channell.
channel 2.
channel '3.
Clear of mask bit
Set of mask bit
register
can be written also by
a
single
<---
Bit
1-0
1_1
Clear of mask bit of channel O.
Set of mask bit of channel O.
i-O
----- I_I
Clear of mask bit of channell.
Set of mask bit of channell.
1-0
-------1_1
Clear of mask bit of channel 2.
Set of mask bit of channel 2.
1-0
----------1_1
Clear of mask bit of channel 3.
Set of mask bit of channel 3.
3
2
x
Status Register
This register is read out by CPU through the TMP8237A.
Status
information of the TMP8237A at
time of readout
is
included.
lnformat ion as to which channel reaches the terminal count (TC) and
which channel is pending the DMA request are included in this
information. Bits 0 to 3 are set every time when a channel reaches TC
including the auto initialization.
These bits are cleared by reset or when each status is read out.
bits 4 to 7 are always set when corresponding channels are requesting
the DMA service
7
6
5
4
3
2
0
<--1
1
1
1
1
1
1
1
Bit
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
-539-
0
1
2
3
0
1
2
3
reaches TC.
reaches Te.
reaches TC.
reaches TC.
request.
request.
request.
request.
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8237AP
Temporary Register:
This register is used for holding data during the memory-to-memory
transfer. A last word transferred following the end of tranfer is read
out by CPU that is in the program condition.
Unless cleared by reset,
this register contains the last word transferred during the preceding
memory-to-memory transfer.
Software Commands:
These commands are special software commands which are executed in the
program condition and do not depend upon the specified bit pattern on
the data bus. These commands are available in following two commands:
Clear
First/Last flip-flop
This command is executed prior to write or read
of address
information or word count information of the TMP8237A.
Furthermore,
this command is used when low order or high order 8 bits of register
are accessed.
Master Clear
This software command has the same effect as the hardwar~ reset. The
command,
status,
request,
temporary,
and
internal
First/Last
flip-flop registers are all cleared by this command, and the mask
register is set.
The TMP8237A enters into the idle cycle.
Clear Mask Register
This command clears all mask bits of four channels, enabling
acceptance of the DMA service requests.
Address codes of the software commands are shown in Fig. 4.
Signal
I
A3
)}-
I
1
1
1
1
1
1
1
1
1
1
I
1
1
Note)
A2
0
0
0
0
0
0
0
0
1
1
I
1
1
1
1
I
I
Operation
Al I AO I lOR
0 I 0 I 0
0 I 0 I I
0 I I I 0
0 I 1 I 1
1 I 0 I 0
1 I 0 I 1
1 I 1 I 1
1 I 1 I 1
0 I 0 I 0
0 I 0 I 1
0 I 1 I 0
0 I I I I
I I 0 I 0
I I 0 I 1
1 I 1 I 0
1 I I I 1
lOW
1
0
1
0
1
Read of status register
Write to command register
Write to request register
Bit set, reset of mask register
()
0
0
1
0
I
0
1
0
1
0
Write to mode register
Clear First/Last flip-flop
Read of temporary register
Master clear
Clear mask register
All bit wri te of mask register
The oblique lined codes denote illegal codes.
Fig. 4
Register and Function Addressing
-540-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
IChan-1
1 nell
\
\
Register
\
1
\
\
\ Base & Current
\ Address
1
\
TMP8237AP
(*): Internal F/L,F/F
Signal
1
1 Data Bus 1
IOperationl
1
1
1 \ 1 1 1(*)\
\
ICS\IOR\IOw\A3\A2\Al\AO\
\ DBO-DB7 \
\
Write
\
\
\
\
\
\
\
\
\
\ 0\
\ 0\
\ 0 \ 0\ 0\ 0\ 0\ 0 \ AO - A 7 \
\ 0 \ 0 \ 0 \ 0 \ 0 \ 0 \ AS - AlS \
\
\
\
\
\
\
\
\
\
\
\
\ Current Address
Read
\ 0\ 0 \ 1 \ 0\ 0\ 01 01 0 I AO - A 7 I
I 0 I
I O! 0 I 1 I 0 I 0 I b I 0 I 1 I AS - AlS I
I
I
I I
I
I
I I I I
I
I
I
I Base & Current
Write 101
lo101010111olwo-W71
I
I Address
101IoI0IOI011[llwS-WlSI
I
I
I I
I
I I I I I
I
I
Read
I 0 I 0 I 1 I 0 I 0 I 0 I 11 0 I WO - W 7 I
I
I Current Address
I
I
I
10101110101011111ws-WlSI
\-----1---------------------1---------1--1---1---1--1--1--1--1---1----------1
I
I Base & Current
I Write 101
1010101110101AO-A71
I
I Address
I
I 0I
I 0 I 0 I 0 I 11 0 I 0 I AS - AlS \
I
I
I
I I
I
I
I I I I
I
\
I Read
I 0 I 0 I 1 I 0 I 0 I 1: 0 I 0 I AO - A 7 I
\
\ Current Address
I
\
\
I 0 I 0 I 1 I O! 0 \ 11 0 I 1 I AS - AlS I
\
I I
I
\ \ I I I
I
I
I
I
I Write I 0 I
I 0 I 0 I 0 I 11 11 0 I wo - W 7 I
I
I Base [, Current
I
101
010101111111wS-WlSI
I
I Address
\
I
I
\ I
I
I I \ I
\
\
\ Read
I 0\ 0
1 \ 0 i 0 \ 1\ 1\ 0
wo - W 7 \
\
\ Current Address
\
\
\
\ 0 I 0 \ 1 \ 0 \ 0 \ 1\ 1\ 1 \ WS - WlS \
\-----\---------------------\---------\--\---1---\--\--1--\--\---\----------1
\
I Base [, Current
\ Write \ 0\ 1 \ 0 \ 0\ 1\ 01 0\ 0 \ AO - A 7 \
\
\ 0 I 1 I 0 I 0 \ 1\ 0 \ 0 \ 0 \ AS - AlS \
\
\ Address
I
I
\ \ \ \
I
I
\
\
\
I
\
I Current Address
\ Read
\ 0 \ 0 \ 1 \ 0 \ 11 0 I 0 I 0 I AO - A 7 \
\
I 2 \
\
\ 0 \ 0 \ 1 I 0 I 1 \ 0 I 0 i I I AS - A15 \
I
\ \ I I \
I
\
\
\
\
I I
\ Write \ 01 1 I 0 I 01 11 01 11 0 I wo - W 7 I
\
\ Base [, Current
\
I Address
I
I 0 I 1 I 0 I 0 I 11 0 I 1\ 1 I WS - WlS I
I
1
I
1 I
1
1 1 I I I
1
1
I Read
1010 I 1101 1101 110 I wo - W 7 1
1
1 Current Address
I
1
I
1 0 I 0 I 1 I 01 11 0 I 11 1 I ws - WlS I
1-----1---------------------1---------1--1---1---1--1--1--1--1---1----------1
I
1 Base [, Current
1 Write I 01 1 1 0 1 01 11 11 01 0 1 AO - A 7 1
1
1 0 I 1 1 0 I 0 I 11 11 o! 0 I AS - AlS I
1
1 Address
I
I
I
I I
I
I I
I I I
I
I
I
I Current Address
I Read
101011101111\010IAO-A71
I 3 I
I
1 01 0 I 1 1 0 I 11 11 0 I 1 1 AS - AlS 1
1
1
1
1 1
1
I 1 1 I 1
1
I
1
1 Base [, Current
1 Write I 01 1 1 0 1 01 II 11 II 0 I wo - W 7 1
1
10111010111111111wS-WlSI
1
I Address
I
1
I
I I
I
1 I 1 I 1
1
I
1
1 Current Address
1 Read
1 01 0 1 1 1 01 11 11 11 0 1 wo - W 7 1
I
1
1
I 01 0 1 1 I 01 II II II 1 I WS - WlS I
Fig. S
Word Count, Address Registers
-541-
TOSHIBA INTEGRATED CIRCUIT
TMP8237AP
TECHNICAL DATA
Programming
If HLDA of CPU is inactive it is possible to program the TMP8237A by
CPU even when HRQ is active.
However, it is necessary for CPU to take care that programming of
the TMP8237A and answer of HLDA are taken place simultaneously.
If requires care when the DMA service is requested to an unmasked
channel during the programming of the TMP8237A.
It is considered that an embarrassing trouble may be caused in
this case.
For instance, if CPU is going to rewrite the address register of
channel 2 and in addition, the TMP8237A is enabled and channel 2 is not
masked when channel 2 received a DMA request. The DMA service will be
started after one byte of the address register is written.
Such a
problem as exampled above can be taken place.
To avoid such problems as this, it is better to disable the
controller or mask unmasked channels before reprogramming any register.
It is better to enable the controller or clear the masking when
the programming is completed.
Example of Program Set (CH2)
Interrupt disable
DI
MCLR
Master clear
our
MVI
A, xxxxxxxxB
Command register set-up
OUT
CMND
MVI
A, xxxxxxlOB
MODE
Mode register set-up
OUT
MVI
A, 37H
CH2 Address Reg. (low order)
ADR2
OUT
MVI
A, 82H
CH2 Address Reg. (high order)
OUT
ADR2
MVI
A, 17H
CH2 Word count register (low order)
OUT
WeNT2
MVI
A, 95H
CH2 Word count register (high order)
WCNT2
OUT
MVI
A, OOOOOOIOB
CH2 Hask clear (s ingle bi r)
OUT
MSKB2
Interrupt enable
El
-542-
TOSHIBA INTEGRATED CIRCUIT
TMP8237AP
TECHNICAL DATA
ABSOLUTE MAXIMUM RATINGS
I SIGNAL I
ITEM
I
RATING
I UNIT I
1----------1------------------------------1------------------1--------1
I Tstg
I Storage Temperature
I
-65 to 150 I °c I
1----------1------------------------------1------------------1--------1
I Topr
I Operating Temperature
I
0 to 70 I °c I
1----------1------------------------------1------------------1--------1
I vcc
I Supply Voltage
I -0.5 to 7.0 I
V I
1----------1------------------------------1------------------1--------1
1 VIN
I Input Voltage
1 -0.5 to 7.0 I
V I
1----------1------------------------------1------------------1--------1
I PW
1 Power Dissipation
I
1.5
I
W I
DC CHARACTERISTICS
CTa = OOC to 70°C, vcc = 5V ± 5%, VSS = OV)
I SYMBOL 1
PARA!1ETER
1
CONDTION I MIN. 1 TYP. 1 MAX. I UNIT I
1--------1----------------------1--------------1-----1-----1-------1------1
I
I
I lOB = -200 A I 2.4 I
I
I
I
I VOR I Output Righ Voltage 1--------------1-----1-----1-------1 V I
I
I
I
I
I
I IOR = -100 A I 3.3 I
1
I
I
I
I
I
I (BRQ only) I
1--------1----------------------1--------------1-----1-----1-------1------1
I VOL 1 Output Low Voltage I IOL = 3.2rnA I
1
I 0.45 I V I
1--------1----------------------1--------------1-----1-----1-------1------1
I VIR 1 Input Righ Voltage I
1 2.2 I
IVCC+0.51 V I
1--------1----------------------1--------------1-----1-----1-------1------1
I VIL 1 Input Low Voltage
I
1-0.5 I
I 0.8 I V 1
1--------1----------------------1--------------1-----1-----1-------1------1
1 IIX 1 Input Load Current 1 VSS
ADSTB - 0 -->
TAHW
WRITE
1 -->
ADR hold time
CLK-O --> Delay time up to DACK effective
PARAMETER
0(51) --> AEN = 1
Delay time
1(51) --> AEN = 0
Delay time
1 -->
ADR floating
-->
-->
MIN.
I
READ or WRITE floating
DB floating
300
200
150
UNIT
ns
ns
ns
150
250
ns
ns
MAX.
1
ADR hold time
DB hold time
TCY-I00
30
ns
ns
1
1
1
TAK
TCY-50
250
ns
ns
250
ns
1
1
CLK=l --> Delay time up to EOP=l
CLK=l --> Delay time up to EOP=O
ns
250
CLK-l --> ADR stable time
250
ns
DB stabilit --> ADSTB = 0 Set-up time
100 I
ns
Clock High Level Time (Transition time :
ns
120 1
below 10 ns)
I
I
TCL
Clock Low Level Time (Transition time : I
ns
150 1
below 10 ns)
1
1
Clock Cycle Time
TCY
ns
1
320 1
(Note 3)1
1
270
ns
TDCL
CLK =
--> READ = 0 or WRITE = 0
1
1
-=.:::..::.:=---:-.=.::.:-.---=l Not e 3) 1
1 270
ns
TDCTR
CLK
--> Delay time up to READ = 1 I
1
200
(Note 3)1
1
ns
TDCTW
CLK
--> Delav time up to WRITE = 1 1
1
TDQl
(No te 4) 1_ _ _ _+1--,1~6:.::0~+-...,:n:.:.:s=-CLK
TDQ2
--> HRQ=l or 0 Delay time
1
1
250
ns
TASM
TASS
TCH
TEPS
EOP = 0 -->
CLK
o
1
set-up time
I
1
60
I
TEPW
TFAAB
EOP pulse width
CLK
1 -->
ADR enable
TFAC
TFADB
THS
CLK
CLK
HLDA =
-->
-->
-->
1
READ or WRITE enable
DB enable
CLK = 1 set-up time
300
TIDS
TODH
TODV
TQS
TRH
Input data -->
MEMR
=1
1
1
250
1
I
1
I
200
300
1
100
1
I
I
--> Output data hold time
I
(Note 10) 1
Output data stability --> HEMW = 1
1
DRE -Active --> CLK-O (SI,S4) set-u time I
READY = 0 hold time
CLK = 0 -->
I
MEMW = 1
-544-
1
ns
ns
ns
ns
ns
1
0
I
set-up time
1
1
1
I
-=..T.:;;ID:..:H:...--1-.::M.:;;EM:.:;R:.:-.=---=_-_-...,:>---=I:.:;nJ::p..::u:::-t da t a hoI d time
ns
1
1
f
ns
1
250
I
ns
1
20
I
ns
I
200
0
20
1
I
ns
ns
ns
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
ABBR.
TRS
TSTL
TSTT
IMP8237AP
PARAMETER
READY - 0
> CLK = 0 set-uE time
CLK = 1
De1ax time
> ADSTB = 1
CLK = 1 --> ADSTB = 0
Delay time
MIN.
100
200
140
UNIT
ns
ns
ns
MAX.
UNIT
MAX.
Program Condition (Idle Cycle) (Notes: 2, 8 and 9)
[Ta=OoC to 70°C, VCC=sV±s%, VSS=ovj
ABBR.
TAR
TAW
TCW
TDW
PARA.'1ETER
ADR Stability or CS = 0
ADR Stability
CS = 0
MMIN. \
--> READ = 0
WRITE
Data stability -) WRITE
READ = 1 --)
TRDE
READ = 0
50
-->
=
=
ns
\
\
--> WRITE = 1 set-up time
-->
TRA
\
200
\
ns
\
1 set-up time
200
\
ns
\
1 set-up time
200
o
ADR or CS hold time
(Note 7)
Data stabilitx
TRDF
TRSTD
READ = 1 --)
POWER ON --)
TRSTS
TRSTW
--)
Reset
First lOWR
Reset pulse width
TRW
READ
\
ns
1
1
1
ns
I
200
ns
100
ns
ns
I
DB floating
Reset - 0 set-up time
20
500
\
\
\
=0
2TCY \
300 \
ns
ns
\
TWA
TWC
WRITE
WRITE
pulse width
= 1 -->
=
1
-->
TWD
WRITE = 1 --)
TWWS
WRITE pulse width
TAD
Capacity
CS
=
300
ns
\
\
ADR hold time
CS
=1
20
ns
\
\
hold time
20
Data hold time
30
200
\
ns
1
\
ns
\
ns
I
I
0, address stability --)
Data stability access time
\
ns
300
\
(Ta=2soC, VCC=GND=OV)
I
PARAMETER
I TEST CONDITION I MIN. \ TYP. \ MAX. \ UNIT 1
\--------1---------------------\----------------1------1------\------1------\
1 CO
1 Output Capacitance 1
\
\
\ 8 \
1
\--------\---------------------\ fc = 1.0 MHz, 1------1------1------1 pF 1
1 SYMNOL
1
CI
\ Input Capacitance
\ Input = OV
1--------\---------------------1
1 CIa 1 I/O Capacitance
\
-545-
\
\
\
15
\
\
\
\
20
\
1------1------\------1
\
1
1
TOSHIBA INTEGRATED CIRCUIT
TMP8237AP
TECHNICAL DATA
Timing Diagram
1/,----I
TCW
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
1
I
TWC
i ~----------~Tww~s------------~iil 1 - I"
I
TAW
I
~--------~--------~I
AO-A3
()(>(X)(')()(
INPUT Vi.LID
I
lOR
XXX\JXxxt
I 'I
TDW
:.1
«:
::;
51.3MAX
o
15.24± 0.2 5
or5
~-~--------------------------------------
Z
0.5±0.15
H
2.54±0.25
0-15°
1.4±0.15
Note
Each pitch is 2.54mm, and all the leads are located within
+0.25mm
from their theoretical positions with respect to No. 1 and No. 40
leads.
-551-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8237AP
Example of Application Circuit
The connecting method of the TMP8237A and CPU is shown in Fig. 7
The multi-mode DMA controller outputs a hold request whenever valid
DMA request is produced from peripheral device.
When CPU answers by the
hold acknowledge signal, the TMP8237A receives the control right of the
address bus, data bus, and control bus.
In the first transfer, address
(low order 8 bi ts of the address bi ts and high order 8 bi ts on the data
bus) is output.
The content
of the data bus
is
latched by
the
8-bit
latch
CTC74HC373P) to make the address bus complete.
After execution of the
first transfer, that latched data is updated only when carry or borrow is
produced on the low order address byte.
When one TMP8237A is used, four DMA channels are provided.
)
Address Bus AO-Al5
1I
'"
I--
DE
y
TC74HC373P
I
LE
AE1
AO-J..15
AD-A3 A4-A7
BElT LATCH
.h.DSTB
CS
EUSEN I - HLDA
HOLD
TIlP8237A
,..
HLDA
HRQ,
,'"'" '" I~ I~~ 12 Is
1
'w"
0
CPU
CLOCK
RESET
Y.EIL'i
to
I
to
I
0
cff
i;;j
'"
~
c:: I;:;
p
4
y.EII.W
lOR
lOW
0
<:
p
t 41
1
J
Cont;rol BUB
DBO-DE7
Sye'tern Da "ta Bus
Fig. 7
A8-A15
Basic System Connection Diagram
-552-
TOSHIBA INTEGRATED CIRCUIT
TMP8237AP
TECHNICAL DATA
Fig. 8 shows the extension method for number of DMA channels.
It is
possible to realize net 7 DMA channels by connecting the second TMP8237A
to one of the DMA channels of the first TMP8237A.
Two DMA chips commonly use the same 8-bit latch.
Thus, any channel
is used for extension.
~~====================~~~
I
<
I
It
:i:
.,
It
It
...
'"
:a!
"
- t\i' t")4 >'l >'4:>-1
'"'"
~
I:;
..,
....<
-'
....
III
'"
..,I
t:>
-'
5l0 Ei..,
-'
......
~~
4
-NNt";)t"J~~
"'IIl<~ ....
:::>
0
0
t<:
IX>
0
IX>
-'
0
I~
:z;
.....
t: tito
'"'"It: It:.,
Extension of TMP8237A
-553-
INTEGRATED CIRCUIT
TOSHIBA
TECHNICAL DATA
TMP8237AP
-554-
TOSHIBA INTEGRATED CIRCUIT
TMP82C79P-2/F-2
TECHNICAL DATA
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT
TMP82C79P-2/TMP82C79F-2
SILICON MONOLITHIC CMOS SILICON GATE
PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE
GENERAL DESCRIPTION
The THP82C79P-2/F-2 (hereinafter referred to as TMP82C79) is a programmable
keyboard/display interface chip.
The keyboard portion can provide a scanned
interface to a 64-contact key matrix.
Also, the keyboard portion will
interface to an array of sensors or a strobed interface keyboard.
Key
depressions can be 2-key lockout or N-key rollover.
The display portion has
16 x 8 bits display RAM which can be organized into dual 16 x 4 bits.
Both
right entry and left entry display formats are possible.
FEATURES
o
o
o
o
o
o
°
°
o
Simultaneous Keyboard Display operation is possible.
Scanned Keyboard mode.
Scanned Sensor matrix mode.
Strobed Input Entry mode.
8-Character FIFO is built in.
2 Key Lockout or N-key Rollover with contact De-bounce is programmable.
16 x 8 bit Display RAM is built in.
Scan timing is programmable.
Extend operating temperature
-40°C to +8SoC.
PIN CONNECTION
~;;~~~:;:~
~~::~5;;~;;~;;~
~U)v.ov.oooc::>oooo
RL2
RL!l
CLK
IRQ.
RL4
RL5
RL6
RL'7
RESET
RD
Wi'(
DBD
DBI
DB2
DB:!
DB4
DB5
DB6
DB '7
Vss(OND)
vcc
RLI
RLO
CNTIVSTB
SHIFT
SL3
SL2
SLI
SLO
OUT BO
OUT BI
OUT B2
OUT B3
OUT AO
OUT Al
OUT A2
OUT A3
BD
M~_OcnlQ""~on_,...,
MMC?r?c-"NNNNNt'ooI
SHIFT
CNTl/S18
RlO
Rl1
34
35
36
22
21
20
19
18
wce
• lCV
Rl2
Rl3
TMP82C79F-2
17
16
1.
OUT A3
8'0
cs
AD
NC
lCV •
VSS(GND)
Ne
1(
DBI
DBS
ClK
IRQ
13
12
DB4
DB5
_NM_.nCQ_~~~::
; ~ ~ ~ ;t~l~ i ~ ~ i
~
Cs
AO
*
Pin 17 and Pin 39 must be connected to Vcc
or must be open.
NC: No connection
-555-
TOSHIBA INTEGRATED CIRCUIT
TMP82C79P-2/F-2
TECHNICAL DATA
BLOCK DIAGRAM
1'11'0/
CNTl/STB
KEYBOARD
DEBClUNCE
SHIFT
IHc<
RLO-7
SLO-3
TIMING
AND
CONTROL
CIRCUIT
DBO-7
RESET
CLK
I------'-.J, DISPLAY
OUTBO-3
OUTAO-3
1------r-~lcOUNTER
B.
PIN NAMES AND PIN DESCRIPTION
VSS (Power Supply)
Gound
VCC (Power Supply)
+5V during operation
DBO - DB7 (Input/Output)
Bidirectional Data Bus.
data Bus.
All data and commands are transferred via this
-556-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP82C79P.2/F-2
CLK (Input)
CLOCK from system used to generate internal timing.
RESET (Input)
A high si gna 1 on th is pin rese ts the TMP82C79.
TMP82C79 is placed in the following state.
(1)
(2)
After being reset
16 x 8 bit character display, left entry.
Encode scan keyboard, 2 key lockout, clock pre-scale
set to 31H.
value
the
is
CS (Input)
A low on this pin enables RD and WR communication between the CPU and the
TMP82C79.
AD (Input)
This input acts in conjunction with the CS, WR and RD pins.
a high on
this pin indicates the signals on data bus are interpreted as command or
status. A low indicates they are Data.
WR (Input)
A low on this pin when CS is low enables the TMP82C79 to accept command or
data from the CPU.
RD (Input)
A low on this pin when CS is low enables the TMP82C79 to send data to data
Bus.
IRQ (Output)
Interrupt request output.
In a keyboard mode, the interrupt line is high
when there is data in the FIFO/Sensor RAM.
The interrupt line goes low
with each FIFO/Sensor RAM read and returns high if there is still
information in the RAM.
In a sensor mode, interrupt line goes high
whenever a change in a sensor is detected.
SLO - SL3 (Output)
Scan lines which are used to scan the key switch or sensor matrix and the
display digits. These lines can be either encoded (1 of 16) or decoded (1
of 4).
RLO - RL7 (Input)
Return lines which are connected to the scan lines through the key or
sensor switches.
They have internal pull ups to keep them high until a
switch closure pulls one low.
They also serve as an 8-bit input in the
Strobed Input mode.
SHIFT (Input)
This input status is stored along with the key position on key closure in
the Scanned key board modes.
It has internal pullup to keep it high until
a switch closure pulls it low.
-557-
TOSHIBA INTEGRATED CIRCUIT
TMP82C7UP-2/F-2
TECHNICAL DATA
CNTL/5TB (Input)
For Keyboard modes this line is used as a control input and stored like
status on a key closure. The line is also the strobe line that enters the
data into FIFO in the Strobed Input mode (Rising Edge).
It has an
internal pullup to keep it high until a switch closure pulls it low.
OUTAO - OUTA3 (Output)
OUTBO - OUTB3 (Output)
These two ports are the outputs for the 16 x 4 display refresh registers.
The data from these outputs is synchronized to the scan lines (SLO - 5L3)
for multiplexed digit displays.
The two 4 bit ports may be blanked
independently. These two ports may also be considered as one 8-bit port.
BD (Output)
This output is used to blank the display during digit switching or by a
display blanking command.
FUNCTIONAL DESCRIPTION
[BLOCK DESCRIPTION]
1/0 Control and Data Bus Buffer
The I/O control section uses the
flow of data to and from various
enables the all data flow to and
information given by the CPU, is
CS
o
o
o
o
AO
0
0
1
1
X
RD
0
1
WR
1
0
1
X
1
0
0
X
CS, AD, RD and WR lines and controls the
internal registers and buffers. CS input
from the TMP82C79. The character of the
identified by AD.
Functions
Read Data
Write Data
Read Status word
Write Command word
High-impedance state
RD and WR decide the direction of data flow through the data bus buffer.
The data bus buffer is bidirectional buffer which is used for connecting
the internal bus and a system bus. When CS is high, the buffer is in"a
high impedance state.
Control Register, Timing Register and Timing Control Circuit
The keyboard and display modes and other operating conditions are
programmed by the CPU. These modes are latched at the rising edge of WR
when AO is high. The timing control contains the basic counter chains.
The first counter is the lIN pres caler that can be programmed to yield an
basic internal frequncy.
In case of 100kHz basic internal frequency, it
gives a 5.1 mS keyboard scan time and a 10.3 mS debounce time. The other
counters divide down the basic internal frequency to provide the proper
key scan, row scan, keyboard matrix scan and display Bcan times.
-558-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP82C79P.2/F-2
Scan Counter
Two modes are available for the scan counter.
In the encode mode, the
counter provides a binary count that must be externally decoded to provide
the scan lines for the key board and display.
In the decode mode, the
scan counter decodes the least significant 2 bits internally and provides
a decoded 1 of 4 scan.
It is necessary to pay attention on the fact.that
only first 4 characters in the Display RAM are displayed.
Return Buffer and Keyboard Devounce Control circuit
The 8 return lines are latched by the return buffer.
In the Keyboard
mode, these lines are scanned to look for key closures in a row.
If the
debounce circuit detects a closed switch, it waits about 10 mS, and checks
if the switch remains closed. If it does 30, address of the switch in the
matrix is transferred to the FIFO along with the status of SHIFT and CNTL
lines.
In the scanned Sensor Matrix Modes, the contents of the return lines are
directly transferred to the corresponding row of the sensor RAM (FIFO)
each scan time.
In the Strobed Input Mode,
the contents of the return lines are
transferred to the FIFO on the rising edge of the CNTL/STB line pulse.
FIFO/Sensor RAM and FIFO/Senser RAM Status
The FIFO/Sensor RAM is a dual function RA.'1.
In the keyboard mode or In
the Strobe Input mode, this FIFO/Sensor RAM serves as a FIFO.
The FIFO
status shows whether the FIFO is empty or full and keeps track of the
number of characters in the FIFO.
In addition, there is a flag to show an
error in the case 'lhere too many reads or writes is recognized.
The FIFO
status can be read at CS = RD = 0, AO = 1. The FIFO status logic provides
an IRQ signal when the FIFO is not empty.
In the scanned sensor matrix
mode, the memory serves as a sensor RAM.
IRQ becomes high when a change
in the sensor is detected.
Display Address Registers and Display RAM
The display address registers hold the address of the word currently being
written or read by the CPU and the two 4 bit nibbles being displayed. The
Display RAM stores data for display outputs. The read/write addresses are
programmed by the CPU command.
They also can be programmed to autoincrement after read or write.
The Display RAM can be directry read out
by the CPU after mode and address is set.
The A and B nibbles of the
Display RAM are outputted to the Display Outputs A and B synchronously
with scan signals (5LO - SL3).
The A and B nibbles can be entered
independently or as one word by the CPU command.
-559-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP82C79P-2/F-2
[COMMAND DESCRIPTION]
Keyboard/Display Mode Set
I
I
I
I
I I
D7
D6
DS
D4
D3
D2
o
o
o
D
D
K
DO
K
I
I I
I I I
Display Mode
10101 8 x 8 bit character display - I
i
I I I Left entry
*10111 16 x 8 bit character display -i
I I I Left entry
I
11101 8 x 8 bit character display - I
I I I Right entry
I
11111 16 x 8 bit character display -I
I I I Right entry
I
*
D1
Default after Reset
*1010101 Encoded Scan Keyboard I I I I 2-Key Lockout
1010111 Decoded Scan Keyboard I I I I 2-Key Lockout
1011101 Encoded Scan Keyboard 1 I I I N-Key Rollover
1011111 Decoded Scan Keyboard I I I I N-Key Rollover
1110101 Encoded Scan Sensor Matrix
1110\11 Decoded Scan Sensor Matrix
1111101 Strobed Input, Encoded
I I I I Display Scan
1111111 Strobed Input, Decoded
I I I I Display Scan
Program Clock
D7
D6
o
o
DS
D4
D3
D2
Dl
DO
P
P
P
P
P
The TMP82C79 generates all timing and multiplexing signals by means of the
internal prescaler. The prescaler generates internal reference clocks by
dividing an external clock by a programmable value PPPPP. Any number of
ranging from 2 to 31 can be set as a prescaler value. When this value is
set to 0 or 1, it is interpreted to be 2. If the internal reference clock
is set to 100 kHz, it is possible to obtain S.lmS keyboard scan time and
10.3mS debounce time.
The value PPPPP is set to 31 after reset, but
cannot be changed by the Clear command.
Read FIFO/Sensor RAM
-560-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
07
06
o
05
04
o
Al
I
TMP82C79P-2/F-2
03
02
01
00
X
A
A
A
X=don't ca re
If this command is written, the subsequent data reads are set up for the
FIFO/Sensor RA"I.
Auto-increment flag (AI) and the RAM address bi ts AAA
are valid only in Senser Matrix Mode.
The address bits AAA select one of
the 8 rows of the Sensor RAM.
If Al = 1, the RAM address is incremented
after each successive read. The Auto-incremented flag does not affect the
auto-increment of the Oisplay RAM.
Read Display RAM
07
06
o
05
D4
1
Al
I
D3
02
01
DO
A
A
A
A
If this command is written, the subsequent data reads are set up
Display RAM.
The address bits AAAA select one of the 16 rows
Display RAM.
If Al = 1, the address is incremented after each
write to the Display RAM.
Since the same counter is used for both
and writing, this command sets the next read or write address
sense of the Auto-increment for both operation.
for the
of the
read or
reading
and the
Write Display RAM
D7
D6
05
04
1
o
o
Al
I
03
D2
D1
00
A
A
A
A
If this command is written, the subsequent data writes are set up for the
Display RAM. Note that writing this command does not switch the source of
the subsequent data reads.
The address register of the Display RAM is
same for read/write operations.
The addressing and Auto-increment
function are identical to those for the Read Oispaly RAM.
Display Write Inhibit/Blanking
D7
06
o
D5
D4
x I
D3
IWA
D2
I
IWB
-561-
01
I
BLA
00
I
BLB
I
X"don't care
TOSHIBA INTEGRATED CIRCUIT
TMP82C79P.2/F-2
TECHNICAL DATA
The IWA or IWB bit can be used to mask A nibble or B nibble for entering
the Display data independently. The BLA or BLB flag is available for the
nibble A or B to blank the display. In the case where the Display Outputs
are used as separate 4-bit display ports, the IWA or IWB bit is useful so
as not to affect the other display port when the CPU writes a word to the
display RAM.
The BLA or BLB bit is used for blanking the di.splay
independently without giving any affect to the other 4-bit display port.
The blank code is determined by the last Clear command that has been
·programmed after reset. If the Display Output is used as an 8-bi t port,
it is necessary to set both BLA and BLB bits for blnaking the display.
then BD signal becomes low.
D7
D5
D5
D4
D3
D2
Dl
DO
A3
A2
Al
AD
B3
B2
Bl
BO
Correspondence between Display Output and Data Bus
Clear
D7
D6
1
D5
D4
D3
D2
Dl
DO
o
CD I
CD I
CD I
CF I
CA I
The CD bits are used to clear all rows of the Display RAM to the following
code shown below.
(D4)
CD
1
1
1
0
I
(D3)
CD
0
1
1
X
(D2)
CD
X
0
1
X
All Zeros (X - Don't Care)
All Rex 20R (0010 0000)
A11 Ones
not clear display if CA '"' 0
Enable clear display when CD '"' 1 (or by CA = 1)
While the Display RAM is being cleared, it may not write to the Display
RAM. The MSB bit of the FIFO status word is set during this time. If the
CF bit is set to "1", the FIFO status is cleared and the interrupt request
output (IRQ) is reset. Also, the Senser RAM pointer is set to the row O.
The CA bit has the combined effect of the CD bi t and CF bit. I t enables
clear display code to the Display RAl:1 and also clears the FIFO status.
Furthermore, it re-synchronizes the internal timing chains.
-562-
TOSHIBA INTEGRATED CIRCUIT
TMP8!C79P.!/F-!
TECHNICAL DATA
END Interrupt/Error Mode Set
D6
D7
D5
I
D4
D3
D2
D1
DO
E
x
x
x
x
X: don't care
-In the Sensor Matrix mode, this command loweres the IRQ line and enables
writing to the sensor RAM.
This means that a write to the Sensor RAM is
inhibited when IRQ line is high. If the E bit is set to "1", the S/E bit
of the FIFO status becomes "I" when anyone of the sensor switches is
closed. If E = 0, the S/E bit is always "0". In the N-Key Rollover mode,
if the E bit is programmed to "1". the Special Error mode will be
resulted.
FIFO status
D6
D7
Du
I
S/E
I
D5
D4
D3
D2
D1
DO
0
u
F
N
N
N
X: don't care
Number of characters in FIFO
FIFO Full
Error-Under run
Error-Over run
Sensor Closure/Error Flag for
Multiple Closures
Display unavailable
Du
indicates that the Display RAM was
Display or Clear All command has
operation.
S/E
In a Sensor Matrix mode, if the E bit of END Interrupt/Error Mode Set
is programmed to "0", this S/E bit is set to indicate that at least
one sensor closure indication is contained in the Sensor RAM.
In Special Error Mode, this S/E bit is showing the error flag and
serves as an indication to whether a simultaneous multiple closure
error has occurred.
0
indicates that the entry of another charac tel' into
attempted.
U
indicates that the CPU tried to read an empty }<'IFO.
F
indicates that the FIFO is full of the eight characters.
NNN
indicates number of characters in the FIFO when in the Keyboard Mode
or in the Strobe Input Mode.
-563-
unavailable because
not completed its
II
a Clear
clearing
full FIFO was
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP82C79P.2/F·2
[INTERFACE WITH KEYBOARD)
Scanned Keyboard, 2-key LOCKOUT
In this mode, if one key only is kept depressed during one debounce cycle
(2 times of the key scan cycle), the key is recognized.
When a key is
depressed, the deb ounce logic is set and the other depressed keys are
checked during the next two scan cycle. If none are encountered, it is a
.single key depression and the key position is entered into the FIFO along
wi th the s ta tus of CNTL and SHIFT 1 ines.
If another depres sed key are
encountered, operates as follows.
KEY 1
y
y
y
KEY 2
y
KEY :3
Fig. 1
KEY 1
----y
KEY !l
1
CYCLE
~.------,~
y
y
y
Example of a case where a first depressed
key is continuously kept to the last
Y
KEY 2
y DEBOUN~E
y
y
Y
Y
y
Y
U
Y
y
Debounce logic is set
1
Fig. 2
Ent!"fe
0
I
I
2nd
entry
16th
entry
15
,
Display RAM
Address
5th
entry
3
I
6
6th
entry
I
11th
entry
-568-
I
0
5
1
2
3
4
5
9
101 3
3
4
5
6
9
101
111
4
I
8
I
5
I
2
2
6
4
I
0
7
2
10th
entry
4
7
I
I
I
I
6
7
4
5
7
0
5
6
3
I
6
7
I
1
2
0
I
I
7
I
8
I
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP82C79P-2/F-2
ABSOLUTE MAXIMUM RATINGS
I SYMBOL I
ITEM
I
RATING
I
1--------1---------------------------------------------I---------------------l
I vcc
I VCC Supply Voltage (with respect to VSS(GND)I
-O.SV to +7.0V
I
1--------1---------------------------------------------1---------------------1
I VIN
I Input Voltage (with respect to VSS (GND)
I -O.SV to VCC +O.SV I
1--------1---------------------------------------------1---------------------1
I VOUT -I Output Voltage (with respect to VSS (GND)
I -O.SV to vcc +O.SV I
1--------1---------------------------------------------1---------------------1
I PD
I Power Dissipation
I
250 mW
I
1--------1---------------------------------------------1---------------------1
I Tsol I Soldering Temperature(soldering time 10 sec)1
260°C
I
1--------1---------------------------------------------1---------------------1
I Tstg I Storage Temperature
I -65°C to +lS0oC
I
1--------1---------------------------------------------1---------------------1
I Topr I Operating Temperature
I -40°C to +8S o C
I
D.C. ELECTRICAL CHARACTERISTICS
(Ta=-40 to +8SoC, VCC=VSS (GND)=OV)
SYMBOL I1______________________________
PARAMETER
, I ___________
CONDITION 1----1----1-------1---IMIN. ITYP. I MAX. I UNIT
1I ________
1_1
I VILl I Input Low Voltage (RLO - RL7)' I
l-o.sl
I 1.4 I V
1--------1--------------------------------1-----------1----1----1-------1---I VIL2 I Input Low Voltage (Others)
I
1-0.51
I 0.8 I V
1--------1--------------------------------1-----------1----1----1-------1---I VIH} I Input High Voltage (RLO - RL7) I
12.21
Ivcc+o.sl V
1--------1--------------------------------1-----------1----1----1-------1---I VIH2 I Input High Voltage (Others)
I
I 2.21
Ivcc+o.sl V
1--------1--------------------------------1-----------1----1----1-------1---I VOL
I Output Low Voltage
I IOL=2.2rnA I
I
I 0.45 I V
1--------1--------------------------------1-----------1----1----1-------1---I VORl I Output High Voltage
I IOH=-400uAl 2.41
I
I V
1--------1--------------------------------1-----------1----1----1-------1----1
I VOH2 I Output High Voltage
I IOH=-lOOuAl vcci
I
I V
I
I
I
1-0.81
I
I
1--------1--------------------------------1-----------1----1----1-------1---I
I
I VIN=VCC
I
I
I +10 I
I
I Input lLeak Current
1-----------1----1----1-------1
I IIL1 I
I VIN=2.4V I -101 -301
I uA
I
I (SHIFT, CNTL, RLO - RL7)
1-----------1----1----1-------1
I
I
I VIN=OV
I
I
I -100 I
1--------1--------------------------------1-----------1----1----1-------1---I IIL2 I Input Leak Current (Others)
10V--------------Read-operation
AO,CS
~
X
twv;
tAW
tWA
V
1\
tDl\'
I\.
~
X.
X-
DBO-DB7
twCY
Wri te-opera tion
I
CLK
I
tOWL
l
------~~~--~~--~~--------~
'----
Clock input
-571-
TOSHIBA INTEGRATED CIRCUIT
TeCHNICAL DATA
TMP82C79P.2/F-2
OUTLINE DRAWING (40Pins Plastic Package)
Unit in =
O.S±O 1S
14
Note
2 S4±02S
01 S
Each lead pitch is 2.54=, and all the leads are located within
+0.25mm from thei r theoritical positions wi th respect to No.1 and
No.40 leads.
-572-
TOSHIBA INTEGRATED CIRCUIT
TMP82C7SP-2/F-2
TECHNICAL DATA
OUTLINE DRAWING (44Pins Mini Flat Package)
Uni t 1n nun
rIIi!
08PJTCH
M---------------------~
14 0:1 OJ
( 1 7.6± 0 3)
1~5
".;
.(
:>i
MARK
J,
J
( 12±02)
( 0.6 )
~I
"',..
'"
1
1
I
15.2±03
-573-
\
"\
t
1
~
~
~
TOSHIBA INTEGRATED CIRCUIT
TMP82C7SP-2/F-2
TECHNICAL DATA
EXAMPLE OF APPLICATION CIRCUIT
SHIFT
KEYBOARD
MATRIX
CONTROL
RETURN LINE
1
/
/
6 COLUMNS
BROWS
6
SHIFT CNTL RLO-7
V
IR~
Ii!
....
CD
;...
IX<
RiS
0
III
CD
<)
CONTROL
RESET
0
IX<
0..
0
IX<
<)
H
WR
ADDRESS
:>(
CLOCK
CS
AO
CLK
I
II.
P
DBO-7
DATA BUS
CD
Ii!
6
T
:0;
8
2
RD
WR
C
RESET
CS
9
7
4
SO-3
P
1
2
AO
CLK
BO-3
/
I
BD
3--+6 DECODER
}
3
1--7'
4-16 DECODER
I
(LSB 3 BI T)
1
AO-3
_V
4
rCA'"'' mR~' (D
15
3
4
2
5
6
3
15
2
0
1 17 1 18 1 ------- 115 1 16 1
4th entry 11
I2
3
4
6
3
I4
Right Entry
In Right Entry, the first entry is from the right-most position.
Display RAM does not correspond to the display position.
-587-
Address of the
TOSHIBA INTEGRATED CIRCUIT
TMP8279p·5
TECHNICAL DATA
+
2
1st
entry
12
3
2nd
entry
3
18th
entry
--
-
14
--
1
15
4
1
I--- ---
I
1
------
1
13
-----.
11 1 2 1
I
0
--------
0
1
t2
1
2
3
1 2 1
I
I
2nd
ent ry
15
1
2
2 1
31--~_-_-~~_1151161171
2
3
3 1 4
I ~~-_-_-_-_J
6
6
5
5
6
7
0
7
7
5
1 3
1 3
1 4
2
6
I, 4 I
6
I I
I
0
7
1
1
1 2 1
0
1
I
4
5 1 1 1 2
7
0
5 1 6 1 2
3
4
4
5
2
1
I2 I
2
I
2
3
4
3
4
5
1 31
6
I
3
1
I
5
6
2
1
1 12
0
1 8 1 9 1 10 1 3
3
-588-
1
1
0
1
4 15 1 6 1 7
7
0
11th
ent ry
J
0
0
11
3
6
10th
ent ry
5
I I I I
5
6th
entry
4
4
0
5th
entry
6
2 1
1
Right Entry from Address 5
with Auto-increment mode
4
161171181
5
1
4th
entry
15
4
3
3
0
4
1
Command wri tel
(10010101)
3rd
entry
15
3
2
1
3
1
2
1141151161
14
2
1
1st
entry
1
1
14
~
0
15
-
---------
0
17th
entry
-
1 -------- 1
3rd
en try
16 th
entry
--
Display RMI
Address
6 1 7 1
1 9 1 10 1 11 1 4 1 51
I
2
81
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8279P-5
ABSOLUTE MAXI MUt" RATINGS
snlBOL
RATING
ITHI
Vee
Vee Supply Voltage (with respect to CND (VSS»
VIN
Input Voltage (with respect to GND (VSS»
_._----
---
VOUT
Output Voltage (with respect to CND (VSS»
PD
Power Dissipation
Tso 1
Soldering Tempe rdt ure (soldering time 10 sec)
Tstg
Storage Temperature
Topr
Operat ing Temperature
D.C. ELECTRICAL CHARACTERISTICS
SYMBOL
-O.S\' to +7.0V
-0.5\' to +7.0V
-r-----
-O.SV to +7.0V
lH
260 0 e
-S 5 ° e to +lSOoe
oOe to 70°C
(Ta=O'" 70°C, Vec=5V±10%, VSS=OV)
PARAHETER
mN. T\,I'.
CONDITION
HAX.
UNIT
VILl
Input Low Voltage ( RL o"' RL 7)
-0. S
l.4
V
VIL 2
Input Low Voltage (Others)
-O.S
0.8
V
VIHI
Input HI gh Voltage ( RL O"' RL 7)
2.2
VIH 2
Input High Voltage (Others)
2.0
VOL
Output Low Voltage
TaL =2. 2mA
VOHl
Output High Voltage (I RQ)
IOW-IOOjJA
3.5
VOH2
Output High Voltage (Others)
IOII=-400lJA
2.4
Input Leak Current
VIN=VCC
IILl
(SHIFT, CNTL, RLO '" RL 7 )
VIN=(JV
IIL2
Input Leak Current (Others)
IOFL
Output Leak Curren t
ICC
Supply Current
V
V
0.45
V
V
V
+10
pA
-100
----
tIO
OV ~ VIN ~ VCC
liA
----
0.4SV;VOUT~VCC
no
pA
120
mA
INPUT CAPACITY
SYNBOL
CIN
eONDITlON
PARMIETER
Input Capacity
fc=IMllz lJnmf'3SUre(
PillS retu(neJ to
COUT
Output Capacity
VSS.
-589-
~II
N.
TYP.
~IAX.
UNIT
S
10
pF
10
20
pF
TOSHIBA INTEGRATED CIRCUIT
TMP8279P-5
TECHNICAL DATA
A.C. ELECTRICAL CHARACTERISITCS
SYMBOL
(Ta=O"- 70·C, VCC=5.0V±l0%, VSS=UV)
PARAMETER
TEST CONDITION HIN.
TYP.
MAX. UNIT
tAR
Address Set up Time (RN)
0
nS
tRA
Address Hold Time (ROt)
0
nS
tRR
RD Pulse IHdth
250
nS
tRD
Valid Data (ROt)
CL=150pF
150
nS
tAD
Address to Valid Data
CL=150pF
250
nS
tDF
Data Floating (RDt)
100
nS
tReY
Read Cycle Time
tAW
Address Set up Time
10
(WR~)
1
~S
0
nS
0
nS
----
tWA
Address Hold Time (WRt)
tlVW
WR Pulse IHdth
250
nS
tow
Data Set up Time (WRt)
150
nS
tWD
Data Hold Time (WRt)
0
nS
t0W
CLK Pulse Width
120
nS
tCY
Clock pe riod
320
nS
-590-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
AU,Cd
=><
TMP8279P-5
K
tj{~Y
tAR
tj{A
tRR
Y
\
~
tRlJ
tAD
DBli-DB?
---- ----------0
~---
---- - - - - ----
Read-operation
AD
,CS
=><
K
tww
tAW
tWA
I
\
V
tow
DBO-DB?
~
,X
K
Write-operation
I
CLK
Clock input
-591-
TOSHIBA INTEGRATED CIRCUIT
TMP8279P-5
TECHNICAL DATA
OUTLINE DRAWING
Unit in mm
40 39 38 37 36
~
3
4
~
,;
7
b
~
1U
11 I;. J.) J4 10 Jb 17 It;
1~
.iJ
f--_ _ _ _ _ _ _ _ _ _ ~_O_7_±_O_10_______ _
"'u
'"
o
rl
-H
o
-H
")
'"
(Notel)
~
o ~5± 0 1
1500-1780
;:';
P.
:0
CD
0
"''"
,..~
"''"
H
0~5TYP
Ob±Ol
Note:
1. This dimension is measured at the center of bening point of leads.
2. Each lead pitch is 2.54mm, and all the leads are located within
±O.2Smm from their theodtical positions with respect to No.1 and
No.40 leads.
-592-
TOSHIBA INTEGRATED CIRCUIT
TMP8279'-5
TECHNICAL DATA
EXA~PLE
OF APPLICATION CIRCUIT
SHIFT
KEYlJllAHlJ
CllNTHllL
MATHIX
H!!:TUHN [,IN!!:
-7
B COLUMNS
/
8 HOWS
ti
i!!i
....
IRQ.
,..'"
'"0::
T
M
IlBu--'l
DATA BUs
'"
[;l
RD
CJ
0
WR
0::
p.,
B
CONTROL
0
H!!:SET
...;:;;
CS
0::
CJ
....
H
,
Output strobe for the TMP8243P I/O exapnder
PIO-Pl7 (Input/Output) Port 1
8-bit quasi-bidirectional port
(Internal Pullup
50 kohm).
P20-P27 (Input/Output) Port 2
8-bit quasi-bidrectional port (Internal Pullup = 50 kohm).
P20-P23 Contain the four high order program counter bits during an
external program memory fetch and serve as a 4-bit I/O expander bus for
the TMP8243P.
DBO-DB7 (Input/Output, 3 State)
True bidirectional port which can be ~~itten or read synchronously using
the RD, WR strobes. The port can also be statically latched.
Contains
the 8 low order program counter bits during an external program memory
fetch, and receives the addressed instruction under the control of PSEN.
Also contains the address and data during an external RAM data store
instruction, under control of ALE, RD and WR.
TO
(Input/Output)
Input pin testable using the conditional transfer instructions JTO and
J~~O.
TO can be designated as a clock output using ENTO CLK instruction.
Tl
(Input)
Input pin testable using the JTI and JNTI instruction.
Can be designated
the event counter input using the timer/STRT CNT instruction.
INT
(Input)
External interrupt input.
Initiates an interrupt if interrupt is
enabled. Interrupt is disabled after a reset. Also testable with
conditional jump instruction.
(Active Low)
RD
(Output)
Output strobe activated during a Bus read.
Can be used to enable data
onto the Bus from an external device. Used as a Read Strobe to External
Data Memory (Active Low).
WR
(Output)
Output strobe during a Bus write (Active Low). Used as a Write Strobe to
External Data Memory.
-598-
TOSHIBA INTEGRATED CIRCUIT
TMPl048AJTMP8035A
TMfB049AJTMP8039A
TECHNICAL DATA
PIN CONNECTIONS (Top View)
TO
Vcc (+sV)
Tl
XTALI
XTAL2
P27
P26
P 2s
P24
P17
P16
PIS
PI4
RESET
SS
INT
EA
PSEN
\o,lR
P13
ALE
DBO
DBI
DB2
DB3
DB4
P12
Pll
PIa
VDD(+sV)
PROG
P23
P22
DB')
DB6
DB7
(OV)VSS
P 2I
P 20
r
......
~ ..... .....
V)<
<
N
U
V) ~ t-< t-< oU U ......
IV) ~ >< >< t-t-<
L!"\
rN
N
N
p.. p.. p..
'"
tb. '5' '<9;' '34 '2' ill 4.;. Iri3 a.t2 ~l 40
.. oJ
INT
EA
RD
PSEN
WR
NC
ALE
DBO
DBl
DB2
DB3
1- J
L.J
L. ..
a.. ..I
L.J
1.. ..
L.J
1.. ....
L.J
L-'
:-.
P24
L"'""
.....
""
F::
:It
;:s
"-"
u.n
~
.,...,
-,
l"_
~
.."
~
<'U
Li
."
~
.'"
--''''
~
~
~
I:;:
:~{
;~
;9'
2~ 2]~ C; ~ ~~ ~~ ~: ~;
....
L!"\
'"
0
0 0
~
~
~
r~
0
V)U
g;z
0
N
......
N
""
e;;
t.:l
N
N
N
p..p.. p.. p.. 0
~
p..
-599-
Pl7
Pl6
PIS
PH
NC
P13
Pl2
Pll
PIO
VDD
TOSHIBA INTEGRATED CIRCUIT
TMP8048AJTMP8035A
TMP8049AJTMP8039A
TECHNICAL DATA
BLOCK DIAGRAM
Oscillation
Frequency
2
Mask ROM
lk X 8 (8048A)
2k X 8 (S049A)
(Program
Area)
6
RAM
L-.------':!...,I'] 64 X 8 (804M)
gister/
Decoder
t====:::;-,
128 X 8 (8049A)
Accumula tor
!lit Test
Control and Timing Circuit
XTAL 2
Rl:5E'l' fKf EA
XTAL 1
....
55
M
.....
'"rc "c " .,~'">< ....
.,'" "
...
" ""....
... ,.,c: 'tn~
0
'1:l
::>
if>
" "....
~
'" .,....
'1:l
~
,.,
Ul
~
It
til
"OM
It
M,.,
It
""
III
M
II>
III
::>
..,c:
..... .....
n >
Crt
M
I
tn
M
It
"0
ALE
1"SEN RiS WR
~·t ..,Mon
.,
"""Ill
'"
...
M
Cl.
til{/)
M
0
0II>
0
C"
It
.,0
"".,..,
"tl
E
PROG
'---0---'
tn~
a?
.,
::;~
til
It C.
III
M
...0
0
M
Note 1)
The lower order 4 bits of
port 2 output latch are
used also for input/output operations with the
I/O expander.
/ic'te 2)
The output latch of port
o is also used for
address output.
"
.,
"'::>
or
ro
til
-600-
TOSHIBA INTEGRATED CIRCUIT
TMP8048A1TMP8035A
TMP8049AJTMP8039A
TECHNICAL DATA
RESET (Input)
Active Low signal which is used to initialize the Processor.
during Power down.
ALE
Also used
(Output)
Address Latch Enable. This signal occurs once during each cycle and is
useful as a clock output. The negative edge of ALE ~trobes address into
external data and program memory.
PSEN (Output)
Program Store Enable. This output occurs only during a fetch to external
program memory (Active Low).
55
(Input)
Single Step input can be used in conjunction with ALE to "single step"
processor through each instruction when SS is low the CPU is placed into
a wait state after it has completed the instruction bein? excuted.
EA
(Input)
External Access input which forces all program memory fetchs to reference
external memory. Useful for emulation and debug and essential for
testing and program verification.
(Active High).
XTAL 1 (Input)
One side of crystal input for internal oscillator.
external source.
Also input for
XTAL 2 (Input)
Other side of crystal input.
FUNCTIONAL DESCRIPTION
1.
System Configuration
The following sy stem functions of the IMP 8048A are described ~n detail.
(6) Stack (S tack Point er)
Program Memory
(7)
Flag 0, Flag 1
Data Memory
(8)
Program Status Word (PSW)
I/O Port
(9)
Reset
(4)
Timer/Counter
(10) Oscillator Circuit
(5 )
Interrupt Control Circuit
(1)
(2)
(3)
(1)
Program Memory
The maximum memory that can be directly addressed by the IMP8048A is
4096 bytes. The first 1024 bytes from location 0 through 1023
(TMP8048A) or the first 2048 bytes from location 0 to 2047 (TMP8049A)
can be internal resident mask ROM.
The rest of the 3072 bytes or the
2048 bytes of addressable memory are external to the chip. The
TMP8035A and TMP8039A have has no internal resident memory; all memory
must be external.
-601-
TOSHIBA INTEGRATED CIRCUIT
TMP8048A/TMP8035A
TMP8049A/TMP8039A
TECHNICAL DATA
There are three locations ln Program Memory of special importance.
Address
4095
Memory Bank 1
2048
2047
Memory Bank 0
o
Program Memory Area
Location 0
Activating the Reset line of the processor causes the first instruction
to be fetched from Location O.
Location 3
Activating the interrupt line of the processor (if interrupt enabled)
causes a jump to subroutine defined by address held in Location 3.
Location 7
A timer/counter
enabled) causes
Location 7.
interrupt resulting from a timer/counter overflow (if
a jump to a subroutine defined by address held in
Program address 0-2047 and 2048-4095 are called memory banks 0 and 1 respectively switching of memory banks is achieved by changing the most
significant bit of the program counter (PC) during execution of an
uncoditional jump instruction or call instruction executed after using SEL
MBO or SEL MB1.
Reset operation automatically selects Bank O.
(2)
Data Memory
Resident Data Memory (volatile RAM) is organized as 64 words (TMP8048A)
or 128 words (TMP8049A) by 8-bits wide.
The first 8 locations (0 - 7) of the memory array are designed as
working registers and are directly addressable by several instructions.
By executing a Register Bank switch instruction (SEL RBI) locations 24
- 31 are designated as the working registers in palce of 0 - 7.
-602-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPB048AJTMPl035A
TMPl049AJTMPB039A
Addressr--------------,
127
Data Memory
32
31 R-;;;i~;e-;.-ia_;;kJ.24
RBI
23 ---------
8 Level Stack
8
(16 byte)
7 R-;;;i;t~~ -B-;';COo
RBO
Internal Data Memory Area
RAM locations 8 - 23 serve a dual rol~ in that they contain the program
counter stack which is a stack 2 bytes wide by 8 levels deep.
These
locations store returning addresses from subroutines. If the level of
subroutine nesting is less than the permitted 8, you free up 2 bytes of
RAM for general use for every level of nesting not utilized.
All
64
(TMP8048A)
or
128
(TMP8049A)
locations
are
indirectly
addressable through either of two RAM Pointer Registers which reside at
RO and Rl of the Register array.
The TMP8048A architecture allows extension of the Data Memory to 256
words.
(3)
Input/Output Ports
The TMP8048A has 27 I/O lines which can be used for either input or
output.
These I/O lines are grouped into 3 ports each having 8
bidirectional lines and 3 "test" inputs which can after program
sequences when tested by conditional jump instructions.
Ports 1 and 2 are each 8-bits wide and have identical characteristics.
Data written to these ports is statically latched and remains unchanged
until rewritten.
As input ports these lines are non-latching, i.e.,
inputs must be present until read by an input instruction.
All lines of Ports 1 and 2 are called quasi-bidirectional because of a
special output circuit structure (illustrated in Figure 1). Each line
is continuously pulled to a +5V level through a high impedance
resistive device (50kohm) which is sufficient to provide the source
current for a TTL high level yet can be pulled low by a standard TTL
gate thus allowing the same pin to be used for both input and output.
In order to speed up the "0" to "1" trans i t ion a low impedance device
(5kohm) is switched in momentarily whenever a "1" is written to line.
When "0" is written to line a low impedance device overecomes the
pullup and provides TTL current sinking capability.
-603-
TOSHIBA INTEGRATED CIRCUIT
TMP8048A/TMP8035A
TMP8049A/TMP8039A
TECHNICAL DATA
ANL. ORL
+SV
+SV
SOHI
Internal
Bus-----r-..&-~
D
Q
D-Type
Flip-Flop
CLK
Write
SOk>l I/O pins
PortI or 2
Q 1--1-----;
Puls~---+--~------------~
Inter Buffer
IN
Fig.]
Input/Output Circuit of Port 1. Port 2
Reset initializes all lines to a high impedance "I" state.
~hen
external data memory area is not addressed during execution of an
internal program, Port 0 (DBO - DB7) becomes a true bidirectional port
(bus) with associated input and output strobes.
If bidirectional
feature not needed Bus can serve as either a statically latched output
port or a non-latched input port.
However, I/O lines of this port
cannot be intermixed.
As a static port data is written and latched using the OUTL instruction
and inputted using the INS instruction these two commands generate
pulses on the corresponding RD and VIR strobe lines.
As a bidirectional port the MOVX instructions are
write the port ,which generate the RD and VIR strobes.
When not being written or read,
s tate.
(4)
the
Bus
lines are
used
to
read
and
in a high
impedance
following
frequency
Timer/Event Counter
The 8-bit binary
inputs
(1)
up
counter
can use either
Internal clock (1/480 of OSC frequency)
.•..••........ Timer mode
-604-
of the
TOSHIBA INTEGRATED CIRCUIT
TMPB048AJTMP8035A
TMPB049AJTMPB039A
TECHNICAL DATA
(2)
External input clock form TI terminal
(minimum cycle time 3 x ALE cycle)
..•.•..•••.• Event Counter mode
The counter is preset table and readable with two MOV instructions
which transfer the content of the accumulator to the counter and vice
versa.
The counter content is not affected by a Reset and is
initialized solely by the MOVT, A instruction.
The counter is stopped
by a Reset or STOP TCNT instruction and remains stopped until started
by STRT T instruction or as an event counter by a STRT CNT.
One
started the counter will increment to its maximum count (FF) and
overflow to Zero continuing its count until stopped by a STOP TCNT
instruction or RESET.
The increment from maximum count to Zero (overflow) results in the
setting of an overflow flag and the generation of an interrupt request.
When interrupt acknowledged a subroutine call to Location 7 will be
initiated.
Location 7 should store the starting address of the timer
or counter service routine. The state of the overflow flag is testable
with the conditional Jump (JTF).
The flag is reset by excuting a JTF
or by RESET.
Figure 2 illustrates the concept of the timer circuit.
XTAL/1S
1/32
Pre-scaler
Cleared on Start Timer
JTF Instruction
8-Bit Timer/
Counter
T1 1-----IEdge Detector
n
Read/Write Enable
Timer Interrupt
Request Fl ip- Flop
INT
Timer Interrupt Enable
Fig. 2
Concept of Timer Circuit
-605-
TOSHIBA INTEGRATED CIRCUIT
-
TMPB048A/TMP8035A
TMPB049AJTMP8039A
TECHNICAL DATA
Conditional Jump Logic
S
JTF
Instruction
Timer
Flag F-F
R
Reset
Timer Overflow
--------~~s
Q~----~
Timer
Overflow
R F-F
Timer Interrupt
Execution-------r~
RETR
Instruction
Reset
00 pin
Inter-rupt
F-F
K
QI-----f"--...~-I-.J----__ID
ALE
CLK
External inter--
Q rupt Recognized
Timer interrupt
Recognized
Last cycle
of Instruct
EN I
Inst ruct ion
s'"
§-ooc
. '"
.......
Q
N
TCI~T
1
S
Instruction
..., Q
~
lI- I-
~~fo,
"'.0
...... fo,
Execution of Interrupt Call Instruction
R~;;~
R ;; ~ ~
Reset----~~----------------~
DIS TCNTl
Ins t ruct ion
Fig. 3
(5)
Instruction
Concept of Interrupt Control Circuit
Interrupt Control Circuit
There are two distinct types of Interrupts in the TMP8048A.
(1)
External Interrupt from the INT terminal
(2)
Timer Interrupt caused by timer overflow
-606-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPB048A/TMP8035A
TMPB049A/TMP8039A
The interrupt system is single level 1n that once an interrupt is
detected all further interrupt requests are ignored until execution of
an RETR (which should occur at the end of an interrupt service routine)
reenables the interrupt logic.
~interrupt
sequence is initiated by applying a low level "0" to the
INT pin.
INT is level triggered and active low which allows "Wire
Oring" of several interrupt sources.
The interrupt level is sampled
every machine cycle during ALE and when detected causes a "j ump to
subroutine" at Location 3.
As in any call to subroutine, the Program
Counter and Program Status Word are saved in the stack.
When an overflow occurs
in the
internal timer/event
counter an
interrupt request is generated which is reserviced as outlined 1TI
previous paragraph except that a jump to Location 7 is used instead of
3.
If INT and times overflow occur simultaneously then external
request INT takes precedence.
If an extra external interrupt 1S needed in addition to INT this can be
achieved by enabling the counter interrupt, loading FFH in the counter
(one less than the terminal count), and enabling the event counter
mode.
A "1" to "0" transition on Tl will cause an interrupt vector to
Location 7.
The interrupt service routine pointed to be addresses 1n Location 3 or
7 must reside in memory between 0 and 2047, i.e., Bank O.
Figure 3 illustrates the concept of the interrupt control circuit.
(6)
Stack (Stack Pointer)
An interrupt or Call to subroutine causes the contents of the program
counter to be stored in one of the 8 register pairs of the Program
Counter Stack.
The pair to be used 1S determined by a 3-bit stack
pointer which is part of the Program Status Words (PSW explained in
section (8)).
Data RAM locations, 8 through 23 are available as stack
registers and are used to store the program counter and 4-bits of PSW
as shown in the figure.
The stack pointer when initialized points to RAM location 8 and 9. The
first subroutine jump or interrupt results in the program counter contents being transferred to Locat ions 8 and 9.
Then the stack pointer
is incremented by one to point to Locations 10 and 11. Eight levels of
subroutine are obviously possible.
At the end of a subroutine signalled by a RET or RETR causes the stack
pointer to be decremented by one and the contents of the resulting pair
to be transferred to the Program Counter.
-607-
TOSHIBA INTEGRATED CIRCUIT
TMP8048A1TMP8035A
TMP8049AJTMP8039A
TECHNICAL DATA
23
I
I
7
6
I
22
I
I
I
I
20
21
I
19
I
I
I
5
18
17
4
16
15
14
3
13
2
12
11
1
a
10
_______
1. ________
PSW
PCB'\, 11
PC4'\, 7
I
I
pca", 3
Stack
Pointer
(7)
9
8
RAM
Address
Flag 0, Flag 1 (FO, Fl)
The TMPB048A has two flags FO and Fl which are used for conditional
jump. These flags can be set, reset and tested with the conditional
jump instruction JFO.
FO is a part of the program status word (PSW) and is saved 1n the stack
area when a subroutine is called.
(8)
Program Status Word (PSW)
An 8-bit status word which can be loaded to and from the accumulator
exists called the Program Status Word (PSW). The PSW is read by a MaV
A, PWS and written to by a MOV PSW, A. The information available in
the PSW is shown in the diagram below.
-608-
TOSHIBA INTEGRATED CIRCUIT
TMP8048A1TMP8035A
TMP8049A1TMP8039A
TECHNICAL DATA
Stack Pointer
/
Ic lAC IFO IBS 11 IS2 151 Iso
MSB I
II
1_ _ _ _ _ 11
Saved in stack area
at the time of Subroutine Call.
Bits a
Bit 3
Bit 4
-
2
Bit 7
(9)
Spare ("1" during Read)
Stack Pointer Bits (SO, 51, S2)
Not used ("1" level when read.)
Working Register Bank Switch Bit (BS)
a
Bit 5
Bit 6
LSB
Bank
Bank
a
Flag 0 (Fa)
Auxiliary Carry (Ae)
instruction and used
DA, A (Ae)
Carry ee) flag which
tion has resulted in
carry bit generated by an ADD
by the decimal adjust instruction
indicates that the previous operathe accumulator. (C)
Reset
The reset input provides a means for initialization of the processor.
This Schmitt trigger input has an internal pullup register which in
combination with an external luF capacitor provides an internal reset
pulse sufficient length to guarantee that all internal logic is
initialized.
-609-
TOSHIBA INTEGRATED CIRCUIT
TMPB048A/TMP8035A
TMPB049A/TMP8039A
TECHNICAL DATA
If the pulse is generated externally the reset pin must be held at ground
(~0.8V) for at least IOmS after the power supply is within tolerance.
Reset performs the following functions within the chip:
(i)
( ii)
(iii)
(iv)
(v)
( vi)
(vii)
(viii)
(ix)
(x)
(xi)
Sets PC to Zero.
Sets Stack Pointer to Zero.
Selects Register Bank O.
Selects Memory Bank O.
Sets BUS (DBO - DB7) to high impedance state. (Except when EA=SV)
Sets Ports I and 2 to input mode.
Disables interrupts (timer and external).
Stops Timer.
Clears Timer Flag.
Clears FO and Fl.
Disables clock output from TO.
(10) Oscillator Circuit
TMP8048A can be operated by the external clock input
crystal oscillator as shown below.
in addition to
+SV
r--~---t'
r - _........_....:3:..r;
XTAL 1
XTAL 2
2
XTAL 1
3
XTAL 2
+'::"SV-~~-~--+:
(a) Crystal Parameters and External Capacitance
The frequency of the oscillator will be calculated from the following
formula.
f ~ (1+CO/2(CL+C»/2n~
Load Capacitance DL
CL=(CI+Cfl)(C2+Cf2)/«CI+Cfl)+(C2+Cf2»
Cfl
Input Capacitance (4pF Typ.)+Stray Capacitance (less than SpF)
Cf2 : Output Capacitance(6pF Typ.)+Stray Capacitance (less than SpF)
-610-
TOSHIBA INTEGRATED CIRCUIT
TMPB048A/TMP8035A
TMPB049A/TMP8039A
TECHNICAL DATA
However the recommended value in the following table will be used
better by the reason of the start of the oscillation will depend on the
Equivalent Series Resistance Rl and the External Capacitances Cl+Cfl,
C2+Cf2.
Frequency Equivalent External Capacitance
Cl=C2(pF)
Series Res.
f(MHz)
R(ohm)
Recommended Typ i ca 1
Value
Allowance
11
11
10
10
8
8
6
6
5
5
4
4
3
3
2
2
1
25
30
25
30
30
40
40
80
50
80
100
150
100
200
400
500
800
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
10
10
10
10
15
10
20
10
20
15
15
10
20
15
25
15
25
5
5
5
5
5
5
5
5
5
')
5
5
5
5
5
5
10
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
17
15
20
17
25
20
35
17
40
25
30
20
40
25
40
25
40
Rf
XTAL1 2
.......
,_
-----
C1
Cn
f(MHz)
3 to 11
1 to 3
2.
.
--.--
7i77
J:
External Capacitance
Recommended Value
Cl=C2 (pF)
33
100
The following basic operations and timing are explained
Instruction Cycle
External Memory Access Timing
Interface with I/O Expander TMP8243P
Internal Program Verify (Read) Timing
Single Step Operation Timing
Low Power Stand-by Mode
-611-
XTAL 2
---- ....... -_ ..,
Cz
.
Cf2 :
---"-
Basic Operation and Timing
(1)
(2)
(3)
(4)
(5)
(6)
0
--'--
(b) Ceramic Resonator and External Capacitance
Frequency
3
I
7777
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
(1)
TMPB048AJTMP8035A
TMPB049AJTMP8039A
Instruction Cycle
The instruction of TMP8048A are executed in one or two machine cycles,
and one machine cycle contents of five states.
Fig. 4 illustrates its relationship with the clock input to CPU.
¢2 clock shown in Fig. 4 is derived to outside by ENTO CLK instruction.
ALE can be also used as the clock to indicate the machine cycle as well
as giving the external address latch timing.
(2)
External Memory Access Timing
(i) Program Memory Access
TMP8048A programs are executed in the following three modes.
(1) Execution of internal program only.
(2) Execution of both external and internal programs.
(3) Execution of external program only.
The external program memory is accessed (instructions are fetched)
automatically when the internal ROX address is exceeded in mode (2) and
from initial start address 0 in mode (3).
In the external program memory access operation, the following will
occur
The contents of the 12-bit program counter will be output on BUS(DBO
- DB7) and the lower 4-bits of Port 2.
Address Latch Enable (ALE) will indicate the time at which address is
valid. The trailing edge of ALE is used to latch the address
externally.
Program Store Enable (PSEN) indicates that an external instruction
fetch is in progress and serves to enable the external memory device.
Bus (DBO - DB7) reverts to Input mode and the processor accepts its
8-bit contents as an Instruction Word.
Figure 5 illustrates the timing.
(ii) Access of External Data Memory
In the extended data memory access operation during READ/WRITE cycle
the following occurs
The contents of RO Rl is output onto BUS (DBO - DB7).
ALE indicates address is valid. The trailing edge of ALE is used to
latch the address externally.
A read RD or write WR pulse on the corresponding output pins
indicates the type of data memory access in progress. Output data
valid at trailing edge of WR and input data must be valid at trailing
edge of RD.
Data (8-bits) is transferred over BUS.
-612-
TOSHIBA INTEGRATED CIRCUIT
TMP8048A/TMP8035A
TMP8049A/TMP8039A
TECHNICAL DATA
XTALl
Input
(6MHz)
(AO-3)
I
I
I -I -I
I
I
I I I I I I I I
(Rr)
I
j
I
I
I
I
I
I
I
I
<-!
]
I
I
I
I
I
I
I
Ir=0-7
I -I -I
IXCH A,@Rr
0101 1101010101 r](A)-->CCRr))
1
I
I
I
I
I
I
I
!
<-]
I I I 1 I ! I I r = 0, 1
-I ]XCHD A,@Rr
0101 11 11010101 rl(AO-3)-->«RrO-3))1
I
I
I
I
I
I
I
I
I
I
<-I
] r = 0, 1
I
I
I
I
I
I
!
I
2 I - - i
IMOVX A,@Rr
110] 01 01 01 01 01 rl(A)<--CCRr))
I
I
I
1 I
I
I
]
I
I r = 0, 1
I
I
110101110101 O[ rICCRr))<--(A)
I
2
1- -[
!HOVX @Rr,A
I
I
I
I
I
I
I
I
I r = 0, 1
I
I
I
IMOVP A,@A
1101110101 O! 1] 11(pcO-71<--(A)]
2
I
-I
I
I
I
I
I
I
I
I
I (A)<--«PC))
I
11 11 11 O[ 01 01 11 11 (pco-71<--(A)
2
I
IHOVP3 A,@A
I
I
I
I
I
I
I
I
I
I (PC8-11)<--001l
I _ _ _ _~_~I~I~I_~I~I~I~!_~I(~A-=-)<_=_-_--=-«~P_=C~))_ _~_ _~_~I~__
-621-
TOSHIBA INTEGRATED CIRCUIT
TMP8048A1TMP8035A
TMP8049A1TMP8039A
TECHNICAL DATA
Timer/Counter Instruction
Mnemonic
IMOV A,T
I ~lOV T, A
j STRT T
I
I
I STRT CNT
I
I
I STOP TCNT
I
I
! EN TCNT1
I
IDIS TCNT1
I
Operation
Instruction Code
D7 I D61 D5 : D4 I D3 r D2 I D1 I DO I
01 1101010101 1101(A)<--(T)
01 1 i I I 0 I O! O! 1 I 01 (T) <-- (A)
01 11 0 I 1 I 01 1 I 01 1 I Counting is
I started in the
I
I
I
I
I
I
I
Itimer mode
I
I
I
I
I
I
I
01 11 0 I 0: 01 1 I 01 11 Counting is
Istarted in the
I
I
I
I
I
I
I
I event counter
I
I
I
I
I
I
I
! I ! ! I Imode
I
I
01 1 I 1 I 01 01 II 01 11 Stop both time
laccumulation and
I
I
I
I
I
I
I
I event counting
I
I
I
I
I
I
I
01 0 I 11 01 01 11 01 11Timer interrupt
lis enabled
I
I
I
I
I
I
I
01 01 1 I 11 01 1 I 01 IITimer interrupt
I is disabled
I
I
I
I
I
I
IBytes
I
1
I
1
I
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I Cy cl e s I F 1ag I
ICTAcI
I
I -I -I
I
I -I -I
I
I -I -I
I
I
I
I
I
I
I
I
I
I -I -I
I
I
I
I
I
I
I
I
I
I
I
I
I
I -I -I
I
I
I
I
I
I
I
I
I
I
I -I
I
I
I
I
I
I -I -I
I
I
I
I
I
-,
Control Instruction
Mnemonic
EN I
DIS I
SEL RBO
SEL RBI
SEL MBO
SEL MBI
ENTO CLK
NOP
Instruction Code
Operation
IBytes
D7ID6ID5!D4ID3[D2!Dl!DOI
I
01 01 01 01 01 11 0 I 1!Externa1 interrupti
lis enabled
I
I
I
I
I
I
I
I
01 01 01 1 I 01 11 01 11Externa1 interrupti
lis disabled
I
I
I
I
I
I
I
I
1
1 I 11 01 01 01 1[ 01 1 I (BS)<-- 0
I
1
11 1 I 01 11 01 1 I 01 11(BS)<-- 1
I
1
11 1 I 1 I 01 01 1 I 01 11 (DBF)<-- 0
I
1
1 I 1 I 11 11 01 1 01 11 (DBF) <-- 1
I
1
01 1 I 1 I 1 I 01 11 01 liTO is enabled to
1
lact as the clock
I
I
1 1 I
1 I
1
loutput
1 I
I
I
I
I
1
I
01 01 01 01 01 01 01 o I No o]2eration
I
r
-622-
I Cycles 1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1 I
!
I
I
I
1
I
I
1
I
Flag I
clAcl
-I -I
I
I
-I -[
I
I
-I -I
-I -I
-I -I
-I -I
-I -I
I
1 1
-I -I
TOSHIBA INTEGRATED CIRCUIT
TMP8048A/TMP8035A
TMP8049A/TMP8039A
TECHNICAL DATA
I SYMBOL
IVDD
Ivcc
IVINA
I VINB
IrD
ITSOLDER
ITSTG
ITOPR
I RATTING
1-0.5V to +7V
1-0.5V to +7v
1-0.5V to +7V
1-0.5V to +l3V
I
1 . SW
I
260' C
I-ss'c to lSO'C
I O'C to 70'C
(with
to GND (VSS))
Supply Voltage (with respect to GND (VSS))
IInput Voltage (Except EA)
IInput Voltage (Only EA)
IPower Dissipation (Ta - 70'C)
ISoldering Temperature (Soldering Time 10 sec)
IStorage Temperature
10perating Temperature
DC CHARACTERISTICS
TA=OoC to 70 o C, VCC=VDD=+SV~lO%, VSS=OV, Unless Otherwise Noted.
SYMBOL
!VIL
IVIH
I
I
IInput Low Voltage
IInput High Voltage
I (Except XTALI ,XTAL2 ,RESET
ITEST CONDITIONS IMIN. ITYP.
I
1-0.51 I
I 2.01
I
I
I
IMAX. I UNIT I
I 0.81
V I
I vcci
V I
I
I
I
I~V~IH~l~~I~I~np~u~t~H~i~g~h~V~o~l~t~a~g~e~~~----~I--------------1~3-.78~1--~I--V-CC~I---V-1
I
I (XTALI ,XTAL2,RESET)
I
I
I
I
I
I
-:-:v-::-oL::-----T~O.:.:u.c::tp~u:::..:t~L~o.:.:w~V;:,.o.t.:l,:=t:.::a:.:::g~e.!...-,-.(B::-:U:-:S")-------jI~I-:-0-=-L---=-2--:.Om,---,A--------,I~----+I--~I-:-O-.-'-4S+1---v-I
IVOL]
IOutput Low Voltage
IIOL=1.8mA
I - I
10.451
V I
I
I(RD, WR, PSEN, ALE)
I
I
I
I
!
I
I~V-::-OL~2~~!~O':':u~tpLu~t~L-O~W~V~o~lLt~a~g~e'!"'-'-'(P::-:R::-:O::-:G~)----~I~I-:-O-=-L--~]--:.Om~A------I~----+I--~1-:-0-.-'-45+1---v-I
I VOL3
IOutput Low Voltage
I IOL-1.6mA
I - I
10.4SI
V I
I
I (For other output pins)
I
I
I
I
I
I
I~V~OH~--~I~O~u~tp~u~t~H~i~g~h~V~o~l~t~a-gLe~(B~U::-:S~)----~I~I~O~H----4~0~0~u~A-----j1~2-.74+1--~I-----rl--7.v~1
IVOHI
I
IOutput High Voltage
I (RD, WR, PSEN, ALE)
I IOH=-]OOuA
I
I 2.41
I
I
I
I
- I
I
V I
I
I-V-OH-~~?--~I~O~u~tpLu~t~H~i~g~h~V~oLl~t~a=g~e-----------I~I-O-L-=--4-0-u-A------~1-2-.-4+1--~I----~I---v-1
1______+I~(F~o~r~o~t.:.:h=e~r~o~u~t~p.:.:u~t~p~i~n.:.:s~)______~1------------~I----rl__-+I__~I--___ I
I
I
I
I
I
I
I
I
IILI
IInput Leak Current (Tl, INT)
Ivss < VIN < vcci - I
1+]01 uA I
I~~~I____________________~I---=~~=~~I--~I--~I--~I----I
lUll
IInput Leak Current
IVSS+0.4S.
1:"
>
0
!?
UHf,
...; ....
~S
t'"
i:t
~;g
::Hi 68
:r",
'" :r'" '"
tr.,W
0
IT
Pi:
tr"s:
",:0-
"-0
~:t>
l<"';
0:tr
'"
tr.
~ri
"'"
",to
0:0-
tr2
po
"
tU.
Note 1)
Note 2)
The lower order 4 bit of port 2 output latch are used also
input/output operations with the I/O expander.
The output latch of port 0 is also used for address output.
-633-
for
TOSHIBA INTEGRATED CIRCUIT
TMPlOC48AP/-6, TMP80C35AP/-6
TMPlOC48AF/-6
TECHNICAL DATA
PIN NAMES AND PIN DESCRIPTION
VSS (Power Supply)
Circuit GND potential
VCC (Power Supply)
+5V during operation
PS (Input)
The control
Low)
signal
for
the power saving at
the
power down mode
(Act i ve
PROG (Output)
Output strobe for the IMP 82 C43P I/O expander.
PIO - P 17 (Input/Output) Port
8-bit quasi-bidirectional port (Internal Pullup
50Kn) •
P20 - P27 (Input/Output) Port 2
8-bit quasi-bidirectional port (Internal Pullup
= 50Kn) .
P20 - P23 contain the four high order pzogram counter bits during an external
program memory fetch and serve as a 4-bit I/O expander bus for the
TMP8243P.
DBO - DB7 (Input/Output, Tri-State)
True bidirectional port which can be written or read synchronously using
the RD, WR strobes.
The port can also be statically latched.
Contains
the 8 low order program counter bits during an external program memory
fetch, and receives the addressed instruction under the control of PSEN.
Also contains the address and d~a duri~ an external RAM data store instruction, under control of ALE, RD, and WR.
TO (Input/Output)
Input pin testable using the conditional transfer instructions JTO and
JNTO. TO can be designated as a clock output using ENTO CLK instruction.
TI (Input)
Input pin testable using the JTl and JNTl instruction.
Can be designated
the event counter input using the timer/STRT CNT instruction.
INT (Input)
External interrupt input. Initiates an interrupt if interrupt is enabled.
Interrupt is disabled after a reset.
Also testable with conditional jump
instruction. (Active low)
RD (Output)
Output strobe activated during a Bus read.
Can be used to enable data
onto the Bus from an external device. Used as a Read Strobe to External
Data Memory (Active Low).
WR (Output)
Output strobe during a Bus write (Active Low).
External Data Memory.
-634-
Used as a Write Strobe to
TOSHIBA INTEGRATED CIRCUIT
TMPBOC48AP/·6, TMPBOC35AP/·6
TMPB0C48AF/·a
TECHNICAL DATA
RESET (Input)
Active Low signal which is used to initialize
during the power down mode.
the Processor.
Also used
ALE (Oupput)
Address Latch Enable.
This signal occurs once during each cycle and is
useful as a clock output.
The negative edge of ALE strobes address into
external data and program memory.
PSEN (Output)
This output occurs only during a fetch to external
Program Store Enable.
program memory (Active Low) .
SS (Input)
Single step input can be used in conjunction with ALE to "single step"
processor through each instruction when SS is low the CPU is placed into a
wait state after it has completed the instruction being executed.
Also
used during the power down mode.
EA (Input)
External Access input which forces all program memory fetches to reference
external memory. Useful for emulation and debug and essential for testing
and program verification. (Active High)
XTAL 1 (Input)
One side of crystal input for internal oscillator.
nal source.
XTAL 2 (Input)
Other side of crystal input.
-635-
Also input for exter-
,
~
or
IMSTRt,tTlO!lS (114)
Asse~bler
Object CO .... (A)<3:0>
{A) .... {A)
{A) .... (A)<7>
{A) <-{A)
{C) .... (A)<7>
(A) .... (C)
(A) .... (A)
(A)<7> .... (A)
{A) .... (A)
(C) .... (A)
(A)<7> .... {C)
(A) .... (Po)
1
1
1
1
1
1
1
1
HOVO
ANlO
D
- OR)
INC
(1) IHC
0-0-6
!
DEC
-
BUS. Ii
BUS. Ii
10011000
iiiiiiii
10001000
iiiiiiii
98
(B~)""(BUS)
/\ i
2
ii
88
ii
(B~)""{BUS)
vi
2
I
A • Po
000011 PO OC'o
Pp, A
PP. A
PD, A
Rr
0011110p
100111po
100011PJl
00011 rrr
0001000r
11001 rrr
a1l00100
aHl
10110011
11101rrr
aHl
~Rr
JHP
Rr
a
JHPP
OJNl
@A
Rr, a
JC
a
1
8
r
0:0--6
n:0-6
1
a
1
c
JC'o
gc'O
8C'p
18+r
10'r
C8'r
aH+4
B3
£8'r
n
t
0:0-6
P:l,2
2
h
JNC
a
I
n .Il
s
t
----
-
»--I
rn
»
r-
2
2
I
(BUS)~(AC)
C)
0
()
0
2
(A) .... (A)·,
rn
m
()
I
(A) .... (A) v(Rr)
(A) .... (A) v! (RrJ]
(A) .... (A) vi
:z
--I
-i
a
JHl
a
JTO
a
(1) ......
11110110
f6
aHl
11100110
E6
aHl
11000110
C6
aHL
10010110
96
aHL
00110110
36
aHl
Reoister InstnJctlon
po1_7
(A) o-(Pp)
(A)<7'4> -0
(Pp) .... (A)
p-~-7
(Po) .... (Pp)/\(A) p-4-7
1P~) .... !P~)\j(A)<3 Q>J-l-T
(Rr) .... (Rr)·,
r-O-7
roO. 1
((Rr)) o-URr)]'1
(Rr) o-(Rr)-1
roO~7
(PC)<10:0> .... a
(PC)<11> .... (OBF).
(PC)<7.0>o-PRO[(PC)<11.8>' (A)]
(Rr)
.... (Rr)-1
r:0--7
1
if(Rr) *Ot~n(PC)<7.0>""aHl
else no operation
i I(CH then(PC)<7.0)o-aHL
else no operation
i I(C)'O thenIPC)~aHl
else no ooeration
if(A)=O t~n(PC)<7.0)""aHl
else no operation
il(A)otO then(PC)<7 0> ....aHL
else no ooeration
if TO=1 t~n(PC)<7. O> .... aHl
elso no o~rat inn
:;;:0
»
-I
()
» c
--I
I
2
2
2
I
2
1
1
1
2
2
2
2
2
2
2
2
-I ....
Bail
CI;J
c:::I c:::I
nn
~~
z=- z=-
~~
aiA
•
CI
c:::I
n
w
en
z=-
~
m
...
~Ib
'"
s '
Asseo!bler
H~""nic
.NTO
B Jl1
3
3
r
a JlfT1
a
n
c JFO
3
h
I
n
s
t
r
u
JFl
3
Jlf
3
Jlfl
3
rei
Object Code
(1st)
Function
~n<1)
4"DX
Sin
00100110
aHl
01010110
aHL
01000110
aHl
10110110
aHL
01110110
aHL
00010110
aHl
10000110
aHt
26
56
4S
BS
76
16
SG
FlaQ ycle
.....
I
a~
H I HOV
2
I
v
e
2
2
2
I
2
I
I
I
t
i
0
n
s
t
TC
io
,,,u
en
rl
J8b
a
n
CAlt
a
(2)RH
RETR
CLR
CPl
C
C
FO
FO
Fl
FI
A . Rr
A ,~Rr
A •t i
bbblOOIO !}<12
aHt
aHl0100 ali·l4.
aHL
10000011
83
10010011
93
if (A)=1 then
(PC)<7:0> .... aHl
else no operation
b=0~7
IISP)] <-(PSW)<7:4>· (PC)
(SP) .... (SP).1
(PC) 4-3
(PC) <-(DSf)
(SP) 4-(SP)-1
(PC) .... [(SP)]<11 :0>
(SP) <-(SPH
(PC) +-((SP)]<11:0>
(PSW)<7:4> "'::[(SP)]<15:12>
(C)<-O
(C)<-N01(C)
(f0) <-0
(FO) ....NOT(FO)
(Fl) <-0
(F1) <-NOT(Fl)
(A)<-(Rr)
r-0~7
(A)<-[ (Rr)]
roO, 1
(A) <-i
10010111
97
10100111
A7
10000101
8J
1(3) ClR
CPt
10010101
95
CtR
10100101
A5
10110101
CPl
B5
HOV
11111rrr F8'r
I«JV
l111000r FO+r
23
00100011
(4) I«JV
iii i i ii i
ii
Iffl
Rr. A 10101 rrr M'r (Rr)<-(A)
r-0-7
, ,1«JV__@RrLA~ 1010000r AO+r [(Rr)]+-(A)
roO. 1
(2) ---"- Subroutine Instruction (:If ~;.-. TTag)nstruction
(') •• --.. Hove Instruct ion
o
2
r
2
Hne~onlc
HOV-
2
2
Object COIle
(1st)
Assembler
I
C, AC
il TO-O thcn(PC)<7:0><-a~l
else no ooeration
if TI-l thcn(PC)<7:0><-aHl
else no operation
i I Tl-0 then(PC)<7 :O><-aHl
else no operation
i I fO·1 then(PC)<7: O><-aHL
else no operation
if fl-l then(PC)<7:0><-aHl
else no operation
if H-I then(PC)<7:0><-aHl
else no operat ion
if INT =0 then(PC)<7 :O><-aHl
else no operation
c
Ol
W
aen
TlCS-48 LIST OF INSTROCllOllS IV4)
Tlcs-.e LIST or INSTROCllOllS 13m
HOV
HOV
XCii
XCii
XCIID
HOVX
HOVX
HOVP
HOVP3
HOV
HOV
STRT
STRl
STOP
EN
DIS
flr.'i
~Rr.'i
A, PSW
PSW,A
A. Rr
URr
A.~Rr
@Rr.A
A'Rr
A,'A
A,~A
A, 1
T.A
T
CNT
mH
TCNT!
TCNTI
Function
(2m)
Bin.
10111rrr
iiiiiiii
1011000r
iiliiiii
11000111
11010111
00101rrr
0010000r
0011000r
1001000r
1000000r
10100011
11100011
01000010
01100010
01010101
01000101
01100101
00100101
00110101
I Hex.
BS'r
ii
BO'r
ii
C7
07
-:..:z:
flag kCle
I
(Rr)"1
reo;.,
[(Rr)) .. i
r-O.I
III
uci
T2
(A) <-(PSW)
(PSW) <-(A)
2~·r (A) -(Rr)
r-O~71
20'r (A) -I (Rr))
r-O.l
30'r (A)<30>~[(Rr)<30)] r-O.I
90'r [XT[(Rr)] "(A)
roO. I
80'r (A) ---[XT[(Rrl]
roO I
A3 (A) <-PRO[(PC)· (A)]
E3 (A) ---PRQ[(PC)· 011· (AI]
42 (A) <-OR)
62 (TR)"(A)
55 Start TIter
45 Start counter
65 Stop Ti!ller/Counter
25 [Oilhle Ti~~r/Counter Interrupt
35 Disable T"er/Counter Interrupti
I;
I~
Ii
I~
I 1
II 1i
I:
z
--I
rn
-t
m
G)
()
;:::c
:::I:
:>
--I
Z
rn
()
>
0
1:1
n
r-
> ;:::c
-t n
> c
--I
I I
II
1
I
(5)
2
11
2
,
,
1
1
I
1
1
1
I
1
2
1
1
o
r
o
I
[N
I
DIS
SEl
I
RM
R81
HBO
H81
CtK
S[l
SEt
S[t
FNTO
100000101
·00010101
11000101
11010101
11100101
11110101
01110101
I
05 Enable External Interrupt
15 Disable External Interrupt
C5 (8S)<- 0
05
(1lS) .... 1
E5 (08f) <- 0
F5 (OSf) <- I
75 Enab(e Clock OUt[lU\ on TO
I I
HALT
00000001
01 Ha It
~op~~~~00~no~o~pr=a7ti~on~----------~--~~
(5) ...... AID Converter Instruction
(S) ...... Other
-t -t
5151
__
C:C:
aa
nn
po po
~~
J./A
-t
=CI
Q
n
Col
CII
po
~
at
TOSHIBA INTEGRATED CIRCUIT
TMPBOC48AP/-6, TMP80C35AP/-6
TMPB0C48AF/-6
TECHNICAL DATA
TMP80C48AP/TMP80C3SAP/~80C48AF
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
ITEM
I
I SYMBOL
Ivcc SU]2]2ly Voltage (with res]2ect to GND (VSS))
I VCC
IIn]2ut Voltage (Exce]2t EA)
I VINA
IIn]2ut Voltage (Only EA)
I VINB
IPower DiRsi]2ation (Ta=70·C)
I PD
I TSOLDER !Soldering TemEerature (Soldering Timer 10 sec)
IStorage TemEerature
I TSTG
IO]2erating Tem]2erature
I TOPR
I
I
I
I
I
I
I
RATING
-O.SV to +7V
-O.SV to VCC+O .SV
-O.SV to 13V
250mW
260· C
-65 ·C to ISO·C
O·C to 70·C
DC CHARACTERISTICS
TOPR=O·C to 70·C, VCC=+5V±10%, VSS=OV, unless otherwise noted.
I SYHBOL I
PARAHETER
I TEST CONDITIONS I MIN. I TYP. I HAX. I UNIT I
IVIL
IInput Low Volt~Except
I
1-0.5 I
I 0.8 I V I
1_ _ lxTALl. XTAL2, RESET)
I
'I
I
I
I
IVILI
IInput Low Volta~
I
1-0.5 1--I0":6I-v-1
1_ _ _ 1 (XTALI, XTAL2, RESET)
I
I'
I
I
I
IVIH
IInput High Vol~(E.!.£ept I
12T1--I---VCCI-v-'
1_ _ _ lxTALl, XTAL2, RESET, PS)
I
I
,
i
IVIHI
IInput High Voltage(Except
I
10.7 x l - - I v c c l - v I_ _ IXTALI, XTAL2, RESET, PS)
I
I vcci
I
I
1VOL
IOutput Low Voltage
IIOL=1.6mA
'--I--I--0.45,-v1_ _ _ 1 (Exce]2t PIO-PI7, P20-P27)
!
!
I
iVOLI
IOutput Low Voltage
I IOL=1.2mA
, - - : - - : 0.45!-V!
I(PIO-PI7, P20-P27)
I
I
I
I VOHll IOutput High Voltage
I IOH=-l. 6mA
1 2 . 4 1 - - - - -\-,1_ _ _ 1 (Exce]2t PIO-PI7, P20-P27)
!
i
I
I IOH=-400IlA
Ivcc- : - - - - - V IVOHl2 IOutput High Voltage
I
I(ExceptPIO-PI7,P20-P27)
I
10.8 1
1VOH21 IOutput High Voltage
I IOH=-SOIlA
! 2 . 4 1 - - - - -\i-'I
I (p lO-P 17, P 20-P 27)
I
I
I
IVOH22 IOutput High Voltage
I IOH--2SIlA
Ivcc- I - - - - - v I
I (PIO-PI7, P20-P27)
I
I 0.81
I
I
In:r-Ilnput Leak Current
IVSS.IA [
DC CHARACTERISTICS
TMP80C48AP/TMP80C35AP/TMP80C48AF
: TOPR= O·C to 70'C,VCC=5V±10%,VSS=OV
TMP80C48AP-6/TMP80C35AP-6/TMP80C48AF-6 : TOPR=-40'C to 85'C,VCC=5V±20%,VSS=OV
I SYMBOL !
PARAMETER
iTEST CONDITIO", I MIN.! TYP.I MAX.! UNIT [
!
[tPSHR :Po,,'er Save Hold Time
I
(RESET)
I !
[
,
[
I tPSSR
!Power Save Setup Time
[
[
ItVH
Ivcc Hold Time CPS)
1
1
1VCC Set up Time (p S)
1tVS
Note: tCY=2.5>.1S (fXTAL=6MHz)
(RESET)
[
I
10
1
[
>.IS [
1
[
[
1
1
1
1
1
[ 10
1
[5
1
[5
[
1
1
1
[
TIMING WAVEFORM
I
}
VCC
;
,
tVH
[
t
I
tvs
.;
PS
tpSHR
-647-
tpSSR
1
mS [
1
>.IS 1
1
>.IS 1
TOSHIBA INTEGRATED CIRCUIT
TMPBOC48AP/-6, TMP80C35AP/-6
TMPBOC48Af/-6
TECHNICAL DATA
POWER DOWN MODE (II)
. . . . . . . . . ALL Data Hold Mode
The operation of oscillation circuit is suspended by setting PS terminal to
low level after Ss:terminal has been set to low level.
Consequently, all data
can be held in low power consumption.
The m1n1mum hold voltage of VCC in this mode is 3V.
PS terminal is set to ---.!2igh level to resume osci llation after VCC
has been
reset to 5V, and then SS terminal is set to high level, thU's, the normal mode
1S restarted continuously from the state just before the power down mode (II).
DC CHARACTERISTICS
THP80C48AP/TMP80C35AP/TMP80C48AF
: TOPR=O'C to 70'C, VSS=OV
TME' 80C48AP- 6/TME' 80C35AP- 6/TME' 80C48AF-6 : TOPR=-40' C to 85' C, VSS=OV
1SYMBOL 1
PARAMETER
1
TEST CONDITION
1 MIN. 1 TYP. 1 MAX.: UNIT 1
I
i
i
1
1
1
I
I
1 VSB2 1 Standby Voltage(2) 1
1 3.0 1
1 6.0 1 V 1
1---1
iVCC-5V,VIH-VCC-0.2V,
1--1--1--1--1
I ISB2 i Standby Current(2) IVIL=0.2V
1
1 0.5 I 10 I I1A 1
AC CHARACTERISTICS
TMP80C48AP/TMP80CJ5AP/TMP80C48AF
: TOPR= O·C to 70'C,VSS=5V±10%,VSS=OV
TME'80C48AP-6/TME'80C35AP-6/TME'80C48AF-6 : TOPR=-40'C to 85 ·c, VCC=5V±20%, VSS=OV
!SYMBOL!
PARAMETER
iTEST CONDITIONi MIN.I TYP.] MAX. 1 UNIT 1
i i i
I
1
1
! tPSHS iPower Save Hold Time (55)
I
I 10
1
I1S
I i i
1
1
I tPSSS :Power Save Setup Time (55)
I 10
mS
i
l
(PS)
i tVH
I VCC Hol d Time
I
I
1
l
1
tVS
I VCC Setup Time (ps)
Note: tCY-2.5I1S (fXTAL-6MHz)
5
I1S
5
I1S
TIMING WAVEFORM
1\
SS
f
tVH
-\
1
tvs
I
I
PS
t
pSHS
-648-
tpsss
TOSHIBA INTEGRATED CIRCUIT
TMPSOC48AP/-6, TMP80C35AP/-6
TMPSOC48AF/-6
TECHNICAL DATA
HALT MODE
• 1 HALT INSTRUCTION
OP code is "OIH".
HALT INSTRUCTION is an additional
standard 8048/8049 instruction set.
instruction to the
2 Entry to HALT MODE
On the
MODE.
execution
of
HALT
INSTRUCTION,
TMP80C48A/1}lPBOC35A
enter
HALT
· 3 Status in HALT MODE
The oscillator continues its operation,
internal logic values just prior to the
rna in ta ined.
Power consumpt ion in HALT
operation.
The status of each pins are
however, the internal clocks and
execution of HALT INSTRUCTION are
MODE is les s than 50% 0 f norma I
described in the following table.
· 4 Release from HALT MODE
HALT MODE is released by either of two signals (RESET,INT).
(1)
RESET Release Mode: An active RESET input signal causes the normal reset
function.
TMP80C48A/TMP80C35A start the program at address "000 H".
(2)
INT Release Mode: An active INT input signal causes the normal operation.
In case of interrupt enable mode (EI MODE), TMP80C48A/TMP80C35A execute
the interrupt service routine, after the execution of one instruction
which is located at the next address after HALT INSTRUCTION.
In case of interrupt disable mode (DI MODE), TMP80C48A/TMP80C35A execute
normal operation from the next address after HALT INSTRUCTION.
· 5 Supply Voltage Range in HALT MODE
The operating supply voltage range
are same as in normal operation.
and
-649-
the
operating temperature
range
TOSHIBA INTEGRATED CIRCUIT
TMPBOC48AP/-6, TMP80C35AP/-6
TMPBOC48Af/-6
TECHNICAL DATA
PIN STATUS IN POWER DOWN MODE (I) (II)
PIN NAME
DBO - DB7
PlO - P17
P20 - P27
TO
Tl
XTALl
XTAL2
RESET, SS
INT, EA
RD, WR~E
PROG, PSEN
STATUS
High impedance
Input disabled
High impedance, input disabled
Input disabled
High impedance
Output "High" Level
Input disabled when oscillator is stopped.
Pull-up transistors turn off.
Input disabled when oscilltor is stopped.
High impedance
PIN STATUS IN HALT MODE
PIN NAME
DBO - DB7
PIO - P17
P20 - P27
TO
Tl
XTALl, XTAL2
RESET, INT
5S, EA
RD, WR->--PROG, PSEN
ALE
STATUS
Values prior to the execution of HALT
INSTRUCTION are maintained.
Status prior to the execution of HALT
INSTRUCTION is maintained.
Input disabled
Continue oscillation
Input enabled
Input disabled
Output "High" level
Output "Low" level
-650-
TOSHIBA INTEGRATED CIRCUIT
TMPBOC48AP/-e, TMPBOC35AP/-a
TMPBOC48AF/-a
TECHNICAL DATA
OSCILATOR
QUARTZ CRYSTAL
f
lMHz to 4MHz
f = 4MHz to llMHz
Cl
Cl
C2
C2
30pF
20pF
CERAMIC RESONATOR
f
lMHz to 3MHz
f = 3MHz to llMHz
Cl
Cl
C2
C2
lOOpF
30pF
CI
:;J;.,
TYPICAL CHARACTARISTICS: Vee = SV, Ta = 2S'C, unless otherwise noted.
v cc - f MAX . TYPICAL CURVE
V OUT - IOL TYPICAL CURVE
VCC
IOL
(V)
(rnA )
6
40
30
v
V
/"
20
10
10
/
V
5 VOUT(V)
V OUT - IOH TYPICAL CURVE
(PORT 1.2)
1
2
fXTAL - ICC TYPICAL CURVE
ICC
(rnA)
I
I
/
-50
10
.
-100
V·····
V
L
./
-150
r---
~
VV
/
- 200
IOH
10
(uA)
V OUT - IOH TYPICAL CURVE
tRESET
C
RESET
(DB. CONTROL)
1
2
3
- tRESET TYPICAL CURVE
(rns)
5 VOUT(V)
/:
V
100
,/
60
-5
/"
30
20
~
10
,..'
0.01
-10
"
-15
"
~
1
0.020.03
-20
O.Ob 0.1
0.20.3 CRESET
(uF)
IOH
(rnA)
-651-
-V
/
TOSHIBA INTEGRATED CIRCUIT
TMPBOC48AP/-6, TMP80C35AP/-a
TMPBOC48AF/-6
TECHNICAL DATA
OUTLll\E DRAWING (DUAL Il\LlNE PACKAGE)
Unit 1n rrnn
40
2I
1
20
1
z
51.3MAX
Note: 1.
2.
This dimension is measured at the center of bending point of leads.
Each lead pitch is 2.S4mm, and all the leads are located within
±O.2Srrnn from their theoritical positions with respect to No.1 and
No.40 leads.
-652-
TOSHIBA INTEGRATED CIRCUIT
TMP80C48AP/-6, TMP80C35AP/-6
TMP80C48AF/-6
TECHNICAL DATA
OUTLINE DRAWING (FLAT PACKAGE)
Unit in mm
ll=
(J2:>tl
I
0e}'ITCH
------------------~
~
rl
0
~.
0
"
rll
140±O.1
( 17.6±O:l)
180±025
!lARK
(06)
1 5.2± 0:1
-653-
(l.:I±02)
'"-\".
0
'"
r-
rl
INTEGRATED CIRCUIT
TOSHIBA
TECHNICAL DATA
-654-
TMP80C48AP/-6, TMP80C35AP/-6
TMP80C48AF/-6
TOSHIBA INTEGRATED CIRCUIT
TMPlOC48AP/-8, TMP80C38AP/-8
TMPlOC48AF/-8
TECHNICAL DATA
8-BIT SINGLE-CHIP MICROCOMPUTER
TMP 80C49AP /TMP 80C49AP-6
TMP80C49AP /TMP80C39AP-6
TMP80C49AF/TMP80C49AF-6
GENERAL DESCRIPTION
The TMP80C49A is a single chip microcomputer fabricated in Silicon Gate CMOS
technology which provides internal 8-bit parallel architecture.
The following basic architectural functions of a computer have been included
in a single chip; an 8-bit CPU, 128 x 8 RAM data memory, 2K x 8 ROM program
memory, 27 I/O lines and an 8-bit timer/event counter.
The TMP80C49A is particularly efficient as a controller. It has extensive bit
handling capability as well as facilities for both binary and BCD arithmetic.
The TMP80C39AP /-6 is the equivalent of a TMP80 C49AP /-6 without ROM program
memory on chip.
By using this device with external EPROM or RAM, software
debugging becomes easy.
The TMP80C49AP/-6 and TMP80C39AP/-6 are in a standard Dual Inline Package.
The TMP80C49AF/-6 is in a 44-pin Flat Package.
FEATURES
TMP80 C49AP /TMP80C39AP /TMP80C49AF
1.36~s Instruction Cycle Time
O·C to 70·C, SV ±lO%
TMP80C49AP-6/TMP80C39AP-6/TMP80C49AF-6
2.S ~s Instruction Cycle Time
-40·C to 8S·C, SV ±20%
Software Upward Compatible with
TMP8049AP/TMP80C49P-6/INTEL's 8049
HALT Instruction (Additional Instruction)
2K x 8 masked ROM
128 x 8 RAM
27 I/O lines
Interval Timer/Event Counter
-655-
Low Power
lOrnA MAX. in Normal Operation
(VCC=SV, fXTAL=6MHz)
lO~A Max. in Power Down Mode
(VCC=SV, fXTAL : DC)
Single Power Supply
Power Down Mode (Stand-by Mode)
Halt Mode (Idle Mode)
TOSHIBA INTEGRATED CIRCUIT
TMPBOC49AP/-a, TMPBOC39AP/-a
TMPBOC49AF/-a
TECHNICAL DATA
PIN CONNECTIONS (TOP VIEW)
VCC(+SV)
TI
P27
P26
P25
P2~
PI?
PIG
F]S
Pl~
p] 3
P]2
PIl
~O
NC
PROG
P23
P22
P21
P20
P2~
P26
P27
Tl
Vec
TO
XTALl
XTAL2
TOP Vl EVI
tiC
Vss
DB7
DB6
nsrr
liS
DB~
... '"
l')
.to &r.l
It>
DBf
z...
NC: No
-656-
COllllf'f'11rJn
TOSHIBA INTEGRATED CIRCUIT
TMP80C49AP/-6, TMP80C39AP/-6
TMP80C49Af/-6
TECHNICAL
, DATA
BLOCK DIAGRAM
~.sy.
ROll.
lK "B
RAM
64 xB
PO"'£?
SAVE
:zu:
:r
u,
c ....
...;
>--0
"co
";t'"
u. t'"
~
..;
0
:r
""
l';
~
....
Z:Z
"c"';
Cl';
...;?t
H
c:
'"
"c
..;
'U
C
...;
tr;,r>:
t5~
h~
...;%
~.
t"'
I>to
t:<
'u.t"
Note 1)
Note 2)
tr..tr..
...;
....
~g
t"'
l';
~t; ...;:r
tr;.~
;:i!i'
:rl';
[I)
cr..u.
...;
:r
e:8
tr:r
p;~
It:
eGo
~~
!Ie";
0:tt
P;
[J;
~>i
!Ie"c
o~
tt:z
l';e
'"
!Ie
0
tt
P;
The lower order 4 bit of port 2 output latch are used
input/output operations with the I/O expander.
The output latch of port 0 is also used for address output.
-657-
also
for
TOSHIBA INTEGRATED CIRCUIT
TMP80C49AP/-e, TMPlOC39AP/-a
TMPlOC49AF/·e
TECHNICAL DATA
PIN NAMES AND PIN DESCRIPTION
VSS (Power Supply)
Circuit GND potential
VCC (Power Supply)
+5V during operation
PS (Input)
The control
Low)
si gnal
for
the power saving at
the
power
down mode
(Act i ve
PROG (Output)
Output strobe for the TMP 82 C43P I/O expander.
PIO - P 17 (Input/Output) Port I
8-bit quasi-bidirectional port (Internal Pullup
P20 - P27 (Input/Output) Port 2
8-bit quasi-bidirectional port (Internal Pullup
50KQ) .
=
50Kn).
P20 - P23 contain the four high order program counter bits during an external
program memory fetch and serve as a 4-bit I/O expander bus for the
TMP8243P.
DBO - DB7 (Input/Output, Tri-State)
True __£idirectional port which can be written or read synchronously using
the RD, WR strobes.
The port can also be statically latched.
Contains
the 8 low order program counter bits during an external program memory
fetch, and receives the addressed instruction under the control of PSEN.
Also contains the address and data duri~ an external RAM data store instruction, under control of ALE, RD, and WR.
TO (Input/Output)
Input pin testable using the c:;nditional transfer instructions JTO and
JNTO. TO can be designated as a clock output using ENTO CLK instruction.
Tl (Input)
Input pin testable using the JT1 and JNTI instruction.
Can be designated
the event counter input using the timer/STRT CNT instruction.
INT (Input)
External interrupt input. Initiates an interrupt if interrupt is enabled.
Interrupt is disabled after a reset.
Also testable with conditional jump
instruction. (Active low)
RD (Output)
Output strobe activated during a Bus read.
Can be used to enable data
onto the Bus from an external device.
Used as a Read Strobe to External
Data Memory (Active Low).
WR (Output)
Output strobe during a Bus write (Active Low).
External Data Memory.
-658-
Used as a Write Strobe to
TOSHIBA INTEGRATED CIRCUIT
TMP80C49AP/·6, TMPBOC39AP/·6
TMPBOC49AF/·6
TECHNICAL DATA
RESET (Input)
Active Low signal which is used
during the power down mode.
to
initialize
the Processor.
Also used
ALE (Oupput)
Address Latch Enable.
This signal occurs once during each cycle and is
useful as a clock output.
The negat ive edge of ALE strobes address into
external data and program memory.
PSEN (Output)
Program Store Enable.
This output occurs only during a fetch to external
program memory (Active Low).
S5 (Input)
Single step input can be used in conjunction with ALE to "single step"
processor through each instruction whe~ 55 is low the CPU is placed into a
wait state after it has completed the instruction being executed.
Also
used during the power down mode.
EA (Input)
External Access input which forces all program memory fetches to reference
external memory.
Useful for emulation and debug and essential for testing
and program verification. (Active High)
XTAL 1 (Input)
One side of crystal input for internal oscillator.
nal source.
XTAL 2 (Input)
Other side of crystal input.
-659-
Also input for exter-
nCS-43 LIST OF
~
~
I~
~nc'lOnic
XRl
XRl
XRl
A , Rr
A . ~Rr
A . Ii
I"C
DEC
ClR
1'110111
A • Rr
A . ~Rr
A . Ii
AOOC
ADOC
ADOC
A , Rr
A • ~Rr
A .1 i
~~t
I)
NIt
A . Rr
A . ~Rr
A .1 i
A~L
ORL
ORt ..
a ORl
,
A . Rr
A • ~Rr
A ,Ii
t
en
en
o
I
0
r
I
U
DA
c
SII~P
t
i
Rl
A
A
A
A
A
A
A
0
RlC
A
n
s
t
r
cn
flJr( t ion
Hex.
&8'r
6Q+r
03
ii
78'r
70+r
13
ii
58'r
50+r
53
ii
F7
~8'r
~O'r
~3
ii
D8'r
OO'r
03
ii
17
07
27
37
57
47
E7
n
RR
A
01110111
77
RRC
A
01100111
67
IN
I
I
0
A , Po
'f
FlaQ yc Ie
(2rx1)
Bin.
Ol101rrr
0110000r
00000011
iiiiiiii
01111rrr
Dl11000r
00010011
iiiiiiii
01011 rrr
0101000r
01010011
iiiiiiii
0100lrrr
0100000r
01000011
iiiiiiii
11011rrr
1101000r
11010011
iii iii i i
00010111
00000111
00100111
00110111
01010111
01000111
11100111
ADO
ADO
ADO
c
c
I
LIST OF IHSTROCTlCl(S
...
0
(21~)
en
1
Object ewe
(1st)
Assc~bler
A
•u
TlCS-~8
I~STROCTlOMS (1!~)
00001000 08'0
I
C. ~C
(A)o-(A)'(Rr)
(A)o-(A)'((Rr)]
(A)o-(A)'i
(A) 0-( A)' (Rr)' (C)
(A) o-(A). (( Rr)]- (C)
(A)<-(A)·i·(C)
r'0~7
~O.1
1'-0~7
r,O, 1
t!
!!
2
t!
t!
!!
1
1
1'-0.1
:I:
ID
:It
F)aQ ycle
C. AC
P-I.2
2
I
ANl
2
I
1
1
r~~7
Po, A
Object Cwe
( 1st)
fUr(t ion
(2m,)=Bin.
Hex.
00111000138-0 (Po) <-(A)
z
H
(A) o-(A) 1\ (Rr)
(A)<-(A) 1\[(Rr)]
(A)<-(A) 1\1
Hnc!lOnic
OUll
1
1
tt
Assembler
P
U
ORl
INS
r oun
2
Po, Ii
10011000 98-0
iiiiiiii
ii
Po, Ii
10001000 88'0
ii
i i ii iii I
A , BUS 00001000
08
BIJS. A 00000010
02
(PO) <-(Po)/\ I
P'I.2
2
(Po) <-(Po)v i
P~1
2
2
(A) ..... (BUS)
(BUS) ..... (AC)
(A) o-(A) v (Rr)
(A)o-(A) v[(Rrl!
(A) <-(A) vi
r-0~7
1
1
r'O.1
0
U ANl
T
P ORl
U
T
2
~0~7
1
1
2
r'O.1
!
1
1
1
1
1
1
1
n=0~6
1
1
n=O~6
1
n=0~6
t
1
n=0~6
P'I.2
2
-
BUS, Ii
10011000
iiiiiiii
10001000
iiiiiiii
m
rT1
C)
I
:;::c
»
--t
()
2
rT1
>
2
(BUS)<-(BUS) /\ 1
98
ii
88
il
0
r-
()
0
>
>
2
:;::c
()
-I
(BUS)+-(Bl'S) vi
I
0-1~7
A , Po 00001100 oc-o (A)<3 0> ..... (Po)
(A) ..... 0
oc~~7
HOVO po. A 00111100 3C'0 (Po) +-(A)<3 0>
ANI.O Po. A 10011100 9C'0 (Po) <-(Po)/\ (A)<3.0> p-~~7
IA)<3 0> 0-·'~7
1- o~~ ~~()l1P0 ~ _P)jlL'::JI~Q1V
r~0~7
00011 rrr 18'r (Rr) <-(Rr)-1
IHC
Rr
aRr
(I) IHC
r-O. I
OOOIOOOr 10'r [(Rr)] <-((Rr))'1
(Rr)
<-(RrH
r'0~7
Rr
11001rrr C8'r
DEC
JHP
aiiOOlOO al1~4 (PC)<10:0> <-a
a
(PC) <-(OSF)
aHl
B JHPP IA
10110011
B3 (PC)<7:0><-PRO[(PC)<11 8>· (Al]
ro~7
r OJHl Rr, a
11101 rrr E8-r (Rr) <-(Rr)-I
i f(Rr) *Othen(PC)<7'0><-aHL
a
aHl
else no ooer:ltion
n
11110110
F6 If(CH then(PC)<7 O><-aHl
c JC
a
h
aHl
else no operation
JNC
a
11100110
£6 i f(C)'O thenIPC)<7 O><-aHl
else flO operation
I
aHL
a
11000110
C6 i F(A)=O thenIPC)<7 O><-aHl
n Jl
else no orerMlon
s
aHL
t JNl
a
10010110
96 if(A) -to then(PC)<7.0> <-aHl
aHl
else no onoration
JTO
a
00110110
36 if TO,I then(PC)<7.0><-aHl
aHl
else ~_0l'el'at.,!,n
(1) ...... ReQister Instruction
HOVO
(AJo-(A)·1
(A)o-(A)-1
(A)<-O
(A)<-NOT(A)
(A)<-(A)BCO
(A)<7.4> ~(A)<3.0>
(A) .... (A)
(A) ..... (A)<7>
(A) ..... (A)
(C) .... (A)<7>
(A) .... (C)
(A) <-(A)
(A)<7> .... (A)
(A) .... (A)
(C)<-(A)
(A)<7> .... (C)
(A)<-(Po)
BUS, .i
-I
()
Z
/
(A) .... (A) v(Rr)
(A) .... (A) v((Rr)]
(A)<-(A) vi
--t
2
C
--t
I
2
2
I
2
2
I
I
I
2
2
2
2
2
2
2
2
-t -t
5151
;:;:
c:::t c:::t
aa
»
..
~~
m!"
-t
51
;:
c:::t
n
Col
CD
>
~
m
TlCS-fS L1S1 OF IMSIR1!:lI(l1(S
~Ib
~ssel'bler
Mne~onic
J~lO
a
e
Jll
a
a
~11
a
r
n
c JFO
a
h
JFl
I
Ol
Ol
.....
a
JH
s
,
t
JIll
r
-
u
a
-
a
0
g~~
runct ion
B,n
Hex,
(){)100110
26
aHl
01010110
56
aMl
01(){)0110
46
aHl
10110110
86
aHl
01110110
76
aHL
(){)o10110
16
aHL
10000110
8G
aHL
r lao pycle
i I TOoO then(PC)<7 O><-aHl
else no operation
i I I", then(PC)<7 O><-aHl
else no oocration
il T1·0 then(PC)<7:0><-aHl
else no operation
i I rO ol then(PC)<7 O><-aHl
else no operation
il Fl=1 thcn(PC)<7.0><-aHL
else no operat ion
if TF=1 thcn(PC)<7:0><-aHl
else no oocration
if INT =0 thcn(PC)<7:0><--aHL
else no operation
Hne'onlc
~
C, AC
2
2
2
H
I
I
v
e
I
n.
s
2
2
Rr ,I i
HOV
~Rr,1
HOV
HOV
XCH
XCH
XCHO
HOVX
HOVX
HOVP
A, PSW
PSW, A
A Rr
A, 'Rr
URr
'Rr,A
A 'Rr
A, ~A
A,iA
A,I
T, A
T
GMT
JBb
a
CAll
a
(2) RET
RETR
I
CPltR
I (3)' CLR
CPL
CLR -CPL
HOV
HOY
(4) HOY
HOY
HOY
.n.
C
C
FO
FO
Fl
rl
A , Rr
A ,@Rr
A ,I i
bbbl0010 b.12
aHL
aHl0l(){) aH'I4>
aHL
-'000(){)11
83
1001(){)11
93
1(){)1 0111
101(){)111
97
A7
8J
95
A5
B5
FS'r
1(){)(){)101
if (A)=1 thcn
(PC)<7:0><-aHL
b·0~7
else no ooorat ion
[(SP)) <-(PSW)<7:4>· (PC)
(SP) <-(SP)'l
(PC)<10:0> +-a
(PC) +-(DSF)
(SP) +-(SPH
(PC) +-[(SP)]<11 :0>
(SP) +-(SPH
(PC) +-[ (SP) ]<11 :0>
(PSW)<7'4> <-[(SP)J
(C)<-O
(C)<-NOTlC)
(FO) +-Q
(FO) +-NOT(fO)
(Fl) <-0
1Ft) <-N01([I)
(A)<-(Rr)
r=O~7
(A)<-[(Rr))
1"0,1
(A) +-i
1(){)10101
101(){)101
10110101
11111 rrr
1111(){)Or Fa. I'
(){)l(){)o11
23
iii iii i i
ii
Rr, A 10101rrr -Ag·r (Rr)<--(A)
'R~, A_.'0'0?()(J~ A?,r I !(~~~l<--(A) ..
(f) •••••• Move
Instl'llction
2
t
IJf
~3
HOV
io HOV
STRT
en SIRI
rt SlOP
o EN
r DIS
.
.
i
iii i Ii I i
ii
110001 II
C7
07
28- r
20- r
30'r
90'r
80'r
A3
11010111
00101rrr
00100(){)r
0011000r
1001000r
1000aOOr
10100011
111(){)011
010(){)O10
011(){)o10
01010101
01(){)o101
01100101
00100101
00110101
mIT
TCNT]
ICNT!
2
roO, I
25
35
05
15
C5
05
E5
F5
75
Enable External InterruPt
Disable External Interrupt
(BS)+- 0
(8S)<- 1
(OBF) <-- 0
(OBF) +- 1
Enable Clock OUt[>J\ on 10
~2
62
55
45
6~
~
I2
r-0~7
(A) <-(PSW)
(PSW) <-(A)
(A) ~(Pr)
r=0-71
(A) ~[(RrJ]
r=O,1
(A)<3 O>~ [!Rr)<3 0>1 r=O,l
EXT[(Rr)] <-(A)
roO 1
(A) <--[XT[(RrJ]
r=O 1
(A) ~PRO[ (PC)<11 8>, (A))
(A) ~PRn[!PC)<11>' 0,,· (Al)
(A) <--(1R)
(TR)<-(A)
Start II~r
1
Start counter
Stop 11I1\')r/Counter
Enahle T,~~r/Co\lnter Interrupt
Disable li~er/Counter Interrupt
[3
I II
Flap
I
C AC j
-I
m
:c
I;
1
1
1
1
1
()
I
I~
;:0
R rn
}>
r-
0
-I
}>
I I~
I~
I
rn
C)
z »
000004
}>
!I :1
z:
000004
0
n
;:0
n
c
000004
I
(5)
2
11
2
0
n
t
r
0
I
1
I
I
I
C
I
1
1
1
I
I
1
1
2
EN
DIS
S[L
SEL
SEL
SEL
EHTO
I
I
RI\O
RBI
HBO
HBI
CLK
i00000101
(){)010tOl
11(){)0101
11010101
11100101
11110101
01110101
1
1
1
I
I
I
1
-I -I
-aa
ClCI
c::I c::I
..
:IIa :IIa
~~
-
at,!'l
HALT
1"0-7
r=O, I
10111rrr 88'r (Rr) <-I
liiii,ii
ii
1011000r BO'r [ (Rr))<--I
-
~cle
Funct, on
~THex
HOV
0
2
2
Object Code
(1st)
(2m)
Asscmbler
1111J
n
I
-~
Object COOe
c
t
i
en
:z:
11 C5-48 LIST OF INSIR1!:llOHS W4)
I
...s
I
n
(3/~)
...Q
(){)oOO(){)1
01 Hal t
no oprat ion
(5) , .... , AID Converter Instruction
(6) ..~ ... Other
~(6) HOP
(){)(){)(){)(){
()()
1
1
-I
C
I
c::I
n
Col
ca
:IIa
~
at
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPl0C4aAP/-6, TMPlOC3aAP/-6
TMPl0C49AF/-6
TMPSO C49AP ITMP SOC39AP ITMP SOC49AF ELECTRICAL CHARACTERI STI CS
ABSOLUTE MAXIMUM RATINGS
ITEM
I
I SYMBOL
Ivcc SUEEll Voltage (wi th resEe ct to GND (VSS»
I VCC
IInEut Voltage (ExceEt EA)
I VINA
IInEut Voltage (Onil EA)
I VINB
IPower DissiEation (Ta=70·C)
I PD
I TSOLDER ISoldering TemEerature (Soldering Timer 10 sec)
IStorage TemEerature
I TSTG
IOEerating TemEerature
I TOPR
I
I
I
I
I
I
I
I
RATING
-O.SV to +7V
-O.SV to VCC+O.SV
-O.SV to 13V
2 SOr!IW
260 ·C
-6S· C to ISO·C
O·C to 70·C
DC CHARACTERISTICS
TOPR=O·C to 70·C, VCC=+SV±lO%, VSS=OV, unless otherwise noted.
I SYMBOL I
PARAMETER
I TEST CONDITIONS I MIN. I TYP.I MAX. I UNIT I
IInput Low Volt~Except
I
1-0.5 I
I O.S I V I
IVIL
1_ _ _ _ _ _ _ 1
I
I
I
I
1_ _ lxTALl, XTAL2, RESET)
IVILI
IInput Low Volta~
I
1-0.5 1 - - I 0 : 6 I - v - 1
I
I (XTALl, XTAL2, RESET)
I
I
I
I
I
I
1~IInput High Vol!.~(E~ept I
12Y1--I---vcGI-v-1
1_ _ _ lxTALl, XTAL2, RESET, PS)
I
I
!
I
IVIHI
IInput High Voltage(Except
I
1~1--I---vcGi-v-1
1_ _ _ lxTALl, XTAL2, RESET, PS)
I
Ix vcci
1
I
I VOL
IOutput Low Voltage
I IOL=1.6mA
1 - - 1 - - 1 0.451-'-'1_ _ _ 1 (Except PIO-PI7, P20-P27)
I
!
I!
iVOLl
!Output Low Voltage
I IOL=l.2mA
- - - - : 0.45;-'-'I
I(PlO-Pl7, P20-P27)
1-::-:-:::---:--:--:--__
!
IVOH11 IOutput High Voltage
IIOH=-l.6mA
12"":'"4:--,-- - V 1_ _ _ 1 (Except P lO-P 17, P 20-P 27)
I
I
I IOH=-400IJA
Ivcc- 1 - - - - - V IVOHl2 IOutput High Voltage
1_ _ _ 1(ExceEt PlO-Pl7, P20-P27)
I
I O.S!
IVOH21 IOutput High Voltage
IIOH=-SOIJA
12"":'"41-----vI
I(PlO-Pl7, P20-P27)
I
I
I
IVOH22 IOutput High Voltage
IIOH=-2SIJA
Ivcc- 1 - - - - - V I
I (PlO-P17, P20-P27)
I
I o.sl
1u:-r--IInput Leak Current
IVSS<
-<
:G
N
..;.
20
><
-<
:::
o
r-____________S~1.~3~~~IA~X~·__________________~
'"
:z
i
.~
:~~~(,
0.5
1. 4
Note: 1.
2.
± 0.15
± 0.15
2.54 ±0.2S
{~ 025~:i5
A0-15°
This dimension is measured at the center of bending point of leads.
Each lead pitch is 2 • 54mm , and all the leads are located wi thin
±0.2Smrn from their theoritical positions with respect to No.1 and
No .40 leads.
-676-
TOSHIBA INTEGRATED CIRCUIT
TMP80C49AP/-e, TMP80C39AP/-e
TMPBOC49AF/-e
TECHNICAL DATA
OUTLINE DRAWING (FLAT PACKAGE)
l11i
Q:lb
I
08 Pl1 CH
I
14 O±O 1
(l7.6±O:l)
18 o± 0.25
to---
J
'II.
K
..:
:>:
MARK
~-l
1
J..LJ..U.lJ...l U u U U U
T
l
~.2±O:l
-677-
(12±O2)
(06)
It)
t:
'"
"'
J
J
~
.,
~
INTEGRATED CIRCUIT
TOSHIBA
TECHNICAL DATA
-678-
TMPBOC49AP/-S, TMPBOC39AP/-S
TMP80C49AF/-8
TOSHIBA INTEGRATED CIRCUIT
TMP80C50AP/-6, TMP80C40AP/-6
TMP80C50AF/-6
TECHNICAL DATA
8-BIT SINGLE-CHIP MICROCOMPUTER
TMP 80 C50AP /TMP 80C50AP- 6
TMP80C40AP /TMP80C40AP-6
TMP 80C50AF /TMP 80 C50AF- 6
GEI--:ERAL DESCRIPTION
The TMP80CSOA is a single chip microcomputer fabricated in Silicon Gate OIOS
technology which provides internal 8-bit parallel architecture.
The following basic architectural functions of a computer have been included
in a single chip; an 8-bit CPU, 256 x 8 RAM data memory, 4K x 8 ROM program
memory, 27 I/O lines and an 8-bit timer/event counter.
The TMP80CSOA is particularly efficient as a controller.
It has extensive bit
handling capability as well as facilities for both binary and BCD arithmetic.
The TMP80C40AP/-6 1S the equivalent of a TMP80C50AP/-6 without ROM program
memory on chip. By using this device with external EPROM or Rfu'l, software
debugging becomes easy.
The TMP80C50AP /-6 and TMP80C40AP /-6 are in a standerd Dual Inline Pakage.
The TMP80CSOAF /-6 is in a 44-pin Flat Package.
FEATURES
TMP80C50AP /TMP80C40AP /TMP80C50AF
1.36ws Instruction Cycle Time
O'C to 70'C, 5V±10%
TMP 80 CSOAP -6/TMP 80C40AP -6/TMP 80CSOAF-6
2,5~s Instruction Cycle Time
-40'C to 8S'C, 5V±20%
Software Upward Compatible with
TMP80C49AP /TMP80C49AP-6/INTEL' s 8049
HALT Instruction (Additional Instruction)
4K x 8 masked ROM
256 x 8 RAM
27 I/O lines
Interval Timer/Event Counter
-679-
Low Power
lOrnA MAX. in Normal Operation
(VCC=5V,fXTAL=6MHz)
10~AMax. in Power Down Mode
(VCC=SV, fXTAL: DC)
Single Power Supply
Power Down Mode (Stand-by Mode)
Halt Mode (Idle Mode)
TOSHIBA INTEGRATED CIRCUIT
TMPlOC50AP/-&, TMP80C40AP/-&
TMPlOC50AF/-&
TECHNICAL DATA
PIN CONNECTIONS (TOP VIEW)
VCC (+5V)
Tl
Pn
P26
P25
P 21j
Pl7
PH,
F 15
P11j
P13
P12
Pll
~Q
PROG
P23
Pn
P2]
P20
NC
P2f>
P26
P2?
'.1'1
Vce
'.I'OP Vl EW
P23
P22
P21
P20
NC
Vss
'.1'0
)cTAL1
DB?
DB6
DB!>
DlU.
-680-
TOSHIBA INTEGRATED CIRCUIT
TMP80C50AP/-6, TMP80C40AP/-6
TMP80C50AF/·6
TECHNICAL DATA
BLOCK DIAGRAM
INSTf:"" to
"'H
t-<'" 1i;Z;
"'..,
.., Ct>: !;!i
..,z F:t-<
~
t'J
~E; ~;¥
PO.
;:j!i
tf.Ir-r:;
cr,
H
..,""c::
."
..,~
C
..,'"
~.
t-<
:>0
fi
tI..
lrt>:
..,
til
tt;.L0
~
0
28
tr!:o
1'::>-
'"
"'0
....;:>
~'"
O~
::ir;:
~'"
0>
t::
t::z
F:t::
tr.
~
t>:
t>:
tr
t>:
tu,
Note 1)
Note 2)
The lower order 4 bit of port 2 output latch are used
input/output operations with the 1/0 expander.
The output latch of port 0 is also used for address output.
-681-
also
for
TOSHIBA INTEGRATED CIRCUIT
TMP80C50AP/-6, TMP80C40AP/-6
TMP80C50AF/-6
TECHNICAL DATA
PIN NAMES AND PIN DESCRIPTION
VSS (Power Supply)
Circuit GND potential
VCC (Power Supply)
+5V during operation
PS (Input)
The control
Low)
signal
for
the
power
saving at
the
power
down mode
(Active
PROG (Output)
Output strobe for the TMP82C43P I/O expander.
PIO-PI7 (Input/Output) Port I
8-bit quasi-bidirectional port (Internal Pullup
50K[l) .
P20-P 27 (Input/Output) Port 2
8-bit quasi-bidirectional port (Internal Pullup = 50K[l).
P20-P23 contain the four high order program counter bits during an external
program memory fetch and serve as a 4-bit I/O expander bus for the
TMP8243P.
DBO-DB7 (Input/Output, Tri-State)
True bidirectional port which can be written or read synchronously using
the RD, WR strobes.
The port can also be statically latched.
Contains
the 8 low order program counter bits during an external program memory
fetch, and receives the addressed instruction under the control of PSEN.
Also contains the address and d~a duri£g an external RAM data store instruction, under control of ALE, RD, and WR.
TO (Input/Output)
Input pin testable using the conditional transfer instructions JTO and
JNTO. TO can be designated as a clock output using ENTO CLK instruction.
(Input)
Input pin testable using the JTl and JNTI instruction.
Can be designated
the event counter input using the timer/STRT CNT instruction.
INT (Input)
External interrupt input. Initiates an interrupt if interrupt is enabled.
Interrupt is disabled after a reset.
Also testable with conditional jump
instruction. (Active Low)
RD (Output)
Output strobe activated during a Bus read.
Can be used to enable data
onto the Bus from an external device.
Used as a Read Strobe to External
Data Memory (Active Low)
WR (Output)
Output strobe during a Bus write (Active Low).
External Data Memory.
-682-
Used as a Write Strobe to
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP80C50AP/-6, TMP80C40AP/-6
TMP80C50AF/-6
RESET (Input)
Active Low signal which is used to initialize the Processor.
during the power down mode.
Also used
ALE (Oupput)
Address Latch Enable.
This signal occurs once during each cycle and is
useful as a clock output.
The negative edge of ALE strobes address into
external data and program memory.
psi"N
(Output)
Program Store Enable. This output occurs only during a fetch to external
program memory (Active Low).
SS (Input)
Single step input can be used in conjunction with ALE to "single step"
processor through each instruction when SS is low the CPU is placed into a
wait state after it has completed the instruction being executed.
Also
used during the power down mode.
EA (Input)
External Access input which forces all program memory fetches to reference
external memory. Useful for emulation and debug and essential for testing
and program verification. (Active High)
XTAL 1 (Input)
One side of crystal input for internal oscillator.
nal source.
XTAL 2 (Input)
Other side of crystal input.
-683-
Also input for exter-
-t
TLCS-18 LIST OF INSIROCTlONS (214)
, TlCS-48 LIST OF IHSTROCTJONS (1/4)
I
~
Asse~bler
~~'!!Onic
I~
~
• Rr
A .@Rr
A ,'i
ADO
ADO
ADO
AOOC
AOOC
ADOC
A , Rr
A • 'Rr
A ,Ii
A
c
c
,
u
,
u
a
t
en
CO
0
r
~
I
ML
AHLAHL
A . Rr
A ,~Rr
A ,Ii
ORL
ORL
ORL
A , Rr
--
A • ~Rr
A ,Ii
XRL
XRL
XRL
A , Rr
A . ~Rr
A . Ii
INC
OfC
CLR
A
A
A
(
n
s
t
r
IJ
cn
VA
SWAP
A
t
i
Rl
A
A
A
0
RlC
A
c
Object COIle
(1st)
(2nd)
Hex.
Bin.
01101rrr sg'r
0110000r 6O+r
00000011
03
iiiiiiii
ii
01111rrr 7g'r
0111oo0r 70'r
00010011
13
iiiiiiii
ii
01011rrr 58'r
0101000r 50'r
01010011
53
iiiiiiii
ii
01oo1rrr 48'r
0100000r 40'r
4.3
01000011
iiiiiiii
ii
11011rrr OS·r
1101000r oo'r
11010011
D3
iiiiiiii
ii
17
00010111
00000111
07
00100111
27
00110111
37
01010111
57
47
01000111
11100111
£7
11 110111
I(
(A)<-(A)+(Rr)
(A)<-{A)'[(Rr) J
{A)<-{AH
(A) <-(A)' (Rr)'(C)
(A)<-(AJ.[( Rr) ]'(C)
(A)<-(A)'i+(C)
(A)<-{A) I\(Rr)
(A)<-(A) I\[(Rr}]
(A) .... (A) 1\ i
0
A
01110111
77
RRC
A
01100111
67
IN -. A • Po
00001000 08'0
r=0~7
r=0.1
r=O~7
r·O,1
tr
tt
2
!!
1
1
2
tt
!!
r·~7
r=0,1
Assembler
I~
HnelllOnic
OUTl
1
1
tt
-:..m
I
"~
C. ~C
Pp, A
::I:
Object COIle
(1st)
(2nd)
Bin.
Hex.
oo1110pp J8.p
Flag ycle
Funct ion
I
C. AC
(Po) .... (A}
2
P'I,2
I
AHL
1
1
2
I
H
P
U
I
1
1
0
U ANt
ORt
INS
oun
(Pp) .... (Pp)/\ i
P'I,2
2
{Po} .... {Po)v i
P,1 2
2
10011000 98'0
iiiiiiii
ii
PO,li
10001000 88'0
iii i i ii i
ii
A , BUS 00001000
OS
BUS, A 00000010
02
(A)<-(BIIS)
(BUS) .... (AC)
BUS, Ii
(BUS) .... (BUS) I\i
2
(BUS)<-(BUS) vi
2
Po. 'i
2
I
I
2
(A)<-(A) 'f(Rr)
(A)<-(A) 'f[(Rr)]
(A}<-(A) 'fi
r'0~7
r·O, 1
2
r=0~7
1
1
2
r·O, 1
r
p
U
ORt
r
(A) .... O
I
(A)<-NOT(A)
{A)<-(A)BCO
(A)<7:4> ~(A)<3:0>
(A) <-(A)
(A) <-(A)<7>
(A} <-(A)
(C)<-(A)<7>
(A) .... (C)
(A) .... (A)
(A)<7> <-(A}
(A} .... (A)
(C)<-(A}
(A)<7> .... (C)
(A) .... (Po)
!
1
1
1
1
1
1
1
n=0~6
t
1
n=O~6
n·0~6
1
t
1
n=0~6
P·l,2
2
98
ii
88
ii
p,d~7
{A}<3 0> .... (Po}
(A}<7'd> .... 0
MOVO Po, A
00111100 3C·p (Po) .... (A)<3 0>
0'd~7
100111pp X'D (Po) <-(Po)I\(A)<3 0> o-d~7
AHlO Po, A
8C'o JPPl.!::.!PQ)V(A)<3 0> Q-l~7
t-- r?~I_D ~~~ rJg.~.9JJ.po
0(){)11rrr 18'r (Rr) .... (Rr)·1
r·O~7
IHC
Rr
QRr
(1) IHC
oo01000r 10'r [(Rr)] <-[(Rr)]'1
r·O.1
r-O~7
OEC
Rr
11001 rrr C8'r (Rr) <-{Rr)-1
all(){)100 aH'd (PC}<10'O> .... a
JHP
a
(PC)<11> .... {DSf)
aHt
B JHPP aA
10110011
B3 fPC}<7:0> .... PRO[(PC)<11.8>. {A}]
r OJHZ Rr. a
11101rrr £8'r (Rr) <-{Rr)-1
r'~7
a
aHt
i f(Rr} *Othen{PC)<7:0> .... aHl
n
else no operation
c JC
a
11110110
F61 if(CH lh€n{PC)<7.0> .... aHL
h
aHl
el~c no operation
JNC
a
11100110
[6
if(C)'O then(PC)<7'0><-aHt
(
aHt
else no oocratlon
11000110
n JZ
a
C61 i f(A)·O then(PC} .... aHl
s
aHl
else no operation
t JNZ
10010110
a
96 if(A)*O th€n(PC)<7'0> .... aHl
aHl
else no oocration
JTO
00110110
th€n(PC)<7.0> .... aHl
a
36 if
aHL
else no ooeratlon
(I) ...... ReQister InstructIon
A , Pp
(){)001100 OC'o
ro·,
-.----~--
m
rT1
()
C>
::I:
>
---t
Z
R
»
r-
:;:;0
rT1
0
---t
I
I
HOVO
(A} .... {A}·1
(A)<-{A)-1
BUS, Ii
10011000
iiiiiiii
10001(){)0
iiiiiiii
z---t
-i
n
0
:;:;0
»
-i
n
» c:
/
(A)<-(A) v(Rr)
(A)<-(A) v[(Rr)]
(A}<-(A) vi
f7
RR
Flag ycle
Function
n
I
I
a
en
2
2
2
II
2
1
1
1
2
2
2
2
2
2
_51
CICI
c»c::»
-t -t
nn
CII CII
C»c::»
z-
:Do
.:::!!~
m'p»
2
-t
2
;:
51
c::»
~
C»
z-
.
~
GJ
TlCS-le lIS1 Of
~...
INS1Rt(lI~S (3/~)
~sse1!bler
Object Code
HneMnic
S .
.IIITO
a
B JT1
r
a .IIITl
3
n
c JfO
3
h
a
JFj
I
n
In
3
JIll
a
5
t
r
u
OJ
CO
0'1
I
1
g~:
funcl ion
flaq ycle
~
C AC
if TO-O thcn(PCI<7:0>4--aHl
else no o(leration
if H=l thcn(PC)<7'0>4--aMl
else no oocration
if 11=0 thcn(PC)<7:0>'-aMl
else no oocral ion
if fo-l then(PC)<7:0><-aML
else no O(leral ion
if fH then(PC)<7:0>4--aHL
e Iso no operat ion
if H=1 then(PC)<7:0><-aML
else no o(leration
if INT -0 then(PC)<7:0><--aHL
else no o(lerat ion
2
M HOV
2
v t10V
e
2
I
2
I\.
2
t
s
2
TC
10
IIIU
en
rt
o
r
a
CAll
3
bbblool0 11<12
aHl
n
(2) REf'
,
aHl0loo aH-I41
aHL
-,
R[li!
CLR
CPl
1(3),m
CPl
CLR
t10V
IfJV
(I) IfJV
IfJV
IfJV
(2)
(I)
"
83
10010011
93
10010111
97
10100111
A7
10000101
85
10010101
95
10100101
A5
10110101
85
l1111rrr fS+r
l111000r FO+r
00100011
23
iii iii i i
ii
(Rr)--(A)
M+r
Rr. A 10101rrr
r=0-7
i (Rr)]<-(A)
1010000r
AO+r
r=O, 1
'Rr. A
...... Subroutine Instruction (3) ...... flag Instruction
...... Hove Instrutt ion
C
C
fO
FO
fl
fl
A • Rr
A .'Rr
A •ti
crt
';0006011
if (A)=l then
(PC)<7:0>4--aMl
elso no o(lerat ion
b-0-7
[(SP)) 4--(PSW)<7:4>· (PC)
(SP) --(SP)+1
(PC)<10:0> __ 3
(PC)<11> <-(OBr)
(SP) --(SP)-1
(PC) --[(SP))<11 :0>
(SP) --{SP)-1
(PC) 4--[(SP)]<11:0>
(PSW)<7:4> 4--[(SP)l
(C) ...O
(C)--H01(C)
(FO) <-0
(FO) <--M01(FO)
(fl) --0
(F1) <-HOT(f1)
(A)4--(Rr)
r·0-7
(A)<--[ (Rr))
r=0.1
(~) <--i
Rr.' i
'Rr.' i
0
t
i
JBb
HneMOnic
t10V
2
c
0
Object Code
(1st)
(2n· (All
(A) ... PR0[(PC)<11>· 011· (Al)
(A)<3,O>~[(Rr)<3
0»
Ii
I~
(1R)"'(A)
Start TIf€r
Start counter
Ston Tllner/Counter
[na~le TllerfCounter Interrunt
Disable Ti~pr/Countcr Interrunt
II
()
m
rn
G)
:I:
;::0
-I
I
I
»
--I
Z
()
rn
0
»
r-
("")
0
;::0
»
-i
("")
» c
!~
(A) "'OR)
z:
--I
2
I~
I~
I 1
I~
--I
I~
I
I
(5)
~cle
I
(Rr)4--1
(A) ... (PSW)
(PSW) "'(A)
{AI ~(Rr)
(A) ~[(Rr))
UJ
%
2
11
2
1
1
1
1
1
1
1
1
2
1
1
0
n
t
r
0
I
I
I
C
EM
DIS
SEt
SEl
SEL
S[l
EMTO
I
I
RI\O
RBI
HBO
HBI
eLK
i00000101
00010101
11000101
11010101
11100101
11110101
01110101
05 Enable External Interrupt
15 Disable External Interrupt
C5 (8S)-- 0
05 (85l- 1
E5 (DBr) ... 0
F5 (OBr) -- 1
7S Enable Clock OUtM on TO
HALT
00000001
01 Halt
(6) MOP
OOOOOOOO
00 no oprat Ion
(5) ...... AID Converter Instruction
(6) ...... Other
I
I
,
,
1
1
1
1
1
1
1
1
1
-t ....
BB
;B;B
c::t c::t
nn
en
c::t
CII
Q
:a:- :a:.::::!~
i
mt-
....
B
;:
Q
....
n
Q
:a:-
~
=
TOSHIBA INTEGRATED CIRCUIT
TMP80C50AP/-6, TMP80C40AP/-6
TMP80C50AF/·6
TECHNICAL DATA
"
TMPBOC50AP /TMPBOC40AP /TMPBOC50AF ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
I SYMBOL
I
ITEM
I
RATING
I_V--,Co..,C~__ IVCC Supply Voltage (with respect to GND (VSS» I -0.5V to +7V
!Input Voltage (Except EA)
1--0::-.'-:5'""V:--t':'-o-:\"""C~C-+-=-0-;.5:-:CV:-1
I VINA
I VINB
i~In:.:JpLu::::t"--O:V-"'-o-=-I':':ta::Jg"'e'--'(-:::o:.:c.n::-IY=:E:-:A...:;:)::.:c..---------1 -0.5V to l3V
I_P::-D~~=-iF::-,:.:JowLe::::r~D~i~s':':sl~op~a~t~i~o:.:c.n~(T~a~-~7~07'~C')--------I~~~~25::-~~,~~~--
! TSOLDER ISoldering Temperature (Soldering Time 10 sec) I
I TSTG
I TOPR
260'C
!---:-65::-:-'C=-=t"'o-'-:-1-=-50::-'''''C:---
IStorage Temperature
!70~p':':er::::a~t~i~n~g~T~eLmLp~e~r~a~t':':ur-e-------------1-0~·~C~t-o.:.:7:-:0~·~C~~-
De CHARACTERISTICS
TOPR=O'C to 70'C, VCC=+5V±10%, VSS=OV, unless otherwise noted.
I SYMBOL I
PARAMETER
I TEST CONDITIONS I MIN. I TYP. I MAX. I UNIT I
IInput Low Volt~Except
I
1-0.5 I
I O.B! V I
IVIL
I
I
I
I
I
I
I
IXTAL1, XTAL2, RESET)
1~IInput Low Volta~
I
1-=0:-51--IOTI-v-1
I
I (XTAL1, XTAL2, RESET)
I
I
I
I
I
I
1~IInput High Vol~(E~ept I
1--z:-2!--I--VCCI-\-'I
! XTALl, XTAL2, RESET, PS)
I
I
I
I
I
1'ViHlllnput High Volt~ _
I
1~1--I--VCCI-vI
I (XTALl , XTAL2, RESET, PS)
I
Ix veci
I
I
1~IOutput Low Voltage
IIOL=I.6mA
1 - - 1 - - 1 0.451-v!
: (Except PIO-PI7, P20-P27)
i
I
I
i VOLl iOutput Low Voltage
I IOL=l. 2mA
--I--I0.4si-V:
:(PIO-P17, P20-P271
I
I
I
I
I
IIOH=-1.6mA
12.41--I--I-vIVOHII 10utput High Voltage
1_ _ _ I(ExceptPlO-P17,P20-P271
I
I
I
!
!
IVOH12 10utput High Voltage
I IOH--40011A
Ivcc- I - - I - - I - v 1_ _ _ i(ExceptPIO-P17,P20-P271
I
10.BI
I
I
[ VOH2l 10utput High Vol tage
IIOH--5011A
12.41-- --I-vI
I (p 10-P 17, P 20-P 27)
I
I
I
I
IVOH22 °iOutput High Voltage
IIOH--2511A
ivcc- 1 - - - - I - v I
I(PlO-P17, P20-P271
I
I o.BI
I
I
In:r-Ilnput Leak Current
IVSSle memory and
lK x 8 masked ROM
PIN CONNECTIONS
(To~
iO
Single leve:
1~terrupt
Single SV supply
-40'C to +8S'C Operation
View)
TO
XTALI
XTAL2
RESET
SS
Vee
INT
P24
Tl
P27
(+5V)
P26
P2S
EA
P17
P16
PIS
P14
P13
P12
PH
PIO
VDD(+SV)
PROG
P23
P22
RD
PSEN
"'R
ALE
DBO
DBI
DB2
DB3
DB4
DBS
DB6
DB7
(OV)VSS
P21
P 20
-703-
INTEGRATED CIRCUIT
TOSHIBA
TECHNICAL DATA
TMP8048PI, TMP8035PI
BLOCK DIAGRAM
O~cillation
2
Frequency
Nask ROM
IK x 8
(Program
Area)
Control and Timing Circuit
55
H
0
"....c: "',......"
'U
III
.....
'0"
rt
'1
:>:J
HH
::> ::>
'" ""c:
(J)
It
....
ro
M
"''1
'1
H
::>
'"
c:
M
Q.";
'1 x
'"
M
til '1
'"
OJ
::>
....::>
U>
00
.....
ALE
PSEN Ri5
U>'U
t-'> ....
'"
0. ... '1
0
nO.
o
00
" '1
::>"'"
0"'1
'" "'"' '" S'"
ro
rt
...0
'"rt "''''
ro > ro
c:
i-'
I-'
"
rt
Ul
, '"
0.
OJ
rt
0"
ro
Wi(
t:'
-----------
'"
M
'"
til
...0
rt
PROG
u>,,;
n X
...0'"'"
Note 1) The lower order 4 bits ~' f
port 2 output latch are
used also for input/output
operations with the I/O
expander .
0"::>
ro 0.
...ro
0"
ro
'"
-704-
Note 2) The output lat ch of port
is also used for address
output.
a
TOSHIBA INTEGRATED CIRCUIT
TMP8048PI, TMP8035PI
TECHNICAL DATA
PIN NAMES AND PIN DESCRIPTION
VSS (Power Supply)
Circuit GND potential
VDD (Power Supply)
+5V durin!, operation Low power standby pin for TMP8048 RMl
VCC (Main Power Supply)
+5V during operation
PROG(Output)
Output strobe for the TMP8243P I/O expander
FlO-PI7 (Input/Output) Fort 1
8-bit quasi -bidirectional port
(Internal Pullup=50kQ).
P20-P27 (Input!Outnut) Port 2
8-bit quasi-bidirectional port (Internal Fullup=50kQ).
P20-P23 Co~tain tl-je four hi?~ order pr0:;;ro-r::. C0U!1ter bjts dtlrin~ an
external pro~raG m2QOry f€tc~ a~d serve as a ~-bit i/O expa~der bus for
the TM?8243P.
DBO-DB7
(Ir:cL!!:: /Out;::..:.t.
3 State:1
:~,.;:: E ::'-'v' :J:'C-::::- :=r.:;~r=-:.-:.- =:. ....:-~:._:-=- ::::3 ':-"::-:=-.2 2:'. '2X:'2:-::~: :-=-_2:-8-: ::,.-::=-.::--",'
fetch, and receives the addressed instruction under the control of
Also contains the address and data during an external RAM data store
instruction, under control of ALE, RD, and WR.
PSEN.
TO
(Input/Output)
Input pin testable using the conditional transfer instructions JTO and
J~fO.
TO can be designated as a clock output using ENTO CLK instruction.
11
(Input)
'\
Input pin testable using the JTl and JNII instruction.
Can be designated
the event counter input using the timer/STRT CNT instruction.
INT
(Input)
External interrupt input.
Initiates an interrupt if interrupt is
enabled.
Interrupt is disabled after a reset.
Also testable with
conditional jump instruction.
(Active Low)
RD
(Output)
Output strobe activated during a Bus read.
Can be used to enable data
onto the Bus from an external device.
Used as a Read Strobe to External
Data Memory (Active Low).
WR
(Output)
Output strobe during a Bus write (Active Low) Used as a Write Strobe to
External Data Memory.
-705-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8048PI, TMP8035PI
RESET CInputl
Active Low signRl which 1S used to initialize the Processor.
during Power down.
Also used
ALE
(Output)
Address Latch Enable. This signal occurs once during each cycle and is
useful as a clock output. The negative edge of ALE strobes address into
external data and program memory.
PSEt;
(Output)
PrograM Stor~ Enable. This output occurs only during a fetch to external
program memory (Active Low).
SS (Input)
Single step input can be used in conjunction with ALE to "single step"
processor through each instruction when
is low the CPU is placed into
a wait state after it has completed the instruction being excuted.
SS
EA (Input)
External Access input which forces all program memory fetches to reference
ex:e~~5: G~~:~~·.
~s2£~1 f2~ e~~lation a~j deb~~ a~d ess2n:ia: £2~ test~~;
and program ver1fication.
(Active High).
,:::;s:il:a::-:-.
in':'c..:.:
,~_
2X:err:.-
s::....:;-:::::.•
Other side of crystal input.
FUNCTIONAL DESCRIPTION
1. System Configuration
The following system functions of the TMPS04S are described in detail.
0) Program Xemory
(6)
Stack (Stack Pointer)
(2)
Data Memory
(7)
Flag 0, Flag 1
(3)
I/O Port
(S) Program Status Word (PSW)
(4) Timer/Counter
(9) Rese t
(5) Interrupt Control Circuit
(10) Oscillator Circuit
(1) Program Memory
The maximum memory that can be directly addressed
4096 bytes. The first 1024 bytes from location 0
internal resident mask ROM. The rest of the 3072
memory are external to the chip. The TMPS035 has
memory; all memory must be external.
-706-
by the TMPS04S is
through 1023 can be
bytes of addressable
no internal resident
TOSHIBA
Th('re
INTEGRATED CIRCUIT
TMP8048PI, TMP8035PI
TECHNICAL DATA
ell t'
t
hrel' locat ions In Frogram
M~mc)r\'
of spe..:: i
,l.~
importance.
Address
4095
Memory Bank 1
2048
2047
1024
Memory Bank 0
1023
Program Memory Area
Location 0
Activating the ReSet line of the processor causes the first instruction to be fetched from Location O.
Location 7
A timer/counter interrupt resulting from a timer/counter overflow
(if enabled) causes a jump to a subroutine defined by address held ln
Location 7.
Program address 0-2047 and 2048-4095 are called memory banks 0 and 1
respectively switching of memory banks is achieved by changing the
most significant bit of the program counter (PC) during execution of
an unconditional jump instruction or call instruction executed after
using SEL MBO or SEL MBI.
Reset operation automatically selects Bank O.
(2) Data Memory
Resident Data Memory (volatile RAM) is organized as 64 words by 8-bits
wide.
The first 8 locations (0 -7) of the memory array are designated as
working registers and are directly addressable by several
instructions. By executing a Register Bank switch instruction (SEL
RBI) locations 24 - 31 are designated as the working registers in
pIa ce of 0 - 7.
-707-
TOSHIBA INTEGRATED CIRCUIT
TMP8048PI, TMP8035PI
TECHNICAL DATA
Address~--------------,
(,3
Data Memory
32
31
24
rRe;::i~~e~-ia-;:;k-lRBI
231----------8 Level Stack
8
(16 byte)
7 Resister Bank a
RBa
a '-------~
Internal Data Memory Area
RA~
locations 8 - 23 serve a dual role ix· t),a~ they contain the program
counter stack which is a stack 2 bytes wide bv 8 levels deep.
T~ese
Ic:~:i2ns store retur3i,g a~jresses fro= 5J~~)~~i~es.
If t~E :eve: c~
subroutine nesting is less than the permitted 8, you free up 2 bytes of
R&'1 for general use for every level of nesting not utilized.
:c.~
1::::S':)~8
architecture allows extension of the Data
~emory
to 256 words.
(3)Input/Output Ports
The TMP8048 has 27 I/O lines which can be used for either input or output.
These I/O lines are grouped into 3 ports each having 8 bidirectional lines
and 3 "test" inputs which can alter program sequences when tested by conditional jump instructions.
Ports 1 and 2 are each 8-bits wide and have identical characteristics.
Data written to these ports is statically latched and remains unchanged
until rewritten.
As input ports these lines are non-latching, i.e., inputs
must be present until read by an input instruction.
All lines of Ports 1 and 2 are called quasi-bidirectional because of a
special output circuit structure (illustrated in Figure 1). Each line is
continously pulled to a +5V level through a high impedance resistive device
(50kQ ) which is sufficient to provide the source current for a TTL high
level yet can be pulled low by a standard TTL gate thus allowing the same
pin to be used for both input and output.
In order to speed up the "0"
to "1" transition a low impedance device (5k(l ) is switched in momentarily
whenever a "1" is written to line. When a "0" is written to line a low
impedance device overcomes the pullup and provides TTL current sinking
capabi I i ty.
-708-
TOSHIBA INTEGRATED CIRCUIT
TMP8048PI, TMP8035PI
TECHNICAL DATA
ANL, ORL
+5V
+5V
SOHl
Internal
Bus--~~"--1
D
Q
D-Type
Flip-Flop
cn
Write
SOkD I/O pins
PortI or 2
Q~~---l
Pulse---t-~----------J
Inter Buffer
IN
Fig.I
Reset
~hen
initia~izes
all
Input/Output Circuit of Port 1, Port 2
lines to a h:gh
im~ed.ance
1'1"
s:ate.
external data memory area is not addressed during excution of an
intermixed.
As a static port data is written and latched using the OUTL instruction
and inputted using the INS instruction these two commands generate
pulses on the corresponding RD and WR strobe lines.
As a bidirectional port the MOVX instructions are used to read and write
the port which generate the RD and WR strobes.
When not being written or read, the Bus lines are in a high impedance
state.
(4)Timer/Event Counter
The 8-bit binary up counter can use either of the following frequency
inputs
(1) Internal clock (1/480 of OSC frequency)
.........•.. Timer mode
-709-
TOSHIBA INTEGRATED CIRCUIT
1MP8048PI, 1MP8035PI
TECHNICAL DATA
(2) External input clock form Tl terminal
(minimum cycle time 3 x ALE cycle)
Event Counter mode
The counter is presettable and readable with two MOV instructions
which transfer the content of the accumulator to the counter and vice
versa. The counter content is not affected by a Reset and is initialized
solely by the MOVT, A instruction.
The counter is
stopped by a Reset or
STOP TCNT instruction and remains stopped
until started by
START T
instruction or as an
event
counter by a START CNT.
Once started
the
counter will increment to its maximum count (FF) and overflow to Zero
continuing its count until stopped by a STOP TCNT instruction or RESET.
The increment from maximum count to Zero (overflow) results in the setting
of an overflow flag and the generation of an interrupt request. When
interrupt acknowledged a subroutine call to Location 7 will be initiated.
Location 7 should store the starting address of the timer or counter
service routine. The state of the overflow flag is testable with the
conditional Jll!1? (JTF). P,e flag is reset by excuting a JTF or bv R.::S;::,.
Figure 2 illustrates the concept of the timer circuit.
XTAL/1S
1/32
Pre-scaler
Cleared on Start Timer
JTF Instruction
8-Bit Timer!
Counter
Tl f-----IEdge Detector
n
Read/Write Enable
Timer Interrupt
Request Flip-Flop
INT
Timer Interrupt Enable
Fig.2
Concept of Timer Circuit
-710-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPB048PI, TMPB035PI
C0nditional Jump Logic
JTf
Inst ruction
Timer
nag F-F
R
Reset
Timer Overflow
QI---"
Timer
Timer Interrupt
Execution---....,-.....,
Overflow
~ t:...
g-~d.Q
"-l
R F-F
~
RETR
~ ~ ~
lnstruc- R ~ ~ ~
tion
H to 0
Reset
IKT pin
InterA:"E - - - " - - - .
Last
cr-
E::~
Ir:~!:r.J.:!:ic ...
--is
oJ
I
I
i
I
I
Reset---~~----------"
DIS TCNTl
Instruction
Instruction
Fig.3
Concept of Interrupt Control Circuit
(5) Interrupt Control Circuit
There are two distinct types of Interrupts in the TMP8048.
(1) External Interrupt from the INT terminal
(2) Timer Interrupt caused by timer overflow
-711-
TOSHIBA INTEGRATED CIRCUIT
TMP8048PI, TMPB035PI
TECHNICAL DATA
The interrupt system is single level in that once an interrupt is detected
all further interrupt requests are ignored until execution of an RETR
(which should occur at the end of an interrupt service routine) reenables
the interrupt input logic.
An interrupt sequence is initiated by applying a low level "0" to the INT
pin. INT is level triggered and active low which allows "Wire Dring" of
several interrupt sources. The interrupt level is sampled every machine
cycle during ALE and when detected causes a "jump to subroutine" at Location 3. As in any call to subroutine, the Program Counter and Program
Status Word are saved in the stack.
When an overflow occurs in the internal timer/event counter an interrupt
request is generated which is reserviced as outlined in previous paragraph
except that a jump to Location 7 is used instead of 3. If INT and times
overflow occur simultaneously then external request INT takes precedence.
If an extra external interrupt is needed in addition to I~7 this can be
achieved by enabling the counter interrupt, loading FF~ in the counter
(one less than the terminal count), and enabling the event counter mode.
A "I" to "0" transition on Tl will cause an interrupt vector to Location 7.
Figure 3 illustrates the concept of the interrupt control circuit.
(6) Stack (stack Pointer)
An interrupt or Call to subroutine causes the contents of the program
counter to be stored in one of the 8 register pairs of the Program Counter
Stack. The pair to be used is determined by a 3-bit stack pointer which is
part of the Program Status Words (PSW explained in section (8)). Data RAM
locations, 8 through 23 are available as stack registers and are used to
store the program counter and 4-bits of PSW as shown in the figure.
The stack pointer when initialized points to RAM location 8 and 9. The
first subroutine jump or interrupt results in the program counter contents
being transferred to Locations 8 and 9. Then the stack pointer is incremented by one to point to Locations 10 and 11. Eight levels of subroutine
are obviously possible.
At the end of a subroutine signalled by a RET or RETR causes the stack
pointer to be decremented by one and the contents of the resulting pair
to be transferred to the Program Counter.
-712-
TOSHIBA INTEGRATED CIRCUIT
TMP8048PI, TMP8035PI
TECHNICAL DATA
I
I
23
I
22
I
I
I
I
6
21
20
I
19
I
I
I
I
5
18
I
I
I
17
1
16
,I
15
I
I
I
14
1
13
I
1
12
I
1
I
1
I
11
10
I
PC8 '" 11
---psw-- --+------I
o
PC4'" 7
I
PcO'" 3
n·v
""",,,
Sta:::1.:
Pointer
(7) Fla gO,
Fla g l,
9
8
Address
(FO, Fl)
lnsrr'-1c:ior;. j?u.
FO is a part of the program status word (PSW) and
area when a subroutine is called.
lS
saved in the stack
(8) Program Status Word (PSW)
An 8-bit status word which can be loaded to and from the accumlator exists
called the Program Status Word (PSW). The PSW is read by a HOV A, PSI{ and
written to by a HOV PSW, A. The information available in the PSW is shown
in the diagram below.
-713-
TOSHIBA INTEGRATED CIRCUIT
TMP8048PI, TMP8035PI
TECHNICAL DATA
Stack Pointer
/
! C ! AC I Fa ! BS 11
MSB
I
I!
1_______
11
Saved in stack area
at the time of Subroutine Call.
is 2 Is 1 I so
LSB
Spare ("I" during Read)
Bits 0 - 2
Bit 3
Bit 4
Stack Pointer Bits(SO, 51, 52)
Kot used ("1" level when read.)
Working Register Bank Switch Bit
(BS)
Bit 5
Flag 0 (fO)
Bit 7
Carry (C) flag which indicates that the ?re,"oous
operation has resulted in the accumulator.
(el
(9) Reset
The reset input provides a means for initialization or the processor.
This Schmitt trigger input has an internal pullup registor which in
combination with an external l~F capacitor provides an internal reset
pulse
sufficient length to guarantee that all internal logic 1S
initialized.
IHl
r-'-O-...Jv'I/Y--lv-
---1--......q
F
1
-714-
RESET
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8048PI, TMP8035PI
If the pulse is generated externally the reset pin must be held at ground
(~0.5V)for at least 50mS after the power supply is within tolerance .
• Reset performs the following functions within the chip:
( i)
Sets PC to Zero.
Sets Stack Pointer to Zero.
( iill Selects Register Bank O.
(iv)
Selects Memory Bank O.
(v)
Sets BUS (DBO - DB 7) to high impedance state. (Except when EA
(vi)
Sets Ports I and 2 to input mode.
(vii) Disables interrupts (timer and external).
(viii) Stops Timer.
(ix)
Clears Timer Flag.
(x)
Clears FO and Fl.
(xi)
Disables clock output from TO.
(ii)
(10) Oscillator Circuit
TI:?8J48 can be operated by the external clock input in additio:1 to
crystal oscillator as shown belo~.
+5\'
.....-_..+-_...:3,. XTAL 2
20 pF
2
T.J:/.J... 1
3
XTAL 2
~--~~--~---y
l
2. Basic Operation and Timing
The following basic operations and timing are explained
(1) Instruction Cycle
(2) External Memory Access Timing
(3) Interface with I/O Expander TMP8243P
(4) Internal Program Verify (Read) Timing
(5) Single Step Operation Timing
(6) Low Power Stand-by Mode
-715-
5V)
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8048PI, TMP8035PI
(1) Instruction Cycle
The instructions of TMP8048 are executed in one or two machine cycles,
and one machine cycle contents of five states.
Fig.4 illustrates its relationship with the clock input to CPU.
62 clock shown in Fig.4 is derived to outside by ENTO CLK instruction.
ALE can be also used as the clock to indicate the machine cycle as well
as giving the external address latch timing.
(2) External Memory Access Timing
(i) Program Memory Access
TMP8048 programs are excuted in the following three modes.
(1) Execution of internal program only.
(2) Execution of ~oth external and i~ternal ?rogra~s.
(3) Execution of externa: progra~ o~iy.
The external program memory is accessed (instructions are fetched)
aG:or::atically whE::": ::he i::t€!'"~a: RO~: E~~!'"ess is ex(:ee~e~ i:l r:~::!~ (2'
T~e contents of the 12-bit program counter will be output on BUS(DBO DB7) and the lower 4-bits of Port 2.
Address Latch Enable (ALE) will indicate the time at which address is
valid. The trailing edge of ALE is used to latch the address
externally.
Program Store Enable (PSEN) indicates that an external instruction
fetch is in progress and serves to enable the external memory device.
BUS (DBO - DB7) reverts to Input mode and the processor accepts its
8-bit contents as an Instruction Word.
Figure 5 illustrates the timing.
(ii) Access of External Data Memory
. In the extended data memory access operation during READ/WRITE cycle the
following occurs
The contents of RO Rl is output onto BUS (DBO - DB7).
ALE indciates address is valid. The trailing edge of ALE is used to
latch the address externally.
A read RD or write WR pulse on the corresponding output pins indicates
the type of data memory access in progress. Output data valid at trailing edge of WR and input data must be valid at trailing edge of RD.
Data (8-bits) is transferred over BUS.
-716-
TOSHIBA INTEGRATED CIRCUIT
TMP8048PI, TMP8035PI
TECHNICAL DATA
Xl,\l.1 lnpn!
(6MHz)
¢1
(2MHz)
Generated
internally cj>2
State
1
2
Instruction
Fetch
(500ns)
1 State
Decode
3
Execution
4
5
Execution
1
Execution
(2.5)1 sec)
r=
ALE
Next Address Latch Timing
(400KHz)
Fig.4
Address
Address
P20-P23
DBO -
Instruction Cycle Timing
Address
DB7
Instruction
ALE
~~I--~\~~I~I--~\~~II~~L
Fig. 5
Timing of External Program Memory Access
-717-
TOSHIBA INTEGRATED CIRCUIT
TMPB048PI, TMP8035PI
TECHNICAL DATA
Program Address
Data Address
Program Address
DBO - DB7
Instruction
ALE
RD (WR)
I
\
PSEN
\
r
\
I
External Data Memory Access Instruction
5ugg~st
Al.E
~\
we have diagrans
Read
A!..E
BUS
BUS
RD
\
Fig.6
I
WR
n
>.'rite
8--<
\
Timing of Accessing External Data Memory
-718-
Data
)-
I
TOSHIBA INTEGRATED CIRCUIT
TMP8048PI, TMP8035PI
TECHNICAL DATA
Figure 6 illustrat~s the timing of accessing the external data memory
during execution of external program.
(3)
Interface with I/O Expander (TMP8243P)
The TMP8048 I/O can be easily expanded using the TMP8243 I/O Expander.
THis device uSeS only the lower half 4-bits of Port 2 for commuication
with the TMP8048. The TMP8243 contains four 4-bit I/O ports which serve
as extensions of one chip I/O and are addressed as Ports (4-7). All
communication takes place over the lower half of port 2 (P20 - P23) with
timing provided by an output pulse on the PROG pin. Each transfer consists
of two 4-bit nibbles the first containing the "OP Code" and port
address and the second containing the actual 4-bits of data.
+12V r-____________________________________________________
EA
oJ
~.lf
/f
RESET OV_ _ _ _ _ _ _'?'f-___
DBO- DB7
Input of Internal
PD~
Address
Output of Internal
R(,~
Input of Internal
R'J~~
Dc.:a
Acdress
\ / i _ _ ....
c:
~7'.te.Ll.al
P20, P21 ____I_:-_.?_;J_t_c_-_~_:::_::_::_E_:::--_.._c._:_?_':_~_:_A_::_C_::_e_E_s_ _ _ _ _ _ _-JJ\;~;~-~ddress
Fig.7
Timing of
Rpadin~
Internal Program Hernor"
sv
SV
10K
55
R~
10K
SV
F-L
D
S
Q
S5
74
T
R
Q
ALE
Fig.8
(a) Single Step Circuit
-719-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPB048PI, TitPB035PI
Reading of Internal Program Memory
The processor is placed in the READ mode by applying +l2V to the EA pin and
OV to the RESET pin. The address of the location to be read is
then
applied to BUS and the low order 2-bits of Port 2. The address is latched
by a 0 to 1 transition on RESET and the high level causes the contents of
program memory location addressed to appear on the eight lines of BUS.
Figure 7 illustrates the timing diagram for this operation.
(5) Single Step Operation.
A single step feature useful for debug can be implemented by utilizing a
circuit shown in Figure 8 (a) combined with the SSpin and ALE pin.
A D-ty£E' flip flop with set and reset is used to generate S5. In the run
mode 5S is held high by keeping the flip flop set. To enter single step,
set is remo\( d allowing ALE to bring 55 low via reset input. The next
instruction is started by clocking a "1" into the FF which will not appear
on S5 unlp,,~ ,\LE is high removing reset.
In response to SS going high
the proce""o.· begins an instruction fetch which brings ALE low resetting
~r a3d ca~~~~~ ~~e pr0cessor to again e~ter th~ stopped state.
The timing diagt",[·. i" this case is as shown in Figure 8 (b).
(EA
5V) •
_;-.'i: .OJO-...·c:- :-.'""'=-3~-'S ;-',:"5 .)t't,.--. ,--;::ga7"~:2~,~ ... , & ... i.ov; p.)\oi2r to be rer...:n",·ed frot:'. a:l
but the volatile, (lit x:; d"ta RAil array.
In pO\~er (lawn mode the contents
of data RAH can be ma''1tainE'd while drawing :.ypical1y 10 - 15% of normal
operating power requ~1~mel1ls.
vee
serves as the 5V supply ior th" bulk of the TMP8CJ48 w~ile the VDD
supplies only the RAM array.
In standby mode vee is reduced to OV but VDD
is kept at 5V. Applying a low level to reset inhi.bits any access to the
RAJ>! by the processor and guarantees that RA}.j cannot be inadvertently
a] t ered as power is rem:wed from vee.
ss~
\
ALE
L__________ J For two
/
________~--~---,Instruction Inputr-________~--~-------i---nstruction
DBO - DB7
P20 -P23
Addres s (PC)
Address (PC)
>-0
('--...:A.:.:d~d..:r..:e::..ss__(:.:,P..;C_+_l)=--_______
~___A_d_d_r_e_s_s__(P_C_+_l_)_________
Port20 -23
Data
Fig.8(b)
Single Step Operation Timing
-720-
TOSHIBA INTEGRATED CIRCUIT
TMPB04BPI, TMPB035PI
TECHNICAL DATA
INSTRUCTION
ACCLlf1ULATOR INSTRlICTlON
1
.
1 Instruction Code
1
1 Mnemonic
!D7!D6!DSID4ID3!D2!DIIDOI
Operation
I ADD A, Rr
0111 110111 rl rl rl(A)<-(A)+(Rr)
I
I
I
I
I
1 I
I
Ir= 0-7
1
IADD A,@Rr
! 01 11 II O~ 01 01 01 rl(A)<-(A)+«Rr»
I
I
I
I
!
!
I
I
I r = 0, 1
!
I ADD A,!!Data
! o! 01 01 O! O! 01 II II(A)<-(A)+Data
: d71 db dSI d41 d3! dzl dIldO I
I
i 01
I! II II II rl rl rl(A)<-(A)+(Rr)+(C)
IADDC A,Rr
I
I
I
I
I
I
I
Ir= 0-7
i
IADDC A,@Rr
01 II 11 11010101 rl(A)<-(A)+«Rr»+
I
I
I I I I (C)
I
1
I
I
IADDC A,d!Data
I
IANL A,Rr
I
IAl'llL A,@Rr
I
!ANL A,i:Data
lORL A,Rr
I
IORL A,@Rr
I
I
I
I
I
r
=
--
-- c..:
I
I
I INC
A
iDEC A
I CLR A
I CPL A
IDA A
I
I SI-IAP
I
I
A
I
I
I
I
I
1 I
I
I
I
I
I
1
I
I
I
I
2
I
I
I
I
2
0:
0
I
I
0
0
I
I
I o!
I I
I I
0 I o!
I I
-I -I
I I
-I -I
2
I
I
I
2
I
I
I
I
0
I
I
1
0
I!
0
!
2
I
I
I
0: 0 I
I
0, 1
I
2
I
_:
i
_I
I
I -I -!
'_'.
_ \ ...... ) -'!-.'
__
:-
:::::z
lJ2t.:: 3.
r
(.;.) :-'..;:
'\:\.r/
III
Ir= 0-7
I
I I! 1101 I! 01 O! 01 rl(A)<-(A) EOR«Rr»I
I
I
I
I
I
I
I
I
I r = 0, 1
I
111 1101 II O! 0111 11(A)(-(A) EOR Data I
!d7Id6IdS!d4!d31d2IdlldOI
I
010101 1101 1111 11(A)<-(A)+1
010: 01 0: 01 11 1! 11(A)<'-(A)-1
01 oi 110: 0: 1: 11 11(A)<-0
O! 01 11 I' 01 11 11 l!(A)<-NOT (A)
O! 110111011111 11Decimal Adjust
I
I
I
I
I
I
I
IAccumu1ator
01 11010101 11 11 11(A4-7)->(AO-3)
I
I
I
I
I
I
I
I
<-
I
1
I.
I Flag I
I Cycles ICTAC 1
__
I"
IXRL A,#Data
I
10: 01 O! 11 O! 01 II II(A)<-(A)+Data+(C)
!d7!d6IdSld4Id3Id2Id1IdOI
101 I! 01 11 11 rl rl rl(A)<-(A) and (Rr)
I!
I
!
I
I
I
I
ir= 0-7
I
I O[ 11 01 11 01 01 01- rl(A)<-(A)and «Rr» I
!
1 I
1 I
I
I
I r = 0, 1
10: 110,110: 0: 11 1!(A)(-(A) and Data
'd7 d6'd5 d~ d3'd:'c1'dO'
o Ii 0 0, II r: r! rl(A)<-(A) or (Rr)
I
: ! Ir=0-7
10: 1: 0' 01 O! 0' 0' rl(A)(-(A) or «Rr»1
r:;;;:
!XRL A,@Rr
1
IBytes
I
I
I
I
-721-
I
2
2
1
1
1
1
1
-I -I
I I
-I -I
I
-I -I
-I -I
1
1
-I -I
1
-!
-I
01 -I
I I
-I -I
I
1
I
I
TOSHIBA INTEGRATED CIRCUIT
TMP8048PI, TMP8035PI
TECHNICAL DATA
I Mnemonic
I
!RL A
I
I
: RLC A
1
I
I
IRR A
I Instruction Code
I
Operation
ID7ID6iDS1D4ID3ID2!DIIDOI
I 1 I 1 I 1 I 01 01 1 ! 1 I II(An+l)<-(An)
0-6
I
I
I I n
I
I
I
I
I
i I I I I I (AO)<-(A7)
I
1 1 ! 1 I 1 I 1 I 01 1 I 1 I 11 (An+1)<-(An)
0-6
1 I
I
I
I
I n
I
I(C)<-(A7)
I
I
I
I (AO)<-(C)
I
I
I
I O! 1 I 1 I 1 I 01 1 ! 1 I 11 (An)<-(An+1)
o- 6
i ! n
I
I I I I
I
I
I
I
i I (A7)<-(AO)
O! 1 ! 1 ! 0: 01 1 : 1 1 11 (An)<-(An+))
I
I I I I I n = 0-6
I
I (C)<-(AO)
I
I
I
I
! (A7)<-(C)
I
I
I
~
~
1
I
I Flag 1
I Cycles ICTACI
I
I
I
I
I
1
I
1
I
I
I
I - i -I
1 I I
Input/Output Instruction
Instruc~i8~
: Ir-; A ,Pp
1
1
0 I O! 0: O!
1 I
I
o
I]
C?era!:ion
1 1 0 I pip! (A) <- (Pp)
I
I
I P = 1, 2
110'?' P'(?~)/-(A)
'ORL Pp,J'Data
iBytes
1 1: 0' 0' 0: 1 i 01 pj pi (ppl<-(Pp)or Data
Id71d6idSid4id31d2idlidOI P = 1,2
IINS A,BUS
! 01 0: 01 01 110101 OI(Al<-(BUS)
loun BUS,A
I 01 01 01 01 01 01 11 01 (BUS)<-(A)
[ANL BUS,lIDatal 110101 11 110101 OI(BUS)<-(BUS) and
1
Id7!d6IdS!d4Id3Id2!dlldO! Data
IORL BUS,iiDatal 11010101 11 O! 01 01 (BL'S)<-(BUS) or
Id7!d6!dS[d4!d3!d2Idl!dO:Data
IHOVD A,Pp
10101 O[ 01 11 11 pi pl(AO-3)<-(Pp)
I
I
I
I
I
I
I
I
I (A4-7) <-0
1
Ii!
I
I
I
IIp=4-7
IHOVD Pp,A
01 01 11 11 11 11 pip I (Pp)<-(AO-3)
I
I
I
I 1 I I IIp=4-7
IANLD Pp,A
110101111111 pi p[(ppl<-(Ppland
I
I
I
I
I
I
I
I
I (AO- 3)
I
I
I
I
I
I
I
IIp=4-7
I
IORLD Pp,A
110101011111 pi pi (pp)<-(Pp)orCAO-3) I
Ip=4-7
I
I
I
I
I
I
1 1 I
1
I
I
I
I
1
! Flag l
C::c:les-CAc ,
2
I -I -I
I
I
I
2
2
2
!
-722-
I
I
1
,
Code
jD7:D6;DS D4,D3iD2IDl,DO:
I
I
I
I
I
I
1 -I -I
I
I
I I I
I -I -I
1
~
I
IRRC A
I
1
1 -I -I
I
!
2
2
2
2
2
2
2
2
2
2
i -
-I
I
I
I -I -I
! -I -I
I -I -I
I
I
I
I -I -I
1 I
-I -I
I
I
I
I
-I -I
I
I
-I -I
I
1
1 I
-I -I
I
1
TOSHIBA INTEGRATED CIRCUIT
TMPJ048PI, TMP8035PI
TECHNICAL DATA
RcgistPr Instruction
Instruction Codt'
I
I
Hnemonic
Operation
ID7 i D6!DSID4!D3!D2!DIIDOI
rl
(Rr)<--(Rr)+1
INC Rr
I o i 0: 01 II I I rl rl
I
I
I I i I I I r = 0 - 7
INC :ORr
0
0: 01 I I 01 01 01 r I ( (Rr ) ) <- ( (Rr ) ) + I
I,
I
! I r = 0, I
I
I
DEC Rr
I! I' 01 01 II rl r! rl (Rr)<--(Rr)-I
,
I
I
I r = 0 - 7
I
I
:Bytes
I
I
I
I
I
I
I
Branch Instruction
Mn~monic
I
InstructIon Code
:
Operation
IBytes
-:-:-::~--:-:-__ I D7'D6!DS!D4D3ID2!DI'DOI
I
!JM}' Address la10:a91a81 01 01 1101 01 (PCO-7)<--(aO-71
1
2
I
la7 la6 I aSla4Ia3!a2IallaO! (PC8-10)<--(a8-10) I
!
I
1
I
:
I
I
I
I (pClll<--DBF
i
I JHPP @A
I I 0 I I I I I 0 I 0 I I I 1: (p CO-7) (-- ( (A) )
:DJ:--iZ Rr,
1 1 1 I I! 0 II! r I r I r 1 (Rr) <-- (Rr )-1
2
!Addr-ess
a7:a6!a5'a4 I a3 a21311a01if Rr not 0
I i (PCO-7)<--(aO-7)
l' l'
o l' I' 0 (!'cO-il'--(an-71
2
i
l , ifC=1
a7Ia6!aS!a4!a3'a2'allaO I (pC) = (PC)+2
I
I I if C = 0
l' 0 (!'CO-7)"-(20-7')
c
2
IJZ Address
l' Ii 0' O. 0: 1, 110 (PCO-71<,--(aO-7)
a7ia6!aS a4:a3Ia2IallaO!if (A) = 0
! il'
1
I (pC)<--(PC)+2
!
1
I
I
I
I if (A) .NEQ.O
IJNZ Address
110101 110
I! 11 01 (PCO-7)<--(aO-71
a7!a6iaSla4Ia3!a2!allaOlif (A) .NEQ.O
I
I
I
1
I
1 (pC)<--(PC)+2
lif (A) =0
IJTO Address
01 0 1 11 1; 01 11 11 O! (PCO-7)<--(aO-71
a7Ia6!aS!a4Ia3Ia2Ial laO!if TO = 1
I
1
I
i I I I (pC)<--(PC)+2
I
I
I
I
I
I if TO = 0
IJNTO Address I
0101 110101 11 11 01 (PCO-71<--(aO-71
1
1 a71a6la5 1 a41a31a21al laOlif TO = 0
I
I
I i ! I I I I (pC)<--(PC)+2
I
I
I I
I
! I I i f TO = 1
IJTl Address I 01 1101 1101 11 11 01 (PCO-71<--(aO-71
I
I a71a61aSla41a31a21aliaOlif Tl = 1
I
I
I
I
I
I
I
I I (pC)<--(PCl+2
I
I
I I I I I I I lif Tl = 0
!JNTl Addres s I 0 1 1101010111 11 01 (PCO-71<--(aO-71
I
I a7la6laSla L.la3la2lallaOlif Tl = 0
I
I
I I I I I I (PC)<--(PC)+2
I
I
I
I
I
I
I
I I I I lif Tl = I
I
I
! -I
I
1
I
-I -I
I
I
-! -I
!
I
I
I FlaQ.1
I Cy cl e s I C I AC I
I Cycles I Flag I
I
I
ClACI
2
I
1
-
-
I
!
I
I
2
2
2
2
2
2
2
2
-I -I
-I -I
1
1
I I
-I, -I
1
-723-
- i
-
f
I
I
2
2
2
2
2
2
-I
I
I
-I
I
I
I
-I
I
I
I
I
-I
I
I
I
-I
I
I
I
-I
I
I
I
TOSHIBA INTEGRATED CIRCUIT
1MP8048PI, 1MP8035PI
TECHNICAL DATA
Mnemonic
iJFO Address
I
iJFJ
!
Address
I
I
J IF ,'I.ddress
IJ
,\I Address
IJEb Address
,
InRtruction Cod",
Operation
D7'D6!D5:D41D3:D2IDl:DO'
1 : 01 I! 1 ! 01 1 I 1 ! 01 (PCo-7) <-- (aO-7)
a7ia6Ia5!a41a3I a 2IallaO'if FO - 1
,
I
I
!, ,, i (PC) (-- (PC)+2
,
! i f FO = 0
!
0' 1 ' 1 i 1 ' o i 1 ! 1 : 01 (Pco-7)/--(aO-7)
a7 'a6'a5'a4 I a31a2ial!aO!if Fl = 1
,
I (PC) <' -- (Pc)+2
,
,
iif Fl = 0
0 0: O! 1 : 01 1 ! 1 : 01 (Pco-7)(--(aO-7)
a7 'a6iaSia4la3ia2:allaOiif TF = 1
I (pC)<--(PC)+2
I
I
I
,, i
lif TF = 0
I
I
I
1 : 0; 01 0' 01 1 I J I 01 (PCO-7)<--(aO-7)
a7ia6!a5!a4!a3ia2:al!aOlif INT = 0
I,
I I 1 I 1 (pC)<--(PC)+2
I
,,
!if INT = 1
1
b2'bl!bO! 1 ' 01 01 1 : 01 (PCO-7)<--(aO-7)
27 a6:a5,a4 :a3'a2:al aOi i f Bb =
I
i (PC) <- (PC)+2
if
E~
=
iBytes
!
2
2
2
2
I Cycles! Flagl
! CIAC!
I
2
-I -I
I
! I
I
I
I
I
I
I
I
I
2
I -1 -I
I
I
I
I
I
I
I
I
2
I -I -I
I
!
I
I
I
I
I
2
-I -I
! I
1 1
1 1
2
2
J
1(b = 0 - 7l
: CALL Address 1 aJO'a9;aS: 1 I 0' 1 ! 01 o ( (SP ) ) <-(PC), (PS ....'4-7)
a7'26 1 a5' af... I a 3 a2'a1'aOI
{5? ~ / - 'S? , ..<
,r
, [I.El
1' 0
,
I
0
1 ' 0:
_-
-
--: 28-
--
~-
2
2
0'
-,,
-I
I
~j~,'
-
,pel 1)', --JEt
0: 0: 1 ! 1 ' (S P ) <-- ( sP ) - 1
1 (p C) <-- ( (SP ) )
I
I
1 ! O! 0; 1 ! II (SP)<--(SP)-1
I (p C) <-- ( ( SP ) )
I
I
1
!(PSW4-7)<--«SP»
I
0
i
, RETR
~
-I
I
i
(?C9-2~!
-I
2
2
Flag Manipulation Instruction
Mnemonic
CLl{
CPL
CLR
CPL
eLR
CPL
C
c
FO
FO
Fl
fl
Instruction Code
O£eration
D7 I D61 D5! D4 i D3 i D2! Dl: DO I
1 : 01 01 1 ! 0 1 1 1 1 I 11 (C) <-- 0
1 I O! 1 I 0; 01 1 I 1 1 11 (C)<--NOT(C)
1 I . 0] 01
Oi 1 ] 01 II (FO) <-- 0
1 I 01 0 1 1 ' oj 1 ! 01 II (FO)<'--NOT(FO)
1 I oj 1 I 01 Oi 1 I 01 II(Fl)<-- 0
1 I 01 1 I 1 : O! 1 1 01 II (Fl)<--NOT(Fl)
0:
-724-
,iBytes
I
1
iCy cles 1 Flagl
I
I
I
I
1
I
I
! CIACI
01
I 01
I -I
I -I
I -I
I -I
-I
-I
-I
-I
-I
-I
TOSHIBA INTEGRATED CIRCUIT
TMP8048PI, TMP8035PI
TECHNICAL DATA
Ddta Tr311!:,ff'r Inst.ruction
IBytes ICyclesl Flag 1
I
1
1 CIACI
1
1
1 -] -I
1
1 -I -I
1
I
1
1 -I -I
1
I
1
,!
2
2
1
1 -I
!
1
1
1 1 i
1
1 -I -I
I
-I
1
1 1
1
2
2
1
1 -] -!
1 I
2
2
1 -I -I
I 1 ,1
1 -I
Instruction Code
Operation
!
D71D61D51D41D31D21DI1DOI
~ ~10V A, Rr
1 1 1 1 1 1 1 1 1 ! rl r 1 r 1(A)<-- (Rr)
,
!
1 1 ,
1 I
1 I r = 0 - 7
1~10V A, @Rr
1 1 1 1 1 1 1 i 0 1 01 01 rl(AJ<-- ( (Rr) )
,
I
I
i ,
1 r = 0, 1
; ~10V A, ,IDa ta i 01 01 1 1 01 0) 01 1 1!(A)(--Data
,,
dO!
I d7Id6'd5!d4 I d3!d2Idl
,
; ~10V Rr, A
r I (Rr )"--(A)
1 : 0, 1 ! 01 1 I r, r
I
1
1 r = 0 - 7
1 1 1
;NO\I@Rr,A
j! 01 1 : 0; 01 01 0 rl ((Rr))(-(A)
,
,
1 1 ,
1 1 1
1 r = 0, 1
; ~10V Rr ,~';D8.ta
r 1 (Rr) <--Da ta
1 : 01 1 ! 1 1 1 1 rl r
d7ld6!d5ld4ld3ld2ldlldOI r = 0 - 7
1
iMOV@Rr,liData
1 1 01 1 1 1 1 01 01 01 r 1((Rr)) (--Data
,,
a7la6:aSla4la3ia2lallaO I r = 0, 1
IHOV A,PS'-'
1 1 1 : 01 01 01 1 1 1 I II(A)<-- (pSW)
: ~lOV PS~} , A
1 1 1 1 01 1 1 0' 1 I 1 1 I! (pSW)(-- (A)
! XCH A, Rr
01 01 1 1 01 1 : r
r' r ! (A) -- > (Rr)
Nnemonjc
,
-,
-,
-i
-
<-,
i
!XCH A,@Rr
:-:=::.::J
.-
01 0 1 1 I 01 01 0
1 1
1 1
G
u
i r = 0 - 7
01 r 1(A)-->((Rr))
(-1 1
r = O. 1
u
r \Av-.);-- \ ' r..I"
r
,MOVX A,(CRr
1
1}10VX @Rr,A
,,
1HOVP A, CoA
!
I MOVp 3 A,@A
I
1
1 I 0: 0: 0:
1 1
1 i
1 1 0: 01 1 1
1
1 1 01 1 i 01
1 1 1 !
1 ] 1 I 1 1 01
O!
0
01 0
1
0' 0
1
Or 0
=
:.),
-I
"
0: r!(A)<--((Rr))
1 1 r = 0, 1
01 r 1 Rr) <-- (A)
1 1 r = 0, 1
1 ! 11 (pCo-71<--(A)
1 1(A) < -- ( (p CJ )
1 I 11 (PCO-7J<-- (A)
! (PC8-1j)(--OOll
I (Al (-- «(PC»
«
-725-
-
-.:"
2
:
2
-I -
2
-! -
1
i
2
1
-!
-[
1
TOSHIBA INTEGRATED CIRCUIT
TMP8048PI, TMP8035PI
TECHNICAL DATA
T,mer/Counter Instruction
IBytes I Cycles I Flagl
Instruction Code
I
D7ID6!DS1D4!D3 I U2!DIIDOI
!
ICTACI
I
01 110101010111 OI(A)<--(T)
INOV A,T
I
1
I - i -I
01 11 1101 O! 01 11 OI(T)<--(A)
INOV T ,A
I
1 I -I -I
I STH.T T
1 I -! -I
o I II 0 I 11 0 I 11 01 II Counting is
I
! I I I I I Istarted In the
I
I
I
I
1 I
I
I
I
I
Itimer mode
I
I
I
I Sny CNT
0 1 110101 O! 1101 llCounting is
I -: -!
I
I
I
I
I
I
I
Istarted in the
I I I
I
I -I -I
I
! I I I I I levent counter
I
I
I
I
I
I
I
I
Imode
I
I
I
I
I STOP TCNT
oI I i 1 I 0 I 0 I 1 I 0 I 1 1St op bo t h time
I -I -I
I
i I I I I I I accumulation and
I I I
I
I
I
I
I
I
I
I
I event count ing
I I I
lEN TCNTI
0101 110101 1101 IITimer interrupt
I -I -I
I
I
I
I
I
I
I I lis enabled
I I I
IDIS TC1;'1'l
0101 11 1101 1101 IITimer interrupt
I -I -I
!______________________________~I~i~s~d~i~s~a~b~le~d~____~__
! I !
I
Mnemonic
I
Control Instruction
Xnemonic
Instruction Code
D7'D5'DS 1 D4'D3:D2'Dl'DO!
n'
pperation
\;
,
SEL RBO
SEL RB 1
SEL MBO
SEL MBI
ENTO eLK
NOP
11
1I
11
Ii
oI
I
I
01
I!
1I
11
11
1I
I
I
O~
ICyclesi~i
I
! C AC I
l'
15
::5
!Bytes
e:la':J:ec
c
1
0:
01
; 011101
0 I 1 I O! I! 0 I
1: 01 0 I 1 I 0 I
1111011101
1I 1I 0I 1I 0 I
I
I
I
I
I
I
I
I
1 I
01 01 01 01 01
iis disabled
11(BS)<-- 0
1 I (B S ) < -- 1
11 (DBF) < -- 0
11 (DBF)<-- 1
1 ITO is e na bled to
lact as the clock
loutput
O!No operation
-726-
1
1
1
1
I
I
I
1 I
1 I
1
1
1
-
-I
-I
-I
-I
-I
I
I
-I
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
ITXP8048PI/803SPI:
ABSOLUTE
I SYMBOL
!VDD
!VCC
IVINA
IVINB
IpD
jTSOLDER
ITSTG
ITOPR
DC
TMP8048PI, TMP8035PI
INDUSTRIAL SPECIFICATlON"1
MAXIMUM RATTINGS
I
ITEM
IVDD Supply Voltage (with respect to GND (VSS))
iVCC Supply Voltage (with respect to GND (VSS))
IInput Voltage (Except EA)
IInput Voltage (Only EA)
IPower Dissipation (Ta - 70'C)
ISoldering Temperature (Solderin Time 10 sec)
Storage Temperature
!Operating Temperature
! RATTING
I-o.sv to + 7V
I-o.sv to + 7V
I-a.sv to + 7V
I-O.5V to + 13V
!
1. 5W
I
260' C
-SS'C to lSO'C
1-40'C to 8S'C
CHARACTE=R~I~S'_r~IC~S~__~~~
ITA=-40'C to 8s'cl, VCC=VDD=+SV±lOZ, VSS=OV, Unless Otherwise Noted.
PARAMETER
! TEST CONDITIONS IMIN.iTYP. !MAX.IUNIT I
I SYMBOL I
IVIL
IInput Low Voltage
1-0.51
0.71 V I
1~~___I~(~E~x~c~e~p~t_XT
__A~L~1~,~X_T~A~L~2~,R_E~S~E_T~)____~______________~I~~----+-~~'~I--_
!VIL1
!Input Low Vol~
!-0.5'
'0.6' \'
!~~__~:(~XT~A=L~1~'7X~T.~AL~2~,R~E~S~E~I~)__________- ,______________-+~~~__~~~I~_
IVIH
ilnput High Voltage
2.2:
vcci V
1~~__~I(~E~x~c=eLP~t~XT~A~L~1~,~X~T~A=L=22,~R~E~SE~T~)____~______________+-~~I--~~~TI~v Ell
i Irmut High Vo~
3.S I \'CC i \'
-:--:::c:--_--:-'_X-_'"-_-.~:..: ~X: ..:..=-<:, R~S':: =- '
\'~=--
: \'C=-~
:>..:::~-..:.t
~='¥.-
':!'...l::;::.:~:"ov.~
':=<. ':EZ':-:
;:~:
f~'~":3'
ta E -=
i
I(RD, WR, PSEN, ALE)
I
I
IVOL2
iOutput Low Voltage (PROG)
lOL - 0.8 mA
10.451
IVOL3
IOutputLowVoltage
!lOL
1.2mA
I
10.451
I
I (For other output pins)
I
I
I
i :-Ov-:O-OHO:----'I"O'""u...::tc::.p-u-"-t-"-H::-':;::ig'--:h--:::..c\'-o:":l'
'/ -"t=a-g-"-e=i-(B=-U':-S;:-c):------~;:-cIO-: C}C"" 1-_-_-:2:-::8c::0->-t"""CA----T-:2=-.-:4--;1-----T-1
IVOHI
IOutput High Voltage
IOH --80IlA
2.41 I - I
I
I(RD, WR, PSEN, ALE)
I
I
I
V
V
--_--:c---:-V,---V
I:-:-V-:O-OH~2---I~O~u~t2p-u-t~H~1~·g~,h~V~o~1~t=a~g~e----------~~IO~H~---~3:-::0->-t~A-----,~2=-.-:~~!----+---~1~\~/-
1______~I,-(~F~o-r--o-th-e-r--c-)u-t~p-u-t-Lp-i-n-s-)-------71--------------~I--~I----+_---I~,--I
I
I
I
I
I
IILl
IInput Leak Current (T1, INT)
Ivss ~ VIN ~ VCC! - I ±lol IlA
I
I
I
I
I
I
IILIl
!Input Leak Current
IVSS+O.4Sw:'
~?C
:FR
I
ItDP
I tPD
ItPF
I
ItPP
ItPL
ItLP
? :.'!'"~
:Port
- ............
,.. .....
Se~'.:::-
C:-~~::
:-:;1
Ho!~
_
l~-?
Ti~-=
(p
"e
t,:;
ITEST CONDITIONS IMIN. ITYP.
2001
I
1201 I
801 I
I
I
I
400 I I
I
4201 I
I
I
80 I I
2.sl I
!
I
20 EF
01 I CL
I
I
- I I
I
I
230! !
- I !
~
(P~0G:
'Pert 2 ~:l?U~ Data Set Time
I (PROG)
10utEut Data SetuE Time (PROG)
IOutEut Data Hold Time (PROG)
IPort 2 Input Data Hold Time
I (PROG)
IPROG Pulse Width
IPort 2 I/O Data SetuE Time
IPort 2 I/O Data Hold Time
-40 ;
101
-
1::
IMAX. IUNIT I
I - I ns
I I ns
I
I ns
I
I
I I ns
I
I
I - I n8
I
I
I - I ns
IlS.O I l.ls
I
I
I 2001 ns
I
I
I 4001 ns
I
I
I - I ns
I 600 ! ns
I
I
I
I
ns
ns
-
::-s:
~5
r;.s
86~\
230 ! 2s1 01 I
920 I 3001 1201 -
-
I
I
I
1601
I
- I
- I
- I
-
Note :tCY=2.S1.1s, Control Output:CL=80pF, BUS Output: CL=lSOpF, PORT20-23:
CL=80pF.
-728-
;::s
ns
ns
ns
ns
ns
ns
TOSHIBA INTEGRATED CIRCUIT
TIP8048PI, TMP8035PI
TECHNICAL DATA
TIMING WAVEFORM
A. I net ruct ion Fet ch from External Program Memory
tcy
ALE
BUS
f,. '(, .• "
[rom External Data !1emory
ALE
-.l
\ ~-----------t-e-e-----_-~F~~eJA~Il ____
~,"---r_
RD
i
Bl:S
tAre
~~1<--:_Da_ta_~'-
Address~
C
_---:;1:z
~
'.',. te into External Data Memory
-729-
TOSHIBA INTEGRATED CIRCUIT
TMPBD48PI, TMPBD35PI
TECHNICAL DATA
D. Timing of Port 2 during Expander Instruction Execution
ALE
PORT20
I
PORT23
(Output Data)
PORT20
I
PCH
PCH
PORT23
(Input Data)
Port
PROG
*
Input Lnabled State
TYPICAL CHARACTERISTICS
1) BUS:I OH - VOH
VDn=VCc=5V
TA=2soC
-50
!
-30
"- "'i'o.....
::t:
H
3) BUS, PI, P2: IOL - VOL
o
-10
o
o
,.J
c
........
10
o '"
o
t--
2
VOH (V)
4
VDD=VCC=5V
,.. -500
...:
TA=25°C
=>.
::t:
.---
30
H
2) PI, P2:I OH -VOH
'-'
VDD=VCC=sV
TA=2SoC
50
-300
0
H
-,...
-100
'-...
4
2
VOH (V)
-730-
.."V
2
4
TOSHIBA INTEGRATED CIRCUIT
TMP8048PI, TMP8035PI
TECHNICAL DATA
T'RllGRAM TAPE FORMAT
TMP8048 programs are delivered in the form of paper tape with the following
format and it is required to attach the tape list. The format of paper tape
lS same as the Intel type object tape (hexadecimal tape output by Intel MDS
system, PROMPT 48 Development Tool, etc.)
11)
[ape Format
01 J
Leader, 50 "NULL" characters or more
CoT'iJTH?n t s
Cornnent (Record mark
II: 11
is not inClUded)}
CR)
Option
f----':'-...---1- - - - - Record Mark
Record Length (2 hexadecimal digits)
Loading Address (4 hexadecimal digits)
Record Type (2 Digits)
"00"
Normal Record
"01" .•.. End of File Record
Data
~1"'-'
Check S= (2 hexadecitr.al digits)
C",)
(17~
"
~
H
~y cha racters
(Ri.."'E:)l'"I. BLI;.!\'1:) befcre 2!1d after
c~ti~n2!.
'eooc' ''co ',""oe'e' 'e(e')
LF
}Trailer, 50 "!lULL" characters or more
(2) Example of Tape List
TOSHIBA MICRO COMPUTER TLCS-48
:l00000000665C7D79CF50F3F951FED55A8FFI6E570
:lOOOl00088884DDE67D31F5D8ABA6DF292FI13F5CI
:l00020004FFIFB5DFFDAA96A99CF7DF94A346B7C09
:I0003000197352F729F12F79AA9C057C5B851EED77
:l003C0005DFDB5E556A67277F61A51C631CF9FOE80
:l003DOOOBD2F6F20E8BB1977E3FB5ADIF41FDAA7E2
:l003EOOOB53D42EOEC32546025B7308CDD52063DID
:l003FOOOB4BE9E9E345B6138060B20VC372BF60BD6
:OOOOOOOlFF
-731-
II
(CR) (LF)" are
TOSHIBA INTEGRATED CIRCUIT
TMP8048PI, TMP8035PI
TECHNICAL DATA
OUTLINE DRAWiNG
Unit in mm
2I
40
]
::2':
..,.N
20
I
1 5.24
± 0 25
I
II
,f\
::,"'Il
v
J
i'l
I
\:
I"";
+0 1
0.25_ 005
~~I:·".i'~''i
~
Note: 1. This dimension is measured at the center of bending point of leads.
2. Each lead pitch is 2.S4mm, and all the leads are located within
±0.2Smm from their theoritical positions with respect to No.1 and
No.40 leads.
-732-
TOSHIBA INTEGRATED CIRCUIT
TMP8049PI-6, TMPB039PI-6
TECHNICAL DATA
8-BIT SINGLE-CHIP MI CROCOMPUTER
GENERAL DESCRIPTION
The TMP 8049PI -6, from here on referred to as the TMP 8049, is a single chip
microcomputer fabricated in N-channel Silicon Gate MOS technology which
provides internal 8-bit parallel architecture.
The following basic architectural functions of a computer have been
included in a single chip; an 8-bit CPU, 128 x 8 RAM data memory, 2K x 8 ROM
program memory, 27 I/O lines and an 8-bit timer/event counter.
The TMP8049 is particularly efficient as a controller.
It- has extensive
bit handing capability as well as facilities for both binary and BCD
arithmetic.
The TMP8039PI is the equivalent of a TMP8049 without ROM program memory on
chip. By using this device with external EPROM Or RAJ1, software debugging
becomes easy.
FEATURES
2.5 ~S Instruction Cycle
All instruction 1 or 2 cycles
Over 90 instructions; 70% single byte
Easy expandable memory and I/O
2K x 8 masked RO~
128 x 8 RAM
27 I/O lines
Interval Timer/Event Counter
Single level interrupt
Single SV supply
-40·C to +85·C Operation
PIN CONNECTIONS (Top View)
TO
XTALI
XTAL2
RESET
SS
INT
EA
VCC (+5\')
Tl
P27
P26
P 2S
P24
P17
P16
PIS
Pl4
P13
P12
Pll
PIa
V1Jl)(+SV)
PROG
P 23
P22
P 21
P 20
RD
PSEN
I·m
ALE
DBa
DBI
DB2
DB3
DB4
DB)
DB6
DB7
(ov/ ss
-733-
TOSHIBA INTEGRATED CIRCUIT
TMP8049PI-6, TMPB039PI-6
TECHNICAL DATA
BLOCK DI AGRAM
OscUla tion
Frequency
2
Mask ROM
lK
x
8
(Program
Area)
6
gister/
Decoder ~===;l
RAM
64 x 8
Accumula tor
Bit Test
Control and Timing Circuit
XTAL 2
RESTr TIlT EA
XTALj
H
0
"tJ
n
~
C
rt
CIl
"''0
'"' "0
c ro '" ro'"'
n ... "
o DO
:Tro
''""' ...
'"
ro
'"''' ro "
"' ro s'"
...
"''''
"'"'
...
...
'"'c"' '" nro > '"ro 0
'" '"
'"'
'"'"
Ul
HH
0..",
"tJrt
" x
~
~
::1
'" 0..
,",00
Ul
Ul "
H
C'.
::1
C
I-'
cr"
I-'
H
rt
00
I
cr"
"
FROG
~
'='
'"
'"
'"'"'
rt
"
0
cr"
cnt11
;:;.iJ
ocr"::1
'"
ro
00
Note 1 ) The lower order 4 bits of
port 2 output lat ch are
used also for input/output
operations wi th the I/O
expander.
ro
"
'"
Ul
-734-
Note 2) The output latch of port
is also used for address
output.
a
TOSHIBA
INTEGRATED CIRCUIT
TMPB049PI-6, TMPB039PI-6
TECHNICAL DATA
PIN NAMES AND PIN DESCRIPTION
VSS (Power Supply)
Circuit GND potential
VDD (Power Supply)
+5V during operation Low power standby pin for TMP8049 RAM
vce (Main Power Supply)
+5V during operation
PROG(Outputl
Output strobe for the TMP8243P I/O expander
P10-P17 (Input/Output) Port 1
8-bit quasi -bidirectional port (Internal Pullup=50k0).
P20-P27 (Input/Output) Port 2
8-bit quasi-bidirectional port (Internal Pullup=50k0).
P20-P23 Contain the four high order program counter bits during an
external program memory fetch and serve as a 4-bit I/O expander bus for
the TM?8243P.
DBO-DB7 (Input/Output, 3 State)
True bidirectional port which can be written or read synchronously using
the RD, "1{ strobes. The port can also be statically latched.
Contains
the 8 low order program counter bits during an external progra~ mem~
fetch, and receives the addressed instruction under the control of PSEN.
Also contains the address and data during a~external RAM data store
instruction, under control of ALE, RD, and WR.
TO
(Input/Output)
Input pin testable using the conditional transfer instructions JTO and
JNTO. TO can be designated as a clock output using ENTO CLK instruction.
Tl
(Input)
Input pin testable using the JTl and JNTl instruction.
Can be designated
the event counter input using the timer/STRT CNT instruction.
INT
(Input)
External interrupt input.
Initiates an interrupt if interrupt is,
enabled.
Interrupt is disabled after a reset. Also testable with
conditional jump instruction.
(Active Low)
RD
(Output)
Output strobe activated during a Bus read.
Can be used to enable data
onto the Bus from an external device. Used as a Read Strobe to External
Data Memory (Active Low).
WR
(Output)
Output strobe during a Bus write (Active Low) Used as a Write Strobe to
External Data Memory.
-735-
TOSHIBA INTEGRATED CIRCUIT
TMP8049PI-8, TMPl039PI-8
TECHNICAL DATA
RESET (Input)
Active Low signal which is used to initialize the Processor.
during Power down.
Also used
ALE
(Output)
Address Latch Enable. This signal occurs once during each cycle and is
useful as a clock output. The negative edge of ALE strobes address into
external data and program memory.
PSEN
(Output)
Program Store Enable. This output occurs only during a fetch to external
program memory (Active Low).
SS (Input)
Single step input can be used in conjunction with ALE to "single step"
processor through each instruction when SS is low the CPU is placed into
a wait state after it has completed the instruction being excuted.
EA (Input)
External Access input which forces all program memory fetches to reference
external memory. Useful for emulation and debug and essential for testing
and program verification. (Active High).
XTAL 1 (Input)
One side of crystal input for internal oscillator.
al source.
Also input for extern-
1.."TAL 2 (Input)
Other side of crystal input.
FUNCTIONAL DESCRIPTION
1. System Configuration
The following system functions of the TMP8049 are described in detail.
(1) Program Memory
(6) Stack (Stack Pointer)
(2)
(7) Flag 0, Flag 1
Data Memory
(3) I/O Port
(8) Program Status Word (PSW)
(4) Timer/Counter
(9) Reset
(5) Interrupt Control Circuit
(10) Oscillator Circuit
(1) Program Memory
The maximum memory that can be directly addressed
4096 bytes. The first 2048 bytes from location 0
internal resident mask ROM. The rest of the 2048
memory are external to the chip. The TMP8039 has
memory; all memory must be external.
-736-
by the TMP8049 is
through 2047 can be
bytes of addressable
no internal resident
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8049PI-6, TMP8039PI-6
There are three locations in Program Memory of special importance.
Address
4095
Memory Bank 1
2048
2047
Memory Bank 0
Program Memory Area
Location 0
Activating the Reset line of the processor causes the first instruction to be fetched from Location O.
Location 3
Activating the interrupt line of the processor (if interrupt enabled)
causes a jump to subroutine defined by address held in Location 3.
Location 7
A timer/counter interrupt resulting from a timer/counter overflow
(if enabled) causes a jump to a subroutine defined by address held in
Location 7.
Program address 0-2047 and 2048-4095 are called memory banks 0 and 1
respectively switching of memory banks is achieved by changing the
most significant bit of the program counter (PC) during execution of
an unconditional jump instruction or call instruction executed after
using SEL MBO or SEL MB1.
Reset operation automatically selects Bank O.
(2) Data Memory
Resident Data Memory (volatile RAM) is organized as 128 words by 8-bits
wide.
The first 8 locations (0 -7) of the memory array are designated as
working registers and are directly addressable by several
instructions. By executing a Register Bank switch instruction (SEL
RBI) locations 24 - 31 are designated as the working registers 1n
place of 0 - 7.
-737-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8049PI-6, TMPB039PI-6
j,ddre ss , - - - - - - - - - ,
127
Data Nemory
32
31 r-R-;;;i~~;;'-Ba-;:;kl24
REI
23 - - - - - - - - - 8 Level Stack
8
(16 byte)
7 Resister Bank 0
O' - - - - - - -REO
----'
Internal Data Memory Area
RAM locations 8 - 23 serve a dual role in that they contain the program
counter stack which is a stack 2 bytes wide by 8 levels deep. These
locations store returning addresses from subroutines. If the level of
subroutine nesting is less than the perreitted 8, you free up 2 bytes of
RAM for general use for every level of nesting not utilized.
ALL 128 locations are indirectly addressable through either of two RAM
Pointer Registers which reside at RO and Rl of the Register array.
The TMP8049 architecture allows extension of the Data Memory to 256 words.
(3)Input/Output Ports
The TMP8049 has 27 I/O lines which can be used for either input or output.
These I/O lines are grouped into 3 ports each having 8 bidirectional lines
and 3 "test" inputs which can alter program sequences when tested by conditional jump instructions.
Ports 1 and 2 are each 8-bits wide and have identical characteristics.
Data written to these ports is statically latched and remains unchanged
until rewritten. As input ports these lines are non-latching, i.e., inputs
must be present until read by an input instruction.
All lines of Ports 1 and 2 are called quasi-bidirectional because of a
special output circuit structure (illustrated in Figure 1). Each line is
continously pulled to a +SV level through a high impedance resistive device
(SOkQ ) which is sufficient to provide the source current for a TTL high
level yet can be pulled low by a standard TTL gate thus allowing the same
pin to be used for both input and output. In order to speed up the "0"
to "1" transition a low impedance device (5k(l ) is switched in momentarily
whenever a "1" is written to line. When a "0" is written to line a low
impedance device overcomes the pullup and provides TTL current sinking
capability.
-738-
TOSHIBA INTEGRATED CIRCUIT
TMPB049PI-6, TMPB039PI·6
TECHNICAL DATA
MiL. ORL
+SV
+SV
SOk[J
Internal
Bus--~""'--j
Q
D
D-Type
Hip-Flop
CLK
SOH2 I/O pins
Portl or 2
Q ~+------j
"'ri t e Pulse---1--"-----------'
Inter Buffer
IN
Fig.l
Input/Output Circuit of Port 1, Port 2
Reset initializes all lines to a high impedance "1" state.
When external data memory area is not addressed during excution of an
1nternal progra~, Port a (DBO DB7) becomes a true bidirectional port
(bus) with associated input and output strobes.
If bidirectional feature
not needed Bus can serve as either a statically latched output port or
a non-latched input port. However, I/O lines of this port cannot be
intermixed.
As a static port data is written and latched using the OUTL instruction
and inputted using the INS instruction these two commands generate
pulses on the corresponding RD and WR strobe lines.
As a bidirectional port the MOVX in~ructions are used to read and write
the port which generate the RD and WR strobes.
When not being written or read, the Bus lines are in a high impedance
state.
(4)Timer/Event Counter
The 8-bit binary up counter can use either of the following frequency
inputs
(1) Internal clock (1/480 of OSC frequency)
..•••....••. Timer mode
-739-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPB049PI-8, TMPB039PI-8
(2) External input clock form TI terminal
(minimum cycle time 3 x ALE cycle)
..•••.•••••.. Event Counter mode
The counter is presettable and readable with two MOV instructions
which transfer the content of the accumulator to the counter and vice
versa. The counter content is not affected by a Reset and is initialized
solely by the MOVT, A instruction. The counter is
stopped by a Reset or
STOP TCNT instruction and remains stopped until started by
START T
instruction or as an event
counter by a START CNT.
Once started
the
counter will increment to its maximum count (FF) and overflow to Zero
continuing its count until stopped by a STOP TCNT instruction or RESET.
The increment from maximum count to Zero (overflow) results in the setting
of an overflow flag and the generation of an interrupt request. When
interrupt acknowledged a subroutine call to Location 7 will be initiated.
Location 7 should store the starting address of the timer or counter
service routine. The state of the overflow flag is testable with the
conditional JUMP (JTF). The flag is reset by excuting a JTF or by RESET.
Figure 2 illustrates the concept of the timer circuit.
XTAL/lS
1/32
Pre-scaler
Cleared on Start Timer
JTF Instruction
8-Bit Timer/
STOP TCNT 0
Tl t------lEdge Detector
Counter
n
Read/Write Enable
Til'ler Interrupt
Request Flip-Jlop
INT
Timer Interrupt Enable
Fig.2
Concept of Timer Circuit
-740-
TOSHIBA INTEGRATED CIRCUIT
TMP8049PI-6, TMPl039PI-6
TECHNICAL DATA
Conditional Jump Logic
S
JTF
Instruction
Timer
Flag F-F
Reset--....--,
>--+---1 R
Timer Overflo",'
Qf-------f
Timer
Overflow
R F-F
----~--ls
Timer Interrupt
Execution---~r-"
RETR
Instruction
Reset
INT pin
Interrupt
F-F
ALE
r--C~L'-;K"".--,External
QI-------[
Q
Timer interru?t
Recognized
Last cycle
of Tnstructl0n
EN I
lnst ruct ion
interrupt Recognized
s
~
=--=~
....
...
~
0
!..~~
T C:~T 1
S
Instruction
~
~
,!;
.... r.
Q
E
.... ...
c:. c:.
~
Executio~ of Ir.terrupt Call Instruction
E.u~
R;:::":J..
R ~ ~ ~
Reset---+~----------~
DIS TCNTl
Instruction
Instruction
Fig.3
Concept of Interrupt Control Circuit
(5) Interrupt Control Circuit
There are two distinct types of Interrupts in the TMP8049.
(1) External Interrupt from the INT terminal
(2) Timer Interrupt caused by timer overflow
-741-
TOSHIBA INTEGRATED CIRCUIT
TMP8049PI·6, TMPB039PI·6
TECHNICAL DATA
The interrupt system is single level in that once an interrupt is detected
all further interrupt requests are ignored until execution of an RETR
(which should occur at the end of an interrupt service routine) reenables
the interrupt input logic.
An interrupt sequence is initiated by applying a low level "0" to the INT
pin.
INT is level triggered and active low which allows "Wire Oring" of
several interrupt sources. The interrupt level is sampled every machine
cycle during ALE and when detected causes a "jump to subroutine" at Location 3. As in any call to subroutine, the Program Counter and Program
Status Word are saved in the stack.
When an overflow occurs in the internal timer/event counter an interrupt
request is generated which is reserviced a~ outlined in previous paragraph
except that a jump to Location 7 is used instead of 3. If INT and times
overflow occur simultaneously then external request INT takes precedence.
If an extra external interrupt is needed in addition to INT this can be
achieved by enabling the counter interrupt, loading FFH in the counter
(one less than the terminal count), and enabling the event counter mode.
A "1" to "0" transition on Tl will cause an interrupt vector to Location 7.
The interrupt service routine pointed to be addresses in Location 3 or 7
must reside in memory between 0 and 2047, i,e., Bank O.
Figure 3 illustrates the concept of the interrupt control circuit.
(6) Stack (stack Pointer)
An interrupt or Call to subroutine causes the contents of the program
counter to be stored in one of the 8 register pairs of the Program Counter
Stack. The pair to be used is determined by a 3-bit stack pointer which is
part of the Program Status Words (PSW explained in section (8)). Data RAM
locations, 8 through 23 are available as stack registers and are used to
store the program counter and 4-bits of PSW as shown in the figure.
The stack pointer when initialized points to RAM location 8 and 9. The
first subroutine jump or interrupt results in the program counter
contents
being transferred to Locations 8 and 9. Then the stack pointer is incremented by one to point to Locations 10 and 11. Eight levels of subroutine
are obviously possible.
At the end of a subroutine signalled by a RET or RETR causes the stack
pointer to be decremented by one and the contents of the resulting pair
to be transferred to the Program Counter.
-742-
TOSHIBA INTEGRATED CIRCUIT
TMPB049PI-e, TMPB039PI-e
TECHNICAL DATA
23
7
22
21
6
20
19
5
18
17
4
16
15
3
14
13
2
12
11
1
10
o
(7) Flag 0, Flag 1,
PS1~
PC8 ro 11
_______
.L ________
PC4'\. 7
I
I
PCO'\. 3
Stack
Pointer
(fG. Fl)
9
8
RAM
Address
The TMP8049 has two flags FO and Fl which are used for conditional jump.
These flags can be set, reset and
tested with the
conditional
jump
instruction JFO.
FO is a part of the program status word (PSW) and is saved in the stack
area when a subroutine is called.
(8) Program Status Word (PSW)
An 8-bit status word which can be loaded to and from the accumlator exists
called the Program Status Word (PSW). The PSW is read by a MOV A, PSW and
written to by a MOV PSW, A. The information available in the PSW is shown
in the diagram below.
-743-
TOSHIBA INTEGRATED CIRCUIT
TMPB049PI-6, TMPl039PI-6
TECHNICAL DATA
Stack Pointer
/
Ic lAC IFO IBS 11 IS2 lSI Iso
LSB
MSB I
II
1_ _ _ _ _ 11
Saved in stack area Spare ("1" during Read)
at the time of Subroutine Call.
Bits 0 - 2
Bit 3
Bit 4
Stack Pointer Bits(SO, 51, 52)
Not used ("1" level when read.)
Working Register Bank Switch Bit
(BS)
o
Bank a
Bank 1
Bit 5
Bit 6
Flag a (Fa)
Auxiliary Carry (AC) carry bit generated by an ADD
instruction and used by the decimal adjust instruction
DA, A (AC)
Bit 7
Carry (C) flag which indicates that the previous
operation has resulted in the accumulator.
(e)
(9) Reset
The reset input provides a means for initialization of the processor.
This Schmitt trigger input has an internal pullup registor which in
combination with an external l~F capacitor provides an internal reset
pulse
sufficient length to guarantee that all internal logic is
initialized.
r
IHI
-L-o--tvVv----r---d RESET
lllF
J.
-744-
TOSHIBA INTEGRATED CIRCUIT
TMP8049PI-6, TMP8039PI-6
TECHNICAL DATA
If the pulse is generated externally the reset pin must be held at ground
(£O.SVlfor at least sOms after the power supply is within tolerance •
• Reset performs the following functions within the chip:
(i)
Sets PC to Zero.
Sels Stack Pointer to Zero.
(iii) Selects Register Bank 0.
(iv)
Selects Memory Bank 0.
(v)
Sets BUS (DBO - DB 7) to high impedance state. (Except when EA
Sets Ports 1 and 2 to input mode.
(vi)
(vii) Disables interrupts (timer and external).
(vi ii) Stops Timer.
(ix)
Clears Timer Flag.
(x)
Clears FO and Fl.
(xi)
Disables clock output from TO.
(ii)
(10) Oscillator Circuit
TMP8049 can be operated by the external clock input in addition to
crystal oscillator as shown below.
+5\'
2
,----?---i-'
XTAL 1
.--_--+-_--=3:..r XTAL 2
10pF
I
2
XTAL 1
3
XTAl 2
--JWr--~--V
+5V
2. Basic Operation and Timing
The following basic operations and timing are explained
(1) Instruction Cycle
(2) External Memory Access Timing
(3) Interface with I/O Expander TMP8243P
(4) Internal Program Verify (Read) Timing
(5) Single Step Operation Timing
(6) Low Power Stand-by Mode
-745-
5V)
TOSHIBA INTEGRATED CIRCUIT
TMPB049PI-6, TMP8039PI-6
TECHNICAL DATA
(1) Instruction Cycle
The instructions of TMP8049 are executed in one or two machine cycles,
and one machine cycle contents of five states.
Fig.4 illustrates its relationship with the clock input to CPU.
62 clock shown in Fig.4 is derived to outside by ENTO CLK instruction.
ALE can be also used as the clock to indicate the machine cycle as well
as giving the external address latch timing.
(2) External Memory Access Timing
(i) Program Memory Access
TMP8049 programs are excuted in the following three modes.
(1) Execution of internal program only.
(2) Execution of both external and internal programs.
(3) Execution of external program only.
The external program memory is accessed (instructions are fetched)
automatically when the internal ROM address is exceeded in mode (2)
and from initial start address 0 in mode (3).
In the external program memory access operation, the following will occur
The contents of the 12-bit program counter will be output on BUS(DBO DB7) and the lower 4-bits of Port 2.
Address Latch Enable (ALE) will indicate the time at which address is
valid. The trailing edge of ALE is used to latch the address
externally.
Program Store Enable (PSEN) indicates that an external instruction
fetch is in progress and serves to enable the external memory device.
BUS (DBO - DB7) reverts to Input mode and the processor accepts its
8-bit contents as an Instruction Word.
Figure 5 illustrates the timing.
(ii) Access of External Data Memory
. In the extended data memory access operation during READ/WRITE cycle the
following occurs
The contents of RO Rl is output onto BUS (DBO - DB7).
ALE indciates address is valid. The trailing edge of ALE is used to
latch the address externally.
A read RD or write WR pulse on the corresponding output pins indicates
the type of data memory access in progress. Output data valid at trailing edge of WR and input data must be valid at trailing edge of RD.
Data (8-bits) is transferred over BUS.
-746-
TOSHIBA INTEGRATED CIRCUIT
TMPB049PI-6, TMPl039PI-6
TECHNICAL DATA
XTALl Input
(6NHz)
~'1
(2}!Hz)
Generated
internally ¢2
State
__---...InL-_----'n
I 1
Inst ruct ion
I Fetch
n
n
3
Execution
2
Decode
1 State
1
4
DBO -
1
Execution
CyclE'
r
Next Address Latch Timing
Instruction Cycle Timing
Address
P20 - P23
5
Execution
ALE
(400kHZ')----------------------~
Fig.4
n
Address
Address
DB7
Instruction
ALE
PSEN
~
\
Fig. 5
jI
\
jI
Timing of External Program Memory Access
-747-
L
TOSHIBA INTEGRATED CIRCUIT
TMP8049PI-6, TMP8039PI-6
TECHNICAL DATA
Pr()~ram
Pro~ram
Data Address
Address
,.-----,.
Address
DBG - DB7
ln~tructioll
ALE
Inslruction
~
_ _ _ _ _ _.....J
RD (~R) ------------------------------,
\L------J!
psn;
\'-----J/
External Data
Me~orv
Access Instruction
Suggest we have diagrams
rI
ALE
~
Write
Read
\-----------------
ALE -----"
BUS
BUS
Fig. 6
----0-< >L-J
Timing of Accessing External Data Memory
-748-
Data
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP0049PI-6, TMP8039PI-6
Figure 6 illustrates the t~m~ng of accessing the external data memory
during execution of external program.
(3) Interface with I/O Expander (TMP8243P)
The TMP8049 I/O can be easily expanded using the TMP8243 I/O Expander.
THis device uses only the lower half 4-bits of Port 2 for cornmuication
with the TMP8049. The TMP8243 contains four 4-bit I/O ports which serve
as extensions of one chip I/O and are addressed as Ports (4-7). All
communication takes place over the lower half of port 2 (P20 - P23) with
timing provided by an output pulse on the PROG pin. Each transfer consists
of two 4-bit nibbles the first containing the "OP Code" and port
address and the second containing the actual 4-bits of data.
+12V r -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
EA
oJ
RESET O"":..'------1f-----1'-'
ALE
Input of Internal
RO!-! Address
DBO - DB7
P20, P21
Input of Internal RON Address
Fig.7
Fig.8
Timing of Reading Internal Program Memory
(a) Single Step Circuit
-749-
Input of Internal
R0l1 Address
TOSHIBA INTEGRATED CIRCUIT
1MP8049PI-6, 1MP8039PI-6
TECHNICAL DATA
Reading of Internal Program Memory
The processor is placed in the READ mode by applying +12V to the EA pin and
OV to the RESET pin. The address of the location to be read is then
applied to BUS and the low order 2-bits of Port 2. The address is latched
by a 0 to 1 transition on RESET and the high level causes the contents of
program memory location addressed to appear on the eight lines of BUS.
Figure 7 illustrates the timing diagram for this operation.
(5) Single Step Operation.
A single step feature useful for debug can be implemented by utilizing a
circuit shown in Figure 8 (a) combined with the SS pin and ALE pin.
A D-tYEe flip flop with set and reset is used to generate SS. In the run
mode SS is held high by keeping the flip flop set. To enter single step,
set is removed allowing ALE to bring SS low via reset input. The next
instruction is started by clocking a "1" into the FF which will not appear
on SS unless ALE is high removing reset. In response to SS going high
the processor begins an instruction fetch which brings ALE low resetting
FF and causing the processor to again enter the stopped state.
The timing diagram in this case is as shown in Figure 8 (b). (EA
5V).
(6) Lower Power Stand-by Mode.
The Lower TMP8049 has been organized to allow power to be removed from all
but the volatile, 128 x 8 data RAM array. In power down mode the contents
of data RAM can be maintained while drawing typically 10 - 15% of normal
operating power requirements.
VCC serves as the 5V supply for the bulk of the TMP8049 while the VDD
supplies only the RAM array. In standby mode VCC is reduced to OV but VDD
is kept at 5V. Applying a low level to reset inhibits any access to the
RAM by the processor and guarantees that RAM cannot be inadvertently
altered as power is removed from VCC.
\~-------------------------________
L __________
:
: For two
/
Instruction Inputr-______________________~1~·n~s~truction
__
I)___________
DBO - DB7 --A-d-d-r-e-s-s--(-P-C-)-----~~----~(~__A_d_d_r_e_s_s~(_P_C+
\
ALE
P20-P23
Add re s S (p C)
~
~
X
X\..__A_d_d_r_e_s_s__(_P_C+__l:...)__________
Port20-23
Data
Fig.8(b)
Single Step Operation Timing
-750-
~
TOSHIBA INTEGRATED CIRCUIT
TMP8049PI-6, TMPB039PI-6
TECHNICAL DATA
INSTRUCTION
ACCUMULATOR INSTRUCTION
.
I Instruction Code
I
I
I Mnemon1c
ID71D61DSID41D31D21DI1DOI
Operation
IADD A,Rr
101 11 1101 11 rl rl rl(A)<-(A)+(Rr)
I
I
I
I
I
I
I
I
I
I r = 0-7
IADD A,@Rr
101111101010101 rl(A)<-(A)+«Rr»
I
I
I
I
I
I
I
I
I
I r = 0, 1
IADD A,ifData
010 01010101 11 II(A)<-(A)+Data
I
d71d6 dSld41d31d21dlidOI
!ADDC A,Rr
01 1 11 11 11 rl rl rl(A)<-(A)+(Rr)+(C)
I
I
I
I
I
I
I
I r = 0-7
IADDC A,@Rr
01 11 11 11010101 rl(A)<-(A)+«Rr)+
I
I
I
I
I
I
I
I
I (C)
I
I
I
I
I
I
I
I
I r = 0, 1
IADDCA,l/Data I 01 01 0111 01 0111 II(A)<-(A)+Data+(C)
I
Id71d61dSld41d31d21dlidOI
IANL A,Rr
1011101 11 11 rl rl rl(A)<-(A) and (Rr)
I
I
I
I
I
I
I
I
I
I r = 0-7
I
101 1101 11010101 rl(A)<-(A)and «Rr)) I
IANL A,@Rr
I
I
I
I
I
I
I
I
I
I r = 0, 1
I
101110111010111 II(A)<-(A) and Data I
IANL A,l/Data
Id71d6idSld41d31d21dlidOI
I
I
101 110101 11 rl rl rl(A)<-(A) or (Rr)
I
IORL A,Rr
1IIIIIIIIr=0-7
I
I
IORL A,@Rr
I 01 11 01 01 01 01 01 rl (A)<-(A) or «Rr»1
I
I
i
I
I
I
I
I
I
I r = 0, 1
I
IORL A,l/Data
101 II 01 01 01 01 Ii 11 (A)<-(A) or Data
I
id7id6ldS!d4id3ld2ldlidOI
I
I
I 11 1101 11 11 rl rl rl(A)<-(A) EOR (Rr) I
IXRL A, Rr
I
I
I
I
I
I
I
I
I
I r = 0-7
I
111110111010101 rl(A)<-(A) EOR«Rr»I
IXRL A,@Rr
I
I
I
I
I
I
I
I
I
I r = 0, 1
I
I 11 11 01 11 01 01 11 11 (A)<-(A) EOR Data I
IXRL A,l/Data
Id71d61dSld41d31d21dlidOI
I
I
IINC A
I 01 01 01 11 01 11 11 11 (A)<-(A)+1
I
IDEC A
10101010101 11 11 II(A)<-CA)-1
I
I 0 I 0 I 11 0 I 0 I 11 11 11 CA) <-0
I
I CLR A
I 0 I 0 I 11 11 0 I 11 11 11 (A) <-NOT CA)
I
I CPL A
101110111011111 1 I Decimal Adjust
I
IDA A
IAccumulator
I
I
I
I
I
I
I
I
I
I
ISWAP A
101110101011111 II(A4-n-)CAO-3)
I
I
I
I
I
I
I
I
I
I
I
(Rr)
I
<-I
I I I I I I I I
I
I I I I I I I I r =a - 7
01 01 11 01 01 01 01 rl(A)-->(Rr))
I
<-/
/
I ! 1 /
/
1
I
I,
I
/ r = 0, 1
I
I
I
I I
01 at I! 11 0/ 0: at r! (AO-3)-->«RrO-3))I
<-I
/
/
/
I I I I I
I
I I I I I I I I r = 0, 1
1
11 01 01 01 01 01 01 rl (A)<--(Rr))
I
I I I I I I I I r = 0, 1
I
11 01 01 11 01 01 01 rl «Rr))<--(A)
I
I
I I I I I I I I r = 0, 1
11 01 11 01 01 01 11 1 I (pco-7)<--(A)
I
I I I I I I I I (A)<--( (PC))
I
11 11 11 01 01 01 11 1 I (pCO-7)<--(A)
I
I I / I / I / I (PC8-11)<--001l
I
I
I I / / I I / I (A)<--«PC))
-755-
I Cycles I
I
I
I
I
I
I
I
I
I
I
2 I
I
I
I
I
I
I
I
I
I
I
I
2 I
I
I
I
2 I
I
I
I
I
I
1 I
I
1 I
I
I
I
I
I
/
I
/
I
2
2
2
2
I
I
I
I
I
I
I
I
I
I
Flag I
CIACI
-I -I
- I -I
-I -I
I I
-I -I
I I
-I -I
I I
-I -I
I I
-I -I
I I
-I -I
I I
-I -I
-I -I
-I - I
I I
I I
-/ -/
1
I
-/ -/
I I
I I
-I -I
I I
-I -I
I I
-I -I
I I
-I -I
I I
/
I
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPB049PI-6, TMP8039PI-6
Timer/Counter Instruction
I Mnemonic
I
IMOV A,T
IMOV T ,A
I STRT T
I
I
I STRT CNT
I
I
I
I STOP TCNT
I
I
lEN TCNTl
I
IDIS TCNTl
I
Instruction Code
I
D71D61DSID41D31D21DI1DOI
01 11 01 01 01 01 1! 01 (A)<--(T)
01 11 11 01 01 01 11 01 (T)<--(A)
01 11 01 11 01 11 0 11Counting is
!started in the
I I I I I I
timer mode
I I I
I
01 11 0 I 0 0 11 0 1 Counting is
started in the
I I I
I
event counter
I I I
I
I I I I I I I Imode
01 11 11 01 01 11 01 11Stop both time
I I I I I I I laccumulation and
I I I I I I I levent counting
01 01 11 01 01 11 01 l!Timer interrupt
I I I I I I I lis enabled
01 01 11 11 01 11 01 IITimer interrupt
lis disabled
IBytes I Cycles I Flag I
I
I clAcl
I
1 -I -I
1
1
I -I -I
I
I
I -I -I
I
I
I I
I I
I -I I I
I -I -I
I I I
I -I -I
I I I
I I I
I -I -I
I I I
I -I -I
I I I
Control Instruction
Mnemonic
EN I
DIS I
SEL RBO
SEL RBI
SEL MBO
SEL MBI
ENTO CLK
NOP
Instruction Code
Operation
IBytes ICyclesl~1
I
D7!D6!DS!D4 I D3!D2ID1\Dol
I C AC!
!
I
O! 0; 01 0\ 01 Ii 0; liExternal interrupti
-i
I I
I
!
I
I II ! I I II I lis enabled
1 I - -I
01 0 0 1 I! 01 I! 01 1!Externa1 interrupt!
I
I
I
I I I 0 1 I I I lis disabled
1 I - -I
11 11 01 I 01 11 01 11 (BS)<-- 0
I
1 I - -I
11 11 01 11 01 11 01 11 (BS)<-- 1
I
1 I - -I
11 11 11 01 01 11 01 11 (DBF)<-- 0
I
1 I - -I
11 11 11 11 01 11 01 11 (DBF)<-- 1
I
1 I - -I
01 11 11 11 01 11 01 liTO is enabled to I
I
1
I 1 1 I 1 1 1 lact as the clock 1
I
I
1 I 1 1 1 1 1 1output
1
1 I - -I
01 01 01 01 01 01 01 OINo oEeration
1 1
1
-756-
TOSHIBA INTEGRATED CIRCUIT
TMP8049PI-&, TMPB039PI-&
TECHNICAL DATA
ITMP8049PI!8039PI:
INDUSTRIAL SPECIFICATION I
ABSOLUTE MAXIMUM RATTINGS
I SYMBOL I
ITEM
IVDD
IVDD Supply Voltage (with respect to GND (VSS))
Ivcc
Ivcc Supply Voltage (with respect to GND (VSS))
IVINA
IInput Voltage (Except EA)
IVINB
IInput Voltage (Only EA)
IPD
IPower Dissi ation (Ta - 70'C)
ITSOLDER ISolderin Tem erature (Solderin Time 10 sec
ITSTG
IStorage Temperature
ITOPR
10perating Temperature
DC
I RATTING
I-o.sv to + 7V
I-O.SV to + 7V
I-o.sv to + 7V
I-o.sv to + 13V
I
1.SW
260' C
-5S'C to IS0'C
1-40'C to 8S'C
CHARACTE=R~I~S~T~IC~S~__~77_
ITA=-40'C to 8S'cl, VCC=VDD=+5V±10%, VSS=OV, Unless Otherwise Noted.
PARAMETER
I SYMBOL I
IInput Low Voltage
I VIL
I (Except XIALI,XTAL2,RESET)
I
IInput Low Vol~
IVILI
I (XTALI,XTAL2,RESET)
I
IInput High Voltage
IVIH
! (Except XTALl,XTAL2,RESET)
i \'IH 1
IInput High Voltage
i (XIALl,XTAL2.RESET)
i
lOut ut Low Volta e (BUS)
IVOL
IVOLI
10utpu~Low Voltage
I (RD, WR, PSEN, ALE)
I
!Output Low Voltage (PROG)
IVOL2
10utput Low Voltage
IVOL3
I (For other output pins)
I
IVOH
10utput High Voltage (BUS)
IVOHI
10utpu~High Voltage
I (RD, WR, PSEN, ALE)
I
IVOH2
10utput High Voltage
I (For other output pins)
I
I
I
IInput Leak Current (Tl , INT)
I ILl
I
I
IInput Leak Current
IILl 1
I (PlO-17, P20-P27, EA, SS)
I
10utput Leak Current (BUS, TO)
IILO
I (Hi h im edance condition)
I
VDD Su I Current
IIDD
IIDD+ICCITotal Supply Current
ITEST CONDITIONS IMIN.ITYP.IMAX.IUNITI
1-0.51 0.71 V
I
I
I
I
I
0.61 V
I-o.si I
I
I
I
I
vcci V
I 2.21 I
I
I
i
vcci V
I 3.8! I
I
I
I
1.6 rnA
0.451 V
I
I
I IOL
IOL
1.6
rnA
0.45 V
I
I I
I
I
I
I
0.8 rnA
0.4SI V
I - I I IOL
1.2 rnA
0.451 V
I - I I IOL
I
I
I
I
- I V
I 2.41 I IOH =-28011A
- I V
I IOH =-8011A
I 2.41 I
I
I
I
- I V
I 2.41
I IOH -- 3011A
I
I
I
I
I
I
I
I
±lol llA
Ivss ~ VIN ~ VCC I - I I
I
I
1
I
- I - 1-7001 llA
IVSS+0.4S~VIN~Vccl
I
I
I
I
I
- I - I ±lol llA
IVSS+O.4S~VIN~vccl
I
I
I
I
I
I
I - I - I 501 rnA
I
I 170, rnA
-757-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPB049PI-a, TMPB039PI-a
AC CHARA CTE::R.,:..I,,-ST:..;I;-;C""S,-=-_-::-::-:ITA=-40·C to 8s·cl, VCC=VDD=+sV±lO%, VSS=OV, Unless Otherwise Noted.
I SYMBOL I
PARAMETER
ITEST CONDITIONS IMIN.ITYP.IMAX. UNITI
ItLL
IALE Pulse Width
I
I 2001 I ns I
ItAL
IAddress Setup Time (ALE)
I
I 1201 I ns I
ItLA
IAddress Hold time (ALE)
I
I 801 I ns I
I
I
I
I
I
I
I
I tCC
I Control Pulse Width(PSEN,RD,WR) I
I 4001 I ns I
I
I
I
I
I
I
I
IData Setup Time (WR)
I
I 420 I I ns I
I tDW
I
I
I
I
I
I
I
ItWD
IData Hold Time (WR)
I
I 801 1ns I
ICycle Time
I
12.51
115.0 Ils I
ItCY
I
I
I
I
I
I
I
ItDR
IData Hold Time (PSEN,RD)
I CL - 20 pF
I
01
12001 ns I
I
I
I
I
I
I
I
I
ItRD
IData Input Read Time (PSEN, RD)I
- I 14001 ns I
I
I
I
I
I
I
I
I tAW
I Address Setup Time (WR)
I
230 I I I ns I
I tAD
I Address Setup Time (Data Input) I
- I I 600 I ns 1
I
I
__
I
I
I
I
1
ItAFC
IAddress Float Time (RD, PSEN)
1
-401 1 I ns 1
I tCA
I Internal between Control Pulse I
10 I I I ns I
1~~__~!a~n=d~A~L~E~~~____~__~~~I~__________~~~I__~I__~I____ 1
i tCP
:?ort Control Setup Time (PROG) I
1151
i
1 ns 1
ItPC
:Port Control Hold Time (PROG)
65\ 1 I ns I
ItPR
IPort 2 Input Data Set Time
- 1 I 8601 ns I
____-+~(P~R=OG=)~______~~~--~_+------------~~I--_+I--_+I---I
I tDP
10utput Data Setup Time (PROG)
230 I 1 - 1 ns I
I tPD
10utput Data Hold Time (PROG)
251 I - I ns I
IPort 2 Input Data Hold Time
01 I 160 I ns I
I tPF
I-=__-+I~(P~R~OG~)~~~____________+-__________~~~I__~I---+I---I
I tPP
I PROG Pulse Width
920 I I - 1 ns I
ItPL
IPort 2 I/O Data Setup Time
3001 I - I ns I
ItLP
IPort 2 I/O Data Hold Time
1201 I - I ns I
Note :tCY=2.slls, Control Output:CL=80pF, BUS Output: CL=lsOpF, PORT20-23:
CL=80pF.
-758-
TOSHIBA INTEGRATED CIRCUIT
TMPS049PI-6, TMP8039PI-6
TECHNICAL DATA
TIMING WAVEFORM
A. Instruction Fetch from External Program Memory
tCl'
ALE
BUS
B. fi.e£d from External Data Memory
ALE
\'--_ _ _ _~if
tc
RD
BUS
c.
Write into External Data Memory
ALE
BUS
-759-
TOSHIBA INTEGRATED CIRCUIT
TMPl049P)-S, TMP8039PI-6
TECHNICAL DATA
D. Timing of Port 2 during Expander Instruction Execution
TYPICAL CHARACTERISTICS
ALE
PORT20
I
PORT23
PCH
Port
(Output Data)
PORTZO
I
PCH
PORT23
Port
(Input Data)
PROG
*
Input Enabled State
TYPICAL CH;P,ACTERISTICS
3) BUS, PI, P2: 10L - VOL
VDD=VCC=5V
-50
--
J
50
TA=25°C
1
~
<
..:;
-30
"- ~
::c
H
0
-10
o
o
,..J
....,c
-........
30
10
t--2
VOH (V)
o
o
4
VDD=VCC=5V
I TA=25°C
)",--1
L
V
1
J
,/
2
4
VOL (V)
2) PI, P2:IOH -VOH
VDD=VCC=5V
-500
'.2;:l
::c
TA=25°C
-300
0
H
-,....
-100
r--.
4
2
VOH (V)
-760-
TOSHIBA INTEGRATED CIRCUIT
TMP8049PI-6, TMPB039PI-6
TECHNICAL DATA
PROGRAM TAPE FORHAT
THP8049 programs are delivered in the form of paper tape with the following
format and it is required to attach the tape list. The format of paper tape
is same as the Intel type object tape (hexadecimal tape output by Intel MDS
system, PROMPT 48 Development Tool, etc.)
(] I
Tape Format
0t J
Leader, 50 "l\ULL" characters or more
Conrrnents
(T)
Co!Ilr.'tent
(Record mark II:" is not inClUded)}
Option
1-----''---1-" - - -
Record Mark
Record Length (2 hexadecimal digits)
Loading Address (4 hexadecimal digits)
"00"
Record Type (2 Digits)
Normal Record
"01" •••. End of File Record
Data
~
CR)
il"i::l.:
Check Sum (2 hexadecimal digits)
Dummy characters (RFBOl1T, BLANK) before and after "(CR) (LF)" are
optional.
--- " .. Record Mark (Repeated belo.·)
'R
~
LF
H)"""'" " """," 'om" ...., ~"'
(2) Example of Tape List
TOSHIBA MICRO COMPUTER TLCS-48
:l00000000665C7D79CF50F3F951FED55A8FF16E570
:lOOOl00088884DDE67D31F5D8ABA6DF292Fl13F5Cl
:l00020004FFlFB5DFFDAA96A99CF7DF94A346B7C09
:l0003000197352F729F12F79AA9C057C5B851EED77
:l003C0005DFDB5E556A67277F61A51C631CF9FOE80
:l003DOOOBD2F6F20E8BB1977E3FB5ADIF41FDAA7E2
:l003EOOOB53D42EOEC32546025B7308CDD52063DID
:l003FOOOB4BE9E9E345B6138060B20VC372BF60BD6
:OOOOOOOlFF
-761-
TOSHIBA INTEGRATED CIRCUIT
TMPBD49PI-6, TMPBD39PI-6
TECHNICAL DATA
OUTLINE DRAWING
Unit in mm
40
21
><
<:
~
...'"
20
r-____________S~J.~3~M~A~X~·__________________~
z
~
f 1
J~ =::, !152<±o25
I
z
O.S ± 0.1S
2.S4 ±0.25
1. 4 ± 0.1S
\,
025
0-1So
Note: 1. This dimension is measured at the center of bending point of leads.
2. Each lead pitch is 2.S4mm, and all the leads are located within
±O.2Smm from their theoritical positions with respect to No.1 and
No.40 leads.
-762-
TOSHIBA INTEGRATED CIRCUIT
TMP8243PflMP8243PI
TECHNICAL DATA
INPUT/OUTPUT EXPANDER
GENERAL DESCRIPTION
The TMPS243P is an input/output expander designed specifically to provide a low
cost means of 1/0 expansion for the TLCS-S4 family.
The I/O ports of the Tl1P8243P serve as a direct extension of the resident I/O
facilities of the TLCS-84 microcomputers and are accessed by their own MOVD,
A~LD,
and ORLD instructions.
FEATURES
o
Simple interface to TLCS-S4 microcomputers
o
Four 4-bit I/O ports
o
A1W and OR directly to ports
o
Single 5V supply
o
High output drive
o
Direct extension of resident THPS04SP/TMPS049P I/O ports.
o
Compatible with intel's S243
o
-40°C to +85°C Operation (TMP8243PI: Industrial Specification)
BLOCK
PIN CONNECTION (TOP VIEW)
DIAGRA~1
PORT 4
I-'~)C
vee
J4~
P51
=~=-
pt,:;.:
14%
Pc;'
1 ~=
Per::.
c:'
:Pi'1
FROG
1'62
F23
1'63
P:<~
PI~
1'21
P72
P20
1'71
'j l~l'
J~IC
PORT 5
PORT 2
PORT 6
PORT 7
-763-
TOSHIBA INTEGRATED CIRCUIT
TMP8243P/TMP8243PI
TECHNICAL DATA
PIN NAMES AND PIN DESCRIPTION
PROG (Input)
Clock Input.
A high to low transistion on PROG signifies that address and
control are available on P20-23, and a low to high
transi~ion
signifies that
data is available on P20-23.
CS Unput)
Chip Select Input.
A high on CS inhibits any change of output or internal
status.
P20-23 (lnput/Output, 3-state)
Four (4) bit bi-directional port contains the address and control bits on a
high to low transition of PROG.
During a low to high transition contains the
data for a selected output port if a write oepration, or the data from a
selected port before the low to high transition if a read operation.
P40-43, PSO-S3, P60-63, P70-73 (Input/Output, 3-state)
Four (4) bit bi-directional I/O ports.
May be programmed to be input (during
read), low impedance latched output (after write) or a
3-state (after read).
Data on pins P20-23 may be directly written, ANDed or ORed with previous data.
VCC (Power)
+5 volt supply
GND (Power)
o volt
supply
FUNCTIONAL DESCRIPTION
General Operation
The THP8243P contains four 4-bit 1/0 ports which serve as an extension of the
on-chip 1/0 and are addressed as ports 4-7.
performed on these ports.
o
Transfer accumulator to port
o
Transfer port to accumulator
o
AND accumulator to port
o
OR accumulator to port
-764-
The following operations may be
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP8243P/TMP8243PI
All communication between the TMPS04SP and the 1l1PS243P occurs over Port 2
(P20-23) with timing provided by an output pulse on the PROG pin of the processor.
Each transfer consists of two 4-bit nibbles.
A high to low transition of the PROG line indicates that ~ddress is present
while a low to high transition indicates the presence of data.
Additional
T}W8243P'S may be added to the 4-bit bus and chip selected using additional
output lines from the T}WS04SP/S035P.
Power On Initialization
Initial application of power to the device forces input/output ports 4, 5, 6,
and 7 to the tri-state and port 2 to the input mode.
high or low when power is applied.
The PROG pin may be either
The first high to low transition of PROG
causes device to exit power on mode.
The power on sequence is initiated if VCC
drops be 10'" IV.
P2l
P20
Address Code
P23
P22
Instruction Code
o
o
o
Port 4
o
Read
1
Port 5
o
o
1
Write
1
o
Port 6
1
o
ORLD
1
1
Port 7
1
1
ANLD
Write Modes
The device has three write modes.
selected port and old data is lost.
MOVD Pi, A directly writes new data into the
ORLD Pi, A takes new data, OR's it with
the old data and then writes it to the port.
ANLD Pi, A takes new data
it with the old data and then writes it to the port.
A~D's
Operation code and port
address are latched from the input port 2 on the high to low transition of the
PROG pin.
On the low to high transition of PROG data on port 2 is transferred
to the logic block of the specified output port.
After the logic manipulation is performed, the data is latched and outputed.
The old data remains latched until new valid outputs are entered.
-765-
TOSHIBA INTEGRATED CIRCUIT
TMP8243P/TMP8243PI
TECHNICAL DATA
Read Hode
The device has one read mode.
The operation code and port address are latched
from the input port 2 on the high to low transition of the PROG pin.
As soon
as the read operation and port address are decoded, the appropriate outputs are
3-stated,
and the input buffers switched on.
by a low to high transition of the PROG pin.
The read operation is terminated
The port (4, 5, 6 or 7) that was
3-stated mode while port 2 is returned to the
selected is switched to the
input mode.
Normally, a port will be in an output (write mode) or input (read mode).
If
modes are changed during operation, the first read following a write should be
ignored; all following reads are valid.
This is to allow the external driver
on the port to settle after the first read instruction removes the low impedance
drive from the TMP8243P output.
A read of any port will leave that port in a
high impedance state.
125
...:l
100
o
H
W
75
GUARANTEED WORST CASE
CURRENT SINKING
CAPABILITIES OF ANY 1/0
PORT PIN vs. TOTAL SINK
CURRENT OF ALL PINS
50
...:l
25
"'E-
,Input Leah.Gge Port 4-7
iInput Leadage Port 2, cs, PROG
[\' CC
OveV1N' Vel'
+~O
ICC
-'
10L
2.4
_
V
V
1
12~
'---~
Supply Current
[Sum of all 10L of 15 Outputs
1
10.45 I
\'UI:2
I
V
7sTI,----L~
I
:Output High
Ports 4- 7
jvct 0.5
i
IiI
\'OHl
\'01 tage
I 0.8 I V
--+
I
I OL=0.6",_\
0
Units
Typ.1 Max.
-0.5
VIH
"
VOLl iOutput Low Voltage Ports 4-7
VOL 3
260°C
---
-J
10
I
5 mA Each Pin
V
V
71
,_A
10
;li\
I 20
""\
I 80
rnA
* See following graph for additional sink current capability
A.C. CHARACTERISTICS
Symbol
tA
tB
tc
vee
Parameter
= 5V ± 10%
-
Test Condition
Min.
Code Valid Before PROG
CL
~
SOp}'
100
Code Valid After PROG
C],
~
20pF
60
C], = 80pF
CL = 20pF
200
C], = 20pF
0
t-
jDaLd
Valid Before PROG
~~lta-Valid
tll
TA = O°C to 70 0 e,
After PROG
!Floating After PROG
Typ.
Hax. Units
I ns
i
n5
ns
--
20
ns
150
ns
-
tK
iPROG Negative Pulse Width
tCs
CS Valid Before/After PROG
tpo
Ports 4-7 Valid After PROG
- - r---------
ns
50
ns
CL = 100pF
tLPl Ports 4-7 Valid Before/After PROG
tAce IPOrl 2 Valid After PROG
700
--
100
--,-
CL = 80pF
-768-
1-
700
ns
--
ns
650
ns
TOSHIBA INTEGRATED CIRCUIT
TMP8243P/TMP8243PI
TECHNICAL DATA
IH1PS243PI
INDUSTRIAL SPECIFICATION I
ABSOLUTE MAXIMUM RATINGS
SVml1(1 I I
Rating
I t em
G~W
-0.5\' t" +7.0V
-~~---r---;---~----- ~--~~~~-~--I-~~~---~~~~-__1
-0.51' t" +7.0\'
1'1:';:
I IIl])ul \'(d tage wHIl He'spec! to C:"l)
! Vee SuppIv Voltelg'" "'itl1 Hl'sp('cl
Vcc:
VOL']
l'n
[0
-0.5\' to +7.0V
I (1"tpul V"llagl' "'ill, He'specr to r;r,])
~_ P(wer Dissipation
-------------1------------__1
800ml')
~~. DI~_ SO I der i n g
Te mpe rat ure
TSTC
i
TOFR
I Operating Temperature
Stor"ge Tc'mperature
D.C. CHARACTERISTICS
260°C
(So 1 de r i_n_"'g'----T_i_m_e_l_O_s_e_c_....:,)_ _ _-+_____
:. . . . _____--j
-55°C to +150 0 C
-40°C to +85°C
TA=-40"C to 85°C, Vce=5V']07
Nin. I Typ. I Hax.
O.B
I
Test Condition
Symbol
VIL
Input LOI, Vol tage
VIH
Input High Vol tage
Vall
\'OL2
Outp tu Low Voltage Forts 4-7
Outp"t LOI'I Voltage Fort 7
IOL=/,.5mA
(lutput
10L =0.61TC\
i
II
Output High Voltage Port 2
I OH =-240,A
IOH=-l 00 l.A
Input Leakage Ports 4- 7
OVO:Vn:;SVce
Input Leakage Port 2, CS,FEOC
VCC Suppl v Current
OV':::VIN'::VCC
Sum of all lOL of 16 outputs
4 . 5rnJ\ each pin
\'OL3
Parameter
I
--
VOHI
VOH 2
1 ILl
IIL2
IOL
Voltage Fort :2
(lUlput High V"l tage Forts 4- 7
I
I
I
i
I
T
ICC
LO,\,',7
enits
V
-0.5 I
2.0 !
0.45 I
V
I
V
i
!
1
0.45
2,4 iI
2.4 !!
I
-]0 I
,
i
I
I
I
I
i
i
I
I
I 10
I
-
I
I
I
-]0
1
V
i
I
I01,=20mA
~Vcc+0.5i
I
I
--
-V
V
~~
1-:/\
10
20
mA
72
J1'u'I
See following graph for additional sink current capability
A.C. CHARACTERISTICS
Symbol
tA
TA=-40"C to 85°C, VCC =5V±lO%
Parameter
tB
C"de Vali d before FROG
Cod" Valid after pEOG
tc
Data Valid before PEOG
tD
Data \'alid after FRO"
tH
Fl"ating after PROG
tK
PROG Negative Pulse Width
tes
tpo
Ports 4- 7 Valid after FROG
tLFl
lACe
Fort s 4- 7 Va 1 i d be fore/after FROG
Port .) Volid after PROG
Nin.
Typ.
Max.
e L = 80pF
] on I
CL = 20pF
60 I
e 1. = 80pF
I 200 I
-~~---~-~---f------ ~--+
CL = 20pF
20 :
C],
= 20pF
0
ns
I ns
ns
150
ns
700
lOO
C1. = BOpF
-769-
ns
ns
50
CL = 100pF
llnits
ns
700
CS Valid before/after PROG
f - - - - - t------~----------
t----
Test Condition
n8
ns
(,50
ns
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
THHNG
TMP8243P/TMP8243PI
~!AVErORt1
PROG
~,J1r"
~. ~
PORTZ
r1
~.iCj :5--
~STRue~iY:
DATA
X'--F-L-OA-T--
~
C-------~i
PORTZ
r--------
OUTPUT
VALID
I
PORT4-7
PREVIOUS OUTPUT VALID
PORT4-7
INPUT VALID
tpo
OUTPUT
VALID
y-
tes
-770-
TOSHIBA INTEGRATED CIRCUIT
TMP8243P/TMP8243PI
TECHNICAL DATA
OUTU NE DRilYHiGS
Unit in mm
Note:
Each lead pitch is 2. 54mm.
All leads are located within
O.25mm of their true longitudinal position .'i th respect
to No.1 and No.24 leads.
All dimensions are in millimeters.
-771-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
-772-
TMP8243P/TMP8243PI
TOSHIBA INTEGRATED CIRCUIT
TMP82C43P
TECHNICAL DATA
INPUT/OUTPUT EXPANDER
GENERAL DESCRIPTION
The
T~W82C43p
is an input/output expander designed specifically to provide
a low cost means of I/O expansion for the TLCS-84C family.
The I/O ports of the THP82C43p serve as a direct extension of the resident
I/O facilities of the TLCS-84C microcomputers and are accessed by their own
HOVD, ANLD, and ORLD instructions.
FEATURES
° CNOS LSI for low power dissipation
° Low cost
° Simple interface to TLCS-84C microcomputers
° Four 4-bit I/O ports
°
AN~
and OR directly to ports
° Single 5V supply
° High output drive
° Direct extension of resident TI!P80C49P-6 I/O ports.
° PIN compatible with intel's 8243
° Extended operation temperature range
-40°C to 85°C
BLOCK DIAGRAt1
PIN CONNECTION (TOP VIEW)
!-':<,
',J
-"u.
~\ ~
-4-:,
[,:
{)()
~.
'C1
.~.
}:\)}
10"
J ~~
j-'7~
J :"".l
t 7%
..
.
~)
;~.
'
PORT 6
!b:-"
}~.'
PROG
;','1
PORT 7
' ','u
-773-
TOSHIBA INTEGRATED CIRCUIT
TMP82C43P
TECHNICAL DATA
PIN NAMES AND PIN DESCRIPTION
PROG (Input)
Clock input.
A high to low transistion on PROG signifies that address and
control are available on P20-23, and a low to high transition signifies
that data is available on P20-23.
CS (Input)
Chip Select Input.
A high on CS inhibits any change of output or internal
status.
P20-23 (Input/Output, 3-state)
Four (4) bit bi-directional port contains the address and control bits on a
high to 1m" transition of PROG.
During a low to high transition contains
the data for a selected output port if a write operation, or the data from
a selected port before the low to high transition if a read operation.
P40-43, P50-53, P60-63, P70-73 (Input/Output, 3-state)
F.our (4) bit bi-directional I/O ports.
Hay be programmed to be input (during
read), low impedance latched output (after write) or a 3-state (after read).
Data on pins P20-23 may be directly written, ANDed or ORed with previous data.
VCC (Power)
+5 volt supply
GND (Power)
o volt
supply
FUNCTIONAL DESCRIPTION
General Operation
The TMP82C43P contains four 4-bit I/O ports which serve as an extension of
the on-chip I/O and are addressed as ports 4-7.
may be performed on these ports.
o
Transfer accumulator to port
o
Transfer port to accumulator
o
AND accumulator to port
o
OR accumulator to port
-774-
The following operations
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP82C43P
All communication between the microcomputer (THP80C49P-6) and the nrp82C43P
occurs over Port 2 (P20-23) with timing provided by an output pulse on the
PROG pin of the processor.
Each transfer consists of two 4-bit nibbles.
A high to low transition of the PROG line indicates that address is present
while a low to high transition indicates the presence of data.
Additional
THP82C43P's may be added to the 4-bit bus and chip selected using additional
output lines from the microcomputer.
Power On Initialization
Initial application of power to the device forces input/output ports 4, 5,
6, and 7 to the tri-state and port 2 to the input mode.
either high or low 'vhen power is applied.
The PROG pin may be
The first high to low transition
of PROG causes device to exit pmver on mode.
The power on sequence is ini-
tiated if VCC drops below IV.
p21
P20
Address Code
P23
p22
0
0
Port 4
0
0
0
1
Port 5
0
1
0
Port 6
1
0
ORLD
1
1
Port 7
1
1
ANLD
Instruction Code
Read
Write
Write Modes
The device has three write modes.
MOVD Pi, A directly writes new data into
the selected port and old data is lost.
with the old data and then
~~ites
ORLD Pi, A takes new data, OR's it
it to the port.
ANLD Pi, A takes new data
AND's it with the old data and then writes it to the port.
Operation code
and port address are latched from the input port 2 on the high to low transition of the PROG pin.
On the low to high transition of PROG data on port 2
is transferred to the logic block of the specified output port.
After the logic manipulation is performed, the data is latched and outputed.
T'
'd data remains latched until new valid outputs are entered.
-775-
TOSHIBA INTEGRATED CIRCUIT
TMP82C43P
TECHNICAL DATA
Read Hade
The device has one read mode.
The operation code and port address are
latched from the input port 2 on the high to low transition of the PROG
pin.
As soon as the read operation and port address are decoded, the
appropriate outputs are 3-stated, and the input buffers switched on.
The read operation is terminated by a low to high transition of the
PROG pin.
The port (4, 5, 6 or 7) that was selected is switched to the
3-stated mode while port 2 is returned to the input mode.
Normally, a port will be in an output (write mode) or input (read· mode).
If modes are changed during operation, the first read following a write
should be ignored; all following reads are valid.
This is to allow the
external driver on the port to settle after the first read instruction
removes the low impedance drive from the
T~IT82C43P
output.
any port will leave that port in a high impedance state.
-776-
A read of
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMP82C43P
H1P8243P
ABSOLUTE.
11AXH1U~1
RATINGS
snmoLi
ITEi1
Vcc Supply Voltage with Respect to GND
Vec
c--------
~_VH:
-
;
-
-,_. _.
_._--
-
-----
i
Input Voltage with Respect to GND
PD
,
,i
h-SOLDE~
TSTG
I
f-- TOPR
i
I
Output Voltage with Respect to G1W
VII
i
--0.5V to Vcc+0 . 5V
------~---T
Power Dissipation
---0.5V to Vcc+ 0 . 5V
1
250mv]
i
260"C
I
Soldering Temperature (soldering Time 10 sec.)
Storage Temperature
I
Operating Temperature
D.C. CHARACTERISTICS (I) TOPR =-40°C
SYHBOLI
-0.5V to +7.0V
I
~---~
r--
!
--------------------------- ---~~~
~.---------
VOCT
RATING
l_
I
~
85"C,
VCc=5V~10%,
TEST CONDITION
PARAHETER
-65"C to +l50°C
-40"C to +85°C
VSs=OV
HIN.
TYP.
IInput Low Voltage
HAX.
UNITS
0.8
v
v
~____-+__l_._o__rl__V__~
I
I-
0.45
I
v
1
VOH22!Out p ut High Voltage Port 2
I OH=-0.3mA
IILl 'Input Leakage Port 4-7
I---ri----------
IIL2 IInput Leakage Port 2, CS,PROG
I
VSS-VIN-VCC....J___
VSS~VIN~VCC
±'
IVcc-O.8!
----~--<--<~---,-
__
'I
v
V
I
no
J -±-l-O-~'---~
I'
~~~~-~--~~--~--------
,
ICel iPower Supply Current (1)
t
f---
VCC=5V,VIL=0.2V
'IVIH~VCC-O. 2V
IPROGPERI0D=5)JS
- - - - - - - - - - - - I V C C = 5 V , VIL=0.2V
I
I
_ _
-----11
I
vA
I
!
I
vA
2
rnA
I-
-tl-~---+I----
1CC2 IPower Supply Current (2)
IV 1H =VCC-O. 2V
--t--;-]r
wA
I
IPROG=V CC-O. 2V
~I-0-I-~~I-s-u-m-O~f-a-1-1~I--O-1-~-O--£~1-6~O-u-t-p--u-t-s~~5m-A~E-a~C~.l-1-p-i-n~~-~~~~i 80 -~~-mA--~
-777-
TOSHIBA INTEGRATED CIRCUIT
TMP82C43P
TECHNICAL DATA
D.C. CHARACTERISTICS (TI) TOPR =-40°C to S5°C, Vcc=5V::20%, vss=ov
PARj'.~1ETER
SYMBOL
VIL
Input Low Voltage
i
VIH
I
TEST CONDITION
I
i
I Input High Voltage
VOLl ; Output Low Voltage Ports 4-7
VOL 2
VOL3
-0.5
5.5V:5VCC~6.0V
0.5VCC
IOL=4mA
I OL=15mA
Output Low Voltage Port 2
I OL=0.6mA
I
VOm2:I Ou tpu t High Voltage Ports 4-7 I
I
IOL
4.0V~VCC~4.5V
Output Low Voltage Port 7
VO:122 ! Output High Voltage Port 2
I
Sum of all IOL of 16 outputs
A.C. CHARACTERISTICS
SYHBOL
mN.
I
i
IOH=-200~A
I
I
MAX.
UNITS
O.l5VCCI
V
VCC
V
0.45
V
1.0
iI
I
0.45
I VCC-O.S
I
II
IOH=-lOO~A I VCC-O.SI
I
4mA Each Pin I
i
64
V
V
I
I
V
I
V
rnA
TOPR=-40°C to SO°C, VCC=5V±20%, VSS=OV
PARAMETER
TEST
CONDITIO~
HIN.
tA
Code Valid Before PROG
CL=SOpF
100
tB
Code Valia "iter PROG
Cl-20pF
60
tc
Data Valid Before PROG
CL=SOpF
tD
Data Valid After PROG
CL=20pF
tH
Floating After PROG
CL=20pF
tK
TYP.
CS
tpo
Ports 4-7 Valid After PROG
tIP
Ports 4-7 Valid Before/After
PROG
t ACC
Port 2 Valid After PROG
I
Valid Before/After PROG
200
MAX.
ns
I
!
ns
I
ns
!
150
ns
50
ns
700
ns
ns
100
-778-
ns
700
CL=lOOpF
CL=SOpF
UNITS
ns
20
0
I
I PROG Negative Pulse hlidth
tcs
I
TYP.
650
ns
TOSHIBA INTEGRATED CIRCUIT
TMP82C43P
TECHNICAL DATA
T1t1I NG WAVEFORr1
PROG
FLOAT
PORT2
PORT2
PREVIOUS OUTPUT VALID
PORT4-7
INPUT VALID
PORT4-7
tcs
-779-
OUTPUT
VALID
TOSHIBA INTEGRATED CIRCUIT
,
TMP82C43P
TECHNICAL DATA
OUTU NE DRA\H NGS
PLASTIC PACKAGE
Unit in mm
~
, ' , I
, ,,"I" , , , , "
(Note)
;'::"~~
"
S
"t:-:
Note: Each lead pitch is 2.54mm.
All leads are located within
O.25mm of their true longitudinal position with respect
to No.1 and No.24 leads.
-780-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
APPLICATION SPECIFIC
STANDARD PRODUCTS (ASSP)
Super Integrated New CPU Products
Philosophy
Toshiba has developed the advanced CMOS VLSI technology needed to integrate a Microprocessor and
several Peripheral Devices onto a single Monolithic Silicon Die. Using this Super Integration technology
Toshiba has the capability to define and produce CMOS devices with a particular configuration of CPU
and Peripheral Devices, which will meet the requirements of specific kinds of applications. The first of
these APPLICATION SPECIFIC STANDARD PRODUCTS (ASSP) will soon be available. These devices
offer the user the benefits of lower system cost, greatly reduced PCB size, higher system reliability,
reduced assembly and test costs, and lower power dissipation.
ASSP Products
Type Number
TMPZ84C011 AF
TMPZ84C011 AF-e
TMPZ84C015AF
TMPZ84C015AF-8
TMPZ84C013AT
TMPZ84C01-3AT-e
Function
+ CGC + CTC + I/O (8X5)
+ CGC + CTC + I/O (8X5)
Z80 MPU (4Mhz) + CGC + CTC + PIO + SIO
Z80 MPU (6Mhz) + CGC + CTC + PIO + SIO
Z80 MPU (4Mhz) + CGC + CTC + SIO
Z80 MPU (6Mhz) + CGC + CTC + SIO
Z80 MPU (4Mhz)
Z80 MPU (6Mhz)
TMPZ84C011 AF Block Diagram
No. of
Pins/Pkg
Production
Availability
100/MFP
100/MFP
Nov, 86
Jan, 87
100/MFP
100/MFP
Jan,87
Jan, 87
84/PLCC
84/PLCC
Feb,87
Feb,87
TMPZ84C013/015 Block Diagram
CTC
,------r---r---'i'----------:I..>E.
>EO
CLK/TROO 3
Zo/TOO2
Z-BO
MPU
+CGC
ZCT02
AO AIS
0007
MOO
M"
XTALI
XTALZ
lIlT
"'&r
"
BUSES
TM PZ84C011 AF Applications
TMPZ84C013/015 Applications
• Industrial Control
• Modems
• Robotics
• LAN's
• I/O Intensive Processor
• Communications Control Processor
'Note These devices also have Watchdog Timer Function
-781-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
-782-
TOSHIBA INTEGRATED CIRCUIT TMPZ84COllAF/TMPZ84COllAF-6
CMOS Z80 MICROPROCESSOR
TECHNICAL DATA
GENERAL DESCRIPTION
TMPZ840C011A is a high performance and low power CMOS Z80 microprocessor containing peripheral
functions such as on-chip clock generator controller (CGC), counter timer circuit (CTC), and five 8-bit
parallel input/output ports. TMPZ84COllA is fabricated with Toshiba's C2 MaS technology and molded
in 100 pin flat package.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Z80® software compatible
High speed operation (4/6MHz)
On-chip clock generator controller
Stand-by control is available.
Low power consumption
Operating power supply current
15 rnA Typ. @ 4MHz
1 rnA Typ. @ 4MHz
Power supply current in IDLE mode
Stand-by current
500 nA Typ.
5V±10%
Single power supply
-40°C to 85°C
Wide operating temperature range
Three operation modes
(1) Run Mode
(Normal operation)
(2) Idle Mode
(Only clock generator continues to operate)
(All operation is stopped: Stand-by state)
(3) Stop Mode
(can be programmed as input or output for each
bit)
Five 8-bit ports
Four independent 8-bit counter/timer channels
On-chip dynamic memory refresh register
Three modes of high speed interrupt processing: 8080 similar, non Z-80 peripheral device, and Z80
family peripheral with or without daisy chain.
100-pin flat package
Real-time emulator RTE 80 and emulation board (BM8024) are available.
Note) Five 8-bit parellel
va
va ports do not have daisy chain interrupt function.
Z80® is a trademark of Zilog Inc.
-783-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COllAF
TMPZ84COllAF·6
TECHNICAL DATA
PIN NAMES AND PIN DESCRIPTION
Pin Name
DO -D7
A 0 -A15
PAO -PA 7
PBO -PB 7
PCO -PC 7
PDO -PD7
PEO opE 7
M1
RD
WR
MREQ
IORQ
No. of Pins
4
Input
Input
8-bit bidirectional data bus
16-bit address bus
Port A : Input / Output port
Port B : Input / Output port
Port C : Input / Output port
Port D : Input / Output port
Port E : Input / Output port
Machine cycle 1
Memory read
Memory write
Memory request
Input / Output request
Wait request
Bus request
Bus acknowledge
HALT
Refresh
Input signal for emulator mode.
When EV Tenninal is in high level, Ml and HALT
output is in high impedance state. When EV terminal
is high with active BUSREQ. TMPZ84COllA will
relinquish the internal Z80 cpu portion and will be
controlled by another cpu (i.e. cpu in ICE).
Test terminal. It must be tied to ground.
External clock/timer trigger
3
Output
Zero count/timer out
Interrupt enable input for CTC
Interrupt enable output for CTC
X'tal input/output. Two times frequency is required
for cpu operation.
Mode control inputs
MS1
MS2
Modi!
IDLE
o
0
1
Do not use
o
o
STOP
8
16
8
8
8
8
8
1
1
1
WAfT
BUSREQ
BUSACK
HALT
RFSH
EV
TEST
CLKlTRGO
-CLK/TRG3
ZC/TOO
-ZC/TC02
Description
Direction
1
]
1
I/O, 3-atate
Output, 3-state
I/O, 3-atate
I/O, 3-atate
I/O, 3-atate
I/O, 3-atate
I/O, 3-atate
Output, 3-state
Output, 3-state
Output, 3-state
Output, 3-state
Output, 3-state
Input
Input
Output
Output, 3-state
Output
Input
IEI
1
lEO
XTAL1/XTAL2
1
2
Input
Output
Input/Output
MS1, MS2
2
Input
1
CLK
RESET
INT
NMI
Vcc
Vss
1
1
1
1
Output
Input
Input
Input
Single phase system clock output.
Reset input.
Maskable interrupt request.
Non maskable interrupt request.
5V power supply.
Ground reference. (OV)
-784-
RUN
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COllAF
TMP284C011AF-6
TECHNICAL DATA
I/O PORT CONFIGURATION AND ASSIGNMENT
(1)
Port configuration
DO-D7
t:I
Output buffer
~.
'&."
Port
§
-t>- I--r--~
8
"
l
Note) Each I/O bit can be programmed as input or output. When
reset occurs, Direction control register and port register are
cleared, therefore, all ports are in input mode.
Port Direction]
Input
Output
(2) I/O assignment
Address
I/O Name
I/O Function
A7
A6
A5
A4
A3
A2
A1
AO
CTC
(Counter
/Timer)
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
$10
$11
$12
$13
Channel 0
1
2
3
Port A
0
0
1
1
0
0
1
1
0
0
1
0
0
0
0
0
$54
$50
Direction Register
Port Register A
Port B
0
0
1
1
0
0
1
1
0
0
1
0
0
0
1
1
$55
$51
Direction Register
Port Register B
Port C
0
0
1
1
0
0
1
1
0
0
1
0
1
1
0
0
$56
$52
Direction Register
Port Register C
Port D
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
0
$34
$30
Direction Regi ster
Port Register D
Port E
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
$44
$40
Direction Register
Port Register E
-785-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84COll AF
TMPZ84C011AF-6
TECHNICAL DATA
BLOCK DIAGRAM
XTALl
CLK
Ml
HALT
1 t
MSl
MS2
l\TMI
---
RESET
INT
11 1
-
XTAL2
CLK
HALT
CGC
CLK
HALT
Ml
NMI
-
Ml
NMI
t
r---
RESET
f--
mT
CPU
INT
ZC/TOO_2
-
--
CLK/
TRG 0-3
lEO
IEI
CLK
RESET
Ml
RD
-
RD WR IORQ DO~D7
AO~A15
/"
RD
WR
IORQ
IORQ
A
)
DO~D7
-
CE
CSO
CSl
CTC
V'-
rv-.:
0.,
(t
"0
0.,
~
decoder
---
I
Icontr8J'CUltl
A
~.J..
A
@
-"
'3::::J
en -
ro .,
ro
TEST
..
.,.......,c
o 0
., "
~8
B
C
0"
q-
II
.,ro
~
~
C
D
E
E
I/O Port
-786-
B
0
'0
~s
'1J
::I
'"
~
~
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C013AT
TMPZ84C013AT-6
TECHNICAL DATA
TOSHIBA
Pre I I m I na ry
TMPZ84C013AT
TMPZ84C013AT-6
( CMOS Z80 Microprocessor)
Communications Control
November
TOSHIBA
1986
CORPORATION
-787-
Processor
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPZ84C013AT/TMPZ84C013AT-6
(CMOS Z80 MICROPROCESSOR)
COMMUNICATIONS CONTROL PROCESSOR
GENERAL DESCRIPTION
TMPZ84C013AT is a low power CMOS Z80 8-blt microprocessor containing peripheral functions such
as on-chip clock generator (CGC), counter timer circuit (CTC), serial input/output controller (SIO) and
watch dog timer.
TMPZ84C013AT is designed for broad range of commumcation applications and has two independent
full-duplex channels with separate control and status lines for modems or other devices.
TMPZ84C013A IS fabricated with Toshiba's C2 MaS technology and molded in 84-pin PLCC package.
FEATURES
• Z80(") software compatible
• Low Power ConsumptIOn
• High speed operation: TMPZ84C013AT 4MHz
TMPZ84COl:lAT-6 6MHz
• Single Power Supply: 5V±10'X
• On-chip clock generator and controller
• On-chIp peripheral functions
(l) Four independent 8-bit counter/timer channels
(2) Two independent full-duplex serial channels
• Data rates of 0 to 800K bits/second in the xl clock mode with a 4MHz clock.
• Asynchronous protocols in 5, 6, 7 or 8 bits/character includmg variable stop bits and several
clock-rate multipliers; break generatIOn and detection; parity; overrun and framing error detection.
• Synchronous protocols: complete bit-or byte onented IBM Bisync, SDLC, HDLC, CCITT-X.25
and othen;. Automatic eRC generatIOn/checking, sync character and zero insertion/deletion,
abort generation/detectIOn, and flag insertIon.
• Watch dog timer
• On-chIp dynamIC memory refresh register (8-blt)
• Four OperatIOn' mode mcluding power save function.
RU:--.r
mode (Normal operatIOn)
IDLE] mode (CPU operatIOn is stopped, but only oscillator works)
IDLE2 mode (CPU operation IS stopped, but oscillator, counter/hmer and system clock output
operation is contmued.)
STOP mode (All operations are stopped)
• Three modes of high speed interrupt processmg: 8080 SImilar, non-Z80 penpheral device, and Z80
fallllly peripheral with or without daisy cham.
• Extended operating temperature: -40"C to 85"C
• Molded in R4-pin plastIC' leaded chIp carner.
Z8()'
IS
a trademark of Zliog Inc.
-788-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C013AT
TMPZ84C013AT-6
TECHNICAL DATA
The following is I/O Assignment and additional functions to the standard Z80 family devices.
1. I/O ASSIGNMENT
Address
I/O Name
:
:
CTC
(Counter
/timer)
:
:
SIO
(Serial I/O)
:
:
Watchdog
timer
:
Daisy chain
:
:
I/O Function
A7
A6
A5
A4
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
:
:
:
:
:
0
0
0
A2
Al
AD
:
:
:
:
:
:
:
:
0
()
()
0
1
0
0
0
0
:
:
:
:
:
()
1
1
1
1
1
1
1
1
0
0
0
0
:
0
:
0
0
A3
()
1
1
0
1
#10
#11
#12
#13
Channel 0
1
:
:
:
:
:
:
:
:
0
0
0
1
1
1
0
#18
#19
#lA
#1B
:
:
:
:
:
:
:
:
:
2
3
rhannel A
A
B
B
Data
Command
Data
Command
0
0
0
0
:
:
:
:
:
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
#FO
#F1
Watch dog Timer
Control
:
:
:
:
:
:
:
:
:
:
1
1
1
1
0
1
0
0
#F4
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
:
:
-789-
1
:
:
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C013AT
TMPZ84C013AT-6
TECHNICAL DATA
2. WATCHDOG TIMER
FUNCTION REGISTER #FO
(WRITE/READ)
2-1. Write Operation (Command Set)
D7
D5
D6
#FO
Timer Out
0:
1:
D3
D4
0:
1:
1 0:
1:
DO
When a command is loaded to
Watchdog Timer Function Register
(address #FO), D2, Dl and DO
must be as follows.
Note)*
0
Dl
,
MODE
Disable
Enable
0
D2
16 ms
64 ms
256 ms
1000ms
U
2 = 0
D1 = 1
DO = 1
Note)*
IDLE 1
IDLE 2
STOP
RUN
MS1
MS2
o
o
o
o
Note)*When RESET occurs, Timer Out will be set as 1000 ms.
Also cpu will be set in Run Mode and Watchdog Timer is enabled.
2-2. Read Operation (Status Read)
D7
#FO
,WDT Enable
D6
D5
D4
Timer Out
D3
MODE
D2
Dl
DO
J
When status is read out from address #FO, D1 and DO will be always high ("I") and the other (D7
through D2) will be in the status when a command has been loaded.
-190-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C013AT
TMPZ84C013AT-6
TECHNICAL DATA
2-3. Commands
1) D7 (Enabling the watchdog timer)
*) D7=1 : Watch Dog Enable
D7=0 : Watch Dog Disable
Note*) When RESET occurs, watch-dog timer is enabled (D7=1).
2) D6, D5 (Determining time period for prescaler)
D6
0
0
D5
0
0
Time
16 ms
64 ms
256 ms
1000 ms
at 4MHz
*)
Note*) When RESET occurs, prescaler will be set as 1000 ms.
3)
D4~D3
(Mode control for clock generator)
D4
D3
o
o
o
IDLE 1
IDLE2
STOP
RUN
1
o
*)
Note*) When RESET occurs, CPU will be set as RUN mode.
Internal operation
CTC
SIO
CLKOl;T
Status
S
0
S
0
S
S
S
0
S
0
S
0
Mode
IDLE 1
IDLE 2
STOP
RUN
O·
S· . .
CG
CPU
WD Timer
0
0
S
0
S
S
S
0
S
S
S
0
Operating (CLKOUT and eLKIN must be connected.)
Stop
-791-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C013AT
TMPZ84C013AT-6
TECHNICAL DATA
4) D1=1, DO=l
When a command is loaded to address #FO, Dl and DO must be high ("1").
Output Pulse width of WDTOUT.
a. When WDTOUT terminal is
connected
with
RESET
terminal.
b. When WDTOUT tenninal is
connected with other than
RESET terminal.
Low level pulse during five clock cycles will be
output.
Low level pulse will be output until software reset
or hardware reset is generated.
3. WATCHDOG TIMER FUNCTION REGISTER #Fl
(WRITE ONLY)
7
6
5
4
3
2
#Fl
(Explanation for commands)
1) "Bl" : Disable Watchdog Timer
D7 of IIO address #FO must be cleared and then #B1
must be loaded to I/O address #Fl.
2) "4E" : Clear Watchdog Timer
#4E Must be loaded to I/O address #Fl. This command is
independent of D7 of I/O address #FO.
3) "DB" : Updating content of D4 and D3 in IIO address #FO:
#DB must be loaded to IIO address #Fl before updating
D4 and D3.
-792-
o
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C013AT
TMPZ84C013AT-6
TECHNICAL DATA
4. INTERRUPT PRIORITY CONTROL REGISTER
#F4 (WRITE ONLY)
5
6
7
4
3
o
2
#F4
*
1
(Priority)
CTC - SIO
SIO -
o
CTC
*) After Reset
5. RFSH ADDRESS
A7' is added to refresh dynamic RAM in Ml cycle automatically.
Ml
RFSH ADDR
A07~AOO
X
RFSH ADDR
~ 7FH
X'-____--IX
RFSH ADDR
of' Standard Z80 cpu
PFSH
- - - -....
A7RF
RFSH ADDR
AOO~A07
'SOH'
'7FH'
of TMPZ84C013A
-193-
~ OOH
x:=
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C013AT
TMPZ84COl3AT-6
TECHNICAL DATA
PIN CONNECTION
84-PIN PLCC
a
C!l
.,.,
....
.... ....
too
<0
'" ..:co.... :;;:... ..:....
..: ..: ..: ..: ~ :;;: ..: ..:
.,.,
0
u
u
:>
0
~
is ~'"
co
~
...
~
~
.,.,
~
<0
~
t~
~
...<
u
A4
CLKlTRGl
A3
CLK/TRG2
A2
CLKlTRG3
Al
ZC/T03
AO
ZC/T02
MI
ZC/TOI
ZC/TOO
BUSREQ
CLKIN
WAIT
CLKOUT
WR
IORQ
TMPZ84C013AT
VSS
NC
XTAL2
XTALI
MREQ
VSS
NC
WDTOUT
INT
lEI
RFSH
NC
lEO
RESET
EV
BUSACK
NC
NMI
RD
A7RF
HALT
W/RDYB
W/RDYA
I II§ I~ I~ I~ ~ I~ I~ ~ I~
I~ ~ I~ I~ ~ Ig I~ I~ I§ ~
~
~
-794-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C015AF
TMPZ84C015AF-6
TECHNICAL DATA
TOSHIBA
Pre lim I na ry
TMPZ84C015AF
TMPZ84C015AF-6
( CMOS Z80 Microprocessor)
Communica~ions
Control
Nove.ber 1986
TOSHIBA
CORPORATION
-795-
Processor
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
TMPl84C015AF/TMPl84C015AF-6
(CMOS l80 MICROPROCESSOR)
COMMUNICATIONS CONTROL PROCESSOR
GENERAL DESCRIPTION
TMPZ84C015A is a low power CMOS Z80 8-bit microprocessor containing peripheral functions such
as on-chip clock generator (CGC), counter timer circuit (CTC), parallel input/output (PlO), serial
input/output controller (SIO) and watch dog timer.
TMPZ84C015A is designed for broad range of communication applications and has two independent fullduplex channels with separate control and status lines for modems or other devices.
TMPZ84C015A is fabricated with Toshiba's C2 MaS technology and molded in lOO-pin flat package.
FEATURES
• Z80® software compatible
• Low Power Consumption
• High speed operation: TMPZ84C015AF 4MHz
TMPZ84C015AF-6 6MHz
• Single Power Supply: 5V±lO%
• On-chip clock generator and controller
• On-chip peripheral functions
(1) Four independent 8-bit counter/timer channels
(2) Two independent full-duplex serial channels
• Data rates of 0 to 800K bits/second in the xl clock mode with a 4MHz clock.
• Asynchronous protocols in 5, 6, 7 or 8 bits/character including variable stop bits and several
clock-rate multipliers; break generation and detection; parity; overrun and framing error detection.
• Synchronous protocols: complete bit-or byte oriented IBM Bisync, SDLC, HDLC, CCITT-X.25
and others. Automatic CRC generation/checking, sync character and zero insertion/deletion,
abort generation/detection, and flag insertion.
(3) Two independent 8-bit input/output ports with handshake function.
• Watch dog timer
• On-chip dynamic memory refresh register (8-bit)
• Four Operation mode including power save function.
RUN
mode (Normal operation)
IDLEI mode (CPU operation is stopped, but only oscillator works)
IDLE2 mode (CPU operation is stopped, but oscillator, counter/timer and system clock output
operation is continued.)
STOP mode (All operations are stopped)
• Three modes of high speed interrupt processing: 8080 similar, non-Z80 peripheral device, and Z80
family peripheral with or without daisy chain.
• Extended operating temperature: -40'C to 85'C
• Molded in lOa-pin flat package.
Z80® is a trademark of Zilog Inc.
-796-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C015AF
TMPZ84C015AF-6
TECHNICAL DATA
The following is I/O Assignment and additional functions to the standard Z80 family devices.
1. I/O ASSIGNMENT
Address
I/O Name
I/O Function
A7
:
:
A6
A5
A4
A3
A2
Al
AO
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
#18
#19
#IA
#1B
~hannel A Data
SIO
(Serial I/O)
PIO
(Paraller I/O)
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
#IC
#1D
#1E
#IF
~hannel A
A
B
B
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
#FO
#Fl
Watch dog Timer
Control
:
:
:
:
:
:
:
:
:
:
1
1
1.
1
0
1
0
0
#F4
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
CTC
(Counter
/timer)
Watchdog
timer
:
Daisy chain
:
:
-797-
#10
#11
#12
#13
Channel 0
1
2
3
:
:
A Command
B Data
B Command
:
:
Data
Command
Data
Command
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C015AF
TMPZ84C015AF-6
TECHNICAL DATA
2. WATCHDOG TIMER
FUNCTION REGISTER #FO
(WRITE/READ)
2-1. Write Operation (Command Set)
D7
#FO
Timer Out
0:
1:
D3
D4
D5
D6
D1
D2
DO
MODE
•
Disable
Enable
When a command is loaded to
Watchdog Timer Function Register
(address #FO), D2, D1 and DO
must be as follows.
Note)*
0
0
0:
1:
0:
1:
16 ms
64 ms
256 ms
1000ms
a
2
=
0
D1 = 1
DO = 1
Note)*
IDLE 1
IDLE 2
STOP
RUN
MS1
MS2
o
o
o
1
o
Note)*
Note)*When RESET occurs, Timer Out will be set as 1000 ms.
Also cpu will be set in Run Mode and Watchdog Timer is enabled.
2-2. Read Operation (Status Read)
D7
#FO
WDT Enable
D6
D5
D4
Timer Out
D3
D2
D1
DO
MODE
When status is read out from address #FO, D1 and DO will be always high ("I") and the other (D7
through D2) will be in the status when a command has been loaded.
-798-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C015AF
TMPZ84C015AF-6
TECHNICAL DATA
2-3. Commands
1) D7 (Enabling the watchdog timer)
*) D7=1 : Watch Dog Enable
D7=0 : Watch Dog Disable
Note*) When RESET occurs, watch-dog timer is enabled (D7=1).
2) D6, D5 (Determining tIme period for prescaler)
D6
D5
o
o
o
Time
16 ms
64 ms
256 ms
1000 ms
1
o
at 4MHz
*)
Note*) When RESET occurs, prescaler will be set as 1000 ms.
3)
D4~D3
D4
0
0
(Mode control for clock generator)
D3
IDLE 1
IDLE2
STOP
RUN
0
1
0
*)
Note*) When RESET occurs, cpu will be set as RUN mode.
Internal operation
CG
CPU
PIO
WD Timer
CTC
SIO
CLKOUT
Status
0
0
S
0
S
S
S
0
S
S
S
0
S
S
S
0
S
0
S
0
S
S
S
0
S
0
S
0
Mode
IDLE 1
IDLE 2
STOP
RUN
O·
S·
Operating (CLKOUT and eLKIN must be connected.)
Stop
-799-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C015AF
TMPZ84C015AF-6
TECHNICAL DATA
4) D1=1, DO=l
When a command is loaded to address #FO, DI and DO must be high ("I").
Output Pulse width of WDTOUT.
a. When WDTOUT terminal is
connected
with
RESET
temlinal.
b. When ;-;W"'"'D"'T"'"O"-U'"""'T terminal is
connected with other than
RESET terminal.
Low level pulse during five clock cycles will be
output.
Low level pulse will be output until software reset
or hardware reset is generated.
3. WATCHDOG TIMER FUNCTION REGISTER #Fl
(WRITE ONLY)
7
6
5
4
3
2
o
#FI
(Explanation for commands)
1) "BI" : Disable Watchdog Timer
D7 of I/O address #FO must be cleared and then #BI
must be loaded to I/O address #Fl.
2) "4E"
#4E Must be loaded to I/O address #Fl. This
command is independent of D7 of I/O address #FO.
3) "DB"
Clear Watchdog TImer
Updating content of D4 and D3 in I/O address #FO:
#DB must be loaded to I/O address #FI before
updating D4 and D3.
-800-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C015AF
TMPZ84C015AF-6
TECHNICAL DATA
4. INTERRUPT PRIORITY CONTROL REGISTER
#F4 (WRITE ONLy)
7
5
6
4
3
o
2
#F4
(Priority)
* CTC - SlO -
PlO
0
0
0
SlO -
CTC -
PlO
0
CTC -
PlO -
SlO
0
PlO -
SlO -
CTC
0
0
Reset
0
PlO -
CTC -
SlO
0
SlO -
PlO -
CTC
0
0
5. RFSH ADDRESS
A7' is added to refresh dynamic RAM in Ml cycle automatically.
RFSH ADDR
A07 ~AOO
X
RFSH ADDR = 7FH
X'-____ X
--J
RFSH ADDR = OOH
of Standard Z80 cpu
A7RF
RFSH ADDR
AOO~A07
'7FH'
'80H'
of TMPZ84C013A
-801-
*)
After
C
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C015AF
TMPZ84C015AF-6
TECHNICAL DATA
PIN CONNECTION
A5
100
1
A3
AZ
Al
AO
RFSH
Ml
RESET
BUSREQ
WAIT
BUSACK
90
95
•
A4
85
80
ZC/T03
ZC/TOZ
5
75
10
70
vm
RO
IORQ
VSS
MREQ
HALT
TMPZ84C015AF
TMPZ84C015AF-6
15
65
TNT
ARDY
ASTB
PA7
PA6
PA5
PA4
PA3
PAZ
PAl
PAO
W7RDVA
CI_K/TRGI
CLK/TRGZ
CLK/TRG3
20
60
25
55
30
35
.0
Note) leT terminal must be open
-802-
4S
50
ZC/TOI
ZC/TOO
WOTOUT
lEI
lEO
AiRF
elKIN
CLKOUT
EV
XTAL2
XTAL1
VSS
NMI
BROY
BSTB
PB7
PB6
PB5
PB4
PB3
PB2
PSI
PBO
W/RDYB
SYNCS
TOSHIBA INTEGRATED CIRCUIT
TMPZ84CO 15AF
TMPZ84C015AF-6
TECHNICAL DATA
BLOCK DIAGRAM
:-:IA],I
ill HALT
'1',\1.2
CLKOUJ'
-wI
,I
----,-;:;:1
(L0-/.,
HALT
lIt
fLK['
I--+-.....o---+----j
HAL']'
ili .........-----+-----i \T1
MSJ
'\)\1(
1-+------+-----1 ~
III
CGC
11-----1
CLI(
HESEf-w>~~~~==l===~+_-~~~--~T~~HESEI
W
,,_
-\1\1'1'
CPU
iVf
j
L\T
CLK .....+-~
Z(',;T0 8
...-
IOHQ
A
ZUT0 3
CLI\/(rR{;4 _~
<:LK/TRG 3
lEI
lEO
eTC
"
;';P~--rf~
PA,
PH,
J ----.'
I
- - - - " MI HJ<:::-.ET
PH,
MT BRDY
-f-
HSTH
-t-
fLK
H----!;+-.~
~
cc PIO
C/D'"
(2)
~
CLK
_\
(2)
'---____k_/A--'-+-==JJ===!UJh
IEl
\\f{
HF."H
IJ,~D,
- - . \\IHOl'T
Watchdog 'rImer
&
FunctIOn RegJsters
7~"' i'"'""
Note (1) Control circuit
(2) Decoder
-803-
_
,"HE
-11"[
_[(''I'
TOSHIBA
INTEGRATED CIRCUIT
TMPZ84C015AF
TMPZ84C015AF-fi
TECHNICAL DATA
Unit: mm
0.65
NO.1
....
M
o
0
+1
+1
C'i
>Q
""
C'1
""
~
14.0±0.1
16.2±0.4
19.6±0.3
~
:;;:
C"l
e
\4
19.6+0.3
,....
0
+1
>Q
..-<
0
-804-
~
..-<
TOSHIBA INTEGRATED CIRCUIT
TMP82C54P
TMP82C54P-2
TECHNICAL DATA
TMP82C54P/TMP82C54P-2
PROGRAMMABLE INTERVAL TIMER
The TMP82C54P/P-2 is a programmable counter/timer fabricated in Silicon Gate CMOS technology
which provide low power operation and high performance. It is organized as three independent 16-bit
counters, with high clock rate input.
The TMP82C54P/P-2 has six operational modes. All modes of operation are software programmable.
The TMP82C54P/P-2 is a superset of TMP82C53P-2.
FEATURES
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Pin compatible with TMP82C53P-2
Three independent 16-bit counters
Counter latch command
Status Read-Back command
Six programmable Counter Modes
Count Binary or BCD
High speed
TMP82C54P-2
Clock inputs
TMP82C54P
Clock inputs
(8) Low power consumption
30mA Max. (at operation)
10JLA Max. (at power down)
(9) Operating temperature
-40 to 85"C
(10) Supply voltage
5V ± 10%
10MHz Max.
8MHz Max.
PIN CONNECTIONS (Top View)
D7
06
05
04
03
02
D1
00
CLKO
aUTO
GATE a
VSS(GNO)
~
2
3
4
5
WR
6
7
8
9
10
11
12
-805-
RO
CS
Al
AO
CLK 2
OUT 2
GATE 2
CLK 1
GATE 1
OUT 1
TOSHIBA INTEGRATED CIRCUIT
TMP82C54P
TMP82C54P-2
TECHNICAL DATA
BLOCK DIAGRAM
COUNTER #0
CLKO
GATEO
DATA BUS
BUFFER
D7-DO
aUTO
COUNTER #1
CLK!
GATEl
OUT!
HD
READ/
WRITE
WR
AO
CS
LOGIC
_ _ _.-11
CLK2
GATE 2
aUT2
PIN NAMES AND PIN DESCRIPTION
Pin Name
Input/Output
Function
D7 - DO
CLK 2 - CLK 0
GATE 2 - GATE 0
OUT 2 - OUT 0
Al - AO
RD
WR
CS
VCC, GND
I/O
Input
Input
Output
Input
Input
Input
Input
Power supply
Data bus
Counter clock inputs
Counter gate inputs
Counter outputs
Counter address
Read signal
Write signal
Chip select
+5V,OV
-806-
TO·' ·'BA
ABi:>L
SYMBOL
INTEGRATED rl orr '
1"1="
-.
TMP82C54P
TMP82C54P-2
'-INICAl
"" .AIMUM RATINGS
ITEMS
Vcc
VIN
VOUT
Supply Voltage
Input Voltage
Output Voltage
TEST CONDITION
With Respect
To GND.
RATING
UNIT
-0.5 to +7.0
-0.5 to Vcc+0.5
-0.5 to Vcc+0.5
V
V
V
250
PD
Power Dissipation
Tsol
Solder Temperature
260 (10 sec)
mW
·C
Tstg
Storage Temperature
-65 to +150
·C
Topr
Operating Temperature
-40 to +85
·C
DC CHARACTERISTICS
(Ta=-40 to +85°C, Vcc=5V+I0%,
Vss (GND)=OV)
MAX.
UNIT
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.2
Vcc+0.5
V
VOL
Output Low Voltage
IOL=2.2mA
0.45
V
VOH 1
Output High Voltage
IOH=-400rnA
2.4
VOH2
Output High Voltage
IOH=-100!LA
VCC-0.8
IlL
Input Leakage Current
SYMBOL
ITEMS
TEST CONDITONS
V
0.45 ::; VOUT ::;VCC
Output Leakage Current
ICC 1
Operating Supply Current
CLK=10MHz
VIH=VCC-0.2V
VIL=0.2V
ICC 2
Stand-by supply Current
CLK=DC
VIH=VCC-0.2V
VIL=0.2V
SYMBOL
V
OV::; VIN::; VCC
IOFL
AC CHARACTERISTICS
READ/WRITE
TYP.
MIN.
±10
!LA
±10
30
!LA
rnA
±10
!LA
3
(Ta=-40 to +85°C, VCC=5V±10%, Vss (GND)=OV)
ITEM
TMP82C54P
MIN.
MAX.
TMP82C54P-2
MIN.
MAX.
UNIT
tAR
Address Set-up Time (RD)
30
30
tSR
CS Set-up Time (RD)
0
0
ns
ns
tRA
Address Hold Time (RD)
20
20
ns
150
ns
tRR
RD Pulse Width
tRD
Valid Data (RD)
120
85
ns
tAD
Valid Data (Address)
220
185
ns
tDF
Data Floating (RD)
5
65
ns
tAW
Address Set-up Time (WR)
0
0
ns
tSW
CS Set-up Time (WR)
0
0
ns
tWA
Address Hold Time (WR)
0
0
ns
tWW
WR Pulse Width
150
95
ns
tDW
Data Set-up Time (WR)
120
95
ns
tWD
Data Hold Time (WR)
0
0
ns
tRY
Recovery Time
200
165
ns
-807-
95
85
5
TOSHIBA INTEGRATED CIRCUIT
TMP82C54P
TMP82C54P.2
TECHNICAL DATA
CLOCK/GATE
SYMBOL
TMP82C54P
ITEM
TMP82C54P-2
MIN.
MAX.
MIN.
MAX.
DC
100
DC
UNIT
tCLK
Clock Period
125
tPWH
CLK High Pulse Width
50
30
tPWL
CLK Low Pulse Width
50
30
tR
CLK Rise Time
25
25
ns
tF
CLK Fall Time
25
25
ns
tGW
GATE Width High
ns
ns
ns
50
50
ns
tGL
GATE Width LOW
50
50
ns
tGS
GATE Set-up Time (CLK)
50
40
ns
tGH
GATE Hold Time (CLK)
50
50
tOD
Output Delay From CLK
150
100
ns
tODG
OutPllt Delay From GATE
120
100
ns
tWC
Count Loading Set-up Time (CLK)
tWG
WR Set-up Time (GATE)
tWO
Output Delay Fro:n Command Write
tCL
CLK Set-up Time (Count Latch)
INPUT CAPACITANCE
SYMBOL
100
80
0
0
260
85
ns
ns
ns
240
68
ns
(Ta=25°C, Vcc=Vss (GND)=V)
ITEM
CIN
Input Capacitance
CIIO
Input/Output
Capacitance
TEST CONDITION
fc=1MHz
Unmeasured pins,
OV
MIN.
TYP.
MAX.
UNIT
10
pF
20
pF
AC TESTING INPUT WAVE FORM
x::> <::X",,___
2.4 _ _ _ _
0.45
ns
mST POmT
-808-
TOSHIBA INTEGRATED CIRCUIT
TMP82C54P
TMP82C54P-2
TECHNICAL DATA
READ TIMING
WRITE TIMING
LATCH COMMAND
eLK
1GH
GATE
----:-1---~
OUT
~I.~-----~O------~
CLOCK & GATE TIMING
-809-
*LAST BYTE WRITE
TOSHIBA INTEGRATED CIRCUIT
TMP82C54P
TMP82C54P-2
TECHNICAL DATA
PACKAGE OUTLINE
24 Pins PLASTIC DIP
Unit in mm
24
13
12
330 MAX
15.24±0.25
I
I
I
I.
"
II
...II
&I
1.4±0.15
0.25 +0.1
-0.05
Note) Lead pItch is 2.54mm and tolerance is ±0.25mm against theoretical center of each lead that is obtained
on the basis of No.1 and No. 24 leads.
-810-
TOSHIBA INTEGRATED CIRCUIT
TLCS-Z80 FAMILY
IN PLCC
TECHNICAL DATA
TLCS-Z80 CMOS FAMILY IN PLASTIC LEADED CHIP CARRIER.
TMPZ84COOAT/TMPZ84COOAT-6
TMPZ84CIOAT/TMPZ84CIOAT-6
TMPZ84C20AT/TMPZ84C20AT-6
TMPZ84C30AT/TMPZ84C30AT-6
TMPZ84C44AT/TMPZ84C44AT-6
These devices are CMOS Z-80 Family in 44 pin PLCC.
The function, A.C. and D.C. characteristics are same as in DIP or Flat Package.
REFERENCE TABLE
PART NUMBER
FUNCTION
CLOCK
REFERENCE
TMPZ84COOAT
Z80A CPU
4MHZ
TMPZ84COOAP
TMPZ84CIOAT
Z80A DMA
4MHZ
TMPZ84CIOAP
TMPZ84C20AT
Z80A PIO
4MHZ
TMPZ84C20AP
TMPZ84C30AP
TMPZ84C30AT
Z80A CTC
4MHZ
TMPZ84C44AT
Z80A 810
4MHZ
TMPZ84C43AF
TMPZ84COOAT -6
Z80B CPU
6MHZ
TMPZ84COOAP-6
TMPZ84CIOAT-6
Z80B DMA
6MHZ
TMPZ84CIOAP-6
TMPZ84C20AT-6
Z80B PIO
6MHZ
TMPZ84C20AP-6
TMPZ84C3OAT-6
Z80B CTC
6MHZ
TMPZ84C30AP-6
TMPZ84C44AT -6
Z80B SIO
6MHZ
TMPZ84C43AF -6
-811-
I
TMPZ84COOAT
TMPZ84COOAT-6
TMPZ84COOAT-8
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
PIN CONNECTION
44-Pin PLCC Package
(TLCS-Z80 CPU)
cg
CLK
7
D4
8
D3
9
to
"
,....
cv:l
I I I
"",....
~
..;<
,....
cv:l
~
~
,....
""~,....
,....
,....
0
~
~
,....
i$
---U'£i
-813-
0>
~
00
~
>-<
Q
!l::
U
Z
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C20T
TMPZ84C20AT-6
TECHNICAL DATA
PIN CONNECTION
44-Pin PLCC Package
(TLCS-Z80 PIO)
BfA
RD
PA7
PB7
PA6
PB6
PA5
PB5
PA4
NC
TMPZ84C20T
TMPZ84C20AT-6
PB4
PB3
VSS
PB2
PA3
PBl
PA2
PBO
PAl
VCC
PAO
CLK
-814-
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C30T
TMPZ84C30AT-6*
TECHNICAL DATA
PIN CONNECTION
44-Pin PLCC Package
(TLCS-Z80 CTC)
VSS
7
NC
ND
8
NC
RD
9
VCC
NC
ZC/TOO
CLK/TRGO
NC
TMPZ84C30T
TMPZ84C30AT-6
ZC/TOI
NC
ZC/T02
CLK/TRGI
IORQ
CLK/TRG2
NC
CLKlTRG3
NC
lEO
CSI
NC
.-<
C'1
~
.-<
U
Z IE-<
Z
H
U
Z
1>-<
fil
>-<
C'1
C'1
.-<
C'j
C'1
:;s UZ
""
C'1
l.Q
C'1
~ lfil
U
~
U
CD
C'1
~
C'1
I-I
I
E-<
fil
CI1
~
-815-
t:C'1
0
CI1
U
U
Z
TOSHIBA INTEGRATED CIRCUIT
TMPZ84C44T
TMPZ84C44AT-6
TECHNICAL DATA
PIN CONNECTION
44-Pin PLCC Package
('l'LC8-Z80 8IO)
'"
lC
~
M
G'I
M
~
~
M
~
""
~
M
~
0
~
B/i\"
lEI
7
lEO
8
C/O
Ml
VCC
W/RDYA
9
RD
VSS
W/RDYB
TMPZ84C44T
TMPZ84C44AT-6
SYNCA
RXDA
SYNCB
RXDB
RXCA
RXCB
TXCA
TXDA
TXCB
TXDB
NC
NC
rY:!
M
0>
0
M
M
G'I
C'l
I-I
G'I
C'l
M
C'l
~
C'l
lC
C'l
I-I I-I
-816-
'"
C'l
tC'l
rY:!
""
TOSHIBA INTEGRATED CIRCUIT
TLCS-Z80 FAMILY
IN PLCC
TECHNICAL DATA
PLASTIC LEADED CHIP CARRIER
6
44 Pin PLCC
1 -1
I 44
40-
o
'"
....
'"
17
_1
29
28
t : _ 1 7 . S 2 ± 0 . 1 2 _ _ _---.\
1"------16.6----""1
0.71 ±O.I
N
:g
fo----- 15.76--
-817-
o
o
+l
~
N
TOSHIBA INTEGRATED CIRCUIT
CMOS TLCS-48
IN PLCC
TECHNICAL DATA
TLCS-48 CMOS F AMILY IN PLASTIC LEADED CHIP CARRIER*
TMP80C48AT/TMP80C49AT/TMP80C50AT
TMP80C35AT/TMP80C39AT/TMP80C40AT
These devices are TLCS-48 Family in 44 pin PLCC.
The function, AC and DC characteristics are same as in DIP or Flat Package.
REFERENCE TABLE
PART NUMBER
ROM
RAM
CLOCK (Mhz)
REFERENCE
TMP80C48AT
1k X 8
64 X 8
11
TMP80C48AP
TMP80C49AT
2k X 8
128 X 8
11
TMP80C49AP
TMP80C50AT
4k X 8
256 X 8
11
TMP80C50AP
TMP80C35AT
External
64 X 8
11
TMP80C35AP
TMP80C39AT
External
128 X 8
11
TMP80C39AP
TMP80C40AT
External
256 X 8
11
TMP80C40AP
* See
Page 597 for description of NMOS TLCS-48 Devices in PLCC.
-818-
TOSHIBA INTEGRATED CIRCUIT
CMOS TLCS-48
IN PLCC
TECHNICAL DATA
PIN CONNECTIONS
E-<
C'l
,.....
to
'
:s
+I
~
ci N
-820-
TOSHIBA INTEGRATED CIRCUIT
TECHNICAL DATA
ERRATA SHEET
VOL. 1. CORRECTIONS
PAGE
HEADING/SECTION/
TABLE/FIG./ADDITION
LINE/
FIGURE
CORRECTION
NOW READS
3
Feature / 1.1
9
NMI
MMI
201
General Description
And Features
(15)
28 Pin
40 Pin
229
Fig. 2.2 (a) SIO Version
Fig. 2 & 3
SIO/1 & SIO/2
All Figures
SIO/O
274
Fig. 2.1 Pin Connection
Pin Numbering
Pin No. (16-9) should
read Top to Bottom
Currently reads (16-23)
Top to Bottom
277
Table 3.1, T6497
Operation Modes
Column ofMS
MS1
MS2
MS2
MS2
1
0
1
1
*
1
0
1
*
0
1
1
287
Additional Info.
-
265
AC Electrical
Characteristics
15
TdIEI (lEO r) 160 ns
Max not Min.
160 Min.
221
Page Heading
Top Comer
(right)
TMPZ84C30 ...
TMPZ84C40 ...
570
AC Electrical
Characteristics
Table
CL for any output is
100 pF
-821-
tWW
tWD
160
30
-
tWW
tWD
140
10
TOSHIBA INTEGRATED CIRCUIT
ERRATA SHEET (Continued)
TECHNICAL DATA
VOL. 1. CORRECTIONS
Page: --639-, -663-, -687-,
Incorrect
tRDl
Data Input Read Time
(RD)
375
ns
tRD2
Data Input Read Time
(PSEN)
4.5t·170
240
ns
tAD 1
Address Setup Time
(RD)
10.5t-220
730
ns
tAD2
Address Setup Time
(PSEN)
7.5t·200
460
ns
5.5t·120
6t·170
Correct
tRDl
Data Input Read Time
(RD)
tRD2
Data Input Read Time
(PSEN)
tAD 1
Address Setup Time
(RD)
tAD2
Address Setup Time
(PSEN)
-
4t-120
10t-170
-
7t-170
375
ns
240
ns
730
ns
460
ns
830
ns
580
ns
1530
ns
Page: -643-, -667-, -691-,
Incorrect
tRDl
Data Input Read Time
(RD)
tRD2
Data Input Read Time
(PSEN)
4.5t-170
6t-170
tAD 1
Address Setup Time
(RD)
10.5t-220
tAD 2
Address Setup Time
(PSEN)
7.5t-200
1050
ns
Data Input Read Time
(RD)
5.5t-120
800
ns
tRD2
Data Input Read Time
(PSEN)
4t-120
550
ns
tADl
Address Setup Time
(RD)
10t-170
1500
ns
tAD2
Address Setup Time
(PSEN)
1000
ns
-
Correct
tRDl
-822-
7t-170
-
MEMO
-823-
MEMO
-824-
CORPORATE OFFICE
2692 Dow Ave.
Tustin, CA 92680
(714) 832-6300
TLX: 314-138
WESTERN AREA
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FAX: (404) 493-4240
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13111 North Central Expy.
Suite 110
Dallas, TX 75243
(214) 480-0470
San Francisco Division
336 Los Caches Street
Milpitas, Callfomla 95035
Electronics Group
Claude Michael Group
FAX
(408) 942-4600
(408) 942-470Q."
(408) 262-12~4
TOSHIBA AMERICA. INC.
2692 Dow Ave.
Tustin, California 92680
Telephone: 714-832-6300
Telex: 314-138
The Information In thiS guide has been carefully checked and is believed to be reliable. however, no responsibility can be assumed lor inaccuracies that
may not have been caught . All Information In thiS guide IS subject to change without prior notice. Furthermore. Toshiba cannot assume responsibility
for the use of any license under the patent rights of Toshiba or any third parties.
1·87 PRINTED IN U.S.A.
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