1988_ATT_Microelectronic_Products_Selection_Guide 1988 ATT Microelectronic Products Selection Guide
User Manual: 1988_ATT_Microelectronic_Products_Selection_Guide
Open the PDF directly: View PDF 
.
Page Count: 302
| Download | |
| Open PDF In Browser | View PDF |
Spring 1988
Microelectronic Products
Selection Guide
Section
1
How To Use This Guide
10
11
12
13
14
15
16
17
18
Product Information
Analog Integrated Circuits
Application Specific Integrated Circuits
Capacitors
Communication Integrated Circuits
Digital Bipolar Integrated Circuits
Digital Signal Processors
Fiber Optics
Frequency Control Products
(Oscillators and Timing Recovery Units)
Gallium Arsenide Integrated Circuits
Hybrid Integrated Circuits
Microprocessors and Peripherals
Opto-Isolators
Power Products
Printed Circuit Boards
Single Board Computers
Transformers and Inductors
Wire and Cable (Electronic)
19
'J\fpical Applications
20
Customer Support
Domestic Sales Offices
Worldwide Design Centers and
Manufacturing Plants
Technical Literature
21
Product Index
2
3
4
5
6
7
8
9
A Word About Trademarks
The following AT&T trademarks are used in the Product Selection Guide:
ASTROTEC®, 5ESS®, FASTECH®, LGXTM, LlGHTPACK®, LlNEAGE®, ODL ®, SLC®,
ST®, UN/TpM, UNlX®, WE®,
The following trademarks, owned by entities other than AT&T, are also used in the
Product Selection Guide: C EXECUTlVE®, CSXTM, ENP-10™, HALAR®, MS-DOS®,
TEFLON®, VAX®, VMS®,
1
How To Use This Guide
AT&T Microelectronics is a major manufacturer of components
and electronic systems. The entire family of integrated products is designed by AT&T Bell Laboratories and supported by
a broad-based network of field applications specialists and
sales engineers. As a world-class supplier, we dedicate these
support resources to providing you with total solutions... not just
components.
We invite you to review our components in the product information section. The product families are arranged alphabetically, in subsections, as outlined in the Table of Contents on
the previous page. Each product subsection also carries a
product family Table of Contents, identifying those products
that were not included in the previous edition.
The Typical Applications Section offers examples of suggested
uses for specific AT&T components within selected electronic
applications.
The Customer Support Section shows the locations of our
domestic sales offices, design centers, and manufacturing
plants, and contains literature ordering information.
The last section carries an alphabetized list of all products
included in the Selection Guide.
In addition to the information offered in the Guide, complete
technical specifications are available upon request. Contact the
sales office nearest you, return one of the inquiry cards found
in the back of the guide, or call our toll-free number:
1-800-372-2447.
We invite you to learn more about our components ...... and
discover how partners in technology become partners in
success.
Spring 1988
1·1
Product Information
2
Analog ICs
Page
More than 600 devices
comprise AT&T's analog
integrated circuit family,
including a variety of
voltage references, relay
drivers, solid-state relays,
analog switches, line
drivers and receivers,
special-purpose amplifiers, telephone circuits,
and linear arrays. The
devices include, in many
cases, an internal fullwave bridge rectifier for
surge protection. On
many circuits, this provides lightning protection
to 1500 V.
The new line of AT&T
semi-custom linear arrays
are the cost-effective
alternative to custom
design. The arrays can
tolerate working voltages
up to 90 V with blocking voltages as high as
1000 V. They have the
sophistication to perform
a host of electronic functions, while interfacing
with a wide variety of
circuits.
For additional Infor·
matlon contact your
nearest sales office
or call:
Analog Switch
High-Speed Dual Analog Switch -
LB1017AC
2·3
Battery Feeds
Battery Feed Battery Feed -
LB1011AB
LB1012AD
2·4
2·5
Communication Devices
Quad Line Driver - AM26LS31CC
Quad Line Receivers - AM26LS32CC, AM26LS33CC
Quad Bus Transceiver - LB1025AC
2·6
2·7
2·8
High·Voltage Gate Arrays
Octal High-Voltage N-Channel - AN0130NA
Octal High-Voltage P-Channel - AP0130NA
2·9
2·10
High.Voltage Level ","anslator
*
8-Channel Logic to High-Voltage Level Translator -
HT0130P
2·11
High.Voltage Solid·State Relays
SPST High-Voltage - LH1056-Type
DPST High-Voltage - LH1061AB
SPST High-Voltage (High mA) - LH1085AT
2·12
2·13
2·14
Operational Amplifiers
*
*
1·800·372·2447.
Dual Programmable Micropower Op Amp - LB1035AC
High-Voltage Dual Op Amp - LB1013AD
High-Voltage Dual Op Amp - LB1108AType
Programmable Medium-Power Output Op Amp LB1032BC
Programmable Wideband Op Amp - LB1034AC
Single General-Purpose Medium-Power Output Op Amp LB1032AC
2·15
2·16
2·17
2·18
2·19
2·21
Power and Control Devices
*
*
Power Controller - LB1019AB
Pulse-Width Modulator - LB1048-Type
Regulation Control Circuit LBR Family
Voltage Reference Family - LB108Hype
2·22
2·24
2·25
2·26
(Continued on next page)
• Did not appear in the previous edition of the Product Selection Guide.
Spring 1988
2·1
Analog ICs
(Continued)
Page
Protection
*
Octal Line Protector - LB1010AD
High-Voltage Isolation Amplifier - LB1109AB
Integrated Secondary Protectors - LH1150:fype
2-27
2-28
2-29
*
60-Volt Dual Relay Driver - LS1014AB
Quad Negative-Voltage Relay Driver - LS1098AAF
2-30
2-31
Semi·Custom Linear Arrays
2-32
Relay Drivers
Speakerphone Device Set
Voice Path Switch - LB1020AF
Power Conditioner/Amplifier - LB1021AD
2-33
2-34
Telephony Devices
Electret Preamplifier - LB1027AB
Full-Feature Tone Ringer/Ringing Detector - LB1004AC
General-Purpose Tone Ringers - LB1005:fype
Ringing Detector - LB1006AB
Keypad-Controlled, Touch:fone Single-Chip Telephone IC LB1008AE
Microprocessor Controlled, Single-Chip Telephone IC LB1009AE
Telephone Interface Circuit - LH1028BB
Universal Voice-Signal Conditioner - LB1068AW
Voice Frequency Level Expander - LB1026AB
Loop Termination Switch with Surge Protection - LB1060AB
* Did not appear in the previous edition of the Product Selection Guide.
2-2
Spring 1988
2-35
2-36
2-38
2-40
2-41
2-42
2-43
2·44
2-46
2-47
Analog ICs
Analog Switches
High·Speed Dual Analog Switch LB1017AC
Description
The LB1017AC High-Speed Dual Analog Switch integrated circuit contains two
channels in one package. Each channel consists of a driver circuit controlling a
SPST sWitch. The drivers interface with TTL-logic input signals for applications
such as multiplexing, commutating, and D/A converter applications. These drivers
enable a low-level input (0.8 to 2.0 volts) to control the ON/OFF condition of each
switch. In the ON-state, each switch will conduct equally well in either direction. In
the OFF-state, each switch will block voltages up to ±5 volts. Positive Logic 1 will
turn each switch ON and Logic 0 will turn each switch OFF.
Features
• Low ON resistance (9 to 15 ohms) for signals up to ±4 V and 100 kHz
• Characterized for audio range; capable of handling small-signal analog inputs to
the M Hz range
• Switching times
< 50 ns
• ±4 volt common-mode range
• Low injected charge «50 pC)
• High open-switch isolation (-70 dB) at 1.0 kHz
• Low leakage current «
100 nA) in the OFF-state
• Low crosstalk (-50 dB) between switches
• Low harmonic distortion
• Switches have sink/source current capabilities
Functional Diagram
• Low feedthrough capacitance «
16
2
INA {
3
6
INB{
7
8
D--u_--~
14
9
D-----u-~
11
> 16 mA
0.3 pF)
SWA1
SWA2
SWB1
SWB2
(Refer to Section 19 for typical applications of this product.)
LOGIC
SWITCH
1 1 1
ON
0
0
0
0
1
1
1
o0
0
1
1
0
0
1
1
0
1
0
1
0
Spring 1988
OFF
2·3
Analog ICs
Battery Feeds
Battery Feed -
LB1011AB
Description
The LB1011AB integrated circuit is an electronic battery feed circuit which supplies
dc currents to a telephone line with minimal loading on the ac signals. The device
is integrated as two complementary chips to supply dc currents of both negative
and positive polarities to either unbalanced or balanced lines. In the balanced-line
application, this device helps suppress undesirable common-mode signals.
Features
• Basic battery feed functions at a low cost
• High ac impedance characteristics for balanced-line, differential-mode, and voiceband signals
• Full internal lightning surge protection
• dc voltage drops can be adjusted to accommodate different peak signal levels
Functional Diagram
• 8-pin plastic DIP
RP1
v+
v..
OF LB1011AB
-
r---I OUTPUT
I STAGE
I
TAPP
RTP
I
I
IL
CCP
____
100 K
POSITIVE
LINE FEED
RS1
1K
P
R
0
T
E
C
T
I
DC
VOLTAGE
DROP
~
-
TIP
CC1
S
U
R
G
E
-
-~
~II
- ;------J
RING
100 K
CCN
RTN
TAPN
V2 OF LB1011AB
RN1
V-
2·4
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Analog les
Battery Feeds
Battery Feed -
LB1012AD
Description
The LB1012AD integrated circuit is an electronic battery feed circuit which supplies a controlled dc current to the Tip-Ring pair of a telephone system. The battery feed circuitry presents a low impedance to dc current, while presenting a
high impedance to the ac signal. The LB1012AD device contains input and output
ports for voice-frequency signals and a hook status output signal.
Features
• Loop lengths up to 1300 ohms can be driven
• Common-mode rejection (longitudinal balance) better than 60 dB
• Well-controlled receive and transmit gains
• TTL-compatible "Hook Status" indicator
• Proper line matching can be provided with a 50:1 scaled network; 30 kO provide
a 600 0 termination
Functional Diagram
• 18-pin plastic power DIP
01,1'
lAC IN
EXTERNAL
SECONDARY PROTECTION
AND
STABILIZATION NETWORK
r--- --- ------l
TO I
I
INTERNAL
100 kfl
1-____-=-c=++-_T6S~I__,
I
I
I
20 pF
I
VTR/2
100 "
20 pF
I
I
CSl
001,1'
RSl
100"
I
I
,FJ
01
I
RP2
10 kll
RS:
F~~~~--+-+-~~I--+---~
VAEF
I
I
100 kn
HOOK
STATUS
:
I
TIP
RPl
I
I
I
I
TO
I
TELL"6~~NE I
I
I
~:;PF
:
RP3
I
10."
I
RD
~
DENOTES SYSTEM
GROUND
RP4
RING
I
I
I
I
IL _ _ _
100"
_ _ _ _ _ _ _ _ _ .JI
DENOTES SIGNAL
GROUND
J
I
I
NOTE
I
v-
L------------4----------~~~~~----------~
(Refer to Section 19 for typical applications of this product.)
______~~----.-48V
Spring 1988
2-5
Analog ICs
Communication Devices
Quad Line Driver -
AM26LS31CC
Description
This device consists of four independent line drivers with a common
ENABLE, ENABLE control. It provides high-speed differential drive to transmission
lines having an impedance of at least 100 ohms. Each of the four drivers has
complementary 3-state outputs. This device requires only a 5 volt supply (±10%)
for operation.
Features
• Direct replacement for industry-standard differential line drivers
• Meets EIA RS-422A requirements
• Input/output propagation delay is less than 20 ns
• ENABLE, ENABLE to output delay is less than 40 ns
• Reduced power supply current (less than 40 mAl when device is disabled
• Output skew (time delay between direct output and inverse output) typically 2 ns
• TTL-compatible ENABLE, ENABLE inputs
Functional Diagram
• 16-pin plastic DIP
"O-----------------+-------------INVERSE
DRIVER
OUTPUT
---------1
INPUT
r~---------------+-------------DIRECT
OUTPUT
"O-----------------+---------------INVERSE
OUTPUT
DRIVER - - - - - - - - - i
INPUT
r-----------------t------------- DIRECT
OUTPUT
ENABlE------------------~
ENABlE-------------------o
'O------------------t---------------INVERSE
DRIVER
---------1
INPUT
OUTPUT
r-----------------/-------------DIRECT
OUTPUT
"O--------------------------------INVERSE
DRIVER
---------1
INPUT
OUTPUT
r~-----------------------------DIRECT
OUTPUT
2-6
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Analog les
Communication Devices
Quad Line Receivers AM26LS32CC, AM26LS33CC
Description
The AM26LS32CC and AM26LS33CC integrated circuits are general-purpose, line
receiver circuits for use in either balanced or unbalanced data transmission
systems. A TTl:compatible ENABLE, ENABLE is common to all four receivers in
each package. The ENABLE, ENABLE allows the output to be put into a
high-impedance state for output busing.
Features
• Direct replacement for industry-standard line receivers
• Meets EIA RS-422A/423A specifications
• Four independent receivers with common strobe TTL-compatible input
• Electrostatic discharge protection on receiver inputs
• Requires only a single 5 V (± 10%) power supply
• Input sensitivity: ±200 mV (AM26LS32CC),
±500 mV (AM26LS33CC)
• Guaranteed minimum input hysteresis: 15 mV (AM26LS32CC),
30 mV (AM26LS33CC)
• Internal fail-safe forces the output high for an open input condition
• Typical propagation delay of 17 ns
Simplified Diagram
• 16-pin plastic DIP, with industry-standard pinout
ENABLE
RI
COMPARATOR
R2
+INPUT O - -.........---'\Nv------1~...--__1
PULL-UP
TRANSISTOR
R3
INTERNAL
VAEF
OUT
R4
RS
-INPUT O--~---'\Nv------------__+__+_--20 dB
• Bias programmable for Wide adjustment of bandwidth and supply current
• Typical minimum unity-gain frequency of 1.0 MHz
• Operation to +85°C
(Refer to Section 19 for typical applications of this product.)
Spring 1988
2·19
2·20
Spring 1988
Analog ICs
Operational Amplifiers
Single General-Purpose
Medium-Power Output Op Amp LB1032AC
Description
The LB1032AC device is an internally compensated, medium-power operational
amplifier Maximum supply voltage is ±70 V and output current IS ±77 mA Into a
45 (2 load. Optional bias control, external compensation, offset nulling, and a lowcurrent, higher frequency output are also provided.
Features
• 80 mA minimum output current capability
• Guaranteed minimum unity-gain frequency of 2.5 MHz
• Offset voltage null capability
• 1.5 VI p,s typical slew rate
• Optional internal or external compensation
• 16-pin plastic DIP
• Supply voltage range ±3.0 to ± 7.0 V
Pin Connections and
Functional Diagram
• Differential-mode voltage range: ±6.5 V
+vs
OPTIONAL BIAS CURRENT
f--~+I----,
HIGH CURRENT OUTPUT
2
LOW CURRENT OUTPUT
31---":>""'::
OPTIONAL BIAS CURRENT
14
SUPPLY CURRENT CONTROL
+IN
OFFSET NULL
5
EXTERNAL COMPENSATION CAPACITOR
OFFSET NULL
6
-IN
GAIN RESISTOR
7
GAIN RESISTOR
8
COMPENSATION
9
INTERNAL COMPENSATION CAPACITOR
(Refer to Section 19 for typical applications of this product.)
Spring 1988
2·21
Analog ICs
Power and Control Devices
Power Controller -
LB1019AB
Description
The LB1019AB Power Controller is used to switch the unregulated -48 volt supply
to multi button telephone station sets or other loads. It is digitally controlled and
has a 300 mA capability. This device can drive higher instantaneous currents and
has a built-in thermal shutdown to prevent destruction in the event of a fault
condition.
This device provides logic output states for three different load conditions:
Load currents $ 3 mA - open circuit.
.
Load currents ;;:::300 mA - overload.
Load currents ;;:::3 mA and $300 mA - normal load conditions.
The power controller will not provide current to the load if the V- supply voltage
is more positive than a nominal -30 volts. This prevents hazardous high-current
conditions from occurring in a switching regulator located In the telephone station
sets.
Features
• Digital controlled power switch
• Power can be turned on and off using the ON input
• Current limiting during a fault condition
• Thermal shutdown during extended fault conditions
• Indicates quiescent current flow to confirm output-to-Ioad continuity
• EO input allows smooth power-up sequence
• Indicates overcurrent condition when the load current exceeds 300 mA (typically)
• 8-pin plastic DIP
• Inquire about the availability of devices with overcurrent threshold settings of
200 mA, 400 mA, and 600 mA (±15%)
2·22
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Analog ICs
Power and Control Devices
LB1019AB Power
Controller Functional
Diagram
V+
I
IIREFERENCE
VOLTAGE CURRENT
GENERATION
EO
l •
-33 V/-22 V
(NOMINAL)
POWER"UP
,
~
I
I CO;~ROL I
I
,h
1
I
r-'L
0
A
D
,
ION/OFF I
CONTROL
'--
t
~
THERMAL SENSE
SHUTDOWN
I
CURRENT
MONITOR - - - 0 CUR MON
OUTPUT AND
MODE SELECl
MODE
v--'
CURRENT
LIMITING
K
~
">
~
OUT
f
1(
i
rr"--
300 rnA
OVERCURRENT
QUIESCENT
CURRENT
INDICATOR
I
V-
Spring 1988
2·23
Analog les
Power and Control Devices
Pulse·Width Modulator
LB1048·~pe
-
Description
The LB1048AAJ and LB1048AG Pulse-Width Modulators are silicon integrated circuits offering a single-ended output which can either sink or source currents up to
200 mA. Each device is suitable for performing the basic pUlse-width modulation
function in switching power supplies. The logic section provides noise immunity by
having an edge-triggered input which allows only one transition per clock cycle.
This device includes a 1.25 V temperature-compensated reference capable of
supplying up to 1 mA to external circuitry It also features circuitry for current
limiting, maximum duty-cycle limiting, shutdown and adaptive startup. An internal
triangular wave shape oscillator (providing equal rise and fall times) is controlled
by external components.
Features
Functional Diagram
• Single source/sink output: ±200 mA
• Double pulse suppression
• Frequency adjustable to 500 kHz
• Current limit control of external FET
• Noise-immunity logic
• QUiescent current less than 7.0 mA
• External oscillator synchronization
• Maximum duty cycle control
• Adaptive startup and shutdown control
• FET driver
INPUT
VOLTAGE
( >12V)
MAXSET
SELECT
VCCO
LB1048
V8G
SHUTON
2-24
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Analog les
Power and Control Devices
Regulation Control Circuit LBR
Family
Description
The Regulation Control Circuit LBR Family consists of integrated circuits which
provide three main functions in the same package; a voltage regulator, a precIsion
1.25 V reference, and a high-speed comparator Each device accepts an
unregulated dc supply voltage ranging from 4 to 26 V and provides two fixed outputs: a 1.25 V reference voltage, common to each device code in this family; and
a customer-specified regulation voltage, ranging from 2 to 24 V, fixed at time of
manufacture. These devices are available in 8-pin (fixed configuration, see Functional Diagram) and 16-pin (flexible configuration) packages.
Features
Voltage Regulator
• Fixed values between 2 and 24 V (±1%)
• Low temperature fluctuation
High-Speed Comparator
• Propagation delay <150 ns
• Output loading to 10 mA maximum
Precision Low-Voltage Reference
• 1.25 V (±1%) from 4- to 26-volt supply
• 4-volt minimum V+ operation (-40 to +100"C)
• Capacitive operation to 100 pF maximum
Functional Diagram
• Current loading to :::;10 mA
COMPo
IN(_)o---------------------~
:>-----0 COMPo OUT
............;1:;:.2:;:.5..:.V__________0
REF
V+o-__~VOUAGE~----~~
REF.
OAOUT
I
I
I
I (OPTIONAL
I CONNECTION)
RFB1
GNDo---~----~--~~--.
RFB2
I
I
I
FEEDBACKo-------------------4-----~~~----_o SENSE+
(Refer to Section 19 for typical applications of this product.)
Spring 1988
2·25
Analog ICs
Power and Control Devices
Voltage Reference Family LB1081·~pe
Description
The LB108Hype Voltage References represent a family of low-power control
devices, each designed to provide a specific output within the range of 4 to 8
volts. Offering multipurpose applications, all circuits are characterized by low
noise, medium current, and a predetermined output voltage. As a special design
consideration, the reference voltage is set dUring manufacture by applying a
voltage waveform to fusible, on-Chip resistors. When used with the appropriate external components, the devices function as negative voltage regulators and highoutput voltage regulators, and are suitable in environments requiring high current
with low-impedance capabilities. Additionally, they are ideal for use in instrumentation equipment, measurement devices, and monitoring systems.
Features
• Five preset output options.
4 V (LB1081AC)
5 V (LB1081BC)
6 V (LB1081CC)
7 V (LB1081DC)
8 V (LB1081EC, LB1081FC)
• Factory-programmable reference voltages
• Negative-voltage and high-voltage capabilities
• Medium-current and high-current capabilities
• Output current limiting, 30 mA
Functional Diagram
• Packaged in a 16-pin plastic DIP
Vee
30 !l
~-'VVv----vOUT
~~--~~----oFB
Code
RFB2*
TC VOUT**
LB1081AC
5.5 kf2
±.0075%/"C
LB1081BC
7.5 kf2
±.0075%/oC
LB1081CC
9.5 kf2
±.0075%/oC
LB1081DC
11.5 kf2
±.0075%/"C
LB1081EC
13.5 kf2
±.0075%/"C
LB1081FCt
13.5 kf2
± .OO45%/"C
* RFB1 = 2.48 kO and may be trimmed via meltback path to achieve
Note: The value of RFB2 and corresponding codes are shown
In the table.
2·26
Spring 1988
precIsion output Voltage.
** TC VOUT denotes temperature coefficient of output voltage
t
The LB1081EC and FC are electrically similar except for the noted
difference In TC VOUT.
(Refer to Section 19 for typical applications of this product.)
Analog ICs
Protection
Octal Line Protector -
LB1010AD
Description
The LB1010AD integrated circuit IS a bidirectional overvoltage/overcurrent limiting
device that protects up to eight digital lines. This circuit contains 16 on-chip fuses,
8 voltage/current clamps, and a clamp threshold reference which tracks the power
supply. In operation, transient on-line surges (within specified limits) are clamped
to a safe level. However, if an extraordinarily high-current fault is detected (on the
order of 1 amp), an on-chip fusing component will open, protecting your electronic CIrcuits.
Features
• Bidirectional clamping
• Clamp threshold tracks supply voltage to 7.0 V
• Protects 8 lines
Functional Diagram
• 18-pin plastic DIP
V+
1-----------,--I
I
NEGATIVE
CLAMP
------,
I
I
I
I
I
I
I
I
I
i I'
I
INPUT/OUTPUT A
I
I
I
I
I
I
I
CLAMP
THRESHOLD
REFERENCE
INTERNAL
FUSE
I
I
I
THIS SECTION IS
ONLY ONE OF EIGHT IDENTICAL
CIRCUITS SHOWN.
I
I
:
I
I
I
I
COMMON
CIRCUITRY
L __________ L ___ ____ ---.l
(Refer to Section 19 for typical applications of this product.)
Spring 1988
2·27
Analog ICs
Protection
High-Voltage Isolation Amplifier LB1109AB
Description
The LB1109AB High-Voltage Isolation Amplifier integrated circuit IS a linear, twoport device designed to pass information across an isolated boundary. This
device can transmit signals of up to 1.0 MHz bandwidth with less than one percent signal error at unity gain, while isolating Input-to-output differential voltages of
up to 1000 volts. The device is packaged in an 8-pin plastic DIP
This device can replace opto-Isolators in many applications. The advantage of the
LB1109AB High-Voltage Isolation Amplifier is that it is a stand-alone unit (i.e., it is
not dependent upon ancillary input and output circuitry). In addition, It has good
temperature coefficients and well-controlled transfer characteristics.
Features
• 1.0 MHz bandwidth
• Emitter follower output stage (1.5 mA source, 100 pA sink)
• Temperature coefficient < 200 ppm/"C
• Input currents :;;1.3 mA @ 5.0 V
• Signal-to-noise ratio
> 60 dB
• 1000 volt transient input/output isolation
• Standby supply current <3.0 mA
• Less than 0.5% signal error with a dvldt of 100 VIps
Functional Diagram
• Signal error at set point is less than ±1.0%
Vlpos
VOpos
INPUT
OUTPUT
COM-IN
COM-OUT
2·28
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Analog ICs
Protection
Integrated Secondary
Protectors - LH1150-Type
Description
The LH1150-Type Integrated Secondary Protectors (ISP) are two-wire overvoltage
devices for secondary protection of electronic switch line units. Each circuit contains four thYristor devices with associated threshold sensing. The fabrication
technology utilizes a high-voltage, bipolar, DMOS, dielectrically Isolated, silicon, integrated circuit chip, available in a rugged plastic package. In many applications
this device is interchangeable with Texas Instruments voltage suppressor part
TISP229A and TECCOR Electronics surge protector part P101.
Features
• Bidirectional overvoltage protection
• Crowbars surge waves and power cross faults
• Internal voltage trim capability to meet threshold voltage requirements
• Symmetrical pinout
Functional Diagram
• No heat sink required
TIPo----t__----------_-_-------,
HV
HV
HV
HV
HV
HV
RING
HV
0-----------------+-------'
(Refer to Section 19 for typical applications of this product.)
Spring 1988
2·29
Analog ICs
Relay Drivers
60-Yolt Dual Relay Driver LS1014AB
Description
The LS1014AB integrated circuit consists of two independent relay drivers and is
intended for use in high-voltage relay applications. Each relay circuit is designed
to operate from positive TTL logic.
Features
• Flyback protection diode at each output for optional connection
• Each output can handle any load from 2 to 30 mA
• Designed to operate from 5 V (V+) and -48 V (V-)
• Tested for 60 V operation
Basic Schematic
• 8-pin plastic DIP
v+
R2
,..----..--...---------0
GNO
500 Il
R1
50 kll
02
INPUT Q - - - - - - - - < - - i
02
.---4>---0 OUTPUT
01
R6
~-4----~~------OV-
NOTE: This device consists of two identical drivers. Only one driver
schematic is shown.
2-30
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Analog ICs
Relay Drivers
Quad Negative-Voltage
Relay Driver - LS1098AAF
Description
The LS1088AAF integrated circuit consists of four independent 60-volt relay drivers
designed to operate over wide ranges of supply voltage, common-mode voltage,
and ambient temperature, with 50 mA source capability. These drivers are
Intended for switching the ground side of loads which are directly connected to a
negative supply, such as in telephone relay systems.
NOise and IR drop between logic ground and negative supply ground are problems which must always be considered in telephone relay systems. Therefore,
these relay drivers are designed to operate with a high common-mode range.
These drivers are compatible with TTL, LS, and CMOS logic, since the differential
input current requirements are low. Differential inputs permit either inverting or
noninvertlng operation. The driver outputs Incorporate transient suppression clamp
networks which eliminate the need for external suppression circuitry when used in
applications for switching inductive loads. A fail-safe feature is incorporated to
ensure that, if the VON input or both inputs (VON and VOFF) are open, the driver
will be off.
Features
• 50 mA source capability (each driver)
• Low propagation delays (s; 10 p.s)
• TTL, LS, or CMOS compatible inputs
• Fail-safe disconnect protection
• High input common-mode voltage range (±20 V)
• Negative supply operating voltage (-10 V to -60 V)
Functional Diagram
• Built-in output clamp diodes
GND 01------
VON(A)~
VOFF(A)~
VON(B)~
VOFF(B)~
VON(C)~
VOFF(C)~
VON(D)~
VOFF(D)~
VSN
0-------
(Refer to Section 19 for typical applications of this product.)
Spring 1988
2·31
Analog ICs
Semi-Custom Linear Arrays
Semi·Custom Linear Arrays
Description
AT&T's family of CBIC linear arrays has been designed to fulfill a wide range of
applications using a complementary vertical NPN and PNP transistor technology.
Our linear arrays satisfy Circuit design requirements ranging from dc to VHF, and
5 to 90 volt applications. In addition, some linear arrays combine analog and
digital circuitry on the same chip. Design kits are available that consist of instruction manuals, building block parts kits, macrocell libraries, and grid plot arrays.
Features
• Two-level metal interconnect
• All 1/0 ESD protected
• Low development costs
• Quick design turnaround, typically six to eight weeks from design approval
Design
Manufacturing
Sequence
• Design proprietorship
• Available in chip form and a variety of JEDEC standard packages
CUSTOMER RESPONSIBILITY (SEE NOTE)
,-------------------,
I
I
I
I
I
DESIGN
CIRCUIT
L --
---
SIMULATE
~
INTERCONNECT
DEVICES
I
I
~
I
PROVIDE
MASKS
:;;4 LEVELS
-----.
METALLIZE
WAFERS
~
PACKAGE
CHIPS
I
------
------
_ _ -.-3
I
I
:L
________
.~OPTIONAL
DESIGN
GUIDE
~
MODEL
LIBRARY
LAYOUT
PLOT/CAD
DELIVER TO
CUSTOMER
DC
VOLTAGE
TEST
~
---l
PATH
DELIVER TO
CUSTOMER
NOTE: AT&T will provide these services if requested
by customer at an additional charge.
Product Matrix
Series
Technology
ALA201/202
ALA300/301
ALA400/401
2-32
Spring 1988
CBIC
CBIC
CBIC
Characteristics
UHF; complementary vertical NPN and PNP transistors
90 V; complementary vertical NPN and PNP transistors
33 V; complementary vertical NPN and PNP transistors
(Refer to Section 19 for typical applications of this product_)
Analog les
Speakerphone Device Set
Voice Path Switch -
LB1020AF
Description
These speakerphone ICs are designed specifically for PBX and other office applications. The voice path sWitch, combined with the LB1021AD Power Conditioner/Amplifier, provides superior vOice quality and low nOise characteristics not
offered by competitive line-powered devices. The LB1020AF performs the switching functions needed for speakerphone operation, accepting transmit and
receive signals as input, and providing transmit and receive variolosser control
signals as output. Timing of switching functions is selectable uSing external RC
combinations. There is a noise-guard feature which permits steady background
noise to be ignored in making the transmit/receive switching decIsion.
Features
• Switching, unaffected by background noise
• Single power supply
• Half-duplex operation; receive in default
• All timing, Including fallback to default, controllable with external components
• Provides complete speakerphone operation when used with the LB1021AD device
Functional Diagram
• 24-pin plastic DIP
XMIT TALKDOWN
INPUT
RCVSW
GUARD INPUT
XMIT SW
GUARD INPUT
~---+-----+------·~~~~CKT
~---t------·~~~~CKT
TO RC
TIMING CKT
RCV
TALKDOWN ------------+---~
INPUT
TO RC
TIMING CKT
~------.~~~~CKT
QUIET ON/OFF
INPUT
RCV VARIOLOSSER XMT VARIOLOSSER
CONT CUR CONT CUR
(Refer to Section 19 for typical applications of this product.)
Spring 1988
2·33
Analog ICs
Speakerphone Device Set
Power Conditioner/Amplifier LB1021AD
Description
This device provides the linear amplification for a full-feature speakerphone
system, including switch able, controllable gain for the transmit and receive voice
paths, speaker and line drive capabilities, and switchguard/talkdown gain. In addition, it provides a stable, low-noise signal reference from the single 12 volt supply
needed to power the circuit.
Features
• High-gain receive preamplifier accommodates variety of microphones
• 700 mA speaker drive capability
• Gains and switching controllable by 0-100 pA control currents
• Provides complete speakerphone operation when used with the LB1020AF device
Functional Diagram
• 18-pin plastic DIP
RECEIVE PREAMP
VARIOLOSSERISPEAKER DRIVER
RC2
RC1
RCV
IN
SPEAKER OUTPUT
RECEIVE SWITCHGUARD PREAMP
+IRVL
RECEIVE
TALKDOWN
PREAMP
RECEIVE
VARIOLOSSER
CONTROL CURRENT
+6V
-
RECEIVE PATH
VARIOLOSSER/LINE DRIVER
TRANSMIT PREAMP
REFERENCE
L-_,..---' VOLTAGE
TO LINE
TC2
TC1
-6V
IIVL
MIKE
IN
+
TRANSMIT
VARIOLOSSER
CONTROL
CURRENT
TRANSMIT
TALKDOWN
PREAMP
TRANSMIT PATH -
2·34
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Analog ICs
Telephony Devices
Electret Preamplifier -
LB1027AB
Description
The LB1027AB is a voice-frequency preamplifier specifically designed for electret
microphone applications. This device operates from a supply voltage of 15 volts
down to 1.1 volts (with some performance degradation below 1.6 volts).
Features
• Input impedance of 125 MO (in parallel with 2.5 pF)
• Low power drain « 327 pA at 4 V)
• ac voltage gain of 18 dB
• 600 mV peak-to-peak output voltage swing
• TYPical output resistance of 50
Functional Diagram
n
• Available in wafer form or as an 8-pin DIP
v+
2
~______~______1~OUT
IN
3
NOTE 2
+
+
NOTE 2
GND
Notes:
1. Internal Current Source
2. Effective Internal Voltage Source
(Refer to Section 19 for typical applications of this product.)
Spring 1988
2·35
Analog ICs
Telephony Devices
Full-Feature Tone Ringer/Ringing
Detector - LB1004AC
Description
The LB1004AC integrated circuit is a Full Feature Tone Ringer/Ringing Detector
which simultaneously provides a ringer-output tone and a "ringing-detected" output signal. The tone ringer portion of the device provides switch-selectable output
frequencies of 750, 900, 940, and 1200 Hz at Independently selectable modulation rates of 7.5, 10, 15, and 20 Hz. Amplitude or frequency modulation may also
be independently selected. These TTL/CMOS logic or switch-selectable features,
controlling both the type of sound and its duration, provide distinctive ringing
capabilities which are useful for a multiphone office environment. The ringer can
be prevented from providing a tone output with a "Ringing Inhibit" function. These
functions can be controlled by a microprocessor, allowing various alerting tasks to
be performed by appropriate programming. The ringing detector portion of the
device provides an output (LED OUT) which can interface with a microprocessor
or an opto-isolator.
Features
• Complete telephone bell replacement with distinctive ringing capability
• Tight output frequency control (±3%) for maximum acoustic output
• External components: only two capacitors and one resistor required
• Independently selectable AM or FM modulation
• On-chip volume control resistors provided
• Immune to rotary dial pulsing (bell tap)
• Meets both type A and B ringing requirements (40 VRMS :::;VIN :::;150
15 Hz :::;flN :::;68 Hz) as specified by EIA RS-470 and FCC Part 68
VRMS,
• Meets input impedance criteria specified by EIA RS-470 and AT&T Technical
Publication 47001
• Logic- or switch-selectable output frequency and modulation rate options
• Internal polarity guard and 1500 V lightning surge protection provided
• Ringer equivalency: 1.0 B
2·36
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Analog ICs
Telephony Devices
LB1004AC Tone
Ringer/Ringing
Detector Functional
Diagram
V+
TP
FULL WAVE RECT.
ZIN VS. VIN
SURGE PROTECTION
MAG. COMPARATOR
RP
COMM ON
~
-
J
AIVINI
(MAG.)
VBRIDGE
RESET
BRIDGE LOADING
&
LED CIRCUITRY
RINGING
DETECTOR
LOGIC
+8 r--<~
(ItERNtL
CONNECTIONS)
!
,--
OSC.
28.8 ! - - kHz
'---
REF. CURRENTS
AND
REF. VOLTAGES
VBG
OUTL
~
RING DETECTED
:>
~
OUT M
~
--
MO 01
~
MODULATION RATE
LOGIC & INTERFACE
--
MO 02
t
r
+
SELECTABLE
FREQ.OSC.
26.25 kHz
31.50 kHz
42.00 kHz
f
FS 1
f
FS 2
------
LED
OUT
+5/+4
SHIFT
1
AM
----
+7
DUTY
CYCLE
(28%)
TON~
,
ENABLE
LOGIC
&
I'P
OVERRIDE
Vose
Sl.J1...1'
VOUT
RINGING INHIBIT
(FREQ. CONTROL)
Spring 1988
2·37
Analog les
Telephony Devices
General·Purpose Tone Ringers LB1005·TYpe
Description
These integrated circuits provide a low-cost telephone alerter function with an output tone warbling between the base frequency and 1.25 times that of the base
frequency, at a 15 or 20 Hz modulation rate. These devices meet all known standard criteria for telephone alerters, and also drive piezoelectric transducers directly. The LB1005AB is a tone ringer having an 1800 Hz base frequency, and is particularly suited for applications where space for the alerter is at a premium. The
LB1005BB is a tone ringer having a 1200 Hz base frequency. This device produces a pleasant tone where required space is available for the alerter. The
LB1005CB has a base frequency of 900 Hz.
Features
• Provides an inexpensive and more compact alerter than an electromechanical bell
• Tight output frequency control (±3%) for maximum acoustic output
• External components required are two capacitors, one resistor, and an alerter
• Meets both Type A and B ringing requirements (40 VRMS :::;VIN :::;150
15 Hz :::;flN :::;68 Hz) as specified by EIA RS-470 on FCC Part 68
VRMS,
• Immune to rotary dial pulsing (bell tap)
• Meets input impedance criteria specified by EIA RS-470 and AT&T Technical
Publication 47001
• Polarity guard and 2000 V lightning surge protection provided
• On-chip volume control resistors provided
• Provides essentially no loading under non-ringing conditions
2-38
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Analog ICs
Telephony Devices
LB1005·Type General·
Purpose Tone Ringer
Functional Diagram
V+
TP---t--~
R P - - -......
t~
COMMON
FULL WAVE RECT.
ZIN VS. VIN
SURGE
PROTECTION
& MAG. COMPo
--~ -~j
.......
AIVINI
(MAG.)
......
VSG
VSRIDGE
RESET
RING
OSC.
LL!
BRIDGE LOADING
CIRCUITRY
RINGING
DETECTOR
LOGIC
REF. CURRENTS
AND
REF. VOLTAGES
CONNECTIONS)
RING
DETECTED
20 Hz
MODULATION
RATE DIVIDER
L -_ _ _.....
5/4
SHIFT
DUTY
CYCLE
(20/25%)
r------
OUTPUT
ENABLE
OUTM
H>
" > - - - - - - -.... VOUT
Spring 1988
2·39
Analog ICs
Telephony Devices
Ringing Detector -
LB1006AB
Description
The LB1006AB Ringing Detector provides ringing detection functions from the TipRing pair of a telephone loop. This device provides a nominal output current (up
to approximately 1 mAl for two types of output drives. The output can be connected to either an opto-isolator device or to a logic interface with a
microprocessor.
Features
• Provides an inexpensive means of ringing detection
• Operates on less than 1.0 mA from the telephone loop
• Internal polarity guard and 2000 V lightning surge protection
• Immune to rotary dial pulsing (bell tap)
• Meets both Type A and B ringing requirements (40 VRMS :5VIN :5150 VRMS,
15 Hz diN :568 Hz) as specified by EIA RS-470 and FCC Part 68
Functional Diagram
• Ringer equivalency: 0.8 B
V+
TP
FULL WAVE RECT.
ZIN VS. VIN
SURGE PROTECTION
& MAG_ COMPo
RP
I
VBG
VBRIDGE
RESET
COMMO N
-
AIVINI
~
+++
BRIDGE LOADING
CIRCUITRY
(MAG.)
RINGING
DETECTOR
LOGIC
REF. CURRENTS
AND
REF. VOLTAGES
(INTERNAL
CONNECTIONS)
RING
DETECTED
OUT H
RING
OSC.
... 25
OUTPUT
MIRROR
OUT L
2·40
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Analog ICs
Telephony Devices
Keypad-Controlled, Touch-Tone
Single-Chip Telephone Integrated
Circuit - LB1008AE
Description
The LB1008AE integrated circuit requires only a few external components to provide all of the touch-tone electronic functions. This integrated circuit furnishes ac
and dc loop termination for both sWltchhook states, transmits and receives vOice
signals to and from the Central Office, provides dual-tone multi-frequency (OTMF)
signals to the Central Office, and properly distinguishes between spurious noise
and genuine ringing signals, providing a distinctive audible alerter output.
Features
• An alerter select function of 1200/1500 Hz or 1800/2250 Hz
• Capable of speech transmission down to 3.0 mA loop current
• Compatible with electret and carbon microphones
• Signal ground pin eliminates external capacitor for dial-in-handset designs
Functional Diagram
(4·Wire Handset
Interface)
• 700
n line-matching
impedance, 600
n receiver
impedance
• Provides a power port for driving an LED
n
480 kHz
RESONATOR
ALERTER
FREQUENCY
SELECT
c=J
OS
AS
ALERTER
LB1008AE
AL1
RINGER
LOGIC
SURGE
PROTECTOR
KEYPAD
TP
C1-C3
DTMF
LOGIC
RING
SWITCH
HOOK
AC
TERMINATION
RESISTOR
AND
POWER
CONDITIONER
SW
RP
FILTER
CAPACITOR
Advanced information -
AL2
I
VS
R1-R4
DOD
DOD
DOD
DOD
SPEECH
NETWORK
DR
Sample devices are not necessarily available at this time.
(Refer to Section 19 for typical applications of this product.)
Spring 1988
2·41
Analog ICs
Telephony Devices
Microprocessor Controlled,
Single-Chip Telephone Integrated
Circuit - LB1009AE
Description
The LB1009AE single-chip touch-tone telephone integrated circuit interfaces with a
4-bit microprocessor for applications requiring enhanced features such as repertory dialing, Four basic telephone functions are integrated on-chip: furnishes ac
and dc loop termination for both switchhook states; transmits and receives vOice
signals within performance guidelines (including transducer variations); provides
dual-tone multifrequency (OTMF) signals to the Central Office; properly
distinguishes between spurious noise and genuine ringing signals, providing a
distinctive audible alerter output.
Features
• Signal Ground pin eliminates an external capacitor for dial-in-handset designs
• Requires only a 2-contact switch hook
• Capable of speech transmission down to 3 mA loop current
• Operates from power supplied by the Central Office
• Alerter select options 1200/1500 Hz, 1800/2250 Hz
• Compatible with electret microphones
Functional Diagram
• Provides a power port for driving an LED or microprocessor
ALERlER
FREQUENCV
SELECT
LB1009AE
TiP
SURGE
PROTECTOR
TP
sw
RING
AC TERMINATION
RESISTOR AND
POWER
CONDITIONER
RP
VR
TX
SPEECH
NETWORK
RO
1
V+
+
FILTER
CAPACITOR
2·42
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Analog ICs
Telephony Devices
Telephone Interface
Circuit - LH1028BB
Description
The LH1028BB Telephone Interface CIrcuit (TIC) IS a product fabrication of
monolithic high-voltage DMOS technology and dielectric Isolation This Integrated
CIrCUit performs the following basIc functions high-voltage dial pulse sWitching,
protection against reversal of Tip-Ring polarity from the Central Office, and (wervoltage/overcurrent protection of telephone circuits.
Features
• Withstands telephone loop voltages to 155 V
• Operates at low Tip-Ring voltages (tYPically as low as 2 7 V)
• Minimal internal voltage drop across polarity guard
Functional Diagram
• Monolithic solid-state construction allows for greater reliability and physical area
conservation
TP
OUTPUT VOLTAGE ~,
LIMITING DEVICE
(+)
TIP ~
RING
--
POLARITY
GUARD
(FULL-WAVE
RECTIFIER)
I
(-)
DIAL PULSE/CURRENT
LIMITING CONTROL
~
~
:I
I-
DP
DP'
I
CURRENT
SENSING
RESISTOR
I
I
I
RP
DIAL
PULSE
SWITCH
(Refer to Section 19 for typical applications of this product.)
Spring 1988
2·43
Analog ICs
Telephony Devices
Universal Voice-Signal
Conditioner - LB1068AW
Description
The LB1068AW silicon integrated circuit is intended for use as a conditioner of
voice signals in telephone handset and speech applications. The device provides
the following five functions:
1. High PSRR electret microphone biasing - low noise output in the presence of
power-supply modulation.
2. Microphone preamplification with adjustable gain-provides flexibility for different microphone and acoustic applications.
3. Gain expansion of the microphone signal - reduces the effects of background
noise during periods when the talker is silent.
4. Adjustable gain receiver amplification With a choice of 300 0 or 600 0 output
impedance; active receiver driver for noisy environments or hearing-impaired
applications.
5. Receiver clamping - limits high transient signals from overdriving the receiver.
Features
• Supply-voltage range from 2.6 to 10 V (suitable for line-powered applications)
• High PSRR electret microphone biasing (typically> 50 dB)
• User-selectable microphone and receiver gain
• Usable with other types of microphones (ceramic, dynamic, etc.)
• Internally supplied signal ground
• Built-in receiver equalizing resistors for 300 0 or 600 0 applications
This information is preliminary and subject to change.
2·44
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Analog ICs
Telephony Devices
LB1068AW Universal
Voice·Signal Con·
ditioner Functional
Diagram
V+
,--- -- ------------------l
I
LEVEL EXPANDER
I
I
SECTION
I
TXOUT
IN V - - f - t - - - - - - - _ - - - - - - ;
PRO Q - - f - t - - - - - - - - ,
TRANSMIT
PREAMP
L
TXIN 0--1-,-----1
MICOUT 0 - - + + - - - - ' - - - - - ,
RTCC
MICIN 0--H---1
,-
- - -1
I
I
I
I
I
I
I
I
SPEECH
NETWORK
I
,----0--+-'-----------;
I
ELECTRET
XMTR
I
I
I
I
+----t-+----{J RXI N
RX AMP 1
I
I
I
SPEECH
RETURN
SECTION
I
I
I
I
I RXOUT N
I
I
I
I
I
L ___________________ J
:
I
I
I
I
I
I
I
i
I
TELEPHONE
HANDSET
L- _ _ _ _ _
...J
COMMON
1 A
ESD > 2.5 kV (H BM)
• Polysillclde Resistance: 2.5 DID
• Effective Channel Length: 1.0 J.!m
• Speed Performance (SLM): tPLH = tPHL = 0.7 ns
(typical process parameters: 2-input NAND, fanout = 2.2 mm metal track,
VDD = 5 V, T = 25°C)
1.75 and 1.25 11m CMOS Standard Cell Libraries
Total of over 400 different functions available.
1. Logic Functions:
Logic Cells
Latches/Flip-Flops
2. 1/0 Functions:
1/0 Drivers
1/0 Buffers
3. MSIILSI Digital Functions
Arithmetic Logic Units
4-Phase Clock Generator
Divide-by Counters
4-Bit Fast Adder
4-Bit Look-ahead Carry Generator
Microprocessor Interface
Majority Vote
Programmable CounterfTimers
Fast-Locking Data-Rate PLL
4. Complex Macrocells:
Functional Block Compilers
Adder
Comparator
Counter
Decoder
Multiplexer
Parity Generator
Universal Register
Combinational Block
Finite State Machine
Parameterized Macroblock Compilers
ROM
RAM
PLA
Shift Register
5. Selected Analog Functions:
Oscillators
Power-up Reset
Resistors and Capacitors
TransmitterlReceiver Interfaces
Spnng 1988
3·5
Application Specific ICs
ASIC Standard Cells
CAD System
• SCHEMA - allows schematic entry and automated netllst generation
• FDS - synthesizes complex functions from standard cells
• SCOAP - estimates the testability of digital circuits
• MOTIS - provides logic, timing, and fault analysis for complete chip design
• MISL - generates test vectors from high-level language
• Design Audits - detect certain design flaws, such as: races, glitches, asynchronous loops, etc.
• Synchronous Delay Audits paths
analyze speed performance of Individual circuit
• ADVICE - circuit simulator, proVides transistor-level simulations
• LTX2 - produces optimum chip layout with respect to chip size and performance
• HCAP - extracts layout connectivity and node capacitances
• GRED - allows Interactive layout editing
• LARC - provides layout design rule checking
• Vector Audits - detect potential hazards in test vectors
• TPG2 - program for automatic test program generation
Design Cycle
SILVAR·LlSCO, HILO, VALID,
MENTOR, DAISY, SUN
WORK STATIONS
3-6
Spring 1988
AT&T'S
CAD SYSTEM
4
Capacitors
AT&T's metallized film
capacitor line includes
axial, radial, and 2-pin
DIP configurations. These
capacitors are highly
reliable due to their selfhealing property. The
benign failure mode,
characteristic of metallized film capacitors (they
fail open rather than
short), makes them
suitable for a broad range
of electronic system
applications.
Page
Miniature Metallized Film Capacitors
4-2
Standard Metallized Film Capacitors
4-3
Other Products
4-4
Our 2-pin DIP capacitor is
epoxy-molded and
machine-insertable. It is
particularly well-suited for
bypass applications
where high component
packing densities are
required.
For additional infor·
mation contact your
nearest sales office
or call:
1-800-372-2447.
Spring 1988
4·1
Capacitors
Miniature Metallized Film
Our smallest size capacitors utilize micro-thin metallized polyester films for a higher
capacitance per volume ratio. These capacitors are self-healing, resulting in high
reliability, and are specially sealed for added moisture resistance. Mini-box and
mini-tubular type configurations are designed to operate from -40 to +85"C
without derating. The 2-pin DIP type configuration is designed to operate from
-40 to +100"C without derating. Capacitors with rated voltages of 50, 100, or 200
Vdc are available, depending on capacitor size and value. They are machineinsertable and well-suited for general-purpose applications. These miniature
capacitors are also designed for soldering methods employing water-soluble flux.
2·Pin DIP Type
• Capacitance range: 0.01 to 0.12 /-tF
• Encased in flame-retardant epoxy molding compound
• Full hard Olin 194 brass, solder-plated leads
• Ideal for PC board bypass applications (fails open - not short)
• Designed for long-term reliability, even in hostile (elevated temperature and high
humidity) environments
• Packed in plastic tubes for automatic insertion
Mini·Box Type
• Capacitance range: 0.01 to 2.2 /-tF
• Encapsulated in flame-retardant rectangular insulated case and sealed with flameretardant epoxy
• Radial solder-coated wire leads
• Supplied in standard lead spacings
• Volumetrically efficient unit requiring minimum PC board real estate
• Available on reels or in plastic tubes for automatic insertion
Mini·Tubular Type
• Capacitance range: 0.0022 to 1.2 /-tF
• Flame-retardant tape encapsulation and epoxy-filled ends
• Axial solder-coated wire leads
• Cost-effective mini-axial design
• Available on reels for automatic insertion
• Polypropylene film version available
4·2
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Capacitors
Standard Metallized Film
Our standard size family of metallized polyester film capacitors is available in a
wide range of sizes and values. These capacitors are designed to operate at
temperatures ranging from -40 to +85"C and can be used with water-soluble
flux. They have superior moisture resistance. Their self-healing property and stable
electrical characteristics make them an excellent choice for general-purpose
applications, such as coupling, bypassing, filtering, timing, and noise suppression.
Tubular Type
• Capacitance range: 0.020 to 5.1 ,J=
• Rated voltages: 80, 100, 150, and 200 Vdc
• High volumetric efficiency
• Flame-retardant tape encapsulation and epoxy-filled ends
• Axial solder-coated wire leads
• Available on reels for automatic insertion
Box Type
• Capacitance range: 0.147 to 2.2 JLF
• Rated voltages: 100 and 250 Vdc
• High volumetric efficiency
• Encapsulated in flame-retardant rectangular insulated case and sealed with flameretardant epoxy
• Radial solder-coated wire leads
• Available in plastic tubes for automatic insertion
Flat Type
• Capacitance range: 0.004 to 10.0 JLF
• Rated voltages: 100, 150, 200, 250, 300, 350, and 500 Vdc; 220 Vac
• Flat oval form saves PC board space
• Flame-retardant tape encapsulation and epoxy-filled ends
• Axial solder-coated wire leads
• Tolerances down to
±1%
available
(Refer to Section 19 for typical applications of this product.)
Spring 1988
4·3
Capacitors
Other Products
Film-Foil Type
AT&T Film-Foil capacitors use polystyrene, polypropylene, or polyester film as a
dielectric and tin/lead metal foil as an electrode. They operate in a temperature
range of -40 to +85"C. All of these capacitors are encapsulated with flameretardant tape and epoxy-filled ends. Both polystyrene and polypropylene
capacitors are preferred for applications requiring exceptional capacitance stability,
low losses, or negative temperature-coefficient characteristics. Polystyrene
capacitors are particularly well-suited for quick discharge applications and can
withstand lightning surges of up to 850 volts.
• Polystryrene dielectric: 0.000301 to 0.768 j.tF, 50, 100, 200 Vdc
• Polypropylene dielectric: 0.000301 to 0.787 j.tF, 125 Vdc
• Polyester dielectric: 0.001 to 0.0196 j.tF, 125 Vdc
Networks
Networks are unique laser-generated series capacitor-resistor elements of metallized film construction which offer self-healing properties. They are compact,
space-saving components, specifically designed for contact protection applications. Two types (0.13 j.tF/470 0 and 0.05 j.tF/75 0) are available, both with 350 V
and 10· pulse rating. These axial-lead, flame-retardant, tape-wrapped, and epoxy
end-filled networks can be supplied on reels for automatic insertion.
CAP-PAKs
CAP-PAKs are combinations of individual wound film capacitors, housed in a
rugged, modular, radial-leaded, flame-retardant package. They can be tailored for
almost any multi-capacitor requirement. The installation of a single CAP-PAK
reduces assembly time and cost, especially when using higher volume units. In
addition, insertion errors and inventory problems are minimized.
4-4
Spring 1988
(Refer to Section 19 for typical applications of this product.)
5
Communication Integrated
Circuits
Page
Included in AT&T's comprehensive line of communication ICs are a
complete line of ISDN
basic-rate and primaryrate devices, DS1 interface solutions, encryption
devices, data formatters,
codecs, and clock
recovery circuits.
Our digital loop controller
circuits spearhead the industry's move to integrated services digital
networks (ISDN), soon to
be the backbone of digital
communications, combining both voice and data
signals.
The DS1 chip set performs the various multiplexing and framing functions required by the
physical interface to a T1
facility.
For additional infor·
mation contact your
nearest sales office
or call:
ISDN - Integrated Services Digital
Network
5·3
UNITETM ISDN Family of Basic-Rate
Devices
*
Four-Wire Interfaces
User Network Interface for Terminal Equipment - T7250A
User Network Interface Termination for Switches T7252A
Two-Wire Interface
ISDN U-Interface Basic Access Transceiver Chip Set T7260 and T7261
Synchronous Packet Data Formatter - T7111A
Asynchronous Receiver/Transmitter Interface - T7112
5·4
5·6
5·8
5·10
5·12
UNITETM ISDN Family of Primary-Rate
Devices
*
*
1-800-372-2447.
*
Digital Signaling Interfaces
DS1IDS1C - LC1046A
DS1 - LC1046C
CEPT - LC1135B
DS1/CEPT Support Circuits
Primary Access Framer - T7229
Maintenance Buffer - 229FB
Transmit Formatter - 257AL
Receive Synchronizer - 257AU
DS1 Support Circuits
Loop Divider - 41 KW
Timing Generator - 129EC
Synchronous Protocol Data Formatter with
Serial Interface - T7110
Synchronous Protocol Data Formatter - T7115
5·14
5·15
5·17
5·18
5·20
5·21
5·22
5·23
5·24
5·25
5·26
(Continued on next page)
* Did not appear in the previous edition of the Product Selection Guide.
Spring 1988
5·1
Communication ICs
(Continued)
Page
Data Protocol
*
Digital Encryption Processor - T7000A
Random Number Generator - T7001
Bit Slice Multiplier and Extender - T7002, T7003
X.2S Protocol Controller - T7100A
X.2S/X.7S Protocol Controller - T7102A
5·28
5·29
5·30
5·31
5·33
Codec Products
*
*
p,-Law, A-Law, ±5 Volts
PCM Codec With Filters - T7500
PCM Codec With Filters - T7513A
wLaw, A-Law, 5 Volts
Dual PCM Codec With Filters - T7512
Linear, High-Precision, ±5 Volts
PCM Codec With Filters - T7520A
PCM Codec Without Filters - T7521A
PCM Codec With Filters - T7522, T7523
Linear, High-Precision, 5 Volts
PCM Codec With Filters - T7525
5·34
5·36
5·38
5·40
5·42
5·44
5·46
Clock Recovery Circuits
1-50 MHz with descrambler - T7032
1-50 MHz without descrambler - T7033
* 25-50 MHz without descrambler - Tl034
* Did not appear in the previous edition of the Product Selection Guide.
5-2
Spring 1988
5·48
5-49
5·50
Communication ICs
ISDN - Integrated Services
Digital Network
The major purpose of ISDN is the definition and worldwide agreement for both
user-to-network and network-to-network Interfaces, A user who has a system connected to an ISDN interface has access to network services through one interface
structure, The ISDN network will provide all of these services at faster speeds and
larger capacity while incorporating advanced digital switching and transmission
systems that all speak the same language, regardless of manufacturer or location,
Two Interfaces are defined to govern interactions between the network and
customer equipment. The two CCITT-approved interfaces are called basic rate and
primary rate, Both interfaces can provide data or voice service simultaneously and
circuit-switched or packet-switched connections on the same transmission channel.
Basic Rate Interface consists of two 64 kb/s information channels (B channels)
used for voice and data, and one 16 kb/s packet-switched data channel
(D-channel) used for signaling and data. The Band 0 channels are full duplex bit
streams, They are time-division multiplexed into a common stream containing both
user information and signaling, The basic rate interface serves small end-systems
such as voice/data workstations and terminal adapters for non-ISDN devices,
Primary Rate Interface consists of twenty-three 64 kb/s B-channels for voice and
data plus one 64 kb/s D-channel for,signaling, This interface is based on the DS1
transmission rate of 1.544 Mb/s. The signaling is performed on the D-channel,
allowing the user a full 64 kb/s range tin the B-channels. Typical applications are
connecting a PBX or mainframe compl'lter to an ISDN.
PABX
TERMINAL ENDPOINT
CONCENTRATION
HIGHWAY
(28+0)
4-WIRE S-INTERFACE
POINT-TO-POINT
NETWORK TERMINATION
(2B+0)
CENTRAL OFFICE
c
0
4-WIAE S-INTERFACE
N
K V
POINT-TO-MULTIPOINT
TO E
(2B+O)
2-WIRE
U-INTERFACE
,------1 s ~
I
o
N
PABX
T
7
I
~
,
9
LC1046 I+--=~".......-H LC1046
OR
ISDN PRI
OR
LC1135
(CEPT)
(238+0)
LC1135
(CEPT)
RS232
DATA LINE
(Refer to Section 19 for typical applications of this product.)
Spring 1988
5·3
Communication ICs
UNITE ISDN Family of Basic·Rate Devices
Four-Wire Interfaces
User Network Interface for
Terminal Equipment - T7250A
Description
The T7250A User Network Interface for Terminal Equipment circuit provides the
line interface used for basic access service offered by the Integrated Services
Digital Network (ISDN). The device conforms to all CCITT 1.430 recommendations
for point-to-point and point-to-multipoint configuration. Priority, contention resolution, multiframing, and activation/deactivation processes are fully supported. With
a simple transformer circuit, 1.430 impedance and voltage requirements can be
met. An HOLC formatter and a sophisticated queue manager are provided to
simplify the 0 channel interface.
This device is manufactured using CMOS technology, and is available in either a
40-pin plastic DIP or 44-pin plastic leaded chip carrier (PLCC). The 44-pin chip
carrier provides additional 16/8 kHz and 6.144 MHz/192 kHz clocks that the 40-pin
DIP does not have. The T7250A device uses a nominal 5 volt supply and has a
maximum power consumption of 55 mW.
Features
• Built-in HOLC formatter for the 0 channel
• Programmable synchronization signal for codecs
• Power-up reset with a programmable timer for system interface control
• Interchangeable B channels for voice or data
• 16 bytes of transmit and receive buffers for the 0 channel
• Local and remote loopback test modes
• Passive bus support
5·4
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Communication ICs
UNITE ISDN Family of Basic-Rate Devices
T7250A User Network
Interface for Terminal
Equipment Block
Diagram
TXB1, TXB2
I
SIT TRANSCEIVER
INTERFACE
2B + 0 CORE
B1, B2
2
0
~
FORMATTER
TRANS
---
0
PRIORITY
MECHANISM
E
~
~
CK6
a&s
CKB2, MCKB1
I
1
RXOATA
FSEB1, FSEB2
r---j
TPR
r-----I TNR
CK192
CONTENTION
RESOLUTION
MULTIFRAMER
f--
..- ------.: REXT
2
&
.--
TRANSMIT
OUTPUT
DRIVER
TIMING
RECOVERY
(PLL)
~
RCV
2
2
RECEIVE
DETECTOR
FRAMER
(B1+B2+0+S )
--,
--l
- - - I RPR
VT
RNR
~ CKCOO
CKOM
SYSTEM
CLOCKS
1
l
SYSCKO
o CHANNEL
I
TRANSMITTER
HOLC FORMATTER
II
RECEIVER
I
8
DATA
BUS
TIMER
cs
SYSTEM INTERFACE CONTROLLER
DATA REGISTERS
CONTROL REGISTERS
STATUS REGISTERS
TIMOUT
~P
INTERFACE
CONTROL
~ WR
~ AD
~ NT
~I
~ 00-07
AO-A3
~i
~i RESET
Spring 1988
5-5
Communication ICs
UNITE ISDN Family of Basic·Rate Devices
Four-Wire Interfaces
User Network Interface Termination
for Switches (UNITS) - T7252A
Description
The T7252A User Network Interface Termination for Switches is a silicon integrated circuit that provides the user with level 1 network termination (NT) functions
for ISDN. The T7252A UNITS provides full-duplex 2B+D communication at
192 kb/s over a four-wire digital subscriber loop. Channels B1 and B2 are 64 kb/s
voice or data channels, and the D channel is a 16 kb/s control or data channel.
All point-to-point and point-to-multipoint (passive bus) configurations are supported
as defined in the 1986 version of CCITT Recommendation 1.430 and the
November, 1986 Draft US Specification. The T7252A UNITS communicates with a
switching network over a user-configured time-division multiplexed highway. A
generic microprocessor interface is also provided. The T7252A UNITS is manufactured in low-power 1.25 micron CMOS technology, and is available in either a
44-pm plastic leaded chip carrier or a 40-pin DIP It operates on a 5 V power
supply and has a maximum power consumption of less than 100 mW.
Features
• Full-duplex 2B+D interface for point-to-point and point-to-multipoint (passive bus)
configurations with automatic threshold adjustment
• B1, B2, and D channels separated from and combined into a 192 kb/s stream
• Two independent transmit/receive serial highways, with assignable time slots for
voice/data transfer
• Generic parallel microprocessor interface, with either multiplexed or demultiplexed
address/data lines and maskable Interrupts
• Capability of direct microprocessor control of B1, B2, or D channel through the
microprocessor interface
• M ultiframing support, with access to the S (NT -to-TEl and Q (TE-to-NT) channels
through microprocessor registers
• Provides 1.430 interface for 2B+D applications in digital switches (PBXs, etc.)
• Selectable speeds on serial highway: 256 kHz (4 time slots) to 4.096 MHz (64
time slots)
This information is preliminary and subject to change.
5·6
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Communication ICs
UNITE ISDN Family of Basic-Rate Devices
T7252A UNITS
Block Diagram
RPR
VT
OXB
~
~
,..--.
r---.
TPR
4-WIRE
2B+0
MUX/OEMUX
LINE
~
TRANSCEIVER
CORE
TNR
I--
RNR
OXA
CONCENTRATION
HIGHWAY
~
ACCESS TO
TIME SLOTS
~
TSCA
ORB
ORA
REXT
6.144 MHz
CLOCK OR
CRYSTAL
TSCB
!
---
!
!
.......- FS
.......- CLKXR
MICROPROCESSOR
INTERFACE
----
•
•
I
,
-
INT
~
A (3-0
A0(7-0)
RO
CS
ALE
WR
Spring 1988
5-7
Communication ICs
UNITE ISDN Family of Basic·Rate Devices
Two-Wire Interface
ISDN U-Interface Basic Access
Transceiver Chip Set T7260 and T7261
Description
The AT&T T7260 and T7261 ISDN U-Interface Basic Access Transceiver (U-BAT)
chip set is a pair of silicon integrated circuits providing full-duplex 2B+D communication on a 2-wlre digital subscriber loop. The T7260 and T7261 devices perform line transceiver functions at either the Central Office switch or at the network
termination and operate at a data transfer rate of 144 kb/s. Adaptive echo
cancellation and equalization techniques provide a loss budget of 38 dB. The
T7260 requires both a +5 V and -5 V supply; the T7261 requires only a 5 V
supply. Both are manufactured in CMOS technology and are packaged in a
44-pin plastic leaded chip carrier (PLCC).
Features
• U-interface for 2-wire operation. Pin-selectable for Central Office switch and network termination applications
• 144 kb/s full duplex using echo cancellation (EC)
• Alternate mark inversion line code as used in AT&T SESS® Central Office Switch
• Digital I/O via the AT&T K-interface
• On-chip balanced line driver
• Balanced continuous time filters
• Adaptive equalization and automatic gain control
• Power-down option
• LED driver to signal loss of framing
• Decision feedback equalizer (DFE) for increased tolerance to bridged taps
• EC and DFE reset pins for external power-up reset
• Selectable on-chip or external VCXO
5·8
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Communication ICs
UNITE ISDN Family of Basic·Rate Devices
T7260 and T7261
Block Diagram
K
INTERFACE
I
U
INTERFACE
T7260 (10 V)
T7261 (5 V)
I
I
I
I
I
I
I
I
I
I
I
I
-
RX
TX
+
I
I
I
LINE
INTERFACE
AND
POWER-FEED
R
I
I
I
CONTROL
DECISION
FEEDBACK EQUALIZER
I
I
I
I
I
I
DIGITIZED
RECEIVE
SIGNAL
I
I
LINE INTERFACE CONTROL
I
I
Spring 1988
5·9
Communication ICs
UNITE ISDN Family of Basic·Rate Devices
Synchronous Packet Data
Formatter - T7111A
Description
The T7111A Synchronous Packet Data Formatter (ANT) integrated circuit is used to
interface physical link level lines using bit-synchronous HOLC/SOLC protocols to
8-bit microprocessor or microcontroller systems. All inputs and outputs of the
T7111A ANT are TTL-compatible. It is implemented using CMOS technology and
requires a single +5 V supply. The device is available in a 28-pin plastic DIP for
standard through-hole mounting, or in a 28-pin plastic small-outline J-Iead (SOJ)
package for surface mounting.
Features
Host Interface
• Compatible with 8088 and 80188 Microprocessor-Based Systems and 8051
Microcontroller
• Compatible with 8237 and 8257 OMA Controllers in extended write mode
• Programmable receive and transmit queue interrupts with variable fill levels
• Programmable receive and transmit OMA requests with variable fill levels
Serial Link Interface
• Separate receive and transmit clocks
• 4 Mb/s maximum data rate
• 6-byte receive queue and 4-byte transmit queue
• Automatic flag transmission and detection
• Zero bit insertion and deletion for data transparency
• CRC-CCITT 16-bit polynomial generation and check with inhibit option
5·10
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Communication ICs
UNITE ISDN Family of Basic-Rate Devices
T7111A ANT Block
Diagram
MICROPROCESSOR
BUS
04-07
ADO-AD3
ALE
RD
WR
CS
ROY
REOFINT
RXINT/DAV
TXINT/DRQ
DMAACK
SERIAL
LINK
I
I
RESET
I
DATA,
STATUS
I
I
.... II
I
I
I
I
I
I
I
I
HDlC
RECEIVER
..
BUS
INTERFACE
UNIT
RESET
DATA,
CONTROL
STATUS
HDlC
TRANSMITTER
II
I
I
RXD
RClK
TEST
RESET
ClK
TXD
RTS
CTS
TClK
Spring 1988
5-11
Communication ICs
UNITE ISDN Family of Basic-Rate Devices
Asynchronous Receiverl
Transmitter Interface - T7112
Description
The T7112 ARTI is an asynchronous, single-channel, full-duplex receiver/transmitter
interface for terminals and modems. The ARTI is compatible with the bus protocol
and timing specifications of both the 8051 Microcontroller and the 8088
Microprocessor. The device may be used in a polled or Interrupt driven system.
The transmitter has four buffers and the receiver has six buffers to reduce the
interrupt overhead and the potential for overruns. The device is implemented in
low-power, CMOS technology and is available in a 24-pin plastic DIP or 28-pin
plastic SOJ surface-mount package.
Features
• Programmable data format:
- Seven data bits plus parity
- Odd, even, no parity
- One or two stop bits
• 6-byte receive and 4-byte transmit data buffers
• 8088 (8 MHz) and 8051 (16 MHz) microprocessor interface without wait states
• Clear-to-send/request-to-send selectable signals for DTE or DCE modes and flow
control
• Programmable interrupt systems:
- Full level interrupt of receive FIFOs (first-in, first-out)
- Receive break detection and error interrupt
- Empty level of transmit FIFO and error interrupt
• Transmit/receive FIFO status bits indicate FIFO levels
• Flexible polling capabilities
• On-chip baud rate generator
• Speedmatching (autobaud capability)
5-12
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Communication ICs
UNITE ISDN Family of Basic-Rate Devices
T7112 ARTI Block
Diagram
RECEIVE
FIFO
6 BYTES
RXD
RTS
CTS
RXI
TXI
SXD
-------
i
RECEIVE
SHIFT
REGISTER
8/
/
te--
CONTROL
REGISTERS
ADBO-ADB7
RD
I'P
INTERFACE
WR
ALE
CS
MODEM
CONTROL
--
INTERRUPT
CONTROL
-
TRANSMIT
SHIFT
REGISTER
J
~
-I
STATUS
REGISTERS
INTERNAL DATA BUS
~
I--
BAUD RATE
GENERATOR
ClK
j
TRANSMIT
FIFO
4 BYTES
Spring 1988
5·13
Communication ICs
UNITE ISDN Family of Primary. Rate Devices
DS1/DS1C
Digital Signaling Interface -
LC1046A
Description
The LC1046A Digital Signaling Interface (OSI) is an integrated circuit that provides
a line interface between the OS1 or OS1C cross-connect and terminal equipment
circuits for cable distances of up to 655 feet for 22-gauge plastiC Insulated cable.
The device performs receive pulse regeneration, timing recovery, and transmit
pulse shaping and equalization functions. The LC1046A OSI device is manufactured using 1.75 micron CMOS technology and is available in a 28-pin plastic DIP
or 28-pin plastic small-outline J-Ieaded (SOJ) package for surface mounting.
Features
• Fully integrated OS1/0S1C line interface
• Pin-selectable B8ZS encoder and
decoder
• Compatible with Technical Advisory #34
(TA34) and PUB 43802 specifications
Block Diagram
• On-chip transmit equalization
• Multiple link-status and alarm features
• Monolithic clock recovery
• Minimal external circuitry required
LOCN
LOSN
Rl
--
BZSC
t
~
~MUX
--
BPV
LP3N
IT
T1
• Loopback modes for fault isolation
RECEIVE
,
LOSS OF
CLOCK
DETECTION
t
~
I
BIPOLAR
VIOLATION
DETECT
II
---rr
~
t
L
DUAL TO
SINGLE
RAIL
CONVERTER
.~~
I
~
R2
-
TRANSMIT
~Ic:
MUX [
~
:J
~
oe-r-t:1
MUX
SINGLE
TO DUAL
RAIL
CONVERTER
~
BLUE SIGNAL
GENERATOR
I
MUX
p
'--<
DECODE
LOGIC FOR i--CLR
TEST CLR
RS
EC2
LP2N
ECl
EC3
TBC
5·14
DECODER
-
RDATAN
RCLK
I
-- :J
-
~
MUX
~
T2
RBC
Spring 1988
BCLK
MUX
B8ZS
l1
I ENCODER I
TDATA
I
ATN
$
ALMTN
TCLK
ALL ANALOG
FUNCTIONS
+5
VODA
OUTPUT
DRIVERS
AND
LOGIC
+5
VODD
OUTPUT
DRIVERS
AND
LOGIC
GND
GNDD
ALL AN ALOG
FUNCTI ONS
GND
GNDA
(Refer to Section 19 for typical applications of this product.)
Communication ICs
UNITE ISDN Family of Primary-Rate Devices
DS1
Digital Signaling Interface -
LC1046C
Description
The LC1046C Digital Signaling Interface (DSI) is an integrated circuit that provides
a line interface between the DS1 cross-connect and terminal equipment circuits for
cable distances of up to 655 feet for 22-gauge plastic insulated cable. The device
performs receive pulse regeneration, timing recovery, and transmit pulse shaping
and equalization functions. The LC1046C DSI device is manufactured using 1.75
micron CMOS technology and is available in a 28-pln plastic DIP or 28-pin plastic
small-outline J-Ieaded (SOJ) package for surface mounting.
Features
• Fully integrated DS1 line interface
• Pin-selectable B8ZS encoder and
decoder
• Compatible with Technical Advisory #34
(TA34) and PUB 43802 specifications
• Loopback modes for fault isolation
• On-chip transmit equalization
Block Diagram
LOCN
LOSN
T
T1
R1
T2
R2
--
---
--
~
~ MUX
RECEIVE
LOSS OF
CLOCK
DETECTION
, ,
-==:J
I
~ 1-f
~
.... >-
BZSC
BIPOLAR
VIOLATION
DETECT
II
~
T
DUAL TO
SINGLE
RAIL
CONVERTER
r
MUX
I
P
EC2
LP2N
EC1
EC3
TBC
BCLK
r
>--
-
MUX
ATN
r-CLR
$
ALMTN
RDATAN
RCLK
~I J _IIr
TOATA
I ENCODER
r
MUX
DECODE
LOGIC FOR
TEST CLR
DECODER
1
SINGLE
TO DUAL
RAIL
CONVERTER
BLUE SIGNAL
GENERATOR
~
f
I
MUX
RBC
~-IT
MUX
~
~
• Minimal external cirCUitry required
BPV
LP3N
Lr
TRANSMIT
,
• Multiple link-status and alarm features
• Monolithic clock recovery
TCLK
ALL ANALOG
FUNCTIONS
+5
VOOA
(Refer to Section 19 for typical applications of this product.)
OUTPUT
DRIVERS
AND
LOGIC
+5
Vooo
OUTPUT
DRIVERS
AND
LOGIC
GND
ALL AN ALOG
FUNCTI ONS
GND
GNDD
GNDA
Spring 1988
5·15
5·16
Spring 1988
Communication ICs
UNITE ISDN Family of Primary.Rate Devices
CEPT
Digital Signaling Interface -
LC1135B
Description
The LC1135B Digital Signaling Interface (OSI) is an Integrated circuit that provides
a 2.048 Mb/s line interface to either twisted pair or coaxial cable as specified in
CCITT requirements G.703 and G.823. It performs receive pulse regeneration, timing recovery, and transmit pulse dnving functions. The OSI deVice IS manufactured using 1.75 micron CMOS technology and is available in a 28-pin plastic DIP
or 28-pln plastic SOJ package for surface mounting.
Features
• Fully integrated 2048 Mb/s line interface
• Compiles with CCITT specifications G.703 and G.823
• Pin-selectable 75/120 0 operation
• Monolithic clock recovery
• Low power -
85 mW (120 0), 88 mW (75 0) typical
• Pin-selectable HOB3 encoder and decoder
• Loopback modes for fault isolation
• Multiple link-status and alarm features
Block Diagram
SO
• Minimal external circuitry required
LOCN
LOSN
VIO
LP3N
LP1N
T1
RDATA
"'
T2
"2
't:tG~===t=::::;:=~=::=J--~-----;;;;~;---;;;;:;;;';--------4TCLK
OUTPUT
OUTPUT
I
$ 'U~TNS
ALL ANALOG
ZS
LP2N
TBe
BCLK
ALMTN
VDDA
DRIVERS
DRIVERS
AND
ANO
ALL ANALOG
\1000
GNDO
GNDA
:r G~r 'Gu:rNS
This information is preliminary and subject to change.
(Refer to Section 19 for typical applications of this product.)
Spring 1988
5·17
Communication ICs
UNITE ISDN Family of Primary· Rate Devices
DS1/CEPT Support Circuits
Primary Access Framer -
T7229
Description
The T7229 Framer integrated circuit provides the line-format and frame-format
interfaces for OS1 (1.544 Mb/s) and CEPT (2.048 Mb/s) digital carrier systems. It
performs in-line and off-line frame-oriented functions in both the receive and
transmit directions. The T7229 Framer is TTL-compatible, manufactured uSing
CMOS technology, and is packaged in a 40-pin plastic DIP
Features
• Multiple line-format capability
- AMI and HOB3 (CEPT)
- Bipolar and B8ZS
• Multiple TOM frame formats
- Independent formats - 04, SLC® Carrier, ESF, and DDS TlOM (OS1)
- CCITT 30-channel format, with optional TS-16 signaling (CEPT)
• Off-line, defensive, and fast-frame synchronization
• SLC Carrier, ESF, and DDS TlOM facility data-link insertion and extraction
• Remote frame/multiframe alarm activation and detection
• AIS detection
• Transmission performance monitoring capability:
- Bipolar, B8ZS, AMI, and HOB3 violations
- Frame-alignment signal (frame bit) errors
- Loss-of-frame/loss-of-multiframe alignment
- CRC-6 errors (ESF mode)
- Change-of-frame alignment
5·18
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Communication ICs
UNITE ISDN Family of Primary-Rate Devices
T7229 Primary
Access Framer Block
Diagram
r.-------------,
I RECEIVER
i~
RPDN
I
I
I
RNDN
OSO
OS1
OS2
OS3
COMMON
CONTROL
AND
STATUS
(TO/FROM
ALL BLOCKS)
OS4
OS5
CTLE
SRS
RECEIVE
FRAME-FORMAT
INTERFACE
RECEIVE
LINE-FORMAT
INTERFACE
iI
I
I
I
I
I
I
I
I
I
I
I
I
I
SCS
--
I
I
~
RECEIVE
FACILITY
MONITOR
RLF
RSI
RCEMA
I
RRFMA
I
I
ALIGNMENT
SYNC
I--
RECEIVE TIMING
GENERATOR
(TO ALL
RECEIVE
BLOCKS)
:
I
SCLK--~----~~--~------------------~
TICLK---r------------------------------~
TLCLK~~------------------------------~
TNDN
I
I
I
RISYN
RFDCLK
RLCLK
I
TRANSMITTER
SSYN--~----------~------------------~
1
RLV
RFECE
---------------1
I
TPDN
RFD
I
I
I
I
I
IL_____________ JI
r---
RID
TRANSMIT
LINE-FORMAT
INTERFACE
TRANSMIT
TIMING
GENERATOR
(TO ALL
TRANSMIT
BLOCKS)
TRANSMIT
FRAME-FORMAT
INTERFACE
...-I'--I.TFDCLK
I
I
I
TISYN
TFD
~
I
I
I
TID
L_______________________ JI
Spring 1988
5-19
Communication ICs
UNITE ISDN Family of Primary.Rate Devices
DS1/CEPT Support Circuits
Maintenance Buffer -
229FB
Description
The 229FB Maintenance Buffer integrated circuit provides the microprocessor
interface for the serial report and control streams of the T7229 Framer, 257AU
Receive Synchronizer, and 257AL Transmit Formatter. The device also processes
facility alarms received from the framer and provides additional latched inputs and
outputs for microprocessor use. The maintenance buffer IS manufactured using
depletion-mode NMOS technology, requires a single +5 V supply, and is
available in a 40-pin plastic DIP.
Features
• 8-bit Interface bus
• Microprocessor access to control/report streams
• Ten general-purpose latched outputs
• Two error-source latched inputs
• Preprocessing counters for facility error conditions updated by the framer
• Built-in operational testing capability
Block Diagram
• TTL-compatible
GPLOO-GPL07,
GPL10, GPLll
FSCS
TFCTLE
TSYNC
TRANSMIT
TIMING
\------+---.----t
L--_ _- - '
FSRS
SYSCLK
+------1
TRANSMIT
FORMATTER
INTERFACE
+------1
RECEIVE
SYNCHRONIZER
INTERFACE
'-----.j
RSYNC
RECEIVE
TIMING
RCTLE
TSCS
TSRS
RSCS
RSRS
AS
OS
BUSO-BUS7
ADDRESS
LATCHI
DECODER
WR
RD
ESRO-ESRl
5-20
Spring 1988
CLEAR
REGISTER
(Refer to Section 19 for typical applications of this product.)
Communication ICs
UNITE ISDN Family of Primary-Rate Devices
DS1/CEPT Support Circuits
Transmit Formatter -
257AL
Description
The 257AL Transmit Formatter integrated circuit converts 14 bits of parallel data (8
traffic bits, 5 signaling bits, 1 parity bit), received from a time slot Interchanger,
into a serial stream. The device is manufactured uSing NMOS technology, requires
a single +5 volt supply, and is available in a 32-pin plastiC DIP
Features
• Selectable DS1 (1.544 Mb/s) or CEPT (2.048 Mb/s) formats
• 2-, 4-, 16-state signaling or inhibit signaling Insertion
Block Diagram
LSFSY
LCLK
ASIG-ESIG
GSIG
D1-D8
PDS
PSEL
FSIG
SYSNC
SCLK
DGRSEL
• TTL-compatible
I
I
4.
h
~
!-
+-I
I
DATA
AND
PARITY
MODIFY
!
OUTPUT
SHIFT
REGISTER
(PIS)
r---
r---
RAM
PSENSE
B
U
F-BIT
AND
PARITY
DELAY
F
F
J
J
E
PCMO
OE
PDEL
~ FDEL
R
STIMING ~TOALL
CIRCUITS
CTRLlN
I
CTRLEN
I
I
MODE AND EXERCISES
EXERCISE
DECODER
ALARM
PROCESSING
(Refer to Section 19 for typical applications of this product.)
r-
r--_
RPTOUT
'---
Spring 1988
5·21
Communication ICs
UNITE ISDN Family of Primary-Rate Devices
DS1/CEPT Support Circuits
Receive Synchronizer -
257AU
Description
The 257AU Receive Synchronizer performs serial-to-parallel conversion, slip compensation, and signaling extraction on the serial data received from the framer.
The receive synchronizer is a part of an LSI digital facility interface chip set that
also includes the 257AL Transmit Formatter, the T7229 Framer, and the 229FB
Maintenance Buffer. The receive synchronizer is manufactured using NMOS
technology and is available in a 32-pin plastic DIP.
Features
• Selectable DS1 (1.544 Mb/s) or CEPT (2.048 Mb/s) formats
• 4- or 16-state, RSM signal extraction
• Internal maintenance circuits
• Single +5 V supply
Block Diagram
• TTL-compatible inputs and outputs
I
I
FBIT
SEL
SEL
FBIT
MODE 0-----
SIGINH
LDATA
I
DATA
MODE
a----.
LCLK
~
8
MODE 0-----
SIP
CONY
DATA
a----.
LINE
TIMING
f-----J ALARM
MODE 0 - - -
PY
8
I~AM
READ
SIG
EXT
SLIP
COMP
~ALARM
I
SYSNC
5
DATA
8
BUFFER
8
I ASIG-ESIG
I
01-08
TEST
SF
SYSTEM
TIMING
I
BUFFER
~RM
~MODE
IMODEc:r-CTRLIN
5-22
SIG
5
TEST
SYCLK
CTRLEN
PY
OE
I
MODE
DGRSEL
-.0
RAM
RAM
WRITE
LSFSY
PARITY
r,-
MODE
AND
EX REG
II
Spring 1988
ALARM~
r--4-o
ALARM
EXERCISES
RPT
I
I
SFOUT
RPTOUT
ALARM
PROCESSOR
(Refer to Section 19 for typical applications of this product.)
Communication ICs
UNITE ISDN Family of Primary.Rate Devices
DS1 Support Circuits
Loop Divider -
41KW
Description
The 41KW Loop Divider integrated circuit is an LSTTL-compatible gate array used
in a phase-locked loop (PLL) to derive, from a system clock, the 1,544 MHz or
3.152 MHz square-wave clock signal for the DS1 or DS1C chip set. The diVISor IS
set by logic for either DS1 or DS1C operation. A 32 kHz clock output provides the
required PLL signal. The loop divider requires a single 5 V supply and is
available in a 16-pin plastiC DIP
Features
• 2-bit and 8-bit counters
• Either 1.544 or 3.152 MHz square-wave clock output
• 32 kHz clock output
Block Diagram
• Standard LSTTL-compatlble inputs and outputs
DIVSEl
INClK
I
I
lPClK
DIVIDER
.;.2
I
ClK3
1
TSVNC
I
.;.2
(Refer to Section 19 for typical applications of this product.)
ClK1
Spring 1988
5·23
Communication ICs
UNITE ISDN Family of Primary.Rate Devices
DS1 Support Circuits
Timing Generator -
129EC
Description
The 129EC Timing Generator integrated circuit is an LSTTL-compatible gate array
that provides the synchronization (sync) and latch pulses required to interface a
DS1 chip set to a PBX or host computer. The timing generator requires a single
5 V supply and is available in a 24-pin plastic DIP
Features
• Provides clock and sync signals needed to interface the DS1 chip set to a PBX or
host com puter
• 9-bit binary counter
• Standard LSTTL -compatible inputs and outputs
• Two separate 8 kHz sync outputs
• Two separate 256 kHz clock outputs
• 4.096 MHz clock output and its Inversion
• 32 and 64 kHz clock outputs for phase-locked loop (PLL) circuit
• 2.048 MHz clock output
Block Diagram
INCLK
INSYNC
I
-
~
-
COUNTER
CLK4
BUFFER
I
DIVIDER
-
9/
'1
INVERTER
GATING
LOGIC
I
I
C~6
I
DLYSEL
ANDIN1
ANDIN2
INVIN
5·24
+------I
H
r
()~
C16 ~---------.
AND
GATE
INVERTER
Spring 1988
I
DIVIDER
CLK2
I CLK41
L XWDCLK
,
I
RWDCLK
RSYNC
TSYNC
CLK32
CLK64
I
r----------------------------------------------•• ANDOUT
II---------------------------------------ii~
INVOUT
(Refer to Section 19 for typical applications of this product.)
Communication ICs
UNITE ISDN Family of Primary-Rate Devices
Synchronous Protocol Data
Formatter with Serial Interface
T7110
-
Description
The T7110 Synchronous Protocol Oata Formatter with Serial Interface (SPYOER-S)
is a synchronous packet data communications controller. It is used to interface
data link level lines using bit-synchronous (HOLC/SOLC) protocols to 16-bit and
32-bit microprocessor systems. All inputs and outputs are TTL-compatible. The
device is fabricated using CMOS technology, requires a single +5 volt power
supply, and is packaged in a 68-pin plastic leaded chip carrier (PLCC).
Features
Host Interface Features
• Compatible with iAPX86, MC68000, or WE® 32100 Microprocessor systems
• On-chip 16-channel OMA memory address generator and buffer management
with a 4 Mbyte/s maximum transfer rate
• Transmit and receive buffers accessible through memory-mapped look-up
elements
Serial Interface Features
• 8-channel multiplexed serial input/output
• Automatic flag transmission and detection
• Zero bit insertion and deletion
• CRC generation and checking
Block Diagram
• 2 Mb/s continuous serial data rate, 4 Mb/s instantaneous data rate
TRANSMITTER
CONTROllER
STO-ST3
TClK
Flag Generator
Bit Stuff
CRC Generator
4-Byte Buffer
TCHSO-TCHS2
TO
,/1..
"
v---
I
ClK
RST
RClK
RD
RCHSO-RCHS2
RCS
----------
(J)
:J
!XI
RECEIVER
Flag Detect
Bit Unstuff
CRC Check
6 Byte Buffer
I
DREO: DREO
DACK: DACK
r-v-'
TCS
TEST
BUS EXEC
DEN
WE:DS
RE:CINIT
AlE:AS
ADDRESS
RAM
DT/R:R/W
ROY: DTACK
..J
~ ---'"
vt--~-V
l~~ I
BHE:FAUlT
INT
STATE
MACHINE
POllER
SA
lOCK
I
(Refer to Section 19 for typical applications of this product.)
I
>A:16-A19
r
,) ADO-AD1S
Spring 1988
5·25
Communication ICs
UNITE ISDN Family of Primary.Rate Devices
Synchronous Protocol
Data Formatter - T71115
Description
The T7115 Synchronous Protocol Data Formatter (SPYDER-T) integrated circuit is a
synchronous packet data communications controller device. All inputs and outputs
of the T7115 SPYDER-T are TTL-compatible. The device is fabricated using CMOS
technology, requires a single 5 V supply, and is available in a 68-pin plastic
leaded chip carrier.
Features
Serial Port Interface
• 32-channel (full-duplex) multiplexed serial input/output supports the T11OS1
24-channel and the CEPT 32-channel modes
• Automatic flag transmission and detection
• Flag stuffing up to 2047 flags
• Flag adjustment for the synchronous rate adaption
• Full, partial, or no CRC generation and checking
• Zero-bit insertion and deletion
• Abort/idle detection and transmission
• Short- and long-frame detection
• 2-Mb/s continuous serial data rate
• Dynamic channel allocation (or channel concatenation) supports DSO, HO, H11,
and H12 channels
• Bit rate control on each channel
• Channel inversion
• Transparent mode (no protocol) supports ECMA 102 and CCITT 1.463 RA2 rate
adaption standards
• Loopback mode
• DMA CRC for relay mode
Microprocessor Interface
• Compatible with 16-bit or 32-bit microprocessor systems
• On-chip 64-channel DMA memory address generator and buffer manager
• Nonmultiplexed 16-bit data and 24-bit address (16 Mbytes) buses
• Transmit and receive buffers accessible through memory-mapped look-up tables
• Interrupt queue (up to 4096 interrupts)
Advanced information - Sample devices are not necessarily available at this time.
5·26
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Communication ICs
UNITE ISDN Family of Primary·Rate Devices
SPYDER·T Block
Diagram
24
RAM
TO
TClK
TlSYN
Tx
SERIAL
I/O
UNIT
(128 x 40)
16
I
TRANSMIT SECTION
~--------------------------RECEIVE SECTION
JlP
I/O
INTERFACE
ADDRESS BUS
(AO-A23)
DATA BUS
(00-015)
RE
WR
DREQ
DACK
RD
RClK
RISYN
RST
Rx
INT
SERIAL
I/O
UNIT
SA
RAM
(128 x 40)
ClK
TEST
Spring 1988
5·27
Communication ICs
Data Protocol
Digital Encryption Processor T7000A
Description
The Digital Encryption Processor (DEP) provides a low-cost, high security cryptographic system for encrypting and decrypting digital signals. It implements the
four data encryption standard (DES) modes specified by the National Bureau of
Standards (NBS) and IS capable of performing multiple encryption operations or
multiplexed key and initial value ciphering.
This programmable device provides a maximum ciphering rate of 235,000 operations/second for any of the DES modes. The DEP IS manufactured using CMOS
technology, requires a single +5 volt supply, and is packaged in a 40-pin plastic
DIP
Features
• Programmable DES ciphering modes
• Programmable multiple or multiplexed ciphenng
• On-chip RAM and ROM
• Separate parallel and/or serial plain-text and cipher-text ports
• Separate serial key input port
• Data throughput of 1.882 Mbytes/s using the entire DES output block
Block Diagram
• Validated by the NBS
CLOCK
,I
INTERNAL
INPUT DATA BUS
ADDRESS
BUS
SERIAL
DATA
PORT
--
CONTROL
--
STATUS
--
KEY
CLOCK
Spring 1988
...
----
DATA
BUS
SERIAL
KEY
DATA
5·28
--
----
-1
:-
I
CONTROLLER
AND
MEMORY
....
MASTER
PORT
CIPHERING
HARDWARE
-
I
~
t
OUTPUT
SHIFT
REGISTER
I
t
t
I"'-- ADDRESS
INPUT
SHIFT
REGISTER
SERIAL
INITIAL
VALUE
AND
KEY
REGISTERS
DATA
I--- PORT
DATA
0-3
PORT
CONFIGUR·
ATION
SLAVE
PORT
f---o
I
I--- BUS
-----
CONTROL
STATUS
INTERNAL
OUTPUT OAT A BUS
KEY
CIRCUITRY
(Refer to Section 19 for typical applications of this product.)
Communication ICs
Data Protocol
Random Number Generator
T7001
Description
The Random Number Generator (RNG) produces random bits based on the
phase jitter of a free-running oscillator, The output data stream of this device is truly random (not pseudorandom), In the data encryption unit, the RNG generates a
random number that can be used as a session key,
This device is fabricated In CMOS technology, requires a single +5 volt supply,
and IS available in a 32-pin plastic DIP
Features
• On-chip or external HF oscillator source option
• On-chip or external jitter oscillator source option
• Generation of a 536-bit random number available in 8-bit bytes
Block Diagram
OSCILLATOR
SELECTS
OSCILLATOR
1/0
CLK
-------
-----
,
• Internal elementary randomness check with external access to generated statistics
OSCILLATOR
CIRCUITRY
-----
PARITY
FILTER
---
DIRECT
ACCESS
REGISTER
BIT
SCRAMBLER
------
r
BUS
COMPARATOR
!
r-110
BUFFER
~
DATA
BUS
~
ADDRESS
TIMING
AND
CONTROL
f---.a CLK
"RUN-UP"
TEST
CIRCUITRY
CONTROL
(Refer to Section 19 for typical applications of this product.)
Spring 1988
5·29
Communication ICs
Data Protocol
Bit Slice Multiplier and Extender T7002 and T7003
Description
The T7002 Bit Slice Multiplier (BSM), designed to be a microprocessor peripheral,
is a cascadable integrated circuit useful in cryptosystem applications. When
cascaded with one or more T7003 BSM Extenders, only the T7002 device interfaces with the host processor. The T7002 BSM can handle 292 multiplication bits
while each cascaded T7003 device increases the bit length by 298 bits. The
rY002 device generates the cascade control signals that drive the T7003 device
control inputs. Each device is manufactured using 1.5 micron CMOS technology,
requires a +5 V supply, and is packaged in a 58-pin plastic leaded chip carrier
(PLCC).
Features
• Useful in public-key cryptosystem applications
• Microprocessor-compatible interface
• Calculates Y = [X x Y] (mod N) and under control of a host processor exponentiates: Y = [Bexp] mod N
• Exponentiation rate: 27 ms for 512-bit operation
• Cascadable device design with 292 bits on a T7002 and 298 bits on a T7003
Block Diagram
• 1.5 micron CMOS design
CASCADE CONTROL
CASCADABLE PINS T0
MOST SIGNIFICANT BITS
CA SCADABLE PINS TO
LEAST SIGNIFICANT BITS
BIT SLICE MULTIPLIER
BIT SLICE PAIRS
TO ADJACENT
DEVICE (LEFT)
12
12/
/
BIT SLICES
MSB
3
LSB
3/
• • •
ALGORITHM
TEST BITS
CASCADE
CONTROL
1~V
1
/
BIT SLICE
ENABLE
BIT SLICE
II CONTROLLER
14L'
/
BIT SLICE PAIRS
TO ADJACENT
DEVICE (RIGHT)
LAST
DATA/STATUS
A REG
DREG
I
MICROPROCESSOR
INTERFACE
2
CS
Spring 1988
8
ADDR
R/W
5·30
3
I
DATABUS
(Refer to Section 19 for typical applications of this product.)
Communication ICs
Data Protocol
X.2S Protocol Controller -
T7100A
Description
The T7100A X.25 Protocol Controller, also known as XPC-8, implements the data
link control functions defined in the X.25 packet switching communication standard for an 8-blt data bus. This level 2 protocol controller is fabricated using
NMOS silicon gate technology, is TIL-compatible, and may be interfaced with an
8-bit microprocessor. The device is available in a 48-pin nonhermetic ceramic DIP
Features
• DMA with standard Interface including OMS request, DMA acknowledge, DMA
read, and DMA write
• Programmable timers and window size
• Serial data rate of 250 kb/s
• Wait-state generator (on DMA side) for slow memory
Block Diagram
• Two independent test modes to verify the XPC-8 and its link
AS
INTERFACE UNIT
R/W
cs
ClK
READY
CKO
ADDRESS
ARITHMETIC
WE
OSRE
READ/WRITE
DATA
SECTION
CONTROL
OMA
LOGIC
UNIT
CONTROL
PARV
LPDREQ
LP[:fACi<:
00-07
DACK
CREa
A6-A15
L -__or______________~--------------_,--_,----------------------_r----~~AO-A5
DATA BUS
XMIT
MEMORY
FIFO
COMMAND,
STATUS.
PARAMETER
REGISTERS
rJ
tJ
TO
INTERRUPT
CONTROL
~---------------------------4~
effi---------------------------4~
~--------------------------~Wffi
CD--------------------------~~
~--------------------------~INTR
~----------------~
(Refer to Section 19 for typical applications of this product.)
Spring 1988
5·31
5·32
Spring 1988
Communication ICs
Data Protocol
X.25/X.75 Protocol Controller
T7102A
-
Description
The T7102A XPC device satisfies the X.25 link layer (level 2) requirements for a
balanced link access procedure (LAPB) for data Interchange over a synchronous
full-duplex, serial data link. This device also implements X.75 level 2 protocol used
in inter-network applications. The protocol controller IS bit-oriented with a maximum transmit and receive speed of 333 kb/s. A set of programmable registers
control and record vital events during data transmission
This single-chip LSI device IS available in a 70-pin, pin-grid array package and is
fabricated using NMOS silicon gate technology.
Features
• 24-bit address bus to address 16-Mbyte address space
• Dual-channel DMA with standard interface including DMA request, DMA
acknowledge, DMA read, and DMA write
• Independently programmable timers, retransmission counter, window size (transmit
and receive), and Modulo 8 or 128 frame sequence numbering
• Daisy chain DMA for priority-controlled CPU interface
• Event counters and registers
Block Diagram
• Supports 8-blt or 16-bit data buses
INTERFACE UNIT
DREQ
lPDREQ
DACK
DBC
PDACK
ADO
R/W
AS
cs
RE
WE
DMA CONTROllER
MEMORY BUFFER
AD1-AD6
AD7-A023
BHE/BlE
MANAGER
PARITY
DATAO-OATA15
READY
MAIN
CONTROLLER
X.25/X 75
TC
RC
~m+-_TD
RD
RTS __- - - - - - - - - j
1 4 - - - - - - - - - - - - SYSClK
CTS ---------~
I------------i~ INTR
C D - - - - - - - - - - - - - - - - - - L -__________~
(Refer to Section 19 for typical applications of this product.)
Spring 1988
5·33
Communication ICs
Codec Products w·Law, A·Law, ±5 Volts)
PCM Codec With Filters -
T7500
Description
The T7500 PCM Codec with Filters integrated circuit performs the analog-to-digltal
and digital-to-analog translation functions In a circuit. It incorporates transmit and
receive filtering of vOice information for transmission via a digital network. The
device is a full-duplex, 8-blt codec that operates from a ±5 volt power supply and
provides A-law and/or wlaw conversion algorithms.
The T7500 codec is synchronized off the positive-going edge and has separate
power-down for the transmitter and receiver. The device is manufactured using
CMOS technology and is available In an 18-pin plastic DIP or in a 20-pin plastic
SOJ. Custom configurations and/or special packages may be available on request.
Features
• AT&T/CCITT compatible
• Pin selectable wlaw or A-Iaw operation
• Pin selectable transmit and receive gain
• Variable data rate (128 kHz to 4.096 MHz)
• On-chip voltage reference
• Low power dissipation
• TTL-compatible inputs and outputs
• AT&T Interface timing
5·34
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Communication ICs
Codec Products IlL·Law, A.Law, ±5 Volts)
T7500 PCM Codec
Block Diagram
~------------------I
ENCODER
TGC
~----......II----l
VFxl
--------.t
FIlter
Network
C-Array'
Ox
L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ -1
PDNx
Blasong
CircUItry
Reference
Voltage
t - - - - I - - BCLK
+-___._- MCLK
L - _......_ _ _ _ _ _
MUSEL
PDNR
Blasong
Circuitry
Reference
Voltage
L----.----t------------+----~~-FS
,-------RGC~-----~_=~l
C-Array'
I
I
DR
ILDECODER
------
• Capacitor Arnrj
•• Successive Approximation Register
Spring 1988
5·35
Communication ICs
Codec Products w·Law, A·Law, ±5 Volts)
PCM Co dec With Filters -
T7513A
Description
The T7513A PCM Codec with Filters is a single-chip integrated circuit that provides analog-to-digital and digital-to-analog conversion. In addition, It provides the
transmit and receive filtering necessary to interface a voice telephone circuit to a
time-division multiplexed system. The T7513A Codec IS a direct replacement for
the T7513 Codec, offering enhanced functionality and significantly reduced power
consumption. The T7513A device is available in a 20-pin plastiC DIP or small
outline J-Iead (SOJ) package for surface mounting.
Features
• Direct replacement for the industry-standard 2913 and 29C13 Codecs
• Low-power, latch up-free CMOS technology
- 65-mW typical operating power dissipation
- 5-mW typical power-down dissipation
• Differential architecture for high nOise immunity and PSRR
• Pin-selectable master clock rates of 2.048, 1.544, or 1.536 MHz
• Two timing modes
- Fixed data rate: 2.048, 1.544, or 1.536 MHz
- Variable data rate: 64 kHz to 2.048 MHz
• On-chip sample and hold, autozero, and precision voltage reference external components required
no
• Excellent nOise performance
• Pin-selectable wlaw or A-Iaw operation
This information is preliminary and subject to change.
5·36
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Communication ICs
Codec Products lit-Law, A-Law, ±S Volts)
T7513A PCM Codec
Block Diagram
~~OoER----------------l
GSx
VFxlP
VFxlN
I
I
-'"
J
FILTER
NETWORK
I
BIASING
CIRCUITRY
,
REFERENCE
VOLTAGE
**
C-ARRAY
L_
~
--
l
H
AUTO
ZERO
l
J
I
I
I
I
COMPARATOR
AID
CONTROL
LOGIC
-----J---
SAR*
-j-
POWER
DOWN
CONTROL
t
REFERENCE
VOLTAGE
BIASING
CIRCUITRY
I
GSR
GAIN
CONTROL
II
I
I
-
I
I
I
_I~
I
I
Fll,,"
NETWORK
Dx
DCLKx/TSxB
FSx
DCLKR
PDN
I
I
r-- - - - - - - - - - - - -
PWRON
PARALLEL
TO SERIAL
LOGIC
I
_ _ _ _ -.JI
ASEL
PWROP
I
I
I
I
I
j
I
I
I
I
I
SAMPL~r& HOLD
~~~~~
**
C-ARRAY
H
-
D/A
-
CONTROL
LOGIC
MCLK
CLKSEL
FSR
---,
II
I
I
I
I
I
I
______________ J
IISERIAL
T0j-PARALLEL
' - DR
LOGIC
I
* SUCCESSIVE APPROXIMATION REGISTER
* * CAPACITOR ARRAY
Spring 1988
5-37
Communication ICs
Codec Products (wLaw, A.Law, 5 Volts)
Dual PCM Codec
With Filters - T7512
Description
The AT&T T7512 Dual PCM Codec With Filters integrated circuit provides two
channels of analog-to-digital and digital-to-analog conversion as well as the
transmit and receive filtering necessary to interface two vOice telephone circuits to
a time-division multiplexed system. The device is fabricated uSing low-power
CMOS technology and requires a single +5 volt supply. It is available in either a
28-pin plastic DIP or 28-pin plastic SOJ package for surface mounting.
Features
• AT&T/CCITT-compatible
• Pin selectable wlaw or A-Iaw operation
• Transmit and receive gain control with external resistors
• Two timing modes
- Fixed data rate mode at 2.048 MHz
- Variable data rate mode - 128 kHz to 2.048 MHz
• On-chip voltage reference
• Differential output amplifier
• TTL-compatible I/O
This information is preliminary and subject to change.
5·38
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Communication ICs
Codec Products (p.-Law, A-Law, 5 Volts)
T7512 Dual PCM
Codec Block Diagram
TIP1
TIN1
TGS1
I
:1
E.6
DOUBLE
LOOP
I
I
I
BANDPASS
FILTER
DECIMATOR
f
I
ILfA LAW
COMPRESSOR
AND TDM
SERIAL
INPUT
PORT
J
i
r
CONTROL
AND
TIMING
ROP1
RON1
RGS1
ROP2
RON2
RGS2
MCLK
TIP2
TIN2
TGS2
I~
I
I~
I
I
r--
•
RECONSTRUCTION
FILTER
I-
•
DIGITAL
[.6
fe-
•
LOWPASS
FILTER
GAIN
CONTROL
I
I--
RECONSTRUCTION
FILTER
GAIN
CONTROL
Ij)
1--
I
1
L.6
fe-
f
•f
'
•
L:6
1
-1
DECIMATOR
1
BANDPASS
FILTER
~
RFS1
~ TPCM
....... I
p./A LAW
EXPANDOR
AND TDM
SERIAL
OUTPUT
PORT
I------
T
I
I
J
I
I
TFS1
1--+-
I
CONTROL
AND
TIMING
DOUBLE
LOOP
I
DIGITAL
I-
LOWPASS
FILTER
-
p./A LAW
EXPANDOR
AND TDM
SERIAL
OUTPUT
PORT
I
RPCM
DCLK
ASELN
RFS2
TFS2
p./A LAW
COMPRESSOR
~
AND TDM
SERIAL
INPUT
PORT
Spring 1988
5-39
Communication ICs
Codec Products (Linear, High.Precision, ±5 Volts)
High.Precision PCM Codec With
Filters - T7520A
Description
The T7520A High-Precision PCM Codec With Filters integrated circuit performs
AID and DIA conversion with 15-bit resolution and 10-bit linearity. Anti-aliasing and
reconstruction filters are provided on-chip, as well as precision voltage references.
The device is designed for use in signal-processing applications that require PCM
data with a higher resolution than PCM wlaw data. The T7520A Codec is a linear
device with 16-blt PCM 1/0 data in 2's complement binary format. Typical applications include the use of this codec with echo cancelers, digital signal processors,
and in data sets. The T7520 Codec is manufactured using CMOS technology and
is available in a 24-pin hermetic, ceramic DIP
Features
• Encoder and decoder with on-chip filters
• On-chip precIsion-trimmed reference voltages
• Charge redistribution and switched capacitor techniques
• ±5 V power supplies, with 120 mW nominal power
• Independent transmit and receive power-down
• Easy interface to a DSP device
• Sync deglltching circuitry on-chip
• 3-state TTL -output bus
• Data format: 16-bit PCM In 2's complement binary (LSB first)
• Gain selection -
transmit: 0 or -3 dB
receive: +3 or 0 dB
• Guaranteed monotonic to 15 bits
• Balanced filters for improved PSRR
5·40
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Communication ICs
Codec Products (Linear, High.Precision, ±S Volts)
T7520A PCM Codec
Block Diagram
TGC
TFIN
I
TDIS
I
T2048
TNSYNC
R:::
R2048
I
I
300Hz-3 kHz
BAND PASS
FILTER
1
TPCM
AID
CONVERTER
1 - - - -.......... RFOUT
~I!-------4~
II
,------4-L_____s----0-3 kHz
LOW PASS
FILTER
VOP
1 VON
D/A
RNSYNC - - - - - . t
RDiS
CONVERTER
I
Spring 1988
5·41
Communication ICs
Codec Products (Linear, High.Precision, ±5 Volts)
High·Precision PCM Codec T7521A
Description
The T7521A High-Precision PCM Codec integrated circuit performs AID and DIA
conversion with 15-bit resolution and 10-bit linearity. The device provides an onchip reconstruction filter and a precision voltage reference. The device is designed for use in signal-processing applications that require PCM data with a
higher resolution than PCM wlaw data. The T7521A Codec is a linear device with
16-bit PCM 1/0 data in 2's complement binary format. Typical applications include
the use of this codec with echo cancelers, digital signal processors, and in data
sets. An optional transmit filter may be supplied by the user for this device. The
T7521A Codec is manufactured using CMOS technology and is available in a
24-pin hermetic, ceramic DIP.
Features
• AID and DIA with on-chip D/A filters
• On-chip precision-trimmed reference voltages
• Charge redistribution and switched capacitor techniques
• ±5 V power supplies, with 100 mW nominal power
• Independent transmit and receive power-down
• Easy interface to a DSP device
• Sync deglitching circuitry on-chip
• 3-state TTL -output bus
• Data format: 16-bit PCM in 2's complement binary (LSB first)
• Gain selection -
receive: +3 or 0 dB
• Guaranteed monotonic to 15 bits
• Balanced filters for improved PSRR
• AID filters can be bypassed; AID has sample and hold built in
5·42
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Communication ICs
Codec Products (Linear, Hlgh.Precision, ±S Volts)
T7521A High·
Precision PCM Codec
Block Diagram
TPCM
TFIN
T2048
AID
TNSYNC
I
TOIS
1
CONVERTER
RGC
0-3kHz
RPCM
RFOUT
~---"-:I
VOP
r-----<~-----j-------;
VON
LOW PASS
FILTER
I
I
R2048 ;,...----...-f
RNSy'NC
RDI.
I;,...-___...-f
DIA
CONVERTER
I
Spring 1988
5·43
Communication ICs
Codec Products (Unear, High.Precision, ±S Volts)
High·Precision PCM Codecs With
Filters - T7522 and T7523
Description
The T7522 and T7523 High-Precision PCM Codecs With Filters integrated circuits
perform A/D and D/A conversion with 15-bit resolution and 10-bit linearity. The
devices are designed for use in signal-processing applications that require PCM
data with a higher resolution than PCM wlaw data. Each codec is a linear device
with 16-bit PCM I/O data in 2's complement binary format. Typical applications include the use of the codec with echo cancelers, digital signal processors, and in
data sets. Each codec is manufactured using CMOS technology and is available
in a 24-pin, hermetic ceramic DIP
The T7522 Codec provides anti-aliasing and reconstruction filters and a precision
voltage reference. The chip has selectable LSB or MSB first I/O. The T7522 device
can directly replace the T7520A and T7521A Codecs in applications not requinng
independent AID and D/A power-down options, and is recommended for all new
designs
Designs requiring the independent AID and D/A power-down option should use
the T7523 Codec. The T7523 device is a pin-for-pin replacement and upgrade for
the T7520A and T7521A Codecs, and is recommended as their replacement for
all new designs. However, applications requiring MSB first PCM I/O should use
the T7522 Codec.
Features
• Encoder and decoder with on-chip filters
• On-chip precision-trimmed reference voltages
• Charge redistribution and switched capacitor techniques
• ±5 V power supplies, with 120 mW nominal power
• Easy interface to industry-standard DSP devices
• Independent transmit and receive power-down (T7523)
• Sync deglitching circuitry on-chip
• 3-state TTL -output bus
• Data format 16-bit PCM in 2's complement binary LSB first I/O (T7523)
• Selectable LSB or MSB first I/O (T7522)
• Gain selection: transmit: 0 or -3 dB
receive: +3 or 0 dB
• Guaranteed monotonic to 15 bits
• Balanced filters for improved power supply rejection ratio (PSRR)
• AID has sample and hold built-in
5·44
Spring 1988
• AID filters can be bypassed
(Refer to Section 19 for typical applications of this product.)
Communication ICs
Codec Products (Linear, High.Precision, ±5 Volts)
T7522 Block Diagram
TGC
TFIN
T2048
TNSYNC
IOF
DIS
R2048
I
~r--
•
--.
SWITCHED
CAPACITOR
300 Hz-3 kHz
BAND-PASS
FILTER
--.
,1
r---
MUX
.... ' - - - - -
r-AID
TPCM
CONVERTER
WITH SAMPLE
AND HOLD
BUILT IN
I
I
I
T
I
~
I
RPCM
I
I
RGC
I
RNSYNC
2ND ORDER
RC
LOW-PASS
FILTER
(20 kHz)
~
f--
DIA
CONVERTER
SWITCHED
CAPACITOR
0-3 kHz
LOW-PASS
FILTER WITH
SIN X
-X
CORRECTION
DIFFERENTIAL TO
SINGLE-ENDED
BUFFER
1
r-r--
i
2ND ORDER
RC
LOW-PASS
FILTER
(20 kHz)
~ RFOUT
VOP
I VON
T
I
T7523 Block Diagram
•
TGC
TFIN ~r--
2ND ORDER
RC
LOW-PASS
FILTER
(20 kHz)
f--
r---
SWITCHED
CAPACITOR
300 HZ-3 kHz
BAND-PASS
FILTER
~
FILTER CLOCKS
T2048
TNSYNC
TDIS
TPCM
AID
CONVERTER
WITH SAMPLE
AND HOLD
BUILT IN
I
I
RDIS----------------------~------------~~----------__,
DIFFERENTIAL TO
SINGLE-ENDED
BUFFER
RFOUT
RPCM~--------------~
R2048----------------~
DIA
~----~~--+-------~VOP
CONVERTER
RNSYNC----------------~
~----------+-------~VON
RGC~--------------------------------~
Spring 1988
5·45
Communication ICs
Codec Products (Unear, High.Precision, ±5 Volts)
High.Precision PCM Codec
With Filters - T7525
Description
The AT&T T7525 integrated circuit is a high-precision voiceband sigma-delta PCM
codec with transmit and receive filters. It provides 15-bit resolution and 10-bit
linearity. The serial PCM input/output uses a linear 16-bit 2's complement data format. The device can input or output 16-bit data 16 bits at a time (word mode), or
optionally 8 bits at a time (byte mode) to allow easy interfacing to digital signal
processor devices with 8-bit input/output. The transmit and receive digital filters
can be bypassed, which is useful for echo canceling applications. The T7525
Codec is fabricated using a low-power CMOS technology, operates from a single
+5 volt supply, and is available in either a 24-pin plastic DIP package or in a
28-pin plastic SOJ package.
Features
• Easy interface to AT&T and Tl family DSPs
• Pin-selectable MSB/LSB first
• Transmit/receive gain control with external resistors
• Two timing modes
- fixed data rate mode: 2.048 MHz
- variable data rate mode: 128 kHz to 2.048 MHz
• Filters may be optionally bypassed
• On-chip voltage reference
• Differential output amplifier
• TTL-compatible digital I/O
• Two input/output modes -
byte and word
This information is preliminary and subject to change.
5-46
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Communication ICs
Codec Products (Linear, High.Precision, ±S Volts)
T7525 High.Precision
PCM Codec With
Filters Block Diagram
VRE:t>r
TIN
DOUBLE
LOOP L:~
TGS
i
-!
DECIMATOR
.....
HIGH
PASS
FILTER
L
TFS
TOM
SERIAL
PORT
f------
!
i
CONTROL
AND
TIMING
MCLK
<+
ROP
RON
RGS
-i
LOW
PASS
FILTER
~
I
SMOOTH
FILTER
SAMPLED
DATA
FILTER
W
1:
~
J
GAIN
lCONTROL
i
GNDAl
i
GNDA2
i
VOOA
I-
-
~
DIGITAL
L:~
i
GNDD
~
~
LOW
PASS
FILTER
---
1--<>-
ATFS
TPCM
TESTI
TESTAN
TESTBN
TSTSTB
DCLK
BYPN
MSB
TOM
SERIAL
PORT
RFS
ARFS
RPCM
i
VOOO
Spring 1988
5·47
Communication ICs
Clock Recovery Circuit -
T7032
Description
The T7032 Clock Recovery Circuit integrated circuit operates over a 1 to 50 MHz
frequency range and provides clock recovery, data retiming, and a polynomialbased descrambler. The descrambler may be disabled for those applications
where no data scrambler is used. The device accepts TTL nonreturn-to-zero (NRZ)
data from a receiver (optical or electrical), recovers the clock, and retimes the
data to the recovered clock. The inputs and outputs are TTL-compatible, and the
circuit requires a single +5 V supply. The T7032 Clock Recovery Circuit is
manufactured using CMOS technology and is available in a 300 mil, 20-pin plastic
DIP.
Features
• Pin-programmable for 1 to 50 MHz operation
• Fiber and wire applications
• Compatible with the OOL ® 50 Lightwave Data Link
• Single-chip CMOS design
Block Diagram
DIN
LDIN
LSEL
FREQUENCY {MO_M2
SELECT
LO-L2
PINS
N
• Single +5 V supply
I
I
INPUT
MUX
I
3/
I
3
I
,.
CLOCK
RECOVERY
CIRCUIT
REFERENCE
VOLTAGE
EXTERNAL [XC1
CRYSTAL
XC2
5·48
RETIMED
DATA
INPUT DATA
I
Spring 1988
CLKOUT
DOUT
RETIMER
CIRCUIT
DESCRAMBLER
CIRCUIT
-
OUTPUT
MUX
DATA
SELECT
I
DSCR
CLKOUT
REGULATOR
CIRCUIT
(Refer to Section 19 for typical applications of this product.)
Communication ICs
Clock Recovery Circuit -
T7033
Description
The T7033 Clock Recovery Circuit integrated circuit operates over a 1 to 50 MHz
frequency range and provides clock recovery and data retiming. The device
accepts TTL -NRZ data from a receiver (optical or electrical), recovers the clock,
and retimes the data to the recovered clock. The inputs and outputs are TTLcompatible, and the circuit requires a single +5 V supply. The T7033 Clock
Recovery Circuit is manufactured using CMOS technology and is available in a
300 mil, 20-pin plastic DIP This circuit may be used for many general-purpose
clock recovery and retiming applications. The device is intended for applications
where a data scrambler is not used.
Features
• Pin-programmable for 1 to 50 MHz operation
• Fiber and wire applications
• Single +5 V supply
Block Diagram
DIN
LOIN
LSEL
MO-M2
LO-L2
N
I
I
I
I
I
• Only one external component required: 3.58 MHz crystal
RETIMED
DATA
INPUT DATA
-
INPUT
MUX
DOUT
RETIMER
CIRCUIT
3
/
3
CLOCK
RECOVERY
CIRCUIT
CLKOUT
CLKOUT
,
REFERENCE
VOLTAGE
EXTERNAL (xC1
CRYSTAL L:C2
I
REGULATOR
CIRCUIT
I
(Refer to Section 19 for typical applications of this product.)
Spnng 1988
5-49
Communication ICs
Clock Recovery Circuit -
T7034
Description
The T7034 Clock Recovery Circuit integrated circuit operates over a 25 MHz to
50 MHz frequency range and provides clock recovery and data retiming. The
device accepts TTL-NRZ data from a receiver (optical or electrical), recovers the
clock, and retimes the data to the recovered clock. The inputs and outputs are
TTL-compatible and the circuit requires a single +5 V supply. The Tl034 Clock
Recovery Circuit is manufactured using CMOS technology and is available in a
300 mil, 20-pin plastic DIP. The device is designed for general-purpose clock
recovery and retiming applications.
Features
• Pin-programmable for 25 MHz to 50 MHz operation
• Fiber and wire applications
• Single +5 V supply
Block Diagram
• Only one external component required: 3.58 MHz crystal
INPUT
DATA
RETIMED
DATA
DIN
,.----.
LO-L2
3/
I
N
CLOCK
RECOVERY
CIRCUIT
CLKOUT
DOUT
RETIMER
CIRCUIT
CLKOUT
REFERENCE
VOLTAGE
EXTERNAL
CRYSTAL
[XC1
XC2 I
REGULATOR
CIRCUIT
I
This information is preliminary and subject to change.
5-50
Spring 1988
(Refer to Section 19 for typical applications of this product.)
6
Digital Bipolar Integrated Circuits
The Digital Bipolar product family is made up of
four basic process technologies: Guardring
Isolated Monolithic Integrated Circuits (GIMIC),
Standard Buried Collector
(SBC), Oxide-Isolated
logic (OXll), and ScaledFast Oxide-Isolated logic
(SFOXll).
There are three major
product offerings available
in the Digital Bipolar product family. These are
custom, semi-custom, and
catalog logic devices.
Custom logic devices
include all devices
designed to satisfy a
unique systems application. They are designed
from the gate level to
minimize chip size and
maximize performance.
Semi-custom designs
include gate arrays and
functional logic array circuits that are designed
and manufactured to provide fast turnaround, low
risk, and low development
expense. Catalog logic
devices are used as
building blocks in the
design of digital systems.
Page
Quad Differential Line Receiver Quad Differential Line Driver -
41LF
41LG
6·2
6·3
* Dual Differential Line Driver·Receiver
~B-~~~~~~
~
8 x8 Bipolar Bilateral Crosspoint Array 129EH·P
6·6
Bipolar OXIL Gate Arrays -
6·7
LS2000
Bipolar OXIL Gate Arrays TE1000, TE2000, TE3000
6·8
* ATE·Series Digital Bipolar Gate Arrays
6·9
For additional infor·
mation contact your
nearest sales office
or call:
1-800-372-2447.
* Did not appear in the previous edition of the Product Selection Guide.
Spring 1988
6·1
Digital Bipolar ICs
Quad Differential Line Receiver
41LF
-
Description
The 41 IF Quad Differential line Receiver integrated circuit is a quad differential input to TIL output line receiver. This OXll technology device contains four receiver
clusters and enable circuitry. The average propagation delay IS 4 ns, and the
common mode operating range IS ±4 V The 41lF line receiver is pin-equivalent
to the general-trade AM26lS32 device, but has Improved speed and decreased
power consumption.
The quad differential line receiver is available in a 16-pin plastic DIP (41lF), a
16-pln SOJ (1041 IF), and a 16-pin SOIC-GW (1141 IF).
Features
• Single +5 V supply
• 0 to 850C operating temperature
• Four line receivers per package
• Complementary inputs for each line receiver
• 250 mW maximum power dissipation
• 7 ns maximum propagation delay
• 0.20 V Input sensitivity
Logic Diagram
6-2
• ±4 V common mode rejection
INPUT A (AI)
INPUT A (AI)
>---0 OUTPUT A (AD)
INPUT B (BI)
INPUT B (BI)
OUTPUT B (BO)
INPUT C (CI)
INPUT C (CI)
OUTPUT C (CO)
INPUT D (Dr)
INPUT 0 (01)
OUTPUT 0 (DO)
ENABLE (E)
--0
Vee
ENABLE (E)
--0
GND
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Digital Bipolar ICs
Quad Differential Line Driver
41LG
Description
The 41 lG Quad Differential line Driver Integrated circuit transmits digital data over
balanced transmission lines. It translates Input TTL logic levels to ECl-llke output
levels that directly drive the line. This OXI l technology device IS pin-equivalent to
the general-trade 26lS31 device; however, it has decreased power consumption
and generates lower levels of electromagnetic interference (EM I). By having four
dnvers in one 41 LG device, circuit board package count is reduced. All four line
drivers in the device have common enable and disable functions. The 41 lG line
driver is compatible with many line receivers including the AT&T 41LF and 858B
HIC (built-In terminations) devices, and the general-trade AM26LS32 device.
The quad differential line driver is available in a 16-pin plastic DIP (41LG), a 16-pin
SOJ (1041lG), and a 16-pin SOIC-GW (1141LG).
Features
• 100 mA minimum output short-circuit
current
• Single +5 V supply
• Four line drivers per package
• Complementary outputs from each
line driver
• No line loading when Vec
0
• High output drive for 50
OUTPUT
• 6 ns maximum propagation delay
• 0.2 ns output skew, tYPical
• 0 to 85°C operating temperature
• 40 mA dnve capability
Logic Diagram
• 300 mW maximum power dissipation
n lines
A (Mil
OUTPUT A (AO I
OUTPUT
B (ill I
OUTPUT 8 (80 I
OUTPUT
C (COl
OUTPUT C (CO I
OUTPUT jj (Dill
OUTPUT 0 (00 I
---0
Vee
---0
GND
(Refer to Section 19 for typical applications of this product.)
Spring 1988
6-3
Digital Bipolar ICs
Dual Differential Line DriverReceiver Pairs - 41LK, 41LL,
and 41LM
Description
The 41 LK, 41 LL, and 41 LM devices are dual differential line driver-receiver pairs
that are compatible with the 41LF Receiver and 41 LG Driver devices. These dual
pair devices consist of two line receivers with differential ECl -to-TTL converters,
two line drivers with TTL-to-differential ECl converters, and individual 3-state
enabling circuitry for the driver and receiver pairs. This allows serial data and a
control clock to be transmitted and received on a single integrated circuit. The
typical propagation delays for the driver and receiver of these OXIL-technology
devices are 3.0 ns and 4.0 ns, respectively.
The 41 LK device is intended for use where the minimization of electromagnetic
interference is required, and it has characteristics similar to those of the 41 LG and
41 LF devices. The 41 LL device has internal 200 0 discharge resistors added on
each driver output and is equivalent to the NSC DS8923A. The 41 LM device has
internal resistor terminations for both the driver (200 0) and receiver (100 0),
eliminating the need for external resistors, and is intended for use with 100 0
impedance (Z) twisted-pair or flat cable.
The dual differential line driver-receiver pairs are available in a 16-pin plastic DIP
(41LK, 41LL, and 41LM), SOJ (1041LK, 1041ll, and 1041LM), or SOIC-GW
(1141lK, 1141ll, and 1141lM).
Driver Features
Receiver Features
• Two line drivers per package
• Two line receivers per package
• Complementary outputs from each
line driver
• Complementary inputs for each line
receiver
• Maximum propagation delay 6 ns
• Maximum propagation delay 7 ns
• No line loading when Vee = 0 V
• 0.20 V input sensitivity
• Minimum output short-circuit current
100 mA
• Common mode rejection ±4 V
• Output skew 0.2 ns, typical
• Single 5 V supply
• 0 to 850C operating temperature
• Single 5 V supply
• 0 to 850C operating temperature
This information is preliminary and subject to change.
6·4
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Digital Bipolar ICs
Dual Differential Line Driver·Receiver Pairs 41LK, 41LL, and 41LM
Pin Function Diagrams
R11+
R11+
R11-
R11-
001+
001+
001+
001-
001-
001-
002-
002-
002-
002+
R12-
41LK
1041LK
1141LK
R12-
41LL
1041LL
1141LL
GNO
012
41LM
1041LM
1141LM
Spring 1988
6·5
Digital Bipolar ICs
8 X 8 Bipolar Bilateral
Crosspoint Array - 129EH·P
Description
The 129EH-P 8 x 8 Bipolar Bilateral Crosspoint (B2X) Array integrated circuit is a
high-density, high-performance, bipolar space division switch, It is organized as an
8 x 8 crosspoint array, with crosspoints consisting of 64 symmetrical, lateral
P+NP+ transistors, Each crosspoint is a nearly ideal switch, capable of conducting current in both directions with an insertion impedance of less than 20 fl, The
on-board I2L control and interface logic is TTL-compatible, The 129EH-P B2X
device is available in a 24-pln molded plastic DIP
Features
< -90 dB @ 3 kHz, 900 fl
• Off isolation < -90 dB @ 3 kHz, 900 fl
• Crosspoint-on resistance: 7 n ::5 RON ::5 20 fl
• Crosstalk
• Crosspoint signal bandwidth> 5 MHz
• Power dissipation
Simplified Block
Diagram
<
100 mW, all crosspoints off
• TTL-compatible
YO
DIN
CLK
SE
~
INPUT
SHIFT ~
REGISTER
DLX1
DLX2
)(B
WHER E:
DE IS DECODER ENABLE
LE IS LATCH ENABLE
SC LK IS SHIFT CLOCK
Spring 1988
Y3
Y4 Y5
Y6
Y7
vi
H;I'v /, I'v /, I'v /, I'v /, I'v /, I'v /, I'v /, 1'1
v , v , v , v , v , v , v , vI
X AND Y
I' / I' / I' / I' / I' / I' / I' / 1'1
H>
ADDRESS
DECODER ~
vI
H>I'v /"-I'v /, I'v "-/ I'v /, I'v "" I'v "" I'v "" 1'1
f---4 )I'v /, I' / I' / I' / I' " I' " I' " 1'1
CROSSPOINT
LATCHES
H;I"v /, I"v /, I"v ,/ I"v ,/ I"v "" I"v /, I"v /, I"vII
"- v , v , v , vI
LE
/ I' / I' / I' / I' / I'J
H>I'v /, I'v ,/ I'v "-v
H;I"v "/ I"v /, I"v /, I"v /, I"v "/ I"v /, I"v /, I"vII
H 'v
'v 'v 'v 'v 'v 'v 'v I
/1"/1"/1"/1"/1"/1"/1"/1"1
1/ , 1/ , 1/ , 1/
64
:)
6·6
DE
Y1 Y2
1/
1/
1/
XO
X1
X2
X3
X4
X5
X6
X7
(Refer to Section 19 for typical applications of this product.)
Digital Bipolar ICs
Bipolar OXIL Gate Arrays -
LS2000
Description
The lS2000 high-speed gate array is designed using advanced oxide-isolated
(OXll) bipolar technology. It is compatible with the TTl-ECl series of customized
gate arrays. The internal logic gates are built of stacked ECLlEFl gates, and the
buffers are lS240 compatible.
Product Features
• Internal clock frequency of 200 MHz
• Internal gate delay of 0.9 ns, typical
• Fast turnaround time: 8 weeks from T = 0
• Schottky-compatible 1/0
• Highly Integrated SSI/MSI macro library
CAD Features
• Schematic capture
• Multiple delay logic simulation
• Automatic placement and routing
• Design verification
• Test program generation
Product Matrix
Series
Maximum
No. of
Equivalent Gates
lS2000
2000
Total No. Inputs,
Outputs,
Input/Outputs
84 (84 outputs)
(Refer to Section 19 for typical applications of this product.)
Package Type
68-pin surface-mount
chip carrier;
70-pin PGA;
104-pin PGA
Spring 1988
6·7
Digital Bipolar ICs
Bipolar OXIL Gate Arrays -
TE1000,TE2000,TE3000
Description
The customized high-speed TTl-ECl gate array family IS designed using advanced oxide-isolated (OXll) bipolar technology. The internal logic gates are built
of stacked ECLIEFl gates, and the buffers are a mixture of ECl and TTL for optimum speed/power combinations. The ECl outputs are capable of driving
50-ohm loads. The array is ECl 10K, ECl 10KH, and Schottky TTL compatible.
Product Features
• Internal clock frequency of 200 MHz
• Internal gate delay of 0.9 ns, typical
• All ECl outputs drive 50-ohm loads
• Fast turnaround time: 8 weeks from T
=
0
• Available mixture of ECl and TTL I/O
• Highly integrated SSI/MSI macro library
CAD Features
• Schematic capture
• Multiple delay logic simulation
• Automatic placement and routing
• Design verification
• Test program generation
Product Matrix
6·8
Spring 1988
Series
Maximum
No. of
Equivalent Gates
Total No. Inputs,
Outputs,
Input/Outputs
TE1000
1000
96 (48 outputs)
68-pin chip carrier;
68-pin plastic
multilayer chip carrier
TE2000
2000
84 (84 outputs)
100-pin surface-mount
leaded ceramic chip carrier;
104-pin PGA
TE3000
3000
168 (84 outputs)
Package Type
149-pin PGA
(Refer to Section 19 for typical applications of this product.)
Digital Bipolar ICs
ATE·Series Digital Bipolar
Gate Arrays
Description
AT&T's advanced high-speed TTL-Eel gate arrays are deSigned using Scaled-Fast
Oxide-Isolated logiC (SFOXll) bipolar technology which offers higher operating
speeds. The new gate arrays are the ATE6000, ATE3000, and ATE1000 and will
be available In the 2088, 3088, and 3088, respectively.
Product Features
• Eel outputs that drive 50 Q loads
• Several Internal speed and power
options available:
• Fast turnaround time of 6 weeks from
Speed
Power
500 ps
1.25 mW/gate
300 ps
2.5 mW/gate
200 ps
5.0 mW/gate
• Internal clock frequency of
500-800 MHz
• Eel and TTL buffers for optimum
speed/power combinations:
Eel buffer input: 300 ps
Eel buffer output: 600 ps
t
=
0
• Eel and TTL input/outputs available
• Highly integrated SSI/MSI macro
library available
CAD Features
• SchematiC capture
• Multiple-delay logiC Simulation
• Automatic placement and routing
• Design verification
• Test program generation
TTL buffer Input: 500 ps
TTL buffer output: 2400 ps
Product Matrix
Gate
Array
Code
Maximum No. of
Equivalent Gates
Total No. of
Inputs, Outputs,
and Input/Outputs
Package Type
ATE1000
1000
To be determined
To be determined
ATE3000
3000
To be determined
To be determined
ATE6000
6000
120
149-pin PGA
This mformation is preliminary and subject to change.
(Refer to Section 19 for typical applications of this product.)
Spring 1988
6-9
7
Digital Signal Processors (DSPs)
With both fixed-point and
floating-point DSPs, AT&T
has the single-chip solution. Each digital signal
processor is fully supported with software and
hardware development
tools.
The DSP16 and DSP16A
are 16-bit fixed-point processors that perform a
16x16 bit multiplication
and 36-bit accumulation
in a single instruction cycle. Executing 30 million
instructions per second,
the new DSP16A has
nearly twice the throughput of the DSP16 and
twice the ROM, and four
times the RAM on-chip.
Page
WE® DSP16 Digital Signal Processor
(Fixed Poi nt)
7-2
* WE DSP16A Digital Signal Processor
(Fixed Poi nt)
7-5
WE DSP32 Digital Signal Processor
(Floating Point)
7·8
WE DSP32C Digital Signal Processor
(Floating Point)
7·11
The DSP32 and DSP32C
are 32-bit floating-point
processors targeted for
high-end applications.
Performing up to 25
million floating-point
operations per second,
the new DSP32C offers
full upward compatibility
with the DSP32 and can
address up to 16 Mbytes
of external memory. An
optimizing C language
compiler for the DSP32
and DSP32C is available.
For additional information contact your
nearest sales office
or call:
1-800-372-2447.
• Did not appear in the previous edition of the Product Selection Guide.
Spnng 1988
7-1
Digital Signal Processors
WE DSP16 Digital Signal
Processor (Fixed Point)
Description
The WE DSP16 Digital Signal Processor is a 16-bit fixed-point, high-performance,
low-power CMOS integrated circuit. It can be programmed for a variety of fixedpOint/Integer applications.
There are three internal processing units, two for memory addressing and one for
data operations. The addressing units support high-speed register-indirect memory
addressing with post-modification of the register using associated increment
registers or fixed increments. The data arithmetic unit (DAU) contains a 16 x
16-bit multiplier, whose product can be accumulated into one of two 36-bit
accumulators. 16- or 32-blt ALU instructions are supported along with conditional
branches and subroutine calls. The DSP16 also features a 15-word instruction
cache for high-speed, ROM-efficient vector operations.
WE DSP16 Digital Signal
Processor 84.pin Plastic
Leaded Chip Carrier
On-chip memory includes 2048 words of mask-programmable ROM and 512
words of RAM. Up to 64K words of external ROM may be used in place of the
internal ROM.
Interfacing is supported with serial/parallel I/O ports and interrupts. The serial port
is compatible with a wide variety of serial devices including TOM codecs and
other DSP16 chips for multiprocessing. The parallel I/O port uses a 16-bit bus,
interfacing to other DSP16 devices or peripheral devices, with data rates of up to
18.2 Mbytes/s. A mixture of hardware and software interrupts gives a high degree
of interface flexibility.
Features
• Low-power 1 p1TI 2-level metal CMOS
technology
• 16-bit fixed-point arithmetic
WE DSP16 Digital Signal
Processor 13 x 13 Ceramic
PGA Package
• 55 and 75 ns versions available
• Military version (MIL-STO-883C) in
13 x 13 ceramic PGA package
available 3088
• Single cycle multiply/accumulate
• Two 36-bit accumulators
• 15-word instruction cache
• 2K-word on-chip ROM
• 512-word on-chip RAM
• 64K-word off-chip ROM expansion
• Serial and parallel I/O ports
• Multiprocessor capability
• Maskable interrupts
• UNIX® Systems, MS-OOS~ and
VMS" Software support
• Development system
• Registered trademark of Microsoft Corporation
•• Registered trademark of Digital Equipment Corporation
7·2
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Digital Signal Processors
WE DSP16 Digital Signal Processor
Software Development
Software development tools to create, test, and debug DSP16 application programs are available to run under the UNIX Operating System, and MS-OOS and
VMS Operating Systems.
The assembler source is similar to the C language, with the usual features of
labels, symbols, comments, etc. The DSP16 simulator provides full program
debugging by allowing access to all registers and memory. Conditional breakpoints are supported along with user-defined functions and variables.
Hardware Development
Application system hardware development and real-time software testing is supported by the WE DSP16-DS Digital Signal Processor Development System. Incircuit emulation is provided and up to 16 development systems can be cascaded
for multiprocessor applications.
WE DSP18·DS Digital Signal
Processor Development
System
Product Matrix
Type
Description
Devices
WE-DSP16-M02-075
WE-DSP16-M02-055
WE-DSP16-R02-075
WE-DSP16-R02-055
84-PIn PLCC (Plastic, Leaded), 75 ns 1,2
84-Pin PLCC, 55 ns 1,2
13 x 13 PGA (Pin Grid Array), 75 ns 1,2
13 x 13 PGA, 55 ns 1,2
Software Library Versions
WE-DSP16-SL-UN5VX-T
WE-DSP16-SL-UN5B2-F
WE-DSP16-SL-MSDOS-F
WE-DSP16-SL-VMS-T
WE-DSP16-SL-BKSU N-C
WE-DSP16-SL-UNB4N
UNIX System V (VAX 11/780 Series)
UNIX System V (3B2 Series)
MS-OOS (AT&T PC6300 and Compatibles)
VMS (VAX 11/780 Series)
UNIX System Berkeley 4.2 (Sun Series)
UNIX System Berkeley 4.2 (VAX 11/780 Series)
Development Systems
WE-DSP16-DS
WE-DSP16-DS-055
Development System, 75 ns
Development System, 55 ns
1
2
Custom ROM versions are available.
Secure ROM versions are available.
Spring 1988
7·3
Digital Signal Processors
WE DSP16 Digital Signal Processor
Block Diagram
ABOO-AI"5
LEGEND:
i'v---------===....::..:.::...:..:-'-'-------,
CACHE
t15K'6
ROM
204. . ,&
16 x 16 Mult
16-blt by 16-blt Multiplier
aO-a1
Accumulators 0-1
ADD
Adder
ALU/SHIFT
Arithmetic Logic
Unit Shifter
auc
Arithmetic Unit Control
cO-c2
Counters 0-2
CMP
Comparator
DAU
Data Arithmetic Unit
Increment Register
isr
Input Shift Register
Increment Register
k
!
"iii
7·4
Spring 1988
Increment Register
MUX
Multiplexer
osr
Output Shift Register
p
Product Register
pc
pdx(in)
Program Counter
pdx(out)
Parallel I/O Data Transmit
Output Register
pi
Program Interrupt
Register
PIO
ploc
Parallel 1/0 Unit
pr
Program Return Register
psw
Processor Status Word
pt
ROM Table POinter
rO-r3
RAM POinter
Registers 0-3
RAM
Read/Write Memory
rb
Modulo Addressing
Register
re
Modulo AddreSSing
Register
ROM
sdx(in)
Read Only Memory
sdx(out)
Senal Data Transmit
Output Register
Parallel 1/0 Data Transmit
Input Register
Parallel 1/0 Control Register
Senal Data Transmit
Input Register
SIO
Senal 1/0 Unit
sioc
Senal 1/0 Control
Register
srta
Serial Receive Transmit
Address Register
tdms
Senal 1/0 Time DIvIsion
Multiplex Signal Control
Register
x
Multiplier Input Register
XAAU
ROM Address Anthmetlc
Unit
YAAU
RAM Address Arithmetic
Unit
yh
y(hlgh) DAU Register
yl
y(low) DAU Register
Digital Signal Processors
WE DSP16A Digital Signal
Processor (Fixed Point)
Description
The WE DSP16A Digital Signal Processor is a 16-bit fixed-point, high-performance,
low-power CMOS integrated circuit with nearly twice the throughput of the DSP16
device. It can be programmed for a variety of applications.
There are three internal processing units, two for memory addressing and one for
data operations. The addressing units support high-speed register-indirect memory
addressing with post-modification of the register using associated increment
registers or fixed increments. The data arithmetic unit (DAU) contains a 16 x 16-bit
multiplier, whose product can be accumulated into one of two 36-bit accumulators.
16- or 32-bit ALU instructions are supported. The DSP16 also features a 15-word
instruction cache for high-speed, ROM-efficient vector operations.
WE DSP16A Digital Signal
Processor 84-pin Plastic
Leaded Chip Carrier
On-chip memory includes 4096 words of mask-programmable ROM and 2048
words of RAM. The on-chip ROM can be augmented with up to 60K words of
external memory or can be replaced with up to 64K words of external memory.
Interfacing is supported with serial/parallel I/O ports and interrupts. The serial port
is compatible with a wide variety of serial devices including TDM codecs and
other DSP16 or DSP16A chips for multiprocessing. The parallel I/O port uses a
16-bit bus, interfacing to other DSP16 or DSP16A devices or peripheral devices,
with data rates of up to 30 Mbytes/s. A mixture of hardware and software interrupts gives a high degree of interface flexibility.
Features
• Low-power .75 Itm 2-level metal
CMOS technology
• 16-bit fixed-point arithmetic
• 33 ns instruction time
• Single cycle multiply/accumulate
• Two 36-bit accumulators
• 15-word instruction cache
• 4K-word on-chip ROM
(Refer to Section 19 for typical applications of this product.)
• 2K-word on-chip RAM
• 64K-word off-chip ROM expansion
• Serial and parallel I/O ports
• Multiprocessor capability
• Maskable interrupts
• UNIX® Systems, MS-DOS, and VMS
Software support
• Development system
Spring 1988
7·5
Digital Signal Processors
WE DSP16A Digital Signal Processor
Software Development
Software development tools to create, test, and debug DSP16A application programs are available to run under the UNIX Operating System, and MS-OOS and
VMS operating systems.
The assembler source is similar to the C language, with the usual features of
labels, symbols, comments, etc. The DSP16A simulator provides full program
debugging by allowing access to all registers and memory, and provides precise
simulations. Conditional breakpoints are supported along with user-defined functions and variables.
Hardware Development
Application system hardware development and real-time software testing is supported by the WE DSP16A-DS Digital Signal Processor Development System.
In-circuit emulation is provided and up to 16 development systems can be cascaded for multiprocessor applications.
Product Matrix
Type
Description
Devices
WE-DSP16A-M 11-033
84-Pin PLCC (Plastic Leaded), 33 ns*
Software Library Versions
WE-DSP16A-SlUN5VX:r
WE-DSP16A-SlUN5B2-F
WE-DSP16A-SlUNB42-T
WE-DSP16A-SlBKSUN-C
WE-DSP16A-SlVMS:r
WE-DSP16A-SlMSDOS-F
UNIX System V (VAX 11/780 Series)
UNIX System V (3B2 Senes)
UNIX System Berkeley 4.2 (VAX 11/780 Series)
UNIX System Berkeley 4.2 (Sun Series)
VMS (VAX 11/780 Series)
MS-OOS (AT&T PC6300 and Compatibles)
* Custom ROM versions are available.
7·6
Spring 1988
Digital Signal Processors
WE DSP16A Digital Signal Processor
LEGEND:
Block Diagram
16
.BOO-A84~ i v - - - - - - - - - - ' - - - ' - - - ' - - - ' - - - - - - - - ,
x 16 Mult
16~blt
by
16~blt
Multiplier
aO-a1
Accumulators 0-1
ADD
Adder
ALU/SHIFT
Arithmetic Logic
Unit Sh Ifter
c"
aue
Arithmetic Unit Control
eO-e2
Counters 0-2
I':STB
CMP
Comparator
EX.
DAU
CACHE
ROM
i!5 K 16
4096 )( 16
Data Arithmetic Unit
Increment Register
isr
Input Shift Register
Increment Register
k
Increment Register
MUX
Multiplexer
osr
Output Shift Register
p
Product Register
pc
pdx(in)
Program Counter
Parallel I/O Data Transmit
Input Register
pdx(out)
Parallel I/O Data Transmit
Output Register
pi
Program Interrupt
Register
PIO
Parallel I/O Unit
pioe
Parallel I/O Control Register
pr
Program Return Register
psw
Processor Status Word
pt
ROM Table POinter
rO-r3
RAM POinter
Registers 0-3
RAM
Read/Write Memory
rb
Modulo Addressing
Register
re
Modulo Addressing
Register
ROM
sdx(in)
Read Only Memory
sdx(out)
Serial Data Transmit
Output Register
510
Serial I/O Unit
sioe
Serial I/O Control
Register
srta
Serial Receive Transmit
Address Register
tdms
Serial I/O Time DIvIsion
Multiplex Signal Control
Register
Serial Data Transmit
Input Register
x
Multiplier Input Register
XAAU
ROM Address Arithmetic
Unit
YAAU
RAM Address Arithmetic
Unit
yh
yl
y(hlgh) DAU Register
y(low) DAU Register
Spnng 1988
7-7
Digital Signal Processors
WE DSP32 Digital Signal
Processor (Floating POint)
Description
The WE DSP32 Digital Signal Processor is a 32-bit floating-point integrated CIrcuit.
Its architecture has been optimized for applications such as speech processing,
telecommunications, image processing, and numerical control.
There are two internal arithmetic units available to the designer, the control
arithmetic unit (CAU) for 16-bit integer operations as well as memory and program
control, and the data arithmetic unit (DAU) for 32-bit floating-point operations. The
CAU features a 16-blt adder. program counter, and 21 general-purpose registers.
The DAU has a single-instruction floating-point multiply/accumulate, auto postnormalization, and single-instruction format conversions.
WE DSP32 Digital Signal
Processor 40·pin DIP and
100.pln PGA
Two banks of 512 (32-bit) words of internal RAM are provided, along with 512
words of mask-programmable ROM. 56 Kbytes of external memory (ROM or
RAM) may be added to the 100-pin or 13 x 13 PGA version with no loss in
execution speed.
There are extremely flexible serial and parallel input/output ports with associated
on-chip DMA controllers for multiprocessor and peripheral Interfacing.
The DSP32 device is available in 16 and 25 MHz versions, achieving instruction
cycle times of 250 and 160 ns, respectively. The 13 x 13 PGA package provides
pin compatibility with the new DSP32C device.
Features
• 160 and 250 ns versions available
• 32-bit floating-point arithmetic
• All instructions are single cycle
• Up to 4 memory accesses per instruction
WE DSP32 Digital Signal
Processor 13 x 13 PGA
• Four 40-bit accumulators
• 16-bit integer operations
• 512 words on-chip ROM; 1024 words on-chip RAM
• External memory expansion (100-pin or 13 x 13 PGA)
• Serial and parallel I/O ports
• On-chip DMA
• UNIX Systems and MS-DOS Software support
• Full C compiler
• Extensive application software library
• Development system
7·8
Spring 1988
• Third party support
(Refer to Section 19 for typical applications of this product.)
Digital Signal Processors
WE DSP32 Digital Signal Processor
Software Development
The DSP32 software development tools include an optimizing C compiler, an
assembler/linker, a simulator operating under the UNIX Operating System, and
MS-DOS Operating Systems
The compiler IS a full implementation of standard AT&T C language and uses
pipeline optimization to achieve the efficiency required In real-time applications
Several libraries of functions allow easy porting of C programs from other systems.
WE DSP32·DS Digital Signal
Processor Development
System
The DSP32 simulator is a powerful debugging facility that allows access to all
registers and memory. Precise timing simulations are possible for code optimization. High-level features, such as user defined functions, variables, and If/while
constructs equip the designer for rapid program development. Data files may also
be Interfaced With simulated I/O so that real data may be processed by the
simulator In non-real time
Hardware Development
The DSP32 development system allows real-time evaluation of programs which are
loaded via an RS232 interface. The development system commands are a subset
of the simulator and Include register/memory display and software breakpoints.
Buffered input/output in-circuit emulation IS possible, and up to 7 development
systems may be used together for multiprocessor applications.
Product Matrix
Type
Description
Devices
WE-DSP32-C08-250
WE-DSP32-G08-250
WE-DSP32-C08-160
WE-DSP32-G08-160
WE-DSP32-R08-250
WE-DSP32-R08-160
40-Pin Ceramic DIP, 250 ns*
100-Pin PGA, 250 ns*
40-Pln Ceramic DIP, 160 ns*
100-Pin PGA, 160 ns*
13 x 13 PGA, 250 ns*
13 x 13 PGA, 160 ns*
Software Library Versions
WE-DSP32-SlUN5VX-T
WE-DSP32-SL-U N B42-T
WE-DSP32-SlUN5B2-F
WE-DSP32-SL-MSDOS-F
WE-DSP32-SL-BKSUN-C
UNIX System V (VAX 11/780 Series)
UNIX System, Berkeley 4.2 (VAX 11/780 Series)
UNIX System V (3B2 Series)
MS-DOS (AT&T PC6300 and Compatibles)
UNIX System, Berkeley 4.2 (Sun Series)
Application Library Versions**
WE-DSP32-AL-MSDOS-F
MS-DOS (AT&T PC6300 and compatibles)
Development Systems
WE-DSP32-DS
WE-DSP32-DS-160
Development System (Host Independent), 250 ns
Development System (Host Independent), 160 ns
C-Compiler Versions
WE-DSP32-CC-U N5VX-T
WE-DSP32-CC-UNB42-T
WE-DSP32-CC-BKSU N-C
WE-OSP32-CC-U N5B2-F
WE-DSP32-CC-MSDOS-F
UNIX System V (VAX 11/780 Series)
UNIX System, Berkeley 4.2 (VAX 11/780 Series)
UNIX System, Berkeley 4.2 (Sun Series)
UNIX System V (3B2 Series)
MS-DOS (AT&T PC6300 and Compatibles)
* Custom ROM versions are available.
** Supported for same hosts as Software Library and C Compiler.
Spring 1988
7·9
Digital Signal Processors
WE DSP32 Digital Signal Processor
Block Diagram
*MSNO-MSN3
I...-+-~
* ABOO-ABI3
MMDO L.,;..-+--<~
MMDI
PABO-PAB2 !-~~-.I
PEN ' - - - - - . I
POBO- POB7
PGN
PWN
~---.I
~---.I
PAR
POR
PI R
PCR
EMR
ESR
(16)
(16)
(16)
(8)
(10)
(6)
ROM
512 X 32
RAM
512 X 32
RAM
512 X 32
*OBOO-OB31
*MGN "..--~
01
DAU
~---.rs~~~
ILD ....-----t ""'-:-=-=:7""1
ICK ;.------t f-'-:~-'-=:!....j
ISF ....----1 <-':"::':":""'_--'
32
DO +e---~ ~:7:'::-:-::::;-'
OEN !------.I ~~....:...;:=-j
OLD 14------.1
OCK
~~-OSE
OSE
SY
CKO
CKI
RESTN
ZN
IIOC (16)
I
I
CONTROL
AND
CLOCKS
I
I
*AVAILABLE ON 100- PIN PGA PACKAGE ONLY
LEGEND:
aO-a3
EMR
ESR
laUF
Accumulators 0-3
Arithmetic Logic Unit
Control Arithmetic Unit
Data Arithmetic Unit
Data Arithmetic Unit
Control Register
Error Mask Register
Error Source Register
Input Buffer
7-10
Spring 1988
ALU
CAU
DAU
DAUC
10C
ISR
OBUF
OSR
PAR
PC
PCR
PDR
InputiOutput Control
Register
Input Shift Register
Output Buffer
Output Shift Register
PIO Address Register
Program Counter
PIO Control Register
PIO Data Register
PIO
PIR
R1-r19
PIN
POUT
RAM
ROM
SIO
Parallel 1/0 Unit
PIO Interrupt Register
Registers 1-19
POinter for Serial
DMA Input
POinter for Serial
DMA Output
Read Write Memory
Read-Only Memory
Serial 110 Unit
Digital Signal Processors
WE DSP32C Digital Signal
Processor (Floating Point)
Description
Targeted at high-performance applications, the WE DSP32C Digital Signal Processor brings an unprecedented level of performance to the systems designer.
Upward compatibility has been preserved with the DSP32, so current DSP32
users can easily upgrade to the DSP32C If greater performance IS desired. The
DSP32C features a 16 Mbyte address space, vectored Interrupts, a full C compiler,
enhanced Instruction set, and powerful format conversions.
WE DSP32C Digital Signal
Processor 13 x 13 Ceramic
PGA Package
The DSP32C uses two execution units to achieve ItS high throughput. An integer
processing unit (CAU) IS used as a 16- or 24-bit microprocessor, or it may be
used to generate and modify addresses for the data arithmetic unit (DAU). The
CAU supports conditional and unconditional ALU and branch operations as well
as data move instructions When used to generate addresses for the DAU, the
CAU can generate and post-modify four addresses in a single Instruction cycle.
The DAU employs a straightforward 3-stage fetch/multiply/accumulate pipeline for
32-bit floating-pOint operands. Results are automatically normalized without additional instructions or pipeline stages.
On-chip memory consists of three banks of RAM, each with 512 words. A ROMcoded version is also available which substitutes a 2048-word ROM for one
512-word RAM bank. External memory IS expandable to 16 Mbytes (directly
addressable). A flexible wait-state generator allows efficient use of slower
memories and memory-mapped peripherals.
Features
• 80 and 100 ns versions available
• .75 JLm double-metal CMOS technology
• Object code compatible with DSP32 (Pin compatible with 13 x 13 PGA package)
• Twenty-two 24-bit general-purpose registers
• 32-blt floating-point arithmetic
• Full C compiler
• 24-blt and 16-blt integer microprocessor operations for logic and control
• Data addressable as 8-, 16-, or 32-bit words
• 2048 words of ROM and 2 banks (512 words each) of RAM, or 3 banks (512
words each) of RAM
• 16 Mbytes of directly addressable off-chip memory
• Wait states for slow external memories
(Refer to Section 19 for typical applications of this product.)
Spring 1988
7·11
Digital Signal Processors
WE DSP32C Digital Signal Processor
• Powerful single-cycle data format conversions
- IEEE 7S4 floating point
- 24-bit and 16-bit integer
- 8-bit linear byte
- 8-bit wlaw and A-Iaw
• Serial and parallel ports with DMA
• Interfaces to a microprocessor without glue logic
• 6 vectored interrupts
• 133-pin PGA package
Product Matrix
Type
Description
Devices
WE-DSP32C-R31-100
WE-DSP32C-R31-080
WE-DSP32C-R21-XX-100
WE-DSP32C-R21-XX-080
133-Pin
133-Pin
133-Pin
133-Pin
Software Library Versions
WE-DSP32C-Sl-UNSVX
WE-DSP32C-Sl-U NB42
WE-DSP32C-Sl-UNSB2
WE-DSP32C-SL-MSDOS
WE-DSP32C-SL-BKSUN
UNIX System V (VAX 11/780 Series)
UNIX System, Berkeley 4.2 (VAX 11/780 Series)
UNIX System V (3B2 Series)
MS-DOS (AT&T PC6300 and Compatibles)
UNIX Berkeley 4.2 (Sun Series)
Application Library Versions*
WE-DSP32C-Al-MSDOS
MS-DOS (AT&T PC6300 and Compatibles)
C-Compiler Versions
WE-DSP32C-CC-UNSVX-T
WE-DSP32C-CC-UN B42-T
WE-DSP32C-CC-BKSU N-C
WE-DSP32C-CC-UNSB2-F
WE-DSP32C-CC-MSDOS-F
UNIX System V (VAX 11/780 Series)
UNIX System, Berkeley 4.2 (VAX 11/780 Series)
UNIX System, Berkeley 4.2 (Sun Series)
UNIX System V (3B2 Series)
MS-DOS (AT&T PC6300 and Compatibles)
PGA,
PGA,
PGA,
PGA,
100 ns
80 ns
100 ns, Custom ROM
80 ns, Custom ROM
Development Systems (AT&T PC6300 and Compatibles)
WE-DSP32C-DS-DEV-16
Development Card, 16K Words x 32 Memory
WE-DSP32C-DS-DEV-64
Development Card, 64K Words x 32 Memory
WE-DSP32C-DS-ICE
In-Circuit Emulator Board
WE-DSP32C-DS-PBS
PC Bus Card
WE-DSP32C-DS-EXM
Extended Memory Board
* Supported for same hosts as Software Library and C Compiler.
7·12
Spring 1988
Digital Signal Processors
WE DSP32C Digital Signal Processor
Block Diagram
MSN [0-3)
AS [0-21)
-'
S
rr
J.--
~
PIO
PAS (0-3]
POS [0-15]
PEN
PON
PWN
PDF
PlF
-;=
~
ADDRESS BUS (24)
....;).-
RAM2
lJ
li
S7_
ROMO
RAM1
RAMO
PAR (23)
PDR(lS)
POR2 (16)
ptR(1S)
ROM
2048
OR
x 32
RAM
RAM
RAM
512 x 32
512 x 32
512 x 32
peR (11)
Ef...I=I. (10)
i"CAU
ESR(S)
PCW(16)
PlOP (8)
RWN,DSN,CYClEIN
CKO,MGN,MWN
DB [0-31J
SADYN
[]
ILD
leK
IBF
00
OLD
DCK
OBE
OSE
OEN
SY
1J
tt
~
~
~
f.f.-
~
~
~
~
..,....;).-....
-.!..J>-
DATA BUS (32)
-+L
tt
11
.AJ..
~
y
ALU 16/24
f-
i
PC (24)
r1-r14 (24)
r15-r19 (24)
PIN (24)
SIO
DAU
:
IBUF (32)
ISA
(32)
POUT (24)
.. (32)
CONTROL
(32)
OBUF (32)
I
OSR
(40)
~
IVTP(24)
R...OATIJIKl
POM
MULTIPLIER
. ..
I
FLOATNG
I
-i
POINT
AOOER
(40)
CK! , RESTN , ZN
INTREQ1,INTRE02,BREQ
IACK1,IACK2,BRACKN
CJG 9/87
(4--,,---.,--0 ClKDO
USER SUPPLIED BIAS CIRCUIT
AND CLOCK RETURN TO INPUT
~
+
TO elKIN
Advanced information -
9·6
Spring 1988
Sample devices are not necessarily available at this time.
(Refer to Section 19 for typical applications of this product.)
10
Gallium Arsenide
Integrated Circuits
The intrinsic advantages
of Gallium Arsenide include high speed, low
power, and radiation
hardness.
Page
Decision Circuit: 1.7 Gb/s
10-2
AT&T's initial product offering in this technology
is a decision circuit. It
performs retiming and
regeneration of noisy
digital input data. The
device features a highgain/bandwidth amplifier,
D-type flip-flop, and complementary 50 ohm output buffers. The decision
and clock threshold
voltages are provided as
dc outputs from the chip.
For additional infor·
mation contact your
nearest sales office
or call:
1-800-372-2447.
Spring 1988
10·1
Gallium Arsenide ICs
Decision Circuit:
1.7 Gb/s - LG1088AX
Description
The LG1088AX Decision Circuit is designed for high-performance, high-speed applications in digital terminals, repeaters, synchronizers, and data samplers and can
be interconnected to create higher-level circuit functions. The unit retlmes and
regenerates a digital data stream, determining actual data states from weak input
signals through a threshold voltage reference. A high-gain/bandwidth amplifier
and D-type flip-flop with output buffers produce complementary outputs. The
LG1088AX Decision Circuit is supplied in a 20-pin, surface-mountable ceramic
package with nominal dimensions of 0.580" x 0.488" x 0.084':
Functional Diagram
GND
1
20
GND
DC CLOCK REF
2
19
VOD2
GND
3
18
GND
CLOCK INPUT
4
17
Q OUT
GND
5
16
GND
GND
6
15
GND
DATA INPUT
7
14
Q OUT
GND
8
13
GND
DC DATA REF
9
12
VOD1
GND
10
11
GND
Nominal Specifications (TA
25°C, VOD1
2.0 V)
Parameter
Symbol
Min
Maximum Clock Frequency
Clock Input Voltage
Data Input Voltage
Data Output Voltage*
Propagation Delay. Low to High
High to Low
Setup + Hold Time
Data Output Transition Time (20% to 80%)*
Power Supply Currents: Pin 12
Pin 19
fmax
VCLK
VIN
VOOUT
tPLH
tPHL
tS+H
1.7
Typ
Max
600
600
150
250
400
350
400
150
1001
1002
25
35
Unit
GHz
mV p-p
mV p-p
mV p-p
ps
ps
ps
ps
mA
mA
* ac-coupled into 50 ohms
10-2
Spring 1988
(Refer to Section 19 for typical applications of this product.)
11
Hybrid Integrated Circuits
AT&T's hybrid IC offering
features both thin- and
thick-film technologies. In
thin film, a tantalum
resistor/capacitor (RC)
process allows for
precisely matched and
temperature-stable components. A combination of
both technologies is used
to form reliable and inexpensive crossovers, with
the inherent advantages
of thin film: high precision
and space compaction.
Page
Custom Hybrid Integrated Circuits
11-2
AT&T also provides a
patented copper thin-film
technology that produces
high conductivity paths
for use in high-frequency
applications. This combination of highly stable
tantalum thin-film resistors
and the copper conductor
system allows increased
power densities without
degrading reliability.
Packaging options include
not only standard SIPs
and DIPs but also surface
mount and a variety of
leaded and lead less
packages.
For additional infor·
mation contact your
nearest sales office
or call:
1-800-372-2447.
Spring 1988
11·1
Hybrid ICs
Custom Hybrid Integrated Circuits
Description
AT&T's custom hybrid integrated circuits are produced by depositing thin and/or
thick film metallization on a ceramic base. Active or passive components are
attached to the circuIt, producing a very efficient, Integrated package. These
packages are available in standard or special configurations.
Performance
• High-stability resistor and capacitor technology with extremely tight component
tolerances, ratios, and tracking capabilities
• Low parasitics and controlled impedances
• Excellent thermal performance
• High conductivity with copper or noble metal conductor systems
• Minimum propagation delay
Flexibility
• Efficient electronic packaging by interconnecting different silicon IC technologies,
such as MOS and Bipolar, on one hybrid
• Quick modifications to a design late in the development stage
Modularity
• Pre-tuned and tested modules to meet critical functional requirements
• Pre-tested hybrid ICs improve system yields and reduce diagnostic and repair
costs
Custom Design
Bell Laboratories can design a custom hybrid IC from your circuit specifications.
Our experienced application and design engineers can work with you to partition
and develop a hybrid implementation of your circuit design. Early involvement with
our engineers permits maximum utilization of the benefits of hybrids.
Hybrid Technology
AT&T will recommend the most appropriate technology for your hybrid circuit. Our
selection of hybrid technologies includes thin and thick film, multilayer thin and
thick film, and PCB-based modules.
11-2
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Hybrid ICs
Custom Hybrid Integrated Circuits
Components
AT&T makes available a wide variety of components that can be placed on a
hybrid IC. In addition to thin- and thick-film resistors and capacitors, a full line of
AT&T silicon integrated circuits IS available for your hybrid application. Commercially available active and passive components in packaged or unpackaged configurations are also used. These include: flat packs, chip resistors, chip capacitors,
chip inductors, SOTs, SOICs, chip carriers, and optical components.
Hybrid Packaging
AT&T hybrids are available in a variety of physical packages. Standard SIPs and
DIPs often provide the most cost-effective design solution, but we also offer surface mount packages and a variety of leaded and unleaded packaging options.
AT&T can also supply specially designed microwave hybrids.
End-Point Specifications
Thin Film Components
Resistors
Sheet Resistance
Laser Trimmed (Abs)
Laser Trimmed (Ratio)
Stability (20 Yrs., 65"C)
Temp. Coet. of Res. (TCR)
TCR Tracking
Resistor Density
300 & 100 WSq. (75, 50, & 25 WSq.)*
±0.5% (±0.1%)*
±0.25% (±0.05%)*
+0.1% max.
-145 ±20 ppm/"C
< 4.0 ppm/"C
5 QIRes. to 3 MWCrt.
Capacitors
Capacitance Density
Dissipation Factor
Temp. Coet. of Cap. (TCC)
Tolerance
Stability (20 Yrs., 65°C)
500 - 56000 pF/Crt. (100 :::;.0024 (1 kHz at 25"C)
+ 145 ± 15 ppm/"C
±5.o%
-0.1% max.
RC Product
Tolerance
Temp. Coef. of Freq. (TCF)
±0.3% (±0.1%)*
0.0 ±25 ppm/OC
Conductors
Sheet Resistance (Au)
Sheet Resistance (Cu)
50.0 mWSq. (5.0 mWSq.)*
«2.0 mWSq.)*
Resistors
Sheet Resistance
Laser Trimmed (Abs)
Laser Trimmed (Ratio)
Stability (20 Yrs., 65"C)
Temp. Coef. of Res. (TCR)
TCR Tracking
0.1 nlSq. to 10 MWSq.
± 1.0% (±0.5%)*
±0.5% (±0.25%)*
+0.1%
+100 ppm/"C
<50 ppm/"C
Conductors
Sheet Resistance
25 -
56000 pF/Crt.)*
Thick Film Components
45 mWSq. (2 -
3 mWSq.)*
* Components with these tighter speCifications are also available.
Spring 1988
11-3
12
Microprocessors and Peripherals
AT&T advanced
microprocessors and
peripherals offer you all
the building blocks
necessary for highperformance, 32-bit
system designs. Ranging
from 10-24 MHz, these
chips are upward compatible and optimized for
supporting UNIX® System
V software for multitasking/multiuser systems.
Page
WE® 32100 Microprocessor
12·2
WE 32200 Microprocessor
12·4
WE 32101 Memory Management Unit
12·5
WE 32201 Memory Management
Unit/Cache
12·6
WE 32102 Clock
12·7
WE 32103 DRAM Controller
12·8
WE 32104 DMA Controller
12·10
WE 32204 DMA Controller
12·12
WE 32106 Math Acceleration Unit
(Floating Point)
12·14
WE 32206 Math Acceleration Unit
(Floating POint)
12·15
WE 321DM/WE 322DM CPU and MMU
Device Monitors
12·16
AT&T also offers a design
and development system
which incorporates incircuit emulation of the
CPU and MMU with no
wait states.
WE 321 DS Microprocessor Development
System
12·17
WE 321EB Microprocessor Evaluation
Board
12·18
For additional infor·
mation contact your
nearest sales office
or call:
WE 321SG C·Software Generation
Programs (CPLU Release 4.2)
12·19
UNIX System Release 2.1/3.1
12·20
The 32200 Microprocessor and peripherals
chip set includes an advanced CPU, an integrated Memory Management Unit (MMU) and
Data Cache, and a
floating-point Math
Acceleration Unit (MAU).
The Direct Memory
Access Controller (DMAC)
and Dynamic RAM Controller (DRAMC) round out
the chip set family.
1·800-372-2447.
Spring 1988
12·1
Microprocessors and Peripherals
WE 32100 Microprocessor
Description
The WE 32100 Microprocessor is a second-generation, high-performance, singlechip, 32-bit central processing unit (CPU). It is optimized to support modern
process-oriented operating systems and efficiently execute high-level language
programs. It performs all of the system address generation, control, memory access, and processing functions required in a 32-bit microcomputer system. The
CPU provides special instructions to allow the use of coprocessors and the
necessary signals for interfacing with the WE 32101 Memory Management Unit.
Separate 32-bit address and data buses are provided. The system memory space
is addressed over the 32-bit address bus using either physical or virtual addresses. Data is written over the 32-bit bidirectional data bus in word (32-bit),
halfword (16-bit), or byte (8-bit) lengths. Extensive addressing modes result In a
symmetric, powerful, and extensive instruction set. The WE 32100 Microprocessor
is available in 10-, 14-, and 18-MHz frequency versions. It is available in a 125-pin
square, hermetic, ceramic pin grid array package and requires a single +5 V
supply.
Features
• 2 to 4 MIPS processing power
• Efficient execution of high-level language programs
• Extensive and orthogonal instruction set
• Direct support for process-oriented operating systems, such as UNIX System V,
and process-handling instructions and executions
• Demand-paged virtual memory support provides mainframe computer capabilities
• Full 32-bit paths, address and data buses, and data manipulations
• Sixteen 32-bit on-chip registers; nine general-purpose and seven special-purpose
• On-chip 64 x 32 bit Instruction cache and 8 x 8 bit Instruction queue provide
better system performance
• 4 Gbytes (2 32 ) of direct memory addressing
• Physical and virtual addressing
• General-purpose coprocessor interface
• Four levels of execution privilege: kernel, executive, supervisor, and user
• Fifteen interru pt levels
• Memory-mapped I/O
12-2
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Microprocessors and Peripherals
WE 32100 Microprocessor
• Triadic Instructions
• Instructions start on 8-bit byte boundaries
• Synchronous or asynchronous Interfacing to external deVices
• Complete floating-point support via the WE 32106 Math Acceleration Unit
• 10-, 14-, and 18-MHz versions
• Single +5 V supply
Block Diagram
• Low-power CMOS technology
FROM
INSTRUCTION
QUEUE
ADDRESS
:<)L
H
I
MAIN CONTROLLER
1
I
FETCH CONTROLLER
EXECUTE CONTROLLER
I
! t'
I
TO MAIN
CONTROLLER
32- BIT
REGISTERS
rO
DATA
toc
BUS
INTERFACE
CONTROL
64-WORD
INSTRUCTION
CACHE
r~
B- BYTE
INSTRUCTION
QUEUE
r2
r3
r4
r5
r6
r7
rB
FP
AP
PSW
SP
PCBP
ISP
PC
,
IMMEDIATE
s
DISPLACEMENT
EXTRACTOR
IJ
INTERFACE
a
CONTROL
\
PC
32
32
ABUS
ffi
LOGIC
UNIT
32
.on
32
32,
FETCH UNIT
-I"
32,
CBUS
'U'
I"
I--
ADDRESS c/
ARITHMETIC
UNIT
32
32,
WORKING
REGISTERS
EXECUTE UNIT
Spnng 1988
-
12·3
Microprocessors and Peripherals
WE 32200 Microprocessor
Description
The WE 32200 Microprocessor (CPU) is the next generation of the single-chip,
32-bit WE 32100 Microprocessor. It is protocol and upward object code compatible with the WE 32100 Microprocessor. Application object code for the WE 32100
CPU will run without modification on the WE 32200 CPU. The new features of the
WE 32200 Microprocessor include:
1.
2.
3.
4.
5.
6.
Arbitrary byte alignment for data and instructions
New addressing modes to support array access
Additional kernel and user registers
Loop control
BCD arithmetic instructions
Additional semaphore support
7. Dynamic bus sizing
8. Byte replication
Features
• Performance at 6-8 MIPS
• 32 on-chip 32-bit registers (16 registers are utilized by the WE 321SG Software
Generation Programs)
• 16/32-bit dynamic bus sizing allows transfers to/from 16- and 32-bit memories and
peripherals by dynamically determining data width during an access
• Arbitrary byte alignment enables the CPU to handle nonaligned memory
accesses for both reads and writes
• 15-level interrupt hierarchy for higher speed and improved security in interrupt
handling
• Direct support for operating systems and high-level languages including C,
PASCAL, FORTRAN, and COBOL
• A 256 byte on-chip instruction cache
• Start of instruction and stop pins, allowing you to control and monitor instruction
execution and providing simplified synchronization of processors for fault tolerant
applications
• Hardware support for process switching, minimizing the need for additional
assembly code
• 24 MHz clock operation
• Low-power, 1 pm, CMOS technology
12·4
Spring 1988
(Refer to Section 19 for\ typical applications of this product.)
Microprocessors and Peripherals
WE 32101 Memory
Management Unit
Description
The WE 32101 Memory Management Unit (MMU) is a 32-bit, bus-structured
device that provides logical-to-physical address translation, memory organization,
control, and access protection for the WE 32100 Microprocessor. The MMU performs address translation by mapping virtual memory addresses to physical
memory addresses. It supports both demand paged and demand segmented virtual memory systems, allowing 4 Gbytes of virtual memory and up to 4 Gbytes of
physical memory per process. The MMU also allows the use of shared segments
for intertask communication. Access privileges for each segment provide system
protection. The WE 32101 Memory Management Unit is available in 10-, 14-, and
18-MHz versions; is available in a 125-pin square, hermetic, ceramic pin grid array
package and requires a single +5 V supply.
The 4 Gbyte virtual address space is subdivided into four sections with as many
as 8K segments per section. Segments may be as large as 128 Kbytes of contiguous space, or may be further subdivided into as many as sixty-four 2 Kbyte
pages. The segments are mapped by the MMU into the physical address space.
For each of the four execution levels, there are four access permissions associated with segments - execute only, read/execute, read/write/execute, no access.
The MMU contains descriptor caches, section RAMs, and MMU registers; all are
addressable as memory locations. Each virtual memory section has a segment
descriptor cache, page descriptor cache, base address register, and section
length register associated with it. The four MMU registers are dedicated to
decoding and reporting the status of the currently active virtual address.
Features
• Extended temperature available now; MIL-STO-883C (10 MHz Version) planned
availability 1988
• Manages 4 Gbytes (2 32) of virtual address and up to 4 Gbytes of physical address
space
• Paged and nonpaged segmentation support
• On-chip, segment descriptor cache; 2-way set-associative page descriptor cache
• On-chip cache miss-processing
• Four types of access protection at four execution levels
• Hardware support for UNIX System demand paging with automatic referenced/
modified bit update
• Shared segments managed by indirect segment descriptors
• Extensive fault detection and resolution capability
• Multiple MMU configuration support; low-power CMOS technology
• 10-, 14-, and 18-MHz versions
(Refer to Section 19 for typical applications of this product.)
Spring 1988
12·5
Microprocessors and Peripherals
WE 32201 Memory
Management Unit/Cache
Description
The WE 32201 Memory Management Unit (MMU) provides high-performance
memory management for WE 32200 Microprocessor based systems. This VLSI
device provides logical-to-physical address translation and access protection. It
has 32-bit data and address buses and is upward compatible with the WE 32101
MMU. The MMU can map 232 bytes of virtual memory into a maximum of 232
bytes of physical memory. Paged segments are supported with access rights
checking for system protection. A 64-entry, fully associative page descriptor cache
provides a high hit rate. Transparent multiple contexts are supported for faster context switching. The MMU also allows the use of shared segments for interprocess
communication.
The on-chip, 4-Kbyte, two-way, set-associative instruction/data cache returns data
with zero wait states on WE 32200 CPU virtual and physical memory accesses.
Transparent data cache miss-processing and zero wait-state hits significantly
reduce overall system access wait states. The physical cache stores multiple contexts and performs bus monitoring to maintain cache integrity.
Features
• Manages mapping of up to 4 Gbytes (2 32 ) of virtual address space and up to
4 Gbytes (2 32 ) of physical address space
• One and a half cycle virtual-to-physical address translation for instruction/data
cache misses
• Fully associative, CAM based, 64-entry page descriptor cache
• On-chip zero wait-state, 4-Kbyte physical data cache
• Multiple configurations for up to 16-Kbyte physical cache
• Support for paged and contiguous segments
• Transparent multiple context support, With Internal management of context
identification
• Multiple page sizes: 2, 4, or 8 Kbytes
• Four execution levels with access rights checking
• On-chip miss-processing
• Bus watching maintains data integrity
• Hardware support for UNIX System demand paging, with automatic referenced/
modified bit update
• Indirect segment descriptors in support of shared segments
• 22 M Hz clock operation
• Low-power, 1 {dTl, CMOS technology
12-6
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Microprocessors and Peripherals
WE 32102 Clock
Description
The WE 32102 Clock supplies the two-phase, CMOS-level, frequency source required by the WE 32100 and WE 32200 Microprocessor chip sets. The WE 32102
Clock generates three outputs from an internal crystal controlled encoder. Two of
the outputs are of the same basic frequency, but 90 0 out-of-phase. A third output
is twice the frequency. Other features include an external frequency source input
which provides control for testing of the clock's output. The clock is housed in a
hermetically-sealed metal can (double-width, dual in-line package) and requires a
single +5 V supply for operation. It is available in 10-, 14-, 18-, 22-, and 24-MHz
versions.
The WE 32102 Clock can be controlled by an internal crystal or by an external frequency source for testing purposes. A clock enable input determines whether
control is internal (enable high) or external (enable low).
Features
• Extended temperature
• Available in 10-, 14-, 18-, 22-, and 24-MHz versions
• Two outputs 90 0 out-of-phase
• Each output drives up to 130 pF of capacitive loading
• Input for external frequency source
• Input and output at CMOS levels
• Single +5 V supply
(Refer to Section 19 for typical applications of this product.)
Spring 1988
12-7
Microprocessors and Peripherals
WE 32103 DRAM Controller
Description
The WE 32103 DRAM Controller provides address multiplexing, access and cycle
time management, and refresh control for DRAM devices. In a single chip, it provides the Interface for high-performance, high reliability, 16- and 32-bit wide,
dynamic memory subsystems. Its general-purpose interface is programmable, optimizing system performance for a wide range of memory configurations. The
DRAM controller is capable of addressing up to 16 Mbytes of memory. The WE
32103 DRAM Controller is available in a 125-pin, square, hermetic, ceramic pin
grid array package; is available in 10-, 14-, and 18-MHz versions; and requires a
single +5 V supply.
The important features of the WE 32103 DRAM Controller are:
Memory Access/Address Translation Overlap
To provide an overlap of memory accesses with address translation, the DRAM
controller uses a pretranslation technique. This feature can be used in virtual
memory systems that use paged segments. In such systems, the lower order bits
of the virtual address do not change during translation. The DRAM controller can
use these low-order bits to drive the row address and assert the row address
strobe while the WE 32101 Memory Management Unit is translating the remaining
portion of the address.
Multiword Memory Transfers
Byte, half-word, 3-byte, 4-byte, 2-word, 3-word, and 4-word read and write operations are supported. For I/O bound user applications, use of multiword bus transactions can double the rate of block data transfer over the system data bus.
Multiword access reduces the overhead latencies associated with bus arbitration,
successive address transmission, and subsequent address translation. The DRAM
controller provides 2-word reads to the WE 32100 CPU, as well as 4-word reads
and writes to the WE 32104 DMA Controller. The DRAM controller provides
multiword access by receiving an access size request, supplying a handshake,
and manipulating DRAM strobes for page, nibble, or cycling RAS.
Error Detection and Correction
All of the signals needed to interface with an error detection and correction unit
are provided. The DRAM controller turns partial-word write operations and read
operations with correctable errors into a user-transparent read-modify-write
memory cycle. For high reliability applications, programmable support is provided
for periodic error scrubbing and automatic check-bit Initialization.
12-8
Spring 1988
(Refer to Section 19 for typical applications of this product_)
Microprocessors and Peripherals
WE 32103 DRAM Controller
Dual-Port Configuration
A dual-ported memory can be controlled uSing two DRAM controllers. One IS configured as a master, while the other is configured as a slave. Along with its normal
tasks, the master performs memory arbitration and refreshes. The slave normally
3-states its memory outputs until It is granted ownership of the shared memory
outputs by the master DRAM controller.
Refresh Configurations
The DRAM controller can be programmed to provide a wide variety of refresh
schemes. It has both a programmable, internal refresh timer and an external
refresh request input. The refresh mode can be programmed for distributed
refresh. Combinations of internal, external, and distributed refresh modes allow
many different applications. An explicit refresh interval timer is accessible to the
programmer.
Configuration Registers
Configuration registers are provided to optimize the controller for a wide range of
DRAM configurations.
Features
• Can overlap memory access with MMU address translation and chip select
decoding functions
• Provides 5 cycle access mechanism for CPU, CPU/MMU, CPU/MMUIDMAC
systems
• Supports double-, triple-, and quad-word memory reads and writes
• Full support for error detection and correction devices
• Drives up to 88 DRAM devices without external buffers
• Controls a variety of DRAM configurations including 1-Mbit DRAM devices
• Internal refresh timer and refresh address counter to reduce board-level device
count
• Programmable DRAM access times
• Programmable support for page and nibble mode DRAM
• Dual-ported memory configurations using two DRAM controllers
• General-purpose asynchronous operation and synchronous operation with the
WE 32100 Microprocessor chip set
Spring 1988
12·9
Microprocessors and Peripherals
WE 32104 DMA Controller
Description
Direct memory access (DMA) is a mechanism for servicing 1/0 device data
transfer requests. It is driven by an 1/0 device to provide direct access to system
memory. The WE 32104 Direct Memory Access Controller (DMAC) provides DMA
capabilities while taking advantage of the full 32-bit data and address of the WE
32100 Microprocessor. The DMAC contains specialized hardware that permits
transfers at a much faster rate than possible under microprocessor control.
The DMAC is a memory-mapped peripheral device that performs memory-tomemory, memory-to-perlpheral, and perlpheral-to-memory data transfers quickly
and efficiently. When used with the WE 32100 Microprocessor, the DMAC permits
the full 32-bit width of the system bus to be utilized without external interfacing
logic. In addition, a peripheral bus IS provided to couple 8-bit input/output devices
to the system bus. The DMAC is implemented in CMOS technology, is available in
a 133-pin, square, hermetic, ceramic pin grid array, and requires a single +5 V
supply. The DMAC is available in 10-, 14-, and 18-MHz versions.
Architectural Summary
The DMAC has four independent channels that allow it to serve four unrelated
transfer requests simultaneously. Each channel has a set of registers that configures and controls its operation. In addition, there is one mask register which IS
shared between the four channels. When the DMAC is in peripheral mode,
registers within the DMAC and registers within devices connected to the
peripheral bus are accessed by the CPU. This provides the CPU an access path
to the peripheral bus.
The seven functional elements of the DMAC are:
System Bus Interface - provides address, data, and control signals needed to interface the DMAC to the WE 32100 Microprocessor.
Data Buffers - each of the four channels has a 32-byte data buffer. The lowest address data buffer is used as the memory fill data register (MFDR). This register
contains the data which is written to consecutive locations during memory fill
operations.
Register File - contains eight control registers for each DMA channel and one
global register. The control registers consist of source address, destination address, transfer count, base address, mode, device control, interrupt vector, and
status and control registers. The global register is a mask register used to disable
particular channel activity.
Address Arithmetic Unit (AAU) - calculates addresses of source and destination
using information from the per channel registers and the. data size and request
generator.
12·10
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Microprocessors and Peripherals
WE 32104 DMA Controller
Count Arithmetic Unit (CAU) - calculates number of bytes to be transferred using
information from the per channel registers and the data size and request
generator.
Packing Registers - used to pack bytes Into larger operands when transferring
from the peripheral bus to the system bus. Also used to unpack large system bus
operands to bytes when transferring to the peripheral bus.
Peripheral Bus - used to communicate with 8-bit I/O devices.
Features
• Extended temperature, Mil spec
• Full 32-bit address and data buses
• 8-bit peripheral bus for coupling I/O devices to the system bus
• Double- and quad-word bus cycles available for high system throughput
• Internal data buffers to support burst data peripherals
• Four independent prioritized DMA channels
• Two programmable interrupt vectors per channel
• Memory-to-memory transfers at rates up to 14.4 Mbytes/s at 18 MHz
• Memory-to-peripheral transfers at rates up to 9 Mbytes/s at 18 MHz (With burst
mode)
• Memory fill operations at rates up to 26.2 Mbytes/s are available for writing an
arbitrary constant to a block of memory
Spring 1988
12-11
Microprocessors and Peripherals
WE 32204 DMA Controller
Description
Direct memory access (DMA) is a mechanism for servicing I/O device data
transfer requests. It is driven by an I/O device to provide direct access to system
memory. The WE 32204 Direct Memory Access Controller (DMAC) provides DMA
capabilities while taking advantage of the full 32-bit data and address of the WE
32200 Microprocessor. The DMAC contains specialized hardware that permits
transfers at a much faster rate than possible under microprocessor control.
The DMAC is a memory-mapped peripheral device that performs memory-tomemory, memory-to-peripheral, and penpheral-to-memory data transfers quickly
and efficiently. When used with the WE 32200 Microprocessor, the DMAC permits
the full 32-bit width of the system bus to be used without external interfacing logic.
In addition, a peripheral bus is provided to couple 8-bit input/output devices to
the system bus. The DMAC is implemented in CMOS technology, is available in a
145-pin, square, hermetic, ceramic pin grid array, and requires a single 5 V supply. The DMAC is available in a 24 MHz version.
Architectural Summary
The DMAC has four independent channels, which allow it to serve four unrelated
transfer requests simultaneously. Each channel has a set of registers that configures and controls its operation. In addition, there is one mask register that is
shared between the four channels. When the DMAC is in peripheral mode,
registers within the DMAC and registers within devices connected to the
peripheral bus are accessed by the CPU. This procedure provides the CPU an
access path to the peripheral bus.
The seven functional elements of the DMAC are:
System Bus Interface - provides the address, data, and control signals needed to
interface the DMAC to the WE 32200 Microprocessor.
Data Buffers - each of the four channels has a 32-byte data buffer. The lowest
address data buffer is used as the memory fill data register (MFDR). This register
contains the data that is written to consecutive locations during memory fill
operations.
Register File - contains eight control registers for each DMA channel and one
global register. The control registers consist of source address, destination
address, transfer count, base address, mode, device control, interrupt vector, and
status and control registers. The global register is a mask register used to disable
particular channel activity.
Address Arithmetic Unit (AAU) - calculates addresses of source and destination
using information from the per channel registers and the data size and request
generator.
12·12
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Microprocessors and Peripherals
WE 32204 DMA Controller
Count Arithmetic Unit (CAU) - calculates the number of bytes to be transferred
using information from the per channel registers and the data size and request
generator.
Packing Registers - used to pack bytes into larger operands when transferring
from the penpheral bus to the system bus. Also, It IS used to unpack large system
bus operands to bytes when transferring to the penpheral bus.
Peripheral Bus - used to communicate with 8-blt I/O devices.
Features
• Full 32-bit address and data buses
• 8-bit peripheral bus for coupling I/O devices to the system bus
• Double- and quad-word bus cycles available for high system throughput
• Internal data buffers to support burst data peripherals
• Four independent prioritized DMA channels
• Two programmable interrupt vectors per channel
• Memory-to-memory transfers at rates of up to 19.2 Mbytes/s at 24 MHz
• Memory-to-perlpheral transfers at rates of up to 12 Mbytes/s at 24 MHz (with burst
mode)
• Memory fill operations available for writing an arbitrary constant to a block of
memory
Spring 1988
12·13
Microprocessors and Peripherals
WE 32106 Math Acceleration Unit
(Floating Point)
Description
The WE 32106 Math Acceleration Unit (MAU) provides floating-point capability for
the WE 32100 Microprocessor and is fully compatible with the IEEE standard for
binary floating-point arithmetic.
The MAU can operate in peripheral mode with general-trade microprocessors or
as a coprocessor for the WE 32100 Microprocessor. It provides single (32-bit),
double (64-bit), and double-extended (80-bit) precision for add, subtract, multiply,
divide, remainder, square root, and compare operations. The operand, result,
status, and command information transfers take place over a 32-bit bidirectional
data bus that provides the interface to the host microprocessor. The MAU is implemented in CMOS technology; is available in a 125-pin, square, hermetic,
ceramic pin grid array package; and requires a single +5 V supply.
Features
• Extended temperature available now; MIL-STO-883C (10 MHz Version) planned
availability 1988
• Compatible with ANSI/IEEE Standard 754-1985 for Binary Floating-Point Arithmetic
• Single (32-bit), double (64-bit), and double-extended (80-bit) precision capability
• Add, subtract, multiply, divide, remainder, negate, absolute value, and square root
functions
• Compare, move, and rounding to integral value functions
• Coprocessor and peripheral mode interfaces available
• Up to 1.4 million Whetstones/second
• Symmetric integer, decimal, and floating-point conversions
• 32-bit I/O interface
• Support of transcendental functions via the WE 321SG Software Generation
Programs
• Available in 10-, 14-, and 18-MHz versions
12·14
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Microprocessors and Peripherals
WE 32206 Math Acceleration Unit
(Floating Point)
Description
The WE 32206 Math Acceleration Unit (MAU) IS an enhanced coprocessor that
provides high-speed, IEEE floating-point processing support for the WE 32200
Microprocessor. The MAU can operate in peripheral mode, allowing operation with
general-trade microprocessors, or as a coprocessor for the WE 32200 Microprocessor. Systems using the WE 32206 MAU have a two-times performance
improvement over Its predecessor, the WE 32106 MAU. The WE 32206 MAU IS
footprint, protocol, and upward object code compatible with the WE 32106 MAU.
Features
• Full compliance with ANSI/IEEE Standard 754-1985 for Binary Floating-Point
Arithmetic
• Single (32-bit), double (64-bit), and double-extended (80-bit) precision capability
• Eight 80-bit user registers
• Add, subtract, multiply, divide, remainder, negate, absolute value, square root, sine,
cosine, arctan, and pi operations
• Compare, move, and rounding to Integral value functions
• On-chip trigonometric functions
• Coprocessor and peripheral mode Interfaces available
• Symmetric Integer, decimal, and floating-point conversions
• 32-bit I/O interface
• Up to three memory-based operands for each coprocessor instruction
• 24 MHz clock operation
• 3.1 million Whetstones/second
• Single +5 V supply
• Low-power, 1 micron, CMOS technology
(Refer to Section 19 for typical applications of this product.)
Spring 1988
12-15
Microprocessors and Peripherals
WE 321DM/WE 322DM
CPU and MMU Device Monitors
Description
The WE 321DM/WE 322DM CPU and MMU Device Monitors provide low-cost
solutions for debugging WE 321 001 WE 32200 Microprocessors and the
WE 32101/WE 32201 Memory Management Units.
The device monitor allows signal observation of high-speed target systems with a
logic analyzer that has 10 MHz sampling rates by:
• Generating logic analyzer sample pOints based on bus cycle activity, and
guaranteeing a minimum of 100 ns between sample points at target system
operating frequencies as high as 24 MHz.
• Sampling and holding signals as necessary to assure 30 ns signal set-up and
o ns signal hold times with respect to selected sampling points in a target system
operating frequency up to 24 MHz.
• Providing the flexibility of observing a narrow window of bus activity In detail, or
observing a larger window of bus activity with reduced detail but with a greater
perspective of system bus activity.
These device monitors support zero walt-state block fetch accesses at frequencies
of 18 MHz and 24 MHz, respectively.
12·16
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Microprocessors and Peripherals
WE 321DS Microprocessor
Development System
Description
The WE 3210S Microprocessor Development System is an integrated hardware
and software system used to develop, test, and debug WE 32100 Microprocessor
based applications. It consists of items that can be ordered Individually. The main
component of the development system IS the WE 321AP Microprocessor Analysis
Pod. The analysis pod emulates the WE 32100 Microprocessor, WE 32101
Memory Management Unit, and WE 32102 Clock functions in the target system
under development and IS essential for diagnosing target hardware and software
problems. The analysis pod includes an interactive monitor program (IMP) for
assembly-level debugging. The development system also includes the WE 321SD
Development Software Programs, a package of UNIX System based software
which runs on either an AT&T 382/300 or 400 Computer, or a VAX * 111780 Computer. This package includes utility programs for downloading the host computer.
An optional software package includes Ferret, a C-Ievel symbolic debugger. An
additional software package is available that supports logic analYSIS With the
Hewlett-Packard 64000 Logic Development System.
The WE 3210S Microprocessor Development System can operate in any of four
configurations. All four configurations require a terminal (system console) for user
Interaction with the debuggers and a +5 V power supply for the analysis pod.
These configurations are:
• Microprocessor AnalYSIS Pod Stand-Alone
• Hardware Development Workstation
• Software Development Workstation
• Hardware and Software Integrated Workstation
* Registered trademark of Digital Equipment Corporation
(Refer to Section 19 for typical applications of this product.)
Spring 1988
12-17
Microprocessors and Peripherals
WE 321EB Microprocessor
Evaluation Board
Description
The WE 321EB Microprocessor Evaluation Board is a WE 32100 Microprocessor
based single-board microcomputer evaluation system. It allows evaluation of the
hardware and software capabilities and performance of the WE 32100 Microprocessor, the WE 32101 Memory Management Unit (MMU), and the WE 32106
Math Acceleration Unit (MAU) in an application environment. The evaluation board
contains a WE 32100 Microprocessor, a WE 32101 Memory Management Unit, a
WE 32106 Math Acceleration Unit, a WE 32102 Clock, a ROM-based interactive
monitor program (IMP) and system self-test, 96 Kbytes of RAM, and I/O circuitry.
The evaluation board requires a single +5 V, 3 A power source for operation and
operates at 18 MHz.
Features
• WE 32100 Microprocessor
• WE 32101 Memory Management Unit
• WE 32106 Math Acceleration Unit
• WE 32102 Clock (18 MHz)
• 64 Kbytes of high-speed static RAM
• 32 Kbytes of additional RAM
• 64-Kbyte ROM-reSident interactive monitor program (IMP) and system self-test
program
• Program trace and breakpoint capability
• Seven individually maskable interrupts
• Twenty-four programmable parallel I/O lines
• Two RS-232C serial I/O ports with selectable baud rate (300-9600)
• Communication with terminal and with UNIX System host
• Three programmable 16-bit interval timers
• Eight-character LED display (17-segment)
• Push-button reset and abort switches
12·18
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Microprocessors and Peripherals
WE 321SG C-Software Generation
Programs (CPLU Release 4.2)
Description
The WE 321SG C-Software Generation Programs facilitate using a host UNIX
System V for creating software for the WE 32100 Microprocessor. This support
software provides utility programs that enable the user to write applications software in C language or assembly language.
The C-Software Generation Programs are binary products that satisfy a native programming environment. The WE 321SG C-Software Generation Programs replace
any other Native C compiler already installed in an AT&T 3B2 Computer System
running UNIX System V Release 2.0.5/2.1/3.0/3.1/3.1.1 or UNIX System VIVME
Release 2.1/3.1.
An additional software package that is available with the C-Software Generation
Programs, Advanced Programming Utilities EnVironment (APU), contains commands such as ctrace, lex, and yacc. These and other commands provide the
user with a set of programming tools that allow the programmer to do advanced
programming and debugging, create shared libraries, and work in an environment
where it may be necessary to track and maintain versions of files and programs.
The software generation programs can generate code in either of two floatingpoint modes, MAU or FPE. The MAU mode provides enhanced floating-point
performance through the use of in-line code generation for the WE 32106 Math
Acceleration Unit (MAU). Alternatively, at the cost of lower performance, the FPE
mode supports target systems operating both with and without a math acceleration unit. The FPE mode compiles floating-point operations as calls to library
routines that either execute MIS or emulate the operations, depending on whether
a math acceleration unit has been determined to be present at process start-up.
The software generation programs also provide high-performance math libraries,
integer and floating-point optimizations, and floating-point support that conforms to
the IEEE Standard for Binary Floating-Point ArithmetiC (ANSI/IEEE Std. 754-1985).
The C-Software Generation Programs comply completely with the UNIX System V
Interface Definition (SVID) (i.e., passes the UNIX System V Verification Suite).
Features for the WE 321SG Software Generation Programs
Utilities
• C compiler
• Object file compressor
• Assembler
• Object and archive file converter
• Link editor
• Object file dumper
• Disassembler
• Source code lister
• Object code optimizer
• Object file orderer
• Archiver and library maintainer
• Symbol table printer
• Object file host converter
• Object file stripper
(Refer to Section 19 for typical applications of this product.)
Spring 1988
12·19
Microprocessors and Peripherals
UNIX System V Release 2.1/3.1
Description
UNIX System V Release 2.1/3.1 provides the operating system and user interface
for the 32-bit WE 32100/32200 Microprocessor chip set. Optionally, this software
may be integrated by the user with an optimized version of the WE 321SG
C-Software Generation Programs for the WE 32100 Microprocessor chip set. The
operating system has been tested and certified with these optimized programs.
They provide several levels of optimization and different types of floating-point support as run-time options.
Features
• Multl-user/multi-tasking
• Enhanced C software generation system with symbolic debugging includes
shared library support
• Demand-paged virtual memory gives at least 16 Mbytes of linear address space
per process; includes U page
• File and record locking system calls provide user data protection
• Self-configuration allows installation of new drivers without regenerating the system
• Simplified system administration eliminates the need for a full-time, on-site systems
expert
• Job control language
• Cross-compilers allow program development in a large computer environment
• Exploits UNIX System oriented features of the WE 32100 Microprocessor chip set,
such as full 32-bit architecture, efficient process switching, memory management,
and optional hardware floating-point capability
• Facilitates personalization to user-developed hardware configurations
• Easy to use documentation
• Remote file sharing using Ethernet local area network
• Improved signal mechanisms
• Incremental back-up of nested files systems
12·20
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Microprocessors and Peripherals
UNIX System V Release 2.1/3.1
Additional Features for UNIX System V Release 3.1
• Internationalization, includes support for 8-bit code set, alternate date/time formats,
and character class/conversion rules
• Assists menu/forms interface
• Faster Curses/Terminfo support the writing of terminal-independent applications
• Remote file sharing (RFS)
• STREAMS Mechanism and Tools
• AT&T Transport Interface
• Media-independent uucp
• Executable shared libraries
• ASSIST Interface
• Performance improvements, including paging the user area, remote file sharing
client caching, and smaller and faster curses
• Complies completely with the UNIX System V Interface Definition Issue 2 (SVID)
(i.e., passes the UNIX System V Verification Suite Release 3)
Spring 1988
12·21
13
Opto-isolators
AT&T's complete line of
high-performance optoisolators features a high
minimum transfer ratio
and significantly low drive
current that result in
minimal power consumption. They transmit both
ac and dc signals and
can be used in analog or
digital systems. Moreover,
opto-isolators protect
against transient surges
and provide ground loop
isolation.
Page
Autopolarity IRED Input
Darlington Output
Transistor Output
13-2
13-3
Unipolarity IRED Input
Darlington Output
Transistor Output
SCR Output
Dual Transistor Output
Dual Photodiode Output
13-4
13-5
13-6
13-7
13-8
For additional information contact your
nearest sales office
or call:
1-800-372-2447.
Spring 1988
13-1
Opto-isolators
Autopolarity IRED Input
Darlington Output
Single Channel
Base
Lead to
No. 6
Pin
Specified
Input
Current
(IF)
mA
yes
yes
none
none
2.0
0.1
0.2
1.0
Current
Transfer
Ratio
(CTR)
Sustained
Voltage
[VCE(SUS)]
min
min
(ICEO)"
nA
max
7.5
60
12
12
30
100
100
100
200
V
2.0
1.8
4.0
Isolation
Current""
Pulse
Time
(IISO)
nA
max
(Tr,Tf)
100
100
100
100
100
200
200
Device
Code
Number
pS
max
4Et
4N
4H
9Et
Dual Channel
Specified
Input
Current
(IF)
mA
Current
Transfer
Ratio
(CTR)
Sustained
Voltage
min
min
(ICEO)"
nA
max
7.5
60
100
V
2.0
* Collector-Emitter Leakage Current
** Specified at (Visa) = 2500 V
Single Channel
6
[VCE(SUS)]
t
Isolation
Current""
Pulse
Time
(IISO)
nA
max
(Tr,Tf)
100
100
Dual Channel
VeE
VeE
~
~
~
4
2
2A
UL recognized (File No. E86340). Approvals can be
obtained for other devices.
8
7
+
+
6
5
~
1t
1
pS
max
VeE
5
Device
Code
Number
3
~
VF
NC
2
1
~
VF
13-2
Spring 1988
3
4
~
VF
(Refer to Section 19 for typical applications of this product.)
Opto-isolators
Autopolarity IRED Input
Transistor Output
Single Channel
Specified
Input
Current
(IF)
mA
Current
Transfer
Ratio
(CTR)
Sustained
Voltage
[VCE(SUS)]
min
min
(ICEO)·
nA
max
0.6
60
100
Current
Transfer
Ratio
(CTR)
Sustained
Voltage
V
2.0
Isolation
Current··
Pulse
Time
Device
Code
Number
(lIso)
nA
max
(Tr,Tf)
f1S
max
100
5.0
40
Isolation
Current··
Pulse
Time
Device
Code
Number
(II SO)
nA
max
(Tr,Tf)
f1S
max
100
5.0
2E
Spring 1988
13·3
Dual Channel
Specified
Input
Current
(IF)
mA
min
min
(ICEO)·
nA
max
0.6
60
100
[VCE(SUS)]
V
2.0
* Collector-Emitter Leakage Current
** Specified at (Visa) = 2500 V
Single Channel
Dual Channel
VCE
VCE
~
6
4
VCE
~
~
8
6
7
+
+
IC~
+IC
~
2
1
~
VF
5
"
3
NC
1
2
~
VF
(Refer to Section 19 for typical applications of this product.)
4
3
~
VF
Opto-isolators
Unipolarity IRED Input
Darlington Output
Single Channel
Base
Lead to
No. 6
Pin
Specified
Input
Current
(IF)
mA
yes
yes
none
none
2.0
0.7
0.2
2.0
Current
Transfer
Ratio
(CTR)
Sustained
Voltage
Isolation
Current··
Pulse
Time
(ICEO)*
nA
max
(1150)
nA
max
(Tr,Tt)
min
[VCE(SUS)]
V
min
7.5
4.0
2.0
7.5
60
60
60
60
100
100
100
100
100
100
100
100
100
100
100
100
Device
Code
Number
pS
max
4B
4C
4G
4K
Dual Channel
Specified
Input
Current
(IF)
mA
Current
Transfer
Ratio
(CTR)
2.0
0.2
Sustained
Voltage
Isolation
Current**
Pulse
Time
(ICEO)*
nA
max
(1150)
nA
max
(Tr,Tf)
min
[VCE(SUS)]
V
min
7.5
1.8
60
12
100
100
100
100
100
200
Device
Code
Number
pS
max
2B
2H
• Collector-Emitter Leakage Current
•• Specified at (Visa) = 2500 V
Single Channel
Dual Channel
VCE
VCE
~
654
+
VeE
~
~
8
6
7
+
+
~
+
1
2
'---.--J
VF
3
NC
~
IFj
+
+
1
2
~
VF
13·4
Spring 1988
5
3
4
~
VF
(Refer to Section 19 for typical applications of this product.)
Opto-isolators
Unipolarity IRED Input
Transistor Output
Single Channel
Base
Lead to
No. 6
Pin
Specified
Input
Current
(IF)
mA
none
none
yes
none
yes
none
none
1.0
1.0
2.0
2.0
1.0
0.5
0.16
Current
Transfer
Ratio
(CTR)
Sustained
Voltage
[VCE(SUS)]
min
min
(ICEO)"
nA
max
1.0
1.0
0.6
0.6
0.3
0.3
17
17
60
12
60
12
30
100
100
100
100
100
100
100
V
Isolation
Current""
Pulse
Time
(lIso)
nA
max
(Tr,Tf)
100
100
100
100
100
100
100
5.0 p..s
5.0 p..s
5.0 p..s
5.0 p..s
5.0 p..s
5.0 p's
20 ms
Device
Code
Number
max
4W
4L
4A
4J
4F
4M
4Ut
Dual Channel
Specified
Input
Current
(IF)
mA
Current
Transfer
Ratio
(CTR)
Sustained
Voltage
[VCE(SUS)]
min
min
(ICEO)"
nA
max
0.6
1.8
1.0
60
60
60
100
100
100
V
2.0
2.0
1.0
* Collector-Emitter Leakage Current
** Specified at (Visa) = 2500 V
Single Channel
+
(IISO)
nA
max
(Tr,Tf)
100
100
100
50
p..S
max
Propagation
Delay
Device
Code
Number
p..s
max
50
5.0
2C
2K
2J
Dual Channel
VeE
5
Pulse
Time
t UL recognized (File No. E86340). Approvals can be
obtained for other devices.
VeE
VeE
r----"--->
6
Isolation
Current""
~
4
8
7
~
+
+
5
6
~ ~
Ie
~
~
1Ft
1
2
"---'---'
VF
Ie
3
NC
t
IF
+
1
2
~
VF
(Refer to Section 19 for typical applications of this product.)
4
3
+
~
VF
Spring 1988
13-5
Opto-isolators
Unipolarity IRED Input
SCR Output
seR Output
Input
Current
to Trigger
(IF)
mA
min max
Holding
Current
(IH)
mA
min max
2.0
0.02
15
* Specified at (Visa)
=
2.0
Forward
On-State
Voltage
[VF(SCR)]
V
max
Reverse
Breakdown
Voltage
[VBR(R)]
Isolation
Current*
min
Forward
Breakover
Voltage
[VBR(F)]
V
min
1.5
250
250
100
V
Device
Code
Number
(1Iso)
nA
max
5A
2500 V
VF(SCR)
6
+
,--......-.
5
4
2
3
~
VF
13-6
NC
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Opto-isolators
Unipolarity IRED Input
Dual Transistor Output
Dual Transistor Output
dc
Contrast
Specified
Input
Current
Current
Transfer
Ratio
Sustained
Voltage
(K)
(IF)
mA
(CTR)
min
[VCE(SUS)]
V
min
0.6
60
±100%
1.0
Pulse
Time
(ICEO)*
nA
max
Isolation
Current
(VISO)=
1500 V
(lIso)
nA
max
(Tr,Tt)
J!S
max
100
100
5
Device
Code
Number
2L
* Collector-Emitter Leakage Current
NC
NC
8
7
VeE
~
+
Ie
6
5
+
~
t
IF
2
1
Ie
+
4
~
~
VF
VeE
(Refer to Section 19 for typical applications of this product.)
Spring 1988
13·7
Opto.lsolators
Unipolarity IRED Input
Dual Photodiode Output
Dual Photodiode Output
dc
Contrast
Breakdown
Voltage
min
max
min
Diode
Leakage
Current
(Io)
nA
max
(K)
(VBR)
V
0.80%
1.20%
60
25
Isolation
Current·
Cutoff
Frequency
(IISO)
nA
max
(Fe)
kHz
min
100
70
Device
Code
Number
20
* Specified at (Visa) = 2500 V
The 20 opto-isolator is designed for an in-circuit configuration that utilizes one of
the photodiodes of the 20 as a feedback element for stabilization. When applied
in this manner, the 20 is optimized to monitor situations where complete isolation
is necessary, and low frequency linear or dc transmission is desirable. The ratio of
one output detector to another only varies by ±0.50% when comparing ac and
dc operation over the full temperature range.
The linear epto-isolator not only replaces an isolation transformer, but it allows a
new approach by providing a means for an optically-coupled, isolated circuit.
NC
NC
8
7
1
2
+
~
VF
13·8
Spring 1988
~
Vo
(Refer to Section 19 for typical applications of this product.)
14
Power Products
Page
AT&T offers a broad spectrum of power products.
Board mounted power
modules, ranging from
2.5 to 100 watts, have a
small footprint, high
power density, and high
efficiency. The OLS Power
Supplies range in size
from 25 to 2000 watts
and offer a wide variety of
output features.
DC-DC Converters are
available in a wide range
of outputs, or custom
designed for your particular needs.
AT&T Uninterruptible
Power Systems (UPS) are
on-line, microprocessorcontrolled units that
regulate ac power in normal use and provide continuous backup in
emergencies.
The LINEAGE 2000
Energy Systems include
rectifiers, round cell batteries, and either a conventional or microprocessor-based system
controller.
Board Mounted Power Modules
14·2
Off·Line Switching Power Supplies
14·5
* DC·DC Converters
14·6
Uninterruptible Power Systems
(1, 3, 5, 10 KVA Single-Phase UPS)
* Uninterruptible Power Systems
(10, 20 KVA Three-Phase UPS)
14·8
14·9
LINEAGE 2000® Energy Systems
Battery Plants, 500A Series (MCS/CCS)
Battery Plants, 500B Series (MCS/CCS/XCS)
Battery Plants, 500C Series
Microprocessor-Controlled System (MCS) Controller
CCS Controller
XCS Controller
Rectifiers, 855 Series, 60 Hz
Round Cell Batteries
Battery Stands
Remote Access System
Secondary dc Distribution Battery Distribution
Fuse Board (BDFB)
Secondary dc Distribution Battery Distribution
Circuit Breaker Bay (BDCBB)
Typical Application
14-10
14-11
14-12
14-13
14·14
14-15
14·16
14-18
14-19
14-19
14·20
14-21
14-21
A power systems design
staff is available to assist
you in the selection of
power architectures that
meet your needs.
For additional infor·
mation contact your
nearest sales office
or call:
1-800-372-2447.
* Did not appear in the previous edition of the Product Selection Guide.
Spring 1988
14·1
Power Products
Board Mounted Power Modules
Description
AT&T Board Mounted Power Modules offer low profiles, small footprints, and high
power densities. These miniature dc-dc converters range in output power from 2.5
to 100 watts. The 900 Series is designed with both surface mount and throughhole technology on printed circuit boards. Some models have a thick-film ceramic
substrate control circuit while others have a separate PCB surface mount control
circuit. Only the 990A1, 100 watt model, requires an external heat sink. All other
900-Series modules are entirely self-contained and do not require additional components such as external filters or heat sinks.
The 990A1 Board Mounted
Power Module
A system powered by Board Mounted Power Modules offers benefits to the user.
In addition to the capability for developing non-standard voltages, the power
modules can reduce the cost of power distribution by decreasing distances
traveled by low voltages. Moreover, they can power a system on a fieldreplaceable basis, thereby yielding improved system reliability.
Features
• Low profile (as low as V2 inch)
• Efficiencies to 89%
• 2.5 to 100 watts
• High power densities
• Small footprint
• Remote on/off capability
• Remote sense
• Output current limiting/overcurrent protection
• Overvoltage protection
• Input/output isolation
• Input/output filtering
• External synchronization
• Constant voltage/constant current models
• Regulated output voltage/current
• Operating temperatures range as wide as -40 to +70OC
14-2
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Power Products
Board Mounted Power Modules
Product Matrix -
900 Series Printed Circuit Board-Based
Isolated Input/Output
Output
Input/Output
Characteristics
V (volts)
24 Volt Input
Single Output
10,0
3,5
2,2
5.0
5,0
12.0
12.0
5,0
2,1
2,2
4,6
5,0
5,2
12.0
15.0
5.0
12,0
5.2
5.0
4.2
2,0
2.0
0.833
1.0
3.0
8,0
8.0
4,1
4,0
3.8
48 Volt Input
Single Output
Product Matrix -
I (amps)
1.7
1.3
6.0
2,5
6,0
20.0
Dim.*
Code
35,0
G
984G
9,0
10,0
10,0
10,0
12.0
15,0
17.0
17,6
19,0
20,0
20,0
20.0
20,0
30,0
30,0
31.2
100,0
F
B
920D
910A
910AP1
910BP
912A
915A
984C
984L
920E
920A
920F
920B
920C
984A
984D
984B
990A1
P (watts)
K
K
E
D
G
G
F
F
F
F
F
G
G
G
H
Ceramic
Non-Isolated Input/Output
Input/Output
Characteristics
5 Volt Input
Single Output
15-60 Volt Input
Single Output
Output
Dim.*
V (volts)
I (amps)
P (watts)
Code
-130
-15
-5
15
12
0,005
0.050
0,300
0,100
0,125
0,10
0,75
1.50
1.50
1.50
113E
113C
113G
112C
112E
12
0,084
1.00
117A
* See Physical Dimensions chart, page 14-4,
Spring 1988
14-3
Power Products
Board Mounted Power Modules
Physical Dimensions
Size
Key
A
B
C
0
E
F
G
H
I
J
K
14·4
Spring 1988
Nominal Dimensions (inches)
Length
Width
Height
Pins
1.75
2.50
2.50
2.68
3.00
3.60
3.60
6.25
1.00
2.20
2.68
1.75
1.50
2.50
2.10
2.20
1.85
2.00
3.70
0.70
1.30
1.70
0.50
0.50
1.04
0.61
0.68
0.50
0.75
0.60
0.46
0.49
0.61
4
4
6
5
5
13
6
18
16
40
4
Power Products
Off·Line Switching (OLS)
Power Supplies
Description
OLS Power Supplies are high-quality, custom units designed for use in business
communication systems and computer networking and peripheral applications.
They range In size from 25 to 2000 watts and offer a wide variety of features such
as remote on-off control, remote sense, overload and thermal protection, and
various alarms and indicators. Single- or multiple-voltage outputs are available,
with input voltages consistent with domestic and foreign applications.
Features
• Meet world regulatory agency requirements, such as UL and CSA
• Meet FCC and Class A or B EMI requirements for conducted and radiated
emission
The 336A OLS Power Supply
•
Isolated input/outputs
• Inputs are surge-protected for common line transient conditions
• Outputs are overvoltage protected
• Manual or auto-ranging for worldwide input voltage ranges
• Power factor correction
• Demonstrated high reliability, designed to meet a system's need
Product Matrix
Code
Input
Voltage
332C
117 Vac
Output
Voltage(s)
(Vdc)
5
Switching
Frequency
(kHz)
Full Load
Efficiency
(OAI)
Outline
Dimensions
(in.)
60
45
75
7.77L x 6.0W x 2.95H
80
83
10.218L x 2.06W x 7.15H
Power
at Full Load
(watts)
12
-4
-48
336A
117 Vac
-52
300
631DA1
120 Vac
144 Vdc
-48
300
68
14.42L x 3.02W x 7.67H
631DB1
120 Vac
144 Vdc
-5, -48
384
75
14.42L x 3.02W x 7.67H
(Refer to Section 19 for typical applications of this product.)
Spring 1988
14-5
Power Products
DC·DC Converters
Description
AT&T's dc-dc converters are recommended to power electronic systems where
highly reliable and stable power is needed, and where small size, light weight,
and high efficiency are important. Some typical applications include digital switching systems, PBXs, and the AT&T 3B20 Computer. You can select a power unit to
meet your specific needs, or the Bell Laboratories power system engineers can
design a power system for your application or help integrate an AT&T power unit
into your system design.
Features (available on many codes)
• Power levels from 50 to 670 W
• Independent programmable output voltages for many codes
• Remote sensing with compensation for distribution voltage drops
• Overvoltage shutdown
• Low-voltage alarm
• Output current- and power-limiting
• Meet FCC class A conducted and radiated EMI
14·6
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Power Products
DC·DC Converters
Product Matrix
Input
Voltage
Output Voltage and Amps
FASTECH® Power Unit
48
5 V at 13 A,
48
5 V at 10 A,
4.8
5 V at 15 A,
48
5 V at 50 A
Packaging
5 V at 1 A
17 V at 1 A, -17 Vat 1 A
-5 V at 2 A
TRANSPAC Packaging
24
5 V at 25 A, -5 V at 13 A
48
5 V at 10 A
48
5 V at 10 A
48
12 V at 4 A
48
5 V at 30 A
48
5 V at 25 A, -5 at 13 A
48
5 V at 40 A, 5 V at 13 A
48
5 V at 22 A
Custom Packaging
24
5 V at 74 A, -5 V at 1.4 A, 12 V at 8.5 A, -12 V at 3.4 A
48
5 V at 3 A, 12 V at 2 A, -12 V at 2 A
48
5 V at 4 A, -5 V at 2 A
48
5 V at 25 A, -5 V at 7 A
48
5 V at 8 A, -5 V at 1.5 A, 12 V at 1 A, -12 V at 1 A
48
5 V at 4.4 A, 5 V at 3.9 A, -5.2 A at .5 A
48
5 V at 10.5 A, 5 V at 2 A, -5.2 V at 1.3 A,
-4.5 V at 8.5 A, 12 V at 1.3 A
48
5 V at 92 A, 12 V at 10 A, -12 V at 3 A
Watts
Size (in.)
Notes
Code
70
84
85
250
8x13x1
8x8x1.5
8x13x1
8x13x2
UL
UL
412AA
474EA
494GB
495FB
200
50
50
48
150
200
265
110
7.5x10x2.5
3.5x10x2.25
3.5x10x1.5
3.5x1Ox1.5
7.5x10x2
7.5x10x2.5
7.5x10x3
7.5x10x1
547B
323A
323C
3230
333A
547A
549A
550A
520
60
30
160
50
60
123
5x8x14
4x10x1.5
7.4x2.6x.75
8x10x2.5
3x8x2.2
3x8x1.5
3x8x4
CS785
325A
553A
555A
CS702A
CS703A
CS731
660
5x7x15
CS783A
Spring 1988
14·7
Power Products
Un interruptible Power Systems
(1, 3, S, 10 KVA Single·Phase UPS)
Description
Uninterruptible Power Systems (UPS) protect you from contaminated power and
power interruptions. An uninterruptible power system filters and regulates commercial ac, helping to insure that sensitive electronic components will not be
prematurely stressed into downtime. In the event commercial ac becomes temporarily unstable or disappears completely, the UPS will automatically use its
battery-powered backup system to supply clean, stable ac.
Features
• Cleaned, regulated, stable ac
• Reliable, competitively priced, state-of-the-art technology
• Typically 86% efficient (3, 5, and 10 KVA); 92% efficient (1 KVA)
• No need to oversize the UPS to compensate for load startup
• Microprocessor control providing automatic on-line power management
• Solid-state components
• For longer-term outages beyond the UPS reserve time, the UPS automatically
shuts down and restarts internal software when power returns
• Multiple distribution panel options
• External computer interface provided. Allows your computer to sense on-battery,
low-battery, UPS-fail, and UPS-overload conditions.
• External battery reserve available in incremental sizes (see individual data sheets
for details)
• UL listed, file 1012; IEEE C62.41 - 1980 Category B
• FCC conformance, 47 CFR, Part 15, Subpart II, Class A
• NEC conformance
• Provides for all linear and nonlinear computer power supplies over the full power
range of the UPS power
14-8
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Powe, Products
Un interruptible Power Systems
(10, 20 KVA Three-Phase UPS)
Description
The AT&T Uninterruptible Power System (UPS) is an on-line unit, using ferroresonant, parallel-processing architecture. Three modes of operation - normal, inverter, and electronic bypass - are electronically controlled to provide continuous,
regulated, transient-free power. AT&T Uninterruptible Power Systems protect sensitive electronics from natural and man-made causes of contaminated power.
Features
• Independent operation
- Operator-free, cleaned, regulated, stable ac power
- Reliable, proven, innovative parallel-processing design
- Electronic control providing automatic transient power management without
user intervention
• Cost-effective design
• On-line UPS operations in forward and reverse transfer mode. Maintains continuous sine wave output. Critical loads will not sense mode power transfer when
utility power fails.
• Typically greater than 85% efficient
• Provides 10 or 20 KVA, respectively, at full load, regardless of the type of loads
supported, thus providing lower distortion of output power
• Line filtering in all modes of operation
• UPS automatically restarts itself after an extended power outage for greater
independent operations
• External UPS interface provided to facilitate load sensing of On-battery, Lowbattery, UPS-fail, and UPS-overload conditions, for greater protection of your data
• Battery reserve in incremental sizes
• UL listed
• FCC conformance, 47CFR Part 15, Subpart II, Class A
(Refer to Section 19 for typical applications of this product.)
Spring 1988
14·9
Power Products
LINEAGE 2000 Energy Systems
The LINEAGE 2000 Energy Systems Product Family is based on a line of state-ofthe-art dc battery plants that supply continuous power to telecommunication-type
systems.
The dc battery plants are offered in various output capacities and configurations
to allow the customer to optimize the equipment for specific applications.
Rounding out the LINEAGE 2000 Energy Systems product line are plant controllers, batteries and stands, and a microprocessor-based monitoring system that
provides for remote access of various telecommunication equipment.
LINEAGE 2000 Battery Plants, 500A Series (MCS/CCS)
Description
The LINEAGE 2000, 500A Series Battery Plant, when equipped with the
Microprocessor Controlled System (MCS) or Conventional Controlled System
(CCS), is designed to provide dc power to loads of up to 6400 amps charge
capacity. The MCS Battery Plant gives you a total systems solution for reducing
energy, maintenance, training, engineering, and capital expenses by combining a
state-of-the-art, microprocessor-based controller with a flexible, modular hardware
design.
The MCS Battery Plant is an intelligent and fully integrated system. The controller,
distribution system, rectifiers, and batteries are modularly packaged to ensure
easy installation and maintenance while accommodating a wide range of current
capacities and configurations. This enables your plant to begin small and expand
capacity, hardware, and software features incrementally as demands require. This
add-on capability - and the MCS controller's ability to remotely access plant
operating data - eliminates the guesswork that can lead to excess capacity and
reduced operating efficiency.
The MCS Plant is also available in a lower cost, CCS version that can be
upgraded at a later date to a microprocessor controlled system. The CCS Battery
Plant, while providing more basic control and monitor features, does offer the
same integrated physical design as the MCS version.
Features
• Designed as a totally integrated energy system
• Up to 5200 amp discharge capacity, 6400 amp charge capacity, -48 V or ±24
V output voltages
• Long-life LINEAGE 2000 Round Cells or conventional rectangular cells available in
wide range of configurations
• AT&T LINEAGE 2000 MCS or CCS Controllers can be used
14·10
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Power Products
LINEAGE 2000 Energy Systems
• Utilizes AT&T 855 Series 25, 50, 100, 125, 200, and 400 amp rectifiers or 874
Series 35, 100, and 200 amp rectifiers
• 856 Series and 874 Series 50 Hz rectifiers are also compatible
• dc circuit breakers and fuses of up to 600 amp capacity are available for
distribution
• Improved distribution capacity using center battery distribution busbar in bays
• Interfaces with standard office alarm systems
• Circuit breaker and fuse alarm monitoring
• Connectorized rectifier interface facilitates modular growth
• Plant shunt and charge busbars are mounted external to the bay which facilitates
growth and a reduction of cable congestion
Optional Features
• Low-voltage disconnect
• Capacitor precharge feature
• Supplementary rectifier bay and/or distribution bay available
LINEAGE 2000 Battery Plants, 500B Series (MCS/CCS/XCS)
Description
The LINEAGE 2000, 500B Series Battery Plant makes optimal use of limited floor
space. The compact design takes up less room. Front access lets you position the
battery plant in almost any available space, with easy maintenance. To add to its
flexibility, the 500B can be configured using batteries that are either bay mounted
or in stands. The 500B Series is designed for use with SLC Carrier Systems.
All plant busbars and shunts are incorporated into a compact arrangement that
provides up to 400 amps of charge capacity.
Features
• Front access
• Up to 400 amp discharge capacity; ±24 V or -48 V outputs
• Up to 200 amp charge capacity in single bay arrangement
• Up to 36 dc circuit breakers arranged for front access
• Plant shunt and charge/discharge busbars inside bay
• AT&T LINEAGE 2000 MCS, CCS, or XCS Controllers can be used
• Connectorized rectifier control-cable interface
• Uses AT&T LINEAGE 2000, 855 Series 25, 50, 100, 125, 200, and 400 amp
energy-efficient rectifiers
• Optional capacitor precharge feature
• Optional supplementary rectifier bay and/or distribution bay available
• Low-voltage disconnect feature available
Spring 1988
14·11
Power Products
LINEAGE 2000 Energy Systems
LINEAGE 2000 Battery Plants, 500C Series
Description
Because the LINEAGE 2000, 500C Series Battery Plant has no dedicated frame
space and utilizes the XCS Controller, its flexibility provides a cost-effective solution
for applications such as microwave, remote switching, and lightwave radio
systems. It makes the optimum use of space, which makes it especially useful for
telecommunication equipment in a remote environment. The seven-foot frame
gives you ample room for all components.
Front access, with no-hinged panels, makes the equipment easier to get to. It
opens up areas in which to put wiring and connectors for a neater, uncluttered
job with easier accessibility for changes and maintenance. It adds up to less time
spent for installation, upgrades, and service.
The future addition of a microprocessor option board will furnish you with some of
the more important remote information furnished by the MCS Controller, as well as
provide a remote start capability. The information includes voltage, current, load
statistics, alarms, average load, and elapsed time of battery discharge.
Features
• Front access
• 400 amp capacity; ±24 V or -48 V outputs
• Plug-in circuit packs
• Monitor and control of up to six LINEAGE 2000 Rectifiers
• Connectorized rectifier control-cable interface
• Selective high-voltage shutdown of rectifiers
• Automatic restart
• LED alarm indicators
• Adjustable BD alarm (five settings)
• Adjustable HV alarm
• Single alarm and control PCB for 24 and 48 V
• Visually verifiable alarm settings (DIP switches)
• Circuit-breaker distribution up to 225 amps
• Fuse distribution up to 60 amps
• Batteries can be mounted in the primary bay (inboard) or in a supplementary bay
(outboard)
• Low-voltage disconnect option
• Optional capacitor precharge feature
• Optional supplementary rectifier bay and/or distribution bay available
14·12
Spring 1988
Power Products
LINEAGE 2000 Energy Systems
LINEAGE 2000 Microprocessor-Controlled System (MCS) Controller
Description
Unattended offices, escalating energy and maintenance expenses, and fewer
expert operating personnel have made the provision of high-reliability power
systems more important than ever. The LINEAGE 2000 MCS Controller was
designed with this environment in mind.
The MCS Controller is a firmware-based system which uses state-of-the-art
technology to continuously monitor load requirements and operation of components In a battery plant. It ensures optimal efficiency and the highest reliability
in all LINEAGE 2000 Battery Plants.
Features
• AT&T Bell Laboratories patented energy efficiency algorithm
• To maintain rectifier reliability, the MCS Controller ensures that all rectifiers have
been on and delivering current for at least 24 hours during a 30-day period
• Detailed diagnostics instruct less experienced craft people and enable them to
respond to and clear an alarm condition quickly and easily
• Plant status and diagnostics can be displayed both on the controller front panel
and on a remote terminal
• Controls up to sixteen LINEAGE 2000 Rectifiers
• Plug-in circuit packs simplify the addition of optional features and new design
developments
• Plant alarm history stores events in memory, along with the date and time of each
event
• Plant drain statistics store three highest hourly average discharge currents, three
highest peaks, and three minimums, along with date and time
• Automatic high-voltage shutdown; checks individual rectifiers for status, alarms,
output current, and malfunctions, and shuts down any rectifiers that drive the plant
voltage above specified levels
• Automatic restart of rectifiers
• Help key for technical assistance
• Back up conventional control system
• Physical dimensions: 9" high x 26" wide x 12" deep
Major Alarms
• Battery on discharge
• High battery voltage
• Discharge-fuse/circuit-breaker failure
• Major control-unit fuse failure
Spnng 1988
14-13
Power Products
LINEAGE 2000 Energy Systems
Minor Alarms
• Plant efficiency algorithm disabled
• Limited recharge capacity
• Excess plant load
• Control panel fuse failure
• Rectifier regulation fuse failure
• ac input failure
• Rectifier failure
• Rectifier circuit breaker tripped
• Rectifier manually turned off
• Microprocessor failure
• Minor-fuse failure
• Excess rectifier load
• Plant drain inconsistency
Optional Enhancements
• Remote access
• Universal shunt monitoring
• Data switch
• 300/1200 baud transmission rate
LINEAGE 2000 CCS Controller
Description
The LINEAGE 2000 Conventional Control System (CCS) Controller is ideal for
monitoring and controlling conventional battery plants, at either ±24 V or -48 V,
with up to 16 rectifiers. It provides dependable power control and alarm monitoring at low cost.
The LINEAGE 2000 CCS Controller has an MCS-compatible card cage, which
permits upgrading when the microprocessor capabilities of the MCS Controller are
needed.
Features
• Monitors and controls up to sixteen LINEAGE 2000 Rectifiers
• Connectorized rectifier control cable interface
• Selective high-voltage shutdown
• LED alarm indicators
• Plug-in circuit packs
• Dimensions: 9" high x 26" wide x 12" deep
14·14
Spring 1988
Power Products
LINEAGE 2000 Energy Systems
Major Alarms
• Battery-on discharge
• High battery voltage
• Major-fuse/circuit-breaker failure
Minor Alarms
• Rectifier failure
• Minor-fuse failure
LINEAGE 2000 XCS Controller
Description
The LINEAGE 2000 Expandable Control Systems (XCS) Controller is ideal for
monitoring and controlling battery plants, at either ±24 V or -48 V, with provision
to control up to six LINEAGE 2000 Rectifiers.
The LINEAGE 2000 XCS Controller is designed to handle a vanety of small load
applications, regardless of their distribution requirements. Its built-in flexibility
enables the power engineer to customize the distribution arrangement to best SUit
the needs of the application.
Features
• The XCS Controller is available In four basic configurations, as follows:
-
Basic Controller -
external distribution required
-
Basic Controller -
six regulation fuses and external distribution required
-
Basic Controller - internal busbars/shunt (200 amp capacity) with eight
distribution fuses and external distribution capability
-
Basic Controller - internal busbars/shunt (200 amp capacity) with SIX regulation fuses and external distribution required
• LED indicators make alarm conditions easy to read, while plug-in circuit packs
make service quick and simple
• Dimensions: 9" high x 26" wide x 12" deep
• Front access
• Monitor and control of up to six LINEAGE 2000 Rectifiers
• Connectorized rectifier control-cable interface
• Selective high-voltage shutdown of rectifiers
• Automatic restart
• Adjustable BD alarm (five settings)
• Adjustable HV alarm (five settings)
• Single alarm and control PCB for 24 and 48 V
• Visually verifiable alarm settings (DIP switches)
• Optional meters: voltage and current (analog)
Spring 1988
14-15
Power Products
LINEAGE 2000 Energy Systems
Features of Microprocessor Option Board
• Voltage
• Current
• Load statistics
• Plant alarms/history
• Battery discharge -
average load and elapsed time
• Real-time clock
• Remote restart of rectifiers
• Battery backup of memory
• User-programmable descriptors
• Plant inventory -
listing of equipment/options
LINEAGE 2000 Rectifiers, 855 Series, 60 Hz
Description
The 855 Series Rectifier product line is designed to convert commercial 60 Hz ac
input power into highly regulated and filtered low-noise, 24 or 48 volt dc output
power for telecommunications-type equipment loads. Since Central Offices usually
obtain their electrical power from potentially noisy commercial ac lines (and
emergency generators during commercial power failures), and since high quality
dc power is required in order for the equipment to operate correctly, the 855
Series Rectifier product line is an excellent choice for any telecommunications battery plant.
The 855 Series Rectifier product line offers a variety of input ac volts. The rectifier
output dc current capacities are 25, 50, 100, 125, 200, or 400 amps.
All of the 855 Series Rectifiers are both UL listed and CSA certified, with the exception of the J85503C (400 amp) rectifier. They are also compatible with all
LINEAGE Energy System products, previous AT&T plants, and most other commercial battery plants and controller systems.
Features
• Selective high-voltage shutdown
• Digital ammeter/voltmeter option
• Backup high-voltage shutdown
• Interchangeable circuit boards
• Output current "walk-in" circuit
• dc output circuit breakers
• Adjustable output current limit
• Connectorized control cable interface
• Automatic restart
• ULlCSA listing
• Output circuit breaker
• 32 dBrnC
• MCS/CCS/XCS Controller capability
• Safety interlocks
• Back-up current limit
14·16
Spring 1988
Power Products
LINEAGE 2000 Energy Systems
Rectifier Input Specifications
Phase
Capacity
(amps)
Rectifier
J-code
Input ac
(volts)
Output dc
(volts)
24
48
24
48
24
48
24
48
24
48
24
48
208
25
J85502A-1
240
208
Single
50
J85502B-1
240
208
125
J85502C-1
240
24
48
24
48
24
48
24
48
24
48
24
48
48
48
48
208
100
J85503A-1
240
480
208
Three
200
J85503B-1
240
480
400
J85503C-1
208
240
480
Spring 1988
14-17
Power Products
LINEAGE 2000 Energy Systems
LINEAGE 2000 Round Cell Batteries
Description
The LINEAGE 2000 Round Cell Battery has a revolutionary cylindrical design that
provides longer life and actually helps increase the capacity over time. Round cell
batteries deliver reliable, cost-effective backup power and are easier to handle,
install, and maintain than conventional lead-acid flooded cells.
Features
• Pure lead grids
• Polyvinyl chloride polymer jar and cover
• Oxygen index of 33, which means an exceptionally high flash point
• Heat-sealed bond (over 1,500 pounds per linear inch)
• Corrosion path five times longer than in conventional cells, thanks to specially
designed post-cover seals
• Post-cover seals whose tests indicate a leakage-free integrity in excess of 60 years
• Conically shaped grids stacked horizontally for maximum strength and material
retention
• Specific gravity of 1.215
• Recommended float voltage of 2.17 to 2.22 volts per cell
Round Cell Specifications
Specifications
Ampere hour capacity;
8-hour rate 77°F
List 1S
List 2S
List 3S
List 4S
1600
854
488
296
Change in ampere hour
capacity with time
Predicted life expectancy
(based on positive plate
growth)
Size (height
Greater than 100% at end of life
77°F
70 years
90°F
40 years
x diameter)
Weight (Ibs.)
Time required for recharge
to 90% capacity following
discharge of any fraction of cell
capacity
Inltial capacity
14-18
Spring 1988
26-3/4"
x 13-4/5"
346
18-7/8"
x 13-4/5"
15-3/8"
198
x 13-4/5"
133
Less than 24 hours
90-95%
13-5/8"
x 13-4/5"
100
Power Products
LINEAGE 2000 Energy Systems
LINEAGE 2000 Battery Stands
Description
The LINEAGE 2000 Battery Stand, made of a polyester-glass material, IS stronger,
easier to install, and more compact than metal stands, It offers greater safety and
IS the best choice for soft sites as well as earthquake and 10 or 50 pSI hardened
sites where It requires only minor additional bracing and supporting hardware,
Features
• Outstanding safety
The battery stand is made of white polyester-glass composite that is highly resistant to aCids, It is also an electrical insulator and fire retardant Any battery electrolyte that IS spilled has Virtually no path to ground, so fire hazards are greatly
reduced,
• Substantial space savings
The slimmer design of battery stands assembled In two-tier, two-row stands requires 20 percent less floor space than metal stands,
LINEAGE 2000 Remote Access System
Description
The LINEAGE 2000 Remote Access System (RAS) is a flexible, user-configured,
data-logging, and data-acquisition system designed to monitor all types of power
equipment regardless of age, vintage, or manufacturer, The sophisticated
microprocessor-based monitoring system provides accurate, up-to-the-minute
operational information, detailed alarms, diagnostics, and load statistics,
Features
• Distributed architecture minimizes installed cost, facilitates system expansion, and
ensures greater reliability with lower lead lengths
• Powerful microprocessor and generic program enables you to tailor the RAS to
your office power requirements
• Command language compatible with LINEAGE 2000 MCS Battery Plant
commands
• Both binary and analog sensing, with provisions for out-of-limits alarms that can
be tied to your existing alarm system (enhancing your alarm capability)
• Historical data on individual channels -
load statistics and alarms
• Prints three highest, three lowest, and three highest hourly averages on all
channels
• Prints active and ten most recently retired alarms
• Plenty of capacity, a total of 32 channels per unit - 16 binary (for on/off indicators) and 16 analog (for continuous readings of voltage and current values)
• Optical isolation of binary channels prevents electrical interference between channels so that only accurate information is received at the monitor from the sensor
• Binary channels can also directly sense dc voltages from 20 to 150 V and ac
voltages from 60 to 150 V at 20 Hz and 20 to 150 V at 60 to 400 Hz, Other
voltages can be sensed with minor conditioning, For analog channels, the
measurable differential voltage ranges up to 150 V ac and dc, with channel
accuracy of ±0,1% dc and ±0,7% ac, at 60 to 400 Hz,
Spring 1988
14-19
Power Products
LINEAGE 2000 Energy Systems
• Continuous monitoring - binary and analog channel measurement speed of
greater than 16 channels every 15 seconds
• Three alarms - major, minor, and watchdog, The watchdog alarm is generated if
the system executes improperly or if intermonitor communications are lost.
• Reports on all channels, selected channels, or one channel, depending on your
need
• Hourly and daily trend studies for 10-day periods on anyone channel
• Operates on dc power (±24 or ±48 volts) to maximize reliability - even during
commercial power outages - when status and alarm data are most important
• Units can be cascaded to modularly increase system capacity
• Switchable 300/1200 baud rate modem
• System can directly interface With PEERS (AT&T's Power Equipment Engineering
Record System)
• Callout on alarm, when used in conjunction with LINEAGE 2000 MCS Controller
Data Switch Option
• HELP routine with summary of commands and AT&T toll-free help number
LINEAGE 2000 Secondary dc Distribution Battery Distribution
Fuse Board (BDFB)
Description
The J85568A-1 is a general-purpose Battery Distribution Fuse Board (BDFB), It is
used when dc power is obtained from a central battery plant and must be
distributed to the equipment to be served, The BDFB is designed to distribute
±24 or -48 volt power,
It has a 1200 amp discharge capacity that is divided equally among two separate
input battery buses, Each 600 amp bus provides five panel positions that will
accommodate cartridge- or instrument-type fuses, An alarm panel is provided to
annunciate alarms, The standard digital meter allows for current measurement of
each bus load,
Features
• 1200 amp discharge capacity
• Two load buses
• Standard digital ammeter
• Input power feed from top or bottom
• Maximum to 96 fuse positions
• Accommodates fuse sizes 1 to 60
amps
• Frame alarm indicator lamp
• Individual fuse alarm indicator
14·20
Spring 1988
• Alarm circuit module for remote
sending
• Individual standard shunts
• In-frame cabling gUide
• Floor mounted
• Transparent protective back panels
• Optional appearance package
• Optional extension to accommodate
11'6" environment
Power Products
LINEAGE 2000 Energy Systems
LINEAGE 2000 Secondary dc Distribution Battery Distribution
Circuit Breaker Bay (BDCBB)
Description
The J86335 BDCBB is used where battery is obtained from large fuses on the
battery control board and divided into smaller circuits from a location near the
area to be served.
The BDCBB is designed to distribute +130, -130, +24, -24, +48, or -48 volts.
The ground bar IS arranged In 1200 amp "add on" sections and the unit may be
equipped with prewired blank panels to allow the addition of capacity for tomorrow's expansion.
The baSIC units are available in TO'; 9'0'; and 11'6" frames. Three different circuitbreaker panels are available to accommodate twelve 1-100 amp, and six
100-225 amp, or four 300-400 or two 500-600 amp breakers. An alarm control panel is provided with an indicator lamp and relays for remote alarm sending.
Features
• Floor mounted
• Individual input feed for circuit-breaker panels allow for multiple load
arrangements
• 1200 amp "add on" ground bar sections
• Power feeders enter through top or bottom
• Distribution feeders eXit through top or bottom
• Circuit breakers available from 1 to 600 amps
• Fuse alarm indicator lamp
• Alarm circuit module for remote sending
Typical Application
Application Diagram
co
MMERCIAt
AC
rv
AC RESERVE
AT&T LINEAGE 2000 Energy Systems are used for supplYing highly regulated and
filtered, low-noise, 24 or 48 volt dc output power for telecommunications-type
equipment loads in telephone Central Offices or customer premise locations.
2000 BATTERY PLANT
r - -LINEAGE
- - ----------,
HOUSE
SERVICE
BOARD
I--:--
LINEAGE 2000
LINEAGE
r---- DISTRIBUTION -,.2000
RECTIFIERS
BAY
L
I
LINEAGE
2000
CONTROLLER
r--
LINEAGE
t - - - MICROWAVE
2000
SECONDARY
LIGHTWAVE
t--DC
SYSTEM
DISTRIBUTION
PBX
LINEAGE
2000
ROUND CELLS
L _______
ELECTRONIC
SWITCHING
SYSTEMS
CELLULAR
RADIO
______ .J
LINEAGE
2000
RAS
Spring 1988
14-21
15
Printed Circuit Boards
AT&T's high-density
multilayer Printed Circuit
Boards (PCBs) bring new
levels of precision and
performance for your
complex board requirements. For applications to
22+ layers, AT&T provides
standard line widths and
spaces down to 6 mils,
and below for special
requirements.
Page
Multilayer Printed Circuit Boards
15·2
In addition to conventional plated holes and
vias, buried microvia processing is available for
designs that utilize this
feature in high-density
applications, such as surface mount technology.
AT&T offers boards that
are UL approved and
meet MIL-P-55110D. Each
board is visually inspected and electrically
tested before it leaves the
plant.
For additional information contact your
nearest sales office
or call:
1-800-372-2447.
Spring 1988
15-1
Printed Circuit Boards
Multilayer Printed Circuit Boards
Description
Custom multilayer Printed Circuit Boards (PCBs) are available in FR-4,
bismaleimide triazine, and other special materials. Surface finishes include
reflowed solder, solder mask over bare copper with hot air solder leveling, and
gold over nickel.
A standard via may be as small as .0135 Inch, and a buried microvia as small as
.008 inch.
Standard high-density capabilities include line width and line spacing to .006 Inch,
and hole sizes to .0135 inch with .025 inch lands on external layers. Three tracks
may be routed between lands on .100 inch centers on external layers as well as
innerlayers.
The Richmond Works includes a separate shop for prototypes and utilizes SOC
and SPC quality programs to ensure electrically tested, defect-free boards. All of
our customers receive personalized service, with application engineering support
available from prototypes through volume production.
Features
• Up to 22+ layers for interconnection denSity
• Surface mount technology
• Standard via, blind via, and buried mlcrovia technologies
• High-density circuitry
• Variety of materials and surface finishes
• High-aspect ratio drilling/plating
• Controlled impedance
• MIL-P-55110D qualification
• U L Approved
Processing Capabilities
No. of Layers
Board Sizes
Line Widths
Line Spaces
Hole Sizes
External Layers
Internal Layers (Buried Microvias)
15·2
Spring 1988
6+
To 16.5" x 23"
To 6 mils
To 6 mils
13 mils
8 mils
(Refer to Section 19 for typical applications of this product.)
16
Single Board Computer
The WE® 321SB VMEbus
Single Board Computer is
an open architecture
single board computer
that allows you to mix
and match peripheral and
memory boards from different suppliers to configure high performance,
demand-paged UNIX
Computer Systems. This
single board computer
features chips from the
AT&T Microprocessor
family - the WE 32100
Microprocessor, WE 32101
Memory Management
Unit, and WE 32106 Math
Acceleration Unit (see
Microprocessors and
Peripherals, section 12).
Page
WE 321SB VMEbus Single Board Computer
16·2
For additional infor·
mation contact your
nearest sales office
or call:
1-800-372-2447.
Spring 1988
16·1
Single Board Computer
WE 321SB VMEbus Single
Board Computer
Description
The WE 321SB VMEbus Single Board Computer (SBC) is a high-performance,
32-bit, single board computer that facilitates the rapid configuration of user-defined
VMEbus computer systems. Using the SBC with AT&T UNIX System VIVME, users
can design and assemble open-architecture, demand-paged UNIX Systems that
are object file and floppy disk format compatible with the AT&T 3B Computer family. Thus, many hundreds of applications and language packages available for the
3B Computers will execute directly on a VMEbus computer built using this SBC
and UNIX System VIVME. This compatibility gives SBC users immediate access to
one of the largest collections of off-the-shelf UNIX System software available today.
The VMEbus standard has many supporters and there are over 1000 commercially available bus-compatible products. UNIX System VIVME aids users who need to
add VMEbus boards to their systems. AT&T and others have developed UNIX
System VIVME Device Drivers for a number of third-party VMEbus boards. AT&T
has also released driver design documentation to help users develop their own
device drivers.
Hardware
The WE 321SB VMEbus Single Board Computer provides full 32-bit (A321D32)
master and slave interfaces to the VMEbus. The SBC operates with an on-board
system clock. On-board memory is divided into one bank of EPROM/ROM bytewide sockets and one bank of DRAM. The EPROM/ROM bank can be populated
with 2764-, 27128-, 27256-, or 27512-type EPROMs for a total of 32-, 64-, 128-,
or 256-Kbytes of EPROM, respectively. On-board is 1 Mbyte of DRAM with byte
panty. Byte, halfword (16-bit), word (32-bit), and read/modify/write accesses of
memory are supported. Refresh of the DRAM bank is handled automatically
on-board.
On-board memory management supports a full 32-bit wide virtual and physical
address space. The result is a linear 32-bit wide address space, as seen by the
programmer. The WE 32101 MMU also includes on-chip logic that supports
automatic miss-processing. The WE 32106 MAU provides both IEEE-standard
floating-point and decimal high-speed arithmetic capabilities. Operating as a
coprocessor to the WE 32100 CPU, the MAU works to off-load mathematically intensive operations from the CPU.
The WE 321SB VMEbus Single Board Computer is manufactured using AT&T advanced surface-mount technology to provide a product with an extraordinary sizeto-function ratio. With all of its features, the SBC measures just 160 by 233 mm
(6.3 by 9.2 inches), the standard double-height Eurocard size.
16·2
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Single Board Computer
WE 321SB VMEbus Single Board Computer
Firmware
A debugger/monitor program is included in on-board EPROM. EPROM contents
Include power-up board self-test and initialization. Also provided are low-level
observation and control capabilities, including program tracing, single-stepping,
register and memory examination and modification, exception and Interrupt handling, and breakpointing. Software can be cross-developed and downloaded for
stand-alone execution and development. A floppy and hard disk boot facility for
UNIX System VIVME is also included.
The on-board EPROMs can be replaced by the user, thereby facilitating the use
of user-developed firmware.
Operating Systems
AT&T is offering a highly-tuned release of UNIX System V for the WE 321SB
VMEbus Single Board Computer. UNIX System V, developed by AT&T Bell
Laboratories and available since 1982, has received worldwide acceptance as a
standardized product. UNIX System VIVME Includes the most recent enhancements from AT&T, such as demand paging, record/file locking, simplified system
administration, and remote file sharing.
UNIX System VIVME also includes device drivers for third-party system controller,
floppy/hard disk controller, and Ethernet boards. Additional device drivers are
available from AT&T and others, Including an SCSI disk and intelligent serial I/O.
Drivers may also be developed by users, following the guidelines prOVided Within
the UNIX System VIVME System Builders Reference GUide.
UNIX System VIVME users who want to develop software can use the WE 321SG
Software Generation Programs, which include an AT&T enhanced C compiler,
utilities, and optimizer. The WE 321SG Software Generation Programs are supported either in a stand-alone or cross development environment. Compilers for
other languages are available as well.
For those who require real-time operating system support, there are currently two
choices:
• C EXECUTIVE * from JMI Software Consultants
• CSX ** from Cytec Systems, Inc.
Documentation
Complete and thorough documentation is available from AT&T for the WE 321SB
VMEbus Single Board Computer and UNIX System VIVME. In addition to the
numerous documents available from AT&T addressing the UNIX Operating System
in general, over twenty product-specific documents for the SBC and UNIX System
VIVME are also available. These cover all aspects of configuration, operations, and
programming, including such areas as VMEbus system assembly, using UNIX
System VIVME, OEM modifications to System VIVME, and device driver design.
Call 1-800-372-2447 for the UNIX System VIVME Documentation Roadmap.
* Registered trademark of JMI Software Consultants, Inc.
** Trademark of Cytec Systems, Inc.
Spring 1988
16-3
17
Transformers and Inductors
AT&T designs and
manufactures over 6000
different transformers and
inductors for your electronic and power applications. Our product line
includes a broad range of
both custom- and
standard-designed components and uses a wide
variety of physical structures, core materials, configurations, and winding
technologies. After the
components are designed
and tested for both quality and reliability, they are
coded for your selection.
Page
Electronic Circuit "n'ansformers
and Inductors
17·2
Power "n'ansformers and Inductors
17·5
AT&T supports its
transformer and inductor
product line with full
customer service and applications engineering.
For additional infor·
mation contact your
nearest sales office
or call:
1-800-372-2447.
Spring 1988
17-1
Transformers and Inductors
Electronic Circuit Transformers
and Inductors
Electronic circuit transformers and inductors are used in telecommunication and
other small signal applications for:
• Voltage or current conversion
• Impedance matching
• Direct current (dc) Isolation
• Signal splitting or combining
• Electromagnetic Interference/Radio Frequency Interference (EMI/RFI) suppression
• Signal filtering
Our product line offers a wide range of standard- and custom-designed
transformers and inductors.
The 2718AM Transformer
was designed for the ISDN
SIT Interface.
Transformer Types
• AudioNoice Frequency - for use where the supplied frequency is in the 20 Hz to
20 kHz range with or without superimposed direct current.
Some of the application-related transformers in thiS category are:
- Input
- Line
- Output
- Modem
- Interstage
- Telephone interconnect
- Driver
- VOice/data coupling
• Wide Band - for carrier frequencies (40 kHz to 30 MHz), radio frequencies,
video and microwave intermediate frequencies up to 500 MHz.
• Low-Power Pulse - pulse duration from microseconds to milliseconds, rise time
from nanoseconds to microseconds, and ET constants (pulse amplitude multiplied
by duration in microseconds) up to 4500.
Some digital transmission applications are:
-
DSO
DS1
DS1C
DS3
-
ISDN SIT Interface
ISDN U Interface
- LAN
• Hybrid - for signal combining and splitting with the ability to electrically isolate
ac signals from one port while transmitting them to other ports.
17-2
Spring 1988
(Refer to Section 19 for typical applications of this product.)
ll-ansformers and Inductors
Electronic Circuit Transformers and Inductors
Inductor Types
• AudioNoice Frequency -
fixed toroidal type.
• High Frequency, High Q • Choke Coil -
adjustable and fixed types, pot core
fixed type, variety of cores.
Based on your circuit criteria, the Product Matrices on the following two pages will
help you deterrnlne the AT&T transforrner structure that best SUitS your needs.
Product Matrix -
Audio/Voice and Wide band Transformers
240
a::
-0
a: x
40
0
PULSE TRANSFORMER STRUCTURES
17-4
W:::l::::1
2732
o
2718
•
2661,2662,2664,2745
Spnng 1988
Transformers and Inductors
Power Transformers and Inductors
The power transformers and inductors product line offers you a broad selection of
embedded and common power magnetic structure components. The listing below
shows examples of our broad range of standard- and custom-designed transformers and Inductors, followed by a brief description of their applications The
magnetics are organized In two categories - high and low frequency
High-Frequency Applications
• Inductors
- Common Mode - used In sWitch-mode power supplies to reduce ac line conducted Interference.
- Output Coupled Power - used In the output Inductor capacitor (LC) sections
of multiple output sWitch-mode power supplies
- Output Power supplies.
used In the output LC filter section of switch-mode power
- Snubber - used in sWitch-mode power supplies to limit peak currents that are
generated due to parasltlcs.
• Transformers
- Current Sense another level.
used to change the input current to an output current at
- Driver - used to trigger the base of a bipolar transistor or the gate of a fleldeffect transistor (FET).
- Flyback -
used to store and transfer energy.
- Unipolar and Bipolar Waveform - used to convert dc power at one voltage
and Impedance level to a different level.
Low-Frequency Applications
• Inductors
- Alternating Current (ac) Power -
used In power circuits.
- Commutating Power - used in a semiconductor circuit to limit the rate of
change of current during the on-time and off-time of the excitation cycle.
- Direct Current (dc) Power regulated rectifier.
a basic component of the filter section of a
(Refer to Section 19 for typical applications of this product.)
Spring 1988
17-5
Transformers and Inductors
Power 'n'ansformers and Inductors
• Transformers
- Current Sense another level.
used to change the input current to an output current at
- Ferroresonant supplies.
used in battery charging systems and in uninterruptible power
- Power Line voltage level.
converts power at one input voltage level to a different output
Based on your circuit criteria, the Product Matrix will help you determine the AT&T
magnetic component structure that best SUitS your needs.
Product Matrix
POWER TRANSFORMER AND INDUCTOR PRODUCT SPECTRUM
LOW FREQUENCY
INDUCTORS
de
ae
POWER
POWER
COMMUTATING
. -_ _-+T:..:.R"-A::.,:N.::.SF:..:.O"'-'RMERS
FERRORESONANT
POWER
LINE
CURRENT
SENSE
COMMON
MODE
OUTPUT
POWER
OUTPUT
COUPLED
POWER
SNUBBER
TRANSFORMERS
DRIVER
POWER CONVERTER
FLYBACK
17·6
Spring 1988
UNIPOLAR BIPOLAR
WAVEFORM WAVEFORM
CURRENT
SENSE
18
Wire & Cable (Electronic)
AT&T's extensive line of
copper-based, electronic
wire and cable is specially designed for digital
data transmission. The
products include conventional, enhanced performance, and specialized
performance cable
families, all utilizing
twisted-pair construction.
Page
Conventional Cables
18·2
Enhanced Performance Cables
18·8
Specialized Performance Cables
18·12
Color Codes
18·15
The conventional cables
are interchangeable with
industry-standard commercial cables. The
enhanced-performance
cables incorporate foam
skin insulation for lower
capacitance and smaller
diameters. The
special ized-performance
cables are small-pair-size,
shielded cables designed
for high-performance
applications.
For additional information contact your
nearest sales office
or call:
1-800-372-2447.
Spring 1988
18·1
Wire & Cable (Electronic)
Conventional Cables
Description
AT&T offers a full line of conventional cables that are Interchangeable with industrystandard commercial cables. These cables are either unshielded or shielded
multi pair cables, and utilize twisted-pair construction. This construction involves
twisting Individual conductors and grouping these pairs to form a core or unit for
a larger cable. Twisted-pair construction provides greater separation between
pairs, minimizing crosstalk between adjacent pairs.
Shielded cables are used in electronically sensitive locations, where it is desirable
to control interference.
Features
• High error-free transmission rates
1705 Conventional Cable
• U L approved
• High maximum operating temperature -
up to 90°C
22 AWG (7x30) Stranded Conductors, Twisted Pairs -
1003
Number of Pairs: 1, 2, 3, 4, 6, 9, 12
UL Recognized - 20399: 90°C, 150 V and
UL Listed Type CM: 60°C, 300 V
Nominal Parameters:
Mutual Capacitance: 15.9 pFfft.
DC Resistance: 15.3 Q/1000 ft.
Impedance Zo: 113 0 @ 1 MHz
Error-Free Transmission Rates:
1.54 M bfs up to 3200 ft.
3.1 Mbfs up to 1700 ft.
6.3 Mbfs up to 1400 ft.
Conductors: Tinned Copper
Insulation: Semirigid PVC
Jacket: Gray PVC
Color Code: #3
18-2
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Wire & Cable (Electronic)
Conventional Cables
20 AWG (7x28) Stranded Conductors, Mixed Pairs -
1144
Number of Pairs: 2
UL Recognized - 20399: 90°C, 150 V and
UL Listed Type CM: 60°C, 300 V
Nominal Parameters:
Mutual Capacitance: 55 pF/It.
DC Resistance: 9.8 0/1000 It
Impedance Zoo 38 a @ 1 MHz
Error-Free Transmission Rates:
1.54 M b/s up to 900 ft.
3.1 Mb/s up to 500 ft.
6.3 Mb/s up to 300 ft.
Conductors. Tinned Copper
Insulation· Semirigid PVC
Jacket· Gray PVC
Color Code Red/Black
Green/White
Shield: Red/Black pair has longitudinal foil shield
Dram Wire. 22 AWG stranded tinned copper
22 AWG (7x30) Stranded Conductors, Shielded Pair -
1201
Number of Pairs: 1
Maximum Operating Temperature 90°C
UL Listed Type CM: 60°C, 300 V
Nominal Parameters:
Mutual Capacitance 31.6 pFIft.
DC ReSistance: 15.3 0/1000 ft.
Impedance Zo 61 a @ 1 MHz
Error-Free Transmission Rates:
1.54 Mb/s up to 800 ft.
3.1 Mb/s up to 400 ft.
6.3 Mb/s up to 200 ft.
Conductors: Tinned Copper
Insulation: PP
Jacket: Gray PVC
Color Code. Black and Red
Shield: Longitudinal polyester-aluminum foil overshield
Drain Wire: 22 AWG stranded tinned copper
Spring 1988
18·3
Wire & Cable (Electronic)
Conventional Cables
22 AWG Solid Conductors, Shielded Pair -
1202
Number of Pairs: 1
Maximum Operating Temperature 90°C
UL Listed Type CM: 60°C, 300 V
Nominal Parameters:
Mutual Capacitance 33.1 pF/ft.
DC Resistance: 16.4 Q/1000 ft.
Impedance Zo: 57 n @ 1 MHz
Error-Free Transmission Rates:
1.54 Mb/s up to 700 ft.
3.1 Mb/s up to 400 ft.
6.3 Mb/s up to 250 ft.
Conductors: Tinned Copper
Insulation: PP
Jacket: Gray PVC
Color Code: Black and Red
Shield: Longitudinal polyester-aluminum foil overshleld
Drain Wire: 22 AWG solid tinned copper
22 AWG (7x30) Stranded Conductors, Shielded Pairs -
1221
Number of Pairs: 2
Maximum Operating Temperature 90°C
UL Listed Type CM: 60°C, 300 V
Nominal Parameters:
Mutual Capacitance: 31.6 pF/ft.
DC Resistance: 15.3 Q/1000 ft.
Impedance Zoo 61 n @ 1 MHz
Error-Free Transmission Rates:
1.54 Mb/s up to 800 ft.
3.1 Mb/s up to 400 ft.
6.3 Mb/s up to 200 ft.
Conductors: Tinned Copper
Insulation PP
Jacket: Gray PVC
Color Code: Red/Black
Green/White
Shield: Each pair individually shielded with longitudinal polyester-aluminum foil
Drain Wire: 24 AWG stranded tinned copper
18-4
Spring 1988
Wire & Cable (Electronic)
Conventional Cables
22 AWG (7x30) Stranded Conductors, Shielded Pairs -
1222
(Low-Voltage Computer Cable)
Number of Pairs: 3, 4, 6
UL Recognized - 2919: BOcC, 30 V and
UL Listed Type CM: 60 cC, 300 V
Nominal Parameters:
Mutual Capacitance: 32.0 pFIft.
DC ReSistance: 15.3 nl1000 ft.
Impedance Zo: 58 n @ 1 MHz
Error-Free Transmission Rates:
1.54 Mb/s up to 800 ft.
3.1 Mb/s up to 500 ft.
6.3 Mb/s up to 300 ft.
Conductors: Tinned Copper
Insulation. PP
Jacket Gray PVC
Color Code' #3
Shield. Each pair individually shielded with longitudinal polyester-aluminum foil
Drain Wire. 22 AWG stranded tinned copper, one each pair
22 AWG (7x30) Stranded Conductors, Cabled -
1603
Number of Conductors: 3, 4, 5, 10, 12
UL Recognized - 20399: 90 cC, 150 V and
UL Listed Type CM: 60 cC, 300 V
Nominal Parameters:
Capacitance: C1: 154 pFIft.
C2: 284 pFIft.
DC Resistance 16.2 nl1000 ft.
Conductors' Tinned Copper
Insulation. Semirigid PVC
Jacket: Gray PVC
Color Code: #1
18 AWG (19x30) Stranded Conductors, Cabled -
1705
Number of Conductors: 4
UL Recognized - 20399: 90 cC, 150 V and
UL Listed Type CM: 60 cC, 300 V
Nominal Parameters:
Capacitance: C1: 46.6 pFIft.
C2: 93.3 pF/ft.
DC Resistance: 64 n/1000 ft.
Conductors: Tinned Copper
Insulation: Semirigid PVC
Jacket: Gray PVC
Color Code: Black, Red, White, Green
Shield: Longitudinal polyester-aluminum foil overshleld
Drain Wire: 20 AWG stranded tinned copper
Spring 1988
18·5
Wire & Cable (Electronic)
Conventional Cables
22 AWG (7x30) Stranded Conductors, Cabled -
1764
Number of Conductors: 2
UL Recognized - 2092: 60°C, 300 Vand
UL Listed Type CM: 60°C, 300 V
Nominal Parameters:
Capacitance. C1: 24.0 pF/ft
C2 47.0 pF/ft.
DC Resistance: 16.2 W1000 ft.
Conductors: Tinned Copper
Insulation PE
Jacket. Gray PVC
Color Code: Black and Clear
Shield Longitudinal polyester-aluminum foil overshield
Drain Wire. 22 AWG stranded tinned copper
24 AWG (7x32) Stranded Conductors, Twisted Pairs, Shielded
(Low-Voltage Computer Cable;
RS-232 Application)
Number of Pairs: 2, 4112, 9, 12112, 18'/2
UL Recognized - 2448
Nominal Parameters:
Mutual Capacitance: 13.2 pF/ft.
DC Resistance: 24.2 W1000 ft.
Impedance: 120 Q (±10%) at 1 MHz
Conductors: Tinned Copper
Insulation: Polyethelene
Jacket: Black PVC
Color Code. Combination of #1 and #4
Shield: Longitudinal polyester-aluminum fOil overshleld
Drain Wire: 24 AWG stranded tinned copper
18-6
Spring 1988
Wire & Cable (Electronic)
Conventional Cables
OIW 4 Pair
Number of Pairs: 4-600
UL Listed Type CMR (24 AWG)
and Type CM (22 AWG): 60°C, 300 V
Representative Electrical and Transmission Characteristics:
Error-Free Bit Rates (24 gauge)'
1.6 Mb/s (T1 Rate) up to 2600 ft.
3.15 Mb/s (T1C Rate) up to 1600 ft.
6.3 Mb/s (T2 Rate) up to 1000 ft.
Conductor Resistance.
24 gauge: 25.7 Ul1000 ft.
22 gauge' 16.2 nl1000 ft.
Mutual Capacitance: 15-20 pF/ft.
Color Code Pair No.
1
2
3
4
4 Pair Cable:
Color
BI/W-BI
O/W-O
G/WG
Br/WBr
22 and 24 AWG Ha/ar* fHa/ar Plenum Cable -
26010, 20010, 26020
Number of Conductors and Pairs: 2 Cond, Triple, Quad, Pairs 1 Thru 100
Temperature Range to 150°C
UL Listed - Type CMP
Nominal Parameters:
Mutual Capacitance: 16 pFIft. (pairs)
DC Resistance: 25.8 nl1000 ft. (24 gauge)
16.5 nl1000 ft. (22 gauge)
Impedance: 100 (±10%) n @ 1 MHz
Attenuation: @ 1 kHz = 0.55 dB/1000 ft.
@ 1 MHz = 6.06 dB/1000 ft.
Error-Free Transmission Rates**: (20010)
2800 ft. @ 1.54 M b/s
1600 ft. @ 3.1 Mb/s
1400 ft. @ 6.3 Mb/s
Conductors: Solid, Annealed Copper
Insulation: ECTFE
Jacket: ECTFE
* Registered trademark of the Ausimont Corporation
** Bipolar, one-way transmission
Spring 1988
18·7
Wire & Cable (Electronic)
Enhanced Performance Cables
Description
AT&T's line of enhanced performance cables use foam/skin insulation, which allows
lower capacitance values and smaller diameters. Data rates and transmission
distances, before amplification or regeneration IS required, are also enhanced.
Most of the applications for these cables are at the system Interconnect level,
including computers, mass storage devices, peripherals, and terminals. The
cables are also used for business machines, data communication equipment, data
recording equipment, and programmable controllers.
All of these enhanced performance cables are shielded, multipair cables that
utilize twisted-pair construction. This provides greater separation between pairs,
thereby minimizing crosstalk between adjacent pairs.
1249 Enhanced
Performance Cable
Features
• High data rates
• Error-free transmission
• Longer transmission distances
26 AWG (7x34) Stranded Conductors, Twisted Pairs -
1241
Number of Pairs: 2, 3, 4, 6, 9, 12
UL Listed Type CL2
Nominal Parameters:
Mutual Capacitance: 11 pFIft.
DC Resistance' 41 011000 ft.
Impedance Zo: 138 n @ 1 MHz
Error-Free Transmission Rates:
1.54 Mb/s up to 1000 ft.
3.1 Mb/s up to 500 ft.
6.3 Mb/s up to 400 ft.
Conductors: Tinned Copper
Insulation: Dual, semirigid PVC skin over foamed PE
Jacket: Gray PVC
Color Code: #4
Shield: Longitudinal polyester-aluminum foil overshield
Drain Wire: 26 AWG stranded tinned copper
18-8
Spring 1988
(Refer to Section 19 for typical applications of this product.)
Wire & Cable (Electronic)
Enhanced Performance Cables
24 AWG (7x32) Stranded Conductors, Twisted Pairs -
1242
Number of Pairs: 2, 3, 4, 6, 9, 12112, 18112
UL Listed Type CL2
Nominal Parameters:
Mutual Capacitance: 13 pF/ft.
DC Resistance: 25.7 Ul1000 ft.
Impedance Zo: 138 fl @ 1 MHz
Error-Free Transmission Rates:
1.54 Mb/s up to 1200 ft.
3.1 Mb/s up to 700 ft.
6.3 Mb/s up to 600 ft.
Conductors Tinned Copper
Insulation: Dual, semirigid PVC skin over foamed PE
Jacket: Gray PVC
Color Code: #4
Shield: Longitudinal polyester-aluminum foil overshield
Drain Wire: 24 AWG stranded tinned copper
24 AWG Solid Conductors, Twisted Pairs -
1245
Number of Pairs: 2, 3, 4, 6, 9, 12
UL Listed Type CL2
Nominal Parameters:
Mutual Capacitance: 11 pFIft.
DC Resistance: 26.5 fl/1000 ft.
Impedance Zo: 138 fl @ 1 MHz
Error-Free Transmission Rates:
1.54 M b/s up to 2200 ft.
3.1 Mb/s up to 1400 ft.
6.3 M b/s up to 1200 ft.
Conductors: Tinned Copper
Insulation: Dual, semirigid PVC skin over foamed PE
Jacket: Gray PVC
Color Code: #4
Shield: Longitudinal polyester-aluminum foil overshield
Drain Wire: 24 AWG solid tinned copper
Spring 1988
18-9
Wire & Cable (Electronic)
Enhanced Performance Cables
26 AWG Solid Conductors, Twisted Pairs (Coax Replacement)
1247
Number of Pairs: 18
UL Listed Type CL2 and CSA Certified
Nominal Parameters:
Mutual Capacitance: 12.7 pF/ft.
DC Resistance: 41 nt1000 ft.
Impedance Zo: 118 fl @ 1 MHz
Error-Free Transmission Rates:
3 Mb/s up to 200 ft. (unbalanced mode)
3 Mb/s up to 900 ft. (balanced mode)
Conductors: Tinned Copper
Insulation: Dual, semirigid PVC skin over foamed PE
Jacket Beige PVC, Inner and outer
Color Code: #2
Core Wrap: Polyester film
Shield: Longitudinal polyester-aluminum foil overshleld
Drain Wire: 24 AWG stranded tinned copper
26 AWG Solid Conductors, Twisted Pairs -
1249
Number of Pairs: 4, 6, 12, 16, 20, 25, 32, 50
UL Listed Type CL2
Nominal Parameters:
Mutual Capacitance: 12.5 pF/ft.
DC Resistance 41 nt1000 ft.
Impedance Zo: 120 fl @ 1 MHz
Error-Free Transmission Rates:
1.54 M b/s up to 2700 ft.
3.1 Mb/s up to 1400 ft.
6.3 Mb/s up to 1100 ft.
Conductors: Tinned Copper
Insulation: Dual, semirigid PVC skin over foamed PE
Jacket Gray PVC
Color Code: #2
Shield: Dual longitudinal polyester-aluminum foil overshleld
Drain Wire: 26 AWG solid tinned copper
18·10
Spring 1988
Wire & Cable (Electronic)
Enhanced Performance Cables
24 AWG Solid Conductors, Twisted Pairs -
1251
Number of Pairs: 2, 3, 4, 6, 9, 12
UL Listed Type CL2
Nominal Parameters:
Mutual Capacitance: 18 pF/ft.
DC Resistance: 25.7 011000 ft.
Impedance Zo 92 n @ 1 MHz
Error-Free Transmission Rates:
1.54 Mb/s up to 1900 ft.
3.1 Mb/s up to 1100 ft.
6.3 Mb/s up to 700 ft.
Conductors. Tinned Copper
Insulation. Dual, semirigid PVC skin over foamed PE
Jacket: Gray PVC
Color Code: #4
Shield Longitudinal polyester-aluminum foil overshield
Drain Wire: 24 AWG stranded tinned copper
24 AWG (7x32) Stranded Conductors, Twisted Pairs -
1254
Number of Pairs: 2, 3, 4, 6, 9, 12, 12112, 18112
UL Listed Type CL2
Nominal Parameters:
Mutual Capacitance: 18 pFIft.
DC Resistance: 25.7 011000 ft.
Impedance Zo: 92 n @ 1 MHz
Error-Free Transmission Rates:
1.54 Mb/s up to 1100 ft.
3.1 Mb/s up to 600 ft.
6.3 M b/s up to 400 ft.
Conductors: Tinned Copper
Insulation: Dual, semirigid PVC skin over foamed PE
Jacket: Gray PVC
Color Code: #4
Shield: Longitudinal polyester-aluminum foil overshield
Drain Wire. 24 AWG stranded tinned copper
Spring 1988
18-11
Wire & Cable (Electronic)
Specialized Performance Cables
Description
AT&T's specialized performance cables are small-pair-size shielded data communication cables, using a pair twist scheme that minimizes crosstalk in the
balanced pair mode. They are designed for use in digital channel banks, local
area networks, and applications where joint voice and data communications within
the same jacket are required. Specialized performance cables can be used to
interconnect data processing equipment, terminals, and digital switching networks.
Features
• Specialized designs
• Minimized crosstalk
• Voice/data applications
1281 Speclall_d
Performance Cable
Local Area Network (LAN) Cable -
1283
Number of Pairs: 2, 4
UL Listed Type CM: 60°C, 300 V
Voice Pairs
Data Pairs
19
12
43
122
Nominal Parameters:
Mutual Capacitance (pF/ft.):
DC Resistance (011000 ft.):
Impedance Zo (0 @ 4 MHz):
28
95
Error-Free Transmission Rates:
1.54 Mb/s up to 2700 ft.
3.15 Mb/s up to 1700 ft.
6.3 Mb/s up to 1500 ft.
Voice Pairs
18-12
Spring 1988
Data Pairs
Conductors:
24 AWG Bare Copper
26 AWG Tinned Copper
Insulation:
Semirigid PVC
Dual, Semirigid PVC skin over
foamed PE
Jacket:
Outside Gray PVC
Individual Gray PVC
Color Code:
#4
Red/Green
Black/Orange
Shield:
None
Longitudinal polyester-aluminum foil
Drain Wire:
None
24 AWG solid tinned copper
(Refer to Section 19 for typical applications of this product.)
Wire & Cable (Electronic)
Specialized Performance Cables
Local Area Network (LAN) Cable -
2281
Number of Pairs: 2, 4
UL Listed Type CMP
Voice Pairs
Data Pairs
19
28
95
10.3
41
132
Nominal Parameters:
Mutual Capacitance (pF/ft.):
DC Resistance (0/1000 ft.):
Impedance Zo (0 @ 4 MHz):
Error-Free Transmission Rates:
1.54 M b/s up to 2900 ft.
3.1 Mb/s up to 1800 ft.
6.3 Mb/s up to 1600 ft.
Voice Pairs
Data Pairs
Conductors:
24 AWG Bare Copper
26 AWG Tinned Copper
Insulation:
Semirigid PVC
Dual, Semirigid PVC skin over
foamed PE
Jacket:
Outside Transparent
PVDF
Individual Transparent ECTFE
Color Code:
#4
Red/Green
Black/Orange
Shield:
None
Longitudinal polyester-aluminum foil
Drain Wire:
None
24 AWG solid tinned copper
Thermal
Barrier:
None
TEFLON * tape
26 AWG Solid Conductors, Twisted Pairs -
1205
Number of Pairs: 2, 5
Maximum Operating Temperature 90°C
UL Listed Type CM: 60°C, 300 V
Nominal Parameters:
Mutual Capacitance: 14.5 pF/ft.
DC Resistance: 41 011000 ft.
Impedance Zoo 100 0 @ 1 MHz
Error-Free Transmission Rates:
1.6 Mb/s up to 2600 ft.
3.15 Mb/s up to 1700 ft.
6.3 Mb/s up to 1100 ft.
Conductors: Tinned Copper
Insulation: PP
Jacket: Gray PVC
Color Code: #5
Core Wrap: Polyester Film
Shield: Longitudinal polyester-aluminum foil overshield
Drain Wire: 26 AWG solid tinned copper
* Registered trademark of the DuPont Company
Spring 1988
18·13
Wire & Cable (Electronic)
Specialized Performance Cables
Local Area Network (LAN) Cable -
1281
Number of Pairs: 2
UL Listed Type CM: 60°C, 300 V
Voice Pairs
Data Pairs
Mutual Capacitance:
(pF/ft)
13
9.6
DC Resistance:
(Q/1000 ft.)
18
16.4
Impedance Zo:
(I) @ 1 MHz)
118
146
Nominal Parameters:
Error-Free Transmission Rates:
1.54 M b/s up to 3500 ft.
3.1 Mb/s up to 2300 ft.
6.3 Mb/s up to 2000 ft.
Voice Pairs
18·14
Spring 1988
Data Pairs
Conductors:
22 AWG Tinned Copper
26 AWG Tinned Copper
Insulation:
Dual, Semirigid PVC
skin over PE
Dual, Semirigid PVC skin over
foamed PE
Jacket:
Outside Gray PVC
Individual Gray PVC
Color Code:
Blue-White/White-Blue
Green-White/White-Green
Orange/White
Brown/White
Shield:
None
Longitudinal polyester-aluminum foil
Drain Wire:
None
24 AWG solid tinned copper
Wire & Cable (Electronic)
Color Codes
Color Code #1
Color Code #2
Condo
No.
Color
Pair
No.
1
2
3
4
5
Black
White
Red
Green
Brown
1
2
3
4
5
Blue/White
Orange/White
Green/White
Brown/White
Slate/White
6
7
8
9
10
Blue
Orange
Yellow
Violet
Slate
6
7
8
9
10
Blue/Red
Orange/Red
Green/Red
Brown/Red
Slate/Red
11
12
Pink
Tan
11
12
13
14
15
Blue/Black
Orange/Black
Green/Black
Brown/Black
Slate/Black
16
17
18
19
20
Blue/Yellow
OrangelYeliow
GreenlYellow
Brown/Yellow
SlatelYeliow
21
22
23
24
25
BluelViolet
OrangelViolet
GreenlViolet
BrownlViolet
SlatelViolet
Color Code #3
Pair
No.
Colors
1
2
3
4
5
Black/Red
Black/White
Black/Green
Black/Blue
Black/Yellow
6
7
8
9
10
Black/Brown
Black/Orange
Red/White
Red/Green
Red/Blue
11
12
13
14
15
RedlYellow
Red/Brown
Red/Orange
Green/White
Green/Blue
16
17
18
19
20
GreenlYeliow
Green/Brown
Green/Orange
White/Blue
WhitelYellow
Colors
Spring 1988
18-15
Wire & Cable (Electronic)
Color Codes
18-16
Spring 1988
Color Code #4
Color Code #5
Pair
No.
Pair
No.
Color
1
2
3
4
5
White-Blue/Blue
White-Orange/Orange
White-Green/Green
White-Brown/Brown
White-Slate/Slate
6
7
8
9
10
Red-Blue/Blue-Red
Red-Orange/Orange-Red
Red-Green/Green-Red
Red-Brown/Brown-Red
Red-Slate/Slate-Red
11
12
13
14
15
Black-Blue/Blue-Black
Black-Orange/Orange-Black
Black-Green/Green-Black
Black-Brown/Brown-Black
Black-Slate/Slate-Black
16
17
18
19
20
Yellow-Blue/Blue-Yellow
Yellow-Orange/Orange-Yellow
Yellow-Green/Green-Yellow
Yellow-Brown/Brown-Yellow
Yellow-Slate/Slate-Yellow
21
22
23
24
25
Violet-Blue/Blue-Violet
Violet-Orange/Orange-Violet
Violet-Green/Green-Violet
Violet-Brown/Brown-Violet
Violet-Slate/Slate-Violet
1
2
3
4
5
Colors
Blue/White-Blue
Orange/White-Orange
Green/White-Green
Brown/White-Brown
Slate/White-Slate
TYpical Applications
19
1\fpical Applications
The following pages
describe selected industry
applications that require
sophisticated electronic
components. Each is
characterized by a system
diagram that illustrates
the functional elements of
the application. Accompanying each element is
a list of specific AT&T
devices, identified by product line, that can be
utilized. Devices which
are generally applicable
to any element are listed
at the top of each
diagram. A ( ) reference
after a device indicates
the page where the
device is fully described.
The applications presented are suggestions
that can be adapted for
your specific needs.
When you see the versatility of AT&T's Component Products, we think
you will agree that
whatever your application,
we can become partners
in technology... and in
success.
For additional infor·
mation contact your
nearest sales office
or call:
1-800-372-2447.
Page
Computers
Multiuser Microsystems
Workstations
Storage Products
19-2
19·4
19·6
Data Communications
Local Area Networks (LANs)
19-8
Telecommunications
Loop Carrier Systems
Private Branch Exchanges (PBXs)
Digital Cross-Connect Systems
19·10
19-12
19·14
Industrial
Manufacturing Automation Protocol (MAP) LANs
Cell Controllers
19-16
19-18
AT&T's product lines are identified as follows:
(ALOG)
(ASIC)
(CAP)
(COMM)
(DBIC)
(DSP)
(FIBER)
(FREQ)
(GaAs)
(HYBRID)
(MICRO)
(PCB)
(POW)
(SBC)
(T&I)
(W&C)
Analog Integrated Circuits
Application Specific Integrated Circuits
Capacitors
Communication Integrated Circuits
Digital Bipolar Integrated Circuits
Digital Signal Processors
Fiber Optics
Frequency Control Products
Gallium Arsenide Integrated Circuits
Hybrid Integrated Circuits
Microprocessors and Peripherals
Printed Circuit Boards
Power Products
Single Board Computer
Transformers and Inductors
Wire and Cable (Electronic)
Spring 1988
19·1
Typical Applications
Computers
Multiuser Microsystems
Application Description
Multiuser microsystems are used as file servers, print servers, and communication
servers, as well as a central CPU for dumb terminals.
-----~
L-_ _ _ _ _ _ _ _ _ _ r
_
--_-_-_-_-_-_....J_~======.:;_~====== (FIBER)
.......- ' - _ . . , (DSP) DSP16132 (7·2 to 7-13)
(DBIC) LINE RECEIVERI
DRIVER (6·2 10 6-4)
(MICRO) DMAC (12·10)
L-,.......,...._.....J (ALOG) ALA400 (2·32)
/"
_
SERIAL
(ALOG) LINEAR
ARRAYS (2·32)
(COMM) X 25 (5·33)
(COMM) DIG ENCRYPTION PROC (5·28)
(COMM) CLOCK RECOVERY (5-47 to 5·49)
(COMM) HDLC FORMATTERS (5-10. 5-25. 5·26)
(COMM) ARTI (5-12)
(FIBER) DOL (8-2 to 8-8)
WINCHESTER
-------1
FLOPPY
----
~J&T
UPS
r
a-o __ ...l
TAPE DRIVE
(ALOG) LINEAR ARRAYS (2·32)
Generally Applicable Product Lines
ASIC
CAP
DBIC
FIBER
FREQ
19·2
Spring 1988
HYBRID
PCB
POW
T&I
W&C
rv
~pical
Applications
Computers
Multiuser Microsystems
AT&T Advantages
(A LOG)
Semi-Custom Linear Arrays (A LA 201, ALA400): High speed; high performance; integration of analog
and digital functions
(ASIC)
Interfaces with peripherals; special block capability
(COMM)
ART/: Automatic speed matching
Clock Recovery Circuit: No tuning necessary; 1-5 MHz
Digital Encryption Processor: Does all four DES modes
HDLC Formatters: Multichannel; high speed; on-chip buffers
X.25 Protocol Controller: Full X.25 LAPB protocol for level 2; no software needed
(DBIC)
High-speed designs with reasonable schedule and cost
Line Receivers and Drivers: High speed; low power; low EMI
(DSP)
DSP16 Family (16-bit fixed point): High speed; cost effective
DSP32 Family (32-bit floating point): High precision; flexible architecture
(FIBER)
OOL 50 and OOL 200 Lightwave Data Links: Long transmission; small size and weight
OOL RS232 Modem/Multiplexer and 02X Transceiver: EMI/ESD noninductive noise immunity; plugcompatible; electrical isolation of equipment
(FREQ)
Small, stable, switchable clock oscillators to drive logic; high-performance TRUs to recover data and
clock
(HYBRID) Custom hybrid thin- or thick-film IC combining different technologies in dense packaging functional
subassembly
(MICRO) CPU: Full 32-bit architecture enables complex instructions; high speed
DMAC: Dual bus architecture eliminates bus contention bottleneck
DRAMC: Built-in programmability to change and match memory speed
MAU: Floating-point arithmetic intensive; reduces CPU overhead
MMU: 4 Kbyte, two-way set-associative MMU/Cache with 85% data cache hit rate
(PCB)
Complex, high-density for small size; EMI shielding; surface mount technology
(POW)
UPS: Will reliably power combinations of computer (OLS) , printer/disk (inductive), and modem (linear)
power supplies; parallel processing design allows momentary overloads due to load startup or normal
load operating characteristics
(SBC)
VMEbus: Shortens design cycle by pre-engineering critical elements onto standard VMEbus hardware
in an open architecture; complete software availability. Complementary UNIX System VIVME facilitates
implementation of robust file systems.
(W&C)
Digital transmission cables with solid or stranded copper conductors featuring shielding for EMI protection, twisted pairs to minimize crosstalk, and foam/skin insulations for low capacitance
Spring 1988
19·3
Typical Applications
Computers
Workstations
Application Description
A technical workstation, often described as a single-purpose engineering workstation or graphics workstation, has its own processing capability that is greater than
that of a personal computer. It can function as either a stand-alone or as a
distributed processor linked by a network to other workstations. A workstation is
generally designed with one or more 32-bit microprocessor sets, auxiliary storage,
very high resolution CRT, 70-167 MB Winchester disk, and virtual memory
management. The graphics capabilities of a technical workstation are
sophisticated in terms of complexity, precision, and computational speed, and
separate graphics processors are often used with floating-point units. Multitasking
and LAN capabilities are also offered on some units.
. . . - - - - - - , (COMM) ARTI (5·12)
. . . - - - - - , (DSIC) LINE DRIVER (6·3. 6·4)
(ALOG) LINE DRIVERS (2·6)
(A LOG) REGULATION CONTROL CIRCUIT (2·25)
. - - -.......- - , (MICRO) CPU (12·2 to 12·4)
(MICRO) MMU (12·5. 12·6)
. . . - - - ' - - - , (DSP) DSP16/32
(7·2 to 7·13)
L.;.;.~"=~ (MICRO) DMAC (12·10)
(MICRO) MAU (12·12. 12·13)
(SSC) VMEbus (16·2)
...-_..L...L_--,
~r----""'" i~I~~~) ~~~NR~;~~0(;;7~ 8.7)
(COMM) x 25 (5·31. 5·33)
(COMM) ANT (5·10)
.--_..L...L_--, (COMM)
(COMM) CODEC (5·34 to 5·46)
CODEC
(ALOG) SPEAKERPHONE ICs
(5·34 to 5·46)
(2·33. 2·34)
L -_ _ _- - ' (ALOG) SINGLE CHIP TEL IC
(2·41)
(ALOG) ANALOG SWITCH (2·3)
(ALOG) RINGING DETECTORS (2·40)
(DSP) DSP16132 (7·2 to 7·13)
...-_J...J.._-,
(ALOG) ALA201 (2.32)
(COMM) ARTI (5·12)
(MICRO) DMAC (12·10)
I
(SERIAL I/O)
r-
~~
~
--,
I ____
LAN .JI
L
Generally Applicable Product Lines
ASIC
CAP
DBIC
FIBER
FREQ
19·4
Spring 1988
HYBRID
PCB
POW
T&I
W&C
Typical Applications
Computers
Workstations
AT&T Advantages
(ALOG)
Semi-Custom Linear Arrays (ALA201): High speed; high performance, integration of analog and
digital functions
Ringing Detector: Immune to false detection (bell tap immune)
Speakerphone ICs: Low background noise and soft switch capability
Other: LSI of high-voltage circuitry
(ASIC)
Interfaces with peripherals; special block capability
(COMM)
ISDN: Low cost; easy access to channel peripheral devices; 2- and 4-wire interfaces
ANT: High speed; additional buffering capability; DMA handshaking functions
ART/: Automatic speed matching
Codec: Low-cost, wlaw, A-law devices with superior noise performance; high-precision devices provide excellent linearity and easy interface to DSP
(DBIC)
High-speed design with reasonable schedule and cost
Line Driver: High speed; low power; low EMI
(DSP)
DSP16 Family (16-bit fixed point): High speed; cost effective
DSP32 Family (32-bit floating point): High precision; flexible architecture
(FIBER)
OOL RS232 Modem/Multiplexer and 02X Transceiver: EMI/ESD noninductive noise immunity; plugcompatible with terminal equipment
(FREQ)
Small, stable, switchable clock oscillators to drive logic; 3-stateable, small VCXOs to sync graphics
display
(HYBRID) Custom hybrid thin- or thick-film IC combining different technologies
subassembly
In
dense packaging functional
(MICRO) CPU: Multitasking 32-bit architecture with full set of peripherals
DMAC: Dual bus architecture eliminates bus contention bottleneck
DRAMC: Eliminates costly discrete designs; built-in programmability
MAU: Enhanced floating-point unit improves performance
MMU: MMU/Cache frees CPU to run at zero wait states at 24 MHz
(PCB)
Complex, high-density for small size; EMI shielding; surface mount technology
(POW)
UPS: Will reliably power combinations of computer (OLS), printer/disk (inductive), and modem (linear)
power supplies; parallel processing design allows momentary overloads due to load startup or normal
load operating characteristics
(W&C)
Digital transmission cables with solid or stranded copper conductors featuring sheidling for EMI protection, twisted pairs to minimize crosstalk, and foam/skin insulations for low capacitance. Specialized
performance cables feature data and voice pairs in a common outer Jacket.
Spring 1988
19·5
'lYpical Applications
Computers
Storage Products
Application Description
Mass storage products encompass rigid (hard) disk drives, flexible (floppy) disks,
tape drives, and optical disk drives and are used for data collection and retrieval.
They are comprised of a disk drive and a disk controller. Disk drive controllers
provide the electronics that allow the drive to interface with the host system. The
drive mayor may not contain the controller. If contained in the drive, the controller
may be a single chip, chip set, or board. If not contained, the controller may be a
plug-in board or a stand-alone unit containing many boards.
SINGLE-BOARD
COMPUTER
REMOTE
DRIVE-CONTROLLER
BOARD
(FREQ) OSCILLAWRS
(9·2 to 9·4)
----,
I
SCS1
INTERFACE
(FtBER) LGBC
(8·16)
DRIVE
CONTROLLER
I
(FIBER) OOL (8·2. 8·4)
(FREO) TAUs (8·3, 9·6)
(FREQ) OSCILLAWRS (9·2 to 9·4)
~_.r-_I--
(ALOG) LINEAR ARRAYS (2·32)
(DBIC) LINE DRIVERS AND
RECEIVERS (6·2 to 6·4)
(FREO) OSCILLAWRS (9·2 to 9·4)
(MICRO) DMAC (12,10)
(DSP) DSP16/32 (7·2 to 7·13)
Generally Applicable Product Lines
ASIC
CAP
DBIC
FIBER
HYBRID
19·6
Spring 1988
--~
~
1-+--,
PCB
POW
T&I
W&C
DISK
____ ...J
'lYplcal Applications
Computers
Storage Products
AT&T Advantages
(ALOG)
Line Drivers and Receivers: Industry standard
Semi-Custom Linear Arrays: High speed; high performance; integration of analog and digital
functions
(ASIC)
Higher level of component integration to save board space
(DBIC)
High speed designs with reasonable schedule and cost
Line Drivers and Receivers: High speed; low power; low EMI
(DSP)
Servo-control mechanism in the controller
DSP16 Family (16-bit fixed point): High speed; cost effective
DSP32 Family (32-bit floating pOint): High precision; flexible architecture
(FIBER)
OOL Lightwave Components: EMIIESD noninductive noise immunity; small size and weight; transmits
long distances without repeaters; high bandwidth
MAC: Links hosts to modules
LGBC (Lightguide Building Cable): Secure transmission media; immune to EMI; longer system runs;
capability to upgrade to 200 Mb/s; UL listed for riser and plenum applications
(FREQ)
Oscillators: Small, stable, switchable clock oscillators to drive logic
TRUs: High performance; recover data and clock
(HYBRID) Custom hybrid thin- or thick-film IC combining different technologies in dense packaging functional
subassembly
(MICRO) DMAC: Off-loads work from main processor and increases overall system throughput
(PCB)
Complex, high-density for small size; EMI shielding; surface mount technology
(W&C)
Digital transmission cables with solid or stranded copper conductors featuring shielding for EMI protection, twisted pairs to minimize crosstalk, and foam/skin insulations for low capacitance
Spring 1988
19·7
Typical Applications
Data Communications
Local Area Networks (LANs)
Application Description
LANs provide a communications facility for data systems contained in a small
geographic area. LAN characteristics include high bandwidth interconnection
media and relatively simple hosts or control hubs, although more sophisticated
systems perform extensive protocol conversion, priority, and congestion control as
well as multiplexing functions. Hosts can be either stand-alone systems or
embedded PBX functions.
r-----,
I
I
I
FILE
SERVER
L-
-
I
I
I
r-----..,
,- -'
(DSP) DSP16!32 (7-2 to 7-13)
(FIBER) OOL (8-2. 8-4)
L
II
r I
I
LAN HUBI
HOST
J
i
-l
_ _ _ _ ..J
GRAPHICS
I
WORKSTATION
AT&T
UPS
~
~
L-.._ _- '
VMEbus
HOST
ETHERNET
(COMM) DIG ENCRYPTION PROC (5-28)
(MICRO) CPU (12-2. 12·4)
(SBC) VMEbus (16-2)
I
I
I
I
I
r -- (FIBER) OOL (8-2. 8-4)
I
I
I
OOL
BRIDGEI
GATEWAY
L. _____
I
L~L-..Ii.._UTp_&S_T...J~
ASIC
CAP
DBIC
FIBER(MAC)
FIBER
FREO
Spring 1988
: (8-2.
I
.J
(COMM) DS1 (5-14 to 5-24)
(COMM) X 25 (5-31, 5-33)
Generally Applicable Product Lines
19·8
- -, (FIBER)
HYBRID
PCB
POW
T&I
W&C
8-4)
r---..,
I
I
PBX
L ___ .J
(ALOG) TELEPHONE INTERFACE CIRCUIT (2-43)
(ALOG) BATTERY FEED (2-4, 2-5)
(ALOG) RINGING DETECTOR (2-40)
(DBIC) CROSSPOINT ARRAY (6-6)
Typical Applications
Data Communications
Local Area Networks (LANs)
AT&T Advantages
(ALOG)
Battery Feed: Low cost, single-chip solution
Ringing Detector: Immune to false detection (bell tap immune)
Telephone Interface Circuit: Directs line Interface with high-voltage protection functionality
(ASIC)
Allows high-complexity designs with reasonable schedule and cost
(COMM)
DS1 Chip Set: Supports multiple frame formats; complete DS1 and CEPT solutions
Digital Encryption Processor: Programmable; does all four DES modes
X.25 Protocol Controller: Full X.25 LAPB protocol for level 2; no software needed
(DBIC)
High-speed designs with reasonable schedule and cost
Crosspoint Array: High density; high performance; insertion impedance
< 20
Q
(DSP)
DSP16 Family (16-bit fixed point): High speed; cost effective
DSP32 Family (32-bit floating point): High precision; fleXible architecture
(FIBER)
ODL 50 and 200 Lightwave Data Links: EMI/ESD noninductive noise immunity; small size and
weight; transmits long distances without repeaters; high bandwidth
MAC: Compact backplane to circuit pack multiple fiber optic connector
(FREQ)
Small, stable, switchable clock oscillators to drive logic; 3-stateable VCXOs to sync graphics display;
high-performance TRUs to recover data and clock
(HYBRID) Custom hybrid thin- or thick-film IC combining different technologies in dense packaging functional
subassembly
(MICRO) CPU: Handles full 32-bit word length instructions and increases speed and functionality
(PCB)
Complex, high-density for small size; EMI shielding; surface mount technology
(POW)
UPS: Will reliably power combinations of computer (OLS), printer/disk (inductive), and modem (linear)
power supplies; parallel processing design allows momentary overloads due to load startup or normal
load operating characteristics
-
(SBC)
VMEbus: UNIX System VIVME includes device driver software for the CMC ENP-10* Plus Ethernet
Node Processor
(W&C)
Digital transmission cables with solid or stranded copper conductors featuring shielding for EM I protection, twisted pairs to minimize crosstalk, and foam/skin insulations for low capacitance. Specialized
performance cables feature data and voice pairs in a common outer jacket.
* Trademark of the Communication Machinery Corporation
Spring 1988
19·9
Typical Applications
Telecommunications
Loop Carrier Systems
Application Description
Digital loop carrier systems are used to deploy digital connectivity into the loop efficiently and economically. These systems consolidate (multiplex) message channels onto high bandwidth transmission media, essentially creating interoffice trunk
systems that have the speCial features required for operation in the loop environment such as AID and D/A conversion operational functions.
CUSTOMER
EQUIPMEN T
r---.,
PBX
r--j
f-
:
L ___ ...J
I
I
(DBIC) CROSSPO INT
ARRAY (6-6)
H
LINE
INTERFACE
l_~:r&T
UPS
-
(FIBER) ASTROTEC (8-9 to 8-12)
(GaAs) DECISION CIRCUIT (10 -2)
••
OR
-
.r-
~l INTERFACE
LINE
~
MUX
-
'-
SIGNALING
CONTROL
I
I
-A
(LOG) TE L EPH 0 NE INTERFACE CIRCUITS 2-43
(ALOG) SOLID STATE RELAYS (2-12 to 2-14)
(ALOG) LINE DRIVERS & RECEIVERS (2-6. 2-7)
I
~
I
Generally Applicable Product Lines
19·10
Spring 1988
HYBRID
PCB
POW
T&I
W&C
ANALOG -
(A LOG) TELEPHONE INTERFACE CIRC UIT (2-43)
(A LOG) SINGLE CHIP TELEPHONE IC (2-41. 2-42)
(ALOG) RINGING DETECTOR (2-40)
(ALOG) SOLID STATE RELAYS (2-12 to 2-14)
(ALOG) BATTERY FEED (2-4. 2-5)
(ALOG) INTEGRATED SECONDARY PR OTECTOR (2-29)
(COMM) CODEC (5-34 to 5-46)
(COMM) ISDN (5 4 to 5 26)
~
ASIC
CAP
DBIC
DSP
FIBER
FREQ
~
rv
I
DIGITAL
r-
I
•
•
•
•
I
CENTRAL
OFFICE
(DBIC) LINE RECEIVER/DRIVER (6-2 to 6-4)
(FIBER) OOL (8-2. 8-4)
(COMM) ISDN (5-4 to 5-26)
(COMM) CODEC (5-34 to 5-46)
(COMM) DS1 (5-14 to 5-24)
1\'pical Applications
Telecommunications
Loop Carrier Systems
AT&T Advantages
(ALOG)
Battery Feed: Low cost, single-chip solution
Integrated Secondary Protector: Complete 2-wire protection
Line Drivers and Receivers: Industry standard
Ringing Detector: No false detection (bell tap immune)
Single Chip Telephone IC: Minimum external components
Solid State Relays: Low cost; high reliability
Telephone Interface Circuits: Line interface and dial pulse switch in one package
(ASIC)
Interfaces with peripherals; special block capability
(COMM)
ISDN: Low cost; easy access to channel peripheral devices; 2- and 4-wire interfaces
DS1 Chip Set: Supports multiple frame and signaling formats; complete DS1 and CEPT solutions
Codec: Low-cost, wlaw, A-Iaw devices with superior noise performance; high-precision devices proVide excellent linearity and easy interface to DSP
(DBIC)
High-speed designs with reasonable schedule and cost
Line Drivers/Receivers: High speed; low power; low EMI
Crosspoint Array: High density; high performance; insertion impedance <20
!]
(DSP)
DSP16 Family (16-bit fixed point): High speed; cost effective
DSP32 Family (32-bit floating point): High precision; flexible architecture
(FIBER)
ASTROTEC Laser Modules, Transmitters, Receivers: Compact; high reliability; board mountable;
many different speeds; ESD/EMI noninductive noise immunity; high bandwidth
ODL 50 and ODL 200 Lightwave Data Links: Long transmission; small size and weight; EMI/ESD
noninductive noise immunity; high bandwidth
Lightguide Cable: Low loss; high bandwidth; robust; easy to install
ST Lightguide Cable Connectors: Low loss; low cost; widely used; easy to install; stable
Lightguide Rotary Splice: Low loss; rearrangeable; stable; easy and quick to install
MAC: Compact backplane to circuit pack multiple fiber optic connector
(FREQ)
Small, stable, switchable clock oscillators to drive logic; 3-stateable, small VCXOs for clock recovery
(GaAs)
Decision Circuit: High speed; low power
(HYBRID) Custom hybrid thin- or thick-film IC combining different technologies in dense packaging functional
subassembly
(PCB)
Complex; high-density for small size; EMI shielding; surface mount technology
(POW)
UPS: Will reliably power combinations of computer (OLS), printer/disk (inductive), and modem (linear)
power supplies; parallel processing design allows momentary overloads due to load startup or normal
load operating characteristics
(T&I)
Electronic circuit transformers designed for analog or digital applications on high-density line cards;
optimal combinations of size, performance, and price
(W&C)
Digital transmission cables with solid or stranded copper conductors featuring shielding for EMI protection, twisted pairs to minimize crosstalk, and foam/skin insulations for low capacitance
Spring 1988
19·11
Typical Applications
Telecommunications
Private Branch Exchanges (PBXs)
Application Description
A PBX is a customer premise switch that routes voice and data traffic both intrapremise and to the loop. The application package focuses on PBXs which support 100 to 10,000 lines.
i~ ~T:; ~
(DBIC) CROSSPOINT ARRAY (6-6)
(ALOG) SINGLE CHIP TEL IC (2-41.2-42)
(ALOG) TONE RINGERS (2-38)
(ALOG) SOLID STATE RELAYS (2-12 to 2-14)
(ALOG) RINGING DETECTORS (2-40)
(ALOG) SPEAKERPHONE ICs (2-33. 2-34)
I
II
I
I
(COMM) DIG ENCRYPTION PROC (5-28)
(FIBER) OOL (8-2 to 8-8)
(COMM) ARTI (5·12)
L
c:::J====u
'=j
?
r---"
TERMINAL
I
I
DATA SET
(DSP) DSP16 (7-2 to 7-7)
(ALOG) SOLID STATE RELAYS
(2-12 to 2-14)
(ALOG) SPECIALIZED OP
AMPS (2-21)
I
I
L ___
1
PBX
I
LAN!
LTERMI~aJ
DIGITAL
LINE
INTERFACE
TRUNK
INTERFACE
I
I
I
CONTROL
I I
(FIBER) OOL (8·4)
I
(MICRO) DRAMC (12-8)
MEMORY
I
~~
~
Generally Applicable Product Lines
ASIC
CAP
DBIC
FIBER
FREQ
19·12
Spring 1988
HYBRID
PCB
POW
T&I
W&C
(COMM) CODEC
(5-34 to 5-46)
(FIBER) ASTROTEC
(8-9 to 8-12)
I
SWITCHING FABRIC
(MICRO) CPU (12·2. 12-4),
(MICRO) MMU (12-5. 12-6)
(MICRO) DMAC (12-10)
I
LOOP
I
L _ _ _ --JI
(FIBER)
(GaAs) DECISION CIRCUIT
(10-2)
(COMM) SPYDER (5-25. 5-26)
(COMM) UNITS (5-6)
(COMM) CODEC (5-34 to 5·46)
(ALOG) BATTERY FEED (2-4. 2-5)
(ALOG) HV DUAL OP AMP (2-17)
(ALOG) LINE DRIVERS & RECEIVERS
(2·6. 2-7)
r-----,
(COMM) DS1
(5-14 to 5-24)
(FIBER) OOL (8-4)
(COM M) ISDN (5-4 to 5-26)
I
ANALOG
LINE
INTERFACE
UPS
LAN
I
Typical Applications
Telecommunications
Private Branch Exchanges (PBXs)
AT&T Advantages
(ALOG)
HV Dual Op Amp: High-voltage operation; fail-safe thermal shutdown; constant supply voltage
Solid-State Relays: Low cost; high reliability
Ringing Detectors: No false detection (bell tap immune)
Speakerphone ICs: High performance, low background noise
Single Chip Telephone IC: All telephone functions on one chip; few external components required
Line Drivers and Receivers: Industry standard
Tone Ringers: Low cost
Specialized Op Amps: Low power; wide bandwidth; programmable
(ASIC)
Allows high-complexity designs with reasonable schedule and cost
(COMM)
ISDN: Low cost; easy access to channel peripherals; 2- and 4-wlre interfaces
UNITS: Low cost; high-speed TOM system interface; pass D-channel information to central controller
DS1 Chip Set: Supports multiple frame formats; complete DS1 and CEPT solutions
ART/: Automatic speed matching
Codec: Low cost, wlaw, A-Iaw devices with superior noise performance; high-precision devices provide excellent linearity and easy interface to DSP
Digital Encryption Processor: Programmable, four DES modes
SPYDER: Extremely compact multichannel formatter with buffers and DMA on chip
(DBIC)
High-speed designs with reasonable schedule and cost
Crosspoint Array: High density; high performance; insertion impedance
< 20 n
(DSP)
DSP16 Family (16-bit fixed point): High speed; cost effective
DSP32 Family (32-bit floating point): High precision; flexible architecture
(FIBER)
ASTROTEC Laser Modules, Transmitters, Receivers: High reliability; longer transmission distance;
immunity to EMI, corrosion
ODL 50 Lightwave Data Link: EMI/ESD noninductive noise immunity; high bandwidth; small size
and weight; long distance without repeater
ODL RS232 Modem/Multiplexer: EMI/ESD noninductive; plug-compatible with existing equipment
MAC: Compact backplane to circuit pack multiple fiber optic connector
(FREQ)
Smalj, stable, switchable clock oscillators to drive logic; high-performance TRUs to recover data and
clock
(GaAs)
Decision Circuit: High speed, low power
(HYBRID)
Custom hybrid thin- or thick-film IC combining different technologies in dense packaging functional
subassembly
(MICRO)
&(DSP)
Fully integrated 32-bit microprocessors, peripherals, and DSPs to control PBX functions
(PCB)
Complex, high-density for small size; EMI shielding; surface mount technology
(POW)
UPS: Will reliably power combinations of computer (OLS) , printer/disk (inductive), and modem
(linear) power supplies; parallel processing design allows momentary overloads due to load startup
or normal load operating characteristics
(T&I)
Electronic circuit transformers designed for analog or digital applications on high-density line cards;
optional combinations of size, performance, and price
(W&C)
Digital transmission cables with solid or stranded copper conductors featuring shielding for EMI
protection, twisted pairs to minimize crosstalk, and foam/skin insulations for low capacitance
Spring 1988
19·13
Typical Applications
Telecommunications
Digital Cross-Connect Systems
Application Description
A Digital Cross-Connect System (DCS or DACS) makes direct connections between channels of incoming and outgoing digital lines and provides access to any
channel for remote digital testing. The cross-connect capability permits the assignment and redistribution of lower speed channels among higher rate systems (e.g.,
64 kb/s DSO channels among 1.544 Mb/s DS1 systems or 1.544 M b/s DS1 channels among 45 Mb/s DS3 systems). The capability is used to collect incoming
channels with common destinations and thus increase the filion outgoing systems
and/or on terminal transmission equipment. The cross-connect capability can also
be used to segregate channels by type (e.g., message/special service;
2-wire/4-wire) to simplify Central Office interconnection.
OS1
OR
DS3
DIGITAL LINE
INTERFACE
(COMM) DS1 (5-14 to 5-24)
(FREO) OSCILLATORS (9 2 to 9 4)
f-------1 (FREO)
(MICRO)
TIME SLOT
INTERCHANGE
SWITCHING FABRIC
TO ALL
BLOCKS
CONFIGURATION
CONTROLLERS
(MICRO) DMAC (12 10)
(MICRO) DRAMC (12-8)
(FREQ) OSCILLATORS [9 2 to 9-4)
(DB Ie) LINE DRIVERS AND RECEIVERS (62 to 64)
TO/FROM
OTHER BAYS
(FRED) OSCILLATORS (9-2 to 9-4)
(FRED) TRUOSO (9-6)
ADMINISTRATIVE
ACCESS
(COMM) ISDN (5-4 to 5-26)
(COMM) X 25 (5-31, 533)
{COMM} HDLe FORMATTERS
(FRED) OSCILLATORS (9-2 to
(FRED) TRU050 (9-6)
5-25 526)
Generally Applicable Product Lines
ASIC
CAP
DBIC
FIBER
HYBRID
19-14
Spring 1988
PCB
POW
T&I
W&C
~pical
Applications
Telecommunications
Digital Cross-Connect Systems
AT&T Advantages
(ASIC)
Interfaces with peripherals; special block capability
(COMM)
ISDN: Low cost; easy access to channel peripheral devices; 2- and 4-wlre devices
DS1 Chip Set:Supports multiple frame and signaling formats; complete DS1 and CEPT solutions
Codec: Low cost, wlaw, A-Iaw devices with superior noise performance; high-precision devices provide excellent linearity and easy interface to DSP
HDLC Formatters: Multichannel; high speed; on-chip buffers
X.25 Protocol Controller: Full X.25 LAPB protocol for level 2; no software necessary
(DBIC)
High-speed designs with reasonable schedule and cost
Line Drivers and Receivers: High speed, low power, low EMI
(DSP)
DSP16 Family (16-bit fixed point): High speed; cost effective
DSP32 Family (32-bit floating point): High precision; flexible architecture
(FIBER)
ODL 50 and ODL 200 Lightwave Data Links: Long transmission; small cable size and weight
(FREQ)
Clock recovery and data retlming via TRU050 or VCXO In phase-locked loop; clock oscillators to drive
logic
(HYBRID) Custom hybrid thin- or thick-film IC combining different technologies in dense packaging functional
subassembly
(MICRO) DMAC: Provides high-speed Interface between system memory and administrative access peripheral
(e.g., ISDN, XPC)
DRAMC: Provides control necessary for large banks of dynamic RAM; can be used In dual port
mode for Simultaneous access by multiple processors
(PCB)
Complex, high-density for small size; EMI shielding; surface mount technology
(W&C)
Digital transmission cables with solid or stranded copper conductors featuring shielding for EMI protection, twisted pairs to minimize crosstalk, and foam/skin insulations for low capacitance
Spring 1988
19·15
Typical Applications
Industrial
Manufacturing Automation
Protocol (MAP) LANs
Application Description
The MAP LAN is a specialized LAN adhering to the MAP standard. It provides a
high bandwidth communication link between intelligent controllers, computers, and
terminals in the factory environment. The LAN consists of the transmission media,
interface units, and the network manager. The latter performs maintenance,
monitoring, performance, and status functions .
. - - - - - - - - - . (MICRO) CPU (12-2. 12-4)
MAP LAN
(FIBER) DOL (8-4)
MANAGER
(ALOG) LINEAR ARRAYS (2-32)
' - - -...............- - - - 1 (SBG) VMEbus (16-2)
r---'--'------,
CELL
:
(FIBER) DOL (8-4)
,....--........- ' - - - - , (ALOG) OCTAL LINE
PROTECTOR (2-27)
(ALOG) REGULATION
CONTROL CIRCUITS (2-25)
I (ALOG) TRANSCEIVERS (2-8)
TERMINAL
I (FIBER) OOL (8-4)
IL
I (SBC) VMEbus (16-2)
'--_ _ _ _---!
(SBC) VMEbus (16-2)
IL..CONTROLLER
_ _ _ _ _ ..II
---T-...J
I
~~
~
Generally Applicable Product Lines
ASIC
CAP
DBIC
DSP
FIBER(MAC)
FIBER
19·16
Spring 1988
FREQ
HYBRID
PCB
POW
T&I
W&C
'J\fpical Applications
Industrial
Manufacturing Automation Protocol (MAP) LANs
AT&T Advantages
(ALOG)
Octal Line Protector: Electronic fusing for bus protection
Regulation Control Circuits: High-speed comparator and precision reference in one package
Transceivers: TTL- and CMOS-compatible
(ASIC)
Allows high-complexity designs with reasonable schedule and cost
(DBIC)
High-speed designs with reasonable schedule and cost
(DSP)
DSP16 Famify (16-bit fixed point): High speed; cost effective
DSP32 Famify (32-bit ffoating point): High precision; flexible architecture
(FIBER)
ODL Lightwave Components: EMI/ESD noninductive noise immunity; small size and weight; transmits
long distances without repeaters; high bandwidth
MAC: Compact backplane to circuit pack multiple fiber optic connector
(FREQ)
Small, stable, switchable clock oscillators to drive logic; high-performance TRUs to recover data and
clock
(HYBRID) Custom hybrid thin- or thick-film IC combining different technologies in dense packaging functional
subassembly
(MICRO) CPU: Full 32-bit instruction set; high performance, multitasking capability
(PCB)
Complex, high-density for small size; EMI shielding; surface mount technology
(POW)
UPS: Will reliably power combinations of computer (0 LS) , printer/disk (inductive), and modem (linear)
power supplies; parallel processing design allows momentary overloads due to load startup or normal
load operating characteristics
(SBC)
VMEbus: Shortens design cycle by pre-engineering critical elements onto standard VMEbus hardware in
an open architecture; complete software availability. Open architecture of UNIX System VNME allows for
easy integration of other VMEbus boards, many of which are available for factory applications.
(W&C)
Digital transmission cables with solid or stranded copper conductors featuring shielding for EMI protection, twisted pairs to minimize crosstalk, and foam/skin insulations for low capacitance
Spnng 1988
19·17
Typical Applications
Industrial
Cell Controllers
Application Description
A cell controller IS usually a multiprocessing minicomputer controlling an area of
the factory floor concerned with a particular segment of the manufacturing process (i.e., cell). A real-time operating system is important to service the lower-level
controllers which manage the manufacturing tools in the cell. Communication to
the lower-level controllers may occur through a LAN, MAP LAN, or dedicated 1/0
channels (serial or parallel).
(ALOG) LINEAR ARRAYS (2-32)
,..---1..---, (FIBER)
OOL
(B-2. B-4)
SERIAL
(ALOG) LINE DRIVERS & RECEIVERS
(2-6.2·7)
_____
I
I
WINCHESTER
(COMM) X 25 (5-31. 5·33)
(COMM) DIGITAL ENCR PROC (5-2B)
(COMM) CLOCK RECOVERY (5-47 to 5·49)
(COMM) HDLC FORMATTERS (5-10. 5-25. 5-26)
(COMM) ARTI (5-12)
(FIBER) OOL RS232 (B-5 to 8-7)
~npl
FLOPPY
_____ f
,_ _ _ _ .1
Source Exif Data:
File Type : PDF
File Type Extension : pdf
MIME Type : application/pdf
PDF Version : 1.3
Linearized : No
XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Create Date : 2014:01:09 07:29:43-08:00
Modify Date : 2014:01:09 07:39:44-08:00
Metadata Date : 2014:01:09 07:39:44-08:00
Producer : Adobe Acrobat 9.55 Paper Capture Plug-in
Format : application/pdf
Document ID : uuid:23fad946-5d10-4c78-8c0b-501dccea8339
Instance ID : uuid:c6a202c1-8b8b-4cb5-a098-1a15ba788fb4
Page Layout : SinglePage
Page Mode : UseNone
Page Count : 302
EXIF Metadata provided by EXIF.tools