1988_Analog_Devices_Linear_Products_Databook 1988 Analog Devices Linear Products Databook
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1988
LINEAR
PRODUCTS
DATABOOK
©Analog Devices, Inc., 1988
All Rights Reserved
I] DEVICES
ANALOG
General Information
Operational Amplifiers
Comparators
Instrumentation Amplifiers
Isolation Amplifiers
Analog Multipliers/Dividers
Log/Antilog Amplifiers
RMS-to-DC Converters
Special Function Components
Temperature Transducers
Signal Conditioning
Components & Subsystems
Digital Panel Instruments
Application Specific ICs
Power Supplies
Component Test Systems
Package Information
Appendix
Product Index
II
•II
II
It
II
II
II
IJ
1m
II
II
I
III
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I
.... ANALOG
WOEVICES
LINEAR PRODUCTS DATABOOK
April 1988
© Analog Devices, Inc., 1988
All Rights Reserved
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility
is assumed by Analog Devices for,its use; nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Products in this book may be covered by one or more ofthe following patents. Additional patents are pending.
U.S.:
RE29,619, RE29,992, RE30,586, RE31 ,850, DES. 233,909, 3,007,114, 3,278,736, 3,355,670, 3,441,913, 3,467,908,
3,500,218,3,530,390,3,533,002,3,685,045, 3,729,660, 3,793,563,3,842,412,3,868,583,3,890,611,3,906,486,
3,909,908, 3,932,863, 3,940,760, 3,942,173, 3,946,324, 3,950,603, 3,961,326, 3,978,473, 3,979,688, 4,016,559,
4,020,486,4,029,974,4,034,366,4,054,829, 4,092,698, 4,123,698, 4,136,349, 4,141,004, 4,213,806, 4,250,445,
4,268,759, 4,270,118, 4,268,225, 4,309,693, 4,313,083, 4,323,795, 4,338,591, 4,349,811, 4,363,024, 4,374,314,
4,383,222,4,395,647,4,399,345,4,400,689, 4,400,690, 4,427,973, 4,439,724, 4,460,891, 4,475,103, 4,475,169,
4,476,538, 4,481,708, 4,484,149, 4,485,372, 4,491,825, 4,511,413, 4,521,764, 4,543,560, 4,543,561, 4,547,766,
4,547,961,4,556,870,4,558,242,4,562,400, 4,565,000, 4,586,019, 4,586,155, 4,590,456, 4,596,976, 4,601,760,
4,604,532, 4,608,541, 4,622,512, 4,626,769, 4,639,683, 4,644,253, 4,646,056, 4,646,238, 4,678,936, 4,684,922,
4,685,200,4,694,276,4,697,151,4,703,283, 4,707,682, 4,709,167, 4,717,883
France:
111.833,70.10561,75.27557,7608238,77 20799, 7810462, 79 24041, 80 00960, 8011312,8102661,8114845,
8209758,8303140
Japan:
1,092,928,1,242,936,1,242,965,1,306,235,1,337,318, 1,401,661,1,412,991
West Germany:
2,014034, 2540451.7, 2611858.1
U.K.:
1,310,591, 1,310,592, 1,537,542, 1,590,136, 1,590,137, 1,599,538, 2,008,876, 2,032,659, 2,040,087, 2,050,740,
2,054,992, 2,075,295, 2,081,040, 2,100,081, 2,103,884, 2,104,288, 2,107,951, 2,115,932, 2,118,386, 2,119,139,
2,119,547, 2,126,445, 2,126,814, 2,135,545, 2,137,787
Canada:
984,015,1,006,236,1,025,558, 1,035,464, 1,054,248, 1,141,034, 1,141,820, 1,142,445, 1,143,306, 1,150,414,
1,153,607,1,157,571,1,159,956,1,177,127, 1,177,966, 1,184,662, 1,184,663, 1,191,715, 1,192,310, 1,192,311,
1,192,312,1,203,628,1,205,920,1,212,730, 1,214,282, 1,219,679, 1,219,966, 1,223,086
Sweden:
7603320-8
General Information
Contents
Page
Introduction
.........................................................
1-3
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 - 5
GENERAL INFORMA TION 1-1
•
1-2 GENERAL INFORMA TlON
General Introduction
Analog Devices designs, manufactures and sells worldwide
sophisticated electronic components and subsystems for use in
real-world signal processing. More than six hundred standard
products are produced in manufacturing facilities located throughout the world. These facilities encompass all relevant technologies,
including several embodiments of CMOS, BiMOS, bipolar and
hybrid integrated circuits, each optimized for specific attributes
- and assembled products in the form of potted modules, printedcircuit boards and instrument packages.
State-of-the-art technologies have been utilized (and in many
cases invented) to provide timely, reliable, easy-to-use advanced
designs at realistic prices. Our popular IC products are available
in both conventional and surface-mount packages (SO, LCC,
PLCC) and many of our assembled products employ surface-mount
technology to reduce manufacturing costs and overall size. More
than twenty years of successful applications experience and
continuing vertical integration insure that these products are
oriented to user needs. The ongoing application of today's state-ofthe-art and the invention of tomorrow's state-of-the-art processes
strengthen the leadership position of Analog Devices in standard
data-acquisition and signal-processing products and make us a
strong contender in high-performance mixed-signal ASICs.
MAJOR PROGRESS
Since publication of the selection guides in the 1986 supplement
to our 1984 Data Acquisition Databook, more than 120 significant
new products have been introduced; they run the gamut from
brand new product categories and technologies to new standard
products (with improvements in price, performance, or design)
to augmented second-source products. They are all classified
and summarized in these Volumes, along with existing products
that are desirable for use in new designs.
Among the landmark new linear products are high-accuracy op
amps - such as the ultralow-offset-and-drift AD707, wideband
transconductance op amps - both monolithic (AD5539) and
hybrid (AD9611) aud the 60-femtoampere AD549 electrometer
- using ADl's patented Top-Gate FET process. Other new
high-performance monolithic devices include the fast, accurate
AD9686 comparator, the AD625 software-programmable-gain
amplifier, the innovative AD693 4-to-20mA sensor transmitter,
the AD834 ultimate analog multiplier, plus the AD9521 r-f log
devices and the AD890/891 data-recovery chip set. Also of note
are the 5B Series of compact modular isolated signal-conditioners,
the AD210 high-performance isolator and the IB series of
DIP-packaged signal conditioners - all of which employ automated surface mount assembly for compactness, low cost and
high reliability.
THE 1988 LINEAR PRODUCTS DATABOOK
This Volume provides complete technical data on Analog Devices
"linear" products - designed to process, condition and otherwise
operate on analog signals with analog results. One of a set of
three volumes, it is accompanied by the DSP Products Databook,
dedicated to products for high-performance digital signal-processing (i.e., digital-to-digital) and the Conversion Products Databook,
which covers products involved in spanning the interface between
analog and digital.
The product data in this book is intended primarily for the
majority of users who are concerned with new designs. For this
reason, those existing and available products that offer little if
any uniq~e advantage over newer products in future designs are
included in the Index and their data sheets are available from us
separately - but they aren't published in this book.
This book includes:
• Comprehensive data sheets on more than 160 significant product
families;
• Orientation material and selection guides for rapid product
finding;
• A representative list of available Analog Devices technical
publications on real-world analog and digital signalprocessing;
• Worldwide Service Directory; and
• Product Index to all three volumes.
TECHNICAL SUPPORT
Our extensive technical literature discusses the technology and
applications of products for precision measurement and control.
Besides tutorial material and comprehensive data sheets, including
a large amount in our Databooks, we offer Application Notes,
Application Guides, Technical Handbooks (at reasonable prices),
and several free serial publications; for example, Analog Productlog
provides brief information on new products being introduced,
and Analog DIalogue, our technical magazine, provides in-depth
discussions of new developments in analog and digital circuit
technology as applied to data acquisition, signal processing,
control and test. DSPatch is a quarterly newsletter that brings
its readers up-to-date applications information on our DSP
products and the general field of digital signal processing. We
maintain a mailing list of engineers, scientists, and technicians
with a serious interest in our products. In addition to Databook
catalogs, we also publish several short-form catalogs on specific
product families. You will find Technical Publications described
on pages 17-6 and 17-7 at the back of the book.
GENERAL INFORMA TlON 1-3
SALES OFFICES
Backing up our design and manufacturing capabilities and our
extensive array of publications is a network of sales offices and
representatives throughout the United States and most of the
world. They are staffed by experienced sales and applications
engineers, and many of them maintain a local stock of Analog
Devices products. Our Worldwide Service Directory, as of the
publication date, appears on pages 17-8 and 17-9 at the back of
the book.
RELIABILITY
The manufacture of reliable products is a key objective at Analog
Devices. The primary focus is the companywide Quality Improvement Process (QIP). In addition, we maintain facilities
that have been qualified under such standards as MIL-M-38510
for ICs in the U. S. and Ireland and MIL-STD-1772 for hybrids.
More than 20 of our products - both proprietary and second-source
- have qualified for JAN part numbers; others are in the process.
A larger number of products - including many of the newer
ones just starting the JAN qualification process - are specifically
characterized on Standard Military Drawings (SMDs). Most of
our ICs are available in versions that comply with MIL-STD-883C
Class B. We publish a Military Products Databook for designers
who specify ICs and hybrids for military contracts (the 1987
issue contains data on nearly 150 available product families). A
newsletter, Analog Briefings, provides current information about
the status of reliability at ADI.
1-4 GENERAL INFORMA TION
Our PLUS program makes available standard devices (commercial
and industrial grades, plastic or ceramic packaging) for any user
with demanding application environments, at a small premium.
Subjected to stringent screening, similar to MIL-STD-883 test
methods, they are often suffixed "/ +" and are available from
stock.
PRODUCTS NOT FOUND IN THE SELECTION
GUIDES
For maximum usefulness to designers of new equipment, we
have limited the contents of selection guides to products most
likely to be used for the design of new circuits and systems. If
the model number of a product y\>u are interested in is not in
the Index, turn to page 17-4 at the back of this volume where
you will find a list of older products for which data sheets are
available upon request. On page 17-5 you will find a guide to
substitutions (where possible) for products no longer available.
PRICES
Accurate, up-to-date prices are an important consideration in
making a choice among the many available product families.
Since prices are subject to change, current price lists and/or
quotations are available upon request from our sales offices.
Table of Contents
Page
Operational Amplifiers - Section 2
2-1
Selection Guide . . . . . . . . . . . . . . . . . . . .
2-2
Orientation . . . . . . . . . . . . . . . . . . . . . .
AD380 - Wideband Fast Settling, FET-Input Op Amp
2-4
..
2 - 15
AD381!382 - High Speed, Low Drift, FET Operational Amplifiers
2 - 21
AD507 - IC Wideband Fast Slewing, General Purpose Operational Amplifier
2 - 27
AD509 - High Speed, Fast Settling IC Op Amp . . . . . . . . . . . . . . .
2 - 31
AD515A - Monolithic Precision, Low Power FET-Input Electrometer Op Amp.
AD542/544/547 - High Performance, BiFET Opemtional Amplifiers .
2 - 35
2 - 41
2 - 47
AD548 - Precision, Low Power BiFET Op Amp . . . . .
2 - 55
AD549 - Monolithic Electrometer Operational Amplifier .
2 - 63
AD517 - Low Cost, Laser Trimmed Precision IC Op Amp
.. ' . . .
AD642 - Precision Low Cost, Dual BiFET Op Amp . .
2 -75
AD644 - Dual High Speed, Implanted BiFET Op Amp
2 - 81
AD647 - Ultralow Drift, Dual BiFET Op Amp
AD648 - Dual Precision, Low Power BiFET Op Amp
2 - 87
2 - 93
AD707 - Ultralow Drift Op Amp . . . . . . . . . . .
2 - 103
AD708 - Dual Ultralow Drift Op Amp . . . . . . . . .
2 -105
...
AD711 - Precision Low Cost, High Speed BiFET Op Amp
2 - 107
AD712 - Dual Precision, High Speed BiFET Op Amp .
2 - 119
AD713 - Quad Precision, High Speed BiFET Op Amp
, 2 - 131
AD741 Series - Low Cost, High Accuracy IC Op Amps
2 -133
AD744 - Precision 500ns Settling BiFET Op Amp . . .
2 -137
AD746 - Dual Precision 500ns Settling BiFET Op Amp
2 - 149
AD821 - Single Supply, Low Power Precision Op Amp
2 -153
AD840 - Wideband Fast Settling Op Amp . . . . . . .
2 - 157
AD841 - Wideband, Unity Gain, Stable Fast Settling Op Amp
2 - 159
AD842 - Wideband, High Output Current, Fast Settling Op Amp.
2 - 161
AD845 - Precision 16MHz CBFET Op Amp . . . . . .
2 - 163
AD846 - Very High Speed Operational Amplifier
...
2 - 165
AD847 - High Speed, Low Power Monolithic Op Amp
2 - 177
AD848 - High Speed, Low Power Monolithic Op Amp
2 - 179
AD849 - High Speed, Low Power Monolithic Op Amp
2 - 181
AD5539 - Ultrahigh Frequency Operational Amplifier .
2 - 183
AD9610 - Wide Bandwidth, Fast Settling Operational Amplifier .
2 -199
2 - 207
AD9611 - Wide Bandwidth, Fast Settling Operational Amplifier,.
ADLHOO32G/0032CG - Ultrafast FET Operational Amplifiers
2 - 215
ADLHOO33G/0033CG - High Speed Buffer Amplifiers
2 - 219
AD OP-07 - Ultralow Offset Voltage Op Amp . . . . . . . .
2 - 223
AD OP-27 - Ultralow Noise, Precision Op Amp . . . . . . .
2 - 229
(AvcL~5)
2 - 237
HOS-050/050Al05OC - Fast Settling Video Operational Amplifiers . . .
2 - 245
HOS-060 - Low Offset, Fast Settling Video Operational Amplifier . . .
2 - 251
HOS-IOOAH/lOOSH - Wide Bandwidth, High Speed Buffer Amplifiers
2 - 255
HOS-200 - Wide Bandwidth, High Speed Buffer Amplifier
2 - 257
AD OP-37 - Ultralow Noise, High Speed Precision Op Amp
..... .
GENERAL INFORMA TION 1-5
Page
Comparators - Section 3
3- 1
Selection Guide . . . . . . . . . . . .
3-2
....:.........
3-3
Orientation
AD790 - Fast Single Supply Comparator
3-5
AD9685/9687 - High Speed Comparators
3-9
AD9686 - High Speed TTL Voltage Comparator.
3 - 13
AD96685/96687 - Ultrafast Comparators . . . . .
3 - 17
Instrumentation Amplifiers - Section 4
4-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . .
4-3
Orientation . . . . . . . . . . . . . . . . . . . . . . . . .
4-4
AD365 - Programmable Gain & Track/Hold DAS Amplifier .
4-7
AD521 - Integrated Circuit Precision Instrumentation Amplifier
4 -15
AD522 - High Accuracy, Data Acquisition Instrumentation Amplifier
4 - 21
4- 25
AD524 - Precision Instrumentation Amplifier
..
AD526 - Software Programmable Gain Amplifier . . . .
AD624 - Precision Instrumentation Amplifier
4 - 37
.....
4-49
AD625 - Programmable Gain Instrumentation Amplifier
4 - 61
Isolation Amplifiers - Section 5
5- I
Selection Guide . . . . . . . . . . . . . . . . .
5-3
Orientation . . . . . . . . . . . . . . . . . . .
5-4
AD202/204 - Low Cost, Miniature Isolation Amplifiers
5-7
AD210 - Precision Wide Bandwidth 3-Port Isolation Amplifier
286J/281 - High CMV High Performance, Synchronized Isolation Amplifiers
5555-
289 - Precision Wide Bandwidth Synchronized Isolation Amplifier . .
5 - 45
290A/292A - Low Cost, Single and Multichannel Isolation Amplifiers . . . .
5 - 51
AD295 - Precision Hybrid Isolation Amplifier . . . . . . . . .
284J - Economy High Performance, Self-Contained Isolation Amplifier
19
27
33
39
Analog Multipliers/Dividers - Section 6 .
6-1
Selection Gnide . . . . . . . . . . . . . . . . . . . . . . .
6-3
Orientation . . . . . . . . . . . . . . . . . . . . . . . . .
6-4
AD532 - Internally Trimmed Integrated Circuit Multiplier.
6-7
AD534 - Internally Trimmed Precision IC Multiplier
...
6 - 13
AD538 - Real-Time Analog Computational Unit (ACU) ..
6 - 23
AD539 - Wideband Dual-Channel Linear MuitiplierlDivider .
6 - 31
AD632 - Internally Trimmed Precision IC Multiplier
6 - 39
AD834 - High Frequency Four-Quadrant Multiplier . . . . .
6 - 43
1-6 GENERAL INFORMA TION
Page
Log!Antilog Amplifiers - Section 7
7-1
Selection Guide . . . . . . . . . . . . . . . . . . . .
7-3
Orientation . . . . . . . . . . . . . . . . . . . . . .
7-4
AD9521 - 250MHz Wideband Logarithmic Amplifier
7-7
755/759 - 6-Decade, High Accuracy, Wideband Log, Antilog Amplifiers
7 - 11
757 - 6-Decade High Accuracy, Log Ratio Amplifier . . . . . . . . . . .
7 - IS
RMS-to-DC Converters - Section 8
8-1
Selection Guide . . . . . . . . . . . . . . . . . . . . .
8-2
Orientation . . . . . . . . . . . . . . . . . . . . . . .
8-3
AD536A - Integrated Circuit, True rms-ta-dc Converter
8-5
AD636 - Low Level True rms-to-dc Converter . . . . .
8 - 11
AD637 - High Precision Wideband rms-to-dc Converter
8 - 17
AD736 - Low Cost, Low Power, True rms-to-dc Converter
8 - 25
AD737 - Low Cost, Low Power, True rms-to-dc Converter
8 - 29
Special Function Components - Section 9
9-1
Orientation . . . . . . . . . . . . . . . . . . . . .
9-3
AD345 - High Speed Pin Driver with Inhibit Mode .
9-5
AD630 - Balanced Modulator/Demodulator
9-9
AD639 - Universal Trigonometric Function Converter
9 - 17
AD890 - Precision Wideband Channel Processing Element .
9 - 29
AD891 - Rigid Disk Data Channel Qualifier . . . .
9 - 35
9 - 41
AD9500 - Digitally Programmable Delay Generator
....
Temperature Transducers - Section 10
10 - 1
Selection Guide . . . . . . . . . . . . . . . . .
10 - 3
Orientation '. . . . . . . . . . . . . . . . . . . . . .
AD590 - Two-Terminal IC Temperature Transducer.
10- 4
10 - 5
10 -7
AD592 - Low Cost, Precision IC Temperature Transducer.
10 - 17
AC2626 - General Purpose Temperature Probe . . . .
Signal Conditioning Components & Subsystems - Section 11
11- 1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11- 3
Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11- 4
AD594/S95 - Monolithic Thermocouple Amplifiers with Cold Junction Compensation .
11- 5
11-13
11 - 19
AD5%/597 - Thermocouple Conditioner and Set-Point Controller
AD693 - Loop Powered, 4-20mA Sensor Transmitter
....
IB21 - Isolated Loop Powered, Voltage-to-Current Converter
11- 31
1B22 - Programmable Isolated Voltage-to-Current Converter .
11- 35
IB31 - Wide Bandwidth Strain Gage Signal Conditioner
11- 37
IB32 - Bridge Transducer Signal Conditioner
11- 45
....... .
GENERAL INFORMATION 1-7
Page
IB41 - Isolated RTD Signal Conditioner . . . . . . . . . . . . . . • . . • . . . . . . . . . . . . • . . . . . . . . .
IB51 - Isolated mViThermocouple Signal Conditioner . . . . . . . . . • . . . .
2B20 - High Performance, 4-20mA Output Voltage-to-Current Converter . . . .
2B22 - High Performance, Isolated Voitage-to-Current Converter
....... .
2B23 - Programmable Output, Isolated Voltage-to-Current Converter . . . . . .
2B30/2B31 - High Performance, Economy Strain GagelRTD Conditioners . . . .
2B50 - Isolated ,Thermocouple Signal Conditioner . • . . . . . . . .
2B54/2B55 - Four-Channel Isolated Thermocouple/mV O;lnditioners .
2B Series - Low Cost Two-Wire Transmitters . . . . . . . . . . . .
3B Series - Complete Signal Conditioning I/O Subsystem
4B Series - Alarm Limit Subsystem
..... .
................ .
5B Series - Compact, Low Cost Modular Signal Conditioners
Digital Panel Instruments - Section 12
11 - 53
11- 55
11- 59
11- 63
11- 67
11-71
11-77
11- 81
11- 87
11- 89
11- 93
11- 95
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . .
12 - I
12 - 2
Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . .
12 - 4
AD2010 - Low Cost, 3 112 Digit DPM for OEM Applications . . . . . . . .
12 -9
AD2021- Low Cost, 3 112 Digit, Logic Powered DPM with LED Displays . . . . . . . .
12 - 11
AD2026 - Low Cost, 3 Digit, AC Line or Logic Powered DPM . . . . . . . . . . . . . .
12 - 13
AD2050/2051 - Microprocessor Based Thermocouple Meters . . . . . . . • . . . . • . . .
12 - 15
AD2060/2061 - Microprocessor Based Autoranging RTDlThermistor Meters
12 - 17
..... .
AD2070/2071 - Microprocessor Based Autoranging Thermocouple Meters . . . . . . ., . .
12 - 19
Application Specific Integrated Circuits - Section 13
. . . . . . . . . . . . . . . ..
13-1
. . . • . . . • . . . . . . . . . . . . . . . . . ..
14 - 1
.............................
IS - 1
.................................
16 _ 1
Power Supplies - Section 14
Component Test Systems - Section 15
Package Information - Section 16
Appendix - Section 17
17 - 1
Ordering Guide . . . • . . . . . . • . .
17 -2
Product Families Still Available . . . . .
17 -4
Substitution Guide for Product Families No Longer Available
17 - 5
Technical Publications
...
17 - 6
Worldwide Service Directory
17 - 8
Index - Section 18
18 - 1
1-8 GENERAL INFORMA TION
Operational Amplifiers
Contents
Page
Selection Guide . . . . . . . . . . . . . . . . . . . .
Orientation . . . . . . . . . . . . . . . . . . . . . .
AD380 - Wideband Fast-Setding FET-Input Op Amp
AD38l/382 - High Speed, Low Drift, FET Operational Amplifiers
AD507 - IC Wideband, Fast Slewing, General Purpose Operational Amplifier .
AD509 - High Speed, Fast Settling IC Op Amp . . . . . . . . . . . . . . '.'
AD515A - Monolithic Precision, Low Power FET-Input Electrometer Op Amp
AD517 - Low Cost, Laser Trimmed Precision IC Op Amp . . . .
AD542/544/547 - High Performance, BiFET Operational Amplifiers .
AD548 - Precision, Low Power BiFET Op Amp . . . . .
AD549 - Monolithic Electrometer Operational Amplifier .
AD642 - Precision Low-Cost, Dual BiFET Op Amp
AD644 - Dual High Implanted BiFET Op Amp . . .
2-2
2-4
2 - 15
2 - 21
2 - 27
2 - 31
2 - 35
2 - 41
AD845 - Precision 16MHz CBFET Op Amp . . . . . .
AD846 - Very High Speed Operational Amplifier . . .
2 - 47
2 - 55
2 - 63
2 - 75
2 - 81
2 - 87
2 - 93
2 - 103
2 - 105
2 - 107
2 -1l9
2 - 131
2 - 133
2 -137
2 - 149
2 - 153
2 - 157
2 - 159
2 - 161
2 - 163
2 - 165
AD847 - High Speed, Low Power Monolithic Op Amp
AD848 - High Speed, Low Power Monolithic Op Amp
AD849 - High Speed, Low Power Monolithic Op Amp
AD5539 - Ultrahigh Frequency Operational Amplifier .
2 - 179
2 - 181
2 - 183
AD647 AD648 AD707 AD708 AD71lAD712 -
Ultralow Drift, Dual BiFET Op Amp . . .
Dual Precision, Low Power BiFET Op Amp
Ultralow Drift Op Amp . . . . . . . . . . .
Dual Ultralow Drift Op Amp . . . . . . . .
Precision Low Cost, High Speed BiFET Op Amp
Dual Precision, High Speed BiFET Op Amp .
AD713 - Quad Precision, High Speed BiFET Op Amp
AD741 Series - Low Cost, High Accuracy IC Op Amps
AD744 AD746 AD821 AD840 AD841 AD842 -
Precision 500ns Settling BiFET Op Amp . . .
Dual Precision 500ns Setding BiFET Op Amp
Single Supply, Low Power, Precision Op Amp
Wideband Fast Setding Op Amp . . . . . . .
Wideband, Unity Gain, Stable Fast Setding Op Amp
Wideband, High Output Current, Fast Settling Op Amp.
AD9610 - Wide Bandwidth, Fast Settling Operational Amplifier .
AD9611 - Wide Bandwidth, Fast Settling Operational Amplifier .
ADLHOO32G/OO32CG - Ultrafast FET Operational Amplifiers
ADLHOO33G/0033CG - High Speed Buffer Amplifiers
AD OP-07 - Ultralow Offset Voltage Op Amp . . . . . . . .
AD OP-27 - Ultralow Noise, Precision Op Amp . . . . . . .
AD OP-37 - Ultralow Noise, High Speed Precision Op Amp (A vcL 2:5)
HOS-050/050Al05OC - Fast Setding Video Operational Amplifiers . . .
HOS-060 - Low Offset, Fast Settling Video Operational Amplifier. . .
HOS-l00AH/l00SH - Wide Bandwidth, High Speed Buffer Amplifiers
HOS-200 - Wide Bandwidth, High Speed Buffer Amplifier . . . . . .
2 - 177
2 - 199
2 - 207
2 - 215
2 - 219
222.. 2 -
223
229
237
245
2 - 251
2 - 255
2 - 257
OPERA TfONAL AMPLIFIERS 2-1
Selection Guide
Operational Amplifiers
HIGH SPEED AMPLIFIERS
Supply
Current
rnA
Offset
Voltage
mV
GBWP
MHz
Slew Rate
V/,.._
Load
Settling Time Current
os to %
rnA
ADS539
ADS49
ADS46
AD840
AD96 II
1400
750
450
400
280
600
300
450
400
2100
12
65
110
110
13
I
0.1
0.01'
0.01
0.1
20
35
50
50
50
14
5
5
14
25
ADS48
AD96 10
HOS-050
HOS-060
AD842
175
100
100
100
80
300
3500
300
300
3'5
65
20
80
80
110
0.1
0.1
0.1
0.1
0.01
35
50
100
100
100
5
25
20
20
17
0.5
0.5
15
ADLH0032
ADS41
AD847
AD380
ADS07
70
40
50
40
35
500
300
300
330
35
300
110
65
250
900
0.1
0.01
0.1
0.01
0.1
50
50
35
60
20
20
16
5
12
4
2
1
0.5
1
3
ADS09
AD845
AD744
AD381
AD382
20
16
13
5
5
120
100
75
30
30
500
300
500
750
750
0.1
0.01
0.01
0.1
0.1
50
10
10
50
6
10
3.5
5
6
S
0.25
0.25
Model
Minimum
Stable
Gain
3
.0.5
0.075
0.5
0.5
Page
Note_
3
25
I
10
I
22222-
IS3
lSI
165
157
207
Transimpedance amplifier
5
1
2
22222-
179
199
245
251
161
I
1
1
10
22222-
215
159
177
15
27
22222-
31
163
137
21
21
Transimpedance amplifier
Transimpedance amplifier
FET input, external compensation
FET input, external compensation
FETinput
FET input, dual available
FETinput
FETinput
UNITY GAIN BUFFERS
Model
-3dB
Bandwidth
MHz
Slew Rate
V/,..s
Load
Current
rnA
Supply
Current
rnA
Offset
Voltage
mV
200
125
100
1600
1500
1500
100
100
100
15
15
20
10
5
5
HOS-2oo
HOS-100
ADLH0033
Page
2 - 257
2 - 255
2 - 219
PRECISION AMPLIFIERS
(low Vos, low drift, high de gain)
Model
AD707
ADOP-07
ADOP-37
ADOP-27
AD517
AD821
AD548
AD547
Offset
Voltage
,..V
Offset
Drift
15
25
25
25
0.1
0.6
0.6
0.6
50
250
250
250
1.3
3
2
I
,..vrc
2-2 OPERA TlONAL AMPLIFIERS
Bias
Current
nA
I
2
40
40
0.01
0.01
0.Q25
Open-Loop
Gain
Slew Rate
kVN
V/,..s
13000
3000
1000
1000
0.3
0.17
17
2.S
1000
300
300
250
0.1
3
GBWP
MHz
0.9
0.6
63
1.3
. I
Page
Notes
2222-
103
223
237
229
Dual available
2222-
41
153
55
47
Decompensated AD OP-27
LownOlse
Single-supply, low power
Low power, dual available
Dual available
LOW INPUT CURRENT AMPLIFIERS
Model
AD549
AD515A
AD548
Input
Current
pA
Offset
Voltage
mV
Off.et
Drift
...VI"C
Open-Loop
Gain
kVN
Slew Rate
0.06
0.075
10
0.25
I
0.25
5
IS
2
300
40
300
3
0.3
1
Vi ....
GBWP
MHz Page
I
0.35
1
Note.
2 - 63
2 - 35
2 - 55
Dual available
LOW COST, GENERAL PURPOSE OPERATIONAL AMPLIFIERS
Model
AD711
AD548
ADOP-07
AD544
AD542
AD741
Off.et
Voltage
mV
Offset
Drift
...VI"C
Bia.
Current
nA
Open-Loop
Gain
kVN
Slew Rate
2.
2
0.15
2
2
6
20
20
2.5
20
20
0.05
0.025
12
0.05
0.05
500
200
200
1000
30
100
20
20
I
0.17
13
3
0.5
Vi ....
GBWP
MHz
4
I
0.6
2
Settling
Time
to 0.01%
I",s
8",s
3",s
Page
Note.
222222-
Dual, quad available
Dual available
107
55
223
47
47
133
Dual available
Dual available
DUAL OPERATIONAL AMPLIFIERS
Model
Off.et
Voltage
mV
AD642
AD644
AD647
AD648
AD708
AD712
AD746
0.5
0.5
0.25
0.25
0.03
0.25
0.25
Off.et
Drift
...V/oC
I
2
0.3
Bias
Current
nA
Open Loop
Gain
kVN
0.035
0.035
0.025
0.01
250
50
250
300
13000
200
200
0.035
0.06
Slew Rate
Vi ....
13
3
I
0.3
20
60
GBWP
MHz
Settling
Time
toO.Ol%
1
2
0.9
4
13
I",s
500ns
Page
Type
2 -75
2 - 81
2 - 87
2 - 93
2 - lOS
2 - 119
2 - 149
DualAD542
DuaIAD544
DualAD547
DualAD548
DualAD707
DualAD711
DuaIAD744
QUAD OPERATIONAL AMPLIFIERS
Model
Off.et
Voltage
mV
AD713
0.25
Offset
Drift
...VI"C
Bia.
Current
Slew Rate
nA
Open-Loop
Gain
kVN
Vi ....
GBWP
MHz
Settling
Time
to 0.01%
0.035
200
20
4
I",.
Page
Notes
2 - 131
QuadAD711
OPERA TIONAL AMPLIFIERS 2-3
Orientation
Operational Amplifiers
The amplifiers listed in this volume are intended to provide
cost-effective solutions to the bulk of op-amp requirements in
precision measurement and control, as well as to more general
requirements in electronic circuits. The technical data included
here* cover the properties of more than 40 op amp families,
comprising about 100 distinct types. Some are general purpose;
others provide near optimum performance for specific classes of
application.
They differ in a variety of ways, for example, circuit technology,
circuit architecture, package type and contents, input properties,
output properties, operating temperature range and in terms of
the many performance specifications. Most are monolithic les,
including precision and high-speed dual devices; some are hybrid
les.
The Ie and hybrid amplifiers catalogued in this volume are
available in a broad choice of packaging styles, temperature
ranges, and performance grades. If your application calls for
versions of these products that have been processed in accordance
with MIL-STD-883, a wealth of relevant information can be
found in the latest edition of the Military Products Databook,
available free upon request from Analog Devices.
BACKGROUND
The operational amplifier is today the most widely used analog
subassembly. It is safe to say that its basic properties and applications are sufficiently understood by most circuit designers and
builders. However, the basis for choice, the subtleties of using
op amps in circuits for best results (especially in precision measurement and control) and the varieties of possible applications
are less clearly understood by op amp users, in varying degrees.
In these few pages, we shall address the question of making a
proper choice of op amp type for an application, in relation to
the extensive array of device properties presented in the data
sheets that follow.
For those users requiring basic tutorial material, and detailed
information on getting the most out of op amps, we have provided
on page 2-14 a bibliography t:h;it should make available up to
99% of information needed now and then, with "fanout" to the
vast body of literature that - with some redundancy - will provide
the remainder. Analog Devices' op-amp data sheets are an excellent
source of pertinent information.
SELECTION PRINCIPLES
In selecting the right device for a specific application, you should
have clearly in mind your design objectives and a firm understanding of what published specifications mean. Beyond this,
you should detail the significant variables that are pertinent to
your application. The purpose of this section is to put these
many decision factors into perspective to help you make the
most meaningful buying decisions.
*In addition to the products listed here, which are recommended for new
designs, a number of older products are stiD available (see page 17-4);
data sheets are available upon request.
2-4 OPERA TIONAL AMPLIFIERS
To make a proper choice of an operational amplifier for any
given set of requirements, the designer must have:
1. A complete definition of the design objectives.
Signal levels, closed-loop gain, accuracy desired, bandwidth
requirements, circuit impedance, environmental conditions
and other factors must be well defined before selection can
be effectively undertaken.
2. Firm understanding of what the manufacturer means by the
numbers published for the parameters.
Two manufacturers may have comparable published specifications, but they may have been arrived at using differing
measurement techniques. This creates a pitfall in op amp
selection. To avoid these difficulties, the designer must know
what the published specifications mean and how these parameters are measured and then must be able to translate
these published specifications in terms meaningful to the
design requirements.
There are three fundamental aspects to the rational selection of
an operational amplifier for a given application: (1) establishing
the circuit architecture, (2) defming the performance levels and
(3) choosing the amplifier(s).
1. To obtain a circuit building block to implement a defined
functional job, the principal choices are either to purchase a
committed functional device or to design a circuit employing
op amps to perform the function. For example, to obtain a
difference between two voltages, one may either purchase an
instrumentation or isolation amplifier or design a suitable
subtraction circuit using clp amps. If a committed functional
building block, with appropriate specs and price, is not available, the circuit designer must start by developing schematic
diagrams of circuits that will perform the function simply
using "ideal" operational amplifiers. Many commonly used
circuits can be found in textbooks, "cookbooks" and linear
circuit books as well as in application notes and data sheets.
2. Recognizing that the choice of an op amp depends on both
the overall circuit requirements and the characteristics of
available op amps, the designer should interpret the desired
overall performance in terms of the parameters of op amps
and establish acceptable ranges of parameters and their variation
with time, temperature, supply voltage, etc. Examples of the
key parameters are the input offset voltage, input bias and
offset currents, and the high frequency performance and
transient behavior of the op amp block (and its effect on the
closed-loop circuit) for large and small signals. It will be
helpful to develop an application checklist which includes
such considerations as the character of the input signals and
their impedance, the output load, the desired accuracy static and dynamic - and the environmental conditions.
3. The designer must then relate acceptable performance of the
op amp building block to the specifications and prices of
available devices from preferred suppliers, bearing in mind a
firm understanding of the way in which manufacturers define
their specifications and how definitions can differ in a way
that may be misleading. A set of definitions used by Analog
Devices follows this discussion.
APPLICATION CHECKLIST
By way of an application checklist, the designer will need to
account for the following:
Character of the application: The character of the application
(inverter, follower, differential amplifier, etc.) will often influence
the choice of amplifier. For example, an adjustable-gain wideband
application may call for a transimpedance op amp to keep bandwidth
independent of gain setting.
Accurate description of the input signal: It is extremely important
that the input signal be thoroughly characterized. Is the input a
voltage source or current source? Range of amplitude? Source
impedance? Time/frequency characteristics?
Environmental conditions: What is the maximum range of temperature, time and supply voltage over which the circuits must
operate (to the required accuracy) without readjustment?
Accuracy desired: The accuracy requirement determines the
extent to which the foregoing considerations are critical, and
ultimately points the way to a device (or series of devices) which
are acceptable. Accuracy must, of course, be defined in terms
meaningful to the application with regard to bandwidth, dc
offset and other parameters.
SELECTION PROCESS
In general, the objective of amplifier selection should be to
choose the least expensive device which will meet the physical,
electrical and environmenal requirements imposed by the application. This suggests that a "General Purpose" amplifier will be
the best choice in all applications where the desired performance
requirements can be met. Where this is not possible, it is generally
because of limitations encountered in two areas - bandwidth
requirements and/or offset and drift parameters.
To make it easier to relate bandwidth requirements with the
drift and offset characteristics, a capsule view of bandwidth
considerations precedes the dc discussion below. The reader is
then returned to an expanded discussion of gain bandwidth
considerations.
Gain Bandwidth Considerations, A Capsule View
Although all selection criteria must be met simultaneously,
determination of the bandwidth requirements is a logical starting
point because:
I. If dc information is not of interest, a suitable blocking capacitor
can be connected at the amplifier input and/or output and all
of the "drift" specifications may usually be ignored, and
2. Where high frequency (> lOMHz) characteristics are of primary
importance, the choice will be limited to those amplifiers
designated "Wide Bandwidth/Fast Settling."
Where dc information is required and where frequency requirements are relatively modest (full power response below 100kHz,
unity gain bandwidth of less than 1.5MHz) other criteria will
probably influence the final choice. It is important, however, to
choose an amplifier with which an adequate value of loop gain is
assured (at the maximum frequency of interest) to obtain the
desired accuracy. Loop gain is the excess of open-loop gain over
closed-loop gain, and is responsible for the diminishing error
due to fluctuations in the open-loop gain due to time, temperature,
etc. For example, if the closed-loop gain is 1,000, the open-loop
gain must be at least 100,000 to yield an error of no more than
1%, and 1,000,000 to yield an error no greater than 0.1%. Where
undistorted response is required, the specifications for full linear
response and slewing rate should be chosen such that they are
not exceeded at the highest frequency of operation.
Most operational amplifiers are voltage-to-voltage amplifiers.
However, for wide bandwidth applications, it is often useful to
consider applying a class of current-to-voltage amplifiers called
transimpedance ampltfters. They are characterized by transresistance
(!!.Vo/!!.I,) instead of gain (!!.Vo/!!.V,). Unlike voltage amplifiers,
with their high input impedance, transimpedance amplifiers
have low (ideally zero) input impedance in order to minimize
the gain-error voltage developed by their input current. Such
amplifiers tend to be characterized by high slewing rates and
high closed-loop bandwidth. In contrast to the constant gain x
bandwidth of most voltage amplifiers, the closed-loop bandwidth
of a transimpedance amplifier is essentially independent of closedloop gain - as long as the feedback resistance is kept constant
when the gain is adjusted.
Offset and Drift Considerations
In the majority of op amp applications, final selection is determined
by the dc offset and drift characteristics. To undertake amplifier
selection in these cases, it is necessary to translate the requirements
listed above as follows. (It is assumed that bandwidth requirements
and temperature range have been established at this point.)
1. What input impedance must the circuit present to the signal source?
This depends primarily on the source impedance, R" and
the amount of loading error which is acceptable. Most amplifier
circuits are designed around the inverting and noninverting
circuits of Figure 1. The choice is often made between the
two to accommodate the impedance requirement. Input
impedance for the inverting circuit is approximately equal to
the summing impedance, R" and the upper limit on the
magnitude of R, is determined by the allowable drift error
because of input bias current as discussed below. The noninverting circuit offers inherently higher input impedance than
the inverting circuit (due to "bootstrapping" feedback), and
in this case input impedance is approximately equal to the
common-mode impedance of the amplifier ReM'
2. How much drift error can be tolerated? The question is related
to the input signal level, e" and the required accuracy. For
example, to amplify or otherwise manipulate a dc input signal
of one volt with an accuracy of 0.1 %, the offset drift error,
Vd, must be one millivolt or less. (This assumes that other
sources of error such as input loading, noise and gain error
have already been allowed for.) By the same reasoning, the
allowable drift error for a 1 volt signal and 0.01% accuracy
would be 100fLV.
When this has been defined, the allowable limits of offset
voltage (eo,), bias current (ib) and difference current can be
calculated by the equations of Figure 1.
Figure 1 gives the equations which relate offset voltage (eos),
bias current (ib)' difference current (id) and the external circuit
impedances to the drift error, Vd, for both the inverting and the
noninverting circuits. From these equations it can be seen how
the input impedance requirements of the foregoing paragraphs
are related to the drift error.
OPERA T10NAL AMPLIFIERS 2-5
and this will always be less than the input impedance, R" of the
inverter. Input impedance of the noninverter (approximately
ReM) is typically 107 ohms even for the least expensive bipolar
amplifiers and up to 1011 ohms for FET types.
"
80
Rt r.
=-R."
les + eO!
(Rt + R,)
~
+
Ib
For RC
]
RI
80
=-
Rf
r.
Rf + R
1
.
RI
For RC "" RI Rf/(R. + Rf)
R;"" Les + eos~ + IdR~
-~
=0
and Rs«
'-r'~
Signal Input Dnft Error = Vd
and Rs«
RI
Signal Input Drift Error::: Vd
Input Impedance RIN ~ RI
% Drift Error = 100Vd
e,
Figure la. Inverting Configuration
"
eo
R2 + R, f.
=--R-,Les
Unfortunately, however, the noninverting configuration cannot
always be used since it is not convenient to use for many circuit
functions such as integration or summation. A further limitation
occurs in high accuracy applications where common-mode errors
may rule out this circuit configuration. Transimpedance amplifiers
in the noninverting configuration have high dynamic input
impedance, but they must be driven from a source that can
furnish the input current. This rules out the possibility of unloading
some high impedance sources but still permits a single amplifier
to be used for noninverting gains (as always, it is helpful to
consult the data sheet).
Initial offsets can usually be zeroed at room temperature so that
only the maximum temperature excursion (AT) from +25'C
need be considered. For example, over the range of - 25°C to
+ 85°C, the maximum temperature excursion (AT) from +25oG
would be 60°C. As a practical matter, offset errors due to supply
voltage and time drift can generally be neglected since errors
due to temperature drift are usually much greater.
Current Amplifier Considerations
Before leaving the subject of offset errors, we shall discuss
briefly the current amplifier configuration which is shown in
Figure 2a. The obvious approach to measuring current is to
develop a voltage drop across a load resistor, Rf , and to measure
this potential with a high impedance amplifier as shown in
Figure 2b.
1
+ eU $ + Ib RSJ for Rc ::: 0
~
Signal
-----...-..--
R2 + R, [
eo = - - - as +
RI
"
Dnft Error"" Vd
80s
+
Id
]
Rs for Rc
=
R, R2
Rs - - - RI + R2
~----...----
Signal
Dnft Error"" Vd
Input Impedance RIN ;;::;- ReM
% Drift Error = 100Vd
e,
Figure lb. Noninverting Configuration
eo
= -Rf
....,....
.
(R~.+R:s)
[IS + 8
Signal
0s
Drift error
Input Impedance RIN
+ ibJ
= Ie
= (R~f+R~d ) (
where liP =1 + Rt (R, + Rdl
Rs
Rd
1 +1
A/3)
% Drift Error = 10~ If
'.
Figure 2a. Current Amplifier
For example, in the case of the inverting circuit, an offset error
voltage, it>R" is generated by the bias current flowing through
the summing impedance. This error increases for increasing Ri .
Since Ri also sets the input impedance, there is a conflict between
high input impedance and low offset errors. Likewise, for a
given offset error, higher values for R, can be used with an
amplifier which has lower bias current.
Where it will otHerwise function properly, the noninverting
circuit generally makes a better choice for high input impedance
circuits. Also, for the same source and input impedance requirement, a given amplifier will generate lower offset errors for the
noninverting circuit than for the inverting circuit. This is so
because the bias current flows only through R, for the noninverter
2-6 OPERA TIONAL AMPLIFIERS
"
eo
= Rf
Is
+
eos
+ ib Rf for Rs > Rf
~ , Drift' Error =Vd
Input Impedance RIN
% Drift Error =
.<::;:
Rt
1ROO~d
t "
Figure 2b. Voltage Amplifier with Sampling Resistor
This approach has several disadvantages as compared to the
circuit of Figure 2a. First, the noninverting amplifier introduces common-mode errors which do not occur for Figure 2a.
Second, an ideal current meter would have zero impedance
whereas R f in Figure 2b may become very large since this resistor
determines the sensitivity of the measurement. Third, the changes
of input impedance, Rem, for the noninverting amplifier with
temperature will cause variable loading on R f and hence a change
in sensitivity.
The current amplifier of Figure 2a circumvents all of these
difficulties and approaches an ideal current meter; that is, there
is essentially no voltage drop across the measuring circuit, since
with enough open-loop gain, A, the input impedance RIN becomes
very small.
In selecting a current amplifier, the most important consideration
is current noise, and bias current drift. Measuring accuracy is
largely the ratio of current noise and drift to signal current, i,.
To obtain the drift of error current IE referred to the input, use
the following expression.
L> I = [L> eos ( Rf + Rs ) + L> is] L> T
E
L>T
RfR.
L>T
inverting and noninverting circuits must be evaluated in light of
the common-mode rejection error (with frequency) introduced
by the non inverter.
For greater emphasis, wideband applications can be separated
into categories - steady state and transient. Since the amplifier
requirements for the two are somewhat different, these categories
will be discussed separately.
STEADY STATE APPLICATIONS
Steady state applications involve amplifying or otherwise manipulating continuous sinusoidal, complex or random waveforms.
In these applications the significant issues in choosing an amplifier
are as follows:
1. Is dc coupling required? If dc information is of no consequence,
then the offset drift errors are not usually important and a
capacitor can be used if necessary to block the output dc
offset. Your only concern here is that dc offset at the output
does not become so large, as might be the case with a high
gain stage, that the output is saturated or the dynamic swing
for ac signals is limited. One way to circumvent the latter
problem is to use feedback to lirriit the gain at dc as shown
in Figure 3. The gain of this kind of circuit can be small at
dc but large at high frequencies.
Now, to make a proper selection you must pick an amplifier
with an error current, IE' over the operating temperature which
is small compared to the signal current, i,. Do not overlook
current noise which may be more important than current drift
in many applications.
Gain Bandwidth Considerations, Expanded Discussion
From the previous discussion, it is apparent that most general
purpose operational amplifiers will usually give adequate performance for dc and audio-frequency-range applications. However,
amplifiers having unity-gain bandwidth above 2MHz, full power
response above 20kHz and slewing rate above 6V/f1s, in general,
require special design techniques. Amplifiers with wideband,
fast response characteristics have been listed in the Wide
Bandwidth group to simplify the selection for higher frequency
applications.
One factor often overlooked is that stray capacitance and impedance
levels of the external feedback circuit can be the major limitation
in high frequency applications. For example, in Figure la, if R f
were one megohm, and stray capacitance, C s , were one picofarad,
then the closed-loop bandwidth would be limited to 160kHz
(1I(27rR 1,cs» regardless of how fast the amplifier is. Moreover,
output slewing rate will be limited by how fast Cs can be charged,
which in turn is related to signal level, e" and input impedance,
R" by deJdt = - eJR,C s . For these reasons it is usually not
possible to obtain both fast response and high input impedance
for an inverting circuit since both R, and R f must be large to
obtain high input' impedance.
Another advantage of the noninverting circuit (Figure 1b) is
that input impedance, being determined by potentiometric feedback, is independent of the impedance levels for R, and R 2.
Therefore, a low impedance can be used for R2 so that stray
capacitance of Cs will not limit the circuit's bandwidth. In this
case the minimum value for R2 is constrained only by the
output current rating of the amplifier. Again the trade-off
between the frequency response and input impedance of the
>----+-0 ..
--------:7r"---1
1
(As + Asl C
R3e
Figure 3. DC Feedback Minimizes Output Offset
for AC Applications
2. What closed-loop gain and bandwidth are required? Closed loop
gain, G, is dictated by the application. For V/V amplifiers,
to a first approximation the intersection of the open- and
closed-loop gain curves in Figure 4 gives the closed loop
bandwidth, fcl ( - 3dB). For high gain, wideband requirements,
it may be necessary, or more economical, to use two amplifiers
in cascade each at lower gain. For transimpedance amplifiers,
fcl changes little over a wide range of gain as set by the choice
ofR,.
3. What loop gain is requtred or alternatively what gain stabIlity,
output impedance and/or lmearity are necessary? The available
loop gain at a particular frequency or over a range of frequencies
is very often more important than closed-loop bandwidth in
selecting an amplifier. Loop gain as illustrated in Figure 4, is
defined as the difference, in dB, or as the ratio, arithmetically,
of the open- to closed-loop gain (Af3 = A/G). You will find in
most of the equations defining the closed-loop characteristic
of a feedback (V/V) amplifier that the loop gain (Af3) is the
OPERA TIONAL AMPLIFIERS 2-7
•
determining factor in performance. Some of the more notable
examples of this point are as follows:
Eo +AE-.....
ERROR
BAND
1 -FINALVAWE. 'Eo- - --
SLEWING
_
RECOVERY
LINEAR SETTLING
SETTLING TIME TO ± L ! . E - I
OR±~ x 100%
E.
Figure 4. Closed Loop Bandwidth and Loop Gain
a. Closed-loop gain stability = AG/G
AG/G=(AAlA) [l/(l+A!3)) where AA/A is the open-loop
gain stability, usually about 1%rc.
b. Closed-loop output impedance = Zocl = Z.,I(1 + A!3), where
Zo is the open-loop output impedance, usually 200 to 5,000
ohms.
c. Closed-loop nonlinearity = Lcl = Lol/(l + A!3), where Lol is
the open-loop linearity error, usually less than 5%.
Loop gain of 100, or 40dB, is adequate for most applications,
and this is readily achievable at dc and low frequencies. But
note that loop gain decreases with increasing frequency which
makes it difficult to obtain large loop gains at high frequencies.
For this reason it may be necessary to use a 10MHz unity gain
amplifier in order to obtain adequate feedback over a 10kHz
bandwidth.
4. What full power response and/or slew rate are required?
You should examine your expected output waveform and
select an amplifier whose ~lewing rate, with the expected
capacitive output load, exceeds the maximum rate of change
of output signal. For a sinusoidal waveform with a peak
voltage output equal to the rated amplifier output the frequency
should not exceed fp, the full power response of the amplifier.
As the output signal voltage is reduced below the rated output
voltage, the usable maximum frequency can be extended
proportionately. If you do not observe these restrictions, you
will get distortion and unexpected dc offsets at the output of
the amplifier.
For some monolithic amplifier designs intended for high-gain
and wide-bandwidth applications, their frequency response is
not a simple 6dB roll-off; the response may be shaped with
external RC components for improved performance at lower
closed-loop gains. Using feedforward or phase lag compensation
networks, gain-bandwidth product and/or full power response
may be shaped to meet varying design requirements. Most
internally compensated VN op amps offer a stable 6dB per
octave roll-off with specified unity gain-bandwidth and slew rate
thereby limiting maximum speed and response to those published
specifications.
2-8 OPERATIONAL AMPLIFIERS
Figure 5. Typical Settling Time Characteristics
TRANSIENT APPLICATIONS
In applications such as AID and D/A converters and pulse amplifiers, the transient response of the wideband amplifier is generally
more important than the gain bandwidth characteristic described
above. Slewing rate, overload recovery and settling time are the
specifications which determine the transient response.
When applying the high frequency amplifier, it is important to
understand how amplifier performance is affected by component
selection as well as impedance levels used around the amplifier.
Settling Time
Settling time is defined as the time elapsed from the application
of a perfect step input to the time when the amplifier output
has entered and remained within a specified error band symmetrical
about the fmal value (Figure 5). Settling time therefore includes
the time required for the amplifier to slew from the initial value,
recover from slew rate limited overload, and settle to a given
error in the linear range.
The time and frequency response of a linear, bilateral network
or amplifier are related by well know mathematics. For example,
the step response for a well behaved, ideally linear, 6dB/octave
amplifier with a closed-loop bandwidth of Wcl is shown in
Figure 6.
However, since settling time is determined by a combination of
amplifier characteristics (both linear and nonlinear) and because
it is a closed-loop parameter, it cannot be readily predicted from
the open-loop specifications such as slew rate, small signal bandwidth, etc.
Analog Devices specifies settling time for the condition of unity
gain, relatively low impedance levels and no capacitive loading
(unless otherwise indicated). A full-scale step input is used to
determine settling time and the step is generally unipolar - i.e.,
from zero to plus or minus full scale. The settling time indicated
is generally the longest time resulting from a step of either
polarity and is given as a percentage of the full-scale step
transition.
Settling time is a nonlinear function. It varies with the input
signal level and it is greatly affected by impedances external to
the amplifier.
ERRORS DUE TO NOISE
A major criterion in the selection of an amplifier for low level
signals is the amplifier input noise, since this is usually the
limiting factor on system resolution. In the general case, amplifier
noise can be characterized by a voltage source in series with the
summing junction and a current source in parallel with the
summing junction. Whenever high source impedance is encountered, current noise flowing through the source impedance will
appear as an additional voltage noise, combining with the amplifier
voltage noise. The sum of these noise sources will then be amplified
along with the desired signal. For this reason, selection of a
particular amplifier must consider both the amplifier noise performance as well as the source impedance.
FINAL VALUE r =
~
l
of resistances in other bandwidths can be calculated by remembering that the noise is proportional to the square root
of the resistance and the bandwidth; i.e.
en (rms) = (40nV/vHz) (
Vl~!} (BW) )
2. To convert the rms noise to a Pop value, a conversion factor
of 6.6....V p-p/ ....V rms is applied for less than 0.1% probability
of noise peaks exceeding calculated limits.
3. The total rms noise contribution due to several noise sources
is deteruiined by the square root of the sum of the squares:
2...
r-----______-=:;~W"----~.If any noise source is less than a third of another, it may be
neglected. The resulting error will be less than 5%.
4. Restricting the bandwidth of a system to the minimum usable
and using the lowest impedances possible are ways to reduce
noise.
2.3T
46,
6ST - - ' T
Figure 6. Step Response for Linear 6dB/Octave Amplifier
DESIGN EXAMPLE
Figure 7a illustrates a typical circuit with noise calculations
shown for each noise source. The total of the noise sources is
obtained by adding each of the individnal sources in a rms
fashion.
Consideration must also be given to noise sources other than the
amplifier whenever determining total system noise. RF and digital noise may be fed into an amplifier through any connecting
wire, including power supply and output leads. Adequate shielding
and low-pass filters on all incoming leads will greatly reduce
noise pickUp.
Thermal noise is generated in any conductor or resistor as a
result of thermal agitation of the electrons. This noise voltage
source, sometimes referred to as "Johnson Noise," is generated
in the resistive component of any impedance and has a value:
where en =
k =
T =
B =
the rms value of the noise voltage
Boltzman's Constant (1.38 x 1023 jouleslK)
absolute temperature of the resistance, K
the bandwidth in which the noise is measured
Since noise is related to the bandwidth over which the measurement
is made, no noise specification is meaningful unless the bandwidth
for the specification is given. Although the thermal noise equation
may appear unwieldy, for practical noise calculations, all that is
required to enable rapid approximations is to apply a few simple
rules of thumb.
Rules of Thumb
1. Remember that a lOOkn resistor generates 40nV rms in a
1Hz bandwidth. The noise voltages generated by other values
.
COMPONENT
.,
CAUSE
OUTPUT CONTRIBUTION
R,.
Rs
Johnson N04se
Johnson NoISe
Johnson No.•
v'4kTBRIN (RF/R.NI
..j4kTBRs (RF/R'N + 11
'''''...
.,
Amp Curr.u No...
Amp. Current Noise
Amp Voltage No..
In,RF
IiI12Rsl (RF/RIN + 11
en (RF/R'N + 1)
~
Figure 7a. Noise Components
Figure 7b illustrates how the Rules of Thumb may be applied
in a practical case to approximate the total output noise.
In this example, a low noise type amplifier (AD OP-37) is
being used with a 50k!} source impedance. The two major noise
sources, in addition to the AD OP-37's input voltage noise of
0.18 ....V Pop, are the Johnson noise (59 ....V pop) and current
noise (83pA pop).
OPERA TIONAL AMPLIFIERS 2-9
-
-
- --- --------
101dl
GAIN-100
BW'" 0.01 TO 10Hz
RS = 50kn
RF" 10kn
RIN = 100n
1) RESISTOR NOISE RF
RIN
With the hope that it will be found useful, the following interpretive
list identifies the best device choices in a variety of categories:
-+ 13nV/VH'i
-+ 11 3nV/vHZ
Rs -+ l28nV/YHZ1101 .. 28,...V/YHZ
TOTAL RESISTOR NOISE IN 10Hz BW ::::
(28f1V/VHz) (v'iOiiiI6.6f1V p-pJp.V rms
59p.V pop
=
2) AMPLIFIER CURRENT NOISE 183pAp-p)ISOk)(101):::: 422fJ.VIRsl
(83pAp-p) (10k) :::: 0 B.,..VIRFI
31 AMPLIFIER VOLTAGE NOISE (0 18Vp-p)(101):::: 18 2tJ,Vp-p
TOTAL OUTPUT NOISE = V(4221 2 + (59)2 +(182)i +(0 18)li = 426p.Vp-p
Figure 7b. Design Example
HOW THE OPERATIONAL AMPLIFffiRS ARE
CLASSIFIED
To assist the designer in distinguishing among the many types
available from Analog Devices, we have provided a Selection
Guide in which amplifiers are grouped in terms of common
properties which have been optimized in order to satisfy the
needs of specific classes of applications. Once the choice has
been narrowed to the manageable number of types in any group,
distinctions can be drawn in terms of other requirements or
considerations.
Temperature Range and Nomenclature: Analog DeviCes operationalamplifier nomenclature uses suffixes to permit ready identification
of the temperature range for which device operation to meet
critical specifications has been designed or selected. The most
popular range comprises the "commercial" temperatures from 0
to 70°C; it is designated by suffixes such as J, K, L, M, in
order of increasingly tighter specs (e.g., AD549L). Also popular
is the "extended" range, - 55°C to + 125°C, designated by S,
T, U, (e.g., AD510S); not all families have types with specified
performance in this range. There are a few types designed for
operation in the "industrial" range, - 25°C to + 85°C, designated
by A, B. Wide-range types will generally meet the same or
better specs in a narrower temperature range. A few types are
second-sources for products originally introduced by other manufacturers. In those instances, the generic nomenclature is used
(AD741C) or enlarged upon, if superior selections are offered
(e.g., AD741L).
SELECTION GUIDES
Seven Selection Guides classify operational amplifiers within
these categories:
High-Speed Amplifiers
Unity-Gain Buffers
Precision Amplifiers (low Vos , low drift, high dc gain)
Low-Input-Current Amplifiers
Low-Cost, General-Purpose Op Amps
Dual OpAmps
Quad Op Amps
The choice of category depends on which class of specifications
is most critical. Within these categories, the selection guides
provide comparisons of salient specifications.
2-10 OPERATIONAL AMPLIFIERS
These selection areas are pretty broad; they include various
criteria, not all of which are central to the application. For
example, if one is seeking a high-input-impedance amplifier for
an ac application, voltage offset and drift may be far less critical
than bias current, and both of these may be unimportant compared
to bandwidth.
(At the extremes of performance are the fastest op amps and the
highest-pre~n op amps.)
The fastest op amps include those having
• the highest slewing rates, - the hybrid AD%10 (3,500V/ ....s)
and AD%ll (2,100V/ ....s), and the monolithic AD5539
(600V/ .... s)
• the lowest settling time - the monolithic CB (complementary
bipolar) AD840/8411842/846 (lIOns to ±0.01%), the hybrid
AD%lO and AD9611 (2Ons and Bns to 0.1%) and (again)
the AD5539 (12ns to 1.0%)
• the highest gain-bandwidth - the AD5539 (1,400MHz) and
the CB AD849 (725MHz) and AD840 (400MHz)
High-speed op amps are characterized by high slewing
rates, fast settling time and wide bandwidth. Fast settling
time is especially important in applications with rapidly
changing or switched analog data in buffers, D/A conver·
ters, and multiplexer circuits; wide small-signal bandwidth
is important in preamplification and in handling low-level
wideband ac signals; high slewing rate is associated with
fast settling time and is also important in bandling ac
signals baving large magnitudes with minimum distortion
since the large-signal bandwidth is closely related to the"
slewing rate.
Ies using the proprietary Analog Devices CB (com·
plementary bipolar) process contain wideband PNP and
NPN transistors that have similar characteristics - without
the use of dielectric isolation. Since poor frequency
response of lateral PNPs is the source of the bandwidth
limitation in conventional linear bipolar processes, CB
devices can have much faster response.
The highest-precision monolithic op amp families include those
having
• the grades with the lowest untrimmed offset voltag~ the AD707
(15 ....V) and AD OP-07/27/37 (25 ....V)
• the lowest bias current - the revolutionary electrometer op amp
using top-gate-FET inputs, the AD549 (60 femtoamperes)
• the lowest drift- the AD707 (lOOnVrC)
• the highest open-loop gain (hence highest accuracy as an integrator
and high-gain amplifier) - again the AD707! (13 x 10"VN)
and the CB FET-input AD821 (3 x 10"VN - also capable of
single-supply operation)
• the highest common-mode rejection - once again the AD707
(BOdB), followed by the AD OP-27/37 (1l4dB) and the AD
OP-07 (HOdB)
Precision op amps (in this list) include those empbasizing
• Low bias current and high Input impedance. These types
use the inherently high input impedance and low leakage
current of junction field-effect transistors (FETs) to deal
with configurations that measure low currents or involve
high resistance values. Applications range from general
purpose high-impedance circuitry to integrators, currentto-voltage converters, and log-function generation, to
measurements with high-impedance transducers such as
photomultipliers, flame detectors, pH cells and radiation
detectors.
• High accuracy through low offset and drift voltage, low
voltage noise, high open-loop gain, and high commonmode rejection (CMR). Such types are used for highaccuracy instrumentation, low-level transdu= circuitry,
precision voltage comparison, and impedance buffering.
All FET-input op amps from Analog Devices are
conservatively manufactured to meet their published
bias-current specifications afur full warmup (some manufacturers specify mitial current, which is lower than
warmed-up bias current). Our published max bias-current
specification applies to either input (some manufacturers
call "bias current" the Q'Derage of the two input
currents).
For applications needipg high, but not extreme, performance or
where high speed and high precision must be combined, there are a
number of device families to be considered. For example,
• the complementary-bipolar AD846 family combines low offset
voltage (200,...V) with high slewing rate (400Vi,...s)
• the AD744 BiFET family combines low input bias current (SOpA)
with low settling time (SOOns to 0.01%)
• the AD OP-37 family combines low drift (600nVrC) with wide
gain bandwidth (63MHz)
• the hybrid AD3811382 combine SOpA bias current with 0.7S,...s
settling time (to 0.1%) and SOmA output-cu~rent range
Fast amplifiers, which often boast output current ranges of
SOmA or l00mA, include families with
• high slewing rate - the CB monolithic AD846 (400V/,...s) and
AD840/8411842 (400/300/37SV/,...s), and the hybrid ADLH0032
(SOOVi,...s), AD380 (330V/,...s), and HOS-060 (300V/,...s)
• low settling time - the monolithic AD847/848/849 (6Sns to
0.1%) and hybrid HOS-OSO (80ns to 0.1%, 200ns to 0.01%),
and the AD84S and AD744 families (300ns and SOOns to
0.01%)
• wide gain-bandwidth - the monolithic AD848 (2S0MHz) and
the hybrid AD9611 (280MHz) and HOS-OSO/060 (100MHz)
High-precision monolithic amplifier families start with lower
grades of the highest-precision families; beyond this, they include
the
• low-drift AD OP-07127/37 families (600nVrC)
• hjgh-gain AD OP-07 (3 x 106) and AD OP-27/37 (l x 106 )
.• high-CMR AD821 (90dB); low-V", AD846 (200,...V) and a
• wide selection of low-bias-current FET-input op amps - the
AD821 and ADS48 (lOpA), and the AD711 (2SpA)
Many of these devices are duplicated in a single package; for
example,
•
•
•
•
•
the
the
the
the
the
AD712
AD746
AD648
AD708
AD713
is a dual AD711
is a dual AD744
is a dual ADS48
is a dual AD707
is a quad version of the AD711
Also included in this section are buffers, wideband amplifiers
having slightly less than unity gain, low output impedance and
high output-current availability (lOOmA). Although they can
stand alone, a more frequent use is inside-the-Ioop as a "booster"
amplifier to magnify the output power capability of any op amp
or reduce the dynamic output impedance without losing precision.
A typical example is the HOS-l00, which can follow slewing
rates of up to I,SOOV/,...s with a full-power frequency of 12SMHz
and deliver voltages up to ± 12V and currents up to ± 100mA.
DEFINITIONS OF SPECIFICATIONS
Absolute Maximum Differential Voltage
Under most operating conditions, feedback maintains the error
voltage between inputs to nearly zero volts. However, under
overload conditions or between applications, such as voltage
comparators, the voltage between the inputs can be large. This
specification defines the maximum voltage which can be applied
between inputs without causing permanent damage to the
amplifier.
Common-Mode Rejection
An ideal operational amplifier responds only to the difference
voltage between inputs (e + - e -) and produces no output for a
common-mode voltage, that is, when both inputs are at the same
potential. However, due to slightly different gains between the
plus and minus inputs, or variations in offset voltage as a function
of common-mode level, common-mode input voltages are not
eliminated at the output. If the output error voltage, due to a
known magnitude of common-mode voltage, is referred to the
input (dividing by the closed-loop gain), it reflects the equivalent
common-mode error voltage (CME) between the inputs. Commonmode rejection ratio (CMRR) is defined as the ratio of commonmode voltage to the resulting common-mode error voltage.
Common-mode rejection is usually expressed logarithmically:
CMR (in dB) = 20 10glO (CMRR).
The precise specification of CMR is complicated by the fact that
the common-mode voltage error can be a highly nonlinear function
of common-mode voltage and also varies with temperature. As a
consequence, CMR data published by Analog Devices are average
figures, assuming an end-point measurement over the commonmode range specified. The incremental CMR about sntall values
of common-mode voltage may be greater than the average CMR
specified but decrease and become less in the neighborhood of
large CMV. Published CMR specifications for op amps pertain
to low-frequency voltages, unless specified otherwise: CMR
decreases with frequency.
Common-Mode Voltage, Maximum
For differential-input amplifiers, the voltage at both inputs can
swing about ground (power-supply common) level. Common-mode
voltage is defmed as any voltage (above or below ground) that
could be observed at both inputs. The maximum common-mode
voltage is defmed as that voltage which will produce less than a
specified value of common-mode error. This establishes the
ntaximum input voltage for the voltage-follower connections.
Drift vs. Supply
Offset voltage, bias current and difference current vary as supply
voltage is varied. Usually, de errors due to this effect are negligible
compared to drift with temperature. No inference ntay be drawn
from this low-frequency specification concerning the effects of
rapid variation of voltage at the supply terminals.
OPERATIONAL AMPLIFIERS 2-11
Drift vs. Temperature
Offset voltage, bias current and difference current all change, or
"drift," from their initial values with temperature. This is by
far the most important source of error in most precision applications. The temperature coefficients (tempcos) of those patameters
are all defined as the average slope over a specified temperature
range. Drift can be a nonlinear function of temperature (though
it is often quite linear over limited temperature range); the
slopes generally are greater at the extremes of temperature than
around normal ambient ( + 2S°C), which generally means that
for small temperature excursions in the vicinity of + 2SoC, the
specification is conservative.
Analog Devices precision operational amplifiers ate specified by
three- (or more) point measurements, at 2SoC and at the high
and low extremes of the range (TH, TO, with the amplifier
adjusted to zero at room temperature. The sum of the magnitudes
of the drift in the two ranges must be less than the specified
drift rate (fJ'y1°C or nArC) multiplied by the total temperature
range (modified "butterfly"), or, in some cases, the magnitude
of the drifts in both ranges must be less than the specified drift
rate multiplied by the respective temperature ranges ("true
butterfly").
True Butterfly Spec
Modified Butterflv Spec
AOo.
100.HI+I"o.ll
t;T =
/). ~~s
TH -Tl
is the max. drift coefficient permiSSible
The lowest-cost second-source IC amplifiers are specified only
in terms of the maximum value of the parameter (e.g., offset
voltage) over temperature in the specified range.
Drift vs. Time
Offset voltage, bias current and difference current change with
time as components age. It is important to realize that drift with
time is random and rarely - if ever - accumulates lineatly for
healthy devices. For example, voltage drift might be quoted at
IS,.,.,V/month, whereas cumulative drift might not exceed SO,.,.,V
in a year. A convenient rule of thumb for extrapolation is to
divide the drift for a stated interval by the squate root of its
ratio to any other interval of interest.
Full-Power Response
The large-signal and small-signal response characteristics of
operational amplifiers differ substantially. An amplifier's output
will not respond to large signal changes as fast as the small-signal
bandwidth characteristics would predict, primarily because of
slew-rate limiting in the output stages. Full-power response is
specified in two ways: full linear response and full peak response.
Fuillineat response is specified in terms of the maximum frequency, at unity closed-loop gain, for which a sinusoidal input
signal will produce full output at rated load without exceeding a
predetermined distortion level. There is no industrywide accepted
2-12 OPERATIONAL AMPLIFIERS
value for the distortion level which determines the full-linearresponse limitation, but unless otherwise noted, we use 3% as a
a maximum acceptable limit.
In many applications, the distortion caused by exceeding the
full linear response can be comfortably ignored, but a more
serious effect (often overlooked) is an effect equivalent to dc
offset voltage that can be generated when fulliineat response is
exceeded, due to rectification of the asymmetrical feedback
waveform or overloading of the input stage by latge distortion
signals at the summing junction.
Another frequency response that is often of interest is the maximum
frequency at which full output swing may be obtained, irrespective
of distortion. This is termed "full peak response" and can often
be found in a plot of output voltage swing vs. frequency.
Initial Bias Current
Bias current is defined as the current required at either input
from an infinite source impedance to drive the output to zero
(assuming zero common-mode voltage). For differential amplifiers,
bias current is present at both the negative and the positive
input. All Analog Devices specifications pertain to the larger of
the two, not the average.
Analog Devices specifies initial bias current, Ib' as the bias
current at either input, specified at + 2SoC ambient with the
input junctions at normal operating temperature. (Some manufacturers specify initial bias current at power turn-on. Such
specifications may be misleading. For example, in FET-input
amplifiers, bias current is doubled for each 10°C increase; since
junction temperatures may warm up to 20°C or more above
ambient, the "initial bias current" specs used by some manufacturers may be met only during a brief interval after the power is
burned on, and Ib may be quadrupled under ordinary operation
conditions.)
Initial Difference Current
Difference current is defined as the difference between the bias
currents at the two inputs. Uncompensated input circuitry of
differential amplifiers is generally symmetrical, so that bias
currents at both inputs tend to be equal and tend to track with
changes in temperature and supply voltage. Therefore, difference
current is often about 0.1 times the bias current at either input,
assuming that initial bias current has not been compensated
internally at the input terminals. For amplifiers in which bias
currents track, it is often possible to reduce voltage errors due
to bias current and its variations by the use of equal impedance
loads at both inputs.
Input Impedance
Differential input impedance of voltage-input op amps is defined
as the impedance between the two input terminals at + 2SoC,
assuming that the error voltage is nulled or very neat zero volts.
To a first approximation, dynamic impedance can be represented
by a capacitor in parallel with a resistor.
Common-mode impedance, expressed as a resistance in pata1lel
with a capacitance, is defined as the impedance between each
input and power-supply common, specified at + 25°C. For most
circuits, common-mode impedance on the negative input has
little significance, except for the capacitance which it adds at the
summing junction (one exception is electrometer circuitry).
However, common-mode impedance on the plus input sets the
upper limit on closed-loop input impedance for the noninverting
configuration. Common-mode impedance is a nonlinear function
of both temperature and common-mode voltage. For FET-input
amplifiers, common-mode resistance is reduced by a factor of
two for each 10° of temperature rise. As a function of commonmode voltage, the resistive component is defined as the average
resistance for a common-mode change from zero to the maximum
common-mode voltage. Incremental resistance may be less than
the specified average value, especially at full-scale for some
FET -input amplifiers.
Input Offset Voltage
Offset voltage is defined as the voltage required at the input
from zero source impedance to drive the output to zero; its
magnitude is measured by closing the loop (using low values of
resistance) to establish a large fixed gain, measuring the amplified
error at the output and dividing the measured value by the gain.
The initial offset voltage is specified at + 25°C and rated supply
voltage. In most amplifiers, provisions are made to adjust initial
offset to zero with an external trim potentiometer.
Input Noise
Input voltage- and current-noise characteristics can be specified
and analyzed in much the same way as offset-voltage and biascurrent characteristics. In fact, long-term drift can be considered
as noise which occurs at very low frequencies. When evaluating
noise performance, bandwidth or period must be considered.
Also rms noise from different sources is summed by root-sum-ofsquares, rather than linear, addition. Depending on the amplifier
design, noise may have differing characteristics as a function of
frequency, being dominated by "lIf noise," resistor noise or
junction noise, at various frequencies.
For this reason, several noise specifications are given. Lowfrequency noise in the band 0.01 to 1Hz (or 0.1 to 10Hz) is
specified as peak-to-peak, with a 3.3cr uncertainty, signifying
that 99.9% of the observed peak-to-peak excursions will fall
within the specified limits. Wide band noise is specified as rms.
For some amplifiers types, spectral-density plots or "spot noise,"
at specific frequencies, in 11VtVRi or pA/vRZ, are provided.
Open-Loop Gain
where A is the open-loop gain and R/ is the resistance of the
external input resistor. The significant difference is that, as gain
or transresistance decreases with increasing frequency, the error
in transimpedance-amplifier circuits is independent of R/; hence
closed-loop gain can be increased by reducing R/ without substantially affecting bandwidth.
Overload Recovery
Overload recovery is defined as the time required for the output
voltage to recover to the rated output voltage from a saturated
condition caused by a 50% overdrive. Published specifications
apply for low impedances and contain the assumption that overload recovery is not degraded by stray capacitance in the feedback
network.
Rated Output
Rated output voltage is the minimum peak output voltage which
can be obtained at rated current or a specified value of resistive
load before clipping or out-of-spec nonlinearity occurs. Rated
output current is the minimum guaranteed value of current supplied
at the rated output voltage (or other specified voltage). Load
impedances less than the specified (or implied) value can be
used, but the maximum output voltage will decrease, distortion
may increase, and the open-loop gain will be reduced. (All models
are short-circuit protected to ground, and many are safe against
shorts to the supplies.)
Settling Time
Settling time is defined as the time elapsed from the application
of a perfect step input to the time when the amplifier output
has entered and remained within a specified error band symmetrical
about the final value. Settling time, therefore, includes the time
required: for the signal to propagate through the amplifier, for
the amplifier to slew from the initial value, recover from slew-rate
limited overload (if it occurs) and· settle to a given error in the
linear range. It may also include a "long tail" due to the time
required to reach thermal equilibrium, or the settling time of
compensation circuits. Settling time is usually specified for the
condition of unity gain, relatively low impedance levels, and no
(or a specified value of) capacitive loading, and any specified
compensation. A full-scale unipolar step input is used, and both
polarities are tested.
Open-loop gain is defined as the ratio of a change of output
voltage to the voltage applied between the amplifier inputs to
produce the change. Gain is specified at dc. In many applications,
the frequency dependence of gain is important; for this reason,
the typical open-loop gain as a function of frequency is published
for each amplifier type. See also unity gain small-signal response.
Although settling time can generally be grossly inferred from
the other amplifier specifications (an amplifier that has extra-wide
small-signal bandwidth, extra-fast slewing and excellent full-power
response may reasonably - but not always - be expected to have
fast settling), the settling time cannot usually be rationally predicted from the other dynamic specifications.
For transimpedance amplifiers, since the input is a current and
the output is a voltage, the "gain" is expressed in ohms
(R = VII). Because small changes in current cause large voltage
changes, the transimpedance can be quite large - e.g., 100M!}
for the AD846. As long as the amplifier's internal input impedance
is very low, errors in closed-loop circuitry depend principally on
the ratio, RplRn relative to unity - where Rp is the feedback
resistance and RT is the transimpedance. It will be recalled that,
in VN op amps, the increase in error depends mainly on Rpl(AR/),
Slewing Rate
The slewing rate of an amplifier, usually in volts per microsecond
(V/l1s), defines the maximum rate of change of output voltage
for a large input step change.
Unity-Gain Small-Signal Response
Unity-gain small-signal response is the frequency at which the
open-loop gain (or its projection on a Bode plot) falls to IVN,
or OdB under a specified compensation condition. For amplifiers
having 6 dB-per-octave rolloff, this frequency is also called
OPERA TlONAL AMPLIFIERS 2-13
•
unity-gain bandwidth; Jor such amplifiers, the gain-bandwidth
product is essentially constant. "Small signal" indicates that, in
general, it is not possible to obtain large output voltage swing at
high frequencies because of distortion due to slew-rate limiting
or signal rectification.
For amplifiers with symmetrical response for signals applied to
either input, the dynamic behavior will be consistent for both
inverting and noninverting configurations. However, if feedforward compensation is used, fast response will be available
only on the negative input, restricting fast applications of the
device to the inverting mode.
For amplifiers having 6 dB-per-octave rolloff, this frequency is
also called unity-gain bandwidth; for such amplifiers, the gambandwidth product is essentially constant.
Operational Amplifiers, Theory and Practice, by J.K. Roberge,
J. Wiley & Sons, 1975. Authoritative book on op amp
principles and circuitry: contains extensive material on
compensation to optimize dynamic performance
Transducer Interfacing Handbook, edited by D.H. Sheingold,
1980. $14.50. Analog Devices, Box 796, Norwood, MA 02062
ARTICLES AND APPLICATION NOTES (Available upon
request; ask for specific issue of Analog Dialogue)
"Amplifier Noise Basics Revisited," Analog Dialogue 18-1,
1984
"Analog Signal Handling for High Speed and Accuracy," by
A.P. Brokaw, Analog Dialogue 11-2
BOOKS (Not available from Analog Devices except where noted)
"An IC Amplifier User's Guide to Decoupling, Grounding, and
Making Things Go Right for a Change," by A.P. Brokaw,
Application Note
A Designer's Guide to: Innovative Linear Circuits, by Jim Williams,
Newton, MA, Cahners, 1985
"Applications of High-Performance BiFET Op Amps,:'
Application Note
Analog Signal Processing and Instrumentation, by Arie F. Arbel,
Cambridge (UK), Cambridge University Press, 1980
"Avoiding Passive-Component Pitfalls," Analog Dialogue 17-2,
1983
Bipolar and MOS Analog Integrated Circuit Design, by Alan B.
Greben, New York, Wiley-Interscience, 1984
"Current Inverter with Wide Dynamic Range," by Barrie
Gilbert, Analog Dialogue 9-1, 1975
Electronics with Digital and Analog Integrated Circuits, by
Richard J. Higgins, Englewood Cliffs, NJ, Prentice Hall,
Inc., 1983
"How to Select Operational Amplifiers," Application Note
IC Op-Amp Cookbook, by Walter Jung, Howard Sams & Co.,
Third Edition, 1986, down-to-earth and practical paperback
"Laser-Trimming on the Wafer, A Powerful New Tool for
ICs," by R. Wagner, Analog Dialogue 9-3, 1975
Nonlinear CircuItS Handbook, edited by D.H. Sheingold, 1976.
$5.95. Analog Devices, Box 796, Norwood, MA 02062
"Shielding and Guarding," by Alan Rich, Analog Dialogue
17-1, 1983
A BRIEF BIBLIOGRAPHY ON OP AMPS
Operational AmplifIer Circuits, Theory and Applications, by
E.J. Kennedy, New York, Holt, Rinehart and Winston,
Inc., 1988
OperatIOnal Amplifiers and Linear ICs, by R.F. Coughlin and
F.F. Driscoll, Prentice-Hall, Third Edition, 1987. Practical
textbook
2-14 OPERATIONAL AMPLIFIERS
"How to Test Operational Amplifier Param~ters," Application
Note
. "Simple Rules for Choosing Resistor Values in AdderSubtractor Circuits," by D. Sheingold, Analog Dialogue
10-1, 1976
"Understanding Interference-Type Noise," by Alan Rich,
Analog Dialogue 16-3, 1982
1IIIIIIII ANALOG
WDEVICES
FEATURES
High Output Current: 50mA @ ± 10V
Fast Settling to 0.1%: 130ns
High Slew Rate: 330V/Jis
High Gain-Bandwidth Product: 300MHz
High Unity Gain Bandwidth: 40MHz
Low Offset Voltage (1mV for AD380K. L. SI
Wideband, Fast-Settling
FET-Input Op Amp
AD380 I
AD380 FUNCTIONAL BLOCK DIAGRAM
TOP VIEW
PRODUCT DESCRIPTION
The AD380 is a hybrid operational amplifier that combines the
low input bias current advantages of a FET input stage with the
high slew rate and line driving capability of a fast, high power
output amplifier.
The AD380 has a slew rate of 330V/fLS and will output ± lOY at
± SOmA. A single external compensation capacitor allows the
user to optimize the bandwidth, slew rate, or settling time for
the given application.
A true differential input ensures equally superior performance
in all system designs whether they are inverting, noninverting,
or differential.
PRODUCT HIGHLIGHTS
1. The AD380's high output current (SOmA @ ± 10V) makes it
suitable for driving terminated 200n twisted pairs.
2. The fast settling output (250ns to 0.01%) makes the AD380
an ideal choice for video AID and DIA converters and sample
and hold applications.
3. The settling wave forms are not only fast but are also very
smooth. The absence of large overshoot and oscillations
makes the AD380 a very predictable and dependable system
element.
4. The high gain-bandwidth product (300MHz) ensures low
distortion in high frequency applications.
The AD380 is especially designed for use in applications, such
as fast AID, D/A and sampling circuits, that require fast and
smooth settling and FET input parameters.
5. Quick, symmetrical overdrive recovery time (250ns) is assured
by an internal antisaturation diode. This is useful in applications
where large transient signals may occur.
The AD380 is offered in three commercial versions, J, K and L
specified from 0 to + 70°C and one extended temperature version,
the S, specified from - 55°C to + 125°C. All grades are packaged
in hermetically sealed TO-8 style cans.
6. The precision input (ImV offset, max), along with fast settling
and high current output make the AD380 an excellent choice
for:
• ATE pin drivers
• precision coax buffers
• signal conditioning on pulse waveforms
• high resolution graphics displays.
OPERATIONAL AMPLIFIERS 2-15
SPECIFICATIONS (typical@ +25"C and Vs =
:!: 15V
dc unless otherwise specified)
MODEL
AD380JH
AD380KH
AD380LH
AD380SH
OPEN LOOP GAIN
VOtrr = ± IOV,noload
Votrr = ±IOV,RL "2000
40,000 min
25,000 min
•
•
•
•
•
•
OUTPUT CHARACTERISTICS
Voltage@RL =2000,TA =mintomax
Output Impedance (Open Loop)
Short Circuit Current
± 12V(± 10Vmin)
lOon
100mA
•
•
•
•
•
•
•
·
DYNAMIC RESPONSE
Unity Gain, Small Signal
Gain-Bandwidth Product, f = 100kHz, Cc = IpF
Full Power Response
Slew Rate, Cc = IpF, 20V Swing
Settling Time: IOV Step to 1%
IOVSteptoO.I%
IOV Step to 0.01 %
40MHz
300MHz (200MHz min)
6MHz
330V/.,.s (200V/.,.s min)
90ns
130ns
250ns
*
•
•
•
•
•
•
••
INPUT OFFSET VOLTAGE
vs. Temperature), TA = mmtomax
vs. Supply
2.0mVmax
50.,.VrCmax
ImVNmax
INPUT BIAS CURRENT
Either Input, Initial'
Input Offset Current
10pA(IOOpAmax)
SpA
INPUT IMPEDANCE
Differential
Common Mode
10"n116pF
lO"nl16pF
INPUT VOLTAGE RANGE
Differential'
CummonMode
Common Mode ReJection, V,N = ± IOV
±20V
± 12V(± 10Vmin)
60dBmin
POWER SUPPLY
Rated Performance
Operating
Quiescent Current
±ISV
±(6t020)V
12mA (ISmA max)
VOLTAGE NOISE
O.IHzto 100Hz
100Hz to 10kHz
10kHz to IMHz
3.3.,.V p-p(O.S.,.V rms)
6.6.,.Vp-p(l.,.Vrms)
40.,.V pop (6.,.V rms)
TEMPERATURE RANGE
Operating, Rated Performance
Stot&ge
Thermal Resistance 81A
8 1e
PACKAGE OPTION"
TO-8Style
Oto +70"C
-6S"Cto + ISO"C
IOO"CIW
70"C1W
H-I2A
NOTES
IInpur Offset Voltage Drift IS speaflCd WIth the offset voltage unnulled.
Nulhng will induce an addJtJonaJ 3tLVf'CImV of offset Dulled
2BIIS Current speaficanons are guaranteed maximum at either mput at
TeASE = +2Sac. For higher temperatures see Figure 16.
3Defmed as the maximum safe voltage berween inputs such that neither
exceeds ± IOV from ground.
2-16 OPERATIONAL AMPLIFIERS
•
•
•
•
*
•
250ns (400ns max)
1.0mVmax
20.,.VrCmax
•
·
·•
·•
*
*
•
•
*
*
•
•
·•
*
*
•
·
•
·•
··..
..
·•
lO.,.vrCmax
•
··
··•
·
'.•
·
··
·
*
*
*
•
4See Section 16 fOJ' package outline mformatlon
*Spe<:ificatlons same as AD380JH
*·SpecWcabons same as AD380KH.
Specifications subjcct to change Without DOuce.
*•
·
·•
SO.,.VfCmax
•
•
·•
*
•
•
·
*
•
•
-SS"Cto + 12S"C
·
*
*
•
Typical Characteristics
'"
'"
~
~
~
"pF
,
---
~~
'":s
~
",
\
Va'" ±15V
vc,," '"
.•
\2OpF
\
~
~
~\\
SpF\ \
\
''''
'"
\
.
Z
40
\
--"" ~ ~
~
.v,
~'\
Cc = lOpF
~
~
~ 1\ ', \ 20j
\
Vs-:t.15V
1V p P SINEWAVE
-v,
2Vp-p
~,
"\ ~I
~
-20
,
20
'00.
""
Figure 1. Open Loop Frequency
Response
,
''''
FREQUENCY _ HI
""
'"
I.
""
FREOUENCY - HI
Figure 2. CMRR vs. Frequency
Figure 3. PSRR vs. Frequency
>"r-----~-,~~----,---~,
t---
"R
Ceo _
= lpF
~
~
~15r_----++~~~+_~~+_~--1
'" ""'" ~
~
il0r---~~+---~-J~+_----1
I
6VIN =lV
"-
20
'~,------~------~------",
20
INPUT VOLTAGE-
Figure 5. Slew Rate vs.
Compensation Capacitor
,
001%
NO~AD
'I--"
/'
0025%
,~
/'
--
""
~ 5r---~++~r-++----+_----1
COMPENSATION CAPACITOR _ pF
Figure 4. Slew Rate vs.
Differential Input Voltage
/
o
01.
- ----
Your '" lOV
RF,R, '"
15kfl
I
..........
Rl = 200n
-.....
"'\
'\ \
i\
,
,
,
Figure 6. Output Settling Time vs.
Output Voltage Swing and Error
//
,
,
,
/v
NO LOAO/
/'
V
V
~=200n
/
I'
V
~V
,/
SUPPLVVOLTAGE_ ±V
CLOSED lOOP GAIN - V!V
Figure 7. Settling Time vs.
Closed Loop Gain
,
Figure 8. Gain vs. Temperature
Figure 9. Gain vs. Supply Voltage
,
.,
V
.....- / '
2
V
V
.
,
2
,
,:.--,
-
.
,
r-- ---..,
- -~
~,
--
.............
:--.....
\Is" :!:16V
--
llV'N "2mV
9
CASE TEMPERATURE - 'C
Figure 10. Supply Current vs.
Temperature
,
-50
o
26
CASE TEMPERATURE
Figure 11. Supply Current vs.
Supply Voltage
76
100
125
-"c
Figure 12. Iscvs. Temperature
OPERATIONAL AMPLIFIERS 2-17
'"",-
r--
"'"
~
"'" ~
~
AMBIE~
I
,
50
'oo
75
TEMPERATURE _
°c
1\
,
,
\
-
6
- COMMON MODE VOLTAGE _
5 4
2
.
J
,
0
SUPPLY VOlTAGE_ ±V
V
Figure 15. Input Bias Current vs.
Supply Voltage
Figure 14. Input Bias Current vs.
Common Mode Voltage
Figure 13. Power Dissipation
vi;. Temperature
II
25"C
r\
,
~
,,~/
1\
,
,
.
/
,
,
L l!.:.
,
. . . . i'..
/X
,
~
,
,
/
,
/ /
V/
5
,
-,
,
- 50
CASE TEMPERATURE _ "C
SUPPlVVOLTAGE_
.
-v
Figure 18. Input Voltage Range vs.
Supply Voltage
Figure 17. Offset Voltage vs.
Temperature
Figure 16. Input Bias Current
vs. Temperature
.
5
.
/
,
,
CMRR"60d8
/""
/
/
/
/
\
,
,
~ 10f------f-------:f-f------1
§
Vs=±15V
RL =2oon
RL "'20011
.
10
15
SUPPLY VOLTAGe - ±y
Figure 19. Output Voltage Swing vs.
Supply Voltage
,
,
,
I~
.\
i
,
,
\
'OOM
Figure 21. Large Signal Frequency
Response
Figure 20. Output Voltage Swing vs.
Load Resistance
,
I.
'M
FREQUENCY _ Hz
\.
\
Rf "'5k
,
,
'\
"'~
,
'""'""-
10
20
OPEN lOOP GAIN - VN
-
Figure 22. Recommended Compensation
Capacitor vs. Closed Loop Gain
2-18 OPERATIONAL AMPLIFIERS
,
\
\.
r---....
10k
lOOk
1M
10M
100M
FReQUENCY _ Hz
Figure 23. Input Noise Voltage
Spectral Density
Si~jjiV
tIN
-=
...
v,"
+1VJLf
-IV
l1
!l'
WI
.;
(
!
IJ !
'J
::;;
.......
I]!i
n!
. .... ..
~
SV
~
Figure 24b. Overdrive Recovery
Response (Symmetrial 20ns
Version Available)
Figure 24a. Overdrive Recovery
Test Circuit
:11
II.
,J
Figure 25a. Unity Gain Inverter
Settling Time Test Circuit
~
I,
.-t- [:::I ,
D
l
.. .""-'
I
0
1-
...
,..1
....
l1'
1:.4 I~ ,
Figure 25b. Unity Gain Inverter
Large Signal Response
Figure 25c. Unity Gain Inverter
Small Signal Response
Figure 26b. Unity Gain Buffer
Large Signal Response
Figure 26c. Unity Gain Small
Signal Response
+Vs'
VOUT
~
Figure 26a. Unity Gain Buffer Circuit
APPLICATIONS INFORMATION
Compensation Capacitor
For low gain applications a 5pF to 27pF capacitor between the
frequency compensation input (pin 11) and the output (pin 9)
will reduce the risk of oscillation by adding phase margin. A
compensation capacitor is especially needed when driving capacitive loads. For gains greater than 30 a IpF compensation capacitor
is recommended; see Figure 22.
For unity gain buffer applications it may be necessary to add a
small (I OpF to 20pF) capacitor between pins 8 and 10 for improved
phase margin; see Figure 26a.
Offset Null
If the initial offset voltage is not low enough for the user's application offset nulling is required. To null the offset tie a 20kO
potentiometer between the offset null pins (pins 2 and 8). The
wiper of the potentiometer is tied to the positive supply. With
the analog input signal to the circuit grounded, adjust the
potentiometer for zero output.
To minimize the effects of offset voltage drift as a function of
temperature, null the offset at the midpoint of the operating
temperature range. For example, if the operating environment is
O°C to 700C do the offset nulling at 35°C. This will insure a
maximum offset voltage drift of 35 times the Vas drift specification
at either temperature extreme.
OPERATIONAL AMPLIFIERS 2-19
Typical Circuits
AD578
DIGITAL
OUTPUTS
12·B11
AID
DIGITAL
INPUTS
INPUT
DATA
LATCH
l00pF
AD7545
·Optlonal Dtfferent18llnpUt Components Used to ReJect
NoISe Between Input Ground and the AID Anaklg Ground
Figure 27. Fast-Settling Buffer
Its quick recovery from load variatioos makes the AD380 an
excellent buffer for fast successive approximation ND
converters; see Figure 27.
Many high speed ND converters require a wideband buffer that
can hold a constant output voltage under dynamically-changing
load conditions that fluctuate at the bit decision rate.
Figure 29. CMOS DAC Output Amplifier
CMOS DAC output amplifiers require low offset voltage op
amps. The output impedance of CMOS DACs varies with input
code. This can cause a code dependent error term at the output
that approaches the op amps' offset voltage. If the DAC has a
differential nonlinearity of 1/2LSB, it will require an output
amplifier with less than 1I2LSB offset error to remain monotonic.
An LSB for a l2-bit DAC such as the AD7545 is 2.44mV (10
volts full scalel4096). Thus, the AD380KH, with only ImV
offset maximum, will contribute less than 1I2LSB to differential
linearity error.
ADIi66A
DIA
RF
Figure 28. 12-Bit Voltage Output DAC Circuit Settles to
112LSB in 300ns
The AD565A 12-bit digital to analog converter with an AD380
output amplifier will give a voltage output that typically settles
to within 1I2LSB in less than 300ns. Total settling time is the
root mean square of the DAC current output settling time and
the output amplifier settling time.
2-20 OPERATIONAL AMPLIFIERS
YOUT
3.45kO
ll1pF
R,
500
Figure 30. Video Amplifier
The high output current capability of the AD380 makes it suitable
for video speed driver applications. In the circuit above the
, closed loop gain of 70 (37dB) is available over a bandwidth of
5MHz. Note that a IpF compensation capacitor is required in
this high gain application.
r-IIANALOG
WDEVICES
FEATURES
High Slew Rate 30V/p.s
Fast Settling to 0.1%: 700ns
High Output Current: 50mA for AD382
(10mA for AD381)
Low Drift (5f1.VI"C-L Grades)
Low Offset Voltage (250fl.V-L Grades)
Low Input Bias Currents
Low Noise (2f1.V pop)
High Speed, Low Drift
FET Operational Amplifiers
AD381 /AD382 I
AD381 PIN CONFIGURATION
TAB
v-
'1 !L
OFfSET
(1)
OFFSET
*
4
v-
*KEEPTHIS LEAD AS SHORT AS POSSIBLE
TOPV1EIIoI
PRODUCT DESCRIPTION
The AD381/AD382 are hybrid operational amplifiers combining
the very low input bias current advantages of a FET input stage
with high slew rate and line driving capability of a high power
output stage.
AD382 PIN CONFIGURATION
The ofThet voltage (0.2SmV maximum for the L grades) and
offset voltage drift (SiloVI"C maximum for the L grades) are
exceptipnally low for high speed operational amplifiers.
In addition to superior low drift performance, the AD381 and
AD382 offer the lowest guaranteed input bias currents of any
wideband PET amplifier with l00pA max for-the J grades of
each and SOpA max for the AD382 K, L and S grades. Since
Analog Devices, unlike most other manufacturers, specifies
input bias current with the amplifiers warmed-up, our FET
amplifiers are specified under actual operating conditions.
OFFSET
NULL
OFFseT
NULL
~
~v-
*KEEPTHIS LEAD AS SHORT AS POSSIBLE
TOP VIEW
The AD381 and AD382 are especially designed for use in applications, such as precision high speed data acquisition systems
and signal Conditioning circuits, that require excellent input
parameters and a fast, high power output.
3. Internal frequency compensation, low offset voltage, and full
device protection eliminate the need for external components
and adjustments. This reduces circuit size and complexity
and increases reliability.
The AD381 and AD382 are offered in three commercial versions,
J, K and L specified from 0 to + 70"C, and one extended temperature version, the S specified from - SS"C to + 12S"C. All
grades are packaged in hermetically sealed metal cans.
4. The fast settling output (700ns to 0.1%) makes the AD381
and AD382 ideal for D/A and AID converter amplifier
applications.
PRODUCT HIGHLIGHTS
I. Laser trimming techniques reduce offset voltage drift to
SIIoVI"C max and reduce offset voltage to only 2S0IloV max on
the L grade versions.
2. Analog Devices FET processing provides lOOpA max (2OpA
typical) bias currents specified after 5 minutes of warm-up.
5. The AD382's high output current (SOmA minimum at ± 10
volts) makes it suitable for driving terminated (2000) twisted
pair cables over the commercial temperature ranges.
6. The high slew rate (30V/IIoS) and high gain bandwidth product
(SMHz) make the AD381 and AD382 an ideal choice for
sample and holds and for high speed integrator circuits.
OPERA TIONAL AMPLIFIERS 2-21
•
SPECIFICATIONS
Model
OPEN LOOP GAIN
Vour = =!' IOV,RLi>2kO(AD38I)
Vour = ± 10V, RL = 200fl (AD381)
RL = 101d}(AD381)
OUTPUT CHARACTERISTICS (AD381)
Voitage@RL = ZOOO
Voltage@RL = 101d}
Shon Circuit Current, Continuous
OUTPUT CHARACTERISTICS (AD381)
Voltage@RL = lkO, TA = min to max
Voitage@RL =2Idl,TA = min to max
Voitage@RL = 101d}, TA = mintotD8lt
Shan Circuit Current, Continuous
DYNAMIC RESPONSE
Unity Gain, Small Signal
Full Power Response
Slew Rate, Unity Gain
Settling Time: 10VSteptoO.I%
10VSteptoO.0l%
INPUT OFFSET VOLTAGE
VB, Temperature, TA = minlomax3
v•• Supply
INPUT BIAS CURRENr
Either Input (AD381)
Eithet Input (AD382)
Input ()ffi;et COmot
INPUT IMPEDANCE
Differential
Common Mode
(!Pal @ +m: and Ys
=
±
15Y de unless oIherwise specified)
AD38IJH
AD38lJH
AD381KH
AD38lKH
AD381LH
AD38lLH
AD381SH
AD381SH
60,000 min
25,000 min
100,000 min
lOO,OOOmin
35,000 min
lSO,OOOmin
••
••
..••..
±12V(±IOVmin)
±13V(±12Vmin)
SOmA
Note I
•
± 12V(± 10Vmin)
±12V(±IOVmin)
± i3V(± 12Vmin)
20mA
Note 2
•
5MBz
500kHz
3OV/".. (20V/".. min)
700ns
1.2"..
I.OmVtD8lt
IS,.Vf'Cmax
200,.VNmax
20pA (I00pA max)
20pA (IOOpA max)
SpA
•
1.2".. (2.0,.. tD8lt)
O.SmV~
10,.Vf'C tD8lt
lOO,.VNmax
•
•
..
••
0.2SmVmax
S,.Vf'Cmax
••
10pA(50pAmax)
..
..
10,.Vf'Cmax
z
10120117pF
10120117pF
INPUT VOLTAGE RANGE
DifferentialS
±20V
CommnnMode
± 12V (± 10V min)
Common-Mode Rejection, VIN = ± 10V
76dBmin
80dBmin
POWER SUPPLY
Rated Performance
±15V
±(StoI8jV
Operstins
Quiescent Cumnt AD382
3.4mA(6mAmax)
3.2mA(SmAmax)
AD381
VOLTAGE NOISE
O.IHz-IOHz
2,.Vp-p
10Hz
35nVlv'Hi
100Hz
22nViv'Hi
1kHz
18nViv'Hi
10kHz
16nViv'Hi
TEMPERATURE RANGE"
Oto +70'C
- SS'C to + 12S'C
Operatins, Rated Performance
-6S'Cto + lSO'C
Storase
ThennalResUtanc:e-6JA(AD382)
lOO'CIW
ThetmaiResistance-6JC(AD382)
70'C1W
NOTES
"BwCurrent spccafic:abOD8 are guuu.t=d. maximum _teither input
'TheAD382SH hu an output voI.... cI" ± 12V(± IOVmin)for
after Sminutesofopcrarionat TA "" + 2SOC. For tuperlempentutes J
•
••
•
•
•
•
•
•
•
a 2000 load. fromT... to + lOO"C. To + 12SOCdlcoutput
CUIl'CDt1S3SmA.
'TheAD3BISHhuonoutputvol.... cI" ± 12V(± IOVmin)foraUtll
JoadfromT_to +1O"C. From + 1O"Cto + 12S"CtheoutpUtc:urrent
il7m.\.
'lnputOft"aot Vol.... Dnftilspecificd with tbeoffaet .01.... unnulled.
Nulliogwill indu
100
1
Figure 13b. Voltage Gain vs.
Load Resistance for AD382
12
\
0
10k
LOAD RESISTANce - Ohms
Figure 13a. Voltage Gain vs.
Load Resistance for AD381
0
~
20
LOAD RESISTANCE - Ohm5
20
Figure 12. Open Loop Voltage Gain
vs. Supply Voltage
~40
10k
15
10
SUPPLY VOLTAGE - t.V
o
5k
A.382_
70
~80
2k
AD312-
~
"g
Figure 11b. Open Loop Gain vs.
Temperature for AD382
110
70 1k
AD3I1
..........
120.--,-----,.--,--,.----,
801--+---+--1--+-----1
an
/"" r--
~
!:; 80
i'-.
CASE TEMPERATURE _
V~
,
100
I
,.
°c
Figure lla. Open Loop Gain vs.
Temperature for AD381
-
110
.50
~
20
AL = 200n
Vs::: ±15V
~
~
{AD382j
L 10
i2
'\
~
0
10k
T
lOOk
1M
FREQUENCY - Hz
0
RL =2kO
~
10M
Figure 18. Large Signal Frequency
Response
2-24 OPERA TIONAL AMPLIFIERS
0
~
'" --
0
i
0
~
.........
~
0
>
~-5
~
0
0
10
5
~
-10
100
lk
10k
lOOk
1M
0
02
FREQUENCY - Hz
Figure 19. Noise vs. Frequency
Figure 20a. AD381 Output Settling Time
vs. Output Voltage Swing and
Error (Circuit of Figure 22a)
Typical Characteristics
VOUT '"10V
>''------+--oVo"'
°O~--~5---+'1O~--'±5--~~'
CL.OSED LOOP GAIN -
Figure 20b. A0382 Settling Time vs.
Output Swing and Error (Circuit of
Figure 23a)
-v,
VN
Figure 21. Settling Time vs. Closed
Loop Gain (Circuits of Figures
22a & 23a)
Figure 22. A0381 Unity Gain Inverter
Settling Time Test Circuit
OPERA TlONAL AMPLIFIERS 2-25
2-26 OPERA TIONAL AMPLIFIERS
r'III ANALOG
WDEVICES
Ie, Wideband, Fast Slewing
General Purpose Operational Amplifier
AD507 I
FEATURES
Gain Bandwidth: 100MHz
Slew Rate: 20VIPfJ min
IB: 15nA max (AD507K)
Vas: 3mV max (AD507K)
VasDrift: 151lVtC max (AD507K)
High Capacitive Drive
PRODUCT DESCRIPTION
The Analog Devices ADS07} , K and S are low cost monolithic
operational amplifiers that are designed for general purpose
applications where high gain bandwidth and high speed are
significant requirements. The devices also provide excellent dc
performance with low input offset voltage, low offset voltage
drift and low bias current. The ADS07 is a low cost, high
performance alternative to a wide variety of modular and IC
op amps; a brief review of the specifications confirms its outstanding price/performance characteristics.
The ADS07 is recommended for use where low cost and all
around performance, especially at high frequencies, are
needed. It is particularly well suited as a fast, high impedance
comparator, integrator or wideband amplifier and in sample/
hold circuits. It is unconditionally stable for all closed loop
gains above 10 without external compensation; the frequency
compensation terminal is used for stability at lower closed
loop gains. The circuit is short circuit protected and offset
voltage nullable. The ADS07} and K are specified over the
o to +70 oC temperature range, the ADS07S over the extended,
temperature range, -SSoC to +12SoC. All devices are
packaged in the hermetic T0-99 metal can.
PRODUCT HIGHLIGHTS
1. Excellent dc and ac performance combined with low cost.
2. The ADS07 will drive several hundred pF of output capacitance without oscillation.
3. All guaranteed dc parameters, including offset voltage drift,
are 100% tested.
ADS07 PIN CONFIGURATION
FREQUENCY
COMPENSATION
INVERTING
INPUT
VMIL·STANDARD-883
The ADS07S/883 has the same electrical specifications as the
ADS07S, but is subjected to the 100% screening requirements
specified in MIL-STD-883, Method S004, Class B.
This procedure includes:
1. Pre-Cap Visual Inspection: Method 2010, Condition B.
2. Stabilization Bake: Method 1008, Condition C, 24 hours @
+lS0oC.
3. Temperature Cycle: Method 1010, Condition C, -6SoC to
+lS0oC, 10 cycles.
4. Centrifuge: Method 2001, Condition E, 30,000 g, Y 1
orientation.
S. Hermeticity, Gross Leak: Method 1014, Condition C,
steps 1 and 2.
6. Hermeticity, Fine Leak: Method 1014, Condition A,
5 x 10-8 atm/cc/sec.
7. Burn-In: Method 1015, 160 hours@ +12SoC.
8. Final Electrical Test.
9. External Visual: Method 2009.
4. To insure compliance with gain bandwidth and slew rate
specifications, all devices are tested for ac performance
characteristics.
5. To take full advantage of the inherent high reliability of
. IC's, every ADS07S receives a 24 hour stabilization bake
at +lS0oC.
OPERA T10NAL AMPLIFIERS 2-27
SPECIFICATIONS
(typical at +25°C and ±15V dc, unless otherwise noted)
PARAMETER
OPEN LOOP GAIN
RL = 2kn, CL = SOpF
@TmintoTmax
ADS07J
AD507K
AD507S(AD507S/883 )00
80,000 min (150,000 typ)
70,000 min
100,000 min (1S0,OOO typ)
8S,OOOmin
100,000 min (1S0,OOO typ)
70,000 min
OUTPUf CHARACTERISTICS
Voltage@ RL = 2kn, CL = 50pF, Tmin to Tmax
Current@Vo =±10V
Short Clfcuit Current
±10V min (±12V typ)
±10mA min (±20mA typ)
2SmA
FREQUENCY RESPONSE
Unity Gain, Small Signal
@A= 1 (open loop)
@A = 100 (closed loop)
Full Power Response
Slew Rate
Settling Time (to 0.1 %)
3SMHz
1MHz
320kHz mID (600kHz typ)
±20V/p.s min (±3SV/p.s typ)
900ns
INPUf OFFSET VOLTAGE
IDltial
Avg vs Temp. Tmm to Tmax
vs Supply, Tmin to Tmax
INPUf BIAS CURRENT
Initial
Tmin to Tmax
INPUf OFFSET CURRENT
Initial
Tmin to Tmax
Avg vs Temp, Tmin to Tmax
400kHz min (600kHz typ)
±2SV/p.smin (±3SV/p.s typ)
400kHz min (600kHz typ)
20V/p.s min (±3SV/p.s typ)
S.OmV max (3.0mV typ)
lSp.Vi"C
200p.VNmax
3.0mV max (l.SmV typ)
lSp.VtC max (Sp.vtc typ)
100p.VNmax
4mV max (O.SmV tyf)
20p.VtC max (Sp.VI C typ)
100p.V/Vmax
2SnA max
40nAmax
lSnAmax
2SnA max
lSnAmax
3SnA max
2SnA max
40nAmax
O.SnAtC
lSnAmax
2SnAmax
0.2nAi"C
lSnAmax
3SnAmax
0.2nAi"C
INPUf IMPEDANCE
Differential
Common Mode
40Mn min (300Mn typ)
1000Mn
INPUf VOLTAGE NOISE
f= 10Hz
f= 100Hz
f= 100kHz
lOOn V Iy'iii
30nV/y'iii
12nV/y'iii
INPUf VOLTAGE RANGE
Differential, Max Safe
Common Mode Voltage Range, Tmm to Tmax
Common Mode RejectIOn @±SV, Tmm to Tmax
±12.0V
±ll.OV
74dB min (100dB typ)
POWER SUPPLY
Rated Performance
Operating
Current, Quiescent
±lSV
±(S to 20)V
4.0mA max (3.0mA typ)
TEMPERATURE RANGE
Rated Performance
Operanng
Storage
PACKAGE OPTION'
H'()SA
±10V min (±12V typ)
±lSmA min (±22mA typ)
2SmA
.
6SMn min (SOOMn typ)
SOdB mID (lOOdB typ)
o to +70·C
-ss·C to +12S·C
-2S·C to +SS·C
-6S·C to +lSO·C
-6S·C to +lS0·C
ADS07KH
ADS07JH
ADS!l?SH
NOTES
1 See Section 16 for package oudioe information.
·Speclfu::ations same u AD507J .
•• AD507S/88 3 minimum order 10 pieces.
Specifications SUbject to change without notice.
~
INPUT
v
OV
.... ---------
+6V - - - - .... - - - -
OUTPUT
. .""'"
~
.... .
'
lIOn
~I
I
IN
,.,. ____ ____ ~_:L
ov
-
I t-AT...JSlEW RATE
I
I
I.VI.T
Slew Rate Definition and Test Circuit
2-28 OPERATIONAL AMPLIFIERS
SOdB mID (100dB typ)
1.0
"'"
'
Applying the AD507
APPLICATION CONSIDERATIONS
The ADS07 combines excellent dc characteristics and dynamic
performance with ease of application. Because it is a wideband,
high speed amplifier, care should be exercised in its stabilization. Several practical stabilization techniques are suggested to
insure proper operation and minimize user experimentation.
GENERAL PURPOSE WIDEBAND COMPENSATION
The following considerations are intended to provide guidance
in critical wideband applications. While not necessary in all
cases, the considerations are of prime importance for the user
attempting to obtain the highest performance from his circuit
design.
High Gain Conditions
The ADS07 is fully compensated internally for all closed loop
gains above 10; however, it is necessary to load the amplifier
. with SOpF. In many applications this minimum capacitive load
will be provided by. the load or by a cable at the output of the
ADS07, making an additional SOpF unnecessary. Figure 1
shows the suggested configuration for general purpose usc for
closed loop gains above 10.
The O.lJ.1F ceramic power supply bypass capacitors are considerably more important for the ADS07 than for low frequency
general purpose amplifiers. Their main purpose is. to convert
the distributed high frequency ground to a lumped single point
(the V+ point). The V+ to V- O.lJ.1F capacitor equal~es the
supply grounds while the O.lJ.1F capacitor from V+ to signal
ground should be returned to signal common. The signal
common, which is bypassed to pin 7, is defined as that point
at which the input signal source, the feedback network, and
the return side of the load are joined to the power common.
Note that the diagrams show each individual capacitor
directly connected to the appropriate terminal (pin 7 [V+J
and pin 6 [Output)). In addition, it is suggested that all
connections be made short and direct, and as physically close
to the can as possible, so that the length of any conducting
path shared by external components will be minimized.
.....,..~-.,..vOUT1'lJT
01"F
(CERAMIC DISCI
OFFSET
NULL
100kn
~
5
OFFSET NULL
-NOT REQUIRED fOR LOAD OR
CABLE CAPACITANCE >SOpF
2kn
7 +V
Figure 1. General Purpose Configuration to Closed Loop
Gain> 10
Low Gain Conditions
For low closed loop gain applications, the ADS07 should be
compensated with a 20pF capacitor from pin 8 (frequency
compensation) to signal common or pin 7 (V+). This configuration also requires a 30pF feedback capacitor from pin 6
(Output) to pin 8 (see Figure 2). The SOpF minimum load
capacitance recommended for uncompensated applications is
not required when the ADS07 is used in the compensated
mode. This compensation results in a unity gain frequency of
approximately 10 to 12MHz.
The excellent input characterisitcs of the AD507 make it
useful in low frequency applications where both dc and ac
performance superior to the 741 type of op amp is desired.
Some experimentation may be necessary to optimize the
AD507 for the specific requirement. The unity gain bandwidth
can be reduced by increasing the value of the compensation
capacitor in inverse proportion to the desired bandwidth
reduction. It is advisable to increase the feedback capacitor at
the same time, maintaining its value about 50% larger than the
compensation capacitor. Because the AD507 is fundamentally
a wideband amplifier, careful power supply decoupling and
compensation component layout are required even in low
bandwidth applications.
OFFSET VOLTAGE NULLING
Note that the offset voltage null circuit includes a 2kn resistor
in series with the wiper arm of the 100kn potentiometer.
This resistor is not absolutely required, but its use can prevent
a condition of false null that can be obtained at the ends of
the pot range. The knowledgeable user should have no trouble
differentiating between nulling in the pot mid-range and
erratic end-range behavior when the wiper is connected
directly to V+.
01,.F
Figure 2. Configuration for Unity Gain Applications
HIGH CAPACITIVE LQADING
Like all wideband amplifiers, the ADS07 is sensitive to capacitive loading. Unlike many, however, the AD507 can be
used to effectively drive reasonable capacitive loads in virtually
all applications, and capacitive loads of several hundred picofarads in a number of specific configurations.
In an inverting gain of ten configuration, the internally compensated amplifier will drive more than 200pF in addition to
the recommended 50pF load, or a total of over 250pF. Under
such conditions, the slew rate will be only slighdy reduced,
and the overall setding time somewhat lengthened.
In general, the capacitive drive capability of the AD507 will
increase in high gain confIgUrations which reduce closed loop
bandwidth.
In any wideband application, it is essential to return the load
currents supplied by the amplifier to the power supply without sharing a path with input or feedback signals. This consideration becomes particularly important when driving capacitive loads which may resonate with short lengths of interconnecting wire.
FAST SETTLING TIME
A small capacitor (CS in Figure 3) will improve the setding
time of the AD507, when it is used with large feedback
resistors. The AD507 input capacitance (typically 2 or 3pF),
together with additional circuit capacitance, will introduce an
unwanted pole of open-loop response. The extra phase shift
introduced, for example, by 4pF of input capacitance, and
OPERATIONAL AMPLIFIERS 2-29
SkO inp.ut source impedance, will result in an underdamped
transient response, and long settling time. A small (1.5 to
3.0pF) feedback capacitor will introduce a zero in the openloop transfer function, reducing the phase shift and increasing
the damping, which will more than compensate for the slight
reduction in closed-loop bandwidth.
120
Open Loop VoItagB Gain
VB Tempsratura
VS-±20V
110
V,-±16V
~ov
100 ~=±5V
-
BIAS COMPENSATION NOT REQUIRED
Circuit applications using conventional oj! amps generally
require that the source resistances be matched at the inputs to
cancel the effects of the input currents and take advantage of
low offset current. In circuits similar to that shown in
Figure 3, the compensation resistance would be equal to the
parallel combination of RI and RF, and for large values
would require a bypass capacitor. The ADS07 is specially
designed to cancel the input currents so as to reduce them to
the offset current level. As a result, optimum performance
can be obtained even though no bias compensation is used,
and the non-inverting input can be connecred direcdy to the
signal common.
90
+26
+60
TEMPERATURE -"C
+76
20
~
I
./
~ 15
Common Mode Voltage Range
VB Supply Voltage
~
i
10
i . /'
8
,,/
/
V
TA"O TO 70 0 e
I
10
~
......
o
16
SUPPLY VOLTAGE - Volts
20
10
I
co
2
~
'"
~
g
"~
1.0
Output Voltage Swing
VB Frequency
01
0.01
10k
10M
1M
FREQUENCY - Hz
'.0
100M
3.0
Power Supply Current
VB Temperature
CONBIDERATIONSOF FIGURE 1 APPLV EXCEPT fOR
THE LOAD CAPACITOR
r--- 6
~
-
r--
f-
1I
Va'"' tl0V
2.0
rr:
rr:
i:l
Figure 3. Falft Settling Time Configuration
10
Vs·:t6V
+25
+60
TEMPERATURE -"C
TYPICAL PERFORMANCE CURVES
+7'
+1'
Broadband Input
Noise Characterilftics
+10
Input Bias Current and Offset
Current VB Temperature
- - <::rOFFSET CURRENT"",
......
REN1
UPPER FREQUENCY - 3da - Hz
!8
120
I 100
-10
-I' o
2
+26
+50
TEMPERATURE -"C
+7'
Open Loop Gain
VB Frequency
1000
,.
800
'"2
600
Input Impedance :iI
I
VB Temperature
..
u
r--.....
I ...
'"
"-...
~
+25
+50
TEMPERATURE _ DC
+75
\Is at16V
1. = 26°C-
... ~
80
'~
::-..,CC=OpF -
90
~
,,~
40
g
§
200
2-30 OPERATIONAL AMPLIFIERS
g
ri
20
-20
10
*
I
100
1k
F
-
~
I
10k 100k 1M
FREQUENCY - Hz
10M
1IIIIIIII ANALOG
WDEVICES
High Speed,
Fast Settling Ie Op Amp
AD509j
FEATURES
Fast Settling Time
0.1% in 500ns max
0.01% in 2.5j.1S max
High Slew Rate: 100V/j.IS min
Low 101 : 25nA max
Guaranteed VOl Drift: 30p.vfc max
High CMRR: BOdB min
Drives 500pF
Low Price
APPLICATIONS
DIA and AID Conversion
Wideband Amplifiers
Multiplexers
Pulse Amplifiers
PRODUCT DESCRIPTION
The ADS09J, ADS09K and ADS09S are monolithic
operational amplifiers specifically designed for applications
requiring fast settling times to high accuracy. Other comparable dynamic parameters include a small signal bandwidth of
20MHz, slew rate of 100VI/ls min and a full power response
of lS0kHz min. The devices are internally compensated for
all closed loop gains greater than 3, and are compensated with
a single capacitor for lower gains.
The input characteristics of the ADS09 are consistent with
0.01 % accuracy over limited temperature ranges; offset current
is 2SnA max, offset voltage is 8mV max, nullable to zero, and
offset voltage drift is limited to 30/lV/C max. PSRR and
CMRR are typically 9OdB.
The ADS09 is designed for use with high speed D/A or AID
converters where the minimum conversion time is limited by
the amplifier settling time. If 0.01 % accuracy of conversion
is required, a conversion cannot be made in a shorter period
than the time required for the amplifier to settle to within
0.01 % of its final value.
AD509 PIN CONFIGURATIONS
T0-99
FREQUENCY
COMPENSATION
INVERTING
INPUT
~
!..
T !.
V+
TOP VIEW
PRODUCT HIGHLIGHTS
1. The ADS09 is internally compensated for all closed loop
gains above 3, and compensated with a single capacitor for
lower gains thus eliminating the elaborate stabilizing techniques required by other high speed IC op amps.
2. The ADS09 will drive capacitive loads of SOOpF without
deterioration in settling time. Larger capacitive loads
can be driven by tailoring the compensation to minimize
settling time.
3. Common Mode Rejection, Gain and Noise are compatible
with a 0.01 % accuracy device.
4. The ADS09K and ADS09S are 100% tested for minimum
slew rate and guaranteed to settle to 0.01 % of its final
value in less than 2. S/ls.
All devices are supplied in the TO-99 package. The ADS09J
and ADS09K are specified for 0 to +70o C temperature range;
the ADS09S for operation from -SSoC to +12SoC.
OPERA TlONAL AMPLIFIERS 2-31
SPECIFICATIONS
Model
(@
+ 25"1: and Vs =
Min
AD509J
Typ
± 15V de unless otherwise specified)
Max
Min
AD509K
Typ
Max
Min
AD509S
Typ
Ma.
Units
OPEN LOOP GAIN
Vo ~ '" IOV, RI '" 2kll
TmmtoTm..",RI = 2kH
OUTPUT CHARACTERISTICS
Voitage(a Rr = 2kn. TmmtoTm""
FREQUENCY RESPONSE
Umty Gam Small Signal
Full Power Response
Slew Rate, Unity Gam
SettbngTlme
toO.l%
toO.01 %
7,500
5,000
15,000
10,000
7,500
15,000
10,000
7,500
15,000
VIV
VIV
±10
'" 12
±IO
'" 12
'" 10
'" 12
V
I 2
SO
20
1.6
120
1.5
SO
20
20
120
I 5
100
20
2.0
120
MHz
MHz
V/jJ.s
200
10
INPUT OFFSET VOLTAGE
ImtialOffset
5
Input Offset Voltage T mm to T max
200
1.0
10
14
4
8
II
200
10
500
2.5
ms
jJ.S
4
8
11
mV
mV
100
jJ.VIV
Input Offset Voltage vs. Supply,
125
250
500
100
200
400
100
200
400
nA
nA
20
50
100
10
25
50
10
25
50
nA
nA
TmlntoTmax
INPUT OFFSET CURRENT
InitIal
TA=mmtomax
INPUT IMPEDANCE
DIfferential
INPUT VOLTAGE RANGE
DIfferentIal
Common Mode
Common Mode Rejection
40
100
74
'" 15
=10
90
INPUT NOISE VOLTAGE
f~ 10Hz
f ~ 100Hz
f ~ 100kHz
POWER SUPPLY
Rated Performance
OperatIng
Quiescent Current
TEMPERATURE RANGE
Operating, Rated Performance
Storage
100
200
TmmtoTma"
INPUT BIAS CURRENT
Imtial
50
80
PACKAGE OPTION I
TO-99 Style (H-OSA)
90
",5
6
+70
+ ISO
ADS09JH
NOTES
ISee Section 16 for package outhne mformatlOn
Specifications subject to change WIthout noUce.
Specmc3tions shown In boldface are tested on all production umts at final
electncal test. Results from those tests are used to calculate outgomg quahty
levels. All min and max specIfications are guaranteed, although only those
shown in boldface are tested on all production umts.
2-32 OPERATIONAL AMPLIFIERS
Mil
80
'" IS
=10
90
V
V
dB
100
30
19
nV/\
nV/\
nV/\
=20
4
0
-65
",5
6
+70
+ 150
ADS09KH
6
V
V
rnA
+70
+ ISO
°C
°C
= IS
'" 15
",20
0
-65
100
100
30
19
=15
4
50
'" IS
=10
100
30
19
",5
100
=20
4
-55
-65
ADS09SH
HZ
HZ
HZ
Applying the AD509
APPLYING THE ADS09
MEASURING SETTLING TIME. Settling time is defined as
that period required for an amplifier output to swing from
o volts to full scale, usually 10 volts, and to settle to within
a specified percentage of the final output voltage. For high
accuracy systems, the accuracy requirement is normally
specified as either 0.1 % (10-bit accuracy) or 0.01% (12-bit
accuracy) of the 10 volt output level. The settling time
period is comprised of an initial propagation delay, an
additional time for the amplifier to slew to the vicinity of
10 volts, and a final time period to recover from internal
saturation and other effects, and settle within the specified
error band. Because settling time depends on both linear
and nonlinear factors, there is no simple approach to
predicting its final value to different levels of accuracy. In
particular, extremely high slew rates do not assure a rapid
settling time, since this is only one of many factors affecting
settling time. In most high speed amplifiers, after the
amplifier has slewed to the vicinity of the fmal output
voltage, it must recover from internal saturation and then
allow any overshoot and ringing to damp out. These
definitions are illuStrated in Figure 1.
-
RECOVERY LINEAR SETTLING
-SETTLING TIME TO.f.t.E-1
OR
.f.~
display. The resultant waveform of (Fo - EIN) of a typical
ADS09 is shown in Figure 3. Note that the waveform crosses
the 1mV point representing 0.01 % accuracy in approximately
l.SfJS. The top trace represents the output signal; the bottom
trace represents the error signal.
OUTPUT
1/
-'.;;.:f-
1.0
t
ERROR
SIGNAL
m
1- .. I-
Figure 3. Settling Time of AD509
SETTLING TIME VS. Rf AND Ri. Settling time of an
amplifier is a function of the feedback and input resistors,
since they interact with the input capacitance of the amplifier.
When operating in the non-inverting mode, the source
impedance should be kept relatively low; e.g., Skn; in order
to insure optimum performance. The small feedback
capacitor (SpF) is used in the settling time test circuit in
parallel with the feedback resistor to reduce ringing. This
capacitor partially cancels the pole formed in the loop gain
response as a result of the feedback and input resistors, and
the input capacitance.
SETTLING TIME VS. CAPACITIVE LOAD. The ADS09
will drive capacitive loads of SOOpF without appreciable
deterioration in settling time. Larger capacitive loads can be
driven by tailoring the compensation to minimize settling
time. Figure 4 shows the settling time of a typical ADS09,
compensated for unity gain with a lSpF capacitor, with a
SOOpF capacitive load on the output. Note that settling time
to 0.01% is still under 2.0fJS.
'100%
Figure 1. Settling Time
OUTPUT
The ADS09K and ADS09S are guaranteed to settle to 0.1 %
in SOOns and 0.01 % in 2.SfJS when tested as shown in Figure 2.
There is no appreciable degradation in settling time when
the capacitive load is increased to SOOpF, as discussed below.
The settling time is computed by summing the output and the
input into a differential amplifier, which then drives a scope
ERROR
SIGNAL
It!
7
1.0
i- ns r:;;:
It
,",'
It
i-no :;;::
Figure 4. AD509 with 500pF Capacitive Load
5pF
DECOUPLING CAPACITORS
OMITTED FOR CLARITY
SCOPE
Ein <>-_'VVI..-"i
Figure 2. AD509 Settling Time Test Circuit
SUGGESTIONS FOR MINIMIZING SETTLING TIME. The
ADS09 has been designed to settle to 0.01 % accuracy in
1 to 2.Sps. However, this amplifier is only a building block
in a circuit that also has a feedback network, input and output
connections, power supply connections, and a number of
external components. What has been painstakingly gained in
amplifier design can be lost without careful circuit design.
Some of the elements of a good high speed design are ......... .
CONNECTIONS. It is essential that care be taken in the
signal and power ground circuits to avoid inducing or
generating extraneous voltages in the ground signal paths.
OPERA TlONAL AMPLIFIERS 2-33
The O.lJ.1F ceramic power supply bypass capacitors are
considerably more important for the ADS09 than for low
frequency general purpose amplifiers. Their main purpose
is to convert the distributed high frequency ground to a
lumped single point (the V+ point). The V+ to V- O.lJ.1F
capacitor equalizes the supply grounds while the O.lJ.1F
capacitor from V + to signal ground should be returned to
signal common. The signal common, which is bypassed to
pin 7, is defined as that point at which the input signal
source, the feedback network, and the return side of the load
are joined to the power common.
Note that the diagram shows each individual capacitor
directly connected to the appropriate terminal (pin 7 [V+ I).
COMPONENTS. Resistors are preferably metal film types,
because they have less capacitance and stray inductance
than wirewound types, and are available with excellent
accuracies and temperature coefficients. .
Diodes are hot carrier types for the very fastest-settling
applications, but 1N914 types are suitable for more
routine uses.
Capacitors in critical locations are polystyrene, teflon, or
polycarbonate to minimize dielectric absorption.
01.,F
CERAMIC DISC
~
CIRCUIT. For the fastest settling times, keep leads short,
orient components to minimize stray capacitance, keep
circuit impedance levels as low as consistent with the output capabilities of the amplifier and the signal source,
reduce all external load capacitances to the absolute
minimum. Don't overlook sockets or printed circuit
board mounting as possible sources of dielectric absorption.
Avoid pole-zero mismatches in any feedback networks used
with the amplifier. Minimize noise pickup.
TO SIGNAL
POINT
INVERTING
INPUT
In addition, it is suggested that all connections be short and
direct, and as physically close to the case as possible, so that
the lengrh of any conducting' path shared by external
components will be minimized.
'-"1'----..., COMMON
OUTPUT
NON INVERTING
INPUT
O.",F
CERAMIC DISC
Figure 5. Configuration for Unity Gain Applications
DYNAMIC RESPONSE OF ADS09
120
.oz'
93
zw
80
120
~
100
'Il
1--
-
1111
IIII
~
60'
PHIIS.
60
g~
g
30'
40
1\
GAIN
20
-20
10
100
,.
lOOk
FREQUENCY
~
1M
10M
90'
i
120'
~
1506
f
180'
11:
10k
~
100
1
80
9~
60
Q,.
oz
~~
40
!:i
20
0<
g
1111
I
.
15
~+PSRR
~
...
~
"'"
lOOk
10k
5
~
1M
"-..
60
""-
PHASE
~
40
0
0
....
zw
<>.
0
8
\
~
GAIN
Vs=±15V
R L "10kH
<>.
20
~
0
10,000 _---t---T----t---r---;--'--j;-~<--I_r__l
~
lk
10k
lOOk
20
w
I
g
o
~
~
\
o
10M
Figure 5. Open Loop Frequency Response
~, 1000t---+--+--i-\-"<:--:J,.":
a:
~
Z
FREQUENCY - Hz
2-38 OPERA TIONAL AMPLIFIERS
(/)
40
~
1M
~
w
w
\\
-40
100
(WHEREVER JOHNSON NOISE IS GREATER THAN
AMPLIFIER NOISE. AMPLIFIER NOISE CAN BE
CONSIDERED NEGLIGIBLE FOR APPLICATION)
o
6
~
-20
10
20
15
Figure 6. Input Common-Mode Range vs. Supply Voltage
.........
I
"
10
SUPPLY VOLTAGE ±V
100
III
"
Z
<
V
o
o
10M
Figure 4. PSRR and CMRR vs. Frequency
80
/
<>.
FREQUENCY - Hz
100
10
::;)
0
V
;/..
+Y
w
"
:;
CMRR. -PSRR"'"
20
+ 25°C
~
w
C/l
~
~
20
0.1
40
_
106
L-_~
105
__.J'--_...L.._......J._ _-'-_-L._ _.l.__
10'
10&
109
10 10
_l
1011
SOURCE IMPEDANCE - Ohms
Figure 7. Peak-to-Peak Input Noise Voltage vs. Source
Impedance and Bandwidth
ELECTROMETER APPLICATION NOTES
The ADS1SA offers subpicoampere input bias currents available
in an integrated circuit package. This design will open up many
new application opportunities for measurements from very high
impedance and very low current sources. Performing accurate
measurements of this sort requires careful attention to detail;
the notes given here will aid the user in realizing the full measurement potential of the ADS1SA and perhaps extending its
performance limits.
1. As with all junction FET input devices, the temperature of
the FETs themselves is all important in determining the
input bias currents. Over the operating temperature range,
the input bias currents closely follow a characteristic of doubling
every lO·C; therefore, every effort should be made to minimize
device operating temperature.
2. The heat dissipation can be reduced initially by careful investigation of the application. First, if it is possible to reduce
the required power supplies, this should be done since internal
power consumption contributes the largest component of
self-heating. To minimize this effect, the quiescent current of
the ADS1SA has been reduced to less than lmA. Figure 8
shows typical input bias current and quiescent current versus
supply voltage.
3. Output loading effects, which are normally ignored, can
cause a significant increase in chip temperature and therefore
bias current. For example, a 2kO load driven at lOV at the
output will cause at least an additional 2SmW dissipation in
the output stage (and some in other stages) over the typical
24mW, thereby at least doubling the effects of self-heating.
The results of this form of additional power dissipation are
demonstrated in Figure 9, which shows normalized input
bias current versus additional power dissipated. Therefore,
although many de performance parameters are specified
driving a 2kO load, to reduce this additional dissipation, we
recommend restricting the load resistance to be at least
IOkO.
4. Figure 10 shows the ADS lSA's input current versus differential
input voltage. Input current at either terminal stays below a
few hundred fA until one input terminal is forced higher
than 1 to l.SV above the other terminal. Input current limits
at 30ILA under these conditions.
..
&S •
...
...
... I
... i
T..,=+2!rC
70
SUPPLY CURRENT
.
"1
50
B
..
INPUTCURR 00-
~
30
20.
"
POWER SUPPLY VOLTAGE _ :1:.V
.....
..
Figure 8. Input Bias Current and Supply Curren~ vs. Supply
Voltage
.
BASED ON I
TYPICAL 18 =4OfA
/
V
"
b--- to
25
50
L
~
75
100
125
150
175 200
mW
ADDmONAL INTERNAL POWER DISSIPATION -
Figure 9. Input Bias Current vs. Additional Power
Dissipation
':'p:t±:t:t:h
IIII
!W8
100n ~~:JIY -ll-1-+t-t+H-t-!H-t-t+H
T... "'+2S"C
"",H-t--1H--tt++H-+-t++-t+H-+-t--i
~ '"'H+-t+Hr+++-t+r+*--i+H-~
'OOffm-m.U$~~
10!..~
-3
-2
1
0
DtFfEJilENTlAL VOLTAGE
Figure 10. Input Bias Current vs. Differential Input Voltage
OPERA TIONAL AMPLIFIERS 2-39
ADSlSA CIRCUIT APPLICATION NOTES
The AD5l5A is quite simple to apply to a wide variety of applications because of the pretrimmed offset voltage and internal
compensation, which minimize required external components
and eliminate the need for adjustments to the device itself. The
major considerations in applying this device are the external
problems of layout and heat control which have already been
discussed. In circuit situations employing the use of very high
value resistors, such as low level current to voltage converters,
electrometer operational amplifiers can be destabilized by a pole
created by the small capacitance at the negative input. If this
occurs, a capacitor of 2 to 5pF in parallel with the resistor will
stabilize the loop. A much larger capacitor may be used if desired
to limit bandwidth and thereby reduce wideband noise.
Selection of passive components employed in high impedance
situations is critical. High MO resistors should be of the carbon
mm or deposited ceramic oxide to obtain the best in low noise
and high stability perfortnance. The best packaging for high
MO resistors is a glass body sprayed with silicone varnish to
minimize humidity effects. These resistors must be handled
very carefully to prevent surface contamination. Capacitors for
any high impedance or long-tertn integration situation should be
of a polystyrene formulation for optimum performance. Most
other types have too Iowan insulation resistance, or high dielectric
absorption.
Unlike situations involving standard operational amplifiers with
much higher bias currents, balancing the impedances seen at the
input tertninals of the AD51SA is usually unnecessary and probably
undesirable. At the large source impedances where these effects
matter, obtaining quality, matched resistors will be difficult.
More important, instead of a cancelling effect, as with bias
current, the noise voltage of the additional resistor will add by
root-sum-of-squares to that of the other resistor thus increasing
the total noise by about 40%. Noise currents driving the resistors
also add, but in the ADS15A are significant only above 10 110.
+
OUTPUT
(ALL RESISTORS OF SAME NUMBER SHOULD BE MATCHED
L-~--~--~~R~
(NEGATIVE PULSEI
OUT
... "",-Li
....c
T
.....
0
Figure 12. Low Drift Integrator and Low-Leakage Guarded
Reset
LOW-LEVEL CURRENT-TO-VOLTAGE CONVERTERS
Figure 2 shows a standard low-level current-to-voltage converter.
To obtain higher sensitivity, it is obvious to simply use a higher
value feedback resistor. However, high value resistors above
1090 tend to be expensive, large, noisy and unstable. To avoid
this, it may be desirable to use a circuit configuration with
output gain, as in Figure 13. The drawback is that input errors
of offset voltage drift and noise are multiplied by the same gain,
but the precision perfortnance of the ADS1SA makes the tradeoff
easier.
Figure 13. Picoampere to Voltage Convert~r with Gain
One of the problems with low-level leakage current testing or
low-level current transducers (such as Clark oxygen sensors) is
rmding a way to apply voltage bias to the device while still
grounding the device and the bias source. Figure 14 shows a
technique in which the desired bias is applied at the noninverting
tertninal thus forcing that voltage at the inverting terminal. The
current is sensed by RF , and the ADS24 instrumentation amplifier
converts the floating differential signal to a single-ended output.
to. t%)
(BUFFER At BOOSTS COMMON MODE liN BV DRIVING CABLE SHIELDS
AT COMMON MODE VOLTAGE AND NEUTRALIZING eM CAPACITANCE)
Figure 11. Very High Impedance Instrumentation
Amplifier
Figure 14. Current-to-Voltage Converters with Grounded
Bias and Sensor
2-40 OPERA TIONAL AMPLIFIERS
1IIIIIIII ANALOG
WDEVICES
Low Cost, Laser
Trimmed, Precision IC Op Amp
AD517
FEATURES
Low Input Bias Current: 1nA max (AD517L)
Low Input Offset Current: O.25nA max (AD517L)
Low Vos: 50llV max (AD517L). 150llV max (AD517J)
Low Vos Drift: 1.3p.VfC (AD517L)
Internal Compensation
MI L.standard Parts Available
a·Pin TO·99 Hermetic Metal Can
I
ADS17 PIN CONFIGURATI9N
OFFS~T
NULL
a
1
-IN
2
6
+IN
OUTPUT
NC
4
-VS
TOP VIEW
PRODUCT DESCRIPTION
The ADS17 is a high accuracy monolithic op amp featuring extremely low offset voltages and input currents. Analog Devices'
thermally-balanced layout and superior IC processing combine
to produce a truly precision device at low cost.
The ADS 17 is laser trimmed at the wafer level (LWT) to produce offset volt~es less than SOj.1V and offset voltage drifts
less than 1.31lV I C unnulled. Superbeta input transistors provide extremely low input bias currents of 1nA max and offset
currents as low as 0.2SnA max. While these figures are comparable to presently available BIFET amplifiers at room temperature, the ADS17 input currents decrease, rather than
increase, at elevated temperatures. Open-loop gain in many IC
amplifiers is degraded under loaded 'conditions due to thermal
gradients on the chip. However, the ADS 17 layout is balanced
along a thermal axis, maintaining open-loop gain in excess of
1,000,000 for a wide range of load resistances.
The input stage of the ADS 17 is fully protected, allowing differential input voltages of up to ±Vs without degradation of
gain or bias current due to reverse breakdown. The output
stage is short-circuit protected and is capable of driving a load
capacitance up to 100OpF.
The AD S 17 is well suited to applications requiring high precision and excellent long-term stability at low cost, such as
stable references, followers, bridge instruments and analog
computation circuits.
The circuit is packaged in a hermetically sealed TO-99 metal
can, and is available in three performance versions (], K, and
L) specified over the commercial 0 to +70o C range; and one
version (ADS17S) specified over the extended temperature
range, -SSoC to +12S oC.
PRODUCT HIGHLIGHTS
1. Offset voltage is 100% tested and guaranteed on all models.
2. The ADS17 exhibits extremely low input bias currents
without sacrificing CMRR (over 100dB) or offset voltage
stability.
3. The ADS17 inputs are protected (to ±Vs ), preventing offset
voltage and bias current degradation due to reverse breakdown of the input transistors.
4. Internal compensation is provided, eliminating the need for
additional components (often required by high accuracy IC
op amps).
5. The ADS17 can directly replace 725, 108, and ADS10 amplifiers. In addition, it can replace 741-type amplifiers if the
offset-nulling potentiometer is removed.
6. Thermally-balanced layout insures high open-loop gain independent of thermal gradients induced by output loading,
offset nulling, and power supply variations.
7. Chips are available.
OPERA TIONAL AMPLIFIERS 2-41
SPECIFICATIONS
(@ +25OC and Vs= ±15V de)
Model
Min
OPEN LOOP GAIN
Vo '" ±lOV,RL~2kn
T mm to T max. RL = 2k!l
10'
500,000
OUTPUT CHARACTERISTICS
Voltage (f/ RL = 2kO. T mm to T max
Load Capacitance
Output Current
Short CICCUt[ Current
AD5l7J
Typ
Max
Min
AD517K
Typ
Max
Min
Max
Units
VN
VN
V
pF
rnA
rnA
±lO
1000
10
10
10
AD517S
Typ
10'
250,000
1000
1000
10
Max
±1D
±lO
1000
ADSI7L
Typ
10'
500,000
10'
500,000
±IO
Min
25
25
25
25
250
IS
010
250
I 5
0.10
250
I 5
010
250
I 5
010
FREQUENCY RESPONSE
Unity Gam Small SIgnal
Full Power ResPonse
Slew Rate, Unuy Gam
INPUT OFFSET VOLTAGE
ImualOffset
Input Offset vs Temp.
Input Offset vs Supply
TmmtoTmax
INPUT BIAS CURRENT
Imtlal
TnuntoTmax
vs. Temp, TmmwTmax
kHz
kHz
V/I-ls
~V
ISO
3.0
25
40
75
1.8
10
15
50
1.3
10
15
75
1.8
10
20
5
8
,,20
2
35
,,10
1.0
I 5
,,4
2.0
10
" 10
nA
nA
pArC
1.0
I 5
0.75
I 25
0.25
04
2.0
10
nA
nA
!-lVre
~VN
~VN
INPUT OFFSET CURRENT
Imual
Tnun10Tmax
INPUTIMPEDANCE
Dtfferenual
Common Mode
INPUT VOLTAGE RANGE
DIfferenual
Common Mode Re)eCllOn
Common Mode ReJecuon
Tnun to Tmax
15111 5
lOxlO"
PACKAGE'
TO-99Style(H-08B)
MOllpF
0
:,::Vs
110
110
110
V
dB
94
110
100
100
dB
::tV s
±Vs
2
35
25
20
005
003
003
f= 10Hz
f= 100Hz
f= 1kHz
Current, f '= 10kHz
f= 100Hz
f= 1kHz
TEMPERATURE RANGE
Operatmg, Rated Performance
Storage
20111 5
20xlO"
94
INPUT NOISE
Voltage,O.lHzIO 10Hz
POWER SUPPLY
Rated Performance
Operatmg
QUiescent Current
201115
2.0x 10"
201115
20xlO"
2
35
25
20
005
003
0.03
" IS
,,5
0
,,5
+70
0
AD517jH
NOTES
ISee SectIOn 16 for package oudme IOformatlOn
SpeCIficatIOns sub,ect to change wIthout notICe
Specifications shown In boldface are tested on all productIon unm. at final
electrical test Results from those tests are used to calculate outgomg quality
levels All mm and max specIficatIOns are guaranteed, although only thOlle
shown m boldface are tested on all production umls
2-42 OPERA TlONAL AMPLIFIERS
2
35
25
20
0.05
003
003
:::: 18
,,5
+ 70
+ 150
~65
AD517KH
0
- 65
ADSI7LH
nV/\.I'Hz
nV/v'Hz
nV/YIiz
pA/YHz
pA/Y~
pA/\'Hz
, IS
" 18
3
3
~Vp-p
2
35
25
20
005
003
003
" IS
" IS
" 18
4
+ ISO
~65
.::'::Vs
,5
+ 70
~55
+ ISO
~65
" 18
3
+ 125
+ ISO
AD517SH
V
V
rnA
'c
"C
Typical Pel10rmance Curves
100M
,-,..-,.--r-r-r-,--,-rn
10M
f----t--+-+-++-+--t-t-H
140
120
'\,
"-'\,
100
ACL = 10000
0
I'..
"
60
40
0
ACL
.Joo
AcL
=!o
OPEN-LOOP
GAIN
V
AcL .1000
'''\
lM~-+--+-+-++-+-~-r-~
f\..
."'f\.
'"
0
\
lOOk
-20
01
10
100
lk
FREQUENCY - Hz
10k
lOOk
1M
,.
~_.L-_-'----'----'--'-
Small-Signal Gain vs. Frequency
Open-Loop Gain
2.0
at'--.
1.
6
1.
4
2
0
O.
r--.....
'"'--
..............
~
a
,
~
...
""""'"
•
O.
~
g
~
517K
41---517L
,~
K
200
r" V
3
AD517S
4
AD617L
0)
.J
\V
"'~~VV V~
~
0
517S
vs. Load Resistance
2 AD517K_
300
"
______--'_.L-""
1~
LOAD RESISTANCE - ohms
'00
V
(3
V
~"
2
,
70
25
125
TEMPERATURE _
-75
°c
Input Bias Current vs. Temperature
130
120
-.....
110
,
!!l
100
,.
90
a:
a:
"
" """'-
70
60
10
-25
60
25
TEMPERATURE _ °c
75
100
125
Untrimmed Offset Voltage vs. Temperature
'20
80
10
-50
100
11 0
100
.....
!!l,90
'~
a:
If
"'"
,.
FREQUENCV - Hz
CMRR
i'
vs. Frequency
~
70
"- [\..
'Ok
80
60
"'"
lOOk
50
01
10
100
,.
"
10k
FREQUENCY - Hz
PSRR vs. Frequency
OPERATIONAL AMPLIFIERS 2-43
••
.2
~EGAT'~E ":'NGI
;;V
12
•
.
g•
.
g
•0
.0
~
,
~ 8
~
w
'";!
\
8
f
\
~
~
"\.
3
-
"I"-
•0
FREQUENCY - kHz
o
.00
.0
01
10
0.1
LOAD RESISTOR TO GROUND - kil
Maximum Undistorted Output VB.
Frequency (Distortion"; 1%)
1,
i
'5
10
,.- ,/'
a:
a:
-'5
-10
!
-6
jj
,.-V
i
l -.0~
V
V
Z
i
Output Voltage VB. Load Resistance
//
G
..
- ,/'
/
.
~
40
iii
20
o ~
V
V
.0
80
2
~
~
...
~
\
.j
-20
-40
-20
-26
-30
-16
+5
-10
POS'T'VESW'NG - f -
;/1
1\
.!!
~--
+10
+15
+20
+26
+30
••
DIFFERENTIAL INPUT VOLTAGE
-80
o
""
"-... I"--.
--
TIME AFTER POWER SUPPL V lURN..()N - Minutel
Input Current vs. Differential Input Voltage
Warm-Up Offset Voltage Drift
100
VOLTAGE NOISE 0.1 - 10Hz
lis. e
Rsz • 200k
I
~
Rs =0
10
100
lk
10k
En =500nVIDIV RTI
FREQUENCY - Hz
Total Input Noise Voltage VB. Frequency
2-44 OPERATIONAL AMPLIFIERS
Low Frequency Voltage Noise (0.1 to 10Hz)
Applying the AD517
NULLING THE ADS17
The internally-trimmed offset voltage of the ADS 17 will be low
enough for most circuits without further nulling. However, in
high precision applications, the ADS 17 may be nulled using
either of the following methods:
Figure lA shows a simple circuit using a 10kn, ten-turn potentiometer. This circuit allows nulling to within several microvolts.
The circuit of Figure 18 is recommended in applications where
nulling to within I~V is desired. This circuit has the advantage
that potentiometer instability effects are reduced by a factor
of ten. Values of RI' and Rz' are calculated as follows:
1. Null the offset to zero using a standard 10k pot, as shown
in Figure 1A.
2.. Measure pot halves RI and R z .
3. Calculate:
Rz x SOkn
Rz = ---'''---::--SOkn-R z
,
4. Replace the pot with RI' and Rz' using the closest value
1% metal film resistors.
+15V
R2
10k 1%
3
INPUT
Rl
10Mn
1%
6
2
-15V
R7
lk 1%
Rl0
90k 0.02%
R8
9.09k 1%
Rll
9k 0.02%
R9
10k 1%
R12
900n 0.02%
R13
loon 0.02%
S. Use a lOOk, ten-turn pot for Rp to complete the nulling.
Figure 2. Stable Instrument Input Amplifier
7
1
8
10k
10 TURNS
A. Simple
7
R1'
1
R2'
........-----.l>t,A,/\,..---....-{ 8
B. High Precision
Figure 1. Nulling Circuits
AN INSTRUMENT INPUT AMPLIFIER USING THE ADS17L
The circuit shown in Figure 2 represents a typical input stage
for laboratory instruments and panel meters. The amplifier is
non-inverting and offers selectable gains from 1 to 1000 in
decade steps.
Input impedance of this amplifier is 10 megohms, determined
by resistor R 1 . The offset nulling network comprised of R 3,
R4 and Rs is the same one described earlier. If a less precise
adjustment can be tolerated, a single 10k potentiometer can be
substituted for R 3 , R4 and Rs.
Gain switching is accomplished in the feedback network. The
divider consisting of RIO' R u , R12 and Rl3 determines the
gain by dividing the output and returning it to the inverting
input of the amplifier. The ratio tolerances of these resistors
uniquely determine the gain of the amplifier. The impedance
seen by the inverting input is held constant at 10k ohms by
R6 . R7 Rs or R9 depending on the gain selected. Since input
bias currents flow through equal resistances, the offset voltages
produced will cancel each other. The input offset currents will
produce an insignificant offset voltage on the order of 1 microvolt. If this offset is nulled out at the highest gain selected, it
will be nulled on all ranges.
The ADS 17 offers excellent temperature stability in this circuit. Once the offset has been zeroed, the error produced by
offset current drift will remain quite low due to the extremely
low offset current drift of the ADSI7. A FET-input op amp
would not work well in this application, since the input offset
currents would double for each 10° C increase in temperature,
soon exceeding the input offset currents of the ADS17.
OPERA TlONAL AMPLIFIERS 2-45
CHIP DIMENSIONS AND BONDING DIAGRAM
Dimen'iions shown in inches and (mm).
0.071
(1.803)
......-o+Vs
-IN 0--1_
;-.....-0 OUTPUT
CHIP EDGE
THE ADS17 IS AVAILABLE IN
LASER·TRIMMED CHIP FORM.
2-46 OPERA TIONAL AMPLIFIERS
IIIIIIIIIII ANALOG
WDEVICES
FEATURES
Ultralow Drift: 1/1V/oC - AD547L
Low Offset Voltage: 0.25mV - AD547L
Low Input Bias Currents: 25pA max, Warmed-Up
Low Quiescent Current: 1.5mA
Low Noise: 2/1V p-p
High Open Loop Gain: 110dB
High Slew Rate: 13V//1s
Fast Settling to ± 0.01%: 3/1s
Low Total Harmonic Distortion: 0.0025%
High Performance
BiFET Operational Amplifiers
AD 542/AD 544/AD 547 I
AD542, AD544, AD547 FUNCTIONAL BLOCK DIAGRAM
TAB
INVERTING
INPUT
TOP VIEW
PRODUCT DESCRIPTION
The BiFET series are precision monolithic FET -input operational
amplifiers fabricated with the most advanced BiFET and laser
trimming technologies. The series offers bias currents significantly
lower than currently available BiFET devices, 25pA max, warmedup.
In addition, the offset voltage is laser trimmed to less than
0.25mV on the AD547L which is achIeved by utihzing Analog's
exclusive laser-wafer trimming (LWT) process. When combined
with the AD547's low offset voltage drift (I ""VI'C) , these features
offer the user IC performance truly superior to existing BiFET
op amps-and at low, BiFET pricing.
The AD542 or AD547 is recommended for any operational
amplifier application requiring excellent dc performance at low
to moderate costs. Precision instrument front ends requiring
accurate amplification of millivolt level signals from megohm
source impedances will benefit from the device's excellent combination of low offset voltage and drift, low bias current and
low IIf noise. High common mode rejection (80dB, min on the
"K" and "L" versions) and high open-loop gain--even under
PRODUCT HIGHLIGHTS
1. Improved bipolar and JFET processing results in the lowest
bias current available in a monolithic FET op amp.
2. Analog Devices, unlike some manufacturers, specifies each
device for the maximum bias current at either input in the
warmed-up condition, thus assuring the user that the device
will meet its published specifications in actual use.
3. Advanced laser wafer trimming techniques reduce offset
voltage drift to I ""V/'C max and offset voltage to only 0.25mV
max on the AD547L.
4. Low voltage noise (2"" V, p-p), and low offset voltage drift
enhance performance as a preciSIon op amp.
5. The high slew rate (B.OV/fLS) and fast settling time to 0.01%
(3.0""s) make the AD544 ideal for D/A, AID, sample-hold
circuits and high speed integrators.
6. Low harmonic distortion (0.0025%) make the AD544 an
ideal choice for audio applications.
7. Unmounted chips available for hybrid circuit applications.
heavy loading-ensures better than "12-bit" linearity in high
impedance buffer applications.
The AD544 is recommended for any operational amplifier application requiring excellent ac and dc performance at low cost.
The 2M Hz bandwidth and low offset of the AD544 make it the
first choice as an output amplifier for current output D/ A converters such as the AD7541, 12-bit CMOS DAC.
Devices in this series are available in four versions: the "J",
"K" and "L" are specified over the 0 to + 70'C temperature
range and the "S" over the - 55'C to + l25'C operating temperature range. All devices are packaged in the hermetically-sealed,
TO-99 metal can.
OPERA TlONAL AMPLIFIERS 2-47
SPECIFICATIONS
(@ +25"1: and Vs= :t:15V de)
Model
AD54Z
Min
Typ
ADS44
Max
Min
Typ
AD547
Max
Min
1'1p
Max
Units
OPEN LOOP GAIN'
VOUT
= ::!:lOVR.L~2kO
j
K,L,S
100,000
250,000
30,000
50,000
100,000
250,000
VN
VN
100,000
100,000
250,000
20,000
20,000
40,000
100,000
100,000
250,000
VN
VN
VN
TA = TmmIOT...."
j
S
K,L
OUTPUT CHARACTERISTICS
VOVT = RJ. =2kn
Tit. = TmmIOTm.u
VOI.:T = RL
:10
~12
:10
~12
%10
~
12
Volts
H2
±13
%12
~
:12
~I3
Volts
= lOkO
TA = Tm,nfOTmu
Shon C,rcwt Current
FREQUENCY RESPONSE
URltyGam, Small Signal
Full Power Response
Slew Rate, UrutyGam
Total HannonlC Distortion
25
2.0
13
25
1.0
SO
30
INPUT OFFSET VOLTAGE'
j
K
L
S
vs Temperam(t3
j
K
L
S
vs Supply, TA = Tm.ntoT...."
j
K,L,S
8.0
2ll
200
130
00025
2.0
25
mA
1.0
SO
3.0
V/~s
MHz
kHz
%
mV
2.0
1.0
0.5
1.0
2.0
1.0
0.5
1.0
1.0
O.S
0.25
0.5
20
10
5
15
20
10
5
15
5
2
I
5
""VI"C
200
100
200
100
200
100
".V/V
mV
mV
mV
~V?c
....V/OC
~V?c
~VN
INPUT BIAS CURRENT'
Either Input
j
K,L,S
Input Offset Current
j
K,L,S
INPUT IMPEDANCE
Differential
Common Mode
INPUT VOLTAGE'
Dlfferenual
Common Mode
Common·Mode ReJecuon
VIN = ::tIOV
j
K,L,S
POWER SUPPLY
Rated Performance
Operating
QUIeSCent Current
VOLTAGE NOISE
o I-10Hz
j
K,L,S
10Hz
100Hz
1kHz
lOkH7
10
50
25
10
50
25
10
50
25
pA
pA
5
2
15
15
5
2
15
15
5
2
15
15
pA
pA
~20
:10
~
±IO
~
~
:10
±IS
1.5
20
20
70
45
30
25
IS
~5
18
dB
dB
H8
1.5
Volts
Volts
mA
4.0
~VP'L
!:.IS
:18
2.5
20
20
35
22
18
16
~5
II
p.Vp-p
20
nV/VHz
70
45
30
25
nVf"fh
oV/\
010 170
Oto 170
55to I 125
65 to I 165
55to 1125
65to I 165
IOpen Loop Gam JS speafied With Vos both nulled and unnulled
lInput Offset Voltage speclficauous are guaranteed afIel' 5 mmutes
of operauon at T A ,., +25"<:.
3Input Offset Voltage Dnft 18 speafted With the offset voJtage
unnulled Nullmgwill mduce an addmona13fJ.Vl"ClmV of
ouIIed offset.
4Jhas Current speaficauons are guaranteed maximum at CItbel'
mput IIfm' 5 minutes of operauon at TA = + 2S"C For bJgber
AD544jH, ADS44KH
AD544I.H, ADS44SH
!k
nVf\ Hz
010 t 70
NOTES
2-48 OPERA TIONAL AMPLIFIERS
12
5510 I 125
65(0 I ISO
AD542jH,AD542KH
AD542LH, AD542SH
temperatures, the current doubles every lOOC
~
76
80
~
15
II
Volts
Volts
~20
12
76
80
~5
10"1l116pF
10"1l113pF
~20
12
76
80
TEMPERATURE RANGE
Operaung, Rated Performance
j,K,L
S
Storage
PACKAGE OPTIONS'
TO·99(H-
~is
15
5
~
~
Figure 1. Input Voltage Range vs.
Supply Voltage
0
>
~
~
100
Vs=±15
1000A
~
'"A
V
/"
J/ ,
l00pA
'''A
'.A-55
2.
15
_·v
-25
0
35
Figure 3. Output Voltage Swing vs.
Resistive Load
7.,------,------,
. so,t-------------1-------------;
ia
1
, ,'5-
:1
iD
~
~ ~ir-------------+-------_t~--i
70
TEMPERATURE
Figure 4. Input Bias Current vs.
Supply Voltage
,
~
V V
---V
--
10k
1k
LOAD RESISTANCE - Ohms
I
---- s
l00nA
10
/
0
2.
15
-J,b
SUPPLY VOLTAGE
I.
0
Figure 2. Output Voltage Swing vs.
Supply Voltage
.
~
lL
4
S
2S"C
AL=2k
SUPPLY VOLTAGE - tV
SUPPL Y VOLTAGE - tV
•
If
~
/VOU,
0
20
Vr-"
~
~120
.~o~V
1
25~C
5
/.
~ 15
~ /:.
~Y
I.
30
95
125
".
-10
_·c
COMMON MODE VOLTAGE - V
Figure 5. Input Bias Current vs.
Temperature
Figure 6. Input Bias Current vs. CMV
0
125
RL'''2k
5
100
~
1
~
./
5
I-.;;;;.
V
0
V
7
.........
5
AD542
5<)
V
/V
5~
0
r--... t--......
.............
55
25
WARM UP TIME - MInutes
TEMPERATURE
Figure 7. Change in Offset Voltage
vs. Warm-Up Time
•
100
90
125
FREQUENCY - Hz
Figure 9. Open Loop Frequency
Response
110
110
r;:-Q542, A0547 _
V
V
100
'll
1
Z
/'
280
..-.;;;;
~
;80
I"
~
~40
~
0
2S"C
Rl-2k{}
10
SUPPLY VOLTAGE - tV
"
Figure 10. Open Loop Voltage
Gain vs. Supply Voltage
=~'5V
Vs '" :l:15VWITH
1V pop SINE WAVE
80
60
100
_·c
Figure 8. Open Loop Gain vs.
Temperature
120
11
r-----.t--
5
AD547
20
10
to
""\ .suppL_ r--~
'" '"
100
1k
10k
~
tOOk
1M
so
~
'"
'll
1
~
~
~PPLY
~
.J.
Vs
VCM = 1V pop +2SOC
100
II
60
40
20
o
10M
FREQUENCY - Hz
Figure 11. Power Supply Rejection
vs. Frequency
10
100
~
,.
""
'Ok
"'-00k
M
10M
FREQUENCY - Hz
Figure 12. CommonModeRejection
Ratio vs. Frequency
OPERA TIONAL AMPLIFIERS 2-49
.....
0
r
+10
30
j
I
\ \
5
AD....
.."c
AD547
\
Vs-±15V
RL=2\(
0
0
•
10
15
SUPPLY VOLTAGE - ±Voltl
20
Figure 13. QuiescentCurrentvs.
Supply Voltage
0
AD....
AD547
100
10
lk
i!:
~
~~
\
10k
lOGe
FREQUENCY - Hz
i"
~
\.
~
-s
5
0
1M
10M
-10 !:-o---~-->---:-----'~--'"
SETTLING TIME _
Figure 14. Large Signal Frequency
Response
10
+5
~s
Figure 15. AD544 Output Settling Time vs.
Output Swing and Error
100
(WHEREVER JOHNSON NOISE IS GREATER THAN
AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE
CONSIDERED NEGLIGIBLE fOR APPLICATION)
lkH.
RESISTOR JOHNSON NOISE
~
.-/
,Y\
//
/
~~~~~E,~ WIT~
1
-
10k
lk
0
1
...........
\
1
AD542.
~7
0
AD&44
1
......
0
~~tl~:~~N
i--'
0.001
100
I
.....-
......-
FREQUENCY - Hz
Figure 16. AD544 Total Harmonic
Distortion vs. Frequency
0
.....-:
t
~
V <\
~
/
10Hz
AMPLIFIER
GENEjATEP jOISE
0
lOOk
/
¥,/
/...-
10
100
lk
10k
lOOk
FREQUENCY - Hz
Figure 17. Input Noise Voltage
Spectral Density
1
o ,"
,"
101
lOS
,"
SOURCE IMPEDANCE -
10"
Figure 18. Total rms Noise vs. Source
Resistance
+V
+V
a. UnityGainFollower
b. Follower with Gain = 10
Figure 19. T.H.D. TestCircuits
Figure 21a. Unity Gain Follower'
Pulse Response (Large Signal)
Figure 20. Standard Null Circuit
Figure 21 b. Unity Gain Follower
Pulse Response (Small Signal)
Figure 21c. Unity Gain FollowerAD5421AD547
Figure 22b. Unity Gain Inverter
Pulse Response (Large Signal)
Figure 22c. Unity Gain Inverter
Pulse Response (Small Signal)
,991<"
VINo-"",l.-j
to the log of the ratio of the inputs:
+15V
v,
1k
}
154k
VOUT--WLOG,O I,/IZ
OR -1V LOO,o V,lVz
"'
'OOk
1k
',o--......---'!..j
1k
RTC
TEL LABS
+36OOppm
081
NOTES
CIRCUIT SHOWN FOR NEGATIVE V OR liN
FOR POSITIVE INPUTS,m- PNP,AND VA =-15V
-15V
Figure 33. Log-Ratio Amplifier
The conversion between current (or voltage) input and log output
is accomplished by the base emitter junctions of the dual transistor
Ql. Assuming QI has 13> 100, which is the case for the specified
transistor, the base-emitter voltage on side I is to a close approximation:
VBE
A
= kT/q In 1/ISI
This circuit is arranged to take the difference of the VBE'S of
QIA and QIB, thus producing an output voltage proportional
VOUT= -K(VBE A
-
VBE B)=
Kkt
-q:(In 1/ISI -In 1/182 )
VOUT= -K kT/q In 1/12
The scaling constant, K is set by RI and Rrc to about 16, to
produce IV change in output voltage per decade difference in
input signals. Rrc is a special resistor with a + 3500ppml°C
temperature coefficient, which makes K inversely proportional
to temperature, compensating for the "T" in kT/q. The log-ratio
transfer characteristic is therefore independent of temperature.
This particular log ratio circuit is free from the dynamic problems
that plague many other log circuits. The - 3dB bandwidth is
50kHz over the top 3 decades, 100nA to I OOILA, and de~reases
smoothly at lower input levels. This circuit needs no additional
frequency compensation for stable operation from input current
sources, such as photodiodes, that may have lOOpF of shunt
capacitance. For larger input capacitances a 20pF integration
capacitor around each amplifier will provide a smoother frequency
response.
This log ratio amplifier can be readily adjusted for optimum
accuracy by following this simple procedure. First, apply
VI = V2 = =--lO.OOV and adjust "Balance" for VOUT= O.OOV.
Next apply VI = -lO.OOV, V2 = -l.OOV and adjust gain for
VOUT= + l.OOV. Repeat this procedure until gain and balance
readings are within 2mV of ideal values.
R1 10k
Figure 34. Differentiator
Figure 37. Capacitance Multiplier
VOUT
'--=--"'-+-0
RESET
(NEGATIVE PULSE)
OUT
"6
2.
Figure 35. Low Drift Integrator and Low-Leakage Guarded
Reset
_FC,
Figure 38. Long Interval Timer - tOOO Seconds
C2
"2
820pf Dn
RESET
,r~-----4--!
,."
l.6kn
Figure 36. Wien-Bridge Oscillator - fo = 10kHz
2-54 OPERA TIONAL AMPLIFIERS
Figure 39. Positive Peak Detector
1IIIIIIII ANALOG
WDEVICES
Precision, Low-Power BiFET Op Amp
AD548 I
FEATURES
DC Performance:
200jl.A max Quiescent Current
10pA max Bias Current. Warmed Up (AD548C)
250jl.V max Offset Voltage (AD548C)
2j1.VI"C max Drift (AD548C)
2j1.V pop Noise. 0.1 to 10Hz
AC Performance:
1.8 V/jl.s Slew Rate
1MHz Unity Gain Bandwidth
Available in Plastic. Hermetic Cerdip and
Hermetic Metal Can Packages
MIL-STD-883B Parts Available
Dual Version Available: AD648
AD548 CONNECTION DIAGRAMS
Plastic Mini-DIP (N) Package
and
Cerdip (Q) Package
INVERTING
INPUT
NONINVERTING
INPUT
TOP VIEW
TO-99
(H) Package
NC
PRODUCT DESCRIPTION
The AD548 is a low-power, precision monolithic operational
amplifier. It offers both low bias current (lOpA max, warmed
up) and low quiescent current (200fLA max) and is fabricated
with ion-implanted FET and laser wafer trimming technologies.
Input bias current is guaranteed over the AD548's entire commonmode voltage range.
The economical J grade has a maximum guaranteed input offset
voltage of less than 2mV and an input offset voltage drift of less
than 20fLVrc. The C grade reduces input offset voltage to less
than O.25mV and offset voltage drift to less than 2fLV/oC. This
level of dc precision is achieved utilizing Analog's laser wafer
drift trimming process. The combination of low quiescent current
and low offset voltage drift minimizes changes in input offset
voltage due to self-heating effects. Five additional grades are
offered over the commercial, industrial and military temperature
ranges.
The AD548 is recommended for any dual supply op amp application requiring low power and excellent dc and ac performance.
In applications such as battery-powered, precision instrument
front ends and CMOS DAC buffers, the AD548's excellent
combination of low input offset voltage and drift, low bias current
and low lIf noise reduces output errors. High common-mode
rejection (86dB, min on the "c" grade) and high open-loop gain
ensures better than l2-bit linearity in high impedance, buffer
applications.
The AD548 is pinned out in a standard op amp configuration
and is available in seven performance grades. The AD548J and
AD548K are rated over the commercial temperature range of 0
to + 70°C. The AD548A, AD548B and AD548C are rated over
the industrial temperature range of - 40°C to + 85°C. The
AD548S and AD548T are rated over the military temperature
range of - 55°C to + 125°C and are available processed to MILSTD-883B, Rev. C.
vNOTE PIN 4 CONNECTED TO CASE
,
5
~
10kn
4
-15V
Vos TRIM
TOP VIEW
screening includes 168-hour burn-in, as well as other environmental and physical tests.
The AD548 is available in an 8-pin plastic mini-DIP, cerdip,
small outline or TO-99 metal can.
PRODUCT HIGHLIGHTS
I. A combination of low supply current, excellent dc and ac
performance and low drift makes the AD548 the ideal op
amp for high-performance, low-power applications.
2. The AD548 is pin compatible with industry standard op
amps such as the LF44I, TL061, and AD542, enabling
designers to improve performance while achieving a reduction
in power dissipation of up to 85%.
3. Guaranteed low input offset voltage (2mV max) and drift
(20fLVrC max) for the AD548J are achieved utilizing Analog
Devices' laser drift trimming technology, eliminating the
need for external trimming.
4. Analog Devices specifies each device in the warmed-up condition, insuring that the device will meet its published specifications in actual use.
5. A dual version, the AD648 is also available.
6. The AD548 is available in chip form.
Extended reliability PLUS screening is available for parts specified
over the commercial and industrial temperature ranges. PLUS
OPERATIONAL AMPLIFIERS 2-55
SPECIFICATIONS (@+m:andVs = ±l5Ydc,unlessothelWisenoled)
AD548J/AIS
Typ
Max
Model
MiD
INPUT OFFSET VOLTAGE
Initial Offset
0.75
TmmtoTmall
vs Temp.
MiD
2.0
3.0/3.013.0
20
AD548K1BIT
Typ
Max
0.3
AD548C
Typ
010
0.5
0.7/0.8/1.0
5
Units
0.25
0.4
2.0
mV
mV
jJ.VI"C
dB
dB
80
~V/month
IS
IS
IS
Max
86
86
80
80
76176176
.s. Supply
vs. Supply, T nun to T max
Lons-Tenn Offset StablillY
Min
INPUT BIAS CURRENT
EltherInput2, V('M =0
5
3
20
0.45/1.3/20
Either Input 2 at Tmax' VCM =0
Max Input Bms Current Over
Common-Mode Voltage Range
Offset Current, VCM =0
5
30
10
2
0.25/0 65/10
Offset Current at T max
3
10
0.25/065/10
IS
5
2
o 15/0.35/5
10
065
pA
nA
IS
5
035
pA
pA
nA
INPUT IMPEDANCE
DifferentIal
I x 10"113
3 x 10"113
I x 10"113
3 x 10"113
Common Mode
I x 10"113
3 x 10 1'113
1I11pF
1I11pF
±20
±12
V
V
98
98
90
90
dB
dB
dB
dB
INPUT VOLTAGE RANGE
Dlfferenua1 3
Common Mode
Common-Mode Rc)cctJon
V';M= ± IOV
±ll
76
TmmtoTmax
76176/76
VCM -= :::!:llV
T m1n to Tmax
70
70/70/70
INPUT VOLTAGE NOISE
VoltageO IHzto 10Hz
f= 10Hz
f= 100Hz
f= 1kHz
f= 10kHz
INPUT CURRENT NOISE
f= 1kHz
±20
±12
:til
±20
± 12
90
90
84
84
82
82
76
76
92
92
86
86
±ll
86
86
76
76
4.0
jJ.V~
2
80
2
80
2
80
40
40
40
30
30
30
30
30
30
nVI Hz
nV/V'HZ
nV/v'Hz
nV/V'HZ
1.8
18
1.8
fA/v'Hz
1.0
30
1.8
8
MHz
kHz
V/jJ.s
jJ.S
FREQUENCY RESPONSE
Unity Gam, Small Signal
08
Full Power Response
Slew Rate, UmtyGam
1.0
T mm to T maX) RI.~ lOill
Vo= :::!:lOV,RI.~5k!l
T mm to T max, RJ. ~ SkU
OUTPUT CHARACTERISTICS
Voltage((l RI.~lOkn,
Tmmto Tmax
Voltage((t
RI.~Skn,
TmmtoTmax
300
300
ISO
ISO
1000
700
500
300
300
300
ISO
ISO
1000
700
500
300
V/mV
V/mV
V/mV
V/mV
±12
±12
±ll
±ll
± 13
±12
±12
±13
V
± 12 3
±u
±123
V
IS
mA
300
300/300/300
ISO
150/150/150
1000
700
500
300
±12
±13
1.0
±12/±12/±12
±ll
± 111± 1lI±1l
± 12 3
±18
TEMPERATURE RANGE
Operating, Rated Performance
CommercJal (0 to + 70OC)
Industnal ( - 4O"C to + 85"C)
Mlluary( - 55OCto + 125OC)
PACKAGE OPTIONS'
Plasttc (N-8)
Cenhp(Q-8)
Metal Can (H-08A)
170
±11
± IS
±15
± 15
±4.S
1.0
15
15
Short CircUIt Current
POWER SUPPLY
Rated Performance
Operating Range
QUiescent Current
08
08
SenlmgTlffieto =0.01%
OPEN LOOP GAIN
Vo= ± IOV,RI.~lOkll
1.0
30
18
8
10
30
18
8
200
±4.5
170
±18
200
AD548J
AD548A
AD548S
AD548K
AD548B
AD548T
AD548JN
AD548AQ, AD548SQ
ADS48AH, AD548SH
AD548KN
AD548BQ, AD548TQ
AD548BH, AD548TH
NOTES
JInput Offset Voltage specifications are guaranteed after 5 mlDutes of operation at T A=-+ 25°C
2Blas Current specifications are guaranteed nwumum at either IDPU[ after 5 mlDutes of operation at TA = + 25"C
For hIgher temperature, the current doubles every lO"C
lDefined as voltages between mputs, such that neither exceeds ± lOV from ground.
4See Section 16 for package outline mformauon
SpeCifications subject to change wtthout notice.
Specifications In boldface are tested on all productIOn uru(S at final eiectrlcal test Results from those tests are used to
calculate outgomg quality levels All mID and max speclficatlorn. are guaranteed, although only those shown In boldface
are tested on all production units
2-56 OPERATIONAL AMPLIFIERS
±4.S
170
±18
200
AD548C
ADS48CQ
AD548CH
V
V
jJ.A
ABSOLUTE MAXIMUM RATINGSl
Supply Voltage . • . • . . . . . . . . . • . . . . . • . ± 18V
Internal Power Dissipation . • . • . . . . • . • • . • sOOmw
Input Voluge2 . • • • • • • • • . • • . • . • • . . . •. ± 18V
Output Shon Circuit Duration . . . . . . . . . .. Indefinite
Differential Input Voltage. • • . • • . • . .. + Vs and - Vs
Storage Temperature Range Q, H . . . • . - 6S"C to + lSO"C
N . . . • . . • -6S"C to + 12S"C
Operating Temperature Range
ADS48JIK • • . . . . . . . . . . • . . . . . . 0 to + 7O"C
ADS48AIB/C . . . . • . . . • . . . . •. - 4O"C to + 8S"C
ADS48SIT . . . . . . . . . . . . . . . . - SS"C to + 125°C
Lead Temperature Range (Soldering 6Osec) • . • • • •. 3000C
NOTES
'Stresses above those listed under "Absolute Maximum Ratinp" may
cause pcrIIIIIDCDt damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute muimum rating conditions for extended
periods may affect device reliability.
'Por supply voltqes less than ± IBV, the absolute muimum input voltage is
equal to the supply voltage.
CHIP DIMENSIONS AND PAD LAYOUT
Dimensions shown in inches and (mm).
0.072
(1.829)
OFFSET NULL
1
INVERTING
INPUT
2-
7 V+
......
NONINVERTING 3--1"INPUT
0.067
(1.702)
6 OUTPUT
5 OFFSET NULL
4
VOPERA TIONAL AMPLIFIERS 2-57
20
20r-----,------,r-----,------,
JO
+Vour
025
~
>
"
'20
Z
~
~
~ I.
w
~
~>
~
~
0
~
~
,
+1 15
w
10
~
>10
~
o
oL-____
o
~
______L-____
~----~
15
I
o
,
01-
0
10
0
20
SUPPLY VOLTAGE-
/
5
15
20
Figure 1. Input Voltage Range
Vs. Supply Voltage
10k
1k
100
10
SUPPLY VOLTAGE-
LOAD RESISTANCE - U
Figure 2. Output Voltage Swing
Vs. Supply Voltage
200
Figure 3. Output Voltage Swing
vs. Resistive Load
lDOnA
lDnA
V
180
'"A
.
L
'OOpA
,...... L
,. V
140
L
,/
tOpA
lOA
o
120
10
15
20
lOOfA
SUPPLY VOLTAGE _ :tV
"
20
-55
-25
.5
5
35
65
TEMPERATURE - "C
125
Figure 6. Input Bias Current Vs.
Temperature
Figure 5. Input Bias Current
Vs. Supply Voltage
10
~
IOfA
o
SUPPLY VOLTAGE - ±V
Figure 4. Quiescent Current Vs.
Supply Voltage
./
--
/"
JO
1500
l'Ok
RL ""
25
~
v
j.."'"
V
Oi
~
V
-2
COMMON-MODE VOLTAGE - V
'v
0
10
100
100
0
~HAL
0
1'0. .....
~~
GAIN
20
..... ~
\
0
0
-40
1k
,,
80
.
lOOk
500
V
250
o
10
20
30
40
60
50
70
-55
-25
35
TEMPERATURE -
1M
Figure 9. Open Loop Gain Vs.
Temperature
120
120
v~
i'"""""I"""
/
110
I
100
12'
11
100
I'1'+ SUPPLY
...... .....
1.....
90
"-
1'
20
-SUPPLY
80
.....
"
0
.......
20
10M
FREQUENCY _ Hz
Figure 10. Open Loop Frequency
Response
2-58 OPERA TlONAL AMPLIFIERS
.5
os
·c
Figure 8. Change in Offset Voltage
Vs. Warm-Up Time
40
40
10k
~
750
TIME - Seconds
Figure 7. Input Bias Current Vs.
Common-Mode Voltage
0
v
15
0
-.
,
1000
20
,,
>
70
60
0
o
2
8
10
1
14
1
18
SUPPLY VOLTAGE _ ±V
Figure 11. Open Loop Voltage Gain
Vs.Supply
-20
100
lk
10k
lOOk
FREQUENCY _ Hz
Figure 12. PSRR Vs. Frequency
1M
Typical Characteristics
.
80
-
20
,.
'''-.
.
1Or-----,-------r---~~~--_,
22
r-...
50
40
1"1
~ 16
> ,•
~
"~
~
~
,•
i•
I'
•
12
,
4
2
•
"
20
'K
10K
tOOK
'M
FREQUENCY _ Hz
Figure 13. CMRR Vs. Frequency
_1OL-____
10.
lK
10K
tOOK
•
,M
FREQUENCY - Hz
Figure 14. Large Signal Frequency
Response
..
I
I
, f - +--
1/
~
~
-
;
FOLLOWER
.00''DO
10k
fREQUENCY - Hz
O:>~
',,•
1,000
10'
1--+--17''Tt--~~~'--itt----i
6
4
II
II
lk
7-
~ •
UNITV GAIN
~ DOl
~
10,OOOI--+--1--t---+--1-7"'I
>
8
____
t
120
~100
g~
~
WHENEVER JOHNSON NOISE IS GREATER THAN
%
IJ
FOLLOWER
WITH GAIN = 10
L __ _ _ _
SfTTLING TIME - ... 5
AMPLIAER NOISE, AMPliFIER NOISE CAN BE
CONSIDERED NEGLIGIBLE FOR APPLICATION
'4'
I!-"
______
Figure 15. Output Settling Time Vs.
Output Swing and Error Voltage
,
•
~
'00'
Figure 16. Total Harmonic
Distortion vs. Frequency
Figure 19a. Unity Gain Follower
•
•
10
100
lk
FREQUENCY _ Hz
10k
'DO'
SOURCE IMPEDANCE - it
Figure 17. Input Noise Voltage
Spectral Density
Figure 18. Total Noise Vs. Source
Resistance
Figure 19b. Unity Gain Follower
Pulse Response (Large Signal)
Figure 19c. Unity Gain Follower
Pulse Response (Small Signal)
Figure 20b. Unity Gain Inverter
Pulse Response (Large Signal)
Figure 2Oc. Unity Gain Inverter
Pulse Response (Small Signal)
,....
-v.
Figure 20a. Unity Gain Inverter
OPERA TlONAL AMPLIFIERS 2-59
Applying the AD548
APPLICATION NOTES
The ADS48 is a JFET-input op amp with a guaranteed maximum
IB ofJess than IOpA, and offset and drift laser-trimmed to 0.2SmV
and 2 ....VI"C respectively (ADS48C). AC specs include IMHz
bandwidth, l.8V/....s typical slew rate and 8....s settling time for a
20V step to ± 0.01% - all at a supply current less than 200,....A.
To capitalize on the device's performance, a number of error
sources should be considered.
The minimal power drain and low offset drift of the ADS48
reduce self-heating or "warm-up" effects on input offset voltage,
making the ADS48 ideal for on/off battery powered applications.
The power dissipation due to the ADS48's 200,....A supply current
has a negligible effect on input current, but heavy output loading
will raise the chip temperature. Since a JFET's input current
doubles for every 10·C rise in chip temperature, this can be a
noticeable effect.
The amplifier is designed to be functional with power supply
voltages as low as ± 4.5V. It will exhibit a higher input offset
voltage than at the rated supply voltage of ± 15V, due to power
supply rejection effects. The common-mode range of the ADS48
extends from 3V more positive than the negative supply to I V
more negative than the positive supply. Designed to cleanly
drive up to 10kn and lOOpF loads, the AD548 will drive a 2k!}
load with reduced open loop gain.
OFFSET NULLING
Unlike bipolar input amplifiers, zeroing the input offset voltage
of a BiFET op amp will not minimize offset drift. Using balance
Pins I and 5 to adjust the input offset voltage as shown in Figure
21 will induce an added drift of 0.24 ....VI"C per lOO ....V of nulled
offset. The low initial offset (0.25mV) of the AD548C results in
only 0.6 ....VI"C of additional drift.
+Vs
METAL CAN
MINI-DIP
(jAfi
o!o
0P 9 ~7
1
4
~
""0
6
o-4J
~
0:..
1~
s
~
0:-
Figure 22. Board Layout for Guarding Inputs
INPUT PROTECTION
The AD548 is guaranteed to withstand input voltages equal to
the power supply potential. Exceeding the negative supply voltage
on either input will forward bias the substrate junction of the
chip. The induced current may destroy the amplifier due to
excess heat.
Input protection is required in applications such as a flame
detector in a gas chromatograph, where a very high potential
may be applied to the input terminals during a sensor fault
condition. Figure 23 shows a simple current limiting scheme
that can be used. RPROTECT should be chosen such that the
maximum overload current is l.0rnA (lOOk!} for a lOOV overload,
for example).
Exceeding the negative common-mode range on either input
terminal causes a phase reversal at the output, forcing the amplifier
output to the corresponding high or low state. Exceeding the
negative common-mode on both inputs simultaneously forces
the output high. Exceeding the positive common-mode range on
a single input doesn't cause a phase reversal, but if both inputs
exceed the limit the output will be forced high. In all cases,
normal amplifier operation is resumed when input voltages are
brought back within the common-mode range.
10pF
Figure 21. Offset Null Configuration
LAYOUT
To take full advantage of the AD548's IOpA max input current,
parasitic leakages must be kept below an acceptable level. The
practical limit of the resistance of epoxy or phenolic circuit
board material is berween I x 1Ol2!} and 3 x 1012!}. This can
result in an additional leakage of SpA berween an input of OV
and a -15V supply line. Teflon or a similar low leakage material
(with a resistance exceeding 1017!}) should be used to isolate
high impedance input lines from adjacent lines carrying high
voltages. The insulator should be kept clean, since contaminants
will degrade the surface resistance.
A metal guard completely surrounding the high impedance
nodes and driven by a voltage near the common-mode input
potential can also be used to reduce some parasitic leakages.
The guarding pattern in Figure 22 will reduce parasitic leakage
due to finite board surface resistance; but it will not compensate
for a low volume resistivity board.
2-60 OPERA T10NAL AMPLIFIERS
Rp
= ~ FOR 1 SECONO OR LESS TRANSIENTS
Rp =
1~~"A FOR CONTINUOUS OVERLOAD
Figure 23. Input Protection of IV Converter
D/A CONVERTER OUTPUT BUFFER
The circuit in Figure 24 shows the AD548 and AD7545 12-bit
CMOS D/A converter in a unipolar binary configuration. Vour
will be equal to VREF attenuated by a factor depending on the
digital word. VREF sets the full scale. Overall gain is trimmed
by adjusting RIN• The ADS48's low input offset voltage, low
drift and clean dynamics make it an attractive low power output
buffer.
Application Hints
large signal outputs of the circuit in Figure 24. Upper traces
show the input signal VIN' Lower traces are the resulting output
voltage with the DAC's digital input set to all Is. The AD548
settles to ±0.01% for a 20V input step in 14f.Ls.
Voo
PHOTODIODE PREAMP
The performance of the photodiode preamp shown in Figure 27
is enhanced by the AD548's low input current, input voltage
offset and offset voltage drift. The photodiode sources a current
proportional to the incident light power on its surface. RF converts
the photodiode current to an output voltage equal to RF x Is.
C,
Figure 24. AD548 Used as DAC Output Amplifier
R,
The input offset voltage of the AD548 output amplifier results
in an output error voltage. This error voltage equals the input
offset voltage of the op amp times the noise gain of the amplifier.
That is:
Vos Output = Vos Input ( I +
100Mll
::0)
RFB is the feedback resistor for the op amp, which is internal to
the DAC. Ro is the DAC's R-2R ladder output resistance. The
value of Ro is code dependent. This has the effect of changing
the offset error voltage at the amplifier's output. An output
amplifier with a sub millivolt input offset voltage is needed to
preserve the linearity of the DAC's transfer function.
The AD548 in this configuration provides a 700kHz small signal
bandwidth and l.8V/f.Ls typical slew rate. The 33pF capacitor
across the feedback resistor optimizes the circuit's response.
The oscilloscope photos in Figures 25 and 26 show small and
C SH
20pF
RSH
SOOMI!
PHOTO DIODE
EQUIVALENT CIRCUIT
ADS48 PHQTQ DIODE
PRE AMP
Figure 27.
An error budget illustrating the inIportance of low amplifier
input current, voltage offset and offset voltage drift to mininIize
output voltage errors can be developed by considering the equivalent circuit for the small (0.2mm2 area) photodiode shown in
Figure 27. The input current results in an error proportional to
the feedback resistance used. The amplifier's offset will produce
an error proportional to the preamp's noise gain (I + RFIRSH),
where RSH is the photodiode shunt resistance. The amplifier's
input current will double with every 10°C rise in temperature,
and the photodiode's shunt resistance halves with every 10°C
rise. The error budget in Figure 28 assumes a room temperature
photodiode RSH of 500MO, and the maximum input current
and input offset voltage specs of an AD548C.
TEMP
'c
-25
0
Figure 25. Response to ± 20V p-p Reference Square Wave
+25
+50
+75
+85
RsHIMll) VoslflVI
15.970
150
2,830
200
500
250
88.5
300
15.6
350
7.8
370
II + RFIRsHIVos 1.lpAI
0.30
151flV
2.26
207flV
1000
300flV
56.6
640fl V
26mV
320
5.1mV
640
TOTAL
I.R F
30flV 181flV
262flV 469flV
1.0mV 1.30mV
5.6mV 6.24mV
32m V 34.6mV
64mV 69.1mV
Figure 28. Photo Diode Pre-Amp Errors Over Temperature
The capacitance at the amplifier's negative input (the sum of the
photodiode's shunt capacitance, the op amp's differential input
capacitance, stray capacitance due to wiring, etc.) will cause a
rise in the preamp's noise gain over frequency. This can result
in excess noise over the bandwidth of interest. C F reduces the
noise gain "peaking" at the expense of bandwidth.
Figure 26. Response to ± 100m V p-p Reference Square
Wave
OPERA T10NAL AMPLIFIERS 2-61
INSTRUMENTATION AMPLIFIER
The A054SC's maximum input current of 10pA makes it an
excellent building block for the high input impedance instrumentation amplifier shown in Figure 29. Total current drain
for this circuit is under 600f1A. This configuration is optimal
for conditioning differential voltages from high impedance
sources.
OUTPUT
SENSE
B are developed according to the following familiar diode
equation:
In this equation, k is Boltzmann's constant, T is absolute temperature, q is an electron charge, and I Es is the reverse saturation
current of the logging transistors. The difference of these two
voltages is taken by the subtractor section and scaled by a factor
of approximately 16 by resistors R9, RIO, and RS. Temperature
compensation is provided by resistors RS and R15, which have
a positive 3500 ppmfOC temperature coefficient. The transfer
function for the output voltage is:
VOUT= IV IOglO ChilI)
OUTPUT
REFERENCE
Frequency compensation is provided by Rll, R12, CI, and C2.
Small signal bandwidth is approximately 300kHz at input currents
above IOOf1A and will proportionally decrease with lower signal
levels. 01, 02, R13, and RI4 compensate for the effects of the
two logging transistors' ohmic emitter resistance.
I
FOR EACH AMPLIFIER
\l
FOR EACH AMPLIFIER
PIN7(
PIN4 (
::to
PIN7 <;(---:r"-o-,.-,-O +Vs
O+Vs
nOl. F
PIN4 (
o 11.1-F
To-v,
~O'.' o-v,
H-'~=- Q1,02 == lM394
DUAL LOG TRANSISTORS
I,IN
Figure 29. Low Power Instrumentation Amplifier
The overall gain of the circuit is controlled by R,;, resulting in
the following transfer function:
VOUT
V IN
=
V,IN
R'
'Ok
I + (R I + R z)
R,;
Gains of 1 to 100 can be accommodated with gain nonlinearities
of less than 0.01%. Referred to input errors, which contribute
an output error proportional to in amp gain, include a maximum
untrimmed input offset voltage of 0.5mV and an input offset
voltage drift over temperature of 4f1V;oC. Output errors, which
are independent of gain, will contribute an additional O.SmV
offset and 4f1V;oC drift. The maximum input current is ISpA
over the common-mode range, with a common-mode impedance
of over 1 x 10 120. Resistor pairs R3/RS and R4iR6 should be
ratio matched to 0.01% to take full advantage of the AOS4S's
high common mode rejection. Capacitors CI and CI' compensate
for peaking in the gain over frequency caused by input capacitance
when gains of 1 to 3 are used.
The - 3dB small signal bandwidth for this low power instrumentation amplifier is 700kHz for a gain of I and 10kHz for
a gain of 100. The typical output slew rate is l.SV/f1s.
R'4
499k
SCALE
FACTOR
D2
ADJ
R2
'Ok
R'
V2 1N
143k
VOUT = lV X
VOUT = lV
lOGTO~
x LOG,of,
Dl,D41N4148DIODES
RS, R15 1k + 3500 ppml"C Te RESISTOR
*TEllABQ81 OR PRECISION RESISTOR PT146
ALL OTHER RESISTORS ARE 1% METAL FILM
Figure 30. Log Ratio Amplifier
LOG RATIO AMPLIFIER
Log ratio amplifiers are useful for a variety of signal conditioning
applications, such as linearizing exponential transducer outputs
and compressing analog signals having a wide dynamic range.
The AOS4S's picoamp level input current and low input offset
voltage make it a good choice for the front-end amplifier of the
log ratio circuit shown in Figure 30. This circuit produces an
output voltage equal to the log base 10 of the ratio of the input
currents II and 12 • Resistive inputs RI and R2 are provided for
voltage inputs.
Input currents II and 12 set the collector currents of QI and Q2,
a matched pair of logging transistors. Voltages at points A and
2-62 OPERA TlONAL AMPLIFIERS
To trim this circuit, set the two input currents to IOf1A and
adjust VOUT to zero by adjusting the potentiometer on A3.
Then set 12 to I ",A and adjust the scale factor such that the
output voltage is IV by trimming potentiometer RIO. Offset
adjustment for Al and A2 is provided to increase the accuracy
of the voltage inputs.
This circuit ensures a 1% log conformance error over an input
current range of 300pA to ImA, with low level accuracy limited
by the A054S's input current. The low level input voltage
accuracy of this circuit is limited by the input offset voltage and
drift of the A054S.
Monolithic Electrometer
Operational Amplifier
r'III ANALOG
WDEVICES
A0549* I
ADS49 CONNECTION DIAGRAM
FEATURES
Ultralow Bias Current: 60fA max IAD549L)
2SOfA max IAD549J)
Input Bias Current Guaranteed Over Common-Mode
Voltage Range
Low Offset Voltage: 0.2SmV max IAD549K)
1.00mV max IAD549J)
Low Offset Drift: S....VI"C max IAD549K)
20 ....VI"C max IAD549J)
Low Power: 700 ....A max Supply Current
Low Input Voltage Noise: 4 ....V pop 0.1 to 10Hz
MIL-STD-883B Parts Available
APPUCATIONS
Electrometer Amplifiers
Photodiode Preamp
pH Electrode Buffer
Vacuum Ion Gage Measurement
PRODUCT DESCRIPTION
The ADS49 is a monolithic electrometer operational amplifier
with very low input bias current. Input offset voltage and input
offset voltage drift are laser trimmed for precision performance.
The ADS49's ultralow input current is achieved with "Topgate"
JFET technology, a process development exclusive to Analog
Devices. This technology allows the fabrication of extremely low
input current JFETs compatible with a standard junction-isolated
bipolar process. The 10 150 common-mode impedance, a result
of the bootstrapped input stage, insures that the input current is
essentially independent of common-mode voltage.
The ADS49 is suited for applications requiring very low input
current and low input offset voltage. It excels as a preamp for a
wide variety of current output transducers such as photodiodes,
photomultiplier tubes, or oxygen sensors. The ADS49 can also
be used as a precision integrator or low droop sample and hold.
The ADS49 is pin compatible with standard FET and electrometer
op amps, allowing designers to upgrade the performance of
present systems at little additional cost.
The ADS49 is available in a TO-99 hermetic package. The case
is connected to Pin 8 so that the metal case can be independently
connected to a point at the same potential as the input terminals,
minimizing stray leakage to the case.
GUARD PIN, CONNECTED TO CASE
INVERTING
2
INPUT
v10kn
,
5
~
4 -15V
Vas TRIM
TOP VIEW
The AD549 is available in four performance grades. The J, K,
and L versions are rated over the commercial temperature range
- 0 to + 70DC. The S grade is specified over the military temperature
range of - SSDC to + 12SDC and is available processed to MIL-STD8838, Rev C. Extended reliability PLUS screening is also available.
PLUS screening includes l68-hour burn in, as well as other
environmental and physical tests derived from MIL-STD-8838,
RevC.
PRODUCT HIGHLIGHTS
l. The AD549's input currents are specified, lOO"A> tested and
guaranteed after the device is warmed up. Input current is
guaranteed over the entire common-mode input voltage
range.
2. The ADS49's input offset voltage and drift are laser trinuned
to 0.2SmV and SILVI"C (AD549K), ImV and 20ILVrc
(AD549J).
3. A maximum quiescent supply current of 7001LA minimizes
heating effects on input current and offset voltage.
4. AC specifications include IMHz unity gain bandwidth and
3V/ILs slew rate. Settling time for a lOY input step is SILS
to 0.01%.
S. The ADS49 is an improved replacement for the ADS1S,
OPAI04, and 3S28.
*Covered by Patent No. 4,639,683.
OPERA TIONAL AMPLIFIERS 2-63
SPECIFICATIONS (@+2SOCandVs = %l5Vdc,unlessotheJwisenoled)
Model
Min
ADS49J
Typ
Mal;
150
150
250
250
INPUT BIAS CU~RENTI
Either Input, VCM = OV
Either Input, VCM = ± 10V
Either Input at T max,
VCM=OV
Offset Current
Offset Current at T ....
Min
75
75
0.5
10
32
32
15
Mal;
Min
100
100
0.15
1.0
1.9
20
100
100
2
10
10
15
ADS49L
Typ
40
40
Mal;
Min
ADS49S
Typ
75
75
60
60
Max Units
100
100
0.3
0.3
6
4
90
60
35
35
4
90
60
35
35
nVI Hz
nV/YHz
nVtYHz
nVtYHz
10
10
32
15
0.5
2.0
IS
32
50
mV
mV
.,.VI"C
.,.VN
.,.VN
.,.V/month
0.25
0.4
5
32
32
5
10
10
15
0.5
0.9
10
32
32
fA
fA
pA
fA
pA
420
30
125
2.8
20
0.85
4.2
30
1.3
11
50
2.2
INPUT OFFSET VOLTAGE2
Initial Offset
Offset at T max
v•. Temperature
vs. Supply
vs. Supply, T mm to T max
Long·Term Offset Stability
ADS49K
Typ
INPUT VOLTAGE NOISE
f=O.IHzto 10Hz
f= 10Hz
f= 100Hz
f=lkHz
f= 10kHz
4
90
60
35
35
4
90
60
35
35
INPUT CURRENT NOISE
f=O.IHzto 10Hz
f=lkHz
0.7
0.22
0.5
0.16
0.36
0.11
0.5
0.16
fA! Hz
10 13111
1013 111
10 13111
10 13111
nllpF
10 15110.8
1015110.8
10 15110.8
1015110.8
nllpF
INPUT IMPEDANCE
Differential
VDlFF= ± I
Common Mode
VCM = ±IO
OPEN LOOP GAIN
Vo@±IOV,RL=IOk
Vo@±IOV,RL =lOk,
Tnunto Tmax
Vo= ± IOV,RL=2k
Vo= ± IOV,RL=2k,
TDUntoTmax
INPUT VOLTAGE RANGE
Differential'
Common-Mode Voltage
Common-Mode Rejection Ratio
V=+IOV,-IOV
Tnun to Tmax
OUTPUT CHARACTERISTICS
Voltage@RL= 10k,
Tnun to Tmax
Voltage@RL=2k,
T..,nto Tmax
Short Circuit Current
TnuntoTmax
Load Capacitance Stability
G=+I
FREQUENCY RESPONSE
Unity Gain, Small Signal
Full Power Re.ponse
Slew Rate
SettlingTime,O.I%
0.01%
Overload Recovery,
50% Overdrive, G = - I
POWER SUPPLY
Rated Performance
Operating
Quiescent Currcint
.,.V~
fA~
300
1000
300
1000
300
1000
300
1000
V/mV
300
100
800
250
300
100
800
250
300
100
800
250
300
100
800
250
V/mV
V/mV
80
200
80
200
80
200
25
150
V/mV
±20
+10
-10
80
76
90
80
±20
+10
-10
90
80
100
90
±20
+10
-10
90
80
100
90
±20 V
+10 V
-10
90
80
100
90
dB
dB
-12
+12
-12
+12
-12
+12
-12
+12
V
-10
IS
20
9
+10
35
-10
IS
20
9
+10
35
-10
15
20
9
+10
35
-10
20
15
6
+10
35
V
rnA
4000
4000
0.7
2
1.0
50
3
4.5
5
0.7
2
2
2-64 OPERATIONAL AMPLIFIERS
0.60
0.7
1.0
50
3
4.5
5
2
2
±15
::t5
4000
::t5
0.60
0.7
2
2
±15
::tIS
0.70
1.0
50
3
4.5
5
::t5
0.60
4000
pF
1.0
50
3
4.5
5
MHz
kHz
VI.,..
2
±15
::tIS
0.70
±15
::tIS
0.70
rnA
::t5
0.60
.,..
.,..
.,..
V
::tIS V
0.70 rnA
Min
TEMPERATURE RANGE
Operating, Rated Performance
Storage
PACKAGE OPTION'
TO-99 (H-OSA)
AD549K
AD5491
Model
Typ
0
-65
Max
Min
AD549L
Max
Typ
70
0
+ 150 -65
AD549JH
Min
Typ
Min
Typ
-55
70
+ 150 -65
70
0
+ 150 -65
AD549KH
AD549S
Max
AD549LH
Max
Units
+125 "C
-150 "C
AD549SH
NOTES
IBias current specifications are guaranteed after 5 minutes of operation at TA = + 25°C. BIas current increases by a
factor of 2.3 for every lOoe rise In temperature.
2Input offset voltage speclfictions are guaranteed after 5 minutes of operation at TA = + 25°C.
3Defined as max continuous voltage between the mputs such that neither input exceeds ± lOV from ground.
4See Section 16 for package outline information.
Specifications subject to change without notice.
Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to
calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface
are tested on all production units.
ABSOLUTE MAXIMUM RATINGS'
Supply Voltage . . . . . .
. ±18V
SOOmW
Internal Power Dissipation
. ± 18V2
Input Voltage . . . . . . .
Indefinite
Output Short Circuit Duration
+Vsand -Vs
Differential Input Voltage . . .
-6S"C to + lS0"C
Storage Temperature Range H
OperaTing Temperature Range
o to +70"C
ADS49J, K, L . . . . . . .
- SS"C to + 12S"C
ADS49S . . . . . . . . . . .
Lead Temperature Range (Soldering 60 sec) .. . . . . 300°C
ESD PRECAUTIONS
Charges as high as 4000V readily accumulate on the human
body and test equipment and discharge without detection. Therefore, reasonable ESD precautions are recommended to avoid
functional damage or performance degradation. Unused devices
should be stored in conductive foam or shunts, and the foam
should be discharged to the destination socket before devices are
removed. For further information on ESD precautions, refer to
Analog Devices' ESD Prevention Manual.
NOTES
1Stresses
above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
,
2For supply voltages less than ± 18V, the absolute maximum input voltage is
equal to the supply voltage.
OPERA TlONAL AMPLIFIERS 2-65
•
Hr-----r-----~----~--__,
....,
20
30
R~"'1Ok
__~~
~15
~'Or------t------~~~~-----1
0
,.r_----4_----~r_----+_
>
L
~
7
*
~
/
i
•
•
•
~-v~
IY
O~O------~----~,~O----~,.~----~~
0
10
SUPPLY VoLTAGe
SUPPlY VOLTAGE ::t: V
Figure 1. Input Voltage Range
vs. Supply Voltage
'I.
~ '00 1-----+------r_----4_----~
!
l"'lt==t:====!==~
~
i"OO I---+---+---t-----j
... o!:------:-----~,o=-----7.'.;------H~
SUPPLY VOlTAGE ::t: V
~ 1000
1'00
.
w •• I---~+------r_----+--r_~
I~I-~/_+-~r_-+_+_~
~~,.--~/---,~.----~L------+,~.--L--+~,•
/
§
~
'00
V
'00
•
20
10
15
SUPPLY VOLTAGE ::tV
Figure 6. Open Loop Gain vs.
Supply Voltage
5O,-----r-----,-----,------,
25
..1-----+-----+-----+----.,
20
I ,.
~
i,·~--_b----~===*==~
<3/
!
/
1
.. '0
~40r-----+------f-----+-----i
/'
~
5
IIII
1----+---+---+----.,
20 L-___i.-____..I.-_ _ _..L...____...J
•
•
-'0
WARM-UP TIME Mlnuta
.
30 1-~/'---r-----4--------,r------I
25
'0
-5
0
5
COMMON·MODE VOLTAGE - V
Figure 9. Input Bias Current
vs. Common-Mode Voltage
Figure 8. Change in Offset
Voltage vs. Warm-Up Time
,
50
--
,.
'2'
Figure 7. Open Loop Gain vs.
Temperature
'00k
/'
I
Figure 5. CMRR vs. Input
Common-Mode Voltage
'" 1\
•
36
..
TEMPeRATURE - "C
I
INPUT COMMON·MODE VOLTAGE _ V
1\
1k
10k
LOAD RESISTANCE _ n
3000
!
r--- ...........
100
Figure 3. Output Voltage
Swing vs. Resistive Load
,~r-----_r------r-----_r----_,
3000
- 25
V
•'0
zo
."': 1101-----+------1-----+----_1
i
Figure 4. Quiescent Current
vs. Supply Voltage
'00-55
v
I
Figure 2. Output Voltage
Swing vs. Supply Voltage
~,-----~----~----,-----,
-
::t:
1&
Vs" ::t1& VOLTS
lOOk
WHENEVER JOHNSON NOISE IS GREATER THAN
AMPUFtER NOISE. AMPLIFIER NeMSE CAN BE
CONSIDERED NEGLIGIBLE FOR THE APPlICAllON
,1M<
45
-;
lkHzBAN~~
/'
--
RESISTOR J~N NOIS
20
10
1S
POWER SUPPLY VOLTAGE :tV
20
20
Figure 10. Input Bias Current
vs. Supply Voltage
2-66 OPERATIONAL AMPLIFIERS
,.
100
1k
fREQUENCY - Hz
.
,
,
r-.....
o
/
./
.. '
L
.." It, "/V/
~
V
,.;~
"" "'-
25
,,'
",,'
'Ok
Figure 11. Input Voltage Noise
Spectral Density
lOOk
101
r"
AMPLljRGENE !ATEDNT"E
1M
10M
100M
1G
SOURCE RESISTANCE - II
BAN,DWIDTH
100
1000
Figure 12. Noise vs. Source
Resistance
,
"-
,
~
.
~
"-
I""
:520
g
,
L\
0
.
"" ""
4
\
"" "" ""-.
,
\
Z
~
h
\
i\
1\
L
lk
"" ""
10k
FREOUENCV - H2
Figure 13. Open Loop
Frequency Response
I""
r---
""
Figure 15. CMRR vs.
Frequency
Figure 14. Large Signal
Frequency Response
'i'-,
""
.........
I",
--SUPPLY
,
I"" ~'I'
~+SUPPlY
i'-,
1k
10k
lOOk
FREQUENCY _ Hz
Figure 16. PSRR vs.
Frequency
Figure 18. Unity Gain
Follower
-"!;-.-----!--+'--3~-+"="'!
SETTLING TIME - 11$
Figure 17. Output Settling
Time vs. Output Swing and
Error Voltage
Figure 19. Unity Gain Follower
Large Signal Pulse Response
Figure 20. Unity Gain Follower
Small Signal Pulse Response
Figure 22. Unity Gain Inverter
Large Signal Pulse Response
Figure 23. Unity Gain Inverter
Small Signal Pulse Response
10kU
10k!!
V'.C>-'w..~-{
SQUARE
WAVE
INPUT
-v,
Figure 21. Unity Gain Inverter
OPERATIONAL AMPLIFIERS 2-67
MINIMIZING INPUT CURRENT
The AD549 has been optimized for low input current and offset
voltage. Careful attention to how the amplifier is used will reduce
input currents in actual applications.
c,
R,
The amplifier operating temperature should be kept as low as
possible to minimize input current. Like other JFET input
amplifiers, the AD549's input current is sensitive to chip temperature, rising by a factor of 2.3 for every 10°C rise. This is
illustrated in Figure 24, a plot of AD549 input current versus
ambient temperature.
+
I
~c.
l=C
lOOpA
'OpA
/
lpA
IDOlA
--- --
lOlA
V
1/
/
,...-~
1IA
~55
-25
5
35
TEMPERATURE
65
125
95
~"C
Figure 24. AD549 Input Bias Current
Temperature
VS.
Ambient
On-chip power dissipation will raise chip operating temperature
causing an increase in input bias current. Due to the AD549's
low quiescent supply current, chip temperature when the (unloaded) amplifier is operated with 15V supplies, is less than
3°C higher than ambient. The difference in input current is
negligible.
However, heavy output loads can cause a significant increase in
chip temperature and a corresponding increase in input current.
Maintaining a minimum load resistance of 10kO is recommended.
Input current versus additional power dissipation due to output
drive current is plotted in Figure 25.
Figure 26. Sources of Parasitic Leakage Currents
Finite resistance from input lines to voltages on the board,
modeled by resistor R p , results in parasitic leakage. Insulation
resistance of over 10 15 0 must be maintained between the amplifier's signal and supply lines in order to capitalize on the AD549's
low input currents. Standard PC board material does not have
high enough insulation resistance. Therefore, the AD549's input
leads should be connected to standoffs made of insulating material
with adequate volume resistivity (e.g., Teflon*). The surface of
the insulator's surface must be kept clean in order to preserve
surface resistivity. For Teflon, an effective cleaning procedure
consists of swabbing the surface with high-grade isopropyl alcohol,
rinsing with deionized water, and baking the board at 80°C for
10 minutes.
In addition to high volume and surface resistivity, other properties
are desirable in the insulating material chosen. Resistance to
water absorption is important since surface water ftIms drastically
reduce surface resistivity. The insulator chosen should also
exhibit minimal piezoelectric effects (charge emission due to
mechanical stress) and triboelectric effects (charge generated by
friction). Charge imbalances generated by these mechanisms can
appear as parasitic leakage currents. These effects are modeled
by variable capacitor Cp in Fignre 26. The table in Figure 27
lists various insulators and their properties. 1
60
~
~ 50
a
BAseb ON
'"~ 40
!
/
TYPICAL Is == 40fA
~
~
~
30
/
~~ 20
o
Z
10
o
-
25
Material
Teflon
Kel-F**
Sapphire
Polyethylene
Polystyrene
1/
Ceramic
Glass Epoxy
PVC
Phenolic
r--' V
50
75
100
125
150
175
200
ADDITIONAL INTERNAL POWER DISSIPATION - mW
Figure 25. AD549 Input Bias Current vs. Additional Power
Dissipation
CIRCUIT BOARD NOTES
There are a number of physical phenomena that generate spurious
currents that degrade the accuracy of low current measurements.
Figure 26 is a schematic of an I-to-V converter with these parasitic
currents modeled.
2-68 OPERA TIONAL AMPLIFIERS
Volume
Resistivity
In-CM)
10 '7 _10 18
1017 _10 '8
10 '6 _10 '8
10'4 _10 '8
1012 _10 '8
10'2 _10 '4
10' °_10
10'°_10 '5
1OS_10'2
'7
Minimal
Triboelectric
Effects
W
W
M
M
W
W
W
Minimal
Piezoelectric
Resistance
to Water
Effects
W
M
Absorption
G
G
G
M
M
M
M
W
G
G
G
G
M
M
W
W
G
W
G - Good with Regard to Property
M - Moderate with Regard to Property
W - Weak with Regard to Property
Figure 27. Insulating Materials and Characteristics
IElectrometer Measurements, pp. 15-17, Keithley Instruments, Inc.,
Cleveland, Ohio, 1977.
*Teflon is a registered trademark of E.!. du Pont Co.
**Kel-F is a registered,trademark of 3-M Company.
Guarding the input lines by completely surrounding them with
a metal conductor biased near the input lines' potential has two
major benefits. First, parasitic le3kage from the signal line is
reduced since the voltage between the input line and the guard
is very low. Second, stray capacitance at the input node is
minimized. Input capacitance can substantially degrade signal
bandwidth and the stability of the I-to-V converter. The case of
the AD549 is connected to Pin 8 so that it can be bootstrapped
near the input potential. This minimizes pin leakage and input
common-mode capacitance due to the case. Guard schemes for
inverting and noninverting amplifier topologies are illustrated in
Figures 28 and 29.
c,
referenced to the power supplies in series with the amplifier's
positive input terminal. The amplifier's input offset voltage drift
with temperature is not affected. However, variation of the
power supply voitages will cause offset shifts.
R,
v,
i
+Vs
499.
VOUT
~-
Figure 31. Alternate Offset Null Circuit for Inverter
Figure 28. Inverting Amplifier with Guard
}-.---o+
V OUT
Vs
R,
R,
Figure 29. Noninverting Amplifier with Guard
Other guidelines include keeping the circuit layout as compact
as possible and input lines short. Keeping the assembly rigid
and minimizing sources of vibration will reduce triboelectric and
piezoelectric effects. All precision high impedance circuitry
requires shielding against interference noise. Low noise coax or
triax cables should be used for remote connections to the input
signal lines.
OFFSET NULLING
The AD549's input offset voltage can be nulled by using balance
Pins I and 5, as shown in Figure 30. Nulling the input offset
voltage in this fashion will introduce an added input offset voltage
drift component of 2.411vrc per millivolt of nulled offset (a
maximum additional drift of 0.611vrc for the AD549K, 1.211vrc
for the AD549L, 2.4I1VrC for the AD549J).
AC RESPONSE WITH HIGH VALUE SOURCE AND
FEEDBACK RESISTANCE
Source and feedback resistances greater than 100kn will magnify
the effect of input capacitances (stray and inherent to the AD549)
on the ac behavior of the circuit. The effects of common mode
and differential input capacitances should be taken into account
since the circuit's bandwidth and stability can be adversely
affected.
In a follower, the source resistance and input common-mode
capacitance form a pole that limits the bandwidth to 1I21T RsC s .
Bootstrapping the metal case by connecting Pin 8 to the output
minimizes capacitance due to the package. Figures 32 and 33
show the follower pulse response from a IMn source resistance
with and without the package connected to the output. Typical'
common-mode input capacitance for the AD549 is 0.8pF.
In an inverting configuration, the differential input capacitance
forms a pole in the circuit's loop transmission. This can create
peaking in the ac response and possible instability. A feedback
capacitance can be used to stabilize the circuit. The inverter
pulse response with RF and Rs equal to IMn appears in Figure
34. Figure 35 shows the response of the same circuit with a IpF
feedback capacitance. Typical differential input capacitance for
the AD549 is IpF.
+Vs
+
V OUT
~-Vs
Figure 30. Standard Offset Null Circuit
The approach in Figure 31 can be used when the amplifier is
used as an inverter. This method introduces a small voltage
Figure 33. Follower Pulse Response from 1 Mll Source
Resistance, Case Bootstrapped
OPERA TIONAL AMPLIFIERS 2-69
•
INPUT PROTECTION
The ADS49 safely handles any input voltage within the supply
voltage range. Subjecting the input terminals to voltages beyond
the power supply can destroy the device or cause shifts in input
current or offset voltage if the amplifier is not protected.
Figure 34. Inverter Pulse Response with 1 Mll Source and
Feedback Resistance
A protection scheme for the amplifier as an inverter is shown in
Figure 37. Rp is chosen to limit the current through the inverting
input to lmA for expected transient (less than 1 second) overvoltage
conditions, or to lOOJLA for a continuous overload. Since Rp is
inside the feedback loop, and is much lower in value than the
amplifier's input resistance, it does not affect the inverter's DC
gain. However, the Johnson noise of the resistor will add root
sum of squares to the amplifier's input noise.
R,
Figure 35. Inverter Pulse Response with 1 Mll Source and
Feedback Resistance, 1pF Feedback Capacitance
Figure 37. Inverter with Input Current Limit
COMMON-MODE INPUT VOLTAGE OVERLOAD
The rated common-mode input voltage range of the ADS49 is
from 3V less than the positive supply voltage to SV greater than
the negative supply voltage. Exceeding this range will degrade
the amplifier's eMRR. Driving the common-mode voltage above
the positive supply will cause the amplifier's output to saturate
at the upper limit of output voltage. Recovery time is typically
2JLs after the input has been returned to within the normal
operating range. Driving the input common-mode voltage within
I V of the negative supply causes phase reversal of the output
signal. In this case, normal operation is typically resumed within
O.5JLS of the input voltage returning within range.
In the corresponding version of this scheme for a follower,
shown in Figure 38, Rp and the capacitance at the positive
input terminal will produce a pole in the signal frequency response
at a f= 1/2".RC. Again, the Johnson noise Rp will add to the
amplifier's input voltage noise.
RPIIOTECT
r---,
I
I
DIFFERENTIAL INPUT VOLTAGE OVERLOAD
A plot of the ADS49's input currents versus differential input
voltage (defmed as VIN + - VIN - ) appears in Figure 36. The
input current at either terminal stays below a few hundred
femtoamps until one input terminal is forced higher than I to
I.SV above the other terminal. Under these conditions, the
input current limits at 30JLA.
100/J.
~"J
10.
1.
~
100n
I
10n
~
~
:>
(J
5
~
W-
I
IIN+
Figure 38. Follower with Input Current Limit
Figure 39 is a schematic of the ADS49 as an inverter with an
input voltage clamp. Bootstrapping the clamp diodes at the
inverting input minimizes the voltage across the clamps and
keeps the leakage due to the diodes low. Low leakage diodes,
such as the FD333's should be used, and should be shielded
from light to keep photocurrents from being generated. Even
with these precautions, the diodes will measurably increase the
input current and capacitance.
11'
lOOp
,Op
'.
1001
101
-5 -4
-3
-2
-1
0
1
2
3
4
5
DIFFERENnAL INPUT VOLTAGE - V
IVIN - - V1N-1
Figure 36. Input Current vs. Differential Input Voltage
2-70 OPERATIONAL AMPLIFIERS
Figure 39. Input Voltage Clamp with Diodes
SAMPLE AND DIFFERENCE CIRCUIT TO MEASURE
ELECTROMETER LEAKAGE CURRENTS
There are a number of methods used to test electrometer leakage
currents, including current integration and direct current to
voltage conversion. Regardless of the method used, board and
interconnect cleanliness, proper choice of insulating materials
(such as Teflon or Kel-F), correct guarding and shielding techniques and care in physical layout are essential to making accurate
leakage measurements.
Figure 40 is a schematic of the sample and difference circuit. It
uses two AD549 electrometer amplifiers (A and B) as current to
voltage converters with high value (10100) sense resistors (RSa
and RSb). RI and R2 provide for an overall circuit sensitivity of
10fA/mV (IOpA full scale). Cc and CF provide noise suppression
and loop compensation. Cc should be a low-leakage polystyrene
capacitor. An ultralow-leakage Kel-F test socket is used for
contacting the device under test. Rigid Teflon coaxial cable is
used to make connections to all high impedance nodes. The use
of rigid coax affords immunity to error induced by mechanical
vibration and provides an outer conductor for shielding. The
entire circuit is enclosed in a grounded metal box.
C,
20pF
VERR1 = 10 (VosA - IBA x RSa)
VERR2 = 10 (VosB - IBBxRSb)
Once measured, these errors are subtracted from the readings
taken with a device under test present. Amplifier B closes the
feedback loop to the device under test, in addition to providing
current to voltage conversion. The offset error of the device
under test appears as a common-mode signal and does not affect
the test measurement. As a result, only the leakage current of
the device under test is measured.
VA - VERR1 = 10[RSa x IB( + ))
Vx - VERR2 = 10[RSb x IB ( - ) )
Although a series of devices can be tested after only one calibration
measurement, calibration should be updated periodically to
compensate for any thermal drift of the current to voltage converters or changes in the ambient environment. Laboratory
results have shown that repeatable measurements within IOfA
can be realized when this apparatus is properly implemented.
These results are achieved in part by the design of the circuit,
which eliminates relays and other parasitic leakage paths in the
high impedance signal lines, and in part by the inherent cancellation
of errors through the calibration and measurement procedure.
PHOTODIODE INTERFACE
The AD549's low input current and low input offset voltage
make it an excellent choice for very sensitive photodiode preamps
(Figure 41). The photodiode develops a signal current, Is equal
to:
r-- - ----I
I
I
I
I
I
I
Is=RxP
CAUTEST
r--- --
+
I
I
I
I
VERR1IV A
where P is light power incident on the diode's surface in Watts
and R is the photodiode responsivity in AmpsIW att. RF converts
the signal current to an output voltage:
VOUT =
I
RF
X
Is
~
L __
V OUT
>--+----~~----~
r
I
I
VERR2Nx
I
'Ok
~+
I
I
I
I
I
I
'"F~ ~u,
I
I
'"---
+
----Figure 41. Photodiode Preamp
Figure 40. Sample and Difference Circuit for Measuring
Electrometer Leakage Currents
The test apparatus is calibrated without a device under test
present. A five minute stabilization period after the power is
turned on is required. First, VERR1 and VERR2 are measured.
These voltages are the errors caused by offset voltages and leakage
currents of the current to voltage converters.
DC error sources and an equivalent circuit for a small area
(0.2mm square) photodiode are indicated in Figure 42.
Input current, I B, will contribute an output voltage error, VE!>
proportional to the feedback resistance:
VEl =
IB
X
RF
The op amp's input voltage offset will cause an error current
through the photodiode's shunt resistance, Rs:
I = Vos/Rs
OPERA TIONAL AMPLIFIERS 2-71
10.
IF AND t.§., NO FILTER
C,
\
10pF
IFAN/li' Ti lir"
.lJ~D~~11I
\
OPEN LOOP GAIN
II
IIII
..' CbN~~iJuTlON,
EN
\
NO FilTER
CONTRIBUTION
\
WITH FILTER
Figure 42. Photodiode Preamp DC Error Sources
\
10n
1
The error current will result in an error voltage (VEl) at the
amplifier's output equal to:
VE2 = (l+RFRs) Vos
Given typical values of photodiode shunt resistance (on the
order of 109 0.), RFlRs can easily be greater than one, especially
if a large feedback resistance is used. Also, RFIRS will increase
with temperature, as photodiode shunt resistance typically drops
by a factor of two for every 10°C rise in temperature. An op
amp with low offset voltage and low drift must be used in order
to maintain accuracy. The AD549K offers guaranteed maximum
0.25mV offset voltage, and 5f.LV;oC drift for very sensitive
applications.
Photodiode Preamp Noise
Noise limits the signal resolution obtainable with the preamp.
The output voltage noise divided by the feedback resistance is
the minimum current signal that can be detected. This minimum
detectable current divided by the responsivity of the photodiode
represents the lowest light power that can be detected by the
preamp.
Noise sources associated with the photodiode, amplifier, and
feedback resistance are shown in Figure 43; Figure 44 is the
spectral density versus frequency plot of each of the noise source's
contribution to the output voltage noise (circuit parameters in
Figure 42 are assumed). Each noise source's rms contribution to
the total output voltage noise is obtained by integrating the
square of its spectral density function over frequency. The rms
value of the output voltage noise is the square root of the sum
of all contributions. Minimizing the total area under these curves
will optimize the preamplifier's resolution for a given
bandwidth.
.
10
100
1k
10k
FREQUENCY IN Hz
100k
1M
Figure 44. Photodiode Preamp Noise Sources' Spectral
Density VS, Frequency
The photodiode preamp in Figure 41 can detect a signal current
of 26fA rms at a bandwidth of 16Hz, which assuming a photodiode
responsivity of O.5AIW, translates to a 52fW rms minimum
detectable power. The photodiode used has a high source resistance
and low junction capacitance. C F sets the signal bandwidth with
RF and also limits the "peak" in the noise gain that multiplies
the op amp's input voltage noise contribution. A single pole
filter at the amplifier's output limits the op amp's output voltage
noise bandwidth to 26Hz, a frequency comparable to the signal
bandwidth. This greatly improves the preamplifier's signal to
noise ratio (in this case, by a factor of three).
Log Ratio Amplifier
Logarithmic ratio circuits are useful for processing signals with
wide dynamic range. The AD549L's 60fA maximum input
current makes it possible to build a log ratio amplifier with 1%
log conformance for input current ranging from 10pA to lmA, a
dynamic range of 160dB. The useful resolution of the log amplifier
extends down to 100fA, for a total dynamic range of 10 decades
or 200dB.
The log ratio amplifier in Figure 45 provides an output voltage
proportional to the log base 10 of the ratio of the input currents
II and 12. Resistors RI and R2 are provided for voltage inputs.
Since NPN devices are used in the feedback loop of the front -end
amplifiers that provide the log transfer function, the output is
valid only for positive input voltages and input currents. The
input currents set the collector currents ICI and IC2 of a matched
pair of log transistors Q I and Q2 to develop voltages VA and
VB:
VA, B = - (kT/q) In IC/lES
where IES is the transistors' saturation current.
c,
The difference of VA and VB is taken by the subtractor section
to obtain:
VC = (kT/q) In (IC2/ICI)
VC is scaled up by the ratio of (R9 + RIO)1R8, which is equal
to approximately 16 at room temperature, resulting in the output
voltage:
VOUT = I x log(IC2/ICI) V.
Figure 43. Photodiode Preamp Noise Sources
2-72 OPERA TIONAL AMPLIFIERS
R8 is a resistor with a positive 3500ppml°C temperature coefficient
to provide the necessary temperature compensation. The parallel
combination of RI5 and R7 is provided to keep the subtractor
section's gain for positive and negative inputs matched over
temperature.
Frequency compensation is provided by Rll, R12, and Cl and
C2. The bandwidth of the circuit is 300kHz at input signals
greater than sOJ-LA, and decreases smoothly with decreasing
signal levels.
To trim the circuit, set the input currents to lOJ-LA and trim
A3's offset using the amplifier's trim potentiometer so the output
equals O. Then set 11 to IJ-LA and adjust the output to equal IV
by trimming RIO. Additional offset trims on the amplifiers Al
and A2 can be used to increase the voltage input accuracy and
dynamic range.
The very low input current of the ADs49 makes this circuit
useful over a very wide range of signal currents. The total input
current (which determines the low-level accuracy of the circuit)
is the sum of the amplifier input current, the leakage across the
compensating capacitor (negligible if polystyrene or Teflon
capacitor is used), and the collector to collector, and collector to
base leakages of one side of the dual log transistors. The magnitude
of these last two leakages depend on the amplifier's input offset
voltage and are typically less than lOfA with 1mV offsets. The
low-level accuracy is limited primarily by the amplifier's input
current, ouly 60fA maximum when the ADs49L is used.
TEMPERATURE COMPENSATED pH PROBE
AMPLIFIER
A pH probe can be modeled as a mY-level voltage source with a
series source resistance dependent upon the electrode's composition and configuration. The glass bulb resistance of a typical pH
electrode pair falls between 106 and 109 0. It is therefore important
to select an amplifier with low enough input currents such that
the voltage drop produced by the amplifier's input bias current
and the electrode resistance does not become an appreciable
percentage of a pH unit.
The circuit in Figure 46 illustrates the use of the ADs49 as a
pH probe amplifier. As with other electrometer applications, the
use of guarding, shielding, Teflon standoffs, etc., is a must in
order to capitalize on the ADs49's low input current. If an
ADs49L (60fA max input current) is used, the error contributed
by input current will be held below 60J-LV for pH electrode
source impedances up to 1090. Input offset voltage (which can
be trimmed) will be below O.smV.
+15V
The effects of the emitter resistance of Q 1 and Q2 can degrade
the circuit's accuracy at input currents above IOOJ-LA. The networks
composed of R13, Dl, R16, and R14, D2, Rl7 compensate for
these errors, so that this circuit has less than I % log conformance
error at lmA input currents. The correct value for R13 and Rl4
depends on the type of log transistors used. 49.9kO resistors
were chosen for use with LM394 transistors. Smaller resistance
values will be needed for smaller log transistors.
FOR EACH AMPLIFIER
PIN7 oE('--~I'-o-'.-F-OO +Vs
PIN4
E
~01.F o-v,
Figure 46. Temperature Compensated pH Probe Amplifier
!,IN
SCALE
FACTOR
ADJ
02
..
.2
10k
'43k
LOG1~i
VOUl:
lV x
VOUl
lV X lOG10~
'"
01,041N4148DIQDES
RS, R151k + 3500ppmloCTCRESISTOR
*TElLAB 081 OR PRECISION RESISTOR PT146
ALL OTHER RESISTORS ARE 1% METAL FILM
Figure 45. Log Ratio Amplifier
The pH probe output is ideally zero volts at a pH of 7 independent
of temperature. The slope of the probe's transfer function,
though predictable, is temperature dependent (- s4.2mVlpH at
oand -74.04mV/pH at 100°C). By using an ADs90 temperature
sensor and an ADS 35 analog divider, an accurate temperature
compensation network can be added to the basic pH probe
amplifier. The table in Figure 47 shows voltages at various
points and illustrates the compensation. The ADs49 is set for a
noninverting gain of 13.51. The output of the ADs90 circuitry
(point C) will be equal to 10V at 100°C and decrease by 26.8mV/
°C. The output of the ADs3s analog divider (point D) will be a
temperature compensated output voltage centered at zero volts
for a pH of 7, and having a transfer function of -1.00V/pH
unit. The output range spans from - 7.00V (pH = 14) to + 7.00V
(pH=O).
PROBE
TEMP
0
25'C
3rC
60'C
100'C
A
(PROBE OUTPUT)
54.20mV
59.16mV
61.54mV
66.10mV
74.04mV
B
(Ax 13.51)
O.732V
O.799V
O.831V
O.893V
1.000V
C
(590 OUTPUT)
7.32V
7.99V
8.31V
8.93V
10.00V
0
(lOB/C)
1.00V
1.00V
1.00V
1.00V
1.00V
Figure 47. Table Illustrating Temperature Compensation
OPERATIONAL AMPLIFIERS 2-73
2-74 OPERATIONAL AMPLIFIERS
Precision Low-Cost
Dual. BiFET Op Amp
AD642 I
1IIIIIIII ANALOG
WDEVICES
FEATURES
Matched Offset Voltage
Matched Offset Voltage Over Temperature
Matched Bias Current
Crosstalk-124dB at 1kHz
Low Bias Current: 35pA max Warmed Up
Low Offset Voltage: 500pV max
Low Input Voltage Noise: 2I'V pop
High Open Loop Gain
Low Quiescent Current: 2.8mA max
Low Total Harmonic Distortion
Standard Dual Amplifier Pin Out
AD642 PIN CONFIGURATION
INVERTING
INPUT
INVERTING
INPUT
VPIN 4 IS IN ELECTRICAL
CONTACT WITH THE CASE
TOP VIEW
PRODUCT DESCRIPTION
The AD642 is a pair of matched high-speed monolithic BiFET operational amplifier fabricated with the most advanced
bipolar, JFET and laser trimming technologies. The AD642
offers matched bias currents that are significandy lower than
currently available monolithic dual FET input operational
amplifiers: 3SpA max matched to 2SpA for the AD642K
and L; 7SpA max, matched to 3SpA for the AD642J and S.
In addition, the offset voltage is laser trimmed to less than
O.SmV and matched to O.2SmV for the AD642L, I.OmV and
matched to O.SmV for the AD642K, utilizing Analog's laserwafer trimming (Lwr) process.
The tight matching and temperature tracking between the
operational amplifiers is achieved by ion-implanted JFETs
and laser-wafer trimming. Ion-implantation permits the fabrication of precision, matched JFETs on a monolithic bipolar
chip. This optimizes the process to product matched bias
currents which have lower initial bias currents than other
popular BiFET op amps. Laser-wafer trimming each amplifier's input offset voltage assures tight initial match and
combined with superior Ie processing guarantees offset voltage tracking over the temperature range.
The AD642 is recommended for applications in which excellent ac and dc performance is required. The matched amplifiers provide a low-cost solution for true instrumentation
amplifiers, log ratio amplifiers, and output amplifiers for four
quadrant multiplying D/A converters such as the AD7S41.
The AD642 is available in three versions: the "}", "K" and
"L", all specified over the 0 to +70o e temperature range and
one version, "S", over the -ssoe to +12S o e extented operating temperature range. All devices are packaged in the
hermetically-sealed, TO-99 metal can.
PRODUCT HIGHLIGHTS
1. The AD642 has tight matching specifications to ensure
high performance, eliminating the need to match individual devices.
2. Analog Devices, unlike some manufacturers, specifies each
device for the maximum bias current at either input in the
warmed-up condition, thus assuring the user that the
AD642 will meet its published specifications in actual use.
3. Laser-wafer-trimming reduces offset voltage to as low as
O.SmV max and matched side to side toO.2SmV (AD642L),
thus eliminating the need for external nulling.
4. Low voltage noise (2[J.V, pop), and high open loop gain
enhance the AD642's performance as a precision op amp.
S. The standard dual amplifier pin out allows the AD642 to
replace lower performance duals without redesign.
6. The AD642 is available in chip form.
OPERA TIONAL AMPLIFIERS 2-75
•
SPECIFICATIONS
(@ +25"& and Vs= :!:15V de)
AD642K
AD642J
Model
Min
OPEN LOOP GAIN
Vo "" ::!:lOV,R L ;?:2kfl
Tmm to T max, R L =2kO
100,000
100,000
OUTPUT CHARACTERISTICS
Voltage ((I Rr. = 2kH, T m~n to T max
±10
Voltage ((/ RL = lOkfl, T mm to T max
Typ
Min
Typ
AD642L
Min
Max
250,000
250,000
2.0
AD642S
Max
Min
10
50
30
2.0
Typ
Max
250,000
100,000
±IO
±12
= 12
= 13
25
±12
10
50
3.0
Typ
250,000
250,000
±10
= 12
= 13
25
±12
Short C1rcUit Current
FREQUENCY RESPONSE
Uony Gam Small Signal
Full Power Response
Slew Rate, Dotty Gam
Max
VN
VN
25
= 12
=13
25
V
V
mA
10
50
30
10
50
3.0
MHz
kHz
V/..,.,s
= 12
±IO
±12
::!:l3
2.0
Units
2.0
INPUTOFFSETVOLTAGE'
ImualOffset
InpUl Offset Voltage T mIn to T max
Input Offset Voltage vs Supply,
Tmm10Tmax
2.0
35
1.0
2.0
0.5
1.0
1.0
3.5
mV
mV
200
100
100
100
.VN
35
pA
pA
0.5
3.5
35
INPUT BIAS CURRENT'
10
5
Either Input
Offset Current
MATCHING CHARACTERISTICS'
Input Offset Voltage
InpUl Offset Voltage T mm to T max
10
2
75
10
2
35
10
2
-124
-124
-124
-124
mV
mV
pA
dB
10"116
10"116
10"116
10"116
10"116
10"116
10"116
10"116
MllllpF
MllllpF
=20
= 12
V
V
dB
1.0
35
35
Input Blas Current
Crosstalk
35
0.5
2.0
25
0.25
1.0
25
INPUTIMPEDANCE
Dtfferentlal
Common Mode
INPUT VOLTAGE RANGE
Differeotlal4
Common Mode
Common Mode Rejection
=20
= 12
±lO
=20
= 12
±10
SO
76
=20
= 12
±lO
±10
SO
SO
INPUT NOISE
2
70
45
30
25
VoltageO IHzto 10Hz
f= 10Hz
f" 100Hz
f= 1kHz
f= 10kHz
2
70
45
30
25
2
70
45
30
25
2
70
45
30
25
/-lVp-p
nV/Vfu
nV/\/Hz
nVI\'Hz
nV/\'Hz
POWER SUPPLY
Rated Performance
Operating
QUiescent Current
=5
= 15
2.S
=5
= 15
2.S
V
V
mA
0
+ 70
+ 150
- 55
65
+ 125
+ ISO
'C
'C
= 15
= 15
= 18
2.S
=5
= 15
'" IS
=15
2.S
=5
TEMPERATURE RANGE
OperalJOg, Rated Performance
Storage
PACKAGE OPTION'
TO·99 Style (H-OSBJ
,70
ISO
0
65
0
t
65
t
!
70
ISO
65
AD642KH
AD642JH
AD642LH
AD642SH
NOTES
JInput Offset Voltage speclficatlons are guaranteed after 5 mlnute~
of operation at T A '-" + 25°C
2Blas Current specifications are guaranteed at maximum al either
Input after 5 minutes of operatlon at T A
+ 2S"C For
higher temperatures, the current double~ every 1O"C
3Matching IS defined as the difference between parameter~ of
the two amphfiers
~Defined a~
the maximum ~afe voltage between mput~, ~uch that
neither exceed~ + IOV from ground
Section 16 for package outline mformatlOn
~See
Speclficat1on~ ~ublect
10 change without notice
SpeclficatJom l>hown In holdface are te~ted on all productIOn umh at final
electrical teM Rel>ulh from thof>e te~h are uf>ed 10 calculate outgoing quality
levell> All mm and max l>peclficatJom are guaranteed, although only tho~e
l>hown In boldlace arc te~ted on all production UnJt~.
METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm)
~-----------------~~~--------------------------~
V.
8
6
~INPUT
2
5 +!NPUT 2
OUTPUT 1
2-76 OPERATIONAL AMPLIFIERS
v-
OUTPUT 2
Typical Characteristics
..
20
»r-----~----,-----~----~
v~
,.r_----~----~------~~--_4
•
~
,
~,or-----~----~,,~~+------4
i
I)
•
~----~-----f.,O.-----f.,.---~~
,.
SUPPLY VOLTAGE - tV
SUPPLV VOLTAGE - J:V
•
,.
0
~
V
,.
i,...--
,.
100
Figure 1. Input Voltage Range VB.
Supply Voltage
Figure 2. Output Voltage Swing va.
Supply Voltage
•.• ,-------.------,-------r-------,
20
,,...
".K. L
11'6
,
~
ffi 20r_--~~----~------+_----_4
~
M
~
~
~ 10r_----4------+------+-----~
!!!
i
,.
,.
~
~
10
~
~
«
i
/v
~
V
~
,.
,.
20
20
/
/
il
:fI
ii
!5 ~~------------~------~--~
20
f'.
r--':~~==
MARGIN
•
,.
jTHNOILOAD
-20
'00
'k
•
+80'
z
\
\
~
~
... '"
'20
~
!g 100
,
~
~g
·20
'OM
'20
,00
'25
va.
\Is = t.15Y WITH
I":
2O'e
90
1
~
l~ppLY
20
,.
SUPPLY VOLTAGE - tV
Figure 1.1. Open Loop Voltage
Gain va. Supply Voltage
20
,•
10
" '"
>--
+SUPPLY _
•
,.
55
•
V
..
25
-25
............ .......
Figure 9. Open Loop Gain
Temperature
RL=2kn
eo.
..........
1V p-pSINE WAVE
70
1M
............
TEMPERATURE _ °C
j.--
Z
f'-
Figure 10. Open Loop Frequency
Response
·56
11
11
\
10k
100k
FREQUENCY - Hz
............
••
'20
1',
f'.
,.
,.
Figure B. Input Offset Voltage Tum
On Drift VB. Time
...."
..
20
WARM·up TIME - MinUtes
"00
"
/
I
COMMON MODE VOLTAGE - V
Figure 7. Input Bias Current va.
CMV
70
°c
2.
•
~~O------------~------------+-J,.
.
RLI ...
~r_------------r_----------~
so
·25
Figure 6. Input Bias Current va.
Temperature
~i-'"
f'.
...
.1/
s,'
30
80
f---
loA
,/
k:
/
-- --- .........
TEMPERATURE _
'00
1.
'00
J~
lC10pA
Figure 5. Input Bias Current va.
Supply Voltage
7.,-------------T""'------------,
,
lnA
POWER SUPPLY VOLTAGE -tV
Figure 4. Quiescent Current va.
Supply Voltage
l
\Is _t , 5V
UlnA
'....
SUPPL V VOLTAGE - !Volb
I
-- •
ii
•
n
Figure 3. Output Voltage Swing va.
Resistive Load
'00""
30
,Ok
LOAD f'ESISTANCE -
~,
~
FREauENCY • lkHr:
%16 VOLT SUPPLIES
100
,.
''" "
'"
10k
tOOk
FREQUENCY - Hz
1M
'OM
Figure 12. Power Supply Rejection
va. Frequency
OPERATIONAL AMPLIFIERS 2-77
- - - - - -_. - - . - - ..-
30
11 0
Vs .. .t15V
VCM = 1V pop +25~C
'00
80
"'" ~
0
0
25'C
VS"'i15V
RL"'2k
~
0
'0
'00
,Ok
1k
lOOk
FREQUENCY
~
1M
~
\
"~z
t
10M
o
10
10k
1k
'00
Hz
~
~
~
~
lOOk
1M
°> -,
~
Q
'0
OUTPUT SETTLING TIME
(WHEREVER JOHNSON NOISE IS GREATER THAN
AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE
0
I
CONSIDERED NEGLIGIBLE fOR APPLICATION)
Q
~
Q 0,10
i<
V
~
Q
~
~
0.0
•
...... 1-'
z
~
-jJ.S
Figure 15. Output Settling Time vs.
Output Swing and Error (Circuit of
Figure 23)
Figure 14. Large Signal Frequency
Response
'00
~
~
-lOO'-O--..J...._-L---1--.:~'-'--"'----..,J
10M
FReOUENCY - Hl
Figure 13. Common Mode Rejection
lIS. Frequency
II::
+5
~
!\
I"" '-.....
0
,
+10
t--
-
000'
'00
./
"~
1'\
§:
10k
0
10
'00
FReQUENCY - Hz
FREQUENCY - Hz
Figure 16. Total Harmonic Distortion
vs. Frequency
. ,...
,
1k
.,/
.).-'\
_/
100
./
, .-
0
'OOk
1000
V
/.
0
0
III
1k
~
//
r"-f.,..
;OI'iOW'j
lHNsoN1o'SE
I
V
UNITY GAl""
...... V
lkHl
RJISTOR
~
0
V
~~~~~~~~ WITHlI
,
10,000
/'
-,
Ij
V
/::
~
~
10Hz
AMPLIFIER
,
o lOS
GENE1RATED ~OISE
lOS
10'
SOURCE IMPEDANCE -
Figure 17. Input Noise Voltage
Spectral Density
V
l//
1010
1011
n
Figure 18. Total Noise vs. Source
Resistance
+v
>V
1k
a. Unity Gain Follower
b. Follower with Gain = 10
Figure 19. T.H.D. Test Circuits
E!::!v
Figure 20. Crosstalk Test Circuit
1 S
I
F;yure 21a. Unity Gain Follower
Pulse Response (Large Signal)
Figure 21b. Unity Gain Follower
Pulse Response (Small Signal)
Figure 21c. Unity Gain Follower
Figure 22b. Unity Gain Inverter
Pulse Response (Large Signal)
Figure 22c. Unity Gain Inverter
Pulse Response (Small Signal)
4.99kn
V'No-'Wl.-;I~
SQUARE
WAVE
INPUT
Figure 22a. Unity Gain Inverter
2-78 OPERA TIONAL AMPLIFIERS
....
F====~~~j~I~ERTICAL
VERRORm~
VOUT
SENSE
Figure 23. Settling Time Test Circuit
VoUT-l+~
Fast settling time (8/.1s to 0.01% for 20V p.p step), low power
and low offset voltage make the AD642 an excellent choice
for use as an output amplifier for current output D/A converters such as the AD7541.
.7
TOIdl
"'
VIN
REfERENCE
To 100, which is the case
for the specified transistor, the base-emitter voltage on side 1
is to a close approximation:
VBE A = kT/q In II/lSI
This circuit is arranged to take the difference of the VBE'S of
QlA and QlB, thus producing an output voltage proportional
to the log of the ratio of the inputs:
VOUT = -K (VBE A
-
VBE B) = _15 kT (In I111S1 -In IzII5Z)
q
VOUT=-KkT/qIn 1111z
The scaling constant, K is set by Rl and R TC to about 16,
to produce IV change in output voltage per decade difference
in input signals. RTC is a special resistor with a +3S00ppmtC
temperature coefficient, which makes K inversely proportional
to temperature, compensating for the "T" in kT /q. The logratio transfer "haracteristic is therefore independen t of temperature.
This particular log ratio circuit is free from the dynamic problems that plague many other log circuits. The -3dB bandwidth
is 50kHz over the top 3 decades, lOOnA to lOOIJA, and decreases smoothly at lower input levels. This circuit needs no
additional frequency compensation for stable operation from
input current sources, such as photodiodes, that may have
lOOpF of shunt capacitance. For larger input capacitances a
20pF integration capacitor around each amplifier will provide
a smoother frequency response.
2-80 OPERA TlONAL AMPLIFIERS
INPUT PROTECTION
The AD642 is guaranteed for a maximum safe input potential
equal to the power supply potential. The input stage design
also allows differential input voltages of up to ±O.S volts while
maintaining the full differential input resistance of lolZn.
This makes the AD642 suitable for low speed voltage comparators directly connected to a high impedance source.
Many instrumentation situations, such as flame detectors in
gas chromatographs, involve measurement of low level currents from high-voltage sources_ In such applications, a sensor
fault condition may apply a very high potential to the input
of the current-to-voltage converting amplifier. This possibility
necessitates some form of input protection. Many electrometer type devices, especially CMOS designs, can require
elaborate zener protection schemes which often compromise
overall performance. The AD642 requires input protection
only if the source is not current-limited, and as such is similar
to many J FET -inpu t designs. The failure mode would be overheating from excess current rather than voltage breakdown.
If the source is not current-limited, all that is required is a
resistor in series with the affected input terminal so that the
maximum overload current is 1.0mA (for example, 100kn
for a 100 volt overload). This simple scheme will cause no
significant reduction in performance and give complete overload protection. Figure 30 shows proper connections.
Figure 30. A 0642 Input Protection
r.ANALOG
WOEVICES
Dual High-Speed
Implanted BiFET Op Amp
AD644
FEATURES
Matched Offset Voltage
Matched Offset Voltage Over Temperature
Matched Bias Currents
Crosstalk -124dB at 1kHz
Low Bias Current: 35pA max Warmed Up
Low Offset Voltage: SOOj.1V max
Low Input Voltage Noise: 2p.V POp
High Slew Rate: 13V!p.s
Low Quiescent Current: 4.SmA max
Fast Settling to ±0.01%: 3p.s
Low Total Harmonic Distortion: 0.001S% at 1kHz
Standard Dual Amplifier Pin Out
AD644 PIN CONFIGURATION
INVERTING
INPUT
INVERTING
INPUT
PIN 4 IS IN ELECTRICAL
CONTACT WITH THE CASE
TOP VIEW
PRODUCT DESCRIPTION
The AD644 is a pair of matched high·speed monolithic FETinput operational amplifiers fabricated with the most advanced
bipolar, JFET and laser-trimming technologies. The AD644
offers matched bias currents that are significantly lower than
currently available monolithic dual BiFET operational amplifiers: 35pA max, matched to 25pA for the AD644K and
L, 75pA max matched to 35pA for the AD644J and S. In addition, the offset voltage is laser trimmed to less than 0.5mV,
and matched to 0.25mV for the AD644L, 1.0mV and matched
to 0.5mV for the AD644K, utilizing Analog Devices' laserwafer trimming (LWT) process.
The tight matching and temperature tracking between the
operational amplifiers is achieved by ion-implanted J FETs
and laser-wafer trimming. Ion-implantation permits the fabrication of precision, matched J FETs on a monolithic bipolar
chip. This process optimizes the ability to produce matched
amplifiers which have lower initial bias currents than other
popular BiFET op amps. Laser-wafer trimming each amplifier's input offset voltage assures tight initial match and superior IC processing guarantees offset voltage tracking over the
temperature range.
The AD644 is recommended for applications in which both
excellent ac and dc performance is required. The matched
amplifiers provide a low cost solution to true wideband instrumentation amplifiers, low dc drift active filters and output
amplifiers for four quadrant multiplying DI A converters such
as the AD7541, 12-bit CMOS DAC.
PRODUCT HIGHLIGHTS
1. The AD644 has tight side to side matching specifications to
ensure high performance without matching individual
.
devices.
2. Analog Devices, unlike some manufacturers, specifies each
device for the maximum bias current at either input in the
warmed-up condition, thus assuring the user that the
AD644 will meet its published specifications in actual use.
3. Laser-wafer-trimming reduces offset voltage to as low as
0.5mV max matched side to side to O.25mV (AD644L),
thus eliminating the need for external nulling.
4. Improved bipolar and JFET processing on the AD644 result
in the lowest matched bias current available in a high speed
monolithic FET op amp.
5. Low voltage noise (2p.V p-p) and high open loop gain enhance the AD644's performance as a precision op amp.
6. The high slew rate (13.0VIp.s) and fast settling time to
0.01% (3.0p.s) make the AD644 ideal for D/A, AID, samplehold circuits and dual high speed integrators.
7. Low harmonic distortion (0.0015%) and low crosstalk
(-124dB) make the AD644 an ideal choice for stereo audio
applications.
8. The standard dual amplifier pin out allows the AD644 to
replace lower performance duals without redesign.
9. The AD644 is available in chip form.
The AD644 is available in four versions: the "J", "K" and
"L" are specified over the 0 to +70°C temperature range and
the "5" over the -55°C to +125°C operating temperature
range. All devices are packaged in the hermetically-sealed,
TO-99 metal can.
OPERA T10NAL AMPLIFIERS 2-81
I
•
SPECIFICATIONS
Model
Min
OPEN LOOP GAIN
Vo = ::':: IOV,R L 2:" 2kfl
T mm to Tmax.RL =2kn
30,000
20,000
(@ +25OC and Vs= ±15V de)
AD644J
Typ
Max
AD644K
Typ
Min
Min
Max
AD644L
Typ
Max
50,000
40,000
50,000
40,000
Min
AD644S
Typ
Max
Units
VN
VN
50,000
20,000
OUTPUT CHARACTERISTICS
Voltage til RL = 2kO, T mm to T max
Vollage (51 RL = lOkO, T mm to T max
Short ClrcUJt Current
±lO
±12
~
~
±10
±12
12
13
25
~
~
~
±IO
±12
12
13
~
25
±10
±12
12
13
± 12
~ 13
V
V
rnA
25
25
FREQUENCY RESPONSE
UnIty Gam Small Signal
Full Power Response
Slew Rate, UrntyGam
8.0
Total Harmonic Dlstortton
20
200
130
00015
INPUT OFFSET VOLT AGEl
Initial Offset
Input Offset Voltage T mm to T max
8.0
2.0
200
130
00015
20
200
130
0.0015
8.0
2.0
200
130
00015
8.0
MHz
kHz
V/~s
%
2.0
35
1.0
2.0
0.5
1.0
1.0
3.5
mV
mV
200
100
100
100
~VN
35
pA
pA
0.5
3.5
35
Input Offset Voltage vs Suppl:',
TmmtoTmax
INPUT BIAS CURRENT'
Either Input
Offset Currell(
10
10
10
5
75
MATCHING CHARACTERISTICS'
Inpm Offset Voltage
35
10
5
10
5
Input Bias Current
Crosslalk
-124
-124
-124
-124
mV
mV
pA
dB
INPUTIMPEDANCE
DIfferenual
Common Mode
10 12 116
10 1'113
10"116
10"113
10"116
[01'113
10 12 116
10 12 113
MllllpF
MllllpF
,,20
~ 12
V
V
dB
1.0
3.5
35
Input Offset Voltage T mm to T max
INPUT VOLTAGE RANGE
Dtfferenual4
Common Mode
Common Mode RejectIOn
::'::10
TEMPERATURE RANGE
Operating, Rated Perfdrmance
Storage
PACKAGE OPTION'
TO-99Style(H-08B)
::,::10
80
2
35
22
18
16
~
0.25
1.0
25
,,20
:::: 12
~20
::'::20
::':: 12
76
INPUT NOISE
VoltageO IHzto 10Hz
f= 10Hz
f= 100Hz
f= 1kHz
f ~ 10kHz
POWER SUPPLY
Rated Performance
Operatmg
QUiescent Current
0.5
2.0
25
35
%10
" 12
22
18
16
~
15
35
0
-65
~ 18
4.5
~5
+ 70
+ 150
0
-65
~ 18
4.5
~5
+70
0
-65
35
+ 150
AD644KH
AD644JH
~
~15
15
35
~VP-L
2
35
22
18
16
2
35
22
18
16
2
35
~5
±10
80
80
~ 18
4.5
+ 70
+ 150
nVfYHz
nVrVHz
nV/Vlli
nV/VHz
15
~5
35
+ 125
-55
-65
AD644LH
~ 18
4.5
+ 150
AD644SH
NOTES
IInput Offset Voltage speclficatlons are guaranteed after 5 mmutes
of operation at T i\ = + 25°C
2Blas Current specificatIOns are guaranteed at maximum at either
Input after 5 mmutes of operation at T t\ = + ZsoC For
higher temperatures, the current doubles every lOoe
3Matchmg IS defined as the difference between parameters of the two amphfier~
4Defined as voltage between mputs, such that neither exceeds:,: lOY from ground
5See Section 16 for package outlme mformatlon
SpeCificatIOns subject 10 change Without notice
SpecificatIOns shown m boldface are tested on all produl.:tlOn unus at final
electrical test Results from those tests are used to calculate outgoing quahty
levels All mill and max specificatIOns are guaranteed, although only those
shown In boldface are tested on all production unus
METALIZATION PHOTOGRAPH
Dimensions shown
lfi
inches and (mm).
~---------------------~v~------------------------------~~
V+
8
6 -INPUT 2
5 +INPUT 2
OUTPUT 1
2-82 OPERA TlONAL AMPLIFIERS
V-
OUTPUT 2
V
V
rnA
"C
"C
Typical Characteristics
~r-----'------r-----'----~
0
30
FREQ"lkHz
t16V de SUPPLI
__---1
6
101---+---H'-~+-----1
0
161---+---!---+'~
/
V-
V
0
VVOUT
V
, v0
~
5
10
Hi
>
J
§
10
20
I)
10
5
V
15
_V
0
20
100
vs.
Figure 2. Output Voltage Swing
Supply Voltage
40
lk
10k
LOAD RESISTANCE - Ohms
SUPPLY VOLTAGE -tV
SUPPl V VOLT AGE - tV
Figure 1. Input Voltage Range
Supply Voltage
~o
25°C
Rt-2\<
Figure 3. Output Voltage Swing vs.
Resistive Load
75,,-------,..--------,
vs.
I
-----J,K,l
-
____ 5
1DOnA
,....
30
~
I
I
v=t1
20
~
~
~
'"'
V
,,/
~
10
J/ "
lOOp'
~
lOp.
15
10
SUPf'lY VOLTAGE - tV
20
1,.-55
-- --
/ :(
V
95
70
36
-25
TEMPERATURE _
Figure 4. Input Bias Current vs.
Supply Voltage
v. ."
//S
125
vs.
Figure 6. Input Bias Current vs. CMV
R,I.,.
/'
150
1
100
50
/
V
/
-
-
/
25
80
20
60
15
40
.......
.............
10
............
20
.............
05
-55
TEMPERATURE _
'" "-
-p~~~==
MARGIN
~ITHNO ~OAD
100
126
-20
10
100
1k
\
"\\
"'~
" "'
10k
"-
1---..,
~'C
""
~2kn
0
tOOk
60
10
15
SUPPLY VOLTAGE - tV
20
Figure 10. Open Loop Voltage Gain
vs. Supply Voltage
·
20
10M
1M
Vs '" t15V
VCM '" tV pop +2SOC
10
10
100
100
.su-ty
~
l~ppLY
0
0
~
11 0
100
Rl
80
\
Vs '" t1SV WITH
tV pop SINE WAVE
L
100
Figure 9. Open Loop Frequency
Response
vs.
11 0
11 0
·
·
""
FREQUENCY - Hz
°c
Figure 8. Open Loop Gain
Temperature
Figure 7. Change in Offset Voltage
vs. Warm-Up Time
~
............. ~
55
25
-25
WARM-UP TIME - Minutes
120
--
100
30
200
"0
COMMON MODE VOLTAGE - V
Figure 5. Input Bias Cu"ent
Temperature
250
-10
°c
1k
~
10k
o~
I\.
'"
tOOk
1M
~
40
0
0
10M
FREQUENCY - Hz
Figure ". Power Supply Rejection
vs. Frequency
10
100
""
1k
~
10k
~
tOOk
1M
10M
FREQUENCY - Hz
Figure 12. Common Mode Rejection
Ratio vs. Frequency
OPERA TIONAL AMPLIFIERS 2-83
+10.----r--r--r...,.--.,.-.----,
.
1\
"·C
"
\
VS·t1SV
RL'"'2k
I'
t--t--
•
0
10
1k
100
10k
lOOk
1M
10M
-10 o~--..u-l--L--~--...J
FREQUENCV - Hz
,.
100
Figure 13. Large Signal Frequency
Response
Figure 14. Output Settling Time lIS. Output
Swing and Error (Circuit oiFigure 23a)
1.0
..
1k
,.
V
14
Q
12
V
•
~
~
o
z
!.!
i
~
~~~~~E,~ wiry
•
•
1/
00 1
V
~
J
4
/
V
UNITY GAIN
FOLLOWER
l.--'
0001
100
lk
10k
F'REQUENCY - Hz
1,...
Figure 16. Total Harmonic Dilltortion
lIS. Frequency
..O~,.-'O~'-~'O~.~,.-~'--+~~~
FREQUENCY - MHz
Figure 17. Closed Loop Gain & Phase
lIS. Frequency
+V
f--
V
!::
~ 010
''''
Figure 15. Noise Spectral Density
I
%
10k
FREQUENCY - Hz
SETTLING TIME - p.
'V
•
o
/
I
200m 400m 800m 800m
1
12
14
1.6
ERROR SIGNAL - Volts
Figure 18. Slew Rate lIS. Error
Signal
VOUT
+V
,.
a. Unity Gain Follower
b. Follolll/er with Gain
= 10
Figure 20. Crosstalk Tellt Circuit
Figure 19. T.H.D. Tellt Circuits
Figure 21a. Unity Gain Follower
Pulse Response (Large Signal)
Figure 21b. Unity Gain Follolll/er
Pulse Response (Small Signal)
Figure 21c. Unity Gain Follower
Figure 22b. Unity Gain Inverter
Pulse Response (Large Signal)
Figure 22c. Unity Gain Inverter
Pulse Response (Small Signal)
4.99Idl
.!.l
V'NC>-'WI.....
&WARE
WAVE
INPUT
~D&u·~~~.--~.-o
Figure 22a. Unity Gain Inverter
2-84 OPERATIONAL AMPLIFIERS
F==::""::'==-- ~~~51~ERTICAl
4991<
VERROR=~
4.99k
Your
Figure 23a. Settling Time Test Circuit
VERROR.lmV/DIV
junction via the low pass filter formed by the lOOn series
resistor and the load capacitance, CL.
The low input bias current (3SpA), low noise, high slew rate
and high bandwidth characteristics of the AD644 make it
suitable for electrometer applications such as photodiode
preamplifiers and picoampere current-to-voltage converters.
The use of guarding techniques in printed circuit board
layout and construction is critical for achieving the ultimate in
low leakag~ performance that the AD644 can deliver. The in- •
put guarding scheme shown in Figure 25 will minimize leakage
as much as possible. The same layout should be used on both
sides of a double side board. The guard ring is connected to
a low impedance potential at the same level as the inputs. High
impedance signal lines should not be extended for any unnecessary length on a printed circuit; to minimize noise and leakage,
such conductors should be replaced by rigid shielded cables.
VIN '" lOV/DIV
Figure 23b. Settling Characteristic Detail
The fast settling time (3.0j.ls to 0.01 % for 20V p-p step) and
low offset voltage make the AD644 an excellent choice as an
output amplifier for current output DIA converters such as
the AD7541. The upper trace of the oscilloscope photograph
of Figure 23b shows the settling characteristics of the AD644.
The lower trace represents the input to Figure 23a. The AD644
has been designed for fast settling to 0.01%, however, feedback
components, circuit layout and circuit design must be carefully
considered to obtain the optimum settling time.
499kfl
n . 499kl1
-lfINPUT
Rl
2knto
20kn
TYPICAL CAPACITANCE
LIMIT FOR VARIOUS
LOAD RESISTORS
~
2kn
~UPTO
--+
10kfl --+
2Okn.....
1500pF
600pF
500pF
Figure 24. Circuit for Driving a Large Capacitive Load
Figure 25. Board Layout for Guarding Inputs
INPUT PROTECTION
The AD644 is guaranteed for a maximum safe input potential
equal to the power supply potential. The input stage design
also allows differential input voltages of up to ±1 volt while
maintaining the full differential input resistance of 10 12 n.
This makes the AD644 suitable for comparator situations
employing a direct connection to high impedance source.
Many instrumentation situations, such as flame detectors in
gas chromatographs, involve measurement of low level currents
from high-voltage sources. In such applications, a sensor fault
condition may apply a very high potential to the input of the
current-to-voltage converting amplifier. This possibility necessitates some form of input protection. Many electrometer type
devices, especially CMOS designs, can require elaborate zener
protection schemes which often compromise overall perfor·
mance. The AD644 requires input protection only if the source
is not current-limited, and as such is similar to many JFET-input
designs. The failure mode would be overheating from
excess current rather than voltage breakdown. If the source is
not current-limited, alLthat is required is a resistor in series
with the affected input terminal so that the maximum overload current is 1.0mA (for example, 100kn for a 100 volt
overload). This simple scheme will cause no significant reduction in performance and give complete overload protection.
Figure 26 shows proper connections.
Transient Response RL =2H1. CL =500pF
The circuit in Figure 24 employs a lOOn isolation resistor
which enables the amplifier to drive capacitive loads exceeding 500pF; the resistor effectively isolates the high frequency feedback from the load and stabilizes the circuit. Low
frequency feedback is returned to the amplifier summing
Rp "" lV:A FOR TRANSIENTS LESS THAN 1 SECOND
Rp'"
~ FOR CONTINUOUS OVER LOADS
l00,uA
Figure 26. AD644 Input Protection
OPERA TIONAL AMPLIFIERS 2-85
BIPOLAR
ANALOG INPUT
t10V
The state variable filter (Figure 28) is stable, easily tuned and
is independent of circuit Q and gain. The use of the AD644
with its low input bias current simplifies the resistor (R3, R4)
selection for the passband center frequency, circuit Q and
voltage gain.
R.
lOOk
BIPOLAR
OFFSET
R6
10k NOTES
1 R3/R4 MATCH 005% OR BETTER.
2. R1, R2 USED ONLY IF GAIN
ADJUSTMENT IS REQUIRED
v-
Figure 27a. AD644 Used as DAC Output Amplifiers
fo '" CENTER FREQUENCY = 1/211" Re
Qo = QUALITY FACTOR =
R2;~2
00, IS ADJUSTABLE BY VARYING R2
fo, IS ADJUSTABLE BY VARYING R OR C
Ho '" GAIN AT RESONANCE"" R2/Rl
R3=R4"" 108 /1 0
Figure 28. Barid Pass State Variable Filter
VOUT
Figure 29. Sample and Hold Circuit
Figure 27b. Large Signal Response
The sample and hold circuit, shown in Figure 29 is suitable for
use with 8-bit AID converters. The acquisition time using a
3900pF capacitor and fast CMOS SPST (ADG200) switch is
15/ls.
The droop rate is very low 25 X 10-9 V//lS due to the low
input bias currents of the AD644. Care should be taken to
minimize leakage paths. Leakages around the hold capacitor
will increase the droop rate and degrade performance.
Figure 27c. Small Signal Response
Figure 27a illustrates the 10-bit digital-to-analog converter,
AD75 33, connected for bipolar operation. Since the digital input can accept bipolar numbers and VREF can accept a bipolar
analog input, the circuit can perform a 4-quadrant multiplying
function. The photos exhibit the response to a step input at
VREF' Figure 27b is the large signal response and Figure 27 c
is the small signal response.
The output impedance of a CMOS DAC varies with the digital
word thus changing the noise gain of the amplifier circuit. The
effect will cause a nonlinearity the magnitude of which is
dependent on the offset voltage of the amplifier. The AD644K
with trimmed offset will minimize the effect. The Schottky
protection diodes recommended for use with many older
CMOS DACs are not required when using the AD644.
ACTIVE FILTERS
Literature on active filter techniques and characteristics based
on operational amplifiers is readily available. The successful
application of an active filter however, depends on the component selection to achieve the desired performance. The AD644
is recommended for filters in medical, instrumentation, data
acquisition and audio applications, because of its high gain
bandwidth figure, symmetrical slewing, low noise, and low
offset voltage.
2-86 OPERATIONAL AMPLIFIERS
OFFSET ADJUST
50k
-INPUT
+INPUT
GAIN = (WIN
~T-V'NI
INSTRUMENTATION AMPLIFIER WITH GAIN OF TEN
Figure 30. Wide Bandwidth Instrumentation Amplifier
The AD644 in the circuit of Figure 30 provides highly accurate
signal conditioning with high frequency input signals. It provides an offset voltage drift of 10/lV/oC, CMRR of 80dB over
the ral)ge of dc to 10kHz and a bandwidth of 200kHz (-3dB)
at 1V p-p output. The circuit of Figure 30 can be configured
for a gain range of 2 to 1000 with a typical nonlinearity of
0.01 % at a gain of 10.
Ultralow-Drift
Dual BiFET Op Amp
AD647 I
11IIIIIIII ANALOG
WDEVICES
FEATURES
Low Offset Voltage Drift
Matched Offset Voltage
Matched Offset Voltage Over Temperature
Matched Bias Current
Crosstalk -124dB at 1kHz
Low Bias Current: 35pA max Warmed Up
Low Offset Voltage: 250~V max
Low Input Voltage Noise: ~V POp
High Open Loop Gain: 108dB
Low Quiescent Current: 2.8mA max
Low Total Harmonic Distortion
Standard Dual Amplifier Pin Out
AD647 PIN CONFIGURATION
INVERTING
INPUT
INVERTING
INPUT
VPIN 41S IN ELECTRICAL
CONTACT WITH THE CASE
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD647 is an ultralow-drift dual JFET amplifier that
combines high performance and convenience in a single
.
package.
1. The AD647 is guaranteed and tested to tight matching
specifications to ensure high performance and to eliminate the selection and matching of single devices.
The AD647 uses the most advanced ion-implantation and
laser wafer drift trimming technologies to achieve the highest
performance currently available in a dual JFET. Ion-implantation permits the fabrication of matched JFETs on a monolithic bipolar chip. Laser wafer drift trimming trims both the
initial offset voltage and its drift with temperature to provide
offsets as low as 100llV (2501lV max) and drifts of 2.5IlV/oC
max.
2. Laser wafer drift trimming reduces offset voltage and offset voltage drifts to 250llV and 2.5~V/oC max.
In addition to outstanding individual amplifier performance,
the AD64 7 offers guaranteed and tested matching performance
on critical parameters such as offset voltage, offset voltage
drift and bias cutrents.
This high level of performance makes the AD647 especially
well suited for high precision instrumentation amplifier
applications that previously would have required the costly
selection and matching of space wasting single amplifiers.
The AD647 also offers high levels of performance for
Digital to Analog Converter output amplifiers, and filtering
applications.
3. Voltage noise is guaranteed at 41lV pop max (0.1 to
10Hz) on K, L and S grades.
4. Bias current (35pA K, L, S; 75pA 1> is specified after
five minutes of operation.
5. Total supply current is a low 2.8mA max.
6. High open loop gain ensures high linearity in precision
instrumentation amplifier applications.
7. The standard dual amplifier pin out permits the direct substitution of the AD647 for lower performance devices.
8. The AD647 is available in chip form.
The AD647 is offered in four performance grades, three
commercial (the J, K, and L) and one extended (the S). All
are supplied in hermetically sealed 8-pin TO-99 packages.
OPERA TIONAL AMPLIFIERS 2-87
•
SPECIFICATIONS
(@
Mm
Model
+250& aJII Vs= ±15V de)
AD647J
Typ
Max
AD647K
Typ
Min
Mm
M ..
AD647L
Typ
Max
Mm
AD647S
Typ
Max
Unitt
OPEN LOOPGAIN
Vo=
±lOV,RL~2kfl
T nun to T max, RL = 2k!l
250,000
250,000
100,000
100,000
250,000
250,000
VN
V/V
250,000
100,000
OUTPUTCHARACTERISTICS
Voltage@ RL = 2kO, TIIlID to T max
Voltage@ RL = lOkQ. T nun to Tmlllx
Short Cucwt Current
±12
±I3
2S
"'10
"'12
"'10
,012
,010
",12
±12
±13
25
±12
±13
25
:10
"'12
±12
±13
25
V
V
rnA
1.0
SO
30
MHz
kHz
FREQUENCY RESPONSE
Uruty Gam Small Signal
Full Power Response
Slew Rate, Unity Gam
1.0
50
30
2.0
2.0
1.0
SO
3.0
2.0
1.0
SO
30
2.0
VI""
INPUTOFFSETVOLTAGE'
InmalOffset
InputOffsetVoltagevs Temp
InputOffsetVoltagevs Supply,
Tnun toT max
1.0
10
0.5
5
0.25
2.5
0.5
5.0
"vrc
mV
200
100
100
100
"VN
35
pA
pA
0.5
10.0
25
INPUT BIAS CURRENT'
Either Input
Offset Current
10
5
MATCHING CHARACTERISTICS'
Input Offset Voltage
75
10
2
10
2
0.5
5
25
35
10
2
-124
-124
-124
-124
mV
"VI"C
pA
dB
10 12116
10 12116
10 12116
10 12116
1O'~16
10 12 116
10 12116
10 12116
MOllpF
MOllpF
±20
±12
V
V
dB
1.0
10
35
Input Offset Voltage Tnun to Tmall
Input Bms Current
Crosstalk
35
0.25
2.5
25
INPUT IMPEDANCE
Dlfferentlal
Common Mode
INPUT VOLTAGE RANGE
Dlfferenua14
Common Mode
Common-Mode Rejection
±20
±12
,olD
76
INPUT NOISE
VoltageO IHztolOHz
100Hz
f~lkHz
f~
10kHz
±20
±12
"'10
80
±20
±12
"'10
80
4
4
4
2
70
45
30
25
f~IOHz
f~
:10
80
70
45
30
25
70
45
30
25
70
45
30
25
~~/~
nVIV'iiz
nVIV'iiz
nV/VHz
POWBRSUPPLY
Rated Performance
OperatIng
QultScent Current
TEMPERATURE RANGE
OperanDg, Rated Performance
Storage
PACKAGE OPTION'
TQ·99 Style (H.08B)
• ±IS
±15
::tIS
±IS
±5
± 18
2.8
±5
±18
2.8
±5
± 18
2.8
±5
± 18
2.8
0
-65
+70
+ ISO
0
-65
+70
+ ISO
0
-65
+70
+ 150
-55
-65
+125
+ ISO
AD647JH
NOTES
Ilnput Offset Voltage specaflCllhons are guaranteed after 5 DUnules
of operation al TA :::: + 25"<:
2BJ8S Current specaflC8uons are guaranteed at maximum at either
mput after S IlUnutes of operatIOn at TA = + 2S"C For
higher temperatures, the current doubles every IO"C
3Matclung IS defmed as the d.fference between parameters of
the two amphfrers
AD647LH
AD647KH
AD647SH
4Defmed as the maxunum safe voltage between mputs. sucb that
nenher exceeds ± IOV from ground
5See SectIOn 16 for package outlme tnformanon
SpecIficauons subJect to change without notlCC
SpeClficahons shown m boldface are tested on all production unus at final
electrical test Results from those tests are used to calculate outgomg qualIty
levels All mm and max specutcanons are guaranteed. although only those
shown JD boldface are tested on aU prodUCtion uruts.
METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm).
~--------------------- ~V~---------------------------------4
V+
6 -INPUT2
5 +INPUT2
2-88 OPERA TIONAL AMPLIFIERS
1
4
7
OUTPUT 1
V-
OUTPUT 2
V
V
rnA
°C
OC
Typical Characteristics
..
~
~r-----'------r----_.-----'
v-I-
~,.r_----_r------r_----_b~~~
,
,
~
l;l
i'·~----~----~~~~~-----1
i
,.
,.
V
i
~
~ '0r_----_r------~~~-r----~
~
~
5
,.
20
V
20
'0
t.v
'k
'DO
LOAD RESISTANCE -
Figure 2. Output Voltage Swing VB.
Supply Voltage
4»r-----,------,------,------,
t1& VOLT SLI'PLIES
vI-'
,.
SUPf'LY VOLTAGE -
Figure 1. Input Voltage Range VB.
Supply Voltage
II
•
5~----~~~--~----_r----_1
SUPPLY VOLTAGE -:tV
fREQUENCY. 1kHz
Figure 3. Output Voltage Swing VB.
,,...Resistive Load
20
1-
,
E
1.
U
~
,
Iu
u
S
2.
~
/v
10
~
!;
~
~
l
15
J
~
a:
u
'.A
'I"'"
,/: /
'OOoA
'5
,.
20
Figure 4. Quiescent Current VB.
Supply Voltage
~r-----------_.------------~
'5
'pA
2.
/
.1/
5/
~ Vc
-- ---V
5
SUPPLY VOLTAGE - tVolu
)'5V
Va·
'UnA
'0pA
,.
J, K,l
S
----
'DOnA
c
a:
~
'Ok
n
...
-m
25
70
..
POWER SUPPLY VOLTAGE -:tV
TEMPERATURE _
Figure 5. Input Bias Current VB.
Supply Voltage
Figure 6. Input Bias Current VB.
Temperature
'25
°c
&.
25
RL-a
......... r-
20
1-
,
I
~r_------------+_----------__1
,
~ 15
il
~
J
~ 10
~ m~------------+_------~--~
!
/
I
25
.~
/
~
i
;
~
~
i
II '
•o
~~.------------~------------~+,.
COMMON MODE VOLTAGE - V
10
~
.
.. .
~
,
'Il
~
~
20
--
'"'""-
f--'::'~==
MARGIN
i'THNOtAO
...,.
'DO
'k
-, ,
.............
'0
...
... 1,
\
\
z
\ ..wi
<
~
'\.r-1M
Figure 10. Open Loop Frequency
Response
'20
-25
+20
1
.:c ..
~
~
g
25"c
RL"' 2kn
..
20
'OM
10.
,.
'25
'00
Va· t15VWITH
1V P"iI SINE WAVE
70
~
.
25
TEMPERATURE _ °c
".
/'
, 100
z
t
............. .......
Figure 9. Open Loop Gain VB.
Temperature
I--"
".
--
.............
••
-a;
Figure 8. Input Offset Voltage Turn
On Drift VB. Time
+,..
"
10k
100k
FREQUENCY - Hz
, 5
WARM·UP TIME - MlnUtH
Figure 7. Input Bias Current VB.
CMV
'DO
2.
,.
~
,.
'" '"
10
100
'\
~LY,
,.
SUf'PLYVOLTAGE-t.V
Figure 11. Open Loop Voltage
Gain VB. Supply Voltage
'\ +supLv_ -
""''""
,.
100k
FREQUENCY - Hz
1M
"..
Figure 12. Power Supply Rejection
VB. Frequency
OPERA TIONAL AMPLIFIERS 2-89
30
110
Vs" ±15V
VCM .. tV pop +2SoC
'00
.. '"
~
~
~
80
.0
20
o
'0
"""'"
'00
Vs=:t15V
RL "2k
"
~
I
"'"
'Ok
1k
1M
o
10M
FREQUENCY - Hz
1k
'00
10k
1\
lOOk
1M
10M
OUTPUT SETTLING TIME - ~I
Figure 15. Output Settling Time vs.
Output Swing and Error (Circuit of
Figure 23)
Figure 14. Large Signal Frequency
Response
0
'00
~
C
~
~
C
0' 0
c
u
~~~~~~El~ WITHV
,
,,-
~
....- V
,
000
1k
'00
V
'Ok
FREQUENCY - Hz
~
80
~
:;.
70
I
~
90
;i;
50
t
40
~
30
~
0
~
UNITY GAIN
,o,",oW'i
II
(WHEREVER JOHNSON NOISE IS GREATER THAN
AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE
CONSIDERED NEGLIGIBLE FOR APPLICATION)
90
o
V
~ 00
~
'0
FREQUENCY - Hz
I
~
'0
~
1001<
~,
~
\
25'C
Figure 13. Common Mode Rejection
vs. Frequency
z
o
\
20
I
w
~
1\
g
~
10,000
1000
/
'00
~
r-t-
L"
0
,
....
..,.-:
t
"
'00k
Figure 16. Total Harmonic Distortion
vs. Frequency
'10
100
lk
10k
FReQUENCY - Hz
Figure 17. Input Noise Voltage
Spectral Density
'00k
,
o. lOS
'07
~ /"
~
/
GENjRATED iO'SE
10&
y"
;/ ~
AMPLIFIER
'0
/'
Y\
..
./
~
.............
1kHz
R~SISTOR ~OHNSO~ NOISE
"0..
10'
.
,
SOURCE IMPEDANCE -
10
n
10Hz
"
'0 "
Figure 18. Total rms Noise vs.
Source Resistance
1k
a. Unity Gain Follower
b. Follower with Gain = 10
Figure 19. T.H.D. Test Circuits
Figure 21a. Unity Gain Follower
Pulse Response (Large Signal)
Figure 21b. Unity Gain Follower
Pulse Response (Small Signal)
Figure 20. Crosstalk Test Circuit
Figure 21c. Unity Gain Follower
'99kf!
V,N O-'W\.--"-I
saUARE
WAVE
INPUT
-Vs
Figure 22a. Unity Gain Inverter
2-90 OPERA TIONAL AMPLIFIERS
Figure 22b. Unity Gain Inverter
Pulse Response (Large Signal)
Figure 22c. Unity Gain Inverter
Pulse Response (Small Signal)
Applications
APPLICATION NOTES
The AD647 is fully specified under actual operating conditions to insure high performance in any application, but there
are some steps that will improve on even this high level of
performance.
The bias current of a J FET amplifier doubles with every 10° C
increase in junction temperature. Any heat source that can be
eliminated or minimized will significantly improve bias current
performance. To account for normal power dissipation, the
largest contributor to chip self-heating, the bias currents of the
ADM 7 are guaranteed fully warmed up with ±15V supplies. A
decrease in supply voltage will decrease power consumption,
resulting in a corresponding drop in bias currents.
Open loop gain and bias currents, to some extent, are affected
by output loading. In applications where high linearity is essential, load impedance should be kept as high as possible to minimize degradation of open loop gain.
The outstanding ac and dc performance of the AD647 make it
an ideal choice for critical insttumentation applications. In
such applications, leakage paths, line losses and external noise
sources should be considered in the layout of printed circuit
boards. A guard ring surrounding the inputs and connected to
a low impedance potential (at the same level as the inputs)
should be placed on both sides of the circuit board. This will
eliminate leakage paths that could degrade bias current performance. All signal paths should be shielded to minimize
noise pick-up.
BIPOLAR
ANALOG INPUT
:!:10V
A CMOS DAC AMPLIFIER
The output impedance of a CMOS DAC, such as the AD7541,
varies with digital input code. This causes a corresponding variation in the noise gain of the DAC-amplifier combination.
This noise gain modulation introduces a nonlinearity whose
magnitude is dependent on the amount of offset voltage
present.
Laser wafer drift trimming lowers the initial offset voltage and
the offset voltage drift of the AD64 7, therefore minimizing
the effect of this nonlinearity and its drift with temperature.
This, in conjunction with the low bias current and high open
loop gain, makes the AD647 ideal for DAC output amplifier
applications.
THE AD647 USED WITH THE AD7546
Figure 24 shows the AD647 used with the AD7546 I6-bit segment DAC. In this application, amplifier performance is critical to the overall performance of the AD7546. Al is used as a
dual precision buffer. Here the offset voltage match, low offset voltage and high open loop gain of the AD647 ensure
monotonicity and high linearity over the entire operating
temperature range. A2 serves a dual function: amplifier A is a
Track and Hold circuit that deglitches the DAC output and
amplifier B acts as an output amplifier. The performance of
the amplifiers of A2 is crucial to the accuracy of the system.
The errors of these amplifiers are added to the errors due
strictly to DAC imperfections. For this reason great care
should be used in the selection of these amplifiers. The
matching characteristics, low bias current and low temperature coefficients of the AD647 make it ideal for this application.
R'
''''''
BIPOLAR
OFFSET
R.
'''''
NOTES
1
2
R3/R4 MATCH 005% OR BETTER
Rl, R2 USED ONLY IF GAIN ADJUSTMENT IS REOUIRED
Figure 23. AD647 Used as DAC Output Amplifier
Figure 24. AD647 Used with AD7546 16-Bit DAC
OPERA TIONAL AMPLIFIERS 2-91
•
USING THE AD647 IN LOG AMPLIFIER APPLICATIONS
Log amplifiers or log ratio amplifiers are useful in a wide range
of analog computational applications, ranging from the simple
linearization of exponential transducer outputs to the use of
logarithms in computations involving multi-term products or
arbitrary exponents. Log amps also facilitate the compression
of wide ranging analog input signals into a range that can be
easily handled using standard circuit techniques.
The picoamp level input current and low offset voltage of the
AD647 make it suitable for wide dynamic range log amplifiers. Figure 27 is a schematic of a log ratio circuit employing
the AD647 that can achieve less than 1% conformance error
over 5 decades of current input, InA to 1001lA. For voltage
inputs, the dynamic range is typically 50mV to 10V for 1%
error, limited on the low end by the amplifiers' input offset
voltage.
1k
.------;:-c=----4 "'"
,....
-+-...........- - - - - i
v, ....
"
RTC
}
VOUT"-lVLOG,0 .,112
OR -1V LOG,O V, IV 2
"
TEL LABS
+35OOppm
081
NOTES
CIRCUIT SHOWN FOR NEGATIVE VOR liN
FOR POSITIVE INPUTS, Q1- PNP, AND VA --15V
lOOpF of shunt capacitance. For larger input capacitances a
20pF integration capacitor around each amplifier will provide
a smoother frequency response.
This log ratio amplifier can be readily adjusted for optimum
accuracy by following this simple procedure. First, apply VI =
V2 = -lO.OOV and adjust "Balance" for VOUT = O.OOV. Next
apply VI =-lO.OOV, V2 =-1.00V and adjust gain for VOUT =
+1.00V. Repeat this procedure until gain and balance readings
are within 2mV of ideal values.
ACTIVE FILTERS
In active low pass filtering applications the dc accuracy of the
amplifiers used is critical to the performance of the filter circuits. DC error sources such as offset voltage and bias currents
represent the largest individual contributors to output error.
Offset voltages will be passed by the filtering network and
may, depending on the design of the filter circuit, be amplified and generate unacceptable output offset voltages. In filter
circuits for low frequency ranges large value resistors are used
to generate the low pass filter function. Input bias currents
passing through these resistors will generate an additional offset voltage that will also be passed to the output of the filter.
The use of the AD647 will minimize these error sources and,
therefore, maximize filter accuracy. The wide variety of performance levels of the AD647 allows for just the amount of
accuracy required for any given application.
AD647 AS AN INSTRUMENTATION AMPLIFIER
The circuit shown in Figure 26 uses the AD647 to construct
an ultra high precision instrumentation amplifier. In this type
of application the matching characteristics of a monolithic
dual amplifier are crucial to ensure high performance.
Figure 25. Log-Ratio Amplifier
00lpf
The conversion between current (or voltage) input and log
output is accomplished by the base-emitter junctions of the
dual transistor Q1. Assuming Q1 has i3> 100, which is the case
for the specified transistor, the base-emitter voltage on side 1
is to a close approximation.
VBE A
=kT/q In
"
101en
"
101
~15f------+------f------~~~-;
V
~'20
I
I
r
w
ri
5
~
•
~
5 5~----~~~--r------r-----;
V
1
5
oL-____~----~L-----~----~
o
10
15
SUPPLY VOlTAGE- :!:.V
20
0~'------~----~1~0----~1~5----~ro
Figure 1. Input Voltage Range
vs. Supply Voltage
100
10
1k
LOAD RESISTANCE _ II
Figure 2. Output Voltage Swing
vs. Supply Voltage
400
,,.
0
SUPPLY VOlTAGE- :tV
Figure 3. Output Voltage Swing
vs. Resistive Load
l00nA
10
10nA
~360
1nA
Ia
~
/
100pA
320
~
~
~
C 28 0
, /'
•
24 0
V
10"
I'"
/
1pA
15
12
20
~
Figure 4. Quiescent Current vs.
Supply Voltage
20
-55
-25
35
&5
TEMPERAWRE - "C
Figure 5. Input Bias Current
vs. Supply Voltage
10
~
V
•
-10
~
V
30
1500
25
1250
~
~, 1000
~
-.
-8
10
COMMON-MODE VOLTAGE _ V
Figure 7. Input Bias Current vs.
Common-Mode Voltage
100
•
80
r"-r--.
GAIN
1" .....
,
~
500
30
40
60
80
-55
-25
35
0
Figure 9. Open Loop Gain vs.
Temperature
120
I,....-~
100
t"-r--+
I""' ....
1'1'
•
r-...
-SUPPLY
r"-
i"
•
-40
1M
II
SUPPLY
.....
-40
10M
FREQUENCY _ Ib:
Figure 10. Open Loop Frequency
Response
2-96 OPERATIONAL AMPLIFIERS
..
0
125
TEMPERA lURE _ "C
foo-t""
L
. .
o
10
TlME - Seconds
110
I,ok
250
1
~
-.
tOOk
20
::
750
~
0
10k
10
120
PHJE
~ .....
1k
'.~
i
Figure 8. Change in Offset Voltage
vs. Warm-Up Time
100
•
§
1V"
V
10
125
Figure 6. Input Bias Current vs.
Temperature
RL
v
..
10fA
16
SUPPlY VOLTAGE-:tV
SUPPLY VOLTAGE - :r.V
~
100tA
0
10
V
--L
!t':
2
4
10
1
SUPPLY VOLTAGE- :tV
4
1•
18
Figure 11. Open Loop Voltage Gain
vs. Supply
-20
100
1k
10k,
100k
1M
FREQUENCY - Hz
Figure 12. PSRR vs. Frequency
Typical Characteristics
22
~
80
1-00.
20
,
70
18
16
60
~
50
~
40
0
,.
0
100K
FREQUENCY _ Hz
10K
\
""
,
_1OL-____-L______L-__
o
10
1M
100
10K
lOOK
1M
Figure 13. CMRR vs. Frequency
~~
____
~
o
FREQUENCY - Hz
SETTLING TIME - ."s
Figure 14. Large Signal Frequency
Response
Figure 15. Output Settling Time vs.
Output Swing and Error Voltage
WHENEVER JOHNSON NOISE IS GREATER THAN
AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE
CONSIDERED NEGLIGIBLE FOR APPLICATION
140
I~
__ '20
f-- f--
~
J
FOLLOWER
WITH GAIN'" 10
.... 100
~
~
g
~
l/
1
001
0
Z
FOLLOWER
II I
II I
10k
1k
FREQUENCY _ Hz
100
,
1----+---+--1----+--+-'"
1.000
I-----l-----+--I----+---'S~~y
100
1----+--+,.,s.~I---~"I--o"'__+tI_-l
60
t;
~
UNITY GAIN
0001
80
10,000
20
lOOk
Figure 16. Total Harmonic
Distortion vs. Frequency
Figure 19a. Unity Gain Follower
0
10
oL-__- L__
100
1k
10k
lOOk
FREQUENCY - Hz
lOOK
1M
~
____
10M
~
100M
__- L__
lG
~
__
~
lOG
100G
SOURCE IMPEDANCE - II
Figure 17. Input Noise Voltage
Spectral Density
Figure 18. Total Noise vs. Source
Resistance
Figure 19b. Unity Gain Follower
Pulse Response (Large Signal)
Figure 19c. Unity Gain Follower
Pulse Response (Small Signal)
10kU
10kU
V"_",,,,-.4_(
SQUARE
WAVE
INPUT
-v,
Figure 20a. Unity Gain Inverter
Figure 20b. Unity Gain Inverter
Pulse Response (Large Signal)
Figure 20c. Unity Gain Inverter
Pulse Response (Small Signal)
OPERA TlONAL AMPLIFIERS 2-97
Applying the AD648
MINI-DIP
METAL CAN
APPLICATION NOTES
The AD648 is a pair of JFET-input op amps with a guaranteed
maximum IB of less than 10pA, and offset and drift laser-trimmed
to 0.3mV and 3...VrC respectively (AD648C). AC specs include
IMHz bandwidth, l.8V/IJ.S typical slew rate and 8 ...s settling
time for a 20V step to ±0.01% - all at a supply current less
than 4OO ...A. To capitalize on the device's performance, a number
of error sources should be considered.
The minimal power drain and low offset drift of the AD648
reduce self-heating or "warm-up" effects on input offset voltage,
making the AD648 ideal for on/off battery powered applications.
The power dissipation due to the AD648's 4OO ...A supply current
has a negligible effect on input current, but heavy output loading
will raise the chip temperature. Since a JFET's input current
doubles for every 10°C rise in chip temperature, this can be a
noticeable effect.
The amplifier is designed to be functional with power supply
voltages as low as ±4.SV. It will ,exhibit a higher input offset
voltage than at the rated supply voltage of ± ISV, due to power
supply rejection effects. Common mode range extends from 3V
more positive than the negative supply to I V more negative
than the positive supply. Designed to cleanly drive up to IOkO
and lOOpF loads, the AD648 will drive a 2kO load with reduced
open loop gain.
Figure 21 shows the recommended crosstalk test circuit. A
typical value for crosstalk is - 120dB at 1kHz.
Figure 22. Board Layout for Guarding Inputs
INPUT PROTECTION
The AD648 is guaranteed to withstand input voltages equal to
the power supply potential. Exceeding the negative supply voltage
on either input will forward bias the substrate junction of the
chip. The induced current may destroy the amplifier due to
excess heat.
Input protection is required in applications such as a flame
detector in a gas chromatograph, where a very high potential
may be applied to the input terminals during a sensor fault
condition. Figures 23a and 23b show simple current limiting
schemes that can be used. RPROTECT should be chosen such that
the maximum overload current is l.0rnA (for example lOOkO
for a lOOV overload).
10pF
+Vs
0>----1.---. PIN 8
01.F
h
OI~F:!:
-VIS 0
I
VOUT
20kS1
226k
9
.
P\N4
Rp TYPICALLY 100kH TO 1MH
Rp =
~ FOR
Rp =
l~~",A FOR CONTINUOUS OVERLOAD
1 SECOND OR LESS TRANSIENTS
Figure 23a. Input Protection of I-to-V Converter
Figure 21. Crosstalk Test Circuit
Rp
I
CSTRAY~
LAYOUT
To take full advantage of the AD648's IOpA max input current,
parasitic leakages must be kept below an acceptable level. The
practical limit of the resistance of epoxy or phenolic circuit
board material is between I x 10120 and 3 x 10120. This can
result in an additional leakage of SpA between an input of OV
and a -ISV supply line. Teflon or a similar low leakage material
(with a resistance exceeding 10170) should be used to isolate
high impedance input lines from adjacent lines carrying high
voltages. The insulator should be kept clean, since contaminants
will degrade the surface resistance.
A metal guard completely surrounding the high impedance
nodes and driven by a voltage near the common mode input
potential can also be used to reduce some parasitic leakages.
The guarding pattern in Figure 22 will reduce parasitic leakage
due to finite board surface resistance; but it will not compensate
for a low volume resistivity board.
~
Figure 23b. Voltage Follower Input Protection Method
Figure 23b shows the recommended method for protecting a
voltage follower from excessive currents due to high voltage
breakdown. The protection resistor, Rp, limits the input current.
A nominal value of lOOkn will limit the input current to less
than lmA with a 100 volt input voltage applied.
The stray capacitance between the summing junction and ground
will produce a high frequency roll-off with a comer frequency
equal to:
c..
mer =
I,
21T Rp Cstray
Accordingly, a lOOkn value for Rp with a 3pF C stray will cause a
3dB comer frequency to occur at 531kHz.
2-98 OPERA TIONAL AMPLIFIERS
Figure 23c shows a diode clamp protection scheme for an I-to-V
converter using low leakage diodes. Because the diodes are
connected to the op amp's summing junction, which is a virtual
ground, their leakage contribution is minimal.
R
0,,02 FD333
F0300
lN457
lN3595
Figure 23c. I-to- V Converter with Diode Input Protection
D/A CONVERTER BIPOLAR OUTPUT BUFFER
The circuit in Figure 24 provides 4 quadrant multiplication with
a resolution of 12 bits. The AD648 is used to convert the AD7S4S
CMOS DAC's output current to a voltage and provides the
Exceeding the negative common mode range on either input
terminal causes a phase reversal at the output, forcing the amplifier
output to the corresponding high or low state. Exceeding the
negative common mode on both inputs simultaneously forces
the output high. Exceeding the positive common mode range on
a single input doesn't cause a phase reversal, but if both inputs
exceed the limit the output will be forced high. In all cases,
normal amplifier operation is resumed when input voltages are
brought back within the common mode range.
necessary level shifting to achieve a bipolar voltage output. The
circuit operates with a 12-bit plus sign input code. The transfer
function is shown in Figure 25.
Figure 24. 12-8it Plus Sign Magnitude DIA Converter
SIGN BIT
o
o
1
BINARY NUMBER IN OAC REGISTER
ANALOG OUTPUT
1111 1111 1111
+ V'N
0000 0000 0000
0000 0000 0000
oVOLTS
oVOLTS
1111 1111 1111
- V'N x (409514096)
x (409514096)
NOTE: SIGN BIT AT ·0· CONNECTS THE NONINVERTING INPUT OF
A2 TO ANALOG COMMON
Figure 25. Sign Magnitude Code Table
The AD7S92 is a fully protected dual CMOS SPDT switch with
data latches. R4 and RS should match to within 0.01% to maintain
the accuracy of the converter. A mismatch between R4 and RS
introduces a gain error. Overall gain is trimmed by adjusting
R IN• The AD648's low input offset voltage, low drift over temperature, and excellent dynamics make it an attractive low power
output buffer.
The input offset voltage of the AD648 output amplifier results
in an output error voltage. This error voltage equals the input
offset voltage of the op amp times the noise gain of the amplifier.
That is:
Vos Output = Vos Input (1 +~B)
RFB is the feedback resistor for the op amp, which is internal to
the DAC. Ro is the DAC's R-2R ladder output resistance. The
value of Ro is code dependent. This has the effect of changing
the offset error voltage at the amplifier's output. An output
amplifier with a sub millivolt input offset voltage is needed to
preserve the linearity of the DAC's transfer function.
OPERA T10NAL AMPLIFIERS 2-99
The AD648 in this configuration provides a 700kHz small signal
bandwidth and 1.8V/jLs typical slew rate. The 33pF capacitor
across the feedback resistor optimizes the circuit's response.
The oscilloscope photos in Figures 26a and 26b show small and
large signal outputs of the circuit in Figure 24. Upper traces
show the input signal VIN. Lower traces are the resulting output
voltage with the DAC's digital input set to all I's. The circuit
settles to ± 0.01% for a 20V input step in 14jLs.
Figure 26a. Response to ± 20V p-p Reference Square
Wave
Figure 26b. Response to ± 100m V p-p Reference Square
Wave
DUAL PHOTODIODE PREAMP
The performance of the dual photodiode preamp shown in
Figure 27 is enhanced by the AD648's low input current, input
voltage offset, and offset voltage drift. Each photodiode sources
a current proportional to the incident light power on its surface.
Rp converts the photodiode current to an output voltage equal
to Rpx1s.
an error proportional to the preamp's noise gain (I + RplRsw,
where RSH is the photodiode shunt resistance. The amplifier's
input current will double with every 10DC rise in temperature
and the photodiode's shunt resistance halves with every IODC
rise. The error budget in Figure 28 assumes a room temperature
photodiode RSH of SOOMO, and the maximum input current
and input offset voltage specs of an AD648C.
An error budget illustrating the importance of low amplifier
input current, voltage offset, and offset voltage drift to minimize
output voltage errors can be developed by considering the equivalent circuit for the small (0.2mm2 area) photodiode shown in
Figure 27. The input current results in an error proportional to
the feedback resistance used. The amplifier's offset will produce
The capacitance at the amplifier's negative input (the sum of the
photodiode's shunt capacitance, the op amp's differential input
capacitance, stray capacitance due to wiring, etc.) will cause a
rise in the preamp's noise gain over frequency. This can result
in excess noise over the bandwidth of interest. Cp reduces the
noise gain "peaking" at the expense of signal bandwidth.
C,
RF
100M!l
CSH
20pF
RSH
500M!l
PHOTO DIODE
EQUIVALENT CIRCUIT
RF
100M!}
Figure 27. A Dual Photodiode Pre-Amp
2-100 OPERATIONAL AMPLIFIERS
TEMP
·C
RSH
(Mil)
Vos
(flV)
-25
0
+25
+50
+75
+85
15,970
2,830
500
88.5
15.6
7.8
150
225
300
375
450
480
(1 + RF/RsH)VOS
la
(pA)
laRF
TOTAL
0.30
2.26
10.00
56.6
320
640
30flV
262flV
1.0mV
5.6mV
32mV
64mV
181flV
495flV
1.36mV
6.40mV
35.3mV
70.6mV
151flV
233flV
360flV
800flV
3.33mV
6.63mV
Figure 28. Photodiode Pre-Amp Errors Over Temperature
INSTRUMENTATION AMPLIFIER
The AD648J's maximum input current of 20pA per amplifier
makes it an excellent building block for the high input impedance
instrumentation amplifier shown in Figure 29. Total current
drain for this circuit is under 6OOj1A. This configuration is
optimal for conditioning differential voltages from high impedance
sources.
The overall gain of the circuit is controlled by
the following transfer function:
Ro,
Gains of I to 100 can be accommodated with gain nonlinearities
of less than 0.01%. The maximum input current is 30pA over
the common-mode range, with a common-mode impedance of
over I x 10 120. The capacitors CI, C2, C3 and C4 compensate
for peaking in the gain over frequency which is caused by input
capacitance.
To calibrate this circuit, fIrst adjust trimmer Rl for common-mode
rejection with + 10 volts dc applied to the input pins. Next,
adjust R2 for zero offset at VOUT with both inputs grounded.
Trim the circuit a second time for optimal performance.
resulting in
The - 3dB small signal bandwidth for this low power instrumentation amplifier is 700kHz for a gain of 1 and 10kHz for
a gain of 100. The typical output slew rate is 1.8V/flS.
C3
15pF
R5
20k
R7
20k
Vo
R8
R6
20k
191k
R1
2k
C4
~ 15pF
FOR EACH
AMPLIFIER
+Vs 0
-Vs 0
o 1"F
O.1"F
1
.
tv.
AD548-PIN7
AD648-PIN8
~
+Vs
RlO OFFSET
-Vs
TRIM
PIN4
NOTE VALUES FOR ALL CAPACITORS WERE CHOSEN
FOR BEST RESPONSE FOR GAINS OF 1 TO 5.
THEY ARE NOT REQUIRED FOR GAINS ABOVE 5.
Figure 29. Low Power Instrumentation Amplifier
OPERATIONAL AMPLIFIERS 2-101
LOG RATIO AMPLIFIER
Log ratio amplifiers are useful for a variety of signal conditioning
applications, such as linearizing exponential transducer outputs
and compressing analog signals having a wide dynamic range.
The AD648's picoamp level input current and low input offset
voltage make it a good choice for the front-end amplifier of the
log ratio circuit shown in Figure 30. This circuit produces an
output voltage equal to the log base 10 of the ratio of the input
currents II and 12 , Resistive inputs Rl and R2 are provided for
voltage inputs.
compensation is provided by resistors R8 and RlS, which have
a positive 3500 ppml"C temperature coefficient. The transfer
function for the output voltage is:
Vour= IV 10g1O (hilI)
Frequency compensation is provided by Rll, R12, Cl, and C2.
Small signal bandwidth is approximately 300kHz at input currents
above lOOjLA and will proportionally decrease with lower signal
levels. Dl, D2, RB, and R14 compensate for the effects of the
two logging transistors' ohmic emitter resistance.
Input currents II and 12 set the collector currents of Ql and Q2,
a matched pair of logging transistors. Voltages at points A and
B are developed according to the following familiar diode
equation:
To trinI this circuit, set the two input currents to 10jLA and
adjust Vour to zero by adjusting the potentiometer on A3.
Then set h to 1JLA and adjust the scale factor such that the
output voltage is I V by trimming potentiometer RIO. Offset
adjustment for Al and A2 is provided to increase the accuracy
of the voltage inputs.
In this equation, k is Bolt2mann's constant, T is absolute temperature, q is an electron charge, and IES is the reverse saturation
current of the logging transistors. The difference of these two
voltages is taken by the subtractor section and scaled by a factor
of approxinIately 16 by resistors R9, RIO, and RS. Temperature
This circuit ensures a 1% log conformance error over an input
current range of 300pA to lmA, with low level accuracy limited
by the AD648's input current. The low level input voltage
accuracy of this circuit is limited by the input offset voltage and
drift of the AD64S.
AI
Vas ADJUST
200k
+ Vs ---'V'V'v-- - V s
FOR EACH AMPLIFIER
::g~:::=~:~~ ~.--""1~---OO +Vs
9"!0I~F
-r 01 f.l F
499k
+Vs
PIN4 ~.----1I""'I----O -Vs
I,IN
V, IN o-w~~----f--,.
V,IN o - W l . - . - - - - - - J
R8
lk
1;.lIN
VOUT
499k
-Vs
+VS~'-Vs
200k
A2
Vas ADJUST
= 1V X lOG10~
VOUT = 1V X LOG lOt,
01. 04 lN4148 DIODES
*R8, R15 1k +3500 ppmrc TC RESISTOR
TEL LAB 081 OR PRECISION RESISTOR PT146
ALL OTHER RESISTORS ARE 1% METAL FILM
Figure 30. Precision Log Ratio Amplifier
2-702 OPERATIONAL AMPLIFIERS
1IIIIIIII ANALOG
WDEVICES
Ultralow-Drift Op Amp
AD707 I
FEATURES
Very High dc Precision
15J.LV max Offset Voltage
O.1J.LVI"C max Offset Voltage Drift
O.35J.LV pop max Voltage Noise IO.1Hz to 10Hz)
8 V/J.LV min Open-Loop Gain
130dB min CMRR
120dB min PSRR
1nA max Input Bias Current
AD707 CONNECTION DIAGRAMS
NULL
TO-99 (H)
Package
-v,
AC Performance
O.3V/J.Ls Slew Rate
O.9MHz Closed Loop-Bandwidth
PRODUCT DESCRIPTION
The AD707 is a low-cost, high precision op amp with state-of-theart performance that makes it ideal for a wide range of precision
applications. The offset voltage spec of less than 1511 V is the
best available in a bipolar op amp, and maximum input offset
current is l.OnA. The top grade is the first bipolar monolith~
op amp to offer a maximum offset voltage drift of O",!~VIf('l. -',
and offset current drift and input bias current dri{t"a.'bcith~
specified at 2SpA/oC maximum.
,"" '~"
':~!:,' "" ' ,
The AD70Ts open-loop gain is 8V/I1V ~ut1l,~er the fuli
± lOY output range when driving a lkQ lOid.~' MaxiIllunl, inPut'
voltage noise is 3S0nVp-p (o.Ulz to lOH:I!):C~lt'aild PSRR
are 130dB and 120dB minimurti't~spettively:, ", ; '_ \, ;,' '
The AD707 is available in versions spedf'D;! ~~ to~~ial.
industrial and military temperature ranges:'rt is offered in 8-pin
plastic mini-DIP, small outline, hermetic cerdip and hermetic
TO-99 metal can packages. Chips and Mil Standard/883 parts
are also available.
Ne = NO CONNECT
Plastic (N),
and Cerdip (Q)
Packages
"<~~,
NULL
+v,
'~+lN r:::::t::t+--lV
OUTPUT
Small Outline
(R) Package
',"I,.
:'"
-v,
~t:,:" ~;: '; :
NC
NC
=
NO CONNECT
It "
_APPLtCATION HIGHLIGHTS
'L Th~''''D70Ts 13V/I1V typical open-loop gain and 140dB
typ~-i:l!I,!Ilmon-mode rejection ratio make it ideal for precision
'instijiinentation applications.
-~.
The precision of the AD707 makes tighter error budgets
possible at a lower cost.
3. The low offset voltage drift and low noise of the AD707
allow the designer to amplify very small signals without
sacrificing overall system performance.
4. The AD707 can be used where chopper amplifiers are required,
but without the inherent noise and application problems.
S. The AD707 is an improved pin-for-pin replacement for the
OP-07, OP-77 and the LTlOOl.
OPERA TIONAL AMPLIFIERS 2-103
•
SPEC IFICATIONS
(@
+25"1: and ±15Vdc, unless otherwise noted)
Conditions
Min
AD707J/A
Typ
INPUT OFFSET VOLTAGE
Imtlal
vs Temperature
Max
Units
25
0.3
45
5
0.03
7/S/S
0.2
=4
IS
0.1
25
ILV
ILW'C
ILV
ILV/month
mV
SO
100
0.3
=4
10
2.0
IS
2.5
40
40
OS
I 5
IS
1.5
3.0
25/25/35
OS
1.0
10
1.0
2.0
25
nA
nA
pArc
0.5
2.0
2.0
4.0
40
03
10
1.5
2.0
25/25/35
0.1
0.2
1.0
1.5
25
nA
nA
pArc
0.23
103
0.6
14
12
II 0
023
103
10.0
96
0.6
IS
130
110
14
032
014
012
35
09
027
o IS
20kll
V('M
OV
Average Drift
2
o I to 10Hz
f 10Hz
f 100Hz
f 1kHz
0.23
103
10.0
o IH7.1O 10Hz
f - 10Hz
f - 100Hz
f~ 1kHz
VCM
-
=13V
Tmm10Tmn
OPEN-LOOP GAIN
Typ
Rp
Tmm-Tmax
COMMON-MODE
RE]ECTION RATIO
Min
Tmm- Tmax
Tmm- Tmax
INPUT CURRENT NOISE
Max
10
0.1
IS
03
=4
Average Drift
INPUT VOLTAGE NOISE
AD707CIT
Typ
90
INPUT BIAS CURRENT
OFFSET CURRENT
Min
30
0.3
Long-Term Stability
Adjustment Range
AD707l~:tB/S
Max
120
120
10
I
10.0
96
140
140
I
96
0.35
\3
110
110
nV/v'lli
14
032
014
012
30
O.S
023
017
pAp-p
pA/Yfu
pA/v'fu
pA/v'fu
ILVp-L
nV/v'Hz
nV/v'lli
dB
dB
130
130
140
140
8
8
8
\3
\3
\3
120
120
\30
\30
dB
dB
0.9
0.3
OS
015
09
0.3
MHz
200
300
60
200
400
Gil
=V
=V
=V
VO' '" IOV
RJ OA()2:2kH
TmmtoTmax
RI.()AD~lkn
POWER SUPPLY
RE]ECTIONRATIO
\'I\'~
FREQUENCY RESPONSE
. ,:'
f~\ ~
" '•• 5 ':,:'.0 9
O'/S " 03
Closed-Loop Bandwidth
Slew Rate
V/ILS
INPUT RESISTANCE
Dlfferenual
24
100
200
45
13.5
12.5
12.0
14
\3,0
12.5
13.5
12.5
12.0
14
\30
125
13.5
12.5
12.0
14
\3,0
\2,5
120
\3,0
12.0
\3.0
12.0
\3,0
Common Mode
Mil
OUTPUT CHARACTERISTICS
Voltage
RIOA J)2:lOkH
RroAD 2:2kH
RroAD=-=lkH
Rr OAI>2:2k.H
Tmm10Tmax
OPEN-LOOP OUTPUT
60
ReSistance
POWER SUPPLY
Current, QUiescent
Power Consumpuon
V,==ISV,
No Load
V,==3V
TEMPERATURE RANGE
Operatmg, Rated Performance
Commercial
Industnal
MIlItary
-40"CIO +85"(;
- 55°C to + 125°C
PACKAGE OPTIONS'
Plastic (N-S)
Cerdlp (Q-S)
TO-99 (H-OSA)
SOIC(R-8)
60
60
II
2,5
rnA
2.5
3
2.5
70
7.2
90
70
72
9.0
AD707]N, AD707]R
AD707 AQ, AD707 AH
AD707]N
AD707AQ
AD707AH
AD707]R
90
9.0
AD707KN, AD707KR 1
AD707BQ, AD707BH
AD707SQ, AD707SH
AD707BQ/SQ
AD707BH/SH
AD707KR
90
9.0
AD707CQ, AD707CH
AD707TQ, AD707TH
AD707KN
NOTES
1AD707KR parts are production tested at + 25°C only All Tmm to T mall specrncatlonsare guaranteed but not 100% tested.
lSee Section 16 for package outhne mformatlon
All nun and max specifications are guaranteed Specifications m boldface are tested on all production Units at final electncal test.
Results from those tests are used to caJculate outgOing quality levels
SpecIfications are subJect to change without notice
2-104 OPERATIONAL AMPLIFIERS
70
72
AD707CQITQ
AD707CHITH
mW
thW
Dual Ultralow Drift
OpAmp
11IIIIIIII ANALOG
WDEVICES
AD708 I
AD708 CONNECTION DIAGRAMS
FEATURES
Very High dc Precision
30J.tV max Offset Voltage
0.3J.tVrC max Offset Voltage Drift
0.35J.tV p-p max Voltage Noise (0.1 to 10Hz)
8 Million VN min Open Loop Gain
130dB min CMRR
120dB min PSRR
Matching Characteristics
30J.tV max Offset Voltage Match
0.3J.tV/oC max Offset Voltage Drift Match
140dB min CMRR Match
Plastic DIP (N) Package
and
Cerdip (Q) Package
TOP VIEW
+Vs
AC PERFORMANCE
0.3V1J.ts Slew Rate
0.9MHz Closed-Loop Bandwidth
Single: AD707
Available in 8-Pin Plastic Mini-DIPs and Hermetic
Cerdip and TO-99 Metal Can Packages
PRODUCT D E S C R I P T I O N : . '. .....
The AD708 is a dual precision, low offset voltage and;~w.~l'fset.
'vh
""}fth '~'",
voltage drift, monolithic operational
liti'¢~"E~.4\mplifi~, ... ~;.t·")!i':\!,.
individually offers excellent dc prec' .
(I'IlU ·tniportl!n:t:~ci'l. ' U'
,':'
specifications show excellent stab'fl'ft?t
I"
TOP VIEW
,.
"krfiper~ture'. 'The',
'1"
NOTE PIN 4 CONNECTED TO CASE
"i,i~~!.~~jp,
offset voltage drift match of 0.3fl;Yt'C ilfd offset ~91~~ match d •
,,+.
of 30fLV are the best available matthing ~ificalioIlll for any
:i;,;.:4!.W>;bCATION HIGHLIGHTS
dual bipolar op amp.
Z;
The AD708's BV/fLV typical open loop gain and l40dB
The AD708 sets a new standard for dual precision op amps by"v
common-mode rejection make it ideal for precision instrumentation applications.
providing 8V/fLV min open loop gain and guaranteed max input
voltage noise of 350nV p-p. Input bias current is l.OnA max
2. The combination of outstanding matching and individual
guaranteed. Offset current drift is typically 1pArC and input
specfications makes the AD708 ideal for constructing high
bias current drift is 25pArC max. Both CMRR (BOdB min)
gain, precision instrumentation amplifiers.
and PSRR (l20dB min) are an order of magnitude improved
3. The low offset voltage drift and noise of the AD708 allows
over any available single monolithic op amp except the AD707.
the designer to amplify very small signals without sacrificing
1:
The AD708 is available in six performance grades. The AD708]
and AD708K are rated over the commercial temperature range
of 0 to +70'C and are available in plastic mini-DIP, cerdip, and
TO-99 packages. The AD708A and AD708B are rated over the
industrial temperature range of - 40'C to + 85'C and are available
in cerdip and TO-99 packages. The AD708S and AD708T are
rated over the military temperature range of - 5S'C to + 125°C
and are available in cerdip and TO-99 packages. Military versions
are available processed to MIL-STD-883B, Rev. c..
overall system preformance.
4. Unmounted dice are available for hybrid circuit applications.
5. The AD708 is an improved replacement for the OP-207 and
the LTl002.
OPERATIONAL AMPLIFIERS 2-105
•
SPEC IFICAli 0NS «~ + 25"C and ± 15V dc, unless othBlWise noted)
Model
Min
Conditions
AD708J/A/S
Typ
Max
INPUT OFFSET VOLTAGE
T nun- T max
Drift
Long-Term Stability
INPUT BIAS CURRENT
Tmm-Tmax
Average Drift
OFFSET CURRENT
VCM~OV
Tnun- Tmax
Average Drift
5
15
0.1
0.3
30
60
0.3
ILV
ILV
ILVI"C
ILV/month
1.0
2.0
IS
2.5
4.0
40
0.5
1.0
10
1.0
2.0
25
nA
nA
pA/'C
0.5
2.0
2
2.0
4.0
60
0.1
0.2
1.0
1.5
25
nA
nA
pAI"C
30
60
0.3
2.0
5.0
ILV
ILV
ILVI"C
nA
nA
dB
dB
dB
dB
dB
80
ISO
1.0
4.0
5.0
Offset Voltage Drift
Input Bias Current
Tmm-Tmax
120
115
Common·Mode Rejection
Tmm-Tmax
ISO
140
ISO
lIO
Power Supply ReJection
110
130
Tmm-Tmax
Channel Separation
Units
100
125/145/170
0.7
Toun-Tmax
0.1 to 10Hz
f~ 10Hz
f~ 100Hz
f~lkHz
INPUT CURRENT NOISE
AD708KIB/T
Typ
Max
30
50
0.3
0.3
MATCHING CHARACTERISTICS
Offset Voltage
INPUT VOLTAGE NOISE
Min
O.IHzto 10Hz
f ~ 10Hz
COMMON-MODE
Rejection Ratio
0.23
10.3
10.0
9.6
0.35
12
11.0
11.0
14
0.32
0.14
0.12
30
O.S
0.23
0.17
ILVp-P
nV/VHz
nVlVHz
nVlVHz
pAp-p
pA/VHz
pA/VHz
pA/VHz
140
140
dB
dB
13
13
13
V/ILV
V/ILV
V/ILV
OPEN LOOP GAIN
POWER SUPPLY
Rejection Ratio
Vs~+3Vto+ISV
lIO
TmmtoTmax
110
130
130
120
120
130
130
dB
dB
0.5
0.15
0.9
0.3
0.5
0.15
0.9
0.3
V/ILS
20
60
200
50
200
400
M!l
G!l
R LOAD",lOk!l
R LOAD "'2k!l
R LOAD ",lk!l
R LOAD "'2k!l
13.5
12.5
12.0
14
13.0
12.5
13.5
12.5
12.0
14
13.0
12.5
±V
±V
±V
Tmmto Tmax
12.0
13.0
12.0
13.0
±V
FREQUENCY RESPONSE
Closed Loop Bandwidth
Slew Rate
INPUT RESISTANCE
Differential
Common Mode
OUTPUT VOLTAGE
OPEN LOOP OUTPUT
Resistance
POWER SUPPLY
Current, QUIescent
Power Consumption
60
MHz
!l
60
4.5
5.5
4.5
5.5
rnA
135
12
165
18
±22
135
12
165
18
±22
'mW
mW
V
Vs~±15V,
No Load
±3V
Vs~
Operating Range
PACKAGE OPTIONS'
Plastic (N-S)
Cerdip (Q-S)
TO-99 (H-OSA)
±3
AD70SJN
AD70SJQ/AQ/SQ
AD70SJH/AH/SH
±3
AD70SKN
AD70SKQ/BQ/TQ
AD70SKH/BH/TH
NOTE
Section 16 for package outhne mformatlon
All rom and max specifications are guaranteed. Specifications In boldface are tested on
Specifications subject rochange without notIce
all productIOn umts at final electrical test. Results from those tests are used to calculate
outgomg quality levels.
I See
2-106 OPERA TIONAL AMPLIFIERS
r-IANALOG
WDEVICES
Precision Low-Cost
High-Speed BiFEl Op Amp
AD711 I
FEATURES
AC PERFORMANCE:
Settles to ±O.01% in 1,..s
16V/,..s min Slew Rate (AD711J)
3MHz min Unity Gain Bandwidth (AD711J)
DC PERFORMANCE:
O.25mV max Offset Voltage: (AD711C)
3,..V/oC max Drift: (AD711C)
200V/mV min Open-Loop Gain (AD711K)
4,..V p-p max Noise, O.1Hz to 10Hz (AD711C)
Available in Plastic Mini-DIP, Plastic SO, Hermetic
Cerdip, and Hermetic Metal Can Packages
MIL-STD-883B Parts Available
Dual Version Available: AD712
AD711 CONNECTION DIAGRAMS
TO-99
(H) Package
Plastic Mini-DIP (N)
Small Outline (R)
and
Cerdip (Q) Packages
INVERTING
INPUT
NON-INVERTING
INPUT
v-
TOP VIEW
NOTE PIN 4 CONNECTED TO CASE
TOP VIEW
~
~-'5V
Vas TRIM
PRODUCT DESCRIPTION
The AD711 is a high-speed, precision monolithic operational
amplifier offering high performance at very modest prices. Its
very low offset voltage and offset voltage drift are the results of
advanced laser wafer trimming technology. These performance
benefits allow the user to easily upgrade existing designs that
use older precision BiFETs and, in many cases, bipolar op
amps.
The superior ac and dc performance of this op amp makes it
suitable for active filter applications. With a slew rate of 16V/[J-s
and a settling time of I[J-s to ±0.01%, the AD711 is ideal as a
buffer for 12-bit D/A and AID Converters and as a high-speed
integrator. The settling time is unmatched by any similar IC
amplifier.
The combination of excellent noise performance and low input
current also make the AD711 useful for photo diode preamps.
Common-mode rejection of 88dB and open loop gain of 400V/mV
ensure 12-bit performance even in high-speed unity gain buffer
circuits.
The AD711 is pinned out in a standard op amp configuration
and is available in seven performance grades. The AD711J and
AD71IK are rated over 'the commercial temperature range of 0
to + 70°C. The AD711 A, AD711 Band AD711 C are rated over
the industrial temperature range of - 40°C to + 85°C. The
AD711S and AD711T are rated over the military temperature
range of - 55°C to + 125°C and are available processed to MILSTD-883B, Rev. C.
Extended reliability PLUS screening is available, specified over
the commercial and industrial temperature ranges. PLUS screening
includes 168-hour burn-in, as well as other environmental and
physical tests.
The AD711 is available in an 8-pin plastic mini-DIP, 8-pin
small outline, cerdip, or TO-99 metal can,
PRODUCT HIGHLIGHTS
I. The AD711 offers excellent overall performance at very
competitive prices.
2. Analog Devices' advanced processing technology and with
100% testing guarantees a low input offset voltage (0.25m V
max, C grade, 2mV max, J grade). Input offset voltage is
specified in the warmed-up condition. Analog Devices' laser
wafer drift trimming process reduces input offset voltage
drifts to 3[J-VrC max on the AD71IC.
3. Along with precision dc performance, the AD711 offers
excellent dynamic response. It settles to ±0.01% in I[J-s and
has a 100% tested minimum slew rate of 16V/[J-s. Thus this
device is ideal for applications such as DAC and ADC buffers
which require a combination of superior ac and dc
performance.
4. The AD711 has a guaranteed and tested maximum voltage
noise of 4[J-V p-p, 0.1 to 10Hz (AD711C).
5. Analog Devices' well-matched, ion-implanted JFETs ensure
a guaranteed input bias current (at either input) of 25pA max
(AD711C) and an input offset current of IOpA max (AD71IC).
Both input bias current and input offset current are guaranteed
in the warmed-up condition.
6. Available in chip form.
OPERATIONAL AMPLIFIERS 2-107
•
SPECIFICATIONS
(@
Model
Min
+ 25"CandVs = ±l5Vdc,unlessotherwisenoted)
AD711JIAIS
Typ
INPUT OFFSET VOLTAGE'
Initial Offset
Max
7
95
76
=
0.2
80
80
76176176
+ lOY
Offset Current, VeM = 0
5
100
Max
Min
AD711C
Typ
0.1
0.5
1.0
10
86
86
IS
15
INPUT BIAS CURRENT'
Either Input, VeM = 0
EIther Input at T mau
VeM ~ 0 (70"Cl85°ClI25°C)
EitherInput, VCM
AD711KIBIT
Typ
2/111
3/2/2
20/20/20
0.3
Taun to T max
vs. Temp.
vs. Supply
vs. Supply, T min to T max
Long Tenn Offset Stability
Min
2
110
Max
Units
0.25
0.45
3
rnV
rnV
".VfOC
dB
dB
,...V/month
IS
IS
50
1.1/3.2151
15
50
1.1/3.2/51
IS
25
1.6
pA
nA
20
10
100
25
20
5
100
25
20
5
SO
10
pA
pA
0.65
nA
Offset Current at T max
0.5711.6/26
(70°Cl85°CII25°C)
0.5711.6/26
FREQUENCY RESPONSE
Unity Gain, Small Signal
Full Power Response
Slew Rate, Unity Gain
Settling Time toO.Ol %3
Total Harmonic Distoruon
f~ 1kHz
3.0
4
200
20
I
16
RL"2kn,Vo~3VRMS
INPUT IMPEDANCE
Differential
Common-Mode
INPUT VOLTAGE RANGE
Differentlal 4
Common-Mode Voltage
Over Max Operating RangeS
Common-Mode Rejection Ratio
VCM "" ~lOV
Tmmto Tmax
VCM=±lIV
TmmtoT max
3.4
18
1.2
INPUT VOLTAGE NOISE
VoltageO. 1Hz to 10Hz
f~ 10Hz
f~ 100Hz
f~ 1kHz
f~ 10kHz
MHz
kHz
V/~s
I 2
I"
00003
%
3x 1012 115.5
3x 10"115.5
3x 10 12 115.5
3x 10"115.5
3xlO"1155
3xlO"1155
!lllpF
!lllpF
V
±20
± 20
± 20
+ 14.5, - 1l.5
+ 14.5, - II 5
+ 14.5,
+Vs-2V
70
70170170
I 2
4
200
20
I
00003
88
84
84
80
76176/76
3.4
18
0.0003
-Vs+4V
76
4
200
20
I
-Vs+4V
80
80
76
74
+Vs-2V
88
84
84
80
II 5
-Vs+4V
86
86
76
74
+Vs-2V
94
90
90
84
V
dB
dB
dB
dB
2
45
22
18
16
2
45
22
18
16
2
45
22
18
16
0.01
om
001
pA/Vlli
400
V/rnV
4.0
"VP-IC....
nV/V'Hz
nVry'H'Z
nV/Vlli
nV/\/H'Z
INPUT CURRENT NOISE
f~lkHz
OPEN LOOPGAIN6
Vo= ::tIOV,RL2::2kfl
Vo=::t IOV,R L?::2kO,
TnuntoTmax
OUTPUT CHARACTERISTICS
Voltage(?L RL2::2kfl
Voltage (?L R L2::2kfl,
Tnun to Tmax
Short-Circuit Current
POWER SUPPLY
Rated Performance
Operatmg Range
QUiescent Current
150
400
100/100/100
+ 13.9, -
+ 13, -12.5
13.3
+ 13.8,-13 I
:':: 12/:,:: 12/±12
2.5
V/rnV
+ 13, -12.5 + 13.9, - 13 3
+ 13, -12.5 + 13.9, -133
V
±12
V
rnA
±12
+ 13.8, - 13.1
25
AD711JN
AD711JR
AD711AQ, AD711SQ
AD711AH,AD711SH
±4.S
25
t
13 8,
13.1
25
± 15
±18
3.4
AD711J
AD711A
AD711S
2-108 OPERATIONAL AMPLIFIERS
200
100
± 15
±4.5
400
100
25
TEMPERATURE RANGE
Operating, Rated Pelformance
Commercial (0 to + 70°C)
Industrtal ( - 40°C to + 85°C)
MIlitary ( - 55°C to + 125°C)
PACKAGE OPTIONS'
Plastic (N-8)
SOIC(R-8)
Cerdip (Q-8)
TO-99 (H-OSA)
200
± 15
±18
3.0
AD711K
AD7IIB
AD711T
AD711KN
AD711KR
AD711BQ,AD711TQ
AD711BH,AD711TH
±4.5
25
AD7IIC
AD711CQ
AD711CH
±18
2.8
V
V
rnA
NOTES
IInput offset voltage spectfications are guaranteed. after 5 mlDutes of
operation at TA = + 25"C
28185
METALIZATION PHOTOGRAPH
DimenSIOns in inches and (mm).
current specifications are guaranteed maximum at either Input after
5 nunules of operatIOn at T A= + 25"C.For tugher temperature, the
current doubles every UfC.
JRefer to Figure 29.
4Defmed as voltage between inputs, such that neJ.rher exceeds ± lOY
from ground.
5TYPIcallyexceedmg -14.1V negative common-mode voltage on either
mput results In an output phase reversal
60pen Loop Gam IS specified WIth Vos both nulled and unnulled.
7See SeeOOD 16 for package outlme InCannat10n
SpecUicatlons subject to change Without nouce.
SpeCJficaaons 10 boldface are tested on all produc[lon uruts at fmal electncal
INVERTING
INPUT
J!lI.IIIIIIiI' -:-::-:--,
•
NONINVERTING
INPUT
test. Results from those tests are used to calculate outgomg quality levels
All min and max specificatIOns are guaranteed, although only those shown 10
boldface are tested on aU productIOn uruts.
ABSOLUTE MAXIMUM RATINGS l
Supply Voltage . . . . . .
Internal Power Dissipation
Input Voltage2 • • • • • • •
Output Short Circuit Duration
Differential Input Voltage . . .
Storage Temperature Range Q, H
Storage Temperature Range N
Operating Temperature Range
AD711J/K
AD71IAlB/C . . . . . . . .
. ±18V
500mW
. ±18V
Indefinite
+Vsand -Vs
- 65°C to + 150°C
- 65°C to + 125°C
. . . 0 to +70°C
- 40°C to + 85°C
AD711SIT
. . . . . . . . . . . . . - 55°C to + 125°C
Lead Temperature Range (Soldering 60 seconds) . . .. 300°C
NOTES
IStresses above those bsted under "Absolute MaxImum Ratings" may cause
permanent damage to the device. This is a stress ratmg only and functional
operation of the device at these or any other conditions above those
mdicated in the operational section of this specification IS not implied.
Exposure to absolute maxllIlum rating conditions for extended periods may
affect deVice reliability.
'For supply voltages less than ± 18V, the absolute ml1X1mum input voltage IS
equal to the supply voltage.
OPERATIONAL AMPLIFIERS 2-109
Typical Characteristics
20
30
20
/
II'
o
o
/
g,
wo
:z:>
~~
~~
,,-'
VR =2kn
ig
"~~.
.0
"
l
250C
,.
10
~
~ 15
/
lIJ
:!: 15V
g~
10
.
~
II
o
,.
100
10
10.
LOAD RESISTANCE - OHMS
Figure 2. Output Voltage Swing
vs. Supply Voltage
Figure 3. Output Voltage Swing
VS. Resistive Load
275
100
5
10
,
I
225
I
f
.
1
0
/
V
10
SUPPLY VOLTAGE :!:VOLTS
Figure 7. Input Voltage Swing
VS. Supply Voltage
IG
SUPPUES
15
0
SUPPl V VOLTAGE ± VOL15
1,
IL
20
0~0------~------~'0~----~'~5------~20
20
~
25
~
/
~
20
!
01
L
,
1
ill
IL
L,,;
,
175
10
SUPPLY VOlfAGE -
15
:!:
10-'
-60
20
24
.,
75
1,
i::J
MAX J GRADE LI~
<:25
-10
40
60
I-""
-.
COMMON MODE VOLTAGE _ VOLTS
Figure 7. Input Bias Current vs.
Common Mode Voltage
2-770 OPERATIONAL AMPLIFIERS
80
100
120
10.
oc
100k
1M
Figure 6. Magnitude of Output
Impedance vs. Frequency
VS.
20
-OUTPUT
CURREN~
£!
:;
,
45
:z:
I\.
"r':
i
z
:!
l' I"-
40
r--.
z
;;:
:----i'o..
14
.....
I"
">t:
Z
"
.......
i"-
35
12
10
10M
FREQUENCY - Hz
+ OUTPUT CURRENT
""",
22
,. ~
140
,.
50
i"-
i.. ,.
""
~
0
l"""-
E
Vs= :!:15V
250C
~
20
Figure 5. Input Bias Current
Temperature
VS.
2.
i
0
TEMPERATURE -
100
so
-40 -20
VOLTS
Figure 4. Quiescent Current
Supply Voltage
Iil
001
""
30
10
-60 -40 -20
0
20
40
60
80
100
120 140
AMBIENT TEMPERATURE - "C
Figure 8. Short Circuit Current
Limit VS. Temperature
-60 -40 -20
20
40
60
80
100 120
TEMPERATURE - "C
Figure 9. Unity Gain Bandwidth
VS. Temperature
140
Typical Characteristics
+100
--~ ~-
+80
110
'25
--- ----
-,
"
,,
""
""
""
\
Rl =2kU
2SOC
\
\
,
LOAD
+0
-20
/
'0
'00
,k
'M
'OOk
'Ok
-20"
'OM
i
IIII
80
.
95
o
o
Figure 12. Power Supply
Rejection vs. Frequency
1\
g
,
'"" '5
~
g
\
~
'0
4
Figure 13. Common Mode
Rejection vs. Frequency
1%
"
'M
-90
rg
V
~
i!'
:/
-no
-'0 05
10M
-130
'00
""" "~"'
.7
06
25
,
.
~/
, '5
~
'Ok
Figure 16. Total Harmonic
Distortion vs. Frequency
'OOk
'0
'0
'00
'k
/
'Ok
FREQUENCY - Hz
Figure 17. Input Noise Voltage
Spectral Density
lOOk
V
/,'
.~
I"-r-
,,
'0
Figure 15. Output Swing and
Error vs. Settling Time
:;
FREQUENCY - Hz
09
08
20
V
'k
\
\ 1\ \
SETTLING TIME - p.s
I - ~ ....
-120
001%
~,
"
~
-100
j
001%
01%
-8
r--..r-
'000
-80
01%
1%
\
Figure 14. Large Signal
Frequency Response
-70
3VRMS
Rt. = 2kn
CL = 100pF
J r/
INPUT fREQUENCY - Hz
FREQUENCY - Hz
P"....... ~
/J /
'\
lOOk
,M
lOOk
'Ok
6
"
ERROR
o
,k
~
RL=2kU
25"<:
Vs=±15V
I'
'00
g
...
....
'0
~
V/ /
on
~ 20
'M
lOOk
'Ok
'00
SUPPLY MODULATION FREQUENCY - Hz
25
on
25"<:
20
,
'0
20
IIII I 'k
'0
0
Q
'5
'0
::>
o
V s "" ± 15V SUPPLIESI
WITH 1V pop SINE
WAVE 25GC
on
Figure 11. Open Loop Gain vs.
Supply Voltage
~
Vs=±15V
VCM=lVp-p
,
r-..
r',SUPPLY
40
30
60
r-...
~
;a
SUPPLY VOLTAGE ± VOLTS
'00
,
~
z
0
20
Figure 10. Open Loop Gain and Phase
vs. Frequency
.....
~
.
.
V
+LJp!y
1'0.
'00
fREQUENCV - Hz
rg
,
/
\
'""
2kU 100pF
~
~
80
rg
GAIN
PHASE
r-. ...
'20
,
r\.
I
'00
+80"
o
o
/
100
/'
200
V
300
400
500
600
700
800
900
INPUT ERROR SIGNAL - mV
IAT SUMMING JUNCTION)
Figure 18. Slew Rate vs. Input
Error Signal
OPERA TlONAL AMPLIFIERS 2-111
•
Figure 20. THO. Test Circuit
+Vs
'5~-L~
__~~__~-L~~~~--J
-60 -40 -20
0
20
40
60
80
100
120
140
TEMPERATURE _ °C
Figure 19. Slew Rate vs. Temperature
Figure 21. Offset Null Configurations
SQUARE
WAVE
INPUT
-vs
Figure 22a. Unity Gain Follower
Figure 22b. Unity Gain Follower
Pulse Response (Large Signal)
Figure 22c. Unity Gain Follower
Pulse Response (Small Signal)
SkU
SkU
SQUARE
WAVE
INPUT
-v,
Figure 23a. Unity Gain Inverter
2-112 OPERATIONAL AMPLIFIERS
Figure 23b. Unity Gain Inverter
Pulse Response (Large Signal)
Figure 23c. Unity Gain Inverter
Pulse Response (Small Signal)
OPTIMIZING SETTLING TIME
Most bipolar high-speed D/A converters have curent outputs;
therefore, for most applications, an external op amp is required
for current-to-voltage conversion. The settling time of the converter/op amp combination depends on the settling time of the
DAC and output amplifier. A good approximation is:
v'(t, DAC)2 +
t. Total =
(t, AMP)2
The settling time of an op amp DAC buffer will vary with the
noise gain of the circuit, the DAC output capacitance, and with
the amount of external compensation capacitance across the
DAC output scaling resistor.
Settling time for a bipolar DAC is typically 100 to 500ns. Previously, conventional op amps have required much longer settling
times than have typical state-of-the-art DACs; therefore, the
amplifier settling time has been the major limitation to a high-speed
voltage-output D-to-A function. The introduction of the AD711l
712 family of op amps with their l,...s (to ±0.01% of fmal value)
settling time now permits the full high-speed capabilities of
most modem DACs to be realized.
In addition to a significant improvement in settling time, the
low offset voltage, low offset voltage drift, and high open-loop
gain of the AD711 family assures 12-bit accuracy over the full
operating temperature range.
The excellent high-speed performance of the AD711 is shown in
the oscilloscope photos of Figure 25. Measurements were taken
using a low input capacitance amplifier connected directly to the
summing junction of the AD711- both photos show the worst
case situation: a full-scale input transition. The DAC's 4k!l
[lOk!lIISk!l=4.4k!l] output impedence together with a 10k!l
feedback resistor produce an op amp noise gain of 3.25. The
current output from the DAC produces a lOY step at the op
amp output (0 to -lOY Figure 25a, -lOY to OV Figure 25b.)
Therefore, with an ideal op amp, settling to ± 1I2LSB (±0.01%)
requires that 375,...V or less appears at the summing junction.
This means that the error between the input and output (that
voltage which appears at the AD711 summing junction) must be
less than 375,...V. As shown in Figure 25, the total settling time
for the AD71l1AD565 combination is 1.2 microseconds.
Figure 24. ± 10V Voltage Output Bipolar DAC
AD711
SUMMING
AD711
JUNCTION
SUMMING
JUNCTION
,
J
-10V
,
t
•
;
1iIII.1
'1
'
t
1
OV
•
I
AD711
AD711
OUTPUT
OUTPUT
-10V
500n$
a. (Full-Scale Negative Transition)
b. (Full-Scale Positive Transition)
Figure 25. Settling Characteristics for AD711 with AD565A
OPERATIONAL AMPLIFIERS 2-113
•
OP AMP SETTLING TIME - A MATHEMATICAL
MODEL
The design of the AD711 iives careful attention to optimizing
individual circuit components; in addition, a careful tradeoff
was made: the gain bandwidth product (4MHz) and slew rate
(20V/lJ.s) were chosen to be high enough to provide very fast
settling time but not too high to cause a significant reduction in
phase margin (and therefore stability). Thus designed, the AD71I
settles to ±O.OI%, with a IOV output step, in under llJ.s, while
retaining the ability to drive a 2S0pF load capacitance when
operating as a unity gain follower.
If an op amp is modeled as an ideal integrator with a unity gain
crossover frequency of 0001271, Equation I will accurately describe
the small signal behavior of the circuit of Figure 26a, consisting
of an op amp connected as an I -to-V converter at the output of
a bipolar or CMOS DAC. This equation would completely
describe the output of the system if not for the op amp's finite
slew rate and other nonlinear effects.
When Ro and 10 are replaced with their Thevenin VIN and RIN
equivalents, the general purpose inverting amplifier of Figure
26b is created. Note that when using this general model, capacitance Cx is EITHER the input capacitance of the op amp if a
simple inverting op amp is being simulated OR it is the combined
capacitance of the DAC output and the op amp input if the
DAC buffer is being modeled.
V,N
Equation 1.
-R
Vo
lIN =
R(C f
+
roo
Cx)
S2
+
Figure 26b. Simplified Model of the AD711 Used as an
Inverter
(G
N
+
RC f ) s
+I
(1)0
where ~o = op amp's unity gain frequency
71
,
GN = "noise" gain of circuit
(I + ~J
This equation may then be solved for C r:
In either case, the capacitance C x causes the system to go from
a one-pole to a two-pole response; this additional pole increases
settling time by introducing peaking or ringing in the op amp
output. Since the value of C x can be estimated with reasonable
accuracy, Equation 2 can be used to choose a small capacitor,
CF , to cancel the input pole and optimize amplifier response.
Figure 27 is a graphical solution of Equation 2 for the AD7ll
with R = 4kfl.
Equation 2.
Cr
GN + 2YRCxooo + (l-GN)
Rooo
Rooo
= 2 -
In these equations, capacitor C x is the total capacitance appearing
at the inverting terminal of the op amp. When modeling a DAC
buffer application, the Norton equivalent circuit of Figure 26a
can be used directly; capacitance Cx is the total capacitance of
the output of the DAC plus the input capacitance of the op amp
,
(since the two are in parallel)
,.~~+-
"
__ __
~
2'
~L-
3.
+-__
__~__
4.
5'
~
6.
C,
Figure 27. Value of Capacitor CF vs. Value of Cx
Figure 26a. Simplified Model of the AD711 Used as a
Current-Out DAC Buffer
2-114 OPERATIONAL AMPLIFIERS
The input of the settling time fixture is driven by a flat-top
pulse generator. The error signal output from the false summing
node of Al is clamped, amplified by A2 and then clamped
again. The error signal is thus clamped twice: once to prevent
overloading amplifier A2 and then a second time to avoid overloading the oscilloscope preamp. The Tektronix oscilloscope
preamp type 7A26 was carefully chosen because it does not
overload with these input levels. Amplifier A2 needs to be a
verY high speed FET-input op amp; it provides a gain of 10,
amplifying the error signal output of AI.
Figure 28a. Settling Characteristics 0 to + 10V Step
Upper Trace: Output of AD711 Under Test (5VIDiv)
Lower Trace: Amplified Error Voltage (0.01%IDiv)
Figure 28b. Settling Characteristics 0 to -10V Step
Upper Trace: Output of AD711 Under Test (5VIDiv)
Lower Trace: Amplified Error Voltage (0.01%IDiv)
The photos of Figures 28a and 28b show the dynamic response
of the AD711 in the settling test circuit of Figure 29.
r----'
I 6i~i~~~~~t'E26 I
5p'
VERROR
o
x
I r::~r~ECTION I
~'Mn
HP2835
499kU
5
I
IL
20P':
T
'V
____ J
I
I
Figure 29. Settling Time Test Circuit
GUARDING
The low input bias current (l SpA) and low noise characteristics
of the AD7lI BiFET op amp make it suitable for electrometer
applications such as photo diode preamplifiers and picoampere
current-to-voltage converters. The use of a guarding technique
such as that shown in Figure 30, in printed circuit board layout
and construction is critical to minimize leakage currents. The
guard ring is connected to a low impedance potential at the
same level as the inputs. High impedance signal lines should not
be extended for any unnecessarY length on the printed circuit
board.
TO-99 (D) Package
Plastic DIP (N) Package
and
Cerdip (Q) Package)
Figure 30. Board Layout for Guarding Inputs
OPERATIONAL AMPLIFIERS 2-115
D/A CONVERTER APPUCATIONS
The AD711 is an excellent output amplifier for CMOS DACs.
It can be used to perform both 2 quadrant and 4 quadrant operation.
The output impedance of a DAC using an inverted R-2R ladder
approaches R for codes containing many Is, 3R for codes containing
a single I, and for codes containing all zero, the output impedance
is infinite.
Figures 33a and 33b show the settling time characteristics of the
AD711 when used as a DAC output buffer for the AD7545.
For example, the output resistance of the AD7545 will modulate
between llkH and 33kH. Therefore, with the DAC's internal
feedback resistance of IlkH, the noise gain will vary from 2 to
4/3. This changing noise gain modulates the effect of the input
offset voltage of the amplifier, resulting in nonlinear DACamplifier performance.
The AD711K with guaranteed 500....V offset voltage minimizes
this effect to achieve 12-bit performance.
Figures 31 and 32 show the AD711 and AD7545 (12-bit CMOS
DAC) configured for unipolar binary (2-quadrant multiplication)
or bipolar (4-quadrant multiplication) operation. Capacitor Cl
provides phase compensation to reduce overshoot and ringing.
a. Full-Scale Positive Transition
0811-080
b. Full-Scale Negative Transition
Figure 31. Unipolar Binary Operation
..
RZ·
2Ok,%
Figure 33. Settling Characteristics for AD711 with AD7545
R5
201<,%
The AD711C grade is specified at a maximum level of 4.0 ....V
p-p, in a 0.1 to 10Hz bandwidth. Each AD711C receives a
100% noise test for two 10-second intervals; devices with any
excursion in excess of 4.0 ....V are rejected. The screened lot is
then submitted to Quality Control for verification on an AQL
basis.
eFORVALUESOfR1ANDR2,
SEE TABLE I
Figure 32. Bipolar Operation
Rl and R2 calibrate the zero offset and gain error of the DAC.
Specific values for these resistors depend upon the grade of
AD7545 and are shown below.
TRIM
RESISTOR JN/AQISD
RI
R2
5000
1500
KNIBQITD LN/CQIVD GLNIGCQIGUD
2000
680
1000
330
200
6.80
Table I. Recommended Trim Resistor Values vs. Grades
oftheAD7545 for Voo= +5V
2-116 OPERATIONAL AMPLIFIERS
NOISE CHARACTERISTICS
The random nature of noise, particularly in the IIF region,
makes it difficult to specify in practical terms. At the same.
time, designers of precision instrumentation require certain
guaranteed maximum noise levels to realize the full accuracy of
their equipment.
All other grades of the AD711 are sample-tested on an AQL
basis to a limit of 6 ....V p-p, 0.1 to 10Hz.
DRIVING THE ANALOG INPUT OF AN AID
CONVERTER
An op amp driving the analog input of an AID converter, such
as that shown in Figure 34, must be capable of maintaining a
constant output voltage under dynamically changing load conditions. In successive-approximation converters, the mput current
IS compared to a series of switched trial currents. The comparison
point is diode clamped but may deviate several hundred millivolts
resulting in hIgh frequency modulation of AID input current.
The output Impedance of a feedback amplifier is made artificially
low by the loop gain. At high frequencies, where the loop gain
is low, the amplifier output impedance can approach its open
loop value. Most IC amplifiers exhibit a minimum open loop
output impedance of 2Sn due to current limiting resistors. A
few hundred microamps reflected from the change in converter
loading can introduce errors in instantaneous input voltage. If
the AID conversion speed is not excessive and the bandwidth of
the amplifier is sufficient, the amplifier's output will return to
the nominal value before the converter makes its comparison.
However, many amplifiers have relatively narrow bandwidth
yielding slow recovery from output transIents. The AD711 is
ideally suited to drive high speed AID converters since it offers
both wide bandwidth and high open-loop gain.
DRIVING A LARGE CAPACITIVE LOAD
The circuit in Figure 36 employs a lOOn isolatIon resistor which
enables the amplifier to drive capacitive loads exceeding lSOOpF;
the resistor effectively isolates the high frequency feedback from
the load and stabilizes the circuit. Low frequency feedback is
returned to the amplifier summing junction via the low pass
filter formed by the lOOn series resistor and the load capacitance,
C L . Figure 37 shows a typical transient response for this
connectlon.
499kU
30pF
+v,
J1
U
r-
499kU
INPUT
TYPICAL CAPACITANCE
lIMITFORVARIOUS
LOAD RESISTORS
Rl
2kH
10k.l1
:!olOV
ANALOG
INPUT
20kH
ClUPTO
1S00pF
-v,
1500pF
1000pF
Figure 36. Circuit for Driving a Large Capacitive Load
ANALOG COM
Figure 34. AD711 as ADC Unity Gain Buffer
Figure 37. Transient Response RL
=
2kfl, CL = 500pF
ACTIVE FILTER APPLICATIONS
a. Source Current = 2mA
b. Sink Current = 1mA
Figure 35. ADC Input Unity Gain Buffer Recovery Times
In active filter applications using op amps, the dc accuracy of
the amplifier is critical to optimal filter performance. The amplifier's offset voltage and bias current contribute to output
error. Offset voltage will be passed by the filter and may be
amplified to produce excessive output offset. For low frequency
applications requiring large value input resistors, bias currents
flowing through these resistors will also generate an offset
voltage.
In addition, at higher frequencies, an op amp's dynamIcs must
be carefully considered. Here, slew rate, bandwidth, and open-loop
gain playa major role in op amp selection. The slew rate must
be fast as well as symmetrical to minimize distortion. The amplifier's bandwidth in conjunction with the filter's gain will
dictate U1e frequency response of the filter.
The use of a high performance amplifier such as the AD7ll will
minimize both dc and ac errors in all active filter applications.
OPERATIONAL AMPLIFIERS 2-117
SECOND ORDER LOW PASS FILTER
Figure 38 depicts the AD711 configured as a second order Butterworth low pass ruter. With the values as shown, the comer
frequency will be 20kHz; however, the wide bandwidth of the
AD711 permits a comer frequency as high as several hundred
kilohertz. Equations for component selection are shown below.
RI
= R2 = user selected (typical values:
CI =
10k{} - 100k!l)
1.414
C2 =
0.707
(2'IT) (fcutoff) (RI)
(2'IT) (fcutoff) (RI)
An important property of ruters is their out-of-band rejection.
The simple 20kHz low pass ruter shown in Figure 38, might be
used to condition a signal contaminated with clock pulses or
sampling glitches which have considerable energy content at
high frequencies.
The low output impedance and high bandwidth of the AD711
minimize high frequency feedthrough as shown in Figure 39.
The upper trace is that of another low cost BiFET op amp
showing 17dB more feedthrough at 5MHz.
Where CI and C2 are in farads.
C1
560pF
Figure 39.
Figure 38. Second Order Low Pass Filter
9 POLE CHEBYCHEV FILTER
Figure 40 shows the AD711 and its dual counterpart, the AD712,
as a 9 pole Chebychev ruter using active frequency dependent
negative resistors (FDNR). With a cutoff frequency of 50kHz
and better than 90dB rejection, it may be used as an anti-aliasing
ruter for a 12-bit Data Acquisition System with 100kHz
throughput.
As shown in Figure 40, the filter is comprised of four FDNRs
CA, B, C, D) having values of 4.9395 x 10- 15 and 5.9276 x 10- 15
farad-seconds. Each FDNR active network provides a two-pole
response; for a total of 8 poles. The 9th pole consists of a O.OOII1F
capacitor and a 124k!l resistor at Pin 3 of amplifier A2. Figur!!
41 depicts the circuits for each FDNR with the proper selection
of R. To achieve optimal performance, the O.OOII1F capacitors
must be selected for 1% or better matching and all resistors
should have I % or better tolerance.
+15V
Figure 40. 9 Pole Chebychev Filter
Figure 41. FDNR for 9 Pole Chebychev Filter
2-118 OPERATIONAL AMPLIFIERS
Figure 42. High Frequency Response for 9 Pole Chebychev
Filter
1IIIIIIII ANALOG
WDEVICES
FEATURES
AC PERFORMANCE:
Settles to ±O.01% in 1,..,s
16V1,..,s min Slew Rate (AD712J)
3MHz min Unity Gain Bandwidth (AD712J)
DC PERFORMANCE:
O.30mV max Offset Voltage: (AD712C)
5,..,VrC max Drift: (AD712C)
200VlmV min Open Loop Gain (AD712K)
4,..,V p-p max Noise, O.1Hz to 10Hz (AD712C)
Available in Plastic, Hermetic Cerdip, and Hermetic
Metal Can Packages
MIL-STD-883B Parts Available
Dual Precision
High-Speed BiFEl Op Amp
AD712 I
AD712 FUNCTIONAL BLOCK DIAGRAM
TO-99
eH) Package
-v.
P1N41SIN ELECTRICAL
CONTACTWITHTHECASE
Plastic Mini-DIP eN) Package
and
Cerdip (Q) Package
PRODUCT DESCRIPTION
The AD712 is a high-speed, precision monolithic operational
amplifier offering high performance at very modest prices. Its
very low offset voltage and offset voltage drift are results of
advanced laser wafer trimming technology. These performance
benefits allow the user to easily upgrade existing designs that
use older precision BiFETs and, in many cases, bipolar op
amps.
The superior ac and dc performance of this op amp makes it
suitable for active filter applications. With a slew rate of 16V/,..,s
and a settling time of I,..,s to ± 0.01%, the AD712 is ideal as a
buffer for 12-bit D/A and AID Converters and as a high-speed
integrator. The settling time is unmatched by any similar IC
amplifier.
The combination of excellent noise performance and low input
current also make the AD712 useful for photo diode preamps.
Common-mode rejection of 88dB and open loop gain of 400V/mV
ensure 12-bit performance even in high-speed unity gain buffer
circuits.
The AD712 is pinned out in a standard op amp configuration
and is available in seven performance grades. The AD712J anf!
AD7l2K are rated over the commercial temperature range of 0
to + 70°C. The AD712A, AD712B and AD7I2C are rated over
the industrial temperature range of - 40°C to + 85°C. The
AD712S and AD712T are rated over the military temperature
range of - 55°C to + 125"C and are available processed to MILSTD-883B, Rev. C.
PRODUCT HIGHLIGHTS
I. The AD7I2 offers excellent overall performance at very
competitive prices.
2. Analog Devices' advanced processing technology and with
100% testing guarantees a low input offset voltage (O.3mV
max, C grade, 3mV max, J grade). Input offset voltage is
specified in the warmed-up condition. Analog Devices' laser
wafer drift trimming process reduces input offset voltage
drifts to 5,..,V/oC max on the AD712C.
3. Along with precision dc performance, the AD7I2 offers
excellent dynamic response. It settles to ±0.01% in I,..,s and
has a 100% tested minimum slew rate of 16V1,..,s. Thus this
device is ideal for applications such as DAC and ADC buffers
which require a combination of superior ac and dc
performance.
4. The AD712 has a guaranteed and tested maximum voltage
noise of 4,..,V p-p, 0.1 to 10Hz (AD712C).
5. Analog Devices' well-matched, ion-implanted JFETs ensure
a guaranteed input bias current (at either input) of 50pA max
(AD7I2C) and an input offset current of IOpA max (AD712C).
Both input bias current and input offset current are guaranteed
in the warmed-up condition.
6. Available in chip form.
Extended reliability PLUS screening is available, specified over
the commercial and industrial temperature ranges. PLUS screening
includes 168-hour burn-in, as well as other environmental and
physical tests.
The AD712 is available in an 8-pin plastic mini-DIP, cerdip, or
TO-99 metal can.
OPERA TlONAL AMPLIFIERS 2-119
SPECIFICATIONS
(@
+ 25"CandVs = :t:l5Vdc,unlessothelwisenotad)
AD712J/AIS
Model
Mia
INPUT OFFSET VOLTAGE'
Initial Offset
Tnun to Tmax
vs.Temp.
¥s. Supply
\'$.
Supply, TlQlntoTmax
76
76176176
Long·Tenn Offset Stability
Tnun toT max
Mia
80
80
Tn>
Mu
0.2
1/0.7/0.7
211.511.5
10
7
100
3.0
-Vs+4V
76
76176176
70
70/70/70
AD7l2C
T",
0.1
86
86
15
3
110
Mu
Units
0.30
0.60
5
mV
mV
"VI"C
dB
dB
"Vlmonth
15
75
20
75
20
SO
pA
0.6/1.6/26
1.7/4.8/77
100
2S
0.5/1.3/20
1.7/4.sn7
100
25
1.3
5
5
3.2
75
10
pA
pA
06/1.6/26
0.1/0.3/5
0.6/1.6/26
0.3
0.7
nA
0.3
0.6
5
10
mV
mV
"VI"C
.
1/0.7/0.7
211.511.5
10
25
120
90
120
90
16
Mia
25
3/1/1
41212
20I20I20
25
INPUT IMPEDANCE
Differential
Common Mode
Tnunto Tmu.
VCM= ±l1V
3/1/1
41212
20120120
7
9S
0.3/0.7/11
(70"Cl85"C1125"C)
VCM=±10V
0.3
10
MATCHINGCHARACfERISTICS'
Input OffsetVoItage
Input Offset Voltage T!IUD to Tmu
Input Offset Voltage VS. Temp
Input BIaS Current
Crosstalk'@ 1kHz
@IOOkHz
INPUT VOLTAGE RANGE
Differentlal6
Common·Mode Voltage
Over MIX Operating Range'
Common·Mode RqectlonRatio
Mu
15
INPUT BIAS CURRENT'
Either Input, VCM =0
Elther Input at Tm&l"
VeM ~ 0 (70"C185"C1125"C)
Either Input, VCM = + 10V
Offset Current, VCM = 0
Offset Current at Tmax
FREQUENCY RESPONSE
Unity Gain, Small Signal
Full Power Response
Slew Rate, Unity Gain
SetthngTime toO.OI%'
Total Harmonic Distortion
f= lkHz,RL~2k.O, Vo =3Vrms
AD712KIBIT
Tn>
4
200
20
I
3.4
18
I.2
4
200
3.4
JO
18
I
1.2
nA
pA
120
90
dB
dB
4
200
20
I
MHz
kHz
VI"s
,.s
1.2
0.0003
0.0003
0.0003
%
3xI0"115.5
3xlO"JI5.5
3xlO"115.5
3x 10"115,5
3x 10"115.5
3x 10"115.5
nllpF
nllpF
±20
±20
±2O
V
+ 14.5, -11.5 +Vs -2V
Vs+4V
+ 14.5, -11.5 +Vs-2V
88
Vs+4V
88
80
84
84
80
80
84
86
86
76
74
84
80
76
74
+14.5, -11.5 +Vs -2V
V
94
dB
90
90
dB
dB
84
dB
INPUT VOLTAGE NOISE
VoI_O.IHzto 10Hz
f~ 10Hz
f= 100Hz
f= 1kHz
f~ 10kHz
2
45
22
18
16
2
45
22
18
16
2
45
22
18
16
INPUT CURRENT NOISE
f= 1kHz
0.01
0.01
0.0\
pA/YHZ
400
VlmV
VlmV
OPEN LOOP GAIN
Vo= ±10V,RL~2kn
T maD to T rnu., RL~2kO
ISO
100/100/100
200
100
400
200
100
400
4
"Vp-p
nV/YHZ
nVIV'HZ
nV/YHZ
nVIV'HZ
OUTPUTCHARACfERISTICS
VoJtage
2'
"'"~
20
o
~
100
1k
10k
i\
r-.
1M
lOOk
1M
lOOk
~
10
o
10
'"
"~
Vs= ±15\1
::>
0
r-...
4
'"
o
"- r--.
V
= lkH
C t = 100pF
RL
-90
V
10M
0'
~,
""!:;'"
0 - 100
i!:
/
-110
i--
::>
~,
~
.... t--
"
/
~
~
10
10
/
V
1
-130
100
/
15
~
-~
1k
10k
FREQUENCY - Hz
Figure 16. Total Harmonic
Distortion vs. Frequency
lOOk
10
Figure 15. Output Swing and
Error vs. Settling Time
100
>
Z
09
07
20
'"'"0
>-
"~
"""'"o.
2'
0
V
06
\
SETTLING TIME - fls
~
I'
~
ill,
-.
\
,\..
-10
1000
-70
3V RMS I
-6
001%
~
\
.--
001%
01%
\
>- -4
~
::>
01%
1%
ERROR
-2
Figure 14. Large Signal
Frequency Response
Figure 13. Common Mode
Rejection vs. Frequency
-'0
1%
0
INPUT FREQUENCY - Hz
FREQUENCY - Hz
// /
//
/J /
;;
2'"C
\
>-
t\
"
2
!;
40
6
.....-::: p-:..
!;
RL=2kH
15
'"
!:;
r\
20
,
~
-120
/
o
Figure 10. Open Loop Gain and
Phase vs. Frequency
~
V
100
FREQUENCY - Hz
0>
~
25°C
110
Z
\
1M
lOOk
0>
+40" ~
\
""
-20
ffi
0
;;:
\
"'"
2kH 100pF
100
m
\
PHASE
10
120
\
GAIN
+0
12'
--- ---- -"
1
10
100
1k
10k
FREQUENCY _ Hz
lOOk
o
o
,/
....
V
V
/
100
200
300
400
500
600
700
800
900
INPUT ERROR SIGNAl- mV
(AT SUMMING JUNCTION)
Figure 17. Input Noise Voltage
Spectral Density
Figure 18. Slew Rate vs. Input
Error Signal
OPERATIONAL AMPLIFIERS 2-123
~,
INPUT
i20~t-1--r-+-i--~~+-~~
!
Figure 20. T.H.D. Test Circuit
VOUT
,.L--L~~~~~~~~~~~~
-80 -40 -20
0
ZO
40
10
80
2OkO
2.21<0
100 120 140
TEMPERATURE - -C
Figure 19. Slew Rate VB.
Temperature
Figure 21. Crosstalk Test Circuit
V'N
SQUARE
~~~
-VS
Figure 22a. Unity Gain Follower
Figure 22b. Unity Gain Follower
Pulse Response (Large Signal)
Figure 22c. Unity Gain Follower
Pulse Response (Small Signal)
SkU
SkU
SQUARE
WAVE
INPUT
-VS
Figure 23a. Unity Gain Inverter
2-124 OPERATIONAL AMPLIFIERS
Figure 23b. Unity Gain Inverter
Pulse Response (Large Signal)
Figure 23c. Unity Gain Inverter
Pulse Response (Small Signal)
OPTIMIZING SETTLING TIME
Most bipolar high-speed D/A converters have curent outputs;
therefore, for most applications, an external op-amp is required
for current-ta-voltage conversion. The settling time of the converter/op-amp combination depends on the settling time of the
DAC and output amplifier. A good approximation is:
to Total =
Vet. DAC)2 + (t. AMP)!
The settling time of an op amp DAC buffer will vary with the
noise gain of the circuit, the DAC output capacitance, and with
the amount of external compensation capacitance across the
DAC output scaling resistor.
Settling time for a bipolar DAC is typically 100 to 500ns. Previously, conventional op-amps have required much longer settling
times than have typical state-of-the-art DACs; therefore, the
amplifier settling time has been the major limitation to a high-speed
voltage-output D-to-A function. The introduction of the AD7111
712 family of op amps with their I ....s (to ±0.01% of final value)
settling time now permits the full high-speed capabilities of
most modem DACs to be realized.
In addition to a significant improvement in settling time, the
low offset voltage, low offset voltage drift, and high open-loop
gain of the AD7111AD712 family assures 12-bit accuracy over
the full operating temperature range.
The excellent high-speed performance of the AD712 is shown in
the oscilloscope photos of Figure 25. Measurements were taken
using a low input capacitance amplifier connected directly to the
summing junction of the AD712 - both photos show the worst
case situation: a full-scale input transition. The DAC's 4k!l
[IOkOIl8kO=4.4k!l) output impedance together with a 10kO
feedback resistor produce an op-amp noise gain of 3.25. The
current output from the DAC produces a 10V step at the op-amp
output (0 to -IOV Figure 25a, -lOY to OV Figure 25b.)
Therefore, with an ideal op-amp, settling to ± 1I2LSB (±0.01%)
requires that 375 ....V or less appears at the summing junction.
This means that the error between the input and output (that
voltage which appears at the AD712 summing junction) must be
less than 375 ....V. As shown in Figure 25, the total settling time
for the AD712/AD565 combination is 1.2 microseconds.
Figure 24. ± 10V Voltage Output Bipolar DAC
AD712
SUMMING
JUNCTION
AD712
SUMMING
JUNCTION
ov
AD712
AD712
OUTPUT
OUTPUT
-10V
a. (Full-Scale Negative Transition)
b. (Full-Scale Positive Transition)
Figure 25. Settling Characteristics for AD712 with AD565A
OPERATIONAL AMPLIFIERS 2-125
OP-AMP SETrLING TIME - A MATHEMATICAL
MODEL
The design of the AD712 gives careful attention to optimizing
individual circuit components; in addition, a careful tradeoff
was made: the gain bandwidth product (4MHz) and slew rate
(20V/ILS) were chosen to be high enough to provide very fast
settling time but not too high to cause a significant reduction in
phase margin (and therefore stability). Thus designed, the AD'712
settles to ±O.OI%, with a IOV output step, in under IlLS, while
retaining the ability to drive a 2S0pF load capacitance when
operating as a unity gain follower.
If an op-amp is modeled as an ideal integrator with a unity gain
crossover frequency of oool2'fr, Equation 1 will accurately describe
the small signal behavior of the circuit of Figure 26a, consisting
of an op-amp connected as an I-to-V converter at the output of
a bipolar or CMOS DAC. This equation would completely
describe the output of the system if not for the op-amp's fmite
slew rate and other nonlinear effects.
When Ro and 10 are replaced with their Thevenin V IN and RIN
equivalents, the general purpose inverting amplifier of Figure
26b is created. Note that when using this general model, capacitance Cx is EITHER the input capacitance of the op-amp if a
simple inverting op-amp is being simulated OR it is the combined
capacitance of the DAC output and the op-amp input if the
DAC buffer is being modeled.
V IN
Equation 1.
Vo
-R
lIN =
Figure 26b. Simplified Model of the AD712.Used as an
Invener
(G
::..:R:!,;(Cr:.!-+--"C",.x) s
2
)
1
+ -N+ RCfS+
000
000
where ~: =op amp's unity gain frequency
~
= "noise" gain of circuit
(1 + ~)
This equation may then be solved for Cr:
In either case, the capacitance Cx causes the system to go from
, a one-pole to a two-pole response; this additional pole increases
settling time by introducing peaking or ringing in the op-amp
output. Since the value of Cx can be estimated with reasonable
accuracy, Equation 2 can be used to choose a small capacitor,
CF , to cancel the input pole and optimize amplifier response.
Figure 27 is a graphical solution of Equation 2 for the AD712
withR = 4kO.
Equation 2.
Cr = 2 - GN + 2VRCxoo. + (1 ~)
Roo.
Roo.
In these equations, capacitor Cx is the total capacitance appearing
at the inverting terminal of the op-amp. When modeling a DAC
buffer application, the Norton equivalent circuit of Figure 26a
can be used directly; capacitance Cx is the total capacitance of
the output of the DAC plus the input capacitance of the op-amp
(since the two are in parallel).
x
"
Figure 27. Value of Capacitor CF vs. Value of Cx
Figure 26a. Simplified Model qf the AD712 Used as a
Current-Out DAC Buffer
2-126 OPERA TIONAL AMPLIFIERS
The photos of Figures 28a and 28b show the dynamic response
of the AD712 in the settling test circuit of Figure 29.
The input of the settling time fixture is driven by a flat-top
pulse generator. The error signal output from the false summing
node of Al is clamped, amplified by A2 and then clamped
again. The error signal is thus clamped twice: once to prevent
overloading amplifier A2 and then a second time to avoid overloading the oscilloscope preamp. The Tektronix oscilloscope
preamp type 7A26 was carefully chosen because it does not
overload with these input levels. Amplifier A2 needs to be a
very high-speed, FET-input op amp; it provides a gain of 10,
amplifying the error signal output of A l.
SV
I
I
I
I
·t !
'I
I
I '
Figure 28a. Settling Characteristics 0 to + 10V Step
Upper Trace: Output of AD712 Under Test (5VlDiv)
Lower Trace: Amplified Error Voltage (0.01%IDiv)
•
I
I
,
1-
I
c
Figure 28b. Settling Characteristics 0 to - 10V Step
Upper Trace: Output of AD712 Under Test (5VIDiv)
Lower Trace: Amplified Error Voltage (0.01%IDiv)
r----....,I
5pF
I TEXTRONIX 7A26
~i~~~SCOPE
I
i
20P':
V'":~:-r-nX
5 I,NPUTSEeTiON
HP2835
499kll
I 'Mil
I
T
I
I
V' I
L _____J
Figure 29. Settling Time Test Circuit
Plastic MiDi-DIP (N) Package
GUARDING
The low input bias current (ISpA) and low noise characteristics
of the AD712 BiFET op amp make it suitable for electrometer
applications such as photo diode preamplifiers and picoampere
current-to-voltage converters. The use of a guarding technique
such as that shown in Figure 30, in printed circuit board layout
and construction is critical to minimize leakage currents. The
guard ring is connected to a low impedance potential at the
same level as the inputs. High impedance signal lines should not
be extended for any unnecessary length on the printed circuit
board.
TO-99 (H) Package
and
4lm
l!:Y~ tC¥l)
~A&\,
,P 9 ~7
Cerdip(Q)Paekage
"1J
[Jo..5
o-4J
~
~
'...0
~
8
Figure 30. Board Layout for Guarding Inputs
OPERA TlONAL AMPLIFIERS 2-127
D/A CONVERTER APPLICATIONS
The AD712 is an excellent output amplifier for CMOS DACs.
It can be used to perform both 2 quadrant and 4 quadrant operation.
The outpUt impedance of a DAC using an inverted R-2R ladder
approaches R for codes containing many ls, 3R for codes containing
a single 1, and for codes containing all zero, the output impedance
is infinite.
For example, the output resistance of the AD7545 will modulate .
between llkO and 33kO. Therefore, with the DAC's interilal
feedback resistance of llkO, the noise gain will vary from 2 to
413. This changing noise gain modulates the effect of the input
offset voltage of the amplifier, resulting in nonlinear DACamplifier performance.
TRIM
RESISTOR JN/AQISD
KNIBQITD LN/CQIUD GLN/GCQIGUD
Rl
soon
2000
R2
1500
680
1000
330
200
6.80
Table I. Recommended Trim Resistor Values vs. Grades
of the AD7545 for Voo= +5V
Figures 33a and 33b show the settling time characteristics of the
AD712 when used as a DAC output buffer for the AD7545.
The AD712K with guaranteed 700,...Voffset Voltage minimizes
this effect to achieve 12-bit performance.
Figures 31 and 32 show the AD712 and AD7545 (12-bit CMOS
DAC) configured for unipolar binary (2 quadrant multiplication)
or bipolar (4 quadrant multiplication) operation. Capacitor Cl
provides phase compensation to reduce overshoot and ringing.
a. Full-Scale Positive Transition
DB11-DBO
b. Full-Scale Negative Transition
Figure 33. Settling Characteristics for AD712 with AD7545
DB11-08G
Figure 31. Unipolar Binary Operation
R2"
R4
2Ok1%
••
2Ok1%
NOISE CHARACTERISTICS
The random nature qf noise, particularly in the IIF region,
makes it difficult to specify in practical terms. At the same
time, designers of precision instrUmentation require certain
guaranteed maximum noise levels to realize the full accuracy of
their equipment.
The AD712C grade is specified at a maximum level of 4.0,...V
pop, in a 0.1 to 10Hz bandwidth. Each AD712C receives a
100% noise test for two 100second intervals; devices with any
excursion in excess of 4.0,...V are rejected. The screened lot is
then Submitted to Quality Control for verification on an AQL
v,.
basis.
All other grades of the AD712 are sample-tested on an AQL
basis to a limit of 6,...V pop, 0.1 to 10Hz.
-FORVALUESOFR1 ANDR2,
SEE TABLE I
Figure 32. Bipolar Operation
Rl and R2 calibrate the zero offset and gain error of the DAC.
Specific values for these resistors depend upon the grade of
AD7545 and are shown below.
2-128 OPERATIONAL AMPLIFIERS
DRIVING THE ANALOG INPUT OF AN AID
CONVERTER
An op amp driving the analog input of an AID convener, such
as that shown in Figure 34, must be capable of maintaining a
constant output voltage under dynamically-changing load conditions. In successive-approximation conveners, the input current
is compared to a series of switched trial currents. The comparison
point is diode clamped but may deviate several hundred millivolts
resulting in high frequency modulation of AID input current.
The output impedance of a feedback amplifier is made artificially
low by the loop gain. At high frequencies, where the loop gain
is low, the amplifier output impedance can approach its open
loop value. Most IC amplifiers exhibit a minimum open loop
output impedance of 2Sn due to current limiting resistors. A
few hundred microamps reflected from the change in convener
loading can introduce errors in instantaneous input voltage. If
the AID conversion speed is not excessive and the bandwidth of
the amplifier is sufficient, the amplifier's output will return to
the nominal value before the convener makes its comparison.
However, many amplifiers have relatively narrow bandwidth
yielding slow recovery from output transients. The AD712 is
ideally suited to drive high-speed AID conveners since it offers
both wide bandwidth and high open-loop gain.
DRIVING A LARGE CAPACITIVE LOAD
•
The circuit in Figure 36 employs a lOon isolation resistor which
enables the amplifier to drive capacitive loads exceeding I SOOpF;
the resistor effectively isolates the high frequency feedback from
the load and stabilizes the circuit. Low frequency feedback is
returned to the amplifier summing junction via the low pass
fJlter formed by the lOon series resistor and the load capacitance,
CL • Figure 37 shows a typical transient response for this
connection.
499kU
30pF
Jl
U
r-
499kH
INPUT
TYPICAL CAPACITANCE
liMIT FOR VARIOUS
LOAD RESISTORS
Rl
2kU
10k!!
20kU
:!:10V
ANALOG
INPUT
ClUPTO
1500pf
1500pF
1000pf
-v,
, Figure 36. Circuit for Driving a Large Capacitive Load
-15V
Figure 34. AD712 as ADC Unity Gain Buffer
Figure 37. Transient Response RL = 2kn, CL = 500pF
a. Source Current = 2mA
b. Sink Current = 1mA
Figure 35. ADC Input Unity Gain Buffer Recovery Times
ACTIVE FILTER APPLICATIONS
In active fJlter applications using op amps, the d.c. accuracy of
the amplifier is critical to optimal fJlter performance. The amplifier's offset voltage and bias current contribute to output
error. Offset voltage will be passed by the fJlter and may be
amplified to produce excessive output offset. For low frequency
applications requiring large value input resistors, bias currents
flowing through these resistors will also generate an offset
voltage.
In addition, at higher frequencies, an op-amp's dynamics must
be carefully considered. Here, slew rate, bandwidth, and open-loop
gain playa major role in op-amp selection. The slew rate must
be fast as well as symmetrical to minimize distortion. The amplifier's bandwidth in conjunction with the fJlter's gain will
dictate the frequency response of the fJlter.
The use of a high performance amplifier such as the AD712 will
minimize both dc and ac errors in all active fJlter applications.
OPERATIONAL AMPLIFIERS 2-129
SECOND ORDER LOW PASS FILTER
Figure 38 depicts the AD712 configured as a second order Butterworth low pass filter. With the values as shown, the corner
frequency will be 20kHz; however, the wide bandwidth of the
AD712 permits a corner frequency as high as several hundred
kilohertz. Equations for component selection are shown below.
Rl = R2 = user selected (typical values: 10kO - 100kO)
Cl (in farads) = (2,,)
(:;~~;) (Rl)
The low output impedance and high bandwidth of the AD712
minimize high frequency feedthrough as shown in Figure 39.
The upper trace is that of another low-cost BiFET op amp
showing 17dB more feedthrough at SMHz.
0.707
C2
An important property of filters is their out-of-band rejection.
The simple 20kHz low pass filter shown in Figure 38, might be
used to condition a signal contaminated with clock pulses or
sampling glitches which have considerable energy content at
high frequencies.
Cl
560pF
Figure 39.
Figure 38. Second Order Low Pass Filter
9 POLE CHEBYCHEV FILTER
Figure 40 shows the AD712 and its single counterpart, the
AD711, as a 9 pole Chebychev filter using active frequency
dependent negative resistors (FDNR). With a cutoff frequency
of SOkHz and better than 90dB rejection, it may be used as an
anti-aliasing filter for a 12-bit Data Acquisition System with
100kHz throughput.
As shown in Figure 40, the filter is comprised of four FDNRs
(A, B, C, D) having values of 4.939Sx 10- 15 and S.9276x 10- 15
farad-seconds. Each FDNR active network provides a two-pole
response; for a total of 8 poles. The 9th pole consists of a O.OOlfLF
capacitor and a 124kO resistqr at Pin 3 of amplifier A2. Figure
41 depicts the circuits for each FDNR with the proper selection
of R. To achieve optimal performance, the O.OOlfLF capacitors
must be selected for I % or better matching and all resistors
should have 1% or better tolerance.
+15V
Figure 40. 9 Pole Chebychev Filter
1-- - - -:;:- - -
--:;;v-,
01 ... F
~I
I
I
I
I
I
~ I
1
4
I
-15V
I
I
L 29~O=276E-15
A 24 9k FOR 4
9395E-15
01 ... F
I
499kH
_______
I
~
Figure 41. FDNR for 9 Pole Chebychev Filter
2-130 OPERA TlONAL AMPLIFIERS
Figure 42. High Frequency Response for 9 Pole Chebychev
Filter
rIIIANALOG
WDEVICES
FEATURES
AC PERFORMANCE
Settles to ±O.01% in 11ls
16V/IlS min Slew Rate
3MHz min Unity Gain Bandwidth
DC PERFORMANCE
O.25mV max Offset Voltage
10llVrC max Drift
200V/mV min Open Loop Gain
41lV pop max Noise, O.1Hz to 10Hz
Single Version Available: AD711, Dual: AD712
Available In Plastic and Hermetic Cerdip Packages
MIL-STD-883B Parts Available
Quad Precision
High-Speed BiFEl Up Amp
AD713 I
AD713 FUNCTIONAL BLOCK DIAGRAM
Plastic DIP (N) Package
and
Cerdip (Q) Package
OUTPUT
-IN
+IN
-Vs
+IN
-IN
OUTPUT
Along with dc precision, the AD713 offers exceptional dynamic
response. Itsettles to 0.01% in IfLsand has a 100% tested minimum
slew rate of 18V/fLS (AD713B).
The AD713 is pinned out in a standard quad op amp configuration
and is available in seven performance grades. The AD713J and
AD713K are rated over the commercial temperature range of 0
to + 70°C. The AD713A, AD713B and AD713C are rated over
the industrial temperature range of - 40°C to + 85°C. The
AD713S and AD713T are rated over the military temperature
range of - 55°C to + 125°C and are available processed to MILSTD-883B, Rev. C. The AD713 is available in an 14-pin plastic
DIP or 14-pin cerdip.
3. Precision Data Acquisition Systems: Common-mode rejection
of 88d,B and open-loop gain of 400V/mV ensure 12-bit accuracy
even in high-speed data acquisition circuits.
4. Photodiode Preamps: The combination of excellent noise
performance and low input current makes the AD713 useful
as a photodiode preamp.
S. The AD713 is an enchanced replacement for the TL074,
LF4l4 and other quad op amps in applications where precision
and demanding ac performance are essential.
OPERATIONAL AMPLIFIERS 2-131
SPECIFICATIONS
(@ +25"CandVs
= ::t 15V dc, unless oIhIIWise noIIIIO
AD713JINS
Tn>
Modd
Mill
INPUT OFFSET VOLTAGE'
Initial Offset
0.3
Tmlft10 T lrlllx
VI. Temp
16
VI Supply
vs. Supply, T nun to T_
Long-Term Offset Stabdny
76
76176/76
Max
Min
0.25
2.0
3.5/3.513.5
30130130
9S
AD713K/BIT
Tn>
80
80
12
100
M..
Mill
01
0.5
1.5
20
86
86
Max
Valts
0.25
0.75
10
mV
mV
"VFC
dB
dB
110
15
15
15
AD7I3C
Tn>
p.V/month
INPUT BIAS CURRENT'
Either Input, VCM =0
Either Input at T me.,
VCM =0(70"C185"ClI25"C)
EIther Input, VCM = + IOV
Ofi'selCUtrenl, VCM = 0
40
ISO
50
10
3 419 61154
200
35
40
ISO
50
5
3.419.61154
200
35
40
100
pA
50
5
6.4
ISO
IS
nA
pA
pA
10
nA
03
06
15
10
mV
mV
"VFC
pA
dB
dB
Offset Current at T DUll.
(70"CI85"C1125"C)
08122/36
0.8122/36
MATCHING CHARACTERISTICS'
Input Offset Voltage
Input Offset Voltage T nun to T mar.
InputOffsetVolugevs Temp
Input hs Current
Crosstalk (if 1kHz
(iIIOOkHz
FREQUENCY RESPONSE
Unlly Gam, Small Signal
Full Power Response
Slew Rate, Unity Gam
1
2
40
25
3.4
120
120
90
90
34
4
200
20
I
16
SeuhngTnnetoO,OIO/O
18
Total HarmonIC Distorbon
f= lkHz,RI.~2kO, Vo=3Vnns
INPUT IMPEDANCE
DdT....tiol
Common Mode
INPUT VOLTAGE RANGE
Dd'ferenual"
Common-Mode Voltage
Over Max Operating Ranges
Common-Mode Re,ectlon RatiO
VOM= ~IOV
Tmm10Tmu
VCM = ~l1V
TmmlOT mill
INPUT VOLTAGE NOISE
VoltageO.lHzto 10Hz
f= 10Hz
f= 100Hz
f= 1kHz
f= 10kHz
4
200
20
I
MHz
kHz
Vlf1s
1.2
%
3x 10"115.5
IlllpF
IlllpF
3x 101l115.5
~20
+ 14 5, -11 5
-II
+13
-II
78
76/76176
88
84
72
84
70170170
80
INPUT CURRENT NOISE
f= 1kHz
80
7S
74
88
84
84
86
86
80
80
76
".
00003
V
V
V
94
90
90
84
dB
dB
dB
dB
"VP-L
2
45
22
18
16
2
45
22
18
16
2
45
22
18
16
001
001
0.01
pA/YHz
400
400
V/mV
nV/y'H~
nV/YHz
nVlV'Hz
nV/v'Hz
OPEN LOOP GAIN'
Vo= ± lOV,R1 '2:2k{}
T nun to T rnall.> RI 2:2kfl
ISO
10011001100
400
200
200
ISO
100
V/mV
OUTPUTCHARACTERISTICS
+ 13, -12.5
Voltage
I
I
~
is
>
0
... -2
j
lL
I
J..i
~ ~4
"o -6 r-
-10
II
OUTPUT
INPUT
a
18
~
14
i
10
15
20
SUPPLY VOLTAGE '- ±v
Figure 10. Output Voltage Swing vs.
Supply Voltage
2-136 OPERATIONALAMPLIFIERS
~
L
lOOk
o
1020
12
3040 SO 60 70 8090
TIME -J,!5
Figure 9. Voltage Follower Large
Signal Pulse Response
Vs = ±15V
TA '" +2SoC
V'
RL'" 1OttO
IL
11
.1
il
0.1 ,
~
~ 10
5
=!15V
=+2SOC
-
4
~ 16
./
8
TA = +2S"C
i... 22
...~ 20
~
10
r0+-
Vs = ±15V
26
~ 24
4
o
10k
28
RL
36
!il32
i
lk
Figure 8. Input Noise Current vs.
Frequency
40
>
100
FREQUENCV - Hz
Figure 7. Input Noise Voltage vs.
Frequency
n
-8
~ 10-26
10-18
lOOk
10k
Figure 6. Broad Band Noise vs.
Source Resistance
~!: !~~Yc
~10_15111
100
lk
SOURCE RESISTANCE -
Figure 5. Common Mode Rejection
vs. Frequency
~
ffi
~
0
1
~
vs.
10kHz
10-1kHz
.a'
10
10
FREQUENCY - Hz
10_13~[B.
Vs !15V
10M
-~
10M
Figure 4. Open Loop Phase Response
vs. Frequency
,
1M
~1,10- \OOk~'
,--
\.
; ~:
-180
"-
tOOk
=!15V
=+25°C
~
~3D
-135
10k
Figure 3. Open Loop Gain
Frequency
l\
~
~50
~ 40
I'
if
~
"'
~80
"-
-90
~
I 90
lk
FREQUENCY - Hz
100
!1l
100
°c
Figure 2. Bias Current vs.
Temperature
Vs = ±15V
TA = +2SOC
r'\.
r-
60
TEMPERATURE _
vs.
l'-...
10
'\..
100
140
~
r'\.
$ 200
~
Vs = :t15V
TA '" +25°C
\
"
r--..
......
8
D.;!
0.5
1.0
2.0
5.0
10
LOAD RESISTANCE - kg
Figure ". Output Voltage Swing vs.
Load Resistance
o
100
1k
10k
......
lOOk
1M
FREQUENCY - Hz
Figure 12. Output Voltage Swing
Frequency
vs.
1IIIIIIII ANALOG
Precision, 500ns Settling
WDEVICES
FEATURES
AC PERFORMANCE
SOOns Settling to 0.01% for 10V Step
1.Sl1s Settling to 0.002S% for 10V Step
7SV/I1s Slew Rate
0.0003% Total Harmonic Distortion (THD)
13MHz Gain Bandwidth - Internal Compensation
>200MHz Gain Bandwidth (G=1000)External Decompensation
>1000pF Capacitive Load Drive Capability with
10V/I1s Slew Rate - External Compensation
DC PERFORMANCE
0.2SmV max Offset Voltage (AD744C)
311V/oC max Drift (AD744C)
2S0V/mV min Open-Loop Gain (AD744B)
411V p-p max Noise. 0.1Hz to 10Hz (AD744C)
Available in Plastic Mini-DIP. Hermetic Cerdip
and Hermetic Metal Can Packages
MIL-STD-883B Processing Available
APPLICATIONS
Output Buffers for 12-Bit. 14-Bit and 16-Bit DACs.
ADC Buffers. Cable Drivers. Wideband
Preamplifiers and Active Filters
PRODUCT DESCRIPTION
The AD744 is a fast-settling, precision, FET input, monolithic
operational amplifier. It offers the excellent dc characteristics of
the AD711 BiFET family with enhanced settling, slew rate, and
bandwidth. The AD744 also offers the option of using custom
compensation to achieve exceptional capacitive load drive
capability.
The single-pole response of the AD744 provides fast settling:
SOOns to 0.01%. This feature combined with its high dc precision,
makes it suitable for use as a buffer amplifier for 12-bit, 14-bit
or 16-bit DACs and ADCs. Furthermore, the AD744's low total
harmonic distortion (THD) level of 0.0003% and gain bandwidth
product of 13MHz make it an ideal amplifier for demanding
audio applications. It is also an excellent choice for use in active
fIlters in 12-bit, l4-bit and 16-bit data acquisition systems.
The AD744 is internally compensated for stable operation as a
unity gain inverter or as a noninverting amplifier with a gain of
two or greater. External compensation may be applied to the
AD744 for stable operation as a unity gain follower. External
compensation also allows the AD744 to drive l000pF capacitive
loads, slewing at IOVI."s with full stability. Alternatively, external
decompensation may be used to increase the gain bandwidth of
the AD744 to over 200MHz at high gains. This makes the AD744
ideal for use as ac preamps in digital signal processing (DSP)
front ends.
BiFET Op Amp
AD744 I
AD744 CONNECTION DIAGRAMS
T()"99
(H) Package
•
NUlll
COMPENSATION
-v
NOTE PIN 4 CONNECTED
TO CASE
Plastic Mini·DIP (N) Package
and
Cerdip (Q) Package
NULl!
DECOMPENSATION
5
COMPENSATION
range of - SsoC to + l2SoC and are available processed
STD-883B, Rev. C.
to
MIL-
Extended reliability PLUS screening is available, specified over
the commercial and industrial temperature ranges. PLUS screening
includes a 168-hour burn-in, as well as other environmental and
physical tests.
The AD744 is available in an 8-pin plastic mini-DIP, 8-pin
cerdip, or TO-99 metal can.
PRODUCT HIGHLIGHTS
1. The AD744 is a high-speed BiFET op amp that offers excellent
performance at competitive prices. It outperforms the OP42,
OPA606, LF3S6 and LF400.
2. The AD744 offers exceptional dynamic response. It settles to
0.01% in SOOns and has a 100% tested minimum slew rate of
SOV/."s (AD744B).
3. The combination of Analog Devices' advanced processing
technology, laser wafer drift trimming and well-matched ionimplanted JFETs provide outstanding dc precision. Input
offset voltage, input bias current, and input offset current
are specified in the warmed-up condition; all are 100%
tested.
4. The AD744 has a guaranteed and tested maximum voltage
noise of 4."V p-p, O.IHz to 10Hz (AD744C).
The AD744 is available in seven performance grades. The AD744J
and AD744K are rated over the commercial temperature range
of 0 to + 70°C. The AD744A, AD744B and AD744C are rated
over the industrial temperature range of - 40°C to + 8SoC. The
AD744S and AD744T are rated over the military temperature
OPERA TIONAL AMPLIFIERS 2-137
SPECIFICAli 0NS
(@
+ 25"& and ± 15V dc, unless otherwise noted)
Model
Conditions
INPUT OFFSET VOLTAGE'
Initial Offset
Offset
vs. Temp
vs. Supplyl
vs. Supply
Long.Term Stablhty
Min
AD744JIAIS
Typ
03
Tnun- Tmax
Tmm- Tmalt
82
82182182
5
95
Max
Mi.
AD744K1BIT
Typ
1.0
21212
20/20/20
0.25
88
88
15
5
100
Max
Mia
0.5
1.0
10
AD744C
Typ
0.10
92
92
15
2
110
Max
Units
0.25
0.45
3
mV
mV
jivre
dB
dB
j..lVlmonth
15
INPUT BIAS CURRENT3
Ellherlnpul
Either Input (it T max
J,K
A,B,C
S,T
Eu:herInpul
Offset Current
Offset Current GI T max
I,K
A,B,C
S,T
VCM""OV
VCM=OV
30
100
30
100
70"C
85'C
125'C
VCM=
0.7
19
31
40
20
2.3
6.4
102
150
50
0.7
19
31
40
10
2.3
6.4
102
ISO
70"C
85'C
125'C
04
1.3
20
1.1
32
52
02
06
10
1.1
3.2
52
-I
8
V o =20Vp-p
-I
45
G~ -I
f=lkHz
13
600
75
05
+ lOY
VCM=OV
VCM=OV
50
30
50
1.9
32
40
10
100
20
0.6
13
pA
nA
nA
nA
pA
pA
nA
.A
nA
FREQUENCY RESPONSE
Gam BW, Small Signal
Full Power Response
Slew Rare, UnnyGam
SetthngTlmetoO 01%4
Total HarmoDic
DistortIOn
G~
G~
INPUT IMPEDANCE
Dlfferenual
Common Mode
INPUT VOLTAGE NOISE
09
13
600
75
05
9
50
0.9
13
600
75
0.5
MHz
kHz
00003
0.0003
00003
%
3x 10 12 115.5
3x 10 12115.5
3x 10 12 1155
3x 1012 115 5
3x 10 12115,5
3x 10"115.5
llllpF
llllpF
~20
~20
+ 14 S, -ll.S
-11
VCM=::!:IOV
Tm,ntoTmax
VCM=::!:l1V
Tm,nto Tmax
78
76/76/76
72
70170170
.'
V/j..ls
09
Rl~2kn
Vo =3Vrms
INPUT VOLTAGE RANGE
Dtfferenuat 5
Common-Mode Voltage
Over Max Operating Range6
Common-Mode Re)ecnon Rano
9
50
~20
+ 14.5, -11.5
+ 14.5, -ll.S
+13
88
84
84
80
-11
82
80
78
74
+13
88
84
84
80
-11
8'
86
80
76
+13
94
90
90
84
V
V
V
dB
dB
dB
dB
~~/~
0,1 to 10Hz
f= 10Hz
f= 100Hz
f= 1kHz
f= 10kHz
2
45
22
18
16
2
45
22
18
16
2
45
22
18
16
INPUT CURRENT NOISE
f=lkHz
001
001
001
pAlYHz
OPEN LOOPGAIN 7
Vo=::!: lOY
RW ADz:2kn
TmmtoTmax
400
V/mV
V/mV
OUTPUT CHARACTERISTICS
Voltage
Current
Capacnive Load 8
POWER SUPPLY
Rated Performance
Operatmg Range
QUIescent Current
RI oAD~2kn
TmmtoTmax
Short,Clfcuit
Gam=-1
200
100/100/100
400
250
100
400
250
ISO
+13, -12.5
+ 13.9, -13 3
+ 13 8, - 13,1
25
+ 13, -12.5
+ 13,9, - 13.3
+ 13.8, - 13 I
25
+ 13, -12.5 + 13 9, -13.3
::!:12/:!:12/±12
±12
1000
3.5
±4,5
±18
35
4.0
TEMPERATURE RANGE
Operatmg, Rated Performance
CommerCial (0 to + 70;C)
Industrial ( - 40°C to + 8S"C)
Mdltary( - S5"Cto + 12SOC)
AD744)
AD744A
AD744S
AD744K
AD744B
AD744T
PACKAGE OPTIONS9
8-Pm PlastiC Mini-DIP (N-8)
8-Pm Cerdlp (Q-8)
TO-99 Metal Can (H-08A)
AD744)N
AD744AQ, AD744SQ
AD744AH, AD744SH
AD744KN
AD744BQ,AD744TQ
AD744BH,AD744TH
NOTES
'Input Offset Voltage specifications areguarameed after 5 mmutes of operation at T A"" + 25"C
2PSRRtestcondiuons' +V<;= 15V, - V<;", IZVto 18Vand + V.. = IZVto 18V, - V.. = -ISV
3SIas Current Specifications are guaranteed maximum at either Input after 5 mlDutes of operatIOn at T A= + ZS"C.
For higher temperature, the current doubles every IO"C.
4Gam= -I,R, =Zk,C1 = lOpF,refertoFlgure25.
sDefined as voltage between mputs, such that neither exceeds ± IOV from ground
&ryplcaJlyexceedlDg - 14.1 V negative common-mode voltage on either mput results m an output phase reversal.
70pen_Loop Gam IS specified with Vos both nulled and unnulled.
8Capacltlve load drive specified for CcOMI' = 20pF with [he deVice connected as shown m Figure 32.
Under these conditions, slew rate = 14V/I1sand 0 01% settlmg time = I. 511S tYPical.
Refer [0 Table II for optimum compensatIon while dnvmg a capaclt1ve load
9See SectIOn 16 for package outline mformatlon.
SpectficatlOos subject [ochange Without notice.
Specifications m boldface are tested on aJl productIOn unltsat final electrical test. Results from those tests are used to
calculate outgoingquaJltyleveis All mm and max specifications are guaranteed, although only those shown m boldface
are tested on all production umts.
2-138 OPERA TlONALAMPLlFIERS
1000
V
V
rnA
pF
±18
4.0
V
V
rnA
~15
~15
±18
5.0
nV/VHz
nV/YHz
nV/Vih
+13 8, -13.1
25
1000
~15
±4.S
±12
4
±4.S
35
AD744C
AD744CQ
AD744CH
ABSOLUTE MAXIMUM RATINGS'
Supply Voltage . . . . . .
. ±18V
Internal Power Dissipation ..
500mW
Input Voltage2 • • • • • • • • •
. ±18V
Output Short Circuit Duration
Indefinite
Differential Input Voltage . . .
+Vs and -Vs
Storage Temperature Range Q, H
- 65°C to + 150°C
Storage Temperature Range N
- 65°C to + 125°C
Operating Temperature Range
AD744J/K
. . . 0 to +70°C
AD744A1B/C . . . . . . . .
- 40°C to + 85°C
AD744SIT . . . . . . . . .
- 55°C to + 12SoC
300°C
Lead Temperature Range (Soldering 60 sec)
NOTES
,
lStresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only) and functional
operation of the device at these or any other conditions above those indicated in tbe operational section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
device reliability.
'For supply voltages less than ± J8V, the absolute maximum input voltage
is equal to the supply voltage.
OPERA TIONAL AMPLIFIERS 2-139
•
Typical Characteristics
20
35
~
v
/
/
5
/
+/f
V R =2kU
~
V
l
+ 25°C
0
5
10
15
SUPPLY VOLTAGE :t:VOLTS
20
o
o
5
3.
L
~
IL
:!: 15 VOLTS SUPPLIES
~OUT
+25~
10
4or------,-------r------,-------,
.L
5
2.
15
/
lL
•
Rl ",2kn
,.
,....-
•
SUPPLY VOLTAGE :!:VOLTS
Figure 1. Input Voltage Swing vs.
Supply Voltage
"...- r--
100
,.k
lk
LOAD RESISTANCE - OHMS
Figure 2. Output Voltage Swing vs.
Supply Voltage
·
Figure 3. Output Voltage Swing vs.
Resistive Load
•
10·
10
,
35~----+-----_b,-~=f====~
I~
·
30~----~-------+------1-------4
,
25~----~~-----+-------r------4
·
V
ll - I--
60
40 -20
o
SUPPLY VOLTAGE - VOLTS
Figure 4. Quiescent Current vs.
Supply Voltage
1
+20 +40 +60 +80 +100+120+140
TEMPERATURE _·c
24
vV
0
/
V
./
I"
2.
18
,
10k
1k
-OUTPUT
CURRENT
/
l"-
V
+ OUTPUT
CURRENT
r----
5
~ ['--"
" ~ "-
16
Vs=:!:lSV
+2S"C
I"
"-
f"
'"
3
2
12
-5
0
5
COMMON-MODE VOLTAGE - VOLTS
Figure 7. Input Bias Current vs.
Common-Mode Voltage
2-140 OPERA TIONAL AMPLIFIERS
,.
10
-60
10M
Figure 6. Magnitude of Output
Impedance vs. Frequency
14
-10
1M
tOOk
FREQUENCY - Hz
22
0
0
o.1
7
26
0
0
COMP=Opf
V
Figure 5. Input Bias Current vs.
Temperature
0
V
V
,
10- 1
COMP:::25pf
1
"
200~------~5L-----~10~----~,5~----~~
IL
0
40
20
0
+20 +40 +60 +80 +100+120+140
TEMPERATURE - OC
Figure 8. Short Circuit Current Limit
vs. Temperature
1I
-60 -40 -20
0
i",
'"
'",-
+20 +40 +60 +80 +100 +120+140
TEMPERATURE - ·C
Figure 9. Gain Bandwidth Product
vs. Temperature
+5 0
+90
,
I
h
+4 0
+40 ' "
~ :--L~:D
'\
~+3 0
+45
\ \
50pF
LOAO---+, \
0
GAIN I
I
I II
PHASE--
0
~1
~2
II
0
10k
"~
9 +1 0
1
~
1\
I
LOAD
1M
FREQUENCY - Hz
I
10M
I
I
PHASE- 0
SkU RLOAO
OpF OR l000pF CLOAD
CeoMP = 25pF
45
0
"'OpF
LOAD
100M
-2 0
10k
II I
lOOk
'1l
ZI1 0
\
"~
1\
0
~10 5
\
~
~ogo.:ci -4
I
I
1\
I
10M
100
-45
5
100M
,
-,
10
30
'"
-tRi'"
,,
'\
I 1111
I 1111
lk
,
1;
~
+ 25°C
V s "" ±15V
\ [\
:: 10
::>
10k
FREQUENCV - Hz
"1\
lOOk
.
2
~
0
~
-2
~
~
001%
'
I--
1%~:t \
JRROR
001%
I--
... -4
::>
-6
o
10k
100k
1M
FREQUENCY - Hz
10M
Figure 14. Large Signal Frequency
Response
-10
\
01
02
03
04
80
70
1//
~
7 VOLTS rms OUTPUT
-120
V/
/
100
/
0
/
.... -110
/"
0
/
I
i/
lk
10k
Figure 16. Total Harmonic Distortion
vs. Frequency, Circuit of Figure 20
(G= 10)
"\;0-'-'-'-i'~00c'-.LJ.J';;1k:-'-.L..I..!I;';;Okc'-~1\\;00;;:'kL..J.J.'\\;M""'~'0M
FREQUENCY - Hz
Figure 17. Input Noise Voltage
Spectral Density
.--
V
/
/
0
lOOk
08
/
0
3 VOLTS rms OUTPUT
FREQUENCY _ Hz
07
/
0
I II
06
0
V/
!g -100
05
Figure 15. Output Swing and Error
vs. Settling Time
-80
V
I
o
SETILING TIME - f.Ls
-70
-130
VI
-8
1M
Figure 13. Common~Mode and
Power Supply Rejection vs.
Frequency
-90
20
/ II
I J
1%-r %
:;;
RL-2kll
0> 15
5
15
/ /1
i:!"
r\
~ 20
o
RsouAcE""kU
100
o
>
o
Vs=.±lSV
1 VOLT p.p SINE·WAVE INPUT
+25OC
30
g
:;
+P5RR
.
~
II
4(J
:;
'"
~
'" 25
,~~RR
10
Figure 12. Open Loop Gain vs.
Supply Voltage
35
"
5
SUPPLY VOLTAGE :tVOLTS
Figure ". Open Loop Gain and
Phase vs. Frequency CcoMP =25pF
100
/
0
\
FREQUENCY _ Hz
Figure 10. Open Loop Gain and
Phase vs. Frequency CcoMP=OpF
90
/
2000
0
5
20
25
10
10
10
270
390
1000
0
2
5
7
7
-
-3dB
Bandwidth
(MHz)
75
37
14
12.5*
2.5**
2.3**
75
50
37*
1.2
1.2
1.0
0.85
0.60
*lnto large capacitive load. the AD744's 25mA output current limit sets the slew rate of the amplifier,
in VI"", equal to 0.025 amps divided by the value of C LOAD In ",F. Slew rate is specified into rated
max C LOAD except for cases marked *, which are specified with a 50pF load.
**Bandwidth with C LEAD adjusted for minimum settling time.
Table II. Recommended Values of CCOMP vs. Various Load Conditions for the
Circuits of Figures 31 and 32.
Using Decompensation to Extend the Gain Bandwidth
Product
When the AD744 is used in applications where the closed-loop
gain is greater than 10, gain bandwidth product may be enhanced
R2"
Rl"
+V.
by connecting a small capacitor between Pins I and 5 (Figure
33). At low frequencies, this capacitor cancels the effects of the
chip's internal compensation capacitor, CcoMP, effectively decompensating the amplifier.
Due to manufacturing variations in the value of the internal
CcoMP, it is recommended that the amplifier's response be
Y'N
optimized for the desired gain by using a 2 to 10pF trimmer
capacitor rather than using a fIXed value.
Rl
R2
(0)
(0)
Ik
100
100
10k
10k
lOOk
Gain
Follower
11
101
1001
-31m
Gain
Inverter Bandwidth
10
100
1000
2.5MHz
760kHz
225kHz
GainIBW
Product
25MHz
76MHz
225MHz
~
O.1p.F
"SEE TABLE III
Figure 33. Using the Decompensation Connection to Extend
Gain Bandwidth
Table III. Performance Summary for the Circuit of
Figure 33
OPERATIONAL AMPLIFIERS 2-145
ruGH-SPEED OP AMP APPLICATIONS
AND TECHNIQUES
DAC Buffers (I-to-V Converters)
Digital-to-analog converters which use bipolar transistors to
switch currents into (or out of) their outputs can achieve very
fast settling times. The AD565A, for example, is specified to
settle to 12 bits in less than 250ns, with a current output. However,
in many applications, a voltage output is desirable, and it would
be useful - perhaps essential - that this I-to-V conversion be
accomplished without increasing the settling time or without
degrading the accuracy of the DAC.
Figure 34 is a schematic of an AD565A DAC using an AD744
output buffer. The 10pF CLEAD capacitor compensates for the
DAC's output capacitance, plus the 5.5pF amplifier input
capacitance.
Figure 35 is an oscilloscope photo of the AD744's output voltage
with a + lOY to OV step applied; this corresponds to an all "Is"
to all "Os" code change on the DAC. Since the DAC is connected
in the 20V span mode, lLSB is equal to 4.88mV. Output settling
time for the AD565/AD744 combination is less than 500ns to
within a 2.44mV, 1I2LSB error band.
Figure 35. Upper Trace: AD744 Output Voltage for a
to OV Step, Scale: 5mVldivision.
Lower Trace: Logic Input Signal, Scale: 5Vldivision.
BIPOLAR OFFSET ADJ.
GAIN
ADJ
loon
Figure 34. ± 10V Voltage Output Bipolar DAC Using the
AD744 as an Output Buffer
2-146 OPERATIONALAMPLIFIERS
+ 10V
A HIGH-SPEED, 3 OP AMP INSTRUMENTATION
AMPLIFIER CIRCUIT
The instrumentation amplifier circuit shown in Figure 36 can
provide a range of gains from unity up to 1000 and higher. The
circuit bandwidth is 4MHz at a gain of I and 750kHz at a gain
of 10; settling time for the entire circuit is less than 1ILS to
within 0.01% for a 10V step, (G= 10).
While the AD744 is not stable with 100% negative feedback (as
when connected as a standard voltage follower), phase margin
and therefore stability at unity gain may be increased to an
acceptable level by placing the parallel combination of a resistor
and a small lead capacitor between each amplifier's output and
its inverting input terminal.
The only penalty associated with this method is a small bandwidth
reduction at low gains. The optimum value for CLEAD may be
determined from the graph of Figure 41. This technique can be
used in the circuit of Figure 36 to achieve stable operation at
gains from unity to over 1000.
CIRCUIT GAIN
Figure 37. The Pulse Response of the 3 Op Amp
Instrumentation Amplifier. Gain = " Horizontal Scale:
O.5p.sldiv, Vertical Scale: 5V1div. (Gain = 10)
=~ + 1
*t 5pF - 20pF
,
(TRIM FOR BEST SETTUNG TIMEI
SENSE
5PF
Figure 38. Settling Time of the 3 Op Amp Instrumentation
Amplifier. Horizontal Scale: 500nsldiv., Vertical Scale,
Pulse Input: 5V/div. Output Settling: lmVldiv.
J
REFERENCE
'VOLTRONICS SP20 TRIMMER CAPACITOR OR EQUIVALENT
uRATIO MATCHED 1% METAL FILM RESISTORS
0--,....--••
+Vs
+:1
+15VO
t F
COMMO
+II ~
t~F
0 - -.....- _ .
-1SVO
-v.
r-----------1.
Itt
I
'~
+
PIN7
1p.F
O.1p.f
I
:
I
rEAC
H
AMPURER
I
I r'P.F
r 0 1P.F
I____________
.. PIN4
I
.JI
FOR OPTIONAL
OFFSET ADJUSTMENT.
TRIM At. A3 USING TRIM
PROCEDURE SHOWN IN
FIGURE21.
Figure 36. A High Performance, 3 Op Amp Instrumentation
Amplifier Circuit
Gain
I
2
10
100
Rc.
NC
10k!l
2.02k!l
201!l
Bandwidth
3.5MHz
2.SMHz
IMHz
290kHz
TSettle(O.Ol%)
1.SJ.l.S
1.0J.l.S
1J.l.s
SJ.l.S
Minimizing Settling Time in Real-World Applications
An amplifier with a "single pole" or "ideal" integrator open-loop
frequency response will achieve the minimum possible settling
time for any given unity-gain bandwidth. However, when this
"ideal" amplifier is used in a practical circuit, the actual settling
time is increased above the minimum value because of added
time constants which are introduced due to additional capacitance
on the amplifier's summing junction. The following discussion
will explain how to minimize this increase in settling time by
the selection of the proper value for feedback capacitor, CL •
If an op amp is modeled as an ideal integrator with a unity gain
crossover frequency, fo, Equation I will accurately describe the
small signal behavior of the circuit of Figure 39. This circuit
models an op amp connected as an I-to-V converter.
Equation 1 would completely describe the output of the system
if not for the op amp's fmite slew rate and other nonlinear effects.
Even considering these effects, the fme scale settling to <0.1%
will be determined by the op amp's small signal behavior.
Table IV. Performance Summary for the Three Op Amp
Instrumentation An:'plifier Circuit
OPERATIONAL AMPLIFIERS 2-147
Equation 1.
CcoMP
(optional}
Vo
lIN = ---'-="":=-':::.
s+1
CLOAD
Where Fo = the op amp's unity gain crossover frequency
GN = the "noise" gain of the circuit ( 1 + ~)
This Equation May Then Be Solved for CL :
Equation 2.
Figure 40. A Simplified Model of the AD744 Used as an
Inverting Amplifier
In these equations, capacitance Cx is the total capacitance appearing at the inverting terminal of the op amp. When modeling
an I-to-V converter application, the Norton equivalent circuit of
Figure 39 can be used directly. Capacitance Cx is the total
capacitance of the output of the current source plus the input
capacitance of the op amp, which includes any stray capacitance
at the op amp's input.
CcoMP
(optional)
As an aid to the designer, the optimum value of C L for one
specific amplifier connection can be determined from the graph
of Figure 41. This graph has been produced for the case where
the AD744 is connected as in Figures 39 and 40 with a practical
minimum value for CSTRAY of 2pF and a total Cx value of
7.5pF.
The approximate value of CL can be determined for almost any
application by solving Equation 2. For example, the AD565/AD744
circuit of Figure 34 constrains all the variables of Equation 2
(~= 3.25, R = IOkO, Fo = 13MHz, and C x = 32.5pF). Therefore,
under these conditions, C L = IO.5pF.
35
30
'I ;\ 1\
'I /\ \N=l
'/V
'/V, A~N~ \
'/V/ ,\1\
\
Figure 39. A Simplified Model of the AD744 Used as a
Current-to-Voltage Converter
When Ro and 10 are replaced with their Thevenin V IN and RIN
equivalents, the general purpose inverting amplifier model of
Figure 40 is created. Here capacitor C x represents the input
capacitance of the AD744 (5.5pF) plus any stray capacitance
due to wiring and the type of IC package employed.
In either case, the capacitance C x causes the system to go from
a one-pole to a two-pole response; this additional pole increases
settling time by introducing peaking or ringing in the op amp's
output. If the value of Cx can be estimated with reasonable
accuracy, Equation 2 can be used to choose the correct value for
a small capacitor, CL , which will optimize amplifier response. If
the value of Cx is not known, CL should be a variable capacitor.
2-148 OPERATIONALAMPLIFIERS
G,,='
rr-[>fiGNY
o /VYU
IN THIS REGION
Ct.MD
= OPFIC/I'
GN =1TOx
100
~
~~
1k
10k
VALUE OF RESISTOR R - OHMS
lOOk
Figure 41. Practical Values of CL vs. Resistance of R for
Various Amplifier Noise Gains
~ANALOG
WDEVICES
Dual Precision, 500ns Settling
BiFET Op Amp
AD746
FEATURES
AC PERFORMANCE
500ns Settling to 0.01% for 10V Step
75V/p,s Slew Rate
0.0003% Total Harmonic Distortion (THO)
13MHz Gain Bandwidth
AD746 CONNECTION DIAGRAMS
v+
DC PERFORMANCE
0.25mV max Offset Voltage (AD746C)
3p,VI"C max Drift (AD746C)
250V/mV min Open Loop Gain (AD746B)
4p,V pop max Noise, 0.1Hz to 10Hz (AD746C)
v-
APPLICATIONS
Output Buffers for 12- and 14- Bit DACs,
ADC Buffers, Cable Drivers, Wideband
Preamplifiers and Active Filters
Available in 8-Pin Plastic SOIC, Mini-DIP, Hermetic
Cerdip, and Hermetic Metal Can Packages.
PRODUCT DESCRIPTION
The AD746 is a dual fast-settling, precision, FET in
operational amplifier. It offers the excellent dccha
of the AD711 BiFET family with enhanc~· s '
and bandwidth. The AD746 is inter~Y.~d
operation as a unity gain invert$~.otMi~.nmHivertiAA
with a gain of two or greater "~'~~_~__ ,,~~~ ~;(~';l; ,0"" - ,"'lr '-~ , ':~tI
The single pole response of the A~746 pr!l~e~#~t s~tttifl
to 0.01%. This feature combined with·it~!bigh"'it1155
llilpF
~lpF
±20
+14.5, -11 5
-ll
VCM "" ±IOV 78
TnuntoTIIW< 76/76/76
VCM= ±llV 72
TnuntoTmax 70/70170
+13
74
-ll
86
86
DO
76
+13
94
90
90
84
INPUT CURRENT NOISE
f=lkHz
001
OPEN LOOP GAIN'
Vo= ±IOV
RLOAo:2:2kO ISO
TnuntoTmax 75/75165
300
175
75
300
200
100
+ 13 9, -13.3
+ 13, -12.5
±12
+ 13.9, -13 3
+138,-13.1
25
+13,-12.5 + 13.9, -13.3
+ 13 8, -13.1
±12
25
POWER SUPPLY
Rated Performance
Operating Range
QUiescent Current
RLOAO~21d1
Tnunto Tmax
Short-ClrCUlt
+13, -12.5
±12/::!::12/±12
+ 13.8, -13 1
25
±lS
±lS
±4.S
TEMPERATURE RANGE
Operatlllg, Rated Performance
Commercial (0 to +7O"C)
Industnal ( - 40"C to + 85°C)
Military ( - 55°C to + 125°C)
7.0
±18
10.0
AD746J
AD746A
AD746S
±4.S
70
nV/YHz
nV/YHz
nVf\/Hz
001
pAlYHz
300
V/mV
V/mV
V
V
mA
±lS
±18
8.0
AD746K
AD746B
AD746T
V
V
V
dB
dB
dB
dB
~~/~
2
45
22
18
16
0.Ql
.'
%
2
45
22
18
16
Current
0.9
0.0003
0.1 to 10Hz
f""IOHz
(",,100Hz
f=lkHz
f= 10kHz
OUTPUT CHARACTERISTICS
Voltage
MH,
kHz
V/p.s
Rl~2kn
Vo=3Vrms
INPUT VOLTAGE RANGE
Dtfferential5
Common-Mode Voltage
Over Max Operating Range6
Common-Mode Rejection Ratio
13
600
75
0.5
±4.S
70
±18
8.0
V
V
mA
AD746C
PACKAGEOPTIO~S~
SOIC(R-8)
Plastlc(l'\·8)
Ccrdlp(Q_8)
TO-99 (1I-0SA)
AD746JR
AD746JN
AD746AQ,AD746SQ
AD746AH,AD746SH
NOTES
llnput Offset Voltage specificatiOns are guaranteed after 5 manutes of operatlonatT A"" + 25°C.
2PSRRtestcondltiOns +Vs= 15V, -Vs= 12Vtol8Vand +Vs= 12Vto 18V, -Vs= -ISV.
3B18sCurrent Specmcanonsare guaranteed maxtmum at either Input after 5 mmutes of operation at T A = + 25°C
For hlghertemperature, the current doubles every life
4Matching IS defmed as the difference between parameters of the two ampltfiers.
sDefined as voltage between mputs, such tbat nelther exceeds ± IOV from ground
li
I
~
2
~
rJ)
0
I-
0.01%
::::>
"- -2
1°k~~--~.---~----+----4----~----4
I-
::::>
0
-4
-6
-s
-10
0
0,1
0.2
0.3
0.4
0.5
SETTLING TIME -
0,6
0,7
o.s
,-,s
OPERATIONALAMPLlFlERS 2-151
2-152 OPERATIONALAMPLIFIERS
Single Supply, Low Power
Precision Op Amp
AD821 I
1IIIIIIII ANALOG
WDEVICES
AD821 FUNCTIONAL BLOCK DIAGRAM
FEATURES
True Single Supply Operation:
Input and Output Voltage Ranges
Include Ground
Output Voltage Swing to 50mV of Each Rail
Low Power: 400~A Supply Current max
250~V Input Offset Voltage
1.3MHz Gain Bandwidth Product
3V/~s Slew Rate
Single and Dual Supply Capability
NULL
APPLICATIONS
Battery Powered Precision Instrumentation
Strain Gage Signal Conditioners
Instrumentation Amplifiers
Thermocouple Amplifiers
Multiple Limit Threshold Detection
12- to 14-Bit Data Acqusition Systems
Available in 8-Pin Plastic Mini-DIP, SOIC and
Hermetic Cerdip Packages
Dual Version - AD822. Quad Version - AD824
Available
NULL
-IN
+Vs
+IN
VOUT
8-Pin Plastic Mini-DIP
SO and Cerdip
n excellent choice for battery powered precision
p lications - wherein the extended input and
d the AD821 its versatility in these
21 is available in five performance grades. The AD82lJ
1K are rated over the commercial temperature range
°C. The AD821A and AD821B are rated over the
perature range of -40°C to + 85°C. The AD82lS
36Y ~r!
over the military temperature range. of - 55°C to + 125°C
is available processed to MIL-STD-883B, Rev. C.
PRODUCT DESCRIPTION
The AD821 is a precision, 10
amp that can operate from a si
or dual supplies of ±2.4V to ± 1
capability with its input voltage range inclu
negat
rail, allowing the AD821 to accommodate input signals do
ground in the single supply mode. Its output voltage swing
extends to within 50mY of each rail providing the maximum
possible output dynamic range to the user.
Low input offset voltage (250fJ.Y max), low offset voltage drift
(3fJ.Y/"C max), low input bias current «10pA) and low supply
currents (400fJ.A max) mark the AD821 with true dc precision
at low power operating conditions. Combined with unity gain
bandwidth of 1.3MHz and 3Y/fJ.s slew rate, the AD821 offers
the best combination of ac and dc specs to the single supply op
amp user. Performance in 12- to 14-bit applications is ensured
with the AD821's low noise 26nY/VHz), high open-loop gain
(107Y/mY) and 4fJ.s settling to 0.01%.
r
Extended reliability PLUS screening is available, specified over
the commercial and industrial temperature range. PLUS screening
includes a 168 hour burn-in, as well as other environmental and
physical tests.
PRODUCT HIGHLIGHTS
1. True single supply operation - input voltage range includes
the negative rail.
2. Output voltage range extends to SOmY of each rail.
3. Low power, low supply current.
4. Common-mode rejection of 90dB and open-loop gain of
107Y/mYensure 12- to 14-bit accuracy in high-speed data
acquisition circuits.
5. Dual version - AD822, quad version - AD824 also available.
OPERATIONAL AMPLIFIERS 2-153
SPECIFICATIONS
(@
+ 25"1: unless otherwise noted)
Model
Conditions I
INPUT CHARACTERISTICS
Input Offset Voltage'
Min
AD821J/A/S
Typ
0.3
0.3
Input Offset Voltage Drift
Input BlasCurrent 3
IS
TmmlOTmdx
Input Offset Current
TmmtoTm.tx
Differential Voltge
Range 4
Common-Mode ReJection
Min
AD821B/K
Typ
Max
Units
0.25*
0.25*
0.4*
3'
20
o 5/1.3
7
0.16/0.45
mV
mV
mV
VCM~O
Condition 1, Vo=OV
Condition 2, Vo ~ I.4V
TmantoTmdX
Input ResIstance
Input Capacitance
Common-Mode Vollage Range
Max
1*
1*
1.5/1.6/2*
10'
30
0.6S/2/30
IS
0.34/0.96!lS
0.1
0.1
10
5 x 10
3
5 x 10
3
Differential
-Vs
-Vs
-Vs-0.6
-Vs-0.6
SO*
CondItIOn I
Condition 1
Condition I
Condmon2
ConditIon I
+Vs-I
+V,-I
+V,+0.6
+ V,+0.6
-Vs
-Vs
- V, - 06
-Vs-06
90'
~V!,C
pA
nA
pA
nA
1I
pF
+Vs-I
V
V
+Vs-I
+ Vs+0.6 V
+Vs+0.6 V
dB
VCM~"'12V,V()~OV
Condmon 2
VCM~Oto2.SV, V()~
Power Supply ReJection Ratio
Input NOIse Voltage
Input NOIse Current
OUTPUT CHARACTERISTICS
Output Voltage SWIng
SO'
90*
dB
SO'
SO*
90'
90*
dB
dB
I 4V
Coodmon 1
Condition 2
45< + Vs842 CONNECTION DIAGRAMS
Plastic DIP (N) Package
NC
NC
and
Cerdip (Q) Package)
NC
BALANCE
OUTPUT
NC
= NO CONNECT
NC
TO-S (H) Package
OUTPUT
NC
BQTTQMVIEW
NOTE CAN TIED TO V +
NC
";,,,:(
= NO CONNECT
slew rate and fast settling time of the AD842 make
eal for DAC and ADC buffer amplifiers, line drivers and
all types of video instrumentation circuitry.
~'it
The AD842 is a precision amplifier. It offers accuracy to
0.01% or better and wide bandwidth; performance previously
available only in hybrids.
3. Laser-wafer trimming reduces the input offset voltage to
1mV max, thus eliminating the need for external offset nulling
in many applications.
4. Full differential inputs provide outstanding performance in
all standard high frequency op amp applications where the
circuit gain will be 2 or greater.
5. The AD842 is an enhanced replacement for the HA2542.
OPERATIONAL AMPLIFIERS 2-161
SPEC IFI CAli 0NS (@ +250C and ± 15V de, unless oIhlllWise nollld)
Model
Conditi0D8
Min
INPUT OFFSET VOLTAGE'
AD842J
Typ
Mas
Units
0.5
1.5
3.5
20
mV
mV
,..Vf'C
3.5
S
10
0.4
0.5
3.5
5
6
0.2
0.3
3.5
S
12
0.4
0.6
,..A
,..A
,..A
,..A
Input Offset Current
0.1
Tnun-Tmax
INPUT VOLTAGE NOISE
Wideband Noise
f=lkHz
10Hz to IOMHz
OPEN LOOP GAIN
Vo= ±IOV
RLOAD ;;o500{1
Tnun-TIIWI:
TDUriTmax
OUTPUT CHARACTERISTICS
Voltage
Current
Output Resistance
FREQUENCY RESPONSE
Gain Bandwidth Product
FuU Power Bandwidth'
Rise Time
Overshoot
Slew Rate
Settling Time
Differential Gain
Differential Phase
RLOAD;;olkO
VOUT= ±IOV
Open Loop
±IO
86
SO
0.1
100
1.0
±IO
90
86
100
±IO
86
80
100
9
28
90
40
40
20
20
±IO
100
±IO
100
VOUT= 90mV
AVCL= 2
Vo=20Vp;
4.7
RI=,
AVCL
AVCL=
AVCL=2
10VStep
toO.I%
to 0.01%
f=3.58MHz
f=3.58MHz
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
Power Supply Rejection Ratio
0.1
100
1.0
Differential Mode
VCM= ±IOV
300
80
100
0.1
0.1
±15
±15
±5
TmJllTmax
Vs =±5Vto±15V
T .... -T....
TEMPERATURE RANGE
Rated Performance
PACKAGE OPTIONS'
Plastic (N·14)
Cerdip(Q-14)
TO-8(H-12A)
±IS
14
16
+75
0
ADS42JN
ADS42JQ
AD842JH
SpecIfications marked ID boldface are tested on all production UDlts at final elec~
tneal test.
±5
90
86
100
86
80
NOTES
'Input offset voltage specifications are guaranteed after 5 minutes at T A = + 2S'C.
'FPBW = Slew Ratel2" VPEAK'
'See Seetion 16 for package outline information.
Specifications subject to change without notice.
2-162 OPERATIONALAMPLIFIERS
AD842S
Typ
I
1.5
10
Tnun-Tmu:
Mas
Min
0.5
INPUT BIAS CURRENT
INPUT VOLTAGE RANGE
Common Mode
Common·Mode Rejection
AD842K
Typ
1.5
2.5
20
Tmin - Tmu:
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Min
0.5
Offset Drift
Mas
100
V
dB
dB
9
28
nVI Hz
,..Vrms
90
V/mV
V/mV
-V
mA
{1
80
MHz
6
10
20
375
MHz
ns
%
V/,..s
80
100
0.1
0.1
ns
ns
%
Degree
±S
S6
80
100
+75
AD842KN
AD842KQ
AD842KH
kO
pF
±15
±IS
14
16
0
100
1.0
±IS
14
19
100
V
V
mA
rnA
dB
dB
-55
+ 125
AD842SQ
AD842SH
'C
Precision 16MHz
CBFET Op Amp
r.ANALOG
WDEVICES
AD845 I
FEATURES
Replaces Hybrid Amplifiers in Many Applications
AC PERFORMANCE:
Settles to 0.01% in 350ns
100Vl..s Slew Rate
12.8MHz min Unity-Gain Bandwidth
1.75MHz Full-Power Bandwidth at 20V POp
DC PERFORMANCE:
0.25mV max Input Offset Voltage
5..VI"C max Offset Voltage Drift
0.4nA Input Bias Current
250V/mV min Open-Loop Gain
4..V pop max Voltage Noise. 0.1Hz to 10Hz
94dB min CMRR
Available in Plastic Mini-DIP and Hermetic Cerdip
Packages
PRODUCT DESCRIPTION
The AD845 is a fast, precise, N channel JFET input,
operational amplifier. It is fabricated using Analo
complementary bipolar (CB) process. Advanc
trimming technology enables the very 10
and offset voltage drift performance t
when coupled with a slew rate
bandwidth of 16MHz, an
while driving a parallel 1
combination of features un
The AD845 can easily be used to u
which use BiFET or FET input hybrid a
cases, those which use bipolar op amps.
The AD845 is ideal for use in applications such as active filters,
high-speed integrators, photo diode preamps, sample and hold
amplifiers, log amplifiers, and in buffering AID and D/A
converters. The 250j.lV max input offset voltage makes offset
nulling unnecessary in many applications. The common-mode
rejection ratio of llOdB over a ± lOY input voltage range represents
exceptional performance for a JFET input high-speed op amp.
This, together with an open-loop gain of 250V1mV ensures
that 12-bit performance is achieved, even in unity gain buffer
circuits.
AD845 CONNECTION DIAGRAM
8-Pin Plastic (N) and
and Cerdip (Q) Packages
NULL
NULL
-INPUT
+v
+ INPUT
OUTPUT
-v
~NOTE:
NC
PIN 4 CONNECTED TO CASE
"';;14;,
conforms to the standard 741 pinout except that
.
0 V +. The AD845J and AD845K grade devices
'fied to operate over the commercial 0 to + 70°C
re range. AD845A and AD845B devices are specified
ration over the - 40°C to + 85°C industrial temperature
ge. The AD845S is specified to operate over the full military
re range of - 55°C to + 125°C. Both the industrial
ry versions are available in 8-pin cerdip packages. The
ercial version is available in an 8-pin plastic mini-DIP.
The high slew rate, fast settling time, and dc precision of the
AD845 make it ideal for high-speed applications requiring
12-bit accuracy.
'
2. The performance of circuits using the LF400, OP-42, OP-16,
OP-17, LTl022, LTl056, HA251O, AD381, and AD382 can
be upgraded in most cases.
3. The AD845 is unity-gain stable and is internally
compensated.
4. The AD845 is specified while driving IOOpF/500n loads.
OPERATIONALAMPLIFIERS 2-163
SPEC IFI CATIONS
(@ +25"1: and ± 15V dc, unless othenvise noted)
Model
Conditions
Min
INPUT OFFSET VOLTAGE'
Initial Offset
AD845J/A
Typ
0.7
VCM = :!cIOV
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
INPUT VOLTAGE RANGE
Differential
ComrnonMode
Common-Mode Rejection
INPUT VOLTAGE NOISE
INPUT CURRENT NOISE
VCM= ",IOV
Max Units
mV
mV
fLVI'C
250
400
12/26
500
1000 pA
BOO nA
15
50
1.2/2.6
25
100
25
100
3/6.5
BO
pA
nA
10"
4.0
k!l
pF
±20
+ 10.51-13
110
86
V
V
dB
10"
4.0
±20
+10.5/-13
86
110
0.1 to 10Hz
f= 10Hz
f= 100Hz
f= 1kHz
f= 10kHz
f= 100kHz
AD845S
Typ
1.0
2.0
10
1.5
10"
4.0
Min
0.25
1000
30/65
Tmm-Tmax
Max
0.25
0.4
5.0
500
Tmm-Tmax
INPUT OFFSET CURRENT
Initial
AD845KIB
Typ
0.1
Offset Drift
VCM = :!cIOV
Min
1.5
2.5
20
Tmm- Tmax
INPUT BIAS CURRENT2
Initial
Max
4
SO
60
f= 1kHz
fLV~
4
SO
60
25
IS
12
nVI Hz
nV/vth
nV/vth
nV/vth
nV/vth
0.1
pA/vth
500
250
V/mV
V/mV
V/mV
OPEN·LOOPGAIN
200
100
70
OUTPUT CHARACTERISTICS
Voltage
Current
Output Resistance
FREQUENCY RESPONSE
Small Signal
Full Power Bandwidth'
Rise Time ,
Overshoot
Slew Rate
SettlmgTime
POWER SUPPLY
Rated Performance
Operating Range
Rejection Ratio
Quiescent Current
SO
V
rnA
!l
16
MHz
I. 75
100
MHz
ns
%
V!f.lS
350
250
ns
ns
ns
ns
± 12.5
SO
Unity Gain
Vo=:!c IOV
RI =500n
12.S
16
13.6
1.75
I.7s
SO
10V Step
CWAD = 200pF
RWAD = sOOflF
(00.01%
toO.I%
100
94
350
250
Vs= ",sto '" IsV
Tmm-Tmax
TEMPERATURE RANGE
Operating, Rated Performance
0/-40
±4.75
98
15
75/SS
113
10
01-40
SpecificatIOns subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. All min and max specifications
are guaranteed, although only those shown in boldface are tested on all production units.
500
'" IS
±18
PACKAGE OPTIONS'
Cerdlp (Q·S)
ADS4sAQ
ADS4sBQ
ADS4sJN
ADS4sKN
Plastic Mini·DIP (N·S)
NOTES
IInput offset voltage specdic:attonsare guaranteed after 5 minutes of operation at T A = + 25°C.
2Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at T A=--+ 25°C.
'FPBW = slew rate/2" V peak.
4See Section 16 for package outhne information
2-164 OPERA TIONAL AMPLIFIERS
500
'" IS
±18
110
\0
94
100
350
250
'" IS
±4.75
88
13.6
16
±4.75
88
15
7s/Ss
±18
110
10
15
V
V
dB
rnA
+ 125 'C
- 55
ADS4sSQ
11IIIIIIII ANALOG
L..III DEVICES
FEATURES
AC PERFORMANCE
Small Signal Bandwidth: 46MHz (Av = -1)
Slew Rate: 450VlJ.ls
Full Power Bandwidth: 6.8MHz at 20V p-p, RL =500n
Fast Settling: for 10V Step: 110ns to 0.01%,
80ns to 0.1%
Differential Gain: <0.1% @ 3.58MHz
Differential Phase: <0.1° @ 3.58MHz
Total Harmonic Distortion (THO): 0.0002% @ 100kHz
Open-Loop Transimpedance: 500Mn
DC PERFORMANCE
Input Offset Voltage: 75J.lV max (K Grade)
Input Offset Drift: 2J.lVrC max (K Grade)
Input Voltage Noise: 2nVlv'Hi
Output Current: 50mA min
Quiescent Supply Current: 6mA max
APPLICATIONS
High-Speed DAC Buffers
Multiflash ADC Error Amplifiers
Flash ADC Buffers
Coaxial Cable Drivers
High Performance Audio Circuitry
Available in Plastic Mini-DIP, Her
Hermetic Metal Can Packa
MIL-STD-883B Parts Ava
Very High-Speed
Operational Amplifier
AD846 I
AD846 PIN CONFIGURATIONS
TO-99 (H) Package
NC
-vs
NOTE CAN TIED TO V +
NC = NO CONNECT
TOP VIEW
Plastic DIP (N) Package
and
Cerdip (Q) Package)
NC = NO CONNECT
PRODUCT DESCRIPTION
The AD846 is a monolithic, very high-speed operational amplifier
offering high ~rformance. Although technically classed as a
transimpedance amplifier, it may be used in much the same way
as traditional op amps while providing significant performance
benefits. Employing Analog Devices' junction isolated complementary bipolar (CB) process, the AD846 achieves true "12-bit"
(0.01%) precision on critical ac and dc parameters, a level of
performance unmatched by amplifiers fabricated using either
the dielectrically isolated (DI) or other bipolar processes.
The AD846 offers significant advantages over conventional
high-speed operational amplifiers. It maintains a nearly constant
bandwidth and settling time to 0.01% over a wide range of
closed-loop gains. This makes the AD846 ideal for amplifying
the residue in multiple-pass analog to digital converters.
Other advantages include: low input errors and high open-loop
transresistance (500MO) into a 5000 load, ensuring true 12-bit
dc accuracy for closed-loop gains from - 1 to gains greater than
-100. This combination of ac and de performance makes the
AD846 an excellent choice for buffering precision high-speed
DACs and flash ADCs.
The AD846 is available in three performance grades. The AD846J
and AD846K are rated over the commercial temperature range
of 0 to + 70°C. The AD846S is rated over the full military
temperature range of - 55°C to + 125°C and is available processed
to MIL-STD-883B, Rev C.
Extended reliability PLUS screening is available specified over
the commercial temperature range. PLUS screening includes
168 hour burn-in as well as other environmental and physical
tests. The AD846 is available in three types of 8-pin package:
plastic mini-DIP, hermetic cerdip or TO-99 hermetic metal
cans.
PRODUCT HIGHLIGHTS
I. The AD846 achieves settling times of lIOns to 0.01% for
gains of -I to -10, with a 4S0V//-Ls slew rate, while consuming
only SmA of supply current.
2. For closed-loop gains of - I to - 100, the high-speed performance of the AD846 is achieved without sacrificing full
12-bit dc precision.
3. The AD846 is well suited to line driver and video buffer
applications where the properties of low distortion and high
slew rate are required.
OPERATlONALAMPLIFIERS 2-165
SPEC IFICAli 0NS
(@
+ 25"1: and ± 15V de. unless otIJarwise noted)
Model
Conditions
Min
INPUT OFFSET VOLTAGE'
Initial
25
100
2
Tnun-Tmu.
vs. Temperature
.s.Supply
Init'"
Tm,n-Tmax
vs. Common Mode
BV-IBV'
no
110
VCM = ± 10V
Init'"
no
Tm,n-Tmax
110
INPUT BIAS CURRENT'
- Input Bias Current
Init'"
Max
Min
300
AD846K
T
25
75
I
400
10
125
120
n6
125
120
116
75
375
6.5
Tmm-Tmax
vs. Temperature
.s. Supply
Init'"
AD846J
T
120
120
450
Min
150
250
5
no
104
125
120
104
15
10
10
4
4
AD846S
T
25
200
2
125
120
75
325
5.5
900
Max
no
250
600
10
Max
Units
300
800
10
p.V
p.V
p'vre
125
116
dB
dB
125
116
dB
dB
75
2100
20
450
2700
30
nA
nA
nArC
10
20
nAN
10
20
nAN
10
14
40
20
30
ISO
p.A
p.A
nArC
10
10
25
25
nAN
BV-IBV'
Tnun-Tmu
nAN
vs. Common Mode
ImtIal
Tnun-TmaK
+ Input Bias Current
Imnal
Tm,n-Tmax
vs. Temperature
.s. Supply
Imual
Tmln-Tmax
vs. Common Mode
Inu'"
15
20
Tmm-Tmax
INPUT CHARACTERISTICS
Input Resistance
-Input
+ Input
Input Capacitance
-Input
+ Input
67
10
OPEN LOOP
Transresistance
±1O
Output ResIstance
FREQUENCY RESPONSE
SnuIll Sip Bandwidth
(-3dB)
:t
10
±1O
nAN
nAN
!l
k!l
V
F= 1kHz
10Hz to 10MHz
nVIv'Hz
....Vrms
1kHz
IOHz-IOMHz
1kHz
IOHz-IOMHz
VOt;T= ± IOV
RLOAD =500!l
TnullTmax
OUTPUT CHARACTERISTICS
Voltage
Current
nAN
pF
pF
INPUT VOLTAGE RANGE
Common Mode
INPUT VOLTAGE NOISE
Wldeband NOIse
Input Current NOise
-Input
-Input
+ Input
+ Input
nAN
Rt.OAD= 500!l
20
6
6
20
150
100
500
±IO
50
20
6
6
20
250
100
500
±IO
50
150
70
20
6
6
20
pAlv'Hz
nArms
pAIYHz
nArms
500
M!l
M!l
±10
50
Open Loop
16
16
16
V
mA
!l
Av= -I'R F = Ik
Av= -IORF =875!l
Av= -30RF =B75!l
46
31
IS
46
31
IS
46
31
IS
MHz
MHz
MHz
5.S
6.8
MHz
350
10
20
450
ns
%
Vlp.s
FULL POWER BANDWIDTH'
VOUT = 20V pop
R,=500!l
RISE TIME
Overshoot
Slew Rate
Av= -I
Av= -I
Av= -I
5.5
6.B
350
10
20
450
5.5
6.8
350
10
20
450
SetthngTime
IOVStep,A v = -I
THD'
toO.1%
(00.01%
80
110
80
110
80
110
ns
ns
F~
0.0002
0.0002
0.0002
%
100kHz
2-166 OPERATIONALAMPLIFIERS
Model
AD846J
Min
Conditions
DIFFERENTIAL GAIN
DifferentIal Phase
POWER SUPPLY
Rated Performance
Operatmg Range
QUIescent Current
F~
Typ
3.58MHz
ADS46K
Max
Min
01
01
F~3.58MHz
5
TEMPERATURE RANGE
Rated Performance
0
PACKAGE OPTIONS·
Plastic (N -S)
Metal Can (H-OSA)
Cerdip (Q-S)
Min
Max
Typ
0.1
0.1
'" 15
±6
Tmm-Tm"
ADS46S
±5
70
0
5
AD846JN
AD846JH
AD846JQ
Max
±IS
6
±5
70
- 55
5
ADS46KN
AD846KH
AD846KQ
Units
%
Degree
±IS
V
V
7
rnA
+ 125
'C
'" 15
'" 15
±IS
6
Typ
0.1
0.1
AD846SH
AD846SQ
NOTES
IInput Offset Voltage SpecIfications are guaranteed after 5 minutes atT A = + 25°C.
lTestConditlons: +Vs = lSV, -Vs = 8Vto18Vand +Vs = 8Vto18V, -Vs = -lSV.
3Bias Current Specifications are guaranteed maximum at either Input after 5 minutes at T A = + 25°C.
4FPBW = Slew Ratel21T VPEAK.
STotal Harmonic Distortion.
65ee Section 16 for package outline informatton.
Specifications marked 10 boldface are tested on all production umts at final electrical test.
Specifications subject to change without notice.
Supply Voltage
Internal Power Dissipati
TO-99
Plastic Pac~iSe\r~t .
Cerdip ,",
'~~t~.~~'
Input
o,f'~·
vel
0
Dl~rentiiH 111,1'1
con'nnuous:,r~,u
Inverting Ol;-~0
ting
Storage Temperature Range
Storage Temperature Range N
Operating Temperature Range
AD846J/K . . . . . . . .
AD846S . . . . . . . . . .
Lead Temperature Range (Soldering 60sec)
18V
l.OW
l.6W
l.5W
:!: 18V
Indefinite
. :!:6V
2.0mA
- 65°C to + 150°C
- 65°C to + 125°C
o to +70°c
- 55°C to + 125°C
+ 300°C
NOTES
I Stresses above those listed under" Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only; the functional
operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
'TO-99Package: alA ~ ISO°ClWatt.
Plastic Package: alA ~ 90°ClWatt.
CerdipPackage: alA ~ 100"ClWatt.
3Por supply voltages less than ± 18V, the absolute maximum mput voltage is
equal to the supply voltage.
OPERATIONAL AMPLIFIERS 2-167
Typical Characteristics
2.
20r------,------~-------r------,
V
V
~
/
f...--
--
,·~----~------_+~~---r------1
+ 25°C
/
I.
oL-____
15
20
~
•
SUPPLY VOLTAGE _ ±Volts
Figure 1. Input Voltage Swing
vs. Supply
____
~
______
~
I•
____
~
o
2.
15
•
I•
SUPPLY VOLTAGE - ±Volts
2.
15
SUPPLY VOLTAGE - ±Volts
Figure 2. Output Voltage Swing
vs. Supply
Figure 3. Quiescent Current
vs. Supply Voltage
«
E 6
""
z
l!!
:>
ill
~
0
5
u
>
...>
~
~
iii
~
4
0
-60 -40 -20
0
I.
+20 +40 +60 +80 +100 +120 +140
100
·c
TEMPERATURE -
lk
10k
/
/
'"
\
~ 102
I ••
~
i
~
100
98
i 1//
/
15
SUPPLY VOLTAGE - ±Volts
Figure 7. Open-Loop Transimpedance vs. Supply
2-168 OPERATIONAL AMPLIFIERS
20
.'0
±15V
+25°C
8.
7.
.4
-I.
-5
10M
100M
1\
Vs~
.6
I.
1M
Figure 6. Large Signal Frequency
Response
110
a~
2••
•
tOOk
104
«
8 ••
4••
I.
INPUT FREQUENCY - Hz
Figure 5. Output Voltage Swing vs.
Resistive Load
1000
/
15
LOAD RESISTANCE _ H
Figure 4. Quiescent Supply Current
vs. Temperature
6 ••
2.
I.
COMMON·MODE VOLTAGE - Volts
Figure 8. Positive Input Bias Current
vs. Common-Mode Voltage
\
\
\~
/'
/
V
/
Vs= ±15V
+25"C
6•
-I.
-5
10
COMMON-MODE VOLTAGE _ Volts
Figure 9. Negative Input Bias Current
vs. Common-Mode Voltage
-7
,
",
i
f'.,
~
ffi
~
""
-10
z
~ -11
,
i
~
-12
" -13
"
~
>
,
'\
~
""'"
\
CJ
15
10
-
05
~
5
~ -05
-15
0
J
~
,
'\
-60 -40 -20
~
20
U>
-14
~
+120
;;;
11;;;
I-
+140
25
~
-9
>
!
30
~
-8
/
.,
"-
+80
~
."
+.0
'"~
U>
~
+40
"'-
+20
0
10
+20 +40 +60 +80 +100+120+140
100
lk
TEMPERATURE _ "C
Figure 10. Positive Input Bias
Current vs. Temperature
V s "" ±15V SUPPLIES
"'-
-20
-10
-60 -40 -20
+20 +40 +60 +80 +100+120+140
TEMPERATURE _ "C
,/
V
.........
+100
10k
lOOk
Figure 11. Negative Input Bias
Current vs. Temperature
.0
j~
.,
+80
i,
'"
+.0
1111 I
~ 20
30
1\
\
~
."
ilw
""
~
+40
~ ....
~
~
+20
-20 L-__
~
__
~
__
~
__
~
__
~
__
~
__
10
i'10
100
lk
Figure 14. Input Noise Voltage
Spectral Density
I
~
480
420
"- i"...
500
r<
"
:>,
~
"-
"
~
U>
"
Z
i'-.
70
so
r--. r-.....
450
RISING
SLEW RATE
3.0
........
i!!
r-....
80
Ii:
U>
lOOk
~
f'.-t-
400
.......
........
r--...
o
+20 +40 +60 +80+100+120+140
TEMPERATURE -"C
Figure 16. Short Circuit Current
Limit vs. Temperature
"
300
i!!
240
~,
........
10M
"0
120
300
.0
-60 -40 -20
o
+20 +40 +60 +80 +100 +120 +140
TEMPERATURE _ "C
Figure 17. Slew Rate vs.
Temperature
~
,.- -::::Ir--
'"
FALLING
SLEW RATE
~
~
350
/
/ '/
/ /
//
IV
~
250
-60 -40 -20
1M
Figure 15. Input Noise Current
Spectral Density
550
100
"
10k
FREaUENCY _ Hz
Figure 13. Common-Mode Rejection
vs. Frequency
r--..
r-..
~
FREQUENCY - Hz
i§
100M
AL '" lkU
+100
1, 90
10M
Figure 12. Power Supply Rejection
vs. Frequency
+140
"
1M
•
FREQUENCY - Hz
+120
'"
:;;
"
i/'
-
~
100
200
300
400
INPUT ERROR SIGNAL _ mV
500
(AT SUMMING JUNCTION)
Figure 18. Slew Rate vs. Input Error
Signal
OPERATlONALAMPLlFIERS 2-169
Typical Characteristics, Inverting Gain of 1
+3
11150~olD
jOl~I~
lkll
!g
,
~
:>
~«
lkll
....
~
5
-3
-6
±15
III
VOLT
SUPPLl~sl
-9
fa
"
~ -12
~
z
'PLUS 2pF SCOPE
PROBE CAPACITANCE
-15
-1.
lOOk
1M
10M
100M
INPUT FREQUENCY - Hz
Figure 19a. Inverting Amplifier,
Gain of 1
+270
Figure 19b. Large Signal Pulse
Response, Gain of 1
r--r-..,-"..--,.-..,-T"1-r--"--'-T"1'
+ 180 ~-t-+-t-t+--+""':±:::-H+--t-t-H-l
I----t----,
- 105
+.0 ~-+--+-t-t+--t--+-+4t-~.--'
~
c
I;:
± 15 VOLT SUPPLIES
~
~
-90
«
~
-180
1--t--t-Ht------t--t-t-ff------t--ff--1'IlIH
-270
I--t--t-Ht--t--+-t-H----t--H---t-H
40
2
:!
'"
;ll
36
/
II
/
~
~
~
=
__-L_J
~
~
ns
51
1/
/
~
Figure 23. Settling Time
vs. Step Size
100
/
~
SETTLING TIME -
Figure 22. Harmonic Distortion
vs. Frequency
48
44
L-_L-~_-l~~~-L-l-L
o
FREQUENCY - Hz
Figure 21. Phase vs. Frequency
vs. Load
~
c
-10
lOOk
10k
1k
INPUT FREQUENCY - Hz
Rl =500U
± 15V SUPPLIES
!,
± 15 VOLT SUPPLIES
i!'
e
Rl = 500!~
+2S"C
7 -
4.
/
10
I
V
!8
47
45
43
j......
V
./
........
~.
7
~
01
1
41
001
32
10
15
SUPPLY VOLT AGE ± Volts
Figure 24. 3dB Bandwidth vs.
Supply Voltage
2-170 OPERA TIONAL AMPLIFIERS
20
10k
3.
lOOk
1M
10M
FREQUENCY - Hz
Figure 25. Output Impedance
vs. Frequency
100M
-60 -40 -20
0
+20 +40 +60 +80 +100 +120'+140
TEMPERATURE - QC
Figure 26. 3dB Bandwidth vs.
Temperature
Typical Characteristics, Inverting Gain of 10
l
.3
90911
000fllOAD
sou
90911
LOAD
-6
V 1N
,~\
'\.
- 3
Rs
-'1~
'" 15 VOLT SUPPLIES
-9
-12
I\~
-15
'PLUS 2pF SCOPE
PROBE CAPACITANCE
-18
lOOk
1M
10M
•
100M
INPUT FREQUENCY - Hz
Figure 27a. Inverting Amplifier,
Gain of 10.
Figure 27b. Large Signal Pulse
Response, Gain of 10
Figure 28. Closed-Loop Gain
vs. Frequency vs. Load
10
+ 180
J / It'o/
a"
~\o ~~\O
ri"-1-"''''''~;;;;:ItiTI-ttii
/ / /
~
GAIN OF -10
ERROR
-2
-180
f--+-+-+-++----f-++I+--+
\
-4
f--+-+-+-+t-----f-++I-t---"I
\1\
\'\:
°
I\'~
-6
- 270
Rs =87 Sf! RF =87511
-8
0.....
0"
\~
'\..h.
-10
- 360 L.-L_.L.L.lL---'_...L.l...J...L-.J'-...l..-..llOOk
1M
""J!.
.\
20
40
60
80
100
120
140
160
SETTLING TIME - ns
Figure 29. Phase vs. Frequency
vs. Load
33
100
/
V
31
~
:;
,
i
29
Q
..'"
Z
;li
27
Figure 31. Settling Time vs.
Step Size
Figure 30. Harmonic Distortion
vs. Frequency
)
...,
34
32
1/
10
IR,"~OOl!
>!
:; 30
,
~
§
28
Q
Z
Rl=500n
.
::I
+ 25°C
7
Il:.
01
I
I
± lSI,,' SUPPLIES
/
26
V
V
V
,
"" ~
./
24
".
25
001
10
15
SUPPLY VOLTAGE - :tVolts
Figure 32. 32dB Bandwidth vs.
Supply Voltage
20
".
10k
22
lOOk
1M
10M
FREQUENCY - Hz
Figure 33. Output Impedance
vs. Frequency
100M
-60 -40 -20
0
+20 +40 +60 +80 +100 +120+140
TEMPERATURE - "C
Figure 34. 3dB Bandwidth vs.
Temperature
OPERA TIONAL AMPLIFIERS 2-171
Applying the AD846
POWER SUPPLY BYPASSING
The power supply connections to the AD846 must maintain a
low impedance to ground over a bandwidth of 40MHz or more.
This is especially important when driving a significant resistive
or capacitive load, since all current delivered to the load comes
from the power supplies. Multiple high quality bypass capacitors
are recommended for each power supply line in any critical
application. A O.lfLF ceramic and a 2.2fLF electrolytic capacitor
as shown in Figure 35 placed as close as possible to the amplifier
(with short lead lengths to power supply common) will assure
adequate high frequency bypassing, in most applications. A
minimum bypass capacitance of 0.1 fLF should be used for any
application.
Figure 35.
~f1}~'~~;,
THEORY OF OPERATIONI'{~f,;;J'
The AD846 differs from convenlional 4ilti
that it is a transimpedance device rather t~ a convenu
voltage amplifier. Figure 36 is a simplified schematic of t
AD846. The input stage consists of a pair of transistors, QI and
Q2, which are biased by two diode-connected transistors, Q3
and Q4. Transistors QI and Q2 have their emitters connected
together and this common point functions as the inverting input
of the amplifier. Correspondingly, the common connection of
the two biasing diodes acts as the noninverting input.
When operated as a closed-loop amplifier, feedback error current,
lIN, flows into the inverting input terminal and is conveyed via
current mirrors (transistors Q5, Q6, Q7, and Q8) to the compensation capacitor, CCOMP. The voltage developed across CCOMP
is buffered by the output stage, consisting of transistors
Q9-QI2.
Because the input error signal developed is in the form of a
current, not a voltage, the AD846 differs from conventional
operational amplifiers. This also means that, unlike most operational amplifiers which rely on negative feedback to produce a
"virtual ground" at the inverting input terminal, this terminal
explicitly has a low impedance.
A unique circuit approach allows the AD846 to realize an open-loop
transimpedance of close to 1Go.. This is nearly three orders of
magnitude greater than that of any other operational transimpedance amplifier and results in extremely high levels of dc
precision.
2-172 OPERA T10NAL AMPLIFIERS
Figure 37. Overload Recovery Test Circuit
.
10
:
---
.... ..
u.
I
~
10V/Div
~
~~
1V/Div
-:
"
t
'0
I
n·
m~ nS
. ...
.I.•
~
-
INPUT
OUTPUT
1m
~
HI
I
U
.. • 1
I
...
f
I
~
~
!~
i
~~
Figure 38. Over/oad Recovery Time Photo
As an example, the output voltage gain error is approximately
equal to the value of the feedback resistor divided by the value
of the open-loop transimpedance of the amplifier. That is, when
using a lko. feedback resistor, this error is one part in 500,000.
For a transimpedance amplifier with lMo. transimpedance, this
error is only one part in 1000; such an amplifier would barely
be able to achieve 10-bit precision.
Applying the AD846
is small compared to R F, the closed-loop bandwidth is controlled
by the internal compensation capacitance of 3.3pF and the value
of RF, and not by the closed-loop gain. At higher gains, where
(1 + RF/Rs) RIN is much larger than R F, the behavior is that of
a conventional operational amplifier in which the input stage
transconductance is equal to the inverting terminal input impedance of the transimpedance amplifier (R1N = 670).
A simple equation can, therefore, be used to determine the
bandwidth of an amplifier employing the AD846 in the inverting
configuration.
Figure 39. AD846 Three-Terminal Model
Figure 39 is a simplified three-terminal model for the AD846.
Figure 40 is a simplified three-terminal model for a conventional
voltage op amp. The action of current feedback serves to modify
the behavior of the amplifier under closed-loop conditions. The
feedback resistor, R F, is somewhat analogous to the input stage
transconductance of a conventional voltage amplifier; and therefore, if the value of RF is held constant, the closed-loop band
also remains virtually constant, independent of c1osed-loo
gain.
3dB Bandwidth =
RF+0.06~8(1
Where: The 3dB bandwidth is in MHz
G is the closed-loop inverting gain of the AD846
RF is t feedback resistance in kO.
Figure 4
tes the closed-loop bandwidth vs. closed-loop
for various values of feedback resistor. For
poses, the characteristic of a conventional amplifier
z unity gain bandwidth is also shown.
1M
100k
Figure 40. Op Amp Three- Terminal Model
A more detailed examination of the closed-loop transfer function
of the AD846 results in the following equation:
-RF
~
Closed-Loop Gain G(s) = - - - - - - . . . , - - - = : - , . . - - (1 + CCOMP[RF+(1 +
~:)RIN1S)
Compare this to the equation for a convention op amp:
(1 +
CCOMP (
RF)
---g;1 + Rs
100M
10M
FREQUENCY _ Hz
Figure 41. Closed-Loop Gain vs. Bandwidth for Various
Values ofRF
For the case where RF = IkO and Rs = 1000 (closed-loop
gain of - 10) then the closed-loop bandwidth becomes 28MHz.
It should also be noted that the use of a capacitor to shunt R F, a
normal practice for stabilizing conventional op amps, will cause
this amplifier to become unstable because the c1osed:loop
bandwidth will increase beyond the stable operating frequency.
A similar approach can be taken to calculate the noise performance
of the amplifier. A simplified noise model is shown in
Figure 42.
-RF
R;-
Closed-Loop Gain G(s)
+ G)
s)
Where: CCOMP is the internal compensation capacitor of the
amplifier; gM is the input stage transconductance of the
amplifier.
In tbe case of the voltage amplifier, the closed-loop bandwidth
decreases directly with increasing values of (1 + RF/Rs), the
closed-loop gain. However, for the transimpedance amplifier,
the situation is different. At low gains, where (I + RFIRS) RIN
The equivalent output noise voltage will equal:
VON = RF INN + (1 +
~:) VV~ +
(Rp INP)2
Where: Rp is the external resistance placed in series with the
noninverting input
RF is the feedback resistor
Rs is the source resistor
INN is the noise current in the inverting input
I NP is the noise current in the noninverting input
VN is the input noise voltage.
OPERA T/ONAL AMPLIFIERS 2-173
Applying the AD846
Typical values for these parameters (@ 1kHz) in pA/\IHZ are:
INN = 20, IPN = 6, VN = 2.
Or, referring to the input, the equivalent input voltage noise is:
VIN = Rs INN + ( I + RS)V2
RF
VN+ (RpINP)2
As can be seen from the above equation, the addition
-,
330n
""'"
O~
-2
~
-3
..~
-4
,
'.
~
50n
(OR 750)
-.
'OOk
'M
'OM
'G
'OOM
FREQUENCY - HERTZ
Figure 19. Response of the (Figure 17) Inverter Circuit
Witfi an RLAG Compensation Network Employed
+2
U
-8V
!I
35pF
+1
I
Figure 17. A General Purpose Inverter Circuit
For this circuit, the total capacitance at the inverting input is
approximately 3pF; therefore, CLBAD from Equations 1 & 2
needs to be approximately 1.5pF. As shown in Figure 17, a
small trimmer is used to optimize the frequency response of this
circuit. Without a lag compensation network, the noise gain of
the circuit is 3.0 and, as shown in Figure 18, the output amplitude
remains within ±0.5d8 to 170MHz and the -3d8 bandwidth
is200MHz.
,
i!lj:!
~,,
!
I
.~
0
-,
3300
+10pF
-2
~
,
-3
-4
-.
lOOk
'M
'OM
100M
10
FREQUENCY - HERTZ
Figure 20. Response of the (Figure 17) Inverter Circuit
With an RLAG and a CLAG Compensation Network
Employed
2-190 OPERATIONALAMPLIFIERS
Figures 21 and 22 show the small and large signal pulse responses
of the general purpose inverter circuit of Figure 17, with
CLEAD = l.5pF, R LAG =330n and CLAG =3.5pF.
R2
2k
+8V
•
-8V
Figure 21. Small Signal Pulse Response of the (Figure 17)
Inverter Circuit. Vertical Scale: 50mVldiv; Horizontal Scale:
5nsldiv.
Figure 23. A Gain of 2 Inverter Circuit with the CLEAO
Capacitor Connected to Pin 12
+20
~ +10
,
;
"
CU,AO
TOOUTPUT
"
'" -10
~
::>
o
'l
-20
~
~
C LEAD
PIN 12
-30
\.
i
,
III -40
-50
lOOk
Figure 22. Large Signal Response of the (Figure 17) Inverter
Circuit. Vertical Scale: 200mV/div, Horizontal Scale: 5nsl
div.
A C LEAD capacitor may be used to limit the circuit bandwidth
and to achieve a single pole response free of overshoot
1
).
( - 3dB frequency = 2 R2C
'IT
LEAD
If this option is selected, it is recommended that a CLEAD be
connected between Pin 12 and the summing junction, as shown
in Figure 23. Pin 12 provides a separately buffered version of
the output signal. Connecting the lead capacitor here avoids the
excess output-stage phase shift and subsequent oscillation problems
(at approx. 350MHz) which would otherwise occur when using
the circuit of Figure 17 with a CLEAD of more than about 2pF.
Figure 24 shows the response of the circuit of Figure 23 for
each connection of C LEAD • Lag components may also be added
to this circuit to further tailor its response, but, in this case, the
results will be slightly less satisfactory than connecting CLEAD
directly to the output, as was done in Figure 17.
1M
10M
100M
1G
FREQUENCV - HERTZ
Figure 24. Response of the Circuit of Figure 23 with
CLEAO = 10pF
A General Purpose Voltage Follower Circuit
Noninverting (voltage follower) circuits pose an additional complication, in that when a lag network is used, the source impedance
will affect the noise gain. In addition, the slightly greater bandwidth
of the noninverting configuration makes any excess phase shift
due to the output stage more of a problem.
For example, a gain of 3 noninverting circuit with CLEAD connected
normally (across the feedback resistor - Figure 25) will require
a source resistance of 200n or greater to preveqt UHF oscillation;
the extra source resistance provides some damping as well as
increasing the noise gain. The frequency response plot of Figure
26 shows that the highest - 3dB frequency of all the applications
circuits can be achieved using this connection, unfortunately, at
the expense of a noise gain of 14.2.
OPERATIONAL AMPLIFIERS 2-191
+.
!8
H2
,
-1
I
+8V
2k
2.711
~
0
c _
•
L2
I -.
i
V"'f 150ll
-4
-5
100k
.M
.0
100M
.OM
FREQUENCY - HERTZ
Figure 28. Response of the Gain of 3 Follower with Cl.£Ao.
CLAG and RLAG
-8V
Figure 25. A Gain of 3 Follower with Both Lead and Lag
Compensation
+2
!8,
These same principles may be applied when capacitor CLBAD is
connected to Pin 12 (Figure 29). Figure 30 shows the bandwidth
of the gain of 3 amplifier for various values of RUG. It can be
seen from these response plots that a high noise gain is still
needed to achieve a reasonably flat response (the smaller the
+1
~
10-" f-
I-.
R2
2k
+8V
~~
~~
a: 0 -2
I
1-4
iO -.
•....
.M
'OM
FREQUENCY - HERTZ
.ooM
.G
Figure 26. Response of the Gain of 3 Follower Circuit
Adding a lag capacitor (Figure 27) will greatly reduce the midband
and low-frequency noise gain of the circuit while sacrificing only
a small amount of bandwidth as shown in Figure 28.
-8V
Figure 29. A Gain of 3 Follower Circuit with CI.£AD
Compensation Connected to Pin 12
+'0
••11
5100
R.....
~
+5
l.4
I~ -.
o
R...
,
~>-
-10
L.
i
.. -20
-.•
.Ok
1M
10M
100M
'G
FREQUENCY - HERTZ
Figure 27. A Gain of 3 Follower Circuit with both CLEAD
and RLAG Compensation
2-192 OPERATIONAL AMPLIFIERS
Figure 30. Response of the Gain of 3 Follower Circuit
with CLEAD Connected to Pin 12
value of RUG, the higher the noise gain). For example, with a
2200 RUG and a 500 source resistance, the noise gain will be
12.8, because the source resistance affects the noise gain.
0.1 - 2.SpF
TRIMMER
1.Sk
Figures 31 and 32 show the small and large signal responses of
the circuit of Figure 29.
+8V
+8V
OFFSET
ADJ. ~~>M,...--
R2
Gam = -lto-5
Circuit of FIg. 23
~
G
2k
,;;~
4~-1
•
R2
Gam - +2(0 +5 3
Circuit of FIg 27 ~ 2k
G-I
,;;_R_I_
1O~-1
>
=
I
•
2,,(44 x 10 )RI.AG
R2
Gam = +2to +5 4
ClrcwtofFlg.29
R2
G-I
2k
,;;_R_I_
1O~-1
R2
Gam<-S
~
G
15k
NA
NA
Trimmers
-20
±0.2dB
80MHz
Gain> +5
.JL
l.5k
NA
NA
Trimmers
+20
±0.2dB
80MHz
G-1
G=Gam NA=NotAppbcable
'Values gIven forspecdic results swnmanzed here-applications can be adapted for values different than those speclfred
2It IS recommended tbat C 1 EAD and C LACl be trimmers cavumg a range that mcludes the computed value above
3RsoURCE ~200n
"RSOURCE 5;;500.
sUseVoitrorucsCPA20 1-2.SpFTeflonTrunmerCapaclfor(oreqwvalent)
The photos of Figures 40 and 41 demonstrate how the AD5539
easily settles to 1% (ImV) in less than 12ns; settling to 0.1%
(l00,,"V) requires less than 25ns.
Figure 42 shows the oscilloscope response of the generator alone,
set up to simulate the ideal test circuit error signal (Fiiure 43).
l54nV
nHCPD _ 24.811)S
10 UFj.1 CRS1)
Figure 40. Error Signal from AD5539 Settling Time Test
Circuit - Falling Edge. Vertical Scale: 5nsldiv.; Horizontal
Scale: 5OOILVldiv.
4
Figure 42. The Oscilloscope Response Alone Directly
Driven by the Test Generator. Vertical Scale: 5nsldiv.;
Horizontal Scale: 5OOILVIdiv.
f --1-.n..
H INDUSTRIES
SPG2000 PULSE GENERATOR OUTPUT
1V
Figure 41. Error Signal from AD5539 Settling Time Test
Circuit - Rising Edge. Vertical Scale: 5nsldiv.; Horizontal
Scale: 500ILVIdiv.
Figure 43. A Simulated Ideal Test Circuit Error Signal
OPERATIONALAMPLIFIERS 2-195
Vx
~
+9V
2.711
HF COMP
10",F
Z1
1n';v
Vy,IN
~
CH1
OUTPUT
CH1
INPUT
~
AD539
+Vs
+9V
V OUT
f
BASE
COMMON
-Vs
-9V
V Y2 IN
~
CH2
INPUT
INPUT
COMMON
CH2
OUTPUT
Z2
Rx
OUTPUT
COMMON
\l
01
47011
21!l
THOMPSON-CSF BAR-10 OR SIMILAR SCHOTIKY DIODE
SHORT. DIRECT CONNECTION TO GROUND PLANE.
-9V
Figure 44. A Wide Bandwidth Voltage-Controlled Amplifier
A SOMHz VOLTAGE-CONTROLLED AMPLIFIER
Figure 44 is a circuit for a SOMHz voltage-controlled amplifier
(VCA) suitable for use in high-quality video-speed applications.
This circuit uses the ADS539 as an output amplifier for the
AD539, a high bandwidth multiplier. The outputs from the two
signal channels of the AD539 are applied to the op amp in a
subtracting configuration. This connection has two main advantages: first, it results in better rejection of the control voltage,
particularly when over-driven (Vx3.3V). Secondly, it
provides a choice of either noninverting or inverting responses,
using either input VYI or VY2 respectively. In this circuit, the
output of the op amp will equal:
V 0
Y1 - VY2)..
VOUT -- Vx (V
2V
lor x>
Hence, the gain is unity at Vx = +2V. Since Vx can over-range
to + 3.3V, the maximum gain in this configuration is about
4.3dB. (Note: If Pin 9 of the AD539 is grounded, rather than
connected to the output of the 5539N, the maximum gain becomes
IOdB.)
The bandwidth of this circuit is over 50MHz at full gain, and is
not substantially affected at lower gains. Of course, when Vx is
zero (or slightly negative, to override the residual input offset)
there is still a small amount of capacitive feed through at high
frequencies; therefore, extreme care is needed in laying out the
PC board to minimize this effect. Also, for small values of Vx ,
the combination of this feedthrough with the multiplier output
can cause a dip in the response where they are out of phase.
Figure 45 shows the ac response from the noninverting input,
with the response from the inverting input, Vy2 , essentially
identical. Test conditions: VY1 =0.5V rms for values of Vx from
+ 10mV to +3.16V; this is with a 750 load on the output. The
feedthrough at Vx = -lOmV is also sho~n.
2-196 OPERATIONALAMPLIFIERS
10
vx-
+3162V
........
"\.
v x = +lV
'" \.
"'" '\. 1\
-10
V x =+0316V
vx = +0 1V
'"
vx = +OO32V
-40
Vx =+OO1V
-50
-60
'\.
_-?'
r"'V
V,LOO1V V .....
10
FREQUENCY - MHz
100
Figure 45. AC Response of the VCA at Different Gains
Vy =O.5Vrms
The transient response of the signal channel at Vx = + 2V,
Vy=VOUT = + or -IV is shown in Figure 46; with the VCA
driving a 75n load. The rise and fall times are both approximately
7ns.
A few final circuit details: in general, the control amplifier
compensation capacitor for Pin 2, Cc , must have a minimum
value of 3000pF (3nF) to provide both circuit stability and
maximum control bandwidth. However, if the maximum control
bandwidth is not needed, then it is advisable to use a larger
value of Cc , with typical values between 0.01 and 0.1 fJ.F. Like
many aspects of design, the value of Cc will be a tradeoff: higher
values of Cc will lower the high-frequency distortion, reduce the
high-frequency crosstalk and improve the signal channel phase
response. Conversely, lower values of Cc will provide a higher
control channel bandwidth at the expense of degraded linearity
in the output response when amplitude modulating a carrier
signal.
Diode DI clamps the logarithmic control node at Pin 2 of the
AD539, (preventing this point from going too negative); this
diode helps decrease the circuit recovery time when the control
input goes below ground potential.
THE AD539/5539 COMBINATION AS A FAST, LOW
FEEDTHROUGH, VIDEO SWITCH
Figure 47 shows how the AD539/5539 combination can be used
to create a fast video speed switch suitable for many high-frequency
applications including color key switching. It features both
inverting and noninverting inputs and can provide an output of
:!: IV into a reverse-terminated 750 load (or :!:2V into 1500).
An optional output offset adjustment is provided. The input
range of the video switch is the same as the output range: :!: I V
at either input generates :!: I V (noninverting) or + I V (inverting)
across the 750 load. The circuit provides a gain of about I,
when "ON", or zero when "OFF".
Figure 46. Transient Response of the Voltage-Controlled
Amplifier Vx = +2 Volts, Vy = ± 1 Volt
The control channel bandwidth will vary in inverse proportion
to the value of Ce , providing a typical bandwidth of 2MHz with
aCe ofO.Olf1F and a Vx voltage of + 1.7 volts.
Both the bandwidth and pulse response of the control channel
can be further increased by using a feedforward capacitor, Cff ,
with a value between 5 and 20 percent of Ce . Cff should be
carefully adjusted to give the best pulse response for a particular
step input applied to the control channel. Note that since Cff is
connected between a linear control input (Pin I) and a logarithmic
node, the settling time of the control channel with a pulse input
will vary with different control input step levels.
The differential configuration uses both channels of the ADS39
not only to provide alternative input phases, but also to eliminate
the switching pedestal due to step changes in the output current
as the AD539 is gated on or off.
Figure 49 shows the response to a pulse of 0 to + I V on the
signal channel. With the control input held at zero, the rise
time is under IOns. The response from the inverting input is
similar.
The differential-gain and differential-phase characteristics of this
switch are compatible with video applications. The incremental
gain changes less than 0.05dB over a signal window of 0 to
J3
7511 @7511
lOll
+ 9V o--'II\I'Ir-.--1
-& OUTPUT
+9V
27!1
Rx
47011
Jl
INVERTING ~
INPUT
~
751l ~
SIGNAL
I~
OPTIONAL
TERMINATION
NONJ2 \
INVERTING
INPUT
~-.:.,~~-t---i
lnF
+9
V
751l
'V
lOOk
I
-.AJVV1
1011
- 9V o--'II'II'r---4H
~
50k
Vos
-9V
-9V
J4 7511
n
t---t-~~----@CONTROL~
DENOTES SHORT,
DIRECT CONNECTION
TO GROUND PLANE
-&
887!1
-9V
L-
INPUT
+ IV (OFF)
0 (ON)
'VALUEWILL VARY SLIGHTLY
WITH COMPONENT LAYOUT
j
Figure 47. An Analog Multiplier Video Switch
OPERATIONALAMPLIFIERS 2-197
+ I V , with a phase variatio~ ofless than 0.5 degree at the subcarriet
frequency of 3.58MHz. The noise level of this circuit measured
at the 75.0 load is typically 200jLV in a 0 to 5MHz bandwidth
or approximately lOOnV per root hettz. The noise spectral density
is essentially flat to 4OMHz.
The waveforms shown in Figures 48 and 49 were taken across a
75.0 termination; in both photos, the signal of 0 to + I V (in this
Figure 48. The Control Response of the Video Switcher
2-198 OPERATIONAL AMPLIFIERS
case, an offset sine wave at IMHz) was applied to the noninverting
input. In Figure 48, the envelope response shows the output
being fully switched in about sOns. Note that the output is ON
when the control input is Zeta (or more negative) and OFF for a
control input of + IV or more. There is very little control-signal
breakthrough.
Figure 49. The Signal Response of the Video Switcher
1IIIIIIII ANALOG
WDEVICES
Wide-Bandwidth, Fast-Settling
Operational Amplifier
AD9610 I
FEATURES
Ultrastable Unity Gain Bandwidth (100MHz)
18ns Settling Time to 0.1%
Superior dc Performance
Offset Voltage ±0.3mV
Bias Current 2 ....A
±21mA Supply Currents
AD9610 FUNCTIONAL BLQCK DIAGRAM
33-5011
r--""'''''---'''
BYP~SS
j;
01"F
"
-INPUT--'--JO''-----'
APPLICATIONS
Driving Flash Converters
High-Speed DACs
Radar. IF Processors
Photodiode Preamps
ATE/Pulse Generators
Imaging/Display Drivers
OUTPUT
BYPASS
~ 33 _ 5011
BOTTOM VIEW
i
;T·Olj.tF
'V
GENERAL DESCRIPTION
The AD9610 is a fast-settIing, wide-bandwidth dc-couplcd
transimpedance operational amplifier which combines superior
dc specifications and exceptional dynamic performance. That
combination provides remarkable versatility and utility for
high-speed designers.
Thin-film technology and innovative design techniques help
assure stable operation over the complete operating temperature
range. Input offset voltage temperature drift is typically 5....Vf'C;
input bias current drift is typically 70nAf'C.
Unique internal architecture keeps the AD9610 inherently stable
over its complete gain range and assures wide bandwidth at all
gain settings. With G= -I, 3dB bandwidth is lOOMHz; with
G= -10, bandwidth is 95MHz. When G= -20, 3dB bandwidth
is an incredible 75MHz. Slew rate, rise time, fall time, and
settIing time are also independent of gain.
dB
-3L--L__~~__~~~~__~~__~~
o
10
20
30
40
50
MH,
60
70
80
90
100
AD9610 Inverting Gain
The design of the AD9610 makes it easy to apply. The unit is
internally compensated and needs no external compensation. An
internal 1. 5kO feedback resistor is available to the user by connecting Pin 4 ,to output Pin 11. Pins 2 and 8 are bypass pins
and should be connected to ground through 33 - son resistors
and O.I ....F ceramic capacitors; effective decoupling of the power
supplies is also important for proper operation.
Two temperature ranges are available. The AD9610BH is guaranteed over a case temperature range of - 25"C to + 85"C; the
AD96IOTH is for a range of - 55"C to + 125"C. Standard devices
are produced in a MIL-STD-I772-certificd facility; contact the
factory for information on units screened to MIL-STD-883.
OPERAT/ONALAMPLIFIERS 2-199
SPECIFICATIONS
DC ELECTRICAL CHARACTERISTICS (±v= ±l5V;Av= -10;RtN=15011O;~=15kO;NolIu.a)
Parameter(ConditioDS)
I
I
I
Offset Voltage
OffsetVoitageTc 3
Input Bias Current
Inverting
N oninverting
I Input Bias Current T c 3
Inverting
N oninverting
# Inverting Impedance
# Noninverting
Impedance
Capacitance
# Common-Mode Input
I Internal Feedback Resistor (Rp)
SubGroup
AD9610BHrrH
Typical
@+25"<:
1,2,3
2,3
±0.3
±5
1,2,3
1,2,3
±5
±15
2,3
2,3
±70
±30
20
200k
2
±5
1500
# Rp Temperature Coefficient
Common-Mode Rejection Ratio (CMRR)4
CMRR(Rp= 15000;RIN = 1500;<1Vs =5V)
I Common-Mode Sensitivity (CMS),s
Referred to Input (<1 Vs = 5V)
-CMS
+CMS
CMSVOLTAGE
# Output Impedance (de 10 100kHz)
I Output Voltage Swing (RLOAD = 2000)
# Output Current
(Continuous)
I Open Loop Transimpedance Gain (2000 Load)
I Supply Current"
Power Consumption"
I Power Supply Rejection Ratio (PSRR)4
PSRR(Rp = 15000; R'N = 1500; <1Vs = 10V)
I Power Supply Sensitivity (PSS),7
Referred to Input (<1Vs = 10V)
PSSVOLTAGE
-PSS
+PSS
I
AD9610BH1
MinlMax@
-25"<:
+25"<:
+85"<:
±1.0
±4.0
± IS
±50
±56
±75
-55"<:
AD9610THl
MinlMax@
+25"<:
+ 125"<: Units
±2.5
±4.0
±25
± 1.0
±2.5
±25
mV
±35
±62
±56
±75
±15
±50
±35
±62
"A
"A
±330
±200
nArC
nAl"C
0
±330
±200
±5
14901
1510
±5
±5
±5
±25
;,,35
±25
;,,35
;,,35
±25
;,,35
±5
14901
1510
±5
"vrc
0
pF
V
;,,35
±25
;,,35
0
ppmFC
dB
dB
8
8
;,,50
"AN
"AN
4,5,6
>50
>60
4,5,6
4,5,6
4,5,6
3
3
62
0.05
±1O
±50
8
8
;,,50
8
8
;,,50
8
8
;,,50
8
8
;,,50
8
8
;,,50
2::±9
;,,±50
~±9
;:::±9
;,,±50
~±9
;:::±9
2:±9
;,,±50
;,,±50
;,,±50
;,,±50
>1.5
21
630
>50
>60
;,,0.7
,,;,27
,,;,810
;,,35
;"0.9
,,;,25
,,;,750
;,,35
;,,0.7
,,;,27
,,;,810
;,,35
;,,0.7
,,;,27
,,;,810
;,,35
;,,0.9
,,;,25
,,;,750
;,,35
;,,0.7
,,;,27
,,;,810
;,,35
65
3
3
50
8
8
50
8
8
50
8
8
50
8
8
50
8
8
50
8
8
"AN
"AN
1,2,3
4,5,6
1,2,3
4,5,6
4,5,6
4,5,6
4,5,6
dB
0
V
rnA
MO
rnA
mW
dB
dB
dB
AC ELECTRICAL CHARACTERISTICS (±v= ±l5V;Av= -10; R =l500; R =1.5kfi; RuwJ=2000l
rt
Bandwidth ( - 3dB)(Vo UT = 100mV POp)
4,5,6
I G= -10
Amplitude of Peaking:
4,5,6
I DCt060MHz
# >60MHz
# Phase Nonlinearity (de to 45MHz)
# Rise (Fall) Time (VOUT = 5V Step)
# Slew Rate (VOUT = 18VStep)
# SettiingTimetoO.I%(G=,IO;
5V Output Step)
# SettJingTime to 0.02% (G= -10;
5V Output Step)
# Overshoot Amplitude (VOUT = 5V Output Step)
# Propagation Delay
I Total Harmonie Distortion (Freq. = 20 MHz;
4,5,6
Output Voltage = 2V pop)
# Input Noise (RLOAD = 1000)
Voltage (5MHz to 150MHz)
Current (5MHz to 150MHz)
2-200 OPERATIONALAMPLIFIERS
F
>100
;,,80
;,,80
;,,80
;,,80
;,,80
;,,80
MHz
0
0
I
<3.5
>3.5
,,;,0.4
,,;,0.6
,,;,0.2
,,;,0.3
,,;,1.0
,,;,1.8
,,;,0.4
";'0.6
";'0.2
,,;,0.3
,,;,1.0
,,;,1.8
dB
dB
,,;,4
;,,3
,,;,4
;,,3
,,;,4.3
;,,2.4
,,;,4
;,,3
,,;,4
;,,3
,,;,4.3
;,,2.4
ns
kV/"s
18
,,;,29
,,;,25
,,;,29
,,;,29
,,;,25
,,;,29
ns
30
<4
3.3
,,;,14
,,;,4.0
,,;,8
,,;,4.0
,,;,18
,,;,4.0
,,;,14
,,;,4.0
,,;,8
,,;,4.0
,,;,18
,,;,4.0
ns
%
ns
55
50
50
50
50
50
50
dB
0.7
23
,,;,1.2
,,;,29
,,;,1.5
,,;,30
,,;,2.0
,,;,35
,,;,1.2
,,;,29
,,;,1.5
,,;,30
,,;,2.0
,,;,35
nV/vHZ
pAlvHZ
,
AD9610BHITH
Typical
@+2SoC
SubGroup
Parameter
OTHER INFORMATION
Case to Ambient, SCA8
(Still Air; No Heat Sink)
Case to Ambient, SCA8
(500 LFPM Air; No Heat Sink)
MTBF9
AD9610BH
MiniMax
-2SoC
+2SoC
+8SoC
-SsoC
AD9610TH
MinlMax@
+2SoC
+12SoC Units
65
*
*
*
*
*
*
OCIW
38
*
*
*
*
*
*
·CIW
;,,1.48 X 106
*
*
*
*
*
*
hours
PACKAGE OPTION 10
TO-8 (H-IZA)
AD9610BH
AD96 10TH
NOTES
j 100% tested (See Notes I and 2).
# Specifications guaranteed by design; not rested.
'Specification same as AD9610BHlTH typical specification.
iAD%lOBH parameters preceded by a check (j) are tested at + 25°C ambient temperature; performance is guaranteed over the
industrial temperature range ( - 25°C to + 85°C) case temperature.
'AD96lOTH parameters preceded by a check C/) are tested at 55·C case, + 25·C ambient, and + \25·C case temperatures.
Mil-processed versions are available.
30ffser voltage T c and bias current Teare guaranteed over the respective temperature ranges.
'CMRR and PSRR apply only for stated conditions.
sCMS values can be used to determine the CMRR for specific gam settmgs according to the followmg worst case relationships:
R,
>--"'-0
j.VOUT
= [-CMS) [R,) [j.VSUPPLY)
[1 +~ ]
+ [+CMS) [R2)
VOUT
[.l.VSUoPLY) + [CMSyoLT)
[1 +~ ]
[.l.VSUPPLY)
WHERE j.VSUPPLY = .l-VSUPPLY AND .l.+VSUPPLV
CMRR = -20 LOG
r
( 1 +
j.VOUT
~X .l.VSUPPLY)
]
6S upp ly current and power dISSIpation numbers are for qUiescent operation (mput IS grounded). Values increase with
hIgher frequency operation.
7PSS values can be used to determIne the PSRR for specIfic gam settIngs accordIng to the following worst case relationships
(See diagram in 5 above):
[1 + ~J
j.VOUT = [-PSS) [R,) [j.VSUPPLY) + [+PSS) [R2)
WHERE
AVSUPPlV
=
r
A-VSUPPlV
PSRR = -20 LOG
( 1 +
OR
[.lVSUPPLY) + [PSSYod
[1 +~ ]
[.l.VSUPPLY)
A+VSUPPlY
j.VOUT
~ X .l.VSUPPLY )
]
8Recommended maXImum Junction temperature IS + 165°C. See Thermal Model.
'MTBF calculated usmg MIL-HNBK 217D; Ground Fixed; Temperature (case) ~ + 70·C.
IOSee Section 16 for package outlIne mformauon.
Specifications subject to change Without notice.
EXPLANATION OF GROUP A MILITARY SUBGROUPS
Subgroup
Subgroup
Subgroup
Subgroup
Subgroup
Subgroup
I - Static tests at + 25°C.
2 - Static tests at maximum rated temperature.
3 - Static tests at minimum rated temperature.
4 - Dynamic tests at + 25°C.
5 - Dynamic tests at maximum rated temperature.
6 - Dynamic tests at minimum rated temperature.
Subgroup 7 - Functional tests at + 25°C.
Subgroup 8 - Functional tests at maximum and minimum
rated temperatures.
Subgroup 9 - Switching tests at + 25°C.
Subgroup 10 - Switching tests at maximum rated temperatures.
Subgroup II - Switching tests at minimum rated temperatures.
Subgroup 12 - Periodically sample tested.
ABSOLUTE MAXIMUM RATINGS
Supply Voltages (±Vs) . . . . . . .
Operating Temperature Range (case)
AD9610BH
AD96IOTH . . . _ . . . . . . ..
±18V
- 25°C to + 85°C
- 55°C to + 125°C
Power Dissipation . . . . .
Junction Temperature . . .
Storage Temperature Range
Lead Temperature (soldering, 10 sec)
See Thermal Model
+ 165°C
-65°C to + 150°C
'+300°C
OPERATIONAL AMPLIFIERS 2-201
-15V
R'N
2.
1...._+-__......__ +15V
RIN = RNC55H2001 F
RF = RN55C7501F
10"F = M39003101-2302
o 1"F=M39014101-1553
THIS MICROCIRCUIT IS COVERED BY TECHNOLOGY GROUP{I) PER MIL-M-38510
AD9610 LIFE TEST/BURN-IN CIRCUIT
THEORY OF OPERATION
The advantages of the transimpedance AD9610 Operational
Amplifier become easier to understand when its operation is
compared to the operation of conventional high-speed op amps.
The operation of the AD9610 Operational Amplifier is similar
to a standard voltage-input differential amplifier in terms of
setting gain and calculating noise. The primary difference between
the two types is a low-impedance inverting input on the AD9610;
this causes the unit to use current feedback, rather than voltage
feedback, to achieve signal amplification.
For purposes of discussion, assume the amplifier shown in
Figure I exhibits a single-pole frequency response. When it
does, A(Ol) = Ao/(I + jOlT) where Ao = open loop gain; and
liT = the roll-off frequency. When these terms are substituted
into Equation C, the result is:
VOUT =
VIN
-AoRsRF/(RsRF + RlNR F+ RINRS)
l+jOlT+[AoRINRs/(RsRF+RINRF+ RINRS)]
Based on the idea that
Figure 1 and the discussion which follows help make a comparison
between the AD9610 and "conventional" devices.
Two equations are necessary to describe the amplifier shown in
Figure 1.
is approximately equal to
AoRINRS/(RsRF + RINRF + RINRS)
V OUT
and G (closed loop gain) = RF/R IN , it becomes possible to
simplify and substitute terms in the above equation to obtain:
Figure 1.
One equation is a rudimentary amplifier transfer function:
-VOUT = A(Ol) Vs
(EquafionA)
and the other sums the currents at the inverting input:
VS-VlN + Vs + VS-VOUT = 0
RIN
Rs
RF
(Equation B)
Rearranging and reducing Equation B; and substituting from
Equation A results in a third equation:
The fundamental difference between the AD9610 and traditional
amplifiers becomes apparent at this point.
In traditional voltage-imput amplifiers, the input resistance (Rs)
approaches infinity. Consequently, I/Rs approaches zero; and
the term RF (I/RIN + I/Rs + I/RF) simplifies to the term
RF (I/RIN + I/RF). The latter can be reduced further to (G+ I).
When substitutions are made, the gain/frequency relationship
for a traditional amplifier design is expressed as:
-G
+ jOlT [G+I]
Ao
2-202 OPERA TlONALAMPLlFIERS
There is a dramatically different result for the AD9610.
This difference is because the value of Rs in the transimpedance
amplifier is only 20n. This is important when one realizes
Rs I RIN II Rp; and Rs «
-. J. INVERTINGAND~~
NONINVERTING GAINS
~ ~ }_
A y = (50
-'5
A y = :!:10
-20
-25
'\
0
.
-35
Z
-45
ffi
-50
;;:;
-55
Z
-40
"
>
Ay = :!:50
II
i?/
S"t
PHASE~~V
/
2•
'l±lO
'20
105
.0
75
~'-
.0
~
III
1 L J
-I-t"r
,
t:
iiiw
~
a:
45
30
1\
'5
,G
'00
10
'0
'3'
\,
\,
Z
Z
'50
m~
'I ~\\
Z -30
c
,5
~:.--
I
-60
'Oll
'8.
,.5
.fI1Av " ' " '2&
FREQUENCY - MHz
80
70
"Ej
/
vo","I,OV /
60
50
/
/
40
/
20
..,...-
10
~V
40
f
::---
80
60
............
100
--------'20
-
.,.......-
V ouT =:5V
/'
30
AD9610 Frequency Response (Av= ± t ±2, ±5, ± 10,
±50)
00
.-
~ -02
VOUj=2V_ -
I
~ -06
~ -08
I
'40
'.0
'80
20
Figure 8. Junction Temp. Rise vs. Load Current
The data in this illustration are typical characteristics when the
AD9610 is operated from ± ISV supplies. Assume the desired
output from the op amp is ± lOY swings at ± SOmA currents.
For this combination, maximum junction temperature will be
100°C above the ambient temperature.
Since maximum allowable junction temperature is + 165°C, the
maximum ambient temperature which can be tolerated is + 65°C.
If there is a possibility the ambient may exceed this limit, heat
sinking and/or heat removal is required. Additional details on
the thermal characteristics of the unit are included in the AD9610
Thermal Model. (For more information on thermal protection,
consult the Analog Devices application note "Using the AD9610
Transimpedance Amplifier".)
~TCASE
PNPN
Ilea
t
P""
Av -±lO=-\
-12
~ =~:
Ay = :!:50
z
c -18
:i
-24
~ -26
-
-28
-30
,
10
100
AD9610 Frequency Response (Av= ±" ±2, ±5, ± 10,
±50)
112
108
'04
100
----
0 ••
TAMalENT
080
/'
/'
/'
--
,..-
i/
/
./
07.
10
PCIRCUIT=lcc[+Vcc -(-Vee)) WHERE Icc =21mA(fI ±15V
'G
FREQUENCY - MHz
0.2
+
b---'"
~ -22
g
084
PCIJU;UtT
\
-20
088
t
J
,i.", &1 ±5 1-
J
j
(SEE SPECIFICATIONS)
.... TjPNP
+-T,NPN
t
(COMPONENTS
OTHER THAN
TRANSISTOR
JUNCTIONS}
2tD·eIW
210·CIW
ffi
>
Av=
,\
\
~ -10
T, ABOVE Ta (C}
53
I
"- ~'\."..
-04
"
'2
13
'4
'5
'6
P xxx = [(:tVee) -VOUT -ICOltS)] (Icod (% DUTY CYCLEI
NOTE xxx = NPN OR PNP
(FOR POSITIVE VOUT AND Vee. THIS IS POWER IN NPN OUTPUT STAGE
FOR NEGATIVE VOUT AND Vee. THIS IS POWER IN PNP OUTPUT STAGE
leol- =VouT/RwAD or 3 OmA, WHICHEVER IS GREATER
FEEDBACK RESISTOR RF IS INCLUDED IN RwA )
T]jPNPl = PPNP (210
+ IIca) +
(PCIRCU1T
+
PNPN) III cal
+
Bandwidth vs. Vec
Ta SIMILAR FOR TJ1NPNI
AD9160 Thermal Model
OPERA TlONALAMPLlFIERS 2-205
11
/
'0
>
/
",
~
9
/
g
5
1;
8
/
o
V
11
~
OO,tj:ttit:ti1tt:tI1tt:tjjtt:tj~:tjj1t!:t!n
lOOk
10M
100M
10k
'00
'G
'k
'M
FREQUENCV - Hz
,.
13
'2
Small-Signal Output Resistance vs. Frequency (G= -10)
'5
'6
±V
-70
-80
-90
-100
-110
~ -120
-130
~ -140
-< -150
Output Voltage vs. Vee
,
11.
"'"
112
.............
11 0
, 08
1/
6
•
iE
,/
-,GO
-170
-180
-190
/
1.02
'00
....- V
j
'04
098
•
,
I
v cc -
'0
'0
'0•
'00
,k
'Ok
lOOk
'M
'OM
100M
,G
FREQUENCY - Hz
/
Small-Signal Output Phase Shift vs. Frequency (G= -10)
09
200
.00
6..
800
'k
2k
Bandwidth vs. Load
GAIN= -10; 5V OUTPUT. ERROR WINDOW (±5mVI = 01%. 5nsiDIV
AD9610 Settling Time
GAIN = -10; 136mVIDIV; 10n51D1V
AD9610 Small-Signal Pulse Response
GAIN = -10; 3.4VIDIV; 10nsiDIV
AD9610 Large-Signal Pulse Response
2-206 OPERA TlONALAMPLlFIERS
ORDERING INFORMATION
Two models of the AD9.610 Operational Amplifier are available.
The AD96lOBH is specified for operation over a case temperature
range of - 25°C to + 85°C; the AD96lOTH is intended for
applications in which case temperature may be between - 55°C
and + 125°C.
1IIIIIIII ANALOG
WDEVICES
Wide Bandwidth, Fast-Settling
Operational Amplifier
AD9611 I
FEATURES
Unity Gain Stable
Small-Signal Bandwidth 280MHz
Full Power Bandwidth 210MHz
Settling - 13ns to 0.1"10
Rise/Fall Times 1.3ns/1.5ns
Offset Voltage ±0.5mV
Bias Current ± 1J.lA
Power Dissipation Independent of Load
APPLICATIONS
Driving Flash Converters
High-Speed DACs
Radar, IF Processors
Baseband and Video Communications
Photodiode Preamps
ATE/Pulse Generators
Imaging/Display Applications
GENERAL DESCRIPTION
The AD9611 is an ultrafast-settling, wide-bandwidth, dc-coupled
operational amplifier that combines exceptional ac and de specifications to establish a new standard of excellence in dc-coupled
amplifiers.
Rise and fall times are I. 3ns and I. Sns, respectively. The - 3dB
bandwidth is 280MHz (G = - 5); the full-power bandwidth is
210MHz. The AD9611 settles to 0.1% in Bns, and de performance
is also exceptional. Offset voltage is ±O.SmV and drifts only
SJ.1V/oC. The inverting and noninverting bias currents are IJ.1A.
The AD9611 requires ± SV power supplies and employs an
innovative current-steering output stage that keeps the total
circuit power dissipation essentially constant regardless of output
drive (for loads os lOOn). Circuit power dissipation does not increase
as the load is increased; the unit can be operated up to + 110°C
in still air without heat sinking.
AD9611 FUNCTIONAL BLOCK DIAGRAM
GROUND
-Vee
VOUT
+ Vee
GROUND
BOTTOM VIEW
Current feedback is used instead of voltage feedback to provide
dynamic performance that is relatively independent of gain
settings. Flat gain and phase response combine with excellent
noise and distortion performance to provide a unity-gain-stable
amplifier especially well suited for use in digital communication
systems. The AD9611 is an excellent choice for driving the
newest generation of ultrahigh-speed flash converters when
system SNR and effective number of bits are important.
The AD961 I is constructed with discrete transistors on a precision
thin-fIlm substrate. The AD961lBH is rated for case temperatures
from -25°C to + 85°C; the AD9611TH is guaranteed from
- 55°C to + 125°C. Contact the factory for information about
883 grade parts. All units are built and tested in a MIL-STD-1772certified facility.
OPERA TlONAL AMPLIFIERS 2-207
SPECIFICATIONS
DC ELECTRICAL CHARACTERISTICS {+Ys=
. -5'RIN=200o-~B=lkO'RlOAO
.
. =100fi)
- -+5Y'Av=
Parameter (Conditions)
j
Offset Voltage
# Offset Voltage Tc3
j Input Bias Current
Inverting
Noninverting
Input Bias Current T c 3
# Inverting
# Noninverting
N oninverting
Impedance
Capacitance
j Common-Mode Input Range
j Internal Feedback Resistor (RFB )
SubGroup
AD9611BHITH
Typical
@+2S'C
Common·Mode Rejection Ratio (L1VCM = 0.5V)4
Common-Mode Sensitivity (CMS)'
Referred to Input
-CMS
+CMS
Output Impedance (de to IMHz)
Output Impedance@ looMHz
j Output Voltage SWing
# Output Current (continuous)
# Open-Loop Transimpedance Gain (lOOn Load)
j + Supply Current(5V)6
j - Supply Current( - 5V)"
Power Consumption"
j Power Supply Rejection Ratio (L1 Vs = 0.5V)4
j Power Supply Sensitivity (PSS)7
Referred to Input
-PSS
+PSS
-WC
AD9611TH2
Min/Max@
+2S'C
+ 12S'C Units
1,2,3
±0.5
±5
±5.0
±3.0
±4.3
±5.0
±20
±3.0
±4.3
±20
mV
!LVI'C
1,2,3
1,2,3
±I
±I
±40
±25
±5
±5
± 19
± 15
±40
±25
±5
±5
±19
± 15
!LA
!LA
±275
± 175
nAl'C
nAl'C
±140
±75
1,2,3
150
3
± 1.5
1000
# R pB Temperature Coefficient
j
j
AD9611BH'
Min/Max@
-2S'C
+2S'C
+8S'C
4,5,6
42
4,5,6
4,5,6
5
5
0.03
004/18
±3
±50
>0.35
70
74
720
1,2,3
±275
± 175
±lo4
9871
1013
±25
:2032
±lo4
9901
1010
:524
:524
:520
:520
:524
:524
:524
:524
:2034
± 1.25
9871
1013
±25
d2
n
ppml'C
dB
:520
:520
:524
:524
!LAN
!LAN
n
!l!nH
4,5,6
46
:20±2.8
:20±40
:200.1
:585
:588
:5865
:2035
4,5,6
4,5,6
4
4
:517
:517
1,2,3
1,2,3
±lo4
9871
1013
±25
:2032
±lo4
9901
1010
:2034
± 1.25
9871
1013
±25
:2032
kn
pF
V
:20±2.8
:20±2.5
:20±2.8
:20±2.8
~±40
~::t40
~±40
~±40
:200.2
:577
:580
:5785
:2037
:200.2
:577
:580
:5785
:2035
:200.1
:585
:588
:5865
:2035
:200.2
:577
:580
:5785
:2037
:20±2.5
2::±40
:200.2
:577
:580
:5785
:2035
:514
:514
:517
:517
:517
:517
:514
:514
:517
:517
V
rnA
Mn
rnA
rnA
mW
dB
iJ-AIV
!LAN
AC ELECTRICAL CHARACTERISTICS (±Ys = ±5Y;Av= -5; R1N =200!l; R =lk!l; RlOAO =l00!l unless otherwise specified)
FB
j
j
j
#
#
#
#
#
#
#
j
j
Bandwidth ( -3dB)(VouT = IVp·p)
Full Power Bandwidth (VOUT = 3V p-p)
Slew Rate
Amplitude of Peaking:
de to 70MHz(VouT = IVp·p)
>70MHz(VOUT= IVp-p)
Phase Nonlinearity (de t,o 120MHz)
Rise Time (VOUT = I V Step)
Fall Time (VOUT = IV Step)
Rise Time (VOUT = 3VStep)
Fall Time (VOUT = 3V Step)
Settling Time to 1%
(V oUT =1.5VStep)
Settling Time to 0, 1%
(V OUT = 3V Step; RL = 50n)
Settling Time to 0.05%
(VOUT = 3V Step; RL = 50n)
Overshoot Amplitude (VOUT = 2V Step)
Overdrive Recovery to 1% (2X; 50ns)
Positive Rail to Linear Region
Negative Rail to Linear Region
Propagation Delay
2nd Harmonic Distortion
(f = 60MHz; VOUT = 2V p-p)
3rd Harmonic Distortion
(f=60MHz; VOUT = 2Vp-p)
2-208 OPERATIONALAMPLIFIERS
4,5,6
4,S,6
4,5,6
:20250
:20220
:20250
?250
?220
MHz
MHz
>280
>210
1900
:20250
°°
0.2
:50.8
0.2
:50.8
0.2
:51.6
0.2
:50.8
0.2
:50.8
0.2
:51.6
1.5
104
1.6
7
:51.5
:51.7
:51.6
:52.0
:512
:51.5
:51.7
:51.8
:52.0
:512
:51.7
:51.9
:52,1
:52,1
s13
:51.5
:51.7
:51.6
:52.0
:512
:51.5
:51.7
:51.8
:52.0
:512
:51.7
:51.9
:52,1
:52.1
:513
ns
ns
ns
ns
ns
13
:519
:519
:522
:519
:519
:522
ns
V/!Ls
I
1.3
.
ns
16
4
dB
dB
:514
:514
-,;18
:514
:514
:518
%
4,5,6
20
40
2.1
-54
-,;-50
:5 -50
:5 -42
:5 -50
:5 -50
'S
-42
ns
ns
ns
dB
4,5,6
-58
:5 - 51
:5 - 51
:5-44
:5 - 51
:5 - 51
:::;;~44
dB
SubGroup
Parameter
AD9611BHrFH
Typical
@+25'C
AD9611BH
MinlMax@
-25'C
+ 25'C
+ 85'C
-55'C
AD9611TH
Min/Max@
+25'C
+125'C Units
::::1.4
"25
,,92
"1.4
"25
"92
Noise
#
#
#
Vollage (5MHz 10 28OMHz)
Currenl (5MHz 10 280MHz)
EqulValenllnlegraled Inpul
(5MHzI0280MHz)
1.0
21
75
"14
"25
,,92
Other Information
Case toAmblent,8cA8 •9
(Slill AIr; No Heal Smk)
50
Case to Ambient, 8CA8,9
30
(500 LFPM AIr; No Heal Smk)
MTBF (Mean TIme Belwen Fatlures)
~196x106
sl7
,,28
,,106
"1.4
,,25
,,92
"1.7
,,28
,,106
· · · · · ·
· · · · · ·
· · · · · ·
(TCASE = 70OC, Ground Fnred;
nV/v'iiz
pA/v'Hz
!LV
'CIW
'CIW
hours
per MIL-HDBK-217D)
PACKAGE OPTION IO
TO-8(H-12A)
AD96IlBH
AD96IITH
For apphcatlons asslStance, call Computer Labs DIVISIon (ll (919) 668-9511
NOTES
j 100% lesled (See Noles I and 2)
# Specifications guaranteed by deSign, not tested
*Specliica[1on same as AD9611BHlTH tYPiCal speCification
I AD9611BH parameters preceded by a check (j) are tested at + 25°C ambient temperature, perfonnance IS guaranteed over the
IDdustnal temperature range ( - 2SOC to + 85°C) case temperature
2AD9611TH parameters preceded by a check (,J) are tested at - 55°C case, + 25°C ambient, and + 125°C case temperatures
lQffset voltage T c and bias current Teare guaranteed over the respective temperature ranges
4CMRR and PSRR apply only for stated conditions
sCMS values can be used to determme the CMRR for specific gam !)CtUDgs accordlOg [0 the followmg worst case relationships
.1Vou, = [-CMS] [R,] [.1V CM ]
CMRR
[+CMS] [R2]
-
= -20 LOG [
[1 + ~] [.1V
CM]
.1Vou, ]
( .1VcM I
6Supply current and power dlsslpaoon numbers are for qwescent operation (V IN =- OV). A proprietary output stage assures total Circuit power dlsSlpanon
does not mcrease as a funcnon of output current and RI OAI)' (See Text)
7PSS values can be used to detemnne the PSRR for specific gam setung~ according to the follOWing worst case relationships
(See diagram m 5 above):
.1VOUT = [-PSS] [R,] [.1Vsup",] - [+PSS] [R2]
WHERE AVSUPPLV
=
[1 + ~] [.1V
su ....,]
4-VSUPPLY OR A+VSUPPLY
PSRR = -20 LOG [
.1 You,
(.1VSUPPLY )
]
8Recommended maxlmwi. luncnon temperature IS + 165"C.
9Bottom of umt raised approximately 0 125" (3 2mm) above surface of copper-clad board
IOSee Section 16 for package outime mfonnauon.
SpeC1ficanons sublect to change without notice
ABSOLUTE MAXIMUM RATINGS
Supply Voltages (±Vs) . . . . . . . . . . . • . . . . . . ±6V
Analog InPUI . . . . . . . . . . • . • . . . . . . . . . . "'vs
Invertmg InPUI Sink Current . . . . . . . . . . . . .. 30mA
Continuous Output Current . . . . . . . . . . . . . . :t SOmA
Operating Temperature Range (Case)
AD96l1BH . . . . . . . . . . . . . . .. - 2S'C 10 + 85'C
AD96l1TH . . . . . . . . . . . . . . . . -55'C 10 +125'C
Power Dissipation . . . . . . . . . . • . . See Thermal Model
Junction Temperature . . . . . . . . . . . . . . .•
+ 165'C
Slorage Temperature Range . . . . . . • . . - 6S'C 10 + 15O'C
Lead Temperalure (soldermg, 10 sec.) . . . . . . . . + 300'C
EXPLANATION OF GROUP A MILITARY SUBGROUPS
Subgroup 1 - Sialic tests at + 25'C.
(10% PDA calculated agamst Subgroup 1 for hlgh-rei verstons)
Subgroup 2 - Static tests at maximum rated temperature.
Subgroup 3 - Stanc tests at minimum rated temperature.
Subgroup 4 - Dynanuc teslS at + 2S'C.
Subgroup 5 - DynamJc tests at maxunum rated temperature.
Subgmup 6 - Dynamic tests at minimum rated temperature.
Subgmup 7 - Funcnona1 lests al + 2S'C.
Subgroup 8 - Funcuonal tests at maxnnum and mimmum
rated temperatures.
Subgroup 9 - Switching lests al + 25'C.
Subgmup 10 - Switchmg tests al maximum rated temperatures.
Subgroup 11 - SWItchIng tests at mmimum rated. temperatures.
Subgroup 12 - Periodtcally sample tested.
OPERATIONALAMPLIFIERS 2-209
THEORY OF OPERATION
The advantages of using the transimpedance AD9611 operational
amplifier instead of a conventional high-speed op amp are based
on the difference in the way the two types of amplifiers operate.
The AD9611 operational amplifier uses current feedback, rather
than the voltage feedback common to traditional amplifiers.
Current feedback amplifiers provide significantly more bandwidth
at given gain settings than traditional amplifiers do.
Both types are similar in terms of setting gain and calculating
noise, but there is a major difference in the input stages when
comparing current feedback (transimpedance) amplifiers and
voltage feedback amplifiers.
Traditionally, conventional amplifiers have two high-impedance
inputs. Within the AD9611, however, the inputs are connected
across a unity gain buffer; this causes the noninverting input to
be a high impedance and the inverting input to be low impedance.
Under normal operating conditions, the inverting input current
is very small. The AD9611 operation is similar to a traditional
amplifier in that the voltage between the input terminals and
the bias currents are, ideally, zero.
R1
>-+-OVo
In the AD9611, Rp is internal and has a value of lkfl; this
design helps reduce the effect of stray capacitances and makes it
easier to apply the amplifier. The low input impedance at the
inverting input means all of the input signal voltage is impressed
across Rl; this causes a direct voltage-to-current conversion to
take place.
Using only the feedback resistor within the unit means the gain
of the AD961 I can be set by varying only RI.
APPLYING THE AD9611 OP AMP
In applying the AD9611 op amp, there are certain precautions
which must be observed to protect the unit from damage:
1. Shorting either power supply input pin (Pins 9/10 or Pins
1112) to the output (Pin 11) will destroy the device.
2. Shorting the output (Pin II) to ground will destroy the
device; no internal protection is included.
As noted earlier, the noninverting input of the AD9611 operational
amplifier is a high impedance. This requires that it be driven
from a low-impedance source, or connected to a low impedance
when used in the inverting mode. Driving this input from a
high impedance will reduce bandwidth. Feedback resistor Rp is
internal to the AD9611 and has been precisely adjusted to allow
a wide range of operating conditions. In some instances, the
user may want to obtain higher closed-loop gains than those
which can be achieved with only the internal feedback resistor.
It is possible to use an external feedback resistor in series with
the internal lkfl Rp to achieve relatively higher gains, but
bandwidth will be reduced. Table I lists typical bandwidths at
G = - 5 with varying amounts of feedback resistance. In this
listing, the Rp which is shown is the total resistance, including
the internal lkfl.
Figure 1.
Closed-loop bandwidth (CLBW) of the AD9611 is first-order
independent of its closed-loop gain (G). Its transfer function can
be expressed as:
1.
Vo
Vs ==
G
- 3dB Bandwidth
lkfl
I.SkH
2kH
2.Skfl
280M Hz
175MHz
13SMHz
l2SMHz
RF (
RN)
T(s) 1 + Rl + 1
Table I
where:
Rp is the internal feedback resistor; Rp = lkfl
Rl is the gain-setting input resistor
T(s) is the transimpedance gain as a function of
frequency (s) and is independent of gain-setting
resistors; T(s) = Vo (s)/I,r.{s)
G = RplRl (closed-loop gain)
RN is the open-loop input impedance (typically 22fl
in the 200MHz - 300MHz band)
When closed-loop gain is greatly increased, CLBW is only slightly
diminished because of the low input impedance of R N. The
ratio ofCLBW for any gain to CLBW at G = - 0 can be determined
using the following relationship:
2.
ValueofR F
CLBW (G=x) =
CLBW (G=O)-
(I - 0.022G)
As an example, when G = - 20, the CLBW will be 70% of the
CLBW when G = 0 (typically 31OMHz).
2-210 OPERATIONAL AMPLIFIERS
Good layout practices are always crucial to realize the full potential
of the AD9611. A massive ground plane is strongly recommended.
The ground plane provides a low impedance path for all power
supply and signal currents, and suppresses EM!.
Ceramic O.I ....F decoupling capacitors should be placed as close
to the specified pins shown in Figures 2 and 3 as possible;
preferably, the distance should be less than 0.1 inch. The (lO ....F)
tantalum capacitors for additional decoupling of each power
supply should be placed within one inch of their specified pins.
Run lengths must be kept as short as possible; if the signal path
must be longer than two or three inches, use terminated coaxial
cable and/or microstrip techniques. Impedance mismatches will
cause signal reflections and system distortion.
Output impedance of the driving source should equal RMATCHIIRI
(inverting mode) or RMATCH (noninverting mode). A suggested
layout is shown on the last page of this data sheet.
Parasitic capacitance associated with ZIF (and other) device
sockets will severely degrade the performance of the AD9611; if
sockets must be used, individual pin sockets for each lead are
strongly encoumged.
loads >8pF (if RL = 500) and >4pF (if RL = SOOn),
isolation resistor Rs should be connected in series with the
AD9611 output.
+5V
IF liN
=50n,
AMATCH
IIR1
=son
100
INPUT <>--_"""~-{
;-""",y.,.~-O
80
Vo
RLOAO
I
I
90
Rl =50H
70
I
I
I
I
u. 60
I
/
II
Co
I
GAIN
c5
= -:;
Rl =500H
50
40
RF = 1,OOOfllinternall
0
Rs· required if matching cable impedance or
driving loads with capacitance greater
/
./
20
than approximately 4pF
0
30
20
Rs-H
10
+5V
=1
J
./
0
Figure 2. AD9611 Inverting Operation
GAIN
I
/
40
Figure 5. Output Capacitance vs. Compensation
+ :;
RF = 1.000i!(internal)
Isolating the capacitive load from the amplifier's output is
particularly useful when driving flash AID converters.
REDUCING OUTPUT VOLTAGE DRIFT
The expected dc error at the output of the AD9611 is a function
of input offset voltage (VIQ), and inverting and noninverting
bias currents (lB- and IB +). The calculation is the same as it
would be for conventional amplifiers.
Rs * required if matching cable impedance or
driving loads with capacitance greater
than approximately 4pF
Bias currents vary inversely with temperature and typically,
track to within 10% of each other at high temperatures ( + 25°C
to + 125°C); and within 30% at low temperatures ( - 55°C to
+ 25°C).
+ 15
Figure 3. AD9611 Noninverting Operation
The best high-frequency performance of the AD9611 is achieved
when total output capacitance (Cd is at a minimum. Realistically,
this is not always possible; but performance can be improved if
a series resistor is used at the output of the amplifier, as shown
in Figure 4.
C(
+10
:!.
I
...z
III
+5
'"a:a:
()
""
~
...........
181As+
:::I
III
~~AS-
0
C(
~~
iii
--..
r-----...
-5
-10
-55 -35
~~
~
-15
+5
+25
+45 +65
+85 +105 +125
TEMPERATURE _·C
Figure 6. Bias Currents vs. Temperature
Figure 4. Isolating Capacitive Loads
The unit will drive capacitive loads without appreciable degradation in either settling time or pulse fidelity. For driving capacitive
Output offset voltage drift (VOD) in the inverting mode can be
markedly reduced, especially at high temperatures, by inserting
a resistor (R2) between the noninverting input (Pin 6) and ground.
This connection is shown in Figure 7.
OPERATIONALAMPLIFIERS 2-211
, For this confJgU1"ation, output offset voltage can be determined
as follows:
VO=VIO
(I + :~) + IB+ (Rl) (I + :~) - IB- (R
F)
where:
RI = gain-setting resistor
RF = internal feedback resistor (lkO)
Rl = RIIIRF
CS ;;, (I6,200IR2)pF
A shunt capacitor (Cs) must be connected in parallel with R2
when using this technique to maintain the amplifier's maximum
bandwidth, stability, and low-noise performance. The value of
the shunt is shown above.
Figure 7. Reducing Offset Drift
As an example, assume the AD9611 is set up for a gain of - 5;
RI should be 2000; Rl should be 167; and Cs should be 97pF.
Resistor Rl reduces VOD by indirectly nulling the bias current
drifts. The reduction in VOD is dramatically reduced from what
it would be by simply grounding Pin 6. At high gain settings,
the reduction in VOD becomes relatively less because V10 starts
to dominate.
AD9611 PERFORMANCE
The following graphs and drawings provide additional information
on the performance of the AD9611 transimpedance operational
amplifier. The data which are shown are based on typical
characteristics.
+3
+135
+3
+2
+90
+2
--
+1
GAIN
o
-1
.........,.",
I PHASE
!8 -2
~
3 1 - - - G=-1
-4
r--....
t---
Gj-l
-...........
I"--.. G= -5G--2(
"'""
~ ~-'<
--5" ~ ~'
G--20/
5
6
-45
."""'"
-90
~
50
150
100
200
+1
!
'"u,
..
w
c
250
GAIN
....-:::::
,~
Q
~ -2
'\ -135 it
"\ -180
~~
K"..........-
-7
o
+45
PHASE
--
~
270
6
315
7
t::::-....
0
I
\ po.
G=+~O~ -90
135
~--......
~
100
150
200
250
igo
Q
,
w
!il
iE
-180 ~
;::
225 ~
-270
II:
315
300
MHz
Gain and Phase vs. Frequency - Noninverting
,
5ns)olv
I\.
\
.....
45
.~
50
Gain and Phase vs. Frequency - Inverting
.
+45
~
II:
300
+90
G ,j'0
~~
G= +20 1
~
G-+l0
MHz
~oomv+v
"'""
t:--..."
G=+5~
,
4
5
-
=
G=+5
~I:--
-3
225 w
+135
~
"1
=-5
!
.... (\.- t--.
... 'r-;.' ....
. ... 'CX
AV =-5
.~
r-~---i~-+t--r--~AV~~t-t---~-i
~
Small-Signal Pulse Response
2-212 OPERA TIONALAMPLIFIERS
lot ...
"
A~=~
': i-J .. .... !\.,..-:r-
I
!
..
\
)
-
t-··-·~·--~~~·~~··~·~·-··-·~·-··-·r.-..-.+.-.~\.~r.~.~..+-~
Large-5ignal Pulse Response
150
45
1.
[
"-
40
TCASE (STILL AIR)
140
"'-
E
I-'
al
"+ 35
I
'":::>
130
0:
I-
Z
I-
«
0:
'"
::;
2
120
A.
"-
I
~
'"~
'"
I-
110
i'--
0
"'- ..........
25
f'...
.........
20
!'-- t----..
TAMBIENT (STILL AIR)
100
]
o
4
J
6
OUTPUT - dBM
10
14
12
15
10
16
This unique feature of the unit means that no heat sinking is
required in still air at ambient temperatures as high as + BO°C;
with air flow of 500 LFPM, the device can be operated to + 125°C
before heat sinking is necessary.
-70
-65
RLOAO
~
1
RLOAO = 100!1
-2
3
RLOAD
ID
-4
"
-55
100
150
200
250
~
-50
160 180
""
200
~~
I""
-45
20
30
40
50
60
70
80
Harmonics vs. Frequency
QA AND 08 ARE AD9611 OUTPUT TRANSISTORS.
PCIRCUIT IS TOTAL AD9611 POWER MINUS POWER OF THE OUTPUT TRANSISTORS
r-----~~-----1~--------_Q4-TC~E
\\'
(COMPONENTS
.,c
155"C1W
155°CIW
_T,.,.
'\
50
140
FUNDAMENTAL FREQUENCY - MHz
(R WAO =100!l; V ouT =2Vp-p; Av= -51
~\ I\"
~\
=
-5
120
.........
J250! 1
5011 ./
100
2NDLARM~ b'-~
-60
~ to 50011-
,
80
~DH1RMONlb
-40
10
2
o
60
3rd Order Two-Tone Intermod Intercept
(Gain = -5; RLOAD =50{},)
TEMPERATURE vs. OUTPUT POWER
The chart above illustrates an important characteristic of the
AD9611 amplifier. A proprietary design feature of the output
stage assures a constant case temperature regardless of the amount
of output power. This is in marked contrast to most conventional
amplifiers, in which increasing amounts of power raise the case
temperature of the device as junction temperature increases.
"
40
CENTER FREQUENCY - MHz
Maximum Temperatures vs. Output Power
al
20
-RLOAD =501l; NO HEAT SINK
t
300
p~
0.,.
(SEE SPECIFICATIONS)
OTHER THAN
TRANSISTOR
JUNCTIONS)
.TJOB
t
Pos
t
PClRCUIT
+
(520mWI
TAMBIENT
FREQUENCY - MHz
PctRCUlT
Bandwidth vs. RLOAD (Av= - 5)
= 520mW@
+25"C AND ±5V SUPPLIES
p~= = PQA+Poe=200mW IWORST CASE: VOUT=OV;
RlOAD=SOflI
~!~~~-VoUT)(20mA+~) (WORST CASE IS AT +2.0V]
TjQ8=PQBI1SS+0CAI+(PCIICUIT+PQA) IOCAI+TAMBIENf
=
TlOA PQAI1SS+0CA,}+ IPCllCUIT + PQA) lOCAl + TAMBIENT
AD9611 THERMAL MODEL
AD9611 Thermal Model
OPERATIONAL AMPLIFIERS 2-213
50
45
Operating Mode
Connect
Between
Inverting
R MATCH
Rl
Strap
Strap
Rl
R MATCH
EiandE2
E3 and ES
E6andE7
E8 and E9
E4andES
E9andEIO
40
"I'
35
!R
CMRR
"PSRR
I\.
30
25
\
Noninverting
t\
Table II.
20
15
10
lk
2k 4k
~ ~o
J1
~
V ~
10k 20k 40k lOOk 200k 400k 1M 2M 4M6Ml0M
FREQUENCY - Hz
AD9611 CMRR and PSRR
9
7
~6
:> 5
1N -
80
\
\
I'.
C4
~O
DC5
.......
@
oo
o
0
C6
C7
CJ CJ
.,.:;0;:8
+
C2
-5V
GND
@
@
1
30
2
10'
C3
GND~
@
V!:T
40
I'..
YOLTAGE ...... r--~
10'
CJ CJ
0..
V 1N
60~
5o
@
ET
7
\ \
4
+5V
~ O"~\ .:~\e 9
J2@®
\i1PDca
+
90
\CURRENT
1 \
1 ~
c
o
100
_\
\
GCl
10'
10'
10'
10'
107
1o
10'
AD9611 Suggested Layout Component Side, Viewed from
Top
G.>
'.'
FREQUENCY - Hz
Noise vs. Frequency
AD9611 LAYOUT INFORMATION
The suggested layout of the AD9611 shown below is based on
the proven performance of the AD9611 Evaluation Board. The
user is urged to use a similar layout when incorporating the
amplifier into the system in which it will operate.
In the layout, resistors are fUm; O.IW; ± 1%; SOppm. Capacitors
Cl and C2 are tantalum; lO/LF; 20%; 3SV. C3 - C8 are ceramic;
O.I/LF; 20%; SOY. Connectors 11 - J3 are Amphenol BNC type;
pin sockets are available from Amp as part number 6-330808-0
(closed end) or part number 6-330808-3 (open end).
The input connections shown below are based on the layout of
the evaluation board. Refer to Figure 2 (inverting operation)
and Figure 3 (noninverting operation) for schematic details.
:.;
o
"
::0
~.;
.. ' 0
(x)0~
,,
",
o
.. ..rD.;
•.
:~
" ... '~
::.
'.'
," : . . . . 0\.,
.. ,
" 0"
,',
"
I.
000 ':
1.', :0
.-
:.;
"
0
o
~Jf2______-<~
V
+
~
RMATCH
,
!
__~~-<6
tea
~10
~E7
RESISTORS SHOULO BE
FILM. 1/10 W. ± 1%
Suggested Layout Input Connections
2-214 OPERATlONALAMPLlFIERS
2.00
(50.8)
..I
3.00
(76.2)
AD9611 Suggested Layout Component Side (Top) Viewed
from Top
o
w
:.;
l
J
~
:J
2.00"
(50,8)
0
0
I....1--------
0 0
I
3.00"
(
76,2)-------1-
AD9611 Suggested Layout Solder Side (Bottom) Viewed
from Top
Ultrafast FET
Operational Amplifiers
ADLH0032G/ADLH0032CG I
r.ANALOG
WOEVICES
FEATURES
2nd Source; Replaces All LH0032G
High Slew Rate; 500V!j.ls
Wide 70MHz Bandwidth
Operation Guaranteed _55°C to +125°C (ADLH0032G)
High Input Impedance of 10 12 n
2mV Input Offset Voltage
ADLH0032G/ADLH0032CG PIN CONFIGURATIONS
NC
NON INVERTED
INPUT
INVERTED
INPUT
APPLICATIONS
ADC and SHA Input Buffers
High Speed Integrators
Video Amplifiers
OUTPUT
I
OUTPUT
COMPENSATION
TO-8 PACKAGE
BOTTOM VIEW
GENERAL DESCRIPTION
The ADLH0032G and ADLH0032CG are high slew rate, high
input impedance, differential operational amplifiers, suitable
for numerous applications in high-speed signal processing.
These second-source devices are the same in every characteristic as other LH0032G/LH0032CG amplifiers.
Featuring a wide 70MHz bandwidth, high input impedance
(10 12 n), and high output drive capacity, the ADLH0032G
and ADLH0032CG have already been designed into such
applications as summing amplifiers in high-speed DACs, Buffer
Amps in ADCs and high-speed SHAs, as well as other applications normally reserved for special purpose video amplifiers.
The ADLH0032G is guaranteed over the extended temperature range from -SSoC to +12SoC, while the commercial grade
ADLH0032CG is guaranteed from -2SoC to +8SoC. Both
devices are packaged in a TO-8 metal can package .
v+
NON-INV
INPUT
v-
Figure 2. Output Short Circuit Protection
.---<_--.<:) v+
INPUTS {
OUTPUT
vFigure 1- Offset Null
OPERATIONALAMPLIFIERS 2-215
SPECIFICATIONS
Model
ADLH0032G, ADLH0032CG
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Power Dissipation
Differential Input Voltage
Input Voltage
Operating Temperature Range ADLH0032G
ADLH0032CG
Storage Temperature Range .
Lead Temperature (soldering, lOsec)
±18V
See Characteristic Cu rYes
±30V
±Vs
-SSoC to +12SoC
-2SoC to +8SoC
-65°C to +150°C
300°C
Parameter
Conaitions
DC ELECTRICAL CHARACTERISTICS l
Input Offset Voltage 2
TJ = +25°C
ADLHOO32G
Min
Typ
2
Inpu t Offset Current'
TJ
= +25°C
5
Input Bias Current2
TJ
= +2SoC
10
Average Offset Voltage Drift
Large Signal Voltage Gain
Input Voltage Range
Output Voltage Swing
Power Supply Rejection RatIO
Common Mode Rejection Ratio
Supply Current
25
VOUT - ±lOV, F = 1kHz,
RL = 1kn, Tc =+2SoC
VOUT = ±lOV, RL = 1kn,
F .= 1kHz
R
= lkn
LWS - ±lOV'
L'>VII\! = 10V
Tc = +25"C
AC ELECTRICAL CHARACTERISTICS 3
Slew Rate
Av = +1, t.VIN = 20V
Settling Time
to 1% of Final Value
Av = -1, t.VIN = 20V
Settling Time
to 0.1% of Final Value
Ay = -I, t.VIN = 20V
Small Signal Rise Time
Ay - +1, t.V1N - IV
Small Signal Delay Time
Av = +l,t.VIN = IV
MTBF
Meantime Between Failures
Non,s
1.0608 X 10 7
These specifications apply for Vs = ± j 5V and ·-SS'C to +12S'C
for the ADLH0032G and -2S'C to +8S'C for the ADLII0032CG.
2 Due to high speed automatic test techniques employed these parameters
are correlated to junction temperature.
'These .pecifications apply for Vs = ± 15V, RL = lkfl, TC = +2S'C.
I
Specifications subject to change without notice.
ORDERING INFORMATION
Model
Temperature
Range
ADLII0032CG
ADLII0032G
-25°C to +85°C
-5SoC to +125°C
Package
tion *
TO-8 (H-12A)
TO-8 (H-12A)
°e
·See Section 16 for package outline information.
2-216 OPERATIONAL AMPLIFIERS
60
57
flO
±10
50
50
350
Max
5
10
25
25
100
SO
50
70
±12
±l3.5
60
60
18
5
10
25
2S
60
57
±10
±10
SO
50
20
SOO
3S0
100
300
8
10
ADLHOO32CG
Min
Typ
Max
20
2S
15
20
50
5
200
15
50
Units
mV
pA
nA
pA
nA
IJ.Vt"C
70
dB
±12
±13
60
60
20
dB
V
V
dB
dB
rnA
22
SOO
VI)1s
100
ns
300
8
10
20
2S
ns
ns
ns
hours
Applying the ADLH0032G/ADLH0032CG
POWER SUPPLY DECOUPLING
The ADLH0032G/ADLH0032CG,like most high-speed circuits, are sensitive to stray capacitances and layout. Power supplies should be bypassed as near to ±V (Pins 10 and 12) as
possible, using low inductance capacitors such as O.01J.!F disc
ceramics. Components for compensation should also be
located close to the appropriate pins to reduce stray capacitances. A large ground plane area for low-impedance ground
paths is highly recommended.
HEAT SINKING
The ADLH0032G/ADLH0032CG are specified for operation
without any heat sink. Since internal power dissipation does
create a significant temperature rise, improved bias current
performance can be achieved by using a small heat sink such
as the Thermalloy 2241 or equivalent. Since the case of the
ADLH0032G/ADLH0032CG has no internal connection, it
may be electrically connected to the heat sink. This, however,
will affect the stray capacitances to all pins, therefore requiring
adjustment of all circuit compensation values.
INPUT CAPACITANCE
Inverting Input:
For optimum performance, the inverting input should be
compensated by a small capacitance, around 10pF, across the
feedback resistor. This is because the 5pF input capacitance
may cause significant time constants with high-value resistors.
The capacitor value may be changed somewhat depending on
the effects of layout and closed loop gain.
Noninverting Input:
To divert leakage currents away from the non inverting input
and to reduce the effective input capacitance, it is desirable
to bootstrap the case and/or a guard conductor to the inverting input. The resulting input capacitance of a unity gain
follower configured this way will be less than 1 picofarad.
V+
2k
INPUT
o-.JoiIlV---"t
>-,,11'-lkHz
1000
1500
100
2
2.9
1.2
<0.1
1000
5
1400
100
2
3.2
1.5
<0.1
5
Vips
MHz
Degrees
ns
ns
%
MTBF
hours
Meantime Between Failure 1.962XIO'
PACKAGE OPTION 3
TO-S (H-12A)
ADLHOO33G
NOTES
1 Unless otherwise speCified, these speCifications apply for +15V apphed to pins 1 and 12, -15V
applied [0 pins 9 and 10, and pin 6 connected to pin 7.
2 Unless otherwise noted, specifications apply over a temperature range, -S5°C"'TC~+125°C
for the ADLHOO33G, and -25°C-
~
"
a o.
:/
'>-~"
0:
i'..
""" "''""
75
60
,
1!
CASE
'00
TEMPERATURE _
,
'26
./
v-
,
,.;:
./
w
j 4.0
~
:-~
--,...-
~
z
."a:'"
Vs = ±5V
/' ./
t,
w
2.0
/'
,
0
25
'50
50
75
TEMPERATURE _
°c
Power Dissipation vs Temperature
/'
./ / '
6.0
2
",/
~ 0.0 1
0.00
/'
/'
I
l,ov:x .L/
/'
±l6V .........
--: RS" 5O.U
RL = lkn
100
50
TEMPERATURE _
125
ac
Input Bias Current vs Temperature
150
100
ac
Rise and Fall Time vs Temperature
80
2' ,---,----,----::::;or---::...
'8
i':
"
w
12
g
10
"~
>-
~
8
,
Vs = ±15:0V
Rs= l00kn
/'"
AL '" lkfl
16
As'" 100kn
Tc =+25"C
/"
V
/'
/
........
>
~ 6.0
,
~
w
~
~ 4.0
/
i"--~
i'--- r--
~
o
>~
~ 20
:::>
0
"
,7~10:---...L---,:'::5----'-----!.ZO
'0
SUPPLY VOLTAGE - ±V
Supply Current vs Supply Voltage
12
-
f--
VS" ;'5V
I
r
i!:
~
4
:::>
~
'NPU~
;-
>-
2
,,
,
,
I
If
g
:::>
t
__
-OUTPUT
,'/
j-
-
10
20
30
40
60
TIME -ns
Positive Pulse Response
2-222 OPERA TlONALAMPLIFIERS
,NPUTr--0UTPUT
.....
\\
J'
Rs" 50n
RL "lkn
,
Ii,
Ii,
Output Offset Voltage vs Temperature
--
-
':
,II,
....
Vs = ±15V
-RS"5O.U
AL = lkn
i - - - VIN =
J
36
t.ov rms
-
30
AV
10
,
,
... !
0.8
06
I
0.'
fo
o.2
-1 2
60
40
I
Tc =+25°C
160
100
50
-50
TEMPERATURE _ aC
~
,
,
, '0 I,'
I
~ 8
!:;
I
Vs=±15V
~.
Tc = +2S"C
w
o
20
Output Voltage vs Supply Voltage
Rl = 1kO, As ""son
r- -,
>
15
SUPPLY VOLTAGE - ±V
25
...
"
20
20
30
TIME -AS
40
Negative Pulse Response
50
60
1.0
2.0
••0
100
ZO.O
FREOUENCY - MHz
50
,
Frequency Response
100
~
,
5f
1
,/
10
.~
Ultralow Offset
Voltage Op Amp
~ANALOG
WDEVICES
AD OP-07 I
FEATURES
Ten Times More Gain than Other OP-07 Devices
(3.0M min)
Ultralow Offset Voltage: 10j.lV
Ultralow Offset Voltage Drift: O.2j.lV/OC
Ultrastable vs. Time: O.2j.lVrC
Ultra low Noise: O.35j.lV p-p
No External Components Required
Monolithic Construction
High Common-Mode Input Range: ± 14.0V
Wide Power Supply Voltage Range: ±3V to ± 18V
Fits 725. 108A1308A Sockets
Military Parts and Plus Parts Available
8-Pin Plastic Mini-DIP. Cerdip. Small Outline or
TO-99 Hermetic Metal Can
Available in Wafer-Trimmed Chip Form
AD OP-O' CONNECTION DIAGRAMS
TO-99 (H) Package
Plastic Mini-DIP (N) Package
and
Cerdip (Q) Package
NUll
Ne
The AD OP-07 is available in five performance grades. The AD
OP-07E, AD OP-07C and AD OP-07D are specified for operation over the 0 to +70oC temperature range, while the AD
OP-07A and AD OP-07 are specified for -SSoC to +12SoC
operation. All devices are available in either the TO-99
hermetically sealed metal cans or the hermetically sealed
cerdip packages, while the industrail grades are also available
in plastic 8-pin mini-DiPs and small outline packages.
NULL
= NO CONNECT
TOP VIEW
Small Outline (R) Package
OFFSE80FFSET
1
-IN
A true differential operational amplifier, the AD OP-07 has a
high common-mode input voltage range (±13V, min) commonmode rejection ratio (typically up to 126dB) and high differential input impedance (50MQ typ); these features combine to
assure high accuracy in non inverting configurations. Such
applications include instrumentation amplifiers, where the
increased open-loop gain maintains high linearity at high
closed-loop gains.
8
1
-v,
Ne = NO CONNECT
TOP VIEW
NUll
PRODUCT DESCRIPTION
The AD OP-07 is an improved version of the industry-standard
OP-07 precision operational amplifier. A guaranteed minimum
open-loop voltage gain of 3,000,000 (AD OP-07A) represents
an order of magnitude improvement over older designs; this
affords increased accuracy in high closed-loop gain applications. Typical input offset voltages as low as lOJlV, typical
bias currents of 0.7nA, internal compensation and device protection eliminate the need for external components and
adjustments. An input offset voltage temperature coefficient
of 0.2JlV/C (typ) and long-term stability of 0.2JlV/month
(typ) eliminate recalibration or loss of initial accuracy.
OFFSET
OFFSET
4
NULL
+Vs
+
+IN
- Vs
8
-
OUTPUT
5
NC
NC = NO CONNECT
TOP VIEW
PRODUCT HIGHLIGHTS
1. Increased open-loop voltage gain (3.0 million, min) results
in better accuracy and linearity in high closed-loop gain
applications.
2. Ultralow offset voltage and offset voltage drift, combined
with low input bias currents, allow the AD OP-07 to maintain high accuracy over the entire operating temperature
range.
3. Internal frequency compensation, ultralow input offset
voltage and full device protection eliminate the need for
additional components. This reduces circuit size and complexity and increases reliability.
4. High input impedances, large common mode input voltage
range and high common mode rejection ratio make the
AD OP-07 ideal for noninverting and differential instrumentation applications.
S. Monolithic construction along with advanced circuit design
and processing techniques result in low cost.
6. The input offset voltage is trimmed at the wafer stage. Unmounted chips are available for hybrid circuit applications.
OPERA TIONAL AMPLIFIERS 2-223
SPECIFICATIONS
(TA= +25"1:, Vs= ±15V, unless otherwise specified)
Model
AD OP·07E
Parameter
Symbol
Min
Typ
OPEN LOOP GAIN
Avo
2,000
1,800
300
OUTPUT CHARACTERISTICS
Maximum Output Swing
YOM
±12.S
±12.0
±10.5
± 12.0
Min
Typ
4,000
4,000
1,000
1,200
1,000
300
4,000
4,000
1,000
± 13.0
± 12.8
± 12.0
± 12.6
60
±12.0
±1l.5
± 13.0
± 12.8
±II.O
± 12.6
60
Typ
5,000
4,500
1,000
1,200
1,000
300
±12.0
±ll.S
Ro
± 13.0
± 12.8
± 12.0
± 12.6
60
FREQUENCY RESPONSE
Closed Loop BandwIdth
Slew Rate
BW
SR
0.6
0.17
INPUT OFFSET VOLTAGE
Imttal
VO~
30
45
±4
TCV",
TCV"'N
Vo,/Time
0.3
0.3
0.3
1.3
10:-'
Open-Loop Output Resistance
Adjustment Range
Average Dnft
No External Tnm
With External Trim
Long Term StabIlity
INPUT OFFSET CURRENT
Imttal
Average Dnfl
INPUT BIAS CURRENT
Imtial
Average Drift
TCI",
1M
TCIn
INPUT RESISTANCE
Differenttal
Common Mode
RIN
R INCM
INPUT NOISE
Voltage
Voltage Density
enp-p
en
Current
Current Density
inP-p
in
15
AD OP·07D
AD OP·07C
Min
Max
±II.O
Max
0.6
0.17
0.6
0.17
75
130
60
85
±4
150
250
60
85
±4
150
250
1.3
1.5
0.5
0.4
0.4
1.8
1.6
2.0
0.7
0.7
0.5
2.5
2.5
3.0
0.5
0.9
8
3.8
5.3
3S
0.8
1.6
12
6.0
8.0
50
0.8
1.6
12
6.0
8.0
50
± 1.2
± 1.5
13
±4.0
± 5.5
35
± 1.8
±2.2
18
±7.0
±9.0
50
±2.0
±3.0
18
±12
± 14
50
50
160
0.35
10.3
10.0
9.6
14
0.32
0.14
0.12
8
0.38
10.5
10.2
9.8
15
0.35
0.15
0.13
0.6
18.0
13.0
11.0
30
0.80
0.23
0.17
7
33
120
31
120
0.38
10.5
10.2
9.8
15
0.35
0.15
0.13
0.65
20.0
13.5
11.5
35
0.90
0.27
0.18
INPUT VOLTAGE RANGE
Common Mode
CMVR
±13.0
± 13.0
± 14.0
± 13.5
±13.0
± 13.0
± 14.0
± 13.5
±13.0
± 13.0
±14.0
± 13.5
Common-Mode Rejection
Ratio
CMRR
106
103
123
123
100
97
120
120
94
94
110
106
PSRR
94
90
3.0
90
6.0
107
104
90
86
3.5
105
6.0
104
100
90
86
3.5
105
6.0
104
100
T man , Tmax
0
POWER SUPPLY
Current, Quiescent
Power Consumption
ReJection Ratio
OPERATING TEMPERATURE
RANGE
IQ
PI)
PACKAGEOPTIONS 3
Small Outline (R-8)
Plastic Mini-DIP (N-8)
Cerdip(Q-8)
TO-99 (H-OSA)
4.0
120
9.0
+70
ADOP-07EN
ADOP-07EQ
ADOP-07EH
0
5.0
150
9.0
+70
0
ADOP-07CR
ADOP-07CN
ADOP-07CQ
ADOP-07CH
NOTES
lInput Offset Voltage measurements are performed by automated test eqUipment approximately O.S seconds after application of
power AddmonaJly, the AD OP-07 A offset voltage IS guaranteed fully warmed up.
lLong-Term Input Offset Voltage Stablhty refers to the averaged trend hne of Vos vs. Time over extended periods of time
and IS extrapolated from high temperature test data. Excludmg the Initial hour of operation, changes m Vos during the first
30 operatmg days are tYPically 2.S/-l V - Parameter IS not 100% tested. 90% of umts meet this specificatIon.
3See Section 16 for package outhne Information.
2-224 OPERA TlONALAMPLlFIERS
Max
0.65
20.0
13.5
11.5
35
0.90
0.27
0.18
5.0
150
9.0
+70
ADOP-07DN
ADOP-07DQ
ADOP-07DH
AD OP-07
AD OP-07A
Min
Typ
Test Conditions
Units
5,000
4,000
1,000
2,000
1,500
300
5,000
4,000
1,000
R L;;'2ko., Vo= ±IOV
RL;;.2k!1, Vo= ± IOV, T=ntoT~x
RL= SOO~, Vo= ±0.5V, Vs= ±3V
V/mV
V/mV
V/mV
± 13.0
± 12.8
± 12.0
±12.6
60
±12.5
±12.0
±10.5
±12.0
± 13.0
± 12.8
± 12.0
±12.6
60
R L;;.lOko.
R L;;.2ko.
R L;;.lko.
RL~2k1l) T mm to T max
Vo=O,Io=O
V
V
V
V
0.
0.6
0.17
AVCL = + 1.0
R L;;.2k
MHz
VI",s
Note 1
R p =20ko.
",V
",V
mV
Tnunto Tmax
",vrc
R p =20ko., Tmm toT~x
Note 2
",VI"C
",VIMonth
Tnun toT max
TmmtoTmax
nA
nA
pAI"C
TmmtoTmax
TmmtoTmax
nA
nA
pArc
Min
Typ
3,000
2,000
300
±12.5
±12.0
±10.5
±12.0
Max
0.6
0.17
30
10
25
±4
25
60'
0:2
0.2
0.2
Max
30
60
±4
75
200'
0.6
0.6
1.0
0.3
0.3
0.2
1.3
1.3
0.3
0.8
5
2.0
4.0
25
0.4
8
2.8
5.6
50
±0.7
± 1.0
8
±2.0
±4.0
25
± 1.0
±2.0
13
±3.0
±6.0
50
20
80
200
0.35
10.3
10.0
9.6
14
0.32
0.14
0.12
1.2
0.6
18.0
13.0
11.0
30
0.80
0.23
0.17
1.0
TmmtoTmax
Mo.
Go.
60
200
0.35
10.3
10.0
9.6
14
0.32
0.14
0.12
0.6
18.0
13.0
11.0
30
0.80
0.23
0.17
"'V~
O.IHz to 10Hz
fo= 10Hz
fo= 100Hz
fo= 1kHz
O.IHzto 10Hz
fo= 10Hz
fo= 100Hz
fo ='lkHz
nVI Hz
nV/vHZ
nV/vHZ
pA;JHz
pAl Hz
pAlvHZ
pA/vHZ
±13.0
±13.0
±14.0
± 13.5
±13.0
±13.0
± 14.0
± 13.5
TmmtoTmax
V
V
llO
126
123
llO
106
106
126
123
VCM = ±CMVR
VCM = ±CMVR,TmmtoTmax
dB
dB
100
94
3,0
90
6.0
110
106
100
94
30
90
6.0
110
106
Vs=±15V
Vs=±15V
Vs= ±3V
Vs= ±3Vto ±18V
Vs= ±3Vto ± 18V, TmmtoTmax
rnA
mW
mW
dB
dB
- 55
4.0
120
8.4
+ 125
ADOP·07AQ
ADOP·07AH
4.0
120
8.4
+ 125
-55
"C
ADOP·07Q
ADOP·07H
SpeCificatIOns subJect to change without notice.
Specifications shown in boldface are tested on all production umts at final
electrical test. Results from those tests are used to calculate outgoing quality
levels. All min and max specifications are guaranteed, although only those
shown in boldface are tested on all production units.
OPERATIONAL AMPLIFIERS 2-225
ABSOLUTE MAXIMUM RATINGS
CHIP DIMENSIONS AND BONDING DIAGRAM
Supply Voltage . . . . . . . . . . .
· ±22V
Internal Power Dissipation (Note I)
500mW
Differential Input Voltage .. .
· ±30V
Input Voltage . . . . . . . . .
· . ±Vs
Output Short Circuit Duration
Indefinite
Storage Temperature Range .
- 65°C to + 150°C
Operating Temperature Range
AD OP-07A, AD OP-07 .
- 55°C to + 125°C
AD OP-07E, AD OP-07C, AD OP-07D
o to +70°C
Lead Temperature Range (Soldering 60sec) . . . . .. +300°C
NOTES
Note 1: Maximum package power dissipation vs. ambient temperature.
Maximum Ambient
Derate Above Maximum
Package Type
Temperature for Rating
Ambient Temperature
TO-99 (H)
80"C
7.1mWrC
36°C
Mini-DIP(N)
S.6mWI"C
Cerdip(Q)
WC
6.7mWrC
Dimensions shown in inches and (mm).
...
- - - - - - - - - 0 1 1 0 (2.70)
--------.;--1
NULL
\
+Vs
T
0059
1
NUll
-INPUT
THE AD OP-07 IS AVAILABLE IN WAFER-TRIMMED CHIP FORM FOR
PRECISION HYBRIDS CONSULT THE FACTORY FOR DETAILS
lOOkn
50n
r-~-oVo
Vos=~
ALL OTHER PINS
ARE NOT CONNECTED
-1BV
Offset Voltage Test Circuit
Burn·ln Circuit
AD OP-07 ORDERING GUIDE
Model
Package
Option
ADOP-07EH TO-99
ADOP-07EN Mini-DIP
ADOP-07EQ Cerdip
ADOP-07CH TO-99
ADOP-07CN Mini-DIP
ADOP-07CQ Cerdip
ADOP-07CR Small Outline
ADOP-07DH TO-99
ADOP-07DN Mini-DIP
ADOP-07DQ Cerdip
ADOP-07AH TO-99
ADOP-07AQ Cerdip
ADOP-07H
TO-99
ADOP-07Q
Cerdip
2-226 OPERATIONALAMPLIFIERS
Temperature Max Initial Max Offset
Range("C)
Offset (fl.V) Drift (fl.VfOC)
Oto + 70
Oto + 70
Oto + 70
Oto + 70
Oto + 70
Oto +70
Oto + 70
Oto + 70
Oto + 70
Oto + 70
-55to + 125
-55to+125
-55to+125
- 55 to + 125
75
75
75
150
150
150
150
150
150
150
25
25
75
75
1.3
1.3
1.3
1.8
1.8
1.8
1.8
2.5
2.5
2.5
0.6
0.6
1.3
1.3
Applying the AD OP-07
The AD OP-07 may be directly substituted for other OP-07's
as well as 725, 108/208/308, 108A/208A/308A, 714, OP-OS
or LMll devices, with or without removal of external frequency compensation or offset nulling components. If used to
replace 741 devices, offset nulling components must be re-
moved (or referenced to +Vs). Input offset voltage of the AD
OP-07 is very low, but if additional nulling is required, the circuit shown in Figure 1 is recommended.
The AD OP-07 provides stable operation with load capacitances up to SOOpF and ±10V swings; larger capacitances
should be decoupled with son resistor.
Stray thermoelectric voltages generated by dissimilar metals
(thermocouples) at the contacts to the input terminals can prevent realization of the drift performance indicated. Best operation will be obtained when both input contacts are maintained
at the same temperature, preferably close to the temperature
of the device's package.
Figure 1. Optional Offset Nulling Circuit and
Power Supply Bypassing
Performance Curves
Although the AD OP-07 features high power supply rejection,
the effects of noise on the power supplies may be minimized
by bypassing the power su pplies as close to pins 4 and 7 of the
AD OP-07 as possible, to load ground with a good-quality
O.OlI.1F ceramic capacitor as shown in Figure 1.
(typical @TA = +25°C, Vs = ±15V, AD OP·07 Grade Device unless otherwise noted)
vour. 5V!DIV
AD OP-07 Low Frequency Noise (See Test Circuit,
on the Previous Page)
AD OP'()7 Open Loop Gain Curve
140
6000
4000
120
V
.~
2000
I""- l'..
~
100
"j'\,
80
1\
"[".,.
60
I'\,
40
'\
0
0
'\
0
-50
+100
'50
TEMPERATURE _
°c
"\
+150
-20
-40
001
Open Loop Gain vs. Temperature
01
10
10
100
lk
10k
lOOk
1M
10M
FREQUENCY - Hz
Open Loop Frequency Response
OPERA TlONAL AMPLIFIERS 2-227
Typical Performance ClIves
28
100
i-r
80
........
"-
0
~
•
l"\
2
•
•
I0
')..
-20
10
100
1k
10k
lOOk
1M
1\
0
10M
10
fREQUENCY - Hz
1000
100
FREQUENCY - kHz
Closed Loop Response for Various Gain Configurations
Maximum Undistorted Output vs. Frequency
0
0
•
•
·
2
V-
0
0
2
\
.............
L
8
~
-1 0
o1
0.1
10
10
2346618910
100
HOURS (HUNDREDS)
126°C. t15V
BANDWIDTH - kHz
Input Wideband Noise VB. Bandwidth (0. 1kHz to Frequency
Indicated)
Offset Voltage VB. Time
120
11 0
110 H+l+IllH-+++HlI!f->\I-+t1IttH1-+l~lII-Ht-Hlltl
~100H~~++~~+R~+++HlI~Ht~
.
~ ooH~~++~~+l+IllH-~+HlI~Ht~
100
..,
f
~
1\
90
80
r\
70
60
.
01
FREQUENCY - Hz
1\
0
1
100
1k
10k
FREQUENCV - Hz
CMRR vs. Frequency
PSR R vs. Frequency
1000
.....
/
/
L
.
20
01
80
10
LOAD RESISTOR TO GROUND - kf!
100
TOTAL SUPPLY VOLTAGE, V+ TO V- - Volts
Power Consumption
VB.
Power Supply
2-228 OPERATIONAL AMPLIFIERS
Output Voltage vs. Load Resistance
Ultralow-Noise
Precision Op Amp
AD OP-27 I
IIIIIIIIIII ANALOG
WDEVICES
FEATURES
Ultralow Noise: 80nV pop (O.1Hz to 10Hz),
3nV/v'Hi at 1kHz
Ultralow Offset Voltage Drift: O.2,...V/oC
High Offset Stability Over Time: O.2,...Vlmonth
High Slew Rate: 2.8V/,...s
High Gain Bandwidth Product: 8MHz
Low Offset Voltage: 10,...V
High CMRR: 126dB Over ± 11V Input Voltage Range
Fits OP-07, OP-05, OP-06, 5534, 725, 714 and
741 Sockets
Military Grade and Plus Parts Available
8-Pin Plastic Mini-DIP, Cerdip or TO-99 Hermetic
Metal Can
Available in Wafer-Trimmed Chip Form
PRODUCT DESCRIPTION
The AD OP-27 offers the combined features of high precision,
ultralow noise and high speed in a monolithic bipolar operational
amplifier. State-of-the-art performance for high accuracy amplification of very low level signals, where inherent device noise
can be the limiting factor, is attainable with the AD OP-27. As
a device directly compatible with other low noise op amps, the
AD OP-27 features industry standard dc performance; typical
input offset voltages of lOfL V and typical input offset voltage
temperature coefficients of O.2fL vrc. The super low input voltage
noise performance of the AD OP-27 is characterized by an en
POp (typ) of 80nV (O.IHz to 10Hz), an en (typ) of 3.0nV/YHz
(at 1kHz) and a l/f noise corner frequency of 2.7Hz. AC specifications induding a 2.8V/fLS (typ) slew rate and an 8MHz (typ)
gain bandwidth product are possible without sacrificing dc accuracy. Long-term stability is assured by an input offset voltage
drift specification of O.2fL V/month.
Source resistance related errors with the AD OP-27 are minimized
by a low input bias current at ambient of ± lOnA (typ) and an
input offset current of 7nA (typ). An input bias current cancellation
circuit limits bias and offset currents over the extented temperature
range to ±20nA (typ) and ISnA (typ), respectively. Other factors
inducing input referred errors such as power supply variations
and common-mode voltages are attenuated by a PSRR and
CMRR of at least l20dB.
AD OP-27 CONNECTION DIAGRAMS
Plastic Mini-DIP (N) Package
and
Cerdip (Q) Package
TO-99
(H) Package
OFFSET NULL
OFFSET NULL
INVE~,J~~~ 2
INVERTING 2
INPUT
8
1
OFFSET NULL
-
NONINVERTING
INPUT
v-
TOP VIEW
TOP VIEW
NOTE PIN 4 CONNECTED TO CASE
PRODUCT HIGHLIGHTS
I. Precision amplification of very low level, low frequency voltage
inputs is enhanced by ultralow input voltage noise.
2. The AD OP-27 maintains high dc accuracy over an extended
temperature range due to ultra-low offset voltage, offset
voltage drift and input bias current.
3. Internal frequency compensation, factory adjusted offset
voltage and full device protection eliminate the need for
additional components. Circuit size and complexity are reduced
while reliability is increased.
4. Long-term stability and accuracy is assured with low offset
voltage drift over time.
S. Input referred errors are greatly reduced by superior common
mode and power supply rejection characteristics.
6. Monolithic construction along with advanced circuit design
and processing techniques result in low cost.
The AD OP-27 is available in six performance grades. The AD
OP-27E, AD OP-27F and AD OP-27G are specified for operation
over the - 2SoC to + 8YC temperature range, while the AD
OP-27A, AD OP-27B and AD OP-27C are specified for - SsoC
to + 12SoC operation. All devices are available in either the
TO-99 hermetically sealed metal cans or the hermetically sealed
cerdip packages, while the E, F and G grades are also available
in plastic mini-DIPs.
OPERA TfONALAMPLIFIERS 2-229
•
SPECIFICATIONS
CTA= +25OC, Vs= ±15V, unless oIIterwise specified)
Parameter
Symbol
Min
Typ
OPEN LOOP GAIN
Ava
700
400
200
450
OUTPUT CHARACTERISTICS
Voltage Swing
Va
Open-Loop Output Resistance
Ra
FREQUENCY RESPONSE
Gain Bandwidth Product
Slew Rate
GBW
SR
INPUT OFFSET VOLTAGE
Initial
Vas
Average Drift
Long Term Stability
Adjustment Range
AD OP-27F
AD OP-27G
Model
AD OP-27E
Min
Typ
1,800
1,500
700
1,300
1,000
BOO
250
750
1,800
1,500
700
1,500
±12.0
±10.0
±11.4
± 13.8
±1l.5
± 13.5
70
±12.0
±10.0
± 11.7
± 13.8
± 1l.5
± 13.6
70
5.0
1.7
8.0
2.8
5.0
1.7
8.0
2.8
Min
Typ
1,500
1,500
500
1,000
1,000
BOO
250
700
±1l.5
±10.0
±II.O
± 13.5
± 11.5
±13.3
70
5.0
1.7
8.0
2.8
TCVos
Vas/Time
Max
Max
Max
30
55
0.4
0.4
±4.0
100
220
1.8
2.0
20
40
0.3
0.3
±4.0
60
140
1.3
1.5
10
20
0.2
0.2
±4.0
25
60
0.6
1.0
INPUT BIAS CURRENT
Initial
IB
± IS
±25
±BO
±150
±12
±18
±55
±95
±IO
±14
±40
±60
INPUT OFFSET CURRENT
Initial
las
12
20
75
135
9
14
50
85
7
10
35
50
INPUT NOISE
Voltage
Voltage Density
enp-p
en
0.09
3.8
3.3
3.2
1.7
1.0
0.4
0.25
8.0
5.6
4.5
0.08
3.5
3.1
3.0
1.7
1.0
0.4
0.18
5.5
4.5
3.8
4.0
2.3
0.6
0.08
3.5
3.1
3.0
1.7
1.0
0.4
0.18
5.5
4.5
3.8
4.0
2.3
0.6
Current Density
in
0.6
INPUT VOLTAGE RANGE
Common Mode
CMVR
±11.0
± 10.5
± 12.3
± 1l.8
±11.0
± 10.5
± 12.3
± 11.8
±1l.0
± 10.5
± 12.3
± 1l.8
Common-Mode Rejection
Ratio
CMRR
100
96
120
118
106
102
123
121
114
110
126
124
RIN
R1NCM
0.8
4
2
1.2
5
2.5
1.5
6
3
INPUT RESISTANCE
Differential
Common Mode
POWER SUPPLY
Rated Performance
Operating
Current, Quiescent
Rejection
Power Consumption
± IS
±(4-18)
3.3
2
2
100
IQ
PSR
I'd
OPERATING TEMPERATURE RANGE
T m,m Tmax
PACKAGE OPTIONS 3
Plastic Mini-DIP (N -8)
Cerdip(Q-8)
TO-99 (H-08A)
-25
5.6
20
32
170
+85
ADOP-27GN
ADOI'-27GQ
ADOI'-27GH
± IS
± (4-18)
3.0
I
2
90
-25
4.6
10
16
140
+85
ADOI'-27FN
ADOI'-27FQ
ADOI'-27FH
± IS
±(4-18)
3.0
I
2
90
-25
+85
ADOP-27EN
ADOI'-27FQ
ADOI'-27EH
NOTES
JInput Offset Voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of
power J A and E grades are guaranteed fully warmed up.
2Long_ Term Input Offset Voltage Stability refers to the average trend line of Vas vs. time after the first 30 days.
3S ee Section 16 for package outline information.
Specifications subject to change wIthout notice.
2-230 OPERA TlONAL AMPLIFIERS
4.6
10
IS
140
AD OP-27C
Min
Typ
700
400
200
300
AD OP-27A
AD OP-27B
Min
Typ
1,800
1,500
700
1,000
1,000
800
250
600
1,800
1,500
700
1,200
±12.0
±10.0
±11.0
::': 13.8
::': 11.5
::': 13.2
70
±12.0
±10.0
±11.5
::': 13.8
::': 1l.5
::': 13.5
70
5.0
1.7
8.0
2.8
5.0
1.7
8.0
2.8
Min
Typ
1,500
1,500
500
800
1,000
SOO
250
500
±11.5
±10.0
±10.5
::': 13.5
::': 11.5
::': 13.0
70
5.0
1.7
8.0
2.8
Max
Max
Conditions
Units
RL~2kO,
VOUT - ::': lOV
VOUT=::': lOV
RL = 6000, VOUT=::': IV, Vs= ::':4V
R L 32k!l, VOUT= ± lOY, Ta=mintomax
V/mV
V/mV
V/mV
V/mV
RL~2kO
RL~2kO,T,=min to max
IouT=OA, VOUT=OV
V
V
V
0
RL~2kO
V/fLS
(Note 1)
Ta=min to max
Ta=mm to max
(Note2)
Rp= lOkO
fLY
fLY
fLV/month
mV
Max
RL~lkO,
RL~6000
MHz
30
70
0.4
0.4
::,:4.0
100
300
1.8
2.0
20
50
0.3
0.3
::,:4.0
60
200
1.3
1.5
10
30
0.2
0.2
::,:4.0
25
60
0.6
1.0
::': 15
::': 35
±SO
±150
::': 12
::,:28
± 55
± 95
::': 10
::,:20
±40
±60
Ta= min to max
nA
nA
12
30
75
135
9
22
50
S5
7
15
35
50
Ta = min to max
nA
nA
0.09
3.8
3.3
3.2
1.7
1.0
0.4
0.25
8.0
5.6
4.5
0.08
3.5
3.1
3.0
1.7
1.0
0.4
0.18
5.5
4.5
3.8
4.0
2.3
0.6
0.08
3.5
3.1
3.0
1.7
1.0
0.4
0.18
5.5
4.5
3.8
4.0
2.3
0.6
O.IHz to 10Hz
fo= 10Hz
fo= 30Hz
fo= 1000Hz
fo= 10Hz
fo=30Hz
fo= 1000Hz
nVI Hz
nV/vHz
nV/vHz
pA/vHz
pA/vHz
pA/vHz
fLV/oC
-
-
0.6
fLV~
:±:11.0
::': 10.2
::': 12.3
::': 11.5
:±:11.0
::': 10.3
::': 12.3
::': 11.5
:±:11.0
::': 10.3
::': 12.3
::': 11.5
Ta =min to max
V
V
100
94
120
116
106
100
123
119
114
108
126
122
VCM=::':l1V
VCM = ::': lOV, T, = min lomax
dB
dB
0.8
4
2
1.2
5
2.5
1.5
6
3
MO
GO
::': 15
::':(4--18)
3.0
1
2
90
V
V
rnA
fL VIV
fL VIV
mW
::': 15
::': (4--18)
3.3
2
4
100
5.6
20
51
170
+ 125
-55
ADOP-27CQ
ADOP-27CH
::': 15
::': (4--18)
3.0
4.6
I
10
2
20
90
140
+ 125
-55
ADOP-27BQ
ADOP-27BH
4.6
10
16
140
+ 125
-55
Vs=::': 15V
Vs= ::,:4Vto::': 18V
Vs= ::':4.5Vto::': 18V, T, = min lOmax
VOUT=OV
°C
ADOP-27AQ
ADOP-27AH
Specifications shown in boldface are tested on all production units at final
electrical test. Results from those tests are used to calculate outgoing quality
levels. All min and max specifications are guaranteed, although only those
shown in boldface are tested on all production units.
OPERA T10NAL AMPLIFIERS 2-231
•
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . .
Internal Power Dissipation (Note 1)
Input Voltage . . . . . . . . . . .
Output Short Circuit Duration
Differential Input Voltage (Note 2)
. ±18V
500mW
. . ±Vs
Indefinite
.. ±O.7V
Differential Input Current (Note 2)
Storage Temperature Range
Operating Temperature Range
AD OP-27A, AD OP-27B, AD OP-27C
AD OP-27E, AD OP-27F, AD OP-27G
Lead Temperature Range (Soldering 60sec)
. . . . . ±2SmA
- 65°C to + 150°C
- 55°C to + 125°C
- 25°C to + 85°C
. . . . .. 300°C
NOTES:
Note 1: Maximum package power dissipatIOn vs. ambient temperature.
Maximum Ambient
Derate Above Maximum
Package Type
Temperature for Rating
Ambient Temperature
TO-99 (H)
80°C
7.lmW/oC
Mini-DIP(N)
36°C
5.6mWrC
Cerdlp(Q)
75°C
6.7mWrC
Note 2: The AD OP-27's inputs are protected by back-to-back diodes. To achieve low noise current hmiting resistors could
not be used. If the differential input voltage exceeds ± O. 7V, the input current should be limIted to 25mA.
CHIP DIMENSIONS AND BONDING DIAGRAM
AD OP-27 ORDERING GUIDE
Dimensions shown in inches and (mm).
I
T
0057
(145)
1
NULL
3
I
+ INPUT
THE AD OP-27 IS AVAILABLE IN WAFER-TRIMMED CHIP FORM
CONSULT THE FACTORY FOR DETAILS
Model
Option*
Temperature
Range(°C)
Max Initial
Offset (,.V)
Max Offset
Drift (,.VI"C)
ADOP-27GH
ADOP-27GN
ADOP-27GQ
ADOP-27FH
ADOP-27FN
ADOP-27FQ
ADOP-27EH
ADOP-27EN
ADOP-27EQ
TO-99
Mini-DIP
Cerdip
TO-99
Mmi-DIP
Cerdlp
TO-99
MinI-DIP
Cerdip
-2510+85
-2510 +85
-2510+85
-25'0+85
-2510 +85
-25'0+85
-25'0+85
-25'0+85
-2510 +85
100
100
100
60
60
60
25
25
25
1.8
1.8
1.8
1.3
1.3
1.3
0.6
0.6
0.6
ADOP-27CH
ADOP-27CQ
ADOP-27BH
ADOP-27BQ
ADOP-27AH
ADOP-27AQ
TO-99
Cerdip
TO-99
Cerdip
TO-99
Cerdip
-5510+125
- 55 10 + 125
-5510 + 125
-5510 + 125
- 55 10 + 125
-5510+125
100
100
60
60
25
25
1.8
1.8
1.3
1.3
0.6
0.6
Package
·See Section 16 for package outlIne informatlon_
2-232 OPERA TlONAL AMPLIFIERS
APPLICATION NOTES FOR THE AD OP-27
The AD OP-27 can be used in the sockets of many of the popular
precision bipolar input operational amplifiers on the market.
Elimination of external frequency compensation or nulling circuitry may be possible in many cases. In 741 replacement situations, if nulling has been implemented, it should be modified or
removed for optimum AD OP-27 performance.
In applications where the initial factory adjusted input offset
voltage provides insufficient accuracy, further offset trimming
can be accomplished with the resistor network shown in Figure
1. The adjustment range attainable using a 101dl potentiometer
will be ± 4mV. If a smaller adjustment range is required, the
sensitivity of the nulling can be increased by using a smaller
potentiometer in series with fixed resistor(s). For example, a
IIdl pot in series with two 4.71dl resistors will yield a ± 280,...V
range.
-Vs
001"F
'::'
Figure 1. Optional Offset Nulling Circuit and Power Supply
Bypassing
.
Zeroing the initial offset with potentiometers other than 101dl,
but between lItO and 1Mfl, will introduce an additional input
offset voltage temperature drift error of from 0.1 to 0.2,...Vrc.
Additionally, by intentionally trimming in a dc level shift a
voltage dependent offset drift will be created. It will be approximately the input offset voltage at 2SOC divided by 300 (in ,...VI
OC).
Parasitic thermocouple EMFs can be generated where dissimilar
metals meet the contacts to the input terminals of the AD OP-27.
These temperature dependent voltsges can manifest themselves
as drift type errors. Optimized temperature performance will be
obtained when both contacts are maintained at the same temper-ature-a temperature close to the device's package.
Output stability with the AD OP-27 is possible with capacitive
loads of up to 2000pF and ± 10V output swings. Larger capacitances should be decoupled with a
resistor.
son
High closed loop gain and excellent linearity can be achieved by
operating the AD OP-27 within an output current range of
± 10mA. Minimizing output current will provide the highest
linearity.
+1SV
-1BV
AU OTHER PINS
ARE NOT
CONNECTED
SLEW RATE DISCUSSION
In unity gain buffer applications with feedback resistances of
less than 1000 where the input is driven with a fast, large (greater
than IV) pulse, the output waveform will appear as in Figure 3.
~
~
i~. .
~
+SUPPLY
10
,02
101
10"
i ' f-----lo+---+--t---i
;-4
-SUPPLY
~
,"
8-·.~---4----~~~=*-----1
~
'0'
107
10-
.
Power Supply Rejection Ratio
vs. Frequency
..
..
,~----~------~------~
FftEQUENCV - HE
TOTAL SUPPLY VOLTAGE- V
Supply Current vs. Supply Voltage
II
,,,
\
J.W
r\
r\
"
'GO
CMRR vs. Frequency
2-236 OPERA nONALAMPLIFIERS
"
SUPPLY VOLTAGE-
~v
"
Common-Mode Input Range vs.
Supply Voltage
r.ANALOG
WDEVICES
FEATURES
Ultralow Noise: 80nV pop (O.lHz to 10Hz),
3nV/YHz at 1kHz
High Speed: 17Vll1s
High Gain Bandwidth Product: 63MHz
Ultralow Offset Voltage Drift: 0.211VrC
High Offset Stability Over Time: 0.2l1V/month
Low Offset Voltage: lOI1V
High CMRR: 126dB Over ±llV Input Voltage Range
Fits OP-07, OP-05, OP-06, 5534, LH0044,
5130,3510,725,714 and 741 Sockets
in Gains 2: 5
Military Grade and Plus Parts Available
8-Pin Plastic Mini-DIP, Cerdip or TO-99 Hermetic
Metal Can
Available in Wafer-Trimmed Chip Form
PRODUCT DESCRIPTION
The AD OP-37 offers the combined features of high precision,
ultralow noise and high speed in a monolithic bipolar operational
amplifier. High-speed accurate amplification of very low level
signals, where inherent device noise can be the limiting factor,
is attainable with the AD OP-37 in applications requiring gains
greater than or equal to five. This instrumenation grade op amp
features industry standard dc performance; typical input offset
voltages of IOfLV and typical input offset voltage temperature
coefficients of 0.2fLvrc. The super low input voltage noise
performance of the AD OP-37 is characterized by an en Pop
(typ) of 80nV (0. 1Hz to 10Hz), an en (typ) of 3.0nV/v'HZ (at
1kHz) and a lIf noise corner frequency of 2.7Hz. High speed
performance is assured by a typical 17VI fLS slew rate and a
typical 63MHz gain bandwidth product. Long-term stability
is guaranteed by an input offset voltage drift specification of
0.2fLV/month.
Source resistance related input errors with the AD OP-37 are
minimized by a low input bias current of :!: 10nA (typ) and an
input offset current of7nA (typ). An input bias current cancellation
circuit restricts bias and offset currents over the extended temperature range to :!: 20nA (typ) and lSnA (typ), respectively.
Other factors inducing input referred errors such as power
supply variations and common-mode voltages are attenuated by
a PSRR and CMRR of l20dB.
Ultralow-Noise, High-Speed
Precision Op Amp (AYCL >5)
AD OP-37 I
AD OP-37 CONNECTION DIAGRAMS
TO-99
(H) Package
Plastic Mini-DIP (N) Package
and
Cerdip (Q) Package
OFFSET NULL
INVERTING
INPUT
NONINVERTING
INPUT
TOP VIEW
vNOTE PIN 4 CONNECTED TO CASE
TOP VIEW
PRODUCT HIGHLIGHTS
I. High speed accurate amplification (gains 2: 5) of very low
level low frequency voltage inputs is enhanced by a high gain
bandwidth product and ultralow input voltage noise.
2. The AD OP-37 maintains high dc accuracy over an extended
temperature range due to ultralow offset voltage, offset voltage
drift and input bias current.
3. Internal frequency compensation, factory adjusted offset
voltage and full device protection eliminate the need for
additional components. Circuit size and complexity are reduced
while reliability is increased.
4. Long-term stability and accuracy is assured with low offset
voltage drift over time.
5. Input referred errors are greatly reduced by superior commonmode and power supply rejection characteristics.
6. Monolithic construction along with advanced circuit design
and processing techniques result in low cost.
The AD OP-37 is available in six performance grades. The AD
OP-37E, AD OP-37F and AD OP-37G are specified for operation
over the - 25°C to + 85°C temperature range, while the AD
OP-37 A, AD OP-37B and AD OP-37C are specified for - 55°C
to + 125°C operation. All devices are available in either the
TO-99 hermetically sealed metal cans or the hermetically sealed
cerdip packages, while the industrial grades are also available in
plastic mini-DIPs.
OPERA TlONALAMPLlFIERS 2-237
•
SPECIFICATIONS
.
.
ITA- +2WC Vs- ±15V unless oIhenvise specified)
Model
Symbol
Min
Typ
OPEN LOOP GAIN
Avo
700
400
200
450
OUTPUT CHARACTERISTICS
Voltage Swing
Vo
Open· Loop Output Resistance
Ro
FREQUENCY RESPONSE
Gain Bandwidth Product
Slew Rate
INPUT OFFSET VOLTAGE
Initial
Average Drift
Long·Term Stability
Adjustment Range
AD OP·37F
AD OP·37G
Parameter
GBW
SR
Min
Typ
1,500
1,500
500
1,000
1,000
SOO
250
700
±ll.S
±10.0
±II.O
± 13.5
± ll.5
± 13.3
70
45
63
40
17
-
II
Vos
TCVos
Vos/Time
Max
AD OP·37E
Min
Typ
I,SOO
1,500
700
1,300
1,000
SOO
250
750
I,SOO
1,500
700
1,500
±12.0
±10.0
±11.4
± 13.8
± ll.5
± 13.5
70
±I2.0
±IO.O
±11.7
± 13.S
± 11.5
± 13.6
70
45
63
40
17
45
63
40
17
II
Max
-
II
Max
30
55
0.4
0.4
±4.0
100
220
1.8
2.0
20
40
0.3
0.3
±4.0
60
140
1.3
1.5
10
20
0.2
0.2
±4.0
25
60
0.6
1.0
INPUT BIAS CURRENT
Initial
Is
± 15
±25
±so
± 150
± 12
± IS
±S5
±95
±IO
± 14
±40
±60
INPUT OFFSET CURRENT
Initial
los
12
20
75
135
9
14
50
85
7
10
35
50
INPUT NOISE
Voltage
Voltage Density
enp·p
en
0.09
3.S
3.3
3.2
1.7
1.0
0.4
0.25
8.0
5.6
4.5
0.08
3.5
3.1
3.0
1.7
1.0
0.4
0.18
5.5
4.5
3.S
4.0
2.3
0.6
0.08
3.5
3.1
3.0
1.7
1.0
0.4
0.18
5.5
4.5
3.S
4.0
2.3
0.6
Current Density
INPUT VOLTAGE RANGE
Common Mode
Common· Mode Rejection
Ratio
INPUT RESISTANCE
Oifferential
Common Mode
POWER SUPPLY
Rated Performance
Operating
Current, Quiescent
Rejection
Power Consumption
in
CMVR
±: 1l.0
-
0.6
± 10.5
± 12.3
± ll.S
±1l.0
± 10.5
± 12.3
± ll.S
±1l.0
± 10.5
± 12.3
± II.S
CMRR
100
96
120
liS
106
102
123
121
114
llO
126
124
RIN
O.S
4
2
1.2
5
2.5
1.5
6
3
R 1NCM
± 15
±(4-18)
3.3
2
2
100
IQ
PSR
Pd
OPERATING TEMPERATURE RANGE
TmImTmax
PACKAGE OPTIONS 3
Plastic Mini· DIP (N·8)
Cerdip (Q·S)
TO·99 (H·08)
-25
± 15
±(4-18)
3.0
I
2
90
5.6
20
32
170
+S5
ADOp·37GN
ADOP·37GQ
ADOp·37GH
-25
± 15
±(4-IS)
3.0
4.6
I
10
2
15
90
140
4.6
10
16
140
+85
-25
ADOp·37FN
ADOP·37FQ
ADOp·37FH
NOTES
lInput Offset Voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of
power. A and E grades are guaranteed fully warmed up.
'Long-Term Input Offset Voltage Stability refers to the average trend line of Vos vs. time after the first 30 days.
3See Section 16 for package outline information.
Specifications subject to change without notice.
2-238 OPERA TIONALAMPLIFIERS
+S5
ADOp·37EN
ADOP·37EQ
ADOP·37EH
-
AD OP-37C
Min
Typ
700
400
200
300
±1l.5
±10.0
±10.5
45
II
Max
ADOP-37B
Min
Typ
1,500
1,500
500
800
1,000
800
250
500
± 13.5
± 1l.5
± 13.0
70
±12.0
±10.0
±1l.0
63
63
17
45
II
Max
Units
ADOP-37A
Min
Typ
1,800
1,500
700
1,000
1,000
800
250
600
1,800
1,500
700
1,200
RL;;.2kO, VOUT= ± 10V
RL ;;.lkO, VOUT= ± 10V
RL = 6000, VOUT= ±IV, Vs= ±4V
R L;;.2kO, VOUT= ± 10V, T.= min to max
V/mV
V/mV
V/mV
V/mV
± 13.8
± 1l.5
± 13.2
70
±12.0
±10.0
±11.5
± 13.8
±1l.5
± 13.5
70
R L;;.2kO
R L ;;.6000
R L ;;.2kO,T. = min to max
IouT=OA, VOUT=OV
V
V
V
0
63
40
17
fo= 10kHz
fo= IMHz
RL ;;.2kO
MHz
MHz
V/ILS
(Note I)
Ta=mintomax
Ta = min to max
(Note 2)
Rp= IOkO
ILV
ILV
ILVI"C
ILV/month
mV
63
40
17
45
II
Max
30
70
0.4
0.4
±4.0
100
300
1.8
2.0
20
50
0.3
0.3
±4.0
60
200
1.3
1.5
10
30
0.2
0.2
±4.0
25
60
0.6
1.0
± IS
±35
±80
±150
± 12
±28
± 55
±95
±IO
±20
±40
±6O
T. = min to max
nA
nA
12
30
75
135
9
22
50
85
7
IS
35
50
Ta = min to max
nA
nA
0.09
3.8
3.3
3.2
1.7
1.0
0.4
0.25
8.0
5.6
4.5
0.08
3.5
3.1
3.0
1.7
1.0
0.4
0.18
5.5
4.5
3.8
4.0
2.3
0.6
0.08
3.5
3.1
3.0
1.7
1.0
0.4
O.IS
5.5
4.5
3.8
4.0
2.3
0.6
O.IHz to 10Hz
fo= 10Hz
fo= 30Hz
fo= 1000Hz
fo= 10Hz
fo= 30Hz
fo= 1000Hz
ILV~.
nVI Hz
nWVHz
nV/vHZ
pAlvHZ
pAlYHz
pAlYHz
-
-
0.6
±1l.0
± 10.2
±12.3
± 1l.S
±1l.0
± 10.3
± 12.3
± 1l.S
±1l.0
± 10.3
± 12.3
± 1l.S
T.= min to max
V
V
100
94
120
116
106
100
123
119
114
108
126
122
VCM = ± llV
VCM = ± 10V, T. = min to max
dB
dB
0.8
4
2
1.2
5
2.5
1.S
6
3
MO
GO
±IS
±(4-18)
3.0
I
2
90
V
V
mA
ILVN
ILVN
mW
±IS
±(4-18)
3.3
2
4
100
-55
±IS
±(4-18)
3.0
4.6
I
10
20
2
90
140
5.6
20
51
170
+ 125
ADOP-37CQ
ADOP-37CH
-55
+ 125
-55
ADOP-37BQ
ADOP-37BH
4.6
10
16
140
Vs= ± ISV
Vs =±4Vto±18V
Vs= ± 4.5V to ± ISV, T. = min to max
VOUT=OV
+125
ADOP-37AQ
ADOP-37AH
°C
I
Specificauons shown In boldface are tested on all production units at final
electrical test. Results from those tests are used to calculate outgomg quality
level~. All min and max specifications are guaranteed) although only those
shown in boldface are tested on all production U011s.
OPERATIONALAMPLIFIERS 2-239
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . .
Internal Power Dissipation (Note I)
Input Voltage . . . . . . . . . . .
Output Short Circuit Duration . .
Differential Input Voltage (Note 2)
. ±18V
500mW
. . ±Vs
Indefinite
.. ±O.7V
Differential Input Current (Note 2)
Storage Temperature Range . . . .
Operating Temperature Range
AD OP-37A, AD OP-37B, AD OP-37C
AD OP-37E, AD OP-37F, AD OP-37G
Lead Temperature Range (Soldering 60sec)
. . . . . ±25mA
-65°C to + 150°C
- 55°C to + 125°C
- 25°C to + 85°C
. . . . . . 300°C
NOTES:
Note 1: Maximum package power dissipation vs. ambIent temperature.
Maximum Ambient
Derate Above Maximum
Package Type
Temperature for Rating
Ambient Temperature
TO-99 (H)
80°C
7.lmWI"C
Mini-DIP(N)
36°C
5.6mWI"C
Cerdip (Q)
75°C
6.7",WI"C
Note 2: The AD OP-37's Inputs are protected by back-to-back diodes. To achieve low noise current limitmg resistors could
not be used. If the differential input voltage exceeds ± O. 7V, the input current should be hmited to 25mA.
AD OP-37 ORDERING GUIDE
CHIP DIMENSIONS AND BONDING DIAGRAM
Model
Package"
Temperature
Range (OC)
Max Initial
Offset (,.V)
Max Offset
Drift (,.V/oC)
ADOP-37GH
ADOP-37GN
ADOP-37GQ
ADOP-37FH
ADOP-37FN
ADOP-37FQ
ADOP-37EH
ADOp·37EN
ADOP-37EQ
TO-99
Mml-DIP
Cerdip
TO-99
Mini-DIP
Cerdip
TO·99
Mini-DIP
Cerdip
-2510+85
~25 10 + 85
-2510+85
-2510 +85
- 25 10 + 85
-2510 +85
-2510 +85
-2510 +85
-2510+85
100
100
100
60
60
60
25
25
25
1.8
1.8
1.8
1.3
1.3
1.3
0.6
0.6
0.6
ADOP-37CH
ADOP-37CQ
ADOP-37BH
ADOP-37BQ
ADOP-37AH
ADOP-37AQ
TO·99
Cerdip
TO-99
Cerdip
TO-99
Cerdip
- 55 to + 125
-5510 +125
- 55 10 + 125
-5510 + 125
-5510 + 125
-5510+125
100
100
60
60
25
25,
1.8
1.8
1.3
1.3
06
0.6
DImenSIOns shown m inches and (mm).
1 - - - - - - - 0100(254) - - - - - - - 1
THE AD OP-37IS AVAILABLE IN WAFER·TRIMMED CHIP FORM CONSULT THE FACTORY FOR DETAILS
*See Secuon 16 for package outhne mformatlon
2-240 OPERA TlONALAMPLlFIERS
APPLICATION NOTES FOR THE AD OP-37
The AD OP-37 can be used in the sockets of many of the popular
precision bipolar input operational amplifiers on the market.
Elimination of external frequency comp.::nsation or nulling circuitry may be possible in many cases. In 741 replacement situations, if nulling has been implemented, it should be modified or
removed for correct AD OP-37 performance.
In applications where the initial factory adjusted input offset
voltage provides insufficient accuracy, further offset trimming
can be accomplished with the resistor network shown in Figure
1. The adjustment range attainable using a 10kO potentiometer
will be ±4mV. If a smaller adjustment range is required, the
sensitivity of the nulling can be increased by using a smaller
potentiometer in series with fixed resistor(s). For example, a
IkO pot in series with two 4.7kO resistors will yield a ± 280j.LV
range.
High closed loop gain and excellent linearity can be achieved by
operating the AD OP-37 within an output current range of
± IOmA. Minimizing output current will provide the highest
linearity.
+18V
-18V
ALL OTHER PINS
ARE NOT
CONNECTED
Figure 2. Burn-In Circuit
CAUTION: NOISE MEASUREMENTS
Precise measurement of the extremely low input noise associated
with the AD OP-37 is a difficult task. In order to observe the
rated noise in the O.IHz to 10Hz frequency range the following
cautions should be exercised.
Figure 1. Optional Offset Nulling Circuit
and Power Supply Bypassing
Zeroing the initial offset with potentiometers other than IOkO,
but between IkO and IMO, will introduce an additional input
offset voltage temperature drift error of from 0.1 to 0.2j.LV/oC.
Additionally, by intentionally trimming in a dc level shift a
voltage dependent offset drift will be created. It will be approximately the input offset voltage at 25°C divided by 300 (in j.LV/
0c).
Parasitic thermocouple EMF's can be generated where dissimilar
metals meet the contacts to the input terminals of the AD OP-37.
These temperature dependent voltages can manifest themselves
as drift type errors. Optimized temperature performance will
be obtained when both contacts are maintained at the same
temperature.
Output stability with the AD OP-37 is possible with capacitive
loads of up to 1000pF and ± lOY output swings. Larger capacitances should be decoupled with a 500 resistor inside the feedback
loop.
(1) The test time to measure O.IHz to 10Hz noise should not
exceed 10 seconds. As shown in the noise test frequency response
plot in this data sheet the O.IHz corner is only defined by a
single zero. A test time of 10 seconds acts as an additional zero
to eliminate noise contributions from frequencies lower than
O.IHz.
(2) Warm-up for a least five minutes will eliminate temperature
induced effects. During the first few minutes the offset voltage
typically increases 4j.L V. In a 10 second measurement interval
prior to temperature stabilization the reading could include
several nanovolts of warm-up offset error in addition to the
noise.
(3) For reasons similar to (2) the device under test should be
well shielded from air currents or other heat sinks to eliminate
the possibility of temperature changes over time invalidating the
measurements. Sudden motion in the vicinity or physical contact
with the package can also increase the observed noise.
An input voltage noise spectral density test is recommended
when measuring noise on a large number of units. Because the
IIf noise corner frequency is around 3Hz, a 1kHz noise voltage
density measurement combined with a O.IHz to 10Hz peak-to-peak
noise reading will guarantee IIf and white noise performance
over the rated frequency spectrum.
Although the AD OP-37 features high-power supply rejection,
the effects of noise on the power supplies may be minimized by
bypassing the power supplies as close to Pins 4 and 7 of the AD
OP-37 as possible, to load ground with a good quality O.OIj.LF
ceramic capacitor as shown in Figure 1.
OPERATIONAL AMPLIFIERS 2-241
Typical Performance Curves
(@ TA= +25"C, Vs= ±15VJ
,
i'..
,, I'.
. . . . AD~'(
-
"
'::: ' ~
r--.
ADOP·01
tlf CORNER =21Hz
~
~
ADOP-37
llf Cr~;R"2 7m
JI
II
111111111
100
FREQUENCY - HI
10
100
FREQUENCY _ Hz
Input Voltage Noise Spectral Density
V
1000
10
10
BANOWIDTH - kHz
Comparison of Op Amp Input Voltage
Noise Spectrums
Input Wideband Noise VS. Bandwidth
(0. 1Hz to Frequency Indicated)
0
/'
Ii
-(.10Hz
V
I--"
V I-:/
I-- ~
V
V f--
Ii
~
-
i,
;.
I
Ii
(iJ1OHz
~
.,....
I, o~
Ii3
b-
u"i""jJjl
Rs=l00U
Rl =lldl
1
"
TEMPERATURE _ "C
Input Voltage Nose vs. Temperature
II
I II
,00
1k
FREQUENCY - Hz
SUPPLY VOLTAGE _ :tV
Input Voltage Noise vs. Supply Voltage
Input Current Noise Spectral Density
'00
.,
-
.,.... .... t:::1-'
((110Hz
1/
..
..
1/1.- . /
1 J.-: :/""
vI-' l~ON RESlSTOR NOISE
~
i=
V
I'
1\
~~ TEST TIME MUST
E 10 SECONDS OR LESS
1111
I
"
01
SOURCE IMPEDANCE _
n
Total Noise vs. Source Impedance
o 1....F
,
I
10
J'ftEOUENCV _ Hz
0.1Hz to 10Hz Noise Test Frequency
Response
0.1Hz to 10Hz pop Voltage Noise
NOTE: Al.L CAPACITORS MUST BE NONPOLARIZED
0.1Hz to 10Hz Noise Test Bandpass Filter (Voltage Gain =50,000)
, 2-242 OPERATIONAL AMPLIFIERS
[
·
·r
J
·
10
ADoL
IIV
V
"".".,""
",,':"NE-
~
V
·
/,,'~
V."""SV
"-
... i...
o
WARM-UP 11ME _ M"tutes
"- ~OP~
200
-I
LESIZE 30
,...
.
~
"'
r"-
........
......
o
-15
-60
"
-
9 ..
AD0P47A
so
-26
80
~
') ~78
75
10G
126
Input Bias Current vs. Temperature
"
" '\
10k
10l1li
1M
10M
100M
Open Loop Frequency Response
0
"
.
: ,,
~
SlEW
,~ 1
-
- 2S
0
+25
+50
,
~2
·
0
·,
·
I
0
+1ti +100 +12$
"
IUPPLY VOLTAGI-
V.V
~
,M
r-..
'/' NEGAnt...i...J..
r--....
I'----. t--
//
Undistorted Output Swing vs.
Frequency
..,1-1
1ac1+1
If
10M
LOAD RESISTANCE _ leO
Open Loop Gain vs. Resistive Load
....J. •.J.J
1\
\
"
~y
Open Loop Gain vs. Supply Voltage
"
4
·
I~, ...
nMPERATURE _ 'C
·
II
I
•
.
Slew Rate, Gain Bandwidth Product
and Phase Margin vs. Temperature
.·
•
1
PHASE
fREQUENCY - MHz
./"". ~
:;:: /"'"
,
-GOW
~20
IT
/'
0
...........
.J~.s.
Open Loop Gain and Phase Shift vs.
Frequency
·
1
I---'
TI K
0
'\
0
,
,
10-
GA'",
FREQUENCY _ HI
=;-
..
l"-
i'-'
·
'TEMPERATURE -"C
Input Offset Current vs. Temperature
"
r-...
z
~
AD OP 37C
I
-75
·~ 100
AOOP-31A
TEMPEWATUAE -"C
Long Term Offset Stability @
Temperature
Input Offset Voltage Turn-On Drift vs.
Time
"'
I--
......... ......... ~:::~ t-
1
1
"
LOAD RESISTANCE -In
Output Swing vs. Resistive Load
ElAPSED TIME FROM SHORT - Mlnutws
Output Short Circuit Current vs. Time
OPERA TlONALAMPLIFIERS 2-243
,
"
,
~1dLATION
{A v '" +5. V, .. =20mV~
V
/
,/
,V
1500
1000
CAPACITIVE LOAD - pF
Large Signal Pulse Response
(Av = 5, RL =2k)
Small Signal Overshoot vs.
Capacitive Load
""'\:\
!g 80
~
~
~
+5UPPLY
102
10'
10·
Small Signal Pulse Response
(Av = 5, RL =2k)
-SUPPLY
~
105
~
10·
10'
loB
FREQUENCY - Hl
Power Supply Rejection Ratio
vs. Frequency
II
I III
[\
V c ... =:!:10V
"
Supply Current vs. Supply Voltage
,
,
·
,
·
·
,,
01
/
I
,
, §~
Av- +5V
Vo
=TvPOP
,
,
2-244 OPERA TIONAL AMPLIFIERS
FALL
"
Av= +5V
,
"
'00
LOAD RESISTANCE _ kU
CMRR vs. Frequency
;:::::::::::- ~
,
,
'\
Common-Mode Input Range vs.
Supply Voltage
Slew Rate vs. Resistive Load
12
18
24
TOTAL SUPPLY VOLTAGE _ V
Slew Rate vs. Supply Voltage
11IIIIIIII
ANALOG
WDEVICES
Fast Settling
Video Operational Amplifiers
HOS-050/HOS-050AlHOS-050C I
FEATURES
80ns Settling to 0.1%; 200ns to 0.01%
100MHz Gain Bandwidth Product
55MHz 3dB Bandwidth
100mA Output @ ± 10V
APPLICATIONS
D/A Current Converter
Video Pulse Amplifier
CRT Deflection Amplifier
Wideband Current Booster
HOS-OSOIAIC PIN DESIGNATIONS
TO-S PACKAGE
GROUND
+ INPUT
V-
-INPUT
OUTPUT
OFFSET
ADJUST*
V+
GROUND
GENERAL DESCRIPTION
The HOS-OSO, HOS-OSOA, and HOS-OSOC op amps are very
high speed wide band operational amplifiers designed to complement the Analog Devices' lines of high speed data acquisition
products. They feature a 100MHz gain bandwidth product; slew
rate of 300V//-1s; and settling time of 80ns to ±O.l%.
The HOS-OSOA, HOS-OSO, and HOS-OSOC have typical input
offset voltages of 10mV, 2SmV, and 4SmV, respectively.
'PINS FOR CONNECTING OPTIONAL
OFFSET POTENTIOMETER. RECOMMENDED
VALUE IS 10k OHMS, WITH CENTER ARM
CONNECTED TO +15V.
NC = NO CONNECT
BOnOMVIEW
,
,
~
GAIN 110011 LOAD)
All models have a rated output of ± lOOmA minimum, and an
exceptional noise spec of only 71LV rms, dc to 2MHz; they are
ideally suited for a broad range of video applications.
FAST-SETTLING OP AMPS
At one time, operational amplifiers could be specified according
to slew rates, bandwidth, and drive capability; and these parameters would be sufficient. Settling time was not considered until
the use of high speed video DIA converters became widespread.
The conversion speed of the DIA can be limited by the settling
time of the output amplifier, so it has become essential to select
an op amp whose settling time is compatible with the DIA
converter.
The increased emphasis on settling time has, in some cases,
created a preoccupation with slew rates in the minds of some
designers. But slew rate is only one component in establishing
settling time.
The amount of overshoot, and the ringing which are present at
the end of a step function change also have an effect. These
parameters, in turn, are influenced by the bandwidth (or lack of
it) when operating the op amp with closed loop gains greater
than one.
(continued after SpecljicatlOns)
,
--eM'
----
,
,
,
/
--- ~
----
V
L
V
,
~ . /V
~
PHASE
I"", ,
I
lk
,
OOM
10k
FREQUENCY _ Hz
Figure 1. HOS-050 Frequency Response
;:
I
Z
0
2.0
i= 15
~
iii
15 10
ffi
~
0.5
TEMPERATURE _
°c
Figure 2. Power Dissipation vs. Temperature
OPERA TIONAL AMPLIFIERS 2-245
SPECIFICATIONS (typical
@
+ 25°C and
Model
± 15V unless otherwise specified)
HOS-OSOA
HOS-OSO
ABSOLUTE MAXIMUM RATINGS
Supply Voltages (Vs)
Power DissIpation
Input Voltage
Differential Input Voltage
Operating Temperature Range (case)
Junction Temperature
Storage Temperature Range
Lead Temperature (soldering, lOsec.)
HOS-OSOC
±18V
See Figure 2
±Vs
±Vs
- 55°C to + 125°C
175°C
- 65°C to + 150°C
300°C
DC ELECTRICAL CHARACTERISTICS
Parameter
Open Loop Gain
Rated Output
Voltage
Current
(not short CIrcUIt protected)
Voltage
Input Offset Voltage
Imtial
vs. Temperature
vs. Power Supply Voltage
Input BIas Current
Imtial
vs. Temperature
Input Offset Curren t
Initial
Input Impedance
Dlfferenual
Common Mode
Conditions
RL
RI
~
~
Min
1O011
>10011
Max
~
~
>10011
>200!!
Max
*
*
35
150
Typ
Max
10
20
15
35
V
*
45
75
rnA
V
65
200
*
*
Units
dB
*
*
± 100
25
50
0.5
Min
*
*
±IO
Adjustable to Zero
@+25°e
Typ
*
+ 10/-8
RL
RL
Min
100
mV
/.lV/oe
mVIV
«I
+2SOe
I
2
Doubles
*
*
«I
+25°e
± 100
*
*
pA
1010
1010
*
*
*
*
!!
}In parallel with 5pF
Input Voltage Range
Common Mode
Differential
Common Mode RejectIon
Input NOise
de to 100kHz
dcto2MHz
Typ
=18
::'::18
=10
RFF
~
lOO!!; RFB
~
*
70
*
5
7
*
*
*
*
*
*
*
*
*
*
nA
110°C
fl
*
*
V
V
dB
IkH
*
*
j..tVrms
j..tVrms
AC ELECTRICAL CHARACTERISTICS I
Parameter
Slew Rate
Noninvertmg Slew Rate
Overload Recovery
UOlty Gam BandWidth Product
Small SIgnal BandWIdth, - 3dB
Output Impedance
Noninverting Bandwidth, - 3dB
Conditions
A = -l;R FF = RFB = soon,
Load ~ loon
A = 2; RFF = RFB = IOOOn;
Load ~ 100!!
SO% Overdnve
RFF ~ RFB ~ l00!!
A ~ -I,R FF ~ RFB ~ soon
A ~ -I,R FF ~ RFB ~ looon
A ~ - 2; RFF ~ l00!!,
RFB ~ 1000n
A ~ - 4, RFF ~ 2500;
RFB ~ 1000!!
Min
Typ
Max
Min
Typ
300
*
320
400
100
45
35
35
2-246 OPERA TIONALAMPLIFIERS
Typ
Max
Units
Vij..ts
*
*
V/f'.S
*
*
*
*
*
*
*
*
ns
MHz
MHz
MHz
*
*
MHz
*
30
Min
*
*
l>Cmbhe!o (one per pm) are av,ulable from AMP .I'> pdrl number 6·330808-0
SpeclficatlOn\ \uble(.t tochangc Without notlLC
PIN DESIGNATIONS
PINS
1
2
3
•
•
5
,.
7
8
9
11
12
FUNCTION
+v
GROUND
OFFSETADJ'"
OFFSETADJ'"
-INPUT
+INPUT
NC
GROUND
-v
-v
+v
OUTPUT
"'PINS FOR CONNECTING OPTIONAL
OFFSET POTENTIOMETER RECOMMENDED
VALUE IS 10k OHMS, WITH CENTER ARM
CONNECTED TO +15V
OPERA TIONALAMPLIFIERS 2-247
(continued from Features page)
The HOS-050 Series stands up under close scrutiny of these
characteristics because of its 100MHz gain bandwidth product.
The use of these amplifiers in a wide variety of applications has
confirmed their suitability for video circuits.
VOLTAGE AMPLIFIERS/CURRENT BOOSTERS
Video op amps such as the HOS-050 are generally characterized
by high gain bandwidth products, fast settling times, and high
output drive.
One of the most common uses of video op amps is for D/A
converter output voltage amplification or current boosting.
Figure 3 is one example of this type of application. In this circuit,
the internal resistance of the D/A is the feed forward resistor for
the op amp.
IUNIPOLAR = FI,,, -1024mA)
= R. x -S 12mA)
(BIPOLAR
Figure 3. Inverting Unipolar or Bipolar Voltage Output
The HDS Series D/A converters are fast -settling, current output
D/As available in 8-, 10-, and 12-bit resolutions. Both TTL and
ECL versions are available, and settling times range from IOns
for 8-bit units through 40ns for 12-bit units.
The circuit which is shown will provide a negative unipolar
output with binary coding on the input, and bipolar offset grounded. It will provide a bipolar output with complementary offset
binary coding on the input, and bipolar offset connected to 10 .
An approximation of the total settling time for the D/A op amp
combination is calculated by:
where: Eo max = peak voltage needed
10 max = maximum continuous current HOS-050 can
produce
IRFB = current in feedback resistor at peak voltage
Assume the feedback resistor value is 5,000n. Minimum load
would be:
10
Eo max
max - IRFB
JOV
lOY
:-::1O:;-Om-;A---2:;-m-;-A = -98m-A = I02fl minimum load
Designs which strive for driving a minimum load (by increasing
the feedback resistor) can create settling problems because of a
fundamental characteristic of op amp circuits . . . the higher the
feedback resistance, the slower the system response.
This phenomenon is the result of increased impedance for driving
stray capacitances in the circuit employing the op amp, and
fixed capacitances in the summing node.
Impedances need to be kept as low as possible consistent with
low distortion; and stray capacitances need to be eliminated to
the maximum possible extent. A large ground plane structure is
recommended to help assure low ground impedances. In addition,
0.1 f.LF ceramic capacitors and 3-IOf.LF tantalum capacitors connected as close as possible to power supply inputs will decrease
the potential for parasitic oscillations and other noise signals.
Another argument for limiting the size of the feedback resistor
is because of its effect on bandwidth. Bandwidth of the HOS-050
op amp and the value of the feedback resistor are inversely
related.
At any given gain of the op amp, the gain setting with the widest
bandwidth will be the one which employs the lower value of
feedback. As an example, a gain of I can be achieved with RFF
= RpB = 500n; or Rpp = RFB = I,ooon. Small-signal bandwidth
for the first combination is typically 45MHz; bandwidth for the
second is typically 35MHz.
OFFSET AND GAIN ADJUSTMENT
Figure 4 shows a method of using the HOS-050 op amp which
allows adjusting the offset and gain of the output voltage.
OFFSET
ADJUST
Ts = YTD 2+ To2
where TD is D/A settling time and To is HOS-050 settling time.
'"
-v, ,0--'11\/_-<>
This approximation is valid because both the D/A and the HOS050 exhibit 6dB/octave roll-off charateristics (single pole response);
and the combination of low D/A output capacitance and op amp
input capacitance does not materially affect the formula.
The user of the HOS-050 should remember the current flowing
in the feedback resistor (RI) must be subtracted from the output
available from the HOS-050.
There is a tendency, because of this fact, to use a high value of
feedback resistor to assure maximum current drive being available
for driving low impedances; but this approach may create undesirable side effects.
Calculating the minimum load that can be driven under two
conditions of feedback resistor values will serve to illustrate the
difference.
Assume the feedback resistor value is 500n. If output voltage of
the HOS-050 is 10 volts, and output current is 100mA, minimum
load would be:
10
Eo max
max - IRFB
JOV
JOOmA - 20mA
lOY
80mA
Figure 4. HOS-050 Offset and Gain Adjust
As shown, the gain of the circuit is established by the equation:
G
=
_
(RFB)
RFF
where RFB is the total of RGAIN and Gain Adjust.
Once the user has established the desired gain for the illustrated
circuit, the value of RFB can be used to determine the correct
value of ROFFSET with the equation:
1250 minimum load
RoFFSET = -
( Vee x RFB)
aEo
where aEo is the desired amount of offset on the output.
2-248 OPERA TIONAL AMPLIFIERS
Assume ±Vcc = ± 15V; RGAIN
the desired change on the output
= 900H; Gain Adjust
Under these conditions,
will be 15kH:
ROFFSET =
ROFFSET =
ROFFSET =
ROFFSET
=
100H;
± I volt.
_ (15V x [900 +IV1001)
settling time. They include (I) propogation delay through the
amplifier; (2) slewing time to approach the final output value;
(3) the time of recovery from the overload associated with slewing;
and (4) linear settling to within the specified error band.
Expressed in these terms, the measurement of settling time is
obviously a challenge and needs to be done accurately to assure
the user that the amplifier is worth consideration for his
application.
- (I 51V
kV )
15,000H
Figure 4 shows bipolar output operation. If unipolar output is
desired, the appropriate Vcc should be removed from the Offset
Adjust potentiometer.
Figure 6 is the test circuit for measuring settling time to 0.1%.
This method creates a "false" summing junction and the error
band is observed at that point.
R"
The O.ItJ-F capacitor attached to the wiper arm of the Offset
Adjust control isolates the control and helps prevent adjustment
noise from appearing on the output of the HOS-050.
CFB can be any value between 0 and 20pF, depending on the
value of RcAIN; and should be selected to optimize settling time
for the particular circuit layout in which the HOS-050 is being
used.
The Gain Adjust control should be a low value, low inductance
cermet trimming potentiometer.
Note: R FF , RcAIN, CFB and ROFFSET must be located as close to
the summing node of the HOS-050 as physically possible. This
helps prevent additional capacitance in the summing node and
corresponding bad effects on frequency response and settling
times.
Variable controls (such as Offset Adjust and Gain Adjust) should
never be tied to the summing node of the op amp. Their correct
electrical locations are those shown in Figure 4.
325
300
275
GAI~ ~FI_l
RFF
= RFB
=
I
soon
250
225
en
Q 200
Z
0
U 175
w
en
0
Z 150
Z
125
'"
,0" v-~
100
75
50
~1V~1
---
V
V
II
OUTPUT ERROR
=
[Rf~F: RFII]
Figure 6. Settling Time Test Circuit for
o. 1% Settling
If one were to attempt the measurement at the "true" summing
junction of the op amp, the results would be misleading. All
scope probes will add capacitance to the input and will change
the response of the system. Making the measurement at the
output of the amplifier is also impractical, since scope nonlinearities
and reading inaccuracies caused by overdriving the scope preclude
accurate measurements to the tolerances which are required.
The false summing junction method causes the amplifier to
subtract the output from the input; only one-half the actual
error appears at the false junction, and it can be measured to
the required accuracies.
The false junction is clamped with diodes to limit the voltage
excursion appearing at that point. This is necessary because the
amplifier will be overdriven and one-half its input voltage will
appear at the junction. Without the clamps, the scope used for
making the measurement would be overdriven and its recovery
time would mask the settling time of the amplifier.
The test circuit for measuring settling time to 0.01%, Figure 7,
is simply an extension of the same basic technique. Ml'asuring
to the closer tolerance requires additional gain in the circuit
driving the oscilloscope.
V
I
25
SUMMING NODE ERROR
FROM FALSE
SUMMING
NOOE
TOSmV
~---_ SENsmVITY
OF 475 SCOPE
1%
0.1%
0.05%
0.01%
PERCENTAGE OF FULL SCALE ..
Figure 5. Settling Time - Inverting Mode
SETTLING TIME MEASUREMENT
Although there are some exceptions, most members of industry
are in agreement on the description which says settling time is:
The interval of time from the application of an ideal step
function input until the closed-loop amplifier output has
entered and remains within a specified error band.
The well-informed user needs to be alert to the consequences of
settling time specs which do not meet that description.
This definition encompasses the major components which comprise
Figure 7. Settling Time Test Circuit for 0.01% Settling
IMPEDANCE MATCHING
The characteristics of the HOS-050 operational amplifier make
it an ideal choice for matching the impedances of video circuits
to the impedances of transmission lines.
In this application, source and load terminating resistors will
cause the output voltage to be halved at the end of the cable
OPERA TlONAL AMPLIFIERS 2-249
being driven by the op amp. This makes it necessary to set the
gain of the circuit to provide twice the desired voltage.
Three different values of resistors and cables are "phantomed"
into the figure as examples of possible characteristic impedances
which might be used. Figure 8 is not meant to imply the HOS-050
can drive three cables simultaneously.
...
v.
>+V;::~::..'_...., lOW
Z OUTPUT
The Analog Devices HOS-050 has different performance characteristics when operating as a noninverting amplifier, but the
care used in the design makes the differences less pronounced
than they are in many competing units.
The HOS-050 can be considered a true differential video op
amp. It requires little or no external compensation because its
rolloff characteristics approach a 6dB/octave slope. This helps
the user determine summing errors and loop response; and
helps assure the stability of the system.
The performance parameters for both inverting and noninverting
operation are shown elsewhere in this data sheet (see SPECIFICATIONS section and figures). A comparison of the characteristics
will highlight the similarities in performance, with the exceptions
noted above.
(RFF = RFB = soon. A = -1)
- - - -0 2V p.p. RL = 15011
-40 1-t-t--ji=-=-=-=-:;"~4V p.p. RL = 15011
I
2V P·P. RL = lk
" , - - " , 4 V p.p. RL = lk
~ -45
Figure 8. HOS-050 Impedance Matching
NONINVERTING OPERATION
The vast majority of video operational amplifiers display marked
differences in settling times and bandwidths when operated in a
noninverting mode instead of the inverting mode. There are a
number of valid reasons for this characteristic.
11
"':::l
...:::l
-50
9w
-55
"
-60
~
III
III
Most high-speed op amps use feed-forward compensation for
optimizing performance in the inverting mode. This is necessary
to obtain wide gain-bandwidth products while maintaining dc
performance in these types of devices. In effect, the op amp has
a wideband ac channel wlJich is not perfectly matched to the dc
channel.
Feed-forward techniques enhance the performance of the op
amp in the inverting mode by incresing the slew rate and smallsignal bandwidth. These techniques, however, also decrease the
amplifier's tolerance to stray capacitances, so must be employed
judiciously.
The overall input capacitance of the op amp is kept as low as
possible in the desigu; and any mismatch in the capacitance of
the two channels appears as an error in the output. Because of
the inherently low total input capacitance of the op amp, even a
small capacitive mismatch between channels shows up as a large
effective error signal.
-65
As a consequence, the mismatch is reduced to the smallest practical
value consistent with the economics of producing and using the
op amp. But it remains a mismatch, and manifests itself as a
difference in performance in the inverting versus noninverting
modes.
There are video op amps available at low cost which use a 741-type
amplifier for high dc open loop gain in the noninverting channel.
The user of these kinds of desigus may sometimes gain an economic
advantage, but at a high cost in performance. Bandwidths for
noninverting applications are often measured in kHz, not MHz,
for this approach.
A video op amp is acting as a voltage mode device at both inputs
when operating in the noninverting mode. This contrasts with
the inverting mode, where it is operating as a current mode
device.
2-250 OPERA TIONALAMPLIFIERS
4
OUTPUT FREQUENCY - MHz
Figure 9. Harmonic Distortion - Inverting
(R FF = RFB
..
0-
- - ... 2V P·P. RL
- - ... 4V p.p; RL
-40
.,~
-45
:::l
~ -50
~~ -55
!g
-60
Decreasing the channel mismatch can be achieved only by complicating the design of the op amp with additional components,
and rigorous selection of those components in the manufactuting
process.
05 1
"
1,,_ ," •
"
05 1
=
1k. A = 2)
= 15011
= 15011
2V P·P. RL
lk
4V P·P. RL
= lk
...J
".
...... '. '
"
2
..
~~
,,~
~./"~--~~~
4
OUTPUT FREQUENCY - MHz
Figure 10. Harmonic Distortion - Noninverting
IN SUMMARY. ,. A CAVEAT
Settling time specifications, bandwidth capabilities, harmonic
distortion performance, and other parameters for video op amps
cannot possibly inc1U1\e all possible situations and applications.
A multitude of seemingly insignificant conditions can have a
major impact on the unit and its ability to operate in any given
circuit.
The potential user is strongly urged to evaluate the effectiveness
of the HOS-OSO in the actual circuit in which it will be used.
In many instances, the application conditions are different from
the conditions used in specifying; there is no substitute for a
tria1 in the proposed circuit to determine if the op amp will
provide the desired results.
11IIIIIIII ANALOG
WDEVICES
FEATURES
<1mV Vos
Low Drift
80ns Settling to 0.1%; 200ns to 0.01%
100mA Output @ ± 10V
Low Offset, Fast Settling
Video Operational Amplifier
HOS-060 I
HOS-060 PIN DESIGNATIONS!
TO-8 (H-12A) Package
GROUND
APPLICATIONS
D/A Current Converter
Video Pulse Amplifier
CRT Deflection Amplifier
Wideband Current Booster
BOTTOM VIEW
NOTES
'SEESECTION 16(H-12A) fOR
PACKAGE OUTLINE INFORMATION
"PINS FOR CONNECTING OPTIONAL
GENERAL DESCRIPTION
The HOS-060 Operational Amplifier is an extension of the
proven hybrid technology used in the HOS-OSO series of op
amps.
The PET input and high-performance characteristics, including
wide bandwidth and fast settling, make it useful for a variety of
applications in the processing of video signals.
Recent innovations in circuit design have been incorporated into
the HOS-060 to make it extremely useful to the designer who
needs outstanding performance in current boosting, voltage
amplification, impedance matching, or a multiplicity of other
high-frequency requirements.
Voltage offset and its temperature coefficient have been dramatically improved in the HOS-060; offset is as low as most high
performance monolithic op amps.
The HOS-060 op amp is pin-for-pin compatible with its forerunner
HOS-OSO and is useable in the same diversity of video requirements. The reader is strongly urged to refer to the six-page data
sheet for the HOS-OSO op amp to obtain additional insight and
details on potential uses for the HOS-060.
The HOS-060 Operational Amplifier package is the industry
standard TO-8 metal can and operates over a case temperature
range of - 55°C to + 125°C; the model number for the standard
unit is HOS-060SH.
OFFSET POTENTIOMETER RECOMMENDED
VALUE IS 10k OHMS, WITH CENTER ARM
CONNECTED TO +1SV
·
·
,
GAIN Il00n LOAD)
,
·
·
~
---- --- ~
--- ---eM"
/
V
VPHAr
,./",
,
~ .../'V
~
lk
FREQUENCY _ Hz
,
I"" :
10M
Figure 1. HOS-060 Frequency Response
s:
I
2.0
Z
0
;: 1.5
~
ill
0
15
~
1.0
0.5
TEMPERATURE - "C
Figure 2. Power Derating
OPERA TIONAL AMPLIFIERS 2-251
SPECIFICATIONS(typical
@
+ 25"& and ± 15V unless otherwise specified)
HOS-060SH
Model
ABSOLUTE MAXIMUM RATINGS
Supply Voltages (V s)
Power Dissipation
Input Voltage
Differential Input Voltage
Operating Temperature Range (Case)
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, IOsec)
:t18V
See Figure 2
±Vs
±Vs
- 55°C to + 125°C
175°C
- 65°C to + 150°C
300°C
DC ELECTRICAL CHARACTERISTICS
Parameter
Conditions
Open Loop Gain
Rr. = lOon
Rated Output
Current
(Not Short-Circuit Protected) Rr. = >lOon
Voltage
Rr. = >200n
Input Offset Voltage
Initial
vs. Case Temperature
- 55°C to + 125°C
vs. Power Supply Voltage
«I
Input Offset Current
Initial
«I
Max
dB
:t 100
mA
V
:to.5
:t 1.5
mV
35
0.5
f!VrC
mVIV
Doubles
nA
110°C
+25°C
:t 100
IOlO
IOlO
}In Parallel with 5pF
Units
100
+25°C
Input Voltage Range
Common Mode
Differential
Common-Mode Rejection
Input Noise
dcto 100kHz
dct02MHz
Typ
:t1O
Adjustable to Zero
@ +25°C
Input Bias Current
Initial
vs. Temperature
Input Impedance
Differential
Common Mode
Min
:t1O
pA
!!
n
:t18
:t18
70
V
V
dB
7
f!Vrms
f!Vrms
RFF = 100!!; RFB = Ikn
AC ELECTRICAL CHARACTERISTICS 1
Parameter
Slew Rate
N oninverting Slew Rate
Overload Recovery
Unity Gain Bandwidth Product
Small Signal Bandwidth, - 3dB
Output Impedance
Noninverting Bandwidth, - 3dB
Conditions
A = -I;RFF = RFB = soon;
Load = lOon
A = 2;RFF = RFB = 1000n;
Load = lOon
50% Overdrive
RFF = RFB = soon
A = -I;RFF = RFB = soon
A = - I; RFF = RFB = 1000n
A = -2;RFF = soon;
RFB = 1000n
A = -4;RFF = 250n;
RFB = looon
Min
Typ
Max
300
V/f!s
320
400
100
45
35
V/f!s
35
MHz
ns
MHz
MHz
MHz
30
__
-55
'"
~-
__~~
__ ---
__~~..<-'
-60
05 ,
OUTPUT FREQUENCY - MHz
Figure 6. Harmonic Distortion - Noninverting
THE READER IS URGED TO CONSULT THE HOS-050
DATA SHEET FOR ADDITIONAL APPLICATIONS INFORMATION. THE HOS-060 IS PIN-FOR-PIN COMPATIBLE WITH THE HOS-050 SERIES AND CAN BE USED
IN SIMILAR WAYS.
11IIIIIIII ANALOG
WDEVICES
FEATURES
Wide Bandwidth - dc to 125MHz
High Slew Rate -1500V//Ls
Operation Guaranteed _55°C to +125°C (SH)
High Output Drive - ±10V with 100n Load
Wide Bandwidth,
High-Speed Buffer Amplifiers
HOS-l OOAH/HOS-l OOSH I
HOS-IOOAHIHOS-IOOSH
FUNCTIONAL BLOCK DIAGRAM
GND
APPLICATIONS
Current Boosters
High Speed AID Input Buffers
Nuclear Instrumentation Amplifiers
Coaxial Cable Drive
High Speed Line Drivers
Video Impedance Transformation
GND
GENERAL DESCRIPTION
The HOS-100SH and HOS-100AH Bipolar Buffer Amplifiers
are high-speed, voltage followerlbuffers designed to provide
high-current drive at frequencies from dc to over 12SMHz, as
well as providing ±10mA into 1kn loads (±lOOmA peak) at
slew rates of 1S00V//Ls. Both units also exhibit excellent phase
linearity (2°), and low distortion «0.1 %).
For commercial temperature ranges the HOS-IOOAH is specified for operation over the range of -2SoC to +8SoC (case).
The HOS-IOOSH is specified for operation over the military
range of -SSoC to +12SoC (case).
The HOS-IOOSH and HOS-100AH are intended to fulfill a
wide range of buffer applications, such as video impedance
transfoffilation, high impedance input buffers for AID converters and comparators, as well as high-speed line drivers and
nuclear instrumentation amplifiers. Additionally, both amplifiers will continuously drive son coaxial cables or serve as
yoke drives in high resolution CRT displays.
They are particularly well suited for current booster applications (Figure 3) within an op-amp loop where input impedance
and bias current requirements are less stringent than in FET
design.
'
;0:
I
z
0
;::
20
:1:
15
~
,ICAS~
i"'o
iii
C 10
ffi
I<
"i\I"'~
jMBllENT
;:
05
0
25 50
75 100 125 150
TEMPERATURE -
~c
Figure 2. Power Derating
"Fe
~F
11
~F
OUTPUT
RL
-15V
Figure 3. Current Booster
Figure t. Schematic Diagram HOS-tOO
OPERA TlONAL AMPLIFIERS 2-255
SPECIFICATIONS
PARAMETER
CONDITIONS
DC ELECTRICAL CHARACTERISTICS I ,2
Input Bias Current
Tc = 2SoC
HOS-IOOSH
MIN TVP MAX
S
HOS-IOOAH
MIN TVP MAX
20
2S
S
2S
UNITS
JAA
JAA.
Input Impedance
VIN = 1Vrms, f= 1kHz
RL = 1k, Tc = 25°C
100 200
100 200
kn
Voltage Gain
VIN = IV rms, f = 1kHz
RL = 1k, Tc = 25°C
0.9S 0.97 1.0
0.94 0.96 1.0
VIV
Output Offset Voltage
Rs = son, Tc = 2SoC
S
10
mV
mV
Output Offset Voltage Tc
Output Impedance
Rs = son
VIN = 1V rms, f = 1kHz
RS = SOOn, RL = 1k
RS = son, RL = 1k
Vs = iSV, RL = 1k
25
8
Output Voltage Swing
Supply Current
Power Consumption
AC ELECTRICAL CHARACTERISTICS 3
Slew Rate
Bandwidth
Rise Time
Propagation Delay
Phase Nonlinearity
Harmonic Distortion
i12
VIN = OV, TC = 25°C
Vs = ±lS
VS=iS
VIN=OV, Vs=i15V
Tc = 2SOC
10
25
7S
12
i13
6
±1'!
13
16
10
390 480
1000 lS00
100 12S
2
S
VIN = ±10V
VIN = IV rms
t.VIN = O.SV
t.VIN = O.SV
BW = 1 to 20MHz
25
8
1.5
2
<0.1
2S
3S
7S
12
JAvtc
n
±13
6
V
V
20
IS
10
4S0 600
rnA
rnA
mW
10001400
100 125
S
2
loS
2
<0.1
VIJAs
MHz
ns
ns
Degrees
%
l.S09X 10 7 hours
MFBF
NOTES
1 Unless otherwise noted, these specifications apply for +15V applied to Pin 12, and -15V applied to Pin 10.
a Unless otherwise noted, specifications apply over a temperature range, -55' C " TS; " +125' C for the HOS-l00SH, and
-2S'C "TC" +85'C for the HOS-I00AH. Typical values shown are for TC = +25 C.
'
'These specifications all measured with the following conditions: TC = +2S'C, Vs = ±ISV, RS = son, RL = lk_
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V+ - V-) . . . . . . . . . . . . . . . . . . . . . .40V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . l.SW
Input Voltage . . . . . . . . . . . . . . . . Equal to Supply Voltage
Maximum Continuous Output Current . . . . . . . . . . ±10OmA
Maximum Peak Output Current . . . . . . . . . . . . . . . ±2SOmA
Operating Temperature Range (Case) , .... -SSoC to +125°C
Storage Temperature . . . . . . . . . . . . . . . . -6S oC to +1S00C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C
Maximum Junction Temperature . . . . . . . . . . . . . . +17 S° C
2-256 OPERA TlONALAMPLlFIERS
ORDERING INFORMATION
Model
Temperature Range
Package
Options·
HOS-100AH
HOS-100SH
-2SoC to +8SoC
_SSoC to +12S oC
H-12A
H-12A
·See Section 16 for package outline information.
Wide Bandwidth,
High-Speed Buffer Amplifier
HOS-200 I
IIIIIIIIIII ANALOG
WDEVICES
FEATURES
Wide Bandwidth/Good Drive
Fast Rise Time
Low Power
± 5V Supplies
HOS-200 FUNCTIONAL BLOCK DIAGRAM
+5V
+5V
APPLICAnONS
Current Boosters
High-Speed AID Input Buffers
Instrumentation Amplifiers
Coaxial Cable Drivers
High-Speed Une Drivers
GENERAL DESCRIPTION
The HOS-200AH and HOS-200SH Buffer Amplifiers are highspeed, voltage followerlbuffers designed to provide up to lOOmA
of continuous current at frequencies from dc to 200MHz. AC
performance is enchanced with slew rates exceeding 1SOOV/ jIoS.
Both units exhibit excellent phase linearity and low distortion,
making them ideal for raster graphic and other video-speed
applications.
These devices are designed to fit into a broad range of buffer
applications, such as video impedance transformation; highimpedance input buffers for AJD converters and comparators;
and high-speed line drivers for nuclear instrumentation amplifiers.
The HOS-200 will drive son and 7Sn cables, and can serve as a
yoke driver in high-resolution CRT displays.
The versatility of the HOS-200 makes it particularly well suited
for use with the Analog Devices series of raster graphic video
DACs, such as the monolithic AD9700 and the hybrid HDG
Series. The HOS-200 followerlbuffer can also economically
enhance the output drive of monolithic op amps.
MIL-STD-1772 approval has been granted to the Analog Devices
manufacturing facility that produces the parts, which are also
available with MIL processing. The HOS-200AH operates from
- 2SOC to + 8SOC; the HOS-200SH is specified for - SSOC to
+ 12SOC.
-5V
-5V
GND
GND
90
4
45
..=
!
w
:8'u
.!
~
~
0
PH~ \
I
~
to
Rs
-2
Q
I
-
RL
Vs
VIN
-4
lOOk
GAIN
.::
IJl
'\
= son
= lkll
= ±5V
il
....::
45
= 1V rms
I
1M
;;
10M
100M
\\
-90
lG
FREQUENCY - Hz
HOS-200 Phase and Gain Response
OPERAT/ONALAMPLIF/ERS 2-257
SPEC IFICATIONS (typical
@ + 25"& with ± Vs
= ± 5V unless otItelWise specified)
Model
HOS·200AH
HOS·200SH
ABSOLUTE MAXIMUM RATINGS
Peak Voltage Between Supply Terminals (Vs + to Vs - )
Continuous Voltage Between Supply TenninaIs (Vs + to Vs - )
Power Dissipation
Input Voltage
Continuous Output Current
Peak Output Current
Operating Temperature Range (Case)
Junction Temperature
Storage Temperature Range
Lead Temperature (soldering, 10see)
30V
16V
See Derating Graph
±Vs
±100mA
±250mA
- 25·C to + 85"C
+ 150·C
-65"Cto + 150"C
+300"C
*
*
*
*
*
*
- 55·C to + 125·C
*
*
*
DC ELECTRICAL CHARACTERISTICS
Parameter
Conditions
Input Bias Current
Input Impedance
VIN=OV;Rs= 10k!!
VIN = IVrms;f= 1kHz;
RL=lk
VIN=IV;RL=lk
VIN =IV;RL =I000
Rs = 500
Rs = 500
V IN = IVrms;f= 1kHz
Rs = 5000;RL = IkO
Rs=5000;RL=lkO
VOUT=OV
VIN=OV;Vs = ±5V
VIN=OV;Vs = ±5V
Voltage Gain
Offset Voltage
Offset Voltage Tc l
Output Impedance
Output VoItage Swing
Output Current (Continuous)
Supply Current
Power Consumption
Power Supply Rejection
Ratio (PSRR)
AC
AVs= ±2.5V
Min
100
0.975
0.900
4.0
100
Typ
Max
-SS"C
+2S"C
+12S·C
Units
8
25
30 (max)
20 (max)
20 (max)
/LA
200
0.985
0.915
12
25
8
12
1000min)
kO
0.975(min) 0.975(min) 0.975(min) vrv
0.900 (min)
vrv
18 (max)
15 (max)
15 (max)
mV
25 (typ)
5 (typ)
5(typ)
/LVrC
12 (max)
0
16
160
3.75 (min) 4.0 (min)
100 (min)
16 (max)
16 (max)
160 (max) 160 (max)
25
4.25
12
120
40
45
4.0(min)
20 (max)
200 (max)
40 (min)
V
rnA
rnA
mW
dB
ELECTRICAL CHARACTERISTICS2,
Parameter
Conditions
Min
Typ
Slew Rate
Bandwidth ( - 3dB)
Rise Time
Propagation Delay
Phase Nonlinearity
Harmonic Distortion
VIN = ±2.5V
VIN=IVrms
AVIN =O.5V
AVIN = O.5V
BW = I to 20MHz
1000
1500
200
1.5
1.5
2
<0.1
1000 (min)
200
1.5
1.5
2
<0.1
V//Ls
MHz
ns
ns
degree
%
90
40
90
40
·CIW
·CIW
>1.1 X 107
hours
Max
-SS·C
+2S·C
+12S"C
Units
THERMAL RESISTANCE'
Junction to Air, alA (Free Air)
Junction toCase,alc
MTBF4
PACKAGE OPTIONs
TO·8(H·12A)
NOTES
'Input offset voltage T c IS typically less than Sf.LVrc from + 2SOC to hIgh temperature extreme.
2These specificat:J.ons measured under following condItIons: T c = + 25"C; ± Vs = ± SV; Rs = on, RI = lkH.
3Recommended maxImum Junction temperature IS + lSO"C.
'MTBF calculated uslOg Mil Handbook217, Ground; Fixed; Temperature (case) ~ 35°C.
sSee Section 16 for package outlme informatIOn.
Specificanons subject to change WIthout notice.
PIN DESIGNATIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
2-258 OPERA TIONALAMPLIFIERS
FUNCTION
v+
GROUND
NC
NC
INPUT
NC
NC
GROUND
vvOUTPUT
v+
I-20
~
"
;t
I
"'SE
Z
0
~
1.5
'"
~
Q
0:
"';t
Each power supply voltage bas been provided with two pins on
the HOS-200; + 5V is connected to pins 1 and 12, and - 5V is
connected to pins 9 and 10. Each pair of pina is connected
internally, but should also be connected extemally to its mate
and the appropriate power supply. Pins 2 and 8 are ground pins
which are connected internally, but should also be connected
. together extemally before the connection to the low-impedance
ground recommended above.
1.0
~
0.5
o
o
25
~
"~
AMBI~~
r-....
50
75
100
TEMPERATURE - 'C
125
HEAT SINKING
An eftIcient heat sink is required for the HOS-200SH if the user
expects to obtain maximum output drive at temperatures up to
+ 125"C. One possibility is the Thermalloy-2204A, but other
appropriate devices are also avai1able.
150
HOs-200 Power Derating
ENHANCING HOS-200 PERFORMANCE
The HOS-200 is an excellent building block in high slew rate,
pulse-oriented systemS. Output loading in these types of systems
is often highly capacitive because of coaxial cables and twisted
pair lines; but the powerful drive capability of the HOS-200
makes it a good choice for inclusion in the system.
The case of the HOS-200 is electrically isolated from the circuit
containing the amplifier. This means the case can be connected
to system ground(s) for additional heat dissipation, and shielding.
Pins 3, 4, 6, and 7 are designated as "no connection" and can
also be connected to the low-impedance ground to help dissipate
heat.
SUGGESTED APPLICATIONS
Figures 1 and 2 are possible application ideas using the HOS-200
amplifier. The circuits which are shown are not intended as the
only possible applications for this device; they are simply intended
to illustrate some possibilities offered by the unit.
Its effectiveness can be extended funher through the use of a
sma11 series resistance (50-3000) in the output of the unit. This
bas two effects: it shields the HOS-200 from the load capacitance,
which might otherwise be outside the design limits of the amplifier;
and also tailors the pulse response. The output response can
also be enhanced with a sma11 (I00pF-300pF) capacitor connected
between the input and output.
.
LAYOUT CONSIDERATIONS
Like any high-speed device, the HOS-200 amplifier will benefit
from the use of good high-frequency design practices. The
undesirable effects of stray capaQ.tance and high frequency
coupling can be minimized with close attention to circuit layout.
A low-impedance ground plane under the HOS-200 can reduce
the effects of distributed capacitance; and provide a greater
degree of shielding for the device. Lead lengtbs in and out of
the HOS-200 should be kept as short as practicable to minimize
impedances and limit the effects of signal reflections.
R2
Av = -
Rl
m
Cl
v+
R4
50-10n
Cl AND R4 SELECTED
FOR OPTIMAL
PULSE RESPONSE
Figure 1. Increased Output Current Drive
Direct soldering of the unit into the circuit is recommended to
avoid the inter-lead capacitance of sockets and the reduction in
performance which can result. If socket mount must be used,
individual pin sockets are preferable to device sockets.
The HOS-200 contains internal power supply decoup1ing
capacitors, but funher improvement in performance can often
be achieved with external decoup1ing capacitors connected as
closely as possible to the power supply pins of the amplifier.
Typically, a combination of a O.IIJ.F ceramic disk capacitor and
a l00pF tantalum capacitor is connected to each supply pin.
Figure 2. Impedance Transformations for 5Dn, 75Jl, and
9311 Cables
OPERATIONAL AMPLIFIERS 2-259
PERFORMANCE GRAPHS
Figures 3 through 9 depict typical performance of the HOS-200
amplifier for a number of characteristics. As in the parameters
shown in the SPECIFICATIONS section of the data sheet, the
data shown in the graphs are typical performance at .j. 2S"<:,
unless noted otherwise.
14
V
.992
12
V
.990
-
'--...
Rs = 10k!!
r--.RL == nn
Vs == ±5V
~
.
v... =ov
............
r-- r-....
'"
=
.9..
r-r=!j
r-- ... .0..
• 984
RL == 1kU
Vs = ±5V
-50
-25
25
50
7S
100
-so
125
-25
TEMPERATURE - "C
Figure 3. Input Bias Current vs.
Temperature
/
........
............
25
50
TEMPERATURE - "C
/
i""-
75
100
125
.8
±2
:!:4
:!:6
SUPPLY VOLTAGE - Votts
Figure 4. Gain vs. Temperature
2.
son
At. == nn
0988
!i
!:; 098G
g
...........
=
Rs
~
CI
Figure 5. Output Voltage vs.
Supply Voltage
20
/
V
15
/
VIN = OV
/
V
/
/
300
III
IV
200
c::,
15
j
~ 10
".
!!!
/
/'
100
i
~
~
-10.
-200
~
-300
:!:2
"
:8
::t4
10
20
FREQUENCY _ MHz
SUPPLY VOLTAGE - Volts
Figure 6. Supply Current vs.
Supply Voltage
Figure 7. Output Impedance vs.
Frequency
.
2.
,.
50
I
'.0
-400
o
ro
20
U
q
~
h
n
h
H
~
NANOSecONDS
Figure 8. Small-5ignal Settling
(± 250m V Square Wave Input)
ORDERING INFORMATION
The model HOS-200AH operates over an industrial temperature
range of - 2S"<: to + 8S"<:. The model HOS-200SH is designed
for a military temperature range of - Ss·c to + 12S"<:. The
Computer Labs Division of Analog Devices, which produces the
HOS-200 bas been certified as meeting the standards established
by MIL-STD-1772. Contact the division for details regarding
parts with MIL processing.
o.
~
g -05
-1.
o
ro
20
~
q
~
h
n
h
H
NANOSECONDS
Figure 9. Large-Signal Settling
(± 2.5V Square Wave Input)
2-260 OPERA TlONALAMPLIFIERS
~
Comparators
Contents
Page
Selection Guide . . . . . . . . . . . . .
3-2
Orientation . . . . . . . . . . . . . . .
3- 3
AD790 - Fast Single Supply Comparator
3-5
3-9
AD9685/9687 - High Speed Comparators
AD9686 - High Speed TTL Voltage Comparator.
AD96685/96687 - Ultrafast Comparators . . . . .
3 - 13
3 - 17
COMPARATORS 3-1
Selection Guide
Comparators
Prop Delay
Model
AD790
AD9685
AD9686
AD9687
AD96685
AD96687
3-2 COMPARTORS
os
Latch
35
2.2
7
2.7
2.5
2.5
X
X
X
X
X
X
Interface
Logic
TIL
EeL
TIL
EeL
EeL
EeL
Page
3-5
3-9
3 - 13
3-9
3 -17
3 - 17
Notes
Dual
Dual
Orientation
Comparators
A voltage comparator compares two voltages and provides an
output that is a function of their difference. For the products in
this section, the output of an ideal comparator has two stable
states representing the sign of the difference. Thus, the output
will be a logic" I" if the voltage at the input labelled "+" is
greater than the voltage at the input labelled" - ," and logic
"0" for the opposite case.
In addition, practical comparators have a small amount of hysteresis
(internal or external) to help keep noise from causing the output
to bounce around, and most have a latch, which makes it possible
to freeze the output at the state it has at a given instant of time,
in response to a logic signal. Since the comparator is producing
a digital decision, fts outputs are generally compatible with
either TTL or ECL.
A comparator is used wherever some action depends on whether
a voltage is - or becomes - greater or less than another voltage usually a reference. Since it is in effect a I-bit ND converter,
the comparator is the basic element of virtually all AID converters,
as well as a sign-magnitude adjunct. Because the voltage that is
compared with a reference can be the linearly varying output of
an integrator with constant input, a comparator can be used in
analog-based event timing. The comparator is also an element of
pulse-width modulators, peak detectors, delay generators, switch
drivers, etc.
Aside from its op-amp related specifications, such as bias current,
offset & drift and the various logic-related timing and interface
specs, the key comparator spec is propagation delay: the time
required for the output to reach the 50% point of a transition,
after the net input has crossed the offset voltage - when driven
by a square wave to a prescribed value of input overdrive, usually
5mVor lOmV.
A comparator is essentially a fast, high-gain amplifier whose
output is always at an upper or lower limit, except when switching.
The simplest comparator would be an open-loop-connected,
uncompensated, high-gain, high-slew-rate op amp with excellent
offset & drift characteristics, fast recovery from overdrive and
an overdrive-protected input.
The Selection Guide classifies Analog Devices comparators by
propagation delay, presence or absence of a latch and interface
logic compatibility. It also indicates the presence of dual comparators, each comprising two independent comparators on a
single monolithic chip. Since pairs of comparators jointly have
four possible states, they may be used for high-accuracy 2-bit
ADCs and for window measurements, as well as for simple twoin-one space-saving.
CaMPARA TORS 3-3
3-4 COMPARATORS
Fast Single Supply
Comparator
r.ANALOG
WDEVICES
AD790 I
AD790 FUNCTIONAL BLOCK DIAGRAM
FEATURES
35ns max Response Time
Single +5V Supply Operation
CMOS or TTL Logic Capability
250....V max Input Offset Voltage
1mV Input Voltage Resolution
15V max Differential Input Voltage
Latching Function Capability
Glitch Free Output Stage
60mW Power Dissipation
APPUCATIONS
Oversampling AID Converters
Single Supply Line Receiver
MOS Switch Drivers
Pulse Width Modulator
Peak Detector
Single Supply Ground Crossing Detector
Time Delay Generator
Available in Plastic, Mini-DIP, Hermetic
~
Cerdip Packages
8-Pin Plastic Mini-DIP
and Cerdip
VLOGIC
OUTPUT
GND
AD790
.
-precision, low-power and glitch-free operbrought together in the AD790, make it the
''-\I, ''i, ';'-ii'
'iiio
oice for l2-bit high-speed applications.
\1'., ~ ';',11 ",,,,,,',,,,_....-___ 790 is available in five performance grades. The AD790J
\~,;.t'
<.'1>., '1;., '
790K are mted over the commercial temperature
PRODUCT DESCRIPTION
;'L;'
¢,~ ~\l''''(ilj~ \""
:t70°C. The AD790A and AD790B are rated over
The AD790 is a fast (3Sns) pre
. t~. It ~ ,,"
. temperature range of - 40°C to + 85°C. The
a number of features that make
eptl
~~d
S is rated over the military temperature range of - 55°C
easy to use. The AD790 may ope
fro
~1fI''5V sl,Jffi~,
+ l250C and is available processed to MIL-STD-883B,
or a dual ± lSV supply. In the single supply
de, the A~O'~;'
Rev. C.
inputs may be referenced to "ground," a feature not found irl:;P1'
most other comparators. In the dual supply mode it has the
Extened reliability PLUS screening is available, specified over
unique advantage of handling a maximum differential voltage of
the commercial and industrial temperature range. PLUS screening
l5V across its input terminals, easing interfacing of the input to
includes a 168 hour burn-in, as well as other environmental and
large amplitude and dyanamic signals.
physical tests.
'ii,
'~,
,
This device is fabricated using Analog Devices' complementary
bipolar (CB) process - offering benefits such as fast response
time (35ns), low input offset voltage (250""V) and high input
voltage resolution (lmV). To preserve its speed, the AD790
incorporates a "low glitch" output stage which does not exhibit
large current spikes normally found in TTL or CMOS output
stages. Its controlled switching reduces power supply disturbances
which would tend to feed back to the input causing undesired
oscillations or hysteresis. The AD790 has a latching function
which makes it ideal for applications requiring synchronous
detection - wherein the latch is activated by forcing the latch
pin low with either a CMOS or TTL gate.
PRODUCT HIGHLIGHTS
1. The AD790 is a fast, high precision, easy to use voltage
comparator.
2. True single supply operation plus dual supply capability
allow usage in many design environments.
3. CMOS or TTL compatible output stage.
4. 60mW power dissipation is the lowest in its class.
5. Glitch-free output stage minimizes oscillation and hysteresis.
COMPARATORS 3-5
SPECIFICATIONS(@+2SOCandVs= ± 15V dc, V
LOG1C'
Model
RESPONSE TIME
Propagation Delay
Latch Response Time
Latch Setup Time
OUTPUT CHARACTERISTICS
Output HIGH Voltage
Conditions
Min
5mVOverdrive
100fLASink
T11lln- T max
Output Low Voltage
AD790j/AlS
Typ
Max
30
15
10
4.7
4.6/4.614.6
8mASink
Tmm-T~x
INPUT CHARACTERTISTICS
Input Offset Voltage l
Hysteresis2"
Voltage Resolution
Input Bias Current
unless otherwise noted)
4.8
4.8
0.44
0.44
200
Tmm-Tmax 1
Tnun- Tmax
Tnun- Tmax'
Either Input
TlUln-Tmax
300
400
0.8
2
Min
35
20
15
30
15
10
4.7
4.6
0.5
0.5/0.5/0.5
1000
1.5
600
1.2
5
6/618
300
88
85
INPUT VOLTAGE RANGE
Differential Input Voltage
Common-Mode Input
CMRR
s-2
LATCH CHARACTERISTICS 2
LOW Input Level
HIGH Input Level
Latch Input Current
-Vs
90
88
35
20
15
0.5
0.5
500
0.75
500
1.0
3
4
0.15
0.2
+Vs =+15V
-Vs= -15V
VLOG1C = +5V
± 15VOperation
8
4
2
±Vs
+Vs-2
100
NOTES
lDefmed as the average of the low to high and high to low transition input voltages.
2Guaranteed over full temperature range a1tbough not 100% tested at temperature for IIA grades. 100% tested on all other geades.
'Defmed as half the magnitude between low to high and bigh to low transition input voltages.
4+ Vs must be no less than O.SV below VLOG1C in any supply operating conditions.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final test. All min and max specifications are guaranteed
although only those shown in boldface are tested.
V
V
dB
dB
4.5
4
10
5
3
240
V
V
V
V
dB
2
6
ns
100
0.8
4
ns
ns
96
400
0.8
1.3
1.6
TmtntoTmax
Units
fLV
mV
fLV
mV
I1A
fLA
fLA
fLA
dB
0.01
PSRR
3-6 COMPARA TORS
4.8
4.8
0.44
0.44
50
Input Offset Current
SUPPLY CHARACTERISTICS
Differential Supply Voltage 2,'
Logic Supply
Quiescent Current
.+Vs
-Vs
VLOGIC'
Power Dissipation
AD790KIB
Typ
Max
8
4
2
V
V
5
fJ.A
6
fLA
36
6
V
V
10
5
3
240
rnA
rnA
rnA
mW
SP EC IFICAli 0NS
Model
RESPONSE TIME
Propagation Delay
Latch Response Time
Latch Setup Time
OUTPUT CHARACTERISTICS
Output HIGH Voltage
(@ + 250C and Single
+ 5V Supply, unless otherwise mted)l
Conditions
5mV Overdrive
lOO..,ASink
Trrun-Tmax
Output LOW Voltage
AD790J/AiS
Typ
Max
Min
35
20
15
4.7
4.6/4.6/4.6
4.8
4.8
0.44
0.44
8mASink
Trrun- Tmax
INPUT CHARACTERTISTICS
Input Offset Voltage2
Min
40
25
20
AD790KIB
Typ
Max
35
20
15
4.7
4.6
0.5
0.5/0.5/0.5
200
4.8
4.8
0.44
0.44
50
TmJo-Tmax
HysteresisM
Voltage Resolution
Input Bias Current
Tmm-Tmax
Tmm-Tmax
Either Input
300
300
450
0.9
1.3
Tnun- Tmax
Input Orrset Current
PSRR
0.01
TIlUD-Tmax
4.5-~M.-t-~M.-+-o:SIENSE
)Vs
OUTPUT
R.,.
R,.. Rv ARE EXTERNAL GAIN-SEmNG RESISTORS
An amplifier circuit which is optimized for performance as an
instrumentation amplifier gain block has high input impedance,
low offset and drift, low nonlinearity, stable gain and low effective
output impedance. It is commonly used for applications which
capitalize on these advantages. Examples include: transducer
amplification - for thermocouples, strain-gage bridges, current
shunts and biological probes; preamplification of small differential
signals superimposed on high common-mode voltages, signal
conditioning and (moderate) isolation for data acquisition; and
signal translation for differential and single-ended signals wherever
the common "ground" is noisy or of questionable integrity.
Single-ended software-programmable gain amplifiers, such as
the AD526, with fixed binary gains of 1, 2,4, 8, etc., are often
listed with instrumentation amplifiers. They are used in systems
having a "clean" signal ground to provide appropriate amounts
of digitally controlled gain to normalize the level of the output
signal to correspond to a large fraction of the input range of an
AID converter; they can thus be used as components of a floatingpoint AID conversion system to preserve accuracy over a wide
dynamic range. See also "Data-Acquisition Subsystems" in the
Data Conversion Products Databook.
Instrumentation amplifiers are usually chosen in preference to
user-assembled op-amp circuitry because they offer optimized,
specified performance in low-cost, easy-to-use, compact packages.
If the application calls for high common-mode voltages (typically,
voltages in excess of the amplifier supply voltage), or if isolation
impedances must be very high (e.g., 10 100, with galvanic isolation,
as in medical and industrial applications), the designer should
consider an Isolation amplifier.
NOTES
IApplication Note: "A User's Guide to Ie Instrumentation Amplifiers,"
by J. Riskin, available upon request.
'Transducer Interfacing Handbook, D.H. Sheingold, ed., 1980. $14.50,
Analog Devices, Inc., P.O. Box 796, Norwood, MA 02062
4-4 INSTRUMENTA TlON AMPLIFIERS
INSTRUMENTATION AMPLIFIER ARCHITECTURE
Basic Analog Devices instrumentation amplifiers have two highimpedance input terminals, a set of terminals for gain programming, an "output" terminal and a pair of feedback terminals,
labeled sense and reference, as well as terminals for power supply
and offset trim. Gain is programmable in three ways:
• The gain of basic amplifiers, such as the AD521, AD522
and AD625, is established by connecting resistors externally.
Such circuits are generally used for dedicated fixed-gain
applications.
• Pin-programmable amplifiers, such as the AD524 and AD624,
have a set of internal resistors; a limited set of fixed gains in
the range of 1 to 1,000 are chosen by appropriately interconnecting the resistors via external pins. The connections can be
fixed or switched via DIP switches or reed relays (if CMOS
switches are used, the on resistance of the switches must be
considered in series with the internal gain resistors).
• Digitally (or "software-") programmable amplifiers are completely self-contained, with gains set by a 2-, 3- or 4-bit digital
control word. These devices include the AD365 (with gains of
1, 10, 100, SOD) and the AD526 (with binary gains of 1-16,
cascadable to 256).
Except for the AD521, the differential input amplifiers use
variations of the well known three-op-amp configuration, consisting of a differential input -output gain stage and a subtractor
stage. Gain (",IVN) is set by the choice of a single gain-setting
resistor, RG • When the sense (Vs) feedback terminal is connected
to the output terminal, and the reference terminal (VR ) is connected
to power common, the output voltage appears between the
output terminal and power common.
The V s and V R terminals may be used for remote sensing - to
establish precise outputs in the presence of line drops; they may
be used with an inside-the-loop booster follower to obtain power
amplification without loss of accuracy; and they may be used to
establish an output current that is precisely proportional to the
difference signal. A voltage applied to the V R terminal will bias
the output by a predetermined amount. It is important always
to maintain very low impedance (in relation to the specified V s
and VR input impedances) when driving the Vs and VR inputs,
in order not to introduce common-mode, gain, and/or offset
errors. In devices using the 3-amplifier configuration, the VR
terminal is sometimes used for "tweaking" common-mode
rejection.
SPECIFICATIONS
Specification tables are generally headed by the legend: "specifications are typical at V s = ± 15V, RL = 2kn, and T A = + 25°C,
unless otherwise specified." This tells the user that these are the
normal operating conditions under which the device is tested.
Deviations from these conditions might degrade (or improve)
performance. When deviations from the "normal" conditions
are likely (such as a change in temperature), the significant
effects are usually indicated within the specs. "Typical" means
that the manufacturer's characterization process has shown this
number to be in the middle of a distribution.
Specifications not discussed in detail are self-explanatory and
require only a basic knowledge of electronic measurements.
Such specs are not uniquely applicable to instrumentation amps.
GAIN: These specifications refer to the linear transfer function
of the device; for example, the AD524 gain equation is:
G = I
+ 40,000 VIV
RG
The value of RG for a given gain value is:
= 40,000 n
R
G
G--'I
For example, if G is to be 200VIV,
~ =
201 ohms.
Gain Range: Specified at 1 to 1,000, for example, resistorprogrammable devices may work at higher gains (lVIV is
minimum, except for the AD521), but the manufacturer does
not specify performance outside the range. In practice, noise
and drift may make higher gains impractical for a given device.
Equation Error (or "Gain Accuracy"): The number given by this
specification describes deviation from the gain equation when
RG is at its nominal value. The user can trim the gain or compensate
for gain error elsewhere in the overall system. Systems using
microprocessors (or computers, or other digital "intelligence")
can be made self-calibrating, to take into account the lumped
gain errors of all the stages in the analog portion of the system,
from transducer to A/D converter.
Gain vs. Temperature: These numbers give the deviations from
the gain equation as a function of temperature.
SETTLING TIME is defined as that length of time required
for the output voltage to approach and r~main within a certain
(±) tolerance of its final value. It is usually specified for a fast
step that will drive the output through its full-scale range, and
it includes slewing time. Since several factors contribute to the
overall settling time, fast settling to 0.1 % does not necessarily
mean proportionally fast settling to 0.01 %, nor is settling time
necessarily proportional to gain. Principal contributing factors
include slew-rate limiting, underdamping (ringing) and thermal
gradients (long tails).
GAIN-BANDWIDTH PRODUCT (GBWP) - the product of
the highest gain and its corresponding bandwidth - is a rough
figure of merit for bandwidth as an aid to the preliminary screening
process. However, since gain and bandwidth are not necessarily
in exact inverse proportion, it can be a misleading specification,
especially at the lower gains, if interpreted literally.
VOLTAGE OFFSET: Voltage offset and common-mode rejection
(see below) specifications are often considered the key figures of
merit for instrumentation amplifiers. While initial offset can be
adjusted to zero, shifts in offset voltage with time and temperature
introduce errors. Systems that involve "intelligent" processors
can correct for offset errors in the whole measurement chain,
but such applications are still relatively infrequent; in most
applications, the instrumentation amplifier's contribution to
system offset error must be defined.
Voltage offset and offset drift in instrumentation amplifiers are
functions of gain. 1 The offset, measured at the output, is equal
to a constant plus a term proportional to gain. For an amplifier
with specified performance over a gain range from 1 to 1,000,
the constant is essentially the offset at unity gain, and the proportionality term (or slope) is equal to the change in output
offset between G = 1 and G = 1,000, divided by 999. To refer
offset to the input (RTI), divide the total output offset by the
gain. Since offset at a gain of 1,000 is dominated by the proportional
term, the slope is often called the "RTI offset, G = 1,000." At
any value of gain, the offset is equal to the unity-gain offset plus
the product of the gain and the "RTI offset."
The same considerations apply to the offset drift. For example,
the maximum RTI drift ofthe AD624C is specified at 0.2S.,VI"C.
Thus, the output drift is (0.2SfLVI"C x G) + lOfLV/oC at any
gain, G, in the range.
Voltage offset as a function of power supply level is also specified
RTI at one or more gain settings.
Nonlinearity (or Gain Nonlinearity): Nonlinearity is defined as
the deviation from a straight line on the plot of output vs. input.
The magnitude of linearity error is the maximum deviation from
a "best-straight line," with the output swinging through its fullscale range. Nonlinearity is usually specified in percent of full-scale
output range.
IThere is a good explanation of the specification of offset in the
Application Note: "A User's Guide to Ie Instrumentation
Amplifiers," by J. Riskin, available upon request.
INSTRUMENTATION AMPLIFIERS 4-5
INPUT BIAS AND OFFSET CURRENTS: Input bias currents
are those currents needed to bias the input transistors of a dc
amplifier or to supply the junction leakage of FETs. FET-input
devices have lower bias currents than those using bipolar transistors, but FET leakage currents increase dramatically ,with
temperature, approximately doubling every lIoC. Since bias
currents can be considered as a source of voltage offset (when
multiplied by source resistance), the change in bias currents is
of more concern than the magnitude of the bias currents. Input
offset current is the difference between the two input bias
currents.
Important Note
Although instrumentation amplifiers have differential
inputs, there must be a return path for the bias
currents. If it is not provided, those currents will
charge stray capacitances, causing the output to
drift uncontrollably or to saturate. Therefore, when
amplifying outputs of "floating" sources, such as
transformers and thermocouples, as well as ac-coupled
sources, there must still be a path from each input
to common, or to the guard terminal. If a dc return
path is impracticable, an isolator must be used.
4-6 INSTRUMENTA TION AMPLIFIERS
COMMON-MODE REJECTION (CMR) is a measure of the
change in output voltage when both inputs are changed by
equal amounts. CMR is usually specified for a full-range commonmode voltage change (CMV) at a given frequency, and a specified
imbalance of source impedance (e.g. ·lkO source unbalance, at
60Hz). CMR is a logarithmic expression of the common-mode
rejection ratio (CMRR): CMR = 20 10glO (CMRR). The commonmode rejection ratio is defined as the ratio of the signal gain, 0,
to the ratio of common-mode signal appearing at the output to
the input CMV.
In most instrumentation amplifiers, the CMR increases with
gain because the front-end configuration does not amplify
common-mode signals, and the amount of common-mode signal
appearing at the output stays relatively constant as the signal
gain (0) increases.
However, at higher gains, amplifier bandwidth decreases. Since
differences in phase shift through the differential input stage
will show up as common-mode errors, CMR becomes more
frequency-dependent at high gains ..
1IIIIIIII ANALOG
WDEVICES
FEATURES
Software Programmable Gain (1, 10, 100, 500)
Low Input Noise 10.211.V pop)
Low Gain Error 10.05% max)
Low Nonlinearity 10.005% max)
Low Gain Drift 110ppmrc max)
Low Offset Drift 1211.Vrc RTI max)
Fast Settling 115p.s @ Gain 100)
Small 16-Pln Metal DIP
Programmable Gain &T/H
DAS Amplifier
AD365 I
AD365 FUNCTIONAL BLOCK DIAGRAM
APPUCATIONS
Digitally Controlled Gain Amplifier
Auto-Gain Renging Amplifier
Wide Dynamic Range Measurement System
Gain Selection/Channel Amplifier
Transducer/Bridge Amplifier
Test Equipment
HIGHLIGHTS
The AD365 is a two stage data acquisition system (DAS) front
end consisting of a digitally selectable gain amplifier followed by
an independent ttacklhold amplifier. The programmable gain
amplifier features differential inputs for excellent common-mode
rejection, high open loop gain for superior linearity, and fast
settling for use in multiplexed high speed systems. The tracklhold
amplifier features high open loop gain for 12-bit compatible
linearity, internal hold capacitor for high reliability, and fast
acquisition time for use with multichannel systems. Both amplifiers
are capable of being used separately and are specified as independent function blocks.
GENERAL DESCRIPTION
The AD365 is comprised of the AD625 monolithic precision
instrumentation amplifier to provide a precision differential
input, the AD7502 monolithic CMOS multip1exer to handle
gain switching, a precision thin-film resistor network, and the
AD585 monolithic track and hold amplifier with internal hold
capacitor.
The input stage provides high common-mode rejection, low
noise, fast settling at all gains, and low drift over temperature.
The gains of I, 10, 100, and 500 are digitally selected with the
two gain control lines which are SV CMOS compatible.
The track and hold amplifier section is ideally suited for high
speed 12-bit applications where fast settling, low noise, and low
sample-ta-hold offset are critical. The TIH mode is controlled
with a single input line which can be tied to the status output
line of the accompanying AID converter.
/NSTRUMENTATION AMPLIFIERS 4-7
SPECIFICATIONS
(typical @ Ys
AD365AM
PGAGAIN
Inaccuracy!
@G=I,10,100
@G=500
Nonlinearity
@G=I,10,100
@G=500
Drift
@G=1
@G=IO,I00,500
PGA OFFSET (May be Nulled at Input and Output)
Input Offset Voltage (RTI)
vs. Temperature
vs. Common-Mode Voltage
vs. Supply Voltage
Output Offset Voltage (RTO)
vs. Temperature
vs. Common-Mode Voltage
vs. Supply Voltage
PGAINPUT
Common- Mode and Differential Impedance
Differential Input Voltage, Linear
Common-Mode Voltage, Linear
Input Stage Noise 0.1 to 10Hz
Input Stage Noise Density @ 1kHz
Bias Current
vs. Temperature
Offset Current
vs. Temperature
Noise Current (0.1 to 10Hz)
PGAOUTPUT
Voltage 2knLoad
Output Impedance
Short Circuit Current
Capacitive Load
Output Stage Noise 0.1 to 10Hz
Output Stage Noise Density @ 1kHz
Guard Voltage
Guard Offset
= ±15Y, RL = 2kO and TA = +25°C unless otherwise specified)
Min
10
4-8 INSTRUMENTA TION AMPLIFIERS
Max
Units
0.02
0.04
0.05
0.1
%
%
0.005
0.01
%
%
1
3
5
10
ppmrC
ppml"C
25
0.1
0.5
1
1
30
60
60
200
2
3.2
10
5
150
316
316
fL V
fLv;oC
fL VN
109 115
12
12 - VDlFF x G/2
0.2
5
50
2
20
60
10
fLV/V
mV
fLv;oC
fLVN
fLVN
nllpF
V
V
fLVP-P
4
PGA DYNAMIC RESPONSE
Small Signal - 3dB
G=1
G=10
G=I00
G=500
Full Power Bandwidth G = 1 @ Vo = 20V pop
Slew Rate
Settling Time to 0.01 %@Vo=20Vp-p
G= 1, 10
G=100
G=500
Gain Switching Time
Overdrive Recovery Time V IN = 15V @ G = 1
PGA DIGITAL INPUTS
Logic Low
Logic High
Current, IINH or lIN!..
Typ
nV/YHZ
50
20
12
0.2
25
500
10
75
(V +IN + V -IN)/2
- 550
nA
pAloC
nA
pArC
pAp-p
V
n
rnA
pF
fLVP-P
nV/YHZ
V
mV
800
400
150
60
kHz
kHz
kHz
kHz
kHz
4
V/fLS
40
8
12
40
10
15
50
fLS
fLS
fLS
fLS
fLS
0.8
+Vs
1
V
V
fLA
1.5
7
0
3.0
0.01
AD365AM
Min
Typ
lOOk
200k
Max
Units
TRACK AND HOLD AMPLIFIER SECTION
TRANSFER CHARACTERISTICS
Open LoopGainVo= 10V,RI =2k
Nonlinearity (II G = + I
Output Voltage RI = 2kll
Capacitive Load
Short Circuit Current
0.005
10
12
100
25
,
TRACK MODE DYNAMICS
Acquisition Time to 0.01% IOV Stcp
20VStep
Small Signal BandWidth - 3dB
Full Power BandWidth (20V p-p)
Slew Rate
2
4
2
120
10
TRACK/HOLD SWITCHING
Aperture Time
Aperture Uncertainty
Switchmg Translent
Settling Time to 2m V
35
0.5
40
0.5
HOLD MODE
DroopRate(II +25°C
from T AMRIEN r to T MAX
Feedthrough
Pedestal, Offset (a + 25°C
Over Temperature
0.3
Doubles/10°C
25
2
3
I
T/H ANALOG INPUT
Bias Current
Over Temperature
Offset Voltage
Over Temperature
vs. Common Mode
vs. Supplies
Input Impedance
Noise Density (II 1kHz
NoiseO.IHzto 10Hz
T/H DIGITAL INPUT CHARACTERISTICS
Logic Lo~ (Hold Mode)
LogJ< High (Track Mode)
Input Current
AD365 POWER REQUIREMENTS
Positive Supply Range
Negative Supply Range
Quiescent Current
Power Dissipation
Warm-Up Time to Specification
Ambient Operating Temperature
Package Thermal Resistance (0,.)
AD365 ABSOLUTE MAXIMUM RATINGS
Positive Supply + V s
NegativeSupply - Vs
Analog Input Voltage
Analog Input Current
Digital Input Voltage
T/H Differential V IN
Storage Temperature
Lead Soldering, 10 Sec
Short Circuit Duration
0.1
0.2
25
100
10 121110
50
10
0
2.0
10
+\1
-\1
12
360
5
-25
3
5
ns
ns
mV
,...S
I
3
V/sec
V/sec
,...VN
mV
mV
2
5
2
3
100
316
nA
nA
mV
mV
,...VN
,...VN
nllpF
nVr,,/Hz
,...Vp-p
0.8
+Vs
50
V
V
,...A
+17
-17
16
550
V
V
rnA
mW
Minutes
°C
°c/W
+85
+ 17
-17
+Vs
+10
+Vs
±30
+ ISO
300
-65
,...S
,...S
MHz
kHz
V/,...s
60
-0.3
+0.3
-Vs
-10
-0.3
VN
%FSR
V
pF
rnA
Vdc
Vdc
V
rnA
V
V
°C
°C
Indefinite
PACKAGEOPTION2
DH-16B
NOTE
1G8m = 10, 100 and 500 are trimmed and tested ratlometnc to G = 1.
2See Section 16 for package outbne information.
Speafications subject to change without DoUce,
INSTRUMENTA TION AMPLIFIERS 4-9
TYPICAL CHARACTERISTICS
(@ +25"unless othenvise noIed)
160
~ lOOk
S,
1000
,
~
I~
!
~
,
120
I
1..0
o
80
I~
100
5
G=1oo, 1000- f----
10
15
20
G=1ooo ........
10
100
1k
FREQUENCY - Hz
..
G~ ..J
1-'"
G=500
-120
sg
-100
~
-8
,
0
G=1
lOOk
100
lk
10k
FREQUENCY - Hz
lOOk
10M
Figure 4. PGA CMRR vs.
Frequency RTI, Zero to 1kIJ
Source Imbalance
0
II I
1000
i~DYnbT~U~r
"'1
I
Glool
G1ooo.
10k
FREQUENCY - Hz
''''
J
'"
0
V
~V
I
~
0
30
40
SO
60
70
80
Figure 7. PGA Offset Voltage,
RTI, Turn On Drift
10
100
'\
100
10k
1k
,,\
1M
lOOk
10M
Figure 6. PGA Gain vs.
Frequency
-12TO 12
,,)dc
-BT08
-4T04
~
~
WARM·UP TIME - Minutes
"~
1
FREQUENCY - Hz
~ I'---~
~D~l
1/
20
1M
•••
lV pop SINE WAVE -
0
lOOk
l"
10
Figure 5. PGA Large Signal
Frequency Response
160
V
=:::-..
~
"
~
1k
10k
Figure 3. PGA Input Current
Noise
~
0
-20
/"
100
lk
FREQUENCY - Hz
100
~
10
100
500
.............. 1"-..'"
-40
..........
10
G=1,100
r-.," ~
~
-60
10
10k
~
~ ..... ~
G-10
0
'
~2-
Figure 2. PGA RTf Noise
Spectral Density vs. Gain
-140
G=100
I
1000
g;
0
1
SUPPLVVOLTAGE_ :!:.V
Figure 1. AD365 Quiescent
Current vs. Supply Voltage
'I "
;;l
§
G=10
g
10
I
0=1
~
01
o
~ 10k
I
1,40
lk
FREQUENCY - Hz
Figure 8. PGA PSRR vs.
Frequency
I
lLl
G=100
G=1ooo
I
II G =l°O
G=1000
G=1
STEP - V
4TO -4
0=500
8TO -8
10k
G=600
I
OUTPUT
~
A
I L11
G=1
1210 -12
lOOk
10
20
30
40
senUNG TIME -
50
60
p.s
Figure 9. PGA Settling Time
to 0.01%
.
40
20
-
1
,
~
Ii
il
10
-
0
r::
-30
-40
-75
-25
25
TEMPERATURE - "c
15
125
Figure 10. PGA Input Bias
Current vs. Temperature
4-10 INSTRUMENTATION AMPLIFIERS
Figure 11. PGA Large Signal
Pulse Response and Settling
Time, G=100
Figure 12. Sample-to-Hold
Settling Time
70
Theory of Operation
The AD365 PGA section uses the AD625 monolithic instrumentation amplifier based on a modification of the classic three-op-amp
approach. Monolithic construction and laser-wafer-trimming
allow the tight matching and tracking of circuit components.
This insures the high level of performance inherent in this circuit
architecture.
A preamp stage (QI-Q4) provides additional gain to Al and A2.
Feedback from the outputs of Al and A2 forces the collector
currents of Q l-Q4 to be constant, thereby, impressing the input
voltage across ~. This creates a differential voltage at the outputs
of Al and A2 which is given by the gain (2R~ + 1) times
the differential portion of the input voltage. The unity gain
subtractor, A3, removes any common-mode signal from the
output voltage yielding a single ended output, VOUT , referred to
the potential at the reference pin.
Digital gain control is provided using the DO and Dl inputs
(pins 14 and 15) which are decoded internally in the gain switching
AD7502 as shown in Figure 15 below. The switch selects the
resistance ~ from the laser trimmed resistor network according
to the following gain select table.
Dl
DO
PGAGAIN
0
0
1
1
0
1
0
1
1
10
100
500
12kn
-IN
12k!!
O--'III,.,...-+------.--w.-{
F0333
FD333
-v,
Figure 14. Input Protection Circuit for PGA
necessary to protect the PGA under all overload conditions at
any gain. The diodes to the supplies are only necessary if input
voltages outside of the range of the supplies are encountered.
REFERENCE TERMINAL
The reference terminal may be used to offset the output by up
to ± 2V. This is useful when the load is "floating" or does not
share a ground with the rest of the system. It also provides a
direct means of injecting a precise offset. It must be remembered,
however, that the total output swing, to be shared between
signal and reference offset, should be ± 10 volts (from ground).
In the AD625, a reference source resistance will unbalance the
CMR trim by the ratio of 10kn1RREF • For example, if the reference
source impedance is In, CMR will be reduced to 80dB (10k!llln
= 8OdB). An operational amplifier may be used to provide the
low impedance reference point as shown in Figure 15. The
input offset voltage characteristics of that amplifier will add
directly to the output offset voltage performance of the instrumentation amplifier.
GAIN
DRIVE
~R'
I
I
FD333
The PGA section reference terminal must be presented with
nearly zero impedance. Any significant resistaIice, including
those caused by PC layouts or other connection techniques, will
increase the gain of the noninverting signal path, thereby, upsetting
the common-mode rejection of the In-Amp. Inadvertent thermocouple connections created in the sense and reference lines
should also be avoided as they will directly affect the output
offset voltage and output offset voltage drift.
+v,
50n
-IN C>-''W'O...... - ;
FD333
12kU
12kU
+IN o--'III,.,...~-----t--w.-<:'J
~""""""'I'oIV--o+IN
son
RG
L-~----G~~N~G~A~'N----t-~
SENSE
SENSE
-v,
Figure 13. Simplified Circuit of the PGA
INPUT PROTECTION
Differential input amplifiers frequently encounter input voltages
outside of their linear range of operation. There are two considerations when applying input protection for the PGA; I) that
continuous input current must be limited to less than lOrnA and
2) that input voltages must not exceed either supply by more
than one diode drop (approximately 0.6V @ 25"C).
Under differential overload conditions there is (~ + 300)n in
series with two diode drops (approximately 1.2V) between the
plus and minus inputs, in either direction. With no external
protection and ~ very small (i.e., 80n @ G = 500), the maximum
overload voltage the PGA can withstand, continuously, is approximately ± 5V. Figure 14 shows the external components
-v. <>-'-"'-t::-----,---,-::---------------------,
OATA
INPUTS
Figure 15. Software Controllable Offset
INSTRUMENTATION AMPLIFIERS 4-11
-- ------- - - - - - - - -
•
The circuit of Figure IS also shows a CMOS DAC operating in
the bipolar mode and connnected to the reference terminal to
provide software controllable offset adjustments. The total offset
range is equal to ± (VR FP2 x R5~). To be symmetrical about
OV, R3 must be equal to 2 x R..
The offset per bit is equal to the total offset range divided by
2N , where N = number of bits of the DAC. The range of offset
for Figure 15 is ± 120mV, and the offset is incremented in steps
of 0.9375mV/LSB.
INPUT AND OUTPUT OFFSET VOLTAGE
Offset voltage specifications are often considered a figure of
merit for instrumentation amplifiers. While initial offset may be
adjusted to zero, shifts in offset voltage due to temperature
variations will cause errors. Intelligent systems can often correct
for this factor with an auto-zero cycle, but this requires extra
circuitry.
Offset voltage and offset voltage drift each have two components:
input and output. Input offset is that component of offset that
is generated at the input stage. Measured at the output it is
directly proportional to gain, i.e., input offset as measured at
the output at G = 100 is 100 times greater than that measured
at G = 1. Output offset is generated at the output and is constant
for all gains. Input errors dominate at high gains and output
errors dominate at low gains.
cables are used to minimize noise. This technique can create
common-mode rejection errors unless the shield is properly
driven. Figure 17 shows active data guards which are configured
to improve ac common-mode rejection by "bootstrapping" the
capacitances of the input cabling, thus minimizing differential
phase shift.
GROUNDING
In order to isolate low level analog signals from a noisy digital
environment, many data-acquisition components have two or
more ground pins. These grounds must eventually be tied together
at one point. It would be convenient to use a single ground line,
however, current through ground wires and pc runs of the circuit
card can cause hundreds of millivolts of error. Therefore, separate
ground returns should be provided to minimize the current flow
from the sensitive points to the system ground (see Figure 18).
Since the AD365 output voltage is developed with respect to the
potential on the reference terminal, it can solve many grounding
problems.
By separating these errors, one can evaluate the total error independent of the gain. For a given gain, both errors can be combined
to give a total error referred to the input (RTI) or output (RTO)
by the following formula:
Total Error RTI = input error
+
(output error/gain)
Total Error RTO = (Gain x input error)
+
output error
The AD365 provides for input offset voltage adjustment (see
Figure 16). This simplifies nulling in very high precision applications and minimizes offset voltage effects in switched gain
applications. In such applications the input offset is adjusted
first at the highest programmed gain, then the output offset is
adjusted at G = 1. If only a single null is desired, the input
offset null shonld be used. The most additional drift when using
only the input offset null is 0.9j.t.VfC, RTO.
Output offset adjustment is normally provided by the AID converter offset adjustment which will compensate for the output
offset of the PGA, offset of the T/H amplifier, and offset of the
AID.
Figure 18. Basic Grounding Practice
GROUND RETURNS FOR BIAS CURRENTS
Input bias currents are those currents necessary to bias the
input transistors of a dc amplifier. There must be a direct return
path for these currents, otherwise they will charge external
capacitances, causing the output to drift uncontrollably or saturate.
Therefore, when amplifying "floating" input sources such as
transformers, or ac-coupled sources, there must be a dc path
from each input to ground as shown in Figure 19.
+v,
]
Figure 16. Input Voltage Offset Adjustment
COMMON-MODE REJECTION
In an instrumentation amplifier, degradati~n of common-mode
rejection is caused by a differential phase shift due to differences
in distributed stray capacitances. In many applications shielded
Figure 17. Common-Mode Shield Driver
4-12 INSTRUMENTATION AMPLIFIERS
Figure 19a. Ground Returns for Bias Currents with
Transformer Coupled Inputs
'
+v.
Figure 19b. Ground Returns for Bias Currents with ac
Coupled Inputs
AUTO-ZERO CIRCUITS
In many applications it is necessary to maintain high accuracy.
At room temperature, offset effects can be nulled by the use of
offset trimpots. Over the operating temperature range, however,
offset nulling becomes a problem. For these applications the
auto-zero circuit of Figure 20 provides a hardware solution.
+v,
Figure 21. Pictorial Showing Various TIH Characteristics
TRACK-TO-HOLD TRANSITION
The aperture delay time is the time required for the track-and-hold
amplifier to switch from track to hold. Since this is effectively a
constant, it may be tuned out. If however, the aperture delay
time is not accounted for then errors of the magnitude as shown
in Figure 22 will result.
%
112 BIT
8 BITS
.'"
;,
V
,
%
Figure 20. . Auto-Zero Circuit
1/2 BIT
\\
10 BITS
OTHER CONSIDERATIONS
One of the more overlooked problems in designing ultra-low-drift
dc amplifiers is thermocouple induced offset. In a circuit comprised
of two dissimilar conductors (i.e., copper, kovar), a current
flows when the two junctions are at different temperatures.
When this circuit is broken, a voltage known as the "Seebeck"
or thermocouple emf can be measured. Standard IC lead material
(kovar) and copper form a thermocouple with a high thermoelectric
potential (about 3SI-LV°C). This means that care must be taken
to insure that all connections (especially those in the input circuit
of the AD36S) remain isothermal. This includes the input leads
(1, 2). In addition, the user should also avoid air currents over
the circuitry since slowly fluctuating thermocouple voltages will
appear as "flicker" noise.
The base emitter junction of an input transistor can rectify outof-band signals (i.e., RF interference). When amplifying small
signals, these rectified voltages act as small dc offset errors. In
the case of a resistive transducer, a capacitor across the input
working against the internal resistance of the transducer may
suffice to provide an RC filter. These capacitances may also be
incorporated as part of the external input protection circuit (see
section on input protection). As a general practice every effort
should be made to match the extraneous capacitance at pins I
and 2, to preserve high ac CMR.
THEORY OF OPERATION - TIH SECTION
In sampled data systems there are a number of limiting factors
in digitizing high frequency signals accurately. Figure 21 shows
pictorially the track-and-hold errors that are the limiting factors.
In the following discussions of error sources the errors will be
divided into the following groups: 1. Track-to-Hold Transition,
2. Hold Mode and 3. Hold-to-Track Transition.
IT
..,'"...
V
112 BIT
~
12 BITS
,.,
!I,
112 BIT
14 BITS
0001
V
~~UREDELAY
(35nsl
V
..
,
1k
10k
SIGNAL FREQUENCY - Hz
lOOk
Figure 22. Aperture Delay Error vs. Frequency
To eliminate the aperture delay as an error source the track-to-hold
command may be advanced with respect to the input signal.
Once the aperture delay time has been eliminated as an error
source then T IH trigger uncertainty/jitter and internal aperture
jitter which are the variations in aperture delay time from sampleto-sample remain. The aperture jitter is a true error source and
must be considered. The aperture jitter is a result of noise within
the switching network which modulates the phase of the hold
command and is manifested in the variations in the value of the
analog input that has been held. The aperture error which results
from this jitter is directly related to the dV/dt of the analog
input.
The error due to aperture jitter is easily calculated as shown
below. The error calculation takes into account the desired
accuracy corresponding to the resolution of the N -bit AID
converter.
F
m~
=
2-(N+l)
-~~(Afp~e~rt~m--e'Jl"tt~e'r)
INSTRUMENTATION AMPLIFIERS 4-13
•
For an application with a 12-bit AID converter with a 10V full
scale to a 1I2LSB error maximum:
2-(12+1)
Fmax =
"IT
(0.5 x 10- 9)
that a sampled data system must sample, convert and acquire
the next point at a rate at least twice the signal frequency. Thus
the maximum input frequency is equal to
= 77.7kHz
f
MAX
Track-to-hold offset is caused by the transfer of charge to the
holding capacitor via the gate capacitance of the switch when
switching into hold. Since the gate capacitance couples the
switch-control voltage applied to the gate on to the hold capacitor,
the resulting track-to-hold offset is a function of the logic level
applied to the gate and the change in the gate capacitance over
temperature.
HOLD MODE
In the hold mode there are two important specifications that
must be considered; feedthrough and the droop rate. Feedthrough
errors appear as an attenuated version of the input at the output
while in the hold mode. Hold-Mode feedthrough varies with
frequency, increasing at higher frequencies. Feedthrough is an
important specification when a track and hold follows an analog
multiplexer that switches among many different
channels.
Hold-mode droop rate is the change in output voltage per unit
of time while in the hold mode. Hold mode droop originates as
leakage from the hold capacitor, of which the major leakage
current contributors are switch leakage current and bias current.
The rate of voltage change on the capacitor dV/dt is the ratio of
the total leakage current IL to the hold capacitance CH •
2(TACQ
+
I
T CONV
+
TAP)
Where T ACQ is the acquisition time of the sample-to-hold
amplifier, TAP is the maximum aperture time (small enough to
be ignored) and T CONV is the conversion time of the AID
converter.
DATA ACQUISITION SYSTEMS
The fast acquisition time of the AD365 when used with a high
speed AID converter allows accurate digitization of high frequency
signals and high throughput rates in multichannel data acquisition
systems. The AD365 can be used with a number of different
AID converters to achieve high throughput rates. Fignres 23
and 24 show the use of an AD365 with the AD578 and
AD574A.
T
dVoUT
= IL(pA)
CH(PF)
Droop Rate = ~ (VoltS/Sec)
c~~~:~6 o-----~---------'
For the AD365 in particular;
100pA
.
Droop Rate = IODpF = IV/sec maxnnum
Figure 23. AID Conversion System, 117.6kHz Throughput
58. 8kHz Max Signal Input
Additionally the leakage current doubles for every 1DOC increase
in temperature above 25°C; therefore, the hold-mode droop rate
characteristic will also double in the same fashion.
Since a track and hold is used typically in combination with an
AID converter, then the total droop in the output voltage has to
be less than 1I2LSB during the period of a conversion. The
maximum allowable signal change on the input of an AID converter
is:
, 'V
a
_ Full Scale Voltage
max z(15 ±o 4G)ppmtC
o 1% max
0.2% max
±(3 ±O OSG)ppm/C
fIOV, ±lOmAmm
±lOV@SmAmm
om
>2MHz
300kHz
200kHz
40kHz
75kHz
26kHz
24kHz
6kUol
100kHz
lOV1tls
7~s
S~s
10~s
3SlA s
SOIA S
lOps
3mV max (2mV typ)
IS~VtC max (7/lYtC typ)
1 OmV max (0 'mV typ)
2p.V/Q C max
l~V/%
=::f~~!!~~~~J~ typ)
200mV max (30mV ty~)
!SOlAvfC max (SO",ViC typ)
OOOSVoso /%
SOnAmax
lnAfCmu
.
lOOmVmax
7Sp.VfCmax
40nA max
~oopAfcmax
2%IV
20nAmax
2S0pAfCmax
lOnAmax
12SpAtCmax
l x 10' UII1.8pF
6 x 1O,oU1I3 OpF
±lOV
lOY
Vs ±lSV
74dB mm (BOdB typ)
94dB mm (lOOdB typ)
104dB min (1l4dB typ)
110dB mm (120dB typl
G", 1000
10MU
±lOV
I
POWER SUPPLY
Operaung Voltage Range
quiescent Supply CUrrent
±SV to ±lBV
SmA max
TEMPERATURE RANGE
SpeCified Performance
OperatlDg
,
Storage
Oto +70o C
-2SoC to +SSOC
-6S o C to +lSOoC
PACKAGE OPTION'
Ceramic (D-14)
AD521JD
4-16 INSTRUMENTATION AMPLIFIERS
AD521W
1 to 1000
G= Rs/ReV/V
('0 25-0 004G)%
NOISE
Voltage RTO (p-p)@O 1Hz to 10Hz (Note 10)
RMS RTO, 10Hz to 10kHz
Input Current, rms, 10Hz to 10kHz
REFERENCE TERMINAL
Bias Current
Input ResJstance
Voltage Range
Gam to Output
NOTES
1 See Section 16 for package outline mfonnatlOn,
·Speafic:auons same as ADS21]D.
·"SpeClflCLtions same IS ADS21KD
Speclficadons subject to change Without notice
AD521KD
JO SG 2 + 22S2J.lV
(I 2G) + (50) ~V
lSpA (rms)
3~A
.
'.
-SSOC to +12S oC
_SSoC to +12SoC
AD521KD
ADS21LD
ADS21SD
Applying the AD521
NOTES:
1. Gains below 1 and above 1000 are realized by simply adjusting the gain setting resistors. For best results, voltage at
either input should be restricted to ±lOV for gains equal to
or less than 1.
2. Nonlinearity is defined as the ratio of the deviation from
the "best straight line" through a full scale output range of
±9 volts. With a combination of high gain and ±10 volt output
swing, distortion may increase to as much as 0.3%.
3. Full Peak Response is the frequency below which a typical
amplifier will produce full output swing.
4. Differential Overload Recovery is the time it takes the amplifier to recover from a pulsed 30V differential input with 15V
of common mode voltage, to within 10mV of final value. The
test input is a 30V, lOllS pulse at a 1kHz rate. (When a differential signal of greater than 11 V is applied between the inputs,
transistor clamps are activated which drop the excCS!' input
voltage across internal input resistors. If a continuous overload
is maintained, power dissipated in these resistors causes temperature gradients and a corresponding change in offset voltage,
as well as added thermal time constant, but will not damage
the device.)
5. Common Mode Step Recovery is the time it takes the amplifier to recover from a 30V common mode input with zero
volts of differential signal to within 10mV of final value. The
test input is 30V, lOllS pulse at a 1kHz rate. (When a com-
mon mode signal greater than Vs -o.5V is applied to the
inputs, transistor clamps are activated which drop the excessive
input voltage across internal input resistors. Power dissipated
in these resistors causes temperature gradients and a corresponding change in offset voltage, as well as an added thermal time
constant, but will not damage the device.)
6. Output Offset Voltage versus Power Supply Change is a
constant 0.005 times the unnulled output offset per percent
change in either power supply. If the output offset is nulled,
the output offset change versus supply change is substantially
reduced.
7. Differential Input Impedance is the impedance between the
two inputs.
8. Common Mode Input Impedance is the impedance from
either input to the power supplies.
9. Maximum Input Voltage (differential or at either input) is
30V when using ±15V supplies. A more general specification is
that neither input may exceed either supply (even when
Vs = 0) by more than 15V and that the difference between the
two inputs must not exceed 30V. (See also Nares 4 and 5.)
10. O.IHz to 10Hz Peak-ta-Peak Voltage Noise is defined as
the maximum peak-to-peak voltage noise observed during 2
of 3 seperate 10 second periods with the test circuit of Figure8.
+y
DESIGN PRINCIPLE
Figure 1 is a simplified schematic of the AD521. A differential
input voltage, VIN, appears across RG causing an imbalance in
the currents through Ql and Ch, ~I=VIN/RG' That imbalance
is forced to flow in Rs because the collector currents of Q3
and C4 are constrained to be equal by their biasing (current
mirror). These conditions can only be satisfied if the differential voltage across Rs (and hence the output voltage of the
AD521) is equal to ~I X Rs. The feedback amplifier, AFB
~:::rm~at function. Therefore, VOUT = V~
~=~
OR-~"~
X Rs or
r-----+--I-----98.NSE
VIN = RG'
OUT
I~
+IX
I.
CURRENT MIRROR
+
+1
,
~"
....
y-
Figuffl 1. Simplified AD521 Schematic
INSTRUMENTATION AMPLIFIERS 4-17
APPLICATION NOTES FOR THE AD521
These notes ensure the AD521 will achieve the high level of
performance necessary for many diversified IA applications.
1. Gains below 1 and above 1000 are realized by adjusting
the gain setting resistors as shown in Figure 2 (the resistor,
Rs between pins 10 and 13 should remain 100kO ±IS%,
see application note 3). For be~t results, the input vOltage
should be restricted to ±10V especially for gain equal to
or less than 1.
2. Provide a return path to ground for input bias currents. The
ADS21 is an instrumentation amplifier, not an isolation
amplifier. When using a thermocouple or other "floating"
source, this return path may be provided directly to ground
or indirectly through a resistor to ground from pins 1 andl
or 3, as shown in Figure 3. If the return path is not provided, bias currents will cause the output to saturate. The
value of the resistor may be determined by diViding the
maximum allowable common mode voltage for the application. by the bias current of the instrumentation amplifier.
RS
a}. Trantdormer Coupled, Direct Return
Rs
V+
b). Thermocouple, Direct Return
+IN
RS
>""-0 OUTPUT
-IN
OUTPUT
' - - - - 0 SIGNAL
I
COMMON
I
IL
V-
I
I
_____ ..JI
OPTIONAL
OFFSET
TRIM
GAIN VALUE OF Ro
0.1
lMO
1
lOO1cO
10
100
1000
10k0
lkO
1000
c). AC Coupled, Indirect Return
Figure 3. Ground Returns for "Floating" Transducers
Figure 2. Operating Connections for AD521
3. The resistors between pins 10 and 13, (RSCALE) must equal
l00kO ±IS% (Figure 2).lf RSCALE is too low (below 85kO)
the output swing of the ADS21 is reduced. At values below
80kO and above 120kO the stability of the AD521 may be
. impaired.
4. Do not exceed the allowable input signal range. The linearity of the AD521 decreases if the inputs are driven within
5 volts of the supply rails, particularly when the device is
used at a gain less than 1. To avoid this possibility, attenuate the input signal through a resistive divider network and
use the AD521 as a buffer, as shown in Figure 4. The resistor R/2 matches the impedance seen by both AD 521 inputs so that the voltage offset caused by bias currents will
be minimized.
4-18 INSTRUMENTATION AMPLIFIERS
1.
2.
INCREASE Ro TO PICK UP GAIN LOST BY R
DIVIDER NETWDRK
INPUT SIGNAL MUST BE REDUCED IN
PROPORTION TO POWER SUPPLY VOLTAGE LEVEL
Figure 4. Operating Conditions for VIN""'VS= 10V
5. Use the compensation pin (pin 9) and the applicable compensation circuit when the amplifier is required to drive a
capacitive load. It is worth mentioning that coaxial cables
can "invisibly" provide such capacitance since many popular coaxial cables display capacitance in the vicinity of 30pF
per foot.
This compensation (bandwidth control) feature permits the
user to fit the response of the AD 5 21 to the particular application as illustrated by Figure 5. In cases of extremely high
load capacitance the compensation circuit may be changed
as follows:
1.
2.
3.
4.
Reduce 680S"l to 24S"l
Reduce 330S"l to 7.5S"l
Increase 1000pF to 0.1J.1F
Set Cx to 1000pF if no compensation was originally
used. Otherwise, do not alter the original value.
This allows stable operation for load capacitances up to
300OpF, but limits the slew rate to approximately 0.16V/J.ls.
6. Signals having frequency components above the Instrumentation Amplifier's output amplifier closed-loop bandwidth
will be transmitted from V- to the output with litde or no
attenuation. Therefore, it is advisable to decouple the Vsupply line to the output common or to pin 11.1
V+
GAIN=~
+0------;.;
----,
RG
errors into two categories. Those errors which simply add to
the output signal and are unaffected by the gainlcan be classified as output errors. Those which act as if they are associated
with the input signal, such that their effect at the output is
proportional to the gain, can be classified as input errors.
As an illustration, a typical AD521 might have a +30mV output
offset and a -o.7mV input offset. In a unity gain configuration,
the total output offset would be +29 .3mV or the sum of the
two. At a gain of 100, the output offset would be -40mV or:
30mV + 100(-o.7mV) = -40mV.
By separating these errors, one can evaluate the total error
independent of the gain settings used, similar to the situation
with the input offset specifications on an op amp. In a given
gain configuration, both errors can be combined to give a total •
error referred to the input (R.T.I.) or output (R.T.O.) by the
•
following formula:
Total Error R.T.I. = input error + (output error/gain)
Total Error R.T.O. = (Gain x input error) + output error
The offset trim adjustment (pins 4 and 6, Figure 2) is associated primarily with the output offset. At any gain it can be
used to introduce an output offset equal and opposite to the
input offset voltage multiplied by the gain. As a result, the
total output offset can be reduced to zero.
As shown in Figure 6, the gain range on the AD521 can be
extended considerably by adding an attenuator in the sense
terminal feedback path (as well as adjusting the ratio, Rs/RG)'
Since the sense terminal is the inverting input to the output
amplifier, the additional gain to the output is controlled by
Rl and R2' This gain factor is 1 + R2/Rl'
I
Rs
I
I
3300
:
v,
l000pF :
____ ...I
>'-'p-o VOUT
V-
1
Cx = 1OO1rft when ft is the desired bandwidth.
(ft in kHz, Cx in J.lF)
Figure 5. Optional Compensation Circuit
INPUT OFFSET AND OUTPUT OFFSET
When specifying offsets and other errors in an operational
amplifier, it is often convenient to refer these errors to the
inputs. This enables the user to calculate the maximum error
he would see at the output with any gain or circuit configuration. An op amp with 1mV of input offset voltage, for
example, would produce 1V of offset at the output in a gain
of 1000 configuration.
- ...- - - - - - -...-0 OUTPUT COMMON
Figure 6. Circuit for utilizing some of the unique features of the
AD521. Note that gain changes introduced by changing R1 and
R2 will have a minimum effect on output offset if the offset is
carefully nulled at the highest gain setting.
In the case of an instrUmentation amplifier, where the gain is
controlled in the amplifier, it is more convenient to separate
1
For further details, refer to "An I.C. User's Guide to Decoupling,
Grounding, and Making Things Go Right for a Change," by A.
Paul Brokaw. This application note is available from Analog Devices
without charge upon request.
INSTRUMENTATION AMPLIFIERS 4-19
Where offset errors are critical, a resistor equal to the parallel
combination of Rl and R2 should be placed between pin 11
and VREF. This minimizes the offset errors resulting from the
input current flowing in Rl and R2 at the sense terminal. Note
that gain changes introduced by changing the RI/R2 attenua·
,tor will have a minimum effect on output offset if the offset
is carefully nulled at the highest gain setting.
When a predetermined output offset is desired, VREF can be
placed in series with pin 11. This offset is then multiplied by
the gain factor 1 + R2/Rl as shown in the equation of
Figure 6.
RG
VIN
VCM
L _ ...{ )__________ + __.,
Figure 7. Ground loop elimination. The reference input, Pin 11,
allows remote referencing of ground potential. Differences in
ground potentials are attenuated by the high CMRR of the
AD521.
+15V---1.......- - - - - -.....- - - - - - - - - - - - . . . . . . . . . . ,
aoon
o 15p.F
'OOk
COMMON - -.....-
11
O.25J,1F
----"-l
.....
~F
10Mn
3000
-+------.....----+----....;-+--...J
.'5V _ _......
~---------~~---......-
.....- - - - - - - - - -......-_¢COMMON
Figure 8. Test circuit for measuring peak to peak noise in the
bandwidth O. 1Hz to 10Hz. Typical measurements are found by
reading the maximum peak to peak voltage noise of the device
under test (D. U. T.) for 3 observation periods of 10 seconds each.
4-20 INSTRUMENTA TION AMPLIFIERS
r.'ANALOG
L.IIII DEVICES
FEATURES
Performance
Low Drift: 2.0p.vfc (AD522B)
Low Nonlinearity: 0.005% (G = 100)
High CMRR: >11OdB (G =1000)
Low Noise: 1.5p.V .p-p (0.1 to 100Hz)
Low Initial VOS: 100p.V (AD522B)
Versatility
Single·Resistor Gain Programmable: 1 .;; G .;; 1000
Output Reference and Sense Terminals
Data Guard for Improving ae CMR
Value
Internally Compensated
No External Components except Gain Resistor
Active Trimmed Offset, Gain, and CMR
PRODUCT DESCRIPTION
The ADS22 is a precision IC instrumentation amplifier designed
for data acquisition applications requiring high accuracy
under worst-case operating conditions, An outstanding com·
bination of high linearity, high common mode rejection, low
voltage drift, and low noise makes the ADS22 suitable for
use in many 12-bit data acquisition systems.
An instrumentation amplifier is usually employed as a bridge
amplifier for resistance transducers (thermistors, strain gages,
etc,) found in process control, instrumentation, data processing,
and medical testing. The operating environment is frequently
characterized by low signal-to·noise levels, fluctuating temperatures, unbalanced input impedances, and remote location which
hinders recahbration.
The ADS 22 was designed to provide highly accurate signal conditioning under the~e severe conditions. It provides output offset voltage drift of less than lOIlV I" C, input offset voltage drift
of less than 2.0IlV/oC, CMR above SOdB at unity gain (llOdB
at G = 1000), maximum gain nonlinearity of 0.001% at G = 1,
and typical input impedance ~f 109 n.
High Accuracy Data Acquisition
Instrumentation 'Amplifier
AD522 I
ADS22 FUNCTIONAL BLOCK DIAGRAM
14-PIN Drp
11l===:::;-li41 R GAIN
DATA GUARD
SENSE
This excellent performance is achieved by combining a proven
circuit configuration with state-of-the-art manufacturing technology which utilizes active laser trimming of tight-tolerance
thin-film resistors to achieve low cost, small size and high reliability. This combination of high value with no-compromise performance gives the ADS22 the best features of both monolithic and modular instrumentation amplifiers, thus providing
extremely cost-effective precision low-level amplification.
The ADS22 is available in three versions with differing accuracies and operating temperature ranges; the "A", and "B"
are specified from -25°C to +SSoC, and the "s" is guaranteed over the extended aerospace temperature range of -5 S° C
to +12S oC. All versions are packaged in a 14-pin DIP and are
supplied in a pin configuration similar to that of the popular
ADS21 insttumentation amplifier.
INSTRUMENTATION AMPLIFIERS 4-21
SPECIFICATIONS1 (typical@+Vs= ±15V, RL = 2kn &.TA =+25°C unless otherwise specified)
MODEL
GAIN
Gam Equatl~n
Gam Range
Equation Error
G=I
ADS22AD
ADS22BD
Rg
1 to 1000
02%max
D.05%max
1.0% max
02%max
G=l
0005%
0001%
G '" 1000
001%
0005%
G
= 1000
AD522SP
1 + ~_!.105)
Nonlmeanty, max (see Fig 4)
vs Temp, max
G=I
G = 1000
OUTPUT CHARACTERISTICS
Output Ratmg
2ppmtC (lppm/C typ)
sOppmfe (2SppmfC typ)
±tOV@SmA
DYNAMIC RESPONSE (see Fig 6)
Small Signal (-3dB)
G", 1
G= 100
300kHz
3kHz
15kHz
o 1V/.us
OSms
5ms
2ms
Full Power GBW
Slew Rate
Settlmg Time to 0 1%, G '" 100
toOOl%,G= 100
to 0 01 %, G '" 10
toDOl%,G= 1
OSms
VOLTAGE OFFSET
Offsets Referred to Input
Initial Offset Voltage
(adjustable to zero)
G
\'5
=:
±400"..!V max (±200IlV typ)
1
Temperature, max (see Fig 3)
y/oC(±1O,.Nfc typ)
G", 1
r; = 1000
± 50.u
I120dB typ)
80dS (88dB typ)
NOISE
Voltage NOise, RTI (see Fig 4)
o 1Hz to 100Hz (p-p)
G=I
G;: 1000
10Hz to 10kHz (rms)
G=I
TEMPERATURE RANGE
SpeCified Performance
Operatmg
Storage
_25°C to +8S oC
_SSoC to +12S oC
_65°C to +IS0oC
POWER SUPPLY
Power Supply Range
QUiescent Current, max @ ± 15 V
±(S to l8)V
±10mA
±8mA
AD522AD
AD522BD
PACKAGE OPTIONS 2
Ceramlc 3 (DH-14A)
Metal (D~·14B) _
NOTES
I Speclfic8tlODsguaratlteed after 10 nunute warm-up.
J See Section 16 for package outline information.
3 Analog Devlca; reserves the nght to ship metal package
of the standard ceramic packages for A and B grades.
75dB (90dB typ)
90dB (IIOdB typ)
100dB (I20dB typ)
loodB (>120dB typ)
15~V
I
5~V
AD522SD
In
heu
·Speuf ..;:atlons same as AD522A
"SpeCifICatiOnS same as AD522B
SpeCifIcations subject to change without notIce
4-22 INSTRUMENTATION AMPLIFIERS
Applying the AD522
GENERAL APPLICATION CONSIDERATIONS
Figure 1 illustrates the ADS22 wiring configuration when used
in a typical bridge amplifier application. In any low-level, high
impedance, noise-dominated environment, proper shielding and
grounding are requisite for optimum performance; a recommended technique is shown.
sensing. These points can also be used to trim the device CMR,
add an output booster, or to offset the output to a reference
level. These applications are illustrated in following sections.
It is good practice to place RG within several inches of the
ADS22. Longer leads will increase stray capacitance and cause
phase shifts that will degrade CMR at higher frequencies. For
frequencies below 10Hz, a remote RG is generally acceptable;
no stability problems are caused. Bear in mind that a leakage
impedance of 200MO between RG pins will cause an 0.1 % gain
error at G = 1. Unity gain is not trimmable.
TYPICAL APPLICATION AND ERROR BUDGET ANALYSIS
(See Figure 1 and Table I)
A floating transducer with a 0 to 1 volt output has a 1kO source
imbalance. A noisy environment induces a one volt 0 to 60Hz
common mode signal in the ground return. This signal must be
amplified to interface with a data acquisition system calibrated
for a 0 to 10 volt signal range. The operating temperature range
is 0 to +SOoC and an ADS22B is to be used. Table 1 lists
error sources and their effect on system accuracy.
The total effect on absolute accuracy is less than ±0.2%, allowing
adjustment-free 8-bit operation. In computer or microprocessor controlled data-acquisition systems, automatic recalibration
can nullify gain and offset drifts leaving noise, distortion and
CMR as the only error sources. In this case, full 12-bit operation is achieved.
NOTES
1 GAIN RESISTOR RG SHOULD BE ....6ppm1 C (V/SHAY TYPE RECOMMENDED)
2 SHIELDED CONNECTIONS TO Rc RECOMMENDED WHEN MAXIMUM SYSTEM BANDWIDTH
AND AC CMR IS REQUIRED, ANeWHEN Rc IS LOCATED MORE THAN SIX INCHES FROM
AD522 NO INSTABILITIES ARE CAUSED BY REMOTE RG lOCATIONS WHEN NOT U&ED
THE DATA GUARD PIN CAN BE LEFT UNCONNECTED
3 POWER SUPPLY FILTERS ARE RECOMMENDED FOR MINIMUM NOISE IN NOISY ENVIRON_
MENTS
4 NO TRIM REQUIRED FOR MOST APPLICATIONS IF REQUIRED, A 1OkSl, ~I C, 25 TURN
TRIM POT (SUCH ASVISHAV 1202 Y lOki IS RECOMMENDED
Figure 1. Typical Bridge Application
Direct coupling of the ADS22 inputs makes it necessaty to
provide a signal ground return for input amplifier bias currents.
This can be achieved by direct connection as shown, or through
an indirect path of less than 1MO resistance such as other system interconnections.
To minimize noise, shielding should be provided for the input
leads and gain resistor connections. A passive data guard is provided to improve ac common mode rejection by "bootstrapping" the capacitance of the input cabling, thus minimizing
differential phase shift. This will also reduce degradation of
system bandwidth.
Balanced design eliminates the need for external bypass capacitors for most applications. If, however, the power supplies
are remotely located (farther than 10 feet or so) or if they are
likely to carry more than a few millivolts of noise, local filtering will enable the user to retain optimal performance.
Reference and sense pins are provided to permit remote load
Error Source
Gam Nonlinearity
Voltage Dnft
Gain Errors: Absolute gain errors can be nulled by trimming
RG. Gain drift is a linear effect, not detrimental to resolution
and is caused by the change in value of internal resistors over
the operating temperature range. An "intelligent" system can
correct for these errors with an automatic calibration cycle.
Gain nonlinearity never exceeds 0.002% at G = 10.
Offset Drift & Pins Current Errors: Special care has been taken
in the design of the ADS22 input stage to minimize offset drift.
Unless transducer impedances are unbalanced by more than
2kO, errors caused by offset current drift are negligible compared to offset voltage drift. Although initial offset voltages
are laser-nulled for most applications, provisions have been
made to allow further adjustment to correct for initial system
offset. In this example, all offset drifts amount to ±0.014%
and do not effect resolution (can be corrected with an automatic calibration cycle).
CMR and Noise Errors: Common mode rejection and noise
performance of instrumentation amplifiers are critical because
Effect on Absolute
Accuracy, % of F .5.
Specification
±0.002% max, G = 10
(from Spec Sheet and Fig 4)
25p.vfc
Gam
+ 2 0 vfc= 4 5 V/'C
Jl
/.l
±0.002
Effect on Resolution
% of F.s.
±0002
±0.01l
R T.!. = 0 00055%fC
(from Spec Sheet)
86dB (from Spec. Sheet, CMR vs F
G, typical curve)
±0005
±O 005
15p.V (p-p) R T 0 (from Spec Sheet,
NOise vs G typical curve)
±00015
±O 0015
Offset Current
Drift
±SOpA/oC x lk source Imbalance
(Spec Sheet) = ±5Op.V/'C =
±125p.V R T.!.
±0.000125
Gam Dnft
(add 10ppm/'C for
external RG)
60ppm/'C
(Spec. Sheet)
±0.15
CMR
'YS.
NOise, R.T.O.
(0
1 to 100Hz)
Table I. Error Sources
INSTRUMENTA TlON AMPLIFIERS 4-23
these errors can not be corrected by calibration. Common mode
rejection of the AD522 is active laser-trimmed to the limits of
thin-film resistor stability. Further trimming could improve
CMR on a short term basis, but regular readjustment would be
necessary to maintain this improvement (see Figure 2). In this
example, untrimmed CMR and noise cause a total error of
±0.0065% of full scale and are the major contributors to resolution error.
,t::i
G ~ 1000
r-G~ 100
G~
---r--r-.
10
~.'
I
,
--I--r-
TYPICAL CMR, AD522B
lkll SOURCE IMBALANCE
r- ± COV:LT)
"COMMOIIIMOOEINPUTVOLTAGE
NOTE
oI
~~~~~~;~ ~:E~~~~;e~,~~iSc~A:
,
~5~:!NA~~D/REarENCY FIOR
1
II
10
1
100
Ion
Figure 2. Optional CMR Trim
Figure
PERFORMANCE CHARACTERISTICS
Offset Voltage and Current Drift: The AD522 is available in
four drift selections. Figure 3 is a graph of maximum RTO offset voltage drift vs. gain for all versions. Errors caused by offset voltage drift can thus be determined for any gain. Offset
current drift will cause a voltage error equal to the product of
the offset current drift and the source impedance unbalance.
5.' Common Mode Rejection vs.
,
,
TVJCAL SMALL ISIGNAL
FREOUENCY RESPONSE
G",100
:to 1%
RESPONSE
ERROR
0
,
II
G~10~
G~10
RE-SPONSE
ERROR
-".L " "
'"
""",
G=l
'"
~,
j
to
~
If
~ 2~-+---+-+~+---~~--~~--~~~~-4-~t1
Figure 3. Output Offset Drift (RTO) vs. Gain
Gain Nonlinearity and Noise: Gain nonlinearity increases with
gain as the device loop-gain decreases. Figure 4 is a plot of
typical nonlinearity vs. gain. The shape of the curve can be
safely used to predict worst-case nonlinearity at gains below
100. Noise vs. gain is shown on the same graph.
,
~
.
1
~ 001
~
~
001
1
l~i'~~:20'SE. RTO, 0 1 TO 10kHz B W ~
,
t-tt
'0
~
~
ffi
~
;
001
,
000
~
~ 0004
~
L.V
0006
~IMUM NONLINEARITY. AD522A
/
MAXI~UM NoL'NLRI'T~~
/
, ~TYPIC~A!ITY'Al~ AD522
V
2
AD522B,S
"""
1M
SPECIAL APPLICATIONS
Offset and Gain Trim: Gain accuracy depends largely on the
quality of RG. A precision resistor with a 10ppmtC temperature coefficient is advised. Offset, like gain, is laser-trimmed to
a level suitable for most applications. If further adjustment is
required, the circuit shown in Figure 1 is recommended. Note
that good quality (25ppm) pots are necessary to maintain voltage drift specifications.
CMR Trim: A shorr-term CMR improvement of up to 10dB at
low gains can be realized with the circuit of Figure 2. Apply a
low-frequency 20/G volt peak-to-peak input signal to both
inputs through their equivalent source resistances and trim the
pot for an ac ou tpu t null .
Sense Output: A sense output is provided to enable remote
load sensing or use of an output current booster. Figure 7 illustrates these applications. Being "inside the loop", booster
drift errors are minimized. When not used, the sense output
should be tied to' the output.
10 ~
If/
i<"'V
""
Figure 6. Small Signal Frequency Response (-3dB)
~ '~r-+44+~-4~~~-+lf~
~
Frequency and Gain
1/
/
V
100
1
Figure 4. Gain Nonlinearity and Noise (RTO) vs. Gain
Common Mode Rejection: CMR is rated at ±10V and lkn
source imbalance. At lower gains, CMR depends mainly on
thin-film resistor stability but due to gain-bandwidth considerations, is relatively constant with frequency to beyond 60Hz.
The dc CMR improves with increasing gain and is increasingly
subject to phase shifts in limited bandwidth high-gain amplifiers. Figure 5 illustrates CMR vs. Gain and Frequency.
Dynamic Performance: Settling time and unity gain bandwidth
are directly proportional to gain. As a result, dynamic performance can be predicted from the well-behaved curves of
Figure 6.
4-24 INSTRUMENTA TlON AMPLIFIERS
Figure 7. Output Current Booster and Buffered Output
Level Shifter
Reference Output: The reference terminal is provided to permit
the user to offset or "level shift" the output level to a datum
compatible with his load. It must be remembered that the total
output swing i~ ±1O volts to be shared between signal and reference offset. Furthermore, any reference source resistance will
unbalance the CMR trim by the ratio 10k/Rref. For example, if
the reference source impedance is In, CMR will be reduced to
SOdB (lOkn/lD. = 10,000 = SOdB). A buffer amplifier can be
used to eliminate this error, as shown in Figure 7, but the
drift of the buffer will add to output offset drift. When not
used, the reference terminal should be grounded.
ANALOG
WDEVICES
IIIIIIIIIII
I
Precision Instrumentation Amplifier
AD524
FEATURES
Low Noise: 0.3,..V pop 0.1Hz to 10Hz
Low Nonlinearity: 0.003% (G = 1)
High CMRR: 120dB (G = 1000)
Low Offset Voltage: 50,..V
Low Offset Voltage Drift: 0.5,..V/oC
Gain Bandwidth Product: 25MHz
Pin Programmable Gains of 1, 10, 100, 1000
Input Protection, Power On - Power Off
No External Components Required
Internally Compensated
MIL-STD-883B, Chips, and Plus Parts Available
16-Pin Ceramic DIP Package and 20-Terminal
Leadless Chip Carriers Available
PRODUCT DESCRIPTION
The AD524 is a precision monolithic instrumentation amplifier
designed for data acquisition applications requiring high accuracy
under worst-case operating conditions. An outstanding combination of high linearity, high common mode rejection, low offset
voltage drift, and low noise makes the AD524 suitable for use in
many data acquisition systems.
The AD524 has an output offset voltage drift ofless than 25...,V/oC,
input offset voltage drift of less than 0.5...,V/oC, CMR above
90dB at unity gain (12OdB at G = 1000) and maximum nonlinearity
of 0.003% at G = l. In addition to the outstanding de specifications
the AD524 also has a 25MHz gain bandwidth product (G =
100). To make it suitable for high speed data acquisition systems
the AD524 has an output slew rate of 5V/...,s and settles in 15...,s
to 0.01% for gains of 1 to 100.
As a complete amplifier the AD524 does not require any external
components for fixed gains of 1, 10, 100 and 1,000. For other
gain settings between 1 and 1000 only a single resistor is required.
The AD524 input is fully protected for both power on and
power off fault conditions.
I
AD524 FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTS
1. The AD524 has guaranteed low offset voltage, offset voltage
drift and low noise for precision high gain applications.
2. The AD524 is functionally complete with pin programmable
gains of 1, 10, 100 and 1000, and single resistor programmable
for any gain.
3. Input and output offset nulling terminals are provided for
very high precision applications and to minimize offset voltage
changes in gain ranging applications.
4. The AD524 is input protected for both power on and power
off fault conditions.
5. The AD524 offers superior dynamic performance with a
gain bandwidth product of 25MHz, full power response of
75kHz and a settling time of 15...,s to 0.01% of a 20V step
(G = 100).
The AD524 IC instrumentation amplifier is available in four
different versions of accuracy and operating temperature range.
The economical "A" grade, the low drift "B" grade and lower
drift, higher linearity "c" grade are specified from - 25°C to
+ 85°C. The "S" grade guarantees performance to specification
over the extended temperature range - 55°C to + 125°C. Devices
are available in a 16-pin ceramic DIP package and a 20-terminal
leadless chip carrier.
INSTRUMENTATION AMPLIFIERS 4-25
SPECIFICATIONS
(@ Vs
ADS24A
Typ
Min
Model
= ±15V,
Max
At = 2kfl and TA = +25"& unless otheIwise specified)
ADS248
Typ
Min
Max
ADS24C
Typ
Min
Max
ADS24S
Typ
Min
Max
UOIts
GAIN
Gam EquatIon
(External ResislOr Gam
Programming)
[
4O~000 + I] ±20%
[
4O~000 + I]
±20%
[
G
Gain Range (Pm Programmable)
I to 1000
I to 1000
[40~~+ 1]±20%
4O~:OO + 11 ± 20%
I to 1000
I to 1000
Gam Error
G~I
±O.O5
±O.O3
±0.02
G~IO
±0.25
±0.5
±O.lS
±O.l%
±2.0
±0.35
±l.D
±O.2S
±O.5
±0.01
±OOI
±O.OI
±O.OOS
±O OOS
±0.01
±0.003
±0.003
±O.Ol
±O.OI
±0.01
±O 01
%
5
15
35
100
5
10
25
50
5
10
25
50
5
10
25
50
ppml'C
ppm/"C
ppmf'C
ppmf'C
250
2
5
100
100
0.75
3
50
50
0.5
2.0
25
100
2.0
3.0
50
"V
G ~ 100
G ~ 1000
Nonbnearuy
G~ I
G ~ 10,100
G~lOoo
±O.OS
±O.2S
±0.5
±2.0
%
%
%
%
%
%
Gain vs. Temperature
G~I
G~IO
G
~
100
G~lOoo
VOLTAGE OFFSET (May be Nulled)
Input Offset Voltage
vs. Temperature
OUtput Offset Voltage
vs. Temperamre
Offset Referred to the
Input vs. Supply
G ~ I
G~IO
G
G
~
~
100
1000
70
85
9S
100
75
9S
105
llO
mV
"vrc
dB
dB
dB
dB
75
95
105
llO
80
100
llO
ll5
"vrc
INPUT CURRENT
Input Bias Current
Differenual Capacitance
Common Mode Resistance
Common Mode Capacitance
Input Voltage Range
Max Differ. Input Linear (V D)
Max Common Mode Linear (VeM)
Common Mode ReJection dc
to 60Hz with lkfl Source Imbalance
G ~ I
G~IO
G = 100
G ~ 1000
OUTPUT RATING
VouT.RL = 2kfl
DYNAMIC RESPONSE
Smail Signal -3dB
G = I
G~IO
G
G
~
~
100
1000
Slew Rate
SenlmgTimetoO.Ol%, 20V Step
G = 1 to 100
G = 1000
NOISE
Voltage Noise,lkHz
R.T.I.
R.TO.
R.T.I.,O.l to 10Hz
G=I
G~IO
G~
100, 1000
Current NOlse
O.lHz to 10Hz
12V
±IO
±15
±35
±50
nA
pA/'C
±35
nA
±lOO
±Ioo
±Ioo
±Ioo
INPUT
Input Impedance
Dlffereoual Resistance
±15
±25
±5O
vs. Temperature
Input Offset Current
vs. Temperature
+ 100
+ 100
+100
+100
pArc
10'
10
10'
10
10'
10
10'
10
10'
10
10'
10
10'
10
10'
10
a
±IO
±10
±IO
±lO
V
-(~ XVo )
70
90
100
110
12V
-(~ XV D)
I
400
150
25
5.0
15
75
::'::10
I
400
150
25
5.0
15
75
12V
-(~ XVD)
:t1O
pF
V
dB
dB
dB
dB
70
90
100
110
80
100
110
120
75
95
105
I1S
:t1O
12V-(~XVo)
pF
a
±1O
V
MHz
kHz
kHz
kHz
I
I
400
400
150
25
5.0
150
25
5.0
15
75
15
75
",
'"
VJ~s
7
7
7
7
90
90
90
90
nV/YHz
nV/YHz
15
2
0.3
15
2
0.3
15
2
0.3
15
2
0.3
"Vp-p
"Vp-p
"Vp-p
60
60
60
60
pAp-p
4-26 INSTRUMENTATION AMPLIFIERS
Model
Mon
AD524A
Typ
Min
Max
AD>24B
Typ
Max
AD524C
Typ
Min
Max
Mon
AD524S
Typ
Units
Max
SENSE INPUT
RIN
liN
Voltage Range
Gam to Output
20
15
20
15
20
15
"A
V
%
,,10
±IO
±IO
±IO
kn :!;20°;'
20
15
I
I
I
I
40
15
40
15
40
15
40
15
REFERENCE INPUT
RIN
liN
Voltage Range
Gam to OutPUt
TEMPERATURE RANGE
Specified Performance
Storage
POWER SUPPLY
Power Supply Range
QUiescent Current
,,10
I
+ 85
t ISO
±6
PACKAGE OPTIONS ,
16-PmCeramlc(D-16)
LCC(E-28A)
I
I
25
65
25
65
±lS
5.0
" 15
l 5
±6
:!; IS
l 5
t
85
!
ISO
±lS
5.0
I
I 85
25
65
t
±6
:!:
±6
5.0
" 15
l 5
cC
+ 125
~ 150
°C
±18
5.0
V
rnA
55
65
150
±lS
15
l 5
AD524SD
AD524SE
AD524CD
AD524CE
AD524BD
AD524BE
AD524AD
AD524AE
"A
V
%
10
10
±IO
kH ±20%
NOTES
ISee Section 16 for package outline mformalm
Speclficatlons SUb,eC! to change wtthout nouce
Specifications shown 10 boldface are tested on all production unm at final
electncal test Results from those tests are used to calculate outgomg quality
levels All mm and max speCifications are guaranteed, although onlv those
shown m boldface are tested on all production umts
CONNECTION DIAGRAMS
Ceramic (D) Package
Leadless Chip Carrier (E) Package
g
RG,
Z
I-
i
OUTPUT NULL
+
OUTPUT NUll
I-
I-
itz
cO
<>
z
'j'
2.a:
1
G = I. }
G = 100
I
.
SHORT TO
I
I.~
0
I I
I I
RGl! FOR
DESIRED
GAIN
18 OUTPUT NUll
L~
G = 1000
INPUT NUll 5
NC 6
+vs--c: 15J_-V.
TOP VIEW
(Not to Scale)
~
INPUT NUll 7
15 G = 100
REFERENCE 8
14 G = 10<10
I.
INPUT
OFFSET NUll
17 G = I.
16 NC
AD524
SENSE
10
11
12
::+
~
II
OUTPUT
OffSET NUll
NC = NO CONNECT
SHORT TO
HG 2 FOR
DESIRED
GAIN
13
METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm).
1 - - - - - - - - - - 0 1 1 1 1 4 3 4 ) --------~~
'G,
B +Vs
0103
(262)
7 -Vs
3
4
5
RG INPUT INPUT
NUll NULL
REFERENCE
PAD NUMBERS CORRESPOND TO PIN NUM8ERS FOR THE D16A 16-P1N Cf:RAMIC PACKAGE
INSTRUMENTATION AMPLIFIERS 4-27
Typical Characteristics
20
30
20
5
V
/
•
/
•
~
•
•
v.:.c
1/
•
/
10
Figure 1. Input Voltage Range vs.
Supply Voltage, G = 1
.
'.
20
16
SUPPLY VOLTAGE -t.V
/
/
/
/
.
,
•,.
20
.
+1
~
z
•
~
20
~
l°r---=....----+---t--~i
•
•
8 ~----+----_+------~----_t
•f-----+_-----f-----+-----;
--- -......
-1
"
•
r--
,.
~
I
-
30
12~----+----_+------~----_t
1
10k
Figure 3. Output Voltage Swing vs.
Resistive Load
1.~----1------+------~----~
~
V
100
1k
LOAD RESISTANCE - n
SUPPLY VOLTAGE -t.V
1.,----..,----,------,-----,
•
/
l/
Figure 2. Output Voltage Swing vs.
Supply Voltage
•
II
•
,.
,
•
e-
-20
-30
•
5
10
SUPPLY VOLTAGE
-:tv
20
lEi
·.~----~.------~,.~--~,~.----~20
POWER SUPPL V VOLTAGE -
Figure 4. Quiescent Current vs.
Supply Voltage
-40
-76
tV
26
-25
125
TEMPERATURE _ °C
Figure 5. Input Bias Current vs.
Supply Voltage
Figure 6. Input Bias Current vs.
Temperature
1.r-----,-----~------r_----~
•
,.r-----1------+------~----~
1'2~----+_----~----~----_4
.",
/
1
/
V
I
i'0(-----i;~~_*------r---~~
2
'"G .~----1_----_+------~----~
3
~ .~----+_----~----~----_4
iiE • ~-----f------+-----_I-------l
5
/
~
100
3
/
10
•
·~.----~~----,~.----~,~.----~20
1
Figure 7. Input Bias Current vs.
CMV
30
40
•
G = 1
5.0
6.0
70
8.0
10
r
100
111:
10k
lOOk
fREQUENCY _ Hz
1M
10M
Figure 9. Gain vs. Frequency
ILLJ
}
G = 10
-100
•
Figure 8. Offset Voltage, RTI, Turn
On Drift
G = 100
-120
2.
WARM-UP TIME - MINUTES
INPUT VOLTAGE -:tV
'.~----~------~-----r-----'
••,~--~~------t~----+----~
I
'1-80 G = 1
,
g;
~-60
~60'~----~------t~----+----~
ij •
!\I
~
•
1
10
100
1k
10k
lOOk
1M
10M
FREQUENCY _ Hz
Figure 10. CMRRvs. FrequencyRTI,
Zero to 1k Source Imbalance
4-28 INSTRUMENTATION AMPLIFIERS
G=1ooo\
! ~.
-20
•
1k
01000.
10k
8iNir~Tl~,~r
01001 010
100k
FREQUENCY - Hz
,,
~.
\
1
-4G
i
.
,
'M
Figure 1,. LargeSignalFrequency
Response
\
'00
GAIN - VfY
Figure 12. Slew Rate vs. Gain
1000
Typical Characteristics
.
,ao
..
+Vs= 15Vdc+
,
WPIPSINEWAVE
40
1
20
.........
oo
.
.........
f::- ~~
I'--. ~~ -..... r-
r---..
4
~.70--.....
....
--
--
..........
.,
,
.
1k
FREQUENCY _ H;r
.........
.,.
0
,
10k
GOk
Figure 13. Positive PSRR vs.
Frequency
100
~
r---..
...................
1
%
,
........
...... .........
..........
lk
1000
~,oo
Q. ,
.........
1
I--
..;: ~ .........
r---.. ~
Q~
..........
~
lv•. I_'5v1+
rPIPSINEWAVE -
10k
~
I'-......
10
G=1
0=10
r-..
~ ,
......
0=1000.....
,
100
10
'00k
FREQUENCY - Hz
Figure 15. RTI Noise Spect,,]1
Density vs. Gain
Figure 14. Negative PSRR vs.
Frequency
.
,
FREQUENCY _ Hz
0.1- 10Hz
-12TO 12
!
If
I
= 5p.V
0.1%
/'
001%
-8ro 8
V
....
-4TO 4
I
OUTPUT
OUTPUT
STEP-V
STEP- V
4TO - 4
8TO -
II
I
1\
"
" ,%
12 TO -1 2
Figure 18. Low Frequency Noise G = 1000 (System Gain = 100,000)
-12T01 2
,%
If /
VERTICAL SCALE. 1 DIVISION
Figure 17. Low Frequency NoiseG = 1 (System Gain = 1000)
Figure 16. Input Current Noise
-4TO 4
'Ok
"
'""
-8TO 8
lk
FREQUENCY - Hz
01 - 10Hz
"'-
'.
0-100,1000
/'"
/ ,/
"' 0'"
.........
10
SETTLING TIME - ps
8ro- 8
001%
12TO-l 2
'5
20
Figure 20. Large Signal Pulse
Response and Settling Time G= 1
Figure 19. Settling Time Gain
-121012
".,.
-aTO 8
01%
/001%
V
I
0
I
\
410- 4
........
VOl%
\
\,,,
\
01%
'~Ot%
,.
SETrLING TIME -
'5
20
fLs
Figure 21. Settling Time Gain = 10
001%
/ /
-4T04
I"
OUTPUT
STEP-V
410-4
1\
\
,,%
12TO-1 2
Figure 22. Large Signal Pulse
Response and Settling Time
G = 10
i\
\ \
aTO- 8
01%
001%
10
SETILINGTIME- )1.5
,
20
Figure 23. Settling Time Gain = 100
Figure 24. Large Signal Pulse
Response and Settling Time
G= 100
INSTRUMENTATION AMPLIFIERS 4-29
Ir
-12T01 2
1%
-STO 8
/
-4TO 4
V
/
1\
"-
1
%
0.01%
v /
OUTPUT
STEP-V
4TO- 4
\
STO- 8
r\ \
1%
12TO-1 2
10
20
~.1%
30
40
50
SETILINGTIME- JlS
001%
Figure 28. Noise Test Circuit
60
70
SO
+v.
Figure 25. Settling Time Gain = 1000
-v,
Figure 26. Large Signal Pulse Response and
Settling Time G = 1000
10kO
001%
1kO
lOT
10kfl
01%
Figure 27. Settling Time Test Circuit
Theory of Operation
The ADS24 is a monolithic instrumentation amplifier based on
the classic 3 op amp circuit. The advantage of monolithic construction is the closely matched components that enhance the
performance of the input preamp. The preamp section develops
the programmed gain by the use of feedback concepts. The
programmed gain is developed by varying the value of R<; (smaller
values increase the gain) while the feedback forces the collector
currents Ql, Q2, Q3 and Q4 to be constant which impresses the
input voltage across R<;.
As RG is reduced to increase the programmed gain, the transconductance of the input preamp increases to the transconductance
of the input transistors. This has three important advantages.
First, this approach allows the circuit to achieve a very high
open loop gain of 3 x 108 at a programmed gain of 1000 thus
reducing gain related errors to a negligible 30ppm. Second, the
4-30 INSTRUMENTA TION AMPLIFIERS
Figure 29. Simplified Circuit of Amplifier; Gain is Defined as
((R56 + R57)I(RG) + 1. Fora Gain of1, RGisan Open Circuit
gain band with product which is determined by C3 or C4 and
the input transconductance, reaches 2SMHz. Third, the input
voltage noise reduces to a value determined by the collecto~
current of the input transistors for an RTI noise of 7n VtVHz at
G = 1000.
INPUT PROTECTION
As interface amplifiers for data acquisition systems, instrumentation amplifiers are often subjected to input overloads, i.e.,
voltage levels in excess of the full scale for the selected gain
range. At low gains, 10 or less, the gain resistor acts as a current
limiting element in series with the inputs. At high gains the
lower value of R<; will not adequately protect the inputs from
excessive currents. Standard practice w(lUld be to place series
limiting resistors in each input, but to limit input current to
below SmA with a full differential overload (36.Yl would require
over 7k of resistance which would add lOnVVHz of noise. To
provide both input protection and low noise a special series
protect FET was used.
A unique FET design was used to provide a bidirectional current
limit, thereby, protecting against both positive and negative
overloads. Under nonoverload conditions, three channels CH2,
CH3 , CH4 , act as a resistance (= lkO) in series with the input as
before. During an overload in the positive direction, a fourth
channel, CHI, acts as a small resistance (=3kO) in series with
the gate, which draws only the leakage current, and the FET
limits IDss, When the FET enhances under a negative overload,
the gate current must go through the small FET formed by CHI
and when this FET goes into saturation, the gate current is
limited and the main FET will go into controlled enhancement.
The bidirectional limiting holds the maximum input current to
3mA over the 36V range.
Applying the AD524
INPUT OFFSET AND OUTPUT OFFSET
Voltage offset specifications are often considered a figure of
merit for instrumentation amplifiers. While initial offset may be
adjusted to zero, shifts in offset voltage due to temperature
variations will cause errors. Intelligent systems can often correct
for this factor with an auto-zero cycle, but there are many smallsignal high-gain applications that -don't have this capability.
Voltage offset and drift comprise two components each; input
and output offset and offset drift. Input offset is that component
of offset that is directly proportional to gain i.e., input offset as
measured at the output at G = 100 is 100 times greater than at
G = I. Output offset is independent of gain. At low gains,
output offset drift is dominant, while at high gains input offset
drift dominates. Therefore, the output offset voltage drift is
normally specified as drift at G = I (where input effects are
insignificant), while input offset voltage drift is given by drift
specification at a high gain (where output offset effects are negligible). All input-related numbers are referred to the input
(RTI) which is to say that the effect on the output is "G" times
larger. Voltage offset vs. power supply is also specified at one or
more gain settings and is also RTI.
By separating these errors, one can evaluate the total error independent of the gain setting used. In a given gain configuration
both errors can be combined to give a total error referred to the
input (R.T.I.) or output (R.T.O.) by the following formula:
Total Error R. T.1. = input error + (output error/gain)
Total Error R.T.O. = (Gain x input error) + output error
The ADS24 can be configured for gains other than those that
are internally preset; there are two methods to do this. The first
method uses just an external resistor connected between pins 3
and 16 which programs the gain according to the formula
Ro = G40k (see Figure 31). For best results R<; should be a
-1
precision resistor with a low temperature coefficient. An external
RG affects both gain accuracy and gain drift due to the mismatch
between it and the internal thin-film resistors. Gain accuracy is
determined by the tolerance of the external R<; and the absolute
accuracy of the internal resistors (± 20%). Gain drift is determined
by the mismatch of the temperature coefficient of RG and the
temperature coefficient of the internal resistors (- SOppm/oC
typ).
+v,
-INPUT
~'
RG,
OR
2105I1.U
lkn
REFERENCE
+INPUT
G.~+,.20t2""
Figure 31. Operating Connections for G = 20
The second technique uses the internal resistors in parallel with
an external resistor (Figure 32). This technique minimizes the
gain adjustment range and reduces the effects of temperature
coefficient se~sitivity.
+v,
As an illustration, a typical AD524 might have a + 250,...V output
offset and a - SOli-V input offset. In a unity gain configuration, .
the total output offset would be 20011-V or the sum of the two.
At a gain of 100, the output offset would be -4.7SmV or:
+2S01l-V + lOO(-SOIl-V) = -4.7SmV.
The ADS24 provides for both input and output offset adjustment.
This simplifies very high precision applications and minimize
offset voltage changes in switched gain applications. In such
applications the input offset is adjusted first at the highest programmed gain, then the output offset is adjusted at G = 1.
GAIN
The ADS24 has internal high accUracy pretrimmed resistors
for pin programmable gain of 1, 10, 100 and 1000. One of
the preset gains can be selected by pin strapping the appropriate gain terminal and RGz together (for G = I RGz is not
connected).
+v,
-INPUTo------{I)
VOUT
RG,'L-_ _ _o--(3)
' - - - - - 0 "FERENCE
+INPUTOo-------(
G
= ~ + 1 = 20 ± 17%
Figure 32. Operating Connections for G = 20, Low Gain
T.C. Technique
The ADS24 may also be configured to provide gain in the output
stage. Figure 33 shows an H pad attenuator connected to the
reference and sense lines of the ADS24. RI, R2 and R3 should
be made as low as possible to minimize the gain variation and
reduction of CMRR. Varying R2 will precisely set the gain
without affecting CMRR. CMRR is determined by the match of
RI and R3.
+v,
-INPUT
G
G
R'
2.2ekn
o------{
-INPUT o-----~
= 100
= 1000
r-t----t-ov
OUT
OUTPUT
G
'----0() SIGNAl
RG,
RG,
COMMON
+INPUT o - - - - - - {
= 1000
+~~To------U
R3
22111dl
-v,
G "'"
IRall40kl + R, +
R3
IR,fl4Okl
Figure 30. Operating Connections for G = 100
Figure 33. Gain of 2000
INSTRUMENTATION AMPLIFIERS 4-31
•
Table I. Output Gajn Resistor Values
COMMON-MODE REJECTION
Common-mode rejection is a measure of the change in output
voltage when both inputs are changed equal amounts. These
specifications are usually given for a f\ill-range input voltage ,
change and a specified source imbalance. "Common-Mode Rejection Ratio" (CMRR) is a ratio expression while "Common-Mode
Rejection" (CMR) is the logarithm of that ratio. For example, a
CMRR of 10,000 corresponds to a CMR of 8OdB.
INPUT BIAS CURRENTS
Input bias currents are those currents necessary to bias the
input transistors of a dc amplifier. Bias currents are an additional
source of input error and must be considered in an total error
budget. The bias currents when multiplied by the source resistance
appear as an offset voltage. What is of concern in calculating
bias current errors is the change in bias cUrrent with respect to
signal voltage and temperature. Input offset current is the difference between the two input bias currents. The effect of offset
current is an input offset voltage whose magnitude is the offset
current times the source impedance imbalance.
In an instrumentation amplifier, ac common-mode rejection is
only as good as the differential' phase shift. Degradation of ac
common-mode rejection is caused by unequal drops across differing
track resistances and a differential phase shift due to varied
stray capacitances or cable capacitances. In many applications
shie1d~ cables are used to minimize noise. This technique can
create common mode rejection errors unless the shield is properly
driven. Figures 35 and 36 shows active data guards which are
configured to improve ac common mode rejection by "bootstrapping" the capacitances of the input cabling, thus minimizing
differential phase shift.
Output
Gain
2
5
10
R2
Rl,R3
Nominal
Gain
5kO
2.26kO 2.02
1.05kO 2.05kO 5.01
IkO
4.42kO 10.1
+v.
Although instrumentation amplifiers have differential inputs,
there must be a rerum path for the bias currents. If this is not
provided, those currents will charge stray capacitances, causing
the output to drift uncontrollably or to saturate. Therefore,
when amplifying "floating" input sources such as transformers
and thermocouples, as well as ac-coupled sources, there must
still be a dc path from each input to ground.
-v.
Figure 35. ShieldDriver,G;;.100
J
TO POWER
SUPPLY
S--------=-------=::i.- GROUND
a. Transformer Coupled
Figure 36. Differential Shield Driver
TO POWER
SUPPLY
t---------=-------=::i._ GROUND
GROUNDING
Many data-acquisition components have two or more ground
pins which are not connected together within the device. These
grounds must be tied together at one point, usually at the system
power-supply ground. Ideally, a single solid ground would be
desirable. However, since current flows through the ground
wires and etch stripes of the circuit cards, and since these paths
b. Thermocouple
L-~
_____
~
____
TOPOW£R
SUPPLY
--=~--.'GROUND
c. AC Coupled
'* IFRETURN
INDEPENDENT. OTHERWISE
AMPLIFIER REFERENCE
TO MECCA AT ANALOG P S COMMON
Figure 34. Indirect Ground Returns for Bias Currents
4-32 INSTRUMENTAnO/ll AMPLIFIERS
Figure 37. Basic Grounding Practice
have resistance and inductance, hundreds of millivolts can be
generated between the system ground point and the data acquisition
components. Separate ground returns should be provided to
minimize the current flow in the path from the sensitive points
to the system ground point. In this way supply currents and
logic-gate return currents are not summed into the same return
path as analog signals where they would cause measurement
errors.
Since the output voltage is developed' with respect to the potential
on the reference terminal an instrumentation amplifier can solve
many grounding problems.
SENSE TERMINAL
The sense terminal is the feedback point for the instrument
amplifier's output amplifier. Normally it is connected to the
instrument amplifier output. If heavy load currents are to be
drawn through long leads, voltage drops due to current flowing
through lead resistance can cause errors. The sense terminal can
be wired to the instrument amplifier at the load thus putting the
IxR drops "inside the loop" and virtually eliminating this error
source.
Any significant resistance from the reference terminal to ground
increases the gain of the noninverting signal path thereby upsetting
the common-mode rejection of the IA.
In the ADS24 a reference source resistance will unbalance the
CMR trim by the ratio of20knlRREP • For example, ifthe reference
source impedance is In, CMR will be reduced to 86dB (20knl
In = 86dB). An operational amplifier may be used to provide
that low impedance reference point as shown in Figure 39. The
input offset voltage characteristics of that amplifier will add
directly to the output offset voltage performance of the instrumentation amplifier.
An instrumentation amplifier can be turned into a voltage-to-current converter by taking advantage of the sense and reference
terminals as shown in Figure 40.
+INPUT
-INPUT
I
L
= Vx = VIN
lr,
ff1"
(1 + 40,000)
--.:IG
Figure 40. Voltage-to-Current Converter
v-
Figure 38. AD524 Instrumentation Amplifier with Output
Current Booster
Typically, IC instrumentation amplifiers are rated for a full
± 10 volt output swing into 2kn. In some applications, however,
the need exists to drive more current into heavier loads. Figure
38 shows how a high-current booster may be connected "inside
the loop" of an instrumentation amplifier to provide the required
current boost without significantly degrading overall performance.
Nonlinearities, offset and gain inaccuracies of the buffer are
minimized by the loop gain of the IA output amplifier. Offset
drift of the buffer is similarly reduced.
REFERENCE TERMINAL
The reference terminal may be used to offset the output by up
to ± lOY. This is useful when the load is "floating" or does not
share a ground with the rest of the system. It also provides a
direct means of injecting a precise offset. It must be remembered
that the total output swing is ± 10 volts to be shared between
signal and reference offset.
By establishing a reference at the "low" side of a current setting
resistor, an output current may be defmed as a function of
input voltage, gain and the value of that resistor. Since only a
small current is demanded at the input of the buffer amplifier
A2, the forced current IL will largely flow through the load.
Offset and drift specifications of A2 must be added to the output
offset and drift specifications of the IA.
PROGRAMMABLE GAIN
Figure 41 shows the ADS24 being used as a software programmable
gain amplifier. Gain switching can be accomplished with mechanical switches such as DIP switches or reed relays. It should be
noted that the "on" resistance of the switch in series with the
internal gain resistor becomes part of the gain equation and will
have an effect on gain accuracy.
+v,
Figure 39. Use of Reference Terminal to Provide Output
Offset
When the IA is of the three-amplifier configuration it is necessary
that nearly zero impedance be presented to the reference terminal.
Figure 41. 3 Decade Gain Programmable Amplifier
INSTRUMENTATION AMPLIFIERS 4-33
The AD524 can also be connected for gain in the output stage.
Figure 42 shows an AD547 used as an active attenuator in the
output amplifier's feedback loop. The active attenuation presents
a very low impedance to the feedback resistors therefore minimizing the common rejection ratio degradation.
-Vs
Another method for developing the switching scheme is to use a
DAC. The AD7528 dual DAC which acts essentially as a pair of
switched resistive attenuators having high analog linearity and
symmetrical bipolar transmission is ideal in this application.
The multiplying DAC's advantage is that it can handle inputs of
either polarity or zero without affecting the programmed gain.
The circuit shown uses an AD7528 to set the gain (DAC A) and
to perform a fine adjustment (DAC B).
AUTO-ZERO CIRCUITS
In many applications it is necessary to provide very accurate
data in high gain configurations. At room temperature the offset
effects can be nulled by the use of offset trimpots. Over the
operating temperature range, however, offset nulling becomes a
problem. The circuit of Figure 44 show a CMOS DAC operating
in the bipolar mode and connected to the reference terminal to
provide software controllable offset adjustments.
o-....-If-r(7]
+ Vs o-+-1r-p..m
-INPUT
GND
Figure 44. Software Controllable Offset
In many applications complex software algorithn)s for auto-zero
applications are not available. For those applications Figure 45
provides a hardware solution.
VOUT
+v,
~
15
1.
14
13
RG,
,
I
I
VOUl
11~
RG,
:
I
12
I
I
11
I
r-- - ~ ==== __
AD75100tKD
GNO
Figure 43. Programmable Output Gain Using a DAC
4-34 INSTRUMENTA TlON AMPLIFIERS
Figure 45. Auto-Zero Circuit
I
I
I
.J
~CH
Error Budget Analysis
+Vs
+10V
,.--...\
\
,
,, ,
,,
I
I
I
\
I
14-BIT
I
,
ADC
I
OT02V
F.S.
I
I
I
---------'I.! __ j
Figure 46. Typical Bridge Application
ERROR BUDGET ANALYSIS
To illustrate how instrumentation amplifier specifications are
applied, we will now examine a typical case where an ADS24 is
required to amplify the output of an unbalanced transducer.
Figure 46 shows a differential transducer, unbalanced by lOOn,
supplying a 0 to 20mV signal to an ADS24C. The output of the
IA feeds a 14-bit A to D converter with a 0 to 2 volt input
voltage range. The operating temperature range is - 2SoC to
+8SoC. Therefore, the largest change in temperature ~T within
the operating range is from ambient to + 8SoC (8S0C - 2SoC
= 60°C).
In many applications, differential linearity and resolution are of
prime importance. This would be so in cases where the absolute
value of a variable is less important than changes in value. In
these applications, only the irreducible errors (4Sppm = 0.004%)
are significant. Furthermore, if a system has an intelligent processor monitoring the A to D output, the addition of a auto-gaini
auto-zero cycle will remove all reducible errors and may eliminate
the requirement for initial calibration. This will also reduce
errors to 0.004%.
ADS24C
Error Source
Specifications
Calculation
Gain Error
Gain Instability
Gain Nonlinearity
Input Offset Voltage
Input Offset Voltage Drift
±0.2S%
2Sppm
±0.003%
±SO."V,RTI
±O.S."VfC
Output Offset Voltage l
Output Offset Voltage Drift l
±2.0mV
±2S."VrC
Bias Current - Source
Imbalance Error
Bias Current - Source
Imbalance Drift
Offset Current- Source
Imbalance Error
Offset Current - Source
Imbalance Drift
Offset Current- Source
Resistance - Error
Offset Current- Source
Resistance- Drift
Common Mode Rejection
SVdc
Noise,RTI
(0. I-10Hz)
±ISnA
± 0.2S% = 2S00ppm
(2SppmfC)(60OC) = ISOOppm
± 0.003% = 30ppm
±SO."V/2OmV = ±2S00ppm
(±O.S."VfC)(60°C) = 30."V
30."V/2OmV = ISOOppm
±2.0mV/20mV = lOOOppm
(±2S."VfC)(60°C) = ISOO."V
ISoo."V/2OmV = 7S0ppm
(± ISnA)(loon) = l.S."V
l.S."V/20mV = 7Sppm
(± lOOpArC)(IOOn)(60°C) = 0.6."V
0.6."V/2OmV = 30ppm
(±IOnA)(lOOn) = I."V
I."V/2OmV = SOppm
(IOOpArC)(IOOn)(60OC) = 0.6."V
0.6."V/2OmV = 30ppm
(lOnA)(l7Sn) = 3.S."V
3.S",V/20mV = 87.5ppm
(lOOpArC)(17Sn)(60°C) = I."V
I."V/20mV = SOppm
l1SdB = l.8ppm x SV = 8.8."V
8.8."V/2OmV = 444ppm
± 100pArC
±IOnA
±IOOpAfC
±IOnA
±IOOpArC
l1SdB
O.3."Vp-p
0.3."Vp-p/2OmV
Effect on
Absolute
Accuracy
atTA = 25°C
Effect on
Absolute
Accuracy
atTA = 85°C
2Sooppm
2S00ppm
ISOOppm
2S00ppm
2S0Oppm
1000ppm
ISOOppm
lOOOppm
7S0ppm
7Sppm
30ppm
SOppm
SOppm
30ppm
87.Sppm
87.Sppm
SOppm
444ppm
444ppm
= ISppm
Total Error
Effect
on
Resolution
30ppm
7Sppm
ISppm
66S6.Sppm
IOS16.Sppm
•
4Sppm
'Output offset voltage and output offset voltage drift are given as RTI figures.
Table II. Error Budget Analysis of AD524CD in Bridge Application
INSTRUMENTATION AMPLIFIERS 4-35
Figure 47 shows a simple application, in which the variation of
the cold-junction voltage of a Type J thermocouple-iron( + )constantan- is compensated for by a voltage developed in series
by the temperature-sensitive output current of an AD590
semiconductor temperature sensor.
perature and the circuit near 25°C. If resistors with low tempcos
are used, compensation accuracy will be to within :!:;O.5°C, for
temperatures between + 15°C and + 35°C. Other thermocouple
types may be 'accommodated with the standard resistance values'
shown in the table. For other ranges of ambient temperature,
the equation in the figure may be solved for the optimum values
ofRTand R A •
The circuit is calibrated by adjusting RT for proper output
voltage with the measuring junction at a known reference tem-
7.5V
+Vs
RA
NOMINAL
TYPE VALUE
J
52.W
K
T
41.2.11
61.4.11
40.2.11
S.R
5.76.!l
E
AD560
REFERENCE
JUNCTION
15°C < TA <35"C
G = 100
+Vs
•t
IRON
Eo
CU
MEASURING
JUNCTION
lk.l1
-Vs
OUTPUT
AMPLIFIER
OR METER
NDMINAL
VALUE
9135.!l
Figure 47. Cold-Junction Compensation
The microprocessor controlled data acquisition system shown in
Figure 48 includes both auto-zero and auto-gain capability. By
dedicating two of the differential inputs, one to ground and one
to the AID reference, the proper program calibration cycles can
eliminate both initial accuracy errors and accuracy errors over
temperature. The auto-zero cycle, in this application, converts a
number that appears to be ground and then writes that same
number (8 bit) to the AD7524 which eliminates the zero error
since its output has an inverted scale. The auto-gain cycle converts
the AID reference and compares it with full scale. A multiplicative
correction factor is then computed and applied to subsequent
readings.
MICROPROCESOR
ADDRESS BUS
Figure 48. Microprocessor Controlled DataAcquisition System
4-36 INSTRUMENTA TION AMPLIFIERS
ANALOG
WOEVICES
IIIIIIIIIII
FEATURES
Digitally Programmable Binary Gains from 1 to 16
Two-Chip Cascade Mode Achieves Binary Gain from
1 to 256
Gain Error:
0.01% max, Gain = 1,2,4 (C Gradel
0.02% max, Gain = 8, 16 (C Gradel
0.5ppmfC Drift Over Temperature
Fast Settling Time
10V Signal Change:
0.01% in 4.5 ....s (Gain
161
Gain Change:
0.01% in 5.6 ....s (Gain = 161
Low Nonlinearity: ±0.005% FSR max (J Gradel
Excellent dc Accuracy:
Offset Voltage: 0.5mV max (C Gradel
Offset Voltage Drift: 3 .... VfC (C Gradel
TTL Compatible Digital Inputs
PRODUCT DESCRIPTION
The AD526 is a single-ended, monolithic software programmable
gain amplifier (SPGA) that provides gains of I, 2, 4, 8 and 16.
It is complete, including amplifier, resistor network and
TTL-compatible latched inputs, and requires no external
components.
Low gain error and low nonlinearity make the AD526 ideal for
precision instrumentation applications requiring programmable
gain. The small signal bandwidth is 350kHz at a gain of 16. In
addition, the AD526 provides excellent de precision. The FETinput stage results in a low bias current of 50pA. A guaranteed
maximum input offset voltage of 0.5mV max (C grade) and low
gain error (0.01%, G= 1,2,4, C grade) are accomplished using
Analog Devices' laser trimming technology.
Software Programmable
Gain Amplifier
AD526 I
AD526 PIN CONFIGURATION
DIG GND
•
Al
NUll
AD
CS
V'N
!\NAlOG GND 2
ANALOG GND 1
-Vs
VOUT SENSE
AD526
ClK
TOP VIEW
(Not to Scale)
A2
B
+Vs
V OUT FORCE
APPLICATION HIGHLIGHTS
I. Dynamic Range Extension for ADC Systems: A single
AD526 in conjunction with a 12-bit ADC can provide 96dB
of dynamic range for ADC systems.
2. Gain Ranging Pre-Amps: The AD526 offers complete digital
gain control with precise gains in binary steps from I to 16.
Additional gains of 32,64, 128 and 256 are possible by cascading
two AD526s.
To provide flexibility to the system designer, the AD526 can be
operated in either latched or transparent mode. The force/sense
configuration preserves accuracy when the output is connected
to remote or low impedance loads.
The AD526 is offered in one commercial (0 to + 70°C) grade, J,
and three industrial grades, A, Band C, which are specified
from - 40°C to + 85°C. The S grade is specified from - 55°C to
+ 125°C. The military version is available processed to MIL-STD
883B, Rev C. The J grade is supplied in a 16-pin plastic DIP,
and the other grades are offered in a 16-pin hermetic side-brazed
ceramic DIP.
INSTRUMENTATION AMPLIFIERS 4-37
SPECIFICATIONS
(@ Vs
= ± 15V. RL =
Min
+ 25"C
Typ
Max
Min
Typ
unless otheIwise specified)
AD526B/S
AD526A
AD526J
Model
2kO and TA =
Max
Min
Typ
AD526C
Max
Min
Typ
Max
Units
0.01
0.01
0.01
0.02
0.02
%
%
%
%
%
GAIN
Gam Range
(Digitally Programmable)
Gain Error
G~ I
G ~ 2
0.05
0.05
0.10
0.15
0.15
G~4
G~8
G~ 16
Gain Error Drift
Over Temperature
G~I
0.5
0.5
0.5
0.5
1.0
G ~ 2
G~ 4
G~8
G ~ 16
Gain Error (Tmm [0 T max)
G~ I
G ~ 2
G ~4
G~8
G ~ 16
Nonlinearity
G~ I
G ~ 2
G ~4
G ~8
G ~ 16
Nonlmearity (T mm to T max)
G~ I
G~2
G
G
G
~4
~
~
1,2,4,8,16
1,2,4,8,16
8
16
VOLTAGE OFFSET, ALL GAINS
Input Offset Voltage
Input Offset Voltage Drift Over
Temperature
1,2,4,8,16
0.02
0.03
0.03
0.07
0.07
2.0
2.0
3.0
5.0
5.0
0.5
0.5
0.5
0.5
1.0
1,2,4,8,16
0.01
0.02
0.02
0.04
0.04
0.5
0.5
0.5
0.5
1.0
2.0
2.0
3.0
5.0
5.0
2.0
2.0
3.0
5.0
5.0
0.06
0.06
0.12
0.17
0.17
0,03
0.04
0.04
0.08
0.08
O.oz
0.005
0.001
0.001
0.001
0.001
0.005
0.001
0.001
0.001
0.001
0.01
0.001
0.001
0.001
0.001
0.01
0.001
0.001
0.001
0.001
0.4
1.5
0.25
5
20
3
0.5
0.5
0.5
0.5
1.0
0.015
0.015
0.015
0.25
10
3
ppm/oC
ppmrC
ppm/oC
ppml°C
ppm/oC
0.03
%
%
%
%
%
0.005
0.001
0.001
0.001
0.001
0.0035
0.001
0.001
0.001
0.001
%FSR
%FSR
%FSR
%FSR
%FSR
0.01
0.001
0.001
0.001
0.001
0.007
0.001
0.001
0.001
0.001
%FSR
%FSR
0.5
mV
0.03
0.03
0.05
0.05
0.7
2.0
2.0
3.0
5.0
5.0
O.O~
0.5
0.25
10
3
%FSR
%FSR
%FSR
10
",vrc
0.8
mV
Input Offset Voltage
2.0
TmmtoTmax
Input Offset Voltage vs. Supply
(Vs = 10%)
80
INPUT BIAS CURRENT
Over Input Voltage Range ± lOY
1.0
80
50
150
0.8
84
50
150
dB
90
50
150
50
150
pA
ANALOG INPUT
CHARACTER.ISTICS
Voltage Range
(Linear Operation)
Capacitance
RATED OUTPUT
Voltage
Current (VOUT ~ = IOV)
Short -Circuit Current
DC Output Resistance
Load Capacitance
(For Stable Operation) ,
=10
±IO
±5
15
±I2
5
=10
12
±10
30
0.002
%10
±5
IS
±
::tI2
5
±IO
=12
=10
30
0.002
±10
±5
15
=12
5
±IO
:tIl
±IO
±5
15
'" 10
30
0.002
± 12
5
V
pF
= 12
"'10
30
0.002
V
rnA
rnA
fl
700
700
700
700
pF
3
3
3
3
",Vp-p
70
60
30
25
70
60
30
25
70
60
30
25
70
60
30
25
nVVHz
nVVHz
nVVHz
nVVHz
NOISE, ALL GAINS
Voltage Noise, RTI
O.IHz to 10Hz
Voltage Noise Density, RTI
f~
10Hz
100Hz
1kHz
f~ 10kHz
f~
f~
4-38 INSTRUMENTATION AMPLIFIERS
ADSUj
Model
Typ
Min
DYNAMIC RESPONSE
- 3dB Bandwidth (Small SIgnal)
G~ I
G~2
G ~4
G~8
G ~ 16
SIgnal Setthng TIlDe to 0.01%
(AVouT=±IOV)
G~ I
G ~2
G~4
~ 16
Full Power Bandwidth
G ~ 1,2,4
G ~ 8,16
TIMING'
(VL ~ 0.2V, VH ~ 3.7V)
AO,AI,A2
Tc
Ts
TH
B
Tc
Ts
TH
Typ
1.5
1.5
0.65
035
0.65
0.35
2.1
2.5
2.7
3.6
4.1
4
5
5
7
7
0.10
0.35
4
18
6
24
60
2
0
100
ADS26B1S
Max
Min
4.0
2.0
2I
2.5
2.7
3.6
4.1
G~8
D1GITALINPUTS
(Tnun to T max)
Input Current (VH ~ 5V)
l.og!c"I"
Lo(!1C"O"
Min
4.0
2.0
G
Slew Rate
G ~ 1,2,4
G~ 8,16
ADS26A
Max
140
6
0.8
6
24
60
2
0
100
ADS26C
Max
Min
2.1
2.5
2.7
3.6
4.1
4
5
5
7
7
140
6
0.8
6
24
60
2
0
100
'MOl<
1.5
2.1
2.5
27
3.6
4.1
4
5
5
7
7
140
6
0.8
Units
MHz
MHz
MHz
MHz
MHz
065
0.35
4
5
5
7
7
J.'S
J.'S
J.'s
I'S
I'S
0.10
0.35
MHz
MHz
4
18
6
24
V/J.'s
V/J.'S
60
2
0
100
0.10
0.35
4
18
Typ
4.0
2.0
4.0
2.0
1.5
0.65
0.35
0.10
0.35
4
18
Typ
140
6
0.8
J.'A
V
V
50
30
30
50
30
50
30
30
50
30
30
ns
ns
ns
50
40
10
50
40
10
50
40
10
50
40
10
ns
ns
ns
30
TEMPERATURE RANGE
Specified Performance
Stornge
POWER SUPPLY
Operating Range
0
-65
+70
+125
±4.S
POSItive Supply Current
Negative Supply Current
PACKAGE OPTIONS'
Plasbc(N·16)
Ceramic DIP (D·16)
-40
-65
±16.S ±4.S
14
13
10
10
+85
+ 150
10
10
-40/-55
-65
±16.S ±4.S
14
13
+85/+ 125
+150
10
10
±16.S
14
13
-40
-65
+85
±4.S
10
10
+ 150
"C
"C
±16.S
14
13
V
mA
mA
AD526jN
NOTE
lRefer to FIgUre 35 for deflrunons.
FSR ~ Full·Scale Range ~ 20V
RTI = Referred to Input.
2See Section 16 for package outlIne information.
ADS26AD
ADS26BD ADS26SD
AD526SD/883B
AD526CD
Specdicaoons subJect to change Without notice.
Specific8nom. shown 10 boldf~"e are tested on all producnon unlts at final
e1ectncal test All mm and max specdicatlODs are guaranteed, although only
those shown 10 boldface are tested on al1 production umts.
INSTRUMENTATION AMPLIFIERS 4-39
Typical Characteristics
>,IS
.
/
V
VV
v
/
..
~V
("Ys =:l::15V
10.
v.. =o
.
10
SUPPlY VOlTAGE - :IOV
5
Figure 3. Input Bias Current vs.
Supply Voltage
20
"
...
•,
V."'t15V
JI
V
I--V
---\
V
.
'00
-00
TEMPERATURE _ 'C
Figure 4. Input Bias Current vs.
Temperature
"-
1\
.
Giii"'t'l
tOOk
-V
100
1"-
:l:15VLTHW!P
I\.
'"
"\
'\
.
1M
100
10k
FREQUENCY _ Hz
10
Figure 7. Large Signal Frequency
Response
1M
Figure 6. Gain vs. Frequency
,
K"ppJ
'\
- - rt-
f'-..
"\
FREQUENCY _ Hz
lk
10k
lOOk
FREQUENCY - Hz
SINE WAVE'!
-i~ f\.
1\
,-
INPUT VOLTAGE _ V
r\
III I 1\1\f'.
10k
r\
.
f\
•
-.
/
/
~-
,
Figure 5. Input Bias Current vs.
Input Voltage
..U!.
I'
" 'M
..
Figure 8. PSRR vs. Frequency
,....
-10
TEMPERATURE _ "C
Figure 9. Normalized Gain vs.
Temperature, Gain = 1
....
'000
VI"
r--r--
10
..
Figure 2. Output Voltage Swing vs.
Resistive Load
,
,.
/
· L
,
"
LOAD RESISTANCE - n
l00nA
'oA
•
•
V
RL e 2kU
Figure 1. Output Voltage vs. Supply
Voltage, G = 16
,,..
-I-
V
v .,,...
SUPPLVYOLTAGE-
I-- f--
100
./
10k
FflEOUENCY _ Hz
'00'
Figure 10. Noise Spectral Density
4-40 INSTRUMENTATION AMPLIFIERS
....
-
-60
-
./
/
.. ..
TEMPERATURE _"C
Figure 11. Nonlinearity vs.
Temperature, Gain = 1
'40
Figure 12. Wideband Output Noise,
G= 16 (Amplified by 10)
Figure 13. Large Signal Pulse
Response and Settling Time*, G= 1
Figure 16. Small Signal Pulse
Response, G = 2
Figure 14. Small Signal Pulse
Response, G = 1
Figure 17. Large Signal Pulse
Response and Settling Time*, G=4
Figure 19. Large Signal Pulse
Response and Settling Time*, G=8
Figure 20. Small Signal Pulse
Response, G = 8
Figure 15. Large Signal Pulse
Response and Settling Time*, G = 2
Figure 18. Small Signal Pulse
Response, G =4
Figure 21. Large Signal Pulse
Response and Settling Time*,
G=16
,
,
/
/
",/
,
,
VI
-100 10
Figure 22. Small Signal Pulse
Response, Gain = 16
-,,
10
FREOUENCY - Hl
Figure 23. Total Harmonic Distortion
vs. Frequency, Gain = 16
FREOUENCY -
H~
Figure 24. Phase Distortion vs.
Frequency, Gain = 16
*For Settling Time Traces, 0.01% = 112 Vertical Division
INSTRUMENTATION AMPLIFIERS 4-41
//
iiV/
G"'~. 16
hi' "\"'2.8
7//
/ /
1
III
III
!"""
G_l
1M
10k
FREQUENCY _ Hz
Figure 25. Output Impedance vs.
Frequency
Figure 26. Gain Change Settling
Time*, Gain Change: 1 to 2
Figure 27. Gain Change Settling
Time*, Gain Change 1 to 4
*Scope Traces are:
Top: Output Transition
Middle: Output Settling
Bottom: Digital Input
Figure 29. Gain Change Settling
Time*, Gain Change 1 to 16
Figure 28. Gain Change Settling
Time*, Gain Change 1 to 8
r~;T~';X -,
I
I
I
7000 SERIES
SCOPE
7A13
~ :,:~~~~
~----
H---i<>I
\:
I
I
I
:
I
I
:
L ____ .J
V o =160xep-1'
SHIELD
NOTE COAX CABLE 1 FT OR LESS
Figure 30. Wideband Noise Test Circuit
+15V -15V
;O;TA- - - -,
I DYNAMICS
I
I
Tci~9EQUIVALENT
:
: ~~~TE~~~6~lSE I
r-----,
I
I
I
I
I
TEKTRONIX
I 700:C~~~ES
I
I
'I
7A13
I
PREAMP
I
5MHl BW
I
G
R'N,
1
56ku
2
28k!l
14kH
715H
348B
4
8
"
I
I
L ____ J
IN6263
G
1
2
4
,.
8
Figure 31. Settling Time Test Circuit
4-42 INSTRUMENTA TlON AMPLIFIERS
T,
12".5
12115
12IJ.s
14f,l.s
18fJ.s
Theory of Operation
r
THEORY OF OPERATION
The AD526 is a complete software programmable gain amplifier
(SPGA) implemented monolithically with a drift-trimmed BiFET
amplifier, a laser wafer trimmed resistor network, JFET analog
switches and TTL compatible gain code latches.
V'N
A particular gain is selected by applying the appropriate gain
code (see Table I) to the control logic. The control logic turns
on the JFET switch that connects the correct tap on the gain
network to the inverting input of the amplifier; all unselected
JFET gain switches are off (open). The "on" resistance of the
gain switches causes negligible gain error since only the amplifier's
input bias current, which is less than 150pA, actually flows
through these switches.
The AD526 is capable of storing the gain code, (latched mode),
B, AO, AI, A2, under the direction of control inputs CLK and
CS. Alternatively, the AD526 can respond directly to gain code
changes if the control inputs are tied low (transparent mode).
For gains of 8 and 16, a fraction of the frequency compensation
capacitance (CI in Figure 32) is automatically switched out of
the circuit. This increases the amplifier's bandwidth and improves
its signal settling time and slew rate.
---:M~F;'-
----,
I
I
I
I
A.
AI
A2
------;--t_
I
Ig
lI~
~I~
~
elK
Os
+v,
34k
Il
I
I
I
I
•
RESISTOR
NETWORK
0=2
~I~
I?
Ie
17k
G=4
DIGITAL
1k
GND
17k
ANALOG
ANALOG
GND1
GN02
Figure 32. Simplified Schematic of the AD526
TRANSPARENT MODE OF OPERATION
In the transparent mode of operation, the AD526 will respond
directly to level changes at the gain code inputs (AO, AI, A2) if
B is tied high and both CS and CLK are allowed to float low.
After the gain codes are changed, the AD526's output voltage
typically requires 5.5f1s to settle to within 0.01% of the fmal
value. Figures 26 to 29 show the performance of the AD526 for
positive gain code changes.
LATCHED MODE OF OPERATION
The latched mode of operation is shown in Figure 34. When
either CS or CLK go to a logic "1," the gain code (AO, AI, A2,
B) signals are latched into the registers and held until both CS
and CLK return to "0." Unused CS or CLK inputs should be tied
to ground. The CS and CLK inputs are functionally and electrically
equivalent.
.
TIMING SIGNAL - - - - - - - - - - - -......- - - - - - - - - - - - - - - - -
Al--~------------~-------------
A2 -------------t--~------------
AI --~--------_t--~------------
AO--1---~--------~--------------
A.--~--._----_t--~-------------
A2----------------~--------------
+v,
+V,
+5V
I
I
I
",VOUT
I
.... vou,
I
V'N - - - - - - - - - "
Figure 33. Transparent Mode
V'N - - - - - - - - - '
Figure 34. Latched Mode
INSTRUMENTATION AMPLIFIERS 4-43
TIMING AND CONTROL
GAIN CODE
CONTROL
CONDITION
A2
Al
AO
B
CLK (CS= 0)
Gain
X
0
0
0
0
1
X
X
0
0
0
0
1
X
0
0
1
1
X
X
X
0
0
1
1
X
X
0
1
0
1
X
X
X
0
X
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
1
1
1
1
Previous State
1
2
4
8
16
1
1
1
2
4
8
16
0
1
X
Condition
Latched
Transparent
Transparent
Transparent
Transparent
Transparent
Transparent
Latched
Latched
Latched
Latched
Latched
Latched
NOTE: X ~ Don't Care
Table I. AD526 Logic Input Truth Table
The specifications on page 3 in combination with Figure 35 give
the timing requirements for loading new gain codes.'
DIGITAL FEEDTHROUGH
With either CS or CLK or both held high, the AD526 gain
state will remain constant regardless of the transitions at the AO,
AI, A2 or B inputs. However, high-speed logic transitions will
unavoidably feed through to the analog circuitry within the
AD526 causing ,spikes to occur at the signal output.
This feedthrough effect can be completely eliminated by operating
the AD526 in the transparent mode and latching the gain code
in an external bank of latches (Figure 36),
Tc =MINIMUM CLOCK CYCLE
Ts=DATASETUPTIME
TH = DATA HOLD TIME
NOTE THRE~OLD LEVEL FOR
GAIN CODE. es,
ANDCLKIS1.4V
To operate the AD526 using serial inputs, the configuration
shown in Figure 36 can be used with the 74LS174 replaced by a
serial-in/parallel-out latch, such as the 54LS594.
Figure 35. AD526 Timing
A1
AO
A2
+5V
TIMING
SIGNAL
. . . . VOUT
I
I
Figure 36. Using an External Latch to Minimize Digital
Feedthrough
4-44 INSTRUMENTATION AMPLIFIERS
GROUNDING AND BYPASSING
Proper signal and grounding techniques must be applied in
board layout so that specified performance levels of precision
data acquisition components, such as the AD526, are not
degraded.
As is shown in Figure 37, logic and signal grounds should be
separate. By connecting the signal source ground locally to the
AD526 analog ground Pins 5 and 6, gain accuracy of the AD526
is maintained. This ground connection should not be corrupted
by currents associated with other elements within the system.
CASCADED OPERATION
A cascade of two AD526s can be used to achieve binarily weighted
gains from 1 to 256. If gains from 1 to 128 are needed, no additional
components are required. This is accomplished by using the B
pin as shown in Figure 38. When the B pin is low, the AD526
is held in a unity gain stage independent of the other gain code
values.
VOUTNIN
Utilizing the force and sense outputs of the AD526, as shown in
Figure 38, avoids signal drops along etch runs to low impedance
loads.
A2
Al
AO
0
0
0
0
I
1
0
0
1
1
0
0
0
I
0
1
0
I
0
I
I
2
4
8
16
32
64
128
Table II. Logic Table for Figure 38
Figure 37. Grounding and Bypassing
CLK------------~--------------------------------_,
~------------~--~-----------------------------+------,
Al=~==:;======~=4====================~_,
AO
-v,
-v,
Figure 38. Cascaded Operation
INSTRUMENTA TION AMPLIFIERS 1H15
OFFSET NULLING
Input voltage offset nulling of the AD526 is best accomplished
at a gain of 16, since the referred-to-input CRTI) offset is amplified
the most at this gain and therefore is most easily trimmed. The
resulting trimmed value of RTI voltage offset typically varies
less than 3",V across all gain ranges.
Note that the low input current of the AD526 minimizes RTI
voltage offsets due to source resistance.
+V,
OFFSET NULLING WITH A D/A CONVERTER
Figure 41 shows the AD526 with offset nulling accomplished
with an 8-bit D/A converter CAD7524) circuit instead of the
potentiometer shown in Figure 39. The calibration procedure is
the same as before except that instead of adjusting the potentiometer, the DIA converter corrects for the offset error. This
calibration circuit has a number of benefits in addition to eliminating the trimpot. The most significant benefit is that calibration
can be under the control of a microprocessor and therefore can
be implemented as part of an autocalibration scheme. Secondly,
dipswitches or RAM can be used to hold the 8-bit word after its
value has been determined. In Figure 42 the offset null sensitivity,
at a gain of 16, is 80",V per LSB of adjustment, which guarantees
dc accuracy to the 16-bit performance 1e'!el.
"VOUT
I
~UT
V'N---f-...J
+v,
Figure 39. Offset Voltage Null Circuit
OUTPUT CURRENT BOOSTER
The AD526 is rated for a full ± 10V output voltage swing into
2kfl. In some applications, the need exists to drive more current
into heavier loads. As shown in Figure 40, a high current booster
may be connected "inside the loop" of the SPGA to provide the
required current boost without significantly degrading overall
performance. Nonlinearities, offset and gain inaccuracies of the
buffer are minimized by the loop gain of the AD526 output
amplifier.
+v,
Figure 40. Current Output Boosting
4-46 INSTRUMENTA TlON AMPLIFIERS
-v,
ALL BYPASS CAPACITORS ARE 0 1 j.lF
MfS
LSB
cs
WR
Figure 41. Offset Nulling Using a OAC
Applications
FLOATING-POINT CONVERSION
High resolution converters are used in systems to obtain high
accuracy, improve system resolution or increase dynamic range.
There are a number of high resolution conveners available with
throughput rates of 66.6kHz that can be purchased as a single
component solution; however in order to achieve higher
throughput rates, alternative conversion techniques must be
employed. A floating point AID convener can improve both
throughput rate and dynamic range of a system.
In a floating point AID converter (Figure 42), the output data is
presented as a 16-bit word, the lower 12 bits from the AID
convener form the mantissa and the upper 4 bits from the digital
signal used to'set the gain form the exponent. The AD526 programmable gain amplifier in conjunction with the comparator
circuit scales the input signal to a range between half scale and
full scale for the maximum usable resolution.
The AID convener diagrammed in Figure 42 consists of a pair
of AD585 sample/hold amplifiers, a flash convener, a five-range
programmable gain amplifier (the AD526) and a fast 12-bit AID
converter (the AD7572). The floating-point AID converter achieves
its high throughput rate of 125kHz by overlapping the acquisition
time of the first sample/hold amplifier and the settling time of
the AD526 with the conversion time of the AID converter. The
first sample/hold amplifier holds the signal for the flash autoranger,
which determines which binary quantum the input falls within,
relative to full scale. Once the AD526 has settled to the appropriate
level, then the second sample/hold amplifier can be put into
hold which holds the amplified signal while the AD7572 performs
its conversion routine. The acquisition time for the AD585 is
3....s, and the conversion time for the AD7572 is 5....s for a total
of 8 ....s, or 125kHz. This performance relies on the fast settling
characteristics of the AD526 after the flash autoranging (comparator) circuit quantizes the input signal. A 16-bit register
holds the 3-bit output from the flash autoranger and the 12-bit
output of the AD7572.
The AID converter in Figure 42 has a dynamic range of %dB.
The dynamic range of a convener is the ratio of the full-scale
input range to the LSB value. With a floating-point AID convener
the smallest value LSB corresponds to the LSB of the monolithic
convener divided by the maximum gain of the PGA. The floating
point AID converter has a full-scale range of 5V, a maximum
gain of 16VN from the AD526 and a 12-bit AID convener; this
produces:
LSB = ([FSRl2N]/Gain) = ([5V14096]/16) = 76 ....V. The dynamic
range in dBs is based on the log of the ratio of the full-scale
input range to the LSB; dynamic range = 2010g(5VI76 ....V) =
96dB.
-15V +5V
06
05
04
03
02
01
AO
El
A'
E2
A2
E3
NOTE ALLBYPASSCAPACITORSAREO 1pF
Figure 42. Floating-Point AID Converter
INSTRUMENTA TlON AMPLIFIERS 1HZ7
HIGH ACCURACY AID CONVERTERS
Very high accuracy and high resolution floating-point AID converters can be achieved by the incorporation of offset and gain
calibration routines. There are two techniques commonly used
for calibration, a hardware circuit as shown in Figure 43 and/or
a software routine. In this application the tnicroprocessor is
.
functioning as the autoranging circuit, requiring software overhead; therefore, a hardware calibration technique was applied
which reduces the software burden. The software is used to set
the gain of the AD526. In operation the signal is converted, and
if the MSB of the AD574 is not equal to a logical I, the gain is
increased by binary steps, up to the maximum gain. This maximizes
the full-scale range of the conversion process and insures a wide
dynatnic range.
The calibration technique uses two point correction, offset and
gain. The hardware is simplified by the use of programmable
magnitude comparators, the 74ALS528s, which can be "burned"
for a particular code. In order to prevent under or over range
hunting during the calibration process, the reference offset and
gain codes should be different from the endpoint codes. A calibration cycle consists of selecting whether gain or offset is to be
calibrated then selecting the appropriate multiplexer channel to
apply the reference voltage to the signal channel. Once the
operation has been initiated, the counter, a 74ALS869, drives
the DIA converter in a linear fashion providing a sma1I correction
voltage to either the gain or offset trim point of the AD574.
The output of the AID converter is then compared to the value
preset in the 74ALS528 to determine a match. Once a match is
detected, the 74ALS528 produces a low going pulse which stops
the counter. The code at the DIA converter is latched until the
next calibration cycle. Calibration cycles are under the control
of the tnicroprocessor in this application and should be implemented only during periods of converter inactivity.
Figure 43. High Accuracy AID Converter
~
INSTRUMENTA nON AMPLIFIERS
IIIIIIIIIII ANALOG
WDEVICES
Precision Instrumentation Amplifier
AD624 I
FEATURES
Low Noise: 0.2fJ,V pop 0.1Hz to 10Hz
Low Gain TC: 5ppm max (G = 1)
Low Nonlinearity: 0.001% max (G = 1 to 200)
High CMRR: 130dB min (G
500 to 1000)
Low Input Offset Voltage: 25fJ,V, max
Low Input Offset Voltage Drift: 0.25fJ,VfC max
Gain Bandwidth Product: 25MHz
Pin Programmable Gains of 1, 100,200,500,1000
No External Components Required
Internally Compensated
AD624 FUNCTIONAL BLOCK DIAGRAM
=
PRODUCT DESCRIPTION
The AD624 is a high precision low noise instrumentation amplifier
designed primarily for use with low level transducers, including
load cells, strain gauges and pressure transducers. An outstanding
combination oflow noise, high gain accuracy, low gain temperature
coefficient and high linearity make the AD624 ideal for use in
high resolution data acquisition systems.
The AD624C has an input offset voltage drift of less than 0.251LVI
°C, output offset voltage drift of less than lOlLV/oC, CMRR
above 80dB at unity gain (BOdB at G = 500) and a lIIa1(imum
nonlinearity of 0.001% at G= 1. In addition to these outstanding
dc specifications the AD624 exhibits superior ac performance as
well. A 25MHz gain bandwidth product, 5V/ILs slew rate and
15 ILS settling time permit the use of the AD624 in high speed
data acquisition applications.
The AD624 does not need any external components for pretrimmed gains of 1, 100, 200, 500 and 1000. Additional gains
such as 250 and 333 can be programmed within one percent
accuracy with external jumpers. A single external resistor can
also be used to set the 624's gain to any value in the range of 1
to 10,000.
PRODUCT HIGHLIGHTS
1. The AD624 offers outstanding noise performance. Input
noise is typically less than 4nVIYHZ at 1kHz.
2. The AD624 is a functionally complete instrumentation amplifier. Pin programmable gains of 1, 100, 200, 500 and 1000
are provided on the chip. Other gains are achieved through
the use of a siugle external resistor.
3. The offset voltage, offset voltage drift, gain accuracy and
gain temperature coefficients are guaranteed for all pre-trimmed
gains.
4. The AD624 provides totally independent input and output
offset nulling terminals for high precision applications. This
minimizes the effect of offset voltage in gain ranging
applications.
5. A sense terminal is provided to enable the user to minimize
the errors induced through long leads. A reference terminal
is also provided to permit level shifting at the output.
INSTRUMENTA TlON AMPLIFIERS 4-49
SPECIFICATIONS
(@ Vs
= ± 15V. RL
= 2k0 and TA = + 25"1: unless otherwise specified)
Model
AD624A
l)p
AD624B
MiD
Tn>
[~+1]±20%
[
4O~000 +
1 to 1000
1001000
MiD
Mas
M ..
AD624C
l)p
AD624S
MiD
Tn>
[~+1]±20%
[
4O~000 +
1 to 1000
1 to 1000
MiD
Mas
M ..
Units
GAIN
Gain Equation
(External ResistorGain
Prognmming)
Gain Range (Pin Programmable)
Gain Error
±0.01
±o.I5
±0.15
±I.O
±0.02
±O.I
±0.25
±I.O
±O.OS
±0.25
±0.5
±I.O
%
%
%
%
±0.005
±0.005
±0.005
±O.O03
±O.OO3
±O.OO5
±O.OOI
±O.OOI
±0.005
±0.005
±0.005
%
%
%
5
5
5
10
10
10
25
15
IS
5
10
IS
ppmrc
ppmlOC
ppmI"C
200
2
5
50
75
0.5
1
25
25
0.25
2
10
75
2.0
1
50
"V
"VfC
mV
G~
100
G ~ 200,500
G ~ 1000
Nonlinearity
G~I
G ~ 100,200
G = 500,1000
Gain vs. Temperature
G~I
~
~
100,200
500,1000
VOLTAGE OFFSET (May be Nulled)
Input Offset Voltage
vs. Temperature
Output Offset Voltage
vs. Temperature
Offset Referred to the
I] ±20%
±0.05
±0.25
±0.5
±I.O
G~I
G
G
I] ±20%
±O.OO5
"VIOC
Inputvs. Supply
G~I
G
G
~
~
100,200
500,1000
75
lOS
110
70
95
100
dB
dB
dB
75
lOS
110
80
110
115
INFUTCURRENT
Input Bias Current
vs. Temperature
Input Offset Current
VS. Temperature
±20
±20
,.20
nA
pAre
nA
pAre
10'
10
10'
n
10
10'
10
n
10
10'
10
10'
10
±IO
±IO
±IO
±25
±50
±50
±15
±50
±50
±IO
±15
±20
±50
±15
±50
±15
INPUT
Input Impedance
Dlfferential Resistance
10'
10
10'
10
Dnferennai Capacitance
Common·Mode Resistance
Common.ModeCapacitance
10'
Input Voltage Range
OUTPUT RATING
VoUT,RL = 2k!l
pF
/
Max Differ. Input Linear (V D)
Max Common-Mode Linear (VeM)
Common-Mode ReJection de
to 60Hz with IkO Source Imbalance
G~ I
G ~ 100,200
G ~ 500,1000
pF
±IO
12V-(¥XVo )
70
100
110
12V -(~XVD)
12V - ( ¥ XVo )
75
lOS
120
12V-(¥XVo )
110
130
V
dB
dB
dB
70
100
110
80
V
±IO
±IO
±10
±IO
V
I
ISO
100
50
25
I
ISO
100
SO
25
I
ISO
100
50
25
I
150
100
SO
25
MHz
kHz
DYNAMIC RESPONSE
Small Signal - 3dB
G~I
G~
G
G
G
~
~
~
100
200
500
1000
4-50 INSTRUMENTATION AMPLIFIERS
kHz
kHz
kHz
Model
AD624A
MiD
1)p
Max
Min
AD624B
Typ
Max
Min
AD624C
Typ
AD624S
Max
Min
1)p
Max
Vaita
Slew Rate
50
50
50
5.0
V/J.Ls
SetdmgTlDlCtoO.Ol%, 20V Step
G:II0200
G: 500
G: 1000
15
35
75
15
35
75
15
35
75
15
35
75
~,
4
75
4
75
4
75
4
75
nVNHZ
nVNHZ
10
0.3
02
10
03
02
10
03
02
10
03
02
~Vp·p
60
60
60
60
pAp·p
\
~,
~.
NOISE
Voltage NOise, 1kHz
RT.I.
RTO.
R.T I ,O.1tolOHz
G:I
G:lOO
G: 200, 500, 1000
p.Vp-p
~Vp·p
Current NOIse
O.lHzto 10Hz
SENSE INPUT
RJN
8
lIN
Vollage Range
Gam to Output
10
30
12
~1O
8
10
30
12
8
12
8
10
30
12
kll
~A
~1O
I
I
I
10
30
~1O
±lO
V
I
%
REFERENCE INPUT
RJN
16
lIN
Voltage Range
Storage
POWER SUPPLY
Power Supply Range
QuIescent Current
PACKAGE I
Ceranuc(D·16)
NOTES
'See SectlOn 16 for package outlme Information
Spectficauons subJeCt to change Without nouce
24
~1O
Gam to Output
TEMPERATURE RANGE
Spearocd Perlormance
20
30
16
24
16
-25
-65
I
~15
35
AD624A
+85
+150
-25
±IS
5
±6
20
30
24
16
+85
+ 150
-25
-65
~15
±lS
±6
3.5
5
± 15
35
+85
+150
-55
-65
±lS
5
±6
AD624C
AD624B
24
kll
~A
V
%
I
I
-65
20
30
~1O
~1O
~1O
I
±6
20
30
±15
35
+ 125
+150
Of:
Of:
±lS
5
V
mA
AD624S
SpeclflC8tlons shown In boldface are tested on all production umts at final
electncal test. Results from those tests are used to calculate outgomg quality
levels AIiIDID.and max speaficatlons are guaranteed, although only those
shown In boldface are tested on all prodUCtion umts
PIN CONFIGURATION
RG,
QUTPUTNUU
OUTPUT NULL
G: 'GO} :~~
SHORT TO
0=200
GAIN
G:: 500
SENSE
FOR GAIN OF 1000 SHORT RG, TO PiN 12
AND ptNS 11 AND 13 TO RGl!
INSTRUMENTATION AMPLIFIERS 4--51
Typical Characteristics
•
30
20
L ..
6
V
/
•
V
••
/
5
•
v.:c
5
V
0
10
15
SUPPLY VOLTAGE - tV
,.
V
>
~
Figure 2. Output Voltage Swing vs.
Supply Voltage
15
!O
20
SUPPLY VOLTAGE - tV
- - r---
20
,.
-,.
4
-20
2
-30
•
5
10
15
-40
20
Figure 4. Quiescent Current vs.
Supply Voltage
Figure 5. Input Bias Current vs.
Supply Voltage
'4
0
,
•
'Ok
n
40
-75
-25
25
TEMPERATURE _oc
POWER SUPPLY VOLTAGE - t.V
,.
111
30
•
•
100
LOAD RESISTANCE -
Figure 3. Output Voltage Swing vs.
Resistive Load
,
•
•
/
V
•'0
15
-:tv
2
!
•
2
V
4
•
-
i
•
•
I-
•
10
SUPPLY VOLTAGE
20
Figure 1. Input Voltage Range vs.
Supply Voltage, G = 1
/
V
/
.
"
2
V
"6
75
Figure 6. Input Bias Current vs.
Temperature
V
V
~ 100
,
~
3
4
10
5
2
•
10
INPUT VOLTAGE -
15
20
±v
G "" SOD
=
-,
30
40
5,0
80
70
80
Figure 8. Offset Voltage, R77, Tum
On Drift
30
IG.L
1\
•
G= ,
,
20
DO
.
!B -80
10
WARM-UP TIME _ MINUTES
Figure 7. Input Bias Current vs.
CMV
-'20
•
•
Ll.
.
,
10
100
111
10t
lOOk
FREQUENCY - Hz
1M
10M
Rgure 10. CMRR vs. Frequency R77,
Zero to lk Source Imbalance
4-52 INSTRUMENTATION AMPLIFIERS
•
Ok
10k
FREQUENCY - Hz
lOOk
I
t"--. ~
~
~ ...............
........
........ a.l
...............
40
Figure 11. Large Signal Frequency
Response
10M
G ..
60
'M
1M
Iv. = '-15VJ.. -
so
BTIrjTt\):r
lOOk
10k
1VPIPSINEWAVE
2Or-- i""-
I
Gl000 •
111
FREQUENCY _ Hz
40
i\
-2.
100
••
1\
•
10
Figure 9. Gain vs. Frequency
DO
1-..
-40
•,
~
•,.
100
1k
.......
10k
FREQUENCY - Hz
Figure 12. Positive PSRR vs.
Frequency
'00k
,.
...
,
0
l_ vs=l_lsvt+ t--1VPIPSINEWAVE -
140
120
,.
.
..
0
......
I
I'-- ~
r-....
G"
r--
G'k
40
0,.
100
lk
I"-.
"-
r--...
r--...
r--....
0
1000'I---+--+------1f--+----l
.....
10k
FREQUENCY - Hz
...
,
Figure 13. Negative PSRR vs.
Frequency
"!-,----:'='=0--",,.""0---,J1k~-..,J'Ok~-.,.J,00k
'" '"
0
10
FREQUENCY - Hz
-12 TO 12
!s
I
~
-8TO
I
•
-4TO 4
l
OUTPUT
STEP- V
4TO - 4
8TO -
•
12 TO -1 2
Figure 16. Low Frequency Voltage
Noise- G = 1 (System Gain = 1000)
Figure 17. Low Frequency Voltage
Noise - G = 1000 (System Gain =
100,000)
-12T01 2
-&TO
.,%
/10/,
•
-4TO 4
/
,...
Figure 15. Input Current Noise
Figure 14. RTf Noise Spectral
Density vs. Gain
It>!lv
10k
FREQUENCY - Hz
.,.
",
l7
If
/
I' If
"
I
00'%
V
,
I,
\ "'"
./
~
.,,,
....... 001%
10
16
20
SETILING TIME - p.s
Figure 18. Settling Time Gain
11 00'%
/ I
/
OUTPUT
STB'_V
\
.no- 4
BTO-
\
\ \
•
,,%
'"
12TO-1 2
001%
.
'5
10
Figure 19. Large Signal Pulse
Response and Settling TimeG = 1
SETTLING TIME- ....
100
Figure 20. Settling Time Gain
Figure 21. LargeSignalPulse
Response and Settling Time
G = 100
-12T01 2
-BTO
•
I
-4TO 4
/~'%
'"
V
/
001%
7
OUTPUT
STEP-V
4TO- 4
BTO-
r\
'"
lnO-l 2
Figure 22. Range Signal Pulse
Response and Settling Time
G = 500
"-
\
•
10
~
~
q
\
\.,,,
~
001%
~
~
•
SETIUNGTlME- p.s
Figure 23. Settling Time Gain = 1000
Figure 24. Large Signal Pulse
Response and Settling Time
G = 1000
INSTRUMENTA TlON AMPLIFIERS 4--53
10kll
1%
1kll
10T
10kll
1%
INPUT
20V p-p
100kH
Figure 25. Settling Time Test Circuit
Theory of Operation
The AD624 is a monolithic instrumentation amplifier based on
a modification of the classic three-op-amp instrumentation amplifier. Monolithic construction and laser-wafer-trimming allow
the tight matching and tracking of circuit components and the
high level of performance that this circuit architecture is capable
of.
A preamp section (QI-Q4) develops the programmed gain by
the use of feedback concepts. Feedback from the outputs of Al
and A2 forces the collector currents of QI-Q4 to be constant
thereby impressing the input voltage across RG.
The gain is set by choosing the value of ~ from the equation,
Gain = ~Ok + 1. The value of RG also sets the transconductance
of the inp'tt preamp stage increasing it asymptotically to the
transconductance of the input transistors as RG is reduced for
larger gains. This has three important advantages. First, this
approach allows the circuit to achieve a very high open loop
gain of 3 x 108 at a programmed gain of 1000 thus reducing gain
related errors to a negligible 3ppm. Second, the gain bandwidth
product which is determined by C3 or C4 and the input transconductance, reaches 2SMHz. Third, the input voltage noise
reduces to a value determined by the collector current of the
input transistors for an RTI noise of 4nV/vRZ at G ;;. SOO.
Figure 26. Noise Test Circuit
INPUT CONSIDERATIONS
Under input overload conditions the user will see RG + 1000
and two diode drops (-1.2V) between the plus and minus inputs,
in either direction. If safe overload current under all conditions
is assumed to be lOrnA, the maximum overload voltage is - ±2.SV.
While the AD624 can withstand this continuously, momentary
overloads of ± lOY will not harm the device. On the other hand
the inputs should never exceed the supply voltage.
4-54 INSTRUMENTATION AMPLIFIERS
Figure 27. Simplified Circuit of Amplifier; Gain is Defined as
((R56 + R57)I(RG) + 1. For a Gain of 1, RG is an Open Circuit.
The ADS24 should be considered in applications that require
protection from severe input overload. If this is not possible,
external protection resistors can be put in series with the inputs
of the AD624 to augment the internal (SOO) protection resistors.
This will most seriously degrade the noise performance. For this
reason the value of these resistors should be chosen to be as low
as possible and still provide lOrnA of current limiting under
maximum continuous overload conditions. In selecting the value
of these resistors, the internal gain setting resistor and the 1.2
volt drop need to be considered. For example, to protect the
device from a continuous differential overload of 20V at a gain
of 100, 1.9kO of resistance is required. The internal gain resistor
is 4040; the internal protect resistor is 1000. There is a 1.2V
drop across D I or D2 and the base-emitter junction of either
Ql and Q3 or Q2 and Q4 as shown in Figure 27, 14000
of external resistance would be required (700n in series with
each input). The RTI noise in this case would be
v'4KTRext. + (4nV/vRZ)2 = 6.2nV/vRZ.
INPUT OFFSET AND OUTPUT OFFSET
Voltage offset specifications are often considered a figure of
merit for instrumentation amplifiers. While initial offset may be
adjusted to zero, shifts in offset voltage due to temperature
variations will cause errors. Intelligent systems can often correct
for this factor with an auto-zero cycle, but there are many smallsignal high-gain applications that don't have this capability.
Voltage offset and offset drift each have two components; input
and output. Input offset is that component of offset that is
Applying the AD624
Temperature
Gain
Coefficient
Pin 3
(Nominal) (Nominal)
to Pin
directly proportional to gain i.e., input offset as measured at the
output at G = 100 is 100 times greater than at G = 1. Output
offset is independent of gain. At low gains, output offset drift is
dominant, while at high gains input offset drift dominates.
Therefore, the output offset voltage drift is normally specified
as drift at G = 1 (where input effects are insignificant), while
input offset voltage drift is given by drift specification at a high
gain (where output offset effects are negligible). All input-related
numbers are referred to the input (RTI) which is to say that the
effect on the output is "G" times larger. Voltage offset vs. power
supply is also specified at one or more gain settings and is also
RTI.
1
100
125
137
186.5
200
250
333
375
500
624
688
831
1000
By separating these errors, one can evaluate the total error independent of the gain setting used. In a given gain configuration
both errors can be combined to give a total error referred to the
input (R.T.I.) or output (R.T.O.) by the following formula:
-I.SppmrC
-l.SppmrC
-5ppm/oC
-S.SppmrC
-6.5ppmrC
-3.SppmrC
-S.Sppm/oC
-ISppmrC
-O.SppmrC
-lOppmrC
-SppmrC
-I.Sppml°C
+4ppml°C
OppmrC
Total Error R.T.1. = input error + (output error/gain)
Total Error R.T.O. = (Gain x input error) + output error
As an illustration, a typical AD624 might have a + 2S0fLV output
offset and a - SOfLV input offset. In a unity gain configuration,
the total output offset would be 200fLV or the sum of the two.
At a gain of 100, the output offset would be -4.75mV or:
+2S0fLV + 100(-SOfLV) = -4.7SmV.
The AD624 provides for both input and output offset adjustment.
This optimizes nulling in very high precision applications and
minimizes offset voltage effects in switched gain applications. In
such applications the input offset is adjusted first at the highest
programmed gain, then the output offset is adjusted at G = 1.
GAIN
The AD624 includes high accuracy pre-trimmed internal gain
resistors. These allow for single connection programming of
gains of I, 100,200 and 500. Additionally, a variety of gains
including a pre-trimmed gain of 1000 can be achieved through
series and parallel combinations of the internal resistors. Table I
shows the available gains and the appropriate pin connections
and gain temperature coefficients.
The gain values achieved via the combination of internal resistors
are extremely useful. The temperature coefficient of the gain is
dependent primarily on the mismatch of the temperature coefficients of the various internal resistors. Tracking of these resistors
is extremely tight resulting in the low gain TC's shown in
Table I.
If the desired value of gain is not attainable using the internal
resistors, a single external resistor can be used to achieve any
gain between 1 and 10,000. This resistor connected between
+v,
Connect Pins
13
13
13
13
12
12
12
12
11
11
11
11
11
11 to 16
11 to 12
11 to 12 to 16
Ilto13
J.l to 16
13 to 16
13 to 16
11 to 12; 13 to 16
16 to 12
16 to 12; 13 to 11
Table I.
pins 3 and 16 programs the gain according to the formula
~
= G4~ 1 (see Figure 29). For best results RG should be a
precision resistor with a low temperature coefficient. An external
RG affects both gain accuracy and gain drift due to the mismatch
between it and the internal thin-film resistors RS6 and RS7.
Gain accuracy is determined by the tolerance of the external Ro
and the absolute accuracy of the internal resistors (± 20%). Gain
drift is determined by the mismatch of the temperature coefficient
of RG and the temperature coefficient of the internal resistors
(-ISppml°C typ), and the temperature coefficient of the internal
interconnections.
+v,
-INPUT
~'
RG,
OR
2105kU
1kU
RG,
REFERENCE
+INPUT
-v,
G=~+1"'20±20%
Figure 29. Operating Connections for G = 20
The AD624 may also be configured to provide gain in the output
stage. Figure 30 shows an H pad attenuator connected to the
reference and sense lines of the AD624. The values of RI, R2
and R3 should be selected to be as low as possible to minimize
the gain variation and reduction of CMRR. Varying R2 will
precisely set the gain without affecting CMRR. CMRR is determined by the match of RI and R3.
+v,
R1
6kU
-INPUT C > - - - - - - - {
-INPUT
R2
o-------t
Ok"
1).......j......--~--oVOUT
VOUT
G
=
RG,
500
OUTPUT
L-_ _-o SIGNAL
COMMON
RG,
+ INPUT O - - - - - - {
+ INPUT C > - - - - - - - {
R3
SkU
-v,
-v,
Figure 28. Operating Connections for G =200
Figure 30. Gain of 2500
INSTRUMENTATION AMPLIFIERS 4-55
NOISE
The AD624 is designed to provide noise performance near the
theoretical noise floor. This is an extremely important design
criteria as the front end noise 'Of an instrumentation amplifier is
the ultimate limitation on the resolution of the data acquisition
system it is being used in. There are two sources of noise in an
instrument amplifier, the input noise, predominantly generated
by the differential input stage, and the output noise, generated
by the output amplifier. Both of these components are present
at the input (and output) of the instrumentation amplifier. At
the input, the input noise will appear unaltered; the output
noise will be attenuated by the closed loop gain (at the output,
the output noise will be unaltered; the input noise will be amplified
by the closed loop gain). Those two noise sources must be root
sum squared to determine the total noise level expected at the
input (or output).
The low frequency (0.1 to 10Hz) voltage noise due to the output
stage is 10ftV p.p, the contribution of the input stage is 0.2ft V
p-p. At a gain of 10, the RTI voltage noise would be lftV p-p,
'"V1(10\2
. would be 1O.2ftV
r.J + (0.2)2. The RTO voltage nOIse
p-p, Q:)10 2 + (0.2 (G»2. These calculations hold for applications
using either internal or external gain resistors.
INPUT BIAS CURRENTS
Input bias currents are those currents necessary to bias the
input transistors of a dc amplifier. Bias currents are an additional
source of input error and must be considered in an total error
budget. The bias currents when multiplied by the source resistance
imbalance appear as an additional offset voltage. (What is of
concern in calculating bias current errors is the change in bias
current with respect to signal voltage and temperature.) Input
offset current is the difference between the two input bias currents.
The effect of offset current is an input offset voltage whose
magnitude is the offset current times the source resistance.
Although instrumentation amplifiers have differential inputs,
there must be a return path for the bias currents. If this is not
provided, those currents will charge stray capacitances, causing
the output to drift uncontrollably or to saturate. Therefore,
when amplifying "floating" input sources such as transformers
and thermocouples, as well as ac-coupled sources, there must
still be a dc path from each input to ground, (see Figure 31).
~~
__________________
GROUND
Figure 31c. AC Coupled
Figure 31. Indirect Ground Returns for Bias Currents
COMMON-MODE REJECTION
Common-mode rejection is a measure of the change in output
voltage when both inputs are changed by equal amounts. These
specifications are usually given for a full-range input voltage
change and a specified source imbalance. "Common-Mode Rejection Ratio" (CMRR) is a ratio expression while "Common-Mode
Rejection" (CMR) is the logarithm of that ratio. For example, a
CMRR of 10,000 corresponds to a CMR of 80dB.
In an instrumentation amplifier, ac common-mode rejection is
only as good as the differential phase shift. Degradation of ac
common-mode rejection is caused by unequal drops across differing
track resistances and a differential phase shift due to varied
stray capacitances or cable capacitances. In many applications
shielded cables are used to minimize noise. This technique can
create common-mode rejection errors unless the shield is properly
driven. Figures 32 and 33 shows active data guards which are
configured to improve ac common-mode rejection by "bootstrapping" the capacitances of the input cabling, thus minimizing
differential phase shift.
VOUl
-v,
Figure 32. Shield Driver, G
+v,
TO POWER
"- SUPPLY
4-~
~
100
J
TO POWER
SUPPLY
...._ _ _ _ _ _ _ _ _ _ _-'"...,_ GROUND
Figure 31a. Transformer Coupled
Figure 33. Differential Shield Driver
! -_ _ _ _ _ _ _ _ _ _ _-',..._
Figure 31b. Thermocouple
4-56 INSTRUMENTATION AMPLIFIERS
TO POWER
SUPPLY
GROUND
GROUNDING
Many data-acquisition components have two or more ground
pins which are not connected together within the device. These
grounds must be tied together at one point, usually at the system
power supply ground. Ideally, a single solid ground would be
desirable. However, since current flows through the ground
wires and etch stripes of the circuit cards, and since these paths
have resistance and inductance, hundreds of millivolts can be
generated between the system ground point and the data acquisition
components. Separate ground returns should be provided to
DIGITAL
DATA
OUTPUT
* RETURN
IF INDEPENDENT, OTHERWISE
AMPLIFIER REFERENCE
TO MECCA AT ANALOG P S COMMON
Figure 34. Basic Grounding Practice
minimize the current flow in the path from the most sensitive
points to the system ground point. In this way supply currents
and logic-gate return currents are not summed into the same
return path as analog signals where they would cause measurement
errors (see Figure 34).
Since the output voltage is developed with respect to the potential
on the reference terminal an instrumentation amplifier can solve
many grounding problems.
SENSE TERMINAL
The sense terminal is the feedback point for the instrument
amplifier's output amplifier. Normally it is connected to the
instrument amplifier output. If heavy load currents are to be
drawn through long leads, voltage drops due to current flowing
through lead resistance can cause errors. The sense terminal can
be wired to the instrument amplifier at the load thus putting the
IxR drops "inside the loop" and virtually eliminating this error
source.
Figure 36. Use of Reference Terminal to Provide Output
Offset
When the IA is of the three-amplifier configuration it is necessary
that nearly zero impedance be presented to the reference terminal.
Any significant resistance, including those caused by PC layouts
or other connection techniques, which appears between the
reference pin and ground will increase the gain of the noninverting
signal path, thereby upsetting the common-mode rejection of
the IA. Inadvertent thermocouple connections created in the
sense and reference lines should also be avoided as they will
directly affect the output offset voltage and output offset voltage
drift.
In the AD624 a reference source resistance will unbalance the
CMR trim by the ratio of IOk!1lRREF • For example, if the reference
source impedance is In, CMR will be reduced to 80dB (IOkn/
In = 80dB). An operational amplifier may be used to provide
that low impedance reference point as shown in Figure 36. The
input offset voltage characteristics of that amplifier will add
directly to the output offset voltage performance of the instrumentation amplifier.
An instrumentation amplifier can be turned into a voltage-to-current converter by taking advantage of the sense and reference
terminals as shown in Figure 37.
+ INPUT
-INPUT
Figure 35. AD624 Instrumentation Amplifier with Output
Current Booster
Typically, IC instrumentation amplifiers are rated for a full
± 10 volt output swing into 2kn. In some applications, however,
the need exists to drive more current into heavier loads. Figure
35 shows how a current booster may be c!Jnnected "inside the
loop" of an instrumentation amplifier to provide the required
current without significantly degrading overall performance.
The effects of nonlinearities, offset and gain inaccuracies of the
buffer are reduced by the loop gain of the IA output amplifier.
Offset drift of the buffer is similarly reduced.
REFERENCE TERMINAL
The reference terminal may be used to offset the output by up
to ± IOV. This is useful when the load is "floating" or does not
share a ground with the rest of the system. It also provides a
direct means of injecting a precise offset. It must be remembered
that the total output swing is ± 10 volts, from ground, to be
shared between signal and reference offset.
Figure 37. Voltage-to-Current Converter
By establishing a reference at the "low" side of a current setting
resistor, an output current may be defmed as a function of
input voltage, gain and the value of that resistor. Since only a
small current is demanded at the input of the buffer amplifier
A z, the forced current IL will largely flow through the load.
Offset and drift specifications of A z must be added to the output
offset and drift specifications of the IA.
PROGRAMMABLE GAIN
Figure 38 shows the AD624 being used as a software programmable
gain amplifier. Gain switching can be accomplished with mechanical switches such as DIP switches or reed relays. It should be
noted that the "on" resistance of the switch in series with the
internal gain resistor becomes part of the gain equation and will
have an effect on gain accuracy.
INSTRUMENTATION AMPLIFIERS 4-57
VOUT
Figure 38. Gain Programmable Amplifier
A significant advantage in using the internal gain resistors in a
programmable gain configuration is the minimization of thermocouple signals which are often present in multiplexed data
acquisition systems.
If the full performance of the AD624 is to be achieved, the user'
must be extremely careful in designing and laying out his circuit
to minimize the remaining thermocouple signals.
The AD624 can also be connected for gain in the output stage.
Figure 39 shows an AD547 used as an active attenuator in the
output amplifier's feedback loop. The active attenuation presents
a very low impedance to the feedback resistors therefore minimizing the common-mode rejection ratio degradation.
Figure 40. Programmable Output Gain Using a DAC
AUTO-ZERO CIRCUITS
In many applications it is necessary to provide very accurate
data in high gain configurations. At room temperature the offset
effects can be nulled by the use of offset trimpots. Over the
operating temperature range, however, offset nulling becomes a
problem. The circuit of Figure 41 shows a CMOS DAC operating
in the bipolar mode and connected to the reference terminal to
provide software controllable offset adjustments.
Figure 41. Software Controllable Offset
In many applications complex software algorithms for auto-zero
applications are not available. For these applications Figure 42
provides a hardware solution.
Figure 39. Programmable Output Gain
~.,.......--{i)
151 16
Another method for developing the switching scheme is to use a
DAC. The AD7528 dual DAC which acts essentially as a pair of
switched resistive attenuators having high analog linearity and
symmetrical bipolar transmission is ideal in this application.
The multiplying DAC's advantage is that it can handle inputs of
either polarity or zero without affecting the programmed gain.
The circuit shown uses an AD7528 to set the gain (DAC A) and
to perform a fine adjustment (DAC B).
I
I
I"
I
I
,
lAG.
---~ll*
..::J:9-....
Figure 42. Auto-Zero Circuit
4-58 INSTRUMENTA TION AMPLIFIERS
~'"
The microprocessor controlled data acquisition system shown in
Figure 43 includes includes both auto-zero and auto-gain capability. By dedicating two of the differential inputs, one to ground
and one to the AID reference, the proper program calibration
cycles can eliminate both initial accuracy errors and accuracy
errors over temperature. The auto-zero cycle, in this application,
converts a number that appears to be ground and then writes
that same number (8 bit) to the AD7524 which eliminates the
zero error since its output has an inverted scale. The auto-gain
cycle converts the A/D reference and compares it with full scale.
A multiplicative correction factor is then computed and applied
to subsequent readings.
ACBRIDGE
Bridge circuits which use dc excitation are often plagued by
errors caused by thermocouple effects, lIf noise, dc drifts in the
electronics, and line noise pick-Up. One way to get around these
problems is to excite the bridge with an ac waveform, amplify
the bridge output with an ac amplifier, and synchronously demodulate the resulting signal. The ac phase and amplitude information from the bridge is recovered as a dc signal at the
output of the synchronous demodulator. The low frequency
system noise, dc drifts, and demodulator noise all get mixed to
the carrier frequency and can be removed by means of a low
pass filter. Dynamic response of the bridge must be traded off
against the amount of attenuation required to adequately suppress
these residual carrier components in the selection of the filter.
Figure 45 is an example of an ac bridge system with the AD630
used as a synchronous demodulator. The oscilloscope photograph
shows the results of a 0.05% bridge imbalance caused by the
IMeg resistor in parallel with one leg of the bridge. The top
trace represents the bridge excitation, the upper middle trace is
the amplified bridge output, the lower-middle trace is the output
of the synchronous demodulator and the bottom trace is the
filtered dc system output.
This system can easily resolve a 0.5ppm change in bridge impedance. Such a change will produce a 6.3mV change in the low
pass filtered dc output, well above the RTO drifts and noise.
Figure 43. Microprocessor Controlled Data Acquisition
System
The AC-CMRR of the AD624 decreases with the frequency of
the input signal. This is due mainly to the package-pin capacitance
associated with the AD624's internal gain resistors. If AC-CMRR
is not sufficient for a given application, it can be trimmed by
using a variable capacitor connected to the amplifier's RG2 pin
as shown in Figure 45.
WEIGH SCALE
Figure 44 shows an example of how an AD624 can be used to
condition the differential output voltage from a load cell. The
10% reference voltage adjustment range is required to accommodate the 10% transducer sensitivity tolerance. The high linearity
and low noise of the AD624 make it ideal for use in applications
of this type particularly where it is desirable to measure small
changes in weight as opposed to the absolute value. The addition
of an auto gain/auto tare cycle will enable the system to remove
offsets, gain errors, and drifts making possible true 14-bit
performance.
Figure 45. AC Bridge
BRIDGE EXcrrAllON
I20VldlvllAI
AMPUAED BRIDGE
OUTPUT (!IV/iii") (8)
DEMODULATED MUDGE
OU'Tl"UTI5VlGlvilCI
AlTER OUTPUT (2Vldnol
10'
Figure 44. AD624 Weigh Scale Application
Figure 46. AC Bridge Waveforms
INSTRUMENTATION AMPLIFIERS 4-59
4
+Vs
+10V
,.. --,, ,
,
I
\
....
\
, ,
,
,,
I
14-BIT
I
ADC
I
OT02V
I
I
I
F.S.
I
- ________'I.! __ j
Figure 47. Typical Bridge Application
ERROR BUDGET ANALYSIS
To illustrate how instrumentation amplifier specifications are
applied, we will now examine a typical case where an AD624 is
required to amplify the output of an unbalanced transducer.
Figure 47 shows a differential transducer, unbalanced by =50,
supplying a 0 to 20mV signal to an AD624C. The output of the
IA feeds a 14-bit A to D converter with a 0 to 2 volt input
voltage range. The operating temperature range is - 25°C to
+ 85°C. Therefore, the largest change in temperature aT within
the operating range is from ambient to + 85°C (85°C - 25°C
= 60°C).
Error Source
AD624C
Specifications
Gain Error
Gain Instability
Gain Nonlinearity
Input Offset Voltage
Input Offset Voltage Drift
±O.I%
IOppm
±0.001%
±2SII-V,RTI
±0.25."VrC
Output Offset Voltage l
Output Offset Voltage Drift l
±2.0mV
± IO."VrC
Bias Current- Source
Imbalance Error
Offset Current - Source
Imbalance Error
Offset Current - Source
Resistance- Error
Offset Current - Source
Resistance - Drift
Common Mode Rejection
SVdc
Noise,RTI
(O.I-IOHz)
±ISnA
±lOnA
±IOnA
±IOOpAfOC
IlSdB
0.22I1-Vp-p
In many applications, differential linearity and resolution are of
prim\! importance. This would be so in cases where the absolute
value of a variable is less important than changes in value. In
these applications, only the irreducible errors (20ppm = 0.002%)
are significant. Furthermore, if a system has an intelligent processor monitoring the A to D output, the addition of a auto-gainl
auto-zero cycle will remove all reducible errors and may eliminate
the requirement for initial calibration. This will also reduce
errors to 0.002%.
'
Calculation
±O.I% = 1000ppm
(IOppmrC)(60°C) = 600ppm
±0.001% = 10ppm
±2511-V/20mV = ± 1250ppm
(± 0.25."V/°C)(60°C) = IS."V
1511-V/20mV = 750ppm
±2.0mV/20mV = 1000ppm
(± 1011-V/OC)(60°C) = 600."V
600."V/20mV = 300ppm
(± 15nA)(SO) = 0.07511-V
0.07S."V/20mV = 3.7Sppm
(± 10nA)(SO) = 0.05011-V
0.OS0Il-V/2OmV = 2.Sppm
(lOnA)(17S0) = 3.5."V
3.5I1-V/20mV = 87.5ppm
(IOOpAfOC)(l7S0)(60°C) = I."V
III-Vl20mV = SOppm
IlSdB = 1.8ppm x 5V = 911-V
911-V/20mV = 444ppm '
0.22I1-Vp-p/20niV
Effect on
Absolute
Accuracy
atTA = 25°C
Effect on
Absolute
Accuracy
atTA = 85°C
1000ppm
lOOOppm
600ppm
12S0ppm
I 250ppm
1000ppm
750ppm
1000ppm
IOppm
300ppm
3.75ppm
3.7Sppm
2.5ppm
2.5ppm
87.Sppm
87.5ppm
SOppm
4S0ppm
450ppm
= 10ppm
Total Error
IOppm
3793.7Sppm
S493.7Spp~
'Output offset voltage and output offset voltage drift are given as RTI figures.
Table II. Error Budget Analysis of AD624CD in Bridge Application
4-60 INSTRUMENTATION AMPLIFIERS
Effect
on
Resolution
20ppm
Programmable Gain
Instrumentation Amplifier
11IIIIIIII ANALOG
L.III DEVICES
AD625 I
FEATURES
User Programmed Gains of 1 to 10,000
Low Gain Error: 0.02% max
Low Gain TC: 5ppmrc max
Low Nonlinearity: 0.001% max
Low Offset Voltage: 25p.V
Low Noise 4nVlv'Hi (at 1kHz) RTI
Gain Bandwidth Product: 25MHz
16-Pin Ceramic or Plastic DIP Package
MIL-Standard Parts Available
Low Cost
PRODUCT DESCRIPTION
The AD625 is a precision instrumentation amplifier specifically
designed to fulfill two major areas of application:
I) Circuits requiring nonstandard gains (i.e., gains not easily
achievable with devices such as the AD524 and AD624).
2) Circuits requiring a low cost, precision software programmable gain amplifier.
For low noise, high CMRR, and low drift the AD625}N is the
most cost effective instrumentation amplifier solution available.
An additional three resistors allow the user to set any gain from
I to 10,000. The error contribution of the AD625}N is less than
0.05% gain error and under 5ppml'C gain TC; performance
limitations are primarily determined by the external resistors.
Common-mode rejection is independent of the feedback resistor
matching.
A software programmable gain amplifier (SPGA) can be configured
with the addition of a CMOS multiplexer (or other switch network),
and a suitable resistor network. Because the ON resistance of
the switches is removed from the signal path, an AD625 based
SPGA will deliver 12-bit precision, and can be programmed for
any set of gains between I and 10,000, with completely user
selected gain steps.
AD625 FUNCTIONAL BLOCK DIAGRAM
+GAIN
DRIVE
+GAIN
SENSE
PRODUCT HIGHLIGHTS
I. The AD625 affords up to 16-bit precision for user selected
fixed gains from I to 10,000. Any gain in this range can be
programmed by 3 external resistors.
2. A 12-bit software programmable gain amplifier can be configured using the AD625, a CMOS multiplexer and a resistor
network. Unlike previous instrumentation amplifier designs,
the ON resistance of a CMOS switch does not affect the gain
accuracy.
3. The gain accuracy and gain temperature coefficient of the
amplifier circuit are primarily dependent on the user selected
external resistors.
4. The AD625 provides totally independent input and output
offset nulling terminals for high precision applications. This
minimizes the effects of offset voltage in gain-ranging
applications.
5. The proprietary design of the AD625 provides input voltage
noise of 4nV/YRZ at 1kHz.
6. External resistor matching is not required to maintain high
common-mode rejection.
For the highest precision the AD625C offers an input offset
voltage drift of less than 0.25f.LVI'C, output offset drift below
15f.LV/oC, and a maximum nonlinearity of 0.001% at G= I. All
grades exhibit excellent ac performance; a 25MHz gain bandwidth
product, 5Vf.Ls slew rate and 15f.Ls settling time.
The AD625 is available in three accuracy grades (A, B, C) for
industrial ( - 25°C to + 85°C) temperature range, two grades (J,
K) for commercial (0 to + 70°C) temperature range, and one (S)
grade rated over the extended ( - 55°C to + 125°C) temperature
range.
INSTRUMENTATION AMPLIFIERS 4-61
SPECIFICATIONS
Model
(typical @ Vs = ±15V,
Min
AD62SAlJ/S
Typ
GAIN
Gain Equation
Gain Range
Gam Error'
Nonlinearity, Gain = 1-256
Gain>256
Gain vs. Temp. Gain< 1000'
Rt = 2110 and TA = +25"1: unless otherwise specified)
Max
Min
±.035
Max
Min
2 RF
-+1
RG
2 RF
R;;+ I
I
AD62SBIK
Typ
10,000
±0.05
±0.005
±0.01
5
I
±0.02
AD625C
Typ
Max
Units
10,000
±0.02
±O.OOI
±0.005
5
%
%
%
ppm!'C
2 RF
-+1
RG
10,000
±0.03
±0.002
±0.008
5
I
±0.01
GAIN SENSE INPUT
Gain Sense Current
300
5
ISO
2
vs. Temperature
Gain Sense Offset Current
vs. Temperature
VOLTAGE OFFSET (May be Nulled)
Input Offset Voltage
vs. Temperature
Output Offset Voltage
vs. Temperature
Offset Referred to the
Input vs. Supply
G=I
G=IO
G=IOO
G= 1000
50
I
4
20
70
85
95
100
20
500
15
200
2/2
5
SO/SO
75
95
100
110
INPUT CURRENT
Input Bias Current
vs. Temperature
Input Offset Current
vs. Temperature
±30
±50
±2
±20
INPUT
Input Impedance
Differential Resistance
Differential Capacitance
Common-Mode Resistance
Common-Mode Capacitance
Input Voltage Range
Differ. Input Linear (V 0)
Common-Mode Lmear (VeM)
Common-Mode Rejection Ratio dc to
60Hz with Ikn Source Imbalance
G=I
G=IO
G=IOO
G= 1000
SOO
75
90
lOS
110
±SO
ISO
2
75
I
250
15
250
10
50
2
50
I
100
10
100
5
nA
nAI"C
nA
nAl"C
25
0.25
2
10
50
0.50/1
3
,25/40
10
0.1
I
10
25
0.25
2
,..V
,..VI"C
mV
IS
,..VI"C
85
100
110
120
±20
±50
±I
±20
±35
70
100
110
OUTPUT RATING
DYNAMIC RESPONSE
Small Signsl - 3dB
G=I(RF =20kn)
G=IO
G=IOO
G= 1000
Slew Rate
Settling Time 100.01 %, 20V Step
G= !to 200
G=SOO
G=IOOO
NOISE
Voltage NOIse, 1kHz
R.T.r.
R.T.O.
R.T.r.,O.ltoIOHz
G=I
G= 10
G=IOO
G= 1000
Current Noise
O.IHzlO 10Hz
4-62 INSTRUMENTATION AMPLIFIERS
dB
dB
dB
dB
±IO
±50
±I
±20
±15
12V -
75
95
105
115
±15
±5
±IO
(~XVo)
85
105
115
125
12V -
80
100
110
120
nA
pAI"C
nA
pN°C
Gn
pF
Gn
pF
±IO
-(~ XVo )
75
95
105
115
90
105
120
140
I
4
I
4
±IO
90
±25
I
4
I
4
I
4
I
4
12V
80
95
110
115
V
(~XVo)
90
115
125
140
dB
dB
dB
dB
±IOV
@5mA
±IOV
ilL5mA
±IOV
(!.<5mA
650
400
ISO
25
5.0
650
400
ISO
25
5.0
650
400
ISO
25
5.0
IS
35
75
IS
35
75
IS
35
75
4
75
4
75
4
75
nV/vHZ
nV/vHZ
10
1.0
0.3
0.2
10
1.0
0.3
0.2
10
1.0
0.3
0.2
,..Vp-p
,..Vp-p
,..Vp-p
,..Vp-p
60
60
60
pAp-p
kHz
kHz
kHz
kHz
VI,..s
....
,..S
,...
Model
SENSE INPUT
RIN
lIN
Vollage Range
Gain to Output
REFERENCE INPUT
RIN
lIN
Voltage Range
Gain to Output
TEMPERATURE RANGE
Specified Performance
J/KGrades
AlBIC Grades
SGrade
Srorage
POWER SUPPLY
Power Supply Range
Quiescent Current
PACKAGE OPTIONS'
Ceramic (D-16)
Plastic DIP (N -16)
Min
AD625A/J/S
Typ
Max
Min
10
30
AD625B/K
Typ
Max
Min
10
30
Max
Units
10
30
kll
I-'A
V
=10
=10
=10
AD625C
Typ
1±0.01
1=0.01
1=0.01
%
20
30
20
30
20
30
k{}
±IO
=10
1±0.01
0
-25
- 55
-65
+70
+85
+ 125
+ 150
±6to ± 18
3.5
5
AD625AD/SD
AD625JN
I-'A
V
%
±IO
1=,),01
1=0.01
0
-25
+70
+85
-25
+85
°C
°C
-65
+150
-65
+ 150
°C
±6to ::tIS
3.5
5
AD625BD
AD625KN
±6to ± 18
3.5
5
V
rnA
AD625CD
NOTES
'Gam error and gam TC are for the AD625 only Resistor network errors will add to the specified errors.
2See Sectlon 16 for package outlme informatIOn.
Specifications subJect to change wIthout notice
SpecIfications shown III boldface are tested on all productIon umts at final
electncal test. Results from those tests are used to calculate outgomg quallty
levels. All mlm and max specificatIons afe guaranteed, although only those
shown In boldface are tested on all production uruts.
PIN CONFIGURATION
INSTRUMENTATION AMPLIFIERS 4-63
•
Typical Characteristics
20
20
,.
>
+<
f..- i-
,
~
!:i
g
/
/
10
~'C
~
!
V
o
30
/
o
V
10
15
o
20
o
/
/
/
1
V
5
10
SUPPLY VOLTAGE -
SUPPLY VOLTAGE - ±V
Figure 1. Input Voltage Range vs.
Supply Voltage, G = 1
II
/
±v
16
o
'0
20
Figure 2. Output Voltage Swmg
vs. Supply Voltage
V
100
'0'
lk
LOAD RESISTANCE - fl:
Figure 3. Output Voltage Swmg
vs. Resistive Load
30
-140
-'2o
-'00 • '0
~
-00 G ,
~
1\
n i'"
6=100
m
,
GJ...
G 1000
~"
~ ......
"~
-00
-40
,<,
o
10
0.-
100
1k
10k
FAEQUENCY- Hz
tOOk
o
10M
Bn~+fl~n
G'OO9I
-t=
-1SV
"-
~
> 00
~
t
~BO
20
o
30
40
50
60
70 80
Figure 7. Offset Voltage, RTI, Turn
On Drift
..
'0
'00
,.
'Ok
FREQUENCY - Hz
1V PIP SINEWAVE
...
....................... ~
~ '-.....
BO
............
..
0 ..,
~
2.
'00'
Figure B. Negative PSRR vs.
Frequency
'OM
+Js:: : + 15vlct_
6.
~
'M
Figure 6. Gam vs. Frequency
'00
'-.....
tOOk
"\.\~
FREQUENCY - Hz
'20
~ '-.....
~
10k
1k
..
~
Q~l
'00
'B.
,
dC~
tV PIP SINEWAVE -
~ 100
WARM-UP TIME - MINUTES
'M
Figure 5. Large Signal Frequency
Response
.
...
,
IGlOO'
10k
tOOk
FREO ENCY - Hl
1k
,
,
/
20
c '0
t\
~'20
10
\
C
\
...... ~......
v
o
'"" "'\
'00
Figure 4. CMRR vs. Frequency
RTI, Zero to 1kO Source Imbalance
o
'000
z
-20
o
J.
11,
•,.
'00
,.
'-.....
..........
,.k
FREQUENCy-tb
'00k
Figure 9. Positive PSRR vs.
Frequency
30
20
1
,
'0
~
0
!
-
-
1)
~-10
!
-20
-30
.
-
26
TEMPERATURE -
Qc
7.
'26
Figure 10. Input Bias Current vs.
Temperature
4-64 INSTRUMENTATION AMPLIFIERS
Figure ". Overange and Gain
Switcl!ing Test Circuit (G=8, G=1)
Figure 12. Gain Overange Recovery
Typical Characteristics
80
,00k
~
i1,
60
~~
.
'00
G
~
c
,
I
~
z
~
i ~
.
"'"
.
,
c
;I
G=10
r--.
1000
G 100, 1000
G=l00~~""
I'
20
~
"
'00
z
~
~
o
"u
0' ,
'0
o
100
lk
FREQUENCY - Hz
SUPPLY VOLTAGE - ±V
s V"
+-
-j
t
.L.
I
,.
t-~~-"
.1 I I
,
1k
'00
'0
lOOk
'Ok
FReQUENCY - Hz
FIgure 14. RTf Noise Spectral
DenSIty vs. Gain
F,gure 13. Quiescent Current vs.
Supply Voltage
'0
Figure 15. Input Current NOIse
'15
'
j ,t
-. t i " .
1
- I1 '' , II
t
I
+
,
-+--
_ _ t-_ _ _ ---t
~
_ _ r-_
I
--
-------
"-_
~-
+
:.
~--
FIgure 16. Low Frequency Voltage
NOIse, G=l (System Gatn=1000)
+
-
------:------'------r--
Figure 18. Low Frequency Voltage
Noise, G=1000 (System
Gain= 100, 000)
F,gure 17. NOIse Test CirCUIt
-12 to 12
-8 to 8
il
Gl, f
-4 to 4
I'
G-l00
G-l000
G~ ,\ G~'~O
G 1000
I
OUTPUT
STEP-V
4to -4
1\
8 to-8
12 to -12
20
30
40
50
SETTLING TIME -115
70
Figure 19. Large Signal Pulse
Response and Settltng Time, G=l
F,gure 20. Settling Time to 0.01%
Figure 22. Large Signal Pulse
Response and Settling Time, G = 10
Figure 23. Settling Time Test
Circuit
Figure 21. Large Signal Pulse
Response and Settling Time, G = 100
Figure 24. Large Signal Pulse
Response and Settling Time,
G=1000
INSTRUMENTATION AMPLIFIERS 4-65
Theory of Operation
The AD625 is a monolithic instrumentation amplifier based on
a modification of the classic three-op-amp approach. Monolithic
construction and laser-wafer-trimming allow the tight matching
and tracking of circuit components. This insures the high level
of performance inherent in this circuit architecture.
A preamp section (QI-Q4) provides additional gain to Al and
A2. Feedback from the outputs of Al and A2 forces the collector
currents of QI-Q4 to be constant, thereby, impressing the input
voltage across RG • This creates a differential voltage at the outputs
of Al and A2 which is given by the gain (2RF/~ + I) times
the differential portion of the input voltage. The unity gain
subtractor, A3, removes any common-mode signal from the
output voltage yielding a single ended output, VOUT , referred to
the potential at the reference pin.
The value of RG is the determining factor of the transconductance
of the input preamp stage. 'As RG is reduced for larger gains the
transconductance increases. This has three important advantages.
First, this approach allows the circuit to achieve a very high
open-loop gain of (3 x 108 at programmed gains"" 500) thus
reducing gain related errors. Second, the gain-bandwidth product,
which is determined by C3, C4, and the input transconductance,
increases with gain, thereby, optimizing frequency response.
Third, the input voltage noise is reduced to a value determined
by the collector current of the input transistors (4nV/YHz).
INPUT PROTECTION
Differential input amplifiers frequently encounter input voltages
outside of their linear range of operation. There are two considerations when applying input protection for the AD625; I) that
continuous input current must be limited to less than lOrnA and
2) that input voltages must not exceed either supply by more
than one diode drop (approximately 0.6V @ 25°C).
The diodes to the supplies are only necessary if input voltages
outside of the range of the supplies are encountered. In higher
gain applications where differential voltages are small, back-toback zener diodes and smaller resistors, as shown in Figure 26b,
provides adequate protection. Figure 26c shows low cost FETs
with a maximum ON resistance of 3000 configured to offer
input protection with minimal degradation to noise, (5.2nV/YHz
compared to normal noise performance of 4nV/YHz).
During differential overload conditions, excess current will flow
through the gain sense lines (pins 2 and IS). This will have no
effect in fixed gain applications. However, if the AD625 is
being used in an SPGA application with a CMOS m,ultiplexer,
this current should be taken into consideration. The current
capabilities of the multiplexer may be the limiting factor in
allowable overflow current. The ON resistance of the switch
should be included as part of RG when calculating the necessary
input protection resistance.
Figure 26a. Input Protection Circuit
Under differential overload conditions there is (RG + 100)0 in
series with two diode drops (apprOldmately 1.2V) between the
plus and minus inputs, in either direction. With no external
protection and RG very small (i.e., 400), the maximum overload
voltage the AD625 can withstand, continuously, is approximately
± 2.5V. Figure 26A shows the external components necessary to
protect the AD625 under all overload conditions at any gain.
50",A
Figure 26b. Input Protection Circuit for G>5
~fl'
I
fl,
L-+--_~_"""'_-I>-
GAIN
__t-...J
GAIN
SENSE
SENSE
-v,
Figure 25. Simplified Circuit of the AD625
4-66 INSTRUMENTA TlON AMPLIFIERS
Figure 26c. Input Protection Circuit
Applying the AD625
Any resistors in series with the inputs of the AD625 will degrade
the noise performance. For this reason the circuit in Figure 26b
should be used if the gains are all greater than 5. For gains less
than 5, either the circuit in Figure 26a or in Figure 26c can be
used. The two 1.4kO resistors in Figure 26a will degrade the
noise performance to:
V 4kTRext
+ (4nV/v'HZ)2
=
,
7.9nV/YHz
RESISTOR PROGRAMMABLE GAIN AMPLIFIER
In the resistor-programmed mode (Figure 27), only three external
resistors are needed to select any gain from I to 10,000. Depending
on the application, discrete components or a pretrimmed network
can be used. The gain accuracy and gain TC are primarily determined by the external resistors since the AD625C contributes
less than 0.02% to gain error and under 5ppmrC gain TC. The
gain sense current is insensitive to common-mode voltage, making
the CMRR of the resistor programmed AD625 independent of
the match of the two feedback resistors, R F.
Selecting Resistor Values
As previously stated each RF provides feedback to the input
stage and sets the unity gain transconductance. These feedback
resistors are provided by the user. The AD625 is tested and
specified with a value of 20kO for R F. Since the magnitude of
RTO errors increases with increasing feedback resistance, values
much above 20kO are not recommended (values below 10kO for
RF may lead to instability). Refer to the graph of RTO noise,
offset, drift, and bandwidth (Figure 28) when selecting the
feedback resistors. The gain resistor (Re) is determined by the
formula Re = 2RF/(G-I).
,
L-- f.---'
V
,
,~
V
V
/
1/
~.
FEEOBACK RESISTANCE
n
RTO OffSET VOLTAGE DRIFT
/
/
V
a
1\ /
, \V
ff:
10k
f-+-++++-+++++--I--I-+H
Figure 28. RTO NOise, Offset, Drift, and 8andwidth vs.
Feedback ReSistance Normalized to 20kO
I
2
5
10
20
50
100
200
500
1000
4
8
16
32
64
128
256
512
1024
A list of standard resistors which can be used to set some common
gains is shown in Table I.
--
..-/
,
GAIN
Figure 27. AD625 in Fixed Gain Configuration
FllO OFFSET VOLTAGE
ATO NOISE
RF
20kO
19.6kO
20kO
20kO
20kO
19.6kO
20kO
20,5kO
19,6kO
19.6kO
20kO
19.6kO
20k!l
19,6kO
20k!l
20k!l
19.6k!l
19,6k!l
19,6k!l
39.2k!l
lOkO
4.42k!l
2.1kO
806!l
4020
205!l
78.m
39.2!l
13.3kO
5,62k!l
2,67k!l
l.27kO
6340
3160
1540
76.8!l
38.3!l
Table I. Common Gains Nominallv within :±O.5% Error
Using Standard 1% Resistors
For single gain applications, only one offset null adjust is necessary;
in these cases the RTI null should be used.
INSTRUMENTA TlON AMPLIFIERS 4-67
•
SENSE TERMINAL
The sense terminal is the feedback point for the AD62S output
amplifier. Normally it is connected directly to the output. If
heavy load currents are to be drawn through long leads, voltage
drops through lead resistance can cause errors. In these instances
the sense terrr.inal can be wired to the load thus putting the
I x R drops "inside the loop" and virtually eliminating this
The offset per bit is equal to the total offset range divided by
2N , where N = number of bits of the DAC. The range of offset
for Figure 30 is
:t
120m V, and the offset is incremented in steps
of 0.937SmV/LSB.
error source.
Typically, IC instrumentation amplifiers are rated for a full ± 10
volt output swing into 2kO. In some applications, however, the
need exists to drive more current into heavier loads. Figure 29
shows how a high-current booster may be connected "inside the
loop" of an instrumentation amplifier. By using an external
power boosting circuit, the power dissipated by the AD62S will
remain low, thereby, minimizing the errors induced by self-heating. The effects of nonlinearities, offset and gain inaccuracies of
the buffer are reduced by the loop gain of the AD62S's output
amplifier.
V'N+
",
"0
",
",
V'N-
Figure 29. AD625 Instrumentation Amplifier with Output
Current Booster
REFERENCE TERMINAL
The reference terminal may be used to offset the output by up
to ± 10V. This is useful when the load is "floating" or does not
share a ground with the rest of the system. It also provides a
direct means of injecting a precise offset. However, it must be
remembered that the total output swing is ± 10 volts, from
ground, to be shared between signal and reference offset.
Figure 30. Software Controllable Offset
An instrumentation amplifier can be turned into a voltage-tocurrent converter by taking advantage of the sense and reference
terminals as shown in Figure 31.
The AD62S reference terminal must be presented with nearly
zero impedance. Any significant resistance, including those
caused by PC layouts or other connection techniques, will increase
the gain of the noninverting signal path, thereby, upsetting the
common-mode rejection of the In-Amp. Inadvertent thermocouple
connections created in the sense and reference lines should also
be avoided as they will directly affect the output offset voltage
and output offset voltage drift.
In the AD62S a reference source resistance will unbalance the
CMR trim by the ratio of 10kO/RREF . For example, ifthe reference
source impedance is 10, CMR will be reduced to 80dB (lOkntlO
= 80dB). An operational amplifier may be used to provide the
low impedance reference point as shown in Figure 30. The
input offset voltage characteristics of that amplifier will add
directly to the output offset voltage performance of the instrumentation amplifier.
The circuit of Figure 30 also shows a CMOS DAC operating in
the bipolar mode and connnected to the reference terminal to
provide software controllable offset adjustments. The total offset
range is equal to ± (VREF/2 x Rs/R,), however, to be symmetrical
about OV R3 = 2 X R4 •
4-68 INSTRUMENTATION AMPLIFIERS
Figure 31. Voltage-to-Current Converter
By establishing a reference at the "low" side of a current setting
resistot, an output current may be defined as a function of
input voltage, gain and the value of that resistor. Since only a
small current is demanded at the input of the buffer amplifier
AI, the forced current IL will largely flow through the load.
Offset and drift specifications of A2 must be added to the output
offset and drift specifications of the In-Amp.
INPUT AND OUTPUT OFFSET VOLTAGE
Offset voltage specifications are often considered a figure of
merit for instrumentation amplifiers. While initial offset may be
adjusted to zero, shifts in offset voltage due to temperature
variations will cause errors. Intelligent systems can often correct
for this factor with an auto-zero cycle, but this requires extra
circuitry.
common-mode rejection errors unless the shield is properly
driven. Figures 32 and 33 show active data guards which are
configured to improve ac common-mode rejection by "bootstrapping" the capacitances of the input cabling, thus minimizing
differential phase shift.
Offset voltage and offset voltage drift each have two components:
input and output. Input offset is that component of offset that
is generated at the input stage. Measured at the output it is
directly proportional to gain, i.e., input offset as measured at
the output at G = 100 is 100 times greater than that measured
at G = I. Output offset is generated at the output and is constant
for all gains.
The input offset and drift are multiplied by the gain, while the
output terms are independent of gain, therefore, input errors
dominate at high gains and output errors dominate at low gains.
The output offset voltage (and drift) is normally specified at
G = 1 (where input effects are insignificant), while input offset
(and drift) is given at a high gain (where output effects are
negligible). All input-related parameters are specified referred to
the input (RTI) which is to say that the effect on the output is
"G" times larget. Offset voltage vs. power supply is also specified
as an R TI error. .
By separating these errors, one can evaluate the total error independent of the gain. For a given gain, both errors can be combined
to give a total error referred to the input (RTI) or output (RTO)
by the following formula:
Total Error RTI = input error + (output error/gain)
Total Error RTO
=
(Gain x input error) + output error
Figure 33. Differential Shield Dover
GROUNDING
In order to isolate low level analog signals from a noisy digital
environment, many data-acquisition components have two or
more ground pins. These grounds must eventually be tied together
at one point. It would be convenient to use a single ground line,
however, current through ground wires and pc runs of the
circuit card can cause hundreds of millivolts of error. Therefore,
separate ground returns should be provided to minimize the
current flow from the sensitive points to the system ground (see
Figure 34). Since the AD625 output voltage is developed with
respect to the potential on the reference terminal, it can solve
many grounding problems.
The AD625 provides for both input and output offset voltage
adjustment. This simplifies nulling in very high perecision applications and minimizes offset voltage effects in switched gain
applications. In such applications the input offset is adjusted
first at the highest programmed gain, then the output offset is
adjusted at G = I. If only a single null is desired, the input
offset null should be used. The most additional drift when using
only the input offset null is O.9J.LV/'C, RTO.
COMMON-MODE REJECTION
Common-mode rejection is a measure of the change in output
voltage when both inputs are changed by equal amounts. These
specifications are usually given for a full-range input voltage
change and a specified source imbalance.
In an instrumentation amplifier, degradation of common-mode
rejection is caused by a differential phase shift due to differences
in distributed stray capacitances. In many applications shielded
cables are used to minimize noise. This technique can create
Figure 34. Basic Groundmg Practice for a Data Acquisition
System
GROUND RETURNS FOR BIAS CURRENTS
Figure 32. Common-Mode Shield Driver
Input bias currents are those currents necessary to bias the
input transistors of a dc amplifier. There must be a direct return
path for these currents, otherwise they will charge external
capacitances, causing the output to drift uncontrollably or saturate.
Therefore, when amplifying "floating" input sources such as
transformers, or ac-coupled sources, there must be a dc path
from each input to ground as shown in Figure 35.
INSTRUMENTATION AMPLIFIERS 4-69
Figure 35a. Ground Returns for Bias Currents with
Transformer Coupled Inputs
Figure 35b. Ground Returns for Bias Currents with
Thermocouple Input
Figure 36. Auto-Zero Circuit
over the circuitry since slowly fluctuating thermocouple voltages
will appear as "flicker" noise. In SPGA applications relay contacts
and CMOS mux leads are both potential sources of additional
thermocouple errors.
Figure 35c. Ground Returns for Bias Currents with AC
Coupled Inputs
The base emitter junction of an input transistor can rectify out
of band signals (i.e., RF interference). When amplifying small
signals, these rectified voltages act as small dc offset errors. The
AD625 allows direct access to the input transistors' bases and
emitters enabling the user to apply some first order filtering to
these unwanted signals. In Figure 37, the RC time constant
should be chosen for desired attenuation of the interfering signals.
In the case of a resistive transducer, the capacitance alone working
against the internal resistance of the transducer may suffice.
R,
R,
AUTO-ZERO CIRCUITS
In many applications it is necessary to maintain high accuracy.
At room temperature, offset effects can be nulled by the use of
offset trimpots. Over the operating temperature range, however,
offset nulling becomes a problem. For these applications the
auto-zero circuit of Figure 36 provides a hardware solution.
OTHER CONSIDERATIONS
One of the more overlooked problems in designing ultra-low-drift
dc amplifiers is thermocouple induced offset. In a circuit comprised
of two dissimilar conductors (i.e., copper, kovar), a current
flows when the two junctions are at different temperatures.
When this circuit is broken, a voltage known as the "Seebeck"
or thermocouple emf can be measured. Standard IC lead material
(kovar) and copper form a thermocouple with a high thermoelectric
potential (about 3511 VOC). This means that care must be taken
to insure that all connections (especially those in the input circuit
of the AD625) remain isothermal. This includes the input leads
(I, 16) and the gain sense lines (2, 15). These pins were chosen
for symmetry, helping to desensitize the input circuit [0 thermal
gradients. In addition, the user should also avoid air currents
4-70 INSTRUMENTA TION AMPLIFIERS
Figure 37. Circuit to Attenuate RF Interference
These capacitances may also be incorporated as part of the external
input protection circuit (see section on input protection). As a
general practice every effort should be made to match the extraneous capacitance at pins 15 and 2, and pins I and 16, to
preserve high ac CMR.
SOFTWARE PROGRAMMABLE GAIN AMPLIFIER
An SPGA provides the ability to externally program precision
gains from digital inputs. Historically, the problem in systems
requiring electronic switching of gains has been the ON resistance
(RoN) of the multiplexer, which appears in series with the gain
setting resistor ~. This can result in substantial gain errors and
gain drifts. The AD62S eliminates this problem by making the
gain drive and gain sense pins available (pins 2, IS, 5, 12; see
Figure 39). Consequently the multiplexer's ON resistance is
removed from the signal current path. This transforms the ON
resistance error into a small nullable offset error. To clarify this
point, an error budget analysis has been performed in Table II
based on the SPGA configuration shown in Figure 39.
v,"
Figure 39. SPGA with Multiplexer Error Sources
Figure 39 shows a complete SPGA feeding a 12-bit DAS with a
(}-IOV input range. This configuration was used in the error
budget analysis shown in Table II. The gain used for the RTI
calculations is set at 16. As the gain is changed, the ON resistance
of the multiplexer and the feedback resistance will change,
which will slightly alter the values in the table.
Induced Error
RTIOffset
Valtas<
Specification
AD62SC
AD7S02KN
Gain Sense
Offset
Current
40nA
Switch
ResIstance
Calculation
4OnAxl7on~
Voltage Offset
IndueedRTI
6.S",V
6.S",V
1700
RTIOffset
Gain Sense
Voltage
Current
60nA
RTOOffset
Feedback
DJfferential
Voltage
Resistance
Leakage
Current (Is)'
+O.2nA
-0.2nA
Differential
Switch
Resistance
6OnAx6.S0~
O.41",V
O.4I",V
6.80
20kO'
2(O.2oA x 20kO)
O.S",V
~8",V/16
RTOOffset
Feedback
Differential
2(lnA x 20kO)
Voltage
Resistance
Leakage
~40",V/16
20kn'
Current
2.S",V
(lOUT)'
FIgure 38. SPGA in a Gam of 16
+ Ina
-InA
Total error induced by a typical CMOS multiplexer
to an SPGA at 2S"C
Figure 38 shows an AD625 based SPGA with possible gains of
1,4, 16, 64. ~ equals the resistance between the gain sense
lines (pins 2 and IS) of the AD62S. In Figure 38, RG equals the
sum of the two 97Sfl resistors and the 6S0fl resistor, or 2600fl.
RF equals the resistance between the gain sense and the gain
drive pins (pins 12 and IS, or pins 2 and 5), that is RF equals
the IS.6kfl resistor plus the 3.9kfl resistor, or 19.5kfl. The
gain, therefore equals:
I = 16
I = 2(l9.Skfl)
(2.6kfl) +
As the switches of the differential multiplexer proceed synchronously, RG and RF change, resulting in the various
programmed gain settings.
2RF
~ +
10.21 ...V
NOTES
lThe resistor for thiS calculation IS the user proVided feedback resistance (RF). 20kfl IS
recommended value (see resistor programmable gam amphfier sectIOn).
2The leakage currents (Is and lOUT) wtll mduce an offset voltage, however, the offset will
be determmed by the difference between the leakages of each "half' of the differential
multiplexer. The ddferenual leakage current is multlphed by the feedback resistance
(see Note l),to determine offset voltage Because differenualleakage curent IS not a
parameter specified on multiplexer data sheets, the most extreme difference (one most
posmve and one most negative) was used for the calculations m Table II. Typical
performance wIll be much better.
.The frequency response and setthng wIll be affected by the ON resistance and mternal
capacitance of the multiplexer Figure 40 shows the settling tune vs. ON resistance at
different gam settings for an AD625 based SPGA.
··Switch reSistance and leakage current errors can be reduced by using relays.
Table II. Errors Induced by Multiplexer to an SPGA
INSTRUMENTATION AMPLIFIERS 4-71
•
1000
800
!J
400
~
200
;jVI
100
III /
SO
fJ
'[
,
i~
~
40
~
20
10
I) Unity gain is treated as a separate case. It is implemented
with separate 20kO feedback resistors as shown in Figure 41. It
is then ignored'in further calculations.
2) Before making any calculations it is advised to draw a resistor
network similar to the network in Figure 41. The network will
have (2 x M) + I resistors, where M = number of gains. For
Figure 38 M=3 (4,16,64), therefore, the resistor string will
have 7 resistors (plus the two 20kO "side" resistors for unity
gain).
3) Begin all calculations with Go = 1 and R po = O.
//;rt
g
running total of the preceding feedback resistors. To illustrate
how the formula can be applied, an example similar to the calculation used for the resistor network in Figure 38 is examined
below.
Rp, = (20kn-RpO> (1-114): Rpo=O :. Rp, = 15kO
R p2 = [20kO-(Rpo + Rp,)l (1-4/16):
Rpo + Rp, = 15kn:.Rp2 = 3. 75kO
~
,., ~
.&'/
R pl = [20kO - (Rpo + Rp, + Rp)l (1-16/64):
Rpo + Rp, + R P2 = 18.75kO:.Rpl =937.50
4) The tenter resistor (Ro of the highest gain setting), is determined
last. Its value is the remaining resistance of the 40kO string,
and can be calculated with the equation:
M
Ro= (40kO- 2
I
,=0
Rp,)
R<;=40kO-2(Rpo +Rp, +Rp2 + Rpl)
40kn - 39.375kO = 6250
,.
..
~
266
1024
40••
GAIN
Figure 40. Settling Time to 0.01% of a 20V Step Input for
SPGA with AD625
DETERMINING SPGA RESISTOR NETWORK VALUES
The individual resistors in the gain network can be calculated
sequentially using the formula given below. The equation determines the resistors as labeled in Figure 41. The feedback resistors
and the gain setting resistors are interactive, therefore; the formula
must be a series where the present term is dependent on the
'preceding term(s). The formula
I
5) If different resistor values are desired, all the resistors in the
network can be scaled by some convenient factor. However,
raising the impedance will increase the RTO errors, lowering
the total network resistance below 20kO can result in amplifier
instability. More information on this phenomenon is given in
the RPGA section of the data sheet. The scale factor will not
affect the unity gain feedback resistors. The resistor network in
Figure 38 has a scaling factor of 650/625 = 1.04, if this factor is
used on Rp" R p2 , R pl , and R<;, then the resistor values will
match exactly.
6) Round off errors can be cumulative, therefore, it is advised
to carry as many significant digits as possible until all the values
have been calculated.
G.
Rp ,= (20kO- ~ Rp.) (I - -G
1 )
1+
~
J
i+l
can be used to calculate the necessary feedback resistors for any
set of gains. This formula yields a network with a total resistance
of 4Okn. A dummy variable (j) serves as a counter to keep a
CONNECT IF UNITY TO GAIN DRIVE
GAIN IS DESIRED
(PIN 51
TO GAIN DRIVE
(I'IN 12)
CONNECT IF UNITY
GAIN IS DESIRED
Figure 41. Resistors for a Gain Setting Network
4-72 INSTRUMENTA TlON AMPLIFIERS
Isolation Amplifiers
Contents
Page
Selection Guide . . . . . . . . . . . . . . . . . . . . .
Orientation . . . . . . . . . . . . . . . . . . . . . . .
AD202/204 - Low Cost, Miniature Isolation Amplifiers
5-3
5-4
AD210 - Precision, Wide Bandwidth, 3-Port Isolation Amplifier.
AD295 - Precision Hybrid Isolation Amplifier . . . . . . . . . .
284} - Economy, High Performance, Self-Contained Isolation Amplifier
555555-
286}/281 - High CMV, High Performance, Synchronized Isolation Amplifiers
289 - Precision, Wide Bandwidth, Synchronized Isolation Amplifier .
290A/292A - Low Cost, Single and Multichannel Isolation Amplifiers . . . .
5-7
ISOLA TlON AMPLIFIERS
19
27
33
39
45
51
~1
5-2 ISOLATION AMPLIFIERS
Selection Guide
Isolation Amplifiers
Model
CMV
Ini00t
Vpk
Gain
Range
vrv
Frequency
Response
kHz
281 (External oscillator for 286 or 292A isolation amplifiers)
2500
1-10
I
284
286
2500
1-100
I
Page
5 - 39
5 - 33
5 - 39
289
290
292A
2500
1500
1500
1-100
1-100
1-100
20
2.5
2.5
5 - 45
5 - 51
5 - 51
ADZ02
ADZ04
ADZ 10
ADZ95
2000
2000
3500
2500
1-100
1-100
1-100
1-1000
1.5
5
20
4.5
5-7
5-7
5 - 19
5 - 27
Notes
External oscillator (281)
3-port isolation
External oscillator (281)
External oscillator, uses AD246 clock
3-port isolation
3-port isolation
ISOLA TlON AMPLIFIERS ~3
Orientation
Isolation Amplifiers
The isolation amplifier (or isolator) has an input circuit that is
galvanically isolated from the power supply and the output
circuit. In the basic two-port form, the output and power circuits
are not isolated from one another; in three-port isolators (see the
figure), the input circuits, output circuits, and power source are
all isolated from one another. In some 3-port isolators, the power
for the output stage must be furnished from the signal's destination;
however, in the device shown in Figure I, all internal power is
furnished by its own power source; in addition, a modicum of
auxiliary power is available to power external input and output
circuitry.
Isolators are intended for applications requiring safe, accurate
measurement of dc and low-frequency voltage or current in the
presence of high common-mode voltage (to thousands of volts)
with high CMR, line-receiving of signals transmitted at high
impedance in noisy environments, and for safety in general-purpose
measurements where dc and line-frequency leakage must be
maintained at levels well below certain mandated minima. *
Principal applications are in electrical environments of the kind
associated with medical equipment conventional and nuclear
power plants, automatic test equipment and industrial processcontrol systems.
Analog Devices Isolators described in this section (and in the
Signal Conditioner section) use electromagnetically coupled highfrequency carrier techniques for communication of power to and
signals from the input (and in some cases the output) circuit.
CHOOSING AN ISOLATOR
The choice of isolator depends on the desired functional characteristics and the required specifications. Functional characteristics
include such considerations as number of channels in the system,
range of output common-mode (output to power supply), nature
of the front-end amplifier (amplification only or general op-amp
functioning) and the availability of isolated power for additional
external front-end (or back-end) circuitry. Key specifications
include performance specs and "absolute maximin" mandated
safety specifications. Definitions of specifications follow this
section. In addition to the products listed here, which are recommended for new designs, a number of older products are
still available; data sheets are available upon request. In addition
to the useful applications information on the data sheets published
here, an applications guide l , available upon request, provides
information useful to the circuit designer.
The devices described in this section are all voltage-output
isolation amplifiers, useful in general-purpose circuit applications
for instrumentation amplifiers or op amps where isolation is a
necessity. In addition to these devices, there are a growing
number of isolators available from Analog Devices that perform
dedicated functions, for use where isolation is necessary or
desirable. Some of their applications can be seen in the Signal
Conditioner section of this book and the Transducer Interfacing
Handbook 2 • Power Supplies and DC-DC Converters, usually
transformer-coupled, also provide isolation.
*Examples of such requirements may be found in UL STD 544 and SWC
(Surge Withstand Capability) in IEEE Standard for Transient Voltage
Protection 472-1974.
I Analog Devices Applications Guide to Isolation Amplifiers and Signal
Conditioners
2Sheingold, D.H., ed, Transducer Interfacing Handbook - A guide to
analog signal conditioning. Norwood, MA 02062 (P.O. Box 796):
Analog Devices, Inc., 1980, $14.50
5-4 ISOLA nON AMPLIFIERS
Figure 7. AD270 Block Diagram
Functional Characteristics: The figure shows the circuit architecture
of a self-contained isolator, Model AD210. The various models
differ, but their properties can be discussed in terms of the
device shown. An isolator of this type requires power from a
two-terminal dc supply. An internal oscillator converts the dc
power to ac, which is transformer-coupled to the shielded input
section, then converted to dc for the input stage and the auxiliary
power output. The ac carrier is also modulated by the amplifier
output, transformer-coupled to the output stage, demodulated
by a phase-sensitive demodulator (using the carrier as the reference), filtered and buffered, using isolated dc power (also available
for auxiliary circuitry) derived from the carrier.
The amplifier in this example is an uncommitted op amp, specified
for programmable gains from I to 100VN, as determined by its
feedback circuitry. Since both input terminals are floating, the
amplifier functions effectively as an instrumentation amplifier.
Most of the other devices in this series require just a single
external resistor to set the gain.
In the figure it can be seen that ac power is magnetically coupled
from the oscillator to the output stage. This permits the output
to operate at a dc common-mode potential with respect to power
common. An isolator of this type is said to provide three-port
isolation, because there .are three isolated ports: input, power
supply and output. Two-port devices are those in which there is
a dc connection between the oscillator power supply and the
output stage.
The AD210, as can be seen, is a completely self-contained device.
There are applications for which a degree of "unbundling" can
lead to economy and improved performance. For example, if
there are many input channels to be isolated, economies can be
realized by the use of a common oscillator. In addition, the
common oscillator makes it possible to avoid the possibility of
small errors due to beat frequencies developed by small amounts
of crosstalk in older amplifier designs.
Several synchronized multichannel devices are available. Model
204 is essentially a 202A with a power converter instead of an
oscillator. It requires a pair of leads for an oscillator input,
which can be furnished by an AD246 clock.
SPECIFICATIONS
The illustration on the next page shows a typical specification
block; the specifications of key interest are defined.
applications) and identifies devices that are three-port isolated.
Good starting points are: for high performance, the AD210; for
lowest cost, the AD202 and AD204, depending on whether the
application calls for few or many channels.
For an initial choice of data sheets to inspect for a given application,
the Selection Guide permits comparison on the basis of these
key characteristics: common-mode voltage, specified gain range
and frequency response. The "Notes" column indicates which
devices require ex:ternal oscillators (for lower cost in many-channel
SPEC IFI CATIONS (tJpicaI@ + 25"C, Us = + 15V unless oIherwise IPIICifiedl
NONLINEARITY - This is the
MODEL
peak deviation from a best straight
G~:':ge
line, expressed as a % of peak~toError
peak output. Should be considered
vs Temperature~Ot;5~0"~850C)
~hen signal fidelity is of prime ~ vs SUPPiyvoltageto
unportance.
-,N,.;o;:.;nl:;..m:.;.e':;..";;:ty,..,'
INPlITVQLTAGERATINGS
AD210AN
IVN-IOOVN
AD210BN
±2%max
j;
CMV, INPUTS TO OUTPUTSVoltage that may be safely applied
to both inputs with respect to
outputs or power common. Necessary consideration in applications
with high CMV input or when
high voltage transients may occur
1% max
:~~::~:::
:to 002%N
±_O,-O;.;2:.:.S%:.;.m::;,::;x,-_ _...:±:..;O;.;O:.;.12:..;%:..;m:;:.:;:x__
====___
Linear DdTerential Range
Maximum Safe Differential Input
~Max CMVInpUHo-Output
MAX SAFE DIFFERENTIAL~
INPUT - Max voltage that can be
safely applied across input terminals.
Important to consider for fail-safe
designs io tbe presence of high
voltages.
::~~:,;,<,;::~nuou,
::tIOV
± lSV
••. . . - - - - - -
~~~~m~'k:
~
Common·ModeRe,cctmn
at the input.
CMR, INPUTS TO OUTPUTS-
Indicates ability to reject commonmode v,oltages between inputs
Le~~~!~!~:~:~~t!~o~:~e
and outputs. Imponant when
(<> 240V200Hz
4",Vp-p
SOnV/YHZ
*
*
*
*
*
*
FREQUENCY RESPONSll
Bandwidth(VosIOVp-p,G= I-SOVN)
Settling Time, to:!: IOmV (I0V Step)
SkHz
Ims
SkHz
2kHz
2kHz
*
*
*
OFFSET VOLTAGE (RTI)
Initial, @+25'CAdjustabletoZero
(:!:15 ±15/G)mVmax
(±S±SIG)mVmax
(±15 ±15/G)mVmax
(±5±SIG)mVmax
*
*
(:!: IO±~)",VI'C
*
RATED OUTPUT
Voltage (Out HI to Out LO)
Voltage at Out HI or Out LO(Ref. Pin 32)
Output Resistance
Output Ripple, 100kHz Bandwidth
5kHz Bandwidth
:!:SV
±6.5V
3kO
IOmVpk-pk
0.5mVrms
3kn
7kn
7kn
*
*
*
*
*
*
ISOLATED POWER OUTPUT2
Voltage, No Load
Accuracy
Current
Regulation, No Load to Fun Load
Ripple
±7.5V
±Io%
2mA (Either Output)'
5%
100mVpk-pk
*
*
.
*
*
*
*
*
*
*
*
OSCILLATOR DRIVE INPUT
Input Voltage
Input Frequency
·
I SV pk-pk nominal
2SkHz nontinal
ISVpk-pknominaI
2SkHz nominal
N/A
N/A
N/A
N/A
POWER SUPPLY (AD202 Only)
Voltage, Rared Performance
Voltage, Operating
Current,NoLoad(Vs= + 15V)
N/A
N/A
N/A
N/A
N/A
N/A
+15V:!:5%
+ ISV ±Io%
SmA
+ISV ±5%
+ISV±lo%
SmA
TEMPERATURE RANGE
Rated Performance
Operating
StOtage
Oto +7O'C
- 4O"C to + S5'C
-4O'Cto +S5'C
*
*
*
•
*
.
2.0S" x 0.250" x 0.62S"
2.10" x 0.700" x 0.350"
.
*
*
*
*
vs. Temperature (0 to + 70'C)
PACKAGE DIMENSIONS'
SIP Package (Y)
DIP Packase (N)
.
NOTES
*SpectflCabOns ~asAD204J.
INonlineantyJSspecafJedasa%dCV1lluonfromabeststnughthne.
21.0..,F mmdecoupling reqwred (see text)
33mA with one supply loaded
'Width 1$0.25" typ, O.26"max
SpecJfications sublect to change Without notice
5-8 ISOLA TION AMPLIFIERS
*
*
2mA (Either Output)'
*
*
*
4OO11A Total
·
*
*
4OO",ATotal
*
*
PIN DESIGNATIONS
AD202/AD204 SIP PACKAGE
PIN
1
2
3
4
AD202/AD204 DIP PACKAGE
FUNCTION
PIN
FUNCTION
+ INPUT
1
2
3
18
19
20
21
+ INPUT
INPUTIV,sa COMMON
-INPUT
OUTPUTLO
OUTPUT HI
+ 15V POWER IN (AD202 ONLV)
CLOCK INPUT (AD204 ONLV)
CLOCK/POWER COMMON
+ V,sa OUTPUT
-V,sa OUTPUT
INPUT FEEDBACK
INPUTIV,sa COMMON
-INPUT
INPUT FEEDBACK
- V,sa OUTPUT
+ V,sa OUTPUT
5
6
+ 15V POWER IN (AD202 ONLV)
CLOCK/POWER COMMON
CLOCK INPUT (AD204 ONLV)
OUTPUTLO
OUTPUT HI
31
32
33
37
38
22
36
37
38
AD202/AD204 ORDERING GUIDE
Model
Package
Option
Max CommonMode Voltage (Peak)
Max
Linearity
AD202JY
AD202KY
AD202JN
AD202KN
SIP
SIP
DIP
DIP
lOOOV
2000V
IOOOV
2000V
±O.O5%
, ±O.02S%
±O.OS%
±O.02S%
AD204JY
AD204KY
AD204JN
AD204KN
SIP
SIP
DIP
DIP
IOOOV
2000V
lOOOV
2000V
±O.OS%
±O.02S%
±O.OS%
±O.02S%
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
AD202/AD204 SIP PACKAGE
AD202/AD204 DIP PACKAGE
o 250 (6 3) TYP
o260 (6 6) MAX
2::::2::::4-.----~i r.~ij
010
FRONT VIEW
MAX
VIEW
.L ~nnnnr---------rnnr-=-.
•
--L
.-
'--i t-- o
'
10 (25) TYP
..f-- • 3~ _+5
0010x0020
..j
(025)(051)
I--
010 (2 5) TVP
BOTTOM VIEW
2~4_1~6
I l..j 1-005 (13)
r--- i - - - 1 30 (33 0)
,--00--tl-tU 0010xOx 020
(0 25
T -_J.~
123
1 -T--
ACI058 MATING SOCKET
rlMAX
i--
(!76~) ------~·r
-I ~
0 075
(19)
--*l-$~~~~:-;~ 1
The "noninverting" circuit of Figures 5 and 6 can also be used
to advantage when a signal inversion is needed: just interchange
either the input leads or the output leads to get inversion. This
approach retains the high input resistance of the "noninvertiog"
circuit, and at unity gain no gain-setting resistors are needed.
When the isolator is not powered, a negative input voltage of
more than about 2V will cause an input current to flow. If the
signal source can supply more than a few rnA under such conditions, the 2kO resistor shown in series with IN + should be
used to limit current to a safe value. This is particularly in1portant
with the AD202, which may not start if a large input current is
present.
Figure 7 shows how to accommodate current inputs or sum
currents or voltages. This· circuit can also be used when the
input signal is larger than the ± SV input range of the isolator;
for example, a ± SOY input span can be accommodated with
RF = 20k 80d Rs = 200k. Once again, a capacitor from FB to
IN COM is required for gains above S.
5k
GAIN
AD202
OR
AD204
47.5k
2k
RG
Vs
2000
50k
Figure Sa. Adjustments for Noninverting Connection of
OpAmp
V=-(VS1~+VS2=:2 +lsRF+"')
RF2:20kO
Figure 7. Connections for Summing or Current Inputs
Adjustments. When gain 80d zero adjustments are needed, the
-circuit detsils will depend on whether adjustments are to be
made at the isolator input or output, 80d (for input adjustments)
on the input circuit used. Adjustments are usually best done on
the input side, because it is better to null the zero ahead of the
gain, 80d because gain adjustment is most easily done as part of
the gain-setting network. Input adjustments are also to be preferred
when the pots will be near the input end of the isolator (to
minimize common-mode strays). Adjustments on the output
side might be used if pots on the input side would represent a
hazard due to the presence of large common-mode voltages
during adjustment.
Figure 8a shows the input-side adjustment connections for use
with the "noninverting" connection of the input amplifier. The
zero adjustment circuit injects a sma1l adjustment voltage in
series with the low side of the signal source. (This will not work
if the source has 800ther current path to input common or if
current flows in the signal source LO lead). Since the adjustment
voltage is injected ahead of the gain, the values shown will work
for 80Y gain. Keep the resistaoce in series with input LO below
a few hundred ohms to avoid CMR degradation .
,-
Also shown in Figure 8a is the preferred means of adjusting the
gain-setting network. The circuit shown gives a nominal RF of
SOIdl, 80d will work properly for gains of ten or greater. The
adjustment becomes less effective at lower gains (its effect is
halved at G = 2) so that the pot will have to be a 1arger fraction
of the total RF at low gain. At G = 1 (follower) the gain cannot
be adjusted downward without compromising input resistaoce;
it is better to adjust gain at the signal source or after the output.
Figure 8b shows adjustments for use with inverting input circuits.
The zero adjustment nulls the voltage at the summing node.
This method is preferable to current injection because it is less
affected by subsequent gain adjustment. Gain adjustment is
again done in the feedback; but in this case it will work all the
way down to unity gain (8Od below) without alteration.
AD202
OR
AD204
Vs
.
Figure 8b. Adjustments for Summing or Current Input
(Circuit figures shown on this page are for SIP style packages. Refer to third page of this data sheet for proper DIP
package pin-out.)
ISOLA TlON AMPLIFIERS 5-13
Figure 9 shows how zero adjustment is done at the output by
taking advantage of the semi-floating output port. The range of
this adjustment will have to be increased at higher gains; if that
is done, be sure to use a suitably stable supply voltage for the
pot circuit.
180
__ 1
160
...
,
........
140
There is no easy way to adjust gain at the output side of the
isolator itself. If gain adjustment must be done on the output
side, it will have to be in a following circuit such as an output
buffer or filter.
t
........
~
~ 100
III
I
If,
...... . ... ........ ...
... If,O',.
r-..... .....
~
80
;,..-~
20
..._--
-. ... ---~ I:!!.--
~ j"--..
~ ~':'D.t
l.O~7
~
It.~
D.trl
60
40
10
-,.-----
"~Torl
1"' ...
120
G=IIOO
-G=I
5060 100
200
500
r==:.=:.
Ik
2k
5k
FREQUENCY - Hz -
Figure 70b. AD202
Figure 9. Output-Side Zero Adjustment
Common-Mode Performance. Figures lOa and lOb show how
the common-mode rejection of the AD202 and AD204 varies
with frequency, gain, and source resistance. For these isolators,
the significant resistance will normally be that the path from the
source of the common-mode signal to IN COM. The AD202
and AD204 also perform well in applications requiring rejection
of fast common-mode steps, as described in the Applications
section.
180
160
I
1-..
...... ..
....
140
t
120
III
I
~ 100
~ r-.....
........
~
u
80
............
-G=1
,
+60
+40
t;:~ ~ ...
~ ~o,.
...~ (J
......
,
-
. . ... ~,
,
. --
.!
,
-AD204
- - - AD202
-[
'"..,
AJPLlTUDE
RESPONSE
+20
I 1.:::::-: ....
~
I
~
't~F::. .....
~ ~'o,.,D.t
I""---. -,.,D.t..,
~
PHASE
I-- f--,RESPONSE
(G=I)
..
~,
-20
.
-:: r--..
..... ....
.....
I-~ .......
t':....
10
20
50 60 100
200
500
Ik
2k
5k
FREQUENCY - Hz _
Figure 70a. AD204
(Circuit figures shown on this page are for SIP style packages. Refer to third page of this data sheet for proper DIP
package pin-out.)
ISOLATION AMPLIFIERS
10
20
50
100 200
500
Ik
~
2k
~
0"
"', 0
-40
40
~74
At SO/60Hz, phase shift through the AD202/AD204 is typically
0.8°C (lagging). Typical unit - unit variation is ± 0.2°C
(lagging).
I
- __ G = 100
~
60
Dynamics and Noise. Frequency response plots for the AD202
and AD204 are given in Figure 11. Since neither isolator is
slew-rate limited, the plots apply for both large and small signals.
Capacitive loads of up to 470pF will not materially affect frequency
response. When large signals beyond a few hundred Hz will, be
present, it is advisable to bypass - V,so and + V,so to IN COM
with I",F tantalum capacitors even if the isolated supplies are
not loaded.
5k
PHASE
(DEGREES)
-50
~
10k
-100
20k
FREQUENCY - Hz -
Figure 77. Frequency Response at Several Gains
The step response of the AD204 for very fast input signals can
be improved by the use of an input filter, as shown in Figure
12. The filter limits the bandwidth of the input (to about S.3kHz)
so that the isolator does not see fast, out-of-band input terms
that can cause small amounts (± 0.3%) of internal ringing. The
AD204 will then settle to ±O.l% in about 300 microseconds for
a lOY step.
In applications where more than a few AD204s are driven by a
single clock driver, substantial current spikes will flow in the
power return line and in whichever signal out lead returns to a
low impedance point (usually output LO). Both of these tracks
should be made large to minimize inductance and resistance;
ideally, output LO should be directly connected to a ground
plane which serves as measurement common.
Current spikes can be greatly reduced by connecting a small
inductance (68",H-100f1H) in series with the clock pin of each
AD204. Molded chokes such as the Dale IM-2 series, with dc
resistance of about SO, are suitable.
•
Figure 12. Input Filter for Improved Step Response
Except at the highest useful gains, the noise seen at the output
of the AD202 and AD204 will be almost entirely comprised of
carrier ripple at multiples of 25kHz. The ripple is typically 2mV
p-p near zero output and increases to about 7mV p-p for outputs
of ± SV (lMHz measurement bandwidth). Adding a capacitor
across the output will reduce ripple at the expense of bandwidth:
for example, O.OS",F at the output of the AD204 will result in
l.SmV ripple at ± SV, but signal bandwidth will be down to
1kHz.
When the full isolator bandwidth is needed, the simple two-pole
active filter shown in Figure 13 can be used. It will reduce
ripple to O.lmV p-p with no loss of signal bandwith, and also
serves as an output buffer.
An output buffer or filter may sometimes show output spikes
that do not appear at its input. This is usually due to clock
noise appearing at the op amp's supply pins (since most op
amps have little or no supply rejection at high frequencies).
Another common source of carrier-related noise is the sharing of
a ground track by both the output circuit and the power input.
Figure 13 shows how to avoid these problems: the clock/supply
port of the isolator does not share ground or ISV tracks with
any signal circuits, and the op amp's supply pins are bypassed
to signal common (note that the grounded filter capacitor goes
here as well). Ideally, the output signal LO lead and the supply
common meet where the isolator output is actually measured,
e.g. at an AJD converter input. If that point is more than a few
feet from the isolator, it may be useful to bypass output LO to
supply common at the isolator with a O.I",F capacitor.
Figure 13. Output Filter Circuit Showing Proper
Grounding
Using Isolated Power. Both the AD202 and the AD204 provide
±7.SV power outputs referenced to input common. These may
be used to power various accessory circuits which must operate
at the input common-mode level; the input zero adjustment pots
described above are an example, and several other possible uses
are shown in the section titled Application Examples.
The isolated power output of the AD202 (400",A total from
either or both outputs) is much more limited in current capacity
than that of the AD204, but it is sufficient for operating micropower
op amps, low power references (such as the ADS89), adjustment
circuits, and the like.
The AD204 gets its power from an external clock driver, and
can handle loads on its isolated supply outputs of 2mA for each
supply terminal (+ 7.SV and -7.5V) or 3mA for a single loaded
output. Whenever the external load on either supply is more
than about 200",A, a I",F tantalum capacitor should be used to
bypass each loaded supply pin to input common.
(Circuit figurfJs shown on this page are for SIP style packages. Refer to third page of this data sheet for proper DIP
package pin-out.)
ISOLATION AMPLIFIERS 5-15
Up to 32 AD204s can be driven from a single AD246 (or equivalent)
clock driver when the isolated power outputs of the AD204s are
loaded with less than 200!IA each, at a worst-case supply voltage
of 14.2SV at the clock driver. The number of AD204s that can
be driven by one clock driver is reduced by one AD204 per
3.SmA of isolated power load current at 7.SV, distributed in
any way over the AD204's being supplied by that clock driver.
Thus a load of 1.7SmA from + VIS<> to - VISO would also count
as one isolator because it spans ISV.
It is possible to increase clock fanout by increasing supply vol.
above the 14.2SV minimum required for 32 loads. One additional
isolator (or 3.5mA unit load) can be driven for each 40mV of
increase in supply voltage up to ISV. Therefore if the minimum
supply voltage can be held to ISV - 1%, it is possible to operate
32 AD204's and S2mA of7.SV loads. Figure 14 shows the
allowable combinations of load current and channel count for
various supply voltages.
PCB Layout for Multicluumel Applications. The pinout of the
AD204Y has been designed to make very dense packing possible
in multichannel applications. Figure 16a shows the recommended
printed circuit board (PCB) layout for the simple voltage-follower
connection. When gain-setting resistors are present, 0.2S· channel
centers can still be achieved, as shown in Figure 16b.
.,.::..
CHANNEL INPUl'S
o
1
2
GRID1m!Y
~
CHANNEL OUTPUTS
TOMUX
Figure 168.
CH.O
CH.l
'iiI'Lo' 'IiIi:O'
MINIMUM SUPPlY VOLTAGE
Figure 14. AD246 Fanout Rules
Operation at Reduced Sipal Swing. Although the nominal
output signal swing for the AD202 and AD204 is ± SV, there
may be cases where a smaller signal range may be desirable.
When that is done, the fixed errors (principally offset terms and
output noise) become a larger fraction of the signal, but nonlinearity
is reduced. This is shown in Figure IS.
ft
it
J l
11---+-+J
0.025
0.02
~
III
~
~ 0.015
;z~
,. ...-
0.01
L
0.005
o
o
V
Figure 16b.
,.1
±3
OUTPUT SIGNAL SWING - ±V
Figure 15. Nonlinearity VB. Signal Swing
5-16 ISOLATION AMPLIFIERS
(Circuit figures shown on this page are for SIP style packages. Refer to third page of this data sheet for proper DIP
package pin-out.)
SynchroDization. Since AD204's operate from a common clock,
synchronization is inherent. AD202s will normally not interact
to produce beat frequencies even when mounted on O.2S-inch
centers. Interaction may occur in rare situations where a large
number of long, unshielded input cables are bundled together
and channel gains are high. In such cases, shielded cable may
be required or AD204's can be used.
APPLICATIONS EXAMPLES
Low-Level Sensor Inputs. In applications where the output of
low-level sensors such as thermocouples must be isolated, a lowdrift input amplifier can be used with an AD204, as shown in
Figure 17. A three-pole active filter is included in the design to
get normal-mode rejection of frequencies above a few Hz and to
provide enhanced common-mode rejection at 60Hz. If offset
adjustment is needed, it is best done at the trim pins of the
OP-07 itself; gain adjustment can be done at the feedback
resistor.
2370
AD589
68k
-15V
Figure 18. Process Current Input Isolator with Offset
The circuit as shown requires a source compliance of at least
SV, but if necessary that can be reduced by using a lower value
of current-sampling resistor and configuring the input amplifier
for a small gain.
39'
Lo~--~---+-+--~~~--4
cue
RET
Figure 17. Input Amplifier & Filter for Sensor Signals
High-Compliance Current Source. In Figure 19, an isolator is
used to sense the voltage across current-sensing resistor R to
allow direct feedback control of a high-voltage transistor or FET
used as a high-compliance current source. Since the isolator has
virtually no response to dc common-mode voltage, the closed-loop
current source has a static output resistance greater than 10 140
even for output currents of several mAo The output current
capability of the circuit is limited only by power dissipation in
the source transistor.
-10Vto +250V
Note that the isolated supply current is large enough to-mandate
the use of I ....F supply bypass capacitors. This circuit can be
used with an AD202 if a low-power op amp is used instead of
the OP-07.
Process Current Input with Offset. Figure 18 shows an isolator
receiver which translates a 4-20mA process current signal into a
o to + IOV output. A IV to SV signal appears at the isolator's
output, and a -IV reference applied to output LO provides the
necessary level shift (in multichannel applications, the reference
can be shared by all channels). This technique is often useful
for getting offset with a follower-type output buffer.
Rs
lkll
470pF
lOOk
+5V REF
MPS
Ul0
1---~20k
+
Vc
-15V
Figure 19. High-Compliance Current Source
(Circuit figures shown on this page are for SIP style packages. Refer to third page of this data sheet for proper DIP
package pin-out.)
ISOLA TION AMPLIFIERS 5-17
Motor Control Isolator. The AD202 and AD204 perform very
well in applications where rejection of fast common-mode steps
is important but bandwidth must not be compromised. Current
sensing in a full-wave bridge motor driver (Figure 20) is one
example of this class of application. l;'"or 200V common-mode
steps (I,...s rise time) and a gain of 50 as shown, the typical
response at the isolator output will be spikes of ± 5mV amplitude,
decaying to zero in less than 100,...s. Spike height can be reduced
by a factor of four with output fIltering just beyond the isolator's
bandwidth.
AD204
30>
+
AD589
-
-
-
-
IlOAD
=:
~
12mA max)
VLOAD ::'54V
Figure 21. Floating Current Source
+
200V de
Photodiode Amplifier. Figure 22 shows a transresistance connection used to isolate and amplify the output of a photodiode.
The photodiode operates at zero bias, and its output current is
scaled by Rp to give a + 5V full-scale output.
Figure 20. Motor Control Current Sensing
Floating Current Source/Ohmmeter. When a smaIl floating
current is needed with a compliance range of up to ± IOOOV dc,
the AD204 can be used to both create and regulate the current.
This can save considemble power, since the controlled current
does not have to return to ground. In Figure 21, an AD589
reference is used to force a smaIl fixed voltage across R. That
sets the current which the input op amp will have to return
through the load to zero its input. Note that the isolator's output
isn't needed at all in this application; the whole job is done by
the input section. However, the signal at the output could be
useful: it's the voltage across the load, referenced to ground.
Since the load current is known, the output voltage is proportional
to load resistance.
(Circuit figures shown on this page are for SIP style packages. Refer to third page of this data sheet for proper DIP
package pin-out.)
5-18 ISOLATION AMPLIFIERS
10"A J
F.S. ,
/v'
PHOTO
DIODE
Figure 22. Photodiode Amplifier
11IIIIIIII ANALOG
L..III DEVICES
FEATURES
High CMV Isolation: 2500V rms Continuous
:l:3500V peak Continuous
Small Size: 1.00"x2.10"xO.350"
Three-Port Isolation: Input. Output. and Power
Low Nonlinearity: :1:0.012% max
Wide Bandwidth: 20kHz Full-Power (-3dBI
Low Gain Drift: :I: 25ppm?C max
High CMR: 120dB (G=100VN)
Isolated Power: :l:15V @ :l:5mA
Uncommitted Input Amplifier
Precision, Wide Bandwidth,
3-Port Isolation Amplifier
AD210 I
AD210 FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
Multi-Channel Data Acquisition
High Voltage Instrumentation Amplifier
Current Shunt Measurements
Process $ignal Isolation
GENERAL DESCRIPTION
The AD210* is the latest member of a new generation of low
cost, high performance isolation amplifiers. This three-port,
wide bandwidth isolation amplifier is manufactured with surfacemounted components in an automated assembly process. The
AD210 combines design expertise with state-of-the-art manufacturing technology to produce an extremely compact and economical
isolator whose performance and abundant user features far exceed
those offered in more expensive devices.
The AD210 provides a complete isolation function with both
signal and power isolation supplied via transformer coupling
internal to the module. The AD210's functionally complete
design, powered by a single + 15V supply, e1iminates the need
for an external DClDC converter, unlike optically coupled isolation
devices. The true three-port design structure permits the AD210
to be applied as an input or output isolator, in single or multichannel applications. The AD210 will maintain its high performance under sustained common-mode stress.
Providing high accuracy and complete galvanic isolation, the
AD210 interrupts ground loops and leakage paths, and rejects
common-mode voltage and noise that may otherwise degrade
measurement accuracy. In addition, the AD210 provides protection from fault conditions that may cause damage to other sections
of a measurement system.
PRODUCT HIGHLIGHTS
The AD210 is a full-featured isolator providing numerous user
benefits including:
High Common-Mode Performance: The AD210 provides 2500V
rms (Continuous) and ± 3500V peak (Continuous) common-mode
voltage isolation between any two ports. Low input
capacitance of 5pF results in a 120dB CMR at a gain of 100,
and a low leakage current (21LA rms max @ 240V rms, 60Hz).
High Accuracy: With maximum nonlinearity of ±0.012%
(B Grade), gain drift of ± 25ppmf'C max and input offset drift
of (± 1O± 30/G) ILVrC, the AD210 assures signal integrity while
providing high level isolation.
Wide Bandwidth: The AD210's full-power bandwidth of 20kHz
makes it useful for wideband signals. It is also effective in applications like control loops, where limited bandwidth could result
in instability.
Small Size: The AD210 provides a complete isolation function
in a small DIP package just 1.00" x 2.10" x 0.350". The low
profile DIP package allows application in 0.5" card racks and
assemblies. The pinout is optimized to facilitate board layout
while maintaining isolation spacing between ports.
Three-Port Design: The AD210's three-port design structure
allows each port (Input, Output, and Power) to remain independent. This three-port design permits the AD210 to be used as
an input or output isolator. It also provides additional system
protection should a fault occur in the power source.
Isolated Power: ± 15V @ 5mA is available at the input and
output sections of the isolator. This feature permits the AD210
to excite floating signa1 conditioners, front-end amplifiers and
remote transducers at the input as well as other circuitry at the
output.
Flexible Input: An uncommitted operational amplifier is provided
at the input. This amplifier provides buffering and gain as required,
and facilitates many alternative input functions as required by
the user.
·Patent Peadlac
ISOLATION AMPLIFIERS 5-19
•
SPEC IFICAli ONS (tJpicaI@ + 25"1:; &Vs = +15V IIIIass aIharwisa spdiad)
MODEL
AD210AN
GAIN
Range
Error
vs. Temperature (0 10 + 70'C)
( - 25'C 10 + 85'C)
vs. Supply Voltage
Nonhnearityl
IVN-IOOVN
::t2%max
± 25ppmI'C max
± 5OppmI"C max
±0.002%IV
OUTLINE DIMENSIONS
AD210BN
Dimensions shown in inches and (mm).
± O.02S% max
I_
::tl%max
I'-rrU.". U""'UUrnUIMUr-----nU..,.,U--."..U
~DE ~EW
I~axmax
IrUUrnU......o
±0.012%max
15 (3 811
INPUT VOLTAGE RATINGS
Lmear Differential Range
Maximum Safe D.fferential Input
Max. CMV Inpul-Io-OUIPUI
±IOV
±15V
ac, 60Hz, Continuous
dc, Continuous
Common~Mode Rejecnon
6OHz,G=IOOVN
RssSOOI1 Impedance Imbalance
Leakage Current Input-to-Output
@240Vrms,6OHz
2500Vrms
±3500Vpeak
INPUT IMPEDANCE
Differential
Common Mode
(Ir
Spa typ (200pA max)
2nAmax
IOnAmax
I'"
--I I-- 0 100 (254) TVP
IT -I
It
(25)
IVI~
±ISV
±l00/o
±5mA
Sec Text
SecText
POWER SUPPLY
Voltage, Rated Performance
Voltage, Operating
Currenl, Quiescenl
Currenl, Full Load-Full Si8naI
SOmA
SOmA
TEMPERATURE RANGE
Rated PerformllllCe
Operating
Storage
- 25'C 10 + 85'C
-4O'C10 +85'C
- 4O'C 10 + 85'C
(±5 ± 15/G)mVmax
*
±lOVnun
+15Vdc ±5%
+15Vdc±10%
1.00 x 2.10 x 0.350
25.4 x 53.3 x 8.9
NOTES
·Specifications same as AD210AN.
IGain DODIineuity ioacues by ± O.OO2%lmA when the IIDIated power outputs are UICd.
'RTI-Rofmodto_,
JA rcduc:ed. upallWiDg is I'CCOIDII1CI1de when both ± Vrss and ± VO$S supphes are
fully w.dcd. due to IUppIy vol. . rcdUChOJJ..
4See text for detuIcd infotmabOD.
00 0
~lo 00+
0
0000
1-1
'-~.'~~
-..tI~0300 J....-
1--0.,00(251
I
(76)
PIN DESIGNATION FUNCTION
1 Vo
Output
2 OCOM
Output Common
3 + Voss
+ Isolated Power@ Output
4 -Voss
-Isolated Power @Output
14 +V,ss
+ Isolated Power@ Input
15 -V,SS
-Isolated Power @ Input
16 FB
Input Feedback
17 -IN
-Input
18 ICOM
Input Common
19 +IN
+ Input
29 PwrCom
Power Common
30 Pwr
Power Input
WARNING!
~
~~~
'41Tl TJ"lo' ~fN'>llIJF
rJEVI(
E
CAUTION
ESD (I!lectro-Static-Discbarge) SCDBitive devic:c.
Permanent damaae may ocicur on um::oDIICCted devices subject to high energy electrostatic fields.
Unuacd devices must be stored in conductive foam
or shWltS. The protective foam should be disciwFd to the destillation socket before deviccs are
removed.
5-20 ISOLATION AMPLIFIERS
0100DIA.CIS: 0
@'-
PACKAGE DIMENSIONS
to.cbaatP: Without nobCc.
0 180DIA. TVP
O~pO
AD210 PIN DESIGNATIONS
150fLS
500fLS
ISOLATED POWER OlITPuTS'
Voltage, No Load
Accuracy
Currenl
Regulation, No Load 10 Full Load
Ripple
-,
--1 ~o 15 (3751
20kHz
15kHz
111 max
IOmVp-pmax
(201
(~2":)LI
O.OlpAIV'Hi
RATEDOlITPUT'
Voitage,2k1lLoad
Impedance
Ripple, (Bandwidth = 100kHz)
Z 10(53.31
-,~: ~150'(31.51---"'.~1
4....Vrms
(±15 ±45/G)mVmax
(± 10 ±30/G)fLVI'C
(±IO ±501G)fLVI'C
Spcaficatioas subject
4 3 2 1
19 1817 16 15 14
--l f-- 0 150 (3 811
18nV/YHz
OFFSET VOLTAGE (RTI)'
Initial,@ + 25'C
vs. Temperature(Olo +7O'C)
( - 25'C 10 + 85'C)
Millimeters
J
BOTTOM VIEW
'1111 ( 1
ACIOS9 MATING SOCKET
INPUT DIFFERENCE CURRENT
Initial, @ + 25'C
vs. Temperalure(Olo +70'C)
(-25'Clo + 85'C)
Inches
1
29~O
2f,LArmsmax
10"11
5GI1115pF
~
I\D210
0800
30pA typ (4OOpA max)
10nAmax
30nAmax
FREQUENCY RESPONSE
BandWldlh ( - 3dB)
G=IVN
G=IOOVN
SettiingTime(± IOmV,20VStep)
G=IVN
G=IOOVN
SIewRate~G= IVIV)
~~OQ20-X0010PIN12PLACES
120dB
INPUT BIAS CURRENT
Inma!, @ + 25°C
vs. Temperalure(Olo +70'C)
( - 25'C 10 + 85'C)
INPUT NOISE
Voltage (1kHz)
(IOHzto 10kHz)
Currenl (1kHz)
-I
21015331max
INSIDE THE AD210
The AD210 basic block diagram is illustrated in Figure 1. A
+ 15V supply is connected to the power port, and ± l5V isolated
power is supplied to both the input and output ports via a 50kHz
carrier frequency. The uncommitted input amplifier can be used
to supply gain or buffering of input signals to the AD21O. The
fullwave modulator translates the signal to the carrier frequency
for application to transformer TI. The synchronous demodulator
in the output port reconstructs the input signal. A 20kHz, threepole filter is employed to minimize output noise and ripple.
Finally, an output buffer provides a low impedance output
capable of driving a 2k!1 load.
Figure 3. Input Configuration for G> 1
Figure 4 shows how to accommodate current inputs or sum
currents or voltages. This circuit configuration can also be used
for signals greater than ± IOV. For example, a ± lOOV input
span can be handled with RF =20kn and RSI =200kn .
PWR
PWRCOM
Figure 1. AD210 Block Diagram
USING THE AD210
The AD210 is very simple to apply in a wide range of applications.
Powered by a single + 15V power supply, the AD210 will provide
outstanding performance when used as an input or output isolator,
in single and multichannel configurations.
Input Configurations: The basic unity gJin configuration for
signals up to ± lOY is shown in Figure 2. Additional input
amplifier variations are shown in the following figures. For
smaller signa1levels Figure 3 shows how to obtain gain while
maintaining a very high input impedance.
Figure 4. Summing or Current Input Configuration
Adjustments
When gain and offset adjustments are required, the actual circuit
adjustment components will depend on the choice of input
configuration and whether the adjustments are to be made at
the isolator's input or output. Adjustments on the output side
might be used when potentiometers on the input side would
represent a hazard due to the presence of high common-mode
voltage during adjustment. Offset adjustments are best done at
the input side, as it is better to null the offset ahead of the gain.
Figure 5 shows the input adjustment circuit for use when the
input amplifier is configured in the noninverting mode. This
offset adjustment circuit injects a small voltage in series with the
V""
±10V
Figure 2. Basic Unity Gain Configuration
The high input impedance of the circuits in Figures 2 and 3 can
be maintained in an inverting application. Since the AD210 is a
three-port isolator, either the input leads or the output leads
may be interchanged to create the signal inversion.
Figure 5. Adjustments for Noninverting Input
ISOLA TION AMPLIFIERS 5-21
•
low side of the signal source. This will not work if the source
has another current path to input common or if current flows in
the signal source LO lead. To !l).inimize CMR degradation, keep
the resistor in series with the input LO below a few hundred
ohms.
Figure 5 also shows the preferred gain adjustment circuit. The
circuit shows Rp of 50kll, and will work for gains of ten or
greater. The adjustment becomes less effective at lower gains
(its effect is halved at G = 2) so that the pot will have to be a
larger fraction of the total Rp at low gain. At G = 1 (follower)
the gain cannot be adjusted downward without compromising
input impedance; it is better to adjust gain at the signal source
or after the output.
Figure 6 shows the input adjustment circuit for use when the
input amplifier is configured in the inverting mode. The offset
adjustment nulls the voltage at the summing node. This is preferable to current injection because it is less affected by subsequent
gain adjustment. Gain adjustment is made in the feedback and
will work for gains from I to lOOVN.
PCB Layout for Multichannel Applications: The unique pinout
positioning minimizes board space constraints for multichannel
applications. Figure 8 shows the recommended printed circuit
board layout for a noninverting input configuration with gain.
CHANNEL OUTPUTS
GRID
POWER
l
T
R,
R,
RG
RG
CHANNEL INPUTS
V OUT
Figure 8. PCB Layout for Multichannel Applications
with Gain
Synchronization: The AD2I0 is insensitive to the clock of an
adjacent unit, eliminating the need to synchronize the clocks.
However, in rare instances channel to channel pick-up may
occur if input signal wires are bundled together. If this happens,
shielded input cables are recommended.
Figure 6. Adjustments for Inverting Input
Figure 7 shows how offset adjustments can be made at the
output, by offsetting the floating output port. In this circuit,
± 15V would be supplied by a separate source. The AD2l0's
output amplifier is fIXed at unity, therefore, output gain must
be made in a subsequent stage.
PERFORMANCE CHARACTERISTICS
Common.Mode Rejection: Figure 9 shows the common-mode
rejection of the AD2l0 versus frequency, gain and input source
resistance. For maximum common-mode rejection of unwanted
signals, keep the input source resistance low and carefully lay
out the input, avoiding excessive stray capacitance at the input
terminals.
'8.
I
-- ............. ",ol " GTGJ100
"'at. . r-r-........._~
'6.
'4.
.....
~ 120
,
~
~
(,,) 100
8.
--
.....
o
..........
-
-....;..;
....
Ft-'f'~J
~(}
Il _
lo
~l}
.....
to'::::-70kl/
"
,
.....
10
20
5060 100
-
--
- -.........
------....:::.::~
-
r::..- --
6.
•
..
:-- r -
200
500
1k
2k
-Sk
10k
FREQUENCY - Hz
Figure 7. Output-Side Offset Adjustment
5-22 ISOLA TlON AMPLIFIERS
Figure 9. Common-Mode Rejection vs. Frequency
Phase Shift: Figure 10 illustrates the AD210's low phase shift
and gain versus frequency. The AD210's phase shift and wide
bandwidth performance make' it well suited for applications like
power monitors and controls systems.
~
40
G
20
=
,.-G
+0.02
100~t\1,\
\
J
-100
-.0
-120
11
10k
:;:
..... /
-2
-.
-6
-0"-10
'"w
:rI:z:
-8
-8
-6
-4
+2
-2
+4
+6
+8
+10
OUTPUT VOLTAGE SWING - Volts
1:1.
Figure 12. Gain Nonlinearity Error vs. Output
-140
lOOk
100
001
FREQUENCY - Hz
.0
00. .
Figure 10. Phase Shift and Gain vs. Frequency
80
0008
70
0007
~
0,006
I
go
i
~
o
50
K
~40
i'"
••
30
ffi
2.
/'
10
50
40
.... /
'"~60
Input Noise vs. Frequency: Voltage noise referred to the input
is dependent on gain and signal bandwidth. Figure II illustrates
the typical input noise in nWv'Hz of the AD210 for a frequency
range from 10 to 10kHz.
~,
w
:g
./
""-.. -.......
-003
I;:
80
-40
1k
-
+2
...........
-002
.0 ,
\
-80
000
-001
'\
-20
.,/
+4
-40
\
z
100
I
2.
~
10
'",
=1
'",
~
+6
+003
+001
.0
~
+8
+0"
Z
2'
'"
0004
'0
'",
gj
0003
ffi
0002
0000
10
12
14
16
18
20
TOTAL SIGNAL SWING - Volts
Figure 13. Gain Nonlinearity vs. Output Swing
.......... ......
Gain VS. Temperature: Figure 14 illustrates the AD21O's gain
vs. temperature performance. The gain versus temperature
performance illustrated is for an AD210 configured as a unity
gain amplifier.
10
10
"
0005
0001
•o
~
30
/'"
V
V
V
go
1k
100
10k
FREQUENCY - Hz
.00
200
G=1
Figure ". Input Noise vs. Frequency
Z
-200
l';
-400
!
-600
~
Gain Nonlinearity VS. Output: Gain Nonlinearity is defined as
the deviation of the output voltage from the best straight line,
and is specified as % peak-to-peak of output span. The AD210B
provides guaranteed maximum nonlinearity of ±0.012% with an
output span of ± 10V. The AD210's nonlinearity performance is
shown in Figure 12.
Gain Nonlinearity VS. Output Swing: The gain nonlinearity of
the AD210 varies as a function of total signal swing. When the
output swing is less than 20 volts, the gain nonlinearity as a
fraction of signal swing improves. The shape of the nonlinearity
remains constant. Figure 13 shows the gain nonlinearity of the
AD210 as a function of total signal swing.
e
gj
'"ffi
-800
~
-1000
"
-1200
-1400
V
/
/
/
-.........
i'--..
/
/
V
-1600
-25
+25
+50
TEMPERATURE lOCI
+70
+85
Figure 14. Gain vs. Temperature
ISOLA T/ON AMPLIFIERS 5-23
•
Isolated Power: The AD210 provides isolated power at the
input and output ports. This power is useful for various signal
conditioning tasks. Both ports are rated at a nominal ± lSV
at SmA.
The load characteristics of the isolated power supplies are shown
in Figure IS. For example, when measuring the load rejection
of the input isolated supplies VISS, the load is placed between
+ VISS and - VISS' The curves labeled VIss and Voss are the
individual load rejection characteristics of the input and the
output supplies, respectively.
There is also some effect on either isolated supply when loading
the other supply. The curve labeled CROSSLOAD indicates the
sensitivity of either the input or output supplies as a function of
the load on the opposite supply.
Under any circumstances, care should be taken to ensure that
the power supplies do not accidentally become shorted.
The isolated power supplies exhibit some ripple which varies as
a function of load. Figure 16a shows this relationsliip. The
AD210 has internal bypass capacitance to reduce the ripple to a
point where performance is not affected, even 'under full load.
Since the internal circuitry is more sensitive to noise on the
negative supplies, these supplies have been filtered more heavily.
Should a specific application require more bypassing on the
isolated power supplies, there is no problem with adding external
capacitors. Figure 16b depicts supply ripple as a function of
external bypass capacitance under full load.
1V
~
30~~----------~-------------4------~
.
~
~ 100mV
"
" r--..
"-
~
£,
w
~
~
g
25~----------~~~~~-------1------~
10mV
I'-..
'"
r-....
,(+v"'J
+Vos
~
iii:
(-v"' J
Voss
""'-VOSS
~::' SIMrTANEOUS
V1SS SIMULTANEOUS
20L-____________-L____________
______
~
1mV
o 1f1F
100p,F
10f1F
~
CAPACITANCE
10
CURRENT- mA
Figure 15. Isolated Power Supplies vs. Load
Lastly, the curves labeled Voss simultaneous and VISS simultaneous indicate the load characteristics of the isolated power
supplies when an equal load is placed on both supplies.
The AD210 provides short circuit protection for its isolated
power supplies. When either the input supplies or the output
supplies are shorted to input common or output common, respectively, no damage will be incurred, even under continuous
,application of the short. However, the AD210 may be damaged
if the input and output supplies are shorted simultaneously.
100
0.
Q.
Figure 16b. Isolated Power Supply Ripple vs. Bypass
Capacitance (Volts p-p, 1MHz Bandwidth, 5mA Load)
APPLICATIONS EXAMPLES
Noise Reduction in Data Acquisition Systems: Transformer
coupled isolation amplifiers must have a carrier to pass both ac
and dc siguals through their sigual transformers. Therefore,
some carrier ripple is inevitably passed through to the isolator
output. As the bandwidth of the isolator is increased more of
the carrier signal will be present at the output. In most cases,
the ripple at the AD21O's output will beinsigificant when compared
to the measured signal. However, in some applications, particularly
when a fast analog-to-digital converter is used following the
isolator, it may be desirable to add filtering; otherwise ripple
may cause inaccurate measurements. Figure 17 shows a circuit
that will limit the isolator's bandwidth, thereby reducing the
carrier ripple.
75
>
E
~
Do
I!,
a:
50
R=
C~~5) kH
LOAD (mAl
+15V
Figure 16a. Isolated Supply Ripple vs. Load
(ExternaI4.7p.F Bypass)
5-24 ISOLA TlON AMPLIFIERS
Figure 17. 2-Pole, Output Filter
Self-Powered Current Source
The output circuit shown in Figure 18 can be used to create a
self-powered output current source using the AD210. The 2kO
resistor converts the voltage output of the AD2lO to an equivalent
current VOUT/2kO. This resistor directly affects the output gain
temperature coefficient, and must be of suitable stability for the
application. The external low power op amp, powered by + Voss
and - Voss, maintains its summing junction at output common.
All the current flowing through the 2kO resistor flows through
the output Darlington pass devices. A Darlington configuration
is used to minimize loss of output current to the base. The low
leakage diode is used to protect the base-emitter junction again~t
reverse bias voltages. Using - Voss as a current return allows
more than lOY of compliance. Offset and gain control may be
done at the input of the AD210 or by varying the 2kO resistor
and summing a small correction current directly into the summing
node. A nominal range of I-SmA is recommended since the
current output cannot reach zero due to reverse bias and leakage
currents. If the AD210 is powered from the input potential, this
circuit provides a fully isolated, wide bandwidth current output.
This configuration is limited to SmA output current.
the input terminal (cold-junction). Ambient temperature changes
from 0 to + 40°C sensed by the ADS90, are cancelled out at the
cold junction. Total circuit gain equals 183; 100 and 1.83, from
Al and the AD210 respectively. Calibration is performed by
replacing the thermocouple junction with plain thermocouple
wire and a millivolt source set at O.OOOOV (O°C) and adjusting \
Ro for EOUT equal to O.OOOV. Set the millivolt source to
+0.0218SV (400°C) and adjust ~ for VOUT equal to +4.000V.
This application circuit will produce a nonlinearized output of
about + lOmV/oC for a 0 to + 400°C range.
Figure 20. Isolated Thermocouple Amplifier
v~
0-10V
Figure 18. Self-Powered Isolated Current Source
Isolated V-to-I Converter
Illustrated in Figure 19, the AD2l0 is used to convert a 0 to
+ 10V input signal to an isolated 4-20mA output current. The
AD210 isolates the 0 to + lOY input signal and provides a proportional voltage at the isolator's output. The output circuit
converts the input voltage to a 4-20mA output current, which in
turn is applied to the loop load R LOAD •
Precision Floating Programmable Reference
The AD210, when combined with a digital-to-analog converter,
can be used to create a fully floating voltage output. Figure 21
shows one possible implementation.
The digital inputs of the AD7S41 are TTL or CMOS compatible.
Both the AD7541 and ADS81 voltage reference are powered by
the isolated power supply + VISS ' IcoM should be tied to input
digital common to provide a digital ground reference for the
inputs.
The AD7S41 is a current output DAC and, as such, requires an
external output amplifier. The uncommitted input amplifier
internal to the AD210 may be used for this purpose. For best
results, its input offset voltage must be trimmed as shown.
The output voltage of the AD2l0 will go from OV to - 10V for
digital inputs of 0 and full scale, respectively. However, since
the output port is truly isolated, VOUT and OCOM may be freely
interchanged to get 0 to + lOY.
This circuit provides a precision O-IOV programmable reference
with a ± 3S00V common-mode range.
Figure 19. Isolated Voltage-to-Current Loop Converter
Isolated Thermocouple Amplifier
The AD210 application shown in Figure 20 provides amplification,
isolation and cold-junction compensation for a standard J type
thermocouple. The ADS90 temperature sensor accurately monitors
Figure 21. Precision Floating Programmable Reference
ISOLA TlON AMPLIFIERS 5-25
•
CHANNEL 1
4'~
~
25U
SOk
+V
-v
COM
CHANNEL 2
AD7502
MULTI PLEXER
TO
AID
CHANNEL 3
CHANNEL 4
+V1SS
AD584 f'+:.:l:.;OV'--_ _- ,
DC POWER
SOURCE
Al, A2 = AD547
Figure 22. Multichannel Data Acquisition Front-End
MULTICHANNEL DATA ACQUISmON FRONT·END
Illustrated in Figure 22 is a four-channel data acquisition front-end
used to condition and isolate several common input signals
found in various process applications. In this application, each
AD210 will provide complete isolation from input to output as
well as channel to channel. By using an isolator per channel,
maximum protection and rejection of unwanted siguals is obtained.
The three-port design allows the AD210 to be configured as an
input or output isolator. In this application the isolators are
configured as input devices with the power port providing additional protection from possible power source faults.
Channell: The AD210 is used to convert a 4-20mA current
loop input signal into a O-IOV input. The 250 shunt resistor
converts the 4-20mA curreot into a + 100 to + 500mV signal.
The signal is offset by - 100mV via Ro to produce a 0 to + 400mV
input. This signal is amplifIed by a gain of 25 to produce the
desired 0 to + lOY output. With an opeo circuit, the AD210
will show - 2.5V at the output.
Channel 2: In this channel, the AD210 is used to condition and
isolate a current output temperature transducer, Model AD590.
At + 25°C, the AD590 produces a nominal current of 298.21JA.
This level of current will change at a rate of Ij.LAloC. At -17.8°C
(OOF), The AD590 current will be reduced by 42.8j.LA to
+255.41JA. The AD580 refereoce circuit provides an eqnal but
5-26 ISOLA TION AMPLIFIERS
opposite current, resulting in a zero net current flow, producing
a OV output from the AD21O. At + 100°C ( + 212°F), the AD590
current output will be 373.21JA minus the 255.41JA offsetting
current from the AD580 circuit to yield a + 117.8j.LA input
current. This curreot is converted to a voltage via RF and Ro to
produce an output of + 2.12V. Channel 2 will produce an output
of + IOmVrF over a 0 to + 212°F span.
Channel 3: Channel 3 is a low level input channel configured
with a high gain amplifier used to condition millivolt siguals.
With the AD21O's input set to unity and the input amplifier set
for a gain of 1000, a ± IOmV input will produce a ± lOY at the
AD210's output.
Channel 4: Channel 4 illustrates one possible configuration for
conditioning a bridge circuit. The ADS84 produces a + IOV
excitation voltage, while Al inverts the voltage, producing negative
excitation. A2 provides a gain of lOOOVN to amplify the low
level bridge signal. Additional gain can be obtained by reconfiguration of the AD210's input amplifier. ± V1SS provides the
complete power for this circuit, eliminating the need for a separate
isolated excitation source.
Each channel is individually addressed by the multiplexer's
channel select. Additional filtering or signal conditioning should
follow the multiplexer, prior to an anaiog-to-digital conversion
stage.
r'IIIIIANALOG
WDEVICES
FEATURES
Low Nonlinearity: ±O.012% max (AD295C)
Low Gain Drift: ± 60ppmrC max
Floating Input and Output Power: ± 15V dc @ 5mA
3-Port Isolation: ±2500V CMV (Input to Output)
Complies with NEMA ICS1-111
Gain Adjustable: 1VN to 1000VN
User Configurable Input Amplifier
Precision Hybrid
Isolation Amplifier
AD295 I
AD295 FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
Motor Controls
Process Signal Isolator
High Voltage Instrumentation Amplifier
Multi-Channel Data Acquisition Systems
Off Ground Signal Measurements
GENERAL DESCRIPTION
The AD295 is a high accumcy, high reliability hybrid isolation
amplifier designed for industrial, instrumentation and medical
applications. Three performance versions are available offering
guaranteed nonlinearity error at lOY pop output: ±O.05% max
(AD295A), ±O.025% max (AD295B), ±O.012% max (AD295C).
Using a pulse width modulation technique the AD295 provides
3-port isolation between input, output and power supply ports.
Using this technique, the AD295 interrupts ground loops and
leakage paths and minimizes the effect of high voltage transients.
Additionally, floating (isolated) power ± 15V dc @ SmA is
available at both the input and output. The AD295's gain can
be programmed at the input, output or both sections allowing
for user flexibility. An uncommitted input amplifier allows
configumtion as a buffer, inverter, subtractor or differential
amplifier.
The AD295 is provided in an epoxy sealed ceramic 4O-pin
package that insures quality performance, high stability and
accuracy. Input/output pin spacing complies with NEMA
(ICSl-lll) separation specifications required for many industrial
applications.
Medical: In biomedical and patient monitoring equipment like
diagnostic systems and blood pressure monitors, the AD295
provides protection from lethal ground fault currents. Low level
signal recording and monitoring is achieved with the AD295's
low input noise (2ILV POp @ G= lOOOVN) and high CMR
(l06dB @ 60Hz).
DESIGN FEATURES AND USER BENEFITS
Isolated Power: Isolated power supply sections at the input and
output provide ± 15V dc @ SmA. Isolated power is load
regulated to 4%. This feature permits the AD295 to excite
floating signal conditioners, front-end buffer amplifiers and
remote transducers at the input and external circuitry at the
output. This eliminates the need for a separate dddc converter.
Input Amplifier: The uncommitted input amplifier allows the
user to configure the input as a buffer, inverter, subtractor or
differential amplifier to meet the application need.
Adjustable Gain: Gain can be selected at the input, output or
both. Thus, circuit response can be tailored to the user's
application. The AD295 provides the user with flexibility
for circuit optimization without requiring external active
components.
WHERE TO USE THE MODEL AD295
Industrial: The AD295 is designed for measuring signals in
harsh industrial environments. The AD295 provides high
accuracy with complete galvanic isolation and protection from
transients or where ground fault currents or high common-mode
voltages are present. The AD295 can be applied in process
controllers, current loop receivers, motor controls and weighing
systems.
Wide Operating Temperature: The AD295 is designed to
operate over the -40°C to + 100°C temperature range with
mted performance over - 25°C to + 85°C.
Instrumentation: In data acquisition systems the AD295
provides common-mode rejection for conditioning thermocouples,
strain gauges or other low-level signals where high performance
and system protection is required.
Leakage: The low coupling capacitance between input and
output yields a ground leakage current of less than 2ILA rms at
115V ac, 60Hz. The AD295 meets standards established by
UL STD 544.
Three-Port Isolation: Provides true galvanic isolation between
input, output and power supply ports. Eliminates the need for
power supply and output ports being returned through a
common ground.
ISOLA TION AMPLIFIERS 5-27
•
SPECIFICATIONS
(typical @
+25"1:, & Vs = + 15V unless oIII8IWise noted)
MODEL
ADZ9SA
GAIN
Range
Open Loop
IVNlolOOOVN
lOOdB
AccuracyG=lVN
ADZ9SB
AD29SC
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
±1.5%
+ 85"C)
vs Temperature ( - 2S"C to
G = lVIV to lOOVIV
\
± 6Oppmf'C max
Nonhneanty( + SV Swmg) G = IV-lOOVIV
+
INPUT VOLTAGE RATINGS
LmearDdferent:1alRange
Max Safe Dlfferentw Input
MaxCMV (Input to Output)
0.05% max
+0 025% max
+0.012% max
±10VmlD
± 15V
Conunuousacordc
ac,60Hz, I MInute Durabon
I
±2S00Vpeak
2500V rms
0600 (1524)
I
_MAX~
Max CMV (Input to Power Common/Output to Power Common)
Connnuous accr de
± 2000V peak
ae.60Hz, 1 Mmute Duranon
CMR. Input to Output60Hz, G = IVIV
Rs :s Uta Balanced Source Impedance
2000V rms
1. (~~~I
106dB
I03dB mm
Rs :s; lk Source Impedance Imbalance
•
Max LeakageCurrent, Input to Output
(f.v115Vac,60Hz
INPUT IMPEDANCE
DdIetenual
5 x IO'Ill133pF
1O'1l1120pF
Common Mode
INPUT BIAS CURRENT
lwtIal,(w +2S"C
AD295
SnAmax
vs Temperature(-25"Cto + 85°C)
J
±2nAmax
±SpArcmax
vs. Temperature ( -2S"Cto + 8SOC)
INPUT NOISE (Gwn = lOOOVN)
Voltage
o OlHz to 10Hz
2"Vp-p
I fJ,V rms
10Hz to 1kHz
Current
oOlHzto 10Hz
1000p-p
FREQUENCY RESPONSE
Small S.gnal ( - 3dB)
G = IVNlolooVN
G = lOOOVN
Full Power, 20V p-p Output
G = lVlVto lOOVN
G = lOOOVN
SlewRateG = IVNtolOPVN
Settlmg Time G = 1Vtv
(to ±O l%forlOVStep)
(to ±O. 1% for20V Step)
45kH,
600Hz
14kHz
200Hz
SS0fJ,S
PIN DESIGNATIONS
,
PIN
700....
2
(±3 ±
Irutial@ +25"C(AdJustableloZero)
Temperature ( - 2S"'C to
TOP VIEW
RECOMMENDED MATING SOCKET AC1220
o IV/....
OFFSETVOLTAGE,REFERREDTOINPUT
ci:N)mvmax
(±IO ±ci~k::.c (±3 ±::)~:C (±I 5 ±~~k~~
(±1 ~,:)"v/%
+ 85°C)
vs Supply
±
RATED OUTPUT
Voltage, 2kO Load
Output Impedance
Output Ripple (10Hz to 10kHz)
(10Hz 10 100kHz)
± IOVnun
21l(dclo 100Hz)
6mVp-p
4OmVp-p
ISOLATED POWER SUPPLIES' (VISOI & VIS02 )
Voltage
Accuracy
±1SVdc
±S%
Current2
Load RegulallOn (No Load 10 Full Losd)
Rlpple,IOOkHzBW
± SmA max
-4%
12mVp-p
POWER SUPPLY (+ Vs )
Voltage, Rated Performance
Voltage,OperatlDg
Current,Qwescent(Vs
With V1so Loaded
1
11
-2SpArCmax
INPUT DIFFERENCE CURRENT
Inltial,([v +2SoC
VS.
MAX
2JJArmsmax
+lSVdc±3%
+12Vdcto+16Vdc
= + ISV)
40mA
4SmA
TEMPERATURE RANGE
Rated Performance
OperallDg
-25°Cto +85"C
-4O"Cto +lOOOC
- 4O"C to + lOOOC
Storage
CASE DIMENSIONS
2.7"xO.88"xO 375'
NOTES
IV ISOl au::uracy and fCiUlatlOD 10%
*SpeclfiClltlOnS same as AD295A
2:t: IOmA can be 8UppJ!ed by VI'iOh IfVI~w IS not ullt'd
Speclficauons subJcct to change WIthout notice
5-28 ISOLATION AMPLIFIERS
3
•
'8
,.
17
20
FUNCTION
+15V(+VlSo,)
VI8o,COM
-15V(-VI80,)
NO CONNECTION
PIN
40
39
.8
37
38
+V.
2.
POWER COMMON
+ 15VI+VISQZI
2.
23
22
-15V(+VISQZI
~,
FUNCnoN
INPUT FEEDBACK
+ INPUT
-INPUT
INPUT COM
NO CONNECTION
OUTPUTCOMI
V1sozCOM
ALTER
OUTPUT FEEDBACK
OUTPUT
OUTPUT OFFSET TRIM
Understanding the Isolation Amplifier Performance
INTERCONNECTIONS AND SHIELDING TECHNIQUE
To preserve the high CMR performance of the AD295, care
must be taken to keep the capacitance balanced about the input
terminals. Use twisted shielded cable for the input signal to
reduce inductive and capacitive pick-up. During circuit layout
or interassembly connections, twisted wire pairs are recommended
for power input and signal output. For basic isolator connections,
see Figure 1. Capacitors CI-C5 are required in all applications
to achieve the low noise rating and provide adequate flltering of
the power supply.
the modulator. If the input signal of Al is zero, the triangle
wave remains symmetrical. If Al moves away from zero, the
triangle wave moves positive or negative becoming asymmetrical.
These modulated signals are converted to a pulsed waveform
and transferred to the output section via Tl. In the output
section the signals are demodulated and flltered. The output
amplifier A2 provides gain and additional flltering.
INTERELECTRODE CAPACITANCE AND TERMINAL
RATINGS
Capacitance: Interelectrode terminal capacitance arises from
stray coupling capacitance effects between the input terminals
and signal output terminals. Each are shunted by leakage resistance
values exceeding 50GO. Figure 3 illustrates the AD295's capacitance between terminals.
Terminal Ratings: CMV performance is given in both continuous
ae, or dc peak ratings. Continuous peak ratings apply from dc
up to the normal full power response frequency. Figure 3 illustrates
the AD295's ratings between terminals. Note that for the ± 2500V
rating between the input and output terminals to apply, the
AD295 must be used in a three port configuration. If the output
common is tied to the power common, the input to output
CMV rating is ± 2000V.
~=!~~:S~5OppmI"CMfTALRLMTYPE
4 CouT = 2wfI7!>110")FARADS-22OpF
2 ADJUSTMENTPOTENnOMETEftSARETENTURN,
100ppmr'C CERMETTVPE
3 CAPACITORS. C1-C5 ARE 2 2.."
5 c"...
211"FRt6 10kO INPUT PROTECT1ON RESISTOR REQUIRED
FOR GAINS LESS THAN 10
Figure 1. Basic Isolator Interconnection
THEORY OF OPERATION
The AD295 obtains its outstanding performance from a pulse
width modulation technique using transformer coupling. This
technique permits both signal and power transfer from input to
the output stage of the isolator. Additionally, this technique
provides higher noise immuuity and lower nonlinearity than
obtained from optically coupled or amplitude modulated transformer coupled techniques.
The three basic sections of the AD295 are shown in Figure 2.
The power section 80kHz oscillator signal is transferred to the
input and output sections via T2. The signal is then rectified
and flltered providing dc power for that section's circuitry and
for external application use. The input section consists of input
amplifier Al and the input modulator attenuator circuit. A
triangular waveform derived from the 80kHz oscillator is sent to
t-H"";;;i.-{,i91 g~Fr:~TTRIM
OUTPUT
L-______~~~~~25 ~~~~~
r----~i·l- ----..,
I
I
1
1
I
1
1
1
1
L _ --11--
II
1
-I L--II--l
33pf
33pf
Figure 3. Interelectrode Capacitance and Terminal Ratings
OFFSET AND GAIN ADJUSTMENT PROCEDURE
The calibration procedure, illustrated in Circuits I and 2, shows
the recommended techniques that can be used to minimize
output error. In this example, the output span is - IOV to
+IOV.
Offset Adjustment
1. Configure the AD295 as shown in Circuit 1. G = 1.
2. Apply EIN=OV dc and adjust Ro for Eo=O volts.
3. Configure the AD295 as shown in Circuit 2. G= 100.
4. Apply EIN=OV dc and adjust RI for Eo=O volts.
5. Repeat steps 1-4 if necessary.
Gain Adjust
6. Apply EIN= +O.IV dc adjust Ro for Eo= +IO.OOOV dc.
7. Apply EIN = -O.IV dc and measure the output error (see
Curve a.)
L.:...I....L..-L..J:O\ COMMON
AD295
i~mU-fl
-10
8
6
-4
-2
0
+2
+4
+6
+8
+10
OUTPUT VOLTAGE - Volts
Figure 2. Basic Block Diagram
ISOLA TlON AMPLIFIERS 5-29
5
8. Adjust Ro until the output error is one half that measured
in step 6 (see Curve b).
9. Apply EIN = +O.IV de and adjust Ro until the output error
is one half that measured in step 7 (see Curve c).
10. Repeat steps 6-9 if necessary.
Input to output gain greater than unity can be independently set
at the input, output, or both. For input gain ~nfiguration see
Figures 4b and 4c. Output gain configuration is shown in Figure
4d.
lourm.":F1
*R= 10k REQUIRED FOR e.>1V
b. Basic Gain Noninverting Configuration
-
-
o
~
E
Circuit 1. G= 1
-eo= (~) ..
___-(i
Apt10k
c. Input Gain Inverting Configuration
r;:;;-,
~
*R= 10k REQUIRED FOR e ..>1V
Circuit 2. G= 100
d. Output Gain Noninverting Configuration
SELECTING GAIN
The AD295 basic gain is unity from input to output. All input
signals are attenusted by 2.5 at the input modulator/attenuator
then amplified at the output (see Figure 2).
The AD295 contains both input and output amplifiers, the
gains of which can be set independently. Figure 4 illustrates the
basic gain configurations. Taking input gain helps dilute output
stage offset drift and is recommended where offset drift is to be
minimized since taking output gain multiplies output drift by
the gain taken. Output gain can be used for improved linearity
and frequency response at the expense of higher offset drift.
Figure 4a illustrates the basic unity gain configuration. With the
uncommitted input amplifier configured as a buffer and pins 22
and 23 of the output amplifier jumpered, eo=es.
Figure 4. Input/Output Gain Configurations
PERFORMANCE CHARACTERISTICS
Phase Shift vs. Frequency: The phase shift vs. frequency response, for the AD295 is shown in Figure 5.
...
T
7
300
.
1.
/
100
/
/
.-/
1k
10k
FREQUENCV - Hz
Figure 5. Typical AD295 - Phase Shift vs. Frequency
eo
-R=1Ok REQUIRED FOR e.>1V
+1&V
a. Basic Unity Gain Configuration
~o
ISOLA TION AMPLIFIERS
CMR vs. Frequency: Input-to-output CMR is dependent on
source impedance imbalance, input signal frequency and amplifier
gain. CMR is rated at 60Hz and lkO source impedance imbalance
at a gain of IVN. Figure 6 illustrates the CMR vs. frequency
for the AD295. CMR approaches 120dB at de with a source
impedance imbalance of lkO.
•
12
100
.
--
•. 02
~
1'---...
•
40
•
..
,
1.
'"'"
Figure 6. Typical AD295 - CMR vs. Frequency
Input Voltage Noise vs. Bandwidth: Voltage noise referred to
the input is dependent on gain and bandwidth. Figure 7 illustrates
the typical input noise in 11V peak-ta-peak in a 10Hz to 10kHz
frequency range.
6
7
5
4
,~
./
3
2/
G IN
~
....
,.,
"
FREOUENCY - Hz
)
1
.,
1
0.01
Figure 9. Typical AD295 - Gain Nonlinearity vs. Output Swing
Full Power Bandwidth vs. Gain: Figure 10 illustrates the full
power bandwidth vs. gain for the AD295. A 1.4kHz full power
response is possible with gain up to lOOVN.
•
10,00
:!!,
~ 1.00•
~
~
=10DOV/V
..
100
V
1
•
,.
•
10
100
1000
10,000
BANOW1DTH - Hz
Figure 7. Typical AD295 - Input Voltage Noise vs.
Bandwidth
Output Voltage Noise vs. Bandwidth: Voltage noise referred to
the output is dependent on gain, bandwidth, input and output
noise contributions. Figure 8 illustrates the typical output noise
in mV peak-to-peak in a 10Hz to 10kHz frequency range.
1.r---------,---------~--------~
,
~
~
...>
10,000
:!!,
~
i
~
E
0
100.
Figure 10. Typical AD295 - Full Power Bandwidth vs. Gain
Small Signal Bandwidth vs. Gain: Figure II illustrates the
small signal bandwidth vs. gain for the AD295. The small signal
response remains at 4.5kHz for gain up to lOOVN.
:l, •••
~
>
.
100
""
GIN VIV. GouT =1
1
~z
2.
1.
OUTPUT SWING - V/p-p
~
GOlJT =1VN
V
'\
~
i
.,
..
,
~
=>
1
,.
100
1000
Figure 11. Typical AD295 - Small Signal Bandwidth vs. Gain
0
.,
O.01-,~• .£:..--------,-J,00':---------IOOO~--------,•.J,00.
BANDWIDTH - Hz
Figure 8. Typical AD295 - Output Voltage Noise vs.
Bandwidth
Gain Nonlinearity vs. Output Swing: Linearity error is defmed
as the deviation of the output voltage from the best straight line
and is specified as % peak-to-peak of output voltage span, e.g.,
nonlinearity of model AD295A operating at an output span of
10V peak-to-peak(±5V)is ±O.05%or ±5mV. Figure 9 illustrates
the gain nonlinearity for output swing up to ± IOV (20V peak-topeak).
~
/
AD295A
...,
A0295B
~
ADZ95C
:I •• 1
Z
::l
~
VOUT= ±10V
.001
I.
100
1,000
Figure 12. Typical AD295 - Gain Nonlinearity vs. Gain
ISOLA TION AMPLIFIERS 5-31
•
Isolated Strain Gauge Using Front End of AD295
The AD295 can be used to condition and isolate differential
signal sources like those present with strain gauge measurements.
Figure 13 illustrates one possible conftguration for conditioning
a strain gauge. Amplifters Al and A2 are powered by the AD295's
input isolated power supply. This eliminates the need for a
separate dcldc converter and provides a completely floated differential input. Input gain is selected via Ro and determined by the
input gain formula.
Isolated Voltage-to-Current Loop Converter
Illustrated in Figure 15, the AD295 is used to convert a 0 to
+ lOY input sigual [0 a standard 4-to-20mA current. Here high
common-mode rejection and high common-mode voltage suppression are easily obtained with the AD295. The AD295 conditions the 0 to + lOY input signal and provides a proportional
voltage at the isolator's output. This output signal is converted
to a 4-to-20mA current, which in turn is applied to the loop
load R LOAD •
ADJUST TO 4mA
WITH OV IN ""'--- - - ' "
- EXCITATION
GAIN=1+~
Al/A2
576n
COM
INPUT AMPLIFIER IS
POWERED BY INPUT
FLOATING SUPPLY
= AOOP-07
1000
FOR 0 TO +10V IN
4-20mA OUT
lN4149
Figure 13. Isolated Strain Gauge Using Front End of
AD295
Isolated Temperature Measurement with Cold Junction
Compensation
The AD295 can be used to condition, isolate and provide cold
junction compensation of thermocouples in temperature measurement applications. With the circuit shown in Figure 14, the
AD590 must be thermally connected to the cold junction terminal
for an accurate temperature measurement of the terminals.
Using this circuit, accurate temperature measurements using the
industry's popular J type thermocouple can be made.
L---- :l:2500vPt< (tsltV", MAXI
Ro MAY BE MOUNTED ON AC1049 MOUNTING SOCKET USING STANDOFF PROVIDED
(USE % WATT. 5%, CARBON COMPOSITION TYPE, ALLEN BRADLEY RECOMMENDED)
NOTE 3 OUTPUT FilTER CAPACITOR, C SELECT TO RDLLDFF NOISE
AND OUTPUT RIPPLE Ie, SELECT C" 15pF fOR de TO 100Hz BANDWIDTH}
Figure 1. Basic Isolator Interconnection
5-34 ISOLA TION AMPLIFIERS
T
78dB
INPUT DIFFERENCE CURRENT
Initial, @ +2S OC
vs. Temperature (0 to +70 oC)
FREQUENCY RESPONSE
Small Signal, -3dB, G = 1VN to iOVN
Slew Rate
Full Power, 10V p-p Output
Gam = 1V/V
Gam = 10V/V
Recovery Time, to ±lOO.uV after Application
of ±6S00Vpk Dlfferentlallnput Pulse
6
>v,7
1---'51138"0"---1
0.20T0025
2S00V nns
±2S00Vp k max
±SOOOVpk max
±2S00Vpk max
108 nl170pF
300kn
Sxl0'o nll20pF
INPUT NOISE
Voltage, G = iOVN
O.OSHz to 100Hz
10Hz to 1kHz
Current
O.OSHz to 100Hz
l00kn
±3%
INPUT IMPEDANCE
Differential
Overload
Common Mode
I
OUTUNE DIMENSIONS
2M}
MODEL
GAIN (NON·INVERTING)
Range (sOkSl Load)
Formula
Understanding the Isolation Amplifier Performance
THEORY OF OPERATION
The remarkable performance of model 284J is derived from
the carrier isolation technique which is used to transfer both
signal and power between the amplifier's guarded input stage
and the rest of the circuitry. The block diagram for model 284J
is shown in Figure 2 below.
The 320kil input protection resistor limits the differential input current during periods of input amplifier saturation and
also limits the differential fault current to approximately 3Sj.lA
in case the preamplifier fails.
The bipolar input preamplifier operates single-ended (noninverting). Only a difference bias current flows with zero net
bias current. A third wire return path for input bias current is
not required. Gain can be set from lV/V to lOVIV by changing the gain resistor, Ri. To preserve high CMR, the gain resistor
must be guarded. Best performance is achieved by shorting
terminal 2 to terminal 1 and operating model 284J at a gain of
lOV/V.
For powering floating input circuitry such as buffer amplifiers,
instrumentation amplifiers, calibration signals and transducers,
dual isolated power is provided. High CMV isolation is achieved
by the low-leakage transformer coupling between the input
preamplifier, modulator section and the output circuitry. Only
the 20pF leakage capacitance between the floating guarded input section and the rest of the circuitry keeps the CMR from
being infinite.
Terminal Ratings: CMV performance is given in both peak
pulse and continuous ac or dc peak ratings. Pulse ratings are
intended to support defibrillator and other transient voltages.
Continuous peak ratings apply from dc up to the normal full
power response frequencies. Figure 4 and Table 1 illustrate
model 284J'.s ratings between terminals.
RATING
REMARKS
±6500VpK (lOms)
±240VRMS
±2500VpK (lOms) Rc = 0
±5000VPK (lOms) RG =:: 510kn
±2500VPK
±50VPK
Withstand Voltage, Deflbnllator
Withstand Voltage, Steady State
TranSient
Iso\atlOn, Defibrillator
Isolation, Steady State
Isolation, de
IsolatIOn Impedance
Input Fault Luna, DC to 60kHz
SYMBOL
VI
VI
V2
V2
V2
V3
ZI
I
(pulse)
(cont)
(pulse)
(pulse)
(cont )
(cont)
50kMQII2opF
35pA nus
Table 1. Isolation Ratings Between Terminals
Leakage Current Limits: The low coupling capacitance between
inputs and output yields a ground leakage current of less than
2.0j.lA rms at l1SV ac, 60Hz (or O.02j.1AIV ac). As shown in
Figure S, the transformer coupled modulator signal, through
stray coupling, also creates an internally generated leakage current of about Sj.lA rms@ 60kHz. Line frequency leakage current levels are unaffected by the power on or off condition of
model 284J.
For medical applications, model 284J is designed to improve
on patient safety current limits proposed by F.D.A., U.L.,
A.A.M.I. and other regulatory agencies. (e.g. model 284J complies with leakage requirements for the Underwriters Laboratory STANDARD FOR SAFETY, MEDICAL AND DENTAL
EQUIPMENT as established under ULS44 for type A and B
patient connected equipment - reference Leakage Current,
paragraph 27.5).
In patient monitoring equipment, such as ECG recorders,
model 284J will provide adequate isolation without exposing
the patient to potentially lethal microshock hazards. Using
passive components for input protection, this design limits
input fault currents even under amplifier failure conditions.
TEST CIRCUITS 80 MAX CURRENT LIMITS FOR
ANY SWITCH CLOSURE COMBINATION
E~
r---~r--t--
Figure 2. Block Diagram - Model 284J
INTERELECTRODE CAPACITANCE, TERMINAL RATINGS
AND LEAKAGE CURRENTS LIMITS
Capacitance: Interelectrode terminal capacitance arising from
stray coupling capacitance effects between the inpu t terminals
and the signal output terminals are each shunted by leakage
resistance values exceeding SOkMil. Figure 3 illustrates the
CMR ratings at 60Hz and Skil source imbalance between signal input/output terminals, along with their respective capacitance.
rms
~
~
1M
I_
5000.
284J
~
_'-.J
,--r--t-~-1
.....
"5V
INTERNALLY
GENERATED
TEST 01
+15V
LINE INDUCED
TEST 1111
·
10mA'T"-----,----,-,---,-----.---,----,
4
lm:~+--~~-+--I_-J~=+==1
•
4
101J~:+---=~--!'-----i--+--t--l
4
·,
'"A+--~-~+---+--IH~~~_+
4
o lIJA1~O-.....,~-'-~-----,;;t:----;:::~-7.;;--~
·WHEN GUARD TIED TO INPUT COMMON MODE SOURCE
Figure 3. Model 284.1
Terminal Capacitance
and CMR Ratings
FREQUENCV-HI:
Figure 4. ,Model 284.1
Terminal Ratings
Figure 5. Model 284.1 Leakage Current Performance from Line
Induced and Internally Generated (Modulator) Operating
Conditions
ISOLA TlON AMPLIFIERS 5-35
PERFORMANCE CHARACfERISTICS
Common Mode Rejection: Input-to-output CMR is dependent
on source impedance imbalance, signal frequency and amplifier gain. CMR is rated at llSV ac, 60Hz and SkG imbalance
at a gain of lOVN. Figure 6 illustrates CMR performance as a
function of signal frequency. CMR approaches 146dB at dc
with source imbalances as high as SkG. As gain is decreased,
CMR is reduced. At a gain of 1V/V, CMR is typically 6dB
lower than at a gain of lOVN.
For lowest noise performance, a low pass filter at the output
should be used to selectively roR-off noise, output ripple and
undesired signal frequencies beyond the bandwidth of interest
(see note 3, Figure 1).
Input Offset Voltage Drift, Total input voltage drift is composed of two sources, input and output stage drifts and is gain
dependent. The curve of Figure 9 illustrates the total input
voltage drift over the gain range of 1 to lOV/V.
200
'40
Ii
........
GUARANTEED CMR. G = 10VIV
"OdBMIN08OHz
11 r-....
.-~
. .
_
•
~III''''
r-
"
LOIN
ob~
I
"~
_
G
'"
WITH 5kU SOURCE IMBALANCE
i
I
10'1/11
"- r-..
..........
r-..
l1WAC
I IIII I II
0
'TEST CIRCUIT
-SIca EACH RESiSTOR
CMR VALUE GIVEN FOR WORST CASE RESISTOR COMBINATION
'00
I.
'000
FREQUENCY - Hz
667
1
9
I.
GAIN -V/V
Figure 6. Common Mode Rejection
VB.
Frequency
Figure 7 illustrates the effect of source imbalance on CMR performance at 60Hz and Gain =lOVN. CMR is typically 120dB
at 60Hz and a balanced source. CMR is maintained greater than
80dB for source imbalances up to 1OOkG.
'40
GUARANTEED CMR iii G"
10vN
1lOdS MIN. 60Hz AND SkU
SOURCE IMPEDANCE IMBALANCE
"".. .
-~
'GAlli
_
'lon.
&11*i'
_
"
10
,.
Gain Nonlinearity: Linearity error is defined as the peak deviation of the output voltage from the best straight line and is
specified as a % of peak-to-peak output voltage span; e.g. nonlinearity of model 284J operating at an output span of lOV
pk-pk (±SV) is ±O.OS% or ±SmV. In applying model 284J,
highest accuracy is achieved by adjusrment of gain and offset
voltage to minimize the peak error over the operating output
voltage span. A calibration technique illustrating how to minimize output error is shown below. In this example, model 284J
is operating over an output span of +SV to -SV and a gain of
SV/V.
OIJT
I~G"'''.MlVIV
...
I
rI
1(1
Figure 9. Input Offset Voltage Drift VB. Gain
j
III I II
wrEST CIRCUIT - EACH RESISTOR ADJlISTED o.n TO l00kn
CMR VALUE GIVEN FOR WORST CASE RESISTOR COMBINATION
100
lk
SOURCE IMPEDANCE IMBALANCE -
10k
n
'OOk
Figure 7. Common Mode Rejection VB. Source Impedance
Imbalance
-6
-4
-3
-2
-1
+1
+2
+3
+4
+5
OUTPUT VOLTAGE - Vofts
Input Voltage Noise: Voltage noise, referred to input, is de:pendent on gain and bandwidth as illustrated in Figure 8. RMS
voltage noise is shown in a bandwidth from O.OSHz to the frequency shown on the horizontal axis. The noise in a bandwidth from O.OSHz to 100Hz is 8pV pk-pk at a gain of lOV N.
This value is derived by multiplying the rms value at f = 100Hz
shown in Figure 8 (l.2pV rms) by 6.6.
+15V
r--.------------~~
Figure 10. Gain and Offset Adjustment
Figure 8. Input Voltage Noise VB. Bandwidth
5-36 ISOLA TION AMPLIFIERS
Applying the Isolation Amplifier
GROUNDING PRACTICES
The more common sources of electrical noise arise from ground
loops, electrostatic coupling and electromagnetic pickup. The
guidelines listed below pertain to guarding low level, millivolt
signals in hostile environments such as current shunt signals in
"heavy industrial" plants.
Guidelines:
• Use twisted shielded cable to reduce inductive and capacitive pickup.
• Drive the transducer cable shield, S, with the common mode
signal source, EG, to reduce the effective cable capacitance
as shown in Figure 11 below. This is accomplished by connecting the shield point S, as close as possible to the transducer signal low point B. This may not always be possible.
In some cases the shield may be separated from signal low
by a portion of the medium being measured (e.g. pressure
transducer). This will cause a common mode signal, EM, to
be generated by the medium between the shield and the
signal low. The 78dB CMR capability of model 284J between
the input terminals (HI IN and LO IN) and GUARD, will
work to suppress the common mode signal, EM'
• To avoid ground loops and excessive hum, signal low, B, or
the transducer cable shield, S, should never be grounded at
more than one point.
• Dress unshielded leads short at the connection terminals and
reduce the area formed by these leads to minimize inductive
pickup.
APPLICATIONS IN INDUSTRIAL MEASUREMENT AND
CONTROL SYSTEMS
Remote Sensor Interface: In chemical, nuclear and metal processing industries, model 284J can be applied to measure and
control off-ground millivolt signals in the presence of
±2S00V dc CMV signals. In interface applications such as pH
control systems of on-line process measurement systems such
as pollution monitoring, model 284J offers complete galvanic
isolation to eliminate troublesome ground loop problems. Isolated power outputs and adjustable gain add to the application
flexibility of this model.
Figure 13 illustrates how model 284J can be combined with a
low drift, 1J,LV/oC max, front-end amplifier, model ADS17K,
to interface low level transducer signals. Model 284}'s isolated
±8.SV dc power and front-end guard eliminate ground loops
and preserve high CMR (114dB @ 60Hz).
00l.u F
r-~~-+---~-o~v
PC CARD SHIELD
TRANSDUCER
TRANSOUCER
CABLE
r.1- - --,
I
-15V
I
POWER
COM
Figure 13. Input Signal Conditioning Using Isolated Power for
Transducer Buffer Amplifier
MEDIUM
Instrumentation Amplifier: Model 284J provides a floating
guarded input stage capable of directly accepting isolated differential signals. The non-inverting, single-ended input stage offers
simple two wire interconnection with floating input signals.
....-
CO~~~:A~~DE ' -_ _ _---'
TR.t>NSOUCER
GROUND
GROUND COMMON MODE
VOLTAGE
SYSTEM
GROUNO
Figure 11. Transducer- Amplifier Interconnection
Isolated Power and Output Voltage Swing: Model 284J offers
a floating power supply providing ±8.SV dc outputs with
±SmA output current rating. As shown in Figure 12, the minimum voltage output for ±V1SO ' as well as the maximum load
capability, is dependent on the input power supply, +Vs. Figure 12 also illustrates the typical output voltage range as both
input supply, +Vs' and the isolated supply loads, ±I L , are
varied. At ±SmA isolated load and Vs = +lSV dc, model 284J
can provide an output voltage swing of ±7.SV.
I I
~r,~~t;o~~P-- b::
VtSO
"\,..
+14
+15
-IN 2OOkll:
PROCEOURE
~'N~C~O.~_~~~7f+r
~"~
+9
+10
+11
+12
+13
POWER SUPPLY \Vs) -Volts
::
'S" C., T".
tV PKPK
~5OI-----AHO"
-
I~Dg/J:E:L~TIffiYW!ffitr:~EEOEl
GUARDING TECHNIQUES
To preserve the high CMR performance of model 286, care
must be taken to keep the capacitance balanced about the input terminals. A shield should be provided on the printed circuit board under model 286 as illustrated in the outline drawing
above (screened area). The GUARD (pin 6) must be connected
to this shield. This shield is provided with the mounting socket,
model ACIOS4 (solder feedthrough wire to the socket guard
pin and copper foil surface.) A recommended guarding technique using model ACIOS4 is illustrated in Figure 1.
Best CMR performance will be achieved by using twisted,
shielded cable to reduce inductive and capacitive pickup. To
reduce effective cable capacitance, cable shield should be connected to the common mode signal source by connecting the
shield as close as possible to signal low as shown in Figure 1.
LOAD
>50k!~
+15Vdc
+(8V dc to 16V dc)
+13mA
TEMPERATURE RANGE
Rated Performance
0 to +70°C
Storage _ _ _ _ _ _ _ _ _ _ _ _ _-_5S."o_C_tO--::+8_5_o_C--::_ _ __
CASE DIMENSIONS
""m"
I
1.5" xIS" x 0.62"
I G,un temperature dnft IS specIfied as a percentage of output Signal level
:Gam nonlinearity IS specified as a percentage of output sJgnai span.
'Recommended power supply, ADl model9Q4, ±15V@±50mAoutput.
·Speclflcatlons are for model 286} when dnven by ADI model 281 oscillator Circuit (see Figure 12)
Specifications subject to change Without notice
POWER GROUND ";'"
NOTE 1
~~~NG~~~I~Tt~?V ,,[~:~i~fR"~I~A~~T6~E~LM TYPE
FOR GAIN = 100VIV, SHORT TERMINAL 2 TO TERMINAL 1
FOR GAINS FROM lVIV TO l00VIV
tookl'
GAIN ~ 1 + ·ik!~A;lkl;-1
NOTE 2 OPTIONAL GUARD RfSISTOR,..., REQUIRED ONLY FOR CMV" _2500V••
RG MAY SE CONVENIENTLY MOUNTED ON ACt054 MOUNTING SOCKET USING
THE STANDOFF PROVIDED 11\;1 USE 114 WATT 5% CARBON COMPOSITION TYPE
(ALLEN BRADLEY RECOM"'ENO~DI
NOTE 3 OUTPUT FILTER CAPACITOR C SELECT TO ROLLOH NOISE AND OUTPUT
RIPPLE leg SELECT C-t 5~F FOR de TO 100H,BANDWIOTH)
,
FI-3dBI~i1T
Figure 1. Basic Isolator Interconnection
5-40 ISOLA TlON AMPLIFIERS
Understanding the Isolation Amplifier Performance
THEORY OF OPERATION
The remarkable performance of model 286J is derived from
the carrier isolation technique which is used to transfer both
signal and power between the amplifier's guarded input stage
and the rest of the circuitry. The block diagram for model 286J
is shown in Figure 2 below.
The 320kn input protection resistor limits the differential input current during periods of input amplifier saturation and
also limits the differential fault current to approximately
50f.lA in case the preamplifier fails.
The bipolar input preamplifier operates single-ended (noninverting). Only a difference bias current flows with zero net
bias current. A third wire return path for input bias current
is not required. Gain can be set from 1VIV to 100V/V by
changing the gain resistor, Ri. To preserve high CMR, the gain
resistor must be guarded. Best performance is achieved by
shorting terminal 2 to terminal 1 and operating model 286J at
again of 100VIV.
F or powering floating input circuitry such as buffer amplifiers,
instrumentation amplifiers, calibration signals and transducers,
dual isolated power is provided. High CMV isolation is achieved
by the low-leakage transformer coupling between the input preamplifier, modulator section and the output circuitry.
OUTPUT
•'1
1
•
"WHI"N GUARD TIED TO INPUT COMMON MODE SOURCE
Figure 5. Model286.1
Terminal Ratings
Figure 4. Model286.1
Terminal Capacitance
and CMR Ratings
Terminal Ratings: CMV performance is given in both peak
pulse and continuous ac or dc peak ratings. Pulse ratings are
intended to support defibrillator and other transient voltages.
Continuous peak ratings apply from dc up to the normal full
power response frequencies. Figure 5 and Table 1 illustrate
model 286J ratings between terminals .
100kHZ
OSC
INPUT
POWE.
L----(l). COM
GAIN - 1 + lkn :OO~~m
INTERELECTRODE CAPACITANCE, TERMINAL RATINGS
AND LEAKAGE CURRENTS LIMITS
Capacitance: Interelectrode terminal capacitance arising from
stray coupling capacitance effects between the input terminals
and the signal output terminals are each shunted by leakage
resistance values exceeding 50kMn. Figure 4 illustrates the
CMR ratings at 60Hz and 5kn source imbalance between signal input/output terminals, along with their respective capacitance.
{WN TO l00v/V}
Figure 2. Block Diagram - Model 286.1
OPTIONAL TRIM ADJUSTMENTS
Model 286J can be applied directly to achieve rated performance as shown in Figure 1, on previous page. Additional trim
adjustment capability for bandwidth, output offset voltage and
gain (for gains greater than 1OOVIV) is easily provided as
shown in Figure 3 (below). The OUT and TRIM terminals can
be floated with respect to PWR COM up to ±50V pk, max offering three-port isolation.
The TRIM terminal (pin 11) must be connected to the PWR
COM terminal (pin 8) when not used to adjust the output offset voltage. A O.1~F capacitor from pin 11 to PWR COM is
recommended whenever the TRIM terminal is used.
a;>---!--<>-..,E.
;"2kn
Figure 3. Optional Connections: Offset Voltage Trim Adjust,
Bandwidth (-3dB) Rolloff and Gain Adjust (G> 100V!V)
SYMBOL
RATING
REMARKS
VI (pul.. )
VI (cont.)
V2 (pulse)
V2 (pulse)
V2 (cont.)
V3 (cont.)
Zl
±6S00VPK (10m.)
±240VRMS
±2S00VPK (lOms) Rc • 0
±SOOOVPK (10m.) RG = SlOill
±2500VPK
Withstand Voltage, Oeflbnllator
Withstand Voltage. Steady State
±SOVPK
SOkMnll2OpF
SOJtA, rms
TranSient
Isolation, Deflbnllator
Isolation, Steady State
Isolauon, de
Isolation Impedance
Input Fault Limit, de to 200kHz
Table 1. Isolation Ratings Between Terminals
Leakage Current Limits: The low coupling capacitance between
inputs and output yields a ground leakage current of less than
2.5f.lA rms at 115V ac, 60Hz (or O.02jJ.A/V ac). As shown in Figure 6, the transformer coupled modulator signal, through stray
coupling, also creates an internally generated leakage current
of about 5jJ.A rms @ 100kHz. Line frequency leakage current
levels are unaffected by the power on or off condition' of
model 286J.
For medical applications, model 286J is designed to improve
on patient safety current limits proposed by F.D.A., U.L.,
A.A.M.I. and other regulatory agencies (e.g., model 286J complies with leakage requirements for the Underwriters Laboratory STANDARD FOR SAFETY, MEDICAL AND DENTAL
EQUIPMENT as established under UL544 for type A and B
patient connected equipment - reference Leakage Current,
paragraph 27.5).
In patient monitoring equipment, such as ECG recorders,
model 286J will provide adequate isolation without exposing
the patient to potentially lethal microshock hazards. Using
passive components for input protection, this design limits
input fault currents even under amplifier failure conditions.
ISOLATION AMPLIFIERS 5-41
•
TEST CiRCUITS .. MAX CURRENT LIMITS FOR
ANY SWITCH CLOSURE COMBINATION
Gain Nonlinearity. Linearity error is defined as the deviation
of the output voltage from the best straight line and is specified as a % of peak-to-peak output voltage span; e.g., nonlinearity of model 286J operating at an output span of 10V pk-pk
(±5V) is ±O.05% or ±SmV. Figure 9 illustrates gain nonlinearity
for any output span to 20V pk-pk (±10V).
~'''V
~6""-'M-'I-",,-o---""
r-'"M:
r- . , "."
r-,,""
hi
,
o
r-
III
-
~,
,...-
Iij
"
(5
z
""!:;"'
0
-TEST CIRCUIT - 5kn EACH RESISTOR
CMR VALUE GIVEN FOR WORST CASE RESISTOR COMBINATiON
1.0
,...-
...>
~
-
GUARANTEED CMR@lG"l00v1V
nOdB MIN @160Hz AND 5Icn
IMPEDVCE IMBALANCE
~
~CE
GAIN" 10vN
G~IN~ L~
80
- I-
L. -
.
l-
~
00'
An
SlOld'
I
"
6
I
I
10
1
100
11
Figure 10. Input Voltage Noise vs. Bandwidth
Input Offset Voltage Drift: Total input drift is composed of
two sources, input and output stage drifts and is gain dependent. The curve of Figure 11 illustrates total input drift over the
gain range of 1 to lOOV/V.
TRIM
1
,
I
'00
SOURCE IMPEDANCE IMBALANCE -
,
n
Figure 8. Common Mode Rejection vs. Source Impedance
Imbalance
5-42 ISOLA TION AMPLIFIERS
1000
BANDWIDTH (-3dBJ - Hz
'000
-TEST CIRCUIT - EACH RESISTOR ADJUSTED on TO l00kf!
CMR VALUE GiVEN FOR WORST CASE RESISTOR COMBINATION
10
10I.1EL
"
.~
•
~
~~
I "
~
~'
~'T"Tcr.c~or
01
140
I2O,IIV PK·PK
GLUooVN1;;o>
Figure 7. Common Mode Rejection vs. Frequency
Figure 8 illustrates the effect of source imbalance on CMR performance at 60Hz at gains of IV/V, lOY/V, and lOOV/V.
CMR is typically l40dB at 60Hz and a balanced source. CMR
is maintained greater than 80dB for source imbalances up
to lOOl 16
Isolators
025 (6 35) MAX
t
-1l----002(52)OIA
-LEAVE TERMINAl60PEN, WHEN POWER 18APPliED TO TERMINAL 7
Model 281 oscillator is capable of driving up to 16 model
286]'s as shown in Figure 14. An additional model 281 may
be driven in a slave-mode, as shown in Figure 15, to expand
the total system channels from 16 to 32. By adding additional
model 281 's in this manner, systems of over 1000 channels
may be easily configured.
(124)
IlffiH!-IJ80TlOM VIEW
WEIGHT 10GRAMS
I I
~
t-01(254)GRlD
PIN TERMINAL IDENTIFICATION
1
POWE R COMMON
5
SYNC OUTPUT
2
WoUTPUT
6
+Vs HIGH RANGE +114 to 28)Vdo
3
I/> OUTPUT
7
+Vs LOWRANGE+(8to,4)V""
4
SYNC INPUT
MATING SOCKET, CINCH #16 DIP OR EQUIVALENT
GUIDELINES ON EFFECTIVE SHIELDING &
GROUNDING PRACTICES
• Use twisted shielded cable to reduce inductive and capacitive pickup.
• Drive the transducer cable shield, S, with the common mode
signal source, EG , to reduce the effective cable capacitance
as shown in Figure 16!. This is accomplished by connecting the shield point S, as close as possible to the transducer signal low point B. This may not always be possible.
In some cases the shield may be separated from signal low
by a portion of the medium being measured (e.g. pressure
transducer). This will cause a common mode signal, EM' to
be generated by the medium between the shield and the signallow. The 78dB CMR capability of model 286J between
the input terminals (HI IN and LO IN) and GUARD, will
work to suppress the common mode signal, EM'
• Dress unshielded leads short at the connection terminals
and reduce the area formed by these leads to minimize inductive pickup.
ISOLA TlON AMPLIFIERS ~43
•
isolation to eliminate troublesome ground loop problems.
Isolated power outpu ts and adjustable gain add to the application flexibility of this model.
TRANSDUCER
Figure 18 illustrates how model 286J can be combined with a
low drift, 1/lVtC max, front-end amplifier, model AD510K,
to interface low level transducer signals. Model 286}'s isolated
±15V dc power and front-end guard eliminate ground loops
and preserve high CMR (HOdB min @ 60Hz).
MEOIUM;"~
COMMON
MODE
VOLTAGE
TRPNSOUCER
GROUND
GROUND COMMON MODE
VOLTAGE
SYSTEM
GROUND
Figure 16. Transducer - Amplifier Interface
GAIN AND OFFSET TRIM PROCEDURE
In applying the isolation amplifier, highest accuracy is achieved
by adjustment of gain and offset voltage to minimize the peak
error encountered over the selected output voltage span. The
following procedure illustrates a calibration technique which
can be used to minimize output error. In this example, the
output span is +5V to -SV and operation at Gain = 10V/V
is desired.
eo = 0 volts.
2. ApplyelN = +O.500V dc and adjust Rc for eo = +5.000V dc.
1. Apply eIN = 0 volts and adjust Ro for
3. ApplyeIN =-D.500V dc and measure the output error
(see curve a).
4. Adjust RG until the output error is one half that measured
in step 3 (see curve b).
S. Apply +O.SOOV dc and adjust Ro until the output error is
one half that measured in step 4 (see curve c).
-6
-4
-3
-2
-1
+1
+2
+3
+4
+5
OUTPUT VOLTAGE - Vol~
~
POWER
COM
Figure 18. Input Signal Conditioning Using Isolated Power for
Transducer Buffer Amplifier
Current Loop Receiver: Model 286J can be applied to measure·
ment of analog quantities transmitted via 4-20mA current
loops over substantial distances through harsh environments.
Figure 19 shows an application of model 286J as a current
loop receiver. A 250 resistor converts the 4-2OmA current
input from a remote loop to a 100-500mV differential voltage
input, which the 286J amplifies, isolates, and translates to a
o to +5V output level at local system ground.
Among the most-helpful characteristics of the 286J in this kind
of measurement are the high common-mode rejection (HOdB
minimum at 60Hz with 5kO source unbalance) and the high
common-mode rating (±2500 volts dc). The former means low
noise pickup; the latter means excellent isolation and protection against large transients. The high common-mode rejection,
permitting relatively low input voltage to be used (O.4V span.
in this case), permits the use of a low current-metering resistance, which in turn results in low compliance-voltage loading
on the current loop, and therefore permits insertion into existing loops without encountering overrange problems. The gain
of 12.5 provides a substantial output span, and the floating output permits biasing to a 0 to 5V range.
4-2OmA
CURRENT
LOOP
Figure 17. Gain and Offset Adjustment
25n
MEASURING
RESISTOR
)
ZERO ADJUST
ADJUST FOR
~..cl;~V WHEN
G=126VN
0'0""----,
19
I
20kll
APPLICATIONS IN INDUSTRIAL MEASUREMENT AND
CONTROL SYSTEMS
Remote Sensor Interface: In chemical, nuclear and metal processing industries, model 286J can be applied to measure and
control off-ground millivolt signals in the presence of
,±2500V de CMV signals. In interface applications such as pH
control systems or on-line process measurement systems such
as pollution monitoring, model 286J offers complete galvanic
5-44 ISOLATION AMPLIFIERS
10k"
01pF
""""
-"""E o
f ~~"
~15V
Figure 19. Isolated Analog Interface; 4 to 20mA is Converted
to 0 to +5Vat the Output, with Up to ±2500V of Isolation
~ANALOG
WDEVICES
Precision, Wide Bandwidth,
Synchronized Isolation Amplifier
Model 289 I
FEATURES
Low Nonlinearity: ±O.012% max (289L)
Frequency Response: (-3dB) de to 20kHz
(Full Power) de to 5kHz
Gain Adjustable 1 to 100VN, Single Resistor
3-Port Isolation: ±2500V CMV Isolation Input/Output
Low Gain Drift: ±O.oo5%fC max
Floating Power Output: ±15V @ ±5mA
120dB CMR at 60Hz: Fully Shielded Input Stage
Meets UL Std. 544 Leekage: 2IAA rms max, @ 115V ac, 60Hz
MODEL 289 FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
Multi·Channel Data Acquisition Systems
Current Shunt Measurements
Process Signal Isolator
High Voltage Instrumentation Amplifier
SCR Motor Control
GENERAL DESCRIPTION
Model 289 is a wideband, accurate, low cost isolation amplifier designed for instrumentation and industrial applications.
Three accuracy selections are available offering guaranteed
gain nonlinearity error at lOV POp output: ±O.Ol2% max
(289L), ±O.025% max (289K), ±O.05% max (289]). All versions of the 289 provide a small signal frequency response
from dc to 20kHz (-3dB) and a large signal response from dc
to 5kHz (full power) at a gain of 1VN. This new design offers
true 3-port isolation, ±2500V dc between inputs and outputs
(or power inputs), as well as 240V rms between power supply
inputs and signal outputs. Using carrier modulation techniques with transformer isolation, model 289 interrupts
ground loops and leakage paths and minimizes the effect of
high voltage transients: It provides l20dB Common Mode
Rejection between input and output common. The high CMV
and CMR ratings of the model 289 facilitate accurate measurements in the presence of noisy electrical equipment such as
motors and relays.
WHERE TO USE THE MODEL 289
The model 289 is designed to interface single and multichannel
data acquisition systems with dc sensors such as thermocouples, strain gauges and other low level signals in harsh industrial environments. Providing high accuracy with complete
galvanic isolation, and protection from line transients of fault
voltages, model 289's performance is suitable for applications
such as process controllers, current loop receivers, weighing
systems, high CMV instrumentation and computer interface systems.
Use the model 289 when data must be acquired from floating
transducers in computerized process control systems. The
photograph above shows a typical multichannel application
allowing potential differences or interrupting ground loops,
among transducers, or between transducers and local ground.
DESIGN FEATURES AND USER BENEFITS
Isolated Power: The floating power supply section provides
isolated ±l 5V outputs @ ±5mA. Isolated power is regulated to
within ±5%. This fearure permits model 289 to excite floating
signal conditioners, front-end buffer amplifiers and remote
transducers such as thermistors or bridges, eliminating the need
for a separate isolated dc/dc converter.
Adjustable Gain: A single external resistor adjusts the model
289's gain from 1VN to lOOV N for applications in high and
low level transducer interfacing.
Synchronized: The model 289 provides a synchronization
terminal for use in multichannel applications. Connecting the
synchronization terminals of model 289s synchronizes their
internal oscillators, thereby eliminating the problem of oscillator "beat frequency" interference that sometimes occurs
when isolation amplifiers are closely mounted.
Internal Voltage Regulator: Improves power supply rejection
and helps prevent carrier oscillator spikes from being broadcast via the isolator power terminal to the rest of the system.
Buffered Output: Prevents gain errors when an isolation amplifier is followed by a resistive load of low impedance. Model
289 can drive a 2kn load.
Three-Port Isolation: Provides true galvanic isolation between
input, output and power supply ports. Eliminates need for
power supply and output ports being returned through a common terminal.
Reliability: Model 289 is conservatively designed to be capable
of reliable operation in harsh environments. Model 289 has. a
calculated MTBF of 271,835 hours. In addition, the model
289 meets UL Std. 544 leakage, 21lA rms @ 115V ac, 60Hz.
ISOLA TION AMPLIFIERS 5-45
SPECIFICATIONS
(typical @
+2ft and Vs
= ± 14.4V to +25V de unless otherwise noted)
289K
289J
Model
r---
1 to lOOVN
~~~!fu)
Formula
G= I +
Deviation from Formula
VS Temperature (0 to +70 0 C)1
Nonbneanty. (±SV Swmg)2,3
±1.S% max
ISppmtc typ (SOppmtc max)
to 025% max
±O.012% max
±o 05%'max
INPUT VOLTAGE RATINGS
Linear Differential Range (G = IV/V)
Max Safe Dlfferentlallnpur
Continuous
2.02 (6118) MAX----1
I Mmute
-,
0.15
(18.961
MODEL 289
MAX
±10Vmm
1...
t20Vrms
240Vrms
""LQ.20 TO 0.26
ISTOUI
~
'0.04 (1 02) DIA
Max CMV (Inputs to Outputs)
Contmuous ac or de
ac, 60HL,,1 Minute Duration
CMR, Inputs to Outputs 60Hz
Rs ~ 1kn. Balanced Source Impedance
RS '" lkSl, HI IN Lead Only
Max Leakage Current, Input to Output (!)
115V cms, 60Hz ae
±2S00V peak max
2S00V nns
120dS
l04dB mm
2JJ.A rms max
INPUT IMPEDANCE
Differential
Overload
Common Mode
l3pFIlIO'n
lOOkn
20pFliS X 10Wn
INPUT DIFFERENCE CURRENT
Imttal@+2Soc
vs. Temperature (0 to 70°C)
10nA (75nA max)
o lSnA/C
INPUT NOISE (GAIN = lOOVN)
Voltage
o 05Hz to 100Hz
10Hz to 1kHz
Current
0.05Hz to 100Hz
SHIELDED MATING SOCKET
AC1214
.LI
8~Vp·p
3IJVrms
0.08
'2.031
27 (68.68) REF - - - -.....J.1 MAX
TF'
3pArms
FREQUENCY RESPONSE
Small Slgnal-3dB
G=IVN
Go 100V/V
Full Power, 10V pop Output
G=IV/V
G= IOOVI\'
Full Power, lOV pop Output
GolVN
G= IOOV/V
Slew Rate
Setthng Tlme4 ±O.OS%, ±lOV Step
r2~
vs Supply Voltage (+lSV to +20V change)
ISOLATED POWER SUPPLY
Voltage
Accuracy
CUrrent
Regulation No Load to Full Load
Ripple, O.lMHz BandWldth, No Load
Full Load
POWER SUPPLY, SINGLE POLARITY'
Voltage, Rated Performance
Voltage, Operating
Current, Qulcscent (@Vs = +lSV)
TEMPERATURE RANGE
Rated Performance
Operanng
Storage
23kH,
23kHz
3 -ViSa
ft SYNC 8
GAIN
,LOOUT 9
400/JS
6 HI IN
HI OUT 10
4
±~mvmax
±IS ± l~O max
±2±7fSLV/V
:tIOV mm
lVN. CONNECT GAIN RESISTOR tAG I BETWEEN PIN 4 AND PIN 1
50pprnrc
GAIN = 1 + lOk!l
Jr.lrnl
Figure 1. Basic Isolator Interconnection
THEORY OF OPERATION
The remarkable performance of the model 289 is derived from
the carrier isolation technique used to transfer both signal and
power between the amplifier's input stage and the rest of the
circuitry. A block diagram is shown in Figure 2.
Terminal Ratings. CMV performance is given in both peak
pulse and continuous ac, or dc peak ratings. Continuous peak
ratings apply from dc up to the normal full power response
frequencies. Figure 4 illustrates model 289 ratings between
terminals.
GAIN AND OFFSET TRIM PROCEDURE
The following procedure illustrates a calibration technique
which can be used to minimize output error. In this example,
the output span is +SV to -SV and Gain = 10V/V.
1. Apply EIN = 0 volts and adjust Ro for Eo = 0 volts.
2. Apply EIN = +O.SOOV dc and adjust RG for Eo
+S.OOOV dc.
=
3. Apply EIN = -O.SOOV dc and measure the output error
(see curve a).
H-+-~+---\V
~~~~
4. Adjust RG until the output error is one-half that measured
in step 3 (see curve b).
S. Apply +O.SOOV dc and adjust Ro until the output error is
one-half that measured in step 4 (see curve c).
IT==;::=:::===~ IN/OUT
II
SYNC
-5
Figure 2. Model 289 Block Diagram
The input signal is filtered and appears at the input of the noninverting amplifier, Al. This signal is amplified by A1, with its
gain determined by the value of resistance connected externally between the gain terminal and the inpu t common terminal. The output of A1 is modulated, carried across the isolation barrier by signal transformer T1, and demodulated. The
demodulated voltage is filtered, amplified and buffered by
amplifier A2, and applied to the output terminal. The voltage
applied to the Vs terminal is set by the regulator to +12V
which powers the 100kHz symmetrical square wave power
oscillator. The oscillator drives the primary winding of transformer T2. The secondary windings of T2 energize both input
and output power supplies, and drives both the modulator
and demodulator.
INTERELECTRODE CAPACITANCE AND TERMINAL
RATINGS
Capacitance. Interelectrode terminal capacitance, arising from
stray coupling capacitance effects between the input terminals
and the signal output terminals, are each shunted by leakage
resistance values exceeding SOGn.. Figure 3 illustrates model
289's capacitance, between terminals.
-4
-3
-2
-1
+1
+2
+3
+4
+5
OUTPUT VOLTAGE - Volu
Figure 5a. Recommended Offset and Gain Adjustment
for Gains> 1
.-----------<,..- Eo
-"_t ~~51
....--1r-2Ok
o 'J1.F
lOkn
-15V
Figure 5b. Recommended Offset Adjustment for G = 1VN
ISOLA TION AMPLIFIERS 5-47
II
Gain Nonlinearity: Linearity error is defined as the deviation
of the output voltage from the best straight line and is specified as a % peak-to-peak output voltage span; e.g., nonlinearity of mode! 289j operating at an output span of 10V pk-pk
(±5V) is ±0.05% or ±5mV. Figure 9 illustrates gain nonlinearity for any output span to 20V pk-pk (±10V). Figure 10
shows the effect of gain vs. gain nonlinearity.
PERFORMANCE CHARACTERISTICS
Figure 6 shows the phase shift vs. frequency. The low phase
shift and wide bandwidth of the model 289 make it suitable
for use in SCR Motor Controiler and other high frequency
applications.
'"
<>
/
<>
~
-
~89K
~
,
V
r----r--
--- ~
~
V
<>
<>
,
I
<>
289L
.........
FREQUENCY - H.
Figure 6. Typical 289 Phase vs. Frequency
000
Figure 7 illustrates the effect of source impedance imbalance
on CMR performance at 60Hz for gains of IV/V, lOY/V, and
100VIV. CMR is typically l20dB at 60Hz and a balanced
source impedance. CMR is >60dB for source impedance imbalances up to 100kn.
z
100
~
00
~
60
~
4 <>
8
20
""
SOURCE IMBALANCE _
"
20
Figure 9. Typical Gain Nonlinearity vs. Output Swing
28
l-
I
I
I
I
I
,,,
"
"
OUTPUT SWING P P VOLTS
,
J
GAN~lVIV
~
•
4
I
GAIN~10-100VN
~ 120
,
t-
~
I-
"
~ , f-o
,~ ,
K
l - v,; V
000
".
n
"
>
",.
Figure 7. Typical 289 Common Mode Rejection vs.
Source Impedance
000
Input Voltage Noise: Voltage noise, referred to input, is
dependent on gain and bandwidth. Figure 8 shows rms voltage
noise in a bandwidth from 0.05Hz to the frequency shown on
the horizontal axis. The noise in a bandwidth from 0.05Hz to
100Hz is 8/N pk-pk at a gain of 100VIV. The peak-to-peak
value is derived by multiplying the rms value at F = 100Hz
(1.2/lV rms) by 6.6.
For best noise performance in particular applications, a low
pass filter at the output should be used to selectively rolloff noise and undesired signal frequencies beyond the bandwidth of interest. Increasing gain will also reduce the noise,
referred to inpu t.
,
"
GAIN·- V!V
Figure 10. Typical Gain Nonlinearity vs. Gain
Common Mode Rejection: Input-to-output CMR is dependent
on source impedance imbalance, signal frequency and amplifier gain. CMR is rated at 115V ac, 60Hz and 1kn balanced
source at again of 100VIV. Figure 11 illustrates CMR performance as a function of signal frequency. CMR approaches
156dB at dc with source imbalance as high as 1kn. As gain is
decreased, CMR is reduced. At a gain of IV IV, CMR is typically 6dB lower than at a gain of 100V/V.
0
-,.~
~OO
~I
4
,
o~
LOIN
l~~:;:S
g
7
tl~~~':E~SS
SCOP~
LO
ollr
PWRCOM
h-
0
NOISETESTCIRCUIT
. """f:f~:
-l- ~-""":jl
. -r'[!JDi:
_
.......
5
-I-
OUT
'"
V""'"
0
-1-11 I I I
I I I -r-t-..l.
-
:
_~ '----'co,"
'"
t-- G1Vr FOR wrST r SlRrlSTOA
115V.c
'TEST CHlCUH
,,
,
'00
,.
TMBINATIION
)00
,0.
Figure 8. Typical Input Voltage Noise vs. Bandwidth
5-48 ISOLA TlON AMPLIFIERS
1.1l fACti RESISTOR CMR VALuE
""
1,.
.
Figure
Typical Common Mode Rejection vs. Frequency
at a Gain of 1VN, CMR is typically 6dB Lower than at a
Gain of 100VN
Applications
MULTICHANNEL APPLICATIONS
Isolation amplifiers containing internal oscillators may exhibit
a siowly varying offset voltage at the output when used in
multichannel applications. This offset voltage is the result of
adjacent internal oscillators beating together. For example, if
two adjacent isolation amplifiers have oscillator frequencies of
100.0kHz and 100.lkHz respectively, a portion of the difference frequency may appear as a slowly varying ou tpu t
offset voltage error. Model 289 eliminates this problem by
offering a synchronization terminal (pin 8). When this terminal
is interconnected with other model 289 synchronization terminals, the units are synchronized. Alternately, one or more
units may be synchronized to an external 100kHz ±2% squarewave generator by the connection of synchronization termial(s) to that generator. The generator output should be
2.5V-5.0V pop with 1kn source impedance to each unit.
Use an external oscillator when you need to sync to an external 100kHz source, such as a sub-multiple of a microprocessor clock. A differential line driver, such as SN75158, can
be used to drive large clusters of model 289. When using the
synchronization pin, keep leads as short as possible and do
not use shielded wire. These precautions are necessary to avoid
capacitance from the synchronization terminal to other points.
It should be noted that units synchronized must share the same
power common to ensure a return path.
APPLICATIONS IN INDUSTRIAL MEASUREMENT AND
CONTROL SYSTEMS
Isolated DAS: In data acquisition systems where multiple
transducers are powered by a single supply and the magnitude
of that supply is low enough for a multiplexer to handle the
voltages on all the transducers, it is economical to multiplex
ahead of an isolator. The fast settling time of the model 289
makes this configuration practical where slower isolators would
not be usable.
Figure 12 shows an application where the difference in voltage
between any two terminals of any of the transducers does not
exceed 30 volts. Though the input of the model 289 is protected against line voltage, its power terminals are not; neither
is the multiplexer so protected. This circuit will not, therefore,
withstand the differential application of line voltage.
10k
',.
(FROM
ISOLATOR)
EOUT
·15V
+15V
LM310 IS A BUFFER AMPLIFIER
Figure 13. 2·Pole, 5kHz Active Filter
Noise Reduction in Data Acquisition Systems: Transformer
coupled isolators must have a carrier to pass dc signals through
their signal transformers. Inevitably some carrier frequency
ripple passes through to the isolator output. As the bandwidth
of an isolator becomes a larger fraction of its carrier frequency,
this ripple becomes more difficult to control. Despite this difficulty, the model 289 produces very low ripple; therefore,
additional filtration will usually be unnecessary. However, in
some applications, particularly where a fast analog-to-digital
converter is used following the isolator, it may be desirable to
add filtration; otherwise, ripple may cause inaccurate conversions. The 2-pole low-pass shown in Figure 13 limits isolator
bandwidth to 5kHz, which is the full power bandwidth of the
model 289. Carrier ripple is much reduced. Another beneficial
effect of an output filter is smoothing of discontinuous high
frequency waveforms.
Motor Control and AC Load Control: Phase shift and bandwidth are important considerations for motor control and ac
load control applications. The model 289 possesses sufficient
bandwidth and acceptable phase shift for such tasks.
Figure 14 shows two model 289's sensing the armature voltage
and current of a motor. Faithful replicas of the waveforms
of these variables are applied to the motor control. Al operates at unity gain from divided R1-R3 to deliver an output
that is 11100 of the armature voltage of the motor. A2
operates at a gain of 100V IV to deliver a voltage 100 times
that developed across the current sensing shunt.
Multiplexer addressing is binary, an enable providing selection
of the circuit shown as a signal source. Optical isolation is provided for digital signals. When several of these circuits are used
for several groups of transducers, the model 289's should be
synchronized.
AID
CONVERTER
MOlOR
INPUT
Figure 12. OAS with MUX Ahead of Isolator
CONTROL
Figure 14. Isolating a Motor Controller
ISOLA TlON AMPLIFIERS 5-49
•
Figure IS shows three model 289's sensing the voltages on the
three phases of an ac load. The Y network shown divides the
voltages of the three phases and creates a neutral for the input
commons of the isolators. The output of each isolator is a
faithful replica of the phase of the waveform it senses. The
isolator ou tputs provide the feedback necessary for the trigger control to correcdy fire the triacs. In other applications,
the outputs of the isolators might have been fed to rms-to-dc
converters.
"~~~r---------------------------------~~--
.
TO
~-O~+---~---------------------+~~~,PWRCOMt+VS 7
l06dB
lOOdBmm
IkO H. In Lead Only
MAX
(5TO&4)
llOVnns
'0
(1.71
-1TO 0.25
.....rr--n,------Tr-:!020
tSV mm (±IOV mm)3
Balanced Source Impedance
@
i
±O.OOl9611000 Hours
~~~! ~e:raml
--I
J..-GRID 0 1IZ.54)
·PINS 9 AND 10 NOT PRESENT ON 200A
SHIELDED MOUNTING SOCKET
ACIOS4
Ip.Vp·p
1.5p.Vrms
5pAp·p
2.5kHz
50mVIp.s
2.0kHz(LOkHz)'
3 OkHz(1 OkHz)'
OFFSET VOLTAGE REFERRED TO INPUT
±(S + 50/G)mV
Imtlal, @ +25° C, Adjustable to Zero
vs Temperature (-2S Q C to +8SoC)
±(10+ ISOIG)p.VtC
±(8+250IG)p.VtC
VS. Supply Voltage
±lmV/%
RATED OUTPUT
Vnltage, 50k Load
Output Impedance
Output Ripple, IMHz BandWidth
OSCILLATOR DRIVE INPUT
Input Voltage
Input Frequency
±5V mm (±IOV mm)3
IkO
10mVpk·pk
=:~l
Regulation, No Load to Full Load
Ripple, 100kHz BandWldth
POWER SUPPLY, SINGLE POLARITY
Voltage, Rated Performance
Voltage, Operating
Current, Quiescent
8 to 16V pk·pk
100kHz ±S%, max
NIA
NIA
ISOLATED POWER OUTPUTS
Voltage Full Load
±13Vde
±5%
±SmAmm
±1SmAmm
+0, -15%
_1-
250mVp·p
2oomVp1
+15V dc
+8V de to +15.5V de
+20mA
TEMPERATURE RANGE
Rated Performance
Storage
_25°C to +85°C
-SSoC to +85°C
CASE DIMENSIONS
1.5" X 1.5" X 0.62"
@ z,
..L
f
:}
c£:
NOTES
I Gam temperature dnft IS specified as a percentase of output SlfDailevel.
IGain nonlmearity IS spec1ficd as a percenu,e of lOV pk-pk output span.
5These specs apply for a 20V pk-pk output span.
'Dono,l'" VlSOwb.. ...,.tingatoutpu,l"ans,......,than lOVpk"9k
Spcw.caaons subject to chaD" wichout DObcc.
PWRCOM
Figure 1. Model 290A and 292A Terminal Ratings
Symbol
VI
V2
V2
V2
V3
Z.
Rating
±1l0V nns (cont.)
±IOOOV pk (cont.)
±1500V pk (cant)
±1500V nns (I mID)
±50V pk (cont.)
5OGOll20pF
Remarks
WIthstand Voltage, Steady State
Isolation, Steady State, ac
Isolation, Steady State, dc
IsolatIOn, ac, 60Hz
IsolatIOn, de
Isola non Impedance
Table I. Isolation Ratings Between Terminals
~52
ISOLATION AMPLIFIERS
Understanding the Isolation Amplifier Performance
THEORY OF OPERATION
The remarkable performance of models 290A and 292A are
derived from the carrier isolation technique which is used to
transfer both signal and power between the amplifier's guarded
input stage and the rest of the circuitry. The block diagram for
both models is shown in Figure 2 below.
The bipolar input preamplifier operates single-ended (noninverting). Only a difference bias current flows with zero net
bias current. A third wire return path for input bias current is
not required. Gain can be Set from 1V IV to lOOV IV by changing the gain resistor, Ri. To preserve high CMR, the gain resistor must be.guarded. Best performance is achieved by shorting
terminal 2 to terminal 1 and operating the isolator at a gain
of lOOV/V.
For powering floating input circuitry such as buffer amplifiers,
instrumentation amplifiers, calibration signals and transducers,
dual isolated power is provided. High CMV isolation is achieved
by the low-leakage transformer coupling between the input
preamplifier, modulator section and the output circuitry. Only
the lOpF leakage capacitance between the floating input section
and the rest of the circuitry keeps the CMR from being infinite.
BIPOLAR INPUT AMPLIFIER
HI INPUT 5
H'
OUTPUT
9
il~kH2
1
•
Il!Put
(292AONlYJ
TRANSDuceR
MEDIUM.,,'/
COMMON
MODE
""
l
VOLTAGE
TR~NSDUCER
GROUND
GROUND COMMON MODE
VOLTAGE
SYSTEM
GROUND
Figure 3. Transducer - Amplifier Interface
GAIN AND OFFSET TRIM PROCEDURE
In applying the isolation amplifier, highest accuracy is achieved
by adjustment of gain and offset voltage to minimize the peak
error encountered over the selected output voltage span. The
following procedure illustrates a calibration technique which
can be used to minimize output error. In this example, the
output span is +SV to -SV and operation at Gain = lOV/V
is desired.
1. Apply EIN = 0 volts and adjust Ro for Eo = 0 volts.
2. Apply EIN = +O.SV dc and adjust RG for Eo = +S.OV dc.
3. Apply EIN = -{).SV dc and measure the output error (see
curve a).
4. Adjust ~ until the output error is one half that measured
in step 3 (see curve b).
s. Apply +O.SV dc and adjust Ro until the output error is
one half that measured in step 4 (see curve c).
L..._-,--{.!) ~~R
GAIN"' 1 + lkSl ~o:,~kfl)
(WN TO l00vN)
Figure 2. Block Diagram - Models 290A and 292A
-5
-4
-3
-2
-1
+1
+2
+3
+4
+5
OUTPUT VOLTAGE - Volts
GUIDEUNES ON EFFECTIVE SHEILDING &
GROUNDING PRACTICES
• Use twisted shielded cable to reduce inductive and capacitive pickup.
• Drive the transducer cable shield, S, with the common
mode signal source, EG, to reduce the effective cable capacitance as shown in Figure 3. This is accomplished by
connecting the shield point S, as close as possible to the
transducer signal low point B. This may not always be possible. In some cases the shield may be separated from signal
low by a portion of the medium being measured (e.g. pressure transducer). This will cause a common mode signal,
EM, to be generated by the medium between the shield and
the signal low. The 86dB CMR capability of both models
between the input terminals (HI IN and LO IN) and
GUARD, will work to suppress the common mode signal,
EM·
• Dress unshielded leads short at the connection terminals
and reduce the area formed by these leads to minimize
inductive pickup.
GAIN RESISTOR. RI • 1%. 50ppmrc METAL FILM TYPE IS RECOMMENDED
FOR GAIN" WN. LEAVE TERMINAL 2 OPEN.
FOR GAIN = 100VIV. SHORT TERMINAL 2 TO TERMINAL 1
GAIN. 1 +
100kn
~
OUTPUT FILTER, 10kn RESISTOR AND CAPACITOR, C.
SELECT C TO ROLL'()FF NOISE AND OUTPUT RIPPLE
f'I~B)' 2wC1~'kn)
Figure 4. Gain and Offset Adjustment
ISOLA TION AMPLIFIERS 5-53
SELECTING BANDWIDTH
In low frequency signal measurements, such as thermocouple
temperature measurements, strain gage measurements and
geophysical instrumentation, an external filter is used to
select bandwidth and minimize output noise.
When used with a buffer amplifier as shown in Figure Sa below, a series resistor (Rs) is used to lower the effective value
of the filter capacitor required to achieve very low frequency
(under 200Hz) noise filtering.
'40
,
III
GU~=T~~3::'R'::'; 1~~
1
Hllj
'20
~ 100
II UReE IMPEDANCE IMBALANC
II
r---. . . .
r--..
LOIN
.
?I-is.
~~
QUA!...:
!i
I--- ~ ''=:
I" I I III I II
OlIO
I"'-...
2 GAIN
1 LOIN
1
ob~~
G· lfl1NN
'"
20
-TEST CIRCUIT - EACH RESJSTOR ADJUSTED on TO 1DOkn
CMR VALUE GIVEN FOR HI IN LEAD AND LO IN LEAD
,.
,
'Ok
"
00k
'00
SOURCE IMPEDANCE IMBALANCE - n
Figure 7. Typical Common Mode Rejection VB. Source
Impedance Imbalance
Figure 5a. Selecting Bandwidth with External Capacitor and
Buffer
An active filter, as illustrated in Figure Sb will significandy
improve 60Hz noise reduction at the output by providing a
sharp roll-off characteristic. The SHz 3-pole active filter design
illustrated in Figure Sb, will increase the 60Hz noise reduction
by SOdB. Overall CMR performance of models 290 and 292
and the SHz active filter approaches !SOdB @ 60Hz and lkO
imbalance.
Gain Nonlinearity' Linearity error is defined as the deviation
of the output voltage from the best straight line and is specifield as a % of peak-to-peak outpu t voltage span; e.g., nonlinearity of models 290A and 292A operating at an output span of
10V pk-pk (±SV) is ±O.l% or ±lOmV. Figure 8 illustrates gain
nonlinearity for any output span to 20V pk-pk (±lOV).
.,.
• .20
t
>
1/
1/
0.18
J
L
014
.
'1012
V
I 010
~
! 0.08
i
NOTE. MOUNT FILTER ABelOSE TO EXTERNAL
AMPLIFIER AS POSSIBLE
i! 0."
Figure 5b. Selecting Bandwidth with a 3-Pole 5Hz Active Filter
PERFORMANCE CHARACTERISTICS
Common Mode Rejection. Input-to-<>utput CMR is dependent
on source impedance imbalance, signal frequency and amplifier gain. CMR is rated at llSV ac, 60Hz and lkO imbalance
at a gain of 100V/V. Figure 6 illustrates CMR performance as
a function of signal frequency. CMR approaches HOdB at dc
with source imbalances as high as lkO. As gain is decreased,
CMR is reduced. At a gain of 1 VIV, CMR is typically 12dB
lower than at a gain of 100VIV.
V
OO6
~
V
V
.02
8101214161a2O
OUTPUT VOLTAGE - Volts Pi»
FigureS. Typical Gain Nonlinearity vs. Output Voltage
Input Voltage Noise. Voltage noise, referred to input, is dependent on gairi and bandwidth as illustrated in Figure 9.
RMS voltage noise is shown in a bandwidth from O.OlHz to
the frequency shown on the horizontal axis. The noise in a
bandwidth from O.OlHz to 10Hz is Ij.1V pk-pk at a gain of
100VIV. This value is derived by multiplying the rms value at
f = 10Hz shown in Figure 9 by 6.6.
For best noise performance in particular applications, a low
pass filter at the output should be used to selectively roll-~ff
noise and undesired signal frequencies beyond the bandWIdth
of interest. Increasing gain will also reduce the inpu t noise.
,.
~
I ,. . . . . . _ -r-!
~
~_,,~" ..
I
I
1r.m- _
G.~
I
"TEST CIRCUIT - 1kO EACH RESISTOR
CMR VALUE GIVEN FOR HI IN LEAD AND LO IN LEAD
10
100
1000
lOt
FREQUENCY - Hz
Figure 6. Typical Common Mode Rejection vs. Frequency
Figure 7 illustrates the effect of source imbalance on CMR performance at 60Hz and Gain =100VIV. CMR is rypically
llOdB at 60Hz and a balanced source. CMR is maintained
greater than 70dB for source imbalances up to 100kO.
~54
ISOLA TlON AMPLIFIERS
~
I---
0.,00...........
g
~
!
---
~V~
.., b--- ~ ~ ,.
'00
1000
BANDWIDTH (-3cB) - Hz
FigU1'fl9. Typical Input Voltage Noise VB. Bandwidth
The Multichannel Isolation Amplifier
Input Offset Voltage Drift: Total input drift is composed of
two sources, input and output stage drifts and is gain dependent. The curve of Figure 10 illustrates total input drift over
the gain range of 1 to 100VN.
TO PINS 9 AND 10 OF ISOLATORS 18 THRU 32
2.,
IN
1000
'\
TO PINS 9 AND 10 OF ISOLATORS 2 THRU 16
~~
r--
292J
r-2jO
~
10
1
~~
100
10
GAIN-VN
Figure 13. External Oscillator Interconnection
Figure 10. Typical Input Offset Voltage Drift vs. Gain
REFERENCE EXCITATION OSCILLATOR, MODEL 281
When applying model 292A, the user has the option of building
a low cost 100kHz excitation oscillator, as shown in Figure 11,
or purchasing a module from Analog Devices-model 281.
SPECIFICATIONS
(typical @+25°Cand Vs = +15V dc unless otherwise noted)
MODEL
281
OUTPUT
Frequency
Waveform
Voltage (4) and
100kHz ±5%
Squarewave
iP terminals)
o to +12V pk
Fan-out 1,2
16 max
POWER SUPPLY RANGE'
High Input, Pm 6
QUiescent Current, N L
FL
Low Input. Pm 7
Quiescent Current, N L
FL
+(14 to 28)V de
+5mA
+16mA
+(8 to 14)V de
+12mA
+33mA
TEMPERATURE
NOTES
1
FREQ ADJUST ADJUST TRIM POT FOR OUTPUT FREQUENCY OF 100kHz ±5%
2
FOR SL.AVE OPERATION, REMOVE JUMPER FROM SYNC OUT AND SYNC IN PINS
3
USE CERAMIC CAPACITOR, "COG" OR "NPO" CHARACTERISTIC
Figure
1,.
Rated Performance
o to +70o C
Storage
-SSQ C
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
f.1..·----1(~M~X----..·-t1
(?>-;:===:::;T---i
281
(+BV TO +14V) ...
(+14v+~A·+28VI
+8S o C
100kHz Oscillator Interconnection Diagram
The block diagram of model 281 is shown in Figure 12. An
internal +12V dc regulator is provided to permit the user
the option of operating over two, pin selectable, power input ranges; terminal 6 offers a range of +14V dc to +28V dc;
terminal 7 offers an input range of +8V dc to +14V dc.
+V,
(0
1Model 292A OSCIllator drive input represents unity oscillator load.
2 For applicanons requmng more than 16 292As, additional 281s may
be used m a master/slave mode. Refer to Figure 13.
~
'Pull load consists of 16 model 292As and 281 OSCillator slave.
Specificaoons subject to change Without notice.
6
:(AX
--1
(12.41
L-----"nr-"IT"TT"T1rrrrr---l
0.20 (5.08) MIN
025 16.35) MAX
+1~Jl.S
')-_ _1-_-1 OSC~~:;OR
f - - - - - { 2 eOUTPUT
+1~l.Jl..
PWRCOM
(==~==!::===!:====~r3
"LEAVE TERMINAL
-lI-002IS.2)OIA
t
tOUTPUT
e OPEN, WHEN POWER IS APPLIED TO TERMINAL 7
11111
Figure 12_ Model2B1 Block Diagram
Model 281 oscillator is capable-of driving up to 16 model
292As_ As shown in figure 13, an additional model 281 may be
driven in a slave-mode to expand the total system channels
from 16 to 32. By adding additional model 281'sin this manner, systems of over 1000 channels may be easily configured.
BOTTOM VIEW
III 11111-l lit
WEIGHT 10GRAMS
I-
0.1 (2&4)GAID
PIN TERMINAL IDENTIFICATION
POWER COMMON
5
SYNC OUTPUT
,OUTPUT
6
+Vs HIGH RANGE +(14 to 28)V de
• OUTPUT
7
+VS: LOW RANGE +(8 to 14)V de
SYNC INPUT
MATING SOCKET:
CINCH #16 DIP OR EQUIVALENT
ISOLA TION AMPLIFIERS 5-55
APPLICA~IONS IN INDUSTRIAL MEASUREMENT AND
CONTROL SYSTEMS
Remote Sensor Interface. In chemical, nuclear and metal processing industries, models 290A and 292A can be applied to
measure and control off-ground millivolt signals in the presence ±ISooV dc CMV signals. In interface applications such
as pH control systems or on-line process measurement systems such as pollution monitoring, models 290A and 292A
offer complete galvanic isolation to eliminate troublesome
ground loop problems. Isolated power outputs and adjustable gain add to the application flexibility of these models.
Figure 14 illustrates how model 290A or 292A can be combined with a low drift, I/lVtC front-end amplifier, model
ADSI7L, to interface low level transducer signals. Both
products provide isolated ±13V dc power and front-end
guard in addition to eliminating ground loops and preserving high CMR (100dB @ 60Hz).
Isolated Temperature Measurements. Industrial temperature
measurements are often performed in harsh environments
where line voltages or transients can sometimes be impressed
on the temperature sensor. To provide protection for the delicate recording instrumentation, models 290A and 292A can be
applied as shown in Figure 16. The Analog Devices' AC2626
probe is a temperature sensor whose output is a current directly proportional to absolute temperature. The isolation
amplifier provides the isolated power ( +13 V de) as well as the
input/output isolation. Zero calibration is performed by
placing the AC2626 probe in a zero temperature bath and
adjusting Ro for Eo to 0 volts. Full scale output adjustment
is performed by placing the AC2626 probe in boiling water
(100°C) and adjusting Rs for 1.000Voutput.
+16V
Figure 16. Isolated Temperature Measurements
l-~--o~''''''
rw;;-,
~
-16V
POWER
COM
Figure 14. Input Signal Conditioning Using Isolated Power for
Transducer Buffer Amplifier
Instrumentation Amplifier. Models 290A and 292A provide
a floating guarded input stage capable of directly accepting
isolated differential signals. The noninverting, single-ended
input stage offers simple two wire interconnection with
floating input signals:
In applications where the isolated power is applied to transducers such as bridges which generate differential input signals
with common mode voltages measured With respect to the isolated power common, models 290A and 292A can be connected as shown in Figure 15. To achieve high CMR with
respect to the ISO PWR COM, the following trim procedure
is recommended.
CMR Trim Procedure
1) Connect a IV pk-pk oscillator between the +IN/-IN and
IN COM terminals as shown in Figure 15.
2) Set the input frequency at O.SHz and adjust Rl for minimum Eo.
3) Set the input frequency at 60Hz and adjustR2for minimum Eo.
4) Repeat steps 2 and 3 for best CMR performance.
~
OIrrent Loop Receiver. Model 290A and 292A can be applied
to measurement of analog quantities transmitted via 4-2OmA
current loops over substantial distances through harsh environments. Figure 17 shows an application of model 290A or 292A
as a current loop receiver. A 25n resistor converts the 4~2OmA
current input from a remote loop to a 100-50OmV differential voltage input, which the isolator amplifies, isolates, and
translates to a 0 to +SV output level at local system ground.
Among the most-helpful characteristics of the isolator in this
kind of measurement are the high common-mode rejection
(100dB minimum at 60Hz with lkn source unbalance) and
the high common-mode rating (±1 500 volts dc). The former
means low noise pickup; the latter means excellent isolation
and protection against large transients. The high commonmode rejection, permitting relatively low input voltage to be
used (O.4V span, in this case), permits the use of a low currentmetering resistance, which in tum results in low compliancevoltage loading on the current loop, and therefore permits insertion into existing loops without encountering overrange
problems. The gain of 12.5 provides a substantial output
span, and the floating output permits biasing to a 0 to 5V
range.
"'"
4-2OmA
MEASURING
~~JlRR'NT ~~t:"D RESTOR
~~
7 ....,
SPAN
RESISTOR
'<:~
.8E~ CUR TRIM
0-125V!V
ZERO ADJUST
ADJUST FOR
~.a.:;~V WHEN
:.<~:
,
Eo
9
:-="Tj:_-_-_....;_':,F::f-:-:-:-"O!
-15V
"" PROCEDURE
1VPK-PK
'.COM
.... o-------==-j--4----{!l
-v... o - - - - - - - - - < l____
~
Eo-IO~',- ..I+ (~) x..ln.]
/~
GAIN
INPUT
SIGNAL
~
CMR ERROR
CMR a 84dB
Figure 15. Application of 290A as Instrumentation Amplifier
5-56 ISOLATION AMPLIFIERS
Figure 17. Isolated Analog Interlace; 4 to 20mA is Converted
to 0 to +5V at the Output, with Up to ±1500Vof Isolation
Analog Multipliers/Dividers
Contents
Page
Selection Guide . . . . . . . . . . . . . . . . . . . . . . .
6-3
Orientation . . . . . . . . . . . . . . . . . . . . . . . . .
6-4
AD532 - Internally Trimmed Integrated Circuit Multiplier.
6-7
AD534 - Internally Trimmed Precision IC Multiplier
6 - 13
AD538 - Real-Time Analog Computational Unit (ACU) ..
6 - 23
AD539 - Wide band Dual-Channel Linear Multiplier/Divider .
6 - 31
AD632 - Internally Trimmed Precision IC Multiplier
6 - 39
AD834 - High Frequency Four-Quadrant Multiplier . . . . .
6 - 43
ANALOG MULTIPLIERS/DIVIDERS 6-1
6-2 ANALOG MUL TIPLIERSIDIVIDERS
Selection Guide
Analog Multipliers/Dividers
Model
AD532
AD534
AD538
AD539
AD632
AD834
SmaUSignal
Bandwidth
MHz
0.4
30
1
500
Full-Scale
Accuracy
%
I
0.25
0.5
I
0.5
0.5
y
X
Nonlinearity Nonlinearity
%ofFS
%ofFS
0.5
0.12
0.2
0.01
0.08
0.01
Full-Scale
Output
Page
Notes
10V
10V
10V
6-7
6- 13
6- 23
4-quadrant multiplication
4-quadrant mUltiplication
Multiplication, division, powers, roots
lmA
10V
4mA
6- 31
6 - 39
6 - 43
2-quadrant multiplication/division
High frequency 4-quadrant multiplier
ANALOG MUL T/PLIERSIDIVIDERS 6-3
Orientation
Analog Multipliers/Dividers
The devices catalogued in this section are high-performance ICs
that accept analog voltages and multiply, divide, square and/or
square-root them, depending on device properties and connections.
Other multiplying devices available from Analog Devices include
digital multipliers (in DSP Products Databook) and multiplying
D/A converters (Data Conversion Products Databook).
Multiplication: For two inputs, Vx and VY' a multiplier will
provide the output, E out = VxV/Ere{, where Ere{ is a dimensional
constant, usually of lOY nominal value. If Ere{= lOY, E out = lOY
when Vx and Vy are lOY. Multipliers are used for modulation
and demodulation, fixed and variable remote gain adjustment,
power measurement and mathematical operations in analog
computing, curve fitting and linearizing.
If the inputs may be of either positive or negative polarity and
the output polarity is in a correct relationship for multiplication,
the device is called a "four-quadrant" multiplier, reflecting the
four quadrants of the X-Y plane.
devices published in this section. In addition to the products
listed here, a number of popular earlier products are still available;
data sheets are available upon request.
Internal Architecture: All of the devices in this section rely on the
logarithmic properties of silicon P-N junctions. An example of
the translinear principle that they embrace can be seen in the
circuitry of a "Gilbert cell," employed in various forms for
analog multiplication. Its four-quadrant multiplying circuitry
and performance are described in (1), with further references to
the original sources. The input voltages are converted to currents;
the currents are multiplied together and divided by a reference,
and the net output current, IxIylIrec, is converted to voltage by
feedback around the output amplifier. The feedback terminals
are available as inputs for applications involving division.
A
Squaring: If Vx = Vy = Vm' a multiplier's output will be Vin21Ere{.
A four-quadrant multiplier, used as a squarer, will have an output that is positive whether Vm is positive or negative. Squarers
are useful in frequency doubling, power measurement of constant
loads and mathematical operations.
Q1
I+~
,"
Q2
I,'
I_~
.-------~~--+---~--~--~
Division: For a numerator input, V.. and a denominator input,
V.. an analog divider will provide the output, E out = EreiVJVJ.
If Ere{ = lOY, E out will be lOY or less for Vz ,.; Vx. Vx is of a
single polarity and will not provide meaningful results if it
approaches zero too closely. If Vz may be of either positive or
negative polarity, the device is descnbed as a "two-quadrant"
divider, and the output will reflect the polarity of Vz. Analog
dividers are used to compute ratios - such as efficiency, attenuation,
or gain; they are also used for fixed and variable remote gain
adjustment, ratiometric measurements and for mathematical
operations in analog computing.
Basic Four-Quadrant Variable- Transconductance Multiplier
Circuit
Square Rooting: For a numerator input, Vin, and a denominator
input, Eo (th~ ~utP~t fed back to the denominator in!Vt), the
output of a dlVlder IS Eo = Ere{ (VmlEJ; hence Eo = ErecVin.
A square rooter works in one quadrant; some devices require
external diode circuitry to prevent latchup if the input polarity
changes, even momentarily. Square roots are used in vector and
rms computation, to linearize flowmeters, and for mathematical
operations in analog computing.
CHOOSING A MULTIPLIER, DMDER, ETC.
A number of devices are listed here, differing in internal ararchitecture, external functional configuration and performance
specifications. Most have essentially fixed references; the AD538
is a multifunction device that performs the one-quadrant operation,
Eo = V.t(VylVJm , where m is an exponent adjustable from 1/5
to 5.
Considerable information on these functions, the nature of devices
to perform them and extensive discussions of their applications
can be found in the Nonlinear Circuits Handbook.' A wealth of
information is also to be found in the data sheets for the individual
INonJi1Jear Circuits HlUldbook, D.H. Sheingold, ed., 1976, 536pp., $5.95,
Analog Devices, Inc., P.O. Box 796, Norwood, MA 02062
6-4 ANALOG MUL TIPLIERSIDIVIDERS
AD538 Functional Block Diagram
In multifunction devices like the AD538, the feedback currents
of the Vz and Vx input op amps are used to develop logarithmic
voltages across transistor base-emitter junctions; these voltages
are differenced to provide the logarithm of the ratio, V,IVx.
At the user's choice, this log ratio is either amplified (m> 1),
attenuated (m10:1),
will always benefit greatly by the trimming of offsets, especially
Zo (affects offsets) and Xo (affects gain), for small values of X.
and has a temperature specification), and a nonlinear one, which
is irreducible. F eedthrough is usually specified at one frequency
(50Hz) for a 20V p-p sine wave input. It increases with frequency,
and plots of typical feedthrough vs. frequency are provided on
multiplier data sheets.
Noise is specified and measured with both inputs at zero signal
and zero impedance (Le., shorted). For low-frequency applications, ftItering the output of the mulitplier may improve smallsignal resolution significantly.
DEFINITIONS OF SPECIFICATIONS·
Accuracy is defined in terms of total error of the multiplier at
room temperature and constant nominal supply voltage. Total
error includes the sum of the effects of input and output dc
offsets, nonlinearity, and feedthrough. Temperature dependence
and supply-voltage effects are specified separately.
Dynamic Parameters include: small-signal bandwidth, full-power
response, slew(ing) rate, small-signal amplitude error and settling
time.
Small-Signal Bandwidth is the frequency at which the output is
down 3dB from its low-frequency value (Le., by about 30%) for
a nominal output amplitude of 10% of full scale.
Scale Factor: The scale-factor error (or gain error) is the difference
between the average scale factor and the ideal scale factor (e.g.,
(IOV) -I). It is expressed in percent of the output signal. Temperature dependence is specified.
Full-Power Response is the maximum frequency at which the
mUltiplier can produce the full-scale voltage into its rated load
without noticeable distortion.
Output Offset refers to the offset voltage at the output -amplifier
stage. This offset is usually minimized at manufacture and can
be trimmed where high accuracy is desired. Output offset vs.
temperature is also specified.
Slew(ing) Rate (V/jJ-s) is the maximum rate of change of output
voltage for the product of a full-scale dc voltage and a full-scale
step input.
Small-Signal Amplitude Error is defined in relation to the frequency
at which the amplitude response, or scale-factor, is in error by
1%, measured with a small (10% of full-scale) signal.
Linearity Error or Nonlinearity is the maximum difference between
actual and "best-straight-line" theoretical output, for all pairs of
input values, expressed as a percentage of full scale, with all
other dc errors nulled. It is the irreducible minimum error. It is
usually expressed in terms of X and Y nonlinearity, with the
named input swinging over its full-scale range and the other
input at (±) IOV. Y nonlinearity is considerably less than X
nonlinearity in simple "Gilbert-cell" multipliers. This specification
includes nonlinear feedthrough.
Settling Time, for the product of a ± lOY step and 10V dc, is
the total length of time the output takes to respond to an input
change and stay within some specified error band of its final
value. Settling time cannot be accurately predicted from any
other dynamic specifications; it is specified in terms of a prescribed
measurement.
Vector Error is the most sensitive measure of dynamic error. It is
usually specified in terms of the frequency at which a phase
error of 0.01 radians (0.57°) occurs.
X or Y F eedthrough is the signal at the output for any value of X
or Y input in the rated range, when the other input is zero. It
has two components, a linear one, corresponding to an input
offset at the zero input, which can be trimmed out (but can drift
DENOMINATOR
V,
+
r--;==~=~r1:--00UT' Eo
Xl
X2
OUTPUT, Eo
OUT
R lOAD
X,
(MUST BE PROVIDED)
X2
AD535
Zl
Y1
6-6 ANALOG MUL TlPLIERSIDIVIDERS
Zl
Y1
Eo (-Eo)
Divider
+
_ INPUT, v'z
Z2
~
V2
BASIC RELATIONSHIP' (X, - X2 ) IV, - Y2} = 10V (Z,- Z2)
VxVy = 10V Eo
*These are general definitions. Further defmitions are provided as
footnotes to the Specifications tables; they should be read carefully.
AD535
_ NUMERATOR, Vz
Z2
Y2
Multiplier
+
OUT
=
10V Vz
Square Rooter
Eo =J-10V VZ
·~ANALOG
WDEVICES
Internally Trimmed
Integrated Circuit Multiplier
AD532 \
FEATURES
Pretrimmed To ±1.0% (AD532K)
No External Components Required
Guaranteed ±1.0% max 4·Quadrant
Error (AD532K)
Diff Inputs For (X1-X2) (V1-V21110V
Transfer Function
Monolithic Construction, Low Cost
APPLICATIONS
Multiplication, Division, Squaring,
Square Rooting
Algebraic Computation
Power Measurements
Instrumentation Applications
Available in Chip Form
PRODUCT DESCRIPTION
The ADS 32 is the first pretrimmed single chip monolithic
multiplier/divider. It guarantees a maximum multiplying
error of ±1.0% and a ±10V output voltage without the need
for any external trimming resistors or output op amp. Because
the AD S3 2 is internally trimmed, its simplicity of use provides
design engineers with an attractive alternative to modular
multipliers, and its monolithic construction provides
significant advantages in size, reliability and economy. Further,
the ADS 32 can be used as a direct replacement for other IC
multipliers that require external trim networks (such as the
ADS30).
FLEXIBILITY OF OPERATION
The ADS 32 multiplies in four quadrants with a transfer
function of(Xl-X2)(Yl-Y2)/10V, divides in two quadrants
with a 10VZ/(Xl-X2) transfer function, and square roots in
one quadrant with a transfer function of ± Yl0VZ. In addition to these basic functions, the differential X and Y inputs
provide significant operating flexibility both for algebraic
computation and transducer instrumentation applications.
Transfer functions, such as XY/IOV, (X2_y2)/IOV,±X2/
lOY, and IOVZI(X 1-X2) are easily attained, and are extremely useful in many modulation and function generation
applications, as well as in trigonometric calculations for
airborne navigation and guidance applications, where the
monolithic construction and small size of the ADS 32 offer
considerable system advantages. In addition, the high CMRR
(7SdB) of the differential inputs makes the AD532 especially
well qualified for instrumentation applications, as it can
provide an output signal that is the product of two transducergenerated input signals.
AD532 PIN CONFIGURATIONS
ADS32H
v,
·Vs
ADS32D
x,
NC
NC
X2
NC
NC
-Vs
GND
Vas
Yz
--
OUT
+Vs
NC ARE NO CONNECT PINS
GUARANTEED PERFORMANCE OVER TEMPERATURE
The ADS32J and ADS32K are specified for maximum multiplying errors of ±2% and ±l % of full scale, respectively at
+2SoC, and are rated for operation from 0 to +70oC. The
ADS 32S has a maximum multiplying error of ±1 % of full
scale at +2SoC; it is also 100% tested to guarantee a maximum
error of ±4% at the extended operating temperature limits of
-SSoC and +12SoC. All devices are available in either the
hermetically-sealed TO-IOO metal can or TO-116 ceramic DIP.
ADVANTAGES OF ON-THE-CHIP TRIMMING
OF THE MONOLITHIC ADS32
1.
True ratio metric trim for improved power supply
rejection.
2.
Reduced power requirements since no networks
across supplies are required.
3.
More reliable since standard monolithic assembly
techniques can be used rather than more complex
hybrid approaches.
4.
High impedance X and Y inputs with negligible
circuit loading.
S.
Differential X and Y inputs for noise rejection and
additional computational flexibility.
ANALOG MUL T/PLIERSIDIVIDERS 6-7
SPECIFICATIONS
(@ +25"1:, Vs= ±l5V, R2:2kO Vos grounded)
Model
AD532J
Min
Typ
AD532K
Mu
Mia
Typ
AD532S
Mu
Min
Typ
Mu
Uai\"
MULTIPLIER PERFORMANCE
(X,-X,)(Y,-Y,)
Transfer FUDction
10V
±1.5
±2.5
::!:O.04
±0.05
±0.8
±0.3
Total Error ( -IOVsX, Ys + 10V)
TA=mmtomax
Total Error vs Temperature
Supply Rejecuon(: 15V: 10%)
Noniinearity,X(X~20Vpk-pk, Y~
Nonlmearity, Y(Y~20Vpk-pk,X~
Feedthrough, X (Y Nulled,
X ~ 20V pk-pk 50Hz)
Feedthrough, Y (X Nulled,
Y ~ 20V pk·pk 50Hz)
Feedthrough V1. Temp.
Feedthrough V1. Power Supply
IOV)
IOV)
(X,-X,)(Y,-Y,)
(X,-X,)(Y,- Y,)
10V
±O.7
: 1.5
:0.03
±0.05
±O.s
±0.2
±2.0
10V
±0.5
±I.O
±I.O
±4.0
±0.04
±0.01
±0.05
±0.5
±O.2
%
%
%rC
%/%
%
%
50
200
30
100
30
100
mV
30
2.0
±0.25
15O
25
1.0
±0.25
80
25
1.0
±0.25
80
mV
mVp.prc
mV/%
DYNAMICS
SmaIIS>gnaIBW(VOUT~O
Inn.)
1% Amphtude Error
Slew Rate (VOUT 20 pk-pk)
Settlmg Tune (to 2%,.:\VOUT ~ 20V)
NOISE
Wideband NOise f ~ 5Hz to 10kHz
f~5Hzt05MHz
OUTPUT
Output Voltage Swing
Output Impedance (f'" 1kHz)
Output Offaet Voltage
OutputOffsetVoltagev. Temp.
Output Offset Voltagevs. Supply
INPUT AMPLIFIERS (X, Y and Z)
S,gna1 Voltage Range (Dtff. or CM
Operaung DifI)
CMRR
±10
I
75
45
I
I
75
45
I
I
75
45
I
MHz
kHz
V/fJo'
fJo'
0.6
3.0
0.6
3.0
0.6
3.0
mV(rm.)
mV(rms)
±13
±IO
I
±40
0.7
±2.5
±13
I
±2.5
50
3
1.5
8
:5
±25
10
Offset Current
:tIO
±30
±0.3
Dtfferential Resistance
10
Z Input T mm to T max
1.5
8
±5
±25
::to.1
10
4
±IS
:to.1
10
mV
mVrc
mV/%
V
dB
±IO
±IO
50
ZInput
±30
2.0
±2.S
::tIO
V
0
I
0.7
40
Input BUlS Cunent
X, Ylnputs
X, YlnputsTrruntoTnwr.
±13
±10
±30
4
fJoA
±IS
".A
".A
fJoA
fJoA
MO
DIVIDER PERFORMANCE
Transfer Function (X, > X,)
Total Error
(Vx~ -IOV, -IOVsVzs+ IOV)
(Vx ~ -IV, -IOV"'Vz '" + IOV)
IOV ZI(X,- X,)
IOV ZI(X, - X,)
IOV ZI(X, - X,)
%
%
±I
±3
±I
:3
±2
±4
SQUARE PERFORMANCE
Transfer Function
(X,-X,>,
(X,-X,>,
(X,-X,)'
--wv-
--wv-
----wv:0.8
:0.4
:0.4
Transfer Function
-vloVz
-vloVz
-vloVz
Total Error (OV",Vz'" 10V)
±1.S
±l.O
±l.O
Total Error
%
SQUARE-ROOTER PERFORMANCE
POWER SUPPLY SPECIFICATIONS
Supply Voltage
Rated Performance
Operating
Supply Current
Quiescent
PACKAGE OPTIONS'
TO-II6(D-14)
TO-lOO(H-IOA)
±IS
4
±IS
±IS
:tIS
:!:10
6
AD532JD
ADS32JH
:10
±IS
4
AD532KD
AD532KH
%
:10
6
4
:22
V
V
6
rnA
AD532SD
ADS32SH
NOTE
ISee Secnon 16forpackage outilDe mfonnauon.
Speafications subJect to change without nonce.
Speafications shown in boldface are tested. on aU producnon uruts at fmal electr-1C8I test. Results from those tests are used to calculate ourgoing quality levels.
tHJ ANALOG MUL TIPLIERSIDIVIDERS
All min and max specifications are guaranteed, although only tbose shown
in boldface are tested on aU production units.
FUNCTIONAL DESCRIPTION
The functional block diagram for the ADS32 is shown in
Figure 1, and the complete schematic in Figure 2. In the
multiplying and squaring modes, Z is connected to the output
to close the feedback around the output op amp. (In the
divide mode, it is used as an input terminaL)
x,
The X and Y inputs are fed to high impedance differential
amplifiers featuring low distortion and good common mode
rejection. The amplifier voltage offsets are actively laser
trimmed to zero during production. The product of the two
inputs is resolved in the multiplier cell using Gilbert's
linearized transconductance technique. The cell is laser
trimmed to obtain V out = (X 1 -X2)(Y 1 -Y 2)/10 volts.
The built:in op amp is used to obtain low output impedance
and make possible self-contained operation. The residual
output voltage offset can be zeroed at Vos in critical applications .... otherwise the Vos pin should be grounded.
Vx
1 X2
Vy
1 Y2
Y,
OUTPUT
Vas
(WITH Z TIED TO OUTPUT)
Figure 1. Functional Block Diagram
•
Figure 2. AD532 Schematic Diagram
ORDERING GUIDE
Model
AD532JH
AD532JD
AD532KH
AD532KD
Max Mult Error
±2.0%
±2.0%
±1.0%
±1.0%
Temperature Range
Model
o to +70°C
o to +70°C
o to +70 oC
o to +70°C
AD532SH
AD532SD
AD532SH/883B
Max Mult Error
±1.0%
±1.0%
±1.0%
±1.0%
AD532SD/883B
Temperature Range
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
_55°C to +125°C
CHIP DIMENSIONS AND BONDING DIAGRAM
Dimensions shown in inches and (mm).
t-~------ (~:m)
---------Vs
0.062
(1.575)
LL
+Vs
GND
Vos
Y2
ANALOG MUL TlPLlERSIDIVIDERS 6-9
ADS32 PERFORMANCE CHARACTERISTICS
Multiplication accuracy is defined in terms of total error at
+2SoC with the rated power supply. The value specified is in
percent of full scale and includes Xin and Yin nonlinearities,
feedback and scale factor error. To this must be added such
application-dependent error terms as power supply rejection,
common mode rejection and temperature coefficients
(although worst case error over temperature is specified for
the ADS32S). Total expected error is the rms sum of the
individual components, since they are uncorrelated.
AC FEEDTHROUGH
AC Feedthrough is a measure of the multiplier's zero
suppression. With one input at zero, the multiplier output
should be zero regardless of the signal applied to the other
input. Feedthrough as a function of frequency for the
AD532 is shown in Figure 5. It is measured for the condition
Vx = 0, Vy = 20V(p-p) and Vy = 0, Vx = 20V(p-p) over the
given frequency range. It consists primarily of the second
harmonic and is measured in millivolts peak-to-peak.
1000
Accuracy in the divide mode is only a little more complex. To
achieve division, the multiplier cell must be connected in the
feedback of the output op amp as shown in Figure 13. In this
configuration, the multiplier cell varies the closed loop gain of
the op amp in an inverse relationship to the denominator
voltage. Thus, as the denominator is reduced, output offset,
bandwidth and other multiplier cell errors are adversely affected. The divide error and drift are then Em • lOV/Xl-X2)
where Em represents multiplier full scale error and drift, and
(Xl-X2) is. the absolute value of the denominator.
Y FEEDTHAU
:e
V
100
v
I
ex FEEDTHRU
,
100
NONLINEARITY
Nonlinearity is easily measured in percent harmonic distortion.
The curves of Figures 3 and 4 characterize output distortion as
a function of input signal level and frequency respectively,
with one input held at plus or minus lOV dc. In Figure 4 the
sine wave amplitude is 20V(p-p).
°
x m......
_f---
,
COMMON MODE REJECTION
The ADS 32 features differential X and Y inputs to enhance
its flexibility as a computational multiplier/divider. Common
mode rejection for both inputs as a function of frequency is
shown in Figure 6. It is measured with Xl = X2 = 20V(p-p),
(Y l-Y 2) = ±lOV dc and Y 1 = Y 2 = 20V(p-p), (Xl-X2) =
±lOV dc.
0
..
./ ,/
./ Ym
'OM
'M
Figure' 5. Feedthrough VS. Frequency
10
/~
",/
lOOk
'OFREQUENCY
k
_ Hz
1k
r--.
VI-"'
r- r--.
I !I
~
YCOMMONU.W
~t"
"lOY
0
x COMMON
0
MOD~
~~
z' =
(V,-Y
+10V
0
~t--
10
001
,
2
3
10
.. .
,
10
•
9lOn121314
1
pell.K SIGNAL AMPLITUDE· Votta
.
,
10
FREQUENCY
10
Hz
,
10
.
'0
,
Figure 6. CMRR vs. Frequency
Figure 3. Percent Distortion vs. Input Signal
'0
'00
V
r
z
Q
20V pop SIGNAL
g
~
RL"'2kn CL'''OpF
,
c-
'/
10
~~2kn Cl=1000pF
\
\'\
"
V
Xm
"0
100
,.
'Ok
Ii
lOOk
FREQUENCY - Hz
Figure 4. Percent Distortion vs. Frequency
6-10 ANALOG MULTIPLIERS/DIVIDERS
'M
001
'Ok
'OOk
FREQUENCY - Hz
'M
Figure 7. Frequency Response, Multiplying
'OM
Applying the AD532
DYNAMIC CHARACTERISTICS
The closed loop frequency response of the ADS 32 in the
multiplier mode typically exhibits a 3dB bandwidth of
IMHz and rolls off at 6dB/octave thereafter. Response
through all inputs is essentially the same as shown in
Figure 7. In the divide mode, the closed loop frequency
response is a function of the absolute value of the
denominator voltage as shown in Figure 8.
Stable operation is maintained with capacitive loads to
1000pF in all modes, except the square root for which
SOpF is a safe upper limit. Higher capacitive loads can be
driven if a lOon resistor is connected in series with the
output for isolation.
0
Yz"O 1 X Vx SIN wT
0
f'.
""" I~
o
,
10.
'00k
Vx"'WV
f'
'\
1\\
~X=5V
\
1\
,OM
FREQUENCV • H'l
Figure 8. Frequency Response, Dividing
POWER SUPPLY CONSIDERATIONS
Although the ADS32 is tested and specified with ±lSV dc
supplies, it may be operated at any supply voltage from
±lOV ro ±18V for the J and K versions and ±10V to ±22V
for the S version. The input and output signals must be
reduced proportionately to prevent saturation, however,
with supply voltages below ±ISV, as shown in Figure 9.
Since power supply sensitivity is not dependent on external
null networks as in the ADS 30 and other conventionally
nulled multipliers, the power supply rejection ratios are
improved from 3 to 40 times in the ADS32.
I
SATURATED OUTPUT
SWING
V
/ ~O'VIN"",
.~
•
4
3"-..
2
,
10k
1k
100
'0
'00
FREQUENCY
Figure 10. Spot Noise vs. Frequency
APPLICATIONS CONSIDERAnONS
The performance and ease of use of the AD S 32 is achieved
through the laser trimming of thin film resistors deposited
directly on the monolithic chip. This trimming-on-the-chip
technique provides a number of significant advantages in
terms of cost, reliability and flexibility over conventional
in-package trimming of off-the-chip resistors mounted or
deposited on a hybrid substrate.
First and foremost, trimming on the chip eliminates the
•
need for a hybrid substrate and the additional bonding wires
'
that are required between the resistors and the multiplier
chip. By trimming more appropriate resistors on the ADS 32
chip itself, the second input terminals that were once
committed to external trimming networks (e.g., ADS30) have
been freed to allow fully differential operation at both the X
and Y inputs. Further, the requirement for an input
attenuator to adjust the gain at the Y input has been
eliminated, letting the user take full advantage of the high
input impedance properties of the input differential amplifiers.
Thus, the ADS32 offers greater flexibility for both algebraic
computation and transducer instrumentation applications.
Finally, provision for fine trimming the output voltage offset
has been included. This connection is optional, however, as
the ADS32 has been factory-trimmed for total performance
as described in the listed specifications.
REPLACING OTHER IC MULTIPLIERS
Existing designs using IC multipliers that require external
trimming networks (such as the ADS 30) can be simplified
using the pin-for-pin replaceability of the ADS 32 by merely
grounding the X2. Y2 and Vos terminals. (The Vos terminal
should always be grounded when unused.)
APPLICATIONS
MULTIPLICATION
FOR 1% LlNEAArrv
..
X,
X2
_4
'0
'2
,.
,.
,.
AD632
v,
20
22
OUT
VOUT
+
V2
POWER SUPPLY VOLTAGE· Volts
Figure 9. Signal Swing vs. Supply
NOISE CHARACTERISTICS
All ADS32s are screened on a sampling basis to assure that
output noise will have no appreciable effect on accuracy.
Typical spot noise vs. frequency is shown in Figure 10.
(OPTIONAL)
+Vs
-Vs
Figure ". Multiplier Connection
ANALOG MUL TIPLIERSIDIVIDERS 6-11
For operation as a multiplier, the AD532 should be connected
as shown in Figure 11. The inputs can be fed differentially to
the X and Y inputs, or single-ended by simply grounding the
unused input. Connect the inputs according to the desired
polarity in the output. The Z terminal is tied to the output
to close the feedback loop around the op amp (see Figure 1).
The offset adjust Vos is optional and is adjusted when both
inputs are zero volts to obtain zero out, or to buck out other
system offsets.
SQUARE ROOT
X,
X,
AD532
Vour
VOUl
SQUARE
X,
Figure 14. Square Rooter Connection
VOUT
Your
(OPTIONAL)
+Vs
-Vs
Figure 12. Squarer Connection
The squaring circuit in Figure 12 is a simple variation of the
multiplier. The differential input capability of the ADS32 can
be used, however, to obtain a positive or negative output
response to the input .... a useful feature for control
applications, as it might eliminate the need for an additional
inverter somewhere else.
The connections for square root mode are shown in
Figure 14. Similar to the divide mode, the multiplier cell is
connected in the feedback of the op amp by connecting the
output back to both the X and Y inputs. The diode DI is
connected as shown to prevent latch-up as Zin approaches
o volts. In this case, the Vos adjustment is made with
Zin = +0.1 V dc, adjusting Vos to obtain -1.0V dc in the
ou tpu t, Vout = - v' 10VZ. For optimum performance, gain
(S.F.) and offset (Xo) adjustments are recommended as
shown and explained in Table I.
DIFFERENCE OF SQUARES
Xo-------~~------~
DIVISION
OUT
r------~
X
Your =
lO~Z
Your
X2 _ y2
VOUl
.=
X,
----;ov-
r---~X,
AD532
(OPTIONAL)
OUT
+v,
-v,
Figure 15. Differential of Squares Connection
-Vs
-Vs
Figure 13. Divider Connection
The ADS 32 can be configured as a two-quadrant divider by
connecting the multiplier cell in the feedback loop of the
op amp and using the Z terminal as a signal input, as shown
in Figure 13. It should be noted, however, that the output
error is given approximately by 10VEm /(XI-X2), where Em
is the total error specification for the multiply mode; and
bandwidth by fm • (XI-X2)110V, where fm is the bandwidth of the multiplier. Further, to avoid positive feedback,
the X input is restricted to negative values. Thus for singleended negative inputs (OV to -lOY), connect the input to X
and the offset null to X2; for single-ended positive inputs
(OV to + 10V), connect the input to X2 and the offset null
to Xl. For optirnum performance, gain (S.F.) and offset (Xo)
adjustments are recommended as shown and explained in
Table I.
For practical reasons, the useful range in denominator input
is approximately SOOmV"; 1(XI-X2) I"; 10V. The voltage
offset adjust (Vos), if used, is trimmed with Z at zero and
(XI-X2) at full scale.
6-12 ANALOG MUL TlPLlERSIDIVIDERS
The differential input capability of the ADS32 allows for the
algebraic solution of several interesting functions, such as
the difference of squares, X2_y2110V. As shown in Figure 15,
the ADS 32 is configured in the square mode, with a simple
unity gain inverter connected between one of the signal
inputs (Y) and one of the inverting input terminals (-Yin)
of the multiplier. The inverter should use precision (0.1 %)
resistors or be otherwise trimmed for unity gain for best
accuracy.
TABLE I
ADJUST PROCEDURE (Divider or Square Rooter)
DIVIDER
with:
Adjust
X
Scale Factor -lOY
Xo (Offset) -IV
Repeat if required.
Adjust for:
Z
+lOV
+O.lV
Vout
±lOV
±lOV
SQUARE ROOTER
With: Adjust for:
Z
+10V
+O.lV
Vout
-10V
-IV
Internally Trimmed
Precision Ie Multiplier
AD534 I
IIIIIIIIIII ANALOG
WDEVICES
FEATURES
Pretrimmed to ±O.25% max 4·Quadrant Error (AD534L)
All Inputs (X, V and Z) Differential, High Impedance for
[(XI-XZ HY I -Y z Il10V] +Zz Transfer Function
Scale· Factor Adjustable to Provide up to X100 Gain
Low Noise Design: 90l.lV rms, 10Hz-10kHz
Low Cost, Monolithic Construction
Excellent Long Term Stability
APPLICATIONS
High Quality Analog Signal Processing
Differential Ratio and Percentage Computations
Algebraic and Trigonometric Function Synthesis
Wideband, High·Crest rms·to-dc Conversion
Accurate Voltage Controlled Oscillators and Filters
Available in Chip Form
AD534 FUNCTIONAL BLOCK DIAGRAM
I-;;~~l--------o
o------j
+Vs
.Vs
TRANSFER FUNCTION
x,
Va "'A
X2
[(X1-X2~~Y1 -Y2)
-(2,-Z2)J
TRANSLlNEAA
MULTIPLIER
Y,
Y2
ELEMENT
OUT
z,
Z2
PRODUCT DESCRIPTION
The AD534 is a monolithic laser trimmed four·quadrant multi·
plier divider having accuracy specifications previously found
only in expensive hybrid or modular products. A maximum
multiplication error of ±O.2S% is guaranteed for the ADS 34L
without any external trimming, Excellent supply rejection, low
temperature coefficients and long term stability of the on-chip
thin film resistors and buried zener reference preserve accuracy
even under adverse conditions of use. It is the first multiplier
to offer fully differential, high impedance operation on all inputs, including the Z-input, a feature which greatly increases
its flexibility and ease of use. The scale factor is pretrimmed
to the standard value of 10.00V; by means of an external resistor, this can be reduced to values as low as 3V.
PROVIDES GAIN WITH LOW NOISE
The ADS 34 is the first general purpose multiplier capable of
providing gains up to X100, frequently eliminating the need
for'separate instrumentation amplifiers to precondition the
inputs. The ADS 34 can be very effectively employed as a
variable gain differential input amplifier with high common
mode rejection. The gain option is available in all modes, and
will be found to simplify the implementation of many functionfitting algorithms such as those used to generate sine and tangent. The utility of this feature is enhanced by the inherent low
noise of the ADS34: 90I.lV, rms (depending on the gain), a
factor of 10 lower than previous monolithic multipliers. Drift
and feedthrough are also su bstan tially reduced over earlier
designs.
The wide spectrum of applications and the availability of several grades commend this multiplier as the first choice for all
new designs. The ADS 34J (±1 % max error), ADS 34K (±O.S%
max) and ADS34L (±O.2S% max) are specified for operation
over the 0 to +70oC temperature range. The ADS34S (±1 % max)
and AD534T (±0.5% max) are specified over the extended
temperature range, -SSoC to +12S°C. All grades are available
in hermetically sealed TO-100 metal cans and TO-116 ceramic
DIP packages.
UNPRECEDENTED FLEXIBILITY
The precise calibration and differential Z-input provide a
degree of flexibility found in no other currently available multiplier. Standard MDSSR functions (multiplication, division,
squaring, square-rooting) are easily implemented while the
restriction to particular input/output polarities imposed by
earlier designs has been eliminated. Signals may be summed into the output, with or without gain and with either a positive
or negative sense. Many new modes based on implicit-function
synthesis have been made possible, usually requiring only external passive components. The output can be in the form of a
current, if desired, facilitating such operations as integration.
ANALOG MUL TlPLlERSIDIVIDERS 6-13
•
SPECIFICATIONS
ITA= +25"&, ±Vs=l5V, R;;::2kfl)
Model
Mln
ADS14J
Typ
Mu
Mln
ADSl4K
Typ
Max
ADS14L
Typ
Mln
MIX
Units
MULTIPLIER PERFORMANCE
(X,-X,)(Y,-Y,)
lOY
+Z,
Transfer Function
Total Error' (-lOV:s;X, Y-s + lOY)
TA""mtntomax
:1.0
Total Error vs Temperature
Scale Factor ErrOJ'
(SF= 10.OOOVNommair
Temperature-CoeffiCient of
Scaling Voltage
Supply ReJectlon (± ISV :!: 1V)
Nonimearity,X(X= 20Vpk·pk, Y= lOY)
Nonhneanty, Y(Y= 20V pk-pk, X = IOV)
Feedthrough 3 , X (Y Nulled,
X = 20V pk.pk 50Hz)
Feedthrough', Y (X Nulled,
Y = 20V pk·pk 50Hz)
Output Offset Voltage
Output Offset Voltage Onft
DYNAMICS
SmaIlSIgIlaIBW,(VOVFO Inn.)
1% Ampluude Error(CI.OAD = 1000pF)
Slew Rate (VOUT 20 pk-pk)
Senhng Tune (ro 1% • .6.Vo l/T=20V)
OUTPUT
Output Voltage Swmg
±1.0
±0015
±O.S
±O.OO8
%
%
%f'C
±0.25
::to I
±O.I
%
±0.02
±OOI
±0.4
±0.2
±0.01
,::to.OI
±O 2
±O I
±03
=0.15
",001
±5
200
"'0.01
",2
100
"'0.5
:30
%I"C
"'8.l
±0.005
±OOI
±0.1O
±0.005
±o.li
:0.1
%
:0.3
±O.OS
",0.12
%
±O.l
",IS
"'0.003
±2
100
:O.I
",10
%
:0.3
%
%
mV
~VI"C
MHz
kHz
V/,u
20
2
I
50
20
2
0.8
0.4
I
0.8
0.4
I
0.8
0.4
I
90
90
90
mV/nns
....V/rms
0.1
V
n
30
70
dB
I
SO
",11
Output Impeda.oce (fS;lkHz)
Output Shon Cireul[ Current
(RL=O, TA=mmtomax)
Amphfier Open LoopGam (f = 50Hz)
:0.25
± 1.5
±0022
I
50
20
2
NOISE
NOlse Spectral-Density SF = lOY
SF = 3\'"
Wideband NOise f "" 10Hz to 5MHz
f= 10Hz to 10kHz
(X,-X,)(Y,-Y,)
10V
+Z,
(X,-X,)(Y,-Y,)
lOY
+Z,
"'"
dl
01
01
30
30
70
70
~.
~vtVHi
~vtVHi
mA
INPUT AMPLIFIERS (X, Y and Z)
Signal Voltage Range (Dlff. orCM
Operating DdT)
Offset Voltage X, Y
Offset Voltage DnftX, Y
Offsct Voltage Z
Offset Voltage DnftZ
±12
:20
",30
200
60
CMRR
±IO
±12
=2
50
",2
100
=10
",5
100
",5
80
0.8
01
10
BtasCurrent
Offset Current
Differential Resistance
70
:15
70
90
0.8
01
10
2.0
:10
V
V
mV
dO
mV
±lO
±12
=2
50
",2
100
dO
~VI"C
~VI"C
dB
90
08
0.05
10
2.0
~A
2.0
0.2
~A
Mn
DIVIDER PERFORMANCE
TotaiErrorl(X= lOY, -lOVsZ:s: + IOV)
(X-IV, -IV,;Z,; + IV)
(Z,-Z,)
(Z,-Z,)
IOV (X,-X,) + Y,
(Z,-Z,)
lOY (XI ~X2)+ YI
Transfer Function (XI> X 2)
IOV (X 1-X 2)+YI
",075
±2.0
=035
±1.0
",0.2
%
:t08
%
±25
=10
±O 8
%
(O,IV:s:XsIOV, -lOVs
Z,;IOV)
SQUARE PERFORMANCE
Transfer Function
Total Error( -lOV:sXSIOV)
SQUARE·ROOTERPERFORMANCE
Transfer Function (ZI SZ2)
Total Error' (1 VsZslOV)
(X,-X,>,
---wy--+Z,
(X,-X,>,
---wv-+Z2
(X,-X,)'
---wv-+ Z2
±06
",o.3
+0.2
%
"'IOV(Z, - Z,) + X,
=10
"'IOV(Z, - Z,) + X,
=0.5
"'IOV(Z, - Z,) + X,
=025
%
POWER SUPPLY SPECIFICATIONS
Supply Voltage
Rated Performance
Operatmg
Supply Current
QUiescent
PACKAGE OPTIONS'
TO-IOO (H· lOA)
TO-1I6 (0-14)
",IS
±15
:18
=8
4
AD534JH
AD534JD
6
",8
4
AD534KH
AD534KD
:18
V
V
6
mA
=15
:18
6
",8
4
AD534LH
AD534LD
NOTES
IPtgUresgivenare percent o(fuJl scale, ± 10V(1 e ,001% = ImV),
2May be reduced down to 3V U!ungeztemal resIStor between - Vs and SF
31rreduclblecomponentdue to nonhneanty excludes effect of offsets
4Usmgexternal re5JstoradJustedtogave SF = 3V,
5See functtonal block dugram forde(uubonofsectlDRS.
'See Section 16forpackage oudme mfonnauon
SpeaftcaUODS subject tochangeWithout DOnee
6-14 ANALOG MULTIPLIERS/DIVIDERS
SJXClficarlons shqwn lD boldface are tested on all producuon uruts at fmal e1ectrl
cal rest. Results from those tests are used to cakulatc outgomg quabty levels All
mm and max speaflCaboIUI are guaranteed, although only those shown lD
boldface are tested on aU producbon UDIts.
M
Model
Min
ADS34S
Typ
Max
Min
ADS34T
Typ
Max
Units
M UL TIPLIER PERFORMANCE
Transfer Functton
(X,-X,)(Y,-Y,)
lOY
+Z2
(X,-X,)(Y,- Y,)
IOV
+Z2
±1.0
±2.0
±O.O2
±0.5
±1.0
±0.01
%
%
±O.OO5
%/OC
Total Error l (-I'OV~X, Y~ + IOV)
TA""mmlomax
Total Error vs Temperature
Scale Factor Error
(SF = 1O.OOOV Nommali
Temperature-Coefficient of
ScahngVoltage
Supply Re)ectlOn( ± 15V ± IV)
Nonlmeanty, X (X "" 20Vpk-pk. Y = 10V)
Nonhnearny, Y (Y =20Vpk-pk,X "" 10V)
Feedthrough 3 , X (Y Nulled,
X ~ 20V pk-pk 50Hz)
Feedthrough 3 , Y (X Nulled,
Y ~ 20V pk-pk 50Hz)
Omput Offset Voltage
Output Offset Voltage Dnft
~O
25
:t.O.1
~0.02
%/oC
%
~0.4
~O 01
±O2
~0.2
~o
I
±O.3
±O.l
%
%
%
~0.3
~O
15
±O.3
%
~O
01
±O.l
±IS
300
%
±O.OI
~O
01
~5
±30
~2
SOO
mV
j.lV/oC
DYNAMICS
SmallSlgnaIBW,(VOUT=O 1 rms)
I%AmphtudeError(C LOAD = lOOOpF)
Slew Rate (V OCT 20 pk-pk)
':ienhngTlme(to 1%. AV OUT "" 20V)
50
20
2
I
50
20
2
I"
NOISE
NOIse Spectral-Densuy SF = lOY
SF =3V 4
Wldeband NOIsef= 10Hz to 5MHz
f = 10Hz to 10kHz
O.S
04
10
90
OS
04
10
90
mV/rms
,...Vlrms
0.1
01
V
n
30
70
30
70
rnA
dB
OUTPUT
Output Voltage SWing
Omput Impedance (fs 1kHz)
Outpul Shot( CirCUll Current
RL=O, TA = mm to max)
AmphfierOpen Loop Gam (f = 50Hz)
INPUT AMPLIFIERS (X, Y and Z)'
Signal Voltage Range (Duf. or CM
Operatmg Duf )
Offset Voltage X, Y
Offset Voltage DrtftX, Y
Offset VohageZ
Offset Voltage Drift Z
CMRR
Bias Current
Offset Current
Duferenual ReSistance
\
~V/v'Hz
~V/v'Hz
±Il
±ll
~IO
~10
~
± 12
~S
~5
SO
O.S
0.1
10
12
~2
±20
100
60
MHz
kHz
V/J.lS
±10
150
±30
500
~2
70
Z.O
90
OS
±lS
300
V
V
mV
,...vrc
mV
~V/oC
dB
2.0
0.1
10
~A
~A
Mn
DIVIDER PERFORMANCE
(Z,-Z,)
10V eX \_X 2)+Y j
Transfer Funcuon(X J > X 2 )
(Z2- Z \)
lOY (X,- X 2) + Y 1
~0.75
Total Error l (X = lOV, -IOVsZs + 10V)
eX-IV, -IVsZs '-IV)
eO.lVsXslOV, -IOVs
ZslOV)
~2.0
~25
~O
35
± 1.0
%
%
~IO
%
SQUARE PERFORMANCE
----wv- +Zz
Transfer Function
Total Error( -lOVsXslOV)
SQUARE-ROOTER PbRFORMANCE
Transfer Function (Z\ sZ2)
Total Error l (l VsZSIOV)
POWER SUPPLY SPECIFICATIONS
Supply Voltage
Rated Performance
Operatmg
Supply Current
Quiescent
PACKAGE OPTIONS'
TO-looPackage(H-IOA)
TO-1l6 Package (D-14)
(X,-X 1)2
(X\-X 2)2
----wv- +Z2
~0.6
~0.3
VIOV(Z2 - Z\) + X 2
±IO
VIOV(Z, -Z,)+ X,
~
~05
~
15
±22
~S
4
6
AD534SH
AD534SD
NOTES
IPlguresgtvenarepercentoffullscale, ± lOV(l.e.,O 01% = ImV).
2May be reduced down to 3V usmg external resistor between - Vs and SF.
3lrreduclblecomponentdue to nonhnearlty: excludes effect of offsets
4Usmgexternal resistor adJusted to give SF = 3V.
SSee funcnonal blockdJagram for deflIUuon of secuons
6See Section 16 for package outline mfonnatIon
SpecIfications sub,ect to change WithOut nonce.
%
%
15
~S
4
±22
V
V
6
rnA
AD534TH
AD534TD
Spectiicatlons shown In boldface are tested on aU production umts at final electncal test Results from those tests are used to calculate outgomg quality levels All
mm and max specIfications are guaranteed, although only those shown m
boldface are tested on all production UDlIS.
ANALOG MULTIPLIERS/DIVIDERS 6-15
CHIP DIMENSIONS AND BONDING DIAGRAM
DImensions shown in inches and (nun).
THE AD534 IS AVAILABLE IN LASER TRIMMED CHIP FORM, CONSULT THE CATALOG FOR DETAILS
ABSOLUTE MAXIMUM RATINGS
AD534J, K, L
AD534S, T
±18V
SOOmW
±22V
Supply Voltage
Internal Power Dissipation
Output Short-Cilcuit to Ground
Input Voltages, Xl Xz Y I Y Z Zl Zz
Rated Operating Temperature Range
Indefinite
±Vs
o to +70°C
Storage Temperature Range
Lead Temperature, 60s soldering
-65°C to +lS0°C
+300o C
FUNCTIONAL DESCRIPTION
Figure 1 is a functional block diagram of the AD534. Inputs
are converted to differential currents by three identical voltageto-current converters, each trimmed for zero offset. The product of the X and Y currents is generated by a multiplier cell
using Gilbert's translinear technique. An on-chip "Buried
Zener" provides a highly stable reference, which is laser trim- .
med to provide an overall scale factor of lOY. The difference between XY /SF and Z is then ap{llied to the high gain
output amplifier. This permits various closed loop configurations and dramatically reduces nonlinearities due to the input
amplifiers, a dominant source of distortion in earlier designs.
The effectiveness of the-new scheme can be judged from the
fact that under typical conditions as a multiplier the nonlinearity on the Y input, with X at full scale (±lOV), is ±O.005% of
F.S.; even at its worst point, which occurs when X= ±6.4V,
it is typically only ±O.05% of F.S. Nonlinearity for signals
applied to the X input, on the other hand, is determined almost entirely by the multiplier element and is parabolic in
form. This error is a major factor in determining the overall
accuracy of the unit and hence is closely related to the
device grade.
,,0-----.,
1--------0
+Vs
1--------0
-Vs
'---,-----'
_55°C to
+12S o C
TRANSFER FUNCTION
X,
*
Vo '" A [(Xl -
X2~~Yl - Y2)
- (Zl - Z21J
Y,
·Same as AD534J specs.
Y,
OPTIONAL TRIMMING CONFIGURATION
OUT
Z,
Z,
+Vs
Figure 1. AD534 Functional Block Diagram
470k
50k
~o--Wl.---""'-
TO APPROPRIATE
INPUT TERMINAL
lk
-Vs
6-16 ANALOG MULTIPLIERS/DIVIDERS
The generalized transfer function for the AD 5 34 is given by:
XI-X2)(YI-Y2)
~
VOUT=A
where
SF
~
-(Zl- Z2)
A = open loop gain of output amplifier, typically
70dB at de
x,
Y, Z = input voltages (full scale = ±SF, peak=
±1.25SF)
SF = scale factor, pretrimmed to 10.00V but
adjustable by the user down to 3V.
In most cases the open loop gain can be regarded as infinite,
and SF will be 10V. The operation performed by the AD534,
can then be described in terms of equation:
(XI-X2)(YI-Y2)= 10V(Zl- Z2)
The user may adjust SF for values between 10.00V and 3V by
connecting an external resistor in series with a potentiometer
between SF and -v s. The approximate value of the total resistance for a given value of SF is given by the relationship:
SF
RSF = 5.4K - - 10 - SF
Due to device tolerances, allowance should be made to vaty
RSF by ±25% using the potentiometer. Considerable reduction
in bias currents, noise and drift can be achieved by decreasing
SF. This has the overall effect of increasing signal gain without the customaty increase in noise. Note that the peak input
signal is always limited to 1.25SF (i.e., ±5V for SF = 4V) so the
overall transfer function will show a maximum gain of 1.25.
The performance with small input signals, however, is improved
by using a lower SF since the dynamic range of the inputs is
now fully utilized. Bandwidth is unaffected by the use of this
option.
, Supply voltages of ±15V are generally assumed. However, satisfactory operation is possible down to ±8V (see curve 1). Since
all inputs maintain a constant peak input capability of ±1.25SF
some feedback attenuation will be necessaty to achieve output
voltage swings in excess of ±12V when using higher supply
voltages.
OPERATION AS A MULTIPLIER
Figure 2 shows the basic connection for multiplication. Note
that the circuit will meet all specifications without trimming.
X INPUT
±10V FS
±12V PK
>V,
X,
+15V
X,
OUTPUT, ±12V PK
OUT
• (X, - X2)(Y' - Val + Z2
10V
AD534
SF
Z,
Z,
Y INPUT
V,
OPTIONAL SUMMING
INPUT, Z, ±10V PK
V
V,
±lOV FS
±12V PK
I
I
.v,
-15V
shows the typical ac feedthrough with this adjustment mode.
Note that the Y input is a factor of 10 lower than the X input and
should be used in applications where null suppression is critical.
The high impedance Z terminal of the AD5 34 may be used to
sum an additional signJ into the output. In this mode the output
amplifier behaves as a voltage follower with a 1MHz small signal
bandwidth and a 20V/)J.s slew rate. This terminal should
always be referenced to the 'gtound point of the driven system,
particularly if this is remote. Likewise the differential inputs
should be referenced to their respective ground potentials to
realize the full accuracy of the ADS 34.
A much lower scaling voltage can be achieved without any
reduction of input signal range using a feedback attenuator as
shown in Figure 3. In this example, the scale is such that
VOUT = XY, so that the circuit can exhibit a maximum gain of
10. This connection results in a reduction of bandwidth to
about 80kHz without the peaking capacitor CF = 200pF. In
addition, the output offset voltage is increased by a factor of
10 making external adjustments necessaty in some applications.
Adjustment is made by connecting a 4.7Mn. resistor between
Zl and the slider of a pot connected across the supplies to
provide ±300mV of trim range at the output.
Feedback attenuation also retains the capability for adding a
signal to the output. Signals may be applied to the high impedX INPUT
±10V FS
±12V PK
x,
'V,
+15V
X,
OUTPUT, ±12V PK
=(X,-X2 )(Y'.Y2)
(SCALE = 1V)
OUT
AD534
90k
Z,
Z,
Y INPUT
±10V FS
±12V PK
10k
V,
V,
N,
OPTIONAL
PEAKING
CAPACITOR
CF '" 200pF
-15V
Figure 3. Connections for Scale-Factor of Unity
ance Z2 terminal where they are amplified by + 10 or to the
common ground connection where they are amplified by + 1.
Input signals may also be applied to the lower end of the 10kn.
resistor, giving a gain of -9, Other values of feedback ratio, up
to X100, can be used to combine multiplication with gain.
Occasionally it may be desirable to convert the output to a
current, into a load of unspecified impedance or dc level. For
example, the function of multiplication is sometimes followed
by integration; if the output is in the form of a current, a simple
cap,acitor will provide the integration function. Figure 4 shows
how this can be achieved. This method can also be applied in
squaring, dividing and square rooting modes by appropriate
choice of terminals. This technique is used in the voltage-controlled low-pass filter and the differential-input voltage-tofrequency converter shown in the Applications Section.
Figure 2. Basic Multiplier Connection
In some cases the user may wish to reduce ac feed through to
a minimum (as in a suppressed carrier modulator) by applying
an external trim voltage (±3OmV range required) to the X or Y
input (see Optional Trimming Configuration, page 3). Curve 4
ANALOG MULTIPLIERS/DIVIDERS 6-17
•
X INPUT
±10V F.S.
±12V PK
X,
~
X.INPUT
+
(DENOMINATOR) - - - , X ,
+10V FS
+12V PK
X2
+Vs
X,
OUT
v,
OUT
AD534
Z, ~~~~--~~-----l
lOUT
=
z, 1 - - - - - - - - ' {X'-~l!ci~'-Ya!·is
l
I
OPTIONAL
SUMMING INPUT
tlOV PK
INTEGRATOR ... T"
-Vs
i,
SF
I
_.l,_
Y,
Y,
OUTPUT, t12V PK
'" 10VIZa -Zd +
IX,-Xa)
CURRENT-SENSING
RiSTOR, RS, 2'f! MIN
A0534
Y INPUT
flOV F.S.
±12V PK
+15V
+Vsr-
Z-INPUT
(NUMERATOR)
tl0V FS, t12V PK
Z,
Y,
f~EA~~~~~ ~\~/9
I
I
V
Y,
~15V
-Vs
Figure 4. Conversion of Output to Current
OPERATION AS A SQUARER
Operation as a squarer is achieved in the same fashion as the
multiplier except that the X and Y inputs are used in parallel.
The differential inputs can be used to determine the output
polarity (positive for Xl = Y I and X2 = Y 2, negative if either
one of the inputs is reversed). Accuracy in the squaring mode
is typically a factor of 2 better than in the multiplying mode,
the largest errors occurring with small values of output for
input below IV.
Since the output will be near +10V, it should be ac-coupled for
this adjustment. The increase in noise level and reduction in
bandwidth preclude operation much beyond a ratio of 100
to 1.
If the application depends on accurate operation for inputs
that are always less than ±3V, the use of a reduced value of
SF is recommended as described in the FUNCTIONAL
DESCRIPTION section (previous page), Alternatively, a feedback attenuator may be used to raise the output level. This is
put to use in the difference-of-squares application to compensate for the factor of 2 loss involved in generating the sum
term (see Figure 7).
As with the multiplier connection, overall gain can be introduced by inserting a simple attenuator between the output and
Y2 terminal. This option, and the differential-ratio capabili~
of the AD534 are utilized in the percentage-computer apphcation shown in Figure 11. This configuration generates an output proportional to the percentage deviation of one variable
(A) with respect to a reference variable (B), with a scale of one
volt per percent.
The difference-of-squares function is also used as the basis for
a novel rms-to-dc converter shown in Figure 14, The averaging
filter is a true integrator, and the loop seeks to zero its input,
For this to occur, (VIN)2 - (VOUT)2 = 0 (for signals whose
, period is well below the averaging time-constant), Hence VOUT
is forced to equal the rms value of VIN' The absolu te accuracy
of this technique is very high; at medium frequencies, and for
signals near full scale, it is determined almost entirely by the
ratio of the resistors in the inverting amplifier, The multiplier
scaling voltage affects only open loop gain, The data shown is
typical of performance that can be achieved with an ADS HK,
but even using an ADSHJ, this technique can readily provide
better than 1% accuracy over a wide frequency range, even for
crest-factors in excess of 10.
OPERATION AS A SQUARE ROOTER
The operation of the ADS 34 in the square root mode is shown
in Figure 6, The diode prevents a latching condition which
could occur if the input momentarily changes polarity. As
shown, the output is always positive; it may be changed to a
negative output by reversing the diode direction and interchanging the X inputs, Since the signal input is differential, all
combinations of input and output polarities can be realized,
but operation is restricted to the one quadrant associated with
each combination of inputs.
OPERATION AS A DIVIDER
The AD53S, a pin for pin functional equivalent to the AD534,
has guaranteed performance in the divider and square-rooter
configurations and is recommended for such applications.
Figure S shows the connection required for division, Unlike
earlier products, the ADS 34 provides differential operation on
both numerator and denominator, allowing the ratio of two
floating variables to be generated, Further flexibility results
from access to a high impedance summing input to Y 1, As with
all dividers based on the use of a multiplier in a feedback loop,
the bandwidth is proportional to the denominator magnitude,
as shown in curve 8,
Without additional trimming, the accuracy ofthe AD534K and
L is sufficient to maintain a 1% error over a 10V to 1 V denOIpinator range, This range may be extended to 100: 1 by simply
reducing the X offset with an externally generated trim voltage
(range required is ±3.5mV max) applied to the unused X input
(see Optional Trimming Configuration). To trim, apply a
ramp of +100mV to +V at 100Hz to both Xl and Zl (if X2
6-18 ANALOG MUL TIPLIERSIDIVIDERS
Figure 5. Basic Divider Connection
is used for offset adjustment, otherwise reverse the signal polarity) and adjust the trim voltage to minimize the variation in
the output,'
OUTPUT, :t12V PK
=.jl0V(Za- Z,!+X2
REVERSE
THISANDX
INPUTS FOR
NEGATIVE
OUTPUTS
+15V
+Vs
X,
X,
OPTIONAL
SUMMING
INPUT, x,
:tl0V PK
I
I
I
I
I
~
RL BE
(MUST
PROVIDED)
I
I
V
OUT
A0534
SF
Z,
I
I
V
Z,
+
Z-INPUT
10V FS
12VPK
Y,
Y,
-Vs
-15V
Figure 6. Square-Rooter Connection
In contrast to earlier devices, which were intolerant of capacitive loads in the square root modes, the ADS 34 is stable with
all loads up to at least 1000pF. For critical applications, a small
adjustment to the Z input offset (see Optional Trimming Configuration) will improve accuracy for inputs below 1 V.
'See the ADS 3 S Data Sheet for more details,
Applications Section
The versatility of the ADS 34 allows the creatiye designer to
implement a variety of circuits such as wattmeters, frequency
doublers and automatic gain controls to name but a few. These
applications along with many other such "idea stimulators"
are described in detail in the Multiplier Application Guide,
available upon request from Analog Devices.
x,
+Vs ~+15V
MODU LATtON
INPUT,±EM
X,
OUT
AD534
SF
Z,
OUTPUT
U
=
1±~
Ecsmwt
Z'r--
CARR IER INPUT
Ec sin wt
V,
_Vs~5V
~v'
THE SF PIN OR A Z-ATTENUATOR CAN BE USED TO PROVIDE OVERALL SIGNAL
AMPLIFICATION OPERATION FROM A SINGLE SUPPLY IS POSSIBLE, BIAS Y2 TO Vs/2.
v,
.A+B
v,
-Vs
Figure 10_ Linear AM Modulator
~15V
Figure 7. Difference-of-Squares
9k
x,
+Vs
+15V
x,
Ik
OUTPUT = (l00V) A ~ B
OUT
AD534
(1% PER VOL TI
Z,
Sf
A INPUT
z,
B INPUT
(+VE ONLY)
--------1 v,
I±l
v,
-15V
v,
-Vs
SIGNAL INPUT,
Es. ±5V PK
----__""""v,
NOTES
1)
2)
3)
4)
-Vs
-15V
GAIN IS Xl0 PER VOLT OF fe. ZERO TO X50
WIDEBAND (10Hz - 30kHz) OUTPUT NOISE IS 3mV RMS, TVP
CORRESPONDING TO A F S SIN RATIO OF 70dB
NOISE REFERRED TO SIGNAL INPUT, WITH Ec '" ±5V, IS 60~V RMS, TYP
BANDWIDTH IS DC TO 20kHz, -3dB, INDEPENDENT Of GAIN
OTHER SCALES, FROM 10% PER VOLT TO 0.1% PER VOLT CAN BE OBTAINED BY
ALTERING THE FEEDBACK RATIO
Figure 11. Percentage Computer
Figure 8. Voltage-Controlled Amplifier
x,
+Vs
r
+15V
x,
10k
+15V
t-
x,
OUT
18k
OUTPUT'" (lOV) Sin 8
~~34
WHERE 8 = ~
z,
SF
OUT
~
IDV
z,
INPUT, £8
OTO+l0V
-Vs
-15V
Z'r--
1+V
WHERE y =
(l~V)
Z'r--
INP UT, Y
±10V F S
v,
OUTPUT,±5V PK
= (10V)-'1-
AD534
SF
v,
Ws
x,
v,
r-
v
'
.Vs~V
USING CLOSE TOLERANCE RESISTORS AND AD534l, ACCURACY OF FIT IS WITHIN
±O.5% AT ALL POINTS. 8 IS IN RADIANS.
Figure 9. Sine-Function Generator
Figure 12. Bridge-Linearization Function
ANALOG MUL TIPLIERSIDIVIDERS 6-19
•
+I6V
x,
+v,
20k
2k
ADJ IkHl:
+1"
INPUT
X,
&V RMS FS
:tlOYP£AK
OUT
OUTPUT,
A. . . .
t16YAPPROX
OUTPUT
OTO+6V
::-+':=:-:--IY,
CONTROL INPUT. Ec
"'kH~PER
10DmVTO lOV
Y,
VOLT
WITH VALUES SHOWN
·V,
Y,
.Vlf-.....---"M--o
Vz
-16V
CALIBRATION PROCEDURE.
WITH EC -1.GY,ADJUST POT TO SET f .. 1.DOOkHz.WITH EC" S.OV, ADJUST TRIMMER
CAPACITOR TO SET f .. 8.000kHz. LINEARITY WILL TYPICALL V BE WITHIN 1:0.1% OF
F.S. FOR ANY OTHER INPUT.
DUE TO DELAYS IN THE COMPARATOR, THIS TECHNIQUE IS NOT SUITABLE FOR
MAXIMUM FReQUENCIES ABOVE 10kHz. FOR FREQUENCIES ABOVE 10kHz THE
AD637 VOLTAGE TO FREQUENCY CONVERTER IS RECOMMENDED
A TRIANGLE·WAVE OF t6V PK APPEARS ACROSS THE O.01"F CAPACITOR; IF USED
AS AN OUTPUT, A VOLTAGE·FOLLOWER SHOULD BE INTERPOSED.
CALIBRATION PROCEDURE.
WITH 'MODE' SWITCH IN 'AMS + DC' POSITION, APPLY AN INPUT OF +l.00VDC. ADJUST
ZERO UNTIL OUTPUT READS SAME AS INPUT. CHECK FOR INPUTS OF :t1OV. OUTPUT
SHOULD BE WITHIN:tOO6% I6mVI
ACCURACY IS MAINTAINED FROM 60Hz to 100kHz, AND IS TYPICALLY HIGH BY
0.5% AT 1MHz FOR VIN .. 4V RMS (SINE, SQUARE OR TRIANGULAR WAVE)
PROVIDED THAT THE PEAK INPUT IS NOT EXCEEDED, CREST·FACTORS UP TO AT
LEAST TEN HAVE NO APPRECIABLE EFFECT ON ACCURACY.
INPUT IMPEDANCE IS ABOUT 1Okn, FOR HIGH C1OMOI IMPEDANCE, REMOVE MODE
SWITCH AND INPUT COUPLING COMPONENTS.
FOR GUARANTEED SPECIFICATIONS THE AD536A AND AD636 IS OFFERED
AS A SINGLE PACKAGE RM8-TO-DC CONVERTER
Figure 14. Wideband, High-Crest Factor,
RMS-to-DC Converter
Figure 13. Differential-Input Voltage-to-Frequency Converter
Typical Performance Curves
(typical at +25°C, with Vs =±15V dc, unless otherwise stated)
/
/I
OUTPUT··'7 k'.NPUTS.
/
4
'l
8
......
V
Sf •
I'--..
,ov
/
--- r-12
.
20
POSITIVE OR NEGATIVE SUPPLY -Volts
.........
r---
-r--r- -
~NGVOLTAGE=1OV
-
.........SCALING VOLTAGE· 3V
.
eo
,...
I ..
TEMPERATURE _·c
Curve 1. InputlOutputSignal Range Vs. Supply Voltages
6-20 ANALOG MUL TIPLIERSIDIVIDERS
Curve 2. Bias CurrenlB Vs. Temperature (X, Y or Z inpulB)
I"--t'-
"'-
" "-
TYPICAL/
FOR ALL
INPUTS
30
CONDITIONS
10Hz - 10kHz BANDWIDTH
'"
r-..
V
/
"
..
Curve 6. Wideband Noise Vs. Scaling Voltage
1000
JJJJL Ij
~~
V
II
r-..
1--1-
r--., r\
\.
r"-r-,
FEEOTHROUGH
-~
V
~\
CF=O
,.;
1,\
L.J>1\ ~'-'-i
~Cl"l000pF
I
I
CF"2OOpF
'\
,}"HX10
FEEDBACK
CONNECTION
\TTE~OR
-20
"
11<
FREQUENCY - Hz
..
•
I/"":"+~' }2kO
CL ",OOOpf
V
"
/
"'k
Curve 3. Common-Mode-Rejection-Ratio Vs. Frequency
I-
/
I
,
'00
/'
V
/'
I
100k
'OM
FREQUENCY - Hz
Curve 7. Frequency Response as a Multiplier
Curve 4. AC Feedthrough Vs. Frequency
15
i"-r-.
-I"--
-
~X-l00mVdC
SCALING VOLTAGE "lOV
VZ" lOmVrrm
JNGllJl
.
"
1\1\
r"-iI
Vx "lVdc
Vz .. l00mV..".
1\
r\.
"
11<
FREQUENCV _ Hz
1\[ :~T
lOOk
10M
FREQUENCY - Hz
Curve 6. Noise Spectral Density Vs. Frequency
Curve 8. Frequency Response Vs. Divider Denominator
Input Voltage
ANALOG MUL TIPLIERSIDIVIDERS 6-21
6-22 ANALOG MUL TIPLIERSIDIVIDERS
11IIIIIIII ANALOG
WOEVICES
Real-Time Analog
Computational Unit (ACU)
AD538 I
FEATURES
VOUT
AD538 FUNCTIONAL BLOCK DIAGRAM
= V y (~)m Transfer Function
Wide Dynamic Range (Denominator) -1000:1
Simultaneous Multiplication and Division
Resistor-Programmable Powers & Roots
No External Trims Required
Low Input Offsets <100,..V
Low Error ±0.250/0 of Reading (100:1 Range)
+2Vand + 10V On-Chip References
Monolithic Construction
APPLICATIONS
One- or Two-Quadrant MultJDiv
Log Ratio Computation
Squaring/Square Rooting
Trigonometric Function Approximations
Linearization Via Curve Fitting
Precision AGC
Power Functions
PRODUCT DESCRIPTION
The ADS38 is a monolithic real-time computational circuit
which provides precision analog multiplication, division and
exponentiation. The combination of low input and output offset
voltages and excellent linearity results in accurate computation
over an unusually wide input dynamic range. Laser wafer trimming
makes multiplication and division with errors as low as 0.2S% of
reading possible, while typical output offsets of lOOILV or less
add to the overall off-the-shelf performance level. Real-time
analog signal processing is further enhanced by the device's
400kHz bandwidth.
The ADS38's overall transfer function is Vo =Vy (VzNx:r.
Programming a particular function is via pin strappjng. No
external components are required for one quadrant (positive
input) multiplication and division. Two quadrant (bipolar
numerator) division is pOssible with the use of extemallevel
shifting and scaling resistors. The desired scale factor for both
multiplication and division can be set using the on-chip + 2V or
+ 10V references, or controlled externally to provide simultaneous
multiplication and division. Exponentiation with an m value
from 0.2 to S can be implemented with the addition of one or
two external resistors.
Direct log ratio computation is possible by utilizing only the log
ratio and output sections of the chip. Access to the multiple
summing junctions adds further to the ADS38's flexibility.
Finally, a wide power supply range of ±4.SV to ± 18V allows
operation from standard ± SV, ± 12V and ± ISV supplies.
The ADS38 is available in two accuracy grades (A and B) over
the industrial ( - 2SoC to + 8S0C) temperature range and one
grade (S) over the military ( - 55°C to + 12S°C) temperature
range. The device is packaged in an 18-pin TO-li8 hermetic
side-brazed ceramic DIP.
PRODUCT HIGHLIGHTS
1. Real-time analog multiplication, division and exponentiation.
2. High accuracy analog division with a wide input dynamic
range.
3. On-chip + 2V or + lOY scaling reference voltages.
4. Both voltage and current (summing) input modes.
S. Monolithic construction with lo",:er cost and higher reliability
than hybrid and modular circuits.
ANALOG MUL TlPLlERSID/VIDERS 6-23
•
SPECIFICAli 0NS (vs =
± 15V, TA = 25"& unless othelWise specified)
ADS3SAD
Parameters
Min
Conditions
ADS3SBD
Max
Typ
Min
ADS3SSD
Max
Typ
Min
Max
Typ
Units
MULTIPLIERIDIVIDER
PERFORMANCE
Nominal Transfer
Function
4OOJ,lA'2:I x,I y,I Z 2 O
Total Error Terms
100: I Input Range'
Vz~lOVx,m=
Wide DynamiC Rangel
Vo~25k!lx
100mV"Vx"lOV
lOOmV"Vy"lOV
100mVsVz " lOY
Ti\
lOmV"VxslOV
ImV"Vy"IOV
OV"Vz"lOV
Exponent (m) Range
Ti\=TmmtoTmax
Vy~O, Vc~
FREQUENCY RESPONSE
Slew Rate
Small Signal Bandwtdth
I;;
Vo~2Sk!lx
Iy
I;;
CZf
Vo~2Sk!lx
Iy
I;;
CZf
±1
±500
±0.2S
± 100
±O.5
±2S0
±0.5
±200
±I
±4S0
±2
±7S0
±O.S
±3S0
±1
±SOO
± 1.25 :!:2.5
±750 ±1000
% of Readmg +
±I
±200
± 100
±2
±SOO
±2S0
±O.S
± 100
±7S0
±1
±2S0
±lS0
±I
±200
±200
±2
±SOO
±2S0
%ofReadmg +
f'V +
f'Vx (Vy + Vz)lVx
±1.5
±450
±450
±3
±7S0
±7S0
±I
±350
± 350
±2
±SOO
±SOO
±2
±7S0
±750
±4
±lOOO
±1000
%ofReadmg +
f'V +
f'V x (Vy + Vz)lV x
±1
±SOO
% ofReadmg
f'V
f'V
5
-600mV,'
±200
±4S0
Rl. ~ 2kll
-II
5
±SOO
±750
±11
10
0.2
5
± 100
± 350
-11
5
10
1.4
400
100mV"Vy , Vz,
VxslOV
±2S0
±500
+11
0.2
5
±200
±750
10
f'V
f'V
V
mA
1.4
400
V/f's
kHz
-11
5
1.4
400
±SOO
±1000
+11
VOLTAGE REFERENCE
Accuracy
Additional Error
VREF ~ lOY or 2V
TA=TmmorTmax
Output Current
VREF~
Power Supply Rejection
+2V=VREF
+ lOV~VREF
::!:
POWER SUPPLY
Rated
Operating Range 3
PSRR
+
±O.S
±200
0.2
Ti\=TmmlOTmax
Output Voltage Swing
Output Current
CT
1.0
TA=TmmtoTmax
OUTPUT
CHARACTERISTICS
Offset Voltage
Iy
VX
VO~Vy (Vzf
1.0
= TmlntoTmax
Vz~IOVx,m=
VX
. VO~Vy (Vzf
VO~Vy (Vzf
Vx
lOV2V x , V y, V z :2:0
lOVt02V
±25
±20
1
2.5
:::!::4.5V~Vs$::!:
18V
I3Vs;Vs $::!: 18V
300
200
RL ~ 2kll
±4 5V 100: 1), the ADS38 has a more detailed error specification
which is the sum of three components: a percent of reading
term, an output offset term and an input offset term for the Vyl
The ADS 38's error sources do not follow the percent of full-scale Vx log ratio section. A sample application of this specification,
approach to specification, thus it more optimally fits the needs
taken from the chart below, for the ADS38AD with Vy = IV,
of the very wide dynamic range applications for which it is best Vz = loomV and Vx = IOmV would yield a maximum error
suited. Rather than as a percent of full scale, the ADS 38's error of ±2.0%ofreading ±Sooll-V ±(lV + loomV)/lOmV x
2S0Il-Vor ±2.0% ofreading ±S00Il-V ± 27.SmV. This example
as a multiplier or divider for a 100:1 (IOOmV to lOY) input
range is specified as the sum of two error components: a percent illustrates that with very low level inputs the ADS 38's incremental
of reading (ideal output) term plus a fixed output offset. Following gain (Vy + Vz)Nx has increased to make the input offset contribution to error substantial.
this format the ADS 38AD, operating as a multiplier or divider
AD538 SAMPLE ERROR CALCULATION CHART (worst case)
Vy
Vz
Ideal
Vx
Input Input Input Output
(in V) (in V) (in V)
(in V)
100:1
INPUT RANGE
Total Error =
±%rdg
±OutputVos
WIDE
OYNAMIC
RANGE
Total Error =
±%rdg
± Output Vos
±InputVos x
(Vy+ Vz)Nx
Total Offset % of Reading
Error Term
Error Term
(inmV)
(inmV)
Total Error
Summation
(inmV)
Total Error Summation
as a % of the Ideal
Output
10
10
10
10
0.5 (AO)
0.25 (BO)
100 (AO)
50 (BO)
100.5 (AO)
50.25 (BO)
1.0 (AO)
0.5 (BO)
10
0.1
0.1
10
0.5 (AO)
0.25 (BO)
100 (AD)
50 (BO)
100.5 (AD)
50.25 (BO)
1.0 (AD)
0.5 (BO)
I
I
I
I
0.5 (AO)
0.25 (BO)
10 (AO)
5 (BO)
10.5 (AO)
5.25 (BO)
1.05 (AO)
0.5 (BO)
0.1
0.1
0.1
0.1
0.5 (AO)
0.25 (BO)
I (AO)
0.5 (BO)
1.5 (AO)
0.75 (BO)
1.5 (AO)
0.75 (BO)
I
0.10
0.01
10
28 (AO)
16.75 (BO)
200 (AO)
100 (BO)
228 (AO)
116.75 (BO)
2.28 (AO)
\.17 (BO)
10
0.05
2
0.25
1.76 (AO)
I (BO)
5 (AO)
2.5 (BO)
6.76 (AO)
3.5 (BO)
2.7 (AO)
1.4 (BO)
5
0.01
O.oI
5
125.75 (AO)
75.4 (BO)
100 (AO)
50 (BO)
225.75 (AO)
125.4 (BO)
4.52 (AO)
2.51 (BO)
10
0.01
0.1
I
25.53 (AO)
15.27 (BO)
20 (AO)
10 (BO)
45.53 (AO)
25.27 (BO)
4.55 (AO)
2.53 (BO)
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . .
Internal Power Dissipation . . .
Output Short Circuit-to-Ground
Input Voltages Vx , Vy , Vz ..
Input Currents lx, Iy , Iz, 10 . . . . .
Operating Temperature Range
Storage Temperature Range.
Lead Temperature, Storage . .
. . ±I8V
. 2S0mW
Indefinite
(+Vs-IV), -IV
. . '.' . . . ImA
- 25°C to + 85°C
- 65°C to + 150°
. 60 sec, + 300°C
ANALOG MUI. TlPLlERSIDIVIDERS 6-25
5.
1000
...
...
...
/
r---...
r-- :::::
"
.
-55
-40
~T
-20
..... ~
20
40
60
"
V
V
./'
120.
5.
1
C
~
4.
£i
~
3.
~
0
~
!:l
2'
<
,.
1
% OF jEADING
•
•
80, 100
125
%
""--
20
1000
"0
0
...
/
OFFSE\
400
20
40
60
80
~
£i
80
100
2"
•
125
~
~
100.
4.
800
/
30
~
~
~
~
~
,
~
;,
•
20
10
"
I'-...
•
125
100
5.
i
200
%OFt!ADING
-20
c
il
V
..........
-40
60
~
,<
Multiplier Error vs. Temperature
(1 Om V < Vx , Vy, Vz s 100mV)
5.
-55
40
T
400
TEMPERATURE -"C
Multiplier Error vs. Temperature
(100mV < Vx , Vy, Vz s 10V)
•
~
7
V
20
~
/ ... ~
OF READI[;7
I(
-.... t--
40
55
g
800
V v V:ClET-
" l"-
TEMPERATURE - 'C
10
...
/
0
,
2••
••
% OF READING
... ~
V 1/ ...
/
~,
~
~
0
~
..........
-40
-55
0
r--...
./
'-
-20
/ ~
,/
20
40
60
;,
200
OFI'
80
100
TEMPERATURE _·c
TEMPERATURE - "C
Divider Error vs. Temperature
(100mV < Vx , V y, Vz s10V)
Divider Error vs. Temperature
(10m V s Vx , Vy , Vz s 100mV)
•
125
15.
V x =10V
t-+_++tt--+-f-t-++--l~:~~~+5V SIN Nt VOLTS
V, IOV
Vv=5V +5V SIN
V;z=OV
I
,,,t VOLTS
f--
~
/
100
10k
INPUT FREQUENCY IN Hz
lOOit'
•
1
1M
I
100
Vz Feedthrough vs. Frequency
I
1k
10k
INPUT FREQUENCY IN Hz
lOOk
1M
Vy Feedthrough vs. Frequency
,•• r--------------------r----------,
~
~
400kHzr--t~~~~--_+--~~++--~--+_~~
/~
~-+-++,;--+--++++-+-+-~~
~
V y =10Vde,Vz =V",+005Vx SINwt
FOR THE FREQUENCY RANGE OF 10Hz
TO 100kHz THE TOTAL RMS OUTPUT
NOISE, eo, FOR A GIVEN BANDWfDTH
Bw, IS CALCULATED 80 '"'en VBvii
~
10
1-------,-------:
~
~
~~ l00kHZ~=+==:t:t~===t==~~tt==~==t=~~
l-
i 40kHz 1-_+--++,;--_+--++++--+-+_+-1~
...
10kHz ' - - - ' -__-'--'--'--'__--L.__-'--'-J...L__-'-_'-.J......U
01
10
IO'
DENOMINATOR VOLTAGE, VI( IN VDC
Small Signal Bandwidth vs Denominator Voltage
(One-Quadrant MultlDiv)
6-26 ANALOG MUL TIPLIERSIDJVIDERS
01
10
DC OUTPUT VOLTAGE, IN VOLTS
1kHz Output Noise Spectral Density vs. dc Output Voltage
function eqnals:
VZ\m
Vo = Vy ( 'Vx)
where 0.2
7V
",4.2
Vx= +3V, Vy=O
(T~.toTmLl
Power Supply Sensttivity
±4.2
U.2
400
10
5
10
2
Vx= +3V, Vy=O
400
10
5
5
2
30
20
400
10
5
IS
2
20
10
30
20
35
CONTRuLINr~uT,
x
Nominal Full.ScaIe Input
Operational Range, Degraded. Performance
Input Res1stance l
Off'ser:VoJl8ge
(TllllJltoTmaJ
Power Supply SensttlVlty
Gain
Absolute GamError
(Tmm toT
CURRENTOUTPUT t
Full·Scale Output Current
Peak OutputCurrent
Output Offset Current
Output Offset Volrage'
Output Res!stance l
_>
+3.0
500
I
3
30
(Figure2)
Vx= +O.lVto +3 OVand
Vy=::!;lV
Vx=+3V,Vy=::!;2V
Vx = +3.3V, Vy = ±SV, Vs= ±7.SV
Vx=O, Vy=O
FJgW'el, Vx=O, Vy=O
+3,0
+3.0
+3.2
+3.2
0.2
0.3
±I
±1.8
0.2
3
1.2
±2
4
5
V
V
n
mV
mV
0.4
0.5
dB
dB
+3.2
500
I
2
4
SUO
I
2
2
30
01
0.15
0.4
±I
±2.8
0.2
3
1.2
±2
1.5
10
~VN
30
0.2
02
0.25
±2
1.5
10
±I
±28
0.2
3
1.2
mA
mA
1.5
10
,.A
mV
ill
ScaImg ResistOrs
CHI
CH2
VOLTAGE OUTPUTS, VW1 &Vwl
MultipberTransfer FuncbOD,
EltherChannel
Multlpber Scahng Voltage, Vu
Zl,WltoCHI
Control Feedthrough
TmlRtoTmax
ill
ill
6
6
(FIgUre 2)
Vw
0.98
Accuracy
(Tmm toT_)
Power Supply SenslUvity
Total Multiphcabon Error3
Tnun toT_
6
6
6
6
Zl,WltoCHl
Vx< = + 3V, - lV------v
, "- .....
I!i
m 0 I--
I
+0.1
+1
CONTROL VOLTAGE - Vx
+'0
Figure 3a. Maximum ae Gain Error Boundaries
Distortion is a function of the signa1 input level (Vy) and the
control input (Vx). It is also a function of frequency, although
in practice the op amp will generate most of the distortion at
frequencies above 100kHz. Figure 3b shows typical results at
f = 10kHz as a function of Vx with Vy = 0.5 and 1.SV rms.
02~--------~--------~---------'
f=10kHz
=
-VX V Y1
v,, ___--I
>-----_vwz =
-VxVva
0~0--------~'----------~2--------~
CONTROL VOLTAGE - V
Figure 3b. Total Harmonic Distortion vs. Control Voltage
NOTE
ALL DECOUPUNG CAPACITORS ARE 0 47fLF CERAMIC
Figure 2. Standard Dual-Channel Multiplier
Viewed as a voltage-controlled amplifier, the decibel gain is
simply
G = 20 log Vx
where Vx is expressed in volts. This results in a gain of 10dB at
Vx = +3.162V,OdBatVx = +IV, -20dBatVx = +O.IV,
and so on. In many ac applications the output offset voltage (for
Vx = 0 or Vy = 0) will not be of major concern; however, it
can be eliminated using the offset nulling method recommended
for the particular op amp, with Vx = Vy = O.
6-34 ANALOG MUL TIPLIERSIDIVIDERS
In some cases it may be desirable to alter the scaling. This can
be achieved in several ways. One option is to use both the Z
and W feedback resistors (see' Figure I) in parallel, in which
case Vw = - Vx Vyl2. This may be preferable where the output
swing must be held at ±3V FS (±6.7SV pk), for example, to
allow the use of reduced supply voltages for the op amps. Alternatively, the gain can be doubled by connecting both c1wmels
in parallel and using only a single feedback resistor, in which
case Vw = -2Vx Yy and the full-scale output is ± 12V. Another
option is to insert a resistor in series with the control-channel
input, permitting the use of a large (for example, 0 to + lOy)
control voltage. A disadvantage of this scheme is the need to
adjust this resistor to accommodate the tolerance of the nominal
5000 input resistance at pin I. The signal channel inputs can
also be resistively attenuated to permit operation at higher values
ofVy , in which case it may often be possible to partially compensate
for the response roll-off of the op amp by adding a capacitor
across the upper arm of this attenuator.
Signal.Channel ac and Transient Response
The HF response is dependent almost entirely on the op amp.
Note that the "noise gain" for the op amp in Figure 2 is determined
by the value of the feedback resistor (6kfl) and the 1.2Skfl
control·bias resistors (Figure I). Op amps with provision for
external frequency compensation (such as the AD301 and ADSI8)
should be compensated for a closed·loop gain of 6.
The layout of the circuit components is very important if low
feedthrough and flat response at low values of Vx is to be msin·
tained (see GENERAL RECOMMENDATIONS).
For wide·bandwidth applications requiring an output voltage
swing greater than ± IV, the ADLHOO32 hybrid op-amp is
recommended. Figure 4a shows the HF response of the circuit
of Figure 2 using this amplifier with Vy = I V rms and other
conditions as shown in Table I. C F was adjusted for IdB peaking
at Vx = + IV; the - 3dB bandwidth exceeds 2SMHz. The
effect of signal feedthrough on the response becomes apparent
at Vx = +O.OIV. The minimum feedthrough results when Vx
is taken slightly negative to ensure that the residual control-channel
offset is exceeded and the dc gain is reliably zero. Measurements
show that the feedthrough can be held to - 9Od8 relative to full
20
I
I
I
-
I
Vx =l.00V
I
1
V x =O.316V
-10
dB
I
I
\.
\.
I
-
I
FEEDTHROUGH
-so
\
.......
V,,::O.01V
-40
v" =
-O.01V
/
1111/
-00
10M
1M
op Amp Supply Voltages
Op Amp Compensation Capacitor
Feedback Capacitor, C F
-3dBBandwidth,Vx~ +IV
Load Capacitance
HF Feedthrough,
Vx ~ -O.OIV,f ~ 5MHz
AD7U'
ADSS39'
ADLHOO32'
±ISV
None
None
900kHz
300n
Figure 5b shows the HF response for Figure Sa with the AD539
in a carefully-shielded son test-environment; the test system
response was first characterized and this background removed
by digital signal processing to show the inherent circuit response.
= lV
f _ 3
I
I I II
Vx = +OO32V
-so
CONTROL
I I I
'7~~T
V,(=+OO1V
-60
I I I
.6
I II
-7.
100'
lO:,.--3.3V). Secondly, it provides a choice of either non-inverting
or inverting responses, using either inputs VY1 or VY2 respectively.
In this circuit, the output of the op-amp will equal:
Vom =
Vx~\?-VY2) forVx>O
Hence, the ism is unity at Vx = +2V. Since Vx can over-range
to + 3.3V, the maximum gain in this configuration is about
4.3dB. (Note: If pin 9 of the AD539 is grounded, rather than
connected to the output of the 5539N, the maximum gain becomes
10dB.)
•
CH'
INPUT
V.
AD539
BASE
V"
COMMON
CH2
CH2
OUTPUT
INPUT
V"
Figure 7a. Low-Distortion Differential Configuration
01
~
21U
THOMPSON-CSF BAR-l0 OR SIMILAR SCHOTTKY DIODE
SHORT, DIRECT CONNECTION TO GROUND PLANE
-9V
o~,r-----------,------------;-----------,
.,.
Figure 8. A Wide Bandwidth Voltage-Controlled Amplifier
The - 3dB bandwidth of this circuit is over 50MHz at full gain,
and is not substantially affected at lower gains. Of course, when
Vx is zero (or slightly negative, to override the residual input
offset) there is still a small amount of capacitive feedthrough at
high frequencies; therefore, eXITeme care is needed in laying out
the PC board to minimize this effect. Also, for small values of
Vx , the combination of this feedthrough with the multiplier
output can cause a dip in the response where they are out of
phase. Figure 9a shows the ac response from the noninverting
,
Ii
u
0.02"
i
Vx "" +3162V
o~o----------~----------~--------~
"
VI(=+1V
CONTROL VOLTAGE - Vx
-10
Vx=+0316V
Figure 7b. Distortion in Differential Mode Using
ADLH0032 Op-Amp
-...,
~
~~
IIx'" +0 1V
~
Even lower distortion (0.01%, or - 80dB) has been measured
using two output op amps in a configuration similar to Figure 2
connected as virtual-ground current-summers (to prevent the
modulation effect). Note that to generate the difference output
it is merely necessary to connect the output of the CHI op amp
to the Z node ofCH2. In this way, the net input to the CH2 op
amp is the difference signal, and the low-distortion resultant
appears as its output.
Vx -+0032V
"i:::,
-40
V,,=+001V
-so
-60
,
1
vx -oo1v
V
....... 1-'"
V
~
10
FREQUENCY - MHz
Figure 9a. AC Response of the VCA at Different Gains
Vy=O.5VRMS
ANALOG MUL TIPLIERSIDIVIDERS 6-37
input, with the response from the inverting input, Vy2, essentially
identical. Test conditions: VY1 = 0.5V rms for values of Vx from
+ IOmV to +3.16V; this is with a 750 load on the output. The
feedthrough at Vx = -IOmV is also shown.
NUMERATOR 1
vw,
DENOMINATOR
INPUT. VJlO--+--~
The transient response of the signal channel at Vx = + 2V,
Vy=VOlIT = ± IV is shown in Figure 9b; with the VCA driving
a 75.0 load. The rise and fall-times are approximately 7ns.
NOTE DECOUPLE OP AMP SUPPlIES
NUMERATQR2
V_
Figure 10a. Two-Channel Divider with 1V Scaling
Y,,=OO1V
Figure 9b. Transient Response of the Voltage-Controlled
Amplifier Vx = +2 Volts Vy =::!:: 1 Volt
.
r--+.
V,,=OO32V
V,,=01V
A more detailed description of this circuit, including differential
gain and phase characteristics, is given in the application note
"Low Cost, Two Chip Voltage-Controlled Amplifier and Video
Switch" available from Analog Devices.
V,,=0316Y
V Il _1V
YIl_3112V
BASIC DMDER CONNECTIONS
Standard Scaling
-20
10k
The AD539 provides excellent operation as a two-quadrant
analog divider in wide-band wide gain-range applications, with
the advantage of dual-channel operation. Figure lOa shows the
simplest connections for division with a transfer function of
Vy = - VuVwlVx
Recalling that the nominal value of Vu is 1V, this can be
simplified to
Vy = -VwlVx
where all signals are expressed in volts. The circuit thus exhibits
unity gain for Vx = + IV and a gain of 40dB when Vx =
+O.OIV.
The output swing is limited to ± 2V nominal full-scale and
± 4.2V peak (using a - Vs supply ofat least 7.5V for the AD539).
Since the maximum loss is IOdB (at Vx = 3.162V), it follows
that the maximum input to Vw should be ±6.3V (4.4V rms)
for low distortion applications, and no more than ± B.4V (9.5V
rms) to avoid clipping. Note that offset adjustment will be needed
6-38 ANALOG MUL TIPLIERSIDIVIDERS
I I
1M
FREQUENCY _ Hz
10M
Figure 10b. HF Response of Figure 10a Divider
for the op amps to maintain accurate dc levels at the output in
high gain applications: the "noise gain" is 6VIVx, or 600 at Vx
= +O.OIV.
The gain-magnitude response for this configuration using the
ADLHOO32 op amps with nominally 12pF compensation (pins 2
to 3) and CF = 7pF is shown in Figure lOb; of course, other
amplifiers may also be used. Since there is some manufactdring
variation in the HF response of the op amps, and load conditions
will also affect the response, these capacitors should be adjustable:
5-15pF is recommended for both positions. The bandwidth in
this configuration is nominally 17MHz at Vx = +3.162V,
4.5MHz at Vx = + IV, 350kHz at Vx = +O.IVand 35kHz at
Vx = +O.OIV. The general recommendations regarding the use
of a good ground plane and power-supply decoupling should be
carefully observed.
Internally Trimmed
Precision I.C. Multiplier
AD632 I
r-IANALOG
WDEVICES
FEATURES
Pretrimmed to ±O.5% Max 4.Quadrant Error
All Inputs (X, Y and Zl Differential, High Impedance for
[(X 1 -X2 )(Y 1 -Y 2 1/10] +Z2 Transfer Function
Scale· Factor Adjustable to Provide up to X10 Gain
Low Noise Design: 90llV rms, 10Hz·10kHz
Low Cost, Monolithic Construction
Excellent Long Term Stability
APPLICATIONS
High Quality Analog Signal Processing
Differential Ratio and Percentage Computations
Algebraic and Trigonometric Function Synthesis
Accurate Voltage Controlled Oscillators and Filters
PRODUCT DESCRIPTION
The AD632 is an internally-trimmed monolithic four·quadrant
multiplier/divider. The AD632B has a maximum multiplying
error of ±O.S% without external trims.
Excellent supply rejection, low temperature coefficients and
long term stability of the on-chip thin film resistors and buried
zener reference preserve accuracy even under adverse conditions. The simplicity and flexibility of use provide an atrractive alternative approach to the solution of complex control
functions.
The AD632 is pin for pin compatible with the industry stand·
ard ADS32 with improved specifications and a fully differelltial high impedance Z-input. The AD63 2 is capable of providing
gains of up to XIO, frequently eliminating the need for separate instrUmentation amplifiers to precondition the inputs.
The AD632 can be effectively employed as a variable gain
differential input amplifier with high common mode rejection.
The effectiveness of the variable gain capability is enhanced by
the inherent low noise of the AD632: 90llV rms.
AD632 PIN CONFIGURATIONS
H-Package TO-IOO'
D-Package TO-116
V2
+Vs
Y1
Y2
Vos Z2
X2
NC
14131211108.
1234587
Z1
TOP VIEW
OUT -Va
NC
NC
Ne
X1
TOP VIEW
PRODUCT HIGHLIGHTS
Guaranteed Performance Over Temperature: The AD632A and
AD632B are specified for maximum multiplying errors of
±1.0% and ±O.S% of full scale, respectively at +2S oC and are
rated for operation from -25°C to +8S oC. Maximum multiplying errors of ±2.0% (AD632S) and ±1.0% (AD632T) are
guaranteed over the extended temperature range of -SSoC to
+12SoC.
High Reliability: The AD632S and AD632T series are also
available with MIL-STD-883 Level B screening and all devices
are available in either the hermetically-sealed TO-IOO metal can
or TO-116 ceramic DIP package.
ANALOG MUL TIPLIERSIDIVIDERS ~39
SPECIFICATIONS
+25"&, Ys= ±15Y, R;::2k!l unless otherwise noted)
(@
Model
AD632A
Typ
Min
Max
M;n
AD632B
Typ
Max
AD632S
Typ
Min
M ..
AD632T
Typ
M;n
Max
Units
MULTIPLIER PERFORMANCE
(X,-X,)(Y,-Y,)
lOY
+Z2
Transfer FunCHon
Total Error l ( - IOVsX, ¥s + lOY)
TA=mmtomax
Total Errorvs Temperature
(X,- X,)(Y,- Y,)
lOY
+Z1
(X,-X,)(Y,-Y,)
IOV
+Z2
(X,- X,)(Y,- Y,)
lOY
+ Z2
:to.S
±1.0
±2.0
±0.02
:to.S
±l.D
Scale Factor Error
(SF = IO.OOOV Nommali
Temperature-Coefficient of
Scalmg-Voltage
Supply ReJection ( ± 15V ± IV)
Nonlmearny,X(X= 20Vpk-pk. Y = lOY
Nonlmearlty, Y(Y = 20Vpk-pk,X = IOV
Feedthrough3.X (Y Nulled.
X ~ 20V pk-pk 50Hz)
Feedthrough 3 • Y (X Nulled,
Y ~ 20V pk-pk 50Hz)
Output Offset Voltage
Output Offset Voltage Dnft
±l.S
±0.022
±1.0
±0.015
±0.25
::to.1
±0.25
:to.02
::to 01
±0.4
±0.2
±O.Of
:to.2
::to.Ol
::to.al
::to.2
±0.1
±1.0
±O.Of
%
%
'IorC
±O.OOS
%rc
±O.l
::to.1
%
%
%
::to.1
%
±O.Ol
±0.3
::tO,I
±0.4
±0.2
::to.2
::to.1
±O.l
::to.IS
±0.1
±O.l
::to.IS
±0.1
%
±0.01
±5
200
±0.01
±2
100
::to
±0.01
±5
::to.Ol
±2
::to.1
±lS
300
%
mV
±30
I
±lS
±30
500
~VI"(;
DYNAMICS
Small Signal BW,(VOVT = O.lrms)
l%ArnpinudeError(CLOAD = lOOOpF)
Slew Rate (V OUT 20 pk-pk)
SettImg Time (to 1%, 6. VOUT = 20V)
1
50
20
2
1
50
20
2
1
50
20
2
1
50
20
2
MHz
kHz
NOISE
NOise Spectral-Densny SF = lOV
SF=3V4
Wideband NOise A "'" 10Hz to 5MHz
P = 10Hz to 10kHz
O.S
0.4
1.0
90
O.S
0.4
1.0
90
O.S
0.4
1.0
90
O.S
0.4
1.0
90
"VlYHz
~V/YHz
.... V/rms
.... V/rms
OUTPUT
Output Voltage SWlllg
Output lmpedance(fs 1kHz)
Output Short ClfCun Current
(RL =0, TA = mm lomax)
Amplifier Open Loop Gam (f = 50Hz)
INPUT AMPLIFIERS (X, Y and Z)'
Signal Voltage Range (Diff. orCM
Operatmg Duf.)
'Offset Voltage X. Y
Offset Voltage Drift X, Y
Offset Voltage Z
Offset Voltage Dnfl Z
CMRR
BlasCurrem
Offset Current
Differential ReSistance
60
~s
V
±Il
±ll
±ll
±Il
V/ ....s
0.1
0.1
0.1
01
11
10
70
30
70
30
70
10
70
rnA
dB
±10
± 12
±5
100
±5
200
SO
O.S
0.1
10
±10
±12
±2
50
±2
100
90
O.S
0.1
10
±10
±12
±5
100
±5
±20
±30
70
2.0
±10
±lS
60
±30
500
2.0
±10
V
V
mV
±lS
300
"vrc
~V/oC
mV
dB
90
OS
01
10
70
SO
O.S
0.1
10
2.0
±10
±12
±2
150
±2
±20
2.0
~A
~A
Mil
DIVIDER PERFORMANCE
(Z,-Z,)
lOY (X,-X,)+Y,
(Z,-Z,)
Transfer Function (X1>X Z)
lOY
Total Error l
(X= lOY, -lOVsZS + lOY)
(X~ IV, -lV,;Z,; + IV)
(O.lVSXslOV, -lOVsZsIOV
(X1-XZ)+Y 1
lOY
lOY
(Z, -Z,)
(X,-X,)+ Y,
%
%
%
±0.35
±1.0
±1.0
±0.75
±2.0
±2.S
±O.35
±1.0
±1.0
±0.75
±20
±2.5
(Z,-Z,)
(X,-x,tY,
SQUARER PERFORMANCE
(X -X )Z
I
2
--wv-
Transfer Function
Total Error ( -lOVsXsIOV)
SQUARE-ROOTER PERFORMANCE
Transfer Function, (Z, sZ2)
Total Error' (1 VsZsIOV)
POWER SUPPLY SPECIFICAnONS
Supply Voltage
Rated Performance
Operatmg
Supply Current
Quiescent
PACKAGE OPTIONS'
TO-100(H-lOA)
TO-116(D-14)
(X,-X,)'
(X,-X,)'
(X,-X,)'
--wv-
+Z2
--wv-
+Z2
--wv-
+Z2
+Z2
%
±0.1
±O.6
±0.6
±0.3
YlOV(Z,-Z,) +X,
Y10V(Z, - Z,) + X,
YlOV(Z,-Z,) +X,
Y10V(Z,-Z,) +X,
±1.0
±0.5
±1.0
±0.5
±15
±S
4
AD632AH
AD632AD
NOTES
IFtgUresglVenarepercentoffull-scale, ::!:: IOV(I.e ,0.01% = ImV)
to 3V usmg external re5lstor between - Vs and SF
Jlrreduclble component due to non1meanty: excludes effect of offsets.
"Usmg external resistor adjusted to gtye SF = 3V.
~See funcbonal block daagram forderwboD of secbons
6See Secbon 16 for package outline mformabon.
± 15
±15
±18
6
±S
±lS
4
±S
6
AD632BH
AD632BD
± 15
±22
4
±S
6
4
AD632SH
AD632SH
AD632TH
AD632TD
SpectficaUODS 5ub,cct to cbange Without nouce.
2 May be reduced down
6-40 ANALOG MUL T1PLlERSIDIVIDERS
%
Spectficabons shown 10 boldface are tested on all producuon uruts at final electrical test. Results from those tests are used to calculate outgoing qualIty levels. All
rom and max specificauons are guaranteed, although only those shown
boldface are tested on all producuon units.
lD
±22
V
V
6
rnA
Typical Performance Curves
(typical at +25°C with ±VS = 15V)
'000
r-...
vlJJ.llG' I
'00
,., ~
10
Vz = lOmVnnl
'Ix
"
'00k
I/
_f-- i-r-.
B
~O
••:
w
+LJ,,"
\ 1\ c!.J~~ ~,o'OOO"1
\\
lYdc
:\
1\
OdB"'WRMS,R l -2It1l
, ['v'\1_J wi
""
FREQUENCY - Hz
Figure 1. AC Feedthrough vs. Frequency
CF
1\1\
0
"',
~
r--,I v, . ,,,,,"vi' I
FREQUENCY - Hz
Cl '" 1000pF
No,,,,,"v",
,.,1-'
'00
r--,~
r--r-,
~FEEDTHROUGH
'/
/
........
r-.. '\
\,1'
Figure 3. Frequency Response vs. Divider Denominator
Input Voltage
CHIP DIMENSIONS & PAD LAYOUT
1 - - - - - - - 0 1 (2541----~.j
I 1000pF
I
: - - - CL"
CF<6200pF
W1HX10
FEEDBACK
I\m~OR
["
CONNECTION
fREQUENCY - Hz
Figure 2. Frequency Response as a Multiplier
For further information, consult factory
ANALOG MUL TlPLlERSIDIVIDERS 6-41
1-------00
+Vs
X INPUT
±10V FS
±12VPK
+15V
X2
TRANSFER FUNCTION
OUTPUT, ±12V PK
x,
OUT
VO=A[(X'-X2~~Vl-Y2)
X2
(SCALE'" 1)
TRANSLINEAR
MULTIPLIER
ELEMENT
v,
'" (X, - X2HV, - Va)
-(Zl- Z2)]
2,
22
OUT
V2
V-INPUT
V,
Vos
V2
-Vs
±10V FS
±12V PK
-15V
Vos
25k
Figure 4. AD632 Functional Block Diagram
OPERATION AS A MULTIPLIER
Figure 5 shows the basic connection for multiplication. Note
that the circuit will meet all specifications without trimming.
X-INPUT
f10V FS
i12V PK
x,
+Vs
+15V
X2
OUTPUT, i12V PK
OUT
Vos
= (X, -
OPTIONAL SUMMING
I
I
V
V,
Y2
OPERATION AS A DIVIDER
Figure 7 shows the connection required for division. Unlike
earlier products, the AD632 provides differential operation on
both numerator and denominator, allowing the ratio of two
floating variables to be generated. Further flexibility results
from access to a high impedance summing input to Y 1. As with
all dividers based on the use of a multiplier in a feedback loop,
the bandwidth is proportional to the denominator magnitude,
as shown in Figure 3.
2,
22
V-INPUT
±10V FS
±12V PK
X2~~' - V2) + 22
Figure 6. Connections for Scale-Factor of Unity
-Vs
INPUT, Z, ±10V PK,
Vos TERMINAL
NOT USED
X INPUT
(DENOMINATOR)
+10V FS
X,
+12V PK
X2
20kn
TO
+Vs
=
In some cases the user may wish to reduce ac feed through to
a minimum (as in a suppressed carrier modulator) by applying
an external trim voltage (±3OmV range required) to the X or Y
input. Curve 1 shows the typical ac feedthrough with this
adjustment mode. Note that the feedthrough of the Y input
is a factor of 10 lower than that of the X input and should be
used in applications where null suppression is critical.
The Z2 terminal of the AD632 may be used to sum an additional signal into the output. In this mode the output amplifier
behaves as a voltage follower with a 1MHz small signal bandwidth and a 20VI/ls slew rate. This terminal should always be
referenced to the ground point of the driven system, particularly if this is remote. Likewise the differential inputs should
be referenced to their respective signal common potentials to
realize the full accuracy of the AD632.
A much lower scaling voltage can be achieved without any
reduction of input signal range using a feedback attenuator as
shown in Figure 6. In this example, the scale is such that
VOUT = XV, so that the circuit can exhibit a maximum gain of
10. This connection results in a reduction of bandwidth to
about 80kHz without the peaking capacitor CF. In addition,
the output offset voltage is increased by a factor of 10 making
external adjustments necessary in some applications.
Feedback attenuation also reti'-ins the capability for adding
a signal to the output. Signals may be applied to the Z,
terminal where~they are amplified by -10 or to the common ground connection where they are amplified by -1. Input signals may also be applied to the lower end of the 2.7kQ
resistor, giving a gain of +9.
6-42 ANALOG MUL TIPLlERSIDItIIDERS
OPTIONAL -15V
SUMMING INPUT
:tl0V PK
10122- 2 ,1 +Y,
IX, ~X2)
OUT
Vos
2,
-Vs
22
200kn
Figure 5. Basic Multiplier Connection
+15V
OUTPUT. ±12V PK
+15V
-15V
+Vs
Z INPUT
(NUMERATOR)
±10V FS, ±12V PK
Y,
I
I
V
Y,
-Vs
-15V
Figure 7. Basic Divider Connection
Without additional trimming, the accuracy of the AD632B
is sufficient to maintain a 1% error over a 10V to 1V denominator range (The AD535 is functionally equivalent to the
AD632 and has guaranteed performance in the divider and
square-rooter configurations and is recommended for such
applications).
This range may be extended to 100:1 by simply reducing the
X offset with an externally generated trim voltage (range required is ±3.5mV max) applied to the unused X input_ To
trim, apply a ramp of +100mV to +V at 100Hz to both X,
and Z, (if X2 is used for offset adjustment, otherwise reverse
the signal polarity) and adjust the trim voltage to minimize
the variation in the output.'
Since the output will be near +10V, it should be ac-coupled for
this adjustment. The increase in noise level and reduction in
bandwidth preclude operation much beyond a ratio of 100
to 1.
·See the ADS 3 S Data Sheet for more details.
Very High Frequency
Four-Quadrant Multiplier
AD834 I
1IIIIIIII ANALOG
WDEVICES
FEATURES
500MHz Large-Signal Bandwidth
Differential ± 1V Full-Scale Inputs
Differential ± 4mA Full Scale Output Current
Low Distortion (.;;;0.05% for 10dBm Inputl
Supply Voltages from ±4V to ±9V
Low Power (290mW at Vs = ±5VI
AD834 FUNCTIONAL BLOCK DIAGRAM
X2
x,
+v,
W'
v,
V2
-v,
W2
APPLICATIONS
High-Speed Real-Time Computation
Wideband Modulation and Gain Control
Signal Correlation and Power Measurement
Voltage-Controlled Filters and Oscillators
Linear Keyers for High Resolution Television
Wideband True RMS
PRODUCT DESCRIPTION
The AD834 is a monolithic laser-trimmed four-quadrant analog
multiplier intended for use in high frequency applications, having
differential voltage inputs and a differential current output. The
transconductance bandwidth (RL = SOn) is typically SOOMHz
from either input. Performance is relatively insensitive tOJ!!~
perature and supply variations, due to the use of stabl!' ~3based on a bandgap reference generator and other-,g_,:;, -,;~
features.
;~il\', '~f~~~_,ry::, '"it'
To preserve the full bandwidth pot
bipolar process used to fabricate
as current as a differential paU!''O'
The transfer function is accu
X = Y ± IV, the differential 0
ei\bigh-speed<,,-, -,
~- 01;lfJ?P~-,~t
n'~ollectUrs. -
-,-t~,!~lhe~
,,;i"'M,
In multiplier modes, the maximum total
scale error i~go;~~
dependent on the application mode and the external circuitiY':' A
square-law transfer function can be achieved by connecting the
inputs in parallel; in this mode, the AD834 can be used as a
power detector.up to SOOMHz. The AD834J is specified for use
, cial temperature range of O°C to + 70°C, and is
an 8-pin SO package or 8-pin cerdip. The
ecified for use over the military temperature range
to,,+ 12SoC, and is available in an 8-pin cerdip.
'l\~;:j:,
~-,,,,
performs four-quadrant multiplication with a
gnal bandwidth in excess of SOOMHz.
M~J~iplier
~,,,,,-U
""'\'i~t,(,;;;
static accuracy of 2% of full-scale can be achieved.
esign techniques result in low output distortion
for + IOdBm inputs).
-------< 2~~
50
X·INPUT
WIOUTPUT
AD834
:l:1VFS
200mVFS
IIIT
W2
V·INPUT
:l:1VFS
I
~
R4
.7
'----------c;. 29:'~
Figure 3. Basic Connections for Wideband Operation
Figure 3 shows the use of optional termination resistors at the
inputs. Note that although the resistive component of the input
impedance is quite high (about 2SkO), the input bias current of
typically 4SjLA can generate quite significant offset voltages if
not compensated. For example, with a source and termination
resistance of son (net source of 2S0) the offset would be
2S0x 4SjLA = 1.12SmV. This can be almost fully cancelled by
including (in this example) another 2S0 resistor in series with
the "unused" input (in Figure 3, either X2 or Y2). In order to
6-46 ANALOG MUL TIPLIERSIDIVIDERS
I
V-INPUT
:t1VFS
~
.7
'----------~
..!':.
Figure 4. Transformer- Coupled,Output
A particularly effective type of transformer is the balun, which
is a short length of transmission line wound on to a toroidial
ferrite core. Figure S shows this arrangement used to convert
the 'bal'anced output to an 'un'-balanced one (hence the use of
the term). Although the symbol used is identical to that for a
transformer, the mode of operation is quite different. In the
Applying the AD834
first place, the load should now be equal to the characteristic
impedance of the line, although this will usually not be critical
for short line lengths. The collector load resistors Rc may also
be chosen to reverse-terminate the line, but again this will only
be necessary when an electrically long line is used. In most
cases, Rc will be made as large as the de conditions allow, to
minimize power loss to the load. The line may be a miniature
coaxial cable or a twisted pair.
+5V
50
29mA
The element values were chosen in this example to result in a
full-scale output of ± I V, so the overall multiplier transfer function
is
W = (XI-X2) (YI-Y2)
where it is understood that the inputs and output are in volts.
The polarity of the output can be reversed simply by reversing
either the X or Y input.
The op amp should be chosen to support the desired output
bandwidth. The AD842 and ADSS39 may be used in wideband
applications - the former providing about SOMHz of usuable
bandwidth. Many other choices are possible where lower post-.
multiplication bandwidths are acceptable. The level-shifting
network places the input nodes of the op amp to within a few
hundred millivolts of ground using the recommended balanced
supplies. The output offset may be nulled, either by use of a
1000 trim pot included between each of the lower pair of resistors
(4.7kO) and t negative supply, or by the use of an adjustment
e altered so that the output is ± 10V full scale
2SO feedback resistors to 1.2SkOk, raising the
to the op amp to ± I SV, and optionally raising
.stors to 1000. As always, attention to power
is essential for stable wideband operation.
It is important to note that the uppe
balun is determined only by the
hence, it will usually exceed t
a conventional transformer, w
flux in a magnetic core, and is
inductance. The lower limit on bandwi
. termin
series inductance of the line, taken as a whole, and the I
resistance (if the blocking capacitors C are sufficiently large). In
practice, a balun can provide excellent differential-to-single-sided
conversion over much wider bandwidths than a transformer.
WIDEBAND MULTIPLIER CONNECTIONS
Where operation down to de and a ground-based output are
necessary, the configuration shown in Figure 6 can be used.
AND SQUARING OPERATION
834 can be used as a signal squarer by connecting the X
s in parallel, as shown in Figure 7, which shows the
d to provide a SOO termination to the source,
pair of 1000 resistors in a symmetrical layout to reduce
e effect of resistor lead inductance. Minimum lead lengths and
direct routes to the ground plane are important. The SOO resistors
included in series with the XI and Y2 pins reduce offset voltages
generated by the input bias currents.
The same output system as used for the wideband multiplier is
used here, and similar measures may be taken to alter the scaling
factor and deal with output offset. Alternatively, one of the
several transformer-coupled arrangements may be used.
47
47
-6V
-6V
Figure 6. Widebanddc-CoupledMultiplierwith ± 1VOutput
Figure 7. Wideband Squarer Connection
ANALOG MUL TlPLIERSIDIVIDERS 6-47
POWER MEASUREMENT (MEAN-SQUARE)
The wide bandwidth of the AD834 makes it well suited to measurement of power, either as a multiplier for the determination of
the average V x I product, or as a squarer for use with a single
input. In these applications, the AD834 is followed by some
sort of low-pass filtering to extract the long-term average value.
If the first pole of this filter is formed by the addition of capacitors
placed directly at the output Pins WI and W2, the effective
multiplication or squaring bandwidth can be limited solely by
the AD834, since the following active circuitry is required to
process only low-frequency signals.
Figure 8 shows a general configuration which can be adapted to
suit a variety of scaling needs. The load resistors Rl are chosen
to result in minimal low-frequency voltage variation at the output
nodes WI and W2, consistent with also ac4ieving low drift in
the foiiowing subtraction stage formed by the op amp VI and
resistor pairs R2 and R3. The first pole is formed by R 1 and
Cl, the second by R3 and C2. Extreme care must be taken in
the layout of the circuit near the input and in the placement of
the capacitors Cl; these will dominate the high-frequency
behavior of the circuit, which, under favorable conditions, will
extend to beyond IGHz. Representative values are Rl = 510,
R2 = 430kO, R3 = IMO, Cl = IJloF ceramic in parallel with
(physically-smaller) O.OI""F' capacitors, C2 = O.OI""F. The op
amp may be an AD711; for maximum accuracy at the low end
of the dynamic range, use the offset-nulling pins of the op amps.
OUTPUT
±IVFS
4.7
4.7
-6V
Figure 8. Connections for Extracting the Mean-Square
Output
6-48 ANALOG MUL TIPLIERSIOIVIDERS
Log!Antilog Amplifiers
Contents
Page
Selection Guide . . . . . . . . . . . . . . . . . . . .
7- 3
..................... .
7-4
Orientation
AD9521 - 250MHz Wideband Logarithmic Amplifier
7-7
755/759 - 6-Decade, High Accuracy, Wideband Log, Antilog Amplifiers
757 - 6-Decade, High Accuracy, Log Ratio Amplifier . . . . . . . . . .
7 - II
7 - 15
•
LOG/ANTILOG AMPLIFIERS 7-1
7-2 LOG/ANTILOG AMPLIFIERS
Selection Guide
Log!Antilog Amplifiers
Model
Log Conformity
IoputRange
3dBError
%RTI
755
757
759
AD9521
IOnA-lmA
IOnA-lmA
20nA-lmA
OAVp-p
0.5
0.5
1.0
:!:ldB
Bandwidth
kHz
10
25
200
IOMHz-250MHz
Page
7 - II
7 - 15
7 - II
7-7
Notes
Wideband amplifier
w/logarithmic detected output
•
LOG/ANTILOG AMPLIFIERS 7-3
Orientation
Log!Antilog Amplifiers
The devices catalogued in this section include complete, selfcontained modules that provide output voltage proponional to
the logarithm or the antilogarithm (exponential) of an input
quantity. These modules operate on the instantaneous values of
inputs from dc to an upper cutoff frequency well below IMHz.
ranging from simple translation of natural relationships in log
form (e.g., computing absorbence as the log ratio of input currents), to the use of logarithms in facilitating analog computation
of terms involving arbitrary exponents and multiterm products
and ratios.
10
Also included is the AD9521 monolithic wideband ac logarithmic
amplifier with about 12dB of gain, pin compatible with the
Plessey SL521 and SLl521. Wideband log amplifiers are cascaded
to form "strips" with gains of 90dB and more - depending on
input amplitude - over a wide dynamic range, for frequencies
typically in the range of 7MHz to 250MHz.
K=2
LOGS AND LOG RATIOS
In the logarithmic mode, the ideal output equation is
Eo = -K 10gIO
{~:J
K = -2 -8
MODEL 755P
-INPUT CURRENT -10
)
Log of Current
Eo can be positive or negative; it is zero when the ratio is unity,
i.e., lin = lref. K is the output scale constant; it is equal to the
number of output volts corresponding to a decade* change of
the ratio. In the 755 and 759 log amplifiers, K is pin programmable
to be either I V, 2V or 2/3V, or externally adjustable to any
value ",,2/3V; in the model 757 log-ratio amplifier, K may be
either a preset value of I V or an arbitrary value adjustable by an
external resistance ratio.
lin is a unipolar input current within a 6-decade range (InA to
ImA); it may be applied directly, as a current, or derived from
an input voltage via an input resistor (in which case, the ratio
becomes E,oI(RmIref) = Em/Ere{. In models 755 and 759, the
magnitude of lref is internally fixed at IOILA (Eref = O.IV) or
externally adjusted; but model 757 is log-ratio amplifier, in
which both 1m and lref (or Em and Ere{, using external scaling
resistors) are input variables.
Each of the log amplifiers is available as a "P" or "N" option,
depending on the polarity of the input voltage. Logarithms may
be computed only for positive arguments, therefore the reference
current must be of appropriate polarity to make the ratio positive.
"N" indicates that the input current (or voltage) for the log
mode is positive; "P" indicates that only negative voltage or
current may be applied in the log mode. The polarity of K also
differs: K is positive for "N" versions and negative for "P"
versions. Thus, + 10V applied to model 759N, with K = + IV,
would produce an output voltage, Eo = -IV log (100) = - 2V;
on the other hand, -IOV applied to model 759P with K = IV,
would produce an output voltage, Eo = - ( -I V) log (100)
= +2V. The figure shows, in condensed form, the outputs of
P and N log amps, with differing K values, for both voltage and
current inputs, plotted on a semi-log scale.
Log amplifiers in the log mode are useful for applications reqniring
compression of wide-range analog input data, linearization of
transducers having exponential outputs and analog computing,
*A decBJJe is a 10:1 ratio, two decades is 100:1, etc. For example, if
K = 2, and the ratio is 10, the magaitude of the output would be 2V,
and its polarity ~ould depend on whether the ratio were creater or
less than unity. If the input signal then changed by a factor of 1,000
(3 decades), the output would change by 6V.
7-4 LOG/ANTILOG AMPLIFIERS
MODEL 755N
+INPUT CURRENT
(
MODEL 755P
-INPUT VOLTS
-5
MODEL 755N
+INPUT VOLTS
41
Log of Voltage
Output vs. Input of Model 755N & 755P in Log Connection
(Log Input Scales), Showing Voltages, and Polarity Relationships
ANTILOGS
In the antilogarithmic (exponential) mode, the ideal output equation
is
Em can be positive or negative; when it is zero, Eo = Eref. However,
Eo is always of single polarity, positive for "N" versions, negative
for "P" versions. Thus, for 759P, connected for K = -2V, if
Em = +4V, and Eref = -O.lV, then Eo = -0.lV·IO- 41 - 2, or
-IOV.IfEin= -4V, then Eo = -0.IV·IO-(-4)1-2= -lmV.
The figure on the next page shows in condensed form, the
outputs of P and N log amps, connected for antilogarithmic
operation, with different K values.
Antilog amplifiers are useful for applications reqniring expansion
of compressed data, linearization of transducers having logarithmic
outputs, analog function fitting or function generation, to obtain
relationships or generate curves having voltage-programmable
rates of growth or decay, and in analog computing, for such
functions as compound multiplication and division of terms
having differing exponents.
Eo (LOG)
756
Von
IIlk"
1/4"
'ON
OUT
(SUMMING
POINT)
-::-
-"'~-+--"""'--I-- +---I,"--~-+--"""""'_"
VIN
(LINEAR)
+15V
COM -15V TRIM Eos
a) Log/Antilog Amplifier Connected in the Log Mode (K = 1)
Antilog Operator Response Curves, Semilog Scale
Eo = EREF 10 VIN/-K
VON
1KK=.
- 1
At ;; 10k!), 1/4%
LOG-ANTILOG AMPLIFIER PERFORMANCE
Considerable information regarding log- and antilog-amplifier
circuit design, performance, selection and applications is to be
found in the Nonlinear Circuits Handbookl. Several salient points
will be covered here, and specifications will be defmed.
A log/antilog amplifier consists of an operational amplifier and
an element with antilogarithmic transconductance (i.e., the
voltage into the element produces a current that is an exponential
function of the voltage). As the figure shows, for logarithmic
operations, the input current is applied at the op-amp summing
point, and the feedback circuit causes the amplifier output to
produce whatever voltage is required to provide a feedback
current that will exactly balance the input ct/l"rent.
In antilog operation, the input voltage is applied directly to the
input of the antilog element, producing an exponential input
current to the op-amp circuit. The feedback resistance transduces
it to an output voltage.
The wide range of log/exponential behavior is made possible by
the exponential current-voltage relationship of transistor baseemitter junctions,
I = loCeqVIkT
-
1) "" 10eqVlkT
and V = (kT/q) In (1110)
where I is the collector current, 10 is the extrapolated current
for V = 0, V is the base-emitter voltage, q/k (11,605 KN) is
the ratio of charge of an electron to Boltzmann's constant and T
is junction temperature in kelvins. In log/antilog devices, two
matched transistors are connected so as to subtract the junction
voltages associated with the input and reference currents, making
the ratio independent of Io's variation with temperature.
t:.V = (kT/q) In (I;nIlo) - (kT/q) In (Ird1o)
= (kT/q)(In lin - In lref)
+ (kT/q)(In 10
- In 10)
= (kT/q) In (linlIref)
lNoo/iIJear Circuits HlUJdbook, Analog Devices, Inc., 1974, 1976,
536pp, edited by D. H. Sbeingold, $5.95; send check or complete
MasterCard data to P.O. Bo" 796,·Norwooci, MA 02062
155
"::'
+15V
COM -15V TRIM Eos
b) Log/Antilog Amplifier Connected in the Exponential Mode
The temperature dependence of gl1in is compensated for by a
resistive attenuator that uses a temperature-sensitive resistor for
compensation. The attenuator also produces amplification of K
to the specified nominal values, e.g., from the basic 59mV/decade,
(kT/q) InlO at room temperature, to IV/decade.
Errors are introduced by the offset current of the amplifier (and
the offset voltage) for voltage inputs; by inaccuracy of the reference
current (or the effective reference voltage, for voltage inputs) in
fixed-reference devices; and by inaccuracy of setting K. Additional
errors are introduced by drift of these parameters with temperature.
At any temperature, if these parameters are nulled out, there
remains a fmal irreducible difference between the actual output
and the theoretical output, called log-conformity error, which is
manifested as a "nonlinearity" of the input-output plot on semilog
coordinates. Best log conformity is realized away from the extremities of the rated signal range. For example, log-conformity
error of model 755 is ± 1% maximum, referred to the input,
over the entire 6-decade range from InA to lmA; but it is only
±0.5% maximum over the 4-decade range from IOnA to 100",A.
A plot of log conformity error for model 759 is shown on the
following page.
Errors occurring at the input, and log-conformity errors, can
only be observed at the output, but it is useful to refer them to
the input (RTI). Equal percentage errors at the input, at whatever
input level, produce equal incremental errors at the output, for
a given value of K. For example, if K = 1, and the RTI logconformity error is + 1%, the maguitude of the output error
will be
Error = Actual output - ideal output
IV·log (1.01 lllref) - IV·log (IIIref)
IV·log 1.01 = 0.0043V =4.3mV
LOG/ANTILOG AMPLIFIERS 7-5
I
i
•
•
•
DEFINITIONS OF SPECIFICATIONS
Log-Conformity Error: When the parameters have been adjusted
i8 ··,
,
7
to compensate for offset, scale-factor and reference errors, the
log-conformity error is the deviation of the resulting function from
a straight line on a semilog plot over the range of interest.
3
§
2
•
'oA
"
'" "
UlnA20nA
,i'T!!~T!~r~n;~!"T~'~Ti1'r
,,,.
,
Offset Current (los) is the bias current of the amplifier, plus any
,.... """"
1~
A
A
'mA
Log Conformity Error for Models 759N and 759P
If, in this example, the input range happens to be 5 decades;
the corresponding output range will be 5 volts, and the 4.3mV
log-conformity error, as a percentage of total output range, will
be less than 0.1%, Because this ambiguity can prove confusing
to the user, it is important that a manufacturer specify whether
the error is referred to the input or the output. The table below
indicates the conversion between RTI percentage and output
error-magnitudes, for various percent errors, and various values
ofK.
LOG OUTPUT ERROR (mV)
%ERRORRTI
0.1
0.5
1.0
2.0
3.0
4.0
5.0
10.0
K=IV
K=2V
0.43
2.2
4.3
8.6
13
17
21
41
0.86
4.3
8.6
17
26
34
42
83
K=(2/3)V
0,28
1.4
2.9
5.7
8.6
11
14
28
For antilog operations, input and output errors are
interchanged.
To arrive at the total error, an error budget should be made up,
taking into account each of the error sources, and its contribution
to the total error, over the temperature range of interest.
Dynamic response of log amps is a function of the input level.
Small-signal bandwidths of ac input signals biased at currents
above lILA tend to be roughly comparable. However, below
lILA, bandwidth tends to be in rough proportion to current
level. Similarly, rise time depends on step magnitude and direction - step changes in the direction of increasing current are
responded to more quickly than step decreases of current.
stray leakage currents. This parameter can be a significant source
of error when processing signals in the nanoampere region. Its
contribution in antilog operation is negligible.
Offset Voltage (Bus) depends on the operational amplifier used
for the log operation. Its effect is that of a small voltage in
series with the input resistor. For current-logging operations,
with high-impedance sources, its error contribution is negligible.
However, for voltage logging, it modifies the value of VIn. Though
it can be adjusted to zero at room temperature, its drift over the
temperature range should be considered. In antilog operation,
Eos appears at the output as an essentially constant voltage; its
percentage effect on error is greatest for small outputs.
Reference Current (Ire£) is the effective internally-generated currentsource output to which all values of input current are compared.
l..c tolerance appears as a dc offset at the output; it can be adjusted
towards zero by adjusting the reference current, adding a voltage
to the output by injecting a current into the scale-factor attenuator
or simply by adding a constant bias at the output's destination.
Reference Voltage (E..c) is the effective internally generated voltage
to which all input voltages are compared. It is related to l..c by
the equation: E..c = I..cRm' where Rin is the value of input
resistance. Typically, l..c is less stable than Rio; therefore,
practically all the tolerance is due to l..c.
Scale Factor (K) is the voltage change at the output for a decade
(i.e., 10:1) change at the input, when connected in the log mode.
Error in scale factor is equivalent to a change in gain, or slope
(on a semilog plot), and is specified in percent of the nominal
value.
WlDEBAND (AC) LOGARITHMIC AMPLIFIERS
Amplifiers in the class of the AD9521 are essentially limiting
amplifiers, providing high gain for small signals and low gain for
large signals. They accept high-frequency ac signals (7MHz to
250MHz) and provide two amplified outputs: a radio-frequency
output (voltage) and a nonlinearly detected output (current).
The amplification characteristic (current output vs. rf input) on
a semilog scale is S-shaped, starting with zero slope, increasing
to a linear slope, then soft-saturating (with a slight overshoot).
They are used in strips, or cascades, of n (for example, 6 to 9)
stages, with the rf output of one unit becoming the input of the
next, thus multiplying their gains. The nonlinearly detected (or
video) outputs are connected together for current summation.
The resulting output-vs.-input characteristic (semilog scale) is
S-shaped, with a lengthy log-linear region whose extent depends
on the number of stages (about 12dB per device). Once an
amplifier saturates, its contribution to the summation is fixed;
thus, the maximum output for large signals is n times the output
of one device. The maximum dynamic range has been realized
when the number of stages, n, is such that the input-stage noise
alone produces full output from the last stage.
7-6 LOGIANnLOG AMPLIFIERS
250MHz Wideband
Logarithmic Amplifier
AD9521
1IIIIIIII ANALOG
WDEVICES
I
PIN DESIGNATIONS
FEATURES
250MHz Bandwidth
Monolithic Construction
Low Noise Figure 4.7dB
Excellent Detected Output Matching
Direct Replacement for SL521/SL1521
OUTPUT GROUND
APPUCATIONS
Missile Guidance
Electronic Warfare (ECM, ECCM, ESM)
Miniaturized LOG Strips
Nuclear Instrumentation
DETECTED OUTPUT
"
~~
...
~ ~
3
GENERAL DESCRIPTION
The AD9521 is a wideband amplifier stage with a logarithmic
detected output. The high-performance bipolar process used to
construct the AD9521 allows operation from 10MHz to 250MHz
with minimal gain variation. The AD9521 is pin compatible
with the SL521 and the SL1521.
NC 4
2
U:;:)£I: U
201:1 2
.....
1
20 19
.~
+V.5
NC 6
RFOUTPUT 7
17 BIAS
AD95Z1
TOP VIEW
INot to Scalel
NC 8
The AD9521 is constructed in a well controlled monolithic
process which provides very good gain tolerance (± 1.5dB)over
the full performance range. An added benefit of the high gain
tolerance is a high degree of detected output current ntatching
from device to device. The ntatching combined with the low
4dB noise figure allows the construction of 80dB to 90dB dYnamic
range LOG strips with better than ± IdB linearity.
18 NC
16 NC
15 INPUT
14 NC
The AD9521 is offered in two gain tolerance grades as both a
commercial temperature range device, 0 to + 70,,{;, and as an
extended temperature range device, - 55'e to + 125'e. All
grades are available packaged in 8-pin TO-99 metal cans with
the military grades also available packaged in ceramic Lee.
ORDERING INFORMATION
Device
AD952IJH
AD9521KH
AD9521SE
AD9521SH
AD9521TE
AD9521TH
3
Detected Output
Matching
Temperature Range
O.2mA
O.lmA
O.2mA
0.2mA
O.lmA
O.lmA
Oto +70'C
Oto +70"C
55"C to + 125"C
55"<: to + 125"<:
55"C to + 125"C
55"<: to + 125'C
-
Description
Package
Options·
S-Pin Can, Industrial
S-Pin Can, Industrial
20-Pin LCC, Extended Temperature
S-PinCan, Extended Temperature
20-Pin LCC, Extended Temperature
S-Pin Can, Extended Temperature
H-OSA
H-OSA
E-2OA
H-OSA
E-20A
H-OSA
See Section 16 for package outline information.
LOG/ANTILOG AMPLIFIERS 7-7
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS·
Supply Voltage (+ VS) • • • • • • • •
Differential Voltage Between Grounds
Maximum Input Before Overload . . .
Instantanious Voltage at the Detected
Video Output . .
RF Output Current
Power Dissipation .
. .. +9V
Operating Temperature Rang~
. . . ,O.5V
AD952lJHlKH • . . . . .
AD952lSElSHffEffH . .
1.9V rms
..
... ° +
to +70OC
- 550C to
- 55°C to
Storage Temperature Range •
Junction Temperature . . . .
Lead Soldering Temperature (IOsec)
12V
• 10mA
500mW
125°C
+ 1500C
+ 175°C
. . . . . +300°C
ELECTRICAL CHARACTERISTICSCSupplyYDItages = +6V; INPUT connected to BIAS pin; Rs = 50{l;CL~ SpF,unlessothenvisestated)
Parameter
AC PERFORMANCE
Voltage Gain (fIN = 30MHz)
Voltage Gain (fm = 6OMHz)
Voltage Gain (fIN = 120MHz)
Voltage Gain (fIN = 160MHz)
Input Capacitance
Noise,Figure·
Gain Variation VS. Temperature5
Gain Variation va. Supply"
Frequency Response
UpperCutoffFrequency
Lower Cutoff Frequency
DETECTED VIDEO OUTPUT
Output Current @60MHz(Max)'
(80% Input Level)!
(No Input)9
Output Current @ 120MHz (Max)'
(80% Input Level)!
(No Input)9
Detected Output Variation vs. Supply·
Detected Output vs. Temperature'
Mil'
Sub
Group Temp
Industrial Temp.1lauge
Military Temp.1lauge
Oto +70'C
-ss'Cto + 12SOC
AD9s21KH
AD9s21TEffH
AD9S21JH
AD9s21SElSH
Min Typ Max Min Typ Max Min TypMaJ Min Typ Max Units
7
8
7
8
7
8
7
8
11.5
11.0
12.0
11.7
12.2
11.5
12.7
11.5
12
12.2
12.8
13.0
13.4
6
4.7
0.67
0.74
7,8
7
8
7,8
+25"C
Full
Full
230
200
7
8
7
7
7
8
7
7
7
+25'
Full
+25"C
+25"C
+25"C
Full
+25"C
+25OC
+25"C
Full
0.90
0.80
0.70
RFOUTPUT'·1
Maximum RF Output Voltage
RF Output Propagation Delay
POWER SUPPLylO
Supply Current ( + 6.0V)
+25OC
Full
+ 25'C
Full
+25OC
Full
+25"C
Full
+25'C
+25"C
Full
I
2,3
Nominal Power Dissipation
0.68
0.57
0.66
1.02
1.10
1.20
0.90
0.04
0.90
0.91
0.86
0.04
30
0.76
0.02
28
9
+ 25'C
+25"C
1.6
1.4
+25"C
Full
+ 25"C
14.0
84
Exposure to absolute maximum rating conditions for extended periods
may affect device relisbility.
'Typical thermal unpedance ...
AD952 I Metal Can.
8/A = 185"CJW;8/c=50'C1W
8/A=8O'CJW;8/c =50'C1W.
230
200
10
12.2
12.8
13.0
13.4
6
4.7
0.67
0.74
1.15
7
0.82
0.02
0.79
11.5
11.0
12.0
11.7
12.2
11.5
12.7
11.5
4.9
245
NOTES
IAbsolute maxunurn ratings are limitmg values, to be apphed individually,
and beyond which serviceability of the circuit may be impaired. Functional
operation under any of these conditions is not necessarily IDlplied.
AD9521LCC
12.5
13.0
13.0
13.7
13.8
14.5
14.2
14.5
0.95
0.85
0.75
0.73
0.68
0.71
12.5
13.0
13.0
13.7
13.8
14.5
14.2
14.5
1.15
230
200
7
10
1.02
1.05
1.15
0.85
0.04
0.85
0.90
0.81
0.04
30
0.76
0.02
28
9
0.90
0.80
0.70
0.68
0.57
0.66
1.6
1.4
16.0
16.5
14.0
12.2
12.8
13.0
13.4
6
4.7
0.67
0.74
4.9
245
0.82
0.02
0.79
11.5
11.0
12.0
11.7
12.2
11.5
12.7
11.5
12.5
13.0
13.0
13.7
13.8
14.5
14.2
14.5
1.15
230
200
7
10
1.02
1.10
1.20
0.90
0.04
0.90
0.91
0.86
0.04
30
0.76
0.02
28
9
1.6
1.4
16.0
16.5
84
14.0
16.0
16.5
12.2
12.8
13.0
13.4
6
4.7
0.67
0.74
4.9
245
0.82
0.02
0.79
11.5
11.0
12.0
11.7
12.2
11.5
12.7
11.5
0.95
0.85
0.75
0.73
0.68
0.71
12.5
13.0
13.0
13.7
13.8
14.5
14.2
14.5
4.9
1.15
245
MHz
MHz
7
10
MHz
1.02
1.05
1.15
0.85
0.04
0.85
0.90
0.81
0.04
30
mA
mA
mA
mA
mA
mA
mA
mA
0.82
0.02
0.79
0.76
0.02
'28
%N
9
%
1.6
1.4
Vp-p
14.0
na
16.0
16.5
84
84
dB
dB
dB
dB
dB
dB
dB
dB
pF
dB
dB
dBN
mA
mA
mW
4Rs = 4500; 6OMHz.
SA1N = 6OMHz.
6Measured at ±S% of + Vs; AlN =6OMHz.
'Input = O.5V rms.
'Input = O.09V rms.
'Input = O.OV rms.
IOSupply voltage should remain stable WIthin ± 5% for normal operation.
Specifications subject to change without notice.
'Military subgroups apply to military quahfied devices only.
EXPLANATION OF GROUP A MILITARY SUBGROUPS
Subgroup
Subgroup
Subgroup
Subgroup
1234-
Stane tests at + 25"C.
Stane tests at max rated operatmg temp
StatiC tests at mID rated operatmg temp.
Dynanuc tests at + 25"C.
7-8 LOG/ANTILOG AMPLIFIERS
Subgroup
Subgroup
Subgroup
Subgroup
5678-
DynamtC tests at max rated operaung temp
Dyruumc tests at mm rated operanng temp
Funcuonal tests at + 25"<:.
Functtonal tests at max an!d mm rated
operating temp
Subgroup
Subgroup
Subgroup
Subgroup
910 11 12 -
SWitching tests at + 25"<:
SWltcrung tests at max rated operaung temp.
SWitChing tests at mm rated operanng temp.
PenodK&lly sample tested.
FUNCTIONAL DESCRIPTION
PIN NAME
DESCRIPTION
CASE
+Vs
RFOUTPUT
DETECTED OUTPUT
INPUT GROUND
INPUT
BIAS
OUTPUT GROUND
- Case connection for the TO-99 metal can package only.
- Positive supply terminal, nominally + 6.0V.
- The RF OUTPUT is used to drive subsequent LOG detection stages. The RF OUTPUT
level is roughly + 12dB above the IF signal strength at the input.
- The DETECTED OUTPUT provides a dc current 10garithmic1y proportional to the IF
signal level at the input.
- Isolated input ground connection. The input and output grounds should be connected together
near the AD9521.
- IF signal input.
- The BIAS connection is tied to the INPUT pin to provide an adequate biasing level between
ac coupled stages. The bias connection should be omitted between direct dc coupled stages.
- Isolated output ground connection. The input and output grounds should be connected
together near the AD9521.
SCHEMATIC
r-~--~------~--------~--------~~~O+V,
BIAS
INPUT
J--t--+--'11'0.....-+---+-------t-t----O RF OUTPUT
INPUT
GROUND 0-.....- -.....- -__------'
OUTPUT
' - - -.....- - - - - - - -.....- - - 0 GROUND
DIE LAYOUT AND MECHANICAL INFORMATION
RF OUTPUT
Die Dimensions
Pad Dimensions
Metalization . .
Backing . . . .
Substrate Potential
Passivation
Die Attach
Bond Wire
86x97x 15 (±2) mils
4x4mils
Aluminum
None
. .. -Vs
Oxynitride
Gold Eutectic
1.25 mil Aluminum; Ultrasonic Bonding
or lmil Gold; Gold Ball Bonding
DETECTED
OUTPUT
INPUT
GROUND
LOG/ANTILOG AMPLIFIERS 7-9
TYPICAL LOG STRIP CONFIGURATION
INPUT
APPLICATIONS INFORMATION
The AD9521 is primarily designed for use in successive detection
LOG strips. The application circuit above, illustrates the typical
configuration for one such design with roughly 90dB of dynamic
range. In operation the IF input signal level is successively
amplified by each stage in the upper chain. The IF signal at
each stage generates a detected output current. The detected
output current from each stage is summed in the common base
follower stage at the end of the strip.
The key to the circuit is the limiting quality of the AD9521
logarithmic detected output. As the IF signal at each stage
drives the detected output into saturation, the output current
ceases to increase. In operation, the combined gain of all of the
previous stages drives the last stage into saturation first. Any
further increase in signal level will not increase the detected
output level of the last stage, but all of the previous stages will
enter saturation one-by-one as the signal level increases.
The limiting factor to the number of stages that can be combined
is the input noise level. When the gain of the entire strip is
sufficient to drive the last stage into saturation on the input
noise of the first stage alone, further extensions of the strip will
not increase the dynamic input range.
There are, however, two methods of increasing the dynamic
range of the LOG strip which include bandwidth reduction and
parallel strip configurations. The dynamic range can be extended
by 20dB or more by incorporating a parallel log strip with an
attenuated input. The main strip functions as before, but the
7-10 LOG/ANTILOG AMPLIFIERS
second strip, because of the attenuation, only contributes to the
output for signals in excess of the main strip saturation level.
The ultimate limitation is the maximum input signal level which
the main strip will tolerate. Any further signal level increases
could damage the input stage of the AD9521. This should not
be a major problem since with this technique the dynamic range
of the total strip can be as high as I OOdB.
The dynamic range can also be increased by reducing the
bandwidth of the strip itself. The noise voltage is directly proportional to the square root of the circuit bandwidth. This means
that large operating bandwidths produce large amounts of noise
which translates into limited dynamic range. The AD9521 is a
particularly low-noise device, but even it can benefit from
bandwidth reduction which has been incorporated into the circuit
above. The two interstage fIlters limit the noise to a smaller
~egion of frequencies and thereby allow the strip to be extended
further.
Because of the high-frequency nature of the AD952 I , several
guidelines should be followed to insure optimum performance.
The first is the use of an adequate low impedance ground plane.
Just as important is the use of power supply decoupling capacitors
to prevent signal feedthrough on the supply lines. Chip capacitors
are highly recommended because of their reduced lead inductance.
Sockets are not likely to produce the best results because of the
interlead capacitance, but if they must be used, pin sockets are
preferred.
1IIIIIIII ANALOG
WDEVICES
FEATURES
High Accuracy: Models 755N. 755P
Wideband: Models 759N. 759P
Complete Log/Antilog Amplifiers: External Components Not
Required
Temperature-COmpensated Internal Reference
6 Decades Current Operation: 1nA to 1mA
1% max Error: 1nA to 1mA (755)
20nA to 2001lA (759)
4 Decades Voltage Operation: 1mV to 10V
1% max Error: 1mV to 10V (755)
1mVto 2V (759)
Small Size: 1.1"X 1.1" X OA"
6-0ecade, High Accuracy,
Wideband Log, Antilog Amplifiers
Models 755N/755P/759Nl759P
I
MODELS 755/759 FUNCTIONAL BLOCK DIAGRAM
r---I
IsIG
~.~.~~
+15V
COM
-15V TRIM
'POSITIVE INPUT SIGNALS, AS SHOWN; USE MODEL 759N, 755N.
NEGATIVE INPUT SIGNALS, USE MODEL 759N, 755P.
GENERAL DESCRIPTION
The models 75SN, 7SSP and 7S9N, 7S9P are low cost dc
logarithmic amplifiers offering conformance to ideal log opera:tion over 6 decades of current (inA to 1mA) and 4 decades'
of voltage (lmV to 10V). For high accuracy requirements,
models 7SSN, 7SSP offer maximum nonconformity of 0.5%,
from 10nA to 1mA, and 1mV to 1V. For wideband applications, the models 7S9N, 7S9P provide fast response (300kHz
@ ISIG = lOIlA to 1mA) and feature maximum nonconformity
of 1% from 20nA to 200llA, and 1mV to 2V. The models
7SSN and 759N compute the log of positive (+) input signals,
while the models 75SP, 7S9P compute the log of negative (-)
signals.
Designed for ease of use, the models 755N/P and 759N/P are
complete, temperature compensated log/antilog amplifiers
packaged in a compact epoxy-encapsulated module. External
components are not required for logging currents over the
complete 6 decade range of lIlA to 1mA. Both the scale factor
(K=2, 1, or 213 volt/decade) and log/antilog operation are
selected by simple pin connection. In addition, both the internal lOIlA reference current as well as the offset voltage may
be externally adjusted to improve overall accuracy.
10
8
6
4
en
I...J
2
>
0
0
I-
...
:;)
I-
:;)
0
1
-2
-4
-6
-8
KI=2
'":"
K~1
K=~ t--........ ~ ~o-5
I
"
10-9 10-8 10-7 10-6
10-4 10-3
~~
"
MODEL 755N,759N
-10
+ INPUT CURRENT (AMPS), LOG SCALE
Figure 1. Transfer Function
The models 755 and 759 are ideally suited as an alternative
to in-house designs of OEM applications. Advanced design
techniques and superior performance place the 755 and 759
ahead of competitive designs in terms of price, performance
and package design.
APPLICATIONS
When connected in the current or voltage logging configuration, as shown in Figure 1, the models 755 and 759 may be
used in several key applications. A plot of input current
versus output voltage is also presented to illustrate the log
amplifier's transfer characteristics.
LOG/ANnLOG AMPLIFIERS 7-11
SPECIFICATIONS (typical @+25°C and ±15V de unless otherwise noted)
755N/P
MODEL
OUTLINE DIMENSIONS'
759N/P
Dimensions shOWD in inches and (mm).
TRANSFER FUNCTIONS
Current Mode
j-W
VohagcMode
h
r
55.759
L
AntdogMode
_I
]0.•1'0."
,MAX
0.2 TO 0.26
15
TRANSFER FUNC'tION PARAMETERS
Scale Fat'tor (K) Selec:aonsl, 2
Errol'@ +ZSDC
0
2, I. 2/3 Volt/Decade
±t% max
±O 04%/"C max
VI Temperature (0 to +70 C)
Reference Volt~e (Ea£F)2
Error@+2S oC
vs Temperature (0 to +70°C)
Reference Current (lREF)2
Error@ +2SoC
0
±3% max
:t4%max
to l%fC max
±o.o,%fC
vs Temperature (0 to +70 C)
±O l%fC max
MAXIMUM LOG CONFORMITY ERROR
(filG RANGE
ESIC RANGE
InA to IOnA
IOnA to 20nA
20nA to lOOIlA
loo,.A to 200jlA
200pAto ImA
Of~:\~:~a:~~r:2(~u~ (;;~~~~able to 0)
VI
Supply Voltage
.... 5
8 TRIM
EsIG •
lO",A
8 ·16
±3% max
RTI
RTI
RTO(K-1)
±43mV
±2.17mV
±217mV
±43mV
±43mV
±S%
±21mV
±8.64mV
±D.S%
±I%
±I%
+lnA to +lmA mm
-InA to -lmA mm
±lOmA max
(0, +) 10pA max
x2l+10oC
±2%
±I%
±I%
±2%
2VIOEC 2
8 +15
TRIM·
±4.3mV
1V/DEC 1
IsIG:: ImA
±43mV
~O, +)
TEMPERATURE RANGE
Rated Performance
Operatms
Storage
CASE SIZEs (W x L x H)
MATING SOCKET ACI016
+lmV to +lOV mm
-lmV to -IOV mm
-2<:~<2
±40OIJV max
±lSpVtC max
±ISI'VI%
f!!1
g
±2mVmax
±Io~vfc
!5
~
o
10kHz
40kHz
100kHz
K-2
8
4
-10-9 0
-8
.
2p.Vrms
2pA rms
IOjlVnm
10pArms
±tOVmm
MODEL 766P. 759P
Plot of Output Voltage vs Input Current
for Model .155 Connected in the Log Mode
il
K=-2
osn
±4mA
Oto+70 C
_2SDC to +SSDC
_5S DC to +12SDC
D
1.5" X 1.5" x 0.4"
US x'S x 104)
Use termlaall for K -IV/decade, tennma1l for K. lV/decade, termioaIs I or 2
power supply,moclel904, :t15V" :t50mAoutput.
10 iDdta (nun)
4 Recommended
SpedficatioD.lUb,J«t ID c:hanp witbout 1lOQC:C.
+INPUT CURRENT
LOG OF CURRENT
±4mA
±lSVdc
±(12 to 18)Vdc
±7mA
6
4
K-2
2
-1
-2
1.125" X 1.125" x 0 4"
C29x29xl04)
-3
-4
..
MODEL 766P.769P
-INPUT VOLTS
-5
..
MODEL 756N. 769N
+INPUT VOLTS
LOG OF VOLTAGE
Plot of Output Voltage vs Input Voltage
for Models 755, 759 Connected in the Log Mode
Figure 2. Transfer Curves
7-12 LOG/ANTILOG AMPLIFIERS
.
MODEL 766N. 769N
-'0
-INPUT CURRENT
±SmA
(tborted topCber) for K = 2/3V/dccade
YSpedficatioD Is + for models 755N, 759N, -for 755P, 759P.
• No damaF due to any pm be.... lhorted to IfOUIKI
'Cue _
'08
2
250Hz
100kHz
200kHz
200kHz
SOHz
NOl'BS
I
12.5'
200pA max
POWER SUPPLy4
Rated Perfonnance
Operatmg
CUrrent, QUiescent
\--0.1 GRID
'Optional l00kn external trim pot. Input offset voltege may be
adjusted to zaro with trim pot connected as shown. With trim
terminal 9 left open, input offset voltege will be ±OAmV (755)
or ±2mV (759) maximum.
INPUT NOISE
Voltage, 10Hz to 10kHz
Current, 10Hz to 10kHz
---t
±8.64mV
RISE TIME
Increasmg Input Current
10nA to 100nA
lOOnA to IpA
lILA to ImA
Decreasmg Input Current
lmA to IpA
lpA to lOOnA
100nA to iOnA
OUTPUT SPECIFICATIONS3
Rated Output
Voltage
Current
Log Mode
AntdogMode
Reststance
I
BOTTOM VIEW
FREQUENCY RESPONSE. Smewave
Small Signal Bandwidth, -3dB
's'G= InA
's1G· I~A
's'G'I""A
L
IIOUT 3
7 COM
RTO(K=!!
±I%
INPUT SPECIFICATIONS
Current S"nal Range
Model 755N, 759N
Model 755P, 759P
Max Safe Input CUlJCnt
Bias Current@ +25 C
0
vs Temperature (0 to +70 C)
Voltage Stgnal Range (Log Mode)
Model 7SSN, 7S9N
Model 755P, 759P
Voltage Signal Range. Antilog M.Jde
Model 755N, 7SSP
1
J
OIV
±D.5%
ImVtolV
IVto2V
2Vto IOV
004D'AI1.02)
Understanding the Log Amplifier Performance
PRINCIPLE OF OPERA nON
Log operation is obtained by placing the antilog element in the
feedback loop of the op amp as shown in Figure 1. At the
summing junction, terminalS, the input signal current to be
processed is summed with the output current of the antilog
element. To attain a balance of these two currents, the op amp
provides the required output voltage to the antilog feedback
element. Under these conditions the ideal transfer equation
(K = 1) is:
t:oUT = IV log10 IsIG IIREF
The log is a mathematical operator which is defined only for
numbers, which are dimensionless quantities. Since an input
current would have the dimensions of amperes it must be
referenced to another current, IREF' the ratio being dimensionless. For this purpose a temperarure compensated reference of
10j.lA is generated internally.
The scale factor, K, is a multiplying constant. For a change in
input current of one decade (decade = ratio of 10: I), the output changes by K volts. K may be selected as IV or 2V by connecting the output to pin 1 or 2, respectively. If the output is
connected to both pins 1 and 2, K will be 213V.
REFERRING ERRORS TO INPUT
A unique property of log amplifiers is that a dc error of any
given amount at the output corresponds to a constant percent
of the input, regardless of inpu t level. To illustrate this, consider the output effects due to changing the input by 1%.
The output would be:
t:oUT = IV log10 (IsIG/IREF)(1.0l) wpich is equivalent to:
.
t:oUT = IV log10 (IsIG /IREF)
\
±lV 10giO (1.01)
'~
Initial Value
Change
The change in output, due to a 1% input change is a constant
value of ±4.3mV. Conversely, a dc error at the output of
±4.3mV is equivalent to a change at the input of 1%. An abbreviated table is presented below for converting between errors
referred to output (R.T.O.), and errors referred to input (R.T.I.).
ERROR R.T.O.
ERROR R.T.I.
0.1%
0.5
1.0
3.0
4.0
5.0
10.0
K=1
K=2
K= 213
0.43mV
2.17
4.32
12.84
17.03
21.19
41.39
0.86mV
4.34
8.64
25.68
34.06
42.38
82.78
0.28mV
1.45
2.88
8.56
11.35
14.13
27.59
SOURCES OF ERROR
Log Conformity Error - Log conformity in logarithmic devices is a specification similar to linearity in linear devices. Log
conformity error is the difference between the value of the
transfer equation and the acrual value which occurs at the ou tput of the log module, after scale factor, reference and offset
errors are eliminated to taken into account. The best linearity
performance for the models 755, 759 are obtained in the 5
decades from 10nA to 1mA. To obtain optimum performance,
the input data should be scaled to this range.
Offset Voltage - The offset voltage, Eos' of models 755, 759
is the offset voltage of the internal FE T amplifier. This voltage
appears as a small dc offset voltage in series with the input
terminals. For cur.rent logging applications, its error contribution is negligible. However, for log voltage applications, best
performance is obtained by an offset trim adjustment.
Bias Current - The bias current of models 755, 759 is the bias
current of the internal FET amplifier. This parameter can be a
significant source of error when processing signals in the nanoamp region. For this reason, the bias current for model 755 is
lOpA, maximum, and 200pA maximum for model 759.
Reference Current - IREF is the internally generated current
source to which all input currents are compared. IREF tolerance errors appear as a dc offset at the output. The specified
value of IREF is ±3% referred to the input, and, from Table I,
corresponds to a dc offset of ± 12.84mV for K = 1. This offset
is independent of mput signal and may be removed by injecting a current into terminal 1 or 2.
Reference Voltage - EREF is the effective internally generated
voltage to which all input voltages are compared. It is related
to IREF through the equation:
EREF = IREF x RIN , where RIN is an internal10kH, precision
resistor. Virtually all tolerance in EREF is due to IREF . Consequently, variations in IREF cause a shift in ~EF'
Scale Factor - Scale factor is the voltage change at the output
for a decade (Le., 10:1) change at the input, when connected
in the log mode. Error in scale factor is equivalent to a change'
in gain, or slope, and is specified in per cent of the nominal value. An external adjustment may be performed if fine trimming is desired for improved accuracy.
Table I. Converting Output Error in mV to Input Error
in %
LOG/ANTILOG AMPLIFIERS 7-13
OPTIONAL EXTERNAL ADJUSTMENTS FOR LOG
OPERATION
Trimming Eos - The amplifier's offset voltage, Eos' may be
trimmed for improved accuracy with the models 755,759
connected in its log circuit. To accomplish this, a 100kn., 10
turn pot is connected as shown in Figure 3. The input terminal,
Pin 4, is connected to ground. Under these conditions the output voltage is:
eOUT'= -K 10glO Eos/~EF
To obtain an offset voltage of 100JLV or less, for K = 1, the
trim pot should be adjusted until the output voltage is between +3 and +4 volts for models 755N, 759N, and -3V to
-4V for models 755P, 759P.
For other values of K, the trim pot should be adjusted for an
output of eOUT = 3 x K to 4 x K where K is the scale factor.
+16V -15V COM
TRIM
Figure 4. Functional Block Diagram
Principle of Operation - The antilog element converts the
voltage input, appearing at terminal 1, to a current which is
proportional to the antilog of the applied voltage. The currentto-voltage conversion is then completed by the feedback resistor in a closed-loop op amp circuit.
A more complete expression for the antilog function is:
CoUT = ~EF 10-e1N1K + Eos
The terms K, Eos' and ~F are those described previously in
the LOG section.
Offset Voltage (EOS) Adjustment - Although offset voltage
of the antilog circuit may be balanced by connecting it in the
log mode, and using the technique described previously, it may
be more advantageous to use the circuit of Figure 5. In this
configuration, offset voltage is equal to CoUT/100. Adjust for
the desired null, using the lOOk trim pot. After adjusting, turn
power off, remove the external lOOn. resistor, and the jumper
from Pin 1 to +15V. For 755P, 759P use the same procedure
but connect Pin 1 to -15V.
Figure 3. Trimming EOS in Log Mode
Reference Current or Reference Voltage - The reference current or voltage of models 755,759 may be shifted by injecting
a constant current into the unused scale factor terminal (Pin 1
or Pin 2). The current injected will shift the reference one
decade, in accordance with the expression: I, =66~ log
10~/IREF (755),1, = 330~ log 10JLA/IREF (759), where
I, =current to be injected and IREF = the desired reference
current.
By changing IREF , there is a corresponding change in EREF
since, ~EF = IREF x RIN . An alternate method for rescaling
EREF is to connect an external Rm, at the lIN terminal (Pin 5)
to supplant the 10kn. supplied internally (leaving it unconnected). The expression for ~EF is then, ~EF =RIN lREF .
Care must be taken to choose RIN such that (eg'G max)/RIN
';;;lmA.
Scale Factor (K) Adjustment - Scale factor may be increased
from its nominal value by inserting a series resistor RS between
the output terminal, Pin 3, and either terminal 1 or 2. The
table below should be consulted when making these scale
factor changes.
RANGEOFK
213V to 1.01 V
1.01 V to 2.02V
>2.02V
CONNECT
SERIES
RTOPIN
1
1
2
VALUEOFRs
Rx (K - 213)
Rx (K -1)
Rx (K-2)
NOTE
use pins 1, 2
use pin 1
use pin 2
Figure 5. Trimming EOS in Antilog Mode
Reference Voltage (EREF) Adjustment -In antilog operation,
the voltage reference appears as a multiplying constant. EREF
adjustment may be accomplished by connecting a resistor, R,
from Pin 5 to Pin 3, in place of the internal10kn.. The value
of R is determined by:
R =~EF desired/lO- S A
Scale Factor (K) Adjustment - The scale factor may be adjusted for all values of K greater than 2/3V by the techniques
described in the log section. If a value of K less than 2/3V is
desired for a given application, an external op amp would be
required as shown in Figure 6. The ratio of the two resistors is
approximately:
R1I~ =(11K - 1) where K =desired scale factor
R = 15kn (755); 3kn (759)
Table 2. Resistor Selection Chart for Shifting Scale Factor
ANTILOG OPERATION
The models 755 and 759 may be used to develop the antilog
of the input voltage when connected as shown in Figure 4.
The antilog transfer function (an exponential), is:
eOUT =~EF lO-eIN /K
[-2';;;eIN/K';;;2)
7-14 LOG/ANTILOG AMPLIFIERS
+16V
-15V
COM TRIM
Figure 6. Method for Adjusting K<2/3V
6-Decade, High Accuracy
Log Ratio Amplifiers
Models 757N/757P
r-IANALOG
WDEVICES
FEATURES
6 Decade Operation - 1 nA to 1 mA
1/2% Log Conformity -10nA to 100pA
Symmetrical FET Inputs
Voltage or Current Operetion
Temperature Compensated
I
MODEL 757 FUNCTIONAL BLOCK DIAGRAM
r--------------------,:
R1 '-BIG:
.,
ISIO
6
~
.,
-&ott
.,
: lV!D£C
1
,
I
I
I
APPLICATIONS
Absorbence Measurements
Log Ratios of Voltages or Currents
Data Compression
Trensducer Linearization
Rz
'-REF I
ezo-_y...-<44H-1--I
IREF=
~~
·2
:
II ..... I'""'--~
I
I
I
~--------------------~
-POSITIVE INPUT CURRENTS lAS SHOWN), USE
MODEL 767N. NEGATIVE INPUT CURRENTS,
USE MODEL 757P.
GENERAL DESCRIPTION
Model 757 is a complete, temperature compensated, dc-coupled
log ratio amplifier. It is comprised of two input channels for
processing signals spanning up to 6 decades in dynamic range
(InA to 1mA). By virtue of its symmetrical FET input stages,
the 757 can accommodate this 6 decade signal range at either
channel. Log conformity is maintained to within 112% over 4
decades of input (10nA to 100pA) and to within 1% over the
full input range. Unlike other log ratio designs, model 757
does not restrict the relative magnitude of the two signal inputs
to achieve rated performance. Either input can be operated
within the specified range regardless of the signal level at the
other channel.
The model 75 7 log-ratio amplifier design makes available both
input amplifier summing junctions. As a result, it can directly
interface with photo diodes operating in the shon-circuit current mode without the need of additional input circuitry.
The excellent performance of model 757 can be further improved by means of external scale factor and output offset
adjustments. A significant feature of model 757 not found
on competing devices is that, when the offset adjustment is
used to establish a fixed bias at the output, the output offset
level does not vary as a function of input signal magnitude. On
other designs, the sensitivity of output offset to input levels
results in output effects resembling log conformity errors.
CURRENT LOG RATIO
Current log ratio is accomplished by model 757 when two currents, ISIG and IREF, are applied directly to the input terminals
(see Figure 1). The two log amps process these signals providing
voltages which are proportional to the log of their respective
inputs. These voltages are then subtracted and applied to an
output amplifier. The scale factor, when connected as shown,
is 1VIdec. However, higher scale factors may be achieved by
connecting external scale factor adjusting resistors.
VOLTAGE LOG RATIO
The principle of operation for voltage log ratio is identical to
that of current log ratio after the voltage signal has been convened to a current. To accomplish this conversion, an external
resistor ~iS attachediiomthevoltage signal to the approi;rlate
input current terminal of the 757. Input currents are then
determined by:
eOSl =Input Offset Voltage (ISIG Channel)
eOSZ = Input Offset Voltage (IREF Channel)
Model 757 can operate with either current or voltage inputs.
Its excellent performance makes it ideally suited for log ratio
applications such as blood analysis, chromatography, chemical
analysis of liquids and absorbence measurements.
LOG/ANTILOG AMPLIFIERS 7-15
SPECIFICATIONS
(typical @+25°Cand Vs = ±15V dc unless otherwise noted)
MODEL
757N/P
OUTLINE DIMENSIONS
TRANSFER FUNCTION I
Current Mode
Dimensions shown in inches and (mm).
!---•.
yoltageMode
~J
ACCURACY
Log Conformlty2
ISIG,IREF = 10nA to IOOIIA
ISIG.IREF = InA to tmA
Scale Factor (1 VIDee)
vs Temperature (0 to +70°C)
= InA
IOnA to IOOnA
IOOnA to IJ.lA
IliA to lOOllA
Decreasmg Input Current
100llA to IliA
IlIA to lOOnA
IOOnA to IOnA
IOnA to InA
-v,
B
COM
:l
+V,
160Hz
60kHz
75kHz
Signal Channel
(IREF = 10llA)
2.Srns
250lls
25",
10",
INPUT NOISE
Voltage (10Hz to 10kHz)
Current (10Hz to 10kHz)
OUTPUT SPECIFICATIONS
Rated Output
Yoltage
Current
Resistance
Offset Voltage' (K = I V/Deeade)
vs Temperature (0 to +70oC)
vs Supply
POWER SUPPLY'
Rated Performance
Operating
Current, QUiescent
TEMPERATURE RANGE
Rated Performance
Operatmg
Storage
MECHANICAL
Case Size
Weight
5
'SIG
4
IREf
~?UT
OFF
ADJ
6
•
tv/
DEC
_
II
T
• .6'
1
~
TRANSFER CURVES
60Hz
30kHz
80kHz
IREF = IliA
IREF =·IOOIIA
InA to IOnA
9
0'(26)GRID~
= InA
RISE TIME
Increasmg Input Current
~~1~1
BOTIOM VIEW
ISIG = IliA
ISIG = IOOIIA
Reference Channel
0 04 (11)
(6.TO 64)
FREQUENCY RESPONSE, Slnewave
Small SIgnal Response (-3d B)
Signal Channel
IREF
U T
---11--
020T0025
±004%tC max
INPUT SPECIFICATIONS - Both Input Channels
Current
Signal Range, Rated Performance
Model7S7N
+lnAto+lmAmm
Model 757P
-InA to-lmA mm
Max Safe
±10mA max
(0, +) IOpA max
Bias Current,@ +2SoC
x2l+10°C
vs Temperature (0 [0 +70°C)
±lmVmax
Offset Voltage,@ +2S o C
0
vs Temperature (0 to +70 C)
±25/J.V/C max
'ISIG Channel
±25/J.V/C max
IREF Channel
±511V/%
vs Supply Yoltage
ISIG
I Ui~)
-.r----U
to 5%, max
±1%, max
(+0. -2%) max
~
6H38.• ) M A X - - - j
K=2V/DEC
Reference Channel
(lSIG = 101lA)
I.Oms
40lls
30",
2511s
10",
50",
500",
IOms
..
MODEL 757P
ISIG INPUT
3p.Vrms
o IpA rms
-'0
MODEL 757N
ISIG INPUT
..
Log mode output Voltage VI. input current for
IREF = 10~A.
±IOVmm
±SmAmm
O.In
±lSmVmax
±O 3mVlC
±511VIV
·2
757
±15V de
±(12 to 18)V de
±8mA
* + FOR 757N
- FOR 757P
Figure 2. Scale Factor Adjustment
o to +70o C
_25°C to +8S o C
_55°C to +12S oC
I Sn x 1.5" x04"
21 grams
NOTES
For model7S7N, K = +IV/Decade and mput currents must be POSItive. For
model 7S7P, K z -IV/Decade and input currents must: be negatIVe (Input currents are defined as positive when flowing into the Input terminals, 4 and S
Refer to TRANSFER CURVES)
: The log conformity error IS referred to Input (RTI). I % error RTI IS eqUivalent
to 4 3m V of error at the output for K = IV/Dec
3 Externally adjustable to zero
'" Recommended power supply: Analog Devices mode1904. ± 15V @ 5OmA.
"SEE SCALE FACTOR-OPTIONAL
ADJUSTMENT AND TRIMS (p.3)
R**
757
I
Specifications subject to change without notice.
7-16 LOG/ANTILOG AMPLIFIERS
*+ FOR 757N
• FOR 757P
-,sv
2Ok1l
Figure 3. Output Voltage Offset Adjustments
OPTIONAL ADJUSTMENTS AND TRIMS
Scale Factor - A one volt per decade scale factor is available
when pin 1 is tied to 3 and pin 7 is connected to 9. Higher
scale factors are possible by using a potentiometer, Rl> between pins 1 and 3 and a resistor, R2, between pins 7 to 9 as
shown in Figure 2. The value ofthe required resistor is (I 3.2kU)
(K-l) where K is the desired scale factor. The approximate
potentiometer value is also (13.2kU) (K-l). The scale factor
adjustment procedure is as follows:
1. Connect the appropriate value of resistor between pins
7 and 9.
2. Set IREF = IJ.lA, ISIG = lOJ.lA. Measure eo·
3. Set IREF = IJ.lA, ISIG = IOOJ.lA. Adjust Rl until the
difference in eo corresponding to steps 2 and 3 is K volts.
4. Repeat steps 2 and 3 until the change in eo = K volts.
Output Voltage Offset - Ou tpu t voltage offset must be adjusted
after the desired scale factor is established as indicated above.
To adjust the offset, inject equal dc input currents into the
reference and signal channels. The value of the input currents
should approximate the average input current levels expected
to be encountered in normal operation. Adjust the potentiometer shown in Figure 3 until the output voltage is zero.
LOG CONFORMITY
Log conformity in logarithmic devices is a specification similar
to linearity in linear devices. Log conformity error is the difference between the theoretical value of the log of a ratio and the
actual value that appears at the output of the log-ratio module
after scale factor errors have been eliminated. Measurement of
this error is made after initially zeroing the module at unityratio and adjusting the desired scale factor.
Figure 4 shows the log conformity performance of model 757
over a 6 decade input range. Log conformity for each channel
does not vary noticeably as the current is varied in the other
channel.
a:
Applying the Log Ratio Amplifier
"'" =
~1
0.5
~~
I
~
ffi~
~~
itHpLJll.L
~~
z 0
8"
'"g
~V
-r-.
0
lnA
l00nA
10nA
1#AA
10/JA
l00jJ.A
Vi
lrnA
INPUT CURRENT
Figure 4. Log Conformity Error for Model 757. Curve is for
Either Input Channel with Current Held Constant at 10J.LA
On Other Channel.
FREQUENCY CHARACTERISTICS
Figure 5 shows a plot of small signal response (-3dB) as a function of input signal current. The graph demonstrates the frequency response performance for each input channel over the
range of InA to ImA, independent of current on the other
channel.
lOOk
~
~
,/'
V/
10k
//
//
,. CHANNEX/
---T-7
SIGNAL
REFERENCE CHANNEL
//
Z
01.
lnA
lDnA
100nA
lilA
1O/JA
10DpA
lrnA
INPUT CURRENT
LOG/ANTILOG AMPLIFIERS 7-17
APPLICATIONS
Data Compression - Processing signals with wide dynamic
range is a common problem in instrumentation and data transmission. For example, digitizing an analog signal with a range'
of 10nA to 100/lA with 1% accuracy requires a 20 bit AID converter. (Required resolution =11100 x 1110,000 =1/106 9!!
11220 ).
By using the 757 with IREF adjusted to 10nA and K ser for
5/4 V/decade, the input data can be compressed into a 5 volt
output range. For a 1% resolution of any signal, the allowable
output error is 4.32mV x K. Log conformity contributes
2.17mV x K (0.5%) over this range. The remaining error with
K = 5/4 is 2.69mV and should correspond to less than the LSB
of the converter. With a 5 volt output range 2.69mV corresponds just over the LSB of an ll-bit converter. Thus the 757
module can compress the data for U$C with a 12 bit AID (such
as Analog Devices ADS74JD) to obtain the desired 1%
resolution.
Absorbence Measurements - Critical properties of materials
which are of particular interest in the fields of chemistry,
medicine, spectrometry and pollution control are characterized
by absorbence. The relationship between absorbence, A, and
light intensity, I, is: A =log 10llT where 10 =intensity of incident light, and IT = intensity of transmitted light.
Figure 6 shows the 757 log-ratio module used in such a photometer application. Two inpu ts represent the intensities of light
transmitted through space and through a medium that absorbs
light. The absorbence of the medium is given by the formula
A =log ISIGNAL
IREFERENCE
where ISIGNAL and IREFERENCE are the currents representing
the light intensities.
The transducers used in this application are photodiodes, which
provide a short-circuit current proportional to the intensiry of
applied light. The lowest value of absorbence is determined by
the value of IREF' since when ISIG =IREF' A =O. The output of the log-ratio module is externally trimmed to IVIdecade
and applied to the input of a 3Y.a-digit DPM through the scaling
nerwork R1 and R2.
Model 757 was chosen for this design because it makes available both amplifier summing junctions. When the photodiodes
are connected to the summing junctions, they are operated in
the short-circuit mode, that is, with zero volts across the diodes.
7-18 LOG/ANTILOG AMPLIFIERS
Short-circuit loading is necessary, because accuracy of the
photodiodes can be degraded several percent when operated
with as little as 100mV across the diode junction.
"SIGNAL"
PHOTOOIOOE
I
•• =_I",,!I!ll.
....-+-_ls.'G_ _----'~---"I3
ATTENUATOR TO
OPM LEVEL
!le_g .2OOmVF,S_1
I_E.
MODEL
AD20IO
3112-DIGIT
DPM
"REFERENCE"
PHOTODIODE
Figure 6. Model757NAppliedtoAbsorbenceMeasurements
INTERCONNECTION GUIDELINES
Model 757 is a complete log ratio amplifier that requires no
additional frequency compensation for proper operation.
Input Capacitance - Model 757is able to operate with 1000pF
at both input terminals. Therefore, the 757 can be used in applications requiring long cable lengths between the module
and the signal transducers.
Input-to-Output Capacitance - When using alog ratia.module
the user should take care in system configurations to avoid
excessive stray capacitance between input and output terminals.
Such precautions include avoiding running input and output
signal lines close together. If long cable runs are required where
inputs and output are closely bundled together, it is advisable
to enclose the inputs andlor output in separate, grounded electrostatic shields. By observing simple rules of good circuit
layout, problems with oscillations that may result from excessive input-to-Qutput capacitance can easily be avoided. Model
757 can accommodate up to 33pF of input-to-output capacitance without oscillation.
Leakage Resistance - Since model 757 can operate at extremely
low input current levels, precautions must be taken to prevent
current leakage into the input terminals. Such leakage can
cause errors when small input or reference currents are used.
This problem may arise on printed circuit layouts if the inputs
are run too close to the power supply busses. Providing an
etched guard around the input lines, connected to analog signal ground will also reduce unwanted current leakage.
RMS-to-OC Converters
Contents
Page
Selection Guide . . . . . . . . . . . . . . . . . . . . .
Orientation . . . . . . . . . . . . . . . . . . . . . . .
AD536A - Integrated Circuit, True rms-to-dc Converter
8-2
8-3
8-5
AD636 - Low Level True rms-to-dc Converter . . . . .
AD637 - High Precision Wideband rms-to-dc Converter
AD736 - Low Cost, Low Power, True rms-to-dc Converter
8 - II
8 - 17
AD737 - Low Cost, Low Power, True rms-to-dc Converter
8 - 29
8 - 25
RMS-TO-DC CONVERTERS 8-1
Selection Guide
RMS-to-OC Converters
Model
AD536A
AD636
AD637
AD736
AD737
Full-Scale
Range
Vrms
7
0.2
7
0.2
0.2
8-2 RMS- TO-DC CONVERTERS
Accuracy
mV± %ofReading
2.0
0.2
0.5
0.3
0.2
±
±
±
±
±
0.2
0.5
0.2
0.3
0.3
Frequency
Response
MHz
2
1.3
8
0.19
0.19
dB
Output
X
X
X
Page
Notes
8-5
8 - 11
8 - 17
8 - 25
8 - 29
General purpose
Highest accuracy
Buffered output, low power
Unbuffered output, low power
Orientation
RMS-to-OC Converters
RMS-to-DC converters continuously compute the instantaneous
square of the input signal, average it, and take the square root
of the result, to provide a dc voltage proportional to the rms of
the input (and, in the case of the ADS36, AD636 and AD736,
an auxiliary dc voltage that is proportional to the log of the rms,
for dB measurements).
Excellent pretrimmed performance, improvable by simple optional
trims, makes these devices ideal for all types of laboratory and
OEM rms instrumentation where amplitude measurements must
be made with high accuracy, independently of waveshape.
An alternative to rms that has been widely used in the past,
principally for measurements on sine waves, is mean absolutedeviation, or "ac average." It is performed by taking the absolute
value of a signal (i.e., rectifying it) filtering it and scaling it by
the ratio of rms to m.a.d. for sine waves, l.llI, so that it reads
correctly (for undistorted sine waves). Unfortunately, this ratio
varies widely as a function of the waveform; it will give grossly
incorrect results in many cases. The table shows a few representative examples comparing rms with m.a.d.
An important application is noise measurement - for example,
thermal noise, transistor noise, and switch-contact noise. True
rms measurement is a technique that provides consistent theoretically valid measurements of noise amplitude (standard deviation)
from different sources having different properties.
True rms devices are also useful for measuring electrical signals
derived from mechanical phenomena, such as strain, stress,
vibration, shock, expansion, bearing noise and acoustical noise.
WAVEFORM
o-q}
ItT,
~
The electrical signals produced by these mechanical actions are
often noisy, nonperiodic, nonsinusoidal, and superimposed on
dc levels, and require true rms for consistent, valid, accurate
measurements. RMS converters are also useful for accurate
measurements on low-repetition-rate pulse-trains having high
crest factors (ratio of peak to rms), and for measurements of the
energy content of SCR waveforms at differing firing angles.
The basic approach used in these converters for computing the
rms is to take the absolute value, square it and divide by the
fed-back output (using the logarithmic characteristics of transistor
junctions), and filter the result. The resulting approximation
is valid if the averaging time constant is sufficiently long compared
with the periods of the lowest frequency ac components of the
signal.
The simplest form of averaging involves a single-pole filter
using an external filtering capacitor (CAV)' Increased values of
capacitance for filtering will improve the accuracy for low frequency rms measurements and provide reduced ripple at the
output, but at the cost of increased settling time. For fastest
settling and minimum ripple, an additional stage of 2-pole filtering • •
is useful. The additional filtering permits improvement of settling
time or reduction of ripple (or both) because of substantial
reduction of CAY .
RMS
Vm
SINE WAVE
SYMMETRICAL
SQUARE WAVE
OR DC
TRIANGULAR WAVE
OR SAWTOOTH
J2
MAD
2
-;-V""
0707 Vm
0637 Vm
Vm
Vm
Vm
Vm
-n
2
.
RMS
MAD
>J2"'
1111
~~I I IT aft!
-7
-5
~
logo
~
0-1
.T
11. "DUTY CYCLE"
1
2
-n = 1732
-n
-1155
C.F
0
1
2
3
33
39
4
4.4
4.9
6
32%
4.8%
RMS
0
CREST FACTOR IS
THEORETICAllY
UNLIMITED. q IS
RMS
=0798 RMS
THE FRACTION OF
f:2
1253
TIME DURING WHICH
GREATER PEAKS CAN
BE EXPECTED TO
OCCUR
-1
Vm
.,f2 = 1414
1
GAUSSIAN NOISE
2J.~
i
CREST
FACTOR
PULSE TRAIN
•
1
0.26
0.0825
0.0166
0.01
MARK/SPACE
...
03333
0.0667
00159
0.0101
1
V.Vii
Vm
O.5V",
O.25Vm
O.125Vm
O.1Vm
v••
v.
O.25V""
O.0626Vm
00156Vm
O.01Vm
0.37%
0.1%
001%
83ppm
10ppm
1ppm
b10B
1
V.
Vii
1
2
4
8
10
1
2
4
8
10
RMS-TO-DC CONVERTERS 8-3
PERFORMANCE SPECIFICATIONS
Frequency for l%-of-Reading Error is the minimum value of
Considerable information regarding rms-io-dc converter circuit
design, performance, selection and applications is to be found in
the RMS-to-DC Conversion Application Guide. 1 In addition,
useful applications information can be found in the Nonlinear
frequency (at the high end) at which the error increases from
the midband value by 1% of reading. It is a function of peak-to-peak
input amplitude.
Circuits Handbook. 2
The most-salient feature of a true rms-to-dc converter is that it
ideally has no error due to an indirect approximation to the rms.
Frequency for -3dB Reading Error is the minimum value of
frequency (at the high end) at which the error may equal - 30%
of reading. It is a function of amplitude.
Crest Factar (to a property of the signal) is the ratio of peak
Static errors are due only to scale-factor, linearity and offset
errors; dynamic errors are due to insufficient averaging time at
the low end and finite bandwidth and slewing rate at the upper
end. Linearity errors affect crest factor in midband. DynanIic
errors are also a function of signal amplitude, due in part to the
variation of bandwidth of the "log" transistors with signal level.
Averaging Time Constant and External Capacitor: The time constant
Total Error, Internal Trim, a specification for quick reference, is
of the internal averaging filter, and the increase of time constant
per fLF of added external capacitance (CAV).
the maximum deviation of the dc component of the output
voltage from the theoretical output value over a specified range
of signal amplitude and frequency. It is shown as the sum of a
fixed error and a component proportional to the theoretical
output (% of reading). It is specified for a sinusoidal input in a
given frequency and amplitude range. The fixed error component
includes all offset errors and irreducible nonlinearities; the %-ofreading component includes the linear scale-factor error.
Total Error, External Adjustment is the amount by which the
output may differ from the theoretical value when the output
offset and scale factor have been trimmed. Note that the fixed
error-component cannot be reduced to zero, even though
the output offset can be nulled at zero input. This is because
of residual input offsets and inherent nonlinearities in the
converter.
Total Error vs. Temperature (Tmm to T"'''') is the average change
of %-of-full-scale error component plus the average change of
percent-of-reading error component per degree Celsius, over the
rated temperature range.
'RMS-to-DC CoDversion Application Guide 2nd Edition, by C. Kitchin
and L. Counts (1986-61 pages). Avallable free from Analog Devices.
'NOBIilJear Circuits lIJmdbook, Analog Devices, Inc., 1974, 1976,
536pp, edited by D.H. Sheingold. ($5.95).
8-4 RMS-TO-DC CONVERTERS
signal voltage to the ideal value of rms; the specified value of
crest factor is that for which the error is maintained within
specified limits at a given rms level for a worst-case - rectangular
pulse - input signal.
Input: The voltage range over which specified operation is obtained,
the maximum voltage for which the unit operates, the maximum
safe input voltage, and the effective input resistance.
Output: The maximum output range for rated performance, the
minimum current guaranteed available at full-scale output voltage,
and the source resistance of the output circuit.
Power Supply: Power-supply range for specified performance,
power-supply range for operation and quiescent current drain.
Temperature Range: The range of temperature variation for operation within specifications. Temperature coefficients are determined by three-point measurements (TH - 25°C), (25°C - TO,
when measured.
r'III ANALOG
Integrated Circuit
True rms-to-dc Converter
AD536A I
WDEVICES
FEATURES
True rms-to-dc Conversion
Laser-Trimmed to High Accuracy
0_2% max Error (AD536AK)
0_5% max Error (AD536AJ)
Wide Response Capability:
Computes rms of ac and dc Signals
450kHz Bandwidth: Vrms > 100mV
2MHz Bandwidth: V rms >1V
Signal Crest Factor of 7 for 1% Error
dB Output with 60dB Range
Low Power: 1_2mA Quiescent Current
Single or Dual Supply Operation
Monolithic Integrated Circuit
-55°C to +125°C Operation (AD536AS)
Low Cost
AD536A PIN CONNECTION AND
FUNCTIONAL BLOCK DIAGRAM
lOUT
NO
NC
NC
COM
BUF
OUT
BUF
IN
PRODUCT DESCRIPTION
The ADS36A is a complete monolithic integrated circuit which
performs true rms-to-dc conversion. It offers performance
which is comparable or superior to that of hybrid or modular
units costing much more. The ADS36A directly computes the
true rms value of any complex input waveform containing ac
and dc components. It has a crest factor compensation scheme
which allows measurements with 1% error at crest factors up
to 7. The wide bandwidth of the device extends the measurement capability to 300kHz with 3dB error for signal levels
above 100mV.
An important feature of the ADS36A not previously available
in rms converters is an auxiliary dB output. The logarithm of
the rms output signal is brought out to a separate pin to allow
the dB conversion, with a useful dynamic range of 60dB. Using
an externally supplied reference current, the OdB level can be
conveniently set by the user to correspond to any input level
from 0.1 to 2 volts rms.
The ADS 36A is laser trimmed at the wafer level for input and
output offset, positive and negative waveform symmetry (dc
reversal error), and full scale accuracy at 7V rms. As a result,
no external trims are required to achieve the rated accuracy
of the unit.
There is full protection for both inputs and outputs. The input
circuitry can take overload voltages well beyond the supply
levels. Loss of supply voltage with inputs connected will not
cause unit failure. The output is short-circuit protected.
The ADS36A is available in two accuracy grades (J, K) for
commercial temperature range (0 to +700 C) applications, and
one grade (S) rated for the -5 SO C to + 12SO C extended range.
The ADS36AK offers a maximum total error of ±2mV ±O.2%
-v,
of reading and the AD536AJ and AD536AS have maximum errors of ±SmV ±0.5% of reading. All three versions are
available in either a hermetically sealed 14-pin DIP or lO-pin
TO-100 metal can.
PRODUCT HIGHLIGHTS
1. The ADS36A computes the true root-mean-square level of
a complex ac (or ac plus dc) Input signal and gives an equivalent dc output level. The true rms value of a waveform is a
more useful quantIty than the average rectified value since
it relates directly to the power of the signal. The rms value
of a statistical signal also relates to its standard deviation.
2. The crest factor of a waveform is the ratio of the peak
signal swing to the rms value. The crest factor compensation scheme of the ADS36A allows measurement of highly
complex signals with wide dynamic range.
3. The only external component required to perform measurements to the fully specified accuracy is the capacitor
which sets the averaging period. The value of this capacitor determines the low frequency ac accuracy, ripple
level and settling time.
4. The ADS36A will operate equally well from split supplies or
a single supply with total supply levels from 5 to 36 volts.
The one milliampere quiescent supply current makes the
device well-suited for a wide variety of remote controllers
and battery powered instruments.
5. The AD536A directly replaces the ADS36, and provides
improved bandwidth and temperature drift specifications.
RMS-TO-DC CONVERTERS 8-5
SPECIFICATIONS
(@ +25"&, and ±15V de unless otherwise noted)
Model
ADS36AJ
Min
TRA:-;SFER Ft::-;CTlO:-;
VOLT::
CO:-;VERSIO:-; ACCt:RACY
Total Error, Internal TrIml (Figure I)
\'S Temperamre, T mIn to + 70"C
+ 70"C to + 12S"C
\oS Supply Voltage
de Reversal Error
Total Error, External Trlml (FIgure 2)
ERROR VS CREST FACTOR'
Crest Factor 1 to 2
Crest Factor'" 3
Crest Factor'" 7
VIN'" lOOmV
VIN=lV
::!: 3dB Bandwidth
V'N=lOmV
VIN = lOOmV
VIN=IV
AVERAGING TIME CONSTANT (Fagure 5)
OUTPUT CHARACTERISTICS
Offset Voltage, V IN = COM (Figure I)
vs. Temperature
vs Supply Voltage
Voltage SWing, = ISV Supphes
= SV Supply
=
IVrms
IOL T TERMINAL
IOL T Scale Factor
1m T Scale Factor Tolerance
OUtput Resistance
VoltageComphance
BUFFER AMPLIFIER
Input and Output Voltage Range
Yavg.(V IN )2
±2±0.2
~O
~0.05 ~0.005
1 :::001
::to.2
~2 ~O.I
±3 . . . 0.3
mV ..... % ofReadim~
~O.I
~O.I
% of Reading
~
1.0
~IO
%ofReadmg
5
45
120
5
45
120
5
45
120
kH,
kH,
kH,
90
450
23
90
450
2.3
90
450
2.3
kH,
kH,
MH,
25
25
25
ms/fLFCAV
Ot07
PACKAGE OPTIONS s
Ceramic DIP(D.14)
Metal Can TO-IOO(H·lOA)
Ot07
=7
±7
=25
20
=25
20
=25
20
13 33
~2
±2
16.67
05
±O 5
=01
I
+ l2.S
~1
Oto + 11
Oto +2
±O.6
±O 2
±O.3
+0.33
20
5
80
100
I
=20
30
=20
30
=10
20
25
05
~
+ 70
+ ISO
I
5
IS
:::: 15
:t 18
=30
+5
+36
12
2
±4
60
20
05
I
5
+36
~A
IJ-ANrms
%
kll
V
mV
nA
II
~ 130~A)
05
AD536AJD
AD536AJH
20
10'
20
:::: 18
~A
(+SmA,
~ 130~A)
= 15
% ofReadmgl°C
V
~0.5
±4
60
(+SmA,
I
5
dBrc
80
- Vslo(+Vs
5V)
20
10'
20
dB
mVldB
~2
~O.S
±4
60
±O.6
40
=20
=10
25
30
-Vsto(+Vs
25V)
20
V peak
kll
mV
mV
mV/oC
mVN
V
V
100
5)
~2.5V)
55
I
-V~to(+Vs
~2
5
Vrms
Vpeok
Vrms
V peak
±2
±0.2
=0.2
+ 12.5
-0.033
+0.33
20
5
40
V~
~2
~3
~0.O33
80
100
1667
08
~O
~3
(+SmA,
-130fLA)
0
~55
AD536AKD
AD536AKH
=30
+5
2
+70
+ 150
NOTES
I Accuracy IS specified for 0 to 7V nns, dc or lkH7 slnewave inPut with the AD536A connected as In the fig'lfe referenced
lError vs crest factor IS specified as an additional error for I V nns rectangular pulse mput, pulse wtdth = 200lJ-s
lInpul voltages areelo:pressed m volts nns, and error IS percent of reading
4Wlth 2k e):lernal pulldown resistor
'See Section 16 for packageouthne mformatlon
SpcclficauonssubJect tochangewlthout notice
8-6 RMS-TO-DC CONVERTERS
Oto + 11
Oto +2
-VSlo( +Vs
12
13.33
~I
:to
-V!<.lO(+V!<.
5V)
~
Ow2
=7
=0 I
+ 12 5
=0.5
20
10'
=20
=20
0[02
1667
08
40
=10
25
- V~ toC +
~ 2.5Vt
0
Specified Accuracy
Speclfied Accuracy
10
I
TEMPERATURE RANGE
Rated Performance
Storage
01
~
~O 033
+033
20
=30
+5
~O.I ~o
~O.I
~3
POWER SUPPLY
Voltage Rated Performance
Dual Supply
Smgle Supply
QUiescent Current
Total V.,. SV to 36V, TmHlIOT max
mV:::!:%ofReadmg
=0.1 =001
±Ol
=0.4
Short CirCuit Current
OUtput ReSistance
Small Signal Bandwidth
Slew Rate 4
±S :to.S
±O.l ±0.005
:1:0.3 :to.OO5
~3~03
=1
20
U ....
=0 I =0.01
=0.2
:to 1
5
Max
T ...
\favg. (V IN )2
mV ±%ofReadmgl"C
mV:t%ofReadmgl"C
mV:::%ofReadlOgl V
:!:%ofReadmg
=20
Oto + 11
Olo +2
Mi.
V OLI =
±S :to.S
Ot07
13 33
ADS36AS
Max
VOt'T = \favg (V,N;
~2
Input Offset Voltage, R., = 2Sk
Input Btas Current
Input Resistance
OutPUt Current
Typ
Min
Or02
dB OUTPUT (Figure 12)
Error, V IN 7mVto 7Vrms,OdB "" lVrms
Scale Factor
Scale FactorTC (Uncompensated, see Figure 12 forTemperatureCompensauon)
IRrrforOdB
IRrrRange
Max
Specified Accuracy
FREQt:E:-;CY RESPONSE'
Bandwtdthfor l%addltlOnalerror(O.09dB)
VIN:: IOmV
INPUT CHARACTERISTICS
Signal Range, = ISV Supphes
ContInuous rms Level
Peak Transient Input
Contmuousrms Level, = SV Supphes
Peak Transient Input, :::: SV Suppltes
Maximum Contmuous Nondestructive
Input Level (All Supply Voltages)
Input ReSistance
Input Offset Voltage
ADS36AK
Typ
= 18
+36
12
rnA
II
MH,
V/jJ.s
V
V
V
2
rnA
~55
+ 125
~55
+ 150
°C
"C
AD536ASD
AD536ASH
Specifications shown In boldface are tested on all production umts at final e1ectrl·
cal test Results from those tests are used 10 calculate outgoing quality levels All
mm and max specifications are guaranteed, although only those shown m
boldface are tested on all productIOn umts
Applying the AD536A
STANDARD CONNECTION
The AD536A is simple to connect for the majority of high
accuracy rms measurements, requiring only an external capacitor to set the averaging time constant. The standard connection is shown in Figure 1. In this configuration, the AD536A
will measure the rms of the ac and dc level present at the
input, but will show an error for low frequency inputs as a
function of the filter capacitor, CAY, as shown in Figure 5.
Thus, if a 41lF capacitor is used, the additional average error
at 10Hz will be 0.1 %, at 3Hz it will be 1%. The accuracy at
higher frequencies will be according to specification. If it is
desired to reject the dc input, a capacitor is added in series with
with the input, as shown in Figure 3; the capacitor must be
non-polar. If the AD536A is driven with power supplies with
a considerable amount of high frequency ripple, it is advisable
to bypass both supplies to ground with O.lIlF ceramic discs as '
near the device as possible.
The input and output signal ranges are a function of the supply voltages; these ranges are shown in Figure 16. The AD536A
can also be used in an unbuffered voltage output mode by disconnecting the input to the buffer. The output then appears
unbuffered across the 25k resistor. The buffer amplifier can
then be used for other purposes. Further the ADS 3 6A can be
used in a current output mode by disconnecting the 25k resistor from ground. The output current is available at pin 8 (pin
10 on the "H" package) with a nominal scale of 40llA per volt
rms input, positive out._
Figure 1. Standard rms Connection
The major advantage of external trimming is to optimize
device performance for a reduced signal range; the AD536A
is internally trimmed for a 7V rms full scale range.
Figure 2. Optional External Gain and Output Offset Trims
SINGLE SUPPLY CONNECTION
The applications in Figures 1 and 2 require the use of approximately symmetrical dual supplies. The AD536A can also be
used with only a single positive supply down to + 5 volts, as
shown In Figure 3. The major limitatIon of this connection is
that only ac signals can be measured since the differential in_.
put stage must be biased off ground for proper operation.
This biasing is done at pin 10; thus it is critical that no
extraneous signals be coupled into this point. Biasing can be
accomplished by using a resistive divider between +Vs and
ground. The values of the resistors can be increased in the
interest of lowered power consumption, since only 5 microamps of current flows into pin 10 (pin 2 on the "H" package).
AC input coupling requires only capacitor C 2 as shown; a dc
return is not necessary as it is provided internally. C2 is selected
for the proper low frequency break point with the input resistance of 16.7k!1; for a cut-off at 10Hz, C2 should be 11lF. The
signal ranges in this connection-are slightly more restricted
than in the dual supply connection. The input and output signal ranges are shown in Figure 16. The load resistor, RL, is
necessary to provide output sink current.
OPTIONAL EXTERNAL TRIMS FOR HIGH ACCURACY
If it is desired to improve the accuracy of the ADS 36A, the
external trims shown in Figure 2 can be added. R4 is used to
trim the offset. Note that the offset trim circuit adds 365!1 in
series with the internal 25k!1 resistor. This will cause a 1.5%
increase in scale factor, which is trimmed out by using Rl
as shown. Range of scale factor adjustment is ±1.5%.
The trimming procedure is as follows:
1. Ground the input signal, VIN, and adjust R4 to give zero
volts output from pin 6. Alternatively, ~ can be adjusted to
give the correct output with the lowest expected value of VIN.
2. Connect the desired full scale input level to VIN, either
dc or a calibrated ac signal (lkHz is the optimum frequency);
then trim RI to give the correct output from pin 6, i.e.,
1.000V dc input should give 1.000V dc output. Of course, a
±1.000V peak-to-peak sinewave should give a O. 707V dc output.
The remaining errors, as given in the specifications, are due to
the nonlinearity.
CAV
,---------1 j..!.+----~
10k to lk
Figure 3. Single Supply Connection
RMS-TO-DC CONVERTERS 8-7
CHOOSING THE AVERAGING TIME CONSTANT
The ADS36A will compute the rms of both ac and dc signals.
If the input is a slowly-varying dc, the output of the ADS36A
will track the input exactly. At higher frequencies, the average
output of the ADS36A will approach the rms value of the input signal. The actual output of the ADS 36A will differ from
the ideal output by a dc (or average) error and some amount
of ripple, as demonstrated in Figure 4.
,.
SETTLING
'\
7.6
r\.
TIME RELATIVE
T01Vrrm
INPUT
SETTLING
6.0
"-
TIME
2.5
...... ......
,.0
Eo
'mV
IDEAL
Eo
DC ERROR = Eo - Eo (IDEAL)
/
-
~
"I -"""'" -
_
T
AVERAGE Eo = Eo
DOUBLE-FREQUENCY
RIPPLE
TIME
Figure 4. Typical Output Waveform for Sinusoidal Input
The dc error is dependent on the input signal frequency and
the value of CA V. Figure 5 can be used to determine the minimum value of CA v which will yield a given percent dc error
above a given frequency using the standard rms connection.
The ac component of the output signal is the ripple. There are
two ways to reduce the ripple. The first method involves using
a large value of CAV. Since the ripple is inversely proportional
to CAV, a tenfold increase in this capacitance will effect a tenfold reduction in ripple. When measuring waveforms with high
crest factors, (such as low duty cycle pulse trains), the averaging time constant should be at least ten times the signal period. For example, a 100Hz pulse rate requires a lOOms time
constant, which corresponds to a 4pF capacitor (time constant =2Sms per pF).
,GOrnV
'OmV
,OV
1V
rms INPUT LEVEL
Figure 6. Settling Time vs Input Level
A better method for reducing output ripple is the use of a
"post-filter". Figure 7 shows a suggested circuit. If a singlepole filter is used (C 3 removed, Rx shorted), and C2 is approximately twice the value of CAv, the ripple is reduced as shown
in Figure 8, and settling time is increased. For example, with
CAY =1pF and C2 =2.2pF, the ripple for a 60Hz input is reduced from 10% of reading to approximately 0.3% of reading.
The settling time, however, is increased by approximately a
factor of 3. The values of CAY and C2 can therefore be reduced
to permit faster settling times while still providing substantial
ripple reduction.
The two-pole post-filter uses an active filter stage to provide
even greater ripple reduction without substantially increasing
the settling times over a circuit with a one-pole filter. The
values of CAv, C 2 • and C 3 can then be reduced to allow extremely fast settling times for a constant amount of ripple.
Caution should be exercised in choosing the value of CAV,
since the dc error is dependent upon this value and is independent of the post filter.
For a more detailed explanation of these topics refer to the
RMS to DC Conversion Application Guide 2nd Edition,
available from Analog Devices.
The primary disadvantage in using a large CAV to remove ripple is that the settling time for a step change in input level is
increased proportionately. Figure S shows that the relationship
between CAV and 1% settling time is 11 S milliseconds for each
microfarad of CA V. The settling time is twice as great for decreasing signals as for increasing signals (the values in Figure S
are for decreasing signals). Settling time also increases for low
signal levels, as shown in Figure 6.
100
I
\.
\.
I.
D,
DD'%~.J
;:::~~
••
I
'I-&:,
1
,.
I
.,
~'I-
"
,
.'1-
OCERROR
OR RIPPLE-
-
1\
:!:20%DUETO
COMPONENT TOLERANCE
,..-1
1 11\
1
\.
1 I
i%dj i"IOr + ~"'Pr-~ "i"ik)
1
10
100
\.
1k
\.
10k
O~
lOOk
INPUT FREQUENCY-Hz
Figure 5. ErrorlSettling Time Graph for Use with the
Standard rms Connection in Figure 1
8-8 RMS-TO-DC CONVERTERS
"-
0'''' 'OH.
r'\
~~K PK RIPPLE
CAY = 1p;F (FIG 1)
.~
PKPK
RIPPLE (ONE POLEI
CAY - 1liF, Cz - 2.2J,tF
,"
\
AVERAGING ERROR'"
om
,
,,., 1\ '(
VALUESFORCAvAND
1%SETTUNGTIME
FOR STATED%OFREADING
_~CCURACV
\
%of Readllll
~
5l
'"
'0%
1,\
"-I>
~'90'I>
~
Figure 7. 2 Pole "Post" Filter
\
Rx - 0
I
DC ERROR
CAy"1I'F
~~L FIL
1E"S)
"-
N
PK PK 100Hz
RIPPLE,
CAY ""'I'F
Cz .. C3 .. 2.2J,tF (TWO POLEI
1k
'" ,
'Ok
Figure 8. Performance Features of Various Filter Types
rms Measurements
AD536A PRINCIPLE OF OPERATION
The AD536A embodies an implicit solution of the rms equation that overcomes the dynamic range as well as other limitations inherent in a straight-forward computation of rms.
The actual computation performed by the AD536A follows
the equation:
VDllS
= Avg.
[
VIN 2 ]
V nns
Figure 9 is a simplified schematic of the AD5 36A; it is subdivided into four major sections: absolute value circuit (active rectifier), squarer/divider, current mirror, and buffer amplifier. The input voltage, VIN , which can be ac or dc, is converted to a unipolar current II, by the active rectifier AI, A 2 •
II drives one input of the squarer/divider, which has the
transfer function:
14 = 11 2/1 3
The output current, 14 , of the 5quarer/divider drives the current mirror through a low pass filter formed by R I and the
externally connected capacitor, CAv. If the R I , CAY time
constant is much greater than the longest period of the input
signal, then 14 is effectively averaged. The current mirror returns a current 13 , which equals Avg. [141, back to the squarer/
divider to complete the implicit rms computation. Thus:
14
=
Avg. [11 2 /141
=
PAD NUMBERS CORRESPOND TO PIN NUMBERS FOR THE TO 116 14 PIN CERAMIC DIP PACKAGE
NOTE
'BOTH PADS SHOWN MUST BE CONNECTED TO VIN
THE A0536A IS AVAILABLE IN LASER TRIMMED CHIP FOAM
CONSULT ANALOG DEVICES' CATALOG FOR SPECIFICATIONS
AND APPLICATION DETAILS
Figure 10. Chip Dimensions and Pad Layout.
Dimensions shown in inches and (mm).
lOUT
II rms
The current mirror also produces the output current, 'oUT'
which equals 214. 'oUT can be used directly or converted to
a voltage with R2 and buffered by A4 to provide a low impedance voltage output. The transfer function of the AD536A
thus results:
Figure 11. AD536A Pin Connections and Functional Diagram
The dB output is derived from the emitter of 100mV
Signal Crest Factor of 6 for 0_5% Error
dB Output with 50dB Range
Low Power: 800j.lA Quiescent Current
Single or Dual Supply Operation
Monolithic I ntegrated Circuit
Low Cost
Available in Chip Form
PRODUCT DESCRIPTION
The AD636 is a low power monolithic IC which performs true
rrns-to-dc conversion on low level signals. It offers performance which is comparable or superior to that of hybrid and
modular converters costing much more. The AD636 is specified for a signal range of 0 to 200 millivolts rms. Crest factors
up to 6 can be accommodated with less than 0.5% additional
error, allowing accurate measurement of complex input
waveforms.
The low power supply current requirement of the AD636,
typically 800j.lA, allows it to be used in battery-powered
portable instruments. A wide range of power supplies can be
used, from ±2.5V to ±16.5V or a single +5V to +24V supply.
The input and output terminals are fully protected; the input signal can exceed the power supply with no damage to
the device (allowing the presence of input signals in the
absence of supply voltage) and the output buffer amplifier
is short-circuit protected.
The AD636 includes an auxiliary dB output. This signal is
derived from an internal circuit point which represents the
logarithm of the rms output. The OdB reference level is set
by an externally supplied current and can be selected by the
user to correspond to any input level from OdBm (774.6mV)
to -20dBm (77.46mV). Frequency response ranges from
1.2MHz at a OdBm level to over 10kHz at -50dBm.
The AD636 is designed for ease of use. The device is factorytrimmed at the wafer level for input and output offset, positive and negative waveform symmetry (de reversal error), and
full scale accuracy at 200mV rrns. Thus no external trims are
required to achieve full rated accuracy.
Low Level
True rms-to-dc Converter
AD636 I
AD636 FUNCTIONAL BLOCK DIAGRAM
is accurate within ±0.2mV to ±0.3% of reading. Both versions
are specified for the 0 to +70 o C temperature range, and are
offered in either a hermetically sealed 14-pin DIP or a 10-pin
TO-100 metal can.
PRODUCT HIGHLIGHTS
1. The AD636 computes the true root-mean-square of a complex ac (or ac plus de) input signal and gives an equivalent
de output level. The true rrns value of a waveform is a
more useful quantity than the average rectified value since
it is a measure of the power in the signal. The rrns value
of an ac-coupled signal is also its standard deviation.
2. The 200 millivolt full scale range of the AD636 is compatible with many popular display-oriented analog-to-digital
converters. The low power supply current requirement
permits use in battery-powered hand-held instruments.
3. The only external component required to perform measurements to the fully specified accuracy is the averaging
capacitor. The value of this capacitor can be selected for
the desired trade-off of low frequency accuracy, ripple, and
settling time.
4. The on-chip buffer amplifier can be used to buffer either
the input or the output. Used as an input buffer, it provides accurate performance from standard 10MU input
attenuators. As an output buffer, it can supply up to 5
milliamps of output current.
5. The AD636 will operate over a wide range of power supply voltages, including single +5V to +24V or split ±2.5V
to ±16.5V sources. A standard 9V battery will provide
several hundred hours of continuous operation.
The AD636 is available in two accuracy grades; the AD636J
has a; total error of ±O.5mV ±0.6% of reading, and the AD636K
RMS-TO-DC CONVERTERS 8-11
SPECIFICATIONS
(@
Model
Min
TRANSFER FUNCfION
+25"&. and +Vs= +3V. -Vs= -5V unless otheIwise noted)
AD636K
AD636J
Typ
VOUT
Max
Min
~ Vav,. (VIN)'
Typ
VOUT
Max
Voits
±0.2±0.3
±0.1 :to.005
mV±%ofReadlltg
mV ±% ofReadingrC
mV ±%ofReadingIV
% of Reading
mV ±%ofReading
~ Vavg.(VINY
CONVERSION ACCURACY
Total Errot, Internal Trim 1,2
%0.5 ±0.6
:to.1:t0 01
vs. Temperature,Oto +7O"C
vs. Supply Voltage
:to.l :to.Ol
±0.2
±0.3 :to.1
de Reversal Error at 200mV
Total Error. External Trim'
ERROR VS.CRESTFACTOR'
Crest Factor 1 to 2
Crest Factor
Crest Factor
Specified Accuracy
=3
=
±0.1 ±0.01
±O,l
:to.1 :to.1
SpeafiedAccuracy
-0.2
-0.5
-0.2
-0.5
6
AVERAGING TIME CONSTANT
25
% of Reading
%ofReading
ms/f.lFCAV
25
INPUT CHARACTERISTICS
Signal Range, All Supplies
Continuous nns Level
Peak Transient Inputs
+3V, -SVSupply
Oto200
±2.SVSupply
±5VSupply
mVrms
Oto200
±2.8
±2.0
±5.0
±2.8
±2.0
±5.0
Vpk
Vpk
Vpk
±12
8
±0.2
Vpk
kO
mV
Maximum Continuous Non-Destructive
Input Level (All Supply Voltages)
Input ReSIstance
5.33
±12
8
±0.5
6.67
Input Offset Voltage
FREQUENCY RESPONSE"
Bandwidth for 1% addItional error (O.09dB
VIN=lOmV
VIN=lOOmV
V1N = 200mV
:!: 3dB Bandwidth
VIN=lOmV
VIN = lOOmV
V1N = 200mV
OUTPUTCHARACfERISTICS'
Offset Voltage, VIN=COM
vs Temperature
vs. Supply
Voltage Swmg
+3V, -SVSupply
±5Vto ± 16.5VSupply
Output Impedance
= IVnns
6.67
14
90
130
90
14
130
kHz
kHz
kHz
100
900
1.5
100
900
1.5
kHz
MHz
MHz
±O.S
±0.2
±10
±O.l
Oto +1.0
Oto +1.0
8
dB OUTPUT
Error,VIN = 7mVto300mVrms
Scale Factor
Scale FactorTemperatureCoefficlent
IREFforOdB
IREFRange
5.33
2
1
+1.4
10
12
±0.3
-3.0
+0.33
-0.033
4
Oto + 1.0
Oto +1.0
8
±O.S
8
50
2
1
+1.4
10
±O.l
-3.0
+0.33
-0.033
4
mV
~VI"C
±10
±0.1
mVN
12
±0.2
V
V
kn
dB
mY/dB
% ofReadingf'C
8
50
dBI"C
.,A
.,A
lOUT TERMINAL
lOUT Scale Factor
lOUT Scale FactorTolerance
-20
Output Resistance
Voltage Comphance
8
BUFFER AMPLIFIER
Input and Output Voltage Range
Input Offset Vohage, Rs= 10k
Input BiaS Current
Input ReSistance
Output Current
-Vsto(+Vs
-2V)
TEMPERATURE RANGE
Rated Performance
Storage
-20
8
±O.5
20
10'
60
(+5mA,
-13O.,A)
±I
60
V
mV
nA
n
16.5
+24
:!::
0.80
+2, -2.5
+5
+70
+150
±16.s
+24
0.80
1.00
0
-55
MHz
V/J.l.s
+3, -5
+3, -5
0
-55
AD636JD
AD636JH
V
rnA
+70
+ 150
·C
·C
AD636KD
AD636KH
SWith IOkO pull down resJstorfrom pm6 (BUF OUT) to - Vs.
specified forO to 200mV rms, de or 1kHz smewave mput
Accuracy IS degraded at lugber rms signal levels
2Measured atpm 8 ofDIP(louT), with pm 9 [led to common.
~ltbBUF input ned toCommon.
1Accuracy
3Error vs. crest factor is specnred as adthnonal error for a 100mV rms
rectangular pulse tram, pulse WIdth = 2oop.s.
V
V
1.00
NOTES
8-12 RMS-TO-OC CONVERTERS
V
mA
20
1
5
+1, -1.5
+5
4Input voltages are expressed m voItsrms.
p.AIVrms
%
kO
(+5mA,
- I30~A)
20
1
5
PACKAGE OPTIONS'
TO·116(D-14)
TL·loo(H-10A)
100
±IO
+20
10
12
-Vsto(+Vs
-2V)
-Vsto(+Vs
-2V)
±2
±0.8
20
10'
Short Crrcuit Current
Small Signal BandWIdth
Slew Rate 5
POWER SUPPLY
Voltage, Rated Performance
DualSuply
Stngle Suply
QUIescent Current6
100
±IO
+20
10
12
-Vsto(+Vs
-2V)
7See Secuon 16 for package outline informanon.
Specificanons subject to change WIthout nonce
SpecifICations shown In boldface are tested on all productlon uruts at fmal
electncal test. Results from those tests are used to calculate outgomg quality
levels. All mm and max specificauons are guaranteed, although only those
shown m boldface are tested on all productlOn UlUts.
Applying the AD636
STANDARD CONNECTION
The AD636 is simple to connect for the majority of high
accuracy rms measurements, requiring only an external capacitor to set the averaging time constant. The standard connection is shown in Figure 1. In this configuration, the AD636
will measure the rms of the ac and dc level present at the
input, but will show an error for low frequency inputs as a
function of the filter capacitor, CAY, as shown in Figure 5.
Thus, if a 4pF capacitor is used, the additional average error
at 10Hz will be 0.1 %, at 3Hz it will be 1%. The accuracy at
higher frequencies will be according to specification. If it is
desired to reject the dc input, a capacitor is added in series with
with the input, as shown in Figure 3; the capacitor must be
non-polar. If the AD636 is driven with power supplies with
a considerable amount of high frequency ripple, it is advisable
to bypass both supplies to ground with O.lJ.lF ceramic discs as
near the device as possible. CF is an optional output ripple
filter, as discussed elsewhere in this data sheet.
The input and output signal ranges are a function of the supply voltages as detailed in the specifications. The AD636 can
also be used in an unbuffered voltage output mode by disconnecting the input to the buffer. The output then appears
unbuffered across the 10k resistor. The buffer amplifier can
then be used for other purposes. Further, the AD6 36 can be
used in a current output mode by disconnecting the 10k resistor frqm the ground. The output current is available at
pin 8 (pin 10 on the "H" package) with a nominal scale
of 100pA per volt rms input, positive out.
±200mV peak-to-peak sinewave should give a 141.4mV dc output. The remaining errors, as given in the specifications, are
due to the nonlinearity.
SINGLE SUPPLY CONNECTION
The applications in Figures 1 and 2 assume the use of dual
power supplies. The AD636 can also be used with only a
single positive supply down to +5 volts, as shown in
Figure 3. Figure 3 is optimized for use with a 9 volt battery.
The major limitation of this connection is that only ac
signals can be measured since the input stage must be biased
off ground for proper operation. This biasing is done at pin
10; thus it is critical that no extraneous signals be coupled into
this point. Biasing can be accomplished by using a resistive
divider between +Vs and ground. The values of the resistors
can be increased in the interest of lowered power consumption, since only 1 microamp of current flows into pin 10 (pin
2 on the "H" package). Alternately, the COM pin of some
CMOS ADCs provides a suitable artificial ground for the
AD636. AC input coupling requires only capacitor C2 as
sh0:-vn; a dc return is not necessary as it is provided internally.
C2 IS selected for the proper low frequency break point with
the input resistance of 6. 7kQ; for a cut-off at 10Hz, C2 should
be 3.3pF. The signal ranges in this connection are slightly more
restricted than in the dual supply connection. The load resistor, RL, is necessary to provide current sinking capability.
Figure 2. Optional External Gain and Output Offset Trims
Figure 1. Standard rms Connection
OPTIONAL EXTERNAL TRIMS FOR HIGH ACCURACY
If it is desired to improve the accuracy of the AD636, the
external trims shown in Figure 2 can be added. R4 is used to
trim the offset. The scale factor is trimmed by using Rl
as shown. The insertion of R2 allows Rl to either increase
or decrease the scale factor by ±1.5%.
The trimming procedure is as follows:
1. Ground the input signal, VIN, and adjust R4 to give zero
volts output from pin 6. Alternatively, ~ can be adjusted to
give the correct output with the loweSt expected value of VIN'
2. Connect the desired full scale input level to VIN, either
dc or a calibrated ac signal (1kHz is the optimum frequency);
then trim R, to give the correct output from pin 6, i.e.,
200mV dc input should give 200mV dc output. Of course, a
Figure 3. Single Supply Connection
RMS-TO-DC CONVERTERS 8-13
CHOOSING THE AVERAGING TIME CONSTANT
The AD636 will compute the rms of both ac and dc signals.
if the input is a slowly-varying dc voltage, the output of the
AD636 will track the input exactly. At higher frequencies,
the average output of the AD636 will approach the rms value
of the input signal. The actual output of the AD636 will differ
from the ideal output by a dc (or average) error and some
amount of ripple, as demonstrated in Figure 4.
Eo
IDEAL
f
Eo
DC ERROR =
Eo (IDEAL)
Eo -
TIME
Figure 4. Typical Output Waveform for Sinusoidal Input
The dc error is dependent on the input signal frequency and
the value of CA V. Figure 5 can be used to determine the minimum value of CAV which will yield a given % dc error above
a given frequency using the standard rms connection.
..
,
••
1
,. "
~
J
~
I'\.
I'\.
"
~
'%
I'\. '.%~
~
I
.~~o.,.
"'%....~~ it
1>~~
'S'
VALUES FORC"vAND
I'\.
l'\.
1%SeTILlNGTIME
FORSTATED%QFREADING
I I II
-"lode ER~~R
1
,.
I
I'\.
I'\.
AVERAGING ERRORACCURACY ±20%DUETO
COMPONENT TOLERANCE
f--.-Ir
I
~
I'\.
.,
°0,%
.1.
,.
..,
The primary disadvantage in using a large CA V to remove ripple is that the settling time for a step chanl(e in input level j.
increased proportionately. Figure 5 shows the the relationship
between CAV and 1% settling time is 115 milliseconds for
each microfarad of CAV. The settling time is twice as great
for decreasing signals as for increasing signals (the values in
Figure 5 are for decreasing signals). Settling time also increases for low signal levels, as shown in Figure 6.
A better method for reducing output ripple is the use of a
"post-filter". Figure 7 shows a suggested circuit. If a singlepole filter is used (C 3 removed, Rx shorted), and C 2 is approximately 5 times the value of CAV, the ripple is reduced as
shown in Figure 8, and settling time is increased. For example, with CAV = 11lF and C2 = 4.7 IlF, the ripple for a
60Hz input is reduced from 10% of reading to approximately 0.3% of reading. The settling time, however, is increased
by approximately a factor of 3. The values of CA V and ~
can therefore be reduced to permit faster settling times
while still providing substantial ripple reduction.
I'\.
I'\.
II
+ %RIPPLE I~iak)
100
I'\.
,.k
lk
1'0..
..
lOOk
,
Figure 7. 2 Pole "Post" Filter
INPUT FREQUENCY - Hz
Figure 5. Error/Settling Time Graph for Use with the Standard
rms Connection
The ac component of the output signal is the ripple. There are
two ways to reduce the ripple. The first method involves using
a large value of CA V. Since the ripple is inversely proportional
to CA V, a tenfold increase in this capacitance will effect a tenfold reduction in ripple. When measuring waveforms with high
crest factors, (such as low duty cycle pulse trains), the averaging time constant should be at least ten times the signal period. For example, a 100Hz pulse rate requires a lOOms time
constant, which corresponds to a 41lF capacitor (time constant = 25ms per IlF).
The two-pole post-filter uses an active filter stage to provide
even greater ripple reduction without substantially increasing
the settling times over a circuit with a one-pole filter. The
values of CA V, C2 , and C3 can then be reduced to allow extremely fast settling times for a constant amount of ripple.
Caution should be exercised in choosing the value of CAY,
since the dc error is dependent upon this value and is independent of the post filter.
For a more detailed explaination of these topics refer to
the RMS-to-DC Conversion Application Guide, 2nd Edition,
available from Analog Devices.
,.%
100
~~~~~~~ATlVE
rOSETTLING
TIME AT
200mV rms
75
5.0
2.
""
10
o
lmV
DC ERROR
OR RIPPLE%01 Reading
~
1%
""
tOmV
\
"-
Pr ~
,I',
\'
'-....
\
fOOrnV
mlS INPUT LEVEL
1V
.1%
tOHz
Figure 6. Settling Time vs. Input Level
~ ~K PK RIPPLE
CAY = ljJF (FIG 1)
~
PKPK
RIPPLE (ONE POLE)
CAV -l$'F.C2=47jJF
~
,,
PK PK
Rx - 0
ERRO~
DC
CAV = 1J.1F
(ALL FILTERS)
N
100Hz
~
"\.
~
tk
10k
RIPPLE,
CAv=lpF
~ - ~ m 4 7pF (TWO POLE)
Figure 8. Performance Features of Various Filter Types
8-14 RMS-TO-DC CONVERTERS
rms Measurements
AD636 PRINCIPLE OF OPERATION
The AD636 embodies an implicit solution of the rms equation that overcomes the dynamic range as well as other limitations inherent in a straight-forward computation of rms.
The actual computation performed by the AD636 follows
the equation:
VDIlS = Avg.
[
VIN
2
]
V nns
Figure 9 is a simplified schematic of the AD636; it is subdivided into four major sections: absolute value circuit (active rectifier), squarer/divider, current mirror, and buffer amplifier. The input voltage, VIN , which can be ac or dc, is converted to a unipolar current II , by the active rectifier A I, A2.
II drives one input of the squarer/divider, which has the
transfer function:
14 = 11 2/13
The output current, 14 , of the squarer/divider drives the current mirror through a low pass filter formed by RI and the
externally connected capacitor, CAY. If the R I , CAY time
constant is much greater than the longest period of the input
signal, then 14 is effectively averaged. The current mirror returns a current 13 , which equals Avg. [I4] , back to the squarer/
divider to complete the implicit rms computation. Thus:
THE AD636 BUFFER AMPLIFIER
The buffer amplifier included in the AD636 offers the user
additional application flexibility. It is important to understand
some of the characteristics of this amplifier to obtain optimum
performance. Figure 10 shows a simplified schematic of the
buffer.
Since the output of an rms-to-dc converter is always positive,
it is not necessary to use a traditional complementary Class
AB output stage. In the AD636 buffer, a Class A emitter
follower is used instead. In addition to excellent positive output voltage swing, this configuration allows the output to
swing fully down to ground in single-supply applications
without the problems associated with most IC operational
amplifiers.
+1Is
.,
BUFFER
INPUT
o
I
I
______ ,..",.,_.Jo
REXTERNAL
IOPTIONAL, SEe TeXT)
-lis
Figure 10. AD636 Buffer Amplifier Simplified Schematic
The current mirror also produces the output current, 'oUT'
which' equals 214. loUT can be used directly or converted to
a voltage with R2 and buffered by A4 to provide a low impedance voltage output. The transfer function of the AD636
thus results:
The dB output is derived from the emitter of Q3, since the
voltage at this point is proportional to -log V IN. Emitter follower, Qs, buffers and level shifts this voltage, so that the
dB output voltage is zero when the externally supplied
emitter current (IREF) to Qs approximates 13 ,
CURRENT MIRROR
When this amplifier is used in dual-supply applications as an
input buffer amplifier driving a load resistance referred to
ground, steps must be taken to insure an adequate negative
voltage swing. For negative outputs, current will flow from the
load resistor through the 40kil emitter resistor, setting up a
voltage divider between -Vs and ground. This reduced effective -Vs will limit the available negative output swing of the
buffer. Addition of an external resistor in parallel with RE
alters this voltage divider such that increased negative swing
is possible.
Figure 11 shows the value of REXTERNAL for a particular
ratio of VPEAK to -Vs for several values of RLOAD' Addition
of REXTERNAL increases the quiescent current of the buffer
amplifier by an amount equal to REXT/-VS. Nominal buffer
quiescent current with no REXTERNAL is 30I.lAat -Vs = -SV.
• ...~ f~
,,'\.
ABSOLUTE VALUEI
VOLTAGE - CURRENT
CONVERTER
JJ
:!Ok
\
'\.
'\.
,
\ \
0.6
R4
""
\."
~
o
DIVIDER
Figure 9. Simplified Schematic
"",-""""
I' '\. ~=167kn
S
'\.
"-
'Ok
ONE - OUADRANT
SQUARER/
\
•
'''''
..
,"
'OOkO
--
R -6.7kn
,....
REXTERNAL
Figure 11. Ratio of Peak Negative Swing to - Vs VB.
REXTERNAL for Several Load Resistances
RMS-TO-DC CONVERTERS 8-15
FREQUENCY RESPONSE
The AD636 utilizes a logarithmic circuit in performing the
implicit rms computation. As with any log circuit, bandwidth
is proportional to signal level. The solid lines in the graph below represent the frequency response of the AD636 at input
levels from 1 millivolt to 1 volt rms. The dashed lines indicate the upper frequency limits for 1%, 10%, and ±3dB of
reading additional error. For example, note that a 1 ~olt rms
signal will produce less than 1% of reading additional error up
to 220kHz. A 10 millivolt signal can be measured with 1%
of reading additional error (100~N) up to 14kHz.
IW,
,1,'' '81\
,1VJLT,L,INJJT
II
200m
100m
j
200mV rms INPUT
I
... 10m
~
,
,
I
1m
"
_/~u~
"
//
""'<
,
I
1/
l
I
I
"-
/
"
><
"
1k
10k
1/
\
jJ---T--J
1\
::-n----l-n--=1
~ '-
+05
--
1\
I'
1M
10M
r--
FREQUENCY - Hz
Figure 12. AD636 Frequency Response
AC MEASUREMENT ACCURACY AND CREST FACTOR
Crest factor is often overlooked in determining the accuracy
A COMPLETE AC DIGITAL VOLTMETER
Figure 14 shows a design for a complete low power ac digital
voltmeter circuit based on the AD636. The 10MQ input attenuator allows full scale ranges of 200mV, 2V, 20V and
200V rms. Signals are capacitively coupled to the AD636
buffer amplifier, which is connected in an ac bootstrapped
configuration to minimize loading. The buffer then drives
the 6.7kQ input impedance of the AD636. The COM terminal of the ADC chip provides the false ground required by
the AD636 for single supply operation. An ADS89 1.2
volt reference diode is used to provide a stable 100 millivolt
reference for the ADC in the linear rms mode; in the dB mode,
elN (rms) = ZOOmV
-10
1
-- - -"--
CREST FACTOR
Figure 13. Error vs. Crest Factor
a 1N4148 diode is inserted in series to provi<;le correction
for the temperature coefficient of the dB scale factor. Calibration of the meter is done by first adjusting offset pot
R17 for a proper zero reading, then adjusting the R13 for an
accurate readout at full scale.
Calibration of the dB range is accomplished by adjusting R9
for the desired OdB reference point, then adjusting R14 for
the desired dB scale factor (a scale of 10 counts per dB is
convenient).
Total power supply current for this circuit is typically
2.8mA using a 7106-type ADC.
Dl
lN4148
~____~_____________+~v~s
1N~~48
H~--I,.,
+VOD
31/2 DIGIT
7106 TYPE
AID
CONVERTER
R7
20k
D'
1N4148
lXD 7543
Figure 14. A Portable, High Z Input, rms DPM and dB
Meter Circuit
8-16 RMS-TO-DC CONVERTERS
2~PS
CF = l/y'Ti
200ps
I'
lOOk
TJ '" DUTY CYCLE '"
o
\
[\
100
Figure 13 is a curve of reading error for the AD6 36 for a
200mV rms input signal with crest factors from 1 to 7. A rectangular pulse train (pulse width 200l1s) was used for this test
since it is the worst-case waveform for rms measurement (all
the energy is contained in the peaks). The duty cycle and peak
amplitude were varied to produce crest factors from 1 to 7
while maintaining a constant 200mV rms input amplitude.
A
J
,JJ.I
10ml rm} 'Nlu~ " "
1mv rms It
10%
I
100mV rms INPUT
30ml ,m!
30m
/1%
of an ac measurement. Crest factor is defined as the ratio of the
the peak signal amplitude to the rms value of the signal (C.F. =
Vp/Vrms )' Most common waveforms, such as sine and triangle
waves, have relatively low crest factors «2). Waveforms which
resemble low duty cycle pulse trains, such as those occurring
in switching power supplies and SCR circuits, have high crest
factors. For example, a rectangular pulse train with a 1% du ty
cycle has a crest factor of 10 (C.F. = 1I.J;i).
~ANALOG
WDEVICES
High Precision
Wideband rms-to-dc Converter
AD637
FEATURES
High Accuracy
0.02"10 Max Nonlinearity. 0 to 2V rms Input
0.10"10 Additional Error to Crest Factor of 3
Wide Bandwidth
8M Hz at 2V rms Input
600kHz at 100mV rms
Computes:
True rms
Square
Mean Square
Absolute Value
dB Output (60dB Range)
Chip Select-Power Down Feature Allows:
Analog "3-State" Operation
Quiescent Current Reduction from 2.2mA to 350,...A
Side-Brazed DIP or Low-Cost Cerdip
AD637 FUNCTIONAL BLOCK DIAGRAM
PRODUCT DESCRIPTION
The AD637 is a complete high accuracy monolithic rms to dc
converter that computes the true rms value of any complex
waveform. It offers performance that is unprecedented in integrated circuit rms to de converters and comparable to discrete
and modular techniques in accuracy, bandwidth and dynamic
range. A crest factor compensation scheme in the AD637 permits
measurements of signals with crest factors of up to 10 with less
than 1% additional error. The circuit's wide bandwidth permits
the measurement of signals up to 600kHz with inputs of 200mV
rms and up to 8MHz when the input levels are above 2V rms.
The AD637 is avai1able in two accuracy grades U, K) for commercial (0 to + 70°C) temperature range applications and one
(8) rated over the - 55°C to + 125°C temperature range. All
versions are avai1able in hermetically-sealed, 14-pin side-brazed
ceramic DIPs as well as low-cost cerdip packages.
As with previous monolithic rms converters from Analog Devices,
the AD637 has an auxiliary dB output available to the user. The
logarithm of the rms output signal is brought out to a separate
pin allowing direct dB measurement with a useful range of
6OdB. An externally programmed reference current allows the
user to select the OdB reference voltage to correspond to any
level between O.IV and 2.0V rms.
A chip select connection on the AD637 permits the user to
decrease the supply current from 2.2mA to 350,...A during periods
when the rms function is not in use. This feature facilitates the
addition of precision rms measurement to remote or hand-held
applications where minimum power consumption is critical. In
addition when the AD637 is powered down the output goes to a
high impedance state. This allows several AD637s to be tied
together to form a wide-band true rms multiplexer.
The input circuitry of the AD637 is protected from overload
voltages that are in excess of the supply levels. The inputs will
not be damaged by input signals if the supply voltages are lost.
PRODUCT HIGHLIGHTS
1. The AD637 computes the true root-mean-square, mean square,
or absolute value of any complex ac (or ac plus dc) input
waveform and gives an equivalent dc output voltage. The
true rms value of a waveform is more useful than an average
rectified signal since it relates directly to the power of the
signal. The rms value of a statistical signal is also related to
the standard deviation of the signal.
2. The AD637 is laser wafer trimmed to achieve rated performance
without external trimming. The only external component
required is a capacitor which sets the averaging time period.
The value of this capacitor also determines low frequency
accuracy, ripple level and settling time.
3. The chip select feature of the AD637 permits the user to
power down the device down during periods of nonuse,
thereby, decreasing battery drain in remote or hand-held
applications.
4. The on-chip buffer amplifier can be used as either an input
buffer or in an active filter configuration. The filter can be
used to reduce the amount of ac ripple, thereby, increasing
the accuracy of the measurement.
RMS-TO-OC CONVERTERS 8-17
SPECIFICATIONS
(@ +25"1:, and ±15V de unless otherwise noted)
Model
AD637AK
Typ
AD637AJ
Mi.
Typ
Max
Min
Your ~ Yavg (V,N)'
TRANSFER FUNCTION
V OVT
=:
AD637AS
Max
Mi.
Tyo
Max
Units
±l ±O.S
±6 ±O.7
mV:!:%ofReadmg
mV:!::%ofReadmg
150
300
0.25
0.04
0.05
%ofReadtng
Vom -= Vavg (V,Ni
v'avg (V1Ni
CONVERSION ACCURACY
±J ±O.S
±3.0±O.6
TotalError,IntemalTnm l (F1g 2)
T mm lOTlI1II;x
vs Supply+
30
100
vs Supply-
±O.S±O.2
±2.0 ±O.3
ISO
30
100
300
0.25
0.04
O.OS
de Reversal Error at 2V
NonhnearJty 2V Full Scalel
Nonhnearny 7V Full Scale
Total Error, External Trim
:to 5::tO 1
ERROR VS. CREST FACTOR'
Crest Factor 1 ta2
Crest Factor == 3
Crest Factor = 10
±O 5:tO I
±02S±OOS
Specified Accuracy
AVERAGING TIMECONSTANT
30
100
150
300
0.1
0.02
0.05
SpeClfied Accuracy
:to I
:to I
±IO
±IO
25
25
Specllied Accuracy
±O I
±IO
~VN
~VN
%ofFSR
%ofFSR
mV ±%ofReadmg
%ofReadmg
%ofReadmg
ms/ ....FCAV
25
INPUT CHARACTERISTICS
Signal Range, ::!:: ISV Supply
C..onnnuous rms Level
::!:
Ot07
Ot07
Peak TranSient Input
Signal Range,
::tIS
Vnns
Vp-p
,6
Vnns
Vp·p
±IS
96
±o 5
Vp·p
kIl
mV
Ot07
±IS
±15
SV Supply
ContinUOUS rms Level
Peak TranSient Input
Maximum ContlDuous Non-Destructive
Input Level (All SupplyVohages)
Input ReSistance
Input Offset Voltage
64
8
+ 12.0
Oto +2
6
dB OUTPUT
Error, V1N7mVto7Vrms,OdB = IVrms
Scale Factor
Scale Factor Temperature CoeffiCient
IRrrforOdB = IVnns
IRrrRange
BUFFER AMPLIFIER
,Input and Output Voltage Range
Input Offset Voltage
Input Current
Input ReSistance
OutPUt Current
5
I
64
8
1\
1\
66
200
kHz
kHz
kHz
150
I
8
150
I
8
150
I
8
kHz
MHz
MHz
0,1
::!:0.089
±004
+ 12.0
+135
Oto
+2.2
Oto +2
6
±O.S
0,0.056
±O 04
Oto + 12.0
+135
V
Oto +2
6
+22
V
mA
mA
MO
kO
20
OS
100
±I
-3
+033
-0033
20
±I
-3
+033
-0.033
20
±I
-3
+0.33
-0.033
20
5
I
80
100
-2 SV)
0,2
±lO
(+SmA,
0,1
±5
S
010+10
25
,02
±08
±2
10'
Oto + IO
25
±02
20
±2
±10
V
mV
.A
0
-130~A)
20
I
S
30
±05
dBfC
~
~
(+5mA,
130~A)
20
I
80
100
-2 SV)
zO S
±2
10"
(+5mA,
SlewRale~
5
I
dB
mVldB
% ofReadmgrc
-V~to(+Vs
-V"to(+V"
±O8
±2
10"
mA
MHz
V/....s
20
I
5
30
±OS
20
Oto + 10
25
±02
30
±O S
Open or + 2 4V lit)
This ripple can add a significant amount of uncertainty to the
accuracy of the measurement'being made. The uncertainty can
be significantly reduced through the use of a post filtering network
or by increasing the value of the averaging capacitor.
FOR 1 POLE
Ril
24kU
F1lTEfI.SHORT
R.AND
REMOVECl
"W
Figure 8. Two Pole Sal/en-Key Filter
RMS-TO-DC CONVERTERS 8-21
•
Figure 9a shows values of CAY and the corresponding averaging
, error as a function of sine-wave frequency for the standard rms
connection. The 1% settling time is shown on the right side of
the graph.
Figure 9b shows the relationship between averaging error, signal
frequency settling time and averaging capacitor value. This
graph is drawn for fllter capacitor values of 3.3 times the averaging
capacitor value. This ratio sets the magnitude of the ac and dc
errors equal at 50Hz. As an example, by using a I",F averaging
capacitor and a 3.3",F fllter capacitor the ripple for a 60Hz
input signal will be reduced from 5.3% of reading using the
averaging capacitor alone to 0.15% using the single pole fllter.
This gives a factor of thirty reduction in ripple and yet the
settling time would only increase by a factor of three. The values
of CAY and Cz, the fllter capacitor, can be calculated for the
desired value of averaging error and settling time by using
Figure 9b.
,
The symmetry of the input signal also has an effect on the magnitude of the averaging error. Table I gives practical component
values for various types of 60Hz input signals. These capacitor
values can be directly scaled for frequencies other than 60Hz,
i.e., for 30Hz double these values, for 120Hz they are halved.
RecommendedCAV andC2
M'nimum
AbsoluteValue
InputWavelorm
RxCAV
C,rcu,tWavefo.m
8ndPerrod
T,me
Constant
andPerrod
Valuesforl%Averagmg
Error(aSOHZWlthT=166ms
ValueCAV
ValueC2
112T
:---T----1
A
1%
~~:~~a7d'!Ilded ~~:~:ra';'dended ~,e:~mg
H
--if\P~~ __i0IY\_
o 47p.F
151-'-F
o 821-'F
27IJF
lOn-T,1
681'-F
22r. "
,
VAlUESOfC"v,C2 ANoelANO
I I III
I I III
I
,
"LU'N'U'
,,1..1,,1
RMS INPUT
III
1% SETTLING TIME FOR STATED "IoOF READING
AVERAGING ERROR'
2 POLE SALLEN-KEY FilTER
II
,
I
,
I
1V RMS INPUT
~:. /
1%
INPUT FREQUENCY - Hz
Figure 9b.
rt', ",
,
2V RMS INPUT
I
~~
'"
/
I
/
/
"",JdB
/
/
'"
r--
'"
tOOk
INPUT FREOUENCY _ Hz
*% de ERROR + % PEAK RIPPLE ACCURACY
±ZO% DUE TO COMPONENT TOLERANCE
~~
I
"i~"~I
~%~1i<:~o
$%~
Figure 10. Frequencv Response
,
-.o.
'9-S>O<9R
,
GO,
tOOk
INPUT FREOUENCY _ Hz
Figure 9c.
8-22 RMS-TO-DC CONVERTERS
To take full advantage of the wide bandwidth of the AD637
care must be taken in the selection of the input buffer amplifier.
To insure that the input signal is accurately presented to the
converter, the input buffer must have a -3dB bandwidth that
is wider than that of the AD637. A point that should not be
overlooked is the importance of slew rate in this application.
For example, the minimum slew rate required for a IV rms
5MHz sine-wave input signal is 44V/",s. The user is cautioned
that this is the minimum rising or fa1ling slew rate and that care
must be exercised in the selection of the buffer amplifier as
some amplifiers exhibit a two-to-one difference between rising
and falling slew rates. The AD381 is recommended as a precision
input buffer.
AC MEASUREMENT ACCURACY AND CREST FACTOR
Crest factor is often overlooked in determining the accuracy of
an ac measurement. Crest factor is defmed as the ratio of the
peak signal amplitude to the rms value of the signal (C. F. =
YrIV nns). Most common waveforms, such as sine and triangle
waves, have relatively low crest factors (:52). Waveforms which
resemble low duty cycle pulse trains, such as those occurring in
switching power supplies and SCR circuits, have high crest
factors. For example, a rectangular pulse train with a 1% duty
cycle has a crest factor of 10 (C.F. = 1Iv:Yj).
1..I--T--1
T)
,~
E
DUTY CYCLE
,
,
,
.,
,
CF = 10
,
,
..-----
,
/
/
-------
~V
.,
./
/
Cf '" 3
V'N_Vrms
~ l~S
CF=l/..;ri
Figure 13. Error vs. rms Input Level for Three Common
Crest Factors
"'IN (rm$)=lVottnn5
1001'S
CONNECTION FOR dB OUTPUT
Another feature of the AD637 is the logarithmic or decibel
output. The internal circuit which computes dB works well over
a {iOdB range. The connection for dB measurement is shown in
Figure 14. The user selects the OdB level by setting RI for the
proper OdB reference current (which is set to exactly cancel the
log output current from the squarer/divider circuit at the desired
OdB point). The external op amp is used to provide a more
convenient scale and to allow compensation of the + 0.33%;oC
temperature drift of the dB circuit. The special T.C. resistor R3
is available from Tel Labs in Londenderry, New Hampshire
(model Q-81) and from Precision Resistor Inc., Hillside, N.J.
(model PTl46).
'''~,----:':------::':-----::'.
PULSE WIDTH - JLS
Figure 11. AD637 Error vs. Pulse Width Rectangular Pulse
Figure 12 is a curve of additional reading error for the AD637
for a 1 volt rms input signal with crest factors from I to II. A
rectangular pulse train (pulse width 100fLS) was used for this
test since it is the worst-case waveform for rms measurement
(all the energy is contained in the peaks). The duty cycle and
peak amplitude were varied to produce crest factors from I to
10 while maintaining a constant I volt rms input amplitude.
,/'
...-/
f.-- I-I--
r--
POSITIVE
INPUT
PULSE
C"V = 22,..F
"lUI + 3500ppm
TC RESISTOR TEL LABS OS1
PRECISION RESISTOR PT146
OR EaUIVALENT
V
----
--
"'.
Figure 14. dB Connection
-............
~
dB CALIBRATION
1. Set YIN = 1.00Y dc or 1.00Y rms
~
2. Adjust RI for OdB out = O.OOV
3. Set VIN = O.IY dc or O.IOV rms
4. Adjust R2 for dB out = - 2.00V
Figure 12. Addilonal Error
VS.
Crest Factor
Any other dB reference can be used.by setting VIN and RI
accordingly.
RMS- TO-DC CONVERTERS 8-23
LOW FREQUENCY MEASUREMENTS
If the frequencies of the signals to be measured are below 10Hz,
the value of the averaging capacitor required to deliver even 1%
averaging error in the standard rms connection becomes extremely
large. The circuit shown in Figure 15 shows an alternative method,
of obtaining low frequency rms measurements. The averaging
time constant is determined by the product of R and CAY!> in
this circuit O.Ss/jl.F of CAY. This circuit permits a 20: 1 reduction
in the value of the averaging capacitor, permitting the use of
high quality tantalum capacitors. It is suggested that the two
pole Sallen-Key fIlter shown in the diagram be used to obtain a
low ripple level and minimize the value of the averaging
capacitor.
VECTOR SUMMATION
Vector summation can be accomplished through the use of two
AD637s as shown in Figure 16. Here the averag'u-.g capacitors
are omitted (nominal l00pF capacitors are used to insure stability
of the fIlter amplifier), and the outputs are summed as shown.
The output of the circuit is
Figure 15, A0637 as a Low Frequency rms Converter
If the frequency of interest is below 1Hz, or if the value of the
averaging capacitor is still too large, the 20: 1 ratio can be increased.
This is accomplished by increasing the value of R. If this is
done it is suggested that a low input current, low offset voltage
amplifier like the ADS42 be used instead of the internal buffer
amplifier. This is necessary to minimize the offset error introduced
by the combination of amplifier input currents and the larger
resistance.
Figure 16. A0637 Vector Sum Configuration
This concept can be expanded to include additional terms by
feeding the signal from pin 9 of each additional AD637 through
a 10k!} resistor to the summing junction of the AD611, and
tying all of the denominator inputs (pin 6) together.
If CAY is added to ICI in this configuration the output is
Vvi + V/ If the averaging capacitor is included on both
ICI and IC2 the output will be
Vvl + V
y2
This circuit has a dynamic range of IOV to IOmV and is limited
only by the O.5mV offset voltage of the AD637. The useful
bandwidth is 100kHz.
8-24 RMS- TO-~C CONVERTERS
Low-Cost, Low-Power
True rms-to-dc Converter
AU736
r.ANALOG
WDEVICES
FEATURES
COMPUTES
True rms Value
Average Rectified Value
Absolute Value
AD736 FUNCTIONAL BLOCK DIAGRAM
PROVIDES
200mV Full-Scale Input Range
High Input Impedance of 10120
Low Input Bias Current: 25pA max
High Accuracy: ±0.5mV ±0.5% of Reading
RMS Conversion with Signal Crest Factors Up to 5
Wide Power Supply Range: +2.SV, -3.2V
to ±16.5V
Low Power: 200llA max Supply Current
Buffered Voltage Output
No External Trims Needed for Specified Accuracy
AD737 ..:. An Unbuffered Voltage Output Version
with Chip Power Down is also Available
allows the choice of two signal input terminals: a
(10 12.0) FET input which will directly interface
tenuators and a low impedance (Sk.o) input
measurement of 300mV input levels, while
m the minimum power supply voltage of +2.SV,
e two inputs may be used either singly or
PRODUCT DESCRIPTION
The AD736 is a low-power, precision, monolitkic t
converter. It is laser trimmed to provide
.'
lessthan±0.5mV±0.5%ofreadi
'i:;i;..
e~IY.
FUrther:more, it maintains hig
A
achieves a 1% of reading error bandwidth exceeding
range of input waveforms, inc!
,;~ 10I'ilJz r input amplitudes from 20mV rms to 200mV rms
~!Vl ~,' {,,}lilt consuming only ImW.
and triac (phase) controlled si
ves. ];
physical size of this converter make it sJh ,
gra~'~
performance of non-rms "precision rectifiersij,in many ap~.~f' The AD7361S available In four performance grad~s. The AD736J
and AD736K grades are rated over the commercial temperature
tions. Compared to these circuits, the AD736 offers higher '<
accuracy at equal or lower cost.
range of 0 to + 70°C. The AD736A and AD736B grades are
rated over the industrial temperature range of - 40°C to + 85°C.
The AD736 can compute the rms value of both ac and de input
The AD736 is available in three low-cost S-pin packages: plastic
voltages. It can also be operated ac coupled by adding one external
mini-DIP, plastic SO and hermetic cerdip.
capacitor. In this mode, the AD736 can resolve input signal
levels of 10011V rms or less, despite variations in temperature or
PRODUCT HIGHLIGHTS
supply voltage. High acccuracy is also maintained for input
1. The AD736 is capable of computing the average rectified
waveforms with crest factors of 1 to 3. In addition, crest factors
value, absolute value or true rms value of various input
as high as 5 can be measured (while introducing only 2.5%
signals.
additional error) at the 200mV full-scale input level.
2. Only one external component, an averaging capacitor, is
The AD736 has its own output buffer amplifier, thereby providing
required for the AD736 to perform true rms measurement.
a great deal of design flexibility. Requiring only 200I1A of power
The
low power consumption of ImW makes the AD736
3.
supply current, the AD736 is optimized for use in portable
suitable for many battery powered applications.
multimeters and other battery powered applications.
JlfI
;rr
...
4. A high input impedance of 1012.0 eliminates the need for an
external buffer when interfacing with input attenuators.
5. A low impedance input is available for those applications
requiring up to 300mV rms input signal operating from low
power supply voltages.
RMS-TO-DC CONVERTERS
~25
SPECIFICATIONS
(@
+25"1: ± 5V supplies, ac coupled with 1kHz sine-wave input applied unless otherwide noted.)
Model
AD736J/A
Conditions
Min
TRANSFER FUNCTION
CONVERSION ACCURACY
Total Error, Internal Trim 1
All Grades
Typ
VOUT
AD736KIB
Max
Min
~ v'Avg. (VIN')
1kHz Sine Wave
acCoupled
0-200mVrms
2oomV·IVrms
0.2/0.2
1.2
@20OmVrms
@2oomVrms
0.007
Typ
VOUT
O.S/O.S
2.0
Max
Units
0.3/0.3
2.0
±mV/±%ofReading
±%ofReading
0.5/0.5
± mV/ ± % of Reading
± % ofReadingf'C
+0.1
-0.3
2.5
+0.35
%N
%N
~ v'Avg. (V IN')
0.2/0.2
1.2
Tnun-Tmax
A&BGrades
J&KGrades
vs. Supply Voltage
@200mVrmslnput
@200mVrmsInput
de Reversal Error, de Coupled
Nonlinearity', 0-2oomV
T ota! Error, External Trim
ERROR vs. CREST FACTOR'
Crest Factor 1 to 3
CrestFactor= 5
Vs~
±5Vto ±16.5V
±5Vto ±3V
@6oomVdc
@loomVrms
0-20OmVrms
Vs~
CAV,CF~
CAV,CF~
0.7/0.7
0
0
0
100,..F
loo,..F
+0.06
-0.18
I.3
+0.25
0.110.5
0.007
+0.1
-0.3
2.5
+0.35
0
0
+0.06
-0.18
0
I.3
+0.25
0.110.3
0.7
2.S
% of Reading
% of Reading
±mV ±%ofReading
% Additional Error
% Additional Error
0.7
2.S
INPUT CHARACTERISTICS
High Impedance Input (Pin 2)
Signal Range
Continuous rms Level
Continuous rms Level
Vs~
Peak Transient Input
Peak Transient Input
Peak Transient Input
Input Resistance
Input Bias Current
Vs~
Vs~
Vs~
Vs~
+2.8V, -3.2V
±SVto ±16.5V
+2.8V, -3.2V
±SV
± 16.5V
200
±2.7
10 12
1
Low Impedance Input (Pin 1)
Signal Range
Continuous rms Level
25
300
Continuous rms Level
Peak Transient Input
Peak Transient Input
Peak Transient Input
Input Resistance
Maximum Continuous NonDestructive Input
Input Offset Voltage'
J&KGrades
A&BGrades
vs. Temperature
vs. Supply
vs. Supply
OUTPUT CHARACTERISTICS
Output Offset Voltage
J&KGrades
A&BGrades
vs. Temperature
vs. Supply
6.4
Output Current
Short-Circuit Current
Output Resistance
9.6
All Supply Voltages
acCoupled
:!:
8
SO
80
Vs~
±SVIO ± 16.5V
Vs= ±SVto :!:3V
±O.l
I
Vs~
Vs~
OutPUI Voltage Swing
2kOLoad
2kOLoad
2kOLoad
No Load
1.7
±3.8
±11
8
:!:
Vs~
V,~
Vs~
Vs~
±5Vto±16.SV
±SVto±3V
+2.8V, -3.2V
±SV
± 16.SV
± 16.5V
@dc
8-26 RMS-TO-DC CONVERTERS
50
SO
010 + 1.6
Oto + 3.6
Oto +4
Oto+4
+1.7
+3.8
+5
+ 12
3
0.2
6.4
12
±3
±3
30
ISO
8
50
80
±O.S
±O.s
20
130
±O.l
1
SO
50
Oto
Oto
Oto
Oto
+1.6
+ 3.6
+4
+4
9.6
mVrms
Vrms
V
V
V
0
pA
mVnns
Vrms
V
V
V
kO
±12
Vp-p
±3
±3
30
ISO
'mY
mV
,..VI"C
,..VN
,..VN
±0.3
±0.3
20
130
mV
mV
,..VI"C
,..VlV
,..VN
+1.7
+3.8
+S
+ 12
V
V
V
V
3
0.2
rnA
rnA
0
Model
AD736J/A
Conditions
FREQUENCY RESPONSE
High Impedance Input (Pin 2)
For 1% Additional Error
V IN ~ ImVnns
V1N ~ IOmVnns
V1N ~ lOOmVrms
V1N ~ 200mVrms
:t 3dB Bandwidth
V1N ~ ImVrms
V1N ~ 10mVnns
VIN ~ lOOmVnns
VIN ~ 200mV nns
FREQUENCY RESPONSE
Low Impedance Input (Pin I)
For I % Additional Error
V IN ~ ImVnns
V IN ~ 10mVnns
V1N ~ lOOmVnns
V1N ~ 200mVnns
:t 3dB Bandwidth
VIN = ImVrms
V IN ~ IOmV rms
VIN ~ lOOmV nns
V1N ~ 200mVnns
Min
Min
Mu:
Typ
Max
Units
Sine-Wave Input
1
6
37
33
1
6
37
33
kHz
kHz
kHz
kHz
5
55
170
190
5
55
170
190
kHz
kHz
kHz
kHz
1
6
90
90
I
6
90
90
kHz
kHz
kHz
kHz
5
55
350,""
5
55
350
460
kHz
kHz
kHz
kHz
Sme-Wavelnput
Sine-Wave Input
Sine-Wave Input
,
\,
POWER SUPPLY
Operating Voltage Range
Quiescent Current
200mVnns, No Load
TEMPERATURE RANGE
Operating, Rated Performance
Commercial (0 to + 70'C)
Industrial ( - 4O"C to + 85"C)
AD736KIB
Typ
460i," "';,: ,
"
t,
:t5
160
230
.'.
:t 16.5
200
270
Volts
".A
".A
~\~~~
'",
,~
,"
'1-
"
AD736K
AD736B
-, '.:;>;
PACKAGE OPTIONS'
8-Pin Plastic Mini-DIP (N-8)
8-Pm PlaStiC SO (R-8)
8-PinCerdtp(Q-8)
',';~36jN
AD736KN
AD736KR
AD736BQ
AD736JR
AD736AQ
NOTES
I Accuracy IS specified with the AD736 connected as shown In FIgUre 1.
2Nonlineanty IS defined as the maxlDlum deVl3tIOn (m percent error) from a straight line connectIng
the readmgs at 0 and 200mV rms. Output offset voltage is adJusted to 7.erO.
3Error vs. Crest Factor is specified as additional error for a 200mV nns signal. C.F. = VPEAKN rms.
·OC offset does not blnit ae resolution.
5See Section 16 for package outhne mformatlon.
Specifications are subJect to change without nonce.
Specificanons shown m boldface are tested on all production units at final
Results from those tests are used to calculate outgomg qualIty levels.
~Iectncal
test.
ABSOLUTE MAXIMUM RATINGS 1
Operating Temperature Range
AD736J/K
Supply Voltage . . . . . .
Internal Power Dissipation
Input Voltage . . . . . . .
Output Short-Circuit Duration
Differential Input Voltage
Storage Temperature Range Q
Storage Temperature Range N, R .
±16.SV
200mW
.. ±Vs
Indefinite
+Vs and -Vs
- 6SoC to + IS0°C
- 6SoC to + 12SoC
....... .
AD736AIB . . . . . . . .
Lead Temperature Range (Soldering 6Osec)
o to +70°C
- 40°C to + 8SoC
+300OC
NOTE
IStresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
RMS-TO-DC CONVERTERS 8-27
Applications Circuits
L--------::c"
I+(OPTIONAll
POSITIVESUPPLY ---1:r--~
10l-lF
T
1 p.F
01fLF
COMMON - -....
I~--'
T
NEGATIVE SUPPLY
0'"''\7-v,
NEGATIVESUPPLY--.........
~-~.-
Figure 1. True rms Connection
OPTIONAL
V1N
0-,/ ACCOUPLING
CAPACITOR
.L
01J.l.F
'kV
200mV
9M
900k
90k
+
C,
(OPTIONALI
10J.lF
Figure 3. Connection to HI Z Input Attenuator
CF
10J.lF
(OPTIONAL)
Figure 4. Connection for Battery Powered Operation.
8-28 RMS-TO-DC CONVERTERS
+v,
T0
COMMON ---I+-----,
POSITIVESUPPLY--....
:tP---~.~ +V,
T
01"'?
-v,
Low-Cost, Low-Power
True rms-to-dc Converter
~ANALOG
WDEVICES
AD737
FEATURES
COMPUTES
True rms Value
Average Rectified Value
Absolute Value
AD737 FUNCTIONAL BLOCK DIAGRAM
PROVIDES
200mV Full-Scale Input Range
Direct Interfacing with 3 1/2 Digit
CMOS AID Converters
Power Down Feature which Reduces Supply Current
High Input Impedance: 1012 ohms
Low Input Bias Current: 25pA max
High Accuracy: ±0.2mV ±0.3% of Reading
RMS Conversion with Signal Crest Factors Up to 5
Wide Power Supply Range: +2.SV,
-3.2V to ± 16.5V
Low Power: 160....A max Supply Current
No External Trims Needed for Specified Accuracy
of power supply current, the AD737 is
AD736 - A General Purpose, Buffered Voltage
o'\Jp~,tor use in portable multimeters and other battery
Output Version is also Available
\ ~ ';~:"~~d app,lica~ns. This converter also provides a "power
":,,,', I~: '1',40wn" feat~w~ireduces the power supply standby current
Req.~"~Y'J60~A
(/,'/,
\~~ ~4 ~;,
'{
"n'~A..,f
PRODUCT DESCRIPTION
, ",:', :' ';:~ \!:
,. ')
•
••
'.
The AD737 is a low-power, precision, mon~}rue"'~-to;;7 allows ~~e chOlce ?f two sl~ll?pu~ term~als. a
converter. It is laser trimmed to provid~ a Ittaximfilw'error 0 '
pedance (10 n) FET mput whIch WIll dIrectly mterface
less than ±0.2mV ± 0.3% of reading';'it1l, ;iib>WaV~ i,Iwu1$,',/ ",
h i g ' ut attenuators and a low n:npedance (8kn~ input
Furthermore, it maintains high at~}~raCf"wliile measlil;mg jl'w,jde' w"
e mea~u.rement of 300mV mput levels while
range of input waveforms, includ~ varlabl~,d~ ,9Yct. ,pulses ~~per '"
om th~ mmlmum power su?ply v?ltage of + 2.8V,
and triac (phase) controlled sine waves. The'low Q)s~and s~, ~,,~'f$·2~ !he two mputs may be used either SIngly or
physical size of this converter make it suitabfe:for'upgradint,Piq;} ,,..,ditrerenttally.
performance of non-rms "precision rectifiers" 'in many appli~"t' The AD737 achieves a 1% of reading error bandwidth exceeding
tions. Compared to these circuits, the AD737 offers higher
10kHz for input amplitudes from 20mV rms to 200mV rms
accuracy at equal or lower cost.
while consuming only O.72mW.
The AD737 can compute the rms value of both ac and dc input
voltages. It can also be operated ac coupled by adding one external
capacitor. In this mode, the AD737 can resolve input signal
levels of 100.,.V rms or less, despite variations in temperature or
supply voltag~. High acccuracy is also maintai,n~ for input
waveforms WIth crest factors of 1 to 3. In addiuon, crest factors
as high as 5 can be measured (while introducing only 2.5%
additional error) at the 200mV full-scale input level.
The AD737 has no output buffer amplifier, thereby significantly
reducing dc offset errors occurring at the output. This allows
the device to be highly compatible with high input inlpedance
AID converters.
The AD737 is available in four performance grades. The AD737J
and AD737K grades are rated over the commercial temperature
range of 0 to + 70°C. The AD737A and AD737B grades are
rated over the industrial temperature range of - 40°C to + 85°C.
The AD737 is available in three low-cost, 8-pin packages: plastic
mini-DIP plastic SO and hermetic cerdip.
'
PRODUCT HIGHLIGHTS
1. The AD737 is capable of computing the average rectified
value, absolute value or true rms value of various input
signals.
2. Only one external component, an averaging capacitor, is
required for the AD737 to perform true rms measurement.
3. The low power consumption of O.72mW makes the AD737
suitable for many battery powered applications.
RMS-TO-DC CONVERTERS 8-29
•
SPECIFICATIONS
(@
+ 25"1:, ± 5V supplies, ac coupled willi 1kHz sine-wave input applied unless o1herwise noted.)
Model
AD737J/A
Conditions
Min
Tnun-Tmax
A&BGrades
J&KGrades
vs. SupplyVoliage
r{c 200mV rms Input
rf" 200m V rms Input
de Reversal Error, de Coupled
Nonlinearity 2, 0-200mV
Total Error, External Trim
AD737KIB
Max
VOUT~ -YAvg.(VIN ')
TRANSFER FUNCTION
CONVERSION ACCURACY
Total Error,Internal Trim l
All Grades
Typ
1kHz Sine Wave
ACCoupled
0-200mVrms
200mV-IVrms
0.2/0.3
-1.2
(il'200mVrms
CSt" 200m'! rms
0.007
Vs~ ",5Vto '" 16.5V
Vs= :±:5Vto ±3V
(i'c600mVde
(jl' 100mV ems
0-200mVrms
Typ
Min
VOUT~
+0.06
-0.18
1.3
+0.25
0.110.2
Units
0.2/0.3
2.0
:±:mV/±%ofReadmg
:±: % of Reading
0.3/0.5
:±:mV/±%ofReading
± % ofReadingrC
-YAVg.(VIN')
0.2/0.2
0.4/0.5
2.0
-1.2
0.5/0.7
0
0
Max
0.007
+0.1
-0.3
2.5
+0.35
0
0
0
+0.06
-0.18
1.3
+0.25
0.110.2
+0.1
-0.3
2.5
+0.35
%/V
%N
% of Reading
%ofReadmg
± mVI ± % of Reading
ERROR vs. CREST FACTOR'
Crest Factor 1 to 3
Crest Factor = 5
CAV,CF~ 100,..F
C AV , C F ~ 100,..F
% Additional Error
% Additional Error
0.7
2.5
0.7
2.5
INPUT CHARACTERISTICS
High Impedance Input (Pin 2)
Signal Range
Continuous rms Level
Continuous rms Level
Peak Transient Input
Peak Transient Input
Peak Transient Input
Input Resistance
Input Bias Current
Vs~
+2.8V, -3.2V
±5Vto '" 16.5V
+2.8V, -3.2V
Vs~ ±5V
Vs~ '" 16.5V
200
Vs~
±0.9
25
Low Impedance Input (Pin I)
Signal Range
Continuous rms Level
Continuous rms Level
Peak Transient Input
Peak Transient Input
Peak Transient Input
Input ReSIstance
Maximum Continuous Non M
Destructive Input
Input Offset Voltage 4
J&KGrades
A&BGrades
vs. Temperature
vs. Supply
vs. Supply
OUTPUT CHARACTERISTICS
Output Voltage Swing
No Load
No Load
No Load
Output Resistance
FREQUENCY RESPONSE
HIgh Impedance InpuI (Pm 2)
For 1% Addiuonal Error
VIN = ImVrms
VIN = lOmVrms
VIN = lOOmVrms
V IN = 200mV rms
:t 3dB BandWIdth
V IN = ImVrms
VIN = lOmV rms
VIN = IOOmV rms
VIN = 200mV rms
300
All Supply Voltages
aeCoupled
Vs~
8
50
80
±5Vto ±16.5V
",5Vto",3V
Vs ~ + 2.8V, - 3.2V
Vs~ ",5V
Vs ~ '" 16.5V
(",de
Oto -1.6
010 - 3.3
010 -4
6.4
-1.7
-3.4
-5
8
V
V
V
n
pA
9.6
mVrms
Vrms
V
V
V
kn
:tI2
± 12
Vp-p
±3
±3
30
150
±3
±3
30
150
mV
mV
,..V/oC
,..VN
,..VN
6.4
Vs~
mVrms
Vems
Vs~
9.6
± 1.7
'" 3.8
:tIl
8
8
50
80
010 -1.6
010-3.3
010 -4
6.4
-1.7
-3.4
-5
8
9.6
V
V
V
kn
Sme-WaveInput
37
33
37
33
kHz
kHz
kHz
kHz
5
55
170
190
55
170
190
kHz
kHz
kHz
kHz
SmcM Wave Input
8-30 RI'iAS-TO-DC CONVERTERS
Model
AD737J/A
Conditions
FREQUENCY RESPONSE
Low Impedance Input (Pin 1)
For 1% Additional Error
VIN = ImVrms
Min
AD737K1B
Typ
Max
Min
V IN
=
lOOmVrms
VIN
=
200mV fms
POWER SUPPLY
Operating Voltage Range
QUiescent Current
V IN = 200mV rms, No Load
Power Down Mode Current
Max
Sme-Wave Input
Units
90
99
6
90
90
kHz
kHz
kHz
kHz
5
55
350
460
5
55
350
460
kHz
kHz
kHz
kHz
V IN = lOmVrms
VIN = lOOmVrms
NrN = 200mVrms
~ 3dB BandwIdth
V IN = ImVrms
V IN = IOmV rms
Typ
Sme-Wave Input
+2.S, - 3.2
Zero Signal
Sme-Wave Input
Pm 3 uedto +V~
±5
120
170
25
± 16.5
160
210
40
+2.S,- 3.2
± 16.5
160
210
40
±5
120
170
25
V
,.A
,.A
,.A
TEMPERATURE RANGE
Operating, Rated Performance
Commercial (0 to + 70°C)
AD737]
AD737A
Industrial ( - 40°C to + S5°C)
PACKAGE OPTIONS'
S-Pm Plastic Mmi-DIP (N-S)
S-Pin Plastic SO (R-S)
S-Pm Cerdip (Q-S)
AD737K
AD737B
AD737KN
AD737KR
AD737BQ
•
'i•. ~,
NOTES
I Accuracy is specified with the AD737 connected as shown In Figure 1.
'" -;,~
,1" "
2Nonhnearity IS defined as the maximum deviation (m per~~'t-err<~)from·~;i!trillght hn~~J;m.llt~'
f
thereadmgsatOand200mVrms
, \,' .,,'
!;\!J!ffi;
',,>:,:_'/ . . :.
3Error vs. Crest Factor IS specified as addmonal ermif~ 20Q{n V, ~'s signal.
rdts.
4DC offset does not lImit ac resolution.
;':;,:
i,,"
'e1:'
sSeeSectlon 16forpackageouthnemformaij~m •.';
,"t II;jA
"i-r
A"JV
I"
','
'
Specifications are subject to change wlthoo.r ~e
_
':::: ','"~
"'
Specifications shown in boldface are tested on producti~'pmtS'~,~ elecrr
"',
Results from those tests are used to calculate outgomg qualltj]~vels/.!' !
an
ABSOLUTE MAXIMUM RATINGS]
Supply Voltage
Internal Power Dissipation
Input Voltage . . . . . . .
Output Short-Circuit Duration
Differential Input Voltage . _ .
Storage Temperature Range Q
Storage Temperature Range N, R .
Operating Temperature Range
AD737J/K
.............. .
AD737A/B . . . . . . . . . . . . . . .
Lead Temperature Range (Soldering 60sec)
± l6.5V
200mW
.. ±Vs
Indefinite
+Vs and -Vs
- 65°C to + 150°C
- 65°C to + 125°C
o to +70°C
- 40°C to + 85°C
+ 300°C
NOTE
I Stresses
above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
RMS-TO-DC CONVERTERS 8-31
Applications Circuits
v,.
::i~F
POSITIVE SUPPLV
POSITIVESUPPLV _ _....._~~
(OPTIONAL)
1
.
+Vs
COMMON
01.-,F
COMMON
NEGAl1VESUPPLV
to'"F Y-v.
--+--,
"';1I;-.......-
Figure 1. AD737 True rms Circuit
-*ReaL
•• R1
4
"Q1,Q2PARTOF
RCACA3046
ORSIMILARNPN
** R1 + ReAL IN OHMS = 10,ooon )('Od;;;B"liJNP"UT-;"'+lV~EV"E"L""N;oV;;;O"LT"'S:- TR~~~I:~OR
Figure 3. dB Output Connection
VIN
200mV
Figure 4. 3 112 Digit DVM Circuit
8-32 RMS-TO-DC CONVERTERS
........
-v.
Special Function Components
Contents
Page
Orientation . . . . . . . . . . . . . . . . . . . . .
9-3
AD345 - High Speed Pin Driver with Inhibit Mode
9-5
AD630 - Balanced ModulatorlDemodulator
9-9
AD639 - Universal Trigonometric Function Converter
9 - 17
AD890 - Precision Wide band Channel Processing Element .
AD891 - Rigid Disk Data Channel Qualifier . . . .
9 - 29
AD9500 - Digitally Programmable Delay Generator
9 - 41
. . . .
9 - 35
SPECIAL FUNCTION COMPONENTS 9-1
9-2 SPECIAL FUNCTION COMPONENTS
Orientation
Special Function Components
This section contains technical data on integrated-circuit chips
that could not be classified in any of the major sections of this
databook without losing their identities. For example, the AD639
trigonometric function generator is a close relative of analog
multiplier/dividers, in both function and circuitry; but if it were
listed in that section, its unique trigonometric capabilities would
be "buried".
cosecant and cotangent - as well as some lesser known variants,
such as the versine and exsecant, plus a corresponding set of
inverse functions. All inputs are differential, and either polarity
of input or output can be generated.
We describe briefly here the function and salient uses of these
devices. For further information, consult the individual data
sheets.
ANALOG FUNCTIONS
AD630 Balanced Modulator/Demodulator
The AD630 is a fast, flexible, switched dual-input op amp with
an on-chip comparator. Intended for wideband, low-level, and
wide-dynamic-range instrumentation applications and coherent
systems, it is capable of such analog signal-processing functions
as balanced modulator, balanced demodulator, absolute-value
amplifier, phase detector, square-wave multiplier and two-channel
precision multiplexer. It can be used as a lock-in amplifier,
synchronous detector, rectifier, dual-mode circuit, and much
more. Essentially a complete device with on-chip scaling resistors;
it can be used for these functions with little or no additional
circuitry.
Trigonometric functions play an important role in electronics.
Inherent to many communications, measurement and display
systems, they also find increasing application in control and
robotics. Most familiar are the sine and the cosine, which find
wide use as fundamental signal sources - both separately and in
orthogonal pairs. In display systems, these functions are basic to
graphical manipulations (axis rotation and polar-to-Cartesian
conversion), and they also appear in many antenna-related signal
transformations. The tangent is important in scanning systems,
and the arctangent is used in Cartesian-to-polar conversion and
in determining phase angle from the real and imaginary components of a complex signal.
With its large repertoire of functions, the AD639 makes it possible
to include trigonometric transformations in the analog portion of
a system with little added cost or board space, and with high
accuracy, without the overhead in software, memory or time,
which would accompany such computations in an associated
digital system. It also makes it easy to generate low-distortion
sine-wave signals, with voltage control of amplitude and frequency,
up to IOVand IMHz, respectively.
DIGITAL FUNCTIONS
As a lock-in amplifier, it can recover a 0.1-Hz sine wave, transmitted
as a modulation on a 400-Hz carrier, from a band-limited, clipped
white-noise signal approximately 100,000 times larger - a dynamic
range greater than 100dB.
It consists of a frequency-compensated op-amp-output stage,
with two identical switched differential front ends (A and B), a
differential comparator that controls the switching and a set of
jumper-programmable matched precision resistors - trimmed to
produce closed-loop gain accuracies to ± 0.015% and gain match
(between channels) to ±0.03%. When the net input to the
comparator is positive, front-end A will be selected; when the
comparator input is negative, front-end B is selected. A status
output indicates the state of the comparator.
AD639 Universal Trigonometric Function Generator
The AD639 is an analog "trigonometric microsystem" on a
single silicon chip, packaged in a 16-pin DIP. From a differential
input voltage, representing an angle (20mV(0), it can be pin
programmed to generate a voltage output, accurately determined
by any of the standard functions - sine, cosine, tangent, secant,
AD345 Pin Driver for Automatic Test Equipment
The AD345 is a complete high-speed pin driver designed for
use in digital functional test equipment and general purpose
instrumentation. It accepts digital, analog and timing information
from system sources and translates them directly to digital output
levels to be applied to the input of a device to be tested (DUT).
By teaming up the economy of surface-mount technology and
the accuracy of thick-fIlm laser trimming, the AD345 attains
superb electrical performance while preserving optimum packaging
densities in a convenient lO-pin SIP package.
Its output is switched by digital control inputs, and its amplitude
is derived from analog sources; its output high level can be set
by an analog voltage at any value from - 2V to + 8V, and its
low level can be set from - 3V to + 6V; this flexibility makes it
compatible with ECL, TTL and CMOS logic levels and timing.
It can drive level changes at up to 100MHz, with slewing rates
better than I VIns; its dynamic output impedance is laser trimmed
for waveform integrity and guaranteed performance with 50-ohm
transmission lines. Output impedance is 50 ohms, matching it
SPECIAL FUNCTION COMPONENTS ~3
by attenuation and noise - and must be amplified, qualified and
reconstituted. Separately, the AD890 is an excellent AGC amplifier
for radio-frequency signals.
AD9500 Digitally Programmable Delay Generator
The AD9500 delays events by an interval selected by an 8-bit
digital code, with settable time resolution as small as 10
picoseconds. The delay is initiated at the time a Trigger input
goes high: an integrator generates a downgoing ramp, and when
it crosses a preset level (established by an '8-bit DAC), a comparator
output changes state to produce the delayed output, Q.
-v,
to coaxial cable used for interconnecting the pin driver and the
device's input terminal, in order to minimize error-causing
reflections.
Who should use the AD345? Anyone who manufactures or
designs equipment for automatic test of semiconductor devices
or boards, or for instrumentation and characterization. It can
also function as a high-performance, low-cost general purpose
digital driver.
AD890 and AD891 Hard-Disk Bit-Recovery ICs
The AD890 Precision Wideband Channel-Processing Element
and the AD891 Rigid-Disk Data-Channel Qualifier are a pair of
monolithic integrated circuits that together are the key to a
complete signal-processing subsystem capable of error-free high
performance in demanding disk-drive applications. They take
data directly from the disk-head preamplifier, condition and
qualify it and produce recovered precisely timed data bits at
rates in excess of 50 megabits per second (guaranteed). Such
rates are essential for making efficient use of high-capacity,
high-performance disk drives. This chip pair replaces slower,
lower-performing discrete-circuit "kludges," and no external
trims are needed.
As the diagram below shows, the AD890 amplifies the signal to
a normalized level, using stable variable-gain amplification with
automatic gain control (AGC); and the AD891 establishes whether
a pulse exists, using differentiation to fmd peaks, then produces
data-output pulses of precise width. Since the actual timing
requirements - of both the filter time constants and the differentiator characteristics - are a function of the user's system, the
filter functions (using only passive elements) remain off-chip
under full control of the user. In addition to the functions shown,
the AGe can be turned off digitally when necessary; and input
clamping can be switched in during write so as to avoid input
overloads.
Although these circuits were developed for use in disk-drive
applications, it should be apparent that their applicability may
be considered wherever high-speed 'pulses have been degraded
The delay is equal to the programmed delay - which depends
on the integrator's selectable RC time constant and the precision
threshold set by the DAC - plus a propagation delay of SAns
minimum. A pulse of appropriate width applied at the Reset
input resets the integrator and the Q output to prepare t,he
device for the next Trigger. The range of full-scale programmed
delays is from 2.5ns to more than I ms, depending on the choice
of Rand C. When RC = 2.5ns, the LSB (or one increment of
delay) is 2,500 ps/256 = 10 ps, which is also the typical jitter
level.
INTERNAL
LINEAR
RAMP
TRIGGER
INPUT
RESET
INPUT
tn(MAX) _ PROGRAMDELAY(FULlSCALE)
t.n
- MINIMUM PROPAGATION DELAY
to
- PROGRAM VELA Y
tLRS
tRD
- LlNEARRAMPSETTLINGTIME
- RESETPROPAGATlONDELAY
AD9500 Internal Timing Diagram
The differential Trigger and Reset inputs are designed primarily
for single-ended or differential ECL, but they function with
analog and TTL input levels. The Q, ~ output is a complementary
ECL stage, with a parallel 'tR output circuit to facilitate reset
timing implementations.
An important application is in equalizing skew in multichannel
systems; with one line used as the standard, the programmed
delays of the other AD9500s are adjusted to eliminate the timing
skews. Other applications include multiple-phase clock generators,
measuring unknown delays and time response of high-speed ac
waveforms, and digitally programmable oscillators.
RECOVERED
DATA BITS
IUUlJL
9-4 SPECIAL FUNCTION COMPONENTS
11IIIIIIII ANALOG
WDEVICES
FEATURES
100MHz Driver Operation
Driver Inhibit (Tristate) Function
Guaranteed Industry Specifications
SOO Output Impedance
1V/ns Slew Rate
Variable Output Voltages for ECl, TTL and CMOS
High-Speed Differential Inputs for Maximum Aexibility
Small SIP Package
Low Cost
APPUCATIONS
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
Instrumentation & Characterization Equipment
General Purpose Driver
High-Speed Pin Driver
with Inhibit Mode
AD345 I
AD345 FUNCTIONAL BLOCK DIAGRAM
-v,
PRODUCT DESCRIPTION
The AD34S is a complete high-speed pin driver designed for
use in digital test systems. By combining surface mount technology
and thick-film laser trimmed technology, this product attains
superb electrical performance while preserving optimum packaging
densities in a convenient 100pin SIP package.
the drivers placed in close proximity to the device under test
guaranteeing optimum signal integrity. A metal tab is mounted
on the back side allowing for heatsinking or mechanical support.
The AD34S is available for operation over the 0 to + 70"C
range.
Featuring unity gain programmable output levels of - 3 to + 8
volts with output amplitude capability of 700mV to 11 V, the
AD34S is designed to stimulate ECL, TIL and CMOS logic
families. The lOOMHz (Sns pulse width) data rate capacity, IVI
ns controlled slew rate, and son output impedance allows for
real-time stimulation of these digital logic families. To test 110
devices the pin driver can be switched into a high impedance
state (inhibit or tristate) by using the inhibit mode. The pin
driver leakage in tristate is typically SOnA and output charge
transfer going into tristate is guaranteed at 200pC maximum.
PRODUCT IDGHLIGHTS
1. The AD34S is a complete lOOMHz pin driver designed to
meet the requirements of ATE manufacturers.
2. Output high voltage level is adjustable from - 2V to + 8V
and output low levels from - 3 to + 6V allowing compatibility
with ECL, TIL, CMOS logic levels.
3. Certified large signal slew rates of better than IVIns with
dynamic output impedance laser trimmed for waveform
integrity and guaranteed performance with 500 transmission
lines.
4. TRISTATE (inhibit) capability for testing 110 devices.
S. INHIBIT leakage current of SOnA typical virtually eliminates
the requirement for a disconnect relay in a semiconductor
test system.
6. Repeatability from driver-to-driver is guaranteed to meet
published specifications through pretesting and active laser
trimming.
7. The 100pin SIP hybrid package with mounting tab provides
high functional mechanical densities with maximum
versatility.
The AD34S transition from hiIlow or to tristate is effected through
the data and inhibit inputs. The input circuitry is implemented
utilizing high-speed differential inputs with a common-mode
range of 8 volts. This allows for direct interface to the precision
of differential ECL timing or the simplicity of stimulating the
pin driver from a single ended TIL or CMOS logic source. The
analog inputs V high or V low are equally easy to interface.
Requiring typically SOOIlA of bias current, the AD34S can be
directly coupled to the output of a DAC either singularly or in
parallel with several other pin drivers.
The AD34S utilizes surface mount technology creating a small
single in-line package which can be mounted upright or laying
down (leads bent 90") depending on the specific application.
The SIP packaging enables the user to create a tight radial test
head design or a custom high-speed dedicated probe card with
SPECIAL FUNCTION COMPONENTS 9-5
9
SPEC IFICAli 0NS (All specs
Min
Parameter
D1FFERENTIALINfUT
CHARACTERISTICS
DtoD,INHIOINH
Voltage Range
Pulse Amplitude
Bias Current
@ 25"1: in free air, output unloaded,
AD345KY
Tn>
Mu
Units
V LOW
Bias Current
-Vs +6V
0.37
EeL
500
+Vs -6V Volts
3.5
Voltsp·p
750
...A
-2
-3
+8.3
+6.2
750
Gam Error
PIN CONFIGURATION
Comments
0
See Note 1
See Note 2
500
OUTPUT CHARACTERISTICS
LOgiC HI~h Range
Logic Low Range
Amphtude
ImtialOffset
BY, unless oIhelWise specified)
Component Side View
REFERENCE INPUTS
VH1GH
+V= + 12V, - V= -
Volts
Volts
AD345
",A
See Notes 2 & 3
-2
-3
0.7
-30
-1.2
+8
+6
Volts
11
Volts
Volts
+30
+i.2
mV
%ofSetLevel
1.0
mVrC
60
100
mA
mA
pF
1 2
3 4
5 6
7 8 9 10
See Note 3
NormalIZed to
FtgUres I &2
Output Voltage Temp. Coeff.
0.5
Current Drive
Static
DynamiC
Output Capacitance
9
Output Charge Gomg
Into InhibIt Mode
LeakageCurrent In
InhIbit Mode
ProtectIon
Output «.- GND
50
+V
INDEFINITELY
1 Mmutew/o Damage
Output(il -V
1 MlDule w/o Damage
Output~'
DYNAMIC PERFORMANCE
Dnver Delay Time
Driver Delay Matching
Edge to Edge
Dnver to Driver
200
pC
200
nA
PIN
1
2
3
4
See Notes 4 & 5
1.5
2.0
-0.5
-1.0
2.5
ns
+0.5
+1.0
ns
ns
2.5
4.0
ns
ns
V/ns
MHz
Slew Rate
IVSwlDg20%-80"k
4VSwmglO%-90%
LargeStgnai
Toggle Rate
1.0
1.5
3.5
1.25
100
ECL Output Level
Overshoot and Preshoot
In DrIver Mode
IVSwlDg
>2VSwing
In InhIbit Mode
Settling CharacterIstic
200
120
350
5
mV
mV
mV
% of Steady State 50ns
after Starting Time of
Voltage Slew. Steady State IS
Greater Than lmsafter
StartmgTlmeofVoltageSlew.
InhIbit Delay Time
Inhibit to AC[lve
Active to Inhibit
Output Impedance
14
5.5
47.5
15
8
50
16
105
52.5
n
ns
ns
25
+15
-10
Volts
Volts
Volts
+70
+60
mA
mV
mV
See Notes 6 & 7
See Notes 6 & 7
See Note 8
POWER SUPPLIES
-Vsto+VsRange
Positive Supply Range
Negallve Supply Range
Current
+PSRRVoH~8V
-PSRRVOI,~
-3V
PACKAGE OPTIONS'
SIP (Y-IO)
20
+11
-5
+12
-8
100
-70
-60
+V= ±2.S0/0
-V~±2.5%
AD345KY
NOTES
'The maximum allowable voltage from D [0 0 and from INH to INH IS 3 SV
lThc output voltage range IS speCIfied for - 3V to + 8V for [}'Plcal power supply values of - 8V and + 12V but can be
offset for different values of VOUT such as OV [0 + IIV as long as the reqUIred headroom of 4V between VH and
+ Vs are mamtamed and the negauve he3droom of 5V between VI and - VS IS preserved
JDynanucally trimmed at SMHz, SO% duty cycle
4DeIa)' times are measured from the crosSIng of dlfferennal EeL outputs at mputs of the device to a 2SOmV transltlon
at output WIth V H and VL set to ± IV respectively
5DeJay tllnes, slew rates, overshoot and undershoot performance spectfied with a 10k, 2pF probe Oscilloscope bandwtdth
to exceed 300MHz
6J:nhlbu mode delay tllnes are measured from the cro8smg of differentIal EeL outputs at INH IDpUts to threshold crossmg at the
pUKlnver output Vom IS connected to a lOOfiJoad temunated at +2V dc The VH
and VI. are set to a nonnalu:ed +3 5Vand +0 5V respectively High delay times are measured
to a + 1 5V threshold Frequency IS set to 10MHz With a 50% duty cycle
'The mhwlt delay bme Specdicabon allows for devlCC-to-devJce vanabons. The stab,IIty and Jitter of a gIven deVice
IS better than Ins and lOOps respecbveJy
BDynanucaUy trunmed at the factory for son Other unpedance values can be obtalDed on specull request
9See Se('bon 16 for package outhne mformabon
SpecificatIOns subJect to change WIthout Donce
~6
SPECIAL FUNCTION COMPONENTS
SYMBOL
FUNCTION
VL
VOLTAGE LOGIC LOW
VH
VOLTAGELOGICHIGH
D
DRIVER INPUT
0
DRIVER INPUT
5
6
+Vs
POSITIVE SUPPLY
-Vs
NEGATIVE SUPPLY
7
8
9
10
V OUT
DRIVER OUTPUT
GND
CIRCUIT GROUND
INH
INHIBIT INPUT
INH
INHIBIT INPUT
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
. . . 0 to +70°C
Storage Tempemture Range.
- 65°C to + 125°C
Power Supply Voltage
+Vs to GND . . . . . . .
+15V
-Vs to GND . . . . . . .
-IOV
Difference from + Vs to - Vs
+25V
Input . . . . . . . . .
. . . . . .
-Vs to +V.
Your . . . . . . . . .
+Vs +0.6Vor -Vs -O.6V
Your to Short Circuit
to GND . . . .
IndefInitely
to +Vor -Vs . . .
.. 1 Minute
DETERMINING LOGIC SET LEVELS
Within a system it is possible to minimize gain error and increase
the output level accuracy of the AD345 by using the information
providea by Figures 1 and 2. Figure 1 is a table of desired
output high levels followed by the recommended input reference
levels. Figure 2 accomplishes the same for the output low levels.
Values of output levels not supplied by the tables can simply be
interpolated from the data supplied.
Another potential source of output level error is offset error.
The value, once determined for a specific device, should be
algebraically subtracted for the appropriate VmGH or VLOW set
value.
V OUTPUT HIGH
V H INPUT LEVEL
-2.00V
-1.00V
+1.00V
+2.00V
+3.00V
+4.00V
+5.00V
+6.00V
+7.00V
+8.00V
-2.016
-1.009
+1.007
+2.018
+3.028
+4.041
+5.054
+6.070
+7.098
+8.150
FUNCTIONAL DESCRIPTION
The AD345 is a complete high-speed pin driver designed for
use in general purpose instrumentation and digital functional
test equipment. The purpose of a pin driver is to accept digital,
analog and timing information from a system source and interface
those elements to the input of a digital device to be tested.
The circuit configuration for the AD345 has been summarized
in Figure 3. Simply stated a pin driver performs the function of
a precise, controlled, high-speed level translator with an output
which can be disabled. The AD345 accepts digital information
utilizing high-speed comparators on the D, D and INH, INH
from ECL differential outputs for precise timing at logic cross-over
and high-noise immunity. The wide input voltage range allows
for ECL operation between 0 to -5.2V, or +2V to -3.2V and
+ 5V to OV. Where timing is less critical TTL or CMOS logic
levels may be used to toggle the AD345. By biasing the D and
INH inputs to approximately + 1.3V for TTL and 1I2Vcc for
CMOS, the D and INH inputs can be directly stim~ated from
these single-ended output sources. The output of the pin driver
will follow the logic state of the D input providing the inhibit
input is low. When the inhibit level is asserted the output will
be disconnected and any activity on the input will not be transferred
to the output.
Analog information is input to the pin driver through the VH
and VL terminals as a reference voltage. These analog voltages
are then buffered using unity gain followers. The resulting gain
error has been characterized in Figures I and 2. System timing
requirements are achieved through a specified 2.0ns, ± 500ps
driver propagation delay, 1.25V/ns slew rate, defined preshoot
and overshoot, and a dynamically trimmed son output
impedance.
+Vs
Figure 1. Table of Normalized VH1GH Levels
V OUTPUT LOW
V L INPUT LEVEL
-3.00V
-2.00V
-1.00V
+1.00V
+2.00V
+3.00V
+4.00V
+5.00V
+6.00V
-3.012
-2.007
-1.008
+ 1.015
+2.023
+3.031
+4.040
+5.050
+6.060
-Vs
Figure 3. AD345 Block Diagram
Figure 2. Table of Normalized Vww Levels
SPECIAL FUNCTION COMPONENTS 9--7
•
LAYOUT CONSIDERATIONS
While it is generally considered good engineering practice to
capacitively decouple an active device from the power supplies,
it is absolutely essential for a high-power, high-speed device
such as the AD345. The engineer merely has to consider the
current pulse demanded from the power supply when a dynamic
current change of - 90mA to + 90mA is required in only a few
nanoseconds. Therefore, a O.Oljl.F high frequency decoupling
capacitor must be located within 0.25 inches of the + Vs and
- V s terminals to a low impedance ground. A 10jl.F capacitor
should also be situated between the power supplies and ground,
however, the proximity to the device is less critical assuming
low impedance power supply distribution techniques are employed. Circuit performance will be similarly enhanced and
noise minimized by locating a O.Oljl.F capacitor as close as possible
to VH, V L and connected to ground. Bypass considerations have
been summarized in Figure 4.
An. equally important consideration is the use of microwave
stripline techniques on the output of the AD345. Failure to
preserve the son output impedance of the pin driver will result
in unwanted reflections, ringing and general corruption of the
output waveshape. Care should therefore be exercised when
selecting etch widths and routing, wire and cable to the device
to be tested, and in choosing relays if they are required.
--+-----.-:---_a +12V
Figure 5. High-Speed Digital Test System Block Diagram
[OVEftSHOOT _
'" STEADV
STEADY
STA,TE
STATE
'
:
,-,,__-+I~~
,1.
,,
,
,
:----- SLEW RATE =
~
,, ''
, '
PAESHOOT I
I,
I'
RISETIME~
}--+-+---~---. VH
}--t-i---~---.COMMON
Figure 6. Definition of Terms
Figure 7. ± 1 Volt Waveform
with Inhibit (Output
Terminated into 5012)
}--+-.....---+:+,.---.. V,
11o"F
.,.. O.Ol"F
~__~~----__
....._ _~. -8V
Figure 4. BasicCircuitDecoupling
The quality of the ECL differential driving source to the data
inputs of the AD345 is another important consideration. The
ECL driving outputs should be located close to the D and D
inputs of the pin driver. Due to the low propagation delay of
the AD345 excessive overshoot at the D input can be coupled to
the pin driver output at low pulse amplitudes. In this case, an
isolation resistor of approximately 620 can be inserted between
the ECL output and the D input to the pin driver without, any
degradation in performance.
FigureS. LargeSignal50ns
Pulse
Figure 9. 5Volt50nsPulse
APPLICATIONS
The AD345 has been optimi2ed to function as a pin driver in an
ATE test system. Shown in Figure 5 is a block diagram illustrating
the electronics behind a single pin of a high-speed digital functional
test system with the ability to test I/O pins on 10000c devices.
The AD345 pin driver, AD96687 high-speed dual comparator,
and the AD394 quad 12-bit voltage DAC would comprise the
pin electronics portion of the test system. Such a system could
operate at lOOMHz in the data mode or 50MHz in the 1/0
mode, yet fit into a neat trim package.
,....
GENERATOR
'OOM",
Figure 10. AD345 Test Setup
~
SPECIAL FUNCTION COMPONENTS
ANALOG
&.III DEVICES
11IIIIIIII
FEATURES
Recovers Signal from + 100dB Noise
2MHz Channel Bandwidth
45V/....s Slew Rate
-120dB Crosstalk @ 1kHz
Pin Programmable Closed Loop Gains of :!: 1 and
0.05% Closed Loop Gain Accuracy and Match
100....V Channel Offset Voltage (AD630BD)
350kHz Full Power Bandwidth
Chips Available
Balanced Modulator/Demodulator
AD630 I
AD630 FUNCTIONAL BLOCK DIAGRAM
:!: 2
PRODUCT DESCRIPTION
The AD630 is a high precision balanced modulator which combines
a flexible commutating architecture with the accuracy and temperature stability afforded by laser wafer trimmed thin film
resistors. Its signal processing applications include balanced
modulation and demodulation, synchronous detection, phase
detection, quadrature detection, phase sensitive detection, lock-in
amplification and square wave multiplication. A network of onboard applications resistors provides precision closed loop gains
of :!: I and ± 2 with 0.05% accuracy (AD630B). These resistors
may also be used to accurately configure multiplexer gains of
+ I, +2, +3 or +4. Alternatively, external feedback may be
employed allowing the designer to implement his own high gain
or complex switched feedback topologies.
The AD630 may be thought of as a precision op amp with two
independent differential input stages and a precision comparator
which is used to select the active front end. The rapid response
time of this comparator coupled with the high slew rate and fast
settling of the linear amplifiers minimize switching distortion.
In addition, the AD630 has extremely low crosstalk between
channels of -100dB @ 10kHz.
The AD630 is intended for use in precision signal processing
and instrumentation applications requiring wide dynamic range.
When used as a synchronous demodulator in a lock-in amplifier
configuration, it can recover a small signal from 100dB of interfering noise (see lock-in amplifier application). Although optimized
for operation up to 1kHz, the circuit is useful at frequencies up
to several hundred kilohertz.
PRODUCT HIGHLIGHTS
1. The configuration of the AD630 makes it ideal for sigual
processing applications such as: balanced modulation and
demodulation, lock-in amplification, phase detection, and
square wave multiplication. .
2. The application flexibility of the AD630 makes it the best
choice for many applications requiring precisely fixed gain,
switched gain, multiplexing, integrating-switching functions,
and high-speed precision amplification.
3. The 100dB dynamic range of the AD630 exceeds that of any
hybrid or IC balanced modulatorldemodulator and is comparable to that of costly sigual processing instruments.
4. The op-amp format of the AD630 ensures easy implementation
of high gain or complex switched feedback functions. The
application resistors facilitate the implementation of most
common applications with no additional parts.
S. The AD630 can be used as a two channel multiplexer with
gains of + I, +2, +3 or +4. The channel separation of
100dB @ 10kHz approaches the limit which is achievable
with an empty Ie package.
6. The AD630 has pin-strappable frequency compensation (no
external capacitor required) for stable operation at unity gain
without sacrificing dynamic performance at higher gains.
7. Laser trimming of comparator and amplifying channel offsets
eliminates the need for external nulling in most cases.
Other features of the AD630 include pin programmable frequency
compensation, optional input bias current compensation resistors,
common mode and differential offset voltage adjustment, and a
channel status output which indicates which of the two differential
inputs is active.
SPECIAL FUNCTION COMPONENTS 9-9
•
'
SPECIFICATIONS
(@ +25"1: and ±Vs
Model
MiD
GAIN
Open Loop Gain
± I, ± 2 Closed Loop Gain Error
Closed Loop Gain Match
Closed Loop Gain Drift
CHANNEL INPUTS
VIN Operational Limit'
Input Offset Voltage
Input Offset Voltage
90
110
0.1
0.1
2
.
120
300
10
SO
(-Vs +3V)to(+Vs -1.5V)
±1.s
1.6
100
200
90
50
100
200
(-Vs + 33V)
90
90
±s
±16.5
5
4
1000
300
50
110
110
±S
4
90
90
.,.V
nA
nA
dB
Volts
mV
±2.s
mV
nA
ns
rnA
Volts
2
45
3
MHz
VI....
110
110
dB
dB
Volts
rnA
±s
±16.5
5
Volts
.,.V
300
(-Vs +33V)
2
45
3
lOS
110
ppm"C
(-Vs +3V)to(+Vs -1.3V)
±1.s
±2.0
300
~.6
2
45
3
dB
1.6
(-Vs+33V)
85
100
10
100
300
Units
%
%
(- Vs HV)to( + Vs -IV)
500
(-Vs +3V)to(+Vs -1.5V)
±1.s
±2.0
300
Max
110
0.1
0.1
2
160
100
10
100
100
DYNAMIC PERFORMANCE
Unity Gain Bandwidth
Slew Rate'
Settling Time to 0.1 % (20V step)
AD630S
Typ
90
(- Vs +4V)to( + Vs -IV)
100
800
100
200
Min
2
100
TuuntoTma!(2
OPERATING CHARACTERISTICS
Common-Mode Rejection
Power Supply Rejection
Supply Voltage Range
Supply Current
AD630KIB
Typ
Max
0.05
0.05
500
Tl1llI1toTmax
Input Bias Current
RespanseTime( -5mVto + 5mV step)
Cl2annel Status
ISINK@VOL = -Vs + 0.4V'
Pull-Up Voltage
MiD
100
(- Vs + 4V) to ( + Vs -IV)
Input Bias Current
Input Offset Current
Channel Separation@ 10kHz
COMPARATOR
VIN Operational Limit'
Switching Window
Switching Window
= ±15V unless othelWise specified)
AD630J/A
Typ
Max
4
.,.S
± 16.5
5
OUTPUTVOLTAGE,@RL=2kll
TnuntoTmax
±10
Output Shon Circuit Current
TEMPERATURE RANGES
Rated Performance- N Package
DPackage
±10
25
±IO
25
0
-25
+70
+85
0
-25
Volts
rnA
25
N/A
+70
+85
-55
+125
NOTES
lIf one terminal of each differential channel or comparator input is kept within these limits the other terminal may be taken to the positive supply.
2 This parameter guaranteed but not tested.
'ISINK@VoL=(-Vs+ l)voltistypically4mA.
4 Pin 12 Open. Slew rate with Pins 12 & 13 shorted is typically 35V/.,.s.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calcuJste outgoing quality levels. All
min and max specifications are guaranteed, although only those shown in
holdface are tested on all production units.
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . • . . . . • . .
Intema1 Power Dissipation • • . • . .
Output Short Circuit to Ground
Storage Temperature, Ceramic Package
Storage Temperature, Plastic Package.
Lead Temperature, 10 sec. Soldering
Max Junction Temperature . . . . . .
. . :t 18V
. 600mW
Indefinite
-65°C to + 150°C
- 55°C to + 125°C
+300"C
. . . .. + 150"C
Model
Package
Options·
AD630JN
AD630KN
AD630AD
AD630BD
AD630S0
Plastic (N-20)
Plastic (N-20)
Ceramic (D-20)
Ceramic (0-20)
Ceramic (0-20)
*See Section 16 for package outline information.
9-10 SPECIAL FUNCTION COMPONENTS
"C
"C
Typical Peliormance Characteristics
1B
15
.~I)
5k
15
~
2'
>
0
>
~
+
"
~0 10
", 10
~
~
Vo
>
>
Sk
~
"0
5
0
V-
'/11
1I
f "'1kHz
C l =100pF
1I
IIII
~
10
10
RESISTIVE LOAD - U
Figure 7. Output Voltage vs.
Frequency
Figure 3. Output Voltage Swing
vs. Supply Voltage
Figure 2. Output Voltage vs.
Resistive Load
p=+l+J:+=1+l1:TmrTlTrnrrnrT"rTIl
60
120
100
H-ti1t-H+*+ffikl-++H-I-+H+-f-,H1l
40
UNhoM~ENS~T~
i'.,
20
;
;gl~
-20
~
~~
-40
-60
~Ij
~~
5
4
FREQUENCY _ Hz
~
-3
./ ~
j
II
~
~~
-
120
-
\00
0
COMPENSATED
~
\
,
,
I
U~COjPlNSATJ- -
~
"
\
~~
,;:. ,.......'"
,',<:-
/
"",
COMPENSATED -'"
I
0
~
-2
0
-1
10
100
dVo
'
Figure 5. vs. Input Voltage
dt
lk
10k
100k
,
\
\
~\
\
10M
1M
.
±10V 20kHz
(V,)
1mV/div
(A)
(V o)
,
Figure 6. Gain and Phase vs.
Frequency
50mV/div
IV,)
20mVldiv
~
./i~ 1',
I~
~
~
~
FREQUENCY _ HI.
INPUT VOLTAGE - V
Figure 4. Common Mode
Rejection vs. Frequency
15
SUPPLY VOLTAGE - :tV
1mVld,v
(8)
20mV/div
10Vldlv
(V,)
IV.)
100mV/dlv
(vol
TOP TRACE V,
MIDDLE TRACE SETTLING
I
ERROR IS}
ERROR (A)
BOTTOM TRACE V
BOTTOM TRACE Vo
Q
'Ok
10k
Vo
V.o---,......---i
I
I
I
.~
Figure 7. Channel-to-Channel SwitchSettling Characteristic
> ....>--<~---oVo
BOTTOM
TRACE
TOP
TRACE
1k
V, o--..~"""--..>-I
TOP
TRACE
> .........,......--l- V,I. Vnder such conditions the AD639
generates a HIGH output at pin 11 and simultaneously clamps
the analog output to zero (in fact, to the voltage
Grounding
GT disables the error trap.
Zv.
The GT pin may also be used as an input to gate the function
output. This is achieved by raising pin II to a voltage above
+ I.SV. Response time is typically sOOns for a logic drive of 0
to +2V, and the ON/OFF ratio is greater than 83dB when used
as a continuous-wave sine converter with a single-sided ± 1. 8V
triwave drive at frequencies up to 10kHz, or 63dB at 100kHz;
the feedthrough is entirely capacitive, and is equivalent to SpF,
between XI or X2 and the op-amp summing node. Feedthrough
can be minimized by using a balanced drive to Xl and X2.
SPECIAL FUNCTION COMPONENTS 9-21
9
Operation In Normal Modes
In normal modes, the Z-input establishes a feedback path around
the output op-amp, by connecting ZI to the output, W, and Z2
to the ground associated with the load circuit. For the highest
accuracy Z I can be used to sense the output at the load terminals.
Simi1arly, zero-valued angle inputs and the angle common (pin
5) should be connected to the ground associated with the source
circuitry.
SINE MODE
The AD639 can generate either (1) a low-distortion continuous
sinewave from a repetitive triwave input or (2) a high-accuracy
sine function for use in computational applications. In most
cases, the choice of preset or externally-controlled amplitude
will make little difference to distortion or accuracy, and both
methods are used in this section. In all of the normal modes, the
Z2 input can be used either to sum a further signal to the output
(or introduce an optional output offset trim). The denominator
is set to unity by making y = 90", using the + l.8V output.
Figure 2 shows typical connections. The 10V preset is selected,
using Vr as a control input to UP, and the ideal output is
(lOV)sin(x). In practice, five basic types of error arise:
Figure 3. Output Function for Peak X-Input of ± 18V, with
U= 15~ RL =600n (± Vs= 18V)
01%
/ '-.
~~
-.......::: ~
1. X-angk scaling error: The amount by which the angle generated
for each volt of X-input differs from 50°. In triwave-ta-sinewave
(CW) applications this introduces odd-order harmonic distortion, and is indistinguishable from an incorrect triwave
amplitude.
3. Ampliltuk scaling error: The amount by which the peak-ta-peak
amplitude of the sinewave differs from the ideal value, U/sin(y).
This error is usually critical only in computational applications.
Errors associated with the Y-network also affect the amplitude
in the sine mode.
4. Output offset error: The amount by which the mean wllUl of
the sinewave differs from zero (strictly, the voltage on Z2).
This error is only important in computational applications.
Note that the output may also be non-zero due to angular
offset on the X-input. For example, the typical specified Xangle offset of 0.1 ° introduces an output error of 17.45mV
when U/sin(y) = 10V, more than three times the specified
mean offset component of 5mV.
5. Law-conformance error: The residual deviation between the
output function and the ideal function when all of the above
errors have been removed by trimming during manufacture
or further external trimming, limiting the ultimate accuracy
of the function.
Figure 3 shows the function when driven well beyond the specified
angular range, using a differential X-input of ± ISV peluc. This
also shows the AD639's ability to drive ± ISV into a 6000 load,
with supplies of ± ISV. Using an accurate data-acquisition system
the output can be compared to a computer-generated sine function.
When the first four types of errors are trimmed out, the peak
error over the full input range is typically less than 0.5%. Over
the central - 90° to + 90", the peak law-conformance error is
typically only 0.02%. Figure 4 shows the law conformance for
four typical samples of AD639. The differential signal interfaces
simplify the inclusion of optional offset correction to any of the variables.
9-22 SPECIAL FUNCTION COMPONENTS
-.:::::::: -v'
' - i-===""
2. X-angk offset error: The actual angle generated when
X=(XI-XV=O. In CW applications this introduces evenorder harmonic distortion, as a non-zero mean in the triwave
would.
~
./?
-01%
-
...
..,.....
-.......
+ ...
INPUT ANGLE
Figure 4. Residual Error Over Central 180 0 Using External
Trimming
HARMONIC DISTORTION
The AD639 can genemte continuous sinewaves of very low
distortion using a linear, highly-symmetric triangle-wave of
± I.SV amplitude. Imperfections in the triwave will cause the
following errors:
I. Incorrect amplitude: This causes odd-order distortion. Each
1% error (either too large or too small) genemtes 0.25% of
HD3, 0.OS33% of HDS and a total harmonic distortion (THD)
of 0.27% (- SI.42dBs).
2. Baseline offset: This causes even-order distortion. Each millivolt
of offset in a I.SV triwave genemtes 0.037% of HD2, 0.0074%
of HD4 and a THD of 0.03S%, as well as a DC offset of
0.055% of the output amplitude.
3. Time-asymmetry: The run-up time, t10 and run-down time, t2,
of the triwave may be unequal. This causes both odd- and
even-order harmonics. Let the asymmetry in percent be
p = 1000ti - t2)/(tl + t2). The even-order terms are proportional
to p; the odd-order terms increase as p2. A 1% time-asymmetry
genemtes 0.57% of HD2, 0.00625% of HD3, 0.043% of
HD4 and 0.00167% of HD5, and a THD of -44dBs. There
is
DC term.
no
4. Amplitude-nonlinearity: This can take on many forms, such as
an exponential nonlinearity in the triwave, amplitude compression, and so on. Distortion can be calculated for various
special cases. Fortunately, it is fairly easy to avoid these
types of imperfections in the triwave genemtor using appropriate design methods.
Norinal Modes
When triwave errors are minimized, harmonic distortion can be
as low as 0.01%. Figure 5 shows the output spearum at 10kHz,
with an output amplitude of 20V pk-pk and a load resistance of
10kfl. An HP3325A synthesizer/function generator was used to
produce the triwave. Distortion rises only slightly when using
the minimum spec:ified load of 2kfi; in fact, the AD639 can
drive loads down to 6000. At ±V.= ± 18V, sine amplitudes of
± 15V (10.6V rms, or 225mW of load power) can be generated,
with typic:ally 0.03% HD2 and HD3.
+15V
AMPLITUDE
VOLTAGE-U
AD639
IOto +10VI
OPTIONAL
11z'1---.....- - SUMMING
INPUT
'OF
~CERAMIC
Figure 6. Connections for the Cosine Mode with External
Amplitude Control
X-ANGLE
VOLTAGE
150"/VI
+15V
-.-----l1il
AD639
OPTIONAL
11zlr----_-- INPUT
SUMMING
Figure 5. Spectrum of 10V Sine Output at 10kHz;
HD2= -88dBs, HD3= -85.5dBs
COSINE MODE
The cosine function is generated by offsetting the sine by 90"
using Vr • The X-input is connected to X2 and VR to Xl; then
_ sin (90" - x) _
W - U sin (90"-0) - U cos (x)
9
'OF
CERAMIC
Figure 7. Connections for Tangent Mode with Amplitude
Preset to 1V
Connections for the cosine are shown in Figure 6; the amplitude
in this case is determined externally, by way of illustration. The
angular range now extends from _400° to +600", with highest
accuracy between 0" and + 180°.
TANGENT AND COTANGENT MODES
The tangent function is provided by the connections shown in
Figure 7. The angle voltage, corresponding to 8, is applied both
to the numerator, set to the sine mode, and the denominator,
set to the cosine of the same angle:
W=U ~ (8-0) =U sin (8) =U tan (8)
SID (90" - 8)
cos (8)
Most applications require accurate operation for angles up to
nearly ±90" and accordingly U is preset to IV (rather than
10V). Under these conditions, W= IV when 8=45° and 1l.43V
when 8=85°. Using 15V supplies, the output op-amp will be
unable to generate the tangent much beyond this point: at only
86° it would theoretically need to reach 14.3V. For an input
exceeding 90° in either direction the denominator becomes negative, and the error trap is enabled. Figure 8 shows the function
for inputs up to ± 2.5V (± 125°).
scaling and offset errors of this network are absorbed during
trimming of the output in the sine mode.
The errors associsted with the sine mode, (see above) apply to
the tangent mode also, but the total error in the tangent, cosecant,
secant and cotangent modes (when the Y-input is also varied)
are higher, since the Y network is not trimmed and the angular
The cotangent is generated by interchanging numerator and
denominator. The principal range is now from 0 to + 180", and
the output (lV)cot (8) ranges from + 1l.43Vat 8=5°, through
zero at 8=90", to -1l.43V at 8= 175°.
Figure 8. The Tangent Output for Angle Inputs Up to
;t 125 0 (Error Trap Activated Above 85°)
SPECIAL FUNCTION COMPONENTS 9-23
•
SECANT AND COSECANT MODES
In secant and cosecant modes, the numerator is fIxed to unity
by connecting XI to VR and X2 to analog common. For the
secant, angle voltage A is connected to Y2 and YI is tied to VR;
then
sin(90° - 0)
I
W = V sin(900 _ 0) = V cos (0) = V sec (0)
The principal range is - 90° to + 90°. The most practical amplitude
scaling is provided using the V-preset of I V, when the output
ranges from + 11.47V at 0= -85° and +85°, to + IV at 0=0.
The cosecant differs only slightly: the angle input is connected
to YI and Y2 is connected to analog common, making the denominator sin (0). The principal range is now 0 to + 180°. When
V = IV the output is + 11.47V at 0= + 5° and + 175°, and + IV
at 0=90°.
'
OFFSET MODES
The versine, vers (0) = 1- cos (0), coversine, covers (0) =
1- sin (0), and exsecant, exsec (0) = 1- sec (0) involve the addition
of a constant term to one of the normal trigonometric functions.
These can be generated with the AD639 using the Z2 input to
add a voltage to the output proportional to the amplitude of the
basic function. In the versine and coversine modes this is simply
the same voltage as applied to VI (V2 grounded) to set up
the amplitude of the sign-inverted cosine or sine function,
respectively:
W= V - Uf (0)= U(l-f (0»
In these two modes the output starts at zero and has a peak
value of twice the amplitude voltage, V.
For the exsecant a negative voltage is added at Z2 and this same
voltage is applied to U2 with UI grounded; this satisfIes the
requirement that the sign of U 1 - U 2 be positive. (See comments
on the Amplitude Control Inputs). The angle inputs are set up
for the secant; the principal range is still - 90° to + 90°, but the
output is now zero when the input angle is zero.
OPERATION AT LOW SUPPLY VOLTAGES
The signal ranges at the angle interfaces are essentially independent
of the supply voltages. In almost all cases, the primary limitation
to the function's range will arise at the output, W, which can
swing to within approximately 2V of either supply. For example,
the X-input may have a peak value of ± 12V (± 600°) even
when using ± 5V supplies.
whatever combinations of variables are used to set up the feedback
path. In particular, when the angle inputs are used the system
will have one of the normal functions in the feedback path. The
input to this system is now the ratio (ZIU), and the output is a
voltage corresponding to the angle generated by the inverse of
the function in the feedback path.
Since all of the normal functions are periodic, and the maximum
value of the op-amp output can be equivalent to angles as large
as ± 650°, the closed-loop system could arrive at false "solutions"
to the above equation, that is, at angles outside of the principal
range. Also, the feedback can become positive in the wrong
angular range, causing latch-up. Hence, it is essential to limit
the magnitude of the feedback voltage. Ideally, this is done
using precise active clamps, but the saturated value of the output
at given supply voltages, in combination with a simple resistive
divider to the angle inputs, is usually sufficient to limit operation
to the principal range. The voltage at the angle inputs will be
accurate, but the op-amp output will in general have inaccurate
scaling and may show large offsets, due to the bias currents at
the angle inputs. The error-trap should be disabled in the inverse
modes by grounding GT.
ARCTANGENT MODE
The arctangent is the most useful of the inverse modes. With
the connections shown in Figure 9 the loop solves the equation
sin(O-O) __
_ (ZI- Z2)
sin (90°-0) - tan (0)- (V I - U2)
where 0 is the angle corresponding to voltage A, scaled by 500 N.
It follows that
6
-I
=tan
(Z2- Z I)
(UI-U2)
The reversal of Zl and Z2 in the numerator is due to the negative
sign in the tangent function. The numerator may be either
positive or negative, and the connections can be interchanged to
alter the overall sign of the function. The denominator must be
positive, but UI and V2 may be interchanged to accept a negative
input voltage. The ability of the AD639 to form the ratio of two
5k
+15V
+Vs
CC
Inverse Function Modes
s~
~XI-X2~ -(ZI- Z2)]
sm YI-Y2
where AOL is the open-loop gain of the output op-amp (typically
85dB). Provided that the overall feedback remains negative, the
loop can be closed in many ways, so as to force the quantity
inside the brackets to a null, when
sin (XI - X2)
(ZI - Z2)
sin (YI-Y2) = (U I - V 2 )
9-24 SPECIAL FUNCTION COMPONENTS
15
7 ,.F
CERAMIC
ZINPUT
The AD639 generates the inverse trigonometric functions by
closing the feedback loop around the output op-amp' through
the angle inputs, rather than through the Z-interface, resulting
in a nonlinear feedback system. To understand this, note fIrst
that the general transfer function (with UP disabled) is
W=AOL [(U I - U2)
161-t----.....- -
Ro,
16kf!
Figure 9. Connections for the General Arctangent Mode
Inverse Modes
variables prior to the arctangent operation is very useful in
many applications, for example, in real-time Cartesian-to-polar
conversion (see Applications section). The denominator can also
be preset to IV or lOY using the UP input; when U = IV, the
angle a is simply the arctangent of the voltage value of Z2 - ZI.
Figure 10 shows an X-Y plot of the output for Z = - lOY to
+ lOY (horizontal axis of photograph) with four values of U
(0.3V, IV, 3V, lOY).
Figure 10. The Arctangent Output for Z= ± 10V and
U=0.3V, IV, 3V and 10V
Range-Limiting and Loading
Resistor Rr in Figure 9 forms a divider with the parallel sum of
the input resistance at Xl and Y2 and the load resistance, shown
here as 2k!l, which prevents the output angle voltage A from
exceeding ± 1.7V (0 = ± 85 0 ) , using ± l5V supplies. This voltage
is not directly affected by the load ·resistance (that is, the output
behaves as a low-impedance node) but the angular range limits
are. Consequently, the nominal value of Rr should be calculated
for specific values of load resistance, angular range and supply
voltages, and a trim range of about ± 10% included to set up
the angle limits correctly. Res is needed to compensate the input
bias currents and thus equalize the clipping limits; it does not
cause an offset in o. The direct output at pin 14 is also the
arctangent but with imprecise scaling. Although this can be
trimmed by Rr there will also be a supply-dependent offset due
to Res. For these reasons, the direct output should not be used
in this mode.
HF Compensation
The output op-amp is internally compensated to be stable in all
the normal modes when feedback is via the unity-gain difference
amplifier associated with the Z-interface. The dominant pole is
determined by the 30k!l resistor and on-chip 3.5pF capacitor
(see Figure 1) for a closed-loop bandwidth of l.SMHz. In the
arc-tangent mode, however, the gain of the feedback path is
much greater than unity for practical angle values and is theoretically unbounded. For example, if the forward path is set up to
generate (1 V)tan(O), the incremental gain near 0 = 0 is slightly
less than unity (since a 20mV change in voltage A causes a
change of (lV)tan(lO) or l7.5mV in output W) but at 0=85 0 the
gain is 115. While the resistive divider used to limit the angle
voltage A will lower the loop gain, it can still exceed unity. The
capacitors Cc and Cm in Figure 9 provide the HF compensation
required for operation up to ± 85 0 , with all values of U.
ARCSINE AND ARCCOSINE MODES
The basic principles for the arcsine and arccosine are similar to
those described for the arctangent. As before, the argument of
the function is the ratio (- ZIU), where U may be preset to IV
or lOV, the loop gain must be negative over the principal angular
range of the output, and the feedback voltage must be limited
to ensure that this range is not exceeded. The loop stability is
easier to ensure, since the peak gain is bounded. With U = lOY
the maximum incremental gain of the forward path (at 0° for
the sine and + 90° for the cosine) is 8.75 and the peak loop gain
is much less than this because of the attenuation used to limit
the angular range. Thus relatively little additional HF compensation is required.
Connections for the arcsine are similar to the arctangent (Figure
9) except that Y2 is grounded, and Cc and Cm can be reduced or
even omitted. Rr is adjusted for a peak angular range of ± 90° at
the (attenuated) output; if too high, the function will still be
correct, but the maximum angle will be less than 90°; if too
low, the function will exhibit hysteresis near the peak output.
Adjustments will be needed for other values of load resistance
and supply voltages. Note that the general limitation on the
amplitude input (u<=I-Vsl) must be observed. Figure 11
shows an X-V plot of the arcsine output for Z = -lOY to + lOY
(horizontal axis of photograph) with three values of U (2V, 5V
and lOY). The arcsine can be inverted by reversing the
Z-interfact:.
•
Figure 11. The Arcsine Output for Z = ± 1OV and U = 2V,
5Vand 10V
For the arccosine, use the arcsine connections with Xl tied to
V, and insert a small-signal diode in series with R r, having its
cathode on the angle-interface side. This allows the output to
move only in a positive direction. Zl now becomes the positive
numerator input, and the principal range is from 0° (when
ZIU = - I) to + 180°. The function is similar in appearance to
the arcsine, except for the + 90° output pedestal and the reversal
of phase along the horizontal axis. Note that
cos-I(ZIU) = 90° - sin-\ZIU) = 90° + sin-I( - ZIU).
To generate the negative arccosine, reverse the X- and Z-interfaces
and the polarity of the diode. The output now runs from -180°
for an input of Z = (ZI - Z2) = - lOY (with U = lOY) to 0° at
Z= +IOV.
It is strongly recommended that X-Y oscilloscope methods are
used to investigate functional behavior during the development
of any of these modes of operation: time-domain displays can
easily become confusing.
SPECIAL FUNCTION COMPONENTS 9--25
SQUAREWAVE
OUTPUT (15VI
2k
+15V
±10V
>-+---_0 OUTPUT
TRIWAVE
r'"
:~
I
LINEAR
I P1
FREQUENCYCONTROL - a........yqo,;,JIJl/Ir.:..;
INPUT
(2VFSI
+0------1
110
7
41'18 PIN3} (ONAD654)
±V C>-4"""''''''+i........ PIN4
887
P2
200k
ALTERNATIVE
LOGARITHMIC
374k
FREQUENCYCONTROL INPUT (± 2V FS)
+15V
OPTIONAL
MODULATION o---.--+~
INPUT,U
OPTIONAL
....- - - - 0 GATING
LOADABLE
REFERENCE
OUTPUT, 1.8V
INPUT
1-........---0 -15V
Figure 12. General-Purpose Function Generator
Applications
WIDE-RANGE WAVEFORM GENERATOR
Figure 12 shows an inexpensive signal generator, providing
voltage control of frequency from 20Hz to 20kHz and a pre-set
sine amplitude of 2.8V (within O.ldB of 2V rms). This output
may be further modulated by an input of up to ± 2.8V to U2,
or gated off by an input of + l.SV or more to GT; Figure 13
shows the gated response. If required, a further input can be
summed into Zl. The sine output can be set to lOY amplitude
by connecting UP to va and grounding Ul.
An AD654 is used to generate the triwave which appesrs across
the timing capscitor Cr, and is buffered, amplified and Ievel-shifted
by Al and A2. Using a spectrum ansIyzer, P3 and P4 are adjusted
to minimize even- and odd-harmonic distortion, respectively.
The triwave linesrity is not good enough to reaIize the inherent
capabilities of the AD639, but total harmonic distortion is in the
- SOdB to - 60dB range. A3 provides further gain for a ± lOY
triwave output. The square-wave output is taken directly from
the AD6S4 and is unbuffered. It swings between ground and
+ ISV; if pins 2 and 5 of the AD6S4 are connected to - ISV,
this output is 30V pk-pk.
The frequency scaling with the Iinesr input (shown) is IOkHzIV,
calibrated using Pl. The frequency can be controlled manually,
using a potentiometer and the Vr output of the AD639. PI has
sufficient trim range to provide a full-scale frequency of 20kHz
with the l.8V peak input. The alternstive input scheme provides a "log-sweep" response with an approximate scaling of
lOy kHZ (when V is in volts). The range is now from about
10Hz to 100kHz; the frequency should be set to 1kHz with
V=O, using P2. The frequency is now sensitive to variations in
~26
SPECIAL FUNCTION COMPONENTS
Figure 13. Gated Output. Top Trace: 0 to +2V Gate Input.
Bottom Trace: 2V rms Gated Sine Output
both temperature and the + ISV supply, but stsbility will be
adequate for many applications.
Frequency Multiplication
Because of the exceptionally wide angular range of the numerator
function of the AD639, it is possible to generate sinewave outputs
with 2, 3, 4 or 5 times the triwave frequency using the cosine
mode for even multiples or the sine mode for odd multiples. 2
For example, to multiply the output frequency by 3, use the
sine function with the X-input driven to ± S.4V (±270"). Distortion remains low; all harmonics are typically under - SOdBs,
even for the frequency-quintup1ing mode.
2For full details see "A Remarbble Monolithic Microsystem Generates
Triaonometric Functions," Barrie Gilbert, Illdlutrial Ekaronia Equipment
Duip, September 1984, pp. 19-24. Reprints available.
Applications
+
:!:x
----_--.l!J
+15V
~,~IL~OI-~~---·~
~ r---t-+--L.!J
l.!iJ--.----;-f- - ::!:Aslnlxl
ASlnhdFORA OONLY
/
-15V
"'
AsmixlFORA OONLV
\
I:illr--------'--
OUTPUT'LO'
~
-15V
Figure 14. Four-Quadrant Sine Multiplier; for Cosine,
Interchange Xl and X2 and Connect Angle 'Lo' Input to VR
FOUR-QUADRANT SINE/COSINE MULTIPLICATION
In synchro applications it is often necessary to multiply an AC
sinusoidal 'carrier' by a further sine 'modulation' function. This
can be achieved in two ways; the first is suitable only when
there is a large ratio between the carrier frequency and the
modulation frequency. Using a single AD639, the carrier input
Asin(lIlt) is applied to U2, and a DC bias yoltage established on
Ul (which can be provided by a series resistor connected to
+ V,). The modulation input, x, is applied to angle inputs
connected for - sin(x). The output is then W = - sin(x)
(UI - Asin(lIlt)). Using AC-coupling to the load, the voltage
Asin(x)sin(lIlt) results. Since the peak value of W is (U I + A), a
maxintum of about 6V amplitude can be achieved before output
saturation. A further limitation of this approach is that the ACcoupling may allow excessive transmission of the sine modulation
function. However, with typical values of 400Hz for the carrier
and 10Hz for the upper modulation frequency, this simple
approach is practical. Cosine modulation is similarly achieved.
An alternative method is DC-coupled and thus imposes no
frequency-ratio limitations; it also allows an input/output
amplitude of up to 12V. Two AD639s are used (Figure 14), the
second having both the X- and U-interfaces phase-inverted
relative to the first, and the two outputs are summed. The
figure shows a general bipolar input, A, applied to the U-inputs.
The first device generates Asin(x) when A is positive and zero
when A is negative. The second device generates - Asin(x)
(actually Asin( -x)) when A is negative and zero when A is
positive. The instantaneous sum of the two half-sines is Asin(x).
The switching speed of the U-interface is adequate to handle a
sinusoidal input A=(10V)sin(wt) at frequencies up to at least
1kHz, without significant crossover distortion. In synchro applications errors as small as 5 arc-minutes can be achieved.
Polar-to-Cartesian Conversion
Using a pair of AD639s connected as shown in Figure 14, and a
second pair connected similarly for the cosine function, a vector
of magnitude A and angle x can be resolved into its orthogonal
components Asin(x) and Acos(x), with unrestricted operation in
all quadrants and very high accuracy.
Cartesian-ta-Polar Conversion
A point Z,U in a plane can be converted to a magnitude component,
A, and an angle component, o. A suitable vector summation
circuit can be found in the AD637 data sheet. The AD639 in
the arctangent mode can provide the angle output 0 = tan-I(ZIU).
If U is bipolar, an absolute-value circuit using an AD630 should
be added.
Sine/Cosine (Quadrature) Oscillators
Quadrature oscillators generate a pair of sinusoudal outputs
displaced by 90", and invariably are based on a "state-variable"
loop consisting of two integrators and a sign-inverter. Practical
difficulties in this approach are (1) considerable additional circuitry
is required to control the amplitude of the oscillation; (2) a
trade-off arises between the settling-time of this control circuitry
and the distortion level, particularly troublesome at low frequencies; (3) the amplitude balance of the two outputs is dependent
on the matching of two time-constants; (4) two tracking analog
multipliers or multiplying DACs are needed if the frequency is
to be prolirammable.
These problems are avoided using a function-shaping technique
based on a triwave oscillator, which requires only one time-constant, and whose frequency can thus be more easily controlled.
The need for an amplitude control system is eliminated using
the scheme shown in Figure 15. The two outputs have accurate
amplitudes of 10V (without the need for an external reference
so~) or can be individually controlled by external voltages,
without any effect on frequency. Variable-amplitude sine and
cosine outputs can be added (using the Z-input discussed earlier)
to provide continuously-variable phase-control of the output.
SPECIAL FUNCTION COMPONENTS 9--27
•
Figure 15. Quadrature Oscillator
The triwave oscillator comprises an AD630, which alternates the
sign of the I.SV reference from one of the AD639s to generate a
square-wave output of ± l.SV amplitude, and an integrator
formed by RI, CI and the op-amp, which generates the triwave.
The amplitude of the triwave is determined by the ratio of R3
and R4, and is nominally ± I.S45V, 2.5% higher than needed at
the inputs of the AD639s, providing the adjustment range needed
to minimize distortion. In many applications, all adjustments
can be eliminated; to do this, make R3=R4=5k!l, omit P2,
P4, R5 and R7 and replace PI, P3, R6, and RS with short
circuits. The frequency is nominally 1/4C 1R .. and is 1kHz with
the component values shown. A variety of methods may be used
to provide external control of frequency, including the use of
another AD630 in series with RI, or the use of a multiplying
DAC.
Figure 16. Top Waveform: Difference Voltage Between
Triwave and Squarewave. Bottom Waveform: Resulting
Output
The sine output is generated using the triwave directly. PI and
P2 should be adjusted using a spectrUm analyzer for minimum
odd-order and even-order harmonics, respectively. The cosine
output is generated by using the difference between the triwave
and the square-wave, shown in the upper waveform in Figure
16. This composite voltage first generates a sine-function over
the range 0 to + ISO", then over the range 0 to -ISO°, to produce
the function shown in the lower waveform, which can be seen
to be 90° out of phase with the triwave. The complete set of
waveforms available from this generator are shown in Figure 17.
9-28 SPECIAL FUNCTION COMPONENTS
Figure 17. Timing Relationships Between All Outputs of
the Quadrature Oscillator
Figure 78. Spectrum of Cosine Output at 1kHz
P3 and P4 are adjusted for minimum odd-order and even-order
cosine harmonics, respectively; Figure IS shows the cosine
spectrum for a well-adjusted circuit.
Due to the finite transition time back to the baseline in the
drive voltage to the cosine generator, a brief spike occurs at the
zero-crossing of tIPs output. The frequency components will be
beyond the bandwidth of the output amplifier in the AD639,
and the energy contained in these spikes will not generally be
troublesome. They may be further reduced, if necessary, by
adding a capacitor between pins 14 and 15, to roll off the AD639
output response.
Precision, Wideband
Channel Processing Element
AD890 I
r'IIII ANALOG
WDEVICES
FEATURES
An 80MHz Bandwidth Permitting a 50Mb/s Data
Transfer Rate
A Variable Gain Amplifier with 30dB max Gain
and 40dB Control Range
Two Gain of 4 RF Buffers
200n Differential Load Drive Capability
A Pair of Precision Rectifiers
AGC Level and Threshold Outputs
An Averaging, High Gain Sample-and-Hold for
Accurate AGC Operation
Typical Gain Drift in Hold Mode: O.2dB/ms
Gains Trimmed and Temperature Compensated
AGC Operation Independent of AGC Level
Symmetrical AGC Attack/Decay Times
1... s AGC Attack/Decay Times Using a 1000pF
External Capacitor
"
J ',; ',;,
Suitable for Use as an Accurate Video ProQ!Ii~bW ,\,
Gain Amplifier
", "
'c"
Dynamic Clamp Ensures Fast RecQJliri'J\,fter ,Writetc:l1;"
Read Transients
, """,,:,,""':;1,,"", "":: ):'
", '. .:, "'''i
AGC RF Output Level is Int~~ij"tJ,·.~e~et
'
;,1-
PRODUCT DESCRIPTION
)"
'j",';,
I,.:
,,
"
The AD890 is primarily intended for high-performance di$k
subsystem use and as such it is configured around the classic'
read channel processing block diagram. It is intended to be
connected between the head preamplifier and the qualification
circuitry required for digital data recovery. When used with the
AD891 rigid disk data qualifier, data transfer rates in excess of
50Mb/s can be processed.
A temperature-compensated AGC loop, with an exponential
transfer characteristic, permits optimal settling and allows for
predictable performance in the classic single integrator control
loop configuration. Fast acquisition and low droop while in the
hold mode allow for AGC operation to be performed within the
sector header without compromising channel behavior when
reading data.
The AD890 processing element has the flexibility to perform
both continuous and sampled AGe functions; it is also ideal for
embedded, dedicated, or mixed servo applications. Two userdefined filter/equalizer stages may be employed, thus allowing
maximum design flexibility. This greatly simplifies the design of
the overall channel characteristics. Using the AD890, the designer
no longer needs to resort to passive techniques to isolate network
functions; this avoids problems of signal loss and interaction.
AD890 FUNCTIONAL BLOCK DIAGRAM
POSITIVE
INPUT
NEGAT1VE
INPUT
POSITIVE
OUTPUT
NEGATIVE
OUTPUT
ANALOG
GROUND
+SV de
POSITIVE
INPUT
NEGATIVE
INPUT
POSITIVE
OUTPUT
NEGATIVE
OUTPUT
POSITIVE
INPUT
NEGATIVE
INPUT
;~rf!:;i,,"
" '11)1(0 I~w-offset, IOOMHz full-wave rectifiers provide the capability
toi/track a 1V peak signal. The rectifier generating the "Qualifier
Threshold" output may be used for creating a data qualification
level. A second rectifier is used to drive the sample-and-hold
circuitry.
The 80MHz bandwidth of the AD890 ensures good phase linearity
up to 50MHz. Thus, data transfer rates in excess of 50Mb/s can
be supported with good error rates and predictable channel
behavior.
The AD890 is available in both a 24-pin, slim-line cerdip package
and in a 28-pin PLCC package and is specified to operate over
the 0 to 70°C commercial temperature range.
PRODUCT HIGHLIGHTS
I. A highly predictable gain control function allows the user to
perform a very accurate preset operation and facilitates DIA
converter control capability.
2. Two low-offset, lOOMHz full-wave rectifiers are provided.
3. An internal clamping circuit ensures short recovery times
after read/write switching of the external head chip.
4. An 80MHz bandwidth ensures good phase linearity.
5. A O.2dB per ms droop in gain during AGC hold mode.
6. All RF gain stages offer calibrated temperature-stable gains.
SPECIAL FUNCTION COMPONENTS 9-29
•
SPEC IFICAli 0NS
(@+25"& and ± 5V dc, unless otherwise noted)
AD890J
Model
VARIABLE GAIN AMPLIFIER
Maximum Gain I
± 3dB Bandwidth
Input Voltage Noise
Input Signal Range
Input Resistance
Output Impedance
Harmonic Distortion
Conditions
Up to 26dB Gain Reduction
OdB Gain Reduction, f = 1kHz
Recommended POp Differential
Min
T
Max
Units
29.5
100
30.0
30.5
dB
MHz
nV/vHz
mV
10
OdB Gain Reduction
26dB Gain Reduction
Output dc Level
INPUT CLAMp2
Turn-On Time
Turn-Off Time
Input Signal Attenuation
On-State Input Impedance
GAIN OF 4 BUFFER
Nominal Gain
Gain Variation
± 3dB Bandwidth
Input Voltage Noise 3
Input Resistance
Input Common-Mode Range
Output Resistance
Harmonic Distortion
Output Signal Level
Output dc Level
FULL WAVE RECTIFIER
Input Signal Level
- 3dB Bandwidth
dcOffset 4
AGC CONTROL SECTION
Attack Time
Hold Time
AGC Control Range
AGC Control Sensitivity
AGC Control Linearity
Set Level Input Range
200
12
n
0.15
1.5
3.5
%
%
V
ns
ns
dB
n
Differential
13.00
Tmmto Tmax
f
=
1kHz
V
IO
n
0.20
%
V
V
1.3
2.5
1
dB
dB
MHz
nV/vHz
kn
+1.5
d
POp Dift'dten~ial
100mV(illVPeak
0.3
±20
V
MHz
mV
±0.2S
800
Vee
ns
ms
dB
dB,
dB
mV
V
3
100
IO
26dB Gain Step -I OOOpF CSAMPLE
26dB Gain Step - < SOpF CSAMPLE
IdB Gain Change - I OOOpF CSAMPLE
36
Per 20mV Input
26dB AGC Range
For Specified Accuracy
Nondestructive Input Range
MODE CONTROL SECTION
TTL Compatible
V IH
1.0
120
10
40
o
-0.3
fLs
V
2.0
VIl.
0.8
100
2.0
SO
IIH
Ill.
Mode Switching Times
POWER SUPPLY REQUIREMENT
Rated Performance
Operating Range
Quiescent Current
Vee
VEE
kn
5
nA
fLA
ns
v
±S.O
±4.6
V
±6.S
V
76
40
rnA
rnA
T nun to T max
44
18
60
28
NOTES
IGam cahbrated In gam set mode wIth 0 volts appbed [0 the Gam Set Pm
lClampoperatlOn IS specified with a source Impedance 0[2000 10 senes with O.I,.,.F
.lOver the fullIOOMHz bandwidth of the AD890, the worst-case rms slgnal-to-nOise ratio
IS 40dB or better with a 40dB AGe range.
"Measured usmg a 4k!} resIstor connected between the Quahfier Threshold Pm and V I I .
9-30 SPECIAL FUNCTION COMPONENTS
Specifications subject to change without notice.
All mm and max specificatIOns are guaranteed. Specifications In boldface are tested on
all productIon UDlts at final electrical test Results from those tests are used to calculate
outgomg quahty levels.
Logic Assignments
AGCAcquire
AGCHold
Gain Set
Input Clamp
Bit 0
0
0
I
Bitl
ORDERING GUIDE
0
I
0
Model
Package
Package
Options*
AD890JQ
AD890}P
24-Pin Cerdip
28-PinPLCC
Q-24
P-28A
*See Section 16 for package outline information.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . .
"!:'7.SV
RF Gain Stage Differential Input Voltage
"!:'S.6V
Storage Temperature Range
AD890}P, AD890}Q . . . . . . . . . . . - 65°C to + 150°C
Operating Temperature Range'
AD890}P, AD890}Q . . . . . . . . . .
o to + 70°C
Lead Temperature Range (Soldering 60sec)
NOTE
'2S-pin PLCC package: aJA ~ 100"CIW;
24-pin cerdip package: aJA ~ SO"CIW.
*Stresses above those listed under "Absolu~)~
permanent damage to the device. This ~'_ ';,.\,,' '
functional operation of the dev~ce .-t/:,~~, ot:,a~
those indicated in the Opjfra~';,';,~~ions of
implied. Exposure 1O""absof~" ~~iIltnuin
periods may affect
i~r~liabil,i;y"
24-Pin Cerdip Package
28-Pin PLCC Package
w
>~
:.
POSITIVE
INPUT
SAMPLE·
AND·HOLD
CAPACITOR
u
z
E~
~~
w
,,~
!:i~
ffi~
z
NEGATIVE
5
OUTPUT
NEGATIVE
INPUT
GAIN SET
3
POSITIVE
SAMPLE·
AND·HOLD
CAPACITOR
4
NEGATIVE
ANALOG
GROUND
OUTPUT
OUTPUT
AGe
ANALOG
RECTIFIER
POSITIVE
GROUND
INPUT
+5Vdc
DIGITAL
POSITIVE
GROUND
INPUT
QUALIFIER
THRESHOLD
RECTIFIER
INPUT
NEGATIVE
QUALIFIER
INPUT
THRESHOLD
OUTPUT
NEGATIVE
NEGATIVE
POSITIVE
RECTIFIER
INPUT
POSITIVE
OUTPUT
OUTPUT
OUTPUT
OUTPUT
NC
POSITIVE
9
RECTIFIER
INPUT
POSITIVE
NEGATIVE
INPUT
DIGITAL
GROUND
INPUT
+
~
,,~
NEGATIVE
INPUT
~~
~~
~~
~~
~~
CJ"
~o
w~
""
5
20
~~
iii
U
z
w
,,~
~"
~~
@~
z
w
E~
~;r;
~~
~~
~~
~5
NC = NO CONNECT
SPECIAL FUNCTION COMPONENTS 9-31
Applying the AD890
GENERAL LAYOUT REQUIREMENTS
Almost 60dB of total gain is available at lOOMHz. Care must be
taken to ensure good RF practice in the PC layout to avoid
oscillations in the ISOMHz-3S0MHz region. A parallel combination
of O.lfLF and O.OlfLF ceramic bypass capacitors should be used
as close to the, supply pins as possible.
Additionally, a single pole RC fIlter applied at the input of each
stage, with a cut off in the region of lOOMHz-ISOMHz, will
help avoid oscillation problems. As a general rule, keep the
connections to interstage components as short as possible; it is
also recommended that any low pass fIltering function which
may be required by the system be performed between the VGA
stage and the first X4 buffer amplifier. A ground plane should
be used to surround any interstage components wherever possible.
If these simple rules are followed, stable operation should be
assured.
OPERATING THE FULL WAVE RECTIFIERS
The full wave rectifiers consist of two nearly identical stages.
Full wave rectification is performed in each stage using two
transistors whose emitters are connected together. The inputs to
the two full wave rectifiers are biased at one diode drop above
analog ground; therefore, ac coupling is recommended. The full
wave rectifier outputs - "AGC Rectifier" and "Qualifier
Threshold" - are connected directly to these commoned emitters.
Thus, the normal output voltage with zero input signal applied
is close to analog ground. The "AGe Rectifier" pin allows
access to the output of the rectifier which drives the AGC sampleand-hold section of the AD890. The "Qualifier Threshold" pin
allows access to th~ output of the threshold rectifier.
The AGC rectifier has an internal 2kO resistive pull-down
connected between analog ground and the negative power supply
pin. The threshold line has no built in pull-down, in order to
allow for a peaf hold capability during thresholding. If a well
BIASING THE RF GAIN STAGES
controlled ~er offset is required, an external 4kO pull-down
The VGA Stage
resistof:~f~,/Ie"'49ualifier Threshold" pin is recommended and
will proQJice,a nominal 10mV offset.
The 30dB variable gain stage is biased at a potential of one
':,': ''':, ""
diode drop above analog ground. No additional de bias is required,,,:,"
but ac coupling is necessary. The bias voltage is maintainec(
''':THE AGC SAMPLE-AND-HOLD
during normal operation and during operation of the clamp:,)ri:,,, ,:' "The Aa¢'~pw,and-hold section performs averaging of the
input wavefohn to set the RF average output level to 200mV
order for the clamp to operate correctly with an emittiir'foHo~r;
driven input, 500-1000 resistors should be pl~ed in:§:;ti~s':with
' sif1$1e ~i:!ed, or 330mV peak for a sinusoidal signal. Thus,
the input coupling capacitors. These resis~¥,c'iII,!:\~I:!,uSed il1"
'iIl.irhoU't a peak hold capacitor at the "AGC Rectifier" pin, accurate
, '" AGC o:peration only occurs with sinusoidal input signals. An
conjunction with a S.lpF shunt capllPtor to":iiI;o;it,'the inIDlt'
amtro:idI1ljjte 2mA pull-down current is permanently present at
bandwidth to ISOMHz. In the case Of'"IIt1'open colle\:tOi"·d'dven,
the "A(iC Rectifier" pin, and a capacitor may be added here to
input with resistive termination"RO adUitional seri!!s)'esistors
are required.
'"," "','
provide a degree of peak hold for AGC operation within non"", ',:
' ,
sinusoidal fields. A capacitance value of less than 0.03fLF or less
per fLS of transition spacing is recommended. The addition of
The differential outputs have a nominal de "'alue of I.SV less
than the positive supply. Internal 13000 resistors provide biM
the capacitor alters the symmet~y of the attack and decay rates
of the rectifier, which is otherwise symmetric in operation. In
current to the output emitter followers which operate with 2.7mA
order to ensure that the overall AGC response is the same for
nominal current. Output drive can be increased by an additional
2.SmA by paralleling external resistors to either the analog
both high-to-low and low-to-high input level steps, it is necessary
ground or the negative power supply. However, caution should
to make the rectifier attack and decay times at least a factor of
be exercised in order to avoid causing excess dissipation for the
two less than the AGC response time.
package. The recommended output level for th~ VGA is 300mV
Pop differential into 2000 loads.
The AGC acquire time is approximately IfLS per 1000pF of hold
capacitor. A low leakage variety of hold capacitor, such as a
silver mica, is necessary to ensure low droop rates. The "Gain
The X4 Buffers
Set" pin should be tied to analog ground if not used, in order to
The inputs of these stages have no committed de biasing, and
prevent excessive leakage which would otherwise affect the hold
an input bias current path must be provided. This path can
performance. '
normally be supplied via shunt resistors to analog ground which
are generally part of the interstage fIlter termination networks.
The AGC control potential is present at the "Sample-and-Hold
The inputs can be biased successfully within ± l.SV of analog
Capacitor" pin. If control over open-loop gain is desired, based
ground.
on AGC control potentials obtained during trial AGC operations,
c,:,'< '
Output drive can be increased in a similar manner to that described
for the VGA stage. The nominal dc output level is 2.SV with
the internal 5000 load resistors connected to analog ground
which provides a nominal standing current of SmA to the output
emitter followers. This current can be increased by up to an
additional SmA by paralleling external resistors to either analog
ground or the negative power supply. As before, precautions to
limit excessive overall power dissipation apply when steps are
taken to increase the output drive capability.
9-32 SPECIAL FUNCTION COMPONENTS
a FET input op amp should be used to buffer this node in
order to avoid disturbing the hold operation.
USING THE AD890 AS A PROGRAMMABLE GAIN
AMPLIFIER
The ADS90 is ideally suited for use as an accurate video programmable gain amplifier. If the X4 buffers are utilized with
the variable gain amplifier, nearly 60dB of total gain is available
at frequencies up to 100MHz. The VGA gain and exponentiator
scale factors are trimmed with respect to dc control potentials
applied to the "Gain Set" pin. In this mode of operation (see
Logic Assignments for bit pattern to be applied to the "Bit 0"
and "Bit 1" pins), a OV dc potential applied to the "Gain Set"
pin will produce a nominal VGA gain of 30dB. With an additional
12.75dB from each X4 buffer, total nominal gain is 55dB. Each
20mV increment of voltage applied will produce a IdB reduction
in gain. A simple equation can be used to calculate the nominal
gain of VGA in this mode:
VGA Gain (dB) = (30 - VGA1N
where VGA1N
SET
SET X
50)
is in volts.
OPERATION WITH +5V, +12V SUPPLIES
Operation with + SV (± 0.2SV) and + 12V (± 1.2V) suppJi
'
readily achieved. Figure 1 shows the ADS90 configure
+ SV, + 12V operation. The analog and digital gro
R3
SkU
R1
Both the + SV and + 12V supplies should be RF bypassed to
ground with at least two capacitors: values of O.Ij.LF and O.OIj.LF
are recommended. In addition, some higher level of decoupling
capacitance such as 3.3j.LF value may be desirable. Next, insert
a series-connected 6. SO 114W resistor and 100mA diode in
series with the + 12V supply. This helps to reduce overdissipation
in the chip.
Power supply decoupling should occur on the circuit side of the
resistor-diode network. A second diode can be substituted for
the 6. SO resist .f the voltage difference between the two supplies
volts.
trol is achieved by using open collector drivers
as shown; 5.1V Zener diodes can be substituted
ors ~. and R2. Internal diode clamping in the ADS90
s ~~.~~,,;!}l operation.
'h:hing times will be affected by resistor values
is due to the RC time constants formed by the
n conjunction with the input capacitance of the chip
.,.~*" a~~, ~.
+12V
39kU
connected to the + SV line or to an available center tap of the
+ 12V supply. Thus connected, a current of approximately
30mA will flow in this line under normal operation. The input
clamping action occurs with respect to this line, increasing its
current by an additional 12mA or so.
R2
39kU
AD890
,,!!,'i~E , fING WITH THE AD891 RIGID DISK DRIVE
,.:~1,~"DAl!A QUALIFIER
~jt';~t>igure 2 shows a typical application using the ADS90 and ADS91
\.1, connected together to create a 30MHz channel (cerdip connections
shown). This circuit includes as-pole 30MHz Gaussian-to-6dB
transitional filter plus a second-order RLC time domain equalizer.
A typical second-order, fully differential, passive delay-line
differentiator interface for the ADS91 is also included. (For a
more detailed description of the delay-line differentiator, see the
ADS91 data sheet.) The analog and digital grounds should be
connected at the power supply common.
Figure 1. A 0890 Connection for +5V, + 12VOperation
SPECIAL FUNCTION COMPONENTS 9-33
•
I
50 MHz _ 3dB POINT
40 nS PW50
RLC EQUALIZER
5TH ORDER GAUSSIAN-TO-6dB
62,.H
o
733
636
5k
2••
5k
DATA
OUT
n
H--+-<>
lk
15ns
PULSE
1k
-sv
-4-
DIGITAL GND
~ANALOG GND
~\. '~;;,"~~, "~~•• ,fl;C
Figur!1f['~~ A
'k!~;.,. ':i.'.:;:'11~;':","
.,"
,I',
..:,p.
.,',"
,;~
,
(1.
itt
~ 1, ...1
nnect.ioljf,~r a 30MHz Channel
,, ·t;'/,,:"
The AD890 is ideal for applications whet1l'~u~on ~~.!: \~'~""~hus minimizing problems of overequalization. To alter k, the
ployed. The X4 buffer output drivers are ~igned to op~E';/~ 't.
ratio of the 1.1kn and 953n resistors should be changed. To
alter T, the reactive element should be scaled proportionally.
into 200n loads, making tapped delay-line designs easy. sillri'"
The equalizer in Figure 2 is optimized for k = 0.6 and
and differencing of different tap weights can be achieved by
simple resistive dividers.
T = 12ns.
As an alternative, a simple RLC network can be implemented to
provide a low-cost, fully differential alternative to the three-tap,
tapped delay-line equalizer which often is used for pulse slimming.
Essentially, the equalizer shown in Figure 3 consists of an RC
lattice, which provides the magnitude characteristic, together
with an LR shunt section which acts to define the overall passband
group delay and the ratio of minimum to maximum gains within
the passband.
5kU
It is important to note the benefits of fully differential (as opposed
to single-ended) operation: 1) reduced harmonic distortion due
to symmetric operation; 2) improved power supply noise rejection;
3) less insertion loss, allowing for reduced gain and, hence,
improved distortion in stages prior to the equalizer.
CHOICE OF LOW PASS FILTER WITH THE
RECOMMENDED EQUALIZER
A fifth order, Gaussian-to-6dB transitional filter is recommended
for use with the equalizer. Such a low pass filter is shown in I
Figure 4. Low group delay ripple and high out-of-band rejection
make this design work well with the recommended equalizer
and the differentiator specified in the AD891 data sheet. The
recommended location for the low pass filter is between the
VGA and first X4 buffer. The eqnalizer should be placed between
the first and second X4 buffers. This minimizes the potential
for oscillations induced by interstage parasitic feedback.
5kU
Figure 3. RLC Equalizer
The network shown approximates a function of the form:
F(wT) = l-k cos wT,wherek= 0.6,andT = 36ns.
The circuit is optimized for a 120ns transition PW50. Altering
the 953.0 resistor and the 24 ....H inductor can change both k and
9-34 SPECIAL FUNCTION COMPONENTS
Figure 4. 5th Order Gaussian-to-6dB Transitional Filter
Rigid Disk Data
Channel Qualifier
IIIIIIII ANALOG
WDEVICES
AD891 I
AD891 FUNCTIONAL BLOCK DIAGRAM
FEATURES
Three Matched, Offset-Trimmed Comparators
3.1ns (typ) Comparator Propagation Delay
Eel logic Permits 50Mb/s Transfer Rates
6.8ns Delay (typ) from Inputs to Data Output
500ps (typ) Additional Pulse Pairing
Temperature-Compensated Operation
Compatible with 10kH ECl logic
Two Temperature·Compensated One·Shots
One-Shot Periods Set Using External Resistors
LEVEL
IN+
DlFF -
LEVEL
IN -
AMP+
OIGITAL
GND
Vee
DIGITA~
',~
PRODUCT DESCRIPTION
The AD891 disk channel qualifier is intended as a COl11P
chip to the AD890 wideband channel processor. T 'I."
OUTPUT
PULSE SET
",
Y~1.
,,_
'/'7,".;'"
~omprise. a sophisti~ated p~c~ge, capableo! ~ov,
"i",,':"ft'~~heouslY, an output one.shot is activated, the leading
mformauon from d!fferenuatmg channels"wnh ~~et rat~,l~V;\~;:"::'j!d~e of which is synchronous with the change in the flip-flop
excess of 50 megabns per second. . ' " , ,,;~, !".:i;)~, "{f;, '" OuijlU~i"1Pe period of this one-shot is also user.definable and is
dtiiiendil(t:'i"bensure adequate output pulse duration for transmission
The AD891 provides both levd)Jia ~e-doma.in ~;\for
a 30MHz Channel
"'l,< '.,
. ,
.
.'
OPERATION WITH +5V, +12V SUPPLIES
.,.'
J'
'.•
.
Operation with + SV (± O.2SV) and + flY. (±UV') su~ksi$
readily achieved. The digital ground pins milst be connect&i.~6
the + SV line or to an available center tap of the + 12V supply.
The specified output EeL logic levels are therefore referred to
the + SV supply. Pull-down resistors for the "Data +" and
"Data-" pins should be connected to VEE' Thus connected, a
current of approximately 23mA will flow in the + SV supply
under normal operation.
In order to ensure correct comparator operation, a pair of lOOmA
diodes should be added in series with the + 12V supply which
is connected to the Vee terminal. This connection is shown in
Figure 4 (shown for cerdip package).
Both the + SV and + 12V supplies should be RF bypassed to
ground; the values of O.lI1F and 0.0 1l1F in parallel are recommended. In addition, some higher value of decoupling capacitance
- such as 3.3I1F - may be desirable. This decoupling should be
applied directly at the AD891 "Vee" and "Digital GND" pins.
Finally, the common-mode range for the comparators is now
referred to the + SV supply line, and care must be taken to
operate within the common-mode limits.
9-40 SPECIAL FUNCTION COMPONENTS
'l,,-
lN4001
r----..-t----~-*----o+12V
)-.-.._--.--o+5V
} - - - - - . , - - o DATA +
} - -.....- - + - - o DATA lkU
Figure 4. AD892 Connection for +5V,
+ 12VOperation
11IIIIIIII
Digitally Programmable
.Delay Generator
ANALOG
WDEVICES
AD9500 I
AD9500 FUNCTIQNAL BLOCK DIAGRAM
FEATURES
10ps Delay Resolution
2.5ns to 100....s+ Full-Scale Range
Fully Differential Inputs
Separate Trigger and Reset Inputs
Low Power Dissipation - 310mW
DIF:~:t~~AL. I------i
RESET
APPLICATIONS
ATE
Pulse Deskewing
Arbitrary Waveform Generators
High-Stability Timing Source
Multiple Phase Clock Generators
INPUT
Q
STAGE
RESET
INTERNAL OAe
TTL lATCHES
-v,
GENERAL DESCRIPTION
The AD9S00 is a digitally programmable delay generator, which
provides programmed delays, selected through an 8-bit digital
code, in resolutions as small as lOps. The AD9S00 is constructed
in a high-performance bipolar process, designed to provide
high-speed operation for both digital and analog circuits.
PIN CONFIGURATIONS
•
The AD9S00 employs differential TRIGGER and RESET inputs
which are designed primarily for ECL signal levels but function
with analog and TTL input levels. An on-board ECL reference
midpoint allows both of the inputs to be driven by either single
ended or differential ECL circuits. The AD9S00 output is a
complementary ECL stage, which also provides a parallel QR
output circuit to facilitate reset timing implementations.
The digital control data is passed to the AD9S00 through a
transparent latch controlled by the LATCH ENABLE signal. In
the transparent mode, the internal DAC of the AD9S00 will
attempt to follow changes at the inputs. The LATCH ENABLE
is otherwise used to strobe the digital data into the AD9S00
latches.
coo'iccc
4
3
2
1
28 27 26
0 7 (MSB) 5
250 0 (LSBI
24 LATCH ENABLE
23 GROUND
OFFSET ADJUST 7
AD9500
TOP VIEW
iNotto Scate)
C, 9
The AD9S00 is available as an industrial temperature range
device, - 25°C to + 85°C, and as an extended temperature range
device, - 55°C to + 125°C. Both grades are packaged in a 24-pin
ceramic "Skinny" DIP (0.3" package width), as well as 28-pin
surface mount packages. Contact the factory for MIL-STD-883,
revision C, qualified devices.
21 Rs
+Vs 10
TRIGGER "
20 -Vs
~::~~;:::=:=:::;
12
13 14
Io~
\!i!
15 16 17
19 Eel COMMON
18
ffil~~~O'OIO
••
~
NC
='
NO CONNECT
ORDERING INFORMATION
Device
Temperature Range
AD9S00BP
AD9S00BQ
AD9S00TE
AD9S00TQ
-
25°C to
25°C to
55°C to
55°C to
+ 85°C
+ 85°C
+ 125°C
+ 125°C
Description
Package
Options·
28-Pin PLCC (Plastic), Industrial Temperature
24-Pin "Skinny" DIP, Industrial Temperature
28-Pin LCC, Extended Temperature
24-Pin "Skinny" DIP, Extended Temperature
P-28A
Q-24
E-28A
Q-24
*See Section 16 for package outline information.
SPECIAL FUNCTION COMPONENTS 9-41
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS!
Positive Supply Voltage ( + Vs) . . . . . . . . . . . . . . + 7V
Negative Supply Voltage (- Vs ) . . . . . . . . • . . . . . -7V
ECL COMMON to Ground Differential .. - 2.0V to + 5.0V
Digital Input Voltage Range . . . . . . . . - 3.5V to + 5.0V
TriggerlReset Input Voltage Range . • . • • . • • • . . ± 5.0V
TriggerlReset Differential Voltage . • • . . . . . • . . . 5.0V
Minimum RSET . . . . . . • . . . . . . . . . . . . . . . 2200
Digital Output Current (Q and Q) . . . . . . . . . . . 30mA
Digital Output Current (QIJ . . . . . . • . . . • . . . . 2mA
Offset Adjust Current (Sinking) . • • • . . . . . . . . . . 4mA
Power Dissipation (+25OC Free Air)2 . . . . . . . . . . 2.62W
Operating Temperature Range
AD9500BPIBQ . . • . . . . . . . . . .. - 25·C to + 850C
AD9500TElTQ . . . . . . . . . . • . . . - 550C to + 1250C
Storage Temperature Range . • . . . • . . . -65·C to + 1500c
Junction Temperature. . . . . . . . • . . . . . . .. + 1750C
Lead Soldering Temperature (10sec) . . . . . . . . . + 3000C
ELECTRICAL CHARACTERISTICS (SUpplyVoIIages + Vs = +5.DV, -Vs = -5.2V;Cm = OpF;Rsa = 5000,
unless otherwise staIad)
Mil3
Parameter
Sub
Group
Temp
RESOLUTION
Industrial
- 2S·C to + 8SOC
AD9S00BP/BQ
Min
Typ
Max
Min
8
8
ACCURACy4
Differential Linearity
Integral Linearity
Monotonicity
7
7
7
+ 25·C
+ 25·C
+ 25·C
DIGITAL INPUT
Logic "1" Voltage
Logic "0" Voltage
Logic" 1" Current
Logic "0" Current
Digital Input Capacitance
Data Setup TimeS
Data Hold Time6
Latch Pulse Width (tLPW)
7,8
7,8
1,2,3
1,2,3
12
12
12
12
Full
Full
Full
Full
+ 25·C
+ 25·C
'+25·C
+ 25·C
7,8
1
2,3
Full
Full
Full
+25OC
Full
-2.5;4.5
-2.5;2.0
40
40
+25~C
12
+ 25·C
4
6.5
+ 25·C
2.0
RESETrrRIGGERINPUTS7
TRIGGER Input Voltage Range
RESET Input Voltage Range
Differential Switching Voltage
Input Bias Current
Input Resistance
Input Capacitance
Minimum Input Pulse Width
(tTPW, tRPW)
DYNAMIC PERFORMANCE"
Maximum Trigger Rate
Minimum Propagation Delay (tPD)9
Minimum Propagation Delay TC10
Full-Scale Range TC
Delay Uncertainty (Jiner)
Reset Propagation Delay (tRD)l1
Reset-to-Trigger Holdoff(tTHo)12
Trigger-to-Reset Holdoff (tRHo)i3
Minimum Output Pulse Width
Output Rise Time
Output Fall Time
Delay Coefficient Settling Time (tDAc)14
Linear Ran!p Settling Time (tLRS)
12
4
4
4
4
12
12
9-42 SPECIAL FUNCTION COMPONENTS
+ 25·C
+ 25·C
Full
Full
+ 25·C
+25OC
+25OC
+25OC
+ 25·C
+ 25·C
+ 25·C
+ 25·C
+ 25·C
Military
- ss·c to + 12S·C
AD9S00TEfI'Q
Typ
5.4
0.2
2.0
LSB
LSB
0.8
5
5
5.5
0.75
0.75
V
V
jIA
jIA
pF
ns
ns
ns
300
50
75
V
V
mV
/-LA
/-LA
kO
pF
2.0
0.8
5
5
5.5
0.75
0.75
3.0
100
5.4
0.5
1.0
Guaranteed
2.0
0.4
0.4
0.4
0.4
3.0
6.4
7.5
0.5
10
6.4
0
1.5
3.3
-2.5;4.5
-2.5;2.0
40
40
300
50
75
4
6.5
7.25
7.25
2.0
7.4
7.4
100
5.4
5.4
0.2
2.0
6.4
7.5
0.5
10
6.4
0
1.5
3.3
2.0
2.0
29
22
Units
Bits
0.5
1.0
Guaranteed
Max
ns
7.4
7.4
2.0
2.0
29
22
MHz
ns
ps!"C
psl"C
ps
ns
ns
us
ns
ns
ns
ns
ns
Mil3
Sub
Group
Parameter
SUPPORT FUNCTIONS
ECLREF
ECLREF Voltage Drift lS
Offset Adjust Range
DIGITALOUTPUTS8
Logic "1" Voltage
Logic "0" Voltage
POWER SUPPLyl6
Positive Supply Current ( + 5.0V)
Negative Supply Current (- 5.2V)
Nominal Power Dissipation
Power Supply Rejection Ratio l7
Full-Scale Range Sensitivity
Minimum Propagation Delay
Sensitivity
Temp
Industrial
- 2S·C to + 8S·C
AD9S00BPIBQ
Min
Typ
Max
+ 25'C
Full
Full
-1.4
1,2,3
1,2,3
Full
Full
-1.1
1
2,3
1
2,3
+25OC
Full
+25OC
Full
+ 25'C
37
7
+25'C
70
300
7
+25'
150
500
1
NOTES
IAbsolute maximum ratings are limiting values, to be applied individually,
and beyond which serviceability of the circuit may be impaired. Functional
operability under any of the.. conditions is not necessarily implied.
Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
'Typical tbermaI impedance
24-PinCeramic
0IA =S6"C/W;Olc= 16"C/W
28-PinPLCC(Plastic) 0IA =60"C/W; 0IC= 22"C/W
28-Pin Cerantic LCC
0IA = 69"CIW; 0IC = 2S'C!W
'Military subgroups apply to military qualified devices only.
4RsET = IOkO. (Full-scale delay = lOOns).
'The digital data inputs must remain stable for the specifIed time prior to
the LATCH ENABLE signal.
"The digital data inputs must remain stable for the specified time after the
LATCH ENABLE signal.
'The TRIGGER and RESET inputs are differential and must be driven
relative to one another. Both of the.. inputs are ECL compatible, but
can also be used with TTL logic families in a limired fasbion.
·Outputs terminated through son resistors to -2.0V.
-1.3
-1.2
Military
- SS·C to + 12S·C
AD9S00TEJTQ
Min
Max
T,p
-1.4
1.1
-2
-1.3
1.1
-2
-1.2
-1.1
-1.5
24
28
30
42
44
-1.5
V
mVI"C
rnA
V
V
28
30
42
44
rnA
rnA
mA
rnA
mW
70
300
ps/V
150
500
ps/V
24
37
312
Voits
312
'Program Delay = O.Ops (Digital Data = 00,,). In Operation, any
programmed delays are in addition to the Minimum Propagation Delay.
I·Measured from the SO% transition point of the reset signal input, to the
SO% transition point of tbe resetting output.
11 Minimum time from falling edge of RESET to triggering input, to insure a
valid output event.
"Change in total delay througb AD9S00, exclusive of changes in minimumpropagation delay tpD.
"Minimum time from triggering event to rising edge of RESET, to insure a
valid output event.
14Measured from the LATCH ENABLE input to the point when the
AD9S00 becomes 8-bit accurate again, after a fnll-scale change in
the programmed delay.
"Standard 10K and IOKH ECL families operate with a 1.ImVrc
drift by design.
"Supply voltages shonld remain stable within ± S% for normal operation.
"Measured at ± S% of - V. and + V •.
Specifications subject to change without notice.
EXPLANATION OF GROUP A MILITARY SUBGROUPS
Subgroup
Subgroup
Subgroup
Subgroup
Subgroup
Subgroup
Subgroup
I2345-
Static tests at + 25°C.
Static tests at max rated operating temp.
Static tests at min rated operating temp.
Dynamic tests at + 25'C.
Dynamic tests at max rated operating temp.
6 - Dynamic tests at min rated operating temp.
7 - Functional tests at + 25'C.
Subgroup 8 - Functional tests at max and min rated
operating temp.
Subgroup 9 - Switching tests at + 25'C.
Subgroup 10 - Switching tests at max rated operating temp.
Subgroup II - Switching tests at min rated operating temp.
Subgroup 12 - Periodically sample tested.
SPECIAL FUNCTION COMPONENTS ~
•
I
FUNCTIONAL DESCRIPTION
PIN NAME
0 4-06
0 7 (MSB)
ECLREF
OFFSET ADJUST
Cs
+Vs
TRIGGER
TRIGGER
RESET
Q
ECLCOMMON
-Vs
Rs
GROUND
LATCH ENABLE
Do (LSB)
DESCRIPTION
- One of eight digital inputs used to set the programmed delay.
- One of eight digital inputs used to set the programmed delay. 0 7 (MSB) is the most significant bit of
the digital input word.
- ECL midpoint reference, nominally -1.3V. Use of the ECL REF , allows either of the TRIGGER or
the RESET inputs to be configured for single-ended ECL inputs.
- The OFFSET ADJUST is used to adjust the minimum propagation delay (tpo), by pulling or
pushing a small current out of or into the pin.
- Cs allows the full-scale range to be extended by using an external timing capacitor. The value of
CEXT> connected between Cs and + Vs, may range from OpF to O.lIJ.F +. See Rs (CIN"rERNAL
= lOpF).
- Positive supply terminal, nominally + S.OV.
- NorJnvertcd input of the edge-sensitive differential trigger input stage. The output at Q will be
delayed by the programmed delay, after the triggering event. The programmed delay is set by the
digital input word. The TRIGGER input must be driven in conjunction with the TRIGGER input.
- Inverted input of the edge-sensitive differential trigger input stage. The output at Q will be delayed
by the programmed delay, after the triggering event. The programmed delay is set by the digital
input word. The TRIGGER input must be driven in conjunction with the TRIGGER input.
- Inverted input of the level-sensitive differential reset input ,stage. The output at Q will be reset
after a signal is received at the reset inputs. In the "minimum configuration," the minimum output
pulse width will be equal to the "reset propagation delay," tRO. The RESET input must be driven in
conjunction with the RESET input.
- Noninverted input of the level-sensitive differential reset input stage. The output at Q will be reset
after a signal is received at the reset inputs. In the "minimum configuration," the minimum output
pulse width will be equal to the "reset propagation delay," tRO. The RESET input must be
driven in conjunction with the RESET input.
- One of two complementary ECL outputs. A "triggering" event at the inputs will produce a logic
HIGH on the Q output. A "resetting" event at the inputs will produce a logic LOW on the
Q output
- One of two complementary ECL outputs. A "triggering" event at the inputs will produce a logic
LOW on the Q output. A "resettillg" event at the inputs will produce a logic HIGH on the
Q output.
- QR output is parallel to the Q output. The Q R output is typically used to drive delaying circuits
for extending output pulse widths. A "triggering" event at the inputs will produce a logic
LOW on the ~ output. A "resetting" event at the inputs will produce a logic HIGH on the
~ output.
- The collector common for the ECL output stage. The collector common may be tied to + S.OV,
but normally it is tied to the circnit ground for standard ECL outputs.
- Negative supply terminal, nominally -S.2V.
- Rs is the reference current setting terminal. An external setting resistor, RsET , connected between
Rs and - Vs determines the internal reference current. See Cs (2S00:sRsET :sSOkO).
- The ground return for the TTL and analog inputs.
- Transparent TTL latch control line. A logic HIGH on the LATCH ENABLE freezes the digital
code at the logic inputs. A logic LOW on the LATCH ENABLE allows the internal current levels to
be continuously updated through the logic inputs Do thru 0 7 •
- One of eight digital inputs used to set the programmed delay. Do (LSB) is the least significant bit of
the digital input word.
- One of eight digital inputs used to set the programmed delay.
TRIGGER
TRIGGER
DIF:~:~~~AL 1----,
INPUT
STAGE
RESET
Q
RESET
EC4tEF
INTERNAL DAC
R,
TTL LATCHES
RSET
- Vs
-v,
9-44 SPECIAL FUNCTION COMPONENTS
GROUND
On 0, O2
(lSB)
03 0 4
05 0 6
07
LATCH OFFSET
(MSBj ENABLE ADJUST
AD9500 Functional Block Diagram
LATCH
ENABLE
~
F=~-----------------i\.-.JI I
tLPW
tH
DIGITAL
1~~1~.
T~~~~~R
RESET
INPUT
n
f--toAC--J
f'
~tRHO~
~I
tPD~
ts
- DIGITAL DATA SETUP TIME
tH
-
tpo
-
to
-
tRO t TPW t RPw t THO t RHo -
tTPw ' - -
~~
---~---{ L
OOUTPUT _ _ _ _
t LPW t OAC -
n _-____
_ _
--I
1\
-i;:;r
~"-----~(
\....
{\....._tR_O_ _ _ _Ll.J!lhr.u'!/,wlll
to
NOTE
A TRIGGERING EVENT MAV OCCUR AT ANV TIME
WHILE THE INTERNAL DAC (PROGRAMMED DELA V)
IS BEING CHANGED_ TRIGGERING EVENTS DURING THE
INTERNAL DAC SETILING TIME MA V NOT GENERATE AN
ACCURATE PULSE DELAV.
DIGITALDATAHOLDTIME
LATCH ENABLE PULSE WIDTH
INTERNAL DAC SETTLING TIME
MINIMUM PROPAGAnON DELA v
RESET PROPAGATION DELAV
PROGRAMMEDDELAV
TRIGGER PULSE WIDTH
RESET PULSE WIDTH
RESET-TO-TRIGGERHOLDOFF
TRIGGER-TO-RESETHOLDOFF
System Timing Diagram
DIE LAYOUT
LATCH
/ENABlE
OFFSET
AOJUST~
/GROUND
/R'
+v'~~
~~.....c
/
I
TRIGGER
TRIGGER
R;'ET \
RESET
\\\a;
Q
Q
MECHANICAL INFORMATION
Die Dimensions
Pad Dimensions
Metalization _ _
Backing _ _ _ _
Substrate Potential
Passivation
Die Attach
Bond Wire
104 x 103 x 18 (max) mils
_ 4 x 4 (min)mils
Aluminum
None
- . - -Vs
Oxynitride
Gold Eutectic
1.25 mil, Aluminum; Ultrasonic Bonding
or Imil, Gold; Gold Ball Bonding
SPECIAL FUNCTION COMPONENTS 9-45
•
Input/Output Circuits
ECLCOMMON
+Vs
--=2l ~~a;
128
r----,
Oo-D7
AND
LATCH
ENABLE
OFFSET
ADJUST
jOUTPUTS
-Vs
+Vs
1
TRIGGER/RESET
-
--
.,
-Vs
-Vs
RSET
-Vs
Burn-In Circuit
-Vs
1kn
A,
+Vs
LArCH
ENABLE
0,
.w{
CAPACITORS ±20%
RESISTORS ± 5%
0
I
-Vs= -52V±5%
a
r
1--250'--1+-250'--1-- 250'"'-1
AD9500
A,
500
0,
a;
A,
l
10k
+20V
+08V
-l
EC~EF
A,
+Vs= +50V±S%
5{l0
,.... 2.5J.1.s
A,~
-09V
A,~
+20V
-17V
R,
1kfl
TRIGGER
RESET
-I J.t- 25p.s
RESET
-v,
9-46 SPECIAL FUNCTION COMPONENTS
+08V
INSIDE THE AD9500
The heart of the AD9500 is the linear ramp generator. A triggering
event at the input of the AD9500 initiates the ramp cycle. As
the ramp voltage falls, it will eventualy go below the threshold
set up by the internal DAC (digital-to-analog converter). A
comparator monitors both the linear ramp voltage and the DAC
threshold level. The output of the comparator serves as the
output for the AD9500, and the interval from the trigger until
the output switches is the total delay time of the AD9500.
The total delay through the AD9500 is made up of two components.
The first is the full-scale programmed delay, to (max), determined
by RSET and CEXT . The second component of the total delay is
the minimum propagation delay through the AD9500 (tpo). The
full-scale delay is variable from 2.5ns to greater than lms. The
internal DAC is capable of generating 256 separate programmed
delays within the full-scale range (this gives lOps increments for
a 2. Sns full-scale setting).
The actual programmed delay is directly related to both the
digital control data (digital data to the internal DAC) and the
RC time constant established by RSET and CEXT . The specific
relationship is as follows:
Minimum Propagation Delay +
Programmed Delay
tpo + (digital valueJ256) RSET (CEXT + lOpF)
Total Delay
Both the LATCH ENABLE control and the data inputs are
TTL compatible. The internal DAC may be updated at any
time, but full timing accuracy may not be attained unless triggering
events are held off until after the DAC settling time (tOAc).
INTERNAL
LINEAR
RAMP
TRIGGER
INPUT
aOUTPUT
RESET
INPUT
tD(MAXl - PROGRAMDELAY(FULLSCALE)
tPD
- MINIMUMPROPAGATIQNDELAY
PROGRAM DELAV
tD
-
tLRS
tHO
- LINEAR RAMP SETTLING TIME
- RESET PROPAGATION DELAY
Internal Timing Diagram
'.'
V/
/
V/ /
,,
,
On resetting, the ramp voltage held in the timing capacitor
(CEXT + lOpF) is discharged. The AD9500 discharges the bulk
of the ramp voltage very quickly, but to maintain absolute accuracy,
subsequent triggering events should be held off until after the
linear ramp setding time (tLRS). Applications which employ
high frequency triggering at a constant rate will not be affected
by the slight setding errors since they will be constant for fixed
reset-to-trigger cycles.
~ v-V " "
/
~ ;/ vV
lOOns
/'/: /
~/ V
~ /'
/
The RESET and TRIGGER inputs of the AD9S00 are differential
and must be driven relative to one another. Accordingly, the
TRIGGER and RESET inputs are ideally suited for analog or
complementary input signals. Single-ended ECL input signals
can be accommodated by using the ECL midpoint reference
(ECLREF) to drive one side of the differential inputs.
0-;// /
10ns
"~
,
'L, /
ln,
j/V
.- ,,
,,
"
100
~
/
1k
10k
RSET -
lOOk
n
Typical Programmed Delay Ranges
The internal DAC detertnines the programmed delay by way of
the threshold level at its output. The LATCH ENABLE control
for the on-board latch is active (latches) logic "HIGH". In the
logic "LOW" state, the latch is transparent, and the internal
DAC will attempt to follow changes at the digital data inputs.
The output of the AD9S00 consists of both Q and Q driver
stages, as well as the QR output which is used primarily for
extending the output pulse width. In the most direct reset configuration, either the Q or the Q output is tied to the respective
RESET input. This generates a delayed output pulse with a
duration equal to the reset delay time (tRD) of approximately
6ns. Note that the reset delay time (tRD) becomes extended for
very small programmed delay settings. The duration of the
output pulse can be extended by driving the reset inputs with
the QR output through an RC network (see "Extended Output
Pulse Width" application). Using the QR output to drive the
reset circuit avoids loading the Q or Q outputs.
SPECIAL FUNCTION COMPONENTS 9-47
9
APPLICATIONS
The AD9500 is a very versatile device, but at the same time, it
is not difficult to use. Essentially there are only a few bask
configurations which can be extended into a number of applications. The TRIGGER and RESET inputs of theAD9500 can be
treated as single ended, or as differential, which allows the
AD9500 to operate with a wide range of signal sources. The
output pulse from the AD9500 can be reset in one of two ways,
either immediately by driving the RESET inputs with the output
itself, or in a delayed mode.
+50V
1
CEXT
LATCH ENABLE
+sov
-S2V
Do TO De
Eel GROUND
AD9500
DeLAYEO
I-"---......-l--10Mil) provides excellent
rejection of supply voltage drift and ripple. For instance,
changing the power supply from SV to lOV results in only
a lj.lA maximum current change, or lOC equivalent error.
S. The ADS90 is electrically durable: it will withstand a
forward voltage up to 44V and a reverse voltage of 20V.
Hence, supply irregularities or pin reversal will not damage
the device.
The ADS90 is particularly useful in remote sensing applications. The device is insensitive to voltage drops over long lines
due to its high impedance current output. Any well·insulated
twisted pair is sufficient for operation hundreds of feet from
the receiving circuitry. The output characteristics also make
the ADS90 easy to multiplex: the current can be switched by
a CMOS multiplexer or the supply voltage can be switched by
a logic gate output.
·Covered by Patent No. 4,123,698
TEMPERA TURE TRANSDUCERS 10-7
SPECIFICATIONS
(@ +25"C and Vs=5V unless otherwise noted)
Model
AD590K
AD590J
Typ
Min
ABSOLUTE MAXIMUM RATINGS
Forward Voltage (E + toE-)
Reverse Voltage (E + to E - )
Breakdown Voltage (Case to E + or E - )
Rated Performance Temperature Rangel
Storage Temperature Rangel
Lead Temperature (Soldering, 10 sec)
+44
-20
±2oo
+150
+155
+300
-55
-65
POWER SUPPLY
Operating Voltage Range
Min
Max
+4
+30
OUTPUI
Nominal Current Output@ + 2S'C (298.2K)
Nominal Temperature Coefficient
Calibration Error@ + 2S"C
Absolute Error (over rated performance
temperature nl!lge)
Without External Calibration Adjustment
With + 2S'C Calibration Error Set to Zero
Nonlinearity
Repeatability 2
Long Term Drift'
Current Noise
Power Supply Rejection
+4V:5Vs:5 + 5V
+ 5V:5Vs:5 + 15V
+15V:5Vs :5+3OV
Case Isolation to Either Lead
Effective Shunt Capacitance
Electrical Tum·On Tinte
Reverse Bias Leakage Current'
(Reverse Voltage = 10V)
-55
-65
+4
298.2
I
PACKAGE OPTIONS
TO-52 (H-03A)
Flat Pack (F-2A)
+223"
_50°
.,.A
.,.A/K
±2.5
±10
±3.0
:1:1.5
±O.I
±O.I
±5.5
:1:2.0
:1:0.8
±O.I
±O.I
'c
"C
'c
"C
'c
·C
pAlvHZ
100
20
pF
.,.s
10
10
pA
.,.AN
.,.AN
.,.AN
0
AD590KH
AD590KF
'Leakage current doubles every lOOC.
ss.. Section 16 for package outline infOmIation.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final
electrical test. Results from those tests are used to calculate outgoiug quality
levels. All min and max specifications are guaranteed, although ouly those
shown in boldface are tested on all production units.
!
+291f +3230
+25° +50"
+373°
+100"
+423°
+150"
I
: +100"
7Cf'
+200°:
212"
+300"
TEMPERATURE SCALE CONVERSION EQUATIONS
°c =~(oF -32)
9
10-8 TEMPERATURE TRANSDUCERS
Volts
0.5
0.2
0.1
1010
100
20
32"
OF
+30
0.5
0.2
0.1
1010
rf'
0"
Volts
Volts
Volts
"C
·C
"C
40
+2730
_100"
+44
-20
±200
+150
+155
+300
±5.0
I', ,,, !,1"11 '1Ii IIIi f " I', II" ,'" 11111 I! " ,'11', t'l /1 I d
OF
Units
40
NOTES
'The ADS90 has been used at -IOOOC and + 2000C for short periods
of measurement with no physical damage to the device. However,
the absolute errors specified apply to only the rated performance
temperature range.
2Maximum deviation betweeo + 2SOC readings after temperature cycling between - SS'C and + ISOOC; guaranteed not tested.
'Conditions: constant + SV, constant + 12SOC; guaranteed,
not tested.
K
Max
298.2
I
AD590JH
AD590]F
DC
Typ
= ~ °c +32
K
=°c +273.15
Model
Min
ABSOLUTE MAXIMUM RATINGS
Forward Voltage (E+ toE-)
Reverse Voltage (E + to E -)
Breakdown Voltage (Case to E + or E -)
Rated Performance Temperature Rangel
Storage Temperature Range 1
Lead Temperature (Soldering, 10 sec)
POWER SUPPLY
Operating Voltage Range
OUTPUT
Nominal Current Output@ + 25°C (298.2K)
Nominal Temperature Coefficient
Calibration Error@ + 2S oC
Absolute Error (over rated performance
temperature range)
Without External Calibration Adjustment
With + 2S oC Calibration Error Set to Zero
Nonlinearity
Repeatability'
Long Term Drift'
Current Noise
Power Supply Rejection
+4V"Vs"+SV
+ SV"Vs" + ISV
+ ISV"Vs" + 30V
Case Isolation to Either Lead
Effective Shunt Capacitance
Electrical Turn-On Time
Reverse Bias Leakage Current'
(Reverse Voltage = IOV)
PACKAGE OPTION 5
TO-52 (H-03A)
Flat Pack (F-2A)
AD590L
Typ
Max
+44
-20
±200
+ ISO
+ ISS
+300
-55
-65
+4
+30
298.2
I
Min
AD590M
Typ
-55
-65
+4
Max
Units
+44
-20
±200
+ ISO
+ ISS
+300
Volts
Volts
Volts
°C
°C
°C
+30
Volts
298.2
I
.,.A
.,.AlK
±1.0
±0.5
°C
±3.0
±1.6
±0.4
±O.I
±O.I
±1.7
± 1.0
±0.3
±O.I
±O.I
°C
°C
°C
°C
°C
pAYHz
40
40
0.5
0.2
0.1
1010
0.5
0.2
0.1
1010
100
20
100
20
fl
pF
.,.s
10
10
pA
ADS90LH
ADS90LF
.,.AN
.,.AN
.,.AN
ADS90MH
ADS90MF
TEMPERATURE TRANSDUCERS 10-9
The 590H has 60j.l inches of gold plating on its Kovar leads and
Kovar header. A resistance welder is used to seal the nickel cap
to the header. The AD590 chip is eutectically mounted to the
header and ultrasonically bonded to with 1 MIL aluminum
wire. Kovar composition: 53% iron nominal; 29% ±1% nickel;
17% ±1 % cobalt; 0.65% manganese max; 0.20% silicon max;
0.10% aluminum max; 0.10% magnesium max; 0.10% zirconium max; 0.10% titanium max; 0.06% carbon max.
In the AD590, this PTAT voltage is converted to a PTAT current by low temperature coefficient thin film resistors. The
total current of the device is then forced to be a multiple of
this PTAT current. Referring to Figure 1, the schematic diagram of the AD590, Q8 and Q11 are the transistors that produce the PTAT voltage. R5 and R6 convert the voltage to
current. QlO, whose collector current tracks the collector
currents in Q9 and Q11, supplies all the bias and substrate
leakage current for the rest of the circuit, forcing the total
current to be PTAT. R5 and R6 are laser trimmed on the
wafer to calibrate the device at +25°C.
Figure o2 shows the typical V-I characteristic of the circuit
at +25 C and the temperature extremes.
0005~~:
(;
J~
: vz0zzzzz zzz»Li::-~~)
(013~gt)
c:==;j' ,
FLAT-PACK PACKAGE: DESIGNATION "F"
The 590F is a ceramic package with gold plating on its Kovar
leads, Kovar lid, and chip cavity. Solder of 80/20 Au/Sn composition is used for the 1. 5 mil thick solder ring under the lid.
The chip cavity has a nickel underlay between the metalization
and the gold plating. The AD590 chip is eutectically mounted
in the chip cavity at 410°C and ultrasonically bonded to with
1 mil aluminum wire. Note that the chip is in direct contact
with the ceramic base, not the metal lid.
Figure 1. Schematic Diagram
423
lOUT
(/LA)
THE AD590 IS AVAilABLE IN LASER·TRIMMEO CHIP
FORM, CONSUL TTHE CHIP CATALOG FOR DETAILS
298
218
+150°C
+25°C
_55°C
rf~
Metalization Diagram
CIRCUIT DESCRIPTION!
The AD590 uses a fundamental property of the silicon transistors from which it is made to realize its temperature proportional characteristic: if two identical transistors are operated
at a constant ratio of collector current densities, r, then the
difference in their base-emitter voltages will be (kT/q)(In r).
Since both k, Boltzman's constant and q, the charge of an
electron, are constant, the resulting voltage is directly proportional to absolute temperature (PTAT).
10-10 TEMPERATURE TRANSDUCERS
SUPPL Y VOLTAGE
Figure 2. V-I Plot
1
For a more detailed circuit description see M.P. Timko, "A Two~
TerminallC Temperature Transducer," IEEE J. Solid State Circuits,
Vol. SC-U, p. 784-788, Dec. 1976.
Understanding the AD590 Specifications
EXPLANATION OF TEMPERATURE SENSOR
SPECIFICATIONS
The way in which the ADS90 is specified makes it easy to
apply in a wide variety of different applications. It is important
to understand the meaning of the various specifications and
the effects of supply voltage and thermal environment on accuracy.
The ADS90 is basically a PTAT (proportional to absolute temperature») current regulator. That is, the output current is
equal to a scale factor times the temperature of the sensor in
degrees Kelvin. This scale factor is trimmed to l!lA/K at the
factoty, by adjusting the indicated temperature (i.e. the output
current) to agree with the actual temperature. This is done with
SV across the device at a temperature within a few degrees of
2SoC (298.2K). The device is then packaged and tested for
accuracy over temperature.
CALIBRATION ERROR
At final factory test the difference between the indicated temperature and the actual temperature is called the calibration
error. Since this is a scale factor error, its contribution to the
total error of the device is PTAT. For example, the effect of
the 1°C specified maximum error of the ADS90L varies from
0.73°C at -SSoC to 1.42°C at 150°C. Figure 3 shows how
an exaggerated calibration error would vary from the ideal
over temperature.
loUT lilA}
2982
TEMP{K\
Figure 3. Calibration Error vs. Temperature
The calibration error is a primary contribu tor to maximum
total error in all AD590 grades. However, since it is a scale
factor error, it is particularly easy to trim. Figure 4 shows the
most elementary way of accomplishing this. To trim this circuit the temperature of the ADS90 is measured by a reference
temperature sensor and R is trimmed so that VT = 1mV/K at
that temperature. Note that when this error is trimmed out at
one temperature, its effect is zero over the entire temperature
range. In most applications there is a current to voltage conversion resistor (or, as with a current input ADC, a reference)
that can be trimmed for scale factor adjustment.
ERROR VERSUS TEMPERATURE. WITH CALIBRATION
ERROR TRIMMED OUT
Each ADS90 is also tested for error over the temperature range
with the calibration error trimmed out. This specification could
also be called the "variance from PTAT" since it is the maximum difference between the actual current over temperature
and a PTAT multiplication of the actual current at 25°C. This
error consists of a slope error and some curvature, mostly at
the temperature extremes. Figure S shows a typical ADS90K
temperature curve before and after calibration error trimming.
+2"c
BEFORE
CALIBRATION
TRIM
0
::~~UTE ~--~:""---=..Jk=::::=====~....\AFTER
CALIBRATION
TRIM
-2"CL--~_5~5'~C--------------+1~5=~~C-TEMPERATURE
Figure 5. Effect of Scale Factor Trim on Accuracy
ERROR VERSUS TEMPERATURE. NO USER TRIMS
Using the ADS90 by simply measuring the current, the total
error is the "variance from PTAT" described above plus the
effect of the calibration error over temperature. For example
the AD590L maximum total error varies from 2.33°C at
-SSoC to 3.02°C at 150°C. For simplicity, only the larger figure is shown on the specification page.
NONLINEARITY
Nonlinearity as it applies to the ADS90 is the maximum deviation of current over temperature from a best-fit straight line.
•
The nonlinearity of the ADS90 over the -SSoC to +lS0°C
range is superior to all conventional electrical temperature
sensors such as thermocouples, RTD's and thermistors. Figure 6 shows the nonlinearity of the typical AD590K from
Figure S.
+16'C
-16"C
L----:.,.:::.:-c-----------------::+,=,,::.c-
5V+
Figure 6. Nonlinearity
+
VT'" lmV/K
95011
Figure 4. One Temperature Trim
1
T('C) =T(K) -273.2; Zero on the Kelvin scale is "absolute zero";
there is no lower temperature.
Figure 7A shows a circuit in which the nonlinearity is the major contributor to error over temperature. The circuit is
trimmed by adjusting Rl for a OV output with the ADS90
at O°C. R2 is then adjusted for 10V out with the sensor at
100° C. Other pairs of temperatures may be used with this procedure as long as they are measured acc~rately by a reference
sensor. Note that for +lSV output (150 C) the V+ of the op
amp must be greater than 17V. Also note that V- should be
at least -4V: if V- is ground there is no voltage applied across
the device.
TEMPERATURE TRANSDUCERS 10-11
+15V
26° C/watt. 0CA is the thermal resistance between the case and
its surroundings and is determined by the characteristics of
AD581
the thermal connection. Power source P represents the power
dissipated on the chip. The rise of the junction temperature,
TJ' above the ambient temperature TA is:
Eq. 1
v-
Figure lA. Two Temperature Trim
+2"C
Table I gives the sum of 0Jc and OCA for several common
thermal media for both the "H" and "F" packages. The heatsink used was a common ciip-()n. Using Equation 1, the temperature rise of an ADS90 "H" package in a stirred bath at +2S o C,
when driven with a SV supply, will he 006°C. However, for
the same conditions in still air the temperature rise is O.72°C.
For a given supply voltage, the temperature rise varies with
the current and is PTAT. Therefore, if an application circuit
is trimmed with the sensor in the same thermal environment
in which it will be used, the scale factor trim compensates for
this effect over the entire temperature range.
IJ U;; + OCA (oC/watt)
MEDIUM
Figure lB. Typical Two- Trim Accuracy
VOLTAGE AND THERMAL ENVIRONMENT EFFECTS
The power supply rejection specifications show the maximum
expected change in output current versus input voltage changes.
The insensitivity of the output to input voltage allows the use
of unregulated supplies. It also means that hundreds of ohms
of resistance (such as a CMOS multiplexer) can be tolerated
in series with the device.
It is important to note that using a supply voltage other than
5V does not change the PTAT nature of the AD590. In other
words, this change is equivalent to a calibration error and can
be removed by the scale factor trim (see previous page).
The AD590 specifications are guaranteed for use in a low
thermal resistance environment with 5V across the sensor.
Large changes in the thermal resistance of the sensor's environment will change the amount of self-heating and result
in changes in the output which are predictable but not necessarily desirable.
The thermal environment in which the AD590 is used determines two important characteristics: the effect of self heating
and the response of the sensor with time.
Aluminum Block
Stirred Oil!
Moving Air2
With Heat Sink
Without Heat Sink
Still Air
With Heat Sink
Without Heat Sink
{sec) (Note 3)
T
!!
E
!!
f
30
42
10
60
0.6
1.4
0.1
0.6
45
115
190
5.0
13.5
10.0
191
480
650
108
60
30
Note: T is dependent upon velocity of oil; average of several velocities
listed above.
• Air velocity'" 9ft/sec.
'The time constant is defined as the time required to reach 63.2% of
an instantaneous temperature change.
1
Table I. Thermal Resistances
The time response of the ADS90 to a step change in temperature is determined by the thermal resistances and the thermal
capacities of the chip, C(;H' and the case, C(;. C(;H is about
0.04 watt-sec/C for the AD590. C(; varies with the measured
medium since it includes anything that is in direct thermal contact with the case. In most cases, the single time constant exponential curve of Figure 9 is sufficient to describe the time
response, T(t). Table I shows the effective time constant, T,
for several media.
TFINAL
-
-
-
-
-
- ___
-.._----
SENSED
TEMPERATURE
Figure 8. Thermal Circuit Model
Figure 8 is a model of the AD590 which demonstrates these
characteristics. As an example, for the TO-52 package, 0Jc is
the thermal resistance between the chip and the case, about
T(tl '" TINITIAL +(TFINAL - TINITIALH1 -
TINITIAL
'--~------4~'------=T"'IM"'E-
Figure 9. Time Response Curve
10-12 TEMPERATURE TRANSDUCERS
e- t/T )
Applying the AD590
GENERAL APPLICATIONS
V+
10k!1
AD590L
#2
+5V
8
9
OFFSET
CALIBRATION
5M!1
AD590L
AD590
AD2040
4
GAIN SCALING
2
OFFSET SCALING
(T1 - T2)(10mVrC)
#1
50k!1
VGND
Figure 12. Differential Measurements
Figure 10. Variable Scale Display
Figure 10 demonstrates the use of a low-cost Digital Panel
Meter for the display of temperature on either the Kelvin,
Celsius or Fahrenheit scales. For Kelvin temperature Pins 9,
4 and 2 are grounded; and for Fahrenheit temperature Pins 4
and 2 are left open.
The above configuration yields a 3 digit display with 1°C or
1°F resolution, in addition to an absolute accuracy of ±2.0°C
over the -55°C to +12S oC temperature range if a one-temperature calibration is performed on an ADS90K, L, or M.
+15V
a desired temperature difference. For example, the inherent
offset between the two devices can be trimmed in. IfV+ and
V- are radically different, then the difference in internal dissipation will cause a differential internal temperature rise. This
effect can be used to measure the ambient thermal resistance
seen by the sensors in applications such as fluid level detectors or anemometry.
7.SV
+5V
AD590
52.an
B.66kU
333.3!1
(0.1%)
RESISTORS ARE 1%. 50ppml'C
Figure 13. Cold Junction Compensation Circuit for
Type J Thermocouple
Figure 11. Series & Parallel Connection
Connecting several ADS90 units in series as shown in Figure
11 allows the minimum of all the sensed temperatures to be
indicated. In contrast, using the sensors in parallel yields the
average of the sensed temperatures.
The circuit of Figure 12 demonstrates one method by which
differential temperature measurements can be made. Rl and
R z can be used to trim the output of the op amp to indicate
Figure 13 is an example of a cold junction compensation circuit
for a Type J Thermocouple using the ADS90 to monitor the
reference junction temperature. This circuit replaces an ice-bath
as the thermocouple reference for ambient temperatures
between +1S oC and +3S oC. The circuit is calibrated by adjusting RT for a proper meter reading with the measuring junction
at a known reference temperature and the circuit near +2SoC.
Using components with the T.C.'s as specified in Figure 13,
compensation accuracy will be within ±O.SO C for circuit
temperatures between +1S o C and +3S o C. Other thermocouple
types can be accommodated with different resistor values.
Note that the T.C.'s ofthe voltage reference and the resistors
are the primary contributors to error.
TEMPERATURE TRANSDUCERS 10-13
v+
4mA = 17"C
12mA = 25°C
20mA =33"C
115kfl
+5V
Skll
AD590
6981<11
+5V
12.7kll
0.01
I'F
Skll
50011
lkSl
OUTPUT HIGH - TEMPERATURE ABOVE seT POINT
10kC
OUTrUT tOW - T;;:MFERAiuRE BELV"" SET POINT
AD590
51Mn
100
6Skll
vFigure 14. 4 to 20mA Current Transmitter
Figure 16. DAC Set Point
Figure 14 is an example of a current transmitter designed to be
used with 40V, lkU systems; it uses its full current range of
4mA to 20mA for a narrow span of measured temperatures.
In this example the Ip.A/K output of the ADS90 is a~lified
to 1mA/oC and offset so that 4mA is equivalent to 17 C and
20mA is equivalent to HOC. RT is trimmed for proper reading
at an intermediate reference temperature. With a suitable
choice of resistors, any temperature range within the operating
limits of the AD590 may be chosen.
particular circuit operates from 0 (all inputs high) to +sl°C
(all inputs low) in O.2°C steps. The comparator is shown with
1° C hysteresis which is usually necessary to guard-band for
extraneous noise; omitting the s.lMU resistor results in
no hysteresis.
+
AD590
AD681
OUT
v-
+
I HEATING
I ELEMENTS
I
RH
AsET
RL
1kll (0.1%)
Figure 15. Simple Temperature Control Circuit
Figure 15 is an example of a variable temperature control circuit (thermostat) using the ADs90. RH and RL are selected to
set the high and low limits for R SET ' RSET could be a simple
pot, a calibrated multi-turn pot or a switched resistive divider.
Powering the ADS90 from the 10V reference isolates the
ADS90 from supply variations while maintaining a reasonable
voltage (-7V) across it. Capacitor C1 is often needed to filter
extraneous noise from remote sensors. RB is determined by
the fJ of the power transistor and the current requirements of
the load.
Figure 16 shows how the ADS90 can be configured with an 8bit DAC to produce a digitally controlled set point. This
10-14 TEMPERATURE TRANSDUCERS
Figure 17. AD590 Driven from CMOS Logic
The voltage compliance and the reverse blocking characteristic
of the ADS90 allows it to be powered directly from +5V CMOS
logic. This permits easy multiplexing, switching or pulsing for
minimum internal heat dissipation. In Figure 17 any ADS90
connected to a logic high will pass a signal current through the
current measuring circuitry, while those connected to a logic
zero will pass insignificant current. The outputs used to drive
the ADS90's may be employed for other purposes, but the
additional capacitance due to the ADS90 should be taken
into account.
,.
+10V
14r--<~------t---f-------~---t--------,
+
4028
I
ROW
SELECT
+
CMOS
BCD-TODECIMAL
DECODER
+
+
02
+
-
01
+
"
12
13
10
COLUMN
SELECT
II
4051 CMOS ANALOG
MULTIPLEXER
INHIBIT
10k.l1 10mVrC
Figure 18. Matrix Multiplexer
CMOS Analog Multiplexers can also be used to switch ADS90
current. Due to the ADS90's current mode, the resistance of
such switches is unimportant as long as 4 V is maintained
across the transducer. Figure 18 shows a circuit which combines
the principal demonstrated in Figure 17 with an 8 channel
CMOS Multiplexer. The resulting circuit can select one of
eighty sensors over only 18 wires with a 7 bit binary word. The
inhibit input on the multiplexer turns all sensors off for minimum dissipation while idling.
•
5k"
-5V to -15V
EN--BINARY
CHANNEL
SELECT
Figure 19. 8-Channel Multiplexer
Figure 19 demonstrates a method of multiplexing the ADS90
in the two-trim mode (Figure 7). Additional ADS90's and their
associated resistors can be added to multiplex up to 8 channels
of ±O.SoC absolute accuracy over the temperature range of
-55°C to +12S oC. The high temperature restriction of +12S oC
is due to the output range of the op amps; output to +1S0°C
can be achieved by using a +20V supply for the op amp.
TEMPERATURE TRANSDUCERS
10--15
10-16 TEMPERATURE TRANSDUCERS
11IIIIIIII
ANALOG
WDEVICES
FEATURES
High Precalibrated Accuracy: O.soC max @ 2SoC
Excellent Linearity: 0.1SoC max 10 to + 70°C)
Wide Operating Temperature Range: - 2SoC to + 10SoC
Single Supply Operation: +4V to +30V
Excellent Repeatability and Stability
High Level Output: 1p.AlK
Two Terminal Monolithic IC: Temperature Inl
Current Out
Minimal Self-Heating Errors
Low Cost, Precision IC
Temperature Transducer
AD592* I
AD592 CONNECTING DIAGRAM
PIN 2
PIN 1
o o
INC)
1+)
*PIN 2 CAN BE EITHER ATTACHED OR UNCONNECTED
BOTTOM VIEW
PRODUCT DESCRIPTION
The ADS92 is a two terminal monolithic integrated circuit temperature transducer that provides an output current proportional
to absolute temperature. For a wide range of supply voltages the
transducer acts as a high impedance temperature dependent
current source of IIJ.1\/K. Improved design and laser wafer
trimming of the IC's thin fIlm resistors allows the ADS92 to
achieve absolute accuracy levels and nonlinearity errors previously
unattainable at a comparable price.
The ADS92 can be employed in applications between - 2S"C
and + 105°C where conventional temperature sensors (i.e., thermistor, RTD, thermocouple, diode) are currently being used.
The inherent low cost of a monolithic integrated circuit in a
plastic package, combined with a low total parts count in any
given application, make the ADS92 the most cost effective temperature transducer currently available. Expensive linearization
circuitry, precision voltage references, bridge components, resistance measuring circuitry and cold junction compensation are
not required with the ADS92.
Typical application areas include; appliance temperature sensing,
automotive temperature measurement and control, HVAC (heating/ventilating/air conditioning) system monitoring, industrial
temperature control, thermocouple cold junction compensation,
board-level electronics temperature diagnostics, temperature
readout options in instrumentation, and temperature correction
circuitry for precision electronics. Particularily useful in remote
sensing applications, the ADS92 is immune to voltage drops and
voltage noise over long lines due to its high impedance current
output. ADS92s can easily be multiplexed; the signal current
can be switched by a CMOS multiplexer or the supply voltage
can be enabled with a tri-state logic gate.
The AD592 is available in three performance grades; the
ADS92AN, ADS92BNand ADS92CN. All devices are packaged
in a plastic TO-92 case rated from -45°C to + 125°C. Performance
is specified from - 25°C to + 105°C. ADS92 chips are also
available, contact the factory for details.
PRODUCT HIGHLIGHTS
1. With a single supply (4V to 30V) the ADS92 offers OSC
temperature measurement accuracy.
2. A wide operating temperature range ( - 25°C to + 105°C) and
highly linear output make the AD592 an ideal substitute for
•
older, more limited sensor technologies (i.e., thermistors,
RTDs, diodes, thermocouples).
3. The AD592 is electrically rugged; supply irregularities and
variations or reverse voltages up to 20V will not damage the
device.
4. Because the ADS92 is a temperature dependent current source,
it is immune to voltage noise pickup and IR drops in the
signal leads when used remotely.
5. The high output impedance of the ADS92 provides greater
than O.soC/V rejection of supply voltage drift and ripple.
6. Laser wafer trimming and temperature testing insures that
ADS92 units are easily interchangeable.
7. Initial system accuracy will not degrade significantly over
time. The ADS92 has proven long term performance and
repeatability advantages inherent in integrated circuit design
and construction.
·Covered by Patent No. 4,123,698.
TEMPERATURE TRANSDUCERS 10-17
SPECIFICATIONS
(typical @ 25"&, Ys=5V, unless othelWise noted)
Model
Min
ADS92AN
Typ
Max
ADS92BN
Typ
Max
Min
Min
ADS92CN
Typ
Max
Units
ACCURACY
Calibration Error@25"C'
TA = Oto +70"C
Error over Temperature
Nonlineariti
TA = -25to + 105'C
Error over Temperature3
Nonlineariti
1.5
2.5
0.7
1.0
0.3
0.5
"C
1.8
0.15
3.0
0.35
0.8
0.1
1.5
0.25
0.4
0.05
0.8
0.15
'C
"C
2.0
0.25
3.5
0.5
0.9
0.2
2.0
0.4
0.5
0.1
1.0
0.35
"C
'C
OUTPUT CHARACTERISTICS
Nominal Current Output
@25'C(298.2K)
TemperatureCoefficient
Repeatability'
Long Tenn Stability'
298.2
I
0.1
0.1
j.l.A
,
iJ-AI'C
'C
'CImonth
+ 105
+ 125
44
20
'C
"C
V
V
300
'C
30
V
0.5
0.2
0.1
'CN
'CIY
'CIY
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
Package Temperature"
Forward Voltage ( + to - )
Reverse Voltage ( - to +)
Lead Temperature
(Soldering 10 sec)
POWER SUPPLY
Operating Voltage Range
Power Supply Rejection
+4V
I...
.....
..
80
- --
60
50
0
'0
t-
iii
~
/ y
II
./
J
20
AD592
A
B
C
/
30
+y
V
V
EV
70
t-
The circuit of Figure 10 demonstrates a m!=thod in which
a voltage output can be derived in a differential temperature
measurement.
~
:Ii
2
It
because the coldest device limits the series current flowing through
the sensors. Both of these circuits are depicted in Figure 9.
D
E
F
ALUMINUM BLOCK
FLUORINERT UQUID
MOVING AIR (WITH HEAT SINK)
MOVING AIR (WITHOUT HEAT SINK)
STILL AIR (WITH HEAT SINK)
STILL AIR (WITHOUT HEAT SINK)
-- -
AD592
o
20
V
*-
Figure 10. Differential Measurements
40
60
80
100 120 140 160 180 200 220 240 260 280 300
TIME- sec
The time constant, 'T, is dependent on IlJA and the thermal
capacities of the chip and the package. Table I lists the effective
'T (time to reach 63.2% of the final value) for several different
media. Copper printed circuit board connections where neglected
in the analysis, however, they will sink or conduct heat directly
through the ADS92's solder dipped Kovar leads. When faster
response is required a thermally conductive grease or glue between
the ADS92 and the surface temperature being measured should
be used. In free air applications a clip-on heat sink will decrease
output stabilization time by 10-20%.
MOUNTING CONSIDERATIONS
If the ADS92 is thermally attached and properly protected, it
can be used in any temperature measuring situation where the
maximum range of temperatures encountered is between - 2SOC
and + IOS·C. Because plastic IC packaging technology is employed,
excessive mechanical stress must be safeguarded against when
fastening the device with a clamp or screw-on heat tab. Thermally
conductive epoxy or glue is recommended under typical mounting
conditions. In wet or corrosive environments any electrically
isolated metal or ceramic well can be used to shield the ADS92.
Condensation at cold temperatures can cause leakage current
related errors and should be avoided by sealing the device in
nonconductive epoxy paint or dips.
APPLICATIONS
Connecting several ADS92 devices in parallel adds the currents
through them and produces a reading proportional to the average
temperature. Series ADS92s will indicate the lowest temperature
+5V
+15V
+
~
VOUT=
IT1-T2))(
110mVrci
- -
Figure 8. Thermal Response Curves
+
+
5M0
I
-y
U
,0
.,
..kG
AD592
h
hAD 592
AD592
AD592
33330
(0'%1
VT.....,(1 mVIK)
~7
Figure 9. Average and Minimum Temperature
Connections
10-22 TEMPERA TURE TRANSDUCERS
Rl can be used to trim out the inherent offset between the two
devices. By increasing the gain resistor (lOkO) temperature
measurements can be made with higher resolution. If the magnitude of V + and V - is not the same, the difference in power
consumption between the two devices can cause a differential
self-heating error.
Cold junction compensation (Clc) used in thermocouple signal
conditioning can be implemented using an ADS92 in the circuit
configuration of Figure 11. Expensive simulated ice baths or
hard to trim, inaccurate bridge circuits are no longer required.
+75Y,
THERMOCOUPLE APPROX
TYPE
RVALUE
!IZO
410
410
8m
AD,403
MEASURING
r-- - - -- - I
80
on
10kn
AD OP-07E
JUN~ONr-~~~-r~~~__~I~"~0-r__4-____~
I
I
I
JUNCTION
___ ...II
AD592
REFERENCE
I
L
c.
___
,ookD
...
I1kfl}
Figure 11. Thermocouple Cold Junction Compensation
The circuit shown can be optimized for any ambient temperature
range or thermocouple type by simply selecting the correct
value for the scaling resistor - R. The ADS92 output (ljLJ\lK)
times R should approximate the line best fit to the thermocouple
curve (slope in VfC) over the most likely ambient temperature
range. Additionally, the output sensitivity can be chosen by
selecting the resistors ~l and ~2 for the desired noninverting
gain. The offset adjustment shown simply references the ADS92
to ·C. Note that the TC's of the reference and the resistors are
the primary contributors to error. Temperature rejection of 40
to 1 can be easily achieved using the above technique.
Although the AD592 offers a noise immune current output, it is
not compatible with process control/industrial automation current
loop standards. Figure 12 is an example of a temperature to 420mA transmitter for use with 4OV, lkO systems.
In this circuit the 1jLJ\IK output of the ADS92 is amplified to
lmArC and offset so that 4mA is equivalent to 170C and 20mA
is equivalent to 33·C. Rt is trimmed for proper reading at an
+15V
r---------------~------~~+~
AD581
RPULLUP
""-
+
627kO
AD592
COMPARATOR
I TEMPSETPOINT
I HEATER
I
I
I
I
I
I •
Lt__~~~__
20MU
I
I
(OPTIONAL)
FOR HYSTERESIS
.... I
~~_~~
Figure 10. Using the Alarm to Drive a TTL Gate
("Grounded" Emitter Configuration)
L- -
(CHROMEU:
TEMPERATURE
_ _~_ _~~_--1 '
T3
------
CONSTANTAN
c,
- - - --,,
I
I
I
I
I
l ____..!."!'!.____.-!..Jc'
I
I
L _______________
II
J
Figure 16. Connecting Isothermal Junctions
Since the compensation is at the reference junction temperature,
it is often convenient to form the reference "junction" by connecting directly to the circuit wiring. So long as these connections
and the compensation are at the same temperature no error will
result.
11-12 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
Thermocouple Conditioners and
Set-Point Controllers
A0596* /A0597* I
~ANALOG
WDEVICES
FEATURES
Low Cost
Operates with Type J (ADS96) or Type K (AD597)
Thermocouples
Built-In Ice Point Compensation
Temperature Proportional Operation - 10mVrc
Temperature Sat-Point Operation - ONIOFF
Programmable Switching Hysteresis
High Impedance Differential Input
AD596/AD597 FUNCTIONAL BLOCK DIAGRAM
-AUII
v-
PRODUCT DESCRIPTION
The AD596fAD597 is a monolithic temperature set-point controller which has been optimized for use at elevated temperatures
such as those found in oven control applications. The device
cold junction compensates and amplifies a type J or K thermocouple input to derive an internal signal proportional to
temperature. The internal signal is then compared with an externally applied set-point voltage to yield a low impedance switched
output voltage. Dead-Band or switching hysteresis can be programmed using a single enemal resistor. Alternately, the ADS961
ADS97 can be configured to provide a voltage output (lOmVI"C)
directly from a type J or K thermocouple signal. It can also be
used as a stand-alone voltage output temperature sensor.
The ADS96fADS97 can be powered with a single supply from
+ SV to + 30V, or dual supplies up to a total span of 36V.
Typical quiescent supply current is 160II-A which minimizes
self-heating errors.
The ADS96fADS97 includes a thermocouple failure alarm that
indicates an open thermocouple lead when operated in the temperature proportional measurement mode. The alarm output has
a flexible format which can be used to drive relays, LEOs or
TTL logic.
The ADS961ADS97 has a calibration accuracy of ±4°C at an
ambient temperature of 600C and an ambient temperature stability
specification of
from + 25°C to + lOOOC. If higher
accuracy, or a lower ambient operating temperature is required,
either the ADS94 (J thermocouple) or ADS9S (K thermocouple)
should be considered.
O.Osocrc
PRODUCT HIGHLIGHTS
I. The ADS96fADS97 provides cold junction compensation
and a high gain amplifier which can be used as a set-point
comparator.
2. The input stage of the ADS96fADS97 is a high quality instrumentation amplifier that allows the thermocouple to float
over most of the supply voltage range.
3. Linearization not required for thermocouple temperatures
close to 175°C (+ 100°C to + S400C for ADS96).
4. Cold junction compensation is optimized for ambient temperatures ranging from + 25°C to + lOOOC.
S. In the stand-alone mode, the ADS96/ADS97 produces an
output voltage that indicates its own temperature.
The device is packaged in a reliability qualified, cost effective
lO-pin metal can and is trimmed to operate over an ambient
temperature range from + 25°C to + lOOOC. Operation over an
extended ambient temperature range is possible with slightly
reduced accuracy. The ADS96 will amplify thermocouple signals
covering the entire - 200°C to + 7600C temperature range
recommended for type J thermocouples while the ADS97 can
accommodate - 2000C to + 12S0°C type K inputs.
*Protected by u.s. Patent No. 4,029,974.
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 77-73
SPECIFICATIONS
= lDV, Tp J (AD596), Tp K(AD597) Thennocoup/e, unless otherwise notad)
(@ +Iitrc and Vs
Model
ADS97AH
ADS96AH
UailS
ABSOLUTE MAXIMUM RATINGS
+Vsto -Vs
Common-Mode Input Voltqe
Differential Input VoItqe
A1ann VollBJeS
+ALM
-ALM
Operating Temperature Range
Output Shon Circuit to Common
TEMPERATURE MEASUREMENT
(Specifled Temperature Range
+ 25'C to + 100'(;)
Calibration Error l
Stabilityvs. Temperature2
Gain Error
36
+Vs
+Vs
(-Vs -0.15)
-Vs
-Vs
-Vs
-55
Indeflrute
-4
±0.02
-1.5
Nominal Transfer Function
36
(-Vs -0.15)
-Vs
+Vs
+Vs
(-Vs+36)
+Vs
+ 125
-Vs
-Vs
-55
Indefmite
(-Vs+36)
+Vs
+125
+4
±0.05
+1.5
-4
±0.02
-1.5
+4
±0.05
+1.5
10
10
Volts
Volts
Volts
Volts
Volts
'C
'C
'C/'C
%
mVI'C
AMPLIFIER CHARACTERISTICS
Closed LoopGain'
Input Offset Voltage
Input BIas Current
Differential Input Range
Common-Mode Range
Common-ModeSensiuvlIy-RTO
Power Supply Sensttivity - RTO
Output Voltage Range
DualSupp1ies
Single Supply
Usable Output Current4
3dB Bandwidth
ALARM CHARACTERISTICS
VCB(SAT)at 2mA
Leakage Current
Operating Voltqe at - ALM
Short Circuit Current
180.6
'C x 53.21 + 235
0.1
-10
(-Vs-0.15)
+50
(+Vs -4)
10
10
(-Vs +l.5)
(+Vs -2)
(+Vs -2)
o
VN
245.5
'Cx41.27-37
0.1
-10
!LV
+50
(+Vs-4)
10
10
(-Vs-O.IS)
(+Vs -2)
(+Vs -2)
(-Vs +2.5)
o
±5
±5
±I
!LA
(+Vs -4)
(+Vs -4)
Volts
mA
20
20
Volts
Quiescent Current
300
300
200
+Vs
-Vs
transfer function nurumizes the error over the amblCllt temperature range
200
AD597AH
AD596AH
NOTES
IThlS IS a measure of the deviallOn from Ideal with a measunng
thermocouple junChoD of 17S"C and a chip temperacure of 6O"C. The
Ideal transfer functIOn 15 given by:
AD596. VOVT = l80.57x(VM-V.+ (amb,entm 'C) x 53.21!LVI'C
+ 235!LV)
AD597. VOVT = 245.46 x (VM-VA+ (amb...tm'C)x41.27,LVI'C
-37!LV).
Where VM and VA. represent the measunng and ambient temperatures and
are taken from the appropnate J or K thermocouple table. The Ideal
of 2S"C to lOO"C WIth a thermocouple temperature of
approximately l75'C.
Volts
Volts
mA
±I
POWER REQUIREMENTS
Operating'
PACKAGEOPTION6
TO-IOO(H-IOA)
mVN
mVN
Volts
0.3
0.3
Volts
kHz
15
IS
!LA
mV
'Dermed as the slope of the line connecllll8 the AD596IAD597 qc enors
measured at 250C and lOO"C ambient temperature.
JPm 6 shorted to Pm 7.
'current Sink Capability 10 smgle supply conf.aguratlOD IS llIDlted to current
drawn to ground through a SOkn resistor at outpUt voltages below 2.SV.
5_VS must Dot exceed -J6.SV.
6See Section 16 for packqe outhne mformatin.
Specifications subiea to change Without DObee.
SpecificanOftS shown 10 boldface are tested on all prodUCbon umts at fmal
electrical test. Results from those tests are used to calculate outgOlDg QuallEY
levels. All DUn and max speafications are guaranteed, although only those
shown in boldface are tested on all production UDib.
11-14 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
Type)
AD596
TypeK
AD597
Voltage
mV
Output
Output
mV
Voltage
mV
500
520
540
560
580
27.388
28.511
29.642
30.782
31.933
5000
5203
5407
5613
5821
20.640
21.493
22.346
23.198
24.050
5066
5276
5485
5694
5903
- 872
- 717
- 551
- 375
- 191
600
620
640
660
680
33.096
34.273
35.464
36.671
37.893
6031
6243
6458
6676
6897
24.902
25.751
26.599
27.445
28.288
6112
6321
6529
6737
6944
-
96
0
97
196
245
700
720
740
750
760
39.130
40.382
41.647
42.283
7120
7346
7575
7689
-
-
29.128
29.965
30.799
31.214
31.629
7150
7355
7560
7662
7764
780
800
820
-
32.455
33.277
34.095
34.909
35.718
7966
8168
8369
8569
8767
36.524
37.325
38.122
38.915
39.703
8965
9162
9357
9552
9745
40.488
41.269
42.045
42.817
43.585
9938
10130
10320
10510
10698
44.439
45.108
45.863
46.612
47.356
10908
11072
11258
11441
11624
48.095
48.828
49.555
50.276
50.633
11805
11985
12164
12341
12428
Type)
AD596
TypeK
AD597
Voltage
mV
Output
Output
Thermocouple
Tem.perature
mV
Voltage
mV
mV
'C
-
7.890
7.402
6.821
6.159
5.426
-1370
-1282
-1177
-1058
- 925
-
5.891
5.550
5.141
4.669
4.138
-1446
-1362
-1262
-1146
-1016
100
80
60
.- 40
- 20
- 4.632
- 3.785
- 2.892
- 1.960
- .995
- 782
- 629
- 468
- 299
- 125
- 3.553
- 2.920
- 2.243
- 1.527
.777
-
-
-
-
-
Thermocouple
Temperature
'C
-
200
180
160
140
120
-
-
-
10
0
10
20
25
.501
0
.507
1.019
1.277
36
54
146
238
285
.392
0
.397
.798
1.000
30
40
50
60
80
1.536
2.058
2.585
3.115
4.186
332
426
521
617
810
1.203
1.611
2.022
2.436
3.266
295
395
496
598
802
840
-
860
-
-
100
120
140
160
180
5.268
6.359
7.457
8.560
9.667
1006
1203
1401
1600
1800
4.095
4.919
5.733
6.539
7.338
1005
1207
1407
1605
1801
880
900
920
940
960
-
-
-
-
-
-
200
220
240
260
280
10.777
11.887
12.998
14.108
15.217
2000
2201
2401
2602
2802
8.137
8.938
9.745
10.560
11.381
1997
2194
2392
2592
2794
980
1000
1020
1040
1060
300
320
340
360
380
16.325
17.432
18.537
19.640
20.743
3002
3202
3402
3601
3800
12.207
13.039
13.874
14.712
15.552
2996
3201
3406
3611
3817
1080
1100
1120
1140
1160
400
420
21.846
22.949
24.054
25.161
26.272
3999
4198
4398
4598
4798
16.395
17.241
18.088
18.938
19.788
4024
4232
1180
1200
1220
1240
1250
440
460
480
4440
4649
4857
-
-
-
-
-
-
-
-
-
-
-
-
-
Table I. Output Voltage vs. Thermocouple Temperature (Ambient +60°C, Vs
TEMPERATURE PROPORTIONAL OUTPUT MODE
The AD596JAD597 can be used to generate a temperature proportional output of lOmV;oe when operated with J and K type
thermocouples as shown in Figure I. Thermocouples produce
low level output voltages which are a function of both the temperature being measured and the reference or cold junction
temperature. The AD596JAD597 compensates for the cold junction temperature and amplifies the thermocouple signal to produce
a high level 10mV;oe voltage output which is a function only of
the temperature being measured. The temperature stability of
the part indicates the sensitivity of the output voltage to changes
in ambient or device temperatures. This is typically 0.02°e;oe
over the + 25°e to + loooe recommended ambient temperature
range. The parts will operate over the extended ambient temperature ranges from - 55°e to + 125°e, but thermocouple
nonlinearity at the reference junction will degrade the temperature
stability over this extended range. Table I is a list of ideal AD596J
AD597 output voltages as a function of Celsius temperature for
type J and K ANSI standard thermocouples with package and
reference junction at 60oe. As is normally the case, these outputs
-
-5V,
mV
+ 15V)
CONSTANTAN
IALUMELI
-', IRON
(CHROMEL)
+15
100k
100k
Figure 1. Temperature Proportional Output Connection
are subject to calibration and temperature sensitivity errors.
These tables are derived using the ideal transfer functions:
AD596 output = (Type J voltage +301.5!,-V)
AD597 output = (Type K voltage) x 245.46
X
180.57
The offsets and gains of these devices have been laser trimmed
to closely approximate thermocouple characteristics over measurement temperature ranges centered around 175°e with the
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-15
•
AD596/AD597 at an ambient temperature between 25°C and
100°C. This eliminates the need for additional gain or offset
adjustments to make the output voltage read:
Your = lOmVrc x (thermocouple temperature in DC)
(within specified tolerances).
r~~:~fi!il
I
:
I
I
I
L_
REGION
I CONSTANtAN
11ALUMEl)
,-~IR~ON~__~~~
I (CHROMEL)
ti
I
_.J
v
."
Excluding calibration errors, the above transfer function is accurate
to within loe from + 800e to + 550°C for the AD596 and - 200e
to + 3500e for the AD597. The different temperature ranges are
due to the differences in J and K type thermocouple curves.
POINT
VOLTAGE
European DIN FE-CuNi thermocouple vary slightly from ANSI
type J thermocouples. Table I does not apply when these types
of thermocouples are used. The transfer functions given previously
and a thermocouple table should be used instead.
Fig'J.~
. 1 also shows an optional t,.-!ur..ming network which can be
used to change the device's offset voltage. Injecting or sinking
200nA from Pin 3 will offset the output aproximately IOmV
(l"C).
The AD596/AD597 can operate from a single supply from SV to
36V or from split supplies totalling 36V or less as shown. Since
the output can only swing to within 2V of the positive supply,
the usable measurement temperature range will be restricted
when positive supplies less than 15V for the ADS97 and lOY for
the ADS96 are used. If the AD5961AD597 is to be used to
indicate negative Celsius temperatures, then a negative supply is
required.
Common-mode voltages on the thermocouple inputs must remain
within the common-mode voltage range of the ADS96/ADS97,
with a return path provided for the bias currents. If the thermocouple is not remotely grounded, then the dotted line connection
shown in Figure I must be made to one of the thermocouple
inputs. If there is no return path for the bias currents, the input
stage will saturate, causing erroneous output voltages.
In this configuration, the ADS96/ADS97 has circuitry which
detects the presence of an open thermocouple. If the thermocouple
loop becomes open, one or both of the inputs to the device will
be deprived of bias cUrrent causing the output to saturate. It is
this saturation whicli is detected intema1ly and used to activate
the alarm circuitry. The output of this feature has a flexible
format which can be used to source or sink up to 20mA of
current. The collector ( + ALM) should not be allowed to become
more positive than ( - Vs + 36V), however, it may be permitted
to be more positive than + Vs. The emitter voltage ( - ALM)
should be constrained such that it does not become more positive
than 4V below + Vs. If the alarm feature is not used, this pin
. should be connected to Pins 4 or 5 as shown in Figure I.
SET-POINT CONTROL MODE
The AD596/AD597 can be connected as a set-point controller as
shown in Figure 2. The thermocouple voltage is cold junction
comPensated, amplified, and compared to an external set-point
voltage. The relationship between set-point voltage and temperature is given in Table I. If the temperature to be controlled is
within the operating range ( - S5°C to + 12S0C) of the device, it
can monitor its own temperature by shorting the inputs to ground.
The set-point voltage with the thermocouple inputs grounded is
given by the expressions:
ADS96 Set-Point Voltage = °c x 9.6mVrC +42mV
ADS97 Set-Point Voltage = °C x lO.lmVrC -9.1mV
The input impedance of the set-point pin of the AD596/ADS97
is approximately SOkO. The temperature coefficient of this
resistance is ± 15ppmfOC. Therefore, the lOOppmfOC SkO pot
5k
100ppmrc
SET-
Figure 2. Set-Point Control Mode
shown in Figure 2 will only introduce an additional ± 1°C degradation of temperature stability over the + 2SoC to + 100°C
ambient temperature range.
Switching hysteresis is often used in set-point systems of this
type to provide noise immunity and increase system reliability.
By reducing the frequency of on-off cycling, mechanical component wear is reduced leading to enhanced system reliability.
This can easily be implemented with a single external resistor
between Pins 7 and 3 of the ADS96/ADS97. Each 200nA of
current injected into Pin 3 when the output switches will cause
. t hat IS:
. R HYST (0) = V
OUT
1 •
about 1°C 0 f hysteresls;
200nA
x 0C HYST
In the set-point configuration, the ADS96/ADS97 output is
saturated at all times, so the alarm transistor will be ON regardless
of whether there is an open circuit or not. However, - ALM
must be tied to a voltage below ( + Vs - 4V) for proper operation
of the rest of the circuit.
STAND-ALONE TEMPERATURE TRANSDUCER
The ADS96/ADS97 may be configured as a stand-alone Celsius
thermometer as shown in Figure 3.
J •.•,.'
-v,
Figure 3. Stand-Alone Temperature Transducer
Temperature Proportional Output Connection
Simply omit the thermocouple and connect the inputs (Pins 1
and 2) to common. The output will now reflect the compensation
voltage and hence will indicate the AD596/AD597 temperature.
In this three terminal, voltage output, temperature sensing
mode, the AD596/AD597 will operate over the full extended
-SSoC to+ 12SoC temperature range. The output scaling will be
9.6mV per °c with the ADS96 and IO.lmV per oe with the
AD597. Additionally there will be a 42mV offset with the AD596
causing it to read slightly high when used in this mode.
11-16 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
THERMOCOUPLE CONNECTIONS
The connection of the thermocouple wire and the normal wire
or printed circuit board traces going to the AD596/AD597 forms
an effective reference junction as shown in Figure 4. This junction
must be kept at the same temperature as the AD596/AD597 for
the internal cold junction compensation to work properly. Unless
the AD5961AD597 is in a thermally stable enclosure, the thermocouple leads should be brought in directly to Pins I and 2.
REFERENCE JUNCTION
+zO"C
----------------
+17S"C
~:::~~~~~~~~"I~~~~~~~~~~
I
10 1
CONSTANTAN
IALUMEL,
@;
®
t1'\
''-iC~i;ELi ~E
A BIASPINS
RETURN
PATH
FROM
1 AND
2
OF LESS THAN 11tH
IMPEDANCE MUST BE
PROVIDED
~~'!!N..G.RESlSTOTOR
"v.::t
I O)L ___ .J\!!....) LED
S+Vs
I'
..!-------z
t ; \:J
7
~ "!I
r....
-
@
~ o.!~F ~
....
-175""
-2O"C
25"C
I
\~fi\
\!I
GND
Ii
o.
~
I
,
I
·~OO'.f
®
'0
I
-
~~
/ _ _ _ _ _ _--J'> v"",
"",,/
1
-Va
Figure 4. PCB Connections
To ensure secure bonding, the thermocouple wire should be
cleaned to remove oxidization prior to soldering. Noncorrosive
resin flux is effective with iron, constantan, chromel, and alumel,
and the following solders: 95% tin-5% silver, or 90% tin-IOOIo
lead.
SINGLE AND DUAL SUPPLY CONNECTIONS
In the single supply configuration as used in the set-point controller
of Figure 2, any convenient voltage from + 5V to + 36V may be
used, with self-heating errors being minimized at lower supply
levels. In this configuration, the - Vs connection at Pin 5 is tied
to ground. Temperatures below zero can be accommodated in
the single supply set-point mode, but not in the single supply
temperature measuring mode (Figure I reconnected for single
supply). Temperatures below zero can only be indicated by a
negative output voltage, which is impossible in the single supply
mode.
Common-mode voltages on the thermocouple inputs must remain
below the positive supply, and not more than 0.15V more negative
than the minus supply. In addition, a return path for the input
bias currents must be provided. If the thermocouple is not
remotely grounded, then the dotted line connections in Figures
I and 2 are mandatory.
STABILITY OVER TEMPERATURE
The AD5961AD597 is specified for a maximum error of ±4"C
at an ambient temperature of 6O"C and a measuring junction
temperature at 175"C. The ambient temperature stability is
specified to be a maximum of 0.05"C/"C. In other words, for
every degree change in the ambient temperature, the output will
change no more than 0.05 degrees. So, at 2S"C the maximum
deviation from the temperature-voltage characteristic of Table I
is ±5.7S·C, and at lOO"C it is ±6"C maximum (see Figure 5).
If the offset error of ± 4"C is removed with a single offset adjustment, these errors will be be reduced to ± 1. 7S·C and ± 2"C
max. The optional trim circuit shown in Figure I demonstrates
how the ambient offset error can be adjusted to zero.
I
I
I
I
I
-------,---------1
HOC
1000c
Figure 5. Drift Error vs. Temperature
THERMAL ENVIRONMENTAL EFFECTS
The inherent low power dissipation of the AD5961AD597 keeps
self-heating errors to a minimum. However, device output is
capable of delivering ± SmA to an extemalload and the alarm
circuitry can supply up to 20mA. Since the typical junction to
ambient thermal resistance in free air is 1500CIW, significant
temperature difference between the package pins (where the
reference junction is located) and the chip (where the cold junction
temperature is measured and then compensated) can exist when
the device is operated in a high dissipation mode. These temperature differences will result in a direct error at the output. In
the temperature proportional mode, the alarm feature will only
activate in the event of an open thermocouple or system transient
which causes the device output to saturate. Self-Heating errors
will not effect the operation of the alarm but two cases do need
to be considered. First, after a fault is corrected and the alarm
is reset, the AD5961AD597 must be allowed to cool before readings
can again be accurate. This can take 5 minutes or more depending
upon the thermal environment seen by the device. Second, the
junction temperature of the part should not be allowed to exceed
150"C. If the alarm circuit of the AD5961AD597 is made to
source or sink 20mA with 30V across it, the junction temperature
will be 9O"C above ambient causing the die temperature to exceed
15O"C when ambient is above 6O"C. In this case, either the load
must be reduced, or a heat sink used to lower the thermal
resistance.
TEMPERATURE READOUT AND CONTROL
Figure 6 shows a complete temperature indication and control
system based on the AD5961AD597. Here the AD5961AD597 is
being used as a closed-loop thermocouple signal conditioner and
an external op-amp is used to implement set point. This has two
important advantages. It provides a high level (lOmVI"C) output
for the AID panel meter and also preserves the alarm function
for open thermocouples.
The AID panel meter can easily be offset and scaled as shown to
read directly in degrees Fahrenheit. If a two temperature calibration scheme is used, the dominant residual errors will arise
from two sources; the ambient temperature rejection (typically
± 2"C over a 25"C to lOO"C range) and thermocouple nonlinearity
typical + I"C from 8O"C to SSO"C for type J and + I"C from
- 20"C to 35O"C for type K.
An external voltage reference is used both to increase the stability
of the AID converter and supply a stable reference for the set-point
voltage.
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-17
•
A traditional requirement for the design of set-point control
thermocouple systems has been to configure the system such
that the appropriate action is taken in the event of an open
thermocouple. The open, thermocouple alarm pin with its flexible
current-limited output format supixJns this function when the
part operates in the temperature proportional mode. In addition,
if the thermocouple is not remotely grounded, it is possible to
program the device for either a positive or negative full scale
output in the event of an open thermocouple. This is done by
connecting the bias return resistor directly to Pin 1 if a high
output voltage is desired to indicate a fault condition. Alternately,
if the bias return is provided on the thermocouple lead connected
to Pin 2, an open circuit will result in an output low reading.
Figure 6 shows the ground return connected to Pin 1 so that if
the thermocouple fails, the heater will remain off. At the same
time, the alarm circuit lights the LED signalling the need to
service the thermocouple. Grounding Pin 2 would lead to low
output voltage saturation, and in this circuit would result in a
potentially dangerous thermal runaway under fault conditions.
~-;I;;P-;';-~~
:
I CONSTANTAN
I
I
IIALUMELI
IRON
"
I
I
I
I
I
L_
ICL7136
IICHROMELI
HEATER
J
I
I
I
I
IN HI
10k
fi
IN LO
IH~--""-+~-'V'>IV-""-1 REF
HI
REF LO
1k
10kH
%:'8~~T ~o-IIIlI'v-e-I
r
I
5kfi
L
10Mfi
Figure 6. Temperature Measurement and Control
11-18 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
120V Be
Loop-Powered 4-20mA
Sensor Transmitter
AD693 I
11IIIIIIII ANALOG
WDEVICES
FEATURES
Instrumentation Amplifier Front End
Loop-Powered Operation
Precalibrated 30mV or 60mV Input Spans
Independently Adjustable Output Span and Zero
Precalibrated Output Spans: 4-20mA Unipolar
0-20mA Unipolar
12±8mA Bipolar
Precalibrated 1000 RTD Interface
S.2V Reference with Up to 3.5mA of Current Available
Uncommitted Auxiliary Amp for Extra Flexibility
Optional External Pass Transistor to Reduce
Self-Heating Errors
PRODUCT DESCRIPTION
The AD693 is a monolithic signal conditioning circuit which
accepts low-level inputs from a variety of transducers to control
a standard 4-20mA, two-wire current loop. An on-chip voltage
reference and auxiliary amplifier are provided for transducer
excitation; up to 3.5mA of excitation current is available when
the device is operated in the loop-powered mode. Alternatively,
the device may be locally powered for three-wire applications
when 0-20mA operation is desired.
Preca1ibrated 30mV and 60mV input spans may be set by simple
pin strapping. Other spans from ImV to l00mV may be realized
with the addition of external resistors. The auxiliary amplifier
may be used in combination with on-chip voltageS to provide six
precalibrated ranges for won RTDs. Output span and zero are
also determined by pin strapping to obtain the standard ranges:
4-20mA, 12 ± SmA and 0-20mA.
Active laser trimming of the AD693's thin-film resistors result
in high levels of accuracy without the need for additional adjustments and calibration. Total unadjusted error is tested on every
device to be less than 0.5% of full scale at + 25"C, and less than
0.75% over the industrial temperature range. Residual nonlinearity
is under 0.05%. The AD693 also allows for the use of an external
pass transistor to further reduce errors caused by self-heating.
For transmission of low-level signals from RTDs, bridges and
pressure transducers, the AD693 offers a cost-effective signal
conditioning solution. It is recommended as a replacement for
discrete designs in a variety of applications in process control,
factory automation and system monitoring.
AD693 PIN CONFIGURATION
PRODUCT HIGHLIGHTS
1. The AD693 is a complete monolithic low-level voltage-tocurrent loop signal conditioner.
2. Precalibrated output zero and span options include 4-20mA,
0-20mA, and 12 ± SmA in two- and three-wire configurations.
3. Simple resistor programming adds a continuum of ranges to
the basic 30mV and 60mV input spans.
4. The common-mode range of the signal amplifier input extends
from ground to near the device's operating voltage.
5. Provision for transducer excitation includes a 6.2V reference
output and an auxiliary amplifier which may be configured
•
for voltage or current output and signal amplification.
6. The circuit configuration permits simple linearization of
bridge, RTD, and other transducer signals.
7. A monitored output is provided to drive an external pass
transistor. This feature off-loads power dissipation to extend
the temperature range of operation, enhance reliability, and
minimize self-heating errors.
S. Laser-wafer trimming results in low unadjusted errors and
affords precalibrated input and output spans.
9. Zero and span are independently adjustable and noninteractive
to accommodate transducers or user defined ranges.
10. Six precalibrated temperature ranges are available with a
won RTD via pin strapping.
The AD693 is packaged in an 20-pin ceramic side-brazed DIP
and is specified over the - 4O"C to + S5°C industrial temperature
range.
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-19
s =+24v,lnputSpan=30mvorBDmv,DutputSpan = 4-2DmA,
SPECIFICATIONS (@+25"CandV
Rt. = 2500, VCM = 3.1V, with external pass transistor unless othlllWise specified}
Model
Conditions
Min
Max
Units
±0.2S
±0.4
±O.S
±0.7S
% Full Scale
% Full Scale
±O.S
±2.0
°C
±2S
±40
+35
±O.S
±3.0
±80
±120
+100
± I.~
±S.6
fLA
fLA
fLA
,_tA/oC
fL VN
±1O
+5
+7
+Vop-4V6
±30
+20
+2S
V
fL VN
nA
nA
VS1G=0
±O.S
±3.0
nA
30mV Input Span
60mV Input Span
0.5333
0.2666
±O.OS
±0.2
%
±0.03
±O.OS
±20
±0.01
±om
±0.04
±0.06
±SO
±O.OS
±0.07
%N
%N
ppml°C
% of Span
% of Span
+500
+36
+700
V
fLA
+25
+32
rnA
±40
± 1.0
±3.0
±200
±2.5
±S.6
fLV
fLVrC
fL VN
±30
± 1.0
±80
±3.0
fLA
fLAN
0.2666
±O.OS
±0.2
AN
%
LOOP rQWIUWJH>PERATION
TOTALUNADJUSTEDERROR I ,2
TmintoTmax
1000RTDCALIBRATIONERROR3 (See Fig. 17)
LOOP POWERED OPERATION 2
Zero Current Error4
vs. Temp.
Power Supply Rejection (RTI)
Common-Mode Input Range
Common-Mode Rejection (RTI)
Input Bias Currene
Tminto Tmax
Input Offset Currenr1
Transconductance
Nominal
Unadjusted Error
vs. Common-Mode
Errorvs. Temp.
Nonlinearity8
AD693AD
Typ
Zero = 4mA
Zero = 12mA
.Zero = OmA 5
Zero = 4mA
12V sVops36V6
OVsVcM s6.2V
(See Fig. 3)
OVsVcM s6.2V
+7
0
OVsVcM s6.2V
30mV InputSpan
60mV InputSpan
30mV InputSpan
60mV Input Span
OPERATIONAL VOLTAGE RANGE
Operational Voltage, VOp6
Quiescent Current
Into Pin 9
+12
OUTPUT CURRENT LIMIT
+21
AN
AN
COMPONENTS OF ERROR
SIGNAL AMPLIFIER9
Input Voltage Offset
vs. Temp
Power Supply Rejection
VII CONVERTER9 ,10
Zero Current Error
Power Supply Rejection
Transconductance
Nominal
Unadjusted Error
6.200V REFERENCE9 ,12
Output Voltage Tolerance
vs. Temp.
Line Regulation
Load Regulation II
Output Current 13
AUXILIARY AMPLIFIER
Common·Mode Range
Input Offset Voltage
Input Bias Current
Input Offset Current
Common·Mode Rejection
Power Supply Rejection
12VsVops36V6
OVsVCM s6.2V
Output Span = 4-20rnA
12VsVops36y6
12VsVops36V6
OmAsIREP s3rnA
LoopPowered,(Fig.IO)
3-Wire Mode, (Fig. 15)
+3.0
±3
±20
±200
±0.3
+3.5
+5.0
0
11-20 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
±SO
+5
+0.5
90
105
±12
±SO
±300
±0.7S
mV
ppml°C
fL VN
mV/rnA
rnA
mA
+VOp -4V6
±200
+20
±3.0
V
fLV
nA
nA
dB
dB
Model
Output Current Range
Output Current Error
TEMPERATURE RANGE
Case Operating 14
Storage
Conditions
Min
Pin Ix OUT
PinVx -Pin Ix
+0.01
TmmtoTmax
-40
-65
AD693AD
Typ
Max
+5
rnA
%
±0.OO5
PACKAGE OPTION 15
Units
+85
+ ISO
°C
°C
0-20
NOTES
'Total error can be significantly reduced (typically less than 0.1 %) by trimming the zero curreD!. The remaining unadjusted
error sources are transconductance and nonlinearity.
2The AD693 is t~sted as a loop powered device with the signal amp, VII converter, voltage reference, and application voltages
operating together. Specifu:ations are valid for preset spans and spans between 30mV and 60mV.
'Error from ideal output assuming a perfect 1000 RTD at 0 and + 100°C.
'Refer to the Error Analysis to calculate zero current error for input spans less than 30mV.
'By forcing the differential signal amplifier input sufficiently negative the 7",A zero current can always be achieved.
"The operational voltage (Vop) is the voltage directly across the AD693 (Pin 10 to 6 in two-wire mode, Pin 9 to 6 in
local power mode). For example, Vop=Vs - (ILOoP x R L ) in two-wire mode (refer to Figure 10).
'Bias currents are not symmetrical with input SJgnallevel and flow out of the input pins. The input bias current of the
inverting input increases with input signal voltage, see Figure 2.
8Nonlinearity is defmed as the deviation of the output from a straight line connecting the endpoints as the input is swept over a
30mV and 60mV input span.
'Specifications for the individual functional blocks are components of error that contribute to, and that are included in, the Loop
Powered Operation specifications.
"'Includes error contributions of VII converter and Applicauon Voltages.
"Changes in the reference output voltage due to load will affect the Zero Current. A I % change in the voltage reference output wtll
result in an error of 1% in the value of the Zero Current.
"If not used for external excitation, the reference should be loaded by approximately ImA (6.2kO to common).
"In the loop powered mode up to SmA can be drawn from the reference, however, the lower limit of the output span will be
increased accordingly. 3.5mA is the m8Xlmum current the reference can source while still maintaining a 4mA zero.
14The AD693 is tested with a pass transistor so TA"'Tc .
"See Section 16 for package outline information.
Specifications subJect to change without notice.
Specifications shown in boldface are tested on all production units at fmal electncal test. Results from those tests are used to
calculate outgoing quality levels. All mm and max specifications are guaranteed, a1thongh only those shown in boldface are
tested on all producnon units.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . .
Reverse Loop Current . . . • . . . .
Signal Amp Input Range .. . . . .
Reference Short Circuit to Common
Auxiliary Amp Input Voltage Range
Auxiliary Amp Current Output . .
Storage Temperature . . . . . . .
Lead Temperature, lOsec Soldering
Max Junction Temperature . . . .
. . . . +36V
. . . . 200mA
-O.3V to Vop
IndefInite
-O.3V to Vop
10mA
- 65°C to 150·C
+3OO"C
+ 1500c
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-21
Typical Characteristics
1250.----,----r--_-,-_ _- ,
-'20
~
~
-8'
I---+---I---::l~.;;t-~~~
750
~
-'00
1000 I---+---I---+~~~
'Ii,
~
-00
I
i.: I---+-----,"""t- 2
T
COPPER·NICKEL
Table II. ThermocoupleApplication - Cold Junction Compensation Table
From Table II simply choose the type of thermocouple and the
appropriate average reference junction temperature to select
.
values for RcoMP and R z . The qc voltage is developed across
RcoMP as a result of the AD592 IjJ.A1K output and is added to
the thermocouple loop voltage. The son potentiometer is biased
by R z to provide the correct zero adjustment range appropriate
for the divider and also translates the Kelvin scale of the ADS92
to ·Celsius. To calibrate the circuit, put the thermocouple in an
ice bath (or use a thermocouple simulator set to 0) and adjust
the potentiometer for a 4mA loop current.
The span of the circuit in ·C is determined by matching the
signal amplifier input voltage range to it's temperature equivalent
via a set of thermocouple tables referenced to ·C. For example,
the output of a properly referenced type J thermocouple is
60mV when the hot junction is at 103S·C. Table II lists the
maximum measurement temperature for several thermocouple
types using the preadjusted 30mV and 60mV input ranges.
More convenient temperature ranges can be selected by determining the full-scale input voltages via standard thermocouple
tables and adjusting the AD693 span. For example, suppose
only a 300·C span is to be measured with a type K thermocouple.
From a standard table, the thermocouple output is 12.207mV;
since 60mV at the signal amplifier corresponds to a 16mA span
at the output again ofS, or more precisely60mV/12.207mV =4.91S
will be needed. Using a 12.207mV span in the gain resistor
formula given in "Adjusting Input Span" yields a value of about
2700 as the minimum from PI to 6.2V. Adding a SOO potentiometer will allow ample adjustment range.
With the connection illustrated, the AD693 will give a full-scale
indication with an open thermocouple.
ERROR BUDGET ANALYSIS
Loop-Powered Operation specifications refer to parameters
tested with the AD693 operating as a loop-powered transmitter.
The specifications are valid for the preset spans of 30mV, 60mV
and those spans in between. The section, "Components of Error",
refers to parameters tested on the individual functional blocks,
(Signal Amplifier, VII Converter, Voltage Reference, and Auxiliary
Amplifier). These can be used to get an indication of device
performance when the AD693 is used in local power mode or
when it is adjusted to spans of less than 3OmV.
Table III lists the expressions required to calculate the total
error. The AD693 is tested with a 250n load, a 24V loop supply
and an input common-mode voltage of 3.1V. The expressions
below calculate errors due to deviations from these nominal
conditions.
The total error at zero consists only of offset errors. The total
error at full scale consists of the offset errors plus the span
errors. Adding the above errors in this manner may result in an
error as large as 0.8% of full scale, however, as a rule, the AD693
performs better as the span and offset errors do not tend to add
worst case. The specification ''Total Unadjusted Error", (TUE),
reflects this and gives the maximum error as a % of full scale
for any point in the transfer function when the device is operated
in one of its preset spans, with no external trims. The TUE is
less than the error you would get by adding the span and offset
errors worst case.
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-29
•
Thus, an alternative way of calculating the total error is to start
with the TUE and add to it those errors that result from operation
of the AD693 with a load resistance, loop supply voltage, or
common-mode input voltage different than specified. (See Example
I below.)
RTI Contributions to Offset Enor
Error Source
Zero Current Error
PSRR
CMRR
Iz~s
Power Supply Rejecnon Ratio
qVLOOF -24Vi +[lRL -25001 x Izl) x PSRR
Common·Mode Rejection Ratto
lOS
Input Offset Current
IVCM -3.IVI x CMRR
Rsx lOS
RTI Contributions to Span Error
Error Source
ERROR BUDGET FOR SPANS LESS THAN 30mV
An accommodation must be made to include the input voltage
offset of the signal amplifier when the span is adjusted to less
than 30mV. The TUE and the Zero Current Error include the
input offset voltage contribution of the signal amplifier in a gain
of 2. As the input offset voltage is multiplied by the gain of the
signal amplifier, one must include the additional error when the
signal amplifier is set to gains greater than 2.
Expression for RTI Error at Zero
IZE
Exprel!lSioD for RTI Enor at Full Scale
Transconductance Error
Transconductance PSRR I
V SPAN x X SE
Transconductance CMRR
IVCM -3.1VI x
VSPAN X X NL
Nonhneanty
DIfferential Input Current2
IRe - 25001 x Is x PSRR
V SPAN x ~
Rs
X IOIFF
AbbreviatioDs
Iz
Zero Current (usually 4mA)
For eX2...f!lple, the 300 OK span thermocouple application discussed
previously requires a 12.207mV input span; the signal amplifier
must be adjusted to a gain of approximately s. The loop transconductance is now 1.333 AN, (5 X 0.2666 AN). Calculate the
total error by substituting the new values for the transconductance
and span into the equations in Table III as was done in Example
I. The error contribution due to Vos is 5 x Vos, however, since
2 x Vos is already included in the TUE and the Zero Current
Error it is necessary to add an error of only (5 - 2) x Vos to the
error budget. Note that span error may by reduced to zero with
the span trim, leaving only the offset and nonlinearity of the
AD693.
Is
Rs
Output span (usually 16mA)
Input source impedance
RL
V LOOP
VCM
V SPAN
Xs
[..oad rf"O;:lo;:tQn~
Loop supply voltage
Input common-mode voltage
Input span
Nominal ttansconductance m AN
lThe 4-20mA signal, flowmg through the metenng resistor, modulates the power supply
voltage seen by the AD693. The change m voltage causes a power supply rejection error
that varies With the output current, thus it appears as a span error.
2The mput bias current of the mvertmg input mcreases With mput signal voltage. The differential
mput current, I DlFF, equals the mvenmg mput current IOlOUS the noninvenmg mput current;
see Figure 2. I DlFF, flowmg mto an mput source mpedance, will cause an input voltage
error that varies WIth signal. If the change m dtfferenualmput current With input SlgnallS
approXlIOated as a linear funcuon, then any error due to source unpedance may be approxnnated
as a span error. To calculate I DlFF, refer to Figure 2 and fmd the value for IDiPP/+In correspondtng to the full-scale lOput voltage for your application. MulupJy by + In max to get
I D1FF• Multiply IDiFF by the source impedance to get the mput voltage error at full scale.
Table Iff. RTI Contributions to Span and Offset Error
EXAMPLE I
The AD693 is configured as a 4-20mA loop powered transmitter
with a 60mV FS input. The inputs are driven by a differential
voltage at 2V common mode with a 300n balanced source resistance. A 24V loop supply is used with a
metering
resistance. (See Table IV below.)
soon
Trimming the offset and span for your application will remove
all span and offset errors except the nonlinearity of the AD693.
OFFSET ERRORS
Iz
Already included in the TUE spec.
PSRR
PSRR~S.6fLVIV;(j24V
-24VI
O.OfLV
+ [lSOOn -25001 x 4mA]) x S.6fLVIV
~
S.6fLV
V wop
RL
~
~ 24V
SOOnl z
~
4mA
CMRR CMRR ~ 30fLVIV;12V -3.IVI x 30fLVIV ~
33.0fLV
VCM~2V
lOS
lOS
~
3nA, Rs
~
30011; 3000 x 3nA
~
0.9fLV
Total Additional Error at 4mA
39.5fLV
As % offuU scale; (39.SfLV x 0.2666A1V)l20mA x 100%
~
0.OS3%ofFS
SPAN ERRORS
X SE
Already mcluded in [he TUE spec.
X PSRR
PSRR ~ S.6fLVIV;(ISOOO -25001 x 16mA) x S.6fLVIV
RL ~ soon, Is ~ I6mA
XcMRR Xc..RR
~
O.OfLV
~
22.4fLV
0.06%1V;12V -3.IVI x 60mV x 0.06%1V ~
39.6fLV
VCM =2V, VSPAN = 60mV
IDlFF
X NL
VSPAN = + 6OmV;300n x 2 x ZOnA
IDIFFI + In = 2
from Figure 2)
12.0!-,V
Already mcluded in the TUE
O.OfLV
Total Additional Span Error at Full Scale
74.0fLV
Total AddItional Error at Full Scale; EOFFSET + ESPAN = 39.Sf.LV
As % of Full Scale; (1 13.SfLV x 0.2666AIV)/20mAx 100% ~
+ 74.0/J-V
=
NewTotalUnadjustedError@FS;ETUE+ EADDITIONAL = 0.5% +0.151% =
Table IV. Example 1
11-30 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
IJ3.SfLV
O.ISI%ofFS
O.651%ofFS
Isolated, Loop-Powered
Voltage-to-Current Converter
11IIIIIIII ANALOG
WDEVICES
1B21 I
IB21 FUNCTIONAL BLOCK DIAGRAM
FEATURES
Wide Input Range: 0-1V to 0-10V
High CMV Isolation: 1500V rms
Programmable Output Ranges: 4mA to 20mA
o to 20mA
Load Resistance Range: 0 to 1.35kfi max
High Accuracy
Low Offset Tempco: ±300nA/oC
Low Gain Tempco: ±50ppm/oC
Low Nonlinearity: ± 0.02%
High CMR: 90dB min
Small Package: 0.7" x 2.1" x 0.35"
Meets IEEE Std. 472: Transient Protection (SWC)
REF
OUT
+15V
-15V
APPLICATIONS
Multichannel Process Control
D/A Converter - Current Loop Interface
Analog Transmitters and Controllers
Remote Data Acquisition Systems
GENERAL DESCRIPTION
The IB21 is an isolated voltage-to-current converter that incorporates a unique circuit design utilizing transformer based isolation
and automated surface mount manufacturing technology. It
provides an unbeatable combination of versatility and performance
in a compact plastic package. Designed for industrial applications,
it is especially suited for harsh environments with extremely
high common-mode interference.
Functionally, the VII converter consists of four basic sections:
input conditioning, modulator, demodulator and current source
(lB21 Functional Block Diagram). The input is a resistor programmable gain stage that accepts a 0-1 V to O-IOV voltage input.
This maps into a 0 to 20mA output or can be offset by 20%
using the internal reference for 4mA to 20mA operation. The
high level signal is modulated and passed across the barrier
which provides complete input to output galvanic isolation of
1500V rms continuous by the use of transformer coupling techniques. Nonlinearity is an excellent ± 0.05% max.
Designed for multichannel applications, the IB21 requires an
external loop supply and can accept up to 30V max. This would
provide a loop compliance of 27V, which is sufficient to drive a
1.35k,O load resistance.
The IB21 is fully specified over - 25°C to + 85°C and operates
over the industrial ( - 40°C to + 85°C) temperature range.
DESIGN FEATURES AND USER BENEFITS
High CMV Isolation: The lB2l features high input to output
galvanic isolation to eliminate ground loops and offer protection
against damage from transients and fault voltages. The isolation
barrier will withstand continuous CMV of 1500V rms and meets
the IEEE Standard for Transient Voltage Protection (Std. 472SWC).
Small Size: The IB2l package size (0.7" x 2.1" DIP) makes it
an excellent choice in multichannel systems for maximum channel
density. The 0.35" height also facilitates applications with limited
board clearance.
Ease of Use: Complete isolated voltage-to-current conversion
with minimum external parts required to get a conditioned
current signal. No external buffers or drivers are required.
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-31
III
SPECIFICATIONS (typical at +25"Cand Vs = ±15VunlessolhelWisenoted)
Model
IB21AN
INPUT SPECIFICATIONS
Input Range
Full-Scale Input
Input Bias Current
Oto + lOY
+ IVmin to + 10Vmax
± 30pA ( ± 400pA max)
OUTPUT SPECIFICATIONS
Current Output Range
Load Compliance at VLOOP = 30V
Max Output Current @ Input Overload
Output Noise, 100Hz Bandwidth
4mA t020mA, 0 to 20mA
27Vmin
2SmA
liJ.Ap-p
NONLINhAKI 1 Y (% of Span)
±U.UZ%(±U.U5%max)
ISOLATION
CMV, Input to Output Continuous
CMR,@60Hz
Transient Protection
lSOOVrms
90dBmin
IEEE-STD 472 (SWC)
ACCURACY
Warm-Up Time to Rated Performance
Total Output Error ([Ii + 25°C (Untrimmed)
Offset (V IN = OV) I
Span(VIN = + 10V)
vs. Temperature ( - 25°C to + 85°C)
Offset 2
Span
REFERENCE OUTPUT
Voltage
Output Error
Temperature Coefficient
DYNAMIC RESPONSE
Settling Time toO.l% ofF.S. for lOY Step
Small Signal Bandwidth
-1
I-t20~1
r+
1821
05
BOTIOM
(1251
VIEW
1.-:
ACI060 MATING SOCKET
Smin
± 100iJ.A
±0.6%FSR
±300nA/oC
±SOppmfOC
PIN DESIGNATIONS
PIN
+ 6.4V de
± 1.5% max
± 20ppmfOC max
9ms
100Hz
POWER SUPPLY
Input Side
Operating Voltage
Quiescent Current
+ ISVSupply
- iSVSupply
Power Supply Rejection
Loop Side
Operating Voltage
Maximum Current
+ ISVto +30V
2SmA
ENVIRONMENTAL
Temperature Range
Rated Performance
Operating
Storage
Relative Humidity, Noncondensing
- 25°C to + 85°C
- 40°C to + 85°C
-- 40°C to + 85°C
oto 95% 0' + 60°C
CASE SIZE
OUTLINE DIMENSIONS
Dimensions shown in inches and (rom).
±lSV±S%
lOrnA
SmA
±O.OI%iV
0.7"x2.l"x 0.35"
(\7.8 x 53.3 x 8.9)mm
NOTES
1For 0-20mA mode. For 4-20mA mode an addltional60J.1A IS contnbuted by the:±: 1.5%1 reference error on the 4mA output.
2For a complete discussIOn of the temperature effect~ of the offset resIstor and reference refer to "U!.lflg the 1B21" sectIOn.
Specification!. !.ubjcct to change Without notIce.
11-32 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
1
17
18
19
20
21
22
38
FUNCTION
OUTHI
IN
FB
REF
+15V
COM
-15V
OUTLOW
INSIDE THE IB21
Referring to the functional block diagram, the ± 15V power
inputs provide power to both the input side circuitry and the
power oscillator. The 25kHz power oscillator provides both the
timing information for the signal modulator and drives transformer
T2 for the output side power supplies. The secondary winding
of T2 is full wave rectified and filtered to create the output side
power.
The input stage is configured as an inverting amplifier with
three user supplied resistors for gain, offset and feedback. The
conditioned signal is modulated to generate a square wave with
a peak-to-peak amplitude proportional to VIN. This signal drives
the signal transformer Tl. An internal reference with a nominal
output voltage of + 6.4V and tempco of ± 20ppm/oC is provided
to develop a 4mA offset for 4mA to 20rnA current loop
applications.
After passing through signal transformer T I, the amplitude
modulated signal is demodulated and filtered by a single pole
filter. Timing information for the output side is derived from
the power transformer T2. The filtered output provides the
control signal for the voltage-to-current converter stage. An
external power supply is required in series with the load to
complete the current loop.
V'N O-..J>,Jvv-....-.{"
+15Vo---1~
_ _-t
,~
_ _-'------'-----'L-.I
---,
COM O---1~--{
Figure 1. Basic Interconnections
Input
Volts
Output
rnA
RI
kG
RF
kG
Ro
kG
0-5
0-10
0-5
0-10
1-5
0-20
0-20
4-20
4-20
4-20
25
50
25
50
25
25
25
20
20
25
Open
Open
128
128
Open
Table I. Resistor Values for Typical Ranges
USING THE IB21
Input Configurations: The lB21 has been designed with a
flexible input stage for a variety of input and output ranges.
The basic interconnection for setting gain and offset is shown in
Figure I. The output of the internal amplifier is constrained to
o to - 5V, which maps into 0 to 20mA across the isolation
barrier. Thus to create a 4mA offset at the output, the input
amplifier has to be offset by IV.
For example, for 0 to 20rnA operation the transfer function for
the input stage is:
5NIN = RFiRI
Adjustments: Figure 2 is an example of using potentiometers
for trimming gain and offset for a 0-5V input and 0 to 20mA
output. The network for offset adjustment keeps the resistors
relatively small to minimize noise effects while giving a sensitivity
of ± 1% of span. For more adjustment range, resistors smaller
than 274k can be used. Resistor values froI& Table I can be
substituted for other input and output ranges.
In general, any bipolar voltage can be input to the IB21 as long
as it is offset to meet the 0 to - 5V constraint of the modulator
and the input signal range is IV minimum.
and no offset resistor is needed. For 4mA to 20mA operation we
get:
4NIN = RFiRI
which maps the input voltage into a 4V span. To create a IV
offset at the output of the internal amplifier (4mA at the output
of the IB21) a current derived from the reference can be fed
into the summing node. The offset resistor (for a IV output
offset) will be given by the equation: Ro = 6.4RF. For most
applications it is recommended that RF be in the 25kO ± 20%
range. Resistor values for typical input and output ranges are
shown in Table I.
Figure 2. Offset and Span Adjustment
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-33
•
TC Considerations of External Resistors: The specifications
for gain and offset temperature coefficient (TC) for the lB21
exclude the effects of external components. The total gain TC
for the circuit in Figure 1 is:
r---'-...-'-W.""-......
r---,
BECKMAN SDk RIN
IN2
O-....:.._ _
--{1
I}-'----,
":j:~~:tt~::t+--(i~~~
IN1 0
OFFSET
4mA~~_~,~~~~~
Gain TC = lB21 Gain TC + (Tracking TC of RF and R 1)
COM
V
L ___ .J
L ___ .J
The offset TC is also affected by the thermal stability of the
internal voltage reference and its contribution is:
NOTE
Ref TC = (VREF)(RF/Ro)(4mAIV)(TC of VREF +
Tracking TC of RF and Ro Y1 x 106
NODES LABELLED FOR
ILLUSTRATION ONLY
Total Offset TC = 1B21 Offset TC + Ref TC
Specifically using R F , R! and Ro from
absolute TCs of ± 25ppm;oC we get:
f:'5("
3 in Table I, with
Gain TC = 50 + (25 + 25) = 100ppm;oC
Offset TC
300 + (6.4V)(20k/128k)(4mAIV)(20 + 25 + 25)1
1 x 106
±580nA;oC
Figure 4. Low Tempco Resistor Network Configuration
Multiloop Isolation: Multiple 1B21s can be connected to a
single loop supply in parallel as shown in Figure 5. The amperage
of the loop supply should be sufficient to drive all the loops at
full-scale output.
Similarly, when using a resistor network with a tracking spec of
± 5ppm;oC, the total gain TC would be ± 55ppm;oC and the
total offset TC would be ±400nA;oC.
APPLICATIONS
Output Protection: In many industrial applications it may be
necessary to protect the current output from accidental shorts to
ac line voltages in addition to high common-mode voltages and
short circuits to ground. The circuit shown in Figure 3 can be
used for this purpose. The maximum permissible load resistance
will be lowered by the fuse resistance (typically 8H) when
protection circuitry is utilized.
Figure 5. Multiple IB21s with Single Loop Supply
RLOIilO
Figure 3. Output Protection Circuitry
Low Drift Input Network: Figure 4 shows a configuration
suitable for applications where errors have to be minimized over
a wide temperature range. A temperature tracking network such
as a 50k Beckman (PN 698-3R50KD) can be used to implement
both offset and gain for either 0 to 20mA or 4mA to 20mA
current loops. For 0-IOV signals either INI or IN2 can be used
for input. For 0-5V signals, jumper INl to IN2. Similarly, for
4mA to 20mA operation the 4mA node should be jumpered to
OFFSET, while for 0 to 20mA it should be tied to COM.
11-34 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
Programmable, Isolated
Voltage-to-Current Converter
1B22 I
IIIIIIIIIII ANALOG
WOEVICES
IB22 FUNCTIONAL BLOCK DIAGRAM
FEATURES
Internal Isolated Loop Supply Drives 10000 Load
Pin Programmable Inputs: 0-5V or 0-10V
Pin Programmable Outputs: 4-20mA or 0-20mA
High CMV Isolation: 1500V rms
Normal-Mode Output Protection: 240V rms
Wide Input Range: 0-1V to 0-10V
High Accuracy
Low Input Offset Tempco: ±300nAloC
Low Gain Tempco: ±50ppm/oC
Low Nonlinearity: ± 0.02%
High CMR: 90dS min
Small Package: 1.0" x 2.1" x 0.35"
Meets IEEE Std 472: Transient Protection (SWC)
,
OUT
HI
APPLICATIONS
Multichannel Pr9cess Control
DIA Converter - Current Loop Interface
Analog Transmitters and Controllers
Remote Data Acquisition Systems
":J~~t'~n,d W1.th V LOOP
""·1o~~,;. '\1't&:;","&:I""
= 28V, it is sufficient to drive a lOOO!}
., 11le
iBZ~'1~;tully specified over - 25°C to + 85°C and operates
".;""!i;~~,,,ttI'e o/,ndustrial ( - 40°C to + 85°C) temperature range.
GENERAL DESCRIPTION
': ;
I.I:~~,
The IB22 is an isolated voltage-to-cur~en~, convi;l'~er that iniulr~:<" ':i}
porates transformer isolation to achieve;. "ighperform;ln~ and,,:i~
DESlON FEATURES AND USER BENEFITS
automated surface mount maal.lf¢trlringfor lower,cost a!ld'la~i~op Power: Internal loop supply completely isolates
increased reliability. Designed'~i industrial IlJ?Pijca~~, it is
OJ> from the input terminals (l500V rms) and provides the
especially suited for harsh envirOnmenl/l'withexWnnely ,high :"
ility to drive 0 to lOOO!} loads. This eliminates the need
an external dc/dc converter.
common-mode interference. With programmable inputs and 'I~
outputs, the lB22 provides an unbeatable combination ofveiS\l,dllty
Ease of Use: The IB22 offers complete isolated voltage-to-current
and performance in a compact plastic package.
conversion with minimum external parts required to get a conditioned current signal. No external buffers or drivers are
Functionally, the VII converter consists of four basic sections:
required.
input conditioning, modulator/demodulator, isolated loop supply
and current source (Figure I). The input is pin programmable
for 0-5V or O-lOV inputs and 0-20mA or 4-20mA outputs using
an internal resistor network. It can also be set by an external
resistor to accept O-IV to O-IOV voltage inputs. Transformer
coupling provides 1500V rms galvanic isolation between the
inputs and the current loop. Nonlinearity is an excellent ± 0.05%
max.
Loop power is generated internally through a dc/dc converter
and is also isolated from the input side (1500V rms). Loop
compliance voltage is dependent on the voltage supplied to the
High CMV Isolation: The IB22 features high input to output
galvanic isolation to eliminate ground loops and offer protection
against damage from transients and fault voltages. The isolation
barrier will withstand continuous CMV of 1500V rms and
meets the IEEE Standard for Transient Voltage Protection (Std.
472-SWC).
Small Size: The IB22 package size (1.0" x 2.1" DIP) makes it
an excellent choice in multichannel systems for maximum channel
density. The 0.35" height also facilitates applications with limited
board clearance.
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-35
•
SPECIFICATIONS
(typical @+25OC and Vs= ± 15V unless otherwise noted)
Model
INPUT SPECIFICATIONS
Factory Calibrated, User Selectable
Input Impedance
O-IOV input range
0-5V input range
IB22AN
Oto +5V,Oto +IOV
50kO
25kO
OUTPUT SPECIFICATIONS
Current Output Range, User Selectable
Load Compliance Range, VLQOP= + 15V
VLQOP= +28V
l.taximum Output Current @ Inpui Overluad
Output Noise, 100Hz Bandwidth
4 to 20rnA, 0 to 20mA
8Vmin
22Vmin
25mA
l ..Ap-p
NONLINEARITY (% OF SPAN)
± 0.02% (0.05% max)
ISOLATION
CMV, Input to Output Continuous
CMR,@60Hz
Normal-Mode Output Protection
Transient Protection
OUTLINE DIMENSIONS
Dimensions shown in inches and (nun).
(~.~~I
---L I
3
J]08
MAX
iJ
U
MAXT
!--0.80(20.3ITYP---j
16
2~--1
1500Vrms
90dBmin
2.10
(53.31
BOTTOM
MAX
VIEW
ACCURACY
Warm-Up Time to Rated Performance
TotalOutputError@ +25°C
Offset (VIN = OV) .
Span(VIN = + lOY)
vs. Temperature ( - 25°C to + 85°C)
Offset
Span
0.1
(2541
TYP
01
(2.541
TYP
~
T
L
T
1
38-l
.-<-
I
-I I- (2"s~1
I--- 1.00 (2.541 MAX ~ TYP
DYNAMIC RESPONSE
SettlingTimetoO.l%ofF.S. fo
Small Signal Bandwidth
POWER SUPPLY
Bipolar Input Supplies
Operating Voltage
Quiescent Current
Power Supply Rejection
Loop Supply
Operating Voltage
Operating Current, at Full-Scale Output
+14Vto +30V
30rnA
ENVIRONMENTAL
Temperature Range
Rated Performance
Operating
Storage
Relative Humidity, N oncondensing
- 25°C to + 85°C
-40°Cto + 85°C
- 40°C to + 85°C
oto 95% @ 60°C
CASE SIZE
1.0" X 2.1" X 0.35"
PIN DESIGNATIONS
± 15V ±5%
±7.5rnA
±O.OOl%N
NOTE
Specifications subject to change without notice.
11-36 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
01
(2.541
TYP
PIN
FUNCTION
16
17
18
19
20
21
22
23
24
25
38
OUTHI
IN2
IN1
S.NODE
4mAOFFSET
+15V
ANA COM
-15V
SYNC
V lOOP
POWER COM
OUTLOW
Wide Bandwidth Strain Gage
Signal Conditioner
1B31 I
~ANALOG
WDEVICES
FEATURES
Low Cost
Complete Signal-Conditioning Solution
Small Package: 2a-Pin Double DIP
Internal Half-Bridge Completion Resistors
Remote Sensing
High Accuracy
Low Drift: :!:O.25J1.VI"C
Low Noise: 0.3J1.V pop
Low Nonlinearity: :I: 0.005% max
High CMR: 140dB min (60Hz. G=1000VNl
Programmable Bridge Excitation: +4V to + 15V
Adjustable Low Pass Filter: fc = 10Hz to 20kHz
IB31 FUNCTIONAL BLOCK DIAGRAM
+INPUT 1
IUNAtTERED)
INPUTOO::~
APPLICATIONS
Measurement of: Strain. Torque. Force. Pressure
Instrumentation: Indicators. Recorders. Controllers
Data Acquisition Systems
Microcomputer Analog 1/0
I}--++--+
9
INPUTOFF:~ 1 0 } - - - - - '
OUTPUT~tIT~: 1 1 } - - - - . ,
BANm:~r: 12
BAND~~ 13
GENERAL DESCRIPTION
Model IB31 is a high performance strain gage signal-conditioning
component that offers the industry's best pricelpenormance
solution for applications involving high-accuracy interface to
strain gage transducers and load cells. Packaged in a 28-pin
double DIP using hybrid technology, the IB31 is a compact and
highly reliable product. Functionally, the signal conditioner
consists of three sections: a precision instrumentation amplifier, a two-pole low pass filter, and an adjustable transducer
excitation.
The instrumentation amplifier (IA) section features low input
offset drift of ±0.25 ....VI"C (RTI, G= lOOOVIV) and excellent
nonlinearity of ± 0.005% max. In addition, the IA exhibits low
noise of 0.3 ....V POp typ (0. 1Hz-10Hz), and outstsnding l40dB
min common-mode rejection (G= lOOOVlV, 60Hz). The gain is
programmable from 2VIV up to 5000VIV by one external
resistor.
The two-pole low pass filter offers a 40dB/decade roll-off from
1kHz to reduce high frequency noise and improve system signalto-noise ratio. The comer frequency is adjustable downwards by
external capacitors and upwards to 20kHz by three resistors.
The output voltage can also be offset by ± lOY with an external
potentiometer to null out dead weight.
The IB31's regulated transducer excitation stage features low
output drift (±0.004%/"C typ) and can drive 120n or higher
resistsnce load cells. The excitation is preset at + lOY and is
adjustable from +4Vand + 15V. ThiS section also has remote
sensing capability to allow for lead-wire compensation in 6-wire
bridge configurations. For half-bridge strain gages, a matched
IRL~ED)
14
pair of thin-film 20k{} resistors is connected across the excitation
outputs. This assures temperature tracking of ± 5ppm/"C max
and reduces part count.
The IB3l is available in a plastic package specified over the
industrial ( - 4O"C to + 85°C) temperature range and will be
available soon in a bottom-brazed ceramic package specified
over the military ( - 55°C to + 125°C) temperature range.
DESIGN FEATURES AND USER BENEFITS
Eaae of Use: Direct transducer interface with minimum external parts required, convenient offset and span adjustment
capability .
Half-Bridge Completion: Matched resistor pair tracking to
± 5ppmfOC max for half-bridge strain gage applications.
Remote Sensing: Voltage drops across the excitation lead-wires
are compensated by the regulated supply, making 6-wire load-cell
interfacing straightforward.
Programmable Transducer Excitation: Excitation source preset
for + lOY dc operation without external components. Userprogrammable from a +4V to + 15V dc to optimize transducer
performance.
Adjustable Low Pass Filter: The two-pole active filter (fe = 1kHz)
reduces noise bandwidth and aliasing errors with provisions for
extemal adjustment of cutoff frequency (lOHz to 20kHz).
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-37
•
SPECIFICATIONS{tJpicaI@ +25"C and Vs = :tl5Vlriessalh8lWisenollld)
IB31AN
Model
GAIN'
Gam Range
Gam Equation
Gain Equation Accuracy, G.s;; lOOOVN
Gam Temperature CoeffiClent2
Nonhneanty
OFFSET VOLTAGES'
Total Offset Voltage, Referred to Input
Initial,@ + 25°C (AdJustable to Zero)
G = 2VIV
G = lOooVIV
Warm·Up Dnft. 51D1n ,G = lOOOVIV
2to5000VIV
Rc = 8Ok!l
G-2
±2mV(±IOmVmax)
±50jLV(±2oojLVrnax)
With!!! ± !~Voffina! '!2!ue
G = 2VIV
G = lOooVIV
±25jLVI"C(±50jLVl"Cmax)
± O.25jLVI"C (± 2jLV/OC max)
At Other Gams
( +2 + 100) .
- -QjLVI"C
INPUT BIAS CURRENT
lrutial@25°C
vs. Temperature
INPUT DIFFERENCE CURRENT
IDlbal@ +25OC
vs. Temperature
±50jLVIV
±O.5jLVIV
±10Vmin
± IOnA(± 50nA max)
±25pAI"C
± 5nA (± 20nA max)
±IOpAl"C
INPUT IMPEDANCE
DIfferential
Common Mode
INPUT VOLTAGE RANGE
Linear Differential Input (V D)
MaximumCMVlnput
CMR, lill Source Imbalance
G=2VIV,dcto60Hz
G= looVIVto 5000VIV
1kHz Bandwidth'
@dcto60Hz
10Hz Bandwidth'
@dc
@60Hz
INPUT NOISE
VoItage,G= lOOOVIV
O.IHzto 10Hz
IOHuo 100Hz
Current,G=IOOOVIV
O.IHztoIOHz
10Hz to 100Hz
RATED OUTPUT'
Voltage, 2ill Load, min
Current
Impedance, de to 2Hz, G'= 2VN to lOOOVN
Load Capacitance
Output Short-Urcuit Duration
DYNAMIC RESPONSE'
Small Signal Bandwidth - 3dB, G= 2VIV to lOOOVIV
Slew Rate
Full Power
SettlingTime,G = 2VIV to lOOOVIV, ± IOVOutput,
Stepto ::!::O.l%
IG!lll4pF
IG!l114pF
±5V
o)
GXV
± ( 12-Vmax
486dB
1I0dBmin
lIOdBmin
140dBmin
O.3jLVp,p
I jLV p-p
6OpAp-p
lOOpAp-p
±IOV
±5mA
o.m
lOOOpF
Indefinite
1kHz
O.05V/jLs
350Hz
2ms
LOW PASS FILTER
Number of Poles
Gain (Pass Band)
Cutoff Frequency ( - 3dB Point)
Roll-Off
Dimensions shown in inches and (mm).
··
·
PLASTIC PACKAGE (N)
. i--- o 83121.11 MAX ~--1..
..ll
±3%
± 15ppmfC(±25ppmI"Crnax) •
±O.OOS%max
vs. Temperature
vs. Supply
G = 2VIV
G = lOooVIV
Output Offset AdjuSl Range
OUTLINE DIMENSIONS
IB31SDt
2
-2VIV
1kHz
40dB/decsde
·
··
13~1~IN ~
*
11-38 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
;4'
15
8
21
4
25
1
28
T
1
1.64
141.71
MAX
-./ j.- 0 0.;(, 271 GRID
BOTTOM VIEW
CERAMIC PACKAGE (D)
"
"
SEE
NOT<1 ....
I
/-
"
157514001
f -, -' -- ----]C
_I
~IOO16103
.m•• :
~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ I'·'
"'1=~:f
i,\:
~
010012541
~~
001410381
~
~
o 030!0 161
OlOO/2S4)
0023(058)
~ ~
0137134.)
0070(178)
NOTES
1 LEAD NO t IOENTlFlED BV DOT OR NOTCH
r-- :!!:l!::~: ----t
···
·
··
··
00110.251+
-r=
·
··
·
···
··
··
··
·
·
·
·
·
··
··
··
·
··
1163g~AX
l
1
~f
J
001&(038)
I--::::~:~:--'{
PIN DESIGNATIONS
PIN
1
2
3
4
8
9
10
11
12
13
14
FUNCTION
+INPUT
-INPUT
GAIN
GAIN
VouTIUNFILTERED)
INPUT OFFSET ADJ.
INPUT OFFSET ADJ
OUTPUT OFFSET ADJ.
BANDWIDTH ADJ 1
BANDWIDTH ADJ. 2
V"'JTIFILTERED)
PIN FUNCTION
15
V.
16 COMMON
17
+V.
18
+V.REGULATOR
19 REF OUT
20 REF IN
21 EXCITATION AOJ.
25 HALF·BRIDGE COMP.
26 SENSE LOW
27 SENSE HIGH
28
VEXcOUT
Model
1831AN
1831SDt
AC1222 MOUNTING CARD
BRIDGE EXCITATION
Regulator Input Voltage Range
Output Voltage Range
Regulator Input/Output Voltage Differential
Output CurrentS
Regulauon, Output Voltage vs. Supply
Load RegulatIon, IL = ImA to SOmA
Output Voltage VS. Temperature
Output Noise, 10Hz to lkHz6
Reference Voltage(Internal)
Internal Half-Bridge Completion
Nominal ResIstor Value
Temperature TracklOg
POWER SUPPLY
Voltage, Rated Performance
Voltage,Operatmg
Current, Qwescent7
+9.SVto +28V
+4Vto + lSV
+3Vto +24V
100mAmax
:to 05%N
±0.1%
Q
o
fINE~~JN
0"0" 0"
0"'0'''0 TP4
0:"
TPl OUT
~2
OfFSET
O
:!:O.004%/oC
INPUT
GNU
OuT
TP3
D
EXCITATtO:
""
UNFilTERED
OUT
"
J3
~
OFFSET
<><=T,"
200",Vp-p
+6.8V ±5%
20k!! ± 1%
± Sppm/oC max
" 15Vdc
± 12Vto ± 18V de
+lOmA
ENVIRONMENTAL
Temperaturt: Range
Rated Performance
Operating
Storage
RelatIve Hunudlty
Oto9S%@ +60°C
CASE SIZE
o 83"x 1.64"xO.2S"
- 40°C to + 85°C
-40°C to +85°C
- 40"'C to
+ lOQoC
(21Ix41.7x63S0mm)max
- 55°C to + 125°C
- 55°C to + 125°C
-6S0Cto + ISO°C
AC1222 CONNECTOR DESIGNATION
0.81" x I 57" x 0.23"
(206x40.0x5.72mm)
,
2
FUNCTION
+ INPUT
-INPUT
3
N/C
PIN
NOTES
*Speclficatlons same as lB3lAN
tSD grade avadable In Spring 1988
'SpecificatIOns referred to the filtered output at Pm 14
2Excluslve of external gam setthng resistor
3Unadtusted filter settmg
4Fdtercutofffrequency set with external capacitors
5Deratefrom + 50°C as shown m Figure 14
64 7J.lF capacitor from VREF IN (Pm 20) toCOMM
7Exdudmg bndge excitation's current, and with no loadmg on the output
SpeCifications subtect to change without notice
4
••
•
,."
7
·.
10
12
21
22
GAIN!3)
GAIN!4)
VollT(UNFILTERED)
INPUT OFFSET ADJ !9)
INPUTOFFSETADJ !10)
OUTPUT OFFSET ADJ
BANDWIDTHADJ 1
BANDWIDTHADJ 2
VouT/FiLTERED)
PIN
5
T
U
V
X
V
Z
FUNCTION
VEXcOUT
SENSE HIGH
SENSE LOW
HALF-BRIOGECOMP
REF OUT
REF IN
EXC AOJ
-V,
COMMON
+V,
+VsREG
The AC1222 mounting card IS available for the IB31. The AC1222
IS an edge connector card with a 28-pm socket for pluggmg m
the IB31. In addition, 1t has prOVlSlons for installIng the gam
reSIstor and adJusnng the brIdge excitatIOn voltage and cutoff
frequency. Adjustment potentiometers for offset, fine gam and
excitation are also prOVided. The AC1222 comes With a Cmch
251-22-30-160 (or equivalent) edge connector
APPLICATIONS
The IB31 can be interfaced easily and directly to a wide variety
of transducers for precise measurement of strain, torque, force
and pressure. For applications in harsh industrial environments,
such characteristics as high CMR, low noise and excellent temperature stability make the IB31 unsurpassed for use in indicators,
recorders and controllers.
The combination of low cost, small size and high performance
of the 1831 allows the system designer to use one conditioner
per channel. The advantages include significantly lower system
noise and high resolution, and elimination of crosstalk and
aliasing errors.
+INPUT
1
seNSE HIGH
SENSE LOW
20kH
NC
NC
NC
V OIJT
EXC ADJ
(UNFIL TEAEDI
INPUT OFFSET
REF IN
ADJ
FUNCTIONAL DESCRIPTION
Model 1831 is based on a two-stage amplifier design and an
adjustable voltage regulator section, as shown in Figure 1. The
front end is a low noise, low drift, instrumentation amplifier
(IA) that is optimized to amplify low level transducer signals
(from 2mV full scale) riding on high common-mode voltage
(±9.SV). The gain of the IA is programmed by a single resistor
(IVN to 2S00VN) and the input offset nulled out by an external
potentiometer across the offset adjust Pins 9 and 10. The inverted
signal (V -INPUT - V + INPUT) is brought out to Pin 8 for applications
such as vibration and torque testing where the unfIltered output
is required.
The signal is also fed to an inverting 8utterworth fIlter with a
fixed gain of -2VN. This two-pole fIlter is preset with a 1kHz
HALF-BRIDGE
COMPLETION
INPUT OFFSET
REF OUT
ADJ
OUTPUT OFFSET
+Vs REG
ADJUST
BANDWIDTH
+v,
ADJ 1
COMM
1831
VOUT
(FllTEREDJ
-v,
Figure 1. Block Diagram and Pinout
corner frequency which can be adjusted downwards to 10Hz by
using two external capacitors or upwards to 20kHz by three
resistors. This stage also provides a convenient means of adjusting
output offset voltage ( ± IOV) by connecting a SOkO potentiometer
to Pin II.
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-39
III
The bridge excitation section is an adjustable output, regulated
supply with an internally provided reference voltage ( + 6.SV). It
is configured as a gain stage with the output preset at + 10V.
The excitation voltage is increased by connecting a resistor
between Pins 21 and 26, and decreased by connecting a resistor
between Pins 19 and 20. Sense lines are provided to compensate
for lead-wire resistance by effectively bringing the leads into the
feedback loop.
Filter Cutoff Frequency Programming: The low pass filter
cutoff frequency is internally set at 1kHz. It may be decreased
from 1kHz by the addition of two external capacitors connected
as shown in Figure 3 (from Pin 12 to common and between
Pins 13 and 14). The values of capacitors required for a desired
cutoff frequency, fe, below 1kHz are obtained by the equations
below:
-I]
C 0.OO22fLF [1%Hz - I]
CSEL1 = O.OlSfLF
For half-bridge applications, two tracking thin-film resistors
(20kn), ±SppmI"C max) are connected from VBXC OUT
(Pin 2S) to SENSE LOW (Pin 26).
SELZ
[I~
=
CSELI can be polarized for large values.
OPERATING INSTRUCTIONS
Gain Setting: The diffe..--ential gain, G, is detei"iiih"'led by the
24011
equation:
G= 2
+ SOkO
Ra
where Ro is connected between the GAIN terminals (Pins 3 and
4) of the 1831, as shown in Figure 2. For best performance, a
low temperature coefficient (Sppm/"C) Ro is recommended. For
fme span adjustment, a son potentiometer may be connected in
series with Ro.
COMM -1SV
+15V
NOTE
• USESppmI"C GAIN RESISTOR FOR lOWGAINTEMPCO
Figure 3. Narrow Bandwidth Application
The cutoff frequency may also be increased from 1kHz to 20kHz
by the addition of three external resistors, connected as shown
in Figure 4. The equations for determining the resistor values
are:
....,
NOTES
+ v.
son
RsELI
= 20kW
[Ik~ -I]
RsELZ
= 16kW
[I~ -I]
RSEL3
= 40kW
[Ik~ -I]
• USE5ppmI"CGAIN RESISTOR FOR lOWGAINTEMpCQ
• ALL TRIMPOTSSHOULDBE100ppmfCORBETTER
240/1
(TYPE 79PR 151URNCERMETRECOMMENDED)
Figure 2. Typical Application
Input Offset Adjustment: To null input offset voltage, an optional
10kO potentiometer may be connected across the INPUT
OFFSET ADJ. termirulis (Pins 9 and 10 in Figure 2). With
gain set at the desired value, connect both inputs (Pins I and 2)
to COMMON (Pin 16), and adjust the IOkO potentiometer for
zero volts at Pin 14. For applications using software nulling,
Pins 9 and 10 should be left unconnected.
Output Offset Adjustment: The output can be offset over the
± 10V range to compensate for dead load or bridge imbalance
as shown in
by using a SOkn potentiometer connected to Pin
Figure 2. Pin 11 is normally grounded if output offsetting is not
desired.
II
NOTE
• USE5ppml"CGAIN RESISTOR FOR LOWGAINTEMPCO
Figure 4. Wide Bandwidth Application
77-40 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
Table I gives the nearest resistor and capacitor values for several
common filter cutoff frequencies.
fcCHz)
CSEu( ....F)
CSEL2(p.F)
10
50
100
200
500
1.5
0.27
0.15
0.056
0.015
0.2
0.039
0.02
0.0082
0.0022
RSELl(kO)
R SEL2 (kO)
R SEL3 (kO)
2000
5000
10000
20000
20
4.99
2.21
1.05
16.2
4.12
1.78
0.866
40.2
10.0
4.42
2.21
A 20kO potentiometer between the REF IN and REF OUT
pins will span the +4V to + IOV excitation range. A 4.7 ....F
tantalum capacitor from REF IN (Pin 20) to COMMON (Pin
16) is recommended in all cases to lower the voltage noise at the
reference input.
lB31
Table I. Filter Cutoff Frequency vs. RSEL and CSEL
EXC ADJ
Note: The 25MHz gain bandwidth product of the IA should be
considered in high-gain, wide bandwidth configurations.
NOTE
TRIM POT SHOULD BE 100 ppml"C OR BETTER
(TYPE 79PR 15 TURN CERMET RECOMMENDED)
Voltage Excitation Programming: The excitation voltage is
preset to + IOV. To increase VEXC up to + 15V a resistor must
be connected between EXC. ADJ. and SENSE LOW (Pins 21
and 26) as shown in Figure 5. For a desired VEXC the resistor
value, R EXT , is determined by the following equations:
10kO X VREFOUT
RT = VEXC-VREFOUT
;
Figure 6. Constant Voltage Excitation: +4Vto
+ 10VRange
The remote sensing inputs should be connected to the transducer
separately from the excitation leads or jumpered as shown in
Figure 2.
Power Supply Decoupling: The power supplies should be decoupled with I ....F tantalum and 1000pF ceramic capacitors as
close to the lB3l as possible (Figure 2).
VREFOUT = +6.8V
20kO X RT
R EXT = 20kO - RT
Input Protection: The differential inputs of the IB31 can be
protected from accidental shorts to power line voltages (1l5V
rms) by the circuit shown in Figure 7. The back-to-back diodes
clamp the inputs to a maximum of ± l2.5V and were selected
for low leakage current. The l5kO resistors in series with the
inputs will degrade the noise performance of the IB31 to 4.2 ....V
p-p in a bandwidth of O.IHz to 1kHz. For six-wire load cells in
harsh environments the additional protection for the sense inputs
shown in Figure 7 is recommended.
The + 10V to + l5V range can be covered by a 20kO
potentiometer between the reference terminals.
NOTE
TRIM POT SHOULD BE 100 ppml"COR BETTER
(TYPE 79PR 15 TURN CERMET RECOMMENDED)
Figure 5. Constant Voltage Excitation:
Range
+ 10V to + 15V
To decrease V EXC down to +4V, a resistor has to be connected
between REF IN and REF OUT (Pins 19 and 20) as shown in
Figure 6. The equations to determine the value of REXT are:
VREF
IN =
430kfi 2W RESISTORS FOR 240V INPUT PROTECTION
Figure 7. 115V Input Protection for 1B31
0.68VEXC
R EXT = IOkO [VREFOUT - 1]
VREFIN
VREFOUT
+6.8V
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-41
III
PERFORMANCE CHARACTERISTICS
Input Offset Voltage Drift: Total offset voltage drift is composed
of input and output drifts and is a function of gain. The IB31
typically exhibits ±O.25ILVrC RTI drift at a gain of lOOOVN
over the full temperature range. The RTI voltage offset drift vs.
gain is graphed in Figure 8.
'00
"
u '0
S-o.
I
5c
a. Bandwidth =0. 1Hz to 10Hz
.......
I.........
i
......
o
!:i
~ 01
00'
,
'0
-1000
'00
'0.000
GAIN-VIV
Figure 8. Total Input Offset Drift vs. Gain
Low Pass Filter: The two pole Butterworth filter is a multiple
feedback design with a gain of -2VN. It is preset at a cutoff
frequency of 1kHz ( - 3dB) with a 40dB/decade roll-off. The
step response at 1kHz is 1.5ms settling time to 0.1% of final
value with less than 5% overshoot. The frequency response of
the filter is shown graphically in Figure 9.
-20
~
'"
b. Bandwidth =0. 1Hz to 1kHz
Figure 10. Voltage Noise, RTO @ G= 1000VN
Common-Mode Rejection: CMR as a function of gain and
frequency is shown in Figure 11. The best results (l4OdB @
60Hz) are obtained by programming the low pass filter with a
10Hz cutoff frequency, which contributes an additiona13OdB to
the 1kHz specification where 60Hz noise is not attenuated by
the filter.
'40
~
'"
-80
-'00
.....
I
Z
~
~
'0
f-kHz
'00
lli4lJ I
IG=:ooo~
80
, . . . .r-.
G=2VN
FILTERED OUTPUT·
~:;;
'000
:;;
8
Figure 9. Filter Amplitude Response vs. Frequency
Gain Nonlinearity and Noise: Gain Nonlinearity is specified as
a percent offull-scale output, and for the IB31 it is ±O.OO5%
maximum over the full-gain range. The IA design also offers
exceptionally quiet performance with typical input noise of
O.3ILV p-p for a 10Hz bandwidth (Figure lOa) and IILV p-p for
a 1kHz bandwidth (Figure lOb).
f--"
G=,OOOVN
RLTERED OUTPUT'
'r-. r-
Ul
II:
8'"
~
::--.
UNFILTERED OUTPUT
'00
0
~
0'
'20
60
40
20
o
,
,
'0
'00
,k
'Ok
'OOk
FREQUENCY - Hz
·1kHz CUTOFF FREQUENCY
Figure ". Common-Mode Rejection vs. Frequency and
Gain
11-42 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
Tum On Drift: The input offset of the IB31 stabilizes to within
Ill-V of final value in 5 minutes (Figure 12). The test conditions
are: 350.0 bridge with + 10V excitation and ambient temperature
of +,2S"C.
700
1\
CERAMIC PACKAGE
&DO
~
~ \
PLASTIC PACKAGE
~
L
1
I
W
3
~
2
i /
~
II:
3
V
/
v
0
~
\ \
0
V
\
SAFE OPERATING REGION
0
----.
1\
----~ - 150
II
l
-55
-25
+25
+50
+75
+100
+125
AMBIENT TEMPERATURE - "C
Figure 14. Excitation Source Internal Power Dissipation
vs. Temperature
WARM-UP TIME - Minutes
Figure 12. Offset Voltage, RTI, Turn-On Drift
Bridge Excitation: The adjustable bridge excitation is specified
over a wide regulator input voltage range ( + 9.5V to + 2SV).
Maximum load current IL as a function of regulator input-output
differential voltage is shown in Figure 13. The maximum output
current also depends on ambient temperature and above 50°C a
derating factor should be derived from Figure 14.
100
80
~
E
I
j
ACTIVE
~ I'-..
C
60
dummy gage mounted adjacent to the active gage provides temperature compensation. The rest of the bridge is completed by
the IB31 internal half-bridge network which consists of two
20kn, 1% thin-film resistors tracking to within ±SppmfC max.
Bridge excitation is set at + 4V to avoid self-heating errors from
the strain gage. System calibration produces a + I V output for
an input of 1000 microstrains. The fdter cutoff frequency is set
at approximately 100Hz.
GAGE
120n
0101000.... 1.
~I'-..
40
"'"
20
10
15
20
NOTES
• USE 5ppmI"CGAlN RESISTOR FOR LOWGAINTEMPCO
• TRIM POT SHOULD BE 100ppmI"COR BETTER
(TYPE 79PR 15 TURNCERMETRECOMMENDEDI
Figure 15. Strain Gage Application Using Internal
Half-Bridge
24 25
INPUT-OUTPUT VOLTAGE DIFFERENTIAL - V
Figure 13. Excitation Source Input - Output Voltage
Differential vs. Lt}ad Current; Ambient Temperature
s25°C.
APPLYING THE IB31
Strain Measurement: The IB31 is shown in a strain measurement
system in Figure IS. A single active gage (120.0, Gage Factor =
2) is used in a bridge configuration to detect fractional changes
in gage resistance caused by strain. An equivalent resistance
Pressure Transducer Inferface: A strain gage type pressure
transducer (Dynisco SOO series) is interfaced to a IB31 in Figure
16. Regulated excitation of + 10V dc is provided for a 30mV
full-scale output. The gain is sett at 333.3 to achieve a O-IOV
output for a 0-10,000 psi range of the transducer. A shunt calibration resistor is built into the transducer for easy verification
of the SO% point of its full-scale output. A typical shielding
scheme to preserve the excellent performance characteristics of
the IB31 is also shown. To avoid ground loops, signal return or
cable shield should be grounded only at one point.
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-43
•
COMM -15V
,-,
+15V
ivon
• USE 10ppmI"CGAlNRESISTOR FORlOWGAINTEMPCO
-v.
Figure 76. Pressure Transducer Application
Multiple Load-Cells: For transducer configurations where the
maximum load current of 100mA of the IB31 is not sufficient, a
buffer and a power transistor such as a TIP31 can be used as
shown in Figure 17. This design can supply 300mA at + 10V
excitation over the full industrial temperature range ( - 25'C to
+85OC). In a multiple IB31 system an added advantage is that
ratiometric operation can be preserved by using one excitation
source which also serves as the reference voltage for the system
AID converter.
Figure 78. NBgative Supply Generation for 7837
ADI170. In addition, fixed offsets caused by bridge imbalance
can be nulled out by the ADII70 with a power-up initialization
command from the microcomputer. This eliminates a potentiometer or software overhead which might otherwise be
needed.
v~.
(FlLTfA£OJ 14 0-10V
1831
Figure 77. Multiple Load-Cell Application
NOTES
.3mVIVLOADCELL
Mobile Transducer Application: The small size and reliability
of the IB31 make it an ideal choice for mobile applications.
Since the IB31 requires a negative supply, one possible solution
for its generation is shown in Figure 18. The positive voltage of
a + 12V battery is used to drive a CMOS TLC555 oscillator
with a typical supply current of 360j.LA. The output is a square
wave that is rectified by the diodes and filtered to provide a
- 9V supply. Excitation voltage should be equal to or less than
+9V for adequate headroom for the IB31 voltage regulator.
Pressure Transducer Data Acquisition System: Figure 19
shows a two module solution for microcomputer based data
acquisition using a IB31 and an ADI170 18-bit AID converter.
A 3mVN pressure transducer (e.g. Dynisco 800 series) is interfaced
to a IB31 set up with a gain of 333.3 to give a 0 - 5V output.
The regulated excitation is + 5V, and for ratiometric operation
it is also used as the voltage reference input for the AD1I70. An
initial ECAL command establishes the voltage excitation as the
full-scale input of the AD 1170 and periodic calibration cycles
keep the converter tracking the reference input. This configuration
yields very high CMR (168dB @ 60Hz) enhanced by the IB31
low pass filter and the integrating conversion scheme of the
• +5VEXCITATION,15mVFS
• GAIN:: 333
• USE 10ppmI"CGAINRESISTORfORLOWGAINTEMPCO
Figure 79. Pressure Transducer Data Acquisition Using
7B37 and AD 7170
Isolated Current Loop Interface: The outpUt of the IB31 can
be interfaced to a process loop as shown in Figure 20. The 2B23
module produces an isolated 4-to-20mA output current which is
proportional to the input Voltage and independent of the output
load resistance. Common-mode input/output isolation is ± 1500V
pk continuous.
71-44 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
Figure 20. Isolated 4-20mA Transmitter
Bridge Transducer
Signal Conditioner
1832 I
11IIIIIIII ANALOG
WDEVICES
1832 FUNCTIONAL BLOCK DIAGRAM
FEATURES
Low Cost
Complete Signal-Conditioning Solution
Small Package: 28-Pin Double DIP
Internal Thin-Film Gain Network
High Accuracy
Low Input Offset Tempco: :!:0.01p.VI"C
Low Gain Tempco: ±2ppml"C
Low Nonlinearity: :!: 0.005% max
High CMR: 140dB min (60Hz. G=1000VNI
Programmable Bridge Excitation: +4V to + 15V
Remote Sensing
Low Pass Filter (fc=4HzI
APPUCATIONS
Weigh Scales
Instrumentation: Indicators. Recorders. Controllers
Data Acquisition Systems
Microcomputer Analog I/O
The IB32 is fully specilled over the industrial ( - 25°C to + 85°C)
temperature range.
GENERAL DESCRIPTION
Model IB32 is a precision, chopper-based, signal-conditioning
component ideally suited for high-accuracy applications of load
cells and bridge transducers. Packaged in a compact 28-pin
plastic double DIP, the IB32 takes advantage of hybrid technology
for high reliability as well as higher channel density. Functionally,
the signal conditioner consists of three basic parts: a high performance chopper-based amplifier, a low-pass ftlter and an adjustable transducer excitation source.
The chopper-based amplifier features extremely low input offset
tempco of :!:0.07"VI"C (RTI, G=500VN) and excellent nonlinearity of ± 0.005% max over its full gain range of 100 to
5000VN. The IB32 has a thin-ftlm resistor network for pinstrapping the gain to 500VN or 333.3VN (for 2mVN and
3mVN load cells). The gain tempco for these fixed gains is a
highly stable ± 2ppmfOC. Additionally, the gain can be set to
any value in the gain range with two external resistors. The
amplifier also has a wide-range input referred zero suppression
capability (:!: I OV), which can easily be interfaced to a D/A
converter. The bandwidth of the chopper is 4Hz at G = lOOVN.
The integral three-pole, low-pass ftlter offers a 6OdB/decade rolloff from 4Hz to reduce common-mode noise and improve system
signal-to-noise ratio.
DESIGN FEATURES AND USER BENEFITS
Pin-Strappable Gain: The internal resistor network can be pinstrapped for gains of 500VN and 333.3VN for 2mVN and
3mVN load cells. The tracking network gnarantees a gain tempco
of ± 6ppmfOC max.
Custom Trimmable Network: For volume applications, the
IB32 can be supplied with a custom laser trimmed gain network.
Contact factory for further information.
Wide Range Zero Suppression: The output can be offset by
± 10V for nulling out a dead load or to do a tare adjustment.
Remote Sensing: Voltage drops across the excitation lead-wires
are compensated by the regulated supply, making 6-wire load-cell
interfacing straightforward.
Programmable Transducer Excitation: The excitation source is
preset for + 10V dc operation without external components. It
is user-programmable for a +4V to + 15V dc range (@ lOOmA)
to optimize transducer performance.
Low-Pass Filter: The three-pole active ftlter (fc = 4Hz) reduces
60Hz line noise and improves system signal-to-noise ratio.
The IB32's regnlated transducer excitation stage features low
output drift (±40ppmfOC typ) and can drive 120n or higher
resistance load cells. The excitation is preset at + 10V with
other voltages between +4Vand + 15V programmable with
external resistors. This section also has remote sensing capability
to allow for lead-wire compensation in 6-wire load cells and
other bridge configurations.
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-45
•
SPEC IFICAli 0NS (typical
Model
@
+ 250C IIHI Vs = ± 15V unless otheIwise noIad)
IB31AN
GAIN
Gain Range
Internal Gain Setting
Gain Equation
Gain Equation Accuracy'
Gain Temperature Coefficient2
Gain Nonlinearity
OFFSET VOLTAGES
Total Offset Voltage, RTI
Initial,@ +2S"C,G= lOOOVN
Warm-UpDrift,G = lOOOVN,lOmin
vs. Temperature ( - 2S"C to + 8S°C)
G= lOOOVN
At Other Gains
Output Offset Adjust Range
INPUT BIAS CURRENT
Initial@2SoC
vs. Temperature ( - 25°C to + 8S'C)
INPUT DIFFERENCE CURRENT
Initial @ + 2S"C
vs. Temperature ( - 2S'C to + 85'C)
INPUT RESISTANCE
Differential
Common Mode
INPUT VOLTAGE RANGE
Linear Differential Input
Maximum Differential Input
CMVInputRange
CMR, lkO Source Imbalance'
G= lOOVNt05000VN@dc
G= lOOVN,@60Hz
G= lOOOVN,@60Hz
INPUT NOISE
Voltage, G = lOOOVN
O.IHzto 10Hz
Current, G = lOOOVN
O.lHzto 10Hz
RATED OUTPUT
Voltage, 2kOLoad, min
Current
Impedance, de to 2Hz, G= lOOVN
Load Capacitance
Output Shon Circuit Duration (to Ground)
DYNAMIC RESPONSE
Small Signal Bandwidth
- 3dB Gain Accuracy, G= lOOVN
G=IOOOVN
Slew Rate
Full Power
Sett1ingTime,G= lOOVN, ± 10VOutpuI
Stepto ±O.I%
LOW PASS FILTER
Number of Poles
Cutoff Frequency ( - 3dB Point)
Roll-Off
OUTLINE DIMENSIONS
IOOVNto SOOOVN
333.3VN and SOOVN
1+ RF
R,
±O.I%
± 2ppmf'C (± 6ppml"Cmax)
±O.OOS%max
Dimensions shown in incbes and (nun).
r-----1-1
(3 0.15
81 MIN
--r=
086 (218IMAX
~
---1-1
I 3~~~AX
+t
(6
0 01 (0.251
--r
14
15
8
21
3
26
1
28
±0.07...VfC(±0.2 ...VfCmax)
±(0.06 +
~)"'VfC
±lOV
±3nA
±5OpAfC
164
'(41.71
MAX
±3nA
±IOpAfC
IOOMO
IOOMO
±O.IV
+5V
Oto +7.5V
BOTTOM VIEW
'-'-
-I f.- 0 05 (1 271 GRID
86dB
120dB
I40dBmin
PIN DESIGNATIONS
l ...Vp-p
3pAp-p
±IOV
±5mA
0.60
500pF
Indefinite
4Hz
3.5Hz
20V/sec
0.5Hz
2sec
3
4Hz
6OdB/decade
(Continued on next page)
11-46 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
FUNCTION
PIN
FUNCTION
+ INPUT
-INPUT
INPUT OFFSET ADJ
15
16
17
18
19
20
21
22
-V.
COMM
+V.
+V.REG
REF OUT
REF IN
EXCADJ
NC
NC
NC
NC
SENSE LOW
SENSE HIGH
VExcOUT
NC
NC
NC
NC
SlGNALCOMM
EXT GAIN SET
333.3 GAIN
500 GAIN
GAIN SENSE
GAiNCOMM
VOUT
23
24
25
26
27
28
Model
IB32AN
BRIDGE EXCITATION
Regulator Input Voltage Range
Output Voltage Range
Regulator Input/Output Voltage Differential
Output Current'
Regulation, Output Voltage vs. Supply
Load Regulation, IL = lmA to SOmA
Output Voltage vs. Temperature ( - 2SoC to + 8S°C)
Output Noise, O.IHz to 10Hz'
Reference Voltage (Internal)
Sense & Excitation Lead Resistance
+9.SVto+28V
+4Vto +ISV
+3Vto +24V
l00mAmax
±O.OS%N
±0.1%
±4Oppm/"C
300,..Vp-p
+6.8V ±S%
100 max
POWER SUPPLY
Voltage, Rated Performance
Voltage, Operating
Current, Quiescent"
± ISVdc
± l2Vto ± 18Vdc
+4mA, -lmA
ENVIRONMENTAL
Temperature Range
Rated Performance
Operating
Storage
Relative Humidity
-2S0Cto +8SoC
-4Q°Cto +8SoC
- 4Q°C to + 100°C
oto 9S%, Noncondensing, @ + 60°C
0.83" x 1.64" x 0.2S"
(21.1 x 41. 7 x 6.3Smm) max
CASE SIZE
NOTES
iUsing internal network for gain.
lFor pin-strapped gain. The tempco of the individual thin-fIlm resistors is ± 5OppmI"C max.
33V p-p 60Hz common-mode signal used in test setup.
'Derate 2mAI'"C from + sooc.
'4.7ILF capacitor from REF IN (Pin 20) toCOMM.
6Excluding bridge excitation current and with no loading on the output.
Specifications subject to change without notice.
ACl224 Connector Designation
AC1224 Mounting Card
r
4125
(104111
0
~~~~'N'U~T0'''''0
R2. 0
0
o
AC1Z24
EXCITATION ADJ
00
0 Rl
0
R4~
R5~
RS
a ..C:::J-e
g
8
0
,=='I~I
g
-c::::::::::.
8
0
3
R1
G{::::}-€l 8
g
o
o
o
o
o
o
o
o
rJ
~
---~
o
'3
I
PIN
FUNCTION
PIN
FUNCTION
T
U
V
X
VExcOUT
SENSE HIGH
SENSE LOW
REF OUT
REFIN
EXCADJ
1
2
12
19
20
21
22
+INPUT
-INPUT
V OUT
-Vs
COMM
+Vs
+VsREG
y
Z
g
g
The AC1224 mounting card is available for the 1B32. The AC1224
is an edge connector card with a socket for plugging in the
IB32. In addition it has provisions for switch selecting internal
gains as well as installing gain resistors. Adjustment pots for
offset, fme gain and excitation are also provided. The AC1224
comes with a Cinch 251-22-30-160 (or equivalent) edge
connector.
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-47
•
FUNCTIONAL DESCRIPTION
COMM
Model IB32 is based on a switched capacitor, chopper stabilized
amplifier followed by an active filter and an adjustable voltage
regulator section for excitation. The ultralow drift chopper
samples the difference between the + INPUT and - INPUT at
190Hz. The signal is modulated, amplified and then demodulated.
This stage introduces a pole with a 20dB/decade rolloff from
4Hz. The high-level signal is then filtered by a two-pole active
filter with a 4Hz cutoff frequency to give a ± lOY output. The
clock signal for the chopper is generated by an on-board
oscillator.
-15V
+15V
1000pF
As shown in Figure I, the gain can be pin-strapped by an internal
resistor network. Standard gains of 333.3 and 500 can be achieved
by this method with gain tempco of ± 6ppm/"C max:. Finally,
the offset adjust of the amplifier is input referred, and requires
a voltage input similar to the differential input voltage to implement
wide range suppression.
The bridge excitation section is an adjustable ouput, regulated
supply with an internally provided reference voltage ( + 6.8V). It
is configured as a gain stage with the output preset at + I OV.
The excitation voltage is increased by connecting a resistor
between Pins 19 and 20. Sense lines are provided to compensate
for lead-wire resistance by bringing the leads into the feedback
loop.
+INPUT
1 )----.,
V EXC OUT
-INPUT
2
SENSE HIGH
INPUT OFFSET
ADJ
Figure 2. Internal Gain Strapping
SENSE LOW
NC
NC
Nt:
Figure 3. External Gain Setting
NC
SIGNAL COMM
8
EXC AOJ
EXT GAIN SET
9
REF IN
3333 GAIN
500 GAIN
REF OUT
+V. (REG)
GAIN SENSE
+Vs
GAINCOMM
COMM
Figure 1. 1B32 Block Diagram and Pinout
OPERATING INSTRUCTIONS
Gain Setting: The differential gain of the IB32 can be either
pin-strapped or programmed externally with two resistors. The
internal thin-film gain network (Figure I) provides gains of 500
and 333.3 for standard load-cell sensitivities of 2mVN and
3mVN. This is achieved by connecting GAIN SENSE (Pin 12)
to GAIN COMM (Pin 13) and grounding Pin 10 or Pin 11
(Figure 2). The gain tempco using the internal network is an
excellent ±2ppmrc typ (±6ppmrc max).
Offset Adjustment: The input-referred offset adjust has the
same sensitivity as the inputs of the IB32. The voltage level at
INPUT OFFSET ADJ (Pin 3) is gained by the same factor as
the input signal to provide a ± 10V output adjust. Figure 2
shows an external network and potentiometer set up for a ± 7.smV
span at the input, which gives a ±2.5V (7.5mVx 333.3) output
adjust capability. Wider ranges can be choseti with the appropriate
resistor and potentiometer values.
Note: If offset adjustment is not reqUired, Pin 3 must be
grounded.
Voltage Excitation Programming: The excitation voltage is
preset to + 10V. To increase VBXC up to + 15V a resistor must
be connected between EXC ADJ and SENSE LOW (Pins 21
and 26) as shown in Figure 4.
The Vs (REG) input (Pin 18) must be raised to + 18V to satisfy
the + 3V min input-output voltage differential of the regulator.
Consult the Performance Characteristics section for safe operating
conditions of the regulator. For a desired VBXC the resistor
value, RElIT, is determined by the following equations:
To program the gain externally, two resistors are connected as
shown in Figure 3. The gain equation is:
RT
G= I + RF
RI
The gain-strapping Pins (11 and 12) and GAIN SENSE (Pin 12)
are left unconnected, effectively floating the internal network.
=
10kfl x VREFOUT
V EXC _ VREFOUT
20kfl
X RT
REXT = 20kfl
RT
;
VREFOUT
=
+6.8V
The + 10V to + 15V range can be covered by a 20kfl potentiometer
between REF IN (Pin 20) and REF OUT (Pin 19). RBXT of
11-48 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
15kO
'w·
,-
+v"
,5kfl
'wo
-v..
,N183
Figure 4. Constant Voltage Excitation: + 10V to + l5V
Range.
200kO is recommended for fine adjustment at + 10V excitation
voltage.
Similarly to decrease VEXC down to +4V, connect a 200kO
resistor and a 20kO potentiometer between Pins 19 and 20,
between SENSE LOW and EXC ADJ (Pins 26 and 21), as
shown in Figure 5.
*30kUZWRESISTORSFOR24OV INPUT PROTECTION
Figure 6. l15V Input Protection
PERFORMANCE CHARACTERISTICS
Input Offset Voltage Drift: The chopper froJ;lt end of the 1832
gives it excellent input offset stability. As shown in Figure 7, it
typically exhibits drift of ±0.07JLVrc RTI at a gain of lOOOVN
(±75JLVrc RTO). The measurement is two-point, and is taken
at - 25"C and + 85"C, which covers the specified temperature
range of the IB32.
400
~
'"
I
Ii:
;;:
300
Q
Iii
If
IL
~
200
0
...:::I
...:::I""
Figure 5. Constant Voltage Excitation: +4 to + 10V Range
A 4.7JLF tantalum capacitor from REF IN (Pin 20) to COMMON
(16) is recommended in aU cases to lower the voltage noise at
the reference input.
k"" .....
100
0
o
V
.,.;'V-
i ........
o
1000
2000
3000
4000
5000
GAIN-VN
Figure 7. Total Output Offset Orift VB. Gain
The remote sensing inputs should be connected to the transducer
separately from the excitation leads or jumpered as shown in
Figure 2. The resistance of the excitation and sense lines should
not exceed 100.
.
,.
Power Supply: The Vs REG input (Pin 18) should be connected
to + Vs (Pin 17) even if the bridge excitation section is not
used. Also the power supplies should be decoupled with IJLF
•
,
I
II
tantalum and lOOOpF ceramic capacitors as close to the 1832 as
possible (Figure 2).
Input Protection: The 1832 differential inputs can be protected
from accidental shorts to power line voltages (1l5V rms) by the
circuit shown in Figure 6. The back-ta-back diodes clamp the
inputs to a maximum of ± 12.5V and were selected for low
leakage current. The 15kO resistors in series with the inputs
will degrade the noise performance of the 1832 to 4JLV PoP
(0. 1Hz to 10Hz). When interfacing with six-wire load cells in
harsh environments, input protection for the sense inputs is also
recommended (Figure 6).
V
l/ io"'"
G :: 1000
1/
V~=,!
/
~
.
.
•,
.
,
FREQUENCY - Hz
'DO
Figure 8. Common-Mode Rejection vs. Frequency
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-49
15
.....-
L
L
L
I
10
1
o
15
10
WARM-UP TIME ·'Minut.s
20
Figure 11. Offset voltage Rn, Turn-On Drift
Figure9. Voltage Noise, O. 1Hz to 10Hz, G = 1000
Common-Mode Rejection: CMR as a function of frequency is
shown in Figure 8. Test conditions are a 3V pop common-mode
signal and lkil source imbalance. The CMR improves with
increasing gain. Note that the 4Hz filter enhances the CMR
performance above the comer frequency by attenuating the
normal-mode signal at 6OdBIdecade.
Bridge &cltation: The adjustable bridge excitation is specified
over a wide regulator input voltage range (+9.5V to +28V).
Maximum load current IL as a function of regulator input-output
differential voltage is shown in Figure 12. The maximum output
current also depends on ambient temperature, and above + 5O"C
a derating factor of 2mAI"C must be applied. The aafe operating
region for internal power dissipation vs. temperature is graphed
in Figure 13.
Gain Nonlinearity and Noise: Gain Nonlinearity is specified as
a percent of full-scale output, and for the IB32 it is ± 0.005%
max over the full span. The chopper design also offers exceptional
low-noise performance, with typical input noise of I,...V pop in
the O.IHz to 10Hz bandwidth (Figure 9).
100
"" ""
so
Low-Pass Filter: The IB32 bas three poles at 4Hz in its design.
One is introduced in the amplifier, wbHe the other two are
provided by an active Butterworth filter following the amplifier.
Total roll-off is 60dB/decade from 4Hz. The frequency response
of the filter is shown in Figure 10.
Lo
-"
40
1'-..
""
"
20
so
-.....
so
3
•
10
1.
20
2425
INPUT-OUTPUT VOLTAGE DIFFERENTIAL - V
40
Figure 12. Excitation Source Load Current VB.
Voltage Differential, $;25"C
1\
\
0
001
600
~
0
~
,
\
0,1
1
FREQUENCY-Hz
10
400
j~
100
I
Figure 10. Filter Amplitude Response VB. Frequency,
G=QW
Input~Output
..
I
.
Turn-On Drift: The IB32 offset wltage stabilizes to within
I,...V ofits final value in 10 minutes (Figure 11). The test conditions
200
r'\.
100
. 2•
are: 350n bridge with a + 10V excitation and ambient temperature
of +25"C.
''
~
SAFE OPERATING REGION
+25
+50
+76
+85
AMBIENT TEMPERATURE - "C
Figure 13. Excitation Source Internal Power Dissipation
VB. Temperature
11-50 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
APPLYING THE 1832
Pressure Transducer Interface: A strain gage type pressure
transducer (Dynisco 800 series) is interfaced to a 1832 in Figure
14. Regulated excitation of + 10V de is provided for a 30mV
full-scale output for a 0-10,000 psi range of the transducer. A
shunt calibration resistor is built into the transducer for easy
verification of the 80% point of its full-scale output. A typical
shielding scheme to preserve the excellent performance characteristics of the 1832 is also shown. To avoid ground loops,
signal return and cable shield should be grounded only at one
point.
COMM
-t5V
This configuration yields very high CMR enhanced by the IB32
low pass filter and the integrating conversion scheme of the
AD1l70.
+15V
1000pF
NOTES
• 3mVIV Load Cell
• +5V EXCItatIOn, 15mV FS
• Gam"'J]33
Figure 15. Auto-Calibrating Data Acquisition Using
1B32 and AD 1170
In addition, fIXed offsets caused by bridge imbalance can be
nulled out by the AD 1170 with a power-up initialization command
from the microcomputer. The full-scale output of the IB32 and
transducer can be normalized to the AD 1170 full scale through
the electronic calibration command ECAL. Both the offset and
full-scale correction data will then be stored in nonvolatile memory
to eliminate the need for the trim process after each power-up.
The AD 1170 eliminates a potentiometer or software overhead
which might otherwise be needed for these functions.
Figure 14. Pressure Transducer Interface
Pressure Transducer Data Acquisition System: A two module
solution for microcomputer based data acquisition using a IB32
and an AD1l70 18-bit AJD converter is shown in Figure IS. A
3mVN pressure transducer (e.g. Dynisco 800 series) is interfaced
to a IB32 configured with a gain of 333.3, to provide a 0 to SV
output. The regulated excitation is + SV, and is used as the
reference input for the AD 1170 to produce ratiometric operation.
Multiple Load-CeDs: For transducer configurations where the
maximum load current of the 1832 is not sufficient, a buffer
and a power transistor such as a TIP31 can be used as shown in
Figure 16. This approach will supply 300mA at + 10V excitation
over - 25°C to + 8SOC temperature range. In a multiple IB32
system an added advantage is that ratiometric operation can be
preserved by using the excitation voltage as the reference for the
system AJD converter.
12 §~~:::::::
Figure 16. Multiple Load-Cell Application
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-51
III
Mobile Transducer Applications: The small size lind reliability
of the IB32 make it an excellent choice for mobile applications.
Since the IB32 requires bipolar supplies, a possible circuit to
provide the negative voltage is shown in Figure 17. The CMOS
TLCSSS is powered by a + 12V battery, and typically draws
360,..A. The output is a square wave that is rectified by the
diodes and filtered to provide a - 9V supply. Excitation voltage
should be equal to or less than + 9V for adequate headroom for
the IB32 voltage regulator. Note that the IB32 will operate with
± 9V supplies as long as the excitation voltage and the output
range are less than SV.
lkll
DiPtai Output Offset Adjust: A IO-bit multiplying DAC such
as the AD7S33 can be used to control the output offset of the
IB32 as shown in Figure 18. The DAC is configured for unipolar
operation with an AD OP-07 generating a voltage output. This
O-IOVoutput is attenuated by Rl and Rsm. and superposed on
another fixed voltage deriVed from VEXC. Thus the voltage at
Pin 3 (INPUT OFFSET ADJUST) is insensitive to the tempco
of the excitation voltage since it is also used as the reference of
the DAC. For best performance Rl and R2 should track to
± SppmI"C. As an example, a ± SV output adjustment can be
obtained by using Rsm.. = 2000 for G = 500 and VEXC =
10V.
TO PIN 28
1832
VDD (+1SVI
R,
100kll
R2
200kll
R
_ VAOJ x 200k
SEL-~
Figure 18. Output Offset Adjust Using a 10-Bit DAC
Figure 17. Negative Supply Generation for 1832
DIGITAL INPUT
MSB
LSB
IIIIIIIIII
1000000001
ANALOG OUTPUT
le)
----
±O.2417S max
(±0.1 typ)
±O.OI27 max
Total Output Error
(Worst Case)
±0.0025
±O.OO4
±0.00025
±O.D!
The total worst case effect on absolute accuracy over ±10oC is
less than ±O.2S% and the 2B31 is capable of 112 LSB resolution in a 12 bit, low input level system. Since the 2B31 is conservatively specified, a typical overall accuracy error would be
lower than ±O.l% of F.S.
In a computer or microprocessor based system, automatic
recalibration can nullify gain and offset drifts leaving noise,
nonlinearity and CMR as the only error, sources. A transducer
excitation drift error is frequently eliminated by a ratiometric
operation with the system's AID converter.
Figure 1. Typical Bridge Transducer Application Using 2B31
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-73
BRIDGE EXCITATION (2B31)
The bridge excitation stage of the model 2B31 is an adjustable
output, short circuit protected, regulated supply with internally
provided reference voltage (+7.15V). The remote sensing
inputs are used in the voltage output mode to compensate
for the voltage drop variations in long leads to the transducer.
The regulator circuitry input (pin 24) may be connected to
+Vs or some other positive dc voltage (pin 28 referenced)
within specified voltage level and load current range. Userprogrammable constant voltage or constant current excitation
mode may be used. Specifications are listed below in Table J.
MODEL
Constant Voltage Output Mode
Regulator Input Voltage Range
Output Voltage Range
Reguiawr input/OutpUt voitage
Differential
Output Current'
Regulation, Output Voltage
vs Supply
Load Regulation. IL = ImA to
IL:: SOmA
2Bll)
lB31L
3Vta 24V
o to l00mA max
OOS%/V
01%
Output Voltage vs Temperature
o 015%/C max
(0 to +70°C)
Output NOise
o 003 %/° C typ
Reference Voltage (Internal)
2831K
+9.SV to +28V
+4V to +15V
1% RSEL for several common filter cutoff (-3dB) frequencies.
RSIlLl (kG)
fc (Hz)
10
SO
100
500
1000
5000
(Pin 1 to 9)
RSIlL2 (kG)
(Pin 9 to 8)
Open
Open
1270.000
523000
90000
44.200
8660
4.320
0.866
205000
80600
137.00
68.10
13 30
665
133
RSIlL3 (kG)
(Pin 8 to 6)
Open
383000
154.000
26.700
13 300
2.610
1.300
0.261
Table II. Filter Cutoff Frequency vs. RSEL
Voltage Excitation Programming: Pin connections for a constant voltage output operation are shown in Figure 2. The
bridge excitation voltage, VEXC, is adjusted between +4V to
+15V by the 20kn (50ppm/oC) RVSEL potentiometer. For
ratiometric operation, the bridge excitation can be adjusted
by applymg an external positive reterence to pin 25 ot the
2B31. The output voltage is given by: VEXC OUT = 3.265VREP
IN. The remote sensing leads should be externally connected
to the excitation leads at the transducer or jumpered as shown
in Figure 2 if sensing is not required.
ImVrms
715V±3%
Constant Current Output Mode
Regulator Input Voltage Range
Output Current Range
Comphance Voltage
Load Regulation
Temperature CoeffiCient
(0 to +70°C)
Output NOise
1
+9 5V to +28V
lOOJ..lA to lOrnA
Oto lOY
01%
0OO3%/C
IJ,LArms
Output Current derated to HmA max for 24V regulator mputloutput
voltage differential
Table I. Bridge Excitation Specifications
OPERATING INSTRUCTIONS
Gain Setting: The differential gain, G, is determined according
to the equation:
G =(1 +94kn/RG) [20kn/(Rp + 16.2kn»)
where RG is the input stage resistor shown in Pigure I and Rp
is the variable 10kn resistor in the output stage. For best
performance, the inpu t stage gain should be made as large as,
possible, using a low temperature coefficient (lOppm/oC) RG,
and the output stage gain can then be used to make a ±20%
linear gain adjustment by varying Rp.
lnput Offset Adjustment: To null input offset voltage, an optionall00kn potentiometer connected between pins 13 and
14 (Figure 1) can be used. With gain set at the desired value,
connect both inputs (pins 12 and 15) to the system common
(pin 28), and adjust the 100kn potentiometer for zero volts
at pin 3. The purpose of this adjustment is to null the internal
amplifier offset and it is not intended to compensate for the
transducer bridge unbalance.
Output Offset Adjustment: The output of the 2B3012B31 can
beintentionally offset from zero over the ±1OV range by applying a voltage to pin 29, e.g., by using an external potentiometer
or a fixed resistor. Pin 29 is normally grounded if output offsetting is not desired. The optional filter amplifier offset null
capability is also provided as illustrated in Figure 1.
Filter Cutoff Frequency Programming: The low pass filter cutoff frequency may be increased from the internally set 2Hz by
the addition of three external resistors connected as shown in
Figure 1. The values of resistors required for a desired cutoff
frequency, fe' above 5Hz are obtained by the equation below:
Figure 2. Constant Voltage Excitation Connections
Current Excitation Programming: The constant current excitation output can be adjusted between 100ilA to lOrnA by two
methods with the 2B31. Figure 3 shows circuit configuration
for a current output with the maximum voltage developed
across the sensor (compliance voltage) constrained to +5V. The
value of programming resistor RISEL may be calculated from
the relationship: RISEL = (VREG IN - VREP IN)/IEXC OUT.
This application requires a stable power supply because any
variation of the input supply voltage will result in a change
in the excitation current output.
(-t96V TO+28V~>--t-'~.,----,
(100"A TO lOmA~
19
RISH ~ (VRfG IN - VREF 1N)!IUC OUT
IEXCO\JT
VREG1N ~'~5VTO+28V
VREF IN ~ VREF OUT ~ +7
~I!i01'AI<>
lOrnA
16V
Figure 3. Constant Current Excitation
Connections (VCOMPL = 0 to +5V)
A compliance voltage range of 0 to + lOV can be obtained by
connecting the 2B31 as shown in Figure 4. The 2kn potentiometer RISEL is adjusted for desired constant current excitation output.
,~,
(l!i01'A TO lOrnA)
19
RSELI = 11.6 X 106 /(2.67fe - 4.34);
RSEL2 = 27.6 X 106 1(4.12fc - 7)
RSEL 3 = 1.05 X 106 /(0.806fe - 1.3)
where RSEL is in ohms and fo in Hz. Table II gives the nearest
11-74 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
Figure 4. Constant Current Excitation
Connections (VCOMPL = 0 to +10V)
Applying the 2830/2831
I
APPLICATIONS
Strain Measurement: The 2B30 is shown in Figure 5 in a strain
measurement system. A single active gage (120n, GF = 2) is
used in a bridge configuration to detect small changes in gage
resistance caused by strain. The temperature compensation is
provided by an equivalent dummy gage and two high precision
120n resistors complete the bridge. The 2B35 adjustable
power supply is set to a low +3V excitation voltage to avoid
the self-heating error effects of the gage and bridge elements.
System calibration produces a 1V output for an input of 1000
microstrains. The filter cutoff frequency is set at 100Hz.
wide range (-100°C to +600°C) RTD temperature measurement system. YSI - Sostman four-wire, lOOn platinum RTD
(PT139AX) is used. The four wire sensor configuration, combined with a constant current excitation and a high input impedance offered by the 2B31, eliminates measurement errors
resulting from voltage drops in the lead wires. Offsetting may
be provided via the 2B31 's offset terminal. The gain is set by
the gain resistor for a +10Voutput at +600°C. This application requires a stable power supply.
-15V
+15V
Figure 7. Platinum RTD Temperature Measurement
Figure 5. Interfacing Half-Bridge Strain Gage Circuit
Pressure Transducer Interface: A strain gage type pressure
transducer (BLH Electronics, DHF Series) is interfaced by the
2B31 in Figure 6. The 2B31 supplies regulated excitation
(+10V) to the transducer and operates at a gain of 333.3 to
achieve 0-10V output for 0-10,000 p.s.i. at the pressure transducer. Bridge Balance potentiometer is used to cancel out any
offset which may be present and the Fine Span potentiometer
adjustment accurately sets the full scale output. Depressing
the calibration check pushbutton switch shunts a system calibration resistor (ReAL) across the transducer bridge to give an
instant check on system calibration.
Interfacing Three-Wire Sensors: A bridge configuration is particularly useful to provide offset in interfacing to a platinum
RTD and to detect small, fractional sensor resistance changes.
Lead compensation is employed, as shown in Figure 8, to
maintain high measurement accuracy when the lead lengths are
so long that thermal gradients along the RTD leg may cause
changes in line resistance. The two completion resistors (R1,
R2) in the bridge should have a good ratio tracking (±5ppm/0 C)
to eliminate bridge error due to drift. The single resistor (R3)
in series with the platinum sensor must, however, be of very
high absolute stability. The adjustable excitation in the 2B31
controls the power dissipated by the RTD itself to avoid
•
self-heating errors.
COM
-15V
COM
OTO
+10V
Figure 8. Three-Wire RTD Interface
Figure 6. Pressure Transducer Interface Application
Platinum RTD Temperature Measurement: In Figure 7 model
2B31 provides complete convenient signal conditioning in a
Linearizing Transducer Output: To maximize overall system
linearity and accuracy, some strain gage-type and R TO transducer analog outputs may require linearization. A simple circuit may be used with the 2B31 to correct for the curvature
in the input signal as shown in Figure 9. The addition of feedback in the excitation stage will allow for the correction of
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
11-75
nonlinearity by the addition of two components. The sense
of the feedback is determined by whether the nonlinearity
is concave upward or concave downward Gumper A to pin 21,
or to pin 25). The magnitUde of the correction is determined
by the resistor, RSEL, and the linearity adjust pot provides
a fine trim.
If an RTD is to be used, the adjustment can be made efficiently, without actually chapging the temperature, by
simulating the RTD with a precision resistance decade. The
offset is adjusted at the low end of the resistance range, the
fine span is adjusted at about one third of the range, and
the linearity is adjusted at a resistance ~orresponding to
full-scale temperature. One or two iterations of the adjustments will probably be found necessary because of the
interaction of linearity error and scale-factor error. This
circuit's applications are not restricted to RTD's; it will
work in most cases where bridges are used - e.g., load cells
and pressure transducers.
offer also an excellent voltage noise performance by guaranteeing maximum RTI noise of 1p.V POp (G =1000VIV, Rs "
Skn) with noise bandwidth reduced to 2Hz by the LPF.
Common Mode Rejection. CMR is rated at ±10V CMV and
1kn source imbalance. The CMR improves with·increasing
gain. As a function of frequency, the CMR performance is enhanced by the incorporation of low pass filtering, adding to
the 90dB minimum rejection ratio of the instrumentation amplifier. The effective CMR at 60Hz at the ourput of the fllter
(fc = 2Hz) is 140dB min. Figure 11 illustrates a typical CMR
vs. Frequency and Gain.
~
'40
~ '"
~
.i
BRIDGE COMPLETION
RElUSTORSSHOULD BE
~
:tOQn.&ppmrc
FOftBEST PERFOAMANCE
8
OUTPUT
o TO+1OV
FREQUENCY _ Hz
"ro
""'"
FINE SPAN
""""
~TES
Figure ". Common-Mode Rejection VB. Frequencyand Gain
ORREeTION
GAOE TYPE TRANSDUCERS
Figure 9. Transducer Nonlinearity Correction
PERFORMANCE CHARACTERISTICS
Input Offset Voltage Drift. Models 2B3012B31 are available
in three drift selections: ±O.S, ±1 and ±3p.V/oC (max, RTI, G =
1000VIV). Total input drift is composed of two sources (input
and output stage drifts) and is gain dependent. Figure 10 is a
graph of the worst case total voltage offset drift vs. gain for
all versions.
,~
"~
I II
I II
M-:~~,~JRIFT LIMIT
"
2830J12B31J (16Oj.vfc)
.
r---
1"-
i"-
f!,
MODEL2B3OJI2B3!)
~~
i'i I'j"'-'i
TO!'LI~PtJ!
~R!FT -1
, :1:.[
,
L
OUTPUT DRIFT. G .. lK
±
"
MAX INPUT DRIFT LIMIT
I I
I
t'jVfF'
1"~LJ283ILf' iYI
G.
'"
"
.0" l000v1V
10
~ ~L.J~
,
~
'00
FREQUENCY - Hz
r-
",
,o
Ii
10
16
20
25
INPUT-OUTPUT VOLTAGE DifFERENTIAL - V
2B3OJ/2B31J13pV/·CI
OUTPUT DRIFT.a .. , ]
'000
H'H~-
-70
-
,
'00
.a,
......2B30K/2B31K
B3'L
l".
...
'""'t-r- Jll
MrOEL 12Bf~~B3tK
,
11
11 I
1\
['\ ~ ~ ~.:=~~7~:jrl)
,
•
,
,
Low Pass Filter. The three pole Bessel-type active filter attenuates unwanted high-frequency components of the input signal above its cutoff frequency (-3dB) with 60dB/decade rolloff. With a 2Hz filter, attenuation of 70dB at 60Hz is obtained,
settling time is 600ms to 0.1% of final value with less than 1%
overshoot response to step inputs. Figure 12 shows the filter
response.
~I
10002000
I
10,000
GAIN-VIV
Figure 10. Total Input Offset Drift (Worst Case) vs. Gain
Gain Nonlinearity and Noise. Nonlinearity is specified as a percent of full scale (lOV), e.g. 0.2SmV RTO for 0.0025%. Three
maximum nonlinearity selections offered are: ±0.002S%,
±O.OOS% and ±0.01%'(G =1 to 2000VIV). Models 2B3012B31
Figure 12. Filter Amplitude
Response vs. Frequency
Figure 13. Maximum Load
Current vs. Regulator InputOutput Voltage Differential
Bridge Excitation (2B31). The adjustable bridge excitation is
specified to operate over a wide regulator input voltage range
(+9.SV to +28V). However, the maximum load current is a
function of the regulator circuit input-output differential voltage, as shown in Figure 13. Voltage ourput is short circuit
protected and its temperature coefficient is ±O.OlS% VOUTt"C
max (±0.003%t"C typ). Output temperature stability is directly
dependent on a temperature coefficient of a reference and for
higher stability requirements, a precision external reference
may be used.
11-76 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
Isolated, Thermocouple
Signal Conditioner
r'IIII ANALOG
WDEVICES
2850
FEATURES
Accepts J. K. T. E. R. S or B Thermocouple Types
Internally Provided Cold Junction Compensation
High CMV Isolation: ±1500V pk
High CMR: 160dB min @ 60Hz
Low Drift: ±1p.VI"C max (2850B)
High Linearity: ±0.01% max (2850B)
Input Protection end Filtering
Screw Terminal Input Connections
I
2B50 FUNCTIONAL BLOCK DIAGRAM
ISOLATED
POW'R
+VOUT
~VOUT
OUTPUT OFFSET
ADJUST
"
APPLICATIONS
Precision Thermocouple Signal Conditioning For:
Process Control and Monitoring
Industrial Automation
Energy Management
Data Acquisition Systems
• f+
1NPUTl_
SENSOR
OUT"
SENSOR
IN
CJC SENSOR
J
K,T
X
,~
PROGRAMMING
OPEN INPUT
DETECTION
COM
W
OSC
~
OSCILLATOR
POWER
GENERAL DESCRIPTION
The model 2BSO is a high performance thermocouple signal
conditioner providing input protection, isolation and common
mode rejection, amplification, filtering and iIltegral cold junction compensation in a single, compact package.
The 2BSO has been designed to condition low level analog
signals, such as those produced by thermocouples, in the presence of high common mode voltages. Featuring direct thermocouple connection via screw terminals and internally provided
reference junction temperature sensor, the 2BSO may be jumper programmed to provide cold junction compensation for
thermocouple types J, K, T, and B, or resistor programmed for
types E, R, and S.
I
The high performance of the 2BSO is accomplished by the use
of reliable transformer isolation techniques. This assures complete input to output galvanic isolation (±lSOOV pk) and
excellent common mode rejection (160dB @ 60Hz).
Other key features include: input protection (220V rms),
futerin& (NMR of 70dB @ 60Hz), low drift amplification
(±lp.Vf'C max - 2BSOB), and high linearity (±0.01% max2BSOB).
In thermocouple temperature measurement applications, outstanding features such as low drift, high noise rejection, and
lSOOV isolation make the 2BSO an ideal choice for systems
used in harsh industrial environments.
DESIGN FEATURES AND USER BENEFITS
High Reliability. To assure high reliability and provide isolation protection to electronic instrumentation, the 2BSO has
been conservatively designed to meet the IEEE Standard for
transient voltage protection (472-1974: SWC) and provide
220V rms differential input protection.
High Noise Rejection: The 2BSO features internal filtering
circuitry for elimination of errors caused by RFI/EMI, series
mode noise, and SOHz/60Hz pickup.
Ease of Use, Internal compe~sation enables the 2BSO to be
used with seven different thermocouple types. Unique circuitry offers a choice of internal or remote reference junction
temperature sensing. Thermocouple connections may be
made either by screw terminals or, in applications requiring
PC Board connections, by terminal pins.
Small Package: 1.S" X 2.S" X 0.6" size conserves board space.
APPLICATIONS
The 2BSO has been designed to provide thermocouple signal
conditioning in data acquisition systems, computer interface
systems, and temperature measurement and control instrumentation.
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-77
•
SPECIFICATIONS
(typical @
MODEL
INPUT SPECIFICATIONS
Thermocouple Types
Jumper Configurable Compensation
Resistor Configurable Compensation
Input Span Range
Gain Range
Gain Equation
Gain Error
Gain Temperature Coefficient
Gain Nonlinearity'
Offset Voltage
Input Offset (A.djustable to Zero)
vs. Temperature
vs. Time
Output Offset (Adjustable to Zero)
vs. Temperature
Total Offset Drift
Input Noise Voltage
O.OlHz to 100Hz, Rs = lkn
Maximum Safe Differential Input Voltage
CMV, Input to Output
Continuous, ac or de
Common Mode Rejection
@ 60Hz, lkn Source Unbalance
Normal Mode Rejection @ 60Hz
Bandwidth
Input Impedance
Input Bias Current2
Open Input Detection
Response Time3 , G = 2S0
Cold Junction Comiensation
Initial Accuracy
vs. Temperature' (+SoC to +4S°C)
OUTPUT SPECIFICATIONS
Output Voltage Range6
Output Resistance
Output Protection
POWER SUPPLY
Voltage
Output ±Vs (Rated Performance)
(Operating)
,
Oscillator +Vosc (Rated Performance)
ENVIRONMENTAL
Temperature Range, Rated Performance
Operating
Storage Temperature Range
RFI Effect (SW @470MHz@ 3ft)
Error
PHYSICAL
Case Size
= ± 15V unless otherwise noted)
+ 25°C and Vs
2BSOA
OUTLINE DIMENSIONS
2BSOB
Dimensions shown in inches and (rom).
~_
J, K, T, or B
R, S, or E
±SmV to ±lOOmV
SOV/V to lOOOVIV
1 + (200kn/RG)
±0.2S%
±3Sppm/oC max
±0.02S% max
'51
L
(38 35)
1
±2Sppm/C max
±0.01% max
D~~~,~~~
2850A
E+
ISOLATED THERMOCOUPLE
CONDITIONER
I
251163.75)---_-1
~50;.:V
±2.Sj1VtC max
±1.Sj1V/month
±lOmV
±30j1V/oC
±(2.S +
~)
020IS.OS)
±ljJ.vfc max
M
j1V/C
lj1V pop
220V rms, Continuous
1- •.60.
±lSOOV pk max
l60dB min
70dB min
de to 205Hz (-3dB)
100Mn
±SnA
Downscale
1.4sec
±O.SoC
±O.OloC/oC
±SV@±2mA
O.ln
Continuous Short to Ground
H)
INPUT
LO
INPUT
:
11111111111111111111111'1'11
44
PIN DESIGNATIONS
,
••
,.••
o to +70 o C
,.
1.S" X 2.S" X 0.6"
NOTES
·Specifications same as 2BSOA.
nonlinearity is specified as a percentage of output signal span representing peak deviation from the
best straight line; e.g., nonlinearity at an output span of IOV pk-pk (±SV) is ±O.Ol% or ±lmV.
2 Does not include open circuit detection current of ZOnA (optional by jwnper connection).
3 Open input resPonse time is dependent upon gain.
4 When used with internally provided CJC sensor.
5 Compensation error contributed by ambient temperature changes at the module •
• Output swing of ±IOV may be obtained through output scaling (Figure 5).
1 Gain
Specifications subject to change without notice.
11-78 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
FUNCTION
PIN
±lSV de ±10% @ ±O.SmA
±12V to ±18V de max
+13V to +18V@ lSmA
±O.S% of Span
,.
BOTTOM VIEW
-II-~~~ (2.54) GRIO
WEIGHT 45G
NOTE· TERMINAL PINS INSTALLED ONL V IN
SHADED HDLE LOCATIONS
2
3
-2SoC to +8SoC
-SSoC to +8SoC
I
115.3tU-j
INPIITI a
I P THI
R
R ICOM
6
7
+V ISO OUT
-v ISO OUT
11
12
13
15
,.,
6
'7
2.
OUTPUT OFFSET
ADJUST
OUTPUT 5CJ>LE
OUTPUT
OUTPUT COM
+
-
PIN
FUNCTION
,.
'3
2'
26
27
2.
29
3.
31
32
33
34
35
36
+vase
OSCCOM
.,
39
40
4
42
43
44
OPEN INPUT DET
X } TTYPE
~. T PROGRAMMING
CJCs
RI
MATING SOCKET:
AC121S
Applying the 2850
I
FUNCTIONAL DESCRIPTION
The internal structure of the 2B50 is shown in Figure 1. An
input filtering and protection network precedes a low drift,
high performance amplifier whose gain is set by a user supplied
resistor (RG ) for gains of 50 to 1000V IV. Isolated power is
brought out to permit convenient adjustment of the input offset voltage, if desired.
ISOLATED
POWER
+VOUT
OUTPUT OFFSET
ADJUST
-VOUT
Two sets of parallel thermocouple input connections are provided. The thermocouple input may be connected by screw'
terminals (input +, Input -) or to terminal Pins 1 (-) and
2 (+) in cases where thermocouples are to be remotely termi·
nated. The following sections describe a basic thermocouple
application, as well as detail some optional connections to en·
hance performance in more demanding applications. Jumper A
(Figure 2) is used to disconnect cold junction compensation
circuitry during offset adjustments.
INTERCONNECTION GUIDELINES
All power supply inputs should be decoupled with lpF capacitors as close to the unit as possible. Any jumpers installed
for programming purposes should also be installed as close as
possible to minimize noise pickup effects.
Since the oscillator section of the 2B 50 accounts for most
of the power consumption but can accept a wide range of
voltages (+13V to +18V), it may be desirable to power this
section from a convenient source of unregulated power.
, f+
INPUTl_
SENSOR SENSOR
OUT
IN
'f
J
~
I
CJC SENSOR
K,T X
"fTVPE
PROGRAMMING
OPEN INPUT
DETECTION
OSC
COM
DSC
~
OSCILLATOR
POWER
Figure 1. 2B50 Functional Block Diagram
Internal circuitry provides reference junction compensation.
An integral reference junction sensor is provided for direct
thermocouple connections, or an external reference sensor
(2N2222 transistor) may be used in applications having remote
thermocouple termination. Compensating networks for
thermocouple types J, K, and T are built into the 2B50. A
fourth compensation (X) may be programmed with a single
resistor for any other thennocouple type. The 2B50 can be
programmed for uncompensated output when used with
inputs other than thermocouples.
Transformer coupling is used to achieve stable, reliable input
to output galvanic isolation, as well as elimination of ground
loop error effects.
Nonnally, the full scale output of the 2B50 is ±5V. However,
with the addition of an external resistive divider, the output
buffer amplifier may be scaled for a gain of up to 2, providing
a full scale output swing of ±lOV.
OPERATING INSTRUCTIONS
The connections shown in Figure 2 are common to most applications using the 2B50, and, in many cases, will be all that is
required.
If the same supply is to be used for both amplifier and oscil·
lator circuitry, the power supply returns should be brought
out separately so that oscillator power supply currents do not
flow in the low lead of the signal output. In either case, a
lpF capacitor must be connected from +VOSC (Pin 28) to
Oscillator COM (Pin 29).
The oscillator and amplifier sections are completely isolated;
therefore, a dc power return path is not required between the
two power supply commons.
GAIN SETTING
The gain of the 2B50 is set by a user-supplied resistor (RG)
connected as shown in Figure 2. Gain will normally be selected
so that the maximum output of the signal source will result in
a plus full scale output swing. The resistor value required
is detennined by the equation: RG = 200kil/(G-l).
A series trim on the gain setting resistor can be used to trim
out the resistor tolerance and module gain error (Figure 3).
Since addition of a series resistance will always decrease gain,
the value of the gain·setting resistor should be selected to provide a gain somewhat higher than the desired trimmed gain. A
good quality (e.g., lOppmtC), metal-film resistor should be
used for RG, since drift of RG will add to the overall gain
drift of the 2B50. A cennet pot is suitable for the trim. Note
that a minimum gain of 50 is required for guaranteed operation.
RG
...._
@~'---_
I
!!
: i
Figure 2. Basic 2B50 Application
COM
Figure 3. Gain Adjustment
INPUT AND OUTPUT OFFSET ADJUSTMENTS
The 2B50 has provisions for adjusting input and output offset
errors of the module. None of the offset adjustments will affect drift performance, and adjustments need not be used
unless the particular application calls for lower offsets than
those specified.
Connections for offset adjustments are shown in Figure 4.
Isolated supply voltages are brought out for input trimming
convenience only and are not for use as a power supply for
external components.
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-79
III
Type B thermocouples are unique, in that they have almost
no output in the +SoC to +4S oC range, and, therefore, do not
require cold junction compensation at all. To accommodate a
type B thermocouple, resistor Rx must be left open. Error due
to cold junction temperature will be less than ±1°C for any
measurement above 260° C. In the measurement range above
lOOOoC (where type B thermocouples are normally used) the
error will be less than ±0.3° C.
(AI
(BI
'f Type
Rx (kil)
E
R,S
B
1.87
19.6
Open
Figure 4. (A) Input and (B) Output Offset Adjustment
Table I. Compensation Values for Therrnocouple Types E,
R,Sand B
OFFSET CALIBRATION
1. Short Input + and Input - together.
2. Disconnect cold junction compensation circuitry by
removing Jumper "A" (Figure 2).
3. Adjust input offset trim P()t (±250jN range, RTI) to
zero output while operating at the desired gain. In most
applications, adjustment of the input offset alone will be
sufficient. Output offset adjustment (±30mV range) may be
performed if it is desired to adjust output offset on the
nonisolated side.
REMOTE REFERENCE SENSING
In applications requiring termination of thermocouple leads
at a point located remotely from the 2B50, with connections
brought to the 2B50 (Pins 1, 2) by copper wires, reference
temperature sensing at the remote location will be necessary.
The 2B50 has provisions for connection of a 2N2222 transistor (metal can version) for use as a reference junction
sensor. The connections are shown in Figure 6. The remote
sensing transistor is calibrated by adjusting ReAL to obtain
the value of VeAL as specified in Table II.
OPEN INPUT DETECTION
Connecting the open input detection pin (Pin 39) to Input
High (Pin 2) creates a 20nA bias current which will provide a
negative overscale response if the input is opened, or in case
of thermocouple "burn out". The speed at which this occurs
is dependent on gain, with a typical response time of 1.4sec
@ G = 250. For positive upscale response, connect a 500Mil
resistor between +VISO (Pin 8) and Input Hi (Pin 2).
(Example: VeAL = 570.0mV @ 25°C)
m.r~p:
2N2222 I
.
"
(
~+---~
.~cu
~Cu
I
I
REMOTE
RJ~~~~~~E
OUTPUT SCALING
With the output scale (Pin 16) connected to the output (Pin
17), the full scale output range is ±5V and the total gain is
equal to the gain set by RG. F or applications requiring a full
scaJe output of ±10V, a resistive divider may be connected
to provide a gain of 2 at the output amplifier (see Figure 5).
In this configuration, total gain will be twice the gain set by
RG" Output gains greater than 2 cannot be used.
-
-
.J
......_ - { . ,
'----_-..I
Figure 6. Remote Reference Junction Sensing
Sensor Temp (0C)
5
10
15
20
25
30
35
40
45
>--_---±10VOUT
,Okf!
10kn
veAL (mV)
616.5
604.9
593.3
581.6
570.0
558.4
546.8
535.1
523.5
(Values may be interpolated)
Figure 5. Output Scaling Connections
COLD JUNCTION COMPENSATION
The 2B50 may be programmed to provide cold junction
compensation for types J, K and T thermocouples by connecting a jumper from Input Low (Pin 1) to the appropriate
programming points (Pin 42 for J, Pin 41 for K or T). To
compensate other themocouple types, a resistor (Rx) is connected from the "X" programming point (Pin 40) to Input
Low (Pin 1). Table I shows the appropriate Rx values for
types E, R, and S. Rx should be a 50ppm/C, 1% tolerance
resistor.
.... -
Table II. Calibration Voltages vs. Sensor Temperature
Proper sensor placement is important. Close thermal contact
of the sensor and thermocouple termination point (reference
junction) is essential for accurate operation of the 2B50. The
sensor may be placed any distance from the 2B50. When the
sensor leads are more than ten feet long, or in the presence of
,strong noise signal sources, shielded cable should be used.
11-80 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
Four-Channel, Isolated
Thermocouple/mV Conditioners
1IIIIIIII ANALOG
WDEVICES
2854/2855
FEATURES
Low Cost Per Channel
Wide Input Span Range: ±5mV to ±100mV (2854)
±50mV to ±5V (2B55)
Pin Compatible with 2834 RTD Conditioner
High CMV Isolation: ±1000V dc; CMR = 156dB min @ 60Hz
Low Input Offset Voltage Drift: ±1/lVfC max (2B54B)
Low Gain Drift: ±25ppmfC max (2B54B)
Low Nonlinearity: ±0.02% max (±0.012% typ)
Normal Mode Input Protection (130V rms) and Filtering
Channel Multiplexing: 400 chan/sec Scanning Speed
Solid State Reliability
I
2854/2855 FUNCTIONAL 8LOCK DIAGRAM
HI
R. {i8)ii--f---4":""-..l
RG/COM
®f-:::-.I..------j
LOIOFS
R.
RG/COM
LOIOFS
APPLICATIONS
Multichannel Thermocouple Temperature Measurements
Low and High Level Data Acquisition Systems
Industrial Measurement and Control Systems
GENERAL DESC~IPTION
Models 2BS4 and 2BSS are low cost, high performance, fourchannel signal conditioners. Both models are functionally
complete, providing input protection, isolation and common
mode rejection, multiplexing, fihering and amplification.
The 2BS4 has been designed to condition low level signals
(±SmV to ±IOOmV),like those generated by thermocouples
or strain gages, in the presence of high common mode voltages.
The 2BSS is optimized to condition ±SOmV to ±SV or 4 to
20mA transmitter signals as inputs. The four-channel structure
of both models results in significant cost and size reduction.
The high performance of the 2BS4 and 2BSS is accomplished
by the use of reliable transformer isolation techniques and an
amplifier-per-channel architecture. Each of the input channels
is galvanically isolated (±IOOOV dc) from the other input
channels and from output ground. The amplifier-per-channel
structure is used to obtain low input drift (±Ip.Vf C max,
2BS4B), high common mode rejection (lS6dB ® 60Hz), and
very stable gain (±2Sppm/oC max). Other key features include
low input noise (Ip.V p-p),low nonlinearity (±0.02% max)
and open-thermocouple detection (2BS4).
APPLICATIONS
Models 2BS4 and 2BSS were designed to serve as a superior
alternative to the relay multiplexing circuits used in multichannel data acquisition systems, computer interface systems,
process signal isolators, and temperature measurement and
control instrumentation. Advantages over relay circuits include
functional versatility, superior performance, and solid state
reliability. Both models are also pin compatible with the
2B34, four-channel RTD/strain gage conditioner.
In thermocouple temperature measurement applications, outstanding low drift, high noise rejection, high throughput and
IOOOV isolation make the 2BS4 a natural choice over flying
capacitor multiplexers in conditioning any thermocouple type.
When cold junction compensation is required in measurement
of temperature with thermocouples, the 2B54 may be used
directly with the model 2B56 Universal Cold Junction Compensator.
DESIGN FEATURES AND USER BENEFITS
High Reliability. To assure high reliability and provide isolation protection to electronic instrumentation, reliable transformer isolation and solid state switching are used. Both
models have been conservatively designed to meet the IEEE
standard for Transient Voltage Protection (472-1974:SWC)
and offer 130V rms normal mode input protection.
High Noise Rejection. To preserve high system accuracy in
electrically noisy industrial environments, the 2BS4 and 2B55
provide excellent common mode noise rejection, RFI/EMI
immunity, and low pass filtering for rejection of series mode
noise and 50Hz/60Hz pickup.
~se of Use. Th~ mu!tichan,?el, functionally complete design
m a compact (2 X 4 X 0.4 ) module, assures ease of use, conserves board space and eliminates the need for a number of
discrete components necessary in relay multiplexing circuits.
Low Cost. The 2B54 and 2B55 offer the lowest cost per channel for isolated, solid. state, low level signal conditioners.
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-81
•
SPECIFICATIONS
(typical @ +25"C and Vs = ± 15V and Vosc
1B54A
Model
1B54B
=+15V, unless oIheJWise noted)
OUTLINE DIMENSIONS
1B55A
Dimensions shown in inches and (mm).
ANALOG INPUTS
Number of Channels
Input Span Range
Gam Equation
4
tSmV to ±l00mV
G= 1 + IOkn/ft(;
to.2% max (G = SO to 300) ...
±I% max (G = (000)
Gam Error
±3SppmfC max
±25ppmfC max
±O.03" max (G = SO to 300) ±o.02% mu(±O 012% typ)
Gam Temperature Coefficient
Gam Nonlinearity 1
to.03% (G '" 1000)
Offset Voltage
Input Offset, lmnal (Adj. to Zero)
vs Temperature
vs Tune
Output Offset (Adjustable to Zero)
vs. Temperature
±20",Vmax
±2 SJlVfC max
±! SJlV/month
±12mVmax
±SOIlVfCmax
I
lin\
...
...
Input NOise Voltage
OOlHz -100Hz, RS = lkn
CMV. Channel-to-Channel or
Channel-to-Ground
Contmuous. ac, 60Hz
ContlOuoUS, ae or de
Common Mode Rejection
RS .. 100n.l;;,sOHz
Rs" lOon. I;;' SOHz
Normal Mode Input. Without Damage
Normal Mode ReJection, @'60Hz
Input Resistance, Power On
Power Off
Input Bias Current
ANALOG OUPUT
Output Voltage Swmg2
Output NOise, dc - 100kHz
Oc.tput ReSIStance
Direct Output
SWitched Output
.LI n
to 2% max (G "" 1 to 100)
NA
±25ppmf C max
±O.02% max (G = 1 to 100)
NA
I
±~IoIv+~)Jlvfc
t
402
I~Vp·p
11021)
55
IS6dB mm (G = 1000)
128dB min (G = SO)
BOV rms, 60Hz
SSdB min (G = (000)
lOOMn
3Sknmm
+8nAmax
14SdB min (G = 100)
110dB mm (G= 1)
SSdBmm(G=l00)
74kO mm
:ici~~~5~ ~
2Smsmax
400 chan/sec mm
3Vmax
TERMINAL PINS INSTALLED ONLY IN SHADED
HOLE LOCATIONS
2854/2855 PIN DESIGNATIONS
PIN
FUNCTION
:--j
..
~ ~~
IELECTCH 0
3
DIRECT
7 SENSE
±lSV dc ±IO%
±12V to ±18V de max
+13 SV to +24V
+26V
8
9 OFS AO.I
11
!OO~VNRTO
I~VNRTI
Oto +70°C
-25°C to +85° C
_55°C to +8SoC
Oto 85%
2" X 4"XO.4"
tOUTf'UT
-Vt
~: ~
IS]
..
~~
±4mAmax
40mAmax
I-011254IGRIO
NOTES
e
CASE SIZE
MAX
7S0V rms
±1000V pk max
3Sn
POWER SUPPLV
Voltage
Output ±VS (Rated Performance)
(Operatmg)
Oscillator ...VOSC
(Rated Performance)
Absolute max "'Vose
Current
Output ±VS '" ±1SV
Oscillator "'Vose = ... lSV
Supply Effect on Offset
Output±Vs
Oscillator +Vase
ENVIRONMENTAL
Temperature
Rated Performance
Operanng
Storage
Relatlve Humidity
Non-COndensmg to +400 C
T
±SOIlVmax
oHl
to
l'~~:4I
LoZHi 11 MAX
±SV@±SmA
O.8mVp-p
CHANNEL SELECTION
Channel Selectton Tune to
01% FS
Channel Scanrung Speed
Channel Select Input Reverse Voltage
Ratmg
O~I~II
!l101Vfc max(±O SJlVfC typ) !SJlV/oC max
%1:' >+G)~VI c
Towl OffK[ Dnft (RTO, max
I--- '01'" IIMAlC----I.1
±5OmVto ±SV
......
SELECT eH C
40
~l
42
RalCOM
LOIOFS
V-OUT
V+OUT
....
.
....
a
liZ
sa
::
:}SELECTCHB
}SYNe
RoICOM
LOIOFS
V-OUT
V+OUT
}6ELECTCH A
"
CHANNEL B
J
HI
19
....
~ ~OICPOWER
}
M
.,
tz
CHANNEL A
AalCOM
LOIOFS
V-OUT
V..-OUT
....
"
to
"
I':
....... :.r
. ".
}
7 HI
I;;
I;;
fUNCTION
38
"HI
60
61
"
~
PIN
•
H'
..
70
11
RalCOM
LOIOFS
V-OUT
.. R.
CHANNEL C
}
CHANNEL 0
72 V+OUT
NOTBS
'spcCJfIQuonssunc as 2BS4A.
I Guo aoDbnearity I. apectfied as. percmtap of output signal span rcpreseotin, peak de¥lttion
from the best straipt bae,e ,. nonlinearity at an output span of lOY pk-pk (:I:5V) II ±O.oZ% or ±1mV
I
AC1215 OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Protected for shorts to ground and/or either supply voltqe.
Specd'icatloDS subJect to change without notICe.
MOUNTING CARDS
AC1215, AC1216
The AC121S and AC1216 mounting cards are available to asSlst in evaluation of the
2BS4 and 2BSS. These 4112" X 6" printed circuit edge connector cards have sockets
that allow a 2BS4/2BSS and 2BS6 to be plugged directly onto them, as well as offset
adjustment pots, and address decoding circuitry. The AC121S and AC1216 differ only
in input signal connections: the AC121S includes a screw terminal block and AC1216
has an edge connector.
11-82 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
Mating Connector,
Cinch 251-22-30-160 or equivalent.
Understanding the 285412855 Isolated Conditioners
FUNCTIONAL DESCRIPTION
The internal structure of the 2B5412B55 is shown in Figure 1.
Four individually isolated input channels are multiplexed into
a single output buffer, with the desired channel selected by
control inputs SELECT A through SELECT D. Isolated power
and timing signals for the input channels are provided by an
internal oscillator.
Each channel contains an input protection and filtering network and a low-drift amplifier whose gain is set by a usersupplied resistor (H(;). Additional filtering is provided in the
amplifier circuit. This structure preserves signal integrity by
taking all signal gain ahead of the isolation and multiplexing
circuits. The isolated power supply for each channel is brought
out to permit convenient fine adjustment of the input offset
voltage if desired.
Transformer coupling is used to achieve stable, reliable galvanic
isolation of each channel from all other channels and from output ground. Although the bandwidth of the input channels is
small (<2Hz at high gains) to provide immunity to normalmode noise, the multiplexing technique allows the channels
to be scanned at a high rate (400 channels/sec). Thus a high
revisitation rate is maintained even in systems with a large
number of input channels.
The outpUt buffer amplifier operates at unity gain with feedback provided by an external connection from the DIRECT
output to the SENSE input. The DIRECT output provides a
±5V swing with low source resistance to permit error-free
operation with heavy loads. In addition, a separate seriesswitched output with an active-low enable control is provided
so that multiple modules may be combined without the use of
external analog multiplexers. An offset trim point which does
not affect drift is also provided on the output channel.
2B5 5 's are used or when a system clock is present.
The 2B54 and 2B55 share the same design, differing only in
input specifications and filter characteristics.
OPERATING INSTRUCTIONS
The connections shown in Figure 2 are common to most
applications of the 2B5412B55, and in many cases will be all
that is required. The following sections describe this basic
application and also detail some optional connections which
enhance the module's utility in more complex applications.
,
SIGNAL} OUTPUT
COM
r+-----
-15V
I-"'-+....="'--l....-
+15V
OUTPUT
} POWER
SELECT
•
r
C
B
r
A
""
15
"LECT
:
1/274LS139
}
CHANNEL
SELECT
20
35
LOGIC
COMMON
OPTIONAL
GUARD TRACK ON PCB
*OOTTED CONNECTIONS SHOWN FOR
SEPARATE OSCILLATOR SUPPLY IF USED
Figure 2. 8asic 2854/2855 Application
Interconnection Guidelines
In any high accuracy isolator application it is important to
minimize coupling between input and output, and the 2B54/
2B55 pinout has been designed to make this easy to do. For
best results, keep all leads associated with signals on the input
edge as far as possible from signals on the ou tpu t edge. This
will minimize the effects of board leakage and capacitance.
The use of a guard track on both sides of the board (Figure 2)
can also be helpful.
The power supplies should be decoupled with tantalum capacitors as close to the unit as possible. For lowest noise, the output grounding scheme should be as shown in Figure 2. The
output signal common is connected directly to pin 12, with
power supply returns brought separately to that pin so that
power supply currents do not flow in the low lead of the signal
output.
I
,
CHANNEL
A
l- _____________
I
J,
2854/2855
Figure 1. 2854/2855 Functional Diagram
The internal oscillator has its own power supply pins for enhanced application flexibility, and a sync mechanism is provided to eliminate beat-frequency errors when multiple 2B54/
Since most of the power taken by the 2B5412B55 is supplied
to the internal oscillator which requires only a positive supply
and can accommodate a wide range of supply voltages, it is
sometimes desirable to power the oscillator from a convenient
source of untegulated power (such as +24V - Figure 2). A
O.lJ.1F capacitor should be then connected directly from
pin 12 to pin 31. Since the output and oscillator circuits
are not fully isolated, a dc path must exist between the two
power supply commons. A small (one or two volts) potential
difference between OUT COM and OSC COM will not affect
operation.
SIGNAL CONDITIONING COMPONENTS & SU8SYSTEMS 11-83
•
Gain Setting
The gain of each channel is independently set by a usersupplied resistor (RG) connected as shown in Figure 2. Channel gain will normally be selected so that the maximum output
of the signal source will result in a plus or minus full scale
(±5V) output swing. The resistor value required is ~ =
10kW (G -1). Thus if RG =101n, the gain wiJI be 100, and
an input signal swing of ±50mV will yield an output span of
±5V.
A parallel trim on the gain-setting resistor can be used to trim
out the resistor's tolerance and the module's gain error (Figure 3). Since a parallel trim will always increase the gain, the
value of the gain-setting resistor should be chosen to give an
untrimmed gain somewhat lower than the desired trimmed
gain. Good quality metal-film resistors should be used for ~
since gain accuracy and drift are a direct function of RG's
characteristics. Cermet pots are suitable for the trim.
Figure 3. Input Offset and Gain Adjustments
Optional Offset Adjustment
The 2B5412B55 has provision for fine adjustment of the input
offset of each channel and the output offset of the entire
module. None of the offset adjustments affect offset drift, and
there is no need to make any adjustment unless the application
calls for tigh ter offsets than those specified for the module type.
Connections for input offset adjustment are shown in Figure
3. This is a fine trim with a limited range (±250/lV - 2B54
and ±lmV - 2B55, RTI), used to adjust each channel for
zero offset while operating at the desired gain. Since the
range of the input offset trim is small, it will usually be necessary to adjust output offset first. This can be conveniently
done by operating one channel with zero input at unity gain
(by disconnecting the gain resistor) and adjusting the output
offset control for zero output. Connections for output offset
adjustment are shown in Figure 4.
Stable components (a metal film resistor and a cermet pot)
should be used for the input offset adjustment to avoid compromising drift. Output offset adjustment components are not
critical and may be omitted altogether when a single 2B54/
2B55 is followed by an A to D Converter that has a zero
adjustment.
Otannel Selection
Each channel in the 2B54/2B55 is turned on and off' by a
SELECT input. As indicated in Figure 1, each SELECT input
consists of an LED in series with a resistor, and is not connected to any other circuits in the module. Turning the LED
on O;;'2.5mA) turns the channel on, and turning the LED off
O";50/lA) turns the channel off. This allows considerable
flexibility of connection, but the easiest way to use the SELECT
inputs IS to tie all four SELECT + pins to +5V and drive the
SELECT-inputs from TTL logic (either open-collector or
totem-pole outputs can be used), as shown in Figure 2.
It is also possible to use CMOS logic to drive the SELECT
inputs (Figure 5). With a +15V logic supply a standard CMOS
decoder or gate can supply enough current to drive the SELECT inputs directly, but at lower supply voltages it is advisable to use a buffer such as that shown in Figure 5b. The power
taken by the SELECT inputs is small, since only'one is on at a
time, but at the higher CMOS supply voltages more current
than the required 2.5mA will flow. This does not affect operation, but if desired the current can be brought back to the minimum value with series resistors as shown in Figure 5. Use 2kn
for 10V operation, and 3.9kU at lSV.
The maximum reverse voltage applied to any SELECT input
must be limited to 3V to avoid damage to the LED. Maximum
forward current should be kept below 25mA. Each SELECT
input is isolated from all other circuits in the module and may
be operated up to ±50V away from output and power ground.
Channels may be selected in any order, and there are no
restrictions on rate or duty cycle except the 2.5ms settling
time for access to a channel. It should be noted, however, that
selecting two or more channels simultaneously for more than
a few microseconds will result in a very long settling time when
the conflict is resolved. Timing overlaps should therefore be
avoided.
28541
2855
f.'-..---<>---- +15V LOGIC POWER
2854/2855
OUTPUTl
~~:::::f!:~~-==
CO"~"''-----_
Figure 5a.
~16V
*ro PRESERVE GAIN STABlllTV THE OUTPUT GAIN ADJUSTMENT
RANGE SHOULD NOT BE MORE THAN 10%
28541
2855
Figure 4. Output Offset and Master Gain Adjustments
An alternative offset adjustment procedure is appropriate in
applications where the channel gains are field-selected by
switching the gain-setting resistor. Here it is desirable to set
the input offset so that there is no zero shift at the output
when the gain is changed. To make the adjustment, switch
back and forth from low to high gain with zero input and adjust the input offset control until no shift occurs at the output
when changing gains. Then adjust the output offset control for
zero output at the lower gain.
11-84 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
Figure 5b.
Figure 5. CMOS Channel Selection
Otannel Expansion
The 2B54/2B55 has provision for directly interconnecting
several modules when more than four channels are needed.
The series-switched outputs of a group of modules are connected together, the SELECT inputs are driven in parallel,
and the output of the desired module is selected using the
Output Enable pin. This is shown in Figure 6. A single
74LS139 decoder is used to drive the SELECT inputs of up
to four modules, and also provides address expansion so that
the binary coded channel address word selects the appropriate
module output via the Output Enable pins. The overall operation of the series-switched outputs is analogous to three-state
logic, and the output rail is thus an analog bus.
It is possible to operate up to sixteen modules in parallel, for
a total of 64 input channels. Note that it will be necessary to
break up the SELECT inpu ts into several groups to avoid overloading the decoder when many modules are used. The settling time of the output switches is <50tls to ±O.Ol % and is
thus negligible in comparison to the channel selection times.
The Output Enable signal is active low, and is compatible with
both TTL and CMOS logic. The switching threshold is + lo8V;
input current at OV is typically -O.4mA.
The output resistance of the Switched Output (typically 35S1
+o.5%lC) is low enough to provide fast switching times but
will cause gain errors when driving a heavy load. A single buffet isolating the Switched Outputs from the load will solve
this problem in an "analog bus" application (Figure 6). In
single-module applications the DIRECT (low impedance) output should be used. Note that in all cases the SENSE pin must
be connected to the DIRECT output to provide feedback for
the output amplifier.
TO ADDITIONAL MODULES
/
.
2854/2855
ANALOG
BUS
~
CHANNEL
SELECT
r~" ti,J
DIRECT
OUTPUT
SENSE
COMMON
pL
r
r-"
ENABLE
,
c-
"
SELECT
MOOULE
SELECT
~~
~
+
The frequency of the external sync source, when used, will
have a small effect on the gain and output offset of the 2B541
2B55. Thus any adjustments should be made with the module
synchronized.
FROM EXTERNAL
SYNC SOURCE
(IF USED)
NOTE MAKE NO CONNECTIONS TO SYNC IN OR SYNC OUT
FDA UNSYNCHRONlzeo OPERATION
400kHz ;10%, 1V -15VPP,
30% TO 70% DUTY CYCLE
Figure 7. Synchronization
Open Input Detection
The 2B54 can be programmed to respond to an open-circuit
condition on a channel input with either an upscale or downscale response when the affected channel is selected. The
response time to detect an open input can be in the tens of
seconds, since only a few nA of input bias current are available to charge the input filter. The circuits in Figure 8
indicate the selection of either downscale or upscale response
and can be used to provide shorter open-circuit response
times. Either circuit will produce a bias current of approximately 20nA which can be used to aid or oppose the 3nA
typically supplied by the module, as shown. The circuit of
Figure 8A has the advantage of simplicity, but the highvalue resistor may not be readily available. Figure 8B shows
how to solve the problem at the expense of complexity. The
values shown may be modified to give an optimum trade of
bias current for response time in a given application. A 2 to
5 second response is typical for the values shown.
If a downscale response is desired, a resistor divider circuit
like Figure 8B may be desired to prevent a negative overscale. If a negative overscale condition occurs (typically
-7V), the output will saturate on all channels.
SUFFER
A0741C
32) terminal of the adjacent 2B5412B55 (Figure 7). The first
of a group of modules may be synchronized to an external
source via the SYNC IN pin. To minimize noise pickup, sync
wiring should be separated from analog signal runs.
TDAD
} CONVERTER
2854/2855
2854/2B55
20
e-
35
A-
2854/2855
f!-
I
DIRECT
OUTPUT
SENSE
COMMON
3
ENABLE
,
c-
"
r
SELECT
/
~
pL
e-
A-
74LS 139
..--,v,
'--- m
~
m
m
--
" t--t--- LSe
G) GIVES DOWNSCALE RESPONSE
BINARY
CHANNEL
>A
m
WO
'GH1G
'-----
o
GIVES UPSCALE REsPONSE
G) GIVES DOWNSCALE RESPONSE
o
GIVES UPSCALE RESPONSE
ADDRESS
>V3
m
20
35
"
"'r- MSS}
~
NOTE ALL "SELECT +" PINS TIED TO +6V
Figure 6. Expansion to More than Four Channels
Synchronization
In applications where multiple 2B5412B5 5 's are used in close
proximity or when system clock signals are present near the
isolator, differences in individual oscillator frequencies may
cause "beat frequency" related output errors. To eliminate
these errors, multiple units may be synchronized by connecting the SYNC OUT (pin 3~) terminal to the SYNC IN (pin
Figure 8. High Speed or Reversed Open Input Detection
Output Filtering
In most applications, no output filtering will be required since
the effect of the small carrier-related noise spikes on the output «lmV pop, 100kHz B.W.) drops off rapidly as bandwidth
decreases and in many cases will be negligible_ In some applications (e.g., when driving a successive-approximation A to D)
the effective system bandwidth may be large enough to pass
the noise. To eliminate the carrier noise (without any effect
on switching times), a simple R-C filter may be used at the
output (Figure 9A). Only one filter is needed even when multiple modules are used, as shown in Figure 9B. If the load to
be driven has an' input resistance of less than lOMS1, a buffer
will be needed.
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-85
III
ADDITIONAL
MODULES
rr-T'
2854/2855
I
I
SWITCHED 4
TOAID
} CONVERTER
OR BUFFER
DIRECT 6
SE"'BE 7
1<'-_-<>-
} ~::eRTER
OR BUFFER
2854/2866
thermocouples must be compensated for the temperature of
the reference junction which is formed where the thermocouple leads are terminated, the 2B56 Universal Cold Junction
Compensator is used. The 2B56 monitors the temperature of
the reference junction (terminal block) via an external sensor
and corrects the signal at the output of the 2B54 for reference
temperature. Compensation for several thermocouple types is
selectable via digital control inputs. Thermocouple linearization, if needed, would be typically performed in system's
software.
Figure 9. Output Filtering
CMR AND NMR PERFORMANCE
Common mode rc;jection is a result of both isolation and
filtering and indicates ability to reject common mode inputs
while amplifying differential signal inputs. CMR is dependent
on source impedance imbalance, signal frequency and conditioner gain.
Normal mode rejection is also a function of the 2B 5412B5 5
gain. Figures 10 and 11 illustrate typical CMR and NMR
performance. Note that any additional low pass filtering (e.g.,
an integrating A to D converter) at the output of the 2BS4!
2BSS will further improve both CMR and NMR performance.
...... 1'--
2B~4
t--..
-20
~
NORMAL
"'-
MOOE"
IESPONSE I
G-1IIOO
r-
_'20
.,
_'OIl
~·r=~'"'
--dl:~'T
,
-oo
--
p... ....
......
Figure 12. Four-Channel Thermocouple TemperatureMeasurement with Cold Junction Compensation
\rG'"
Process Signals Interface: In Figure 13, the 2B55 is used to
provide floating inputs for four 4-20mA process signal loops.
The use of floating inputs in this type of application gives
protection from common-mode voltages and greatly simplifies
system configuration, since additional loads in series with the
loop can be connected on either side of the isolator input.
,-,
"-
r
_'40 r-
I"'< -"'-
"
_....
.... - "100- .......
r.-. -.
-.- -
-
~-
,........... '00
,0<
FREQUENCY - Hz
Figure 10. Common Mode and Normal Mode Response Model 2854
Rtf}..
.JJLlti
"-
2S'55
......
G· ....
.......
When there are several loads on the loop, compliance voltage
at the transmitter may be at a premium. In this case it will
be advantageous to reduce the voltage swing at the isolator
inputs by using smaller resistors (perhaps 2Sn) and scaling
the output back to a SV span by taking an appropriate gain
in the isolator.
'
G"
,
r-...
r-...r----..
-'20 -'40
.,
-'OIl
COMMON-MODE
AEIIf'ONSE
-Rs"1kO
----R.<100n
I II
-
..
-
Each current input is converted into a 1 to 5 volt signal by
a 2S0n resistor. The 2B55 is operated at unity gain (no gainsetting resistors) so that a 1 to S volt signal appears at the output. Since no gain-setting resistors are used, gain adjustment,
if required, is done by connecting trims directly across the
input resistors. Other current ranges can be accommodated
by changing the value of the input resistors .
-
, ...:::. ......
- - -- - - - - -- --
.. :
.,/GDM
70 LOfOfS
G'"
10
100
FREQUENCY - Hz
'000
,0<
Figure 11. Common Mode and Normal Mode Response Model 2855
APPUCATIONS
Thermocouple Temperature Measurement: Figure 12 shows a
four-channel thermocouple input system with isolation, amplification, and multiplexing provided by the 2B54. Several
different thermocouple types are used, and the gain-setting
resistors on each channel have been chosen to take the standard ANSI range for each type to a SV output span. Since
11-86 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
66 :
R&COM
}CH~NEL{ D;:: :
}CHANNEL
COMM:~:3~,;::::::;::::=::::=
5
1
COMMON
C
osc
80 LOfOfS
l~~i~U:v
y_I''''-+_____
OUT
y+ 30
47: }C:::L{ {~~;,
51
~=
S
SELECT
37: }CH~NEL
4t~=
p-----
+
21
:
:
_ {::
J~tm"
AU
LOGIC
COMMON
Figure 13. IlIOlated 4-20mA Loop Signals Interface
Low-Cost, Two-Wire
Transmitters
28 Series
~ANALOG
WOEVICES
The 2B Series two-wire transmitters are versatile, rugged and
accurate (±O.l%) instruments designed to operate in harsh
environments. All units feature RFIIEMI immunity and an
operating temperature range of - 30'C to + 85°C. The 2B Series
transmitters accept input from thermocouples (both isolated and
nonisolated), RTDs, AD590 sensors and dc current or voltage
sources. The thermocouple and RTD models are FM approved
for intrinsically safe operation. A loop-powered isolator is also
available.
2852 and 2853: Thermocouple Input
z~ ~~
2824: Loop·Powered Isolator
2858: RTD Input
285212863
2824
•
•
•
•
Accuracy: ± 0 1%
Isolation: ± 800V pk (2852 only)
Supply voltage range. + 12V to + 60V
Load resIstance range. 0 to 600n
(at Vs = + 24V)
• FM approved (2852)
•
•
•
•
•
Accuracy ± 0 1%
L,nearized output
Sensor eXCItation. 0 SmA
Supplyvoltagerange + 16Vto +60V
Load resIstance range 0 to 400n
(atVs = + 24V)
• FM approved
• Accuracy. ±O.I%
• Input current· 1-30mA (2824A). I-SOmA
(28248)
• Input voltage requirement 3 5V plus voltage
drop across output load
• Isolation ± 1500V pk
Ordering Information
Ordering Information
Ordering Information
Example.
Example.
MocJeI2B58A·1·1-01
Example.
Enter Model
2858A
~I
Enter Model
~:~~ l~~~~~~ted)
MocJeI2B52A-1-J-OJ
~I
Enter HousIng
I-standard er>closure
Enter HousIng
I-standard enclosure
Model2B24A
I
Enter Model
2824A {1-30mA) _ _ _ _..J
28248 ( I-SOmA)
III
Enter RTD Type
I-lOOn Pt. a = 0.00385
Enter Thermocouple Type
J. K or T
Enter Temperature Range
01 through 04
_::.-_ _ _ _ _ _ _..J
Enter Temperature Range
01 through 06 -~-------~
Range In °C ,oFI
No.
Range In °c ,oFI
No.
-IOOto +300
(- 148to + 572)
J. K. T
01
-IOOto + 100
(-148to +212)
01
Oto +200
(+32to +392)
T
02
Oto + 100
(+32to +212)
02
03
Oto +200
(+32to +392)
03
04
Oto +400
(+32to +752)
04
TCType
Oto +500
(+32to +932)
Oto +600
(+32to + I 112)
K
Oto + 750
(+32to + 1382)
Oto + 1000
(+ 32 to + 1832)
05
K
Custom ranging is also available.
Custom ranging is also available.
06
This two-page data summary contains key specifications to speed your selection of the proper solution for your application. Additional information on this
product can be obtained from your local sales office.
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
11-87
TRANSMITTERS FOR ENERGY MANAGEMENT
APPLICATiONS
The 2B57 in a modular form and 2B59 two-wire transmitters
were specifically designed to provide low cost, small size and
ease of installation in mUltipoint temperature monitoring applications. These transmitters can be mounted in a standard 2" x 4"
utility box with a probe for duct temperature sensing or in wall
thermostat boxes. The 2B57 is also available in a standard metal
enclosure.
2859. RTD Input
2857. Solid State Temperature
Transducer Input
Outline Dimensions
DimenSions shown In Inches and (mm)).
2824,2852,2853,2857,
2857A·' ,28S8
,m
2WIRE
• Accuracy ±O 1%
• Supply voltage range. + 10V to + 35V
• Load resistance range 0 to 7000
(at Vs = + 24V)
Ordering Information
:::::_:_I____
jBS9A-G-,_Ot
M_od_e---J1
1
2859A
Enter HOUSIng
O-Module
Enter Sensor Type
1-1000 Pt. a = 0 00385
2-10000 NIFe. a = 0.00527
3-20000 NIFe. a = 0.00527
Enter Temperature Range
01 through 06 -~---------'
•
•
•
•
AD590 or AC2626 probe Input
Accuracy ±O 1%
Supply voltage range: + INto + 50V
Load reSistance range: 0 to 6000
(atVs = +24V)
Ordering Information
Example.
--l 1--
ModeIZBS7A-t
~
.
Enter Model
2857A - - - Enter HOUSIng
I-standard enclosure
I RRRHHHRR
031 179)
G
2857
r---- '"
1-1
I
(383)-_
M"
U
~)MIN
[I~t~)
::::u= ~I~
0
02)
025 (635) MAX
Available Temperature Ranges
Rangeln"C,OFJ
Sen_Type
-18to+38
1.2
(0 to + 100)
-7to +49
1.2.3
(+20to + 120)
+ 10to +66
1,2
(+50to + ISO)
1,2,3
Oto + 100
(+32to+212)
-34to +54
3
(-30to + 130)
+93 to +204
3
(+200to +400)
No.
01
02
~1
TI~V'"
I"
WEIGHT 12G-II-Ol(254IGRID
03
2859
04
05
06
SENSOR
-\!SUPPlY
11-88 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
+IISUIIPlV
1IIIIIIII ANALOG
WDEVICES
The Complete
Signal Conditioning liD Subsystem
3BSeries I
FEATURESIBENEFITS
Low Cost, Completely Integrated 16-Channel Modular
Signal Conditioning Subsystem
Wide Selection of Functionally Complete Input and
Output Plug-In Modules
Rugged Industrial Chassis, Rack or Surface Mounted
On-Board Power Supplies Available
Analog Input Modules Available for Direct Interface to a
Wide Variety of Signal Sources
Thermocouples, RTDs, Strain Gages, LVDTs
Millivolt, Voltage and Frequency Sources,
4-20mAlO-20mA Process Current Inputs
Current Output Modules
4-20mAlO-20mA Outputs
Complete Signal Conditioning Function
Input Protection, Filtering, Amplification,
Galvanic Isolation to ± 1500V,
Wide-Range Zero Suppression,
High Noise Rejection and RFI/EMI Immunity,
Simultaneous Voltage and Current Outputs
GENERAL DESCRIPTION
The 3B Series Signal Conditioning 110 Subsystem provides a
low cost, versatile method of interconnecting real-world analog
signals to a data acquisition, monitoring or control system. It is
designed to interface directly to analog signals such as thermocouple, RTD, Strain Gage, or AD590/AC2626 solid state
temperature sensor outputs or millivolt or process current signals
and convert the inputs to standardized analog outputs compatible
with high level analog 110 subsystems.
The 3B Series Subsystem consists of a 19" relay rack compatible
universal mounting backplane and a family of plug in (up to 16
per rack) input and output signal conditioning modules. Eight
and four channel backplanes are also available. Each backplane
incorporates screw terminals for sensor inputs and current outputs
and a connector for high level single ended outputs to the user's
equipment.
The input and output modules are offered in both isolated
(± 1500V peak) and nonisolated versions. The input modules
feature complete signal conditioning circuitry optimized for
specific sensors or analog signals and provide high level analog
outputs. Each input module provides two simultaneous outputs:
o to IOV (or ± IOV) and 4-20mA (or 0-20mA). Output modules
accept high level single ended signals and provide an isolated or
nonisolated 4-20mA (or 0-20mA) process signal. All modules
feature a universal pin-out and may be readily "mixed and
matched" and interchanged without disrupting field wiring.
Each backplane contains the provision for a subsystem power
supply. The 3B Series Subsystem can operate from a dcldc
converter or ac power supply mounted on each backplane or
from externally provided dc power. Two LEDs are used to
indicate that power is being applied.
APPLICATIONS
The Analog Devices 3B Series Signal Conditioning Subsystem is
designed to provide an easy and convenient solution to signal
conditioning problems in measurement and control applications.
Some typical uses are in mini- and microcomputer based systems,
standard data acquisition systems, programmable controllers,
analog recorders, dedicated control systems, and any other applications where monitoring and control of temperature, pressure,
flow, and analog signals are required. Since each input module
features two simultaneous outputs, the voltage output can be
used to provide an input to a microprocessor based data acquisition
or control system while the current output can be used for
analog transmission, operator interface, or an analog backup
system.
DESIGN FEATURES AND USER BENEFITS
Ease of Use: Direct sensor interface via screw terminals, standardized high level outputs, factory precalibration of each unit
and the modular design make the 3B Series Subsystem extremely
easy to use. The subsystem features rugged packaging for the
industrial environment and can be easily installed and
maintained.
High Protection and Reliability: All field wired terminations
offer BOV or 220V rms normal-mode protection. To assure
connection reliability, gold plated pin and socket connections
are used throughout the system. The isolated modules offer
protection against high common-mode voltages and are designed
to meet the IEEE Standard for Transient Voltage Protection
(472-1974: SWC).
High Performance: The high quality signal conditioning features
± 0.1 % calibration accuracy and chopper-based amplification
which assures low drift (± I J.LV1°C) and excellent long-term
stability. For thermocouple applications, high accuracy cold
junction sensing is provided in the backplane on each channel.
Low drift sensor excitation is provided for RTD and strain gage
models. For RTD models, the input signal is linearized to provide
an output which is linear with temperature.
This four-page data summary contains key specifications to speed your selection of the proper solution for your application. Additional information on this
product can be obtained from your local sales office.
SIGNAL CONOITIONING COMPONENTS & SUBSYSTEMS 11-89
III
FEATURES
Wide Variety of Sensor Inputs
Thermocouples, RTDs, Strain Gages, LYDTs,
AD59OIAC2&26
Dual High Level Outputs
Voltage: 0 to + 10V or :t 10V
Current: 4-20mAIO-2OmA
Mix and Match Input Capability
Sensor Signals, mY, V, 4-20mA, 0-20mA
High Accuracy: :to.1%
Low Drift: :t1"VI"C
Reliable Transformer Isolation:
:t1600V CMV, CMR =16OdB
Meets IEEE-BTD 472: Transient Protection (SWC)
InpL-t Protection: 130V or DOV ImS Continuous
Low Cost Per Channel
GENERAL DESCRIPTION
Each input module is a siugle channel signal conditioner that
plugs into sockets on the backplane and accepts its signal from
the input screw terminals. All input modules provide input
protection, amplification and filtering of the input signal, accuracy
of :to.l%, low drift of I ....Vrc (low level input modules), and
feature two high level analog outputs that are compatible with
most process instrumentation. The isolated input modules also
provide :t 1500V isolation.
The choice of specific 3B module depends on the type of input
signal and also whether an isolated or nonisolated interface is
required. Input modules are available to accept millivolt, volt,
process current, thermocouple, RTD, strain gage, and AD590
inputs. The voltage output of each module is available from the
Voltage 110 connector wbile the current output is available on
the output screw terminals.
THERMOCOUPLE INPUT MODELS 3837, 3847
The isolated thermocouple models incorporate cold junction
compensation circuitry which provides an accuracy of :t 0.5"<:
over the +5"<: to +45"<: ambient temperature range. Open
thermocouple detection (upscale) is also provided. Standard
models are available for thermocouple types J, K, T, E, R, S
and B. Factory configured custom ranges are also available. The
3B37-X-OO can be user configured with the ACBIO ranging
card. The 3B47 internally linearizes the thermocouple signal.
All screw terminals have a 220V rms protection.
RID INPUT MODELS 3B14, 3B15, 3B34
Each RTD model provides a sensor excitation current and produces
an output signal that is linear with temperature with a conformity
error of :to.05% of span and accuracy of :to.l% span. The
lead resistance effect for the three models is :t 0.02"C10 for the
3Bl4 and the 3B34, and :t .OOOOloClO for the 3B15. All excitation
input and output screw terminal connections have at least BOV
rms protection.
STRAIN GAGE INPUT MODEL 3816
Models 3Bl6 accepts inputs from full four arm bridge strain
gage-type transducers. It provides a constant + lOY bridge
excitation and can be used with a bridge resistance of 3000 or
greater. All excitation input and output screw termina1 connections
have BOV rms protection.
W1DEBAND STRAIN GAGE MODEL 3818
Model 3Bl8 accepts inputs from full four arm bridge strain
gage-type transducers. It provies a switch selectable excitation of
+ 3.3V or + 10.OV and can be used with 1000 to 10000 strain
gage bridges. The module has a 20kHz bandwidth to interface
to dynsmic signals.
MILLIVOLT AND VOLTAGE INPUT MODELS 3810,
3811, 3830, 3831
Models 3BIO and 3B11 are nonisolated modules that accept mV
and V signals respectively. Models 3B30 and 3B31 are isolated
modules that accept mVand V signals respectively. All screw
termina1 connections have at least BOV rms protection.
W1DEBAND MILLIVOLT AND VOLT INPUT
MODELS 3840, 3841
Models 3B40 and 3B41 are isolated modules that accept mV and
V signals respectively. The modules have a 10kHz bandwidth to
interface to dynamic signals. All screw termina1 connections
have at least BOV rms protection.
CURRENT INPUT MODELS 3812, 3832
Models 3B 12 (nonisolated) and 3B32 (isolated) accept process
current signals. Both models use a 1000 sensing resistor that is
mounted on backplane terminals 2 and 3. All screw terminal
connections have at least l30V rms protection.
AD590 INPUT MODEL 3B13
Model3BB accepts an AD590 as its input signal. Sensor excitation
is provided and a 2kO sensing resistor is mounted on backplane
terminals 2 and 3. All excitation input and output screw terminal
connections have BOV rms protection.
LVDT OR RVDT INPUT MODEL 3B17
Model3Bl7 accepts signals from 4,5 and 6 wire LVDT or
RVDT transducers. It provides an ac excitation of 1-5V rms at
frequencies ranging from 1kHz to 10kHz and has a 100Hz
bandwidth. All screw terminal connections have BOV rms
protection.
AC INPUT MODELS 3842, 3843 AND 3844
Models 3B42, 3B43, and 3844 accept ac signals from 20mV to
450V rms. The modules are rms calibrated for sinusoidal inputs,
such as ac power lines. Ail screw terminal connections have at
least BOV rms protection.
FREQUENCY INPUT MODELS 3845, 3846
Models 3B45 and 3B46 accept frequency input signals from
25Hz to 25kHz. User selectable thresholds of 1.6V and OV (for
zero crossing) are available. All screw terminal connections have
at least BOV rms protection.
11-90 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
Output Modules
FEATURES
High Level Voltage Input (0 to + 10V, :!: 10VI
Process Current Output (4-20mAlO-20mAI
High Accuracy: :!: 0.1%
Reliable Transformer Isolation: :!: 1500V CMV, CMR =
90dB
Meets IEEE-STO 472: Transient Protection (SWCI
Output Protection: 130V or 220V rms Continuous
Reliable Pin and Socket Connections
Low Cost Per Channel
GENERAL DESCRIPTION
Each output module accepts a high level analog signal from the
system connector and provides a current output on the output
screw terminals. When a + 24V loop supply is used, loads up to
8500 can be driven. If desired, + ISV can be used to power the
output modules with a smaller load (up to 4000). Each output
module features high accuracy of ± 1%. If isolation is required,
the 3B39 provides ± ISOOV peak common-mode voltage isolation
protection.
NONISOLATED OUTOUT MODEL 3B19
The 3Bl9 output module accepts a 0 to + lOY or ± lOY input
signal and converts it to a proportional current output. Output
ranges are jumper selectable for either O-to 20rnA or 4-to-20rnA.
The current output is protected to BOV rms continuous.
ISOLATED OUTPUT MODEL 3B39
Model 3B39 is an isolated module that accepts a 0 to + lOY or
± lOY input signal and converts it to a proportional current
output. Output ranges are jumper selectable for either 0-to-20mA
or 4-to-20mA. Input to output isolation is rated to ISOOV pk
continuous.
Backplanes
FEATURES
4-,8-, or 16-Channel Versions Available
ac or dc Power Supply Options
GENERAL DESCRIPTION
The three backplane models, 3B01, 3B02 and 3B03 are designed
for 16, 8 and 4 channels, respectively, to give users the flexibility
to match the size of a system to specific applications. The 16-channel backplane can be mounted in a 19" x 5.25" panel space. The
backplanes can be surface mounted, mounted on a rack or mounted
in a NEMA enclosure.
POWER SUPPLY
The 3B Series Subsystem can operate from a common ac power
supply or dc/dc ( + 24V input) power supply mounted on the
backplane or an externally provided ± ISV and +24V supply.
The power supply is bussed to all signal conditioners in the
system. The current consumption is a function of the modules
that are actually used.
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-91
III
3B Series Subsystem Specifications
INPUT MODULES
BACKPLANES
Input Types
Thermocouples: J, K, T, E, R, S, B
Thermocouples: J, K, T, E, R, S, B (Linearized)
RTDs: 1000 Platinum, 100 Copper, 1200Nickel (Linearized)
Strain Gage Transducers: ±30mVand ± lOOmV spans
LVDT or RVDT: 4, 5, 6 Wire
Solid State Temperature Transducers: ADS90 or AC2626
DC Voltage: ±IOmV, ±SOmV, ±IOOmV ±IV, ±SV,±10V
DC Current: 4-ta-20mA, 0-ta-20mA
"A..C Voltage: 0-50mV rn1S, O-lOOmV iTIlS, v-lOV rms,
0-IS0V rms, 0-2S0V rms
Frequency: 0-2SHz, 0-300Hz, 0-IS00Hz, 0-3000Hz, 0-2SkHz
Channel Capacity
3BO 1: 16 channels
3B02: 8 channels
3B03: 4 channels
Outputs (Simultaneous)
+ lOY or ± 10V and
4-to-20mA or 0-to-20mA*
POWER SUPPLIES
Backplane Mounted:
100, 115,220, 240V ac, 50i60Hz
or +24Vdc
External Power Option
± ISV dc and + 24V dc
o to
Performance
Accuracy: ±O.I% of span
Nonlinearity: ±0.01% of span
Bandwidth: 3Hz ( - 3dB)
Isolated Modules
Common-Mode Voltage, Input to Output: ± ISOOV pk continuous
Transient Protection: Meets IEEE-Std 472 (SWC)
Normal-Mode Input Protection: 220V rms continuous
Current Output Protection: BOV rms continuous
Common-Mode Rejection @ 50Hz or 60Hz: l60dB
Normal-Mode Rejection @ 50Hz or 60Hz: 60dB
MECHANICAL
Input or Output Modules:
3.150" x 0.775" x 3.395"
(80.Omm x 19.7mm x 86.2mm)
Backplanes:
3BOl: 17.40" x 5.20" x 4.37"
(442.0mm x B2.1mm x 111.lmm)
3B02: 11.00" x 5.20" x 4.37"
(279.4mm x B2.lmm x 111.lmm)
3B03: 7.80" x 5.20" x 4.37"
(l98.lmm x B2.lmm x 111.lmm)
ENVIRONMENTAL
Nonisolated Modules
Common-Mode Voltage: ±6.SV
Normal-Mode Input Protection: BOV rms continuous
Current Output Protection: BOV rms continuous
Common-Mode Rejection @ 50Hz or 60Hz: 90dB
Normal-Mode Rejection @ 50Hz or 60Hz: 60dB
OUTPUT MODULES
Input
+ lOY or ± 10V
o to
Output
4-to-20mA or O-to-20mA
Performance
Accuracy: ± 0.1 % of span
Nonlinearity: ±0.01% of span
Isolated Module
Common-Mode Voltage,
Input to Output: ± IS00V pk continuous
Current Output Protection
Transient: Meets IEEE-Std 472 (SWC)
Continuous: 220Vrms
Nonisolated Module
Current Output Protection: BOV rms continuous
*There is no current output on the 3B47.
Specifications subject to change without notice.
11-92 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
Temperature Range, Rated Performance:
- 25°C to + 85°C
Storage Temperature Range:
-55°C to +85°C
Relative Humidity: Conforms to MIL-STD 202,
Method 103
RFI Susceptibility: ± 0.5% span error,
5W @ 400MHz @ 3 ft.
r'IIII ANALOG
WDEVICES
Alarm Limit Subsystem
48 Series I
FEATURES/BENEFITS
• Low Cost, Completely Integrated 12-Channel Modular
Alarm Limit Subsystem
Selection of Alarm Limit Modules
Rugged Industrial Chassis, Rack or Surface Mounted
On-Board Power Supplies Available
• Alarm Modules Accept High Level Voltage and Process
Current Inputs
• Complete Alarm Function per Module
High Accuracy of ±0.1%
Two Set Points, Adjustable Over 100% Span
Dead Band Adjustment per Set Point, Adjustable
Over 0.5°/_10.0% Span
Alarm Types are Configurable for HI or LO Operation
Two Relay Outputs
Three Digit Display Indicates Set Points and Process
Variable as a Percent of the Input Span
LED per Set Point Provides Local Alarm Indication
Input Protection
High RFI/EMI Immunity
• Specifications Valid Over the 0 to + 70°C Temperature
Range
• Easy to Install, Calibrate and Service
Direct Connections to Industrial Screw Terminals
Modules Removable without Disturbing Field Wiring
or Power
Front Panel Set Point and Dead Band Adjustments
• Convenient Connection to User's Equipment
Interfaces Directly to Analog Output Subsystems
Used for Single Board Computer Interfaces
Universal Adapter Board Allows Easy Interface
to Any Equipment
GENERAL DESCRIPTION
The 4B Series Alarm Limit Subsystem is a low cost method of
providing adjustable alarm limits. Used in conjunction with
either the 5B Series, the 3B Series or a module in the 2B Series
transmitter family, the 4B Series' modules provide alarms for a
wide variety of process sensors and transducers. The Alarm
Limit Subsystem accepts a high level signal and provides fully
independent HI and LO relay outputs.
The subsystem consists of a 19" relay rack compatible universal
mounting backplane and a family of plug-in (up to 12 per rack)
alarm limit modules. A four channel backplane is also available.
The modules, designed for voltage or current inputs, can be
readily mixed and matched and interchanged without disturbing
field wiring. Each backplane incorporates screw terminals for
field wiring and a connector for high level single ended inputs
from the user's equipment.
Each alarm module has two set points which are fully adjustable
over the 100% span. It will accept a standardized high level
analog input and will provide one or two ON/OFF outputs. The
allowable input ranges are ± IOV, 0 to + IOV, 4-20mA and 020mA. All input types can be connected to either the voltage
input connector or the input screw terminals.
The two set points within each module can be user configured
with push-on jumpers for HI-LO, HI-HI or LO-LO use. If
only one limit per channel is desired, the module can be used in
a HI or LO state. The value of each set point and the process
variable can be viewed with a 3 digit display which is controlled
with a rotary switch. Each set point has an adjustable dead band
(hysteresis) which can be adjusted up to 10% of span and can be
used to eliminate nuisance alarms.
This two-page data summary contains key specifications to speed your selection of the proper solution for your ~pplication. Additional information on this
product can be obtained from your local sales office.
SIGNAL CONOITIONING COMPONENTS & SUBSYSTEMS 11-93
•
DESIGN FEATURES AND USER BENEFITS
Direct interface via screw-terminals or ribbon cable, two screwdriver adjustable set points per module, adjustable dead band
per set point, a three digit display that indicates the value of the
process variable and set points, and the modular design make
the 4B Series Subsystem extremely easy to use. The subsystem
features rugged packaging for the industrial environment and
can be easily installed and maintained.
All input screw terminals offer BOV rms normal mode protection.
Connection reliability is assured by gold plated pin and socket
connectors. The high quality alarm modules feature ±O.I%
accuracy and a low drift with temperature (±0.OO5%1"C).
APPLICATIONS
The Analog Devices' 4B Series Alarm LL1!li! Subsystem provides
an easy and convenient solution to alarm/annunciation problems
in measurement and control applications. When used with field
transmitters or any other device that provides a process current
or high level voltage output, it can provide either alarm indication
or ON/OFF control. In a typical application, the 4B Series
Alarm Subsystem provides alarm indication for any sensor input
when used with the 3B Series Signal Conditioning Subsystem.
The 3B Series interfaces directly to sensors and converts the
inputs to the standardized high level analog signal that the 4B
Series alarms. This modular approach provides a very flexible
means to alarm indication since the same 4B module can be
used to alarm a variety of sensors when used with the appropriate
3B module.
FUNCTIONAL DESCRIPTION
Each alarm module is a single channel unit that plugs into sockets
on the backplane and accepts its signal from either the input
screw terminals or the voltage input connector. All alarm modules
provide input protection, ftItering of the input signal, accuracy
of ± 0.1 % and feature two relay outputs that are capable of
driving loads up to 3A.
The choice of a specific 4B module depends on whether the
input signal is a high level voltage or a process current. The
voltage inputs can be connected to a 4B module by either the
input screw terminals or the voltage input connectors. Process
currents can also be connected through either the screw terminals
or the voltage input connector, but must use a sensing resistor.
The current input models are shipped with the required sense
resistor, which is to be installed on the input screw terminals.
The transfer function provided by each alarm module is:
Inputs: High level voltage or process current
Outputs: Two independent ON/OFF Relay Outputs
Figure 1 shows a functional diagram for the model4BI0 alarm
limit module which has been configured for HI-LO operation.
The high level voltage input signal is ftItered and compared
against both set points. If the process variable is above the HI
limit or below the LO limit, the appropriate relay is turned on.
Each set point has an adjustable dead band (0.5%-10.0% span),
which is used to eliminate nuisance alarms. Dead band is the
amount of signal change necessary, after an alarm has occurred,
to return an alarm to its original condition. As an example, if
the HI limit is set at 75% of span and the dead band is 2%, the
alarm will turn on when the process variable is at 75% and will
not turn off until the process variable falls to 73%. For a LO
limit configuration, the dead-band relationship is reversed and
the alarm would not turn off until the process variable has risen
above the sum of the LO set point value and the dead-band
value.
Each set point has an LED which turns on when an alarm
condition occurs and provides local alarm indication.
Figure 1. 4B1O Functional Block Diagram
The alarm status of both limits can be read externally from the
digital I/O connector. When an alarm state exists which is TTL
active high on the readback pins, the relay can be turned off
with an external override sig~al (TTL active low) that connects
to the digital I/O connector. The readbackloverride feature
allows for external monitoring of the alarl!Jl states as well as for
external control or alarm acknowledgement. When an override
signal is used, the readback feature reads the alarm state and
not the relay input signal so that the state of the process variable
can still be monitored.
For the modules with a display, positive overload is indicated
by ] ] ] and negative overload is indicated by a [ in the left
most position.
The 4B modules have five user programmable jumper options.
Each unit can be configured for unipolar or bipolar inputs, both
set points can be configured for HI or LO limit operation, and
both relays can be configured for Normally Open (NO) or Normally
Closed (NC) operation. These options allow the user to readily
tailor the 4B units to his specific needs. For instance, if HI-HI
operation were required, it is available by changing the appropriate
jumpers. All modules are shipped from the factory configured
for unipolar input, NO relay action, and HI-LO operation.
48 MODULE
SPECIFICATIONS
+ 25'C and 15Y. + 5Y de p_l
(typical@
±
Model
Inputs!
4810,4820
4811,4821 4812,4822
Oto + IOV, ± lOY
1l-20mA
Outputs (2 SPST Relays)
ReSlStlve Raung, 3A@
120V ac or 24V de
4-20mA
Performance
Accuracy2
Temperature StabIlity
Bandwldth3
Normal Mode Input Protection
Normal Mode ReJection@50Hzor60Hz
Input Resistance4
Warm-Up Tune to Rated
Performance
Features
Two Set Pomts per Module
Dead band per Set Pomt
RelayAcllon
Three Digit DisplayS
Alarm Status Rt"adback
External Override Signal
Power Supply
Voltage, Rated Performance
Voltage,Operaung
Current6
Sue'
± 0 1% span
± 0.005% spanI"C
5Hz ( - 3dB)
BOV rms
20dS
lOOMll
3 Mmutes
AdJustable over l{)()O/o span
by 25 turn potenuometers
0.5%-10.0% span, adjustable
by 1 turn potenuometer
Field reverSIble by Jumperchange
0-99.9% ofmput span
TTL Level
TTL Leve1
±15V,+5V
± 12Vto ± 18V, +4.5Vto5.5V
± 12rn.A, + l50mA
4.020" x 1.050"x4.020~
Environmental
Temperature Range, Rated Performance Oto + 70°C
~25"Cto + 85"C
Storage Temperature Range
Relative Humidity, Conforms to MIL
to 95%@60"C,noncondensing
Std 202, Method 1038
±O.S%spanerror,
RFI SUscepUbllity
SW@400MHz@ 3 ft.
o
'II
'II
'II
NOTES
'Voltage mput range is Jumper selectable
zAccuracy mcludes setabulIY, repeatability, lmeanty, alld bystereSls Models 4810, 4811, and 4B12 have a quantlZatlOn
errotof::tl dtgtl
lUrupoJar mputs only Bipolar mputs have a bandWldth of 10Hz (- 3dB)
4UrupoJar mputs only Bipolar mputs have an mput reSlstance of 4OOk.Il
sOnly modeb 4BIO, 4Bll and 4B12 have a three dtgtt display
~nly modeb 4BIO, 4Bll and 4B12 ModeJs 4820, 4821 and 4822 reqwre ± 12mA fOf ± ISV and + 12SmA
from +5V
10nly applies to models 4BI0, 4Bli and 4BI2 Models 4B2O, 4B21 and 4B22 measure 4 020"x I OSO"x3 530"
*Specdicauons same as 4BI0, 4B2O
Specdicauons subject to change WithOUt Douce
11-94 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
Compact, Low-Cost
Modular Signal Conditioners
58 Series I
~ANALOG
WDEVICES
FEATURES
• Rugged, Compact, Low Cost Signal Conditioners
• Analog Input Modules for Direct Interface to
Sensors: Thermocouples and RTDs
Millivolt and Voltage Sources
4-20mA or 0-20mA Process Current Inputs
• Analog Output Module
4-20mA or 0-20mA Process Current Output
• Complete Signal Conditioning Function
240V rms Field Wiring Protection, Flitering,
Amplification, 1500V rms CMV Isolation,
High Noise Rejection, RFllEMllmmunity, and
Wide Range Zero Suppression
• High Accuracy: ±O.05%
• Low Drift: ±1p.VI"C
• -25"C to +85"C Temperature Range
• Mix and Match Module Capability
• Convenient Connection to User's Equipment
• Simplified Designer Application
GENERAL DESCRIPTION
The 5B Series represents a new generation of low cost, high
performance plug-in signal conditioners. Designed for industrial
applications, these modules incorporate a new circuit design
utilizing transformer-based isolation and automated surface
mount manufacturing technology. They are remarkably compact,
economical components whose performance exceeds that available
from more expensive devices. Combining I500V rms continuous
CMV isolation, ±O.05% calibrated accuracy, small size and low
cost, the 5B Series is an attractive alternative to expensive signal
conditioners and in-house designs.
All modules are hard potted and identical in pinout and size
(2.25" x 2.25"x 0.60"). They can be mixed and matched, permitting users to address their exact needs, and may be changed
without disturbing field wiring. The isolated input modules
provide 0 to +5V outputs and accept J, K, T, E, R, S, and B
thermocouples; 1000 platinum, 100 copper and 1200 nickel
RTDs; mY, V, 4-20mA or 0-2OmA, and wide bandwidth (10kHz)
mV and V signals. These modules feature complete signal conditioning functions including 240V rms input protection, filtering,
chopper stabilized low drift (± I""VfC), amplification, 1500V
rms isolation, linearization for RTD and thermocouple (with
5B47) inputs and sensor excitation when required. The output
module converts a 0 to + 5V input to an isolated 4-20mA or 020rnA process current signal. All modules feature excellent
common mode rejection and meet IEEE 472-1974 surge withstand
The 5B Series provides system designers with an easy to use
solution for analog 1/0 in a minimum of board space. The modules'
simple pinout and easy mechanical application simplify design.
There are also a number of backplanes which provide a complete
signal conditioning solution for end users. Each backplane incorporates screw terminals for field wiring inputs and outputs
and cold junction compensation sensors for thermocouple applications. Nineteen-inch relay rack compatible units that can hold
up to sixteen modules are available.
APPLICATIONS
These signal conditioners are designed to provide an easy and
convenient solution to signal conditioning problems of both
designers and end users in measurement and control applications.
Typical uses include mini- and microcomputer-based measurement
systems, standard data acquisition systems, programmable controllers, analog recorders, and dedicated control systems. The
5B Series modules are ideally suited to applications where monitoring and control of temperature, pressure, flow, and other
analog signals are required.
specs.
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-95
•
DESIGN FEATURES AND USER BENEFITS
System Desip: It is easy for a system designer to apply the
functionally complete SB Series modules in his own circuit
board or backplane. These modules feature a simple pinout,
plug into widely available sockets and are sec:ured with selfconbiined mounting screws. Other features, which can be used
to minimize system interface cost, have also been incorporated
in the SB Series design. Each input module bas an output switc:h
which is controlled by a TIL-compatible enable input, elinJinating
the need for an external multiplexer. Each output module bas a
track and hold input which permits a single DAC to serve numerous
current output channels. For thermocouple applications, cold
junction compensation sensors are available,
SubeYSlem Solution: The SB Series provides a complete sipal
conditioning soiution. it. family of backplanes, plug-in modules,
factory precalibration of each unit, direct sensor interface via
screw terminal connec:tions, standardized high level outputs,
and ribbon cable system interface result in easy integration into
any system. For thermocouple applications, high ac:c:unu:y cold
junction compensation sensing is provided on each channel. A
general susbsystem application is outlined in Figure l.
Fluibility: The SB Series can be easily tailored to meet each
users needs. These plug-in sipal conditioners can be mixed
and matched to provide I/O for various process sensors and
actuators. Many standard configurations of each module are
available, and, for added flexibility, factoty laser trimmed custom
units can be supplied. A wide zero suppression capability allows
a user to map any portion of the input sipal into the full ouput
span permitting improved system resolution within a selected
measurement range ..
HiP Reliability:
The SB Series was designed to assure maximum
reliability under real-world conditions. The modules are specified
over the - 2S"C to + 8S"C temperature range. Each module is
bard potted; there are no adjustment potentiometers which
could introduce mechanical and human errors that impair system
integrity. All field wired terminations, including sensor inputs,
excitations and current outputs, are protected against continuous
240V rms line voltage. This prevents a fault from damaging not
only the module itself but also the backplane and other devices
connected to the system. The modules also provide protection .
mV. V, THERMOCOUPLE,
RTD,4-20mA/O-20mA
against high common-mode voltages and are designed to meet
the IEEE standard for transient voltage protection (472-1974:
SWC). Gold plated pin and socket connections are used throughout
the system to assure connection reliability.
HiP Performance: The high quality sipal conditioning features
± 0.05% calibration ac:c:unu:y, nonlinearity of only ± 0.02%
span, and chopper-based amplification which assures low drift
(± I ....VI"C) and excellent long-term stability. Low drift sensor
excitation is provided when required, and the RTD module
provides an output which is linear with temperature.
HiP Noise Rejec:Iion: The SB Series Modules were designed
to acc:urate1y process low level sipals in e1ectrically noisy environments by providing ISOOV rms continuous transformer isolation
which elinJinates ground loops, protects against transients and
solves common-mode voltage probleDis. To further preserve
sipal integrity, I60dB common-mode rejection, 60dB normalmode rejection and excellent RFIIEMI immunity are provided.
Small Size: Each SB Series module measures only
2.25' x 2.25' x 0.60" resulting in space savings for both system
designers and end users: each module occupies 1.35 square
inches of board space and a I6-channe.I backplane occupies only
3.5 inches in a rack.
INPUT MODULES ACCEPT REAL
WORLD ANALOG INPUTS AND
PROVIDE ISOLATED HIGH LEVEL
ANALOG OUTPUTS
INPUT MODULE
I
o to
+5V/±5V
COMPUTER
OUTPUT MODULES ACCEPT
HIGH LEVEL VOLTAGE INPUTS
AND PROVIDE ISOLATED
PROCESS CURRENT OUTPUTS
I
OUTPUT MODULE
4-20mAlO-20mA
I
L..._ _ _ _ _ _ _ _.........I 0 TO
+5V/±5V
Figure 1. Functional Block Diagram ofa General Measurement and Control Application Using the 5B Series
11-96 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
INPUT MODULE FEATURES
• Variety of Signal Source Inputs
Sensors: Thermocouples and RTDs
Millivolt and Voltage Sources
4-20mA or 0-20mA Process Current Inputs
• Mix and Match Input Capability
• High Level Voltage Output: :!:5V or 0 to +5V
• High Accuracy: :!: 0.05%
• Low Drift: :!: 1....Vrc
• Reliable Transformer Isolation: 1500V rms CMV,
160dB CMR, Meets IEEE-STD 472: Transient
Protection (SWC)
• Input Protection: 240V rms Continuous
• Factory Ranged and Trimmed, Custom Ranges
Available
GENERAL DESCRIPTION
The galvanically isolated 5B Series input modules are single
channel, plug-in signal conditioners that provide input protection,
amplification and filtering, series output switching, and a high
level analog output. Key specifications include: 1500V rms
isolation, accuracy of ± 0.05%, ± 0.02% span nonlinearity and
low drift of ± Ij.LVI"C. All modules operate from a single +5V
supply with typical power consumption of 0.15W. The modules,
which measure only 2.25" x 2.25" x 0.60", are hard potted.
The transfer function provided by each input module is:
Input - specified sensor measurement range
Output - Oto +5Vor ±5V.
Each 5B Series input module is available in a number of standard
ranges, and special ranges can be factory configured. Analog
Devices will provide a special function when a model 5B
-CUSTOM is ordered with the desired range.
- 5837 FUNCTIONAL DESCRIPTION
Figure 2 shows a functional diagram for a typical input module,
the 5B37 thermocouple conditioner. The module provides cold
junction compensation for the associated screw terminals as well
as a bias current to give a predictable (upscale) response to an
open thermocouple. Input protection allows safe operation even
in the event of a 240V rms power line beiug connected to the
signal terminals. (In modules designed to work with sensors
requiring excitation, low drift sensor excitation is provided and
is protected at the same level).
A three-pole filter with a 4Hz cutoff provides 60dB of normal-mode
rejection and CMR enhancement at 60Hz. One pole of this filter
is located at the module input while the other two poles are in
the output stage for optimum noise performance. A chopperstabilized input amplifier provides all of the module's gain for
ultra-low drift. This amplifier operates on the input signal after
subtraction of a stable, laser trimmed zero-suppression signal
which sets the zero-scale input value. It is, therefore, possible to
suppress a zero-scale input which is many times the total span
to provide precise expanded scale measurements.
Signal isolation is provided by transformer coupling, using a
proprietary modulation technique for exceptionally linear, stable
performance at low cost. A demodulator on the output side of
the signal transformer recovers the originai signal, which is then
filtered and buffered to provide a clean, low-impedance output.
, A series outpUt switch is included to eliminate the need for
external multiplexing in many applications. This switch has a
low output resistance (500) and is controlled by an active-low
enable input which is compatible with CMOS and LSTTL
signals. In cases where the output switch is not used, such as
single-channel and conventionally multiplexed applications, the
enable input should be grounded to power common to turn on
the switch.
A single + 5V power. supply input (as used for all 5B Series
modules) operates a clock oscillator which drives power transformers for the input and output circuits. The input circuit is,
of course, fully floating. 'In addition, the output section acts as a
third floating port, eliminating many problems that might be
created by ground loops and supply noise. The common-mode
range of the output circuit is limited; however, output common
must be kept within ± 3V of power common, and a current
path must exist between the two commons at some point for
proper operation of the demodulator and output switch.
+25V
Figure 2. 5B37 Block Diagram
SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS 11-97
•
INPUT MODULE SPECIFICATIONS (lypical@ +25"1:8l1li +5Vpower)
Model
SB30/SBn
SB32
SB34
SB37/SB47
Input Ranges
Output Ranges
Accuracyl
Nonlinearity
StabIlity vs. Ambient Temperature
Input Offset
Output Offset
Spsn
Common~Mode Voltage, Input to Output
Common-Mode Rejection@ 50Hz to 60Hz
till Source Unbalance
Normal-Mode Rejection@ 50Hz or 60Hz
D!fferential Input Protection
Output Resistance
Voltage Output Protection
Input Transient Protection
Input Resistance
Bandwidth
Output Selection Time
Power Supply
PowerConsumptlon
Size
EnVironmental
Temperature Range, Rated Performance
dcmV/dcV
±5VerOto +5V
±O.OS%Spsn
± 0.02% Spsn
Process Current
RTD
Oto +SV
Thermocouple
Oto+SV
"/O.IO%Spsn
Temperature Range, Operation
Storage Temperature Range
Relative Hunuduy Conforms to
MIL Spec 202
RFI Suscepllbility
Oto +5V
± I".V?CI20".VI"C
±20".VI"C
±2SppmofrdgI"C
lS00V rms Continuous
16OdB/150dB
60dB
240V I'm" CcntL..uous
500
Continuous Shon to Ground
Meets IEEE-STD472 (SWC)
SMO/6S0kO
4Hz
20".s
+SV ±S%
O.ISW
2.25" x 2.25" x 0.6"
-25°Cto +8S"C
-4O"Cto + 85°C
-4O"Cto +8S"C
Ot09S%(U 6O"C
Noncondensmg
±O.5%SpanError,5W
(U 400MHz(U 3'
"
"
0.05% Spsn Conformity
± 0.0025% SpsnI"C
±0.02°Cl"C
"
"±3Sppmofrdgl"C ' "± 50ppm of rdgl"C
"
"
"
"
"
"
·
"
"
"
"
"
"
·
"
"
"
"
···
·
···
··
·
··
"
"
"
"
"
"
"INA
SB40/SB41
WidebanddcmVN
"
"
"
± 0.02"C1°Cl". VI"C
±2".V?CI±4O".VI"C
"INA
"
"
"
·"
·""
·""
··"
·
··
"
"
"
"
"
1000BI9OdB
N/A
·
"
"
"
200Mnl6S0kn
10kHz
··
·
··
"
"
"
"
NOTES
*Specdkauonssameas5B30
IAccuracy specdicauon mcludes the combmed effects of repeatability. hystereSIs and hnearlty and does not mclude sensor or Slgnal source error
nus speclfi.canon IS for the 58 Series fanuly and may not apply to all ranges of all modules Consuh theSS Senes User'sManualfordetaded specifications
Specifications subJect to change without nouce
Input Type/Span
Output
Model
dc, ±SmVto ±SOOmV
dc, ±soOmVto ± lOY
Process Current, 4-20mA or 0-20mA
Thermocouple Types], K, T, E, R, S, B
Linearized Thermocouple
Types], K, T,E, R, S,B
2,3,4 WireRTDs-IOOfiPlatinum,
10.11 Copper, 120.11 Nickel
±SV
±SV
O-SV
O-SV
SB30,SB40
SB31,SB41
SB32
SB37
O-SV
SB47
O-SV
SB34
Table I. InputSelection
ISOLATED MILLIVOLT AND VOLTAGE INPUT
MODELS 5830, 5831
Model SB30 and SB31 accept millivolt and voltage signals respectively and have a 4Hz bandwidth.
ISOLATED CURRENT INPUT MODEL 5832
Model SB32 accepts process current signals. A resistor is supplied
to convert the signal current to a voltage, and, since that resistor
cannot be protected against destruction in the event of inadvertent
connection of the power line, it is provided in the form of a
separate pluggable resistor carrier assembly. Extra current conversion resistors are available as accessories.
ISOLATED RTD INPUT MODEL 5834
This RTD input module provides 3 wire lead resistance compensation and can be connected to 2,3, or 4 wire RTDs. The
lead resistance effect is ± 0.02°Clfi. It provides a low drift sensor
excitation current of 0.2SmA for the SB34 or SB34-N or l.OrnA
for the SB34-C and produces an output signal that is linear with
temperature with a conformity error of ± 0.05% of span and
accuracy of ± 0.05% of span.
ISOLATED THERMOCOUPLE INPUT MODELS 5837,
5847
The isolated thermocouple model incorporates cold junction
compensation circuitry which provides an accuracy of ±O.soC
over the + SOC to + 45°C ambient temperature range. Open
thermocouple detection (upscale) is also provided. Standard
models are available for thermocouple types], K, T, E, R, S,
and B. Model 5B47 provides a linearized O-SV output.
ISOLATED WIDEBAND MILLIVOLT AND VOLTAGE
INPUT MODELS 5840, 5841
Models 5B40 and 5B41 accept millivolt and voltage signals
respectively and have a 10kHz bandwidth for interface to dynamic
signals.
11-98 SIGNAL CONDITIONING COMPONENTS & SUBSYSTEMS
58 SERIES MODULE OUTLINE
Dimensions shown in inches and (mm).
,--0590--1
15.0
I
I
T
2.250
~I'-r::m----'
(TOP)
PIN DESIGNATIONS
WRITEEN(O}
23
RESERVED
21
110 COM
19
+5V
17
INLO
-EXC
22
READEN(O}
20
VOUT
18
VIN
16
POWER COM
6
INHI
4
+EXC
2
SENSOR +
5
3
•
SENSOR-
+
+
-----tt--11~
2
3
4(5)\
THERMOCOUPLE
mV,V
+
4·20mA
RTD
Figure 3. 58 Series Input Connections
SIGNAL CONDITIONING COMPONENTS & SU8SYSTEMS
11-99
OUTPUT MODULE FEATURES
• Voltage Input Ranges: 0 to +5V or ±SV
• Process Current Output: 4-20mA or 0-20mA
• High Accuracy: ± 0.05%
• Reliable Transformer Isolation: 1500V rms CMV,
CMR=90dB
• Meets IEEE-STD 472: Transient Protection (SWC)
• Output Protection: 240V rms Continuous
GENERAL DESCRIPTION
The SB39 Current Output Module accepts a high level analog
signal at its input and provides a 4-20mA or 0-20mA process
current signal at its output. The module feature
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LED DISPLAY
BCD DATA
APPLICATIONS
Medicel/Scientific/Analytic Instruments
Data Acquisition Systems
Industrial Weighing Systems
Readouts in Engineering Units
Digital Thermometers
GENERAL DESCRIPTION
Analog Devices' model AD2010 represents an advance in pricel
performance capabilities of 3Y.. digit digital panel meters. The
~2010 offers 0.05% ±1 digit maximum error with bipolar,
smgle ended input, resolution of 100j.tV, and a common mode
rejection ratio of 60dB (CMRR) at ±200mV (CMV).
The AD2010 features a light-emitting-diode (LED) display
with a full scale range of 0 to ±199.9 millivolts, latched digital
data outputs and control interface signals, and leading zero display blanking. Automatic-zero correction circuitry measures
and compensates for offset and offset drift errors, thereby
providing virtually no error. Another useful feature of the
AD2010 is its 5V dc operation. The AD2010 can operate from
the users' 5V dc system supply, thereby eliminating the shielding and decoupling needed for line powered units when the ac
line must be routed near signal leads.
To satisfy most application requirements, the conversion rate
of the AD2010 is normally 4 readings per second. However, an
external trigger may be applied to vary the sampling rates from
a maximum of 24 readings per second down to an indefinite
hold time. The AD2010 can also be connected for automatic
conversion at its maximum conversion rate. During conversion,
the previous reading is held by the latched logic. The numeric
'----0/
POLARnY SIGNAL
{ OVERLOAD SIGNAL
OVERRANGE SIGNAL
STATUS SIGNAL
readout is available as BCD data. Application of the metering
system in a computer or data logging system is made easy with
the availability of the "overrange," "polarity," "overload,"
and "status" signals.
A simplified block diagram of the AD2010, illustrating the
features described above is shown in Figure 1.
IMPROVED NOISE IMMUNITY, ACCURACY AND
ZERO STABILITY
Dual-slope integration, as used in the AD2010 and as described
in the the?ry of operation section, offers several design benefits.
• Conversion accuracy, for example, is independent of both
the timing capacitor value and the clock frequency, since
they affect both the up ramp and down ramp integration
in the same ratio.
• Normal mode noise at line frequencies or its harmonics is
rejected since the average value of this noise is zero over the
integration period.
• To achieve zero stability, a time interval during each conversion is provided to allow the automatic-zero correction circuitry to measure and compensate for offset and offset drift
errors, thereby, providing virtually no zero error.
For detailed informadon, contact factory.
DIGITAL PANEL INSTRUMENTS 12-9
SPECIFICATIONS
(typical @+25°C and +5VDC unless otherwise noted)
DISPLAY OUTPUT
• Display consists of four LED's (0.27" (6.9mm) high).
for data digits plus 100% overrange and polarity
indication.
• Overload - three data digits display zeros
and flashes.
• Decimal Points - selectable at input connector.
• Leading "0" DIsplay Blanking - controlled externally.
INPUT
• Full Scale Range - 0 to ±199.9 mtlhvolts
• Automatic Zero
• AutomatIc Polarity
• Bias Current - 3nA
• DC Impedance - 100Mfi
• Overvoltage Protection - 20V sustained, SOY momentary
without damage.
• Decimal Points (3) - I1lummate with logic "1" t extinguish with logic "0".
ACCURACY
• MaxImum Error - O.OS% of reading ±1 dIgit
• Resolution - 0.1 milhvolt
• Temperature Range - 0 too +SOoC o~eratmg
-30 C to +8S C storage
• Temperature CoefficIent - ±SOppm/oC
NORMAL MODE REJECTION
• 4OdB@60Hz
COMMON MODE REJECTION
• 60dB @ ±200mV
CONVERSION RATE
• External Trigger - up to 24 conversions per second
• Internal Trigger - 4 conversions per second
• AutomatIc - A new conversion is initiated automatically
upon completion of conversion in process; conversion
rate will vary from 24/sec to 40/sec depending on input
magnttude.
• Hold and Read upon command.
CONVERSION TIME
• Normal ConversIon - 42ms max (full scale Input)
• Overload Conversion - 62ms max
INTERFACE SIGNALS
• DTLITTL Compatible
logiC "0"
logic "I"
IN
<0.8V
>2.0V
OUT
<0.4V
>2.4V
• Inputs
External TrIgger - Opera non In the "External Trigger"
mode requires that the "External Hold" input be a logiC
"0" or ground.
Negative TrIgger Pulses - Applying a logical "low" to
the "HOLD" input disables the Internal trigger. A
negatIve trtgger pulse (logic "I" to logic "0") of
1.0/JS minImum apphed to the "EXT TRIGGER" In·
put will initiate conversion in the same manner as the
internal oscIllator. The external trigger should not be
repeated. however. until the "status" indicates completion of the conversion in process.
PosItIve Truer Pulses - The "HOLD" mput can be
used to trigger the AD2010 from a "normally low"
signal with the "EXT TRIGGER" input open or logic "1".
Following a "hold" a new reading will b~ inttiated on the
leading edge of the "hold" sIgnal. Thus, a momentary
poslttve pulse on the "HOLD" input can be used to
trigger the AD2010. The drift correct interval, how·
ever, begins on the trailing edge of the pOSItive pulse,
so if the pulse width exceeds 1 ms, the conversion WIll
actually be inttlated by the internal trigger.
Maximum Conversion Rate· Automatic - The AD2010
can also be connected for automatic converSIon at its
maximum conversion rate by connecting the "status"
output back into the "hold" input. In this manner the
status signal going high at the end of one conversion
immediately initiates a new conversion. The pulses
appearing on the status line can be used to step a
multiplexer directly, since the built·in drift·correct
delay of 8.33ms will allow settling of the input prior
to converSIOn. A logic "0" applied to the "EXT TRIGGER"
will inhibit the automatic trigger mode.
External Hold - Logic "0" or ground applied to thIS in·
put disables the internal trillller and the last conversion is
held and displayed. For a n-;'-;' con~ersion under internal
control the input must be opened or at logic "1". For a
new conversion under external control, a positive pulse
of less than 1.0ms can be applied (as previously explained).
OUTPUTS
• 3 BCD DigIts (8421 POSItive True) • latched • 3TTL loads
• Overrange· logIC "I" -latched· 6TTL loads, indicates
overrange.
• Overload . logIc "0" indicates overload (>199.9mV)
logic "I" . latched - 6TTL loads, indicates
data valid.
• Polarity - logic "I" . latched· 6TTL loads, indicates
positive polarity input.
• Status -logic "0" - conversion in process
logic "I" - latched· 6TTL loads, indicates conversion complete.
POWER
• +SV dc ±S%, SOOmA
WARM UP
• Essenttally no~e to speCIfied accuracy
ADJUSTMENTS
• Range potenttometer for full scale caltbration. Calibra·
tion recommended every SIX months.
SIZE
• 3"W x 1.8"H x 0.84"D (76.2 x 45.7 x 21.3mm) (overall
depth for case and printed CirCUit board extenSion IS
1.40" (3S.6mm».
ORDERING GUIDE
• AD2010· Standard AD2010 as descrIbed above· tuned
for peak normal mode rejection at 60Hz and its
harmonics.
WEIGHT
• 4 oz. (113.5gm)
OVERALL DIMENSIONS
All dimensions are given in inches and (mm).
PIN "S"
0 0 3 0 ( 7 8 2 ) MIN
ML
(35 81
f=!======~--r
~ (2' 31 MAX
I I--- 3020 (76 71 MAX ---I 1~5 (3 941 MAX
1-----3420 (88 91 MAX ---I
LENS
~2[~L
~-----\--7'-'I~ ~X
(5'41
Specifications subject to change without notice.
12-10 DIGITAL PANEL INSTRUMENTS
(4581
~ANALOG
WDEVICES
Low-Cost, 3 1/2 Digit
Logic Powered DPM with LED Displays
AD2021 I
FEATURES
"Second Generation" MOS-LSI Design
Large 0.5" (13mml LED Displays
+5VDC Logic Powered
±1.999V, ±199.9mV or ±19.99V Full Scale Ranges
Limited Differential Input
Low Power Consumption: 2_0 Watts
Small Size, Industry Standard Case Design
APPLICA TIONS
General Purpose Logic Powered DPM Applications
Portable Applications Requiring Low Power Consumption
GENERAL DESCRIPTION
The AD2021 is a low cost, 3V, digit, +SV dc logic powered
digit~1 panel meter with large LED displays. While designed for
general purpose DPM applications, the small size, light weight
and low power consumption of the AD2021 make it an ideal
digital readout for modern, compact instrument designs.
THE BENEFITS OF "SECOND GENERATION" DESIGN
The AD2021 is designed around MOS-LSI (Metal-Oxide-Semiconductor, Large Scale Integration) integrated circuits, which
greatly reduce the number of components, and thereby the
size, and reduce power consumption to 2.0 watts. Both the
lower power consumption and fewer interconnections between
components promise greatly increased reliability, and the circuit design maintains the performance and features of earlier
DPMs. Large O.S inch (13mm) LED displays offer the visual
appeal of gas discharge displays with the ruggedness and lifetime of all solid state devices.
AD2021 uses the same pin connections as the AD2010 (except
in BCD outputs, of course) as a convenience to allow updating
designs to take advantage of the second generation design and
larger display of the AD2021. Each AD2021 receives a full
one week failure free burn-in before shipment_
'3
CLOCK
OL
14
BCD 1
t51
DIGIT 3
171
EXCELLENT PERFORMANCE AND EASY APPLICATION
The AD2021 measures input voltage over a full scale range of
±1.999V dc or ±199.9mV dc ("S" option) with an accuracy
of ±O.OS% reading ±0.02S% full scale ±1 digit. Using the
"limited differential" input first used on Analog Devices'
• AD2010, the AD2021 prevents ground loop problems and
provides 3 S to SOdB of common mode rejection at common
mode voltages up to ±200mV. Normal mode rejection is
40dB at SOHz to 60Hz.
BCD data outputs are provided in a bit parallel, character serial
format compatible to CMOS logic systems. For those applications requiring parallel BCD data, schemes for making the serial to parallel conversion are available. Controls to hold readings,
select decimal points and blank the display are provided.
DESIGNED AND BUILT FOR RELIABILITY
The AD2021 is packaged in Analog Devices' logic powered
DPM case size, only 1.2S inches (32mm) deep. The small size
of this DPM makes it easy to accommodate in any instrument
design, and since several other manufacturers now use the same
panel cutout for logic powered DPMs, this industry standardization allows. mechanical second sourcing. In addition, the
OR •
4,13
'4
"
BCD2
161
DIGIT 2
(121
4,13
'4
BCD.
tFI
"
4,13
'4
1/674lS04
"
}..
1
}
7475 QUAD LATCH
Figure 1. AD2021 Bit Parallel Character Serial to Full Parallel
Data Conversion. AD2021 Pin Connections are Shown in
Parentheses.
For detailed informatioo contact factory.
9
DIGITAL PANEL INSTRUMENTS 12-11
SPECIFICATIONS
(typical at +25°C and nominal power supply voltage)
DISPLAY OUTPUT
• Light emitting diode, planar seven segment display readouts, 0.5" (13mm) high for three data digits, 100% overrange and negative polarity indication. Overload indicated
by flashing display, polarity remains valid.
• Decimal points selectable at input connector.
• Display blanking on three data digits (does not affect
overrange digit, polarity sign of decimal points).
ANALOG INPUT
• Configuration: bipolar, limited differential
• Full Scale Range: ±1.999V ~r ±199.9mV ("S" option)
±19.99V ("V" option)
• Automatic Polarity
• Auto Zero
• Input Impedance: 100Mil (lMil - "V" option)
• Bias Current: 50pA
• Overvoltage Protection: ±50V dc, sustained
ACCURACY
• ±0.05% reading ±0.025% full scale ±1 digit'
• Resolution: ImV, 10mV ("V" option) or 100pV
("S" option)
• Temperature Range 2 : 0 to +50 oC operating; -25°C to
+85°C storage
• Temperature Coefficient: Gain: 50ppm/C
Zero: auto zero
• Warm-Up Time to Rated Accuracy: less than one minute
• Settling Time to Rated Accuracy: 0.4 second
DATA OUTPUTS (See Application Section for details on
data outputs)
• BCD Data Outputs: (CMOS, LP TTL or LP Schottky
compatible), bit parallel, character serial format.
• Digit Strobe Outputs: (CMOS, DTL, TTL compatible,
one TTL load). Logic "I" on any of these lines indicates
the output data is valid for that digit.
• Polarity Output: (CMOS, TTL, DTL compatible, one
TTL load). Logic "I" indicates positive polarity input,
logic "0" indicates negative polarity.
• Status: (CMOS or LP TTL compatible). When this signal
is at Logic" i"", the output data ,s valid.
• Clock: (CMOS, 'DTL, TTL compatible, one TTL load).
The clock signal is brought out to facilitate conversion
from character serial to parallel data.
• INTERFACING DATA OUTPUTS. The BCD data outputs
are in a bit parallel, character serial format. There are four'
BCD bit outputs (I, 2, 4, 8) and four digit outputs (lOo,10 1
102 , 103 ). The BCD digits are gated onto the output lines
sequentially, and the BCD bits are valid for the digit whose
digit line is high. The data is valid except when being updated
which occurs within 2 milliseconds after the status line
goes low.
REFERENCE OUTPUT
• A 6.4V ±5% analog reference output is made available.
This reference should be buffered and filtered if use in
external circuitry is desired.
NORMAL MODE REJECTION
• 40dB at 50-60Hz
COMMON MODE REJECTION
• AD2021: 35dB (dc -10kHz)
• AD2021/S: 50dB (dc -10kHz)
• AD20211V: 15dB (dc -10kHz)
COMMON MODE VOLTAGE
• ±200mV
CONVERSION RATE
• 5 conversions per second
• Hold and read on command
POWER INPUT
• +5V dc ±5%, 1.45 watts
CALIBRATION ADjUSTMENTS (See Application Section 'for
calibration instructions)
• Gain
• Zero
• Recommended recalibration interval: six months
CON~ROL
WEIGHT
• 4 ounces, (115 grams)
OPTIONS - ORDERING GUIDE
• Input Voltage Range: AD2021 - 1.999V dc Full Scale
AD20211S - 199.9mV dc Full Scale
AD20211V - 19.99V dc Full Scale
CONNECTOR
• 30 pin, 0.156" spacing card edge connector. Viking
2VK1SD/I-2 or equivalent.
• Optional: Order AC1501
INPUTS
• Display Blanking: (TTL, DTL compatible, 2 TTL loads).
Logic "0" or grounding blanks the three data digits only,
not the decimal points, overrange digit (if on) and polarity sign. Logic "I" or open circuit for normal operation.
Display blanking has no effect on output data and the
display reading is valid immediately upon removal of a
blanking signal.
• Hold: (CMOS, DTL, TTL compatible, lLP TTL load).
Logic "0" or grounding causes the DPM to cease conversions and display the data from the last conversion. Logic
"1" or open circuit for normal operation. After the
"Hold" input is removed, one to two conversions are
needed before the reading is valid.
• Decimal Points: Grounding or Logic "0" will illuminate
the desired decimal point. External drive circuitry must
sink 35mA peak at a 25% duty cycle when the decimal
points are illuminated.
12-12 DIGITAL PANEL INSTRUMENTS
SIZE
• 3"W x 1.S"H x 1.33"D (76 x 46 x 34mm)
• 1.90" (4I1mm) overall depth to rear of card edge connector.
• Panel cutout required: 3.175" x LillO" (SO.65 x 45.97mm).
NOTES
I Guaranteed at 25°C and nominal supply voltage
• Guaranteed
Specifications subject to change without notice.
1IIIIIIII ANALOG
WDEVICES
Low-Cost, 3 Digit
AC Line or Logic Powered DPM
AD2026* I
FEATURES
Third Generation 12 L LSI Design
Either Line Powered or Logic Powered
Large 0.56" Red Orange LEOs
Balanced Differential Input/Floating
1000V, CMV
Terminal Block Interface (ac Version)
High Reliability: >250,000 Hour MTBF
Small Size and Weight
Low Cost
GENERAL DESCRIPTION
The AD2026 is specifically designed to provide a digital alternative to analog panel meters. The AD2026 is available either
logic powered (+5V dc) or ac line powered. Most of the
analog and digital circuitry is implemented on a single 12L
LSI chip, the AD2020. Only 13 additional components are required to complete the AD2026 +5V dc version. The entire
dc version is mounted on a single 3" X 1 5/S" PCB. AC line
power is achieved with the addition of a second PCB containing the ac power transformer and power supply circuitry.
The AD2026, on both the ac line and logic powered versions,
offers as a standard feature, 0.56" high LED Displays. Brightness
is enhanced on both versions due to the Red Orange lens. In addition to the Red Orange lens, the AD2026 is also available
with a dark red lens for applications where maximum brightness is not required and minimum backlighting is desired.
A unique patented case design utilizes molded-in fingers, both
to capture the PCB in the case and to provide snap-in mounting of the DPM in a standard panel cutout. No mounting hardware of any kind is used. The dc version occupies less than I"
of space behind the panel. The lme powered version offers the
same mounting features but occupies 2 112" of behind-panel
space.
EXCELLENT PERFORMANCE
The AD2026 offers the instrument designer digital accuracy,
resolution and use of readout while occupying less space than
its analog counterpart. Other features of analog meters such as
reliability and instantaneous response are retained in the
AD2026.
The AD2026 measures and displays inputs from -99mV to
+999mV, with an accuracy of 0.1% of reading ±1 digit. Zero
shift is less than one bit over the full operating temperature
range, resulting in the same performance as a DPM with auto
zero. The balanced differential input of the dc powered
AD2026 rejects common mode voltages up to 200mV, enough
to eliminate most ground loop problems. The floating differential input inherent in the ac line powered verSIOn offers
1000V of common mode voltage rejection.
Optionall0.0V full scale (F.S.) range is available on the ac
line version that will accept inputs from -o.99V to 9.99V.
WIRING CONNECTIONS
For Balanced Differential operation with the AD2026 dc version, connect input as shown in Figure 1. The common mode
loop must provide a return path for the bias currents internal
to the AD2026. The resistance of this path must be less than
100kn and total common mode voltages must not exceed
200mV.
For applications where attenuation is required, scaling resistors can be connected between pins 6 and 7 and between
pins F and H. Pin 5 must be used as the High Analog Input
when scaling resistors are used and pin 4 when they are not.
Pin E is the Analog Low Input.
\61
'7>
EXTERNA~
SCAlING,L L-....,
IF}
RESISTORS
IE)
ECOMMON MODE
(HI
R(,100k5ll
Figure 1.
Connection to the ac line powered AD2026 is via the terminal
strip on the rear. AC line power is connected to terminals 4
and 5 and the signal inpu t is connected to terminal 1 (Analog HI) and 2 (Analog Ground).
·Covered by patent numbers. 4,092,698,29,992, 3,872,466,
and 3,887,863.
DIGITAL PANEL INSTRUMENTS 12-13
SPECIFICATIONS
(typical at +25°C and nominal supply voltage unless otherwise noted)
DISPLAY OUTPUT
• Light emitting diode, planar seven segment display readouts, 0.56" (14.6mm)
POWER INPUT LOGIC POWER'
• Converter. +SV ±5%, 0.2 watts typ, 0.33 watts max
• Display: +5V ±40%, 0.45 watts typ, 0.75 watts max
high (orange)
•
•
•
•
OverJoad Indication: EEE
Negative IndlcatJOn: -XX
Negative Overload Indication'
DeO A
Conductor to pm A IS color coded. Sequence of nbbon connecOons
A, 1, B, 2, C, 3, etc.
The A02026 ac version
ORDERING GUIDE
AD2026
Power Input
+5V dc
90-129Vac
198·264Vac
Full Scale InputS
1V dc Full Scale
IOV dc Full Scale 6
Lens 5
Red Lens
Red Orange Lens
CONVERSION RATE
• 4 conversIOns per second
• Hold and read on command (dc versIOn only)
CONTROL INPUTS
Display Blanking/Display Power Input, (dc versIOn only) The display of the
AD2026 can be blanked by removal of power to the display power mput, With
no effect on convenaon CirCUitry. If external logic sWltchmg IS used, the display
requires llOmA peak (85mA average) when Illummated.
(A, B or 3).
To Illuminate decimal pomts on ac verSion, remove shroud and bndge
appropnate solder pad (A, B or 3).
3:1_7_5 ±O.OIS" X 1.810 ±O.OIS"
::t:U"HSmmJ
CONNECTIONS
A 10-pm T&B/Ansley 609-1000M With two feet of 10 conductor nbbon
cable IS avaIlable. Order AC2618 (de version, only).
NORMAL MODE REJECTION
• 30dB at 50-60Hz (ac version)
•
't:J.'Y'
WEIGHT
• 1.8 ounces (53 grams) (dc versiOn)
• 7 ounces (198 grams) (ac versiOn)
COMMON MODE REJECTION (1kn source Imbalance, dc to 1kHz)
• SOdS, ±200mV common mode volrage (dc version)
• l16dB (96dB on 10V range), IOOOV rms max CMV (ac version)
DECIMAL POINT
• To Illuminate decimal 'POints on dc VerSIOn, ground appropnate pm
~:~e!"c~~o~~ ~:q~~r~~
•
ACCURACY
• ±O.l% ±1 digIti
• Resolution lmV or lOmV
• Temperature Range 2 -WoC to +60°C operating, -25°C to +80°C storage
• Temperature Coefficient Gain 5Opprr~tC
Zero I~V / C (essentially auto zero)
• Warm-Up Time to Rated Accuracy Instantaneous
• Settling Time to Rated Accuracy. 0.3 second for full mpu t voltage
SWing (dc version), 0.75 second for full mput voltage swmg (.iC version)
Hold (de versIOn only) When the Hold mput IS at Logic "0", grounded or open
CirCUIt, the AD2026 wIll convert at 4 conversIOns per second. If a voltage of
O.6V to 2AV IS applied to thiS mput, the DPM will stop converting and hold the
last readmg. A 12k!l reSistor m senes With thiS mput to +5V will prOVide the
proper voltage input. (Consult factory for "HOLD" on ac versIOn.)
Gain
Zero
Recommended recahbratlon mterval SIX months
IS
IS
complete With terminal strIP for easy mterface
:}-,,,,,J 1
;}-ENTER~
; } - ENTER - - - - - - '
NOTES
I
Guaranteed at +25"( and nommal supply voltage.
2 Guaranteed.
3When the same power supply IS used to power both display and converter, +5V, ±5%,
0.65 watts tyPiCal, 0.9 watts max IS required.
.. Olillenslons for ac hne powered verSIon 3 43"W X 2.0"H X 2 44"0 (87mm X 52mm X
63mm)
'No Charge Options
10V de full scale optiOn IS aVallable on ae power only
SpeCIfications subject to change WithOUt notice.
f
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
I
"~~'i"
n.
MODEl AD2026
{4521!
.11
:IT
Jl
L - - " L.---"I'---"
AC VERSION
" .
{1271
~5
IT
--Il~~1 t-PIN CONNECTIONS
AC VERSION
DC VERSION
"N
1
NC
4
5
ACHI
AClO
2
"N
A
FUNCTION
Inut
Ground
"".
,
F·
6*
Sa.." Arm of Scaling
Res'$to,DIY'~r
7·
Oe(:lmal Po,nt XX X
Dec..",,1 POint XXX
Power Ground
Hold
AnalogG,ound
Shunt Arm of Scahng
fies.$tGrD.vlCie.
Shunt Arm of Sc:ailng
R ,to,Dtv,der
SerIeS Arm 01 Sc:along
ReslStorD,y,dar
"NOT NORMAll V USED AllOWS CONVENIENT
MOUNTING OF SCALING RESISTORS
12-14 DIGITAL PANEL INSTRUMENTS
Microprocessor-Based
Thermocouple Meters
IIIIIIIIIII ANALOG
WDEVICES
AD2050/AD2051
I
FEATURES
Automatic Self-Calibration for Gain, Offset, Cold Junction
Compensation and Thermocouple Linearization
J, K, T, E, R, S Thermocouple Selections (AD2050)
Universal Meter (AD2051), User Programmable
Character Serial ASCII Digital Output
Optional Linearized Analog Output: 1mV/degree
Optional Isolated 20mA Loop/TTL Serial Outputs
Meets DIN/NEMA Dimension Specifications
Temperature Ranges: -265°F to + 1999°F
-165°C to + 1760°C
Power Options: 120V ac, 240V ac, + 7.5V dc to + 28V dc
APPLICATIONS
Temperature Monitoring in Laboratory, Manufacturing,
and Quality Control Environments
Process Control Temperature Measurements
Remote Data Logging
GENERAL DESCRIPTION
The AD20S0 and AD20S1 are high performance single channel
3 '/z digit thermocouple meters that can measure temperatures
accurately between - 26S and + 1999 in degrees Celsius or
Fahrenheit. The AD20S0 is supplied factory programmed to
interface directly with any of the following six thermocouple
types: J, K, T, E, Rand S. The AD20S1 is a universal instrument
in which the user selects one of the six thermocouple types via
switch programming. Being microprocessor based, all gain and
offset error correction, cold junction compensation, thermocouple
linearization, and °C;oF scaling are automatically performed in
firmware.
The AD20S0 and AD20S1 display temperature information on
large 0.S6" (l4.3mm) high LEDs. Digital information is provided
in standard ASCII character serial format with rate selection for
easy interface to printers, terminals, and other peripherals. For
remote data acquisition applications, an optional isolated 20mA
serial loop/TTL compatible interface is available. Also an optional
analog output linearized to ImV/degree is provided for driving
recorders and other analog instruments. Selection of °C or OF
scaling is accessed by removing the front panel lens and setting
the selector switch to its proper position.
The AD20S0 and AD20S I can also be ordered with any of the
following power versions: 120V ac, 240V ac, or + 7.sV dc to
+ 28V dc. Input overvoltage protection for 300V peak (thermocouple to ac line shorts) and common mode voltages as high
as 1400V peak (ac version) with overrange and open thermocouple
detection are provided. These instruments are rated for operation
over the + 10°C to + 40°C temperature range. Testing is performed
per MIL-STD-202E Method 103B to insure specified operation
over various relative humidity conditions. The AD20S0 and
AD20S I are supplied in rugged high impact plastic cases that
meet DIN/NEMA standard dimensions.
AD20S0/AD20S1 FUNCTIONAL BLOCK DIAGRAM
INTEGRATOR
•
r-----'
COMPARATOR
I
I
I
I
I
I
M
I
c
1..._ _..1\1
R
°RP
°C
E
S
5
~
L.._ _
~_--'''
DIGIT
ASCII INFO
t----,/I
SElF-CAUBRAnON CHANNEL SELECT
}
'OPTIONALI
For detailed information, contact factory.
DIGITAL PANEL INSTRUMENTS 12-15
--
SPECIFICATIONS (typical
@
+ 25°C and rated supply voltages unless otherwise specified)
THERMOCOUPLE INPUTS
• Thermocouple Types: J, K, T, E, S, R
• Input Impedance: > 100M!}
• External (Lead) Resistance Effect: <20,.V per 350n of Lead
Resistance
• Cold Junction Compensation Error: ± O.5°C max ( + lOoC to
+ 40°C)
• Open Thermocouple: + EEE Display; + EEEE ASCII
DigitalOutputj +2.048VAnalogOutput
• Thermocouple Short to ac Line: Internal Protection Provided
to 300V peak (200V ac rms)
• Common Mode Voltage: 1400V peak (dc or ac), between
Input and Power Line Ground(ac Versions)
• Common Mode Rejection Ratio: > 130dB with 2S00 Source
!!!!ba!ance (ae Versio;,ns); (cleto;, 60Hz)
• Normal Mode Rejection Ratio: >8OdB@ SO/60Hz
DIGITAL OUTPUTS
• Character Serial ASCII
Data: Nine transmitted characters, (each 7 bits plus ~trobe)
Drive Capability: 2TTL loads, CMOSffTL compatible
Strobe: Negative transition determines when character serial
data is valid. CMOS/TTL compatible.
Character Rate: Selectable onPI (pin 32)
Grounded: 25 characters/sec. (SLOW)
Open: 100 characters/sec. (FAST)
• Isolated Serial Output (Optional)
Data: Asynchronous ASCII 20rnA current loop
(Optically isolated to ± 600V peak)
Baud Rate: Selectable on PI (Pin 32)
Grounded: 300 baud (SLOW)
Open: 1200 baud (FAST)
Distance: 10,000 ft. max
• Serial Output (Nonisolated, Optional)
Data: Serial ASCII
Drive Capability: 2TTL Loads, CMOSITTL compatible
Baud Rate: (same as Isolated Serial Output)
• Overrange: ± EEEE
• Mmunum Time Between New Data Update: ISOms
DIGITAL INPUTS
• REQ: Low-Level Tnggered: Must go low at any time other
than during data transmisslOn to be recognized. REQ line
taken low during data transmiSSIon will not be acknowledged
and the ASCII digital output transmission will not occur. Display readings are not effected by REQ.
• SERIAL INPUT (Optional): Edge Triggered, Current On to
Current Off: Must be tnggered at any time other than during
data transmission to be recogmzed. Serial Input triggered
during data transmiSSIOn will not be acknowledged and the
20mA isolatedITTL compatible serial output transmission
will not occur. DIsplay readings are not effected by Serial
Input.
ANALOG OUTPUT (OPTIONAL)
• Voltage: ImV/degree,lineanzed
• Current: ±2mAmaxdrive
• CMV: 1400V peak Cae or dc) Peak between Analog Output
Ground & ac Power Line Ground
• Overrange: +2.048V, -0.S12V
ACCURACY
• Temperature Resolution: I °C/I OF
• All Ranges are Guaranteed Monotonic
• Range Temperature Coefficient: ± 2Sppm/"C typ, ± 60ppiTJ
°Cmax
• Readout Accuracy (q,2SoC:
Sensor
Type
J
J
K
K
T
T
E
E
S,R
S,R
Range
- 165°C to 760°C
-265°Fto 1400°F
- 50°C to 1250°C
- 58°F to 1999°F
-150°Cto400°C
- 238°F to 752°P
-100°C to 870°C
- 148°P to 1598°F
+ 300°C to 1760°C
0° to 299"C
+572°Ptol999°F
+ 32°F to 571°F
Accuracy
±0.7°C
±1.3"F
±0.9°C
±1.6°F
±0.8°C
±1.4°F
±1.0"C
±2.0°F
± I.soC
±6.O"C
±3.0°F
±12.0°F
± Jl2LSD
± 1/2LSD
± Jl2LSD
± Jl2LSD
± 1/2LSD
± 1/2LSD
± I12LSD
± 1/2LSD
± JlZLSD
± Jl2LSD
± 1/2LSD
± 1/2LSD
ANALOG TO DIGITAL CONVERSION
• Techmque: Offset Dual Slope WIth Gain and Offset Error
CorrectIon
12-16 DIGITAL PANEL INSTRUMENTS
• Rate: 2.5 Conversions/Second Typical
• Input Integration Period: lOOms for SO/60Hz
Noise Rejection
POWER REQUIREMENTS (Choice of Three Supply Ranges)
• ac: 90V ac to 132Vac @ 25mA (47Hz to 500Hz)
198Vac to 264V ac @ 12.5mA (47Hz to 500Hz)
• dc: + 7.5V to + 28V dc @ 200mA (Protected Against
Supply Reversals)
DISPLAY
• Type: Seven Segment Orange LED 0.56" (J4.3mm) high
• Polarity Indication: "+" or "-" displayed
• Overrange Indication: ± EEE
• Display Test: At Power Turn-On, 3 Second Display of
. "+ 1888" Tests all Segments of Display
ENVIRONMENTAL
• Rated Temperature Range:
+ 10 e to + 40°C
D
• Operating Temperature Range: -lO"C to + SO°C
• Storage Temperature Range: - 40°C to + 85 D C
• Relative Humidity: Meets MIL-STD-202E, Method 103B
DIMENSIONS
• Case: 3.78" x 1.89" x 5.13" (96.8mm x 48.9mm x
13J.3mm), high impact molded plastic case. DININEMA
Standard
• Weight: 15.2 oz (431 grams) max, ac powered
12.0 02 (341 grams) max, de powered.
RELIABILITY
• Burn In: 168 Hours at
+ SW'C and Power ON/OFF Cy-
cles.
• Calibration: NBS Traceable
• Recalibration: Recommended IS-Month Intervals
• Warranty: 12 months
CONNECTOR
One 44 pin 0.1" (2.54mm) spacing card edge connector
Vlkmg 3VHZ2/1 JN5 or equivalent
Optional: Order AC2630
P1
ASCII DIGITAl
OUTPUT SOARD
o
Rear Panel View
ORDERING GUIDE
AD2051/_/_/_
'""'It
THERMOCOUPLE TYPE*
J
t
j
K
ENTER
T
E
R
S
POWEROPTION*
,
(I) 120Vac
(Z)Z40Vac
(3) +7.5Vdcto +28Vdc
ANALOG OUTPUT OPTION
(A) Contams .{\.nalogOutput
(Blank) Does Not Contam Analog Output
SERIAL OUTPUT OPTION
(S) Contains Serial Output
(Blank) Does Not Contain Serial Output
J
ENTER
!
ENTER
f ENTER----.J
·Only one opuon can be ordered The thermocouple type does not need to be specmed
when ordenng the AD205151flce It 15 user programmable
Speclficatlons subject to change Without notIce
r'III ANALOG
WDEVICES
Microprocessor-Based Autoranging
RTDIThermocouple Meters
AD2060/AD2061 I
FEATURES
Temperature Ranges: -328°F to + 1562°F
- 200°C to + 8500C
Autoranging: 0.1° from -199.9° to + 199.9°; 1°2:200°
Sensor Selection (AD2060): RTD 1000 Platinum
(l< = 0.00385. 0.00390. 0.00392 or 22520 Thermistor
Universal Meter (AD2061) Sensor User Programmable
Switch Selectable Sensor Configuration: 2. 3 or 4-wire
7-Bit ASCII Character Serial Data Output
Automatic Self-Calibration for Gain. Offset. Excitation
and Sensor Linearization
Optional Linearized Analog Voltage Output:
1mV/degree
Optional Isolated 20mA ASCII LoopmL Serial Outputs
APPLICATIONS
Temperature Monitoring in Laboratory. Manufacturing
and Quality Control Environments
Process Control Temperature Measurements
Remote Data Logging
GENERAL DESCRIPTION
The AD2060/AD2061 are high performance single channel 3'1z
digit RTDlThermistor meters that can measure temperature
accurately between - 328°F and + 1562°F ( - 200°C and + 850°C).
Both meters offer autoranging from O.loC/F to IOC/F. The
AD2060 is supplied factory programmed for one of four sensor
types: 1000 Platinum RTDs: a =0.00385, 0.00390, 0.00392 or
a 22520 Thermistor. The AD2061 is a universal meter in which
the user selects one of the four sensor rypes via switch programming. The microprocessor based AD2060/AD2061 provides
gain, offset and excitation error correction, linearization and OCt
OF scaling in firmware. The AD2060/AD2061 display temperature
information on large 0.56"(14.3mm) high LEDs. Digital information is provided in 7-bit standard ASCII character serial
format with baud rate selection for easy interface to printers,
terminals and other peripherals. For remote data acquisition
applications, an optional isolated 2-wire 20rnA ASCII serial
loop/TTL compatible interface is available. For driving recorders
or other analog instruments, an optional linearized analog voltage
output of ImV/degree is available. Selection of °c or OF scaling
is accessed by removing the front panel lens and setting the
selector switch to its proper position.
The AD2060/AD2061 can be ordered in one of the following
power versions: 120V ac, 240V ac or + 7.5V dc to + 28.0V dc.
Input voltage protection of 180V peak (RTD short to ac line),
common-mode voltage to 1400V peak (ac version) with overrange
and open sensor detection is provided. These meters are rated
for operation over the 0 to + 40°C temperature range. Each
AD2060/AD2061 is burned-in for 168 hours @ 50°C with on/off
power cycles for increased reliability.The AD2060/AD2061 are
supplied in rugged molded plastic cases that meet UL94V-0 and
DININEMA standard dimensions.
AD2060/AD2061 FUNCTIONAL BLOCK DIAGRAM
For detailed infonnation, contact factory.
DIGITAL PANEL INSTRUMENTS 12-17
•
SPEC IFICATIONS (typical
RTDINPUTS
• RTDTypes:
@
+ 25"C and rated supply voltages unless otherwise specified)
ANALOG TO DIGITAL CONVERSION
• Technique-: Offset Dual Slope with Gain and Offset Error Correction
• Rate: 2.5 Conversions/Second Typical
• Input Integration Period: lOOms for SO/60Hz Noise Rejection
lOon Platinum
a
~ 0.00385
(Per DIN 43760)
a~0.00390
a~0.00392
• Conftguration: 2, 3 or 4 Wtre
• Excitation Current: O.2SmA nommal
• External Lead
Resistance Effect: Automabcally Compensated for 3 & 4 wtre configuratIons
• Lead Resistance: SOO/Lead max; RTD + Lead Resistance must be less than 4000
• 3 Wtre Error: 2.SoC/O of impedance Imbalance
• Open Sensor: DISPLAY + EEE
• RTD Shon to ac Lme: Internal protection provided to 180V peak (BOV rms)
• Maximum Common-Mode Voltage: 1400V peak (ae or de) between input and power
line ground (ae version)
# Coi'fuTavii-:ytWIC Ri::jection Ratao. IMdB oil. power to RTD inPUt
• Normal Mode ReJection: 60dB @ SO/60Hz
THERMISTOR INPUTS
• Thermistor Type: Series 400 R = 22520
• Configuration: 2 Wlle
• Open Sensor: DISPLAY -EEE
ACCURACY
• Temperature Resolution: Autoranging (0.1° from -199.9° to + 199.1)0,1°;::-:200")
• All Ranges Guaranteed Monotonic
• Range Temperature Coefficient: 20ppmFC typ, 3OppmfOC max
• Readout Accuracy· @ + 2SoC
SeDsor
Raall"
loonRTDa~0.00385
loon RTD a
~ 0.00392
loonRTDa~0.00390
Thermistor R = 22520
- 200"C to + 850"C
- 328"Fto + 1562"F
- 2000C to + 64O"C
- 328"F to + 1184"F
- 200"C to + 640"C
- 328"Fto + 1184"F
- 30"C to + lOO"C
-22"Fto +212"F
Accuracy
±O.3"C± 1/2LSD
±0.6"F± 1/2LSD
± 0.3OC ± 112LSD
± 0.6"F ± 1I2LSD
± 0.3"C ± 112LSD
±0.6"F± 112LSD
± 0.4"C ± 1I2LSD
±0.8"F± 1I2LSD
·Readout Accuracy: Includes Gain and Offset Errors. Recommended
Recalibration Interval IS-MONTHS.
DIGITAL OUTPUTS
• Character Senal ASCII
Data: Eleven transmitted characters, (each 7 bits plus strobe)
Drive Capabihty: 2TIL loads, CMOSrrTL compatible
Strobe: Negative transition determines when character serial data IS vahd. CMOSITTL
compatible.
Character Rate: Selectable on PI (Pm 32)
Grounded: 2S characters/sec, (SLOW)
Open: 100 characters/sec. (FAST)
• Isolated Senal Output (Optional)
Data: Asynchronous ASCII 20mA current loop (Optically isolated to ± 600V peak)
Baud Rate: Selectable on Jl (Pin 32)
Grounded: 300 baud (SLOW)
Open: 1200 baud (FAST)
Distance: 10,000 ft. max
• Nomsolated Senal Output (Ortional)
Data: Senal ASCII
Drive Capability: 2TIL Loads, CMOSfITL compatible
Baud Rate: (same as h.olated Serial Output)
• Overrange: ± EEE.E
• Muumum Tune Between New Data Update: I sOms
DIGITAL INPUTS
• REQ, Low-Level Triggered: Must go iow at any time other than during ciala
transmission to be recogruzed. REQ Ime taken low during data transmission will
not be acknowledged and the ASCII digital output transmission will not occur.
Display readings are not effected by REQ.
• SERIAL INPUT (Optional): Edge Triggered, Current On to Current Off: Must be
tnggered at any tune other than during data transmission to be recognized. Serial
Input triggered during data transmiSSion will not be acknowledged and the 20mA
lsolatedfITL compatible serial output transnussion will not occur Display readings
are not effected by Serial Input.
ANALOG OUTPUT (OPTIONAL)
• Voltage: ImVfdegree, linearized
• Current: ± 2mA max drive
• CMV: 1400V peak Cae or de) between Analog Output Ground & ac Power Line
Ground
.Overrange: +2.048V. -O.SI2V
• Accuracy: ± 2mV from Display Readmg
12-18 DIGITAL PANEL INSTRUMENTS
POWER REQUIREMENTS (Choice of Three Supply Ranges)
• ac: 90V ac to 132V ac @ 2SmA (47Hz to SooHz)
198Vac to 264V ac @ 12.SmA (47Hz to SooHz)
• de: +7.SV to +28V de @ 200mA (Protected Against Supply Reversals)
DISPLAY
• Type: Seven Segment Orange LED 0.S6" (I4.3mm) high
• Polarity Indication: "+" or .. --" displayed
• Overrange Indication: ± EEE
• Display Test: At Pow'!r Turn-On, 3 Second Display of "+ 188.8." Tests all
SCgiii<::iits of Display
ENVIRONMENTAL
• Rated Temperature Range: 0 to + 4O"C
• Operating Temperature Range: -10"<: to + SOOC
• Storage Temperature Range: -40°C to +8SoC
• Relative Humidity: Meets MIL-STD-202E, Method 103B
(0 to 90%. Noncondensing)
DIMENSIONS
• ease: 3.78" x 1.89" x 5.13" (96.8mm x 48.9mm x 131.3mm), ru88ed molded
plastic case. Meets UL94V..o and DININEMA Sumdard dunensions
• Weight: IS.2 oz (431 grams) max, ae powered
12.0 oz (341 grams) max, de powered.
RELIABILITY
• MTBF: >SS,OOO hours calCUlated
• Bum In: 168 Hours at + SO°C and Power ON/OFF Cycles.
• Calibration: NBS Traceable
• Recalibration: Recommended IS-Month Intervals
• Warranty: 12 months
CONNECTOR
One 44 pin O.l~ (2.S4mm) spacing card edge connector Viking 3VH22fl ]NS or
equivalent
Optional: Order AC2630
Rear Panel View
ORDERING GUIDE
AD2061
I I I
1_1_1_
LLI_I_
S~~:S~~~~:inumRTDa~0.00385~J
AD2060
(390) loon Platinum RTD a ~ 0.00390 ENTER
(392) loon Platinum RTDa ~ 0.00392
(2252) Thermistor R ~ 225m
POWEROPTION*
(1)120Vac
}
(2) 240V ac
ENTER
(3) + 7.5V dc to + 28Vdc
ANALOG OUTPUT OPTION
(A) Cantains Analo8 Output
} ENTER
(Blank) Does Not Cnntain Analog Output
SERIAL OUTPUT OPTION
(S)Cantains Serial Output
} ENTER _ _ _ _ _--'
(Blank) Does NotCantain Serial Output
*Only ooe optioo can be ordered. The sensor type does Dot Deed to be specified
when ordering the AD2061 since it is user programmable.
Specifications subject to change without notice.
~ANALOG
WDEVICES
Microprocessor-Based Autoranging
Thermocouple Meters
AD2070/AD2071 I
FEATURES
Autoranging (0.1° _ 1°)
4 1/2 Digit Resolution
Automatic Self-Calibration for Gain, Offset, Cold
Junction Compensation and Thermocouple
Linearization
J, K, T, E, R, S, C, B, J DIN, and T DIN Thermocouple
Selection
Universal Meter (AD2071), User Programmable for all
Thermocouple Types
Four Port Isolation: Input, Power, Digital Output
and Analog Output
Optional Isolated and Linearized Analog Voltage Output 1mV/Degree
Optional Isolated 20mA LooplTTL Serial Data Output
Optional Isolated RS-232/TTL Serial Data Output
Heavy Gauge Rugged Metal Case
GENERAL DESCRIPTION
The AD2070/AD2071 are high performance, microprocessor
based, autoranging, single channel thermocouple meters that
can measure temperature accurately from - 328°F to + 4200°F
(- 200°C to + 2315°C). The AD2070 is supplied factory programmed for any of the following ten thermocouple types: J, K,
T, E, R, S, C, B, J DIN, and T DIN. The AD2071 is a universal
meter in which the user selects one of the ten thermocouple
types via switch programming. Both meters offer autoranging
from O.loCfF to lOCfF. The microprocessor based AD20701
AD2071 provides gain and offset error correction, cold junction
compensation, thermocouple linearization and °CfF scaling in
firmware.
The AD2070/AD2071 display temperature information on large
0.56" (l4.3mm) high LEDs. Digital information is provided in
standard ASCII character serial format with rate selection for
easy interface to printers. For remote data acquisition applications,
an optional isolated 20rnA serial loop or RS-232 compatible
interface is available. For driving recorders or other analog
instruments, an optional isolated and linearized analog voltage
output of ImV/degree is available. Selection of °C or OF scaling
is accessed by removing the front panel lens and setting a selector
switch.
The AD2070/AD2071 can be ordered in one of the following
power versions: 120V ac, 240V ac or +7.5V dc to +28.0V dc.
Input overvoltage protection rating is 300V peak (thermocouple
to ac line shorts). The common-mode voltage mting is 1400V
peak. Overrange and open thermocouple detection are provided
in all models. Analog output and digital outputs are isolated to
500V peak from power, input and output sections. Each meter
is burned-in for 168 hours at 50°C with on/off power cycles for
increased reliability. These meters are rated for operation over a
+ lOoC to + 40°C range. The AD2070/AD2071 are supplied in a
heavy gauge, rugged metal case that meets DIN/NEMA standard
dimensions.
AD2070/AD2071 FUNCTIONAL BLOCK DIAGRAM
opnoNAL
AC OR DC}
}
20rnA
LOOP
INPUT
POWER
O,,"'ONAL
}
RS·232
For detailed information, contact factory.
DIGITAL PANEL INSTRUIV!ENTS 12-19
SPEC IFI CAli ONS
(tPaI@
+25"1: and IlIIIId supply voIIlIps IIIIess oIIIerwise specified)
THERMOCOUPLE INPUTS
THERMOCOUPLE TYPES:
J, K, T, E, R,
B, C, J DIN arut T DIN
INPUT IMPEDANCE:
lOOMO
EXTERNAL LEAD RESISTANCE EFFECT:
<20",V per 3500 of Lead rnistanc:e
COLD JUNCTION COMPENSATION ERROR:
± 0.3"<: max ( + IO'C to + 4O"C)
OPEN THERMOCOUPLE:
+EEEE Display; +EEEE.E ASCII DIGITAL OUTPUT: +3.SOOV
ANALOG OUTPUT
THERMOCOUPLE SHORT TO AC LINE:
Intema1 Protection Provided to 300V peak, (200V ae rms)
COMMON-MODE VOLTAGE:
1-400V peak (de or ac), Between Input and Power Line Ground
COMMON-MODE REJECTION RATIO:
> I30dB with 25011 Source Imbalance (dc to 60Hz)
NORMAL-MODE REJECTION RATIO:
>80dB @ SO/60Hz
s,
DIGITAL OUTPUTS
ISOLATED CHARACTER SERIAL ASCII (Standard)
DATA:
Eleven transmitted eharacters, each 7 bits plus strobe
DRIVE CAPABILITY:
2TTL Loads, CMOSITfL compatible
OVERRANGE: ± EEEE.E
STROBE:
poaiiive transitino determinea wben eharacter serial data is valid.
CMOSfITL compatible.
ISOLATION:
,
SOOV Between Input, Analog Output and Power Input
CHARACTER RATE:
Selectable on PI (Pin 20)
Grounded: 2S Characters/sec. (SLOW)
Open: 100 Characterslaec. (FAST)
ISOLATED SERIAL OUTPUT (0ptinnaI)
DATA:
Aayncbronous ASCII 20mA current loop or RS-232
BAUD RATE:
Selectable on PI (Pin 20)
Grounded: 300 baud (SLOW)
Open: 1200 baud (FAST)
OVERRANGE:
±EEEE.E
DISTANCE:
SO ft. (RS-232), 10,000 ft. (20mA loop)
ISOLATION:
SOOV Between Input, Analog Output and Power Input
ISOLATED SERIAL OUTPUT
DATA:
Serial ASCII TTL
DRIVE CAPABILITY:
2TTL Loads, CMOSITTL Compatible
BAUD RATE:
(same as above)
OVERRANGE:
±EEEE.E
ISOLATION:
SOOV Between Input, Analog Output and Power Input
MINIMUM TIME BETWEEN NEW DATA UPDATE:
lOOms
DIGITAL INPUTS
REQ: LOW-LEVEL TRIGGERED:
Must go low at any time other than during data transmission to be
recognized. ~ line taken low during data transmission will not be
acknowledged and the ASCII digital ~ut tranantission will not occur.
Display readings are not effected by REQ.
SERiAL INPUT: EDGE TRIGGERED, CURRENT ON TO CURRENT OFF
Must be ~ at any time otber than during data transmission to be
recognized.
Input triggered during data transmission will not
be acknowledged and the isolated 20mA 1oop/TfL or isolated RS·2321TfL
compatible serial ou~t transmission will not occur. Display readings
are not effected by Serial Input.
ISOLATED ANALOG OUTPUT (0P'l10NAL)
VOLTAGE:
ImV/degree, Fahrenheit or Celsius linearized
CURRENT:
±2mA max
OVERRANGE:
+ 3.S00V, - 0.328V
ACCURACY:
, ± Zmv from Display Reading
ISOLATION":
SOOV Between Input, Digital Output and Power Input
ACCURACY
TEMPERATURE RESOLUTION:
Autoranging O.I"CI"F - I"CI"F
RANGE TEMPERATURE COEFFICIENT:
2OppmI"C tvp. ±4OppmI"C max (of Reading)
AD Rangea are Guaranteed Monotonic.
POWER REQUIREMENTS (Cboice of Tluee Supply Ranges)
ae:
90V ae to 132V ac @ 25mA (de to 1kHz)
198V ac to 264V ae @ 12.5mA (dc to 1kHz)
de:
+ 7.SV to + 28V de @ 600mA (Protected Agaiust Supply Reversals)
DISPLAY
TYPE:
Seven Segment Orange LED 0.56" (14.3mm) high
POLARITY INDICATION:
"+" or "-" displayed
OVERRANGE INDICATION:
±EEEE
DISPLAY TEST:
At Power Tum-On, 3 Second Display of" + 1888.8." Tests All Segments
of Display
DIMENSIONS
CASE:
3.78'x 1.89" x 6.7S" (96.8mmx48.Ommx 17I.Omm), ragged
aluminum case. DlNINEMA Standard.
PANEL CUT OUT: 3.622" + 0.031'(92 + ,8)mm x 1.771 + 0.024(4S + ,6)mm
-0.000' - ,0
-0.000 - ,0
PANEL THICKNESS:
1/16" (I.Smm) to 3/16" (4.8mm)
WEIGHT:
23 oz. (6S0 gratOs) typ
ORDERING GUIDE
THERMOCOUPLE TYPE"
, AD2071/--/---/---
J
K
T
E
R
S
AD2070
/TI-
I
ENTER~
C
B
JDIN
TDIN
POWER. 0P'l10N"
(I) 120Vac
}
(2) 240V ae
(3) +7.SV de to +28Vde
ENTER - - - - - - '
ANALOG OUTPUT OPTION
(A) Contains Analog Ouput
} ENTER
(BLANK) Does Not Contain Analog Output
SERIAL OUTPUT 0P'l10N"
(SI) Contains RS-232 Serial Output
}
(S2) Contains 20rnA Loop Serial Output
(BLANK) Does Not Contain Serial Output
ENTER - - - -..
Example Order Number: AD2070/J/lIAiSI =AD2070 for J Thermocouple
Type, 120V ae Power, Analog Voltage Output and
RS-232 Serial Output.
*Only one ophon can be ordered. The thermocouple type does not need to
be speCIfied. when ordenng the AD2071 smce It 18 user programmable.
Specifications subject to change without notice.
12-20 DIGITAL PANEL INSTRUMENTS
I
Application Specific Integrated Circuits
Analog Devices offers a full spectrum of capabilities in applicationspecific integrated circuits (ASICs). These chip-level systems
can implement designs with 12-bit accuracy and 16-bit resolution
that formerly required board-level solutions.
an 8-channel multiplexer, programmable-gain amplifier, sampleand-hold, and 12-bit AID converter with internal voltage
reference.
AD75003 DATA ACQUISITION SYSTEM
Analog Devices can incorporate most of the functions of its
standard monolithic parts in full-custom and semicustom ICs.
Full-custom parts optimize performance and space requirements,
while cell-based semicustom parts reduce development time and
engineering expense. Development costs can be cut further
by tailoring a generic predefined system-on-a-chip to your
application.
Analog's experienced design engineers work with powerful
computer-aided design tools to design and layout your circuit.
Design centers are currently in Massachusetts, California and
England.
Multiple locations for fabrication, assembly, and testing ensure
a ready supply of production parts. Products can be processed
in full MIL-38510 certified facilities.
DESIGN EXAMPLES
Analog Devices has created a variety of customer-specific and
function-specific ASIC parts. Described here are two examples,
a custom chip set and a semicustom chip.
AD75004 QUAD DAC
VREFOUT
VII~F1N
Voun
....
•7
Vouu
•3
.2
Your,
V"
-12V
WR
Vss
ANALOG GROUND
AGND I
DIGITAL GROUND
DOND
CH7
CH'
PROGRAMMABLE GAIN
AMPLIFIER AND
SAMPLf: AND HOLD
VIIIFiN
VRfJ'OUT
V"
..
v..
v"
cs
Wii
"GND
DGND
cc
Derivative Circuits
The circuits outlined above can be modified to suit a specific
customer's application. One such device is a serial-interface
DAS. The AD75003 design was altered to have programmable
gains of 1 to 20 instead of 1 to 16, and a serial UART instead of
an 8-bit parallel interface. In addition to the AD75003 functions,
this part contains a precision instrumentation amplifier, a programmable line-frequency notch filter, a 7-bit trim DAC, and
a temperature sensor .
Modem Chip Set
Library cells can be combined to form macro building blocks
for high-speed modems. This two-chip design concept filters
and converts data to interface a digital signal processor with the
analog circuitry of a 9600-baud modem. On one chip, the received
signal passes through an anti-aliasing filter, sample-and-hold,
12-bit AID converter, 8th-order digital filter and decimation.
On the other chip, transmit data is 8 x oversampled, then goes
to an 8th-order filter, a 12-bit DAC and an active reconstruction
filter.
,1,3 A2 A1 AO
HIGH·SPEED MODEM CHIP SET
AD75004 Quad DAC
This circuit contains four separate 12-bit DIA converters with
amplifiers for voltage output and an on-board reference. Doublebuffering latches interface with an 8-bit parallel bus and permit
updating of all four channels individually or simultaneously.
AD75003 Data Acquisition System
This DAS converts analog signals on 8 input channels to 12-bit
values and interfaces via an 8-bit parallel bus. The chip integrates
APPLICATION SPECIFIC ICs 13-1
Transversal Filter Element
This design implements 5 taps of a finite-impulse response
filter. Each tap comprises an 8-bit DAC and a multiplier, which
handle signals up to 4OMHz. A parallel interface sets the tap
weights.
.
TRANSVERSAL FILTER ELEMENT
DIGITAL
INPUTS
AND
ANALOG
Tpe BiMOS II and Linear-Compatible CMOS (LC2MOS) processes combine bipolar and CMOS devices on one chip. Functional
density is an order of magnitude greater than previous mixed-signal
processes; over 20,000 devices can be placed on a single chip.
Bipolar transistors provide low-noise, low-offset input stages and
high-power output stages. The CMOS devices offer high input
impedance, and make dense logic and good switches for data
converters and switched-capacitor filters. LC2MOS also provides
a JFET for very low input noise ..
INPUTS
CONTROL
The bipolar-CMOS processes operate on supply voltages ranging
from single + 5 volts to split ± l5V, with signal levels ranging
from single-ended + 3V to ± I OV. These processes are ideally
suited for applications in data acquisition, instrumentation,
industrial automation and telecommunications.
SIGNALS
The High-Voltage Switch (HVS) process provides quality analog
switches that can operate with supply voltages up to ± 22 volts.
It can combine switches and multiplexers with CMOS logic.
ANALOG
OUTPUTS
HIGH-PERFORMANCE PROCESSES
Analog Devices' semicustom and custom circuits are fabricated
using the same high-performance processes as our standard ICs.
These technologies include two mixed bipolar-CMOS processes,
a high-voltage CMOS process, and high-speed and low-power
bipolar processes. These processes can include thin-film resistors,
which may be laser trimmed for precise matching and stable
performance over a wide temperature range.
The Flash bipolar process makes high-speed linear signal processing, data conversion, and ECL logic functions on one chip.
Signal levels are ± 4 volts with ± 5V supplies or + IOV with a
+ 12V supply. Applications include disk-drive read/write circuitry
and high-speed telecommunications equipment.
The Complementary Bipolar (CB) process features high-speed
PNP and NPN devices for precision, low-power linear applications.
It also offers low-noise buried-Zener references and dual-gate
JFETs. CB runs on + 5V to ± 15V supplies.
The table below summarizes the processes available for designing
ASICs. Other processes in development will offer even higher
speed, denser logic and higher integration of analog and digital
functions.
ANALOG DEVICES HIGH-PERFORMANCE PROCESSES FOR ASICs
Process
Power
Signal
BiMOSII
LC 2 MOS
HVS
Flash
CB
± 12V
:t5V
±3to±10
+2to±18
+ 5 to
+ 5 to
±
± 15
± 22
5 or + 12
± 15
+ 5 to
13-2 APPLICATION SPECIFIC ICs
<
±40r
+ lO
+ 2 to
± 10
Features
Wide Variety of Precision Linear and Digital Functions
Wide Variety of Precision Linear and Digital Functions
High-Voltage Switches, Muxes and Logic Functions
High-Speed Linear and Digital Functions
High-Speed, Low-Power Linear Functions
<
CELL LIBRARIES
Cell libraries for the bipolar-CMOS processes are described
below. These libraries are growing with the development of new
processes, macrocells and cells. Many new catalog parts will also
be available as cells. Your local sales office can give you current
information on the cell libraries and available generic
circuits.
Operational amplifiers are available in bipolar and CMOS configurations. Representative bipolar opamp cells have performance
characteristics similar to an AD OP-27 and a slew-enhanced
AD741. The LC2MOS process offers JFET op amps, including
an AD544 equivalent.
The following figure shows the standard design cycle, which
begins with schematic entry. After logic and initial electrical
simulation, the designer uses the graphics editor to layout the
circuit. Parasitics and other data are extracted from the layout
and circuit operation is simulated again. Finally, the system
checks that the layout follows process design rules and matches
the schematic.
IC DESIGN WITH
COMMERCIAL CAD SYSTEM
Instrumentation amplifiers with performance comparable to the
AD521 and AD524 are available. Comparators suitable for 12-bitaccurate applications are available. Linear comparators have
response times down to 100 nanoseconds and strobed comparators
have setup/access times down to 50 nanoseconds.
Digital-to-analog converters range in resolution from 8 to 14
bits, and include a cell similar to the AD667. Analog-to-digital
converters vary from 8 to 12 bits in resolution, and include cells
equivalent to the AD7572 and AD574. One half-flash ADC cell
converts to 8-bit accuracy in 500 nanoseconds, and one successive
approximation-cell converts to 12 bits in 5 microseconds.
Support cells include sample-and-hold amplifiers with performance
comparable to the AD585, low-voltage bandgap references comparable to the AD584 and low-noise buried-Zener references.
RC active filters and programmable switched-capacitor filters
are available with specifications in these ranges:
In addition to using these commercial CAD tools, Analog Devices
has developed a proprietary compiler for mixed-signal IC design,
called JANUS. By integrating all design functions into one
environment with a common database, JANUS reduces design
time by an order of magnitude.
IC DESIGN WITH JANUS
PROPRIETARY CAD SYSTEM
Topology: all classical filter types
Frequency Range: 200Hz to 20kHz (switched-cap)
Number of Sections: up to 10th-order (switched-cap) or
4th-order (RG)
SignallNoise and THD: >72dB, compatible with
12-bit data acquisition.
Logic cells include gates, counters, registers, PLA, RAM and
ROM. Interface cells include 8- and l6-bit parallel 110 ports
and UARTs.
•
DESIGN AND LAYOUT
Analog Devices engineers are available to design your integrated
circuit, drawing on their years of experience and using powerful
computer-aided design (CAD) tools. These comprehensive CAD
tools help design, simulate and layout the circuit and aid in
generating test programs.
APPLICATION SPECIFIC ICs 13-3
To speed schematic entry, the designer selects devices, cells and
macrocells from comprehensive menus. Device generators allow
the designer to specify devices for maximum performance and
minimum size. Analog, logic and functional simulators verify
the performance of individual cells and the overall chip design.
Placement and routing algorithms complete circuit layouts automatically, yet allow intemction with the designer to handle
special cases. When placing devices, JANUS considers thermal
and electrical matching as well as die area. An expert system
optimizes routing to minimize interconnect length and number
of vias. Post-layout simulation comprehends the parasitics of the
final routing and is more accurate than the initial simulation.
Future goals for JANUS include automatically generating programs for production trim and test of analog/digital ICs.
TEST AND TRIM
Analog Devices has over 20 years of experience in testing complex
circuits and manufactures commercial test systems for precision
linear ICs. In each fabrication facility, a computer network
integrates Analog Devices, Teradyne and L TX test equipment.
The design, wafer probe and test areas share data on the network
for statistical analysis and device modelling.
All Analog Devices ASICs are tested at the wafer level, and
most are laser-wafer trimmed to achieve high accuracy. Untrimmed
thin-mm resistors match within 1% to 0.1%, depending on area.
Trimmed resistors can match to better than 0.01%. Wafers may
be laser-drift trimmed with a hot-chuck probe to minimize the
effects of temperature on accuracy.
After packaging, all parts are tested to assure that they meet
guaranteed specifications. Environmental handlers can verify
parts at multiple tempemtures. Burn-in is performed as specified
by the customer.
PACKAGING
Analog Devices ICs are available in most modern package types,
including high-pin-count and surface-mount-varieties. ASICs
may be assembled in any of Analog Devices' standard packages,
listed below. This list is constantly expanded and other packages
may be used if they are suitable for high-performance
applications.
Available Packages
Pin-grid array (PGA): 68 to 144 pins
Leadless ceramic chip carrier (LCC): 20 to 68 pins
Plastic leaded chip carrier (PLCC): 20 to 44 pins
Plastic dual in-line package (DIP): 14 to 64 pins
Side-brazed DIP: 14 to 64 pins
Frit-seal DIP (C'-erdip): 14 to 28 pins
Small outline (SO): 14 and 16 pins
13-4 APPLICATION SPECIFIC ICs
PROGRAM RESPONSmILITIES AND INTERFACES
The following chart sh\?ws the major phases in developing an
ASIC, and responsibilities during each phase. The overall development time depends on the complexity of the circuit and on
how custom the design is.
Your Analog Devices Sales Engineer is your first interface for
ASIC development. Your local sales office can provide further
inforIr&3.tion on Analog Devices' custmrJsemicustom capabilities.
PROGRAM RESPONSIBILITIES AND INTERFACES
CUSTOMER
JOINT CUSTOMER/AOI
GENERATE DESIGN.
TEST AND
EXECUTE
NONDISCLOSURE
RELIABILITY
SPECIFICATIONS
AND CONTRACT
AGREEMENT
ANALOG OEVICES
Power Supplies
Modular AC/DC Power Supplies
GENERAL DESCRIPTION
Analog Devices offers a broad line of modular ac/dc power
supplies that provide both OEMs and designers a reliable, easy
to use, low-cost solution to their power requirements. Models
are available in PC mountable and chassis mountable designs
with 5 volt to 15 volt (single, dual, triple) outputs and current
ratings from 25mA to 3 amps. Since these modular supplies are
fully encapsulated, no trimming or external component selection
is necessary; simply mount the unit, connect power and output
leads, and you're on the air! Most Analog Devices' power supplies
are available from stock in !-oth large and small quantities with
substantial discounts being applied to large quantity orders.
ACIDC POWER SUPPLY FEATURES
• Current Limit Short Circuit Protection
• PC Mounted and Chassis Mounted Versions
• Single ( + 5V), Dual (± 12V, ± 15V), and Triple
(±15V/+5V, ±15V/+IV to +15V) Output Supplies
• Current Outputs:
25mA to IOOOmA for Dual and Triple Output Supplies
250mA to 3000mA for Single Output Supplies
• Wide Input Voltage Range
• Low Output Ripple and Noise
• Excellent Line & Load Regulation Characteristics
• High Temperature Stability
• Free-Air Convection Cooling; No External Heat Sink Required
GENERAL SPECIFICATIONS
Power Requirements
Input Voltage Range:
I05V ac to 125V ac
Frequency:
50Hz to 250Hz
Electrical Specifications
Temperature Coefficient:
Output Voltage Accuracy:
Breakdown Voltage:
Isolation Resistance:
Short Circuit Protection:
O.02%f'C
±2%,max
See Specification Table
500V rms, min
50MH
All ac/dc power supplies
employ current limiting. They
can withstand substantial
overload including direct
short. Prolonged operation
should be avoided since
excessive temperature rises
will occur.
Environmental Requirements
Operating Temperature
Range:
Storage Temperature
Range:
SPECIFICATIONS- Typical@ + 25"Cand 115Vac60Hzunlessotherwisenoted*
Type
Model
Output
Voltage
Volts
904
902
Line Reg.
max
%
±IS
±SO
0.02
0.02
::t200mV
05
3.5x25xO.875
±15
±Ioo
0.02
0.02
-OmV
+300mV
05
3.5x2 5x 125
902·2
::tIS
±100
0.02
0.02
05
3 5x2 5xO.875
920
::tIS
±2oo
0.02
0.02
+3OOmV
-OmV
+3OOmV
0.5
3 5 x 2.5 x 1.25
925
921
::tIS
::tl2
±350
±240
0.02
0.02
002
0.02
±J%
+300mV
0.5
0.5
3 5x2 5xl.62
3.5 x 2.5 x 1.25
1000
2000
3000
0.02
0.02
005
005
0.05
0.10
:±;J%
±J%
I
I
5 (typ)
3.5 x 2.5 x 1.25
35x2.5x1.62
3.5 x 2.5 x 1.25
±IOO
0.02
005
0.02
0.10
01
01
0.02
0.02
±l%
±l%
±2%
±2%
(-0, +3OOmV)
05
0.5
0.5 (typ)
1.0 (.yp)
05
0.25
0.5
0.25
3.5 x 2.5 x 1.25
125
0.02
0.02
0.02
002
008
008
0.01
0.01
±lOO
±2oo
±350
±500
0.05
005
0.05
0.05
0.05
0.05
0.05
0.05
±2%
±2%
±2%
±20/0
1000
3000
0.05
0.05
0.15
0.10
±2%
±2%
2
5 ('yp)
4.4x2.7xl.44
4.75x2.7x2.00
±150
300
±150
1000
0.02
002
0.02
0.02
0.02
0.10
0.02
0.10
±2%
±2%
±2% .
±2%
o 5 (typ)
4.75x2.7x 1.45
1.0 (.yp)
o 5 ('yp)
1.0 (.yp)
4.75x2 7x 1.45
905
922
928
923
±IS
+5
927
::tIS
2B35J
2B35K
Dual
Output
952
970
973
975
SiqIe
Output
955
976
972
Triple
Output
974
+5
±IS
+ 1 to + 15**
±IS
+ 1 to + 15**
::tIS
::tIS
::tIS
±IS
±15
+5
::tIS
+5
500
±150
1000
=65
125
±65
*Consult Analog Devices Power Supply Catalog for adcilnonal tnformanon
·*Rmstorprogrammable.
Load Reg. Output
max
Voltage
%
Error max
Ripple &
Noise
Output
Current
mA
-Omv
-Omv
-Omv
±2%
(-0, +3OOmV)
mVnnsmax
Dimensions
Inches
3 5 x 2.5 x 1.62
3.5 x 2.5 x I 25
3.5 x 2.5 x 1.25
4.4 x 2.7 x 1.44
4.4x2.7x 1.44
4.4 x 2.7 x 2.00
4.4x2.7x2.00
SpeaficatKms subJect to change Without nouce
POWER SUPPLIES 14-1
•
Modular DC/DC Converters
GENERAL DESCRIPTION
Analog Devices' line of compact dddc converterS offer system
designers a means of supplying a reliable, easy to use, low-cost
solution to a variety of floating (analog and digital) power applications. These devices provide high accuracy, short circuit protected, re-gulated outputs with very low output noise and ripple
characteristics.
Fourteen models are offered in five power levels of 1 watt, 1.8
watts, 4.5 watts, 6 watts and 12 watts. Input voltage versions
include 5 volt, 12 volt, 24 volt and 28 volt with output ranges as
follows: + 5 volt, ± 12 volts and ± 15 volts at ±60mA to l000mA
output current capability.
Most models are high efficiency (typically over 60% at full load)
and feature complete 6-sided continuous shielding for EMIIRFI
protection. A 'IT-type input filter is contained, in some models,
which virtually eliminates the effects of reflected input ripple
current. Most Analog Devices' dc/dc converters are available
from stock in both large and small quantities with substantial
discount~ being applied to large quantity orders.
DClDC POWER SUPPLY FEATURES
• Inaudible (>20kHz) converter switching frequency
• Continuous, Six-Sided EMIIRFI Shielding Except on 1 Watt
and 1.8 Watt Models
• Output Short Circuit Protection (either output to common)
• Automatic Restart After Short Condition Removed
• Automatic Starting with Reverse Current Injected into
Outputs
• Low Output Ripple and Noise
• High Temperature Stability
• Free Air Convection Cooling
No external heat sink or specification derating is
required over the operating temperature range.
GENERAL SPECIFICATI9NS FOR lW AND
1.8W MODELS
Line Regulation-full range: ± 0.3% (± 1% max, 949)
Load Regulation-no load to full load: ±0.4% (±0.5% max,
949)
Output ~-loise and Ripple: 20nlV p-p (with lSfJ.F Ianlaium
capacitor across each output) (2mV rms max, 949)
Breakdown Voltage: 300V dc min (500V dc min, 949)
Input Filter Type: 'IT
Operating Temperature Range: - 25°C to + 71 °C
Storage Temperature Range: -40°C to + 125°C (+ 100°C, 949)
Fusing: If input fusing is desired, we recommend the use of a
slow blow type fuse that is rated at 150%-200% of the
dc/dc converter's full load input current.
GENERAL SPECIFICATIONS FOR 4.5W, 6W,
12W MODELS
Line Regulation-full range: ±0.07% max (±0.02% max, 951,
960 series) (±0.1% max, 943)
Load Regulation-no load to full load: ± 0.07% max (± 0.02%
max, 951, 960 series) (±0.1% max, 943)
Output Noise and Ripple: ImV rms max
Breakdown Voltage: 500V dc min
Input Filter Type: 'IT
Opemting Temperature Range: - 25°C to + 71 °C
Storage Temperature Range: -40°C to + 125°C
Fusing: If input fusing is desired, we recommend the use of a
slow blow type fuse that is rated at 150%-200% of the
dc/dc converter's full load input current.
SPECIFICATIONS - Typical @ + 25°C at nominal input voltage unless otherwise noted*
Model
943
958
941
960
962
964
965
966
967
949
940
953
94S
951
Output
Voltage
Volts
Output
Current
mA
±12
±12
± 15
± 15
± 15
± 15
± 15
± 15
± 15
±15
± 15
±15
1000
100
±150
±40
±33
±33
±190
±190
±190
±60**
±150
±150
±150
±410
Input
Voltage
Volts
5
5
5
5
5
12
5
12
24
5
5
12
28
5
Input'
Voltage
Range
Volts
4.75/5.25
4.5/5.5
4.75/5.25
4.5/5.5
4.5/5.5
10.8/13.2
4.65/5.5
11.2/13.2
22.3/26.4
4.65/5.5
4.75/5.25
1l/13
23/31
4.65/5.5
Input
Current
FuULoad
1.52A
200mA
1.I7A
384mA
396mA
165mA
1.7A
7l0mA
350mA
0.6A
l.35A
0.6A
250mA
3.7A
Output
Temperature
Voltage
Coefficient
f'Cmax
Error max
±l%
±5%
±I%
±5%
±5%
:t5%
±1%
±I%
±1%
±2%
±1%
±0.5%
::to.5%
±0.5%
±0.02%
±O.OI%(typ)
±0.01%
±O.OI%(typ)
±O.OI%(typ)
::t 0.01% (typ)
± 0.005% (typ)
± 0.005% (typ)
± 0.005% (typ)
±0.03%
±0.01%
±0.01%
::to.01%
±0.01%
Efficiency
FuULoad
min
62%
50%
58%
50%
50%
50%
62% (typ)
62% (typ)
62% (typ)
58%
62%
62%
61%
62%
Dimensions
Inches
2.0 x 2.0 x 0.38
1.25 x 0.8 x 0.4
2.0 x 2.0 x 0.38
1.25 x 0.8 x 0.4
1.25 xO.8 xO.4
1.25 xO.8xO.4
2.0 x 2.0 x 0.38
2.0 x 2.0 x 0.38
2.0 x 2.0!, 0.38
2.0 x 1.0 x 0.375
2.0 x 2.0 x 0.38
2.0 x 2.0 x 0.38
2.0 x 2.0 x 0.38
3.5 x 2.5 x 0.88
NOTES
I Models 940 and 941 will deliver up to 120mA output current (and model 943 wdl deliver up to6OOmA)over an mput voltage range of 4 65V de and S.5V de
*Consult Analog Devices Power Supply Catalog for additional information
**Single-ended or unbalanced operanon IS pernusslble such that total output current load does not exceed a total of 120mA
Spccdicanons subJect to change without notice.
14-2 POWER SUPPLIES
LTS-2U2U Component Test Systems
HANDLER INTERFACE FOR
HANDLER CONTROL SIGNALS
UNI-DIRECTIONAL RS-232 PORT
FOR OPTIONAL PRINTER
BI-DIRECTIONAL RS-232 PORT
FOR COMMUNICATING WITH
ANY RS-232 DEVICE
DUAL DISK DRIVES, DOUBLE-SIDED FOR
OPERATING SYSTEM, MASS STORAGE OF DATA,
USER PROGRAMS, AND SUPPLIED PROGRAMS
\
IEEE 488 PORT (OPTIONAL)
~ -"7'=:~rc~'~
PLUG-IN FAMILY
MODULE (E.G.,
LINEAR, DIGITAL, DATA CONVERSION, DISCRETE)
THE LTS CONCEPT
The L TS-2020 is a versatile component test system which tests
a multitude of components to the manufacturer's specifications
(linear, digital, data conversion and discrete devices). The system
offers such features as RS-232 ports for networking, IEEE for
compatibility with handlers and probers, dual disk drives for
mass storage of data, automatic self calibration, and a full statistical
analysis software package.
The L TS-2020 provides several data output formats - datalog,
yield analysis and statistical analysis. The console provides the
primary measurement and control functions to test a specific
class of devices. The socket assembly is the mechanical and
electronic interface for the family board and the DUT board.
The DUT board plugs directly into the socket assembly and
contains the circuitry and socket, specific to the actual device
under test.
Voltage Measurement Range
±IOV
Analog Devices' component test systems are the first benchtop
testers that are programmable in BASIC and fill-in-the-blanks
CREATE. CREATE is menu-driven software which prompts
the user for data sheet limits and conditions, then builds a completed test program for the specified device. Turnkey program
libraries are available for each of the device families.
Far more than just comprehensive production testers, these test
systems can handle complex engineering analysis and incoming
inspection. They are the first systems that can provide all the
capabilities of today's large centralized test systems at a price
that is approximately one-third the cost. The L TS-2020 not
only provides the flexibility of distributed or decentralized testing,
it allows for cost effective multiple system purchases. They
increase overall test reliability, since the threat of a single big
failure is eliminated in a distributed testing environment.
LTS-2020 CONSOLE SPECIFICATIONS
Current Range
Resolution
HIZ
IOfl-V
Accuracy
±(0.0015% + l50fl-V)
Current Measurement Range
lOrnA to + 150rnA
- l50rnA to + lOrnA
- l.OrnA to + l.OrnA
-lOrnA to + lOrnA
Voltage Range
Oto +20V
Oto -20V
Oto + lOY
±IOV
Resolution
2fl-A
2fl-A
0.2fl-A
O.lfl-A
Accuracy
±(2.5% +
± (2.5% +
± (0.5% +
± (0.5% +
Voltage Forcing Range
010 +20V
010 -20V
010 + lOY
-IOVIO + lOY
Current Range
- lOrnA to + l50rnA
- l50rnA to + lOrnA
- l.OrnA to + l.OrnA
- lOrnA to + lOrnA
Resolution
100rnV
100rnV
SOrnV
IrnV
Accuracy
±50rnV
±50rnV
±2SmV
± 500fl-V
Operating Voltage Range
105Vto l25Vac@ 50Hz to 60Hz
2lOV to 250V ac@ 50Hz to 60Hz
Console Dimensions
W19in. x o 26in.(66cm.) xHI2in.(3Icrn.)
WI. 751bs. (39Kgs.)
System Reference Stability
lOY ± 25 ppmllOOOhrs. noncumulative
Operating Temperature Range
010 + 40°C, + 32°F to 104°F
100fl-AN + l5fl-A)
100fl-AiV + l5fl-A)
1Ofl-A)
1Ofl-A)
COMPONENT TEST SYSTEMS 15-1
II
LTS-2020 Test Capabilities
LINEAR DEVICE TEST CAPABILITY
The LTS-2101 Operational Amplifier Family Board tests today's
very demanding high precision op amps, comparators and regulators. This board houses the test loop used in testing op amps
and comparators and the pulse load circuitry used in developing
the high currents needed for voltage regulator testing.
For testing devices under 100J.LV, the L TS-2101 offers a tight
offset spec of ±(O.2S% + SJ.LV). Use oi iow thermal Emf relays
and a test loop gain of 10,045 ensures superior low level Vos
measurement performance for optimum repeatability of low
le~el signals.
Testing of low current devices is achieved with the LTS-0614
Socket Assembly which is designed to test bias and offset currents
with an accuracy of ±(S% + 2SfA) for any FET amplifier,
including quad devices. Program libraries containing prewritten
test programs for many standard op amps, comparators and
regulators are available on disk.
ANALOG-TO-DIGITAL TEST CAPABILITY
The L TS-2200 ADC Family Board provides the test circuitry
required for testing monolithic, hybrid or modular ADCs. An
on-board 16-bit microprocessor with 8K bytes of memory acts
as a slave for the system console and executes preprogrammed
test routines such as linearity, all codes existence, transition
noise measurements and conversion time measurements at high
speed. Absolute accuracy can be measured within 200f.l.V. Linearity, differential nonlinearity, offset, gain and PSSR are tested to
± .05 OUT LSB + 200J.LV. Turnkey test packages are available
for many of the standard ADCs cUrrently in use.
DIGITAL-TO-ANALOG TEST CAPABILITY
The L TS-2302 DAC Family Board utilizes advanced state of the
art test techniques to provide comprehensive test capabilities for
a wide variety of D/A converters. It will test both voltage and
current output DACs, DACs with and without buffer registers
and serial or parallel input DACs to 16-bit accuracy.
High repeatability on low level signals is achieved because of the
grounding scheme on the LTS-2302. The incorporation of high
level components in the VII circuits ensures true accuracy. In
addition, the methodology for measuring low bit currents allows
appropriate testing of this parameter on CMOS DACs.
Output leakage current on the L TS-2302 is measured with the
bit drivers to the DAC set to logic o. Current is measured using
the I to V converter. A Imn resistor within the I to V circuitry
ensures sensitivity, thereby measuring current down to ± 1J.LA
full scale.
15-2 COMPONENT TEST SYSTEMS
DIGITAL DEVICE TEST CAPABILITY
The LTS-2SIO Digital Device Family Board provides 24 pin
driverldetectors and a precision, four quadrant VII source for
testing SSIIMSI TTL and CMOS tligital devices. This board
contains four programmable device supplies and switching circuitry necessary for performing accurate parametric measurements
on all device pins.
Together with the LTS-06SS remote ac test fixture, dynamic
parametric testing of 24-pin SSI/MSI TTL digital devices can
be achieved. Accuracies are achieved down to ± 4% + 1. Sns at
a resolution of SOOps. Dynamic parameters tested are propagation
delay, setup and hold times.
DISCRETE DEVICE TEST CAPABILITY
The L TS-2600 Transistor Family Board tests bipolar transistors,
JFETs, diodes and optocouplers. An on-board 16-bit microprocessor with 4K bytes of memory acts as a slave for the L TS
system and coordinates the timing and pulse width control of
the stimulus and measurement signals. In addition, the microprocessor monitots the interlock circuitry to insure safe handling
of high power test signals.
MOSFET software packages support the testing of Nand P
channel enhancement mode and N channel depletion mode
devices. Tests which may be performed on MOSFET devices
include Idss, Igss, Igssf, Igssr, Id (off), Id (on), B Vdss, B
Vgss, B Vgssf, B Vgssr, Vds (on), Vgs (th), Vgsoff, Vsd, Rds
(on) and Gsf.
ANALOG SWITCH TEST CAPABILITY
The L TS-2700 Analog Switch Family Board adds switch and
multiplexer testing capability to the L TS-2020. This test capability,
with CREATE software allows datalogged device testing at the
incoming inspection and semiconductor manufacturing levels
and includes software power for use in component evaluation
applications.
The L TS-2700 tests on and off drain to source leakage currents
with an accuracy of 2S0pA, while forcing differential voltages
up to SOV (± 2SV from GND). Other tests performed are drain
to source on resistance, greatest change in drain-source on
resistance between channels, digital input current and supply
current.
Twenty high integrity analog lines are provided - 4 to be used
as drain connections and 16 for source connections. Also provided
are 8 programmable digital drivers, 4 digital control bits, 6
variable power supplies and I fixed + SV supply. These combinations of sources provide testing of devices such as 4-channel
switches, 16 to I multiplexers and other combinations of switches
and multiplexers.
Package Information
Contents
ADILETTERDESIGNATOR
DESCRIPTION
PAGE
14 Lead
16 Lead
IS Lead
20 Lead
16 16 16 16 -
14 Lead
16 - 6
14 Lead
16 Lead
16 - 7
16 - S
20 Terminal
2STerminal
16 - 9
16 - 10
2 Lead
16 - 11
3 Lead (TO-52)
3 Lead (TO-5 Style)
S Lead (TO-99)
S Lead (TO-99 Style)
10 Lead (TO-100)
12 Lead (TO-S Style)
16 16 16 16 16 16 -
12
13
14
15
16
17
SLead
14 Lead
16 Lead
IS Lead
20 Lead
16 16 16 16 16 -
IS
19
20
21
22
20 Lead
2SLead
16 - 23
16 - 24
SLead
14 Lead
16 Lead
IS Lead
24 Lead
16 16 16 16 16 -
SLead
16 - 30
3 Lead
16 - 31
10 Lead
16 - 32
Side Brazed DIP (Ceramic)
D-14
D-16
D-lS
D-20.
2
3
4
5
Bottom Brazed DIP (Ceramic)
DH-14A
Metal Platform DIP
DH-14B
DH-16B
Leadless Chip Carrier (Ceramic)
E-20A
E-2SA
Flat Pack (Ceramic)
F-2A
Metal Can
H-03A
H-03B
H-OSA
H-OSB
H-lOA
H-12A
Plastic DIP
N-S
N-14
N-16
N-lS
N-20
Plastic Leaded Chip Carrier (PLCC)
P-20A
P-2SA
Cerdip
Q-S
Q-14
Q-16
Q-lS
Q-24
25
26
27
2S
29
Small Outline (SOIC)
R-S
Plastic
TO-92
Single In-Line Package (SIP)
Y-I0
PACKAGE INFORMA TION 16-1
III
Package Outlin.e Dimensions
D-14
14-Lead Side Brazed Ceramic DIP
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
MIN
INCHES
MAX
MILLIMETERS
MIN
MAX
0.200
0.023
0.070
0.015
0.785
0.310
0.320
0.110
0.200
5.08
0.58
1.78
0.38
19.94
7.87
8.13
2.79
5.08
0.014
0.030
0.008
Q
0.220
0.290
0.090
0.125
0.150
0.015
S
S,
0.005
0.060
0.098
16-2 PACKAGE INFORMATION
0.36
0.76
0.20
5.59
7.37
2.29
3.18
3.81
0.38
0.13
1.52
2.49
NOTES
6
2,6
6
4
4
7
3
5
5
NOTES
1. Index area; a notch or a lead one identification mark
Is IocIIted adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(O.58mm) for a" four comer leeds only.
3. Dimension Q sha" ba measured from the seating plane
to tha base plane.
4. This dimension allows for off-center lid, meniscus
and glass overrun.
5. Applies to a" four corners.
6. A" leeds - Increa.. maximum limit by 0.003" (0.08mm)
measured at the center of the flat, when hot solder
dip lead finish Is applied.
7. Twelve spaces.
D-16
16-Lead Side Brazed Ceramic DIP
f~
PlANE+~-tr
Jl +
A
.
SEATING
Q
L
.L-
b../j.-
SYMBOL
A
b
b,
c
MIN
INCHES
MAX
MILUMETERS
MIN
MAX
0.200
0.023
0.070
0.015
0.840
0.310
0.320
0.110
0.200
5.08
0.58
1.78
0.38
21.34
7.87
8.13
2.79
5.08
0.014
0.030
0.008
D
E
E,
e
L
L,
-I e
Q
0.220
0.290
0.090
0.125
0.150
0.015
S
S,
0.005
0.060
0.080
0.36
0.76
0.20
5.59
7.37
2.29
3.18
3.81
0.38
0.13
1.52
2.03
L,
\.-
NOTES
6
2,6
6
4
4
7
3
5
5
b,
NOTES
1. Index area; a notch or a lead one Identification mark
Is located adjacent to lead one.
2. The minimum limit for dimension b, may ba 0.023"
(O.58mm) for all four corner leads only.
3. Dimension Q shall be maasurad from the seating plane
to tha base plane.
4. This dimension allows for off-center lid. meniscus
and glass overrun.
5. Applies to all four corners.
6. All leads - increasa maximum limit by 0.003" (O.08mm)
measured at the center of the flat, when hot solder
dip lead finish is applied.
7. Fourteen spaces.
II
PACKAGE INFORMATION 16-3
0-18
I8-Lead Side Brazed Ceramic DIP
-!
~S,
C"7
-r
---'
NOTE~
C"7
18
1
n
n
.., ..,
r
I
!--E,--!
SYMBOL
A
b
b,
c
MIN
INCHES
MAX
MILLIMETERS
MIN
MAX
0.200
0.023
0.070
0.015
0.960
0.310
0.320
0.110
0.200
5.08
0.58
1.78
0.38
24.38
7.87
8.13
2.79
5.08
0.014
0.030
0.008
0
E
E,
e
L
L,
Q
0.220
0.290
0.090
0.125
0.150
0.015
S
S,
0.005
1~
0.060
0.098
PACKAGE INFORMA TION
0.36
0.76
0.20
5.59
7.37
2.29
3.18
3.81
0.38
0.13
1.52
2.49
NOTES
6
2.6
6
4
4
7
3
5
5
NOTES
1. Index erea; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.58mml for all four corner leads only.
3. Dimension Q shall be measurad from the seating plane
to the base plane.
4. This dimension allows for off-center lid. meniscus
and glass overrun.
5. Applies to all four corners.
'6. All leads - increase maximum limit by 0.003" (O.08mm)
measured at the center of the flat. when hot solder
dip lead finish is applied.
7. Sixteen spaces.
D·20
20-Lead Side Brazed Ceramic DIP
SEE
NOTE 1
""
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
MIN
10
INCHES
MAX
MILLIMETERS
MIN
MAX
0.200
0.023
0.070
0.015
1.060
0.310
0.320
0.110
0.200
5.08
0.58
1.78
0.38
26.92
7.87
8.13
2.79
5.08
0.014
0.030
0.008
Q
0.220
0.290
0.090
0.125
0.150
0.015
S
S,
0.005
0.060
0.080
0.36
0.76
0.20
5.59
7.37
2.29
3.18
3.81
0.38
0.13
1.52
2.03
NOTES
6
2,6
6
4
4
7
3
5
5
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.58mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off-center lid, meniscus
and glass overrun.
5. Applies to all four corners.
6. All leads - increase maximum limit by 0.003" (0.08mm)
measured at the center of the flat, when hot solder
dip lead finish is applied.
7. Eighteen spaces.
III
PACKAGE INFORMA TlON 16-5
DH-14A
14-Lead Bottom Brazed Ceramic DIP
II "
• II
'
NM~\ ~I
f~
SEATING
PlANE
--t--H
+
~I
D
I I I I I I
A
I I I
II
Q
I I I I I...L,..
~s'7j~~ ~b' L~ ~
e
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
S
S,
INCHES
MAX
MILLIMETERS
MAX
MIN
0.220
0.014
0.023
0.030
0.070
0.008
0.015
0.805
0.480
0.505
0.290
0.320
0.100BSC
0.125
0.200
0.180
0.015
0.060
0.098
0.005
5.59
0.36
0.58
1.78
0.76
0.20
0.38
20.45
12.83
12.19
7.37
8.13
2.54BSC
5.08
3.18
4.57
1.52
0.38
2.49
0.13
MIN
16-6 PACKAGE INFORMATION
I
11- - - - J- I- T +
I"T
NOTES
2
6
4,7
3
5
5
S
c
I-- E,--I
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.58mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. The basic pin spacing is 0.100" (2.54mm) between
centerlines.
5. Applies to all four corners.
6. E, shall be measured at the centerline of the leads.
7. Twelve spaces.
DH·14B
14·Lead Metal Platform DIP
14
SEE
NOTE 1
[
:1
I-
SEATING
PLANE
nr
Q
-
t
*
SYMBOL
A
+b
D
E
E,
e
L
L,
Q
*
INCHES
MAX
MILLIMETERS
MIN
MAX
0.225
0.014
0.023
0.885
0.490
0.520
0.295
0.305
0.100BSC
0.140
0.200
0.160
0.015
0.075
5.72
0.58
MIN
-h
L,
L
0.36
NOTES
2
22.48
12.45
13.21
7.49
7.75
2.54BSC
5.08
3.56
4.57
0.38
1.91
6
4,7
3
NOTES
1. Index area; a square corner or a lead one identification
mark is located edjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
10.58mml for all four corner leads only.
3. Dimension Q shall ba measured from the seating plane
to the base plane.
4. The basic pin spacing is 0.100" 12.54mml between
centerlines.
5. Applies to all four corners.
6. E, shall be measured at the centerline of the leads.
7. Twelve spaces.
•
PACKAGE INFORMATION 16-7
· DH-16B
16-Lead Metal Platform DIP
SEE
rr
16
9
~
l
.
~r======D======::::'·1
ITr - ,-h
NOTE\{,
lJ
Q
SEATING _
•
E
PLANE~
L
L,
t
SYMBOL
A
b
D
E
E,
e
L,
*
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.175
0.016
0.960
0.490
0.295
0.095
0.160
4.45
0.41
24.4
12.45
7.49
2.41
4.06
0.215
0.020
0.985
0.520
0.305
0.105
0.255
16-8 PACKAGE INFORMA TION
b
5.46
0.51
25.0
13.21
7.75
2.67
6.48
NOTES
4
5
NOTES
1. Index area; a square corner or a lead one identification
mark is located adjacent to lead one.
2. Pin 6 is electrically connected to the case.
3. Case has metal bottom surface.
4. E, shall be measured at the centerline of the leads.
5. Fourteen spaces.
E-20A
20-Terminal Leadless Ceramic Chip Carrier
-..NO.1 PIN INDEX
BOTTOM VIEW
(hx45°)
3PLACES
L
TT
~D
I
ITp...1
r
450)
IX
•
IIHHHHHTfJ
SYMBOL
A
B,
D
D,
e
j
h
L
MIN
INCHES
MAX
0.064
0.100
0.022
0.028
0.342
0.358
0.075 REF
0.050BSC
0.020 REF
0.040 REF
0.045
0.055
MILLIMETERS
MIN
MAX
1.63
2.54
0.56
0.71
8.69
9.09
1.91 REF
1.27BSC
0.51
1.02
1.14
1.40
NOTES
1
NOTES
.
1. Dimension A controls the overall package thickness.
2. Applies to all 4 sides.
3. All terminals are gold plated.
2
•
PACKAGE INFORMATION 16-9
E-28A
28-Terminal Leadless Ceramic Chip Carrier
t-*- B,
L
"NO.1 PIN INDEX
e
r
IhX45o,L
3 PLACES
BOTTOM VIEW
...1.
I
I
'f
P
D
Ii x 45°'
I rH HHHHHHTI1
SYMBOL
A
B,
D
D,
e
j
h
L
1~10
INCHES
MAX
MILUMETERS
MIN
MAX
0.064
0.100
0.022
0.028
0.442
0.458
0.075 REF
0.050BSC
0.020 REF
0.040 REF
0.045
0.055
1.63
2.54
0.56
0.71
11.23
11.63
1.91 REF
1.27BSC
0.51
1.02
1.14
1.40
MIN
PACKAGE INFORMATION
NOTES
1
2
NOTES
1. Dimension A controls the overall package thickness.
2. Applies to all 4 sides.
3. All terminals are gold plated.
F·2A
2·Lead Flat Pack (Ceramic)
POSITIVE LEAD
INDICATOR
+ ~~---------------'T
-;£51
~]l
/'
~~
L,
c
t:::=:1.
SYMBOL
A
b
c
0
0,
E
e
L,
MIN
INCHES
MAX
0.041
0.015
0.0045
0.081
0.045
0.500
0.050
0.019
0.0065
0.250
0.220
0.093
0.055
+
t
MILLIMETERS
MIN
MAX
1.04
0.38
0.12
2.06
1.14
12.69
1.27
0.48
0.17
6.35
5.59
2.36
1.40
I·
0,
0
~
vh2:zzzzzzzz»H
NOTES
NOTE
1. This dimension allows for off-center lid. meniscus and
solder overrun.
1
1
II
PACKAGE INFORMATION 16-11
H-03A
3-Lead Metal Can (TO-52)
SYMBOL
A
cl>b
cI>~
cl>D
cl>D,
e
e,
F
j
k
L
L,
Lz
ot
MIN
INCHES
MAX
0.115
0.150
0.021
0.016
0.019
0.209
0.230
0.178
0.195
0.100T.P.
0.050T.P.
0.030
0.036
0.046
0.028
0.048
0.500
0.050
0.250
45°T.P.
16-12 PACKAGE INFORMATION
MILLIMETERS
MIN
MAX
3.81
0.53
0.41
0.48
5.31
5.84
4.52
4.95
2.54T.P.
1.27T.P.
0.76
0.91
1.17
0.71
1.22
12.70
1.27
6.35
NOTES
2.92
1,4
1,4
2
2
3
1
1
NOTES
1. (Three Leads) cl>bz applies between L, and Lz. cl>b applies
between Lz and 0.5" (12.70mm) from seating plane.
Diameter is uncontrolled in L, and beyond 0.5"
112.70mm) from seating plane.
2. Leads having maximum diameter 0.019" (O.48mm)
measured in gauging plane 0.054" (1.4mm) + 0.001"
(0.03mm) - 0.000" (O.OOmm) below the seating plane
of the device are within 0.007" (0.18mm) of their true
positions relative to a maximum-width tab.
3. Measured from maximum diameter of the actual
device.
4. All leads - increase maximum limit by 0.003" (0.08mm)
when hot solder dip finish is applied.
8-03B
3-Lead Metal Can CTO-5 Style)
\
b
SYMBOL
A
b
~
D
D,
e
e,
h
j
k
L
L,
L2
P
Q
r
a
MIN
INCHES
MAX
MILLIMETERS
MIN
MAX
0.165
0.185
0.016
0.021
0.016
0.019
0.335
0.370
0.305
0.335
0.200T.P.
0.100T.P.
0.015
0.035
0.028
0.034
0.029
0.045
0.500
0.050
0.250
0.100
4.19
4.70
0.41
0.53
0.41
0.48
8.51
9.40
7.75
8.51
5.0BT.P.
2.54T.P.
0.38
0.89
0.71
0.86
0.74
1.14
12.70
1.27
6.35
2.54
0.007
45°T.P.
0.18
NOTES
2,7
2,7
4
3
2
2
2
1
5
NOTES
1. This zone is controlled for automatic handling. The
variation in actual diameter within the zone shall not
exceed 0.010" (0.25mm).
2. (Three leads) b2 applies between L, and L2. b applies
between L2 and 0.500" (12.70mm) from seating plane.
Diameter is uncontrolled in L, and beyond 0.500"
(12.70mm) from seating plane.
3. Measured from maximum diameter of the actual
device.
4. Leads having maximum diameter 0.019" (O.48mm)
measured in gauging plane 0.54" (1.37mm) + 0.001"
(0.03mm) - 0.000" (O.OOmm) below the seating plane
of the device are within 0.007" (0.18mm) of their true
positions relative to the maximum-width tab.
5. ~etails of outline in this zone optional.
6. Lead #3 connected to case.
7. All leads - increase maximum limit by 0.003" (0.08mm)
when hot solder dip finish is applied.
•
PACKAGE INFORMATION 16-13
H-08A
8-Lead Metal Can (TO-99)
~ REFERENCE PLANE
L
_
lr
L--I
,A1:
In' "
+0
~z.
I
II
llL~ II: \;
-'...It
=::J<
¢:::!
F
Q
SYMBOL
A
+b
+b,
+0
+0,
+02
e
e,
F
k
k,
L
L,
Lz
Q
Cl
MIN
INCHES
MAX
0.165
0.185
0.019
0.01'
0.021
0.01'
0.335
0.370
0.305
0.335
0.110
0.160
O.200BSC
0.100BSC
0.040
0.027
0.034
0.027
0.045
0.500
0.750
0.050
0.250
0.010
0.045
45°BSC
t6-14 PACKAGE INFORMATION
r
+b
+b,
SEATING PLANE
MILUMETERS
MIN
MAX
4.19
4.70
0.41
0.41
0.41
0.53
9.40 .
8.51
7.75
8.51
2.79
4.06
5.08BSC
2.54BSC
1.02
0.69
0.86
0.69
1.14
12.70
19.05
1.27
6.35
1.14
0.25
45°BSC
NOTES
1,4
1,4
3
3
3
NOTES
1. (All leads) +b applies between L, and Lz. +b, applies
between Lz and 0.500" (12.70mm) from the reference
plane. Oiamater is uncontrolled in L, and beyond 0.500"
(12.70mm) from the reference plane.
2. Measured from the maximum diameter of the
product.
3. Leads having a maximum diamater 0.019" (O.48mm)
measued in gauging plane 0.054" (1.37mm) + 0.001"
(O.03mm) - 0,000" (O.OOmm) below the base plane of
the product are within 0.007" (0.1Bmm) of their true
position relative to the maximum width tab.
4. All leads - increase maximum limit 0.003" (O.OBmm)
when hot solder dip finish Is applied.
H-08B
8-Lead Metal Can (TO-99 Style)
.,-----7--1'
-;€r:'lR:NCEPLANE
In'
~~:,
IJ
",0
',:\
I
llL~ ~c'
F~
Q
SYMBOL
A
",b
",b,
",0
",0,
",02
e
e,
F
k
k,
L
L,
L2
..
Q
r
",b
",b,
SEATING PLANE
INCHES
MAX
MILLIMETERS
MIN
MAX
0,165
0,185
0.016
0.019
0.016
0.021
-0.370
0.335
0.305
0.335
0.110
0.160
O.230BSC
0.115BSC
0.040
0.027
0.034
0.027
0.045
0.500
0.750
0.050
0.250
0.010
0.045
45°BSC
4,19
4,70
0.41
0.48
0,41
0.53
8.51
9.40
7.75
8.51
2.79
4.06
5.84BSC
2.92BSC
1.02
0.69
0.86
0.69
1.14
12.70
19.05
1.27
6.35
0.25
1.14
45°BSC
MIN
\
NOTES
1.4
1.4
3
3
NO"T:ES
1. (All leads) ",b applies between L, and L2. ",b, applies
between L2 and 0.500" (12.70mm) from the reference
plane. Diameter is uncontrolled in L, and beyond 0.500"
(12.70mm) from the reference plane.
2. Measured from the maximum diameter of the
product.
3. Leads having a maximum diameter 0.019" (O.48mm)
measued in gauging plane 0.054" (1.37mm) + 0.001"
(0.03mm) - 0.000" (O.OOmm) below the base plane of
the product are within 0.007" (0.18mm) of their true
position relative to the maximum width tab.
4. All leads - increase maximum limit 0.003" (0.08mm)
when hot solder dip finish is applied.
2
1
1
1
3
II
PACKAGE INFORMATION 16-15
H-lOA
IO-Lead Metal Can (TO-IOO)
c-
REFERENCE PLANE
I-A~L,--j
~rL2l
I
rr
~I
jll -I-Ji: I'\~
F
cf>b
Q
SYMBOL
A
cf>b
cf>b,
cf>D
cf>D,
cf>D2
e
e,
F
k
k,
L
L,
L2
Q
Of
t
SEATING PLANE
INCHES
MAX
MILLIMETERS
MIN
MAX
0.165
0.185
0.016
0.019
0.016
0.021
0.335
0.370
0.305
0.335
0.110
0.160
0.230BSC
0.115BSC
0.040
0.027
0.034
0.045
0.027
0.500
0.750
0.050
0.250
0.010
0.045
36°BSC
4.19
4.70
0.41
0.48
0.41
0.53
8.51
9.40
7.75
8.51
2.79
4.06
5.84BSC
2.92BSC
1.02
0.69
0.86
0.69
1.14
12.70
19.05
1.27
6.35
0.25
1.14
36°BSC
MIN
16-16 PACKAGE INFORMATION
cf>b,
NOTES
1.4
1.4
3
3
2
1
1
1
3
NOTES
1. (Three Leads) b2 applies between L, and L2. cf>b applies
between L2 and 0.5" (12.70mm) from seating plane.
Diameter is uncontrolled in L, and beyond 0.5"
(12.70mm) from seating plane.
2. Leads having maximum diameter 0.019" (O.48mm)
measured in gauging plane 0.054" (1.4mm) + 0.001"
(0.03mm) - 0.000" (O.OOmm) below the seating plane
of the device are within 0.007" (0.18mm) of their true
positions relative to a maximum-width tab.
3. Measured from maximum diameter of the actual
device.
4. All leads - increase maximum limit by 0.003" (0.08mm)
when hot solder dip finish is applied.
H·12A
12·Lead Metal Can (TO.S Style)
SYMBOL
A
",b
",b,
",0
",0,
e
e,
...
F
k
k,
L
L,
Q
MIN
INCHES
MAX
0.148
0.181
0.016
0.019
0.016
0.021
0.592
0.610
0.545
0.555
O.400BSC
0.200BSC
0.100BSC
0.040
0.026
0.036
0.026
0.036
0.375
0.050
0.010
0.045
MILLIMETI'RS
MIN
MAX
3.76
0.41
0.41
15.04
13.84
4.60
0.48
0.53
15.44
14.10
NOTES
1
1
3
3
3
0.66
0.66
9.50
0.25
1.02
0.91
0.91
1.27
1.14
NOTES
1. (All leads) ",b applies between Land L,. ",b, applies
between L, and 0.375" (9.50mm) from the reference
plane. Diameter is uncontrolled in L, and beyone! 0.375"
(9.50mm) from the reference plane.
2. Measured from the maximum diameter of the
product.
3. Leads having a maximum diameter 0.019" (O.48mm)
measued in gauging plane 0.054" (1.37mm) + 0.001"
(0.03mm) - 0.000" (O.OOmm) below the base plane of
the product is within 0.007" (0.18mm) of their true
position relative to the maximum width tab.
2
1
1
III
PACKAGE INFORMATION 16-17
N-8
8-Lead Plastic DIP
b
SYMBOL
A
A2
b
b,
c
0
E
E,
e
L
L,
Q
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.210
0.115
0.195
0.014
0.022
0.045
0.070
0.008
0.015
0.348
0.430
0.300
0.325
0.240
0.280
0.100BSC
0.125
0.200
0.150
0.015
0.060
5.33
2.93
4.95
0.356
0.558
1.15
1.77
0.204
0.381
8.84
10.92
7.62
8.25
7.11
6.10
2.54BSC
3.18
5.05
3.81
1.52
0.38
16-18 PACKAGE INFORMATION
e
b,
NOTES
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. This dimension does not include mold flash or
protrusions.
2
2
N-14
14-Lead Plastic DIP
~
SEE
NOTE 1
~
I
E,
'-r'-r--r-r,-.,-..--r-r....-r,-.,-7r-J
~D~
--.l
T~Q
~
t'
SEATING
•
PLANE--.-
-
-
-
-
-
-
~~ -ol. ~ ~ ~
SYMBOL
A
A2
b
b,
c
0
E
E,
e
L
L,
Q
INCHES
MIN
MAX
MILLIMETERS
MAX
MIN
0.210
0.115
0.195
0.014
0.022
0.045
0.070
0.008
0.015
0.725
0.795
0.300
0.325
0.240
0.280
0.100BSC
0.125
0.200
0.150
0.015
0.060
5.33
4.95
2.93
0.558
0.356
1.77
1.15
0.381
0.204
18.42
20.19
8.25
7.62
7.11
6.10
2.54BSC
5.05
3.18
3.81
1.52
0.38
NOTES
b,
'*
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. This dimension does not include mold flash or
protrusions.
2
2
111
PACKAGE INFORMATION 16-19
N-16
16-Lead Plastic DIP
{l.l\/\/\I\!\{\/\
C
16
9
"( 1
8
SEE
NOTE 1
It
11
~D~
T~Q
A
SEATING
PLANE+-
-
-
-
-
L
..l..-
-.II+- b
SYMBOL
A
Az
b
b,
c
0
E
E,
e
L
L,
a
..j
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.210
0.115
0.195
0.014
0.022
0.045
0.070
0.008
0.015
0.745
0.840
0.300
0.325
0.240
0.280
0.100BSC
0.125
0.200
0.150
0.015
0.060
5.33
2.93
4.95
0.356
0.558
1.15
1.77
0.204
0.381
18.93
21.33
7.62
8.25
6.10
7.11
2.54BSC
3:18
5.05
3.81
0.38
1.52
16-20 PACKAGE INFORMATION
e
-
I-
-
~
NOTES
U ! +f
-
L,
b,
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. This dimension does not include mold flash or
protrusions.
2
2
N-18
IS-Lead Plastic DIP
SYMBOL
A
A2
b
b,
c
0
E
E,
e
L
L,
Q
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.210
0.115
0.195
0.014
0.022
0.045
0.070
0.008
0.015
0.845
0.925
0.325
0.300
0.240
0.280
0.100BSC
0.125
0.200
0.150
0.015
0.060
5.33
2.93
4.95
0.356
0.558
1.15
1.77
0.204
0.381
23.49
21.47
8.25
7.62
7.11
6.10
2.54BSC
5.05
3.18
3.81
1.52
0.38
NOTES
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. This dimension does not include mold flash or
protrusions.
2
2
•
PACKAGE INFORMATION 16-21
N-20
20·Lead Plastic DIP
/\/\/\/\/\/\l\/\/\/\
SEE
NOTE 1
~ 20
"r
11
11
"
1
10
I~
~V V V V VDV V V V V~
PlA'E~
u~
t~O
A
SEATING
L
...L.-
SYMBOL
A
A2
b
b,
c
0
E
E,
e
L
L,
a
+I j.. b
~
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.210
0.115
0.195
0.014
0.022
0.045
0.070
0.008
0.015
0.925
1.060
0.300
0.325
0.240
0.280
0.100BSC
0.125
0.200
0.150
0.015
0.060
5.33
2.93
4.95
0.558
0.356
1.15
1.77
0.204
0.381
23.50
26.90
7.62
8.25
6.10
7.11
2.54BSC
3.18
5.05
3.81
0.38
1.52
16-22 PACKAGE INFORMA TION
e
j.-
NOTES
:'
L,
b,
*
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. This dimension does not include mold flash or
protrusions.
2
2
P-20A
20-Lead Plastic Leaded Chip Carrier (PLCC)
PIN 1
IDENTIFIER
19W
II
111~
TOP
VIEW
,~
,,~
U
B
l'
I3dUl
~:~
SYMBOL
A
B
C
D
E
F
G
H
J
K
R
U
V
W
X
Y
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.385
0.395
0.385
0.395
0.165
0.180
0.025
0.040
0.085
0.110
0.013
0.021
0.050BSC
0.026
0.032
0.015
0.025
0.290
0.330
0.350
0.356
0.350
0.356
0.042
0.048
0.042
0.048
0.042
0.056
0.020
9.78
10.02
9.78
10.02
4.19
4.57
0.64
1.01
2.16
2.79
0.33
0.53
1.27BSC
0.66
0.81
0.38
0.63
7.37
8.38
8.89
9.04
8.89
9.04
1.21
1.07
1.07
1.21
1.07
1.42
0.50
NOTES
•
PACKAGE INFORMATION 16-23
P-28A
28-Lead Plastic Leaded Chip Carrier (pLCC)
LJVrooooooo
W-Y4
P
5
0
26
PIN 1
IDENTIFIER
TOP
VIEW
I.
U B
~I-
R
A
SYMBOL
A
B
C
0
E
F
G
H
J
K
R
U
V
W
X
Y
16-24 PACKAGE INFORMATION
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.025
0.040
0.085
0.110
0.013
0.021
0.050BSC
0.026
0.032
0.015
0.025
·0.390
0.430
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
0.020
12.32
12.57
12.32
12.57
4.19
4.57
0.64
1.01
2.16
2.79
0.33
0.53
1.27BSC
0.66
0.81
0.38
0.63
10.92
9.91
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
0.50
NOTES
Q-8
8-Lead Cerdip
SYMBOL
A
b
b1
c
D
E
E1
e
L
L1
Q
S
S1
CIt
MIN
INCHES
MAX
MIWMETERS
MIN
MAX
0.200
0.023
0.070
0.015
0.405
0.310
0.320
0.110
0.200
5.08
0.58
1.78
0.38
10.29
7.87
8.13
2.79
5.08
0.014
0.030
0.008
0.220
0.290
0.090
0.125
0.150
0.015
0.005
0"
0.060
0.055
15°
0.36
0.76
0.20
5.59
7.37
2.29
3.18
3.81
0.38
0.13
0"
1.52
1.35
NOTES
7
2.7
7
4
4
6
8
3
5
5
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b1 may be 0.023"
(0.58mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off-center lid. meniscus
and glass overrun.
5. Applies to all four corners.
6. Lead center when CIt is 0°. E1 shall be measured at the
centerline of the leads.
7. All leads - increase maximum limit by 0.003"(0.OSmm)
measured at the center of the flat. when hot solder
dip lead finish is applied.
S. Six spaces.
15°
•
PACKAGE INFORMATION 16-25
Q-14
14-Lead Cerdip
NOTE 7
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
S
S,
III
MIN
INCHES
MAX
MILUMETERS
MIN
MAX
0.200
0.023
0.070
0.015
0.785
0.310
0.320
0.110
0.200
5.08
0.58
1.78
0.38
19.94
7.87
8.13
2.79
5.08
0.014
0.030
0.008
0.220
0.290
0.090
0.125
0.150
0.015
0.005
0"
0.060
0.098
15°
0.36
0.76
0.20
5.59
7.37
2.29
3.18
3.81
0.38
0.13
0"
16-26 PACKAGE INFORMATION
1.52
2.49
15°
NOTES
7
2,7
7
4
4
6
8
3
5
5
NOTES
1. Index area; a notch or a lead one identHication mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.58mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off-center lid, meniscus
and glass overrun.
5. Applies to all four corners.
6. Lead center when III is 0". E, shall be measured at the
centerline of the leads.
7. All leads - increase maximum limit by 0.003" (0.08mm)
measured at the center of the flat, when hot solder
dip lead finish is applied.
8. Twelve spaces.
Q-16
16-Lead Cerdip
11+ s,
-.j
r-
~~:I- : : : : : : :1
D
s
~I
s=~~-ht-1
~~ ~ JLb' ~.
L
'
E,
.-+-
..j •
SEE
NOTE 7
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
MIN
INCHES
MAX
MILLIMETERS
MIN
MAX
0.200
0.023
0.070
0.015
0.840
0.310
0.320
0.110
0.200
5.08
0.58
1.78
0.38
21.34
7.87
8.13
2.79
5.08
0.014
0.030
0.008
0.220
0.290
0.090
0.125
0.150
0.015
0.060
0.36
0.76
0.20
5.59
7.37
2.29
3.18
3.81
0.38
O.oao
S
S,
0.005
at
0"
1.52
2.03
0.13
15°
0"
NO,..,S
7
2.7
7
4
4
6
8
3
5
5
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(D.58mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off-center lid. meniscus
and glass overrun.
5. Applies to all four corners.
6. Lead center when at is D·. E, shall be measured at the
centerline of the leads.
7. All leads - increase maximum limit by D.OO3"(D.D8mm)
measured at the center of the flat. when hot solder
dip lead finish is applied.
8. Fourteen spaces.
15°
•
PACKAGE INFORMATION 16--27
Q-18
IS-Lead Cerdip
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
S
S,
II
MIN
INCHES
MAX
MILLIMETERS
MIN
MAX
0.200
0.023
0.070
0.015
0.960
0.310
0.320
0.110
0.200
5.08
0.58
1.78
0.38
24.38
7.87
8.13
2.79
5.08
0.014
0.030
0.008
0.220
0.290
0.090
0.125
0.150
0.015
0.005
0°
0.060
0.098
0.36
0.76
0.20
5.59
7.37
2.29
3.18
3.81
0.38
1.52
2.49
0.13
15°
0-
16-28 PACKAGE INFORMATION
15°
NOTES
7
2.7
7
4
4
6
8
3
5
5
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.58mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off-center lid. meniscus
and glass overrun.
5. Applies to all four corners.
6. Lead center when II is 0°. E, shall be measured at the
centerline of the leads.
7. All leads - increase maximum limit by 0.003"(0.08mm}
measured at the center of the flat. when hot solder
dip lead finish is applied.
8. Sixteen spaces.
Q-24
24-Lead Cerdip
-II--S,
r
-I
N~~: :::::::::::1
~
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
S
S,
III
MIN
-1.
INCHES
MAX
MILLIMETERS
MAX
MIN
0.200
0.023
0.070
0.015
1.280
0.310
0.320
0.110
0.200
5.08
0.58
1.78
0.38
32.51
7.87
8.13
2.79
5.08
0.014
0.030
0.008
0.220
0.290
0.090
0.125
0.150
0.015
0.005
0"
0.060
0.098
15°
~
D
Ib-l~
0.36
0.76
0.20
5.59
7.37
2.29
3.18
3.81
0.38
0.13
0°
1.52
2.49
~
NOTES
7
2.7
7
4
4
6
8
3
5
5
s
JL..
~.
E, •..\\0SEE
NOTE 7
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.58mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off·center lid. meniscus
and glass overrun.
5. Applies to all four corners.
6. Lead center when a is 0°. E, shall be measured at the
centerline of the leads.
7. All leads - increase maximum limit by 0.003"(0.OSmm)
measured at the center of the flat, when hot solder
dip lead finish is applied.
S. Twenty·two spaces.
15°
•
PACKAGE INFORMA TlON 16-29
R·8
8·Lead Small Outline (SOle)
SYMBOL
A
B
C
0
F
G
J
K
L
P
16-30 PACKAGE INFORMA TlON
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.188
0.198
0.150
0.158
0.089
0.107
0.014
0.022
0.018
0.034
0.050BSC
0.007
0.015
0.005
0.011
0.195
0.205
0.224
0.248
4.77
5.03
3.81
4.01
2.26
2.72
0.36
0.56
0.46
0.86
1.27BSC
0.18
0.38
0.125
0.275
4.95
5.21
5.69
6.29
NOTES
TO·92
3·Lead Plastic
SYMBOL
A
c
<\>D
e
e,
E
J
L
L,
S
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.170
0.016
0.175
0.095
0.045
0.125
0.175
0.500
4.58
0.407
4.96
2.42
1.15
3.94
4.96
12.70
0.080
0.210
0.019
0.205
0.105
0.055
0.165
0.205
0.050
0.105
2.42
NOTES
5.33
0.482
5.20
2.66
1.39
4.19
5.20
1.27
2.66
PACKAGE INFORMATION 16-31
Y-lO
IO-Lead Single In-Line Package (SIP)
~ 14~---S--~·1,
r
-
G,
E
SEATING
PLANE
l,
1
10
-./e/--
b-./j.-
SYMBOL
INCHES
MIN
MAX
A
A,
0.123
0.038
b
b,
0.016
0.040
0.009
c
0
E
E,
1.566
0.990
0.150
3.12
3.81
0.042
0.020
0.070
0.97
0.41
1.02
1.07
0.51
1.78
0.012
0.23
0.31
1.586
1.050
39.78
25.15
L,
0.750 REF
0.810REF
0.100BSC
0.150
0.350
Q
0.060
E2
e
S
S,
MILLIMETERS
MIN
MAX
0.080
0.780 REF
0.115REF
16-32 PACKAGE INFORMA TION
40.28
26.67
19.05 REF
20.57 REF
2.54BSC
3.81
8.89
1.52
2.03
19.51 REF
2.92 REF
NOTES
.. k.
L,
!
NOTE
1. Metal tab is electrically insulated from circuitry.
Appendix
Contents
Page
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . .
17 - 2
Product Families Still Available . . . . . . . . . . . . . . . .
17 - 4
Substitution Guide for Product Families No Longer Available
17 - 5
Technical Publications
17 - 6
Worldwide Service Directory
17 - 8
III
APPENDIX 17-1
Ordering Guide
INTRODUCTION
This Ordering Guide should make it easy to order Analog Devices products, whether you're buying one IC op amp, a
multi-option subsystem, or 1000 each of IS different items. It will help you:
I. Find the correct part number for the options you want.
2. Get a price quotation and place an order with us.
3. Know our warranty for components and subsystems.
For answers to further questions, call the nearest sales office (listed at the back of the book) or our main office in Norwood,
Mass. U.S.A. (617-329-4700).
MODEL NUMBERING
Many of the data sheets in the Databook for products having a number of standard options contain an Ordering Guide.
Use it to specify the correct part number for the exact combination of options you want. I.C. and hybrid part numbers are
created using one of these two systems:
Figure I shows the form of model number used for our proprietary standard monolithic ICs and many of our hybrids. It
consists of an "AD" (Analog Devices) prefix, a 3-to-5-digit model number*, an alphabetic performance/temperature-range
designator and a package designator. One or two additional letters may immediately follow the digits ("A" for second-generation
redesigned ICs, "DI" for dielectrically isolated CMOS switches, e.g., AD536AJH, AD7512DIKD).
Figure 2 shows the somewhat different numbering scheme used by our Computer Labs Division for some hybrid circuits.
The number starts with a three-character alphabetic prefix, followed by a hyphen, a three- or four-digit number, and
alphabetic designators (as applicable) to indicate additional functional designations or options and packaging options.
[NANN]
AD XXXX A Y Z
I
ANALOG
DEVICES
PREFIX
J--
Il
THREE-rO-FIVE
DIGIT NUMBERS
I
I
1 OR 2 LEnERS
PROVIDE ADDITIONAL
GENERAL INFORMATION
A SECOND GENERATION
01. OJELECTRICAlL Y
ISOLATED
Z OPERATION ON ± 12V SUPPLIES
PERFORMANCE·
TEMPERATURE RANGE
DESIGNATOR'
f
J
o TO
+70"C
K
PACKAGE OPTIONS
-
I
M
j'~-'~
PARAMETRIC-
PERFORMANCE
L
{ t
+ 85°C
:
INCREASING
PERFORMANCE
C BEST OVERALL
PERFORMANCE
-55"C TO+125°C
HERMETICALLY SEALED DIP,
lEADLESS CHIP CARRIER
CERAMICFLATPACK
METAL CAN. HERMETICALLY
SEALED
METAL-CAN DIP, HERMETICALLY
SEALED-COMPUTER LABS
PLASTIC OIP
PLASTIC LEADLESS CHIP
CARRIER
CERDIP
SMALL OUTLINE
MONOLOTHIC CHIP '
CERAMIC OR METAL
M BEST OVERALL
PERFORMANCE
- 25°C OR - 40ac TO
o
E
F
H
{~ t
INCREASING
PERFORMANCE
U BEST OVERALL
PERFORMANCE
N
P
Q
R
CHIPS
EXAMPLES.
AD521 KCHIPS
AD7524AD
AD536ASH/883B
AD7512DIKD
'MONOLITHIC CMOS CHIPS IN THE AD75XX
SERIES WERE FORMERLY DESIGNATED
AD75XX/COM/CHIPS AND AD75XX/MILICHIPS
AND MAY APPEAR ON PRICE LISTS WITH
THOSE DESIGNAnONS CONSULT ANALOG
DEVICES FOR CURRENT PRICING OF AD75XX
CHIPS
Figure 1. Model-Number Designations for Standard
Analog Devices Monolithic and Hybrid Ie Products.
S, T and U Grades have the Added Suffix, /8838 for
Devices that Qualify to the Latest Revision of MIL-STD883, Level 8.
*For some models, the combination [digit][letter][two or three digits] is used instead of ADXXXX, e.g., 2S80.
17-2 APPENDIX
xxx -
YYZZ W M B
1
MILITARY OPTIONS
1883. SCREENED TO
MIL·STD 883, PER
METHOD 5008
B. SCREENED
TO MIL·STD 883
CLASS B
-
HERMETICALLY
SEALED
METAL-CASE DIP
ADDITIONAL FUNCTIONAL
DESIGNATION OR OPTION
eg, E. C, A, ETC
EXAMPLES
PACKAGE OPTION
M OR H
L=
H A S- 12 02 M
HVBRID~l
AID
CONVERTER
HERMETIC
METAL CASE
2 2,...5
12-81T
L
HVBRID;1jHWD
S- 10 15 E. HDS-1015 E
CONVERTER
1•. BITS
15ns TO 0 10;.,
(VOLT AGE)
Eel
HERMETIC
METAL
D/A
CASE
HDS-1015EMB
L
100% SCREENED
TO MIL-STD 883
CLASSB
Figure 2. Computer Labs Video Hybrid Product Designations
SECOND SOURCE
In addition to our many proprietary products, we also manufacture devices that are fit-, form-, and function-compatible
(and often superior in performance and reliability) to popular products that originated elsewhere. For such products, we
usually add the prefix "AD" to the familiar model number (example: ADDAC85C-CBI-V).
ORDERING FROM ANALOG DEVICES
When placing an order, please provide specific information regarding model type, number, option designations, quantity,
ship-to and bill-to address. Prices quoted are list; they do not include applicable taxes, customs, or shipping charges. All
shipments are F.O.B. factory. Please specify if air shipment is required.
Place your orders with our local sales office or representative, or direcdy with our customer service group located in the
Norwood facility. Orders and requests for quotations may be telephoned, sent via TWX or TELEX, or mailed. Orders
will be acknowledged when received; billing and delivery information is included.
Payments for new accounts, where open-account credit has not yet been established, will be C.O.D. or prepaid. On all
orders under fifty dollars ($50.00), a five-dollar ($5.00) processing charge is required.
When prepaid, orders should include $2.50 additional for packaging and postage (and a 5% sales tax on the price of the
goods if you are ordering for delivery to a destination in Massachusetts).
WARRANTY AND REPAIR CHARGE POLICIES
All Analog Devices, Inc., products are warranted against defects in workmanship and materials under normal use and
service for one year from the date of their shipment by Analog Devices, Inc., except that components obtained from others
are warranted only to the extent of the original manufacturers' warranties, if any, except for component test systems, which
have a I80-day warranty, and J.1MAC and MACSYM systems, which have a 90-day warranty. This warranty does not
extend to any products which have been subjected to misuse, neglect, accident, or improper installation or application, or
which have been repaired or altered by others. Analog Devices' sole liability and the Purchaser's sole remedy under this
warranty is limited to repairing or replacing defective products. (The repair or replacement of defective products does not
extend the warranty period. This warranty does not apply to components which are normally consumed in operation or
which have a normal life inherendy shorter than one year.) Analog Devices, Inc., shall not be liable for consequential
damages under any circumstances.
THE FOREGOING WARRANTY AND REMEDY ARE IN LIEU OF ALL OTHER REMEDIES AND ALL OTHER
WARRANTIES, WRITTEN OR ORAL, STATUTORY, EXPRESS, OR IMPLIED, INCLUDING ANY WARRANTY
OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
APPENDIX 17-3
•
Product Families Not Included in the Oatabook
(But Still Available)
The information published in this Databook is intended to assist the user in choosing components for the design of new
equipment, using the most cost-effective products available from Analog Devices. The popular product types listed below
may have been designed into your circuits in the past, but they are no longer likely to be the most, economic choice for
your new designs. Nevertheless, we recognize that it is often a wise choice to refrain from redesigning proven equipment,
and we are continuing to make these products available for use in existing designs or in designs for which they are uniquely
suitable. Data sheets on these products are available upon request.
Model
ADIOI
ADl08/208/308
AD I 08A/208A/308A
ADl1ll21l1311
AD293
AD294
AD351
AD370/371
AD503
AD506
ADS 10
AD5l5
AD518
ADS28
AD530
AD531
AD533
AD535
AD545
AD567
AD611
AD651
AD801
AD2004
AD2006
AD2008
AD2009
AD2016
AD2020
AD2022
AD2023
AD2033
AD2036
AD2037
AD2038
AD2040
AD3554
AD3860
AD6012
AD7110
AD7118
AD7520
AD7521
17-4 APPENDIX
Model
AD7522
AD7523
AD7525
AD7530
AD7531
AD7541
AD7546
AD7550
AD7552
AD7571
AD7574
AD ADC-816
ADC-8S
ADC-IOZ
ADC-12QZ
ADC-14I1I 71
ADCllOO
ADCll02
ADCll05
ADCllll
ADCI133
ADC1I43
ADC-QM
AD DAC-08
ADG201
ADSHC-85
AP11620/1718
BDM 1615/16
BDM 1617
CAV-0920
CAV-I21O
DAC-M
DAC-QS
DAC-QZ
DAC-IOZ
' DACI009
DAClI06
DAClI08
DACI132
DAC1I46
DACI420
DACI422
DACI423
Model
Model
Model
DASI128
DASI150
DAS1I51
DAS1l55
DASI156
DRC I 765/66
DSC I 705/06
DTMI716/17
HAS-0802
HAS-1002
HDD-1409
HDH-0802
HDH-1003
HDH-1205
HDL-3806
HDS-0810E
HDS-0820
HDS-1015E
HDS-1025
HDS-1240E
HDS-1250
IPAI751
IRDCI730
IRDCI731
IRDCI732
IRDCI733
MATV-0811
MATV-0816
MATV-0820
MCI1794
MDA-IOZ
MOD-I005
MOD-I020
OSCI754
RDCI721
RTM Series
SACI763
SBCDI752/53
SBCD 1756/57
SCDXI623
SCMI677
SDCI604
SDCI700/RDCI700
SDCI702/RDC 1702
SDC I 704/RDCI 704
SDCI71l1RDCI711
SDCI721
SDCI725/RDC1725
SDCI726/RDCI726
SDCI768/RDCI768
SHA-IA
SHA-2A
SHA-4
SHA-5
SHA-1l14
SHA-I134
SHA-1144
SSCTI621
STM Series
TSL1612
2B24
2B34
2B52
2B53
2B56
2B57A-I
2B58A
2B59A
2S20
40
43
44
45
46
48
SO
51
52
118
141
165
171
183
230
232
233
234
235
260
261
272
273
275
276
277
285
288
310
311
424
426
428
429
432
433
434
435
436
440
442
450
452
454
456
458
460
606
610
752
756
903
906
915
926
944
946
947
959
968
Substitution Guide for Product Families
No Longer Available
The products listed in the left-hand column are no longer available from Analog Devices. In many cases, comparable functions
and performance may be obtained with newer models, but - as a rule - they are not directly interchangeable. The closest
recommended Analog Devices equivalent, physically and electrically, is listed in the right-hand column. If no equivalent is
listed, or for further information, contact your local sales office.
Model
Closest
Recommended
Equivalent
Model
Closest
Recommended
Equivalent
AD501
ADS02
AD505
AD508
ADS 11
ADSI2
AD513
AD514
AD516
AD520
AD523
AD546
AD555
ADS 59
AD612
AD614
AD810-813
AD814-816
AD818
AD820-822
AD830-833
AD835-839
ADI408
ADI508
AD2003
AD2024
AD2025
AD2027
AD2028
AD5010/6020
AD7115
AD7513
AD7516
AD7519
AD7527
AD7544
AD7555
AD7560
AD7570
AD7583
ADC 11 03
ADC 11 09
ADCI121
ADDACIOO
ADG200
ADM501
ADP501
ADSHM-S
CAV-I020
DAC-100F
DAC-I0H
DACI112
AD7I1
AD7I1
AD509
AD517
AD711
AD7I1
AD7I1
AD7I1
AD7I1
ADS24
ADS49
AD7I1
AD7519
None
AD524
AD524
None
None
None
None
None
None
None
None
AD2021
None
None
None
None
AD9000
None
None
AD7510DI
None
None
None
None
None
None
None
None
None
AD7550
None
None
ADMSOIl506
ADP511
HTC-0300
MOD-1020
None
DAC-IOZ
DAC12QS
DAC1II8
DACl122
DACI125
HDL-3805
HTC-0500
IDC1703
MAH-0801
MAH-1001
MAS-0801
MAS-1001
MAS-1202
MDA-LB
MDA-LD
MDA-UB
MDA-UD
MDA-8H
MDA-10H
MDA-11MF
MDH-0870
MDH-1001
MDH-1202
MDMS-0801
MDMS-1001
MDMS-1101
MDS-0815
MDS-0815E
MDS-0830
MDS-0850
MDS-1020
MDS-1020E
MDS-1040
MDS-1080
MDS-1240
MDSL-0802
MDSL-0825
MDSL-1002
MDSL-1035
MDSL-1201
MDSL-1250
RTI-1200
RTI-1201
RTI-1202
SERDEX
SHA-3
SHA-6
THC-0300
THC-07S0
THC-1500
THS-002S
THS-0060
THS-022S
TSDC1608-1611
None
AD7541
AD7533
HDL-3806
HTC-0300
IRDC1730/1731
HAS-0802
HAS-lOO2
HAS-0802
HAS-1002
HAS-1202
None
None
None
None
MDA-IOZ
MDA-IOZ
AD7521
None
None
None
AD9768
HDM-1210
HDM-1210
None
None
HDS-0820
HDS-0820
None
None
HDS-1025
HDS-1025
None
HDS-0820
None
HDS-1025
None
HDS-1250
None
R TI -711 Series
RTI-711 Series
RTI-711
JLMAC-SOOO
None
SHAII44
HTC-0300
None
None
HTC-0300
HTC-0300
None
TSLI612
Model
2N3954
2N5900
41
47
101 (Module)
102
106
107
108
110
III
114
115
120
142
143
146
149
153
161
163
170
180
220
231
274J
279
280
282J
283J
301 (Module)
302
350
427
602JIO
602J100
602K100
603
605
901
907
908
909
931
932
933
935
942
948
956
971
Closest
Recommended
Equivalent
None
None
AD515
48
45
48
118
118
52
48
AD308
119
43
50
48
52
AD382
50
AD517
165
165
17l
ADOP-07
234
233
284J
2&6J
281
292A
292A
52
310 (Module)
None
424
AD524
ADS24
AD524
AD524
AD524
904
921
921
921
None
None
None
None
None
947
None
921
APPENDIX 17-5
Technical Publications
TECHNICAL PUBLICATIONS
Analog Devices provides a wide array of FREE technical publications. These include Data Sheets for all products, Catalogs,
Application Notes and Guides and four serial publications:
Analog Productlog, a digest of new-product information;
DSPatch™, a newsletter about digital signal-prqcessing (applications); Analog Briefings, current information about products
for military/avionics and the status of reliability at AD!; 2...'1d
Analog Dialogue, our technical mag~zine, with in-depth discussions
of products, technologies and applications.
In addition to the free publications, three technical Handbooks,
and Synchro & Resolver Conversion, are available at reasonable
cost. System and subsystem products are supported with hardware,
software and user documentation, at prices related to content.
Brief descriptions of typical publications appear below. For
copies of any items, to subscribe to any of our free serials or to
request any other publications, please get in touch with Analog
Devices or the nearest sales office.
CATALOGS
DATA ACQUISITION PRODUCTS DATABOOKS. Contain
selection guides, data sheets and other useful information about
all Analog Devices ICs, hybrids, modules and subsystem components recommended for new designs. The 1988 series consists
of:
DATA CONVERSION PRODUCTS DATABOOK - 1988.
Data Sheets and Selection Guides on D/A, AID, V/F, and FN
Converters, Sample-Track/Hold Amplifiers, Voltage References,
Multiplexers & Switches, Synchro-Resolver Converters, DataAcquisition Subsystems, Application-Specific ICs~ (Available
FREE with the Linear Products Databook as a 2-volume set.)
DSP PRODUCTS DATABOOK -1987. Data Sheets, Selection
Guides and Application Notes on DSP Microprocessors, Microcoded Support Components, Floating-Point Components and
Fixed-Point Components. Available FREE.
LINEAR PRODUCTS DATABOOK - 1988. Data Sheets and
Selection Guides on Op Amps, Instrumentation Amplifiers,
Isolators, RMS-to-DC Converters, Muitipliers/Dividers, Logi
Antilog Amplifiers, RMS-to-DC Converters, Comparators,
Temperature-Measuring Components and Transducers, Special
Function Components, Digital Panel Instruments, Signal-Conditioning Components and Subsystems. (Available FREE with the
Conversion Products Databook as a 2-volume set.)
1987 MILITARY PRODUCTS DATABOOK. 704 pages of
information and data on products processed in accordance with
MIL-STD-883C Class B.
APPLICATION NOTES AND GUIDES
Application Notes. All are available individually upon request.
AID Converters:
"AD670 8-Bit AID Converter Applications."
"Exploring the AD667 12-Bit Analog Output Port."
"Interfacing the AD7572 to High-Speed DSP Processors."
"The AD7574 Analog-to-Microprocessor Interface."
Analog DSPatch is a trademark of Analog Devices, Inc.
17-6 APPENDIX
Amplifiers:
"An IC Amplifier User's Guide to Decoupling, Grounding,
and Making Things Go Right for a Change."
"Applications of High-Performance BiFET Op Amps."
"A User's Guide to IC Instrumentation Amplifiers"
"How to Select Operational Amplifiers."
"How to Test Basic Operational Amplifier Parameters."
"Lc1y1,7-Ccst, Two-Chip Voltage-Controlled Amplifier and
Video Switch."
"Using the AD9610 Transimpedance Amplifier."
D/A Converters:
"AD7528 Dual8-Bit CMOS DAC."
"Analog Panning Circuits Provide Almost Constant Output
Power."
"CMOS DACs and Operational Amplifiers Combine to Build
Programmable-Gain Amplifiers." In two parts.
"CMOS DACs in the Voltage Switching Mode Can Work
from a Single Supply."
"CMOS D/A Converter Circuits for Single + 5-Volt
Supplies."
"14-Bit DACs (AD7534/AD7535) Maintain High Performance
Over Extended Temperature Range."
"Gain Error and Tempco of CMOS Multiplying DACs."
"Interfacing the AD7549 Dual 12-Bit DAC to the MCS-48
and MCS-51 Microcomputer Families."
"Methods for Generating Complex Wavefortns and Vectors
Using Multiplying D/A Converters."
"Simple Interface Between D/A Converter and Microcomputer Leads to Programmable Sine-Wave Oscillator."
"The AD7224 DAC Provides Programmable Voltages Over
Varying Ranges."
Digital Signal Processing (Note: Eight additional DSP
Application Notes will be found in the DSP
Products Databook):
"A Guide to Designing Microcoded Circuits."
"Implement a Writeable Control Store in Your
Word-Slice™ System."
"Variable-Width Bit Reversing with the ADSP-1410
Address Generator."
Resolver-to-Digital Conversion:
"Dynamic Characteristics of Tracking Converters."
"Dynamic Resolution-Switching on the IS74 Resolver-toDigital Converter."
"Resolver-to-Digital Conversion - A Simple and CostEffective Alternative to Optical Shaft Encoders."
"Why the Velocity Output of the IS74 and IS64 Series RID
Converters is Continuous and Step-Free Down to
Zero Speed."
Sample-Holds:
"Applying IC Sample-Hold Amplifiers."
"Generate 4 Channels of Analog Output Using AD7542
12-Bit D/A Converters and Control It All with Only
Two Wires."
Switches:
"ADG201N202A and ADG2211222 Performance with
Reduced Power Supplies."
VIF Converters:
"Operation and Applications of the AD654 IC V-to-F
Converter. "
"Analog-to-Digital Conversion Using Voltage-to-Frequency
Converters (AD65 I)."
Application Guides. All are available upon request.
Analog CMOS Switches and Multiplexers. A 16-page short-form
guide to high-speed CMOS switches, CMOS switches with
dielectric isolation, and CMOS multiplexers. Also included are
reliability data and infor~ation on single-supply operation.
Applications Guide for Isolation Amplifiers and Signal Conditioners.
A 20-page guide to specifications and applications of galvanically
isolated amplifiers and signal conditioners for industrial, instrumentation, and medical applications.
CMOS DAC Application Guide 2nd Edition by Phil Burton
(1986 - 63 pages). Introduction to CMOS DACs, Inside CMOS
DACs, Basic Application Circuits in Current-Steering Mode,
Single-Supply Operation Using Voltage-Switching Mode, The
Logic Interface, Applications.
ESD Prevention Manual - Protecting ICs from electrostatic
discharges. Thirty pages of information that will assist the reader
in implementing an appropriate and effective program to assure
protection against electrostatic discharge (ESD) failures.
High-Speed Data Conversion - A 24-page short-form guide to
video and other high-speed AID and DIA converters and
accessories, in forms ranging from monolithic ICs to card-level
products.
RMS-to-DC Conversion Application Guide 2nd Edition by
C. Kitchin and L. Counts (1986- 61 pages). RMS-DC Conversion:
Theory, Basic Design Considerations; RMS Application Circuits;
Testing Critical Parameters; Input Buffer Amplifier Requirements;
Programs for Computing Errors, Ripple, and Settling Time.
Surface Mount IC - A 28-page guide to ICs in SO and PLCC
packages. Products include op amps, rms-to-dc converters,
DACs, ADCs, VFCs, sample-holds, and CMOS switches.
BOOKS - Can be purchased from Analog Devices, Inc.; send
check for indicated amount to One Technology Way, P.O. Box
796, Norwood, MA 02062. If more than one book is ordered,
deduct a discount of $1 from the price of each book.
ANALOG-DIGITAL CONVERSION HANDBOOK: Third
Edition, by the Engineering Staff of Analog Devices, edited by
Daniel H. Sheingold. Englewood Cliffs, NJ: Prentice-Hall (1986).
A comprehensive guide to AID and DIA converters and their
applications. This third edition of our classic is in hardcover
and has more than 700 pages, an Index, a Bibliography, and
much new material, including: video-speed, synchro-resolver,
VIF, high-resolution, and logarithmic converters, ICs for
DSP, and a "Guide for the Troubled." Seven of its 22 chapters
are totally new.
$32.95
NONLINEAR CIRCUITS HANDBOOK: Designing with
Analog Function Modules and ICs, by the Engineering Staff of
Analog Devices, edited by Daniel H. Sheingold. Norwood MA:
Analog Devices, Inc. (1974). A 540-page guide to multiplying
and dividing, squaring and rooting, rms-to-dc conversion, and
multifunction devices. Principles, circuitry, performance,
specifications, testing, and application of these devices 325 illustrations.
$5.95
SYNCHRO& RESOLVER CONVERSION, edited by Geoff
Boyes. Norwood MA: Analog Devices, Inc. (1980). Principles
and practice of interfacing synchros, resolvers, and Inductosyns*
to digital and analog circuitry.
$11.50
TRANSDUCER INTERFACING HANDBOOK: A Guide to
Analog Signal Conditioning, edited by Daniel H. Sheingold.
Norwood MA: Analog Devices, Inc. (1980). A book for the
electronic engineer who must interface transducers for temperature, pressure, force, level, or flow to electronics, these 260
pages tell how transducers work - as circuit elements - and how
to connect them to electronic circuits for effective processing of
their signals.
$14.50
ADSP-ZIOO SUPPORT PUBLICATIONS - for the ADSP-2100
single-chip digital signal processor, available at no charge for
single copies.
ADSP-2100 USER'S MANUAL - Introduction, Architecture,
System Interface, Instruction Set, Appendix - 180 pages.
ADSP-2100 CROSS-SOFTWARE MANUAL - Development
System, System Builder, Assembler, Linker, Simulator, PROM
Splitter, Appendix - 102 pages.
ADSP-2100 APPLICATIONS HANDBOOK - Introduction,
Fixed Point Arithmetic, Floating-Point Arithmetic, FixedCoefficient Digital Filters, FFTs, Adaptive Filters, Image Processing, Linear Predictive Speech Coding, High-Speed MODEM
Algorithms, Bibliography - 178 pages.
III
*Inductosyn is a registered trademark of Farrand Industries, Inc.
APPENDIX 17-7
Worldwide Service Directory
North America
Alabama
(205) 536-1506
Alaska
*(206) 251-9550
*/71 A\ l!A1 n~n ..
\1."" U""-o::J">" I
Arizona
(602) 949-0048
*(303) 590-9952
Idaho
(303) 443-5337
*(303) 590-9952
*(206) 251-9550
Minnesota
(612) 835-2414
North Carolina
(919) 373-0380
Mississippi
(205) 536-1506
North Dakota
(612) 835-2414
Illinois
(312) 520-0710
Missouri
(314) 521-2044
Ohio
(216) 248-4995
*(614) 764-8795
Indiana
(317) 244-7867
Washington
*(206) 251-9550
Nebraska
(913) 829-2800
Oregon
*(206) 251-9550
West Virginia
*(614) 764-8795
Kentucky
(615) 459-0743
*(617) 329-4700
Nevada
(505) 828-1300
*(408) 559-2037
*(714) 641-9391
Pennsylvania
*(215) 643-7790
*(614) 764-8795
Wisconsin
(414) 784-7736
Louisiana
*(214) 231-5094
New Hampshire
*(617) 329-4700
Maine
*(617) 329-4700
New Jersey
(516) 673-1900
*(617) 329-4700
*(215) 643-7790
California
*(714) 641-9391
*(408) 559-2037
*(619) 268-4621
Kansas
(913) 829-2800
Delaware
*(215) 643-7790
Maryland
*(301) -992-1994
Florida
(305) 855-0843
(305) 724-6795
(813) 963-1076
Massachusetts
*(617) 329-4700
Michigan
(313) 559-9700
Georgia
(404) 449-7662
Hawaii
*(714) 641-9391
*Analog Devices, Inc. Direct Sales Offices
17-8 APPENDIX
Virginia
*(301) 992-1994
Oklahoma
*(214) 231-5094
Iowa
(319) 373-0200
Connecticut
(516) 673-1900
*(617) 329-4700
Vermont
*(617) 329-4700
Montana
(801) 466-9336
*(714) 641-9391
Arkansas
*(214) 231-5094
Colorado
(303) 443-5337
*(719) 590-9952
Utah
(801) 466-9336
*(303) 590-9952
New Mexico
(505) 828-1300
*(303) 590-9952
New York
(516) 673-1900
(716) 425-4101
Rhode Island
*(617) 329-4700
South Carolina
(919) 373-0380
South Dakota
(612) 835-2414
Tennessee
(205) 536-1506
(615) 459-0743
Texas
*(214) 231-5094
Wyoming
(801) 466-9336
Puerto Rico
*(617) 329-4700
Canada
(416) 821-7800
(613) 729-0023
(514) 697-0804
(604) 941-7707
Mexico
*(617) 329-4700
International
Australia
(03)5750222
(02)8888777
(619)2422000
India
(212)53880
(11 )611823
(812)560506
Austria
*(222)885504
Ireland
*(932)232222
(United Kingdom)
Belgium
*(3)2371672
Brazil
(11)531-9355
Denmark
*(2)845800
Finland
(0)8041041
France
*(1)46873411
*(76)222190
*(61 )408562
*(99)535200
*(83)515200
Mexico
(83)351721
(83)351661
Switzerland
*(22)315760
(18)200102
New Zealand
(9)592629
Taiwan
(2)5018231
Norway
(3)847099
United Kingdom
*(932)232222
*(01 )9411066
*(635)35335
*(506)30306
*(021)5011166
*(0279)418611
Israel
*(052)911415
*(052)914461
People's Republic
of China - Beijing
(1)890721, Ext. 120
Italy
*(2)6883831
*(6)8393405
*(11 )6504572
(2)9520551
(51)555614
(49)633600
(6)390083
(11)599224
(55)894105
Romania
*(222)885504
(Austria)
Holland
*(1620)81500
Japan
*(3)2636826
*(6)3721814
Hong Kong
(5)8339013
Korea
(82)7841144
Singapore
(65)2848537
South Africa
(11 )882-1300
Spain
(1)7543001
(3)3007712
Sweden
*(8)282740
United States of
America
*(617) 329-4700
West Germany
*(89)570050
*(4181)8051
*(721)616075
*(30)316441
*(221 )686006
Yugoslavia
*(222)885504
(Austria)
Malaysia
*(617)329-4700
*Analog Devices, Inc. Direct Sales Offices
WORLDWIDE HEADQUARTERS
One Technology Way, P.O. Box 9106, Norwood, Massachusetts 02062-9106 U.S.A.
Tel: (617) 329-4700, TWX: (710) 394-6577; FAX: (617) 326-8703, Telex: 924491
Cable: ANALOG NORWOODMASS
APPENDIX 17-9
17-10 APPENDIX
Product Index
Alpha-Numeric by Model Number
Page·
Model
AC2626 . . . . . . .
ADIOI . . . . . . . .
ADI08/208/308 . . . .
AD 108A/208A/308A
AD1I1/2111311 .
AD202/204 .
eAD210 .
AD293
AD294
AD295
eAD345
AD346 ..
AD351
AD362 ..
AD363 ..
AD364 ..
AD365
AD367 .
eAD368 ..
AD369 ..
AD370/371 .
eAD374 ..
AD376 ..
AD380 ..
AD381 ..
AD382 .
AD389 ..
AD390 ..
eAD392 ..
AD394 .
AD395 .
eAD396 .
ADS03 .
AD506 .
ADS07 .
AD509 .
ADSIO .
ADS15 .
eADS15A
AD517 .
ADS18 .
AD521 .
ADS22 . . .
ADS24 .
eAD526 .
ADS28 .
AD530 .
AD531
AD532 .
ADS33 .
ADS34.
ADS35 ..
AD536A
ADS37 . .
·
·
·
·
· L 10-5
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
· . . . . L 5-7
· . . . . L 5-19
C 14-4, L 17-4
C 14-4, L 17-4
.. L 5-27
· . . . . L 9-5
. . . . .. C 6-5
C 14-4, L 17-4
C 9-5
C 9-5
C 9-5
L 4-7
· C 9-17
· C 3-13
· C 3-13
C 14-4, L 17-4
· C 3-23
· C 3-31
· L 2-15
· L 2-21
· L 2-21
· C 6-11
· C 2-11
· C 2-19
· C 2-25
· C 2-25
· C 2-33
C 14-4, L 17-4
C 14-4, L 17-4
· . . . . L 2-27
· . . . . L 2-31
C 14-4, L 17-4
C 14-4, L 17-4
· . . . . L 2-35
· . . . . L 2-41
C 14-4, L 17-4
· L 4-15
· L 4-21
· L 4-25
· L 4-37
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
· . . . . L 6-7
. C 14-4, L 17-4
. . . . . . L 6-13
. C 14-4, L 17-4
L 8-5
. . . . . . C 4-5
Model
ADS38
ADS39 .
ADS42 .
AD544 ..
ADS45
AD547
AD548
eAD549
eADS57
AD558
AD561
AD562
AD563
AD565A
AD566A
ADS67 .
eADS68 .
AD569 . . . .
ADS70 ..
ADS71
AD572 . . . .
AD573 .
ADS74A
ADS75 .
AD578 .
ADS79 .
ADS80 .
ADS81
AD582 ..
ADS83 .
AD584 . . .
AD585 ..
eAD586 .. .
eAD587 .. .
ADS88 .
AD589 ..
ADS90 ..
AD592 ..
ADS94 ..
AD595
AD596
AD597
AD611
AD624 .
AD625 .
AD630 .
AD632 .
AD636 .
AD637 .
AD639 .
AD642 ..
AD644 ..
AD647 ..
AD648 ..
Page·
·
·
· .
· ....
C 14-4,
·
·
·
·
·
·
·
·
· .
· .
C 14-4,
· ....
· ....
· ....
· .
· ....
· ....
· ..
· .
·
·
·
·
·
· ..
. ......
. ......
·
·
·
·
L 6-23
L 6-31
L 2-47
L 2-47
L 17-4
L 2-47
L 2-55
L 2-63
C 2-41
C 2-45
C 2-53
C 2-57
C 2-57
C 2-61
C 2-61
L 17-4
C 2-69
C 2-81
C 3-39
C 3-39
C 3-45
C 3-53
C 3-61
C 3-73
C 3-81
C 3-87
C 8-5
C 8-9
C 6-17
C 6-21
C 8-15
C 6-23
C 8-23
C 8-31
C 8-39
C 8-51
· L 10-7
L 10-17
· L 11-5
· L 11-5
L 11-13
L 11-13
. C 14-4, L 17-4
· ..
· ..
· ..
· ..
· ....
·
· ....
· ....
· .
· .
· .
L 4-49
L 4-61
L 9-9
L 6-39
L 8-ll
L 8-17
L 9-17
L 2-75
L 2-81
L 2-87
L 2-93
*C ~ Data Conversum Products Databook, D ~ DSP Products Databook, L ~ L.near Products Databook.
eNew product since publication of 1986 Data Acquu.twn Databook Updaw and Sekctwn GuuJe.
PRODUCT INDEX 18-1
II
Model
AD650
AD651
eAD652
AD654
eAD664
AD667
eAD668
AD670
AD673
eAD674A
eAD678
eAD679
eAD681
eAD683
eAD689
AD693
eAD707
eAD708
AD711
AD712
eAD713
eAD736
eAD737
AD741 Series
eAD744
eAD746
eAD767
eAD770
eAD790
AD801
eAD821
eAD834
eAD840
eAD841
eAD842
eAD845
eAD846
eAD847
eAD848
eAD849
eAD890
eAD891
eADl139
eADl145
ADl147
ADl148
ADl170
eAD1l75K
eAD1332
eAD1376
eAD1380
ADl4031l403A .
AD2004
AD2006 ....
Page*
· C 4-13
C 14-4, L 17-4
· C 4-25
· C 4-41
· C 2-93
C 2-105
C 2-113
· C 3-93
C 3-105
C 3-113
C 3-123
C 3-135
· C 6-29
· C 6-29
· C 8-55
L 11-19
L 2-103
L 2-105
L 2-107
L 2-119
L 2-131
· L 8-25
· L 8-29
L 2-133
L 2-137
L 2-149
C 2-117
C 3-147
L 3-5
C 14-4, L 17-4
L 2-153
· L 6-43
L 2-157
L 2-159
L 2-161
L 2-163
L 2-165
L 2-177
L 2-179
L 2-181
· L 9-29
· L 9-35
C 2-125
C 2-131
C 2-137
C 2-137
C 3-155
C 3-167
C 3-175
C 3-179
C 3-187
· C 8-63
C 14-4, L 17-4
C 14-4, L 17-4
Model
AD2008
ADZOO9
AD2010
AD2016
ADZ020
AD2021
ADZ022
AD2023
AD2026
ADZ033
AD2036
AD2037
AD2038
AD2040
ADZ050
AD2051
AD2060
AD2061
AD2070
AD2071
ADZ700/270112702
AD2710/2712
AD3554 ...
AD3860 ...
AD5200 Series
AD5210 Series
AD5240
eAD5539
AD6012
AD7ll0
AD7ll1
AD7118
AD7224
AD7225
AD7226
eAD7228
AD7245
AD7248
AD7501
AD7502
AD7503
AD7506
AD7507
AD7510DI .
AD75llDI
AD7512DI
AD7520
AD7521
AD7522
AD7523
AD7524
AD7525
AD7528
AD7530
*C == Data ConversIOn Products Databook, D =: DSP Products Databook, L = Lmear Products Databook.
eNew product since publication of 1986 Data AcqUJsUJon Databook Update and Selectwn Guzde.
18-2 PRODUCT INDEX
Page*
C 14-4, L 17-4
C 14-4, L 17-4
· . . . . L 12-9
C 14-4, L 17-4
r..... 1',1 A T 17 A
· . . . L 12-11
C 14-4, L 17-4
C 14-4, L 17-4
· . . . L 12-13
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
L 12-15
L 12-15
L 12-17
L 12-17
L 12-19
L 12-19
C 8-67
C 8-71
C 14-4, L 17-4
C 14-4, L 17-4
C 3-189
C 3-189
C 3-391
L 2-183
C 14-4, L 17-4
C 14-4, L 17-4
· ... C 2-143
C 14-4, L 17-4
C 2-149
C 2-153
C 2-159
C 2-165
C 2-173
C 2-173
C 7-5
C 7-5
C 7-5
C 7-7
C 7-7
C 7-9
C 7-9
C 7-9
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
· ... C 2-187
C 14-4, L 17-4
· ... C 2-193
C 14-4, L 17-4
"T-~,
.L..
.1/-"
Page*
Model.
AD7531
AD7533
AD7534
AD7535
AD7536
AD7537
eAD7538
AD7541
AD7541A
AD7542
AD7543
AD7545
eAD7545A
AD7546
AD7547
AD7548
AD7549
AD7550
AD7552
eAD7569
AD7571
AD7572
AD7574
AD7575
AD7576
AD7578
eAD7579
eAD7580
AD7581
AD7582
AD7590DI ..
AD7591DI .
AD7592DI .
eAD7628
eAD7672
AD7820
eAD7821
AD7824
AD7828
AD7845
eAD7870
eAD7878
AD9000
eAD9002
eAD9003
eAD9012
eAD9500
eAD9502
eAD9521
eAD9610
eAD9611
AD9685/87 .
eAD9686
eAD9688
..
C 14-4, L 17-4
C 2-197
C 2-203
C 2-207
C 2-211
C 2-215
C 2-219
C 14-4, L 17-4
C 2-227
C 2-233
C 2-237
C 2-241
C 2-245
C 14-4, L 17-4
C 2-249
· ... C 2-253
· ... C 2-265
C 14-4, L 17-4
C 14-4, L 17-4
· ... C 3-195
C 14-4, L 17-4
· ... C 3-211
C 14-4, L 17-4
C 3-223
C 3-227
C 3-231
C 3-237
C 3-237
C 3-253
C 3-261
· C 7-13
· C 7-13
· C 7-13
C 2-273
C 3-267
C 3-283
C 3-295
C 3-305
C 3-305
C 2-277
C 3-317
C 3-323
C 3-331
C 3-337
C 3-345
C 3-353
· L 9-41
C 3-361
L 7-7
L 2-199
L 2-207
L 3-9
· L 3-13
C 3-369
Model
AD9700
eAD9701
AD9702
eAD9703
AD9768
eAD96685/87
AD ADC71172 .
AD ADC80 ..
AD ADC84/85 .
AD ADC-816
ADC-8S ..
ADC-I0Z ..
ADC-12QZ
ADC-14I1I7I .
ADC1100
ADCll02
ADC1105
ADC1111
ADC1130/1131 .
ADC1133
ADC1140
ADC1143
ADC-QM
AD DAC-08 .
AD DAC71172 .
AD DAC80
AD DAC85
AD DAC87
ADG201
ADG201A
ADG202A
eADG211A
eADG212A
ADG221
ADG222 .
eADG506A
eADG507A
eADGS08A
eADG509A
eADG526A
eADG527A
eADG528A
eADG529A
ADLHOO32G/CG
ADLHOO33G/CG
AD OP-07 .
AD OP-27 .
AD OP-37 .
eADREFOI
eADREF02 .
ADSHC-85.
ADSP-1008A .
ADSP-1009A .
ADSP-IOIOA .
Page*
C 2-281
C 2-287
C 2-293
C 2-297
C 2-301
· L 3-17
C 3-375
C 3-383
C 3-391
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
.... C 3-399
C 14-4, L 17-4
.... C 3-403
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 2-305
C 2-309
C 2-309
C 2-309
C 14-4, L 17-4
· C 7-17
· C 7-17
· C 7-21
· C 7-21
· C 7-25
· C 7-25
· C 7-29
· C 7-29
· C 7-37
· C 7-37
· C 7-41
· C 7-41
· C 7-49
· C 7-49
L 2-215
L 2-219
L 2-223
L 2-229
L 2-237
· C 8-75
· C 8-79
C 14-4, L 17-4
D 5-27
D 5-33
D 5-39
*C = Data Converswn Products Databook, D = DSP Products Databook, L = Lmear Products Databook.
eNew product SInce publication of 1986 Data AcqulSltlOn Databook Update and SelectIOn GUIde
PRODUCT INDEX 18-3
III
Model
Page·
Model
Page·
ADSP-1012A .
ADSP-1016A .
ADSP-1024A.
ADSP-1080A .
D 5-15
D 5-21
D 5-61
D 5-5
DASII57 .
DASII58.
DASII59 .
~A:t.DSP -108 L.A...
D 5-11
UftL.I/0J/OO
ADSP-llOl
ADSP-1I10A .
ADSP-1401
ADSP-141O
eADSP-2100
eADSP-3128
D 5-83
D 5-69
D 3-5
D 3-25
D 2-15
D 4-87
D 4-51
D 4-5
D 4-85
D 4-5
D 4-85
D 5-45
D 5-53
. C 4-49
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 3-407
· ... C 3-411
· ... C 3-415
C 14-4, L 17-4
· ... C 3-419
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
eADSP-320J/02
ADSP-3210/11
eADSP-3212
ADSP-3220/21
eADSP-3222
eADSP-7018
eADSP-8018
ADVFC32
APII62011718
BDM 161511616
BDM 1617 .
CAV-0920
CAV-1040
CAV-1202
eCAV-1205
CAV-121O
CAV-1220
DAC-M
DAC-QS ..
DAC-QZ ..
DAC-08 (see AD DAC-08)
DAC-IOZ .........
DAC71172 (see AD DAC7II72)
DAC80 (see AD DAC80)
DAC85 (see AD DAC85)
DAC87 (see AD DAC87)
DACI009
DAClI06
DAClI08
DACI132
DACI136
DACI138
DACII46
DAC1420
DAC1422
DAC1423
AS1I28 ..
DASII50.
DASII51 .
DAS1152.
DASII53·.
DASI155 .
DAS1156.
C 14-4, L 17-4
L 17-4
L 17-4
L 17-4
L 17-4
· ... C 2-319
· ... C 2-319
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
· . . . . C 9-23
· . . . . C 9-23
C 14-4, L 17-4
C 14-4, L 17-4
C
C
C
C
14-4,
14-4,
14-4,
14-4,
DRCI745/46
r...r.,....'..,r~lrr
DSCI705/06
DTM1716/17.
HAS-0802
HAS-1002
HAS-1201
..
..
HAS-1202/1202A .
HAS-1204
HAS-1409
HDD-1206.
HDD-1409.
HDG-0407 .
HDG-0807 .
HDG Series
HDH-0802 .
HDH-1003 .
HDH-1205 .
HDL-3806 .
HDM-121O .
HDS-08IOE
HDS-0820
HDS-1015E
HDS-1025
HDS-1240E
HDS-I250
HOS-050/050A/050C .
HOS-060 . . . .
HOS-IOOAH/SH
eHOS-200 ..
HTC-0300A
HTS-OOIO
HTS-0025
IPAI751
IPAI764
IRDCI730
IRDCI731
IRDCI732
IRDCI733
eLTS-2020
MATV-081I
MATV-0816
MATV-0820
MCII794 ..
MDA-IOZ
MOD-1005 .
MOD-1020.
MOD-1205.
OSCI754 .
OSC1758 ..
RDCI721
*C = Data Convemon Products Databook, D = nsp Products Databook, L = Lrnear Products Databook .
• New product since' publication of 1986 Data Acqumlwn Databook Update and Selection GUide.
18-4 PRODUCT INDEX
· C 9-27
· C 9-27
· C 9-27
C 5-7
C 14-4, L ii-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 3-423
C 3-429
C 3-433
C 3-437
C 2-325
C 14-4, L 17-4
C 2-335
· ... C 2-335
C 2-329
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
· ... C 2-339
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 2-345
L 2-245
L 2-251
L 2-255
L 2-257
· C 6-33
· C 6-37
· C 6-43
C 14-4, L 17-4
· . . . . C 5-15
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4.
C 12-1, LIS-I
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
· ... C 3-443
C 14-4, L 17-4
· . . . . C 5-17
C 14-4, L 17-4
Page*
Model
RDC I 74011 74111 742
RTM Series
SACl763 . . .
S8CDl752/53
S8CDl756/57
SCDXI623.
SCMI677 ..
SDC1604 . . .
SDC1700IRDC1700
SDC1702/RDC1702
SDC1704/RDCI704
SDCI711IRDCI711
SDCI721 . . . . . .
SDCI725/RDCI725
SDCI726IRDCI726
SDC1740/174111742
SDC176SIRDC176S
SHA-1A
SHA-2A
SHA-4 .
SHA-5
SHA-l114
SHA-1J34
SHAl144 .
SSCT1621
STM Series
TSLJ612 . . .
e1821
e1822
e1831
e1832
e1B41
e1851
IS14
IS20
IS24
IS40
IS44
IS60
IS61
IS64
IS74
2820
2822
2823
2824
2830
2831
2834
2835
2B50
2B52
2B53
2B54
·
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
· ....
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 5-19
L 17-4
L 17-4
L 17-4
L 17-4
L 17-4
L 17-4
L 17-4
L 17-4
L 17-4
L 17-4
L 17-4
L 17-4
L 17-4
L 17-4
C 5-19
L 17-4
L 17-4
L 17-4
L 17-4
L 17-4
L 17-4
L 17-4
L 17-4
L 17-4
L 17-4
L 17-4
L 11-31
L 11-35
L 11-37
L 11-45
L 11-53
L 11-55
· C 5-25
. . . C 5-33
· . C 5-25
· . C 5-33
· . C 5-25
· . C 5-33
: . C 5-33
· C 5-25
· C 5-41
L 11-59
L 11-63
L 11-67
C 14-4, L 17-4
· . . . L 11-71
· . . . L 11-71
C 14-4, L 17-4
C 11-1, L 14-1
· . . . L 11-77
C 14-4, L 17-4
C 14-4, L 17-4
. . . . . L 11-S1
Model
2B55 .
2B56 .
2B57A-l
285SA
2B59A
2B Series
2S20
2S50
e2S54
e2S56
e2SS0
e2SS1
e2S82
3B Series
4B Series
e5B Series
e5S70
e5S72 . . .
40
43
44
45
46
48
50
51
52
liS ..
141 ..
165 ..
171 ..
183 ..
230 .
232 .
233 .
234 .
235 .
260 .
261 .
272 .
273 .
275 .
276 .
277 .
284J
285 .
286J/281
288 .. .
289 .. .
290A/292A .
310 .
311 .
424.
426.
Page*
L 11-81
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
· . . . L 11-S7
C 14-4, L 17-4
· C 5-49
· C 5-51
· C 5-51
· C 5-59
· C 5-71
· C 5-83
L 11-89
L 11-93
L 11-95
· . . . . C 5-85
· . . . . C 5-85
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4,
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
· . . . . L 5-33
C 14-4, L 17-4
· . . . . L 5-39
C 14-4, L 17-4
· . . . . L 5-45
· . . . . L 5-51
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
C 14-4, L 17-4
II
*C ~ Data Convernon Products Databook, D ~ DSP Products Databook, L ~ L,near Products Databook.
eNew product since pubhcalion of 1986 Data AcqulSltwn Databook Update and Selecuon GUIde.
PRODUCT INDEX 18-5
Model
428 ..
429 ..
432 ..
433 .
434 ..
435 ..
436 ..
440.
442.
450.
451 .
452 .
453 .
454.
456 .
458 .
460.
606.
610 ..
752 . . .
7551759 .
756 . . .
757 . . .
902/902-2 .
903 .
904 .
905 .
906.
915 ..
920 ..
921 ..
922 ..
Page*
...
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
· ....
C 14-4,
· ....
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
C 14-4,
· ....
C 14-4,
· ....
ell-I,
C 14-4,
ell-I,
ell-I,
C 14-4,
C 14-4,
ell-I,
ell-I,
ell-I,
L
L
L
L
L
L
L
L
L
L
C
L
C
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
17-4
17-4
17-4
17-4
17-4
17-4
17-4
17-4
17-4
17-4
4-53
17-4
4-53
17-4
17-4
17-4
17-4
17-4
17-4
17-4
7-11
17-4
7-15
14-1
17-4
14-1
14-1
17-4
17-4
14-1
14-1
14-1
Model
923 .
925 .
926.
927 .
928 .
940 .
941 .
943 .
944 .
945 .
946 .
947 .
949 .
951 .
952 .
953 .
955 .
958 .
959 .
960 .
962 .
964 .
965 .
966 .
967 .
968 .
970 .
972 .
973 .
974.
975 .
976.
.,'
Page*
.
·C = Data Con .....sum ProduclS Databook, 0 = DSP Products Databook, L = Linear Products Databook.
eNew product since publication of 1986 Data AcqumlWn Databook UpdalJ! and Se/eclSon Guule.
1~6
PRODUCT INDEX
ell-I,
ell-I,
C 14-4,
ell-I,
ell-I,
C 11-2,
C 11-2,
C 11-2,
C 14-4,
C 11-2,
C 14-4,
C 14-4,
C 11-2,
C 11-2,
ell-I,
C 11-2,
ell-I,
C 11-2,
C 14-4,
C 11-2,
C 11-2,
C 11-2,
C 11-2,
C 11-2,
C 11-2,
C 14-4,
ell-I,
ell-I,
ell-I,
ell-I,
ell-I,
ell-I,
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
14-1
14-1
17-4
14-1
14-1
14-2
14-2
14-2
17-4
14-2
17-4
17-4
14-2
14-2
14-1
14-2
14-1
14-2
17-4
14-2
14-2
14-2
14-2
14-2
14-2
17-4
14-1
14-1
14-1
14-1
14-1
14-1
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