1988_Burr Brown_Integrated_Circuits_Data_Book_Supplement 1988 Burr Brown Integrated Circuits Data Book Supplement
User Manual: 1988_Burr-Brown_Integrated_Circuits_Data_Book_Supplement
Open the PDF directly: View PDF 
.
Page Count: 307
| Download | |
| Open PDF In Browser | View PDF |
...
::l
BURR-BROWN
Integrated Circuits
Data Book Supplement
~~
(1)
(Q
...Dl
(1)
C-
o
n_.
...
c
tn
...mmC
OJ
o
o
~
en
c
"'C
"'C
-
(1)
3
(1)
...
::l
AID Converters
D/A Converters
Sample/Hold Converters
Multiplexers
Power Supplies
Operational Amplifiers
Instrumentation Amplifiers
Isolation Amplifiers
Analog Circuit Functions
Military Products
RR-BROWN ®
II
I
{)1
MODEL INDEX
Model
Page
AD515 ................. 1-153
ADC10HT ............... 5-3
ADC71 ................. 5-13
ADC72 ................. 5-21
ADC73 ................. 5-29
ADC76JG/KG ........ 5-40
ADC76AM/BM/JM/KM .. 5-48
ADC80 ................. 5-56
ADC80H ............... 5-64
ADC80MAH12 ........... 87
ADC84 .................... 95
ADC85 ................. 5-72
ADC85H .................. 95
ADC87/883B .......... 12-8
ADC87H .................. 95
ADC574 ............... 5-80
ADC600 ................ 103
ADC674 ............... 5-93
ADC731 ............... 5-29
ADC800 .............. ~102
ADC804 .............. 5-114
DAC10HT ............... 6-5
DAC63 ................. 6-12
DAC70 ................. 6-20
DAC71 ................. 6-28
DAC71-CCD .......... 6-35
DAC72 ................. 6-20
DAC73 ................. 6-41
DAC74 ................. 6-49
DAC80-CBI ........... 6-64
DAC80-CCD .......... 6-72
DAC80P ................ 123
DAC82 ................. 6-78
DAC85 ................. 6-85
DAC87/883B ......... 12-24
DAC87-CBI-I ........ 12-36
DAC90 ................. 6-93
DAC700 ............... 6-98
DAC701 ............... 6-98
DAC702 ............... 6-98
DAC702/BS9000 ..... 13-9
DAC703 ............... 6-98
DAC703/BS9000 .... 13-10
DAC703/883B ......... 191
DAC705 .............. 6-106
DAC706 .............. 6-106
DAC707 .............. 6-106
DAC707JP ............. 131
DAC708 .............. 6-106
DAC709 .............. 6-106
DAC710 .............. 6-116
DAC711 .............. 6-116
DAC729 ................ 141
DAC736 ............... 6-41
DAC800 .............. 6-123
DAC811 .............. 6-130
DAC811 DIE .......... 11-3
DAC811JUlKU ........ 151
DAC812 .............. 6-138
DAC850 .............. 6-144
DAC851 .............. 6-144
DAC870/883B ....... 12-48
DAC1200 ............. 6-151
DAC1201 ............. 6-155
DAC1600 ............. 6-160
DAC7541 ............... 159
DACjl545 ............... 167
DAC7700 DIE ......... 11-8
DAC7701 DIE ........ 11-13
DAC8012 ............... 174
Data Communication
Devices ............. 16-5
Model
Page
DIV100 ................... 4-7
DSP/ay'· . ............... 260
INA101 .................. 2-7
INA101/BS9000 ...... 13-11
INA101 DIE ........... 11-18
INA101/883B ........... 200
INA102 ................ 2-18
INA102 DIE .......... 11-20
INA102KP ................ 42
INA104 ................ 2-26
INA105 ................ 2-36
INA106 .................... 45
INA110 ................ 2-46
INA110KP ................ 53
INA117 .................... 57
INA258/883B ........ 12-61
IS0100 .................. 3-6
IS0102 .................... 68
IS0106 .................... 68
LOG100 ............... 4-15
MCS Series ........... 16-5
MP32 ..................... 8-3
MPC4D .................. 9-3
MPC8D ................ 9-10
MPC8S .................. 9-3
MPC16S ............... 9-10
MPC800 ............... 9-17
MPC801 ............... 9-24
MPY100 ............... 4-23
MPY100/BS9000 ..... 13-12
MPY534 ............... 4-31
MPY634 ............... 4-38
Microcomputer
I/O Systems ........ 16-2
Microterminals ....... 16-1
OPA11HT ............... 1-9
OPA21 ................. 1-13
OPA27 ................. 1-17
OPA27/BS9000 ...... 13-13
OPA27 DIE ........... 11-22
OPA27HT ............. 1-29
OPA37 ................. 1-17
OPA37/BS9000 ...... 13-14
OPA37 DIE ........... 11-24
OPA37HT ............. 1-29
OPA101 ............... 1-33
OPA102 ............... 1-33
OPA103 ............... 1-45
OPA104 ............... 1-49
OPA105/883B ....... 12-74
OPA106/883B ....... 12-84
OPA111 ................ 1-53
OPA1111BS9000 .... 13-15
OPA111 DIE ......... 11-26
OPA111HT ............ 1-63
OPA111/883B .......... 210
OPA121 ............... 1-67
OPA121/BS9000 .... 13-16
OPA128 ............... 1-73
OPA156 ............... 1-81
OPA356 ............... 1-81
OPA201 ............... 1-87
OPA404 ............... 1-95
OPA404KP ................ 1
OPA445 ................... 5
OPA501 .............. 1-103
OPA501/883B ......... 222
OPA511 .............. 1-111
OPA512 .............. 1-116
OPA541 ................... 9
OPA600 .................. 15
OPA600/883B ....... 12-94
Model
Page
OPA602 .................. 23
OPA605 .............. 1-129
OPA606 .............. 1-135
OPA606 DIE .. : ...... 11-28
OPA633 .................. 29
OPA2111 ............. 1-143
OPA2111 DIE ......... 11-30
OPA2111KP .............. 38
OPA8780/883B .... 12-110
OPA8785/883B .... 12-120
PCI-3000 .............. 16-4
PCI-20000 ............. 16-4
PCM52 ................ 6-164
PCM53JG ............ 6-164
PCM53JP ............ 6-168
PCM54 ................ 6-180
PCM55 ................ 6-180
PCM56 .................. 182
PCM75 ................ 5-123
PGA100 ............... 2-58
PGA102 ............... 2-66
PGA200 ............... 2-76
PGA201 ............... 2-76
PSB100 ................ 14-7
PWR1XX ............... 14-9
PWR2XX .............. 14-11
PWR3XX .............. 14-13
PWR4XX .............. 14-15
PWR5XX .............. 14-17
PWR6XX .............. 14-19
PWR7XX ................ 237
PWR8XX .............. 14-25
PWR70 ................ 14-27
PWR71 ................ 14-29
PWR72 ................ 14-31
PWR74 ................ 14-33
PWR1017 ............... 241
PWR5038 ............... 245
PWR5104 ............... 247
PWR5105 ............... 247
PWS725 .................. 82
PWS726 .................. 82
REF10 ................. 4-46
REF101 ................ 4-52
SCADAR .............. 16-5
SDM854 ................. 8-7
SDM856 ............... 8-12
SDM857 ............... 8-12
SDM862 ................ 251
SDM863 ................ 251
SHC76 ................... 7-3
SHC85 ................. 7-11
SHC298AM ........... 7-15
SHC600 ............... 7-21
SHC803 ............... 7-24
SHC804 ............... 7-24
SHC5320 .............. 7-30
TM2500 ................. 258
TM2700 ................. 258
UAF11 ................. 4-60
UAF21 ................. 4-60
UAF41 ................. 4-68
VFC32 ................. 10-3
VFC32/BS9000 ...... 13-17
VFC32 DIE ........... 11-32
VFC32/883B ....... 12-135
VFC42 ................ 10-11
VFC52 ................ 10-11
VFC62 ................ 10-17
VFC62/BS9000 ...... 13-18
VFC100 ............... 10-25
VFC320 ............... 10-40
Model
Page
VFC320/BS9000 ..... 13-19
XTR100 ................ 2-82
XTR101 ................ 2-94
XTR101KP ............... 65
XTR110 ............... 2-104
XTR110 DIE .......... 11-34
100MS ................. 3-17
546 ..................... 14-3
550 ..................... 14-3
551 ..................... 14-3
552 ..................... 14-3
553 ..................... 14-3
554 ..................... 14-3
556 ..................... 14-3
558 ..................... 14-3
560 ..................... 14-3
561 ..................... 14-3
562 ..................... 14-3
700 .................... 14-35
710 .................... 14-37
722 .................... 14-41
724 .................... 14-45
3329/03 ...... ......... 1-157
3450 .................... 3-19
3451 .................... 3-19
3452 .................... 3-19
3455 .................... 3-19
3500 ...............•... 1-159
3500/883B . ......... 12-147
3507J ................. 1-161
3508J ................. 1-163
3510 ................... 1-165
3510VM/883B ...... 12-158
3521 ................... 1-167
3522 ................... 1-167
3523 ................... 1-170
3527 ................... 1-172
3528 ................... 1-174
3550 ................... 1-176
3551 ................... 1-180
3553 ................... 1-184
3554 ................... 1-188
3571 ................... 1-196
3572 ................... 1-196
3573 ................... 1-202
3580 ................... 1-206
3581 ................... 1-206
3582 ................... 1-206
3583 ................... 1-210
3584 ................... 1-214
3606 ................... 2-114
3627 ................... 2-122
3650 .................... 3-21
3652 .................... 3-21
3656 .................... 3-29
4023/25 ................ 4-80
4085 .........•.......... 4-82
4115/04 ..... ........... 4-88
4127 .................... 4-90
4203 .................... 4-97
4204 .................... 4-99
4206 .................... 4-99
4213 ................... 4-105
4213/BS9000 . ........ 13-20
4213/883B .. ........ 12-166
4214 ................... 4-109
4302 ................... 4-111
4340 ................... 4-117
4341 ................... 4-119
4423 ................... 4-123
DSPlay·· Burr-Brown Corp.
"*-A complete price list for these products is located inside the back cover.
SUPPLEMENT TO
INTEGRATED CIRCUiTS DATA BOOK
Burr-Brown Corporation • International Airport Industrial Park • P.O. Box 11400 • Tucson, Arizona 85734 USA
Telephone: 602-746-1111 • Telefax: 602-746-7357 • TWX 910-952-1111 • Telex: 66-6491 BURRBROWN ATU • Cable: BBRCORP
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for
inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such
information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No
patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN
does not authorize or warrant any BURR-BROWN product for use in life support deliices and/or systems.
© 1987 Burr-Brown Corporation
LI-340
Printed in
U.S.~July,
1987
INTRODUCTION
This supplement to the Burr-Brown Integrated Circuits Data Book contains
product data sheets on new products that have been developed and
introduced since the Data Book was published. Product lines such as
Operational, Instrumentation, and Isolation Amplifiers, Analog-to-Digital
and Digital-to-Analog Converters, Military Products, Moduiar Power
Supplies, Data Entry and Display Terminals, Microcomputer 1/0 Systems,
and Data Acquisition Components are represented.
The Model Index list on the inside of the front cover refers to models and
page numbers in both the Data Book and this supplement. Products in this
supplement are set in bold type.
A Selection Guide beginning on page iii contains a summary of performance characteristics of all products in both the Data Book and this
supplement.
A complete list of all Burr-Brown offices and sales representatives can be
found on the inside of the back cover. If you have questions on any of our
products please contact the nearest Burr-Brown office or sales representative.
iii
SELECTION GUIDE
HIGH PERFORMANCE OPERATIONAL AMPLIFIERS
GENERAL PURPOSE
options when a special function op amp is not required. You can be
confident that Burr-Brown's quality and reliability are inherent in
their design.
These moderately priced FET and bipolar op amps offer good
performance over a wide range of parameters. These are good
GENERAL PURPOSE
Offset Voltage,
max
Bias
Current
AI
Temp
(25· C),
2S·C,
Drift,
max
(±mV) (±pVl'C)
(nA)
Frequency
Response
Open
Loop
Gain,
min
(dB)
(MHz)
Unity
Slew
Gain
Rate
Rated
Output, min
Temp
Range l1l
Package
Page
Low Power
OPA21GZ
OPA21EZ
0.5
0.1
5
1
50
25
114
120
0.3
0.3
0.2
0.2
13.6
13.7
1.3
1.4
Ind
Ind
DIP
DIP
1-13
1-13
Switchable
Input
OPA201AG
OPA201BG
OPA201CG
OPA201SG
0.5
0.2
0.1
0.2
5
2
1
2
50
40
25
40
114
114
120
114
0.5
0.5
0.5
0.5
0.1
0.1
0.1
0.1
13.5
13.5
13.5
13.5
5
5
5
5
Com
Com
Com
MIL
DIP
DIP
DIP
DIP
1-B7
1-B7
1-B7
1-B7
Low Cost
FET
OPAI21KP*
OPA121KM
3
2
10
10
±o.010
±o.OO5
106
110
2
2
2
2
10
10
5
5
Com
Com
DIP
TO-99
1-67
1·67
Wide Temp
Range
OPAllHT
5
5'21
±25
94
12.0
7.0
10
15
-55·Cto
+175·C
TO-99
1-9
OP.A.2?HT
1),05
n.~fil2'
1."A
120
6
1.9
12
16121
-S5·Cto
+200·C
TO-99
1-29
OPA37HT
0.05
0.25121
lpA
120
36
11.9
12
16121
-55·Cto
+200·C
TO-99
1-29
OPA111HT
0.5
8121
0.002
114
2
2
10
5
-5S·Cto
+200·C
TO-99
1-63
Description
NOTES:
Model
(Vlpsec) (±V) (±mA)
(1) Com = 0 to HO·C; Ind = -2S·C to +B5·C; MIL = -5S·C to +125·C. (2) Typical.
LOW DRIFT
Low offset voltage drift vs temperature performance in both FET
and bipolar input types is obtained by our sophisticated drift
compensation techniques. First, the drift is measured and then
special laser trim techniques are used to minimize the drift and the
initial offset voltage at 25°C. Finally, "max drift" performance is
retested for conformance with specifications.
LOW DRIFT (:5SpVl·C)
Offset Voltage,
max
Description
Bias
Current
Temp
(25·
C),
At
2S·C
Drift
max
(±mV) (±pVrC)
(nA)
Open
Loop
Gain,
Frequency
Response
(dB)
Unity
Gain
(MHz)
min
Rated
Slew
Output, min
Rate
(Vlpsec) (±V) (±mA)
Temp
Range l11
Package
Page
FET
OPAlllAM*
OPAlllBM
OPA111SM
0.5
0.25
0.5
5
1
5
±0.002
±0.001
±o.o02
114
120
114
2
2
2
2
2
2
11
11
11
5
5
5
Ind
Ind
MIL
TO-99
TO-99
TO-99
1-53
1-53
1-53
Wideband
OPA156AM
OPA356AM
2
2
5
5
0.05
0.05
94
94
6
6
14
14
10
10
5
5
MIL
Com
TO-99
TO-99
1-Bl
1-81
Model
OPA606LM
0.5
5
±0.01
100
13
35
12
5
Com
TO-99
1-135
Dual FET
OPA2111BM*
0.5
2.8
±0.004
114
2
2
11
5
Ind
TO-99
1-143
Bipolar
OPA27A*
OPA37A*
OPA27B
OPA37B
OPA27C
OPA37C
OPA27E
OPA37E
OPA27F
OPA37F
OPA27G
OPA37G
OPA27GP
OPA37GP
0.025
0.025
0.060
0.060
0.100
0.100
0.025
0.025
0.060
0.060
0.100
0.100
0.100
0:100
0.6
0.6
1.3
1.3
1.8
1.8
0.6
0.6
1.3
1.3
I.B
I.B
I.B
I.B
±40
±40
±55
±55
±80
±BO
±40
±40
±SS
±55
±BO
±80
±BO
±80
120
120
120
120
117
117
120
120
120
120
117
117
117
117
8
63121
8
63121
8
8
63 121
8
63 121
1.9
11.9
1.9
11.9
1.9
11.9
1.9
11.9
1.9
11.9
1.9
11.9
1.9
11.9
12
12
12
12
12
12
12
12
12
12
12
12
12
12
16.6
16.6
16.6
16.6
16.6
16.6
16.6
16.6
16.6
16.6
16.6
16.6
16.6
16.6
MIL
MIL
MIL
MIL
MIL
MIL
Ind
Ind
Ind
Ind
Ind
Ind
Com
Com
TO-99,.DIP
T0-99, DIP
TO-99, DIP
TO-99, DIP
TO-99, DIP.
TO-99, DIP
TO-99, DIP
TO-99, DIP
TO-99, DIP
TO-99, DIP
TO-99, DIP
TO-99, DIP
DIP
DIP
1-17
1-17
1-17
1-17
1-17
1-17
1-17
.1-17
1-17
1-17
1-17
1-17
1-17
1-17
OPA21EZ
OPA21GZ
0.1
0.5
1
5
25
50
120
114
0.3
0.3
0.2
0.2
13
13
5
5
Ind
Ind
DIP
DIP
1-13
1-13
Low Power
63121
8
63121
8
63121
NOTES: (1) Com = 0 to +70·C, Ind =; -25·C to +BS·C, MIL = -SS·C to +125·C. (2) Gain-bandwidth product for OPA37. Av= 5 minimum.
"'Available in 20·pin ceramic leadless chip carriers.
v
LOW BIAS CURRENT
currents as low as 75fA (75 X 10-15 amps) and low voltage drift as
low as Ip.V/oC. With offset voltage laser-trimmed to as low as
250p.V, the need for expensive trim pot adjustments is eliminated.
Our many years of experience in designing, manufacturing and
testing FET amplifiers gives us unique abilities in providing low
and ultra l~w bias Current op amps. These amplifiers offer bias
LOW BIAS CURRENT (:550pA)
Offset Voltage,
max
Description
Model 1u
Bias
Current
At
Temp
(25' C),
25'C,
Drift,
max
(±mV) (±pV/'C)
(pA)
Open
Loop
Gain,
Frequency
Response
(dB)
Unity
Gain
(MHz)
min
Rated
Slew
Output, min
Rate
(Vlpsac) (±V) (±mA)
Temp
Range'"
Package
Page
To-99
TO-99
TO-99
1-53
1-53
1-53
OPAlllAM*
OPAll1BM
OPAlllSM
0.5
0.25
0.5
5
1
5
±2
±1
'±2
114
120
114
2
2
2
2
2
2
11
11
11
5
Ind
Ind
MIL
OPA101AM
OPA101BM
OPA102AM
OPA102BM
0.50
0.25
0.50
0.25
10
-15
-10
-15
-10
94
94
94
94
10
10
40
40
6.5
6.5
14
14
12
12
12
12
12
12
12
12
Ind
Ind
Ind
Ind
TO-99
TO-99
TO-99
TO-99
1-33
1-33
1-33
1-33
OPAI26JM*
OPA128KM
OPA128LM
OPA128SM
1
0.5
0.5
0.5
20
10
10
±0.300
±0.150
±0.075
±a.150
94
110
110
110
1
1
1
1·
3
3
3
3
10
10
10
10
5
5
5
5
Com
Com
Com
MIL
TO-99
TO-99
TO-99
TO-99
1-73
1-73
1-73
1-73
OPA2111AM*
OPA2111BM
OPA2111SM
OPA2111KM
OPA2111KP
0.75
0.5
0.75
2
2
6
2.8
6
15
15
±8
±4
±8
±15
±15
110
114
110
106
106
2
2
2
2
2
.2
2
2
2
2
11
11
11
11
11
5
Ind
Ind
MIL
Com
Com
TO-99
TO-99
T0-99
T0-99
DIP
1-143
1-143
1-143
38
39
OPA404AG*
OPA404BG
OPA404SG
OPA404KP
1
0.75
1
2.5
3'41
3141
3141
±8
±4
±8
±12
88
92
35
35
35
35
11.5
12
11.5
11.5
5
5
98
98
6.4
6.4
6.4
6.4
5
Ind
Ind
MIL
Com
DIP
Dip
DIP
DIP
1-95
1-95
1-95
1
Low Cost
OPAI21KM*
OPA121KP
2
3
10
10
±5
±10
110
106
2
2
2
2
11
11
5
5
Com
Com
TO-99
DIP
1-67
1-67
Wideband
OPA602AM
OPA602BM
OPA602CM
OPA602SM
1
0.5
0.25
0.5
15
5
2
5
10
2
1
2
75
88
92
6.5
6.5
6.5
6.5
20
24 .
28
24
10
10
10
10
15
15
15
15
rnd
Ind
Ind
MIL
TO-99
TO-99
TO-99
TO-99
23
23
23
23
OPA606KM
OPA606LM
OPA606SM
OPA606KP
1.5
0.5
1.5
3
5141
5
5141
10141
±15
±10
±15
±25
' 95
100
95
90
12.5
13
12.5
12
33
35
33
30
11
12
11
11
5
5
5
5
Com
Com
MIL
Com
TO-99
TO-99
To-99
DIP
1-135
1-135
1-135
1-135
3
1
1
50
15
25
0.300
0.150
0.075
86
92
88
0.35
0.35
0.35
1
1
1
10
10
10
5
5
5
Com
Com
Com
TO-99
TO-99
TO-99
1-153
1-153
·1-153
Premium
Performance
Low Noise
Ultra-Low
Bias
Current
Dual FET
Ouad FET
Low Cost,
Ultra-Low
Bias Current
AD515JH
AD515KH
AD515LH
5
10
5
5
5(41
98
5
5
5
5
5
5
5
NOTES: (1) "(0)" indicates product also available with screening for increased reliability. (2) Com = 0 to +70'C, Ind =-25'C to +85'C, MIL =-SS'C to
+125'C. (3) Gain-bandwidth product. (4) Typical.
LOW NOISE
rely on "typical" specs for his demanding low noise designs. These
fully characterized parts allow a truly complete error budget
calculation.
Now both FET and bipolar input op amps are. offered with
gnaranteed low noise specifications. Until now the designer had to
LOW NOISE (Guaranteed en)
Description
Bipolar
Model
OPA27A*
OPA37A*
OPA27B
OPA37B
OPA27C
OPA37COPA27E
OPA37E
OPA27F
OPA37F
Noise
Voltage
at
10kHz,
max
(nV/y'Hz)
3.8
3.8
3.8
3.8
4.5 '
4.5
3.8
3.8
3.8
3.8
Bias
Current
(25'C),
max
(pA)
.Offset
Voltage, max
Temp
At
Drift
25'C
(±mV) (±pV/'C)
±40nA .0.025
±40nA 0.025
±55nA 0.060
±S5nA 0.060
±80nA 0.100
±80nA 0.100
±40nA 0.025
±40nA 0.025
±55nA 0.060
±55nA 0.060
0.6
0.6
1.3
1.3
1.8
1.8
0.6
0.6
1.3
1.3
Open
Loop
Gain,
min
(dB)
120
120
120
'120
117
117
120
120
120
120
*Available in 20-pin ceramic lead less chip carriers.
Frequency
Response
Gain
Bandwidth
(MHz)
8
63
8
63
8
63
8
63
8
63
Slew
Rate,
min
(V/poec)
(±V)
(±mA)
'1)
Package
Page
1.7
11
1.7
11
1.7
11
11
11
1.7
11
12
12
12
12
12
12
12
12
12
12
16.6
16.6
16.6
16.6
16.6
16.6
16.6
16.6
16.6
16.6
MIL
MIL
MIL
MIL
MIL
MIL
Ind
Ind
Ind
Ind
TO-99,DIP
TO-99, DIP
TO-99, DIP
TO-99, DIP
TO-99,DIP
TO-99, DIP
TO-99, DIP
TO-99, DIP
TO-99, DIP
TO-99, DIP
1-17
1-17
1-17
1-17
1-17
1-17
1-17
1-17
1-17
1-17
Rated
Output, min
Temp
Range
This table continued on next page.
Models in boldface type are found in this supplement; others are in the Burr-Brown Integrated Circuits Data Book.
vi
LOW NOISE (Guaranleed e.) (CO NT)
Frequency
Noise
(25'C),
max
(pA)
AI
Temp
25'C
Drift
(±mV) (±pVl'C)
4.5
4.5
±80nA
±80nA
0.100
0.100
1.8
1.8
OPA101AM
OPA101BM
8
8
-15
-10
0.5
0.25
OPA102AM
OPA102BM
8
8
-15
-10
OPA111AM'
OPAll1BM
OPA111SM
8
8
8
±2
±1
±2
Model
OPA27G
OPA37G
Wide
Bandwidlh
FET
Low CoSI
Dual FET
NOTES:
Response
Open
Loop
Bias
Current
Description
Bipolar
Offsel
Vollage, max
Vollage
al
10kHz,
max
(nVl.jHz)
Slew
Rale,
Gain
Raled
(dB)
Bandwidlh
(MHz)
(Vlpsec)
(±V)
(±rnA)
'"
117
117
8
63
1.7
11
12
12
16.6
16.6
Ind
10
5
94
94
20
20
5
5
12
12
12
12
lr1d
0.5
0.25
10
5
94
94
40
40
10
10
12
12
12
12
ImJ
0.5
0.25
0.5
5
1
5
114
120
114
2
2
2
1
1
1
11
-11'
11
Gain,
min
min
Output, min
Temp
Range
Package
Page
TO-99, DIP
TO-99, DIP
1-17
1-17
TO-99
TO-99
1-33
1-33
Ind
TO-99
TO-99
1-33
1-33
5
5
5
Ind
Ind
MIL
TO-99
TO-99
TO-99
1-53
1-53
1-53
Ind
Ind
OPA606LM
13
±10
0.5
5
100
13
25
12
5
Com
TO-99
1-135
OPA27GP
OPA37GP
4.5
4.5
±80nA
±80nA
0.100
0.100
1.8
1.8
117
117
8
63
1.9121
11.9[21
10
10
16.6
16.6
Com
Com
DIP
DIP
1-17
1-17
8
8
8
±8
±4
±4
±15
±15
0.75
0.5
0.75
2
2
6
110
114
110
108
108
2
2
2
2
2
1
1
1
1
1
11
11
11
11
11
5
5
5
5
5
Ind
2.8
6
15
15
MIL
Com
Com
TO-99
TO-99
TO-99
TO-99
DIP
1-143
1-143
1-143
38
38
OPA2111AM'
OPA2111BM
OPA2111SM
OPA2111KM
OPA2111KP'
612~
61~'
(1) Ind = -25'C 10 +85'C, MIL = -55'C 10 +125'C, Com =O'C 10 +70'C.
Ind
(2) Typical.
UNITY-GAIN BUFFER (Power Booster)
circuit; may be used inside the feedback loop of another op amp to
These versatile amplifiers: boost Ihe output current capability of
another amplifier; buffer an impedance that might load a critical
form a current-boosted, composite amplifier. Currents as high as
±IOOmA are available with speeds of 2000V/ JLsec.
UNITY-GAIN BUFFER
Raled
Oulpul, min
Model
(±V)
Frequency Response
Inpul
(±mA)
-3dS
(MHz)
Full Power
BW(MHz)
Slew Rale
(Vlpsec)
Gain
(VN)
Impedance
(0)
Temp
Rangu lll
Package
Page
High Performance
3553AM
10
200
300
32
2000
=1
1011
Inct
TO-3
1-184
Low Cost
OPA833AH
OPA633SH
OPA633KP
10
10
10
80
80
80
275
275
275
65
65
65
1000
1000
1000
=1
=1
=1
10'
10'
10'
Ind
MIL
Com
TO-8
TO-8
DIP
29
29
29
Description
NOTES:
(1) Ind = -25'C 10 +85'C, MIL = -55'C 10 +125'C, Com = O'C to +70'C.
WIDE BANDWIDTH
Design expertise in wide band circuits combines with our fully'
developed technology to create cost effective wide band op amps,
Burr-Brown high speed amplifiers also offer outstanding DC
performance specifications,
WIDE BANDWIDTH (2:5MHz)
Offset Voltage,
max
Frequency Response
Description
FET
Bipolar
Model '11
Gain
Bandwidth
(MHz)
Slew
Rate,
min
(Vlpsec)
3554AM, (a)
3554BM, (a)
3554SM, (a)
1700, A = 1000
1700, A = 1000
1700, A = 1000
1000
1000
1000
120
120
120
ext.
ext.
ext.
10
10
10
100
100
100
2
1
1
3551J
35515, (a)
50, A=10,
50, A=10
250
250
400
400
ext.
ext.
10
10
10
10
3550J
3550K
35505, (a)
10,A=10
20,A=1
10,A=1
65
100
65
400
400
400
into
Int.
int.
10
10
10
3508J
3507J, (a)
100, A=l00
20, A=10
0
80
-
ext.
ext.
10
10
Corn-
ts
±0.1%
(nsec)
penss-
200
tion
Rated
Output, min
AI
Temp
25'C
Drift
(±V) (±mA) (±mV) (±pVl'C)
Open
Loop
Gain,
min
TOlllp
Rnll(]o
(dB)
w
Package
Page
50
15
25
100
100
100
In ..
TO-3
TO-3
TO-3
1-188
1-188
1-188
1
1
5013.1
88
88
Com
TO-99
TO-99
1-180
1-180
10
10
10
1
1
1
50131
88
88
88
Com
50~1
MIL
TO-99
TO-99
TO-99
1-176
1-176
1-176
10
10
5
10
30131
30<31
98
83
Corn
COllI
TO-99
TO-99
1-163
.1-161
50~1
50~1
Ifld
MIL
MIL
CUIlI
*Available in 20-pin ceramic leadless chip carriers.
Th!:1 table continued on next page.
Models in boldface type are found In this supplement; others are in the Burr-Brown Integrated Circuil" Data Book.
vii
WIDE BANDWIDTH (25M Hz) (CONT)
Frequency Response
Description
FET
Advance {
Information
Gain
Bandwidth
(MHz)
OPA156AM
OPA356AM
6,A=1
6,A=1
OPA802AM
OPA802BM
OPA802CM
OPA802SM
6.5
6.5
6.5
6.5
Modell'!
OPA605H
OPA605A
OPA605K
OPA605C
Ouad FET
Low Noise
Bipolar
Low Noise
FET
Fast
Settling
?OO.
200,
?OO,
?OO.
Slew
Rate,
Offset Voltage,
max
Com-
ponsa-
(Vlpsec)
±0.1%
(nsec)
10
10
1.5psec
1.5psec
int.
int.
10
10
5
5
20
26
800
800
800
Int.
Int.
Int.
Int.
10
10
10
10
15
15
15
15
10
10
10
10
30
30
30
30
11
12
11
11
5
5
min
24
A=IOOO
A=1000
A=1000
A=looo
24
800
300131
300
300131
300
oxt.
oxt
300131
300.31
300
300
ext.
ext.
inl.
int.
12.5
13
12.5
12
22
25
22
20
lpsec
lpsec
lpsec
lps9C
OPA404AG
OPA404BG
OPA404SG
OPA404K"
6.4
6.4
6.4
6.4
24
28
24
600
800
600
600
Int.
OPA27A*
OPA37A*
OPA27B
OPA37B
OPA27C
OPA37C
OPA27E
OPA37E
OPA27F
OPA37F
OPA27G
OPA37G
B,A=1
63,A=5
B,A= 1
63, A=5
B,A=1
63, A = 5
8,A=1
63, A=5
8,A=1
63, A=5
8,A=1
63, A = 5
1.7
11
1.7
11
1.7
11
1.7
11
1.7
11
1.7
11
-
int. I '"
int. I .'
-
OPAIOIAM
OPA101BM
~O,
~O,
A=I00
A=I00
5
5
OPAI02AM
OPAI02BM
~O,
A=IOO
1.000, A=looo
1;000, A=looo
5000, A = 1000
11.5
11.5
11.5
11.5
5
(dB)
I~
. Package
Page
2
2
5
5
94
94
MIL
Com
TO-99
TO-gg
1-81
1-81
1
0.5
0.5
15
5
2
5
75
88'
92
88
Ind.
Ind.
Ind.
MIL
TO-gg
TO-99
TO-99
TO-99
23
23
23
23
1
1
0.5
0.5
25
25
5
5
96131
Com
Ind
Com
Ind
DIP
DIP
DIP
DIP
1-129
1-129
1-129
1-129
1.5
0.5
1.5
3
5131
95
100
TO-99
To-99
TO-99
To-gg
1-135
1-135
1-135
1-135
DIP
DIP
DIP
DIP
1-85
1-95
1-95
1
0~2S
95
10.31
90
Com
Com
MIL
Com
3QJ
88
92
88
Ind
Ind
MIL
5'
88
Com
Int.· 4 '
int.''''
0.025
0.025
0.060
0.060
0.100
0.100
0.025
0.025
0.060
0.060
0.100
0.100
0.6
0.6
1.3
1.3
1.8
1.8
0.6
0.6
1.3
1.3
1.8
1.8
120
120
120
120
117
117
120
120
120
120
117
117
MIL
MIL
MIL
MIL
MIL
MIL
Ind
Ind
Ind
Ind
Ind
Ind
2.5psec
2.5p.ec
int.
int.
12
12
12
12
0.5
0.25
10
5
94
94
Ind
Ind
TO-99
TO-99
1-33
1-33
10
10
1.5psec
1.5psec
int.
int.
12
12
12
12
0.5
0.25
10
5
94
94
Ind
Ind
TO-99
TO-99
1-33
1-33
500
500
500
500
500
oxt.
oxt.
oxt.
9
9
9
9
9
9
180
180
180
180
180
180
5
4
±5
±4
±5
±4
100
20
±80
±40
±100
±80
86
86
86
86
500
60
80
80
60
60
80
86
MIL
MIL
Ind
Ind
MIL
MIL
DIP
DIP
DIP
DIP
DIP
DIP
12-94
12-84
1-121
1-121
1-121
1-121
-
10
200
50
300.31
NA
Ind
TO-3
1-184
int.
12
12
16.6
16.6
0.100
0.100
1.8
1.8
117
117
Com
Com
DIP
DIP
1-17
1-17
0.25131
0.25 13)
120
120
-55'C
to
+200'C
To-99
TO-gg
1-29
1-29
5
98
-55'C
to
+2OO'C
To-99
1-9
-
-
3553AM, (0)
32
20Q0
-
Low Cost
OPA27GP
OPA37GP
B,A=I
63, A=5
1.9131
11.9~J
-
OPA27HT
OPA37HT
6,A=1
36, A=5
1.9
11.9
-
OPAIIHT
12,A=1
4
1.5psec
-
-
int.
int. I'"
int. I'"
int. I.. '
int.''''
int.''''
int. I .. '
int. I '"
int. I '"
ext.
ext.
ext.
int.'·'
int.
int.I"1
12
12
ext.
10
5
16.6131 0.050
16.6131 0.050
15
5131
NOTES: (1) "(0)" indicates product also available with screening for increesed reliability.
MIL = -55'C to +125'C. (3) TYPIcal. (4) G = 5 min for OPA37.
leadln~s
5131
16.6
16.6
16.6
16.6
16.6
16.6
16.6
16.6
16.6
16.6
16.6
16.6
Unity-Gain
Buffer
*Available in 2o-pin ceramic
96131
96IS1
96131
12
12
12
12
12
12
12
12
12
12
12
12
int.
5
Temp
Range
3131
5131
5000, A = 1000
51100, A = 1000
1000
into
5
Open
Loop
Gain,
min
5
5
24
~O,A=IOO
into
into
At
Temp
25'C
Drift
(±V) (±mA) (±mV) (±pVrC)
1
0.75
1
2.5
OPA800UM
OPA600VM
OPA600BM
OPA600CM
OPA600SM
OPA600TM
Wide Temp
Range
tion
OPA606KM
OPA606LM
OPA606SM
OPA606KP
snoo, A =
Rated
Output, min
Is
3 131
86
TO-99,
TO-gg,
TO-99,
TO-99,
TO-99,
TO-gg,
TO-99,
To-99,
TO-99,
TO-99,
TO-gg,
TO-99,
(2) Com = 0 to +70·C, Ind
chip carriers.
Models in bold lace type are found in this supplement; others aro in the Burr-Brown Integrated CIrcuits Data BOOk.
Vlll
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
1-17
1-17
1-17
1-17
1-17
1-17
1-17
1-17
1-17
1-17
1-17
. 1-17
-25' C to +85· C,
HIGH VOLTAGE-HIGH CURRENT
Offset Voltage,
max
Rated Output,
(±V)
(±mA)
At
25'C,
(±mV)
20
26
20
26
lOA
lOA
lOA
lOA
10
5
10
5
65
40
65
40
min
Description
High Power
Modell1!
OPA501AM
OPA501BM
OPA501RM
OPA501SM
Frequency
Response
Bias
Current
Temp
Drift,
(±pVl'C)
(25'C),
max
(pA)
Unity
(MHz)
Slew
Rate
(Vlpsec)
40nA
20nA
40nA
20nA
1
1
1
1
1.35
1.35
1.35
1.35
Gain
Open
Loop
Temp
Gain
Range
(dB)
..,
Package
Page
94
98
94
98
Ind
Ind
MIL
MIL
TO-3
TO-3
TO-3
TO-3
1-103
1-103
1-103
1-103
OPA511AM
22
5A
10
65
40
1
1
91
Ind
TO-3
1-111
OPA512BM
OPA512SM
35
35
lOA
15A
6
3
65
40
30
20
4
4
2.5
2.5
110
110
Ind
MIL
TO-3
TO-3
1-116
1-116
OPA541AM
OPA541BM
OPA541SM
30
35
35
5A
SA
SA
10
1
1
40
30
30
50
50
50
1.6
1.6
1.6
8
8
8
90
90
90
fnd.
Ind.
MIL
TO-3
TO-3
TO-3
9
9
9
3573AM
3572AM
3571AM, (0)
20
30
30
2A1Sl
lA14:
10
2
2
65
40
40
40nA
-100
-100
1
0.5
0.5
2.6
3
3
94
94
94
Ind
Ind
Ind
TO-3
TO-3
TO-3
1-202
1-196
1-196
Wideband
3554AM, (0)
35548M, (0)
3554SM, (0)
10
10
10
100
100
100
2
1
1
50
15
25
-50
-50
-50
170013 )
170013)
170013)
1200
1200
1200
100
100
100
Ind
Ind
MIL
TO-3
TO-3
TO-3
1-188
1-188
1-188
High Voltage
3584JM, (0)
3583AM
3583JM
15
75
75
15
30
60
3
3
3
3
3
10
25
25
25
25
25
30
-20
-20
-20
-20
-20
-50
20 131
150
30
30
20
126
118
118
118
TO-3
TO-3
TO-3
TO-3
1-214
1-210
1-210
1-206
3581J
3580J
145
140
140
145
70
30
TG-3
1-2:3
TO-3
1-206
Advance {
Information
OPA445BM
OPA445SM
35
35
15
15
3
1
10
10
50
50
2
2
Booster
3553AM, (0)
10
200
50
300/6 )
-200
OPA633AH
OPA633SH
OPA633KP
10
10
10
80
80
80
15
15
15
33(6)
35pA
35pA
35pA
3582.1
2AI51
33 161
33 161
20
11::::
15
106
Com
Ind
Com
Com
Corn
Com
10
10
100
100
Ind
MIL
TO-99
TO-99
5
5
300
2000
NA
Ind
TO-3
1-184
275161
1000
1000
1000
NA
NA
NA
Ind
MIL
TO-8
TO-8
DIP
29
29
29
5
5
5
5
5
275(61
275(61
NOTES: (1) "(0)" Ind. cates product also ava.lable w.th screening for increased reliability.
to +t25'C. (3) Gain-bandwidth product. (4) 2A peak. (5) SA peak. (6) Typical.
(2) Com
Com
= 0 to HO'C, Ind =-25'C to +85'C, MIL = -55'C
INSTRUiViENTAll0N AMPLIFIERS AND
PROGRAMMABllE GAIN AMPLIFIERS
INSTRUMENTATION AMPLIFIERS
Range
INA104HP
INA104JP
INA104KP
INA104AM
INA104BM
INA104CM
INA104SM
1_1000121
1_1000121
1-1000121
1-1000 121
1-1000 121
1-1000121
1-1000121
0.15
0.15
0.15
0.15
0.15
0.15
O. t5
INA101AM'
INA101CM
iNA101SM
INA101AG
INA101CG
INA101SG
INA101HP
INA101KU
1_1000 121
1-1000121
1-1000121
1-1000121
1-1000121
1-1000121
1-1000121
1-1000 121
0.03
0.03
0.03
0.03
0.03
0.03
0.3
0,3
22141
INA102AG'
INA102CG
} 1,10,100,
1000
0.25
0.15
20
15
Gain
Description
Very-High
Accuracy
Low Quiescent
Power
Input Parameters
Gain
Accuracy,
G=100,
25'C,
max (0/0)
Model
NonGain
Drift,
,Linearity,
G =100
G=100,
(ppm/'C) max(%)
22
22
22
22131
22131
22131
22131
22141
221~1
22 131
22 131
22 (3)
2213)
22[31
Offset
Voltage
Dynamic
Response,
CMR, DC to
60Hz, G =10,
lkCl Unbal.,
vs Temp,
G =100,
±3dB BW
(kHz)
Range
Temp
min (dB)
max (p.V/"'C)
'"
Package
Page
±0.007
±0.003
±0.003
±O.OO7
±0.003
±O.OOJ
±O.OOJ
96
±(2±20/G)
±(0.25 ± 10/G)
±(0.75 ± to/G)
±(2±20/G)
±(0.75 ± 10/G)
±(0.25 ± 10/G)
±(0.75 ± 10/G)
25
25
25
25
25
25
25
Com
Com
Com
Ind
Ind
Ind
MIL
DIP
DIP
DIP
DIP
DIP
DIP
DIP
2-26
2-26
2-26
2-26
2·26
2-26
2-26
±0.007
±0.004
±0.004
±0.OO7
±0.003
±0.003
±0.OO7
±0.O07
96
96
96
96
96
96
25
25
25
25
25
25
25
25
Ind
Ind
MIL
Ind
Ind
MIL
Com
Com
TO-laO
TO-l00
TO-l00
DIP
DIP
DIP
DIP
SOIC
2-7
2-7
2-7
2-7
2-7
2-7
2-7
90
±(2+20/G)
±(0.25 + 10/G)
±(0.25 + la/G)
±(2 +20/G)
±(0.25 + 10/G)
±(0.25 + la/G)
±(2 + 20/G) typ
±(2 + 20/G) typ
xxiii
±0.05
±0.02
80
90
±(5+10/G)
±(2+ 5/G)
3
3
Ind
Ind
DIP
DIP
2-18
2-18
96
96
96
96
96
96
90
*Available in 20-pin ceramic leadless chip carriers.
I nls table continued on next page.
Models in boldface type are found in this supplement; others are in the Burr-Brown Integrated Circuits Data Book.
ix
INSTRUMENTATION AMPLIFIERS (CO NT)
Gain
G=100,
25'C,
max (%)
Drift.
G =100
(ppm/'C)
} 1,10,100,
200,500
} 1,10,100
200,
500
0.2
0.1
0.1
0.2
0.2
3627AM
3627BM
lVIV, fixed
1V1V, fixed
0.01
om
INA105AM'
INA105BM
INA105KP
INA105KU
1V1V, fixed
Description
Gain
Range
Model
Fast Settling
INAll0AG'
INA110BG
INA110SG
INA110KP
INAll0KU
FET Inpul
Buffer,
Unity-Gain
Oifferential
Input Parameters
Gain
Accuracy.
0.01
G=100,
max(%)
CMR, DC to
60Hz, G = 10,
lkO Unbal"
min (dB)
40
20
20
Styp
Styp
±0.02
±0.01
0.01·
0.02
0.02
87
96
9S
87
87
5
5
±O.O01 13!
±O.OO1 13J
±O.OOlI3l
±O.OOl 131
±O.OOlI31
±O.OO1 131
86 161
72161
721111
NonLinearity.
Dynamic
Response,
Offset
Vortage
G=100,
±3dB BW
(kHz)
Temp
Range
Package
Page
±(2+50/G)
±(2 + 20/G) typ
±(2 + 2OJG) typ
470
470
470
470
470
Ind
Ind
MIL
Com
Com
DIP
DIP
DIP
DtP
SOIC
2-46
2-46
53
53
53
90
100
30
20
800131
600131
Ind
Ind
TO-99
TO-99
2-122
2-122
SOISI
20
10
51yp
5
1000 131
1000(3)
1000 131
1000131
Ind
Ind
Com
Com
TO-99
TO-99
DIP
SOIC
2-36
2-36
2-36
5001~'
500151
500151
Ind
Ind
Com
DIP
DIP
DIP
45
45
45
vs Temp,
max (pV!'C)
±(5 +100/G)
±(2 +50/G)
• (11
1VIV. fixed
om
lVIV, fixed
1VIV. fixed
0.025
0.025
5
,5
5
5
INA108AM
INA106BM
INA106KP
10VIV IIxed
10VIV IIxed
10VlV IIxed
0.01
0.01
0,025
10
10
4typ
0.001
0.001
0.001
tOO l61
86(11)
5
2
0.2typ
INA117AG
INA117BG
INA117P
lVlVllxed
lVIV IIxed
lV/V fixed
O.05C3~
0.02131
0.05 431
10'31
10/31
10 131
0.001 131
0.001'31
0.001 431
74 13•61
8613.6 )
7413.61
40
20
40
200131
20043)
200131
Ind
Ind
Com
TO-99
TO-99
DIP
57
57
57
PGA100AG
PGA100BG
Gain set
with4·bit
word 1, 2,
4,8 ... 128
PGA102AG
PGA102BG
PGA102SG
PGA102KP
Gain set
with 2·bit
word 1, 10
100
Instrumentalion
Amplifier
Input
PGA200AG
PGA200BG
Gain set
with 2·bit
word 1, 10,
100,1000
Differential
Input
3606AG
3606AM
3606BG
3606BM
Gain set
with3·blt
word 1, 2, 4
8 ... 1024
Gain of 10
Differential
High Common
Mode Voltage
Differential
(200VDCCMV
94161
xxIII
PROGRAMMABLE GAIN AMPLIFIERS
Noninverting
Multiplexed
Input
0.05
0.02
10
10
±O,O)
±0.005
NA
NA
61yp
61yp
5MHz
5MHz
Ind
Ind
DIP
DIP
2-58
2-58
0.02
0,01
0.02
20
20
20
50
0.01
0.01
0,01
0.01
-
3,G=I00
3,G=100
3,G=I00
3,G=I00
250
250
250
250
Ind
Ind
Ind
Com
DIP
DIP
DIP
DIP
2-66
2-66
2-1;6
2-66
0.05
0.02
20
10
±0.007
±0.003
96
96
2, G = 100
0.4, G =100
30
30
Ind
Ind
DIP
DIP
2-76
2-76
0.05
0.05
0.02
0.02
10
10
10
10
0.004
0.004
0.004
0.004
90, G=1'
90, G =1
9O,G=1
90,G =1
±(3+ 50/G)
±(3 +50JG)
±(1 +20/G)
±(1 +20/G)
40
40
40
40
Ind
Ind
Ind
Ind
DIP
DIP
DIP
DIP
2-114
2-114
2-114
2-114
om
NOTI;S: (1) Com ~ O'C to +70'C, Ind ~ -25'C to +85'C, MIL
external reSistor. (5) Gain = 10. (6) No source imbalance.
~
-5S'C to +125'C.
(2) Set with external resistor.
(3) Unity-gain.
(4) With zero TC
PRECISION TRANSMITIERS
Span
Description
Two·Wire
Three·
Wire and
Current
Source
Input Parameters
Output Parameters
Model
Untrimmed
Error,
max(%)
CMR,
DC,
min
(dB)
Current
Range
(rnA)
'XTR100AM
XTR100AP
XTR100BM
XTR100BP
-3
-3
-3
-3
XTR101AG*
XTR101BG
-5
-5
om
±100
±100
±60
±30
±1.5
±0.75
90
90
4-20
4-20
±10
±6
XTR101AP
XTR101AU
-5
-5
0.01
0.01
±100
±100
±100
±100
±1,5
±1.5
90
90
4-20
4-20
XTR110AG'
XTR110BG
XTR110KP
XTR110KU
0.6
0.2
0.025
0.005
0.025
0.025
50
30
50
50
-
--
-
} 4-20,
0-20,
5-25
Non·
Linearity,
max(%)
Temp
Oriftl1i
(ppmI'C)
Offsel
Voltage,
max (PV)
Offset
Voltagevs
Temp, max
(pVl'C),
0.01
±100
±100
±100
±100
±50
±50
±25
±25
±1
±1
±D.5
±D.5
90
90
90
90
4-20
4-20
4-20
4-20
O.S
0,6
NOTES: (1) With zero TC span resistor.
ranges with appropriate,circuit.
om
0.01
0.01
0.01
-
-
(2) Com ~ 0 to +70' C, Ind
~
'"
Olfsel
Current
Error,
max (PA)
FS Output
Current
Error,
max (PA)
Temp
Range
±20
±20
±20
±20
Pack·
age
Page
Ind
Ind
Ind
Ind
DIP
DIP
DIP
DIP
2-82
2-82
2-82
2-82
±40
±30
Ind
Ind
DIP
DIP
2-94
2-94
±19
±19
±SO
±60
rnd l31
Indl31
DIP
SOIC
65
xxIII
±64
±16
±64
±64
±96
±32
±96
±S6
Ind
Ind
Com
Com
DIP
DIP
DIP
SO.IC
2-104
2-104
2-104
xxIII
±4
±4
±4
. ±4
-25' C to +85' C, MIL ~ -55' C to +125'C.
'"
(3) -40'C to +85'C.
*Available in 20-pin ceramic leadless chip carriers.
Models in boldface type are found in this supplement; .others are in the Burr-Brown Integrated Circuits Data Book.
x
(4) Many more
ISOLATION PRODUCTS
TRANSFORMER COUPLED AMPLIFIERS
Isolation
Voltage (V)
Isolation
Mode Rejeetion, typo
DC
(dB)
60Hz
(dB)
Leakage
Current
at Test
Voltage
(pA)
Gain
peak
peak
(0)
(pF)
(%)
(%)
Voltage
Drift.
(±pVl'C)
max
max
±3dB
Freq.
(kHz)
Required
C1I
Package
Page
Low Drift l2J
3450
±500
±2000
t60
120
,t
10'2
16
±0.005
±0.0015·
100
50nA
1.5
No
Com
Module
3-19
Low Bias
3451
3452
3455
±500
±2000
±2000
±5000
10'2
10'2
10'2
16
16
16
±0.025
±0.025
±0.025
±0.005
±0.O05
±0.005
100
100
100
25pA
10pA
20pA
2.5
2.5
2.5
No
NO'41
'"
120
120
120
1
t
'"
160
160
160
No''''
Com
Com
Com
Module
Module
Module
3-19
3-19
3-19
3656AG
±3500
±BOOO
160
125
0.5
10'2
6
±0.1
±0.03
25+
(500/G,)
5+
(tOOO/G,)
200 +
(1000/G,)
50+
(750/G,)
10+
(350/G,)
100nA
30
No
Ind
DIP
3-29
Description
FET
Highest
Isolation
Voltage
Model
Contin-
Pulsel
UQUS,
Test,
'"
Isolation
Impedance
Nonlinearity
max
typo
3656BG
±3500
±BOOO
160
125
0.5
10'2
6
±0.05
±0.03
3656HG
±3500
±BOOO
160
125
0.5
10'2
6
±0.15
±0.03
3656JG
±3500
±BOOO
160
125
0.5
10'2
6
±0.1
±0.03
10'2
6
±0.1
±0.03
3656KG
±3500
±BOOO
160
125
0.5
Balanced
Current
Input
3650HG
3650JG
3650KG
3650MG
±2000
±2000
±2000
±2000
±5000
±5000
±5000
±5000
140
140
140
140
120
120
120
120
0.25151
Balanced
3652HG
3652JG
3652MG
±2000
±2000
±2000
±5000
:t:tiOOU
±5000
140
14U
140
120
750
750
750
2500
2500
2500
,
Bias
Cur-
rent.
External
Isolation
Power
Temp.
Range
lOOnA
30
No
Ind
DIP
3-29
100nA
30
No
Com
DIP
3-29
100nA
30
No
Com
DIP
3-29
100nA
30
No
Com
DIP
3-29
10nA
15
15
15
15
Yes lSI
Yes'S!
Yes lS!
Yes l6!
Ind
Ind
Ind
Ind
DIP
DIP
DIP
DIP
3-21
3-21
3-21
3-21
Yes
OPTICALLY COUPLED AMPLIFIERS
FET Input
0.25 151
10'2
10'2
10'2
10'2
I.B
1.B
I.B
1.B
±0.2
±0.1
±0.05
±0.2
0.25 151
0.25 151
±0.05
±0.03
±0.02
±0.05
25
10
5
100
lOnA
lOnA
lOnA
0.25151
1012
U.~O~:;l
±0.05
50
50nA
lU ' .:!
::tu.u5
:!5
50nA
±0.05
100
50nA
Yes
Ind
Inu
Ind
DIP
DIP
DIP
3-21
±0.2
15
10
15
"TtlS
0.25 151
10'2
::tU.l
120
I.B
1."
1.8
±0.2
1lU
0.3
0.3
0.3
10'2
10'2
10'2
2.5
2.5
2.5
0.4
0.1
0.07
0.1
O.ot
0.02
10(61
4C61
4161
10nA
10nA
10nA
60
60
60
Yes
Yes
Yes
Ind
Ind
Ind
DIP
DIP
DIP
3-6
3-6
3-6
146161 10a l61
146161 10al61
146161 lOal6J
3-21
3-21
Low Drift
Wide
Bandwidth
IS0100AP
IS0100BP
IS0100CP
1500VAC
150102
1501028
±2121
±2121
±4000
±4000
160
160
120
120
1.0
1.0
10'·
10'4
6
6
0.075
0.025
0.04
0.02
±500
±250
100pA
100pA
70
70
Yes
Yes
Ind
Ind
DIP
DIP
68
68
150106
1501068
±4950
±4950
±8000
±8000
160
160
130
130
1.0
1.0
10'4
10'4
6
6
0.075
0.025
0.04
0.02
±500
±250
100pA
100pA
70
70
Yes
Yes
Ind
Ind
DIP
DIP
68
68
CAPACITOR COUPLED, HERMETICALLY SEALED AMPLIFIERS
Isolation
3500VAC
Isolation
=
=
NOTES: (1) Com
O'C 10 HO'C, Ind
-25'C 10 +85'C. (2) Bipolar. (3) Isolation vollage tesled at 2500V, rms, 60Hz; leakage currenl tesled for 2pA
max a1240V, rms, 60Hz. (4) ±15V at ±15mA isolated power available 10 power exlernal circuitry. (5) At 240v/60Hz. (6) R'N 10k, Gain 100.
=
=
..
ISOLATION POWER SUPPLIES'"
Isolation
Voltage (V)
Continuous
Input
Voltage
(V DC)
Description
Model
Peak
Pulsel
Test
Peak
Single
±15V
Output
700
700U
725
726
1500
2000
2121
4950
4200
5000
4000
8000
10
10
7
7
lB
18
18
18
Dual ±15V
Output
722
4950
8000
5
16
Quad ±15V
Oulpul
710
1000
3100
10
Quad ±8V
Output
724
1000
3000
5
NOTE:
Leakage
Current,
240VAC,
60Hz
(pA)
Isolation
Rated
Max
Current,
Current,"1
Balanced
Sensitivity To
(0)
(pF)
Balanced
Loads On All
Outputs (mA)
'"
Package
Page
1.2
10'0
10'0
10'2
10'2
5
3
9
9
±3-30
±3-30
±15
±15
±60
±60
±40
±40
1.08
1.0B
1.15
1.15
Ind
Ind
Ind
Ind
Module
Module
DIP
DIP
14-35
14-35
82
82
1
10 '0
6
±3-40
±50
1.13
Ind
Module
14-41
18
1
10 '0
B
±9.5
±60
1.08
Ind
Module
14-37
16
1
10'0
6
±3-16
±60
0.63
Ind
Module
14-45
Min
Max
1
1
1.2
Impedance
Loads On All
Outputs (mA)
To Inpul
Voltage
Change (V/v)
Temp
Range
(1) See complete data sheel for full specifications, especially regarding output current capabilities.
(2) Ind
=
-25'C to +85'C.
Models in boldface type are found in this supplement; others are in the Burr-Brown Integrated Circuits Data Book.
xi
ANALOG CIRCUIT FUNCTIONS
MULTIPLIERS/DIVIDERS
You can select accuracy from 0.25% to 2% max from tbis complete
lhie of integrated circuit multipliers. Most provide full fourquadrant multiplication. All are laser-trimmed for accuracy-no
trim pots are needed to meet specified performance. Tbese compact
models bring tbe cost of bigb performance down to acceptable
levels.
MULTIPLIERS/DIVIDERS
Temperature
Coefficient
(%/'C)
Feedthrough
(mV)
Offset
Voltage
("1V)
1% Bandwidth
(kHz)
Temp
Range
Transfer Function
Error at
+25'C,
max(%)
'"
Package
Page
[(X, - X,)(y, - Y,)/l0] + Z,
!
!
!
±2
±1
±0.5
±0.5
0.017
0.008
0.008
0.025
100
30
30
30
50
10
7
7
70
70
70
70
Ind
Ind
Ind
MIL
TO-l00
TO-l00
TO-lOO
TO-l00
4-23
4-23
4-23
4-23
!
!
!
!
0.022
0.022
0.015
0.015
0.008
0.008
0.02
0.02
0.01
0.01
0.3%
0.3%
0.15
0.15%
0.05%
0.05%
0.3%
0.3%
0.15%
0.15%
5
5
2
2
2
2
5
5
2
2
3MHz
3MHz
3MHz
3M Hz
3MHz
3MHz
3M Hz
3MHz
3MHz
3M Hz
Com
Com
Com
Com
Com
Com
MIL
MIL
MIL
MIL
TO-lOO
D!P
TO-l00
DIP
TO-lOO
DIP
TO-l00
DIP
TO-l0o
DIP
4-31
4-31
4-31
4-31
4-31
4-31
4-31
4-31
4-31
4-31
10MH~
Model
MPY100A'
MPY100B
MPY100C
MPY100S
MPY534JH'
MPY534JD
MPY534KH
MPY534KD
MPY534LH
MPY534LD
MPY534SH
MPY534SD
MPY534TH
MPY534TD
•
!
!
!
!
!
±1.0
±1.0
:1;0.5
±0.5
±0.25
±0.25
±1.0
±1.0
±0.5
±0.5
MPV634AM'
MPY634BM
MPY634SM
MPV634KP
MPY634KU
!
!
!
!
!
±1.0
±0.5
±1.0
±2.0
±2.0
0.022
0.015
0.02
0.03
0.03
0.3%
0.15%
0.3%
0.3%
0.3%
5
2
5
25
25
10MHz
10MHz
10MHz
10MHz
Ind
Ind
MIL
Ind
Com
TO-lOO
TO-lOO
TO-lOO
DIP
SOIC
4-38
4-38
4-38
4-38
xxIII
AD632A ,
AD632B
AD632S
AD632T
•
•
1
0.5
1
0.5
0.02
0.01
0.02
0.01
0.3
0.15
0.3
0.15
30
15
30
15
50
50
50
50
Ind
Ind
MIL
MIL
TO-lOO,
DIP
Advance
Information
!
!
.Same as model above.
NOTE:
(1) Com
= O'C to +70'C, Ind = -25'C to +85'C, MIL = -55'C to +125'C.
*Available in 2o-pin ceramic leadless chip carriers.
SPECIAL FUNCTIONS
Tbis group of models offers many different functions tbat are tbe
,quick, easy way to solve a wide variety of analog computational
problems. Most are in integrated circuit packages and are lasertrimmed for excellent accuracy.
SPECIAL FUNCTIONS
Temp
Function
Model
Comments
Description
Rangelll
Package
Page
Ind
DIP
4-111
4302
V (ZlX)m
This function may be used to multiply,
divide, raise to powers. take roots
and form sine and cosine functions.
Plastic package.
LOG100JP
K Log (1,/1,)
Optimized for log ratio of current
inputs. Specified over six decades of
input (1 nA to 1rnA), 55mV total error,
0.25% log conformity.
Com
DIP
4-15
Logarithmic
Amplifier
.4127JG
4127KP
K Log (1,/lR")
A more versatile part which contains
an internal reference and 8: current
inverter. 1% and 0.5% accuracy.
Com
Com
DIP
DIP
4-90
4-90
.JtIc
4341
True rms~to~DC conversion based on
a log~antilog occupational
approach.
Some external trimming required.
Lower cost in plastic package. Pin
compatible with 4340.
Ind
DIP
4-119
4085BM
4085KG
4085SM
These are analog memory circuits
which hold and provide read-out of a
DC voltage equal to peak value of a
complex input waveform.
Digital mode control provides reset
capability and allows selection of peaks
within a desired time interval. May
be used to make peak-to-peak detector.
Com
Ind
MIL
DIP
DIP
DIP
4-82
4-82
4-82
Multifunction
Converter
T
E,.' (t) dt
Peak Detector
NOTE:
(1) Com
= O'C to +70'C, Ind = -25'C to +85'C, MIL = -55'C to +125'C.
Models in boldface type are found in this supplement; others are in the Burr-Brown Integrated Circuits Data Book.
xii
DIVIDERS
The use of a special log/ antilog commited divider design overcomes
the major problem encountered when trying to use a multiplier in a
divider circuit. Outstanding accuracy is maintained even at very
low denominator voltages.
DIVIDERS
Accuracy, max
Transfer
Input
Model
Function
Range
0= 250mV
(%)
DIVtOOHP
DIV100JP
DIV100KP
NID to
NID 10
NID 10
250mV
to
10V
1.0
0.5
0.25
NOTE:
Temperature
Coefficient
Rated
Temp
(%J'C)
0.5%
Bandwidth
(kHz)
Output, min
Range l1 )
Package.
Page
0.2
0.2
0.2
15
15
15
±10V, ±5mA
±10V, ±5mA
±10V, ±5mA
Ind
Ind
Ind
DIP
DIP
DIP
4-7
4-7
4-7
(1) Ind = -25'C to +85'C.
FREQUENCY PRODUCTS
This group of products consists of precision oscillators and active
filters for both signal generation and attenuation. Both fixed
frequency and user-selected frequency units are available.
FREQUENCY PRODUCTS
Function
Oscillator
Universal
Active
Filter
NOTE:
Model
4423
UAF41
UAF21
Description
Comments
Temp Range 'll
Package
Page
Com
DIP
4-123
Ind
Ind
DIP
DIP
4-68
4-60
Frequency range: 0.002Hz 10 20kHz.
Frequency stability: O.Ol%/'C.
Very-low cost in plastic package.
Provides resistor programmable
quadrature outputs (sine and cosine
wave outputs simultaneously available).
Quadrature phase error: ±O.1%.
These filters provide a complex pole
pair. Based on state variable approach,
low-pass, high-pass and bandpass
outputs are available.
Add only resistors to determine pole
location (frequency and Q). Easily
cascaded for complex filter responses.
(1) Com: 0 to +70'C, Ind = -25'C to +85'C.
VOLTAGE REFERENCE
These products are precision voltage references which provide a
+ lOY
output. The output can be adjusted with minimal effect on drift or
stability.
VOLTAGE REFERENCE
Power Supply
Temp
Minimum
Maximum
Output (V)
Output (mA)
Drift (ppm/'C)
(V)
(mA)
Range t1l
Package
Page
REF10KM'
REF10JM
REF10SM
REF10RM
+10.00 ±0.005
+10.00 ±O.OOS
+10.00 ±O.OOS
+10.00 ±O.OOS
10
10
10
10
1
2
3
6
+13.5/35
+13.5/35
+13.5/35
+13.5/35
4.5
4.5
4.5
4.5
Com
Com
MIL
MIL
TO-99
TO-99
TO-99
TO-99
4-46
4-46
4-46
4-46
REF101KM'
REF101JM
REF101SM
REF101RM
+10.00 ±O.OOS
+10.00 ±O.OOS
+10.00 ±O.OOS
+10.00 ±O.OOS
10
10
10
10
1
2
3
6
+13.5/35
+13.5/35
+13.5/35
+13.5/35
4.5
4.S
4.S
4.S
Com
Com
MIL
MIL
TO-1m
TO-99
TO-99
4-52
4-52
4-52
4-52
Model
"'Available in 20-pin ceramic lead less chip carriers.
(1) Com = 0 to +70'C, MIL = -S5 to +125'C.
NOTE:
Xlll
TO-99
DATA CONVERSION AND DATA ACQUISITION
ANALOG-TO-DIGITAL CONVERTERS
Description
Model
Linearity ConverError
sion
(%FSR). Time·(PS)
Screen
Resolution
(Bits)
a
12
±0.012
1.5
30
QI1I
Gain
TampeD
Temp
Input
(ppm/'C)
Rangel2l
Range'~ (V)
Package
Page
MIL,lad
10,20, utB
Hermetic Metal DIP
5-102
Very High Speed
ADC803
Ultra High Speed
ADC600
12
±O,OlS
0,1
30
Com
1.25 B
Module
103
Serial Out
ADC804
a
12
±0.012
17
30
-}
MIL
Com,lnd
5,10,20 utB
Hermelic Ceramic DIP
5-114
Low Cost, MicroADC574
processor Interface ADC674
a
a
a
12
12
±0.012
±0.012
25
15
25
25
}
MIL,
Com,lnd
10,2OutB
10,20utB
Hermetic Ceramic DIP
Hermetic Ceramic DIP
5-80
5-93
12
12
±0.012
±0.012
25
25
30
30
Ind
Ind
5,10,20 U/B
5,10,20U/B
Hermetic Ceramic DIP
Hermetic Ceramic DIP
5-56
12
±0.012
50
35
-55'Cto
+200'C
10,20, U/B
Hermetic Ceramic DIP
5-3
Low Cost
ADC80AG
ADCBOMAH
aM
111·
High Temp
ADC10HT
High Speed,
Low Cost
ADC84
a
12
±O.012
10
30
Cem
5,10,20 U/B
Hermellc Ceramic DIP
95
High Speed,
Wide Temp
ADC85H
ADC87H
a
a
12
12
±O.012
±0.012
10
10
30
30
Ind
MIL
5,10, 20 U/B
5,10,20U/B
Hermetic Ceramic DIP
Hermetic Ceramic DIP
95
High Resolution
ADC71
ADC72
ADC76
a
a
a
16
16
16
±0.003
±0.003
±0.003
50
50
17
15
15
15
Ind,Com
Ind,Com
Ind,Cpm
5,10,20 utB
5,10,20 utB
5,10,20utB
Ceramic DIP
Hermetic Metal DIP
Ceramic DIP
5-13
5-21
5-40
Audio
PCM75
16
0.006%
THO
17
20
Com
5,10,20 U/B
Ceramic DIP
5-122
..
(1) "a" or "OM" ondlcates product available with screening for enhanced reliability.
t'OTES:
-55'C to +125'C.
95
(2) Com = O'C to +70'C, Ind = -25'C to +85'C, MIL =
(3) U = Unipolar, B = Bipolar.
DIGITAL-TO-ANALOG CONVERTERS
Gain
Linearity
Error
(%FSR)
Settling
Time
(PS)
Tempco
(ppm/'C)
Temp
Range t2i
Output
Range l31
Package
Page
5
15
Com
10V,20V U/B
Hermetic Ceramic DIP
141
1
1
8
10
10
10
10
MIL,
MIL,
MIL,
MIL,
Ind
Ind
Ind
Ind
-lmA
10V, 20V U/B
±lmA
10V, 20V U/B
Hermetic
Ceramic DIP,
Plastic DIP,
LCC, Die
}
.
6-98
6-98
6-98
6-98
Model
Screen
Resotutian
(Bits)
Very High
Resolution
DAC729
a
18
±O.00075
High Resolution
DAC700
DAC701
DAC702
DAC703
OM
OM
OM
OM
16
16
16
16
±0.0015
±0.0015
±0.00f5
±0.0015
DAC7D5
DAC706
OM
OM
16
16
±0.OO3
±0.OO3
8
1
15
15
MIL, Com, Ind
MIL, Com, Ind
10V, 20V U/B
±lmA
Hermetic Ceramic DIP
Hermetic Ceramic DIP
6-106
6-106
DAC707
OM
16
±0.OO3
8
15
MIL, Com, Ind
10V, 20V ut8
Hermetic Ceramic DIP,
Plastic DIP
6-106
DAC708
DAC709
OM
OM
16
16
±0.OO3
±0.003
1
8
15
15
MIL, Com, Ind
MIL, Com, Ind
2mA,±lmA
10V, 20V utB
Hermetic Ceramic DIP
Hermetic Ceramic DIP
6-106
6-106
High Resolution
DAC70BH
DAC71
DAC72BH
OM
OM
OM
16
16
16
±0.OO3
±0.003
±0.003
1,10
1,10
1,10
20
20
20
Ind
Com
Ind
Low Cost,
High Resolution
DAC710
DAC711
16·
16
±0.003
±0.003
1
8
50
50
Com
Com
±lmA
10V, 20V utB
} Hermetic Ceramic
DIP, Plastic. DIP
6-116
6-116
Low Cost,
Bus Intertace
DAC811
OM
12
±Q.006
4
20
MIL, Com, Ind
10V, 20V utB
Hermetic Ceramic DIP,
Plastic ·DIP, SOIC, Die
6-130
CMOS
DAC7541
aM
12
±O.012
2
5
MIL, Com, Ind
Multiplying
Hermetic Ceramic DIP,
Plastic DIP, SOIC, Ole
1St
CMOS,
Bus Intertace
DAC7545
DAC8012
aM
aM
12
12
±O.012
±O.012
2
1
5
5
MIL, Com, Ind
MIL, Com, Ind
Multiplying
Multiplying
}Hermellc Csramlc DIP,
Pla.tlc DIP, SOIC, Ole
167
174
Low Cost,
Industry Standard
DAC80
12
±0.012
0.3,3 typ
30
Com
6-64
6-85
6-85
0 111
Description
Bus Intertace,
High Resolution
8
Com,
Com,
Com,
Com,
10V, 2OV, 2mA U/B Hermetic Ceramic DIP
10V, 20V, 2mA utB Hermetic Ceramic DIP
10V, 20V. 2mA utB Hermetic Ceramic DIP
DAC85H
OM
12
±0.012
0.3,3typ
20
Ind
10V, 20V, 2mA utB Hermetic Ceramic DIP,
Plastic DIP, Die
10V, 20V, 2mA U/B Hermetic Ceramic DIP
Ml1Jtary Temp,
DAC87H
Industry Standard
OM
12
±0.012
0.3,3 typ
20
MIL
10V, 2OV, 2mA U/B Hermetic Ceramic DIP
6-20
6-28
6-20
This table continued on next page.
Models in boldface type are found In this supplement; others are In the Burr-Brown Integrated Circuits Dats Book.
xiv
DIGITAL·TO-ANALOG CONVERTERS (CO NT)
Linearity
Error
(%FSR)
Settling
Gain
Time
Screen
Resolution
(Bits)
(ps)
Tempco
(ppmI"C)
Temp
Range'21
Oulput
Range l31
0 111
Package
Page
Ultra High Speed
ECL
DAC63
0
12
±0.012
0.05
30
MIL,lnd
10mA, utB
Ceramic DIP,
Metal Can
6·12
Uitra High Speed
TTL
DAC812
0
12
±0.012
0.065
20
Ind
10mA, utB
Ceramic DIP,
Metal Can
6·138
Model
Description'
"
NOTES: (1) "0" or "OM" indicates product available With screening for enhanced reliability.
-25'C to +85'C. (3) U ; Unipolar, B; Bipolar.
(2) MIL; -55'C to +125'C, Com - O'C to +70'C, Ind-
VOLTAGE·TO·FREOUENCY CONVERTERS
Frequency
Range
Description
Model'"
Low Cost,
Monolithic
VFC32KP'
VFC32BM, (0)
VFC32SM, (0)
Low Cost
Complete
VFC42BP
VFC42SM
VFC52BP
VFC52SM
Precision
Monolithic
VFC62BG'
VFC62BM
VFC62SM
VFC62CG
VFC62CM
(kHz)
}
}
Oto 10
Oto 10
Oto 100
Oto 100
1
}
User·
selected,
I
VFC320BG'
VFC320BM
VFC320SM
VFC320CG
VFC320CM
Synchronized
Monolithic
User·
selected,
500kHz, max
VFC100AG'
VFC100BG
VFC100SG
1MHz max
V,N
Range
(V)
Linearity,
max
(% of FSR)
TempeD,
max
(ppm of FSR/'C)
Temp
Rangel21
Package
Page
User·
selected
±0.01 at 10kHz
±0.05 at 100kHz
±0.2 at 500kHz
75 typ
±100
±150
Com
Ind
MIL
OIP
TO·l00
TO·l00
10·3
10·3
10·3
Oto+l0
Oto+l0
Oto+l0
Oto+l0
±0.01
±0.01
±0.05
±0.05
±100
±100
±150
±150
Ind
MIL
Ind
MIL
DIP
DIP
DIP
DIP
10·11
10·11
10·11
10·11
User·
selected
±0.005 at 10kHz
±0.005 at 10kHz
±0.005 at 10kHz
±0.002 at 10kHz
±0.002 at 10kHz
±50
±50
±50
±20
±20
Ind
Ind
MIL
Ind
Ind
DIP
TO·l00
TO·l00
DIP
TO·l00
10·17
10·17
1()"17
10·17
10·17
User·
selected
±0.005 at 10kHz
±0.005 at 10kHz
±0.005 at 10kHz
±0.002 at 10kHz
±0.002 at 10kHz
±50
±50
±50
±20
±20
Ind
Ind
MIL
Ind
Ind
DIP
TO·l00
TO·l00
DIP
TO·l00
1()"40
10·40
10·40
10·40
10·40
Oto+l0
Oto+l0
Oto+l0
0.025 at 100kHz
0.1 atlMHz
0.025 at 100kHz
±100
±50
±100
Ind
Ind
MIL
DIP
DIP
DIP
10·25
10·25
10·25
I
}
}
User·
selected,
1MHz max
}
Clock
Programmed,
2MHz max
NOTES: (1) "(0)" indicates product also available with screening for increased reliability.
to+125'C .
• Available in 20-pin ceramiC leadless chip carriers.
(2) Com; 0 to +70'C, Ind; -25'C to +85'C, MIL; -55'C
SAMPLE/HOLD AMPLIFIERS
Description
Model
Gain
Offset Charge
QI1I
Error
Error Offset
Screen (%FSR) (mV)
(mV)
Amplifier
Band·
width,
-3dB
(MHz)
Hold
Acqui·
Transient
sition
SetWng Time(ps)
(ps to
(0.01%
lmV)
FSR)
Aper·
ture
Time
(ns)
Aper·
ture
Input
Jitter Range
(ns) (Vp·p)
Package
Page
SHC600
0
0.1
5
lOmax
70
0.D15
0.05
8
0.009
2.5
Ceramic DIP
7·21
High Speed SHC803
With Buffer
0
0.1
3
5 max
16
0.15
0.35
25
0.025
20
Hermetic Metal DIP
7·24
High Speed SHC804
0
0:1
Low Cost
SHC5320
0
SHC85
SHC298
0
Ultra High
Speed
NOTE:
0.01
0.01
3
5 max
16
0.15
0.35
25
0.025
20
Hermetic Metal DIP
7·24
0.5
1 typ
1.5
0.25
1.5
25
0.3
20
Hermetic Ceramic DIP
7·30
2
7
2 max
25 max
0.5
1.5
4.5
10
30
200
1.5
15
20
20
Hermetic Metal DIP
TO·99
7·11
7·15
(1) "Q" indicates product available with screening for enhanced reliability.
xv
MULTIPLEXERS
Description
Protected
Inputs
High Speed
On Resistance,
Channels
Input Range
(V)
max(Q)
Crosstalk (%
of Off Channel)
Settling Time
(to 0.01%)
8 Single
4 Differential
16 Single
8 Differential
±15
±15
±15
±15
1.8k
1.8k
1.8k
1.8k
0.005
0.005
0.005
0.005
5/ls
4/ls
16 Single or 8 Differential
16 Single or 8 Differential
8 Single or 4 Differential
:8 Single or 4 Differential
±15
±15
±15
±15
750
750
750
750
0.004
0.004
0.004
0.004
800ns
BOOns
800ns
800ns
Input Range
(V)
Operating
Temperature
Range
Model
MPC8S
MPC4D
MPC16S
MPC8D
MPC800KG
MPC800SG
MPC801KG
MPC801SG
Package
<;po
4ps
Page
9-3
DIP
DIP
DIP,
DIP
9-3
9-10
9-10
DIP
DIP
DIP
DIP
9-17
9-17
9-24
9-24
MILITARY PRODUCTS
ANALOG-TO-DIGITAL CONVERTERS
Conversion
Resolution
Model
ADC87/883B
ADC87
ADC87U1883B
ADC87U
ADC87V1883B
ADC87V
(Bits)
Linearity,
max (±LSB)
Time,max
(ps)
Gain Drift,
max (±ppm/' C)
12
12
12
12
12
12
1/2
1/2
112
112
1/2
1/2
10
10
10
10
10
10
15
15
15
15
15
15
j~""
Package
MIL
MIL
MIL
MIL
MIL
MIL
Oto+5,
,0 to +10
32-pin
32-pin
32-pin
32-pin
32-pin
32-pin
DIP
DIP
DIP
DIP
DIP
DIP
Page
12-8
12-8
12-8
12-8
12,8
12-8
DIGITAL-TO-ANALOG CONVERTERS
Monotonicity
('C)
Gain Drift,
max
(±ppm/'C)
Settling
Time.
max
Output
Ranges
(V)
±2.5, ±S,
±10,+5,
+10
(Bits)
Linearity,
max
(±LSB)
DAC87-CBI-VlB
DAC87-CBI-V
DAC87U-CBI-VlB
DAC87U-CBI-V
DAC87-CBI-I/B
DAC87-CBI-1
DAC87U-CBI-I/B
DAC87U-CBI-1
12
12
12
12
12
12
12
12
1/2
1/2
112
1/2
1/2
112
1/2
1/2
-55 to +125
-55 to +125
-25 to +85
-25 to +85
-55 to +125
-55 to +125
-25 to +85
-25 to +85
20
20
20
20
20
20
20
20
7/lsec
7pSec
7pSec
7pSec
400nsec
400nsec
400nsec
400nsec
DAC870Vl883B
DAC870V
DAC870U/883B
DAC870U
DAC870VU883B
DAC870VL
DAC870UU883B
DAC870UL
12
12
12
12
12
12
12
12
1/2
1/2
1/2
112
1/2
1/2
1/2
112
-55 to +125
-55 to +125
-25 to +85
-25 to +85
-55 to +125
-55 to +125
-25 to +85
-25 to +85
25
25
20
20
25
25
20
20
7/lsec
7/lsec
7/lsec
7/lsec
7pSec
7pSec
7pSec
7pSec
DAC703VG/883B
DAC703VG
DAC703VU883B
DAC703VL
16
16
16
16
±.OO3%FSR
±.OO3%FSR
±.003% FSR
±.003%FSR
20
20
20
20
8/lsec
8/lsec
8pSec
8paec
Resolution
Model
NOTE:
-55
-55
-55
-55
to +125'"
to +125'"
to +125 111
to +125111
Operating
Temperature
Range
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
Ot02mA,
±1mA
}~
±5,±10,
Oto+5,
Oto+10
,
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
±10
±10
±10
±10
Package
24-pin
24-pin
24-pin
24-pin
24-pln
24-pin
24-pin
24-pin
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
Page
12-24
12-24
12-24
12-24
12-24
12-24
12-24
12-24
carrier
12-48
12-48
12-48
12-48
12,48
12-48
12-48
12-48
24-pln DIP
24-pln DIP
} 28-term.
LCC
191
191
191
191
24-pln
DIP
ceramic
28-term.
leadless
chip
(1) Monotonicity to 14-bit accuracy.
VOLTAGE-TO-FREQUENCY CONVERTERS
Model
VFC32WM/883B
VFC32WM
VFC32VM/883B
VFC32VM
VFC32UM/883B
VFC32UM
at 10kHz (% FSR)
Full Scale Drift,
max (ppm FSR/' C)
Operating Temp-
V,N Range (V)
FoUT Range,
max (kHz)
erature Range
Package
Page
±10
±10
±10
±10
±10
±10
200
200
200
200
200
200
±0.006
±0.006
±0.01
±0.01
±O.Ol
±0.01
±100 at 10kHz
±100 at 10kHz
-400, +150 at 200kHz
-400, +150 at 200kHz
±150 at 10kHz
±150 at 10kHz
MIL
MIL
MIL
MIL
MIL
MIL
TO-IOO
TO-IOO
TO-IOO
TO-IOO
TO-IOO
TO-l00
12-135
12-135
12-135
12-135
12-135
12-135
Linearity. max
Models in boldface type are found in this supplement; others are in the Burr-Brown Integrated Circuits Data Book.
XVl
MULTIPLIERS
Model
Accuracy
Accuracy
at 25'C,
max (±%)
at 125'C,
max (±%)
4213WM/883B
4213WM
4213VM/883B
4213VM
4213UM/883B
4213UM
NOTES:
112
112
1
1
1
1
Output
Offset,
max (±mV)
Output,
Feedthrough,
max (±mV)
50
50
100
100
100
100
25
25
30
50
50
50
4
4
4
4
2111
2111
(V,mA)
Operating
Temperature
Range
Package
Paga
±10,±5
±10,±5
±10,±5
±10, ±5
±10, ±5
±10, ±5
MIL
MIL
MIL'
MIL
MIL
MIL
TO-IOO
TO-IOO
TO-IOO
TO-l00
TO-l00
TO-l00
12-166
12-166
12-166
12-166
12-166
12-166
min
(1) At +85'C.
OPERATIONAL AMPLIFIERS
Description
Wideband
General
Purpose
Opera-
Slew
Olfsot Vollago
8andwidlh
Rate.
Drift,max
(±pVl'C)
Current,
Unity Gain,
min
max (nA)
min (MHz)
(Vips)
Is
±0.01%
(ns)
OPA600VM/B638
OPA600VM
OPA600UM/BB38
OPA600UM
2
2
5
5
20
20
BO
BO
lOOpA
-IOOpA
-100pA
-100pA
400
400
400
400
125
125
150
150
3500R/B638
3500U/BB38
5
5
20
±30
±30
1
I
0.6
0.6
-
internal
20121
2
±25
0.25
0.5
0.9
0.9
0.9
0.9
0.9
0.9
Modol
} 5000, '"
A =1000
Bipolar
Precision
Bipolar
3510VM/BB38
0.12
Low Drift.
Low Bias
OPA105WM/BB38
OPA105WM
OPA11J5VM/ee38
OPA105VM
OPA105UM/BB38
OPAI05UM
0.250
0.250
2
2
-lpA
-lpA
0.250
5
-l~.A.
0.250
0.250
0.250
5
15121
15121
-lpA
-lpA
-lpA
I
1
1
1
1
1
OPA106WM/B638
OPA106WM
OPAI06VM/8838
OPA106VM
OPAI06UM/8838
OPAI06UM
0.250
0.250
0.250
0.250
0.250
0.250
5
5
10
10
20121
20121
lOOlA
-100lA
-I501A
-I501A
-300lA
-3001A
1
1
1
1
1
1
1.2
1.2
1.2
1.2
1.2
1.2
OPAllWM/8838
OPA111UM
0.500
0.500
10
10
±2pA
±2pA
2
2
1
1
OPA50WM/8838
OPA50WM
OPAS01UM/8638
OPA501UM
5
5
10
10
40
40
65
65
±20
±20
±40
±40
1
1
1
1
1.35
1.35
1,35
1.35
OPA8780VM/8838
OPA8780VM
OPA8780UM/8838
OPA8780UM
10
10
10
10
30
30
50
50
-0.05
-0.05
-0.05
-0.05
5
5
5
5
15
15
15
15
Ultra Low
81as
Current
Low Drift,
Low Bias,
Low Noise
Power
Output,
Bias
AI 25'C,
max (±mV)
NOTES: (1) Gain-bandwidth product.
(V,mA)
ling
Temp.
Range
±IO, ±200
±10, ±200
±10, ±200
±10, ±200
MIL
MIL
MIL
MIL
} 16-pin
DIP
12-94
12-94
12-94
12-94
internal
±10,±10
±10,±10
MIL
MIL
TO-99
TO-99
12-147
12-147
-
internal
±10,±10
MIL
TO-99
12-15B
-
internal
internal
±10,±10
±10,±10
±10,±10
±10,±10
±10,±10
±10,±10
MIL
MIL
MIL
MIL
MIL
TO-99
TO-99
TO-99
TO-99
TO-99
TO-99
12-74
12-74
12-74
12-74
12-74
12-74
±10,±5
±10,±5
±10,±5
±10,±5
±10,±5
±10,±5
MIL
MIL
MIL
MIL
MIL
MIL
TO-99
TO-99
TO-99
TO-99
TO-99
TO-99
12-84
12-84
12-84
12-84
12-84
12-84
Internal
±10,±5
±10,±5
MIL
MIL
TO-99
TO-99
210
210
Internal
Internal
Intemal
Internal
±26,±10A
±26,±10A
±20,±10A
±20,±10A
MIL
MIL
MIL
MIL
TO-3
TO-3
TO-3
TO-3
222
222
internal
internal
internal
internal
±30, ±60
±30, ±60
±30, ±60
±30, ±60
MIL
MIL
MIL
MIL
TO-3
TO-3
TO-3
TO-3
12-1110
12-1110
12-1110
12-1110
Campensatian
external
external
external
external
;nto:-rnal
internal
internal
intarlJa!
internal
internal
internal
internal
internal
internal
Internal
-
-
-
min
MIL
Package
Page
222
222
(2) -25'C to +85'C.
INSTRUMENTATION AMPLIFIERS
Input Parameters
Description
Vory High
Accuracy
NOTES:
Nonlinearity
G=I00
max
CMR,
DC 10 60Hz,
G =10, min,
lkQ UnbaJ.
(d8)
Offsol
Voltage
vs Temp,
G =1000,
max (PV/'C)
Dynamic
Response,
G=I00,
±3d88W
(kHz)
Temp
Range
Package
Page
22
22
22
22
0.007
0.007
0,007
0,007
96
96
96
96
1,75
1,75
1.75
1.75
25
25
25
25
MIL
MIL
MIL
MIL
DIP
DIP
TO-l00
TO-l00
·200
200
200
200
22
0.007
0.007
0.007
0.007
0.007
0.007
0.007
0.007
0.007
0.007
0.007
0.007
96
96
96
96
96
96
96
96
96
96
96
96
0.5
0.5
1.0
1.0
3.0
3.0
0.5
0.5
1.0
1.0
3.0
3.0
25
25
25
25
25
25
25
25
25
25
25
25
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
DIP
DIP
DIP
DIP
DIP
DIP
12-61
12-61
12-61
12-61
12-61
12-61
12-61
12-61
12-61
12-61
12-61
12-61
Gain
Range"l
Gain
Accuracy,
G=100,
AI 25'C,
max (%FS)
Gain
Drift,
G=100,
Iyp
(ppm/'C)
INA101VG/8838
INA101VG
INA101VM/8838
INA101VM
HOOD
HOOD
1-1000
1-1000
0.10
0.10
0,10
0,10
iNA258WG/8638
INA258WG
INA258VG/8838
INA258VG
INA258UG/8638
INA258UG
INA258WLl8838
INA258WL
INA258VLl8838
INA258VL
INA258ULl8638
INA258UL
1-1000
HOOO
HOOO
1-1000
HOOO
HOOD
HooO
HOOO
HOOD
HOOD
HOOD
HOOO
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
Model
22
22
22
22
22
22
22
22
22
22
22
20terminal
eadless
chip
carrier
(1) Set WIth external resistor.
Models in boldla.e type are found in this supplement; others are in the Burr-Brown Integrated Circuit~ Data Book,
XVll
MODULAR POWER SUPPLIES
DC/DC CONVERTERS
Description
Model
Input (VDC)
Output
Isolation (VDC)
Leakage Current, max (PA)
Package
Page
Unregulated
Unregulated
Unregulated
Unregulated
Unregulated
Regulated
Regulated
Unregulated
PWRlxx
PWR2xx
PWR3xx
PWR4xx
PWR5xx
PWR6xx
PWR7xx
PWR8xx
5t048
5to 48
5 to 48
5 to 48
5 to 48
5 to 48
·51048
5to 48
450mW
1.5W
2W, dual channel
3W
4W
2W
5W
5W, triple output
1000
1000
1000
1000
750
1000
1000
1000
5
5
5
5
15
20
25
5
Module
Module
Module
Module
Module
Module
Module
Module
14-9
14-11
14-13
14-15
14-17
14-19
237
14-25
Unregulated
Unregulated
Unregulated
Unregulated
PWR70
PWR71
PWR72
PWR74
10 to18
IOta 18
5t022
IOta 20
±15VDC, ±15mA
±15VDC, ±25mA
±15VDC, ±100mA
±15VDC, ±25mA
2000
1000
1000
1500
2
3
3
2
Module
Module
Module
Module
14-27
14-29
14-31
14-33
Unregulated
PWR1017
101018
3
Module
241
PWR5038
PWR5104
PWR5105
4.75105.25
4.75105.25
4.75105.25
±15VDC, ±25mA,
4 channels
2,75W,lrlple outpul
±12VDC, ±370mA
±15VDC, ±300mA
1000
Regulated
Regulated
Regulated
500
750
750
5
15
15
Module
Module
Module
245
247
247
NOTES: (1) Models 700 and 700M have separate internal input and output shields. Models 700U and 700UM have no internal shields. Models 700M and
700UM are similar to models 700 and 700U, but in addition, they are 100% screened to patient-connected circuit requirements for the leakage current (par.
27.5) and withstand voltage (par. 31.11) of UL544. Additional per·unit charge for 700M or 700UM. (2) Model 710 provides four channels (sets) of isolated
outputs.
RELIABILITY
All Burr-Brown PWR Series DC; DC converters are manufactured
using stringent in-process controls and quality inspections. The
customer may also choose one of two additional levels of screening
Standard Manufacturing Process
to meet specific requirements. The advanced reliability program is
designed to reduce infant mortality, system rework, field failures,
and equipment downtime.
IG-Levell Screening
I
Incoming Material Inspection
Standard Manufacturing Process
Per MIL-S-19500
I
I
IT -Level II Screeni ng
I
I
.
Standard Manufacturing Process
I
Burn-in, MIL-STD-883,
method 1015, 160 hours, T. = +125°C
Stabilization Bake, MIL-STD-883,
method 1008, 24 hours, T. = +125°C
I
I
I
OA Lot Acceptance Testing, AQL = 0.5
Temperature Cycling, MIL-STD-883,
method 1010, Condition B (-55°C to +125°C)
Component Attachment
100% Visual Inspection
I
I
100% Electrical Test
Final Electrical Test
I
I
Burn-in, MIL-STD-883,
method 1015, 160 hours, T. = +125°C
Seal
T
I
100% Final Electrical Test
Final Electrical Test
I
I
OA Lot Acceptance Testing, AOL = 0.25
External Visual
l
QA Lot Acceptance Testing, AQL = 1.0
xviii
BURR-BROWN-A WORLDWIDE LEADER IN MICROCIRCUITS
AND MICROPROCESSOR-BASED SYSTEMS AND SUBSYSTEMS
Burr-Brown first introduced VMEbus products in 1983
and now manufactures a comprehensive line of specialized products for the industrial instrumentation, control,
and automation markets. Utilizing Burr-Brown's high
performance data conversion products (e.g. ADC803),
Burr-Brown is able to offer products which set new
performance standards in the VMEbus market. When
these are operated with the digital signal processing
boards, a wide range of applications can be addressed.
With over ten years experience in the design and manufacture of board-level products, you can rely on the
market leaders for VMEbus data acquisition boards.
•
•
•
•
o
THE SYSTEMS APPROACH
TOP-QUALITY VMEbus PRODUCTS
FROM BURR-BROWN
In addition to the full Q.C. inspection of incoming components, the boards are subjected to a comprehensive temperature-cycled burn-in (8 cycles between -20°C and +50°C).
Short addressing available if required (64 bytes)
150ns response to CPU interrogation
7-level interrupt priority selection
Full interrupt vector selection-8 lines (256 options)
Double Eurocard format, 160mm X 233mm
SUPPORT DOCUMENTATION
Each VMEbus board is fully supported with a comprehensive operating manual. In addition to detailed set-up
and operating instructions, the manual includes schematics and assembly language software written for the
68000 processor.
A systems approach has been taken in the design of the
bus interface. This ensures software compatibility between
the boards as well as giving the system designer a wide
range of VMEbus features .
• Configuration A24, D16, DTB slave
• Address block selectable within 16M bytes memory
space
Exhaustive tests before and after burn-in ensure that any
problems are identified before the product leaves the
factory.
VMEbus ANALOG 110 BOARDS
Output
Input
Product
MPV901
MPV901A
MPV901P
MPV904
MPV905
MPV906
ACX906
MPV907
MPV911
MPV950S
MPV950D
MPV952
MPV954
MPV940
ACX945A
ACX945B
ACX945C
ACX946
Resolution
(Bits)
Number of
Channels
Sampling
Rate (kHz)
12
12
12
32SEl16DIF
32SEl16DIF
32SEl16DIF
11
11
11
-
-
-
12
84SEl32DIF
33
-
-
-
12
16
12
12
12
32SEl16DIF
8SE
16SE
8SE +8DIF
8SE
33
45
330
330
330
-
-
-
-
Resolution
(Bits)
Number of
Channels
Sampling
Rate (kHz)
-12
-2
200
2
16
8
200
285Hz
285Hz
-
-
-
-
-
-
12
12
12
-
-
:
-
-
-
12
-
8
858
-
-
-
-
-
-
12
16
4
4
500
83
12
12
12
16SEl8DIF
16SEl8DIF
16SEl8DIF
33
33
33
-
-
-
-
-
xix
-
Description
General purpose, .analog Input.
As MPV901. with analog output.
As MPV901A. with software-programmable gain.
Low-cost analog output (voltage output).
Current output.
High-density analog input. optically isolated. optional
digital 110.
Digital 110 module for MPV9061907. 32 110 lines.
Low~cost analog input, optional digital 110.
High resolution analog input. with on-board data buffer.
High speed analog input.
As MPV950S. with 8 user-configurable input amplifiers.
High speed analog input. with on-board data buffer.
High speed analog output. with on-board data buffer.
Intelligent I/O controller-6800 CPU. optically isolated
I/O expansion Interface.
Analog Input module for MPV940.
As ACX945A. with 12-bit analog output.
As ACX945A. with 16-bit analog output.
Digital 110 module for MPV940, 32 programmable 110
lines.
VMEbus DIGITAL 110
Description
Product
Number of Channels
Type
MPV902
MPV910
MPV910NS
MPV910LV
MPV930
32
32
32
32
48
Relay contact output
Optical isolated input
Optical isolated input
Optical Isolated input
TTL level I/O
28VDC at O.5A, lOW max output rating.
As MPV910 without power supply.
As MPV910NS for low voltage Inputs.
Lines programmable as input or output in groups of eight.
VMEbus DIGITAL SIGNAL PROCESSING BOARDS
Description
Product
SPV100
FFT100'"
FILlOO'"
COR100'"
ASM310V
MON100V
APS100V'"
SPV120
ACX120A
ACX120B
ASM320V
MON120V
APSI20V'"
MPV960
ACX960
MPV990
NOTE:
A VMEbus board for general purpose DSP, based on the Texas Instruments TMS32010. Swinging buffer data memory for pipelining of
data inpuVoutputand processing. Program ROM and RAM for user programming.
Fast Fourier Transform firmware for the SPV100. FFT-l 64 points, -3 256 points, -4 512 point, -51024 pOint transform.
Digital filter firmware for the SPV100. From 5 to 89 taps.
Correlation firmware for the SPV100. Auto-and cross-correlation.
TMS32010 cross-assembler. Runs under VERSAdos.
Monitor/debugger software for SPV100. Runs under VERSAdos.
DSP applications software library for SPV100. Includes vector operations, correlation, trigonom~tric functions, interpolation and
decimation, filtering, windowing and FFTs. Routines are called from FORTRAN running under VERSAdos.
Second generation DSP board based on TMS32020. Two RS-232 ports, auxiliary input and output ports, DMA controller for faster I/O
concurrent with processing. Program RAM, bipolar ROM and EPROM. Supplied with EPROM-based debug monitor.
Add-on program RAM module for SPV120-16k X 16 bits.
Add-on program RAM module for SPV120-80k X 16 bits.
TMS32020 cross-assembler for SPVI20. Runs under VERSAdos.
Monitor/debugger software for SPVI20. Runs under VERSAdos.
DSP applications software library for SPV120. Includes vector operations. correlation, trigonometric functions, interpolation and
decimation, filtering, windowing and FFTs. All routines are callable from FORTRAN running under VERSAdos.
Analog input and DSP. Four channels of simultaneously sampled analog input (at 100kHz sampling rate) plus TMS32010 processor.
Applications in digital filtering, signal averaging, etc.
Add-on program RAM/ROM module for MPV960. Includes debug monitor and basic data acquisition routines.
Anti-aliasing filter board. Four independent programmable filters, with user-configurable front ends. Ideal for use with MPV960.
(1) This software is also available as source code. To order, add S suffix to product code; e.g., APS100VS.
SOFTWARE DRIVERS FOR. VMEbus BOARDS
Product
Description
PSOA
PSOA-P
P,SOB
PSOB-P
VDR100
VDR120
pSOS drivers for MPV901, MPV904, MPV905, MPV950, MPV952. Distributed In UNIX,format 5-114" floppy disks.
As PSOA, but distributed in MS-DOS format disks.
pSOS drivers for MPV960, SPV100. Distributed in UNIX format 5-114" floppy disks.
As PSOB, but distributed in MS-DOS format disks.
VERSAdos driver for SPV100.
VERSAdos driver·for SPVI20.
xx
SURFACE MOUNT MICROCIRCUITS
Burr-Brown is the first manufacturer to offer high performance
microcircuits in a wide variety of surface mount packages. These
packages permit denser layouts on one or both sides of a PC
board, often saving 50% or more of the space normally required
for these analog circuits. Many of these miniature devices also fit
inside transducer cavities and may be used on modules or even
hybrid circuits. Packages currently available are:
• SOle-Plastic small-outline package, gull-wing leads on 1.27mm
centers. Example: SOIC-8 has 8 leads.
• Lee-Ceramic lead less chip carrier, terminals on 1.27mm
centers. Example: LCC-20 has 20 terminals.
SURFACE MOUNT DEVICES
Device Type
Analog Multipliers/Dividers
Description
Low Cost
Precision
Current Transmitters/Converters
Two-Wire, 4-20mA
Voltage-ta-Current Converters
Model
Package
Dimensions (mm)
Product Data Sheet
MPY100L
4213L
LCC-20
LCC-20
9.0 X 9.0
9.0 X 9.0
LCC Short Form
LCC Short Form
XTR101L
XTR101U
XTRll0L
XTRll0U
LCC-20
SOIC-16
LCC-20
SOIC-16
9.0 X 9.0
10.4 X 7.5
9.0 X9.0
10.4 X 7.5
LCC Short Form
PDS-734
LCC Short Form
PDS-731
Digital-ta-Analog Converters
16-Bit. Monolithic
16-Bit, Monolithic, Military
12-Bit. /JP-Compatible
12-Bit. Monolithic
12-Bit. MIL Temp
12-Bit. Military
12-Bit, CMOS
16-Bit. Digital Audio
DAC700-703BL
DAC703L
DAC811U
DAC850L
DAC851L
DAC870L
DAC7541AU
PCM55
LCC-28
LCC-28
LCC-28
LCC-28
LCC-28
LCC-28
SOIC-18
SOIC-24
11.4X 11.4
11.4 X 11.4
11.4 X 11.4
11.4 X 11.4
11.4 X 11.4
11.4 X 11.4
11.6X7.5
15.8 X9.0
Instrumentation Amplifiers
t"recision, jyionoliihic
li.JAi01L
INA101U
INA102L
INA105L
INA105U
INAll0L
INAll0U
INA258L
LCC-:iG
SOIC-16
LCC-20
LCC-20
SOIC-8
LCC-20
SOIC-16
LCC-20
S,U/\ ;.0
Lee Si",v,", ::0...-.-,
10.4 X 7.5
9.0 X 9.0
9.0X9.0
4.9 X3.9
9.0X 9.0
10.4X 7.5
8.9 X 8.9
PDS-730
LCC Short Form
LCC Short Form
PDS-693
LCC Short Form
PDS-733
PDS-501
Electrometer Grade
High Speed, Quad
Precision, Dual
AD515L
OPA27137L
OPA27137U
OPA111L
OPA121L
OPA121U
OPA128L
OPA404L
OPA2111L
LCC-20
LCC-20
SOIC-8
LCC-20
LCC-20
SOIC-8
LCC-20
LCC-20
LCC-20
9.0 X 9.0
9.0 X9.0
4.9 X3.9
9.0X9.0
9.0 X 9.0
4.9X 4.9.
9.0 X 9.0
9.0 X 9.0
9.0 X 9.0
LCC Short
LCC Short
PDS-691
LCC Short
LCC Short
PDS-692
LCC Short
LCC Short
LCC Short
Precision Analog Multipliers
Low Cost, Monolithic
Wide Bandwidth
MPY534L
MPY634L
LCC-20
LCC-20
9.0X 9.0
9.0X 9.0
LCC Short Form
LCC Short Form
Precision Voltage References
Ultra-Stable
Low Drift
REF10L
REF101L
LCC-20
LCC-20
9.0 X 9.0
9.0 X 9.0
LCC Short Form
LCC Short Form
Voltage-to-Frequencyand
Low Cost. Monolithic
Frequency-to-Voltage Conv,erters
Precision, Monolithic
Synchronized
Precision, Monolithic
VFC32L
VFC62L
VFC100L
VFC320L
LCC-20
LCC-20
LCC-20
LCC-20
9.0X
9.0X
9.0 X
9.0 X
LCC
LCC
LCC
LCC
Data Acquisition System
12-Bit, 16-Channel
SDM862/863L
LCC-68
24.3 X 24.3
Low Power
Unity Gain, Differential
Fast, FET Input
Precision, Military
Operational Amplifiers
Electrometer
Ultra-Low NOise
Precision, Dire'®
Low Cost, Dire'
Oi/e'® Burr-Brown Corp.
xxi
9.0
9.0
9.0
9.0
PDS-494
PDS-751
PDS-503
PDS-453
.PDS-453
PDS-511
PDS-639
PDS-619
Short
Short
Short
Short
PDS-686
Form
Form
Form
Form
Form
Form
Form
Form
Form
Form
Form
HIGH PERFORMANCE CHIPS
HIGH PERFORMANCE DICE BACKED BY
BURR-BROWN'S TRADITION OF QUALITY
Many of Burr-Brown's high-performance monolithic products are
available in die form, including D/ A converters, precision operational and instrumentation amplifiers, current transmitters, voltage/frequency converters, and many more.
those used in our
All Burr-Brown dice products are the same
high quality, high performance monolithic and hybrid devices and
are proven in demanding applications throughout the world. The
dice are manufactured and tested at our Tucson Microtechnology
facility using the most advanced equipment and methods available,
assuring total control of quality and reliability for every product.
as
The state-of-the-art performance achieved by these precIsIOn
monolithic products reflects Burr-Brown's unmatched technical
capabilities in low noise processing, high stability nichrome thinfilm resistors, active laser trimming, dielectric isolation, and
patented circuit design.
At Burr-Brown concern for quality is a fundamental part of wafer
processing. Dice are 100% visually inspected according to MILSTD-883, Method 2010, Condition B. All wafers are 100% probe
tested to specified electrical test limits.
Our newest products are described below. See also our current
Integrated Circuits Data Book for additional product information.
HIGH PERFORMANCE CHIPS
Product Data Sheet
Model
Die Size
(mils)
INA105AD
INA110AD
83X63
139X 89
Precision Analog Multiplier
MPV534AD
100X92
VO----~---{11
-Vee
OPA404 S:implified Circuit
(Each Amplifier)
Oi/'e'@ Burr-Brown Corp .. BIFET® National Semiconductor Corp.
Inlernalional Airporllnduslrial Park - P.O. Box 11400 - Tucson. Arizona B5734 - Tel. 1602) 746-1111 - Twx: 910-952-1111 'C.able: BBRCORP - Telex: 66·6491
PDS-677 A (Abbreviated)
SPECIFICATIONS
ELECTRICAL
At Vee = ±15VDC and TA = +2S·C unless otherwise noted.
OPA404AG, KP
PARAMETER
CONDITIONS
MIN
TYP
OPA404BG
MAX
MIN
TYP
OPA404SG
MAX
MIN
TYP
MAX
UNITS
INPUT
'NOISE'1J
Voltage: 10' =
10
10
10 ~
=
=
I.
I.
Current: I.
10
10Hz
100Hz
1kHz
10kHz
10Hz to 10kHz
O.IHz to 10Hz
O.IHz to 10Hz
O.IHz to 20kHz
32
19
15
12
1.4
0.95
12
0.6
=
=
=
=
OFFSET VOLTAGE
Input" Oflset Voltage
KP
Average Drift
KP
'Supply Reiection
KP
VCM= OVDC
±lmV
±2.5mV
100Hz, RL = 2kQ
±260
±750
±3
±5
100
100
10
10
125
BIAS CURRENT
Input Bias Current
KP
VCM =OVDC
±1
~1
±8
±12
OFFSET CURRENT
Input Offset Current
KP'
VCM= OVDC
0.5
0.5
8
12
KP
Channel Separation
T,.,= TMIN to TMAX
±Vcc = 12V to 18V
80
76
IMPEDANCE
Differential
Common-Mode
VOLTAGE RANGE
Common-Mode Input Range
Common-Mode R~jection
KP
86
100
200
Open-Loop Voltage Gain
±10.5
88
84
+13,-11
100
100
92
RL;:o,2kQ
88
100
92
Gain = 100
20V p-p, RL = 2kQ
Vo = ±10V, RL = 2kQ
Gain = -I, RL = 2kQ
CL = loopF, 10V slep
4
6.4
570
35
0.6
1.5
5
24
28
RATED OUTPUT
Voltage Output
Current Output
Output Resislance
Load Capacitance Stability
Short Circuit Current
RL = 2kn
Vo=±10VDC
1MHz, open loop
Gain=+1
±11.5
±5
±10
I
+13.2, -13.8
±10
80
1000
±18
±20
POWER SUPPLY
Rated Voitage
Voltage Range,
Derated Performance
Current, Quiescent
±15
±5
10=OmADC
9
±18
10
TEMPERATURE RANGE
Specification
KP
Operating
KP
Storage
8 Junction-Ambient
KP
· ··
·
··
··
·
·· ··
··
· ·
·
· ·
·
·
· ·
V'N=±10VDC
FREQUENCY RESPONSE
Gain Bandwidth
Full Power Response
Slew Rate
Settling Time: 0.1%
0.01%
·
·
··
10"111
10" 113
OPEN-LOOP GAIN, DC
Ambient temp.
Ambient temp.
Ambient temp.
~25
+85
+70
+125
+85
;r150
0
-55
-25
-65
100
120
·Specification same as PPA404AG.
NOTES:. (1) Noise testing available-inquire.
2
··
··
···
·
·
·
·
·
·
±750
50
±4
4
··
···
···
· ·
·
· ·
· ·
·
· ·
.. ·
··
·· ··
·
·
·
··
· ·
·· ·
·
· ·
-55
nVlJHz
nVlJHz
nVlJHz
nVlJHz
pV,rms
"V, p-p
lA, p-p
fAlJHz
"V
pV
"V/·C
"VI·C
dB
dB
"VN
"VN
dB
pA
pA
pA
pA
Q II pF
Q II pF
V
dB
dB
·
··
···
··
··
· ·
·
· ··
+125
·
· · · ·
dB
MHz
kHz
VIpS
pS
pS
V
mA
n
pF
mA
VDC
VDC
mA
·C
·C
.q
·C
·C
·CIW
·CIW
ELECTRICAL (FULL T.EMPERATURE RANGE SPECIFICATIONS)
At Vee = ±15VDC and TA;: T"'IH 10 TMAX unless otherwise noted.
OPA404AG, KP
PARAMETER
CONDITIONS
MIN
Ambient temp.
-25
TYP
OPA404BG
MAX
TEMPERATURE RANGE
Specification Range
KP
+85
+70
a
MIN
TYP
,
OPA404SG
MAX
MIN
,
-55
TYP
MAX
UNITS
+125
'C
'C
INPUT
OFFSET VOLTAGE
Input Offset Voltage
KP
Average Drift
KP
Supply Rejection
BIAS CURRENT
Input Bias Current
OFFSET CURRENT
Input Offset Current
VOLTAGE RANGE
Common-Mode Input Range
Common-Mode Rejection
KP
VeM"·OVDC
75
VeM = OVDC
,
±450
±1
±3
±5
96
t6
2mV
±3.5
178
,
100
93
22
316
pVN
±32
±200
,
±100
±500
±5nA
pA
100
,
50
260
2.5nA
pA
VeM = OVDC
17
±1.5rnV
±550
,
80
,
±2.5mV
,
,
70
IN
mV
pVl'C
pv/oC
dB
±10.2
82
80
+12.7.-10.6
99
99
86
,
,
±10
80
1+12.6,-10.5
V," = ±10VDC
88
V
dB
dB
R,''''2kCl
82
94
86
,
BO
88
dB
R,=2kCl
Vo = ±10VDC
Vo=OVDC
±11.5
±5
±5
+12.9.-13.8
±9
±12
±11
±30
+12.7. -t3.8
±8
±10
,
V
mA
mA
9.3
10.5
9.4
11
rnA
Ut't:N-LUUt' \iAIN, Uf.,;
Open-Loop Voltage Gain
RATED OUTPUT
Voltage Output
Current Output
Short Circuit Current
.,, ..,
,
,
±8
POWER SUPPLY
Current, Quiescent
10= OmADC
,
,
'Specification same as OPA404AG.
ABSOLUTE MAXIMUM RATINGS
ORDERING INFORMATION
Supply •....••......•.•..••...•••..•••••••••••••••.•.••••..•. ±18VDC
Internal Power Dissipation''' ••••••••••••••..••••••.•..•.••.... l000rnW
Differentiallnput'Voltage'" .......... : ....................... ±36VDC
Input Voltage Range'" .•.••••••••••••••....•.•••...••••...••• ±18VDC
Storage Temperature Range ..••••...• P = -40/+85'C. G = -65/+150'C
Operating Temperature Range .••••... P = -25/+85'C. G = -55/+125'C
Lead Temperature (soldering, 10 seconds) .••....•••••••••••••• +300'C
Output Short Circuit Duration'" .••••.•..•.••...•...••..••• Continuous
Junction Temperature ........................................ +175'C
OPA464 X X
Basic model number------=r---'
Performance grade - - - ' - - - - - - - - - - ' K = O°C to +70·C
A, B = -2S·C to +8SoC
= -SS·C to +12SoC
S
Packagecode---------------'
G = 14-pin ceramic DIP
P = 14-pin'plastic DIP
T
NOTES:
(1) Packages must be derated based on BJc= 30°CIW orBJA = 120°CIW.
(2) For supply voltages less than ±18VDC the absolute maximum input
voltage Is equal to: 18V > V," > -Vee - 8V. See Figure 2.
(3) Short circuit may be to power supply common only. Rating applies to
+25'C ambient. Observe dissipation limit and TJ •
NOTE:
Refer to complete data
sheet PDS-677 for complete typical curves and
applications information.
CONNECTION DIAGRAM
Top View
3
MECHANICAL
"P" Package
"G" Package
~[~]~
LA~
(.25mm) R at MMC at seating plane.
~+J
~-4.jG~fa~~~nq
.012
.008
.120
.240
.300 BASIC
K
Pin material and plating composition
.070
.025
J
L
M
N
conform to Method 2003 (solderability)
of MIL-STD-883 (except paragraph 3.2).
.710
.170
.021
.045
.060
.100 BASIC
G
H
I-L'::I·Y
MAX
.Q15
P
MILLIMETERS
MIN
MAX
17.02
18.03
1.65
4.32
0.38
0.53
1.14
1.52
2.54 BASIC
1.78
0.64
0.20
0.30
6.10
3.05
INCHES
MIN
.670
.065
e
.060
(25mm) R at MMC at seatln9 plane
INCHES
MIN
MAX
DIM
B, B
A
A,
B
8,
-::4..J.
.700
.685
.230
.200
MILLIMETERS
MIN
MAX
17.78
20.32
17.40
19.94
5.85
7.38
5.09
6.36
.800
.785
.290
.250
r- ~ 1-;'~2-t-';.~;O~0;-5-t--,;.~",~;--t--;;-~.,",~~;-r--;;-~.~~:;-I
1
.__ ~__-1
L
JI1MAnn~
L~-IG~I-o
i
- i I N I JlM
.
J_
H;;-t-,;.·~;;;1~;;-:-'iBA",S",:I~~::nt--;,~~~;-BTA-"S,,;:C~::.-I
t-';J'-+-.';;;00~8-t--';;.0~'5;-1--';;0:;;.20;;-r-0;;':.3;;;-18
r.~'-I~.0",73;;;00-;:0OBA;;;·~;;;~~H-1.";~~'<;63~B"A;;;~;;~~:-j
Seating Plane
Pin material and plating composition
M
0°
15°
0°
15°
conform to Method 2003 (solderability).
N
.010
.030
0.25
0.76
of MIL-STD-883 (except paragraph 3.2). r .P;-t-':.0"'2;-5-t--';.0;;50;;-t--;;-0.~64;-t-o".';;'27;-j
10'
1.52
0.23
-
P
7.62 BASIC
.100
.009
NOTE: Leads in true position within .010"
At
Pin numbers shown for reference only.
Numbers may not be marked on package.
DIM
A
C
D
F
14-pin plastic DIP
~
NOTE: Leads in true position within .010"
TYPICAL PERFORMANCE CURVES
... 25° C. Vee:;:= ±15VDC unless otherwise noted
T...
INPUT CURRENT NOISE SPECTRAL DENSiTY
100
If'>
~
INPUT VOLTAGE NOISE SPECTRAL DENSITY
If'>
10
:>
.s
~
i
100
~
0
Z
V
1:
~
"
.!!!
en
';
10
I
1
I
01
100
10
1M
lOOk
.
V
~
100
95
..V
V
CMR
V-
~ 100
8~
g:+
u!
t--
If>
,......
105
a:
I
g
-........
··50
Rs
~
OPA404
a
+
25
-25
• 50
·75
·100
...it.
ReSistor
,1 :
n~ls~ only
1ill lUi '
~
I
10k
1M
100k
Source ReSistance (0)
lk
100
·125
I..!'
J.I;o'
o
>
10nA
10
illilill
S
100
~
';
10
~
....
25
·25
01
Offset Current
1,
:
0.1
50
'"
Iii
f-
~
j
';
()
l
.......
1:
~
l
11'
Bias Current
i
~
'"
100M
10 I
1nA
~
Iii
10M
BIAS AND OFFSET CURRENT
vs INPUT COMMON MODE VOLTAGE
BIAS AND OFFSET CURRENT
vs TEMPERATURE
10nA
~
1M
Resistor
Temperature iOC)
()
100k
io'"
_on
~ 10
1
-75
1:
10k
(Hz)
'
z
90
\
1k
1k
:;;
()
100
I
TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY
AT 1kHz vs SOURCE RESISTANCE
PSR
D-
I
Freque~cy
110
..,c
I
10
POWER SUPPLY REJECTION AND COMMON-MODE
REJECTION vs TEMPERATURE
1ii
E
a:
en
,
I I
lk
10k
Frequency (Hz)
1:
,..
~
I i
0
>
()
I
,
0
z
, I
i
I
,
·5D
Ambient Temperature
. 75
·100
0.1
·12;
00 1
I I
·15
-10
--5
+5
Common-Mode Voltage (V)
(0 ,C)
4
0.01
BURR-BROWN®
OPA445
IElElI
ADVANCE INFORMATION
Subject to Change
High Voltage FET-Input
OPERATIONAL AMPLIFIER
FEATURES
~ tA!!!!~ !'!!'.M~!!
S!!!,!,!..Y
APPLICATIONS
!!~~~~: ±1OI]!~
±5!!1]
III
• HIGH SLEW RATE: 10VlpS
• LOW INPUT BIAS CURRENT: 50pA max
IJ STANDARD-PINOUT TO-99 PACKAGE
•
•
•
•
mlT ~QIJ!PMF.tH
HIGH VOLTAGE REGULATORS
POWER AMPLIFIERS
DATA ACQUISITION
SIGNAL CONDITIONING
DESCRIPTION
The OPA445 is a monolithic operational amplifier
capable of operation from power supplies up to
±50V and output currents of l5mA. It is useful in a
wide variety of applications requiring high output
voltage or large common-mode voltage swings.
The OPA445's high slew rate provides wide powerbandwidth response, which is often required for
high voltage applications. FET input circuitry allows
the use of high impedance feedback networks, thus
minimizing their output loading effects. Laser trimming of the input circuitry yields low input offset
voltage and drift.
The OPA445 is unity-gain stable and requires no
external compensation components. It is available
in both industrial (-25°C to +85°C) and military
(-55°C to +125°C) temperature ranges.
Inlernational Alrporllnduslrial Park· P.O. Box 11400 . Tucson. Arizona B5734 • Tel. (6021 746·1111 . Twx: 910·952·1111 . Cable: BBRCORP • Telex: 66·6491
PDS·754
5
SPECIFICATIONS
ELECTRICAL
PARAMETER
OFFSET VOLTAGE
Input Ollset Voltage
Average Drift
Supply Rejection
VOM=OV
= TMIN to TMAX
Vs = ±10V to ±50V
0.5
1.0
TA
BIAS CURRENT
Input Bia. Current
Over Temperature
VOM =OV
OFFSET CURRENT
Input Ollset Current
Over Temperature
VOM =OV
80
1.0
10
110
20
100
4
50
10
5
IMPEDANCE
10"111
10" 113
Differential
CommonwMode
VOLTAGE RANGE
V,. =±30V,
Over temp.
.
±35
BO
. Vo =±35V,
RL=5kQ
Vo= ±200mV
Av=+l
ZL = 5kQ II 50pF
5
95
10
80
30
RL=5kQ
Vo= ±2BV
DC, open loop
±35
±15
Over temp.
lo=OmA
±10
220
±26
±40
3.B
'Specification .ame as OPA445BM.
ABSOLUTE MAXIMUM RATINGS
ORDERING INFORMATION
T
OPA445 ( )
Basic model number "'-_ _ _ _ _ _ _ _..:==r-=
Power Supply, , .. , , ... , , ....•....... , . . . . . . • . . . . . • . . . . • . . .. ±55V
Internal Power Dissipation ................................ 680mW
Differential Input Voltage.. .. .. .. . . .. . .. .. .. . . .. . .. . .. .. .. .. ±BOV
Input Voltage Range ••.•..••.•.. , ..•.••..••...•••.•.•• I±Vsl - 3V
Storage Temperature Range: M ....•...••...•.... -65'C to +150'C
P ................... -40'C to +B5'C
Operating Temperature Range: M ...•••...•....•. -55'C to +125'C
P ................. -40'C to +B5'C
Lead Temperature (soldering, 10 seconds) .•......••.....•. +300'C
Output Short-Circuit to Ground (TA = +25·C) .......... Continuous
Junction Temperature. .. .. . .. . .. . . .. .. . .. • .. .. . . .. . .. . ... +175'C
( )
Performance grade (blank indicates A grade) - - - - - - ' A: -25'C to +B5'C
B: -25'C to +B5'C
S: -55'C to +125'C
Package code _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...
~
M: B-pin TO-99
P: B-pin plastic DIP.
6
CONNECTION DIAGRAM
Top View
MECHANICAL
TO-99 Package
TO-99
NC
f:3
NOTE: Leads in true position
within .010" (.25mm) Rat MMC
at seating plane.
2Jr1
G-
-;J
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
IIIII~
Seating
Plane ---Il.-D
-Vs
Ni
L
Case is connected to -Vs
,
~
.~
T
M
N G'
' + •
"8
',,5,
(~J
INCHES
MIN
MAX
.335
.370
.305
.335
,165
.185
.021
.016
.010
.040
.040
.010
.200 BASIC
.028
.034
.045
.029
.500
.110
.160
45° BASIC
.095
.105
MILLIMETERS
MIN
MAX
8.51
9.40
8.51
7.75
4.19
4.70
0.53
0.41
0.25
1.02
0.25
1.02
5.08 BASIC
0.71
0.86
0.74
1.14
12.7
2.79
4.06
45° BASIC
2.41
2.67
TYPICAL PERFORMANCE CURVES '
T. : +25°C, Vs: ±15VDC unless otherwise noted.
GAIN BANDWIDTH AND SLEW RATE
VS TEMPERATURE
GAIN BANDWIDTH AND SLEW RATE
VS SUPPLY VOLTAGE
2.6
14
2.4
........
N
I
~ 2.2
r-.....
'6
'i 2.0
.
"0
c:
GBW
1.8
c:
'OJ
Cl
~
-- "
.<:
CD
....
1.6
1.4
-75
-50
-25
o
'" --
---
SR
t--..
"
+50
--..
"1\
~
..........
+75
+100
1.6
10
+125
20
30
1
-
S/R---
5
+25
_ _ GBW
40
50
Supply Voltage (±Vee)
Ambient Temperature (OC)
INPUT 'BIAS CURRENT
VS TEMPERATURE
POWER SUPPLY REJECTION
VS FREQUENCY
120
110
10nA
iil
100
:!:!. 90
c:
.2 80
..........
~ 100pA
.;;;
g
70
0
a:
60
...... "-..... +VCC
""- .....
i'-
50
Vee
lnA
E
"
r:
jjj
·ago
10pA
lpA
(f)
.1pA
.01pA
-60 -45 -30 -15
10
Temperature
"".....
"- ...... ".......
30
20
10
o
0 +15 +30 +45 +60 +75 +90 +105+120
-""'- ......
40
1'0..
100
lk
10k
lOOk
Frequency (Hz)
7
1M
.........
.....
10M
,100M
OPEN-LOOP
FREQUENCY RESPONSE
OPEN-LOOP GAIN AND SUPPLY CURRENT
VS SUPPLY VOLTAGE
120
140
;30
120
110
100 ~
90
80
70
60
50
40 f30
20
10
iil
~
<=
'0;
el
"
g
'"
l!!
o
10
45
j
I!!
~
90
e
:l"1li
100
1k
10k
-
;(
3.5
<=
'0;
1:rs~
....
Gain
-
e-"'" el
= l!!'"" . ~
:c
100
(f)
-.
~
iil 110
~
4.0
~
"
U
'"
'""
0
>
'"
Q.
90
. 10
'180
10M
1M
20
30
2.5
50
40
Supply Voltage (±Vcc)
Frequency (Hz)
SUPPLY CURRENT VS TEMPERATURE
OPEN-LOOP GAIN VS TEMPERATURE
120
;(
§.
E
4
• i-oo-
r-- r--.
~
"
U
'"
C.
g.
a;:
r-.. ~
3
~
<=
r-...... ~
el
"
'"
~
100
0
>
(f)
-75
110
'0;
r-..
-50
-25
o
90
+25
+50
+75
+100
-75
+125
-50
-25
o
i'- to......
+25
+50
"'"
+75
Ambient Temperature ('C)
Ambient Temperature (OC)
"
+100
+125'
MAXIMUM OUTPUT VOLTAGE SWING
VS FREQUENCY
INPUT VOLTAGE NOISE SPECTRAL DENSITY
100
90
80
~:>
c:
r- ~
6.
;::.
.s
"'"
l!!
5: 10
'0
z
g
"'"
l!!
:;
>
0
60
40
~
ll-
0
"
1
10
100
1k
10k
-"
20
o
100k
1k
Frequency (Hz)
10k
Frequency (Hz)
8
E
~
3.0 C.
.<=
100k
§.
100k
~
1M
OPA541
BURR-BROWN®
IElElI
ADVANCE INFORMATION
Subject 10 Change
High Power Monolithic
OPERATIONAL AMPLIFIER
FEATURES
APPLICATIONS
POWER SUPPLIES TO ±40V
o OUTPUT CURRENT TO lOA PEAK
II
\\I
o riWGiii\iviiviAiii.t [;uiiiitNT i.iiviiT
o INDUSTRY-STANDARD PINOUT
f.)
MOTOR ORIVER
o SERVO AMPLIFIER
~
" " ... nll"n ,."nITATln ...
i)
11'",nnU I:A'" uu Iun
o AUDIO AMPLIFIER
FET INPUT
1/1
PROGRAMMABLE POWER SUPPLY
DESCRIPTION
The OPAS41 is a monolithic power amplifier capable
of operation from power supplies up to ±40V and
continuous output currents up to SA. Internal current
limit circuitry can be user-programmed with a single
external resistor, protecting the amplifier and load
from fault conditions. The OPAS41 is fabricated
using a proprietary bipolar / FET process.
Pinout is compatible with popular hybrid power
amplifiers such as the OPASll, OPASl2 arid the
3S73. The OPAS41 uses a single current-limit resisto~
to set both the positive and negative current limits.
Applications currently using hybrid power amplifiers
requiring two current-limit resistors need not be
modified.
The OPAS41 is available in an industry-standard 8pin TO-3 hermetic package. The case is isolated
from all circuitry, thus allowing it to be mounted
directly to a heat sink without special insulators
which degrade thermal performance.
+Ys
-In
t---<>---,.-o
VOUT, •
Rcc
(ext.)
-Ys
International Airport Industrial Park· P.O. Box 11400 • Tucson. Arizona B5734 • Tei. (6021 746·1111 • Twx: 910·952·1111 • Cable: BBRCORP • Telex: 66·6491
PDS-737
9
SPECIFICATIONS
ELECTRICAL
At Tc = +2S·C and Vs = ±3SVDC uniess otherwise. noted.
PARAMETER
I
L
CONDITIONS
OPA541AM
I
TYP
MAXJ
±2
±20
±2.5
±20
±10
±40
±10
±60
4
±10
50
±1
±30
5
MIN
OPA541BM/SM
MIN
TYP
MAX
±0.1
±15
±1
±30
UNITS
INPUT OFFSET VOLTAGE
Vos
vs Temperature
vs Supply Voltage
Specified temperature range
Vs = ±10V to ±VMA'
vs Power
INPUT BIAS CURRENT
I.
;
vs Supply Voltage
INPUT OFFSET CURRENT
los
Specified temperature range
INPUT CHARACTERISTICS
Common-Mode Voltage Range
CommonwMode Rejection
Input Capacitance
Input Impedance, DC
Specified temperature range
VCM = (1,±Vsl-6V)
±(IVsl-6)
95
±(lVsl-3)
113
5
1
RL =6rl
90
97
1.6
±(IVsl-5.5)
±(IVsl-4)
±(I Vsl-4)
9
±(IVsl-4.5)
±(IVsl-3.6)
±(IVsl-3.2)
10
S
45
10
55
2
··
GAIN CHARACTERISTICS
Open Loop Gain at 10Hz
Gain-Bandwidth Product
·
··
··
··
OUTPUT
Voltage Swing
10
= SA, Continuous
10=2A
10= 0.5A
Current, Peak
AC PERFORMANCE
Slew Rate
Power Bandwidth
Settling Time to 0,1%
Capacitive Load
Phase Margin
RL
= Srl, Vo = 20Vrms
2V Step
Specifieq temperature range. G
=1
3,3
Specified temperature range, G > 10
Specified temperature range, RL = 80:
SOA
40
POWER SUPPLY
Power Supply Voltage, ±Vs
Specified temperature range
±10
Current, Quiescent
±30
20
±35
25
1,25
1.4
30
1.5
1.9
·
THERMAL RESISTANCE
BJc, (junction to case)
BJC
BJA, (junction to ambient)
AC output f > 60Hz
DC output
No heat sink
TEMPERATURE RANGE
TeASE
-25
AM,8M
SM
+S5
·
-55
'Specification same as OPA541AM
10
··
··
·
···
·
··
··
··
··
·
·
··
··
··
pA
pAN
pA
nA
V
dB'
pF
Trl
dB
MHz
V
V
V
A
VIps
··
·
·
·· ··
·
±35
mV
pVl·C
pVN
pVIW
±40
·
+125
kHz
IlS
nF
Degrees
V
mA
·C/W
·CIW
·CIW
·C
·C
MECHANICAL
Seating Plane
UTt~
E
~
DIM
A
B
C
D
E
F
G
H
J
K
NOTE: Leads in true position
within 0.010" (0.2Smm) A at MMC
at seating plane.
o----L-
Pin numbers shown for reference
only. Numbers may not be marked
on package.
Q
Supply Voltage, +Vs to -Vs ......................... 90V
Output Current ................................ see SOA
Power Dissipation, Internal'" .................... .i25W
Input Voltage: Differential .......................... ±Vs
Common-mode ..................... ±Vs
Temperature: Pin solder, 10s ................... +300·C
Junction lll ........................ +1S0·C
Temperature Range:
Storage ............................. -6SoC to +1S0·C
Operating (case) .................. -SS·C to +12S·C
.161
.980
1,020
NC
+In
~CL
-In
NC
ORDERING INFORMATION
----r--
.151
R
40° BASIC
12.7 BASIC
30,12 BASIC
15.06 BASIC
10.16
12.70
3.84
4.09
24.89
25.91
/' Top View
NOTE: (1) Long term operation at the maximum junction temperature will result in reduced product life.
Derate internal power,dissipation to achieve high MTTF.
OPA541
a
MILLIMETERS
MIN
MAX
38.35
39.37
19.56
18.92
6.10
7.37
0.97
1.07
2.03
2.67
CONNECTION DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Basic Model Number
INCHES
MIN
MAX
1.510
1.550
.745
.770
.240
.290
.038
.042
.080
.105
40° BASIC
.500 BASIC
1.1S6BASIC
.593 BASIC
.400
.500
T
()
M
Performance Grade Code
A: -25°C to +85°C
B: .-25°C to +85°C
S: -55°C to +125°C
Package Code - - - - - - - - - - - '
M = TO-3
11
TYPICAL PERFORMANCE CURVES
TA = +25°C. Vs = ±35VDC unless otherwise noted.
INPUT BIAS CURRENT
VS TEMPERATURE
OPEN-LOOP GAIN AND
PHASE VS FREQUENCY
100
.110
«
.s
-'
10
-'
-'
~
0
.
..,
0.1
:;
70
60
(!)
50
40
"
C>
J!!
0
-'
-'
0.Q1
iil
<=
·iii
:!1.
-'
0
E
I""-
90
80
<=
iIi
1111
100
~
>
-25
~
I"iIIIIJ
Z, =
~
+75
+50
+100
1
+125
1.2
5
1.1
.10
100
1k
10k
100k
1M
~
I
10M
;:
±i.
~ ~~I-IVol
3
6
10
+V. +.I-V.I (V)
lou, (A)
VOLTAGE NOISE DENSITY
VS FREQUENCY
TOTAL HARMONIC DISTORTION
VS FREQUENCY
1k
,."
~
~
I"""'"
I
E
0
z
(+V;;':~ ~
,, .--,..,,-.
,.~
~
1.0
0;
10
,
'/
I...
1.0
~
~
Z'
.~
"
Z,=2kD
OUTPUT VOLTAGE SWING
VS OUTPUT CURRENT
.2
0
III
IJI
Frequency (Hz)
6
~
-135
-180
~~1=3.~~
0
-10
+25
-90
3.3~:~~
I""-
30
20
1.3
~
Z, = 2kD
IIIIL.
Gain
NORMALIZED QUIESCENT CURRENT VS
TOTAL POWER SUPPLY VOLTAGE
.~
45
.1
Temperature (0C)
"0
o
1111
Phase
'iIII
10
-'
-'
0.001
1111
100
z
-Po
5W
0
ioo"
r
z
f-
"
Po
50W
~
0.01
C>
~
".
III
0.1
+
~
·0
,,-
Po-100mW
~
·0
J!!
0
>
10
0.001
1
10
100
1k
10k
100k
10
100
1k
Frequency (Hz)
Frequency
12
10k
100k
CURRENT LIMIT VS
RESISTANCE LIMIT
COMMON-MODE REJECTION
VS FREQUENCV
110
~
a:
a:
::;:
......
r"-o~
100
iii
,
10
120
~
90
SO
+IOUT
"'~
()
70
lOUT
~~
1,0
::fti
1\
I"
60
t\
50
10
100
1k
10k
100k
0,1
0,1
0,01
1M
1,0
~
10
Frequency (Hz)
CURRENT LIMIT VS RESISTANCE
LIMIT VS TEMPERATURE
nVNAMIC RESPONSE
10
f - - fo-
,1,1',
~ l,
r--
t~
Tc
0,1
0,01
lOUT
-.; ~~,
T10UT
+S5°C :
~ --25~C
0,1
1111
10
G
~
1, C,
~
4,7nF
Rce (0)
emitter turn-on voltage. The value of the current limit
resistor is approximately:
INSTALLATION
INSTRUCTIONS
RCL
0.809
= -II - I - 0.OS7
LIM
POWER SUPPLIES
The current limit value decreases with increasing temperature due to the temperature coefficient of a baseemitter junction voltage. Similarly, the current limit
value increases at low temperatures. Current limit versus
resistor value and temperature effects are shown in the
Typical Performance Curves.
The OPAS4l is specified for operation from power
supplies up to ±40V. It can also be operated from
unbalanced or single power supply as long as the total
power supply voltage does not exceed 80V. The power
supplies should be bypassed with low series impedance
capacitors such as ceramic or tantalum. These should be
located as near as practical to the amplifier's power
supply pins. Good power amplifier circuit layout is, in
general, like good high frequency layout. Consider the
path of large power supply and output currents. Avoid
routing these connections near low-level input circuitry
to avoid waveform distortion and oscillations.
The adjustable current limit can be set to provide
protection from short circuits. The safe short-circuit
current depends on power supply voltage. See the discussion on, Safe Operating Area to determine the proper
current limit value,
Since the full load current flows through Rd. it must be
selected for sufficient power dissipation. For a SA
current limit, the dissipation of RCL will be 3.2SW for SA
continuous currents. Sinusoidal output will create dissipation according to the rms load current. Thus for the
same SA current limit, AC peaks would be limited to SA,
but the rms current would be 3.SA and a resistor with a
lower power rating could be used. Some applications
CURRENT LIMIT
Internal current limit circuitry is controlled by a single
external resistor, RCL. Output load current Hows through
this external resistor. The current limit is activated when
the voltage across this resistor is approximately a base-
13
(such as voice amplification) are assured of signals with
much lower duty cycles, allowing a current resistor with
a lower power rating. Wire-wound resistors may be used
for RcL • Some wire-wound resistors, however, have
excessive inductance and may cause loop-stability problems. Be sure to evaluate circuit performance with
resistor' type planned for production to assure proper
circuit operation.
'
'""
HEAT SINKING
Power amplifiers are rated by case temperature, not
ambient temperature. as with signal op amps. The maximum allowable power dissipation is a function of the
case temperature as shown on the power derating curve.
All points on the power derating slope .produce a
maximum internal junction temperature of +150°C. Sufficient heat sinking must be provided to keep the case
temperature within safe bounds for the maximum ambient temperature and power dissipation. The thermal
resistance of the heat sink required may be calculated by:
OHS
=
TCASE -
elimination significantly improves thermal performance.
See Burr-Brown Application Note AN-83 for further
details on heat sinking.
SAFE OPERATING AREA
The safe operating area (SOA) plot provides comprehensive information on the power handling abilities of
the OPA541. It shows the allowable output current as a
, function of the voltage across the conducting output
transistor (see Figure I). This voltage is equal to the
power supply voltage minus the output voltage. For
example, as the amplifier output swings near the positive
power supply voltage, the voltage across the output
transistor decreases and the device can safely provide
large output currents demanded by the load.
Short circuit protection requires evaluation of SOA.
When the amplifier output is shorted to ground, the full
power supply voltage is impressed across the conducting
output transistor.' The current limit must be set to a
value which is safe for the power supply voltage used.
For instance, with Vs ±3~V, a short to gro\lnd would
force 35V across the conducting power transistor. A
current limit of 1.8A would be safe.
TAMBIENT
P,,(max)
Commercially available heat sinks often specify their
thermal resistance. These ratings are often suspect, however, since they depend greatly on the mounting environment and air flow conditions. Actual thermal performance
should be verified by measurement of case temperature
under the required load and environmental conditions.
Reactive, or EMF-generating, loads such as DC motors
can present difficult SOA requirements. With a purely
reactive load, output voltage and load current are 90°
out of phase. Thus, peak output current occurs when the
output voltage is zero and the voltage across the conducting transistor is equal to the full ,power supply
voltage. See Burr-Brown Application Note AN-123 for
further information on evaluating SOA.
No insulating hardware is required when using the TO-3
package. Since mica and other similar insulators typically
add approximately 0.7°CjW thermal resistance, their
SAFE OPERATING AREA
10
..........
_
I"'l1o.
{
I"!I
'C~
"<>s.C'
~
""c9s' ~
b~
.,,,l,;l~
{iii!..
"'"
"-,
~ ~ 1\
1.0
\
o.1
10
IV. - VoUTI (V)
FIGURE I. Safe Operating Area.
14
100
BURR-BROWN®
OPA600
T' ......··~n
IElElI
l'~~-":;
. J I i 11/1 j
Fast-Settling Wideband
OPERATIONAL AMPLIFIER
FEATURES
APPLICATIONS
• GAIN BANDWIDTH PRODUCT: 5GHz
• FAST SETTLING: SOns to ±D.J%
IDDns 10 ±D.01%
• -25°C 10 +S5°C AND
-55°C 10 +125°C TEMPERATURE RANGES
• ±10V OUTPUT: 200mA
•
•
•
•
•
•
DESCRIPTION
the user to optimize the settling time for various
gains and load conditions.
The OPA600 is useful in a broad range of video,
high speed test circuits and ECM applications. It is
particularly well suited to operate as a voltage
controlled oscillator (VCO) driver. It makes an
excellent digital-to-analog converter output amplifier.
It is a workhorse in test equipment where fast pulses,
large signals, and 50n drive are important. It is a
good choice for sample/ holds, integrators, fast
waveform generators, and multiplexers.
The OPA600 is specified over the industrial temperature range (OPA600BM, CM) and military temperature range (OPA600SM, TM). The OPA600 is
housed in a welded, hermetic metal package.
The OPA600 is a wide band operational amplifier
specifically designed for fast settling to ±O.OI%
accuracy. It is stable, easy to use; has good phase
margin with minimum overshoot, and it has excellent
DC performance. It utilizes an FET input stage to
give low input bias current. Its DC stability over
temperature is outstanding. The slew rate exceeds
400V/ J.ls. All of this combines to form an outstanding
amplifier for large and small signals.
High accuracy with fast settling time is achieved by
using a high open-loop gain which provides the
accuracy at high frequencies. The thermally balanced
design maintains this accuracy without droop or
thermal tail. External frequency compensation allows
Offset Offset
Frequency
Compensation
FAST VCO
HIGH·SPEED D/A CONVERTER OUTPUT AMPLIFIER
VIDEO AMPLIFIER
HIGH·SPEED ADC DRIVER
lOW·DlSTORTION AMPLIFIER
TRANSMISSION LINE BUFFER
. Frequency
qompensation +Vcc
Frequency
Common Compensation
leaSe)p
14
11
500
3r-----------~----------~
-Input
International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734 • Tel. (6021746·1111 • Twx: 911).952·1111 • Cable: BBRCORP • Telax: 66·6491
PDS-672
15
SPECIFICATIONS
ELECTRICAL
~t
Vee;;:: ±15VDC and TA;;:: +25°C·unless otherwise specified.
OPA600CM, TM'"
PARAMETER
CONDITIONS
MIN
TYP
MAX
OUTPUT
Voltage
RL; 2kO
RL = 500 121
Current
Current Pulse
Resistance
Short-Circuit Current
RL ;;:: 500 121
RL:::;50n C31
±10
±9
±180
±180
Open loop DC
To COMMON only,
tMAX;;::
1st• 1
±200
±200
75
250
300
100
80
70
125
105
95
DYNAMIC RESPONSE
Settling Time"': to ±0.01% (±1mV)
to ±0.1% (±10mV)
to ±1%(±100mV)
.0. VOUT = 10V
AVouT ;10V
AVouT = 10V
Gain-Bandwidth Product (open-loop)
Ce - OpF. G ;
Ce = OpF. G ;
Ce = OpF. G ;
Co; OpF. G ;
Ce; OpF. G =
Bandwidth (-3dB small signal)'61
G=+1VN
G=-1VN
G=-10VN
G ;-100VN
G = -1000VN
Full Power Bandwidth
VOUT; ±5V. G; -1VN. Ce; 3.3pF. RL; 1000
Slew Rate
VOUT = ±5V. G ; -1000VN. Ce ; OpF; RL = 1000
VOUT ; ±5V. G = -1VN'4I
Phase Margin
1VN
10VN
100VN
1000VN
10.000VlV
150
500
1.5
5
10
125
90
95
20
6
16
400
G; -1VN. Ce = 3.3pF
500
440
40
GAIN
Open-Loop Voltage Gain
I ; DC. RL = 2kO. T. ; +25'C
86
T.; +25'C
T. = -25'C to +85'C
T. ; -55'C to +125'C
±1
Offset Voltage Drift
T. = -25'C to +85'C
T. ; -55'C to +125'C
Bias Current
T.= +25'C
T. ; -25'C to +125'C
, -20
Offset Current
T.= +25'C
T. = -55'C to +125'C
20
20
Power Supply Rejection Ratio
Common-Made Voltage Range
Common-Mode Rejection Ratio
Impedance
Voltage Noise
Voc = ±15V. ±1V
±4
±5
±6
±20
±20
-20
200
-10
60
VeM = -5V to +5V
Differential and Common-Mode
10kHz Bandwidth
-100
-100
500
+7
80
10"112
20
POWER SUPPLY
- Rated (Voc)
Operating Range
Quiescent Current
±15
±9
±30
±16
±38
TEMPERATURE RANGE (Ambient)'"
Operating: BM. CM
SM.TM
-25
-55
-65
Storage
8,e. (junction to case)
8CA • (case to ambient
+85
+125
+150
30
35
TYP
·· •
·· ·
··
·
··
···
··
····
··
· ···
MAX
±2
··
···
·· ·
··
· ··
···
··
UNITS
V
V
mA
mA
·
··
·
0
mA
ns
ns
ns
MHz
MHz
GHz
GHz
GHz
MHz
MHz
MHz
MHz
MHz
MHz
VI,.,s
VI,.,s
Degrees
· ·
94
INPUT
Offset Voltage'"
· OPA600BM, SM
MIN
dB
±5
±10
±15
mV
mV
mV
±80
±100
,.,VI'C
,.,VI'C
··
··
··
··
·
pA
nA
pA
nA
,.,VN
V
dB
OllpF
nV/VHz
VDC
VDC
mA
'C
'C
'C
'CIW
'CIW
-Specilication same as OPA600CM. TM.
NOTES: (1) BM. CM grades: -25'C to +85'C. SM. TM grades: -55'C to +125'C. (2) Pin 9 connected to +Vci:. pin 7 connecte'd to -Vee. Observe power disSipation
ratings. (3) Pin 9 and pin 7 open. Single pulse t = 100ns. Observe power dissipation ratings. (4) Pin 9 and pin 7 open. See section on Current Boost. (5) G =
-1VN. Optimum settling time and slew rate achieved byiridividually compensating each device. Reterta saction on Compensation. (6) Frequency compensation as
discussed in section on Compensation. (7) Adjustable to zero. (8) Heat Sink (optional): IERC LBOCI-72CB with 2 each DCV-1B Clamps.
16
CONNECTION DIAGRAM
MECHANICAL
r-Ai
TO
DHf
t
f-~ 0
•
Offset Null
(optional)
JO':'ooo
8
I
-Input
'6
o
('I
o·
J
0
I)
0
3
9
0
DenotesPin 1
Y-r
+K
H
1~~Hul .
-L-l j u U U D D D
-G-
[
"l
ID
I--L--l
Output
Sealing Plane
-lo
DIM
A·
!U
8
8
C
0
G
H
K
L
R
INCHES
MIN
MAX
.963
.980
.760
.805
.175
.190
.014
.022
.100 BASIC
.135
.155
.230
.270
.600 BASIC
,115
.095
MILLIMETERS
MIN . MAX
24.89
19.30 20.45
4.45
4.83
0.56
0.36
2.54 BASIC
3.43
3.94
5.94
6.86
15.24 BASIC
2.41
2.92
+Input
24.46
NOTES: (1) Refer to Figure 4 for recommended frequency compensation .
(2) Connect pin 9 to pin 12 and connect pin 710 pin 6 for maximum output
current. See Application Information for further information. (3) Bypass
each power supply lead as close as possible to the amplifier pins. A lpF
C813 tantalum capacitor is recommended. (4) There is no internal
connection. An external connection may be made. (5) It is recommended
that the amplifier be mounted with the case in contact with a ground plane
for good thermal transfer and optimum AC performance.
~~OT~:::;:
1. Leads in true position within 0.010"
(0.25mm) R at MMC at seating plane.
2. Pin numbers shown for reference only.
ORDERING INFORMATION
OPA600 B
T
Performance Grade _ _ _ _ _ _ _ _ _ _,..-_...J
B. C = -25·C 10 +85·C
S. T = -55·C 10 +125°C
Package _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...l
1
ABSOLUTE MAXIMUM RATINGS"I
Q
Supply Voltage. +Vccto -vee ................................ ±17V
Power Dissipation, At TCASE +125 oC(21 ••••••••••••••••••••••• -1.6W
Input Voltage: Differential ••....••....•••..•..••.••......•••. ±Vee
Common-Mode .••••.......•......... : ........ ±Vee
Output Short Circuit Duration to Common. . . . . • • • • . • • • . . . .. <5sec
Temperature: Pin (soldering. 20sec) ...•....•..........•... +3OO·C
Junction l1l, TJ ••••••••••••••••••••••••••••••• +175°C
Temperature Range: Storage .................... -65·C to +150·C
Operating (case). . • . . . . . • • .. -55·C 10 +125·C
M=Metal DIP
Hi'Reliabilily Q-Screening _ _ _ _ _ _ _ _ _ _ _ _--l
(oplional)
NOTES: (1) Stresses above those listed under "Absolute Max.mum
Ratings" may cause permanent damage to the device. Exposure to
absolute maximum conditions for extended periods may affect device
reliability. (2) Long term operation at the maximum junction temperature
will result in reduced product life. Derate internal power dissipation to
achieve high MTTF.
TYPICAL PERFORMANCE CURVES
ITypical at TA
= +25°C and ±Vcc = 15VDC, unless otherwise specified).
BODE PLOT
COMPENSATION AND SLEW RATE VS GAIN
700
10
600
g
1\
1\
,
10-'10-
SLEW RATE
500~
*
)(
400 a:
~
'"
i'",
300
COMPENSATION
~
10
Closed-loop Gain IVNI = 1 + RF/RIN
Frequency 1Hz I,
17
200
100
SETTLING TIME
VS OUTPUT VOLTAGE CHANGE
SETTLING TIME
VS
GAIN
300r---.;;.;;.;..;-F-..;......;,.
__
.;,.;.
____...
200·r---~T-~~~~~~~~
:J.V=20V
1. 2
S(;TTLING TIME ANn
SLEW RATE VS TEMPERATURE
G=1VN
25o1t----+----+--::II~_I
_1~1~--4---~--~--~
1. 1
~ 2001----+---2IfE::....-~1:....I ~
=
.,c
~ 150t----+~IO-_:Jr#f"-,~O::;
~ ts,IO.OIJ,
~
0
'"
'"
~ l°OE=;;;;.~"r~.",-"'--t----;~
~ .....
£
c
0 ..
1 - - -...
10.....--~·1~00~--..1....
000
Closed-loop Gain VN, = 1 + RF/RIN
30 OUTPUT VOLTAGE VS OUTPUT CURRENT
501~--~~~+---+--~
o. 9
0 ....--~5!---:o!10~-...,1i\.5--~20
Output Voltage Change ,V,
875 -50 -25
0._
1.2
OPEN·LOOP GAIN AND QUIESCENT
CURRENT VS TEMPERATURE
-
ts~
~
I""'IIiiiS~
""""
o +25 +50 +75 +100+125
Temperature 1°C,
GAIN-BANDWIDTH
1.4
G=·10VN
25
f
~ 15
Co
"5
010
5
o
1.2
1. 1
>
Cii 20
10
10
-
Vee
Vee
50
--
15
±12
100
15~
200
250
Output Current rnA
0.9
300
0·~75
.. '
-50
~
~
11
~
.~1.0
AoL~ f-- j
~
-25
0 +25 +~ +75 +100 +125
Temperature 1°C,
INSTALLATION AND
OPERATION
WIRING PRECAUTIONS
The OPAliOO is a wideband, high frequency operational
amplifier with a gain-bandwidth product exceeding 5GHz.
This capability can be realized by observing a few wiring
precautions and using high frequency layout techniques.
In general, all printed circuit board conductors should
be wide to provide low resistance, low impedance signal
paths and should be as short as ·possible. The entire physical circuit should be as small as is practical. Stray capacitances should be minimized, especially at high impedance nodes, such as the input terminals of the amplifier
and compensation pins. Stray signal coupling from the
output to the input should be minimized. All circuit element leads should be as short as possible and low values
of resistance should be used. This will give the best circuit performance as it will minimize the time constants
formed with the circuit capacitances and will eliminate
stray, unwanted tuned circuits.
Grounding is the most important application consideration for the OPA600, as it is with all high frequency
circuits. Ultra-high frequency transistors are used in the
design of the OPA600 and oscillations at frequencies of
500MHz and above can be stimulated if good grounding
......
~
"""""
0.8
0·~75
-50
-25
'" ~
I'
0 +25 +~ +75 +100 +125
Temperature ,OCt
'
techniques are not used. A ground plane is highly
recommended. It should connect all areas of the pattern
side of the printed circuit that are not otherwise used.
The ground plane provides a low resistance, low inductance common return path for all signal and power
returns. The ground plane also reduces stray signal
pickup.
Point-to-point wiring is not recommended. However, if
point-to-point wiring is used, a single-point ground
should be used. The input signal return, the load signal
return and the power supply common should all be connected at the same physical point. This eliminates common current paths or ground loops which can cause
unwanted feedback.
Each power supply lead should be bypassed to ground as
near as possible to the amplifier pins. A II'F CSI3 timtalum capacitor is recommended. A parallel O.OII'F ceramic
may be added if desired. This is especially important
when driving high current loads. Properly bypassed and
modulation-free power supply lines allow full amplifier
output and optimum settling time performance.
OPA600 circuit common "is connected to pins I and 13;
these pins should be connected to the ground plane. The
input signal return, load return, and power supply commmon should also be connected to the ground plane.
18
The primary compensation capacitors are C, and C2(see
Figure I). They are connected between pins 4 and Sand
between pins II and 14. Both C, and C2 should be the
same value. As Figure I and the performance curves
show, larger closed-loop configurations require less capacitance and improved gain-bandwidth product can be·
realized. Note that no compensation capacitor is required
for closed-loop gains equal to or above 100V/V. If upon
initial application the user's circuit is unstable, and
remains so after checking for proper bypassing, grounding, etc., it may be necessary to increase the compensation slightly to eliminate oscillations. Do not over compensate. It should not be necesary to increase C, and C2
beyond 10pF to ISpF. It may also be necessary to individually optimize C, and C2 for improved performance.
The case of the OPA600 is internally connected to circuit
common, and as indicated above, pins I and 13 should be
connected to the ground plane. Ideally, the case should
be mechanically connected to the ground plane for good
thermal transfer, but because this is difficult in practice,
the OPA600 should be fully inserted into the printed
circuit board with the case very close to the ground plane
to make the best possible thermal connection. If the case
and ground plane are physically connected or are in
close thermal proximity, the ground plane will provide
heat sinking which will reduce the case temperature rise.
The minimum OPA600 pin length will minimize lead
inductance, thereby maximizing performam;e.
COMPENSATION
The OPA600 uses external frequency compensation so
that the user may optimize the bandwidth or settling
time for his particular application. Several performance
curves aid in the selection of the correct compensations
capacitance value. The Bode plot shows amplitude and
phase versus frequency for several values of compensation. A related curve shows the recommended compensation capacitance versus closed-loop gain.
The flat high frequency response of the OPA600 is preserved and high frequency peaking is minimized by connecting a small capacitor in parallel with the feedback
resistor (see Figure I). This capacitor compensates for
the closed-loop, high frequency, transfer function zero
that results from the time constant formed by the input
capaci!arfce of the amplifier, typi~aHy 2pF. !\nd thp. inpHt
and feedback resistors. The selected compensation capacitor may be a trimmer, a fixed capacitor or a planned
PC board capacitance. The capacitance value is strongly
dependent on circuit layout and closed-loop gain. It will
typically be 2pF for a clean layout using low resistances
(Ikn) and up to IOpF for circuits using larger resitances.
Using small resistor values will preserve the phase margin and avoid peaking by keeping the break frequency of
this zero sufficiently high. When high closed-loop gains
are required, a three-resistor attenuator is recommended
to avoid using a large value resistor with its long time
constant.
Figure I shows a recommended circuit schematic. Component values and comp~nsation for amplifiers with several different closed-loop gains are shown. This circuit
will yield the specified settling time. Because each device
is unique and slightly different, as is each user's circuit,
optimum settling time will be achieved by individually
compensating each device in its own circuit, if desired. A
10% to 20% improvement in settling time has been experienced from the values indicated in the Electrical Specifications table.
Closed
Loop
Gain
R,
RZ,
R3
R.
c,.cz
C3
c.
+'
open
100
short
open
6,8
0
0
"
-1
620
620
short
open
3.3
4.7
0
56
2.2
CAPACITIVE LOADS
The OPA600 will drive large capacitive ioads (up to
100pF) when properly compensated and settling times of
under ISOns are achievable. The effect of a capacitive
load is to decrease the phase margin of the amplifier,
which may cause high frequency peaking or oscillations.
A solution is to increase the compensation capacitance,
somewhat slowing the amplifier's ability to respond. The
recommended compensation capacitance value as a function of load capacitance is shown in Figure 2. (Use two
capcitors, each with the value indicated.) Alternately,
without increasing the OPA600's compensation capacitance, the capacitive load may be buffered by connecting
a small resistance, usually So. to son, in series with the
Output, pin 8.
For very-large capacitive loads, greater than 100pF, it
will be necessary to use doublet compensation. Refer to
Figure 3 and discussion on slew rate. This places the
dominant pole at the input stage. Settling time will be
approximately SO% slower; slew rate should increase.
Load capacitance should be minimized for optimum
high frequency performance.
Because of its large output capability, the OPA600 is
particularly well suited for driving loads via coaxial
R5
-10
'00
open
,
'00
3,3k
32k
0
,
0
100
'k
3,3k
short
-100
0
100
-1000
'00
3.3k
3.3k
116
0
0
4,7
100
FIGURE I. Recommended Amplifier Circuits and
Frequency Compensation.
19
250
125
-3pF'
6000
200
Ii:
e"c:
C)
S
'u
..
..,.
U
5lc:
150 ;;
75
E
i=
C-
U
6000
e'N
O>
.,.
'"
50
100 ,§
25
50
0
...J
8
0
10 0
Compensation Capacitance (pF i
'3pF typo should match stray capacitance between pin 3 and common.
FIGURE 2. Capacitive Load Compensation and Response.
cables. Note that the capacitance of coaxial cable
(29pF /foot ofiength for RG-58) will not load the amplifier when the coaxial cable or transmission line is terminated in its characteristic impedance.
=3pF
6000
SETTLING TIME
Settling time is defined as the total time required, from
the input signal step, for the output to settle to within the
specified error band around the final value. This error
band is expressed as a percentage of the magnitude of
the output transition, a lOY step.
Settling time is a complete dynamic measure of the
OPA600's total performance. It includes the slew ra,te
time, a large signal dynamic parameter, and the time to
accurately reach the final vaiue, a small signal parameter
that is a function of bandwidth and open-loop gain. Performance curves show the OPA600 settling time to ±I%,
±O.l%, and ±0.01%. The best settling time is achieved in
low closed-loop gain circuits.
Settling time is dependent upon compensation. Undercompensation will result in small phase margin, overshoot or instability. Over-compensation will result in
poor settling time.
Figure I shows the recommended compensation to yield
the specified settling time. Improved or optimum settling
time may be achieved by individually compensating each
device in the user's circuit since individual devices vary
slightly from one to another, as do user's circuits.
For alternate doublet compensation refer to Figure 3.
For a closed-loop gain equal to -I, delete Cl and C2 and
add a series RC circuit (R = 220, C = O.OIp.F) between
pins 14 and 4. Make no connections to pins 11 and 5.
Absolutely minimze the capacitance to these pins. If a
connector is used for the OPA600, it is recommended
that sockets for pins 11 and 5 be removed. For a PC
board mount, it is recommended that the PC board
holes be overdrilled for pins II and 5 and adjacent
ground plane copper be removed. Effectively this compensation places the dominant pole at the input stage,
allowing the output stage to have no compensation and
to slew as fast as possible. Bandwidth and settling time
are impaired only slightly. For closed-loop gains other
than -I, diffe'rent values of Rand C may be required.
SLEW'RATE
OFFSET ADJUSTMENT
Slew rate is primarly an output, large signal parameter.
It has virtually no dependence upon the closed-loop gain
or small signal bandwidth. Slew rate is dependent upon
compensation and decreasing the compensation capacitor value will increase the available slew rate as shown in
the performance curve.
The OPA600 slew rate may be increased by using an
alternate compensation. as shown in Figure 3.. The slew
rate will increase between 700 and 800Y/ p.s typical, with
0.01% settling time increasing to between 175 and 190ns
typical, and 0.1% settling time increasing to between 110
.and 120ns typical.
The offset voltage of the OPA600 may be adjusted to
zero by connecting a 5kO resistor in series with a IOkO
linear potentiometer in series with another 5kO resistor
between pins 2 and 15, as shown in Figure 4. It is important that one end of each of the two resistors be located
very close to pins 2 and IS" to isolate and avoid loading
these sensitive terminals. The potentiometer should be a
small noninductive type with the wiper connected to the
positive supply. The leads connecting these components
should be short, no longer than O.S-inch, to avoid stray
capacitance and stray signal pick-Up. If the potentiometer must be located away from the immediate vicin-
·3pF typo should match stray capacitance between pin 3 and common.
FIGURE. 3. Amplifier Circuit for Increased Slew Rate.
20
t
the 0 PA600 can deliver these current pulses is limited by
the RC time constant.
The internal voltage drops, output voltage available,
power dissipation, and maximum output current can be
determined for the user's application by knowing the
load resistance and computing:
VOUT = 14 [RLOAD ';- (SO + RLOAD)]
This applies for ReoAD less than lOon and the current
boost not activated. When RLOAD is large, the peak output voltage is typically ±IlV, which is determined by
other factors within the OPA600.
+VCC
10kCl
5kCl
5kCl
SHORT-CIRCUIT PROTECTION
The OPA600 is short-circuit-protected for momentary
short to common «Ss), typical of those enountered
when probing a circuit during experimental breadboarding or troubleshooting. This is true only if pins 7 and 9
are open (current boost not activated). An internal son
resistor is in series with the collector of each of the output transistors, which under fault conditions will cause
the output transistors to saturate and limit the power
dissipation in the output stage. Extended application of
an output short can damage the amplifier due to excessive power dissipation.
The OPA600 is not short-circuit-protected when the current boost is activated. The large output current capability of the OPA600 will cause excessive power dissipation
and permanent damage will result even for momentary
shorts to ground.
Output shorts to either supply will destroy the OPA600
whether the current boost- is activated or not.
FIGURE 4. Offset Null Circuit.
ity of the OPA600, extreme care must be observed with
the sensitive leads. Locate the two Skn resistors very
close to pins 2 and IS.
Never connect +Vcc directly to pin 2 or IS. Do not
attempt to eliminate the Skn resistors because at extreme
r('t~tion> the potentiometer will directly connect +Vr,. to
pin 2 or IS and permanent damage will result.
Offset voltage adjustment is optional. The potentiometer
and two resistors are omitted when the offset voltage is
considered sufficiently low for the particular application.
For each microvolt of offset voltage adjusted, the offset voltage temperature sensitivity will change by
±0.004j.1V/oC.
CURRENT BOOST
External ability to bypass the internal current limiting
. resistors has been provided in the QPA600. This is
referred to as current boost. Current boost enables the
OPA600 to deliver large currents into heavy loads
(±200mA at ±IOV). To bypass the resistors and activate
the current boost, connect pin 7 to - Vee at pin 6 with a
short lead to minimize lead inductance and connect pin 9
to +Vcc at pin 12 with a short lead.
HEAT SINKING AND POWER DISSIPATION
The OPA600 is intended as a printed circuit board
mounted device, and as s\lch does not require a heat
sink. It is specified for ambient temperature operation
from -SSOC to + l2SoC. However, the power dissipation
must be kept within safe limits. At extreme temperature
and under full load conditions, some form of heat sinking will be necessary. The use of a heat sink, or other
heat dissipating means such as proximity to the ground
plane, will result in cooler operating temperatures, better
temperature performance, and improved reliability.
It may be necessary to physically connect the OPA600 to
the printed circuit board ground plane, attach fins, tabs,
etc., to dissipate the generated heat. Because of the wide
variety of possibilities, this task is left to the user. For all
applications it is recommended that the OPA600 be fully
inserted into the printed circuit board and that the pin
length be short. Heat will be dissipated through the
ground plane and the AC performance will be its best.
With a maximum case temperature of'+12SoC and not
exceeding the maximum junction of + I7SoC, a maximum power dissipation of 600mW is allowed in either
output transistor.
CAUTION-Activating current boost by bypassing the
internal current limiting resistors can permanently damage the OPA600 under fault conditions. See section on
short circuit protection.
Not activating current boost is especially useful for
initial breadboarding. The son (±S%) current limiting
resistor in the collector circuit of each of the output
transistors causes the output transistors to saturate; this
limits the power dissipation in the output stage in case of
a fault. Operating with the current boost not activated
may also be desirable with small-signal outputs (i.e.,
±IV) or when the load current is small.
Each resistor is internally capacitively-bypassed (O.Olj.lF,
±20%) to allow the amplifier' to deliver large pulses of
current, such as to charge diode junctions or circuit capacitance and still respond quickly. The length of time that
21
TESTING
For static and low frequency dynamic measurements,
the OPA600 may be tested in conventional operational
amplifier test circuits, provided proper ground techniques are observed, excessive lead lengths are avoided,
and care is maintained to avoid parasitic oscillations.
The circuit in Figure 3is recommended for low fre~
quency functional testing, incoming inspection, etc. This
circuit is less susceptible to stray capacitance, excessive
lead length, parasitic tuned circuits, changing capacitive
loads, etc. It does not yield optimum settling time. We
recommend placing a resistor (approximately 3000) in
series with each piece of test equipment, such as a DVM,
to isolate loading effects on the,OPA600.
.
To realize the full performance capabilities ofthe OPA600,
high frequency techniques must be employed and the test
fixture must not limit the amplifier. Settling time is the
most critical dynamic test and Figure 5 shows a recommended OPA600 settling time test circuit schematic.
Good grounding, truly square drive signals, minimum
stray coupling, and small physical size are important.
The input pulse generator must have a flat topped, fast
settling pulse to measure the true settling time of the
amplifier. A circuit that generates a ±5V flat topped
pulse is shown in Figure 6.
(21 HP2835
+~
....
Pulse In
Error Out
Input = ±5V
Output = ±5V
Error Output ±O,5mV (±0,01%)
':"
(1) 0,020 Matched
-15VDC
(2) With Co C. 3,3pF typical, C, optimized for circuit layout, and RL
(3) Use 5100 with generator of Figure 6,
= =
1pF
=500, t. < 100ns,
15VDC
~
FIGURE 5. Settling Time and Slew Rate Test Circuit.
+15VDC
+15VDC
+--""'........+----f:'O) Pulse Out
Trigger In
Input.::: TTL
Output - "!:SV.
1.8kO
'ALT 2N3906
2N2907
.
.... 15VDC
100pF
-15VDC~
*" +,
r
10IIF
100pF
150
':"
-15VDC
FIGURE 6. Flat Top Pulse Generator.
22
BURR-BROWN®
IElElI
OPA602
(~~
l~)
·\l.~
)j
~
,
,
,
ADVANCE INFORMATION
Subject to Change
High-Speed Precision
O//e'® OPERATIONAL AMPLIFIER
APPLICATIONS
FEATURES
_ nnr:I',(llnl'
•
•
•
•
•
HIGH SLEW RATE: 35V/ps
LOW OFFSET: ±250pV max
LOW BIAS CURRENT: ±lpA max
FAST SETTLING: Ips 10 0.01%
UNITY·GAIN STABLE
IllQlTDllUl:lITIlTlnll
...
I IIL.Un,IUI'
•
•
•
•
•
OPTOELECTRONICS
SONAR. ULTRASOUND
PROFESSIONAL AUDIO EQUIPMENT
MEDICAL EQUIPMENT
DATA CONVERSION
.. ,"'. IIUI1I ...... " . I""n
DESCRIPTION
The OPA602 is a precision, wide bandwidth FET
operational amplifier. Monolithic Dire' (dielectrically isolated FET) construction provides an unusual combination of high speed and accuracy.
Its wide bandwidth design minimizes dynamic errors.
High slew rate and fast-settling behavior allow
accurate signal processing in pulse and data conversion applications. Wide bandwidth and low distortion
characteristics provide high performance in frequency-domain circuitry. All dynamic and DC specifications are rated with a IkO resistor in parallel with
500pF load impedance. The OPA602 is unity-gain
stable and easily drives capacitive loads up to l500pF.
Laser-trimmed input circuitry provides offset voltage
and drift performance normally associated with
precision bipolar op amps. Dire' construction
achieves extremely low input bias currents (I pA
max) without compromisin& input voltage noise.
The OPA602's unique input cascode c.ircuitry maintains low input bias current and precise input char.~cteristics over its full input common~mode voltage
range.
Oire'®
Burr-Brown Corp.
Inlernalional Alrporllnduslrial Park· P.O. Box 11400· Tucson. Arizona 85734 • Tel. (6021 746·1111 • Twx: 911).952-1111 . Cable: BBRCORP . Telex: 66·8491
PDS-753
23
SPECIFICATIONS
ELECTRICAL
At Vs
= ±15VDC and TA = +25°C unless otherwise 'noted.
OPA602AM
PARAMETER
CONDITIONS
INPUT NOISE
Voltage: fo = 10Hz
fo = 100Hz
fo = 1kHz
fo = 10kHz
fa = 10Hz to 10kHz
fa = O.IHz to 10Hz
Current: f8
MIN
-
OFFSET VOLTAGE
Average Drift
VCM = OVDC
T" = TMIN to TMAX
±Vs = 12V to 18V
70
TYP
MAX
OPA602CM
MIN
··
±1000
±15
80
TYP
MAX
UNITS
···
···
·
23
19
·13
12
1.4
0.95
12
0.6
±300
±550
BIAS CURRENT
Input Bias Current
Over Specified Temp.
MIN
··
··
·
fo = O.IHz to 20kHz
Supply Rejection
OPA602BM/SM
MAX
··
·
= O.lHz to 10Hz
Inpul Offsel Voltage
Over Specified Temp.
TYP
nV/v'Hz
nV/v'Hz
nV/v'Hz
nV/v'Hz
/iVrms
INp-p
fAp-p
fAlv'Hz
·
±150
±250
±3
100
·±500
±1000
±5
±100
±200
±1
86
·
±2.50
±500
±2
IN
pV
pV/'C
dB
VCM =OVDC
±2
±20
±10
±500
±1
±20
±200
±2
±200
±2000
±0.5
±10
±1
±100
pA
pA
pA
VCM =OVDC
1
20
10
500
0.5
20
200
2
200
1000
0.5
10
1
100
pA
pA
pA
SM Grade
OFFSET CURRENT
Input Offset Current
Over Specified Temp.
SM Grade
INPUT IMPEDANCE
Differential
Common-Mode
INPUT VOLTAGE RANGE
+13,
-'-II
100
92
dB
R,?lkn
75
88
100
92
dB
Gain = 100
20Vp-p, R, = lkn
Vo = ±10V, R, = lkn
3.5
4
MHz
kHz
24
6.5
570
35
0.7
1.0
5
20
28
V/fiS
FREQUENCY RESPONSE
Gain Bandwidlh
Full Power Response
Settling Time: 0.1%
0.01%
Gain
= -1,
RL
= 1kO
C, = 500pF, 10V step
RATED OUTPUT
Voltage Output
Current Output
Output Re'sistance
Load Capacitance Stability
R,=lkn
Vo ",±10VDC
lMHz, open loop
Gain = +1
Raled Voltage
Voltage Range,
10=OmADC
TEMPERATURE RANGE
Specification
Ambient temp.
SM Grade
Operating
Storage
Ambient temp.
Ambient temp.
8 Junction-Ambient
*Speciflcation same as OPA602BM
±11
±25'
Short Circuit Current
POWER SUPPLY
Derated Performance
Current, Quiescent
Over Specified Temp.
nllpF
nllpF
88
OPEN LOOP GAIN, DC
±10.2
··
· ·
·
·
··
··
·
· ·
· ··
· ··
·
· · ··
· ·
·
·
··
··
·
75
V1N
Open-Loop Voltage Gain
Slew Rate
10"111
10"113
= ±10VDC
Common-Mode Input Range
Common-Mode Rejection
··
· ·
·
·
··
··
·
·
· ··
··
·
· · ··
· ·
·
·
··
··
·
±11.5
±15
±30
+12.9,
-13,8
±20
80
1500
±50
±15
±5
3
3.5
-25
-55
-55
-65
±18
4
4.5
+85
±125
+125,
+150
200
V
fiS
ps
V
rnA
n
pF
mA
VDC
VDC
mA
mA
'C
'C
·C
'C
'CIW
ORDERING INFORMATION
OPA602
Basic model number--..,.-----------y----J
Performance grade code
(
) .(
T.
T
A, B, C: -25'C to +85'C
S: -55'C to +125'C
Package Code----------------~
M: TO-99 Metal Package
24
)
MECHANICAL
CONNECTION DIAGRAM
TO-99 Package
Top View
NC
NOTE: Leads in true position
within .010" (.2Smm) Rat MMC
at seating plane.
seati~g IIIII~
Plane
---1\....-0
DIM
A
B
C
0
E
ABSOLUTE MAXIMUM RATINGS
Supply ................•.....•..................•..•••.• ±18VDC
Internal Power Dissipation (T, :5 +175'C) ................ +1000mW
Differential Input Voltage .......•••....................... Total Vs
Input Voltage Range ...•...........•........•.......•......•. ±Vs
F
INCHES
MIN
MAX
.335
.370
.305
.335
.165
.185
.016
.021
.010
.040
.010
.040
G
.200 BASIC
H
.028
.034
.029
.045
.500
.110
.IGU
45' BASIC
.095
.105
Storage Temperature Range .... ',_ ............... -65°C to +150°C
O..,cle.i.ill!;j TCllltJt;ll'ia;'UI~ nall\tCs ................... -G:;"C lc.. -1-12:;"C
J
K
L
Lead Temperature (soldering 10 seconds) .................. +300°C
Output Short-Circuit to ground (+25'C) ...•• Continuous to ground
M
N
MILLIMETERS
MIN
MAX
8.51
9.40
7.75
8.51
4.19
4.70
0.41
0.53
0.25
1.02
1.02
0.25
5.08 BASIC
0.71
0.8B
0.74
1.14
12.7
".Gu
£.,:::1
45' BASIC
2.41
2.67
Junction Temperature ...............................•.... +175°C
TYPICAL PERFORMANCE CURVES
T.
= +25'C, Vs = ±ISVDC unless otherwise noted.
INPUT CURRENT NOISE SPECTRAL DENSITY
100
l~
>
~
INPUT VOLTAGE NOISE SPECTRAL DENSITY
lk
l~
,
>
;:
10
100
Eo
lil
0
z
.......
lil
0
z
l
C
~
~
10
~
'5
I;
"0
(J
>
I
01
100
10
lk
10k
Frequency (Hz)
1M
lOOk
10
POWER SUPPLY REJECTION AND COMMON-MODE
REJECTION vs TEMPERATURE
0..
CMR
..
a:"
100
(J
95
ttt-
"
105
a:
"0
PSR
::;:
---
~ 100
.",
ul
...........
3i
o
z
t:::
r-:-
~
~
1M
-50
-25
o
+25
+50
Temperature (DC)
OPA602 + Resistor ...
.Uo"'"
~ 10
!!!
"0
Resistor noise only
1
+75
,
:. itt
>
90
-75
lOOk
TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY
AT 1kHz vs SOURCE RESISTANCE
L~
:!!.
'"
10k
Frequency (Hz)
lk
lk
110
iii"
100
+100
~
100
+125
25
IIII I IIII
lk
10k
lOOk
1M
Source Resistance (0)
10M
100M
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25'C,
10nA
v. = ±15VDC unless otherwise noted.
BIAS AND OFFSET CURRENT
YS TEMPERATURE
YS
~~~tt~~~~~~~~~t!~~~~~'0nA
BIAS AND OFFSET CURRENT
INPUT COMMON MODE VOLTAGE
InA
<
~
E
i!!
~
u
.'"
100
10
Iii
tt:tjjtt:t:t:t:t11:1::t:t::tti:i:1:1:jj 0.1
0.1
-50
-25
0
+25
+50
+75
+100
om LJ...I..L.J..L.J...Ll..J,..l...Ll..u...Ll...Ll...l...L...l...L..L.J...Ll..u..L.J..J...JU-JUJ 0.01
-15
-10
-5
o +5 +10 +15
+125
Common-Mode Voltage (V)
Ambient Temperature (Oe)
POWER SUPPLY. REJECT ION
YS FREOUENCY
140
COMMON-MODE REJECTION
YS FREOUENCY
140 rr01rrr-"rT11rr01rrr-"'-rT11rT01m-,.-n-r....,....,m
is.
60
Q.
+
..
~
rJl
Iii
40
a.
20
..
~
0
0
H-:+Hf-+++lf-H+HH+I*+++lf-Hf-I+H+l+I
1
100
10
lk
10k
I
..
1M
lOOk
10M
Frequency (Hz)
Frequency (Hz)
YS
COMMON-MODE REJECTION
INPUT COMMON MODE VOLTAGE
120
90
l!!
e0
E
E
0
~
~
100
40
-10
-5
0
o
+5
+10
+15
8
~
1
100
10
..........
6
"CDc:
c:
35
R........
,
L~
~:-
. Slew Rate
4
\
CJ
2
-75 -50
-25
0
+25
+50
+75
lk
10k
lOOk
1M
""
-180
10M
Frequency (Hz)
37
r;
ij
1
GAIN-BANDWIDTH AND SLEW RATE
YS SUPPLY VOLTAGE
10
.
~
- 135
Ao<
Oommon-Mode Voltage (VI
i
;::
,
GAIN-BANDWIDTH AND SLEW· RATE
YS TEMPERATURE
<;
-90 ~:
20
70
-15
...
-
60
80
u
:I:
i
til
80
'5
>
-45
-+
c.,:,'00pF
iii 100
a:
:;
III
RL -lkCl
120
110
c:
.2
tl
OPEN-LOOP FREOUENCY RESPONSE
140
8
en
I:Jl
..
33 Ii
~
!
31
36
L~~11
of
~
r;
-h
i
".c:
CD
c:
~
6
ij
i-"
5
o
ILl-
SlrjR'jte
10
15
26
i
:Jl
34
Supply Voltage (±Vcc)
Ambient Temperature ("'C)
36
ioI"i-"""
CJ
29
+100 +125
.... ~
GBW
<;
32
20
~
~
!.
TYPICAL PERfORMANCE CURVES (CONT)
T" :::;: +25°C, Vs
= ±15VDC unless otherwise noted.
OPEN-LOOP GAIN
vs TEMPERATURE
120
- ---...
110
iii
~
.
c
100
l!l
Q)
N'
0
>
-50
-25
o
,
c:
6.
~ 20
Q)
........
~
90
80
-75
MAXIMUM OUTPUT VOLTAGE SWING
vs FREQUENCY
30
+25
+50
'"
1!!
o
r-.....
+75
.>
5..
-:;
" "'"
+100
10
1'-
o
"
-R,=lkQ
o
+125
10k
......
1M
lOOk
10M
Ambient Temperature (DC)
Frequency (Hz)
LARGE SIGNAL TRANSIENT RESPONSE
SMALL SIGNAL TRANSIENT RESPONSE
(Time (ps)
Time (PO)
~ +10
a.
1!!
0
>
0
0
-10
-:;
Co
-:;
SETTLING TIME
vs CLOSED-LOOP GAIN
4
i
CD
E
;( 3.25
3
c
I I
1/ 1/
2
~
~
~
5 3.0
()
'"
/
0.
Co
I'
~ 2.75
R,=lkQ
C,= 100pF
0
-10
-100
Closed-Loop Gain (VIV)
-1
2.5
-75
-lk
-50
-25
+25
0
...E
N'
;g
0.1
i!:
;~
-
--c-
z
+
o
96
.
+.
_l..
rms
lkQ
-:-
Av= +10WIV
0.01
_JTest
Av=+WN-.,
92
.J;I
o
5
10
15
Supply Voltage (±Vcc)
+125
.L
Av-+,10WN
-
~
i-"
CD
+100
TOTAL HARMONIC DISTORTION
VS FREQUENCY
100
l!l
+75
1.0
40.2kQ
...c
+50
---
Ambient Temperature (DC)
OPEN-LOOP GAIN vs SUPPLY VOLTAGE
104
- - -r--r-
g
J
i=
.='"
irn
SUPPLY CURRENT vs TEMPERATURE
3.5
I I
J It
II
0.001
0.1
20
-
10
100
Frequency (Hz)
27
lk
I
10k
Limit
lOOk
APPLICATIONS INFORMATION
(2)
HP 5082-2835
+15V
2kO
2kO
500
1pF
+~
5100
2kO
+15V
1pF
High Quality
+~
1pF Tantalum
Pulse Generator
+~
Pulse In
±5V
1I22N5564
2kO
>-----------+--{e
510
Output
Error Out
±0.5mV
(0.01%)
t----{e
-15V
5100
1P~
-15V
FIGURE 1. Settling Time and Slew Rate Test Circuit.
6
±10mV Typical
Trim Range
·10kO to 1MO Trim
Potentiometer (100kO
Recommended)
FIGURE 2. Offset Voltage Trim.
28
.....
BURR-BROWN®
OPA633
IElEI·1
High Speed
BUFFER AMPLIFIER
FEATURES
APPLICATIONS
275M!!z
HIGH SLEW RATE: 2500V/pS
HIGH OUTPUT CURRENT:.100mA
LOW OFFSET VOLTAGE: 1.5mV
REPLACES HA·5033
IMPROVED PERFORMANCE/PRICE: LH0033,
LTC10l0, HOS200
'!' '.A!!!!~ !!A~!!'.A!!!!T!!:
•
•
.•
•
•
Q
OP AMP r.IIRRENT BRRSTER
o VIDEO BUFFER
• LINE DRIVER
o A/D CONVERTER INPUT BUFFER
+Vs
DESCRIPTION
The OPA633 is a monolithic unity·gain buffer amplifier featuring very wide bandwidth and high slew
rate. A dielectric isolation process incorporating
both NPN and PNP high frequency transistors
achieves performance unattainable with conventional
integrated circuit technology. Laser trimming provides low input offset voltage.
High output current capability allows the OPA633
to drive son and 7Sn lines, making it ideal for RF,
IF and video applications. Low phase shift allows
the OPA633 to be used inside amplifier feedback
loops thus bringing high current output and ability
to drive capacitive loads to many circuit applications.
The OPA633 is available in the 12-pin TO·8 hermetic
metal package with -2Soe to +8Soe and -ssoe to
+12Soe temperature ranges and a low cost plastic
DIP package specified for operation from ooe to
+7S°c..
j
V'N
"
l"-
?r;
v
t-.
VOUT
LK
S--
v
"-
-Vs
f'o
Inlernational Airport Industrial Park. P.O. Box 11400 • Tucson. Arizona B5734 • Tel.: 1602) 746·1111 • Twx: 910·952·1111 • Cable: BBftCORP • Telex: 66·6491
PDS·699
29
SPECIFICATIONS
ELECTRICAL
At +25'C, Vs = ±12V, Rs = 500, R, = 1000, C, = tOpF unless otherwise noted,
OPA633AH
PARAMETER
CONDITIONS
MIN
TYP
OPA633SH
MAX
FREQUENCY RESPONSE
Small Signal Bandwidth
= 1Vrms, Rl = lkO
Full Power Bandwidth
Vo
Slew Rate
Rise Time. 10% to 90%
Vo = 10V, Vs = ±15V, R, = lkO
Vo = 500mV
1000
Propagation Delay
Overshoot
Settling Time, 0.1%
Differential Phase Errorl1)
Differential Gain Error '11
Total Harmonic Distortion
Vo = tvrms, R, = lkO, I = 100kHz
Vo = tvrms, R, = 1000, I = 100kHz
Voltage
TAo
= TMIN to TMAX
R, = lkO, Vs = ±15V
±S.O
±11
±SO
±10
'±13
±100
5
0.93
0.95
0.99
0.95
Resistance
···
·
·
TRANSFER CHARACTERISTICS
Gain
R,=lkO
TA
= TMIN to TMAX
0.92
tNPUT
Oflset Voltage
T,= +25'C
TAo::: TMIN to TMAX
vs Temperature
vs Supply
Bias Current
Noise Voltage
Resistance
Capacitance
TA ::: TMIN to TMAX
T.= +25'C
TA == TMIN to TMAX
10Hz to lMHz
54
±1.5
±5
±33
72
±15
±20
20
1.5
1.6
±15
±25
±35
±50
POWER SUPPLY
Rated Supply Voltage
Operating Supply Voltage
Current, Quiescent
Specified performance
Derated performance
10=0
10 = 0, TAo::;:: TMIN to TMAX
±12
±5
21
21
±16
25
30
TEMPERATURE RANGE
-25
-55
Specification, Ambient
Operating. Ambient
8 Junction, Ambient C21
8 Junction, Casel21
TYP
OPA633KP
MAX
··
· ··
···
··
·
275
65
2500
2.5
1
10
50
0.1
0.1
0.005
0.02
OUTPUT CHARACTERISTICS
Current
MIN
+S5
+125
MIN
• Specification same as OPA633AH.
MAX
260
40
···
·
··
· ··
··
··
··
· ·..
· ··
· ··
· ·
·
··'. ··
±5
±6
VIps
ns
ns
%
ns
Degrees
%
%
%
V
V
mA
0
VN
VlV
VN
··
··
· ·· · · ···
·· ·
··
··
··
· ·· ·· · ·· ··
· ·
· ·
· · ·
-55
+125
0
-25
UNITS
MHz
MHz
.'
·
99
31
TYP
+75
+S5'
90
27
mV
mV
pVl'C
dB
pA
pA
pVp-p
MO
pF
V
V
rnA
rnA
'c
'c
'C/W
'C/W
NOTES:
(1) Differential phase error in video transmission systems is the change in phase of a colorsubcarrier resulting from a change in picture signal from blanked
to white. Differential gain error is the change in amplitude at the color subcarrier frequency resulting from a change in picture Signal from blanked to
white. (2) Recommended heat sinks lor the TO-S package are: Thermalloy 2204A with
= 27'C/W and IERC Up TO-S-4SCB,
= 10'C/W.
e••
CONNECTION DIAGRAMS
ABSOLUTE MAXIMUM RATINGS
Power Supply, ±V, , ............•.... , .........• ±20V
Input Voltage V,N • , , .............. , +V. + 2 to -V. - 2
Output Current (peak) ...•............. , •.... ±200mA
Internal Power Dissipation (25'C): 1'o-s (H) .... 1.75W
DIP (P) ...... 1.95W
Junction Temperature ......................... 200°C
Storage Temperature Range: TO-S .. , -65'C to +150'C
,
DIP ..... -40'C to +S5'C
Lead Temperature (soldering, 60s) ............. 300'C
Case
+V,
Out
NC
NC
NC
In
Substrate
(Ground)
e••
IN
-Vs
Case
30
MECHANICAL
TO·8
~:=i1
'~
m=tl
12
"
-01-0
/
8~Pin
8
I
o
0-0
I
Plastic
M
I
...IN
Eb~
.
m
I.-j L
H
""'-Pin 1
! !J
s;,~~:g
MAX
MIN
.593
.603
.553
.150
.019
040
15.06
15.32
13.89
14.05
3.30
3.Bl
0.41
0.48
1.02
.547
,130
.016
,ala
0.25
066
0.66
M
N
.100 BASIC
DIM
A
A,
MIN
MAX
MIN
MAX
.355
.400
.385
.290
.250
.200
.023
.070
9.03
8.65
5.85
5.09
3.05
0.38
0.76
10.16
.100 BASIC
1.78
2.54 BASIC
.025
.008
0.64
0.20
1.27
0.38
8
e,
C
D
F
l~--.J\\
.J L M
MAX
.026
.036
.026
.036
500
.562
45° BASIC
J
~
tNf
D G
MILLIMETERS
MIN
G
H
J
K
L
..\\.-J
.340
.230
.200
.120
.015
.030
14.27
45° BASIC
2.54 BASIC
MILLIMETERS
.050
.015
.150
.070
0.91
0.91
12.70
INCHES
----.C
!
E
H
L/
----1 '
,
D
K
NOTE: Leads in true position
within 0.01" 10.25mm) R at MMC
at seating plane.
.
C
NOTE: Leads in true
position within 0.010"
(D.25mm) R a1 MMC at
seating plane.
-0
~
P
-.J
0 3_
I
..H-D
"P" Package.
DIM
A
--:-1-~n
------I
-,-I--i
~~
~ ~ ~ ~
INCHES
J
/Hd.
.300 BASIC
9.80
7.38
6.36
5.09
0.59
3.82
1.78
7.63 BASIC
n'
'"
1"
TYPICAL PERFORMANCE CURVES
SMALL SIGNAL BANDWIDTH VS TEMPERATURE
GAIN/PHASE VS FREQUENCY
+6
+2
-2
-4
Cl
-6
-8
1/ \
.......
iii'
...'c"
,
~
+4
--- Rs = 300n
-Rs=50n
300
~
0.5
I
z
;; 0.4
0.3
Vs - ±5V
0.2
0.1
0
100
200 300 400 500
600 700
800 900
lk
10
20
30
40
r---T---:==~;::---'"
:>
oS
SO
;;
I
0
>
~
0>
J!l 0.85
g
Vo
RL
r-
z
·iii
t!l
o
-50
+.1-~10b~ ~
+0.8
+0.6
-
r---
o
-25
V l.......:: ~
h ~ I""'"" .......
~ +0.2
....... ~~AL-\~O
AL
~
~~
~ I--
-1.0
-10 -8
10kn
r-
"'~ ' l
Lr-
+40
+20
0
-20
~
"3
.s
2
4
:>
oS
+2
~
>
0
-2
-80
0
+100
+125
+4
f
I
if,
-60
-2
+75
+80
+60
-40
~
-4
+50
+S
V
10
Input Voltage (V)
L
~~
V
-25
o
+25
+50
Temperature (oG)
33
~
./
-4
-50
-100
-6
+25
OFFSET VOLTAGE VS TEMPERATURE
+100
A,-500,
+0.4
-0.8
±10V
lkO
Temperature (OC)
OUTPUT EAAOA VS INPUT VOLTAGE
+1.0
-0.6
100
40
Load Aesistance (0)
-0.4
90
20
0.80. &..I~---.l....----"""----....I
lk
10k
100
10
5
80
80
0.90
JI -0.20
70
100
0.95 t----~'Io"''-----,...----_;
~c
60
GAIN ERROR VS TEMPERATURE
VOLTAGE GAIN VS LOAD AESISTANCE
1.00
50
Output Current (mA)
Load Aesistance (0)
+75
+100 +125
INSTALLATION AND
OPERATION
CIRCUIT LAYOUT
As with any high frequency circuitry, good circuit layout
technique must be used to achieve optimum performance.
A circuit-board layout is provided which demonstrates
the principles of good layout. Most of the applications
circuits shown can be evaluated using this circuit board.
Pinout of the TO-8 package version haS'been designed
for maximum compatibility with other buffer amplifiers.
Pins I and 12 are internally connected to +Vs. Pins 9 and
10 are internally connected to -Vs. This allows the
OPA633 to be used in applications presently using the
LH0033 buffer amplifier. Only one of the power supply
connections for +Vs and -Vs must be connected for
proper operation.
Power supply connections must be bypassed with high
frequency capacitors. Many applications benefit from
the use of two capacitors on each power supply-a
ceralJlic capacitor for good high frequency deco'upling'
and a tantalum type for lower frequencies. They should
be located as close as possible, to the buffer's power
supply pins. A large ground plane is used to minimize
high frequency ground drops and stray coupling.
Since significant heat transfer takes place through the
package leads, wide printed circuit traces to all leads will
improve heat sinking. Sockets can reduce heat sinking
significantly and thus are not recommended.
Junction temperature rise is proportional to internal
power dissipation. This can be reduced by using the
minimum supply voltage necessary to produce the required' output voltage swing. For instance" I V video
signals can be easily handled with ±5V power supplies
thus minimizing the internal power dissipation.
Output overloads or short circuits can result in permanent
damage by causing excessive output current. The 50.0 or
75.0 series ~lUtput resistor used to match line impedance
will, in most cases, provide adequate protection. When
this resistor is not used, the device can be protected by
limiting the power supply current. See "Protection
Circuits."
Excessive input levels at high frequency can cause increased internal dissipation and permanent damage. See
the safe input voltage versus frequency curves. When
used to buffer an op amp's output, the input to the
OPA633 is limited, in most cases, by the op amp. When
high frequency inputs can exceed sitfe levels, the device
must be protected by limiting the power supply current.
The case of the TO-8 package is connected to pin 2;
which should be grounded. Pin 6 of the DIP package
connects to the substrate of the integrated circuit and
should be connected to ground. In principle it could also
be connected to +Vs or -Vs, but ground is preferable.
The additional lead length and capacitance associated
with sockets may present problems in applications requiring the highest fidelity of high speed pulses.
Depending on the nature ofthe input source impedance,
a series input resistor may be required for best stability.
This behavior is influenced somewhat by the load impedance (including any reactive effects). A value of 50n to
200.0 is typical. This resistor should be located close to
the OPA633's input pin to avoid stray capacitance at the
input which could reduce bandwidth (see Gain and
Phase Versus Frequency curve).
PROTECTION CIRCUITS
The OPA633 can be protected from damage, due to
excessive currents, by the simple addition of resistors in
series with the power supply pins (Figure 5a). While this
limits output current, it also limits voltage swing with
low impedance loads. This reduction in voltage swing is
minimal for AC or high crest factor signals since only the
average current from the power supply causes a voltage
drop across the series resistor. Short'duration loadcurrent peaks are supplied by the bypass capacitors.
The circuit of Figure 5b overcomes the limitations of the
previous circuit with DC loads. It allows nearly full
output voltage swing up to its current limit of approximately 140mA. Both circuits require good high frequency
capacitors (e.g., tantalum) to bypass the buffer's power
supply connections.
OVERLOAD CONDITIONS
The input and output circuitry of the OPA633 are not
protected from overload. When the input signal and load
characteristics are within the device's capabilities, no
protection circuitry is required. Exceeding device limits
can result in permanent damage.
The OPA633's small package and high output current
capability can lead to overheating. The internal junction
temperature should not be allowed to exceed 150°C.
Although failure is unlikely to occur until junction
temperature exceeds 200°C, reliability of the part will be
degraded significantly at such high temperatures. External
heat sinks can be used to reduce the temperature rise.
CAP~CITIVE LOADS
. The OPA633 is designed to safely drive capacitive loads
up to O.OlJ.lF. It must be understood, however, that
rapidly changing voltages demand large output load
currents:
ILOAD = (CLOAD) dV/dt
Thus a signal slew rate of 1000V/ J.lS and load capacitance
of O.OIJ.lF demands a load current of lOA. Clearly
maximum slew rates cannot be combined with large
capacitive loads. Load current should be kept less than
100mA continuous (200mA peak) by limiting the rate of
change of the input signal or reducing the load capacitance.
34
USE INSIDE A FEEDBACK LOOP
by the buffer are divided by the loop gain of the op amp.
The OPA633 may be used inside the feedback path of an
op amp such as the OPA606. Higher output current is
achieved without degradation in accu·racy. This approach
may actually improve performance in precision applications by removing load-dependent dissipation from a
precision op amp. All vestiges of load-dependent offset
voltage and temperature drift can be eliminated with this
technique. Since the buffer is placed within the feedback
loop of the op amp, its DC errors will have a negligible
effect on overall accuracy. Any DC errors contributed
APPLICATIONS
The low phase shift of the OPA633 allows its use inside
the feedback loop of a wide variety of op amps. To
assure stability, the buffer must not add significant phase
shift to the loop at the gain crossing frequency of the
circuit-the frequency at which the open loop gain of the
op amp is equal to the closed loop gain of the application.
The OPA633 has a typical phase shift ofless than 10° up
to 70MHz, thus making it useful-even with wide band op
amps.
CIRCU~TS
+15V
!I
'"'~ 0."-,,, I
VO UT
OU,O'l
Termination " .
~15V
LARGE SIGNAL RESPONSE
10V STEP - R, = 1000
10V STEP - R,= 1kO
10ns/div
10ns/dill
SMALL SIGNAL RESPONSE
0.5V STEP - R, = 1000
0.5V
V'N
0.5V
VOUT
o
FIGURE I. Dynamic Response Test Circuit.
35
POSITIVE PULSE RESPONSE
100mV
VON
+12V
50mV
VOUT
R,
500
o
RG-58
Coaxial Cable
o
VON
-100mV
o
VOUT
-50mV
FIGURE 2. Coaxial Cable Driver Circuit.
R,
R,
R,
1kO
G=-10
FIGURE 4. Buffered Inverting Amplifier.
FIGURE 3. Precision High Current Buffer.
+Vs
+Vs
(a)
(b)
1000
Inpui
1000
-Vs
-Vs
FIGURE 5. Output Protection Circuits.
36
NOTE: The prototype circuit board layout shown
may be used to test many common applications
circuits. Component designations in the applications
circuit diagrms refer to the component positions on
this prototype board layout.
FIGURE 6. Prototype Circuit Board Layout.
37
BURR-BROWN®
OPA2111
IElElI
NEW PACKAGE
NOW AVAILABLE
Dual Low Noise Precision
Di/e'® OPERATIONAL AMPLIFIER
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
LOW
LOW
LOW
LOW
HIGH
HIGH
NOISE: 1011% tested: BnV/v'Hz max at 10kHz
BIAS CURRENT: 4pA max
OFFSET: 5110pV max
DRIFT: 2.8tlV/oC
OPEN LOOP GAIN: 114dB min
COMMON·MODE REJECTION: 96dB min
PRECISION INSTRUMENTATION
DATA ACQUISITION
TEST EQUIPMENT
PROFESSIONAL AUDIO EQUIPMENT
MEDICAL EQUIPMENT
DETECTOR ARRAYS
DESCRIPTION
The OPA2111 is a high precision monolithic
Dire' (dielectrically isolated FET) operational
amplifier. Outstanding performance characteristics
allow its use in the most "critical instrumentation
applications.
Noise, bias current, voltage offset, drift, open-loop
gain, common-mode rejection, and power supply
rejection are superior to BIFET® amplifiers.
Very-low bias current is obtained by dielectric isolation with on-chip guarding.
Laser trimming of thin-film resistors gives very-low
offset and drift. Extremely-low noise is achieved
with new circuit design techniques (patent pending).
A new'cascode design allowshigh precision input
specifications and reduced susceptibility to flicker
noise.
Standard dual op-amp pin configuration allows
upgrading of existing designs to higher performance
levels.
·PATENT PENDING
-Vee
OPA2111 SIMPLIFIED CIRCUIT
(EACH AMPLIFIER)
BIFET@ National Semiconductor Corp., Dife,e Burr-Brown Corp.
International AIrport IndustrIal Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. (602) 7411-1111· Twx: 910.952·1111 . Cable: BBRCORp· Telex: 66·6491
PDS-S40B (abbreviated)
38
SPECIFICATIONS
ELECTRICAL
At Vee
=::
±15VDC and T"
= +25°C unless otherwise noted.
OPA2111AM
PARAMETER
CONDITIONS
MIN
OPA2111BM
TYP
MAX
40
15
'8
6
0.7
1.6
15
0.8
I MIN
OPA2111SM
TYP
MAX
80
40
15
8
1.2
3,3
24
1,3
30
11
7
6
0,6
1,2
12·
0.6
±0.1
±2
±1
110
±3
136
±0,75
±6
VCM = OVDC
±2
±1
VCM = OVDC
±1,2
MIN
OPA2111KM/KP
TYP
MAX
60
30
12
8
1.0
2,5
19
1.0
40
15
8
6
0,7
1.6
15
0,8
80
40
15
8
1.2
3.3
24
1,0
40
15
8
6
0.7
1.6
t5
0,8
±O,05
±0,5
±O,5
1'10
±3
136
±O,5
±2.8
±0.1
±2
2
110
±3
136
±O,75
±6
±O,3
±8
2
110
±3
136
±2
±15
±8
±1.2
±O,5
±4
±2
±1
±8
±3
2
±15
pA
pA
±6
±O,6
±3
±1,2
±6
±3
±12
pA
MIN
TYP
MAX
UNITS
INPUT
NOISE
Vollage. 10 = 10Hz
Max: 100% tested
Max: 100% tested
Max: 100% tested
=
fa
100Hz
fa = 1kHz
fa :: 10kHz
I,
= 10Hz to 10kHz'
fu
= a.1Hz to 10Hz
Current, f8
10
~·O.1Hz
= 0.1Hz
'"
'"
'"
'"
to 10Hz
'"
to 20kHz
OFFSET VOLTAGE'"
Input Ollset Voltage
Average Drift
Match
Supply Rejection
Channel Separation
BIAS CURRENT'"
Initial Bias Current
Match
OFFSET CURRENT'"
Input Offset Current
VCM
TA
= OVDC
::: TMIN
to TMA)(
90
100Hz. R,
= 2kCl
IMPEDANCE
Differential
96
±31
10"111
10"113
Common-Mode
90
:t16
10"111
10"113
86
±31
10"111
10"113
nVIJHz
nVIJHz
nVIJHz
nVIJHz
pV, rms
I'V. p-p
IA. p-p
fA/JHz
mV
I'VI·C
I'v/·C
dB
±50
I'V/v
dB
10"111
10"113
Cl II pF
Cl II pF
±10
82
±11
110
dB
106
125
3
dB
dB
2
32
2
6
10
2
32
2
6
10
VIpS
5
5
I'S
±12
±10
100
1000
40
mA
0
pF
mA
VOLTAGE RANGE
Common-Mode Input Range
Common-Mode Rejection
V'N = ±10VDC
±10
90
±11
110
110
125
3
±10
±11
96
±10
110
±11
90
110
V
OPEN-LOOP GAIN. DC
Open-Loop Voltage Gain
Match
R,~
2kCl
114
125
2
110
125
3
FREQUENCY RESPONSE
Unity Gain. Small Signal
Full Power Response
Slew Rate
Settling Time, 0.1%
0.01%
Overload Recovery,
50% Overdrive l3J
20V P-P. R, = 2kCl
Vo = ±10V. R, = 2kCl
Gain = -1, RL = 2kO
10V step
16
1
Gain =-1
2
32
2
6
10
16
1
5
2
32
2
6
10
16
1
5
MHz
kHz
I's
I'S
RAT,ED OUTPUT
Voltage Output
Current Output
Output Resistance
Load Capacitance Stability
Short Circuit Current
R,= 2kCl
Vo= ±lOVDC
DC, open loop
Gain = +1
±11
±5
10
±12
±10
100
1000
40
±11
±5
10
±12
±10
100
1000
40
±11
±5
10
±12
±10
100
1000
40
±11
±5
10
V
POWER SUPPLY
Rated Voltage
±15
±15
vec
±15
±15
Voltage Range.
Derated Performance
Current, Quiescent
±5
10 = OmADC
5
±18
7
±5
+85
+125
+150
-25
-40
-65
5
±18
7
±5
+85
+85
+150
-55
-55
-65
5
±18
7
±5
+125
+125
+150
0
-40
-40
±18
5
9
VDC
mA
+70
+85
+85
·C
·C
·C
TEMPERATURE RANGE
Specification
Operating
Storage
(J Junction-Ambient
Ambient temp.
Ambient temp.
Ambient temp.
-25
-55
-65
200
200
200
20044'
·C/W
NOTES: (1) Sample tested-maximum parameters are guaranteed. (2) Offset voltage, offset current, and bias current are measured with the units fully warmed
up. (3) Overload recovery is defined as the time required for the output to return from saturation to linear operation following the removal of a 50% input
overdrive, (4) Typical9J -A = 150'C/W lor plastiC DIP,
39
ELECTRI.CAL (FULL TEMPERATURE RANGE SPECIFICATIONS)
At Vee = ±15VDC and
1,,= TMIN to TUAX unless otherwise noted.
OPA2111AM
PARAMETER
CONDITIONS
MIN
Ambient temp.
-25
TYP
OPA2111BM
MAX
MIN
+85
-25
TYP
OPA2111KM/KP
OPA2111SM
MAX
MIN
+85
-55
TYP
MAX
MIN
+125
0
TYP
MAX
UNITS
+70
'C
±0.9
±8
2
100
±10
±5
±15
mV
1lV/'C
1lV/'C
±80
IlV/V
TEMPERATURE RANGE
Specification Range
INPUT
I
OFFSET VOLTAGE'"
Input Offset Voltage
Average Drift
Match
Supply Rejection
BIAS CURRENT'"
Initial Bias Current
Match
OFFSET CURRENT'"
Input Offset Current
VOLTAGE RANGE
Common-Mode Input Range
Common-Mode Rejection
VCM = OVDC
±0.22
±2
1
100
±10
±1.2
±6
VCM = OVDC
±125
60
VCM = OVDC
±75
.86
±0.08
±0.5
0.5
100
±10
±0.75
±2.8
±lnA
±75
30
±500
±2.0nA ±16.3nA
InA
±125
±500
pA
pA
±750
±38
±375
±1.3nA ±12nA
±75
±375
pA
90
±50
±0.3
±2
2
100
±10
86
±32
±1.5
±6
82
±50
dB
V'N = ±10VDC
±10
86
±11
100
±10
90
±11
100
±10
86
±11
100
±10
80
±11
100
dB
V
RL 2: 2kO
106
120
5
110
120
3
106
120
5
"00
120
5
dB
dB
RL = 2kO
Vo =±10VDC
Vo= OVDC
±10.5
±5
10
±11
±10
40
±10.5
±5
10
±11
±10
40
±10.5
±5
10
±11
±10
40
±10.5
±5
16
±11
±10
40
V
rnA
rnA
OPEN-LOOP GAIN, DC
Open-Loop Vollage Gain
Match
RATED OUTPUT
Voltage Output .
Current Output
Short Circuit Current
POWER SUPPLY
Current. Quiescent
NOTES:
lo=OmADC
5
8
5
8
5
8
(1) Offset voltage, offset current, and bias current are measured with the units fully warmed up.
CONNECTION DIAGRAMS
'M' Package-Top View
ORDERING INFORMATION
-InA
T
OPA2111 () ()
=
Basic model number-_ _ _ _ _.....:=r-=·
Performance grade - - - -_ _ _ _ _ _-'_
A, B = -25'C to +85'C
S
= -55'C to +125'C
K = O'C to +70'C
Package Code _ _ _ _ _ _ _ _ _ _ _ _ _.J
M = TO-99 metal can
P = Plastic DIP
'p' Package-Top View
ABSOLUTE MAXIMUM RATINGS
Supply ................................................. ±18VDC
Internal Power Dissipation (TJ::; +175°C) ............... t.. 500mW
Differential Input Voltage ................................ Total Vee
Input Voltage Range ........................................ ±Vee
Storage Temperature Range ......•........•....• -65'C to +150'C'
Operating Temperature Range ................... -55'C to +125'C
Lead Temperature (soldering, 10 seconds) ................. +300'C
Output Short Circuit to ground (+25'C) ..•....•....•.. Continuous
Junction Temperature ................................. : .. +F5°C
40
+VCC And Case
5
10
rnA
MECHANICAL
'P' Package-Plastic DIP
'M' Package- TO-99 (Hermetic)
•¥'
,.'
T
1
M.;.
.,
+
~
,.;;
"~~]
~
,
~!l\
-.~
N
J
~
F::j
Ii
~
D
E
F
G
H
J
K
L
M
N
IIIII
--1
!
1
--B.- D
MAX
MIN
MAX
.335
.370
.305
.335
.185
.165
.C2i
.CHi
.040
.010
.010
.040
.200 BASIC
.034
.028
.045
.029
.500
.160
.110
45° BASIC
.105
.095
8.51
7.75
4.19
9.40
8.51
4.70
O.~1
O.~3
-
12.7
2.79
4.06
45° BASIC
DIM
A
. A,
B
B,
C
0
MAX
MIN
MAX
9.02
8.65
10.16
~
L
M.
N
p
Sea long Plane
MILLIMETERS
.355
.400
.340
.385
.230
.290
.200
.250
.120
.200
.015
.... ...
.030
.070
.100 BASIC
.025
.050
.015
.008
.150
.070
.300 BASIC
IS'
.0°
.010
.030
.025
.050
MIN
F
G
H
J
K
2.67
2.41
D G
INCHES
..\\..J
C
!J!,. [
!
jl
H
NOTE: Leads in true
position within 0.01"
(0.25mm) R al MMC al
seating plane. Pin numbers
shc'.'m for referenco::- onl~l .
Numbers may not be
marked on package. Pin
material and plating
composition conform to
Melhod 2003 (solderabilily)
of MIL-STD-883 (excepl
paragraph 3.2) .
0.25
1.02
1.02
0.25
5.08 BASIC
0.86
0.71
1.14
0.74
j
-J I.M
1fm~
MILLIMETERS
INCHES
MIN
DIM
A
B
C
1"----1
Pin 1
1.1[~
Sealing
Plane
~
5.85
9.80
7.38
5.09
6.36
3.05
5.09
O.~S
0.59
0.76
1.78
2.54 BASIC
0.64
1.27
0.201 0.38
1.713
3.82
7.63 BASIC
0°
W
0.25
0.76
0.64
1.27
NOTE: Leads in true
position within 0,01"
(O.25mm) R al MMC al
seating plane. Pin numbers
shown for reference only.
Numbers may not be
marked on package. Pin
material and plating
composition conform to
Melhod 2003 (solderabilily)
of MIL-STD-883 (excepl
paragraph 3.2).
TYPICAL PERFORMANCE CURVES
TA
= +25°C, Vee = ±15VOC unless otherwise noted.
~
~
VOLTAGE AND CU.RRENT NOISE SPECTRAL
DENSITY vs TEMPERATURE
12 r---~--~--~--~--~--~--~~100
INPUT CURRENT NOISE SPECTRAL DENSITY
100
~:>
10
10
Eo
ill
z
·0
'I
E
~
~
·0
2
V
~
S
::I
0
0
>
If
,~,
0.1
10
4
100
lk
10k
lOOk
1M
TOTAL' INPUT VOLTAGE NOISE SPECTRAL
DENSITY vs SOURCE RESISTANCE
lk
Rs
~:;;
..
,
l1li
R.
.!!!
I
0
Z
"'"
tJ
100
.:.
S
'0
10Mcj
I
10
>
-Includes contribution
from source resistance
0.1
10
I
lookn
III I I
i.JliU
I'
R. lOOn
BM
: Ilil I
I 1111 i
I
100
lk
10k
-50
-25
-25
-50
Temperature (OC)
- 75
-100
-125
NOTE:
Refer to complete data sheet
PDS-540 for complete typical
curves and applications information .
'JIJ
I
1
, Rs ' lMn -t
,
0.Q1
-75
Frequency (Hz)
lOOk
Frequency (Hz)
41
BURR-BROWN@
INA102
11:31:31
Low Power
High Accuracy
INSTRUMENTATION AMPLIFIER
FEATURES
APPLICATIONS
• LOW QUIESCENT CURRENT: 750pA. max
• AMPLIFICATION OF SIGNALS FROM SOURCES
SUCH AS:
Strain Gauges
Thermocouples
RTOs
• INTERNAL GAINS: X 1. 10. 100. 1000
• LOW GAIN DRIFT: 5ppm/oC. max
• HIGH CMR: 90dB. min
• REMOTE TRANSDUCER AMPLIFIER
• LOW OFFSET VOLTAGE DRIFT: 2pV/oC. mal
• LOW LEVEL SIGNAL AMPLIFIER
• LOW OFFSET VOLTAGE: 100pV. max
• MEDICAL INSTRUMENTATION
• LOW NONLlN.EARITY: 0.01%. max
• MULTICHANNEL- SYSTEMS
• HIGH INPUT IMPEDANCE: 101°0
• BATTERY POWERED EQUIPMENT
• LOW COST
DESCRIPTION
The INAI02 is a high-accuracy monolithic instrumentation amplifier designed for signal conditioning
applications where low quiescent power is desired.
On-chip thin-film resistors provide excellent temperature and stability performance. State-of-the-art
laser trimming technology insures high gain accuracy and common-mode rejection while avoiding
expensive external components. These features make
the INAI02 ideally suited for b'attery powered and
high volume applications.
The INAI02 is also convenient to use. A gain of I.
10, 100, or 1000 may be selected by simply strapping
the appropriate pins together. 5ppm/oC gain drift in
low gains can then be achieved without external
adjustment. When higher than specified CMR is
required, CMR can be trimmed using the pins provided. In addition. balanced filtering can be accomplished in the output stage.
OFFSET
ADJUST
ALTER
-INI1l"~--...p..
+IN@15J--,--iY'
+Vcc -Vee
CMR
TRIM
International Airport Industrial Park· P,O. Box 11400 - Tucson. Arizona 85734 - T81.(602) 746-11 11 - Twx: 910-952-11 11 • Cable: BBRCORP - Telex: 66-6491
PDS-523A
42
SPECIFICATIONS
ELECTRICAL
At T.; +25"C with ±15VDC power supply and in circuit of Figure 2 unless otherwise noted.
MODEL
INA102AG
CONDITIONS
MIN
GAIN
Range of Gain
Gain Equation
Error. DC: G
TYP
MIN TYP
INA102KP
MAX
MIN
TYP
1000
MAX
UNITS
1000
VN
VN
0.15
0.35
0.4
0.9
%
%
%
%
%
%
%
%
G=1+
=1
(40k/RG)11I
= +25"'C
= +25"'C
0.05
0.05
0.15
0.5
T,,=TMINtoTMAX
0.1
0.1
0.25
0.75
0.16
0.19
0.37
0.93
T... = +25°C
T... = +25"'C
T... =+25"'C
T... = +25°C
10
15
20
30
0.03
0.03
0.05
0.1
5
10
15
20
T...
T...
T... =
T... =
G=10
G=100
G = 1000
+25"'C
+25"'C
T ... = TMIN to TM.u:
T... =TMINtoTMAX
G=1
G;10
G=100
G = 1000
T... = T.,m~ to TM,u,
Gain Temp. Coefficient
G=1
G=10
G=100
G = 1000
Nonlinearity, DC: G=1
G=10
G=100
G =1000
=
to TM4X
G=1
T...
G=10
G=100
G = 1000
T" = TM,N to TMAX
- -- -
.....--- ...............
...... ..
..........
INA1Q2CG
MAX
Voltage
Current
Short-Circuit Current
Output Impedance: G = 1000
TMIN
T,,=TMINtoTMAX
= 10kCl
0.21
0.44
0.11
0.21
0.62
0.52
1.08
ppm/DC
ppm/DC
ppm/Ole
ppm/DC
%ofFS
0/0 of FS
%ofFS
%ofFS
%ofFS
%ofFS
OfoofFS
%ofFS
0.01
0.Q1
0.02
0.05
0.015
0.015
0.03
0.1
0.045
0.045
0.075
0.15
TA,=TM1NtoTMAX
R..
o.oa
±(lV",I-2.5)
±(lV",I-3.5)
±1
V
mA
mA
2
0.1
n
INPUT
OFFSET VOLTAGE
InitialOffsetl21
vs Temperature
vs Supply
vsTlme
T,,=+25"C
±(20 + 30/G)
±300±300/G
±5.±10/G
±40±50/G
±100±200/G
50
30
±400 ±700/G
±2±5IG
±10±20/G
"V
pVl"C
pVIV
pVlmo
BIAS CURRENT
Initial Bias Current (each input)
vs Temperature
vs Supply
Initial Offset Current
vs Temperature
T" = TMIN to TMAX
nN"C
±0.1
nNV
nA
±15
±2.5
±0.1
T" = TMIN to TMAX
nA
±O.1
±2.5
±10
nN"C
IMPEDANCE
nil
nil
10'0112
10'0112
Differential
Common·mode
pF
pF
VOLTAGE RANGE
Range, Linear Response
CMR with 1kCl Source Imbalance
G=1
G=10
G = 1010 1000
T,,=TMINtoTMAX
±(lV•• 1-3.51
DC 10 60Hz
DC 10 60Hz
DC to 60Hz
80
80
80
V
±(lV""I-2.5)
94
100
100
90
90
90
94
60
84
100
dB
dB
dB
NOISE
Input Voltage Noise
fa = O.01Hz to 10Hz
Density. G = 1000
= 10Hz
fo = 100Hz
fo = 1kHz
Input Current Noise
fa = O.01Hz to 10Hz
Density: fo = 10Hz
fo = 100Hz
fo = 1kHz
pV, p.p
0.1
'0
.
30
25
25
nVl.,fH'i
nVl..JHZ
nVl.,fH'i
pA. p-p
25
0.3
0.2
0.15
pN.,fH'i
pN.,fH'i
pN.,fH'i
300
30
3
0.3
kHz
kHz
kHz
kHz
30
3
0.3
0.03
2.5
0.15
kHz
kHz
kHz
kHz
kHz
Vlpsec
50
360
3300
80
500
4500
psec
psec
psec
psec
psec
psec
DYNAMIC RESPONSE
Small Signal, ±3dB Flatness
VOUT - 0.1Vrms
G=1
G=10
G=100
G =1000
Small Signal, ±1% Flatness
G=1
G=10
G=I00
G;I000
Full Power, G =:= 1 to 100
Slew Rate, G = 1 to 100
Settling Time, 0.1%:
G=1
G = 100
G; 1000
Settling Time, 0.01%: G = 1
G = 100
G = 1000
VOUT = 0.1Vrms
=
=
=
=
=
=
VQ4JT 10Y. AL 10kO
YOUT 10Y. RL 10kn
RL 10kO. Ct. 100pF
10V step
10V slep
1.7
0.1
43
ELECTRICAL (CO NT)
MODEL
UNITS
POWER SUPPLY
v
Rated Voltage
Voltage Range
Quiescent Current f31
V
~A
TEMPERATURE RANGE
·c
Specification
Operation
Storage
·C
·C
'Specifications same a~ for INA102AG.
NOTES: (1) The internal gain set resistors have an a~solute tolerance of ±20%; however, their tracking is 50ppmrC. RG will add to the gain error if gains other than 1,
10.100 or 1000 are set externally. (2) Adjustable to zero at anyone time.
MECHANICAL
Hermetic
~,~[ ~ ~]~:I
I--.-F-t
AAAAAA
t-- I
N=.l---.i
rntmtd
H
~ G l-
.""Y""vvv,"
,
Pin 1
-iF(~
DIM
A
C
at seating plane.
D
F
Pin numbers shown, for reference
only. Numbers are not marked on
G
package.
J~
&.-L--IM
Seating Plane
NOTE: Leads in true position
within .010" (.2Smm) R
~
11===n
j'j
p;r
-n.~.
A.----t
--I L
Plastic
~-:,=-----~
H
J
K
L
M
N
[lUB"
-
MILLIMETERS
MIN
MAX
20.07
20.57
4.32
2.67
0.53
0.38
1.52
1.22
2.54 BASIC
0.76
'.78
0.20
0.30
3.05
6.'0
7.62 BASIC
10'
1.52
0.64
INCHES
MAX
MIN
.790
.8'0
.105
.170
.02'
.0'5
.048
.060
.'00 BASIC
.030
.070
.008
.0'2
.240
.120
.300 BASIC
'0'
.025
.060
DIM
A
A,
B
10- H
Seating Plan] B,
C
D
NqTE: Leads in true position
F
within .010" (.2Smm) R at MMC at
G
seating plane.
PINS: Pin material and plating
. composition conform to method
20D3 (solderability) of MIL-STD~
883 (except paragraph 3.2).
CASE: Plastic
H
J
K
L
M
N
P
M
INCHES
MIN
MAX
.740
.800
.725
.785
.230
.290
.200
.250
.200
.'20
.023
.0'5
.070
.030
.'00 BASIC
0.05
0.02
.015
.008
.070
.'50
.3ODBASIC
O·
'5'
.030
.0'0
.025
.050
jlJ
MILLIMETERS
MIN
MAX
20.32
'8.80
18.42
'9.94
5.85
7.38
5.09
6.36
3.05
5.09
0.38
0.59
0.76
'.78
2.54 BASIC
0.5'
'27
0.20
0.38
1.78
3.82
7.63 BASIC
0'
'5'
0.25
0.76
1.27
0.64
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
OFFSET ADJUST ~
XIO GAINI 2
Supply .................................................... ±IBV
Input Voltage Range ........................................ ±Vee
Operating' Temperature Range ••.••••••••.•••••••• -2S·C to +B5°C
XIOOGAIN~
Storage Temperature Range: Ceramic ........... '. -65°C to +150°C
Plastic ......... : ... -SS'C to +12S·C
Lead Temperature (soldering 10 seconds) •.•••••••••.•••.•• +300·C
XI 000 GAIN I 4
XIOOO GAIN
SENSE >!C
GAIN SENSE ~
GAIN SET 7
>t
Output Short-Circuit Duration .............. Continuous to ground
ORDERING INFORMATION
INA102
Basic Model Number _ _ _ _ _ _ _ _ _ _ _
-=r--J
CMR TRIM (':
T
X
G
Performarice Grade Code - -_ _ _ _ _ _ _ _ _--'_
A. C: -2S·C to +BS·C
K: O·C to +70·C
Package Code - - - - - - - - - - - - - - - - - - '
G: 16-pin Hermetic DIP
P: 16-pin Plastic DIP
INA102AG. !NA102CG, INA102KP
44
~ OFFSET ADJUST
~+IN
14 -IN
~FILTER
12
+Vco
~OUTPUT
>i: COMMON
>;c
-Vee
BURR-BROWN®
IElElI
INA106
~
~
~
j':,
I~I
1
I,
,
I
Precision Fixed-Gain
DIFFERENTIAL AMPLIFIER
APPLICATIONS
FEATURES
.•
•
•
•
•
•
•
•
•
• DIFFERENTIAL AMPLIFIER. A = 10
• BASIC INSTRUMENTATION AMPLIFIER BUILDING
BLOCK
• INVERTING AMPLIFIER. A = -10
• NONINVERTING AMPLIFIER. A = 10
• SUMMING AMPLIFIER. WEIGHTED
• ±100V CM'RANGE DIFFERENTIAL AMPLIFIER
F!X~!! BAl"'. A = 10
CMR 100dB min over temp
NONLINEARITY 0.001% max
NO EXTERNAL ADJUSTMENTS REQUIRED
EASY TO USE
COMPLETE SOLUTION
HIGHLY VERSATILE
LOW COST
TO·99 HERMETIC METAL AND LOW COST PLASTIC
PACKAGES
DES'CRIPTION
The IN A106 is a precision fixed-gain differential
amplifier. As a monolithic circuit, it offc:rs high reliability at low cost. It consists of a premium grade
operational amplifier and an on-chip precision resistor network.
The INA106 is completely self-contained and offers
the user a highly versatile function. No adjustments
to gain, offset, and CMR are necessary. This pro·
vides three important advantages: (I) lower initial
design engineering time, (2) lower manufacturing
assembly time and cost, and (3) easy cost-effective
field repair of a precision circuit.
,r;-.,
- ln
10kO
100kO
Ir.\
0J-.N.r
--r~sense
R, -L-~_~R2
_ .............
,.-----I~ +Vcc
">----I'~ Output
r~
~-."
+In f'3IJ--'lR
,."............._ _..J\IIR.IV-_ _-r1f'0. Reference
o \.::J
10kO
100kO
f-..!J
Inlernallonal Alrpon Industrial Park • P.O. Box 11400 • Tucson. Arizona B5734 • Tel.: (602) 741HII1 • Twx: 910·952·1111 • Cable: BBRCORP • Telex: 66-6491
PDS·729A·
45
SPECIFICATIONS
ELECTRICAL
At +25°C, Vee = ±15V unless otherwise noted.
INA106AM
CONDITIONS
PARAMETER
MIN
GAIN
Initial lll
Error
vs Temperature
Nonlinearityl21
OUTPUT
Rated Voltage
Rated Cu rrent
Impedance
Current Limit
Capacitive Load
10 = +20mA, -5mA
10
+20, -5
Eo=10V
Differential
Common-mode
Differential
Common-mode
Voltage Range
OFFSET VOLTAGE
Initial
vs Temperature
vs Supply
vs Time
12
100
30
2
V9 = 10V step
Vo = 10V step
VCM
== 10V step. V01FF == OV
100
5
10
5
50
3
5
10
5
TEMPERATURE RANGE
Specification
Operation
Storage
±5
±18
±2
±1.5
-25
-55
-65
+85
+125
+150
..
Speclflcallon same as for INA106AM.
TYP
MAX
106
0.025
·
UNITS
VN
%
ppmloC
%
V
rnA
Q
rnA
pF
kQ
kQ
V
V
dB
86
200
·
2
. ±15
Derated performance
VOUT=OV
.MIN
·· ·
·
·· ··
··
·· ·
·· ··
··
··
·
··
··
··
··
·
·· ·
·
·
·· ·
··
··
··
·· ···
·· ···
··
··
·
·
· ·· ·· · ··
···
···
100
1
30
-3dB
Vo=20V p-p
INA106KP
MAX
0.01
RTI 'S)
OUTPUT NOISE VOLTAGE
F, = O.OIHz to 10Hz
Fo = 10kHz
POWER SUPPLY
Rated
Voltage Range
Quiescent Current
0.01
±10
0.001
50
0.2
1
10
±Vcc = 6V to 18V
DYNAMIC RESPONSE
Gain Bandwidth
Full Power BW
Slew Rate
Settling Time: 0.1 %
0.01%
0.01%
10
0.005
-4
0.0002
. TYP
MIN
10
110
±1
±11
94
T... == TMIN to TMAX
RTI141
Common .. mode Rejection l31
MAX
0.01
+401-10
1000
To common
Stable operation
INPUT
Impedance
INA106BM
TYP
pV
"V/oC
pVN
"Vlmo
"Vp-p
nVIy'Hz
MHz
.kHz
Yips
ps
ps
ps
0
-25
-40
··
rnA
+70
+85
+85
°C
°C
°C
V
V·
NOTES: (1) Connected as difference amplifier (see Figure 4). (2) Nonlinearity is the maximum peak deviation from the best-fit straight line as a percent oflull-scale
peak-to-peak output. (3) With zero source impedance (see Maintaining CMR section). (4) Includes effects of amplifier's input bias and offset currents.
(5) Includes effects of amplifier's input current noise anp thermal noise contribution of resistor network.
MECHANICAL
TO-99 Package
"P" Package-Plastic DIP
NOTE: Leads in true position
within 0.01" (0.25 mm) R at MMC at
seating plane.
!t=~::fl
L.JL J
~I!!!!
I
C
FJ
!
I
Seatingm
Plane
0
DIM
A
B
C
0
E
~
~~l1=~-'
~
··i
G
:'~
g
Pin numbers shown for reference
only. Numbers are not marked on
package.
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
.335
.370
.305
.335
.165
.185
.016
.021
.010
.040
.010
.040
.200 BASIC
.028
.034
.029
.045
.500
.110
.160
45' BASIC
.095
.105
8.51
9:40
7.75
8.51
4.19
4.70
0.41
0.53
0.25
1.02
0.25
1.02
5.08 BASIC
0.71
0.86
0.74
1.14
12.7
2.78
4.06
45 0 BASIC
2.41
2.67
==:U
P
F
Pln1--i
DIM
Cd
"~1 ~F.L
Seating
Pls.ne
46
NOTE: Leads in true position
within 0.01" (0.25mm) Rat MMC
at sea~ing plane. Pin material and
plating composition conform to
Method 2003 (solderability) of MILSTD-B83 (except paragraph 3.2).
B,
C
G
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
.355
.400
.340
.385
.230
.290
.200
.250
.120
.200
.015
.023
.030
.070
.100 BASIC
.025
.050
.008
.015
.070
.160
.300 BASIC
9.02
10.16
8.64
9.78
5.84
7.37
5.08
6.35
3.05
5.08
0.38
0.58
0.76
1.78
2.54 BASIC
0.64
1.27
0.20
0.38
1.78
3.81
.010
.030
.025
.050
0.25
0.64
7.63 BASIC
M
0.76
1.27
PIN DESIGNATIONS
PIN DESIGNATIONS
TOPYIEW
TOPYIEW
PLASTIC DIP
INA106KP
Reference
1
-In
2
+In
~8
.....
j~
"I
~7
+Vee
~6
Output
5
Sense
-Vee 4
INA106AM
INA106BM
-Yee
Case connected to -VCI:. internally. Make no connection.
ORDERING INFORMATION
Basic Model Number
Perlt)rman~e
NA
_ _ _ _ _ _'=-r-_
...J106
~
ABSOLUTE MAXIMUM RATINGS
Supply .................................................... ±18V
Input Voltage Range •..••.......•..............•......... ±Vcc
Operating Temperature Range: M .......•. -SS'C to +12S'C
P ........... -40'C to +8S'C
Storage Temperature Range .•.....••...... -6S'C to +12S'C
. Lead Temperature (soldering 10 seconds) .........•. +300'C
Output Short Circuit to Common ••.•.•...•.•..•. Continuous
TI
I
IX X
GrE!de
A, B: -2S'C to +8S'C
K: O'C to +70'C
No Internal
Connection
Package Code _ _ _ _ _ _ _ _ _ _ _ _ _-1.
M: TO-99 metal can
P: 8-pin mini plastic DIP
TYPICAL PERFORMANCE CURVES
T.
=25·C. ±Vee =15V unless otherwise noted.
SMALL SIGNAL RESPONSE
(No Load)
STEP RESPONSE
o
4
8
o
16
Time (PO)
~
A = 20dB. 3Vrms, 10ka load
ill
z
-116
-126 t---+-O~-+---1--+---i
-106
"-106 I----''d---+-''~--+--+--_l
E
-100
.,-96
E
II:
II:
+
~ -86
I..I~
c
J: 0.01
I-
10
Frequency (kHz)
8M
.......
P.M.
~
-86
-76
30kHz low p ass
filtered
1
CMR VS FREQUENCY
II:
1-:---I--..3o,.......--+~
Inverting
0.001
10
POWER SUPPLY REJECTION
tt
'0
5
Time (PO)
-146 .-_--.---..,;V;,::S:.,;F...R.:.;E;,::Q;,::U;,::E:;.N.:.;C:.,;Y_-r-_--,
I Noninverting""
0.1
a
10
Time (PO)
TOTAL HARMONIC DISTORTION AND NOISE
VS FREQUENCY
=
5
SMALL SIGNAL RESPONSE
(RLOAD = 000, CLOAD = l000pF)
~6
100
10
Frequency (Hz)
47
I(P
~
\
\
lk
lOa
10k
Frequency (Hz)
\
lOOk
TYPICAL PERFORMANCE CURVES (CO NT)
T. = +25°C, Vee = ±15VDC unless otherWise noted.
MAXIMUM
VOUT
VS
MAXIMUM You, VS lou,
(Negative Swing)
lOUT
(positive Swing)
17.5
IVa
15
12.5
=
"'=
~
10 I - -
B
>
7.5
=~18VI
t-115V
-17.5
-
Va - ±18V
-15
-12.5 I - - -VSI ±lr
-L=Lv
~ -10 -
J
-
Vs
±12V
-7.5
-5
5
Va = ±5V
2.5
o
S
12
18
-2.5
24
30
36
-
I- Vi-±r
-2
4
10
S
12
-lOUT (rnA)
lOUT (rnA)
DISCUSSION OF
PERFORMANCE
BASIC POWER SUPPLY AND SIGNAL
CONNECTIONS
OFFSET ADJUSTMENT
Figure I shows the proper connections for power supply
and signal. Supplies should be decoupled with I/LF tantalum capacitors as c.lose to the amplifier as possible. To
avoid gain and CMR errors introduced by the external
circuit, connect grounds as indicated, being sure to minimize ground resistance.
Figure 2 shows the offset adjustment circuit for the
INAI06. This circuit will allow ±3mV of adjustment and
will not affect the gain accuracy or CMR.
r-----------l
I
INA10S
I
Is
R,
R.
I
I
I
I
I
I
100
R,
6VIN
R,
I
I
I
t
I
I
I
is
Eo
1
I
I
I
3:
E.
•
I
21
I
R,
1
R,
:
+15V
L_ ---1.-_-_-_'i.,9;..,.k~;;------J_!100kCl
VOUT
l
Eo = E. - E1
Offset Adjustment
Range = ±3mV
Ve
1000
-15V
FIGURE 2. Offset Adjustment.
FIGURE I. Basic Power Supply and Signal
Connections.
MAINTAINING COMMON-MODE REJECTION
Two factors are important iJ;l maintaining high CMR: (I)
resistor matching and tracking (the internal INAI06 circuitry does this for the user) and (2) source impedance
including it~ imbalance.
48
Referring to Figure I, the CMR depends upon the match
of the internal R4/R3 ratio to the RI/R2 ratio. A CMR
of 106dB requires resistor matching of 0.005%. To maintain 100dB, minimum CMR to +8S oC, the resistor TCR
tracking must be better than 2ppm/ DC. These accuracies
are difficult and expensive to reliably achieve with discrete components.
Any source impedance adds directly to the input resistors, RI and R3, and will degrade DC and AC CMR.
Likewise any wiring resistance adds directly to any of the
precision difference resistors. A resistance of 0.50
(0.005% of 10kO) will degrade the I06dB CMR of the
INAI06; SO will degrade the CMR to 86dB.
When input filters are used preceding an instrumentation amplifier, care should also be taken to match RCs
on the two input lines. For example, mismatched input
filters for high frequencies will reduce the CMR at lower
frequencies, e.g, 60Hz. Differential filters will not degrade
ACCMR.
Adding as the root of the sums squared,
END = 193nV VHZ
RTI, with A = 10,
ENI = 19.3nV/VHZ
For example,
END within a
600kHz BW = O.lsmVRMs
= 0.9mVp-p with a crest factor of 6
(statistically includes 99.7% of all
noise peak occurrences)
This is the noise due to the resist~rs alone. It is included
in the noise specification of the INAI06.
APPUCATIONS CIRCUITS
The INAI06 is ideally suited for a wide range of circuit
functions. The following figures show many applications
circuits.
I
RESISTOR NOISE IN THE INA106
Figure 3 shows the model for calculating resist.or TlOisp, i.n
the INAI06. Resistors ~ave Johnson noise resulting from
thermal agitation. The expression for this noise is:
Where: K =
T =
R =
B=
r----------•
R,
INA106
R~·
., I
-I
-In
E,
ERMs = v'4KTRB
Boltzman's constant (J/oK)
Absolute temperature (OK)
Resistance (0)
Bandwidth (Hz)
R,
I
I
I
I
I
I
I
R,
100kO
I
I
I
31
+In
E,
I"
I~
10kO
I
16
I
I
R,
Out
Eo
11
10kO
100kO
IL _
______
_ _ _JI
Eo = 10 (E. - E, )
Gain Error = 0.005%
CMR= 106dB
Nonlinearity = 0.0002%
FIGURE 4A. Precision Difference Amplifier.
>--_--oENO
R,II R.
E,
EN,
o--'lM'-=7-_""'-----'W.--~~M--i Gain
100
10kO
Adjust
Eo
FIGURE 3. Resistor Noise ModeL
At room temperature, this noise becomes:
EN = 1.3- 10
The three noise sources in Figure 2 are:
v'R
100
(V/VHZ)
To eliminate adjustment interactions,
first adjust gain with E. grounded.
ENI = 1.3- 10 (R2/RI) y'R;
EN2 = 1.3- 10 y'R;
EN3
=
FIGURE 4B. Difference Amplifier With Gain And
CMR Adjust.
1.3- 10 (1 + R2/R 1) v'R311R4
49
-,
r-----------,
2',
:5
,,
,
,,
I
R.
, R.
INA106
15
I
1
I
16
> .........1.........---0 ~
31
I
I
3'
1
R.
I
10kCl
IL ______
l~kn
--1
Eo = 10 (1 + 2R./R,) (Et - E,)
Eo=10E,
Gain Error,:, 0.01% max
For the ultimate performance high gain instrumentaUon amplifler,the
INA106 can be combined with state-of-the-art op amps. For low
source Impedance applications, an input stage using OPA37s will give
the best low noise, offset, and temperature drift. Alsourca Impedances'
above about10kCl, the bias current noise of the OPA37 reacUng with
the input impedance begins to dominate the noise. For theM appllcalions, using an OPA111 or a dual OPA2111 FET Input op amp will
provide 1000r noise. For an electrometer grade lA, use the OPA128.
(See tabla below.)
FIGURE 7. Precision Noninverting Amplifier with Gain
of 10.
Using the INA108 for the difference amplifier also exlands the input
common-mode renge of the instrumentation amplifier to ±1OV. A,
conventional IA with a unlty-galn differenca amplifier has an input
common-mode range limited to ±5V for an output swing of ±10V. This
is because a unlty-galn diffentnce amp needs ±5Y at the Input for 10Y
at the output, allowing only 5Y additional for common mode.
OPA37A
OPA111B
OPA128LM
>-~-O~
NoM at 111Hz
R,
R.
(kCl)
Gain
(VIV)
CMRR
(Cl)
(dB)
Ib (pA)
(nY/v'Hzj
50.5
202
202
2.5
10
10
1000
1000
1000
128
110
118
40000
,1
0.075
4
10
~=11e,
38
Gain Error = 0.01% maximum
Gain Drift = -4ppmrC
FIGURE S. Precision Instrumentation Amplifier.
FIGURE 8. Precision Noninverting Amplifier with Gain
of n.
r-------- -- ---,
2 ,
INA106
,5
Elo-~~~~--.-----~~----~-,
1
I
,
1
1
1
I
,
,
~~~O~
1
1
I
,I
,6
I
,
1
I
I
I
L__
,
>+16~-o~
I
R.
:.... _______.J
10kCl
1
I
L __________ .JI
E·o-~I~~---
~=~10E,
Gain Error = 0.01% maximum
Nonlinearity = 0.001% maximum
Gain Drift = -4ppm/'C
Eo=E,+10Et
FIGURE 6. Precision Inverting Amplifier with Gain of
FIGURE 9, Precision Summing Amplifier with
Weighted Inputs.
-10.
50
r"R;- INAi"06- R, -
INA106
51 100kn
I
I
I
I
I
I
;-.......;-;1:-<':--00 Eo
E;
16
I
I
10kn
L _______ J
o--+-;y..Iv--9-1
loon
~+'~~~~-~Eo
16
I
I
10
I
I
R,
-,
10kO! 2
I
.¢.
0.22pF
3
Eo= E,
Gain =1/10
Also: Gain = -1/10 by grounding R, and driving R,
Gain = 1110 differential driving both R, and R,.
This circuit follows an 1111 divider with a gain of 11 for an overall gain
of unity. With an 11/1 divider, the input signal can exceed 100V without
exceeding the oJ? amp common-mode range.
The 1000, lOn, 0.22pF network on the output assures stability by
inserting a 70kHz zero and 700kHz pole to decrease the loop gain by
10 at 700kHz. With the output taken at the junction of the loon and Ion
resistors, gain accuracy is maintained, and noise gain at the output
remains at unity. For a 10V output swing, the load should be limited to
10kO since the loon resistor acts as a voltage divider with the load.
AlSO me large signal oanawiatn will De limited DY tile ability oj tile
FIGURE lO. Voltage Follower with Input Protection.
amplifier to slew into the O.22#F capacitor. Assuming 10mA output
r- - -INAios - --,
2110kn
R,
current and a 20Vp-p output Signal, the full power bandwidth will be
1.0kHz. Since the circuit is a 1011 attenuator, this would assume a
200Vp-p Input signal. With a 20Vp-p Input signal, the bandwidth would
be 10kHz.
C,
i5 100pF
I
I
I
16
I
ltr..
Eo
FIGURE 12. Precision Attenuator.
Gain = 20dB
I
I
I
I
I
176n
I
R,
I
100kn
_______
.JI
1,;",
:>-L~----~_()eo
FIGURE II. Differential-Input, Low-Impedance,
Microphone Preamplifier (20dB gain).
80=02-91
Common-Mode Range = ±100V
500n CMR Adjust
(ISSn Nominal) ,
The addition of two external resistors and a pot turns the INA1061nto a
unity-gain difference amplifier with input common-mode range
exceeding ±100V. The circuit requires CMR adjustment and has a 2%
gain accuracy. Better gain accuracy Is difficult to obtain, since CMR
and gain adjustments interact. See Figure 14.
FIGURE 13, ±lOOV Common-Mode Range Difference
Amplifier.
51
1.13kO
A.
,
...---
.
I--+-M~
L __ .J120kO
390kO
:>~--------~~----~~eo
'Optional Gain Adjust
90=e2-81
Common-Mode Aange = ±100V
The add Ilion of an op amp to circuit of Figure 13 can eliminate the
need for CMA and gain adjustments. CMA will be 20dB lower than that
of the INA106. which Is specified in a gain of 10. Gain accuracy is set
strictly by the A•• A, ratio and the Inilial gain accuracy of the INA106
(A = 1 + A./A.±.Ol%). CMA can be adjusted by adding a 100 resistor
In series with A, (pin 2) and a 200 pot In series with A, (pin 2). Gain
and CMR adjustments do not Interact.
FIGURE 14. ±lOOV Common-Mode Range 'Difference
Amplifier Requiring No Adjustments.
52
BURR-BROWN®
INA110
IElElI
Fast-Settling FET-Input
Very High Accuracy
INSTRUMENTATION AMPLIFIER
FEATURES.
APPLICATIONS
•
•
•
•
•
•
•
•
• Fast scanning rate multiplexed Input data acquisition
system amplltier
• Fast differential pulse amplifier
• High speed. low drift gain block
• Amplification of low level signals from high impedance sources and sensors
ct Instrumentation amplifier with input low pass filtering using large series resistors
• Instrumentation amplifier with overvoltage input
protection using large series resistors
• Amplification of signals from strain gauges. thermocouples. andRTDs
LOW BIAS CURRENT: 50pA. max
FAST SETTLING: 4J.1s to 0.01%
HIGH CMR: I06dB. min; 90dB at 10kHz
CONVENIENT INTERNAL GAINS: 1.10.100.200.500
VERY-LOW GAIN DRIFT: 10 to 50ppm/oC
LOW OFFSET DRIFT: 2J.1V/oC
LOW COST
PINOUT COMPATIBLE WITH A0524 AND A0624.
allowing upgrading of many existing applications
DESCRIPTION
The INAIIO is a monolithic FET input instrumentation amplifier with a maximum bias current of
50pA. The circuit provides fast settling of 41'S to
0.01%. Laser trimming guarantees exceptionally good
DC performance. Voltage noise is low, and current
noise is virtually zero. Internal gain set resistors
guarantee high gain accuracy and low gain drift .
. Gains of 1, 10, 100, 200, and 500 are provided.
The inputs are inherently protected by P-channel
FETs on each input. Differential and commonmode voltages should be limited to ±Vcc. When
severe overvoltage exists, use diode clamps as shown
in the application section.
The INAIIO is ideally suited for applications requiring
large input resistors for overvoltage protection or
filtering. Input signals from high source impedances
can easily be handled without degrading DC performance. Fast settling for rapid scanning data
acquisition systems is now achievable with one
component, the INAIIO.
Input
+Vcc
-Vee
Offset
Adjust
Output
Offset
Adjust
• Connect to Ro for desired gain.
International Airport Industrial Park· P.O. Box 11400 . Tucson. Arizona B5734 • Tel. 1602) 746·11 11 . Twx: 9t0-952·1I 11 . Cabte: BBRCORP . Telex: 66·6491
PDS-645A
53
SPECIFICATIONS
ELECTRICAL
At +2S'C, ±Vcc = ISVDC, RL = 2kCl unless otherwise noted.
INAll0AG
PARAMETER
CONDITIONS
MIN
INAll0,BGISG
TYP
MAX
MIN
GAIN
Range 01 Gain
Gain Equation l11
Gain Error, DC: G = 1
G=10
G=100
G=200
G=SOO
Gain Temp. Coefficient: G = 1
G=10
G=I00
G =200
G =,SOO
Nonlinearity, DC: G = 1
G=10
G=I00
G=200
G=SOO
1
I
I
0.002
0.Q1
0.02
0.04
0.1
±3
±4
±6
±10
±2S
±0.001
±O.002
±O.OO4
±0.008
±O.OI
800
0.04
0.1
0.2
0.4
1.0
±20
±20
±40
±eo
,±100
±O.OI
±0.01
±O.02
±0.02
±O.O4
OUTPUT
Voltage, RL = 2kCl
Current
Short-Circuit Current
Capacitive Load
Overtemp
Over temp
±10
±5
Stability
±(100+
l000/G)
·
INA110KPIKU
. ·
I
I
G = 1 + I40KI(R. + SOCl)]
0.02
0.005
O.OS
0.01
0.1
0.02
0.2
0.05
O.S
±10'
±10
±2
±3
±20
±S
±30
±10
±SO
±O.OOOS
±O.OO5
±O.OOI
±0.005
±0.Q1
±O.002
±O.OO3
±0.01
±O.OOS
±O.O2
·
·
±(SO+
8OO/G)
±(SOO+
Sooo/G)
±(2S0+
3000/G)
U
BIAS CURRENT
Initial Bias Current
Initial Offset Current
Impedance: Differential
Common-Mode
VOLTAGE RANGE
Range, Linear Response
CMR with lkCl Source Imbalance:
G=1
G=10
G=100
G=200
G=500
Vcc= ±6V to
±18V
Each input
V1N
±(2+
20/G)
±(4+
60/G)
±(S+
l00/G)
±(30+
3OO/G)
±(1+
10/G)
±(2+
3OIG)
±(2+
SO/G)
±(10+
180/G)
20
2
5Xl012 116
2Xl012 111
100
SO
10
1
SO
25
DC
DC
DC
DC
DC
±10
±12
70
87
100
100
100
90
104
110
110
110
60
98
106
106
106
65
8
-3dB
Vou,=±10V,
RL = 2kCl
G =1 to 100
Vo=20V step
2.5
2.5
470
240
100
190
12
100
112
116
116
116
··
·
··
··
··
·
·· ··
··
··
·
10
1
1.8
DYNAMIC RESPONSE
Slew Rate
Settling Time:
O.I%,G=1
G=10
G= 100
G =200
G=500
··
Diff. = OVI3)
NOISE, Input'"
Voltage, 10 = 10kHz
Is = O.IHz to 10Hz
Current, 10 = 10kHz
NOISE, Output'"
Voltage, 10 = 10kHz
Is = O.IHz to 10Hz
Small Signal: G = 1
G=10
G=100
G =200
G=500
Full Power
I
TVP
I
MAX
I
··
··
···
···
··
··
·
·· ••
·•
·
·
·
···
·
· ·
·· ··
·· ··
· ·
··
·
··
··
··•
··
··
··
·
···
··
··
··
·
270
17
4
2
3
5
11
54
·
UNITS
VN
VN
%
%
%
%
%
pprn/'C
pprnl'C
pprn/'C
ppml"C
~~;~
%oIFS
%ofFS
%ofFS
%ofFS
V
mA
mA
pF
·
±(200+ ±(looo+
2OOO/G) ,SOOO/G)
vs Temperature
vs Supply
MIN
MAX
·· ··
··
±12.7
±2S
±2S
SOOO
INPUT
OFFSET VOLTAGE'2I
Initial Offset: G, P
I
TVP
pV
pV
pVI"C
·
··
pVN
pA
pA
ClllpF
ClllpF
V
dB
dB
dB
dB
dB
nVl,,(HZ
pVp-p
fAl,,(HZ
nVl,,(HZ
pVp-p
MHz
MHz
kHz
kHz
kHz
kHz
VIpS
pS
pS
pS
ps
pS
ELECTRICAL (CO NT)
INAll0BG/SG
INAll0AG
PARAMETER
Settling Time:
0.01%, G = 1
G=10
G = lOa
G = 200
G = 500
Overload Recovery4fil
CONDITIONS
MIN
Vo = 20V step
50% overdrive
TYP
MAX
5
3
4
7
16
I
12.5
7.5
7.5
12.5
25
POWER SUPPLY
Rated Voltage
Voltage Range
Quiescent Current
±15
±6
Vo=OV
±18
±4.5
±3.0
TEMPERATURE RANGE
Specification: A. B, K
S
Operation
Storage
9J A
-25
+85
MIN
TYP
+125
+150
100
TYP
MIN
·· ··
·· ··
·· ·
MAX
UNITS
·
···
·
ps
ps
ps
ps
ps
ps
·
·
· ·· ·· . · ..
·
·
·· · ··
·
-55
-55
-65
INAll0KP/KU
MAX
a
+70
-25
-40
+85
+85
V
V
rnA
'c
'c
'c
+125
'C
'C/W
• Same as INAll0AG.
NOTES: II) Gains other than 1, la, lOa, 200. and 500 can be set by adding an external resistor, Ro, between pin 3 and pins 11,12, and 16. Gain accuracy is a function of
RG and the internal resistors which have a ±20% tolerance with 20ppm/c C drift. (2) Adjustable to zero. (3) For differential input voltage other than zero, see Typical Performance Curves. (4) VNOISE RTI :;; ..jV~ INPUT + (VN OUTPuT/Gain)2. (5). Time required for output to return from saturation to linear operation following the removal
of an input overdrive voltage.
ORDERING INFORMATION
PIN CONFIGURATION
INA110
Basic Model Number _ _ _ _=r---'
T
Performance Grade Code
A. B: -25°C to +85°C
S: -55°C to +125°C
K: DOC to +7DoC
-
X X
-In
+In
RG
Input Offset Adjust
Input Offset Adjust
Reference
Package Code
G: 16-Pin Hermetic DIP
P: 16-Pin Plastic DIP
U: 16-Pin Small Outline Surface Mount
I
16
2
3
4
5
14
13
12
IS
6
II
-Vee
7
10
+Vcc
B
9
X200
Output Offset Adjust
Oulput Offset Adjust
Xl0
Xl00
X500
Output Sense
Output
ABSOLUTE· MAXIMUM RATINGS
Supply ....................................................... ±18V
Input voltage Range ....................................... ±Vcc
bperating Temperature Range: G .......... -55°C to +125°C
P, U . . . . . . .. -25°C to +85°C
Storage Temperature Range: G ............ -65°C to +150°C
P, U .......... -40°C to +85°C
Lead Temperature (soldering lOS): G, P .............. +300°C
(soldering 3s): U ................. +260°C
Output Short-Circuit Duration ...... Continuous to Common
MECHANICAL
NOTE: Leads in true position
within .010" (.25mm) R
at seating plane.
Pin numbers shown for reference
only. Numbers are not marked on
package.
DIM
A
C
G
M
55
INCHES
MIN
MAX
.790
.810
.105
.015
.170
.021
.048
.060
.100 BASIC
.030
.070
.OOB
.012
.120
.240
.300 BASIC
10'
.025
.060
MILLIMETERS
MIN
MAX
20.07
20.57
2.67
4.32
0.38
0.53
1.22
1.52
2.54 BASIC
0.76
1.78
0.20
0.30
3.05
6.10
7.62 BASIC
10'
0.64
1.52
Small Outline Surface Mount
A
A,
NOTE: Leads in true position
within 0.010" (.2Smm) Rat MMC
at seating plane.
DIM
A
A,
B
B,
C
D
G
H
J
L
M
N
INCHES
MIN
MAX
.400
.416
.388
.412
.302
.286
.268
.286
,109
.093
.015
.020
.050 BASIC
.022
.038
.012
.008
.391
.421
5° TYP
.000
.012
MILLIMETERS
MIN
MAX
10.16 10.57
9.86
10.46
7.26
7.67
6.81
7.26
2.36
2.77
0.38
0.51
1.27 BASIC
0.56
0.97
0.20
0.30
9.93
10.69
5' TYP
0.00
0.30
(1) Performance grade identifier box for small outline surface mount. Blank indicates K grade. Part is marked INA110U.
Plastic DIP
t-:,~
r"l r'1 r"l r
p/
~
/
NOTE: Leads in true position
within .010" (.2Smm) Rat MMC at
seating plane.
=nB~'
!
:J
'v''v''v'V'v' V
Pin 1
L---.J'
.... Flo-
~
"
-.j
..1\.-J
--M
TI~T~
G -1.-0
....
~
H
.
•
PINS: Pin material and plating
composition conform to method
2003 (solderability) of MIL-STD883 (except paragraph 3.2).
CASE: Plastic
DIM
A
A,
B
B,
C
D
F
G
H
J
K
L
M
N
P
Seating Plane
56
INCHES
MAX
MIN
.740
.800
.785
.725
.290
.230
.250
.200
.120
.200
.015
.023
.030
.070
.100 BASIC
0.02
0.05
.008
.015
.070
.150
.300 BASIC
0'
IS'
.010
.030
.050
.025
MILLIMETERS
MAX
MIN
18.80 20.32
18.42 19.94
7.38
5.85
6.38
5.09
5.09
3.05
0.38
0.59
0.76
1.78
2.548ASIC
1.27
0.51
0.20
0.38
1.78
3.82
7.83 BASIC
IS'
0'
0.25
0.76
0.84'
1.27·
BURR-BROWN®
IElElI
t~!
.:::.
INA117
~~
, r:
J\.I\f
ADVANCE INFORMATION
Subject to C~ange
Precision High Common-Mode Voltage
Unity-Gain
DIFFERENTIAL AMPLIFIER
FEATURES
APPLICATIONS
• HIGH COMMON·MODE RANGE: ±200VDC OR AC
• AC OR DC POWER LINE MONITORING
DI:AU'
. . .nil"
•
•
•
•
•
",,,ntlnll"II"
uu ........ u .. '"
UNITY GAIN: 0.02% GAIN ERROR. max
EXCELLENT NONLINEARITY: 0.001 % max
HIGH CMR: 86dB. min
8·PIN TO·99 OR PLASTIC DIP
LOW COST
• INDUSTRIAL PROCESS CONTROL
• GROUND BREAKER
• INDUSTRIAL DATA ACQUISITION SYSTEMS-INPUT
BUFFER WITH OVER·VOLTAGE PROTECTION
DESCRIPTION
The INA1l7 is a precision unity-g/!in differential
amplifier offering an extremely high common-mode
input voltage range. As a monolithic circuit, it offers
high reliability at low cost. The INA1l7 consists of a
premium grade operational amplifier with an onchip precision resistor network. In instances where
an isolation amplifier is used for its inherent high
common-mope capabilities and not for galvanic
isolation, the INAl17 may be substituted at substantially lower cost, especially since no costly isolation
power supply is needed.
The INAIl7 is completely self-contained and offers
the user a highly versatile function. No adjustments
to gain, offset or CMR are needed. This provides
three important advantages: lower initial design
engineering time, lower manufacturing assembly
time and cost, and easy, cost-effective field repair of
a precision circuit.
+Vcc -Vee
Reference B
Compensation
Inlematlonal Airport Industrial Park· P.O. Box 11400· Tucson. Arizona B5734· Tel. 16021 746-1111 • Twx: 9111-952·1111 • Cable: BBRCORp· Telex: 66-6491
PDS·748
57
SPECIFICATIONS
ELECTRICAL
At +25°C, Vee = ±15V unh;ss otherwise noted.
INA117AM
PARAMETER
CONDITIONS
MIN
MAX
1
0.01
2
0.0002
0.05
10
0.001
MIN
OUTPUT
Rated Voltage
Rated Current
Impedance
Current Limit
Capacitive Load
10 = +20mA, -SmA
Eo=10V
10.0
+20, -5
Stable operation
INPUT
Impedance
Differential
800
400
Common-mode
Voltage Range
Differential
Common-mode, continuous
Common-mOde Rejection l31
vs Temperature: DC
AC,60Hz
TA
= TUIN to TMAX
vs Temperature
TA :;::::
Supply
vsTime
±Vcc = 5V to 18V
OUTPUT NOISE VOLTAGE
Fa = 0.01 Hz to 10Hz
fo = 10kHz
DYNAMIC RESPONSE
Gain Bandwidth
Full Power Bandwidth
Slew Rate
Settling Time: 0.1%
0.01%
0.01%
POWER SUPPLY
Rated
Voltage Range
Quiescerit Current
TEMPERATURE RANGE
Specification
Operation
Storage
80
75
80
TMIN
to TMA](
74
120
8.5
90
200
·
1000
40
80
RTO'"
25
550
-3dB
Vo=20Vp-p
200
30
2
Vo= 10V step
Vo= 10V step
VCM = 10V step. V01FF = OV
2.6
6.5
10
.4.5
±15
Derated performance
VOUT=OV
±5
1.5
-25
-55
±18
2.0
+85
+125
+150
-65
..
MIN
0.02
86
80
RT0141
OFFSET VOLTAGE
Initial
YS
±10
±200
74
66
66
MAX
·· ·
·
··
··
·
·
12
0.01
+49,
-13
1000
To common
TYP
··
· ··
GAIN
Initial 111
Error
vs Temperature
Noniineari ty l2J
INA117P
INA117BM
TYP
··
94
90
94
··
··
··
500
20
·
TYP
MAX
·· ·
·· ·
·
·
··
·
··
··
·
·· ·
··
··
·
···
··
·· ··
··
··
·
·
· ·· ·· · ·· ··
··
··
·
·
0
-25
-40
+70
+85
+85
UNITS
VN
%
ppmloC
%
V
mA
Cl
mA
pF
kCl
kCl
V
VDC,ACpk
dB
dB
dB
pV
pV/·C
pVN
pV/mo
.pVP-P
nV/VHz
kHz
kHz
Vips
ps
ps
ps
V
V
mA
·C
·C
·C
'Speclflcallon same as for INA117AM.
NOTES: (1) Connected as difference amplifier. (2) Nonlinearity is the maximum peak deviation flom the best-fit straight line as a percent of full-scale peak-topeak outpu\. (3) With zero source impedance (see Offset and CMR section). (4) Includes effects of amplifier's input bias and offset currents. (5) Includes effects
of amplifier's input current noise and thermal noise contribution of resistor network.
58
MECHANICAL
TO-99 Packago
DIM
A
B
C
D
E
F
G
H
J
K
L
M
NOTE: Leads in true position
within 0.010" (0.25mm) R at MMC
at seating plane.
INCHES
MIN
MAX
.335
.370
.305
.335
.165
.185
.016
.021
.010
.040
.010
.040
.200 BASIC
.028
.034
.029
.045
.500
,110
.160
MILLIMETERS
MIN
MAX
8.51
9.40
7.75
8.51
4.19
4.70
0.41
0.53
0.25
1.02
0.25
1.02
5.08 BASIC
0.71
0.86
0.74
1.14
12.7
2.79
4.06
45° BASIC
45° BAsrC
2,41
2.67
.095
N
.105
"P" Pacltoga-Plastic DIP
DIM
A
A,
B
B,
C
D
H
G
H
~
Jlo
G
J
K
L
M
N
MILLIMETERS
MIN
MAX
9.02
10.16
9.78
8.64
7.37
5.84
6.35
5.08
3.05
5.08
0.38
0.58
V./U
,., ...
2.54 BASIC
1.27
0.64
0.20
0.38
1.78
3.81
7.63 BASIC
0'
IS'
0.25
0.78
0.64
1.27
~~CT:::: !.~::~~!:-; !::.!:::
position within 0.01"
(0.25mm) R at MMC at
seating plane. Pin
material and plating
composition conform to
method 2003 (solderability) of MIL-STO-883
(except paragraph 3.2) .
Seating
Plane
PIN DESIGNATIONS
·TopVlew
INCHES
MIN
MAX
.355
.400
.385
.340
.290
.230
.250
.200
.120
.200
.015
.023
.u;u
.Wii
.100 BASIC
.060
.025
.008
.015
.070
.160
.300 BASIC
0'
IS'
.010
.030
.025
.050
ORDERING INFORMATION
T
INA117 X X
Basic Model Number _ _ _ _ _ _ _ _ _
Molal TO-9!1-INA117AM, Dr.!
:r__
Tab
Performance Grade - - - - - - - - - - - - - - ' A, B: -2S·C to +8S·C
None: O·C to +70·C
Pacl-~---<--oOutPut
L________ I~~_J
Rs) + 1]
FIGURE 4. Simplified Equivalent Circuit Diagram.
61
APPLICATIONS CIRCUITS
The INA1l7 is ideally suited for a wide range of circuit
functions. The following figures show many applications
circuits.
BATTERY CELL MONITOR
Batteries are often charged in series. The INA1l7 is ideal
for directly monitoring the condition of each cell. Operating range is up to ±200V, and differential fault conditions in this range will not damage the amplifier. Since
the INAI17 requires no isolated front-end power, cost
per cell is very low. .
NE2H
NE2H
+200V max
FIGURE 6. 4-20mA Current Receiver.
INAl17
LEAKAGE CURRENT TEST MONITOR
When the return path is not independently available,
leakage current must be measured in series with the
input. When the 400kfl input impedance of the INA1l7
is too low, a buffer amplifier may be added to the front
end. In this example, an OPA128 electrometer-grade
operational amplifier is used. The lkfl and 9kfl feedback
resistors set a noninverting gain of 10. Bias current of the
amplifier is less than 75fA. The diodes and lOOkfl
resistor protect the amplifier from 200V short circuit
fault conditions.
Since common-mode rejection is the ratio of commonmode gain to differential gain, CMR is boosted. The
20dB gain ofthe OPA128 added to the 86dB CMR ofthe
INAll7 results in a total CMR of lO6dB miuimum.
80= Cell
VoltSge
-200V max
FIGURE 5. Battery Cell Monitor.
100MO
INAl17
1-------,
I
Vee
I
eo
= h.
X 10V
(lV1nA)
FIGURE 7. Leakage Current Monitor.
62
currents II and 1, across sense resistors RI and R,. Since
the INA1I7 has a ±2DOV CMV range, the inputs (pins 2
and 3) can be tied to ±Vcc as long as the differential
input is less than IOV.
If
RI = R, = R
then el = II X R
e, = -I, X R
and el + e, = lLOAD X R
A, is an IN AID5 difference amplifier connected as a
noninverting summing amplifier with a gain of 5. The
accurate matching of the two 25kO input resistors makes
a very accurate summing amplifier.
eo = 5 (el + e,) = 5 (ILOAD X R)
since R = 0.20
eo = hOAD (lV/A)
BRIDGE AMPLIFIER LOAD CURRENT MONITOR
Bridge amplifiers are popular because they double the
voltage swing possible across the load with any given
power supply. In this circuit AI and A, form a bridge
amplifier driving a load. AI is connected as a follower
and A, as an inverter.
At low frequencies, a sense resistor could be inserted in
series with the load and an instrumentation amplifier
used to directly monitor the load current. Under high
frequency or transient conditions, CMR errors limit the
accuracy of this approach. An alternate approach is to
measure the power amplifier supply currents. To understand how it works, notice that since essentially no
current flows in the amplifier inputs, lLOAD = II - h.
A3 and A. are INA1I7s used to monitor AI supply
PoiNer Amplifier Supply (2DDV max)
1"-"'\
+ >>-------12V
30
12-bit resolution. 1LSB, 20VFS
16-bit resolution, lLSB, 20VFS
50
16
74
96
··
···
·
·
70
5
0.5
100
40
vs Supplies
vs Load
Current Output
Short Circuit Current
+5.00
+5.005
±5
10
20
400
' 1000
+5
30
-0.1
6
69
·
·
· ·
··
·· ·
··
·· ·
· ·
·
···
·
··
··
·
··· ··
· ·
· ·
Cl
pF
/1Arms
±0.025
+12
+4.995
·
dB
/1VrmslV
dB
pVrms/V
dB
/1VDCIV
±0.02
10000
No Load.
·
±0.Q75
+10
vs Temperature
··
···
··
··
··
VIV
% FSR
ppm FSR/'C
%FSR
-10
Vo; ±10V
Yo; ±10V
Vo; -10V to +10V
C,;C,;O
Vrms
Vpk
±25
-12
±5
9
f ; 0.5MHz to 1.5MHz
Vrms
VDC
Vrms
VDC
±12
5
Current Drive
UNITS
±0.25
±50
-10
Rated Operation
Capacitive
MAX
±0.1
±20
±0.04
3.7
-3.7
Resistance
TYP
···
·
.:-Rated Continuous, 60Hz
DC
Barrier Resistance
Barrier Capacitance
Leakage Current
TYP
14
·
··
mV
mVlV
mVIV
V
kCl
pF
V
V
mA
mA
mVp-p
Cl
pF
/1S
/1Vp-p
/1V1vHz
dB
dB
kHz
kHz
VI/1s
/1s
%
VDC
ppm/'C
/1V1V
/1V!mA
mA
rnA
ELECTRICAL (CONT).
IS01Q2, IS0108
PARAMETER
CONDITIONS
POWER SUPPLIES
Rated Voltage. ±VCC1. ±V=
Voltage Range
Quiescent Current: +VCC1
MIN
TVP
IS01028, IS01088
MAX
MIN
±15
Rated Performance
±10
No Load
+11
:-9
-VCC1
+25
-15
300
600
+Vce.
-Vcca
Power Dissipation: ±VCC1
±V=
TEMPERATURE RANGE
Specification
Operatlng l91
Storage
Thermal Resistance. BJA
-25
-55
-65
±20
+15
-12
+33
-20
400
BOO
+B5
+125
+150
40
TVP
MAX
UNITS
· ·· ··
·· ··
·· ··
· ·
·
··
·
· · ·
V
V
mA
mA
mA
mA
mW
mW
'C
'C
'C
'CIW
• Same as IS0102. iS0108.
NOTES: (1) 100% tested at rated continuous for 1 min~te. (2) Isolation-mode rejection is the ratio of the change in output voitage to a change in isoiation
barrier voltage. It is a function of frequency as shown in the Typicai Performance Curves. This is specified for barrier voitage siew rates n'ot exceeding
l00VlpS. (3) Adjustable to zeno. FSR Full Scale Range 20V. (4) Nonlinearity is the peak deviation of the output voltage from the best fit straight line. it
is expnsssed as the ratio of deviation to FSR. (5) Power Suppiy Rejection = change in Vos/20V supply change. • (6) Ripple is the residual component of
the barrier carrier frequency generated internally. (7) Dynamic Range = FSR/(Voltage Spectral Noise Density X square root of User Bandwidth).
(B) Overshoot can be eliminated by band-limiting. (9) See Typical Performance Curve E for limitations.
=
=
ABSOLUTE MAXIMUM RATINGS
ORDERING INFORMATION
Supply Without Damage ........................ , . .. ±20V
Input Voltage Range ................................ ±50V
Continuous Isolation Voltage Across Barrier
IS0102 ................................ :.;..... 1500Vrms
IS0106 ........................................ 3500Vrms
Junction Temperature ............................. +160·C
Storage Temperature Range .......... -65·C to +150·C
Lead Temperature (soldering 10 seconds) ..... +300·C
Amplifier and Reference Output
Short Circuit Duration...... Continuous to Common
IS010X X
Basic model number----------=r--,
...J
IS0102, 150106
Performance grade ----------'-----1
No designation, B: -25·C to +85·C
I
T.
MECHANICAL
180102
24-Pin Double-Wide Hermetic DIP
124·23
A
101 [OJ
~
J
U
l.G
L-J~
NOTE: Leads in true position
within 0.01" (0.25mm) R at MMC
at seating plane.
CASE: Ceramic
WEIGHT: 3.7g (0.130z)
40
2fi
~
2
1.400
Cil ~
"§.
70
"
,60
>
50
Cl
l!!
"0
"
0.
c.
40
.9-
30
;;:
:;
"
0
lo-±15mA
V," = ±15V
16
~
0
\
VIN
>
:;
.9- 14
-....
""
Balanced Loads
Single-ended' Loads -
<5
\
= +15V
l
~
"
il!'"
20
10
,
18
80
.......;;; t:--
12
f'. '::~:<-IO-ieak
.........
0.1
Capacitor Only
DC
I
:;
:;
)111"'1
o
+85
c.
:;
I
I
o
6
I
o
0
8
/
/
2
o
1
-25
4
./
r
V
L
V
~
4
+25
+50
Temperature ("C)
+75
8
+100
10
12
14
16
18
Input Voltage (V)
OUTPUT VOLTAGE DRIFT
Temperature \ 'C)
THEORY OF OPERATION
The PWS725 and the PWS726 DC-to-DC converters
consist of a free-running oscillator, control and switch
driver circuitry, MOSFET switches, a transformer, a
bridge rectifier, and filter capacitors together in a 32-pin
DIP (0.900 inches nominal) package. The control circuitry consists of current limiting, soft start, frequency
adjust, enable, and synchronization features.
In instances where several converters are used in a
system, beat frequencies developed between the converters are a potential source of low frequency noise in the
supply and ground paths. This noise may couple into
signal paths. By connecting the SYNC pins together, up
to eight converters can be synchronized and these beat
frequencies avoided. The unit with the highest natural
84
frequency will determine the synchronized running frequency. To avoid excess stray capacitance, the SYNC
pin should not be loaded with more than 50pF. If
unused, the SYNC pin must be left open.
Soft start circuitry protects the MOSFET switches during
start up. This is accomplished by holding the gate-tosource voltage of both MOSFET switches low until the
free-running oscillator is fully operational. In addition to
the soft start circuitry, input current sensing also protects
the MOSFET switches. This current limiting keeps the
FET switches operating in their safe operating area
under fault conditions or excessive loads. When either of'
these conditions occur, the peak input current exceeds a
safe limit. The result is an approximate 5% duty cycle,
300ilS drive period to the MOSFET switches. This
protects the internal MOSFET switches as well as the
external load from any thermal damage. When the fault
or excessive load is removed, the converter resumes
normal operation. A delay period of approximately 50lls
incorporated in the current sensing circuitry allows the
output filter capacitors to fully charge after a fault is
removed. This delay period corresponds to a filter
capacitance. of no more than I/LF at either of the output
pins. This provides full protection of the MOSFET
switches and also sufficiently filters the output ripple
voltage (see specification table). The current sensing
circuitry is designed to provide thermal protection for
the MOSFET switches over the operating temperature
range as well. The low thermal resistance of the package
(OlC = JOoCj W) ensures safe operation under rated
.conditions. When these rated conditions are exceeded,
the unit will go into its shutdown mode.
An optional potentiometer can be connected between
the two FREQUENCY ADJUST pins to trim the oscillator operating frequency ±JO% (see Figure I). Care
should be taken when trimming the frequency near the
low frequency range. If the frequency is trimmed too
low, the peak inductive currents in the primary will trip
the input current sensing circuitry to protect the MOSFET
switches from these peak inductive currents.
NOTES: (1)
(2)
(3)
(4)
(5)
The ENABLE pin allows external control of output
power. When this pin is pulled low, output power is
disabled. Logic thresholds are TTL compatible. When
not used, the Enable input may be left open or tied to
VIN (pin 16).
OUTPUT CURRENT RATING
The total current which can be drawn from the PWS725
or PWS726 is a function of total power being drawn
from both outputs (see Functional Diagram). If one
output is not used, then maximum current can be drawn
from the other output. If both outputs are loaded, the
total current must be limited such that:
It should be noted that many analog circuit functions do
not simultaneously draw full rated current from both the
positive and negative supplies. For example, an operational amplifier may draw 13mA from the positive
supply under full load while drawing only 3mA from the
negative supply. Under these conditions, the PWS725 j 726
could supply power for up to five devices (SOmA +- 16mA
= 5). Thus, the ?WS725/72G caii power. more circuit3
than is at first apparent.
ISOLATION VOLTAGE RATINGS
Because a long-term test is impractical in a manufacturing
situation, the generally accepted practice is to perform a
production test at a higher voltage for some shorter
period of time. The relationship between actual test
conditions and the continuous derated maximum specification is an important one. Burr-Brown has chosen a
deliberately conservative one: VDCTEST = (2 X VACrms
CONTINUOUS RATING) + JOOOV for ten seconds. This choice
is appropriate for conditions where system transient
voltages are not well defined.* Where the real voltages
are well-defined or where the isolation voltage is not
continuous, the user may choose a less conservative
derating to establish a specification from the test voltage.
Frequency Adjust is optional. with pins 19 and 20 left open. The normal switching frequency Is 400kHz.
Leave SYNC pin open if unused, limit stray capacitance on SYNC pin to less than 50pF.
leave ENABLE pin open or connect to V,N if not used.
Optional output filtering, with Lo ~ 0, limit Co';; II'F, with Lo ~ 1001'H, limit Co';; 101'F, See Performance Curves for Lo ~ O.
Optional input filtering, see Performance Curves for L,N ~ O.
FIGURE I. PWS725j726 Functional Diagram.
• Reference National Electrical Manufacturers Association (NEMA) Standards Parts ICS 1-109 and ICS I-Ill.
85
THIS PAGE INTENTIONALLY LEFT BLANK
86
BURR-BROWN®
ADC80MAH-12
113131
Monolithic 12-811
ANALOG-TO-DIGITAL CONVERTER
FEATURES
• INDUSTRY-STANDARD 12-BIT ADC
A
!V!!!~!!UT!!!C C!!~!mmCT!!!~
• LOW COST
• ±o.D12% LINEARITY
It 25ps MAX CONVERSION TIME
• ±12V or ±15V OPERATION
• NO MISSING CODES -25°C 10 +B5°C
• HERMETIC 32-PIN PACKAGE
• PARALLEL OR SERIAL OUTPUTS
• 705mW MAX DISSIPATION
DESCRIPTION·
The ADC80MAH-12 is a 12-bit single-chip successiveapproximation analog-to~digital converter for low
cost converter applications. It is complete with a
comparator, a 12-bit DAC which includes a 6.3V
reference laser-trimmed for minimum temperature
coefficient, a successive approximation register
(SAR), clock, and all other associated logic functions.
Internal scaling resistors are provided for the
selection of analog input signal ranges of ±2.5V,
±5V, ± IOV, 0 to +5V, or 0 to + IOV. Gain and offset
errors may be externally trimmed to zero, enabling
initial end-point accuracies of better than ±O.l2%
(±1/2LSB).
The maximum conversion time of 25/Ls makes the
ADC80MAH-12 ideal for a wide range of 12-bit
applications requiring system throughput sampling
rates up to 40kHz. In addition, this AI D converter
may be short-cycled for faster conversion speed with
reduced resolution, and an external clock may be
used to synchronize the converter to the system clock
or to obtain higher-speed operation. The convert
command circuits have been redesigned to allow
simplified free-running operation with internal or
external clock.
Data is available in parallel and serial form with
corresponding clock and status signals. All digital
input and output signals are TTLI LSTTL-compatible, with internal pull-up resistors included on all
digital inputs to eliminate the need for external pullup resistors on digital inputs not requiring connection. The ADC80MAH-12 operates equally well
with either ±15V or ±12V analog power supplies,
and also requires use of a +5V logic power supply.
However, unlike many ADC80-type products, a
+5V analog power supply is not required. It is
packaged in a hermetic 32-pin side-brazed ceramic
dual-in-line package.
I~~~~~ 0---,.-------,
Ex~I~Ca~ 0 - - - - - - - ,
~~~r! 0--:-----,
Comparator
In
0---...,
20V Range .......N-<...."......---ilc-..
10V Range
B~f~~:~ O------"'----......---Re-j-er-en-Oce Out
Inlernational Airporllnduslrial Par~· P.O. Box 11400· Tucson. Arizona B5734· Tel. (6021746·1111 . Twx: 911).952·1111 . Cable: BBRCORp· Telex: 66·6491.
PDS-694
87
SPECIFICATIONS
ELECTRICAL
At T. ~ +25'C, ±Vcc ~ 12V or 15V; VDD ~ +5V unless otherwise specified,
MOOEL
ADC80MAH-12
MiN
RESOLUTION
I
I
TYP
MAX
UNITS
12
Bits
2.55
5.1
10.2
V
V
kO
kO
kO
INPUT
ANALOG
Voltage Ranges: Unipolar
Bipolar
Impedance: 0 to +5V, ±2.5V
oto +10V, ±5V
±10V
DIGITAL
Logic Characteristics (Over specification temperature range)
V'H (Logic "1")
V" (Logic "0")
I'H (V'N ~ +2.7V)
I" (V'N ~ +0.4V)
Convert Command Pulse Wldth lll
2.45
4.9
9.B
a to +5, 0 to +10
±2.5, ±5, ±10
2.5
5
10
2.0
-0.3
5.5
+O.B
20
-20
100ns
20
V
V
/lA
/lAo
/lS
TRANSFER CHARACTERISTICS
ACCURACY
Gain Errorl21
Offset ErrortZ': Unipolar
Bipolar
Linearity Error
Differential Linearity r;:rror
Inherent Quantization"Error
POWER SUPPLY SENSITIVITY
11.4V S ± VocS 16.5V
+4.5V S VDD S +5.5V
DRIFT
"
Total Accuracy. Bipolar""
Gain
Offset: Unipolar
Bipolar
I.,.inearity Error Drift
Differential Linearity over Temperature Range
No Missing Code Temperature Range
Monotonicity Over Temperature Range
%ofFSR'31
%ofFSR
% of FSR.
%ofFSR
LSB
LSB
±0.1
±0.05
±0.1
±O.S
±0.2
±0.3
±0.O12
±1/2
±1/2
±3/4
±0.O03
±0.002
±0.009
±0.OO5
% of FSR/%Vee
% of FSR/%VDD
±10
±15
±3
±7
±1
±23
±30
±15
±3
±3/4
+B5
ppm/'C
ppm/'C
ppm of FSR/'C
ppm of FSR/'C
ppm of FSR/'C
LSB
'C
25
/lS
+0.4
V
V
kHz
+6.3
+6.32
±10
±30
V
/lA
ppm/'C
-25
Guaranteed
CONVERSION TIME'"
22
OUTPUT
DIGITAL (Bits 1-12, Clock Oul, Status, Serial Out)
.
Output Codes'"
Parallel: Unipolar
Bipolar
Serial (NRZ)17I
Logic Levels: Logic 0 (IS'NK S 3.2mA)
Logic 1 (ISOURCE S BO/lA)
Internal Clock Frequency
CSB
COB,CTC
CSB,COB
+2.4
520
INTERNAL REFERENCE VOLTAGE
Voltage
Source Current Avail~~le for External Loadslill
Temperature Coefficient
.
+6.2B
200
POWER SUPPLY REQUIREMENTS
Rated Supply Voltages
Supply Ranges; ±Vcc
VDD
Supply Drain: +Iee (+Vee ~ 15V)
-Icc (-Vee ~ 15V)
100 (Vee ~ 5V)
Power Dissipation (±Vcc ~ 15V, VDD ~. 5V)
Thermal R~sistance. 8JA
±16.5
+5.5
11
24
36
705
V
V
'V
mA
mA
mA
mW
'C/W
+B5
+125
+150
'C
'C
'C
+5, ±12 or ±15
±11.4
+4.5
B.5
21
30
593
50
TEMPERATURE RANGE (Ambient)
Specification
Operating (derated specs)
Storage
-25.
-55
-65
NOTES: (1) Accurate conversIon WIll be obtaIned wIth any convert command pulse WIdth of greater than 100ns; .however, It must
be .limited to 20/ls ,(max) to assure the spacifled conversion time. (2) Gain and offset errors are adjustable t6 zero: See "Optional
External ·Galn and Offset Adjustment" section. (3) FSR means Full-Scale Range and is 20V for ±10V range, 10V for ±5V and 0 to
+10V ranges, etc. (4) Includes drift due to linearity, gain, and offset drifts. (5) Conversion time is specified using internal clock.
For operation with an external clock see "Clock Options" section. This converter may also be short-cycled to less than 12·bit
resolution for shorter conversion time; see "Short Cycle Feature" section. (6) CSB means Complementary Straight Binary, COB
means Complementary Offset Binary, and CTC means Complementary Two's Complement coding. See Table I for additional
information. (7) NRZ means Non-Return-to-Zero coding. (B) ,External loading must be constant during conversion, and must
not exceed 200pA for glJar~nteed specification,
.' .
88
CONNECTION DIAGRAM
Pin 32
Pin 31
Pin 30
Pin 29
Pin 28
Pin 27
Pin 26
Pin 25
Pin 24
Pin 23
Pin 22
Pin 21
Pin 20
Pin 19
Pin 18
Pin 17
Bit6
BitS
Bit4
Bit3
Bit2
Bitl (MSB)
N/C'
Bitl (MSB)
+5V Digital Supply,
Pin 1
Pin 2
Pin3
Pin 4
Pin 5
Pin 6
Pin 7
PmS
Pin 9
Pin 10
Pin 11
Digital Common
Comparator In
Pin
Pin
Pin
Pin
Pin
Bipolar Offset
Rl 10V Range
R2 20V Range
Analog Common
Gain Adjust
12
13
14
IS
16
Bit 7
Bit8
Bit9
Bit 10 (LSB-l0 Bits)
Bitll
Bit 12 (LSB-12 Bits)
Serial Out
-Vee
Reference Out (+6.3V)
Clock Out
Status
Short Cycle
Clock Inhibit
External Clock
Convert Command
+Vcc
• +SV applied to pin 7 has
ne effect on circuit.
ABSOLUTE MAXIMUM RATINGS
MECHANICAL
+Vee to Analog Common.. .. . .. . .. . . .. . .. .. .. .. .. .... 0 to +IS.5V
-Vee to Analog Common. .. . .. .. .. . .. . • .. .. . . .. .. .. .. 0 to -1S.SV
,.-----A---11
p
11
l
D
'---~--__,r-'
J
Voo to Digital Common ... : .............................. 0 to +7V
Analog Common to Digital Common •.•...•...•....•.••..••. ±0.5V
Logic Inputs (Convert Command, Clock In)
to Digital Common ................. : ............. -0.3V to +Vee
Analog Inputs (Analog In, Bipolar Offset)
to Analog Common •••.• , ..••••••••.•.•••...•••.•...••.• ±16.SV
Reference Output •.•••••.•.•.•....•..• Indefinite Short to Common,
Momentary Short to Vee
Lead Temperature, Soldering •......•................. +300°C, 10s
Leads in true position
within .010" (.2Smm) R
B at MMC at seating plane.
Seal ring is connected
to pin 15.
lPin 15
~
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . .. +160°C
I
~:.:::::..-iCF
N ·K -t-J
j.lG
.
Jl D ~g I--.-L--I
'
CAUTION: These devices are sensitive to ele~trostatic discharge.
Appropriate I.C. handling procedures should be followed.
Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. Exposure to absolute maximum conditions for extendf:1~ periods.~~y affect device reliability.
Plane
DIM
A
B
C
D
F
G
J
K
L
N
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
1.584
1.616
.885
.905
.124
.188
.016
.020
.045
.055
.100 BASIC
,009
,012
.165
.175
.900 BASIC
.040
.060
40.23
22.48
41.05
22.99
4.22
0.51
1.40
3.15
0.41
1.14
2.54 BASIC
0.23
0.30
4.19
TYPICAL PERFORMANCE
CURVES
CASE: Ceramic, hermetic
MATING CONNECTaR: 2302MC
WEIGHT: 8.4gm (0.290z)
POWER SUPPLY REJECTION
VS POWER SUPP~Y RIPPLE FREOUENCY
4.45
22.86 BASIC
1.02
1.52
di
t
e.<
0.1
0.08
0.06
0.04
g~
ORDERING INFORMATION
Relolutlon
Model
(bill)
ADC80MAH-12
ADC80MAH-12/0M'"
12
12
7
0.02
w<>
a: g» 0.0 1
fe ~ 0.008
''0 ~ 0.006
#. ~ 0.004
-Vee ......
/
....+SV""-.Supply
0.002
0.00 I
1
NOTE: (I) 10M .ufflx Indlca,e. EnVironmental Screening; see Table IV
for details.
89
+Vee--::7
10
lk
100
Frequency (Hz)
10k,
lOOk
LINEARITY ERROR VS CONVERSION TIME
DIFFERENTIAL LINEARITY ERROR
VS CONVERSION TIME
0.200
0.200
8-Bit Linearity*
iI 0.175
8-Bit Differential Linearity*
'""-
.~
~
e
w
,..
"
~:Ja:
0.125
-'"
"'"·.go
t~
0.100
.~
~ 0.D75
:J
~
.0.
0.175
C
0 0.150
\
10-Bil Linearity*
i
\.
~ 0.Q25
12-Bit Linearity
~ --~-~---l8 10 12 14 16 18
Conversion Time (J.ls)
-
20 22
0.125
0.100
~e
0.075
'-'
.0.
0.050
coW
0.050
0.150
\
~
~
0.025
12-Bit
-- -- -
-
24 26
1O-Bit Differential Linearity*
Diff~ren~ial ~ine~rity
--t--~-~-
-
8 10 12 14 16 18
Conversion Time (,us)
*Converslon Time can be further reduced by using Short-Cycle feature.
DISCUSSION OF
SPECIFICATIONS
OOOH
LINEARITY ERROR
001 H
f~-
20 22
-
24 26
Gain
Error
Rotates
the
002H
Linearity error is defined as the deviation of actual code
transition values from the ideal transition values. Under
this definition of linearity (sometimes referred to as
integral linearity), ideal transition values lie on a line
drawn through zero (or minus full scale for bipplar
operation) and plus full scale, providing a significantly
better definition of converter accuracy than the beststraight-line-fit definition of linearity employed by some
manufacturers.
The zero or minus full-scale value is located at an analog
input value Ij2LSB before the first code transition
(FFF H to FFEH). The plus full-scale value is located at
an analog value 3j2LSB beyond the last code transition
(OOIH to OOOH). See Figure I. which illustrates these
relationships. A linearity specification which guarantees
±lj2LSB maximum linearity error assures the user that
no code transition will differ from the ideal transition
value by more than ±lj2LSB.
7FDH
~
B- 7FEH
6
:§
.0,
is
7FFH
BOOH
Offset
I
I:
I I
II
II
II
: I-- Midscale
I
: I
-i I-
I
3/2LSB I-----i
I +Full
I
I Scale
I----Transition Values-----l
I
1/2LSB
Analog Input
FIGURE 1. Transfer Characteristic Terminology.
Thus, for a converter connected for bipolar operation
and with a full-scale range (or span) of 20V (±IOV
operation), the minus full-scale value of -lOY is 2.44mV
below the first code transition (FFFH to FFEH at
-9.99756V) and the plus full-scale value of + lOY is
7.32mV above the last code transition (OOIH to OOOH at
+9.99268V). Ideal transitions occur ILSB (4.88mV) apart,
and the ± I j 2LSB linearity specification guarantees that
no actual transition will vary from the ideal by more
than 2.44mV. The LSB weights, transition values, and
code definitions for each possible ADC80 analog input
signal range are described in Table I.
TABLE I. Input Voltages, Transition Values, LSB Values, and Code Definitions.
Input Voltage Range and LSB Values
Binary Output
Analog Input Voltage Range
±10V
±5V
±2.5V
o to +10V
eOB(1J or CTC '2)
COBorCTC
COB orCTC
CSB I3 )
CSB
FSR/2"
n=8
n = 10
n = 12
20V/2"
78.13mV
19.53mV
4.88mV
10VJ2"
39.06mV
9.77mV
2.44mV
5V12"
19.53mV
4.88mV
1.22mV
10Vl2"
39.06mV
9.77mV
2A4mV
5VJ2"
19.53mV
4.88mV
1.22mV
+ Full Scale
Midscale
- Full Scale
+10V - 3/2LSB
0
-10V + 1/2LSB
+5V - 3/2LSB
0
-5V + 1I2LSB
+2.5V - 3/2LSB
0
-2.5V + 1/2LSB
+10V - 3/2LSB
+5V
0+ 1/2LSB
+5V - 3/2LSB
+2.5V
0+ 1/2LSB
Defined As:
Code Designation
One Least Significant
Bit (LSB)
Transition Values
MSB
LSB
001 H to OOOH
800H to 7FFH
FFFH to FFEH
o to +5V
NOTES: (1) COB = Complementary Offset BiQary. (2) eTC = Complementary Two's Complement-obtained by using the complement of the most
significant bit (MS8). MSB is available on pin B. (3) esa = Complementary Straight Binary.
90
CODE WIDTH (QUANTUM)
Code width (or quantum) is defined as the range of
analog input values for which a given output code will
occur. The ideal code width is ILSB, which for l2-bit
operation with a 20V span is equal to 4.BBmV. Refer to
Table I for LSB values for other ADCBO input ranges.
DIFFERENTIAL LINEARITY ERROR AND NO
MISSING CODES
Differential linearity error is the difference l;>etween an
ideal ILSB code width (quantum) and the actual code
width. A specification which guarantees no missing
codes requires that every code combination appear in a
monotonically increasing sequence as the analog input is
increased throughout the range, requiring that every
input quantum must have a finite width. If an input
quantum has a value of zero (a differential linearity error
of -ILSB), a missing code will occur but the converter
may still be monotonic. Thus, no missing codes represent
a more stringent definition of performance than does
monotonicity. ADCBO is guaranteed to have no missing
codes to 12-tit resulution over its fun ;;pccificatiot
temperature range.
QUANTIZATION UNCERTAINTY
Analog-to-digital converters have an inherent quantization error of ±1/2LSB. This error is a fundamental
property of the 'quantization process and cannot be
eliminated.
UNIPOLAR OFFSET ERROR
actual 2SoC value to the value at the extremes of the
Specification temperature range. The temperature coefficient applies independently to the two halves of the
temperature range abov~ and below +2S°C.
POWER SUPPLY SENSITIVITY
Electrical specifications for the ADCBO assume the
application of the rated power supply voltages of +SV
and ±12V or ±ISV. The major effect of power supply
voltage deviations from the rated values will be a small
change in the plus full-scale value. This change, of
course, results in a proportional change in all code
transition values (i.e., a gain error). The specification
describes the maximum change in the plus full-scale
value from the initial value for independent changes in
each power supply voltage.
TIMING CONSIDERATIONS
Timing relationships of the ADCBO are shown in Figure 2.
During conversion, the decision as to the proper state of
any bit (bit "n") is made on the rising edge of clock pulse
"u + i"'. Thus, a c.:ullipleit: I..:UllVt:fSiulI i'c4uin:s 13 dut,;k
pulses with the status output dropping from logic "I" to
logic "0" shortly after the falling edge of the 13th clock
pulse, and with valid output data ready to be read at that
'time.
Additional convert commands applied during conversion
will be ignored.
S'tatus remains high until after the falling edge of the 13th
clock pulse. This allows direct use of status for latching
parallel data.
An ADCBO connected for unipolar operation has an
analog input range of OV to plus full scale. The first
output code transition should occur at an analog input
value 1/2LSB above OV. Unipolar offset error is defined
as the deviation of the actual transition value from the
ideal value, and is applicable only to converters operating
in the unipolar mode.
-I
Status
BIPOLAR OFFSET ERROR
A/ D converter specifications have historically defined
bipolar offset at the first transition value above the
minus full-scale value. The ADCBO follows this convention. Thus, bipolar offset error for the ADCBO is defined
as the deviation of the actual transition value from the
ideal transition value located 1/2LSB above minus full
scale.
I-tSD
--I
I--tep
--I
Hew
---1
Bit12~
~
5 . I
--I HDV '
D:~~ D&!&lnvalldi Bill! 811216'1316'141 BIISI BitS! ell7! B'Isl 8,'916,1101611"la"
GAIN ERROR
The last output code transition (OOIH to OOOH) occurs for
an analog input value 3/2LSB below the nominal plus
full-scale value. Gain error is the deviation of the actual
analog value at the last transition point from the ideal
value.
Symbol
Parameter
Typ.
Units
teo
Clock delay from convert command
Nominal clock period
Nominal clock pulse width
Status delay from convert command
All bits reset delay from convert command
Data valid time from clock pulse high
15,3
1.81
0.87
186
141
-15
ns
ps
ps
ns
ns
ns
!cP
tew
tSD
t,
tDv
ACCURACY DRIFT VS TEMPERATURE
The temperature coefficients for gain, unipolar offset,
and bipolar offset specify the maximum change from the
121
FIGURE 2. Timing Diagram (nominal values at +2SoC
with internal clock).
91
DEFINITION OF DIGITAL CODES
ANALOG SIGNAL SOURCE IMPEDANCE
The signal source supplying the analog input signal to
the ADC80 will be driving into a nominal DC input
impedance of 2.3kfl to 9.2kfl depending upon the range
selected. However, the output impedance of the driving
source should bevery low, such as the output impedance·
provided by a wideband, fast-settling operational amplifier. Transients in A/ D input current are caused by the
changes in output current of the internal D / A converter
as it tests the various bits. The output voltage of the
driving source must remain constant while furnishing
these fast current changes. If the application requires a
sample/hold, select a sample/hold with sufficient bandwidth to preserve the accuracy or use a separate wideband
buffer amplifier to lower the output impedance.
Parallel Data
Three binary c,odes are available on the ADC80 parallel
output; all three are compleme'n'tary 'codes, meaning that
logic "0" is true. The available codes are complementary
straight binary (CSB) for unipolar input signal ranges,
and complementary offset binary (COB) and complementary two's complemen't (CTC) for bipolar input
signal ranges. CTC coding is obtained by complementing
bit I (the MSB) relative to, its normal state for CSB or
COB coding; the complement Of bit I is available on pin 8.
Serial Data
Two (complementary) straight binary codes are available
on the serial output of the ADC80; as in the parallel
case, they are CSB and COB. The serial data is available
only during conversion and appears with the most
significant bit (MSB) occurring first. The serial data is
synchronous with the internal dock as shown in the
timing diagram of Figure' 2. The LSB and transition
values of Table I also apply to the serial data output,
except that the CTC code is not available. All clock
pulses available from the ADC80 have equal pulse
widths to facilitilte transfer of the serial data into
external logic devices without external shaping.
INPUT SCALING
The ADC80 offers five standard input ranges: OV to
+5V, OV to +IOV. ±2.5V, ±5V, and ±IOV. The input
range should be scaled as close to the maximum input
signal range as possible in order to utilize the maximum
signal resolution of the converter. Select the appropriate
input range as indicated by Table II. The input circuit
architecture is illustrated in Figure 3. External padding
resistors can be added to modify the factory-set input
ranges (such as addition of a small external input resistor
to change the 10V range to a 10.24V range). Alternatively,
the gain range of the converter may easily be increased a
small amount by use of a low temperature coefficient
potentiometer in series with the anaJog input signal or by
decreasing the value of the gain adjust series resistor in
Figure 5.
LAYOUT AND OPERATING
INSTRUCTIONS
LAYOUT PRECAUTIONS
Analog and digital commons are not connected together
internally in the ADC80, but ,should be connected
together as close to the unit as possible, preferably to an
analog common ground plane beneath the converter. If
these common lines must be run separately, use wide
conductor pattern and a O.OI/tF to O.J/tF nonpolarized
bypass capaCitor between analog and digital commons at
the .unit. Low impedance analog and digital common
returns are essential for low noise performance. Coupling
between analog input lines and digital lilies should be,
minimized by careful layout. For instance, if the lines
must cross, they should do so at right angles. Parallel
analog and digital lines should be separated from each
other by a pattern connected to common. If external
gain and offset potentiometers are used,' the potentiometers and associated resistors should be located as
close to the ADC80 as possible. Capacitive loading on
comparator and input pins should be kept to a minimum
to maintain converter performance.
TABLE II. Input Scaling Connections.
Input
Signal
Range
±10V
±S4V
±2.SV
oto +SV
oto+l0V
Output
Code
Connect
Pin 12
To Pin
Connect
Pin 14
To
Connect
Input
Signal
To
COB orCTC
COBorCTC
COBorCTC
CSB
CSB
11
11
11
15
15
Input Signal
Open
Pin 11
Pin 11
Open
14
13
13
13
13
10V Range ":"13::-------..,
R2
20V Range
-:-:-----'W...---+
14
SkCl
Rl
POWER SUPPLY DECOUPLING
SkCl
Comp.ln ""'1"-1----~~~~-I
The power supplies should be bypassed with I/tF to IO/tF
tantalum bypass capacitors located close to the converter
to obtain noise-free oper"ation. Noise on the power
supply lines can degrade the converter's performance.
Noise and spikes from a switching power supply are
especially troublesome.
'
... !~om O/A Converter
Bipolar
Offset
Analog
6~kcit
12
~
Common 15
..
VREF
FIGURE 3. Input Scaling Circuit.
92
CALIBRATION
Optional External Gain And Offset Adjustments
Gain and offset errors may be trim:ned to zero using
external offset and gain trim potentiometers connected
to the ADC80 as shown in Figures 4 and 5 for botli
unipolar and bipolar operation. Multiturn potentiometers
with 100ppm/oC or better TCR are recommended for
minimum drift over temperature and time. These pots
may be of any value between IOkn and 100kn. All fixed
resistors should be 20% carbon or better. Although not
necessary in some applications, pin 16 (Gain Adjust)
should be preferably bypassed with a O.O\JlF nonpolarized
capacitor to analog common to minimize noise pickUp at
this high impedance point, even if no external adjustment
is required.
(8)
(A)
+vcc
+vcc
~
_tt_..,~~",:J,...~___
~g~~~o
COIll~. In
Adjust
t.SMCl to
!
Offset
~~ t ~~-!I ~g~~~o
COI'np. In 122kCl to
28kCl
-Vee
AOdf~set
•
Just
-Vee
FIGURE 4. Two Methods of Connecting Optional
Offset Adjust.
(A)
!.
(8)
+Vee
Gain Adjust 8.2MCl to
16
10MCl
+vcc
~g~~~o
t6
Adjust
« ;0.011116.8kCl to
~
9.1kCl
270kCl
270kCl
~Gain
..
"T"
~
Analog
Common
O,01I1 F
-Vee
-:-
until the output code is alternating between OOOH and
OOIH with an approximate 50% duty cycle. As in the case
of offset adjustment, this procedure sets the converter
end-point transitions to a precisely known value.
CLOCK OPTIONS AND SHORT CYCLE FEATURE
The ADC80 is extremely versatile in that it can be
operated. in several different modes with either internal
or external clock. Most of these options can be implemented with inexpensive TTL logic as shown in Figures
6 through 9. Pin 20 (clock inhibit) must be grounded for
use with an external clock, which is applied to pin 19.
A short-cycle input (pin 21) permits the conversion to be
terminated after any number of desired bits has been
converted, allowing shorter conversion times in applications not requiring full 12-bit resolution. In these situations, the short-cycle pin shoul~ be connected to the bit
output pin of the next bit after the desired resolution.
For example, when lO-bit resolution is desired, pin 21 is
connected to pin 28 (bit II).. In this example, the
conversion cycle terminates and status is reset after the
bit 10 decision. Short-cycle pin connections and associated maximum 12-, 10-, and 8-bit conversion times (with
internal clock) are shown in Table III. Shorter conversion
times are possible with an external clock applied to pin
19. With increasing clock speed, linearity performance
will begin to degrade as indicated in the Typical Performance Curves. These curves should be used only as
. guidelines because guaranteed. 'peiformance is specified
and tested only with the internal clock.
.
10kClto
100kCl
Gain
Adjust
TABLE III. Short-Cycle Conne'ctions and Conversion
Times for 8-, 10-, and 12-Bit ResolutionsADC80MAH-12.
-Vee
Resotutlon (Bits)
Connect pin 21 to
FIGURE 5. Two Methods of Cunnecting Optional Gain
Adjust.
12
10
8
Pin 90rNC
Pin 28
Pin 30
25
22
18
J.012
0.048
0.20
Maximum Conversion Tima f11
Internal Clock (ps)
Maximum Linearity Error
at +25'C (% of FSR)
Adjustment Proc.edure
OFFSET -Connect the offset ·potentiometer as shown
in Figure 4. Set the input voltage to the nominal zero or
minus full-scale voltage plus 1/2LSB. For example,
referring to Table I, this value is -lOY +2.44mV or
-9.99756V for the -lOY to +IOV range.
NOTE: (1) Conversion time to maintain ±1/2LSB linearity error.
External
Clock
With the input voltage set as above, adjust the offset
potentiometer until an output code is obtained which is
alternating between FFEH and FFFH with approximately
50% occurrence of each of the two codes. In other words,
the potentiometer is adjusted until bit 12 (the LSB)
indicates a true (logic "0'') condition approximately half
the time.
GAIN-Connect the gain adjust potentiometer as shown
in Figure 5. Set the input voltage to the nominal plus
full-scale value minus 3/2LSB. Once again referring to
Table I, this value is +IOV -7.32mV or +9.99268V for
the -lOY to + lOY range. Adjust the gain potentiometer
19 External
Clock
Bit 11
28
Short
Cycle
21
10·Bit
,.. Operation
I
I
ADC80
18
Digital
Common
Cony.
Com.
Clock 20
Inhibit
":"
Digital
Common
FIGURE 6. Continuous Conversion with External
Clock. (Conversion is initiated by 14th
clock pulse. Clock runs continuously.)
93.
,~ Convert
+SV
ADC80
Jl
No
Connection
Necessary
Command
Short~,
Cycle
r-}'
J
18
Bitll
Convert
Command
Short
Cycle
21
I'
Clock 20
Inhibit
ADC80
I;~~~i~ ~
10-Bit
Operation
28
External 19
Clock
External ~,
Clock
FIGURE 7. Continuous Conversion.
Optional
Connection
+5Y
FIGURE 8. Internal Clock-Normal Operating Mode.
(Conversion initiated by the rising edge of
the convert command. The internal clock
runs only during conversion.)
External Bit 11
Clock
External
Clock
28
10-Bit
Operation
1/
1
ADC80
, -_ _ _ _ _ _ _
22.... Status
Short
Cycle
21
_ _ _~_ _ _ _ _ _..;1,8 ConY,
Com.
Clock
Inhibit
20
'Digital
":' Common
FIGURE 9. Continuous External Clock. (Conversion intitiated by rising edge of
convert command. The convert command must be synchronized with
clock.)
,
ENVIRONMENTAL SCREENING
The inherent reliability of a semiconductor device is
controlled by the design, materials, and fabrication of
the device-it cannot be improved by testing. However,
the use of environ'mental screening can eliminate the
majority of those units which would fail early in their
lifetimes (infant mortality) through the application of
carefully selected accelerated stress levels. Burr-Brown Q
models are environmentally screened versions of our
standard industrial products, designed to provide
enhanced reliability. The screening illustrated in Table
IV is performed to selected methods of MIL-STD-S83.
Reference to these methods provides a convenient way
of communicating the screening levels and basic procedures employed; it does not imply conformance to any
other military standards or to any methods of MILSTD-883 other than those specified. Burr-Brown's
detailed procedures may vary slightly, model-to-model,
from those in MIL-STD-883.
TABLE IV. Screening Flow for ADCSOMAH-12/QM.
Screen
Internal Visual
MIL-STO-883
Method,
Condition
Screening Level
2010
High Temperature Storage
(Stabilization Bake)
1008,C
24 hour, +IS0"C
Temperature Cycling
1010, C
10 cycles, -6S"C
to +IS0"C
2001,A
SOOOG
Constant Acceleration
Electrical Test
Burr-Brown
test procedure
Burn-in
Hermeticity:
Fine Leak
Gross Leak
Final Electrical
1015, B
160 hour, +12S"C,
steady state
1014, AI or A2
1014, C
5 X 10-7 atm eels
Burr-Brown
test procedure
Final Drift
Burr-Brown
test p'rocedure
External Visual
94
2009
bubble test only,
pre-cond,itioning
omitted
BURR-BROWN®
ADC84
ADC85H
ADC87H
IEJEJI
IC ANALOG-TO-DIGITAL CONVERTERS
FEATURES
•
•
•
•
•
•
• THREE TEMPERATURE RANGES:
u:::\: io +iii=L:
-25° C to +85° C
-55°C to +125°C
• NO MISSING CODES OVER FULL TEMPERATURE
RANGE
• PARALLEL AND SERIAL OUTPUTS
• ±12V or ±15V POWER SUPPLY OPERATION
• HERMETIC 32·PIN CERAMIC SIDE·BRAZED DIP
INDUSTRY STANDARD 12·BIT AID CONVERTERS
COMPLETE WITH CLOCK AND INPUT BUFFER
HIGH SPEED CONVERSION: lOps (max)
REDUCED CHIP COUNT-HIGH RELIABILITY
LOWER POWER DISSIPATION: 450mW (typ)
±0.012%MAX LINEARITY
DESCRIPTION
The ADC8SH Series o(analog.to-digital converters
utilize state-of-the-artIC and laser-trimmed thinfilm components, and are packaged in a 32-pin
hermetic side-brazed package.
Complete with internal reference and input buffer
amplifier, they offer versatility and performance
formerly offered only in larger modular or rackmount packages.
Thin-film internal scaling resistors are provided for
the selection of analog input signal ranges of ±2.SV,
±SV, ±IOV, 0 to +SV orO to +IOV. Gain and offset
errors may be externally trimmed to zero, offering
initial accuracies of better than ±O.OI2% (± 1/ 2LSB).
The fast lOlLS conversion speed for 12-bit resolution
makes these ADCs excellent for a wide range of
applications where system throughput sampling rates
of 100kHz are required. In addition, they may be
short cycled and the clock rate control may be used
to obtain faster conversion speeds at lower resolutions.
Data is available in parallel and serial form with
corresponding clock and status signals. All digital
input and output signals are CMOS/TTL-compatible. Power supply voltages are ±12VDC or
±lSVDC and +SVDC.
Inlernational Airporllnduslrlal Pa'rk • P.o. Box 11400· Tucson. Arizona 85734 • Tel. 1602f]46·1111 : Twx: 910·952·1111 • Cabla: BBRCORP • Telex: 66·6491
PDS-714
95
SPECIFICATIONS
ELECTRICAL
Specified at +2SClC and rated supplies unless otherwise noted.
MODEL
AOC84KG-12'"
MIN
ADC85H-12
TYP
MAX
RESOLUTION
MIN
TYP
INPUTS
I
I
±2.5, ±5, ±10
o to +5, 0 to +10
2.45
2.5
2.55
4.9
5
5.1
9.8
10
10.2
100
50
··
··
2
DIGITAL'"
Convert Command
Logic Loading
I
±0.1
±0.05
±0.1
I
I
±0.25
±0.2
±0.25
±0.012
±0.5
±0.5
0
+70
POWER SUPPLY SENSITIVITY
Gain and Offset: ±15V
+5V
-25
±0.004
±0.001
DRIFT
Gain
Guaranteed
10
DIGITAL OUTPUT'"
I
CSB
COB,CTC
2
CSB,COB
2
Logic "1" during conversion
I
I
I ,t I
INTERNAL REFERENCE VOLTAGE
Reference Output
Max. External Curtent With No Degradation
Tempeo of Drift
+6.2
+6.3
+6.4
200
±20
POWER SUPPLY REQUIREMENTS
Rated Supply Voltages
Supply Ranges: VDD
±Vcc
Supply Drain: +Icc
-Icc
+5, ±12 or ±15
+4.75
±".4
100
Total Power Dissipation
450
+5.25
±16.5
20
25
10
725
TEMPERATURE RANGE
Specification
Operating (with Derated Specs)
Storage
PACKAGE
0
-25
-65
+70
+85
+150
Hermetic Ceramic
IS
MAX
·
··
·
UNITS
Bits
V
V
kO
kO
kO
MO
nA
I1S
+85
the same as ADC84KG-12 .
96
TTL Load
I
-55
··
·
.'
+125
±7
±2
· ·
··
··
···
··
· ·
···
···
···
· · ·· · · ··
·· · ·· ·· · ··
··
··
·
· ··
· ·
±5
-25
-55
±10
+85
+125
±5
-55
%
%ofFSR'5I
% of FSR
%ofFSR
LSB
LSB
"C
% of FSR/%V.
% of FSR/%V.
±15
:\:5
±10
±2
±3
±15
±3
Frequency(7)
f
I
±15
±3
CONVERSION TIME
..
·Speclflcatlon
·
·
··· ·· ·· ···
· · ·· ·
·'.
·
·
·
·
·· ··
··
· ··
·
··
··
··
··
±30
Offset: Unipolar
. Bipolar
Linearity
Monotonicity
(All Codes Complementary)
Parallel Output Codes: Unipolar
Bipolar
Output Drive
Serial Data Codes (NRZ)
Output Drive
Status
Output Drive
Internal Clock: Output Drive
TYP
Positive pulse SOns (min). trailing edge initiates conversion
1
TRANSFER CHARACTERISTICS
ACCURACY
Gain ErrorC41
Offset ErrorC4J : Unipolar
Bipolar
Linearity Errorcs1
Inherent Quantization Error
Differential Linearity Error
No Missing Codes Temperature Range
MIN
·
12
ANALOG
Voltage Ranges: Bipolar
Unipolar
Impedance (Direct Input): 0 to +5V, ±2.5V
o to +10V, ±5V
±10V
Bul!.r Amplifier: Impedance
Bias Current
Settling Time to
0.01% for 20V step'"
ADCB7H-12
MAX
±10
+125
· · · · · ·
ppm/"C
ppm of FSR/"C
ppm of FSR/"C
ppm of FSR/"C
IJS
TTL Loads
TTL Loads
TTL Loads
TTL Loads
MHz
V
I1A
ppm/"C
V
V
V
mA
mA
mA
mW
"C
"C
"C
NOTES: (1) Model ADCB4KG-l0 is the same as model ADC84KG-12 except for the following: (a) Resolution: 10 bits (max), (b) Linearity Error: ±0.048% of
FSR (max), (c) Conversion Time: 6ps (max), (d) Internal Clock Frequency: 1.9MHz (typ). (2) If the buffer is used, delay Convert Command until amplifier
settles. (3) DTUTTl compatible. For digital inputs logic "0" = 0.8V (max) end logic "1" = 2.0V min. For digital outputs logic "0" = O.4V (max) and logic
"1" = 2.4V (min). (4) Adjustable to zero. (5) FSR means Full Scale Range. (6) The error shown is the same as ±1I2lSB max linearity error in % of
FSR. (7) Internal clock is externally adjustable.
CONNECTION DIAGRAM-ADC85H SERIES
Top View
(lSB for 12 bits) Bit 12
Serial Out
Billl
-Vee
(lSB for 10 bits) Bit 10
Buffer In
Bil9
Buffer Out
Bit8
+Vcc
Bit7
Gain Adjust
Bit6
Analog Common
BitS
R, 20V Range
Bit4
R,10V Range
Bit3
Bipolar Offset
Bit2
Comparator In
Bltl (MSB)
Convert Command
Bit 1 (MSB)
Status
Clock Out
Short Cycle
Reference Out (+6.3V)
Digital Common
Clock Rate Control
Vee
MECHANICAL
32
D
17 __
I
Pin numbers shown for
1...
' ...cT+-____ reference only. Pin numbers
..
!
~~-..-..--...l"
I-I.--A----........--II
+".OO~=i~'
J .
~ ,-1
PIN: Pin material and plating
composition conform to
method 2003 (solderability) of
Mll-STD-883 (excepl
paragraph 3.2).
HERMETICITY: Conforms to .
Method 1014, Condition Alar
A2 (fine leak) and Condition C
(gross leak). Metal lid of
package is connected to -Vee
internally.
ORDERING INFORMATION
Resolution
(Bits)
Temp Range
(OC)
ADC84KG-l0
ADCB4KG-12
10
12
Oto+70
Oto+70
ADC85H-12
ADC85HQ-12'
12
12
-25 to +85
-25 to +85
ADC87H-12
ADC87HQ-12'
12
12
-55 to +125
-55 to +125
Model
'" Q suffix mdlcates environmental screening; see Table" for details.
97
NOTE: leads in true position
within .010" (0.25mm) R at MMC
at seating plane.
DIM
A
B
C
D
F
G
H
J
K
L
N
INCHES
MIN
MAX
1.580
1.620
.880
.900
.138
.186
.016
.020
.000TYP
.100 BASIC
.044
.056
.009
.012
.165
.185
.900
.920
.040
.060
MILLIMETERS
MIN
MAX
40.13
41.15
22.35
22.86
3.51
4.72
0.41
0.51
1.02TYP
2.54 BASIC
1.12
1.42
0.23
0.30
4.19
4.70
23.37
22.86
1.02
1.52
The ADC84, ADC85H and ADC87H are also monotonic,
assuring that the output digital code either increases or
remains the same for increasing analog 'input signals.
Burr-Brown also guarantees that these converters will
have no missing codes over a specified temperature
range. Figure 2 is the timing diagram.
THEORY OF OPERATION
The accuracy of a successive approximation AI D converter is described by the transfer function shown in Figure
I. All successive approximation AI D converters have an
inherent Quantization Error of ± I I 2LSB. The remaining
errors in the AI D conve'rter are combinations of analog
errors due to the linear circuitry, matching and tracking
properties of the ladder and scaling networks, power
supply rejection, and reference errors. In summary, these
errors consist of initial errors including Gain, Offset,
.' Li'nearity, Differential Linearity and Power Supply Sensitivity, Initial Gain and Offset errors may be adjusted to
zero. Gain drift over temperature rotates the line (Figure
l) about the zero or minus full scale point (all bits OFF)
and Offset drift shifts the line left or right over the
operatiIig temperature range. Linearity error is unadjustable and is the most meaningful indicator of AI D
converter accuracy. Linearity error is the deviation of an
actual bit transition from the ideal transition value at
any level over the range of the AI D converter. A
Differential Linearity error of ±1/2LSB means that the
width of each bit step over the range of the AI I)
converter is ILSB ±1/2LSB.
000 .. 000
CD
'0
0
()
000 .. 00'
0" ... '0'
0
~ 0" ... "0
III
~
'0
0
()
0" ...
",
""- 100 .. 000
:;
0
'00 .. 00'
]j
'0,
is
I"~ ... "0
I"~
...
,,,
+FSR -.1LSB
2
E," Off
* See Table I for digital code definitions.
FIGURE I. Input vs Output for an Ideal Bipolar AI D
Converter.
Maximum Throughput Time(21
Conved 11
Conversion Time
Command
MSB
Bit2
Bit3
Bit4
BitS
Bit6
Bit 7
BitS
Bit9
Bit 10
Bit',
LSB
Serial(3)
Data Out
~==J "0"
~~~~"=,,,========================
==_-J
:::1
LJ",,,
1"0"
---J
Iv
---~------~.==~~===============-~
::'-:J
Lj"'"
=:::: -l-,r-------------.U
=="J
---I
"t"
Lj"'"
1"0"
LJ . ,.
LJ . ,.
___ J
::-J
===-J
"0"
1
::::= =- Wffa.:rJ ", ..
2
"0"
. ,.
. ,.
6
"0"
"0"
7
", .
", .. W'O.., ..
"0"
..,.
I
"0"
NOTES: (1) The convert command must be at least 50ns wide and must remain low during a conversion. The conversion is initiated by the
.. trailing edge" of the convert command. (2) '0.5Ils for'2 bits and 6.4lls for 10 bits. (3) Use trailing edge of clock to strobe serial output.
FIGURE 2. Timing Diagram.
98
definitions for each possible analog input signal range
for 8-, 10-, and 12-bit resolutions.
DIGITAL CODES
Parallel Data
Three binary codes are available on the ADC85H series
parallel output:
• complementary (logic "0" is true) straight binary (CSB)
for unipolar input signal ranges;
• complementary two's complement (CTC) for bipolar
input signal ranges;
• complementary offset binary (COB) for bipolar input
signal ranges.
Table I describes the LSB, transition values and code
Serial Data
Two straight binary (complementary) codes are available
on the serial output line; they are CSB and COB. The
serial data is available only during conversion and
appears with the most significant bit (MSB) occurring
first. The serial data is synchronous with the internal
clock as shown in tlie timing diagram of Figure 2. The
LSB and transition values shown in Table I also apply to
the s'erial data output except for the CTC code.
TABLE l. Input Voltages, Transition Values, LSB Values, and Code Definitions.
Binary Output
Input Vollage Range and LSB Values
Analog Input Vottage Ranges
±IOV
±SV
±2.SV
oto+IOV
Oto +SV
eos UI or CTC 421
COS lll or CTC l21
eDa l1l or CTC~21
ese(3)
CSS l31
n= 10
n= 12
20V/2'
7B.13mV
19.53mV
4.BBmV
IOV/2'
39.06mV
9.77mV
2.44mV
SV/2'
19.53mV
4.BBmV
1.22mV
IOV/2'
39.06mV
9.77mV
2.44mV
SV/2'
19.53mV
4.BBmV
1.22mV
+Full Scale
Mid Scale
-Full Scale
+IOV - 3/2LSB
0
-IOV + 1I2LSB
+SV -3/2LSB
0
-SV + 1I2LSB
+2.SV - 3/2LSB
0
-2.SV + 1I2LSB
+IOV - 3/2LSB
+SV
0+ 1I2LSB
+SV - 3/2LSB
+2.SV
0+1I2LSB
Defined As
Code Designation
One Least Significant Bit (LSB)
FSR/2"
n=8
Transition Values
M:>fj L:>t!
000 .. 000('"
Oil ... 111
III ... 110
NOTES: (I) COB = Complementary Offset Binary. (2) CTC = Complementary Two's Complement-obtained by using the complement of the
most-significant bit (MSB). MSB is available on pin 13. (3) Complementary Straight Binary. (4) Voltages given are the nominal value fortransition to the
code specified.
ENVIRONMENTAL SCREENING
The inherent reliability of a semiconductor device is
controlled by the design, materials, and fabrication of
the device-it cannot be improved by testing. However,
the use of environmental screening can eliminate the
majority of those units which would fail early in their
lifetimes. Burr-Brown Q models are .environmentally
screened versions of our standard industrial products,
designed to provide enhanced reliability. The screening
illustrated in Table iI is performed to selected methods
of MIL-STD-883. Reference to these methods provides
a convenient way of communicating the screening levels
and basic procedures employed; it does not imply conformance to any other military standards or to any
methods of MIL-STD-883 other than those specified.
Burr-Brown's detailed procedures may vary slightly,
model-to-model, from those in MIL-STD-883.
TABLE II. Screening for ADC85HQ-12 and
ADC87HQ-12.
Screen
Internal Visual
MIL-STD-883
Method, Condillon
Screening Level
Burr-Brown OC4118*
High Temperature Storage
(Stabilization Bake)
100B. C
24 hour. +ISO'C
Temperature Cycling
1010. C
10 cycles. -6S'C
to+ISO'C
Constant Acceleration
2001. A
SOOOG
Burn-in
1015. B
160 hour. +12S'C
steady-state
Electrical Test
Burr-Brown
test procedure
Hermeticity: Fine Leak
Gross Leak
1014, AI or A2
1014.C
Final Electrical
Burr-Brown
test procedure
Final Drift
Burr-Brown
test procedure
DISCUSSION OF
SPECIFICATIONS
The ADC85H series is specified to provide critical
performance criteria for a wide variety of applications.
The most critical specifications for an AI D converter are
linearity, drift, gain and offset errors, and conversion
speed effects on accuracy. These ADCs are factorytrimmed and tested for all critical key specifications.
5 X 10-7 atm cc/s
bubble test only.
preconditioning
GAIN AND OFFSET ERROR
Initial Gain and Offset errors are factory-trimmed to
±O:l% of FSR (±0.05% for unipolar offset) at 25°C.
These 'errors may be trimmed to zero by connecting
external trim potentiometers as shown in Figures 6 and 7.
omitted
External Visual
QCSISO'
'" Available upon request.
99
ACCURACY DRIFT VS TEMPERATURE
Three major drift parameters degrade AI D converter
accuracy over temperature: gain, offset and linearity
drift. The worst-case accuracy drift is the summation of
all three drift errors over temperature. Statistically, these
errors do not add algebraically, but are random variables
which behave as root-sum-squared (RSS) or 10 errors as
follows:
RSS = . .J eg2 + e0 2 + ee2
where eg = gain drift error (ppm 1°C)
EO = offset drift error (ppm of FSRrC)
ee = linearity error (ppm of FSR/°C)
For the ADC85H-12 operating in the unipol~r mode, the
total RSS drift is ±15.42ppmloC and for bipolar operation the total RSS drift is ±16.7ppml°C.
ACCURACY VS SPEED
In successive approximation AID converters, the conversion speed affects linearity and differential linearity
errors. The power supply sensitivity specification is a
measure of how much the plus full-scale value will
change from the initial value for independent changes in
each power supply. This change results in a proportional
change in all code transition values (i.e., a gain error).
The conversion speeds are specified for a maximum
linearity error of ±1/2LSB with the internal clock.
Faster conversion speeds are possible but at a sacrifice in
linearity (see Clock Rate Control Alternate Connections).
POWER SUPPLY SENSITIVITY
Changes in the DC power supplies will affect accuracy.
Normally, regulated power supplies with 1% or less
ripple are recommended for use with these ADCs. See
Layout Precautions and Power Supply Decoupling.
~
iii t
0.1
0.08
0.06
0.04
~>
a: g>
LAYOUT PRECAUTIONS
Analog and digital commons are not connected internally
in the ADC85H series, but should be connected together
as close to the unit as possible, preferably to a large
ground plane under the ADC. If these grounds must be
run separately, use a wide conductor pattern and a
. O.OIILF to O.lILF nonpolarizaed bypass capacitor between
analog and digital commons at the unit. Low impedance
analog and digital common returns are essential for low
noise performance. Coupling between analog inputs and
digital lines should be minimized by careful layout.
POWER SUPPLY DECOUPLING
The power supplies should be bypassed with tantalum or
electrolytic type capacitors as shown in Figure 4 to
reduce noise during operation. These capacitors should
be located close to the ADC. IILF electrolytic type
capacitors should by bypassed with O.OIILF ceramic
capacitors for improved high frequency performance.
~
31
+5VDC •
Dig.
Com.
T
•
1PF
..
I+ •
0.02
-Vee
0.01
~ 1! 0.008
26
1pF
15
T+
28
/+vcc-L
26~
~
10
100
1k
10k
30
Uffer
Direct
Out
Input
~
+
_
125------,24
29
R,
R,
R,
=
..#+5V Supply
1
Com.
.. +15VDC
.INPUT SCALING
The analog input should be scaled as close to the
maximum input signal range as possible in order to
utilize the maximum signal resolution of the AI D converter. Connect the input signal as shown in Table III. See
Figure 5 for circuit details.
Buffer
Input
0.001
Ana.
FIGURE 4. Recommended Power Supply Decoupling.
'0 0 0.006
if'. ~ 0.004
0.002.
15VDC
1pF
16
Jot
I
c.~
e"
w·;
LAYOUT AND OPERATING
INSTRUCTIONS
100k
Frequency (Hz)
C~~p.
22------__----~------~~
Bipolar
23~
,
Offset
FIGURE 3. Power Supply Rejection vs Power Supply
Ripple Frequency.
VAEF
Converter
FIGURE 5. Input Scaling Circuit.
100
TABLE III. Input Scaling Connections.
(a)
For
Buffered
Inputl1l
Input
Signal
Range
Output
Code
±10V
COB orCTC
22
±5V
±2.5V
o to +5V
o to +10V
COB orCTC
COB orCTC
CSB
CSB
22
22
26
26
Connect Connect Connect
Pin 23
Pin 25
Pin 29
To Pin
To
To Pin
Input
Signal 13J
Open
Pin 22
Pin 22
Open
For
Direct
Input!21
Connect
Input
Signal
To Pin
25
25
24
24
24
24
24
24
24
24
NOTES: (1) Connect to pin 29 or input signal as shown in next two
columns. (2) If the buffer amplifier Is not used, pin 30 must be connected
to ground (pin 26). (3) The input signal is connected to pin 30 if the
buffer amplifier is used.
OPTIONAL EXTERNAL GAIN AND OFFSET
ADJUSTMENTS
Gain and Offset errors may be trimmed to zero using
external gain and offset trim potentiometers connected
to the ADC as shown in Figures 6 and 7. Multiturn
potentiometers with lOOppmjOC or hetter TCRs are
recommended for minimum drift over temperature and
time. These pots may be any value from IOkO to 100kO.
All resistors should be 20% carbon or better. Pin 27
(Gain Adjust) should be bypassed with O.OJJ,LF to reduce
noise pickup and Pin 22 (Offset Adjust) may be left open
if no external adjustment is required.
Gain
Adjust
10MCl
27~
To.01pF
26-1
Ana.
Com.
Clock Rate Control Alternate Connections
If adjustment of the "Clock Rate is desired for faster
conversion speeds, the Clock Rate Control may be
connected to an external multiturn trim potentiometer
with TCR of ± 100ppmj °C or less as shown in Figure 8.
If the potentiometer is connected to -15VDC, conversion
time can be increased as shown in Figure 8. If these
adjustments are used, delete the connections shown in
Table IV for pin 17. See Typical Performance Curves for
nonlinellrity error vs. clock frequency, and Figure 9 for
the effect of the control voltage on clock speed. Operation
with clock rate control voltage of less than -IVDC is
not recommended.
1
+5VDC
Clock
17- _ _ __
Rate
Control
.
Camp. In
-15VDC
180kCl
180kCl
~~~
Clock
Frequency
Adjust
20
+15VDC
10kCl to
100kCl
Offset
Adjust
2kClor
5kCl .
FIGURE 8. 12-Bit Clock Rate Control Optional Fine
Adjust.
(b)
1.8MCl
22 -~'.,.,
..,.,
...--........_~
10kCl to
100kCl
Gain
Adjust
FIGURE 7. Two Methods of Connecting Optional Gain
Adjust.
Adjust the Offset potentiometer until the actual end
point transition voltage occurs at Eotl. The ideal transition voltage values of the input are given in Table I.
+15VDC
+15VDC
-15VDC
Adjustment Procedure
OFFSET-Connect the Offset potentiometer as shown
in Figure 6. Sweep the input through the end point transition voltage that should cause an output transition to all
bits off (EOI~I').
(a)
(b)
+15VDC
~
10kClto
100kCl
Offset
Adjust
c:
0
'f!?
~
c:
-= -15VDC
0
(.l
~ 10-Bit Operation
10
I'!!o~
~
""~~
,
12-8ilOperation t--
8-8it Operation.
~
FlGURE 6. Two Methods of Connecting Optional
Offset Adjust.
GAIN-Connect the Gain adjust potentiometers as shown
in Figure 7. Sweep the inpilt through the end point
transition voltage that should cause an output transition
voltage to all bits on (E?~). Adjust the Gain potentiometer until the actual end point transition voltage
occurs at E?~.
Table I details the transition voltage levels required.
15
"E
;::
-1 0
4
10
12
Control Voltage on Pin 17
1415
FIGURE 9. Conversion Time vs Clock Speed Control.
Additional Connections Required
The ADC85H series may be operated at faster speeds for
resolutions less than 12 bits by connecting the Short
Cycle input, pin 14,as shown in Table IV. Conversion
101
speeds, linearity and resolution are shown for reference.
Specifications for lO-bit units assume connections as
shown below.
Converter Initialization
On power-up, the state of the ADC internal circuitry is
indeterminate. One conversion cycle is required to initialize the converter after power is applied.
TABLE IV. Short Cycle Connections and Specifications
. for 8- to 12-Bit Resolution.
Resolution (Bits)
Connect Pin 17 to f11
Connect Pin 14 to
Maximum Conversion Speed (ps)f21
Maximum Nonlinearity at 2S"C (% of FSR)
12
10
Pin 1S Pin 16
Pin 2
Pin 16
10
6
131
0.012
0.048141
Output Drive
Normally all ADC84, ADC85H, and ADC87H logic
outputs will drive two standard TTL loads; however, if
long digital lines must be driven, external logic buffers
are recommended.
.
8
Pin 28
Pin4
4
0.2014'
NOTES: (1) Connect only if clock rate control is not used. (2) Maximum
conversion speeds to maintain ±1/2LSB nonlinearity error. (3) 12-bit
models only. (4) 10- or 12-bit models.
102
BURR-BROWN®
ADC600
IElElI
12-BIT
ULTRA-HIGH SPEED AID CONVERTER
FEATURES
•
•
•
•
•
•
•
•
•
• HIGH RESOLUTION: 12 bils
'!!' !!~~!'!.~ !!~T~: !:!G t!! l!:!M!!!
• HIGH SINAO RATIO: 67dB
• LOW HARMONIC DISTORTION: -71dB
• LOW INTERMODULATION DISTORTION: -70dB
• INPUT RANGE: ±1.25V
• COMPLETE SUBSYSTEM: Contains Sample/Hold
. and Reference
• LOW DISSIPATION: B.5W
• DoC TO +70°C AND -40°C TO +85°C
DIGITAL SIGNAL PROCESSING
RADAR SIGNAL ANALYSIS
TRANSIENT SIGNAL RECORDING
FFT SPECTRUM ANALYSIS
HIGH·SPEED DATA ACQUISITION
JAM·RESISTANT SYSTEMS
SIGINT. ECM. AND EW SYSTEMS
DIGITAL COMMUNICATIONS
DIGITAL OSCILLOSCOPES
DESCRIPTION
The ADC600 is an ultra-high speed analog-to-digital
converter capable of digitizing signals at any rate
from DC to 10 megasamples per second. Outstanding
dynamic range has been achieved by minimizing
noise and distortion. .
-
Samplel
Hold
~
MSB
Flash
Encoder
...
Digital-to
Analog
Converter
The ADC600 is a two-step subranging ADC subsystem containing an ADC, sample/hold amplifier,
voltage reference, timing, and error-correction circuitry. Laser-trimmed ceramic submodules are mounted on a 17-square-inch multilayer PC motherboard.
Logic is ECL.
~~
~
LSB
Flash
Encoder
-
Digital
Error
Corrector
(Adder)
-
Digital
Output
r-
Internalional Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. (602) 746·1111 . Twx: 910·952·1111 . Cable: BBRCORp· Telex: 66-6491
PDS-642A
103.
SPECIFICATIONS
ELECTRICAL
TA = +25°C, 10MHz sampling rate, Rs
otherwise noted.
= 50n,
±Vcc = 15V,
VD01
= +5V,
VOD2
= -S.2V,
and 15-minute warmup in normal convection environment, unless
ADC600K
PARAMETER
CON'DITIONS
MIN
TYP
ADC600B
MAX
RESOLUTION
MIN
12
INPUTS
ANALOG
Input Range
Input Impedance
Input capacitance
Full scale
-1.25
+1.25
1.5
5
DIGITAL
logic Family
ECll0k-Compatible
Negative Edge
Convert Command
Pulse Width
10
I
I
TRANSFER· CHARACTERISTICS
·
·
ACCURACY
Gain Error
Input Offset
Integral Linearity Error
Differential Linearity Error
F = 200Hz
DC
F=200Hz
F = 200Hz: 68.3% of all codes
99.7% of all codes
100% of all codes
±0.1
±0.1
Missing Codes
±0.5
±0.5
1.25
0.25
1.00
+1.25
-1.00
none
CONVERSION CHARACTERISTICS
Sample Rate
DC
First conversion
'Conversion Time
140
10M
150
·
DYNAMIC CHARACTERISTICS
Differential Linearity Error
F = 4.9MHz: 68.3% of all codes
99.7% of all codes
100% of all codes
0.5
1.5
2.0
Total Harmonic Distortion C2!
F=
F' =
F=
F=
4.8MHz (OdB)
O.58MHz (OdB)
2.4MHz (OdB)
0.58MHz (OdB)
Fs='10MHz
-71
-74
Fs = 5MHz
-73
-74.5
Two-Tone Intermodulation Distortion c2J1.. J
F = 4.88MHz (-6dB)
4.65MHz (-6dB)
F = 2.40MHz (-6dB)
2.25MHz (-6dB)
SignaHo-Noise and Dislortion (SINAD)
Fs= 10MHz
-70.5
Fs=.5MHz
-74.5
Fs =10MHz
65.8
66.6
67.2
69
6
±5
Ratio
F=
F=
F=
F=
4.8MHz (OdB)
0.58MHz (OdB)
2.4MHz (OdB)
0.58MHz (OdB)
I
Fs=5MHz
Aperture Time
Aperture Jitter
Analog Inpul Bandwidlh
Small Signal
Full Power
-20dB input
OdB input
70
40
OUTPUTS
Logic Family
Logic Coding
Logic Levels
EOC Delay Time
Trand Tf
Data Valid Pulse Widlh
Logie "LO"
logic "HI"
Data Out 10 DV
20% to 80%
50%
5
5
Operating
VOD1
VOD2
Supply Currents: +Vcc
+14.25
-14.25
+4.75
-4.95
Operating
-Vee
VODl
VOD2
Power Consumption
Operating
104
+15
-15
+5
-5.2
75
45
400
900
8.5
+15.75
-15.75
+5.25
-5.46
..·
··
··
MAX
·
·· ·
··
·· ··
·
···
··
· ··
··
·
··
··
·
·
··
··
··
··
··
··
·
··· ···
··· ·
···
ECl with pull-down to -VOD2 (see text)
Offset Binary. Twos Complement
-1.7
-0.9
35
5
8
POWER SUPPLY REOUIREMENTS
Supply Voltages: +Vcc
-Vee
TYP
UNITS
Bits
V
Mil
pF
ns
%FSR
% FSR llI
LSB
LSB
lSB
LSB
LSB
Samplesls
ns
LSB
lSB
LSB
dBC'"
dBC
dBC
dBC
dBC
dBC,
dB
dB
dB
dB
ns
ps
MHz
MHz
V
V
ns
ns
ns
V
V
V
V
rnA
rnA
rnA
rnA
W
ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS)
±V6c == 15V, V00 1 = +SV,
VOD2;;;;
-S.2V, As:::: 500,15-minute warmup, and
TA
= TMIN to Tw.x, unless otherwise noted.
ADC600K
PARAMETER
CONDITIONS
MIN
TYP
ADC600B
MAX
MIN
+70
+100
-40
TEMPERATURE RANGE
Specific~tion
TCASE
Storage
0
-40
max
TAMBIENT
TYP
.
F = 200Hz
DC
F= 200Hz
F=200Hz
63% of all codes
98% of all codes
100% of all codes
Differential Linearity Error
..
±30
±50
1.5
Sample Rate
DC
0.5
1.25
1.5
10
UNITS
·
'C
'C
+85
ACCURACY
Gain Error
Input Offset
Integral Linearity Error
MAX
ppm/'C
pV/'C
LSB
·
··
··
.
LSB
LSB
LSB
MHz
'Same as ADC600K
NOTE: (1) FSR: full-scale range = 2.5Vp-p. (2) Units with tested and guaranteed distortion specifications are available on special order-inquire.
(3) dBC = level referred to carrier (input Signal = OdB); F = input Signal frequency; F. = sampling frequency. (4) IMD is referred to the larger of the two
input test Signals. If referred to the peak envelope signal (= OdB), the intermodulation products will be 6dB lower.
MECHANICAL
4.500
±0.010
, -
1
l'
' , - I
-,
,~~~]
r
/151
0.156 Diameter
4 Places
A B 0.007
r-r=====~3g8~~DED~7-DII~~~U~'~~~1
115DD
CEl
~~
B
@J
I I
;;~~
1
Pin Location
40 Places
101 AI BI 0.002<9)1
--
Mating Lead Socket: Mill-Max 0314 or equivalent.
A
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
TJ
±Vcc "." .. ,', ..• ,.,", •. " •.••..•••..••.•••.••••.••••.•• ±16.5V
VDD, .•....•.•...•...•...•••..• : ..••..•..••••.•••••••..••••. +7.0V
VDD.2 ....................................................... -7.0V
Analog Input ... , .......................................... ±5.0V
Logic Input ......................................... VDD• to +0.5V
Case Temperature ••••••...••......••...•......•.•...•..•.. 100'C
Junction Temperature 'll .................................... 150°C
Storage Temperature .....••.•........•..•••..••• -40'C to +100'C
Stresses above these ratings may cause permanent damage to the
device.
ADC600 X 0
Basic Model Number _ _ _ _ _ _ _ _ _ _==r-_..J
Performance Grade Code
K = O'C to +70'C
B = '-40 to +85'C
-
Reliability S c r e e n i n g - - - - - - - - - - - - - - - - '
Q = Q-Screened
(1). See Table I for thermal resistance data.
105
achieving high conversion speed without sacrificing accuracy is a difficult task.
The analog input signal is sampled by a high-speed
sample/hold amplifier with low distortion, fast acquisition time and very low aperture uncertainty (jitter); A
diode bridge sampling switch is used to achieve an
acceptable compromise between speed and accuracy.
The diode bridge switching transients are buffered from
the analog input by a high input impedance buffer
amplifier. Since the hold capacitor does not appear in
the feedback of the diode bridge output buffer the
capacitor can acquire the signal in 25ns. The low-biascurrent output buffer is then required to settle to only
the resolution (7 bits) ofthe first (MSB) flash encoder in
25ns while an additional 60ns is allowed for settling to
the resolution (12 bits) of the second (LSB) flash encoder.
Sample/hold droop appears as only an offset error and
does not affect linearity.
Both the MSB and the LSB flash encoder (ADC) are
high-speed 7-bit resolution converters formed by parallelconnecting two 6-bit flash ADCsas shown in Figure 2.
The DAC +IOV reference is also used to generate
reference voltages Cor the MSB and LSB encoders to
compensate drift errors. Buffering and scaling are performed by 1m and Ic2. Laser-trimming is used to minimize
voltage offset errors and optimize gain (input full-scale
range) symmetry.
The subtraction DAC is an ECL 7-bit resolution DAC
with l4-bit accuracy. Laser-trimmed thin-film nichrome
resistors on sapphire and high-speed bipolar circuitry
allow the DAC output to settle to l4-bit accuracy in only
25ns.
A "remainder" or coarse conversion-error voltage is
generated by resistively subtracting the DAC output
from the output of the sample/hold amplifier. Before the
second (LSB) conversion, the "remainder" is amplified
by a wideband Cast.-settling amplifier with a gain of
32V/V. ,To prevent overload on large amplitude transients, a high-speed FET switch blanks the amplifier
input from the beginning of the S/H acquisition time to
end of the MSB encoder update time.
The timing circuits shown in Figure 3 supply all the
critical timing signals necessary for proper operation of
the ADC600. Some noncritical timing signals are also
generated in the digital error correction circuitry. Timing
signals are laser-trimmed for both pulse width and delay.
The ECLJogic timing delay is stable over a wide range of
temperatures and power supply voltages. Basic timing is
derived from the output of a three-stage shift register
driven by a synchronized 20MHz oscillator.
The convert command pulse is differentiated by IC I to
allow triggering by pulses from as narroW as 5ns to as
wide as 75% duty cycle. This differentiated signal sets
flip-flop IC2, placing the Sf H back into its sample mode .
The output of the third stage of the shift register is also
differentiated by ICg and used to generate a strobe for
the LSB flash encoder. RI is laser-trimmed to generate a
precise 8ns pulse while the oscillator frequency is adjusted
to trim the strobe pulse delay. IC4 and ICs comprise the
PIN ASSIGNMENTS
1
2
3
4
S
6
7
8
9
10
11
12
13
14
1S
16
17
18
19
20
Common
Common
21
22
23
24
2S
26
27
28
29
VDD. (-S.2V)
30
Common
Common
31
32
+Vee(+1SV)
-Vee (-1SV)
VDD2 (-S.2V)
Voo. (+SV)
33
-Vee (-1SV)
VDrn (-S.2V)
VDD• (+SV)
+Vee (+1SV) .
Common
VDD• (-S.2V)
VDD. (+5V)
Common
Dala Valid
Bil12 (LSB)
Bil11
BI110
Bil9
Bil8
BI17
BI16
BilS
Bil4
Bit 3
Bil2
BI11 (MSB)
Bii1 (MSB)
VDrn (-S.2V)
34
3S
36
37 Common
38 Convert Command
39 Anal<;>9 Inpul
40 Analog Inpul Relurn
Common
VDD• (-S.2V)
VDD• (+SV)
VDD. (-S.2V)
tyPICAL PERFORMANCE
CURVE
ANALOG INPUT BANDWIDTH
+2
iii'
:!!.
5l
c
i
"S
~
r- L 1~oJv~pl,
+1
,
o
-1
-2
~
-3
-4
'0
'0
-S
0.
-6
~
~
-7
-8
0.1
0.2
0.6
1
6
10
20
60 100
Frequency (MHz)
THEORY OF OPERATION
The ADC600 is a two-step subrlmging analog-to-digital
converter. This architecture is shown in Figure 1. The
major system building blocks are: Sample/Hold Amplifier, MSB Flash encoder. DAC and Error Amplifier,
LSB Flash Encoder, Digital Error Corrector, and Timing
Circuits. The ADC600 uses individually tested and lasertrimmed submodules mounted on a four-layer motherboard to integrate this complex circuit into a complete
analog-to-digital converter subsystem with state-of-theart performance.
Conceptually, the subranging technique is simple: sample
and hold the input signal,convert to digital with a coarse
. ADC, convert back to analog with acoarse-resolution
(but high-accuracy) DAC, subtract this voltage from the
S / H output, amplify this "remainder," convert to digital
with a second coarse ADC, and combine the digital
.output from the first ADC (MSB) with the digital output
from the second ADC (LSB): In practice, however,
106
Encoder
LSB Flash Encoder
I-'+-----"\. Digital
ht----v' Output
~~---v~~-v~~
1--+1------- ~~~~
LSB Strobe
MSBStrobe
Amphfier
Enable
' - - - - - - - - - - - - - - - - - - - t S a m p l e / H o l d Gate
>-=C.::o"'nv:..:e::.rt:..C::.o:..:m=m.::a"'nd=--_ _ _ _ _ _ _ _ _ _-t Start
Timing
FIGURE I. Block Diagram of l2-Bit IOMHz ADC600.
________~R~3~ 2' (MSB)
+Reference
r+R~;m~~
a-Bit
Flash
Encoder
Analog In
From
Sample/Hold
N------l'-----<- 2'
t-:!:+:;:==:=j=::::::
...
2'
24
H++-1>----+--- 2'
H-++i-t--ir--- 2'
L:-~R~ef~e~rn~n~c~e.tt-t1rt-rlr~-~27
1000
+Reference
6-Bit
Flash
Encoder
No Ground
on MSB Encoder
R5
FIGURE 2. 7-Bit Flash Encoder.
107
Register
Strobe
R2
C2
Convert
Command
C
Amplifier
Enable
Q
IC2
IC3
20MHz
Oscillator
Sample
IHoid
Gate
IC10
Ice
~
~
IC7
,
•
~
MSB
Strobe
FIGURE 3. Schematic of Timing Module.
principal elements of a 20MHz ring oscillator. R2 and C2
add additional delay and allow laser-trimming for the
LSB delay. A blanking pulse to prevent error amplifier
overload is generated by the second stage of the shift
register. Proper timing is generated by laser-trimming R3
which, along with C3 forms a delay element along with
two gates of IC;.
A strobe pulse of the MSB flash encoder is generated
and trimmed in a similar circuit using IC7• This technique
generates a variable width S/H gate pulse which is
determined by the conversion command pulse period
minus the fixed 67ns AOC conversion time AOC600
conversion rates are therefore possible above the 10M Hz
specification but S/H acquisition time is sacrificed and
accuracy is rapidly degraded.
The output of the MSB encoder is read into a separate
7-bit latch at the same time the LSB encoder is being
strobed. The latched MSB data, along with the LSB
data, is then read into a 14-bit latch 30ns after the leading
edge of the LSB strobe and before being applied to the
adder, where the actual error correction takes place. This
latch eliminates any critical timing problems that would
result when the converter is operated at the maximum
conversion rate.
The function of the digital error correction circuitry
(Figure 4) is to assemble the 7-bit words from the two
flash encoders into a 12-bit output word. In addition, the
circuit uses the LSB flash encoder strobe to generate
timing strobes for both data registers. A data valid (OV)
pulse is also generated which is used to indicate when
output data can be latched into an external register. This
OV pulse is delayed Sns after the output data has settled
to allow a sufficient set-up time for an external ECL data
latch.
The 14-bit register output is then sent to a 12-bit .adder
where the final data output word is created. The MSB
data forms the most significant seven bits of a l2-bit
word, with the last five bits being assigned zeros. In a
similar fashion, the LSB data from the least significant
bits form the other input to the adder with the first five
bits being assigned zeros. As two l2-bit words are being
added, the output of the adder could excee,d 12 bits in
range; however, the final data output is only a 12-bit
word, so a means of detecting an overrange is included.
To prevent reading erroneous data, the converter data
output reads all ones for a full-scale positive input or
overrange and reads all zeros for a negative full-scale
input or overrange. The d~ta output does not "roll-over"
if the converter input exceeds its specified full-scale
'
range of ±I.2SV.
DISCUSSION OF
PERFORMANCE
DYNAMIC PERFORMANCE TESTING
The AOC600 is a very high performance converter and
careful attention to test techniques is necessary to achieve
accurate results. Spectral analysis by application of a
Fast Fourier Transform (FFT) to the AOC digitial output will provide data on all important dynamic performance parameters: total harmonic distortion (THO),
signal-to-noise raito (SNR) or the more severe signal-tonoise-and-distortion ratio (SINAO), total noise and distortion (TNO), and intermodulation distortion'(IMO).
108
Register Strobe
Data Valid
Carry Out
Bit t
2'
7-Bit
Latch
7-Bit
Latch
A
2'
,,
,,
Bit 2
,
,,
14-Bit
Latch
and
12-Bit
Adder
I
I
7-Bit
Data From
________________-,,/
LSBEnc~o~d~er
B
Latch
2"
2"
I Bit 11
Bit 12
FIGURE 4. Block Diagram of Digital Error Corrector.
A test setup for performing high-speed FFT testing of
analog-to-digital converters is shown in Figure S. This
was used to generate the typical FFT performance
curves shown on pages 112 through I1S.
To prese1'¥e measurement accuracy, a very low side-lobe
window must be applied to the digital data before
executing an FFT. A commonly used window such as
the Hanning window is not appropriate for testing high
performance converters; a minimum four-sample Blackman-Harris window is strongly recommendedY) To
assure that the majority of codes are exercised in the
ADC600 (12 bits), a ten-sample average of Sl2-point FFTs
is taken.
Dynamic Performance Definitions
I. Signal-to-Noise-and-Distortion(2) Ratio (SINAD):
10 10 sine wave signal power
g nOIse
. +h armomc
. power
2. Total Harmonic Distortion (THD):
10 log harmonic power (first nine harmonics)
sinewave signal power
3. Total Noise Distortion (TND):
10 10
noise power
g smewave
.
.
I power
signa
4. Intermodulation Distortion (IMD):
10 10 IMD product power,
g.
. al
smewave sign power
IMD is referenced(3' to the larger of the test signals f, or f2 •
Five "bins" either side of peak are used for calculation of
fundamental and harmonic power. The "0" frequency
bin (DC) is not included in these calculations as it is oflittie importance in dynamic signal processing applications.
Attention to test set-up details can p'revent errors that
109
contribute to poor test results. Important points to
remember when testing high performance converters are:
I. The ADC analog input must not be overdriven. Using
a signal amplitude slightly lower than FSRwill allow a
small amount of "headroom"so that noise will not
overrange the ADC and "hard limit" on signal peaks.
2. Two-tone tests can produce signal envelopes that
exceed FSR. Set each test signal to slightly less than
-6dB to prevent "hard limiting" on peaks.
3. Low-pass filtering (or bandpass filtering) of test signal
generators is absolutely necessary for THD and IMD
tests. An easily built LC low-pass filter (Figure 6) will
eliminate harmonics from the test signal generator.
4. Test signal generators must have exceptional noise
performance (better than -IS5dBC) to achieve accurate SNR measurements(4). GO,od generators together
with fifth-order elliptical bandpass filters are recommended for SNR' and SINAD tests.
5. The analog input of the ADC600 should be terminated
directly at the input pin sockets with the correct filter
terminating impedance (SOO or 7S0) or it should be
driven by an OPA600 buffer. Short leads are necessary
to prevent digital noise pickup.
6. A low-noise (jitter) clock signal (convert command)
generator is required for good ADC dynamic performance. A recommended interface circuit is shown in
Figure 7. Short leads are necessary to preserve fast,
ECL rise times.
t
7. Two-tone testing will require isolation between test
signal generators to prevent IMD generation in the
test generator output circuits. An active summing
amplifier using an OPA600 is shown in Figure 8. This
circuit will provide excellent performance from DC to
Power Supplies
±15V +5V
-5V
(Probe Signals)
Status
Burr·Brown
AOC600
Test Fixture
0106 A146-2 Rev. C
GPIS
Analog
Output
Tektronix
4052A
Graphics
Computer
FIGURE 5. Test Setup for High Speed FFT Testing.
5MHz with harmonic and intermodulation distortion
products typically better than -70dBC. A passive
hybrid transformer signal combiner can also be used
(Figure 9) over a range of about IMHz to 30MHz.
The port-to-port isolation will be ".. 45dB between
signal generators and the input-output insertion loss
will be ".. 6dB.
8. A very low side-lobe window must be used for FFT
. calculation. A minimum four-sample Blackman-Harris
window function is recommendedY)
9. Digital data must be latched into an external ECL
12-bit register only by the Data Valid output pulse.
Due to the possibility of improper timing, output data
cannot be latched by using the convert command!
10. Do not overload the data output logic. These outputs
are already provided with internal 68n pull-down
'
resistors tied to -S.2V.
II. A well-designed, clean PC board layout will assure
proper operation and clean spectral response(S)(6).
Proper grounding and bypassing, short lead lengths
and separation of analog and digital signals and
ground returns are particularly important for high
frequency circuits. Multilayer PC boards are recommended for best performance, but a two-sided PC
board with large, heavy (20z-foil) ground planes can
give excellent results, if carefully designed.
Prototyping "plug-boards" or wire-wrap boards will
not be satisfactory.
NOTES:
1. On the Use of Windows for Harmonic Analysis with the Discrete Fourier
Transform, Fredric J. Harris. Proceedings of the IEEE, Vol. 66, No. I,
January 1978. pp 51-83.
2. SINAD test includes harmonics ~hereas SNR does not include these important
spurious products.
'
3. If IMD is referenced to peak envelope power, an improvement of 6dB.
4. ·Test Report: EFT Characterization of Burr-Brown ADC600K, Signal Conversion Ltd., Swansea, Wales, U.K.
5. MEeL System Design Handbook, 3rd Edition, Motorola Corp.
6. Motorola MECL. Motorola ~orp.
50n
L,
L.
son
L.
L.
In~
@out
r
IT
or
C9.
+
9th Order 0.5dS Ripple
Tchebychev Low-Pass Filter
Attenuation at 2X cutoff frequency = 90dS.
Cutoff frequency = -3dS frequency; to convert cutoff frequency to
-0.5dB frequency. multiply all LC values by 0.9897.
Culoff
Freq.
(MHz)
C,
C,
C,
C,
C,
L.,
L.
L,
(pF)
(pF)
(pF)
(pF)
(pF)
(PH)
(!JII)
(PH)
L,
(!JII)
2.056
4.11
8.23
16.45
2.216
4.43
8.86
17.73
2.216
4.43
8.86
17.73
2.056
4.11
8.23
16.45
5.0 1134.6 1729.2
2.5
2269 3458
1.25 4538 6917
0.625 9077 13.833
1765.6 1729.2 1134.6
3531 3458 2269
7062 6917 4538.
14.125 13.833 9077
FIGURE 6. Ninth-Order Harmonic Filter.
110
-5.2V
82n
ADC600
Convert
Command
38
L
'''\
_50n
MC10115
ECL Line
Receiver
,
ECL Inpul
From
Generator
49.9n
120n
"'if"
po
FIGURE 7. Optional Convert Command Interface Circuit.
1kn
r---~~~--------~
+15V,
Optional transmission line
back·termination resistor;
increases insertion loss by
6dB.
r- - - ,
I
I
~
.Jr.
50n
Oulpul
..
1kn
50n~
49.9n
In . .
49.9n
Bandwidlh: DC 10 ;;, 70MHz
Insertion Loss: OdB
FIGURE 8. Active Signal Combiner.
50n Oulpul
49.9n
50n
In
@-
49.9n
Jr
~
•
49.9n
10 lurns #24 AWG bitilar wound on
Amidon FT 50-4310roid core.
II
II
II
II
II
Bandwidlh: -lMHz 10 = 30MHz
In-Io-In Isolal;'on: = 45dB al5MHz
In-Io-Oul Loss: - 6dB
FIGURE 9. Passive Signal Combiner.
111
TYPICAL FFT SPECTRAL PERFORMANCE
All FFT data: 512-point FFT, 10-sample average; minimum 4-sample Blackman-Harris Window.
Sample Rate = 10MHz,Input Vollage = Full·Scale (OdB)
Frequency (MHz)
0
-10
-20
Level re:
Full·Scale
-30
~
CD
:!'!. -40
"
~
4.8438MHz Fundamental = -0.7
Harmonics: 21 ;:::: -80.5
31 = -74.7
41 = -86.6
-50
C.
E
..: -60
SINAD =' 67.2dB
TND = -69.5dBC
THD = -71.0dBC
-70
-80
-90
-100
Frequency (MHz)
-10
-20
10
:e
"
~
Level re:
Full·Scale
-30
~
-40
0.6055MHz Fundamental = -0.6
"0
Harmonics: 2f ;::;: -84.7
-50
31 = -84.6
41 = -87.5
C.
E
..:
-60
SINAD = 69.6dB
TND = -70.7dBC
THD = -76.4dBC
-70
-80
-90
-100
Frequency (MHz)
-6
-16
-26
Level re:
Full·Scale
-36
10
:e
~
F,: 4.9219MHz = -6.3
F,: 4.6484MHz = -6.3
Peak Envelope = -0.6
-46
~
"0
.ec.
E
<
-56
-66
IMD: 0.4883MHz = -80.8
4.1797MHz = -76.3
4.4336MHz = -78.9
-76
-86
-96
-106
112
'TYPICAL FFT SPECTRAL PERFORMANCE (CONT)
All FFT data: 512-point FFT, 10-sample average; minimum 4-sample Blackman-Harris Window.
Sample Rate
= 10MHz, Input Voltage = Hall-Scale (-6dB)
Frequency (MHz)
0
2
3
0
-10
II,
III
-20
Level re:
Full-Scale
-30
iii'
I"il
~
-40
'"
-50
"ill
-50
tiilill
"',,1
-70
:I,:il]!
-80
!ii
~
0.
E
..:
III,!'i
1
1
~
4.B438MHz Fundamental = -5.B
Harmonics: 2f
=
-85.4
31 = -89.1
41 = -90.1
1::::1:
SINAO
TNO
THO
= 54.0dS
= -65.2dBC
= -70.2dSC
-90
-100
Frequency (MHz)
0
2
3
0
-10
-20
Level re:
Full-Scale
-30
~
iii'
~
-40
~
'"
-50
0.
E
..:
-50
0.5055MHz Fundamental = -5.5
Harmonics: 2f :;:: -86.6
=
31
-84.2
41 = -84.9
SINAO = 53.7dS
-55.,1dSC
TNO
THO
-69.2dBC
-70
=
=
-80
-90
-100
Frequency (MHz)
0
-12
-22
-32
iii'
-42
'"
.~
-52
Level re:
Full-Scale
~
~
'0
0.
E
F,: 4.9219MHz = -12.35
F,: 4.5484MHz = -12.45
Peak Envelope = -5.7
-62
..: -72
IMO: 0.2734MHz
0.4883MHz
4.7555MHz
-82
-92
-102
-112
113
= -85.5
= -84.5
= -85.3
TYPICAL FFT SPECTRAL PERFORMANCE (CO NT)
All FFT data: 512-point FFT, 10-sample average; minimum 4-sample Blackman-Harris Window.
Sample Rate: 5MHz, Input Vollage : Full-Scale (OdB)
2.5
Level re:
Full-Scale
~
: 2.4121 MHz Fundamental:
Harmonics: 21 :
31:
41:
-0.6
-77.9
-83.1
-85.3
SINAO : 67.3dB
TNO : -68.5dBC
THO: -73.3dBC
2.5
Level re:
Full-Scale
~
0.5859MHz Fundamental :
Harmon ies: 21 :
31:
41:
-0.7
-81.4
-87.2
-87.0 .
SINAO : 69.6dB
TNO : -70.7dBC
THO: -76.1dBC
2.5
Level re:
Full-Scale
~
F,: 2.2461MHz : -6.3
F.: 2.4023MHz : -6.4
Peak Envelope : -0.7
IMO: 0.3809MHz :. -81.2
2.0996MHz : -82.9
2.4707MHz : -83.9
114
TYPICAL FFT SPECTRAL PERFORMANCE (CO NT)
All FFT data: S12-point FFT, 1D-sample average; minimum 4-sample Blackman-Harris Window.
Sample Rate = 5MHz, Input Voltage = Hall-Scale (-6dB)
Frequency (MHz)
0
O.S
1
1.S
2
2.S
0
-10
-20
Level re:
Full-Scale
-30
iii
~
:2- -40
'"
:E
'C
2.4121MHz Fundamental = -6.6
-SO
Harmonics: 2f = -87.6
'li
E -60
31 = -80.4
41 = -88.3
«
-70
SINAO = 64.3dB
TNO = -6S.7dBC
THO = -69.9dBC
'-80
-90
-100
Frequency (MHz)
0
O.S
1
,
1.S
2.S
0
-10
-20
Level re:
Full-Scale
-30
~
iii
.,
':2-
-40
0.S8S9MHz Fundamental = -6.6
Harmonics: 21 = -84.6
31 = -8S.9
41 = -87.8
'C
:E
-SO
«
-60
'li
E
SINAO = 64.8dB
TNO = -6S.9dBC
THO = -71.3dBC
-70
-80
-90
-100
Frequency (MHz)
0
O.S
1
1.S
2.S
-12
-22
-32
Level re:
Full-Scale
-42
~
iii
:2- -S2
:E
"
-62
'li
E
«
-72
'C
F,: 2.2461MHz
t=.: 2.4023MHz
= -12.4
= -12.4
Peak Envelope = -6.8
IMO: 1.6406MHz = -87.S
1.87S0MHz = -86.7
2.4609MHz = -86.0
-82
-92
-102
-112
115
DIGITIZING INPUT WAVEFORMS
The response of the ADC600 is illustrated by the digitized
waveforms of Figure 10. The 4.99MHz sine wave near
the Nyquist limit is virtually identical to much lower
frequency sine wave input. The under-sampled 19.999MHz
sine wave illustrates the ADC600's excellent analog
input full-power bandwidth. Figure 11 shows a block
diagram of this high-speed digitizer.
HISTOGRAM TESTING
Histogram testing is used to test differential nonlinearity
of the ADC600. This system block diagram is shown in
Figure 12 and histogram test results for a typical converter
are shown in Figure 13. Note that differential nonlinearity
is 1/2LSB at 200Hz and it shows virtually no degradation
near the Nyquist limit of 5MHz; there are no missing
codes present and the peak nonlinearity does not exceed
I LSB. Histogram t~sting is a useful performance indicator
as the width of all codes can be determined.
SPECTRUM ANALYZER TESTING
A beat-frequency technique (Figure 14) can be used to
view digitized waveforms on an oscilloscope and, with
care, this technique can also be used for testing highspeed ADC dynamic characteristics with an analog
spectrum analyzer.
In this method a test signal is digitized by the ADC600
and the output digital data is latched into an external
ECL latch by the converter Data Valid output pulse
driving a divide-by-N counter. The holding register
drives a 12-bit video-speed DAC which reconstructs the
digital signal back into an analog replica of the ADC600
input. This analog signal also includes distortion products
and noise resulting from the digitization, which can be
viewed on an ordinary RF spectrum analyzer. Typical
results are shown in Figures IS and 16.
. It is important to realize that the distortion and noise
measured by this technique include not only that from
the ADC600, but also the entire analog-to-analog test
10MHz Sample rate. 2.5Vp-p Input signal
F=4.999MHz
. F = 1.000kHz
,/"-. \ r
V
F= 2.499MHz
F = 19.999MHz
FIGURE 10. Digitized Waveforms (512 points).
116
HP 9000. 300
Computer
ECL Data
Latch
And
HighSpeed
RAM
In
HP3325A
Synthesizerl
Function Generator
ADC600
ADC
Cony,
HP3325A
Synthesizer!
Function Generator
Latch
Fs
• Plotter
Out
HP9133
Computer
FIGURE II. High-Speed Digitizer.
'v'w"'",
Clock
Generator
\
HP3325A
Synthesizer
Convert Command
Digital
Analog
Input
Function
Data
12-Bit 10MHz
ADC600
Generator
Handshake
Logic
HP9816
Computer
Data
Valid
HP3456
DVM
IEEE-488
FIGURE 12. Block Diagram of Histogram Test.
system. Nonlinearity of the reconstruction circuit must
be very low to measure a high performance ADC, and
this places severe requirements on the DAC, deglitcher,
and buffer amplifiers.
Using the high-speed video DAC63 in the analog reconstruction circuit aliows excellent test circuit linearity to
be achieved. Clocking the DAC (demodulating) at felN
allows a longer settling time and keeps linearity high in
the digital-to-analog portion of the test circuit. Spectrum
analyzer dynamic range can be a limiting factor in this
method and a sharp notch filter can be used to attenuate
the high-level fundamental frequency. Attenuating the
fundamental allows the spectrum analyzer to be used on
a more sensitive range without generating distortion
products within the input of the analyzer.
Note that even though the signal is demodulated at a
frequenpy of sample ratejN (here N = 2 or 4), the
distortion products still maintain a correct frequency
relationship to the fundamental. While this analog tech. nique shows excellent performance, it cannot exclude
'some distortion products unavoidably generated within
the analog reconstruction portion of the test system. For
this reason, the digital FFT technique is capable of more
accurate high-speed analogi digital converter dynamic
performance measurements.
TIMING
The ADC600 generates .all necessary timing signals in
laser-trimmed submodules. Only the timing between
Convert Command, Output Data, and Data Valid must
117
DL Histogram
DL Histogram
Frequency = 200Hz
Frequency = 4.9MHz
Differential
Nonlinearity
Dillerentlal
Non.
linearity
FIGURE 13. Histogram Test Results (10M Hz Sample Rate).
NOTE: Two generators shown
(IMDtest)
FIGURE 14. Analog-to-Analog Spectral Analysis by Beat-Frequency Techniques.
.
\
be considered. Proper timing is shown in Figure 17. The
output data cannot be timed by the conversion clock,
since the data from the 12-bit adder is not guaranteed
until the Data Valid pulse is generated.
Data should be latched into an' external 12-bit ECL
register that can operate reliably with a set-up time of
5ns minimum (Figure IS).
Logic conversion to TTL can be accomplished by logic
level translator ICs (such as 10125 or 10124), but care
must be exercised, since TTL is very noisy and maintaining a clean analog signal can be difficult. To preserve
the low noise of ECL logic, any conversion to TTL
should be done on a separate circuit board which is
driven by differential ECL drivers.
THERMAL' REQUIREMENTS
The ADC600 is tested and specified over a temperature
range ofO°C to +70°C (K grade) and -40°C to +S5°C (B
grade). The converters are tested in a forced-air environment with a 10 SCFM air flow. The ADC60U can be
operated in a normal convection ambient-air environment
if submodule case temperature does not exceed the upper
limit of its specification.!')
High junction temperature can be avoided by using
forced-air cooling, but it is not required at moderate
ambient temperatures. Worst-case junction temperature
«(he) and top-surface submodule (8CA) are presented in
Table I to aid the designer in determining cooling
requirements.
L FASr Applications Handbook, 1987. Fairchild Semiconductor Corp.'
2. Fairchild Advanced CMOS Techn%gy, Technology Seminar Notes. 1985.
3. Impedance Matching 1Weaks Advance CMOS IC Testing, Gerald C. Cox,
Electronic Design, April, 1987.
4. Grounding for Electromagnetic Compatibility. Jerry H. Bogar. Design News,
23 February, 1987.
I. Maximizing Heat Transfer from PCBs, Machine Design, March 26, 1987,
Jeilong Chu~g.
118
Fs = B.OOOMHz. F = 1.73MHz. 2.5Vp-p Input Level (OdB)
-20
-30
-40
iii' -50
~
:;
.e
6
C)
0
-60
OJ
c:
«
-70
-BO
21s
,
,
31s
Sis
"--
a
1
61s
,
.; I
!
~
i
A
jTr·~~~
o
IFBW=1kHz
100
200
300
400
500
600
Frequency (kHz)
700
BOO
900
1K
-- = Notch Filter Loss Correction
FIGURE 15. Analog-to-Analog Harmonic Distortion.
Notch Filter at Midpoint"""
a
Fs = B.6249MHz F, = 1.93BB5MHz -6dB Input Level
',~
I
I,
I
I
I
I
-10
F, = 1.79517MHz -6dB Input Level
I
I
I
--20
iii'
-30
~
:;
c.
:;
0
-40
C)
0
OJ
c:
«
-50
-60
\2',-',
-70
-~
f2 -1 1
21,-1,
41,-31,
~a..
.-.
31 2 -311
21rll::.
I
.A-
1
1-
-
311 -21 2
I
d..
I ...
.J. .A.
.A
-BO
0
100
200
300
400
500
Frequency (kHz)
FIGURE 16. Analog-to-Analog Two-Tone IMD.
119
600
700
BOO
900
1K
--- = Notch Filter Loss Correction
TABLE I. Cooling Requirement Factors.
Power
25°C Amblent Air
Normal Con.ecllon
DIP
Package
SubmOdule
Dissipation
(W)
BJc(OCIW)
BOA (OCIW)
1\'pe
SHC600
SM10343
SM10344
SM10345
SM10346
SM10347
1.5
1.6
1.6
1.6
2.1
1.1
28.7
17.5
10.6
17.5
8.6
17.3
23.3
24.4
21.3
21.9
24-pin
24-pin
32-pin
24-pin
4o-pin
4o-pin
16T
28.2
other than those specified. Burr-Brown's detailed procedures may vary slightly, model-to-model, from those in
MIL-STD-883. Table III shows the board-level screening
flow for ADC600Q.
TABLE II, Screening Flow for ADC600Q (active components).
Screen
Internal Visual
Burr-Brown
Electrical. Test
Burr-Brown
test procedure
Not Valid
X
'Valid
High Temperature
Storage
(Stabilization Bake)
Not lVaiid
XValid
Ji'Iid
Temperature Cycling
Data Valid
20
I
60
Screening
Le..1
OC4118
Convert Command
I
40
MIL-STD-883,
Method,
Condition
I
P
I
I
I
I
I
I
I
I
80 100 120 140 160 180 200 220 240 260
100S
24 hour, +125°C
1010
10 cycles, -55OC to -125°C
Constant Acceleration
2001. A
2000 G; Y Axis only
Burn":l"
1015,0
160 hour. +S5 or + 70°C,
steady-state
Hermeticity:' Fine Leak
Gross Leak
1014,C
Nanoseconds
FIGURE 17. ADC600 Timing Diagram.
bubble test only,
preconditioning omitted
Final Electrical
Burr-Brown
test procedure
Exiernal Visual
ENVIRONMENTAL SCREENING
The. inherent reliability of a semiconductor device is
controlled by the design, materials, and fabrication of
the device-it cannot be improved by testing. However,
the use of environmental screening can eliminate the
majority of those units which would fail early in their
lifetimes (infant mortality) through the application of
carefully selected accelerated stress levels. Burr-Brown Q
models are environmentally-screened versions of our
standard industrial products, designed to provide enhanced reliability. The screening illustrated in Table II is
performed to selected methods of MIL-STD-883.' Reference to these. methods provides a convenient way of
communicating the screening levels and basic procedures
employed; it does not imply conformance to any other
military standards or to any methods of MIL-STD-883
Burr-Brown
aC5150
TABLE III. Screening Flow for ADC600Q (board level).
Screen
External Visual
MIL-STD-183,
Method,
Condition
Screening
Level
Burr-Brown
ac Specification
Electrical Test
Burr-Brown
Data Sheet
Stablilization Bake
Bum-In
100S
24 hour, +125°C
1015.0
160 hour, +S5°C or
+ 70°C steady-state
Final Electrical
Burr-Brown
Final External
ViSual
Burr-Brown
Data Sheet
Analog ADC Board
ac Specification
Pull-up Resistor
r--~~d."';'''----- Only Required
"FACT~"
For "FACr' Logic
"FAST~."
or
TTL Logic
1. ECL latch provides differential ECL
output which is properly timed
(Valid) data.
2. Data can be transmitted with termin-'
ated cable between boards.
Differential logic keeps ground-
return noise low.
3. Log ic level is translated to TTL by
MC 10125 which is mounted on the
noisy digital logic PC board.
4. Use good bypass capacitor (not
shown) and heavy ground plane
(;?75% copper) PC boards.
FACT'" FAST'" Fairchild
Semiconductor Corp.
VOD2
(-5.2V)
Dual Latch
FIGURE 18. ECL/TTL Logic Interface.
120
THIS PAGE INTENTIONALLY LEFT BLANK
121
THIS PAGE INTENTIONALLY LEFT BLANK
122
BURR-BROWN®
DAC80
DAC80P
IElElI
Monolithic 12-Bit
DIGITAL-TO-ANALOG CONVERTERS
FEATURES
•
•
•
•
•
•
•
•
•
•
INDUSTRY STANDARD PINOUT
LOW POWER DISSIPATION: 345mW
FULL ±lOV SWING WITH Vee = ±12VDC
DIGITAL INPUTS ARE TTL- AND CMOS-COMPATIBLE
GUARANTEED SPECIFICATIONS WITH ± 12V AND
±15V SUPPLIES
SINGLE-CHIP DESIGN
±1I2LSB MAXIMUM NONLINEARITY, DoC to +70°C
GUARANTEED MONOTONICITY, DoC to HO°C
TWO PACKAGE OPTIONS: Hermetic side-brazed
ceramic and low-cost molded plastic
SETTLING TIME: 4118 max to ±O_O1% of Full Scale
DESCRIPTION
This monolithic digital-to-analog converter is pin"
for-pin equivalent to the industry standard DAC80,
first introduced by Burr-Brown. Its single-chip design
includes the output amplifier and provides a highly
stable reference capable of supplying up to 2.5mA to
an external load without degradation of D / A
performance.
. This conllerter uses proven circuit techniques to
provide accurate and reliable performance over
temperature and power supply variations. The use
of a buried zener diode as the basis for the internal
reference contributes to the high stability and low
noise of the device. Advanced methods of laser
trimming result in precision output current and
output amplifier feedback resistors, as well as· low
integral and differential linearity errors. Innovative
circuit design enables the DAC80 to operate at
supply voltages as low as ± II.4V with no loss in
performance or accuracy over any range of output
voltage. The lower power dissipation of this 1I8-mil
bv PI-mil chin re
.5
SEtTLING TIME
.,""'"
Settling time for each DAC80 model is the total time
(i,ncluding slew time) required for the output to settle
within an error band around its final value after a change
in input (see Figure I).
J::
0
-Vee
0.01
'0
-
~
+15V
Supply
.L
~
GAIN ADJ.
ROTATES
THE LINE
INPUT = FFFFH
~+-I-I"""~~+flr-",,-tl-'-+1-+1-;(
DIGITAL INPUT
FIGURE 4. Relationship of,Zero and Gain Adjustments for Unipolar D/A Converters,
DAC708 and DAC709.
OPERATING INSTRUCTIONS
POWER SUPPLY CONNECTIONS
For optimum performance and noise rejection, power
supply decoupling capacitors should be added as shown
in the Connection Diagram. l/-LF tantalum capacitors
should be located close to the D / A converter.
EXTERNAL ZERO AND GAIN ADJUSTMENT
Zero and gain may be trimmed by installing external
zero and gain potentiometers. Connect these potentiometers as shown in the Connection Diagram and adjust
as described below. TCR of the potentiometers should
be lOOppm/oC or less. The 3.9Mfl and 270kfl resistors
(±20% carbon or better) should be located close to the
D j A converter to prevent noise pickUp. If it is not convenient to use these high-value resistors, an equivalent
"Too network, as shown in Figure 3, may be substituted in
place of the 3.9Mfl resistor. A O.OOI/-LF to O.OI/-LF
ceramic capacitor should be connected from GAIN
ADJUST to ANALOG COMMON to prevent noise
pickUp. Refer to Figures 4 and 5 for the relationship of
zero and gain adjustments to unipqJar D j A converters.
RANGE AND
OffSET
ADJUST
FIGURE 5. Relationship of Zero and Gain Adjustments for Bipolar Dj A Converters,
DAC705j706j707 and DAC708j709.
137
TABLE II. Digital Input And Analog Output Voltage/Current Relationships.
VOLTAGE OUTPUT MODELS
Analog Oulpul
Digital
Inpul
Code
One LSB
'FFFFH
OOOOH
Analog Oulpul
'Unlpolar, 010 +10V
16-BII
15·BII
14·BII
Unlls
153
+9,99985
0
305
+9,99969
0
610
+9.99939
0
pV
V
V
Dlgllal
Inpul
Code
Bipolar, ±10V
One LSB
7FFFH
8000H
Bipolar, ±5V
16·BII
15·BII
14·BII
16·BII
15-BII
14-BII
Unlls
305
+9.99980
-10.0000
610
+9.99939
-10.0000
1224
+9.99878
-10.0000
153 .
+4.99980
-5.0000
305
+4.99970
-5.0000
610
+4.99939
-5.0000
pV
V
V
CURRENT OUTPUT MODELS
Analog Oulpul
Digital
Input
Cdd.
On. LSB
FFFFH
OOOOH
Analog Oulpul
Digital
Inpul
Code
'Unlpolar, 0 10 -2mA
16-BII
15·BII
14·BII
Unll.
0.031
-1.99997
0
0.061
-1.99994
0
0.122
-1.99988
0
pA
rnA
rnA
Bipolar, ±lmA
On. LSB
7FFFH
8000H
16·BII
15·BII
14·BII
Units
0.031
-0.99997
+1.00000
0.061
-0.99994
+1.00000
0.122
-0.99988
+1.00000
pA
rnA
rnA
*MSB assumed to be Inverted externally.
Gain Adjustment
Apply the digital input that gives the maximum positive
output voltage. Adjust the gain potentiometer for this
positive full-scale voltage. See Table II for positive fullscale voltages and the Connection Diagrams for gain
adjustment circuit connections.
LOGIC TIMING· Perillal Dr Serlll Olllinpul
low
lew
t. w
two
IoH
INTERFACE LOGIC AND TIMING
DAC70an09
The signals CHIP SELECT (CS), WRITE (WR), register enables (Ao, At, and Ai) and CLEAR (CLR), provide
the control functions for the microprocessor interface.
They are all active in, the '!low" or logic "0" state. CS
must be low to access any of the registers. An and Al
steer the input. 8-bit data byte to the low- or high-byte,
input latch respectively. A2 gates the contents ofthe two
input latches through to the, D/ A latch in parallel. The
contents are then applied to the input of the D / A converter. When WR goes low, data is strobed into the latch or
latches which have been enabled.
The serial input mode is activated when both Ao and Al
are logic "O"·simultaneously. The DO (D8)/SI input data
line accepts the serial data MSB first. Each bit is clocked
in by a WR pulse. Data strobed through to the D/ A
latch by A2 going to logic "0" the same as in the parallel
input mode.
.
'is
Each of the latches can be made "transparent" by maintaining its enable signal at logic "0". However, as stated
above, when both Ao and Al are logic "0" at the same
time, the serial mode is selected.
The ern line resets both input latches to all zeros and
sets the D / A latch to OOOOH; This is the binary code that
gives a null, or zero, at the output of the D / A in the
bipolar mode. In the unipolar mode, activating CLR will
cause the output to go to one-half of full scale.
The maximum clock rate of the latches is 10MHz. The
minimum time between write (WR) pulses for successive
enables is 20ns. In the serial input mode (DAC708 and
DAC709), the maximum rate at which data can be
clocked into the input shift register is 10MHz.
The timing of the control signals is given in Figure 6.
TIMING DIAGRAM
0111 Vilid 18 and II
Over Tall!plrltura
ns. max
ns. min
Wi
80
80
80
80
Ci Vilid 18 and DI Wi
AD. Ai. A2 valid 18 end II Wi
Wrlll pul.. wldtlt
Data hold IlIIr and 01
Wi
0
rlew----l
Ci----~~
I./~-----
~~~J:===~~./.~----I.
:IOW-1
iii,AI,A2"
~=OI~l:SI---------~
Wii--------~,~~,~~
I~r------
10H-1
~
y~-------
!-Iwp=!
FIGURE 6. Logic Timing Diagram.
DAC706/707
The DAC705j706j707 interface timing is the same as
that described above except instead of two 8-bit separately-enabled input latches, it .has a single 16-bit input
latch ,enabled by Ao. The D/ A latch is enabled by AI.
Also, there is no serial-input mode and no CHIP
SELECT (CS) line.
INSTALLATION
CONSIDERATIONS
Due to the extremely-high accuracy of the D / A converter, system design problems such as grounding and contact resistance become very important. For a 16-bit converter with a +IOV full-scale range, ILSB is 153/LV. With
a load current of 5mA, series wiring and connector
resistance of only 30mn will cause the output to be in
error by lLSB. To understand what this means in terms
138
of a system layout, the resistance of typical I ounce
copper-clad printed circuit board material is approximately lJ2mn per square. In the example above, a 10
milliinch-wide conductor 60 milliinches long would cause
a lLSB error.
In Figures 7 and 8, lead and contact resistances are
represented by RI through Rs. As long as the load resistance RL is constant, R, simply introduces a gain error
and can pe removed with gain calibration. R3 is part of
RL if the output voltage is sensed at ANALOG COMMON.
Figures 8 and 9 show two methods of connecting the
currrent output model with an external precision output
op amp. By sensing the output voltage at the load resistor (connecting RF to the output of the amplifier at RL)
the effect of RI and R, is greatly reduced. RI will cause a
gain error but is independent of the value of RL and can
be eliminated by initial calibration adjustments. The
effect of R, is negligible because it is inside the feedback
loop of the output op amp and is therefore greatly
reduced by the loop gain.
DAC706 OR OAC71N1
ANALOG
COMMON
±v""
SUPPLY
FIGURE 9. Alternate Connection for Ground
Sensing at the Load (Current Output
Models).
-v""
DIGITAL
COMMON
In many applications it is impractical to sense the outpUt
voltage at ANALOG COMMON. Sensing the output
voltage at the system ground point is permissible because
these converters have separate analog and digital common lines and the analog return current is a nearconstant 2mA and varies by only IOI'A to 20l'A over the
entire input code range. R. can be as large as 3.0 without
adversely affecting the linearity of the DJ A converter.
The voltage drop across R. is constant and appears as a
zero error that can be nulled with the zero calibration
adjustment.
Another approach senses the output at the load as
shown in Figure 9. In this circuit the output voltage is
sensed at the load common and not at the D JA converter
common as in the previous circuits. The value of R. and
R7 must be adjusted for maximum common-mode rejection across RL. The effect of R. is negligible as explained
previously.
The D JA converter and the wiring to its connectors
should be located to provide optimum isolation from
sources of RFI and EMI. The key to elimination of RF
radiation or pickup is small loop area. Signal leads and
their return conductors should be kept close together
such that they present a small flux-capture cross section
for any external field.
Voo
SUPPLY
v"
FIGURE 7. DAC705j707j709 Bipolar Output Circuit
(Voltage Out).
ENVIRONMENTAL SCREENING
IQM Screening
All BH and SH models are available with Burr-Brown's
JQM environmental screening for enhanced" reliability.
The screening, tabulated below, is performed to selected
methods of MIL-STD-883. Reference to these methods
provides a convenient method of communicating the
FIGURE 8: DAC706j708 Bipolar Output Circuit
(with External Op Amp).
139
screening levels and basic procedures employed; it does
not'imply conformance to any other military standards
or to any methods of MIL-STD-883 other than those
specified below. Burr-Brown's detailed procedures may
vary slightly, model-to-model, from those in MIL-STD883.
SCREENING FLOW FOR /QM MODELS
MIL-STD-883
Screen
Internal Visual
Method
CondlUon
2017
B
1008
C
+150'C. 24hrs
Comments
High Temperature
Storage (Stabilization Bake)
Cycling
1010
C
-6510 +150'C.
10 cycles
Burn-in
1015
B
+125'C. 160hrs
Constant
Acceleration
2001
B
E
10.OOOG
30.000G
Temperature
28-pin pkg.
24-pin pkg.
Hermeticity
Fine Leak
1014
AlorA2
2 X 10-7 atmee/sec
5 X 10-8 atmce/sec
28-pin pkg.
24-pin pkg.
Gross Leak
1014
External Visual
2009
C
60psig.2hr
APPLICATIONS
LOADING THE DAC709 SERIALLY ACROSS AN
ISOLATION BARRIER
A very useful application of the DAC709 is in achieving
low-cost isolation that preserves high accuracy. Using
the serial input feature of the input register pair, only
three signal lines need to be isolated. The data is applied
to pin II in a serial bit stream, MSB first. The WR input
is used as a data strobe, clocking in each data bit. A·
RESET signal is provided for system startup and reset.
These three signals are each optically isolated. Once the
16 bits of serial data have been strobed into the input
register pair, the data is strobed through to the D/A
register by the "carry" signal out of a 4-bit binary synchronous counter that has counted the 16 WR pulses
used to clock in the data. The circuit diagram is given in
Figure 10.
VDD
+
POWER
SUPPLY
VOLTAGE
,
'::'
L -ISOLATION BARRIER
DATA STROBE
SERIAL INPUT
A2
---v-v-v-v-... ~
~"'.!!f15\.!!...l
~
I
ANALOG
OUTPUT
--------1'V
FIGURE 10. Serial Loading of Electrically Isolated
DAC708!709.
.
WR~::::::::::::::::::::::~~
Iftil~~--------------------~
CONNECTING MULTIPLE DAC707s TO A 16-BIT
MICROPROCESSOR BUS
Figure 11 illustrates the method of connecting mUltiple
DAC707s to a 16-bit microprocessor bus. The circuit
shown has two DAC707s ana uses only one address Ime
to select either the input register or the D / A register. An
external address decoder selects the desired converter.
• pP
AoI------4i
FIGURE II. Connecting Multiple DAC707s to a 16Bit Microprocessor.
140.
BURR-BROWN®
DAC729
IElI3I
/
ADVANCE INFORMATION
Subject to Change
Ultra-High Resolution 18-Bit
DIGITAL-TO-ANALOG CONVERTER
FEATURES
_- tll.IIIT
IINr:ftIlITV r.IIIIIIIINTl=l=n
II( r.Rllnl=l
IV . . . . . . . . . . _ . . . . . . .
_ _ .......... ___ '"
_ •••• _ _ ,
• USER ADJUSTABLE TO lB·BIT LINEARITY (K GRADE)
• PRECISION. INTERNAL REFERENCE NOT DEDICATED
• FAST SETTLING. LOW NOISE INTERNAL OP AMP
NOT DEDICATED
• LOW TEN!PERATURE DRIFT
• HERMETIC 40-PIN CERAMIC PACKAGE
• louT OR VOUT OPERATION
Precision
DESCRIPTION
10V
18-Bit
The DAC729 sets the standard in very high accuracy
digital-to-analog conversion. It is supplied from the
factory at a guaranteed linearity of 16 bits, and is useradjustable to 18-bit linearity (ILSB = FSR/262144).
To attain this high level of accuracy, the design takes
advantage of Burr-Brown's thin-film monolithic DAC
process; dielectric op amp process, hybrid capabilities, and advanced test and laser-trim techniques.
The DAC729 hybrid layout is specifically partitioned
to minimize the effect of external load-currentinduced thermal errors. The op amp design consists
of a fast settling precision op amp with a current
buffer within the feedback loop. This architecture
isolates the load from the op amp, which results in a
fast settling (IS/-Ls to 18 bits) op amp 'that boasts an
open-loop gain of over SOOk. The standard 40-pin
package offers full hermeticity, contributing to the
excellent reliability of the DAC729.
Referente
lOUT
DAC
5kfl
5kfl
5kfl
5kfl
I
Inlern,lIon,l Airporllnduslrlal Park· P.O .. 80x 11400· Tucson. Arizona 85734 . Tel. (602) 746·1111 . Twx: 91()'952·1111 • C,ble: 88RCORp· Telex: 66·6491
PDS-749
141
SPECIFICATIONS
ELECTRICAL
Typical at 25'C, ±Vcc = 15VDC.
DAC729JH
MODEL
PARAMETER
MIN
DAC729KH
MAX
TYP
MIN
TYP
MAX
UNITS
·,,
Bits
V
V
I'A
I'A
±0.0007
±0.0015
% of FSR l41
% 01 FSR
%
mV
mV
I'A
I'A
Bits
Bits
INPUT
DIGITAL INPUT
Resolution
Digitallnputs41l : V1H
V"
I)HI VIN
hL. VIN
18
+2.4
0
+VL
+0.8
+5.0
-300
= 2.7V
= DAV
··
·
,
TRANSFER CHARACTERISTICS
ACCURACY'"
Linearity Error(3 )
Differential linearity Error
Gain Error (51
Offset ErrorIS): Voltage, COSIS'
eSSie)
Current, COB
CSB
Monotonicily (O'C to 70'G)
Differential linearity Adjustment Resolution C71
±0.0015
±0.003
±0.10
±10
±0.8
±5
±1
±0.05
±5
±0.5
15
··
,
16
17
DRIFT (Over Specification Temperature Range)
Total Voltage Error Over Temperature (DOC to +70°C)(SI
Total Full-Scale Drift
Gain Drift (Excluding Reference Drift)
Offset Drift (Excluding Reference Drift): COB
CSB
Linearity Error Over Temperature
Differential Linearity Error Over Temperature
,
,
,
,
,
17
18
·
··
·
,
±0.100
±0.18
±3.0
±5.0
±2.0
±1.0
±1.0
±0.050
±9
±1
±2.0
±0.5
±0.5
±0.5
±7
,
,
±15
±0.25
±0.25
±0.50
±0.50
,
% of FSR
ppm of FSR/'C
ppm/'C
ppm of FSR/'C
ppm of FSR/'C
ppm of FSR/'C
ppm of FSR/'C
OUTPUT
VOLTAGE OUTPUT MODE
Ranges: COB
CSB
Output Current
Output Impedance
Short Circuit Duration
±5
.1
I
I
·
0.15
Indefinite to Common
CURRENT OUTPUT MODE
COB Ranges
Output Impedance
CSB Ranges
Output Impedance
Output Current Tolerance
Compliance Voltage
,
-1 to+5
5
4
20
500
0.45
300
8
7
10.000
10.Q10
+4.0
±2.5
±1.0
,
··
,
,
··
·
,
Inderite 10 COlman
+9.990
10
10.010
-1.0
-2.0
142
V
V
mA
0
···
·
±0.1
+9.990
,
,
,
Indefinite to Common
±1.0
2.86
Oto-2
4.0
SETTLING TIME (To ±O.00038% of FSR)'"
Voltage (Load = 2kO II 100pF):
Full-Scale Step
1LSB Step (Major Carryto!
Slew Rale
Switching Transient Peak
Switching Transient Energy
Currenl Full-Scale Step (2mA X 100)
REFERENCE
Output (pin 32): Voltage
Source Current!11J
Temperature Coefficient
Short-Circuit Duration
Input Voltage Tolerance (external)
Reference Load: Unipolar Mode
Bipolar Mode
!
±2.5, ±5, ±10
o to 10, 0 10 5
,
·
·,
Inderite to com1mon
,
··,
.
"
,
mA
kO
mA
kO
% of FSR
V
J1S
I'S
ViI's
mV
V-I'S
ns
V
mA
ppm/'C
V
mA
mA
ELECTRICAL (CO NT)
MODEL
DAC729JH
PARAMETER
DAC729KH
MIN
TYP
MAX
+13.S
-16.S
+4.75
+1S
-15
+5
+30
-40
+1S
1.14
±0.0001
±0.0001
±0.0004
±0.0001
±0.0005
±0.0001
+16.S
-13.5
+5.25
+40
-55
+25
1.55
±0.0005
±O.OOOS
±0.OO1S
±O.OOOS
±0.001S
±O.OOOS
MIN
TYP
MAX
···
···
··
··
··
··
··
···
··
··
··
··
··
··
POWER SUPPLY REQUIREMENTS
Voltage: +Vcc
-Vee
+V,
Current: +Vcc
-Vee
+V,
Power Dissipation (Typical Supplies)
Power Supply Sensitivity, Unipolar: ±15VDC
+5VDC
Bipolar: ±1SVDC
+SVDC
Gain: ±15VDC
HVDC
,
ENVIRONMENTAL SPECIFICATIONS
a
Temperature Range: Specification
Storage
+70
+1S0
-60
*Specification same as DAC729JH.
··
UNITS
V
V
V
mA
mA
mA
W
%of FSR/%Vs
%of FSR/%Vs
%of FSR/%Vs
% 'of FSR/%Vs
%of FSR/%Vs
%of FSR/%Vs
·C
·C
NOTES: (1) TTL and CMOS compatible. (2) Specified for You, mode using the internal op amp. (3) ±0.00076% of full-scale range is 1I2LSB of 16-bit
resolution. (4) FSR means full-scale range, 20V for ±10V range, etc. (S) Adjustable to zero error with an external potentiometer. (6) COB is
complementary offset binary (bipolar); CSB is complementary straight binary (unipolar). (7) Using the MSB adjustment circuii, the user may improve the
DAC linearity to 1I2LSB of this specification. (8) With gain and offset errors adjusted to zero at 2S·C. (9) Maximum represents 3 sigma limit, not 100%'
production tested. (10) At the major carry; 20000 to lFFFF Hex and from lFFFF to 20000 Hex. (11) Maximum with no degradation in specifications.
External loads must be constant.
ABSOLUTE MAXIMUM RATINGS
MECHANICAL
r--
+Voo to Common ..................................... , OV to +7V
+Vcc to Common ...................................... OV to +18V
-Vee to Common ...........•.......................... OV to -18V
Digital Data Inputs (pins 1-18) to Common ........... +O.SV to +18V
Reference out (pin 32) to Common ..•.. Indefinite Short to Common
External Voltage Applied to DIA Output (pin 29) ....... -SV to +SV
Vou, (pin 23) .......................... Indefinite Short to Common
Power Dissipation. . • . • • . • . • • • . . • . . . • . . • . . . . . . . . • . . • . . • •. 3000mW
Storage Temperature ............................ -60·C to +1S0·C
2~1
A
1[: ::::::::::::::::: JlJ
~
1
NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
~
Seating
Plane
jL D j
NOTE: Leads in true position
within 0.01" (.025mm) R at
~~_a,-seating ~~ane.
Pin numbers are shown for
reference only. Numbers may
not be marked on package.
DIM
A
B
C
D
F
G
H
J
K
L
N
K
LG
INCHES
MIN
MAX
1.980
2.040
.610
.630
.150
.200
,016
.020
.050TYP
.100 BASIC
.030
.070
.012
.009
.155
.195
.600 BASIC
.040
.060
PIN CONNECTIONS
DAC729
Bitl
Bit2
Bit 3
Bit4
BitS
Bit6
Bit7
Bit8
Bit9
Bitl0
Bitll
Bit12
Bit 13
Bit14
BitlS
Bit16
Bit17
Bit18
+V,(SV)
Power Ground
MILLIMETERS
MIN
MAX
50.29
51.82
15.49
16.00
3.81
5.08
0.41
0.51
1.27 TYP
2.54 BASIC
0.76
1.78
0.23
0.30
3.94
4.95
15.24 BASIC
1.02
1.52
143
1
2
3
4
S
6
7
8
9
10
11
12
13
14
1S
16
17
18
19
20
40
39
38
37
36
3S
34
33
32
31
30
29
28
27
26
2S
24
23
22
21
VPOT
Bit 1 Adjust
Bit 2 Adjust
Bit 3 Adjust
Bit 4 Adjust
Reference Adjust
Gain Adjust
Reference Common
Reference Out
Reference In
Analog Common
lOUT
SkO Feedback
SkO Feedback
10kO Feedback
10kO Feedback
Summing Junction
VOUT
+VCC (1SV)
-Vc~ (15V)
THEORY OF OPERATION
The DAC729 is an IS-bit digital-to-analog converter
system, including' a precision reference, 'low noise, fast
settling operational amplifier, and the IS-bit current
source/ DAC chip contained in a hermetic 40-pin ceramic
dual-in-line package.
THE INTERNAL REFERENCE
The reference consists of a very low temperature coefficient closed-loop reference zener circuit that has been
slope-compensated by laser-trimming current-setting
resistors to a zener current to achieve less than 1ppm/ °C
temperature drift of VREF•
By strapping pin 32 (Reference Out) to pin 31 (Reference
In), the DAC will be properly biased from the internal
reference. The internal reference may be fine adjusted
using pin 35 as shown in Figure 7. The reference has an
output buffer that will supply 4mA for use external to
the DAC729. This load must remain constant because
changing load on the reference may change the reference
current to the DAC.
In systems where several components need to track the
same system reference, the DAC729 may be used with an
external IOV reference, however, the internal reference
has lower noise (61' Vp-p) and better stability than other
references available.
THE OPERATIONAL AMPLIFIER
To support a DAC 'of this accuracy, the operational
, amplifier must have a maximum gain~induced error of
less than 1/3LSB, independent of output swing (the op
amp must be linear!). To support 15 bits (1/2-bit linearity) the op amp must have a gain of 130,000V/V. For
18 bits, the minimum gain is well over 500,000V/V. Since
thermal feedback is the major liinitation of gain for
mono op amps, the amplifier was designed as a high
gain, fast settling mono op amp, followed by a monolithic,
. unity gain current buffer to isolate the thermal effects of
external loads from the input stages of the gain transistors. The op amp and buffer are separated from the
DAC chip, minimizing thermally-induced linearity errors
in the DAC circuit. The op amp, like the reference, is not
dedicated to the DAC729. The user may want to add a
network, or select adifferent amplifier. The DAc729
internal op amp is intended to be the best choice for
settling, speed, and noise.
THEDACCHIP
The heart of the DAC729 is a monolithic current source
and switch integrated circuit. The absolute linearity,
differential linearity, and the temperature performance
of the DAC729 are the result of the design, which utilizes
the excellent element matching of the current sources and
switch transistors to each other, and the tracking of the
current setting resistors to the feedback resistors. Older,
'more discrete designs cannot achieve the performance of
this monolithic DAC design.
The two most significant bits are binarily weighted
inner-digitized current sources. The currents for bits 3
through 18 are scaled with both current sources weighting
and an R-2R ladder. The circuit design is optimized for
low noise and low superposition error, with the current
sources arranged to minimize both code-dependent
thermal errors and IR drop errors., As a result, the
superposition errors are typically less than 20/LV.
The DAC chip is biased from a servo amplifier feeding
into the base liIie of the current sources. This servo
amplifier. sets the collector current to be mirrored and
scaled in the DAC chip current sources. The reference
current for the servo is established by the reference
voltage applied to pin 31 feeding an internal resistor
(lOkO) to the virtual ground of the servo amplifier.
DISCUSSION OF
SPECIFICATIONS
DIGITAL INPUT CODES
The DAC729 accepts complementary digital input codes
in either binary format (CSB, Unipolar or COB, Bipolar;
see Table I).
TABLE I., Digital Input Coding.
DAC Analog Output
Dlgllallnput
COB
I 20Y FSR I
CSB
I 10Y FSR
00 0000 0000 0000 0000 + Full Scale 1 9,999924V I + Full Scale 1 9,999962V
-10V
- Full Scale
OV
111111111111111111 - Full Scale
ACCURACY
Linearity
This specification describes one of the most important
measures of performance of a D/ A converter. Linearity
error is the deviation of the analog output from a straight
line drawn through the end points (all bits ON point and
all bits OFF point) .
DIfferential Linearity Error
Differential Linearity Error (DLE) of a D/ A converter is
the deviation from an ideal ILSB change in the output
from, one adjacent output state to the next. A differential
linearity error specification of ±1/2LSB means that the
output step sizes can be between 1/2LSB and 3/2LSB
when the input changes from one adjacent input state to
the next. A negative DLE specification of no more than
-ILSB (-0.0015% for 16-bit resolution) insures monotonicity
Monotonicity
Monotonicity assures that the analog output will increase
or remain the same for increasing input digital codes.
The DAC729 is specified to be monotonic to 16 bits over
the entire specification temperature range.
DRIFT
GaIn Drift
Gain drift is a measure of the change in the full-scale
144
range output over temperature expressed in parts per
million per degree centigrade (ppm/°C). Gain drift is
measured by: (I) testing the end point differences for
each D/ Aat tMIN, +25°C and tMAx; (2) calculating the
gain error with respect to the +25°C value; and (3)
dividing by the temperature change.
Offset Drift
Offset drift is a measure of the change in the output with
3FFFFH applied to the digital inputs over the specified
temperature range. The maximum change in offset at tMIN
or tMAX is referenced to the offset error at +25°C and is
divided by the temperature change. This drift is expressed
in parts per million of full-scale range per degree centigrade (ppm of FSR/°C).
0.16
0.14
0.12
;
0.10
~ 0.08
en
u..
;;';.
a: 0.06
en
a. 0.04
~
0.02
~
0.00
10
100
1k
Frequency (Hz)
10k
100k
FIGURE I. Power Supply Rejection vs Frequency
Using Internal Reference and Op Amp.
SETTLING TIME
Settling time ofthe D/ A is the total time required for the
analog output to settle within an error band around its
final value after a change in digital input.
Voltage Output
Settling times are specified to ±O.00075% of FSR
(±1/2LSB fcr.l6 bits) for t'.VO irrput conditions: a fullscale range change of 20V (COB) or IOV (CSB) and a
ILSB change at the "major carry," the point at which the
worst-case settling time occurs. (This is the worst-case
point since all of the input bits change when going from
one code to the next.)
Figure 2. These capacitors (l/-iF to IO/-IF tantalum
recommended) should be located close to the DAC729.
Electrolytic capacitors, if used, should be paralleled with
O.OI/-iF ceramic capacitors for best high frequency
performance.
40
39
3
38
5
36
6
35
37
Current Output
Settling times are specified to ±O.00075% of FSR for a
full-scale range change with an output load resistance of
100. It is specified this way because the output RC time
constant becomes the dominant factor in determining
settling time for large resistive loads.
8
9
18-
34
Bit
DAC
10
COMPLIANCE VOLTAGE
Compliance voltage applies only to current output models. It is the maximum voltage swing allowed on the
output current pin while still being able to maintain
specified linearity.
POWER SUPPLY SENSITIVITY
Power supply sensitivity is a measure of the effect of a
change in a power supply voltage on the D/ A converter
output. It is defined as a percent of FSR change in the
output per percent of change in either the positive supply
(+Vee), negative supply (-Vee) or logic supply (VL) about
the nominal power supply voltages (see Figure I). It is
specified for DC odow frequency changes. The typical
performance curve in Figure I shows the effect of high
frequency changes in power supply voltages using internal
reference, DAC, and op amp.
OPERATING INSTRUCTIONS
POWER SUPPLY CONNECTIONS
For optimum performance and noise rejection, power
supply decoupling capacitors should be added as shown in
FIGURE 2. Ground Connections and Supply Bypass.
EXTERNAL OFFSET AND GAIN ADJUSTMENT
Offset and gain may be trimmed by installing external
offset and gain potentiometers. Connect these potentiometers as shown in Figure 3 and adjust as described
below. TCR of the potentiometers should be 100ppm/oC
or less. The 3.9MO and 510kO resistors (20% carbon or
better) should be located close to the DAC729 to prevent
noise pickup. If it is not convenient to use these high-value
resistors, an equivalent "T" network, as shown in Figure
4, may be substituted in place of the 3.9MO. A O.OOI/-IF to
O.OI/-iF ceramic capacitor should be connected from Gain
Adjust (pin 34) to common to shunt noise pickup. Refer
145
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
40
39
38
37
36
35
, 34
270kll
32
31
28
27
26
25
24
23
[~:n~~!es
~+Vcc=15V_
~
-Vcc=15V
FIGURE 3. TYPical Gam and Offset Adjust Hook-Up.
0--3--~9"''M''''n--O
== -o--1"J80"'k~Il---'r--:l~80('
23
22
~+15V
2111):':::- lpF
lpF Tantalum:::'
I
Tantalum
_.
FIGURE 9. Typical Hook-Up Diagram with "Holy
Point" Ground and K.elvin Sense Load,
Using Internal Op Amp and Reference.
FIGURE 7. VREF Adjust.
lLSB
l
t
+Full Scale
I
II:
" "
0;
(/J
:;
Input = 3FFFFH
/.
.,
,.
0/
~
(/'i
/ 1(/
r
////)
////
IL
/,j4 r
I/~
'l'
,,-/1'
~Bon.AII
I
/
~~
lr /
r
"g>
-1~V>/''--+-__~ 100kCl
,-O.OlpF
-Vs 3.9MCl
Bit 3 Adjust 37H_~"""'--I----+--....~100kCl
..... O.OlpF
-Vs 1.8MCl
Erms
Bit 4 Adjust 36M_YlIr---I---+----+--~100kCl
where n is the number of samples in one cycle of any given
sine wave, EL(i) is the linearity error of the DAC729 at
each sampling point, and EQ(i) is the quantization error
at each sampling point. The THD can then be expressed
as
-Vs 21}-------~~--~----~--~~
FIGURE 12. Differential Linearity Adjustment Circuit
for the 4MSBs.
rms
1-
3
4
8
9
10
11
12
13
14
15
16
17
18
19
20
38
18-
(2)
rms
where E rms is the rms signal-voltage level.
This cAprc:;:;ion indic~te~ th::.t, in genera!, there is a
correlation between the THD and the square root ofthe
sum of the squares of the linearity errors at each digital
word of interest. However, this expression does not mean
that the worst-case linearity error of the D I A is directly
correlated to the THD.
The DAC729 has demonstrated THD of better than
0.0009% of full scale (at 1kHz). This is the level of
distortion that is desired to test other professional audio
products, making the DAC729 ideal for professional
audio test equipment.
The ability to adjust the linearity of the 4MSBs, the
18-bit resolution, fast settling and low noise give the
DAC729 unmatched performance.
13940
37
6
. I.!. .¥
[EL(i) + EQ(i)]2
Vnl=t
THD = -E- = - - - E - - - - X 100%
Erms
1
=.J J ~ [EL(i) + EQ(i)]2
i = 1
TO.OlpF
-Vs
36
35
34
Bit
DAC
AUTOMATIC TEST EQUIPMENT
The ability to adjust thl! absolute linearity and the ability
to run several DACs from the same reference make the
DAC729 ideal as the reference DAC for an entire data
conversion system. Since the feedback resistors are
absolute value (±O.l%), the addition of a 240n resistor
makes the output 1O.24V.This feature makes discrete
10mV steps easy to create with a resolution of 39p. V for
1O.24V FSR. Figure 14 shows the DAC729 connected for
OV to 1O.24V operation and using an external reference.
The ·two 240n resistors are in series with the parallel
IOkn internal resistors, resulting in 1O.24V out. This
hook-up minimizes the thermal coefficient of resistance
problems associated with this accuracy.
The low superposition error of the DAC729 makes the
system calibration routines become much less complicated. There is seldom a need to iterate through the
calibration routine. Repeatability of the DAC output
voltage is many times better than competitive products.
This feature cuts system overhead time, improves
accuracy, and cuts guard bands for the user. The entire
set of test head DACs could be upgraded from 16 bits to
18 bits by replacing the existing 16-bit DACs.
FIGURE 13. 0 to 10V FSR.
APPLICATIONS
The DAC729 is the DAC of choice for applications
requiring very high resolution, accuracy, and wide
dynamic range.
DIGITAL AUDIO
The excellent linearity and differential linearity are ideal
for PCM professional audio and waveform generation
applications.
The DAC729 offers superb dynamic range. Dynamic
range is a measure of the ratio of the smallest signals the
converter can produce to the full-scale range, usually
expressed in decibels (dB). The theoretical dynamic range
of a converter is approximately 6dB per bit. For the
DAC729 the theoretical range is 108dB! The actual
dynamic range is limited by noise (signal-to-noise) and
linearity errors. The DAC729's 6p.V typical noise floor,
149
T,HE HEART OF AN 18-BIT ADC
The DAC729 makes a good building block in ADC
applications. The key to ADC ,accuracy is differential
linearity of the DAC. The ability to adjust to 18-bit
linearity, coupled with the fast settling time of the
DAC729 makes the design cycle for an 18-bit successive
approximation ADC much faster, and the production
more consistent. Figure IS shows the DAC asthe heart
of a successive approximation ADC. The clock and
successive approximation register could be implemented
in 7400 series TTL, as a simple gate-array or standard
cell, or part of a local processor.
With the DAC out of the way, the comparator is the
toughest part of the ADC design. To resolve an 18-bit
LSB, and interface to a TTL logic device, the comparator
must have a gain of 500kV/V (5X actual) as well as low
hysteresis, low noise, and low thermally·induced offsets.
With this much gain, a slow comparator may be desired
to reduce the risk of instability.
The feedback resistors of the DAC are the input scaling
resistors of the ADC. An OPA404 and an OPA633 make
an excellent buffer for the input signal, giving a very high
input impedance to the signal (minimizing IR drop)
while maintaining the linearity.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
r--
34
18811
DAC
33
~
31
3n
'-
10kn 10kn 29
28
27
240n
26
t
.~
/"=F ~
25
')
,
24 240n
010 10.24V .
23
22
21
. FIGURE 14. OV to 10.24V Using Internal Op Amp and
Internal References.
DAC729
10kn
10kn
Ref. In
To Holy
Custom Design
Comparalor
ReI. Out
Point Ground
18811s
SAR
FIGURE IS. Block Diagram of an 18-Bit ±IOVIN ADC.
150
BURR-BROWN®
DAC811JU
DAC811KU
IElElI
Microprocessor-Compatible
12-BIT DIGITAL-TO-ANALOG CONVERTER
(Small-Outline Surface-Mount Package)
FEATURES
• SINGLE INTEGRATED CIRCUIT CHIP
• MICROCOMPUTER INTERFACE: DOUBLE-BUFFERED
LATCH
• VOLTAGE OUTPUT: ±10V, ±5V, +10V
• MONOTONICITY GUARANTEED OVER
TEMPERATURE
• ±3/4LSB MAXIMUM NONLINEARITY OVER
TEMPERATURE
• GUARANTEED SPECIFICATIONS AT ±12V AND
±15V SUPPLIES
• TTL/5V CMOS-COMPATIBLE LOGIC INJJ(fTS
DESCRIPTION
The DAC81lU is a complete single-chip integratedcircuit microcomputer-compatible l2-bit digital-toanalog converter packaged in a 28-lead plastic SOIC.
The chip' includes a precision voltage reference,
microcomputer interface logic, double-buffered latch,
and a l2-bit D / A converter with a voltage output
amplifier. Fast current switches with laser-trimmed
thin-film resistors provide a highly accurate and fast
D/A converter.
Microcomputer interfacing is facilitated by a dOublebuffered latch. The input latch is divided into three
4-bit nybbles to permit interfacing to 4-, 8-, 12- or
l6-bit buses and to handle right- or left-justified
data. The l2-bit data in the input latches is transferred to the D / A latch to hold the output value.
Input gating logic is designed so that loading the last
byte of data can be accomplished simultaneously
with the transfer of data (previously stored in adjacent latches) from adjacent input latches to the D / A
latch. This feature avoids spurious analog output
values and saves computer instructions.
The DAC81l is laser trimmed at the wafer level and
is specified to ±1/4LSB maximum linearity error (K
grade) at 2SoC and ±3/4LSB maximum over the
temperature range. All grades are guaranteed monotonic over the specification temperatwe range.
DAC8lIJU and KU are specified over the temperature range of O°C to +70°C.
4 MSBs
4 LSBs
Intarnational Alrporllndustrlal Park. P.O. Box 11400 • Tucson. Arizona B5734 • Tel.: (602/ 746·1111 • Twx: 910-952·1111 • Cable: BBRCORP • Telex: 86-8491
PDS-717
151
SPECIFICATIONS
. ORDERING INFORMATION
(
ELECTRICAL
r
DAC811 XU
TA .= +25°C. ±Vcc = 12V or 15V unless otherwise noted.
MOOEL
OAC811JU
PARAMETER
MIN
TYP
I I
OIGITAL INPUT
Resolution
Codes!11
DAC811KU
MAX
MIN
TYP
12
,
USB, BOB
Digital Inputs Over Temperature Range C2J
+2.0
0.0
V,"
V"
+15
+0.8
+10
±2o
hH. VI = +2.7V
hL. VI = +O.4V
Digital Interface Timing Over Temperature Range l31
twP, WR pulse width
tAw1,.N; and LDAC valid to end of WR
tow. data valid to end of WR
101"1, data valid hold time
,
MAX
UNITS
,
Bits
,
,
,
,
,
,
50
50
80
0
VOC
VDC
pA
pA
ns
ns
ns
ns
i
,
,
TRANSFER CHARACTERISTICS
ACCURACY
Li~earity
±1/4
±1/2
Error
Differential Linearity Error
Gain Errorl .)
Offset Errorl4 ,51
±1/8
±1/4
±112
±3/4
,
,
,
,
,
,
±0.1
±0.2
±0.05
±0.15
Guaranteed
±0.001 ±0.003
±0.002 ±0.006
±o.o005 ±0.0015
Monotonicity
Power Supply Sensitivity: +Vcc
-Vee
1Voo
DRIFT (O'C 10 +70'C)
Gain
Unipolar Offset
Bipolar Zero
Linearity Error Over Temperature Range
Monotonicity Over Temperature Range
±10
±5
±5
±30
±10
±10
±1/2
±3/4
·
·,
,
±1/4
Guaranteed
±1/4
±1/2
,
,
··
·
,
,
,
,
LSB
LSB
%
% of FSR(61
Basic Model ---~--I T
Grade
J
Package Type - - - - - - - - '
ABSOLUTE MAXIMUM
RATINGS
±Vee to ACOM ....... :..... 0 to ±18V
VDD to OCOM ..... c. .. .. .... 0 to +7V
Input Voltage Range ••.........•. ±Vcc
Digital Inputs ........... ":'0.4V to Vee
Lead Temp, Wave Soldering
(3 seconds max) .. .. .. .. .... +260'C
Output Short Circuit
to Common. . . . • . . . . . .. Continuous
Power Dissipation ............•... 1W
NOTE: Stresses above those listed may
cause permanent damage to the device.
Exposures to absolute maximum conditions for extended periods may effect
device reliability.
% 01 FSR/%Vcc
% 01 FSR/%Vee
% 01 FSR/%VDD
ppm/'C
ppm of FSR/'C
ppm of FSRI'C
LSB
CONVERSION SPEED
SETTLING TIME'" (to within ±0.01% of FSR
of final value. 2kQ load)
For Full-Scale Range Change: 20V Range
10V Range
For 1LSB Change at Major Carry'8)
Slew Rate l71
MECHANICAL
8
3
3
1
12
4
4
,
OUTPUT
ANALOG OUTPUT
Voltage Range (±Vcc ~ 15V)'91. Unipolar
Bipolar
Output Current
Output Impedance (at DC)
Short Circuit to Common Duration
REFERENCE VOLTAGE
Voltage
Source Current Available for Exte:rnal Loads
Temperature Coefficient
Short Circuit to Common Duration
Oto+10
±5,±10
,
±5
0.2
Indefinite
+6.2
+2.0
,
+6.3
+6.4
±10
Indefinite
±30
+15
-15
+5
+16
-23
+8
+16.5
-16.5
+5.5
+25
-35
+15
±0.5
800
POWER SUPPLY REQUIREMENTS
Voltage: +Vee
I
-Vee
VDD
Current (no load): +Vcc
-Vee
VDD
Potential at DCOM with Respect to ACOM'101
Power Dissipation
+11.4
-11.4
+4.5
625
TEMPERATURE RANGE
Specification
Storage
'Same as OAC811JU.
0
-60
·,, ·,
·
··,
+70
+100
·· · ·
·, ·
··, ·, ··
·· ··
·, ·,
· ··
··
··
ps
ps
ps
Vips
A
"-'lnnnnnnnlinnnn
I
t
l
B
V
V
mA
6u "-
~i~ ; I~e~t~fi~r u
u u u
~
Beveled
n
V
mA
Jp~OJlfl~'~
_11-0
~
G
H
ppm/'C
VDC
VDC
VOC
mA
mA
mA
V
mW
'C
'C
NOTES: (1) USB = Unipolar Straight Binary. BOB = Bipolar Offset Binary. (2) TTL-, LSTTL-, 74HC CMOS-compatible.
(3) Refer to Figures 6 and 7. (4) Adjustable to zero with external trim potentiometer. (5) Error at input code 00018 for both
unipolar and bipolar ranges. (6) FSR means FU,II Scale Range and is 20V for the ±10V range. (7) Maximum represents the 3u
limit. Not 100% tested for this parameter. (8) At the major carry, 7FF" to 800" and 600 .. to 7FF,.. (9) Minimum supply
voltage required for ±10V output swing is ±13.5V. Output swing for ±11.4V supplies is at least -8V to +8V with no external
load. (10) The maximum voltage at which ACOM and DCOM may be separated without affecting accuracy specifications.
152
I"
19L
J~J
'I_L_1f
NOTE: Leads in true position
within 0.010" (.25mm) Rat MMC
at seating plane.
DIM
A
B
C
0
G
H
J
L
M
N
INCHES
MIN
MAX
.700
.716
.288
.302
.109
.093
.015
.019
.050 BASIC
.022
.038
.008
.012
.281
.309
5° TYP
,011
.007
MILLIMETERS
MIN
MAX
18.19
17.78
7.26
7.67
2.38
2.77
0.38
0.48
1.27 BASIC
0.56
0.97
0.20
0.30
7.14
7.85
5° TYP
0.18
0.28
PIN NOMENCLATURE
PIN
6
NAME
FUNCTION
PIN
NAME
Voo
Logic Supply, +5V
15
DCOM
DIGITAL COMMON, Voo supply return
WR
WRITE, command signal to load latches, Logic
low loads latches.
16
DATA, Bit 1, LSB
17
Do
D,
LDAC
LOAD DIA CONVERTER, enables WR 10 load
the D/A latch. logic low enables.
18
D,
DATA, Bil3
19
D,
'DATA, Bil4
FUNCTION
DATA, Bil2
N.
NYBBLE A, enables WR to load input latch A
(the most significant nybble). Logic low enables.
20
+Vcc
Analog Supply Input, +15V or +12V
No
NYBBLE B, enables WR to load input lalch B.
Logic low enables.
21
-Vee
Analog Supply Input, -15V or -12V
22
GAIN ADJ
To externally adjust gain
No
NYBBLE C, enables WR to load input latch C
(the least significant nybble). Logic low enables.
23
ACOM
ANALOG COMMON, ±Vcc supply return
24
VCUT
D/A converter voltage output
D"
Doo
D,
DATA, Bit 12. MSB, positive true.
25
10V RANGE
Connect to pin 24 for 10V Range
DATA, Bit 11
26
SJ
SUMMING JUNCTION 01 output amplifier
DATA, Bit 10
27
BPO
D.
DATA, Bit 9
BIPOLAR OFFSET. Connect to pin 26 for
Bipolar Operation
11
D,
DATA, Bit 8
28
REF OUT
6.3V reference output
12
D,
DATA, Bit 7
13
D,
DATA, Bit 6
14
D,
DATA, Bit 5
10
TABLE I. Digital Input Codes.
CONNECTION DIAGRAM
,
MSB
l
LSB
l
111111111111
100000000000
011111111111
000000000000
+15V
i
i
DIGITAL INPUT
Connect For Bipolar Operation
ANALOG OUTPUT
USB
Unipolar
Straight
Binary
+Full Scale
+1/2 Full Scale
.1/2 Full Scale -1 LSB
Zero
BOB
Bipolar
Offset
Binary
+Full Scale
Zero
-1LSB
-Full Scale
BTC'
Binary
Two's
Complement
-1LSB
-Full Scale
+Full Scale
Zero
-Invert the MSB of the BOB code with external inverter to obatin BTC
code.
+
LINEARITY ERROR
Linearity error as used iiI D / A converter specifications
by Burr-Brown is the deviation of the analog output
from a straight line drawn between. the end points
(inputs all "I's" and all "0 's"). The DAC811 linearity
error is specified at ± I /4LSB (max) at +25°C for the K
grade and ±1/2LSB (max) for the J grade.
DISCUSSION OF
SPECIFICATIONS
INPUT CODES
The DAC811 accepts positive true binary input codes. It
may be connected by the user for anyone of the
following codes: USB (unipolar straight binary), BOB
(bipolar offset binary) or, using an external inverter on
the MSB line, BtC (binary two's complement). See
Table I.
DIFERENTIAL LINEARITY ERROR
DifferentialliI)earity error (DLE) is the deviation from a
I LSB output change from one adjacent state to the next.
A DLE specification of 1/2LSB means that the output
step size can range from 1/2LSB to 3/2LSB when the
input ch'anges from one state to the next. Monotonicity
requires that DLE be less than I LSB over the temperature range of interest.
MONOTONICITY
A D / A converter is monotonic if the output either
increases ,or remains the same for increasing digital
inputs. The DAC811 is monotonic over the entire specification temperature range,
153
DRIFT
Gain drift is a measure of the change of the full-scale
range output over the specificatidn temperature range.
Drift is expressed in parts per million per degree centigrade (ppm/°C). Gain drift is established by testing the
full-scale range value (e.g., +FS minus -FS) at high
temperature, +25°C, and low temperature; calculating
the error with respect to the +25°C value and dividing by
the temperature change.
Unipolar offset drift is a measure of the change in output
with all O"s on the input over the specification temperature range. Offset is measured at high temperature,
+25°C, and low temperature. The maximum change in
offset referred to the +25°C value divided by the temperature change is the offset drift. It is expressed in parts
per million of full-scale range per degree centigrade
(ppm of FSR/°C).
Bipolar zero drift is measured at a digital input of 80016,
the code that gives zero volts output for bipolar operation.
1.0
~~
"
csg»
-"
8g
0.1
li"
~
8.'"
II: :;;
:x~
/
'"
u.. 3:
0
-~ ov.v
a. n
~~
" U"
-' 'x~c
IJ'"
0.'<:
O.UU
~
~
0.0001
100
10.
lK
lOOK
10k
1M
Frequency (Hz)
SETTLING TIME
Settling time is the total time (including slew time) for
the output to settle within an error band around its final
value after a change in input. Three settling times are
specified to ±O.Ol% of full-scale range (FSR): two for
maximum full-scale range changes of 20V and lOY, and
onefor a ILSB change. The ILSB change is.measured at
the major carry (7FF16 to 80016 and 80016 to 7FFI6), the
input transition at which worst-case settling time occurs.
FIGURE 1. Power SupPly Rejection versus Power
Supply Ripple Frequency.
'5
c.
'5
.L
"'T
,
.
.",/
~/'"
~ .. '
• ,'"•
-' /'
+Full-Scale
~
~(\)
~ ~
o
g'
'il
Range Of
< Ollset Adjust
Ollset Adjust
Translates
The Line
REFERENCE SUPPLY
DAC811 contains an on-chip 6.3Vreference. This voltage
(pin 28) has a tolerance of ±O.I V. The reference output
may be used to drive external loads, sourcing at least
2.0mA. This current should be constant for best performance of the DJ A converter.
iB~
1LSB
~
.r
AIlBits
Ii
Range Of
Gain Adjust
~
_;;)1'
~X Gain Adjust
Logic 0
11 1•.
,1'
Rotates
The Line
?
All Bits
Logie 1
Digital Input
FIGURE 2. Re\ationship of Offset and Gain
Adjustments for a Unipolar D/A
Converter.
::r
POWER SUPPLY SENSITIVITY
-S'
o
.2
<~
All Bits
Logic 0 '"
OllsetAdjUstl
Ollset Adjust
Translates
/
The Line
T
Figures 2 and.3 illustrate the relationship of offset and
gain adjustments to unipolar and bipolar D / A converter
t
1
Bipolar V .....t.....~
Ollset,J:'to
Range Of
OFFSET AND GAIN ADJUSTMENTS
' ~'.;
~.
T
lLSB ~
Full·Scale
Range
'5
Power supply sensitivity is a measure of the effect of a
power supply change on the D / A coonverter output. It
is defined as a percent of FSR output change per percent
of change in either the positive, negative, or logic supply
voltages about the nominal voltages. Figure I shows
typical power supply rejection versus power supply
ripple frequency.
+Full
Scale./·
•
'~L
I
.L
Range Of
T' Gain Adjust
~ 1J ,--- Gain Adjust
~./
~:-'"
Rotates
The Line
I'MSB On
All Others
Of
-Full-Scale
~
All Bits
Loglcl
Ollset
Digital Input
FIGURE 3. Relationship of Offset and Gain
Adjustments for a Bipolar DJA Converter.
outp~t.
154
MSB
D11 ...•.... D8
LSB
D3 ..•••••• DO
D7 ........ D4
FIGURE 4. DAC8!! Block Di!!gr!!!!!.
OPERATION
DAC8ll isa complete single IC chip l2-bit D(A converter. The chip contains a l2-bit D(A converter, voltage
reference, output amplifier, and microcomputer-compatible input logic as shown in Figure 4.
±12V OPERATION
The DAC811 is fully specified for operation on ±12V
power supplies. However, in order for the output to
swing to ±10, the power supplies must be ±13.5V or
greater. When operating with ± l2V supplies, the output
swing is restricted to approximately ±8V.
transmit data to the D(A switches when both ~
and WR are at logic "0." When either LDAC or WR are
.at logic "l,"the data is latched in the D/ A latch and held
until LDAC and WR go to logic "0."
All latches are level-triggered. Data present when the
control signals are logic "0" will enter the latch. When
anyone of the control signals returns to logic" I," the
data is latched. A truth table for all latches is given in
Table II and Relatative Timing Diagrams are shown in
Figures 5 and 6.
TABLE II. DAC8ll Interface Logic Truth Table.
Wi!"
~
No
Ne LDAC
1
X
X
X
X
a
a
a
a
a
a
1
1
1
No Operation
Enables Input Latch 4MSBs
1
1
a
1
1
a
1
1
Enables Input Latch 4 Middle Bits
Enables Input Latch 4LSBs
a
a
Loads D/A Latch From Input Latches
All Latches Transoarent
LOGIC INPUT COMPATIBILITY
The DAC8ll digital inputs are TTL, LSTTL, and
54f74HC CMOS-compatible over the operating range
of Voo. The input switching threshold remains at the
TIL threshold over the supply range.
··X··
~
1
1
1
a
a
a
OPERATION
Don·t Care
INTERFACE LuGIC
Input latches A, B, and C hold data temporarily while a
complete l2-bit word is assembled before loading into
the D(A register. This double-buffered organization
prevents the generation of spurious analog output values.
Each register is independently addressable.
These input lat.ches are controlled by NA, No, iii;; and
WR.NA, NB, and Nc are internally NORed with WR so
that the input latches transmit data when both NA (or
NB, Nc) and WR are at logic "0." When either NA (or No,
i'ifC) and WI'{ go to logic "1," the input data is latched
into the input registers and held until both NA (or NB,
Nc) and WR go to logic "0."
The D( A latch is controlled by LDAC and WR. LDAC
and WR are internally NORed so that the latches
(Load First Rank F*ro:"Data
_ ._
DB l1 -DBo
B~s; ~ =: 1)
_I
80ns minimum
_______
~I*~
__-
WR
FIGURE 5. Write Cycle #1 (Data Latched from Data
Bus).
155
(Load Second RankFom First
LDAC
WR
t
R~:~
50ns minimum
r
TABLE III. Digital Input/Analog Output, ±VcC' =:!-i5V.
1)
ANALOG OUTPUT VOLTAGE
I /r----
±5V
±10V
12-Bit Resolution
MSB
LSB
t~
~
~ :_~1 _____ _
I
I
111111111111
100000000000
011111111111
000000000000
lLSB
==c;Lt5ETT':'
__ _____
~~--r-----
_._---------.
Oto 10V
DIGITAL INPUT
+9.9976V
+5.0000V
+4.9976V
O.OOOOV
2.44mV
+4.9976V
O.OOOOV
-0.0024V
-5.0000V
2.44mV
+9.9951V
O.OOOOV
-0.0049V
-10.0000V
4.88mV
OUTPUT RANGE CONNECTIONS
Internal scaling resistors provided in the DACSI I may
be connected to produce bipolar output volt~ge ranges
of ± lOY and ±5V or unipolar output voltage range of 0
to +lOY. The 20V range (±IOV bipolar range) is internally
connected. Refer to Figure S. Connections for the output
ranges are listed in Table IV.
±1/2LSB
FIGURE 6. Write Cycle #2 (Data Transferred to
DAC).
EXTERNAL OFFSET AND GAIN ADJUSTMENT
Offset and gain may be trimmed by installing external
offset and gain potentiometers. Connect these potentiometers as shown in the Connection Diagram. TCR of
the potentiometers should be 100ppmm/oC or less. The
1.0M!l and 3.9M!lresistors (20% carbon or better)
should be located close to the DACSII to prevent noise
pickup. If it is not convenient to use these high value
resistors, an equivalent "T" network, as shown in Figure
7, may be substituted in each case. The Gain Adjust (pin
22) is a high impedance point and a 0.00221lF ceramic
capacitor should be connnected from this pin to analog
common to reduce noise pickup in all applications,
including those not employing external gain adjustment.
From
5.36kQ
C\27 Bipolar
Voltage ---"~,,.----0.:;:.1 Offset
Reference
RsPO
Summing
Junction
4.26kQ
10V Range
From
D/A
Convert~r
VOUT
Resistor Tolerances ±.25%
FIGURE S. Output Amplifier Voltage Range Scaling
Circuit.
~=~~
1.0MQ
~ 1:~~~ _
~ TABLE IV. Output Range Connections.
Output
Range
~=~
~
Oto +10V
±5V
±10V
Digital
Input Codes
Connect
Connect
Pin 25 To
Pin 27 To
USB
24
23
BOB or BTC
24
26
BOB or BTC
NC
26
FIGURE 7. Equivalent Resistances.
Offset Adjustment
For unipolar (USB) configurations, apply the digital
input code that should produce zero voltage output and
adjust the offset potentiometer' for zero output. For
bipolar (BOB, BTC) configurations, apply the digital
input code that should produce the maximum negative
output voltage and adjust the offset potentiometer for
minus full-scale voltage. Example: If the full-scale range
is connected for 20V, the maximum negative output
voltage is -lOY. See Table III for corresponding codes.
Gain Adjustment
For either unipolar or bipolar configurations, apply the
digital input that should give the maximum positive
voltage output. Adjust the gain potentiometer for this
positive full-scale voltage. See Table III for positive fullscale voltages.
INSTALLATION
POWER SUPPLY CONECTIONS
Decoupling: For optimum performance and noi~e rejection, power supply decoupling capacitors should be
added as shown in the Connection Diagram. .
These capacitors (IIlF tantalum recommended) should
be located close to the DAC811.
The DACSII features separate digital and analog power
supply returns to permit optimum connections for low
noise and high speed performance. The analog common
(pin 23) and digital common (pin 15) should be connected
together at one point. Separate returns minimize current
flow in low level signal paths if properly connected.
156
Logic return currents are not added into the analog
signal return path. A ±0.5V difference between ACOM
and DCOM is permitted for specified operation. High
frequency noise on DCOM with respect to ACOM may
cause noise to be coupled through to the analog output.
therefore. some caution is requried in applying these
common connections.
The analog common is the high quality return for the
D / A converter and should be connected directly to the
analog reference point of the system. The load driven by
the output amplifier should be returned to the analog
common.
OBo
DB.
=>"Cl
DB,
E
8
§
~
OAC811
DB,
APPLICATIONS
WR
AN
MICROCOMPUTER BUS .INTERFACING
A,
The DAC811 interface logic allows easy interface to
microcomputer bus structures. The control signal WR is
derived from external device select logic and the I/O
Write or Memory· Write (depending upon the· system
design) signals from the microcomputer.
The latch enable lines N, A. No. Nc, and LDAC determine
which of the latches are enabled. It is permissible to
enable two or more latches simultaneously as shown in
some of the following examples.
The double-buffered latch permits data to be loaded into
the input latches of several DAC811s and later strobed
into the D / A latch of all D / As, simultaneously updating
all analog outputs. All the interface schemes shown
below use a base address decoder. If blocks of memory
are unused. the base address decoder can be simplified or
eliminated altogether. For instance if half the memory
space is unused. address line Als of the microcomputer
can be used as the chip select control.
A,
N.
AD
FIGURE 9. Addressing and Control for 4-Bit
Microcomputer Interface.
1x1x1x1x10,,10,,10.10.1
a. Right-Justified
10,,10,,10.10.10,10.10.10.1
.10,10,10.1001 xIxIxIx I
b. Left-Justified
FIGURE 10. 12-Bit Data Formats for 8-Bit Systems.
4-BIT INTERFACE
An interface to a 4-bit microcomputer is shown in Figure
9. Each DAC811 occupies four address locations. A
74LS 139 provides the two to four decoder and selects
these with the base address. Memory Write (WR) of the
microcomputer is connected directly to the WR pin of
the DAC811. An 8205 decoder is an alternative device to
use instead of the 74LS 139.
$
8-BIT INTERFACE
The control logic of DAC81 I permits interfacing to
right- or left-justified data for~ats illustrated in Figure
10. When a 12-bit D/A converter is loaded from an 8-bit
bus. two bytes of data are required. Figures I I and 12
show an addressing scheme for right-justified and leftjustified data respectively. The base address is decoded
from the high-order address bits. Ao and AI address the
appropriate latches. Note that adjacent addresses are
used. For the right-justified format XI016 loads. the
8LSBs and XOl 16 ioads the 4MSBs and simultaneously
transfers input latch data to the D / A latch. Addresses
XOO l6 and XI 116 are not used.
:3
Co
E
o
e
"
~
FIGURE II. Right-Justified Data Bus Interface.
157
12- AND 16-BIT MICROCOMPUTER INTERFACE
For this application the input latch enable lines, 'lirA, No,
and N; are tied low, causing the latches to be transparent.
The D / A latch, and therefore DAC811, is selected by the
address decoder and strobed by WR:
Left-justified data is handled in a similar manner, shown
in Figure 12. The DAC811 still occupies two adjacent
locations in the microcomputer's memory map.
WR
WR
mc
DAC811
(1)
A1P~
Do
sc.
:J
DAC811
E
0
"e
'i"E
N.
0,
0,
0,
0"
0,
WAC
DAC811
(2)
Nc
A,
No
N.
l!l
:J
C.
E
0
"e
y. '11
74LS138
.2
::;;
A,
C
A,
B
Ao
A
Y. 10
, Y.
9
,y,
FIGURE 12. Left-Justified Data Bus Interface
INTERFACING MULTIPLE DAC811s
IN 8-BIT SYSTEMS
Many applications require that the outputs of several'
D / A converters be updated simultaneously such as
automatic test systems. The interface shown in Figure 13
uses a 74LSI38 decoder to decode a set of eight adjacent
addresses to load the input latches of four DAC811s.
The example shows a right-justified data format.
ADDRESS BUS
A ninth address using A3 causes all DAC811s to be
updated simultaneously. If a particular DAC811 is always
loaded last, for instance, D/ A #4, A3 is not needed, thus
saving eight address spaces for other uses. Incorporate
A3 into the Base Address Decoder, remove the inverter,
connect the common LDAC line to N, of D/A #4, and
connect G, of the 74LSI38 to +5.
OPERATION
A,
Ao
A,
Ao
0
0
0
0
LOAD 8LSB-D/A #1
0
0
0
1
LOAD 4MSB-D/A,#1
0
0
1
0
LOAD 8LSB-D/A #2
0
0
1
1
LOAD 4MSB-D/A #2
0
1
0
0
LOAD 8LSB-D/A #3
0
1
0
1
LOAD 4MSB-D/A #3
0
1
1
0
LOAD 8LSB-D/A #4
0
1
1
1
LOAD 4MSB-D/A #4
1
X
X
X
LOAD D/A LATCH-ALL D/A
FIGURE 13. Interfacing Multiple DAC811s to an 8Bit BlIS.
158
BURR-BROWN®
DAC7541A
1E3E31
Low Cost 12-Bit CMOS
Four-Quadrant Multiplying
DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
• FULL FOUR·QUADRANT MULTIPLICATION
• 12·B11 END·POINT LINEARITY
• DIFFERENTIAL LINEARITY ±1I2LSB MAX OVER
TEMPERATURE (K/B/T GRADES)
• MONQTONICITY GUARANTEED OVER TEMPERATURE
• TTL·/CMOS·COMPATIBLE
• SINGLE +5V TO +15V SUPPLY
• LATCH·UP RESISTANT
• 752117541 17541 A REPLACEMENT
• PACKAGES: HERMETIC DIP. PLASTIC DIP.
PLASTIC SOIC
• LOW COST
The Burr-Brown DAC7541A is a low cost 12-bit,
four-quadrant multiplying digital-to·analog converLei. Laser-trimmed thin-film. r~:;i:;tG!,~ en. ~ !ncnclithic
CMOS circuit provide true 12-bit integral and differentiallinearity over the full specified temperature
ranges.
The DAC7541A is a direct, improved pin-for-pin
replacement for 7521, 7541, and 7541A industry
standard parts. In addition to standard 18-pin plastic
and hermetic ceramic packages, The DAC7541A is
also available in a surface-mount plastic 18-pin SOIC.
FUNCTIONAL DIAGRAM
v...
10kCl
20kCl
10kCl
10kCl
20kCl
10kCl
20kCl
20kCl
20kCl
SPDTNMOS
Swilche~
.....- - - - o l o u..
~+-I-""-"""''''''-n-+--!-~-4-+
L......j1--....+--~"+-·H·-+-I----!I!-....~10~kCl::---oIOUT1
I
I
I
6
........,.,.........0
RFEEDBACK
6
Bit 1 (MSB)
Bit 12 (LSB)
Digital Inputs (DTLfITLJCMOS gompatible)
Logic: A switch is closed to 10uTI for Its digital Input in a "high" state.
Switches shown for digit.' Inputs "high".
Inlernatlonel Alrporllndustrlal Perk • P.O. Box 11400 • Tucson, Arizona B5734 • Tel.: (602)748-1111 • Twx: 911).952·1111 • Cable: BBRCORP • Telex: 68-8491
PDS-639
159
SPECIFICATIONS
ELECTRICAL
At +25°C.
+VDD::;;:
+12V or +15V. VREF
:::;;:
+10V. VP1N 1 = VP1N 2:::; OV unless otherwise specified.
MOOEL
DAC7S41A
PARAMETER
ACCURACY
Resolution
Relative Accuracy
Differential Non-linearity
Gain Error
Gain Temperature Coefficient
(fiGain/,C..Temperature)
Output Leakage Current: OUt, (Pin 1)
Out, (Pin 2)
REFERENCE INPUT
Voltage (Pin 17 to GND)
Input Resistance (Pin 17 to GND)
= TMINI TMAAn'
UNITS
GRADE
T.=+2SoC
All
J,A,S
K, B, T
. J,A, 5
K, B, T
J,A,S
K, B, T
12
±1
±1/2
±1
±1/2
±6
±1
12
±1
±1/2
±1
±1/2
±8
±3
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
All
J, K
A, B
5, T'
J, K
A,B
5, T
±S
±S
±S
±S
±S
±S
S
±10
±10
±200
±10
±10
±200
ppm/DC max
nA max
All
All
-10/+10
7-18
-10/+10
7-18
kO: minimax
TA
TEST CONDITIONS/COMMENTS
±1 LSB = ±0.024% of FSR.
±1/2LSB = ±0.012% of FSR.
All grades guaranteed monotonic to
12 bits, TMIN to TMAX.
Measured using internal RFS and includes
effect of leakage current and gain T.C.
Gain error can be trimmed to zero.
Typical value is 2ppm/oC.
All digital inputs = OV.
nA max
nA
nA
nA
nA
max
max
max
max
All digital inputs;::::: VPD.
V.min/max
I
Typical input resistance = l1kn.
Typical input resistance temperature
coefficient is -SOppmfOC.
DIGITAL INPUTS
V'H (Input High Voltage)
V" (Input Low Voltage)
ioN (Inp~t Current)
All
All
All
2.4
0.8
±1
2.4
0.8
±1
pAmax
Logic'inputs are MOS gates.
ioN typ (2S0C) = 1nA.
VIN=QV
Vmin
V max
CIN (Input Capacitance)421
All
8
8
pFmax
POWER SUPPLY REJECTION
t.Gain/t.Voo
All
±0.01
±0.02
% per % max
POWER SUPPLY
Voo Range
All
+Sto +16
+S to +16
V minto
100
All
2
100
2
SOO
mAmax
Voo = +11.4V to +16V
Accuracy is not guaranteed over this range.
'!max
IJAmax
All digital inputs V" or V,H.
All digital inputs OV or Voo.
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for design guidance only and are not production tested.
Voo = +1SV, VA.F = +10V except where stated, VP'N I = VPlN • = OV, output amp is OPA606 except where stated.
PROPAGATION DELAY
(from Digital Input change to
90% of Final Analog Output)
All
100
DIGITAL-TO-ANALOG GLITCH
IMPULSE
All
1000
MULTIPLYING FEEDTHROUGH
ERROR (V..FtoOut.)
All
1.0
All
0.6
-
All
1.0
-
JJsmax
To 0.01% of Full Scale Range.
Out, load 1000, CEXT = 13pF.
Digital Inputs: OV to Voo or Voo to OV.
All
All
All
'AII
100
60
70
100
100
60
70
100
pFmax
pFmax
pF max
pFmax
Digital Inputs
Digital Inputs
DigltallnRuts =
DIgltallnpuls =
OUTPUT CURRENT SETTLING
TIME
OUTPUT CAPACITANCE
COUT' (Pin 1)
COUT • (Pin 2)
CoUT' (Pin 1)
COUTO (Pin 2)
-
nstyp
nV-s typ
mVp-p max
/AS typ
Out, Load = 1000, CEXT = 13pF.
Digital Inputs = OV to Voo or Voo to OV.
VA.F = OV, all digital Inputs OV to Voo or Voo
to OV. Measured using OPA806 as output
amplifier.
VA.F = ±10V, 10kHz sine wave.
=
,
= V'H
= V'H
V'l
V"
NOTES: (1) Temperature ranges are: 0 to +70°C for JP, KP, JU ,and KU versions; -2SoC to +8SoC for AH, BH versions; -55°C to +12SoC for
SH, TH versions. (2) Guaranteed by design but not producthm tested.
'
160
MECHANICAL
Hermetic DIP
NOTE: Leads in true position
INCHES
MIN
MAX
.960
.220
.310
.200
.014
.023
.030
.070
.100 BASIC
.098
.008
.015
.125
.200
.290
.320
.015
.080
DIM
A
B
C
D
F
G
H
J
K
L
N
within .010" (.25mm) Rat MMC at
seating plane.
MILLIMETERS
MIN
MAX
24.38
'7,87
5.59
5.08
0.58
0.36
1.78
0.76
2.54 BASIC
2.49
0.20
0.38
3.18
5.08
8.13
7.37
0.38
2.03
R
L
-ll~J
L~
r
Plastic DIP
INCHES
MIN
MAX
.840
.940
.240
.280
DIM
A
B
C
G
D
J
H
K
L
M
N
.210
.014
.022
.100 BASIC
.040
.060
.008
.015
.115
.150
.280
.300
. 0'
10'
0.020
0.050
MILLIMETERS
MIN
MAX
21.34
23.88
B.l0
7.11
5.33
0.36
0.56
2.54 BASIC
1.02
1.52
0.20
0.38
2.92
3.81
7.11
7.B2
0'
10'
0.51
1.27
Pinl
J:::::::JI
G
J
H
L
M
N
JI--D
G '--
Seating
Plane
~
~~~
9.91
10.72
0'
0.00
10"
0.30
Q,
K
I
-1M
L--i
NOTE: Leads in true position
within .010" (.25mm) R at MMC at
seating plane.
1, f
B
11
11.84
11.33
11.25
7.26
7.67
B.86
7.24
2.36
2.74
0.38
0.48
1.27 BASIC
0.66
0.86
0.20
0.30
,
1
T
MILLIMETERS
MIN
MAX
11.43
l
IIPIfL-\1FI1IrY
"~
II \.~
Plastic sOle
DIM
A
A,
B
B,
C
D
!
B
-Hr
_
INCHES
MIN
MAX
.450
.466
.443
.446
.286
.302
.270
.285
.093
.108
.015
.019
.050 BASIC
.026
.034
.008
.012
390
.422
0'
10'
.000
.012
NOTE: Leads in true position
'::ithin .010" (.2Smm) R at MMC et
seating plane.
I
A
:
Pin 1
t1 lHJ
H
~t~
Dt1
""""1
, JJj 1[1 n nJ U U
_Gl
161
uJ-.J.
N]
,
,t-=- LL~IrfJ
c
cDr
M
D
/1
ABSOLUTE MAXIMUM RATINGS·
Vee (pin 16) to Ground .................................. +17V
VREF (pin 17) to Ground ................................. ±25V
VRPa (pin 18) to Ground ................................. ±25V
Digitallnput Voltage (pins 4-15) to Ground ..., -0.4V, Vee
VPIN " VPIN • to Ground ............................ -O.4V, Vee
Power Dissipation (any package):
To +75°C .............................................. 450mW
Derates above + 75°C ............................ -6mW/oC
Lead Temperature (soldering, 10s)................. +300°C
Storage Temperature: Ceramic Package ........... +150·C
Plastic Package ... ; ........ +125°C
permanent damage may occur on unconnected devices
subject to high energy electrostatic fields. When not in
use, devices must be stored in conductive foam or
shunts. The protective foam should be discharged to the
destination socket before devices are removed.
ENVIRONMENTAL SCREENING
(QM SCREENING)
Burr"Brown /QM models are environmentally screened'
versions of our standard industrial products, designed to
provide enhanced reliability. The screening is performed
to selected methods of MIL-STD-883. Reference to
these methods provides a convenient method of ~ommun
icating the screening levels and procedures employed; it
does not imply conformance to any other military
standards ,or to any methods of MIL-STD-883 other
than those specified. All of the DAC754lxH grades are
available with /QM screening.
• Strassas above those listed above may'cause permanent damage to the
device. This is a stress rating only and functional operation of the device
at these or any other condition above those Indicated In the operational
sections of this specification Is not Implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PIN CONNECTIONS
lOUT 1
/QM Screening (hermetic packages only)
lOUT 2
Ground
+VDD
la-Pin PI.ltlc DIP
Bit 12 (LSB)
(P Sufllx)
Bltl (MSB)
Bit2
Bit 3
1
Blt4
Blt9
BitS
Bit 8
BitS
BIt7
MIL-STD...3
Method, CondiDon
Screen
Bit 11 la-Pin HermetiC Ceramic DIP
Bit 10
(H Sufllx)
Internal Visual
la-Pin Plasllc SOIC
(USufflx)
CAUTION
The DAC7541A is an ESD (electrostatic discharge)
sensitive device. The digital control inputs have a special
FET structure, which turns on when the input exceeds
the supply by 18V, to minimize ESP damag,e. However,
High Temperature Storage
1008, C
lSO'C, 24hra
Temperalure Cycle
1010,C
-6510 +150'C,
10 cycles
Bum-In
1015, B
+125'C
Constant Accelerallon
2001, E
3O,000G
1014, AI or A2
1014,C
5 X 10" aim eels
60psig, 2hra
Hermeliclly: Fine Leak
Gross Leak
Exlernal Visual
2009
ORDERING INFORMATION
Model
DAC7541AJP
DAC7541AKP
DAC7541AJU
DAC7541AKU
D,AC7541AAH
DAC7541ABH
DAC7541ASH
DAC7541ATH
Relative
Accuracy (LSB)
±1
±1I2
±1
±1/2
±1
±1I2
±1
±1/2
Gain Error (LSB)
Package
±6
±1
±6
±1
±6
±1
±6
±1
Plastic DIP
Plastic DIP
Plastic SOIC
Plastic SOIC
HermetiC DIP
Hermetic DIP
Hernietic DIP
Hermetic DIP
162
Comments
2010. B
Temperature ,
Range (OC)
oto +70
Oto+70
Oto+70
Oto+70
-25 to +85
-25 to +85
-55 to +125
-55 to +125
TYPICAL PERFORMANCE CURVES
T. = +25'C, Voo = +15V unle•• otherwise noted.
GAIN ERROR VS SUPPLY VOLTAGE
FEEDTHROUGH ERROR VS FREQUENCY
10.0
5/2
.
,
ED
en
:::!.
g
3/2
i?
~
"-
w
c:
'iii
1.0
ff!
.c:
0.10
C1
e"
.c:
~
i
(!l
0.010
u.
112
0.001
0
15
10
100
1500
1250
~
:::!.
E
1000
",..
750
~
3/4
U
ifL
C.
i!:'
"c:
1M
SUPPLY CURRENT VS SUPPLY VOLTAGE
5/4
':;
100k
LINEARITY VS SUPPLY VOLTAGE
i
en
e
10k
Frequency (Hz)
3/2
ill
1k
Supply Voltage (V)
g.
1/2
en
.........
::;
114
0
5
500
(/
250
10
~~H=VDO
. 15
10
Relative Accuracy
This term (also known as linearity) describes the transfer
function of analog output to digital input code. The
linearity error describes the deviation from a straight line
between zero and full scale.
Differential Nonlinearity
Differential Nonlinearity is the deviation from an ideal
ILSB change in the output, from. one adjacent output
state to the next. A differential nonlinearity specification
of ±1.0LSB guarantees monotonicity.
Gain Error
.Gain error is the difference in measure of full-scale
output versus the ideal DAC output. The ideal output
for the DAC7541A is -(4095/4096) X (YREP). Gain error
may be adjusted to zero using external trims.
Output Leakage Current
The measure of current which appears at Outl with the
DAC loaded with all zeros, or at Out, with the DAC
loaded to all ones.
15
Supply Voltage (V)
Supply Voltage (V)
DISCUSSION OF
SPECIFICATIONS
x~.
",-------_o lOUT 2
CIRCUIT DESCRIPTION
FIGURE 2. DAC754IA Equivalent Cir,cuit (All Inputs
Low).
The DAC754IA is a 12-bit mUltiplying D/A converter
consisting of a highly stable thin-film R-2R ladder
network and 12 pairs of current steering switches on a
monolithic chip. Most applications require the addition
of a voltage or current reference and an output operational amplifer.
A simplified circuit of the DAC754lA is shown in Figure
1. The R-2R inverted bidder binarily divides the input
currents that are switched between lOUT I and lOUT 2 bus
lines. This switching allows a constant current to be
maintained in each ladder leg independent of the input
code.
The input resistance at VREFERENCE (Figure I) is always
equal to RLDR (RLDR is the. R/2R ladder characteristic
resistance and is equal to value "R''). Since RIN at the
VREFERENCE pin is constant, the reference terminal can be
driven by a reference voltage or a reference current, AC
or DC, of positive or negative polarity.
V••FeRENC.
10kCl
RFEEDBACK
R=10kCl
IAEFERENGE
_
,t
1""-------1---.,---0
I
6
Bit 1 (MSB) Bit 2
I
I
0
Bit 3
lOUT'
I
RFEEDBACK
lOUT 2
55pF
Output Impedance
The output resistance, as in the case of the output
capacitance, is also modulated by the digital input code.
The resistance looking back into the lOUT I terminal may
be anywhere between 10kn (the feedback resistor alone
when all digital inputs are low) and 7.5kn (the feedback
resistor in parallel with approximately 30kn of the R-2R
ladder network resistance when any single bit logic is
high).The static accuracy and dynamic performance will
be affected by this modulation. The gain and phase
stability of the output amplifier, board layout, and
power supply decoupling will all affect the dynamic
performance of the DAC754IA. The use of a compensation capacitor may be required when high-speed operational amplifiers are used. It may be connected across
the amplifier's feedback resistor to provide the necessary
phase compensation to critically dampen the output. See
Figures 4 and 6.
lOUT 2
I
-+
DYNAMIC PERFORMANCE
20kCl
I
I
ILEA....
FIGURE 3. DAC754lA Equivalent Circuit (All Inputs
High).
10kCl
20kCl
R-10kg
~~~~~-----,------~~--~--oIOOT1
~
VREFERENCE
6
Bit12 (LSB)
Digital Inputs (DTLlTTLlCMOS Compatible)
Switches shown for digital inputs "'high"'.
FIGURE 1. Simplified DAC Circuit.
EQUIVALENT CIRCUIT ANALYSIS
Figures 2 and 3 show the equivalent circuits for all
digital inputs low and high respectively. The reference
current is switched to lOUT 2 when all inputs are low and
lOUT I when inputs are high. The ILEAKAGE current source
is the combination of 'surface and junction leakages to
the substrate; the 1/4096 current source represents the
constant one-bit current drain through the ladder termi-
APPLICATIONS
OP AMP CONSIDERATIONS
The input bias current of the op amp flows through the
feedback resistor, creating an error voltage at the output
of the op amp. This will show up as an offset through all
164
codes of the transfer characteristics. A low bias current
op amp such as the OPA606 is recommended.
unipolar D/A converter. With an AC reference voltage
or current, the circuit provides two-quadrant mUltiplication (digitally controlled attenuation). The input/ output
relationship is shown in Table I.
C, phase compensation (10 to 25pF) in Figure 4 may be
required for stability w'hen using high speed amplifiers.
C, is used to cancel the pole formed by the DAC internal
feedback resistance and output capacitance at Out,.
Low offset voltage and Vos drift are also important. The
output impedance of the DAC is modulated with the
digital code. This impedance change (approximately
IOkO to 30kO) is a change in closed-loop gain to the op
amp. The result is that Vos will be multiplied by a factor
of one to two depending on the code. This shows up as a
linearity error. Offset can be adjusted out using Figure 4.
Gain may be adjusted using Figure 5.
TABLE I. Unipolar Codes.
Binary Input
MSB
MSB
B, • • • • • • • • • • 8 , 2
1111 1111 1111
1000 0000 0000
0000 0000 0001
0000 0000 0000
DAC7541A'
-f-Vcc
B'
B. B,
VREF ( -+-+-+
,248
-
<
OUT -
-
o
.. )
... +B-
4096.
BIPOLAR FOUR-QUADRANT OPERATION
-10V " VRE' " +10V
O--+--oVOUT
OPA606
FIGURE 7. pigitally Programmable Gain Block.
166
DAC7545
BURR-BROWN®
113131
ADVANCE INFORMATION
Subject to Change
Low-Cost 12-Bit CMOS
Buffered Multiplying
DIGITAL-TO-ANALOG CONVERTER
FEATURES
•
•
•
•
•
FOUR-QUADRANT MULTIPLICATION
LOW GAIN TC: 2PPM/oC Iyp
MONOTONICITY GUARANTEED OVER TEMPERATURE
SINGLE 5V TO 15V SUPPLY
TTL/CMOS LOGIC COMPATIBLE
•
•
•
•
•
VERY LOW OUTPUT LEAKAGE: IOnA max
VERY LOW OUTPUT CAPACITANCE: 70pF max
VERY LOW GLITCH ENERGY: 250nV-s Iyp
PROTECTION SCHOTTKY NOT REQUIRED
DIRECT REPLACEMENT FOR AD7545, PM7545A
DESCRIPTION
The DAC7545 is a low-cost CMOS, l2-bit fourquadrant multiplying, digital-to-analog converter
with input data latches. The input data is loaded into
the DAC as a i2-bit data word. The data flows
through to the DAC when both the chip select (CS)
and the write (WR) pins are at a logic low.
Laser-trimmmed thin-film resistors and excellent
CMOS current switches provide true 12-bit integral
and differential linearity. The device operates on a
single +5V to +15V supply and is available in 20-pin
side-brazed DIP, 20-pin plastic DIP or a 20-lead
plastic SOIC package. Devices are specified over the
commercial, industrial, and military temperature
ranges and are available with additional reliability
screening.
The DAC7545 is well suited for battery or other low
power applications because the power dissipation is
less than O.5m W when used with CMOS logic inputs
and_ VDD = 5V.
A,a
OBll-0BO
(Pins 4-15)
International Airport Industrial Park - P.O. Box 11400· Tucson. Arizona B5734 - Tel. (6021746·1111 - Twx: 910-952-1111 - Cable: BBRCORP - Telex: 66-6491
PDS·747
167
SPECIFICATIONS
ELECTRICAL
VREf = +10V, VOUT , = OV, ACOM = DCOM unless otherwise specified.
MODEL
DAC7545
Voo = +5V
PARAMETER
STATIC PERFORMANCE
Resolution
Relative Accuracy
Voo = +15V
UNITS
(max)
GRADE
T.=+25'C
TM1N-TM,uI"
T.=+25'C
TMIN""TMAXI1J
All
J,A,S
K,B,T
L,C,U
GL,GC,GU
J,A,S
K,B, T
L,C,U
GL,GC,GU
J,A,S
K,B, T
L,C,U
GL,GC,GU
12
±2
±1
±1/2
12
±2
±I
12
±2
±I
12
±2
±1
±1/2
±1/2
±1/2
±1/2
±1/2
±4
±I
±1
±I
±25
±15
±10
±6
±4
±I
±I
±1
±25
±15
±10
±7
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
±1/2
TEST CONDITIONS/COMMENTS
±4
±1
±I
±1
±20
±10
±5
±1
±1I2
±4
±I
±I
±I
±2O
±IO
±6
±2
All
±5
±5
±10
±10
ppm/'C
All
J, K, L, GL
A,B,C,GC
S, T, U, GU
0.015
±10
±10
±IO
0.03
50
50
200
0.01
10
10
10
0.02
50
200
%/%
nA
nA
nA
DYNAMIC PERFORMANCE
Current Settling Time'"
All
2
2
2
2
JJS
To 1/2LSB. Out, load = lOOf1.
DAC output ~asured from falling
edge of WR. CS = OV.
Propagation Delay'3I (from
digital input change to 90% of
final analog output)
Glitch Energy
AG Feedthrough at lOUT , 10'
All
All
All
300
400
5
250
ns
5
250
5
5
mVp_ pll5l
Out, load = l00f1. CEXT = 13pF14'.
V..., = ACOM.
VA.' '" ±IOV, 10kHz sine wave.
REFERENCE INPUT
.Input Resistance (pin 19 to ACOM)
All
7
25
7
25
7
25
7
25
kn 171
All
All
'70
200
70
200
70
200
70
200
pF
pF
DIGITAL INPUTS
V'H (Input High Voltage)
VOl (Input Low Voltage)
I'N (Input Current)'BJ
Input Capacitance l31 : DBo-DBu
WR.CS
All
All
All
All
All
2.4
0.8
±I
5
2.4
0.8
±IO
5
20
13.5
1.5
±I
5
Vl71
20
13.5
1.5
±10
5
20
SWITCHING
CHARACTERISTICS'"
Chip Select to Write Setup Time
All
280
200
0
250
175
140
100
180
120
0
160
100
90
60
10
200
150
0
240
170
120
80
10
2
100
10
2
100
10
Differential Nonlinearity
Gain Error (with Internal RFB)'"
Gain Temperature Coefflcientl31
(I!.Gain/l!.Temperature)
DC Supply Rejectlon'3I
(I!.Galn/I!.V••)
Output Leakage Current at Out 1
ACOUTPUTS
Output CapacitanceI3':
COUT 1
,COUT 2
20
'Chip Select io Write Hold Time, tC"
Write Pulse Width, tWA
All
All
Data Setup Time, tos
All
Data Hold Time, tOH
All
W
380
270
0
400
280
210
150
10
POWER SUPPLY,I..
All
All
All
2
100
10
2
500
10
Ics
50
nV-sf$l
,
1D-bit monotonic, T..1N to TMAX•
12-bit monotonic, TMIN to TMAX.
12-bit monotonic, TMIN to TMAX•
12-bit monotonic, TM'N to T.....
{D/A
register loaded with FFFH.
Gain error is adjustable using the
circuits In Figures 4 and 5. Typical
value is 2ppm/'C for V•• = +5V.
I!.Voo=±5%.
DBo-Ds" = OV; WR, CS = OV.
Input resistance TC = 3OOppm/'C15':
kCl
DBa-Os" = OV; WR, CS = OV.
DBo-Ds" = V•• ; WR, CS = OV.
V
/J A
pF
pF
V1N ::;. 0 or Voo.
ns·71
See Figure I.
V'N= OV.
V'N =OV.
nsl51
ns·
71
nsm
ns llli
tcs ?!: tWA. tcH ;;:: O.
n8m
nsl51
ns'71
rnA
/JA
pAIS)
All digital inputs VOl or V'H.
All digital inputs OV or Voo.
All digital Inputs OV or Va •.
NOTES: (1) Temperature ranges-JP, KP, LP, GLP: D'C to 7D'C. AH, BH, CH. GCH: -25'C to +85'C. SH. TH. UH. GUH: -55'C to +125'C. (2) This includes the
effect of 5ppm max gain TC. (3) Guaranteed but not tested. (4) DBo-DB" = OV to Vao or V.o to OV. (5) Typical. (6) Feedthrough can be further reduced by
connecting the metal lid on the ceramic package (suffix H) to DCOM. (7) Minimum. (8) Logic Inputs are MOS gates. Typical input current (+25'C) is less than InA.
(9) Sample tested at +25'C to ensure compliance.
.
168
MECHANICAL
20-Pln Hermellc DIP (H Sulllx)
IA'l
,,"J~[~~]]
t
~
r LJ
t--
k
lUi IUl lUi lUi ~ ~ W:!~-1
J L JL .
0
Pin numbers shown for reference
only. Numbers may not be marked
on package.
B
F~
G
NOTE: Leads in true position
wilhin .010" (.25mm) R al MMC
at seating plane.
,1
I
C
•
K
G
i
J
K
L
N
Sealing Piane
INCHES
MIN
MAX
.990
1.010
.285
.305
.100
.140
.016
.020
.054 TYP
.095
.105
.009
.012
.170 BASIC
.300
.320
.025
.045
DIM
A
B
C
D
F
MILLIMETERS
MIN
MAX
25.15
25.65
7.24
7.75
2.54
3.56
0.41
0.51
1.37TYP
2.41
2.67
0.23
0.31
4.32 BASIC
7.62
8.13
0.64
1.14
20-Pln Plasllc DIP (P Suffix)
~,J:::::::: ~
NOTE: Leads in true position
wilhin .010" (.2Smm) R al MMC
at seating plane.
f
Pin numbers shown for reference
only. Numbers may not be marked
on package.
B
r
DIM
A
B
C
D
G
H
•
C
t
\ t
Sealing~
Plane
[I
-J
tl tl tlJttlo tl tl
:l!f1ill1J1I1I1---.t
LG
.040
.060
J
.008
.015
0.20
0.38
K
L
M
N
.115
.280
O·
.000
.150
.300
10'
.020
2.92
7.11
3.81
7.62
10'
0.51
o·
0.00
NOTE: Leads in true position
wilhin .010" (.25mm) R ., MMC
at seating plane.
CJJJ
~~ tl
.210
.022
.100 BASIC
.014
MILLIMETERS
MIN
MAX
24.89
25.91
6.10
7.11
5.33
0.59
0.36
2.54 BASIC
1.02
1.52
20-Pln sOle (U Sulllx)
E:~
Pin1
,
K
INCHES
MIN
MAX
1,020
.980
.240
.280
*
C
NJ f
\-,JJf
c>
co
k,JJ
J1
M L L_ _
169
DIM
A
A,
B
B,
C
D
G
H
J
L
M
N
INCHES
MIN
MAX
.502
.518
.518
.495
.286
.302
.270
.285
.093
.108
.015
.019
.050 BASIC
.026
.034
.008
.012
.390
.422
O·
10'
.000
.012
MILLIMETERS
MIN
MAX
12.75
13.16
12.57
13.16
7.26
7.67
6.86
7.24
2.36 • 2.74
0.38
0.48
1.27 BASIC
0.66
0.86
0.20
0.30
9.91
10.72
O·
10'
0.00
0.30
PIN DESIGNATIONS
ABSOLUTE MAXIMUM RATINGS·
TA = +25'C unless otherwise noted.
OUTt
OGNO
(~SB)OB11
Voo to DCOM ................................... -0.3V, +17
Digital Input to DCOM .......................... -0.3V, Voo
V'F., V'EF, to DCOM ................................... ±25V
VPIN 1 to DCOM .................................. -0.3V, Voo
ACOM to DCOM .... : ....: ...................... -0.3V, Voo
(,ower Dissipation: Any Package to + 75'C ..... 450mW
. Derates aboye +75'C by ... 6mW/'C
Operating Temperature:
Commercial-JP, KP, LP, GLP .......... O'C to +70°C
Industrial-AH, BH, CH, GCH ........ -25°C to +85'C
Military-SH, TH, UH, GUH ......... -55'C to +125°C
Storage Temperature ................... -65'C to +150'C
Lead Temperature (soldering, lOs) ............... +300'C
1
VDD
WR
4
CS
OB10
OBO(LSB)
'20 Pin Epoxy DIP
(P Suffix)
OBI
OB7
OB2
OB6
OB3
20 Pin Hermetic DIP
(H Suffix)
OB5
20 Pin SOIC
(U Suffix)
*NOTE: Stresses above those listed above may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
WRITE CYCLE TIMING DIAGRAM
Mode.Selectlon
VDD
Write Mode
Hold Mode
CS and WR low, OAC responds
to data bus (OB,-OB,,) inputs
Either CS or WR high, dala bus
(OB,-OB,,) is locked oul;
OAC holds lasl data present when
CS or WR assumed high state.
¥iii - - -....~tWR-}r---;DD
NOTES: VDD = 5V; I, = tF = 20ns .
Voo :;::: 15V; tR = tF = 40n5.
All input signal rise and fall times measured from
10% to 90% oivDD.
Timing measurement reference is VIM + VIL.2
. I:--tos-8
Data In -----~X
Data Valid
(OB,-OB,,) _ _ _ _ _J. ' -
X'--VDD
. . . - - - if>
•
ENVIRONMENTAL SCREENING (QM SCREENING)
Burr-Brown /QM models are environmentally screened
versions of our standard industrial products, designed to
provide enhanced reliability. The screening is performed
to selected methods of MIL-STD-883. Reference to these
methods provides a convenient method of communicating
the screening levels and procedures employed; it does not
imply conformance to any other military standards or to
any methods of MIL-STD-883 other than thQse specified.
DISCUSSION OF
SPECIFICATIONS
Relative Accuracy
This term (also known as linearity) describes the transfer
function of analog output to digital input code. The
linearity error describes the deviation from a straight line
from zero to full scale (zero- and full-scale adjusted).
Differential Nonlinearity'
MIL-STD-883
High Temperature Storage
1008
C
+150'C, 24hrs
Differential nonlinearity is the deviation from an ideal
lLSB change in the output, for adjacent input code
changes. A differential nonlinearity specification of
±I.OLSB guarantees monotonicity.
Temperature Cycl.
1010
C
-65 to +150'C,
10 Cycles
Gain Error
Burn-In
1015
B
+125'C, Figure 1
Constant Acceleration.
2001
E
Hermeticity: Fine Leak
Gross Leak
1014
1014
AlorA2
C
External Visual
2009
Screen
Method Condition
Internal Visual
2010
B
Comments
Gain error is the difference in measure of full-scale
output versus the ideal DAC output. The ideal output
for the DAC7545 is -(4095/4096) (VREF). Gain error
may be adjusted to zero using external trims as shown in
.
the applications section.
30,OOOG
5 X 10-' atm cels
60psig, 2hrs
170
Output Leakage Current
Propogation Delay
The measure of current which appears at OUT I with the
DAC loaded with all zeros.
This is the measure of the time that is required for the
analog output to reach 90% of its final value for a change
in digital input code.
Multiplying Feedthrough Error
CIRCUIT DESCRIPTION
This is the AC error output due to capacitive feed through
from VREF to OUT I with the DAC loaded to all zeros.
This test is performed at 10kHz.
Figure 2 shows a simplified schematic of the digi"tal-toanalog converter portion of the DAC7545. The current
from the VREF pin is switched from lOUT 1 to AGND by
the FET switch. This circuit architecture keeps the resistance
at the reference pin constant and equal to RLDR, so the
reference could be provided by either a voltage or
current, AC or DC, positive or negative polarity, and
have a voltage range up to ±20V even with Voo = 5V.
The RLDR is equal to "R" and is typically Ilk!}.
The output capacitance of the DAC7545 is code dependent and varies from a minimum value (70pF) at code
OOOH to a maximum (200pF) at code FFFH.
Output Current Settling Time
This is the time required for the output to settle to a
tolerance of ±0.5LSB of final value from a change in
code of all zeros to all ones, or all ones to all zeros.
Propagation Delay
This is the measure of the delay of the internal circuitry
and is measured as the time from a digital code change to
the point at which the output reaches 90% ~f final value.
Digital-To-Analog Glitch Impulse
VREF
R
R
R
R
~
This is the measure of the area of the glitch energy
measured in nanovoit-seconds. Key contributions to
glitch energy are internal circuitry timing differences and
charge injected from digital logic. The measurement is
performed with VREF = GND and an OPA600 as the
output op amp and C 1 (phase compensation) = OpF.
1
I
Monotonicity
I
Monotonicity assures that the analog output will increase
or stay the same for increasing digital input codes. The
DAC7545 is guaranteed monotonic to l2-bit accuracy,
,except the J, A, S grades are specified to be IO-bit
monotonic.
OB9
Vee
~~
C,
C, of
OUT 1
R"
AGNO
R,
20
R,
19
1kO
c,
+
APPLICATIONS
VREF
OGNO
Figure 3 shows the DAC7545 connected for unipolar
operation. The high-grade DAC7545 is specified for a
ILSB gain error, so gain adjust is typically not needed.
However, the resistors shown are for adjusting full-scale
errors. The value of RI should be minimized to reduce
the effects of mismatching temperature coefficients
between the internal and external resistors: A range of
adjustment of 1.5 times the desired range will be adequate.
For example, for a, DAC7545JP, the gain error is
specified to be ±25LSB. A range of adjustment of
Vee 18
100kO 4 011(MSB) WR 17
,---........;5'-1010
6 09
'
CS
16 ;--'NI.--,
07
(LSB)OO
01 14
13
02
9 06
03 12
10 05
04 11
7 08
8
OBO
(LSB)
The input buffers are CMOS inverters, designed so that
when the DAC7545 is operated from a 5V supply (VOD),
the logic threshold is TTL-compatible. Being simple
CMOS inverters, there is a range of operation where the
inverters operate in the linear region and thus draw more
supply current than normal. Minimizing this transition
time and insuring that the digital inputs are operated as
close to the rails as possible will minimize the supply
drain current.
Power supply rejection is the measure of the sensitivity
of the output (full scale) to a change in the power supply
voltage.
VREF
AGNO
I
FIGURE 2. Simplified DAC Circuit of the DAC 7545.
Power Supply Rejection
+10V
I
I
FIGURE I. Burn-In Circuit.
171
±37LSB will be adequate. The equation below results in
a value of 4580 for the potentiometer (use 5000).
RI =:'
RLADDER
4096
(3 X Gain Error)
resistor of A2. The input/ output relationship is shown in
Table II.
TABLE II. Bipolar Codes.
Analog Output
Binary Code
MSB
R,
1111
1000
0111
0000
R,
FIGURE 3. Unipolar Binary Operation.
The addition of RI will cause a negative gain error. To
compensate for this error, R2 must be added. The value
of R2 should be one-third the value of R I.
The capacitor across the feedback resistor is used to
compensate for the phase shift due to stray capacitances
of the circuit board, the DAC output capacitance, and
op amp input capacitance. Eliminating this capacitor
will result in excessive ringing and an increase in glitch
energy. This capacitor should be as small as possible to
minimize settling time.
The circuit of Figure 3 may be used with input voltages
up to ±20V as long as the output amplifier is biased to
handle the excursions. Table I represents the analog
output for four codes into the DAC for Figure 3.
VOUT
WR
::;;
-VIN
CS
OBO-OBll
+5V
18
OAC7545
19
NOTE: There must be at
least lLSB or the amp will
saturate due to the lack of
feedback.
VOUT
-V'N (4095/4096)
-V'N (2048/4096) = 1I2V,N
-'V'N (1/4096)
OVolls
Figure 4. shows the connections for bipolar four-quadrant
operation. Offset can be adjusted with the Al to A2
summing resistor, with the input code set to 10000000
0000. Gain may be adjusted by varying the feedback
+VREF (2047/2048)
OVolls
-VREF (1/2048)
-VREF (2048/2048)
. . . - - - - - ' - - 0 V'N
LSB
111111111111
1000 0000 0000
0000 0000 0001
0000 0000 0000
1111
0000
1111
0000
OB,,+ DB" + DB. + ... + DB.
1
2
3
4096
Analog Output
Binary Code
1111
0000
1111
0000
Figure 5 shows a hook-up for a digitally-controlled gain
block. The feedback for the op amp is made up of the
FET switch and the R-2R ladder. The input resistor to
the gain block is the RFB of the DAC7545. Since the FET
switch is in the feedback loop, a "zero code" into the
DAC wili result in the op amp having no feedback, and a
saturated op amp output.
TABLE I. Unipolar Codes.
MSB
LSB
FIGURE 5. Digitally-Controlled Gain Block.
APPLICATIONS HINTS
CMOS DACS such as the DAC7545 exhibit a codedependent output resistance. This resistance and the Vos
of the op amp cause error currents to flowlhat look like
linearity and superposition errors. To minimize these
errors, an op amp with a Vos of less· than O.lLSB should
be selected. Also, the op amp should have a gain that is
sufficient to keep Vos below O.lLSB for the desired swing
and load at the op amp output.
VOUT=+VREF(
~+~+~+ ••• +~-1)
124
2048
FIGURE 4. Bipolar Four-Quadrant Multiplier.
As with all analog circuits, the care in designing the
ground system is critical to system accuracy. Static (DC)
errors should be held to less than O.lLSB for any point in
the analog ground path. Holy point sensing is encouraged,
so that all analog circuits are referenced. to the same
potential.
172
THIS PAGE iNTENTIONAllY LEFT BLANK
173
BURR-BROWN®
DAC8012
113131
ADVANCE INFORMATION
I
Subject to Change
Low Cost 12-Bit CMOS
Latched-Readback Multiplying
DIGITAL-TO-ANALOG CONVERTER
FEATURES
•
•
•
•
•
•
•
•
•
•
data word. The data is loaded into the DAC from
the bus when both the data strobe (DS) and the
read/write (RD/WR) pins are held low. Data may
be read back from the DAC by holding OS low and
(RD/WR) high. This readback feature enables the
user to monitor the state of mUltiple DACs on a
single bi-directional bus.
Laser-trimmed thin-film resistors and excellent
CMOS current switches provide true l2-bit integral
and differential linearity. The device operates on a
single +SV to + ISV supply and is available in 20-pin
side-brazed DIP, 20-pin plastic DIP or a 20-lead
plastic SOIC package. Devices are specified over the
commercial, industrial, and military temperature
ranges and are available with additional reliability
screening.
The DAC8012 is well suited for battery or other lowpower applications because the power dissipation is'
less than O.SmW when used with CMOS logic inputs
and VDO= SV.
DATA READ BACK CAPABILITY
FOUR-QUADRANT MULTIPLICATION
LOW-GAIN TC: 2PPM/oC typ
MONOTONICITY GUARANTEED OVER TEMPERATURE
SINGLE 5V TO 15V SUPPLY
VERY LOW OUTPUT LEAKAGE (IOnA maxi
VERY LOW OUTPUT CAPACITANCE (70pF maxi
VERY LOW GLITCH ENERGY (400nVs maxi
PROTECTION SCHOTTKY NOT REQUIRED
DIRECT REPLACEMENT FOR PMI DACB012
DESCRIPTION
The DAC8012 is a low-cost CMOS, 12-bit, fourquadrant multiplying, digital-to-analog converter
with input data latches and read back capabilities.
The input data is loaded into the DAc as a l2-bit
I
VRE ,
I 12-Bil .
OUT 1
c H l - - - - - - - - - I Multiplying )
1
L-JD~A~C~~-----~---toAGND
..., ?-L....._ _ _--,
1~---,__l1
RD/WRcHl--_-·~_· rr-l~np~u~tD~a~la.....,1
Os
T
~L.....,:,L;at;:.\Ch~es~·...
t ~ . :fL-------J I
I_Three-State L
Output Buffers .---
1
...
DGND
~
0
DB1.1 ... DBO
International Airport Industrial Park - P.O. Box 11400· Tucson, Arizon. 85734· Tel. (6021 746-1111 - Twx: 9tO-952-111t - Cable: BBRCORP - Telex: 66-6491
PDS-7sn
174
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VREF ;:;;;
+10V.
VOUT 1
~ av, AGNO ;:;;; DGND ;:;;; OV unless otherwise noted.
DACB012A, J, SI1I
DAC8012B, K, TI1I
PARAMETER
CONDITIONS
MIN
TYP
MAX
MAX
UNITS
±1I2
±1
±1
±2
±1
±1
±3
±4
Bits
LSB
LSB
LSB
LSB
±5
0.002
±5
0.002
ppm/oC
%1%
0.004
0.004
%1%
MIN
TYP
VOD ;:;;; +SV or +1SV
STATIC ACCURACY
Resolution
12
Relative Accuracy
Differential Nonlinearityl21
Gain Error(3U41
TA
TA
Gain Temperature Coefficient
/!l.Gain/.ll. Temperature(SU61
DC Supply Rejection
.Il.Gain/8.VoD
'"
Output Leakage Current at OUT 1
DYNAMIC PERFORMANCE
Propagation Delay(SU71181
Current Settling Timel5U81
n.Utr.h F.np.rgyISJ, V~O:"
= AGND
J:'.C Feedthrough at lOUT 1
(5)(111
12
T" = Full temperatura rango
TA ;:;;; Full temperature range
;:;;;
= +25°C
Full temperature Range
TA = +2S·C (t. Vee = ±S%)
TA ::;;:; Full temperature range
(t. Vee = ±S%)
TA = +2S·C, ROIWR = iSS = OV,
all digital inputs = OV
TA ;:;;; Full temperature range
S. T versions
J, K. A. B versions
10
10
nA
200'
25
200
25
nA
nA
300
300
ns
1
400
500
1
400
500
ps
nVs
nVs
5
5
mVp-p
15
kO
70
150
pF
pF
O.S
1
10
12
6
V
V
pA
pA
pF
pF
0.4
10
V
V
pA
300
400
215
375
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
mA
100
pA
TA=+25°C
(OUT 1 Load = tOon, em = 13pF)
T" ;:;;; Full temperature range
(to 112 LSB) leuT' Load = loon
T.=+25·C
T... = Full temperature range
TA = Full temperature range,
VREF = ±10V, f = 10kHz
REFERENCE INPUT
In'put Resistance
(Pin 19 to GNO)''''
T... = Full temperature range
ANALOG OUTPUTS
Output Capacitance'S)
COUT2
COUT1
T... = Full temperature range
DBO-DBII = OV, RDiWii =liS = OV
080-0811 = Vae, ROiWii =OS =OV
7
11
15
7
11
70
150
Vee = +5V
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current(9)
Input Capacitance l51 : OBO-OB11
ROIWR,D§
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
Three-State Output Leakage Current
SWITCHING CHARACTERISTICS""
Write to Data Stobe Setup Time
Data Strobe to Write Hold Time
Read to Data Strobe Setup Time
Data Strobe to Read Hold Time
Write Mode Data Strobe Width
Read Mode Data Stroba Width
Data Setup Time
Oata Hold Time
Data Strobe to Output Valid Time (3 )
Output Active Time from Deselection
POWER SUPPLY
Supply Current
T... = Full temperature
T... = Full temperature
TA=+25°C
TA = Full temperature
TA = Full temperature
T... = Full temperature
range
range
2.4
2:4
0.8
1
10
12
6
range
range
range
Ie = 400pA
le=-1.6mA
See timing diagram
TA =+25·C
TA =Full temperature range
TA=+25·C
TAo = Full ~emperature range
TA=+2S·C
TA = Full temperature range
TA=+25°C
TAo = Full temperature range
TA=+25°C
TAo = Full temperature range
TA=+25°C
TA = Full temperature range
TA =+25·C
TA = Full temperature range
TA=+2S·C
TA = Full ter:nperature range
TA=+2S·C
TAo = Full temperature range
TA=+25°C
TA = Full temperature range
4.0
4.0
0.4
10
0
0
0
0
0
0
0
0
180
250
220
290
210
250
0
0
0
0
0
0
0
0
0
0
180
250
220
290
210
250
0
0
300
400
215
375
TA = Full temperature range
(all digital inputs V1NL or VINH)
TA = Full temperature range
(all digital inputs OV or Vee)
2
10
175
100
10
ELECTRICAL CHARACTERISTICS (CO NT)
DAC8012A, J, Sm
DAC8012B, K, T'"
PARAMETER
CONDITIONS
MIN
TYP
I
MAX
MIN
I
TYP
MAX
I
UNITS
VDo =+15V
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current(9 )
Input Capacitance"': DBO-DBII
RDtWR, OS
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
Three-State Output Leakage Current
SWITCHING CHARACTERISTICSnm
Write to Data Strobe Setup Time
Data Strobe to Write Hold Time
Read to Data Strobe Setup Time
Data Strobe to Read Hold Time
Write Mode Data Strobe Width
Read Mode Data Strobe Width
Data Setup Time
Data Hold Time
Data Strobe to Output Valid Time
Output Active Time for Deselection
POWER SUPPLY
Supply Current
TA = Full temperature range
T. ;" Full temperature range
T.=+25'C
T. = Full temperature range
T. = Full temperature range
T. = Full temperature range
13.5
lo=3mA
lo=-3mA
13.5
0
0
0
0
0
0
0
0
100
120
110
150
1.5
10
V
V
pA·
180
220
180
250
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
mA
100
pA
0
0
0
0
0
0
0
0
100
120
110
ISO
90
120
0
0
90
120
0
0
180
220
180
250
TA = Full temperature range
(all digital inputs V,NL or V'NH)
T. = Full temperature range
(all digital inputs OV or Voo)
V
V
pA
pA
pF
pF
13.5
1.5
10
See Timing Diagram
T.=+25'C
TA::; Full temperature range
T.= +25'C
T. = Full temperature range
T.= +25'C
TA = Full temperature range
TA= +25'C
TA;;:; Full temperature range
T.= +2S'C
T. = Full temperature range
T.=+2S'C
TA = Full temperature range
. TA=+2S'C
T. = Full temperature range
T.=+25'C
TA = full temperature range
TA=+2S'C
T. = Full temperature range
T.=+2S'C
TA = Full temperature range
1.5
1
10
12
10
13.5
1.5
1
10
12
10
2
10
100
10
NOTES: (1) T. = -SS'C to +12S'C for S, T grades. T. = -25'C to +85'C for A. B grades. T. = O'C to +70'C for J. K grades. (2) 12-bit monotonic over full
temperature range. (3) Includes the effects of Sppm max gain T.C. (4) Using Internal R'B. DAC register loaded with 111111111111. (5) Guaranteed but
not testad. (6) Typical value is 2ppm/'C for Voo = +SV. (7) From digital input change to 90% of final analog output. (8) All digital inputs = OV to Voo: or
Voo to OV. (9) Logic inputs are MOS gates. typical input current (at +2S'C) is.less than InA. (10) Sample tested at +2S'C to ensure compliance.
(11) Feedthrough can further be reduced by connecting the metal lid on the sidebraze package (Suffix H) to DGND. (12) Resistor T.C. = +100ppm/'C
max. (13) CL = l00pF.
MECHANICAL
20-Pln Hermetic DIP (H Suffix)
IA~
~J~[~~]]
F~
t--
I P-li jlJj jl.Q \Ill P-li ~ ~ [}lJ ~----.t
J1 JL l~'~"~M'
NOTE: Leads in true position
within .010" (.2Smm) R at MMC
at seating plane.
t
Pin numbers shown for reference
only. Numbers may not be marked
on package.
B
~
t
C
rt
•
•
K
176
DIM
A
B
C
D
F
G
J
K
L
N
INCHES
MIN
MAX
.990
1.010
.285
.305
.100
.140
.016
.020
.054 TYP
.095
.105
.009
.012
.170 BASIC
.300
.320
.025
.045
MILLIMETERS
MIN
MAX
25.15
·25.65
7.24
7.75
2.54
3.56
0.41
0.51
1.37 TYP
2.41
2.67
0.23
0.31
4.32 BASIC
7.62
8.13
0.64
1.14
20-Pin Plastic DIP (P Suffix)
NOTE: Leads in true position
within .010" (.2Smm) R at MMC
at seating plane.
Pin numbers shown for reference
only. Numbers may not be marked
an package.
B
*
DIM
A
B
C
D
•
C
G
K
K
L
M
N
t
Seating
Plane
J.
H
J
4
INCHES
MIN
MAX
.!JSO
1.020
.240
.280
.210
.014
.022
.100 BASIC
.040
.060
.008
.015
.115
.150
.280
.300
O·
10'
.000
.020
MILLIMETERS
MIN
MAX
24.S!)
::!5.!l1
6.10
7.11
5.33
0.36
0.59
2.54 BASIC
1.02
1.52
0.20
0.36
2.92
3.81
7.11
7.62
O·
10'
0.00
0.51
20-Pln SOIC (U Suffix)
NOTE: Leads in true position
within .010" (.2Smm) R at MMC
at seating plane.
Pin numbers shawn far reference
only. Numbers may not be marked
on package.
\=- J)L.,
IlJJ
MLL~t
0
AGND
DB10
DB9
MILLIMETERS
MIN
MAX
12.75
13.16
12.57
13.16
7.26
7.67
7.24
6.86
2.74
2.36
0.38
0.48
1.27 BASIC
0.86
0.66
0.30
0.20
9.91
10.72
0'
10'
.0.00
0.30
(TA = +25°C, unless otherwise noted.)
Vee to DGND .............................•.......••• -.03V. +17V
Digital Input Voltage to DGND .......•...........•..•. , -0.3V. Vee
·AGND to DGND ........••....••.........•............ -0.3V. Vee
VR, •• VREF to DGND • . . . . . . • . . • . . • • . . . . . .. . . . . . . . . . . . . . . . • • .• ±2SV
V.,N , to DGND. . . . . • . . . . . . . . . . . . . • . • . . . .. . . . . . . . . . . . .. -0.3V. Vee
Power Dissipation (any package) to +7S'C ...•.....•...... 4SomW
Derates Above +7S'C by ..•....•............•...•....• 6mW/'C
Operating Temperature Range
Military Grades ......•.••....••.••....•••..... -SS'C to +12S'C
Industrial Grades ....•.........•..•............ -2S'C to +BS'C
Commercial Grades ............................... O°C to +70°C
Storage Temperature .....•...•...•...... , ....... -6S'C to +1SO'C
Lead Temperature (soldering. 60s) ••••....••••........•... +300'C
CAUTION
1. Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating
only and functional operation at or above this specification is not
implied. Exposure to above maximum rating conditions for extended
periods may affect device reliability.
.
2. Do not apply voltages higher than Vee or less than GND potential on
any terminal except VREF.
3. The digital inputs are zener protected, however, permanent damage
may occur on unprotected units from high-energy electrostatic
fields. Keep units in conductive foam at all times until ready to use.
Use proper antistatic handling procedures.
4. Remove power before inserting or removing units from their sockets.
OUT1
(MSB)DB11
J
L
M
N
INCHES
MIN
MAX
.502
.518
.495
.518
.286
.302
.270
.285
.093
,108
.015
.019
.050 BASIC
.034
.026
.012
.008
.390
.422
0'
10'
.000
.012
ABSOLUTE MAXIMUM RATINGS
PIN DESIGNATIONS
DGND
DIM
A
A,
B
B,
C
D
G
H
Voo
RDIWR
os
DBB
DBo(LSB)
-20 Pin Epoxy DIP
DB1
(P Suffix)
DB7
DB2
DB6
DB3
DBS
DB4
20 Pin Hermetic DIP
(H'Suffix)
20 Pin SOIC
(U Suffix)
177
TIMING DIAGRAM
twsu _____
Read
Cycle
NOTES:
VDn = +5V; tR = tF :::: 20n8
Voe = +15V; tR :;:: lJ = 40n8
os
All input signal rise and fall
ties measured trom 10% to
90% of VDD ,
Timing measurement
3-State
Data Bus -...;..;.;....;;..c
reference level is
'VlN+VIL
Dilts
Valid
--2-
ENVIRONMENTAL SCREENING (aM SCREENING)
Output Leakage Current
Burr-Brown IQM models are environmentally-screened
versions of our standard industrial products, designed to
provide enhanced reliability. The screening is performed
to selected methods of MIL-STD-883. Reference to these
methods provides a convenient method of communicating
the screening levels and procedures employed; it does not
imply conformance to any other military standards or to
any method of MIL-STD-883 other than those specified.
The measure of current which appears at OUT, with the
DAC loaded with all zeros.
Screen
MIL-STD-883
Method, Condition
,
2010, B
High Temperature Storage
1008, C
150'C, 24hrs
Temperature .Cycle
1010, C
-65'C to +150'C,
10 Cycles
Burn-In
1015, B
+125'C, Figure 1
Constant Acceleration
2001, E
30,000G
Hermeticity: Fine Leak
1014, A1 or A2
5 X 10'" atm cc/s
1014,C
60psig, 2hrs
Gross Leak
This is the AC error output due to capacitive feedthrough
from VREF to OUT, with the DAC loaded to all zeros.
This test is performed at 10kHz.
Output Current Settling Time
Comments
Internal Visual
External Visual
Multiplying Feedthrough Error
2009
DISCUSSION OF
SPECIFICATIONS
Relative Accuracy
This term (also known as linearity) describes the transfer
function of analog output to digital input code. The
linearity error describes the deviation from a straight line
from zero to full scale (zero and full scale adjusted).
Differential Nonlinearity
Differential nonlinearity is the deviation from an ideal
ILSB change in the output, for adjacent input code
changes. A differential nonlinearity specification of
±ILSB guarantees monotonicity.
Gain Error
Gain error is the difference in measure of full-scale output
versus the ideal DAC output. The ideal output for the
D~C8012 is -(409~/4096) (~REF) •. Gain error may be
adjusted to zero usmg external tnms as shown in the
applications section.,
This is the time required for the output to settle a
tolerance of ±1/2LSB of final value from a change in
code of all zeros to all ones, or 'all ones to all zeros.
Propagation Delay
This is the measure of the delay of the internal circuitry
and is measured as the time from a digital code change to
the point at which the output reaches 90% of final value.
Dlgital-To-Analog Glitch Impulse
:rhis is the measure of the area of the glitch ene'rgy
measured in nanovolt-seconds. Key contributions to
glitch energy are internal circuitry timing differences and
charge injected from digital logic. The measurement is
performed with V REF = GND.
Monotonicity
Monotonicity assures that the analog output will increase
or stay the same for increasing digital input codes. The
DAC8012 is guaranteed monotonic to 12-bit accuiacy
except the J, A, S grades are specified IO-bit monotonic.
Power Supply Rejection
Power supply rejection is the measure of the sensitivity
of the Qutput (full scale) to.a change in the power supply
'
voltage.
Propagation Delay
This is the measure of the time that is required fo'r th~
analog output to reach 90% of its final value for a change
in digital input code.
178
+10V
VREF
sition time and insuring that the digital inputs are operated
as close to the rails as possible will minimize the supply
drain current.
c,
VOO
DIGITAL SECTION
100kO
OUT1
R,.
AGNO
VREF
OGNO
Vee
011(MSB) RO/WR
R,
19
18
17
Os
010
10
Figure 3 shows the basic current switch. Figure 4 shows
the schematic of the input/ output buffers. When the OS
and the RD / WR are held low the latches are transparent
and pass data from the data bus to the DAC. When the
OS is held low and the RD / WR line is held high, the
three-state buffer becomes active and the data at the
DAC is presented to the digital input/ output lines for
data read back.
20
09
(LSB)OO
DB
01
07
02
06
03
04
05
R,
14
13
To Ladder
5kO
12
From
Interface
11
Logic
0--1
FIGURE I. Burn-In Circuit.
AGNO
FIGURE 3. N-Channel Current Steering Switch.
CIRCUIT DESCRIPTION
DIGITAL-TO-ANALOG SECTION
Figure 2 shows a simplified schematic of the digital-toanalog portion of the DAC80l2. The current from the
VREF pin is switched from louT I to AGND by the FET
switch for that bit. This circuit architecture keeps the
resistance at the reference pin constant and equal to RWR,
so the reference could be provided by either a voltage or
R
,------------RB
r-----------------<=~---------,ToAGNO
Switch
..-:----+-~
To OUT 1
Switch
R
A
R
WR
2R
2A
2R
2R
OUT1
1
WR
2R
FIGURE 4. Digital Input/Output Structure.
APPLICATIONS
I
I
I
OB9
I
I
I
OBO
LSB
AGNO
FIGURE 2. Simplified Circuit ofthe DAC80l2.
current, AC or DC, positive or negative polarity, and
have a voltage range up to ±20V even with Voo == 5V.
The RWR is equal to "R" and is typically llkO.
The output capacitance of the DAC8012 is code dependent and varies from a minimum value (70pF) at code
OOOH to a maximum (200pF) at code FFFH.
The input buffers are CMOS inverters, designed so that
when the DAC8012 is operated from a 5V supply (Voo),
the logic threshold is TTL compatible. Being simple
CMOS inverters, there is a range of operation where the
inverters operated in the linear region and thus draw
more supply current than normal. Minimizing the tran-
Figure 5 shows the DAC8012 connected for unipolar
operation. The high-grade DAC8012 is specified for a
lLSB gain error, so gain adjust is typically not needed.
However, the resistors shown are for adjusting full-scale
errors. The value of RI should be minimized to reduce
the effects of mismatching temperature coefficients
V,N
FIGURE 5. Unipolar Binary Operation.
179
between the internal and external resistors. A range of
adjustment of 1.5 times the desired range will be adequate.
For example, for a DACSOI2JP, the gain error is specified
to be ±3LSB. A range of adjustment of ±4.5LSB will be
adequate. The equation shows a minimum value of 330
for the pot.
.
RI = (RLADDER/4096) X (3 X Gain Error)
The addition of RI will cause a negative gain error. To
compensate for this error, R2 must be added. The value
of R2 should be one third the value of R I.
The capacitor across the feedback resistor is used to
compensate for the phase shift due to stray capacitances
of the circuit board, the DAC output capaCitance, and·
op amp input capacitance. Eliminating this capacitor
will result in excessive ringing and an increase in glitch
energy in higher speed applications. This capacitor should
be as small as possible to minimize settling time.
The circuit of Figure 5 may be used with input voltages
of up to ±20V as long as the output amplifier is biased to
handle the excursions. Table I presents the analog ouput
for four codes into the DAC for Figure 5.
TABLE I. Unipolar Output Code for Figure 5.
Binary Code
Analog Output
MSBI
ILSB
111111111111
1000 0000 0000
0000 0000 0001
0000 0000 0000
-Y,N (4095/4096)
-Y'N (2048/4096) = 1/2V,N
-Y,N (1/4096)
OVolls
BIPOLAR FOUR-QUADRANT OPERATION
Figure 6 shows the connections for bipolar four-quadrant
operation. Offset can be ·adjusted with the Al to A2
summing resi!rtor, with the input code set to 10000000
0000. Gain may be adjusted by varying the feedback
resistor of A2. The input! output relationship is shown iri
Table II.
Bo
B,
82
Figure 7 shows a hook-up for a digitally-controlled gain
block. The feedback for the op amp is made up of the
FET switch and the R-2R ladder. The input resistor to
the gain block is the RFB of the DACSOI2. Since the FET
switch is in the feedback loop, a "zero code" into the
DAC will result in the op amp having no feedback and a
saturated op amp output. TheDAC8012 readback feature
makes the DACSOl2 espeCially good for this configuration
VOUT :;:;::
-VIN
OB,,+ OB,o+ DB, + ... + OBo
1
2
3
4096
RO/WR OS OBO-OBll
+5V
18
19
VOUT
FIGURE 7. Digitally-Controlled Gain Block.
when an automatic gain or automatic calibration routine
is used. If the logic were set up to calibrate a value via
logic external to the processor (successive approximation
register), then when the calibration is done, the procc:ssor
could read the DACSOl2 to store away the calibration
code.
Figure S shows the DACSOl2 interfaced to a l6-bit
Bn
vouT=+VREF(,+T + 3 + ••• + 2048 -1 ).
FIGURE 6. Bipoiar Four-Quadrant Mulitplier.
T~BLE II. Bipolar Codes and Analog Output for
Figure 6.
68000MPU
Binary
MSBI
ILSB
111111111111
1000 0000 0000
0111 11111111
0000 0000 0000
Analog Output
+VREF (2047/2048)
oVolts
FIGURE S. l6-Bit Microprocessor to DACSOl2
Interface.
-VREF (1/2048)
-VREF (2048/2048)
180
microprocessor. The interface requires only address decoding to select the DAC to be written to or read from.
Figure 9 shows an interface scheme for using the
DAC8012 with an 8-bit microprocessor. The data for the
first 4 bits are written and latched into the external write
latch and the next 8 bits are presented on the bus. The
DAC8012 is then instructed to pass the data through the
internal DAC latch (WR + DS) and all 8 bits are
transferred into the DAC. Reading data back is done in
the same manner.
·Qo = Oecoded address for latch to DAe operations.
Q, = Decoded address for data bus to input latch operation.
a, = Decoded address for output latch to data bU5 operation.
A,5t-----------------------------------------------------------~
Address Bus
Ao t-------....,
Q2'
Processor
System
FIGURE 9. 8-Bit Processor to DAC8012 Interface.
181
BURR-BROWN®
PCM56P
1E3E31
DESIGNED FOR AUDIO
Serial Input 16-Bit Monolithic
DIGITAL-TO-ANALOG CONVERTER
This converter is completely self-contained with a
stable, low noise, internal zener voltage reference;
high speed current switches; a resistor ladder. network; and a fast settling, low noise output operational amplifier all on a single monolithic chip. The
converters are operated using two power supplies
that can range from±5V to ±12V. Power dissipation
with ±5V supplies is typically less than 200mW.
Also included is a provision for external adjustment
of the MSB error (differential linearity error at
bipolar zero) to further improve total harmonic
distortion (THO) specifications if desired. Few
external components are necessary for operation,
and all critical specifications are 100% tested. This
helps assute the user of high system reliability and
outstanding overall system performance.
The PCM56P is packaged in a high-quality f6-pin
molded plastic DIP package and has passed operating life tests under simultaneous high-pressure,
high-temperature, and high-humidity conditions.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
SERIAL INPUT
LOW COST
NO EXTERNAL COMPONENTS REQUIREO.
16~BIT RESOLUTION
15-BIT MONOTONICITY, TYP
0.001% OF FSR TYP DIFFERENTIAL LINEARITY
ERROR
0.0025% MAX THO IFS Input, K Grade, 16 Bits)
0.02% MAX THO 1-20dB Input, K Grade, 16 Bits)
1.511s SETTLING TIME, TYP (Voltage Oul)
96dB DYNAMIC RANGE
±3V or ±lmA AUDIO OUTPUT
EIAJ STC-OD7-COMPATIBLE
OPERATES ON ±5V 10 ±12V SUPPLIES
PINOUT ALLOWS lOUT OPTION
PLASTIC DIP PACKAGE
DESCRIPTION
The PCM56P is a state-of-the-art, fully monotonic,
digital-to-analog converter that is designed and
specified for digital audio applications. This device
employs ultra-stable nichrome (NiCr) thin-film
resistors to provide monotonicity, low distortion,
and low differential linearity error (especially around
bipolar zero) over long periods oftime and over the
full operating temperature.
16-Bit Input Latch
16-Bit Serial-te-Parallel Conversion .
Clock LE Data
International Airport Induslrial Park· P.O. Box 11400 . Tucson. Ari~ona 85734 . Tel. (6021 746·1111 . Twx: 91()'952·1I11 • Cable: BBRCORP • Telex: 66·6491
PpS-700
182
SPECIFICATIONS
ELECTRICAL
MECHANICAL
Typical at +25°C and nominal power supply voltages of ±5V unless otherwise noted.
MODEL
PCMS6P/-J/-K
MIN
TYP
MAX
UNITS
+VL
+0.8
+1.0
-50
Bits
V
V
pA
pA
MHz
E-
INPUT
16
+2.4
0
bH. V1N = +2.7V
ItL. V1N = +O.4V
Input Clock Frequency
10.0
l,l
Jl
P
.r' 'v' 'v' 'v' V
'v' 'v' 'lI
Pin 1
ACCURACY
Gain Error
Bipolar Zero Error
Differential Linearity Error
Noise (rms, 20Hz to 20kHz) at Bipolar Zero (Vou, models)
±2.0
±30
±0.001
6
TOTAL HARMONIC DISTORTION
Vo = ±FS at I = 991Hz: PCM56P-K
PCM56P-J
PCM56P
Vo = -20dB at f = 991 Hz: PCM56P-K
PCM56P-J
0.0025
0.004
0.008
0.020
0.040
%
%
%
%
%
0.018
C.C~C
".
Vo = -60dB at f = 991 Hz: PCM56P-K
PCM56P-J
PCM56P
1.8
1.8
1.8
2.0
4.0
4.0
%
%
%
MONOTONICITY
15
Bits
±25
±4
ppm of FSRI'C
ppm of FSR/'C
1.5
1.0
12
350
350
ps
ps
VIps
ns
ns
I~VI"I"'UI'
DRIFT (O'C to +70'C)
Total Oriftl31
Bipolar Zero Drift
SETTLING TIME (to ±0.006% of FSR)
Voltage Output: 6V Step
lLSB
Slew Rate
Current Output, lmA Step: 100 to 1000 load
1kCl load l41
WARM-UP TIME
OUTPUT
±8.0
±3.0
I
I 1
±1.0
1.2
+4.75
-4.75
+VL =
-VL =
+VL =
-VL =
..I
0.10
Indefinite to Common
POWER SUPPLY REQUIREMENTS'"
+5V)
-5V)
+12V)
-12V)
----1
rrrv~
-J~D
G...
-, ,- H
::"..:'0" :-1"0"
~
IL.---.J
-II-M
j\..J
Min
1
Voltage Output Configuration: Bipolar Range
Output Current
Output Impedance
Short Circuit Duration
Current Output Configuration:
Bipolar Range (±30%)
Output Impedance (±30%)
.... FI--
%
mV
%of FSR I21
pV
0.002
0.002
0.002
O.ot8
0.018
Voltage: +Vs and +VL
-Vsand -VL.
Supply Drain (No Load): +V (+V. and
-V (-Vs and
+V'(+Vs and
-V (-V. and
Power Dissipation: Vs and VL. = ±5V
Vs and VL = ±12V
r"d
- , }-
TRANSFER CHARACTERISTICS
+5.00
-5.00
+10.0
-25.0
+12.0
-27.0
175
468
+13.2
-13.2
+17.0
-35.0
260
V
mA
0
+70
+70
+100
0
-25
-60.
mA
kO
V
V
mA
mA
mA
mA
mW
mW
'C
'C
'C
NOTES: (1) Logic input levels are TTL/CMOS-compatible. (2) FSR means full-scale range and is equivalent
to 6V (±3V) for PCM56 in the Vom moile. (3) This is the combined drift error due to gain, offset, and linearity
over temperature. (4) Measured with an active clamp to provide a low impedance for approximately
200ns. (5) All specifications assume +Vs connected to +VL and -Vs connected to -VL.. If supplies are
connected separately. -VL. must not be more negative than -Vs supply voltage to assure proper operation. No
similar restriction applies to the value of +VL. with respect to +Vs.
183
NOTE; Leads in true position
within .010" (.25mm) R at MMC
at seating plane.
PINS: Pin material and plating
composition conform to method
2003 (solderability) of MIL-STD-.
883 (except paragrah 3.2).
TEMPERATURE RANGE
Specification
Operation
Storage
A
A, - - - -
r1 r"1 r'l r'l
DIGITAL INPUT
Resolution
Digitallnputs 'll · V,"
VOL
CASE: Plastic
DIM
A
A,
B
B,
C
D
F
G
H
J
K
L
M
N
p
INCHES
MILLIMETERS
MIN
MAX
.740
.800
.725
.7B5
.230
.290
.200
.250
.120
.200
.015
.023
.070
.030
.100 BASIC
0.02
0.05
.OOB
.015
.150
.070
.300 BASIC
15'
0'
.030
.010
.050
.025
MIN
MAX
1B.BO
20.32
1B.42
'9.94
5.85
7.38
6.36.
5.09
3.05
5.09
0.38
0.59
1.78
0.76
2.54 BASIC
0.51
1.27
0.20
0.38
1.7B
3.B2
7.63 BASIC
15'
0'
0.25
0.76
0.64
1.27
ORDERING INFORMATION
Model
THO at FS ('!oj
PCM56P
PCM56P-J
PCM56P-K
0.008 Max
0.004
0.0025
CONNECTION DIAGRAM
PIN ASSIGNMENTS
1
2
3
4
5
6
7
B
9
10
11
12
13
14
15
16
-Vs
lOG COM
+VL
NC
ClK
lE
DATA
-VL
VO UT
RF
SJ
ANA COM
louT
MSBADJ
TRIM
+Vs
Analog Negative Supply
logic Common
logic Positive Supply
No Connection
Clock· Input
Latch Enable Input
Serial Data Input
logic Negative Supply
Voltage Output
Feedback Resistor
Summing Junction
Analog Common
Current Output
MSB Adjustment Terminal
MSB Trim-pot Terminal
Analog Positive Supply
NOTE: '(1) MSB error (Bipolar Zero differenllailinearity error)
can be adjusted to zero using the external circuit shown 'In
Figure 6.
ABSOLUTE MAXIMUM RATINGS
DC Supply Voltages ..................................... ±16VDC
Input logic Voltage ............... , ........... -tV to +VS/+VL
Power Dissipation....... .......... ... .. ...... .. ... ... .. .. 850mW
Operating Temperature ....................... -25·C to +70·C
Storage Temperature ....................... -60·C to +100·C
lead Temperature During Soldering ............ lOs at 300·C
or time is due to the drift of the internal reference zener
diode. The converter is designed so that these drifts are
in opposite directions. This way the Bipolar Zero voltage
is virtually unaffected by variations in the reference
voltage.
DISCUSSION OF
SPECIFICATIONS
The PCM56P is specified to provide.critical performance
criteria for a wide variety of applications. The most
critical specifications for a D j A converter in audio
applications are Total Harmonic Distortion, Differential
Linearity Error, Bipolar Zero Error, parameter shifts
with time and temperature, and settling time effects on
accuracy.
The PCM56P is factory-trimmed and tested for all
critical key specifications.
The accuracy of a D j A--i:onverter is described by the
transfer function shown in Figure I. Digital input to
analog output relationship is shown in Table I. The
errors in the DjA converter are combinations of analog
errors due to the linear circuitry, matching and tracking
properties ~f the ladder and scaling networks, power
supply rejection, and reference errors. In summary, these
errors consist of initial errors including Gain, Offset,
Linearity, Differential Linearity, and Power Supply
Sensitivity. Gain drift over temperature rotates the line
(Figure I) about the bipolar zero point and Offset drift
shifts the line left or right over the operating temperature
range. Most of the Offset and Gain drift with temperature
0)11...1111
0111 ... 1110
:;
c.
t
1
AIIBItSOn,
Gain
Drift, •
_oo'"~
•
0000 ... 0001
.5
0000 ... 0000
]i
'c, 1111 ... 1111
0
1111 ... 1110
1000 ... 0001
1000 ... 0000
Offset
Drift
\
•
L'
•
\
Bipolar Zero
I
•
-FSR/2
,
.
I' Analog Output I (+FSRl2) -ILSB
·See Table I for digital code' definitions.
FIGURE I. Input vs Output for an Ideal Bipolar DjA
Converter.
TABLE I. Digital Input to Analog Output Relationship.
Digital Input
184
Analog Output
Binary Twos
Complement (BTC)
DACOutput
VOUT
Mode
Current (mA),
lOUT Mode
7FFF Hex
8000 Hex
0000 Hex
FFFF Hex
+ Full Scale
- Full Scale
Bipolar Zero
Zero-1LSB
+2.999908
-3.000000
0,000000
-0.000092
-0.999970
+1.000000
0.000000
+0.030500"A
Voltage (V),
Settling times are specified to ±0.006% of FSR: one for
a large output voltage change of 6V and one for a ILSB
change. The ILSB change is measured at the major carry
(0000 hex to ffff hex), the point at which the worst-case
settling time occurs.
DIGITAL INPUT CODES
The PCM56P accepts serial input data (MSB first) in the
Binary Twos Complement (BTC) form. Refer to Table I
for input/ output relationships.
BIPOLAR ZERO ERROR
Initial Bipolar Zero Error (Bit I "on" and all other bits
"off") is the deviation from OV out and is factorytrimmed to typically ±30mV at +25°C.
1.01
l
!ii"
u"
em
0.31---\----'__--+-+---_
Cl
0.11---\-+
,.,a:
DIFFERENTIAL LINEARITY ERROR
Differential Linearity Error (DLE) is the deviation from
an ideal ILSB change from one adjacent output state to
the next. DLE is important in audio applications because
excessive DLE at Bipolar Zero (at the "major carry') can
result in audible crossover distortion for low level output
signals. Initial DLE on the PCM56P is factory trimmed
to typically ±0.001% of FSR. The MSB DLE is adjustable to zero using the circuit shown in Figure 6.
a~
u..!.
<3
0.031----1H-
u.
0.011--~~1__--_\r_--_I
c
"
~ 0.0031-----1~--_44_--_I
!! .
0.001 ' -_ _---II.-~......_L_._..J
0.1
1.0
10.0
0.01
Settling Time (ps)
FIGURE 3. Full Scale Range Settling Time vs Accuracy.
POWER SUPPLY SENSITIVITY
Changes in the DC power supplies will affect accuracy.
The PCM56P power supply sensitivity is .shown by
Figure 2. Normally, regulated power supplies with 1% or
less ripple are recommended for use with the DAC. See
also Power Supply Connections paragraph in the Installation and Operating Instructions section.
126
JstW~LUs
120
STABILITY WITH TIME AND TEMPERATURE
The parameters of aD/A converter designed for audio
applications should be stable over a relatively wide·
temperature range and over long periods of time to
avoid undesirable periodic readjustment. The most important parameters are Bipolar Zero Error, Differential
Linearity Error, and Total Harmonic Distortion. Most
of the Offset and Gain drift with temperature or time is
due to the drift of the internal reference zener diode. The
PCM56P is designed so that these drifts are in opposite
directions so that the Bipolar Zero voltage is virtually
unaffected by variations in the reference voltage. Both
DLE and THD are dependent upon the matching and
tracking of resistor ratios and upon VBE and hFE of the
current-source transistors. The PCM56P was designed,
so that any absolute shift in these components has
virtually no effect on DLE or THD. The resistors are
made of identical links of ultra-stable nichrome thinfilm. The current density in these resistors is very low to
further enhance their stability.
,
114
~
10 108
:2.
"o
102
'"a:,.,
96
~
C.
g-
en
-
~
Negative Supplies
90
DYNAMIC RANGE
The Dynamic. Range is a measure of the ratio of the
smallest signals the converter can produce to the fullscale range and is usually expressed in decibels (dB). The
theoretical dynamic range of a converter is approximately
6 X n, or about 96dB of a l6-bit converter. The actual, or
useful, dynamic range is limited by noise and linearity
errors and is therefore somewhat less than the theoretical
limit. However, this does point out that a resolution of at
least 16 bits is required to obtain a 90dB minimum
dynamic range, regardless ofthe accuracy ofthe converter. Another specification that is useful for audio applications is Total Harmonic Distortion.
11.
84
1\
78
72
66
1
10
100
1k
Frequency (Hz)
10k
100k
FIGURE 2. Power Supply Sensitivity.
SETTLING TIME
Settling time is the total time (including slew time)
required for the output to settle within an error band
around its final value after a change in input (see Figure
3).
TOTAL HARMONIC DISTORTION
THD is useful in audio applications and is a measure of
the magnitude and distribution of the Linearity Error,
185
Differential Linearity Error, and Noise, as well as Quantization Error. To be useful, THD should be specified for
both high level and low level input signals. This ~rror is
unadjustable and is the most meaningful indicator of
D/ A converter accuracy for audio applications.
Figure 5 shows typical THD as a function of frequency.
0.1
~ 0.05
c
The THD is defined as the ratio of the square root of the
sum of the squares of the values of the harmonics to .the
valueofthe fundamental input frequency and is expressed
in percent or dB. The rms value of the PCM56P error
.
referred to the input can be shown to be
~rrns
=V
I/n
0
(J
'~"
~
0.001
100
X 100%
For optimum performance and noise rejection, power
supply decoupling capacitors should be added as shown
in the Connection Diagram. These capacitors (lp.F tantalum or electrolytic recommended) should be located
close to the converter.
MSB ERROR ADJUSTMENT PROCEDURE
(OPTIONAL)
The MSB error of the PCM56P can be adjusted to make
the differential linearity error (D LE) at BPZ essentially
zero. This is important when the signal output levels are
very low, because zero crossing noise '(DLE at BPZ)
becomes very significant when compared to the small
code changes occurring in the LSB portion of the
converter.
Differential linearity error at bipolar zero and THD are
guaranteed to meet data sheet specifications without any
external adjustment. However, a provision has been
made for an optional adjustment of the MSB linearity
point which makes it possible to eliminate DLE error at
BPZ. Two· procedures are given to allow either static or
dynamic adjustment. The dynamic procedure is preferred
because of the difficulty associated with the static method
(accurately measuring 16-bit LSB steps).
To statically adjust DLE at BPZ, refer to the circuit
shown in Figure 6 or the PCM56 connection diagram.
10.0
c
0
0
(J
0.4
0.2
0.1
'E."
0.04
0.02
]i
~
0.01
0
J:
,,\
'"
0.004
0.002
14 Bits
r0:V
~
I~Bits
~
200kO
100kO
470kO
Trim 15O---¥.Iv--ooooiIj,..,.....----"""'''r--_Q I -Vs
0.001
-60 -50 -40 -30 -20 -10
OdB equals Full Scale Range (FSR)
20k
POWER SUPPLY CONNECTIONS
,
t:
~
10k
INS.TALLATION AND
OPERATING INSTRUCTIONS
I
~
Ik
Frequency (Hz)
FIGURE 5. Total Harmonic Distortion (THD) vs
Frequency.
This expression indicates that; in general, there is a
correlation between theTHDand the square root of the
sum of the squares of the linearity errors at each digital
word of interest. However, this expression does not
mean that the worst-case linearity error of the D / A is
directly correlated to the THD.
For the PCM56P the test period was chosen to be 22.7p.s
(44.1kHz), which is compatible with the EIAJ STC-007
specification for peM audio. The test frequency is
991Hz and the amplitude of the input signal is OdB,
-20dB, and -60dB down from full scale.
Figure 4 shows the typical THD as a function of output
voltage.
1.0
I
I\~~II scale)
iii
(I)
where Errns is the rms signal-voltage level.
~
0.005
;§ 0.002
i = 1
i =1
--~----=---------Errns
4.0
2.0
( 20dB)
0.01
0
J:
where n is the number of samples in one cycle of any
given sine wave, El(i) is the linearity error of the
PCM56P at each sampling point, and EQ(i) is the
quantization error at each sampling point. The THD can
then be expressed as
(2)
THD = ~nns/Enns
VI/n
0
t:
~ 0.02
0
MSB Adjust 1 4 o - - - - - - - - l
VO~T (dB)
FIGURE 6. MSB Adjustment Circuit.
FIGURE 4. Total HarmOniC Distortion (THD) vs YOUT.
186
After allowing ample warm-up time (5-10 minutes) to
assure stable operation of the PCM56, select input code
FFFF hexadecimal (all bits on except the MSB). Measure
the audio output voltage using a 6-1/2 digit voltmeter
and record it. Change the digital input code to 0000
hexadecimal (all bits off except the MSB). Adjust the
100kO potentiometer to make the audio output read
92p,V more than the voltage reading ofthe previous code
(a ILSB step = 92p,V).
A much simple~ method is to dynamically adjust the
DLE at BPZ. Again, refer to Figure 6 for circuitry and
component values. Assuming the device has been installed
in a digital audio application circuit, send the appropriate
digital input to produce a -80dB level sinusoidal output.
While measuring the THD of the audio circuit output,
adjust the 100kO potentiometer untit"a minimum level of
distortion is observed.
stopped before the "17th" Clock cycle occurs, however,
the last serial input shift will not occur (the MSB will be
in the bit 2 position). In any application where clock is
noncontinuous, attention must be given to providing
enough clocks to fully input the data word.
Figure 7 refers to the general input format required for
the PCM56P. Figure 8 shows the specific relationships
between the various signals and their timing constraints.
Data
Input
INPUT TIMING CONSIDERATIONS
Figures 7 and 8 refer to the input timing required to
interface the inputs of PCM56P to a serial input data
stream. Serial data is accepted in Binary Twos Complement (BTC) with the MSB being loaded first. Data is
clocked in on positive going clock (CLK) edges and is
latched into the DAC input register on negative going
latch enable (LE) edges.
MSB
FIGURE 8. Input Timing Relationships.
INSTALLATION
CONSIDERATIONS
The latch enable input must be high for at least one clock
cycle before going low, and then must be held low for at
least one clock cycle. The last 16 data bits clocked into
the serial input register are the ones that are transferred
to the DAC input register when latch enable goes low. In
other words, when more than 16 clock cycles occur
between a latch enable. only the data present during the
last 16 clocks will be transferred to the OAC input
register.
One requirement for clocking in al: 16 bits is the
necessity for a "17th" clock pulse. This automatically
occurs when the clock is continuous (last bit shifts in on
the first bit of the next data word). When the clock is
If the optional external MSB error circuitry is used, a
potentiometer with adequate resolution and a TCR of
100ppm/oC or less is required. Also, extra care must be
taken to insure that no leakage path (either AC or DC)
exists to pin 14. If the circuit is not used, pins 14 and 15
should be left open.
The PCM converter and the wiring to its connectors
should be located to. provide the optimum isolation from
sources of RFI and EMI. The important consideration
in the elimination of RF radiation or pickUp is loop area;
111
Clock
Data
Latch
Enable
t
r - - - - - - - - - - -- - - - - - -- - -- - - - - - - - - -- - - ---
~:
!~
.. -.. _....
.-_ ..... -- - .. - .. - - - - - - .. - - - - - - - -- - _.. -- --- - - _... - ..
NOTES: (1) II clock is stoppad between Input 01 16-blt data words, latch enable (LE) must remain low until after the first clock of the next
16-bit data word stream. (2) Data format ·is binary two's complement (BTC). Individual data bits are clocked in on the corresponding
positive clock edge. (3) Latch enable (LE) must remain low at least one clock cycle after going negative. (4) Latch enable (LE) must be
high for at least one clock cyclebelore going negative.
FIGURE 7. Input Timing Diagram.
187
therefore, signal leads and their return conductors should
be kept close together. This reduces the external magnetic
field along with any radiation. Also, if a signal lead and
its return conductor are wired close together, they
represent a small flux-capture cross section for any
external field. This reduces radiation pickup in the
circuit.
between the left and right channels. The design is greatly
simplified because the PCM56P is a complete D/ A
converter requiring no external reference or' output op ,
amp.
A sample/hold (S/H) amplifier, or "deglitcher" is
required at the output of the D / A for both the left and
right channel, as shown in Figure 9. The S/H amplifier
for the left channel is composed of AI, SWI, and
associated circuitry. Al is used as an integrator to hold
the analog voltage in CI. Since the source and drain of
the FET swtich operate at a virtual ground when "C"
and "B" are connected in the sample mode, there is no
increase in d,istortion caused"by the modulation effect of
RON by the audio signal.
APPLICATIONS
Figures 9 and 10 show a circuit and timing diagram for a
single PCM56P used to obtain both left- and rightchannel output in a typical digital audio system. The
audio output of the PCM56P is alternately time-shared
2,2kO
2,2kO
Serial Data
Clock
PCM56P
Latch Enable
Left Channel
Output to LPF
2,2kO
Left Channel
Deglitcher Control
2,2kO
R3
Right Channel
Deglitcher Control
A "low" signal on the deglitcher control closes switch "A",
while a "high" Signal closes switch "8".
·1 OPA101AM or 1/4 OPA404KP
or 1 OPA606KP
FIGURE 9. A Sample/Hold Amplifier (Deglitcher) is Required at the Digital-to-Analog Output for Both Left and
Right Channels.
I
I
-t1
"'1".'- - - - - - 4 4 , l k H z - - - - -_ _
I
I
I,-----------~ ,----------~I,-----------~
LeltChannel
Right Channel
Lelt Channel
Right Channel
Serial Data
nL...--_---'nL.-__rL
Latch E n a b l e l ' - - _ - - - - - ' n
n:
--l
Right Channel
-i
DeglitcherControl _ _ _ _ _ _ _
I
~ t", = 1,51'5 DAC Settling Time
II
--l
.
n..-----------
I I
-In. ._.. . ;_____________...In. ________
Left Channel
_ _ _ _ _ _ _ _+!I_ _
Deg litcher Control
••
I
'
•
•
•
I
f--
tOEt.Ay 4.5p8 max
The deglitcher control signals are generated by timing control logic, The fast settling time of the PCM56P makes it possible to
minimize the delay between left and right channels to about 4.5l's, which reduces phase error at the higher audio frequencies,
FIGURE 10. Timing Diagram for the Deglitcher Control Signals.
188
Most previous digital audio circuits used a higher order
(9-13 pole) analog filter. However, the phase response of
an analog filter with these amplitude characteristics is
nonlinear and can disturb the pulse-shaped characteristic
transients contained in music.
Figure 10 shows the deglitcher controls for both left and
right channels which are produced by timing control
logic. A delay of I.5/lS (teu) is provided to allow the
output of the PCM56P to settle within a small error
band around its final value before connecting it to the
channel output. Due to the fast settling time of the
PCM56P it is possible to minimize the delay between the
left- and right-channel outputs when using a single 0/ A
converter [or both channds. This is important because
the right- and left-channel data are recorded in-phase
and the use of a slower 0/ A converter would result in
significant phase error at higher frequencies.
The obvious solution to the phase shift problem in a
two-channel system would be to use two 0/ A converters
(one per channel) and time the outputs to change
simultaneously. Figure II shows a block diagram of the
final test circuitry used for PCM56P. It should be noted
that no deglitching circuitry is required on the DAC
output to meet specified THO performance. This means
that when one PCM56P is used per channel, the need for
all the sample/hold and controls circuitry associated
with a single DAC (two-channel) design is effectively
diminat~u. The ?Civi56? is tested to meet its 'fHU
specifications without the need for output deglitching.
A low-pass filter is required after the PCM56P to
remove all unwanted frequency components caused by
the sampling frequency as well as those resulting from
the discrete nature of the 0/ A output. This filter must
have a flat frequency response over the entire audio band
(O-20kHz) and a very high attenuation above 20kHz.
Use 400Hz High-Pass
Filter and 30kHz
Distortion Meter
I---
SECOND GENERATION SYSTEMS
One method of avoiding the problems associated with a
higher order analog filter would be to use digital filter
oversampling techniques. Oversampling by a factor of
two would move the sampling frequency (88.2kHz) out
to a point where only a simple low-order phase-linear
analog filter is required after the deglitcher output to
remove unwanted intermodulation products. In a digital
compact disc application, various VLSI chips perform
the functions of error detection/ correction, digital filtering, and formatting of the digital information to provide
the clock, latch enable, and serial input to the PCM56P.
These VLSI chips are available from several sources
(Sony, Yamaha, Signetics, etc.) and are specifically
optimized for digital audio applications.
Oversampled circuitry requires a very fast OJ A converter
since the sampling freuqency is multiplied by a factor of
two or more (for each output channel). A single PCM56P
can provide two-channel oversampling at a 4X rate
(I 76.4kHz/ channel) and still remain well within the
settling time requirements for maintaining specified THO
performance. This would reduce the complexities of the
analog filter even further from that used in 2X oversampling circuitry.
Programmable
Gain Amp
oto 60dB
Low-Pass
I---
Filter
(Toko APQ-25
(Shiba Soku Model
725 or Equivalent)
Binary
Counter
I
I---
Digital Code
(EPROM)
I---
ParallelTo-Serial
-
Conversion
o CmHARACTERISTIC
I
CD -20
DUT
(PCM56P)
~ -60
~ -40
"
-80
-100
I
Clock
I [1
LOW-PASS FILTER
or Equivalent)
Low-Pass Filter
I
Latch Enable
Timing
Sampling Rate ~ 44,1kHz X 4 (176.4kHz)
Output Frequency ~ 991Hz
Logic
FIGURE 11. Block Diagram of Distortion Test Circuit.
189
1 10' 10' 10' 10' 10'
Frequency (Hz)
THIS PAGE INTENTIONALLY LEFT. BLANK
190
BURR-BROWN®
DAC703/883B SERIES
IE:lE:lI
DAC703VG/883B
DAC703VG
DAC703VL/883B
DAC703VL
REVISION NONE
APRIL,1987
Monolithic 16-Bit Military
DIGITAl-TO-ANALOG CONVERTER
FEATURES
FULLY COMPLIANT MIL-STO-883 PROCESSING
• MONOLITHIC CONSTRUCTION
II) HIGH ACCURACY:
linearity Error ±O.003% of FSR inax
Differential linearity Error ±O.006% of FSR max
• MONOTONIC lat 14 bits) OVER FULL MILITARY
TEMPERATURE RANGE
o PIN-COMPATIBLE WITH OAC72 ICOB model).
It OUAL-IN-lINE AND.LCC PACKAGES
CI
DESCRIPTION
This is a complete 16-bit bipolar output (±IOV)
digital-to-analog converter that includes a precision
buried-zener voltage reference and a low-noise, fastsettling output operational amplifier, all on one
small monolithic chip. A combination of currentswitch design techniques accomplishes not only 14bit monotonicity over the military operating temperature range but also a maximum end-point linearity
error of ±0.003% of full-scale range (at +25°C).
Differential linearity at +25°C is 0.006% of FSR.
Digital inputs are complementary binary coded and
are TTL-, LSTTL-, 54f74C- and 54f74HCcompatible over the entire temperature range.
Internalional Airport Industrial Park • P.O. Box 11400
0
Two product assurance levels are available: Standard
and /883B. The Standard product assurance level
offers Hi-Rei manufacturing where many MILSTD-883 screens are performed routinely. The /883B
product assurance level, /883B suffix, offers Hi-Rei
manufacturing, 100% screening per MIL-STD-883
method 5004 and 5% PDA. Quality assurance further
processes /883B devices, by perform·ing group A
and B inspections on each inspection lot and group
C and D inspections as required by MIL-STD-883.
A report containing the most recent group A, B, C,
and D tests is available for a nominal charge.
Tucson. Arizona 85734
0
Tel.: (6021746·1111 • Twx: 910·952·1111 • Cabl.: BBRCORP
PDS-75I
191
0
Telex: 66·6491
DETAILED SPECIFICATION
MICROCIRCUITS, LINEAR
DIGITAL-TO-ANALOG CONVERTER
MONOLITHIC, SILICON
1. SCOPE
l.l Scope. This specification covers the detail requirements for a 16-bit, voltage output, digital-to-analog converter
monolithic microcircuit.
1.2 Part number. The complete part number is as shown below.
DAC703
V
G
/883B
T
l
~
T
Basic Model
Grade
Package
Hi-Rei Product
(see 1.2.3)
Number
(see 1.2.1)
Designator (see 1.2.2)
1.2.1 Device type. The device is a single 16-bit bipolar voltage output digital-to-analog converter. The input coding is
complementary offset binary (COB). There is one electrical performance grade (V grade). This grade features
specifications and testing over the Military temperature range (-55°C to +125°C). Electrical specifications and tests are
shown in Tables I and II.
1.2.2 Device class. The device class is similar to the class B product assurance level as defined in MIL-M-3851O. The
Hi-Rei product designator portion of the part number distinguishes the product assurance levels available as follows:
Hi-Rei product
designator
Requirements
Standard model plus 100% MIL-STD-883B class B screening, with 5% PDA, plus Quality
/883B
Conformance Inspection (QCI) consisting of Groups A and Bperformed on each inspection
lot, plus Groups C and D performed as required by MIL-STD-883.
(none)
Standard model including 100% electrical testing.
1.2.3 Case outline. Two case outlines are available.
1.2.3.1 24-pin ceramic side-brazed (DIP). The "G" package identifier is utilized to specify the 24-pin ceramic side-brazed
package, which is MIL-M-3851O, Appendix C, designator D-3, configuration 3. Figure I depicts the case outline for this
package type.
1.2.3.2 28-terminalleadlesschip carrier (LCC). The "L" package identifier is utilized to specify the 28-terminal square
leadless chip carrier package, which is MIL-M-3851O, Appendix C, designator C-4. Figure I depicts the case outline for
this package type.
1.2.4 Absolute maximum ratings.
Supply voltage, Vee to common
±18VDC
Supply voltage, Voo to common
OVDC to + 18VDC
-IVDC to +7VDC
Digital data input voltage to common
Short circuit duration:
Continuous
Reference output to common
D/ A voltage out to common
Continuous
-5V to +5V
External voltage applied to D / A output
-65°C to +165°C
Storage temperature range
Temperature (soldering lOs)
+300°C
Junction temperature
1.2.5 Recommended operating conditions.
Supply voltage, ±Vcc
±15VDC
Supply voltage, ±Voo
+5VDC
Ambient temperature range
-55°C to +125°C
1.2.6 Power and thermal charactefistics.
Maximum
Case
Maximum allowable
Package
OJ-C
outline
power dissipation
24-lead DIP
Figure I
1000mW
28-terminal LCC
Figure I
1000mW
192
t:;;;;A-
NOTE: Leads In Irue posilion
wilhin 0.0'" (0.25mm) R al MMC
at seating plane.
Pin numbers shown for reference
only. Numbers may not be marked
on package.
~·U
o
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
1.185
1.215
.600
.620
.125
.171
.015
.021
.Q35
.()';IJ
.100 BASIC
.030
.070
.008
.012
.120
.240
.600 BASIC
10'
.025
.060
MILLIMETERS
MIN
MAX
30.10
30.86
15.24
15.75
3.18
4.34
0.53 .
0.38
1.5~
tH!9
2.54 BASIC
0.76
1.78
0.20
0.30
2.06
6.10
15.24 BASIC
10'
0.64
1.52
I
I
DIM
A
B
C
F
G
H
(a) 24-pin side braze; package 10: "G".
1
*-------++-8
:::::::::::
MIN
MAX
.442
.458
.442
.458
.064
.100
.022
.028
.050 BASIC
.OO8R TYP
I ~.::LL:;.:..: en:>
I
MIN
11.23
I
MAX
11.63
11.63
11.23
1.63
2.54
0.56
0.71
1.27 BASIC
O.20RTYP
(b) 28-lerminal LCC; package 10: "L"
FIGURE
1.
Case Outlines.
2. APPLICABLE DOCUMENTS
2.1 Government specification and standard. Unless otherwise specified, the following specifications and standards
form a part of this specification to the extent specified herein.
SPECIFICATION
MILITARY
MIL-M-38SI0-Microcircuits, general specification for.
STANDARD
MILITARY
MIL-STD-883-Test metho.ds and procedures for microcircuits.
2.2 Order of precedence. In the event of a conflict between the text of this specification and the references cited herein,
the text of this specification shall take precedence.
3. REQUIREMENTS
3.1 General. Burr-Brown used production and test facilities and a quality and reliability assurance program adequate
to assure successful compliance with this specification.
3.1.1 Detail specifications. The individual item requirements are specified herein. In the event of conflicting
requirements, the order of precedence wiH be the purchase order, this specification, and then the reference documents.
3.2 Design, construction, and physical dimensions.
3.2.1 Package, metals, and other materials. The packages, metal surfaces, and other materials are in accordance with
MIL-M-38SI0.
3.2.2 Design documentation. The design documentation is in accordance with MIL-M-38SI0.
3.2.3 Internal conductors and internal wires. The internal conductors and internal lead wires are in accordance with
MIL-M-38SI0.
,
3.2.4 Lead material and finish. The lead material and finish is in aC,cordance with MIL-M-38SI0 and is solderable per
MIL-STD-883, method 2003.
193
3.2.5 Die thickness. The die thickness is in accordance with MIL-M-38510.
3.2.6 Physical dimensions. The physical dimensions are in accordance with paragraph 1.2.3 herein and are shown in
Figure 1.
"
3.2.7 Circuit diagram and terminal connections. The circuit diagram and terminal connections are shown in Figures 2
and 3.
3.2.8 Glassivation. The microcircuit dice are glassivated.
3.3 Electrical performance characteristics. The electrical performance characteristics are specified in Table I and apply
over the full operating ambient temperature range of -55°C to +125°C unless otherwise specified.
3.4 Electrical test requirements. Electrical test requirements are shown in Table II. The subgroups of Table I, which
constitute the mmimum electrical test requirements for screening, qualification, and quality conformance inspection,
are specified in Table II.
PIN#
+Vee
} -_ _=,.,....,:-:!::'-_2'\j70/\jk~O_~131
'-_..-_L--- Voo'''
+.121
NOTES:
1. Can be tied to +Vee Instead of
having separate Vo~ supply.
2. Decoupling capacitors are O.lpF
tol.0pF.
3. Potentiometers are 10kO to 100kO.
"G"PACKAGE
Bit 1 (MSB)
Bit2
Bit3
Bit 4
Bit5
Bit6
Bit7
BI18
Blt9
Blt12
Bllll
Bit12
Bit 13
Bit 14
Bit 15
Bit 16 (lSB)
VOUT
Voo
-Vee
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22"
23
24
Common
Summing Junction (Zero Adjust)
Gain AdJust
+Vee
+6.3V Reference Output
FIGURE 2. "G" Package Circuit Diagram and Terminal Connections.
+Vcc
'21
PIN#
+Ij-.....- " ' f ' - - -Vee
1
2
3
"I~
4
5
6
7
8
I------.~ '21
9
I------.....---.~
+-f"1
1-------......--
VOD I31
+,*,"1
Digital
Inputs
Digital
Inputs
NOTES:
1. Decoupllng capacitors are O.lpF
tol.0pF
2. Potentiometers are 10kO to 100kO.
3. Can be tied to +Vee instead of
having separate Voo supply.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
"l"PACKAGE
No connection
Bitl (",SB)
Bit2
Bit3
Bit4
Bit 5
Bit6
No connection
Blt7
Bit8
Bit 9
Bitl0
Bitll
Bit12
No connection
Bit13
Bit14
Bit15
Bit16 (lSB)
VOUT
Voo
No connection
-Vee
Common
Summing Junction
Gain Adjust
+Vee
+6.3V Reference Output
FIGURE 3. "L" Package Circuit Diagram and Terminal Connections.
'194
TABLE 1. Electrical Performance Characteristics.
(T. = -55'C to +125'C. Supply Voltages: ±Vee = ±15VDC. VDD= +5VDC)
CONDITIONS
CHARACTERISTICS
GROUP A
SUBGROUPS
DAC703 "V" GRADE
MIN
TYP
MAX
UNITS
16
Bits
INPUT
DIGITAL INPUT
Resolution J}
Digital Inputs 2/
V'H
VIL
I'H
III
V, = +2.7V
V, =+0.4V
1
1
1
1
+2.4
-1.0
+Vee
+0.8
+40
-0.5
V
V
pA
mA
1
2.3
1
2,3
1
1
1,2,3
-0.003
-0.006
-0.006
-0.006
-0.1
-0.1
14
+0.003
+0.006
+0.006
+0.009
+0.1
+0.1
%01 FSRaJ
%oIFSR
%01 FSR
%oIFSR
%oIFSR
%oIFSR
Bits
2,3
2,3
-20
-15
-0.1
+20
+15
+0.1
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error
T.= +25'C
-55'C ::; T. ::; +125'C
T.= +25'C
-55'C ::; T.::; +125'C
T.=+25'C
T.=+25'C
Differential Linearity Error
Gain Errorgj
Zero Errorgj
Monotoniclty over Temp. Range J}
DRIFT
Gain Drift
Zero Drllt
Total Error over Temperature
ppm/'C
~pml'C
%oIFSR
DYNAMIC CHARACTERISTICS
Settling Time
to ±0.003%, RL = 2kCl
Full-Scale Output Step
R,=2kCl
Slew Rate
9
OUTPUT
Output Voltage
Output Current
Output Impedance
4
9
10
1
±5
1,2,3
+6.0
1,2,3
-15
ps
8
VlJ.IS
±10
V
mA
Cl
0.15
Relerence Voltage
Source Current
Temperature Coefficient
For external loads
+6.3
+2.5
V
mA
ppm/'C
+6.6
+15
POWER SUPPLY REQUIREMENTS
Suply Voltage. +Vee
-Vee
VDD
Supply Currents, -Icc
+13.5
-13.5
+4.5
1
1
1
1
1
1
-Icc
100
Power Supply Rejection
+15
-15
+5
Delta +Vee = ±1V T. = 25'C
Delta -Vee = ±1V T. = 25'C
Delta VDD = ±1V T. = 25'C
V
V
V
mAo
mA
mA
mVN
mVN'
mVN
+16.5
-16.5
+16.5
+30
-30
+8
4
4
4
NOTES:
J} 1LSB = 0.305mV.
2/ Digital Inputs are TTL-, LSTTL-, 54174C-, 54174HC-, and 54/74HTC-compatlble over the operating voltage range 01 VDD = +5V to +15V and over the
operating temperature range. The input switching threshold remains at the TTL threshold 01 1.4Voverthe supply range 01 VDD = +5V to +15V. As logic
"0" and "1" Inputs vary over OV to +0.8V and +2.4Vto +10V respectively, the change In the D/A converter output voltage will not exceed ±0.003% 01 FSR.
aJ FSR = lull-scale range =.20V.
gj Adjustable to zero.
TABLE II. Electrical Test Requirements.
(The individual tests within the subgroups appear in Table I)
MODELS
MIL-STD-883 TEST REQUIREMENTS
DAC703VG/883B
DAC703VL/883B
DAC703GL
DAC703VL
Subgroups (see table I)
Interim electrical parameters (preburn-in) (method 5005)
Flna! electrical test parameters (method 5005)
Group A test requirements (method 5005)
Group C and 0 end point electrical parameters (method 5005)'
Additional electrical subgroups performed in addition to Group C inspection
·*PDA applies to subgroup I. "Performed to an LTPD of 5.
195
1
1
1',2,3
1.2,3
1,2,3
N/A
1 and Table III
N/A
9"
N/A
TABLE III. Additional End-Point Limits (after 1000Hr Life Test).
PARAMETER
LIMIT
Gain Error
Linearity Error
Differential Linearity Error
±O.2% of FSR'
±SLSB"
±8LSB
. 'FSR = full-scale range.
··ILSB = O.30SmV
3.5 Marking. Marking is in accordance with MIL-M-38510. The following marking is placed on each microcircuit as a
minimum:
a. Part number (see paragraph 1.2)
b. Inspection lot identification code 11
c. Manufacturer's identification (
d. Manufacturer's designating symbol (CEBS)
e. Country of origin
f. Electrostatic sensitivity identifier(~}
3.6 Workmanship. These microcircuits are manufactured, processed, and tested in a workmanlike manner. Workmanship is in accordance with good engineering practices, workmanlike instructions, inspection and test procedures and
training, prepared in fulfillment of Burr-Brown's product assurance program.
3.6.1 Rework provisions. Rework provisions, including rebonding for the ",883B" product designation, are in
.
.accordance with MIL-M-38510.
.
3.7 Traceability. Traceability for the ",883B" product designation is in accordance with MIL-M-3851O. Each
microcircuit is traceable to the production lot and to the component vendor's component lot.
3.8 Product and process change. Burr-Brown will not implement any major change to the design, materials,
construction, or manufacturing process which may .affect the performance, quality or interchangeability of the
microcircuit without full or partial requalification.
3..9 Screening. Screening for the ",833B" Hi-Rei product designation is in accordance with MIL-STD-883B, method
5004, class B, and as specified herein.
Screening for the standard model includes Burr-Brown QC4118 internal visual inspection, stabilization bake, fine leak,
gross leak, constant acceleration (condition A), temperature cycle (condition C), and external visual per MIL-STD883B method 2009.
For the ",883B" product designation, all microcircuits will have l!assed the screening requirements prior to
qualification or quality conformance inspection.
3.10 Qualification. Qualification is not required. See paragraph 4.2 herein.
3.11 Quality conformance inspection. Quality conformance inspection (QCI), for the ",883B" product designation, is
in accordance with MIL-STD-883, and as specified in paragraph 4.4 herein. The microcircuit inpsection lot will have
passed quality conformance inspection prior to microcircuit delivery.
r..LIfi" )
4. PRODUCT ASSURANCE PROVISIONS
4.1 Sampling and inspection. Sampling and inspection procedures are in accordance with MIL-M-38510 and MILSTD-883, method 5005.
4.2 Qualification. Qualification is not required unless specifically required by contract or purchase order. When so
required, qualification will be in accordance with the inspection routine of MIL-M-3851O. The inspections to be
performed are those specified herein for Groups A, B, C, and D inspections (see paragraphs 4.4.1, 4.4.2, 4.4.3, and 4.4.4
herein.).
4.3 Screening. Screening for the ",883B" Hi-Rei product designation is in accordance with MIL-STD-883, method
5004, class B, and is conducted on all devices. The following criteria apply:
a. Interim and final test parameters are specified in Table II.
b. Burn-in test (MIL-STD-883, method 1015) conditions:
(l) Test condition B.
(2) Test circuit is Figure 4.
(3) TA = +125°C.
(4) Test duration is 160 hours minimum.
y A 4-digit code, indicating year' and week of seal, and a 4- or 5-digit lot identifier are marked on each unit.
196
c. Percent defective allowable (PDA). The PDA, for "/883B" product designation only, is five percent and
includes both parametric and catastrophic failures from Group A, Subgroub I test, after cool-down as final
electrical test in accordance with MIL-STD-883, method 5005, and with no intervening electrical
measurements. If interim electrical parameter tests are performed prior to burn-in, failures resulting from
preburn-in screening failures may be excluded from the PDA. If interim electrical parameter tests are
omitted, all screening failures shall be included in the PDA. The verified failures of Group A, Subgroup I,
after burn-in are used to determine the Percent Defective for each manufacturing lot, and the lot is accepted
or rejected based on PDA.
d. External visual inspection need not include measurement of case and lead dimensions.
4.4 Quality conformance inspection. Groups A and B inspections of MIL-STD-883, method 5005, class B, are
performed on each inspection lot. Groups C and D inspections of MIL-STD-883, method 5005, class B are performed
as required by MIL-STD-883.
A report of the most recent Group C and D inspections is available from Burr-Brown.
4.4.1 Group A inspection. Group A inspection consists of the test subgroups and LTPD values shown in MIL-STD883, method 5005, and as specified in Table II herein.
4.4.2 Group B inspection. Group B inspection consists of the test subgroups and LTPD values shown in MIL-STD883, method 5005, class B.
4.4.3 Group C inspection. Group C inspection consists of the subgroups and LTPD values shown in MIL-STD-883,
method 5005, class B, and as follows:
a. Operating life test (MIL-STD-883, method 1005) conditions:
(I) Test condition B.
(2) Test circuit is Figure 4.
(3) TA = +125°C minimum.
(4) Test duration is 1000 hours minimum.
b. End point electrical parameters are specified in Table II herein.
4.4.4 Group D inspection. Group D inspection consists of the test subgroups and LTPD values shown in MIL-STD883, method 5005. End point electrical parameters are specified in Table II herein.
4.4.5 Inspection of packaging. Inspection of packaging shall be in accordance with MIL-M-3851O.
4.5 Methods of examination and test. Methods of examination and test are specified in the appropriate tables.
Electrical test circuits are as prescribed herein or in the referenced test methods of MIL-STD-883.
4.5.1 Voltage and current. All voltage values given, except the input offset voltage (or differential Voltage) are
referenced to the external zero reference level of the supply voltage. Currents given are conventional current and
positive when flowing into the referenced terminal.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-M-3851O.
1kQ
1kQ
Cbl 28·Terminal LCC "L" Package
Cal 24·Pln Side-Brazed "Goo Package
FIGURE 4. Test Circuit for Burn-In and Operating Life Test.
197
6. NOTES
6.1 Notes. The notes specified in MIL-M-38510 are applicable to this specification.
6.2 Intended use. Microcircuits conforming to this specification are intended for use in applications where the, use qf
screened parts is required or desirable.
6.3 Ordering Data. The contract or purchase order should specify the following:
a. Complete part number (see paragraph 1.2).
b. Requirement for certificate of compliance, if desired.
6.4 Microcircuit group assignment. These microcircuits are assigned to technology group D with a microcircuit group
number of 56 as defined in MIL-M-38510, Appendix E.
6.5 Electrostatic sensitivity. Caution-these microcircuits may be damaged by electrostatic discharge. Precautions
should be observed at all times.
6.6 Definitions.
6.6.1 Linearity. This specification describes one of the most important measures of performance of a D/ A converter.
Linearity error is the deviation of the analog output from a straight line drawn through the end points (all bits ON point .
and all bits OFF point).
6.6.2 Differential linearity error. Differential linearity error (DLE) of a D/ A converter is the deviation from its ideal
lLSB change in the output from one adjacent output statj: to the next. A differential linearity error specification of
±1/2LSB means that the output step sizes can be between 1/2LSB and 3/2LSB when the input changes from one
adjacent input state to the next. A negative DLE specification of no more than -ILSB (-O.OO6%FSR for 14-bit
resolution) insures monotonicity.
6.6.3 Monotonicity. Monotonicity assures that the analog output will increase or remain the same for increasing input
digital codes. The DAC703 is specified to be monotonic to 14 bits over the entire specification temperature range.
6.6.4 Gain error. Gain error is the difference between the ideal full-scale output and the actual output of the D/ A
converter. For the DAC703 this is at OOOOH and FFFFH.
6.6.5 Zero error. Zero error is the difference between zero volts and the actual D/A converter output at the zero
output code (7FFFH).
7. APPLICATION INFORMATION.
7.1 Power supply decoupling. For optimum performance and noise rejection, each power supply should be decoupled
by connecting a I/oiF tantalum- or electrolytic capacitors, is used, should be parralleled with O.OI/olF ceramic capacitors
for best high-frequency performance.
.
7.2 Power-supply sensitivity. Power-supply sensitivity is specified in Table 1. Power-supply sensitivity versus ripple
frequency is shown in Figure 5.
7.3 External zero and gain error adjustment. The untrimmed accuracy of the DAC can be adjusted using the circuitry
'
shown in Figures 2 and 3.
7.3.1 Zero adjustment. Apply the digital input code 7FFFH, which should produce zero volts output. Adjust the offset
"
potentiometer until the output is zero volts.
7.3.2 Gain adjustment. Apply the digital input code OOOOH, which should produce 9.99969 volts output. Adjust the
gain potentiometer to produce 9.99969 volts.
7.4 Further information. Further application information can be found in Burr-Brown's commercial data sheet for the
DAC700f702, DAC701f703.
198
0.030
E 0.025
;;
-15V Supply
.5
"g>
0.020
"
.r::;
(J
'0
#. 0,015
l;
a.
g
w 0.010
a:
IL
Ul
u.
'0
#. 0.005
+15V
~PPI
~5V
~~
0
1
10
100
lk
10k
lOOk
Power Supply Ripple Frequency (Hz)
FIGURE 5. Power Supply Rejection Versus Power Supply Ripple Fre4,uency.
199
BURR-.BROWN®
IElElI
INA101/8838 SERIES
INA101VM/883B
INA101VM
INA101VG/883B
INA101VG
REVISION NONE
APRIL,1987
Very High Accuracy Military
INSTRUMENTATION AMPLIFIER
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
• AMPLIFICATION OF SIGNALS FROM SOURCES
SUCH AS:
Strain Gauges
Thermocouples
RTDs
• REMOTE TRAN$DUCERS
• LOW LEVEL SIGNALS
FULLY COMPLIANT MIL-STD-883 PROCESSING
ULTRA-LOW VOLTAGE DRIFT: 1.75pV/oC (A = 1000)
LOW OFFSET VOLTAGE: 50pV
LOW NONLINEARITY: 0.005%
LOW NOISE: 13nV/JIiZ at fa = 1kHz
HIGHCMR: 106d8 at 60Hz
HIGH INPUT If!1PEDANCE: 101°n
DESCRIPTION
The INAIOI is a high-accuracy, multistage, militarygrade, integrated-circuit instrumentation amplifier
designed for signal conditioning requirements where
very high performance is desired. All circuits, including the interconnected laser-trimmed thin-film resistors, are integrated on a single monolithic substrate.
A multiamplifier design is used to provide the
highest performance and maximum versatility with
monolithic construction for low cost. The input
stage uses Burr-Brown's· ultra-low drift, low-lioise
technology to provide exceptional input characteristics.
Two product assurance levels are available: Standard
and /883B. The Standard product assurance level
offers Hi-Rei manufacturing where many MILSTD-883 screens are performed routinely. The /883B
product assurace level, /883B suffix, offers Hi-Rei
manufacturing, 100% screening per MIL-STD-883
method 5004 and 5% PDA. Quality assura!lce further
processes /883 devices, by performing lot and group
C and D inspections as required by. MIL-STD-883.
A report containing the most recent group A, B, C,
and D tests is available for a nominal charge.
International Airport Industrial Park • P.O. Box 114011 • Tucaon. Arizona 85134 • Tel.: (1102) 146-1111 • Twx: 910-952·1111 • Cable: BBRCORP • Talax: 116-8491
PDS-752
200
DETAILED SPECIFICATION
MICROCIRCUITS, LINEAR
INSTRUMENTATION AMPLIFIER
MONOLITHIC, SILICON
I. SCOPE
l.l Scope. This specification covers the detail requirements for a very high accuracy instrumentation amplifier. For
description of operation see paragraph 8.
1.2 Part Number. The complete part number is as shown below.
INAIOI
V
I
Basic model
number
l
M
l
Grade
Package
Hi-ReI product
designator
designator
designator
(see 1.2.1)
(see 1.2.2)
(see 1.2.3)
1.2.1 Device type. The device is a single instrumentation amplifier. One electrical performance grade ("V") is provided.
The "V" grade offers specifications and operation over the Military temperature range (-55°C to +125°C). Electrical
performance characteristics are shown in Table I, and Electrical tests are shown in Tables II and III.
1.2.2 Device class. The device class is similar to the product assurance level B, as defined in MIL-M-3851O. The Hi-ReI
product designator portion of the part number distinguishes the product assurance level as follows:
Hi-ReI product
des~g!!~!,?!...
Requirements
Standard model,. plus 100% MIL-STD-883 class B screening, with 5% PDA, plus
/883B
quality conformance inspection (QCI) consisting of Groups A and B performed on
each inspection lot, plus Groups C and D perfotmed initially and annually thereafter.
(none)
Standard model including 100% electrical testing.
1.2.3 Case outline. Two package options are available ("G" and "M').
a. The "G" package is a 14-terminal ceramic side braze DIP and is case outline D-I, configuration 3, as defined in
MIL-M-3851O, Appendix C (see Figure la).
b. The "M" package is a IO-Iead can, TO-100, and is case outline D-I as defined in MIL-M-38510, Appendix C
(see Figure Ib).
1.2.4 Absolute maximum ratings.
Positive supply voltage (+Vee)
Oto +20VDC
Oto -20VDC
Negative supply voltage (,,-Vec)
Duration output short circuit to ground
Continuous
Lead temperature (soldering, lOs)
+300°C
Junction temperature
+175°C·
-65°C to +150°C
Storage temperature range
1.2.5 Recommended operating conditions.
Positive supply voltage (+Vee)
+HVDC to +20VDC
-HVDC to -20VDC
Negative supply voltage (-Vee)
-55°C to +125°C
Ambient temperature range
1.2.6 Power and thermal characteristics.
Package
Case outline
Maximum allowable power dissipation
Maximum/he
IO-Iead TO-100
Figure I
600mW
60°CfW
14-lead DIP
Figure I
600mW
50°CfW
2. APPLICABLE DOCUMENTS
2.1 The following form a part of this specification to the extent specified herein.
SPECIFICATION
MILITARY
MIL-M-3851O-Microcircuits, general specification for.
STANDARD
MILITARY
MIL-STD-883-Test methods and procedures for microcircuits.
201
TABLE 1. Electrical Performance Characteristics.
All characteristics at -SS'C:;; TA:;; +12S'C. ±Vcc = lSVDC. unless otherwise specified.
INA101VM/883B
INA101VM
INA101VG/883B
INA101VG
CHARACTERISTICS
GAIN
Range of Gain
Gain Equation Error
Gain TempcQ Y
\
Av
EAV
I!.Avll!.T
DC Nonlinearity
NL
RATED OUTPUT
Voltage
Current
Impedance
V.P
I.
Z.
INPUT OFFSET VOLTAGE
Initial 3/
vs Temperature
vs Supply
CONDITIONS
SYMBOL
VI.
VI.
I!.VloIl!.T
PSRR
Av = 1 + (40k/Ro) li
Av = 1. TA = +2S'C
Av = 10. T. = +2S'C
Av = 100. T. = +2S'C
Av = 1000. T. = +2S'C
INPUT OFFSET CURRENT
Initial
TempeD
II.
I!.IIoIl!.T
TA:::: +25°C
ZID
TA = +25°C
TA = +25 11 C
INPUT VOLTAGE
Linear Response Range
Rejection
VIN
CMR
INPUT NOISE
Input Voltage Noise
ENPP
EN
Input Current Noise
INPp
IN
DYNAMIC RESPONSE
Slew Rate
Bandwidth
SR
BW
Settling Time
BW
T.
POWER SUPPLY
Rated Voltage
Quiescent Current
±Vcc
10
1000
' O.OS
0.10
0.10
0.40
VN
%FS
%FS
%FS
% FS
ppm/'C
ppm/'C
ppm/'C
ppm/'C
%
%
%
%
O.OOS
O,OOS
0.007
0.025
V
mA
n
±10
±S
Av = 10. TA = +2S'C
Av = 1000. TA = +2S'C
Av = 10, -55°C::;; TAo:::;; +125°C
Av = 1000, -55°C S T" S +125 11 C
Av = 1, I!.Vcc = ±SVDC, T. = +2S'C
Av = 1000, I!.Vcc = ±SVDC, T. = +2S'C
TAo
Common~Mode
UNITS
0,2
lIB
1!.11a/I!.T
ZtCM
MAX
2
20
22
22
Av=l
R, = 2kn. TA = +2S'C
TYP
1
Av=10
Av = 100
Av = 1000
Av = 1, TAo = +25°C
Av = 10, TAo = +251;1C
Av = 100. T. = +2S'C
Av = 1000. TA = +2S'C
INPUT BIAS CURRENT
Initial
,TempeD
INPUT IMPEDANCE
Differential
Co 'TImon Mode
MIN
±7S
±SO
±2.S
±1,75
3S
2
"V
"V
"VI'C
pV/'C
"VN
"VIV
±30
nA
nAl°e-
±30
±O,S
nA
nAl'C
101°113
10"113
nil pF
nil pF
= +25°C
±0,2
\ DC-60Hz, Av = lkQ Source Imbalance
TA= +25°C
DC-60Hz, Av = 10, lkn Source Imbalance
TAo = +25°C
DC-60Hz, Av = 100-1000,
lkO Source Imbalance. TAo = +25°C
±10
V
80
dB
96
dB
106
dB
0,8
18
',S
13
50
0,8
0,46
0,3S
fa = 0,01 to 10Hz, TA = +2S'C
Av = 1000, fa = 10Hz. TA = +2S'C
Av = 1000, fa = 100Hz, TA = +25°C
Av = 1000, fa = 1kHz. TA = +2S'C
fa = 0.01 Hz to 10Hz, TA = +2S'C
fa = 10Hz, TA = +2S'C
fa = 100Hz, T. = +2S'C
fa = 1kHz. T. = +2S'C
Av = 1 to 100, R, = 2kn, T. = +2S'C
3dB small signal, Av = 1, T" = +25°C
Av = 10, TA = +2S'C
Av = 100, T. = +2S'C
Av = 1000, T. = +2S'C
Full power Av = , to 1000, T. = +2S'C
0,01%, Av = 1, TA = +2S'C
Av = 100, T. = +2S'C
Av = 1000, TA = +25'C
0.2
NOTES,
jj Typically the tolerance of RG will be the major source of gain error.
Not including TCR of Ro,
3/ Adjustable to zero at anyone gain.
Y
202
VI"s
kHz
kHz
kHz
kHz
kHz
ps
300
140
25
2.S
SA
30
SO
SOO
±S
T. =+2S'C
"V. p-p
nVNHz
nV/v'Hz
nV/v'Hz
pA, p-p
pAlv'Hz
pAlv'Hz
pAlv'Hz·
±lS
"s
"s
±20
±8,S
V
mA
TABLE II. Electrical Test Requirements.
(The individual tests within the subgroups appear in Table III)
INAt01VM/883B
INA101VG/883B
MIL·STD-883 REQUIREMENTS (Class B)
Interim electrical parameters (preburn-in) (method 5004)
Final electrical test parameters (method 5004)"
Group A test requirements (method 5005)
Group C and 0 end point electrical parameters (method 5005)
INAt01VM
INA101VG
1
1'.2.3.4
1.2.3.4
1
1.2.3.4
-
'PDA applies to subgroup 1 (see 4.3.c).
TABLE III. Group A Inspection.
LIMITS
SUBGROUP
SYMBOL
MIL-STD-883
METHOD OR
EQUIVALENT
1
V,O
4001
TA
1,0
2
T. = 125'C
3
T. = -55'C
UNITS
pV
pV
4001
4001
±75
±50
±20
±20
~CC!j
..J...U.W
111M
±35
±2
pVN
pVN
PSRR
'"
4003
CMR
4003
!;V,ol!;T
4001
!;V,ol!;T
4
T. = 25'C
unless otherwise specified)
MAX
= 25°C
It.
CONDITIONS
(±Vee = 15VOC
INA101VM/883B
INA101VM
INA101VG/883B
INA101VG
4001
Av = 1. !;Vee = ±5VDC
Av = 1000, !;Vee = ±5VDC
DC, Av = 1. lkO Source Imbalance
DC, Av = 10.lkO Source Imbalance
DC. Av = 100-1000. lkO Source Imbalance
Av=10
[V,O (25'C) - V,O (-55'C)] .;. 80
Av = 1000
. [V,O (25'C) - V,O (-55'C)] .;. 80
=1
Av= 10
Av = 100
Av = 1000
VOP
4004
SR
NL 1/
Figure 4
R, = 2kO
R,;=2kO
Av=l
Av= 10
Av = 100
Av = 1000
dB
dB
dB
±2.5
pVl'C
±1.75
pVI;C
±25
pVl'C
±1.75
pVI'C
0.05
0.10
0.10
0.40
%FS
%FS
%FS
%FS
V
Vips
±10
0.2
0.005
0.005
0.007
0.025
NOTES:
11 E, = OV and E2 is varied to enable nonlinearity error to be measured by sampling 21 pOints between -10V:5
and
de~ermining
nA
nA
80
96
106
Av= 10'
lV,o (125'C) - V,O (25'Cll .;. 100
Av = 1000
[V,O (125'C) - V,O (25'C)] .;. 100
Gain Equation Error: Av
E.v
MIN
Av = 10
Av = 1000
worst CBse deviation from straight line connecting these end pOints at each gain setting.
203
%
%
%
%
EOUT
:5
+ 10V'
NOTE: Leads in true position
wilhin 0.01" (0.25mm) R al MMC
at seating plane.
.
Pin numbers shown for reference
only. Numbers may not be marked
on package.
DIM
A
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
.670
.710
.065
.170
.015
.021
.045
.060
.100 BASIC
.025
.070
.012
.008
.120
.240
.300 BASIC
10'
.009
.060
MILLIMETERS
MIN
MAX
18.03
17.02
1.65
4.32
0.53
0.38
1,14
1.52
2.54 BASIC
0.64
1.78
0.20
0.30
3.05
6.10
7.62 BASIC
10'
0.23
1.52
(a) 14-Pln Ceramic Side Braze-Package 10: "G"
NOTE:
L~ads in t~ue position
wilhin 0.01" (0.25mm) R al MMC
at seating plane.
Pin numbers shown for reference
only. Numbers may not be marked
on package.
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
'.335
.370
.305
.335
.165
.185
.016
.021
.010
.040
.010
.040
.230 BASIC
.028
.034
.029
.045
.500
.120
.160
36' BASIC
.110
.120
MILLIMETERS
MIN
MAX
8.51
9.40
7.75
8.51
4.19
4.70
0.41
0.53
0.25
1.02
0.25
1.02
5.84 BASIC
0.71
0.86
0.74
1.14
12.70
3.05
4.06
36° BASIC
2.79
3.05
Bottom View
(b) TO-l00 Melal Can-Package 10: "M"
FIGURE 1. Case Outlines.
3. REQUIREMENTS
3.1 General. Burr-Brown uses production and test facilities and a quality and reliability assurance program adequate
to assure successful compliance with this specification.
3.1.1 Detail specifications. The individual item requirements are specified herein. In the event of conflicti~g
requirements, the order of precedence will be the purchase order, this specification, and then the reference documents.
3.2 Design, construction and physical dimensions.
3.2.1 Package, metals, and other materials. The package, metal surfaces, and other materials are in accordance with
MIL-M-3851O.
3.2.2 Design documentation. The design documentation is in accordance with MIL-M-38510.
3.2.3. Internal conductors and internal lead wires. The internal conductors and internal lead wires are in accordance
with MIL-M-38510.
3.2.4. Lead material and finish. The lead material and finish (gold plate) are in accordance with MIL-M-38510 and is
solderable per MIL-STD-883, method 2003.
3.2.5 Die thickness. The die thickness is in accordance with MIL-M-3851O.
3.2.6 Physical dimensions. The physical dimensions are in accordance with paragraph 1.2.3 herein.
3.2.7 Circuit diagram and terminal connections. The circuit diagram and terminal connections are shown in Figure 2.
204
Offset Adjust
a
6 7
A, Output
1kn
-Input
3
Gain Sense 1
4
Gain Set1
5
1kn
10kn
20kn
10kn
20kn
10kn
Output
1
Gain S.t2 10
1kn
Gain Sense 2 11
1kn
10kn
+ Input 12
2
+Vcc
14 Common
9
13
-Vee
A, Output
(a) "G" Package
Offset Adjust
2 3
-Input 10
10kn
10kn
Gain Set 1
Output
20kn
a
10kn
Gain Set 2 4
10kn
+Input 5
Common
(b) "M" Package
FIGURE 2. Circuit Diagram and Terminal Connections.
3.2.8 Glassivation. The microcircuit die is glassivated.
3.3 Electrical performance characteristics. The electrical performance characteristics are specified in Table I and apply
over the full operating ambient temperature range of -55°C to +125°C unless otherwise specified.
3.4 Electrical test reguirements. Electrical test requirements are shown in Table II. The subgroups of Table III which
constitute the minimum electrical test requirements for screening, qualification, and quality conformance, are specified
in Table II.
205
3.5 Marking is in accordance with MIL-M-38SI0. The following marking is placed on each microcircuit as a minimum:
a. Part number (see paragraph 1.2)
b. Inspection lot identification code II
c. Manufacturer's identification ( r&i;j® )
d. Manufacturer's designating symbol (CEBS)
e. Country of origin
f. Electrostatic sensitivity identifier(t.)
3.6 Workmanship. These microcircuits are manufactured, processed, and tested in a workmanlike manner. Workmanship is in accordance with good engineering practices, workmanlike instructions, inspection and test procedures,
and training prepared in fulfillment of Burr-Brown's product assurance program.
3.6.1. Rework provisions. Rework provisions, including rebonding for the "/883B" Hi-ReI product designation are in
accordance with MIL-M-38SIO.
3.7 Traceability. Traceability for the "/883B" Hi-ReI product designation is in accordance with MIL-M-38SIO. Each
microcircuit is traceable to the production lot and to the component vendor's component lot.
3.8 Product and process change. Burr-Brown will not implement any major change to the. design, materials,
construction, or manufacturing process which may affect the performance, quality, or interchangeability,of the
microcircuit without full or partial requalificati0!l.
3.9 Screening.
a. Screening for the "/883B" Hi-ReI product designation is in accordance with MIL-STD-883, method 5004,
class B, except as modified in paragraph 4.3 herein. All microcircuits will have passed the screening
requirements prior to qualification or quality conformance inspection. '
b. Screening for the standard model (no Hi-ReI product designation) includes Burr-Brown QC4118 internal
visual inspection, stabilization bake, fine leak, gross leak, constant acceleration (condition E), temperature
cycle (condition C), and external visual per MIL-STD-883, method 2009.
3.10 Qualification. Qualification is not required. See paragraph 4.~ herein.
3.11 Quality conformance inspection. Quality conformance inspection, for the "/883Bn Hi-Rel product designation is
in accordance with MIL-STD-883 and MIL-M-38SIO, except as modified in paragraph 4.4 herein. The microcircuit
inspection lot will have passed quality conformanc~ inspection prior to microcircuit delivery.
4. PRODUCT ASSURANCE PROVISIONS
4.1 Sampling and inspection. Sampling and inspection procedures are in accordance with MIL-M-38510and MILSTD-883, method SOOS, except as modified herein.
4.2 Qualification. Qualification is not required unless specifically required by contract or purchase order. When so
required, qualification will be in accordance with the inspection routine of MIL-M-3851O, paragraph 4.4.2.1. The
inspections to be performed are those specified herein for Groups A, B, C, and D inspections (see paragraphs 4.4.1,
4.4.2, 4.4.3, and 4:4.4). Burr-Brown has performed and successfully completed qualification inspection as described
above. The most recent report is available from Burr-Brown.
4.3 Screening. .screening for the ~'/883B" Hi-ReI product designation is in accordance with MIL-STD-883, method
S004, class B, and is conducted on all deviCes. The following criteria apply:
a. Interim and final test parameters are specified in Table II.
b. Burn-lit test (MIL-STD-883, method lOIS) conditions:
(I) Test condition B.
(2) Test circuit is shown in Figure 3.
(3)TA = +125°C minimum.
(4). Test duration 160 hours minimum.
c. Percent defective allowable (PDA). The PDA, for the "/883B" Hi-ReI product designation only, is·5% based
on failures from Group A, subgroup I test after cool-down as final electrical in accordance with MIL-STD883, method 5004, and with no intervening electrical measurements. If interim electrical parameter tests
performed prior to burn-in are omitted, a1l screening failures shall be included in the PDA calculation. The
verified failures of group A, subgroup 1 after burn-in for each manufacturing lot are used to determine the
percent defective for that lot. Each lot is accepted or rejected based on the PDA.
d. External visual inspection does not include measurement of case and lead dimensions.
1/A 4-digit code, indicating year and week of seal, and a 4- or S.cIigit lot identifier are marked on each unit.
206
2kCl
2kCl
(a)
(b)
"G" Package
"M" Package
FIGURE 3. Test Circuit-Bum-In and Operating Life Test.
4.4 Quality conformance inspection. Groups A and B inspection of MIL-STD-883, method 5005, class B, are
performed on each inspection lot. Group C and D inspections of MIL-STD-883, method 5005, class B are performed as
required by MIL-STD-883. A report of the most recent group C and D inspections is available from Burr-Brown.
4.4.1 Group A inspection. Group A inspection consists of the test subgroups and LTPD values shown in MIL-STD883, method 5005, and as specified in Table II herein.
4.4.2 Group I! insp\;ctioiJ.. Gi"uup D inspcctiuii C0iiSists of tlie test SUtgi0UpS a.uu. LTeD viLluc;s ~llUW1J lu iv1iL-STD883, method 5005, class B.
4.4.3 Group C inspection. Group C inspection consists of the test subgroups and LTPD values shown in MIL-STD883, method 5005, and as follows:
a. Operating life test (MIL-STD-883, method 1005) conditions:
(I) Test condition B.
(2) Test circuit is shown in Figure 3.
(3) TA = +125°C minimum.
(4) Test duration is 1000 hours minimum.
,b. End point electrical parameters are specified in Table II.
4.4.4 Group D. Group D inspection consists of the test subgroups and LTPD values shown in MIL-STD-883, method
5005, end point electrical parameters.
4.4.5 Inspection of packaging. Inspection of packaging shall be in accordance with MIL-M-3851O.
4.5 Methods of examination and test. Methods of examination and test are specified in the appropriate tables.
Electrical test circuits are as prescribed herein or in the referenced test methods of MIL-STD-883.
4.5.1 Voltage and current. All voltage values given are referenced to the external zero reference level of the supply
voltage. Currents given are conventional current and positive when flowing into the referenced terminal.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-M-3851O.
6. NOTES
6.1 Notes. The notes specified in MIL-M-3851O are applicable to this specification.
6.2 Intended use. Microcircuits conforming are intended for use in applications where the use of screened parts is
required or desirable.
6.3 Ordering Data. The contract or purchase order should specify the following:
a. Complete part number (see paragraph 1.2).
b. Requirement for certificate of compliance, if desired.
6.4 Microcircuit group assignment. These microcircuits are assigned to Technology Group D as defined in MIL-M38510, Appendix E.
6.5 Electrostatic sensitivity. CAUTION-these microcircuits may be damaged by electrostatic discharge. Precautions
should be observed at all times.
207
7.0 ELECTRICAL PERFORMANCE CURVES
(Typical at +25°C unless otherwise specified.)
0.01 ,...:';'G;;,A..;;I;.;N..;,N;.;O;,;N;.;L;;,IN;.;E,;;A..;;R..;;I..;,TY;.:.V,;;S.:G;;,A;;,IN';"'2
120.-_C.,.M_R...,V,.;"S,..S..,O,.,U",R",C_E_I_M_BA_LA,...N..;C_E--.
in
u.
ci
C.
~ O.OO3t----t----:~-~oL-I
Max
~
":
.=
==:::::=-+_..:..._-I
~
O.OOII-_T,;,y;;,P_.....
c:
60t----t-----r----+---~
'OJ
Cl
60Hz-DC •••••
0.0003 r...._ _....I._ _ _oI.._ _.....
10
100
Gain (VN)
1000
iii'
c:
"
100
~
G =1 10
'OJ
Cl 20
G=1
1% Error"""'"
a: 80
::;
Source
60
101<
lOOk
lk
Frequency (Hz)
1M
10
WARM-UP DRIFT VS TIME
:=
'"
~
is
:;
0.
.5.
~
'"c:
~
.c:
U
r---3
0
4
±5
5
o
Time (Minutes)
Frequency (Hz)
STEP RESPONSE
Gli
/aCl00b
+5
S"
C>
~
0
i\
:;
o.e- -5
'\ ......
-10
±5
±10
±15
±20
o
100
200
RL =2kn
CL = l000pF
:>
g
C>
c:
INPUT NOISE VOLTAGE
VS FREQUENCY 1100 S GAIN S 10001
g>
g
'0
51
~
'15 10
100
Z
z
:;
0.
:;
'--
a., __
&
0
1000
10
.5
0
32
600
Q)
S'"
g
"E
500
~100~------+--------r-------i
20
Q)
i=
400
~
.§
320
300
Timews)
1000
30
100
10
Gain (VN)
/
/
/
~
OUTPUT NOISE VS GAIN
SETILING TIME VS GAIN
ien
O.OI''\·L.O---:l~OO:---I~k---l~O::-k-~I00..l- k
Supply Voltage (V)
1000
!
lk
100
Frequency (Hz}
G=10
10k
+10
\......
.=
GAIN ERROR VS FREQUENCY
"
~
g-+8
\
\
S
'0
>
100
±9
~
~
32
QUIESCENT CURRENT VS SUPPLY
10
:;
~_~
"
Balanced
u
I
I
100
:!O
~
\
G=II
iii
\~
\
10
""
G= 10
G)IOO
40
__
10
G - 100. 1000
GJooo
:!!.
~
CMR VS FREQUENCY
120
0
__
3.2
Source Resistance Imbalance (knl
GAIN VS FREQUENCY
60
40L-_~
1
C3ain (VN)
208
100
10
Frequency (Hz)
1000
8. APPLICATION INFORMATION
8.1 Description. The INAIOI is a three-amplifier device which provides all the desirable characteristics of a premium
performance instrumentation amplifier. In addition, it has features not normally found in integrated circuit
instrumentation amplifiers. See simplified schematics in Figure 2.
The input section (AI and A2) incorporates high performance, low drift amplifier circuitry. The amplifiers are
connected in the noninverting configuration to provide the high input impedance (10 1°0) desirable in the instrumentation
amplifier function. The offset voltage and offset voltage versus temperature are low due to the monolithic design, and
are improved even further by state-of-the-art laser-trimming techniques.
The output section (A3) is connected in a unity-gain difference amplifier configuration. A critical part of this stage is the
matching of the four 10kO resistors which provide the difference. These resistors must be initially well matched and the
matching must be maintained over temperature and time in order to retain excellent common-mode rejection.
8.2 Using the INAIO!. Figure 4 shows the simplest configuration of the INAJO!. The gain is set by the external resistor,
RG, with a gain equation of G = I + (40kl RG). The reference and TCR of RG contribute directly to the gain
accuracy and drift.
For gains greater than unity, resistor RG is connected externally. At high gains, where the value of RG becomes small,
additional resistance (i.e., relays, sockets) in the RG circuit will contribute to a gain error. Care should be taken to
minimize this effect.
8.3 Typical applications. Many applications of instrumentation amplifiers involve the amplification of low-level
differential signals from bridges and transducers such as strain gauges, thermocouples, and RTD's. Some of the
important parameters include common-mode rejection (differential cancellation of common-mode offset and noise),
input impedance, offset voltage and drift, gain accuracy, linearity, and noise. The INAIOI accomplishes all these with
high precision.
I
I
I
I
+Vcc
+vcc
I
I This circuit may be used as a replacement
I
I
for the single potentiometer. It will adjust
I offset and leave drift unchanged.
L . . : - - - - - - - - - - : l 0 . 3I1A
Optional
Offset
Adjust
I
I
I •
I
This circuit may be used as a replacement
for the single potentiometer. It will adjust
I offset and leave drift unchanged.
L- _ _ _ _ --~;;;.:lO.311.A
I
Offset
Adjust
I
Tantalum
(a)
+Vcc
I __
100kO
L __
~
+vcc
(b)
"Goo Package
FIGURE 4. Basic Circuit Configuration.
209
I
I
iL-L_2.
l~nI __ _
"MOO Package
I::IURR-BROWN®
113131
OPA111/8838 SERIES
OPA111VM/883B
OPA111VM
REVISION NONE
APRIL,1987
Low Noise Precision O//e'® Military
OPERATIONAL AMPLIFIER
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
FULLY COMPLIANT MIL-STD-883 PROCESSING
LOW NOISE: 100% tested, 8nV/v'ifz max at 10kHz
LOW BIAS CURRENT: 2pA max
LOW OFFSET: 500pV max
LOW DRIFT: 10pV/oC max
HIGH OPEN-LOOP GAIN: 114dB min
HIGH COMMON-MODE REJECTION: 90dB min
PRECISION INSTRUMENTATION
DATA ACQUISITION
TEST EQUIPMENT
OPTOELECTRONICS
RADIATION:HARD EQUIPMENT
DESCRIPTION
The OPAlil/883B is a precision monolithic dielectrically-isolated FET (O;/el') operational amplifier. Outstanding performance characteristics allow
its use in the most critical instrumentation applications. The /883B versions are fully compliant to the
requirements of MIL-STD-883.
Noise, bi,as current, voltage offset, drift, open-loop
gain, common-mode rejection, and power supply
rejection are superior to BIFET® amplifiers.
Very low bias current is obtained by dielectric
isolation with on-chip guarding.
Laser-trimming of thin-film resistors gives very low
offset and drift. Extremely low noise is achieved
with new circuit design techniques (patented). A new
cascode design allows high precision input specifications and reduced susceptibility to flicker noise.
Standard 741 pin configuration allows upgrading of
existing designs to higher performance levels.
Dire'S Burr-Brown Corp., BIFET8 National Semiconductor Corp.
International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. 16021 746·1111 : Twx: 91(1.952·1111· Cable: BBRCORp· Telex: 66·6491
PDS-735
210
DETAILED SPECIFICATION
MICROCIRCUITS, LINEAR
LOW NOISE PRECISION O//e'® OPERATIONAL AMPLIFIER
MONOLITHIC, SILICON
1. SCOPE
1.1 Scope. This specification covers the detail requirements for a precision low noise dielectrically-isolated (Dire')
operational amplifier
1.2 Part Number. The complete part number is as shown below.
OPAlll
V
T
l
M
J883B
T
l
Basic model
Grade
Package
Hi-Rei product
(see 1.2.1)
number
(see 1.2.3)
designator (see 1.2.2)
1.2.1 Device type. The device is a single precision dielectrically-isolated (Dire') low noise operational amplifier.
One electrical performance grade (V) is provided. The V grade offers specifications and operation over the "MIL"
temperature range (-55°C to +125°C). Electrical specifications are shown in Table I, and electrical tests are shown in
Tables II and III.
1.2.2 Device class. The device class is similar to the class B product assurance level as defined in MIL-M-3851O. The
!Ii-Rcl product dcsiguatoi' portiuii of thi; part iiuiiitcf distiiiguishcs the prodiict aiiiiUl'iiu~c level as lulluws:
Hi-Rei product
designator
Requirements
Standard model, plus 100% MIL-STD-883 class B screening, with 5% PDA, plus quality
J883B
conformance inspection (QCI) consisting of groups A and B performed on each inspection
lot, plus groups C and D performed as required by MIL-STD-883.
(none)
Standard model including 100% electrical testing.
1.2.3 Case outline. The case outline is A-I (8-lead, TO-99) as defined in MIL-M-3851O, Appendix C 'and is shown in
Figure 1. The case is metal and is conductive.
~:=1
t-1i
Saot;n.
Plane
IIIII
--it..-
DIM
A
B
C
1=+-1
0
I
D
E
F
G
H
J
K
NOTE: Leads in true position
L
M
N
within .010" (.25mm) R at MMC
at seating plane.
FIGURE 1. Case Outline (TO-99) Package Configuration.
1.2.4 Absolute maximum ratings:
Supply voltage +Vcc .
Input voltage range
Differential input voltage
Internal power dissipation
Output short circuit duration
Storage temperature range
Temperature (soldering lOs)
J unction temperature
1.2.5 Recommended op.erating conditions.
Supply voltage
Ambient temperature range
±18VDC
±18VDCl!
±36VDCl!
500mW
continuous to power supply common only
-65°C to + 165°C
+300°C
TJ= +175°C
±15VDC
-55°C to +125°C
lIFor supply voltages less than ±18VDC the absolute maximum input voltage is equal to +18V >
211
VIN
> -Vee -6V.
INCHES
. MAX
MIN
.335
.370
.305
.335
.165
.185
.016
.021
.010
.040
.010
.040
.200 BASIC
.028
.034
.029
.045
.500
.110
.160
45 0 BASIC
,105
.095
MILLIMETERS
MIN
MAX
8.51
9.40
7.75
8.51
4.19
4.70
0.41
0.53
0.25
1.02
0.25
1.02
5.08 BASIC
0.71
0.86
0.74
1.14
12.7
2.79
4.06
45° BASIC
2.41
2.67
1.2.6 Power and thermal characteristics
Case outline
Package
8-lead can
Figure I
Maximum allowable power dissipation
500mW
MaximumOJC
60°C/W
2. APPLICABLE DOCUMENTS
2.1 The following form a part of this specification to the extent specified herein.
SPECIFICATION
MILITARY
MIL-M-3851O-Microcircuits, general specification for.
STANDARD
MILITARY
MIL-STD-883-Test methods and procedures for microcircuits.
3. REQUIREMENTS
3.1 General. Burr-Brown uses production and test facilities and a quality and reliability assurance program adequate
to ensure successful compliance with this specification.
3.1.1 Detail sRecifications. The individual item requirements are specified herein. In the event of conflicting
requirements, the order of precedence will be the purchase order, this specification, and then the reference documents.
3.2 Design, construction and pl!ysical dimensions.
3.2.1 Packa~, metals, and other materials. The package, metal surfaces, and other materials are in accordance with
MIL-M-3851O.
3.2.2 Design documentation. The design documentation is in accordance with MIL-M-3851O.
3.2.3. Internal conductors and internal lead wires. The internal conductors and internal lead wires are in accordance
with MIL-M-3851O.
3.2.4. Lead material and finish. The lead material and finish is in accordance with MIL-M-38510 and is
solderable per MIL-STD-883, method 2003.
3.2.5 Die thickness. The die thiCkness is in accordance with MIL-M-38510.
3.2.6 Physical dimensions. The physical dimensions are in accordance with paragraph 1.2.3 herein and are shown in
Figure 1.
3.2.7 Circuit diagram and terminal connections. The circuit diagram and terminal connections are shown in Figure 2.
Substrate and Case
Case and Substrate
-In
Trim
10kCl
2kCl
-Vee
Trim
(b) Terminal Connections
10kCl
~----~--------~----{4
-Vee
"Patented
(a) Circuli Diagram
FIGURE 2. Circuit Diagram and Terminal Connections.
3.2.8 Glassivation. The microcircuit dice are glassivated.
212
3.3 Electrical p'erformance characteristics. The electrical performance characteristics are specified in Table I and apply
over the full operating ambient temperature range of -55°C to +l25°C unless otherwise specified.
TABLE I. Electrical Performance Characteristics.
All characteristics at -55°C:5 T A :5 +125°C, ±Vcc = 15VDC, pin 8 connected to ground unless otherwise specified.
OPA111VM/883B
OPA111VM
CHARACTERISTICS
CONDITIONS 1/
SYMBOL
MIN
TYP
MAX
UNITS
GAIN
Open-Loop
Voltage Gain
Avs
T. = +25'C
-55'C:5 T.:5 +125'C
R,=2kn
}
Vo = ±10V. F = OHz
114
110
dB
dB
RATED OUTPUT
Voltage
Current
Output Resistance
Load Capacitance Stability
Short Circuit Current
VoP
10
Ro
C,
los
R, = 2kn
±10
±5
DC. Open Loop
Gain =+1
T. = +25'C
T. = +25'C
V
mA
n
pF
mA
100
1000
±10
To Ground
DYNAMIC RESPONSE
Bandwidth
Bandwidth
Slew RAte
Setlling Time (0.1%)
Settling Time (0.01%)
Overload Recovery 21
BW
'BW
SR
Ts
Ts
T.
Unity Gain-Small Signal
T.
T.
Tn
T.
T.
T.
Full Power
R:. = 2~Q, \!~ - =10'.'
G = -1. R, = 2kn. 10V step
G = -1. R, = 2kn. 10V step
Gain =-1
= +25'C
=+25'C
-+~5°C
2
MHz
kHz
Vlji"
ps
16
1
= +25'C
=+25'C
=+25'C
6
10
5
pS
ps
INPUT OFFSET VOLTAGE W
Initial Offset
Temperature Sensitivity
vs Power Supply
V,o
DVlo
PSRR
VeM =OVDC
V,o (T.) - V,o (+25'C)
AT
Vee = ±10Vee = ±18VDC
T.= +25'C
-500
+500
pV
-55:5 T.:5 +125'C
T. = +25'C
-55:5 T.:5 +125'C
-10
-31
-50
+10
+31
+50
pV/'C
pVIV
pVIV
INPUT BIAS CURRENT;)j
Initial
~ias
I"
VCM=O
T.=+25'C
-55°C :S TA :5 +125°C
-2
-4100
+2
+4100
pA
pA
100
VCM
= 0
T.=+25'C
-55'C:5 T.:5 +125'C
-1.5
-3100
+1.5
+3100
pA
pA
T.=+25'C
T. = +25'C
10" 111
10" 113
vs Supply Voltage
INPUT OFFSET CURRENT ;)j
Initial Offset
INPUT IMPEDANCE
Differential
Common-Mode
Z,o
ZICM
nil pF
nil pF
INPUT NOISE
Voltage
Current
eN
iN
fo = 10Hz
fo = 100Hz
.10= 1kHz
fo = 10kHz
f. = 10Hz to 10kHz
f. = 0.1Hz to 10Hz
fo = 0.1Hz thru 20kHz
T. =+25'C
T.= +25'C
80
40
1.5
8
1.2
TA = +25°C
T. =
T.=
T.=
T.=
+25'C
+25'C
+25'C
+25'C
nVlv'Hz
nVlv'Hz
nVlv'Hz
nVlv'Hz
pVrms
fA, p-p
fAlv'Hz
7.5
0.4
INPUT VOLTAGE RANGE
Common-Mode
Common-Mode Rejection
V. eM
CMRR
T.= +25'C
T. = +25'C
-55'C:5 T.:5 +125'C
V'N = ±10V
V
dB
dB
±10
90
86
POWER SUPPLY
Rated Voltage
Voltage Range
. Quiescent Current
±15
Vee
±5
±18
±3.5
-55
-65
+125·
+150
10
VDC
VDC
mA
TEMPERATURE RANGE (ambient)
Operating
Storage
'C
'C
1/ Optimum device performance is characterized in a reduced ambient light environment.
21 Overload recovery is defined as the time required for the output to return from saturation to linear operation following the removal of a 50% input
overdrive signal.
'J/ Offset voltage. offset current, and bias current are measured with units fully warmed up.
213
3.4 Electrical test reHuirements. Electrical test requirements are shown in Table II. The subgroups of Table III which
constitute the minimum electrical test requirements for screening, qualification, and quality conformance inspection,
are specified in Table II.
TABLE II. Electrical Test Requirements.
The individual tests within the subgroups appear in Table III.
MODELS
MIL-STD-BB3 REQUIREMENTS
OPAll1VM/BB3B
Interim electrical parameters (pre burn-in, method 5004)
OPAll1VM
I'
1
Final electrical test parameters (method S004)
1. 2. 3. 4. S, 6, 7
I, 2, 3, 4, S, 6, 7
Group A test requirements (method SOOS)
1. 2. 3. 4. S, 6, 7
-
Group C and D end pOint electrical parameters (method 5005)
1
'PDA appfies to subgroup 1 (see 4.3d).
TABLE III. Group A Inspection.
LIMITS
SUBGROUP
SYMBOL
1
TA = +2S'C
V,o
2
TA = +12S'C
3
TA = -SS'C
I"
1'0
PSRR
CMRR
±Icc
los
DVlo
I"
100
PSRR
CMRR
±Icc
los
DVlo
I"
100
PSRR
CMRR
±I cc
los
4
TA= +2S'C
±Vop
S
TA = +12S'C
±Vop
6
TA = -SS'C
±Vop
7
TA = +25'C
MIL-STD-8B3
METHOD OR
EQUIVALENT
4001
4001
4001
4003
CONDITIONS
±Vee = ±ISVDC
OPAll1VM/BB3B
OPAll1VM
unless otherwise specified
MIN
MAX
UNITS
VeM = OVDC
-SOO
-2
-1.S
-31
90
+SOO
+2
+1.S
+31
/1V
pA
pA
Vee = ±10VDC to ±18VDC
V'N = ±10V
10 = OmA
±3.S
±10
4001
4001.
4001
4003
VeM = OVDC
Vee = ±10VDC to ±IBVDC
V'N = ±10V
10 =OmA
-10
-4100
-3100
-SO
8S
±3.S
±1O
4001
4001
4001
4003
VCM = OVDC
Vee = ±10VDC to ±IBVDC
V'N = ±10V
10= OmA
-10
-4100
-3100
±3.5
±10
RL = 2kO
RL 22kO
114
4004
RL = 2kO
RL22kO
110
Avs
4004
RL = 2kO
RL 22kO
110
SR
eN
4002
Avs
+10
+4100
+3100
±50
B6
4004
Avs
+10
+4100
+3100
+SO
Vo = ±10V. RL = 2kO
fo = 10Hz
fo = 100Hz
fo = 1kHz
fo = 10kHz
f. = 10Hz to 10kHz
BWFP
dB
mA
mA
/1V/'C
pA
pA
/1VIV
dB
mA
mA
/1V1'C
pA
pA
/1VIV
dB
mA
mA
±10
V
• dB
±10
V
dB
+10
V
dB
BO
40
15
8
1.2
nVJF!z
nVJRZ
nVJRZ
nVJRZ
VI/1s
1
16
/1VIV
pVrms
kHz
3.5 Marking,. Marking is in accordance with MIL-M-3851O. The following marking is placed on each microcircuit as a
minimum:
a. Part number (see paragraph 1.2)
b. Inspection lot identification code 11
c. Manufacturer's identification ( iU~E;r )
jJ A 4-digit code, indicating year and week of seal. and a 4- or 5-digit lot identifier are marked on each unit.
214
d. Manufacturer's designating symbol (CEBS)
e. Country of origin
f. Electrostatic sensitivity identifier (tl)
3.6 WorkmanshiQ. These microcircuits are manufactured, processed, and tested in a workmanlike manner. Workmanship is in accordance with good engineering practices, workmanlike instructions, inspection. and test procedures
and training, prepared in fulfillment of Burr-Brown's product assurance program.
3.6.1 Rework provisions. Rework provisions, including rebonding for the "/883B" product designation, are in
accordance with MIL-M-3851O.
3.7 Traceability. Traceability for the "/883B" product designation is in accordance with MIL-M-3851O. Each
microcircuit is traceable to the production lot and to the component vendor's component lot.
3.8 Product and process change. Burr-Brown will not implement any major change to the design, materials,
construction, or manufacturing process which may affect the performance, quality, or interchangeability of the
microcircuit without full or partial requalification.
3.9 Screening. Screening for the "/883B" Hi-Rei product designation is in accordance with MIL-STD-883, method
5004, class B, except as modified herein.
Screening for the standard model includes Burr-Brown QC4118 internal visual inspection, stabilization bake, fine leak,
gross leak, constant acceleration (condition A), temperature cycle (condition C), and external visual per MIL-STD883, method 2009.
Pui' the "/0030" product designation, all microcircuits will have passed the screening requirements prior to
qualification or quality conformance inspection.
3.10 Qualification. Qualification is not required. See paragraph 4.2 herein.
3.11 Quality conformance inspection. Quality conformance inspection, for the "/883B" product designation, is in
accordance with MIL-M-38510, except as modified in paragraph 4.4 herein. The microcircuit inspection lot will have
passed quality conformance inspection prior to microcircuit delivery.
4. PRODUCT ASSURANCE PROVISIONS
4.1 Sampling and inspection. Sampling and inspection procedures are in accordance with MIL-M-3851O and MILSTD-883, method 5005, except as modified herein.
4.2 Qualification. Qualification is not required unless specifically required by contract or purchase order. When so
required, qualification will be in accordance with the' inspection routine of MIL-M-3851O, paragraph 4.4.2.1. The
inspections to be performed are those specified herein for groups A, B, C, and D inspections (see paragraphs 4.4.1,
4.4.2, 4.4.3, and 4.4.4).
Burr-Brown has performed and successfully completed qualification inspections as described above. The most recent
report is available from Burr-Brown.
4.3 Screening. Screening for the "/883B" Hi-Rei product designation is in accordance with MIL-STD-883, method
5004, class B, and is conducted on all devices. The following criteria apply:
a. Interim and final test parameters are specified in Table II.
b. Burn-in test (MIL-STD-883, method lOIS) conditions: .
(I) Test condition B.
(2) Test circuit is Figure 3.
(3) TA = +125°C minimum.
(4) Test duration. is 160 hours minimum.
c. Percent defective allowable (PDA). The PDA, for "/883B" product designation only, is five percent and
includes both parametric and catastrophic failures from group A, subgroup I test, after cool-down as final
electrical test in accordance with MIL-STD-883, method 5005, and with no intervening electrical measurements. If interim electrical parameter tests are performed prior to burn-in, failures resulting from preburn-in
screening failures may be excluded from the PDA. If interim electrical parameter tests .are omitted, all
screening failures shall be included in the PDA. The verified failures of group A, subgroup I, after burn-in are
used to determine the percent defective for each manufacturing lot, and the lot is accepted or rejected based
onPDA.
d. External visual inspection need not include measurement of case and lead dimensions.
4.4 Quality conformance insp'ection. Groups A and B inspections of MIL-STD-883, method 5005, class B, are
performed on each inspection lot. Groups C and D inspections of MIL-STD-883, method 5005, class B are performed
as required by MIL-STD-883.
.
215
A report of the most recent group C and D inspections is available from Burr-Brown.
4.4.1 Group A inspection. Group A inspection consists of the test subgroups and LTPD values shown in MIL-STD883, method SOOS, and as specified in Table II herein.
4.4.2 Group B inspection. Group B Inspection consists of the test subgroups and LTPD values shown in MIL-STD883, method SOOS, class B.
4.4.3 Group C inspection. Group C inspection consists of the subgroups and LTPD values shown in MIL-STD-883,
method 100S, class B, and as follows:
a. Operating life test (MIL-STD-883, method 100S) conditions:
(I) Test condition B.
(b) Testcircuit is Figure 3.
(3) TA = +12SoC minimum.
(4) Test duration is 1000 hours minimum.
b. End point electrical parameters are specified in Table II herein.
R,
100kO
+15VDC
R,
lkO
FIGURE 3. Test Circuit, Burn-In and Operating Life Test.
4.4.4 Group D inspection. Group D inspection consists of the test subgroups and LTPD values shown in MIL-STD883, method SOOS.
4.4.5 Inspection of packaging. Inspection of packaging shall be in accordance with MIL-M-38SIO.
4.S Methods of examination and test: Methods of examination and test are specified in the appropriate tables.
Electrical test circuits are as prescribed herein or in the referenced test methods of MIL-STD-883.
4.S.1 Voltage and current. All voltage values given, except the input offset voltage (or differential voltage) are
referenced to the external zero reference level of the supply voltage. Currents given are conventional current and
positive when flowing into the referenced terminal.
S. PACKAGING
S.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-M-38SI0.
6. NOTES
6.1 Notes. The notes specified in MIL-M-38SIO are applicable to this specification.
6.2 Intended use. Microcircuits conforming to this specification are intended for use in applications where the use of
screened parts is required or desirable.
6.3 Ordering data. The contract or purchase order should specify the following:
a. Complete part number (see paragraph'1.2).
b. Requirement for certificate of compliance, if desired.
6.4 Microcircuit group assignment. These microcircuits are assigned to Technology Group E with a microcircuit group
number of 61 as defined in MIL-M-38SI0, Appendix E.
216
6.5 Electrostatic sensitivity. CAUTION-these microcircuits may be damaged by electrostatic discharge. Precautions
should be observed at all times.
7. ELECTRICAL PERFORMANCE CURVES.
TA = +25 D C, Vee
INPUT CURRENT NOISE SPECTRAL OENSITY
100
~
~
= ±15VDC unless otherwise noted.
INPUT VOLTAGE NOISE SPECTRAL DENSITY
1k
~~
10
100
S
ill
ill
z
~
'0
z
1/
C
~
I""i"'!!.
'0
"
10
'"
!!!
"0
>
:;
C"l
0.1
100
10
10k
1k
100k
1M
100
10
Frequency (Hz)
TOTAL' INPUT VOLTAGE NOISE SPECTRAL
DENSITY vs SOURCE RESISTANCE
1k
100
'"
S
R.
10
0.
> 100 r- .
ill
'0
.J.IlI
~
"0
"
f,
= 0.1 to 101
100
1k
10k
"0
I""
100k
10'
10'
1011
12
ill
0
f o J1kHZ
8
Z
"
'"
!!!
"0
>
6
~
p
4
-75 -50
--25
1k
~
........::
--
10'
~~
l.,.....- ~
: tln=t=tttt-l.
~
.J. 10 ~
~
~
108
TOTAL INPUT VOLTAGE NOISE'SPECTRAL DENSITY
AT 1kHz vs SOURCE RESISTANCE
100
S
107
Sour~e Resistance (0)
VOLTAGE AND CURRENT NOISE SPECTRAL
DENSITY vs TEMPERATURE
10
\.00'
>
Frequency (Hz)
~~
Z
10
_lilt
1111
from source r~rista~e
10
~
z
ill
·Includes contribution
0.1
~
3'
100kO
10!O
>
1M
source resistance
Ci
1111
'0
"
~
100k
.1'nl~lu~:-J~tr;tj~JtJm
r-
10MO
J.UUo+
ill
z
10k
TOTAL' INPUT VOLTAGE NOISE (PEAK-TO-PEAK)
vs SOURCE RESISTANCE
1k
R.
~~
1k
Frequency (Hz)
:a
iloa
in'
g
z0
u1
"
'0
~
~o_
1
'itft=I:::;M'fI=I=::J:l#=t=f:I:I:I
R.
0r-;11;\ resistor
Z
~
~~ -
~ 10
01~
"0
>
+25
+50
+ 75
0.01
+100 +125
1
~~
100
Temperature (0 C)
Resistor noise only
1k
10k
100k
1M
!3ource Resistance (0)
217
10M
100M
INPUT OFFSET VOLTAGE WARM-UP DRIFT
SUPPLY CURRENT vs TEMPERATURE
+20
~ -10
5
0-7~5~--~5~0----~2~5--~---+~25~-+~5~0~~+~7~5--~+~10~0~+~125
-20
Ambient Temperature (0 C)
Time From Power Turn-On (Min)
COMMON-MODE REJECTION
vs INPUT COMMON MODE VOLTAGE
BIAS AND OFFSET CURRENT
vs TEMPERATURE
1k
1k
'£L
100
'""
~
L IL
~
100 0
;(
10
120
iii'
10
t----
~
~
~
a:
~
"
~
u
~
~
.2:
./
.,./
0.1
0.01
-50
-25
E
E
+25
+50
I
I
BO
d
0
0.01
+125
+100
+75
90
u
--
0
I
0
0.1
i75"
t-
r
j
100
~
"0
0
'C
~
iii
110
c
II
70
-15
-10
-5
Ambient Temperature (OC)
I
o
.1
+10
+5
+15
Common-Mode Voltage (V)
GAIN-BANDWIDTH AND SLEW RATE
vs TEMPERATURE
POWER SUPPLY REJECTION
vs FREQUENCY
4
140
iii'
~
c
120
N
.2
100
"
80
Ci
60
U
~
a:
I
""
>-
g.
I Ii
Q;
~
0
0-
40
I !I
"""-
j
"
-
.-
i'-
(/)
1-_
J.
~
1
I L
I'
~
20
0
I
_1'10.
1
10
100
1k
10k
100k
I
o
1\1.
I
1M
-75
50
-25
+25
+50
10M
Frequency (Hz)
Ambient Temperature (0 C)
218
+75
+100 +125
BIAS AND OFFSET CURRENT
ys INPUT ·COMMON MODE VOLTAGE
OPEN-LOOP FREQUENCY RESPONSE
140
-t-
10
10
120
1il
:<:
.e
Bias Current
E
~
u
:::
iii
0.1
:!!.
[
~
80
"
60
C>
!!!
15
>
a
uridn
0.1
.
-15
-10
-5
a
+10
+5
'0
.
0
'P.
100
-
Phase
Margin
o
~~
~
-135
~6rll
20
om
+15
--
40
2!
om
-45
II
--
c
~
[0 fsel
100
Q
"a
II II
"
JJll~r
""'Io.l
1
10
lk
100
10k
lOOk
1M
-180
10M
Frequency (Hz)
Common-Mode Vollage (V)
GAIN-BANDWIDTH AND SLEW RATE
ys SUPPLY VOLTAGE
COMMON-MODE REJECTION
ys FREQUENCY
140
3
1il
:!!. 120
c
~
1--,
N
I
100
"
II:
~
·is
GO
"a
~c:
80
E
E
40
~
N.
80
i
".c
OJ
a
1
c:
~
0
u
2
20
a
1
10
100
lk
10k
lOOk
1M
a
a
10M
15-
10
5
20
Frequency (Hz)
Supply Voll.ge (±Vcc)
OPEN-LOOP GAIN
ys TEMPERATURE
140
1il
-
130
:!!.
c
·iii
.
4!0
>
SETTLING TIME ys CLOSED-LOOP GAIN
10 0
E
j::
~
7
60
II
C>
.5
~
0.1%
40
0.01%
'"
110
V.
0
100
-75
-50
-25
a .,.25 +50 +75
Ambient Temperature (OC)
~
If
If'
I'
a
+100 +125
1
10
100
Closed-Loop Gain (VIV)
219
lk
I
MAXIMUM UNDISTORTED OUTPUT
VOLTAGE vs FREQUENCY
30
c:
6.
G 20
\
\
~
E
g
"-
~ 10
:;
r--
o
......
r-- 1--o
lk _
10k
--- f-
r-...
r1M
lOOk
Frequency (Hz)
LARGE SIGNAL TRANSIENT RESPONSE
25
SMALL SIGNAL TRANSIENT RESPONSE
50
Time (115)
Time (115)
8. APPLICATION INFORMATION
8. I Offset voltage adjustment. Although the OPAlllj883B Series has a low initial offset voltage (500ji V), some
applications may require external nulling of this small offset. Figure 4 shows the recommended circuit for adjustment
of the offset voltage. External offset voltage adjustment changes the laser-adjusted offset-voltage temperature drift
slightly. The drift will change approximately 0.3jiVjOC for every 100jiV of offset adjustment.
3
±iomv Typical
Trim Range
-Vee
'10kO to lMO
Trim Potentiometer
(100kO Recommended)
FIGURE 4. Offset Voltage Trim.
8.2 Guarding and shielding. The ultra-low bias current and high input impedance of the OPAlllj883B Series are
well,suited to a number of stringent applications; however, careless signal wiring of printed circuit board layout can
degrade circuit performance several orders of magnitude below the capability of the OPAlllj883B Series.
As in any situation where high impedances are involved, careful shielding is required to reduce "hum" pickup in input
leads. If large feedback resistors are used, they should also be shielded along with the external input circuitry.
220
Leakage currents across printed circuit boards can easily exceed the amplifier's bias current of the OPAlll/ 883B Series.
To avoid leakage problems, it is recommended that the signal input lead of the OPAIlI/883B Series be wired to a Teflon'·
standoff. If the OPAIlI/883B Series is to be soldered directly.into a printed circuit board, utmost care must be used in
planning the board layout. A "guard" pattern should completely surround the two amplifier input leads and should be
connected to a low input impedance point which is at the signal input potential.
The amplifier case should be connected to any input shield or guard via pin 8. This insures that the amplifier itself is
fully surrounded by guard potential, minimizing both leakage and noise pickUp. Figure 5 illustrates the use of the
guard. The resistor R3 shown in Figure 5 is optional. It may be used to compensate effects of very large source
resistances. However, note that its use would also increase the noise due to the thermal noise of R3.
8.3 Additional application information. Additional application information is presented in the commercial OPAIl!
data sheet.
Qutpul
Input
()------+--+-I
Follower
Inverting Amplifier
Noninverting Amplifier
*R 3 may be used to compensate
for very large source resistances.
(R, X R,) + (R, + R,)
must be low impedance.
Board layout for input guarding
with TQ-99 package.
FIGURE 5. Connection of Input Guard.
Teflon" E.1. du Pont de Nemours and Company.
221
BURR-BROWN®
IElElI
OPA501/883B SERIES
OPAS01VM/8838
OPAS01VM
OPAS01UM/8838
OPAS01UM
High Current, High Power Military
OPERATIONAL AMPLIFIER
FEATURES
•
•
•
•
•
WIDE SUPPLY RANGE. ±10Vto ±40V
HIGH OUTPUT CURRENT. ±10A Peak
HIGH OUTPUT POWER. 260W Peak
LOW DC THERMAL IMPEDANCE: 2.2°C/W
MIL·STD·BB3 SCREENING
DESCRIPTION
The OPA501 is a high power operational amplifier.
Its high current output stage delivers ±IOA, yet the
amplifier is unity-gain stable and it can be used in
any operational amplifier configuration. The 260W
peak output capability allows the OPA501 to drive
loads (such as motors) with a greater safety margin.
Safe operating area is fully specified and output
current limiting is provided to protect both the
amplifier and the load from excessive current.
This hybrid Ie is housed in an 8-pin hermetic TO-3
package. The electrically· isolated package allows
direct mounting to chassis or heat sink without an
insulating washer or spacer which would increase
thermal resistance.
Two electrical performance grades are available. The
premium grade operates from -55°e to + l25°e and
is designed for military, aerospace, and demanding
industrial applications. The U grade has specifications
for operation from -25°C· to +85°e and from
-55°C to + 125°C. Applications include test equip-
ment, shipboard, and ground support equipment
where operation is normally between -25°C and
+85°e and full temperature range operation must
be assured.
The OPA501/883B Series is manufactured on a
separate Hi-Rei manufacturing line with impeccable
clean room conditions, which assures inherent quality
and provides for long product life.
Two product assurance levels are available: Standard
and /883B. The Standard product assurance level
offers Hi-Rei manufacturing where many MILSTD·883 screens are performed routinely. The /883B
product assurance level, /883B suffix, offers'Hi-Rel
manufacturing, 100% screening per MIL-STD-883
method 5008 and 10% PDA. Quality assurance
further processes /883B devices, by performing group
A and B inspections on each inspection lot and
group e and D inspections as required by MILSTD-883. A report containing the most recent group
A, B, e, and D tests is ~vailable for a nominal charge.
NOTE: This device was previously identified as OPA8785/883B
Series.
Inlernational Alrporllndustrlal Park • P.O. Box 11400 • Tucson. Arizona 85734 • Tel.: (602) 7411-1111 • Twx: 910-952·1111 • Cable: BBRCORP • Talax: 66-6491
PDS·707
222
DETAILED SPECIFICATION
MICROCIRCUITS, LINEAR
HIGH CURRENT, HIGH POWER OPERATIONAL AMPLIFIER
HYBRID, SILICON
I. SCOPE
1.I ScoP.!O: This specification covers the detail requirements for a high current, high power operational amplifier.
1.2 Part Number. The complete part number is as shown below.
OPA501
=r=
Basic model
V
M
l
~
/883B
-=r
Hi-Rei product
Grade
Package
number
(see 1.2.1) (see 1.2.3) designator (see 1.2.1)
1.2.1 Device typ.!O: The device is a single operational amplifier. Two electrical performance grades are provided. The V
grade offers performance specifications over the MIL temperature range (-55°C to + 125°C) and the U grade is
specified over the industrial temperature range (-25°C to +85°C). Electrical specifications are shown in Table I and
electrical tests are shown in Tables II and III.
1.2.2 Device class. The device' class is similar to the class B product assurance level as defined in MIL-M-3851O. The
Hi-ReI pj"uduct designator portion of th\:: P"i"t number di:;tingui:;he:; the prcduct ~~~u!":!nce le'.'e!~ available as follo'.1.'s:
Hi-Rei Product
Designator
Reguirements
/883B
Standard model plus 100% MIL-STD-883 class B screening, with 10% PDA, plus quality
conformance inspection (QCI) consisting of Groups A and B performed on each inspection lot,
plus Groups C and D performed as required by MIL-STD-883.
(none)
Standard model including 100% electrical testing.
1.2.3 Case Outline. The case outline is an 8-pin TO-3 package and is depicted in Figure 1.
IE;~~
Seating Plane
E
K
•
NOTE: Leads in true position
within .010" (.2Smm) R at MMC
at seating plane.
Pin numbers shown for reference
only. Numbers may not be marked
on package.
DIM
A
B
C
D
E
Q
F
G
H
J
K
a
R
INCHES
MIN
MAX
1.510
1.550
.745
.770
.34()
.260
.038
.042
.105
.080
4()' BASIC
.500 BASIC
1.166 BASIC
.593 BASIC
.400
.500
.151
.161
.980
1.020
FIGURE 1. Case Outline (TO-3) Package Configuration.
223
MILLIMETERS
MIN
38.35
18.92
6.60
0.97
2.03
MAX
39.37
19.56
8.64
1.07
2.67
40 a BASIC
12.7 BASIC
30.12 BASIC
15.06 BASIC
10.16
12.70
3.84
4.09
24.89
25.91
1.2.4 Absolute maximum rati'ng~
Supply Voltage Vee .................................................... ±40VDC
Differential input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± Vcc -:- 3
DC internal power dissipation .......................................... 80W Jj
AC internal power dissipation (10kHz, SO% duty cycle) ............... l60W Jj
Output short circuit duration ............................ Continuous to ground
Storage temperature range ................................... -6SoC to +l6SoC
Lead temperature (soldering, 60sec)...................................... 300°C
Junction temperature ................................................ Tj = 200°C
Common~mode input voltage .............................................. ±Vcc
I.2.S Recommended orerating conditions.
Supply voltage Range ................................... ±34VDC (see Table I)
Ambient temperature range .................................. -'-SsoC to +l2SoC
1.2.6 Power and thermal characteristics.
Case
Maximum allowable
Maximum
outline
Packag~
Rower dissip'ation
OJ-C
8-lead TO~3
Figure I
80W
2.2°CfW
with heat sink
with heat sink
2. APPLICABLE DOCUMENTS
2.1 The following documents form a part of this specification to the extent specified herein.
SPECIFICATION
MILITARY
MIL-M-38SIO-Microcircuits, general specifications for.
STANDARD
MILITARY
MIL-STD-883-Test methods and procedures for microcircuits.
3. REQUIREMENTS
3.1 General. Burr-Brown uses production and test facilities and a quality and reliability assurance program adequate
to assure successful compliance with this specification. 3.1.1 Detail sp'ecifications. The .individual itein requirements are specified herein. In the event of conflicting
requirements the order of precedence will be the purchase order, this specification, and then the reference documents.
3.2 Design, construction, and PEysical dimensions.
3.2,1 Package, metals, and other materials. The packages, metal surfaces, and other materials are in accordance with
MIL-M-38SIO.
3.2.2 Design Documentation. The design documentation is in accordance with MIL-M-38SIO.
3.2.3 Internal conductors and internal lead wires·. The internal conductors and internal lead wires are in accordance
with MIL-M-38SIO.
3.2.4 Lead material and finish. The lead material and finish is in accordance with MIL-M-38510 and is solderable per
MIL-STD-883, method 2003.
3.2.5 Die thickness. The die thickness is in accordance with MIL-M-38SIO.
3.2.6 Physical dimensions. The physical dimensions are in accordance with paragraph 1.2.3 herein.
3.2.7 Circuit diagram and terminal connections. The circuit diagram and terminal connections are shown in Figure 2.
3.2.8 Glassivation. The microcircuit dice are glassivated.
3.3 Electrical rerformance characteristics. The electrical performance charactersitics are specified in Table I and apply
over the full operating ambient temperature range of -SsoC to + 125°C unless otherwise specified.
224
+Vee
+Current
Limit
(+Rse)
Output
-In
Out
Tin
-Current
Limit
(-:Rse)
No Internal
Connection
-Vec
(b) Terminal Connections-Top View
(a) Circuli Diagram
FIGURE 2. Circuit Diagram and Terminal Connections.
TABLE I. Electrical Performance Characteristics.
All characteristics at -55°C:$ TA S +125°C. ±Vcc;;::; 34VDC unless otherwise specified.
OPAS01VM/883B
OPAS01VM
CHARACTERISTICS
RATED OUTPUT 11
Output Current
Continuous 'J/
Output Voltage 'J/
SYMBOL
CONDITIONS
MIN
TYP
MAX
MIN
-10
-30
+10
+30
-26
+26
··
'?/
DYNAMIC RESPONSE
Bandwidth
Bandwidth
Slew Rate
INPUT OFFSET VOLTAGE
Initial Offset
lop
Vop
Vo.
BW
BW
SR
V,O
Tempco
OVIO
Vs Supply Voltage
PSRR
INPUT BIAS CURRENT
Initial
10.
RL = 2.60, T. = +2S'C
RL = 10kO
10 = lOA peak, 10kHz sine wave,
T. = +25'C
Unity Gain, Small Signal T. = +2S'C
Full Power Vo = 40Vp-p, RL = 80,
T.=+25'C
RL = 6.S0
T.= +2S'C
[V,O (T.) - V,O (+2S'C)].;. AT
-S5'C:5 T.:5 +12S'C
-2S'C:5 T.:5 +8S'C
Vee = ±10, Vee = ±40, T. = +25'C
-55'C:5 T.:5 +125'C
OPAS01UM/883B
OPAS01UM
-20
1
··
10
1.35
-S
+5
-40
+40
-100
-200
+100
+200
TYP
UNITS
··
A
V
+20
·
kHz
Vips
+10
··
+65
··
±40
±20
±35
±50
Vs Supply
±0.02
V
MHz
-10
-6S
T.= +2S'C
-55'C:5 T.:5 +12S'C
-25'C:5 T.:5 +85'C
MAX
±0.02
mV
pVl'C
pVl'C
pVN
pVlV
nA
nA
nA
nAN
INPUT DIFFERENCE
CURRENT
Initial
los
T. = +2S'C
OPEN LOOP GAIN, DC
Av.
INPUT IMPEDANCE
Z,O
±10
±3
±7
-55°C:::; TA.::s;: +125°C
-25°C:::; TA $: +85°C
±7
RL =10kO
94
90
10
2S0
ZICM
225
··
nA
nA
nA
dB
MO
MO
TABLE I. Electrical Performance Characteristics (cont) .
. OPA501VM/883B
OPA501VM
CHARACTERISTICS
SYMBOL
INPUT NOISE
Voltage Noise
e,
Current Noise
i,
INPUT VOLTAGE RANGE
Common-mode
Common-mode Rejection
VICM
CMRR
POWER SUPPLY
'Rated Voltage
Operating Voltage Range
Current, Quiescent
CONDITIONS
f,
f,
f,
f,
MIN
TYP
= 0.3Hz to 10Hz
= 10Hz to 10kHz
= 0.3Hz to 10Hz
= 10Hz to 10kHz
OPA501 UM/883B
OPA501UM
MAX
MIN
TYP
/lV, p-p
/lV,rms
pA,p-p
pA,rms'
·
·
±(lVccl- 6)
76
80
V
dB
dB
70
70
Vee
· · ··
±34
±10
±4O
±10
-55
-65
+125
+150
la
TEMPERATURE RANGE
Specification
Storage
UNITS
···
3
5
20
4.5
Linear Operation
F = DC, V,CM = ±22V
T. = +25'C
MAX
-25
·
.
V
V
mA
·
+85
'C
'C
·Speclflcatlon same as OPA501 V" grade.
NOTES:
1/ Package must be derated based on a junction-ta-case thermal resistance of 2.2 Q CIW or a junction-ta-ambient thermal resistance of 30°CtW.
21 Safe Operating Area and Power Derating Curves must be observed.
W With ±Rsc = O. Peak output currenlls Iypical!y greaterthan lOA if duty cycle and pulse width limitations are observed. Output current greaterlhan lOA is
not guaran,teed.
3.4 Electrical test requirements. Electrical test requirements are shown in Table II. The subgroups of Table III which
constitute the minimum electrical test requirements for screening, qualification, and quality conformance are specified
in Table II.
.
TABLE II. Electrical Test Requirements.
MODELS
MIL-STO-883 REQUIREMENTS (HYBRID CLASS)
OPA501VM/883B
OPA501VM
OPA501UM/883B
1
1
1
I
Final electrical test parameters (method 5008)
1',2,3,4,5,6,7
1,2.3,4,5,6,7
1',2,3,4,5,6,7
1,2,3,4.5,6,7
Group A test requirements (method 5008)
1,2,3,4,5,6,7
-
1,2,3,4,5,6,7
Interim el.eetrieal parameters (Preburn-in) (method 5008)
Group C end point electrical parameters (method 5008)
1
OPAS01UM
-
1
'PDA applies to subgroup 1 for 1883B Hi-Rei designator (see 4.3e).
TABLE III. Group A Inspection.
,
LIMITS
SUBGROUP
SYMBOL
1
T. = +25'C
V,a
118+
118-
100
+PSRR
-PSRR
CMRR
lee.
Icc-
MIL-STD-883
METHOD OR
EQUIVALENT
4001
4001
4001
4001
4003
4003
4003
4005'
4005
CONDITIONS
±Vcc = ±34VDC
. unless otherwise specified
-Vee = 34VDC, +Vee = 10 to 40VDC
+Vee = 34VDC, -Vee = 10 to 40VDC
VCM = ±22V, F = DC
VCM ;; 0, no load condition
V CM ;; 0, no load condition
226
OPA501VM/883B
OPA501VM
OPA501 UM/883B
OPA501UM
MIN
MAX
MIN
MAX
UNITS
-5
-20
-20
-3
-100
-100
80
+5
+20
+20
+3
+100
+100
-10
-40
-40
-10
+10
+40
+40
+10
mV
nA
nA
nA
/lV/V
IlV/V
dB
mA
mA
+10
-10
·· ··
· ·
70
TABLE III. Group A Inspection (cont).
LIMITS'
SUBGROUP
TA ;::::
2
+125°C
SYMBOL
MIL-STD-883
METHOD OR
EQUIVALENT
4001
4001
4001
4001
4003
4003
4003
4005
4005
OVlo
118+
IIB-
1,0
+PSRR
-PSRR
CMRR
Icc+
Icc-
3
TA ;:::: -55°C
OPA50WM/883B
OPA501VM
OPA501UM/883B
OPA501UM
unless otherwise specified
MIN
MAX
MIN
MAX
UNITS
[V,0(+125'C) - Vm(+25'C)] + 100
-40
-35
-35
-7
-200
-200
76
+40
+35
+35
-65
-60
-60
-20
+65
+60
+60
+20
70
··
·
pVl'C
nA
nA
nA
pVIV
pVIV
dB
rnA
rnA
-65
-60
-60
-20
+65
+60
+60
+20
pVl'C
nA
nA
nA
pVIV
pVIV
dB
rnA
rnA
CONDITIONS
±V"" = ±34VDC
-Vee = 34VDC. +Vee = 10 to 40VDC
+Vee = 34VDC. -Vee = 10 to 40VDC
VeM = ±22V. F = DC
VCM = D. no load condition
VCM
= D. no load condition
[V,0(+25'C) - V,0(-55'C)] + 80
+7
+200
+200
+10
-10
-40
-35
-35
-7
-200
-200
76
lee-
4001
4001
4001
4001
4003
4003
4003
4005
4005
4
T, = +25'C
Vop**
lop··
Avs
4004
4004
4004
10:;::: 10A peak, 10kHz sine wave
RL = 2.60, 10kHz sine wave
RL=10kO'
-10
94
5
T,= +125'C
Vop
Avs
4004
4004
RL= 10kO
RL= 10kO
-30
94
+30
6
T, = -55'C
Vop
Avs
4004
4004
. RL= 10kO
RL = 10kO
-30
94
+30
7
T,= +25'C
SR
4002
RL= 6.50
1.35
OVLo
hs+
118-
1,0
+PSRR
-PSRR
CMRR
Icc+
-Vee = 34VDC. +V"" = 10 to +40VDC
+Vee = 34VDC. -Vee = 10 to 40VDC
VeM = ±22V. F = DC
VCM:;;:; 0, no load condition
VCM = 0, no load condition
+40
+35
+35
+7
+200
+200
··
70
+10
-10
-~ti
··
·
+20
+10
·
-20
·
·
·
·
90
90
90
··
·
·
+~u
·
·
V
A
dB
V
dB
V
dB
Vips
... Specification same as OPA501 "V" grade .
• * Performed in final electrical only.
3.5 Markin&. Marking is in accordance with MIL-M-385IO. The following marking is placed on each microcircuit as a
. minimum:
a. Part number (see paragraph 1.2)
b. Inspection lot identification code If
c.
d.
e.
f.
•
•..
BURR-BROWN®
Manufacturer's IdentificatIOn (IElElI )
Manufacturer's designating symbol (CEBS)
Country of origin
Electrostatic sensitivity identifier (~)
3.6 Workmanship-! These microcircuits are manufactured, processed, and tested in a workmanlike manner.
Workmanship is in accordance with good engineering practices, workmanlike instructions, 'inspection and test
procedures and training, prepared in fulfillment of Burr-Brown's product assurance program.
3.6.1 Rework'llrovisions. Rework provisions, including rebonding for the /883B product designation, are in
accordance with MIL-M-38510.
3.7 Traceability-! Traceability for the /883B product designation is in accordance with MIL-M-3851O. Each
microcircuit is traceable to the production lot and to the component vendor's component lot.
3.8 Product and llrocess change. Burr-Brown will not implement any major change to the design, materials,
construction, or manufacturing process which may affect the performance, quality or interchangeability of the
microcircuit without full or partial requalification.
3.9 Screening~ Screening for /883B Hi-ReI product designation is in accordance with MIL-STD-883, method 5008,
class B, except as modified in paragraph 4.3 herein.
Screening for the standard model includes Burr-Brown QC41l8 internal visual inspection, stabilization bake, fine leak,
gross leak, constant acceleration (condition A), temperature cycle (condition C), and external visual per MIL-STD-883,
method 2009.
11 A 4-digit code, indicating year and week of seal, and a 4- or 5-digit lot identifier are marked on each unit.
227
For the /883B product designation, all microcircuits will have passed the screening requirements prior to qualification
or quality conformance inspection.
3.10 Qualification. Qualification is not required. See paragraph 4.2 herein.
3.11 Quality conformance insp'ection. Quality conformance inspection, for the /883B .product designation, is in
accordance with MIL-M-3851O,except as modified in paragraph 4.4 herein. The microcircuit inspection lot will have
passed quality conformance inspection prior to microcircuit delivery.
4. PRODUCT ASSURANCE PROVISIONS
4.1 Samlliing and insllection. Sampling and inspection procedures are in accordance with MIL-M-3851O and MILSTD-883,-;:;i"ethod 5008, except as modified herein.
4.2 .Qualification. Qualification is not required unless specifically required by contract or purchase order. When so
required, qualification will be in. accordance. with the inspection routine of MIL-M-3851O, paragraph 4.4.2.1. The
inspections to be performed are those specified herein for groups A, B, C and D inspections (see paragraphs 4.4.1, 4.4.2,
4.4.3, and 4.4.4).
.
Burr-Brown has performed and successfully completed qualification inspection as described above. The most recent
report is available from Burr-Brown.
4.3 Screening~ Screening for the / 883B Hi-Rei product designation is in accordance with MIL-STD-883, method 5008,
class B, and is conducted on all devices. The following criteria apply:
a. Interim and final test parameters are specified in Table II.
b. Burn-in test (MIL-STD-883, method 1015) conditions:
(I) Test condition B or D
(2) Test circuit is Figure 3 herein for condition B
(3) TA = +125°C minimum
(4) Test duration is 160 hours minimum
c. Percent defective allowable (PDA). The PDA, for /883B product designation only, is 10 percent and includes
both parametric and catastrophic failures. It 'is based 'on failures from group A, subgroup I test, after cool-down
as final electrical test in accordance with MIL-STD-883, method 5008, and with no intervening electrical
measurements. If interim electrical parameter tests are performed prior to burn-in, failures resulting from
preburn-in screening failures may be excluded from the PDA. If interim electrical parameter tests are omitted,
all screening failures shall be included in the PDA. The.verified failures. of group A, subgroup I, after burn-in are
used to determine the percent defective for each manufacturing lot; and the lot is accepted or rejected based on
the PDA:
d. External visual inspection need not include measurement of case and lead dimensions.,
1kO
10kO
. +34VDC
JO.01I1F
100
100
-34VDC
FIGURE 3. Test Circuit-Bum-in and Operating Life Test (Condition B).
228
4.4 Quality conformance insJlection. Groups A and B inspections of MIL-STD-883, method 5008, class B, are
performed on each inspection lot. Groups'C and D inspections of MIL-STD-883, method 5008, class B are performed
as required by MIL-STD-883. A report of the most recent group C and D inspections is available from Burr-Brown.
4.4.1 GrouJl A insJlection. Group A inspection consists of the test subgroups and LTPD values shown in MIL-STD883, method 5008, and as specified in Table II herein.
4.4.2 GroUJl B insJlection. Group B inspection consists of the test subgroups and LTPD values shown in MIL-STD883, method 5008, class B.
4.4.3 GroUJl C insJlection. Group C inspection consists of the test subgroups and LTPD values shown in MIL-STD883, method 5008, class B and as follows:
a. Operating life test (MIL-STD-883, method 1005) conditions:
(I) Test condition B or D
'(2) Test circuit is Figure 3 herein for condition B
(3) TA ::: +125°C minimum
(4) Test condition is 1000 hours minimum
b. End point electrical parameters are specified in Table II herein.
4.4.4 GroUJl D insJlection. Group D inspection consists of the test subgroups and LTPD values shown in MIL-STD883, method 5008 and as follows:
a. End point electrical parameters are specified in Table II herein.
4.4.5 InsJlection of Jlackag~g~ Inspection of packaging shall be in accordance with MIL-M-3851O.
4.5 Methods of examination and test. Methods of examination and ~est are specified in the appropriate tables.
Electrical test circuits are as prescribed herein or in the referenced test methods of MIL-STD-883.
4.5.1 Voltage and current. All voltage values given, except the input offset voltage (or differential voltage) arc
referenced to the external zero reference level _of the supply voltage. Currents given are conventional current and
positive when flowing into the referenced terminal.
5. PACKAGING
5.1 Packagl!lg~quirements. The requirments for packaging shall be in accordance with MIL-M-3851O.
6. NOTES
6.1 No~ The notes specified in MIL-M-3851O are applicable to this specification.
6.2 Intended use. Microcircuits conforming to this specification are intended for use in applications where the use of
screened parts is required or desirable.
6.3 Ordering data. The contract or purchase order should specify the following:
a. Complete part number (see paragraph 1.2).
1,. Requirement for certificate of compliance, if desired.
6.4 Microcircuit grouJl assignment. These microcircuits are assigned to Technology Group I as defined in MIL-M38510, Appendix E.
6.5 Electrostatic sensitivity..:. CAUTION-these microcircuits may be damaged by electrostatic discharge. Precautions'
should be observed at all times.
229
7. ELECTRICAL PERFORMANCE CURVES
Typical at +25°C case and ±Vcc :;;: 28VDC unless otherwise noted.
OPEN-LOOP
FREQUENCY RESPONSE
120
100
iii"
80
-0
i
60
:5.E" 4 0
<:
+--
~
'I'..
1\ ~
Phase
I"
Ampli1Ude 7
0
~
o
-20
~
1"\.1 '
~
.~ 2.
"
'iii'
-120!
ii!
'8"
~
,4 0
E
E
0
-150'.!.
-180
-210
10 100 lK 10K lOOK 1 M 10M
Frequency (Hz)
.
a:
0
o
8
I\.
,
1
I
40
·i'" 20
~
10
g
6
'"
J!!
o
0;
E
20
~ o
-so
0.24
~
~
'"
tlJe ='2.2°C/W
~ 0.16
'[jj
"'~
a: 0.12
1.
is. 1.0
(J
'"
o 0.8
E
:2
RL 811
Av =+1'0'1
s
Tc = +2~,~C
{!.
4 6 10 20 4060
Frequency (kHz)
100
CURRENT LIMITING
_ ±6
~
r= ±5
II
11
~
<3
j
E
~
4
6
10
12
14
Current (A)
PULSE RESPONSE, Av = +1
Time (100I's/~lv)
230
/]Rsc=0.1211
~
,
±Rsc = 0.28n
r- b
~
o
-SO -25 0 25 50 75 100 125
Case Temperature (OC)
PULSE RESPONSE, Av = +1
Time (10pS/dlv)
~
r- r-....
tj ±1
I"""-2
±2
r- t----
o
l"-
0.04
0
±4
":; ±3
1\
()
25
50
75 100 125 150
Case Temperature (OC)
103
102
Frequency (Hz)
10
±7
c
"
75 100 125
~ 1.2
Ma~m~~'!G~~~~rted"~
~ 0.08
~
50
~ 1'::~~11~~~~~11
E_SJne Wave Output
'E
......
25
;!;.1
~
Tc = +25°C
.: 0.20
0
Case Temperature (OC)
CURRENT LIMITING
§:
-25
HARMONIC DISTORTION
Maxim um
Output
28VD
'"
0
0.28
cf100
C
40
iii
'5 O. 4
c.
.5
1
~'I...
POWER DERATING CURVE
120
J
j
34VDC
+Vcc
2
60
gt O.8
100 1K 10K 100K 1M
Frequency (Hz)
~+Vcc
rr-
.S
c.
S
!
" ....
1. 2
()
FULL POWER RESPONSE
~
.2 80
~~
~
10
c: 60
'Ii
is
E
2.
o
z
';:"1. 6
0
100
~
0;
~
o
~ 8C
OUTPUT VOLTAGE SWING
VS POWER SUPPLY VOLTAGE
~
" :i_\
iii"
:2.100
c:
f
-90
2.8
120
30
-60
INPUT BIAS CURRENT'
VS TEMPERATURE
COMMON MODE REJECTION
VS FREQUENCY
o
8. APPLICATION INFORMATION
8.1 Grounding~ Because of the high output current capability of the OPASOI/883B Series, the user is cautioned to
observe proper grounding techniques. Figure 4 illustrates a recommended technique.
Note that the connections are such that the load current does not flow through the wire connecting the signal ground
point to the power supply common. Also, power supply and load leads should be run physically separated from the
amplifier input and signal leads.
FIGURE 4. Proper Power Supply Connections.
8.2 Supp"lyJ?YI~assing! The OPASOI power supplies should be bypassed with SOILF tantalum capacitors connected as
close as possible to pins 3 and 6. These bypass capacitors should be connected to, the load ground rather than the signal
ground.
8.3 Current limits. OPASOI amplifier is designed so that both positive and negative load current limits can be set
independently with external resistors +Rsc and -Rsc respectively. The approximate value of these resistors is given by
the equation:
Rsc = [(0.6S + ILIMIT) - 0.0437] ohms
ILIMIT is the desired maximum current in amperes. The power dissipation of the current limit resistor is:
=
Pm" Rsc (ILIMIT)2 watts
Rsc is in ohms and ILIMIT is in amperes.
Current limit resistors carry the full amplifier output current so lead lengths should be minimized. Highly inductive
resistors can cause loop instability. Variation in limit with case temperature is shown in the Typical Performance
Curves, paragraph 7.
'
The amplifier should be used with as Iowa current limit as possible for its particular application. This will minimize the
chance of damaging the amplifier under abnormal load conditions and will increase reliability by limiting internal
power dissipation.
The c.urrent limits may be used to generate other functions such as constant current supplies and torque or stall current
limits for servomotor applications.
8.4 Heat sinking~ The OPASOI requires a heat sink to limit output transistor junction temperature (TJ) to an absolute
.
maximum of +200°C. The steady-state thermal circuit is illustrated in Figure S.
231
1--.,.--...........- - - - ' 0
Junction
Case
Heat Sink
L-----'--------o
FIGURE 5. Simplified
Steady-~tate
Ambient
Heat Flow Model.
Junction temperature (Tl) is found from the equation:
, Tl = Po (Ole + Oes + OSA) + TA
where Po = average amplifier power dissipation (W)
Ole = junction-to-case thermal resistance (OC/'W)
Oes = case-to-sink thermal resistance (OCj W)
OSA = sink-to-ambient thermal resistance ("CjW)
TA = ambient temperature (0C)
For most heat sink calculations the quiescent power dissipation is very low «lW) and can be disregarded with only a
small error.
The maximum size heat sink can be found as follows:
Example: Find the maximum thermal resistance (smallest heat sink) that can be used for an OPA501 with
±Vee = '28VDC. Output voltage is + JOVDC across a JOn resistor and ,ambient temperature is +50°C:
OSA = [(Tl - TA) + PD] - Oes - Ole
As large a heat sink as possible should be used. Oes depends on the flatness of the heat sink, the thermal compound
used, and the roughness of the mating surfaces. Typical values are between O.l°Cj Wand O.3°Cj W for TO-3 package
properly mounted on a heat sink.
The OPA501 mounting flange is electrically-isolated and can be mounted directly to a heat sink without insulating
washers or spacers.
The output transistor thermal resistance (Ole) is a function of the output current pulse width, pulse shape, and duty
cycle. Long duration pulses allow the junction temperature to approach its steady state value while shorter pulses cause
a lower peak junction temperature due to the junction's thermal time constant. Heat is conducted away from the
junction rapidly so that as the duty cycle decreases, junction temperature decreases.
Steady state Ole is rated at 2.2°Cj W maximum. In applications where the amplifier's output current alternates between
output transistors-for example, an AC amplifier-the transistor Ole will depend on frequency as shown in Figure 6.
Duty Cycle = 0,5 for Each Transistor
1.2
1.0
u
.;;
."
-
0.8
Q)
.!:!
E
0
z
0.6
I"'
0.4
0.2
0.1
10
100
lk
10k
Frequency (Hz)
FIGURE 6. Effective Ole for Applications Where Output Current Alternates Between Output Transistors.
232
8.5 Safe operating area (SOA). In addition to the limits imposed by power dissipation, the amplifier's output
transistors are also limited by a second breakdown region. This occurs because of increased emitter current density due
to current crowding at higher operating voltages. Both the dissipation and second breakdown limits depend on time
and temperature. Figure 7 shows each output transistor's SOA at a case temperature of +25°C.
10
"8 MaXimum Specified I t I\,
Current
TI"'6
Power _ ,
DIssipation
4
'\~ ~-
"-
(T1 '--'" ~ ~\
~
tecond Breakdown"
c
g 1.0 t-- T
It---.
Limit
= +25°C
CASE
u 0.8 I-- TJUNCTION = +200°C
"5
Co
0.6 I- 8,e = 2.2°C/W
"5
0
\ ,~
0.4
0.1
\1
MaXimum"}U Grade
Specified
I
Voltage
V Grade
I
I
I
I
I
I
6 8 10
'",
~~ ~
,
0.2
"%,
I
I
20
40
,m,
I
6080100
Voltage Across Output Transistor (V)
FIGURE 7, Transistor Safe Operating Area at +25°C Case Temperature.
Limits for short,pulse widths are substantially greater than for steady state (DC). At a case temperature of + 125°C the
SOA limits are reduced (see Figure 8). The SOA shown in these curves is based on a conservative linear derating of
both the power dissipation and the second breakdown region.
10
8 I
I "
~,MaXimum
6
Specified
~
~
'-
TeASE = +125°C
TJUNCTION = +200°C
1,0
5
u 0,8
8JC
"
i\.
_'-
"- I\.
138
60
32
16
V
0
-10
o
PMI U12M4T, Motor, No Load
f = 4Hz, Sine Wave
±Vcc 28V, Tc 2S'
Av= +10
=
PMI U12M4T Motor, No Load
f = 4Hz, Square Wave
±Vcc = 28V, Tc = 2S'
Av=+10
=
FIGURE 12. DC Servomotor Load Line,
FIGURE 13, Servomotor Dnve-"P1ugging':
+S
A
0
-S
+10
V
0
-10
PMI U12M4T Motor, No Load
f = 4Hz, Sine Wave
±Vcc = 28VDC, ±Rsc = 0.IS0
Tc=2S',Av=+10
FIGURE 14, Servomotor Drive With Current Limit,
236
BURR-BROWN®
PWR7XX Series
1E3E31
5W Rated Output Power
REGULATED DC/DC CONVERTER SER~ES
FEATURES
o Linear Output Regulation
o Wide Operating Temperature Range:
• Isolation Voltage Tested per UL544. VDE750. and
CSAC22.2 DIelectric Withstand Requirement
• Barrier Leakage Current 100% Tested at 240VAC
• Single Channel
• iiingie or jju~i iillgui~illu uuillUi~
III
-40°C to +IOO°C
Input and Output Filtering
DESCRIPTION
The PWR 7XX Series offers a large selection of
regulated 5W DC/DC converters for use in such
diverse applications as process control, telecommunications, portable equipment, medical systems, airborne and shipboard electronic circuits, and automatic test equipment.
Thirty-six models allow the user to select input voltages ranging from +5VDC to +48VDC and output
voltages of +5, +12, +15, ±5, ±12, or ±15V.
CONNECTION DIAGRAM
Surface-mounted devices and manufacturing processes are used in the PWR 7XX Series to give the
user a device which is more environmentally rugged
than most DC/DC converters. The use of surfacemount technologies also gives the PWR7XX Series
superior isolation voltage. Each PWR7XX Series
unit is tested in compliance with the dielectric
withstand voltage requirements of UL544, VDC750,
and CSAC22.2.
ORDERING INFORMATION
T
Device FamiIY _ _ _ _ _ _ _ _
~_'WR 7XX ;G
PWR indicates DCI DC converter
Model Number
Selected from table of Electrical
Characteristics
Reliability Screening - - - - - - - - - - '
No designator indicates standard manufacturing
processing
I G indicates Level I screening-burn~in only
IT indicates Level II screening-stabilization
bake. temperature cycling, and burn-in
TYPICAL APPLICATIONS
3
3
2
5~--"'"
(S~ln~gl:-eO::-U~IP~UI~M:-od~el')
5
(Dual Oulpul Models)'
Inlernalional Airport Industrial Park· P.O. Box 11400· T~cson. Arizona 85134· Tel. (602) 146·1111 . Twx: 910-952·1111 • Cable: BBRCORP • Telex: 66·6491
PDS-662
237
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS f1I
Input Cumint
Regulation
Nominal
Input Voltege
(VDC)
Rlted
Output Voltege
(VDC)
Rated
Output Current
(mA)
NoLoed,
typ (mA)
RltedLoed,
typ (mA)
Reflected
Ripple Current,
typ(mA) p-p
typ ('10)
Load,
typ('Io)
Elliciency,
mln(%)
PWR700
PWR701
PWR702
PWR703
PWR704
PWR705
5
5
12
15
±5
±12
±15
1000
417
334
±500
±209
±167
168
168
168
168
168
166
1600
1535
1490
1560
1490
1450
30
30
30
30
30
30
.02
.02
.02
.02
.02
.02
.04
.04
.04
.04
.04
.04
61
63
65
62
65
67
PWR706
PWR707
PWR708
PWR709
PWR710
PWR711
12
5
12
15
±5
±12
±15
1000
417
334
±500
±209
±167
38
36
38
38
36
38
620
550
535
640
550
535
10
10
10
10
10
10
.02
.02
.02
.02
.02
.02
.04
.04
.04
.04
.04
.04
61
63
65
62
65
67·
PWR712
PWR713
PWR714
PWR715
PWR716
PWR717
15
5
'12
15
±5
±12
±15
1000
417
334
±500
±209
±167
35
35
35
35
35
35
510
490
470
520
.02
.02
.02
.02
.02
.02
.04
.04
.04
.04
.04
.04
61
63
65
455
10
10
10
10
10
10
PWR718
PWR719
PWR720
PWR721
PWR722
PWR723
24
5
12
15
±5
±12
±15
1000
417
334
±500
±209
±167
33
33
33
33
33
33
320
305
300
330
310
305
20
20
20
20
20
20
.02
.02
.02
.02
.02
.02
.04
.04
.04
.04
.04
.04
61
63
65
62
65
67
PWR724
PWR725
PWR726
PWR727
PWR728
PWR729
28
5
12
15
±5
±12
±15
1000
417
334
±500
±209
±167
33
33
33
33
33
33
280
270
260
280
270
260
20
20
20
20
20
20
.02
.02
.02
.02
.02
.02
.04
.04
.04
.04
.04
.04
61
63
65
62
65
67
PWR730
PWR731
PWR732
PWR733
PWR734
PWR735
48
5
12
15
±5
±12
±15
1000
417
334
±500
±209
±167
31
31
31
'31
31
31
165
160
155
165
155
155
10
10
10
10
10
10
.02
.02
.02
.02
.02
.02
.04
.04
.04
.04
.04
.04
61
63
65
62
65
67
Model
I
460
COMMON SPECIFICATIONS f1I
Parameter
INPUT
Voltage Range
Condition.
VrN = 5V Models
VrN = 12V Models
VrN = 15V Models
VrN = 24V Models
VrN = 48V Models
4.65
11.00
13.70
21.00
25.00
44.50
60 Seconds, 60Hz
1000
3000
VIN
ISOLATION
Rated Voltage
Test Voltage
Resistance
Min
= 28V Models
MIx
Unit.
6
15
17
27
31
53
VDC
VDC
VDC
VDC
Leakage Current
240V rms, 60Hz
OUTPUT
Voltage Accuracy
Voltage Balance
Temperature Coelliclent
Ripple and Noise
Dual Output Units Only
-25·C ,,; T. ,,; +65·C
BW = ec to 10MHz
V••
Gn
25
±C.5
±0.3
±0.01
30
-25
-40
.,.55
vec
vec
vec
10
170
Capacitance
TEMPERATURE
Specification
Operation
Storage
Typ
±1
pF
IIA,rms
'10
%
%/·C
mV, p-p
+85
+100
+125
·C
·C
·C
NOTE: (1) Specifications typical at T. = +25·C, nominal input yoltage, and rated output current
unless otherwise noted.
238
Line,
62
65
67
+VOUT
V'N
VOUT
(Bottom'View-"B" Package Option)
IT
I
0.410
- - Max
(10.41)
~LT'"-0~.0~2-0-±-O-.0-03-------"'I1'[~ 0.170
+-i-++-H
11.02 ± 0.081
+VOUT ....
"+VIN
Min
(4.32)
(Side View-"B" Package Option)
COM· .....l-+--+---I-l-l
H-+++-l--+-V'NH-++--i-I-+++-l---l--l
H-+++-l-++H+-VoUT ot--I-++-!-+-l
(Bottom View-"A" Package Option)
COM·to
iT
=.± (~:.:~)
I
U
Max
o.o4oL-±-o.-oo-3-=u=-..-----....
0.170 Min
(1.02 ±0.08)
(4.32)
(Bottom View-"C" Package Option)
(Side View-"A" Package Option)
IT (~:.:~)
NOTES:
All dimensions are in inches (millimeters)
I
GRID: 0.100 Inches (2.54 millimeters)
* Common
Max
_L-TTF....,'-0.-04-0-±-0.-0-03--------rr~=t 0.170 Min
pins are niissing on single output models.
MATERIAL: Units are encapsulated in a low thermal·resistance
molding compound which has excellent chemical resistance,
wide operating temperature range, and good electrical
properties under high humidity environments. Lead material
is brass with hot·solder·dipped surface to allow ease of
solderability.
(1.02 ±0.08)
(4.32)
(Side View-"C" Package Option)
a
ABSOLUTE MAXIMUM RATINGS
Input VOltage ......................... : ........ 120% of nominal
Output Short-Circuit Duration ........................ 5 seconds
Internal Power Dissipation . ....................... : ........ 3.5W
Lead Temperature (soldering, 10 seconds) .••.......•.... +300'C
Junction Temperature . ................................. +150°C
~ackage Therma,1 Resistance. Junction-to·Ambient, 9JA • •• 15°C/W
239
APPLICATION NOTES
. TESTING ISOLATION BARRIER
CHARACTERISTICS
The insulation and spacings of the PWR 7XX Series are
100% tested to meet the dielectric withstand requirements
of UL544, paragraph 31. A 60Hz essentially sinusoidal
potential is applied between the primary and secondary
for a period of one minute. The potential used for this
test is twice the maximum rated voltage plus 1000V. For
the PWR7XX Series the test voltage is 3000V peak.
Dielectric withstand testing is intended to be done at the
manufacturer's site only. This test will not be repeated.
Exposing the dielectric material of the isolation barrier
to repeated testing causes microscopic carbonizing of the
dielectric, resulting in a weakened barrier. A low resistance
path will eventually be created across the barrier.
PRESERVING ISOLATION CHARACTERISTICS
If intrinsic safety is required, care should be taken in the
layout and assembly of the printed wiring board (PWB)
to avoid degrading the isolation barrier of the PWR7XX.
Precautionary measures include cleaning the PWB prior.
to installing the PWR 7XX to prevent trapping contaminates under the unit. Use nonconductive spacers to keep
the PWR7XX off the PWB. Use epoxy solder mask to
isolate PWB conductive traces which must run under or
close to the PWR 7XX. In the layout of the PWB, avoid
placing PWB traces under the unit. Do not use conductive
inks on the PWB under the unit; e.g., inks used in.
inspection stamps or component identification marking.
DC/DC
Converter
FIGURE 1. Recommended Power Distribution.
MEASURING NOISE
Measuring the input and output noise performance of ~
DC! DC converter is a very difficult task that should be
attempted only in a controlled laboratory test environment
due to extraneous noise sources.
Figure 2 illustrates two recommended methods for testing
output voltage ripple and noise. Reflected input current
ripple and noise should be measured with a high performance current probe. Measuring input current and
noise into a "known" impedance with a voltage probe
should be avoided.
Output
~Toscope
a. Preferred Method
Grounded Probe TIp
OUTPUT POWER DISTRIBUTION
Figure 1 shows the recommended method of connecting
multiple loads to the PWR 7XX. Single-point power
distribution prevents ground loops and interaction between
parallel load circuits.
b. Altemate Method
FIGURE 2. Recommended Noise Measurement Methods.
240
PWR1011
BURR-BROWN®
l'ElE31
Four-Channel, Dual-Outpuit, SYl1u:hroli'ilozalbl~e
UNREGULATED DC/DC CONVERTER
FEATURES
APPUCAT~ONS
() Synchronizable
CD All Outputs Isolated
CD Output Power to 3W
• High Isolation Voltage-l000Vpk
.. Six-Sided Shielding
o Input and Output Filtering
() Low Profile Package-O.4" High
o Power lor High Resolution Data Acquisition
CD Precision Test Equipment
• Spot Regulator
o Process Control
o Portable Equipment
o Multiple Power Supplies
DESCRIPTION
The PWRI017 is a four-channel, dual-output unregulated DC! DC converter designed for low noise
applications where high efficiency and switching
synchronization are required.
Any unit whose slave pin is connected to another
unit's master pin will cause the oscillators to lock
together. The PWRI017 may also be driven from a
system master clock. The free running switching
frequency is 250kHz.
The PWRI017 has four isolated plus and minus
output voltages approximately equal to the magnitude of the input voltage. It operates over an input
voltage range of IOVDC to 18VDC. Rated output
current for the PWRIOl7 is 25mA for all outputs.
CONNECTION DIAGRAM
Osc. Out
4.
+V'N 3411
2'
-V'N
Sync. In HI
,-c
o
rt~t;;tl
l~_ ..
Ch.l
N
"10
Ch.2·
T
R
o
'.
,-- ,,9
];
~
:L:
'F+-::+"
uvlO
151614
MECHANICAL
2.000 ±0.01S
_0.410
(10.41)
AI
II
TL-y-r-I'
"'T__..-~102so±0080
IIII
Ch.3
,~
-- , . 12
:
~13
L__
11
J:....r~: [
Ch.4
Isolation voltage between the input and any of the
four output circuits is 1000Vpk continuous. The
same isolation specification applies between any of
the four dual outputs,
Six-sided shielding suppresses electromagnetic radiation which could disturb sensitive analog measurements or interfere with system timing signals. Filtering the PWRI017 input and outputs minimizes the
effects of electrical noise on the source and loads of
the converter.
Each PWRIOl7 is tested in compliance with UL544,
VDE750, and CSA C22.2 dielectric withstand specifications. In addition, barrier leakage current is
100% tested.
I~ (~.3S ±2:03)
0.040 ±0.002--!
(1.02 ±O.OS)
ill
It)
~
-
~~~
·8
N!!?
I ..
(50.80 ±0.38) ""
~5
8
6 7
9
10
3
:1• •
~161S14
11
_;ma3
12
NOTE: All dimensions are in inches (millimeters).
Grid
= 0.100" (2.S4mm).
International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734 . Tei. (6021 746·1111 • Twx: 910-952·1111 • Cable: BBRCORP . Telex: 66·6491
PDS-706
241
. SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL
At TA :;; 25°C. VIM :;; 15VDC, ILoAD = ±25mA and in free running mode unless otherwise noted.
PWR1017
PARAMETER
CONDITIONS
INPUT
Rated Voltage'"
Voltage Range
Input Current
NORM
MIJII
MAX
UNITS
15
10
ILoAD :;;
ISOLATION
Rated Load
Ratings apply input-to-output
and channel-ta-channel
Test: 60sec, 60Hz, 3000V, pk
Rated Voltage
Resistance
70
285
80
= Rated Load
kOAD
Ripple Current
V,sa
OUTPUT
Rated Voltage
Voltage Range
~
10
15
0.9
240VAC, 60Hz
ILoAD
ILOAC
Rated Current
=OmA
= Rated Load
Each output
Total of all outputs
Each output
Totat of all outputs
10VDC V'N 18VDC
0> ILOAD > 25mA
Current Range.
<
Line Regulation
Load Regulation
Ripple Voltage
<
kOAD;;;:;
kOAD
350
1000
Capacitance
Leakage Current
±15
±16.5
±16
±14.25
±25
200
0
0
VSYNC, max
Max dBviation from -VIN
<
<
VDC
VDC
VDC
mA
mA
mA
mA
mVlmV
mVlmA
mV, pk
mV, pk
±18
±15.75
±40
500
1.16
12.5
±10
0
VSYNC> 6.4Vp-p
400kHz fSYNC 700kHz
VDC
GO
pF
pA
3
= Rated Load
SYNCHRONIZATION'"
f SYNC Range
VSYNC Range
Oscillator Output Fanout
VDC
VDC
mA
mA
mA, p-p
18
kOAO=O
±100
400
6.4
VSYNC Duty Cycle
5
TEMPERATURE
Specification
Operating
Storage
-25
-40
-55
50
700
36
2
50
60
kHz
V, p-p
Synch Inputs
V
+85
+100
+125
'C
'C
'C
Input Voltage .....•........ 18VDC
Output Current ............ 500mA
Output Short Circuit
Duration ............ Momentary
ORDERING INFORMATION
PWR 1017.X
Device Family
T
PWR indicates DC/DC converter
Model Number--------'
Reliability Screening ------~
No designator indicates standard
manufacturing process
/G indicates Level I screeningburn-in only
IT indicates Level II screeningstabilization bake, temperature
cycling, and burn-in
Control Circuitry Block Diagram
%
NOTE: (1) Other voltages available on request. (2) Operating frequency (10 sync mode) ~ fSYNcl2.
Oscillator frequency (pin 4, free running) ~ 2 (f operation). Oscillator frequency (pin 4, sync mode) ~ fSYNC.
NOTE: Care should be taken when the synchronization input pin is not used, in order to avoid the
possibility of noise pick-up and false PLL locking.
This could destroy the unit and/or any other units
that are coupled to its synchronization output (pin
4). This protection may be accomplished byeither
tying the synchronization pin to -VINo or clipping
pin 1 off flush with the module surface. Tying pin 1
to -VIN is preferred.
TYPICAL PERFORMANCE CURVES
OUTPUT VOLTAGE VS
LOAD CURRENT
INPUT VOLTAGE VS
OUTPUT VOLTAGE
TAC' +25'C
17
450
"-
10
__
~
12
__
~
____
14
~
16
Input Voltage (VDC)
. T. ~ +25'C, V'N ~ 15VDC; each output
loaded to indicated value.
T. ~ +25'C, V'N ~ 15V; each output
loaded to indicated value.
25r----r----r----r--~
5~
INPUT CURRENT VS
OUTPUT CURRENT
__
~
18
13
o
~
"
.s
E
f'
~
::I
250
()
'5
c.
E 150
50
10
20
30
Load Current (mA)
242
/
_350
«
40
/
o
V
10
/
20
30
Load Current (mA)
40
TYPICAL PERFORMANCE CURVES (CONT)
INPUT CURRENT VS
INPUT VOLTAGE
TA
~
TA ~
+2S'C, I, '" ±2SmA
320
18
;;( 300
.§.
E
~ 280
:J
o
:;
Co
-=
/
/
V
V
,;
,;
Cl
l!! 16
g
:;
14
14
12
16
Input Voltage (VDC)
18
ISYNC VS OUTPUT VOLTAGE
AND INPUT CURRENT
+2S'C, V,N = lSVDC, I, = ±2SmA, VsyNc
-60
~
Z
o
10
'"
o a:
..
> ..
'S at
~£ - 8 0 t - - + -
,;
-
I
50
25
75
Load Current, I, (mA)
,;
~15.---1---1--~~
g
3
.,
:;
Load Current, I, (rnA)
TEMPERATURE
CHARACTERISTICS
VIN = +15V, !LOAD = ±25mA, free running.
. ::,
Cl ""
g
\
m~
a
:D ;;
:!'3
Mfr
[OHC /[OIlC CO U\lJVlE lR1l'lE [p1
o
Isolation Voltage 500 VOC
o
Barrier leal(age Current 100% Tested at 240VAC
o
low Cost
o Wide Operating Temperature Range
o
,0
The PWR5038 offers a triple output 2.75W DC to DC
converter for use in such diverse applications as process
control, telecommunications, portable equipment
medical systems, airborne and shipboard electronic
circuits, and automatic test equipment.
This model gives the user an output voltage of +5 and
± l5VDC with an input voltage of +5VDC.
Input and Output Filtering
Surface-mounted devices and manufacturing processes
are used in the PWR5038 to give the user a device
which is more environmentally rugged than most DC
to DC converters. The use of surface-mount technology also gives the PWR5038 a low cost reflected in our
low prices.
Six-Sided Shielding
CONNECTION DIAGRAM
ORDERING INFORMATION
0+
T
PWR 5038 /G
Device Family
--,-PWR indicates DC! DC converter
Model Number------------.J
VOUT2
@common,
G)-Vou.,
Reliability Screening _ _ _ _ _ _ _ _ _ _..J
No designator indicates standard manufacturing
processing
/ G indicates Level I screening-bum-in only
/ T indicates Level II screening-stabilization
bake, temperature cycling, and burn-in
~+Vour,
'------_.-
0-VOUT1
TYPICAL APPLICATION
3~
Q'
1
Input
Voltage
I
Load
I
I
LODd
I
4
5----1
6~
I
Load
I
7----1
Inlernalional Airporllnduslrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. 16021746·1111 . Twx: 910·952·1111· Cable: BBRCORp· Telex: 66·6491
PDS-738
245
SPECIFIC~TIONS
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Ta '"
Specifications Typical at
+25 deg C., nominal input voltage
and rated output current unless otherwise noted.
PARAMETER
INPUT
VOLTAGE
RANGE
CURRENT
RIPPLE
CURRENT
CONDITION
MIN
TVP
5.00
5.25
4.75
NO LOAD
FULL LOAD
150
FULL LOAD
60
1.0
OUTPUT 1
VOLTAGE
150
RIPPLE
-25 to + 85 CEG C
I LOAD
SOmAta 150 rnA
INPUT VOLTAGE
4.75 to 5.25 V
OCto 10 MHz
4.75
UNT
vae
vae
mA
A
mA
pop
5
CURRENT
ACCURACY
MSX
BURR-BRO\NN8
mV
pop
±,5
67
-25
vae
mA
1.625 ±0.015
(41.28 ±0.38)
to +85 DEG C
MarkedwitJ
specific model
humber ordered.
I LOAD
33 mAteS7 rnA
INPUT VOLTAGE
4.75 to 5.25 V
RIPPLE
IElElI
PWR5038
QUTPUT2
VOLTAGE
CURRENT
ACCURACV
MECHANICAL
VDe
mA
5.25
20
Input Voltage................ 120% X rated voltage
Output Short..Circuit Duration. . . . . . . .. Momentary
Internal Power Dissipation ......•........•..
4W
Junction Temperature .......................
2W
Package Thermal Resistance ....•....•..•. +l50°C
Lead Temperature
(soldering, 10 seconds) ...........•..•.. +300'C
13.5
16.5
300
OCto 10 MHz
mV
pop
(Top VIew)
ISOLATION
VOLTAGE
RESISTANCE
CAPACITANCE
LEAKAGE
CURRENT
vac
500
Mn
'0
45
3
pF
4
Viso = 240 VAC
5
pA
+85
+100
+125
"C
"C
"C
5
TEMPERATURE
SPECIFICATION
OPERATION
STORAGE
-25
-40
-55
2
1
6
7
(Bottom View)
t
0.410 Max
W (Side View) • U
_11_
0.020 ±0.002
(0.51 ±0.05)
(1°r:
O~
Min=--J
(4.32)
NOTES:
All dimensions are in inches (millimeters) .
GRID: 0.100 inches (2.54 millimeters)
MATERIAL: Low thermal resistance molding
compound which has excellent chemical
resistance, wide operating temperature range
and good electrica'i properties under high
humidity environments. Lead material Is
• brass with a hot~solder-dlpped surface to
allow ease of solderability.
246
BURR-BROWN®
PWR5104
PWR5105
IElElI
9W Rated Output Power
REGULATED DC-TO-DC CONVERTER
FEATURES
• LOW COST
• ±12VDC AND ±15VDC OUTPUTS
.i.iiW i1iii8E
-- ..
IDIIT Alln nllTDIlT r:IITr:IIINI!
I I • • U I h i . . . . . . . . . . . . . . . . . . . . . . . _ ...... _
• LINEAR OUTPUT REGULATION
• WIDE OPERATING TEMPERATURE RANGE:
-40°C TO +100°C
• SIX-SIDED SHIELDING
• BARRIER LEAKAGE CURRENT 100% TESTED AT
240VAC
DESCRIPTION
The PWR5104 and PWR5105 offer respectively
±12VDC and ±15VDC ouputs of regulated 9W
power driven from your +5V system bus. These
units are designed for use in such diverse applications
as process control, telecommunications, portable
equipment, medical systems, airborne and shipboard
electronic circuits, and automatic test equipment.
The PWR5104 and PWR5105 offer a low cost
alternative to the models currently in the market. In
addition these models utilize high frequency switching in order to maintain a low EMI and RFI
environment. Both models incorporate input and
output filtering along with six-sided shielding to
keep unwanted noise from your circuit.
Surface-mounted devices and manufacturing processes are used in the PWR5104 and PWR5105 to give
you a device which is more environmen~ally rugged
than most DC-to-DC converters. These manufacturing and design technologies also give superior
isolation voltage. The PWR5104 and PWR5105 are
tested in compliance with the dielectric withstand
voltage 'requirements of UL544, VDC750, and
CSAC22.2.
ORDERING INFORMATION
CONNECTION DIAGRAM
-VIN
(!::
G)-VOUT
(!)common
+VIN~
0 +VOUT
T
PWR 510X/G
Device Family
.
PWR indicates DC/DC converter
=r
Model Number-----------'
Selected from table of Electrical
Characteristics
Reliability Screening--------.J
No designator indicates standard
manufacturing processing
IG indicates Levell screening-burn-in only
IT indicates Level" screening-stabilization
bake. temperature cycling. and bUrn-in
Inlernalional Alrporllnduslrlal Park· P.O. Box 11400 . Tucson, Arizona 85734 • Tel. (6021 746·1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 66·6491
PD5-713
247
I
SPECIFICATIONS
ELECTRICAL
Specifications typical at TA
otherwise noted.
::;
+25°C, nominal input voltage and rated output current unless
MECHANICAL
PWR5104/5105
PARAMeTER
INPUT
Nominal Voltage
Voltage Rangel1l
Input Current
Input Current
Ripple Current
CONOITIONS
MIN
5.25
60
2400
5
±12
±15
±0.5
±0.3
-25'C to +85'C
2570
±1.0
±0.01
BW = DC to 10MHz
70
6
0.02
0.04
75
UNITS
I
r--
2.000 ±0.Q15
35
'"
;;
ci
+i
%
%
%/oC
rnA
rnA
mV,p-p
§~
N!e.
~~1
Top View
"A" Package Option
• t " . , ., .; ••• t,f+ h
:• :t :.............
: : : : : : : :. :...:-: : !:~2
2.
* ..... ..
~
10
50
15
GENERAL
Switching Frequency
TEMPERATURE
Specification
Operation
Storage
I
VDC
VDC
rnA
rnA
mA,p-p
%
%
%
750
240Vrms, 60Hz
.
(50.80 ±0.38) - - - - - ,
VDC
VDC
±375
±300
Efficiency
ISOLATION
Rated Voltage
Resistance
Capacitance
Leakage Current
MAX
5.00
4.75
No load
Rated load
At rated load
OUTPUT
PWR5104
PWR5105
Rated Voltage
Rated Voltage
Accuracy
Voltage Balance
Temperature
Coefficient
PWR5104 Rated Current
PWR5105 Rated Current
Ripple and Noise
Line Regualtion
Load Regulation
TYP
VDC
GO
pF
pA, rms
kHz
50
,
•
~
. . . . . . . . . "'t
..
+
t
, . . . . . . . . . . . . . _"'t
.......... ,+VOUT.·· ....... .
~ ..... -+ ..... ....
t ~ .,. -+ •
~COt".·.·~
• • '.' ...........
r'" .. ..
· • • . . • +VIN·
......
, ..
· • . • . • -V'N·· ..
-t
• ...... • ............. ·
•••••••••• t··
.. • ..
-+··
• . • . • • • • --VOUTe· .... ..
. . . . . . . . . . . . . . . . T .... ..
-25
-40
-55
+85
+100
+125
'C
'C
'C
..........
t···· t · 'T
••••••••••••••••• T
Bottom View-"A" Package Option
NOTE. (1) Other voltage ranges available. Conlact lactory.
ABSOLUTE MAXIMUM RATINGS
~
u
L.._ _,.,..._ _ _....,.,.
,--u--
Input Voltage ............................. 110% of nominal
putput Short-Circuit Duration ............... 15 seconds
Internal Power Dissipation .......................... 4.0W
Lead Temperature (soldering, 10 seconds)..... +300·C
Junction Temperature ............................. +150·C
Package Thermal Resistance,
Junction-to-Ambient, IIJ •.•..••••.•••.•.••.••••• 15°CIW
LOMO ±0.OO3
.
0'410M
(10.41)
ax
0.170 Min
(4.32)
(1.02 ±0.08)
Side View-"A" Package Oplion
NOTES:
All dimensions are in inches (millimeters)
GRID: 0.100 inche& (2.54 millimeters)
MATERIAL: Units are encapsulated in a low thermal
resistance molding compound which has excellent
chemical resistance. wide operating temperature
range, and good electrical properties under high
humidity environments. Lead material is brass with
a hot-solder-dipped surface to allow ease of solderability.
248
TVP~CAl
PERfORMANCE CURVES
EFFICIENCY VS LOAD
(at Nominal Input Voltage)
EFFICIENCY VS INPUT VOLTAGE
(at Full Power Out)
100
80
90
70
r----
80
l
rJc
w
70
.!2
iij
20
----
60
~
,..
u
c
w
;g
~~
iii
20
10
10
o
+4.50
+4.75
+5.00
+5.25
0
+5.50
Input Voltage (V)
41
9
INPUT CURRENT VS TEMPERATURE
I
~
~
0;
5.0
\
O
2.5
0
12
+85'C
7.5
~
0
9
Power Out (W)
OUTPUT POWER DERATING
10.0 I
a.
"5
S-
v
~
+25
+50
+75
\
~5~0~----2~5~----~----+~2~5----~+~570-----+~7~5----+~1~00
+100
Temperature ('C) At Nominal V,N (5V)
Temperature (Oe)
All Burr-Brown DCI DC converters are manufactured
using stringent in-process controls and quality inspections,The custo~er may also choose one of two additional levels of screening to meet specific requirements,
The advanced reliability program is designed to reduce
infant mortality, system rework, field failures, and equipment downtime,
Standard Manufacturing Process
IG-Levell Screening
Incoming Material Inspection
Per MIL-S-19500
Standard Manufacturing Process
I
Burn-in, MIL-STD-8B3,
method 1015, 160 hours, T. = + 125'C
Stabilization Bake, MIL-STD-BB3,
method 1008, 24 hours, T. = + 125'C
100% Internal Visual Inspection
Final Electrical Test
Temperature Cycling, MIL-STD-883,
method 1010, Condition B (-55'C to +125'C)
100% Electrical Test
OA Lot Acceptance Testing, AOL = 0,5
Component Attachment
I
I
I
I
I
IT-Level II Screening
Standard Manufacturing Process
I
I
I
I
Burn-in, MIL-STD-883,
method 1015, 160 hours, T. = +125'C
100'10 Final Electrical Test
Final Electrical Test
Seal
T
I
I
I
External Visual
OA Lot Acceptance Testing, AOL = 0,25
I
OA Lot Acceptance Testing, AOL = 1,0
249
MEASURING NOISE
Measuring the input and output noise performance of a
DC! DC converter is a very difficult task that should be
attempted only in a controlled laboratory test environment due to extraneous noise sources.
Figure 2 illustrates two recommended methods for testing
output voltage ripple and noise. Reflected input current
ripple and noise should be measured with a high performance current probe. Measuring input current and
noise into a "known" impedance with a voltage probe'
should be avoided.
APPLICATION NOTES
PRESERVING ISOLATION CHARACTERISTICS
If intrinsic safety is required, care should be taken in the
layout and assembly of the printed wiring board (PWB)
to avoid degrading the isolation barrier of the PWR51OX.
Precautionary measures include cleaning the 510X prior
to installing the PWR510X to prevent trapping contaminates under the unit. Use nonconductive spacers to keep
the PWR510X off the PWB. Use epoxy solder mask to
isolate PWB conductive traces which must run under or
close to the PWR51OX. In the layout of the PWB, avoid
placing PWB traces under the unit. Do not use conductive inks on the PWB under the \lnit; e,g., inks used in
inspection stamps or component identification marking.
~
/
OUTPUT POWER DISTRIBUTION
To Scope
Grounded Probe Tip
Figure I shows the recommended method of connecting
multiple loads to the PWR510X. Single-point power
distribution prevents ground loops and interaction between parallel load circuits.
a. Preferred Method
b. Alternate Method
FIGURE 2. Recommended Noise Measurement Methods.
DC/DC
Converter
FIGURE I. Recommended Power Distribution.
250
SDM862
SDM863
BURR-BROWN®
113131
16 Single Ended I 8 Differential Input
12-81T DATA ACQUISITION SYSTEMS
FEATURES
DESCRIPTION
• COMPLETE 12-BIT DATA ACQUISITION SYSTEM
IN A MINIATURE PACKAGE
_. __ .. .
.......
-"" ,,'""'. ,."
The SDM862 and SDM863 are coinplete data acquisition
systems housed in a hermetically sealed 1" square leadless
chip c~rrier or 8. 1.\" 5'111~re !1in grid array. Tlie small
package outlines and low power consumption provide an
ideal data acquisition solution where space is at a
premium.
-_
"
~.--
-. --_ .....
...
.Nru. ""NUCi) i)CI.CII.KDI.': run U",.-uum
•
•
•
•
•
o
OR BIPOLAR OPERATION
THROUGHPUT RATES
B-BIT ACCURACY - 45KHz
12-BIT ACCURACY - 33KHz
SELECTABLE GAINS OF 1. 10 and 100
FULL MICROPROCESSOR COMPATIBLE
INTERFACE
GUARANTEED NO MISSING CODES OVER
TEMPERATURE
SURFACE MOUNT OR PIN GRID ARRAY
PACKAGE OPTIONS
FULL SPECIFICATION OVER 3 TEMPERATURE
RANGES
oto +70°C
-25 to +85°C
-55 to +125°C.
The devices comprise of an input multiplexer (SDM862
16 single-ended inputs. SDM863 8 differential inputs).
instrumentation amplifier with selectable gains. samplel
hold amplifier and AID converter with microprocessor
interface and 3-state buffers.
The SDM862 and SDM863 will accept unipolar or bipolar
voltage inputs in the range 0 to + 1OV. ± 5V and ± IOV.
For low level signals jumper-selectable gains of 10 or 100
can be applied. The number of input channels can be
expanded by the addition of multiplexers. The microprocessor interface and the facility of the samplelhold
amplifier being controlled directly by the AID converter
simplifies system integration.
a:
g
0
X
::>
::;
N
<0
0..
f-
::;
a.
f-
::>
«
..
f- ::>
::>
0 !!:
'"'
<0
ff-
t;
ZW
0..
Ul
!!:
Ul
i§
zw
::>
a.
U
~
..
13 ::>f0
x 9
0
in J: i§
f-
::>
0
f-
ff-
::>
W
~£;5
W
U.W
zC!l oUU
«
a:
S~~
OWW
. ~~~
f-
::>
!!:
~o~
" "
Ul
Ul
16 SINGLE ENDED
DIGITAL
DATA
OUTPUTS
"-r-"'"
W
~~@
zz-'
z
-@@@@
PIN 1 IDENT Terminations: Gold plated
KOVAR.
Case: Black ceramic with gold
plated nickel lid.
Hermeticity: Gross leak test.
Weight: 9 grms (0.320z)
B
0~@@)@®®®®®®
r
00
"C
t
PC/XT/AT or compatible ,into an easy-touse DSP workstation, even for the nonexpert.
DSPlay Software features a menu-driven interface
with pull-up lists to process, analyze, and display
real-world signals. Built-in editor functions make
program developme,nt and modification simple;
and, the package utilizes a concept familiar to the
user for program development-the block diagram
approach.
DSPlay XL is slated for introduction in the fourth
quarter of 1987.
For more information about DSPlay products,
contact the factory at 602-741-1155 or write DSP
Marketing, Burr-Brown Corporation, 6550 S. Bay
Colony, Tucson, AZ 85706.
DSPlay"', DSPlay XL'·, Burr-Brown Corp.; IBMS IBM Corp.
STD BUS INDUSTRIAL I/O PRODUCTS
The Burr-Brown STD Bus products provide the
most cost-effective tool for solving the application-oriented problems of process control and
system integration.
The modularity and simplicity offered by this
well-defined standard have led to the development
of a complete line of STD Bus products. The line
includes a disk controller and operating system,
a Z80 CPU with onboard DMA, vari,ous memory
boards, a 32-channel 12-bit A/D converter, two
, CRT controllers, an I EEE-488 interface card, and
two types of discrete I/O cards.
260
Burr-Brown Data Communications products provide the most cost-effective tool for solving the
local data communications problems for industrial
and institutional iacilities.
shake. It features 1000V isolation and surge
protection.
Fiber optic modems offer the maximum in isolation and EMI/RFI immunity. The LDMBO is signal
powered from RS-232 ports and transmits up to
3.5km at 19.2k bits per second. The LDMa5 is a
unique mUltipoint-capable modem with data rates
to 5M bits per second.
Limited Distance and Fiber Optic Modems provide
extension of RS-232 ports up to several miles. In
addition, electrical isolation for wire units is
provided by transformers and optical couplers,
eliminating ground loops, equipment damage, and
noise pickup. Surge suppression devices are
internally mounted on all field inputs and outputs.
The LDM422 serves as a Limited Distance Modem
and as an RS-232-to-RS-422 converter with multipoint capability. It has two complete high speed
transmit and receive channels for data and hand-
Other products include:
o LDM35-Signal-Powered Limited-Distance
Modem
o LDM70-High Speed Ruggedized Industrial
Modem
o APA120-Personal-Computer-Based Protocol
.
Analyzer.
261
NORTH AMERICAN SALES DIRECTORY
For Component Products
BURR-BROWN OFFICES AND SALES REPRESENTATIVES
ALABAMA
Rep, Inc.
.205-881-9270 Huntsville, AL
IOWA
Rep Associates Corporation
319-373-0152 Marion, IA
NEVADA (Southern)
Burr-Brown Corporation
818-991-8544 Agoura, CA
ALASKA
Burr-Brown Corporation
206-455-2611 Bellevue, WA
KANSAS
BC Electronic Sales, Inc.
913-342-1211 Kansas City, KS
316-722-0104 Wichita, KS
NEW HAMPSHIRE
Burr-Brown Corporation
617-273-9022 Burlington, MA
ARIZONA
Burr-Brown Corporation
602-746-1111 Tucson, AZ
ARKANSAS
Burr-Brown Corporation
214-681-5781 Garland, TX
CALIFORNIA (Northern)
Burr-Brown Corporation
408-559-8600 San Jose, CA
CALIFORNIA (Southern)
Burr-Brown Corporation
818-991-8544 Agoura, CA
805-496-7581 Agoura, CA
714-835-0712 Santa Ana, CA
KENTUCKY
Burr-Brown Corporation
513-891-4711 Cincinnati, OH
LOUISIANA (Northern)
Burr-Brown Corporation
214-681-5781 Garland, TX
LOUISIANA (Southern)
Burr-Brown Corporation
713-988-6546 Houston, TX
MAINE
Burr-Brown Corporation
617-273-9022 Burlington, MA
CANADA
Allan Craw10rd Associates
416-890-2010 Mississauga, ONT
MARYLAND
Marktron, Inc.
301-628-1111 Hunt Valley, MD
301-251-8990 Rockville, MD
COLORADO
Burr-Brown Corporation
303-663-4440 Loveland, CO
MASSACHUSETTS
Burr-Brown Corporation
617-273-9022 Burlington, MA
CONNECTICUT
Burr-Brown Corporation
914-964-5252 Yonkers, NY
MICHIGAN
Burr-Brown Corporation
313-474-6533 Farmington, MI
DELAWARE
OED Electronics, Inc.
215-643-9200 Spring House, PA
MINNESOTA
FLORIDA
Burr-Brown Corporation
305-740-7900 Orlando, FL
305-586-7162 Palm Beach, FL
GEORGIA
Rep, Inc.
404-938-4358 Atlanta, GA
HAWAII
Burr-Brown Corporation
818-991-8544 Agoura, CA
IDAHO
Burr-Brown Corporation
206-455-2611 Bellevue, WA
ILLINOIS
Burr-Brown Corporation
312-832-6520 Addison, IL
INDIANA
Burr-Brown Corporation
513-891-4711 Cincinnati, OH
Electronic.~ales Agency, Inc.
612-884-8291 Bloomington, MN
MISSISSIPPI
Rep, Inc.
404-938-4358 Atlanta, GA
MISSOURI
BC Electronic Sales, Inc.
314-521-6683 SI. Louis, MO
MONTANA
Aspen Sales, Inc.
801-467-240tSalt Lake City, UT
NEBRASKA
BC Electronic Sales, Inc.
913-342-1211 Kansas City, KS
NEVADA (Noi1hern)
Burr-Brown Corporation
408-559-8600 San Jose, CA
NEW JERSEY
Burr-Brown Corporation
914-964-5252 Yonkers, NY
NEW MEXICO
Thorson Desert States, Inc.·
505-293-8555 Albuquerque, NM
NEW YORK (Metro Area)
Burr-Brown Corporation
914-964-5252 Yonkers, NY
NEW YORK
Advanced Components Corp.
315-853-6438 Clinton, NY
607-785-3191 Endicott, NY
315-699-2671 N, Syracuse, NY
716-544-7017 Rochester, NY
716-889-1429 Scottsville, NY
NORTH CAROLINA
Murcota Corporation
919-722-9445 WlnstonSalem, NC
NORTH DAKOTA
Electronic Sales Agency, Inc.
612-884-8291 Bloomington, MN
OHIO
Burr-Brown Corporation
513-891-4711 Cincinnati, OH
OHIO (Northeastern)
K-T/DEPCO Marketing, Inc.
216-442-6200 Cleveland, OH
OKLAHOMA
Burr-Brown Corporation
214-681-5781 Garland, TX
OREGON
Burr-Brown Corporation
. 206-455-2611 Bellevue, WA
PENNSYLVANIA (Eastern)
OED Electronics, Inc.
215-643-9200 Spring House, PA
PENNSYLVANIA (Western)
K-T/DEPCO Marketing, Inc.
412-367-1011 Pittsburgh, PA
SOUTH CAROLINA
MUrCota Corporation
919-722-9445 WinstonSalem,NC
SOUTH DAKOTA
Electronic Sales Agency, Inc.
612-884-8291 Bloomington, MN
TENNESSEE
Rep, Inc.
615-475-4105 Jefferson City, TN
TEXAS (Northern)
Burr-Brown Corporation
214-681-5781 Garland, TX
TEXAS (Southern)
Burr-Brown Corporation
713-988-6546 Houston, TX
TEXAS (EI Paso)
Thorson Desert States, Inc,·
505-293-8555 Albuquerque, NM
UTAH
Aspen Sales, Inc.
801-467-2401 Salt Lake City, UT
VERMONT
Burr-Brown Corporation
617-273-9022 Burlington, MA
VIRGINIA
Marktron, Inc.
301-251-8990 Rockville, MD
WASHINGTON
Burr-Brown Corporation
206-455-2611 Bellevue, WA
WASHINGTON,D,C.
Marktron, Inc.
301-251-8990 Rockville, MD
WEST VIRGINIA
Burr-Brown Corporation
513-891-4711 Cincinnati, OH
WISCONSIN (Eastern)
Burr-Brown Corporation
312-832-6520 Addison, IL
WISCONSIN (Western)
Electronic Sales Agency, Inc.
612-884-8291 Bloomington, MN
WYOMING
Aspen Sales, Inc.
801-467-2401 Salt Lake City, UT
RHODE ISLAND
Burr-Brown Corporation
617-273-9022 Burlington, MA
• Microcircuits only.
BURR-BROWNiI!J
BURR-BROWN CORPORATION
IElElI
CUSTOMER PRICE LIST-COMPONENT PRODUCTS
F.O.B. Tucson, Arizona
Quantity disoounts available.
Prices in U.S. dollars
MODEL
0100M5
0145MC
0546
0548MC
0700
0700M
0700U
0700UH
0710
0722
07228G
0722MG
0724
0803H5
0803HC
0804H5
0805H5
0807H5
2014HC
2020HC
2026MC
2302HC
2350HC
2525HC
3291/14
,3292/14
3293/14
3329/03
3354/25
3355/25
3356/25
3450
3451
3452
3500A
35008
3500C
3500E
3500HP
3500R
3500R/8838
3500RQ
35005
35005Q
3500T •
3500TQ
Page No.1
P.O. BOX 11400· Tucson, Arizona 85734
Telephone: (602) 746-1111 • TWX: 910·952-1111 • Telex: 66·6491
FOOT
NOIE
1-24
14.98
5.21
25-99
100-249
12.74
4.43
10.34
3.78
W4.00
~.OO
%.00
28.00
27.00
26.00
50.00
~.OO
%.00
53.00
44.00
51.00
43.00
49.00
41.00
60.00
~.OO
~.OO
121.00
52.96
67.59
60.ro
73.85
4.20
5.75
5.61
25.25
1.54
17.00
9.00
117.00
40.77
53.14
112.00
36.23
47.09
~.ro
~.~
56.86
3.24
4.43
4.32
19.44
1.19
14.00
7.00
50.98
2.84
4.04
3.94
~.OO
~.OO
H.OO
9.00
14.00
8.60
13.50
8.20
13.00
1.00
11.00
6.00
28.00
n.oo
".00
1n.00
125.00
125.00'
43.23
165.00
133.00
125.00
280.00
228.00
240.00
11..54
19.71
25.14
40.60
40.60
23.80
120.00
120.00
120.00
35.64
159.00
128.00
120.00
269.00
219.00
230.00
8.80
15.61
20.14
30.24
30.24
17.93
1~.00
115.00
115.00
25.20
152.00
123.00
115.00
258.00
210.00
221.00
6.72
11.39
14.91
23.36
23.36
13.13
~.OO
~.OO
~.OO
~.~
n.oo
W.OO
36.96
52.48
59.64
82.72
27.27
38.72
44.28
62.87
22.26
31.60
35.28
50.40
IiODEL
3500U/8838
35015
3507J
3507JQ
3508J
3510AM
35108H
3510CH
35105H
3510VM/8838
3521H
3521J
3S21.J()
3521K
3521L
3521R
3521RQ
3522J
3522K
3522L
35225
35225Q
3523J
3523JQ
3523K
3523L
3523LQ
3527AH
3527AMQ
35278M
35278MQ
3527CH
3528AM.
3528AMQ
35288M
35288HQ
3528CH
3528CMQ
3550J
3550K
35505
35505Q
3551J
35515
35515Q
3553AM
FOOT
NOfE
1-24
30.00
28.56
13.05
19.43
11.48
10.47
13.27
20.44
20.44
70.00
27.65
39.50
52.00
59.30
83.50
97.00
137.75
20.60
27.00
37.78
53.40
71.15
38.50
50.75
45.80
54.90
73.85
18.20
24.42
24.36
29.96
37.13
22.68
30.30
27.83
36.96
33.88
45.86
34.94
44.52
64.74
87.36
35.62
62.89
78.40
40.32
Effective June 1, 1987
25-99
26.00
22.41
10.42
15.07
8.91
8.10
10.15
15.39
15.39
60.00
21.65
28.80
38.55
43.20
61.45
76.50
105.65
16.00
21.55
28.10
·41.50
57.80
29.20
4'1.20
36.00
42.00
60.65
13.72
18.52
17.82
23.81
28.89
17.12
23.27
20.90
28.03
26.08
36.34
27.00
33.75
50.60
69.66
27.27
49.95
64.80
31.21
100-249
24.00
17.80
8.72
12.97
7.77
6.25
7.82
12.18
12.18
50.00
16.49
22.31
30.87
35.96
49.35
58.49
86.78
12.34
16.80
22.16
31.34
45.83
22.73
33.08
28.93
33.39
51.40
11.50
15.59
15.38
20.21
24.47
13.60
18.32
18.43
24.78
23.00
30.45
22.52
26.78
37.49
53.55
22.52
37.49
51.45
23.57
Page No.2
CUSTOMER PRICE LlST--COMPONENT PRODUCTS
F.O.B. Tucson, Arizona
Quantity discounts available.
Prices in U.S. dollars
MODEL
3553AMQ
3554AM
3554AMQ
3554BM
3554BMQ
35545M
35545MQ
3571AM
3571AMQ
3572AM
3572AMQ
3573AM
3573AMQ
3580J
3580JQ
3581J
3582J
3582JQ
3583AM
3583AMQ
3583JM
3584JM
3584JMQ
3606AG
3606BG
3627AM
3627AMQ
3627BM
3627BMQ
3650HG
3650JG
3650KG
3650MG
3652HG
3652JG
3652MG
3656AG
3656BG
3656HG
3656JG
3656KG
4025MC
4085BM
4085KG
40855M
4115/04
FOOT
NOfE
1-24
25-99
63.84
77.35
95.50
88.85
111.30
105.00
145.60
81.14
109.76
92.96
125.44
40.32
54.88
65.72
94.35
99.05
107.60
143.00
106.00
148.40
97.85
100.00
136.75
117.60
153.44
14.00
28.00
18.76
36.40
63.00
54.00
60.00
76.96
73.50
93.60
88.00
118.80
58.32
85.32
69.12
99.36
28.62
42.12
49.40
72.30
72.65
90.90
123.75
88.40
122.75
83.20
75.40
113.35
102.60
136.62
10.64
17 .55
13.61
21.60
46.22
100-249
46.20
50.09
68.25
58.96
80.85
73.50
99.23
50.40
72.45
57.23
'81.90
26.25
36.75
42.25
60.75
62.85
73.15
107.15
72.10
106.10
66.95
67.45
100.95
91.35
.119.54
9.61
14.18
11.81
17 .59
35.44
~.93
~.%
~."
99.57
56.45
81.93
99.57
64.12
96.71
119.56
81.38
39.53
61.94
75.28
51.03
74.52
92.18
68.25
33.60
49.04
67.20
44.94
60.74
81.74
85.W
~.88
~.~
91.06
111.94
39.00
91.84
79.52
115.36
74.26
70.20
86.35
32.00
79.38
65.50
102.06
56.70
57.23
70.30
26.00
61.95
51.98
79.28
51.19
MODEL
4127 JG
4127KG
4203J
4203K
42035
420350
4204J
4204K
42045
420450
4205J
4205K
42055
4205S0
4206J
4206K
4213AL
4213AL-BS
4213AL-BSSI
4213AL-B5S2
4213AL-B5S3
4213AL-BS54
4213AM
4213AM-B5
4213AM- BSS 1
4213AM-BSS2
4213AM-BSS3
4213AM-B5S4
4213AMQ
4213BL
4213BL-BS
4213BL-B5S1
4213BL-B5S2
4213BL-BSS3
4213BL-BSS4
4213BM
4213BM-BS
4213BM-85S1
4213BM-B552
4213BM- BSS3
4213BM- B5S4
42135L .
4213SL-BS
42135L-BS51
42135L-BSS2
42135L-BSS3
FOOT
NOfE
1-24
56.84
65.46
43.50
59.58
92.40
122.40
76.16
99.40
113.12
150.08
35.78
52.08
74.42
98.95
54.26
77.06
34.20
34.20
112.86
44.46
39.33
37.62
31.15
31.15
104.61
40.50
35.82
34.27
38.90
48.40
48.40
159.72
62.92
55.66
53.24
45.05
45.05
151.47
58.57
51.81
49.56
61.90
61.90
204.27
80.47
71.19
Effective June 1, 1987
25-99
42.55
53.41
29.15
47.90
66.10
91.85
64.75
85.91
101.52
139.32
28.08
40.88
56.16
77.60
43.15
61.18
27.10
27.10
89.43
35.23
31.17
29.81
24.40
24.40
81.18
31.72
28.06
26.84
31.85
37.50
37.50
123.75
48.75
43.13
41.25
34.75
34.75
115.50
45.18
39.96
38.23
51.75
51.75
170.78
67.28
59.51
100-249
36.12
46.10
21.55
38.30
58.30
81.40
53.55
67.73
86.10
121.80
20.95
31.76
42.00
59.48
31. 76
44.36
21.95
21.95
72.44
28.54
25.24
24.15
19.50
19.50
64.19
25.35
22.43
21.45
26.25
31.65
31.65
104.45
41.15
36.40
34.82
29.15
29.15
96.20
37.90
33.52
32.07
41.40
41.40
136.62
53.82
47.61
CUSTOMER PRICE LIST-COMPONENT PRODUCTS
Quantity discounts available.
F.O.B. Tucson, Arizona
Prices in U.S. dollars
MODEL
4213Sl-BSS4
4213SM
4213SM-BS
4213SM-BSSI
4213SM-BSS2
4213SM-BSS3
4213SM-BSS4
4213UM
4213UM/883B
4213VM
4213VM/883B
4213WM
42!3HM/8838
4214AP
4214BP
4214RM
4214SM
4302
4340
4341
4423
8300201XC
AD515JH
AD515Jl
AD515KH
AD515Kl
AD515lH
AD515ll
ADC10HT
ADC574AJH
ADC574AKH
ADC574ASH
ADC574ATH
ADC600B
ADC600K
ADC674AJH
ADC674AKH
ADC674ASH
ADC674ATH
ADC71JG
ADC71KG
ADC72AM
ADC72BM
ADC72JM
ADC72KM
ADC76AM
FOOT
NOTE
1-24
25-99
100-249
68.09
56.93
45.54
~.~
~.M
~.~
MODrl
~.OO
~.OO
~.OO
ADC76BM
ADC76JG
ADC76JM
ADC76KG
ADC76KM
ADC803BM
ADC803BMQ
ADC803CM
ADC803CMQ
ADC803SM
ADC803SMQ
ADC804BH
75.00
62.00
48.00
.l'DC8048HQ
~.~
~.80
~.90
196.02
75.79
62.04
64.13
31.00
43.00
45.00
60.49
162.53
63.44
56.12
53.68
26.00
37.00
39.00
38.00
128.37
50.57
44.74
42.79
23.00
29.00
31.00
35.00
28.28
22.95
17.64
41.94
33.70
28.35
34.16
26.95
24.52
55.33
45.36
38.59
58.86
42.88
33.76
108.90
79.95
70.65
32.70
25.97
18.85
27.10
17.48
21.06
170.00
163.00
155.00
14.31
9.98
19.04
19.50
15.75
12.00
25.48
19.71
14.54
20.75
16.35
25.25
24.30
18.90
31.36
30.50
25.00
20.50
477.75
414.75
577.50
45.00
36.00
30.00
59.00
47.20
39.50
124.00
99.00
91.35
177.00141.00118.50
2375.00
2090.00
1695.00
1495.00
58.50
46.75
39.25
75.00
60.00
50.25
158.00
126.00
106.00
228.00
182.00
153.00
98.70
86.10
66.15
107.10
81.90
122.85
156.45
239.40
203.70
298.20
254.10
195.30
199.50
170.10
131.25
249.90
212.10
162.75
281.40
224.70
193.20
ADC804SH
ADC804SHQ
ADC80AG-l0
ADC80AG-12
ADC80AG-12Q
ADC80AGZ-12
ADC80H-AH-12
ADC80H-AH-12Q
ADC80KD
ADC80MAH" 12
ADC80MAH-12/QM
ADC82AG
ADC82AM
ADC82AMQ
ADC84KG-l0
ADC84KG-12
ADC85-10
ADC85-12
ADC85H-12
ADC85HQ-12
ADC87
ADC87/883B
ADC87H-12
ADC87HQ-12
ADC87U
ADC87U/883B
ADC87V
ADC87V /883B
DAC10HT
DACI200KP-V
DACI201KP-V
DACI600JP-V
DACI600KP-V
FOOT
flOlE
Page No.3
Effective June 1, 1987
1-24
25-99
330.75
156.45
193.20
179.55
242.55
2E.OO
321. 00
292.00
369.00
382.00
502.00
66.15
102.90
124.95
156.45
83.48
85.05
110.25
B5.05
85.05
110.25
264.60
135.45
154.35
153.30
194.25
226.80
103.95
132.30
124.95
165.90
1~.OO
I~.OO
E,O
100-249
256.00
205.00
225.00
180.00
293.00
234.00
304.00
243.00
399.00319.00
47.25
40.95
72.45
57.75
69.30
87.15
109.20
B7.15
66.15
46.20
46.73
67.20
88.20
60.90
67.20
46.73
67.20
46.73
88.20
60.90
33.00
33.00
~.OO
~.OO
~.OO
67.00
78.75
113.40
153.30
92.40
97.65
158.55
179.55
131.25
163.80
119.00
130.00
173.25
216.30
110.00
121.00
119.00
130.00
355.95
9.50
11.20
15.10
16.70
54.00
54.60
78.75
115.50
73.50
77.70
143.85
144.90
105.00
131.25
102.00
113.00
138.60
173.25
94.00
104.00
102.00
113.00
241.50
9.50
11.20
14.35
15.95
45.00
46.20
66.15
105.00
61.95
65.10
103.95
110.25
88.20 .
110.25
94.00
105.00
115.50
143.85
91.00
96.00
94.00
105.00
178.50
5.95
6.95
8.95
9.95
CUSTOMER PRICE LIST-COMPONENT PRODUCTS
F.O.B. Tucson, Arizona
Quantity discounts available.
Page No.4
Prices in U.S. dollars
MOOEl
DAC60-10
DAC60-12
DAC63BG
DAC63BM
DAC63CG
DAC63CH
DAC63SH
DAC63TH
DAC700BH
DAC700BH/QH
DAC700BL
DAC700BL/QH
DAC700CH
DAC700KH
DAC700LH
DAC700SH
DAC700SH/QH
DAC700SL
DAC700SL/QH
DAC70lBH
DAC701BH/QH
DAC701BL
DAC70IBL/QM
DAC70lCH
DAC70lKH
DAClOILH
DAClOISH
DAClOISH/QH
DAClOlSL
DAClO(SL/QH
DAC702BH
DAC702BH/QH
DACl02BL
OAC702BL/QH
DAC702CH
OACl02JP
DAC702KH
DAC702KP
OAC702LH
DAC702SH
DAC702SH/QH
DAC702SL
DAC702SL/QH
DAC703BH
OAC703BH/QH
OAC703BL
FOOT
NOfE
1-24
25-99
100-249
I~.OO
IU.OO
le.oo
165.00
159.00
152.00
121.80
97.65
91.35
117.60
107.10
141.75
137.55109.20101.85
160.65
131.25
117.60
192.15
252.00
210.00
276.15
234.15
212.10
n.H
u.~
Q.%
73.50
95.55
109.20
88.20
48.30
71.40
55.65
72.45
82.95
67.20
36.75
54.60
47.25
61.95
71.40
56.70
30.45
46.20
~.Q
~.~
~.M
107.10
154.35
177 .45
60.90
73.50
95.55
109.20
00.20
80.85
122.85
140.70
68.25
103.95
119.70
48.~
Q.%
55.65
72.45
82.95
67.W
47.25
61.95
71.40
48.~
36.~
~.~
71.40
92.40
107.10
154.35
177.45
54.60
70.35
80.85
122.85
140.70
46.20
58.80
68.25
103.95
119.70
n.H
48.~
Q.%
73.50
95.55
109.20
00.20
23.10
48.30
25.20
71.40
92.40
107.10
154.35
177 .45
55.65
72.45
82.95
67.20
19.58
36.75
21.95
54.60
70.35
80.85
122.85
140.70
47.25
61.95
71.40
56.70
17.85
30.45
19.95
46.20
58.80
68.25
103.95
119.70
n.H
48.~
Q.%
73.50
95.55
55.65
72.45
47.25
61.95
~.ro
MODEL
DACl03BL/QM
DAC703CH
DAC703JP
DAC703KH
OAC703KP
OAC703LH
OAC703SH
OAC 703SH/QM
OAC703SL
DAC703SL/QM
OACl03VG
OAC703VG/883B
OAC703VL
OAC703VL/883B
OAC705BH
OAGO 5BH / QH
OACl05KH
OAC705SH
OACl05SH/QM
OAC706BH
DAC706BH/QH
DAC706KH
DAC706SH
DACl06SH/QH
OAC707BH
DAC707BH/QH
DAC707JP
DAC707KH
DAC707KP
DAC707SH
DAC707SH/QM
DAC708BH
DAC708BH/QH
DAC708KH
DAC708SH
DAC708SH/QM
DAC709BH
DAC709BH/QM
DAC709KH
DAC709SH
DAC709SH/QM
DAC 70BH-COB- I
DAC70BH-CSB- I
DAC71-CCD-I
DAC 7l-CCD- V
DAC71-COB-I
FOOT
NOTE
1-24
109.20
88.20
23.10
48.30
25.20
71.40
Effective June 1, 1987
25-99
82.95
67.20
19.58
36.75
22.03
54.60
100-249
71.40
56.70
17.85
30.45
19.95
46.20
~.Q
ro.~
~.M
107.10
154.35
177.45
102.00
118.50
143.50
165.50
76.65
88.20
66.15
99.75
114.45
80.85
122.85
140.70
77.00
89.00
108.00
125.00
72.45
82.95
53.55
97.65
108.15
68.25
103.95
U9.70
64.50
75.00
90.00
105.00
56.70
65.10
46.20
77.17
89.30
~.e
72.~
~.~
88.8
66.15
99.75
114.45
76.65
88.W
27.30
66.15
32.55
99.75
114.45
76.65
88.20
66.15
99.75
114.45
76.65
88.20
66.15
99.75
114.45
150.15
150.15
67.10
70.40
56.70
~.%
~.~
53.55
93.45
108.15
72.45
48.51
77.17
89.30
59.54
~.95
e.w
21.53
53.55
25.73
93.45
108.15
72.45
82.95
53.55
93.45
108.15
72 • 45
82.95
53.55
93.45
108.15
113.40
113.40
52.80
57.20
44.10
18.3.7
46.20
22.05
73.50
85.05
56.70
65.10
46.20
73.50
85.05
56.70
65.10
46.20
73.50
85.05
94.50
94.50
46.20.
52.80
38.85
CUSTOMER PRICE LIST-COMPONENT PRODUCTS
F.O.B. Tucson, Arizona
Quantity dis(X)unfs available.
Prices in U.S. dollars
HODEL
FOOT
1-24
25-99
100-249
DAC7541AAH
OAC7541AAH/QM
OAC7541ABH
OAC7541ABH/QH
DAC7541AJP
OAC7541AJU
OAC7541AKP
OAC7541AKU
OAC7541ASH
OAC7541ASH/QM
OAC7541ATH
OAC7541ATH/QM
DAC7700KD
DAC7701KO
OAC80-CBI-1
OAC80-CBI-V
OAC80-CCO-1
DAC80-CCD-V
OAC800-CBI- I
DAC800-CBI-V
DAC800P-CBI - I
DAC800P-CBI-V
OAC80KD-1
DAC80KD-V
DAC80P-CBI-1
DAC80P-CBI-V
DAC80Z-CBI-I
DAC80Z-CBI-V
DAC811AH
DAC811AH/QM
DAC811Al
OAC811Al/QH
DAC811BH
FOOT
1-24
25-99
35.75
37.00
46.50
28.25
29.25
37.00
. 15.25
14.90
16.40
19.80
21.20
63.00
73.00
82.00
95.00
100-249
NorE
NorE
OAC71-COB-V
DAC71-CSB-1
DAC71-CSB-V
DAC710KH
DAC711KH
OAC72BH-COB-1
OAC72BH-COB-V
OAC72BH-CSB-1
OAC72BH-CSB-V
OAC736J
OAC736K
OAC73J
MODEL
Page No.5
Effective June 1, 1987
59.85
56.70
59.85
42.00
42.00
87.15
90.30
87.15
90.30
375.00
415.00
373.00
47.25
44.10
47.25
35.70
35.70
66.15
70.14
66.15
69.30
360.00
399.00
35B.00
40.95
3B.B5
40.95
30.45
30.45
53.55
55.65
53.55
55.65
345.00
3B2.00
344.00
"tJ.c..uv
... ,., nn
395.00
3no.CO
13.10
16.20
14.45
17.90
11.80
14.15
13.10
15.70
. 38.35
57.00
44.75
66.50
10.75
12.70
11.85
14.10
9.70
11.65
10.75
12.90
31.35
44.70
36.60
52.20
25.20
25.20
18.25
19.00
37.50
38.00
19.95
24.15
17.01
22.05
15.25
15.25
16.00
16.37
18.25
19.00
18.35
23.00
23.25
29.25
22.50
7.95
9.30
8.75
10.20
7.15
B.55
7.95
9.55
23.25
32.60
27.10
38.00
IB.37
18.37
15.25
16.00
25.00
26.00
15.75
IB.90
14.33
16.80
9.60
9.60
13.25
14.00
15.25
16.00
14.90
18.75
19.40
24.25
IB.90
E
E
23.00
24.00
42.00
42.50
24.15
28.87
21.26.
26.25
20.00
21.00
23.00
24.00
23.25
29.15
29.25
36.75
28.50
DAC811BH/QM
DAC811Bl
OAC811Bl/QH
DAC811JO
DAC811JP
OAC811 JU
DAC811KP
DAC811KU
OAC811 RH
DAC811RH/QM
DACBllRl
OAC811Rl/QM
!)l'.C81!SH
OAC811SH/QH
DAC811Sl
DAC811Sl/QM
OAC812BH
DAC812CM
DAC82KG
OACB50-CB I-I
DAC850-CBI-I/QH
OAC850-CBI-V
DAC850-CBI-V/QH
DAC850Bl-I
OAC850Bl-I/QM
DAC850Bl-V
DAC850Bl-V/QH
DAC851-CBI-1
OAC851-CBI-I/QM
OAC851-CBI-V
OAC851-CBI -v /QH
DAC851Sl-1
OACB51Sl-I/QH
DAC851Sl-V
DAC851Sl-V/QH
DAC85H-CBI-1
OAC85H-CBI- I /QH
OAC85H-CBI-V
OAC85H-CBI-V/QM
DAC87-CBI-I
J
DAC87-CBI-I/B
J,+
OAC87-CBI-V
OAC87-CBI-V/B
OAC870U
OAC870U/883B
OAC870Ul
130.00
106.00
150.00
169.00
195.00
137.55
IB3.75
40.95
38.12
47.36
40.43
50.82
49.35
62.37
53.03
66.99
56.59
65.20
61.21
70.36
74.03
85.?8
79.80
91.35
36.23
44.10
37.80
46.20
122.00
138.00
159.00
126.00
139.65
28.35
27.30
34.12
29.40
36.75
35.70
45.15
37.80
47.25
40.95
47.25
44.62
51.45
53.55
61.95
58.80
67.20
28.87
35.18
30.45
35.18
23.75
24.60
31.00
9.60
11.90
13.50
15.85
17.20
53.00
61.00
69.00
80.00
86.00
99.00
112.00
129.00
96.60
127.05
24.15
23.10
28.87
. 24.68
30.98
30.45
38.33
32.02
40.43
34.65
39.90
37.27
43.05
45.15
51.98
48.30
55.65
25.20
30.98
26.25
32.02
98.00
105.00
45.00
65.00
50.00
78.50
85.00
40.00
60.00
45.00
70.50
76.50
35.00
55.00
40.00
IB.60
20.50
24.75
26.50
79.00
91.00
103.00
119.00
Page No.6
CUSTOMER PRICE LIST-COMPONENT PRODUCTS
F.O.B. Tucson, Arizona
Quantity discounts available.
Prices in U.S. dollars
MODEL
FOOT
1-24
25-99
70.00
80.00
100.00
85.00
105.00
82.95
100.80
65.00
75.00
95.00
80.00
100.00
66.15
80.85
60.00
67.00
80.00
72.00
90.00
57.75
70.35
58.00
61.00
25.30
35.07
75.00
85.00
33.88
47.32
67.59
48.80
49.50
20.12
28.06
44.00
47.00
16.96
23.46
26.19
39.15
56.11
8.90
13.50
13.00
13.00
42.90
16.90
14.95
14.30
10.50
10.50
34.65
13.65
12.08
11. 55
15.25
15.25
50.33
19.83
17 .54
16.78
17.00
42.08
22.10
19.55
18.70
17.25
16.30
16.30
19.06
29.14
41.84
4.95
11.00
9.75
9.75
32.18
12.68
11.21
10.73
7.25
7.25
23.93
9.43
8.34
7.98
11.30
11.30
'37.29
14.69
13.00
12.43
16.15
29.04
21.00
18.57
17.77
16.35
15.35
15.35
100-249
MODEL
NorE
OAC870Ul/883B
OAC870V
OAC870V 1883B
OAC870Vl
OAC870Vl/883B
DAC87H-CBI-V
OAC87H-CBI -v IQM
DAC87U-CBI - I J
OAC87U-CBI-I/B
J,+
OAC87U-CBI - V
OAC87U-CBI-V/B
DAC90BG
OAC90SG
DEMI02 KIT
DEMI06 KIT
DTVIOOHP
OIVIOOJP
DIVIOOKP
INAIOIAD
INAIOIAG
INAIOIAl
INAIOIAl-BS
INAIOIAl-BSSI
INAIOIAl-B~SS2
lNA10IAl-BSS3
INAIOIAl-BSS4
INAIOIAH
INAIOIAM-BS
INAIOIAM-BSSI
lNAI0IAM-BSS2
INAIOIAf1-BSS3
INAIOIAM-BSS4
lNAlOIBl
INAIOIBl-BS·
INAIOIBl-BSSI
INAIOIBl-BSS2
lNAI0IBl-BSS3
lNAI0IBl-BSS4
INAI0IBM-BS
INAIOIBM-BSSI
INAIOIBM-BSS2
INAI0IBM-BSS3
INAIOIBM-BSS4
INAIOICG
lNAIOICl
INAI01Cl-BS
17.95
16:50
16.50
54.45
21.45
18.98
18.15
14.00
14.00
46.20
18.20
16.10
15.40
19.50
19.50
64.35
25.35
22.43
21.45
18.70
56.10
24.31
21. 51
20.57
23.00
20.90
20.90
INAIOICl-BSSI
INAIOICl-BSS2
INAIOICl-BSS3
INAIOICl-BSS4
INAIOICM
INAI0ICM-BS
INAIOICM-BSSI
INAI0ICM-BSS2
INAIOICM-BSS3
INAIOICM-BSS4
INAIOIHP
INAIOIKU
INAIOISG
INAI0lSGQ
INAIOISl
INAIOISl-BS
INAIOISl-BSSI
INAIOISl-BSS2
INAIOISl-BSS3
INAIOISl-BSS4
INAIOISM
INAIOISM-BS
INAIOISfl-BSSI
INAIOISfl-BSS2
INAIOISM-BSS3
. INAIOISM-BSS4
INAIOISMQ
INAIOI VG
INAIOIVG/883B
INAIOIVM
INAIOI VM/883B
,INAI02AD
INAI02AG
INAI02AL
INAI02CG
INAI02CL
INAI02KP
INAI02SL
INAI04AM
INAI04BM
INA104CM
INAI04HP
INAI04JP
INAI04KP
INAI04SM
INAI05AD
FOOT
NOTE
.I
Effective June 1, 1987
1-24
25-99
68.97
27.17
24.04
22.99
20.61
20.61
60.72
26.79
23.70
22.67
7.37
8.29
27.72
39.20
22.00
22.00
72.60
28.60
25.30
24.20
21.84
21.84
64.35
28.39
25.12
24.02
31.36
46.00
49.50
43.75
47.25
53.79
21.19
18.75
17.93
14.90
14.90
45.54
19.37
17.14
16.39
5.67
6.26
19.98
29.16
17.15
17.15
56.60
22.30
19.72
18.87
15.82
15.82
48.35
20.57
18.19
17 .40
22.68
41.60
44.75
39.50
42.50
9.35
11.15
13.65
17.12
18.35
5.95
23.10
20.79
25.11
32.24
16.15
19.39
25.11
34.29
4.65
13.95
16.45
20.61
20.90
7.60
26.40
27.16
32.48
41. 94
21.00
25.20
32.48
44.80
100-249
50.66
19.96
17.65
16.89
13.49
13.49
42.14
17.54
15.51
14.84
5.10
5.51
18.53
26.25
16.45
16.45
54.29
21.39
18.92
18.10
14.65
14.65
46.04
19.05
16.85
16.12
21.00
39.50
42.50
37.50
40.50
5.20
7.95
10.45
II. 92
13.85
5.40
17.25
18.85
22.73
29.24
14.65
17.59
22.73
31. 13
3.50
CUSTOMER PRICE LIST-COMPONENT PRODUCTS
Prices in U.S. dollars
MODEL
INAI05AL
INAI05AM
I NAI 05AM- BS
INAI05AM-BSSI
INAI05AM-BSS2
INAI05AM-BSS3
INAI05AM-BSS4
INAI05BL
INAI05BM
INAI05BM-BS
INAI05BM-BSSI
INAI05BM-BSS2
INAI05BM-BSS3
INAI05BM-BSS4
INA105KP
INAI05KU
INAI05SL
INAI06AM
INAI06BM
INAI06KP
INA110AD
INA110AG
INA110AL
INA110BG
INA110BL
INA110KP
INAIIOKU
INAllOSG
INA110SL
INA258UG
INA258UG/883B
INA258UL
INA258Ul/883B
INA258VG
I NA258VG/883B
INA25BVL
I NA2 58Vl/883B
INA258WG
INA258WG/883B
INA25BWL
INA258WL/883B
ISOIOOAP
ISOIOOBP
ISOIOOCP
ISOl02
ISOI02B
F.O.B. Tucson, Arizona
FOOT
NOTE
1-24
25-99
100-249
Quantity discounts available.
MODEL
FOOT
'Page No.7
Effective June 1, 1987
1-24
25-99
100-249
NorE
12.45
9.50
9.50
32.B4
12.35
10.93
10.45
15.25
11.85
11.85
42.08
15.41
13.63
13.04
6.25
7.34
19.10
10.00
12.45
6.50
16.85
19.35
26.43
26.10
7.40
8.74
28.11
27.60
38.15
42.40
41. 35
45.60
49.80
65.70
54.00
74.20
63.60
84.80
69.95
93.30
36.40
39.65
44.24
25.50
34.45
9.95
7.15
7.15
24.59
9.30
8.22
7.87
12.00
8.95
8.95
31. 35
II. 64
10.29
9.85
4.65
5.35
14.85
7.50
9.40
4.89
9.45
12.65
15.15
19.17
20.25
5.80
6.59
20.36
21. 35
36.00
40.30
39.20
43.50
43.45
'58.30
47.70
64.65
55.10
74.20
60.40
81.60
31.05
34.13
39.20
19.50
26.95
8.45
5.75
5.75
19.64
7.48
6.61
6.33
10.15
7.20
7.20
25.25
9.36
8.28
7.92
3.50
3.99
12.45
6.05
7.55
3.65
5.25
8.85
II. 35
12'.97
14.85
5.50
6.09
18.85
20.45
26.50
29.70
28.60
32 ~86
40.30
56.20
44.50
61. 50
51. 95
69.95
56.20
76.30
26.78
30.08
35.28
16.50
22.30
ISOI06
I SOl06B
LOGIOOJP
MA51414
MP22BG
MP32BG
MP32CG
MPCI6S
MPC40
MPC800KG
MPC800SG
MPC80lKG
MPC80lSG
MPC8D
MPC8S
MPYlOOAG
MPYlOOAL
MPYlOOAL-BS
MPYlOOAL-BSSI
MPYI OOAL - 8SS2
MPY I OOAL- BSS3
MPYI OOAL -BSS4
MPYlOOAM
MPYI OOAM- BS
MPYlOOAM-BSSI
MPYlOOAM-BSS2
MPYlOOAM-BSS3
MPYI OOAM- BSS4
MPYlOOBG
MPYlOOBL
MPYI OOBL - BS
MPYlOOBL-BSSI
MPYlOOBL-BSS2
MPYI OOBL - BSS3
MPYI OOBL - BSS4
MPYlOOBM
MPYlOOBM-BS
MPYlOOBM-BSSI
MPYI OOBM- BSS2
MPY I 00BM-BSS3
MPYlOOBM-BSS4
MPYlOOCG
MPYlOOCL
MPYlOOCL-BS
MPYlOOCL-BSSI
MPYlOOCL-BSS2
34.00
45.90
48.16
26.60
35.95
37.80
22.00
29.75
31.50
340.20
340.20
425.25
24.37
13.62
29.25
58.45
15.23
31.50
24.37
13.62
15.51
13.85
13.85
45.71
18.01
15.93
15.24
11.76
11.76
37.46
15.29
13.52
12.94
25.14
20.85
20.85
68.81
27.11
23.98
22.94
19.04
19.04
60.56
24.75
21.90
20.94
37.74
30.50
30.50
100.65
39.65
271.95
271.95
340.20
21.06
11.81
24.21
48.37
12.60
26.07
21.06
11.77
13.94
12.45
12.45
41.09
16.19
14.32
13.70
10.58
10.58
32.84
13.75
12.17
11.64
22.09
18.75
18.75
61.88
24.38
21.56
20.63
16.69
16.69
53.63
21.70
19.19
18.36
33.48
27.35
27.35
90.26
35.56
227.85
227.85
285.60
17.85
9.97
20.18
40.31
10.50
21.72
17.85
9.97
12.26
10.00
10.00
30.00
13.00
11.50
11.00
8.40
8.40
24.75
10.92
9.66
9.24
17.22
14.15
14.15
46.70
18.40
16.27
15.57
12.23
12.23
38.45
15.90
14.06
13.45
27.56
23.00
23.00
75.90
29.90
Page No.8
CUSTOMER PRICE LIST-COMPONENT PRODUCTS
F.O.B. Tucson, Arizona
Quantity discounts available.
Prices in U.S. dollars
MODEL
FOOT
1-24
25-99
100-249
MODEL
NOTE
MPYlOOCL-BSS3
MPYlOOCL-BSS4
MPYlOOCM
MPYlOOCM-BS
MPYlOOCM-BSSI
MPYlOOCM-BSS2
MPYlOOCM-BSS3
MPYlOOCM-BSS4
MPYlOOSG
MPYlOOSGQ
MPYlOOSL
MPYlOOSL-BS
MPYlOOSL-BSSI
MPYlOOSL-BSS2
MPYlOOSL-BSS3
MPYlOOSL-BSS4
MPYlOOSM
MPYlOOSM-BS
MPYlOOSM-BSSI
MPYlOOSM-BSS2
MPYlOOSM-BSS3
MPYlOOSM-BSS4
MPYlOOSMQ
MPY534AD
MPY534JD
MPY534JH
MPY534JH-BS
MPY534JH-BSSI
MPY534JH- BSS2
MPY534JH-BSS3
MPY534JH-BSS4
MPY534JL
MPY534JL-BS
MPY534JL-BSSI
MPY534JL-BSS2
MPY534JL-BSS3
MPY534JL - BSS4
MPY534KD
MPY534KH
MPY534KH-BS .
MPY534KH-BSSI
MPY534KH-BSS2
MPY534KH-BSS3
MPY534KH- BSS4
MPY534KL
MPY534KL-BS
roOT
Effective June 1, 1987
1-24
25-99
122.10
48.10
42.55
40.70
70.45
57.23
57.23
168.14
74.40
65.81
62.95
53.45
53.45
176.39
69.49
61.47
58.80
89.50
76.41
76.41
224.24
99.33
87.87
84.05
70.45
70.45
232.49
91. 59
81.02
77 .50
107.40
91.80
91.80
317.39
119.34
105.57
100.98
98.68
98.68
325.64
128.28
113.48
108.55
20.00
20.00
66.00
98.51
38.81
34.33
32.84
58.23
47.14
47.14
131.84
61.28
54.21
51.85
42.45
42.45
140.09
55.19
48.82
46.70
74.28
62.95
62.95
176.06
81.84
72.39
69.25
55.85
55.85
184.31
72.61
64.23
61.44
89.50
76.50
76.50
252.45
99.45
87.98
84.15
79.00
79.00
260.70
102.70
90.85
86.90
16.35
16.35
53.95
100-249
NOTE
35.08
33.55
28.56
28.56
92.40
37.13
32.84
31.42
56.62
77 .28
44.50
44.50
146.85
57.85
51.18
48.95
42.84
42.84
138.60
55.69
49.27
47.12
58.24
32.98
25.37
25.37
74.42
32.98
29.18
27.91
25.05
25.05
82.67
32.57
28.81
27.56
47.14
38.76
38.76
113.85
50.39
44.57
42.64
37.00
37.00
31.45
30.09
25.33
25.30
82.01
32.89
29.10
27.83
50.22
67.50
39.45
39.45
130.19
51.29
45.37
43.40
38.02
38.02
121.94
49.43
43.72
41.&2
51.30
12.57
27.67
21.18
21.18
59.23
27.53
24.36
23.30
20.45
20.45
67.49
26.59
23.52
22.50
39.94
32.27
32.27
90.26
41. 95
37.11
35.50
29.85
29.85
26.45
25.30
20.95
20:95
67.65
27.24
24.09
23.05
33.60
48.83
30.50
30.50
100.65
39.65
35.08
33.55
28.61
28.61
92.40
37.19
32.90
31.47
43.05
9.38
19.77
15.16
15.16
42.41
19.71
17.43
16.68
15.35
15.35
50.66
19.96
17 ;65
16.89
29.09
23.42
23.42
65.51
30.45
26.93
25.76
22.35
22.35
MPY534KL-8SS1
MPY534KL-8SS2
MPY534KL-BSS3
MPY534KL-BSS4
MPY534LD
MPY534LH
MPY534LH-BS
MPY534LH-BSS1
MPY534LH-BSS2
MPY534LH-BSS3
MPY534LH-BSS4
MPY534LL
MPY534LL-BS
MPY534LL-BSSI
MPY534LL-BSS2
MPY534LL-BSS3
MPY534LL-BSS4
MPY534SD
MPY534SH
MPY534SH-BS
MPY534SH-BSS1
MPY534SH-BSS2
MPY534SH-BSS3
HPY534SH-BSS4
MPY534SL
MPY534SL-BS
MPY534SL-BSSI
MPY534SL-BSS2
MPY534SL-BSS3
MPY534SL - BSS4
MPY534TD
MPY534TH
MPY534TH-BS
MPY534 TH-BSS 1
HPY534TH-BSS2
HPY534TH-BSS3
MPY534TH-BSS4
MPY534TL
MPY534TL-BS
MPY534TL~BSS1
MPY534TL-BSS2
MPY534 TL- BSS3
MPY534 TL -BSS4
MPY634AL
MPY634AL-BS
MPY634AL-BSS1
73.76
29.06
25.70
24.59
43.48
34.81
34.81
97.35
45.25
40.03
38.29
32.00
32.00
105.60
41.60
36.80
35.20
55.46
47.02
47.02
131. 51
61.13
54.07
51. 72
42.35
42.35
139.-76
55.06
48.70
46.59
64.00
54.50
54.50
179.85
70.85
62.68
59.95
57.00
57.00
188.10
74.10
65.55
62.70
12.45
12.45
41.09
CUSTOMER PRICE LIST-COMPONENT PRODUCTS
F.O.B. Tucson, Arizona
Quantity discounts available.
Prices in U.S. dollars
MonEL
MPY634AL-BSS2
MPY634AL-BSS3
MPY634Al-BSS4
MPY634AM
MPY634AM-BS
MPY634AM-BSSI
MPY634AM-BSS2
HPY634AM-BSS3
MPY634AM-BSS4
MPY634BL
MPY634BL-BS
MPY634BL-BSSI
HPY634BL-BSS2
MPY634BL-BSS3
MPY634BL-BSS4
MPY634BM
MPY634BM-BS
MPY634BM-BSSI
MPY634BH-BSS2
MPY634BH-BSS3
MPY634BM-BSS4
MPY634KP
MPY634SL
MPY634SL-BS
MPY634SL-BSSI
HPY634SL-BSS2
MPY634SL-BSS3
MPY634SL-BSS4
MPY634SM
HPY634SM-BS
MPY634SM-BSSI
HPY634SM-BSS2
MPY634SM-BSS3
MPY634SM-BSS4
0245MC
OPAI0IAH
OPAIOIBH
OPAI02AM
OPAI02BM
OPAI03AM
OPAI03BM
OPAI03CM
OPAI03DH
OPAI04AM
OPAI04BM
OPAI04CM
roOT
NOlE
1-24
25-99
26.00
23.00
22.00
18.65
18.65
57.75
24.25
21. 45
20.52
28.45
28.45
93.89
36.99
32.72
31.30
27.72
27.72
85.64
36.04
31.88
30.49
14.39
65.15
65.15
214.99
84.70
74.92
71.67
66.81
66.81
206.75
86.B5
76.83
73.49
6.05
42.00
52.20
44.4ry
54.00
11. 76
15.90
20.83
33.43
19.60
26.49
33.04
21.26
IB.80
17 .99
14.96
14.96
45.71
19.45
17.20
16.45
23.05
23.05
76.07
29.97
26.51
25.36
22.19
22.19
67.82
2B.85
25.52
24.41
11.50
52.35
52.35
172.76
68.06
60.20
57.59
53.84
53.84
164.51
69.99
61.92
59.22
5.05
33.45
42.00
35.56
43.30
9.29
12.37
16.04
25.76
15.07
20.47
25.38
100-249
16.19
14.32
13.70
10.45
10.45
32.B4
13.59
12.02
II. 50
17.75
17.75
5B.58
23.0B
20.41
19.53
16.01
16.01
50.33
20.BI
18.41
17 .61
B.35
40.35
40.35
133.16
52.46
46.40
44.39
39.74
39.74
124.91
51.66
45.70
43.71
4.B5
25.60
36.00
26.70
36.B5
7.14
9.40
12.13
19.43
10.76
15.23
19.95
MOOEL
OPAI05UM
OPAI05UH/883B
OPAI05VM
OPAI05VM/B83B
OPAI05WH
OPAI05HM/BB3B
OPAI06UM
OPAI06UM/BB3B
OPAI06VM
OPAI06VM/8B3B
OPAI06WM
OPAI06WM/BB3B
OPAI1IAD
UPAlllAL
OPAIIIAL-BS
OPAIIIAL-BSSI
OPAIIIAL-BSS2
OPAIlIAL-BSS3
OPAIIIAL-BSS4
OPAII1AM
OPAIIIAM-BS
OPAIIlAM-BSSI
OPAI1IAM-BSS2
OPAII1AM-BSS3
OPAIIIAH-BSS4
OPAI1IBL
OPAI1IBL-BS
OPAI1IBL-BSSI
OPAI1IBL-BSS2
OPAlllBL-BSS3
OPAl llBL-BSS4
OPAI1IBH
OPAlllBM-BS
OPAl llBH-BSSI
OPAl llBH-BSS2
OPAllIBH-BSS3
OPAllIBM-BSS4
OPAlllHT
OPA111SL
OPAlIl SL-BS
OPAlIISL-BSSI
OPAllISL-BSS2
OPAlIISL-BSS3
OPAllISL-BSS4
OPAll ISM
OPAllISM-BS
FOOT
NOTE
Page No.9
Effective June 1, 1987
1-24
25-99
27.00
32.00
37.00
50.00
47.00
68.00
30.00
36.00
40.00
55.00
52.00
72.00
23.50
2B.00
32.00
44.00
42.00
59.00
25.00
32.00
35.00
49.00
45.00
63.00
7.29
Il.l5
lU.45
12.25
40.43
15.93
14.09
13.48
10.92
10.92
32.18
14.20
12.56
12.01
17.85
17.85
58.90
23.21
20.53
19.64
17.19
17.19
50.66
22.35
19.77
18.91
63.30
19.35
19.35
63.86
25.16
22.25
21.29
20.25
20.25
10.45
34.49
13.59
12.02
11. 50
8.59
8.59
26.24
11.17
9.88
9.45
14.75
14.75
48.6B
19.18
16.96
16.23
13.23
13.23
40.43
17.20
15.21
14.55
50.70
16.45
16.45
54.29
21. 39
18.92
18.10
15.65
15.65
100-249
22.00
25.00
30.00
40.00
40.25
52.00
22.00
28.00
32.00
44.00
42.00
57.00
4.04
I.Y5
7.95
26.24
10.34
9.14
B.75
5.72
5.72
17.99
7.44
6.5B
6.29
12.45
12.45
41.09
16.19
14.32
13.70
10.45
10.45
32.84
13.59
12.02
II. 50
40.70
14.45
14.45
47.69
IB.79
16.62
15.90
13.15
13.15
Page No.IO
CUSTOMER PRICE LIST-COMPONENT PRODUCTS
F.O.B. Tucson, Arizona
Quantity discounts available.
Prices in U.S. dollars
HODEL
OPA111 SH- BSSI
OPA111SM-BSS2
OPAl 11 SM-BSS3
OPAl 11 SH-BSS4
OPAl l1SHQ
OPAl11VH
OPAl 11 VH/883B
OPA11HT
OPAI21KL
OPAI2IKL-BS
OPAI2IKL-BSSI
OPAI2IKL-BSS2
OPAI2IKL-BSS3
OPAI2IKL-BSS4
OPAI21KH
OPAI2IKH-BS
OPAI2IKH-BSSI
OPAI2IKH-BSS2
OPAI21KH-BSS3
OPAI2IKH-BSS4
OPAI21KP
OPAI21KU
OPAI21SL
OPAI2ISL-BS
OPAI2ISL-BSSI
OPAI2ISL-BSS2
OPAI2ISL-BSS3
OPAI2ISL-BSS4
OPAI2ISH-BS
OPAI2ISM-BSSI
OPAI2ISH-BSS2
OPAI2ISH-BSS3
OPAI2ISM_BSS4
OPAI28JD
OPAI28JL
OPAI28JL-BS
OPAI28JL-BSSI
OPAI28JL-BSS2
OPI\128JL-BSS3
OPAI28JL-BSS4
OPAI28JH
OPAI28JH-BS
OPAI28JM-BSSI
OPAI28JM-BSS2
OPAI28JH-BSS3
OPAI28JH-BSS4
FOOT
NOTE
1-24
55.61
26.33
23.29
22.28
27.30
26.00
35.00
58.BO
9.35,
9.35
30.86
12.16
10.75
10.29
6.85
6.85
22.61
8.91
7.88
7.54
5.65
7.78
15.05
15.05
49.67
19.57
17.31
- 16.56
12.55
41.42
16.32
14.43
13.81
20.00
20.00
66.00
26.00
23.00
22.00
21.25
21.25
57.75
27.63
24.44
23.38
25-99
46.04
20.35
18.00
17.22
21.85
20.50
30.00
52.15
7.00
7.00
23.10
9.10
8.05
7.70
4.50
4.50
14.85
5.85
5.18
4.95
3.65
4.27
11.55,
11.55
38.12
15.02
13.28
12.71
9.05
29.87
II. 77
10.41
9.96
14.58
16.45
16.45
54.29
21.39
18.92
18.10
16.95
16.95
46.04
22.04'
19.49
18.65
100-249
39.44
17.10
15.12
14.47
17.55
'17.00
27.00
43.15
5.90
5.90
19.47
7.67
6.79
6.49
3.40
3.40
11.22
4.42
3.91
3.74
2.75
3.20
8.75
8.75
28.88
11.38
10.06
9.63
6.25
20.63
8.13
7.19
6.88
8.66
12.75
12.75
42.08
16.58
14.66
14.03
12.50
12.50
33.83
16.25
14.38
13.75
MODEL
OPAI28KL
OPAI28KL-BS
OPAI28KL-BSSI
OPAI28KL-BSS2
OPAI28KL-BSS3
OPAI28KL-BSS4
OPAI28KM
OPAI28KH-BS
OPAI28KH-BSSI
OPAI28KH-BSS2
OPAI28KH-BSS3
OPAI28KH-BSS4
OPAI2Bll
OPAI28ll-BS
OPAI28lL-BSSI
OPAI28ll-BSS2
OPAI28ll-BSS3
OPAI28ll-BSS4
OPAI28lH
OPAI28lH-BS
OPAI28lH-BSSI
OPAI28LM-BSS2
OPAI28lM-BSS3
OPAI28LM-BSS4
OPAI28Sl
OPAI28Sl-BS
OPAI28Sl-BSSI
OPAI2BSL-BSS2
OPAI28Sl-BSS3
OPAI28Sl-BSS4
OPAI28SH
OPAI28SH-BS
OPAI28SH-BSSI
OPAI28SH-BSS2
OPAI28SH-BSS3
OPAI28SH-BSS4
OPAI56AH
OPA20lAG
OPA20lBG
OPA20lCG
OPA201SG
OPA2 I 11 AD
OPA2111Al
OPA2111AM
OPA2111Bl
OPA211IBM
FOOT
NOIE
1-24
27.50
27.50
90.75
, 35.75
31.63
30.25
32.80
32.80
82.50
42.64
37.72
36.08
34.00
34.00
112.20
44.20
'39.10
37.40
41.38
41.38
103.95
53.79
47.59
45.52
56.75
56.75
187.28
73.78'
65.26
62.43
60.76
60.76
179.03
78.99
69.87
66.84
12.60
9.00
14.00
16.75
18.30
18.15
16.24
29.50
29.06
Effective June 1, 1987
25-99
100-249
18.00
22.50
18.00
22.50
59.40
74.25
23.40
29.25
20.70
25.88
19.80
24.75
19.50
25.75
19.50
25.75
66.00
51.15
33.48
25.35
22.43
29.61
28.33
21.45
27.50
22.50
27.50
22.50
90.75
74.25
35.75
29.25
25;88
31.63
24.75
30.25
25.15
32.02
25.15
32.02
66.00
82.50
, 32.70
41.63
28.92
36.82
27.67
35.22
47.45
41.00
47.45
41.00
156.59' 135.,30
61.69
53.30
54.57
47.15
52.20
45.10
48.55
40.43
48.55
40.43
127.05
148.34
52.56
63.12
46.49
55.83
53.41
44.47
7.09
9.67
6.30
4.35
6.80
9.80
8.20
11.70
9.00
12.05
7.30
10.75
14.45
12.45
12.42
10.45
24.20
19.35
17.33
22.52
CUSTOMER PRICE LIST-COMPONENT PRODUCTS
Prices in U.S. dollars
MODEL
OPA2I11KM
OPA2I11KP
OPA2lliSL
OPA2ll ISM
OPA21£Z
OPA2IGl
OPA27AJ
OPA27AJ-BS
OPA27AJ-BSSI
OPA27AJ-BSS2
OPA27AJ-BSS3
OPA27AJ-BSS4
OPA27AJQ
OPA27AL
OPA27AL-BS
OPA27AL-BSSI
OPA27AL-BSS2
OPA27AL-BSS3
OPA27AL-BSS4
OPA27AZ
OPA27AZQ
OPA27BJ
OPA27BJ-BS
OPA27BJ-BSSI
OPA27BJ-BSS2
OPA27BJ-BSS3
OPA27BJ-BSS4
OPA27BJQ
OPA27BL
OPA27BL-BS
OPA27BL-BSSI
OPA27BL-BSS2
OPA27BL-BSS3
OPA27BL-BSS4
OPA27BZ
OPA27BZQ
OPA27CD
OPA27CJ
OPA27CJ-BS
OPA27CJ-BSSI
OPA27CJ-BSS2
OPA27CJ-BSS3
OPA27CJ-BSS4
OPA27CJQ
OPA27CL
OPA27CL-BS
F.O.B. Tucson, Arizona
FOOT
NOIE
1-24
9.90
7.90
31.15
29.68
10.02
4.98
19.95
19.95
70.46
25.94
22.94
21. 95
32.85
23.85
23.85
78.71
31.01
27.43
26.24
19.95
32.85
12.85
12.85
45.38
16.71
14.78
14.14
21.20
16.25
16.25
53.63
21.13
18.69
17.88
12.85
21.20
9.95
9.95
35.15
12.94
11.44
10.95
16.45
13.15
13.15
25-99
7.90
5.50
24.50
22.90
7.72
3.89
15.65
15.65
53.63
20.35
18.00
17.22
25.00
18.75
18.75
61.88
24.38
21. 56
20.63
15.65
25.00
9.65
9.65
33.00
12.55
11.10
10.62
15.45
12.50
12.50
41.25
16.25
14.38
13.75
9.65
15.45
6.30
7.50
7.50
25.74
9.75
8.63
8.25
12.00
10.30
10.30
100-249
5.25
4.25
19.60
17.59
6.25
3.10
12.50
12.50
41.25
16.25
14.38
13.75
18.75
15.00
15.00
49.50
19.50
17.25
16.50
12.50
18.75
7.65
7.65
25.25
9.95
8.80
8.42
11.85
10.15
10.15
33.50
13.20
11.67
11.17
7.65
11.85
4.20
5.95
5.95
19.64
7.74
6.84
6.55
9.25
8.45
8.45
Quantity discounts available.
MODEL
OPA27CL-BSSI
OPA27CL-BSS2
OPA27CL-BSS3
OPA27CL-BSS4
OPA27CZ
OPA27CZQ
OPA27EJ
OPA27EJ-BS
OPA27EJ-BSSI
OPA27EJ-BSS2
OPA27EJ-BSS3
OPA27EJ-BSS4
OPA27EL
OPA27EL-BS
OPA27EL-BSSI
OPA27EL-BSS2
OPA27EL-BSS3
OPA27EL-BSS4
OPA27EZ
OPA27FJ
OPA27FJ-BS
OPA27FJ-BSSI
OPA27FJ-BSS2
OPA27FJ-BSS3
OPA27FJ-BSS4
OPA27FL
OPA27FL-BS
OPA27FL-BSSI
OPA27FL-BSS2
OPA27FL-BSS3
OPA27FL-BSS4
OPA27Fl
OPA27GO
OPA27GJ
OPA27GJ-BS
OPA27GJ-8SS1
OPA27GJ-BSS2
OPA27GJ-BSS3
OPA27GJ-BSS4
OPA27GL
OPA27GL-BS
OPA27GL-BSSI
OPA27GL-BSS2
OPA27GL-BSS3
OPA27GL-BSS4
OPA27GP
FOOT
NOTE
Page No. 11
Effective June 1, 1987
1-24
43.40
17.10
15.12
14.47
9.95
16.45
11.00
11. 00
38.78
14.30
12.65
12.10
14.25
14.25
47.03
18.53
16.39
15.68
11.00
8.55
8.55
30.20
11.12
9.83
9.41
11.65
11.65
38.45
15.15
13.40
12.82
8.55
6.00
6.00
21.29
7.80
6.90
6.60
8.95
8.95
29.54
11.64
10.29
9.85
5.25
25-99
33.99
13.39
11.84
11. 33
7.50
12.00
8.35
8.35
28.71
10.86
9.60
9.19
11.20
11.20
36.96
14.56
12.88
12.32
8.35
5.95
5.95
20.46
7.74
6.84
6.55
8.70
8.70
28.71
11. 31
10.01
9.57
5.95
4.20
4.95
4.95
17 .00
6.44
5.69
5.45
7.65
7.65
25.25
9.95
8.80
8.42
4.15
100-249
27.89
10.99
9.72
9.30
5.95
9.25
6.65
6.65
21. 95
8.65
7.65
7.32
9.15
9.15
30.20
II. 90
10.52
10.07
6.65
4.95
4.95
16.34
6.44
5.69
5.45
7.45
7.45
24.59
9.69
8.57
8.20
4.95
2.80
4.00
4.00
13.20
5.20
4.60
4.40
6.50
6.50
21.45
8.45
7.48
7.15
2.95
Page No. 12
CUSTOMER PRICE LIST-COMPONENT PRODUCTS
F.O.B. Tucson, Arizona
Quantity discounts available.
Prices in U.S. dollars
MODEL
OPA27GU
OPA27GZ
OPA27HT
OPA356AM
OPA37AJ
OPA37AJ-BS
OPA37AJ-BSSI
OPA37AJ-BSS2
OPA37AJ-BSS3
OPA37AJ-BSS4
OPA37AJQ
OPA37AL
OPA37AL-BS
OPA37AL-BSSI
OPA37AL-BSS2
OPA37AL-BSS3
OPA37 AL-BSS4
OPA37AZ
OPA37AZQ
OPA37BJ
OPA37BJ-BS
OPA37BJ-BSSI
OPA37BJ-BSS2
OPA37BJ-BSS3
OPA37BJ-BSS4
OPA37BJQ
OPA37BL
OPA37BL-BS
OPA37BL-BSSI
OPA37BL-BSS2
OPA37BL-BSS3
OPA37BL-BSS4
OPA37BZ
OPA37BZQ
OPA37CD
OPA37CJ
OPA37CJ-BS
OPA37CJ-BSSI
OPA37CJ-BSS2
OPA37CJ-BSS3
OPA37CJ-BSS4
OPA37CJQ
OPA37CL
OPA37CL-BS
OPA37CL-BSSI
OPA37CL-BSS2
FOOT
NOTE
1-24
5.95
6.00
67.09
8.12
19.95
19.95
70.46
25.94
22.94
21.95
32.85
23.85
23.85
78.71
31.01
27.43
26.24
19.95
32.85
12.85
12.85
45.38
16.71
14.78
14.14
21.20
16.25
16.25
53.63
21.13
18.69
17.88
12.85
21.20
9.95
9.95
35.15
12.94
11.44
10.95
16.45
13.15
13.15
43.40
17.10
25-99
4.45
4.95
55.46
6.43
15.65
15.65
53.63
20.35
18.00
17.22
25.00
18.75
18.75
61.88
24.38
21. 56
20.63
15.65
25.00
9.65
9.65
33.00
12.55
11.10
10.62
15.45
12.50
12.50
41.25
16.25
14.38
13.75
9.65
15.45
6.30
7.50
7.50
25.74
9.75
8.63
8.25
12.00
10.30
10.30
33.99
13.39
100-249
3.25
4.00
44.10
4.73
12.50
12.50
41.25
16.25
14.38
13.75
18.75
15.00
15.00
49.50
19.50
17.25
16.50
12.50
18.75
7.65
7.65
25.25
9.95
8.80
8.42
11.85
10.15
10.15
33.50
13.20
11.67
11.17
7.65
11.85
4.20
5.95
5.95
19.64
7.74
6.84
6.55
9.25
8.45
8.45
27.89
10.99
MODEL
OPA37CL-BSS3
OPA37CL-BSS4
OPA37CZ
OPA37CZQ
OPA37EJ
OPA37EJ-BS
OPA37EJ-BSS1
OPA37EJ-BSS2
OPA37EJ-BSS3
OPA37EJ-8SS4
OPA37EL
OPA37EL-BS
OPA37EL-BSSI
OPA37EL-BSS2
OPA37EL-8SS3
OPA37EL-BSS4
OPA37EZ
OPA37FJ
OPA37FJ-BS
OPA37FJ-8SS1
OPA37FJ-8SS2
OPA37FJ-BSS3
OPA37FJ-BSS4
OPA37FL
OPA37FL-BS
OPA37FL-BSSI
OPA37FL-BSS2
OPA37FL-BSS3
OPA37FL-BSS4
OPA37FZ
OPA37GD
OPA37GJ
OPA37GJ-BS
OPA37GJ-BSSI
OPA37GJ-BSS2
OPA37GJ-BSS3
OPA37GJ-BSS4
OPA37GL
OPA37GL-BS
OPA37GL-BSSI
OPA37GL-BSS2
OPA37GL-8SS3
OPA37GL-BSS4
OPA37GP
OPA37GU
OPA37GZ
FOOT
NOIE
1-24
15.12
14.47
9.95
16.45
11.00
11.00
38.78
14.30
12.65
12.10
14.25
14.25
47.03
18.53
16.39
15.68
11.00
8.55
8.55
30.20
11.12
9.83
9.41
11.65
11.65
38.45
15.15
13.40
12.82
8.55
6.00
6.00
21.29
7.80
6.90
6.60
8.95
8.95
29.54
11.64
10.29 '
9.85.
5.25
5.95
6.00
Effective June 1. 1987
25-99
11.84
11. 33
7.50
12.00
8.35
8.35
28.71
10.86
9.60
9.12
11.20
11.20
36.96
14.56
12.88
12.32
8.35
5.95
5.95
20.46
7.74
6.84
6.55
8.70
8.70
28.71
11. 31
10.01
9.57
5.95
4.20
4.95
4.95
17.00
6.44
5.69
5.45
7.65
7.65
25.25
9.95
8.80
8.42
3.95
4.45
4.95
100-2~9
9.72
9.30
5.95
9.25
6.65
6.65
21. 95
8.65
7.65
7.32
9.15
9.15
30.20
11.90
10.52
10.07
6.65
4.95
4.95
16.34
6.44
5.69
5.45
7.45
7.45
24.59
9.69
8.57
8.20
4.95
2.80
4 •.00
4.00
13.20
5.20
4.60
4.40
6.50
6.50
21.45
8.45
7.48
7.15
3.25
4.00
Prices in
CUSTOMER PRICE LIST-COMPONENT PRODUCTS
F.O.B. Tucson, Arizona
Quantity discounts available.
u.s. dollars
MODEL
FOOT
1-24
2S-99
100-249
MODEL
HorE
OPA37HT
OPA404AO
OPA404AG
OPA404AL
OPA4048G
OPM048L'
OPA404KP
OPA404SG
OPM04SL
OPASOIAM
OPASOl8M
OPA50lRM
OPA501SM
OPA50lSMQ
OPA50lUM
OPASOIUM/8838
OPASOIVM
OPASOI VM/8838
OPA511AM
OPAS128M
OPAS12SM
OPA541AM
OPAS418M
OPA541SM
OPA6008M
OPA600CH
OPA600SH
OPA600TH
OPA600UM
OPA600UH/8838
OPA600VH
OPA600VH/8838
OPA605AH
OPA60SCH
OPA60SHG
OPA605KG
OPA606KO
OPA606KH
OPA606KP
OPA606LH
OPA606SH
OPA633AH
OPA633KP
OPA633SH
OPA8780UH
OPA8780UH/8838
+
16.74
17.45
22.12
22.2S
11.85
32.76
31. 75
59.81
70.56
76.72
91.84
125.44
86.00
94.75
96.00
100.00
45.00
55.46
8.59
13.50
15.00
17.01
18.25
9.25
25.11
25.75
43.20
51.68
53.19
64.64
93.96
75.75
83.40
84.50
88.00
44.10
6.25
9.40
11.45
13.49
15.35
6.95
20.95
22.45
34.13
39.74
44.63
52.45
75.60
68.10
74.85
76.00
79.00
~.~
~.~
63.~
".%
~.~
76.50
29.50
34.75
49.00
101.85
124.95
128.10
156.45
143.00
165.00
175.00
195.00
76.80
106.80
61.80
91.98
66.50
21.40
25.20
61. 50
16.85
19.85
B.~
~.~
85.05
106.05
106.05
141.75
115.00
145.00
153.00
176.00
61.00
83.45
50.40
75.00
3.78
4.70
3.10
10.75
lI.07
9.10
4.85
20.35
77.70
101.85
101.85
135.45
102.00
137.75
143.00
163.00
52.80
73.45
44.55
63.25
2.42
3.68
2.60
8.65
8.95
7.60
4.00
16.95
6.38
4.20
15.51
15.96
10.95
5.80
24.50
J
J, +
Effective June 1, 1987
1-24
2S-99
50.00
50.00
22.05
22.05
24.68
24.68
19.43
22.05
24.68
19.43
22.05
20.46
23.10
25.73
137.55
156.45
72.80
80.64
40.63
40.63
20.48
20.48
22.31
22.31
16.38
20.46
22.31
17.90
20.56
19.43
21.53
23.36
119.70
135.45
59.40
66.96
4.43
9.72
17.55
5.13
21. 55
43.15
50.49
43.15
50.49
37.00
52.00
42.00
41.00
29.00
33.00
37.00
42.00
51.00
46.00
69.00
79.00
66.00
50.00
59.00
27.70
36.00
100-249
HorE
67.09
+
rOOT
Page No. 13
OPA8780VM
OPA8780VH/8838
PCH53JG- I
PCH53JG-V
PCM53JP-I
PCM53JP-V
PCH53KP-I
PCH53KP-V
PCH54HP
PCM54JP
PCH54KP
PCH55HP
PCH55JP
PCH56P
PCH56P-J
PCH56P-K
PCH75JG
PCH75KG
PGAIOOAG
PGAI008G
PGAI02AO
PGAI02AG
PGAI02BG
PGAI02KP
PGAI02SG
PGA200AG
PGA200BG
PGA20IAG
PGA20lBG
PWR 70
PWR 71
PIIR 72
PWR 74
PWR IXX
PWR 2XX
PWR 3XX
PWR 4XX
PWR 5XX
PWR 6XX
PWR 7XX
PWR 8XX
PWRIOl7
PWR5038
PWR510X
PIIS 725
PWS 726
J, +
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
12.26
22.34
6.66
27.36
57.66
64.79
57.66
64.79
43.00
61.00
49.00
48.00
33.00
38.00
43.00
49.00
59.00
54.00
81.00
92.00
76.00
65.00
65.00
36.00
46.80
26.75
26.75
12.76
12.76
13.91
13.91
11.45
12.76
13.91
11.45
12.76
12.60
13.91
15.23
91.35
103.95
51.96
56.70
3.57
8.03
14:44
4.15
17.59
36.49
43;05
36.49
43.05
30.10
42.70
34.30
33.60
23.00
27.00
30.00
34.00
41.00
38.00
57.00
65.00
58.75
35.00
51.00
21. 30
27.70
Page No. 14
CUSTOMER PRICE LIST-COMPONENT PRODUCTS
F.O.B. Tucson, Arizona
Quantity discounts available.
Prices in U.S. dollars
HODEL
FOOT
NorE
REflOIJL
REfIOIJM
REFI0lKL
REFlOIKM
REFIOIRL
REflOIRM
REfIOIRMQ
REfIOISL
REFI0lSM
REflOISMQ
REFIOJL
REFIOJM
REFI0KL
REFIOKM
REFIORL
REFlOR~l
REFlORMQ
REFIOSL
REFIOSN
REFIOSMQ
RF-500-108
SOM853
SOf1854AG
SOM8548G
SOM856JG
SOM856KG
SOM857JG
SOM857KG
SOM862AH
SOM862AL
SOM862BH
SDM862BL
SDM862JH
SDM862JL
SDM862KH
SDM862KL
SDM862RH
SDM862RL
SOM862SH
SDM862SL
SDM863AH
SDM863AL
SDM863BH
SDM863BL
SDM863JH
SDM863JL
L.M
L.M
L.M
L.M
L.M
L.M
L.M
L.M
L.M
1-24
25-99
35.85
34.61
44.10
43.12
38.95
37.80
53.20
48.25
47.43
66.08
21. 30
19.49
26.10
24.47
24.05
22.34
31. 36
34.25
32.93
45.92
8.95
346.00
241.50
267.95
208.15
251.85
223.10
266.80
154.00
154.00
178.00
178.00
128.00
128.00
145.00
145.00
239.00
239.00
298.00
298.00
154.00
154.00
178.00
178.00
128.00
128.00
31. 70
30.02
39.25
37.80
34.75
33.16
46.44
43.40
42.07
58.32
18.95
16.90
23.15
21.22
21.35
19.39
27.00
30.15
28.46
39.42
8.25
333.00
193.20
215.05
166.75
201.25
178.25
213.90
129.00
129.00
146.00
146.00
117.00
117.00
129.00
129.00
204.00
204.00
255.00
255.00
129.00
129.00
148.00
148.00
117.00
117.00
100-249
25.65
23.63
32.15
30.24
28.45
26.46
36.75
35.85
34.02
48.30
16.25
14.02
19.75
17.59
18.30
16.12
22.94
25.70
23.63
33.44
7.65
319.00
162.15
179.40
139.15
.169.05
149.50
178.25
11 1.00
11 1. 00
127.00
127.00
103.00
103;00
118.00
118.00
189.00
189.00
235.00
235.00
111.00
111.00
127.00
127.00
103.00
103.00
HODH
SDM863KH
SDM863KL
SDM863RH
SOM863RL
SDM863SH
SDM863SL
SHC298Af1
SHC5320KH
SHC5320SH
SHC600BH
SHC76BM
SHC76KM
SHC803BM
SHC803BMQ
SHC803CM
SHC803CMQ
SHC804BM
SHC804BMQ
SHC804CM
SHC804CMQ
SHC80KP
SHC85
SHC85ET
SHC85ETQ
SHC85Q
SHM60
TM25-300HT
TM25-300NT
TM2500
TM27-12
TM2700
TM70
TM71
TM71-10
TM76
TM76K
TM77
TM77-I/O
TM77K
TM77K-IO
UAF11
UAF21
UAF41
VFCIOOAG
VFCI00AL
VFCIOOBG
FOOT
NorE
L.M
L.M
L.M
Effective June 1, 1987
1-24
25-99
100-249
145.00
145.00
239.00
239.00
298.00
298.00
8.35
13.40
61.00
129.00
129.00
204.00
204.00
255.00
255.00
5.78
11.60
52.75
304.50
75.00
65.10
141.75
177.45
160.65
201.60
127.05
158.55
138.60
174.30
43.05
78.20
126.50
186.30
126.50
1«.00
267.00
267.00
290.00
267.00
315.00
496.00
582.00
658.00
496.00
587.00
562.00
658.00
671.00
746.00
45.60
88.10
15.23
8.70
11.20
13.65
118.00
)18.00
189.00
189.00
235.00
235.00
4.73
9.80
44.70
280.35
63.00
54.60
129.15
160.65
147.00
182.70
115.50
143.85
127.05
. 158.55
35.70
65.55
121.90
178.25
105.80
138;00
226.00
226:00
195.00
226.00
210.00
402.00
456.00
533.00
402.00
476.00
456.00
533.00
543.00
604.00
29.05
58.69
12.08
6.95
9.45
10.95
D
99.00
85.05
182.70
234.15
212.10
265.65
168.00
207.90
183.75
229.95
64.05
112.70
170.20
215.25
180.55
I~.OO
320.00
320.00
325.00
320.00
350.00
595.00
675.00
790.00
595.00
705.00
675.00
790.00
805.00
895.00
64.35
102.60
23.35
10.45
12.95
16.40
CUSTOMER PRICE LIST-COMPONENT PRODUCTS
F.O.B. Tucson, Arizona
Quantity discounts available.
Prices in u.s. dollars
HODEL
FOOT
1-24
25-99
100-249
HODEL
HorE
VFCI00BL
VFCI00SG
VFCI00SL
VFC320BG
VFC320BL
VFC320BL-BS
VFC320BL-BSSI
VFC320BL-BSS2
VFC320BL-BSS3
VFC320BL-BSS4
VFC320BM
VFC320BH-BS
VFC3209H-BSSI
V~C32IitlM-tlSS2
VFC320BM-BSS3
VFC320BM-BSS4
VFC320CG
VFC320CL
VFC320CL-BS
VFC320CL-BSSI
VFC320CL-BSS2
VFC320CL-BSS3
VFC320CL-BSS4
VFC320CM
VFC320CM-BS
VFC320CM-BSSI
VFC320CM-BSS2
VFC320CM-BSS3
VFC320CM-BSS4
VFC320SL
VFC320SL-BS
VFC320SL-BSSI
VFC320SL-BSS2
VFC320SL-BSS3
VFC320SL-BSS4
VFC320SM
VFC320SM-BS
VFC320SM-BSSI
VFC320SM- BSS2
VFC320SM- BSS3
VFC320SM-BSS4
VFC32BD
VFC32BL
VFC32BL-BS
VFC32BL-BSSI
VFC32BL-BSS2
18.90
18.95
21.45
15.95
19.65
19.65
64.85
25.25
22.60
21.62
15.60
15.60
56.59
2u.28
17.94
17.76
20.72
20.75
20.75
68.48
26.98
23.86
22.83
18.59
18.59
60.23
24.17
21.38
20.45
25.20
25.20
83.16
32.76
28.98
27.72
23.13
23.13
74.91
30.07
26.60
25.44
15.65
15.65
51.65
20.35
16.15
15.95
18.45
11.75
14.45
14.45
47.69
18.79
16.62
15.90
11.40
11.40
39.44
14.82
13.11
12.55
14.74
15.50
15.50
51.15
20 ..15
17.83
17.05
13.45
13.45
42.90
17.49
15.47
14.80
18.90
18.90
62.37
24.57
21.73
20.79
16.85
16.85
54.12
21.91
19.38
18.54
8.45
12.95
12.95
42.73
16.84
13.45
13.65
16.15
8.95
11.50
11. 50
37.95
.14.95
13.23
12.65
8.75
8.75
29.70
1l.38
10.06
9.63
12.08
13.25
13.25
43.73
17.23
15.24
14.58
- 10.97
10.97
35.48
14.26
12.62
12.07
16.30
16.30
53.79
21.19
18.75
17.93
14.07
14.07
45.54
18.29
16.18
15:48
5.55
10.45
10.45
34.49
13.59
VFC32Bl-8SS3
VFC32Bl-BSS4
VFC32BM
VFC32BM-BS
VFC32BM-BSSI
VFC32BM-BSS2
VFC32BM-BSS3
VFC32BM-BSS4
VFC32BMQ
VFC32KP
VFC32Sl
VFC32Sl-BS
VFC32Sl-BSSI
VFCJZSL-oSS2
VFC32SL-BSS3
VFC32Sl-BSS4
VFC32SM
VFC32SM-BS
VFC32SM-BSSI
VFC32SM-BSS2
VFC32SM-BSS3
VFC32SM-BSS4
VFC32SMQ
VFC32UM
VFC32UM/883B
VFC32VM
VFC32VM/8838
VFC32I1M
VFC32I1M/883B
VFC42BM
VFC42BP
VFC42SM
VFC52BM
VFC52BP
VFC52SH
VFC62BG
VFC62Bl
VFC62Bl-BS
VFC62BL-BSSI
VFC62BL-BSS2
VFC62Bl-BSS3
VFC62BL-BSS4
VFC62BH
VFC62BH-BS
VFC62BM-BSSI
VFC62BM-BSS2
roOT
NOTE
1-24
18.00
17.22
11.95
11.95
43.40
15.54
13.75
13.15
IB.87
8.95
21.45
21.45
70.79
27.89
24.67
23.60
18.30
18.30
62.54
23.79
21.05
20.13
24.70
15.00
20.00
24.00
36.00
30.00
34.00
33.21
23.91
40.32
33.21
23.91
40.32
17.86
1~.65
19.65
64.85
25.55
22.60
21.62
17.47
17.47
56.59
22.71
Page No.15
Effective June 1, 1987
25-99
14.89
14.25
9.95
9.95
34.48
12.94
I!. 44
10.95
15.07
7.45
17.65
17.65
58.25
22.95
20.30
19.42
14.98
14.98
50.00
19.47
17.23
16.48
20.25
11.00
16.00
19.50
28.75
24.00
27.50
27.16
18.74
32.40
27.00
18.74
32.40
12.69
14.45
14.45
47.69
18.79
16.62
15.90
12.31
12.31
39.44
16.00
100-249
12.02
11.50
7.95
7.95
26.24
10.34
9.14
8.75
12.55
5.95
14.35
14.35
47.36
io.o6
16.50
15.79
11.85
11.85
39.11
15.41
13.63
13.04
16.00
10.45
15.20
18.50
27.25
22.75
26.00
23.05
16.49
25.88
23.05
16.49
25.88
9.40
11.50
11.50
37.95
14.95
13.23
12.65
9.19
9.19
29.}0
11.95
CUSTOMER PRICE LIST-COMPONENT PRODUCTS
Page No. 16
Prices in
u.s. dollars
MODEL
VfC628M-8SS3
VfC628H-8SS4
VFC62CG
vrC62CL
VFC62CL-BS
VFC62CL-BSSI
VFC62CL-BSS2
VFC62CL-BSS3
VFC62CL-BSS4
VFC62CH
VFC62CH-BS
VFC62CH-8SS1
VfC62CH-BSS2
vrC62CH-BSS3
VFC62CH-BSS4
VFC62SL
VFC62SL-BS
VFC62SL-BSSI
VFC62SL-BSS2
vrC62SL-BSS3
VFC62SL-BSS4
VFC62SH
VFC62SM-BS
vrC62SM-BSSI
F.O.B. Tucson, Arizona
FOOT
NOTE
1-24
25-99
20.09
19.22
22.20
20.75
20.75
68.48
26.9B
23.86
22.83
19.95
19.95
60.23
25.94
22.94
21.95
25.20
25.20
83.16
32.76
28.98
27.72
24.80
24.80
74.91
14.16
13.54
15.30
15.50
15.50
51.15
20.15
17 .83
17 .05
13.95
13.95
42.90
18.14
16.04
15.35
18.90
18.90
62.37
24.57
21. 73
20.79
17 .50
17.50
54.12
100-249
10.57
10.11
12.65
13.25
13.25
43.73
17.23
15.24
14.58
11.45
11.45
35.48
14.89
13.17
12.60
16.30
16.30
53.79'
21.19
18.75
17 .93
14.75
14.75
45.54
Quantity discounts available.
MODEL
VfC62SH-8SS2
VFC62SM-8SS3
VFC62SH-8SS4
XTRI00AM
XTRI00AP
XTRI00BH
XTRI00BP
XTRI0IAD
XTRI0IAG
XTRI0IAL
XTRI01AP
XTRI0IAU
XTRI0IBG
XTRI0IBL
XTRIOlSL
XTRllOAD
XTRllOAG
XTRllOAL
XTRllOBG
XTRllOBL
XTRllOKP
XTRllOKU
XTR110SL
rOOT
NOTE
Effective June 1, 1987
1-24
32.24
28.52
27 .28
42.56
33.60
51.52
40.32
11. 75
14.25
8.50
8.95
17.35
19.85
25.05
10.B5
14.25
16.25
20.05
7.45
8.40
25.30
25-99
22.75
20.13
19.25
38.50
30.02
46.B2
36.67
7.30
9.75
12.25
7.05
7.40
14.45
16.95
21. 30
'7.45
8.75
11.65
13.10
16.15
5.95
6.55
20.25
A) Not necessarily pin 'or spec compatible.
B) Expected date of last order 6/30/88.
C) AOC600K pricing: 1-4 $1995; 5-9 $1895; 10-24 $1795; AOC600B; 1-4 $2790; 5-9 $2650; 10-24 $2510.
0) SHC600BH pricing: 1-4 $329; 5-9 $321; 10-24 $314.
E) 25 piece minimum.
F) Minimum order is 10 pieces.
G) Connector supplied with each un~.
H) These products slated to be discontinued June 30, 1987.
I) Prices effective upon introduction.
J) Consult factory.
K) /G level I screening add 25% to pricing above; IT level II screening add
45% to pricing indicated above.
L) Eurocard evah,Jation PCB part #PC862/863-1 $16.00 each.
M) 68 pin LCC socket (Note N) part #MC0068-1 $14.00.
N) Manufacturer and part # for this socket is "Robinson Nugent" part #ICC503 68-2-G (It is a U.S. part).
0) AOC80KO must be ordered in multiples of 36.
tQualification reports $100 each.
Prices subject to change w~hout notice. Minimum order $75.
©1987 Burr-Brown Corp.
MKT-173B
Printed in U.S.A. June, 1987
100-249
19.18
16.96
16.23
30.40
25.04
37.75
30.71
5.50
8.25
10.75
5.95
6.25
12.25
14.75
18.45
4.95
7.45
10.15
H.IO
13.95
4.95
5.40
17.40
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2017:07:13 19:24:52-08:00 Modify Date : 2017:07:13 20:11:14-07:00 Metadata Date : 2017:07:13 20:11:14-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:264ea7a8-27aa-a14a-a761-5a40c95890f2 Instance ID : uuid:cad47720-cd39-2f46-8d27-664798d326f1 Page Layout : SinglePage Page Mode : UseNone Page Count : 307EXIF Metadata provided by EXIF.tools